From 5a413dfbaf3f446a154d65d1d9811a6d311482a5 Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Fri, 2 Jan 2015 21:55:02 +0100 Subject: drm/armada: armada_output: Remove some unused functions Removes some functions that are not used anywhere: armada_drm_encoder_mode_fixup() armada_drm_encoder_commit() armada_drm_encoder_prepare() This was partially found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_output.c | 16 ---------------- drivers/gpu/drm/armada/armada_output.h | 6 ------ 2 files changed, 22 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/armada/armada_output.c b/drivers/gpu/drm/armada/armada_output.c index abbc309fe539..5a9823178291 100644 --- a/drivers/gpu/drm/armada/armada_output.c +++ b/drivers/gpu/drm/armada/armada_output.c @@ -72,22 +72,6 @@ static const struct drm_connector_funcs armada_drm_conn_funcs = { .set_property = armada_drm_connector_set_property, }; -void armada_drm_encoder_prepare(struct drm_encoder *encoder) -{ - encoder_helper_funcs(encoder)->dpms(encoder, DRM_MODE_DPMS_OFF); -} - -void armada_drm_encoder_commit(struct drm_encoder *encoder) -{ - encoder_helper_funcs(encoder)->dpms(encoder, DRM_MODE_DPMS_ON); -} - -bool armada_drm_encoder_mode_fixup(struct drm_encoder *encoder, - const struct drm_display_mode *mode, struct drm_display_mode *adjusted) -{ - return true; -} - /* Shouldn't this be a generic helper function? */ int armada_drm_slave_encoder_mode_valid(struct drm_connector *conn, struct drm_display_mode *mode) diff --git a/drivers/gpu/drm/armada/armada_output.h b/drivers/gpu/drm/armada/armada_output.h index 4126d43b5057..d3a6ce79d094 100644 --- a/drivers/gpu/drm/armada/armada_output.h +++ b/drivers/gpu/drm/armada/armada_output.h @@ -21,12 +21,6 @@ struct armada_output_type { struct drm_encoder *armada_drm_connector_encoder(struct drm_connector *conn); -void armada_drm_encoder_prepare(struct drm_encoder *encoder); -void armada_drm_encoder_commit(struct drm_encoder *encoder); - -bool armada_drm_encoder_mode_fixup(struct drm_encoder *encoder, - const struct drm_display_mode *mode, struct drm_display_mode *adj); - int armada_drm_slave_encoder_mode_valid(struct drm_connector *conn, struct drm_display_mode *mode); -- cgit v1.2.3 From 38bf3aee3ec7b5b264b701da14114a618cddd1a1 Mon Sep 17 00:00:00 2001 From: Rickard Strandqvist Date: Fri, 2 Jan 2015 22:04:25 +0100 Subject: drm/armada: armada_drv: Remove unused function Remove the function armada_drm_vbl_event_remove_unlocked() that is not used anywhere. This was partially found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist Signed-off-by: Russell King --- drivers/gpu/drm/armada/armada_drm.h | 2 -- drivers/gpu/drm/armada/armada_drv.c | 10 ---------- 2 files changed, 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/armada/armada_drm.h b/drivers/gpu/drm/armada/armada_drm.h index ea63c6c7c66f..5f6aef0dca59 100644 --- a/drivers/gpu/drm/armada/armada_drm.h +++ b/drivers/gpu/drm/armada/armada_drm.h @@ -46,8 +46,6 @@ void armada_drm_vbl_event_add(struct armada_crtc *, struct armada_vbl_event *); void armada_drm_vbl_event_remove(struct armada_crtc *, struct armada_vbl_event *); -void armada_drm_vbl_event_remove_unlocked(struct armada_crtc *, - struct armada_vbl_event *); #define armada_drm_vbl_event_init(_e, _f, _d) do { \ struct armada_vbl_event *__e = _e; \ INIT_LIST_HEAD(&__e->node); \ diff --git a/drivers/gpu/drm/armada/armada_drv.c b/drivers/gpu/drm/armada/armada_drv.c index f672e6ad8afa..7c00a9099779 100644 --- a/drivers/gpu/drm/armada/armada_drv.c +++ b/drivers/gpu/drm/armada/armada_drv.c @@ -252,16 +252,6 @@ void armada_drm_vbl_event_remove(struct armada_crtc *dcrtc, } } -void armada_drm_vbl_event_remove_unlocked(struct armada_crtc *dcrtc, - struct armada_vbl_event *evt) -{ - unsigned long flags; - - spin_lock_irqsave(&dcrtc->irq_lock, flags); - armada_drm_vbl_event_remove(dcrtc, evt); - spin_unlock_irqrestore(&dcrtc->irq_lock, flags); -} - /* These are called under the vbl_lock. */ static int armada_drm_enable_vblank(struct drm_device *dev, int crtc) { -- cgit v1.2.3 From 6d293983d4d2d1c233fff94f7b2c4603bdab0170 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Mon, 30 Mar 2015 08:33:12 +0300 Subject: drm/i915: Check lane sharing between pipes B & C using atomic state Makes that code atomic ready. v2: Acquire crtc_state for the "other" pipe only when needed. (Daniel) v3: Really only acquire the other state if necessary. (Daniel) Signed-off-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 69 ++++++++++++++++++++++-------------- 1 file changed, 42 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 75955fee6d24..cfe34c316d77 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5667,65 +5667,80 @@ bool intel_connector_get_hw_state(struct intel_connector *connector) return encoder->get_hw_state(encoder, &pipe); } -static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe) +static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = - to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); - - if (crtc->base.state->enable && - crtc->config->has_pch_encoder) - return crtc->config->fdi_lanes; + if (crtc_state->base.enable && crtc_state->has_pch_encoder) + return crtc_state->fdi_lanes; return 0; } -static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, +static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, struct intel_crtc_state *pipe_config) { + struct drm_atomic_state *state = pipe_config->base.state; + struct intel_crtc *other_crtc; + struct intel_crtc_state *other_crtc_state; + DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", pipe_name(pipe), pipe_config->fdi_lanes); if (pipe_config->fdi_lanes > 4) { DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", pipe_name(pipe), pipe_config->fdi_lanes); - return false; + return -EINVAL; } if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { if (pipe_config->fdi_lanes > 2) { DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", pipe_config->fdi_lanes); - return false; + return -EINVAL; } else { - return true; + return 0; } } if (INTEL_INFO(dev)->num_pipes == 2) - return true; + return 0; /* Ivybridge 3 pipe is really complicated */ switch (pipe) { case PIPE_A: - return true; + return 0; case PIPE_B: - if (pipe_config->fdi_lanes > 2 && - pipe_required_fdi_lanes(dev, PIPE_C) > 0) { + if (pipe_config->fdi_lanes <= 2) + return 0; + + other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); + other_crtc_state = + intel_atomic_get_crtc_state(state, other_crtc); + if (IS_ERR(other_crtc_state)) + return PTR_ERR(other_crtc_state); + + if (pipe_required_fdi_lanes(other_crtc_state) > 0) { DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", pipe_name(pipe), pipe_config->fdi_lanes); - return false; + return -EINVAL; } - return true; + return 0; case PIPE_C: if (pipe_config->fdi_lanes > 2) { DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", pipe_name(pipe), pipe_config->fdi_lanes); - return false; + return -EINVAL; } - if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) { + + other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); + other_crtc_state = + intel_atomic_get_crtc_state(state, other_crtc); + if (IS_ERR(other_crtc_state)) + return PTR_ERR(other_crtc_state); + + if (pipe_required_fdi_lanes(other_crtc_state) > 2) { DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); - return false; + return -EINVAL; } - return true; + return 0; default: BUG(); } @@ -5737,8 +5752,8 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, { struct drm_device *dev = intel_crtc->base.dev; struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; - int lane, link_bw, fdi_dotclock; - bool setup_ok, needs_recompute = false; + int lane, link_bw, fdi_dotclock, ret; + bool needs_recompute = false; retry: /* FDI is a binary signal running at ~2.7GHz, encoding @@ -5760,9 +5775,9 @@ retry: intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, link_bw, &pipe_config->fdi_m_n); - setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, - intel_crtc->pipe, pipe_config); - if (!setup_ok && pipe_config->pipe_bpp > 6*3) { + ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, + intel_crtc->pipe, pipe_config); + if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { pipe_config->pipe_bpp -= 2*3; DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", pipe_config->pipe_bpp); @@ -5775,7 +5790,7 @@ retry: if (needs_recompute) return RETRY; - return setup_ok ? 0 : -EINVAL; + return ret; } static void hsw_compute_ips_config(struct intel_crtc *crtc, -- cgit v1.2.3 From 41037f9f0e299f72e062cb508371906810fcedde Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 27 Mar 2015 11:01:36 +0000 Subject: drm/i915: Add i915_gem_request_unreference__unlocked We were missing a convenience stub to aquire the right mutex whilst dropping the request, so add it. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 13 +++++++++++++ drivers/gpu/drm/i915/i915_gem.c | 8 ++------ 2 files changed, 15 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e326ac9730cf..4ef320c17b63 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2142,6 +2142,19 @@ i915_gem_request_unreference(struct drm_i915_gem_request *req) kref_put(&req->ref, i915_gem_request_free); } +static inline void +i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) +{ + if (req && !atomic_add_unless(&req->ref.refcount, -1, 1)) { + struct drm_device *dev = req->ring->dev; + + mutex_lock(&dev->struct_mutex); + if (likely(atomic_dec_and_test(&req->ref.refcount))) + i915_gem_request_free(&req->ref); + mutex_unlock(&dev->struct_mutex); + } +} + static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, struct drm_i915_gem_request *src) { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index d07c0b1fb498..3a9136584833 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2866,9 +2866,7 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) ret = __i915_wait_request(req, reset_counter, true, args->timeout_ns > 0 ? &args->timeout_ns : NULL, file->driver_priv); - mutex_lock(&dev->struct_mutex); - i915_gem_request_unreference(req); - mutex_unlock(&dev->struct_mutex); + i915_gem_request_unreference__unlocked(req); return ret; out: @@ -4071,9 +4069,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) if (ret == 0) queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); - mutex_lock(&dev->struct_mutex); - i915_gem_request_unreference(target); - mutex_unlock(&dev->struct_mutex); + i915_gem_request_unreference__unlocked(target); return ret; } -- cgit v1.2.3 From b728d7265bfaf125604c48a54d2932add7aebf31 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Sat, 28 Mar 2015 10:57:46 +0100 Subject: Enabled dithering in the intel VCH DVO for 18bpp pipelines. Signed-off-by: Thomas Richter Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/dvo_ivch.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/dvo_ivch.c b/drivers/gpu/drm/i915/dvo_ivch.c index 0f2587ff347c..89b08a896d20 100644 --- a/drivers/gpu/drm/i915/dvo_ivch.c +++ b/drivers/gpu/drm/i915/dvo_ivch.c @@ -23,6 +23,9 @@ * Authors: * Eric Anholt * + * Minor modifications (Dithering enable): + * Thomas Richter + * */ #include "dvo.h" @@ -59,6 +62,8 @@ # define VR01_DVO_BYPASS_ENABLE (1 << 1) /** Enables the DVO clock */ # define VR01_DVO_ENABLE (1 << 0) +/** Enable dithering for 18bpp panels. Not documented. */ +# define VR01_DITHER_ENABLE (1 << 4) /* * LCD Interface Format @@ -74,6 +79,8 @@ # define VR10_INTERFACE_2X18 (2 << 2) /** Enables 2x24-bit LVDS output */ # define VR10_INTERFACE_2X24 (3 << 2) +/** Mask that defines the depth of the pipeline */ +# define VR10_INTERFACE_DEPTH_MASK (3 << 2) /* * VR20 LCD Horizontal Display Size @@ -342,9 +349,15 @@ static void ivch_mode_set(struct intel_dvo_device *dvo, struct drm_display_mode *adjusted_mode) { uint16_t vr40 = 0; - uint16_t vr01; + uint16_t vr01 = 0; + uint16_t vr10; + + ivch_read(dvo, VR10, &vr10); + /* Enable dithering for 18 bpp pipelines */ + vr10 &= VR10_INTERFACE_DEPTH_MASK; + if (vr10 == VR10_INTERFACE_2X18 || vr10 == VR10_INTERFACE_1X18) + vr01 = VR01_DITHER_ENABLE; - vr01 = 0; vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE | VR40_HORIZONTAL_INTERP_ENABLE); @@ -353,7 +366,7 @@ static void ivch_mode_set(struct intel_dvo_device *dvo, uint16_t x_ratio, y_ratio; vr01 |= VR01_PANEL_FIT_ENABLE; - vr40 |= VR40_CLOCK_GATING_ENABLE; + vr40 |= VR40_CLOCK_GATING_ENABLE | VR40_ENHANCED_PANEL_FITTING; x_ratio = (((mode->hdisplay - 1) << 16) / (adjusted_mode->hdisplay - 1)) >> 2; y_ratio = (((mode->vdisplay - 1) << 16) / @@ -380,6 +393,8 @@ static void ivch_dump_regs(struct intel_dvo_device *dvo) DRM_DEBUG_KMS("VR00: 0x%04x\n", val); ivch_read(dvo, VR01, &val); DRM_DEBUG_KMS("VR01: 0x%04x\n", val); + ivch_read(dvo, VR10, &val); + DRM_DEBUG_KMS("VR10: 0x%04x\n", val); ivch_read(dvo, VR30, &val); DRM_DEBUG_KMS("VR30: 0x%04x\n", val); ivch_read(dvo, VR40, &val); -- cgit v1.2.3 From 670b90d20a5d71a2f430e0c4b97dac2d17a659b5 Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Fri, 27 Mar 2015 17:21:32 +0530 Subject: drm/i915: PSR: Keep sink state consistent with source BSpec recommends to keep the main link state consistent between the source and the sink. As per that, update the main link state in sink DPCD register to 'active', for Valleyview based platforms. Signed-off-by: Durgadoss R Reviewed-by: Rodrigo Vivi Tested-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index a8f9348259ae..9668735fce52 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -133,7 +133,7 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp) static void vlv_psr_enable_sink(struct intel_dp *intel_dp) { drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, - DP_PSR_ENABLE); + DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); } static void hsw_psr_enable_sink(struct intel_dp *intel_dp) -- cgit v1.2.3 From 8c7a075da9f7980cc95ffcd7e6621d4a87f20f40 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 30 Mar 2015 16:20:44 +0100 Subject: drm/i2c: tda998x: use drm_hdmi_avi_infoframe_from_display_mode() Make use of the DRM HDMI AVI infoframe helper to construct the AVI infoframe, rather than coding this up ourselves. This allows DRM to supply proper aspect ratio information derived from the DRM display mode structure. Signed-off-by: Russell King --- drivers/gpu/drm/i2c/tda998x_drv.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c index 43d5d91fe880..fbc9c1facdfe 100644 --- a/drivers/gpu/drm/i2c/tda998x_drv.c +++ b/drivers/gpu/drm/i2c/tda998x_drv.c @@ -610,19 +610,21 @@ tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p) static void tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode) { - u8 buf[PB(HDMI_AVI_INFOFRAME_SIZE) + 1]; + struct hdmi_avi_infoframe frame; + u8 buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; + ssize_t len; - memset(buf, 0, sizeof(buf)); - buf[HB(0)] = HDMI_INFOFRAME_TYPE_AVI; - buf[HB(1)] = 0x02; - buf[HB(2)] = HDMI_AVI_INFOFRAME_SIZE; - buf[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN; - buf[PB(2)] = HDMI_ACTIVE_ASPECT_PICTURE; - buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2; - buf[PB(4)] = drm_match_cea_mode(mode); - - tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, - sizeof(buf)); + drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); + + frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; + + len = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf)); + if (len < 0) { + dev_err(&priv->hdmi->dev, "hdmi_avi_infoframe_pack() failed: %d\n", len); + return; + } + + tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, len); } static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) -- cgit v1.2.3 From 85250ddff7a603dfe0ec0503a9e6395f79424f61 Mon Sep 17 00:00:00 2001 From: Deepak S Date: Sat, 28 Mar 2015 15:23:34 +0530 Subject: drm/i915/chv: Remove Wait for a previous gfx force-off MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On CHV, PUNIT team confirmed that 'VLV_GFX_CLK_STATUS_BIT' is not a sticky bit and it will always be set. So ignore Check for previous Gfx force off during suspend and allow the force clk as part S0ix Sequence Signed-off-by: Deepak S Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 82f8be4b6745..182d6a742778 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1194,11 +1194,13 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) int err; val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); - WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on); #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) /* Wait for a previous force-off to settle */ - if (force_on) { + if (force_on && !IS_CHERRYVIEW(dev_priv->dev)) { + /* WARN_ON only for the Valleyview */ + WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on); + err = wait_for(!COND, 20); if (err) { DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n", -- cgit v1.2.3 From 77589f561bce75e6799e2bc05551486bbef3954a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 31 Mar 2015 10:37:22 +0300 Subject: drm/i915: Convert BUGs to WARNs in the video overlay code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BUG is bad, just use WARN. Also drop one BUG(!overlay) since we'd oops anyway when dereferencing it. Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_overlay.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index dd92122ed95c..730ee46563c8 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -216,7 +216,7 @@ static int intel_overlay_do_wait_request(struct intel_overlay *overlay, struct intel_engine_cs *ring = &dev_priv->ring[RCS]; int ret; - BUG_ON(overlay->last_flip_req); + WARN_ON(overlay->last_flip_req); i915_gem_request_assign(&overlay->last_flip_req, ring->outstanding_lazy_request); ret = i915_add_request(ring); @@ -241,7 +241,7 @@ static int intel_overlay_on(struct intel_overlay *overlay) struct intel_engine_cs *ring = &dev_priv->ring[RCS]; int ret; - BUG_ON(overlay->active); + WARN_ON(overlay->active); overlay->active = 1; WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE)); @@ -270,7 +270,7 @@ static int intel_overlay_continue(struct intel_overlay *overlay, u32 tmp; int ret; - BUG_ON(!overlay->active); + WARN_ON(!overlay->active); if (load_polyphase_filter) flip_addr |= OFC_UPDATE; @@ -309,7 +309,8 @@ static void intel_overlay_off_tail(struct intel_overlay *overlay) struct drm_i915_gem_object *obj = overlay->vid_bo; /* never have the overlay hw on without showing a frame */ - BUG_ON(!overlay->vid_bo); + if (WARN_ON(!obj)) + return; i915_gem_object_ggtt_unpin(obj); drm_gem_object_unreference(&obj->base); @@ -329,7 +330,7 @@ static int intel_overlay_off(struct intel_overlay *overlay) u32 flip_addr = overlay->flip_addr; int ret; - BUG_ON(!overlay->active); + WARN_ON(!overlay->active); /* According to intel docs the overlay hw may hang (when switching * off) without loading the filter coeffs. It is however unclear whether @@ -712,9 +713,8 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, u32 swidth, swidthsw, sheight, ostride; enum pipe pipe = overlay->crtc->pipe; - BUG_ON(!mutex_is_locked(&dev->struct_mutex)); - BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); - BUG_ON(!overlay); + WARN_ON(!mutex_is_locked(&dev->struct_mutex)); + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); ret = intel_overlay_release_old_vid(overlay); if (ret != 0) @@ -824,8 +824,8 @@ int intel_overlay_switch_off(struct intel_overlay *overlay) struct drm_device *dev = overlay->dev; int ret; - BUG_ON(!mutex_is_locked(&dev->struct_mutex)); - BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); + WARN_ON(!mutex_is_locked(&dev->struct_mutex)); + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); ret = intel_overlay_recover_from_interrupt(overlay); if (ret != 0) @@ -1432,7 +1432,7 @@ void intel_cleanup_overlay(struct drm_device *dev) /* The bo's should be free'd by the generic code already. * Furthermore modesetting teardown happens beforehand so the * hardware should be off already */ - BUG_ON(dev_priv->overlay->active); + WARN_ON(dev_priv->overlay->active); drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base); kfree(dev_priv->overlay); -- cgit v1.2.3 From 209c2a5ec1c9b59f1f43ecd882a2b04d8a6b65de Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 31 Mar 2015 10:37:23 +0300 Subject: drm/i915: Convert overlay->{active, pfit_active} to bools MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit overlay.{active,pfit_active} are just on/off flags, so make them bool. Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_overlay.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 730ee46563c8..fd9ded771d01 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -172,8 +172,8 @@ struct intel_overlay { struct intel_crtc *crtc; struct drm_i915_gem_object *vid_bo; struct drm_i915_gem_object *old_vid_bo; - int active; - int pfit_active; + bool active; + bool pfit_active; u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ u32 color_key; u32 brightness, contrast, saturation; @@ -242,7 +242,7 @@ static int intel_overlay_on(struct intel_overlay *overlay) int ret; WARN_ON(overlay->active); - overlay->active = 1; + overlay->active = true; WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE)); @@ -318,7 +318,7 @@ static void intel_overlay_off_tail(struct intel_overlay *overlay) overlay->crtc->overlay = NULL; overlay->crtc = NULL; - overlay->active = 0; + overlay->active = false; } /* overlay needs to be disabled in OCMD reg */ @@ -1131,10 +1131,10 @@ int intel_overlay_put_image(struct drm_device *dev, void *data, /* line too wide, i.e. one-line-mode */ if (mode->hdisplay > 1024 && intel_panel_fitter_pipe(dev) == crtc->pipe) { - overlay->pfit_active = 1; + overlay->pfit_active = true; update_pfit_vscale_ratio(overlay); } else - overlay->pfit_active = 0; + overlay->pfit_active = false; } ret = check_overlay_dst(overlay, put_image_rec); -- cgit v1.2.3 From 1c7c4301eeeff9af7e5009785aa721b0da6c9198 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 31 Mar 2015 10:37:24 +0300 Subject: drm/i915: Mark the overlay active only if we got ring space MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After the GPU has wedged we can't turn on the overlay anymore. Only mark it as active if we succeed in allocating ring space. This prevents a WARN (previous;y a BUG) during driver unload if we attempted to use the overlay after the GPU had already wedged. Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_overlay.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index fd9ded771d01..b291f1301c93 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -242,14 +242,14 @@ static int intel_overlay_on(struct intel_overlay *overlay) int ret; WARN_ON(overlay->active); - overlay->active = true; - WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE)); ret = intel_ring_begin(ring, 4); if (ret) return ret; + overlay->active = true; + intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON); intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE); intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); -- cgit v1.2.3 From 46509475a817ed099829be2a8d03cdbc355a284e Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 31 Mar 2015 10:37:21 +0300 Subject: drm/i915: Enable DVO 2x clock around DVO encoder init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ns2501 requires the DVO 2x clock before it will respond to i2c access, so make sure the clock is enabled when we try to initialize the encoder. Fixes the display getting lost on module reload on my Fujitsu/Siemens Lifebook S6010. Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dvo.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index 4ccd6c3f133d..f2ed122615ae 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -495,6 +495,8 @@ void intel_dvo_init(struct drm_device *dev) struct i2c_adapter *i2c; int gpio; bool dvoinit; + enum pipe pipe; + uint32_t dpll[2]; /* Allow the I2C driver info to specify the GPIO to be used in * special cases, but otherwise default to what's defined @@ -520,8 +522,23 @@ void intel_dvo_init(struct drm_device *dev) */ intel_gmbus_force_bit(i2c, true); + /* ns2501 requires the DVO 2x clock before it will + * respond to i2c accesses, so make sure we have + * have the clock enabled before we attempt to + * initialize the device. + */ + for_each_pipe(dev_priv, pipe) { + dpll[pipe] = I915_READ(DPLL(pipe)); + I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); + } + dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); + /* restore the DVO 2x clock state to original */ + for_each_pipe(dev_priv, pipe) { + I915_WRITE(DPLL(pipe), dpll[pipe]); + } + intel_gmbus_force_bit(i2c, false); if (!dvoinit) -- cgit v1.2.3 From e907f1704c402122b0c0a206d8064e19b79ed1c3 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 31 Mar 2015 14:09:47 +0300 Subject: drm/i915: Return more precise cdclk for gen2/3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fill out the lower three digits for gen2 and gen3 cdclk frqeuncy. It's not clear if these are accurate frquencies or just in the ballpark, but without docs this is the best we can do. Signed-off-by: Ville Syrjälä Signed-off-by: Mika Kahola Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cfe34c316d77..2ce097fa4418 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5893,7 +5893,7 @@ static int i945_get_display_clock_speed(struct drm_device *dev) static int i915_get_display_clock_speed(struct drm_device *dev) { - return 333000; + return 333333; } static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) @@ -5909,19 +5909,19 @@ static int pnv_get_display_clock_speed(struct drm_device *dev) switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { case GC_DISPLAY_CLOCK_267_MHZ_PNV: - return 267000; + return 266667; case GC_DISPLAY_CLOCK_333_MHZ_PNV: - return 333000; + return 333333; case GC_DISPLAY_CLOCK_444_MHZ_PNV: - return 444000; + return 444444; case GC_DISPLAY_CLOCK_200_MHZ_PNV: return 200000; default: DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); case GC_DISPLAY_CLOCK_133_MHZ_PNV: - return 133000; + return 133333; case GC_DISPLAY_CLOCK_167_MHZ_PNV: - return 167000; + return 166667; } } @@ -5932,11 +5932,11 @@ static int i915gm_get_display_clock_speed(struct drm_device *dev) pci_read_config_word(dev->pdev, GCFGC, &gcfgc); if (gcfgc & GC_LOW_FREQUENCY_ENABLE) - return 133000; + return 133333; else { switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { case GC_DISPLAY_CLOCK_333_MHZ: - return 333000; + return 333333; default: case GC_DISPLAY_CLOCK_190_200_MHZ: return 190000; @@ -5946,7 +5946,7 @@ static int i915gm_get_display_clock_speed(struct drm_device *dev) static int i865_get_display_clock_speed(struct drm_device *dev) { - return 266000; + return 266667; } static int i855_get_display_clock_speed(struct drm_device *dev) @@ -5962,7 +5962,7 @@ static int i855_get_display_clock_speed(struct drm_device *dev) case GC_CLOCK_166_250: return 250000; case GC_CLOCK_100_133: - return 133000; + return 133333; } /* Shouldn't happen */ @@ -5971,7 +5971,7 @@ static int i855_get_display_clock_speed(struct drm_device *dev) static int i830_get_display_clock_speed(struct drm_device *dev) { - return 133000; + return 133333; } static void -- cgit v1.2.3 From b37a6434cfa9477e6e5cb386e7e3d135073aef63 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 31 Mar 2015 14:11:54 +0300 Subject: drm/i915: ILK cdclk seems to be 450MHz MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on the BIOS DP A AUX 2x clock divider the cdclk frequency on ILK is 450Mhz. At least that holds on my ILK and it matches how we program the divider. Supposedly cdclk is 400MHz on SNB and IVB, again based on the AUX 2x clock divider. Note that I don't have a SNB or IVB machine with eDP so I couldn't verify what the BIOS used, so this notion is purely based on our current code, Signed-off-by: Ville Syrjälä Signed-off-by: Mika Kahola Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2ce097fa4418..c43716a3ad2e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5886,6 +5886,11 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev) return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); } +static int ilk_get_display_clock_speed(struct drm_device *dev) +{ + return 450000; +} + static int i945_get_display_clock_speed(struct drm_device *dev) { return 400000; @@ -13498,6 +13503,9 @@ static void intel_init_display(struct drm_device *dev) if (IS_VALLEYVIEW(dev)) dev_priv->display.get_display_clock_speed = valleyview_get_display_clock_speed; + else if (IS_GEN5(dev)) + dev_priv->display.get_display_clock_speed = + ilk_get_display_clock_speed; else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) dev_priv->display.get_display_clock_speed = i945_get_display_clock_speed; -- cgit v1.2.3 From a7c66cd86ae0a2377b6efda56b93b26ce1f4322e Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 31 Mar 2015 14:11:56 +0300 Subject: drm/i915: Assume 400MHz cdclk for the rest of gen4-7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We don't currently have cdclk extraction code for 965g,snb,ivb. Let's assume 400 MHz until we know better. That seems to match hints in various vague documents. Whether that's good enough is not entirely clear. Signed-off-by: Ville Syrjälä Signed-off-by: Mika Kahola Acked-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c43716a3ad2e..44a146b27c2f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13506,7 +13506,8 @@ static void intel_init_display(struct drm_device *dev) else if (IS_GEN5(dev)) dev_priv->display.get_display_clock_speed = ilk_get_display_clock_speed; - else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) + else if (IS_I945G(dev) || IS_BROADWATER(dev) || + IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) dev_priv->display.get_display_clock_speed = i945_get_display_clock_speed; else if (IS_I915G(dev)) -- cgit v1.2.3 From 469d4b2a4ed7a255ffef31fad9d56bb6f7ac1213 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 31 Mar 2015 14:11:59 +0300 Subject: drm/i915: Simplify ilk_get_aux_clock_divider MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that we are "extracting" the cdclk frequency on ILK-IVB we can also simplify ilk_get_aux_clock_divider() to calculate the divider based on cdclk instead of hardcoding the values. Signed-off-by: Ville Syrjälä Signed-off-by: Mika Kahola Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index b70e635ccaf4..fd9fc3c6a72c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -696,15 +696,13 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; if (index) return 0; if (intel_dig_port->port == PORT_A) { - if (IS_GEN6(dev) || IS_GEN7(dev)) - return 200; /* SNB & IVB eDP input clock at 400Mhz */ - else - return 225; /* eDP input clock at 450Mhz */ + return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000); } else { return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); } -- cgit v1.2.3 From 1652d19e66c2dd118bd263ccba2a951b7946a2bb Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 31 Mar 2015 14:12:01 +0300 Subject: drm/i915: Convert the ddi cdclk code to get_display_clock_speed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unify the HSW/BDW/SKL cdclk extraction code to conform to the same .get_display_clock_speed() mold that all the other platforms use. v2: Update due to SKL code getting added v3: Rebase on top of -nightly (introduction of intel_audio.c) (Mika Kahola) Signed-off-by: Ville Syrjälä Signed-off-by: Mika Kahola Reviewed-by: Damien Lespiau [danvet: Add v3 note as suggested by Damien.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_audio.c | 3 +- drivers/gpu/drm/i915/intel_ddi.c | 101 +---------------------------------- drivers/gpu/drm/i915/intel_display.c | 98 ++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 2 +- 6 files changed, 102 insertions(+), 105 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index 2396cc702d18..0d5b1cea4715 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -485,7 +485,8 @@ static int i915_audio_component_get_cdclk_freq(struct device *dev) return -ENODEV; intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); - ret = intel_ddi_get_cdclk_freq(dev_priv); + ret = dev_priv->display.get_display_clock_speed(dev_priv->dev); + intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); return ret; diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 47b9307da24b..8c692d8a3ef6 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1689,105 +1689,6 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder) } } -static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv) -{ - uint32_t lcpll1 = I915_READ(LCPLL1_CTL); - uint32_t cdctl = I915_READ(CDCLK_CTL); - uint32_t linkrate; - - if (!(lcpll1 & LCPLL_PLL_ENABLE)) { - WARN(1, "LCPLL1 not enabled\n"); - return 24000; /* 24MHz is the cd freq with NSSC ref */ - } - - if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) - return 540000; - - linkrate = (I915_READ(DPLL_CTRL1) & - DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; - - if (linkrate == DPLL_CRTL1_LINK_RATE_2160 || - linkrate == DPLL_CRTL1_LINK_RATE_1080) { - /* vco 8640 */ - switch (cdctl & CDCLK_FREQ_SEL_MASK) { - case CDCLK_FREQ_450_432: - return 432000; - case CDCLK_FREQ_337_308: - return 308570; - case CDCLK_FREQ_675_617: - return 617140; - default: - WARN(1, "Unknown cd freq selection\n"); - } - } else { - /* vco 8100 */ - switch (cdctl & CDCLK_FREQ_SEL_MASK) { - case CDCLK_FREQ_450_432: - return 450000; - case CDCLK_FREQ_337_308: - return 337500; - case CDCLK_FREQ_675_617: - return 675000; - default: - WARN(1, "Unknown cd freq selection\n"); - } - } - - /* error case, do as if DPLL0 isn't enabled */ - return 24000; -} - -static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv) -{ - uint32_t lcpll = I915_READ(LCPLL_CTL); - uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; - - if (lcpll & LCPLL_CD_SOURCE_FCLK) - return 800000; - else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) - return 450000; - else if (freq == LCPLL_CLK_FREQ_450) - return 450000; - else if (freq == LCPLL_CLK_FREQ_54O_BDW) - return 540000; - else if (freq == LCPLL_CLK_FREQ_337_5_BDW) - return 337500; - else - return 675000; -} - -static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv) -{ - struct drm_device *dev = dev_priv->dev; - uint32_t lcpll = I915_READ(LCPLL_CTL); - uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; - - if (lcpll & LCPLL_CD_SOURCE_FCLK) - return 800000; - else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) - return 450000; - else if (freq == LCPLL_CLK_FREQ_450) - return 450000; - else if (IS_HSW_ULT(dev)) - return 337500; - else - return 540000; -} - -int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) -{ - struct drm_device *dev = dev_priv->dev; - - if (IS_SKYLAKE(dev)) - return skl_get_cdclk_freq(dev_priv); - - if (IS_BROADWELL(dev)) - return bdw_get_cdclk_freq(dev_priv); - - /* Haswell */ - return hsw_get_cdclk_freq(dev_priv); -} - static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { @@ -1974,7 +1875,7 @@ void intel_ddi_pll_init(struct drm_device *dev) hsw_shared_dplls_init(dev_priv); DRM_DEBUG_KMS("CDCLK running at %dKHz\n", - intel_ddi_get_cdclk_freq(dev_priv)); + dev_priv->display.get_display_clock_speed(dev)); if (IS_SKYLAKE(dev)) { if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 44a146b27c2f..d3cdc12a6330 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5864,6 +5864,93 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, return 0; } +static int skylake_get_display_clock_speed(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = to_i915(dev); + uint32_t lcpll1 = I915_READ(LCPLL1_CTL); + uint32_t cdctl = I915_READ(CDCLK_CTL); + uint32_t linkrate; + + if (!(lcpll1 & LCPLL_PLL_ENABLE)) { + WARN(1, "LCPLL1 not enabled\n"); + return 24000; /* 24MHz is the cd freq with NSSC ref */ + } + + if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) + return 540000; + + linkrate = (I915_READ(DPLL_CTRL1) & + DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; + + if (linkrate == DPLL_CRTL1_LINK_RATE_2160 || + linkrate == DPLL_CRTL1_LINK_RATE_1080) { + /* vco 8640 */ + switch (cdctl & CDCLK_FREQ_SEL_MASK) { + case CDCLK_FREQ_450_432: + return 432000; + case CDCLK_FREQ_337_308: + return 308570; + case CDCLK_FREQ_675_617: + return 617140; + default: + WARN(1, "Unknown cd freq selection\n"); + } + } else { + /* vco 8100 */ + switch (cdctl & CDCLK_FREQ_SEL_MASK) { + case CDCLK_FREQ_450_432: + return 450000; + case CDCLK_FREQ_337_308: + return 337500; + case CDCLK_FREQ_675_617: + return 675000; + default: + WARN(1, "Unknown cd freq selection\n"); + } + } + + /* error case, do as if DPLL0 isn't enabled */ + return 24000; +} + +static int broadwell_get_display_clock_speed(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t lcpll = I915_READ(LCPLL_CTL); + uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; + + if (lcpll & LCPLL_CD_SOURCE_FCLK) + return 800000; + else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) + return 450000; + else if (freq == LCPLL_CLK_FREQ_450) + return 450000; + else if (freq == LCPLL_CLK_FREQ_54O_BDW) + return 540000; + else if (freq == LCPLL_CLK_FREQ_337_5_BDW) + return 337500; + else + return 675000; +} + +static int haswell_get_display_clock_speed(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t lcpll = I915_READ(LCPLL_CTL); + uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; + + if (lcpll & LCPLL_CD_SOURCE_FCLK) + return 800000; + else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) + return 450000; + else if (freq == LCPLL_CLK_FREQ_450) + return 450000; + else if (IS_HSW_ULT(dev)) + return 337500; + else + return 540000; +} + static int valleyview_get_display_clock_speed(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -13500,7 +13587,16 @@ static void intel_init_display(struct drm_device *dev) } /* Returns the core display clock speed */ - if (IS_VALLEYVIEW(dev)) + if (IS_SKYLAKE(dev)) + dev_priv->display.get_display_clock_speed = + skylake_get_display_clock_speed; + else if (IS_BROADWELL(dev)) + dev_priv->display.get_display_clock_speed = + broadwell_get_display_clock_speed; + else if (IS_HASWELL(dev)) + dev_priv->display.get_display_clock_speed = + haswell_get_display_clock_speed; + else if (IS_VALLEYVIEW(dev)) dev_priv->display.get_display_clock_speed = valleyview_get_display_clock_speed; else if (IS_GEN5(dev)) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index fd9fc3c6a72c..7936155acbe8 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -717,7 +717,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) if (intel_dig_port->port == PORT_A) { if (index) return 0; - return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); + return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000); } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { /* Workaround for non-ULT HSW */ switch (index) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 6036e3b73b7b..4799b11f30c5 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -855,7 +855,6 @@ void hsw_fdi_link_train(struct drm_crtc *crtc); void intel_ddi_init(struct drm_device *dev, enum port port); enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); -int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); void intel_ddi_pll_init(struct drm_device *dev); void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fa4ccb346389..e1392e79c5c4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1792,7 +1792,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, mode->crtc_clock); ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, - intel_ddi_get_cdclk_freq(dev_priv)); + dev_priv->display.get_display_clock_speed(dev_priv->dev)); return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | PIPE_WM_LINETIME_TIME(linetime); -- cgit v1.2.3 From f3dc74c0e17b712cbcb4688a28d27df3fa8644a9 Mon Sep 17 00:00:00 2001 From: John Harrison Date: Thu, 19 Mar 2015 12:30:06 +0000 Subject: drm/i915: Rename 'do_execbuf' to 'execbuf_submit' The submission portion of the execbuffer code path was abstracted into a function pointer indirection as part of the legacy vs execlist work. The two implementation functions are called 'i915_gem_ringbuffer_submission' and 'intel_execlists_submission' but the pointer was called 'do_execbuf'. There is already a 'i915_gem_do_execbuffer' function (which is what calls the pointer indirection). The name of the pointer is therefore considered to be backwards and should be changed. This patch renames it to 'execbuf_submit' which is hopefully a bit clearer. For: VIZ-5115 Signed-off-by: John Harrison Reviewed-by: Tomas Elf Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 14 +++++++------- drivers/gpu/drm/i915/i915_gem.c | 4 ++-- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +++--- 3 files changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4ef320c17b63..727fc5448520 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1814,13 +1814,13 @@ struct drm_i915_private { /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ struct { - int (*do_execbuf)(struct drm_device *dev, struct drm_file *file, - struct intel_engine_cs *ring, - struct intel_context *ctx, - struct drm_i915_gem_execbuffer2 *args, - struct list_head *vmas, - struct drm_i915_gem_object *batch_obj, - u64 exec_start, u32 flags); + int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file, + struct intel_engine_cs *ring, + struct intel_context *ctx, + struct drm_i915_gem_execbuffer2 *args, + struct list_head *vmas, + struct drm_i915_gem_object *batch_obj, + u64 exec_start, u32 flags); int (*init_rings)(struct drm_device *dev); void (*cleanup_ring)(struct intel_engine_cs *ring); void (*stop_ring)(struct intel_engine_cs *ring); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 3a9136584833..815223694f32 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4859,12 +4859,12 @@ int i915_gem_init(struct drm_device *dev) } if (!i915.enable_execlists) { - dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; + dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; dev_priv->gt.init_rings = i915_gem_init_rings; dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; dev_priv->gt.stop_ring = intel_stop_ring_buffer; } else { - dev_priv->gt.do_execbuf = intel_execlists_submission; + dev_priv->gt.execbuf_submit = intel_execlists_submission; dev_priv->gt.init_rings = intel_logical_rings_init; dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; dev_priv->gt.stop_ring = intel_logical_ring_stop; diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index a3190e793ed4..2522f325e0e6 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1601,9 +1601,9 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, } else exec_start += i915_gem_obj_offset(batch_obj, vm); - ret = dev_priv->gt.do_execbuf(dev, file, ring, ctx, args, - &eb->vmas, batch_obj, exec_start, - dispatch_flags); + ret = dev_priv->gt.execbuf_submit(dev, file, ring, ctx, args, + &eb->vmas, batch_obj, exec_start, + dispatch_flags); /* * FIXME: We crucially rely upon the active tracking for the (ppgtt) -- cgit v1.2.3 From bc0dce3fd0526215aa781c28069519d126d50129 Mon Sep 17 00:00:00 2001 From: John Harrison Date: Thu, 19 Mar 2015 12:30:07 +0000 Subject: drm/i915: Make intel_logical_ring_begin() static The only usage of intel_logical_ring_begin() is within intel_lrc.c so it can be made static. To avoid a forward declaration at the top of the file, it and bunch of other functions have been shuffled upwards. For: VIZ-5115 Signed-off-by: John Harrison Reviewed-by: Tomas Elf Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_lrc.c | 474 +++++++++++++++++++-------------------- drivers/gpu/drm/i915/intel_lrc.h | 3 - 2 files changed, 237 insertions(+), 240 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index fcb074bd55dc..cad4300dd55c 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -611,6 +611,243 @@ static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, return logical_ring_invalidate_all_caches(ringbuf, ctx); } +static int logical_ring_alloc_request(struct intel_engine_cs *ring, + struct intel_context *ctx) +{ + struct drm_i915_gem_request *request; + struct drm_i915_private *dev_private = ring->dev->dev_private; + int ret; + + if (ring->outstanding_lazy_request) + return 0; + + request = kzalloc(sizeof(*request), GFP_KERNEL); + if (request == NULL) + return -ENOMEM; + + if (ctx != ring->default_context) { + ret = intel_lr_context_pin(ring, ctx); + if (ret) { + kfree(request); + return ret; + } + } + + kref_init(&request->ref); + request->ring = ring; + request->uniq = dev_private->request_uniq++; + + ret = i915_gem_get_seqno(ring->dev, &request->seqno); + if (ret) { + intel_lr_context_unpin(ring, ctx); + kfree(request); + return ret; + } + + request->ctx = ctx; + i915_gem_context_reference(request->ctx); + request->ringbuf = ctx->engine[ring->id].ringbuf; + + ring->outstanding_lazy_request = request; + return 0; +} + +static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, + int bytes) +{ + struct intel_engine_cs *ring = ringbuf->ring; + struct drm_i915_gem_request *request; + int ret; + + if (intel_ring_space(ringbuf) >= bytes) + return 0; + + list_for_each_entry(request, &ring->request_list, list) { + /* + * The request queue is per-engine, so can contain requests + * from multiple ringbuffers. Here, we must ignore any that + * aren't from the ringbuffer we're considering. + */ + struct intel_context *ctx = request->ctx; + if (ctx->engine[ring->id].ringbuf != ringbuf) + continue; + + /* Would completion of this request free enough space? */ + if (__intel_ring_space(request->tail, ringbuf->tail, + ringbuf->size) >= bytes) { + break; + } + } + + if (&request->list == &ring->request_list) + return -ENOSPC; + + ret = i915_wait_request(request); + if (ret) + return ret; + + i915_gem_retire_requests_ring(ring); + + return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC; +} + +/* + * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload + * @ringbuf: Logical Ringbuffer to advance. + * + * The tail is updated in our logical ringbuffer struct, not in the actual context. What + * really happens during submission is that the context and current tail will be placed + * on a queue waiting for the ELSP to be ready to accept a new context submission. At that + * point, the tail *inside* the context is updated and the ELSP written to. + */ +static void +intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf, + struct intel_context *ctx, + struct drm_i915_gem_request *request) +{ + struct intel_engine_cs *ring = ringbuf->ring; + + intel_logical_ring_advance(ringbuf); + + if (intel_ring_stopped(ring)) + return; + + execlists_context_queue(ring, ctx, ringbuf->tail, request); +} + +static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, + struct intel_context *ctx, + int bytes) +{ + struct intel_engine_cs *ring = ringbuf->ring; + struct drm_device *dev = ring->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + unsigned long end; + int ret; + + ret = logical_ring_wait_request(ringbuf, bytes); + if (ret != -ENOSPC) + return ret; + + /* Force the context submission in case we have been skipping it */ + intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL); + + /* With GEM the hangcheck timer should kick us out of the loop, + * leaving it early runs the risk of corrupting GEM state (due + * to running on almost untested codepaths). But on resume + * timers don't work yet, so prevent a complete hang in that + * case by choosing an insanely large timeout. */ + end = jiffies + 60 * HZ; + + ret = 0; + do { + if (intel_ring_space(ringbuf) >= bytes) + break; + + msleep(1); + + if (dev_priv->mm.interruptible && signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + + ret = i915_gem_check_wedge(&dev_priv->gpu_error, + dev_priv->mm.interruptible); + if (ret) + break; + + if (time_after(jiffies, end)) { + ret = -EBUSY; + break; + } + } while (1); + + return ret; +} + +static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf, + struct intel_context *ctx) +{ + uint32_t __iomem *virt; + int rem = ringbuf->size - ringbuf->tail; + + if (ringbuf->space < rem) { + int ret = logical_ring_wait_for_space(ringbuf, ctx, rem); + + if (ret) + return ret; + } + + virt = ringbuf->virtual_start + ringbuf->tail; + rem /= 4; + while (rem--) + iowrite32(MI_NOOP, virt++); + + ringbuf->tail = 0; + intel_ring_update_space(ringbuf); + + return 0; +} + +static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, + struct intel_context *ctx, int bytes) +{ + int ret; + + if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { + ret = logical_ring_wrap_buffer(ringbuf, ctx); + if (unlikely(ret)) + return ret; + } + + if (unlikely(ringbuf->space < bytes)) { + ret = logical_ring_wait_for_space(ringbuf, ctx, bytes); + if (unlikely(ret)) + return ret; + } + + return 0; +} + +/** + * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands + * + * @ringbuf: Logical ringbuffer. + * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. + * + * The ringbuffer might not be ready to accept the commands right away (maybe it needs to + * be wrapped, or wait a bit for the tail to be updated). This function takes care of that + * and also preallocates a request (every workload submission is still mediated through + * requests, same as it did with legacy ringbuffer submission). + * + * Return: non-zero if the ringbuffer is not ready to be written to. + */ +static int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, + struct intel_context *ctx, int num_dwords) +{ + struct intel_engine_cs *ring = ringbuf->ring; + struct drm_device *dev = ring->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + int ret; + + ret = i915_gem_check_wedge(&dev_priv->gpu_error, + dev_priv->mm.interruptible); + if (ret) + return ret; + + ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t)); + if (ret) + return ret; + + /* Preallocate the olr before touching the ring */ + ret = logical_ring_alloc_request(ring, ctx); + if (ret) + return ret; + + ringbuf->space -= num_dwords * sizeof(uint32_t); + return 0; +} + /** * execlists_submission() - submit a batchbuffer for execution, Execlists style * @dev: DRM device. @@ -787,30 +1024,6 @@ int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf, return 0; } -/* - * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload - * @ringbuf: Logical Ringbuffer to advance. - * - * The tail is updated in our logical ringbuffer struct, not in the actual context. What - * really happens during submission is that the context and current tail will be placed - * on a queue waiting for the ELSP to be ready to accept a new context submission. At that - * point, the tail *inside* the context is updated and the ELSP written to. - */ -static void -intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf, - struct intel_context *ctx, - struct drm_i915_gem_request *request) -{ - struct intel_engine_cs *ring = ringbuf->ring; - - intel_logical_ring_advance(ringbuf); - - if (intel_ring_stopped(ring)) - return; - - execlists_context_queue(ring, ctx, ringbuf->tail, request); -} - static int intel_lr_context_pin(struct intel_engine_cs *ring, struct intel_context *ctx) { @@ -855,219 +1068,6 @@ void intel_lr_context_unpin(struct intel_engine_cs *ring, } } -static int logical_ring_alloc_request(struct intel_engine_cs *ring, - struct intel_context *ctx) -{ - struct drm_i915_gem_request *request; - struct drm_i915_private *dev_private = ring->dev->dev_private; - int ret; - - if (ring->outstanding_lazy_request) - return 0; - - request = kzalloc(sizeof(*request), GFP_KERNEL); - if (request == NULL) - return -ENOMEM; - - if (ctx != ring->default_context) { - ret = intel_lr_context_pin(ring, ctx); - if (ret) { - kfree(request); - return ret; - } - } - - kref_init(&request->ref); - request->ring = ring; - request->uniq = dev_private->request_uniq++; - - ret = i915_gem_get_seqno(ring->dev, &request->seqno); - if (ret) { - intel_lr_context_unpin(ring, ctx); - kfree(request); - return ret; - } - - request->ctx = ctx; - i915_gem_context_reference(request->ctx); - request->ringbuf = ctx->engine[ring->id].ringbuf; - - ring->outstanding_lazy_request = request; - return 0; -} - -static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, - int bytes) -{ - struct intel_engine_cs *ring = ringbuf->ring; - struct drm_i915_gem_request *request; - int ret; - - if (intel_ring_space(ringbuf) >= bytes) - return 0; - - list_for_each_entry(request, &ring->request_list, list) { - /* - * The request queue is per-engine, so can contain requests - * from multiple ringbuffers. Here, we must ignore any that - * aren't from the ringbuffer we're considering. - */ - struct intel_context *ctx = request->ctx; - if (ctx->engine[ring->id].ringbuf != ringbuf) - continue; - - /* Would completion of this request free enough space? */ - if (__intel_ring_space(request->tail, ringbuf->tail, - ringbuf->size) >= bytes) { - break; - } - } - - if (&request->list == &ring->request_list) - return -ENOSPC; - - ret = i915_wait_request(request); - if (ret) - return ret; - - i915_gem_retire_requests_ring(ring); - - return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC; -} - -static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, - struct intel_context *ctx, - int bytes) -{ - struct intel_engine_cs *ring = ringbuf->ring; - struct drm_device *dev = ring->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - unsigned long end; - int ret; - - ret = logical_ring_wait_request(ringbuf, bytes); - if (ret != -ENOSPC) - return ret; - - /* Force the context submission in case we have been skipping it */ - intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL); - - /* With GEM the hangcheck timer should kick us out of the loop, - * leaving it early runs the risk of corrupting GEM state (due - * to running on almost untested codepaths). But on resume - * timers don't work yet, so prevent a complete hang in that - * case by choosing an insanely large timeout. */ - end = jiffies + 60 * HZ; - - ret = 0; - do { - if (intel_ring_space(ringbuf) >= bytes) - break; - - msleep(1); - - if (dev_priv->mm.interruptible && signal_pending(current)) { - ret = -ERESTARTSYS; - break; - } - - ret = i915_gem_check_wedge(&dev_priv->gpu_error, - dev_priv->mm.interruptible); - if (ret) - break; - - if (time_after(jiffies, end)) { - ret = -EBUSY; - break; - } - } while (1); - - return ret; -} - -static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf, - struct intel_context *ctx) -{ - uint32_t __iomem *virt; - int rem = ringbuf->size - ringbuf->tail; - - if (ringbuf->space < rem) { - int ret = logical_ring_wait_for_space(ringbuf, ctx, rem); - - if (ret) - return ret; - } - - virt = ringbuf->virtual_start + ringbuf->tail; - rem /= 4; - while (rem--) - iowrite32(MI_NOOP, virt++); - - ringbuf->tail = 0; - intel_ring_update_space(ringbuf); - - return 0; -} - -static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, - struct intel_context *ctx, int bytes) -{ - int ret; - - if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { - ret = logical_ring_wrap_buffer(ringbuf, ctx); - if (unlikely(ret)) - return ret; - } - - if (unlikely(ringbuf->space < bytes)) { - ret = logical_ring_wait_for_space(ringbuf, ctx, bytes); - if (unlikely(ret)) - return ret; - } - - return 0; -} - -/** - * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands - * - * @ringbuf: Logical ringbuffer. - * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. - * - * The ringbuffer might not be ready to accept the commands right away (maybe it needs to - * be wrapped, or wait a bit for the tail to be updated). This function takes care of that - * and also preallocates a request (every workload submission is still mediated through - * requests, same as it did with legacy ringbuffer submission). - * - * Return: non-zero if the ringbuffer is not ready to be written to. - */ -int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, - struct intel_context *ctx, int num_dwords) -{ - struct intel_engine_cs *ring = ringbuf->ring; - struct drm_device *dev = ring->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - int ret; - - ret = i915_gem_check_wedge(&dev_priv->gpu_error, - dev_priv->mm.interruptible); - if (ret) - return ret; - - ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t)); - if (ret) - return ret; - - /* Preallocate the olr before touching the ring */ - ret = logical_ring_alloc_request(ring, ctx); - if (ret) - return ret; - - ringbuf->space -= num_dwords * sizeof(uint32_t); - return 0; -} - static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring, struct intel_context *ctx) { diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index adb731e49c57..ac8f81a99fea 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -63,9 +63,6 @@ static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf, iowrite32(data, ringbuf->virtual_start + ringbuf->tail); ringbuf->tail += 4; } -int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, - struct intel_context *ctx, - int num_dwords); /* Logical Ring Contexts */ void intel_lr_context_free(struct intel_context *ctx); -- cgit v1.2.3 From 6689cb2b62065b5417aeda13d57d61b437b2126e Mon Sep 17 00:00:00 2001 From: John Harrison Date: Thu, 19 Mar 2015 12:30:08 +0000 Subject: drm/i915: Move common request allocation code into a common function The request allocation code is largely duplicated between legacy mode and execlist mode. The actual difference between the two versions of the code is pretty minimal. This patch moves the common code out into a separate function. This is then called by the execution specific version prior to setting up the one different value. For: VIZ-5190 Signed-off-by: John Harrison Reviewed-by: Tomas Elf Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem.c | 37 +++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_lrc.c | 39 +++++++-------------------------- drivers/gpu/drm/i915/intel_lrc.h | 2 ++ drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +++-------------------- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++ 6 files changed, 54 insertions(+), 56 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 727fc5448520..83cda2786e55 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2115,6 +2115,8 @@ struct drm_i915_gem_request { }; +int i915_gem_request_alloc(struct intel_engine_cs *ring, + struct intel_context *ctx); void i915_gem_request_free(struct kref *req_ref); static inline uint32_t diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 815223694f32..267fdf0f46ae 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2518,6 +2518,43 @@ void i915_gem_request_free(struct kref *req_ref) kfree(req); } +int i915_gem_request_alloc(struct intel_engine_cs *ring, + struct intel_context *ctx) +{ + int ret; + struct drm_i915_gem_request *request; + struct drm_i915_private *dev_private = ring->dev->dev_private; + + if (ring->outstanding_lazy_request) + return 0; + + request = kzalloc(sizeof(*request), GFP_KERNEL); + if (request == NULL) + return -ENOMEM; + + ret = i915_gem_get_seqno(ring->dev, &request->seqno); + if (ret) { + kfree(request); + return ret; + } + + kref_init(&request->ref); + request->ring = ring; + request->uniq = dev_private->request_uniq++; + + if (i915.enable_execlists) + ret = intel_logical_ring_alloc_request_extras(request, ctx); + else + ret = intel_ring_alloc_request_extras(request); + if (ret) { + kfree(request); + return ret; + } + + ring->outstanding_lazy_request = request; + return 0; +} + struct drm_i915_gem_request * i915_gem_find_active_request(struct intel_engine_cs *ring) { diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index cad4300dd55c..6504689467b1 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -611,44 +611,21 @@ static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, return logical_ring_invalidate_all_caches(ringbuf, ctx); } -static int logical_ring_alloc_request(struct intel_engine_cs *ring, - struct intel_context *ctx) +int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request, + struct intel_context *ctx) { - struct drm_i915_gem_request *request; - struct drm_i915_private *dev_private = ring->dev->dev_private; int ret; - if (ring->outstanding_lazy_request) - return 0; - - request = kzalloc(sizeof(*request), GFP_KERNEL); - if (request == NULL) - return -ENOMEM; - - if (ctx != ring->default_context) { - ret = intel_lr_context_pin(ring, ctx); - if (ret) { - kfree(request); + if (ctx != request->ring->default_context) { + ret = intel_lr_context_pin(request->ring, ctx); + if (ret) return ret; - } - } - - kref_init(&request->ref); - request->ring = ring; - request->uniq = dev_private->request_uniq++; - - ret = i915_gem_get_seqno(ring->dev, &request->seqno); - if (ret) { - intel_lr_context_unpin(ring, ctx); - kfree(request); - return ret; } - request->ctx = ctx; + request->ringbuf = ctx->engine[request->ring->id].ringbuf; + request->ctx = ctx; i915_gem_context_reference(request->ctx); - request->ringbuf = ctx->engine[ring->id].ringbuf; - ring->outstanding_lazy_request = request; return 0; } @@ -840,7 +817,7 @@ static int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, return ret; /* Preallocate the olr before touching the ring */ - ret = logical_ring_alloc_request(ring, ctx); + ret = i915_gem_request_alloc(ring, ctx); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index ac8f81a99fea..04d3a6d8b207 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -36,6 +36,8 @@ #define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0) /* Logical Rings */ +int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request, + struct intel_context *ctx); void intel_logical_ring_stop(struct intel_engine_cs *ring); void intel_logical_ring_cleanup(struct intel_engine_cs *ring); int intel_logical_rings_init(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 441e2502b889..99fb2f06710a 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2181,32 +2181,10 @@ int intel_ring_idle(struct intel_engine_cs *ring) return i915_wait_request(req); } -static int -intel_ring_alloc_request(struct intel_engine_cs *ring) +int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) { - int ret; - struct drm_i915_gem_request *request; - struct drm_i915_private *dev_private = ring->dev->dev_private; - - if (ring->outstanding_lazy_request) - return 0; - - request = kzalloc(sizeof(*request), GFP_KERNEL); - if (request == NULL) - return -ENOMEM; - - kref_init(&request->ref); - request->ring = ring; - request->ringbuf = ring->buffer; - request->uniq = dev_private->request_uniq++; - - ret = i915_gem_get_seqno(ring->dev, &request->seqno); - if (ret) { - kfree(request); - return ret; - } + request->ringbuf = request->ring->buffer; - ring->outstanding_lazy_request = request; return 0; } @@ -2247,7 +2225,7 @@ int intel_ring_begin(struct intel_engine_cs *ring, return ret; /* Preallocate the olr before touching the ring */ - ret = intel_ring_alloc_request(ring); + ret = i915_gem_request_alloc(ring, ring->default_context); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index c761fe05ad6f..6566dd447498 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -390,6 +390,8 @@ int intel_alloc_ringbuffer_obj(struct drm_device *dev, void intel_stop_ring_buffer(struct intel_engine_cs *ring); void intel_cleanup_ring_buffer(struct intel_engine_cs *ring); +int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request); + int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n); int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring); static inline void intel_ring_emit(struct intel_engine_cs *ring, -- cgit v1.2.3 From dbe4646d6e3467adbe2ec8dbe6b7ceea57dee2ec Mon Sep 17 00:00:00 2001 From: John Harrison Date: Thu, 19 Mar 2015 12:30:09 +0000 Subject: drm/i915: Fix for ringbuf space wait in LRC mode The legacy and LRC code paths have an almost identical procedure for waiting for space in the ring buffer. They both search for a request in the free list that will advance the tail to a point where sufficient space is available. They then wait for that request, retire it and recalculate the free space value. Unfortunately, a bug in the LRC side meant that the resulting free space might not be as large as expected and indeed, might not be sufficient. This is because it was testing against the value of request->tail not request->postfix. Whereas, when a request is retired, ringbuf->tail is updated to req->postfix not req->tail. Another significant difference between the two is that the LRC one did not trust the wait for request to work! It redid the is there enough space available test and would fail the call if insufficient. Whereas, the legacy version just said 'return 0' - it assumed the preceeding code works. This difference meant that the LRC version still worked even with the bug - it just fell back to the polling wait path. For: VIZ-5115 Signed-off-by: John Harrison Reviewed-by: Thomas Daniel Reviewed-by: Tomas Elf Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_lrc.c | 10 ++++++---- drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++---- 2 files changed, 12 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 6504689467b1..1c3834fc5608 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -634,7 +634,7 @@ static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, { struct intel_engine_cs *ring = ringbuf->ring; struct drm_i915_gem_request *request; - int ret; + int ret, new_space; if (intel_ring_space(ringbuf) >= bytes) return 0; @@ -650,10 +650,10 @@ static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, continue; /* Would completion of this request free enough space? */ - if (__intel_ring_space(request->tail, ringbuf->tail, - ringbuf->size) >= bytes) { + new_space = __intel_ring_space(request->postfix, ringbuf->tail, + ringbuf->size); + if (new_space >= bytes) break; - } } if (&request->list == &ring->request_list) @@ -665,6 +665,8 @@ static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, i915_gem_retire_requests_ring(ring); + WARN_ON(intel_ring_space(ringbuf) < new_space); + return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC; } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 99fb2f06710a..a26bdf89e270 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2059,16 +2059,16 @@ static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) { struct intel_ringbuffer *ringbuf = ring->buffer; struct drm_i915_gem_request *request; - int ret; + int ret, new_space; if (intel_ring_space(ringbuf) >= n) return 0; list_for_each_entry(request, &ring->request_list, list) { - if (__intel_ring_space(request->postfix, ringbuf->tail, - ringbuf->size) >= n) { + new_space = __intel_ring_space(request->postfix, ringbuf->tail, + ringbuf->size); + if (new_space >= n) break; - } } if (&request->list == &ring->request_list) @@ -2080,6 +2080,8 @@ static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) i915_gem_retire_requests_ring(ring); + WARN_ON(intel_ring_space(ringbuf) < new_space); + return 0; } -- cgit v1.2.3 From 988c70156ce1ae146e4105a3d21ec16c5894162b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 27 Mar 2015 00:20:19 +0200 Subject: drm/i915: rename GMBUS_PORT_* macros as GMBUS_PIN_* MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The specs refer to pin pairs. Start moving towards using pin rather than port all around to avoid confusion. No functional changes. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++---------- drivers/gpu/drm/i915/intel_bios.c | 2 +- drivers/gpu/drm/i915/intel_crt.c | 2 +- drivers/gpu/drm/i915/intel_dvo.c | 8 ++++---- drivers/gpu/drm/i915/intel_hdmi.c | 8 ++++---- drivers/gpu/drm/i915/intel_lvds.c | 2 +- drivers/gpu/drm/i915/intel_sdvo.c | 2 +- 8 files changed, 23 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 83cda2786e55..dca3a4d32a11 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3067,7 +3067,7 @@ extern int intel_setup_gmbus(struct drm_device *dev); extern void intel_teardown_gmbus(struct drm_device *dev); static inline bool intel_gmbus_is_port_valid(unsigned port) { - return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); + return (port >= GMBUS_PIN_SSC && port <= GMBUS_PIN_DPD); } extern struct i2c_adapter *intel_gmbus_get_adapter( diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b522eb6e59a4..b6113c9a803b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1788,16 +1788,16 @@ enum skl_disp_power_wells { #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ -#define GMBUS_PORT_DISABLED 0 -#define GMBUS_PORT_SSC 1 -#define GMBUS_PORT_VGADDC 2 -#define GMBUS_PORT_PANEL 3 -#define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */ -#define GMBUS_PORT_DPC 4 /* HDMIC */ -#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ -#define GMBUS_PORT_DPD 6 /* HDMID */ -#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ -#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) +#define GMBUS_PIN_DISABLED 0 +#define GMBUS_PIN_SSC 1 +#define GMBUS_PIN_VGADDC 2 +#define GMBUS_PIN_PANEL 3 +#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */ +#define GMBUS_PIN_DPC 4 /* HDMIC */ +#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ +#define GMBUS_PIN_DPD 6 /* HDMID */ +#define GMBUS_PIN_RESERVED 7 /* 7 reserved */ +#define GMBUS_NUM_PORTS (GMBUS_PIN_DPD - GMBUS_PIN_SSC + 1) #define GMBUS1 0x5104 /* command/status */ #define GMBUS_SW_CLR_INT (1<<31) #define GMBUS_SW_RDY (1<<30) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index c684085cb56a..40c8375a4477 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -1133,7 +1133,7 @@ init_vbt_defaults(struct drm_i915_private *dev_priv) struct drm_device *dev = dev_priv->dev; enum port port; - dev_priv->vbt.crt_ddc_pin = GMBUS_PORT_VGADDC; + dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; /* Default to having backlight */ dev_priv->vbt.backlight.present = true; diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 6095a998bdac..fa5699c8452b 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -747,7 +747,7 @@ static int intel_crt_get_modes(struct drm_connector *connector) goto out; /* Try to probe digital port for output in DVI-I -> VGA mode. */ - i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); + i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); ret = intel_crt_ddc_get_modes(connector, i2c); out: diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index f2ed122615ae..447cdc76c960 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -80,7 +80,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = { .name = "ch7017", .dvo_reg = DVOC, .slave_addr = 0x75, - .gpio = GMBUS_PORT_DPB, + .gpio = GMBUS_PIN_DPB, .dev_ops = &ch7017_ops, }, { @@ -364,7 +364,7 @@ static int intel_dvo_get_modes(struct drm_connector *connector) * that's not the case. */ intel_ddc_get_modes(connector, - intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC)); + intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC)); if (!list_empty(&connector->probed_modes)) return 1; @@ -505,9 +505,9 @@ void intel_dvo_init(struct drm_device *dev) if (intel_gmbus_is_port_valid(dvo->gpio)) gpio = dvo->gpio; else if (dvo->type == INTEL_DVO_CHIP_LVDS) - gpio = GMBUS_PORT_SSC; + gpio = GMBUS_PIN_SSC; else - gpio = GMBUS_PORT_DPB; + gpio = GMBUS_PIN_DPB; /* Set up the I2C bus necessary for the chip we're probing. * It appears that everything is on GPIOE except for panels diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index cacbafdad3ab..26222e6c1ff3 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1681,18 +1681,18 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, switch (port) { case PORT_B: - intel_hdmi->ddc_bus = GMBUS_PORT_DPB; + intel_hdmi->ddc_bus = GMBUS_PIN_DPB; intel_encoder->hpd_pin = HPD_PORT_B; break; case PORT_C: - intel_hdmi->ddc_bus = GMBUS_PORT_DPC; + intel_hdmi->ddc_bus = GMBUS_PIN_DPC; intel_encoder->hpd_pin = HPD_PORT_C; break; case PORT_D: if (IS_CHERRYVIEW(dev)) - intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV; + intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; else - intel_hdmi->ddc_bus = GMBUS_PORT_DPD; + intel_hdmi->ddc_bus = GMBUS_PIN_DPD; intel_encoder->hpd_pin = HPD_PORT_D; break; case PORT_A: diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 06d2da336f7c..875916152645 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -921,7 +921,7 @@ void intel_lvds_init(struct drm_device *dev) if (dmi_check_system(intel_no_lvds)) return; - pin = GMBUS_PORT_PANEL; + pin = GMBUS_PIN_PANEL; if (!lvds_is_present_in_vbt(dev, &pin)) { DRM_DEBUG_KMS("LVDS is not present in VBT\n"); return; diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index f5b7e1e7c5e0..3e0e9b0e3503 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -2294,7 +2294,7 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin)) pin = mapping->i2c_pin; else - pin = GMBUS_PORT_DPB; + pin = GMBUS_PIN_DPB; sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); -- cgit v1.2.3 From 0184df465efc3b0a09e6999437ca4925567acf28 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 27 Mar 2015 00:20:20 +0200 Subject: drm/i915: refer to pin instead of port in the intel_i2c.c interfaces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename intel_gmbus_is_port_valid to intel_gmbus_is_valid_pin, and rename port parameters to pin as well. This matches usage all around, as usually a pin is passed to the validity check function. No functional changes. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 8 ++++---- drivers/gpu/drm/i915/intel_bios.c | 2 +- drivers/gpu/drm/i915/intel_dvo.c | 2 +- drivers/gpu/drm/i915/intel_i2c.c | 8 ++++---- drivers/gpu/drm/i915/intel_lvds.c | 2 +- drivers/gpu/drm/i915/intel_sdvo.c | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index dca3a4d32a11..b0390c8c9595 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3065,13 +3065,13 @@ void i915_teardown_sysfs(struct drm_device *dev_priv); /* intel_i2c.c */ extern int intel_setup_gmbus(struct drm_device *dev); extern void intel_teardown_gmbus(struct drm_device *dev); -static inline bool intel_gmbus_is_port_valid(unsigned port) +static inline bool intel_gmbus_is_valid_pin(unsigned int pin) { - return (port >= GMBUS_PIN_SSC && port <= GMBUS_PIN_DPD); + return (pin >= GMBUS_PIN_SSC && pin <= GMBUS_PIN_DPD); } -extern struct i2c_adapter *intel_gmbus_get_adapter( - struct drm_i915_private *dev_priv, unsigned port); +extern struct i2c_adapter * +intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 40c8375a4477..333f40793435 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -438,7 +438,7 @@ parse_general_definitions(struct drm_i915_private *dev_priv, if (block_size >= sizeof(*general)) { int bus_pin = general->crt_ddc_gmbus_pin; DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin); - if (intel_gmbus_is_port_valid(bus_pin)) + if (intel_gmbus_is_valid_pin(bus_pin)) dev_priv->vbt.crt_ddc_pin = bus_pin; } else { DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n", diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index 447cdc76c960..bfedea3826d7 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -502,7 +502,7 @@ void intel_dvo_init(struct drm_device *dev) * special cases, but otherwise default to what's defined * in the spec. */ - if (intel_gmbus_is_port_valid(dvo->gpio)) + if (intel_gmbus_is_valid_pin(dvo->gpio)) gpio = dvo->gpio; else if (dvo->type == INTEL_DVO_CHIP_LVDS) gpio = GMBUS_PIN_SSC; diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index b31088a551f2..b0003a2bd854 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -574,12 +574,12 @@ err: } struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, - unsigned port) + unsigned int pin) { - WARN_ON(!intel_gmbus_is_port_valid(port)); + WARN_ON(!intel_gmbus_is_valid_pin(pin)); /* -1 to map pin pair to gmbus index */ - return (intel_gmbus_is_port_valid(port)) ? - &dev_priv->gmbus[port - 1].adapter : NULL; + return (intel_gmbus_is_valid_pin(pin)) ? + &dev_priv->gmbus[pin - 1].adapter : NULL; } void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 875916152645..d61aa78ed7e3 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -781,7 +781,7 @@ static bool lvds_is_present_in_vbt(struct drm_device *dev, child->device_type != DEVICE_TYPE_LFP) continue; - if (intel_gmbus_is_port_valid(child->i2c_pin)) + if (intel_gmbus_is_valid_pin(child->i2c_pin)) *i2c_pin = child->i2c_pin; /* However, we cannot trust the BIOS writers to populate diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 3e0e9b0e3503..124992e48abd 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -2291,7 +2291,7 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, else mapping = &dev_priv->sdvo_mappings[1]; - if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin)) + if (mapping->initialized && intel_gmbus_is_valid_pin(mapping->i2c_pin)) pin = mapping->i2c_pin; else pin = GMBUS_PIN_DPB; -- cgit v1.2.3 From 5ea6e5e36ee54a83dfef9739f006a6a91d00e7fe Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 1 Apr 2015 10:55:04 +0300 Subject: drm/i915: index gmbus tables using the pin pair number MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Index the gmbus tables directly using the pin instead of having a confusing "port = i + 1" mapping. This finishes off removing the "gmbus port" as a notion, and leaves us with just the "gmbus pin". As pin 0 is invalid by definition and the gmbus tables will have a gap at that index, add pin validity check to all the loops. This will be benefitial for supporting platforms that have different numbers of pins, or gaps. v2: s/GMBUS_PIN_MAX/GMBUS_NUM_PINS/ (Ville, Daniel) Reviewed-by: Ville Syrjälä Signed-off-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_i2c.c | 65 +++++++++++++++++++++++----------------- 3 files changed, 40 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b0390c8c9595..0ad11d9c123f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1574,8 +1574,7 @@ struct drm_i915_private { struct i915_virtual_gpu vgpu; - struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; - + struct intel_gmbus gmbus[GMBUS_NUM_PINS]; /** gmbus_mutex protects against concurrent usage of the single hw gmbus * controller on different i2c buses. */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b6113c9a803b..49fbed9c35cd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1797,7 +1797,7 @@ enum skl_disp_power_wells { #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ #define GMBUS_PIN_DPD 6 /* HDMID */ #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ -#define GMBUS_NUM_PORTS (GMBUS_PIN_DPD - GMBUS_PIN_SSC + 1) +#define GMBUS_NUM_PINS 7 /* including 0 */ #define GMBUS1 0x5104 /* command/status */ #define GMBUS_SW_CLR_INT (1<<31) #define GMBUS_SW_RDY (1<<30) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index b0003a2bd854..ff47a8fdcb6d 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -34,18 +34,19 @@ #include #include "i915_drv.h" -struct gmbus_port { +struct gmbus_pin { const char *name; int reg; }; -static const struct gmbus_port gmbus_ports[] = { - { "ssc", GPIOB }, - { "vga", GPIOA }, - { "panel", GPIOC }, - { "dpc", GPIOD }, - { "dpb", GPIOE }, - { "dpd", GPIOF }, +/* Map gmbus pin pairs to names and registers. */ +static const struct gmbus_pin gmbus_pins[] = { + [GMBUS_PIN_SSC] = { "ssc", GPIOB }, + [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, + [GMBUS_PIN_PANEL] = { "panel", GPIOC }, + [GMBUS_PIN_DPC] = { "dpc", GPIOD }, + [GMBUS_PIN_DPB] = { "dpb", GPIOE }, + [GMBUS_PIN_DPD] = { "dpd", GPIOF }, }; /* Intel GPIO access functions */ @@ -182,15 +183,14 @@ intel_gpio_post_xfer(struct i2c_adapter *adapter) } static void -intel_gpio_setup(struct intel_gmbus *bus, u32 pin) +intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) { struct drm_i915_private *dev_priv = bus->dev_priv; struct i2c_algo_bit_data *algo; algo = &bus->bit_algo; - /* -1 to map pin pair to gmbus index */ - bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg; + bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_pins[pin].reg; bus->adapter.algo_data = algo; algo->setsda = set_data; @@ -517,7 +517,9 @@ static const struct i2c_algorithm gmbus_algorithm = { int intel_setup_gmbus(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int ret, i; + struct intel_gmbus *bus; + unsigned int pin; + int ret; if (HAS_PCH_NOP(dev)) return 0; @@ -531,16 +533,18 @@ int intel_setup_gmbus(struct drm_device *dev) mutex_init(&dev_priv->gmbus_mutex); init_waitqueue_head(&dev_priv->gmbus_wait_queue); - for (i = 0; i < GMBUS_NUM_PORTS; i++) { - struct intel_gmbus *bus = &dev_priv->gmbus[i]; - u32 port = i + 1; /* +1 to map gmbus index to pin pair */ + for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { + if (!intel_gmbus_is_valid_pin(pin)) + continue; + + bus = &dev_priv->gmbus[pin]; bus->adapter.owner = THIS_MODULE; bus->adapter.class = I2C_CLASS_DDC; snprintf(bus->adapter.name, sizeof(bus->adapter.name), "i915 gmbus %s", - gmbus_ports[i].name); + gmbus_pins[pin].name); bus->adapter.dev.parent = &dev->pdev->dev; bus->dev_priv = dev_priv; @@ -548,13 +552,13 @@ int intel_setup_gmbus(struct drm_device *dev) bus->adapter.algo = &gmbus_algorithm; /* By default use a conservative clock rate */ - bus->reg0 = port | GMBUS_RATE_100KHZ; + bus->reg0 = pin | GMBUS_RATE_100KHZ; /* gmbus seems to be broken on i830 */ if (IS_I830(dev)) bus->force_bit = 1; - intel_gpio_setup(bus, port); + intel_gpio_setup(bus, pin); ret = i2c_add_adapter(&bus->adapter); if (ret) @@ -566,8 +570,11 @@ int intel_setup_gmbus(struct drm_device *dev) return 0; err: - while (--i) { - struct intel_gmbus *bus = &dev_priv->gmbus[i]; + while (--pin) { + if (!intel_gmbus_is_valid_pin(pin)) + continue; + + bus = &dev_priv->gmbus[pin]; i2c_del_adapter(&bus->adapter); } return ret; @@ -576,10 +583,10 @@ err: struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin) { - WARN_ON(!intel_gmbus_is_valid_pin(pin)); - /* -1 to map pin pair to gmbus index */ - return (intel_gmbus_is_valid_pin(pin)) ? - &dev_priv->gmbus[pin - 1].adapter : NULL; + if (WARN_ON(!intel_gmbus_is_valid_pin(pin))) + return NULL; + + return &dev_priv->gmbus[pin].adapter; } void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) @@ -602,10 +609,14 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) void intel_teardown_gmbus(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int i; + struct intel_gmbus *bus; + unsigned int pin; + + for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { + if (!intel_gmbus_is_valid_pin(pin)) + continue; - for (i = 0; i < GMBUS_NUM_PORTS; i++) { - struct intel_gmbus *bus = &dev_priv->gmbus[i]; + bus = &dev_priv->gmbus[pin]; i2c_del_adapter(&bus->adapter); } } -- cgit v1.2.3 From 88ac7939d2a6cb67e338e72cf6aaff2ae526b026 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 27 Mar 2015 00:20:22 +0200 Subject: drm/i915: base gmbus pin validity check on the gmbus pin map array MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This will be helpful for adding future platforms. It is better to keep the information in the single point of truth (the table) instead of duplicating it into the validity function. While at it, add dev_priv parameter to the function, also to prepare for adding future platform support. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 6 ++---- drivers/gpu/drm/i915/intel_bios.c | 2 +- drivers/gpu/drm/i915/intel_dvo.c | 2 +- drivers/gpu/drm/i915/intel_i2c.c | 14 ++++++++++---- drivers/gpu/drm/i915/intel_lvds.c | 2 +- drivers/gpu/drm/i915/intel_sdvo.c | 3 ++- 6 files changed, 17 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0ad11d9c123f..d63997bc80e4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3064,10 +3064,8 @@ void i915_teardown_sysfs(struct drm_device *dev_priv); /* intel_i2c.c */ extern int intel_setup_gmbus(struct drm_device *dev); extern void intel_teardown_gmbus(struct drm_device *dev); -static inline bool intel_gmbus_is_valid_pin(unsigned int pin) -{ - return (pin >= GMBUS_PIN_SSC && pin <= GMBUS_PIN_DPD); -} +extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, + unsigned int pin); extern struct i2c_adapter * intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 333f40793435..ad2f3b0d922f 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -438,7 +438,7 @@ parse_general_definitions(struct drm_i915_private *dev_priv, if (block_size >= sizeof(*general)) { int bus_pin = general->crt_ddc_gmbus_pin; DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin); - if (intel_gmbus_is_valid_pin(bus_pin)) + if (intel_gmbus_is_valid_pin(dev_priv, bus_pin)) dev_priv->vbt.crt_ddc_pin = bus_pin; } else { DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n", diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index bfedea3826d7..9a27ec7100ef 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -502,7 +502,7 @@ void intel_dvo_init(struct drm_device *dev) * special cases, but otherwise default to what's defined * in the spec. */ - if (intel_gmbus_is_valid_pin(dvo->gpio)) + if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio)) gpio = dvo->gpio; else if (dvo->type == INTEL_DVO_CHIP_LVDS) gpio = GMBUS_PIN_SSC; diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index ff47a8fdcb6d..ec9cc8cf642e 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -49,6 +49,12 @@ static const struct gmbus_pin gmbus_pins[] = { [GMBUS_PIN_DPD] = { "dpd", GPIOF }, }; +bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, + unsigned int pin) +{ + return pin < ARRAY_SIZE(gmbus_pins) && gmbus_pins[pin].reg; +} + /* Intel GPIO access functions */ #define I2C_RISEFALL_TIME 10 @@ -534,7 +540,7 @@ int intel_setup_gmbus(struct drm_device *dev) init_waitqueue_head(&dev_priv->gmbus_wait_queue); for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { - if (!intel_gmbus_is_valid_pin(pin)) + if (!intel_gmbus_is_valid_pin(dev_priv, pin)) continue; bus = &dev_priv->gmbus[pin]; @@ -571,7 +577,7 @@ int intel_setup_gmbus(struct drm_device *dev) err: while (--pin) { - if (!intel_gmbus_is_valid_pin(pin)) + if (!intel_gmbus_is_valid_pin(dev_priv, pin)) continue; bus = &dev_priv->gmbus[pin]; @@ -583,7 +589,7 @@ err: struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin) { - if (WARN_ON(!intel_gmbus_is_valid_pin(pin))) + if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) return NULL; return &dev_priv->gmbus[pin].adapter; @@ -613,7 +619,7 @@ void intel_teardown_gmbus(struct drm_device *dev) unsigned int pin; for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { - if (!intel_gmbus_is_valid_pin(pin)) + if (!intel_gmbus_is_valid_pin(dev_priv, pin)) continue; bus = &dev_priv->gmbus[pin]; diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index d61aa78ed7e3..314a5d56ace2 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -781,7 +781,7 @@ static bool lvds_is_present_in_vbt(struct drm_device *dev, child->device_type != DEVICE_TYPE_LFP) continue; - if (intel_gmbus_is_valid_pin(child->i2c_pin)) + if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin)) *i2c_pin = child->i2c_pin; /* However, we cannot trust the BIOS writers to populate diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 124992e48abd..b121796c86aa 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -2291,7 +2291,8 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, else mapping = &dev_priv->sdvo_mappings[1]; - if (mapping->initialized && intel_gmbus_is_valid_pin(mapping->i2c_pin)) + if (mapping->initialized && + intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) pin = mapping->i2c_pin; else pin = GMBUS_PIN_DPB; -- cgit v1.2.3 From f61cccf3e9a4f7deae633b6c073a6e40ef8e86f3 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 31 Mar 2015 11:35:00 +0300 Subject: drm/i915: Set best_encoder field of connector_state also when disabling The best_encoder field of connector_state wasn't properly set when a connector was being disabled, leading to an incosistent atomic state. For now, this doesn't cause anything to blow up, because everywhere we're using connector_state->best_encoder there is a check for connector_state->crtc which is properly initialized. I reached the issue while testing some patches I haven't sent out yet, that remove the usage of intel_connector->new_encoder from check_digital_port_conflicts(). In that case, it would be possible to trigger the converted version of the WARN in that function. Signed-off-by: Ander Conselvan de Oliveira [danvet: Add commit message augmentation Ander supplied.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d3cdc12a6330..84f5b417ad3c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12100,6 +12100,7 @@ intel_modeset_stage_output_state(struct drm_device *dev, connector->encoder = connector->new_encoder; } else { connector_state->crtc = NULL; + connector_state->best_encoder = NULL; } } for_each_intel_crtc(dev, crtc) { -- cgit v1.2.3 From 2d1070b21e004609a5bebafdb4303bb021f5477c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 1 Apr 2015 10:36:56 +0100 Subject: drm/i915: Make debugfs/i915_gem_request more friendly Count the number of requests in a ring for the user and show who submitted them. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 39 ++++++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 007c7d7d8295..91c945b6a762 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -643,31 +643,44 @@ static int i915_gem_request_info(struct seq_file *m, void *data) struct drm_device *dev = node->minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_engine_cs *ring; - struct drm_i915_gem_request *gem_request; - int ret, count, i; + struct drm_i915_gem_request *rq; + int ret, any, i; ret = mutex_lock_interruptible(&dev->struct_mutex); if (ret) return ret; - count = 0; + any = 0; for_each_ring(ring, dev_priv, i) { - if (list_empty(&ring->request_list)) + int count; + + count = 0; + list_for_each_entry(rq, &ring->request_list, list) + count++; + if (count == 0) continue; - seq_printf(m, "%s requests:\n", ring->name); - list_for_each_entry(gem_request, - &ring->request_list, - list) { - seq_printf(m, " %x @ %d\n", - gem_request->seqno, - (int) (jiffies - gem_request->emitted_jiffies)); + seq_printf(m, "%s requests: %d\n", ring->name, count); + list_for_each_entry(rq, &ring->request_list, list) { + struct task_struct *task; + + rcu_read_lock(); + task = NULL; + if (rq->pid) + task = pid_task(rq->pid, PIDTYPE_PID); + seq_printf(m, " %x @ %d: %s [%d]\n", + rq->seqno, + (int) (jiffies - rq->emitted_jiffies), + task ? task->comm : "", + task ? task->pid : -1); + rcu_read_unlock(); } - count++; + + any++; } mutex_unlock(&dev->struct_mutex); - if (count == 0) + if (any == 0) seq_puts(m, "No requests\n"); return 0; -- cgit v1.2.3 From 474d1ec4a3d7775b071e60fdbe431cae37b84ff3 Mon Sep 17 00:00:00 2001 From: Sonika Jindal Date: Thu, 2 Apr 2015 11:02:44 +0530 Subject: drm/i915/skl: Enabling PSR2 SU with frame sync We make use of HW tracking for Selective update region and enable frame sync on sink. We use hardware's hardcoded data values for frame sync and GTC. v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to i915_psr struct, add aux_frame_sync to independently control aux frame sync, rename the TP2 TIME macro for 2500us (Rodrigo, Siva) v3: Moving the resolution restriction to intel_psr_enable so that we check it only once(Durga) Cc: Durgadoss R Cc: Rodrigo Vivi Signed-off-by: Sonika Jindal Reviewed-by: Durgadoss R Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++ drivers/gpu/drm/i915/intel_dp.c | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_psr.c | 38 +++++++++++++++++++++++++++++++++++++- 4 files changed, 68 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d63997bc80e4..1d62fbe3fcc0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -881,6 +881,8 @@ struct i915_psr { struct delayed_work work; unsigned busy_frontbuffer_bits; bool link_standby; + bool psr2_support; + bool aux_frame_sync; }; enum intel_pch { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 49fbed9c35cd..8db2a9169266 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2748,6 +2748,20 @@ enum skl_disp_power_wells { #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) #define EDP_PSR_DEBUG_MASK_HPD (1<<25) +#define EDP_PSR2_CTL 0x6f900 +#define EDP_PSR2_ENABLE (1<<31) +#define EDP_SU_TRACK_ENABLE (1<<30) +#define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20) +#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20) +#define EDP_PSR2_TP2_TIME_500 (0<<8) +#define EDP_PSR2_TP2_TIME_100 (1<<8) +#define EDP_PSR2_TP2_TIME_2500 (2<<8) +#define EDP_PSR2_TP2_TIME_50 (3<<8) +#define EDP_PSR2_TP2_TIME_MASK (3<<8) +#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 +#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) +#define EDP_PSR2_IDLE_MASK 0xf + /* VGA port control */ #define ADPA 0x61100 #define PCH_ADPA 0xe1100 diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7936155acbe8..a651dba7fb5a 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3785,6 +3785,21 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) dev_priv->psr.sink_support = true; DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); } + + if (INTEL_INFO(dev)->gen >= 9 && + (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { + uint8_t frame_sync_cap; + + dev_priv->psr.sink_support = true; + intel_dp_dpcd_read_wake(&intel_dp->aux, + DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, + &frame_sync_cap, 1); + dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; + /* PSR2 needs frame sync as well */ + dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; + DRM_DEBUG_KMS("PSR2 %s on sink", + dev_priv->psr.psr2_support ? "supported" : "not supported"); + } } /* Training Pattern 3 support, both source and sink */ diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 9668735fce52..27608ce19b1c 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -117,6 +117,19 @@ static void vlv_psr_setup_vsc(struct intel_dp *intel_dp) I915_WRITE(VLV_VSCSDP(pipe), val); } +static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp) +{ + struct edp_vsc_psr psr_vsc; + + /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ + memset(&psr_vsc, 0, sizeof(psr_vsc)); + psr_vsc.sdp_header.HB0 = 0; + psr_vsc.sdp_header.HB1 = 0x7; + psr_vsc.sdp_header.HB2 = 0x3; + psr_vsc.sdp_header.HB3 = 0xb; + intel_psr_write_vsc(intel_dp, &psr_vsc); +} + static void hsw_psr_setup_vsc(struct intel_dp *intel_dp) { struct edp_vsc_psr psr_vsc; @@ -165,6 +178,12 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); + /* Enable AUX frame sync at sink */ + if (dev_priv->psr.aux_frame_sync) + drm_dp_dpcd_writeb(&intel_dp->aux, + DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, + DP_AUX_FRAME_SYNC_ENABLE); + aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ? DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev); aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ? @@ -183,8 +202,10 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) val |= DP_AUX_CH_CTL_TIME_OUT_1600us; val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK; val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); - /* Use hardcoded data values for PSR */ + /* Use hardcoded data values for PSR, frame sync and GTC */ val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL; + val &= ~DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL; + val &= ~DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL; I915_WRITE(aux_ctl_reg, val); } else { I915_WRITE(aux_ctl_reg, @@ -232,6 +253,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t max_sleep_time = 0x1f; /* Lately it was identified that depending on panel idle frame count * calculated at HW can be off by 1. So let's use what came @@ -255,6 +277,10 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | EDP_PSR_ENABLE); + + if (dev_priv->psr.psr2_support) + I915_WRITE(EDP_PSR2_CTL, EDP_PSR2_ENABLE | + EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100); } static bool intel_psr_match_conditions(struct intel_dp *intel_dp) @@ -332,6 +358,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = intel_dig_port->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); if (!HAS_PSR(dev)) { DRM_DEBUG_KMS("PSR not supported on this platform\n"); @@ -364,6 +391,15 @@ void intel_psr_enable(struct intel_dp *intel_dp) if (HAS_DDI(dev)) { hsw_psr_setup_vsc(intel_dp); + if (dev_priv->psr.psr2_support) { + /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */ + if (crtc->config->pipe_src_w > 3200 || + crtc->config->pipe_src_h > 2000) + dev_priv->psr.psr2_support = false; + else + skl_psr_setup_su_vsc(intel_dp); + } + /* Avoid continuous PSR exit by masking memup and hpd */ I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); -- cgit v1.2.3 From 51ce4db1749028b89a1f4a70bfa78b77df8795e7 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Tue, 31 Mar 2015 16:03:21 -0700 Subject: drm/i915/bdw: WaProgramL3SqcReg1Default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Program the default initial value of the L3SqcReg1 on BDW for performance v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out. v3: Spec shows now a different value. It tells us to set to 0x784000 instead the 0x610000 that is there already. Also rebased after a long time so using WA_WRITE now. Cc: Mika Kuoppala Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 2 files changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8db2a9169266..9966d3294a02 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5336,6 +5336,9 @@ enum skl_disp_power_wells { #define GEN7_L3SQCREG1 0xB010 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 +#define GEN8_L3SQCREG1 0xB100 +#define BDW_WA_L3SQCREG1_DEFAULT 0x784000 + #define GEN7_L3CNTLREG1 0xB01C #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C #define GEN7_L3AGDIS (1<<19) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a26bdf89e270..b5af9b121ce1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4); + /* WaProgramL3SqcReg1Default:bdw */ + WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); + return 0; } -- cgit v1.2.3 From aa7471d228eb6dfddd0d201ea9746d6a2020972a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 1 Apr 2015 11:15:21 +0300 Subject: drm/i915: add i915 specific connector debugfs file for DPCD Occasionally it would be interesting to read some of the DPCD registers for debug purposes, without having to resort to logging. Add an i915 specific i915_dpcd debugfs file for DP and eDP connectors to dump parts of the DPCD. Currently the DPCD addresses to be dumped are statically configured, and more can be added trivially. The implementation also makes it relatively easy to add other i915 and connector specific debugfs files in the future, as necessary. This is currently i915 specific just because there's no generic way to do AUX transactions given just a drm_connector. However it's all pretty straightforward to port to other drivers. v2: Add more DPCD registers to dump. Signed-off-by: Jani Nikula Reviewed-by: Bob Paauwe Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 96 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_dp.c | 2 + 3 files changed, 99 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 91c945b6a762..10ca5117fcee 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4793,3 +4793,99 @@ void i915_debugfs_cleanup(struct drm_minor *minor) drm_debugfs_remove_files(info_list, 1, minor); } } + +struct dpcd_block { + /* DPCD dump start address. */ + unsigned int offset; + /* DPCD dump end address, inclusive. If unset, .size will be used. */ + unsigned int end; + /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ + size_t size; + /* Only valid for eDP. */ + bool edp; +}; + +static const struct dpcd_block i915_dpcd_debug[] = { + { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, + { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, + { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, + { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, + { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, + { .offset = DP_SET_POWER }, + { .offset = DP_EDP_DPCD_REV }, + { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, + { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, + { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, +}; + +static int i915_dpcd_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + struct intel_dp *intel_dp = + enc_to_intel_dp(&intel_attached_encoder(connector)->base); + uint8_t buf[16]; + ssize_t err; + int i; + + for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { + const struct dpcd_block *b = &i915_dpcd_debug[i]; + size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); + + if (b->edp && + connector->connector_type != DRM_MODE_CONNECTOR_eDP) + continue; + + /* low tech for now */ + if (WARN_ON(size > sizeof(buf))) + continue; + + err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); + if (err <= 0) { + DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", + size, b->offset, err); + continue; + } + + seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); + }; + + return 0; +} + +static int i915_dpcd_open(struct inode *inode, struct file *file) +{ + return single_open(file, i915_dpcd_show, inode->i_private); +} + +static const struct file_operations i915_dpcd_fops = { + .owner = THIS_MODULE, + .open = i915_dpcd_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +/** + * i915_debugfs_connector_add - add i915 specific connector debugfs files + * @connector: pointer to a registered drm_connector + * + * Cleanup will be done by drm_connector_unregister() through a call to + * drm_debugfs_connector_remove(). + * + * Returns 0 on success, negative error codes on error. + */ +int i915_debugfs_connector_add(struct drm_connector *connector) +{ + struct dentry *root = connector->debugfs_entry; + + /* The connector must have been registered beforehands. */ + if (!root) + return -ENODEV; + + if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || + connector->connector_type == DRM_MODE_CONNECTOR_eDP) + debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, + &i915_dpcd_fops); + + return 0; +} diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1d62fbe3fcc0..4fd38f2e6e62 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3007,6 +3007,7 @@ int i915_verify_lists(struct drm_device *dev); /* i915_debugfs.c */ int i915_debugfs_init(struct drm_minor *minor); void i915_debugfs_cleanup(struct drm_minor *minor); +int i915_debugfs_connector_add(struct drm_connector *connector); #ifdef CONFIG_DEBUG_FS void intel_display_crc_init(struct drm_device *dev); #else diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a651dba7fb5a..1b87969536ff 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5584,6 +5584,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); } + i915_debugfs_connector_add(connector); + return true; } -- cgit v1.2.3 From 1347f5b46a270db1991625f9f57af91e23a4b512 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 17 Mar 2015 11:39:27 +0200 Subject: drm/i915/bxt: Add BXT PCI ids MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: Switch to info->ring_mask and add VEBOX support. v3: Fold in update from Damien. v4: Add GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS v5: set no-LLC (imre) Signed-off-by: Damien Lespiau (v1,v4) Signed-off-by: Daniel Vetter (v4) Signed-off-by: Imre Deak Reviewed-by: Antti Koskipää Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 14 +++++++++++++- include/drm/i915_pciids.h | 6 ++++++ 2 files changed, 19 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 82f8be4b6745..4d5078550e0b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -381,6 +381,17 @@ static const struct intel_device_info intel_skylake_gt3_info = { IVB_CURSOR_OFFSETS, }; +static const struct intel_device_info intel_broxton_info = { + .is_preliminary = 1, + .gen = 9, + .need_gfx_hws = 1, .has_hotplug = 1, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .num_pipes = 3, + .has_ddi = 1, + GEN_DEFAULT_PIPEOFFSETS, + IVB_CURSOR_OFFSETS, +}; + /* * Make sure any device matches here are from most specific to most * general. For example, since the Quanta match is based on the subsystem @@ -420,7 +431,8 @@ static const struct intel_device_info intel_skylake_gt3_info = { INTEL_CHV_IDS(&intel_cherryview_info), \ INTEL_SKL_GT1_IDS(&intel_skylake_info), \ INTEL_SKL_GT2_IDS(&intel_skylake_info), \ - INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info) \ + INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \ + INTEL_BXT_IDS(&intel_broxton_info) static const struct pci_device_id pciidlist[] = { /* aka */ INTEL_PCI_IDS, diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 613372375ada..bd0d644d2a03 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -287,4 +287,10 @@ INTEL_SKL_GT3_IDS(info) +#define INTEL_BXT_IDS(info) \ + INTEL_VGA_DEVICE(0x0A84, info), \ + INTEL_VGA_DEVICE(0x0A85, info), \ + INTEL_VGA_DEVICE(0x0A86, info), \ + INTEL_VGA_DEVICE(0x0A87, info) + #endif /* _I915_PCIIDS_H */ -- cgit v1.2.3 From ce89db2eabb0979e823aed38d5f5b22512d06392 Mon Sep 17 00:00:00 2001 From: Daisy Sun Date: Tue, 17 Mar 2015 11:39:28 +0200 Subject: drm/i915/bxt: BXT FBC enablement MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable FBC feature on Broxton Issue: VIZ-3784 Signed-off-by: Daisy Sun Signed-off-by: Damien Lespiau Reviewed-by: Antti Koskipää Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4d5078550e0b..48434cb6898d 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -388,6 +388,7 @@ static const struct intel_device_info intel_broxton_info = { .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_pipes = 3, .has_ddi = 1, + .has_fbc = 1, GEN_DEFAULT_PIPEOFFSETS, IVB_CURSOR_OFFSETS, }; -- cgit v1.2.3 From 46ec15f2662b48103751ea059d2cb4e2571bad5e Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 26 Mar 2015 17:35:40 +0200 Subject: drm/i915: use proper FBC base register on all new platforms MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Starting from GEN5 the FBC base register is the same on all platforms. GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make things work on BXT as well. Motivated by Rodrigo's request to check FBC support on BXT. Signed-off-by: Imre Deak Reviewed-by: Antti Koskipää Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index f8da71682c96..348ed5abcdbf 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -209,7 +209,7 @@ static int i915_setup_compression(struct drm_device *dev, int size, int fb_cpp) dev_priv->fbc.threshold = ret; - if (HAS_PCH_SPLIT(dev)) + if (INTEL_INFO(dev_priv)->gen >= 5) I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); else if (IS_GM45(dev)) { I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); -- cgit v1.2.3 From 1feed8855d168482bb9e6faa0ba0f1f257e62514 Mon Sep 17 00:00:00 2001 From: Satheeshakrishna M Date: Tue, 17 Mar 2015 11:39:29 +0200 Subject: drm/i915/bxt: Add IS_BROXTON macro Adding IS_BROXTON macro for broxton specific implementation. Signed-off-by: Satheeshakrishna M Signed-off-by: Damien Lespiau Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e326ac9730cf..8341f0f2299f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2306,6 +2306,7 @@ struct drm_i915_cmd_table { #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) +#define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev)) #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) -- cgit v1.2.3 From 5a4e33a34fc27d6b54200bde187766e049ae876b Mon Sep 17 00:00:00 2001 From: Sumit Singh Date: Tue, 17 Mar 2015 11:39:31 +0200 Subject: drm/i915/bxt: Enable PTE encoding The caching options for page table entries have remained the same as Cherryview. This patch fixes it so the right code path is taken on BXT. v2: Fix up commit message (Mike) Signed-off-by: Sumit Singh Signed-off-by: Damien Lespiau Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 0239fbff7bf7..22ad9c388121 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1687,7 +1687,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) if (INTEL_INFO(dev)->gen >= 8) { - if (IS_CHERRYVIEW(dev)) + if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) chv_setup_private_ppat(dev_priv); else bdw_setup_private_ppat(dev_priv); @@ -2375,7 +2375,7 @@ static int gen8_gmch_probe(struct drm_device *dev, *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; - if (IS_CHERRYVIEW(dev)) + if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) chv_setup_private_ppat(dev_priv); else bdw_setup_private_ppat(dev_priv); -- cgit v1.2.3 From 8fb9397dafadacd8d3ae21a3f5ac3c473adfe6d4 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 17 Mar 2015 11:39:32 +0200 Subject: drm/i915/bxt: Broxton has 3 sprite planes on pipe A/B, 2 on pipe C v2: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. Signed-off-by: Damien Lespiau Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_dma.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 68e0c85a17cf..ec661fe44e70 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -585,7 +585,11 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info = (struct intel_device_info *)&dev_priv->info; - if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9) + if (IS_BROXTON(dev)) { + info->num_sprites[PIPE_A] = 3; + info->num_sprites[PIPE_B] = 3; + info->num_sprites[PIPE_C] = 2; + } else if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9) for_each_pipe(dev_priv, pipe) info->num_sprites[pipe] = 2; else -- cgit v1.2.3 From b21249c90e7ad8fce2234df98555c80c5f828c4f Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 17 Mar 2015 11:39:33 +0200 Subject: drm/i915/bxt: Add the plane4 related interrupt definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Damien Lespiau Reviewed-by: Antti Koskipää Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b522eb6e59a4..7e1a0fd9333f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5218,9 +5218,11 @@ enum skl_disp_power_wells { #define GEN8_PIPE_VSYNC (1 << 1) #define GEN8_PIPE_VBLANK (1 << 0) #define GEN9_PIPE_CURSOR_FAULT (1 << 11) +#define GEN9_PIPE_PLANE4_FAULT (1 << 10) #define GEN9_PIPE_PLANE3_FAULT (1 << 9) #define GEN9_PIPE_PLANE2_FAULT (1 << 8) #define GEN9_PIPE_PLANE1_FAULT (1 << 7) +#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) @@ -5231,6 +5233,7 @@ enum skl_disp_power_wells { GEN8_PIPE_PRIMARY_FAULT) #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ (GEN9_PIPE_CURSOR_FAULT | \ + GEN9_PIPE_PLANE4_FAULT | \ GEN9_PIPE_PLANE3_FAULT | \ GEN9_PIPE_PLANE2_FAULT | \ GEN9_PIPE_PLANE1_FAULT) -- cgit v1.2.3 From 43d735a686d03033599187c276071eceb32d52dd Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 17 Mar 2015 11:39:34 +0200 Subject: drm/i915/bxt: Broxton DDB is 512 blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Damien Lespiau Reviewed-by: Antti Koskipää Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fa4ccb346389..1e25e3e26a67 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2538,6 +2538,7 @@ static bool ilk_disable_lp_wm(struct drm_device *dev) */ #define SKL_DDB_SIZE 896 /* in blocks */ +#define BXT_DDB_SIZE 512 static void skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, @@ -2556,7 +2557,10 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, return; } - ddb_size = SKL_DDB_SIZE; + if (IS_BROXTON(dev)) + ddb_size = BXT_DDB_SIZE; + else + ddb_size = SKL_DDB_SIZE; ddb_size -= 4; /* 4 blocks for bypass path allocation */ -- cgit v1.2.3 From 8232edb5f74af0f4664362fefab165e891a7fa68 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 17 Mar 2015 11:39:35 +0200 Subject: drm/i915/bxt: Broxton raises the maximum number of planes to 4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pipe A and b have 4 planes. Signed-off-by: Damien Lespiau Reviewed-by: Antti Koskipää Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 8341f0f2299f..2d402e49f7fd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -130,7 +130,7 @@ enum transcoder { * * This value doesn't count the cursor plane. */ -#define I915_MAX_PLANES 3 +#define I915_MAX_PLANES 4 enum plane { PLANE_A = 0, -- cgit v1.2.3 From 2a073f89435771409a21930b78f182d8cb5c5941 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 27 Mar 2015 13:07:33 +0200 Subject: drm/i915/bxt: map GTT as uncached MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Broxton per specification the GTT has to be mapped as uncached. This was caught by the PTE write readback warning, which showed a corrupted PTE value with using the current write-combine mapping. v2: - add comment explaining how the problem with WC mapping manifests (Daniel) Signed-off-by: Imre Deak Reviewed-by: Antti Koskipää Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 22ad9c388121..f48d8454f0ef 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2253,7 +2253,17 @@ static int ggtt_probe_common(struct drm_device *dev, gtt_phys_addr = pci_resource_start(dev->pdev, 0) + (pci_resource_len(dev->pdev, 0) / 2); - dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); + /* + * On BXT writes larger than 64 bit to the GTT pagetable range will be + * dropped. For WC mappings in general we have 64 byte burst writes + * when the WC buffer is flushed, so we can't use it, but have to + * resort to an uncached mapping. The WC issue is easily caught by the + * readback check when writing GTT PTE entries. + */ + if (IS_BROXTON(dev)) + dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size); + else + dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); if (!dev_priv->gtt.gsm) { DRM_ERROR("Failed to map the gtt page table\n"); return -ENOMEM; -- cgit v1.2.3 From cae0437f7a367594cb0abc17ddf337c6b2669fab Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Tue, 17 Mar 2015 11:39:38 +0200 Subject: drm/i915/bxt: HardWare WorkAround ring initialisation for Broxton Adds framework for Broxton HW WAs Signed-off-by: Nick Hoath Signed-off-by: Imre Deak Reviewed-by: Nick Hoath Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 441e2502b889..abe062a95be8 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1027,6 +1027,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) return skl_tune_iz_hashing(ring); } +static int bxt_init_workarounds(struct intel_engine_cs *ring) +{ + gen9_init_workarounds(ring); + + return 0; +} + int init_workarounds_ring(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; @@ -1044,8 +1051,9 @@ int init_workarounds_ring(struct intel_engine_cs *ring) if (IS_SKYLAKE(dev)) return skl_init_workarounds(ring); - else if (IS_GEN9(dev)) - return gen9_init_workarounds(ring); + + if (IS_BROXTON(dev)) + return bxt_init_workarounds(ring); return 0; } -- cgit v1.2.3 From 6c74c87f7cc94e71960e5a1044c1b26f68f7d3c8 Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Fri, 20 Mar 2015 09:03:52 +0000 Subject: drm/i915/bxt: Add Broxton steppings Signed-off-by: Nick Hoath Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2d402e49f7fd..99facbf86043 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2331,6 +2331,10 @@ struct drm_i915_cmd_table { #define SKL_REVID_D0 (0x3) #define SKL_REVID_E0 (0x4) +#define BXT_REVID_A0 (0x0) +#define BXT_REVID_B0 (0x3) +#define BXT_REVID_C0 (0x6) + /* * The genX designation typically refers to the render engine, so render * capability related checks should use IS_GEN, while display and other checks -- cgit v1.2.3 From 3449ca859a2ea8466b58794b256892508ea0c1b0 Mon Sep 17 00:00:00 2001 From: Vandana Kannan Date: Fri, 27 Mar 2015 14:19:09 +0200 Subject: drm/i915/bxt: Increase DDI buf idle timeout For BXT, DDI buf idle timeout delay needs to be increased to 16us. Since this is a timeout value and we return as soon as the condition is realized, no penalty incurred for other platforms. v2: - remove TIMEOUT macro used only at a single place (Daniel) Suggested-by: Satheeshakrishna M Cc: Satheeshakrishna M Cc: Damien Lespiau Signed-off-by: Vandana Kannan Signed-off-by: Damien Lespiau (v1) Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 47b9307da24b..1c9d439e864a 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -322,7 +322,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, uint32_t reg = DDI_BUF_CTL(port); int i; - for (i = 0; i < 8; i++) { + for (i = 0; i < 16; i++) { udelay(1); if (I915_READ(reg) & DDI_BUF_IS_IDLE) return; -- cgit v1.2.3 From 9705ad8a9684c5b4952263821e07929ca3856fd1 Mon Sep 17 00:00:00 2001 From: Jeff McGee Date: Fri, 3 Apr 2015 18:13:15 -0700 Subject: drm/i915: Split SSEU init into functions by platform Signed-off-by: Jeff McGee Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_dma.c | 234 +++++++++++++++++++++------------------- 1 file changed, 125 insertions(+), 109 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index ec661fe44e70..9691f0fc0918 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -564,6 +564,127 @@ static void i915_dump_device_info(struct drm_i915_private *dev_priv) #undef SEP_COMMA } +static void cherryview_sseu_info_init(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_device_info *info; + u32 fuse, eu_dis; + + info = (struct intel_device_info *)&dev_priv->info; + fuse = I915_READ(CHV_FUSE_GT); + + info->slice_total = 1; + + if (!(fuse & CHV_FGT_DISABLE_SS0)) { + info->subslice_per_slice++; + eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | + CHV_FGT_EU_DIS_SS0_R1_MASK); + info->eu_total += 8 - hweight32(eu_dis); + } + + if (!(fuse & CHV_FGT_DISABLE_SS1)) { + info->subslice_per_slice++; + eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | + CHV_FGT_EU_DIS_SS1_R1_MASK); + info->eu_total += 8 - hweight32(eu_dis); + } + + info->subslice_total = info->subslice_per_slice; + /* + * CHV expected to always have a uniform distribution of EU + * across subslices. + */ + info->eu_per_subslice = info->subslice_total ? + info->eu_total / info->subslice_total : + 0; + /* + * CHV supports subslice power gating on devices with more than + * one subslice, and supports EU power gating on devices with + * more than one EU pair per subslice. + */ + info->has_slice_pg = 0; + info->has_subslice_pg = (info->subslice_total > 1); + info->has_eu_pg = (info->eu_per_subslice > 2); +} + +static void gen9_sseu_info_init(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_device_info *info; + const int s_max = 3, ss_max = 4, eu_max = 8; + int s, ss; + u32 fuse2, eu_disable[s_max], s_enable, ss_disable; + + info = (struct intel_device_info *)&dev_priv->info; + fuse2 = I915_READ(GEN8_FUSE2); + s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> + GEN8_F2_S_ENA_SHIFT; + ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> + GEN9_F2_SS_DIS_SHIFT; + + eu_disable[0] = I915_READ(GEN8_EU_DISABLE0); + eu_disable[1] = I915_READ(GEN8_EU_DISABLE1); + eu_disable[2] = I915_READ(GEN8_EU_DISABLE2); + + info->slice_total = hweight32(s_enable); + /* + * The subslice disable field is global, i.e. it applies + * to each of the enabled slices. + */ + info->subslice_per_slice = ss_max - hweight32(ss_disable); + info->subslice_total = info->slice_total * + info->subslice_per_slice; + + /* + * Iterate through enabled slices and subslices to + * count the total enabled EU. + */ + for (s = 0; s < s_max; s++) { + if (!(s_enable & (0x1 << s))) + /* skip disabled slice */ + continue; + + for (ss = 0; ss < ss_max; ss++) { + u32 n_disabled; + + if (ss_disable & (0x1 << ss)) + /* skip disabled subslice */ + continue; + + n_disabled = hweight8(eu_disable[s] >> + (ss * eu_max)); + + /* + * Record which subslice(s) has(have) 7 EUs. we + * can tune the hash used to spread work among + * subslices if they are unbalanced. + */ + if (eu_max - n_disabled == 7) + info->subslice_7eu[s] |= 1 << ss; + + info->eu_total += eu_max - n_disabled; + } + } + + /* + * SKL is expected to always have a uniform distribution + * of EU across subslices with the exception that any one + * EU in any one subslice may be fused off for die + * recovery. + */ + info->eu_per_subslice = info->subslice_total ? + DIV_ROUND_UP(info->eu_total, + info->subslice_total) : 0; + /* + * SKL supports slice power gating on devices with more than + * one slice, and supports EU power gating on devices with + * more than one EU pair per subslice. + */ + info->has_slice_pg = (info->slice_total > 1) ? 1 : 0; + info->has_subslice_pg = 0; + info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0; +} + /* * Determine various intel_device_info fields at runtime. * @@ -624,116 +745,11 @@ static void intel_device_info_runtime_init(struct drm_device *dev) } /* Initialize slice/subslice/EU info */ - if (IS_CHERRYVIEW(dev)) { - u32 fuse, eu_dis; - - fuse = I915_READ(CHV_FUSE_GT); + if (IS_CHERRYVIEW(dev)) + cherryview_sseu_info_init(dev); + else if (IS_SKYLAKE(dev)) + gen9_sseu_info_init(dev); - info->slice_total = 1; - - if (!(fuse & CHV_FGT_DISABLE_SS0)) { - info->subslice_per_slice++; - eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | - CHV_FGT_EU_DIS_SS0_R1_MASK); - info->eu_total += 8 - hweight32(eu_dis); - } - - if (!(fuse & CHV_FGT_DISABLE_SS1)) { - info->subslice_per_slice++; - eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | - CHV_FGT_EU_DIS_SS1_R1_MASK); - info->eu_total += 8 - hweight32(eu_dis); - } - - info->subslice_total = info->subslice_per_slice; - /* - * CHV expected to always have a uniform distribution of EU - * across subslices. - */ - info->eu_per_subslice = info->subslice_total ? - info->eu_total / info->subslice_total : - 0; - /* - * CHV supports subslice power gating on devices with more than - * one subslice, and supports EU power gating on devices with - * more than one EU pair per subslice. - */ - info->has_slice_pg = 0; - info->has_subslice_pg = (info->subslice_total > 1); - info->has_eu_pg = (info->eu_per_subslice > 2); - } else if (IS_SKYLAKE(dev)) { - const int s_max = 3, ss_max = 4, eu_max = 8; - int s, ss; - u32 fuse2, eu_disable[s_max], s_enable, ss_disable; - - fuse2 = I915_READ(GEN8_FUSE2); - s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> - GEN8_F2_S_ENA_SHIFT; - ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> - GEN9_F2_SS_DIS_SHIFT; - - eu_disable[0] = I915_READ(GEN8_EU_DISABLE0); - eu_disable[1] = I915_READ(GEN8_EU_DISABLE1); - eu_disable[2] = I915_READ(GEN8_EU_DISABLE2); - - info->slice_total = hweight32(s_enable); - /* - * The subslice disable field is global, i.e. it applies - * to each of the enabled slices. - */ - info->subslice_per_slice = ss_max - hweight32(ss_disable); - info->subslice_total = info->slice_total * - info->subslice_per_slice; - - /* - * Iterate through enabled slices and subslices to - * count the total enabled EU. - */ - for (s = 0; s < s_max; s++) { - if (!(s_enable & (0x1 << s))) - /* skip disabled slice */ - continue; - - for (ss = 0; ss < ss_max; ss++) { - u32 n_disabled; - - if (ss_disable & (0x1 << ss)) - /* skip disabled subslice */ - continue; - - n_disabled = hweight8(eu_disable[s] >> - (ss * eu_max)); - - /* - * Record which subslice(s) has(have) 7 EUs. we - * can tune the hash used to spread work among - * subslices if they are unbalanced. - */ - if (eu_max - n_disabled == 7) - info->subslice_7eu[s] |= 1 << ss; - - info->eu_total += eu_max - n_disabled; - } - } - - /* - * SKL is expected to always have a uniform distribution - * of EU across subslices with the exception that any one - * EU in any one subslice may be fused off for die - * recovery. - */ - info->eu_per_subslice = info->subslice_total ? - DIV_ROUND_UP(info->eu_total, - info->subslice_total) : 0; - /* - * SKL supports slice power gating on devices with more than - * one slice, and supports EU power gating on devices with - * more than one EU pair per subslice. - */ - info->has_slice_pg = (info->slice_total > 1) ? 1 : 0; - info->has_subslice_pg = 0; - info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0; - } DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total); DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total); DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice); -- cgit v1.2.3 From dead16e2c34343f0e12ee71cd50c9398440e2556 Mon Sep 17 00:00:00 2001 From: Jeff McGee Date: Fri, 3 Apr 2015 18:13:16 -0700 Subject: drm/i915/bxt: Determine BXT slice/subslice/EU info Modify the Gen9 SSEU info initialization logic to support Broxton. Broxton reuses the SKL fuse registers but has at most 1 slice and 6 EU per subslice. Signed-off-by: Jeff McGee Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_dma.c | 47 ++++++++++++++++++++++++++--------------- drivers/gpu/drm/i915/i915_reg.h | 4 +--- 2 files changed, 31 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 9691f0fc0918..a9b7770dc480 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -611,9 +611,21 @@ static void gen9_sseu_info_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_device_info *info; - const int s_max = 3, ss_max = 4, eu_max = 8; + int s_max = 3, ss_max = 4, eu_max = 8; int s, ss; - u32 fuse2, eu_disable[s_max], s_enable, ss_disable; + u32 fuse2, s_enable, ss_disable, eu_disable; + u8 eu_mask = 0xff; + + /* + * BXT has a single slice. BXT also has at most 6 EU per subslice, + * and therefore only the lowest 6 bits of the 8-bit EU disable + * fields are valid. + */ + if (IS_BROXTON(dev)) { + s_max = 1; + eu_max = 6; + eu_mask = 0x3f; + } info = (struct intel_device_info *)&dev_priv->info; fuse2 = I915_READ(GEN8_FUSE2); @@ -622,10 +634,6 @@ static void gen9_sseu_info_init(struct drm_device *dev) ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> GEN9_F2_SS_DIS_SHIFT; - eu_disable[0] = I915_READ(GEN8_EU_DISABLE0); - eu_disable[1] = I915_READ(GEN8_EU_DISABLE1); - eu_disable[2] = I915_READ(GEN8_EU_DISABLE2); - info->slice_total = hweight32(s_enable); /* * The subslice disable field is global, i.e. it applies @@ -644,25 +652,26 @@ static void gen9_sseu_info_init(struct drm_device *dev) /* skip disabled slice */ continue; + eu_disable = I915_READ(GEN9_EU_DISABLE(s)); for (ss = 0; ss < ss_max; ss++) { - u32 n_disabled; + int eu_per_ss; if (ss_disable & (0x1 << ss)) /* skip disabled subslice */ continue; - n_disabled = hweight8(eu_disable[s] >> - (ss * eu_max)); + eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) & + eu_mask); /* * Record which subslice(s) has(have) 7 EUs. we * can tune the hash used to spread work among * subslices if they are unbalanced. */ - if (eu_max - n_disabled == 7) + if (eu_per_ss == 7) info->subslice_7eu[s] |= 1 << ss; - info->eu_total += eu_max - n_disabled; + info->eu_total += eu_per_ss; } } @@ -670,7 +679,8 @@ static void gen9_sseu_info_init(struct drm_device *dev) * SKL is expected to always have a uniform distribution * of EU across subslices with the exception that any one * EU in any one subslice may be fused off for die - * recovery. + * recovery. BXT is expected to be perfectly uniform in EU + * distribution. */ info->eu_per_subslice = info->subslice_total ? DIV_ROUND_UP(info->eu_total, @@ -678,11 +688,14 @@ static void gen9_sseu_info_init(struct drm_device *dev) /* * SKL supports slice power gating on devices with more than * one slice, and supports EU power gating on devices with - * more than one EU pair per subslice. + * more than one EU pair per subslice. BXT supports subslice + * power gating on devices with more than one subslice, and + * supports EU power gating on devices with more than one EU + * pair per subslice. */ - info->has_slice_pg = (info->slice_total > 1) ? 1 : 0; - info->has_subslice_pg = 0; - info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0; + info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1)); + info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); + info->has_eu_pg = (info->eu_per_subslice > 2); } /* @@ -747,7 +760,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev) /* Initialize slice/subslice/EU info */ if (IS_CHERRYVIEW(dev)) cherryview_sseu_info_init(dev); - else if (IS_SKYLAKE(dev)) + else if (INTEL_INFO(dev)->gen >= 9) gen9_sseu_info_init(dev); DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7e1a0fd9333f..7eda205d5e87 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1554,9 +1554,7 @@ enum skl_disp_power_wells { #define GEN9_F2_SS_DIS_SHIFT 20 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) -#define GEN8_EU_DISABLE0 0x9134 -#define GEN8_EU_DISABLE1 0x9138 -#define GEN8_EU_DISABLE2 0x913c +#define GEN9_EU_DISABLE(slice) (0x9134 + (slice)*0x4) #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) -- cgit v1.2.3 From 5d39525a1f2551a33f7f7380a038837e648ed511 Mon Sep 17 00:00:00 2001 From: Jeff McGee Date: Fri, 3 Apr 2015 18:13:17 -0700 Subject: drm/i915: Split-up SSEU device status by platform Signed-off-by: Jeff McGee Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 172 +++++++++++++++++++++--------------- 1 file changed, 100 insertions(+), 72 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 007c7d7d8295..8facc0045f95 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4470,12 +4470,97 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, i915_cache_sharing_get, i915_cache_sharing_set, "%llu\n"); +struct sseu_dev_status { + unsigned int slice_total; + unsigned int subslice_total; + unsigned int subslice_per_slice; + unsigned int eu_total; + unsigned int eu_per_subslice; +}; + +static void cherryview_sseu_device_status(struct drm_device *dev, + struct sseu_dev_status *stat) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + const int ss_max = 2; + int ss; + u32 sig1[ss_max], sig2[ss_max]; + + sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); + sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); + sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); + sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); + + for (ss = 0; ss < ss_max; ss++) { + unsigned int eu_cnt; + + if (sig1[ss] & CHV_SS_PG_ENABLE) + /* skip disabled subslice */ + continue; + + stat->slice_total = 1; + stat->subslice_per_slice++; + eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + + ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + + ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + + ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); + stat->eu_total += eu_cnt; + stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); + } + stat->subslice_total = stat->subslice_per_slice; +} + +static void gen9_sseu_device_status(struct drm_device *dev, + struct sseu_dev_status *stat) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + const int s_max = 3, ss_max = 4; + int s, ss; + u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; + + s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK); + s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK); + s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK); + eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK); + eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK); + eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK); + eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK); + eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK); + eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK); + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | + GEN9_PGCTL_SSA_EU19_ACK | + GEN9_PGCTL_SSA_EU210_ACK | + GEN9_PGCTL_SSA_EU311_ACK; + eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | + GEN9_PGCTL_SSB_EU19_ACK | + GEN9_PGCTL_SSB_EU210_ACK | + GEN9_PGCTL_SSB_EU311_ACK; + + for (s = 0; s < s_max; s++) { + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) + /* skip disabled slice */ + continue; + + stat->slice_total++; + stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; + stat->subslice_total += stat->subslice_per_slice; + for (ss = 0; ss < ss_max; ss++) { + unsigned int eu_cnt; + + eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & + eu_mask[ss%2]); + stat->eu_total += eu_cnt; + stat->eu_per_subslice = max(stat->eu_per_subslice, + eu_cnt); + } + } +} + static int i915_sseu_status(struct seq_file *m, void *unused) { struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_device *dev = node->minor->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0; + struct sseu_dev_status stat; if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev)) return -ENODEV; @@ -4499,79 +4584,22 @@ static int i915_sseu_status(struct seq_file *m, void *unused) yesno(INTEL_INFO(dev)->has_eu_pg)); seq_puts(m, "SSEU Device Status\n"); + memset(&stat, 0, sizeof(stat)); if (IS_CHERRYVIEW(dev)) { - const int ss_max = 2; - int ss; - u32 sig1[ss_max], sig2[ss_max]; - - sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); - sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); - sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); - sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); - - for (ss = 0; ss < ss_max; ss++) { - unsigned int eu_cnt; - - if (sig1[ss] & CHV_SS_PG_ENABLE) - /* skip disabled subslice */ - continue; - - s_tot = 1; - ss_per++; - eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + - ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + - ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + - ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); - eu_tot += eu_cnt; - eu_per = max(eu_per, eu_cnt); - } - ss_tot = ss_per; + cherryview_sseu_device_status(dev, &stat); } else if (IS_SKYLAKE(dev)) { - const int s_max = 3, ss_max = 4; - int s, ss; - u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; - - s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK); - s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK); - s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK); - eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK); - eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK); - eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK); - eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK); - eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK); - eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK); - eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | - GEN9_PGCTL_SSA_EU19_ACK | - GEN9_PGCTL_SSA_EU210_ACK | - GEN9_PGCTL_SSA_EU311_ACK; - eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | - GEN9_PGCTL_SSB_EU19_ACK | - GEN9_PGCTL_SSB_EU210_ACK | - GEN9_PGCTL_SSB_EU311_ACK; - - for (s = 0; s < s_max; s++) { - if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) - /* skip disabled slice */ - continue; - - s_tot++; - ss_per = INTEL_INFO(dev)->subslice_per_slice; - ss_tot += ss_per; - for (ss = 0; ss < ss_max; ss++) { - unsigned int eu_cnt; - - eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & - eu_mask[ss%2]); - eu_tot += eu_cnt; - eu_per = max(eu_per, eu_cnt); - } - } + gen9_sseu_device_status(dev, &stat); } - seq_printf(m, " Enabled Slice Total: %u\n", s_tot); - seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot); - seq_printf(m, " Enabled Subslice Per Slice: %u\n", ss_per); - seq_printf(m, " Enabled EU Total: %u\n", eu_tot); - seq_printf(m, " Enabled EU Per Subslice: %u\n", eu_per); + seq_printf(m, " Enabled Slice Total: %u\n", + stat.slice_total); + seq_printf(m, " Enabled Subslice Total: %u\n", + stat.subslice_total); + seq_printf(m, " Enabled Subslice Per Slice: %u\n", + stat.subslice_per_slice); + seq_printf(m, " Enabled EU Total: %u\n", + stat.eu_total); + seq_printf(m, " Enabled EU Per Subslice: %u\n", + stat.eu_per_subslice); return 0; } -- cgit v1.2.3 From 1c046bc1db49e5a42e5c4167ac42cee4c1725a37 Mon Sep 17 00:00:00 2001 From: Jeff McGee Date: Fri, 3 Apr 2015 18:13:18 -0700 Subject: drm/i915/bxt: Support BXT in SSEU device status dump Modify the Gen9 SSEU device status logic to support Broxton. Broxton reuses the Skylake power gate acknowledgment registers but has at most 1 slice and 3 subslices. Broxton supports subslice power gating within its single slice. Signed-off-by: Jeff McGee Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 45 ++++++++++++++++++++++++++----------- drivers/gpu/drm/i915/i915_reg.h | 13 ++++------- 2 files changed, 36 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8facc0045f95..effb7fc14284 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4514,19 +4514,22 @@ static void gen9_sseu_device_status(struct drm_device *dev, struct sseu_dev_status *stat) { struct drm_i915_private *dev_priv = dev->dev_private; - const int s_max = 3, ss_max = 4; + int s_max = 3, ss_max = 4; int s, ss; u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; - s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK); - s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK); - s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK); - eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK); - eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK); - eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK); - eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK); - eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK); - eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK); + /* BXT has a single slice and at most 3 subslices. */ + if (IS_BROXTON(dev)) { + s_max = 1; + ss_max = 3; + } + + for (s = 0; s < s_max; s++) { + s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); + eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); + eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); + } + eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | GEN9_PGCTL_SSA_EU19_ACK | GEN9_PGCTL_SSA_EU210_ACK | @@ -4537,22 +4540,38 @@ static void gen9_sseu_device_status(struct drm_device *dev, GEN9_PGCTL_SSB_EU311_ACK; for (s = 0; s < s_max; s++) { + unsigned int ss_cnt = 0; + if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) /* skip disabled slice */ continue; stat->slice_total++; - stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; - stat->subslice_total += stat->subslice_per_slice; + + if (IS_SKYLAKE(dev)) + ss_cnt = INTEL_INFO(dev)->subslice_per_slice; + for (ss = 0; ss < ss_max; ss++) { unsigned int eu_cnt; + if (IS_BROXTON(dev) && + !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) + /* skip disabled subslice */ + continue; + + if (IS_BROXTON(dev)) + ss_cnt++; + eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & eu_mask[ss%2]); stat->eu_total += eu_cnt; stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); } + + stat->subslice_total += ss_cnt; + stat->subslice_per_slice = max(stat->subslice_per_slice, + ss_cnt); } } @@ -4587,7 +4606,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused) memset(&stat, 0, sizeof(stat)); if (IS_CHERRYVIEW(dev)) { cherryview_sseu_device_status(dev, &stat); - } else if (IS_SKYLAKE(dev)) { + } else if (INTEL_INFO(dev)->gen >= 9) { gen9_sseu_device_status(dev, &stat); } seq_printf(m, " Enabled Slice Total: %u\n", diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7eda205d5e87..6c1ec72e94c4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6269,17 +6269,12 @@ enum skl_disp_power_wells { #define CHV_POWER_SS1_SIG2 0xa72c #define CHV_EU311_PG_ENABLE (1<<1) -#define GEN9_SLICE0_PGCTL_ACK 0x804c -#define GEN9_SLICE1_PGCTL_ACK 0x8050 -#define GEN9_SLICE2_PGCTL_ACK 0x8054 +#define GEN9_SLICE_PGCTL_ACK(slice) (0x804c + (slice)*0x4) #define GEN9_PGCTL_SLICE_ACK (1 << 0) +#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2)) -#define GEN9_SLICE0_SS01_EU_PGCTL_ACK 0x805c -#define GEN9_SLICE0_SS23_EU_PGCTL_ACK 0x8060 -#define GEN9_SLICE1_SS01_EU_PGCTL_ACK 0x8064 -#define GEN9_SLICE1_SS23_EU_PGCTL_ACK 0x8068 -#define GEN9_SLICE2_SS01_EU_PGCTL_ACK 0x806c -#define GEN9_SLICE2_SS23_EU_PGCTL_ACK 0x8070 +#define GEN9_SS01_EU_PGCTL_ACK(slice) (0x805c + (slice)*0x8) +#define GEN9_SS23_EU_PGCTL_ACK(slice) (0x8060 + (slice)*0x8) #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) -- cgit v1.2.3 From ea9da4e4608104108c6d5eca7b178cec2720ab22 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 2 Apr 2015 10:35:08 +0100 Subject: drm/i915: Allow disabling the destination colorkey for overlay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sometimes userspace wants a true overlay that is never clipped. In such cases, we need to disable the destination colorkey. However, it is currently unconditionally enabled in the overlay with no means of disabling. So rectify that by always default to on, and extending the UPDATE_ATTR ioctl to support explicit disabling of the colorkey. This is contrast to the spite code which requires explicit enabling of either the destination or source colorkey. Handling source colorkey is still todo for the overlay. (Of course it may be worth migrating overlay to sprite before then.) Signed-off-by: Chris Wilson Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_overlay.c | 30 +++++++++++++++++++----------- include/uapi/drm/i915_drm.h | 1 + 2 files changed, 20 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index b291f1301c93..5fd2d5ac02e2 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -175,7 +175,8 @@ struct intel_overlay { bool active; bool pfit_active; u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ - u32 color_key; + u32 color_key:24; + u32 color_key_enabled:1; u32 brightness, contrast, saturation; u32 old_xscale, old_yscale; /* register access */ @@ -630,31 +631,36 @@ static void update_colorkey(struct intel_overlay *overlay, struct overlay_registers __iomem *regs) { u32 key = overlay->color_key; + u32 flags; + + flags = 0; + if (overlay->color_key_enabled) + flags |= DST_KEY_ENABLE; switch (overlay->crtc->base.primary->fb->bits_per_pixel) { case 8: - iowrite32(0, ®s->DCLRKV); - iowrite32(CLK_RGB8I_MASK | DST_KEY_ENABLE, ®s->DCLRKM); + key = 0; + flags |= CLK_RGB8I_MASK; break; case 16: if (overlay->crtc->base.primary->fb->depth == 15) { - iowrite32(RGB15_TO_COLORKEY(key), ®s->DCLRKV); - iowrite32(CLK_RGB15_MASK | DST_KEY_ENABLE, - ®s->DCLRKM); + key = RGB15_TO_COLORKEY(key); + flags |= CLK_RGB15_MASK; } else { - iowrite32(RGB16_TO_COLORKEY(key), ®s->DCLRKV); - iowrite32(CLK_RGB16_MASK | DST_KEY_ENABLE, - ®s->DCLRKM); + key = RGB16_TO_COLORKEY(key); + flags |= CLK_RGB16_MASK; } break; case 24: case 32: - iowrite32(key, ®s->DCLRKV); - iowrite32(CLK_RGB24_MASK | DST_KEY_ENABLE, ®s->DCLRKM); + flags |= CLK_RGB24_MASK; break; } + + iowrite32(key, ®s->DCLRKV); + iowrite32(flags, ®s->DCLRKM); } static u32 overlay_cmd_reg(struct put_image_params *params) @@ -1329,6 +1335,7 @@ int intel_overlay_attrs(struct drm_device *dev, void *data, I915_WRITE(OGAMC5, attrs->gamma5); } } + overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; ret = 0; out_unlock: @@ -1392,6 +1399,7 @@ void intel_setup_overlay(struct drm_device *dev) /* init all values */ overlay->color_key = 0x0101fe; + overlay->color_key_enabled = true; overlay->brightness = -19; overlay->contrast = 75; overlay->saturation = 146; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 551b6737f5df..4851d660243c 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -996,6 +996,7 @@ struct drm_intel_overlay_put_image { /* flags */ #define I915_OVERLAY_UPDATE_ATTRS (1<<0) #define I915_OVERLAY_UPDATE_GAMMA (1<<1) +#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) struct drm_intel_overlay_attrs { __u32 flags; __u32 color_key; -- cgit v1.2.3 From c929cb4524a304cb366854836ef7baf501ef6d06 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 2 Apr 2015 18:28:07 +0300 Subject: drm/i915: Silence a sparse warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ../drivers/gpu/drm/i915/intel_pm.c:3185:45: warning: Initializer entry defined twice ../drivers/gpu/drm/i915/intel_pm.c:3185:52: also defined here Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e1392e79c5c4..cd91407e1f93 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3178,7 +3178,7 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv, { struct drm_device *dev = dev_priv->dev; struct skl_ddb_allocation *cur_ddb, *new_ddb; - bool reallocated[I915_MAX_PIPES] = {false, false, false}; + bool reallocated[I915_MAX_PIPES] = {}; struct intel_crtc *crtc; enum pipe pipe; -- cgit v1.2.3 From 304603f47a7487309d5c450f438c59e92af2d93a Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Thu, 2 Apr 2015 14:47:56 +0300 Subject: drm/i915: Don't use staged config for VLV cdclk calculations Now that we use a drm atomic state for the legacy modeset, it is possible to get rid of the usage of intel_crtc->new_config in the function intel_mode_max_pixclk(). Signed-off-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 55 +++++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 84f5b417ad3c..a6cd8c7a64e9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5160,36 +5160,48 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, } /* compute the max pixel clock for new configuration */ -static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) +static int intel_mode_max_pixclk(struct drm_atomic_state *state) { - struct drm_device *dev = dev_priv->dev; + struct drm_device *dev = state->dev; struct intel_crtc *intel_crtc; + struct intel_crtc_state *crtc_state; int max_pixclk = 0; for_each_intel_crtc(dev, intel_crtc) { - if (intel_crtc->new_enabled) - max_pixclk = max(max_pixclk, - intel_crtc->new_config->base.adjusted_mode.crtc_clock); + crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + if (!crtc_state->base.enable) + continue; + + max_pixclk = max(max_pixclk, + crtc_state->base.adjusted_mode.crtc_clock); } return max_pixclk; } -static void valleyview_modeset_global_pipes(struct drm_device *dev, +static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, unsigned *prepare_pipes) { - struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_private *dev_priv = to_i915(state->dev); struct intel_crtc *intel_crtc; - int max_pixclk = intel_mode_max_pixclk(dev_priv); + int max_pixclk = intel_mode_max_pixclk(state); + + if (max_pixclk < 0) + return max_pixclk; if (valleyview_calc_cdclk(dev_priv, max_pixclk) == dev_priv->vlv_cdclk_freq) - return; + return 0; /* disable/enable all currently active pipes while we change cdclk */ - for_each_intel_crtc(dev, intel_crtc) + for_each_intel_crtc(state->dev, intel_crtc) if (intel_crtc->base.state->enable) *prepare_pipes |= (1 << intel_crtc->pipe); + + return 0; } static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) @@ -5232,8 +5244,18 @@ static void valleyview_modeset_global_resources(struct drm_atomic_state *state) { struct drm_device *dev = state->dev; struct drm_i915_private *dev_priv = dev->dev_private; - int max_pixclk = intel_mode_max_pixclk(dev_priv); - int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); + int max_pixclk = intel_mode_max_pixclk(state); + int req_cdclk; + + /* The only reason this can fail is if we fail to add the crtc_state + * to the atomic state. But that can't happen since the call to + * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which + * can't have failed otherwise the mode set would be aborted) added all + * the states already. */ + if (WARN_ON(max_pixclk < 0)) + return; + + req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); if (req_cdclk != dev_priv->vlv_cdclk_freq) { /* @@ -11550,6 +11572,8 @@ intel_modeset_compute_config(struct drm_crtc *crtc, if (IS_ERR(pipe_config)) return pipe_config; + pipe_config->base.enable = true; + intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, "[modeset]"); } @@ -11598,6 +11622,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_display_mode *saved_mode; + struct drm_atomic_state *state = pipe_config->base.state; struct intel_crtc_state *crtc_state_copy = NULL; struct intel_crtc *intel_crtc; int ret = 0; @@ -11625,7 +11650,9 @@ static int __intel_set_mode(struct drm_crtc *crtc, * adjusted_mode bits in the crtc directly. */ if (IS_VALLEYVIEW(dev)) { - valleyview_modeset_global_pipes(dev, &prepare_pipes); + ret = valleyview_modeset_global_pipes(state, &prepare_pipes); + if (ret) + goto done; /* may have added more to prepare_pipes than we should */ prepare_pipes &= ~disable_pipes; @@ -11669,7 +11696,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, * update the the output configuration. */ intel_modeset_update_state(dev, prepare_pipes); - modeset_update_crtc_power_domains(pipe_config->base.state); + modeset_update_crtc_power_domains(state); /* Set up the DPLL and any encoders state that needs to adjust or depend * on the DPLL. -- cgit v1.2.3 From 225da59b540a92c8f8bbeb4c69c9139da06b061a Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Thu, 2 Apr 2015 14:47:57 +0300 Subject: drm/i915: Don't use intel_crtc->new_config in pll calculation code Move towards atomic by using the atomic state instead. Signed-off-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a6cd8c7a64e9..0b7ddeee681a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11581,10 +11581,11 @@ intel_modeset_compute_config(struct drm_crtc *crtc, return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));; } -static int __intel_set_mode_setup_plls(struct drm_device *dev, +static int __intel_set_mode_setup_plls(struct drm_atomic_state *state, unsigned modeset_pipes, unsigned disable_pipes) { + struct drm_device *dev = state->dev; struct drm_i915_private *dev_priv = to_i915(dev); unsigned clear_pipes = modeset_pipes | disable_pipes; struct intel_crtc *intel_crtc; @@ -11598,9 +11599,15 @@ static int __intel_set_mode_setup_plls(struct drm_device *dev, goto done; for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { - struct intel_crtc_state *state = intel_crtc->new_config; + struct intel_crtc_state *crtc_state = + intel_atomic_get_crtc_state(state, intel_crtc); + + /* Modeset pipes should have a new state by now */ + if (WARN_ON(IS_ERR(crtc_state))) + continue; + ret = dev_priv->display.crtc_compute_clock(intel_crtc, - state); + crtc_state); if (ret) { intel_shared_dpll_abort_config(dev_priv); goto done; @@ -11658,7 +11665,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, prepare_pipes &= ~disable_pipes; } - ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes); + ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes); if (ret) goto done; -- cgit v1.2.3 From d69ba09b68ff779877dbbc3be2958a80151ae91b Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Thu, 2 Apr 2015 14:47:58 +0300 Subject: drm/i915: Remove intel_crtc->new_config It's not needed anymore, now that all the users were converted to using an atomic state. Signed-off-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 31 ------------------------------- drivers/gpu/drm/i915/intel_drv.h | 1 - 2 files changed, 32 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0b7ddeee681a..207c713dd574 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9171,7 +9171,6 @@ retry: intel_crtc = to_intel_crtc(crtc); intel_crtc->new_enabled = true; - intel_crtc->new_config = intel_crtc->config; old->dpms_mode = connector->dpms; old->load_detect_temp = true; old->release_fb = NULL; @@ -9227,10 +9226,6 @@ retry: fail: intel_crtc->new_enabled = crtc->state->enable; - if (intel_crtc->new_enabled) - intel_crtc->new_config = intel_crtc->config; - else - intel_crtc->new_config = NULL; fail_unlock: if (state) { drm_atomic_state_free(state); @@ -9276,7 +9271,6 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, to_intel_connector(connector)->new_encoder = NULL; intel_encoder->new_crtc = NULL; intel_crtc->new_enabled = false; - intel_crtc->new_config = NULL; connector_state->best_encoder = NULL; connector_state->crtc = NULL; @@ -10416,11 +10410,6 @@ static void intel_modeset_update_staged_output_state(struct drm_device *dev) for_each_intel_crtc(dev, crtc) { crtc->new_enabled = crtc->base.state->enable; - - if (crtc->new_enabled) - crtc->new_config = crtc->config; - else - crtc->new_config = NULL; } } @@ -10981,9 +10970,6 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) /* Double check state. */ for_each_intel_crtc(dev, intel_crtc) { WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); - WARN_ON(intel_crtc->new_config && - intel_crtc->new_config != intel_crtc->config); - WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config); } list_for_each_entry(connector, &dev->mode_config.connector_list, head) { @@ -11646,9 +11632,6 @@ static int __intel_set_mode(struct drm_crtc *crtc, *saved_mode = crtc->mode; - if (modeset_pipes) - to_intel_crtc(crtc)->new_config = pipe_config; - /* * See if the config requires any additional preparation, e.g. * to adjust global state with pipes off. We need to do this @@ -11741,9 +11724,6 @@ done: sizeof *crtc_state_copy); intel_crtc->config = crtc_state_copy; intel_crtc->base.state = &crtc_state_copy->base; - - if (modeset_pipes) - intel_crtc->new_config = intel_crtc->config; } else { kfree(crtc_state_copy); } @@ -11922,11 +11902,6 @@ static void intel_set_config_restore_state(struct drm_device *dev, count = 0; for_each_intel_crtc(dev, crtc) { crtc->new_enabled = config->save_crtc_enabled[count++]; - - if (crtc->new_enabled) - crtc->new_config = crtc->config; - else - crtc->new_config = NULL; } count = 0; @@ -12153,11 +12128,6 @@ intel_modeset_stage_output_state(struct drm_device *dev, crtc->new_enabled ? "en" : "dis"); config->mode_changed = true; } - - if (crtc->new_enabled) - crtc->new_config = crtc->config; - else - crtc->new_config = NULL; } return 0; @@ -12184,7 +12154,6 @@ static void disable_crtc_nofb(struct intel_crtc *crtc) } crtc->new_enabled = false; - crtc->new_config = NULL; } static int intel_crtc_set_config(struct drm_mode_set *set) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 4799b11f30c5..686014bd5ec0 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -471,7 +471,6 @@ struct intel_crtc { struct intel_initial_plane_config plane_config; struct intel_crtc_state *config; - struct intel_crtc_state *new_config; bool new_enabled; /* reset counter value when the last flip was submitted */ -- cgit v1.2.3 From 5448a00d3f0640949c2a9a4d16e163b0b40a3b2e Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Thu, 2 Apr 2015 14:47:59 +0300 Subject: drm/i915: Don't use staged config in check_digital_port_conflicts() Reduce dependency on the staged config by using the atomic state instead. Signed-off-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 207c713dd574..b1fbe9d994ff 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10658,23 +10658,30 @@ static bool check_encoder_cloning(struct intel_crtc *crtc) return true; } -static bool check_digital_port_conflicts(struct drm_device *dev) +static bool check_digital_port_conflicts(struct drm_atomic_state *state) { - struct intel_connector *connector; + struct drm_device *dev = state->dev; + struct intel_encoder *encoder; + struct drm_connector_state *connector_state; unsigned int used_ports = 0; + int i; /* * Walk the connector list instead of the encoder * list to detect the problem on ddi platforms * where there's just one encoder per digital port. */ - for_each_intel_connector(dev, connector) { - struct intel_encoder *encoder = connector->new_encoder; + for (i = 0; i < state->num_connector; i++) { + if (!state->connectors[i]) + continue; - if (!encoder) + connector_state = state->connector_states[i]; + if (!connector_state->best_encoder) continue; - WARN_ON(!encoder->new_crtc); + encoder = to_intel_encoder(connector_state->best_encoder); + + WARN_ON(!connector_state->crtc); switch (encoder->type) { unsigned int port_mask; @@ -10716,7 +10723,6 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_atomic_state *state) { - struct drm_device *dev = crtc->dev; struct intel_encoder *encoder; struct intel_connector *connector; struct drm_connector_state *connector_state; @@ -10730,7 +10736,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, return ERR_PTR(-EINVAL); } - if (!check_digital_port_conflicts(dev)) { + if (!check_digital_port_conflicts(state)) { DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); return ERR_PTR(-EINVAL); } -- cgit v1.2.3 From 98a221da4aeb18b2b68b08359666230c1febafe0 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Thu, 2 Apr 2015 14:48:00 +0300 Subject: drm/i915: Don't use staged config in check_encoder_cloning() Reduce dependency on the staged config by using the atomic state instead. Signed-off-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b1fbe9d994ff..bc8e221a30d1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10625,16 +10625,24 @@ static bool encoders_cloneable(const struct intel_encoder *a, b->cloneable & (1 << a->type)); } -static bool check_single_encoder_cloning(struct intel_crtc *crtc, +static bool check_single_encoder_cloning(struct drm_atomic_state *state, + struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_device *dev = crtc->base.dev; struct intel_encoder *source_encoder; + struct drm_connector_state *connector_state; + int i; - for_each_intel_encoder(dev, source_encoder) { - if (source_encoder->new_crtc != crtc) + for (i = 0; i < state->num_connector; i++) { + if (!state->connectors[i]) continue; + connector_state = state->connector_states[i]; + if (connector_state->crtc != &crtc->base) + continue; + + source_encoder = + to_intel_encoder(connector_state->best_encoder); if (!encoders_cloneable(encoder, source_encoder)) return false; } @@ -10642,16 +10650,23 @@ static bool check_single_encoder_cloning(struct intel_crtc *crtc, return true; } -static bool check_encoder_cloning(struct intel_crtc *crtc) +static bool check_encoder_cloning(struct drm_atomic_state *state, + struct intel_crtc *crtc) { - struct drm_device *dev = crtc->base.dev; struct intel_encoder *encoder; + struct drm_connector_state *connector_state; + int i; - for_each_intel_encoder(dev, encoder) { - if (encoder->new_crtc != crtc) + for (i = 0; i < state->num_connector; i++) { + if (!state->connectors[i]) continue; - if (!check_single_encoder_cloning(crtc, encoder)) + connector_state = state->connector_states[i]; + if (connector_state->crtc != &crtc->base) + continue; + + encoder = to_intel_encoder(connector_state->best_encoder); + if (!check_single_encoder_cloning(state, crtc, encoder)) return false; } @@ -10731,7 +10746,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, int i; bool retry = true; - if (!check_encoder_cloning(to_intel_crtc(crtc))) { + if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); return ERR_PTR(-EINVAL); } -- cgit v1.2.3 From 9b4fd8f250e08d8f22a31d947ac3ca16383df1e1 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Thu, 2 Apr 2015 14:48:01 +0300 Subject: drm/i915: Don't use staged config in intel_mst_pre_enable_dp() For the conversion to atomic. The pre_enable() hooks are called as part of the crtc enable sequence, at which point the staged config was already made effective. Furthermore, the function actually changes hardware state, so it should anyway deal with current and not staged config. Signed-off-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp_mst.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 5329c855acce..adcc5e641347 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -150,14 +150,14 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder) enum port port = intel_dig_port->port; int ret; uint32_t temp; - struct intel_connector *found = NULL, *intel_connector; + struct intel_connector *found = NULL, *connector; int slots; struct drm_crtc *crtc = encoder->base.crtc; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - for_each_intel_connector(dev, intel_connector) { - if (intel_connector->new_encoder == encoder) { - found = intel_connector; + for_each_intel_connector(dev, connector) { + if (connector->base.state->best_encoder == &encoder->base) { + found = connector; break; } } -- cgit v1.2.3 From b833bb61fd905a8d2c7392d1bc5fedf34921e251 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 7 Apr 2015 11:32:02 +0200 Subject: drm/i915: use kref_put_mutex in i915_gem_request_unreference__unlocked Signed-off-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4fd38f2e6e62..d5b21153f200 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2148,14 +2148,14 @@ i915_gem_request_unreference(struct drm_i915_gem_request *req) static inline void i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) { - if (req && !atomic_add_unless(&req->ref.refcount, -1, 1)) { - struct drm_device *dev = req->ring->dev; + struct drm_device *dev; + + if (!req) + return; - mutex_lock(&dev->struct_mutex); - if (likely(atomic_dec_and_test(&req->ref.refcount))) - i915_gem_request_free(&req->ref); + dev = req->ring->dev; + if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) mutex_unlock(&dev->struct_mutex); - } } static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, -- cgit v1.2.3 From 51847fb99f25fe1bf4bc6739f9d8ac85fa2c2a65 Mon Sep 17 00:00:00 2001 From: Arun Siluvery Date: Tue, 7 Apr 2015 14:01:33 +0100 Subject: drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor According to Spec this is a reserved bit for Gen9+ and should not be set. Change-Id: I0215fb7057b94139b7a2f90ecc7a0201c0c93ad4 Signed-off-by: Arun Siluvery Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_lrc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 1c3834fc5608..cfc73ea59804 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -265,7 +265,8 @@ static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring, desc = GEN8_CTX_VALID; desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; - desc |= GEN8_CTX_L3LLC_COHERENT; + if (IS_GEN8(ctx_obj->base.dev)) + desc |= GEN8_CTX_L3LLC_COHERENT; desc |= GEN8_CTX_PRIVILEGE; desc |= lrca; desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; -- cgit v1.2.3 From 669506e781d12939ad270b4c281189de119d1319 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Thu, 26 Feb 2015 18:20:38 +0000 Subject: drm/i915/skl: Fix stepping check for a couple of W/As Both WaDisableSDEUnitClockGating and WaSetGAPSunitClckGateDisable are needed on B0 as well. Signed-off-by: Damien Lespiau Reviewed-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index cd91407e1f93..d76d6ab3775f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -67,7 +67,7 @@ static void skl_init_clock_gating(struct drm_device *dev) gen9_init_clock_gating(dev); - if (INTEL_REVID(dev) == SKL_REVID_A0) { + if (INTEL_REVID(dev) <= SKL_REVID_B0) { /* * WaDisableSDEUnitClockGating:skl * WaSetGAPSunitClckGateDisable:skl -- cgit v1.2.3 From f9fc42f4bd9a6b9d63f8587325c7f53a6b788d8e Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Thu, 26 Feb 2015 18:20:39 +0000 Subject: drm/i915/skl: Implement WaDisableVFUnitClockGating Signed-off-by: Damien Lespiau Reviewed-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9966d3294a02..b01da4ebcebe 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6102,6 +6102,7 @@ enum skl_disp_power_wells { # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) #define GEN6_UCGCTL2 0x9404 +# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d76d6ab3775f..67e1e61c50e7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -75,6 +75,10 @@ static void skl_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | GEN8_GAPSUNIT_CLOCK_GATE_DISABLE | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); + + /* WaDisableVFUnitClockGating:skl */ + I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) | + GEN6_VFUNIT_CLOCK_GATE_DISABLE); } if (INTEL_REVID(dev) <= SKL_REVID_D0) { -- cgit v1.2.3 From ee286370d6233da01788c942c2dd7e450078eb27 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:25 +0100 Subject: drm/i915: Cache last obj->pages location for i915_gem_object_get_page() The biggest user of i915_gem_object_get_page() is the relocation processing during execbuffer. Typically userspace passes in a set of relocations in sorted order. Sadly, we alternate between relocations increasing from the start of the buffers, and relocations decreasing from the end. However the majority of consecutive lookups will still be in the same page. We could cache the start of the last sg chain, however for most callers, the entire sgl is inside a single chain and so we see no improve from the extra layer of caching. v2: Avoid the double increment inside unlikely() References: https://bugs.freedesktop.org/show_bug.cgi?id=88308 Signed-off-by: Chris Wilson Cc: John Harrison Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 31 ++++++++++++++++++++++++++----- drivers/gpu/drm/i915/i915_gem.c | 4 ++++ 2 files changed, 30 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d5b21153f200..924676fdb26f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1986,6 +1986,10 @@ struct drm_i915_gem_object { struct sg_table *pages; int pages_pin_count; + struct get_page { + struct scatterlist *sg; + int last; + } get_page; /* prime dma-buf support */ void *dma_buf_vmapping; @@ -2656,15 +2660,32 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, int *needs_clflush); int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); -static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) + +static inline int __sg_page_count(struct scatterlist *sg) +{ + return sg->length >> PAGE_SHIFT; +} + +static inline struct page * +i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) { - struct sg_page_iter sg_iter; + if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) + return NULL; - for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) - return sg_page_iter_page(&sg_iter); + if (n < obj->get_page.last) { + obj->get_page.sg = obj->pages->sgl; + obj->get_page.last = 0; + } + + while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { + obj->get_page.last += __sg_page_count(obj->get_page.sg++); + if (unlikely(sg_is_chain(obj->get_page.sg))) + obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); + } - return NULL; + return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); } + static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) { BUG_ON(obj->pages == NULL); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 267fdf0f46ae..976d27a19192 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2178,6 +2178,10 @@ i915_gem_object_get_pages(struct drm_i915_gem_object *obj) return ret; list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); + + obj->get_page.sg = obj->pages->sgl; + obj->get_page.last = 0; + return 0; } -- cgit v1.2.3 From cf5d8a46a001c9421c7397699db55f962e0410fc Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:26 +0100 Subject: drm/i915: Fix the flip synchronisation to consider mmioflips Currently we emit semaphore synchronisation as if we were going to flip using the target CS engine, but we then change our minds and do the flip using the CPU. Consequently we write instructions to the ring but never use them - even to the point of filling that ring up entirely and never submitting a request. The wrinkle in the ointment is that we have to tell a white lie to pin-to-display for it to skip the synchronisation for mmioflips as we will create a task specifically for that slow synchronisation. An oddity of note is the discrepancy in requests that we tell to pin-display to serialise to and that we then eventually wait upon. This is due to a limitation in the i915_gem_object_sync() routine that will be lifted later. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bc8e221a30d1..6256e6157845 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10210,6 +10210,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, enum pipe pipe = intel_crtc->pipe; struct intel_unpin_work *work; struct intel_engine_cs *ring; + bool mmio_flip; int ret; /* @@ -10307,15 +10308,23 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, ring = &dev_priv->ring[RCS]; } + mmio_flip = use_mmio_flip(ring, obj); + + /* When using CS flips, we want to emit semaphores between rings. + * However, when using mmio flips we will create a task to do the + * synchronisation, so all we want here is to pin the framebuffer + * into the display plane and skip any waits. + */ ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, - crtc->primary->state, ring); + crtc->primary->state, + mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring); if (ret) goto cleanup_pending; work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) + intel_crtc->dspaddr_offset; - if (use_mmio_flip(ring, obj)) { + if (mmio_flip) { ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, page_flip_flags); if (ret) -- cgit v1.2.3 From 8fb55197e64d5988ec57b54e973daeea72c3f2ff Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:28 +0100 Subject: drm/i915: Agressive downclocking on Baytrail MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reuse the same reclocking strategy for Baytail as on its bigger brethren, Sandybridge and Ivybridge. In particular, this makes the device quicker to reclock (both up and down) though the tendency now is to downclock more aggressively to compensate for the RPS boosts. v2: Rebase v3: Exclude Cherrytrail as Deepak was concerned that the increased number of register writes would wake the common powerwell too often. Signed-off-by: Chris Wilson Cc: Deepak S Cc: Ville Syrjälä Cc: Rodrigo Vivi Cc: Daniel Vetter Reviewed-by: Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/i915_irq.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 -- drivers/gpu/drm/i915/intel_pm.c | 8 +++++++- 4 files changed, 12 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 924676fdb26f..b4501647795e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1035,6 +1035,9 @@ struct intel_gen6_power_mgmt { u8 rp0_freq; /* Non-overclocked max frequency. */ u32 cz_freq; + u8 up_threshold; /* Current %busy required to uplock */ + u8 down_threshold; /* Current %busy required to downclock */ + int last_adj; enum { LOW_POWER, BETWEEN, HIGH_POWER } power; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 14ecb4d13a1a..128a6f40b450 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1049,7 +1049,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { if (!vlv_c0_above(dev_priv, &dev_priv->rps.down_ei, &now, - VLV_RP_DOWN_EI_THRESHOLD)) + dev_priv->rps.down_threshold)) events |= GEN6_PM_RP_DOWN_THRESHOLD; dev_priv->rps.down_ei = now; } @@ -1057,7 +1057,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { if (vlv_c0_above(dev_priv, &dev_priv->rps.up_ei, &now, - VLV_RP_UP_EI_THRESHOLD)) + dev_priv->rps.up_threshold)) events |= GEN6_PM_RP_UP_THRESHOLD; dev_priv->rps.up_ei = now; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b01da4ebcebe..77d8874c2fc3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -671,8 +671,6 @@ enum skl_disp_power_wells { #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 -#define VLV_RP_UP_EI_THRESHOLD 90 -#define VLV_RP_DOWN_EI_THRESHOLD 70 /* vlv2 north clock has */ #define CCK_FUSE_REG 0x8 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 67e1e61c50e7..9c705dec853e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3934,6 +3934,8 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) GEN6_RP_DOWN_IDLE_AVG); dev_priv->rps.power = new_power; + dev_priv->rps.up_threshold = threshold_up; + dev_priv->rps.down_threshold = threshold_down; dev_priv->rps.last_adj = 0; } @@ -4005,8 +4007,11 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) "Odd GPU freq value\n")) val &= ~1; - if (val != dev_priv->rps.cur_freq) + if (val != dev_priv->rps.cur_freq) { vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); + if (!IS_CHERRYVIEW(dev_priv)) + gen6_set_rps_thresholds(dev_priv, val); + } I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); @@ -4055,6 +4060,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) & GENFREQSTATUS) == 0, 100)) DRM_ERROR("timed out waiting for Punit\n"); + gen6_set_rps_thresholds(dev_priv, val); vlv_force_gfx_clock(dev_priv, false); I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); -- cgit v1.2.3 From edcf284bfe9c94eab2923b13cfff7456c0dc7dc6 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:29 +0100 Subject: drm/i915: Fix computation of last_adjustment for RPS autotuning The issue is that by computing the last_adj value after applying the clamping, we can end up with a bogus value for feeding into the next RPS autotuning step. Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: Deepak S Reviewed-by: Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 128a6f40b450..8b5e0358c592 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1095,21 +1095,20 @@ static void gen6_pm_rps_work(struct work_struct *work) pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); adj = dev_priv->rps.last_adj; + new_delay = dev_priv->rps.cur_freq; if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { if (adj > 0) adj *= 2; - else { - /* CHV needs even encode values */ - adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1; - } - new_delay = dev_priv->rps.cur_freq + adj; - + else /* CHV needs even encode values */ + adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; /* * For better performance, jump directly * to RPe if we're below it. */ - if (new_delay < dev_priv->rps.efficient_freq) + if (new_delay < dev_priv->rps.efficient_freq - adj) { new_delay = dev_priv->rps.efficient_freq; + adj = 0; + } } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) new_delay = dev_priv->rps.efficient_freq; @@ -1119,24 +1118,22 @@ static void gen6_pm_rps_work(struct work_struct *work) } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { if (adj < 0) adj *= 2; - else { - /* CHV needs even encode values */ - adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1; - } - new_delay = dev_priv->rps.cur_freq + adj; + else /* CHV needs even encode values */ + adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; } else { /* unknown event */ - new_delay = dev_priv->rps.cur_freq; + adj = 0; } + dev_priv->rps.last_adj = adj; + /* sysfs frequency interfaces may have snuck in while servicing the * interrupt */ + new_delay += adj; new_delay = clamp_t(int, new_delay, dev_priv->rps.min_freq_softlimit, dev_priv->rps.max_freq_softlimit); - dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; - intel_set_rps(dev_priv->dev, new_delay); mutex_unlock(&dev_priv->rps.hw_lock); -- cgit v1.2.3 From 6ad790c0f5ac55fd13f322c23519f0d6f0721864 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:31 +0100 Subject: drm/i915: Boost GPU frequency if we detect outstanding pageflips MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If we hit a vblank and see that have a pageflip queue but not yet processed, ensure that the GPU is running at maximum in order to clear the backlog. Pageflips are only queued for the following vblank, if we miss it, there will be a visible stutter. Boosting the GPU frequency doesn't prevent us from missing the target vblank, but it should help the subsequent frames hitting theirs. v2: Reorder vblank vs flip-complete so that we only check for a missed flip after processing the completion events, and avoid spurious boosts. v3: Rename missed_vblank v4: Rebase v5: Cancel the outstanding work in runtime suspend v6: Rebase v7: Rebase required fixing Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: Ville Syrjälä Cc: Deepak S Reviewed-by: Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 11 ++++++++--- drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6256e6157845..7bfe2af42030 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10180,6 +10180,7 @@ void intel_check_page_flip(struct drm_device *dev, int pipe) struct drm_i915_private *dev_priv = dev->dev_private; struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_unpin_work *work; WARN_ON(!in_interrupt()); @@ -10187,12 +10188,16 @@ void intel_check_page_flip(struct drm_device *dev, int pipe) return; spin_lock(&dev->event_lock); - if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) { + work = intel_crtc->unpin_work; + if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", - intel_crtc->unpin_work->flip_queued_vblank, - drm_vblank_count(dev, pipe)); + work->flip_queued_vblank, drm_vblank_count(dev, pipe)); page_flip_completed(intel_crtc); + work = NULL; } + if (work != NULL && + drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) + intel_queue_rps_boost_for_request(dev, work->flip_queued_req); spin_unlock(&dev->event_lock); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 686014bd5ec0..4771d319ac7b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1263,6 +1263,8 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv); void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); void gen6_rps_idle(struct drm_i915_private *dev_priv); void gen6_rps_boost(struct drm_i915_private *dev_priv); +void intel_queue_rps_boost_for_request(struct drm_device *dev, + struct drm_i915_gem_request *rq); void ilk_wm_get_hw_state(struct drm_device *dev); void skl_wm_get_hw_state(struct drm_device *dev); void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9c705dec853e..acf1a318fda9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6772,6 +6772,41 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) return val / GT_FREQUENCY_MULTIPLIER; } +struct request_boost { + struct work_struct work; + struct drm_i915_gem_request *rq; +}; + +static void __intel_rps_boost_work(struct work_struct *work) +{ + struct request_boost *boost = container_of(work, struct request_boost, work); + + if (!i915_gem_request_completed(boost->rq, true)) + gen6_rps_boost(to_i915(boost->rq->ring->dev)); + + i915_gem_request_unreference__unlocked(boost->rq); + kfree(boost); +} + +void intel_queue_rps_boost_for_request(struct drm_device *dev, + struct drm_i915_gem_request *rq) +{ + struct request_boost *boost; + + if (rq == NULL || INTEL_INFO(dev)->gen < 6) + return; + + boost = kmalloc(sizeof(*boost), GFP_ATOMIC); + if (boost == NULL) + return; + + i915_gem_request_reference(rq); + boost->rq = rq; + + INIT_WORK(&boost->work, __intel_rps_boost_work); + queue_work(to_i915(dev)->wq, &boost->work); +} + void intel_pm_setup(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; -- cgit v1.2.3 From 1854d5ca0dd7a9fc11243ff220a3e93fce2b4d3e Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:32 +0100 Subject: drm/i915: Deminish contribution of wait-boosting from clients With boosting for missed pageflips, we have a much stronger indication of when we need to (temporarily) boost GPU frequency to ensure smooth delivery of frames. So now only allow each client to perform one RPS boost in each period of GPU activity due to stalling on results. Signed-off-by: Chris Wilson Cc: Deepak S Reviewed-by: Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 39 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 9 ++++++--- drivers/gpu/drm/i915/i915_gem.c | 35 ++++++++------------------------- drivers/gpu/drm/i915/intel_drv.h | 3 ++- drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++--- 5 files changed, 70 insertions(+), 34 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 10ca5117fcee..9c23eec3277e 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2239,6 +2239,44 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) return 0; } +static int i915_rps_boost_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = m->private; + struct drm_device *dev = node->minor->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_file *file; + int ret; + + ret = mutex_lock_interruptible(&dev->struct_mutex); + if (ret) + return ret; + + ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); + if (ret) + goto unlock; + + list_for_each_entry_reverse(file, &dev->filelist, lhead) { + struct drm_i915_file_private *file_priv = file->driver_priv; + struct task_struct *task; + + rcu_read_lock(); + task = pid_task(file->pid, PIDTYPE_PID); + seq_printf(m, "%s [%d]: %d boosts%s\n", + task ? task->comm : "", + task ? task->pid : -1, + file_priv->rps_boosts, + list_empty(&file_priv->rps_boost) ? "" : ", active"); + rcu_read_unlock(); + } + seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); + + mutex_unlock(&dev_priv->rps.hw_lock); +unlock: + mutex_unlock(&dev->struct_mutex); + + return ret; +} + static int i915_llc(struct seq_file *m, void *data) { struct drm_info_node *node = m->private; @@ -4704,6 +4742,7 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_ddb_info", i915_ddb_info, 0}, {"i915_sseu_status", i915_sseu_status, 0}, {"i915_drrs_status", i915_drrs_status, 0}, + {"i915_rps_boost_info", i915_rps_boost_info, 0}, }; #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b4501647795e..3b6ddd74cd69 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1043,6 +1043,8 @@ struct intel_gen6_power_mgmt { bool enabled; struct delayed_work delayed_resume_work; + struct list_head clients; + unsigned boosts; /* manual wa residency calculations */ struct intel_rps_ei up_ei, down_ei; @@ -2190,12 +2192,13 @@ struct drm_i915_file_private { struct { spinlock_t lock; struct list_head request_list; - struct delayed_work idle_work; } mm; struct idr context_idr; - atomic_t rps_wait_boost; - struct intel_engine_cs *bsd_ring; + struct list_head rps_boost; + struct intel_engine_cs *bsd_ring; + + unsigned rps_boosts; }; /* diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 976d27a19192..4061b4ffe815 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1181,14 +1181,6 @@ static bool missed_irq(struct drm_i915_private *dev_priv, return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); } -static bool can_wait_boost(struct drm_i915_file_private *file_priv) -{ - if (file_priv == NULL) - return true; - - return !atomic_xchg(&file_priv->rps_wait_boost, true); -} - /** * __i915_wait_request - wait until execution of request has finished * @req: duh! @@ -1230,13 +1222,8 @@ int __i915_wait_request(struct drm_i915_gem_request *req, timeout_expire = timeout ? jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; - if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { - gen6_rps_boost(dev_priv); - if (file_priv) - mod_delayed_work(dev_priv->wq, - &file_priv->mm.idle_work, - msecs_to_jiffies(100)); - } + if (ring->id == RCS && INTEL_INFO(dev)->gen >= 6) + gen6_rps_boost(dev_priv, file_priv); if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) return -ENODEV; @@ -5043,8 +5030,6 @@ void i915_gem_release(struct drm_device *dev, struct drm_file *file) { struct drm_i915_file_private *file_priv = file->driver_priv; - cancel_delayed_work_sync(&file_priv->mm.idle_work); - /* Clean up our request list when the client is going away, so that * later retire_requests won't dereference our soon-to-be-gone * file_priv. @@ -5060,15 +5045,12 @@ void i915_gem_release(struct drm_device *dev, struct drm_file *file) request->file_priv = NULL; } spin_unlock(&file_priv->mm.lock); -} - -static void -i915_gem_file_idle_work_handler(struct work_struct *work) -{ - struct drm_i915_file_private *file_priv = - container_of(work, typeof(*file_priv), mm.idle_work.work); - atomic_set(&file_priv->rps_wait_boost, false); + if (!list_empty(&file_priv->rps_boost)) { + mutex_lock(&to_i915(dev)->rps.hw_lock); + list_del(&file_priv->rps_boost); + mutex_unlock(&to_i915(dev)->rps.hw_lock); + } } int i915_gem_open(struct drm_device *dev, struct drm_file *file) @@ -5085,11 +5067,10 @@ int i915_gem_open(struct drm_device *dev, struct drm_file *file) file->driver_priv = file_priv; file_priv->dev_priv = dev->dev_private; file_priv->file = file; + INIT_LIST_HEAD(&file_priv->rps_boost); spin_lock_init(&file_priv->mm.lock); INIT_LIST_HEAD(&file_priv->mm.request_list); - INIT_DELAYED_WORK(&file_priv->mm.idle_work, - i915_gem_file_idle_work_handler); ret = i915_gem_context_open(dev, file); if (ret) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 4771d319ac7b..efa53d57dd37 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1262,7 +1262,8 @@ void gen6_update_ring_freq(struct drm_device *dev); void gen6_rps_busy(struct drm_i915_private *dev_priv); void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); void gen6_rps_idle(struct drm_i915_private *dev_priv); -void gen6_rps_boost(struct drm_i915_private *dev_priv); +void gen6_rps_boost(struct drm_i915_private *dev_priv, + struct drm_i915_file_private *file_priv); void intel_queue_rps_boost_for_request(struct drm_device *dev, struct drm_i915_gem_request *rq); void ilk_wm_get_hw_state(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index acf1a318fda9..1ab9e897994a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4091,10 +4091,14 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv) dev_priv->rps.last_adj = 0; I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); } + + while (!list_empty(&dev_priv->rps.clients)) + list_del_init(dev_priv->rps.clients.next); mutex_unlock(&dev_priv->rps.hw_lock); } -void gen6_rps_boost(struct drm_i915_private *dev_priv) +void gen6_rps_boost(struct drm_i915_private *dev_priv, + struct drm_i915_file_private *file_priv) { u32 val; @@ -4102,9 +4106,16 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv) val = dev_priv->rps.max_freq_softlimit; if (dev_priv->rps.enabled && dev_priv->mm.busy && - dev_priv->rps.cur_freq < val) { + dev_priv->rps.cur_freq < val && + (file_priv == NULL || list_empty(&file_priv->rps_boost))) { intel_set_rps(dev_priv->dev, val); dev_priv->rps.last_adj = 0; + + if (file_priv != NULL) { + list_add(&file_priv->rps_boost, &dev_priv->rps.clients); + file_priv->rps_boosts++; + } else + dev_priv->rps.boosts++; } mutex_unlock(&dev_priv->rps.hw_lock); } @@ -6782,7 +6793,7 @@ static void __intel_rps_boost_work(struct work_struct *work) struct request_boost *boost = container_of(work, struct request_boost, work); if (!i915_gem_request_completed(boost->rq, true)) - gen6_rps_boost(to_i915(boost->rq->ring->dev)); + gen6_rps_boost(to_i915(boost->rq->ring->dev), NULL); i915_gem_request_unreference__unlocked(boost->rq); kfree(boost); @@ -6815,6 +6826,7 @@ void intel_pm_setup(struct drm_device *dev) INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, intel_gen6_powersave_work); + INIT_LIST_HEAD(&dev_priv->rps.clients); dev_priv->pm.suspended = false; } -- cgit v1.2.3 From 7c27f52509994a874371a0756bee35facf51858b Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:33 +0100 Subject: drm/i915: Re-enable RPS wait-boosting for all engines This reverts commit ec5cc0f9b019af95e4571a9fa162d94294c8d90b Author: Chris Wilson Date: Thu Jun 12 10:28:55 2014 +0100 drm/i915: Restrict GPU boost to the RCS engine The premise that media/blitter workloads are not affected by boosting is patently false with a trip through igt. The question that remains is what exactly is going wrong with the media workload that prompted this? Hopefully that would be fixed by the missing agressive downclocking, in addition to the extra restrictions imposed on how frequent a process is allowed to boost. Signed-off-by: Chris Wilson Cc: Deepak S Cc: Daniel Vetter Acked-by: Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 4061b4ffe815..35edc8f9309d 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1222,7 +1222,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req, timeout_expire = timeout ? jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; - if (ring->id == RCS && INTEL_INFO(dev)->gen >= 6) + if (INTEL_INFO(dev)->gen >= 6) gen6_rps_boost(dev_priv, file_priv); if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) -- cgit v1.2.3 From ed9ddd25b2055d29e2106da2a6340e2614d71e86 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:34 +0100 Subject: drm/i915: Split i915_gem_batch_pool into its own header In the next patch, I want to use the structure elsewhere and so require it defined earlier. Rather than move the definition to an earlier location where it feels very odd, place it in its own header file. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 13 +-------- drivers/gpu/drm/i915/i915_gem_batch_pool.c | 1 + drivers/gpu/drm/i915/i915_gem_batch_pool.h | 42 ++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_gem_batch_pool.h (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3b6ddd74cd69..5edacad1a6e0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -37,6 +37,7 @@ #include "intel_bios.h" #include "intel_ringbuffer.h" #include "intel_lrc.h" +#include "i915_gem_batch_pool.h" #include "i915_gem_gtt.h" #include "i915_gem_render_state.h" #include @@ -1142,11 +1143,6 @@ struct intel_l3_parity { int which_slice; }; -struct i915_gem_batch_pool { - struct drm_device *dev; - struct list_head cache_list; -}; - struct i915_gem_mm { /** Memory allocator for GTT stolen memory */ struct drm_mm stolen; @@ -3064,13 +3060,6 @@ void i915_destroy_error_state(struct drm_device *dev); void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); const char *i915_cache_level_str(struct drm_i915_private *i915, int type); -/* i915_gem_batch_pool.c */ -void i915_gem_batch_pool_init(struct drm_device *dev, - struct i915_gem_batch_pool *pool); -void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool); -struct drm_i915_gem_object* -i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size); - /* i915_cmd_parser.c */ int i915_cmd_parser_get_version(void); int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c b/drivers/gpu/drm/i915/i915_gem_batch_pool.c index c690170a1c4f..564be7c5ea7e 100644 --- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c +++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c @@ -23,6 +23,7 @@ */ #include "i915_drv.h" +#include "i915_gem_batch_pool.h" /** * DOC: batch pool diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.h b/drivers/gpu/drm/i915/i915_gem_batch_pool.h new file mode 100644 index 000000000000..5ed70ef6a887 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.h @@ -0,0 +1,42 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#ifndef I915_GEM_BATCH_POOL_H +#define I915_GEM_BATCH_POOL_H + +#include "i915_drv.h" + +struct i915_gem_batch_pool { + struct drm_device *dev; + struct list_head cache_list; +}; + +/* i915_gem_batch_pool.c */ +void i915_gem_batch_pool_init(struct drm_device *dev, + struct i915_gem_batch_pool *pool); +void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool); +struct drm_i915_gem_object* +i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size); + +#endif /* I915_GEM_BATCH_POOL_H */ -- cgit v1.2.3 From de4e783a3f86f63b03303b463cd7ef885e14b476 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:35 +0100 Subject: drm/i915: Tidy batch pool logic Move the madvise logic out of the execbuffer main path into the relatively rare allocation path, making the execbuffer manipulation less fragile. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_cmd_parser.c | 12 +++------ drivers/gpu/drm/i915/i915_gem_batch_pool.c | 39 +++++++++++++++--------------- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 13 ++++------ 3 files changed, 27 insertions(+), 37 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 61ae8ff4eaed..9605ff8f2fcd 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -869,6 +869,9 @@ static u32 *copy_batch(struct drm_i915_gem_object *dest_obj, batch_len + batch_start_offset > src_obj->base.size) return ERR_PTR(-E2BIG); + if (WARN_ON(dest_obj->pages_pin_count == 0)) + return ERR_PTR(-ENODEV); + ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush); if (ret) { DRM_DEBUG_DRIVER("CMD: failed to prepare shadow batch\n"); @@ -882,13 +885,6 @@ static u32 *copy_batch(struct drm_i915_gem_object *dest_obj, goto unpin_src; } - ret = i915_gem_object_get_pages(dest_obj); - if (ret) { - DRM_DEBUG_DRIVER("CMD: Failed to get pages for shadow batch\n"); - goto unmap_src; - } - i915_gem_object_pin_pages(dest_obj); - ret = i915_gem_object_set_to_cpu_domain(dest_obj, true); if (ret) { DRM_DEBUG_DRIVER("CMD: Failed to set shadow batch to CPU\n"); @@ -898,7 +894,6 @@ static u32 *copy_batch(struct drm_i915_gem_object *dest_obj, dst = vmap_batch(dest_obj, 0, batch_len); if (!dst) { DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n"); - i915_gem_object_unpin_pages(dest_obj); ret = -ENOMEM; goto unmap_src; } @@ -1129,7 +1124,6 @@ int i915_parse_cmds(struct intel_engine_cs *ring, } vunmap(batch_base); - i915_gem_object_unpin_pages(shadow_batch_obj); return ret; } diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c b/drivers/gpu/drm/i915/i915_gem_batch_pool.c index 564be7c5ea7e..21f3356cc0ab 100644 --- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c +++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c @@ -67,25 +67,23 @@ void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool) struct drm_i915_gem_object, batch_pool_list); - WARN_ON(obj->active); - - list_del_init(&obj->batch_pool_list); + list_del(&obj->batch_pool_list); drm_gem_object_unreference(&obj->base); } } /** - * i915_gem_batch_pool_get() - select a buffer from the pool + * i915_gem_batch_pool_get() - allocate a buffer from the pool * @pool: the batch buffer pool * @size: the minimum desired size of the returned buffer * - * Finds or allocates a batch buffer in the pool with at least the requested - * size. The caller is responsible for any domain, active/inactive, or - * purgeability management for the returned buffer. + * Returns an inactive buffer from @pool with at least @size bytes, + * with the pages pinned. The caller must i915_gem_object_unpin_pages() + * on the returned object. * * Note: Callers must hold the struct_mutex * - * Return: the selected batch buffer object + * Return: the buffer object or an error pointer */ struct drm_i915_gem_object * i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, @@ -97,8 +95,7 @@ i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, WARN_ON(!mutex_is_locked(&pool->dev->struct_mutex)); list_for_each_entry_safe(tmp, next, - &pool->cache_list, batch_pool_list) { - + &pool->cache_list, batch_pool_list) { if (tmp->active) continue; @@ -114,25 +111,27 @@ i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, * but not 'too much' bigger. A better way to do this * might be to bucket the pool objects based on size. */ - if (tmp->base.size >= size && - tmp->base.size <= (2 * size)) { + if (tmp->base.size >= size && tmp->base.size <= 2 * size) { obj = tmp; break; } } - if (!obj) { + if (obj == NULL) { + int ret; + obj = i915_gem_alloc_object(pool->dev, size); - if (!obj) + if (obj == NULL) return ERR_PTR(-ENOMEM); - list_add_tail(&obj->batch_pool_list, &pool->cache_list); - } - else - /* Keep list in LRU order */ - list_move_tail(&obj->batch_pool_list, &pool->cache_list); + ret = i915_gem_object_get_pages(obj); + if (ret) + return ERR_PTR(ret); - obj->madv = I915_MADV_WILLNEED; + obj->madv = I915_MADV_DONTNEED; + } + list_move_tail(&obj->batch_pool_list, &pool->cache_list); + i915_gem_object_pin_pages(obj); return obj; } diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 2522f325e0e6..166d53330ee4 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -37,7 +37,6 @@ #define __EXEC_OBJECT_HAS_FENCE (1<<30) #define __EXEC_OBJECT_NEEDS_MAP (1<<29) #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) -#define __EXEC_OBJECT_PURGEABLE (1<<27) #define BATCH_OFFSET_BIAS (256*1024) @@ -224,12 +223,7 @@ i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) if (entry->flags & __EXEC_OBJECT_HAS_PIN) vma->pin_count--; - if (entry->flags & __EXEC_OBJECT_PURGEABLE) - obj->madv = I915_MADV_DONTNEED; - - entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | - __EXEC_OBJECT_HAS_PIN | - __EXEC_OBJECT_PURGEABLE); + entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); } static void eb_destroy(struct eb_vmas *eb) @@ -1165,11 +1159,13 @@ i915_gem_execbuffer_parse(struct intel_engine_cs *ring, if (ret) goto err; + i915_gem_object_unpin_pages(shadow_batch_obj); + memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); vma = i915_gem_obj_to_ggtt(shadow_batch_obj); vma->exec_entry = shadow_exec_entry; - vma->exec_entry->flags = __EXEC_OBJECT_PURGEABLE | __EXEC_OBJECT_HAS_PIN; + vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; drm_gem_object_reference(&shadow_batch_obj->base); list_add_tail(&vma->exec_list, &eb->vmas); @@ -1178,6 +1174,7 @@ i915_gem_execbuffer_parse(struct intel_engine_cs *ring, return shadow_batch_obj; err: + i915_gem_object_unpin_pages(shadow_batch_obj); if (ret == -EACCES) /* unhandled chained batch */ return batch_obj; else -- cgit v1.2.3 From 06fbca713e8e4a04c3506a64978969be580cd077 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:36 +0100 Subject: drm/i915: Split the batch pool by engine I woke up one morning and found 50k objects sitting in the batch pool and every search seemed to iterate the entire list... Painting the screen in oils would provide a more fluid display. One issue with the current design is that we only check for retirements on the current ring when preparing to submit a new batch. This means that we can have thousands of "active" batches on another ring that we have to walk over. The simplest way to avoid that is to split the pools per ring and then our LRU execution ordering will also ensure that the inactive buffers remain at the front. v2: execlists still requires duplicate code. v3: execlists requires more duplicate code Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 33 ++++++++++++++++++------------ drivers/gpu/drm/i915/i915_dma.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 8 -------- drivers/gpu/drm/i915/i915_gem.c | 2 -- drivers/gpu/drm/i915/i915_gem_batch_pool.c | 3 ++- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +-- drivers/gpu/drm/i915/intel_lrc.c | 2 ++ drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ drivers/gpu/drm/i915/intel_ringbuffer.h | 8 ++++++++ 9 files changed, 35 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9c23eec3277e..f610a2cd2088 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -377,13 +377,17 @@ static void print_batch_pool_stats(struct seq_file *m, { struct drm_i915_gem_object *obj; struct file_stats stats; + struct intel_engine_cs *ring; + int i; memset(&stats, 0, sizeof(stats)); - list_for_each_entry(obj, - &dev_priv->mm.batch_pool.cache_list, - batch_pool_list) - per_file_stats(0, obj, &stats); + for_each_ring(ring, dev_priv, i) { + list_for_each_entry(obj, + &ring->batch_pool.cache_list, + batch_pool_list) + per_file_stats(0, obj, &stats); + } print_file_stats(m, "batch pool", stats); } @@ -613,21 +617,24 @@ static int i915_gem_batch_pool_info(struct seq_file *m, void *data) struct drm_device *dev = node->minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj; + struct intel_engine_cs *ring; int count = 0; - int ret; + int ret, i; ret = mutex_lock_interruptible(&dev->struct_mutex); if (ret) return ret; - seq_puts(m, "cache:\n"); - list_for_each_entry(obj, - &dev_priv->mm.batch_pool.cache_list, - batch_pool_list) { - seq_puts(m, " "); - describe_obj(m, obj); - seq_putc(m, '\n'); - count++; + for_each_ring(ring, dev_priv, i) { + seq_printf(m, "%s cache:\n", ring->name); + list_for_each_entry(obj, + &ring->batch_pool.cache_list, + batch_pool_list) { + seq_puts(m, " "); + describe_obj(m, obj); + seq_putc(m, '\n'); + count++; + } } seq_printf(m, "total: %d\n", count); diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 68e0c85a17cf..8f5428b46a27 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1072,7 +1072,6 @@ int i915_driver_unload(struct drm_device *dev) mutex_lock(&dev->struct_mutex); i915_gem_cleanup_ringbuffer(dev); - i915_gem_batch_pool_fini(&dev_priv->mm.batch_pool); i915_gem_context_fini(dev); mutex_unlock(&dev->struct_mutex); i915_gem_cleanup_stolen(dev); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5edacad1a6e0..c839b5771a83 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -37,7 +37,6 @@ #include "intel_bios.h" #include "intel_ringbuffer.h" #include "intel_lrc.h" -#include "i915_gem_batch_pool.h" #include "i915_gem_gtt.h" #include "i915_gem_render_state.h" #include @@ -1156,13 +1155,6 @@ struct i915_gem_mm { */ struct list_head unbound_list; - /* - * A pool of objects to use as shadow copies of client batch buffers - * when the command parser is enabled. Prevents the client from - * modifying the batch contents after software parsing. - */ - struct i915_gem_batch_pool batch_pool; - /** Usable portion of the GTT for GEM */ unsigned long stolen_base; /* limited to low memory (32-bit) */ diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 35edc8f9309d..d1ca192afacc 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5021,8 +5021,6 @@ i915_gem_load(struct drm_device *dev) i915_gem_shrinker_init(dev_priv); - i915_gem_batch_pool_init(dev, &dev_priv->mm.batch_pool); - mutex_init(&dev_priv->fb_tracking.lock); } diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c b/drivers/gpu/drm/i915/i915_gem_batch_pool.c index 21f3356cc0ab..1287abf55b84 100644 --- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c +++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c @@ -96,8 +96,9 @@ i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, list_for_each_entry_safe(tmp, next, &pool->cache_list, batch_pool_list) { + /* The batches are strictly LRU ordered */ if (tmp->active) - continue; + break; /* While we're looping, do some clean up */ if (tmp->madv == __I915_MADV_PURGED) { diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 166d53330ee4..48ac5608481e 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1136,12 +1136,11 @@ i915_gem_execbuffer_parse(struct intel_engine_cs *ring, u32 batch_len, bool is_master) { - struct drm_i915_private *dev_priv = to_i915(batch_obj->base.dev); struct drm_i915_gem_object *shadow_batch_obj; struct i915_vma *vma; int ret; - shadow_batch_obj = i915_gem_batch_pool_get(&dev_priv->mm.batch_pool, + shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool, PAGE_ALIGN(batch_len)); if (IS_ERR(shadow_batch_obj)) return shadow_batch_obj; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index cfc73ea59804..580248d92710 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1384,6 +1384,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *ring) ring->cleanup(ring); i915_cmd_parser_fini_ring(ring); + i915_gem_batch_pool_fini(&ring->batch_pool); if (ring->status_page.obj) { kunmap(sg_page(ring->status_page.obj->pages->sgl)); @@ -1401,6 +1402,7 @@ static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *rin ring->dev = dev; INIT_LIST_HEAD(&ring->active_list); INIT_LIST_HEAD(&ring->request_list); + i915_gem_batch_pool_init(dev, &ring->batch_pool); init_waitqueue_head(&ring->irq_queue); INIT_LIST_HEAD(&ring->execlist_queue); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index b5af9b121ce1..1f9463a295a5 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1975,6 +1975,7 @@ static int intel_init_ring_buffer(struct drm_device *dev, INIT_LIST_HEAD(&ring->active_list); INIT_LIST_HEAD(&ring->request_list); INIT_LIST_HEAD(&ring->execlist_queue); + i915_gem_batch_pool_init(dev, &ring->batch_pool); ringbuf->size = 32 * PAGE_SIZE; ringbuf->ring = ring; memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); @@ -2053,6 +2054,7 @@ void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) cleanup_status_page(ring); i915_cmd_parser_fini_ring(ring); + i915_gem_batch_pool_fini(&ring->batch_pool); kfree(ringbuf); ring->buffer = NULL; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 6566dd447498..39f6dfc0ee54 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -2,6 +2,7 @@ #define _INTEL_RINGBUFFER_H_ #include +#include "i915_gem_batch_pool.h" #define I915_CMD_HASH_ORDER 9 @@ -133,6 +134,13 @@ struct intel_engine_cs { struct drm_device *dev; struct intel_ringbuffer *buffer; + /* + * A pool of objects to use as shadow copies of client batch buffers + * when the command parser is enabled. Prevents the client from + * modifying the batch contents after software parsing. + */ + struct i915_gem_batch_pool batch_pool; + struct intel_hw_status_page status_page; unsigned irq_refcount; /* protected by dev_priv->irq_lock */ -- cgit v1.2.3 From 35c94185c56de950110a09efd5d176292a21360b Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:37 +0100 Subject: drm/i915: Free batch pool when idle At runtime, this helps ensure that the batch pools are kept trim and fast. Then at suspend, this releases memory that we do not need to restore. It also ties into the oom-notifier to ensure that we recover as much kernel memory as possible during OOM. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index d1ca192afacc..4ec5d7e010db 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2795,8 +2795,19 @@ i915_gem_idle_work_handler(struct work_struct *work) { struct drm_i915_private *dev_priv = container_of(work, typeof(*dev_priv), mm.idle_work.work); + struct drm_device *dev = dev_priv->dev; + + intel_mark_idle(dev); - intel_mark_idle(dev_priv->dev); + if (mutex_trylock(&dev->struct_mutex)) { + struct intel_engine_cs *ring; + int i; + + for_each_ring(ring, dev_priv, i) + i915_gem_batch_pool_fini(&ring->batch_pool); + + mutex_unlock(&dev->struct_mutex); + } } /** -- cgit v1.2.3 From 8d9d5744c6bc861dbd379fee6dd5633a62f85be4 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:38 +0100 Subject: drm/i915: Split batch pool into size buckets Now with the trimmed memcpy before the command parser, we try to allocate many different sizes of batches, predominantly one or two pages. We can therefore speed up searching for a good sized batch by keeping the objects of buckets of roughly the same size. v2: Add a comment about bucket sizes Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_debugfs.c | 46 ++++++++++++++++++---------- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_batch_pool.c | 49 +++++++++++++++++++----------- drivers/gpu/drm/i915/i915_gem_batch_pool.h | 2 +- 5 files changed, 64 insertions(+), 37 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f610a2cd2088..11eebc28775a 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -378,15 +378,17 @@ static void print_batch_pool_stats(struct seq_file *m, struct drm_i915_gem_object *obj; struct file_stats stats; struct intel_engine_cs *ring; - int i; + int i, j; memset(&stats, 0, sizeof(stats)); for_each_ring(ring, dev_priv, i) { - list_for_each_entry(obj, - &ring->batch_pool.cache_list, - batch_pool_list) - per_file_stats(0, obj, &stats); + for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) { + list_for_each_entry(obj, + &ring->batch_pool.cache_list[j], + batch_pool_link) + per_file_stats(0, obj, &stats); + } } print_file_stats(m, "batch pool", stats); @@ -618,26 +620,38 @@ static int i915_gem_batch_pool_info(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj; struct intel_engine_cs *ring; - int count = 0; - int ret, i; + int total = 0; + int ret, i, j; ret = mutex_lock_interruptible(&dev->struct_mutex); if (ret) return ret; for_each_ring(ring, dev_priv, i) { - seq_printf(m, "%s cache:\n", ring->name); - list_for_each_entry(obj, - &ring->batch_pool.cache_list, - batch_pool_list) { - seq_puts(m, " "); - describe_obj(m, obj); - seq_putc(m, '\n'); - count++; + for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) { + int count; + + count = 0; + list_for_each_entry(obj, + &ring->batch_pool.cache_list[j], + batch_pool_link) + count++; + seq_printf(m, "%s cache[%d]: %d objects\n", + ring->name, j, count); + + list_for_each_entry(obj, + &ring->batch_pool.cache_list[j], + batch_pool_link) { + seq_puts(m, " "); + describe_obj(m, obj); + seq_putc(m, '\n'); + } + + total += count; } } - seq_printf(m, "total: %d\n", count); + seq_printf(m, "total: %d\n", total); mutex_unlock(&dev->struct_mutex); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c839b5771a83..6e0a0ae34a3f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1910,7 +1910,7 @@ struct drm_i915_gem_object { /** Used in execbuf to temporarily hold a ref */ struct list_head obj_exec_link; - struct list_head batch_pool_list; + struct list_head batch_pool_link; /** * This is set if the object is on the active lists (has pending diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 4ec5d7e010db..8feafe9be1f0 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4409,7 +4409,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, INIT_LIST_HEAD(&obj->ring_list); INIT_LIST_HEAD(&obj->obj_exec_link); INIT_LIST_HEAD(&obj->vma_list); - INIT_LIST_HEAD(&obj->batch_pool_list); + INIT_LIST_HEAD(&obj->batch_pool_link); obj->ops = ops; diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c b/drivers/gpu/drm/i915/i915_gem_batch_pool.c index 1287abf55b84..7bf2f3f2968e 100644 --- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c +++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c @@ -47,8 +47,12 @@ void i915_gem_batch_pool_init(struct drm_device *dev, struct i915_gem_batch_pool *pool) { + int n; + pool->dev = dev; - INIT_LIST_HEAD(&pool->cache_list); + + for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++) + INIT_LIST_HEAD(&pool->cache_list[n]); } /** @@ -59,16 +63,20 @@ void i915_gem_batch_pool_init(struct drm_device *dev, */ void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool) { + int n; + WARN_ON(!mutex_is_locked(&pool->dev->struct_mutex)); - while (!list_empty(&pool->cache_list)) { - struct drm_i915_gem_object *obj = - list_first_entry(&pool->cache_list, - struct drm_i915_gem_object, - batch_pool_list); + for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++) { + while (!list_empty(&pool->cache_list[n])) { + struct drm_i915_gem_object *obj = + list_first_entry(&pool->cache_list[n], + struct drm_i915_gem_object, + batch_pool_link); - list_del(&obj->batch_pool_list); - drm_gem_object_unreference(&obj->base); + list_del(&obj->batch_pool_link); + drm_gem_object_unreference(&obj->base); + } } } @@ -91,28 +99,33 @@ i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, { struct drm_i915_gem_object *obj = NULL; struct drm_i915_gem_object *tmp, *next; + struct list_head *list; + int n; WARN_ON(!mutex_is_locked(&pool->dev->struct_mutex)); - list_for_each_entry_safe(tmp, next, - &pool->cache_list, batch_pool_list) { + /* Compute a power-of-two bucket, but throw everything greater than + * 16KiB into the same bucket: i.e. the the buckets hold objects of + * (1 page, 2 pages, 4 pages, 8+ pages). + */ + n = fls(size >> PAGE_SHIFT) - 1; + if (n >= ARRAY_SIZE(pool->cache_list)) + n = ARRAY_SIZE(pool->cache_list) - 1; + list = &pool->cache_list[n]; + + list_for_each_entry_safe(tmp, next, list, batch_pool_link) { /* The batches are strictly LRU ordered */ if (tmp->active) break; /* While we're looping, do some clean up */ if (tmp->madv == __I915_MADV_PURGED) { - list_del(&tmp->batch_pool_list); + list_del(&tmp->batch_pool_link); drm_gem_object_unreference(&tmp->base); continue; } - /* - * Select a buffer that is at least as big as needed - * but not 'too much' bigger. A better way to do this - * might be to bucket the pool objects based on size. - */ - if (tmp->base.size >= size && tmp->base.size <= 2 * size) { + if (tmp->base.size >= size) { obj = tmp; break; } @@ -132,7 +145,7 @@ i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, obj->madv = I915_MADV_DONTNEED; } - list_move_tail(&obj->batch_pool_list, &pool->cache_list); + list_move_tail(&obj->batch_pool_link, list); i915_gem_object_pin_pages(obj); return obj; } diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.h b/drivers/gpu/drm/i915/i915_gem_batch_pool.h index 5ed70ef6a887..848e90703eed 100644 --- a/drivers/gpu/drm/i915/i915_gem_batch_pool.h +++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.h @@ -29,7 +29,7 @@ struct i915_gem_batch_pool { struct drm_device *dev; - struct list_head cache_list; + struct list_head cache_list[4]; }; /* i915_gem_batch_pool.c */ -- cgit v1.2.3 From 481a3d43b94f30c36746dd7861e8de052cf4c6c9 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:39 +0100 Subject: drm/i915: Include active flag when describing objects in debugfs Since we use obj->active as a hint in many places throughout the code, knowing its state in debugfs is extremely useful. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 11eebc28775a..e87f031abc99 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -123,8 +123,9 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) struct i915_vma *vma; int pin_count = 0; - seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s", + seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s", &obj->base, + obj->active ? "*" : " ", get_pin_flag(obj), get_tiling_flag(obj), get_global_flag(obj), -- cgit v1.2.3 From b0da1b79aa4136c955710e755857a196a8226a1b Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:40 +0100 Subject: drm/i915: Suppress empty lines from debugfs/i915_gem_objects This is just so that I don't have to read about the batch pool on systems that are not using it! Rather than using a newline between the kernel clients and userspace clients, just distinguish the internal allocations with a '[k]' Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index e87f031abc99..fbba5c267f5d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -362,16 +362,18 @@ static int per_file_stats(int id, void *ptr, void *data) return 0; } -#define print_file_stats(m, name, stats) \ - seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \ - name, \ - stats.count, \ - stats.total, \ - stats.active, \ - stats.inactive, \ - stats.global, \ - stats.shared, \ - stats.unbound) +#define print_file_stats(m, name, stats) do { \ + if (stats.count) \ + seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \ + name, \ + stats.count, \ + stats.total, \ + stats.active, \ + stats.inactive, \ + stats.global, \ + stats.shared, \ + stats.unbound); \ +} while (0) static void print_batch_pool_stats(struct seq_file *m, struct drm_i915_private *dev_priv) @@ -392,7 +394,7 @@ static void print_batch_pool_stats(struct seq_file *m, } } - print_file_stats(m, "batch pool", stats); + print_file_stats(m, "[k]batch pool", stats); } #define count_vmas(list, member) do { \ @@ -478,8 +480,6 @@ static int i915_gem_object_info(struct seq_file *m, void* data) seq_putc(m, '\n'); print_batch_pool_stats(m, dev_priv); - - seq_putc(m, '\n'); list_for_each_entry_reverse(file, &dev->filelist, lhead) { struct file_stats stats; struct task_struct *task; -- cgit v1.2.3 From 94f8cf109e313e7758dff6cbc0357f6b07f83375 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:47 +0100 Subject: drm/i915: Record ring->start address in error state This is mostly useful for execlists where the rings switch between contexts (and so checking that the ring's start register matches the context is important). Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++++++---- 2 files changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6e0a0ae34a3f..f4daa3d3c126 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -455,6 +455,7 @@ struct drm_i915_error_state { u32 semaphore_seqno[I915_NUM_RINGS - 1]; /* Register state */ + u32 start; u32 tail; u32 head; u32 ctl; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 1d4e60df8883..ac22614dbb0e 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -251,10 +251,11 @@ static void i915_ring_error_state(struct drm_i915_error_state_buf *m, return; err_printf(m, "%s command stream:\n", ring_str(ring_idx)); - err_printf(m, " HEAD: 0x%08x\n", ring->head); - err_printf(m, " TAIL: 0x%08x\n", ring->tail); - err_printf(m, " CTL: 0x%08x\n", ring->ctl); - err_printf(m, " HWS: 0x%08x\n", ring->hws); + err_printf(m, " START: 0x%08x\n", ring->start); + err_printf(m, " HEAD: 0x%08x\n", ring->head); + err_printf(m, " TAIL: 0x%08x\n", ring->tail); + err_printf(m, " CTL: 0x%08x\n", ring->ctl); + err_printf(m, " HWS: 0x%08x\n", ring->hws); err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); @@ -883,6 +884,7 @@ static void i915_record_ring_state(struct drm_device *dev, ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); ering->seqno = ring->get_seqno(ring, false); ering->acthd = intel_ring_get_active_head(ring); + ering->start = I915_READ_START(ring); ering->head = I915_READ_HEAD(ring); ering->tail = I915_READ_TAIL(ring); ering->ctl = I915_READ_CTL(ring); -- cgit v1.2.3 From ec565b3c1589566a15d20e76def021bf4c17ee6b Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:23 +0100 Subject: drm/i915: Remove _entry from PPGTT page structures Lets try to keep this consistent: Page Directory Pointer (PDP). Page Directory (PD), also known as page directory pointer entries. Page Table (PT), also known as page directory entries. s/struct i915_page_table_entry/struct i915_page_table/ s/struct i915_page_directory_entry/struct i915_page_directory/ s/struct i915_page_directory_pointer_entry/struct i915_page_directory_pointer/ Suggested-by: Mika Kuoppala Signed-off-by: Michel Thierry Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 56 ++++++++++++++++++------------------- drivers/gpu/drm/i915/i915_gem_gtt.h | 16 +++++------ drivers/gpu/drm/i915/i915_trace.h | 4 +-- 3 files changed, 38 insertions(+), 38 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 0239fbff7bf7..c1a2fab9c790 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -320,7 +320,7 @@ static inline int i915_dma_map_page_single(struct page *page, return 0; } -static void unmap_and_free_pt(struct i915_page_table_entry *pt, +static void unmap_and_free_pt(struct i915_page_table *pt, struct drm_device *dev) { if (WARN_ON(!pt->page)) @@ -332,9 +332,9 @@ static void unmap_and_free_pt(struct i915_page_table_entry *pt, kfree(pt); } -static struct i915_page_table_entry *alloc_pt_single(struct drm_device *dev) +static struct i915_page_table *alloc_pt_single(struct drm_device *dev) { - struct i915_page_table_entry *pt; + struct i915_page_table *pt; const size_t count = INTEL_INFO(dev)->gen >= 8 ? GEN8_PTES : GEN6_PTES; int ret = -ENOMEM; @@ -383,7 +383,7 @@ fail_bitmap: * * Return: 0 if allocation succeeded. */ -static int alloc_pt_range(struct i915_page_directory_entry *pd, uint16_t pde, size_t count, +static int alloc_pt_range(struct i915_page_directory *pd, uint16_t pde, size_t count, struct drm_device *dev) { int i, ret; @@ -393,7 +393,7 @@ static int alloc_pt_range(struct i915_page_directory_entry *pd, uint16_t pde, si return -EINVAL; for (i = pde; i < pde + count; i++) { - struct i915_page_table_entry *pt = alloc_pt_single(dev); + struct i915_page_table *pt = alloc_pt_single(dev); if (IS_ERR(pt)) { ret = PTR_ERR(pt); @@ -413,7 +413,7 @@ err_out: return ret; } -static void unmap_and_free_pd(struct i915_page_directory_entry *pd) +static void unmap_and_free_pd(struct i915_page_directory *pd) { if (pd->page) { __free_page(pd->page); @@ -421,9 +421,9 @@ static void unmap_and_free_pd(struct i915_page_directory_entry *pd) } } -static struct i915_page_directory_entry *alloc_pd_single(void) +static struct i915_page_directory *alloc_pd_single(void) { - struct i915_page_directory_entry *pd; + struct i915_page_directory *pd; pd = kzalloc(sizeof(*pd), GFP_KERNEL); if (!pd) @@ -497,8 +497,8 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm, I915_CACHE_LLC, use_scratch); while (num_entries) { - struct i915_page_directory_entry *pd; - struct i915_page_table_entry *pt; + struct i915_page_directory *pd; + struct i915_page_table *pt; struct page *page_table; if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) @@ -559,8 +559,8 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, break; if (pt_vaddr == NULL) { - struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[pdpe]; - struct i915_page_table_entry *pt = pd->page_table[pde]; + struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe]; + struct i915_page_table *pt = pd->page_table[pde]; struct page *page_table = pt->page; pt_vaddr = kmap_atomic(page_table); @@ -588,7 +588,7 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, } } -static void gen8_free_page_tables(struct i915_page_directory_entry *pd, struct drm_device *dev) +static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev) { int i; @@ -632,8 +632,8 @@ static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) PCI_DMA_BIDIRECTIONAL); for (j = 0; j < I915_PDES; j++) { - struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i]; - struct i915_page_table_entry *pt; + struct i915_page_directory *pd = ppgtt->pdp.page_directory[i]; + struct i915_page_table *pt; dma_addr_t addr; if (WARN_ON(!pd->page_table[j])) @@ -747,8 +747,8 @@ static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, const int pt) { dma_addr_t pt_addr; - struct i915_page_directory_entry *pdir = ppgtt->pdp.page_directory[pd]; - struct i915_page_table_entry *ptab = pdir->page_table[pt]; + struct i915_page_directory *pdir = ppgtt->pdp.page_directory[pd]; + struct i915_page_table *ptab = pdir->page_table[pt]; struct page *p = ptab->page; int ret; @@ -815,11 +815,11 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) * will never need to touch the PDEs again. */ for (i = 0; i < GEN8_LEGACY_PDPES; i++) { - struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i]; + struct i915_page_directory *pd = ppgtt->pdp.page_directory[i]; gen8_pde_t *pd_vaddr; pd_vaddr = kmap_atomic(ppgtt->pdp.page_directory[i]->page); for (j = 0; j < I915_PDES; j++) { - struct i915_page_table_entry *pt = pd->page_table[j]; + struct i915_page_table *pt = pd->page_table[j]; dma_addr_t addr = pt->daddr; pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, I915_CACHE_LLC); @@ -914,8 +914,8 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) } /* Write pde (index) from the page directory @pd to the page table @pt */ -static void gen6_write_pde(struct i915_page_directory_entry *pd, - const int pde, struct i915_page_table_entry *pt) +static void gen6_write_pde(struct i915_page_directory *pd, + const int pde, struct i915_page_table *pt) { /* Caller needs to make sure the write completes if necessary */ struct i915_hw_ppgtt *ppgtt = @@ -931,10 +931,10 @@ static void gen6_write_pde(struct i915_page_directory_entry *pd, /* Write all the page tables found in the ppgtt structure to incrementing page * directories. */ static void gen6_write_page_range(struct drm_i915_private *dev_priv, - struct i915_page_directory_entry *pd, + struct i915_page_directory *pd, uint32_t start, uint32_t length) { - struct i915_page_table_entry *pt; + struct i915_page_table *pt; uint32_t pde, temp; gen6_for_each_pde(pt, pd, start, length, temp, pde) @@ -1169,7 +1169,7 @@ static inline void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) } static void gen6_initialize_pt(struct i915_address_space *vm, - struct i915_page_table_entry *pt) + struct i915_page_table *pt) { gen6_pte_t *pt_vaddr, scratch_pte; int i; @@ -1195,7 +1195,7 @@ static int gen6_alloc_va_range(struct i915_address_space *vm, struct drm_i915_private *dev_priv = dev->dev_private; struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt, base); - struct i915_page_table_entry *pt; + struct i915_page_table *pt; const uint32_t start_save = start, length_save = length; uint32_t pde, temp; int ret; @@ -1263,7 +1263,7 @@ static int gen6_alloc_va_range(struct i915_address_space *vm, unwind_out: for_each_set_bit(pde, new_page_tables, I915_PDES) { - struct i915_page_table_entry *pt = ppgtt->pd.page_table[pde]; + struct i915_page_table *pt = ppgtt->pd.page_table[pde]; ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; unmap_and_free_pt(pt, vm->dev); @@ -1278,7 +1278,7 @@ static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) int i; for (i = 0; i < ppgtt->num_pd_entries; i++) { - struct i915_page_table_entry *pt = ppgtt->pd.page_table[i]; + struct i915_page_table *pt = ppgtt->pd.page_table[i]; if (pt != ppgtt->scratch_pt) unmap_and_free_pt(ppgtt->pd.page_table[i], ppgtt->base.dev); @@ -1358,7 +1358,7 @@ static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, uint64_t start, uint64_t length) { - struct i915_page_table_entry *unused; + struct i915_page_table *unused; uint32_t pde, temp; gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index fc03c99317c9..1384789673e3 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -206,26 +206,26 @@ struct i915_vma { u32 flags); }; -struct i915_page_table_entry { +struct i915_page_table { struct page *page; dma_addr_t daddr; unsigned long *used_ptes; }; -struct i915_page_directory_entry { +struct i915_page_directory { struct page *page; /* NULL for GEN6-GEN7 */ union { uint32_t pd_offset; dma_addr_t daddr; }; - struct i915_page_table_entry *page_table[I915_PDES]; /* PDEs */ + struct i915_page_table *page_table[I915_PDES]; /* PDEs */ }; -struct i915_page_directory_pointer_entry { +struct i915_page_directory_pointer { /* struct page *page; */ - struct i915_page_directory_entry *page_directory[GEN8_LEGACY_PDPES]; + struct i915_page_directory *page_directory[GEN8_LEGACY_PDPES]; }; struct i915_address_space { @@ -317,11 +317,11 @@ struct i915_hw_ppgtt { unsigned num_pd_entries; unsigned num_pd_pages; /* gen8+ */ union { - struct i915_page_directory_pointer_entry pdp; - struct i915_page_directory_entry pd; + struct i915_page_directory_pointer pdp; + struct i915_page_directory pd; }; - struct i915_page_table_entry *scratch_pt; + struct i915_page_table *scratch_pt; struct drm_i915_file_private *file_priv; diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index b3070a4501ab..4574f0cc9b1c 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -221,7 +221,7 @@ DEFINE_EVENT(i915_page_table_entry, i915_page_table_entry_alloc, DECLARE_EVENT_CLASS(i915_page_table_entry_update, TP_PROTO(struct i915_address_space *vm, u32 pde, - struct i915_page_table_entry *pt, u32 first, u32 count, u32 bits), + struct i915_page_table *pt, u32 first, u32 count, u32 bits), TP_ARGS(vm, pde, pt, first, count, bits), TP_STRUCT__entry( @@ -251,7 +251,7 @@ DECLARE_EVENT_CLASS(i915_page_table_entry_update, DEFINE_EVENT(i915_page_table_entry_update, i915_page_table_entry_map, TP_PROTO(struct i915_address_space *vm, u32 pde, - struct i915_page_table_entry *pt, u32 first, u32 count, u32 bits), + struct i915_page_table *pt, u32 first, u32 count, u32 bits), TP_ARGS(vm, pde, pt, first, count, bits) ); -- cgit v1.2.3 From 9c57f07001f2c093e0455137465242b0bbb6fb66 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:24 +0100 Subject: drm/i915: Remove unnecessary gen8_ppgtt_unmap_pages We are already unmapping them in gen8_ppgtt_free. This function became redundant since commit 06fda602dbca9c59d87db7da71192e4b54c9f5ff ("drm/i915: Create page table allocators"). Cc: Mika Kuoppala Signed-off-by: Michel Thierry Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 34 ---------------------------------- 1 file changed, 34 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index c1a2fab9c790..a7d364ae0518 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -617,44 +617,11 @@ static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) } } -static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) -{ - struct pci_dev *hwdev = ppgtt->base.dev->pdev; - int i, j; - - for (i = 0; i < ppgtt->num_pd_pages; i++) { - /* TODO: In the future we'll support sparse mappings, so this - * will have to change. */ - if (!ppgtt->pdp.page_directory[i]->daddr) - continue; - - pci_unmap_page(hwdev, ppgtt->pdp.page_directory[i]->daddr, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL); - - for (j = 0; j < I915_PDES; j++) { - struct i915_page_directory *pd = ppgtt->pdp.page_directory[i]; - struct i915_page_table *pt; - dma_addr_t addr; - - if (WARN_ON(!pd->page_table[j])) - continue; - - pt = pd->page_table[j]; - addr = pt->daddr; - - if (addr) - pci_unmap_page(hwdev, addr, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL); - } - } -} - static void gen8_ppgtt_cleanup(struct i915_address_space *vm) { struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt, base); - gen8_ppgtt_unmap_pages(ppgtt); gen8_ppgtt_free(ppgtt); } @@ -851,7 +818,6 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) return 0; bail: - gen8_ppgtt_unmap_pages(ppgtt); gen8_ppgtt_free(ppgtt); return ret; } -- cgit v1.2.3 From 5a8e9943528dd84315db2e9dfd7330bcbb872414 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:25 +0100 Subject: drm/i915/gen8: Initialize page tables Similar to gen6, while setting up a page table, make all entries of the pt point to the scratch page before mapping; this is to be safe in case of out of bound access or proactive prefetch. Systems without LLC require an explicit flush. v2: Expanded commit text and fixed indentation (Mika) Signed-off-by: Michel Thierry Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index a7d364ae0518..c2045bd45e5e 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -332,6 +332,24 @@ static void unmap_and_free_pt(struct i915_page_table *pt, kfree(pt); } +static void gen8_initialize_pt(struct i915_address_space *vm, + struct i915_page_table *pt) +{ + gen8_pte_t *pt_vaddr, scratch_pte; + int i; + + pt_vaddr = kmap_atomic(pt->page); + scratch_pte = gen8_pte_encode(vm->scratch.addr, + I915_CACHE_LLC, true); + + for (i = 0; i < GEN8_PTES; i++) + pt_vaddr[i] = scratch_pte; + + if (!HAS_LLC(vm->dev)) + drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); + kunmap_atomic(pt_vaddr); +} + static struct i915_page_table *alloc_pt_single(struct drm_device *dev) { struct i915_page_table *pt; @@ -429,7 +447,7 @@ static struct i915_page_directory *alloc_pd_single(void) if (!pd) return ERR_PTR(-ENOMEM); - pd->page = alloc_page(GFP_KERNEL | __GFP_ZERO); + pd->page = alloc_page(GFP_KERNEL); if (!pd->page) { kfree(pd); return ERR_PTR(-ENOMEM); @@ -719,6 +737,8 @@ static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, struct page *p = ptab->page; int ret; + gen8_initialize_pt(&ppgtt->base, ptab); + pt_addr = pci_map_page(ppgtt->base.dev->pdev, p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); -- cgit v1.2.3 From 9271d959dc03fc7514030e22280cdbd6ca763ca5 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:26 +0100 Subject: drm/i915/gen8: Add dynamic allocation macros and helper functions Similar to gen6, we will use for_each_pde/for_each_pdpe and pte/pde/pdpe_index to iterate over these new structures. v2: Match trace_i915_va_teardown params v3: Multiple rebases. v4: Updated to use unmap_and_free_pt. v5: teardown_va_range logic no longer needed. v6: Rebase after s/page_tables/page_table/. v7: Renamed commit to match what it does now (it was "Use dynamic allocation idioms on free"). v8: Prevent (harmless) out of range access in gen8_for_each_pde and gen8_for_each_pdpe_e. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) Reviewed-by: Mika Kuoppala [danvet: s/BUG/WARN/] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.h | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 1384789673e3..63fda82452ec 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -397,6 +397,58 @@ static inline uint32_t gen6_pde_index(uint32_t addr) return i915_pde_index(addr, GEN6_PDE_SHIFT); } +/* Equivalent to the gen6 version, For each pde iterates over every pde + * between from start until start + length. On gen8+ it simply iterates + * over every page directory entry in a page directory. + */ +#define gen8_for_each_pde(pt, pd, start, length, temp, iter) \ + for (iter = gen8_pde_index(start); \ + pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ + iter++, \ + temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \ + temp = min(temp, length), \ + start += temp, length -= temp) + +#define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ + for (iter = gen8_pdpe_index(start); \ + pd = (pdp)->page_directory[iter], length > 0 && iter < GEN8_LEGACY_PDPES; \ + iter++, \ + temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ + temp = min(temp, length), \ + start += temp, length -= temp) + +/* Clamp length to the next page_directory boundary */ +static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length) +{ + uint64_t next_pd = ALIGN(start + 1, 1 << GEN8_PDPE_SHIFT); + + if (next_pd > (start + length)) + return length; + + return next_pd - start; +} + +static inline uint32_t gen8_pte_index(uint64_t address) +{ + return i915_pte_index(address, GEN8_PDE_SHIFT); +} + +static inline uint32_t gen8_pde_index(uint64_t address) +{ + return i915_pde_index(address, GEN8_PDE_SHIFT); +} + +static inline uint32_t gen8_pdpe_index(uint64_t address) +{ + return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; +} + +static inline uint32_t gen8_pml4e_index(uint64_t address) +{ + WARN_ON(1); /* For 64B */ + return 0; +} + int i915_gem_gtt_init(struct drm_device *dev); void i915_gem_init_global_gtt(struct drm_device *dev); void i915_global_gtt_cleanup(struct drm_device *dev); -- cgit v1.2.3 From 69876bed7e008f5fe01538a2d47c09f2862129d0 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:27 +0100 Subject: drm/i915/gen8: page directories rework allocation Start using gen8_for_each_pdpe macro to allocate the page directories. Similar to PTs, while setting up a page directory, make all entries of the pd point to the scratch pd before mapping (and make all its entries point to the scratch page); this is to be safe in case of out of bound access or proactive prefetch. Systems without LLC require an explicit flush. v2: Rebased after s/free_pt_*/unmap_and_free_pt/ change. v3: Rebased after teardown va range logic was removed. v4: Keep setting up all page directories for systems with less than 4GB of memory. v5: Initialize PDs. (Mika) v6: Initialize also the extra PDs from systems with less than 4GB of memory. (Mika) Cc: Mika Kuoppala Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 100 ++++++++++++++++++++++++++++++------ 1 file changed, 85 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index c2045bd45e5e..e5770189ebff 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -606,6 +606,36 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, } } +static void __gen8_do_map_pt(gen8_pde_t * const pde, + struct i915_page_table *pt, + struct drm_device *dev) +{ + gen8_pde_t entry = + gen8_pde_encode(dev, pt->daddr, I915_CACHE_LLC); + *pde = entry; +} + +static void gen8_initialize_pd(struct i915_address_space *vm, + struct i915_page_directory *pd) +{ + struct i915_hw_ppgtt *ppgtt = + container_of(vm, struct i915_hw_ppgtt, base); + gen8_pde_t *page_directory; + struct i915_page_table *pt; + int i; + + page_directory = kmap_atomic(pd->page); + pt = ppgtt->scratch_pt; + for (i = 0; i < I915_PDES; i++) + /* Map the PDE to the page table */ + __gen8_do_map_pt(page_directory + i, pt, vm->dev); + + if (!HAS_LLC(vm->dev)) + drm_clflush_virt_range(page_directory, PAGE_SIZE); + + kunmap_atomic(page_directory); +} + static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev) { int i; @@ -633,6 +663,8 @@ static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); unmap_and_free_pd(ppgtt->pdp.page_directory[i]); } + + unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); } static void gen8_ppgtt_cleanup(struct i915_address_space *vm) @@ -663,25 +695,55 @@ unwind_out: return -ENOMEM; } -static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, - const int max_pdp) +static int gen8_ppgtt_alloc_page_directories(struct i915_page_directory_pointer *pdp, + uint64_t start, + uint64_t length) { - int i; + struct i915_hw_ppgtt *ppgtt = + container_of(pdp, struct i915_hw_ppgtt, pdp); + struct i915_page_directory *unused; + uint64_t temp; + uint32_t pdpe; + + /* FIXME: PPGTT container_of won't work for 64b */ + WARN_ON((start + length) > 0x800000000ULL); + + gen8_for_each_pdpe(unused, pdp, start, length, temp, pdpe) { + WARN_ON(unused); + pdp->page_directory[pdpe] = alloc_pd_single(); + if (IS_ERR(ppgtt->pdp.page_directory[pdpe])) + goto unwind_out; + + gen8_initialize_pd(&ppgtt->base, + ppgtt->pdp.page_directory[pdpe]); + ppgtt->num_pd_pages++; + } - for (i = 0; i < max_pdp; i++) { - ppgtt->pdp.page_directory[i] = alloc_pd_single(); - if (IS_ERR(ppgtt->pdp.page_directory[i])) + /* XXX: Still alloc all page directories in systems with less than + * 4GB of memory. This won't be needed after a subsequent patch. + */ + while (ppgtt->num_pd_pages < GEN8_LEGACY_PDPES) { + ppgtt->pdp.page_directory[ppgtt->num_pd_pages] = alloc_pd_single(); + if (IS_ERR(ppgtt->pdp.page_directory[ppgtt->num_pd_pages])) goto unwind_out; + + gen8_initialize_pd(&ppgtt->base, + ppgtt->pdp.page_directory[ppgtt->num_pd_pages]); + pdpe++; + ppgtt->num_pd_pages++; } - ppgtt->num_pd_pages = max_pdp; BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPES); return 0; unwind_out: - while (i--) - unmap_and_free_pd(ppgtt->pdp.page_directory[i]); + while (pdpe--) { + unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe]); + ppgtt->num_pd_pages--; + } + + WARN_ON(ppgtt->num_pd_pages); return -ENOMEM; } @@ -691,7 +753,8 @@ static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, { int ret; - ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); + ret = gen8_ppgtt_alloc_page_directories(&ppgtt->pdp, ppgtt->base.start, + ppgtt->base.total); if (ret) return ret; @@ -769,6 +832,17 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) if (size % (1<<30)) DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); + ppgtt->base.start = 0; + /* This is the area that we advertise as usable for the caller */ + ppgtt->base.total = max_pdp * I915_PDES * GEN8_PTES * PAGE_SIZE; + WARN_ON(ppgtt->base.total == 0); + + ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); + if (IS_ERR(ppgtt->scratch_pt)) + return PTR_ERR(ppgtt->scratch_pt); + + gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); + /* 1. Do all our allocations for page directories and page tables. * We allocate more than was asked so that we can point the unused parts * to valid entries that point to scratch page. Dynamic page tables @@ -794,7 +868,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) } /* - * 3. Map all the page directory entires to point to the page tables + * 3. Map all the page directory entries to point to the page tables * we've allocated. * * For now, the PPGTT helper functions all require that the PDEs are @@ -820,10 +894,6 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) ppgtt->base.clear_range = gen8_ppgtt_clear_range; ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; ppgtt->base.cleanup = gen8_ppgtt_cleanup; - ppgtt->base.start = 0; - - /* This is the area that we advertise as usable for the caller */ - ppgtt->base.total = max_pdp * I915_PDES * GEN8_PTES * PAGE_SIZE; /* Set all ptes to a valid scratch page. Also above requested space */ ppgtt->base.clear_range(&ppgtt->base, 0, -- cgit v1.2.3 From 5441f0cbe119496c36fd1c7a7971ecd0e0578ca6 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:28 +0100 Subject: drm/i915/gen8: pagetable allocation rework Start using gen8_for_each_pde macro to allocate page tables. v2: teardown_va_range references removed. v3: Rebase after s/page_tables/page_table/. v4: Keep setting up page tables for all page directories in systems with less than 4GB of memory. v5: Also initialize the page tables. (Mika) v6: Initialize all page tables, including the extra ones from systems with less than 4GB of memory. (Mika) Cc: Mika Kuoppala Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 83 ++++++++++++++++++++++++++----------- 1 file changed, 59 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index e5770189ebff..aad3d6ffbabc 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -675,22 +675,41 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm) gen8_ppgtt_free(ppgtt); } -static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) +static int gen8_ppgtt_alloc_pagetabs(struct i915_page_directory *pd, + uint64_t start, + uint64_t length, + struct i915_address_space *vm) { - int i, ret; + struct i915_page_table *unused; + uint64_t temp; + uint32_t pde; - for (i = 0; i < ppgtt->num_pd_pages; i++) { - ret = alloc_pt_range(ppgtt->pdp.page_directory[i], - 0, I915_PDES, ppgtt->base.dev); - if (ret) + gen8_for_each_pde(unused, pd, start, length, temp, pde) { + WARN_ON(unused); + pd->page_table[pde] = alloc_pt_single(vm->dev); + if (IS_ERR(pd->page_table[pde])) + goto unwind_out; + + gen8_initialize_pt(vm, pd->page_table[pde]); + } + + /* XXX: Still alloc all page tables in systems with less than + * 4GB of memory. This won't be needed after a subsequent patch. + */ + while (pde < I915_PDES) { + pd->page_table[pde] = alloc_pt_single(vm->dev); + if (IS_ERR(pd->page_table[pde])) goto unwind_out; + + gen8_initialize_pt(vm, pd->page_table[pde]); + pde++; } return 0; unwind_out: - while (i--) - gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); + while (pde--) + unmap_and_free_pt(pd->page_table[pde], vm->dev); return -ENOMEM; } @@ -749,20 +768,42 @@ unwind_out: } static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, - const int max_pdp) + uint64_t start, + uint64_t length) { + struct i915_page_directory *pd; + uint64_t temp; + uint32_t pdpe; int ret; - ret = gen8_ppgtt_alloc_page_directories(&ppgtt->pdp, ppgtt->base.start, - ppgtt->base.total); + ret = gen8_ppgtt_alloc_page_directories(&ppgtt->pdp, start, length); if (ret) return ret; - ret = gen8_ppgtt_allocate_page_tables(ppgtt); - if (ret) - goto err_out; + gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { + ret = gen8_ppgtt_alloc_pagetabs(pd, start, length, + &ppgtt->base); + if (ret) + goto err_out; + + ppgtt->num_pd_entries += I915_PDES; + } - ppgtt->num_pd_entries = max_pdp * I915_PDES; + /* XXX: We allocated all page directories in systems with less than + * 4GB of memory. So initalize page tables of all PDPs. + * This won't be needed after the next patch. + */ + while (pdpe < GEN8_LEGACY_PDPES) { + ret = gen8_ppgtt_alloc_pagetabs(ppgtt->pdp.page_directory[pdpe], start, length, + &ppgtt->base); + if (ret) + goto err_out; + + ppgtt->num_pd_entries += I915_PDES; + pdpe++; + } + + WARN_ON(pdpe > ppgtt->num_pd_pages); return 0; @@ -833,9 +874,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); ppgtt->base.start = 0; - /* This is the area that we advertise as usable for the caller */ - ppgtt->base.total = max_pdp * I915_PDES * GEN8_PTES * PAGE_SIZE; - WARN_ON(ppgtt->base.total == 0); + ppgtt->base.total = size; ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); if (IS_ERR(ppgtt->scratch_pt)) @@ -843,12 +882,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); - /* 1. Do all our allocations for page directories and page tables. - * We allocate more than was asked so that we can point the unused parts - * to valid entries that point to scratch page. Dynamic page tables - * will fix this eventually. - */ - ret = gen8_ppgtt_alloc(ppgtt, GEN8_LEGACY_PDPES); + /* 1. Do all our allocations for page directories and page tables. */ + ret = gen8_ppgtt_alloc(ppgtt, ppgtt->base.start, ppgtt->base.total); if (ret) return ret; -- cgit v1.2.3 From 7cb6d7ac635ab0c80607e6ffaf8682d48752523f Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:29 +0100 Subject: drm/i915/gen8: Update pdp switch and point unused PDPs to scratch page One important part of this patch is we now write a scratch page directory into any unused PDP descriptors. This matters for 2 reasons, first, we're not allowed to just use 0, or an invalid pointer, and second, we must wipe out any previous contents from the last context. The latter point only matters with full PPGTT. The former point only effect platforms with less than 4GB memory. v2: Updated commit message to point that we must set unused PDPs to the scratch page. v3: Unmap scratch_pd in gen8_ppgtt_free. v4: Initialize scratch_pd. (Mika) Cc: Mika Kuoppala Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +++++++++++++++++++++----------- drivers/gpu/drm/i915/i915_gem_gtt.h | 1 + 2 files changed, 22 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index aad3d6ffbabc..4b91cc18eef3 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -457,8 +457,9 @@ static struct i915_page_directory *alloc_pd_single(void) } /* Broadwell Page Directory Pointer Descriptors */ -static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, - uint64_t val) +static int gen8_write_pdp(struct intel_engine_cs *ring, + unsigned entry, + dma_addr_t addr) { int ret; @@ -470,10 +471,10 @@ static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); - intel_ring_emit(ring, (u32)(val >> 32)); + intel_ring_emit(ring, upper_32_bits(addr)); intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); - intel_ring_emit(ring, (u32)(val)); + intel_ring_emit(ring, lower_32_bits(addr)); intel_ring_advance(ring); return 0; @@ -484,12 +485,12 @@ static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, { int i, ret; - /* bit of a hack to find the actual last used pd */ - int used_pd = ppgtt->num_pd_entries / I915_PDES; - - for (i = used_pd - 1; i >= 0; i--) { - dma_addr_t addr = ppgtt->pdp.page_directory[i]->daddr; - ret = gen8_write_pdp(ring, i, addr); + for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { + struct i915_page_directory *pd = ppgtt->pdp.page_directory[i]; + dma_addr_t pd_daddr = pd ? pd->daddr : ppgtt->scratch_pd->daddr; + /* The page directory might be NULL, but we need to clear out + * whatever the previous context might have used. */ + ret = gen8_write_pdp(ring, i, pd_daddr); if (ret) return ret; } @@ -664,6 +665,7 @@ static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) unmap_and_free_pd(ppgtt->pdp.page_directory[i]); } + unmap_and_free_pd(ppgtt->scratch_pd); unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); } @@ -880,12 +882,20 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) if (IS_ERR(ppgtt->scratch_pt)) return PTR_ERR(ppgtt->scratch_pt); + ppgtt->scratch_pd = alloc_pd_single(); + if (IS_ERR(ppgtt->scratch_pd)) + return PTR_ERR(ppgtt->scratch_pd); + gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); + gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd); /* 1. Do all our allocations for page directories and page tables. */ ret = gen8_ppgtt_alloc(ppgtt, ppgtt->base.start, ppgtt->base.total); - if (ret) + if (ret) { + unmap_and_free_pd(ppgtt->scratch_pd); + unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); return ret; + } /* * 2. Create DMA mappings for the page directories and page tables. diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 63fda82452ec..acf8ed7f86ef 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -322,6 +322,7 @@ struct i915_hw_ppgtt { }; struct i915_page_table *scratch_pt; + struct i915_page_directory *scratch_pd; struct drm_i915_file_private *file_priv; -- cgit v1.2.3 From 09942c656b7f857e3fd875a20f5967d316a20c73 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:30 +0100 Subject: drm/i915: num_pd_pages/num_pd_entries isn't useful These values are never quite useful for dynamic allocations of the page tables. Getting rid of them will help prevent later confusion. v2: Updated to use unmap_and_free_pd functions. v3: Updated gen8_ppgtt_free after teardown logic was removed. v4: Rebase after s/page_tables/page_table/. v5: Keep allocating all page directories in GEN8+ systems with less than 4GB of memory. Updated gen6_for_all_pdes. v6: Prevent (harmless) out of range access in gen6_for_all_pdes. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 2 -- drivers/gpu/drm/i915/i915_gem_gtt.c | 68 ++++++++++--------------------------- drivers/gpu/drm/i915/i915_gem_gtt.h | 7 ++-- 3 files changed, 23 insertions(+), 54 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index fbba5c267f5d..e890728144b4 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2188,8 +2188,6 @@ static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) if (!ppgtt) return; - seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); - seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); for_each_ring(ring, dev_priv, unused) { seq_printf(m, "%s\n", ring->name); for (i = 0; i < 4; i++) { diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 4b91cc18eef3..c5ec35ac0733 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -657,7 +657,7 @@ static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) { int i; - for (i = 0; i < ppgtt->num_pd_pages; i++) { + for (i = 0; i < GEN8_LEGACY_PDPES; i++) { if (WARN_ON(!ppgtt->pdp.page_directory[i])) continue; @@ -737,34 +737,26 @@ static int gen8_ppgtt_alloc_page_directories(struct i915_page_directory_pointer gen8_initialize_pd(&ppgtt->base, ppgtt->pdp.page_directory[pdpe]); - ppgtt->num_pd_pages++; } /* XXX: Still alloc all page directories in systems with less than * 4GB of memory. This won't be needed after a subsequent patch. */ - while (ppgtt->num_pd_pages < GEN8_LEGACY_PDPES) { - ppgtt->pdp.page_directory[ppgtt->num_pd_pages] = alloc_pd_single(); - if (IS_ERR(ppgtt->pdp.page_directory[ppgtt->num_pd_pages])) + while (pdpe < GEN8_LEGACY_PDPES) { + ppgtt->pdp.page_directory[pdpe] = alloc_pd_single(); + if (IS_ERR(ppgtt->pdp.page_directory[pdpe])) goto unwind_out; gen8_initialize_pd(&ppgtt->base, - ppgtt->pdp.page_directory[ppgtt->num_pd_pages]); + ppgtt->pdp.page_directory[pdpe]); pdpe++; - ppgtt->num_pd_pages++; } - BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPES); - return 0; unwind_out: - while (pdpe--) { + while (pdpe--) unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe]); - ppgtt->num_pd_pages--; - } - - WARN_ON(ppgtt->num_pd_pages); return -ENOMEM; } @@ -787,8 +779,6 @@ static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, &ppgtt->base); if (ret) goto err_out; - - ppgtt->num_pd_entries += I915_PDES; } /* XXX: We allocated all page directories in systems with less than @@ -801,12 +791,9 @@ static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, if (ret) goto err_out; - ppgtt->num_pd_entries += I915_PDES; pdpe++; } - WARN_ON(pdpe > ppgtt->num_pd_pages); - return 0; err_out: @@ -868,8 +855,6 @@ static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, */ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) { - const int max_pdp = DIV_ROUND_UP(size, 1 << 30); - const int min_pt_pages = I915_PDES * max_pdp; int i, j, ret; if (size % (1<<30)) @@ -940,16 +925,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; ppgtt->base.cleanup = gen8_ppgtt_cleanup; - /* Set all ptes to a valid scratch page. Also above requested space */ - ppgtt->base.clear_range(&ppgtt->base, 0, - ppgtt->num_pd_pages * GEN8_PTES * PAGE_SIZE, - true); - - DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", - ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); - DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", - ppgtt->num_pd_entries, - (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); + ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); return 0; bail: @@ -959,26 +935,20 @@ bail: static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) { - struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; struct i915_address_space *vm = &ppgtt->base; - gen6_pte_t __iomem *pd_addr; + struct i915_page_table *unused; gen6_pte_t scratch_pte; uint32_t pd_entry; - int pte, pde; + uint32_t pte, pde, temp; + uint32_t start = ppgtt->base.start, length = ppgtt->base.total; scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); - pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + - ppgtt->pd.pd_offset / sizeof(gen6_pte_t); - - seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, - ppgtt->pd.pd_offset, - ppgtt->pd.pd_offset + ppgtt->num_pd_entries); - for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { + gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { u32 expected; gen6_pte_t *pt_vaddr; dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr; - pd_entry = readl(pd_addr + pde); + pd_entry = readl(ppgtt->pd_addr + pde); expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); if (pd_entry != expected) @@ -1376,13 +1346,12 @@ unwind_out: static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) { - int i; - - for (i = 0; i < ppgtt->num_pd_entries; i++) { - struct i915_page_table *pt = ppgtt->pd.page_table[i]; + struct i915_page_table *pt; + uint32_t pde; + gen6_for_all_pdes(pt, ppgtt, pde) { if (pt != ppgtt->scratch_pt) - unmap_and_free_pt(ppgtt->pd.page_table[i], ppgtt->base.dev); + unmap_and_free_pt(pt, ppgtt->base.dev); } unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); @@ -1443,7 +1412,6 @@ alloc: if (ppgtt->node.start < dev_priv->gtt.mappable_end) DRM_DEBUG("Forced to use aperture for PDEs\n"); - ppgtt->num_pd_entries = I915_PDES; return 0; err_out: @@ -1491,7 +1459,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing) if (aliasing) { /* preallocate all pts */ - ret = alloc_pt_range(&ppgtt->pd, 0, ppgtt->num_pd_entries, + ret = alloc_pt_range(&ppgtt->pd, 0, I915_PDES, ppgtt->base.dev); if (ret) { @@ -1505,7 +1473,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing) ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; ppgtt->base.cleanup = gen6_ppgtt_cleanup; ppgtt->base.start = 0; - ppgtt->base.total = ppgtt->num_pd_entries * GEN6_PTES * PAGE_SIZE; + ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; ppgtt->debug_dump = gen6_dump_ppgtt; ppgtt->pd.pd_offset = diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index acf8ed7f86ef..c3d5d40b78b2 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -314,8 +314,6 @@ struct i915_hw_ppgtt { struct kref ref; struct drm_mm_node node; unsigned long pd_dirty_rings; - unsigned num_pd_entries; - unsigned num_pd_pages; /* gen8+ */ union { struct i915_page_directory_pointer pdp; struct i915_page_directory pd; @@ -350,6 +348,11 @@ struct i915_hw_ppgtt { temp = min_t(unsigned, temp, length), \ start += temp, length -= temp) +#define gen6_for_all_pdes(pt, ppgtt, iter) \ + for (iter = 0; \ + pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \ + iter++) + static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) { const uint32_t mask = NUM_PTE(pde_shift) - 1; -- cgit v1.2.3 From c488dbbaa7626e510c3d2560e9aa2ddc45fb1e99 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:31 +0100 Subject: drm/i915: Extract PPGTT param from page_directory alloc This will be useful for when we move to 48b addressing, and the PDP isn't the root of the page table structure. v2: Rebase after changes for Gen8+ systems with less than 4GB of memory. v3: Rebase after Mika's code review. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index c5ec35ac0733..539060b8b66a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -716,12 +716,11 @@ unwind_out: return -ENOMEM; } -static int gen8_ppgtt_alloc_page_directories(struct i915_page_directory_pointer *pdp, +static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, + struct i915_page_directory_pointer *pdp, uint64_t start, uint64_t length) { - struct i915_hw_ppgtt *ppgtt = - container_of(pdp, struct i915_hw_ppgtt, pdp); struct i915_page_directory *unused; uint64_t temp; uint32_t pdpe; @@ -732,7 +731,7 @@ static int gen8_ppgtt_alloc_page_directories(struct i915_page_directory_pointer gen8_for_each_pdpe(unused, pdp, start, length, temp, pdpe) { WARN_ON(unused); pdp->page_directory[pdpe] = alloc_pd_single(); - if (IS_ERR(ppgtt->pdp.page_directory[pdpe])) + if (IS_ERR(pdp->page_directory[pdpe])) goto unwind_out; gen8_initialize_pd(&ppgtt->base, @@ -743,8 +742,8 @@ static int gen8_ppgtt_alloc_page_directories(struct i915_page_directory_pointer * 4GB of memory. This won't be needed after a subsequent patch. */ while (pdpe < GEN8_LEGACY_PDPES) { - ppgtt->pdp.page_directory[pdpe] = alloc_pd_single(); - if (IS_ERR(ppgtt->pdp.page_directory[pdpe])) + pdp->page_directory[pdpe] = alloc_pd_single(); + if (IS_ERR(pdp->page_directory[pdpe])) goto unwind_out; gen8_initialize_pd(&ppgtt->base, @@ -756,7 +755,7 @@ static int gen8_ppgtt_alloc_page_directories(struct i915_page_directory_pointer unwind_out: while (pdpe--) - unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe]); + unmap_and_free_pd(pdp->page_directory[pdpe]); return -ENOMEM; } @@ -770,7 +769,7 @@ static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, uint32_t pdpe; int ret; - ret = gen8_ppgtt_alloc_page_directories(&ppgtt->pdp, start, length); + ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length); if (ret) return ret; -- cgit v1.2.3 From e5815a2e0543f4381d3e8fa90f86c56ce68eee75 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:32 +0100 Subject: drm/i915/gen8: Split out mappings When we do dynamic page table allocations for gen8, we'll need to have more control over how and when we map page tables, similar to gen6. In particular, DMA mappings for page directories/tables occur at allocation time. This patch adds the functionality and calls it at init, which should have no functional change. The PDPEs are still a special case for now. We'll need a function for that in the future as well. v2: Handle renamed unmap_and_free_page functions. v3: Updated after teardown_va logic was removed. v4: Rebase after s/page_tables/page_table/. v5: No longer allocate all PDPs in GEN8+ systems with less than 4GB of memory, and update populate_lr_context to handle this new case (proper tracking will be added later in the patch series). v6: Assign lrc page directory pointer addresses using a macro. (Mika) Cc: Mika Kuoppala Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 224 +++++++++++------------------------- drivers/gpu/drm/i915/intel_lrc.c | 25 ++-- 2 files changed, 86 insertions(+), 163 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 539060b8b66a..1e1b42f8da42 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -333,7 +333,7 @@ static void unmap_and_free_pt(struct i915_page_table *pt, } static void gen8_initialize_pt(struct i915_address_space *vm, - struct i915_page_table *pt) + struct i915_page_table *pt) { gen8_pte_t *pt_vaddr, scratch_pte; int i; @@ -431,17 +431,20 @@ err_out: return ret; } -static void unmap_and_free_pd(struct i915_page_directory *pd) +static void unmap_and_free_pd(struct i915_page_directory *pd, + struct drm_device *dev) { if (pd->page) { + i915_dma_unmap_single(pd, dev); __free_page(pd->page); kfree(pd); } } -static struct i915_page_directory *alloc_pd_single(void) +static struct i915_page_directory *alloc_pd_single(struct drm_device *dev) { struct i915_page_directory *pd; + int ret; pd = kzalloc(sizeof(*pd), GFP_KERNEL); if (!pd) @@ -453,6 +456,13 @@ static struct i915_page_directory *alloc_pd_single(void) return ERR_PTR(-ENOMEM); } + ret = i915_dma_map_single(pd, dev); + if (ret) { + __free_page(pd->page); + kfree(pd); + return ERR_PTR(ret); + } + return pd; } @@ -637,6 +647,27 @@ static void gen8_initialize_pd(struct i915_address_space *vm, kunmap_atomic(page_directory); } +/* It's likely we'll map more than one pagetable at a time. This function will + * save us unnecessary kmap calls, but do no more functionally than multiple + * calls to map_pt. */ +static void gen8_map_pagetable_range(struct i915_page_directory *pd, + uint64_t start, + uint64_t length, + struct drm_device *dev) +{ + gen8_pde_t *page_directory = kmap_atomic(pd->page); + struct i915_page_table *pt; + uint64_t temp, pde; + + gen8_for_each_pde(pt, pd, start, length, temp, pde) + __gen8_do_map_pt(page_directory + pde, pt, dev); + + if (!HAS_LLC(dev)) + drm_clflush_virt_range(page_directory, PAGE_SIZE); + + kunmap_atomic(page_directory); +} + static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev) { int i; @@ -662,10 +693,10 @@ static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) continue; gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); - unmap_and_free_pd(ppgtt->pdp.page_directory[i]); + unmap_and_free_pd(ppgtt->pdp.page_directory[i], ppgtt->base.dev); } - unmap_and_free_pd(ppgtt->scratch_pd); + unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev); unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); } @@ -677,41 +708,30 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm) gen8_ppgtt_free(ppgtt); } -static int gen8_ppgtt_alloc_pagetabs(struct i915_page_directory *pd, +static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt, + struct i915_page_directory *pd, uint64_t start, - uint64_t length, - struct i915_address_space *vm) + uint64_t length) { + struct drm_device *dev = ppgtt->base.dev; struct i915_page_table *unused; uint64_t temp; uint32_t pde; gen8_for_each_pde(unused, pd, start, length, temp, pde) { WARN_ON(unused); - pd->page_table[pde] = alloc_pt_single(vm->dev); + pd->page_table[pde] = alloc_pt_single(dev); if (IS_ERR(pd->page_table[pde])) goto unwind_out; - gen8_initialize_pt(vm, pd->page_table[pde]); - } - - /* XXX: Still alloc all page tables in systems with less than - * 4GB of memory. This won't be needed after a subsequent patch. - */ - while (pde < I915_PDES) { - pd->page_table[pde] = alloc_pt_single(vm->dev); - if (IS_ERR(pd->page_table[pde])) - goto unwind_out; - - gen8_initialize_pt(vm, pd->page_table[pde]); - pde++; + gen8_initialize_pt(&ppgtt->base, pd->page_table[pde]); } return 0; unwind_out: while (pde--) - unmap_and_free_pt(pd->page_table[pde], vm->dev); + unmap_and_free_pt(pd->page_table[pde], dev); return -ENOMEM; } @@ -721,6 +741,7 @@ static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, uint64_t start, uint64_t length) { + struct drm_device *dev = ppgtt->base.dev; struct i915_page_directory *unused; uint64_t temp; uint32_t pdpe; @@ -730,40 +751,29 @@ static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, gen8_for_each_pdpe(unused, pdp, start, length, temp, pdpe) { WARN_ON(unused); - pdp->page_directory[pdpe] = alloc_pd_single(); - if (IS_ERR(pdp->page_directory[pdpe])) - goto unwind_out; - - gen8_initialize_pd(&ppgtt->base, - ppgtt->pdp.page_directory[pdpe]); - } - - /* XXX: Still alloc all page directories in systems with less than - * 4GB of memory. This won't be needed after a subsequent patch. - */ - while (pdpe < GEN8_LEGACY_PDPES) { - pdp->page_directory[pdpe] = alloc_pd_single(); + pdp->page_directory[pdpe] = alloc_pd_single(dev); if (IS_ERR(pdp->page_directory[pdpe])) goto unwind_out; gen8_initialize_pd(&ppgtt->base, ppgtt->pdp.page_directory[pdpe]); - pdpe++; } return 0; unwind_out: while (pdpe--) - unmap_and_free_pd(pdp->page_directory[pdpe]); + unmap_and_free_pd(pdp->page_directory[pdpe], dev); return -ENOMEM; } -static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, - uint64_t start, - uint64_t length) +static int gen8_alloc_va_range(struct i915_address_space *vm, + uint64_t start, + uint64_t length) { + struct i915_hw_ppgtt *ppgtt = + container_of(vm, struct i915_hw_ppgtt, base); struct i915_page_directory *pd; uint64_t temp; uint32_t pdpe; @@ -774,23 +784,9 @@ static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, return ret; gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { - ret = gen8_ppgtt_alloc_pagetabs(pd, start, length, - &ppgtt->base); - if (ret) - goto err_out; - } - - /* XXX: We allocated all page directories in systems with less than - * 4GB of memory. So initalize page tables of all PDPs. - * This won't be needed after the next patch. - */ - while (pdpe < GEN8_LEGACY_PDPES) { - ret = gen8_ppgtt_alloc_pagetabs(ppgtt->pdp.page_directory[pdpe], start, length, - &ppgtt->base); + ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length); if (ret) goto err_out; - - pdpe++; } return 0; @@ -800,136 +796,54 @@ err_out: return ret; } -static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, - const int pd) -{ - dma_addr_t pd_addr; - int ret; - - pd_addr = pci_map_page(ppgtt->base.dev->pdev, - ppgtt->pdp.page_directory[pd]->page, 0, - PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); - - ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); - if (ret) - return ret; - - ppgtt->pdp.page_directory[pd]->daddr = pd_addr; - - return 0; -} - -static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, - const int pd, - const int pt) -{ - dma_addr_t pt_addr; - struct i915_page_directory *pdir = ppgtt->pdp.page_directory[pd]; - struct i915_page_table *ptab = pdir->page_table[pt]; - struct page *p = ptab->page; - int ret; - - gen8_initialize_pt(&ppgtt->base, ptab); - - pt_addr = pci_map_page(ppgtt->base.dev->pdev, - p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); - ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); - if (ret) - return ret; - - ptab->daddr = pt_addr; - - return 0; -} - /* * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers * with a net effect resembling a 2-level page table in normal x86 terms. Each * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address * space. * - * FIXME: split allocation into smaller pieces. For now we only ever do this - * once, but with full PPGTT, the multiple contiguous allocations will be bad. - * TODO: Do something with the size parameter */ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) { - int i, j, ret; - - if (size % (1<<30)) - DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); + struct i915_page_directory *pd; + uint64_t temp, start = 0; + const uint64_t orig_length = size; + uint32_t pdpe; + int ret; ppgtt->base.start = 0; ppgtt->base.total = size; + ppgtt->base.clear_range = gen8_ppgtt_clear_range; + ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; + ppgtt->base.cleanup = gen8_ppgtt_cleanup; + ppgtt->switch_mm = gen8_mm_switch; ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); if (IS_ERR(ppgtt->scratch_pt)) return PTR_ERR(ppgtt->scratch_pt); - ppgtt->scratch_pd = alloc_pd_single(); + ppgtt->scratch_pd = alloc_pd_single(ppgtt->base.dev); if (IS_ERR(ppgtt->scratch_pd)) return PTR_ERR(ppgtt->scratch_pd); gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd); - /* 1. Do all our allocations for page directories and page tables. */ - ret = gen8_ppgtt_alloc(ppgtt, ppgtt->base.start, ppgtt->base.total); + ret = gen8_alloc_va_range(&ppgtt->base, start, size); if (ret) { - unmap_and_free_pd(ppgtt->scratch_pd); + unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev); unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); return ret; } - /* - * 2. Create DMA mappings for the page directories and page tables. - */ - for (i = 0; i < GEN8_LEGACY_PDPES; i++) { - ret = gen8_ppgtt_setup_page_directories(ppgtt, i); - if (ret) - goto bail; - - for (j = 0; j < I915_PDES; j++) { - ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); - if (ret) - goto bail; - } - } - - /* - * 3. Map all the page directory entries to point to the page tables - * we've allocated. - * - * For now, the PPGTT helper functions all require that the PDEs are - * plugged in correctly. So we do that now/here. For aliasing PPGTT, we - * will never need to touch the PDEs again. - */ - for (i = 0; i < GEN8_LEGACY_PDPES; i++) { - struct i915_page_directory *pd = ppgtt->pdp.page_directory[i]; - gen8_pde_t *pd_vaddr; - pd_vaddr = kmap_atomic(ppgtt->pdp.page_directory[i]->page); - for (j = 0; j < I915_PDES; j++) { - struct i915_page_table *pt = pd->page_table[j]; - dma_addr_t addr = pt->daddr; - pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, - I915_CACHE_LLC); - } - if (!HAS_LLC(ppgtt->base.dev)) - drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); - kunmap_atomic(pd_vaddr); - } + start = 0; + size = orig_length; - ppgtt->switch_mm = gen8_mm_switch; - ppgtt->base.clear_range = gen8_ppgtt_clear_range; - ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; - ppgtt->base.cleanup = gen8_ppgtt_cleanup; + gen8_for_each_pdpe(pd, &ppgtt->pdp, start, size, temp, pdpe) + gen8_map_pagetable_range(pd, start, size, ppgtt->base.dev); ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); return 0; - -bail: - gen8_ppgtt_free(ppgtt); - return ret; } static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) @@ -1354,7 +1268,7 @@ static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) } unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); - unmap_and_free_pd(&ppgtt->pd); + unmap_and_free_pd(&ppgtt->pd, ppgtt->base.dev); } static void gen6_ppgtt_cleanup(struct i915_address_space *vm) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 580248d92710..c8edccb0d782 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -188,6 +188,15 @@ #define GEN8_CTX_FORCE_RESTORE (1<<2) #define GEN8_CTX_L3LLC_COHERENT (1<<5) #define GEN8_CTX_PRIVILEGE (1<<8) + +#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \ + const u64 _addr = ppgtt->pdp.page_directory[n] ? \ + ppgtt->pdp.page_directory[n]->daddr : \ + ppgtt->scratch_pd->daddr; \ + reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ + reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ +} + enum { ADVANCED_CONTEXT = 0, LEGACY_CONTEXT, @@ -1755,14 +1764,14 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); - reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[3]->daddr); - reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[3]->daddr); - reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[2]->daddr); - reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[2]->daddr); - reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[1]->daddr); - reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[1]->daddr); - reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[0]->daddr); - reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[0]->daddr); + /* XXX: Systems with less than 4GB of memory do not have + * all PDPs. Proper PDP tracking will be added in a + * subsequent patch. + */ + ASSIGN_CTX_PDP(ppgtt, reg_state, 3); + ASSIGN_CTX_PDP(ppgtt, reg_state, 2); + ASSIGN_CTX_PDP(ppgtt, reg_state, 1); + ASSIGN_CTX_PDP(ppgtt, reg_state, 0); if (ring->id == RCS) { reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE; -- cgit v1.2.3 From 33c8819f1b057b555c73886f69f9baabe72527e0 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:33 +0100 Subject: drm/i915/gen8: begin bitmap tracking Like with gen6/7, we can enable bitmap tracking with all the preallocations to make sure things actually don't blow up. v2: Rebased to match changes from previous patches. v3: Without teardown logic, rely on used_pdpes and used_pdes when freeing page tables. v4: Rebased after s/page_tables/page_table/. v5: Rebased after page table generalizations. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 59 +++++++++++++++++++++++++++++-------- drivers/gpu/drm/i915/i915_gem_gtt.h | 7 +++++ 2 files changed, 54 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 1e1b42f8da42..1be0a8ee8dd7 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -437,6 +437,7 @@ static void unmap_and_free_pd(struct i915_page_directory *pd, if (pd->page) { i915_dma_unmap_single(pd, dev); __free_page(pd->page); + kfree(pd->used_pdes); kfree(pd); } } @@ -444,26 +445,35 @@ static void unmap_and_free_pd(struct i915_page_directory *pd, static struct i915_page_directory *alloc_pd_single(struct drm_device *dev) { struct i915_page_directory *pd; - int ret; + int ret = -ENOMEM; pd = kzalloc(sizeof(*pd), GFP_KERNEL); if (!pd) return ERR_PTR(-ENOMEM); + pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), + sizeof(*pd->used_pdes), GFP_KERNEL); + if (!pd->used_pdes) + goto free_pd; + pd->page = alloc_page(GFP_KERNEL); - if (!pd->page) { - kfree(pd); - return ERR_PTR(-ENOMEM); - } + if (!pd->page) + goto free_bitmap; ret = i915_dma_map_single(pd, dev); - if (ret) { - __free_page(pd->page); - kfree(pd); - return ERR_PTR(ret); - } + if (ret) + goto free_page; return pd; + +free_page: + __free_page(pd->page); +free_bitmap: + kfree(pd->used_pdes); +free_pd: + kfree(pd); + + return ERR_PTR(ret); } /* Broadwell Page Directory Pointer Descriptors */ @@ -675,7 +685,7 @@ static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_dev if (!pd->page) return; - for (i = 0; i < I915_PDES; i++) { + for_each_set_bit(i, pd->used_pdes, I915_PDES) { if (WARN_ON(!pd->page_table[i])) continue; @@ -688,7 +698,7 @@ static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) { int i; - for (i = 0; i < GEN8_LEGACY_PDPES; i++) { + for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) { if (WARN_ON(!ppgtt->pdp.page_directory[i])) continue; @@ -752,6 +762,7 @@ static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, gen8_for_each_pdpe(unused, pdp, start, length, temp, pdpe) { WARN_ON(unused); pdp->page_directory[pdpe] = alloc_pd_single(dev); + if (IS_ERR(pdp->page_directory[pdpe])) goto unwind_out; @@ -775,10 +786,13 @@ static int gen8_alloc_va_range(struct i915_address_space *vm, struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt, base); struct i915_page_directory *pd; + const uint64_t orig_start = start; + const uint64_t orig_length = length; uint64_t temp; uint32_t pdpe; int ret; + /* Do the allocations first so we can easily bail out */ ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length); if (ret) return ret; @@ -789,6 +803,27 @@ static int gen8_alloc_va_range(struct i915_address_space *vm, goto err_out; } + /* Now mark everything we've touched as used. This doesn't allow for + * robust error checking, but it makes the code a hell of a lot simpler. + */ + start = orig_start; + length = orig_length; + + gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { + struct i915_page_table *pt; + uint64_t pd_len = gen8_clamp_pd(start, length); + uint64_t pd_start = start; + uint32_t pde; + + gen8_for_each_pde(pt, &ppgtt->pd, pd_start, pd_len, temp, pde) { + bitmap_set(pd->page_table[pde]->used_ptes, + gen8_pte_index(start), + gen8_pte_count(start, length)); + set_bit(pde, pd->used_pdes); + } + set_bit(pdpe, ppgtt->pdp.used_pdpes); + } + return 0; err_out: diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index c3d5d40b78b2..29de64d1164e 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -220,11 +220,13 @@ struct i915_page_directory { dma_addr_t daddr; }; + unsigned long *used_pdes; struct i915_page_table *page_table[I915_PDES]; /* PDEs */ }; struct i915_page_directory_pointer { /* struct page *page; */ + DECLARE_BITMAP(used_pdpes, GEN8_LEGACY_PDPES); struct i915_page_directory *page_directory[GEN8_LEGACY_PDPES]; }; @@ -453,6 +455,11 @@ static inline uint32_t gen8_pml4e_index(uint64_t address) return 0; } +static inline size_t gen8_pte_count(uint64_t address, uint64_t length) +{ + return i915_pte_count(address, length, GEN8_PDE_SHIFT); +} + int i915_gem_gtt_init(struct drm_device *dev); void i915_gem_init_global_gtt(struct drm_device *dev); void i915_global_gtt_cleanup(struct drm_device *dev); -- cgit v1.2.3 From d7b2633dba04ef0fd7385f02a7b552abc5f1062f Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:34 +0100 Subject: drm/i915/gen8: Dynamic page table allocations This finishes off the dynamic page tables allocations, in the legacy 3 level style that already exists. Most everything has already been setup to this point, the patch finishes off the enabling by setting the appropriate function pointers. In LRC mode, contexts need to know the PDPs when they are populated. With dynamic page table allocations, these PDPs may not exist yet. Check if PDPs have been allocated and use the scratch page if they do not exist yet. Before submission, update the PDPs in the logic ring context as PDPs have been allocated. v2: Update aliasing/true ppgtt allocate/teardown/clear functions for gen 6 & 7. v3: Rebase. v4: Remove BUG() from ppgtt_unbind_vma, but keep checking that either teardown_va_range or clear_range functions exist (Daniel). v5: Similar to gen6, in init, gen8_ppgtt_clear_range call is only needed for aliasing ppgtt. Zombie tracking was originally added for teardown function and is no longer required. v6: Update err_out case in gen8_alloc_va_range (missed from lastest rebase). v7: Rebase after s/page_tables/page_table/. v8: Updated scratch_pt check after scratch flag was removed in previous patch. v9: Note that lrc mode needs to be updated to support init state without any PDP. v10: Unmap correct page_table in gen8_alloc_va_range's error case, clean-up gen8_aliasing_ppgtt_init (remove duplicated map), and initialize PTs during page table allocation. v11: Squashed LRC enabling commit, otherwise LRC mode would be left broken until it was updated to handle the init case without any PDP. v12: Do not overallocate new_pts bitmap, make alloc_gen8_temp_bitmaps static and don't abuse of inline functions. (Mika) Cc: Mika Kuoppala Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 307 +++++++++++++++++++++++++++--------- drivers/gpu/drm/i915/intel_lrc.c | 23 ++- 2 files changed, 253 insertions(+), 77 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 1be0a8ee8dd7..f6b0ddc7a5fa 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -653,28 +653,6 @@ static void gen8_initialize_pd(struct i915_address_space *vm, if (!HAS_LLC(vm->dev)) drm_clflush_virt_range(page_directory, PAGE_SIZE); - - kunmap_atomic(page_directory); -} - -/* It's likely we'll map more than one pagetable at a time. This function will - * save us unnecessary kmap calls, but do no more functionally than multiple - * calls to map_pt. */ -static void gen8_map_pagetable_range(struct i915_page_directory *pd, - uint64_t start, - uint64_t length, - struct drm_device *dev) -{ - gen8_pde_t *page_directory = kmap_atomic(pd->page); - struct i915_page_table *pt; - uint64_t temp, pde; - - gen8_for_each_pde(pt, pd, start, length, temp, pde) - __gen8_do_map_pt(page_directory + pde, pt, dev); - - if (!HAS_LLC(dev)) - drm_clflush_virt_range(page_directory, PAGE_SIZE); - kunmap_atomic(page_directory); } @@ -718,73 +696,178 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm) gen8_ppgtt_free(ppgtt); } +/** + * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. + * @ppgtt: Master ppgtt structure. + * @pd: Page directory for this address range. + * @start: Starting virtual address to begin allocations. + * @length Size of the allocations. + * @new_pts: Bitmap set by function with new allocations. Likely used by the + * caller to free on error. + * + * Allocate the required number of page tables. Extremely similar to + * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by + * the page directory boundary (instead of the page directory pointer). That + * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is + * possible, and likely that the caller will need to use multiple calls of this + * function to achieve the appropriate allocation. + * + * Return: 0 if success; negative error code otherwise. + */ static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt, struct i915_page_directory *pd, uint64_t start, - uint64_t length) + uint64_t length, + unsigned long *new_pts) { struct drm_device *dev = ppgtt->base.dev; - struct i915_page_table *unused; + struct i915_page_table *pt; uint64_t temp; uint32_t pde; - gen8_for_each_pde(unused, pd, start, length, temp, pde) { - WARN_ON(unused); - pd->page_table[pde] = alloc_pt_single(dev); - if (IS_ERR(pd->page_table[pde])) + gen8_for_each_pde(pt, pd, start, length, temp, pde) { + /* Don't reallocate page tables */ + if (pt) { + /* Scratch is never allocated this way */ + WARN_ON(pt == ppgtt->scratch_pt); + continue; + } + + pt = alloc_pt_single(dev); + if (IS_ERR(pt)) goto unwind_out; - gen8_initialize_pt(&ppgtt->base, pd->page_table[pde]); + gen8_initialize_pt(&ppgtt->base, pt); + pd->page_table[pde] = pt; + set_bit(pde, new_pts); } return 0; unwind_out: - while (pde--) + for_each_set_bit(pde, new_pts, I915_PDES) unmap_and_free_pt(pd->page_table[pde], dev); return -ENOMEM; } +/** + * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. + * @ppgtt: Master ppgtt structure. + * @pdp: Page directory pointer for this address range. + * @start: Starting virtual address to begin allocations. + * @length Size of the allocations. + * @new_pds Bitmap set by function with new allocations. Likely used by the + * caller to free on error. + * + * Allocate the required number of page directories starting at the pde index of + * @start, and ending at the pde index @start + @length. This function will skip + * over already allocated page directories within the range, and only allocate + * new ones, setting the appropriate pointer within the pdp as well as the + * correct position in the bitmap @new_pds. + * + * The function will only allocate the pages within the range for a give page + * directory pointer. In other words, if @start + @length straddles a virtually + * addressed PDP boundary (512GB for 4k pages), there will be more allocations + * required by the caller, This is not currently possible, and the BUG in the + * code will prevent it. + * + * Return: 0 if success; negative error code otherwise. + */ static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, struct i915_page_directory_pointer *pdp, uint64_t start, - uint64_t length) + uint64_t length, + unsigned long *new_pds) { struct drm_device *dev = ppgtt->base.dev; - struct i915_page_directory *unused; + struct i915_page_directory *pd; uint64_t temp; uint32_t pdpe; + WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES)); + /* FIXME: PPGTT container_of won't work for 64b */ WARN_ON((start + length) > 0x800000000ULL); - gen8_for_each_pdpe(unused, pdp, start, length, temp, pdpe) { - WARN_ON(unused); - pdp->page_directory[pdpe] = alloc_pd_single(dev); + gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { + if (pd) + continue; - if (IS_ERR(pdp->page_directory[pdpe])) + pd = alloc_pd_single(dev); + if (IS_ERR(pd)) goto unwind_out; - gen8_initialize_pd(&ppgtt->base, - ppgtt->pdp.page_directory[pdpe]); + gen8_initialize_pd(&ppgtt->base, pd); + pdp->page_directory[pdpe] = pd; + set_bit(pdpe, new_pds); } return 0; unwind_out: - while (pdpe--) + for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES) unmap_and_free_pd(pdp->page_directory[pdpe], dev); return -ENOMEM; } +static void +free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts) +{ + int i; + + for (i = 0; i < GEN8_LEGACY_PDPES; i++) + kfree(new_pts[i]); + kfree(new_pts); + kfree(new_pds); +} + +/* Fills in the page directory bitmap, and the array of page tables bitmap. Both + * of these are based on the number of PDPEs in the system. + */ +static +int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, + unsigned long ***new_pts) +{ + int i; + unsigned long *pds; + unsigned long **pts; + + pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL); + if (!pds) + return -ENOMEM; + + pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL); + if (!pts) { + kfree(pds); + return -ENOMEM; + } + + for (i = 0; i < GEN8_LEGACY_PDPES; i++) { + pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES), + sizeof(unsigned long), GFP_KERNEL); + if (!pts[i]) + goto err_out; + } + + *new_pds = pds; + *new_pts = pts; + + return 0; + +err_out: + free_gen8_temp_bitmaps(pds, pts); + return -ENOMEM; +} + static int gen8_alloc_va_range(struct i915_address_space *vm, uint64_t start, uint64_t length) { struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt, base); + unsigned long *new_page_dirs, **new_page_tables; struct i915_page_directory *pd; const uint64_t orig_start = start; const uint64_t orig_length = length; @@ -792,42 +875,98 @@ static int gen8_alloc_va_range(struct i915_address_space *vm, uint32_t pdpe; int ret; - /* Do the allocations first so we can easily bail out */ - ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length); +#ifndef CONFIG_64BIT + /* Disallow 64b address on 32b platforms. Nothing is wrong with doing + * this in hardware, but a lot of the drm code is not prepared to handle + * 64b offset on 32b platforms. + * This will be addressed when 48b PPGTT is added */ + if (start + length > 0x100000000ULL) + return -E2BIG; +#endif + + /* Wrap is never okay since we can only represent 48b, and we don't + * actually use the other side of the canonical address space. + */ + if (WARN_ON(start + length < start)) + return -ERANGE; + + ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables); if (ret) return ret; + /* Do the allocations first so we can easily bail out */ + ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length, + new_page_dirs); + if (ret) { + free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); + return ret; + } + + /* For every page directory referenced, allocate page tables */ gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { - ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length); + ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length, + new_page_tables[pdpe]); if (ret) goto err_out; } - /* Now mark everything we've touched as used. This doesn't allow for - * robust error checking, but it makes the code a hell of a lot simpler. - */ start = orig_start; length = orig_length; + /* Allocations have completed successfully, so set the bitmaps, and do + * the mappings. */ gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { + gen8_pde_t *const page_directory = kmap_atomic(pd->page); struct i915_page_table *pt; uint64_t pd_len = gen8_clamp_pd(start, length); uint64_t pd_start = start; uint32_t pde; - gen8_for_each_pde(pt, &ppgtt->pd, pd_start, pd_len, temp, pde) { - bitmap_set(pd->page_table[pde]->used_ptes, - gen8_pte_index(start), - gen8_pte_count(start, length)); + /* Every pd should be allocated, we just did that above. */ + WARN_ON(!pd); + + gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { + /* Same reasoning as pd */ + WARN_ON(!pt); + WARN_ON(!pd_len); + WARN_ON(!gen8_pte_count(pd_start, pd_len)); + + /* Set our used ptes within the page table */ + bitmap_set(pt->used_ptes, + gen8_pte_index(pd_start), + gen8_pte_count(pd_start, pd_len)); + + /* Our pde is now pointing to the pagetable, pt */ set_bit(pde, pd->used_pdes); + + /* Map the PDE to the page table */ + __gen8_do_map_pt(page_directory + pde, pt, vm->dev); + + /* NB: We haven't yet mapped ptes to pages. At this + * point we're still relying on insert_entries() */ } + + if (!HAS_LLC(vm->dev)) + drm_clflush_virt_range(page_directory, PAGE_SIZE); + + kunmap_atomic(page_directory); + set_bit(pdpe, ppgtt->pdp.used_pdpes); } + free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); return 0; err_out: - gen8_ppgtt_free(ppgtt); + while (pdpe--) { + for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES) + unmap_and_free_pt(ppgtt->pdp.page_directory[pdpe]->page_table[temp], vm->dev); + } + + for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES) + unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe], vm->dev); + + free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); return ret; } @@ -838,21 +977,8 @@ err_out: * space. * */ -static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) +static int gen8_ppgtt_init_common(struct i915_hw_ppgtt *ppgtt, uint64_t size) { - struct i915_page_directory *pd; - uint64_t temp, start = 0; - const uint64_t orig_length = size; - uint32_t pdpe; - int ret; - - ppgtt->base.start = 0; - ppgtt->base.total = size; - ppgtt->base.clear_range = gen8_ppgtt_clear_range; - ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; - ppgtt->base.cleanup = gen8_ppgtt_cleanup; - ppgtt->switch_mm = gen8_mm_switch; - ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); if (IS_ERR(ppgtt->scratch_pt)) return PTR_ERR(ppgtt->scratch_pt); @@ -864,6 +990,30 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd); + ppgtt->base.start = 0; + ppgtt->base.total = size; + ppgtt->base.cleanup = gen8_ppgtt_cleanup; + ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; + + ppgtt->switch_mm = gen8_mm_switch; + + return 0; +} + +static int gen8_aliasing_ppgtt_init(struct i915_hw_ppgtt *ppgtt) +{ + struct drm_device *dev = ppgtt->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + uint64_t start = 0, size = dev_priv->gtt.base.total; + int ret; + + ret = gen8_ppgtt_init_common(ppgtt, dev_priv->gtt.base.total); + if (ret) + return ret; + + /* Aliasing PPGTT has to always work and be mapped because of the way we + * use RESTORE_INHIBIT in the context switch. This will be fixed + * eventually. */ ret = gen8_alloc_va_range(&ppgtt->base, start, size); if (ret) { unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev); @@ -871,13 +1021,26 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) return ret; } - start = 0; - size = orig_length; + ppgtt->base.allocate_va_range = NULL; + ppgtt->base.clear_range = gen8_ppgtt_clear_range; + ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); - gen8_for_each_pdpe(pd, &ppgtt->pdp, start, size, temp, pdpe) - gen8_map_pagetable_range(pd, start, size, ppgtt->base.dev); + return 0; +} + +static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) +{ + struct drm_device *dev = ppgtt->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + int ret; + + ret = gen8_ppgtt_init_common(ppgtt, dev_priv->gtt.base.total); + if (ret) + return ret; + + ppgtt->base.allocate_va_range = gen8_alloc_va_range; + ppgtt->base.clear_range = gen8_ppgtt_clear_range; - ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); return 0; } @@ -1416,7 +1579,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing) } } - ppgtt->base.allocate_va_range = gen6_alloc_va_range; + ppgtt->base.allocate_va_range = aliasing ? NULL : gen6_alloc_va_range; ppgtt->base.clear_range = gen6_ppgtt_clear_range; ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; ppgtt->base.cleanup = gen6_ppgtt_cleanup; @@ -1457,8 +1620,10 @@ static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt, if (INTEL_INFO(dev)->gen < 8) return gen6_ppgtt_init(ppgtt, aliasing); + else if (aliasing) + return gen8_aliasing_ppgtt_init(ppgtt); else - return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); + return gen8_ppgtt_init(ppgtt); } int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) { diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index c8edccb0d782..58ac414cf603 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -190,7 +190,7 @@ #define GEN8_CTX_PRIVILEGE (1<<8) #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \ - const u64 _addr = ppgtt->pdp.page_directory[n] ? \ + const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \ ppgtt->pdp.page_directory[n]->daddr : \ ppgtt->scratch_pd->daddr; \ reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ @@ -330,6 +330,7 @@ static void execlists_elsp_write(struct intel_engine_cs *ring, static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, struct drm_i915_gem_object *ring_obj, + struct i915_hw_ppgtt *ppgtt, u32 tail) { struct page *page; @@ -341,6 +342,16 @@ static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, reg_state[CTX_RING_TAIL+1] = tail; reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); + /* True PPGTT with dynamic page allocation: update PDP registers and + * point the unallocated PDPs to the scratch page + */ + if (ppgtt) { + ASSIGN_CTX_PDP(ppgtt, reg_state, 3); + ASSIGN_CTX_PDP(ppgtt, reg_state, 2); + ASSIGN_CTX_PDP(ppgtt, reg_state, 1); + ASSIGN_CTX_PDP(ppgtt, reg_state, 0); + } + kunmap_atomic(reg_state); return 0; @@ -359,7 +370,7 @@ static void execlists_submit_contexts(struct intel_engine_cs *ring, WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj)); - execlists_update_context(ctx_obj0, ringbuf0->obj, tail0); + execlists_update_context(ctx_obj0, ringbuf0->obj, to0->ppgtt, tail0); if (to1) { ringbuf1 = to1->engine[ring->id].ringbuf; @@ -368,7 +379,7 @@ static void execlists_submit_contexts(struct intel_engine_cs *ring, WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj)); - execlists_update_context(ctx_obj1, ringbuf1->obj, tail1); + execlists_update_context(ctx_obj1, ringbuf1->obj, to1->ppgtt, tail1); } execlists_elsp_write(ring, ctx_obj0, ctx_obj1); @@ -1764,9 +1775,9 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); - /* XXX: Systems with less than 4GB of memory do not have - * all PDPs. Proper PDP tracking will be added in a - * subsequent patch. + + /* With dynamic page allocation, PDPs may not be allocated at this point, + * Point the unallocated PDPs to the scratch page */ ASSIGN_CTX_PDP(ppgtt, reg_state, 3); ASSIGN_CTX_PDP(ppgtt, reg_state, 2); -- cgit v1.2.3 From a4e0bedca678c81eea4cd79a4bd502335639f73a Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 8 Apr 2015 12:13:35 +0100 Subject: drm/i915: Use complete address space in true PPGTT True PPGTT is capable of having a full address space, even if the system has less allocated memory. Note that aliasing PPGTT always aliases the GGTT and thus should remain of the same size. Signed-off-by: Michel Thierry Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index f6b0ddc7a5fa..2a01d5620a19 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1030,11 +1030,9 @@ static int gen8_aliasing_ppgtt_init(struct i915_hw_ppgtt *ppgtt) static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) { - struct drm_device *dev = ppgtt->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; int ret; - ret = gen8_ppgtt_init_common(ppgtt, dev_priv->gtt.base.total); + ret = gen8_ppgtt_init_common(ppgtt, (1ULL << 32)); if (ret) return ret; -- cgit v1.2.3 From 90e4f1592bb6e82f6690f0e05a8aadcf04d7bce7 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 25 Mar 2015 18:45:58 +0200 Subject: drm/i915: Fix the VBT child device parsing for BSW MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Recent BSW VBT has a VBT child device size 37 bytes instead of the 33 bytes our code assumes. This means we fail to parse the VBT and thus fail to detect eDP ports properly and just register them as DP ports instead. Fix it up by using the reported child device size from the VBT instead of assuming it matches out struct defintions. The latest spec I have shows that the child device size should be 36 bytes for rev >= 195, however on my BSW the size is actually 37 bytes. And our current struct definition is 33 bytes. Feels like the entire VBT parses would need to be rewritten to handle changes in the layout better, but for now I've decided to do just the bare minimum to get my eDP port back. Cc: Vijay Purushothaman Signed-off-by: Ville Syrjälä Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_bios.c | 26 +++++++++++++------------- drivers/gpu/drm/i915/intel_bios.h | 4 ++-- 2 files changed, 15 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index ad2f3b0d922f..c08368c03dad 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -447,6 +447,12 @@ parse_general_definitions(struct drm_i915_private *dev_priv, } } +static union child_device_config * +child_device_ptr(struct bdb_general_definitions *p_defs, int i) +{ + return (void *) &p_defs->devices[i * p_defs->child_dev_size]; +} + static void parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, struct bdb_header *bdb) @@ -476,10 +482,10 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, block_size = get_blocksize(p_defs); /* get the number of child device */ child_device_num = (block_size - sizeof(*p_defs)) / - sizeof(*p_child); + p_defs->child_dev_size; count = 0; for (i = 0; i < child_device_num; i++) { - p_child = &(p_defs->devices[i]); + p_child = child_device_ptr(p_defs, i); if (!p_child->old.device_type) { /* skip the device block if device type is invalid */ continue; @@ -1067,25 +1073,19 @@ parse_device_mapping(struct drm_i915_private *dev_priv, DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n"); return; } - /* judge whether the size of child device meets the requirements. - * If the child device size obtained from general definition block - * is different with sizeof(struct child_device_config), skip the - * parsing of sdvo device info - */ - if (p_defs->child_dev_size != sizeof(*p_child)) { - /* different child dev size . Ignore it */ - DRM_DEBUG_KMS("different child size is found. Invalid.\n"); + if (p_defs->child_dev_size < sizeof(*p_child)) { + DRM_ERROR("General definiton block child device size is too small.\n"); return; } /* get the block size of general definitions */ block_size = get_blocksize(p_defs); /* get the number of child device */ child_device_num = (block_size - sizeof(*p_defs)) / - sizeof(*p_child); + p_defs->child_dev_size; count = 0; /* get the number of child device that is present */ for (i = 0; i < child_device_num; i++) { - p_child = &(p_defs->devices[i]); + p_child = child_device_ptr(p_defs, i); if (!p_child->common.device_type) { /* skip the device block if device type is invalid */ continue; @@ -1105,7 +1105,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv, dev_priv->vbt.child_dev_num = count; count = 0; for (i = 0; i < child_device_num; i++) { - p_child = &(p_defs->devices[i]); + p_child = child_device_ptr(p_defs, i); if (!p_child->common.device_type) { /* skip the device block if device type is invalid */ continue; diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h index 6afd5be33367..af0b47652752 100644 --- a/drivers/gpu/drm/i915/intel_bios.h +++ b/drivers/gpu/drm/i915/intel_bios.h @@ -277,9 +277,9 @@ struct bdb_general_definitions { * And the device num is related with the size of general definition * block. It is obtained by using the following formula: * number = (block_size - sizeof(bdb_general_definitions))/ - * sizeof(child_device_config); + * defs->child_dev_size; */ - union child_device_config devices[0]; + uint8_t devices[0]; } __packed; /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ -- cgit v1.2.3 From b5eba37283181fefe2a4c3b81f1c8f29d9d96904 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:48 +0100 Subject: drm/i915: Use simpler form of spin_lock_irq(execlist_lock) We can use the simpler spinlock form to disable interrupts as we are always outside of an irq/softirq handler. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_lrc.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 58ac414cf603..2779070f59d2 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -522,7 +522,6 @@ static int execlists_context_queue(struct intel_engine_cs *ring, { struct drm_i915_gem_request *cursor; struct drm_i915_private *dev_priv = ring->dev->dev_private; - unsigned long flags; int num_elements = 0; if (to != ring->default_context) @@ -549,7 +548,7 @@ static int execlists_context_queue(struct intel_engine_cs *ring, intel_runtime_pm_get(dev_priv); - spin_lock_irqsave(&ring->execlist_lock, flags); + spin_lock_irq(&ring->execlist_lock); list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) if (++num_elements > 2) @@ -575,7 +574,7 @@ static int execlists_context_queue(struct intel_engine_cs *ring, if (num_elements == 0) execlists_context_unqueue(ring); - spin_unlock_irqrestore(&ring->execlist_lock, flags); + spin_unlock_irq(&ring->execlist_lock); return 0; } @@ -960,7 +959,6 @@ void intel_execlists_retire_requests(struct intel_engine_cs *ring) { struct drm_i915_gem_request *req, *tmp; struct drm_i915_private *dev_priv = ring->dev->dev_private; - unsigned long flags; struct list_head retired_list; WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); @@ -968,9 +966,9 @@ void intel_execlists_retire_requests(struct intel_engine_cs *ring) return; INIT_LIST_HEAD(&retired_list); - spin_lock_irqsave(&ring->execlist_lock, flags); + spin_lock_irq(&ring->execlist_lock); list_replace_init(&ring->execlist_retired_req_list, &retired_list); - spin_unlock_irqrestore(&ring->execlist_lock, flags); + spin_unlock_irq(&ring->execlist_lock); list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { struct intel_context *ctx = req->ctx; -- cgit v1.2.3 From 4bb1bedb28e0f1d04fa6bf5bdcdaecabd904b21c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:49 +0100 Subject: drm/i915: Use the global runtime-pm wakelock for a busy GPU for execlists When we submit a request to the GPU, we first take the rpm wakelock, and only release it once the GPU has been idle for a small period of time after all requests have been complete. This means that we are sure no new interrupt can arrive whilst we do not hold the rpm wakelock and so can drop the individual get/put around every single request inside execlists. Note: to close one potential issue we should mark the GPU as busy earlier in __i915_add_request. To elaborate: The issue is that we emit the irq signalling sequence before we grab the rpm reference, which means we could miss the resulting interrupt (since that's not set up when suspended). The only bad side effect is a missed interrupt, gt mmio writes automatically wake up the hw itself. But otoh we have an umbrella rpm reference for the entirety of execbuf, as long as that's there we're covered. Signed-off-by: Chris Wilson [danvet: Explain a bit more about the add_request issue, which after some irc chatting with Chris turns out to not be an issue really.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 1 - drivers/gpu/drm/i915/intel_lrc.c | 3 --- 2 files changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 8feafe9be1f0..9fbc3558de67 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2605,7 +2605,6 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, struct drm_i915_gem_request, execlist_link); list_del(&submit_req->execlist_link); - intel_runtime_pm_put(dev_priv); if (submit_req->ctx != ring->default_context) intel_lr_context_unpin(ring, submit_req->ctx); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 2779070f59d2..3758298a3531 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -546,8 +546,6 @@ static int execlists_context_queue(struct intel_engine_cs *ring, } request->tail = tail; - intel_runtime_pm_get(dev_priv); - spin_lock_irq(&ring->execlist_lock); list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) @@ -977,7 +975,6 @@ void intel_execlists_retire_requests(struct intel_engine_cs *ring) if (ctx_obj && (ctx != ring->default_context)) intel_lr_context_unpin(ring, ctx); - intel_runtime_pm_put(dev_priv); list_del(&req->execlist_link); i915_gem_request_unreference(req); } -- cgit v1.2.3 From 595e1eeb26d3fcf2e39b494f067ebb5eb3c77e08 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:51 +0100 Subject: drm/i915: Remove vestigal DRI1 ring quiescing code After the removal of DRI1, all access to the rings are through requests and so we can always be sure that there is a request to wait upon to free up available space. The fallback code only existed so that we could quiesce the GPU following unmediated access by DRI1. v2: Rebase Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_trace.h | 27 ---------------- drivers/gpu/drm/i915/intel_lrc.c | 57 +++------------------------------ drivers/gpu/drm/i915/intel_ringbuffer.c | 56 ++------------------------------ 3 files changed, 6 insertions(+), 134 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index 4574f0cc9b1c..7bd48cd2c210 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -597,33 +597,6 @@ DEFINE_EVENT(i915_gem_request, i915_gem_request_wait_end, TP_ARGS(req) ); -DECLARE_EVENT_CLASS(i915_ring, - TP_PROTO(struct intel_engine_cs *ring), - TP_ARGS(ring), - - TP_STRUCT__entry( - __field(u32, dev) - __field(u32, ring) - ), - - TP_fast_assign( - __entry->dev = ring->dev->primary->index; - __entry->ring = ring->id; - ), - - TP_printk("dev=%u, ring=%u", __entry->dev, __entry->ring) -); - -DEFINE_EVENT(i915_ring, i915_ring_wait_begin, - TP_PROTO(struct intel_engine_cs *ring), - TP_ARGS(ring) -); - -DEFINE_EVENT(i915_ring, i915_ring_wait_end, - TP_PROTO(struct intel_engine_cs *ring), - TP_ARGS(ring) -); - TRACE_EVENT(i915_flip_request, TP_PROTO(int plane, struct drm_i915_gem_object *obj), diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3758298a3531..43737541556b 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -647,8 +647,9 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request return 0; } -static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, - int bytes) +static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, + struct intel_context *ctx, + int bytes) { struct intel_engine_cs *ring = ringbuf->ring; struct drm_i915_gem_request *request; @@ -674,7 +675,7 @@ static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, break; } - if (&request->list == &ring->request_list) + if (WARN_ON(&request->list == &ring->request_list)) return -ENOSPC; ret = i915_wait_request(request); @@ -712,56 +713,6 @@ intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf, execlists_context_queue(ring, ctx, ringbuf->tail, request); } -static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, - struct intel_context *ctx, - int bytes) -{ - struct intel_engine_cs *ring = ringbuf->ring; - struct drm_device *dev = ring->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - unsigned long end; - int ret; - - ret = logical_ring_wait_request(ringbuf, bytes); - if (ret != -ENOSPC) - return ret; - - /* Force the context submission in case we have been skipping it */ - intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL); - - /* With GEM the hangcheck timer should kick us out of the loop, - * leaving it early runs the risk of corrupting GEM state (due - * to running on almost untested codepaths). But on resume - * timers don't work yet, so prevent a complete hang in that - * case by choosing an insanely large timeout. */ - end = jiffies + 60 * HZ; - - ret = 0; - do { - if (intel_ring_space(ringbuf) >= bytes) - break; - - msleep(1); - - if (dev_priv->mm.interruptible && signal_pending(current)) { - ret = -ERESTARTSYS; - break; - } - - ret = i915_gem_check_wedge(&dev_priv->gpu_error, - dev_priv->mm.interruptible); - if (ret) - break; - - if (time_after(jiffies, end)) { - ret = -EBUSY; - break; - } - } while (1); - - return ret; -} - static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf, struct intel_context *ctx) { diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 1f9463a295a5..720d29a602a7 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2060,7 +2060,7 @@ void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) ring->buffer = NULL; } -static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) +static int ring_wait_for_space(struct intel_engine_cs *ring, int n) { struct intel_ringbuffer *ringbuf = ring->buffer; struct drm_i915_gem_request *request; @@ -2076,7 +2076,7 @@ static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) break; } - if (&request->list == &ring->request_list) + if (WARN_ON(&request->list == &ring->request_list)) return -ENOSPC; ret = i915_wait_request(request); @@ -2090,58 +2090,6 @@ static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) return 0; } -static int ring_wait_for_space(struct intel_engine_cs *ring, int n) -{ - struct drm_device *dev = ring->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_ringbuffer *ringbuf = ring->buffer; - unsigned long end; - int ret; - - ret = intel_ring_wait_request(ring, n); - if (ret != -ENOSPC) - return ret; - - /* force the tail write in case we have been skipping them */ - __intel_ring_advance(ring); - - /* With GEM the hangcheck timer should kick us out of the loop, - * leaving it early runs the risk of corrupting GEM state (due - * to running on almost untested codepaths). But on resume - * timers don't work yet, so prevent a complete hang in that - * case by choosing an insanely large timeout. */ - end = jiffies + 60 * HZ; - - ret = 0; - trace_i915_ring_wait_begin(ring); - do { - if (intel_ring_space(ringbuf) >= n) - break; - ringbuf->head = I915_READ_HEAD(ring); - if (intel_ring_space(ringbuf) >= n) - break; - - msleep(1); - - if (dev_priv->mm.interruptible && signal_pending(current)) { - ret = -ERESTARTSYS; - break; - } - - ret = i915_gem_check_wedge(&dev_priv->gpu_error, - dev_priv->mm.interruptible); - if (ret) - break; - - if (time_after(jiffies, end)) { - ret = -EBUSY; - break; - } - } while (1); - trace_i915_ring_wait_end(ring); - return ret; -} - static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) { uint32_t __iomem *virt; -- cgit v1.2.3 From f81338a52a82009863b0dc9d597fe1000d1caff6 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Thu, 9 Apr 2015 17:36:21 -0700 Subject: drm: Adding drm helper function drm_plane_from_index(). Adding drm helper function to return plane pointer from index where index is a returned by drm_plane_index. v2: -avoided nested loop by adding loop count (Daniel) v3: -updated patch header prefix to 'drm' (Matt) v4: -fixed a kerneldoc issue (kbuild-internal) Cc: dri-devel@lists.freedesktop.org Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Acked-by: Dave Airlie Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 23 +++++++++++++++++++++++ include/drm/drm_crtc.h | 1 + 2 files changed, 24 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 9f970c2d4819..6254942141d3 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -1285,6 +1285,29 @@ unsigned int drm_plane_index(struct drm_plane *plane) } EXPORT_SYMBOL(drm_plane_index); +/** + * drm_plane_from_index - find the registered plane at an index + * @dev: DRM device + * @idx: index of registered plane to find for + * + * Given a plane index, return the registered plane from DRM device's + * list of planes with matching index. + */ +struct drm_plane * +drm_plane_from_index(struct drm_device *dev, int idx) +{ + struct drm_plane *plane; + unsigned int i = 0; + + list_for_each_entry(plane, &dev->mode_config.plane_list, head) { + if (i == idx) + return plane; + i++; + } + return NULL; +} +EXPORT_SYMBOL(drm_plane_from_index); + /** * drm_plane_force_disable - Forcibly disable a plane * @plane: plane to disable diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index adc9ea5acf02..ed769e79c675 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1264,6 +1264,7 @@ extern int drm_plane_init(struct drm_device *dev, bool is_primary); extern void drm_plane_cleanup(struct drm_plane *plane); extern unsigned int drm_plane_index(struct drm_plane *plane); +extern struct drm_plane * drm_plane_from_index(struct drm_device *dev, int idx); extern void drm_plane_force_disable(struct drm_plane *plane); extern int drm_plane_check_pixel_format(const struct drm_plane *plane, u32 format); -- cgit v1.2.3 From 3e1ab4b70571ea801de6f426f9973c80e1bddfb3 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 10 Apr 2015 09:31:40 +0200 Subject: drm/i915: Update DRIVER_DATE to 20150410 Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f4daa3d3c126..ec6cf1bd7c29 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -56,7 +56,7 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20150327" +#define DRIVER_DATE "20150410" #undef WARN_ON /* Many gcc seem to no see through this and fall over :( */ -- cgit v1.2.3 From 70a101f8639a712576c3ca1d910564c7e2ec91d8 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Wed, 8 Apr 2015 18:56:53 -0700 Subject: drm/i915: Switch to full atomic helpers for plane updates/disable, take two Switch from our plane update/disable entrypoints to use the full atomic helpers (which generate a top-level atomic transaction) rather than the transitional helpers (which only create/manipulate orphaned plane states independent of a top-level transaction). Various upcoming work (SKL scalers, atomic watermarks, etc.) requires a full atomic transaction to behave properly/cleanly. Last time we tried this, we had to back out the change because we still call the drm_plane vfuncs directly from within our legacy modesetting code. This potentially results in nested atomic transactions, locking collisions, and other failures. To avoid that problem again, we sidestep the issue by calling the transitional helpers directly (rather than through a vfunc) when we're nested inside of other legacy modesetting code. However this does allow legacy SetPlane() ioctl's to process an entire drm_atomic_state transaction, which is important for upcoming patches. Cc: Chandra Konduru Signed-off-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++++------------ drivers/gpu/drm/i915/intel_sprite.c | 10 +++++----- 2 files changed, 17 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7bfe2af42030..11b958a56515 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5576,7 +5576,7 @@ static void intel_crtc_disable(struct drm_crtc *crtc) dev_priv->display.crtc_disable(crtc); dev_priv->display.off(crtc); - crtc->primary->funcs->disable_plane(crtc->primary); + drm_plane_helper_disable(crtc->primary); /* Update computed state. */ list_for_each_entry(connector, &dev->mode_config.connector_list, head) { @@ -11731,11 +11731,11 @@ static int __intel_set_mode(struct drm_crtc *crtc, int vdisplay, hdisplay; drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); - ret = primary->funcs->update_plane(primary, &intel_crtc->base, - fb, 0, 0, - hdisplay, vdisplay, - x << 16, y << 16, - hdisplay << 16, vdisplay << 16); + ret = drm_plane_helper_update(primary, &intel_crtc->base, + fb, 0, 0, + hdisplay, vdisplay, + x << 16, y << 16, + hdisplay << 16, vdisplay << 16); } /* Now enable the clocks, plane, pipe, and connectors that we set up. */ @@ -12286,10 +12286,10 @@ static int intel_crtc_set_config(struct drm_mode_set *set) int vdisplay, hdisplay; drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); - ret = primary->funcs->update_plane(primary, set->crtc, set->fb, - 0, 0, hdisplay, vdisplay, - set->x << 16, set->y << 16, - hdisplay << 16, vdisplay << 16); + ret = drm_plane_helper_update(primary, set->crtc, set->fb, + 0, 0, hdisplay, vdisplay, + set->x << 16, set->y << 16, + hdisplay << 16, vdisplay << 16); /* * We need to make sure the primary plane is re-enabled if it @@ -12773,8 +12773,8 @@ void intel_plane_destroy(struct drm_plane *plane) } const struct drm_plane_funcs intel_plane_funcs = { - .update_plane = drm_plane_helper_update, - .disable_plane = drm_plane_helper_disable, + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, .destroy = intel_plane_destroy, .set_property = drm_atomic_helper_plane_set_property, .atomic_get_property = intel_plane_atomic_get_property, diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index e9ff6fc61267..f009c8f970ea 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1139,11 +1139,11 @@ int intel_plane_restore(struct drm_plane *plane) if (!plane->crtc || !plane->state->fb) return 0; - return plane->funcs->update_plane(plane, plane->crtc, plane->state->fb, - plane->state->crtc_x, plane->state->crtc_y, - plane->state->crtc_w, plane->state->crtc_h, - plane->state->src_x, plane->state->src_y, - plane->state->src_w, plane->state->src_h); + return drm_plane_helper_update(plane, plane->crtc, plane->state->fb, + plane->state->crtc_x, plane->state->crtc_y, + plane->state->crtc_w, plane->state->crtc_h, + plane->state->src_x, plane->state->src_y, + plane->state->src_w, plane->state->src_h); } static uint32_t ilk_plane_formats[] = { -- cgit v1.2.3 From f1e2daea79e96a50cdbca1bdd1a70900e1af5da1 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Thu, 9 Apr 2015 10:48:38 -0700 Subject: drm/i915: Clear crtc atomic flags at beginning of transaction Once we have full atomic modeset, these kind of flags should be in a real intel_crtc_state that's tracked properly. In the meantime, make sure we clear out any old flags at the beginning of a transaction so that we don't wind up seeing leftover flags from old transactions that were checked, but never went to the commit step. At the moment, a failed check or prepare could leave stale flags behind that interfere with the next atomic transaction. v2: Just do a memset; the series this patch was originally part of placed additional fields into the structure that shouldn't be cleared, but that's no longer the case. Signed-off-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_atomic.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index 3903b90fb64e..b4ea6762e4ef 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -76,6 +76,8 @@ int intel_atomic_check(struct drm_device *dev, state->allow_modeset = false; for (i = 0; i < ncrtcs; i++) { struct intel_crtc *crtc = to_intel_crtc(state->crtcs[i]); + if (crtc) + memset(&crtc->atomic, 0, sizeof(crtc->atomic)); if (crtc && crtc->pipe != nuclear_pipe) not_nuclear = true; } -- cgit v1.2.3 From efab6d8dd158fdccbe6a030f89fbf9ca0a9564e4 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:57 +0100 Subject: drm/i915: Use a separate slab for requests requests are even more frequently allocated than objects and equally benefit from having a dedicated slab. v2: Rebase Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_dma.c | 12 ++++++---- drivers/gpu/drm/i915/i915_drv.h | 4 +++- drivers/gpu/drm/i915/i915_gem.c | 41 +++++++++++++++++++-------------- drivers/gpu/drm/i915/intel_ringbuffer.c | 1 - 4 files changed, 35 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 8f5428b46a27..180b5d92b279 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1006,8 +1006,10 @@ out_regs: put_bridge: pci_dev_put(dev_priv->bridge_dev); free_priv: - if (dev_priv->slab) - kmem_cache_destroy(dev_priv->slab); + if (dev_priv->requests) + kmem_cache_destroy(dev_priv->requests); + if (dev_priv->objects) + kmem_cache_destroy(dev_priv->objects); kfree(dev_priv); return ret; } @@ -1090,8 +1092,10 @@ int i915_driver_unload(struct drm_device *dev) if (dev_priv->regs != NULL) pci_iounmap(dev->pdev, dev_priv->regs); - if (dev_priv->slab) - kmem_cache_destroy(dev_priv->slab); + if (dev_priv->requests) + kmem_cache_destroy(dev_priv->requests); + if (dev_priv->objects) + kmem_cache_destroy(dev_priv->objects); pci_dev_put(dev_priv->bridge_dev); kfree(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ec6cf1bd7c29..855eaac9ddd1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1558,7 +1558,8 @@ struct i915_virtual_gpu { struct drm_i915_private { struct drm_device *dev; - struct kmem_cache *slab; + struct kmem_cache *objects; + struct kmem_cache *requests; const struct intel_device_info info; @@ -2044,6 +2045,7 @@ struct drm_i915_gem_request { struct kref ref; /** On Which ring this request was generated */ + struct drm_i915_private *i915; struct intel_engine_cs *ring; /** GEM sequence number associated with this request. */ diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 9fbc3558de67..20a61764a4a3 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -378,13 +378,13 @@ out: void *i915_gem_object_alloc(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); + return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); } void i915_gem_object_free(struct drm_i915_gem_object *obj) { struct drm_i915_private *dev_priv = obj->base.dev->dev_private; - kmem_cache_free(dev_priv->slab, obj); + kmem_cache_free(dev_priv->objects, obj); } static int @@ -2506,43 +2506,45 @@ void i915_gem_request_free(struct kref *req_ref) i915_gem_context_unreference(ctx); } - kfree(req); + kmem_cache_free(req->i915->requests, req); } int i915_gem_request_alloc(struct intel_engine_cs *ring, struct intel_context *ctx) { + struct drm_i915_private *dev_priv = to_i915(ring->dev); + struct drm_i915_gem_request *rq; int ret; - struct drm_i915_gem_request *request; - struct drm_i915_private *dev_private = ring->dev->dev_private; if (ring->outstanding_lazy_request) return 0; - request = kzalloc(sizeof(*request), GFP_KERNEL); - if (request == NULL) + rq = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); + if (rq == NULL) return -ENOMEM; - ret = i915_gem_get_seqno(ring->dev, &request->seqno); + kref_init(&rq->ref); + rq->i915 = dev_priv; + + ret = i915_gem_get_seqno(ring->dev, &rq->seqno); if (ret) { - kfree(request); + kfree(rq); return ret; } - kref_init(&request->ref); - request->ring = ring; - request->uniq = dev_private->request_uniq++; + rq->ring = ring; + rq->uniq = dev_priv->request_uniq++; if (i915.enable_execlists) - ret = intel_logical_ring_alloc_request_extras(request, ctx); + ret = intel_logical_ring_alloc_request_extras(rq, ctx); else - ret = intel_ring_alloc_request_extras(request); + ret = intel_ring_alloc_request_extras(rq); if (ret) { - kfree(request); + kfree(rq); return ret; } - ring->outstanding_lazy_request = request; + ring->outstanding_lazy_request = rq; return 0; } @@ -4984,11 +4986,16 @@ i915_gem_load(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; int i; - dev_priv->slab = + dev_priv->objects = kmem_cache_create("i915_gem_object", sizeof(struct drm_i915_gem_object), 0, SLAB_HWCACHE_ALIGN, NULL); + dev_priv->requests = + kmem_cache_create("i915_gem_request", + sizeof(struct drm_i915_gem_request), 0, + SLAB_HWCACHE_ALIGN, + NULL); INIT_LIST_HEAD(&dev_priv->vm_list); i915_init_vm(dev_priv, &dev_priv->gtt.base); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 720d29a602a7..9f3fc81149a4 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2139,7 +2139,6 @@ int intel_ring_idle(struct intel_engine_cs *ring) int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) { request->ringbuf = request->ring->buffer; - return 0; } -- cgit v1.2.3 From e20d2ab741b58ad1ac0209f7a4ee930ebb7a43f3 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:58 +0100 Subject: drm/i915: Use a separate slab for vmas vma are more frequently allocated than objects and so should equally benefit from having a dedicated slab. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_dma.c | 4 ++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 7 ++++++- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++- 4 files changed, 13 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 180b5d92b279..d67cd9e0ef14 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1008,6 +1008,8 @@ put_bridge: free_priv: if (dev_priv->requests) kmem_cache_destroy(dev_priv->requests); + if (dev_priv->vmas) + kmem_cache_destroy(dev_priv->vmas); if (dev_priv->objects) kmem_cache_destroy(dev_priv->objects); kfree(dev_priv); @@ -1094,6 +1096,8 @@ int i915_driver_unload(struct drm_device *dev) if (dev_priv->requests) kmem_cache_destroy(dev_priv->requests); + if (dev_priv->vmas) + kmem_cache_destroy(dev_priv->vmas); if (dev_priv->objects) kmem_cache_destroy(dev_priv->objects); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 855eaac9ddd1..b6750751bb93 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1559,6 +1559,7 @@ struct i915_virtual_gpu { struct drm_i915_private { struct drm_device *dev; struct kmem_cache *objects; + struct kmem_cache *vmas; struct kmem_cache *requests; const struct intel_device_info info; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 20a61764a4a3..a57fdd98b4fe 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4612,7 +4612,7 @@ void i915_gem_vma_destroy(struct i915_vma *vma) list_del(&vma->vma_link); - kfree(vma); + kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); } static void @@ -4991,6 +4991,11 @@ i915_gem_load(struct drm_device *dev) sizeof(struct drm_i915_gem_object), 0, SLAB_HWCACHE_ALIGN, NULL); + dev_priv->vmas = + kmem_cache_create("i915_gem_vma", + sizeof(struct i915_vma), 0, + SLAB_HWCACHE_ALIGN, + NULL); dev_priv->requests = kmem_cache_create("i915_gem_request", sizeof(struct drm_i915_gem_request), 0, diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 2a01d5620a19..559cecaccf7f 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2712,7 +2712,8 @@ __i915_gem_vma_create(struct drm_i915_gem_object *obj, if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) return ERR_PTR(-EINVAL); - vma = kzalloc(sizeof(*vma), GFP_KERNEL); + + vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); if (vma == NULL) return ERR_PTR(-ENOMEM); -- cgit v1.2.3 From 19ee66af15a59f405bfca9949af552d9ec0b03f4 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 10 Apr 2015 10:18:47 +0200 Subject: drm/i915: Remove unused variable in intel_lrc.c Already tagged this one and 0-day builder is failing me. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_lrc.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 43737541556b..037e94c5ab42 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -907,7 +907,6 @@ int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, void intel_execlists_retire_requests(struct intel_engine_cs *ring) { struct drm_i915_gem_request *req, *tmp; - struct drm_i915_private *dev_priv = ring->dev->dev_private; struct list_head retired_list; WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); -- cgit v1.2.3 From a6111f7b6604e6cf98856839b56a2ae436fc0bab Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:21:02 +0100 Subject: drm/i915: Reduce locking in execlist command submission This eliminates six needless spin lock/unlock pairs when writing out ELSP. v2: Respin with my preferred colour. v3: Mostly back to the original colour Signed-off-by: Tvrtko Ursulin [v1] Signed-off-by: Chris Wilson Cc: Daniel Vetter Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 18 +++++++ drivers/gpu/drm/i915/intel_lrc.c | 16 +++--- drivers/gpu/drm/i915/intel_uncore.c | 98 ++++++++++++++++++++++++++++--------- 3 files changed, 103 insertions(+), 29 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b6750751bb93..0ddf6831a321 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2537,6 +2537,13 @@ void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, enum forcewake_domains domains); void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, enum forcewake_domains domains); +/* Like above but the caller must manage the uncore.lock itself. + * Must be used with I915_READ_FW and friends. + */ +void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, + enum forcewake_domains domains); +void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, + enum forcewake_domains domains); void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); static inline bool intel_vgpu_active(struct drm_device *dev) { @@ -3229,6 +3236,17 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) +/* These are untraced mmio-accessors that are only valid to be used inside + * criticial sections inside IRQ handlers where forcewake is explicitly + * controlled. + * Think twice, and think again, before using these. + * Note: Should only be used between intel_uncore_forcewake_irqlock() and + * intel_uncore_forcewake_irqunlock(). + */ +#define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__)) +#define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__)) +#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) + /* "Broadcast RGB" property */ #define INTEL_BROADCAST_RGB_AUTO 0 #define INTEL_BROADCAST_RGB_FULL 1 diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 037e94c5ab42..ed28e7d8adea 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -315,17 +315,19 @@ static void execlists_elsp_write(struct intel_engine_cs *ring, desc[3] = (u32)(temp >> 32); desc[2] = (u32)temp; - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); - I915_WRITE(RING_ELSP(ring), desc[1]); - I915_WRITE(RING_ELSP(ring), desc[0]); - I915_WRITE(RING_ELSP(ring), desc[3]); + spin_lock(&dev_priv->uncore.lock); + intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); + I915_WRITE_FW(RING_ELSP(ring), desc[1]); + I915_WRITE_FW(RING_ELSP(ring), desc[0]); + I915_WRITE_FW(RING_ELSP(ring), desc[3]); /* The context is automatically loaded after the following */ - I915_WRITE(RING_ELSP(ring), desc[2]); + I915_WRITE_FW(RING_ELSP(ring), desc[2]); /* ELSP is a wo register, so use another nearby reg for posting instead */ - POSTING_READ(RING_EXECLIST_STATUS(ring)); - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + POSTING_READ_FW(RING_EXECLIST_STATUS(ring)); + intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); + spin_unlock(&dev_priv->uncore.lock); } static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index ab5cc94588e1..d96d15faf268 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -375,6 +375,26 @@ void intel_uncore_sanitize(struct drm_device *dev) intel_disable_gt_powersave(dev); } +static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, + enum forcewake_domains fw_domains) +{ + struct intel_uncore_forcewake_domain *domain; + enum forcewake_domain_id id; + + if (!dev_priv->uncore.funcs.force_wake_get) + return; + + fw_domains &= dev_priv->uncore.fw_domains; + + for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { + if (domain->wake_count++) + fw_domains &= ~(1 << id); + } + + if (fw_domains) + dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); +} + /** * intel_uncore_forcewake_get - grab forcewake domain references * @dev_priv: i915 device instance @@ -392,41 +412,39 @@ void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) { unsigned long irqflags; - struct intel_uncore_forcewake_domain *domain; - enum forcewake_domain_id id; if (!dev_priv->uncore.funcs.force_wake_get) return; WARN_ON(dev_priv->pm.suspended); - fw_domains &= dev_priv->uncore.fw_domains; - spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - - for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { - if (domain->wake_count++) - fw_domains &= ~(1 << id); - } - - if (fw_domains) - dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); - + __intel_uncore_forcewake_get(dev_priv, fw_domains); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } /** - * intel_uncore_forcewake_put - release a forcewake domain reference + * intel_uncore_forcewake_get__locked - grab forcewake domain references * @dev_priv: i915 device instance - * @fw_domains: forcewake domains to put references + * @fw_domains: forcewake domains to get reference on * - * This function drops the device-level forcewakes for specified - * domains obtained by intel_uncore_forcewake_get(). + * See intel_uncore_forcewake_get(). This variant places the onus + * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. */ -void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, - enum forcewake_domains fw_domains) +void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, + enum forcewake_domains fw_domains) +{ + assert_spin_locked(&dev_priv->uncore.lock); + + if (!dev_priv->uncore.funcs.force_wake_get) + return; + + __intel_uncore_forcewake_get(dev_priv, fw_domains); +} + +static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, + enum forcewake_domains fw_domains) { - unsigned long irqflags; struct intel_uncore_forcewake_domain *domain; enum forcewake_domain_id id; @@ -435,8 +453,6 @@ void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, fw_domains &= dev_priv->uncore.fw_domains; - spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { if (WARN_ON(domain->wake_count == 0)) continue; @@ -447,10 +463,48 @@ void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, domain->wake_count++; fw_domain_arm_timer(domain); } +} +/** + * intel_uncore_forcewake_put - release a forcewake domain reference + * @dev_priv: i915 device instance + * @fw_domains: forcewake domains to put references + * + * This function drops the device-level forcewakes for specified + * domains obtained by intel_uncore_forcewake_get(). + */ +void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + + if (!dev_priv->uncore.funcs.force_wake_put) + return; + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + __intel_uncore_forcewake_put(dev_priv, fw_domains); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } +/** + * intel_uncore_forcewake_put__locked - grab forcewake domain references + * @dev_priv: i915 device instance + * @fw_domains: forcewake domains to get reference on + * + * See intel_uncore_forcewake_put(). This variant places the onus + * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. + */ +void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, + enum forcewake_domains fw_domains) +{ + assert_spin_locked(&dev_priv->uncore.lock); + + if (!dev_priv->uncore.funcs.force_wake_put) + return; + + __intel_uncore_forcewake_put(dev_priv, fw_domains); +} + void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) { struct intel_uncore_forcewake_domain *domain; -- cgit v1.2.3 From cb0d205e0ffc78eb51d5e62c8ee841f286f10303 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:21:04 +0100 Subject: drm/i915: Reduce locking in gen8 IRQ handler Similar in vain in reducing the number of unrequired spinlocks used for execlist command submission (where the forcewake is required but manually controlled), we know that the IRQ registers are outside of the powerwell and so we can access them directly. Since we now have direct access exported via I915_READ_FW/I915_WRITE_FW, lets put those to use in the irq handlers as well. In the process, reorder the execlist submission to happen as early as possible. v2: Restrict the untraced register mmio to just the GT path (i.e. the hotpath for execlists) Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 47 ++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8b5e0358c592..c2c80bf490c6 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1285,56 +1285,56 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, irqreturn_t ret = IRQ_NONE; if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { - tmp = I915_READ(GEN8_GT_IIR(0)); + tmp = I915_READ_FW(GEN8_GT_IIR(0)); if (tmp) { - I915_WRITE(GEN8_GT_IIR(0), tmp); + I915_WRITE_FW(GEN8_GT_IIR(0), tmp); ret = IRQ_HANDLED; rcs = tmp >> GEN8_RCS_IRQ_SHIFT; ring = &dev_priv->ring[RCS]; - if (rcs & GT_RENDER_USER_INTERRUPT) - notify_ring(dev, ring); if (rcs & GT_CONTEXT_SWITCH_INTERRUPT) intel_lrc_irq_handler(ring); + if (rcs & GT_RENDER_USER_INTERRUPT) + notify_ring(dev, ring); bcs = tmp >> GEN8_BCS_IRQ_SHIFT; ring = &dev_priv->ring[BCS]; - if (bcs & GT_RENDER_USER_INTERRUPT) - notify_ring(dev, ring); if (bcs & GT_CONTEXT_SWITCH_INTERRUPT) intel_lrc_irq_handler(ring); + if (bcs & GT_RENDER_USER_INTERRUPT) + notify_ring(dev, ring); } else DRM_ERROR("The master control interrupt lied (GT0)!\n"); } if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { - tmp = I915_READ(GEN8_GT_IIR(1)); + tmp = I915_READ_FW(GEN8_GT_IIR(1)); if (tmp) { - I915_WRITE(GEN8_GT_IIR(1), tmp); + I915_WRITE_FW(GEN8_GT_IIR(1), tmp); ret = IRQ_HANDLED; vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; ring = &dev_priv->ring[VCS]; - if (vcs & GT_RENDER_USER_INTERRUPT) - notify_ring(dev, ring); if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) intel_lrc_irq_handler(ring); + if (vcs & GT_RENDER_USER_INTERRUPT) + notify_ring(dev, ring); vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; ring = &dev_priv->ring[VCS2]; - if (vcs & GT_RENDER_USER_INTERRUPT) - notify_ring(dev, ring); if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) intel_lrc_irq_handler(ring); + if (vcs & GT_RENDER_USER_INTERRUPT) + notify_ring(dev, ring); } else DRM_ERROR("The master control interrupt lied (GT1)!\n"); } if (master_ctl & GEN8_GT_PM_IRQ) { - tmp = I915_READ(GEN8_GT_IIR(2)); + tmp = I915_READ_FW(GEN8_GT_IIR(2)); if (tmp & dev_priv->pm_rps_events) { - I915_WRITE(GEN8_GT_IIR(2), - tmp & dev_priv->pm_rps_events); + I915_WRITE_FW(GEN8_GT_IIR(2), + tmp & dev_priv->pm_rps_events); ret = IRQ_HANDLED; gen6_rps_irq_handler(dev_priv, tmp); } else @@ -1342,17 +1342,17 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, } if (master_ctl & GEN8_GT_VECS_IRQ) { - tmp = I915_READ(GEN8_GT_IIR(3)); + tmp = I915_READ_FW(GEN8_GT_IIR(3)); if (tmp) { - I915_WRITE(GEN8_GT_IIR(3), tmp); + I915_WRITE_FW(GEN8_GT_IIR(3), tmp); ret = IRQ_HANDLED; vcs = tmp >> GEN8_VECS_IRQ_SHIFT; ring = &dev_priv->ring[VECS]; - if (vcs & GT_RENDER_USER_INTERRUPT) - notify_ring(dev, ring); if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) intel_lrc_irq_handler(ring); + if (vcs & GT_RENDER_USER_INTERRUPT) + notify_ring(dev, ring); } else DRM_ERROR("The master control interrupt lied (GT3)!\n"); } @@ -2178,13 +2178,12 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg) aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D; - master_ctl = I915_READ(GEN8_MASTER_IRQ); + master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; if (!master_ctl) return IRQ_NONE; - I915_WRITE(GEN8_MASTER_IRQ, 0); - POSTING_READ(GEN8_MASTER_IRQ); + I915_WRITE_FW(GEN8_MASTER_IRQ, 0); /* Find, clear, then process each source of interrupt */ @@ -2281,8 +2280,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg) } - I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); - POSTING_READ(GEN8_MASTER_IRQ); + I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); + POSTING_READ_FW(GEN8_MASTER_IRQ); return ret; } -- cgit v1.2.3 From 74cdb337c0fc7d97e7db719051e51abcc7bd9579 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:21:05 +0100 Subject: drm/i915: Tidy gen8 IRQ handler Remove some needless variables and parameter passing. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 113 +++++++++++++++++----------------------- 1 file changed, 49 insertions(+), 64 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index c2c80bf490c6..46bcbff89760 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -985,8 +985,7 @@ static void ironlake_rps_change_irq_handler(struct drm_device *dev) return; } -static void notify_ring(struct drm_device *dev, - struct intel_engine_cs *ring) +static void notify_ring(struct intel_engine_cs *ring) { if (!intel_ring_initialized(ring)) return; @@ -1248,9 +1247,9 @@ static void ilk_gt_irq_handler(struct drm_device *dev, { if (gt_iir & (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) - notify_ring(dev, &dev_priv->ring[RCS]); + notify_ring(&dev_priv->ring[RCS]); if (gt_iir & ILK_BSD_USER_INTERRUPT) - notify_ring(dev, &dev_priv->ring[VCS]); + notify_ring(&dev_priv->ring[VCS]); } static void snb_gt_irq_handler(struct drm_device *dev, @@ -1260,11 +1259,11 @@ static void snb_gt_irq_handler(struct drm_device *dev, if (gt_iir & (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) - notify_ring(dev, &dev_priv->ring[RCS]); + notify_ring(&dev_priv->ring[RCS]); if (gt_iir & GT_BSD_USER_INTERRUPT) - notify_ring(dev, &dev_priv->ring[VCS]); + notify_ring(&dev_priv->ring[VCS]); if (gt_iir & GT_BLT_USER_INTERRUPT) - notify_ring(dev, &dev_priv->ring[BCS]); + notify_ring(&dev_priv->ring[BCS]); if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | GT_BSD_CS_ERROR_INTERRUPT | @@ -1275,63 +1274,65 @@ static void snb_gt_irq_handler(struct drm_device *dev, ivybridge_parity_error_irq_handler(dev, gt_iir); } -static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, - struct drm_i915_private *dev_priv, +static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) { - struct intel_engine_cs *ring; - u32 rcs, bcs, vcs; - uint32_t tmp = 0; irqreturn_t ret = IRQ_NONE; if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { - tmp = I915_READ_FW(GEN8_GT_IIR(0)); + u32 tmp = I915_READ_FW(GEN8_GT_IIR(0)); if (tmp) { I915_WRITE_FW(GEN8_GT_IIR(0), tmp); ret = IRQ_HANDLED; - rcs = tmp >> GEN8_RCS_IRQ_SHIFT; - ring = &dev_priv->ring[RCS]; - if (rcs & GT_CONTEXT_SWITCH_INTERRUPT) - intel_lrc_irq_handler(ring); - if (rcs & GT_RENDER_USER_INTERRUPT) - notify_ring(dev, ring); - - bcs = tmp >> GEN8_BCS_IRQ_SHIFT; - ring = &dev_priv->ring[BCS]; - if (bcs & GT_CONTEXT_SWITCH_INTERRUPT) - intel_lrc_irq_handler(ring); - if (bcs & GT_RENDER_USER_INTERRUPT) - notify_ring(dev, ring); + if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT)) + intel_lrc_irq_handler(&dev_priv->ring[RCS]); + if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT)) + notify_ring(&dev_priv->ring[RCS]); + + if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT)) + intel_lrc_irq_handler(&dev_priv->ring[BCS]); + if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT)) + notify_ring(&dev_priv->ring[BCS]); } else DRM_ERROR("The master control interrupt lied (GT0)!\n"); } if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { - tmp = I915_READ_FW(GEN8_GT_IIR(1)); + u32 tmp = I915_READ_FW(GEN8_GT_IIR(1)); if (tmp) { I915_WRITE_FW(GEN8_GT_IIR(1), tmp); ret = IRQ_HANDLED; - vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; - ring = &dev_priv->ring[VCS]; - if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) - intel_lrc_irq_handler(ring); - if (vcs & GT_RENDER_USER_INTERRUPT) - notify_ring(dev, ring); - - vcs = tmp >> GEN8_VCS2_IRQ_SHIFT; - ring = &dev_priv->ring[VCS2]; - if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) - intel_lrc_irq_handler(ring); - if (vcs & GT_RENDER_USER_INTERRUPT) - notify_ring(dev, ring); + if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT)) + intel_lrc_irq_handler(&dev_priv->ring[VCS]); + if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT)) + notify_ring(&dev_priv->ring[VCS]); + + if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT)) + intel_lrc_irq_handler(&dev_priv->ring[VCS2]); + if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT)) + notify_ring(&dev_priv->ring[VCS2]); } else DRM_ERROR("The master control interrupt lied (GT1)!\n"); } + if (master_ctl & GEN8_GT_VECS_IRQ) { + u32 tmp = I915_READ_FW(GEN8_GT_IIR(3)); + if (tmp) { + I915_WRITE_FW(GEN8_GT_IIR(3), tmp); + ret = IRQ_HANDLED; + + if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)) + intel_lrc_irq_handler(&dev_priv->ring[VECS]); + if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT)) + notify_ring(&dev_priv->ring[VECS]); + } else + DRM_ERROR("The master control interrupt lied (GT3)!\n"); + } + if (master_ctl & GEN8_GT_PM_IRQ) { - tmp = I915_READ_FW(GEN8_GT_IIR(2)); + u32 tmp = I915_READ_FW(GEN8_GT_IIR(2)); if (tmp & dev_priv->pm_rps_events) { I915_WRITE_FW(GEN8_GT_IIR(2), tmp & dev_priv->pm_rps_events); @@ -1341,22 +1342,6 @@ static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, DRM_ERROR("The master control interrupt lied (PM)!\n"); } - if (master_ctl & GEN8_GT_VECS_IRQ) { - tmp = I915_READ_FW(GEN8_GT_IIR(3)); - if (tmp) { - I915_WRITE_FW(GEN8_GT_IIR(3), tmp); - ret = IRQ_HANDLED; - - vcs = tmp >> GEN8_VECS_IRQ_SHIFT; - ring = &dev_priv->ring[VECS]; - if (vcs & GT_CONTEXT_SWITCH_INTERRUPT) - intel_lrc_irq_handler(ring); - if (vcs & GT_RENDER_USER_INTERRUPT) - notify_ring(dev, ring); - } else - DRM_ERROR("The master control interrupt lied (GT3)!\n"); - } - return ret; } @@ -1651,7 +1636,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) if (HAS_VEBOX(dev_priv->dev)) { if (pm_iir & PM_VEBOX_USER_INTERRUPT) - notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); + notify_ring(&dev_priv->ring[VECS]); if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); @@ -1845,7 +1830,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) I915_WRITE(VLV_IIR, iir); } - gen8_gt_irq_handler(dev, dev_priv, master_ctl); + gen8_gt_irq_handler(dev_priv, master_ctl); /* Call regardless, as some status bits might not be * signalled in iir */ @@ -2187,7 +2172,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg) /* Find, clear, then process each source of interrupt */ - ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); + ret = gen8_gt_irq_handler(dev_priv, master_ctl); if (master_ctl & GEN8_DE_MISC_IRQ) { tmp = I915_READ(GEN8_DE_MISC_IIR); @@ -3692,7 +3677,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) new_iir = I915_READ16(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) - notify_ring(dev, &dev_priv->ring[RCS]); + notify_ring(&dev_priv->ring[RCS]); for_each_pipe(dev_priv, pipe) { int plane = pipe; @@ -3883,7 +3868,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) new_iir = I915_READ(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) - notify_ring(dev, &dev_priv->ring[RCS]); + notify_ring(&dev_priv->ring[RCS]); for_each_pipe(dev_priv, pipe) { int plane = pipe; @@ -4110,9 +4095,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) new_iir = I915_READ(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) - notify_ring(dev, &dev_priv->ring[RCS]); + notify_ring(&dev_priv->ring[RCS]); if (iir & I915_BSD_USER_INTERRUPT) - notify_ring(dev, &dev_priv->ring[VCS]); + notify_ring(&dev_priv->ring[VCS]); for_each_pipe(dev_priv, pipe) { if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && -- cgit v1.2.3 From 423795cbac3b6b1b9fea6845a9233ba2dcc61142 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:21:08 +0100 Subject: drm/i915: Prefer to check for idleness in worker rather than sync-flush Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a57fdd98b4fe..95e46c7490ab 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2411,7 +2411,6 @@ int __i915_add_request(struct intel_engine_cs *ring, i915_queue_hangcheck(ring->dev); - cancel_delayed_work_sync(&dev_priv->mm.idle_work); queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, round_jiffies_up_relative(HZ)); @@ -2797,6 +2796,12 @@ i915_gem_idle_work_handler(struct work_struct *work) struct drm_i915_private *dev_priv = container_of(work, typeof(*dev_priv), mm.idle_work.work); struct drm_device *dev = dev_priv->dev; + struct intel_engine_cs *ring; + int i; + + for_each_ring(ring, dev_priv, i) + if (!list_empty(&ring->request_list)) + return; intel_mark_idle(dev); -- cgit v1.2.3 From d7b9ca2f7a41cd36f5ca6c220df48ca9294ed37a Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:21:09 +0100 Subject: drm/i915: Remove request->uniq We already assign a unique identifier to every request: seqno. That someone felt like adding a second one without even mentioning why and tweaking ABI smells very fishy. Fixes regression from commit b3a38998f042b862f5ba4d7f2268f3a8dfb4883a Author: Nick Hoath Date: Thu Feb 19 16:30:47 2015 +0000 drm/i915: Fix a use after free, and unbalanced refcounting v2: Rebase Signed-off-by: Chris Wilson Cc: Nick Hoath Cc: Thomas Daniel Cc: Daniel Vetter Cc: Jani Nikula [danvet: Fixup because different merge order.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 4 ---- drivers/gpu/drm/i915/i915_gem.c | 1 - drivers/gpu/drm/i915/i915_trace.h | 13 ++++--------- drivers/gpu/drm/i915/intel_lrc.c | 1 - 4 files changed, 4 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0ddf6831a321..3668d613aeb8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1823,8 +1823,6 @@ struct drm_i915_private { void (*stop_ring)(struct intel_engine_cs *ring); } gt; - uint32_t request_uniq; - /* * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch * will be rejected. Instead look for a better place. @@ -2094,8 +2092,6 @@ struct drm_i915_gem_request { /** process identifier submitting this request */ struct pid *pid; - uint32_t uniq; - /** * The ELSP only accepts two elements at a time, so we queue * context/tail pairs on a given queue (ring->execlist_queue) until the diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 95e46c7490ab..8d28a5d2437f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2532,7 +2532,6 @@ int i915_gem_request_alloc(struct intel_engine_cs *ring, } rq->ring = ring; - rq->uniq = dev_priv->request_uniq++; if (i915.enable_execlists) ret = intel_logical_ring_alloc_request_extras(rq, ctx); diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index 7bd48cd2c210..2aa140edbbd3 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -505,7 +505,6 @@ DECLARE_EVENT_CLASS(i915_gem_request, TP_STRUCT__entry( __field(u32, dev) __field(u32, ring) - __field(u32, uniq) __field(u32, seqno) ), @@ -514,13 +513,11 @@ DECLARE_EVENT_CLASS(i915_gem_request, i915_gem_request_get_ring(req); __entry->dev = ring->dev->primary->index; __entry->ring = ring->id; - __entry->uniq = req ? req->uniq : 0; __entry->seqno = i915_gem_request_get_seqno(req); ), - TP_printk("dev=%u, ring=%u, uniq=%u, seqno=%u", - __entry->dev, __entry->ring, __entry->uniq, - __entry->seqno) + TP_printk("dev=%u, ring=%u, seqno=%u", + __entry->dev, __entry->ring, __entry->seqno) ); DEFINE_EVENT(i915_gem_request, i915_gem_request_add, @@ -565,7 +562,6 @@ TRACE_EVENT(i915_gem_request_wait_begin, TP_STRUCT__entry( __field(u32, dev) __field(u32, ring) - __field(u32, uniq) __field(u32, seqno) __field(bool, blocking) ), @@ -581,14 +577,13 @@ TRACE_EVENT(i915_gem_request_wait_begin, i915_gem_request_get_ring(req); __entry->dev = ring->dev->primary->index; __entry->ring = ring->id; - __entry->uniq = req ? req->uniq : 0; __entry->seqno = i915_gem_request_get_seqno(req); __entry->blocking = mutex_is_locked(&ring->dev->struct_mutex); ), - TP_printk("dev=%u, ring=%u, uniq=%u, seqno=%u, blocking=%s", - __entry->dev, __entry->ring, __entry->uniq, + TP_printk("dev=%u, ring=%u, seqno=%u, blocking=%s", + __entry->dev, __entry->ring, __entry->seqno, __entry->blocking ? "yes (NB)" : "no") ); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index ed28e7d8adea..88c577cdd038 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -540,7 +540,6 @@ static int execlists_context_queue(struct intel_engine_cs *ring, request->ring = ring; request->ctx = to; kref_init(&request->ref); - request->uniq = dev_priv->request_uniq++; i915_gem_context_reference(request->ctx); } else { i915_gem_request_reference(request); -- cgit v1.2.3 From 149c86e74fe44dcbac5e9f8d145c5fbc5dc21261 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:21:11 +0100 Subject: drm/i915: Allocate context objects from stolen As we never expose context objects directly to userspace, we can forgo allocating a first-class GEM object for them and prefer to use the limited resource of reserved/stolen memory for them. Note this means that their initial contents are undefined. However, a downside of using stolen objects for execlists is that we cannot access the physical address directly (thanks MCH!) which prevents their use. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_context.c | 4 +++- drivers/gpu/drm/i915/intel_lrc.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index f3e84c44d009..e4c57a3981b3 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -157,7 +157,9 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) struct drm_i915_gem_object *obj; int ret; - obj = i915_gem_alloc_object(dev, size); + obj = i915_gem_object_create_stolen(dev, size); + if (obj == NULL) + obj = i915_gem_alloc_object(dev, size); if (obj == NULL) return ERR_PTR(-ENOMEM); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 88c577cdd038..aa3ea64e4815 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1845,7 +1845,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx, context_size = round_up(get_lr_context_size(ring), 4096); - ctx_obj = i915_gem_alloc_context_obj(dev, context_size); + ctx_obj = i915_gem_alloc_object(dev, context_size); if (IS_ERR(ctx_obj)) { ret = PTR_ERR(ctx_obj); DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); -- cgit v1.2.3 From f6234c1deedd7d35a09366dba8d92c523ff9cf09 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 17:28:17 +0100 Subject: drm/i915: Simplify object is-pinned checking for shrinker When looking for viable candidates to shrink, we only want objects that are not pinned. However to do so we performed a double iteration over the vma in the objects, first looking for the pin-count, then looking for allocations. We can do both at once and be slightly more explicit in our validity test. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_shrinker.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c index f7929e769250..f6ecbda2c604 100644 --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c @@ -184,9 +184,12 @@ static int num_vma_bound(struct drm_i915_gem_object *obj) struct i915_vma *vma; int count = 0; - list_for_each_entry(vma, &obj->vma_list, vma_link) + list_for_each_entry(vma, &obj->vma_list, vma_link) { if (drm_mm_node_allocated(&vma->node)) count++; + if (vma->pin_count) + count++; + } return count; } @@ -210,8 +213,7 @@ i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) count += obj->base.size >> PAGE_SHIFT; list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { - if (!i915_gem_obj_is_pinned(obj) && - obj->pages_pin_count == num_vma_bound(obj)) + if (obj->pages_pin_count == num_vma_bound(obj)) count += obj->base.size >> PAGE_SHIFT; } -- cgit v1.2.3 From 8d90926139fa69100134917e200aec73607c543f Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Fri, 10 Apr 2015 11:38:31 +0300 Subject: drm/i915: Remove stale comment from __intel_set_mode() Since the following commit, the PLL calculations are done earlier, so the code following the comment doesn't do anything PLL or encoder related. It only updates the primary plane now. commit f3019a4d92f08b2dd92443a4b567a066a51c6ec0 Author: Ander Conselvan de Oliveira Date: Wed Oct 29 11:32:37 2014 +0200 drm/i915: Remove crtc_mode_set() hook Signed-off-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 11b958a56515..d6698e58a278 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11723,9 +11723,6 @@ static int __intel_set_mode(struct drm_crtc *crtc, modeset_update_crtc_power_domains(state); - /* Set up the DPLL and any encoders state that needs to adjust or depend - * on the DPLL. - */ for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { struct drm_plane *primary = intel_crtc->base.primary; int vdisplay, hdisplay; -- cgit v1.2.3 From a4104c556ae3b6279a42b5d27901d255c452cab0 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Fri, 10 Apr 2015 14:11:29 +0530 Subject: drm/i915: Naming constants to be written to GEN9_PG_ENABLE Change-Id: I4253459c075c50d9b6f034b4ed4ad2f54cd7d1d7 Signed-off-by: Sagar Kamble Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 77d8874c2fc3..4b48b3f92507 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6198,6 +6198,8 @@ enum skl_disp_power_wells { #define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4 #define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8 #define GEN9_PG_ENABLE 0xA210 +#define GEN9_RENDER_PG_ENABLE (1<<0) +#define GEN9_MEDIA_PG_ENABLE (1<<1) #define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C) #define PIXEL_OVERLAP_CNT_MASK (3 << 30) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1ab9e897994a..e04ef19673a9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4347,7 +4347,9 @@ static void gen9_enable_rc6(struct drm_device *dev) rc6_mask); /* 3b: Enable Coarse Power Gating only when RC6 is enabled */ - I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0); + I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? + (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); -- cgit v1.2.3 From d81063669a99b216eb6b9dfb17add4f38a839674 Mon Sep 17 00:00:00 2001 From: Sonika Jindal Date: Fri, 10 Apr 2015 14:37:28 +0530 Subject: drm/i915/skl: Allow universal planes to position Signed-off-by: Sonika Jindal Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d6698e58a278..811101372069 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12571,16 +12571,21 @@ intel_check_primary_plane(struct drm_plane *plane, struct drm_rect *dest = &state->dst; struct drm_rect *src = &state->src; const struct drm_rect *clip = &state->clip; + bool can_position = false; int ret; crtc = crtc ? crtc : plane->crtc; intel_crtc = to_intel_crtc(crtc); + if (INTEL_INFO(dev)->gen >= 9) + can_position = true; + ret = drm_plane_helper_check_update(plane, crtc, fb, src, dest, clip, DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING, - false, true, &state->visible); + can_position, true, + &state->visible); if (ret) return ret; -- cgit v1.2.3 From 3b7a5119b5d2def1161226a4c6a643db537dff7e Mon Sep 17 00:00:00 2001 From: Sonika Jindal Date: Fri, 10 Apr 2015 14:37:29 +0530 Subject: drm/i915/skl: Support for 90/270 rotation v2: Moving creation of property in a function, checking for 90/270 rotation simultaneously (Chris) Letting primary plane to be positioned v3: Adding if/else for 90/270 and rest params programming, adding check for pixel_format, some cleanup (review comments) v4: Adding right pixel_formats, using src_* params instead of crtc_* for offset and size programming (Ville) v5: Rebased on -nightly and Tvrtko's series for gtt remapping. v6: Rebased on -nightly (Tvrtko's series merged) v7: Moving pixel_format check to intel_atomic_plane_check (Matt) Signed-off-by: Sonika Jindal Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_atomic_plane.c | 24 +++++++++ drivers/gpu/drm/i915/intel_display.c | 88 ++++++++++++++++++++++--------- drivers/gpu/drm/i915/intel_drv.h | 6 +++ drivers/gpu/drm/i915/intel_sprite.c | 52 ++++++++++++------ 5 files changed, 131 insertions(+), 41 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4b48b3f92507..1d58d9c587c0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4866,7 +4866,9 @@ enum skl_disp_power_wells { #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) #define PLANE_CTL_ROTATE_MASK 0x3 #define PLANE_CTL_ROTATE_0 0x0 +#define PLANE_CTL_ROTATE_90 0x1 #define PLANE_CTL_ROTATE_180 0x2 +#define PLANE_CTL_ROTATE_270 0x3 #define _PLANE_STRIDE_1_A 0x70188 #define _PLANE_STRIDE_2_A 0x70288 #define _PLANE_STRIDE_3_A 0x70388 diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index 976b89156570..a27ee8cbb627 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -162,6 +162,30 @@ static int intel_plane_atomic_check(struct drm_plane *plane, (1 << drm_plane_index(plane)); } + if (state->fb && intel_rotation_90_or_270(state->rotation)) { + if (!(state->fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || + state->fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)) { + DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n"); + return -EINVAL; + } + + /* + * 90/270 is not allowed with RGB64 16:16:16:16, + * RGB 16-bit 5:6:5, and Indexed 8-bit. + * TBD: Add RGB64 case once its added in supported format list. + */ + switch (state->fb->pixel_format) { + case DRM_FORMAT_C8: + case DRM_FORMAT_RGB565: + DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n", + drm_get_format_name(state->fb->pixel_format)); + return -EINVAL; + + default: + break; + } + } + return intel_plane->check_plane(plane, intel_state); } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 811101372069..a0be6ab7ba7b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2338,13 +2338,6 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, info->pitch = fb->pitches[0]; info->fb_modifier = fb->modifier[0]; - if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED || - info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) { - DRM_DEBUG_KMS( - "Y or Yf tiling is needed for 90/270 rotation!\n"); - return -EINVAL; - } - return 0; } @@ -2945,8 +2938,12 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct drm_i915_gem_object *obj; int pipe = intel_crtc->pipe; - u32 plane_ctl, stride_div; + u32 plane_ctl, stride_div, stride; + u32 tile_height, plane_offset, plane_size; + unsigned int rotation; + int x_offset, y_offset; unsigned long surf_addr; + struct drm_plane *plane; if (!intel_crtc->primary_enabled) { I915_WRITE(PLANE_CTL(pipe, 0), 0); @@ -3007,21 +3004,51 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, } plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; - if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) + + plane = crtc->primary; + rotation = plane->state->rotation; + switch (rotation) { + case BIT(DRM_ROTATE_90): + plane_ctl |= PLANE_CTL_ROTATE_90; + break; + + case BIT(DRM_ROTATE_180): plane_ctl |= PLANE_CTL_ROTATE_180; + break; + + case BIT(DRM_ROTATE_270): + plane_ctl |= PLANE_CTL_ROTATE_270; + break; + } obj = intel_fb_obj(fb); stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], fb->pixel_format); - surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj); + surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); + + if (intel_rotation_90_or_270(rotation)) { + /* stride = Surface height in tiles */ + tile_height = intel_tile_height(dev, fb->bits_per_pixel, + fb->modifier[0]); + stride = DIV_ROUND_UP(fb->height, tile_height); + x_offset = stride * tile_height - y - (plane->state->src_h >> 16); + y_offset = x; + plane_size = ((plane->state->src_w >> 16) - 1) << 16 | + ((plane->state->src_h >> 16) - 1); + } else { + stride = fb->pitches[0] / stride_div; + x_offset = x; + y_offset = y; + plane_size = ((plane->state->src_h >> 16) - 1) << 16 | + ((plane->state->src_w >> 16) - 1); + } + plane_offset = y_offset << 16 | x_offset; I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); I915_WRITE(PLANE_POS(pipe, 0), 0); - I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); - I915_WRITE(PLANE_SIZE(pipe, 0), - (intel_crtc->config->pipe_src_h - 1) << 16 | - (intel_crtc->config->pipe_src_w - 1)); - I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div); + I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); + I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); + I915_WRITE(PLANE_STRIDE(pipe, 0), stride); I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); POSTING_READ(PLANE_SURF(pipe, 0)); @@ -12827,23 +12854,32 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, intel_primary_formats, num_formats, DRM_PLANE_TYPE_PRIMARY); - if (INTEL_INFO(dev)->gen >= 4) { - if (!dev->mode_config.rotation_property) - dev->mode_config.rotation_property = - drm_mode_create_rotation_property(dev, - BIT(DRM_ROTATE_0) | - BIT(DRM_ROTATE_180)); - if (dev->mode_config.rotation_property) - drm_object_attach_property(&primary->base.base, - dev->mode_config.rotation_property, - state->base.rotation); - } + if (INTEL_INFO(dev)->gen >= 4) + intel_create_rotation_property(dev, primary); drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); return &primary->base; } +void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) +{ + if (!dev->mode_config.rotation_property) { + unsigned long flags = BIT(DRM_ROTATE_0) | + BIT(DRM_ROTATE_180); + + if (INTEL_INFO(dev)->gen >= 9) + flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); + + dev->mode_config.rotation_property = + drm_mode_create_rotation_property(dev, flags); + } + if (dev->mode_config.rotation_property) + drm_object_attach_property(&plane->base.base, + dev->mode_config.rotation_property, + plane->base.state->rotation); +} + static int intel_check_cursor_plane(struct drm_plane *plane, struct intel_plane_state *state) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index efa53d57dd37..7a0aa2431bc0 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -996,6 +996,12 @@ intel_rotation_90_or_270(unsigned int rotation) return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)); } +unsigned int +intel_tile_height(struct drm_device *dev, uint32_t bits_per_pixel, + uint64_t fb_modifier); +void intel_create_rotation_property(struct drm_device *dev, + struct intel_plane *plane); + bool intel_wm_need_update(struct drm_plane *plane, struct drm_plane_state *state); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index f009c8f970ea..21682a8b60a3 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -190,10 +190,13 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, struct drm_i915_gem_object *obj = intel_fb_obj(fb); const int pipe = intel_plane->pipe; const int plane = intel_plane->plane + 1; - u32 plane_ctl, stride_div; + u32 plane_ctl, stride_div, stride; int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey; unsigned long surf_addr; + u32 tile_height, plane_offset, plane_size; + unsigned int rotation; + int x_offset, y_offset; plane_ctl = PLANE_CTL_ENABLE | PLANE_CTL_PIPE_CSC_ENABLE; @@ -254,8 +257,20 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, MISSING_CASE(fb->modifier[0]); } - if (drm_plane->state->rotation == BIT(DRM_ROTATE_180)) + rotation = drm_plane->state->rotation; + switch (rotation) { + case BIT(DRM_ROTATE_90): + plane_ctl |= PLANE_CTL_ROTATE_90; + break; + + case BIT(DRM_ROTATE_180): plane_ctl |= PLANE_CTL_ROTATE_180; + break; + + case BIT(DRM_ROTATE_270): + plane_ctl |= PLANE_CTL_ROTATE_270; + break; + } intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h, pixel_size, true, @@ -283,10 +298,26 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, surf_addr = intel_plane_obj_offset(intel_plane, obj); - I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x); - I915_WRITE(PLANE_STRIDE(pipe, plane), fb->pitches[0] / stride_div); + if (intel_rotation_90_or_270(rotation)) { + /* stride: Surface height in tiles */ + tile_height = intel_tile_height(dev, fb->bits_per_pixel, + fb->modifier[0]); + stride = DIV_ROUND_UP(fb->height, tile_height); + plane_size = (src_w << 16) | src_h; + x_offset = stride * tile_height - y - (src_h + 1); + y_offset = x; + } else { + stride = fb->pitches[0] / stride_div; + plane_size = (src_h << 16) | src_w; + x_offset = x; + y_offset = y; + } + plane_offset = y_offset << 16 | x_offset; + + I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); + I915_WRITE(PLANE_STRIDE(pipe, plane), stride); I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); - I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w); + I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); POSTING_READ(PLANE_SURF(pipe, plane)); @@ -1286,16 +1317,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) goto out; } - if (!dev->mode_config.rotation_property) - dev->mode_config.rotation_property = - drm_mode_create_rotation_property(dev, - BIT(DRM_ROTATE_0) | - BIT(DRM_ROTATE_180)); - - if (dev->mode_config.rotation_property) - drm_object_attach_property(&intel_plane->base.base, - dev->mode_config.rotation_property, - state->base.rotation); + intel_create_rotation_property(dev, intel_plane); drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); -- cgit v1.2.3 From 1d335d1b62dd8475317d20e3f95072515243a810 Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Fri, 10 Apr 2015 15:54:58 +0300 Subject: drm/i915: Move vm page allocation in proper place Move to i915_vma_bind as it is part of the binding. Suggested-by: Chris Wilson Cc: Michel Thierry Signed-off-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 11 ----------- drivers/gpu/drm/i915/i915_gem_gtt.c | 16 +++++++++++++++- 2 files changed, 15 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 8d28a5d2437f..8ce363aa492c 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3556,17 +3556,6 @@ search_free: if (ret) goto err_remove_node; - /* allocate before insert / bind */ - if (vma->vm->allocate_va_range) { - trace_i915_va_alloc(vma->vm, vma->node.start, vma->node.size, - VM_TO_TRACE_NAME(vma->vm)); - ret = vma->vm->allocate_va_range(vma->vm, - vma->node.start, - vma->node.size); - if (ret) - goto err_remove_node; - } - trace_i915_vma_bind(vma, flags); ret = i915_vma_bind(vma, obj->cache_level, flags & PIN_GLOBAL ? GLOBAL_BIND : 0); diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 559cecaccf7f..0b679143772a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2927,8 +2927,22 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma) int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) { + int ret; + + if (vma->vm->allocate_va_range) { + trace_i915_va_alloc(vma->vm, vma->node.start, + vma->node.size, + VM_TO_TRACE_NAME(vma->vm)); + + ret = vma->vm->allocate_va_range(vma->vm, + vma->node.start, + vma->node.size); + if (ret) + return ret; + } + if (i915_is_ggtt(vma->vm)) { - int ret = i915_get_ggtt_vma_pages(vma); + ret = i915_get_ggtt_vma_pages(vma); if (ret) return ret; -- cgit v1.2.3 From 249e87de5f2a5dd9176d4c316b35462f22c9d6dc Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 10 Apr 2015 16:59:32 +0300 Subject: drm/i915: fix build for DEBUG_FS=n Fix DEBUG_FS=n build broken by commit aa7471d228eb6dfddd0d201ea9746d6a2020972a Author: Jani Nikula Date: Wed Apr 1 11:15:21 2015 +0300 drm/i915: add i915 specific connector debugfs file for DPCD Reported-by: kbuild test robot Signed-off-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3668d613aeb8..6bdd1a6b395d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3029,10 +3029,11 @@ int i915_verify_lists(struct drm_device *dev); /* i915_debugfs.c */ int i915_debugfs_init(struct drm_minor *minor); void i915_debugfs_cleanup(struct drm_minor *minor); -int i915_debugfs_connector_add(struct drm_connector *connector); #ifdef CONFIG_DEBUG_FS +int i915_debugfs_connector_add(struct drm_connector *connector); void intel_display_crc_init(struct drm_device *dev); #else +static inline int i915_debugfs_connector_add(struct drm_connector *connector) {} static inline void intel_display_crc_init(struct drm_device *dev) {} #endif -- cgit v1.2.3 From a6631bc8d60d4c3159bc3dd0897664096f9e9ccd Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Fri, 10 Apr 2015 11:24:27 +0100 Subject: drm/i915: Remove unused variable from execlists_context_queue After commit d7b9ca2f7a41cd36f5ca6c220df48ca9294ed37a ("drm/i915: Remove request->uniq") dev_priv is no longer needed. Cc: Chris Wilson Signed-off-by: Michel Thierry Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_lrc.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index aa3ea64e4815..0fc35dd8a15c 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -523,7 +523,6 @@ static int execlists_context_queue(struct intel_engine_cs *ring, struct drm_i915_gem_request *request) { struct drm_i915_gem_request *cursor; - struct drm_i915_private *dev_priv = ring->dev->dev_private; int num_elements = 0; if (to != ring->default_context) -- cgit v1.2.3 From 9bdbd0b911086d03a27e1fe9531b41f5411ccfac Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Fri, 10 Apr 2015 10:59:10 +0300 Subject: drm/i915: Allocate connector state together with the connectors Connector states were being allocated in intel_setup_outputs() in loop over all connectors. That meant hot-added connectors would have a NULL state. Since the change to use a struct drm_atomic_state for the legacy modeset, connector states are necessary for the i915 driver to function properly, so that would lead to oopses. v2: Fix test for intel_connector_init() success in lvds and sdvo (PRTS) Signed-off-by: Ander Conselvan de Oliveira Reported-and-tested-by: Nicolas Kalkhof Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_crt.c | 2 +- drivers/gpu/drm/i915/intel_ddi.c | 4 +-- drivers/gpu/drm/i915/intel_display.c | 62 ++++++++++++++++-------------------- drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_dsi.c | 2 +- drivers/gpu/drm/i915/intel_dvo.c | 2 +- drivers/gpu/drm/i915/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/intel_lvds.c | 6 ++++ drivers/gpu/drm/i915/intel_sdvo.c | 22 +++++++++++-- drivers/gpu/drm/i915/intel_tv.c | 2 +- 12 files changed, 64 insertions(+), 46 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index fa5699c8452b..93bb5159d093 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -851,7 +851,7 @@ void intel_crt_init(struct drm_device *dev) if (!crt) return; - intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); + intel_connector = intel_connector_alloc(); if (!intel_connector) { kfree(crt); return; diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 8c692d8a3ef6..486f6fa68db1 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2101,7 +2101,7 @@ intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) struct intel_connector *connector; enum port port = intel_dig_port->port; - connector = kzalloc(sizeof(*connector), GFP_KERNEL); + connector = intel_connector_alloc(); if (!connector) return NULL; @@ -2120,7 +2120,7 @@ intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) struct intel_connector *connector; enum port port = intel_dig_port->port; - connector = kzalloc(sizeof(*connector), GFP_KERNEL); + connector = intel_connector_alloc(); if (!connector) return NULL; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a0be6ab7ba7b..4a074aa685e6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5685,6 +5685,34 @@ static void intel_connector_check_state(struct intel_connector *connector) } } +int intel_connector_init(struct intel_connector *connector) +{ + struct drm_connector_state *connector_state; + + connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); + if (!connector_state) + return -ENOMEM; + + connector->base.state = connector_state; + return 0; +} + +struct intel_connector *intel_connector_alloc(void) +{ + struct intel_connector *connector; + + connector = kzalloc(sizeof *connector, GFP_KERNEL); + if (!connector) + return NULL; + + if (intel_connector_init(connector) < 0) { + kfree(connector); + return NULL; + } + + return connector; +} + /* Even simpler default implementation, if there's really no special case to * consider. */ void intel_connector_dpms(struct drm_connector *connector, int mode) @@ -13187,7 +13215,6 @@ static void intel_setup_outputs(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_encoder *encoder; - struct drm_connector *connector; bool dpd_is_edp = false; intel_lvds_init(dev); @@ -13323,39 +13350,6 @@ static void intel_setup_outputs(struct drm_device *dev) if (SUPPORTS_TV(dev)) intel_tv_init(dev); - /* - * FIXME: We don't have full atomic support yet, but we want to be - * able to enable/test plane updates via the atomic interface in the - * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core - * will take some atomic codepaths to lookup properties during - * drmModeGetConnector() that unconditionally dereference - * connector->state. - * - * We create a dummy connector state here for each connector to ensure - * the DRM core doesn't try to dereference a NULL connector->state. - * The actual connector properties will never be updated or contain - * useful information, but since we're doing this specifically for - * testing/debug of the plane operations (and only when a specific - * kernel module option is given), that shouldn't really matter. - * - * We are also relying on these states to convert the legacy mode set - * to use a drm_atomic_state struct. The states are kept consistent - * with actual state, so that it is safe to rely on that instead of - * the staged config. - * - * Once atomic support for crtc's + connectors lands, this loop should - * be removed since we'll be setting up real connector state, which - * will contain Intel-specific properties. - */ - list_for_each_entry(connector, - &dev->mode_config.connector_list, - head) { - if (!WARN_ON(connector->state)) { - connector->state = kzalloc(sizeof(*connector->state), - GFP_KERNEL); - } - } - intel_psr_init(dev); for_each_intel_encoder(dev, encoder) { diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1b87969536ff..589cd92d5c30 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5602,7 +5602,7 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) if (!intel_dig_port) return; - intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); + intel_connector = intel_connector_alloc(); if (!intel_connector) { kfree(intel_dig_port); return; diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index adcc5e641347..73350894e2c9 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -415,7 +415,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo struct drm_connector *connector; int i; - intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); + intel_connector = intel_connector_alloc(); if (!intel_connector) return NULL; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 7a0aa2431bc0..638024fcc8ff 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -928,6 +928,8 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc); void intel_crtc_control(struct drm_crtc *crtc, bool enable); void intel_crtc_update_dpms(struct drm_crtc *crtc); void intel_encoder_destroy(struct drm_encoder *encoder); +int intel_connector_init(struct intel_connector *); +struct intel_connector *intel_connector_alloc(void); void intel_connector_dpms(struct drm_connector *, int mode); bool intel_connector_get_hw_state(struct intel_connector *connector); void intel_modeset_check_state(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 572251e9810b..51966426addf 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -1007,7 +1007,7 @@ void intel_dsi_init(struct drm_device *dev) if (!intel_dsi) return; - intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); + intel_connector = intel_connector_alloc(); if (!intel_connector) { kfree(intel_dsi); return; diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index 9a27ec7100ef..7c9f85285aea 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -469,7 +469,7 @@ void intel_dvo_init(struct drm_device *dev) if (!intel_dvo) return; - intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); + intel_connector = intel_connector_alloc(); if (!intel_connector) { kfree(intel_dvo); return; diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 26222e6c1ff3..02252d9a0cc3 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1755,7 +1755,7 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) if (!intel_dig_port) return; - intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); + intel_connector = intel_connector_alloc(); if (!intel_connector) { kfree(intel_dig_port); return; diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 314a5d56ace2..9a9df0fa67f9 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -946,6 +946,12 @@ void intel_lvds_init(struct drm_device *dev) return; } + if (intel_connector_init(&lvds_connector->base) < 0) { + kfree(lvds_connector); + kfree(lvds_encoder); + return; + } + lvds_encoder->attached_connector = lvds_connector; intel_encoder = &lvds_encoder->base; diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index b121796c86aa..10cd33252838 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -2427,6 +2427,22 @@ intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, } } +static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) +{ + struct intel_sdvo_connector *sdvo_connector; + + sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); + if (!sdvo_connector) + return NULL; + + if (intel_connector_init(&sdvo_connector->base) < 0) { + kfree(sdvo_connector); + return NULL; + } + + return sdvo_connector; +} + static bool intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) { @@ -2438,7 +2454,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) DRM_DEBUG_KMS("initialising DVI device %d\n", device); - intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); + intel_sdvo_connector = intel_sdvo_connector_alloc(); if (!intel_sdvo_connector) return false; @@ -2492,7 +2508,7 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) DRM_DEBUG_KMS("initialising TV type %d\n", type); - intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); + intel_sdvo_connector = intel_sdvo_connector_alloc(); if (!intel_sdvo_connector) return false; @@ -2571,7 +2587,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) DRM_DEBUG_KMS("initialising LVDS device %d\n", device); - intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); + intel_sdvo_connector = intel_sdvo_connector_alloc(); if (!intel_sdvo_connector) return false; diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index bc1d9d740904..8b9d325bda3c 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1621,7 +1621,7 @@ intel_tv_init(struct drm_device *dev) return; } - intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); + intel_connector = intel_connector_alloc(); if (!intel_connector) { kfree(intel_tv); return; -- cgit v1.2.3 From cb07bae0c47c5b66e8e1cc94988d8b48a415ec7d Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Sun, 12 Apr 2015 11:28:14 +0530 Subject: drm/i915: Disable Render power gating When RC6 along with Render power gating is enabled, GPU hang happens due to lack of synchronization between GTI and Render power gating. v2: Updated commit message and WA name (Damien) Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c Reviewed-by: Damien Lespiau Signed-off-by: Sagar Kamble Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e04ef19673a9..fc7e0c7545fd 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4346,9 +4346,12 @@ static void gen9_enable_rc6(struct drm_device *dev) GEN6_RC_CTL_EI_MODE(1) | rc6_mask); - /* 3b: Enable Coarse Power Gating only when RC6 is enabled */ + /* + * 3b: Enable Coarse Power Gating only when RC6 is enabled. + * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6. + */ I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); + GEN9_MEDIA_PG_ENABLE : 0); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); -- cgit v1.2.3 From 1c9a2d4ace0d93ac4e0ef3b7cf6b7fd51d6af189 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Tue, 7 Apr 2015 15:28:35 -0700 Subject: drm/i915: Register definitions for skylake scalers Adding register definitions for skylake scalers. v2: -add #define for plane selection mask (me) Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 115 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1d58d9c587c0..da5c86acace5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5110,6 +5110,121 @@ enum skl_disp_power_wells { #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) +/* + * Skylake scalers + */ +#define _PS_1A_CTRL 0x68180 +#define _PS_2A_CTRL 0x68280 +#define _PS_1B_CTRL 0x68980 +#define _PS_2B_CTRL 0x68A80 +#define _PS_1C_CTRL 0x69180 +#define PS_SCALER_EN (1 << 31) +#define PS_SCALER_MODE_MASK (3 << 28) +#define PS_SCALER_MODE_DYN (0 << 28) +#define PS_SCALER_MODE_HQ (1 << 28) +#define PS_PLANE_SEL_MASK (7 << 25) +#define PS_PLANE_SEL(plane) ((plane + 1) << 25) +#define PS_FILTER_MASK (3 << 23) +#define PS_FILTER_MEDIUM (0 << 23) +#define PS_FILTER_EDGE_ENHANCE (2 << 23) +#define PS_FILTER_BILINEAR (3 << 23) +#define PS_VERT3TAP (1 << 21) +#define PS_VERT_INT_INVERT_FIELD1 (0 << 20) +#define PS_VERT_INT_INVERT_FIELD0 (1 << 20) +#define PS_PWRUP_PROGRESS (1 << 17) +#define PS_V_FILTER_BYPASS (1 << 8) +#define PS_VADAPT_EN (1 << 7) +#define PS_VADAPT_MODE_MASK (3 << 5) +#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) +#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) +#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) + +#define _PS_PWR_GATE_1A 0x68160 +#define _PS_PWR_GATE_2A 0x68260 +#define _PS_PWR_GATE_1B 0x68960 +#define _PS_PWR_GATE_2B 0x68A60 +#define _PS_PWR_GATE_1C 0x69160 +#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) +#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) +#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) +#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) +#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) +#define PS_PWR_GATE_SLPEN_8 0 +#define PS_PWR_GATE_SLPEN_16 1 +#define PS_PWR_GATE_SLPEN_24 2 +#define PS_PWR_GATE_SLPEN_32 3 + +#define _PS_WIN_POS_1A 0x68170 +#define _PS_WIN_POS_2A 0x68270 +#define _PS_WIN_POS_1B 0x68970 +#define _PS_WIN_POS_2B 0x68A70 +#define _PS_WIN_POS_1C 0x69170 + +#define _PS_WIN_SZ_1A 0x68174 +#define _PS_WIN_SZ_2A 0x68274 +#define _PS_WIN_SZ_1B 0x68974 +#define _PS_WIN_SZ_2B 0x68A74 +#define _PS_WIN_SZ_1C 0x69174 + +#define _PS_VSCALE_1A 0x68184 +#define _PS_VSCALE_2A 0x68284 +#define _PS_VSCALE_1B 0x68984 +#define _PS_VSCALE_2B 0x68A84 +#define _PS_VSCALE_1C 0x69184 + +#define _PS_HSCALE_1A 0x68190 +#define _PS_HSCALE_2A 0x68290 +#define _PS_HSCALE_1B 0x68990 +#define _PS_HSCALE_2B 0x68A90 +#define _PS_HSCALE_1C 0x69190 + +#define _PS_VPHASE_1A 0x68188 +#define _PS_VPHASE_2A 0x68288 +#define _PS_VPHASE_1B 0x68988 +#define _PS_VPHASE_2B 0x68A88 +#define _PS_VPHASE_1C 0x69188 + +#define _PS_HPHASE_1A 0x68194 +#define _PS_HPHASE_2A 0x68294 +#define _PS_HPHASE_1B 0x68994 +#define _PS_HPHASE_2B 0x68A94 +#define _PS_HPHASE_1C 0x69194 + +#define _PS_ECC_STAT_1A 0x681D0 +#define _PS_ECC_STAT_2A 0x682D0 +#define _PS_ECC_STAT_1B 0x689D0 +#define _PS_ECC_STAT_2B 0x68AD0 +#define _PS_ECC_STAT_1C 0x691D0 + +#define _ID(id, a, b) ((a) + (id)*((b)-(a))) +#define SKL_PS_CTRL(pipe, id) _PIPE(pipe, \ + _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ + _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) +#define SKL_PS_PWR_GATE(pipe, id) _PIPE(pipe, \ + _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ + _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) +#define SKL_PS_WIN_POS(pipe, id) _PIPE(pipe, \ + _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ + _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) +#define SKL_PS_WIN_SZ(pipe, id) _PIPE(pipe, \ + _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ + _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) +#define SKL_PS_VSCALE(pipe, id) _PIPE(pipe, \ + _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ + _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) +#define SKL_PS_HSCALE(pipe, id) _PIPE(pipe, \ + _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ + _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) +#define SKL_PS_VPHASE(pipe, id) _PIPE(pipe, \ + _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ + _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) +#define SKL_PS_HPHASE(pipe, id) _PIPE(pipe, \ + _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ + _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) +#define SKL_PS_ECC_STAT(pipe, id) _PIPE(pipe, \ + _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ + _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B) + /* legacy palette */ #define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_B 0x4a800 -- cgit v1.2.3 From be41e336c72c74f439d2f8bf996f5daa6a8b5e3c Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Tue, 7 Apr 2015 15:28:36 -0700 Subject: drm/i915: skylake scaler structure definitions skylake scaler structure definitions. scalers live in crtc_state as they are pipe resources. They can be used either as plane scaler or panel fitter. scaler assigned to either plane (for plane scaling) or crtc (for panel fitting) is saved in scaler_id in plane_state or crtc_state respectively. scaler_id is used instead of scaler pointer in plane or crtc state to avoid updating scaler pointer everytime a new crtc_state is created. v2: -made single copy of min/max values for scalers (Matt) v3: -updated commentary for scaler_id (me) v4: -converted src/dst ranges to #defines, dropped ratios (Matt) Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_drv.h | 68 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 638024fcc8ff..40112751ca6e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -256,6 +256,26 @@ struct intel_plane_state { * enable/disable the primary plane */ bool hides_primary; + + /* + * scaler_id + * = -1 : not using a scaler + * >= 0 : using a scalers + * + * plane requiring a scaler: + * - During check_plane, its bit is set in + * crtc_state->scaler_state.scaler_users by calling helper function + * update_scaler_users. + * - scaler_id indicates the scaler it got assigned. + * + * plane doesn't require a scaler: + * - this can happen when scaling is no more required or plane simply + * got disabled. + * - During check_plane, corresponding bit is reset in + * crtc_state->scaler_state.scaler_users by calling helper function + * update_scaler_users. + */ + int scaler_id; }; struct intel_initial_plane_config { @@ -265,6 +285,49 @@ struct intel_initial_plane_config { u32 base; }; +#define SKL_MIN_SRC_W 8 +#define SKL_MAX_SRC_W 4096 +#define SKL_MIN_SRC_H 8 +#define SKL_MAX_SRC_H 2304 +#define SKL_MIN_DST_W 8 +#define SKL_MAX_DST_W 4096 +#define SKL_MIN_DST_H 8 +#define SKL_MAX_DST_H 2304 + +struct intel_scaler { + int id; + int in_use; + uint32_t mode; +}; + +struct intel_crtc_scaler_state { +#define SKL_NUM_SCALERS 2 + struct intel_scaler scalers[SKL_NUM_SCALERS]; + + /* + * scaler_users: keeps track of users requesting scalers on this crtc. + * + * If a bit is set, a user is using a scaler. + * Here user can be a plane or crtc as defined below: + * bits 0-30 - plane (bit position is index from drm_plane_index) + * bit 31 - crtc + * + * Instead of creating a new index to cover planes and crtc, using + * existing drm_plane_index for planes which is well less than 31 + * planes and bit 31 for crtc. This should be fine to cover all + * our platforms. + * + * intel_atomic_setup_scalers will setup available scalers to users + * requesting scalers. It will gracefully fail if request exceeds + * avilability. + */ +#define SKL_CRTC_INDEX 31 + unsigned scaler_users; + + /* scaler used by crtc for panel fitting purpose */ + int scaler_id; +}; + struct intel_crtc_state { struct drm_crtc_state base; @@ -391,6 +454,8 @@ struct intel_crtc_state { bool dp_encoder_is_mst; int pbn; + + struct intel_crtc_scaler_state scaler_state; }; struct intel_pipe_wm { @@ -492,6 +557,9 @@ struct intel_crtc { struct intel_mmio_flip mmio_flip; struct intel_crtc_atomic_commit atomic; + + /* scalers available on this crtc */ + int num_scalers; }; struct intel_plane_wm_parameters { -- cgit v1.2.3 From 08e221fbf69a1e8da66526b340560e99e3e4eed9 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Tue, 7 Apr 2015 15:28:37 -0700 Subject: drm/i915: Initialize plane colorkey to NONE This patch initializes plane colorkey to NONE. Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 1 + drivers/gpu/drm/i915/intel_sprite.c | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4a074aa685e6..d98d5f239dd7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12866,6 +12866,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, primary->plane = pipe; primary->check_plane = intel_check_primary_plane; primary->commit_plane = intel_commit_primary_plane; + primary->ckey.flags = I915_SET_COLORKEY_NONE; if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) primary->plane = !pipe; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 21682a8b60a3..7d1a5b86d06c 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1307,6 +1307,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) intel_plane->plane = plane; intel_plane->check_plane = intel_check_sprite_plane; intel_plane->commit_plane = intel_commit_sprite_plane; + intel_plane->ckey.flags = I915_SET_COLORKEY_NONE; possible_crtcs = (1 << pipe); ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, &intel_plane_funcs, -- cgit v1.2.3 From 549e2bfb54905c734aae77d2cdb809a7acaefeeb Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Tue, 7 Apr 2015 15:28:38 -0700 Subject: drm/i915: Initialize skylake scalers Initializing scalers with supported values during crtc init. v2: -initialize single copy of min/max values (Matt) v3: -moved gen check to callsite (Matt) v4: -squashed planes begin with no scaler to here (me) v5: -updated init function with updated scaler state structure (Matt) Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_sprite.c | 1 + 2 files changed, 33 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d98d5f239dd7..402fad0870ba 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -103,6 +103,8 @@ static void chv_prepare_pll(struct intel_crtc *crtc, const struct intel_crtc_state *pipe_config); static void intel_begin_crtc_commit(struct drm_crtc *crtc); static void intel_finish_crtc_commit(struct drm_crtc *crtc); +static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, + struct intel_crtc_state *crtc_state); static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) { @@ -12862,6 +12864,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, primary->can_scale = false; primary->max_downscale = 1; + state->scaler_id = -1; primary->pipe = pipe; primary->plane = pipe; primary->check_plane = intel_check_primary_plane; @@ -13026,6 +13029,7 @@ static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, cursor->max_downscale = 1; cursor->pipe = pipe; cursor->plane = pipe; + state->scaler_id = -1; cursor->check_plane = intel_check_cursor_plane; cursor->commit_plane = intel_commit_cursor_plane; @@ -13052,6 +13056,24 @@ static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, return &cursor->base; } +static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, + struct intel_crtc_state *crtc_state) +{ + int i; + struct intel_scaler *intel_scaler; + struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; + + for (i = 0; i < intel_crtc->num_scalers; i++) { + intel_scaler = &scaler_state->scalers[i]; + intel_scaler->in_use = 0; + intel_scaler->id = i; + + intel_scaler->mode = PS_SCALER_MODE_DYN; + } + + scaler_state->scaler_id = -1; +} + static void intel_crtc_init(struct drm_device *dev, int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -13071,6 +13093,16 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) intel_crtc_set_state(intel_crtc, crtc_state); crtc_state->base.crtc = &intel_crtc->base; + /* initialize shared scalers */ + if (INTEL_INFO(dev)->gen >= 9) { + if (pipe == PIPE_C) + intel_crtc->num_scalers = 1; + else + intel_crtc->num_scalers = SKL_NUM_SCALERS; + + skl_init_scalers(dev, intel_crtc, crtc_state); + } + primary = intel_primary_plane_create(dev, pipe); if (!primary) goto fail; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 7d1a5b86d06c..6d4e1ea4219f 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1294,6 +1294,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) intel_plane->max_downscale = 1; intel_plane->update_plane = skl_update_plane; intel_plane->disable_plane = skl_disable_plane; + state->scaler_id = -1; plane_formats = skl_plane_formats; num_plane_formats = ARRAY_SIZE(skl_plane_formats); -- cgit v1.2.3 From 0a5ae1b074899f420ea93c019619342b32fe1ad2 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Thu, 9 Apr 2015 16:41:54 -0700 Subject: drm/i915: Keep sprite plane src rect in 16.16 format This patch keeps intel_plane_state->src rect back into 16.16 format. v2: -sprite src rect to match primary format (Matt, Daniel) v3: -moved a hunk from #14 to keep src rect in check & commit in tandom (Matt) Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_sprite.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 6d4e1ea4219f..0cb37674b43a 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1037,10 +1037,10 @@ intel_check_sprite_plane(struct drm_plane *plane, } if (state->visible) { - src->x1 = src_x; - src->x2 = src_x + src_w; - src->y1 = src_y; - src->y2 = src_y + src_h; + src->x1 = src_x << 16; + src->x2 = (src_x + src_w) << 16; + src->y1 = src_y << 16; + src->y2 = (src_y + src_h) << 16; } dst->x1 = crtc_x; @@ -1112,10 +1112,10 @@ intel_commit_sprite_plane(struct drm_plane *plane, crtc_y = state->dst.y1; crtc_w = drm_rect_width(&state->dst); crtc_h = drm_rect_height(&state->dst); - src_x = state->src.x1; - src_y = state->src.y1; - src_w = drm_rect_width(&state->src); - src_h = drm_rect_height(&state->src); + src_x = state->src.x1 >> 16; + src_y = state->src.y1 >> 16; + src_w = drm_rect_width(&state->src) >> 16; + src_h = drm_rect_height(&state->src) >> 16; intel_plane->update_plane(plane, crtc, fb, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h); -- cgit v1.2.3 From 6a60cd87cdc6fab14c33b2ddf338e5de6bf21e87 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Tue, 7 Apr 2015 15:28:40 -0700 Subject: drm/i915: Dump scaler_state too as part of dumping crtc_state Dumps scaler state as part of dumping crtc_state. v2: -use regular ints from plane_state->src (me) v3: -changes to align with updated scaler structures (Matt) -interpret plane_state->src as 16.16 format (Matt, Daniel) Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 402fad0870ba..26f1602bec68 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10638,8 +10638,14 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, const char *context) { - DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, - context, pipe_name(crtc->pipe)); + struct drm_device *dev = crtc->base.dev; + struct drm_plane *plane; + struct intel_plane *intel_plane; + struct intel_plane_state *state; + struct drm_framebuffer *fb; + + DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, + context, pipe_config, pipe_name(crtc->pipe)); DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", @@ -10676,6 +10682,9 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); DRM_DEBUG_KMS("pipe src size: %dx%d\n", pipe_config->pipe_src_w, pipe_config->pipe_src_h); + DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers); + DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users); + DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id); DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", pipe_config->gmch_pfit.control, pipe_config->gmch_pfit.pgm_ratios, @@ -10686,6 +10695,40 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); + + DRM_DEBUG_KMS("planes on this crtc\n"); + list_for_each_entry(plane, &dev->mode_config.plane_list, head) { + intel_plane = to_intel_plane(plane); + if (intel_plane->pipe != crtc->pipe) + continue; + + state = to_intel_plane_state(plane->state); + fb = state->base.fb; + if (!fb) { + DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " + "disabled, scaler_id = %d\n", + plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", + plane->base.id, intel_plane->pipe, + (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, + drm_plane_index(plane), state->scaler_id); + continue; + } + + DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", + plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", + plane->base.id, intel_plane->pipe, + crtc->base.primary == plane ? 0 : intel_plane->plane + 1, + drm_plane_index(plane)); + DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", + fb->base.id, fb->width, fb->height, fb->pixel_format); + DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", + state->scaler_id, + state->src.x1 >> 16, state->src.y1 >> 16, + drm_rect_width(&state->src) >> 16, + drm_rect_height(&state->src) >> 16, + state->dst.x1, state->dst.y1, + drm_rect_width(&state->dst), drm_rect_height(&state->dst)); + } } static bool encoders_cloneable(const struct intel_encoder *a, -- cgit v1.2.3 From 663a36407a71b3a98cea087f9a215660a6d6e387 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Tue, 7 Apr 2015 15:28:41 -0700 Subject: drm/i915: Preserve scaler state when clearing crtc_state crtc_state is cleared during mode set which wipes out complete scaler state too. This is causing issues. To fix, ensure scaler state is preserved because it contains not only crtc scaler usage, but also planes using scalers on this crtc. Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 26f1602bec68..c14ab7b2f831 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10839,11 +10839,14 @@ static void clear_intel_crtc_state(struct intel_crtc_state *crtc_state) { struct drm_crtc_state tmp_state; + struct intel_crtc_scaler_state scaler_state; - /* Clear only the intel specific part of the crtc state */ + /* Clear only the intel specific part of the crtc state excluding scalers */ tmp_state = crtc_state->base; + scaler_state = crtc_state->scaler_state; memset(crtc_state, 0, sizeof *crtc_state); crtc_state->base = tmp_state; + crtc_state->scaler_state = scaler_state; } static struct intel_crtc_state * -- cgit v1.2.3 From d03c93d4801563de43abf91e56ff4b3fbc8cc7e4 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Thu, 9 Apr 2015 16:42:46 -0700 Subject: drm/i915: setup scalers for crtc_compute_config Added intel_atomic_setup_scalers to setup scalers based on staged scaling requests from a crtc and its planes. If staged requests are supportable, this function assigns scalers to requested planes and crtc. Note that the scaler assignement itself is staged into crtc_state and respective plane_states for later commit after all checks have been done. overall high level flow: - scaler requests are staged into crtc_state by planes/crtc - check whether staged scaling requests can be supported - add planes using scalers that aren't in current transaction - assign scalers to requested users - as part of plane commit, scalers will be committed (i.e., either attached or detached) to respective planes in hw - as part of crtc_commit, scaler will be either attached or detached to crtc in hw crtc_compute_config calls intel_atomic_setup_scalers() to start scaler assignments as per scaler state in crtc config. This call should be moved to atomic crtc once it is available. v2: -removed a log message (me) -changed input parameter to crtc_state (me) v3: -remove assigning plane_state returned by drm_atomic_get_plane_state (Matt) -fail if there is an error from drm_atomic_get_plane_state (Matt) v4: -changes to align with updated scaler structure (Matt, me) v5: -added addtional checks before enabling HQ mode (me) -added comments to enable HQ mode (Matt) Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_atomic.c | 148 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 10 ++- drivers/gpu/drm/i915/intel_drv.h | 3 + 3 files changed, 160 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index b4ea6762e4ef..c5e4b6c30643 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -243,3 +243,151 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, { drm_atomic_helper_crtc_destroy_state(crtc, state); } + +/** + * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests + * @dev: DRM device + * @crtc: intel crtc + * @crtc_state: incoming crtc_state to validate and setup scalers + * + * This function sets up scalers based on staged scaling requests for + * a @crtc and its planes. It is called from crtc level check path. If request + * is a supportable request, it attaches scalers to requested planes and crtc. + * + * This function takes into account the current scaler(s) in use by any planes + * not being part of this atomic state + * + * Returns: + * 0 - scalers were setup succesfully + * error code - otherwise + */ +int intel_atomic_setup_scalers(struct drm_device *dev, + struct intel_crtc *intel_crtc, + struct intel_crtc_state *crtc_state) +{ + struct drm_plane *plane = NULL; + struct intel_plane *intel_plane; + struct intel_plane_state *plane_state = NULL; + struct intel_crtc_scaler_state *scaler_state; + struct drm_atomic_state *drm_state; + int num_scalers_need; + int i, j; + + if (INTEL_INFO(dev)->gen < 9 || !intel_crtc || !crtc_state) + return 0; + + scaler_state = &crtc_state->scaler_state; + drm_state = crtc_state->base.state; + + num_scalers_need = hweight32(scaler_state->scaler_users); + DRM_DEBUG_KMS("crtc_state = %p need = %d avail = %d scaler_users = 0x%x\n", + crtc_state, num_scalers_need, intel_crtc->num_scalers, + scaler_state->scaler_users); + + /* + * High level flow: + * - staged scaler requests are already in scaler_state->scaler_users + * - check whether staged scaling requests can be supported + * - add planes using scalers that aren't in current transaction + * - assign scalers to requested users + * - as part of plane commit, scalers will be committed + * (i.e., either attached or detached) to respective planes in hw + * - as part of crtc_commit, scaler will be either attached or detached + * to crtc in hw + */ + + /* fail if required scalers > available scalers */ + if (num_scalers_need > intel_crtc->num_scalers){ + DRM_DEBUG_KMS("Too many scaling requests %d > %d\n", + num_scalers_need, intel_crtc->num_scalers); + return -EINVAL; + } + + /* walkthrough scaler_users bits and start assigning scalers */ + for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { + int *scaler_id; + + /* skip if scaler not required */ + if (!(scaler_state->scaler_users & (1 << i))) + continue; + + if (i == SKL_CRTC_INDEX) { + /* panel fitter case: assign as a crtc scaler */ + scaler_id = &scaler_state->scaler_id; + } else { + if (!drm_state) + continue; + + /* plane scaler case: assign as a plane scaler */ + /* find the plane that set the bit as scaler_user */ + plane = drm_state->planes[i]; + + /* + * to enable/disable hq mode, add planes that are using scaler + * into this transaction + */ + if (!plane) { + struct drm_plane_state *state; + plane = drm_plane_from_index(dev, i); + state = drm_atomic_get_plane_state(drm_state, plane); + if (IS_ERR(state)) { + DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n", + plane->base.id); + return PTR_ERR(state); + } + } + + intel_plane = to_intel_plane(plane); + + /* plane on different crtc cannot be a scaler user of this crtc */ + if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) { + continue; + } + + plane_state = to_intel_plane_state(drm_state->plane_states[i]); + scaler_id = &plane_state->scaler_id; + } + + if (*scaler_id < 0) { + /* find a free scaler */ + for (j = 0; j < intel_crtc->num_scalers; j++) { + if (!scaler_state->scalers[j].in_use) { + scaler_state->scalers[j].in_use = 1; + *scaler_id = scaler_state->scalers[j].id; + DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n", + intel_crtc->pipe, + i == SKL_CRTC_INDEX ? scaler_state->scaler_id : + plane_state->scaler_id, + i == SKL_CRTC_INDEX ? "CRTC" : "PLANE", + i == SKL_CRTC_INDEX ? intel_crtc->base.base.id : + plane->base.id); + break; + } + } + } + + if (WARN_ON(*scaler_id < 0)) { + DRM_DEBUG_KMS("Cannot find scaler for %s:%d\n", + i == SKL_CRTC_INDEX ? "CRTC" : "PLANE", + i == SKL_CRTC_INDEX ? intel_crtc->base.base.id:plane->base.id); + continue; + } + + /* set scaler mode */ + if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) { + /* + * when only 1 scaler is in use on either pipe A or B, + * scaler 0 operates in high quality (HQ) mode. + * In this case use scaler 0 to take advantage of HQ mode + */ + *scaler_id = 0; + scaler_state->scalers[0].in_use = 1; + scaler_state->scalers[0].mode = PS_SCALER_MODE_HQ; + scaler_state->scalers[1].in_use = 0; + } else { + scaler_state->scalers[*scaler_id].mode = PS_SCALER_MODE_DYN; + } + } + + return 0; +} diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c14ab7b2f831..48129fa9360d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5886,6 +5886,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; + int ret; /* FIXME should check pixel clock limits on all platforms */ if (INTEL_INFO(dev)->gen < 4) { @@ -5940,7 +5941,14 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, if (pipe_config->has_pch_encoder) return ironlake_fdi_compute_config(crtc, pipe_config); - return 0; + /* FIXME: remove below call once atomic mode set is place and all crtc + * related checks called from atomic_crtc_check function */ + ret = 0; + DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n", + crtc, pipe_config->base.state); + ret = intel_atomic_setup_scalers(dev, crtc, pipe_config); + + return ret; } static int skylake_get_display_clock_speed(struct drm_device *dev) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 40112751ca6e..885e48295778 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1392,6 +1392,9 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state, return to_intel_crtc_state(crtc_state); } +int intel_atomic_setup_scalers(struct drm_device *dev, + struct intel_crtc *intel_crtc, + struct intel_crtc_state *crtc_state); /* intel_atomic_plane.c */ struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); -- cgit v1.2.3 From e04fa8036203e6f4f82b5a66e6e78e4118d9cfec Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Tue, 7 Apr 2015 15:28:43 -0700 Subject: drm/i915: Ensure setting up scalers into staged crtc_state From intel_atomic_check, call intel_atomic_setup_scalers() to assign scalers based on staged scaling requests. Fail the transaction if setup returns error. Setting up of scalers should be moved to atomic crtc check once atomic crtc is ready. v2: -updated parameter passing to setup_scalers (me) Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_atomic.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index c5e4b6c30643..42045ce29898 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -48,6 +48,8 @@ int intel_atomic_check(struct drm_device *dev, int ncrtcs = dev->mode_config.num_crtc; int nconnectors = dev->mode_config.num_connector; enum pipe nuclear_pipe = INVALID_PIPE; + struct intel_crtc *nuclear_crtc = NULL; + struct intel_crtc_state *crtc_state = NULL; int ret; int i; bool not_nuclear = false; @@ -80,6 +82,10 @@ int intel_atomic_check(struct drm_device *dev, memset(&crtc->atomic, 0, sizeof(crtc->atomic)); if (crtc && crtc->pipe != nuclear_pipe) not_nuclear = true; + if (crtc && crtc->pipe == nuclear_pipe) { + nuclear_crtc = crtc; + crtc_state = to_intel_crtc_state(state->crtc_states[i]); + } } for (i = 0; i < nconnectors; i++) if (state->connectors[i] != NULL) @@ -94,6 +100,11 @@ int intel_atomic_check(struct drm_device *dev, if (ret) return ret; + /* FIXME: move to crtc atomic check function once it is ready */ + ret = intel_atomic_setup_scalers(dev, nuclear_crtc, crtc_state); + if (ret) + return ret; + return ret; } -- cgit v1.2.3 From f76f35dc040e44d63369fdba3124701feec714f0 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Tue, 7 Apr 2015 15:28:44 -0700 Subject: drm/i915: copy staged scaler state from drm state to crtc->config. This is required for commit to perform as per staged assignment of scalers until atomic crtc commit function is available. As a place holder doing this copy from intel_atomic_commit for scaling to operate correctly. Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_atomic.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index 42045ce29898..3c4b7cdeab77 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -168,6 +168,18 @@ int intel_atomic_commit(struct drm_device *dev, swap(state->plane_states[i], plane->state); plane->state->state = NULL; } + + /* swap crtc_state */ + for (i = 0; i < dev->mode_config.num_crtc; i++) { + struct drm_crtc *crtc = state->crtcs[i]; + if (!crtc) { + continue; + } + + to_intel_crtc(crtc)->config->scaler_state = + to_intel_crtc_state(state->crtc_states[i])->scaler_state; + } + drm_atomic_helper_commit_planes(dev, state); drm_atomic_helper_wait_for_vblanks(dev, state); drm_atomic_helper_cleanup_planes(dev, state); -- cgit v1.2.3 From a1b2278e4dfcd2dbea85e319ebf73a6b7b2f180b Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Tue, 7 Apr 2015 15:28:45 -0700 Subject: drm/i915: skylake panel fitting using shared scalers Enabling skylake panel fitting feature using shared scalers v2: -added force detach parameter for pfit disable purpose (me) -read crtc scaler state from hw state (Daniel) -replaced both skylake_pfit_enable and disable with skylake_pfit_update (me) -added scaler id check to intel_pipe_config_compare (Daniel) v3: -updated function header to kerneldoc format (Matt) -dropped need_scaling checks (Matt) v4: -move clearing of scaler id from commit path to check path (Matt) -updated colorkey checks based on recent updates (me) -squashed scaler check while enabling colorkey to here (me) -use values in plane_state->src as regular integers (me) -changes made not to modify state in commit path (Matt) v5: -squashed helper function to update scaler users to here (Matt) -squashed helper function to detach scaler to here (Matt, me) -changes to align with updated scaler structures (Matt, me) Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 250 +++++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/intel_dp.c | 8 ++ drivers/gpu/drm/i915/intel_drv.h | 4 + 3 files changed, 235 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 48129fa9360d..97922fb90824 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2931,6 +2931,35 @@ unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, return i915_gem_obj_ggtt_offset_view(obj, view); } +/* + * This function detaches (aka. unbinds) unused scalers in hardware + */ +void skl_detach_scalers(struct intel_crtc *intel_crtc) +{ + struct drm_device *dev; + struct drm_i915_private *dev_priv; + struct intel_crtc_scaler_state *scaler_state; + int i; + + if (!intel_crtc || !intel_crtc->config) + return; + + dev = intel_crtc->base.dev; + dev_priv = dev->dev_private; + scaler_state = &intel_crtc->config->scaler_state; + + /* loop through and disable scalers that aren't in use */ + for (i = 0; i < intel_crtc->num_scalers; i++) { + if (!scaler_state->scalers[i].in_use) { + I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0); + I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0); + I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0); + DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n", + intel_crtc->base.base.id, intel_crtc->pipe, i); + } + } +} + static void skylake_update_primary_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, int x, int y) @@ -4280,16 +4309,175 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe) } } -static void skylake_pfit_enable(struct intel_crtc *crtc) +/** + * skl_update_scaler_users - Stages update to crtc's scaler state + * @intel_crtc: crtc + * @crtc_state: crtc_state + * @plane: plane (NULL indicates crtc is requesting update) + * @plane_state: plane's state + * @force_detach: request unconditional detachment of scaler + * + * This function updates scaler state for requested plane or crtc. + * To request scaler usage update for a plane, caller shall pass plane pointer. + * To request scaler usage update for crtc, caller shall pass plane pointer + * as NULL. + * + * Return + * 0 - scaler_usage updated successfully + * error - requested scaling cannot be supported or other error condition + */ +int +skl_update_scaler_users( + struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, + struct intel_plane *intel_plane, struct intel_plane_state *plane_state, + int force_detach) +{ + int need_scaling; + int idx; + int src_w, src_h, dst_w, dst_h; + int *scaler_id; + struct drm_framebuffer *fb; + struct intel_crtc_scaler_state *scaler_state; + + if (!intel_crtc || !crtc_state) + return 0; + + scaler_state = &crtc_state->scaler_state; + + idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX; + fb = intel_plane ? plane_state->base.fb : NULL; + + if (intel_plane) { + src_w = drm_rect_width(&plane_state->src) >> 16; + src_h = drm_rect_height(&plane_state->src) >> 16; + dst_w = drm_rect_width(&plane_state->dst); + dst_h = drm_rect_height(&plane_state->dst); + scaler_id = &plane_state->scaler_id; + } else { + struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; + src_w = crtc_state->pipe_src_w; + src_h = crtc_state->pipe_src_h; + dst_w = adjusted_mode->hdisplay; + dst_h = adjusted_mode->vdisplay; + scaler_id = &scaler_state->scaler_id; + } + need_scaling = (src_w != dst_w || src_h != dst_h); + + /* + * if plane is being disabled or scaler is no more required or force detach + * - free scaler binded to this plane/crtc + * - in order to do this, update crtc->scaler_usage + * + * Here scaler state in crtc_state is set free so that + * scaler can be assigned to other user. Actual register + * update to free the scaler is done in plane/panel-fit programming. + * For this purpose crtc/plane_state->scaler_id isn't reset here. + */ + if (force_detach || !need_scaling || (intel_plane && + (!fb || !plane_state->visible))) { + if (*scaler_id >= 0) { + scaler_state->scaler_users &= ~(1 << idx); + scaler_state->scalers[*scaler_id].in_use = 0; + + DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d " + "crtc_state = %p scaler_users = 0x%x\n", + intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC", + intel_plane ? intel_plane->base.base.id : + intel_crtc->base.base.id, crtc_state, + scaler_state->scaler_users); + *scaler_id = -1; + } + return 0; + } + + /* range checks */ + if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || + dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || + + src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || + dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { + DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u " + "size is out of scaler range\n", + intel_plane ? "PLANE" : "CRTC", + intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, + intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h); + return -EINVAL; + } + + /* check colorkey */ + if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) { + DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed", + intel_plane->base.base.id); + return -EINVAL; + } + + /* Check src format */ + if (intel_plane) { + switch (fb->pixel_format) { + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + break; + default: + DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n", + intel_plane->base.base.id, fb->base.id, fb->pixel_format); + return -EINVAL; + } + } + + /* mark this plane as a scaler user in crtc_state */ + scaler_state->scaler_users |= (1 << idx); + DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u " + "crtc_state = %p scaler_users = 0x%x\n", + intel_plane ? "PLANE" : "CRTC", + intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, + src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users); + return 0; +} + +static void skylake_pfit_update(struct intel_crtc *crtc, int enable) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; int pipe = crtc->pipe; + struct intel_crtc_scaler_state *scaler_state = + &crtc->config->scaler_state; + + DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); + + /* To update pfit, first update scaler state */ + skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable); + intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config); + skl_detach_scalers(crtc); + if (!enable) + return; if (crtc->config->pch_pfit.enabled) { - I915_WRITE(PS_CTL(pipe), PS_ENABLE); - I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos); - I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size); + int id; + + if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { + DRM_ERROR("Requesting pfit without getting a scaler first\n"); + return; + } + + id = scaler_state->scaler_id; + I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | + PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); + I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); + I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); + + DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); } } @@ -4694,7 +4882,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_ddi_enable_pipe_clock(intel_crtc); if (IS_SKYLAKE(dev)) - skylake_pfit_enable(intel_crtc); + skylake_pfit_update(intel_crtc, 1); else ironlake_pfit_enable(intel_crtc); @@ -4730,21 +4918,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_crtc_enable_planes(crtc); } -static void skylake_pfit_disable(struct intel_crtc *crtc) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - int pipe = crtc->pipe; - - /* To avoid upsetting the power well on haswell only disable the pfit if - * it's in use. The hw state code will make sure we get this right. */ - if (crtc->config->pch_pfit.enabled) { - I915_WRITE(PS_CTL(pipe), 0); - I915_WRITE(PS_WIN_POS(pipe), 0); - I915_WRITE(PS_WIN_SZ(pipe), 0); - } -} - static void ironlake_pfit_disable(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; @@ -4857,7 +5030,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); if (IS_SKYLAKE(dev)) - skylake_pfit_disable(intel_crtc); + skylake_pfit_update(intel_crtc, 0); else ironlake_pfit_disable(intel_crtc); @@ -8146,14 +8319,28 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - uint32_t tmp; + struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; + uint32_t ps_ctrl = 0; + int id = -1; + int i; - tmp = I915_READ(PS_CTL(crtc->pipe)); + /* find scaler attached to this pipe */ + for (i = 0; i < crtc->num_scalers; i++) { + ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); + if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { + id = i; + pipe_config->pch_pfit.enabled = true; + pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); + pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); + break; + } + } - if (tmp & PS_ENABLE) { - pipe_config->pch_pfit.enabled = true; - pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); - pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); + scaler_state->scaler_id = id; + if (id >= 0) { + scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); + } else { + scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); } } @@ -8787,12 +8974,19 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, intel_get_pipe_timings(crtc, pipe_config); + if (INTEL_INFO(dev)->gen >= 9) { + skl_init_scalers(dev, crtc, pipe_config); + } + pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { if (IS_SKYLAKE(dev)) skylake_get_pfit_config(crtc, pipe_config); else ironlake_get_pfit_config(crtc, pipe_config); + } else { + pipe_config->scaler_state.scaler_id = -1; + pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); } if (IS_HASWELL(dev)) @@ -11320,6 +11514,8 @@ intel_pipe_config_compare(struct drm_device *dev, PIPE_CONF_CHECK_I(pch_pfit.size); } + PIPE_CONF_CHECK_I(scaler_state.scaler_id); + /* BDW+ don't expose a synchronous way to read the state */ if (IS_HASWELL(dev)) PIPE_CONF_CHECK_I(ips_enabled); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 589cd92d5c30..3ea68e164873 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1351,6 +1351,14 @@ intel_dp_compute_config(struct intel_encoder *encoder, if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { intel_fixed_panel_mode(intel_connector->panel.fixed_mode, adjusted_mode); + + if (INTEL_INFO(dev)->gen >= 9) { + int ret; + ret = skl_update_scaler_users(intel_crtc, pipe_config, NULL, NULL, 0); + if (ret) + return ret; + } + if (!HAS_PCH_SPLIT(dev)) intel_gmch_panel_fitting(intel_crtc, pipe_config, intel_connector->panel.fitting_mode); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 885e48295778..6a2ee0c38161 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1128,6 +1128,10 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode, struct intel_crtc_state *pipe_config); void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); +void skl_detach_scalers(struct intel_crtc *intel_crtc); +int skl_update_scaler_users(struct intel_crtc *intel_crtc, + struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane, + struct intel_plane_state *plane_state, int force_detach); unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, struct drm_i915_gem_object *obj); -- cgit v1.2.3 From 2def4ad99befa25775dd2f714fdd4d92faec6e34 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 16:20:41 +0100 Subject: drm/i915: Optimistically spin for the request completion This provides a nice boost to mesa in swap bound scenarios (as mesa throttles itself to the previous frame and given the scenario that will complete shortly). It will also provide a good boost to systems running with semaphores disabled and so frequently waiting on the GPU as it switches rings. In the most favourable of microbenchmarks, this can increase performance by around 15% - though in practice improvements will be marginal and rarely noticeable. v2: Account for user timeouts v3: Limit the spinning to a single jiffie (~1us) at most. On an otherwise idle system, there is no scheduler contention and so without a limit we would spin until the GPU is ready. v4: Drop forcewake - the lazy coherent access doesn't require it, and we have no reason to believe that the forcewake itself improves seqno coherency - it only adds delay. Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: Tvrtko Ursulin Cc: Eero Tamminen Cc: "Rantala, Valtteri" Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 44 +++++++++++++++++++++++++++++++++++------ 1 file changed, 38 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 8ce363aa492c..b1c27da559e3 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1181,6 +1181,29 @@ static bool missed_irq(struct drm_i915_private *dev_priv, return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); } +static int __i915_spin_request(struct drm_i915_gem_request *rq) +{ + unsigned long timeout; + + if (i915_gem_request_get_ring(rq)->irq_refcount) + return -EBUSY; + + timeout = jiffies + 1; + while (!need_resched()) { + if (i915_gem_request_completed(rq, true)) + return 0; + + if (time_after_eq(jiffies, timeout)) + break; + + cpu_relax_lowlatency(); + } + if (i915_gem_request_completed(rq, false)) + return 0; + + return -EAGAIN; +} + /** * __i915_wait_request - wait until execution of request has finished * @req: duh! @@ -1225,12 +1248,20 @@ int __i915_wait_request(struct drm_i915_gem_request *req, if (INTEL_INFO(dev)->gen >= 6) gen6_rps_boost(dev_priv, file_priv); - if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) - return -ENODEV; - /* Record current time in case interrupted by signal, or wedged */ trace_i915_gem_request_wait_begin(req); before = ktime_get_raw_ns(); + + /* Optimistic spin for the next jiffie before touching IRQs */ + ret = __i915_spin_request(req); + if (ret == 0) + goto out; + + if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) { + ret = -ENODEV; + goto out; + } + for (;;) { struct timer_list timer; @@ -1279,14 +1310,15 @@ int __i915_wait_request(struct drm_i915_gem_request *req, destroy_timer_on_stack(&timer); } } - now = ktime_get_raw_ns(); - trace_i915_gem_request_wait_end(req); - if (!irq_test_in_progress) ring->irq_put(ring); finish_wait(&ring->irq_queue, &wait); +out: + now = ktime_get_raw_ns(); + trace_i915_gem_request_wait_end(req); + if (timeout) { s64 tres = *timeout - (now - before); -- cgit v1.2.3 From 30154650b8b58cd2633475d5a730b44baa140d98 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Apr 2015 17:28:24 +0100 Subject: drm/i915: Remove obj->pin_mappable The obj->pin_mappable flag only exists for debug purposes and is a hindrance that is mistreated with rotated GGTT views. For debug purposes, it suffices to mark objects with pin_display as being of note. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_gem.c | 6 +----- 3 files changed, 4 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index e890728144b4..5081e6f8a385 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -160,9 +160,9 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) } if (obj->stolen) seq_printf(m, " (stolen: %08llx)", obj->stolen->start); - if (obj->pin_mappable || obj->fault_mappable) { + if (obj->pin_display || obj->fault_mappable) { char s[3], *t = s; - if (obj->pin_mappable) + if (obj->pin_display) *t++ = 'p'; if (obj->fault_mappable) *t++ = 'f'; @@ -458,7 +458,7 @@ static int i915_gem_object_info(struct seq_file *m, void* data) size += i915_gem_obj_ggtt_size(obj); ++count; } - if (obj->pin_mappable) { + if (obj->pin_display) { mappable_size += i915_gem_obj_ggtt_size(obj); ++mappable_count; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6bdd1a6b395d..745dcd84849d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1963,7 +1963,6 @@ struct drm_i915_gem_object { * accurate mappable working set. */ unsigned int fault_mappable:1; - unsigned int pin_mappable:1; unsigned int pin_display:1; /* diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index b1c27da559e3..89d9ebe67520 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4255,9 +4255,6 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj, WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); vma->pin_count++; - if (flags & PIN_MAPPABLE) - obj->pin_mappable |= true; - return 0; } @@ -4295,8 +4292,7 @@ i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, WARN_ON(vma->pin_count == 0); WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); - if (--vma->pin_count == 0 && view->type == I915_GGTT_VIEW_NORMAL) - obj->pin_mappable = false; + --vma->pin_count; } bool -- cgit v1.2.3 From 9647ff36ae266b74c82780f7f4e3bb4a39506107 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Sun, 25 Jan 2015 13:27:11 -0800 Subject: drm/i915/gen9: fix PIPE_CONTROL flush for VS_INVALIDATE On GEN9+ per specification a NULL PIPE_CONTROL needs to be emitted before any PIPE_CONTROL command with the VS_INVALIDATE flag set. Signed-off-by: Imre Deak Reviewed-by: Nick Hoath Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_lrc.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index fcb074bd55dc..71aeeb35d091 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1262,6 +1262,7 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, { struct intel_engine_cs *ring = ringbuf->ring; u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; + bool vf_flush_wa; u32 flags = 0; int ret; @@ -1283,10 +1284,26 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; } - ret = intel_logical_ring_begin(ringbuf, ctx, 6); + /* + * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe + * control. + */ + vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 && + flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; + + ret = intel_logical_ring_begin(ringbuf, ctx, vf_flush_wa ? 12 : 6); if (ret) return ret; + if (vf_flush_wa) { + intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); + intel_logical_ring_emit(ringbuf, 0); + intel_logical_ring_emit(ringbuf, 0); + intel_logical_ring_emit(ringbuf, 0); + intel_logical_ring_emit(ringbuf, 0); + intel_logical_ring_emit(ringbuf, 0); + } + intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); intel_logical_ring_emit(ringbuf, flags); intel_logical_ring_emit(ringbuf, scratch_addr); -- cgit v1.2.3 From a82abe43cecb26619a7ce7e2052c3e89ed0b9436 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 27 Mar 2015 14:00:04 +0200 Subject: drm/i915/bxt: add bxt_init_clock_gating v2: - Make the condition to select between SKL and BXT consistent with the corresponding condition in init_workarounds_ring (Nick) Signed-off-by: Imre Deak Reviewed-by: Nick Hoath Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1e25e3e26a67..767a3e2ffdd1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -94,6 +94,11 @@ static void skl_init_clock_gating(struct drm_device *dev) GEN8_LQSC_RO_PERF_DIS); } +static void bxt_init_clock_gating(struct drm_device *dev) +{ + gen9_init_clock_gating(dev); +} + static void i915_pineview_get_mem_freq(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -6548,7 +6553,12 @@ void intel_init_pm(struct drm_device *dev) if (INTEL_INFO(dev)->gen >= 9) { skl_setup_wm_latency(dev); - dev_priv->display.init_clock_gating = skl_init_clock_gating; + if (IS_BROXTON(dev)) + dev_priv->display.init_clock_gating = + bxt_init_clock_gating; + else if (IS_SKYLAKE(dev)) + dev_priv->display.init_clock_gating = + skl_init_clock_gating; dev_priv->display.update_wm = skl_update_wm; dev_priv->display.update_sprite_wm = skl_update_sprite_wm; } else if (HAS_PCH_SPLIT(dev)) { -- cgit v1.2.3 From 32608ca255ef0da1a70239a731a1fcdbb212d3f2 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Wed, 11 Mar 2015 11:10:27 +0200 Subject: drm/i915/bxt: add GEN8_SDEUNIT_CLOCK_GATE_DISABLE workaround Signed-off-by: Imre Deak Reviewed-by: Nick Hoath Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 767a3e2ffdd1..a3247e83b072 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -96,7 +96,18 @@ static void skl_init_clock_gating(struct drm_device *dev) static void bxt_init_clock_gating(struct drm_device *dev) { + struct drm_i915_private *dev_priv = dev->dev_private; + gen9_init_clock_gating(dev); + + /* + * FIXME: + * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only. + */ + /* WaDisableSDEUnitClockGating:bxt */ + I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | + GEN8_SDEUNIT_CLOCK_GATE_DISABLE); + } static void i915_pineview_get_mem_freq(struct drm_device *dev) -- cgit v1.2.3 From 868434c51ec13c773e46c2398da18d53f6c78422 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Wed, 11 Mar 2015 10:49:32 +0200 Subject: drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaround Signed-off-by: Ben Widawsky Signed-off-by: Imre Deak Reviewed-by: Nick Hoath Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6c1ec72e94c4..fc3157999a08 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6104,6 +6104,7 @@ enum skl_disp_power_wells { #define GEN8_UCGCTL6 0x9430 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24) #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) +#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28) #define GEN6_GFXPAUSE 0xA000 #define GEN6_RPNSWREQ 0xA008 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a3247e83b072..07b3780677c9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -103,10 +103,12 @@ static void bxt_init_clock_gating(struct drm_device *dev) /* * FIXME: * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only. + * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. */ /* WaDisableSDEUnitClockGating:bxt */ I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | - GEN8_SDEUNIT_CLOCK_GATE_DISABLE); + GEN8_SDEUNIT_CLOCK_GATE_DISABLE | + GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); } -- cgit v1.2.3 From 38a39a7be77a097f7474986fe382cb1b56bf484e Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Wed, 11 Mar 2015 10:54:53 +0200 Subject: drm/i915/bxt: add WaDisableMaskBasedCammingInRCC workaround Signed-off-by: Ben Widawsky Signed-off-by: Imre Deak Reviewed-by: Nick Hoath Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++++++ 2 files changed, 13 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fc3157999a08..a22745855740 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5346,6 +5346,10 @@ enum skl_disp_power_wells { #define HDC_FORCE_NON_COHERENT (1<<4) #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10) +/* GEN9 chicken */ +#define SLICE_ECO_CHICKEN0 0x7308 +#define PIXEL_MASK_CAMMING_DISABLE (1 << 14) + /* WaCatErrorRejectionIssue */ #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index abe062a95be8..e23cbdc029b8 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -966,6 +966,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, GEN9_CCS_TLB_PREFETCH_ENABLE); + /* + * FIXME: don't apply the following on BXT for stepping C. On BXT A0 + * the flag reads back as 0. + */ + /* WaDisableMaskBasedCammingInRCC:bxtA */ + if (IS_BROXTON(dev)) + WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, + PIXEL_MASK_CAMMING_DISABLE); + return 0; } -- cgit v1.2.3 From 8d09c8123db62859886bbbc504a56ff5d9d9e8cd Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Wed, 11 Mar 2015 11:23:12 +0200 Subject: drm/i915/skl: add WaDisableMaskBasedCammingInRCC workaround Signed-off-by: Ben Widawsky Signed-off-by: Imre Deak Reviewed-by: Nick Hoath Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index e23cbdc029b8..000f608d8ea6 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -970,8 +970,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) * FIXME: don't apply the following on BXT for stepping C. On BXT A0 * the flag reads back as 0. */ - /* WaDisableMaskBasedCammingInRCC:bxtA */ - if (IS_BROXTON(dev)) + /* WaDisableMaskBasedCammingInRCC:sklC,bxtA */ + if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev)) WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, PIXEL_MASK_CAMMING_DISABLE); -- cgit v1.2.3 From e3a290553f3b09b657962e0a952fcf9b117bc08b Mon Sep 17 00:00:00 2001 From: Robert Beckett Date: Wed, 11 Mar 2015 10:28:25 +0200 Subject: drm/i915/bxt: add workaround to avoid PTE corruption Set TLBPF in TILECTL. This fixes an issue with BXT HW seeing corrupted pte entries. v2: - move the workaround to bxt_init_clock_gating (imre) Signed-off-by: Robert Beckett (v1) Signed-off-by: Imre Deak Reviewed-by: Nick Hoath Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 2 ++ 2 files changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a22745855740..21e69cab6efe 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1150,6 +1150,7 @@ enum skl_disp_power_wells { /* control register for cpu gtt access */ #define TILECTL 0x101000 #define TILECTL_SWZCTL (1 << 0) +#define TILECTL_TLBPF (1 << 1) #define TILECTL_TLB_PREFETCH_DIS (1 << 2) #define TILECTL_BACKSNOOP_DIS (1 << 3) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 07b3780677c9..472463806759 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -110,6 +110,8 @@ static void bxt_init_clock_gating(struct drm_device *dev) GEN8_SDEUNIT_CLOCK_GATE_DISABLE | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); + /* FIXME: apply on A0 only */ + I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); } static void i915_pineview_get_mem_freq(struct drm_device *dev) -- cgit v1.2.3 From c776eb2edfce88f0a44156b417cac3da11d1f944 Mon Sep 17 00:00:00 2001 From: Vandana Kannan Date: Tue, 19 Aug 2014 12:05:01 +0530 Subject: drm/i915/bxt: don't use unsupported port detection The port detection register flags in SFUSE_STRAP and DDI_BUF_CTL_A are not defined for BXT, so don't use them. Suggested by Satheesh. v2: - DDI_BUF_CTL_A bit 0 is not useful on BXT. Making changes to use this bit when simulator or BXT is not applicable. Code re-arranged as per Damien's suggestion. v3: - clarify commit message, add code comment (imre) Signed-off-by: Vandana Kannan (v2) Cc: M, Satheeshakrishna Cc: Lespiau, Damien Cc: Shankar, Uma Signed-off-by: Imre Deak Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 75955fee6d24..d35f40649247 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13011,7 +13011,16 @@ static void intel_setup_outputs(struct drm_device *dev) if (intel_crt_present(dev)) intel_crt_init(dev); - if (HAS_DDI(dev)) { + if (IS_BROXTON(dev)) { + /* + * FIXME: Broxton doesn't support port detection via the + * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to + * detect the ports. + */ + intel_ddi_init(dev, PORT_A); + intel_ddi_init(dev, PORT_B); + intel_ddi_init(dev, PORT_C); + } else if (HAS_DDI(dev)) { int found; /* -- cgit v1.2.3 From 4c27283415ec9e352d0d336ac45717d5e408ce3c Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 1 Apr 2015 10:58:05 +0300 Subject: drm/i915: add bxt gmbus support For BXT gmbus is pulled from PCH to CPU. From implementation point of view only pin pair configuration will change. The existing implementation supports all platforms previous to GEN8 and also SKL. But for BXT pin pair configuration is completely different than SKL or other previous GEN's. This patch introduces the new pin pair configuration structure specific to BXT and also ensures every real gmbus port has a gpio pin. v3 by Jani: with the platform independent prep work in place, the bxt enabling reduces to a fairly trivial patch. Credits are due Sunil for giving me the ideas (with his patches) what the platform independent parts should look like. v4: Fix intel_hdmi_init_connector() for bxt. Abstract gmbus_pin access more. s/GPU/PCH/ in commit message. v5: Rebase. Issue: VIZ-3574 Signed-off-by: A.Sunil Kamath Signed-off-by: Jani Nikula Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_hdmi.c | 14 +++++++++++--- drivers/gpu/drm/i915/intel_i2c.c | 30 +++++++++++++++++++++++++++--- 3 files changed, 41 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 87d9c0fbc7d9..9ef716a5093c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1794,6 +1794,9 @@ enum skl_disp_power_wells { #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ #define GMBUS_PIN_DPD 6 /* HDMID */ #define GMBUS_PIN_RESERVED 7 /* 7 reserved */ +#define GMBUS_PIN_1_BXT 1 +#define GMBUS_PIN_2_BXT 2 +#define GMBUS_PIN_3_BXT 3 #define GMBUS_NUM_PINS 7 /* including 0 */ #define GMBUS1 0x5104 /* command/status */ #define GMBUS_SW_CLR_INT (1<<31) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 02252d9a0cc3..7dfc3584b6b4 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1681,15 +1681,23 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, switch (port) { case PORT_B: - intel_hdmi->ddc_bus = GMBUS_PIN_DPB; + if (IS_BROXTON(dev_priv)) + intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; + else + intel_hdmi->ddc_bus = GMBUS_PIN_DPB; intel_encoder->hpd_pin = HPD_PORT_B; break; case PORT_C: - intel_hdmi->ddc_bus = GMBUS_PIN_DPC; + if (IS_BROXTON(dev_priv)) + intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; + else + intel_hdmi->ddc_bus = GMBUS_PIN_DPC; intel_encoder->hpd_pin = HPD_PORT_C; break; case PORT_D: - if (IS_CHERRYVIEW(dev)) + if (WARN_ON(IS_BROXTON(dev_priv))) + intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; + else if (IS_CHERRYVIEW(dev_priv)) intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; else intel_hdmi->ddc_bus = GMBUS_PIN_DPD; diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index ec9cc8cf642e..cadbc17d2775 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -49,10 +49,33 @@ static const struct gmbus_pin gmbus_pins[] = { [GMBUS_PIN_DPD] = { "dpd", GPIOF }, }; +static const struct gmbus_pin gmbus_pins_bxt[] = { + [GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB }, + [GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC }, + [GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD }, +}; + +/* pin is expected to be valid */ +static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, + unsigned int pin) +{ + if (IS_BROXTON(dev_priv)) + return &gmbus_pins_bxt[pin]; + else + return &gmbus_pins[pin]; +} + bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, unsigned int pin) { - return pin < ARRAY_SIZE(gmbus_pins) && gmbus_pins[pin].reg; + unsigned int size; + + if (IS_BROXTON(dev_priv)) + size = ARRAY_SIZE(gmbus_pins_bxt); + else + size = ARRAY_SIZE(gmbus_pins); + + return pin < size && get_gmbus_pin(dev_priv, pin)->reg; } /* Intel GPIO access functions */ @@ -196,7 +219,8 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) algo = &bus->bit_algo; - bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_pins[pin].reg; + bus->gpio_reg = dev_priv->gpio_mmio_base + + get_gmbus_pin(dev_priv, pin)->reg; bus->adapter.algo_data = algo; algo->setsda = set_data; @@ -550,7 +574,7 @@ int intel_setup_gmbus(struct drm_device *dev) snprintf(bus->adapter.name, sizeof(bus->adapter.name), "i915 gmbus %s", - gmbus_pins[pin].name); + get_gmbus_pin(dev_priv, pin)->name); bus->adapter.dev.parent = &dev->pdev->dev; bus->dev_priv = dev_priv; -- cgit v1.2.3 From e0a20ad78c06be27fe8afe53750b6eaf25da4ea6 Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Fri, 27 Mar 2015 14:54:14 +0200 Subject: drm/i915/bxt: DDI Hotplug interrupt setup In BXT, DDI hotplug control has been moved to CPU from PCH. This patch adds a new IRQ setup function for BXT which: 1. Checks which HPD ports are requested to be enabled by encoders. 2. Enables those ports in the hot plug control register. 3. Un-masks these port interrupts in the IMR register. 4. Enables these port interrupts in the IER register. V3: Kept the default HPD filter count to default (500 us) as per satheesh's comment v4: Remove unused HPD filter defines (Damien) v5: warn if trying to setup HPD on port A (imre) v6: fix order of definitions for register bitfields (Daniel) v7: (jani) - define the size of the hpd_bxt array explicitly for bound checking - use for_each_intel_encoder instead of open coding it - fix format/order of definitions for BXT_HOTPLUG_CTL reg bitfields Reviewed-by: Satheeshakrishna M Signed-off-by: Damien Lespiau Signed-off-by: Shashank Sharma (v4) Signed-off-by: Imre Deak Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 47 ++++++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++- 2 files changed, 68 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 46bcbff89760..631484dd0b60 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -88,6 +88,12 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are th [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS }; +/* BXT hpd list */ +static const u32 hpd_bxt[HPD_NUM_PINS] = { + [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, + [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC +}; + /* IIR can theoretically queue up two events. Be paranoid. */ #define GEN8_IRQ_RESET_NDX(type, which) do { \ I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ @@ -3159,6 +3165,42 @@ static void ibx_hpd_irq_setup(struct drm_device *dev) I915_WRITE(PCH_PORT_HOTPLUG, hotplug); } +static void bxt_hpd_irq_setup(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_encoder *intel_encoder; + u32 hotplug_port = 0; + u32 hotplug_ctrl; + + /* Now, enable HPD */ + for_each_intel_encoder(dev, intel_encoder) { + if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark + == HPD_ENABLED) + hotplug_port |= hpd_bxt[intel_encoder->hpd_pin]; + } + + /* Mask all HPD control bits */ + hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK; + + /* Enable requested port in hotplug control */ + /* TODO: implement (short) HPD support on port A */ + WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA); + if (hotplug_port & BXT_DE_PORT_HP_DDIB) + hotplug_ctrl |= BXT_DDIB_HPD_ENABLE; + if (hotplug_port & BXT_DE_PORT_HP_DDIC) + hotplug_ctrl |= BXT_DDIC_HPD_ENABLE; + I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl); + + /* Unmask DDI hotplug in IMR */ + hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port; + I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl); + + /* Enable DDI hotplug in IER */ + hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port; + I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl); + POSTING_READ(GEN8_DE_PORT_IER); +} + static void ibx_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4279,7 +4321,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev->driver->irq_uninstall = gen8_irq_uninstall; dev->driver->enable_vblank = gen8_enable_vblank; dev->driver->disable_vblank = gen8_disable_vblank; - dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; + if (HAS_PCH_SPLIT(dev)) + dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; + else + dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; } else if (HAS_PCH_SPLIT(dev)) { dev->driver->irq_handler = ironlake_irq_handler; dev->driver->irq_preinstall = ironlake_irq_reset; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9ef716a5093c..ccdbd25b78a6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5373,10 +5373,16 @@ enum skl_disp_power_wells { #define GEN8_DE_PORT_IMR 0x44444 #define GEN8_DE_PORT_IIR 0x44448 #define GEN8_DE_PORT_IER 0x4444c -#define GEN8_PORT_DP_A_HOTPLUG (1 << 3) #define GEN9_AUX_CHANNEL_D (1 << 27) #define GEN9_AUX_CHANNEL_C (1 << 26) #define GEN9_AUX_CHANNEL_B (1 << 25) +#define BXT_DE_PORT_HP_DDIC (1 << 5) +#define BXT_DE_PORT_HP_DDIB (1 << 4) +#define BXT_DE_PORT_HP_DDIA (1 << 3) +#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ + BXT_DE_PORT_HP_DDIB | \ + BXT_DE_PORT_HP_DDIC) +#define GEN8_PORT_DP_A_HOTPLUG (1 << 3) #define GEN8_AUX_CHANNEL_A (1 << 0) #define GEN8_DE_MISC_ISR 0x44460 @@ -5390,6 +5396,21 @@ enum skl_disp_power_wells { #define GEN8_PCU_IIR 0x444e8 #define GEN8_PCU_IER 0x444ec +/* BXT hotplug control */ +#define BXT_HOTPLUG_CTL 0xC4030 +#define BXT_DDIA_HPD_ENABLE (1 << 28) +#define BXT_DDIA_HPD_STATUS (3 << 24) +#define BXT_DDIC_HPD_ENABLE (1 << 12) +#define BXT_DDIC_HPD_STATUS (3 << 8) +#define BXT_DDIB_HPD_ENABLE (1 << 4) +#define BXT_DDIB_HPD_STATUS (3 << 0) +#define BXT_HOTPLUG_CTL_MASK (BXT_DDIA_HPD_ENABLE | \ + BXT_DDIB_HPD_ENABLE | \ + BXT_DDIC_HPD_ENABLE) +#define BXT_HPD_STATUS_MASK (BXT_DDIA_HPD_STATUS | \ + BXT_DDIB_HPD_STATUS | \ + BXT_DDIC_HPD_STATUS) + #define ILK_DISPLAY_CHICKEN2 0x42004 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ #define ILK_ELPIN_409_SELECT (1 << 25) -- cgit v1.2.3 From 6b5ad42f0a54e522e99734ad5fdbb7fe983277d2 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 27 Mar 2015 17:22:34 +0200 Subject: drm/i915/bxt: support for HPD long/short status decoding All non-GMCH platforms have the same register layout for HPD long/short status, so let's use this condition instead of HAS_PCH_SPLIT, as the latter doesn't apply for BXT. Noticed by Daniel. Signed-off-by: Imre Deak Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 631484dd0b60..7f73f71741ae 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1428,7 +1428,7 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev, if (port && dev_priv->hpd_irq_port[port]) { bool long_hpd; - if (HAS_PCH_SPLIT(dev)) { + if (!HAS_GMCH_DISPLAY(dev_priv)) { dig_shift = pch_port_to_hotplug_shift(port); long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT; } else { -- cgit v1.2.3 From d04a492dd574bba43a558612ddd49fa593a387fe Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Fri, 22 Aug 2014 17:40:41 +0530 Subject: drm/i915/bxt: Add DDI hpd handler This patch adds a hot plug interrupt handler function for BXT. What this function typically does is: 1. Check if hot plug is enabled from hot plug control register. 2. Call hpd_irq_handler with appropriate trigger to detect a plug storm and schedule a bottom half. 3. Clear sticky status bits in hot plug control register.. v2: (jani) - drop redundant unlikely() - s/Todo/FIXME:/ in code comment - declare 'found' var in the scope where it's used - check for IS_BROXTON before handling BXT_DE_PORT_HOTPLUG_MASK Reviewed-by: Satheeshakrishna M Signed-off-by: Damien Lespiau Signed-off-by: Shashank Sharma (v1) Signed-off-by: Imre Deak Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 46 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7f73f71741ae..ac68b5bd8f15 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2152,6 +2152,38 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) return ret; } +static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t hp_control; + uint32_t hp_trigger; + + /* Get the status */ + hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK; + hp_control = I915_READ(BXT_HOTPLUG_CTL); + + /* Hotplug not enabled ? */ + if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) { + DRM_ERROR("Interrupt when HPD disabled\n"); + return; + } + + DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", + hp_control & BXT_HOTPLUG_CTL_MASK); + + /* Check for HPD storm and schedule bottom half */ + intel_hpd_irq_handler(dev, hp_trigger, hp_control, hpd_bxt); + + /* + * FIXME: Save the hot plug status for bottom half before + * clearing the sticky status bits, else the status will be + * lost. + */ + + /* Clear sticky bits in hpd status */ + I915_WRITE(BXT_HOTPLUG_CTL, hp_control); +} + static irqreturn_t gen8_irq_handler(int irq, void *arg) { struct drm_device *dev = arg; @@ -2197,12 +2229,22 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg) if (master_ctl & GEN8_DE_PORT_IRQ) { tmp = I915_READ(GEN8_DE_PORT_IIR); if (tmp) { + bool found = false; + I915_WRITE(GEN8_DE_PORT_IIR, tmp); ret = IRQ_HANDLED; - if (tmp & aux_mask) + if (tmp & aux_mask) { dp_aux_irq_handler(dev); - else + found = true; + } + + if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) { + bxt_hpd_handler(dev, tmp); + found = true; + } + + if (!found) DRM_ERROR("Unexpected DE Port interrupt\n"); } else -- cgit v1.2.3 From 266ea3d9c4f69a4d97533128aba494f7d8b52459 Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Fri, 22 Aug 2014 17:40:42 +0530 Subject: drm/i915/bxt: Add BXT support in gen8_irq functions This patch adds conditional checks in gen8_irq functions to support BXT. Most of the checks just look for PCH split availability, and block the call to PCH interrupt functions if not available. v2: (jani) - drop redundant TODO comment about PCH IRQ flags on BXT - check HAS_PCH_SPLIT instead of IS_BROXTON when handling PCH specific IRQ events in gen8_irq_handler() - check HAS_PCH_SPLIT before calling the function instead of a corresponding early return within the called function for ibx_irq_reset(), ibx_irq_pre_postinstall(), ibx_irq_postinstall() v3: (jani) - in ironlake_irq_postinstall() and ironlake_irq_reset() HAS_PCH_SPLIT is always true, so drop the check for it Reviewed-by: Satheeshakrishna M Signed-off-by: Damien Lespiau Signed-off-by: Shashank Sharma (v1) Signed-off-by: Imre Deak Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index ac68b5bd8f15..17a8f8c61753 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2297,7 +2297,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg) DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); } - if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { + if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) && + master_ctl & GEN8_DE_PCH_IRQ) { /* * FIXME(BDW): Assume for now that the new interrupt handling * scheme also closed the SDE interrupt handling race we've seen @@ -3133,7 +3134,8 @@ static void gen8_irq_reset(struct drm_device *dev) GEN5_IRQ_RESET(GEN8_DE_MISC_); GEN5_IRQ_RESET(GEN8_PCU_); - ibx_irq_reset(dev); + if (HAS_PCH_SPLIT(dev)) + ibx_irq_reset(dev); } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, @@ -3545,12 +3547,14 @@ static int gen8_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - ibx_irq_pre_postinstall(dev); + if (HAS_PCH_SPLIT(dev)) + ibx_irq_pre_postinstall(dev); gen8_gt_irq_postinstall(dev_priv); gen8_de_irq_postinstall(dev_priv); - ibx_irq_postinstall(dev); + if (HAS_PCH_SPLIT(dev)) + ibx_irq_postinstall(dev); I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); POSTING_READ(GEN8_MASTER_IRQ); -- cgit v1.2.3 From 9e63743ebbcb138be83453f7dcf65f817893f851 Mon Sep 17 00:00:00 2001 From: Shashank Sharma Date: Fri, 22 Aug 2014 17:40:43 +0530 Subject: drm/i915/bxt: Enable GMBUS IRQ GMBUS interrupt has been moved to CPU side in BXT. What this patch does is: 1. Enable GMBUS IRQ in de_post_install function 2. Handle this interrupt as a port interrupt in display irq handler v2: Rebase on top of the for_each_pipe() change adding dev_priv as first argument (Damien). v3: read BXT_DE_PORT_GMBUS IIR flag only on BXT on other platforms it's reserved (imre) v4: (jani) - remove redundant 'BXT GMBUS' comment - fix formatting of BXT_DE_PORT_GMBUS definition Reviewed-by: Satheeshakrishna M Signed-off-by: Damien Lespiau Signed-off-by: Shashank Sharma (v1) Signed-off-by: Imre Deak Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 14 +++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 12 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 17a8f8c61753..f776584ce363 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2244,6 +2244,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg) found = true; } + if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) { + gmbus_irq_handler(dev); + found = true; + } + if (!found) DRM_ERROR("Unexpected DE Port interrupt\n"); } @@ -3515,13 +3520,16 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; uint32_t de_pipe_enables; int pipe; - u32 aux_en = GEN8_AUX_CHANNEL_A; + u32 de_port_en = GEN8_AUX_CHANNEL_A; if (IS_GEN9(dev_priv)) { de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; - aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | + de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D; + + if (IS_BROXTON(dev_priv)) + de_port_en |= BXT_DE_PORT_GMBUS; } else de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; @@ -3540,7 +3548,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv->de_irq_mask[pipe], de_pipe_enables); - GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en); + GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en); } static int gen8_irq_postinstall(struct drm_device *dev) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ccdbd25b78a6..4b53b2083c78 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5383,6 +5383,7 @@ enum skl_disp_power_wells { BXT_DE_PORT_HP_DDIB | \ BXT_DE_PORT_HP_DDIC) #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) +#define BXT_DE_PORT_GMBUS (1 << 1) #define GEN8_AUX_CHANNEL_A (1 << 0) #define GEN8_DE_MISC_ISR 0x44460 -- cgit v1.2.3 From 0b4a2a36d078b3a8de871025a958da547a6143f7 Mon Sep 17 00:00:00 2001 From: Satheeshakrishna M Date: Fri, 11 Jul 2014 14:51:13 +0530 Subject: drm/i915/bxt: Define BXT power domains MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add BXT power domains v2: Use DOMAIN_PLLS instead of a new CDCLK one, whitespace fixes (Damien) v3: add VGA, TRANSCODER_A power domains (imre) Signed-off-by: Satheeshakrishna M (v1) Signed-off-by: Damien Lespiau Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 55 +++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index ce00e6994eeb..ff5cce32c7d6 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -319,6 +319,38 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \ BIT(POWER_DOMAIN_INIT)) +#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT(POWER_DOMAIN_TRANSCODER_A) | \ + BIT(POWER_DOMAIN_PIPE_B) | \ + BIT(POWER_DOMAIN_TRANSCODER_B) | \ + BIT(POWER_DOMAIN_PIPE_C) | \ + BIT(POWER_DOMAIN_TRANSCODER_C) | \ + BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ + BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ + BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ + BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ + BIT(POWER_DOMAIN_AUX_B) | \ + BIT(POWER_DOMAIN_AUX_C) | \ + BIT(POWER_DOMAIN_AUDIO) | \ + BIT(POWER_DOMAIN_VGA) | \ + BIT(POWER_DOMAIN_INIT)) +#define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT(POWER_DOMAIN_PIPE_A) | \ + BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ + BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ + BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ + BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ + BIT(POWER_DOMAIN_AUX_A) | \ + BIT(POWER_DOMAIN_PLLS) | \ + BIT(POWER_DOMAIN_INIT)) +#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ + (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ + BIT(POWER_DOMAIN_INIT)) + static void skl_set_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { @@ -1313,6 +1345,27 @@ static struct i915_power_well skl_power_wells[] = { }, }; +static struct i915_power_well bxt_power_wells[] = { + { + .name = "always-on", + .always_on = 1, + .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, + .ops = &i9xx_always_on_power_well_ops, + }, + { + .name = "power well 1", + .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, + .ops = &skl_power_well_ops, + .data = SKL_DISP_PW_1, + }, + { + .name = "power well 2", + .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, + .ops = &skl_power_well_ops, + .data = SKL_DISP_PW_2, + } +}; + #define set_power_wells(power_domains, __power_wells) ({ \ (power_domains)->power_wells = (__power_wells); \ (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ @@ -1341,6 +1394,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) set_power_wells(power_domains, bdw_power_wells); } else if (IS_SKYLAKE(dev_priv->dev)) { set_power_wells(power_domains, skl_power_wells); + } else if (IS_BROXTON(dev_priv->dev)) { + set_power_wells(power_domains, bxt_power_wells); } else if (IS_CHERRYVIEW(dev_priv->dev)) { set_power_wells(power_domains, chv_power_wells); } else if (IS_VALLEYVIEW(dev_priv->dev)) { -- cgit v1.2.3 From cff5190cb989f130afa18b96cd33745b733ffae9 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Fri, 10 Apr 2015 11:15:07 -0700 Subject: drm/i915: PSR: Remove wrong LINK_DISABLE. This wrong logic and useless define came from first versions and came along with all rework. Just now I notice how ugly, wrong and useless this is. val is already defined as 0 anyway and logic is completelly wrong and useless. So let's starting the link_standby fix with this cleaning. Signed-off-by: Rodrigo Vivi Reviewed-by: Durgadoss R Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 1 - drivers/gpu/drm/i915/intel_psr.c | 3 +-- 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4b53b2083c78..077cb90b0822 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2688,7 +2688,6 @@ enum skl_disp_power_wells { #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) #define EDP_PSR_ENABLE (1<<31) #define BDW_PSR_SINGLE_FRAME (1<<30) -#define EDP_PSR_LINK_DISABLE (0<<27) #define EDP_PSR_LINK_STANDBY (1<<27) #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 27608ce19b1c..db95b392bcd4 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -269,8 +269,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) val |= EDP_PSR_TP2_TP3_TIME_0us; val |= EDP_PSR_TP1_TIME_0us; val |= EDP_PSR_SKIP_AUX_EXIT; - } else - val |= EDP_PSR_LINK_DISABLE; + } I915_WRITE(EDP_PSR_CTL(dev), val | (IS_BROADWELL(dev) ? 0 : link_entry_time) | -- cgit v1.2.3 From 3301d4092106ff07e14d7acbf12243d782600930 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Fri, 10 Apr 2015 11:15:08 -0700 Subject: drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic Since the beginning there is a missunderstanding on the meaning of this dpcd bit. This bit shouldn't indicate whether to use link standby or not, but just be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped since HW is the responsible one. Even with help of frontbuffer tracking, HW is still fully responsible for PSR exit logic with/without DP training. DP_PSR_NO_TRAIN_ON_EXIT means the source doesn't need to do the training, but it doesn't tell to avoid TP patterns, so we will send minimal TP1 and avoid TP2. It also means that sink itself can take up to 5 idle frames for training. 6 in our case since we might be off by 1. So we also increment idle_frames by 4 here. v2: Fix and improve commit message (Durga). v3: Use minimal TP1 time avoiding TP2 and increase idle frame. Cc: Durgadoss R Cc: Arthur Runyan Signed-off-by: Rodrigo Vivi Reviewed-by: Durgadoss R Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_psr.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index db95b392bcd4..0e3b652b5946 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -264,11 +264,17 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) uint32_t val = 0x0; const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; - if (dev_priv->psr.link_standby) { + if (dev_priv->psr.link_standby) val |= EDP_PSR_LINK_STANDBY; + + if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { + /* It doesn't mean we shouldn't send TPS patters, so let's + send the minimal TP1 possible and skip TP2. */ + val |= EDP_PSR_TP1_TIME_100us; val |= EDP_PSR_TP2_TP3_TIME_0us; - val |= EDP_PSR_TP1_TIME_0us; val |= EDP_PSR_SKIP_AUX_EXIT; + /* Sink should be able to train with the 5 or 6 idle patterns */ + idle_frames += 4; } I915_WRITE(EDP_PSR_CTL(dev), val | @@ -381,8 +387,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) /* First we check VBT, but we must respect sink and source * known restrictions */ dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; - if ((intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) || - (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A)) + if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A) dev_priv->psr.link_standby = true; dev_priv->psr.busy_frontbuffer_bits = 0; -- cgit v1.2.3 From 89251b177b588adf5e62df42d51017d24047f44b Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Fri, 10 Apr 2015 11:15:09 -0700 Subject: drm/i915: PSR: deprecate link_standby support for core platforms. On Haswell and Broadwell with link in standby when exit event happens between vblank and VSC packet, PSR exit on panel but DPA transmitter still sends black pixel. When this condition hits, panel will intermittently display black frame. The known W/A for this case involve the of single_frame update that isn't supported on Haswell and to be supported on Broadwell 3 other workarounds would be required. So it is better and safe to just deprecate link_standby for now. Also, link fully off saves more power than link_standby and afwk no OEM is requesting link standby on VBT. There is no reason for that. For Skylake let's just consider it behaves like Broadwell until we prove otherwise. v2: Fix commit message (Durga). v3: Fix conflict with PSR2. Reference: HSD: bdwgfx/1912559 Signed-off-by: Rodrigo Vivi Reviewed-by: Durgadoss R Signed-off-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 3 --- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/intel_psr.c | 26 ++++++++++---------------- 3 files changed, 10 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 23949247cf10..07a71c0ff775 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2358,9 +2358,6 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) } seq_puts(m, "\n"); - seq_printf(m, "Link standby: %s\n", - yesno((bool)dev_priv->psr.link_standby)); - /* CHV PSR has no kind of performance counter */ if (HAS_DDI(dev)) { psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3b2124930058..37e74543ca16 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -881,7 +881,6 @@ struct i915_psr { bool active; struct delayed_work work; unsigned busy_frontbuffer_bits; - bool link_standby; bool psr2_support; bool aux_frame_sync; }; diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 0e3b652b5946..5cd374b4a07e 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -170,13 +170,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); - /* Enable PSR in sink */ - if (dev_priv->psr.link_standby) - drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, - DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); - else - drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, - DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, + DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); /* Enable AUX frame sync at sink */ if (dev_priv->psr.aux_frame_sync) @@ -214,6 +209,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); } + + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE); } static void vlv_psr_enable_source(struct intel_dp *intel_dp) @@ -264,9 +261,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) uint32_t val = 0x0; const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; - if (dev_priv->psr.link_standby) - val |= EDP_PSR_LINK_STANDBY; - if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { /* It doesn't mean we shouldn't send TPS patters, so let's send the minimal TP1 possible and skip TP2. */ @@ -325,6 +319,12 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp) return false; } + if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) || + (dig_port->port != PORT_A))) { + DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n"); + return false; + } + dev_priv->psr.source_ok = true; return true; } @@ -384,12 +384,6 @@ void intel_psr_enable(struct intel_dp *intel_dp) if (!intel_psr_match_conditions(intel_dp)) goto unlock; - /* First we check VBT, but we must respect sink and source - * known restrictions */ - dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; - if (IS_BROADWELL(dev) && intel_dig_port->port != PORT_A) - dev_priv->psr.link_standby = true; - dev_priv->psr.busy_frontbuffer_bits = 0; if (HAS_DDI(dev)) { -- cgit v1.2.3 From c7240c3bc5d6610b42dbb10fda71bbbf1dad5515 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Fri, 10 Apr 2015 11:15:10 -0700 Subject: drm/i915: PSR VLV: Add single frame update. According to spec: "In PSR HW or SW mode, SW set this bit before writing registers for a flip. It will be self-clear when it gets to the PSR active state." Some versions of spec mention that this is needed when in "Persistent mode" but define it as same as "SW mode". Since this fix the page flip case let's assume this is exactly what we need. Cc: Dhinakaran Pandiyan Signed-off-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_frontbuffer.c | 2 ++ drivers/gpu/drm/i915/intel_psr.c | 42 ++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 6a2ee0c38161..082be7161203 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1294,6 +1294,7 @@ void intel_psr_invalidate(struct drm_device *dev, void intel_psr_flush(struct drm_device *dev, unsigned frontbuffer_bits); void intel_psr_init(struct drm_device *dev); +void intel_psr_single_frame_update(struct drm_device *dev); /* intel_runtime_pm.c */ int intel_power_domains_init(struct drm_i915_private *); diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c b/drivers/gpu/drm/i915/intel_frontbuffer.c index a20cffb78c0f..57095f54c1f2 100644 --- a/drivers/gpu/drm/i915/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/intel_frontbuffer.c @@ -243,6 +243,8 @@ void intel_frontbuffer_flip_prepare(struct drm_device *dev, /* Remove stale busy bits due to the old buffer. */ dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits; mutex_unlock(&dev_priv->fb_tracking.lock); + + intel_psr_single_frame_update(dev); } /** diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 5cd374b4a07e..5ee0fa57ed19 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -593,6 +593,48 @@ static void intel_psr_exit(struct drm_device *dev) dev_priv->psr.active = false; } +/** + * intel_psr_single_frame_update - Single Frame Update + * @dev: DRM device + * + * Some platforms support a single frame update feature that is used to + * send and update only one frame on Remote Frame Buffer. + * So far it is only implemented for Valleyview and Cherryview because + * hardware requires this to be done before a page flip. + */ +void intel_psr_single_frame_update(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_crtc *crtc; + enum pipe pipe; + u32 val; + + /* + * Single frame update is already supported on BDW+ but it requires + * many W/A and it isn't really needed. + */ + if (!IS_VALLEYVIEW(dev)) + return; + + mutex_lock(&dev_priv->psr.lock); + if (!dev_priv->psr.enabled) { + mutex_unlock(&dev_priv->psr.lock); + return; + } + + crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; + pipe = to_intel_crtc(crtc)->pipe; + val = I915_READ(VLV_PSRCTL(pipe)); + + /* + * We need to set this bit before writing registers for a flip. + * This bit will be self-clear when it gets to the PSR active state. + */ + I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE); + + mutex_unlock(&dev_priv->psr.lock); +} + /** * intel_psr_invalidate - Invalidade PSR * @dev: DRM device -- cgit v1.2.3 From 164dfd2877249e7a768326256ffe0c78026a2863 Mon Sep 17 00:00:00 2001 From: Vandana Kannan Date: Mon, 24 Nov 2014 13:37:41 +0530 Subject: drm/i915: Rename vlv_cdclk_freq to cdclk_freq MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename vlv_cdclk_freq to cdclk_freq so that it can be used for all platforms as required. Needed by the next patch. Signed-off-by: Vandana Kannan Signed-off-by: A.Sunil Kamath Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++-------- 2 files changed, 11 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 37e74543ca16..2645ba35b130 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1656,7 +1656,7 @@ struct drm_i915_private { int num_fence_regs; /* 8 on pre-965, 16 otherwise */ unsigned int fsb_freq, mem_freq, is_ddr3; - unsigned int vlv_cdclk_freq; + unsigned int cdclk_freq; unsigned int hpll_freq; /** diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9f72d9a76a38..bb5f2a570a1d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5214,16 +5214,16 @@ static void vlv_update_cdclk(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); + dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", - dev_priv->vlv_cdclk_freq); + dev_priv->cdclk_freq); /* * Program the gmbus_freq based on the cdclk frequency. * BSpec erroneously claims we should aim for 4MHz, but * in fact 1MHz is the correct frequency. */ - I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); + I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); } /* Adjust CDclk dividers to allow high res or save power if possible */ @@ -5232,7 +5232,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) struct drm_i915_private *dev_priv = dev->dev_private; u32 val, cmd; - WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); + WARN_ON(dev_priv->display.get_display_clock_speed(dev) + != dev_priv->cdclk_freq); if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ cmd = 2; @@ -5296,7 +5297,8 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) struct drm_i915_private *dev_priv = dev->dev_private; u32 val, cmd; - WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); + WARN_ON(dev_priv->display.get_display_clock_speed(dev) + != dev_priv->cdclk_freq); switch (cdclk) { case 333333: @@ -5395,7 +5397,7 @@ static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, return max_pixclk; if (valleyview_calc_cdclk(dev_priv, max_pixclk) == - dev_priv->vlv_cdclk_freq) + dev_priv->cdclk_freq) return 0; /* disable/enable all currently active pipes while we change cdclk */ @@ -5415,7 +5417,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) else default_credits = PFI_CREDIT(8); - if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { + if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { /* CHV suggested value is 31 or 63 */ if (IS_CHERRYVIEW(dev_priv)) credits = PFI_CREDIT_31; @@ -5459,7 +5461,7 @@ static void valleyview_modeset_global_resources(struct drm_atomic_state *state) req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); - if (req_cdclk != dev_priv->vlv_cdclk_freq) { + if (req_cdclk != dev_priv->cdclk_freq) { /* * FIXME: We can end up here with all power domains off, yet * with a CDCLK frequency other than the minimum. To account -- cgit v1.2.3 From f8437dd1b5a5a084302ba8e9fa29f76cdfc2f945 Mon Sep 17 00:00:00 2001 From: Vandana Kannan Date: Mon, 24 Nov 2014 13:37:39 +0530 Subject: drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add CDCLK specific display clock initialization sequence as per BSpec. Note that the CDCLK initialization/uninitialization are done at their current place only for simplicity, in a future patch - when more of the runtime PM features will be enabled - these will be moved to power well#1 and modeset encoder enabling/disabling hooks respectively. This also means that atm dynamic power gating power well #1 is effectively disabled. The call to uninitialize CDCLK during system/runtime suspend will be added later in this patchset. v1: Added function definitions in header files v2: Imre's review comments addressed - Moved CDCLK related definitions to i915_reg.h - Removed defintions for CDCLK frequency - Split uninit_cdclk() by adding a phy_uninit function - Calculate freq and decimal based on input frequency - Program SSA precharge based on input frequency - Use wait_for 1ms instead 200us udelay for DE PLL locking - Removed initial value for divider, freq, decimal, ratio. - Replaced polling loops with wait_for - Parameterized latency optim setting - Fix the parts where DE PLL has to be disabled. - Call CDCLK selection from mode set v3: (imre) - add note about the plan to move the cdclk/phy init to a better place - take rps.hw_lock around pcode access - move DE PLL register macros here from another patch since they are used here first - add BXT_ prefix to CDCLK flags - add missing masking when programming CDCLK_FREQ_DECIMAL v4: (ville) - split the CDCLK/PHY parts into two patches, update commit message accordingly - s/DISPLAY_PCU_CONTROL/HSW_PCODE_DE_WRITE_FREQ_REQ/ - simplify BXT_DE_PLL_RATIO macros - fix BXT_DE_PLL_RATIO_MASK - s/bxt_select_cdclk_freq/broxton_set_cdclk_freq/ - move cdclk init/uninit/set code from intel_ddi.c to intel_display.c - remove redundant code comments for broxton_set_cdclk_freq() - sanitize fixed point<->integer frequency value conversion - use DRM_ERROR instead of WARN - do RMW when programming BXT_DE_PLL_CTL for safety - add note about PLL lock timeout being exactly 200us - make PCU error messages more descriptive - instead of using 0 freq to mean PLL off/bypass freq use 19200 for clarity, as the latter one is the actual rate - simplify pcode programming, removing duplicated sandybridge_pcode_write() call - sanitize code flow, remove unnecessary scratch vars in broxton_set_cdclk() (imre) - Remove bound check for maxmimum freq to match current code. This check will be added later at a more proper platform independent place once atomic support lands. - add note to remove freq guard band which isn't needed on BXT - add note to reduce freq to minimum if no pipe is enabled - combine broxton_modeset_global_pipes() with valleyview_modeset_global_pipes() Signed-off-by: Vandana Kannan (v2) Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 20 ++++ drivers/gpu/drm/i915/intel_ddi.c | 2 + drivers/gpu/drm/i915/intel_display.c | 226 ++++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_drv.h | 3 + 4 files changed, 248 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 077cb90b0822..164350cf760c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5451,6 +5451,9 @@ enum skl_disp_power_wells { #define DISP_FBC_WM_DIS (1<<15) #define DISP_ARB_CTL2 0x45004 #define DISP_DATA_PARTITION_5_6 (1<<6) +#define DBUF_CTL 0x45008 +#define DBUF_POWER_REQUEST (1<<31) +#define DBUF_POWER_STATE (1<<30) #define GEN7_MSG_CTL 0x45010 #define WAIT_FOR_PCH_RESET_ACK (1<<1) #define WAIT_FOR_PCH_FLR_ACK (1<<0) @@ -6402,6 +6405,7 @@ enum skl_disp_power_wells { #define GEN6_PCODE_WRITE_D_COMP 0x11 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) +#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 #define DISPLAY_IPS_CONTROL 0x19 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A #define GEN6_PCODE_DATA 0x138128 @@ -6873,6 +6877,13 @@ enum skl_disp_power_wells { #define CDCLK_FREQ_675_617 (3<<26) #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) +#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22) +#define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22) +#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22) +#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22) +#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) +#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) + /* LCPLL_CTL */ #define LCPLL1_CTL 0x46010 #define LCPLL2_CTL 0x46014 @@ -6937,6 +6948,15 @@ enum skl_disp_power_wells { #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8) #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8) +/* BXT display engine PLL */ +#define BXT_DE_PLL_CTL 0x6d000 +#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ +#define BXT_DE_PLL_RATIO_MASK 0xff + +#define BXT_DE_PLL_ENABLE 0x46070 +#define BXT_DE_PLL_PLL_ENABLE (1 << 31) +#define BXT_DE_PLL_LOCK (1 << 30) + /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, * since on HSW we can't write to it using I915_WRITE. */ #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 5b5048437115..25d697b9d3d9 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1880,6 +1880,8 @@ void intel_ddi_pll_init(struct drm_device *dev) if (IS_SKYLAKE(dev)) { if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) DRM_ERROR("LCPLL1 is disabled\n"); + } else if (IS_BROXTON(dev)) { + broxton_init_cdclk(dev); } else { /* * The LCPLL register should be turned on by the BIOS. For now diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bb5f2a570a1d..5ee5d8cd9cd1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5196,6 +5196,181 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) intel_display_set_init_power(dev_priv, false); } +void broxton_set_cdclk(struct drm_device *dev, int frequency) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t divider; + uint32_t ratio; + uint32_t current_freq; + int ret; + + /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ + switch (frequency) { + case 144000: + divider = BXT_CDCLK_CD2X_DIV_SEL_4; + ratio = BXT_DE_PLL_RATIO(60); + break; + case 288000: + divider = BXT_CDCLK_CD2X_DIV_SEL_2; + ratio = BXT_DE_PLL_RATIO(60); + break; + case 384000: + divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; + ratio = BXT_DE_PLL_RATIO(60); + break; + case 576000: + divider = BXT_CDCLK_CD2X_DIV_SEL_1; + ratio = BXT_DE_PLL_RATIO(60); + break; + case 624000: + divider = BXT_CDCLK_CD2X_DIV_SEL_1; + ratio = BXT_DE_PLL_RATIO(65); + break; + case 19200: + /* + * Bypass frequency with DE PLL disabled. Init ratio, divider + * to suppress GCC warning. + */ + ratio = 0; + divider = 0; + break; + default: + DRM_ERROR("unsupported CDCLK freq %d", frequency); + + return; + } + + mutex_lock(&dev_priv->rps.hw_lock); + /* Inform power controller of upcoming frequency change */ + ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, + 0x80000000); + mutex_unlock(&dev_priv->rps.hw_lock); + + if (ret) { + DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", + ret, frequency); + return; + } + + current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; + /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ + current_freq = current_freq * 500 + 1000; + + /* + * DE PLL has to be disabled when + * - setting to 19.2MHz (bypass, PLL isn't used) + * - before setting to 624MHz (PLL needs toggling) + * - before setting to any frequency from 624MHz (PLL needs toggling) + */ + if (frequency == 19200 || frequency == 624000 || + current_freq == 624000) { + I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); + /* Timeout 200us */ + if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), + 1)) + DRM_ERROR("timout waiting for DE PLL unlock\n"); + } + + if (frequency != 19200) { + uint32_t val; + + val = I915_READ(BXT_DE_PLL_CTL); + val &= ~BXT_DE_PLL_RATIO_MASK; + val |= ratio; + I915_WRITE(BXT_DE_PLL_CTL, val); + + I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); + /* Timeout 200us */ + if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) + DRM_ERROR("timeout waiting for DE PLL lock\n"); + + val = I915_READ(CDCLK_CTL); + val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; + val |= divider; + /* + * Disable SSA Precharge when CD clock frequency < 500 MHz, + * enable otherwise. + */ + val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; + if (frequency >= 500000) + val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; + + val &= ~CDCLK_FREQ_DECIMAL_MASK; + /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ + val |= (frequency - 1000) / 500; + I915_WRITE(CDCLK_CTL, val); + } + + mutex_lock(&dev_priv->rps.hw_lock); + ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, + DIV_ROUND_UP(frequency, 25000)); + mutex_unlock(&dev_priv->rps.hw_lock); + + if (ret) { + DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", + ret, frequency); + return; + } + + dev_priv->cdclk_freq = frequency; +} + +void broxton_init_cdclk(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t val; + + /* + * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT + * or else the reset will hang because there is no PCH to respond. + * Move the handshake programming to initialization sequence. + * Previously was left up to BIOS. + */ + val = I915_READ(HSW_NDE_RSTWRN_OPT); + val &= ~RESET_PCH_HANDSHAKE_ENABLE; + I915_WRITE(HSW_NDE_RSTWRN_OPT, val); + + /* Enable PG1 for cdclk */ + intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); + + /* check if cd clock is enabled */ + if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { + DRM_DEBUG_KMS("Display already initialized\n"); + return; + } + + /* + * FIXME: + * - The initial CDCLK needs to be read from VBT. + * Need to make this change after VBT has changes for BXT. + * - check if setting the max (or any) cdclk freq is really necessary + * here, it belongs to modeset time + */ + broxton_set_cdclk(dev, 624000); + + I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); + udelay(10); + + if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) + DRM_ERROR("DBuf power enable timeout!\n"); +} + +void broxton_uninit_cdclk(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); + udelay(10); + + if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) + DRM_ERROR("DBuf power disable timeout!\n"); + + /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ + broxton_set_cdclk(dev, 19200); + + intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); +} + /* returns HPLL frequency in kHz */ static int valleyview_get_vco(struct drm_i915_private *dev_priv) { @@ -5363,6 +5538,26 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, return 200000; } +static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, + int max_pixclk) +{ + /* + * FIXME: + * - remove the guardband, it's not needed on BXT + * - set 19.2MHz bypass frequency if there are no active pipes + */ + if (max_pixclk > 576000*9/10) + return 624000; + else if (max_pixclk > 384000*9/10) + return 576000; + else if (max_pixclk > 288000*9/10) + return 384000; + else if (max_pixclk > 144000*9/10) + return 288000; + else + return 144000; +} + /* compute the max pixel clock for new configuration */ static int intel_mode_max_pixclk(struct drm_atomic_state *state) { @@ -5392,12 +5587,17 @@ static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(state->dev); struct intel_crtc *intel_crtc; int max_pixclk = intel_mode_max_pixclk(state); + int cdclk; if (max_pixclk < 0) return max_pixclk; - if (valleyview_calc_cdclk(dev_priv, max_pixclk) == - dev_priv->cdclk_freq) + if (IS_VALLEYVIEW(dev_priv)) + cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); + else + cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); + + if (cdclk == dev_priv->cdclk_freq) return 0; /* disable/enable all currently active pipes while we change cdclk */ @@ -8827,6 +9027,23 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv) intel_prepare_ddi(dev); } +static void broxton_modeset_global_resources(struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + int max_pixclk = intel_mode_max_pixclk(state); + int req_cdclk; + + /* see the comment in valleyview_modeset_global_resources */ + if (WARN_ON(max_pixclk < 0)) + return; + + req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); + + if (req_cdclk != dev_priv->cdclk_freq) + broxton_set_cdclk(dev, req_cdclk); +} + static int haswell_crtc_compute_clock(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state) { @@ -11983,7 +12200,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, * mode set on this crtc. For other crtcs we need to use the * adjusted_mode bits in the crtc directly. */ - if (IS_VALLEYVIEW(dev)) { + if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { ret = valleyview_modeset_global_pipes(state, &prepare_pipes); if (ret) goto done; @@ -14005,6 +14222,9 @@ static void intel_init_display(struct drm_device *dev) } else if (IS_VALLEYVIEW(dev)) { dev_priv->display.modeset_global_resources = valleyview_modeset_global_resources; + } else if (IS_BROXTON(dev)) { + dev_priv->display.modeset_global_resources = + broxton_modeset_global_resources; } switch (INTEL_INFO(dev)->gen) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 082be7161203..164f932f9f89 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1112,6 +1112,9 @@ void intel_prepare_reset(struct drm_device *dev); void intel_finish_reset(struct drm_device *dev); void hsw_enable_pc8(struct drm_i915_private *dev_priv); void hsw_disable_pc8(struct drm_i915_private *dev_priv); +void broxton_init_cdclk(struct drm_device *dev); +void broxton_uninit_cdclk(struct drm_device *dev); +void broxton_set_cdclk(struct drm_device *dev, int frequency); void intel_dp_get_m_n(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); -- cgit v1.2.3 From 5c6706e5644b608c2270f1d17c1b277901b3a121 Mon Sep 17 00:00:00 2001 From: Vandana Kannan Date: Mon, 24 Nov 2014 13:37:39 +0530 Subject: drm/i915/bxt: add display initialize/uninitialize sequence (PHY) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add PHY specific display initialization sequence as per BSpec. Note that the PHY initialization/uninitialization are done at their current place only for simplicity, in a future patch - when more of the runtime PM features will be enabled - these will be moved to power well#1 and modeset encoder enabling/disabling hooks respectively. The call to uninitialize the PHY during system/runtime suspend will be added later in this patchset. v1: Added function definitions in header files v2: Imre's review comments addressed - Moved CDCLK related definitions to i915_reg.h - Removed defintions for CDCLK frequency - Split uninit_cdclk() by adding a phy_uninit function - Calculate freq and decimal based on input frequency - Program SSA precharge based on input frequency - Use wait_for 1ms instead 200us udelay for DE PLL locking - Removed initial value for divider, freq, decimal, ratio. - Replaced polling loops with wait_for - Parameterized latency optim setting - Fix the parts where DE PLL has to be disabled. - Call CDCLK selection from mode set v3: (imre) - add note about the plan to move the cdclk/phy init to a better place - take rps.hw_lock around pcode access - fix DDI PHY timeout value - squash in Vandana's "PORT_CL2CM_DW6_A BUN fix", "DDI PHY programming register defn", "Do ddi_phy_init always", - move PHY register macros next to the corresponding CHV/VLV macros - move DE PLL register macros here from another patch since they are used here first - add BXT_ prefix to CDCLK flags - s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments - fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI - fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON when powering on DDI ports - fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports - add missing masking when programming CDCLK_FREQ_DECIMAL - add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN to OCL2_LDOFUSE_PWR_DIS to reduce confusion - add note about mismatch with bspec in the PORT_REF_DW6 fields - factor out PHY init code to a new function, so we can call it for PHY1 and PHY0, instead of open-coding the same v4: (ville) - split the CDCLK/PHY parts into two patches, update commit message accordingly - use the existing dpio_phy enum instead of adding a new one for the same purpose - flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to better match CHV - s/BXT_PHY/_BXT_PHY/ - use _PIPE for _BXT_PHY instead of open-coding it - drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON - define GT_DISPLAY_POWER_ON in a more standard way - make a note that the CHV ConfigDB also disagrees about GRC_CODE field definitions - fix lane optimization refactoring fumble from v3 - add per PHY uninit functions to match the init counterparts Signed-off-by: Vandana Kannan (v2) Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 96 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_ddi.c | 125 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 + 3 files changed, 223 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 164350cf760c..6e0913db6e24 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1117,6 +1117,102 @@ enum skl_disp_power_wells { #define DPIO_FRC_LATENCY_SHFIT 8 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) #define DPIO_UPAR_SHIFT 30 + +/* BXT PHY registers */ +#define _BXT_PHY(phy, a, b) _PIPE((phy), (a), (b)) + +#define BXT_P_CR_GT_DISP_PWRON 0x138090 +#define GT_DISPLAY_POWER_ON(phy) (1 << (phy)) + +#define _PHY_CTL_FAMILY_EDP 0x64C80 +#define _PHY_CTL_FAMILY_DDI 0x64C90 +#define COMMON_RESET_DIS (1 << 31) +#define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \ + _PHY_CTL_FAMILY_EDP) + +/* BXT PHY common lane registers */ +#define _PORT_CL1CM_DW0_A 0x162000 +#define _PORT_CL1CM_DW0_BC 0x6C000 +#define PHY_POWER_GOOD (1 << 16) +#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ + _PORT_CL1CM_DW0_A) + +#define _PORT_CL1CM_DW9_A 0x162024 +#define _PORT_CL1CM_DW9_BC 0x6C024 +#define IREF0RC_OFFSET_SHIFT 8 +#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) +#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \ + _PORT_CL1CM_DW9_A) + +#define _PORT_CL1CM_DW10_A 0x162028 +#define _PORT_CL1CM_DW10_BC 0x6C028 +#define IREF1RC_OFFSET_SHIFT 8 +#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) +#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \ + _PORT_CL1CM_DW10_A) + +#define _PORT_CL1CM_DW28_A 0x162070 +#define _PORT_CL1CM_DW28_BC 0x6C070 +#define OCL1_POWER_DOWN_EN (1 << 23) +#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) +#define SUS_CLK_CONFIG 0x3 +#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \ + _PORT_CL1CM_DW28_A) + +#define _PORT_CL1CM_DW30_A 0x162078 +#define _PORT_CL1CM_DW30_BC 0x6C078 +#define OCL2_LDOFUSE_PWR_DIS (1 << 6) +#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \ + _PORT_CL1CM_DW30_A) + +/* Defined for PHY0 only */ +#define BXT_PORT_CL2CM_DW6_BC 0x6C358 +#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) + +/* BXT PHY Ref registers */ +#define _PORT_REF_DW3_A 0x16218C +#define _PORT_REF_DW3_BC 0x6C18C +#define GRC_DONE (1 << 22) +#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \ + _PORT_REF_DW3_A) + +#define _PORT_REF_DW6_A 0x162198 +#define _PORT_REF_DW6_BC 0x6C198 +/* + * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them + * after testing. + */ +#define GRC_CODE_SHIFT 23 +#define GRC_CODE_MASK (0x1FF << GRC_CODE_SHIFT) +#define GRC_CODE_FAST_SHIFT 16 +#define GRC_CODE_FAST_MASK (0x7F << GRC_CODE_FAST_SHIFT) +#define GRC_CODE_SLOW_SHIFT 8 +#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) +#define GRC_CODE_NOM_MASK 0xFF +#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \ + _PORT_REF_DW6_A) + +#define _PORT_REF_DW8_A 0x1621A0 +#define _PORT_REF_DW8_BC 0x6C1A0 +#define GRC_DIS (1 << 15) +#define GRC_RDY_OVRD (1 << 1) +#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \ + _PORT_REF_DW8_A) + +/* BXT PHY TX registers */ +#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ + ((lane) & 1) * 0x80) + +#define _PORT_TX_DW14_LN0_A 0x162538 +#define _PORT_TX_DW14_LN0_B 0x6C538 +#define _PORT_TX_DW14_LN0_C 0x6C938 +#define LATENCY_OPTIM_SHIFT 30 +#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) +#define BXT_PORT_TX_DW14_LN(port, lane) (_PORT3((port), _PORT_TX_DW14_LN0_A, \ + _PORT_TX_DW14_LN0_B, \ + _PORT_TX_DW14_LN0_C) + \ + _BXT_LANE_OFFSET(lane)) + /* * Fence registers */ diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 25d697b9d3d9..31cadb83429d 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1864,6 +1864,130 @@ static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) } } +static void broxton_phy_init(struct drm_i915_private *dev_priv, + enum dpio_phy phy) +{ + enum port port; + uint32_t val; + + val = I915_READ(BXT_P_CR_GT_DISP_PWRON); + val |= GT_DISPLAY_POWER_ON(phy); + I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); + + /* Considering 10ms timeout until BSpec is updated */ + if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) + DRM_ERROR("timeout during PHY%d power on\n", phy); + + for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); + port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { + int lane; + + for (lane = 0; lane < 4; lane++) { + val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); + /* + * Note that on CHV this flag is called UPAR, but has + * the same function. + */ + val &= ~LATENCY_OPTIM; + if (lane != 1) + val |= LATENCY_OPTIM; + + I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); + } + } + + /* Program PLL Rcomp code offset */ + val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); + val &= ~IREF0RC_OFFSET_MASK; + val |= 0xE4 << IREF0RC_OFFSET_SHIFT; + I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); + + val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); + val &= ~IREF1RC_OFFSET_MASK; + val |= 0xE4 << IREF1RC_OFFSET_SHIFT; + I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); + + /* Program power gating */ + val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); + val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | + SUS_CLK_CONFIG; + I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); + + if (phy == DPIO_PHY0) { + val = I915_READ(BXT_PORT_CL2CM_DW6_BC); + val |= DW6_OLDO_DYN_PWR_DOWN_EN; + I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); + } + + val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); + val &= ~OCL2_LDOFUSE_PWR_DIS; + /* + * On PHY1 disable power on the second channel, since no port is + * connected there. On PHY0 both channels have a port, so leave it + * enabled. + * TODO: port C is only connected on BXT-P, so on BXT0/1 we should + * power down the second channel on PHY0 as well. + */ + if (phy == DPIO_PHY1) + val |= OCL2_LDOFUSE_PWR_DIS; + I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); + + if (phy == DPIO_PHY0) { + uint32_t grc_code; + /* + * PHY0 isn't connected to an RCOMP resistor so copy over + * the corresponding calibrated value from PHY1, and disable + * the automatic calibration on PHY0. + */ + if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, + 10)) + DRM_ERROR("timeout waiting for PHY1 GRC\n"); + + val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); + val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; + grc_code = val << GRC_CODE_FAST_SHIFT | + val << GRC_CODE_SLOW_SHIFT | + val; + I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); + + val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); + val |= GRC_DIS | GRC_RDY_OVRD; + I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); + } + + val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); + val |= COMMON_RESET_DIS; + I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); +} + +void broxton_ddi_phy_init(struct drm_device *dev) +{ + /* Enable PHY1 first since it provides Rcomp for PHY0 */ + broxton_phy_init(dev->dev_private, DPIO_PHY1); + broxton_phy_init(dev->dev_private, DPIO_PHY0); +} + +static void broxton_phy_uninit(struct drm_i915_private *dev_priv, + enum dpio_phy phy) +{ + uint32_t val; + + val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); + val &= ~COMMON_RESET_DIS; + I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); +} + +void broxton_ddi_phy_uninit(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + broxton_phy_uninit(dev_priv, DPIO_PHY1); + broxton_phy_uninit(dev_priv, DPIO_PHY0); + + /* FIXME: do this in broxton_phy_uninit per phy */ + I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); +} + void intel_ddi_pll_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -1882,6 +2006,7 @@ void intel_ddi_pll_init(struct drm_device *dev) DRM_ERROR("LCPLL1 is disabled\n"); } else if (IS_BROXTON(dev)) { broxton_init_cdclk(dev); + broxton_ddi_phy_init(dev); } else { /* * The LCPLL register should be turned on by the BIOS. For now diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 164f932f9f89..1ae0c3a1ad0b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1115,6 +1115,8 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv); void broxton_init_cdclk(struct drm_device *dev); void broxton_uninit_cdclk(struct drm_device *dev); void broxton_set_cdclk(struct drm_device *dev, int frequency); +void broxton_ddi_phy_init(struct drm_device *dev); +void broxton_ddi_phy_uninit(struct drm_device *dev); void intel_dp_get_m_n(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); -- cgit v1.2.3 From eee215660cedb4ee3c93de52a9bbc742891bb290 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 10 Mar 2015 21:18:30 +0200 Subject: drm/i915/bxt: add description about the BXT PHYs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics. v2: - add more detail about the mapping between ports and transcoders (ville) Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- Documentation/DocBook/drm.tmpl | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++------ 2 files changed, 14 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index f4976cd7b32b..a8509c2b9c17 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -4067,7 +4067,7 @@ int num_ioctls; DPIO !Pdrivers/gpu/drm/i915/i915_reg.h DPIO - Dual channel PHY (VLV/CHV) + Dual channel PHY (VLV/CHV/BXT) @@ -4118,7 +4118,7 @@ int num_ioctls;
- Single channel PHY (CHV) + Single channel PHY (CHV/BXT) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6e0913db6e24..11b9a0898111 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -715,7 +715,7 @@ enum skl_disp_power_wells { /** * DOC: DPIO * - * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI + * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI * ports. DPIO is the name given to such a display PHY. These PHYs * don't follow the standard programming model using direct MMIO * registers, and instead their registers must be accessed trough IOSF @@ -746,7 +746,7 @@ enum skl_disp_power_wells { * controlled from the display controller side. No DPIO registers * need to be accessed during AUX communication, * - * Generally the common lane corresponds to the pipe and + * Generally on VLV/CHV the common lane corresponds to the pipe and * the spline (PCS/TX) corresponds to the port. * * For dual channel PHY (VLV/CHV): @@ -768,11 +768,17 @@ enum skl_disp_power_wells { * * port D == PCS/TX CH0 * - * Note: digital port B is DDI0, digital port C is DDI1, - * digital port D is DDI2 + * On BXT the entire PHY channel corresponds to the port. That means + * the PLL is also now associated with the port rather than the pipe, + * and so the clock needs to be routed to the appropriate transcoder. + * Port A PLL is directly connected to transcoder EDP and port B/C + * PLLs can be routed to any transcoder A/B/C. + * + * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is + * digital port D (CHV) or port A (BXT). */ /* - * Dual channel PHY (VLV/CHV) + * Dual channel PHY (VLV/CHV/BXT) * --------------------------------- * | CH0 | CH1 | * | CMN/PLL/REF | CMN/PLL/REF | @@ -784,7 +790,7 @@ enum skl_disp_power_wells { * | DDI0 | DDI1 | DP/HDMI ports * --------------------------------- * - * Single channel PHY (CHV) + * Single channel PHY (CHV/BXT) * ----------------- * | CH0 | * | CMN/PLL/REF | -- cgit v1.2.3 From 664326f8a5b7e4ab7ed469acaadc63d2a05d8720 Mon Sep 17 00:00:00 2001 From: "A.Sunil Kamath" Date: Mon, 24 Nov 2014 13:37:44 +0530 Subject: drm/i915/bxt: Implement enable/disable for Display C9 state v2: Modified as per review comments from Imre - Mention enabling instead of allowing in the debug trace and remove unnecessary comments. v3: - Rebase to latest. - Move DC9-related functions from intel_display.c to intel_runtime_pm.c. v4: (imre) - remove DC5 disabling, it's a nop at this point - squashed in Suketu's "Assert the requirements to enter or exit DC9" patch - remove check for RUNTIME_PM from assert_can_enable_dc9, it's not a dependency Signed-off-by: A.Sunil Kamath (v3) Signed-off-by: Imre Deak Reviewed-by: Sagar Kamble Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 5 +++ drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_runtime_pm.c | 66 +++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 11b9a0898111..29c41f1bba34 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7059,6 +7059,11 @@ enum skl_disp_power_wells { #define BXT_DE_PLL_PLL_ENABLE (1 << 31) #define BXT_DE_PLL_LOCK (1 << 30) +/* GEN9 DC */ +#define DC_STATE_EN 0x45504 +#define DC_STATE_EN_UPTO_DC5 (1<<0) +#define DC_STATE_EN_DC9 (1<<3) + /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, * since on HSW we can't write to it using I915_WRITE. */ #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 1ae0c3a1ad0b..1cad3ddaf3c7 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1117,6 +1117,8 @@ void broxton_uninit_cdclk(struct drm_device *dev); void broxton_set_cdclk(struct drm_device *dev, int frequency); void broxton_ddi_phy_init(struct drm_device *dev); void broxton_ddi_phy_uninit(struct drm_device *dev); +void bxt_enable_dc9(struct drm_i915_private *dev_priv); +void bxt_disable_dc9(struct drm_i915_private *dev_priv); void intel_dp_get_m_n(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index ff5cce32c7d6..8fe2fdeab652 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -351,6 +351,72 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ BIT(POWER_DOMAIN_INIT)) +static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) +{ + struct drm_device *dev = dev_priv->dev; + + WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); + WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), + "DC9 already programmed to be enabled.\n"); + WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, + "DC5 still not disabled to enable DC9.\n"); + WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); + WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); + + /* + * TODO: check for the following to verify the conditions to enter DC9 + * state are satisfied: + * 1] Check relevant display engine registers to verify if mode set + * disable sequence was followed. + * 2] Check if display uninitialize sequence is initialized. + */ +} + +static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) +{ + WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); + WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), + "DC9 already programmed to be disabled.\n"); + WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, + "DC5 still not disabled.\n"); + + /* + * TODO: check for the following to verify DC9 state was indeed + * entered before programming to disable it: + * 1] Check relevant display engine registers to verify if mode + * set disable sequence was followed. + * 2] Check if display uninitialize sequence is initialized. + */ +} + +void bxt_enable_dc9(struct drm_i915_private *dev_priv) +{ + uint32_t val; + + assert_can_enable_dc9(dev_priv); + + DRM_DEBUG_KMS("Enabling DC9\n"); + + val = I915_READ(DC_STATE_EN); + val |= DC_STATE_EN_DC9; + I915_WRITE(DC_STATE_EN, val); + POSTING_READ(DC_STATE_EN); +} + +void bxt_disable_dc9(struct drm_i915_private *dev_priv) +{ + uint32_t val; + + assert_can_disable_dc9(dev_priv); + + DRM_DEBUG_KMS("Disabling DC9\n"); + + val = I915_READ(DC_STATE_EN); + val &= ~DC_STATE_EN_DC9; + I915_WRITE(DC_STATE_EN, val); + POSTING_READ(DC_STATE_EN); +} + static void skl_set_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { -- cgit v1.2.3 From 31335cec02604cba72deee44bb18cb82790ef2aa Mon Sep 17 00:00:00 2001 From: Suketu Shah Date: Mon, 24 Nov 2014 13:37:45 +0530 Subject: drm/i915/bxt: Add DC9 Trigger sequence Add triggers for DC9 as per details provided in bxt_enable_dc9 and bxt_disable_dc9 implementations. v1: - Add SKL check in gen9_disable_dc5 as it is possible for DC5 to remain disabled only for SKL. - Add additional checks for whether DC5 is already disabled during DC5-disabling only for BXT. v2: - rebase to latest. - Load CSR during DC9 disabling in the beginning before DC9 is disabled. - Make gen9_disable_dc5 function non-static as it's being called by functions in i915_drv.c. - Enable DC9-related functionality using a macro. v3: (imre) - remove BXT_ENABLE_DC9, we want DC9 always, and it's only valid on BXT - remove DC5 disabling and CSR FW loaded check, these are nop atm - squash in Vandana's "Do ddi_phy_init always" patch v4: - add TODO to re-enable DC5 during resume if CSR FW is available (sagar) Signed-off-by: Suketu Shah Signed-off-by: A.Sunil Kamath (v2) Signed-off-by: Imre Deak Reviewed-by: Sagar Kamble Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index c1a3cdb5189b..ad77131cdcff 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1009,6 +1009,38 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv) return 0; } +static int bxt_suspend_complete(struct drm_i915_private *dev_priv) +{ + struct drm_device *dev = dev_priv->dev; + + /* TODO: when DC5 support is added disable DC5 here. */ + + broxton_ddi_phy_uninit(dev); + broxton_uninit_cdclk(dev); + bxt_enable_dc9(dev_priv); + + return 0; +} + +static int bxt_resume_prepare(struct drm_i915_private *dev_priv) +{ + struct drm_device *dev = dev_priv->dev; + + /* TODO: when CSR FW support is added make sure the FW is loaded */ + + bxt_disable_dc9(dev_priv); + + /* + * TODO: when DC5 support is added enable DC5 here if the CSR FW + * is available. + */ + broxton_init_cdclk(dev); + broxton_ddi_phy_init(dev); + intel_prepare_ddi(dev); + + return 0; +} + /* * Save all Gunit registers that may be lost after a D3 and a subsequent * S0i[R123] transition. The list of registers needing a save/restore is @@ -1479,6 +1511,9 @@ static int intel_runtime_resume(struct device *device) if (IS_GEN6(dev_priv)) intel_init_pch_refclk(dev); + + if (IS_BROXTON(dev)) + ret = bxt_resume_prepare(dev_priv); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) hsw_disable_pc8(dev_priv); else if (IS_VALLEYVIEW(dev_priv)) @@ -1511,7 +1546,9 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv) struct drm_device *dev = dev_priv->dev; int ret; - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) + if (IS_BROXTON(dev)) + ret = bxt_suspend_complete(dev_priv); + else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ret = hsw_suspend_complete(dev_priv); else if (IS_VALLEYVIEW(dev)) ret = vlv_suspend_complete(dev_priv); -- cgit v1.2.3 From 475d231be9bae4b997eb7e5a9a3cb214259cf90a Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 10 Apr 2015 16:22:39 +0200 Subject: drm/atomic-helper: Don't call atomic_update_plane when it stays off It's a silly thing to do and surprises driver writers. Most likely this did already blow up for exynos. It's also a silly thing to change plane state when it's off, but fbdev is silly (it does an unconditional modeset over all planes). And userspace can be evil. So I think we need this. With this check in the helpers we can remove the one in i915 code for the same conditions (becuase ->crtc iff ->fb). Cc: Gustavo Padovan Cc: dri-devel@lists.freedesktop.org Cc: Inki Dae Cc: Matt Roper Acked-by: Laurent Pinchart Tested-by: Laurent Pinchart Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic_helper.c | 3 ++- drivers/gpu/drm/i915/intel_atomic_plane.c | 4 ---- 2 files changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index a2fb0d45217a..d536817699c1 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -1138,7 +1138,8 @@ void drm_atomic_helper_commit_planes(struct drm_device *dev, if (drm_atomic_plane_disabling(plane, old_plane_state) && funcs->atomic_disable) funcs->atomic_disable(plane, old_plane_state); - else + else if (plane->state->crtc || + drm_atomic_plane_disabling(plane, old_plane_state)) funcs->atomic_update(plane, old_plane_state); } diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index 976b89156570..cb383a0fc392 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -172,10 +172,6 @@ static void intel_plane_atomic_update(struct drm_plane *plane, struct intel_plane_state *intel_state = to_intel_plane_state(plane->state); - /* Don't disable an already disabled plane */ - if (!plane->state->fb && !old_state->fb) - return; - intel_plane->commit_plane(plane, intel_state); } -- cgit v1.2.3 From 5678ad736758db6554c8466921dfc496f1fe58b4 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 17 Mar 2015 14:45:29 +0000 Subject: drm/i915: Fix view type in warning message One month passed between posting a patch and it getting merged, and unfortunately even though it still applies, it needs fixing to account for changes in function parameters since: commit d385612e15b8b6eb3db328d83f1872ef8a381788 Author: Tvrtko Ursulin Date: Tue Mar 17 14:45:29 2015 +0000 drm/i915: Log view type when printing warnings Signed-off-by: Tvrtko Ursulin Cc: Joonas Lahtinen [danvet: Squash in fixup from Tvrtko to fix the rebase conflict.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 89d9ebe67520..f7b8766e09fc 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5181,7 +5181,7 @@ i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, i915_ggtt_view_equal(&vma->ggtt_view, view)) return vma->node.start; - WARN(1, "global vma for this object not found.\n"); + WARN(1, "global vma for this object not found. (view=%u)\n", view->type); return -1; } -- cgit v1.2.3 From d328c9d78d64ca11e744fe227096990430a88477 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 10 Apr 2015 16:22:37 +0200 Subject: drm/i915: Select starting pipe bpp irrespective or the primary plane Since universal planes the primary plane might not be around, and it's kinda silly to restrict the pipe bpp to the primary plane if we might end up displaying a 10bpc video overlay. And with atomic we might very well enable a pipe without a primary plane. So just use the platform max as a starting point and then restrict appropriately. Of course this is all still a bit moot as long as we artificially compress everything to max 8bpc because we don't use the hi-bpc gamma tables. Signed-off-by: Daniel Vetter Reviewed-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 61 +++++++----------------------------- 1 file changed, 12 insertions(+), 49 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5ee5d8cd9cd1..0654fc549ba3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6302,14 +6302,6 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, adjusted_mode->hsync_start == adjusted_mode->hdisplay) return -EINVAL; - if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { - pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ - } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { - /* only a 8bpc pipe, with 6bpc dither through the panel fitter - * for lvds. */ - pipe_config->pipe_bpp = 8*3; - } - if (HAS_IPS(dev)) hsw_compute_ips_config(crtc, pipe_config); @@ -10981,7 +10973,6 @@ connected_sink_compute_bpp(struct intel_connector *connector, static int compute_baseline_pipe_bpp(struct intel_crtc *crtc, - struct drm_framebuffer *fb, struct intel_crtc_state *pipe_config) { struct drm_device *dev = crtc->base.dev; @@ -10989,41 +10980,13 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc, struct intel_connector *connector; int bpp, i; - switch (fb->pixel_format) { - case DRM_FORMAT_C8: - bpp = 8*3; /* since we go through a colormap */ - break; - case DRM_FORMAT_XRGB1555: - case DRM_FORMAT_ARGB1555: - /* checked in intel_framebuffer_init already */ - if (WARN_ON(INTEL_INFO(dev)->gen > 3)) - return -EINVAL; - case DRM_FORMAT_RGB565: - bpp = 6*3; /* min is 18bpp */ - break; - case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: - /* checked in intel_framebuffer_init already */ - if (WARN_ON(INTEL_INFO(dev)->gen < 4)) - return -EINVAL; - case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_ARGB8888: - bpp = 8*3; - break; - case DRM_FORMAT_XRGB2101010: - case DRM_FORMAT_ARGB2101010: - case DRM_FORMAT_XBGR2101010: - case DRM_FORMAT_ABGR2101010: - /* checked in intel_framebuffer_init already */ - if (WARN_ON(INTEL_INFO(dev)->gen < 4)) - return -EINVAL; + if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) bpp = 10*3; - break; - /* TODO: gen4+ supports 16 bpc floating point, too. */ - default: - DRM_DEBUG_KMS("unsupported depth\n"); - return -EINVAL; - } + else if (INTEL_INFO(dev)->gen >= 5) + bpp = 12*3; + else + bpp = 8*3; + pipe_config->pipe_bpp = bpp; @@ -11280,7 +11243,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, struct intel_connector *connector; struct drm_connector_state *connector_state; struct intel_crtc_state *pipe_config; - int plane_bpp, ret = -EINVAL; + int base_bpp, ret = -EINVAL; int i; bool retry = true; @@ -11325,9 +11288,9 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, * plane pixel format and any sink constraints into account. Returns the * source plane bpp so that dithering can be selected on mismatches * after encoders and crtc also have had their say. */ - plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), - fb, pipe_config); - if (plane_bpp < 0) + base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), + pipe_config); + if (base_bpp < 0) goto fail; /* @@ -11395,9 +11358,9 @@ encoder_retry: goto encoder_retry; } - pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; + pipe_config->dither = pipe_config->pipe_bpp != base_bpp; DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", - plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); + base_bpp, pipe_config->pipe_bpp, pipe_config->dither); return pipe_config; fail: -- cgit v1.2.3 From 8805aa713e3590b74500dc2283e2df02ba363a4a Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 10 Apr 2015 16:22:38 +0200 Subject: drm/i915: Drop unecessary fb arguments from function signatures This is a separate patch to simplify conflict handling with other ongoing atomic work. Signed-off-by: Daniel Vetter Reviewed-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0654fc549ba3..783d6008fded 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11235,7 +11235,6 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) static struct intel_crtc_state * intel_modeset_pipe_config(struct drm_crtc *crtc, - struct drm_framebuffer *fb, struct drm_display_mode *mode, struct drm_atomic_state *state) { @@ -12040,7 +12039,6 @@ static void update_scanline_offset(struct intel_crtc *crtc) static struct intel_crtc_state * intel_modeset_compute_config(struct drm_crtc *crtc, struct drm_display_mode *mode, - struct drm_framebuffer *fb, struct drm_atomic_state *state, unsigned *modeset_pipes, unsigned *prepare_pipes, @@ -12078,7 +12076,7 @@ intel_modeset_compute_config(struct drm_crtc *crtc, if (WARN_ON(&intel_crtc->base != crtc)) continue; - pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state); + pipe_config = intel_modeset_pipe_config(crtc, mode, state); if (IS_ERR(pipe_config)) return pipe_config; @@ -12281,7 +12279,7 @@ static int intel_set_mode(struct drm_crtc *crtc, unsigned modeset_pipes, prepare_pipes, disable_pipes; int ret = 0; - pipe_config = intel_modeset_compute_config(crtc, mode, fb, state, + pipe_config = intel_modeset_compute_config(crtc, mode, state, &modeset_pipes, &prepare_pipes, &disable_pipes); @@ -12739,7 +12737,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set) goto fail; pipe_config = intel_modeset_compute_config(set->crtc, set->mode, - set->fb, state, + state, &modeset_pipes, &prepare_pipes, &disable_pipes); -- cgit v1.2.3 From b7192a567ca472ac774b19a672dab77cb1e4b4db Mon Sep 17 00:00:00 2001 From: Sonika Jindal Date: Wed, 15 Apr 2015 11:02:33 +0530 Subject: drm/i915/skl: Add back HDMI translation table The HDMI translation table is added back to bspec, so adding it, and defaulting the 800mV+0dB entry. The HDMI translation table was removed by following commit as per HW team's recommendation: commit 7ff446708bd1 ("drm/i915/skl: Only use the 800mV+2bB HDMI translation entry") v2: Adding reference to commit which removed this table (Jani) Cc: Damien Lespiau Signed-off-by: Sonika Jindal Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 31cadb83429d..24ecb486465b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -155,8 +155,17 @@ static const struct ddi_buf_trans skl_ddi_translations_edp[] = { static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { - /* Idx NT mV T mV db */ - { 0x00004014, 0x00000087 }, /* 0: 800 1000 2 */ + { 0x00000018, 0x000000ac }, + { 0x00005012, 0x0000009d }, + { 0x00007011, 0x00000088 }, + { 0x00000018, 0x000000a1 }, + { 0x00000018, 0x00000098 }, + { 0x00004013, 0x00000088 }, + { 0x00006012, 0x00000087 }, + { 0x00000018, 0x000000df }, + { 0x00003015, 0x00000087 }, + { 0x00003015, 0x000000c7 }, + { 0x00000018, 0x000000c7 }, }; enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) @@ -214,16 +223,9 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp); } - /* - * On SKL, the recommendation from the hw team is to always use - * a certain type of level shifter (and thus the corresponding - * 800mV+2dB entry). Given that's the only validated entry, we - * override what is in the VBT, at least until further notice. - */ - hdmi_level = 0; ddi_translations_hdmi = skl_ddi_translations_hdmi; n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); - hdmi_default_entry = 0; + hdmi_default_entry = 7; } else if (IS_BROADWELL(dev)) { ddi_translations_fdi = bdw_ddi_translations_fdi; ddi_translations_dp = bdw_ddi_translations_dp; -- cgit v1.2.3 From 1f30a61482df44ee75c4db73f7f3d70052b93e83 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 15 Apr 2015 16:39:59 +0100 Subject: drm/i915: Simplify i915_gem_obj_is_pinned() test for set-tiling Since the removal of the user pin_ioctl, the only means for pinning an object is either through binding to the scanout or during execbuf reservation. As the later prevents a call to set-tiling, we need only check if the obj is pinned into the display plane to see if we need reject the set-tiling ioctl. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_tiling.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 6377b22269ad..633bd1fcab69 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -336,7 +336,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, } mutex_lock(&dev->struct_mutex); - if (i915_gem_obj_is_pinned(obj) || obj->framebuffer_references) { + if (obj->pin_display || obj->framebuffer_references) { ret = -EBUSY; goto err; } -- cgit v1.2.3 From baaa5cfb42d94440385e1229c000da1ecc369d47 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 15 Apr 2015 16:42:46 +0100 Subject: drm/i915: Update meaning of debugfs object's pin_flag Since the pin_ioctl is defunct, we only care about whether an object is pinned into the display for debug purposes. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 07a71c0ff775..1bd2ec5a5a57 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -96,7 +96,7 @@ static int i915_capabilities(struct seq_file *m, void *data) static const char *get_pin_flag(struct drm_i915_gem_object *obj) { - if (i915_gem_obj_is_pinned(obj)) + if (obj->pin_display) return "p"; else return " "; -- cgit v1.2.3 From 535afa2e9e3c1867460d6981d879b04d8b2b9ab3 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 15 Apr 2015 16:52:29 -0700 Subject: drm/i915/vlv: check port in infoframe_enabled v2 Same as IBX and G4x, they all share the same genetic material. v2: we all need a bit more port in our lives Signed-off-by: Jesse Barnes Signed-off-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_hdmi.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 7dfc3584b6b4..56d1d13c075a 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -324,10 +324,15 @@ static bool vlv_infoframe_enabled(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); u32 val = I915_READ(reg); + u32 port = intel_dig_port->port; - return val & VIDEO_DIP_ENABLE; + if (port == (val & VIDEO_DIP_PORT_MASK)) + return val & VIDEO_DIP_ENABLE; + + return false; } static void hsw_write_infoframe(struct drm_encoder *encoder, -- cgit v1.2.3 From 1ab23380f8b990ad865349040ec14c3ebe3a09c5 Mon Sep 17 00:00:00 2001 From: Satheeshakrishna M Date: Fri, 22 Aug 2014 09:49:06 +0530 Subject: drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9 PORT_CLK_SEL programming is needed only on HSW/BDW. v2: - don't program PORT_CLK_SEL from mst encoders either (imre) v3: - fix the check for GEN9+ in intel_mst_pre_enable_dp() (damien) Signed-off-by: Satheeshakrishna M Signed-off-by: Imre Deak Reviewed-by: Sagar Kamble Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 4 ++-- drivers/gpu/drm/i915/intel_dp_mst.c | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 24ecb486465b..f98a403c6625 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1567,7 +1567,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) I915_WRITE(DPLL_CTRL2, val); - } else { + } else if (INTEL_INFO(dev)->gen < 9) { WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); } @@ -1626,7 +1626,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) if (IS_SKYLAKE(dev)) I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port))); - else + else if (INTEL_INFO(dev)->gen < 9) I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); } diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 73350894e2c9..3945057c5bbe 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -173,8 +173,10 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder) if (intel_dp->active_mst_links == 0) { enum port port = intel_ddi_get_encoder_port(encoder); - I915_WRITE(PORT_CLK_SEL(port), - intel_crtc->config->ddi_pll_sel); + /* FIXME: add support for SKL */ + if (INTEL_INFO(dev)->gen < 9) + I915_WRITE(PORT_CLK_SEL(port), + intel_crtc->config->ddi_pll_sel); intel_ddi_init_dp_buf_reg(&intel_dig_port->base); -- cgit v1.2.3 From ff6d9f55fe3f217dabce6b5ee7dbd306be5f4391 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 21 Jan 2015 17:19:54 -0800 Subject: drm/i915/bxt: fix panel fitter setup in crtc disable/enable Broxton has the same panel fitter registers as Skylake. v2: - add MISSING_CASE for future platforms (daniel) Signed-off-by: Jesse Barnes Signed-off-by: Imre Deak Reviewed-by: Sagar Kamble Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 783d6008fded..3322e5a12e8e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4881,10 +4881,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_ddi_enable_pipe_clock(intel_crtc); - if (IS_SKYLAKE(dev)) + if (INTEL_INFO(dev)->gen == 9) skylake_pfit_update(intel_crtc, 1); - else + else if (INTEL_INFO(dev)->gen < 9) ironlake_pfit_enable(intel_crtc); + else + MISSING_CASE(INTEL_INFO(dev)->gen); /* * On ILK+ LUT must be loaded before the pipe is running but with @@ -5029,10 +5031,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); - if (IS_SKYLAKE(dev)) + if (INTEL_INFO(dev)->gen == 9) skylake_pfit_update(intel_crtc, 0); - else + else if (INTEL_INFO(dev)->gen < 9) ironlake_pfit_disable(intel_crtc); + else + MISSING_CASE(INTEL_INFO(dev)->gen); intel_ddi_disable_pipe_clock(intel_crtc); @@ -9191,10 +9195,13 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { - if (IS_SKYLAKE(dev)) + if (INTEL_INFO(dev)->gen == 9) skylake_get_pfit_config(crtc, pipe_config); - else + else if (INTEL_INFO(dev)->gen < 9) ironlake_get_pfit_config(crtc, pipe_config); + else + MISSING_CASE(INTEL_INFO(dev)->gen); + } else { pipe_config->scaler_state.scaler_id = -1; pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); -- cgit v1.2.3 From dfb82408471ee2e56b26c05dcd50317f873bee57 Mon Sep 17 00:00:00 2001 From: Satheeshakrishna M Date: Fri, 22 Aug 2014 09:49:09 +0530 Subject: drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequence Plug bxt PLL code into existing shared DPLL framework. v2: (imre) - squash in Satheeshakrishna's "Define BXT clock registers" and "Add state variables for bxt clock registers" patches - squash in Vandanas's "Change grp access to lane access for PLL" - fix group vs. lane access in bxt_ddi_pll_get_hw_state - add code comment why we read from lane registers while writing to group registers - clean up register macros - use BXT_PORT_PLL_* macros instead of open-coding the same - check if BXT_PORT_PCS_DW12_LN01 matches BXT_PORT_PCS_DW12_LN23 during hardware state readout - add missing LANESTAGGER_STRAP_OVRD masking - add note about missing step according to the latest BUN for PORT_PLL_9/lockthresh Signed-off-by: Satheeshakrishna M (v1) Signed-off-by: Imre Deak Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 76 ++++++++++++++++++ drivers/gpu/drm/i915/intel_ddi.c | 165 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 244 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2645ba35b130..a7049ea164e2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -303,6 +303,9 @@ struct intel_dpll_hw_state { uint32_t ctrl1; /* HDMI only, 0 when used for DP */ uint32_t cfgcr1, cfgcr2; + + /* bxt */ + uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pcsdw12; }; struct intel_shared_dpll_config { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 29c41f1bba34..5c81728e4400 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1136,6 +1136,60 @@ enum skl_disp_power_wells { #define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \ _PHY_CTL_FAMILY_EDP) +/* BXT PHY PLL registers */ +#define _PORT_PLL_A 0x46074 +#define _PORT_PLL_B 0x46078 +#define _PORT_PLL_C 0x4607c +#define PORT_PLL_ENABLE (1 << 31) +#define PORT_PLL_LOCK (1 << 30) +#define PORT_PLL_REF_SEL (1 << 27) +#define BXT_PORT_PLL_ENABLE(port) _PORT(port, _PORT_PLL_A, _PORT_PLL_B) + +#define _PORT_PLL_EBB_0_A 0x162034 +#define _PORT_PLL_EBB_0_B 0x6C034 +#define _PORT_PLL_EBB_0_C 0x6C340 +#define PORT_PLL_P1_MASK (0x07 << 13) +#define PORT_PLL_P1(x) ((x) << 13) +#define PORT_PLL_P2_MASK (0x1f << 8) +#define PORT_PLL_P2(x) ((x) << 8) +#define BXT_PORT_PLL_EBB_0(port) _PORT3(port, _PORT_PLL_EBB_0_A, \ + _PORT_PLL_EBB_0_B, \ + _PORT_PLL_EBB_0_C) + +#define _PORT_PLL_EBB_4_A 0x162038 +#define _PORT_PLL_EBB_4_B 0x6C038 +#define _PORT_PLL_EBB_4_C 0x6C344 +#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) +#define PORT_PLL_RECALIBRATE (1 << 14) +#define BXT_PORT_PLL_EBB_4(port) _PORT3(port, _PORT_PLL_EBB_4_A, \ + _PORT_PLL_EBB_4_B, \ + _PORT_PLL_EBB_4_C) + +#define _PORT_PLL_0_A 0x162100 +#define _PORT_PLL_0_B 0x6C100 +#define _PORT_PLL_0_C 0x6C380 +/* PORT_PLL_0_A */ +#define PORT_PLL_M2_MASK 0xFF +/* PORT_PLL_1_A */ +#define PORT_PLL_N_MASK (0x0F << 8) +#define PORT_PLL_N(x) ((x) << 8) +/* PORT_PLL_2_A */ +#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF +/* PORT_PLL_3_A */ +#define PORT_PLL_M2_FRAC_ENABLE (1 << 16) +/* PORT_PLL_6_A */ +#define PORT_PLL_PROP_COEFF_MASK 0xF +#define PORT_PLL_INT_COEFF_MASK (0x1F << 8) +#define PORT_PLL_INT_COEFF(x) ((x) << 8) +#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) +#define PORT_PLL_GAIN_CTL(x) ((x) << 16) +/* PORT_PLL_8_A */ +#define PORT_PLL_TARGET_CNT_MASK 0x3FF +#define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ + _PORT_PLL_0_B, \ + _PORT_PLL_0_C) +#define BXT_PORT_PLL(port, idx) (_PORT_PLL_BASE(port) + (idx) * 4) + /* BXT PHY common lane registers */ #define _PORT_CL1CM_DW0_A 0x162000 #define _PORT_CL1CM_DW0_BC 0x6C000 @@ -1205,6 +1259,28 @@ enum skl_disp_power_wells { #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \ _PORT_REF_DW8_A) +/* BXT PHY PCS registers */ +#define _PORT_PCS_DW12_LN01_A 0x162430 +#define _PORT_PCS_DW12_LN01_B 0x6C430 +#define _PORT_PCS_DW12_LN01_C 0x6C830 +#define _PORT_PCS_DW12_LN23_A 0x162630 +#define _PORT_PCS_DW12_LN23_B 0x6C630 +#define _PORT_PCS_DW12_LN23_C 0x6CA30 +#define _PORT_PCS_DW12_GRP_A 0x162c30 +#define _PORT_PCS_DW12_GRP_B 0x6CC30 +#define _PORT_PCS_DW12_GRP_C 0x6CE30 +#define LANESTAGGER_STRAP_OVRD (1 << 6) +#define LANE_STAGGER_MASK 0x1F +#define BXT_PORT_PCS_DW12_LN01(port) _PORT3(port, _PORT_PCS_DW12_LN01_A, \ + _PORT_PCS_DW12_LN01_B, \ + _PORT_PCS_DW12_LN01_C) +#define BXT_PORT_PCS_DW12_LN23(port) _PORT3(port, _PORT_PCS_DW12_LN23_A, \ + _PORT_PCS_DW12_LN23_B, \ + _PORT_PCS_DW12_LN23_C) +#define BXT_PORT_PCS_DW12_GRP(port) _PORT3(port, _PORT_PCS_DW12_GRP_A, \ + _PORT_PCS_DW12_GRP_B, \ + _PORT_PCS_DW12_GRP_C) + /* BXT PHY TX registers */ #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ ((lane) & 1) * 0x80) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index f98a403c6625..a6d0cb0b10fc 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1990,6 +1990,169 @@ void broxton_ddi_phy_uninit(struct drm_device *dev) I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); } +static const char * const bxt_ddi_pll_names[] = { + "PORT PLL A", + "PORT PLL B", + "PORT PLL C", +}; + +static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, + struct intel_shared_dpll *pll) +{ + uint32_t temp; + enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ + + temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp &= ~PORT_PLL_REF_SEL; + /* Non-SSC reference */ + I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); + + /* Disable 10 bit clock */ + temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); + temp &= ~PORT_PLL_10BIT_CLK_ENABLE; + I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); + + /* Write P1 & P2 */ + temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); + temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); + temp |= pll->config.hw_state.ebb0; + I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); + + /* Write M2 integer */ + temp = I915_READ(BXT_PORT_PLL(port, 0)); + temp &= ~PORT_PLL_M2_MASK; + temp |= pll->config.hw_state.pll0; + I915_WRITE(BXT_PORT_PLL(port, 0), temp); + + /* Write N */ + temp = I915_READ(BXT_PORT_PLL(port, 1)); + temp &= ~PORT_PLL_N_MASK; + temp |= pll->config.hw_state.pll1; + I915_WRITE(BXT_PORT_PLL(port, 1), temp); + + /* Write M2 fraction */ + temp = I915_READ(BXT_PORT_PLL(port, 2)); + temp &= ~PORT_PLL_M2_FRAC_MASK; + temp |= pll->config.hw_state.pll2; + I915_WRITE(BXT_PORT_PLL(port, 2), temp); + + /* Write M2 fraction enable */ + temp = I915_READ(BXT_PORT_PLL(port, 3)); + temp &= ~PORT_PLL_M2_FRAC_ENABLE; + temp |= pll->config.hw_state.pll3; + I915_WRITE(BXT_PORT_PLL(port, 3), temp); + + /* Write coeff */ + temp = I915_READ(BXT_PORT_PLL(port, 6)); + temp &= ~PORT_PLL_PROP_COEFF_MASK; + temp &= ~PORT_PLL_INT_COEFF_MASK; + temp &= ~PORT_PLL_GAIN_CTL_MASK; + temp |= pll->config.hw_state.pll6; + I915_WRITE(BXT_PORT_PLL(port, 6), temp); + + /* Write calibration val */ + temp = I915_READ(BXT_PORT_PLL(port, 8)); + temp &= ~PORT_PLL_TARGET_CNT_MASK; + temp |= pll->config.hw_state.pll8; + I915_WRITE(BXT_PORT_PLL(port, 8), temp); + + /* + * FIXME: program PORT_PLL_9/i_lockthresh according to the latest + * specification update. + */ + + /* Recalibrate with new settings */ + temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); + temp |= PORT_PLL_RECALIBRATE; + I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); + /* Enable 10 bit clock */ + temp |= PORT_PLL_10BIT_CLK_ENABLE; + I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); + + /* Enable PLL */ + temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp |= PORT_PLL_ENABLE; + I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); + POSTING_READ(BXT_PORT_PLL_ENABLE(port)); + + if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & + PORT_PLL_LOCK), 200)) + DRM_ERROR("PLL %d not locked\n", port); + + /* + * While we write to the group register to program all lanes at once we + * can read only lane registers and we pick lanes 0/1 for that. + */ + temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); + temp &= ~LANE_STAGGER_MASK; + temp &= ~LANESTAGGER_STRAP_OVRD; + temp |= pll->config.hw_state.pcsdw12; + I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); +} + +static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, + struct intel_shared_dpll *pll) +{ + enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ + uint32_t temp; + + temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp &= ~PORT_PLL_ENABLE; + I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); + POSTING_READ(BXT_PORT_PLL_ENABLE(port)); +} + +static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, + struct intel_shared_dpll *pll, + struct intel_dpll_hw_state *hw_state) +{ + enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ + uint32_t val; + + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) + return false; + + val = I915_READ(BXT_PORT_PLL_ENABLE(port)); + if (!(val & PORT_PLL_ENABLE)) + return false; + + hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); + hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); + hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); + hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); + hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); + hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); + hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); + /* + * While we write to the group register to program all lanes at once we + * can read only lane registers. We configure all lanes the same way, so + * here just read out lanes 0/1 and output a note if lanes 2/3 differ. + */ + hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); + if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12)) + DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", + hw_state->pcsdw12, + I915_READ(BXT_PORT_PCS_DW12_LN23(port))); + + return true; +} + +static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) +{ + int i; + + dev_priv->num_shared_dpll = 3; + + for (i = 0; i < dev_priv->num_shared_dpll; i++) { + dev_priv->shared_dplls[i].id = i; + dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; + dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; + dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; + dev_priv->shared_dplls[i].get_hw_state = + bxt_ddi_pll_get_hw_state; + } +} + void intel_ddi_pll_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -1997,6 +2160,8 @@ void intel_ddi_pll_init(struct drm_device *dev) if (IS_SKYLAKE(dev)) skl_shared_dplls_init(dev_priv); + else if (IS_BROXTON(dev)) + bxt_shared_dplls_init(dev_priv); else hsw_shared_dplls_init(dev_priv); -- cgit v1.2.3 From 5ab7b0b71e00d5ebfab35f4535e437eb88105d20 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Mar 2015 03:29:25 +0200 Subject: drm/i915/bxt: add bxt_find_best_dpll Signed-off-by: Imre Deak Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/intel_drv.h | 2 ++ 2 files changed, 31 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3322e5a12e8e..ef58a775373e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -105,6 +105,8 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc); static void intel_finish_crtc_commit(struct drm_crtc *crtc); static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state); +static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, + int num_connectors); static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) { @@ -402,6 +404,18 @@ static const intel_limit_t intel_limits_chv = { .p2 = { .p2_slow = 1, .p2_fast = 14 }, }; +static const intel_limit_t intel_limits_bxt = { + /* FIXME: find real dot limits */ + .dot = { .min = 0, .max = INT_MAX }, + .vco = { .min = 4800000, .max = 6480000 }, + .n = { .min = 1, .max = 1 }, + .m1 = { .min = 2, .max = 2 }, + /* FIXME: find real m2 limits */ + .m2 = { .min = 2 << 22, .max = 255 << 22 }, + .p1 = { .min = 2, .max = 4 }, + .p2 = { .p2_slow = 1, .p2_fast = 20 }, +}; + static void vlv_clock(int refclk, intel_clock_t *clock) { clock->m = clock->m1 * clock->m2; @@ -513,7 +527,9 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk) struct drm_device *dev = crtc_state->base.crtc->dev; const intel_limit_t *limit; - if (HAS_PCH_SPLIT(dev)) + if (IS_BROXTON(dev)) + limit = &intel_limits_bxt; + else if (HAS_PCH_SPLIT(dev)) limit = intel_ironlake_limit(crtc_state, refclk); else if (IS_G4X(dev)) { limit = intel_g4x_limit(crtc_state); @@ -598,11 +614,11 @@ static bool intel_PLL_is_valid(struct drm_device *dev, if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) INTELPllInvalid("m1 out of range\n"); - if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) + if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) if (clock->m1 <= clock->m2) INTELPllInvalid("m1 <= m2\n"); - if (!IS_VALLEYVIEW(dev)) { + if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { if (clock->p < limit->p.min || limit->p.max < clock->p) INTELPllInvalid("p out of range\n"); if (clock->m < limit->m.min || limit->m.max < clock->m) @@ -955,6 +971,15 @@ chv_find_best_dpll(const intel_limit_t *limit, return found; } +bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, + intel_clock_t *best_clock) +{ + int refclk = i9xx_get_refclk(crtc_state, 0); + + return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, + target_clock, refclk, NULL, best_clock); +} + bool intel_crtc_active(struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); @@ -6574,7 +6599,7 @@ static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, WARN_ON(!crtc_state->base.state); - if (IS_VALLEYVIEW(dev)) { + if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { refclk = 100000; } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 1cad3ddaf3c7..d7436cbac873 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1126,6 +1126,8 @@ int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, int dotclock); +bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, + intel_clock_t *best_clock); bool intel_crtc_active(struct drm_crtc *crtc); void hsw_enable_ips(struct intel_crtc *crtc); void hsw_disable_ips(struct intel_crtc *crtc); -- cgit v1.2.3 From d683f3bc48655d71b36a8e18babae3036823c44e Mon Sep 17 00:00:00 2001 From: Satheeshakrishna M Date: Fri, 22 Aug 2014 09:49:08 +0530 Subject: drm/i915/bxt: BXT clock divider calculation Calculate and cache clock parameters. Follow bspec algorithm for HDMI. Use precalculated values for DisplayPort linkrates. v2: (imre) - rebase against upstream crtc_state change - use the existing CHV based helper instead of handrolling the same Signed-off-by: Satheeshakrishna M (v1) Signed-off-by: Imre Deak Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 129 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index a6d0cb0b10fc..471631e5ea00 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1212,6 +1212,132 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc, return true; } +/* bxt clock parameters */ +struct bxt_clk_div { + uint32_t p1; + uint32_t p2; + uint32_t m2_int; + uint32_t m2_frac; + bool m2_frac_en; + uint32_t n; + uint32_t prop_coef; + uint32_t int_coef; + uint32_t gain_ctl; + uint32_t targ_cnt; + uint32_t lanestagger; +}; + +/* pre-calculated values for DP linkrates */ +static struct bxt_clk_div bxt_dp_clk_val[7] = { + /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, + /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd}, + /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18}, + /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, + /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd}, + /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, + /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18} +}; + +static bool +bxt_ddi_pll_select(struct intel_crtc *intel_crtc, + struct intel_crtc_state *crtc_state, + struct intel_encoder *intel_encoder, + int clock) +{ + struct intel_shared_dpll *pll; + struct bxt_clk_div clk_div = {0}; + + if (intel_encoder->type == INTEL_OUTPUT_HDMI) { + intel_clock_t best_clock; + + /* Calculate HDMI div */ + /* + * FIXME: tie the following calculation into + * i9xx_crtc_compute_clock + */ + if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { + DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", + clock, pipe_name(intel_crtc->pipe)); + return false; + } + + clk_div.p1 = best_clock.p1; + clk_div.p2 = best_clock.p2; + WARN_ON(best_clock.m1 != 2); + clk_div.n = best_clock.n; + clk_div.m2_int = best_clock.m2 >> 22; + clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); + clk_div.m2_frac_en = clk_div.m2_frac != 0; + + /* FIXME: set coef, gain, targcnt based on freq band */ + clk_div.prop_coef = 5; + clk_div.int_coef = 11; + clk_div.gain_ctl = 2; + clk_div.targ_cnt = 9; + if (clock > 270000) + clk_div.lanestagger = 0x18; + else if (clock > 135000) + clk_div.lanestagger = 0x0d; + else if (clock > 67000) + clk_div.lanestagger = 0x07; + else if (clock > 33000) + clk_div.lanestagger = 0x04; + else + clk_div.lanestagger = 0x02; + } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || + intel_encoder->type == INTEL_OUTPUT_EDP) { + struct drm_encoder *encoder = &intel_encoder->base; + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + switch (intel_dp->link_bw) { + case DP_LINK_BW_1_62: + clk_div = bxt_dp_clk_val[0]; + break; + case DP_LINK_BW_2_7: + clk_div = bxt_dp_clk_val[1]; + break; + case DP_LINK_BW_5_4: + clk_div = bxt_dp_clk_val[2]; + break; + default: + clk_div = bxt_dp_clk_val[0]; + DRM_ERROR("Unknown link rate\n"); + } + } + + crtc_state->dpll_hw_state.ebb0 = + PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); + crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; + crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); + crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; + + if (clk_div.m2_frac_en) + crtc_state->dpll_hw_state.pll3 = + PORT_PLL_M2_FRAC_ENABLE; + + crtc_state->dpll_hw_state.pll6 = + clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef); + crtc_state->dpll_hw_state.pll6 |= + PORT_PLL_GAIN_CTL(clk_div.gain_ctl); + + crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt; + + crtc_state->dpll_hw_state.pcsdw12 = + LANESTAGGER_STRAP_OVRD | clk_div.lanestagger; + + pll = intel_get_shared_dpll(intel_crtc, crtc_state); + if (pll == NULL) { + DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", + pipe_name(intel_crtc->pipe)); + return false; + } + + /* shared DPLL id 0 is DPLL A */ + crtc_state->ddi_pll_sel = pll->id; + + return true; +} + /* * Tries to find a *shared* PLL for the CRTC and store it in * intel_crtc->ddi_pll_sel. @@ -1230,6 +1356,9 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, if (IS_SKYLAKE(dev)) return skl_ddi_pll_select(intel_crtc, crtc_state, intel_encoder, clock); + else if (IS_BROXTON(dev)) + return bxt_ddi_pll_select(intel_crtc, crtc_state, + intel_encoder, clock); else return hsw_ddi_pll_select(intel_crtc, crtc_state, intel_encoder, clock); -- cgit v1.2.3 From bcddf61077592ad9f670502858491ad2788856ef Mon Sep 17 00:00:00 2001 From: Satheeshakrishna M Date: Fri, 22 Aug 2014 09:49:10 +0530 Subject: drm/i915/bxt: Assign PLL for pipe Assign PLL for pipe (dependent on port attached to the pipe) v2: - fix incorrect encoder vs. new_encoder check for crtc (imre) v3: - warn and return error if no encoder is attached (imre) Signed-off-by: Satheeshakrishna M (v2) Signed-off-by: Imre Deak Reviewed-by: Jesse Barnes [danvet: Don't move intel_ddi_get_crtc_new_encoder around.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ 3 files changed, 23 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 471631e5ea00..404cef053688 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -493,7 +493,7 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) return ret; } -static struct intel_encoder * +struct intel_encoder * intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ef58a775373e..c51565a0f2aa 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4209,6 +4209,26 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, goto found; } + if (IS_BROXTON(dev_priv->dev)) { + /* PLL is attached to port in bxt */ + struct intel_encoder *encoder; + struct intel_digital_port *intel_dig_port; + + encoder = intel_ddi_get_crtc_new_encoder(crtc_state); + if (WARN_ON(!encoder)) + return NULL; + + intel_dig_port = enc_to_dig_port(&encoder->base); + /* 1:1 mapping between ports and PLLs */ + i = (enum intel_dpll_id)intel_dig_port->port; + pll = &dev_priv->shared_dplls[i]; + DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", + crtc->base.base.id, pll->name); + WARN_ON(pll->new_config->crtc_mask); + + goto found; + } + for (i = 0; i < dev_priv->num_shared_dpll; i++) { pll = &dev_priv->shared_dplls[i]; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d7436cbac873..7e11a54f0d46 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -936,6 +936,8 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); void intel_ddi_fdi_disable(struct drm_crtc *crtc); void intel_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config); +struct intel_encoder * +intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); void intel_ddi_clock_get(struct intel_encoder *encoder, -- cgit v1.2.3 From 3760b59cba7d592e0ed70cb64291f0403b12f805 Mon Sep 17 00:00:00 2001 From: Satheeshakrishna M Date: Fri, 22 Aug 2014 09:49:11 +0530 Subject: drm/i915/bxt: Determine PLL attached to pipe Determine PLL attached to pipe (which is same as DDI PLL) v2: - rebased on upstream s/crtc_config/crtc_state/ (imre) Signed-off-by: Satheeshakrishna M (v1) Signed-off-by: Imre Deak Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c51565a0f2aa..278f80760d57 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9096,6 +9096,28 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc, return 0; } +static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, + enum port port, + struct intel_crtc_state *pipe_config) +{ + switch (port) { + case PORT_A: + pipe_config->ddi_pll_sel = SKL_DPLL0; + pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; + break; + case PORT_B: + pipe_config->ddi_pll_sel = SKL_DPLL1; + pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; + break; + case PORT_C: + pipe_config->ddi_pll_sel = SKL_DPLL2; + pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; + break; + default: + DRM_ERROR("Incorrect port type\n"); + } +} + static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, struct intel_crtc_state *pipe_config) @@ -9158,6 +9180,8 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, if (IS_SKYLAKE(dev)) skylake_get_ddi_pll(dev_priv, port, pipe_config); + else if (IS_BROXTON(dev)) + bxt_get_ddi_pll(dev_priv, port, pipe_config); else haswell_get_ddi_pll(dev_priv, port, pipe_config); -- cgit v1.2.3 From 977bb38d2dc5a4bcfb8841131e5e44d0463f3411 Mon Sep 17 00:00:00 2001 From: Satheeshakrishna M Date: Fri, 22 Aug 2014 09:49:12 +0530 Subject: drm/i915/bxt: Determine programmed frequency Add placeholder function for calculating programmed pixel clock. Note: Formula to back calculate link clock from dividers not available currently. v2: - rebased on upstream s/crtc_config/crtc_state/ change (imre) Signed-off-by: Satheeshakrishna M (v1) Signed-off-by: Imre Deak Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 30 +++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_dp.c | 2 ++ 2 files changed, 31 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 404cef053688..f9f55bc05e7d 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -880,6 +880,32 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder, pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; } +static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, + enum intel_dpll_id dpll) +{ + /* FIXME formula not available in bspec */ + return 0; +} + +static void bxt_ddi_clock_get(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + enum port port = intel_ddi_get_encoder_port(encoder); + uint32_t dpll = port; + + pipe_config->port_clock = + bxt_calc_pll_link(dev_priv, dpll); + + if (pipe_config->has_dp_encoder) + pipe_config->base.adjusted_mode.crtc_clock = + intel_dotclock_calculate(pipe_config->port_clock, + &pipe_config->dp_m_n); + else + pipe_config->base.adjusted_mode.crtc_clock = + pipe_config->port_clock; +} + void intel_ddi_clock_get(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { @@ -887,8 +913,10 @@ void intel_ddi_clock_get(struct intel_encoder *encoder, if (INTEL_INFO(dev)->gen <= 8) hsw_ddi_clock_get(encoder, pipe_config); - else + else if (IS_SKYLAKE(dev)) skl_ddi_clock_get(encoder, pipe_config); + else if (IS_BROXTON(dev)) + bxt_ddi_clock_get(encoder, pipe_config); } static void diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3ea68e164873..550ac9be1f58 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1471,6 +1471,8 @@ found: if (IS_SKYLAKE(dev) && is_edp(intel_dp)) skl_edp_set_pll_config(pipe_config, common_rates[clock]); + else if (IS_BROXTON(dev)) + /* handled in ddi */; else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); else -- cgit v1.2.3 From 503604038b739b244781904113a377385a341937 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 16 Jan 2015 00:55:16 -0800 Subject: drm/i915: suppress false PLL state warnings on non-GMCH platforms The checks for PLL enabled state on CPU ports are valid only on GMCH platforms but atm we'd also call them on non-PCH-split/non-GMCH platforms like BXT, triggering false warnings. Until the proper check is implented for these platforms simply disable the check. Signed-off-by: Imre Deak Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 278f80760d57..be69e84399a4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2131,7 +2131,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) * a plane. On ILK+ the pipe PLLs are integrated, so we don't * need the check. */ - if (!HAS_PCH_SPLIT(dev_priv->dev)) + if (HAS_GMCH_DISPLAY(dev_priv->dev)) if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) assert_dsi_pll_enabled(dev_priv); else @@ -4666,7 +4666,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc) if (!crtc->state->enable || !intel_crtc->active) return; - if (!HAS_PCH_SPLIT(dev_priv->dev)) { + if (HAS_GMCH_DISPLAY(dev_priv->dev)) { if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) assert_dsi_pll_enabled(dev_priv); else -- cgit v1.2.3 From b403745c84592b26a0713e6944c2b109f6df5c82 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Mon, 4 Aug 2014 22:01:33 +0100 Subject: drm/i915: Iterate through the initialized DDIs to prepare their buffers Not every DDIs is necessarily connected can be strapped off and, in the future, we'll have platforms with a different number of default DDI ports. So, let's only call intel_prepare_ddi_buffers() on DDI ports that are actually detected. We also use the opportunity to give a struct intel_digital_port to intel_prepare_ddi_buffers() as we'll need it in a following patch to query if the port supports HMDI or not. On my HSW machine this removes the initialization of a couple of (unused) DDIs. Signed-off-by: Damien Lespiau Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 4 ++++ drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a7049ea164e2..fd72f3f0cf84 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -251,6 +251,10 @@ enum hpd_pin { &dev->mode_config.connector_list, \ base.head) +#define for_each_digital_port(dev, digital_port) \ + list_for_each_entry(digital_port, \ + &dev->mode_config.encoder_list, \ + base.base.head) #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index f9f55bc05e7d..e0b618851a53 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -198,10 +198,12 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) * in either FDI or DP modes only, as HDMI connections will work with both * of those */ -static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) +static void intel_prepare_ddi_buffers(struct drm_device *dev, + struct intel_digital_port *intel_dig_port) { struct drm_i915_private *dev_priv = dev->dev_private; u32 reg; + int port = intel_dig_port->port; int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, size; int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; @@ -309,13 +311,19 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) */ void intel_prepare_ddi(struct drm_device *dev) { - int port; + struct intel_digital_port *intel_dig_port; + bool visited[I915_MAX_PORTS] = { 0, }; if (!HAS_DDI(dev)) return; - for (port = PORT_A; port <= PORT_E; port++) - intel_prepare_ddi_buffers(dev, port); + for_each_digital_port(dev, intel_dig_port) { + if (visited[intel_dig_port->port]) + continue; + + intel_prepare_ddi_buffers(dev, intel_dig_port); + visited[intel_dig_port->port] = true; + } } static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, -- cgit v1.2.3 From ce3b7e9bcfdc2d255d9ab1a0e1f76d8b0912b8a4 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Mon, 4 Aug 2014 15:04:43 +0100 Subject: drm/i915: Don't write the HDMI buffer translation entry when not needed We don't actually need to write the HDMI entry on DDIs that have no chance to be used as HDMI ports. While this patch shouldn't change the current behaviour, it makes further enabling work easier as we'll have an eDP table filling the full 10 entries. v2: Rely on the logic from intel_ddi_init() to figure out if the DDI port supports HDMI or not (Paulo). Suggested-by: Satheeshakrishna M Signed-off-by: Damien Lespiau Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index e0b618851a53..43b38d76761c 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -191,6 +191,12 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) } } +static bool +intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) +{ + return intel_dig_port->hdmi.hdmi_reg; +} + /* * Starting with Haswell, DDI port buffers must be programmed with correct * values in advance. The buffer values are different for FDI and DP modes, @@ -294,6 +300,9 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, reg += 4; } + if (!intel_dig_port_supports_hdmi(intel_dig_port)) + return; + /* Choose a good default if VBT is badly populated */ if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || hdmi_level >= n_hdmi_entries) -- cgit v1.2.3 From 96fb9f9b154a8dbfe1f74c384cd82f73539fda93 Mon Sep 17 00:00:00 2001 From: Vandana Kannan Date: Tue, 18 Nov 2014 15:45:27 +0530 Subject: drm/i915/bxt: VSwing programming sequence VSwing programming sequence as specified in the updated BXT BSpec v2: Satheesh's review comments addressed. - clear value before setting into registers - move print statement to bxt function Other changes - since signal level will not be set into DDI_BUF_CTL, the value need not be returned to intel_dp_set_signal_levels(). Making the bxt specific function to return void and setting signal_levels = 0 for bxt inside intel_dp_set_signal_levels() - instead of signal levels, printing vswing level and pre-emphasis level - in case none of the pre-emphasis levels or vswing levels are set, setting default of 400mV + 0dB v3: Satheesh's review comments - Check for mask before printing signal_levels. - Removing redundant register writes - Call intel_prepare_ddi_buffers only for HAS_PCH_SPLIT - Making register write part generic as it will be required for HDMI as well. Re-structure the code to include an array for vswing related values, set signal levels v4: Satheesh's review comments - Rebase over latest renaming patches - use hsw_signal_levels for HAS_DDI Other changes - Modified vswing_sequence() func definition - Rebased on top of register macro definitions v5: Satheesh's review comments - Check ddi translation table size v6: Imre's review comments - removed comments in vswing sequence - added vswing, pre-emphasis prints in intel_dp_set_signal_levels - added comment explaining use of DP vswing values for eDP - initialize n_entries and ddi_transaltion table based on encoder type - create bxt_ddi_buf_trans structure and use decimal values - adding a flag in bxt buffer translation table to indicate def entry v7: (imre) - squash in Vandana's "VSwing register definition", "HDMI VSwing programming", "Re-enable vswing programming", "Fix vswing sequence" patches - use BXT_PORT_* regs directly instead of via a temp var - simplify BXT_PORT_* macro definitions - add code comment why we read lane while write group registers - fix readout of DP_TRAIN_PRE_EMPHASIS in debug message Signed-off-by: Vandana Kannan (v6) Signed-off-by: Imre Deak Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 61 ++++++++++++++++++++ drivers/gpu/drm/i915/intel_ddi.c | 120 ++++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_dp.c | 64 ++++++++++++++++++++- drivers/gpu/drm/i915/intel_drv.h | 2 + 4 files changed, 244 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5c81728e4400..d47afbc97a21 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1260,6 +1260,21 @@ enum skl_disp_power_wells { _PORT_REF_DW8_A) /* BXT PHY PCS registers */ +#define _PORT_PCS_DW10_LN01_A 0x162428 +#define _PORT_PCS_DW10_LN01_B 0x6C428 +#define _PORT_PCS_DW10_LN01_C 0x6C828 +#define _PORT_PCS_DW10_GRP_A 0x162C28 +#define _PORT_PCS_DW10_GRP_B 0x6CC28 +#define _PORT_PCS_DW10_GRP_C 0x6CE28 +#define BXT_PORT_PCS_DW10_LN01(port) _PORT3(port, _PORT_PCS_DW10_LN01_A, \ + _PORT_PCS_DW10_LN01_B, \ + _PORT_PCS_DW10_LN01_C) +#define BXT_PORT_PCS_DW10_GRP(port) _PORT3(port, _PORT_PCS_DW10_GRP_A, \ + _PORT_PCS_DW10_GRP_B, \ + _PORT_PCS_DW10_GRP_C) +#define TX2_SWING_CALC_INIT (1 << 31) +#define TX1_SWING_CALC_INIT (1 << 30) + #define _PORT_PCS_DW12_LN01_A 0x162430 #define _PORT_PCS_DW12_LN01_B 0x6C430 #define _PORT_PCS_DW12_LN01_C 0x6C830 @@ -1285,6 +1300,52 @@ enum skl_disp_power_wells { #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ ((lane) & 1) * 0x80) +#define _PORT_TX_DW2_LN0_A 0x162508 +#define _PORT_TX_DW2_LN0_B 0x6C508 +#define _PORT_TX_DW2_LN0_C 0x6C908 +#define _PORT_TX_DW2_GRP_A 0x162D08 +#define _PORT_TX_DW2_GRP_B 0x6CD08 +#define _PORT_TX_DW2_GRP_C 0x6CF08 +#define BXT_PORT_TX_DW2_GRP(port) _PORT3(port, _PORT_TX_DW2_GRP_A, \ + _PORT_TX_DW2_GRP_B, \ + _PORT_TX_DW2_GRP_C) +#define BXT_PORT_TX_DW2_LN0(port) _PORT3(port, _PORT_TX_DW2_LN0_A, \ + _PORT_TX_DW2_LN0_B, \ + _PORT_TX_DW2_LN0_C) +#define MARGIN_000_SHIFT 16 +#define MARGIN_000 (0xFF << MARGIN_000_SHIFT) +#define UNIQ_TRANS_SCALE_SHIFT 8 +#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) + +#define _PORT_TX_DW3_LN0_A 0x16250C +#define _PORT_TX_DW3_LN0_B 0x6C50C +#define _PORT_TX_DW3_LN0_C 0x6C90C +#define _PORT_TX_DW3_GRP_A 0x162D0C +#define _PORT_TX_DW3_GRP_B 0x6CD0C +#define _PORT_TX_DW3_GRP_C 0x6CF0C +#define BXT_PORT_TX_DW3_GRP(port) _PORT3(port, _PORT_TX_DW3_GRP_A, \ + _PORT_TX_DW3_GRP_B, \ + _PORT_TX_DW3_GRP_C) +#define BXT_PORT_TX_DW3_LN0(port) _PORT3(port, _PORT_TX_DW3_LN0_A, \ + _PORT_TX_DW3_LN0_B, \ + _PORT_TX_DW3_LN0_C) +#define UNIQE_TRANGE_EN_METHOD (1 << 27) + +#define _PORT_TX_DW4_LN0_A 0x162510 +#define _PORT_TX_DW4_LN0_B 0x6C510 +#define _PORT_TX_DW4_LN0_C 0x6C910 +#define _PORT_TX_DW4_GRP_A 0x162D10 +#define _PORT_TX_DW4_GRP_B 0x6CD10 +#define _PORT_TX_DW4_GRP_C 0x6CF10 +#define BXT_PORT_TX_DW4_LN0(port) _PORT3(port, _PORT_TX_DW4_LN0_A, \ + _PORT_TX_DW4_LN0_B, \ + _PORT_TX_DW4_LN0_C) +#define BXT_PORT_TX_DW4_GRP(port) _PORT3(port, _PORT_TX_DW4_GRP_A, \ + _PORT_TX_DW4_GRP_B, \ + _PORT_TX_DW4_GRP_C) +#define DEEMPH_SHIFT 24 +#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) + #define _PORT_TX_DW14_LN0_A 0x162538 #define _PORT_TX_DW14_LN0_B 0x6C538 #define _PORT_TX_DW14_LN0_C 0x6C938 diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 43b38d76761c..455d44b49c66 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -168,6 +168,48 @@ static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { { 0x00000018, 0x000000c7 }, }; +struct bxt_ddi_buf_trans { + u32 margin; /* swing value */ + u32 scale; /* scale value */ + u32 enable; /* scale enable */ + u32 deemphasis; + bool default_index; /* true if the entry represents default value */ +}; + +/* BSpec does not define separate vswing/pre-emphasis values for eDP. + * Using DP values for eDP as well. + */ +static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { + /* Idx NT mV diff db */ + { 52, 0, 0, 128, true }, /* 0: 400 0 */ + { 78, 0, 0, 85, false }, /* 1: 400 3.5 */ + { 104, 0, 0, 64, false }, /* 2: 400 6 */ + { 154, 0, 0, 43, false }, /* 3: 400 9.5 */ + { 77, 0, 0, 128, false }, /* 4: 600 0 */ + { 116, 0, 0, 85, false }, /* 5: 600 3.5 */ + { 154, 0, 0, 64, false }, /* 6: 600 6 */ + { 102, 0, 0, 128, false }, /* 7: 800 0 */ + { 154, 0, 0, 85, false }, /* 8: 800 3.5 */ + { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ +}; + +/* BSpec has 2 recommended values - entries 0 and 8. + * Using the entry with higher vswing. + */ +static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { + /* Idx NT mV diff db */ + { 52, 0, 0, 128, false }, /* 0: 400 0 */ + { 52, 0, 0, 85, false }, /* 1: 400 3.5 */ + { 52, 0, 0, 64, false }, /* 2: 400 6 */ + { 42, 0, 0, 43, false }, /* 3: 400 9.5 */ + { 77, 0, 0, 128, false }, /* 4: 600 0 */ + { 77, 0, 0, 85, false }, /* 5: 600 3.5 */ + { 77, 0, 0, 64, false }, /* 6: 600 6 */ + { 102, 0, 0, 128, false }, /* 7: 800 0 */ + { 102, 0, 0, 85, false }, /* 8: 800 3.5 */ + { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ +}; + enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) { struct drm_encoder *encoder = &intel_encoder->base; @@ -219,7 +261,15 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, const struct ddi_buf_trans *ddi_translations_hdmi; const struct ddi_buf_trans *ddi_translations; - if (IS_SKYLAKE(dev)) { + if (IS_BROXTON(dev)) { + if (!intel_dig_port_supports_hdmi(intel_dig_port)) + return; + + /* Vswing programming for HDMI */ + bxt_ddi_vswing_sequence(dev, hdmi_level, port, + INTEL_OUTPUT_HDMI); + return; + } else if (IS_SKYLAKE(dev)) { ddi_translations_fdi = NULL; ddi_translations_dp = skl_ddi_translations_dp; n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp); @@ -1695,6 +1745,67 @@ void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) TRANS_CLK_SEL_DISABLED); } +void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, + enum port port, int type) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + const struct bxt_ddi_buf_trans *ddi_translations; + u32 n_entries, i; + uint32_t val; + + if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { + n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); + ddi_translations = bxt_ddi_translations_dp; + } else if (type == INTEL_OUTPUT_HDMI) { + n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); + ddi_translations = bxt_ddi_translations_hdmi; + } else { + DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", + type); + return; + } + + /* Check if default value has to be used */ + if (level >= n_entries || + (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { + for (i = 0; i < n_entries; i++) { + if (ddi_translations[i].default_index) { + level = i; + break; + } + } + } + + /* + * While we write to the group register to program all lanes at once we + * can read only lane registers and we pick lanes 0/1 for that. + */ + val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); + val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); + I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); + + val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); + val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); + val |= ddi_translations[level].margin << MARGIN_000_SHIFT | + ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; + I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); + + val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); + val &= ~UNIQE_TRANGE_EN_METHOD; + if (ddi_translations[level].enable) + val |= UNIQE_TRANGE_EN_METHOD; + I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); + + val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); + val &= ~DE_EMPHASIS; + val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; + I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); + + val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); + val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; + I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); +} + static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) { struct drm_encoder *encoder = &intel_encoder->base; @@ -1703,6 +1814,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); enum port port = intel_ddi_get_encoder_port(intel_encoder); int type = intel_encoder->type; + int hdmi_level; if (type == INTEL_OUTPUT_EDP) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -1759,6 +1871,12 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) } else if (type == INTEL_OUTPUT_HDMI) { struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); + if (IS_BROXTON(dev)) { + hdmi_level = dev_priv->vbt. + ddi_port_info[port].hdmi_level_shift; + bxt_ddi_vswing_sequence(dev, hdmi_level, port, + INTEL_OUTPUT_HDMI); + } intel_hdmi->set_infoframes(encoder, crtc->config->has_hdmi_sink, &crtc->config->base.adjusted_mode); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 550ac9be1f58..2e27b5215a36 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3409,6 +3409,55 @@ intel_hsw_signal_levels(uint8_t train_set) } } +static void intel_bxt_signal_levels(struct intel_dp *intel_dp) +{ + struct intel_digital_port *dport = dp_to_dig_port(intel_dp); + enum port port = dport->port; + struct drm_device *dev = dport->base.base.dev; + struct intel_encoder *encoder = &dport->base; + uint8_t train_set = intel_dp->train_set[0]; + uint32_t level = 0; + + int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | + DP_TRAIN_PRE_EMPHASIS_MASK); + switch (signal_levels) { + default: + DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n"); + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: + level = 0; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: + level = 1; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: + level = 2; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: + level = 3; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: + level = 4; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: + level = 5; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: + level = 6; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: + level = 7; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: + level = 8; + break; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: + level = 9; + break; + } + + bxt_ddi_vswing_sequence(dev, level, port, encoder->type); +} + /* Properly updates "DP" with the correct signal levels. */ static void intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) @@ -3419,7 +3468,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) uint32_t signal_levels, mask; uint8_t train_set = intel_dp->train_set[0]; - if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { + if (IS_BROXTON(dev)) { + signal_levels = 0; + intel_bxt_signal_levels(intel_dp); + mask = 0; + } else if (HAS_DDI(dev)) { signal_levels = intel_hsw_signal_levels(train_set); mask = DDI_BUF_EMP_MASK; } else if (IS_CHERRYVIEW(dev)) { @@ -3439,7 +3492,14 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; } - DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); + if (mask) + DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); + + DRM_DEBUG_KMS("Using vswing level %d\n", + train_set & DP_TRAIN_VOLTAGE_SWING_MASK); + DRM_DEBUG_KMS("Using pre-emphasis level %d\n", + (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT); *DP = (*DP & ~mask) | signal_levels; } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 7e11a54f0d46..a7ec87266626 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -943,6 +943,8 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); void intel_ddi_clock_get(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config); void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); +void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, + enum port port, int type); /* intel_frontbuffer.c */ void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, -- cgit v1.2.3 From 9314726b9f7329e223dd279819b42842ab7d413f Mon Sep 17 00:00:00 2001 From: Vandana Kannan Date: Tue, 18 Nov 2014 15:45:29 +0530 Subject: drm/i915/bxt: Update max level of vswing Broxton supports 3 voltage swing levels on all DP ports. Max level of pre-emphasis will be taken care with the existing code. v2: Patch rebased v3: (imre) - keep existing behavior for other platforms - clarify commit message Signed-off-by: Vandana Kannan (v2) Signed-off-by: Imre Deak Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2e27b5215a36..aa13608d27ff 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2887,7 +2887,9 @@ intel_dp_voltage_max(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dev->dev_private; enum port port = dp_to_dig_port(intel_dp)->port; - if (INTEL_INFO(dev)->gen >= 9) { + if (IS_BROXTON(dev)) + return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; + else if (INTEL_INFO(dev)->gen >= 9) { if (dev_priv->vbt.edp_low_vswing && port == PORT_A) return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; -- cgit v1.2.3 From 5829975ce098171b7a4b86a5914929b16980d1bd Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 16 Apr 2015 11:36:52 +0200 Subject: drm/i915/dp: Remove intel_ prefix from hw signal_levels functions intel_ is for generic code bxt_ and friends for platform specific functions. Remove the intel_ prefix to be consistent with our naming. Random OCD bikeshed I've spotted while merging bxt patches. v2: Oops, git add fail. Cc: Imre Deak Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index aa13608d27ff..5a955e33ba13 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2971,7 +2971,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) } } -static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) +static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) { struct drm_device *dev = intel_dp_to_dev(intel_dp); struct drm_i915_private *dev_priv = dev->dev_private; @@ -3071,7 +3071,7 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) return 0; } -static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) +static uint32_t chv_signal_levels(struct intel_dp *intel_dp) { struct drm_device *dev = intel_dp_to_dev(intel_dp); struct drm_i915_private *dev_priv = dev->dev_private; @@ -3278,7 +3278,7 @@ intel_get_adjust_train(struct intel_dp *intel_dp, } static uint32_t -intel_gen4_signal_levels(uint8_t train_set) +gen4_signal_levels(uint8_t train_set) { uint32_t signal_levels = 0; @@ -3317,7 +3317,7 @@ intel_gen4_signal_levels(uint8_t train_set) /* Gen6's DP voltage swing and pre-emphasis control */ static uint32_t -intel_gen6_edp_signal_levels(uint8_t train_set) +gen6_edp_signal_levels(uint8_t train_set) { int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK); @@ -3345,7 +3345,7 @@ intel_gen6_edp_signal_levels(uint8_t train_set) /* Gen7's DP voltage swing and pre-emphasis control */ static uint32_t -intel_gen7_edp_signal_levels(uint8_t train_set) +gen7_edp_signal_levels(uint8_t train_set) { int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK); @@ -3376,7 +3376,7 @@ intel_gen7_edp_signal_levels(uint8_t train_set) /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ static uint32_t -intel_hsw_signal_levels(uint8_t train_set) +hsw_signal_levels(uint8_t train_set) { int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK); @@ -3411,7 +3411,7 @@ intel_hsw_signal_levels(uint8_t train_set) } } -static void intel_bxt_signal_levels(struct intel_dp *intel_dp) +static void bxt_signal_levels(struct intel_dp *intel_dp) { struct intel_digital_port *dport = dp_to_dig_port(intel_dp); enum port port = dport->port; @@ -3472,25 +3472,25 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) if (IS_BROXTON(dev)) { signal_levels = 0; - intel_bxt_signal_levels(intel_dp); + bxt_signal_levels(intel_dp); mask = 0; } else if (HAS_DDI(dev)) { - signal_levels = intel_hsw_signal_levels(train_set); + signal_levels = hsw_signal_levels(train_set); mask = DDI_BUF_EMP_MASK; } else if (IS_CHERRYVIEW(dev)) { - signal_levels = intel_chv_signal_levels(intel_dp); + signal_levels = chv_signal_levels(intel_dp); mask = 0; } else if (IS_VALLEYVIEW(dev)) { - signal_levels = intel_vlv_signal_levels(intel_dp); + signal_levels = vlv_signal_levels(intel_dp); mask = 0; } else if (IS_GEN7(dev) && port == PORT_A) { - signal_levels = intel_gen7_edp_signal_levels(train_set); + signal_levels = gen7_edp_signal_levels(train_set); mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; } else if (IS_GEN6(dev) && port == PORT_A) { - signal_levels = intel_gen6_edp_signal_levels(train_set); + signal_levels = gen6_edp_signal_levels(train_set); mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; } else { - signal_levels = intel_gen4_signal_levels(train_set); + signal_levels = gen4_signal_levels(train_set); mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; } -- cgit v1.2.3 From b3f9d7d7bc5a35664e70fceed906eb35593dc644 Mon Sep 17 00:00:00 2001 From: kbuild test robot Date: Thu, 16 Apr 2015 18:34:06 +0800 Subject: drm/i915: fix semicolon.cocci warnings drivers/gpu/drm/i915/i915_debugfs.c:4850:2-3: Unneeded semicolon Removes unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci CC: Jani Nikula Signed-off-by: Fengguang Wu Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 1bd2ec5a5a57..9c2b9e450799 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4950,7 +4950,7 @@ static int i915_dpcd_show(struct seq_file *m, void *data) } seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); - }; + } return 0; } -- cgit v1.2.3 From c5d5ab7a05bc311dd0e57bdfd925ae4720f77a58 Mon Sep 17 00:00:00 2001 From: Todd Previte Date: Wed, 15 Apr 2015 08:38:38 -0700 Subject: drm/i915: Add automated testing support for Displayport compliance testing Add the skeleton framework for supporting automation for Displayport compliance testing. This patch adds the necessary framework for the source device to appropriately respond to test automation requests from a sink device. V2: - Addressed previous mailing list feedback - Fixed compilation issue (struct members declared in a later patch) - Updated debug messages to be more accurate - Added status checks for the DPCD read/write calls - Removed excess comments and debug messages - Fixed debug message compilation warnings - Fixed compilation issue with missing variables - Updated link training autotest to ACK V3: - Fixed the checks on the DPCD return code to be <= 0 rather than != 0 - Removed extraneous assignment of a NAK return code in the DPCD read failure case - Changed the return in the DPCD read failure case to a goto to the exit point where the status code is written to the sink - Removed FAUX test case since it's deprecated now - Removed the compliance flag assignment in handle_test_request V4: - Moved declaration of type_type here - Removed declaration of test_data (moved to a later patch) - Added reset to 0 for compliance test variables V5: - Moved test_active variable declaration and initialization out of this patch and into the patch where it's used - Changed variable name compliance_testing_active to compliance_test_active to unify the naming convention - Added initialization for compliance_test_type variable Signed-off-by: Todd Previte Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 75 +++++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/intel_drv.h | 3 ++ 2 files changed, 74 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5a955e33ba13..371d1e6129e5 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4039,11 +4039,78 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) return true; } -static void -intel_dp_handle_test_request(struct intel_dp *intel_dp) +static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) +{ + uint8_t test_result = DP_TEST_ACK; + return test_result; +} + +static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) +{ + uint8_t test_result = DP_TEST_NAK; + return test_result; +} + +static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) +{ + uint8_t test_result = DP_TEST_NAK; + return test_result; +} + +static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) +{ + uint8_t test_result = DP_TEST_NAK; + return test_result; +} + +static void intel_dp_handle_test_request(struct intel_dp *intel_dp) { - /* NAK by default */ - drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); + uint8_t response = DP_TEST_NAK; + uint8_t rxdata = 0; + int status = 0; + + intel_dp->compliance_test_type = 0; + intel_dp->aux.i2c_nack_count = 0; + intel_dp->aux.i2c_defer_count = 0; + + status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); + if (status <= 0) { + DRM_DEBUG_KMS("Could not read test request from sink\n"); + goto update_status; + } + + switch (rxdata) { + case DP_TEST_LINK_TRAINING: + DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); + intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; + response = intel_dp_autotest_link_training(intel_dp); + break; + case DP_TEST_LINK_VIDEO_PATTERN: + DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); + intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; + response = intel_dp_autotest_video_pattern(intel_dp); + break; + case DP_TEST_LINK_EDID_READ: + DRM_DEBUG_KMS("EDID test requested\n"); + intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; + response = intel_dp_autotest_edid(intel_dp); + break; + case DP_TEST_LINK_PHY_TEST_PATTERN: + DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); + intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; + response = intel_dp_autotest_phy_pattern(intel_dp); + break; + default: + DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); + break; + } + +update_status: + status = drm_dp_dpcd_write(&intel_dp->aux, + DP_TEST_RESPONSE, + &response, 1); + if (status <= 0) + DRM_DEBUG_KMS("Could not write test response to sink\n"); } static int diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a7ec87266626..23a42a40abae 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -739,6 +739,9 @@ struct intel_dp { bool has_aux_irq, int send_bytes, uint32_t aux_clock_divider); + + /* Displayport compliance testing */ + unsigned long compliance_test_type; }; struct intel_digital_port { -- cgit v1.2.3 From 74ebf294a1dd816bdc248ac733009a8915d59eb5 Mon Sep 17 00:00:00 2001 From: Todd Previte Date: Wed, 15 Apr 2015 08:38:41 -0700 Subject: drm/i915: Add a delay in Displayport AUX transactions for compliance testing The Displayport Link Layer Compliance Testing Specification 1.2 rev 1.1 specifies that repeated AUX transactions after a failure (no response / invalid response) must have a minimum delay of 400us before the resend can occur. Tests 4.2.1.1 and 4.2.1.2 are two tests that require this specifically. Also, the check for DP_AUX_CH_CTL_TIME_OUT_ERROR has been moved out into a separate case. This case just continues with the next iteration of the loop as the HW has already waited the required amount of time. V2: - Changed udelay() to usleep_range() V3: - Removed extraneous check for timeout - Updated comment to reflect this change V4: - Reformatted a comment V5: - Added separate check for HW timeout on AUX transactions. A message is logged upon detection of this case. V6: - Add continue statement to HW timeout detect case - Remove the log message indicating a timeout has been detected (review feedback) V7: - Updated the commit message to remove verbage about the HW timeout case that is no longer valid. Signed-off-by: Todd Previte Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 371d1e6129e5..ae4baf96bb00 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -874,9 +874,18 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_RECEIVE_ERROR); - if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR)) + if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) continue; + + /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 + * 400us delay required for errors and timeouts + * Timeout errors from the HW already meet this + * requirement so skip to next iteration + */ + if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { + usleep_range(400, 500); + continue; + } if (status & DP_AUX_CH_CTL_DONE) break; } -- cgit v1.2.3 From 747552b947e1013276851b6a19a9867a94ff1c4f Mon Sep 17 00:00:00 2001 From: Todd Previte Date: Wed, 15 Apr 2015 08:38:47 -0700 Subject: drm: Fix the 'native defer' message in drm_dp_i2c_do_msg() The debug message is missing a newline at the end and it makes the logs hard to read when a device defers a lot. Simple 2-character fix adds the newline at the end. Signed-off-by: Todd Previte Cc: dri-devel@lists.freedesktop.org Reviewed-by: Paulo Zanoni Reviewed-by: Alex Deucher Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_dp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 71dcbc64ae98..575172ed6c32 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -466,7 +466,7 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) return -EREMOTEIO; case DP_AUX_NATIVE_REPLY_DEFER: - DRM_DEBUG_KMS("native defer"); + DRM_DEBUG_KMS("native defer\n"); /* * We could check for I2C bit rate capabilities and if * available adjust this interval. We could also be -- cgit v1.2.3 From f4f71c7dfc5c989f53a1861f3ac42e24018fad4c Mon Sep 17 00:00:00 2001 From: Deepak S Date: Sat, 28 Mar 2015 15:23:35 +0530 Subject: drm/i915: Re-adjusting rc6 promotional timer for chv After feedback from the hardware team we are changing the RC6 promotional timer to increase the power saving without changing performance. Signed-off-by: Deepak S Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a80bfd565ce4..a7516ed24eee 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5046,8 +5046,8 @@ static void cherryview_enable_rps(struct drm_device *dev) I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); I915_WRITE(GEN6_RC_SLEEP, 0); - /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ - I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); + /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ + I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); /* allows RC6 residency counter to work */ I915_WRITE(VLV_COUNTER_CONTROL, -- cgit v1.2.3 From 097f8261ddda4b1896dd335dec95dedeecfeaa1b Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Thu, 16 Apr 2015 21:11:08 +0800 Subject: drm/i915/audio: remove duplicated include from intel_audio.c Remove duplicated include. Signed-off-by: Wei Yongjun Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_audio.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index 0d5b1cea4715..f72e93a45e11 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -28,7 +28,6 @@ #include #include -#include "intel_drv.h" #include "i915_drv.h" /** -- cgit v1.2.3 From 8a0c39b1621adc0f2f1c25bd44645afeee5c1d99 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 13 Apr 2015 11:50:09 +0100 Subject: drm/i915: Simplify and fix object to display tracking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Purpose of this tracking is to know when to flush the cache between the CPU and the non-coherent display engine. Prior to: commit 121920faf2ccce9aa66a7e2588415c9647b66104 Author: Tvrtko Ursulin Date: Mon Mar 23 11:10:37 2015 +0000 drm/i915/skl: Query display address through a wrapper This worked by a mix of direct flag manipulation and checking for existence of a pinned GGTT VMA. With the introduction of rotated display mappings this approach is no longer correct. New simpler approach is to just keep this count over calls which pin and unpin objects to and from display, at the slight cost of extra space in every bo. (Inspired and extracted code from a larger rework by Chris Wilson.) v2: Remove the limit since it is not well defined. (Chris Wilson, Ville Syrjälä) v3: Commit message corrections. (Chris Wilson) Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson Cc: Chris Wilson Reviewed-by: Joonas Lahtinen Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 3 ++- drivers/gpu/drm/i915/i915_gem.c | 30 ++++++------------------------ 2 files changed, 8 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fd72f3f0cf84..93e9d36c2b68 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1969,7 +1969,6 @@ struct drm_i915_gem_object { * accurate mappable working set. */ unsigned int fault_mappable:1; - unsigned int pin_display:1; /* * Is the object to be mapped as read-only to the GPU @@ -1983,6 +1982,8 @@ struct drm_i915_gem_object { unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; + unsigned int pin_display; + struct sg_table *pages; int pages_pin_count; struct get_page { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f7b8766e09fc..761f1b6b4942 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3914,24 +3914,6 @@ unlock: return ret; } -static bool is_pin_display(struct drm_i915_gem_object *obj) -{ - struct i915_vma *vma; - - vma = i915_gem_obj_to_ggtt(obj); - if (!vma) - return false; - - /* There are 2 sources that pin objects: - * 1. The display engine (scanouts, sprites, cursors); - * 2. Reservations for execbuffer; - * - * We can ignore reservations as we hold the struct_mutex and - * are only called outside of the reservation path. - */ - return vma->pin_count; -} - /* * Prepare buffer for display plane (scanout, cursors, etc). * Can be called from an uninterruptible phase (modesetting) and allows @@ -3944,7 +3926,6 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view) { u32 old_read_domains, old_write_domain; - bool was_pin_display; int ret; if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) { @@ -3956,8 +3937,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, /* Mark the pin_display early so that we account for the * display coherency whilst setting up the cache domains. */ - was_pin_display = obj->pin_display; - obj->pin_display = true; + obj->pin_display++; /* The display engine is not coherent with the LLC cache on gen6. As * a result, we make sure that the pinning that is about to occur is @@ -4001,8 +3981,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, return 0; err_unpin_display: - WARN_ON(was_pin_display != is_pin_display(obj)); - obj->pin_display = was_pin_display; + obj->pin_display--; return ret; } @@ -4010,9 +3989,12 @@ void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view) { + if (WARN_ON(obj->pin_display == 0)) + return; + i915_gem_object_ggtt_unpin_view(obj, view); - obj->pin_display = is_pin_display(obj); + obj->pin_display--; } int -- cgit v1.2.3 From c7e16f22e83775de96bf7585682d2e7be7f1c1dc Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:11 +0200 Subject: drm/i915: Move gen8 clear_range vfunc setup into common code Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 9041f3dfdfb4..1c8ef7c143aa 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -994,6 +994,7 @@ static int gen8_ppgtt_init_common(struct i915_hw_ppgtt *ppgtt, uint64_t size) ppgtt->base.total = size; ppgtt->base.cleanup = gen8_ppgtt_cleanup; ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; + ppgtt->base.clear_range = gen8_ppgtt_clear_range; ppgtt->switch_mm = gen8_mm_switch; @@ -1022,7 +1023,6 @@ static int gen8_aliasing_ppgtt_init(struct i915_hw_ppgtt *ppgtt) } ppgtt->base.allocate_va_range = NULL; - ppgtt->base.clear_range = gen8_ppgtt_clear_range; ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); return 0; @@ -1037,7 +1037,6 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) return ret; ppgtt->base.allocate_va_range = gen8_alloc_va_range; - ppgtt->base.clear_range = gen8_ppgtt_clear_range; return 0; } -- cgit v1.2.3 From 777dc5bb26a5aff916af1b6ee84ed7dc8cac1245 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:12 +0200 Subject: drm/i915: Move vma vfuns to adddress_space They change with the address space and not with each vma, so move them into the right pile of vfuncs. Save 2 pointers per vma and clarifies the code. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 28 ++++++++++++---------------- drivers/gpu/drm/i915/i915_gem_gtt.h | 15 +++++++-------- 3 files changed, 20 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 761f1b6b4942..8698cff03fc1 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3067,7 +3067,7 @@ int i915_vma_unbind(struct i915_vma *vma) trace_i915_vma_unbind(vma); - vma->unbind_vma(vma); + vma->vm->unbind_vma(vma); list_del_init(&vma->mm_list); if (i915_is_ggtt(vma->vm)) { diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 1c8ef7c143aa..290db48faf27 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -995,6 +995,8 @@ static int gen8_ppgtt_init_common(struct i915_hw_ppgtt *ppgtt, uint64_t size) ppgtt->base.cleanup = gen8_ppgtt_cleanup; ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; ppgtt->base.clear_range = gen8_ppgtt_clear_range; + ppgtt->base.unbind_vma = ppgtt_unbind_vma; + ppgtt->base.bind_vma = ppgtt_bind_vma; ppgtt->switch_mm = gen8_mm_switch; @@ -1579,6 +1581,8 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing) ppgtt->base.allocate_va_range = aliasing ? NULL : gen6_alloc_va_range; ppgtt->base.clear_range = gen6_ppgtt_clear_range; ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; + ppgtt->base.unbind_vma = ppgtt_unbind_vma; + ppgtt->base.bind_vma = ppgtt_bind_vma; ppgtt->base.cleanup = gen6_ppgtt_cleanup; ppgtt->base.start = 0; ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; @@ -2573,6 +2577,8 @@ static int gen8_gmch_probe(struct drm_device *dev, dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; + dev_priv->gtt.base.bind_vma = ggtt_bind_vma; + dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; return ret; } @@ -2613,6 +2619,8 @@ static int gen6_gmch_probe(struct drm_device *dev, dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; + dev_priv->gtt.base.bind_vma = ggtt_bind_vma; + dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; return ret; } @@ -2645,6 +2653,8 @@ static int i915_gmch_probe(struct drm_device *dev, dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; + dev_priv->gtt.base.bind_vma = i915_ggtt_bind_vma; + dev_priv->gtt.base.unbind_vma = i915_ggtt_unbind_vma; if (unlikely(dev_priv->gtt.do_idle_maps)) DRM_INFO("applying Ironlake quirks for intel_iommu\n"); @@ -2732,22 +2742,8 @@ __i915_gem_vma_create(struct drm_i915_gem_object *obj, vma->vm = vm; vma->obj = obj; - if (INTEL_INFO(vm->dev)->gen >= 6) { - if (i915_is_ggtt(vm)) { - vma->ggtt_view = *ggtt_view; - - vma->unbind_vma = ggtt_unbind_vma; - vma->bind_vma = ggtt_bind_vma; - } else { - vma->unbind_vma = ppgtt_unbind_vma; - vma->bind_vma = ppgtt_bind_vma; - } - } else { - BUG_ON(!i915_is_ggtt(vm)); + if (i915_is_ggtt(vm)) vma->ggtt_view = *ggtt_view; - vma->unbind_vma = i915_ggtt_unbind_vma; - vma->bind_vma = i915_ggtt_bind_vma; - } list_add_tail(&vma->vma_link, &obj->vma_list); if (!i915_is_ggtt(vm)) @@ -2957,7 +2953,7 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, return ret; } - vma->bind_vma(vma, cache_level, flags); + vma->vm->bind_vma(vma, cache_level, flags); return 0; } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 29de64d1164e..12d0ded0d823 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -196,14 +196,6 @@ struct i915_vma { * bits with absolutely no headroom. So use 4 bits. */ unsigned int pin_count:4; #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf - - /** Unmap an object from an address space. This usually consists of - * setting the valid PTE entries to a reserved scratch page. */ - void (*unbind_vma)(struct i915_vma *vma); - /* Map an object into an address space with the given cache flags. */ - void (*bind_vma)(struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags); }; struct i915_page_table { @@ -281,6 +273,13 @@ struct i915_address_space { uint64_t start, enum i915_cache_level cache_level, u32 flags); void (*cleanup)(struct i915_address_space *vm); + /** Unmap an object from an address space. This usually consists of + * setting the valid PTE entries to a reserved scratch page. */ + void (*unbind_vma)(struct i915_vma *vma); + /* Map an object into an address space with the given cache flags. */ + void (*bind_vma)(struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags); }; /* The Graphics Translation Table is the way in which GEN hardware translates a -- cgit v1.2.3 From 061dd493103f14f768475fa666f39377f41814bb Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:13 +0200 Subject: drm/i915: Clean up aliasing ppgtt correctly on error paths While at it inline the free functions - they don't actually free the ppgtt, just clean up the allocations done for it. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 30 ++++++++++-------------------- 1 file changed, 10 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 290db48faf27..abb11f139d25 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -672,8 +672,10 @@ static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_dev } } -static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) +static void gen8_ppgtt_cleanup(struct i915_address_space *vm) { + struct i915_hw_ppgtt *ppgtt = + container_of(vm, struct i915_hw_ppgtt, base); int i; for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) { @@ -688,14 +690,6 @@ static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); } -static void gen8_ppgtt_cleanup(struct i915_address_space *vm) -{ - struct i915_hw_ppgtt *ppgtt = - container_of(vm, struct i915_hw_ppgtt, base); - - gen8_ppgtt_free(ppgtt); -} - /** * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. * @ppgtt: Master ppgtt structure. @@ -1454,11 +1448,16 @@ unwind_out: return ret; } -static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) +static void gen6_ppgtt_cleanup(struct i915_address_space *vm) { + struct i915_hw_ppgtt *ppgtt = + container_of(vm, struct i915_hw_ppgtt, base); struct i915_page_table *pt; uint32_t pde; + + drm_mm_remove_node(&ppgtt->node); + gen6_for_all_pdes(pt, ppgtt, pde) { if (pt != ppgtt->scratch_pt) unmap_and_free_pt(pt, ppgtt->base.dev); @@ -1468,16 +1467,6 @@ static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) unmap_and_free_pd(&ppgtt->pd, ppgtt->base.dev); } -static void gen6_ppgtt_cleanup(struct i915_address_space *vm) -{ - struct i915_hw_ppgtt *ppgtt = - container_of(vm, struct i915_hw_ppgtt, base); - - drm_mm_remove_node(&ppgtt->node); - - gen6_ppgtt_free(ppgtt); -} - static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) { struct drm_device *dev = ppgtt->base.dev; @@ -2268,6 +2257,7 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev, ret = __hw_ppgtt_init(dev, ppgtt, true); if (ret) { + ppgtt->base.cleanup(&ppgtt->base); kfree(ppgtt); return ret; } -- cgit v1.2.3 From 5c5f645773b6d147bf68c350674dc3ef4f8de83d Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:14 +0200 Subject: drm/i915: Unify aliasing ppgtt handling With the dynamic pagetable alloc code aliasing ppgtt special-cases where again mixed in all over the place with the low-level init code. Extract the va preallocation and clearing again into the common code where aliasing ppgtt gets set up. Note that with this we don't set the size of the aliasing ppgtt to the size of the parent ggtt address space. Which isn't required at all since except for the ppgtt setup/cleanup code no one ever looks at this. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 134 +++++++----------------------------- 1 file changed, 24 insertions(+), 110 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index abb11f139d25..75787f1d2751 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -387,50 +387,6 @@ fail_bitmap: return ERR_PTR(ret); } -/** - * alloc_pt_range() - Allocate a multiple page tables - * @pd: The page directory which will have at least @count entries - * available to point to the allocated page tables. - * @pde: First page directory entry for which we are allocating. - * @count: Number of pages to allocate. - * @dev: DRM device. - * - * Allocates multiple page table pages and sets the appropriate entries in the - * page table structure within the page directory. Function cleans up after - * itself on any failures. - * - * Return: 0 if allocation succeeded. - */ -static int alloc_pt_range(struct i915_page_directory *pd, uint16_t pde, size_t count, - struct drm_device *dev) -{ - int i, ret; - - /* 512 is the max page tables per page_directory on any platform. */ - if (WARN_ON(pde + count > I915_PDES)) - return -EINVAL; - - for (i = pde; i < pde + count; i++) { - struct i915_page_table *pt = alloc_pt_single(dev); - - if (IS_ERR(pt)) { - ret = PTR_ERR(pt); - goto err_out; - } - WARN(pd->page_table[i], - "Leaking page directory entry %d (%p)\n", - i, pd->page_table[i]); - pd->page_table[i] = pt; - } - - return 0; - -err_out: - while (i-- > pde) - unmap_and_free_pt(pd->page_table[i], dev); - return ret; -} - static void unmap_and_free_pd(struct i915_page_directory *pd, struct drm_device *dev) { @@ -971,7 +927,7 @@ err_out: * space. * */ -static int gen8_ppgtt_init_common(struct i915_hw_ppgtt *ppgtt, uint64_t size) +static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) { ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); if (IS_ERR(ppgtt->scratch_pt)) @@ -985,8 +941,9 @@ static int gen8_ppgtt_init_common(struct i915_hw_ppgtt *ppgtt, uint64_t size) gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd); ppgtt->base.start = 0; - ppgtt->base.total = size; + ppgtt->base.total = 1ULL << 32; ppgtt->base.cleanup = gen8_ppgtt_cleanup; + ppgtt->base.allocate_va_range = gen8_alloc_va_range; ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; ppgtt->base.clear_range = gen8_ppgtt_clear_range; ppgtt->base.unbind_vma = ppgtt_unbind_vma; @@ -997,46 +954,6 @@ static int gen8_ppgtt_init_common(struct i915_hw_ppgtt *ppgtt, uint64_t size) return 0; } -static int gen8_aliasing_ppgtt_init(struct i915_hw_ppgtt *ppgtt) -{ - struct drm_device *dev = ppgtt->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - uint64_t start = 0, size = dev_priv->gtt.base.total; - int ret; - - ret = gen8_ppgtt_init_common(ppgtt, dev_priv->gtt.base.total); - if (ret) - return ret; - - /* Aliasing PPGTT has to always work and be mapped because of the way we - * use RESTORE_INHIBIT in the context switch. This will be fixed - * eventually. */ - ret = gen8_alloc_va_range(&ppgtt->base, start, size); - if (ret) { - unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev); - unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); - return ret; - } - - ppgtt->base.allocate_va_range = NULL; - ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); - - return 0; -} - -static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) -{ - int ret; - - ret = gen8_ppgtt_init_common(ppgtt, (1ULL << 32)); - if (ret) - return ret; - - ppgtt->base.allocate_va_range = gen8_alloc_va_range; - - return 0; -} - static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) { struct i915_address_space *vm = &ppgtt->base; @@ -1533,7 +1450,7 @@ static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; } -static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing) +static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) { struct drm_device *dev = ppgtt->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -1556,18 +1473,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing) if (ret) return ret; - if (aliasing) { - /* preallocate all pts */ - ret = alloc_pt_range(&ppgtt->pd, 0, I915_PDES, - ppgtt->base.dev); - - if (ret) { - gen6_ppgtt_cleanup(&ppgtt->base); - return ret; - } - } - - ppgtt->base.allocate_va_range = aliasing ? NULL : gen6_alloc_va_range; + ppgtt->base.allocate_va_range = gen6_alloc_va_range; ppgtt->base.clear_range = gen6_ppgtt_clear_range; ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; ppgtt->base.unbind_vma = ppgtt_unbind_vma; @@ -1583,10 +1489,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing) ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + ppgtt->pd.pd_offset / sizeof(gen6_pte_t); - if (aliasing) - ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); - else - gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); + gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); @@ -1600,8 +1503,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing) return 0; } -static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt, - bool aliasing) +static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -1609,9 +1511,7 @@ static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt, ppgtt->base.scratch = dev_priv->gtt.base.scratch; if (INTEL_INFO(dev)->gen < 8) - return gen6_ppgtt_init(ppgtt, aliasing); - else if (aliasing) - return gen8_aliasing_ppgtt_init(ppgtt); + return gen6_ppgtt_init(ppgtt); else return gen8_ppgtt_init(ppgtt); } @@ -1620,7 +1520,7 @@ int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) struct drm_i915_private *dev_priv = dev->dev_private; int ret = 0; - ret = __hw_ppgtt_init(dev, ppgtt, false); + ret = __hw_ppgtt_init(dev, ppgtt); if (ret == 0) { kref_init(&ppgtt->ref); drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, @@ -2255,13 +2155,27 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev, if (!ppgtt) return -ENOMEM; - ret = __hw_ppgtt_init(dev, ppgtt, true); + ret = __hw_ppgtt_init(dev, ppgtt); + if (ret) { + ppgtt->base.cleanup(&ppgtt->base); + kfree(ppgtt); + return ret; + } + + if (ppgtt->base.allocate_va_range) + ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, + ppgtt->base.total); if (ret) { ppgtt->base.cleanup(&ppgtt->base); kfree(ppgtt); return ret; } + ppgtt->base.clear_range(&ppgtt->base, + ppgtt->base.start, + ppgtt->base.total, + true); + dev_priv->mm.aliasing_ppgtt = ppgtt; } -- cgit v1.2.3 From f329f5f6eb4fad8f2e9c62fe37ec01ae5ce0f212 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:15 +0200 Subject: drm/i915: Move PTE_READ_ONLY to ->pte_encode vfunc It's only used as a flag there, so unconfuse things a bit. Also separate the bind_vma flag space from the pte_encode flag space in the code. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +++++++++------ drivers/gpu/drm/i915/i915_gem_gtt.h | 3 ++- 2 files changed, 11 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 75787f1d2751..4e2caef83772 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1610,14 +1610,16 @@ void i915_ppgtt_release(struct kref *kref) static void ppgtt_bind_vma(struct i915_vma *vma, enum i915_cache_level cache_level, - u32 flags) + u32 unused) { + u32 pte_flags = 0; + /* Currently applicable only to VLV */ if (vma->obj->gt_ro) - flags |= PTE_READ_ONLY; + pte_flags |= PTE_READ_ONLY; vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, - cache_level, flags); + cache_level, pte_flags); } static void ppgtt_unbind_vma(struct i915_vma *vma) @@ -1986,10 +1988,11 @@ static void ggtt_bind_vma(struct i915_vma *vma, struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj = vma->obj; struct sg_table *pages = obj->pages; + u32 pte_flags = 0; /* Currently applicable only to VLV */ if (obj->gt_ro) - flags |= PTE_READ_ONLY; + pte_flags |= PTE_READ_ONLY; if (i915_is_ggtt(vma->vm)) pages = vma->ggtt_view.pages; @@ -2010,7 +2013,7 @@ static void ggtt_bind_vma(struct i915_vma *vma, (cache_level != obj->cache_level)) { vma->vm->insert_entries(vma->vm, pages, vma->node.start, - cache_level, flags); + cache_level, pte_flags); vma->bound |= GLOBAL_BIND; } } @@ -2021,7 +2024,7 @@ static void ggtt_bind_vma(struct i915_vma *vma, struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; appgtt->base.insert_entries(&appgtt->base, pages, vma->node.start, - cache_level, flags); + cache_level, pte_flags); vma->bound |= LOCAL_BIND; } } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 12d0ded0d823..fb0a04aa5363 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -158,7 +158,6 @@ struct i915_vma { /** Flags and address space this VMA is bound to */ #define GLOBAL_BIND (1<<0) #define LOCAL_BIND (1<<1) -#define PTE_READ_ONLY (1<<2) unsigned int bound : 4; /** @@ -261,6 +260,8 @@ struct i915_address_space { gen6_pte_t (*pte_encode)(dma_addr_t addr, enum i915_cache_level level, bool valid, u32 flags); /* Create a valid PTE */ + /* flags for pte_encode */ +#define PTE_READ_ONLY (1<<0) int (*allocate_va_range)(struct i915_address_space *vm, uint64_t start, uint64_t length); -- cgit v1.2.3 From 0229da324d23de67fa4af585b4ef134f721adc84 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 19:01:54 +0200 Subject: drm/i915: Dont clear PIN_GLOBAL in the execbuf pinning fallback PIN_GLOBAL is set only when userspace asked for it, and that is only the case for the gen6 PIPE_CONTROL workaround. We're not allowed to just clear this. The important part of the fallback is to drop the restriction to the mappable range. This issue has been introduced in commit edf4427b8055dc93eb5222d8174b07a75ba24fb5 Author: Chris Wilson Date: Wed Jan 14 11:20:56 2015 +0000 drm/i915: Fallback to using CPU relocations for large batch buffers v2: Chris pointed out that we also miss to set PIN_GLOBAL when the buffer is already bound. Fix this up too. Cc: Chris Wilson Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 48ac5608481e..564425fce1a7 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -586,11 +586,12 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, int ret; flags = 0; + if (entry->flags & EXEC_OBJECT_NEEDS_GTT) + flags |= PIN_GLOBAL; + if (!drm_mm_node_allocated(&vma->node)) { if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) flags |= PIN_GLOBAL | PIN_MAPPABLE; - if (entry->flags & EXEC_OBJECT_NEEDS_GTT) - flags |= PIN_GLOBAL; if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; } @@ -600,7 +601,7 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, only_mappable_for_reloc(entry->flags)) ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, - flags & ~(PIN_GLOBAL | PIN_MAPPABLE)); + flags & ~PIN_MAPPABLE); if (ret) return ret; -- cgit v1.2.3 From 070c1d059f43ce719f4e8a6528c7211197bad3b4 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:17 +0200 Subject: drm/i915: Drop redundant GGTT rebinding Since commit bf3d149b25f67f241735b91a56b7f070bc0a5407 Author: Daniel Vetter Date: Fri Feb 14 14:01:12 2014 +0100 drm/i915: split PIN_GLOBAL out from PIN_MAPPABLE i915_gem_obj_ggtt_pin always binds into the ggtt, but I've forgotten to remove the now redundant additional bind call later on. Fix this up. Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_context.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index e4c57a3981b3..dd5bff657c9c 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -638,7 +638,6 @@ static int do_switch(struct intel_engine_cs *ring, struct intel_context *from = ring->last_context; u32 hw_flags = 0; bool uninitialized = false; - struct i915_vma *vma; int ret, i; if (from != NULL && ring == &dev_priv->ring[RCS]) { @@ -696,16 +695,6 @@ static int do_switch(struct intel_engine_cs *ring, if (ret) goto unpin_out; - vma = i915_gem_obj_to_ggtt(to->legacy_hw_ctx.rcs_state); - if (!(vma->bound & GLOBAL_BIND)) { - ret = i915_vma_bind(vma, - to->legacy_hw_ctx.rcs_state->cache_level, - GLOBAL_BIND); - /* This shouldn't ever fail. */ - if (WARN_ONCE(ret, "GGTT context bind failed!")) - goto unpin_out; - } - if (!to->legacy_hw_ctx.initialized) { hw_flags |= MI_RESTORE_INHIBIT; /* NB: If we inhibit the restore, the context is not allowed to -- cgit v1.2.3 From 7df113e47366e6bbc0dd02c9fa776ae52f4ef5c1 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Fri, 17 Apr 2015 12:49:07 +0100 Subject: drm/i915: Fixup kerneldoc for struct intel_context commit ae6c4806927b8b0781ecc187aa16b10c820fc430 Author: Daniel Vetter Date: Wed Aug 6 15:04:53 2014 +0200 drm/i915: Only track real ppgtt for a context Changed the code but didn't update kerneldoc. Signed-off-by: Tvrtko Ursulin Cc: "Thierry, Michel" Cc: Daniel Vetter Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 93e9d36c2b68..167e0bd79f98 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -774,7 +774,7 @@ struct i915_ctx_hang_stats { * context). * @hang_stats: information about the role of this context in possible GPU * hangs. - * @vm: virtual memory space used by this context. + * @ppgtt: virtual memory space used by this context. * @legacy_hw_ctx: render context backing object and whether it is correctly * initialized (legacy ring submission mechanism only). * @link: link in the global list of contexts. -- cgit v1.2.3 From 396aa4451e865d1e36d6d4e0686a9303c038b606 Mon Sep 17 00:00:00 2001 From: Todd Previte Date: Sat, 18 Apr 2015 00:04:18 -0700 Subject: drm: Fix for DP CTS test 4.2.2.5 - I2C DEFER handling For test 4.2.2.5 to pass per the Link CTS Core 1.2 rev1.1 spec, the source device must attempt at least 7 times to read the EDID when it receives an I2C defer. The normal DRM code makes only 7 retries, regardless of whether or not the response is a native defer or an I2C defer. Test 4.2.2.5 fails since there are native defers interspersed with the I2C defers which results in less than 7 EDID read attempts. The solution is to add the numer of defers to the retry counter when an I2C DEFER is returned such that another read attempt will be made. This situation should normally only occur in compliance testing, however, as a worse case real-world scenario, it would result in 13 attempts ( 6 native defers, 7 I2C defers) for a single transaction to complete. The net result is a slightly slower response to an EDID read that shouldn't significantly impact overall performance. V2: - Added a check on the number of I2C Defers to limit the number of times that the retries variable will be decremented. This is to address review feedback regarding possible infinite loops from misbehaving sink devices. V3: - Fixed the limit value to 7 instead of 8 to get the correct retry count. - Combined the increment of the defer count into the if-statement V4: - Removed i915 tag from subject as the patch is not i915-specific V5: - Updated the for-loop to add the number of i2c defers to the retry counter such that the correct number of retry attempts will be made Signed-off-by: Todd Previte Cc: dri-devel@lists.freedesktop.org Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_dp_helper.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 575172ed6c32..80a02a412607 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -432,7 +432,7 @@ static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) */ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) { - unsigned int retry; + unsigned int retry, defer_i2c; int ret; /* @@ -440,7 +440,7 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) * is required to retry at least seven times upon receiving AUX_DEFER * before giving up the AUX transaction. */ - for (retry = 0; retry < 7; retry++) { + for (retry = 0, defer_i2c = 0; retry < (7 + defer_i2c); retry++) { mutex_lock(&aux->hw_mutex); ret = aux->transfer(aux, msg); mutex_unlock(&aux->hw_mutex); @@ -499,7 +499,13 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) case DP_AUX_I2C_REPLY_DEFER: DRM_DEBUG_KMS("I2C defer\n"); + /* DP Compliance Test 4.2.2.5 Requirement: + * Must have at least 7 retries for I2C defers on the + * transaction to pass this test + */ aux->i2c_defer_count++; + if (defer_i2c < 7) + defer_i2c++; usleep_range(400, 500); continue; -- cgit v1.2.3 From a3c6d686443e912e33cebdf9cd80f94df3ded7b0 Mon Sep 17 00:00:00 2001 From: Josef Holzmayr Date: Thu, 16 Apr 2015 14:16:29 +0200 Subject: DRM: Don't re-poll connector for disconnect DRM probe should not repoll a connector if it is already connected and the DRM_CONNECTOR_POLL_DISCONNECT flag is not set. Signed-off-by: Josef Holzmayr Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_probe_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c index d44437fc42b1..2fb2fbe8c2de 100644 --- a/drivers/gpu/drm/drm_probe_helper.c +++ b/drivers/gpu/drm/drm_probe_helper.c @@ -322,8 +322,6 @@ static void output_poll_execute(struct work_struct *work) if (!connector->polled || connector->polled == DRM_CONNECTOR_POLL_HPD) continue; - repoll = true; - old_status = connector->status; /* if we are connected and don't want to poll for disconnect skip it */ @@ -331,6 +329,8 @@ static void output_poll_execute(struct work_struct *work) !(connector->polled & DRM_CONNECTOR_POLL_DISCONNECT)) continue; + repoll = true; + connector->status = connector->funcs->detect(connector, false); if (old_status != connector->status) { const char *old, *new; -- cgit v1.2.3 From 2ebef630fd283642a11c48c0e0f054c3c5c59e86 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Mon, 20 Apr 2015 16:22:48 +0100 Subject: drm/i915/skl: Support Y tiling in MMIO flips Add Y tiling support to skl_do_mmio_flip. Signed-off-by: Tvrtko Ursulin Cc: Damien Lespiau Cc: Sonika Jindal Cc: Daniel Vetter Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index be69e84399a4..30dfc73ac7b2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10556,23 +10556,34 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) struct drm_device *dev = intel_crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_framebuffer *fb = intel_crtc->base.primary->fb; - struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); - struct drm_i915_gem_object *obj = intel_fb->obj; const enum pipe pipe = intel_crtc->pipe; u32 ctl, stride; ctl = I915_READ(PLANE_CTL(pipe, 0)); ctl &= ~PLANE_CTL_TILED_MASK; - if (obj->tiling_mode == I915_TILING_X) + switch (fb->modifier[0]) { + case DRM_FORMAT_MOD_NONE: + break; + case I915_FORMAT_MOD_X_TILED: ctl |= PLANE_CTL_TILED_X; + break; + case I915_FORMAT_MOD_Y_TILED: + ctl |= PLANE_CTL_TILED_Y; + break; + case I915_FORMAT_MOD_Yf_TILED: + ctl |= PLANE_CTL_TILED_YF; + break; + default: + MISSING_CASE(fb->modifier[0]); + } /* * The stride is either expressed as a multiple of 64 bytes chunks for * linear buffers or in number of tiles for tiled buffers. */ - stride = fb->pitches[0] >> 6; - if (obj->tiling_mode == I915_TILING_X) - stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */ + stride = fb->pitches[0] / + intel_fb_stride_alignment(dev, fb->modifier[0], + fb->pixel_format); /* * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on -- cgit v1.2.3 From 71b7e54f71b899db9f8def67a0e976969384e699 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:18 +0200 Subject: drm/i915: Don't look at pg_dirty_rings for aliasing ppgtt We load the ppgtt ptes once per gpu reset/driver load/resume and that's all that's needed. Note that this only blows up when we're using the allocate_va_range funcs and not the special-purpose ones used. With this change we can get rid of that duplication. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_context.c | 6 ------ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 --- 2 files changed, 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index dd5bff657c9c..6b0962db2cf7 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -575,8 +575,6 @@ static inline bool should_skip_switch(struct intel_engine_cs *ring, struct intel_context *from, struct intel_context *to) { - struct drm_i915_private *dev_priv = ring->dev->dev_private; - if (to->remap_slice) return false; @@ -584,10 +582,6 @@ static inline bool should_skip_switch(struct intel_engine_cs *ring, if (from == to && !test_bit(ring->id, &to->ppgtt->pd_dirty_rings)) return true; - } else if (dev_priv->mm.aliasing_ppgtt) { - if (from == to && !test_bit(ring->id, - &dev_priv->mm.aliasing_ppgtt->pd_dirty_rings)) - return true; } return false; diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 564425fce1a7..1cf3468551a2 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1251,9 +1251,6 @@ i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file, if (ctx->ppgtt) WARN(ctx->ppgtt->pd_dirty_rings & (1<id), "%s didn't clear reload\n", ring->name); - else if (dev_priv->mm.aliasing_ppgtt) - WARN(dev_priv->mm.aliasing_ppgtt->pd_dirty_rings & - (1<id), "%s didn't clear reload\n", ring->name); instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; instp_mask = I915_EXEC_CONSTANTS_MASK; -- cgit v1.2.3 From 9258811c961879450502f767773227f5c0d79120 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:19 +0200 Subject: drm/i915: Don't use atomics for pg_dirty_rings It's already protected by the bkl^Wdev->struct_mutex. While at it realign some related code. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_context.c | 16 ++++++++-------- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 5 ++--- 2 files changed, 10 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 6b0962db2cf7..5a47eb5e3c5d 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -578,11 +578,9 @@ static inline bool should_skip_switch(struct intel_engine_cs *ring, if (to->remap_slice) return false; - if (to->ppgtt) { - if (from == to && !test_bit(ring->id, - &to->ppgtt->pd_dirty_rings)) - return true; - } + if (to->ppgtt && from == to && + !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) + return true; return false; } @@ -668,7 +666,7 @@ static int do_switch(struct intel_engine_cs *ring, goto unpin_out; /* Doing a PD load always reloads the page dirs */ - clear_bit(ring->id, &to->ppgtt->pd_dirty_rings); + to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); } if (ring != &dev_priv->ring[RCS]) { @@ -696,12 +694,14 @@ static int do_switch(struct intel_engine_cs *ring, * space. This means we must enforce that a page table load * occur when this occurs. */ } else if (to->ppgtt && - test_and_clear_bit(ring->id, &to->ppgtt->pd_dirty_rings)) + (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) { hw_flags |= MI_FORCE_RESTORE; + to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring); + } /* We should never emit switch_mm more than once */ WARN_ON(needs_pd_load_pre(ring, to) && - needs_pd_load_post(ring, to, hw_flags)); + needs_pd_load_post(ring, to, hw_flags)); ret = mi_set_context(ring, to, hw_flags); if (ret) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 1cf3468551a2..7f69aa820458 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1248,9 +1248,8 @@ i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file, if (ret) goto error; - if (ctx->ppgtt) - WARN(ctx->ppgtt->pd_dirty_rings & (1<id), - "%s didn't clear reload\n", ring->name); + WARN(ctx->ppgtt && ctx->ppgtt->pd_dirty_rings & (1<id), + "%s didn't clear reload\n", ring->name); instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; instp_mask = I915_EXEC_CONSTANTS_MASK; -- cgit v1.2.3 From cd102a687beed1042824d5fa81c6ba8bfe78e6a4 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:20 +0200 Subject: drm/i915: Remove misleading comment around bind_to_vm It's true that we might need to context switch, but both the signalling and implementation of the same are a few source files away. Remove it. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 8698cff03fc1..b86da6fceb76 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4197,10 +4197,6 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj, bound = vma ? vma->bound : 0; if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { - /* In true PPGTT, bind has possibly changed PDEs, which - * means we must do a context switch before the GPU can - * accurately read some of the VMAs. - */ vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, flags); if (IS_ERR(vma)) -- cgit v1.2.3 From 0875546c5318c85c13d07014af5350e9000bc9e9 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Mon, 20 Apr 2015 09:04:05 -0700 Subject: drm/i915: Fix up the vma aliasing ppgtt binding Currently we have the problem that the decision whether ptes need to be (re)written is splattered all over the codebase. Move all that into i915_vma_bind. This needs a few changes: - Just reuse the PIN_* flags for i915_vma_bind and do the conversion to vma->bound in there to avoid duplicating the conversion code all over. - We need to make binding for EXECBUF (i.e. pick aliasing ppgtt if around) explicit, add PIN_USER for that. - Two callers want to update ptes, give them a PIN_UPDATE for that. Of course we still want to avoid double-binding, but that should be taken care of: - A ppgtt vma will only ever see PIN_USER, so no issue with double-binding. - A ggtt vma with aliasing ppgtt needs both types of binding, and we track that properly now. - A ggtt vma without aliasing ppgtt could be bound twice. In the lower-level ->bind_vma functions hence unconditionally set GLOBAL_BIND when writing the ggtt ptes. There's still a bit room for cleanup, but that's for follow-up patches. v2: Fixup fumbles. v3: s/PIN_EXECBUF/PIN_USER/ for clearer meaning, suggested by Chris. Cc: Chris Wilson Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 11 +++-- drivers/gpu/drm/i915/i915_gem.c | 11 ++--- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 ++-- drivers/gpu/drm/i915/i915_gem_gtt.c | 65 ++++++++++++------------------ 4 files changed, 40 insertions(+), 54 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 167e0bd79f98..906f8851df4c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2645,10 +2645,13 @@ void i915_init_vm(struct drm_i915_private *dev_priv, void i915_gem_free_object(struct drm_gem_object *obj); void i915_gem_vma_destroy(struct i915_vma *vma); -#define PIN_MAPPABLE 0x1 -#define PIN_NONBLOCK 0x2 -#define PIN_GLOBAL 0x4 -#define PIN_OFFSET_BIAS 0x8 +/* Flags used by pin/bind&friends. */ +#define PIN_MAPPABLE (1<<0) +#define PIN_NONBLOCK (1<<1) +#define PIN_GLOBAL (1<<2) +#define PIN_OFFSET_BIAS (1<<3) +#define PIN_USER (1<<4) +#define PIN_UPDATE (1<<5) #define PIN_OFFSET_MASK (~4095) int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index b86da6fceb76..91aade7c9f6d 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3589,8 +3589,7 @@ search_free: goto err_remove_node; trace_i915_vma_bind(vma, flags); - ret = i915_vma_bind(vma, obj->cache_level, - flags & PIN_GLOBAL ? GLOBAL_BIND : 0); + ret = i915_vma_bind(vma, obj->cache_level, flags); if (ret) goto err_finish_gtt; @@ -3816,7 +3815,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, list_for_each_entry(vma, &obj->vma_list, vma_link) if (drm_mm_node_allocated(&vma->node)) { ret = i915_vma_bind(vma, cache_level, - vma->bound & GLOBAL_BIND); + PIN_UPDATE); if (ret) return ret; } @@ -4201,10 +4200,8 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj, flags); if (IS_ERR(vma)) return PTR_ERR(vma); - } - - if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) { - ret = i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND); + } else { + ret = i915_vma_bind(vma, obj->cache_level, flags); if (ret) return ret; } diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 7f69aa820458..cfdc8c6073aa 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -400,10 +400,9 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, * pipe_control writes because the gpu doesn't properly redirect them * through the ppgtt for non_secure batchbuffers. */ if (unlikely(IS_GEN6(dev) && - reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && - !(target_vma->bound & GLOBAL_BIND))) { + reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, - GLOBAL_BIND); + PIN_GLOBAL); if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) return ret; } @@ -585,7 +584,7 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, uint64_t flags; int ret; - flags = 0; + flags = PIN_USER; if (entry->flags & EXEC_OBJECT_NEEDS_GTT) flags |= PIN_GLOBAL; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 4e2caef83772..9e06180e206f 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1748,15 +1748,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) continue; i915_gem_clflush_object(obj, obj->pin_display); - /* The bind_vma code tries to be smart about tracking mappings. - * Unfortunately above, we've just wiped out the mappings - * without telling our object about it. So we need to fake it. - * - * Bind is not expected to fail since this is only called on - * resume and assumption is all requirements exist already. - */ - vma->bound &= ~GLOBAL_BIND; - WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND)); + WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE)); } @@ -1957,7 +1949,8 @@ static void i915_ggtt_bind_vma(struct i915_vma *vma, BUG_ON(!i915_is_ggtt(vma->vm)); intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags); - vma->bound = GLOBAL_BIND; + + vma->bound |= GLOBAL_BIND; } static void i915_ggtt_clear_range(struct i915_address_space *vm, @@ -1976,7 +1969,6 @@ static void i915_ggtt_unbind_vma(struct i915_vma *vma) const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; BUG_ON(!i915_is_ggtt(vma->vm)); - vma->bound = 0; intel_gtt_clear_range(first, size); } @@ -1997,35 +1989,19 @@ static void ggtt_bind_vma(struct i915_vma *vma, if (i915_is_ggtt(vma->vm)) pages = vma->ggtt_view.pages; - /* If there is no aliasing PPGTT, or the caller needs a global mapping, - * or we have a global mapping already but the cacheability flags have - * changed, set the global PTEs. - * - * If there is an aliasing PPGTT it is anecdotally faster, so use that - * instead if none of the above hold true. - * - * NB: A global mapping should only be needed for special regions like - * "gtt mappable", SNB errata, or if specified via special execbuf - * flags. At all other times, the GPU will use the aliasing PPGTT. - */ if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { - if (!(vma->bound & GLOBAL_BIND) || - (cache_level != obj->cache_level)) { - vma->vm->insert_entries(vma->vm, pages, - vma->node.start, - cache_level, pte_flags); - vma->bound |= GLOBAL_BIND; - } + vma->vm->insert_entries(vma->vm, pages, + vma->node.start, + cache_level, pte_flags); + + vma->bound |= GLOBAL_BIND; } - if (dev_priv->mm.aliasing_ppgtt && - (!(vma->bound & LOCAL_BIND) || - (cache_level != obj->cache_level))) { + if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) { struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; appgtt->base.insert_entries(&appgtt->base, pages, vma->node.start, cache_level, pte_flags); - vma->bound |= LOCAL_BIND; } } @@ -2040,16 +2016,14 @@ static void ggtt_unbind_vma(struct i915_vma *vma) vma->node.start, obj->base.size, true); - vma->bound &= ~GLOBAL_BIND; } - if (vma->bound & LOCAL_BIND) { + if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) { struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; appgtt->base.clear_range(&appgtt->base, vma->node.start, obj->base.size, true); - vma->bound &= ~LOCAL_BIND; } } @@ -2839,6 +2813,7 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma) int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) { + u32 bind_flags = 0; int ret; if (vma->vm->allocate_va_range) { @@ -2855,12 +2830,24 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, if (i915_is_ggtt(vma->vm)) { ret = i915_get_ggtt_vma_pages(vma); - if (ret) - return ret; + return 0; } - vma->vm->bind_vma(vma, cache_level, flags); + if (flags & PIN_GLOBAL) + bind_flags |= GLOBAL_BIND; + if (flags & PIN_USER) + bind_flags |= LOCAL_BIND; + + if (flags & PIN_UPDATE) + bind_flags |= vma->bound; + else + bind_flags &= ~vma->bound; + + if (bind_flags) + vma->vm->bind_vma(vma, cache_level, bind_flags); + + vma->bound |= bind_flags; return 0; } -- cgit v1.2.3 From fa42331b4cd961cecb3f6919116d2e6efeb2334b Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:23 +0200 Subject: drm/i915: move i915_gem_restore_gtt_mappings around Avoids 2 forward declarations. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 109 ++++++++++++++++++------------------ 1 file changed, 53 insertions(+), 56 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 9e06180e206f..c36dcfeeadd0 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -97,9 +97,6 @@ const struct i915_ggtt_view i915_ggtt_view_rotated = { .type = I915_GGTT_VIEW_ROTATED }; -static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); -static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); - static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) { bool has_aliasing_ppgtt; @@ -1727,59 +1724,6 @@ void i915_gem_suspend_gtt_mappings(struct drm_device *dev) i915_ggtt_flush(dev_priv); } -void i915_gem_restore_gtt_mappings(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - struct drm_i915_gem_object *obj; - struct i915_address_space *vm; - - i915_check_and_clear_faults(dev); - - /* First fill our portion of the GTT with scratch pages */ - dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, - dev_priv->gtt.base.start, - dev_priv->gtt.base.total, - true); - - list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { - struct i915_vma *vma = i915_gem_obj_to_vma(obj, - &dev_priv->gtt.base); - if (!vma) - continue; - - i915_gem_clflush_object(obj, obj->pin_display); - WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE)); - } - - - if (INTEL_INFO(dev)->gen >= 8) { - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) - chv_setup_private_ppat(dev_priv); - else - bdw_setup_private_ppat(dev_priv); - - return; - } - - if (USES_PPGTT(dev)) { - list_for_each_entry(vm, &dev_priv->vm_list, global_link) { - /* TODO: Perhaps it shouldn't be gen6 specific */ - - struct i915_hw_ppgtt *ppgtt = - container_of(vm, struct i915_hw_ppgtt, - base); - - if (i915_is_ggtt(vm)) - ppgtt = dev_priv->mm.aliasing_ppgtt; - - gen6_write_page_range(dev_priv, &ppgtt->pd, - 0, ppgtt->base.total); - } - } - - i915_ggtt_flush(dev_priv); -} - int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) { if (obj->has_dma_mapping) @@ -2603,6 +2547,59 @@ int i915_gem_gtt_init(struct drm_device *dev) return 0; } +void i915_gem_restore_gtt_mappings(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_gem_object *obj; + struct i915_address_space *vm; + + i915_check_and_clear_faults(dev); + + /* First fill our portion of the GTT with scratch pages */ + dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, + dev_priv->gtt.base.start, + dev_priv->gtt.base.total, + true); + + list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { + struct i915_vma *vma = i915_gem_obj_to_vma(obj, + &dev_priv->gtt.base); + if (!vma) + continue; + + i915_gem_clflush_object(obj, obj->pin_display); + WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE)); + } + + + if (INTEL_INFO(dev)->gen >= 8) { + if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) + chv_setup_private_ppat(dev_priv); + else + bdw_setup_private_ppat(dev_priv); + + return; + } + + if (USES_PPGTT(dev)) { + list_for_each_entry(vm, &dev_priv->vm_list, global_link) { + /* TODO: Perhaps it shouldn't be gen6 specific */ + + struct i915_hw_ppgtt *ppgtt = + container_of(vm, struct i915_hw_ppgtt, + base); + + if (i915_is_ggtt(vm)) + ppgtt = dev_priv->mm.aliasing_ppgtt; + + gen6_write_page_range(dev_priv, &ppgtt->pd, + 0, ppgtt->base.total); + } + } + + i915_ggtt_flush(dev_priv); +} + static struct i915_vma * __i915_gem_vma_create(struct drm_i915_gem_object *obj, struct i915_address_space *vm, -- cgit v1.2.3 From 4755265977159be0261972da2ba54917765b18ed Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:24 +0200 Subject: drm/i915: Move ppgtt_bind/unbind around Again avoids some forward declarations. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 44 ++++++++++++++++--------------------- 1 file changed, 19 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index c36dcfeeadd0..1abbc1f95084 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -145,8 +145,25 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) static void ppgtt_bind_vma(struct i915_vma *vma, enum i915_cache_level cache_level, - u32 flags); -static void ppgtt_unbind_vma(struct i915_vma *vma); + u32 unused) +{ + u32 pte_flags = 0; + + /* Currently applicable only to VLV */ + if (vma->obj->gt_ro) + pte_flags |= PTE_READ_ONLY; + + vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, + cache_level, pte_flags); +} + +static void ppgtt_unbind_vma(struct i915_vma *vma) +{ + vma->vm->clear_range(vma->vm, + vma->node.start, + vma->obj->base.size, + true); +} static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr, enum i915_cache_level level, @@ -1604,29 +1621,6 @@ void i915_ppgtt_release(struct kref *kref) kfree(ppgtt); } -static void -ppgtt_bind_vma(struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 unused) -{ - u32 pte_flags = 0; - - /* Currently applicable only to VLV */ - if (vma->obj->gt_ro) - pte_flags |= PTE_READ_ONLY; - - vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, - cache_level, pte_flags); -} - -static void ppgtt_unbind_vma(struct i915_vma *vma) -{ - vma->vm->clear_range(vma->vm, - vma->node.start, - vma->obj->base.size, - true); -} - extern int intel_iommu_gfx_mapped; /* Certain Gen5 chipsets require require idling the GPU before * unmapping anything from the GTT when VT-d is enabled. -- cgit v1.2.3 From d369d2d9683dd98afbc7a37c1119d7a317790c47 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:25 +0200 Subject: drm/i915: Unduplicate i915_ggtt_unbind/bind_vma ggtt_bind/unbind_vma already has checks for aliasing ppgtt or not, there's nothing else magic they do. Resurrect i915_ggtt_insert_entries to make the reuse possibel. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 27 ++++++++------------------- 1 file changed, 8 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 1abbc1f95084..09430178049e 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1876,19 +1876,16 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm, readl(gtt_base); } - -static void i915_ggtt_bind_vma(struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 unused) +static void i915_ggtt_insert_entries(struct i915_address_space *vm, + struct sg_table *pages, + uint64_t start, + enum i915_cache_level cache_level, u32 unused) { - const unsigned long entry = vma->node.start >> PAGE_SHIFT; unsigned int flags = (cache_level == I915_CACHE_NONE) ? AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; - BUG_ON(!i915_is_ggtt(vma->vm)); - intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags); + intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); - vma->bound |= GLOBAL_BIND; } static void i915_ggtt_clear_range(struct i915_address_space *vm, @@ -1901,15 +1898,6 @@ static void i915_ggtt_clear_range(struct i915_address_space *vm, intel_gtt_clear_range(first_entry, num_entries); } -static void i915_ggtt_unbind_vma(struct i915_vma *vma) -{ - const unsigned int first = vma->node.start >> PAGE_SHIFT; - const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; - - BUG_ON(!i915_is_ggtt(vma->vm)); - intel_gtt_clear_range(first, size); -} - static void ggtt_bind_vma(struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) @@ -2471,9 +2459,10 @@ static int i915_gmch_probe(struct drm_device *dev, intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); + dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; - dev_priv->gtt.base.bind_vma = i915_ggtt_bind_vma; - dev_priv->gtt.base.unbind_vma = i915_ggtt_unbind_vma; + dev_priv->gtt.base.bind_vma = ggtt_bind_vma; + dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; if (unlikely(dev_priv->gtt.do_idle_maps)) DRM_INFO("applying Ironlake quirks for intel_iommu\n"); -- cgit v1.2.3 From 2c642b07eba461a244c32279a00d98ffab39ec07 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:26 +0200 Subject: drm/i915: Don't try to outsmart gcc in i915_gem_gtt.c Sprinkling static inline all over the place is carg-culting. Remove it. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 38 ++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 09430178049e..9a0bd95d3518 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -165,9 +165,9 @@ static void ppgtt_unbind_vma(struct i915_vma *vma) true); } -static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr, - enum i915_cache_level level, - bool valid) +static gen8_pte_t gen8_pte_encode(dma_addr_t addr, + enum i915_cache_level level, + bool valid) { gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; pte |= addr; @@ -187,9 +187,9 @@ static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr, return pte; } -static inline gen8_pde_t gen8_pde_encode(struct drm_device *dev, - dma_addr_t addr, - enum i915_cache_level level) +static gen8_pde_t gen8_pde_encode(struct drm_device *dev, + dma_addr_t addr, + enum i915_cache_level level) { gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; pde |= addr; @@ -299,8 +299,8 @@ static gen6_pte_t iris_pte_encode(dma_addr_t addr, #define i915_dma_unmap_single(px, dev) \ __i915_dma_unmap_single((px)->daddr, dev) -static inline void __i915_dma_unmap_single(dma_addr_t daddr, - struct drm_device *dev) +static void __i915_dma_unmap_single(dma_addr_t daddr, + struct drm_device *dev) { struct device *device = &dev->pdev->dev; @@ -321,9 +321,9 @@ static inline void __i915_dma_unmap_single(dma_addr_t daddr, #define i915_dma_map_single(px, dev) \ i915_dma_map_page_single((px)->page, (dev), &(px)->daddr) -static inline int i915_dma_map_page_single(struct page *page, - struct drm_device *dev, - dma_addr_t *daddr) +static int i915_dma_map_page_single(struct page *page, + struct drm_device *dev, + dma_addr_t *daddr) { struct device *device = &dev->pdev->dev; @@ -1268,7 +1268,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, * are switching between contexts with the same LRCA, we also must do a force * restore. */ -static inline void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) +static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) { /* If current vm != vm, */ ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; @@ -1625,7 +1625,7 @@ extern int intel_iommu_gfx_mapped; /* Certain Gen5 chipsets require require idling the GPU before * unmapping anything from the GTT when VT-d is enabled. */ -static inline bool needs_idle_maps(struct drm_device *dev) +static bool needs_idle_maps(struct drm_device *dev) { #ifdef CONFIG_INTEL_IOMMU /* Query intel_iommu to see if we need the workaround. Presumably that @@ -1731,7 +1731,7 @@ int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) return 0; } -static inline void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) +static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) { #ifdef writeq writeq(pte, addr); @@ -2154,14 +2154,14 @@ static void teardown_scratch_page(struct drm_device *dev) __free_page(page); } -static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) +static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) { snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; return snb_gmch_ctl << 20; } -static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) +static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) { bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; @@ -2177,7 +2177,7 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) return bdw_gmch_ctl << 20; } -static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) +static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) { gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; gmch_ctrl &= SNB_GMCH_GGMS_MASK; @@ -2188,14 +2188,14 @@ static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) return 0; } -static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) +static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) { snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; snb_gmch_ctl &= SNB_GMCH_GMS_MASK; return snb_gmch_ctl << 25; /* 32 MB units */ } -static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) +static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) { bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; -- cgit v1.2.3 From 70b9f6f8321f06788dc31783974750cb82745b65 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:27 +0200 Subject: rm/i915: Move i915_get_ggtt_vma_pages into ggtt_bind_vma We have this neat abstraction between ppgtt and ggtt for (un)bind_vma and didn't end up using it really. What a shame, so fix this and make the ->bind_vma hook a bit more useful. Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 41 ++++++++++++++++++++++--------------- drivers/gpu/drm/i915/i915_gem_gtt.h | 6 +++--- 2 files changed, 27 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 9a0bd95d3518..6fae6bdde156 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -92,6 +92,9 @@ * */ +static int +i915_get_ggtt_vma_pages(struct i915_vma *vma); + const struct i915_ggtt_view i915_ggtt_view_normal; const struct i915_ggtt_view i915_ggtt_view_rotated = { .type = I915_GGTT_VIEW_ROTATED @@ -143,9 +146,9 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) return has_aliasing_ppgtt ? 1 : 0; } -static void ppgtt_bind_vma(struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 unused) +static int ppgtt_bind_vma(struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 unused) { u32 pte_flags = 0; @@ -155,6 +158,8 @@ static void ppgtt_bind_vma(struct i915_vma *vma, vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, cache_level, pte_flags); + + return 0; } static void ppgtt_unbind_vma(struct i915_vma *vma) @@ -1898,22 +1903,26 @@ static void i915_ggtt_clear_range(struct i915_address_space *vm, intel_gtt_clear_range(first_entry, num_entries); } -static void ggtt_bind_vma(struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags) +static int ggtt_bind_vma(struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags) { struct drm_device *dev = vma->vm->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj = vma->obj; struct sg_table *pages = obj->pages; u32 pte_flags = 0; + int ret; + + ret = i915_get_ggtt_vma_pages(vma); + if (ret) + return ret; + pages = vma->ggtt_view.pages; /* Currently applicable only to VLV */ if (obj->gt_ro) pte_flags |= PTE_READ_ONLY; - if (i915_is_ggtt(vma->vm)) - pages = vma->ggtt_view.pages; if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { vma->vm->insert_entries(vma->vm, pages, @@ -1929,6 +1938,8 @@ static void ggtt_bind_vma(struct i915_vma *vma, vma->node.start, cache_level, pte_flags); } + + return 0; } static void ggtt_unbind_vma(struct i915_vma *vma) @@ -2749,7 +2760,7 @@ err_st_alloc: return ERR_PTR(ret); } -static inline int +static int i915_get_ggtt_vma_pages(struct i915_vma *vma) { int ret = 0; @@ -2793,8 +2804,8 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma) int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) { + int ret = 0; u32 bind_flags = 0; - int ret; if (vma->vm->allocate_va_range) { trace_i915_va_alloc(vma->vm, vma->node.start, @@ -2808,12 +2819,6 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, return ret; } - if (i915_is_ggtt(vma->vm)) { - ret = i915_get_ggtt_vma_pages(vma); - if (ret) - return 0; - } - if (flags & PIN_GLOBAL) bind_flags |= GLOBAL_BIND; if (flags & PIN_USER) @@ -2825,7 +2830,9 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, bind_flags &= ~vma->bound; if (bind_flags) - vma->vm->bind_vma(vma, cache_level, bind_flags); + ret = vma->vm->bind_vma(vma, cache_level, bind_flags); + if (ret) + return ret; vma->bound |= bind_flags; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index fb0a04aa5363..4e6cac575cd8 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -278,9 +278,9 @@ struct i915_address_space { * setting the valid PTE entries to a reserved scratch page. */ void (*unbind_vma)(struct i915_vma *vma); /* Map an object into an address space with the given cache flags. */ - void (*bind_vma)(struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags); + int (*bind_vma)(struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags); }; /* The Graphics Translation Table is the way in which GEN hardware translates a -- cgit v1.2.3 From 14f1fa2d0c86bcce0a66196acb32648c2f083b87 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Thu, 23 Apr 2015 10:17:34 +0200 Subject: drm/i915: Enable dithering on NatSemi DVO2501 for Fujitsu S6010 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch enables the (unfortunately undocumented) scaler of the NatSemi 2501 DVO found in the Fujitsu-Siemens S6010 laptop and other machines of the same series and age. Parts of the DVO scaler logic have been revealed by reverse engineering and trial and error, so your milage may vary. The patch (and the whole ns2501 DVO code) is currently only good for the 1024x768 panel of the S6010, and may hopefully work on other machines with the same panel size. The mode-specific configuration of the scaler have been moved out into a separate class, the mode-agnostic settings remain as raw register list as their purpose remains unclear at this point. Signed-off-by: Daniel Vetter Signed-off-by: Thomas Richter [danvet: Make the thing apply and conform to kernel patch expectations.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/dvo_ns2501.c | 670 +++++++++++++++++++++----------------- 1 file changed, 374 insertions(+), 296 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/drivers/gpu/drm/i915/dvo_ns2501.c index 441630434d34..97ae8aa157e9 100644 --- a/drivers/gpu/drm/i915/dvo_ns2501.c +++ b/drivers/gpu/drm/i915/dvo_ns2501.c @@ -60,6 +60,130 @@ #define NS2501_REGC 0x0c +/* + * The following registers are not part of the official datasheet + * and are the result of reverse engineering. + */ + +/* + * Register c0 controls how the DVO synchronizes with + * its input. + */ +#define NS2501_REGC0 0xc0 +#define NS2501_C0_ENABLE (1<<0) /* enable the DVO sync in general */ +#define NS2501_C0_HSYNC (1<<1) /* synchronize horizontal with input */ +#define NS2501_C0_VSYNC (1<<2) /* synchronize vertical with input */ +#define NS2501_C0_RESET (1<<7) /* reset the synchronization flip/flops */ + +/* + * Register 41 is somehow related to the sync register and sync + * configuration. It should be 0x32 whenever regC0 is 0x05 (hsync off) + * and 0x00 otherwise. + */ +#define NS2501_REG41 0x41 + +/* + * this register controls the dithering of the DVO + * One bit enables it, the other define the dithering depth. + * The higher the value, the lower the dithering depth. + */ +#define NS2501_F9_REG 0xf9 +#define NS2501_F9_ENABLE (1<<0) /* if set, dithering is enabled */ +#define NS2501_F9_DITHER_MASK (0x7f<<1) /* controls the dither depth */ +#define NS2501_F9_DITHER_SHIFT 1 /* shifts the dither mask */ + +/* + * PLL configuration register. This is a pair of registers, + * one single byte register at 1B, and a pair at 1C,1D. + * These registers are counters/dividers. + */ +#define NS2501_REG1B 0x1b /* one byte PLL control register */ +#define NS2501_REG1C 0x1c /* low-part of the second register */ +#define NS2501_REG1D 0x1d /* high-part of the second register */ + +/* + * Scaler control registers. Horizontal at b8,b9, + * vertical at 10,11. The scale factor is computed as + * 2^16/control-value. The low-byte comes first. + */ +#define NS2501_REG10 0x10 /* low-byte vertical scaler */ +#define NS2501_REG11 0x11 /* high-byte vertical scaler */ +#define NS2501_REGB8 0xb8 /* low-byte horizontal scaler */ +#define NS2501_REGB9 0xb9 /* high-byte horizontal scaler */ + +/* + * Display window definition. This consists of four registers + * per dimension. One register pair defines the start of the + * display, one the end. + * As far as I understand, this defines the window within which + * the scaler samples the input. + */ +#define NS2501_REGC1 0xc1 /* low-byte horizontal display start */ +#define NS2501_REGC2 0xc2 /* high-byte horizontal display start */ +#define NS2501_REGC3 0xc3 /* low-byte horizontal display stop */ +#define NS2501_REGC4 0xc4 /* high-byte horizontal display stop */ +#define NS2501_REGC5 0xc5 /* low-byte vertical display start */ +#define NS2501_REGC6 0xc6 /* high-byte vertical display start */ +#define NS2501_REGC7 0xc7 /* low-byte vertical display stop */ +#define NS2501_REGC8 0xc8 /* high-byte vertical display stop */ + +/* + * The following register pair seems to define the start of + * the vertical sync. If automatic syncing is enabled, and the + * register value defines a sync pulse that is later than the + * incoming sync, then the register value is ignored and the + * external hsync triggers the synchronization. + */ +#define NS2501_REG80 0x80 /* low-byte vsync-start */ +#define NS2501_REG81 0x81 /* high-byte vsync-start */ + +/* + * The following register pair seems to define the total number + * of lines created at the output side of the scaler. + * This is again a low-high register pair. + */ +#define NS2501_REG82 0x82 /* output display height, low byte */ +#define NS2501_REG83 0x83 /* output display height, high byte */ + +/* + * The following registers define the end of the front-porch + * in horizontal and vertical position and hence allow to shift + * the image left/right or up/down. + */ +#define NS2501_REG98 0x98 /* horizontal start of display + 256, low */ +#define NS2501_REG99 0x99 /* horizontal start of display + 256, high */ +#define NS2501_REG8E 0x8e /* vertical start of the display, low byte */ +#define NS2501_REG8F 0x8f /* vertical start of the display, high byte */ + +/* + * The following register pair control the function of the + * backlight and the DVO output. To enable the corresponding + * function, the corresponding bit must be set in both registers. + */ +#define NS2501_REG34 0x34 /* DVO enable functions, first register */ +#define NS2501_REG35 0x35 /* DVO enable functions, second register */ +#define NS2501_34_ENABLE_OUTPUT (1<<0) /* enable DVO output */ +#define NS2501_34_ENABLE_BACKLIGHT (1<<1) /* enable backlight */ + +/* + * Registers 9C and 9D define the vertical output offset + * of the visible region. + */ +#define NS2501_REG9C 0x9c +#define NS2501_REG9D 0x9d + +/* + * The register 9F defines the dithering. This requires the + * scaler to be ON. Bit 0 enables dithering, the remaining + * bits control the depth of the dither. The higher the value, + * the LOWER the dithering amplitude. A good value seems to be + * 15 (total register value). + */ +#define NS2501_REGF9 0xf9 +#define NS2501_F9_ENABLE_DITHER (1<<0) /* enable dithering */ +#define NS2501_F9_DITHER_MASK (0x7f<<1) /* dither masking */ +#define NS2501_F9_DITHER_SHIFT 1 /* upshift of the dither mask */ + enum { MODE_640x480, MODE_800x600, @@ -72,274 +196,178 @@ struct ns2501_reg { }; /* - * Magic values based on what the BIOS on - * Fujitsu-Siemens Lifebook S6010 programs (1024x768 panel). + * The following structure keeps the complete configuration of + * the DVO, given a specific output configuration. + * This is pretty much guess-work from reverse-engineering, so + * read all this with a grain of salt. + */ +struct ns2501_configuration { + uint8_t sync; /* configuration of the C0 register */ + uint8_t conf; /* configuration register 8 */ + uint8_t syncb; /* configuration register 41 */ + uint8_t dither; /* configuration of the dithering */ + uint8_t pll_a; /* PLL configuration, register A, 1B */ + uint16_t pll_b; /* PLL configuration, register B, 1C/1D */ + uint16_t hstart; /* horizontal start, registers C1/C2 */ + uint16_t hstop; /* horizontal total, registers C3/C4 */ + uint16_t vstart; /* vertical start, registers C5/C6 */ + uint16_t vstop; /* vertical total, registers C7/C8 */ + uint16_t vsync; /* manual vertical sync start, 80/81 */ + uint16_t vtotal; /* number of lines generated, 82/83 */ + uint16_t hpos; /* horizontal position + 256, 98/99 */ + uint16_t vpos; /* vertical position, 8e/8f */ + uint16_t voffs; /* vertical output offset, 9c/9d */ + uint16_t hscale; /* horizontal scaling factor, b8/b9 */ + uint16_t vscale; /* vertical scaling factor, 10/11 */ +}; + +/* + * DVO configuration values, partially based on what the BIOS + * of the Fujitsu Lifebook S6010 writes into registers, + * partially found by manual tweaking. These configurations assume + * a 1024x768 panel. */ -static const struct ns2501_reg regs_1024x768[][86] = { +static const struct ns2501_configuration ns2501_modes[] = { [MODE_640x480] = { - [0] = { .offset = 0x0a, .value = 0x81, }, - [1] = { .offset = 0x18, .value = 0x07, }, - [2] = { .offset = 0x19, .value = 0x00, }, - [3] = { .offset = 0x1a, .value = 0x00, }, - [4] = { .offset = 0x1b, .value = 0x11, }, - [5] = { .offset = 0x1c, .value = 0x54, }, - [6] = { .offset = 0x1d, .value = 0x03, }, - [7] = { .offset = 0x1e, .value = 0x02, }, - [8] = { .offset = 0xf3, .value = 0x90, }, - [9] = { .offset = 0xf9, .value = 0x00, }, - [10] = { .offset = 0xc1, .value = 0x90, }, - [11] = { .offset = 0xc2, .value = 0x00, }, - [12] = { .offset = 0xc3, .value = 0x0f, }, - [13] = { .offset = 0xc4, .value = 0x03, }, - [14] = { .offset = 0xc5, .value = 0x16, }, - [15] = { .offset = 0xc6, .value = 0x00, }, - [16] = { .offset = 0xc7, .value = 0x02, }, - [17] = { .offset = 0xc8, .value = 0x02, }, - [18] = { .offset = 0xf4, .value = 0x00, }, - [19] = { .offset = 0x80, .value = 0xff, }, - [20] = { .offset = 0x81, .value = 0x07, }, - [21] = { .offset = 0x82, .value = 0x3d, }, - [22] = { .offset = 0x83, .value = 0x05, }, - [23] = { .offset = 0x94, .value = 0x00, }, - [24] = { .offset = 0x95, .value = 0x00, }, - [25] = { .offset = 0x96, .value = 0x05, }, - [26] = { .offset = 0x97, .value = 0x00, }, - [27] = { .offset = 0x9a, .value = 0x88, }, - [28] = { .offset = 0x9b, .value = 0x00, }, - [29] = { .offset = 0x98, .value = 0x00, }, - [30] = { .offset = 0x99, .value = 0x00, }, - [31] = { .offset = 0xf7, .value = 0x88, }, - [32] = { .offset = 0xf8, .value = 0x0a, }, - [33] = { .offset = 0x9c, .value = 0x24, }, - [34] = { .offset = 0x9d, .value = 0x00, }, - [35] = { .offset = 0x9e, .value = 0x25, }, - [36] = { .offset = 0x9f, .value = 0x03, }, - [37] = { .offset = 0xa0, .value = 0x28, }, - [38] = { .offset = 0xa1, .value = 0x01, }, - [39] = { .offset = 0xa2, .value = 0x28, }, - [40] = { .offset = 0xa3, .value = 0x05, }, - [41] = { .offset = 0xb6, .value = 0x09, }, - [42] = { .offset = 0xb8, .value = 0x00, }, - [43] = { .offset = 0xb9, .value = 0xa0, }, - [44] = { .offset = 0xba, .value = 0x00, }, - [45] = { .offset = 0xbb, .value = 0x20, }, - [46] = { .offset = 0x10, .value = 0x00, }, - [47] = { .offset = 0x11, .value = 0xa0, }, - [48] = { .offset = 0x12, .value = 0x02, }, - [49] = { .offset = 0x20, .value = 0x00, }, - [50] = { .offset = 0x22, .value = 0x00, }, - [51] = { .offset = 0x23, .value = 0x00, }, - [52] = { .offset = 0x24, .value = 0x00, }, - [53] = { .offset = 0x25, .value = 0x00, }, - [54] = { .offset = 0x8c, .value = 0x10, }, - [55] = { .offset = 0x8d, .value = 0x02, }, - [56] = { .offset = 0x8e, .value = 0x10, }, - [57] = { .offset = 0x8f, .value = 0x00, }, - [58] = { .offset = 0x90, .value = 0xff, }, - [59] = { .offset = 0x91, .value = 0x07, }, - [60] = { .offset = 0x92, .value = 0xa0, }, - [61] = { .offset = 0x93, .value = 0x02, }, - [62] = { .offset = 0xa5, .value = 0x00, }, - [63] = { .offset = 0xa6, .value = 0x00, }, - [64] = { .offset = 0xa7, .value = 0x00, }, - [65] = { .offset = 0xa8, .value = 0x00, }, - [66] = { .offset = 0xa9, .value = 0x04, }, - [67] = { .offset = 0xaa, .value = 0x70, }, - [68] = { .offset = 0xab, .value = 0x4f, }, - [69] = { .offset = 0xac, .value = 0x00, }, - [70] = { .offset = 0xa4, .value = 0x84, }, - [71] = { .offset = 0x7e, .value = 0x18, }, - [72] = { .offset = 0x84, .value = 0x00, }, - [73] = { .offset = 0x85, .value = 0x00, }, - [74] = { .offset = 0x86, .value = 0x00, }, - [75] = { .offset = 0x87, .value = 0x00, }, - [76] = { .offset = 0x88, .value = 0x00, }, - [77] = { .offset = 0x89, .value = 0x00, }, - [78] = { .offset = 0x8a, .value = 0x00, }, - [79] = { .offset = 0x8b, .value = 0x00, }, - [80] = { .offset = 0x26, .value = 0x00, }, - [81] = { .offset = 0x27, .value = 0x00, }, - [82] = { .offset = 0xad, .value = 0x00, }, - [83] = { .offset = 0x08, .value = 0x30, }, /* 0x31 */ - [84] = { .offset = 0x41, .value = 0x00, }, - [85] = { .offset = 0xc0, .value = 0x05, }, + .sync = NS2501_C0_ENABLE | NS2501_C0_VSYNC, + .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD, + .syncb = 0x32, + .dither = 0x0f, + .pll_a = 17, + .pll_b = 852, + .hstart = 144, + .hstop = 783, + .vstart = 22, + .vstop = 514, + .vsync = 2047, /* actually, ignored with this config */ + .vtotal = 1341, + .hpos = 0, + .vpos = 16, + .voffs = 36, + .hscale = 40960, + .vscale = 40960 }, [MODE_800x600] = { - [0] = { .offset = 0x0a, .value = 0x81, }, - [1] = { .offset = 0x18, .value = 0x07, }, - [2] = { .offset = 0x19, .value = 0x00, }, - [3] = { .offset = 0x1a, .value = 0x00, }, - [4] = { .offset = 0x1b, .value = 0x19, }, - [5] = { .offset = 0x1c, .value = 0x64, }, - [6] = { .offset = 0x1d, .value = 0x02, }, - [7] = { .offset = 0x1e, .value = 0x02, }, - [8] = { .offset = 0xf3, .value = 0x90, }, - [9] = { .offset = 0xf9, .value = 0x00, }, - [10] = { .offset = 0xc1, .value = 0xd7, }, - [11] = { .offset = 0xc2, .value = 0x00, }, - [12] = { .offset = 0xc3, .value = 0xf8, }, - [13] = { .offset = 0xc4, .value = 0x03, }, - [14] = { .offset = 0xc5, .value = 0x1a, }, - [15] = { .offset = 0xc6, .value = 0x00, }, - [16] = { .offset = 0xc7, .value = 0x73, }, - [17] = { .offset = 0xc8, .value = 0x02, }, - [18] = { .offset = 0xf4, .value = 0x00, }, - [19] = { .offset = 0x80, .value = 0x27, }, - [20] = { .offset = 0x81, .value = 0x03, }, - [21] = { .offset = 0x82, .value = 0x41, }, - [22] = { .offset = 0x83, .value = 0x05, }, - [23] = { .offset = 0x94, .value = 0x00, }, - [24] = { .offset = 0x95, .value = 0x00, }, - [25] = { .offset = 0x96, .value = 0x05, }, - [26] = { .offset = 0x97, .value = 0x00, }, - [27] = { .offset = 0x9a, .value = 0x88, }, - [28] = { .offset = 0x9b, .value = 0x00, }, - [29] = { .offset = 0x98, .value = 0x00, }, - [30] = { .offset = 0x99, .value = 0x00, }, - [31] = { .offset = 0xf7, .value = 0x88, }, - [32] = { .offset = 0xf8, .value = 0x06, }, - [33] = { .offset = 0x9c, .value = 0x23, }, - [34] = { .offset = 0x9d, .value = 0x00, }, - [35] = { .offset = 0x9e, .value = 0x25, }, - [36] = { .offset = 0x9f, .value = 0x03, }, - [37] = { .offset = 0xa0, .value = 0x28, }, - [38] = { .offset = 0xa1, .value = 0x01, }, - [39] = { .offset = 0xa2, .value = 0x28, }, - [40] = { .offset = 0xa3, .value = 0x05, }, - [41] = { .offset = 0xb6, .value = 0x09, }, - [42] = { .offset = 0xb8, .value = 0x30, }, - [43] = { .offset = 0xb9, .value = 0xc8, }, - [44] = { .offset = 0xba, .value = 0x00, }, - [45] = { .offset = 0xbb, .value = 0x20, }, - [46] = { .offset = 0x10, .value = 0x20, }, - [47] = { .offset = 0x11, .value = 0xc8, }, - [48] = { .offset = 0x12, .value = 0x02, }, - [49] = { .offset = 0x20, .value = 0x00, }, - [50] = { .offset = 0x22, .value = 0x00, }, - [51] = { .offset = 0x23, .value = 0x00, }, - [52] = { .offset = 0x24, .value = 0x00, }, - [53] = { .offset = 0x25, .value = 0x00, }, - [54] = { .offset = 0x8c, .value = 0x10, }, - [55] = { .offset = 0x8d, .value = 0x02, }, - [56] = { .offset = 0x8e, .value = 0x04, }, - [57] = { .offset = 0x8f, .value = 0x00, }, - [58] = { .offset = 0x90, .value = 0xff, }, - [59] = { .offset = 0x91, .value = 0x07, }, - [60] = { .offset = 0x92, .value = 0xa0, }, - [61] = { .offset = 0x93, .value = 0x02, }, - [62] = { .offset = 0xa5, .value = 0x00, }, - [63] = { .offset = 0xa6, .value = 0x00, }, - [64] = { .offset = 0xa7, .value = 0x00, }, - [65] = { .offset = 0xa8, .value = 0x00, }, - [66] = { .offset = 0xa9, .value = 0x83, }, - [67] = { .offset = 0xaa, .value = 0x40, }, - [68] = { .offset = 0xab, .value = 0x32, }, - [69] = { .offset = 0xac, .value = 0x00, }, - [70] = { .offset = 0xa4, .value = 0x80, }, - [71] = { .offset = 0x7e, .value = 0x18, }, - [72] = { .offset = 0x84, .value = 0x00, }, - [73] = { .offset = 0x85, .value = 0x00, }, - [74] = { .offset = 0x86, .value = 0x00, }, - [75] = { .offset = 0x87, .value = 0x00, }, - [76] = { .offset = 0x88, .value = 0x00, }, - [77] = { .offset = 0x89, .value = 0x00, }, - [78] = { .offset = 0x8a, .value = 0x00, }, - [79] = { .offset = 0x8b, .value = 0x00, }, - [80] = { .offset = 0x26, .value = 0x00, }, - [81] = { .offset = 0x27, .value = 0x00, }, - [82] = { .offset = 0xad, .value = 0x00, }, - [83] = { .offset = 0x08, .value = 0x30, }, /* 0x31 */ - [84] = { .offset = 0x41, .value = 0x00, }, - [85] = { .offset = 0xc0, .value = 0x07, }, + .sync = NS2501_C0_ENABLE | + NS2501_C0_HSYNC | NS2501_C0_VSYNC, + .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD, + .syncb = 0x00, + .dither = 0x0f, + .pll_a = 25, + .pll_b = 612, + .hstart = 215, + .hstop = 1016, + .vstart = 26, + .vstop = 627, + .vsync = 807, + .vtotal = 1341, + .hpos = 0, + .vpos = 4, + .voffs = 35, + .hscale = 51248, + .vscale = 51232 }, [MODE_1024x768] = { - [0] = { .offset = 0x0a, .value = 0x81, }, - [1] = { .offset = 0x18, .value = 0x07, }, - [2] = { .offset = 0x19, .value = 0x00, }, - [3] = { .offset = 0x1a, .value = 0x00, }, - [4] = { .offset = 0x1b, .value = 0x11, }, - [5] = { .offset = 0x1c, .value = 0x54, }, - [6] = { .offset = 0x1d, .value = 0x03, }, - [7] = { .offset = 0x1e, .value = 0x02, }, - [8] = { .offset = 0xf3, .value = 0x90, }, - [9] = { .offset = 0xf9, .value = 0x00, }, - [10] = { .offset = 0xc1, .value = 0x90, }, - [11] = { .offset = 0xc2, .value = 0x00, }, - [12] = { .offset = 0xc3, .value = 0x0f, }, - [13] = { .offset = 0xc4, .value = 0x03, }, - [14] = { .offset = 0xc5, .value = 0x16, }, - [15] = { .offset = 0xc6, .value = 0x00, }, - [16] = { .offset = 0xc7, .value = 0x02, }, - [17] = { .offset = 0xc8, .value = 0x02, }, - [18] = { .offset = 0xf4, .value = 0x00, }, - [19] = { .offset = 0x80, .value = 0xff, }, - [20] = { .offset = 0x81, .value = 0x07, }, - [21] = { .offset = 0x82, .value = 0x3d, }, - [22] = { .offset = 0x83, .value = 0x05, }, - [23] = { .offset = 0x94, .value = 0x00, }, - [24] = { .offset = 0x95, .value = 0x00, }, - [25] = { .offset = 0x96, .value = 0x05, }, - [26] = { .offset = 0x97, .value = 0x00, }, - [27] = { .offset = 0x9a, .value = 0x88, }, - [28] = { .offset = 0x9b, .value = 0x00, }, - [29] = { .offset = 0x98, .value = 0x00, }, - [30] = { .offset = 0x99, .value = 0x00, }, - [31] = { .offset = 0xf7, .value = 0x88, }, - [32] = { .offset = 0xf8, .value = 0x0a, }, - [33] = { .offset = 0x9c, .value = 0x24, }, - [34] = { .offset = 0x9d, .value = 0x00, }, - [35] = { .offset = 0x9e, .value = 0x25, }, - [36] = { .offset = 0x9f, .value = 0x03, }, - [37] = { .offset = 0xa0, .value = 0x28, }, - [38] = { .offset = 0xa1, .value = 0x01, }, - [39] = { .offset = 0xa2, .value = 0x28, }, - [40] = { .offset = 0xa3, .value = 0x05, }, - [41] = { .offset = 0xb6, .value = 0x09, }, - [42] = { .offset = 0xb8, .value = 0x00, }, - [43] = { .offset = 0xb9, .value = 0xa0, }, - [44] = { .offset = 0xba, .value = 0x00, }, - [45] = { .offset = 0xbb, .value = 0x20, }, - [46] = { .offset = 0x10, .value = 0x00, }, - [47] = { .offset = 0x11, .value = 0xa0, }, - [48] = { .offset = 0x12, .value = 0x02, }, - [49] = { .offset = 0x20, .value = 0x00, }, - [50] = { .offset = 0x22, .value = 0x00, }, - [51] = { .offset = 0x23, .value = 0x00, }, - [52] = { .offset = 0x24, .value = 0x00, }, - [53] = { .offset = 0x25, .value = 0x00, }, - [54] = { .offset = 0x8c, .value = 0x10, }, - [55] = { .offset = 0x8d, .value = 0x02, }, - [56] = { .offset = 0x8e, .value = 0x10, }, - [57] = { .offset = 0x8f, .value = 0x00, }, - [58] = { .offset = 0x90, .value = 0xff, }, - [59] = { .offset = 0x91, .value = 0x07, }, - [60] = { .offset = 0x92, .value = 0xa0, }, - [61] = { .offset = 0x93, .value = 0x02, }, - [62] = { .offset = 0xa5, .value = 0x00, }, - [63] = { .offset = 0xa6, .value = 0x00, }, - [64] = { .offset = 0xa7, .value = 0x00, }, - [65] = { .offset = 0xa8, .value = 0x00, }, - [66] = { .offset = 0xa9, .value = 0x04, }, - [67] = { .offset = 0xaa, .value = 0x70, }, - [68] = { .offset = 0xab, .value = 0x4f, }, - [69] = { .offset = 0xac, .value = 0x00, }, - [70] = { .offset = 0xa4, .value = 0x84, }, - [71] = { .offset = 0x7e, .value = 0x18, }, - [72] = { .offset = 0x84, .value = 0x00, }, - [73] = { .offset = 0x85, .value = 0x00, }, - [74] = { .offset = 0x86, .value = 0x00, }, - [75] = { .offset = 0x87, .value = 0x00, }, - [76] = { .offset = 0x88, .value = 0x00, }, - [77] = { .offset = 0x89, .value = 0x00, }, - [78] = { .offset = 0x8a, .value = 0x00, }, - [79] = { .offset = 0x8b, .value = 0x00, }, - [80] = { .offset = 0x26, .value = 0x00, }, - [81] = { .offset = 0x27, .value = 0x00, }, - [82] = { .offset = 0xad, .value = 0x00, }, - [83] = { .offset = 0x08, .value = 0x34, }, /* 0x35 */ - [84] = { .offset = 0x41, .value = 0x00, }, - [85] = { .offset = 0xc0, .value = 0x01, }, - }, + .sync = NS2501_C0_ENABLE | NS2501_C0_VSYNC, + .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD, + .syncb = 0x32, + .dither = 0x0f, + .pll_a = 11, + .pll_b = 1350, + .hstart = 276, + .hstop = 1299, + .vstart = 15, + .vstop = 1056, + .vsync = 2047, + .vtotal = 1341, + .hpos = 0, + .vpos = 7, + .voffs = 27, + .hscale = 65535, + .vscale = 65535 + } +}; + +/* + * Other configuration values left by the BIOS of the + * Fujitsu S6010 in the DVO control registers. Their + * value does not depend on the BIOS and their meaning + * is unknown. + */ + +static const struct ns2501_reg mode_agnostic_values[] = { + /* 08 is mode specific */ + [0] = { .offset = 0x0a, .value = 0x81, }, + /* 10,11 are part of the mode specific configuration */ + [1] = { .offset = 0x12, .value = 0x02, }, + [2] = { .offset = 0x18, .value = 0x07, }, + [3] = { .offset = 0x19, .value = 0x00, }, + [4] = { .offset = 0x1a, .value = 0x00, }, /* PLL?, ignored */ + /* 1b,1c,1d are part of the mode specific configuration */ + [5] = { .offset = 0x1e, .value = 0x02, }, + [6] = { .offset = 0x1f, .value = 0x40, }, + [7] = { .offset = 0x20, .value = 0x00, }, + [8] = { .offset = 0x21, .value = 0x00, }, + [9] = { .offset = 0x22, .value = 0x00, }, + [10] = { .offset = 0x23, .value = 0x00, }, + [11] = { .offset = 0x24, .value = 0x00, }, + [12] = { .offset = 0x25, .value = 0x00, }, + [13] = { .offset = 0x26, .value = 0x00, }, + [14] = { .offset = 0x27, .value = 0x00, }, + [15] = { .offset = 0x7e, .value = 0x18, }, + /* 80-84 are part of the mode-specific configuration */ + [16] = { .offset = 0x84, .value = 0x00, }, + [17] = { .offset = 0x85, .value = 0x00, }, + [18] = { .offset = 0x86, .value = 0x00, }, + [19] = { .offset = 0x87, .value = 0x00, }, + [20] = { .offset = 0x88, .value = 0x00, }, + [21] = { .offset = 0x89, .value = 0x00, }, + [22] = { .offset = 0x8a, .value = 0x00, }, + [23] = { .offset = 0x8b, .value = 0x00, }, + [24] = { .offset = 0x8c, .value = 0x10, }, + [25] = { .offset = 0x8d, .value = 0x02, }, + /* 8e,8f are part of the mode-specific configuration */ + [26] = { .offset = 0x90, .value = 0xff, }, + [27] = { .offset = 0x91, .value = 0x07, }, + [28] = { .offset = 0x92, .value = 0xa0, }, + [29] = { .offset = 0x93, .value = 0x02, }, + [30] = { .offset = 0x94, .value = 0x00, }, + [31] = { .offset = 0x95, .value = 0x00, }, + [32] = { .offset = 0x96, .value = 0x05, }, + [33] = { .offset = 0x97, .value = 0x00, }, + /* 98,99 are part of the mode-specific configuration */ + [34] = { .offset = 0x9a, .value = 0x88, }, + [35] = { .offset = 0x9b, .value = 0x00, }, + /* 9c,9d are part of the mode-specific configuration */ + [36] = { .offset = 0x9e, .value = 0x25, }, + [37] = { .offset = 0x9f, .value = 0x03, }, + [38] = { .offset = 0xa0, .value = 0x28, }, + [39] = { .offset = 0xa1, .value = 0x01, }, + [40] = { .offset = 0xa2, .value = 0x28, }, + [41] = { .offset = 0xa3, .value = 0x05, }, + /* register 0xa4 is mode specific, but 0x80..0x84 works always */ + [42] = { .offset = 0xa4, .value = 0x84, }, + [43] = { .offset = 0xa5, .value = 0x00, }, + [44] = { .offset = 0xa6, .value = 0x00, }, + [45] = { .offset = 0xa7, .value = 0x00, }, + [46] = { .offset = 0xa8, .value = 0x00, }, + /* 0xa9 to 0xab are mode specific, but have no visible effect */ + [47] = { .offset = 0xa9, .value = 0x04, }, + [48] = { .offset = 0xaa, .value = 0x70, }, + [49] = { .offset = 0xab, .value = 0x4f, }, + [50] = { .offset = 0xac, .value = 0x00, }, + [51] = { .offset = 0xad, .value = 0x00, }, + [52] = { .offset = 0xb6, .value = 0x09, }, + [53] = { .offset = 0xb7, .value = 0x03, }, + /* b8,b9 are part of the mode-specific configuration */ + [54] = { .offset = 0xba, .value = 0x00, }, + [55] = { .offset = 0xbb, .value = 0x20, }, + [56] = { .offset = 0xf3, .value = 0x90, }, + [57] = { .offset = 0xf4, .value = 0x00, }, + [58] = { .offset = 0xf7, .value = 0x88, }, + /* f8 is mode specific, but the value does not matter */ + [59] = { .offset = 0xf8, .value = 0x0a, }, + [60] = { .offset = 0xf9, .value = 0x00, } }; static const struct ns2501_reg regs_init[] = { @@ -350,24 +378,11 @@ static const struct ns2501_reg regs_init[] = { struct ns2501_priv { bool quiet; - const struct ns2501_reg *regs; + const struct ns2501_configuration *conf; }; #define NSPTR(d) ((NS2501Ptr)(d->DriverPrivate.ptr)) -/* - * For reasons unclear to me, the ns2501 at least on the Fujitsu/Siemens - * laptops does not react on the i2c bus unless - * both the PLL is running and the display is configured in its native - * resolution. - * This function forces the DVO on, and stores the registers it touches. - * Afterwards, registers are restored to regular values. - * - * This is pretty much a hack, though it works. - * Without that, ns2501_readb and ns2501_writeb fail - * when switching the resolution. - */ - /* ** Read a register from the ns2501. ** Returns true if successful, false otherwise. @@ -534,6 +549,7 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { + const struct ns2501_configuration *conf; struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); int mode_idx, i; @@ -541,6 +557,36 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo, ("set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d).\n", mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); + DRM_DEBUG_KMS("Detailed requested mode settings are:\n" + "clock : %d kHz\n" + "hdisplay : %d\n" + "hblank start : %d\n" + "hblank end : %d\n" + "hsync start : %d\n" + "hsync end : %d\n" + "htotal : %d\n" + "hskew : %d\n" + "vdisplay : %d\n" + "vblank start : %d\n" + "hblank end : %d\n" + "vsync start : %d\n" + "vsync end : %d\n" + "vtotal : %d\n", + adjusted_mode->crtc_clock, + adjusted_mode->crtc_hdisplay, + adjusted_mode->crtc_hblank_start, + adjusted_mode->crtc_hblank_end, + adjusted_mode->crtc_hsync_start, + adjusted_mode->crtc_hsync_end, + adjusted_mode->crtc_htotal, + adjusted_mode->crtc_hskew, + adjusted_mode->crtc_vdisplay, + adjusted_mode->crtc_vblank_start, + adjusted_mode->crtc_vblank_end, + adjusted_mode->crtc_vsync_start, + adjusted_mode->crtc_vsync_end, + adjusted_mode->crtc_vtotal); + if (mode->hdisplay == 640 && mode->vdisplay == 480) mode_idx = MODE_640x480; else if (mode->hdisplay == 800 && mode->vdisplay == 600) @@ -554,10 +600,44 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo, for (i = 0; i < ARRAY_SIZE(regs_init); i++) ns2501_writeb(dvo, regs_init[i].offset, regs_init[i].value); - ns->regs = regs_1024x768[mode_idx]; - - for (i = 0; i < 84; i++) - ns2501_writeb(dvo, ns->regs[i].offset, ns->regs[i].value); + /* Write the mode-agnostic values */ + for (i = 0; i < ARRAY_SIZE(mode_agnostic_values); i++) + ns2501_writeb(dvo, mode_agnostic_values[i].offset, + mode_agnostic_values[i].value); + + /* Write now the mode-specific configuration */ + conf = ns2501_modes + mode_idx; + ns->conf = conf; + + ns2501_writeb(dvo, NS2501_REG8, conf->conf); + ns2501_writeb(dvo, NS2501_REG1B, conf->pll_a); + ns2501_writeb(dvo, NS2501_REG1C, conf->pll_b & 0xff); + ns2501_writeb(dvo, NS2501_REG1D, conf->pll_b >> 8); + ns2501_writeb(dvo, NS2501_REGC1, conf->hstart & 0xff); + ns2501_writeb(dvo, NS2501_REGC2, conf->hstart >> 8); + ns2501_writeb(dvo, NS2501_REGC3, conf->hstop & 0xff); + ns2501_writeb(dvo, NS2501_REGC4, conf->hstop >> 8); + ns2501_writeb(dvo, NS2501_REGC5, conf->vstart & 0xff); + ns2501_writeb(dvo, NS2501_REGC6, conf->vstart >> 8); + ns2501_writeb(dvo, NS2501_REGC7, conf->vstop & 0xff); + ns2501_writeb(dvo, NS2501_REGC8, conf->vstop >> 8); + ns2501_writeb(dvo, NS2501_REG80, conf->vsync & 0xff); + ns2501_writeb(dvo, NS2501_REG81, conf->vsync >> 8); + ns2501_writeb(dvo, NS2501_REG82, conf->vtotal & 0xff); + ns2501_writeb(dvo, NS2501_REG83, conf->vtotal >> 8); + ns2501_writeb(dvo, NS2501_REG98, conf->hpos & 0xff); + ns2501_writeb(dvo, NS2501_REG99, conf->hpos >> 8); + ns2501_writeb(dvo, NS2501_REG8E, conf->vpos & 0xff); + ns2501_writeb(dvo, NS2501_REG8F, conf->vpos >> 8); + ns2501_writeb(dvo, NS2501_REG9C, conf->voffs & 0xff); + ns2501_writeb(dvo, NS2501_REG9D, conf->voffs >> 8); + ns2501_writeb(dvo, NS2501_REGB8, conf->hscale & 0xff); + ns2501_writeb(dvo, NS2501_REGB9, conf->hscale >> 8); + ns2501_writeb(dvo, NS2501_REG10, conf->vscale & 0xff); + ns2501_writeb(dvo, NS2501_REG11, conf->vscale >> 8); + ns2501_writeb(dvo, NS2501_REGF9, conf->dither); + ns2501_writeb(dvo, NS2501_REG41, conf->syncb); + ns2501_writeb(dvo, NS2501_REGC0, conf->sync); } /* set the NS2501 power state */ @@ -579,34 +659,32 @@ static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable) DRM_DEBUG_KMS("Trying set the dpms of the DVO to %i\n", enable); if (enable) { - if (WARN_ON(ns->regs[83].offset != 0x08 || - ns->regs[84].offset != 0x41 || - ns->regs[85].offset != 0xc0)) - return; - - ns2501_writeb(dvo, 0xc0, ns->regs[85].value | 0x08); + ns2501_writeb(dvo, NS2501_REGC0, ns->conf->sync | 0x08); - ns2501_writeb(dvo, 0x41, ns->regs[84].value); + ns2501_writeb(dvo, NS2501_REG41, ns->conf->syncb); - ns2501_writeb(dvo, 0x34, 0x01); + ns2501_writeb(dvo, NS2501_REG34, NS2501_34_ENABLE_OUTPUT); msleep(15); - ns2501_writeb(dvo, 0x08, 0x35); - if (!(ns->regs[83].value & NS2501_8_BPAS)) - ns2501_writeb(dvo, 0x08, 0x31); + ns2501_writeb(dvo, NS2501_REG8, + ns->conf->conf | NS2501_8_BPAS); + if (!(ns->conf->conf & NS2501_8_BPAS)) + ns2501_writeb(dvo, NS2501_REG8, ns->conf->conf); msleep(200); - ns2501_writeb(dvo, 0x34, 0x03); + ns2501_writeb(dvo, NS2501_REG34, + NS2501_34_ENABLE_OUTPUT | NS2501_34_ENABLE_BACKLIGHT); - ns2501_writeb(dvo, 0xc0, ns->regs[85].value); + ns2501_writeb(dvo, NS2501_REGC0, ns->conf->sync); } else { - ns2501_writeb(dvo, 0x34, 0x01); + ns2501_writeb(dvo, NS2501_REG34, NS2501_34_ENABLE_OUTPUT); msleep(200); - ns2501_writeb(dvo, 0x08, 0x34); + ns2501_writeb(dvo, NS2501_REG8, NS2501_8_VEN | NS2501_8_HEN | + NS2501_8_BPAS); msleep(15); - ns2501_writeb(dvo, 0x34, 0x00); + ns2501_writeb(dvo, NS2501_REG34, 0x00); } } -- cgit v1.2.3 From de4de566f84b87f4d5f8265b11932088adb19896 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 23 Apr 2015 22:02:54 +0200 Subject: drm/i915: Update DRIVER_DATE to 20150423 Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 906f8851df4c..6c030639f8d9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -56,7 +56,7 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20150410" +#define DRIVER_DATE "20150423" #undef WARN_ON /* Many gcc seem to no see through this and fall over :( */ -- cgit v1.2.3 From 699ab787155d6760b396bfd66c403a6b6a3dfdc0 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 16:32:07 +0100 Subject: drm/i915: Silence compiler warning in dvo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/i915/intel_dvo.c: In function ‘intel_dvo_init’: drivers/gpu/drm/i915/intel_dvo.c:531:8: warning: array subscript is above array bounds [-Warray-bounds] gcc -v Using built-in specs. COLLECT_GCC=gcc COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-linux-gnu/4.7/lto-wrapper Target: x86_64-linux-gnu Configured with: ../src/configure -v --with-pkgversion='Debian 4.7.2-5' --with-bugurl=file:///usr/share/doc/gcc-4.7/README.Bugs --enable-languages=c,c++,go,fortran,objc,obj-c++ --prefix=/usr --program-suffix=-4.7 --enable-shared --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.7 --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-gnu-unique-object --enable-plugin --enable-objc-gc --with-arch-32=i586 --with-tune=generic --enable-checking=release --build=x86_64-linux-gnu --host=x86_64-linux-gnu --target=x86_64-linux-gnu Thread model: posix and gcc -v Using built-in specs. COLLECT_GCC=gcc COLLECT_LTO_WRAPPER=/usr/lib/gcc/i686-linux-gnu/4.8/lto-wrapper Target: i686-linux-gnu Configured with: ../src/configure -v --with-pkgversion='Ubuntu 4.8.2-19ubuntu1' --with-bugurl=file:///usr/share/doc/gcc-4.8/README.Bugs --enable-languages=c,c++,java,go,d,fortran,objc,obj-c++ --prefix=/usr --program-suffix=-4.8 --enable-shared --enable-linker-build-id --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.8 --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --enable-gnu-unique-object --disable-libmudflap --enable-plugin --with-system-zlib --disable-browser-plugin --enable-java-awt=gtk --enable-gtk-cairo --with-java-home=/usr/lib/jvm/java-1.5.0-gcj-4.8-i386/jre --enable-java-home --with-jvm-root-dir=/usr/lib/jvm/java-1.5.0-gcj-4.8-i386 --with-jvm-jar-dir=/usr/lib/jvm-exports/java-1.5.0-gcj-4.8-i386 --with-arch-directory=i386 --with-ecj-jar=/usr/share/java/eclipse-ecj.jar --enable-objc-gc --enable-targets=all --enable-multiarch --disable-werror --with-arch-32=i686 --with-multilib-list=m32,m64,mx32 --with-tune=generic --enable-checking=release --build=i686-linux-gnu --host=i686-linux-gnu --target=i686-linux-gnu Thread model: posix gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) Signed-off-by: Chris Wilson Cc: Ville Syrjälä Reviewed-by: Dave Gordon Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_dvo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index 7c9f85285aea..ece5bd754f85 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -496,7 +496,7 @@ void intel_dvo_init(struct drm_device *dev) int gpio; bool dvoinit; enum pipe pipe; - uint32_t dpll[2]; + uint32_t dpll[I915_MAX_PIPES]; /* Allow the I2C driver info to specify the GPIO to be used in * special cases, but otherwise default to what's defined -- cgit v1.2.3 From eeea3e67a4b2ab1df4e6e42e86d365fd14e070af Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 Apr 2015 14:29:39 +0300 Subject: drm/i915/hdmi: fix vlv infoframe port check Due to missing shifting, the vlv infoframe port check only works for port A. Fix it. Broken since introduction in commit 535afa2e9e3c1867460d6981d879b04d8b2b9ab3 Author: Jesse Barnes Date: Wed Apr 15 16:52:29 2015 -0700 drm/i915/vlv: check port in infoframe_enabled v2 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90059 Tested-by: xubin Tested-by: Ye Tian Reviewed-by: Jesse Barnes Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_hdmi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 56d1d13c075a..3b9c1176be5b 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -327,9 +327,8 @@ static bool vlv_infoframe_enabled(struct drm_encoder *encoder) struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); u32 val = I915_READ(reg); - u32 port = intel_dig_port->port; - if (port == (val & VIDEO_DIP_PORT_MASK)) + if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) return val & VIDEO_DIP_ENABLE; return false; -- cgit v1.2.3 From 052f62f78955106a14961f0d3d34c256e896303a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 Apr 2015 15:30:07 +0300 Subject: drm/i915/hdmi: check port in ibx_infoframe_enabled Add port check for ibx similar to vlv in commit 535afa2e9e3c1867460d6981d879b04d8b2b9ab3 Author: Jesse Barnes Date: Wed Apr 15 16:52:29 2015 -0700 drm/i915/vlv: check port in infoframe_enabled v2 Reviewed-by: Jesse Barnes Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_hdmi.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 3b9c1176be5b..f8d0d81da47d 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -223,10 +223,14 @@ static bool ibx_infoframe_enabled(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); u32 val = I915_READ(reg); - return val & VIDEO_DIP_ENABLE; + if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) + return val & VIDEO_DIP_ENABLE; + + return false; } static void cpt_write_infoframe(struct drm_encoder *encoder, -- cgit v1.2.3 From a1e6ad667550a9be173d0a0cfbba236d9252f837 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 17 Apr 2015 19:31:21 +0300 Subject: drm/i915: factor out ddi_get_encoder_port In the next patch we'll need to get at both the encoder's intel_digital_port object - which maybe NULL for a CRT - and it's port, so factor out this functionality. No functional change. Signed-off-by: Imre Deak Reviewed-by: Damien Lespiau Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_ddi.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 455d44b49c66..903d395b27cc 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -210,29 +210,39 @@ static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ }; -enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) +static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, + struct intel_digital_port **dig_port, + enum port *port) { struct drm_encoder *encoder = &intel_encoder->base; int type = intel_encoder->type; if (type == INTEL_OUTPUT_DP_MST) { - struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary; - return intel_dig_port->port; + *dig_port = enc_to_mst(encoder)->primary; + *port = (*dig_port)->port; } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { - struct intel_digital_port *intel_dig_port = - enc_to_dig_port(encoder); - return intel_dig_port->port; - + *dig_port = enc_to_dig_port(encoder); + *port = (*dig_port)->port; } else if (type == INTEL_OUTPUT_ANALOG) { - return PORT_E; - + *dig_port = NULL; + *port = PORT_E; } else { DRM_ERROR("Invalid DDI encoder type %d\n", type); BUG(); } } +enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) +{ + struct intel_digital_port *dig_port; + enum port port; + + ddi_get_encoder_port(intel_encoder, &dig_port, &port); + + return port; +} + static bool intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) { -- cgit v1.2.3 From faa0cdbec1c258896bff8bb59051bbada4fd6f09 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 17 Apr 2015 19:31:22 +0300 Subject: drm/i915: fix intel_prepare_ddi At the moment intel_prepare_ddi buffer will iterate through both MST and CRT encoders, which is incorrect. Neither of these encoder types have an embedding intel_digital_port object, so for these encoder types we will use random data when dereferencing the corresponding intel_digital_port->port field. Introduced in commit b403745c84592b26a0713e6944c2b109f6df5c82 Author: Damien Lespiau Date: Mon Aug 4 22:01:33 2014 +0100 drm/i915: Iterate through the initialized DDIs to prepare their buffers v2: - fix getting at the port for MST encoders too - make sure that intel_prepare_ddi_buffers() gets called for port E too (Paulo) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90067 Signed-off-by: Imre Deak Reviewed-by: Damien Lespiau Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 5 ----- drivers/gpu/drm/i915/intel_ddi.c | 28 ++++++++++++++++++---------- 2 files changed, 18 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6c030639f8d9..e08cd85eb519 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -251,11 +251,6 @@ enum hpd_pin { &dev->mode_config.connector_list, \ base.head) -#define for_each_digital_port(dev, digital_port) \ - list_for_each_entry(digital_port, \ - &dev->mode_config.encoder_list, \ - base.base.head) - #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ if ((intel_encoder)->base.crtc == (__crtc)) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 903d395b27cc..9c1e74a3a277 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -256,12 +256,11 @@ intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) * in either FDI or DP modes only, as HDMI connections will work with both * of those */ -static void intel_prepare_ddi_buffers(struct drm_device *dev, - struct intel_digital_port *intel_dig_port) +static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, + bool supports_hdmi) { struct drm_i915_private *dev_priv = dev->dev_private; u32 reg; - int port = intel_dig_port->port; int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, size; int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; @@ -272,7 +271,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, const struct ddi_buf_trans *ddi_translations; if (IS_BROXTON(dev)) { - if (!intel_dig_port_supports_hdmi(intel_dig_port)) + if (!supports_hdmi) return; /* Vswing programming for HDMI */ @@ -360,7 +359,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, reg += 4; } - if (!intel_dig_port_supports_hdmi(intel_dig_port)) + if (!supports_hdmi) return; /* Choose a good default if VBT is badly populated */ @@ -380,18 +379,27 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, */ void intel_prepare_ddi(struct drm_device *dev) { - struct intel_digital_port *intel_dig_port; + struct intel_encoder *intel_encoder; bool visited[I915_MAX_PORTS] = { 0, }; if (!HAS_DDI(dev)) return; - for_each_digital_port(dev, intel_dig_port) { - if (visited[intel_dig_port->port]) + for_each_intel_encoder(dev, intel_encoder) { + struct intel_digital_port *intel_dig_port; + enum port port; + bool supports_hdmi; + + ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port); + + if (visited[port]) continue; - intel_prepare_ddi_buffers(dev, intel_dig_port); - visited[intel_dig_port->port] = true; + supports_hdmi = intel_dig_port && + intel_dig_port_supports_hdmi(intel_dig_port); + + intel_prepare_ddi_buffers(dev, port, supports_hdmi); + visited[port] = true; } } -- cgit v1.2.3 From 245054a1fe33c06ad233e0d58a27ec7b64db9284 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 14 Apr 2015 17:35:22 +0200 Subject: drm/i915: Enable cmd parser to do secure batch promotion for aliasing ppgtt With the binding regression from the original full ppgtt patches fixed we can throw the switch. Yay! Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90190 Signed-off-by: Daniel Vetter Reviewed-by: Mika Kuoppala [Jani: tweaked commit title per Chris' suggestion] Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index cfdc8c6073aa..d2e21c549756 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1558,12 +1558,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, * dispatch_execbuffer implementations. We specifically * don't want that set when the command parser is * enabled. - * - * FIXME: with aliasing ppgtt, buffers that should only - * be in ggtt still end up in the aliasing ppgtt. remove - * this check when that is fixed. */ - if (USES_FULL_PPGTT(dev)) + if (USES_PPGTT(dev)) dispatch_flags |= I915_DISPATCH_SECURE; exec_start = 0; -- cgit v1.2.3 From 75d04a3773ecee617847de963ae4195d6aa74c28 Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Tue, 28 Apr 2015 17:56:17 +0300 Subject: drm/i915/gtt: Allocate va range only if vma is not bound When we have bound vma into an address space, the layout of page table structures is immutable. So we can be absolutely certain that if vma is already bound, there is no need to (re)allocate a virtual address range for it. v2: - add sanity checks and remove superfluous GLOBAL_BIND set - we might do update for an unbound vma (Chris) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90224 Testcase: igt/gem_exec_big #bdw Reported-by: Chris Wilson Cc: Chris Wilson Cc: Michel Thierry Cc: Daniel Vetter Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 6fae6bdde156..9d3852c521c7 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1928,8 +1928,6 @@ static int ggtt_bind_vma(struct i915_vma *vma, vma->vm->insert_entries(vma->vm, pages, vma->node.start, cache_level, pte_flags); - - vma->bound |= GLOBAL_BIND; } if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) { @@ -2804,21 +2802,13 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma) int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) { - int ret = 0; - u32 bind_flags = 0; - - if (vma->vm->allocate_va_range) { - trace_i915_va_alloc(vma->vm, vma->node.start, - vma->node.size, - VM_TO_TRACE_NAME(vma->vm)); + int ret; + u32 bind_flags; - ret = vma->vm->allocate_va_range(vma->vm, - vma->node.start, - vma->node.size); - if (ret) - return ret; - } + if (WARN_ON(flags == 0)) + return -EINVAL; + bind_flags = 0; if (flags & PIN_GLOBAL) bind_flags |= GLOBAL_BIND; if (flags & PIN_USER) @@ -2829,8 +2819,23 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, else bind_flags &= ~vma->bound; - if (bind_flags) - ret = vma->vm->bind_vma(vma, cache_level, bind_flags); + if (bind_flags == 0) + return 0; + + if (vma->bound == 0 && vma->vm->allocate_va_range) { + trace_i915_va_alloc(vma->vm, + vma->node.start, + vma->node.size, + VM_TO_TRACE_NAME(vma->vm)); + + ret = vma->vm->allocate_va_range(vma->vm, + vma->node.start, + vma->node.size); + if (ret) + return ret; + } + + ret = vma->vm->bind_vma(vma, cache_level, bind_flags); if (ret) return ret; -- cgit v1.2.3 From 99264a61dfcda41d86d0960cf2d4c0fc2758a773 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 15 Apr 2015 19:34:43 +0200 Subject: drm/vblank: Fixup and document timestamp update/read barriers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was a bit too much cargo-culted, so lets make it solid: - vblank->count doesn't need to be an atomic, writes are always done under the protection of dev->vblank_time_lock. Switch to an unsigned long instead and update comments. Note that atomic_read is just a normal read of a volatile variable, so no need to audit all the read-side access specifically. - The barriers for the vblank counter seqlock weren't complete: The read-side was missing the first barrier between the counter read and the timestamp read, it only had a barrier between the ts and the counter read. We need both. - Barriers weren't properly documented. Since barriers only work if you have them on boths sides of the transaction it's prudent to reference where the other side is. To avoid duplicating the write-side comment 3 times extract a little store_vblank() helper. In that helper also assert that we do indeed hold dev->vblank_time_lock, since in some cases the lock is acquired a few functions up in the callchain. Spotted while reviewing a patch from Chris Wilson to add a fastpath to the vblank_wait ioctl. v2: Add comment to better explain how store_vblank works, suggested by Chris. v3: Peter noticed that as-is the 2nd smp_wmb is redundant with the implicit barrier in the spin_unlock. But that can only be proven by auditing all callers and my point in extracting this little helper was to localize all the locking into just one place. Hence I think that additional optimization is too risky. Cc: Chris Wilson Cc: Mario Kleiner Cc: Ville Syrjälä Cc: Michel Dänzer Cc: Peter Hurley Reviewed-by: Chris Wilson Reviewed-and-tested-by: Mario Kleiner Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_irq.c | 95 +++++++++++++++++++++++++---------------------- include/drm/drmP.h | 8 +++- 2 files changed, 57 insertions(+), 46 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index c8a34476570a..8694b77d0002 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -74,6 +74,36 @@ module_param_named(vblankoffdelay, drm_vblank_offdelay, int, 0600); module_param_named(timestamp_precision_usec, drm_timestamp_precision, int, 0600); module_param_named(timestamp_monotonic, drm_timestamp_monotonic, int, 0600); +static void store_vblank(struct drm_device *dev, int crtc, + unsigned vblank_count_inc, + struct timeval *t_vblank) +{ + struct drm_vblank_crtc *vblank = &dev->vblank[crtc]; + u32 tslot; + + assert_spin_locked(&dev->vblank_time_lock); + + if (t_vblank) { + /* All writers hold the spinlock, but readers are serialized by + * the latching of vblank->count below. + */ + tslot = vblank->count + vblank_count_inc; + vblanktimestamp(dev, crtc, tslot) = *t_vblank; + } + + /* + * vblank timestamp updates are protected on the write side with + * vblank_time_lock, but on the read side done locklessly using a + * sequence-lock on the vblank counter. Ensure correct ordering using + * memory barrriers. We need the barrier both before and also after the + * counter update to synchronize with the next timestamp write. + * The read-side barriers for this are in drm_vblank_count_and_time. + */ + smp_wmb(); + vblank->count += vblank_count_inc; + smp_wmb(); +} + /** * drm_update_vblank_count - update the master vblank counter * @dev: DRM device @@ -93,7 +123,7 @@ module_param_named(timestamp_monotonic, drm_timestamp_monotonic, int, 0600); static void drm_update_vblank_count(struct drm_device *dev, int crtc) { struct drm_vblank_crtc *vblank = &dev->vblank[crtc]; - u32 cur_vblank, diff, tslot; + u32 cur_vblank, diff; bool rc; struct timeval t_vblank; @@ -129,18 +159,12 @@ static void drm_update_vblank_count(struct drm_device *dev, int crtc) if (diff == 0) return; - /* Reinitialize corresponding vblank timestamp if high-precision query - * available. Skip this step if query unsupported or failed. Will - * reinitialize delayed at next vblank interrupt in that case. + /* + * Only reinitialize corresponding vblank timestamp if high-precision query + * available and didn't fail. Will reinitialize delayed at next vblank + * interrupt in that case. */ - if (rc) { - tslot = atomic_read(&vblank->count) + diff; - vblanktimestamp(dev, crtc, tslot) = t_vblank; - } - - smp_mb__before_atomic(); - atomic_add(diff, &vblank->count); - smp_mb__after_atomic(); + store_vblank(dev, crtc, diff, rc ? &t_vblank : NULL); } /* @@ -218,7 +242,7 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc) /* Compute time difference to stored timestamp of last vblank * as updated by last invocation of drm_handle_vblank() in vblank irq. */ - vblcount = atomic_read(&vblank->count); + vblcount = vblank->count; diff_ns = timeval_to_ns(&tvblank) - timeval_to_ns(&vblanktimestamp(dev, crtc, vblcount)); @@ -234,17 +258,8 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc) * available. In that case we can't account for this and just * hope for the best. */ - if (vblrc && (abs64(diff_ns) > 1000000)) { - /* Store new timestamp in ringbuffer. */ - vblanktimestamp(dev, crtc, vblcount + 1) = tvblank; - - /* Increment cooked vblank count. This also atomically commits - * the timestamp computed above. - */ - smp_mb__before_atomic(); - atomic_inc(&vblank->count); - smp_mb__after_atomic(); - } + if (vblrc && (abs64(diff_ns) > 1000000)) + store_vblank(dev, crtc, 1, &tvblank); spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags); } @@ -852,7 +867,7 @@ u32 drm_vblank_count(struct drm_device *dev, int crtc) if (WARN_ON(crtc >= dev->num_crtcs)) return 0; - return atomic_read(&vblank->count); + return vblank->count; } EXPORT_SYMBOL(drm_vblank_count); @@ -897,16 +912,17 @@ u32 drm_vblank_count_and_time(struct drm_device *dev, int crtc, if (WARN_ON(crtc >= dev->num_crtcs)) return 0; - /* Read timestamp from slot of _vblank_time ringbuffer - * that corresponds to current vblank count. Retry if - * count has incremented during readout. This works like - * a seqlock. + /* + * Vblank timestamps are read lockless. To ensure consistency the vblank + * counter is rechecked and ordering is ensured using memory barriers. + * This works like a seqlock. The write-side barriers are in store_vblank. */ do { - cur_vblank = atomic_read(&vblank->count); + cur_vblank = vblank->count; + smp_rmb(); *vblanktime = vblanktimestamp(dev, crtc, cur_vblank); smp_rmb(); - } while (cur_vblank != atomic_read(&vblank->count)); + } while (cur_vblank != vblank->count); return cur_vblank; } @@ -1715,7 +1731,7 @@ bool drm_handle_vblank(struct drm_device *dev, int crtc) */ /* Get current timestamp and count. */ - vblcount = atomic_read(&vblank->count); + vblcount = vblank->count; drm_get_last_vbltimestamp(dev, crtc, &tvblank, DRM_CALLED_FROM_VBLIRQ); /* Compute time difference to timestamp of last vblank */ @@ -1731,20 +1747,11 @@ bool drm_handle_vblank(struct drm_device *dev, int crtc) * e.g., due to spurious vblank interrupts. We need to * ignore those for accounting. */ - if (abs64(diff_ns) > DRM_REDUNDANT_VBLIRQ_THRESH_NS) { - /* Store new timestamp in ringbuffer. */ - vblanktimestamp(dev, crtc, vblcount + 1) = tvblank; - - /* Increment cooked vblank count. This also atomically commits - * the timestamp computed above. - */ - smp_mb__before_atomic(); - atomic_inc(&vblank->count); - smp_mb__after_atomic(); - } else { + if (abs64(diff_ns) > DRM_REDUNDANT_VBLIRQ_THRESH_NS) + store_vblank(dev, crtc, 1, &tvblank); + else DRM_DEBUG("crtc %d: Redundant vblirq ignored. diff_ns = %d\n", crtc, (int) diff_ns); - } spin_unlock(&dev->vblank_time_lock); diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 62c40777c009..4c31a2cc5a33 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -686,9 +686,13 @@ struct drm_pending_vblank_event { struct drm_vblank_crtc { struct drm_device *dev; /* pointer to the drm_device */ wait_queue_head_t queue; /**< VBLANK wait queue */ - struct timeval time[DRM_VBLANKTIME_RBSIZE]; /**< timestamp of current count */ struct timer_list disable_timer; /* delayed disable timer */ - atomic_t count; /**< number of VBLANK interrupts */ + + /* vblank counter, protected by dev->vblank_time_lock for writes */ + unsigned long count; + /* vblank timestamps, protected by dev->vblank_time_lock for writes */ + struct timeval time[DRM_VBLANKTIME_RBSIZE]; + atomic_t refcount; /* number of users of vblank interruptsper crtc */ u32 last; /* protected by dev->vbl_lock, used */ /* for wraparound handling */ -- cgit v1.2.3 From 5a8b21b222296d6bc9be0783456838e6ab6e48e4 Mon Sep 17 00:00:00 2001 From: Mario Kleiner Date: Mon, 4 May 2015 06:29:45 +0200 Subject: drm: Prevent invalid use of vblank_disable_immediate. (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For a kms driver to support immediate disable of vblank irq's reliably without introducing off by one errors or other mayhem for clients, it must not only support a hardware vblank counter query, but also high precision vblank timestamping, so vblank count and timestamp can be instantaneously reinitialzed to valid values. Additionally the exposed hardware counter must behave as if it is incrementing at leading edge of vblank to avoid off by one errors during reinitialization of the counter while the display happens to be inside or close to vblank. Check during drm_vblank_init that a driver which claims to be capable of vblank_disable_immediate at least supports high precision timestamping and prevent use of instant disable if that isn't present as a minimum requirement. v2: Changed from DRM_ERROR to DRM_INFO and made message more clear, as suggested by Michel Dänzer. Signed-off-by: Mario Kleiner Reviewed-by: Michel Dänzer Cc: Dave Airlie Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_irq.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index 8694b77d0002..e756485805b6 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -352,6 +352,13 @@ int drm_vblank_init(struct drm_device *dev, int num_crtcs) else DRM_INFO("No driver support for vblank timestamp query.\n"); + /* Must have precise timestamping for reliable vblank instant disable */ + if (dev->vblank_disable_immediate && !dev->driver->get_vblank_timestamp) { + dev->vblank_disable_immediate = false; + DRM_INFO("Setting vblank_disable_immediate to false because " + "get_vblank_timestamp == NULL\n"); + } + dev->vblank_disable_allowed = false; return 0; -- cgit v1.2.3 From d66a1e38280c42a06691e3df23f896273996255c Mon Sep 17 00:00:00 2001 From: Mario Kleiner Date: Mon, 4 May 2015 06:29:46 +0200 Subject: drm: Zero out invalid vblank timestamp in drm_update_vblank_count. (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 844b03f27739135fe1fed2fef06da0ffc4c7a081 we make sure that after vblank irq off, we return the last valid (vblank count, vblank timestamp) pair to clients, e.g., during modesets, which is good. An overlooked side effect of that commit for kms drivers without support for precise vblank timestamping is that at vblank irq enable, when we update the vblank counter from the hw counter, we can't update the corresponding vblank timestamp, so now we have a totally mismatched timestamp for the new count to confuse clients. Restore old client visible behaviour from before Linux 3.18, but zero out the timestamp at vblank counter update (instead of disable as in original implementation) if we can't generate a meaningful timestamp immediately for the new vblank counter. This will fix this regression, so callers know they need to retry again later if they need a valid timestamp, but at the same time preserves the improvements made in the commit mentioned above. v2: Rebased on top of Daniel Vetter's fixup and documentation patch for timestamp updates. Drop request for stable kernel backport as this would be more difficult, unless the original patch would get applied to stable kernels. Signed-off-by: Mario Kleiner Cc: Ville Syrjälä Cc: Daniel Vetter Cc: Dave Airlie Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_irq.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index e756485805b6..1967e7fc9805 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -161,10 +161,13 @@ static void drm_update_vblank_count(struct drm_device *dev, int crtc) /* * Only reinitialize corresponding vblank timestamp if high-precision query - * available and didn't fail. Will reinitialize delayed at next vblank - * interrupt in that case. + * available and didn't fail. Otherwise reinitialize delayed at next vblank + * interrupt and assign 0 for now, to mark the vblanktimestamp as invalid. */ - store_vblank(dev, crtc, diff, rc ? &t_vblank : NULL); + if (!rc) + t_vblank = (struct timeval) {0, 0}; + + store_vblank(dev, crtc, diff, &t_vblank); } /* -- cgit v1.2.3 From 337eb43c8d0000fef80b88e43fee7752a84afab2 Mon Sep 17 00:00:00 2001 From: Mario Kleiner Date: Mon, 4 May 2015 06:29:47 +0200 Subject: drm/qxl: Fix qxl_noop_get_vblank_counter() This breaks under the vblank timestamp cleanup patch by Daniel Vetter. Also it is pointless to return anything but zero (or any other constant) if the function doesn't actually query a hw vblank counter. The bogus return of the current drm vblank counter via direct readout or via drm_vblank_count() is found in many of the new kms drivers, but it does exactly nothing different from returning any arbitrary constant - it's a no operation. Let's simply return 0 - Easy and fast. Signed-off-by: Mario Kleiner Cc: Dave Airlie Signed-off-by: Daniel Vetter --- drivers/gpu/drm/qxl/qxl_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c index e2d07085b6a5..83f6f0b5e9ef 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.c +++ b/drivers/gpu/drm/qxl/qxl_drv.c @@ -198,7 +198,7 @@ static int qxl_pm_restore(struct device *dev) static u32 qxl_noop_get_vblank_counter(struct drm_device *dev, int crtc) { - return dev->vblank[crtc].count.counter; + return 0; } static int qxl_noop_enable_vblank(struct drm_device *dev, int crtc) -- cgit v1.2.3 From 3671c580e55955e61072a6e6d0d9567abdd80b5c Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Mon, 4 May 2015 15:40:52 +0200 Subject: drm/atomic-helper: Really recover pre-atomic plane/cursor behavior I've fumbled this in commit f02ad907cd9e7fe3a6405d2d005840912f1ed258 Author: Daniel Vetter Date: Thu Jan 22 16:36:23 2015 +0100 drm/atomic-helpers: Recover full cursor plane behaviour and accidentally put the assignment for legacy_cursor_upate after the atomic commit, where it is pretty useless. Reported-by: Maarten Lankhorst Cc: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index d536817699c1..9f216ff61af3 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -1310,13 +1310,13 @@ retry: plane_state->src_h = src_h; plane_state->src_w = src_w; + if (plane == crtc->cursor) + state->legacy_cursor_update = true; + ret = drm_atomic_commit(state); if (ret != 0) goto fail; - if (plane == crtc->cursor) - state->legacy_cursor_update = true; - /* Driver takes ownership of state on successful commit. */ return 0; fail: -- cgit v1.2.3 From ed1817036bd6d83829039543c9fe4aa94acc7c39 Mon Sep 17 00:00:00 2001 From: Oleg Drokin Date: Mon, 27 Apr 2015 11:36:46 -0400 Subject: drm: fix a memleak on mutex failure path Need to free just allocated ctx allocation if we cannot get our config mutex. This one has been flagged by kbuild bot all the way back in August, but somehow nobody picked it up: https://lists.01.org/pipermail/kbuild/2014-August/001691.html In addition there is another failure path that leaks the same ctx reference that is fixed. Found with smatch. Signed-off-by: Oleg Drokin CC: Daniel Vetter Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_modeset_lock.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_modeset_lock.c b/drivers/gpu/drm/drm_modeset_lock.c index 51cc47d827d8..c0a5cd8c5262 100644 --- a/drivers/gpu/drm/drm_modeset_lock.c +++ b/drivers/gpu/drm/drm_modeset_lock.c @@ -80,8 +80,10 @@ int __drm_modeset_lock_all(struct drm_device *dev, return -ENOMEM; if (trylock) { - if (!mutex_trylock(&config->mutex)) - return -EBUSY; + if (!mutex_trylock(&config->mutex)) { + ret = -EBUSY; + goto out; + } } else { mutex_lock(&config->mutex); } @@ -114,6 +116,8 @@ fail: goto retry; } +out: + kfree(ctx); return ret; } EXPORT_SYMBOL(__drm_modeset_lock_all); -- cgit v1.2.3 From acab18b5c3a7025640abc84ace5e94c76ebd3d10 Mon Sep 17 00:00:00 2001 From: David Herrmann Date: Mon, 4 May 2015 16:05:12 +0200 Subject: drm: drop unused 'magicfree' list This list is write-only. It's never used for read-access, so no reason to keep it around. Drop it! Signed-off-by: David Herrmann Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_auth.c | 3 --- drivers/gpu/drm/drm_drv.c | 1 - include/drm/drmP.h | 2 -- 3 files changed, 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c index fc8e8aaa34fb..8a37524d0867 100644 --- a/drivers/gpu/drm/drm_auth.c +++ b/drivers/gpu/drm/drm_auth.c @@ -37,7 +37,6 @@ #include "drm_internal.h" struct drm_magic_entry { - struct list_head head; struct drm_hash_item hash_item; struct drm_file *priv; }; @@ -93,7 +92,6 @@ static int drm_add_magic(struct drm_master *master, struct drm_file *priv, entry->hash_item.key = (unsigned long)magic; mutex_lock(&dev->struct_mutex); drm_ht_insert_item(&master->magiclist, &entry->hash_item); - list_add_tail(&entry->head, &master->magicfree); mutex_unlock(&dev->struct_mutex); return 0; @@ -123,7 +121,6 @@ int drm_remove_magic(struct drm_master *master, drm_magic_t magic) } pt = drm_hash_entry(hash, struct drm_magic_entry, hash_item); drm_ht_remove_item(&master->magiclist, hash); - list_del(&pt->head); mutex_unlock(&dev->struct_mutex); kfree(pt); diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index 48f7359e2a6b..26ed9feb3cfd 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -109,7 +109,6 @@ struct drm_master *drm_master_create(struct drm_minor *minor) kfree(master); return NULL; } - INIT_LIST_HEAD(&master->magicfree); master->minor = minor; return master; diff --git a/include/drm/drmP.h b/include/drm/drmP.h index 4c31a2cc5a33..e2b101b49112 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -356,7 +356,6 @@ struct drm_lock_data { * @unique: Unique identifier: e.g. busid. Protected by drm_global_mutex. * @unique_len: Length of unique field. Protected by drm_global_mutex. * @magiclist: Hash of used authentication tokens. Protected by struct_mutex. - * @magicfree: List of used authentication tokens. Protected by struct_mutex. * @lock: DRI lock information. * @driver_priv: Pointer to driver-private information. */ @@ -366,7 +365,6 @@ struct drm_master { char *unique; int unique_len; struct drm_open_hash magiclist; - struct list_head magicfree; struct drm_lock_data lock; void *driver_priv; }; -- cgit v1.2.3 From 32e7b94a3fa8e137aab9f2c65dff86be73245fc8 Mon Sep 17 00:00:00 2001 From: David Herrmann Date: Mon, 4 May 2015 21:01:30 +0200 Subject: drm: simplify authentication management The magic auth tokens we have are a simple map from cyclic IDs to drm_file objects. Remove all the old bulk of code and replace it with a simple, direct IDR. The previous behavior is kept. Especially calling authmagic multiple times on the same magic results in EINVAL except on the first call. The only difference in behavior is that we never allocate IDs multiple times as long as a client has its FD open. v2: - Fix return code of GetMagic() - Use non-cyclic IDR allocator - fix off-by-one in "magic > INT_MAX" sanity check v3: - drop redundant "magic > INT_MAX" check Signed-off-by: David Herrmann Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_auth.c | 175 +++++++++-------------------------------- drivers/gpu/drm/drm_drv.c | 12 +-- drivers/gpu/drm/drm_fops.c | 7 +- drivers/gpu/drm/drm_internal.h | 1 - include/drm/drmP.h | 4 +- 5 files changed, 42 insertions(+), 157 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c index 8a37524d0867..50d0baa06db0 100644 --- a/drivers/gpu/drm/drm_auth.c +++ b/drivers/gpu/drm/drm_auth.c @@ -1,11 +1,3 @@ -/** - * \file drm_auth.c - * IOCTLs for authentication - * - * \author Rickard E. (Rik) Faith - * \author Gareth Hughes - */ - /* * Created: Tue Feb 2 08:37:54 1999 by faith@valinux.com * @@ -13,6 +5,9 @@ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights Reserved. * + * Author Rickard E. (Rik) Faith + * Author Gareth Hughes + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation @@ -36,151 +31,47 @@ #include #include "drm_internal.h" -struct drm_magic_entry { - struct drm_hash_item hash_item; - struct drm_file *priv; -}; - -/** - * Find the file with the given magic number. - * - * \param dev DRM device. - * \param magic magic number. - * - * Searches in drm_device::magiclist within all files with the same hash key - * the one with matching magic number, while holding the drm_device::struct_mutex - * lock. - */ -static struct drm_file *drm_find_file(struct drm_master *master, drm_magic_t magic) -{ - struct drm_file *retval = NULL; - struct drm_magic_entry *pt; - struct drm_hash_item *hash; - struct drm_device *dev = master->minor->dev; - - mutex_lock(&dev->struct_mutex); - if (!drm_ht_find_item(&master->magiclist, (unsigned long)magic, &hash)) { - pt = drm_hash_entry(hash, struct drm_magic_entry, hash_item); - retval = pt->priv; - } - mutex_unlock(&dev->struct_mutex); - return retval; -} - -/** - * Adds a magic number. - * - * \param dev DRM device. - * \param priv file private data. - * \param magic magic number. - * - * Creates a drm_magic_entry structure and appends to the linked list - * associated the magic number hash key in drm_device::magiclist, while holding - * the drm_device::struct_mutex lock. - */ -static int drm_add_magic(struct drm_master *master, struct drm_file *priv, - drm_magic_t magic) -{ - struct drm_magic_entry *entry; - struct drm_device *dev = master->minor->dev; - DRM_DEBUG("%d\n", magic); - - entry = kzalloc(sizeof(*entry), GFP_KERNEL); - if (!entry) - return -ENOMEM; - entry->priv = priv; - entry->hash_item.key = (unsigned long)magic; - mutex_lock(&dev->struct_mutex); - drm_ht_insert_item(&master->magiclist, &entry->hash_item); - mutex_unlock(&dev->struct_mutex); - - return 0; -} - -/** - * Remove a magic number. - * - * \param dev DRM device. - * \param magic magic number. - * - * Searches and unlinks the entry in drm_device::magiclist with the magic - * number hash key, while holding the drm_device::struct_mutex lock. - */ -int drm_remove_magic(struct drm_master *master, drm_magic_t magic) -{ - struct drm_magic_entry *pt; - struct drm_hash_item *hash; - struct drm_device *dev = master->minor->dev; - - DRM_DEBUG("%d\n", magic); - - mutex_lock(&dev->struct_mutex); - if (drm_ht_find_item(&master->magiclist, (unsigned long)magic, &hash)) { - mutex_unlock(&dev->struct_mutex); - return -EINVAL; - } - pt = drm_hash_entry(hash, struct drm_magic_entry, hash_item); - drm_ht_remove_item(&master->magiclist, hash); - mutex_unlock(&dev->struct_mutex); - - kfree(pt); - - return 0; -} - /** - * Get a unique magic number (ioctl). + * drm_getmagic - Get unique magic of a client + * @dev: DRM device to operate on + * @data: ioctl data containing the drm_auth object + * @file_priv: DRM file that performs the operation * - * \param inode device inode. - * \param file_priv DRM file private. - * \param cmd command. - * \param arg pointer to a resulting drm_auth structure. - * \return zero on success, or a negative number on failure. + * This looks up the unique magic of the passed client and returns it. If the + * client did not have a magic assigned, yet, a new one is registered. The magic + * is stored in the passed drm_auth object. * - * If there is a magic number in drm_file::magic then use it, otherwise - * searches an unique non-zero magic number and add it associating it with \p - * file_priv. - * This ioctl needs protection by the drm_global_mutex, which protects - * struct drm_file::magic and struct drm_magic_entry::priv. + * Returns: 0 on success, negative error code on failure. */ int drm_getmagic(struct drm_device *dev, void *data, struct drm_file *file_priv) { - static drm_magic_t sequence = 0; - static DEFINE_SPINLOCK(lock); struct drm_auth *auth = data; + int ret = 0; - /* Find unique magic */ - if (file_priv->magic) { - auth->magic = file_priv->magic; - } else { - do { - spin_lock(&lock); - if (!sequence) - ++sequence; /* reserve 0 */ - auth->magic = sequence++; - spin_unlock(&lock); - } while (drm_find_file(file_priv->master, auth->magic)); - file_priv->magic = auth->magic; - drm_add_magic(file_priv->master, file_priv, auth->magic); + mutex_lock(&dev->struct_mutex); + if (!file_priv->magic) { + ret = idr_alloc(&file_priv->master->magic_map, file_priv, + 1, 0, GFP_KERNEL); + if (ret >= 0) + file_priv->magic = ret; } + auth->magic = file_priv->magic; + mutex_unlock(&dev->struct_mutex); DRM_DEBUG("%u\n", auth->magic); - return 0; + return ret < 0 ? ret : 0; } /** - * Authenticate with a magic. + * drm_authmagic - Authenticate client with a magic + * @dev: DRM device to operate on + * @data: ioctl data containing the drm_auth object + * @file_priv: DRM file that performs the operation * - * \param inode device inode. - * \param file_priv DRM file private. - * \param cmd command. - * \param arg pointer to a drm_auth structure. - * \return zero if authentication successed, or a negative number otherwise. + * This looks up a DRM client by the passed magic and authenticates it. * - * Checks if \p file_priv is associated with the magic number passed in \arg. - * This ioctl needs protection by the drm_global_mutex, which protects - * struct drm_file::magic and struct drm_magic_entry::priv. + * Returns: 0 on success, negative error code on failure. */ int drm_authmagic(struct drm_device *dev, void *data, struct drm_file *file_priv) @@ -189,10 +80,14 @@ int drm_authmagic(struct drm_device *dev, void *data, struct drm_file *file; DRM_DEBUG("%u\n", auth->magic); - if ((file = drm_find_file(file_priv->master, auth->magic))) { + + mutex_lock(&dev->struct_mutex); + file = idr_find(&file_priv->master->magic_map, auth->magic); + if (file) { file->authenticated = 1; - drm_remove_magic(file_priv->master, auth->magic); - return 0; + idr_replace(&file_priv->master->magic_map, NULL, auth->magic); } - return -EINVAL; + mutex_unlock(&dev->struct_mutex); + + return file ? 0 : -EINVAL; } diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index 26ed9feb3cfd..88b594c0593a 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -92,8 +92,6 @@ void drm_ut_debug_printk(const char *function_name, const char *format, ...) } EXPORT_SYMBOL(drm_ut_debug_printk); -#define DRM_MAGIC_HASH_ORDER 4 /**< Size of key hash table. Must be power of 2. */ - struct drm_master *drm_master_create(struct drm_minor *minor) { struct drm_master *master; @@ -105,10 +103,7 @@ struct drm_master *drm_master_create(struct drm_minor *minor) kref_init(&master->refcount); spin_lock_init(&master->lock.spinlock); init_waitqueue_head(&master->lock.lock_queue); - if (drm_ht_create(&master->magiclist, DRM_MAGIC_HASH_ORDER)) { - kfree(master); - return NULL; - } + idr_init(&master->magic_map); master->minor = minor; return master; @@ -143,10 +138,9 @@ static void drm_master_destroy(struct kref *kref) master->unique = NULL; master->unique_len = 0; } - - drm_ht_remove(&master->magiclist); - mutex_unlock(&dev->struct_mutex); + + idr_destroy(&master->magic_map); kfree(master); } diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c index 076dd606b580..0f6a5c8801e3 100644 --- a/drivers/gpu/drm/drm_fops.c +++ b/drivers/gpu/drm/drm_fops.c @@ -380,6 +380,8 @@ int drm_release(struct inode *inode, struct file *filp) mutex_lock(&dev->struct_mutex); list_del(&file_priv->lhead); + if (file_priv->magic) + idr_remove(&file_priv->master->magic_map, file_priv->magic); mutex_unlock(&dev->struct_mutex); if (dev->driver->preclose) @@ -394,11 +396,6 @@ int drm_release(struct inode *inode, struct file *filp) (long)old_encode_dev(file_priv->minor->kdev->devt), dev->open_count); - /* Release any auth tokens that might point to this file_priv, - (do that under the drm_global_mutex) */ - if (file_priv->magic) - (void) drm_remove_magic(file_priv->master, file_priv->magic); - /* if the master has gone away we can't do anything with the lock */ if (file_priv->minor->master) drm_master_release(dev, filp); diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h index 12a61d706827..059af01bd07a 100644 --- a/drivers/gpu/drm/drm_internal.h +++ b/drivers/gpu/drm/drm_internal.h @@ -69,7 +69,6 @@ int drm_getmagic(struct drm_device *dev, void *data, struct drm_file *file_priv); int drm_authmagic(struct drm_device *dev, void *data, struct drm_file *file_priv); -int drm_remove_magic(struct drm_master *master, drm_magic_t magic); /* drm_sysfs.c */ extern struct class *drm_class; diff --git a/include/drm/drmP.h b/include/drm/drmP.h index e2b101b49112..df6d9970d9a4 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -355,7 +355,7 @@ struct drm_lock_data { * @minor: Link back to minor char device we are master for. Immutable. * @unique: Unique identifier: e.g. busid. Protected by drm_global_mutex. * @unique_len: Length of unique field. Protected by drm_global_mutex. - * @magiclist: Hash of used authentication tokens. Protected by struct_mutex. + * @magic_map: Map of used authentication tokens. Protected by struct_mutex. * @lock: DRI lock information. * @driver_priv: Pointer to driver-private information. */ @@ -364,7 +364,7 @@ struct drm_master { struct drm_minor *minor; char *unique; int unique_len; - struct drm_open_hash magiclist; + struct idr magic_map; struct drm_lock_data lock; void *driver_priv; }; -- cgit v1.2.3 From 4a324d33bfe95a279d4c7370d84087d3e773e799 Mon Sep 17 00:00:00 2001 From: David Herrmann Date: Mon, 4 May 2015 16:05:14 +0200 Subject: drm: simplify master cleanup In drm_master_destroy() we _free_ the master object. There is no reason to hold any locks while dropping its static members, nor do we have to reset it to 0. Furthermore, kfree() already does NULL checks, so call it directly on master->unique and drop the redundant reset-code. Signed-off-by: David Herrmann Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_drv.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index 88b594c0593a..3b3c4f537e95 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -132,15 +132,10 @@ static void drm_master_destroy(struct kref *kref) r_list = NULL; } } - - if (master->unique) { - kfree(master->unique); - master->unique = NULL; - master->unique_len = 0; - } mutex_unlock(&dev->struct_mutex); idr_destroy(&master->magic_map); + kfree(master->unique); kfree(master); } -- cgit v1.2.3 From c0fe07aa50befe2e6e6525181e2080377a1c1494 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 5 May 2015 13:52:49 +0200 Subject: drm/qxl: rewrite framebuffer support Completely different approach: Instead of encoding each and every framebuffer update as spice operation simply update the shadow framebuffer and maintain a dirty rectangle. Also schedule a worker to push an update for the dirty rectangle as spice operation. Usually a bunch of dirty rectangle updates are collected before the worker actually runs. What changes: Updates get batched now. Instead of sending tons of small updates a few large ones are sent. When the same region is updated multiple times within a short timeframe (scrolling multiple lines for example) we send a single update only. Spice server has an easier job now: The dependency tree for display operations which spice server maintains for lazy rendering is alot smaller now. Spice server's image compression probably works better too with the larger image blits. Net effect: framebuffer console @ qxldrmfb is an order of magnitude faster now. Signed-off-by: Gerd Hoffmann Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_fb.c | 275 +++++++++---------------------------------- 1 file changed, 57 insertions(+), 218 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_fb.c b/drivers/gpu/drm/qxl/qxl_fb.c index f778c0e8ae3c..6b6e57e8c2d6 100644 --- a/drivers/gpu/drm/qxl/qxl_fb.c +++ b/drivers/gpu/drm/qxl/qxl_fb.c @@ -37,21 +37,6 @@ #define QXL_DIRTY_DELAY (HZ / 30) -#define QXL_FB_OP_FILLRECT 1 -#define QXL_FB_OP_COPYAREA 2 -#define QXL_FB_OP_IMAGEBLIT 3 - -struct qxl_fb_op { - struct list_head head; - int op_type; - union { - struct fb_fillrect fr; - struct fb_copyarea ca; - struct fb_image ib; - } op; - void *img_data; -}; - struct qxl_fbdev { struct drm_fb_helper helper; struct qxl_framebuffer qfb; @@ -66,7 +51,6 @@ struct qxl_fbdev { /* dirty memory logging */ struct { spinlock_t lock; - bool active; unsigned x1; unsigned y1; unsigned x2; @@ -105,23 +89,33 @@ static void qxl_fb_dirty_flush(struct fb_info *info) struct qxl_device *qdev = qfbdev->qdev; struct qxl_fb_image qxl_fb_image; struct fb_image *image = &qxl_fb_image.fb_image; + unsigned long flags; u32 x1, x2, y1, y2; /* TODO: hard coding 32 bpp */ int stride = qfbdev->qfb.base.pitches[0]; + spin_lock_irqsave(&qfbdev->dirty.lock, flags); + x1 = qfbdev->dirty.x1; x2 = qfbdev->dirty.x2; y1 = qfbdev->dirty.y1; y2 = qfbdev->dirty.y2; + qfbdev->dirty.x1 = 0; + qfbdev->dirty.x2 = 0; + qfbdev->dirty.y1 = 0; + qfbdev->dirty.y2 = 0; + + spin_unlock_irqrestore(&qfbdev->dirty.lock, flags); + /* * we are using a shadow draw buffer, at qdev->surface0_shadow */ qxl_io_log(qdev, "dirty x[%d, %d], y[%d, %d]", x1, x2, y1, y2); image->dx = x1; image->dy = y1; - image->width = x2 - x1; - image->height = y2 - y1; + image->width = x2 - x1 + 1; + image->height = y2 - y1 + 1; image->fg_color = 0xffffffff; /* unused, just to avoid uninitialized warnings */ image->bg_color = 0; @@ -136,10 +130,37 @@ static void qxl_fb_dirty_flush(struct fb_info *info) qxl_fb_image_init(&qxl_fb_image, qdev, info, NULL); qxl_draw_opaque_fb(&qxl_fb_image, stride); - qfbdev->dirty.x1 = 0; - qfbdev->dirty.x2 = 0; - qfbdev->dirty.y1 = 0; - qfbdev->dirty.y2 = 0; +} + +static void qxl_dirty_update(struct qxl_fbdev *qfbdev, + int x, int y, int width, int height) +{ + struct qxl_device *qdev = qfbdev->qdev; + unsigned long flags; + int x2, y2; + + x2 = x + width - 1; + y2 = y + height - 1; + + spin_lock_irqsave(&qfbdev->dirty.lock, flags); + + if (qfbdev->dirty.y1 < y) + y = qfbdev->dirty.y1; + if (qfbdev->dirty.y2 > y2) + y2 = qfbdev->dirty.y2; + if (qfbdev->dirty.x1 < x) + x = qfbdev->dirty.x1; + if (qfbdev->dirty.x2 > x2) + x2 = qfbdev->dirty.x2; + + qfbdev->dirty.x1 = x; + qfbdev->dirty.x2 = x2; + qfbdev->dirty.y1 = y; + qfbdev->dirty.y2 = y2; + + spin_unlock_irqrestore(&qfbdev->dirty.lock, flags); + + schedule_work(&qdev->fb_work); } static void qxl_deferred_io(struct fb_info *info, @@ -162,234 +183,51 @@ static void qxl_deferred_io(struct fb_info *info, if (min < max) { y1 = min / info->fix.line_length; y2 = (max / info->fix.line_length) + 1; - - /* TODO: add spin lock? */ - /* spin_lock_irqsave(&qfbdev->dirty.lock, flags); */ - qfbdev->dirty.x1 = 0; - qfbdev->dirty.y1 = y1; - qfbdev->dirty.x2 = info->var.xres; - qfbdev->dirty.y2 = y2; - /* spin_unlock_irqrestore(&qfbdev->dirty.lock, flags); */ + qxl_dirty_update(qfbdev, 0, y1, info->var.xres, y2 - y1); } - - qxl_fb_dirty_flush(info); }; - static struct fb_deferred_io qxl_defio = { .delay = QXL_DIRTY_DELAY, .deferred_io = qxl_deferred_io, }; -static void qxl_fb_delayed_fillrect(struct qxl_fbdev *qfbdev, - const struct fb_fillrect *fb_rect) -{ - struct qxl_fb_op *op; - unsigned long flags; - - op = kmalloc(sizeof(struct qxl_fb_op), GFP_ATOMIC | __GFP_NOWARN); - if (!op) - return; - - op->op.fr = *fb_rect; - op->img_data = NULL; - op->op_type = QXL_FB_OP_FILLRECT; - - spin_lock_irqsave(&qfbdev->delayed_ops_lock, flags); - list_add_tail(&op->head, &qfbdev->delayed_ops); - spin_unlock_irqrestore(&qfbdev->delayed_ops_lock, flags); -} - -static void qxl_fb_delayed_copyarea(struct qxl_fbdev *qfbdev, - const struct fb_copyarea *fb_copy) -{ - struct qxl_fb_op *op; - unsigned long flags; - - op = kmalloc(sizeof(struct qxl_fb_op), GFP_ATOMIC | __GFP_NOWARN); - if (!op) - return; - - op->op.ca = *fb_copy; - op->img_data = NULL; - op->op_type = QXL_FB_OP_COPYAREA; - - spin_lock_irqsave(&qfbdev->delayed_ops_lock, flags); - list_add_tail(&op->head, &qfbdev->delayed_ops); - spin_unlock_irqrestore(&qfbdev->delayed_ops_lock, flags); -} - -static void qxl_fb_delayed_imageblit(struct qxl_fbdev *qfbdev, - const struct fb_image *fb_image) -{ - struct qxl_fb_op *op; - unsigned long flags; - uint32_t size = fb_image->width * fb_image->height * (fb_image->depth >= 8 ? fb_image->depth / 8 : 1); - - op = kmalloc(sizeof(struct qxl_fb_op) + size, GFP_ATOMIC | __GFP_NOWARN); - if (!op) - return; - - op->op.ib = *fb_image; - op->img_data = (void *)(op + 1); - op->op_type = QXL_FB_OP_IMAGEBLIT; - - memcpy(op->img_data, fb_image->data, size); - - op->op.ib.data = op->img_data; - spin_lock_irqsave(&qfbdev->delayed_ops_lock, flags); - list_add_tail(&op->head, &qfbdev->delayed_ops); - spin_unlock_irqrestore(&qfbdev->delayed_ops_lock, flags); -} - -static void qxl_fb_fillrect_internal(struct fb_info *info, - const struct fb_fillrect *fb_rect) -{ - struct qxl_fbdev *qfbdev = info->par; - struct qxl_device *qdev = qfbdev->qdev; - struct qxl_rect rect; - uint32_t color; - int x = fb_rect->dx; - int y = fb_rect->dy; - int width = fb_rect->width; - int height = fb_rect->height; - uint16_t rop; - struct qxl_draw_fill qxl_draw_fill_rec; - - if (info->fix.visual == FB_VISUAL_TRUECOLOR || - info->fix.visual == FB_VISUAL_DIRECTCOLOR) - color = ((u32 *) (info->pseudo_palette))[fb_rect->color]; - else - color = fb_rect->color; - rect.left = x; - rect.right = x + width; - rect.top = y; - rect.bottom = y + height; - switch (fb_rect->rop) { - case ROP_XOR: - rop = SPICE_ROPD_OP_XOR; - break; - case ROP_COPY: - rop = SPICE_ROPD_OP_PUT; - break; - default: - pr_err("qxl_fb_fillrect(): unknown rop, " - "defaulting to SPICE_ROPD_OP_PUT\n"); - rop = SPICE_ROPD_OP_PUT; - } - qxl_draw_fill_rec.qdev = qdev; - qxl_draw_fill_rec.rect = rect; - qxl_draw_fill_rec.color = color; - qxl_draw_fill_rec.rop = rop; - - qxl_draw_fill(&qxl_draw_fill_rec); -} - static void qxl_fb_fillrect(struct fb_info *info, - const struct fb_fillrect *fb_rect) + const struct fb_fillrect *rect) { struct qxl_fbdev *qfbdev = info->par; - struct qxl_device *qdev = qfbdev->qdev; - if (!drm_can_sleep()) { - qxl_fb_delayed_fillrect(qfbdev, fb_rect); - schedule_work(&qdev->fb_work); - return; - } - /* make sure any previous work is done */ - flush_work(&qdev->fb_work); - qxl_fb_fillrect_internal(info, fb_rect); -} - -static void qxl_fb_copyarea_internal(struct fb_info *info, - const struct fb_copyarea *region) -{ - struct qxl_fbdev *qfbdev = info->par; - - qxl_draw_copyarea(qfbdev->qdev, - region->width, region->height, - region->sx, region->sy, - region->dx, region->dy); + sys_fillrect(info, rect); + qxl_dirty_update(qfbdev, rect->dx, rect->dy, rect->width, + rect->height); } static void qxl_fb_copyarea(struct fb_info *info, - const struct fb_copyarea *region) + const struct fb_copyarea *area) { struct qxl_fbdev *qfbdev = info->par; - struct qxl_device *qdev = qfbdev->qdev; - if (!drm_can_sleep()) { - qxl_fb_delayed_copyarea(qfbdev, region); - schedule_work(&qdev->fb_work); - return; - } - /* make sure any previous work is done */ - flush_work(&qdev->fb_work); - qxl_fb_copyarea_internal(info, region); -} - -static void qxl_fb_imageblit_safe(struct qxl_fb_image *qxl_fb_image) -{ - qxl_draw_opaque_fb(qxl_fb_image, 0); -} - -static void qxl_fb_imageblit_internal(struct fb_info *info, - const struct fb_image *image) -{ - struct qxl_fbdev *qfbdev = info->par; - struct qxl_fb_image qxl_fb_image; - - /* ensure proper order rendering operations - TODO: must do this - * for everything. */ - qxl_fb_image_init(&qxl_fb_image, qfbdev->qdev, info, image); - qxl_fb_imageblit_safe(&qxl_fb_image); + sys_copyarea(info, area); + qxl_dirty_update(qfbdev, area->dx, area->dy, area->width, + area->height); } static void qxl_fb_imageblit(struct fb_info *info, const struct fb_image *image) { struct qxl_fbdev *qfbdev = info->par; - struct qxl_device *qdev = qfbdev->qdev; - if (!drm_can_sleep()) { - qxl_fb_delayed_imageblit(qfbdev, image); - schedule_work(&qdev->fb_work); - return; - } - /* make sure any previous work is done */ - flush_work(&qdev->fb_work); - qxl_fb_imageblit_internal(info, image); + sys_imageblit(info, image); + qxl_dirty_update(qfbdev, image->dx, image->dy, image->width, + image->height); } static void qxl_fb_work(struct work_struct *work) { struct qxl_device *qdev = container_of(work, struct qxl_device, fb_work); - unsigned long flags; - struct qxl_fb_op *entry, *tmp; struct qxl_fbdev *qfbdev = qdev->mode_info.qfbdev; - /* since the irq context just adds entries to the end of the - list dropping the lock should be fine, as entry isn't modified - in the operation code */ - spin_lock_irqsave(&qfbdev->delayed_ops_lock, flags); - list_for_each_entry_safe(entry, tmp, &qfbdev->delayed_ops, head) { - spin_unlock_irqrestore(&qfbdev->delayed_ops_lock, flags); - switch (entry->op_type) { - case QXL_FB_OP_FILLRECT: - qxl_fb_fillrect_internal(qfbdev->helper.fbdev, &entry->op.fr); - break; - case QXL_FB_OP_COPYAREA: - qxl_fb_copyarea_internal(qfbdev->helper.fbdev, &entry->op.ca); - break; - case QXL_FB_OP_IMAGEBLIT: - qxl_fb_imageblit_internal(qfbdev->helper.fbdev, &entry->op.ib); - break; - } - spin_lock_irqsave(&qfbdev->delayed_ops_lock, flags); - list_del(&entry->head); - kfree(entry); - } - spin_unlock_irqrestore(&qfbdev->delayed_ops_lock, flags); + qxl_fb_dirty_flush(qfbdev->helper.fbdev); } int qxl_fb_init(struct qxl_device *qdev) @@ -678,6 +516,7 @@ int qxl_fbdev_init(struct qxl_device *qdev) qfbdev->qdev = qdev; qdev->mode_info.qfbdev = qfbdev; spin_lock_init(&qfbdev->delayed_ops_lock); + spin_lock_init(&qfbdev->dirty.lock); INIT_LIST_HEAD(&qfbdev->delayed_ops); drm_fb_helper_prepare(qdev->ddev, &qfbdev->helper, -- cgit v1.2.3 From fcf22d0567ad6cea6d2e84f28bbfa8c73642e899 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 2 Apr 2015 17:02:09 +0300 Subject: drm/edid: Fix up DMT modes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Liu Lei noticed that our 1856x1392@75Hz DMT mode doesn't match the spec. Fix that up, and also fix up a few other inconsistencies I discovered by parsing the spec (DMT version 1.0, revision 13) and comparing the results to our current DMT mode table. Also clean up the indentation mess for the 1024x768i mode. Cc: "liu,lei" Signed-off-by: Ville Syrjälä Reviewed-by: Alex Deucher Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_edid.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 53bc7a628909..567c7ed4acc0 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -160,7 +160,7 @@ static const struct drm_display_mode drm_dmt_modes[] = { DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 640x480@60Hz */ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, - 752, 800, 0, 480, 489, 492, 525, 0, + 752, 800, 0, 480, 490, 492, 525, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, @@ -206,7 +206,7 @@ static const struct drm_display_mode drm_dmt_modes[] = { { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1208, 1264, 0, 768, 768, 772, 817, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | - DRM_MODE_FLAG_INTERLACE) }, + DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@60Hz */ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1184, 1344, 0, 768, 771, 777, 806, 0, @@ -242,7 +242,7 @@ static const struct drm_display_mode drm_dmt_modes[] = { /* 1280x768@75Hz */ { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 1488, 1696, 0, 768, 771, 778, 805, 0, - DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x768@85Hz */ { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 1496, 1712, 0, 768, 771, 778, 809, 0, @@ -258,7 +258,7 @@ static const struct drm_display_mode drm_dmt_modes[] = { /* 1280x800@60Hz */ { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 1480, 1680, 0, 800, 803, 809, 831, 0, - DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x800@75Hz */ { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 1488, 1696, 0, 800, 803, 809, 838, 0, @@ -409,7 +409,7 @@ static const struct drm_display_mode drm_dmt_modes[] = { DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1856x1392@75Hz */ { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, - 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, + 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1856x1392@120Hz RB */ { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, -- cgit v1.2.3 From 24b856b1365266605be07825e4bfc265b5c6b744 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 2 Apr 2015 17:02:10 +0300 Subject: drm/edid: Add the DMT ID in the comments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To help with matching things to spec, include the DMT ID in the comments in out DMT mode table. Cc: "liu,lei" Signed-off-by: Ville Syrjälä Reviewed-by: Alex Deucher Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_edid.c | 160 ++++++++++++++++++++++----------------------- 1 file changed, 80 insertions(+), 80 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 567c7ed4acc0..b131ff1f0f94 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -146,324 +146,324 @@ static struct edid_quirk { * This table is copied from xfree86/modes/xf86EdidModes.c. */ static const struct drm_display_mode drm_dmt_modes[] = { - /* 640x350@85Hz */ + /* 0x01 - 640x350@85Hz */ { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 736, 832, 0, 350, 382, 385, 445, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 640x400@85Hz */ + /* 0x02 - 640x400@85Hz */ { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 736, 832, 0, 400, 401, 404, 445, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 720x400@85Hz */ + /* 0x03 - 720x400@85Hz */ { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 828, 936, 0, 400, 401, 404, 446, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 640x480@60Hz */ + /* 0x04 - 640x480@60Hz */ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 752, 800, 0, 480, 490, 492, 525, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 640x480@72Hz */ + /* 0x05 - 640x480@72Hz */ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 704, 832, 0, 480, 489, 492, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 640x480@75Hz */ + /* 0x06 - 640x480@75Hz */ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 720, 840, 0, 480, 481, 484, 500, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 640x480@85Hz */ + /* 0x07 - 640x480@85Hz */ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 752, 832, 0, 480, 481, 484, 509, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 800x600@56Hz */ + /* 0x08 - 800x600@56Hz */ { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 896, 1024, 0, 600, 601, 603, 625, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 800x600@60Hz */ + /* 0x09 - 800x600@60Hz */ { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 968, 1056, 0, 600, 601, 605, 628, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 800x600@72Hz */ + /* 0x0a - 800x600@72Hz */ { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 976, 1040, 0, 600, 637, 643, 666, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 800x600@75Hz */ + /* 0x0b - 800x600@75Hz */ { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 896, 1056, 0, 600, 601, 604, 625, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 800x600@85Hz */ + /* 0x0c - 800x600@85Hz */ { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 896, 1048, 0, 600, 601, 604, 631, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 800x600@120Hz RB */ + /* 0x0d - 800x600@120Hz RB */ { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 880, 960, 0, 600, 603, 607, 636, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 848x480@60Hz */ + /* 0x0e - 848x480@60Hz */ { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 976, 1088, 0, 480, 486, 494, 517, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1024x768@43Hz, interlace */ + /* 0x0f - 1024x768@43Hz, interlace */ { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1208, 1264, 0, 768, 768, 772, 817, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, - /* 1024x768@60Hz */ + /* 0x10 - 1024x768@60Hz */ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1184, 1344, 0, 768, 771, 777, 806, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1024x768@70Hz */ + /* 0x11 - 1024x768@70Hz */ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1184, 1328, 0, 768, 771, 777, 806, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1024x768@75Hz */ + /* 0x12 - 1024x768@75Hz */ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1136, 1312, 0, 768, 769, 772, 800, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1024x768@85Hz */ + /* 0x13 - 1024x768@85Hz */ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 1168, 1376, 0, 768, 769, 772, 808, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1024x768@120Hz RB */ + /* 0x14 - 1024x768@120Hz RB */ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 1104, 1184, 0, 768, 771, 775, 813, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1152x864@75Hz */ + /* 0x15 - 1152x864@75Hz */ { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1344, 1600, 0, 864, 865, 868, 900, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x768@60Hz RB */ + /* 0x16 - 1280x768@60Hz RB */ { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 1360, 1440, 0, 768, 771, 778, 790, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1280x768@60Hz */ + /* 0x17 - 1280x768@60Hz */ { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 1472, 1664, 0, 768, 771, 778, 798, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x768@75Hz */ + /* 0x18 - 1280x768@75Hz */ { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 1488, 1696, 0, 768, 771, 778, 805, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x768@85Hz */ + /* 0x19 - 1280x768@85Hz */ { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 1496, 1712, 0, 768, 771, 778, 809, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x768@120Hz RB */ + /* 0x1a - 1280x768@120Hz RB */ { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 1360, 1440, 0, 768, 771, 778, 813, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1280x800@60Hz RB */ + /* 0x1b - 1280x800@60Hz RB */ { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 1360, 1440, 0, 800, 803, 809, 823, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1280x800@60Hz */ + /* 0x1c - 1280x800@60Hz */ { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 1480, 1680, 0, 800, 803, 809, 831, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x800@75Hz */ + /* 0x1d - 1280x800@75Hz */ { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 1488, 1696, 0, 800, 803, 809, 838, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x800@85Hz */ + /* 0x1e - 1280x800@85Hz */ { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 1496, 1712, 0, 800, 803, 809, 843, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x800@120Hz RB */ + /* 0x1f - 1280x800@120Hz RB */ { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 1360, 1440, 0, 800, 803, 809, 847, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1280x960@60Hz */ + /* 0x20 - 1280x960@60Hz */ { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 1488, 1800, 0, 960, 961, 964, 1000, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x960@85Hz */ + /* 0x21 - 1280x960@85Hz */ { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 1504, 1728, 0, 960, 961, 964, 1011, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x960@120Hz RB */ + /* 0x22 - 1280x960@120Hz RB */ { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 1360, 1440, 0, 960, 963, 967, 1017, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1280x1024@60Hz */ + /* 0x23 - 1280x1024@60Hz */ { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x1024@75Hz */ + /* 0x24 - 1280x1024@75Hz */ { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x1024@85Hz */ + /* 0x25 - 1280x1024@85Hz */ { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1280x1024@120Hz RB */ + /* 0x26 - 1280x1024@120Hz RB */ { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1360x768@60Hz */ + /* 0x27 - 1360x768@60Hz */ { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 1536, 1792, 0, 768, 771, 777, 795, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1360x768@120Hz RB */ + /* 0x28 - 1360x768@120Hz RB */ { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 1440, 1520, 0, 768, 771, 776, 813, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1400x1050@60Hz RB */ + /* 0x29 - 1400x1050@60Hz RB */ { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1400x1050@60Hz */ + /* 0x2a - 1400x1050@60Hz */ { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1400x1050@75Hz */ + /* 0x2b - 1400x1050@75Hz */ { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1400x1050@85Hz */ + /* 0x2c - 1400x1050@85Hz */ { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1400x1050@120Hz RB */ + /* 0x2d - 1400x1050@120Hz RB */ { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1440x900@60Hz RB */ + /* 0x2e - 1440x900@60Hz RB */ { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 1520, 1600, 0, 900, 903, 909, 926, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1440x900@60Hz */ + /* 0x2f - 1440x900@60Hz */ { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 1672, 1904, 0, 900, 903, 909, 934, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1440x900@75Hz */ + /* 0x30 - 1440x900@75Hz */ { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 1688, 1936, 0, 900, 903, 909, 942, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1440x900@85Hz */ + /* 0x31 - 1440x900@85Hz */ { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 1696, 1952, 0, 900, 903, 909, 948, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1440x900@120Hz RB */ + /* 0x32 - 1440x900@120Hz RB */ { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 1520, 1600, 0, 900, 903, 909, 953, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1600x1200@60Hz */ + /* 0x33 - 1600x1200@60Hz */ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1600x1200@65Hz */ + /* 0x34 - 1600x1200@65Hz */ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1600x1200@70Hz */ + /* 0x35 - 1600x1200@70Hz */ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1600x1200@75Hz */ + /* 0x36 - 1600x1200@75Hz */ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1600x1200@85Hz */ + /* 0x37 - 1600x1200@85Hz */ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1600x1200@120Hz RB */ + /* 0x38 - 1600x1200@120Hz RB */ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1680x1050@60Hz RB */ + /* 0x39 - 1680x1050@60Hz RB */ { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1680x1050@60Hz */ + /* 0x3a - 1680x1050@60Hz */ { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1680x1050@75Hz */ + /* 0x3b - 1680x1050@75Hz */ { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1680x1050@85Hz */ + /* 0x3c - 1680x1050@85Hz */ { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1680x1050@120Hz RB */ + /* 0x3d - 1680x1050@120Hz RB */ { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1792x1344@60Hz */ + /* 0x3e - 1792x1344@60Hz */ { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1792x1344@75Hz */ + /* 0x3f - 1792x1344@75Hz */ { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1792x1344@120Hz RB */ + /* 0x40 - 1792x1344@120Hz RB */ { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1856x1392@60Hz */ + /* 0x41 - 1856x1392@60Hz */ { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1856x1392@75Hz */ + /* 0x42 - 1856x1392@75Hz */ { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1856x1392@120Hz RB */ + /* 0x43 - 1856x1392@120Hz RB */ { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1920x1200@60Hz RB */ + /* 0x44 - 1920x1200@60Hz RB */ { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1920x1200@60Hz */ + /* 0x45 - 1920x1200@60Hz */ { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1920x1200@75Hz */ + /* 0x46 - 1920x1200@75Hz */ { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1920x1200@85Hz */ + /* 0x47 - 1920x1200@85Hz */ { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1920x1200@120Hz RB */ + /* 0x48 - 1920x1200@120Hz RB */ { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 1920x1440@60Hz */ + /* 0x49 - 1920x1440@60Hz */ { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1920x1440@75Hz */ + /* 0x4a - 1920x1440@75Hz */ { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 1920x1440@120Hz RB */ + /* 0x4b - 1920x1440@120Hz RB */ { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 2560x1600@60Hz RB */ + /* 0x4c - 2560x1600@60Hz RB */ { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, - /* 2560x1600@60Hz */ + /* 0x4d - 2560x1600@60Hz */ { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 2560x1600@75HZ */ + /* 0x4e - 2560x1600@75Hz */ { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 2560x1600@85HZ */ + /* 0x4f - 2560x1600@85Hz */ { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, - /* 2560x1600@120Hz RB */ + /* 0x50 - 2560x1600@120Hz RB */ { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, -- cgit v1.2.3 From bfcd74d2aeda25a78f7cc92f80650218b1bce0ca Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 2 Apr 2015 17:02:11 +0300 Subject: drm/edid: Add DMT modes with ID > 0x50 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DMT Version 1.0, Rev. 13 lists a bunch of new modes we don't currently have in our dmt mode table. So add them. The order may look a bit weird since it's not sorted based on the DMT ID, but this is the order they appear in the standard. I suppose they are ordered by the resolution, pixel clock, or some such factor. I decided that it's perhaps best to keep the same order as the spec. Cc: "liu,lei" Signed-off-by: Ville Syrjälä Reviewed-by: Alex Deucher Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_edid.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index b131ff1f0f94..e7a140056d15 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -231,6 +231,10 @@ static const struct drm_display_mode drm_dmt_modes[] = { { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1344, 1600, 0, 864, 865, 868, 900, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 0x55 - 1280x720@60Hz */ + { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, + 1430, 1650, 0, 720, 725, 730, 750, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 0x16 - 1280x768@60Hz RB */ { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 1360, 1440, 0, 768, 771, 778, 790, 0, @@ -307,6 +311,14 @@ static const struct drm_display_mode drm_dmt_modes[] = { { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 1440, 1520, 0, 768, 771, 776, 813, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 0x51 - 1366x768@60Hz */ + { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, + 1579, 1792, 0, 768, 771, 774, 798, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, + /* 0x56 - 1366x768@60Hz */ + { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, + 1436, 1500, 0, 768, 769, 772, 800, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 0x29 - 1400x1050@60Hz RB */ { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, @@ -347,6 +359,10 @@ static const struct drm_display_mode drm_dmt_modes[] = { { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 1520, 1600, 0, 900, 903, 909, 953, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 0x53 - 1600x900@60Hz */ + { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, + 1704, 1800, 0, 900, 901, 904, 1000, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 0x33 - 1600x1200@60Hz */ { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, @@ -415,6 +431,10 @@ static const struct drm_display_mode drm_dmt_modes[] = { { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 0x52 - 1920x1080@60Hz */ + { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, + 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 0x44 - 1920x1200@60Hz RB */ { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, @@ -447,6 +467,10 @@ static const struct drm_display_mode drm_dmt_modes[] = { { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 0x54 - 2048x1152@60Hz */ + { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, + 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 0x4c - 2560x1600@60Hz RB */ { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, @@ -467,6 +491,14 @@ static const struct drm_display_mode drm_dmt_modes[] = { { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 0x57 - 4096x2160@60Hz RB */ + { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, + 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, + /* 0x58 - 4096x2160@59.94Hz RB */ + { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, + 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, + DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, }; /* -- cgit v1.2.3 From 9b0adc29d203116cadd81b663518104cfb19b48c Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Mon, 20 Apr 2015 19:22:50 +0100 Subject: drm/atomic: Don't open-code CRTC state destroy One failure path in crtc_helper had an open-coded CRTC state destroy which didn't actually call through to the driver's specified state destroy. Fix that. Signed-off-by: Daniel Stone Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc_helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index ab00286aec93..d727b73fba3a 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -959,7 +959,12 @@ int drm_helper_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mod if (crtc_funcs->atomic_check) { ret = crtc_funcs->atomic_check(crtc, crtc_state); if (ret) { - kfree(crtc_state); + if (crtc->funcs->atomic_destroy_state) { + crtc->funcs->atomic_destroy_state(crtc, + crtc_state); + } else { + kfree(crtc_state); + } return ret; } -- cgit v1.2.3 From 4339ed82b2fe11689353ab1955c8ee1af8b5c385 Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Mon, 20 Apr 2015 19:22:52 +0100 Subject: drm: Don't leak path blob property when updating Previously, when updating the path blob property, we would leak the existing one. Make this symmetrical with the tile and EDID blob pointers. Signed-off-by: Daniel Stone Cc: Dave Airlie Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 3007b44e6bf4..66671e040ba0 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -4304,6 +4304,9 @@ int drm_mode_connector_set_path_property(struct drm_connector *connector, size_t size = strlen(path) + 1; int ret; + if (connector->path_blob_ptr) + drm_property_destroy_blob(dev, connector->path_blob_ptr); + connector->path_blob_ptr = drm_property_create_blob(connector->dev, size, path); if (!connector->path_blob_ptr) -- cgit v1.2.3 From 6156a45602f990cdb140025a3ced96e6695980cf Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Mon, 27 Apr 2015 13:48:39 -0700 Subject: drm/i915: skylake primary plane scaling using shared scalers This patch enables skylake primary plane scaling using shared scalers atomic desgin. v2: -use single copy of scaler limits (Matt) v3: -move detach_scalers to crtc commit path (Matt) -use values in plane_state->src as regular integers (me) v4: -changes to align with updated scaler structures (Matt, me) -keep plane src rect in 16.16 format (Matt, Daniel) v5: -Rebased on top of 90/270 rotation changes (me) -Fixed an issue introduced by 90/270 changes where plane programming is using drm_plane->state rect instead of intel_plane->state rect. This change also required for scaling to work properly. (me) -With 90/270, updated limits to cover both portrait and landscape usages (me) -Refactored skylake_update_primary_plane to reduce its size (Daniel) Added helper functions for refactoring are comprehended enough to be used for skylake_update_plane (for sprite) too. One stop towards having single function for all planes. v6: -Added fixme note when checking plane_state->src width in update_plane (Daniel) -Release lock when failing to colorkey request with active scaler (Daniel) Signed-off-by: Chandra Konduru Reviewed-by: matthew.d.roper@intel.com Reviewed-by: sonika.jindal@intel.com (v5) Testcase: igt/kms_plane_scaling Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_atomic.c | 5 +- drivers/gpu/drm/i915/intel_display.c | 266 ++++++++++++++++++++++++++--------- drivers/gpu/drm/i915/intel_drv.h | 8 +- drivers/gpu/drm/i915/intel_sprite.c | 10 ++ 4 files changed, 219 insertions(+), 70 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index 3c4b7cdeab77..cb6d5f2d9b60 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -169,7 +169,7 @@ int intel_atomic_commit(struct drm_device *dev, plane->state->state = NULL; } - /* swap crtc_state */ + /* swap crtc_scaler_state */ for (i = 0; i < dev->mode_config.num_crtc; i++) { struct drm_crtc *crtc = state->crtcs[i]; if (!crtc) { @@ -178,6 +178,9 @@ int intel_atomic_commit(struct drm_device *dev, to_intel_crtc(crtc)->config->scaler_state = to_intel_crtc_state(state->crtc_states[i])->scaler_state; + + if (INTEL_INFO(dev)->gen >= 9) + skl_detach_scalers(to_intel_crtc(crtc)); } drm_atomic_helper_commit_planes(dev, state); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3094b0807b40..14709547659f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2985,126 +2985,204 @@ void skl_detach_scalers(struct intel_crtc *intel_crtc) } } -static void skylake_update_primary_plane(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y) +u32 skl_plane_ctl_format(uint32_t pixel_format) { - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_i915_gem_object *obj; - int pipe = intel_crtc->pipe; - u32 plane_ctl, stride_div, stride; - u32 tile_height, plane_offset, plane_size; - unsigned int rotation; - int x_offset, y_offset; - unsigned long surf_addr; - struct drm_plane *plane; - - if (!intel_crtc->primary_enabled) { - I915_WRITE(PLANE_CTL(pipe, 0), 0); - I915_WRITE(PLANE_SURF(pipe, 0), 0); - POSTING_READ(PLANE_CTL(pipe, 0)); - return; - } - - plane_ctl = PLANE_CTL_ENABLE | - PLANE_CTL_PIPE_GAMMA_ENABLE | - PLANE_CTL_PIPE_CSC_ENABLE; - - switch (fb->pixel_format) { + u32 plane_ctl_format = 0; + switch (pixel_format) { case DRM_FORMAT_RGB565: - plane_ctl |= PLANE_CTL_FORMAT_RGB_565; - break; - case DRM_FORMAT_XRGB8888: - plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; - break; - case DRM_FORMAT_ARGB8888: - plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; - plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; + plane_ctl_format = PLANE_CTL_FORMAT_RGB_565; break; case DRM_FORMAT_XBGR8888: - plane_ctl |= PLANE_CTL_ORDER_RGBX; - plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; + plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; break; + case DRM_FORMAT_XRGB8888: + plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888; + break; + /* + * XXX: For ARBG/ABGR formats we default to expecting scanout buffers + * to be already pre-multiplied. We need to add a knob (or a different + * DRM_FORMAT) for user-space to configure that. + */ case DRM_FORMAT_ABGR8888: - plane_ctl |= PLANE_CTL_ORDER_RGBX; - plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; - plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; + plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | + PLANE_CTL_ALPHA_SW_PREMULTIPLY; + break; + case DRM_FORMAT_ARGB8888: + plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | + PLANE_CTL_ALPHA_SW_PREMULTIPLY; break; case DRM_FORMAT_XRGB2101010: - plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; + plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010; break; case DRM_FORMAT_XBGR2101010: - plane_ctl |= PLANE_CTL_ORDER_RGBX; - plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; + plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; + break; + case DRM_FORMAT_YUYV: + plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; + break; + case DRM_FORMAT_YVYU: + plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; + break; + case DRM_FORMAT_UYVY: + plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; + break; + case DRM_FORMAT_VYUY: + plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; break; default: BUG(); } + return plane_ctl_format; +} - switch (fb->modifier[0]) { +u32 skl_plane_ctl_tiling(uint64_t fb_modifier) +{ + u32 plane_ctl_tiling = 0; + switch (fb_modifier) { case DRM_FORMAT_MOD_NONE: break; case I915_FORMAT_MOD_X_TILED: - plane_ctl |= PLANE_CTL_TILED_X; + plane_ctl_tiling = PLANE_CTL_TILED_X; break; case I915_FORMAT_MOD_Y_TILED: - plane_ctl |= PLANE_CTL_TILED_Y; + plane_ctl_tiling = PLANE_CTL_TILED_Y; break; case I915_FORMAT_MOD_Yf_TILED: - plane_ctl |= PLANE_CTL_TILED_YF; + plane_ctl_tiling = PLANE_CTL_TILED_YF; break; default: - MISSING_CASE(fb->modifier[0]); + MISSING_CASE(fb_modifier); } + return plane_ctl_tiling; +} - plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; - - plane = crtc->primary; - rotation = plane->state->rotation; +u32 skl_plane_ctl_rotation(unsigned int rotation) +{ + u32 plane_ctl_rotation = 0; switch (rotation) { + case BIT(DRM_ROTATE_0): + break; case BIT(DRM_ROTATE_90): - plane_ctl |= PLANE_CTL_ROTATE_90; + plane_ctl_rotation = PLANE_CTL_ROTATE_90; break; - case BIT(DRM_ROTATE_180): - plane_ctl |= PLANE_CTL_ROTATE_180; + plane_ctl_rotation = PLANE_CTL_ROTATE_180; break; - case BIT(DRM_ROTATE_270): - plane_ctl |= PLANE_CTL_ROTATE_270; + plane_ctl_rotation = PLANE_CTL_ROTATE_270; break; + default: + MISSING_CASE(rotation); + } + + return plane_ctl_rotation; +} + +static void skylake_update_primary_plane(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int x, int y) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct drm_i915_gem_object *obj; + int pipe = intel_crtc->pipe; + u32 plane_ctl, stride_div, stride; + u32 tile_height, plane_offset, plane_size; + unsigned int rotation; + int x_offset, y_offset; + unsigned long surf_addr; + struct drm_plane *plane; + struct intel_crtc_state *crtc_state = intel_crtc->config; + struct intel_plane_state *plane_state; + int src_x = 0, src_y = 0, src_w = 0, src_h = 0; + int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; + int scaler_id = -1; + + plane = crtc->primary; + plane_state = to_intel_plane_state(plane->state); + + if (!intel_crtc->primary_enabled) { + I915_WRITE(PLANE_CTL(pipe, 0), 0); + I915_WRITE(PLANE_SURF(pipe, 0), 0); + POSTING_READ(PLANE_CTL(pipe, 0)); + return; } + plane_ctl = PLANE_CTL_ENABLE | + PLANE_CTL_PIPE_GAMMA_ENABLE | + PLANE_CTL_PIPE_CSC_ENABLE; + + plane_ctl |= skl_plane_ctl_format(fb->pixel_format); + plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); + plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; + + rotation = plane->state->rotation; + plane_ctl |= skl_plane_ctl_rotation(rotation); + obj = intel_fb_obj(fb); stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], fb->pixel_format); surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); + /* + * FIXME: intel_plane_state->src, dst aren't set when transitional + * update_plane helpers are called from legacy paths. + * Once full atomic crtc is available, below check can be avoided. + */ + if (drm_rect_width(&plane_state->src)) { + scaler_id = plane_state->scaler_id; + src_x = plane_state->src.x1 >> 16; + src_y = plane_state->src.y1 >> 16; + src_w = drm_rect_width(&plane_state->src) >> 16; + src_h = drm_rect_height(&plane_state->src) >> 16; + dst_x = plane_state->dst.x1; + dst_y = plane_state->dst.y1; + dst_w = drm_rect_width(&plane_state->dst); + dst_h = drm_rect_height(&plane_state->dst); + + WARN_ON(x != src_x || y != src_y); + } else { + src_w = intel_crtc->config->pipe_src_w; + src_h = intel_crtc->config->pipe_src_h; + } + if (intel_rotation_90_or_270(rotation)) { /* stride = Surface height in tiles */ tile_height = intel_tile_height(dev, fb->bits_per_pixel, fb->modifier[0]); stride = DIV_ROUND_UP(fb->height, tile_height); - x_offset = stride * tile_height - y - (plane->state->src_h >> 16); + x_offset = stride * tile_height - y - src_h; y_offset = x; - plane_size = ((plane->state->src_w >> 16) - 1) << 16 | - ((plane->state->src_h >> 16) - 1); + plane_size = (src_w - 1) << 16 | (src_h - 1); } else { stride = fb->pitches[0] / stride_div; x_offset = x; y_offset = y; - plane_size = ((plane->state->src_h >> 16) - 1) << 16 | - ((plane->state->src_w >> 16) - 1); + plane_size = (src_h - 1) << 16 | (src_w - 1); } plane_offset = y_offset << 16 | x_offset; I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); - I915_WRITE(PLANE_POS(pipe, 0), 0); I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); I915_WRITE(PLANE_STRIDE(pipe, 0), stride); + + if (scaler_id >= 0) { + uint32_t ps_ctrl = 0; + + WARN_ON(!dst_w || !dst_h); + ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | + crtc_state->scaler_state.scalers[scaler_id].mode; + I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); + I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); + I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); + I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); + I915_WRITE(PLANE_POS(pipe, 0), 0); + } else { + I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); + } + I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); POSTING_READ(PLANE_SURF(pipe, 0)); @@ -4383,6 +4461,7 @@ skl_update_scaler_users( int *scaler_id; struct drm_framebuffer *fb; struct intel_crtc_scaler_state *scaler_state; + unsigned int rotation; if (!intel_crtc || !crtc_state) return 0; @@ -4398,6 +4477,7 @@ skl_update_scaler_users( dst_w = drm_rect_width(&plane_state->dst); dst_h = drm_rect_height(&plane_state->dst); scaler_id = &plane_state->scaler_id; + rotation = plane_state->base.rotation; } else { struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; @@ -4406,8 +4486,12 @@ skl_update_scaler_users( dst_w = adjusted_mode->hdisplay; dst_h = adjusted_mode->vdisplay; scaler_id = &scaler_state->scaler_id; + rotation = DRM_ROTATE_0; } - need_scaling = (src_w != dst_w || src_h != dst_h); + + need_scaling = intel_rotation_90_or_270(rotation) ? + (src_h != dst_w || src_w != dst_h): + (src_w != dst_w || src_h != dst_h); /* * if plane is being disabled or scaler is no more required or force detach @@ -13133,6 +13217,36 @@ intel_cleanup_plane_fb(struct drm_plane *plane, } } +int +skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) +{ + int max_scale; + struct drm_device *dev; + struct drm_i915_private *dev_priv; + int crtc_clock, cdclk; + + if (!intel_crtc || !crtc_state) + return DRM_PLANE_HELPER_NO_SCALING; + + dev = intel_crtc->base.dev; + dev_priv = dev->dev_private; + crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; + cdclk = dev_priv->display.get_display_clock_speed(dev); + + if (!crtc_clock || !cdclk) + return DRM_PLANE_HELPER_NO_SCALING; + + /* + * skl max scale is lower of: + * close to 3 but not 3, -1 is for that purpose + * or + * cdclk/crtc_clock + */ + max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); + + return max_scale; +} + static int intel_check_primary_plane(struct drm_plane *plane, struct intel_plane_state *state) @@ -13141,23 +13255,31 @@ intel_check_primary_plane(struct drm_plane *plane, struct drm_i915_private *dev_priv = dev->dev_private; struct drm_crtc *crtc = state->base.crtc; struct intel_crtc *intel_crtc; + struct intel_crtc_state *crtc_state; struct drm_framebuffer *fb = state->base.fb; struct drm_rect *dest = &state->dst; struct drm_rect *src = &state->src; const struct drm_rect *clip = &state->clip; bool can_position = false; + int max_scale = DRM_PLANE_HELPER_NO_SCALING; + int min_scale = DRM_PLANE_HELPER_NO_SCALING; int ret; crtc = crtc ? crtc : plane->crtc; intel_crtc = to_intel_crtc(crtc); + crtc_state = state->base.state ? + intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev)->gen >= 9) { + min_scale = 1; + max_scale = skl_max_scale(intel_crtc, crtc_state); can_position = true; + } ret = drm_plane_helper_check_update(plane, crtc, fb, src, dest, clip, - DRM_PLANE_HELPER_NO_SCALING, - DRM_PLANE_HELPER_NO_SCALING, + min_scale, + max_scale, can_position, true, &state->visible); if (ret) @@ -13202,6 +13324,13 @@ intel_check_primary_plane(struct drm_plane *plane, intel_crtc->atomic.update_wm = true; } + if (INTEL_INFO(dev)->gen >= 9) { + ret = skl_update_scaler_users(intel_crtc, crtc_state, + to_intel_plane(plane), state, 0); + if (ret) + return ret; + } + return 0; } @@ -13381,6 +13510,9 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, primary->can_scale = false; primary->max_downscale = 1; + if (INTEL_INFO(dev)->gen >= 9) { + primary->can_scale = true; + } state->scaler_id = -1; primary->pipe = pipe; primary->plane = pipe; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 43fe003ba3da..fb8797f1eb8e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -285,11 +285,11 @@ struct intel_initial_plane_config { #define SKL_MIN_SRC_W 8 #define SKL_MAX_SRC_W 4096 #define SKL_MIN_SRC_H 8 -#define SKL_MAX_SRC_H 2304 +#define SKL_MAX_SRC_H 4096 #define SKL_MIN_DST_W 8 #define SKL_MAX_DST_W 4096 #define SKL_MIN_DST_H 8 -#define SKL_MAX_DST_H 2304 +#define SKL_MAX_DST_H 4096 struct intel_scaler { int id; @@ -1145,9 +1145,13 @@ void skl_detach_scalers(struct intel_crtc *intel_crtc); int skl_update_scaler_users(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane, struct intel_plane_state *plane_state, int force_detach); +int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, struct drm_i915_gem_object *obj); +u32 skl_plane_ctl_format(uint32_t pixel_format); +u32 skl_plane_ctl_tiling(uint64_t fb_modifier); +u32 skl_plane_ctl_rotation(unsigned int rotation); /* intel_dp.c */ void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index e3d41c096dc6..b3c5911a6239 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1150,6 +1150,16 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data, } intel_plane = to_intel_plane(plane); + + if (INTEL_INFO(dev)->gen >= 9) { + /* plane scaling and colorkey are mutually exclusive */ + if (to_intel_plane_state(plane->state)->scaler_id >= 0) { + DRM_ERROR("colorkey not allowed with scaler\n"); + ret = -EINVAL; + goto out_unlock; + } + } + intel_plane->ckey = *set; /* -- cgit v1.2.3 From c331879ce8ea4508260c5e9da5ea4b1a7d20e381 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Wed, 15 Apr 2015 15:15:02 -0700 Subject: drm/i915: skylake sprite plane scaling using shared scalers This patch enables skylake sprite plane display scaling using shared scalers atomic desgin. v2: -use single copy of scaler limits (Matt) v3: -detaching scalers moved to crtc commit path (Matt) v4: -changes to align with updated scaler structures (Matt, me) -keep sprite src rect in 16.16 format (Matt, Daniel) v5: -rebased on top of 90/270 rotation changes (me) -Refactored skl_update_plane to reduce its size (Daniel) It is a step towards having a single function covering all planes. Signed-off-by: Chandra Konduru Reviewed-by: Matt Roper Testcase: igt/kms_plane_scaling Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_sprite.c | 125 ++++++++++++++---------------------- 1 file changed, 48 insertions(+), 77 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index b3c5911a6239..856395bbcc4e 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include "intel_drv.h" #include @@ -197,80 +198,17 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, u32 tile_height, plane_offset, plane_size; unsigned int rotation; int x_offset, y_offset; + struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config; + int scaler_id; plane_ctl = PLANE_CTL_ENABLE | PLANE_CTL_PIPE_CSC_ENABLE; - switch (fb->pixel_format) { - case DRM_FORMAT_RGB565: - plane_ctl |= PLANE_CTL_FORMAT_RGB_565; - break; - case DRM_FORMAT_XBGR8888: - plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; - break; - case DRM_FORMAT_XRGB8888: - plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; - break; - /* - * XXX: For ARBG/ABGR formats we default to expecting scanout buffers - * to be already pre-multiplied. We need to add a knob (or a different - * DRM_FORMAT) for user-space to configure that. - */ - case DRM_FORMAT_ABGR8888: - plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | - PLANE_CTL_ORDER_RGBX | - PLANE_CTL_ALPHA_SW_PREMULTIPLY; - break; - case DRM_FORMAT_ARGB8888: - plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | - PLANE_CTL_ALPHA_SW_PREMULTIPLY; - break; - case DRM_FORMAT_YUYV: - plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; - break; - case DRM_FORMAT_YVYU: - plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; - break; - case DRM_FORMAT_UYVY: - plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; - break; - case DRM_FORMAT_VYUY: - plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; - break; - default: - BUG(); - } - - switch (fb->modifier[0]) { - case DRM_FORMAT_MOD_NONE: - break; - case I915_FORMAT_MOD_X_TILED: - plane_ctl |= PLANE_CTL_TILED_X; - break; - case I915_FORMAT_MOD_Y_TILED: - plane_ctl |= PLANE_CTL_TILED_Y; - break; - case I915_FORMAT_MOD_Yf_TILED: - plane_ctl |= PLANE_CTL_TILED_YF; - break; - default: - MISSING_CASE(fb->modifier[0]); - } + plane_ctl |= skl_plane_ctl_format(fb->pixel_format); + plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); rotation = drm_plane->state->rotation; - switch (rotation) { - case BIT(DRM_ROTATE_90): - plane_ctl |= PLANE_CTL_ROTATE_90; - break; - - case BIT(DRM_ROTATE_180): - plane_ctl |= PLANE_CTL_ROTATE_180; - break; - - case BIT(DRM_ROTATE_270): - plane_ctl |= PLANE_CTL_ROTATE_270; - break; - } + plane_ctl |= skl_plane_ctl_rotation(rotation); intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h, pixel_size, true, @@ -279,6 +217,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], fb->pixel_format); + scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id; + /* Sizes are 0 based */ src_w--; src_h--; @@ -316,8 +256,27 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); I915_WRITE(PLANE_STRIDE(pipe, plane), stride); - I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); + + /* program plane scaler */ + if (scaler_id >= 0) { + uint32_t ps_ctrl = 0; + + DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, + PS_PLANE_SEL(plane)); + ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | + crtc_state->scaler_state.scalers[scaler_id].mode; + I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); + I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); + I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); + I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), + ((crtc_w + 1) << 16)|(crtc_h + 1)); + + I915_WRITE(PLANE_POS(pipe, plane), 0); + } else { + I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); + } + I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); POSTING_READ(PLANE_SURF(pipe, plane)); @@ -894,7 +853,9 @@ static int intel_check_sprite_plane(struct drm_plane *plane, struct intel_plane_state *state) { + struct drm_device *dev = plane->dev; struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); + struct intel_crtc_state *crtc_state; struct intel_plane *intel_plane = to_intel_plane(plane); struct drm_framebuffer *fb = state->base.fb; int crtc_x, crtc_y; @@ -906,8 +867,11 @@ intel_check_sprite_plane(struct drm_plane *plane, int hscale, vscale; int max_scale, min_scale; int pixel_size; + int ret; intel_crtc = intel_crtc ? intel_crtc : to_intel_crtc(plane->crtc); + crtc_state = state->base.state ? + intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; if (!fb) { state->visible = false; @@ -934,6 +898,11 @@ intel_check_sprite_plane(struct drm_plane *plane, max_scale = intel_plane->max_downscale << 16; min_scale = intel_plane->can_scale ? 1 : (1 << 16); + if (INTEL_INFO(dev)->gen >= 9) { + min_scale = 1; + max_scale = skl_max_scale(intel_crtc, crtc_state); + } + drm_rect_rotate(src, fb->width << 16, fb->height << 16, state->base.rotation); @@ -1029,8 +998,8 @@ intel_check_sprite_plane(struct drm_plane *plane, width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size; - if (src_w > 2048 || src_h > 2048 || - width_bytes > 4096 || fb->pitches[0] > 4096) { + if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || + width_bytes > 4096 || fb->pitches[0] > 4096)) { DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); return -EINVAL; } @@ -1084,6 +1053,13 @@ finish: } } + if (INTEL_INFO(dev)->gen >= 9) { + ret = skl_update_scaler_users(intel_crtc, crtc_state, intel_plane, + state, 0); + if (ret) + return ret; + } + return 0; } @@ -1296,12 +1272,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) } break; case 9: - /* - * FIXME: Skylake planes can be scaled (with some restrictions), - * but this is for another time. - */ - intel_plane->can_scale = false; - intel_plane->max_downscale = 1; + intel_plane->can_scale = true; intel_plane->update_plane = skl_update_plane; intel_plane->disable_plane = skl_disable_plane; state->scaler_id = -1; -- cgit v1.2.3 From dfb601e6d2c72a7d2d9eddec1d1f65f2ccf66bda Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Fri, 10 Apr 2015 13:12:24 +0100 Subject: drm/i915/bxt: Add WaDisableThreadStallDopClockGating Signed-off-by: Nick Hoath Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index de8c0747aaef..98424e29917c 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1041,8 +1041,15 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) static int bxt_init_workarounds(struct intel_engine_cs *ring) { + struct drm_device *dev = ring->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + gen9_init_workarounds(ring); + /* WaDisableThreadStallDopClockGating:bxt */ + WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, + STALL_DOP_GATING_DISABLE); + return 0; } -- cgit v1.2.3 From c6b8a4bc1ece2469ceef55f3c9423afdcb3b95c8 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Mon, 4 May 2015 14:58:33 +0200 Subject: drm/i915: Simplify cmd-parser DISPATCH_SECURE check i915_needs_cmd_parser already checks that for us. Suggested-by: Mika Kuoppala Cc: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index d2e21c549756..7ab63d9d7dc5 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1559,8 +1559,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, * don't want that set when the command parser is * enabled. */ - if (USES_PPGTT(dev)) - dispatch_flags |= I915_DISPATCH_SECURE; + dispatch_flags |= I915_DISPATCH_SECURE; exec_start = 0; } -- cgit v1.2.3 From eb805623d8b161342ed9c9caf366f0a295041a6d Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Mon, 4 May 2015 14:58:44 +0200 Subject: drm/i915/skl: Add support to load SKL CSR firmware. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Display Context Save and Restore support is needed for various SKL Display C states like DC5, DC6. This implementation is added based on first version of DMC CSR program that we received from h/w team. Here we are using request_firmware based design. Finally this firmware should end up in linux-firmware tree. For SKL platform its mandatory to ensure that we load this csr program before enabling DC states like DC5/DC6. As CSR program gets reset on various conditions, we should ensure to load it during boot and in future change to be added to load this system resume sequence too. v1: Initial relese as RFC patch v2: Design change as per Daniel, Damien and Shobit's review comments request firmware method followed. v3: Some optimization and functional changes. Pulled register defines into drivers/gpu/drm/i915/i915_reg.h Used kmemdup to allocate and duplicate firmware content. Ensured to free allocated buffer. v4: Modified as per review comments from Satheesh and Daniel Removed temporary buffer. Optimized number of writes by replacing I915_WRITE with I915_WRITE64. v5: Modified as per review comemnts from Damien. - Changed name for functions and firmware. - Introduced HAS_CSR. - Reverted back previous change and used csr_buf with u8 size. - Using cpu_to_be64 for endianness change. Modified as per review comments from Imre. - Modified registers and macro names to be a bit closer to bspec terminology and the existing register naming in the driver. - Early return for non SKL platforms in intel_load_csr_program function. - Added locking around CSR program load function as it may be called concurrently during system/runtime resume. - Releasing the fw before loading the program for consistency - Handled error path during f/w load. v6: Modified as per review comments from Imre. - Corrected out_freecsr sequence. v7: Modified as per review comments from Imre. Fail loading fw if fw->size%8!=0. v8: Rebase to latest. v9: Rebase on top of -nightly (Damien) v10: Enabled support for dmc firmware ver 1.0. According to ver 1.0 in a single binary package all the firmware's that are required for different stepping's of the product will be stored. The package contains the css header, followed by the package header and the actual dmc firmwares. Package header contains the firmware/stepping mapping table and the corresponding firmware offsets to the individual binaries, within the package. Each individual program binary contains the header and the payload sections whose size is specified in the header section. This changes are done to extract the specific firmaware from the package. (Animesh) v11: Modified as per review comemnts from Imre. - Added code comment from bpec for header structure elements. - Added __packed to avoid structure padding. - Added helper functions for stepping and substepping info. - Added code comment for CSR_MAX_FW_SIZE. - Disabled BXT firmware loading, will be enabled with dmc 1.0 support. - Changed skl_stepping_info based on bspec, earlier used from config DB. - Removed duplicate call of cpu_to_be* from intel_csr_load_program function. - Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned. - Added sanity check for header length. - Added sanity check for mmio address got from firmware binary. - kmalloc done separately for dmc header and dmc firmware. (Animesh) v12: Modified as per review comemnts from Imre. - Corrected the typo error in skl stepping info structure. - Added out-of-bound access for skl_stepping_info. - Sanity check for mmio address modified. - Sanity check added for stepping and substeppig. - Modified the intel_dmc_info structure, cache only the required header info. (Animesh) v13: clarify firmware load error message. The reason for a firmware loading failure can be obscure if the driver is built-in. Provide an explanation to the user about the likely reason for the failure and how to resolve it. (Imre) v14: Suggested by Jani. - fix s/I915/CONFIG_DRM_I915/ typo - add fw_path to the firmware object instead of using a static ptr (Jani) v15: 1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link with same name will help not to build kernel again. 2) Changes done as per review comments from Imre. - Error check removed for intel_csr_ucode_init. - Moved csr-specific data structure to intel_csr.h and optimization done on structure definition. - fw->data used directly for parsing the header info & memory allocation only done separately for payload. (Animesh) v16: - No need for out_regs label in i915_driver_load(), so removed it. - Changed the firmware name as skl_dmc_ver1.bin, followed naming convention _dmc_.bin (Animesh) Issue: VIZ-2569 Signed-off-by: A.Sunil Kamath Signed-off-by: Damien Lespiau Signed-off-by: Animesh Manna Signed-off-by: Imre Deak Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_dma.c | 11 +- drivers/gpu/drm/i915/i915_drv.c | 20 +++ drivers/gpu/drm/i915/i915_drv.h | 17 ++ drivers/gpu/drm/i915/intel_csr.c | 367 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 5 + 6 files changed, 420 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_csr.c (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index a69002e2257d..5238deb64505 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -12,7 +12,8 @@ i915-y := i915_drv.o \ i915_suspend.o \ i915_sysfs.o \ intel_pm.o \ - intel_runtime_pm.o + intel_runtime_pm.o \ + intel_csr.o i915-$(CONFIG_COMPAT) += i915_ioc32.o i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index e44116f0ad0a..a238889630d8 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -816,6 +816,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) spin_lock_init(&dev_priv->mmio_flip_lock); mutex_init(&dev_priv->dpio_lock); mutex_init(&dev_priv->modeset_restore_lock); + mutex_init(&dev_priv->csr_lock); intel_pm_setup(dev); @@ -861,9 +862,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) intel_uncore_init(dev); + /* Load CSR Firmware for SKL */ + intel_csr_ucode_init(dev); + ret = i915_gem_gtt_init(dev); if (ret) - goto out_regs; + goto out_freecsr; /* WARNING: Apparently we must kick fbdev drivers before vgacon, * otherwise the vga fbdev driver falls over. */ @@ -1033,7 +1037,8 @@ out_mtrrfree: io_mapping_free(dev_priv->gtt.mappable); out_gtt: i915_global_gtt_cleanup(dev); -out_regs: +out_freecsr: + intel_csr_ucode_fini(dev); intel_uncore_fini(dev); pci_iounmap(dev->pdev, dev_priv->regs); put_bridge: @@ -1113,6 +1118,8 @@ int i915_driver_unload(struct drm_device *dev) mutex_unlock(&dev->struct_mutex); i915_gem_cleanup_stolen(dev); + intel_csr_ucode_fini(dev); + intel_teardown_gmbus(dev); intel_teardown_mchbar(dev); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6e9ab2fb1647..b743bb17e288 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -556,6 +556,26 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv) cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work); } +void i915_firmware_load_error_print(const char *fw_path, int err) +{ + DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err); + + /* + * If the reason is not known assume -ENOENT since that's the most + * usual failure mode. + */ + if (!err) + err = -ENOENT; + + if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT)) + return; + + DRM_ERROR( + "The driver is built-in, so to load the firmware you need to\n" + "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n" + "in your initrd/initramfs image.\n"); +} + static void intel_suspend_encoders(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e8e8145df869..df46e2735991 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -669,6 +669,15 @@ struct intel_uncore { #define for_each_fw_domain(domain__, dev_priv__, i__) \ for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) +struct intel_csr { + const char *fw_path; + __be32 *dmc_payload; + uint32_t dmc_fw_size; + uint32_t mmio_count; + uint32_t mmioaddr[8]; + uint32_t mmiodata[8]; +}; + #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ func(is_mobile) sep \ func(is_i85x) sep \ @@ -1574,6 +1583,11 @@ struct drm_i915_private { struct i915_virtual_gpu vgpu; + struct intel_csr csr; + + /* Display CSR-related protection */ + struct mutex csr_lock; + struct intel_gmbus gmbus[GMBUS_NUM_PINS]; /** gmbus_mutex protects against concurrent usage of the single hw gmbus @@ -2426,6 +2440,8 @@ struct drm_i915_cmd_table { #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) +#define HAS_CSR(dev) (IS_SKYLAKE(dev)) + #define INTEL_PCH_DEVICE_ID_MASK 0xff00 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 @@ -2516,6 +2532,7 @@ extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); +void i915_firmware_load_error_print(const char *fw_path, int err); /* i915_irq.c */ void i915_queue_hangcheck(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c new file mode 100644 index 000000000000..b3d6fbefa5c6 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -0,0 +1,367 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ +#include +#include "i915_drv.h" +#include "i915_reg.h" + +#define I915_CSR_SKL "i915/skl_dmc_ver4.bin" + +MODULE_FIRMWARE(I915_CSR_SKL); + +/* +* SKL CSR registers for DC5 and DC6 +*/ +#define CSR_PROGRAM_BASE 0x80000 +#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 +#define CSR_HTP_ADDR_SKL 0x00500034 +#define CSR_SSP_BASE 0x8F074 +#define CSR_HTP_SKL 0x8F004 +#define CSR_LAST_WRITE 0x8F034 +#define CSR_LAST_WRITE_VALUE 0xc003b400 +/* MMIO address range for CSR program (0x80000 - 0x82FFF) */ +#define CSR_MAX_FW_SIZE 0x2FFF +#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF +#define CSR_MMIO_START_RANGE 0x80000 +#define CSR_MMIO_END_RANGE 0x8FFFF + +struct intel_css_header { + /* 0x09 for DMC */ + uint32_t module_type; + + /* Includes the DMC specific header in dwords */ + uint32_t header_len; + + /* always value would be 0x10000 */ + uint32_t header_ver; + + /* Not used */ + uint32_t module_id; + + /* Not used */ + uint32_t module_vendor; + + /* in YYYYMMDD format */ + uint32_t date; + + /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ + uint32_t size; + + /* Not used */ + uint32_t key_size; + + /* Not used */ + uint32_t modulus_size; + + /* Not used */ + uint32_t exponent_size; + + /* Not used */ + uint32_t reserved1[12]; + + /* Major Minor */ + uint32_t version; + + /* Not used */ + uint32_t reserved2[8]; + + /* Not used */ + uint32_t kernel_header_info; +} __packed; + +struct intel_fw_info { + uint16_t reserved1; + + /* Stepping (A, B, C, ..., *). * is a wildcard */ + char stepping; + + /* Sub-stepping (0, 1, ..., *). * is a wildcard */ + char substepping; + + uint32_t offset; + uint32_t reserved2; +} __packed; + +struct intel_package_header { + /* DMC container header length in dwords */ + unsigned char header_len; + + /* always value would be 0x01 */ + unsigned char header_ver; + + unsigned char reserved[10]; + + /* Number of valid entries in the FWInfo array below */ + uint32_t num_entries; + + struct intel_fw_info fw_info[20]; +} __packed; + +struct intel_dmc_header { + /* always value would be 0x40403E3E */ + uint32_t signature; + + /* DMC binary header length */ + unsigned char header_len; + + /* 0x01 */ + unsigned char header_ver; + + /* Reserved */ + uint16_t dmcc_ver; + + /* Major, Minor */ + uint32_t project; + + /* Firmware program size (excluding header) in dwords */ + uint32_t fw_size; + + /* Major Minor version */ + uint32_t fw_version; + + /* Number of valid MMIO cycles present. */ + uint32_t mmio_count; + + /* MMIO address */ + uint32_t mmioaddr[8]; + + /* MMIO data */ + uint32_t mmiodata[8]; + + /* FW filename */ + unsigned char dfile[32]; + + uint32_t reserved1[2]; +} __packed; + +struct stepping_info { + char stepping; + char substepping; +}; + +static const struct stepping_info skl_stepping_info[] = { + {'A', '0'}, {'B', '0'}, {'C', '0'}, + {'D', '0'}, {'E', '0'}, {'F', '0'}, + {'G', '0'}, {'H', '0'}, {'I', '0'} +}; + +static char intel_get_stepping(struct drm_device *dev) +{ + if (IS_SKYLAKE(dev) && (dev->pdev->revision < + ARRAY_SIZE(skl_stepping_info))) + return skl_stepping_info[dev->pdev->revision].stepping; + else + return -ENODATA; +} + +static char intel_get_substepping(struct drm_device *dev) +{ + if (IS_SKYLAKE(dev) && (dev->pdev->revision < + ARRAY_SIZE(skl_stepping_info))) + return skl_stepping_info[dev->pdev->revision].substepping; + else + return -ENODATA; +} + +void intel_csr_load_program(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + __be32 *payload = dev_priv->csr.dmc_payload; + uint32_t i, fw_size; + + if (!IS_GEN9(dev)) { + DRM_ERROR("No CSR support available for this platform\n"); + return; + } + + mutex_lock(&dev_priv->csr_lock); + fw_size = dev_priv->csr.dmc_fw_size; + for (i = 0; i < fw_size; i++) + I915_WRITE(CSR_PROGRAM_BASE + i * 4, + (u32 __force)payload[i]); + + for (i = 0; i < dev_priv->csr.mmio_count; i++) { + I915_WRITE(dev_priv->csr.mmioaddr[i], + dev_priv->csr.mmiodata[i]); + } + mutex_unlock(&dev_priv->csr_lock); +} + +static void finish_csr_load(const struct firmware *fw, void *context) +{ + struct drm_i915_private *dev_priv = context; + struct drm_device *dev = dev_priv->dev; + struct intel_css_header *css_header; + struct intel_package_header *package_header; + struct intel_dmc_header *dmc_header; + struct intel_csr *csr = &dev_priv->csr; + char stepping = intel_get_stepping(dev); + char substepping = intel_get_substepping(dev); + uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; + uint32_t i; + __be32 *dmc_payload; + + if (!fw) { + i915_firmware_load_error_print(csr->fw_path, 0); + goto out; + } + + if ((stepping == -ENODATA) || (substepping == -ENODATA)) { + DRM_ERROR("Unknown stepping info, firmware loading failed\n"); + goto out; + } + + /* Extract CSS Header information*/ + css_header = (struct intel_css_header *)fw->data; + if (sizeof(struct intel_css_header) != + (css_header->header_len * 4)) { + DRM_ERROR("Firmware has wrong CSS header length %u bytes\n", + (css_header->header_len * 4)); + goto out; + } + readcount += sizeof(struct intel_css_header); + + /* Extract Package Header information*/ + package_header = (struct intel_package_header *) + &fw->data[readcount]; + if (sizeof(struct intel_package_header) != + (package_header->header_len * 4)) { + DRM_ERROR("Firmware has wrong package header length %u bytes\n", + (package_header->header_len * 4)); + goto out; + } + readcount += sizeof(struct intel_package_header); + + /* Search for dmc_offset to find firware binary. */ + for (i = 0; i < package_header->num_entries; i++) { + if (package_header->fw_info[i].substepping == '*' && + stepping == package_header->fw_info[i].stepping) { + dmc_offset = package_header->fw_info[i].offset; + break; + } else if (stepping == package_header->fw_info[i].stepping && + substepping == package_header->fw_info[i].substepping) { + dmc_offset = package_header->fw_info[i].offset; + break; + } else if (package_header->fw_info[i].stepping == '*' && + package_header->fw_info[i].substepping == '*') + dmc_offset = package_header->fw_info[i].offset; + } + if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { + DRM_ERROR("Firmware not supported for %c stepping\n", stepping); + goto out; + } + readcount += dmc_offset; + + /* Extract dmc_header information. */ + dmc_header = (struct intel_dmc_header *)&fw->data[readcount]; + if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) { + DRM_ERROR("Firmware has wrong dmc header length %u bytes\n", + (dmc_header->header_len)); + goto out; + } + readcount += sizeof(struct intel_dmc_header); + + /* Cache the dmc header info. */ + if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) { + DRM_ERROR("Firmware has wrong mmio count %u\n", + dmc_header->mmio_count); + goto out; + } + csr->mmio_count = dmc_header->mmio_count; + for (i = 0; i < dmc_header->mmio_count; i++) { + if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE && + dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) { + DRM_ERROR(" Firmware has wrong mmio address 0x%x\n", + dmc_header->mmioaddr[i]); + goto out; + } + csr->mmioaddr[i] = dmc_header->mmioaddr[i]; + csr->mmiodata[i] = dmc_header->mmiodata[i]; + } + + /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ + nbytes = dmc_header->fw_size * 4; + if (nbytes > CSR_MAX_FW_SIZE) { + DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes); + goto out; + } + csr->dmc_fw_size = dmc_header->fw_size; + + csr->dmc_payload = kmalloc(nbytes, GFP_KERNEL); + if (!csr->dmc_payload) { + DRM_ERROR("Memory allocation failed for dmc payload\n"); + goto out; + } + + dmc_payload = csr->dmc_payload; + for (i = 0; i < dmc_header->fw_size; i++) { + uint32_t *tmp = (u32 *)&fw->data[readcount + i * 4]; + /* + * The firmware payload is an array of 32 bit words stored in + * little-endian format in the firmware image and programmed + * as 32 bit big-endian format to memory. + */ + dmc_payload[i] = cpu_to_be32(*tmp); + } + + /* load csr program during system boot, as needed for DC states */ + intel_csr_load_program(dev); +out: + release_firmware(fw); +} + +void intel_csr_ucode_init(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_csr *csr = &dev_priv->csr; + int ret; + + if (!HAS_CSR(dev)) + return; + + if (IS_SKYLAKE(dev)) + csr->fw_path = I915_CSR_SKL; + else { + DRM_ERROR("Unexpected: no known CSR firmware for platform\n"); + return; + } + + /* CSR supported for platform, load firmware */ + ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path, + &dev_priv->dev->pdev->dev, + GFP_KERNEL, dev_priv, + finish_csr_load); + if (ret) + i915_firmware_load_error_print(csr->fw_path, ret); + +} + +void intel_csr_ucode_fini(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!HAS_CSR(dev)) + return; + + kfree(dev_priv->csr.dmc_payload); +} diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index fb8797f1eb8e..8bdb29e3ecb2 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1153,6 +1153,11 @@ u32 skl_plane_ctl_format(uint32_t pixel_format); u32 skl_plane_ctl_tiling(uint64_t fb_modifier); u32 skl_plane_ctl_rotation(unsigned int rotation); +/* intel_csr.c */ +void intel_csr_ucode_init(struct drm_device *dev); +void intel_csr_load_program(struct drm_device *dev); +void intel_csr_ucode_fini(struct drm_device *dev); + /* intel_dp.c */ void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, -- cgit v1.2.3 From dc17430054056049e8b279ffe3f18d0ff13ae3e2 Mon Sep 17 00:00:00 2001 From: Suketu Shah Date: Fri, 17 Apr 2015 19:46:16 +0530 Subject: drm/i915/skl: Add DC5 Trigger Sequence Add triggers as per expectations mentioned in gen9_enable_dc5 and gen9_disable_dc5 patch. Also call POSTING_READ for every write to a register to ensure that its written immediately. v1: Remove POSTING_READ calls as they've already been added in previous patches. v2: Rebase to move all runtime pm specific changes to intel_runtime_pm.c file. Modified as per review comments from Imre: 1] Change variable name 'dc5_allowed' to 'dc5_enabled' to correspond to relevant functions. 2] Move the check dc5_enabled in skl_set_power_well() to disable DC5 into gen9_disable_DC5 which is a more appropriate place. 3] Convert checks for 'pm.dc5_enabled' and 'pm.suspended' in skl_set_power_well() to warnings. However, removing them for now as they'll be included in a future patch asserting DC-state entry/exit criteria. 4] Enable DC5, only when CSR firmware is verified to be loaded. Create new structure to track 'enabled' and 'deferred' status of DC5. 5] Ensure runtime PM reference is obtained, if CSR is not loaded, to avoid entering runtime-suspend and release it when it's loaded. 6] Protect necessary CSR-related code with locks. 7] Move CSR-loading call to runtime PM initialization, as power domains needed to be accessed during deferred DC5-enabling, are not initialized earlier. v3: Rebase to latest. Modified as per review comments from Imre: 1] Use blocking wait for CSR-loading to finish to enable DC5 for simplicity, instead of deferring enabling DC5 until CSR is loaded. 2] Obtain runtime PM reference during CSR-loading initialization itself as deferred DC5- enabling is removed and release it at the end of CSR-loading functionality. 3] Revert calling CSR-loading functionality to the beginning of i915 driver-load functionality to avoid any delay in loading. 4] Define another variable to track whether CSR-loading failed and use it to avoid enabling DC5 if it's true. 5] Define CSR-load-status accessor functions for use later. v4: 1] Disable DC5 before enabling PG2 instead of after it. 2] DC5 was being mistaken enabled even when CSR-loading timed-out. Fix that. 3] Enable DC5-related functionality using a macro. 4] Remove dc5_enabled tracking variable and its use as it's not needed now. v5: 1] Mark CSR failed to load where necessary in finish_csr_load function. 2] Use mutex-protected accessor function to check if CSR loaded instead of directly accessing the variable. 3] Prefix csr_load_status_get/set function names with intel_. v6: rebase to latest. v7: Rebase on top of nightly (Damien) v8: Squashed the patch from Imre - added csr helper pointers to simplify the code. (Imre) v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh) v10: Added a enum for different csr states, suggested by Imre. (Animesh) v11: Based on review comments from Imre, Damien and Daniel following changes done - enum name chnaged to csr_state (singular form). - FW_UNINITIALIZED used as zeroth element in enum csr_state. - Prototype changed for helper function(set/get csr status), using enum csr_state instead of bool. v12: Based on review comment from Imre, introduced bool fw_loaded local to finish_csr_load() which helps calling once to set the csr status. The same flag used to fail RPM if find any issue during firmware loading. Issue: VIZ-2819 Signed-off-by: A.Sunil Kamath Signed-off-by: Suketu Shah Signed-off-by: Damien Lespiau Signed-off-by: Imre Deak Signed-off-by: Animesh Manna Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 7 ++++++ drivers/gpu/drm/i915/intel_csr.c | 42 +++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_drv.h | 3 +++ drivers/gpu/drm/i915/intel_runtime_pm.c | 33 ++++++++++++++++++++++++++ 4 files changed, 83 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index df46e2735991..a49986f8b7f0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -669,6 +669,12 @@ struct intel_uncore { #define for_each_fw_domain(domain__, dev_priv__, i__) \ for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) +enum csr_state { + FW_UNINITIALIZED = 0, + FW_LOADED, + FW_FAILED +}; + struct intel_csr { const char *fw_path; __be32 *dmc_payload; @@ -676,6 +682,7 @@ struct intel_csr { uint32_t mmio_count; uint32_t mmioaddr[8]; uint32_t mmiodata[8]; + enum csr_state state; }; #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index b3d6fbefa5c6..0cae0cd90c21 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -183,6 +183,25 @@ static char intel_get_substepping(struct drm_device *dev) return -ENODATA; } +enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv) +{ + enum csr_state state; + + mutex_lock(&dev_priv->csr_lock); + state = dev_priv->csr.state; + mutex_unlock(&dev_priv->csr_lock); + + return state; +} + +void intel_csr_load_status_set(struct drm_i915_private *dev_priv, + enum csr_state state) +{ + mutex_lock(&dev_priv->csr_lock); + dev_priv->csr.state = state; + mutex_unlock(&dev_priv->csr_lock); +} + void intel_csr_load_program(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -204,6 +223,8 @@ void intel_csr_load_program(struct drm_device *dev) I915_WRITE(dev_priv->csr.mmioaddr[i], dev_priv->csr.mmiodata[i]); } + + dev_priv->csr.state = FW_LOADED; mutex_unlock(&dev_priv->csr_lock); } @@ -220,6 +241,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; uint32_t i; __be32 *dmc_payload; + bool fw_loaded = false; if (!fw) { i915_firmware_load_error_print(csr->fw_path, 0); @@ -326,7 +348,14 @@ static void finish_csr_load(const struct firmware *fw, void *context) /* load csr program during system boot, as needed for DC states */ intel_csr_load_program(dev); + fw_loaded = true; + out: + if (fw_loaded) + intel_runtime_pm_put(dev_priv); + else + intel_csr_load_status_set(dev_priv, FW_FAILED); + release_firmware(fw); } @@ -343,17 +372,25 @@ void intel_csr_ucode_init(struct drm_device *dev) csr->fw_path = I915_CSR_SKL; else { DRM_ERROR("Unexpected: no known CSR firmware for platform\n"); + intel_csr_load_status_set(dev_priv, FW_FAILED); return; } + /* + * Obtain a runtime pm reference, until CSR is loaded, + * to avoid entering runtime-suspend. + */ + intel_runtime_pm_get(dev_priv); + /* CSR supported for platform, load firmware */ ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path, &dev_priv->dev->pdev->dev, GFP_KERNEL, dev_priv, finish_csr_load); - if (ret) + if (ret) { i915_firmware_load_error_print(csr->fw_path, ret); - + intel_csr_load_status_set(dev_priv, FW_FAILED); + } } void intel_csr_ucode_fini(struct drm_device *dev) @@ -363,5 +400,6 @@ void intel_csr_ucode_fini(struct drm_device *dev) if (!HAS_CSR(dev)) return; + intel_csr_load_status_set(dev_priv, FW_FAILED); kfree(dev_priv->csr.dmc_payload); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 8bdb29e3ecb2..980b3aff9bf4 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1155,6 +1155,9 @@ u32 skl_plane_ctl_rotation(unsigned int rotation); /* intel_csr.c */ void intel_csr_ucode_init(struct drm_device *dev); +enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv); +void intel_csr_load_status_set(struct drm_i915_private *dev_priv, + enum csr_state state); void intel_csr_load_program(struct drm_device *dev); void intel_csr_ucode_fini(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 8fe2fdeab652..ffbf9779c26d 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -49,6 +49,8 @@ * present for a given platform. */ +#define GEN9_ENABLE_DC5(dev) (IS_SKYLAKE(dev)) + #define for_each_power_well(i, power_well, domain_mask, power_domains) \ for (i = 0; \ i < (power_domains)->power_well_count && \ @@ -417,9 +419,20 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv) POSTING_READ(DC_STATE_EN); } +static void gen9_enable_dc5(struct drm_i915_private *dev_priv) +{ + /* TODO: Implementation to be done. */ +} + +static void gen9_disable_dc5(struct drm_i915_private *dev_priv) +{ + /* TODO: Implementation to be done. */ +} + static void skl_set_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { + struct drm_device *dev = dev_priv->dev; uint32_t tmp, fuse_status; uint32_t req_mask, state_mask; bool is_enabled, enable_requested, check_fuse_status = false; @@ -459,6 +472,13 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, if (enable) { if (!enable_requested) { + WARN((tmp & state_mask) && + !I915_READ(HSW_PWR_WELL_BIOS), + "Invalid for power well status to be enabled, unless done by the BIOS, \ + when request is to disable!\n"); + if (GEN9_ENABLE_DC5(dev) && + power_well->data == SKL_DISP_PW_2) + gen9_disable_dc5(dev_priv); I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); } @@ -475,6 +495,19 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); POSTING_READ(HSW_PWR_WELL_DRIVER); DRM_DEBUG_KMS("Disabling %s\n", power_well->name); + + if (GEN9_ENABLE_DC5(dev) && + power_well->data == SKL_DISP_PW_2) { + enum csr_state state; + + wait_for((state = intel_csr_load_status_get(dev_priv)) != + FW_UNINITIALIZED, 1000); + if (state != FW_LOADED) + DRM_ERROR("CSR firmware not ready (%d)\n", + state); + else + gen9_enable_dc5(dev_priv); + } } } -- cgit v1.2.3 From 6b457d31ea0465fcadcf6d5044f5f71398954727 Mon Sep 17 00:00:00 2001 From: "A.Sunil Kamath" Date: Thu, 16 Apr 2015 14:22:09 +0530 Subject: drm/i915/skl: Implement enable/disable for Display C5 state. This patch just implements the basic enable and disable functions of DC5 state which is needed for both SKL and BXT. Its important to load respective CSR program before calling enable, which anyways will happen as CSR program is executed during boot. DC5 is a power saving state where hardware dynamically disables power well 1 and the CDCLK PLL and saves the associated registers. DC5 can be entered when software allows it, power well 2 is disabled, and hardware detects that all pipes are disabled or pipe A is enabled with PSR active. Its better to configure display engine to have power well 2 disabled before getting into DC5 enable function. Hence rpm framework will have to ensure to check status of power well 2 before calling gen9_enable_dc5. Rather dc5 entry criteria should be decided based on power well 2 status. If disabled, then call gen9_enable_dc5. v2: Replace HAS_ with IS_ check as per Daniel's review comments v3: Cleared the bits dc5/dc6 enable of DC_STATE_EN register before setting them as per Satheesh's review comments. v4: call POSTING_READ for every write to a register to ensure that its written immediately. v5: Modified as per review comments from Imre. - Squashed register definitions into this patch. - Finetuned comments and functions. v6: Avoid redundant writes in gen9_set_dc_state_debugmask_memory_up function. v7: - Rebase to latest. - Move all runtime PM functions defined in intel_display.c to intel_runtime_pm.c. v8: Rebased to drm-intel-nightly. (Animesh) Issue: VIZ-2819 Signed-off-by: A.Sunil Kamath Signed-off-by: Damien Lespiau Signed-off-by: Animesh Manna Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 41 +++++++++++++++++++++++++++++++-- 2 files changed, 50 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e35d7f29d7c2..1b31238fa531 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7204,6 +7204,17 @@ enum skl_disp_power_wells { #define DC_STATE_EN_UPTO_DC5 (1<<0) #define DC_STATE_EN_DC9 (1<<3) +/* +* SKL DC +*/ +#define DC_STATE_EN 0x45504 +#define DC_STATE_EN_UPTO_DC5 (1<<0) +#define DC_STATE_EN_UPTO_DC6 (2<<0) +#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 + +#define DC_STATE_DEBUG 0x45520 +#define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) + /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, * since on HSW we can't write to it using I915_WRITE. */ #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index ffbf9779c26d..839010a57a2b 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -419,14 +419,51 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv) POSTING_READ(DC_STATE_EN); } +static void gen9_set_dc_state_debugmask_memory_up( + struct drm_i915_private *dev_priv) +{ + uint32_t val; + + /* The below bit doesn't need to be cleared ever afterwards */ + val = I915_READ(DC_STATE_DEBUG); + if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { + val |= DC_STATE_DEBUG_MASK_MEMORY_UP; + I915_WRITE(DC_STATE_DEBUG, val); + POSTING_READ(DC_STATE_DEBUG); + } +} + static void gen9_enable_dc5(struct drm_i915_private *dev_priv) { - /* TODO: Implementation to be done. */ + struct drm_device *dev = dev_priv->dev; + uint32_t val; + + WARN_ON(!IS_GEN9(dev)); + + DRM_DEBUG_KMS("Enabling DC5\n"); + + gen9_set_dc_state_debugmask_memory_up(dev_priv); + + val = I915_READ(DC_STATE_EN); + val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; + val |= DC_STATE_EN_UPTO_DC5; + I915_WRITE(DC_STATE_EN, val); + POSTING_READ(DC_STATE_EN); } static void gen9_disable_dc5(struct drm_i915_private *dev_priv) { - /* TODO: Implementation to be done. */ + struct drm_device *dev = dev_priv->dev; + uint32_t val; + + WARN_ON(!IS_GEN9(dev)); + + DRM_DEBUG_KMS("Disabling DC5\n"); + + val = I915_READ(DC_STATE_EN); + val &= ~DC_STATE_EN_UPTO_DC5; + I915_WRITE(DC_STATE_EN, val); + POSTING_READ(DC_STATE_EN); } static void skl_set_power_well(struct drm_i915_private *dev_priv, -- cgit v1.2.3 From 5aefb2398afad6998d51f90294e02b37b3f19a40 Mon Sep 17 00:00:00 2001 From: Suketu Shah Date: Thu, 16 Apr 2015 14:22:10 +0530 Subject: drm/i915/skl: Assert the requirements to enter or exit DC5. Warn if the conditions to enter or exit DC5 are not satisfied such as support for runtime PM, state of power well, CSR loading etc. v2: Removed camelcase in functions and variables. v3: Do some minimal check to assert if CSR program is not loaded. v4: 1] Used an appropriate function lookup_power_well() to identify power well, instead of using a magic number which can change in future. 2] Split the conditions further in assert_can_enable_DC5() and added more checks. 3] Removed all WARNs from assert_can_disable_DC5 as they were unnecessary and added two new ones. 4] Changed variable names as updated in earlier patches. v5: 1] Change lookup_power_well function to take an int power well id. 2] Define a new intel_display_power_well_is_enabled helper function to check whether a particular power well is enabled. 3] Use CSR-related mutex in assert_csr_loaded function. v6: Remove use of dc5_enabled variable as it's no longer needed. v7: 1] Rebase to latest. 2] Move all DC5-related functions from intel_display.c to intel_runtime_pm.c. v8: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh) v9: Modified below changes based on review comments from Imre. - Moved intel_display_power_well_is_enabled() to intel_runtime_pm.c. - Removed mutex lock from assert_csr_loaded(). (Animesh) Issue: VIZ-2819 Signed-off-by: A.Sunil Kamath Signed-off-by: Suketu Shah Signed-off-by: Damien Lespiau Signed-off-by: Animesh Manna Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_csr.c | 9 ++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_runtime_pm.c | 51 +++++++++++++++++++++++++++++---- 3 files changed, 56 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 0cae0cd90c21..9311cddb86e6 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -403,3 +403,12 @@ void intel_csr_ucode_fini(struct drm_device *dev) intel_csr_load_status_set(dev_priv, FW_FAILED); kfree(dev_priv->csr.dmc_payload); } + +void assert_csr_loaded(struct drm_i915_private *dev_priv) +{ + WARN((intel_csr_load_status_get(dev_priv) != FW_LOADED), "CSR is not loaded.\n"); + WARN(!I915_READ(CSR_PROGRAM_BASE), + "CSR program storage start is NULL\n"); + WARN(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); + WARN(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); +} diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 980b3aff9bf4..ddf3fefd96b2 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1160,6 +1160,7 @@ void intel_csr_load_status_set(struct drm_i915_private *dev_priv, enum csr_state state); void intel_csr_load_program(struct drm_device *dev); void intel_csr_ucode_fini(struct drm_device *dev); +void assert_csr_loaded(struct drm_i915_private *dev_priv); /* intel_dp.c */ void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 839010a57a2b..2f7f0ab363fb 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -64,6 +64,9 @@ i--) \ if ((power_well)->domains & (domain_mask)) +bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, + int power_well_id); + /* * We should only use the power well if we explicitly asked the hardware to * enable it, so check if it's enabled and also check if we've requested it to @@ -433,12 +436,39 @@ static void gen9_set_dc_state_debugmask_memory_up( } } -static void gen9_enable_dc5(struct drm_i915_private *dev_priv) +static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; + bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, + SKL_DISP_PW_2); + + WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); + WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); + WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n"); + + WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), + "DC5 already programmed to be enabled.\n"); + WARN(dev_priv->pm.suspended, + "DC5 cannot be enabled, if platform is runtime-suspended.\n"); + + assert_csr_loaded(dev_priv); +} + +static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) +{ + bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, + SKL_DISP_PW_2); + + WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n"); + WARN(dev_priv->pm.suspended, + "Disabling of DC5 while platform is runtime-suspended should never happen.\n"); +} + +static void gen9_enable_dc5(struct drm_i915_private *dev_priv) +{ uint32_t val; - WARN_ON(!IS_GEN9(dev)); + assert_can_enable_dc5(dev_priv); DRM_DEBUG_KMS("Enabling DC5\n"); @@ -453,10 +483,9 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv) static void gen9_disable_dc5(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; uint32_t val; - WARN_ON(!IS_GEN9(dev)); + assert_can_disable_dc5(dev_priv); DRM_DEBUG_KMS("Disabling DC5\n"); @@ -1416,7 +1445,7 @@ static struct i915_power_well chv_power_wells[] = { }; static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, - enum punit_power_well power_well_id) + int power_well_id) { struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_well *power_well; @@ -1430,6 +1459,18 @@ static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_pr return NULL; } +bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, + int power_well_id) +{ + struct i915_power_well *power_well; + bool ret; + + power_well = lookup_power_well(dev_priv, power_well_id); + ret = power_well->ops->is_enabled(dev_priv, power_well); + + return ret; +} + static struct i915_power_well skl_power_wells[] = { { .name = "always-on", -- cgit v1.2.3 From f75a1985137f272dff1a361b763a76fb8f68c3b9 Mon Sep 17 00:00:00 2001 From: Suketu Shah Date: Thu, 16 Apr 2015 14:22:11 +0530 Subject: drm/i915/skl: Add DC6 Trigger sequence. Add triggers for DC6 as per details provided in skl_enable_dc6 and skl_disable_dc6 implementations. Also Call POSTING_READ for every write to a register to ensure it is written to immediately v1: Remove POSTING_READ and intel_prepare_ddi calls as they've been added in previous patches. v2: 1] Remove check for backlight disabled as it should be the case by that time. 2] Mark DC5 as disabled when enabling DC6. 3] Return from DC5-disabling function early if DC5 is already be disabled which can happen due to DC6-enabling earlier. 3] Ensure CSR firmware is loaded after resume from DC6 as corresponding memory contents won't be retained after runtime-suspend. 4] Ensure that CSR isn't identified as loaded before CSR-loading program is called during runtime-resume. v3: Rebase to latest Modified as per review comments from Imre and after discussion with Art: 1] DC6 should be preferably enabled when PG2 is disabled by SW as the check for PG1 being disabled is taken of by HW to enter DC6, and disabled when PG2 is enabled respectively. This helps save more power, especially in the case when display is disabled but GT is enabled. Accordingly, replacing DC5 trigger sequence with DC6 for SKL. 2] DC6 could be enabled from intel_runtime_suspend() function, if DC5 is already enabled. 3] Move CSR-load-status setting code from intel_runtime_suspend function to a new function. v4: 1] Enable/disable DC6 only when toggling the power-well using a newly defined macro ENABLE_DC6. v5: 1] Load CSR on system resume too as firmware may be lost on system suspend preventing enabling DC5, DC6. 2] DDI buffers shouldn't be programmed during driver-load/resume as it's already done during modeset initialization then and also that the encoder list is still uninitialized by then. Therefore, call intel_prepare_ddi function right after disabling DC6 but outside skl_disable_dc6 function and not during driver-load/resume. v6: 1] Rebase to latest. 2] Move SKL_ENABLE_DC6 macro definition from intel_display.c to intel_runtime_pm.c. v7: 1) Refactored the code for removing the warning got from checkpatch. 2) After adding dmc ver 1.0 support rebased on top of nightly. (Animesh) v8: - Reverted the changes done in v7. - Removed the condition check in skl_prepare_resune(). (Animesh) Issue: VIZ-2819 Signed-off-by: A.Sunil Kamath Signed-off-by: Suketu Shah Signed-off-by: Damien Lespiau Signed-off-by: Animesh Manna Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 30 +++++++++++++++++++++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 43 +++++++++++++++++++++++++++------ 2 files changed, 66 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b743bb17e288..334bcc1badaa 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -594,6 +594,8 @@ static void intel_suspend_encoders(struct drm_i915_private *dev_priv) static int intel_suspend_complete(struct drm_i915_private *dev_priv); static int vlv_resume_prepare(struct drm_i915_private *dev_priv, bool rpm_resume); +static int skl_resume_prepare(struct drm_i915_private *dev_priv); + static int i915_drm_suspend(struct drm_device *dev) { @@ -808,6 +810,8 @@ static int i915_drm_resume_early(struct drm_device *dev) if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) hsw_disable_pc8(dev_priv); + else if (IS_SKYLAKE(dev_priv)) + ret = skl_resume_prepare(dev_priv); intel_uncore_sanitize(dev); intel_power_domains_init_hw(dev_priv); @@ -1022,6 +1026,19 @@ static int i915_pm_resume(struct device *dev) return i915_drm_resume(drm_dev); } +static int skl_suspend_complete(struct drm_i915_private *dev_priv) +{ + /* Enabling DC6 is not a hard requirement to enter runtime D3 */ + + /* + * This is to ensure that CSR isn't identified as loaded before + * CSR-loading program is called during runtime-resume. + */ + intel_csr_load_status_set(dev_priv, FW_UNINITIALIZED); + + return 0; +} + static int hsw_suspend_complete(struct drm_i915_private *dev_priv) { hsw_enable_pc8(dev_priv); @@ -1061,6 +1078,15 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv) return 0; } +static int skl_resume_prepare(struct drm_i915_private *dev_priv) +{ + struct drm_device *dev = dev_priv->dev; + + intel_csr_load_program(dev); + + return 0; +} + /* * Save all Gunit registers that may be lost after a D3 and a subsequent * S0i[R123] transition. The list of registers needing a save/restore is @@ -1536,6 +1562,8 @@ static int intel_runtime_resume(struct device *device) if (IS_BROXTON(dev)) ret = bxt_resume_prepare(dev_priv); + else if (IS_SKYLAKE(dev)) + ret = skl_resume_prepare(dev_priv); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) hsw_disable_pc8(dev_priv); else if (IS_VALLEYVIEW(dev_priv)) @@ -1570,6 +1598,8 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv) if (IS_BROXTON(dev)) ret = bxt_suspend_complete(dev_priv); + else if (IS_SKYLAKE(dev)) + ret = skl_suspend_complete(dev_priv); else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ret = hsw_suspend_complete(dev_priv); else if (IS_VALLEYVIEW(dev)) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 2f7f0ab363fb..5bd7f083aa34 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -49,7 +49,8 @@ * present for a given platform. */ -#define GEN9_ENABLE_DC5(dev) (IS_SKYLAKE(dev)) +#define GEN9_ENABLE_DC5(dev) 0 +#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev) #define for_each_power_well(i, power_well, domain_mask, power_domains) \ for (i = 0; \ @@ -495,6 +496,16 @@ static void gen9_disable_dc5(struct drm_i915_private *dev_priv) POSTING_READ(DC_STATE_EN); } +static void skl_enable_dc6(struct drm_i915_private *dev_priv) +{ + /* TODO: Implementation to be done. */ +} + +static void skl_disable_dc6(struct drm_i915_private *dev_priv) +{ + /* TODO: Implementation to be done. */ +} + static void skl_set_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { @@ -542,9 +553,21 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, !I915_READ(HSW_PWR_WELL_BIOS), "Invalid for power well status to be enabled, unless done by the BIOS, \ when request is to disable!\n"); - if (GEN9_ENABLE_DC5(dev) && - power_well->data == SKL_DISP_PW_2) - gen9_disable_dc5(dev_priv); + if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && + power_well->data == SKL_DISP_PW_2) { + if (SKL_ENABLE_DC6(dev)) { + skl_disable_dc6(dev_priv); + /* + * DDI buffer programming unnecessary during driver-load/resume + * as it's already done during modeset initialization then. + * It's also invalid here as encoder list is still uninitialized. + */ + if (!dev_priv->power_domains.initializing) + intel_prepare_ddi(dev); + } else { + gen9_disable_dc5(dev_priv); + } + } I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); } @@ -562,17 +585,23 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, POSTING_READ(HSW_PWR_WELL_DRIVER); DRM_DEBUG_KMS("Disabling %s\n", power_well->name); - if (GEN9_ENABLE_DC5(dev) && + if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && power_well->data == SKL_DISP_PW_2) { enum csr_state state; - + /* TODO: wait for a completion event or + * similar here instead of busy + * waiting using wait_for function. + */ wait_for((state = intel_csr_load_status_get(dev_priv)) != FW_UNINITIALIZED, 1000); if (state != FW_LOADED) DRM_ERROR("CSR firmware not ready (%d)\n", state); else - gen9_enable_dc5(dev_priv); + if (SKL_ENABLE_DC6(dev)) + skl_enable_dc6(dev_priv); + else + gen9_enable_dc5(dev_priv); } } } -- cgit v1.2.3 From 74b4f371f56fc7ca4058041080b30d5b0a7271af Mon Sep 17 00:00:00 2001 From: "A.Sunil Kamath" Date: Thu, 16 Apr 2015 14:22:12 +0530 Subject: Implement enable/disable for Display C6 state This patch just implements the basic enable and disable functions of DC6 state which is needed for SKL platform. Its important to load SKL CSR program before calling enable. DC6 is a deeper power saving state where hardware dynamically disables power well 0 and saves the associated registers. DC6 can be entered when software allows it, the conditions for DC5 are met, and the PCU allows DC6. DC6 cannot be used if the backlight is being driven from the display utility pin. Its better to configure display engine to have power well 2 disabled before getting into DC6 enable function. Hence rpm framework will ensure to check status of power well 2 and DC5 before calling skl_enable_dc6. v2: Replace HAS_ with IS_ check as per Daniel's review comments v3: Cleared the bits dc5/dc6 enable of DC_STATE_EN register before setting them as per Satheesh's review comments. v4: No need to call gen9_disable_dc5 inside enable sequence of DC6, as its already take care above. v5: call POSTING_READ for every write to a register to ensure that its written immediately. Call intel_prepare_ddi during DC6 exit as it's required on low-power exit. v6: Protect DC6-enabling-disabling functionality with locks to synchronize with CSR-loading code. v7: Remove grabbing CSR-related mutex in skl_enable/disable_dc6 functions as deferred DC5-enabling functionality is now removed. v8: Remove 'Disabling DC5' from the debug comment during DC6 enabling as when DC6 is allowed, DC5 is not programmed at all. v9: - Rebase to latest. - Move all DC6-related functions from intel_display.c to intel_runtime_pm.c. v10: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh) Issue: VIZ-2819 Signed-off-by: A.Sunil Kamath Signed-off-by: Damien Lespiau Signed-off-by: Animesh Manna Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 5bd7f083aa34..39810844a9c9 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -498,12 +498,35 @@ static void gen9_disable_dc5(struct drm_i915_private *dev_priv) static void skl_enable_dc6(struct drm_i915_private *dev_priv) { - /* TODO: Implementation to be done. */ + struct drm_device *dev = dev_priv->dev; + uint32_t val; + + WARN_ON(!IS_SKYLAKE(dev)); + + DRM_DEBUG_KMS("Enabling DC6\n"); + + gen9_set_dc_state_debugmask_memory_up(dev_priv); + + val = I915_READ(DC_STATE_EN); + val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; + val |= DC_STATE_EN_UPTO_DC6; + I915_WRITE(DC_STATE_EN, val); + POSTING_READ(DC_STATE_EN); } static void skl_disable_dc6(struct drm_i915_private *dev_priv) { - /* TODO: Implementation to be done. */ + struct drm_device *dev = dev_priv->dev; + uint32_t val; + + WARN_ON(!IS_SKYLAKE(dev)); + + DRM_DEBUG_KMS("Disabling DC6\n"); + + val = I915_READ(DC_STATE_EN); + val &= ~DC_STATE_EN_UPTO_DC6; + I915_WRITE(DC_STATE_EN, val); + POSTING_READ(DC_STATE_EN); } static void skl_set_power_well(struct drm_i915_private *dev_priv, -- cgit v1.2.3 From 93c7cb6c3a2f8c7204fc8bcf7769059875a54027 Mon Sep 17 00:00:00 2001 From: Suketu Shah Date: Thu, 16 Apr 2015 14:22:13 +0530 Subject: drm/i915/skl: Assert the requirements to enter or exit DC6. Warn if the conditions to enter or exit DC6 are not satisfied such as support for runtime PM, state of power well, CSR loading etc. v2: Removed camelcase in functions and variables. v3: Do some minimal check to assert if CSR program is not loaded. v4: 1] Correct the check for backlight-disabling in assert_can_enable_dc6(). 2] Check csr.loaded = false before disabling DC6 and simplify other checks. v5: 1] Remove checks for DC5 state from assert_can_enable_dc6 function as DC5 is no longer enabled before enabling DC6. 2] Correct the check for CSR-loading in assert_can_disable_dc6 function as CSR must be loaded for context restore to happen on DC6 disabling. v6: 1] It's okay to explicitly disable DC6 during driver-load/resume even though it might already be disabled and so don't warn about it. v7: Rebase to latest. v8: Sqashed the patch from Imre - [PATCH] drm/i915/skl: avoid false CSR fw not loaded WARN during driver load/resume v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh) v10: During initialization added a early return before disabling DC5. (Animesh) Issue: VIZ-2819 Signed-off-by: A.Sunil Kamath Signed-off-by: Suketu Shah Signed-off-by: Damien Lespiau Signed-off-by: Animesh Manna Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 40 +++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 39810844a9c9..b393db78e5cb 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -459,6 +459,12 @@ static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) { bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, SKL_DISP_PW_2); + /* + * During initialization, the firmware may not be loaded yet. + * We still want to make sure that the DC enabling flag is cleared. + */ + if (dev_priv->power_domains.initializing) + return; WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n"); WARN(dev_priv->pm.suspended, @@ -496,12 +502,39 @@ static void gen9_disable_dc5(struct drm_i915_private *dev_priv) POSTING_READ(DC_STATE_EN); } -static void skl_enable_dc6(struct drm_i915_private *dev_priv) +static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; + + WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); + WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); + WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, + "Backlight is not disabled.\n"); + WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), + "DC6 already programmed to be enabled.\n"); + + assert_csr_loaded(dev_priv); +} + +static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) +{ + /* + * During initialization, the firmware may not be loaded yet. + * We still want to make sure that the DC enabling flag is cleared. + */ + if (dev_priv->power_domains.initializing) + return; + + assert_csr_loaded(dev_priv); + WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), + "DC6 already programmed to be disabled.\n"); +} + +static void skl_enable_dc6(struct drm_i915_private *dev_priv) +{ uint32_t val; - WARN_ON(!IS_SKYLAKE(dev)); + assert_can_enable_dc6(dev_priv); DRM_DEBUG_KMS("Enabling DC6\n"); @@ -516,10 +549,9 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv) static void skl_disable_dc6(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; uint32_t val; - WARN_ON(!IS_SKYLAKE(dev)); + assert_can_disable_dc6(dev_priv); DRM_DEBUG_KMS("Disabling DC6\n"); -- cgit v1.2.3 From 00776511da7134b25dd3ea45e2bf38ea08738a64 Mon Sep 17 00:00:00 2001 From: Suketu Shah Date: Thu, 16 Apr 2015 14:22:14 +0530 Subject: drm/i915/skl: Enable runtime PM Enable runtime PM for Skylake platform v2: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh) Issue: VIZ-2819 Signed-off-by: A.Sunil Kamath Signed-off-by: Suketu Shah Signed-off-by: Damien Lespiau Signed-off-by: Animesh Manna Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a49986f8b7f0..136d42a2ef44 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2443,7 +2443,8 @@ struct drm_i915_cmd_table { IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ IS_SKYLAKE(dev)) #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ - IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) + IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ + IS_SKYLAKE(dev)) #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) -- cgit v1.2.3 From 09b1eb130e43264d6a4e8c99ed75d07f40a2d4b3 Mon Sep 17 00:00:00 2001 From: Todd Previte Date: Mon, 20 Apr 2015 15:27:34 -0700 Subject: drm/i915: Move Displayport test request and sink IRQ logic to intel_dp_detect() Due to changes in the driver and to support Displayport compliance testing, the test request and sink IRQ logic has been relocated from intel_dp_check_link_status to intel_dp_detect. This is because the bulk of the compliance tests that set the TEST_REQUEST bit in the DEVICE_IRQ field of the DPCD issue a long pulse / hot plug event to signify the start of the test. Currently, for a long pulse, intel_dp_check_link_status is not called for a long HPD pulse, so if test requests come in, they cannot be detected by the driver. Once located in the intel_dp_detect, in the regular hot plug event path, proper detection of Displayport compliance test requests occurs which then invokes the test handler to support them. Additionally, this places compliance testing in the normal operational paths, eliminating as much special case code as possible. The only change in intel_dp_check_link_status with this patch is that when the IRQ is the result of a test request from the sink, the test handler is not invoked during the short pulse path. Short pulse test requests are for a particular variety of tests (mainly link training) that will be implemented in the future. Once those tests are available, the test request handler will be called from here as well. V2: - Rewored the commit message to be more clear about the content and intent of this patch - Restore IRQ detection logic to intel_dp_check_link_status(). Continue to detect and clear sink IRQs in the short pulse case. Ignore test requests in the short pulses for now since they are for future test implementations. Signed-off-by: Todd Previte Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 937ba31d8dde..bacdec5d8f3f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4220,7 +4220,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) sink_irq_vector); if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) - intel_dp_handle_test_request(intel_dp); + DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); } @@ -4450,6 +4450,7 @@ intel_dp_detect(struct drm_connector *connector, bool force) enum drm_connector_status status; enum intel_display_power_domain power_domain; bool ret; + u8 sink_irq_vector; DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); @@ -4492,6 +4493,20 @@ intel_dp_detect(struct drm_connector *connector, bool force) intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; status = connector_status_connected; + /* Try to read the source of the interrupt */ + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && + intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { + /* Clear interrupt source */ + drm_dp_dpcd_writeb(&intel_dp->aux, + DP_DEVICE_SERVICE_IRQ_VECTOR, + sink_irq_vector); + + if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) + intel_dp_handle_test_request(intel_dp); + if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) + DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); + } + out: intel_dp_power_put(intel_dp, power_domain); return status; -- cgit v1.2.3 From 06615ee5c54740a970754b6d8d7d5e7106dec186 Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Fri, 24 Apr 2015 15:09:03 +0300 Subject: drm/i915: Do not clear mappings beyond VMA size Do not to clear mappings outside the allocated VMA under any circumstances. Only clear the smaller of VMA or object page count. This is required to allow creating partial object VMAs which in turn are needed for partial GGTT views. Signed-off-by: Joonas Lahtinen Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 9d3852c521c7..fc562c68bf48 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1945,19 +1945,23 @@ static void ggtt_unbind_vma(struct i915_vma *vma) struct drm_device *dev = vma->vm->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj = vma->obj; + const uint64_t size = min_t(uint64_t, + obj->base.size, + vma->node.size); if (vma->bound & GLOBAL_BIND) { vma->vm->clear_range(vma->vm, vma->node.start, - obj->base.size, + size, true); } if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) { struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; + appgtt->base.clear_range(&appgtt->base, vma->node.start, - obj->base.size, + size, true); } } -- cgit v1.2.3 From 0b6cc18810cfa958985602ab1849b647250deb0f Mon Sep 17 00:00:00 2001 From: Fabian Frederick Date: Sat, 25 Apr 2015 11:34:29 +0200 Subject: drm/i915: use ERR_CAST instead of ERR_PTR/PTR_ERR Inspired by scripts/coccinelle/api/err_cast.cocci Signed-off-by: Fabian Frederick Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ddf3fefd96b2..ea20edb58528 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1419,7 +1419,7 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state, struct drm_crtc_state *crtc_state; crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); if (IS_ERR(crtc_state)) - return ERR_PTR(PTR_ERR(crtc_state)); + return ERR_CAST(crtc_state); return to_intel_crtc_state(crtc_state); } -- cgit v1.2.3 From d86ed34a4eeefffcc9030e903465a902f6aea9f3 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 13:41:19 +0100 Subject: drm/i915: Add RPS thresholds to debugfs/i915_frequency_info Expose some more of our internal RPS bookkeeping for debugging. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9c2b9e450799..9e5a56cff2f3 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1211,12 +1211,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused) GEN6_CURBSYTAVG_MASK); seq_printf(m, "RP PREV UP: %dus\n", rpprevup & GEN6_CURBSYTAVG_MASK); + seq_printf(m, "Up threshold: %d%%\n", + dev_priv->rps.up_threshold); + seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & GEN6_CURIAVG_MASK); seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & GEN6_CURBSYTAVG_MASK); seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & GEN6_CURBSYTAVG_MASK); + seq_printf(m, "Down threshold: %d%%\n", + dev_priv->rps.down_threshold); max_freq = (rp_state_cap & 0xff0000) >> 16; max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); @@ -1232,12 +1237,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused) max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); - seq_printf(m, "Max overclocked frequency: %dMHz\n", intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); + seq_printf(m, "Current freq: %d MHz\n", + intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); + seq_printf(m, "Actual freq: %d MHz\n", cagf); seq_printf(m, "Idle freq: %d MHz\n", intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); + seq_printf(m, "Min freq: %d MHz\n", + intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); + seq_printf(m, "Max freq: %d MHz\n", + intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); + seq_printf(m, + "efficient (RPe) frequency: %d MHz\n", + intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); } else if (IS_VALLEYVIEW(dev)) { u32 freq_sts; @@ -1246,6 +1260,12 @@ static int i915_frequency_info(struct seq_file *m, void *unused) seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); + seq_printf(m, "actual GPU freq: %d MHz\n", + intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); + + seq_printf(m, "current GPU freq: %d MHz\n", + intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); + seq_printf(m, "max GPU freq: %d MHz\n", intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); @@ -1258,9 +1278,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused) seq_printf(m, "efficient (RPe) frequency: %d MHz\n", intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); - - seq_printf(m, "current GPU freq: %d MHz\n", - intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); mutex_unlock(&dev_priv->rps.hw_lock); } else { seq_puts(m, "no P-state info available\n"); -- cgit v1.2.3 From d4dc5e92c00d41044a86bd98243b322000514d41 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 28 Apr 2015 08:48:03 +0100 Subject: drm/i915: Remove incorrect restriction on 32bit offsets in ppGTT backend This is the wrong layer to apply an arbitrary restriction and the wrong error code (object too large!). If we do want to prevent large offsets being return to the user on 32bit systems (to hide bugs in userspace), you want to restrict the drm_mm range manager instead. This first tells userspace about the correct size of the GTT they can use (so they don't try and overallocate object or batches), and fixes the eviction logic to avoid the eventual and *guaranteed* error. Fixes regression in commit d7b2633dba04ef0fd7385f02a7b552abc5f1062f Author: Michel Thierry Date: Wed Apr 8 12:13:34 2015 +0100 drm/i915/gen8: Dynamic page table allocations Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Mika Kuoppala Cc: Daniel Vetter Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 9 --------- 1 file changed, 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index fc562c68bf48..ce91314f2c0c 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -844,15 +844,6 @@ static int gen8_alloc_va_range(struct i915_address_space *vm, uint32_t pdpe; int ret; -#ifndef CONFIG_64BIT - /* Disallow 64b address on 32b platforms. Nothing is wrong with doing - * this in hardware, but a lot of the drm code is not prepared to handle - * 64b offset on 32b platforms. - * This will be addressed when 48b PPGTT is added */ - if (start + length > 0x100000000ULL) - return -E2BIG; -#endif - /* Wrap is never okay since we can only represent 48b, and we don't * actually use the other side of the canonical address space. */ -- cgit v1.2.3 From 3126a660f352b3fe48125a8a0b4fdbf85935d8bf Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 30 Apr 2015 17:30:50 +0300 Subject: drm/i915: checking IS_ERR() instead of NULL We switched from calling i915_gem_alloc_context_obj() to calling i915_gem_alloc_object() so the error handling needs to be updated to check for NULL instead of IS_ERR(). Fixes: 149c86e74fe4 ('drm/i915: Allocate context objects from stolen') Signed-off-by: Dan Carpenter Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_lrc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 732fd633e73a..0fa9209ff556 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1895,10 +1895,9 @@ int intel_lr_context_deferred_create(struct intel_context *ctx, context_size = round_up(get_lr_context_size(ring), 4096); ctx_obj = i915_gem_alloc_object(dev, context_size); - if (IS_ERR(ctx_obj)) { - ret = PTR_ERR(ctx_obj); - DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); - return ret; + if (!ctx_obj) { + DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); + return -ENOMEM; } if (is_global_default_ctx) { -- cgit v1.2.3 From 3ef62342bd854fff5d792d67fc6a8e66f26c862b Mon Sep 17 00:00:00 2001 From: Deepak S Date: Wed, 29 Apr 2015 08:36:24 +0530 Subject: drm/i915: Setup static bias for GPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on the spec, Setting up static BIAS for GPU to improve the rps performace. v2: rename reg defn to match spec. (Ville) v3: Updated bias setting for chv (Deepak) Signed-off-by: Deepak S Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++ 2 files changed, 18 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1b31238fa531..1d4871b8fdab 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -670,6 +670,12 @@ enum skl_disp_power_wells { #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 +#define VLV_TURBO_SOC_OVERRIDE 0x04 +#define VLV_OVERRIDE_EN 1 +#define VLV_SOC_TDP_EN (1 << 1) +#define VLV_BIAS_CPU_125_SOC_875 (6 << 2) +#define CHV_BIAS_CPU_50_SOC_50 (3 << 2) + #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 /* vlv2 north clock has */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a7516ed24eee..8812fffeac5e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5082,6 +5082,12 @@ static void cherryview_enable_rps(struct drm_device *dev) GEN6_RP_UP_BUSY_AVG | GEN6_RP_DOWN_IDLE_AVG); + /* Setting Fixed Bias */ + val = VLV_OVERRIDE_EN | + VLV_SOC_TDP_EN | + CHV_BIAS_CPU_50_SOC_50; + vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); /* RPS code assumes GPLL is used */ @@ -5166,6 +5172,12 @@ static void valleyview_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RC_CONTROL, rc6_mode); + /* Setting Fixed Bias */ + val = VLV_OVERRIDE_EN | + VLV_SOC_TDP_EN | + VLV_BIAS_CPU_125_SOC_875; + vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); /* RPS code assumes GPLL is used */ -- cgit v1.2.3 From 4e96c97742f4201edf1b0f8e1b1b6b2ac6ff33e7 Mon Sep 17 00:00:00 2001 From: Mika Kahola Date: Wed, 29 Apr 2015 09:17:39 +0300 Subject: drm/i915: eDP link training optimization This is a first of series patches that optimize DP link training. The first patch is for eDP only where we reuse the previously trained link training values from cache i.e. voltage swing and pre-emphasis levels. In case we are not able to train the link by reusing the known values, the link training parameters are set to zero and training is restarted. V2: - flag that indicates if DP link is trained and valid renamed from 'link_trained' to 'train_set_valid' - removed routine 'intel_dp_reuse_link_train' V3: - rebased against the latest drm-intel-nightly V4: - removed HPD long pulse handling for eDP case to clear the flag that indicates to reuse the current link training parameters. (based on Sivakumar's comment) Signed-off-by: Mika Kahola Reviewed-by: Sivakumar Thulasimani [danvet: s/DP/eDP/ in subject to make scope clear.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 27 ++++++++++++++++++++++++--- drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 25 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index bacdec5d8f3f..1af97adadde8 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3547,7 +3547,8 @@ static bool intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, uint8_t dp_train_pat) { - memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); + if (!intel_dp->train_set_valid) + memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); intel_dp_set_signal_levels(intel_dp, DP); return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); } @@ -3660,6 +3661,23 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) break; } + /* + * if we used previously trained voltage and pre-emphasis values + * and we don't get clock recovery, reset link training values + */ + if (intel_dp->train_set_valid) { + DRM_DEBUG_KMS("clock recovery not ok, reset"); + /* clear the flag as we are not reusing train set */ + intel_dp->train_set_valid = false; + if (!intel_dp_reset_link_train(intel_dp, &DP, + DP_TRAINING_PATTERN_1 | + DP_LINK_SCRAMBLING_DISABLE)) { + DRM_ERROR("failed to enable link training\n"); + return; + } + continue; + } + /* Check to see if we've tried the max voltage */ for (i = 0; i < intel_dp->lane_count; i++) if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) @@ -3737,6 +3755,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) /* Make sure clock is still ok */ if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { + intel_dp->train_set_valid = false; intel_dp_start_link_train(intel_dp); intel_dp_set_link_train(intel_dp, &DP, training_pattern | @@ -3752,6 +3771,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) /* Try 5 times, then try clock recovery if that fails */ if (tries > 5) { + intel_dp->train_set_valid = false; intel_dp_start_link_train(intel_dp); intel_dp_set_link_train(intel_dp, &DP, training_pattern | @@ -3773,9 +3793,10 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) intel_dp->DP = DP; - if (channel_eq) + if (channel_eq) { + intel_dp->train_set_valid = is_edp(intel_dp); DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); - + } } void intel_dp_stop_link_train(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ea20edb58528..cf701ed26478 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -736,6 +736,7 @@ struct intel_dp { bool has_aux_irq, int send_bytes, uint32_t aux_clock_divider); + bool train_set_valid; /* Displayport compliance testing */ unsigned long compliance_test_type; -- cgit v1.2.3 From 5fa836a9d85975c5f0f1219669523c1f0ac64349 Mon Sep 17 00:00:00 2001 From: Mika Kahola Date: Wed, 29 Apr 2015 09:17:40 +0300 Subject: drm/i915: DP link training optimization This patch adds DP link training optimization by reusing the previously trained values. v2: - rebase V3: - rebase V4: - when HPD long pulse is received, the flag is cleared that indicates if DP link training is required or not (based on Sivakumar's comment) Signed-off-by: Mika Kahola Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1af97adadde8..7c3dbd465c78 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3794,7 +3794,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) intel_dp->DP = DP; if (channel_eq) { - intel_dp->train_set_valid = is_edp(intel_dp); + intel_dp->train_set_valid = true; DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); } } @@ -4858,6 +4858,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) intel_display_power_get(dev_priv, power_domain); if (long_hpd) { + /* indicate that we need to restart link training */ + intel_dp->train_set_valid = false; if (HAS_PCH_SPLIT(dev)) { if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) -- cgit v1.2.3 From 65b38e0d87a491e25848bea3274825b594cbdb22 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 13 Apr 2015 11:26:56 +0300 Subject: drm/i915: make drm_crtc_helper_funcs const data Because they can be. Signed-off-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 14709547659f..abbca0e76ccf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11034,7 +11034,7 @@ out_hang: return ret; } -static struct drm_crtc_helper_funcs intel_helper_funcs = { +static const struct drm_crtc_helper_funcs intel_helper_funcs = { .mode_set_base_atomic = intel_pipe_set_base_atomic, .load_lut = intel_crtc_load_lut, .atomic_begin = intel_begin_crtc_commit, -- cgit v1.2.3 From 5e562f1dddfa3242cede5ec49888260a856a9da2 Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Thu, 30 Apr 2015 11:02:31 +0300 Subject: drm/i915: Clear vma->bound on unbinding Unbinding doesn't always lead to unconditional destruction of vma. This destruction avoidance happens if vma is part of execbuffer relocation list or if vma is being considered for eviction in i915_gem_evict_something(). For those other users, mark the vma unbound so that the correct state of this vma is preserved. Reported-by: Chris Wilson Cc: Chris Wilson Cc: Daniel Vetter Signed-off-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e8f6f4c0a2c6..c378f0421145 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3069,6 +3069,7 @@ int i915_vma_unbind(struct i915_vma *vma) trace_i915_vma_unbind(vma); vma->vm->unbind_vma(vma); + vma->bound = 0; list_del_init(&vma->mm_list); if (i915_is_ggtt(vma->vm)) { -- cgit v1.2.3 From 4dd738e9cd791ebac2a009f09f1761e85e7f0805 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Thu, 30 Apr 2015 16:06:51 +0100 Subject: drm/i915: Fix 32b overflow check in gen8_ppgtt_alloc_page_directories MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The patch 69876bed7e008f5fe01538a2d47c09f2862129d0: "drm/i915/gen8: page directories rework allocation" added an overflow warning, but the mask had an extra 0. Use less typo-prone option suggested by Dave instead, to check for (start + length) >= 0x100000000ULL. This check will be unnecessary after gen8_alloc_va_range handles more than 4 PDPs (48b addressing). v2: Really check for 32b overflow (Ville) Reported-by: Dan Carpenter Cc: Dave Gordon Cc: Ville Syrjälä Signed-off-by: Michel Thierry Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index ce91314f2c0c..8fee6789fae2 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -756,8 +756,8 @@ static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES)); - /* FIXME: PPGTT container_of won't work for 64b */ - WARN_ON((start + length) > 0x800000000ULL); + /* FIXME: upper bound must not overflow 32 bits */ + WARN_ON((start + length) >= (1ULL << 32)); gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { if (pd) -- cgit v1.2.3 From aeaa2122af4e53f3bfd28e8f294557bb95af43fc Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Thu, 30 Apr 2015 16:39:16 +0100 Subject: drm/i915/skl: Add the INIT power domain to the MISC I/O power well MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Damien Lespiau Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index b393db78e5cb..64968d4ec62c 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -314,7 +314,8 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ BIT(POWER_DOMAIN_INIT)) #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ - SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS) + SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ + BIT(POWER_DOMAIN_INIT)) #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ -- cgit v1.2.3 From 71cd8423cd874d18d9a454a39e2c4d9c9fb3fc69 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Thu, 30 Apr 2015 16:39:17 +0100 Subject: drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Damien Lespiau Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++--------- drivers/gpu/drm/i915/intel_ddi.c | 26 +++++++++++++------------- drivers/gpu/drm/i915/intel_display.c | 6 +++--- drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------ 5 files changed, 32 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 136d42a2ef44..51baca1e085b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -295,7 +295,7 @@ struct intel_dpll_hw_state { /* skl */ /* * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in - * lower part of crtl1 and they get shifted into position when writing + * lower part of ctrl1 and they get shifted into position when writing * the register. This allows us to easily compare the state to share * the DPLL. */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1d4871b8fdab..8924f4b68893 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7141,16 +7141,16 @@ enum skl_disp_power_wells { #define DPLL_CTRL1 0x6C058 #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) -#define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) -#define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1) -#define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) +#define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) +#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1) +#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) -#define DPLL_CRTL1_LINK_RATE_2700 0 -#define DPLL_CRTL1_LINK_RATE_1350 1 -#define DPLL_CRTL1_LINK_RATE_810 2 -#define DPLL_CRTL1_LINK_RATE_1620 3 -#define DPLL_CRTL1_LINK_RATE_1080 4 -#define DPLL_CRTL1_LINK_RATE_2160 5 +#define DPLL_CTRL1_LINK_RATE_2700 0 +#define DPLL_CTRL1_LINK_RATE_1350 1 +#define DPLL_CTRL1_LINK_RATE_810 2 +#define DPLL_CTRL1_LINK_RATE_1620 3 +#define DPLL_CTRL1_LINK_RATE_1080 4 +#define DPLL_CTRL1_LINK_RATE_2160 5 /* DPLL control2 */ #define DPLL_CTRL2 0x6C05C diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 9c1e74a3a277..d5bee8b8c15f 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -870,26 +870,26 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder, if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { link_clock = skl_calc_wrpll_link(dev_priv, dpll); } else { - link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll); - link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll); + link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); + link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); switch (link_clock) { - case DPLL_CRTL1_LINK_RATE_810: + case DPLL_CTRL1_LINK_RATE_810: link_clock = 81000; break; - case DPLL_CRTL1_LINK_RATE_1080: + case DPLL_CTRL1_LINK_RATE_1080: link_clock = 108000; break; - case DPLL_CRTL1_LINK_RATE_1350: + case DPLL_CTRL1_LINK_RATE_1350: link_clock = 135000; break; - case DPLL_CRTL1_LINK_RATE_1620: + case DPLL_CTRL1_LINK_RATE_1620: link_clock = 162000; break; - case DPLL_CRTL1_LINK_RATE_2160: + case DPLL_CTRL1_LINK_RATE_2160: link_clock = 216000; break; - case DPLL_CRTL1_LINK_RATE_2700: + case DPLL_CTRL1_LINK_RATE_2700: link_clock = 270000; break; default: @@ -1294,13 +1294,13 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc, switch (intel_dp->link_bw) { case DP_LINK_BW_1_62: - ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0); + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); break; case DP_LINK_BW_2_7: - ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0); + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); break; case DP_LINK_BW_5_4: - ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0); + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); break; } @@ -1854,7 +1854,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | - DPLL_CRTL1_LINK_RATE_MASK(dpll)); + DPLL_CTRL1_LINK_RATE_MASK(dpll)); val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); I915_WRITE(DPLL_CTRL1, val); @@ -2100,7 +2100,7 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, val = I915_READ(DPLL_CTRL1); val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | - DPLL_CRTL1_LINK_RATE_MASK(dpll)); + DPLL_CTRL1_LINK_RATE_MASK(dpll)); val |= pll->config.hw_state.ctrl1 << (dpll * 6); I915_WRITE(DPLL_CTRL1, val); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index abbca0e76ccf..8e21e2358c0a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6467,10 +6467,10 @@ static int skylake_get_display_clock_speed(struct drm_device *dev) return 540000; linkrate = (I915_READ(DPLL_CTRL1) & - DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; + DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; - if (linkrate == DPLL_CRTL1_LINK_RATE_2160 || - linkrate == DPLL_CRTL1_LINK_RATE_1080) { + if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || + linkrate == DPLL_CTRL1_LINK_RATE_1080) { /* vco 8640 */ switch (cdctl & CDCLK_FREQ_SEL_MASK) { case CDCLK_FREQ_450_432: diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7c3dbd465c78..5e978d69004c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1098,30 +1098,30 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock) ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); switch (link_clock / 2) { case 81000: - ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); break; case 135000: - ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0); break; case 270000: - ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0); break; case 162000: - ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620, + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0); break; /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which results in CDCLK change. Need to handle the change of CDCLK by disabling pipes and re-enabling them */ case 108000: - ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080, + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); break; case 216000: - ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160, + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0); break; -- cgit v1.2.3 From 9043ae020506808b3d2552eace047d3083688512 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Thu, 30 Apr 2015 16:39:18 +0100 Subject: drm/i915: Re-order the PCU opcodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let's keep that list sorted! Signed-off-by: Damien Lespiau Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8924f4b68893..20ed82fa8fb6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6644,15 +6644,15 @@ enum skl_disp_power_wells { #define GEN6_PCODE_MAILBOX 0x138124 #define GEN6_PCODE_READY (1<<31) -#define GEN6_READ_OC_PARAMS 0xc -#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 -#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 #define GEN6_PCODE_READ_RC6VIDS 0x5 +#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) +#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) +#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 +#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 +#define GEN6_READ_OC_PARAMS 0xc #define GEN6_PCODE_READ_D_COMP 0x10 #define GEN6_PCODE_WRITE_D_COMP 0x11 -#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) -#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 #define DISPLAY_IPS_CONTROL 0x19 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A -- cgit v1.2.3 From 57520bc55cf56b77e7a67cb0877fafdb65181f6a Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Thu, 30 Apr 2015 16:39:19 +0100 Subject: drm/i915: Merge the GEN9 memory latency PCU opcode with its friends MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Damien Lespiau Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 20ed82fa8fb6..ea5ca44766d0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6648,6 +6648,11 @@ enum skl_disp_power_wells { #define GEN6_PCODE_READ_RC6VIDS 0x5 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) +#define GEN9_PCODE_READ_MEM_LATENCY 0x6 +#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF +#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 +#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 +#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 #define GEN6_READ_OC_PARAMS 0xc @@ -6661,12 +6666,6 @@ enum skl_disp_power_wells { #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 #define GEN6_PCODE_DATA1 0x13812C -#define GEN9_PCODE_READ_MEM_LATENCY 0x6 -#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF -#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 -#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 -#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 - #define GEN6_GT_CORE_STATUS 0x138060 #define GEN6_CORE_CPD_STATE_MASK (7<<4) #define GEN6_RCn_MASK 7 -- cgit v1.2.3 From 6222709d60734dd1e11f8d24520d9f23b4eb953e Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Thu, 30 Apr 2015 16:39:20 +0100 Subject: drm/i915/skl: Make the Misc I/O power well part of the PLLS domain MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The specs tell us to ungate PG1 and Misc I/O at display init. We'll use the PLLS power domain to ensure those two power wells are up. Signed-off-by: Damien Lespiau Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 64968d4ec62c..bd7ad1d2d5f5 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -315,6 +315,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, BIT(POWER_DOMAIN_INIT)) #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ + BIT(POWER_DOMAIN_PLLS) | \ BIT(POWER_DOMAIN_INIT)) #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ -- cgit v1.2.3 From d3902c3eba3666f001fa82fa16109aa4ab0074dc Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 4 May 2015 17:20:49 +0300 Subject: drm/i915/audio: do not mess with audio registers if port is invalid We should no longer enter the codec enable/disable functions in question with port A anyway, but to err on the safe side, keep the warnings. Just bail out early without messing with the registers. Signed-off-by: Jani Nikula Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_audio.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index f72e93a45e11..c4312177b0ee 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -269,6 +269,9 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder) DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", port_name(port), pipe_name(pipe)); + if (WARN_ON(port == PORT_A)) + return; + if (HAS_PCH_IBX(dev_priv->dev)) { aud_config = IBX_AUD_CFG(pipe); aud_cntrl_st2 = IBX_AUD_CNTL_ST2; @@ -290,12 +293,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder) tmp |= AUD_CONFIG_N_VALUE_INDEX; I915_WRITE(aud_config, tmp); - if (WARN_ON(!port)) { - eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) | - IBX_ELD_VALID(PORT_D); - } else { - eldv = IBX_ELD_VALID(port); - } + eldv = IBX_ELD_VALID(port); /* Invalidate ELD */ tmp = I915_READ(aud_cntrl_st2); @@ -325,6 +323,9 @@ static void ilk_audio_codec_enable(struct drm_connector *connector, DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", port_name(port), pipe_name(pipe), drm_eld_size(eld)); + if (WARN_ON(port == PORT_A)) + return; + /* * FIXME: We're supposed to wait for vblank here, but we have vblanks * disabled during the mode set. The proper fix would be to push the @@ -349,12 +350,7 @@ static void ilk_audio_codec_enable(struct drm_connector *connector, aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; } - if (WARN_ON(!port)) { - eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) | - IBX_ELD_VALID(PORT_D); - } else { - eldv = IBX_ELD_VALID(port); - } + eldv = IBX_ELD_VALID(port); /* Invalidate ELD */ tmp = I915_READ(aud_cntrl_st2); -- cgit v1.2.3 From b3da4a627eb710254e09c6b8dbe94a4aa35382d2 Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Mon, 4 May 2015 17:44:11 +0300 Subject: drm/i915: Free wa_batchbuffer when freeing error state wa_batchbuffer is part of some error states. Make sure it is freed. Signed-off-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gpu_error.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index ac22614dbb0e..a3e330d2a1d8 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -554,6 +554,7 @@ static void i915_error_state_free(struct kref *error_ref) for (i = 0; i < ARRAY_SIZE(error->ring); i++) { i915_error_object_free(error->ring[i].batchbuffer); + i915_error_object_free(error->ring[i].wa_batchbuffer); i915_error_object_free(error->ring[i].ringbuffer); i915_error_object_free(error->ring[i].hws_page); i915_error_object_free(error->ring[i].ctx); -- cgit v1.2.3 From 0fb890c01349c52b55b7adb4a18b362d141303d1 Mon Sep 17 00:00:00 2001 From: Vandana Kannan Date: Tue, 5 May 2015 14:51:56 +0530 Subject: drm/i915/bxt: BLC implementation Enabling BLC on BXT. Includes register definition, and new functions for BXT. In BXT, there are 2 sets of registers for BLC. Until there is clarity about which set would be effective, set 1 is being used. This would have to be re-visited if there is any change or when 2 LFPs are enabled on BXT. This patch enables brightness change which would be effected by use of hot-keys or sysfs entry. TODO:- BLC implementation will have to re-visited when 1. there is clarity about which set of registers has to be used and when. 2. CDCLK frequency is changed v2: Jani's review comments - Modified comment in i915_reg.h - Renamed register defintions - Removed definition of duty cycle max. Not required now and its not 64-bit. v3: - Rebase on top of VLV/CHV backlight changes, in particuliar bxt_set_backlight() now has a different prototype (Damien) Reviewed-by: Jani Nikula Signed-off-by: Vandana Kannan Signed-off-by: Damien Lespiau Cc: Jani Nikula Cc: Shankar, Uma Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 12 ++++++ drivers/gpu/drm/i915/intel_panel.c | 87 +++++++++++++++++++++++++++++++++++++- 2 files changed, 98 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ea5ca44766d0..9447b27703f4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3486,6 +3486,18 @@ enum skl_disp_power_wells { #define UTIL_PIN_CTL 0x48400 #define UTIL_PIN_ENABLE (1 << 31) +/* BXT backlight register definition. */ +#define BXT_BLC_PWM_CTL1 0xC8250 +#define BXT_BLC_PWM_ENABLE (1 << 31) +#define BXT_BLC_PWM_POLARITY (1 << 29) +#define BXT_BLC_PWM_FREQ1 0xC8254 +#define BXT_BLC_PWM_DUTY1 0xC8258 + +#define BXT_BLC_PWM_CTL2 0xC8350 +#define BXT_BLC_PWM_FREQ2 0xC8354 +#define BXT_BLC_PWM_DUTY2 0xC8358 + + #define PCH_GTC_CTL 0xe7000 #define PCH_GTC_ENABLE (1 << 31) diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 08532d4ffe0a..7d83527f95f7 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -536,6 +536,14 @@ static u32 vlv_get_backlight(struct intel_connector *connector) return _vlv_get_backlight(dev, pipe); } +static u32 bxt_get_backlight(struct intel_connector *connector) +{ + struct drm_device *dev = connector->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + return I915_READ(BXT_BLC_PWM_DUTY1); +} + static u32 intel_panel_get_backlight(struct intel_connector *connector) { struct drm_device *dev = connector->base.dev; @@ -616,6 +624,14 @@ static void vlv_set_backlight(struct intel_connector *connector, u32 level) I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level); } +static void bxt_set_backlight(struct intel_connector *connector, u32 level) +{ + struct drm_device *dev = connector->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + I915_WRITE(BXT_BLC_PWM_DUTY1, level); +} + static void intel_panel_actually_set_backlight(struct intel_connector *connector, u32 level) { @@ -741,6 +757,18 @@ static void vlv_disable_backlight(struct intel_connector *connector) I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE); } +static void bxt_disable_backlight(struct intel_connector *connector) +{ + struct drm_device *dev = connector->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 tmp; + + intel_panel_actually_set_backlight(connector, 0); + + tmp = I915_READ(BXT_BLC_PWM_CTL1); + I915_WRITE(BXT_BLC_PWM_CTL1, tmp & ~BXT_BLC_PWM_ENABLE); +} + void intel_panel_disable_backlight(struct intel_connector *connector) { struct drm_device *dev = connector->base.dev; @@ -947,6 +975,33 @@ static void vlv_enable_backlight(struct intel_connector *connector) I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE); } +static void bxt_enable_backlight(struct intel_connector *connector) +{ + struct drm_device *dev = connector->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_panel *panel = &connector->panel; + u32 pwm_ctl; + + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1); + if (pwm_ctl & BXT_BLC_PWM_ENABLE) { + DRM_DEBUG_KMS("backlight already enabled\n"); + pwm_ctl &= ~BXT_BLC_PWM_ENABLE; + I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl); + } + + I915_WRITE(BXT_BLC_PWM_FREQ1, panel->backlight.max); + + intel_panel_actually_set_backlight(connector, panel->backlight.level); + + pwm_ctl = 0; + if (panel->backlight.active_low_pwm) + pwm_ctl |= BXT_BLC_PWM_POLARITY; + + I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl); + POSTING_READ(BXT_BLC_PWM_CTL1); + I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl | BXT_BLC_PWM_ENABLE); +} + void intel_panel_enable_backlight(struct intel_connector *connector) { struct drm_device *dev = connector->base.dev; @@ -1299,6 +1354,30 @@ static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe return 0; } +static int +bxt_setup_backlight(struct intel_connector *connector, enum pipe unused) +{ + struct drm_device *dev = connector->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_panel *panel = &connector->panel; + u32 pwm_ctl, val; + + pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1); + panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY; + + panel->backlight.max = I915_READ(BXT_BLC_PWM_FREQ1); + if (!panel->backlight.max) + return -ENODEV; + + val = bxt_get_backlight(connector); + panel->backlight.level = intel_panel_compute_brightness(connector, val); + + panel->backlight.enabled = (pwm_ctl & BXT_BLC_PWM_ENABLE) && + panel->backlight.level != 0; + + return 0; +} + int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe) { struct drm_device *dev = connector->dev; @@ -1350,7 +1429,13 @@ void intel_panel_init_backlight_funcs(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9)) { + if (IS_BROXTON(dev)) { + dev_priv->display.setup_backlight = bxt_setup_backlight; + dev_priv->display.enable_backlight = bxt_enable_backlight; + dev_priv->display.disable_backlight = bxt_disable_backlight; + dev_priv->display.set_backlight = bxt_set_backlight; + dev_priv->display.get_backlight = bxt_get_backlight; + } else if (IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { dev_priv->display.setup_backlight = bdw_setup_backlight; dev_priv->display.enable_backlight = bdw_enable_backlight; dev_priv->display.disable_backlight = pch_disable_backlight; -- cgit v1.2.3 From abab6311a5784a94a35beda54d4b25312cfc77f3 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:32 +0300 Subject: drm/i915: Use POSTING_READ() in intel_sdvo_write_sdvox() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use POSTING_READ() in intel_sdvo_write_sdvox() as appropriate. Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_sdvo.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 10cd33252838..0a0625761f42 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -242,7 +242,7 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) if (intel_sdvo->sdvo_reg == PCH_SDVOB) { I915_WRITE(intel_sdvo->sdvo_reg, val); - I915_READ(intel_sdvo->sdvo_reg); + POSTING_READ(intel_sdvo->sdvo_reg); return; } @@ -259,9 +259,9 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) for (i = 0; i < 2; i++) { I915_WRITE(GEN3_SDVOB, bval); - I915_READ(GEN3_SDVOB); + POSTING_READ(GEN3_SDVOB); I915_WRITE(GEN3_SDVOC, cval); - I915_READ(GEN3_SDVOC); + POSTING_READ(GEN3_SDVOC); } } -- cgit v1.2.3 From 983b4b9def913991ef829ca635f1b3e7dd391c1b Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Fri, 10 Apr 2015 13:12:25 +0100 Subject: drm/i915/bxt: Add WaDisableSbeCacheDispatchPortSharing Note that we also need this for skl. Signed-off-by: Nick Hoath Reviewed-by: Imre Deak [danvet: Note that we also need this for skl, requested by Imre.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++ 2 files changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9447b27703f4..558d3dd5a039 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6738,6 +6738,7 @@ enum skl_disp_power_wells { #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 #define GEN7_MAX_PS_THREAD_DEP (8<<12) #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) +#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4) #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) #define GEN9_HALF_SLICE_CHICKEN5 0xe188 diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 98424e29917c..b0bd9bb6676e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1050,6 +1050,13 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); + /* WaDisableSbeCacheDispatchPortSharing:bxt */ + if (INTEL_REVID(dev) <= BXT_REVID_B0) { + WA_SET_BIT_MASKED( + GEN7_HALF_SLICE_CHICKEN1, + GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); + } + return 0; } -- cgit v1.2.3 From 9e45803465417acfaaefc331d59dd7e6cf06110b Mon Sep 17 00:00:00 2001 From: Sonika Jindal Date: Wed, 6 May 2015 17:35:48 +0530 Subject: drm/i915/skl: Add module parameter to select edp vswing table This provides an option to override the value set by VBT for selecting edp Vswing Pre-emph setting table. v2: Adding comment about this being a temporary workaround and making the parameter read-only (Jani) v3: Changing mode to 0400 instead of 0 (Jani) https://bugs.freedesktop.org/show_bug.cgi?id=89554 Signed-off-by: Sonika Jindal Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 4 +++- drivers/gpu/drm/i915/i915_params.c | 8 ++++++++ drivers/gpu/drm/i915/intel_bios.c | 9 +++++++-- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_dp.c | 2 +- 5 files changed, 20 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 51baca1e085b..8136005d2c6e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1364,7 +1364,6 @@ struct intel_vbt_data { bool edp_initialized; bool edp_support; int edp_bpp; - bool edp_low_vswing; struct edp_power_seq edp_pps; struct { @@ -1846,6 +1845,8 @@ struct drm_i915_private { void (*stop_ring)(struct intel_engine_cs *ring); } gt; + bool edp_low_vswing; + /* * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch * will be rejected. Instead look for a better place. @@ -2515,6 +2516,7 @@ struct i915_params { int mmio_debug; bool verbose_state_checks; bool nuclear_pageflip; + int edp_vswing; }; extern struct i915_params i915 __read_mostly; diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index bb64415a1c3e..8ac5a1b29ac0 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -53,6 +53,7 @@ struct i915_params i915 __read_mostly = { .mmio_debug = 0, .verbose_state_checks = 1, .nuclear_pageflip = 0, + .edp_vswing = 0, }; module_param_named(modeset, i915.modeset, int, 0400); @@ -184,3 +185,10 @@ MODULE_PARM_DESC(verbose_state_checks, module_param_named_unsafe(nuclear_pageflip, i915.nuclear_pageflip, bool, 0600); MODULE_PARM_DESC(nuclear_pageflip, "Force atomic modeset functionality; only planes work for now (default: false)."); + +/* WA to get away with the default setting in VBT for early platforms.Will be removed */ +module_param_named_unsafe(edp_vswing, i915.edp_vswing, int, 0400); +MODULE_PARM_DESC(edp_vswing, + "Ignore/Override vswing pre-emph table selection from VBT " + "(0=use value from vbt [default], 1=low power swing(200mV)," + "2=default swing(400mV))"); diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index c08368c03dad..cee596d0a6a2 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -672,8 +672,13 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb) if (bdb->version >= 173) { uint8_t vswing; - vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; - dev_priv->vbt.edp_low_vswing = vswing == 0; + /* Don't read from VBT if module parameter has valid value*/ + if (i915.edp_vswing) { + dev_priv->edp_low_vswing = i915.edp_vswing == 1; + } else { + vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; + dev_priv->edp_low_vswing = vswing == 0; + } } } diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index d5bee8b8c15f..b8eabc65dc27 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -282,7 +282,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, ddi_translations_fdi = NULL; ddi_translations_dp = skl_ddi_translations_dp; n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp); - if (dev_priv->vbt.edp_low_vswing) { + if (dev_priv->edp_low_vswing) { ddi_translations_edp = skl_ddi_translations_edp; n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp); } else { diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5e978d69004c..91c8bf3cf62b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2894,7 +2894,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp) if (IS_BROXTON(dev)) return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; else if (INTEL_INFO(dev)->gen >= 9) { - if (dev_priv->vbt.edp_low_vswing && port == PORT_A) + if (dev_priv->edp_low_vswing && port == PORT_A) return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; } else if (IS_VALLEYVIEW(dev)) -- cgit v1.2.3 From 813b5e6971cbf1ae7dd0298fe44e39f7f2629f8d Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 25 Mar 2015 19:27:16 +0200 Subject: drm/i915: s/9/intel_freq_opcode(450)/ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the hardcoded 9 with a call to intel_freq_opcode(450). Signed-off-by: Ville Syrjälä Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8812fffeac5e..9e3bfff2d845 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4295,8 +4295,8 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) if (dev_priv->rps.min_freq_softlimit == 0) { if (IS_HASWELL(dev) || IS_BROADWELL(dev)) dev_priv->rps.min_freq_softlimit = - /* max(RPe, 450 MHz) */ - max(dev_priv->rps.efficient_freq, (u8) 9); + max_t(int, dev_priv->rps.efficient_freq, + intel_freq_opcode(dev_priv, 450)); else dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; -- cgit v1.2.3 From 22e02c0b4bc87c94895b1f4cb25ee705d5687cb1 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 6 May 2015 14:28:57 +0300 Subject: drm/i915: Add missing POSTING_READ()s to BXT dbuf enable sequence MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do a POSTING_READ() between the DBUF_CTL register write and the udelay() to make sure we really wait after the register write has happened. Spotted while reviewing Damien's SKL cdclk patch which had the POSTING_READ()s. Cc: Imre Deak Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8e21e2358c0a..5c2047b6127b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5482,6 +5482,8 @@ void broxton_init_cdclk(struct drm_device *dev) broxton_set_cdclk(dev, 624000); I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); + POSTING_READ(DBUF_CTL); + udelay(10); if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) @@ -5493,6 +5495,8 @@ void broxton_uninit_cdclk(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); + POSTING_READ(DBUF_CTL); + udelay(10); if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) -- cgit v1.2.3 From f1d3d34d1740e13f01411d85f53945596488d4c1 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Wed, 6 May 2015 14:36:27 +0100 Subject: drm/i915/skl: Fix WaDisableChickenBitTSGBarrierAckForFFSliceCS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops. Ville noticed that the write was wrong since FF_SLICE_CS_CHICKEN2 is a masked register. Re-oops. A wonder if went through 2 people while having roughly a bug per line... The problem was introduced in the original patch: commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c Author: Damien Lespiau Date: Mon Feb 9 19:33:20 2015 +0000 drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS v2: Also fix the register write (Ville) Reported-by: Robert Beckett Reported-by: Ville Syrjälä Cc: Robert Beckett Cc: Ville Syrjälä Cc: Nick Hoath Signed-off-by: Damien Lespiau Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 558d3dd5a039..60ef5406fe57 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5718,7 +5718,7 @@ enum skl_disp_power_wells { #define HSW_NDE_RSTWRN_OPT 0x46408 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) -#define FF_SLICE_CS_CHICKEN2 0x02e4 +#define FF_SLICE_CS_CHICKEN2 0x20e4 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) /* GEN7 chicken */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9e3bfff2d845..7006f94b94c1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -88,8 +88,7 @@ static void skl_init_clock_gating(struct drm_device *dev) /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ I915_WRITE(FF_SLICE_CS_CHICKEN2, - I915_READ(FF_SLICE_CS_CHICKEN2) | - GEN9_TSG_BARRIER_ACK_DISABLE); + _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); } if (INTEL_REVID(dev) <= SKL_REVID_E0) -- cgit v1.2.3 From 83a24979c40ebbf0fa0cd14df16f74142f373cd3 Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Fri, 10 Apr 2015 13:12:26 +0100 Subject: drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent Note that we also need this for skl. Signed-off-by: Nick Hoath Reviewed-by: Imre Deak [danvet: Note that we also need this for skl, requested by Imre.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index b0bd9bb6676e..7ef9a29405cd 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1057,6 +1057,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); } + /* WaForceContextSaveRestoreNonCoherent:bxt */ + WA_SET_BIT_MASKED(HDC_CHICKEN0, + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); + return 0; } -- cgit v1.2.3 From 6ba2bd3da7d3f9af3db83f704ca055943fd9ee40 Mon Sep 17 00:00:00 2001 From: Todd Previte Date: Tue, 21 Apr 2015 11:09:41 -0700 Subject: drm: Add edid_corrupt flag for Displayport Link CTS 4.2.2.6 Displayport compliance test 4.2.2.6 requires that a source device be capable of detecting a corrupt EDID. The test specification states that the sink device sets up the EDID with an invalid checksum. To do this, the sink sets up an invalid EDID header, expecting the source device to generate the checksum and compare it to the value stored in the last byte of the block data. Unfortunately, the DRM EDID reading and parsing functions are actually too good in this case; the header is fixed before the checksum is computed and thus the test never sees the invalid checksum. This results in a failure to pass the compliance test. To correct this issue, when the EDID code detects that the header is invalid, a flag is set to indicate that the EDID is corrupted. In this case, it sets edid_corrupt flag and continues with its fix-up code. This flag is also set in the case of a more seriously damaged header (fixup score less than the threshold). For consistency, the edid_corrupt flag is also set when the checksum is invalid as well. V2: - Removed the static bool global - Added a bool to the drm_connector struct to reaplce the static one for holding the status of raw edid header corruption detection - Modified the function signature of the is_valid function to take an additional parameter to store the corruption detected value - Fixed the other callers of the above is_valid function V3: - Updated the commit message to be more clear about what and why this patch does what it does. - Added comment in code to clarify the operations there - Removed compliance variable and check_link_status update; those have been moved to a later patch - Removed variable assignment from the bottom of the test handler V4: - Removed i915 tag from subject line as the patch is not i915-specific V5: - Moved code causing a compilation error to this patch where the variable is actually declared - Maintained blank lines / spacing so as to not contaminate the patch V6: - Removed extra debug messages - Added documentation to for the added parameter on drm_edid_block_valid - Fixed more whitespace issues in check_link_status - Added a clear of the header_corrupt flag to the end of the test handler in intel_dp.c - Changed the usage of the new function prototype in several places to use NULL where it is not needed by compliance testing V7: - Updated to account for long_pulse flag propagation V8: - Removed clearing of header_corrupt flag from the test handler in intel_dp.c - Added clearing of header_corrupt flag in the drm_edid_block_valid function V9: - Renamed header_corrupt flag to edid_corrupt to more accurately reflect its value and purpose - Updated commit message V10: - Updated for versioning and patch swizzle - Revised the title to more accurately reflect the nature and contents of the patch - Fixed formatting/whitespace problems - Added set flag when computed checksum is invalid Signed-off-by: Todd Previte Cc: dri-devel@lists.freedesktop.org Acked-by: Dave Airlie Reviewed-by: Alex Deucher Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_edid.c | 32 ++++++++++++++++++++++++++------ drivers/gpu/drm/drm_edid_load.c | 7 +++++-- include/drm/drm_crtc.h | 8 +++++++- 3 files changed, 38 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 53bc7a628909..be6713c2fc9d 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1041,13 +1041,15 @@ static bool drm_edid_is_zero(const u8 *in_edid, int length) * @raw_edid: pointer to raw EDID block * @block: type of block to validate (0 for base, extension otherwise) * @print_bad_edid: if true, dump bad EDID blocks to the console + * @edid_corrupt: if true, the header or checksum is invalid * * Validate a base or extension EDID block and optionally dump bad blocks to * the console. * * Return: True if the block is valid, false otherwise. */ -bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) +bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, + bool *edid_corrupt) { u8 csum; struct edid *edid = (struct edid *)raw_edid; @@ -1060,11 +1062,22 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) if (block == 0) { int score = drm_edid_header_is_valid(raw_edid); - if (score == 8) ; - else if (score >= edid_fixup) { + if (score == 8) { + if (edid_corrupt) + *edid_corrupt = 0; + } else if (score >= edid_fixup) { + /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 + * The corrupt flag needs to be set here otherwise, the + * fix-up code here will correct the problem, the + * checksum is correct and the test fails + */ + if (edid_corrupt) + *edid_corrupt = 1; DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); memcpy(raw_edid, edid_header, sizeof(edid_header)); } else { + if (edid_corrupt) + *edid_corrupt = 1; goto bad; } } @@ -1075,6 +1088,9 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); } + if (edid_corrupt) + *edid_corrupt = 1; + /* allow CEA to slide through, switches mangle this */ if (raw_edid[0] != 0x02) goto bad; @@ -1129,7 +1145,7 @@ bool drm_edid_is_valid(struct edid *edid) return false; for (i = 0; i <= edid->extensions; i++) - if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true)) + if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) return false; return true; @@ -1232,7 +1248,8 @@ struct edid *drm_do_get_edid(struct drm_connector *connector, for (i = 0; i < 4; i++) { if (get_edid_block(data, block, 0, EDID_LENGTH)) goto out; - if (drm_edid_block_valid(block, 0, print_bad_edid)) + if (drm_edid_block_valid(block, 0, print_bad_edid, + &connector->edid_corrupt)) break; if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { connector->null_edid_counter++; @@ -1257,7 +1274,10 @@ struct edid *drm_do_get_edid(struct drm_connector *connector, block + (valid_extensions + 1) * EDID_LENGTH, j, EDID_LENGTH)) goto out; - if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) { + if (drm_edid_block_valid(block + (valid_extensions + 1) + * EDID_LENGTH, j, + print_bad_edid, + NULL)) { valid_extensions++; break; } diff --git a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c index 4c0aa97aaf03..c5605fe4907e 100644 --- a/drivers/gpu/drm/drm_edid_load.c +++ b/drivers/gpu/drm/drm_edid_load.c @@ -216,7 +216,8 @@ static void *edid_load(struct drm_connector *connector, const char *name, goto out; } - if (!drm_edid_block_valid(edid, 0, print_bad_edid)) { + if (!drm_edid_block_valid(edid, 0, print_bad_edid, + &connector->edid_corrupt)) { connector->bad_edid_counter++; DRM_ERROR("Base block of EDID firmware \"%s\" is invalid ", name); @@ -229,7 +230,9 @@ static void *edid_load(struct drm_connector *connector, const char *name, if (i != valid_extensions + 1) memcpy(edid + (valid_extensions + 1) * EDID_LENGTH, edid + i * EDID_LENGTH, EDID_LENGTH); - if (drm_edid_block_valid(edid + i * EDID_LENGTH, i, print_bad_edid)) + if (drm_edid_block_valid(edid + i * EDID_LENGTH, i, + print_bad_edid, + NULL)) valid_extensions++; } diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index db9a30f10bc4..b9fcdc824997 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -719,6 +719,11 @@ struct drm_connector { int null_edid_counter; /* needed to workaround some HW bugs where we get all 0s */ unsigned bad_edid_counter; + /* Flag for raw EDID header corruption - used in Displayport + * compliance testing - * Displayport Link CTS Core 1.2 rev1.1 4.2.2.6 + */ + bool edid_corrupt; + struct dentry *debugfs_entry; struct drm_connector_state *state; @@ -1443,7 +1448,8 @@ extern void drm_set_preferred_mode(struct drm_connector *connector, int hpref, int vpref); extern int drm_edid_header_is_valid(const u8 *raw_edid); -extern bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid); +extern bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, + bool *edid_corrupt); extern bool drm_edid_is_valid(struct edid *edid); extern struct drm_tile_group *drm_mode_create_tile_group(struct drm_device *dev, -- cgit v1.2.3 From 559be30cb74d6a9f3345f78a0cf3a02a564d8eef Mon Sep 17 00:00:00 2001 From: Todd Previte Date: Mon, 4 May 2015 07:48:20 -0700 Subject: drm/i915: Implement the intel_dp_autotest_edid function for DP EDID complaince tests Updates the EDID compliance test function to perform the analyze and react to the EDID data read as a result of a hot plug event. The results of this analysis are handed off to userspace so that the userspace app can set the display mode appropriately for the test result/response. The compliance_test_active flag now appears at the end of the individual test handling functions. This is so that the kernel-side operations can be completed without the risk of interruption from the userspace app that is polling on that flag. V2: - Addressed mailing list feedback - Removed excess debug messages - Removed extraneous comments - Fixed formatting issues (line length > 80) - Updated the debug message in compute_edid_checksum to output hex values instead of decimal V3: - Addressed more list feedback - Added the test_active flag to the autotest function - Removed test_active flag from handler - Added failsafe check on the compliance test active flag at the end of the test handler - Fixed checkpatch.pl issues V4: - Removed the checksum computation function and its use as it has been rendered superfluous by changes to the core DRM EDID functions - Updated to use the raw header corruption detection mechanism - Moved the declaration of the test_data variable here V5: - Update test active flag variable name to match the change in the first patch of the series. - Relocated the test active flag declaration and initialization to this patch V6: - Updated to use the new flag for raw EDID header corruption - Removed the extra EDID read from the autotest function - Added the edid_checksum variable to struct intel_dp so that the autotest function can write it to the sink device - Moved the update to the hpd_pulse function to another patch - Removed extraneous constants V7: - Fixed erroneous placement of the checksum assignment. In some cases such as when the EDID read fails and is NULL, this causes a NULL ptr dereference in the kernel. Bad news. Fixed now. V8: - Updated to support the kfree() on the EDID data added previously V9: - Updated for the long_hpd flag propagation V10: - Updated to use actual checksum from the EDID read that occurs during normal hot plug path execution - Removed variables from intel_dp struct that are no longer needed - Updated the patch subject to more closely match the nature and contents of the patch - Fixed formatting problem (long line) V11: - Removed extra debug messages - Updated comments to be more informative - Removed extra variable V12: - Removed the 4 bit offset of the resolution setting in compliance data - Changed to DRM_DEBUG_KMS instead of DRM_DEBUG_DRIVER Signed-off-by: Todd Previte Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 42 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ 2 files changed, 44 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 91c8bf3cf62b..d0a88602efab 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -41,6 +41,12 @@ #define DP_LINK_CHECK_TIMEOUT (10 * 1000) +/* Compliance test status bits */ +#define INTEL_DP_RESOLUTION_SHIFT_MASK 0 +#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) +#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) +#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) + struct dp_link_dpll { int link_bw; struct dpll dpll; @@ -4079,6 +4085,39 @@ static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) { uint8_t test_result = DP_TEST_NAK; + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; + + if (intel_connector->detect_edid == NULL || + connector->edid_corrupt == 1 || + intel_dp->aux.i2c_defer_count > 6) { + /* Check EDID read for NACKs, DEFERs and corruption + * (DP CTS 1.2 Core r1.1) + * 4.2.2.4 : Failed EDID read, I2C_NAK + * 4.2.2.5 : Failed EDID read, I2C_DEFER + * 4.2.2.6 : EDID corruption detected + * Use failsafe mode for all cases + */ + if (intel_dp->aux.i2c_nack_count > 0 || + intel_dp->aux.i2c_defer_count > 0) + DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", + intel_dp->aux.i2c_nack_count, + intel_dp->aux.i2c_defer_count); + intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; + } else { + if (!drm_dp_dpcd_write(&intel_dp->aux, + DP_TEST_EDID_CHECKSUM, + &intel_connector->detect_edid->checksum, + 1)); + DRM_DEBUG_KMS("Failed to write EDID checksum\n"); + + test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; + intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; + } + + /* Set test active flag here so userspace doesn't interrupt things */ + intel_dp->compliance_test_active = 1; + return test_result; } @@ -4094,7 +4133,10 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) uint8_t rxdata = 0; int status = 0; + intel_dp->compliance_test_active = 0; intel_dp->compliance_test_type = 0; + intel_dp->compliance_test_data = 0; + intel_dp->aux.i2c_nack_count = 0; intel_dp->aux.i2c_defer_count = 0; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index cf701ed26478..da553af78a65 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -740,6 +740,8 @@ struct intel_dp { /* Displayport compliance testing */ unsigned long compliance_test_type; + unsigned long compliance_test_data; + bool compliance_test_active; }; struct intel_digital_port { -- cgit v1.2.3 From eb3394faeb97d981fae1fab50fd0b49997643d10 Mon Sep 17 00:00:00 2001 From: Todd Previte Date: Sat, 18 Apr 2015 00:04:19 -0700 Subject: drm/i915: Add debugfs test control files for Displayport compliance testing This patch adds 3 debugfs files for handling Displayport compliance testing and supercedes the previous patches that implemented debugfs support for compliance testing. Those patches were: - [PATCH 04/17] drm/i915: Add debugfs functions for Displayport compliance testing - [PATCH 08/17] drm/i915: Add new debugfs file for Displayport compliance test control - [PATCH 09/17] drm/i915: Add debugfs write and test param parsing functions for DP test control This new patch simplifies the debugfs implementation by places a single test control value into an individual file. Each file is readable by the usersapce application and the test_active file is writable to indicate to the kernel when userspace has completed its portion of the test sequence. Replacing the previous files simplifies operation and speeds response time for the user app, as it is required to poll on the test_active file in order to determine when it needs to begin its operations. V2: - Updated the test active variable name to match the change in the initial patch of the series V3: - Added a fix in the test_active_write function to prevent a NULL pointer dereference if the encoder on the connector is invalid Signed-off-by: Todd Previte Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 209 ++++++++++++++++++++++++++++++++++++ 1 file changed, 209 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9e5a56cff2f3..1afbce2c591e 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3951,6 +3951,212 @@ static const struct file_operations i915_display_crc_ctl_fops = { .write = display_crc_ctl_write }; +static ssize_t i915_displayport_test_active_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + char *input_buffer; + int status = 0; + struct seq_file *m; + struct drm_device *dev; + struct drm_connector *connector; + struct list_head *connector_list; + struct intel_dp *intel_dp; + int val = 0; + + m = file->private_data; + if (!m) { + status = -ENODEV; + return status; + } + dev = m->private; + + if (!dev) { + status = -ENODEV; + return status; + } + connector_list = &dev->mode_config.connector_list; + + if (len == 0) + return 0; + + input_buffer = kmalloc(len + 1, GFP_KERNEL); + if (!input_buffer) + return -ENOMEM; + + if (copy_from_user(input_buffer, ubuf, len)) { + status = -EFAULT; + goto out; + } + + input_buffer[len] = '\0'; + DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); + + list_for_each_entry(connector, connector_list, head) { + + if (connector->connector_type != + DRM_MODE_CONNECTOR_DisplayPort) + continue; + + if (connector->connector_type == + DRM_MODE_CONNECTOR_DisplayPort && + connector->status == connector_status_connected && + connector->encoder != NULL) { + intel_dp = enc_to_intel_dp(connector->encoder); + status = kstrtoint(input_buffer, 10, &val); + if (status < 0) + goto out; + DRM_DEBUG_DRIVER("Got %d for test active\n", val); + /* To prevent erroneous activation of the compliance + * testing code, only accept an actual value of 1 here + */ + if (val == 1) + intel_dp->compliance_test_active = 1; + else + intel_dp->compliance_test_active = 0; + } + } +out: + kfree(input_buffer); + if (status < 0) + return status; + + *offp += len; + return len; +} + +static int i915_displayport_test_active_show(struct seq_file *m, void *data) +{ + struct drm_device *dev = m->private; + struct drm_connector *connector; + struct list_head *connector_list = &dev->mode_config.connector_list; + struct intel_dp *intel_dp; + + if (!dev) + return -ENODEV; + + list_for_each_entry(connector, connector_list, head) { + + if (connector->connector_type != + DRM_MODE_CONNECTOR_DisplayPort) + continue; + + if (connector->status == connector_status_connected && + connector->encoder != NULL) { + intel_dp = enc_to_intel_dp(connector->encoder); + if (intel_dp->compliance_test_active) + seq_puts(m, "1"); + else + seq_puts(m, "0"); + } else + seq_puts(m, "0"); + } + + return 0; +} + +static int i915_displayport_test_active_open(struct inode *inode, + struct file *file) +{ + struct drm_device *dev = inode->i_private; + + return single_open(file, i915_displayport_test_active_show, dev); +} + +static const struct file_operations i915_displayport_test_active_fops = { + .owner = THIS_MODULE, + .open = i915_displayport_test_active_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = i915_displayport_test_active_write +}; + +static int i915_displayport_test_data_show(struct seq_file *m, void *data) +{ + struct drm_device *dev = m->private; + struct drm_connector *connector; + struct list_head *connector_list = &dev->mode_config.connector_list; + struct intel_dp *intel_dp; + + if (!dev) + return -ENODEV; + + list_for_each_entry(connector, connector_list, head) { + + if (connector->connector_type != + DRM_MODE_CONNECTOR_DisplayPort) + continue; + + if (connector->status == connector_status_connected && + connector->encoder != NULL) { + intel_dp = enc_to_intel_dp(connector->encoder); + seq_printf(m, "%lx", intel_dp->compliance_test_data); + } else + seq_puts(m, "0"); + } + + return 0; +} +static int i915_displayport_test_data_open(struct inode *inode, + struct file *file) +{ + struct drm_device *dev = inode->i_private; + + return single_open(file, i915_displayport_test_data_show, dev); +} + +static const struct file_operations i915_displayport_test_data_fops = { + .owner = THIS_MODULE, + .open = i915_displayport_test_data_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release +}; + +static int i915_displayport_test_type_show(struct seq_file *m, void *data) +{ + struct drm_device *dev = m->private; + struct drm_connector *connector; + struct list_head *connector_list = &dev->mode_config.connector_list; + struct intel_dp *intel_dp; + + if (!dev) + return -ENODEV; + + list_for_each_entry(connector, connector_list, head) { + + if (connector->connector_type != + DRM_MODE_CONNECTOR_DisplayPort) + continue; + + if (connector->status == connector_status_connected && + connector->encoder != NULL) { + intel_dp = enc_to_intel_dp(connector->encoder); + seq_printf(m, "%02lx", intel_dp->compliance_test_type); + } else + seq_puts(m, "0"); + } + + return 0; +} + +static int i915_displayport_test_type_open(struct inode *inode, + struct file *file) +{ + struct drm_device *dev = inode->i_private; + + return single_open(file, i915_displayport_test_type_show, dev); +} + +static const struct file_operations i915_displayport_test_type_fops = { + .owner = THIS_MODULE, + .open = i915_displayport_test_type_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release +}; + static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) { struct drm_device *dev = m->private; @@ -4846,6 +5052,9 @@ static const struct i915_debugfs_files { {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, {"i915_fbc_false_color", &i915_fbc_fc_fops}, + {"i915_dp_test_data", &i915_displayport_test_data_fops}, + {"i915_dp_test_type", &i915_displayport_test_type_fops}, + {"i915_dp_test_active", &i915_displayport_test_active_fops} }; void intel_display_crc_init(struct drm_device *dev) -- cgit v1.2.3 From ecce87ea3ab55ad0dc64460e6422c357d158a55e Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 21 Apr 2015 17:12:50 +0300 Subject: drm/i915: Remove implicitly disabling primary plane for now Some of the flags that were used are still useful when transitioning to atomic, so keep those around for now. This removes some of the complications of crtc->primary_enabled, making it easier to remove. Signed-off-by: Maarten Lankhorst Reviewed-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_drv.h | 6 ----- drivers/gpu/drm/i915/intel_sprite.c | 45 +------------------------------------ 2 files changed, 1 insertion(+), 50 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index da553af78a65..ade8384a52b4 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -248,12 +248,6 @@ struct intel_plane_state { struct drm_rect clip; bool visible; - /* - * used only for sprite planes to determine when to implicitly - * enable/disable the primary plane - */ - bool hides_primary; - /* * scaler_id * = -1 : not using a scaler diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 856395bbcc4e..be5527245bfc 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -166,17 +166,6 @@ void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) pipe_name(pipe), start_vbl_count, end_vbl_count); } -static void intel_update_primary_plane(struct intel_crtc *crtc) -{ - struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; - int reg = DSPCNTR(crtc->plane); - - if (crtc->primary_enabled) - I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); - else - I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); -} - static void skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, struct drm_framebuffer *fb, @@ -438,8 +427,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; } - intel_update_primary_plane(intel_crtc); - if (key->flags) { I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); @@ -480,8 +467,6 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) int pipe = intel_plane->pipe; int plane = intel_plane->plane; - intel_update_primary_plane(intel_crtc); - I915_WRITE(SPCNTR(pipe, plane), 0); /* Activate double buffered register update */ @@ -585,8 +570,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, } } - intel_update_primary_plane(intel_crtc); - if (key->flags) { I915_WRITE(SPRKEYVAL(pipe), key->min_value); I915_WRITE(SPRKEYMAX(pipe), key->max_value); @@ -629,8 +612,6 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_plane->pipe; - intel_update_primary_plane(intel_crtc); - I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); /* Can't leave the scaler enabled... */ if (intel_plane->can_scale) @@ -725,8 +706,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; } - intel_update_primary_plane(intel_crtc); - if (key->flags) { I915_WRITE(DVSKEYVAL(pipe), key->min_value); I915_WRITE(DVSKEYMAX(pipe), key->max_value); @@ -764,8 +743,6 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_plane->pipe; - intel_update_primary_plane(intel_crtc); - I915_WRITE(DVSCNTR(pipe), 0); /* Disable the scaler */ I915_WRITE(DVSSCALE(pipe), 0); @@ -818,7 +795,7 @@ intel_post_enable_primary(struct drm_crtc *crtc) * @crtc: the CRTC whose primary plane is to be disabled * * Performs potentially sleeping operations that must be done before the - * primary plane is enabled, such as updating FBC and IPS. Note that this may + * primary plane is disabled, such as updating FBC and IPS. Note that this may * be called due to an explicit primary plane update, or due to an implicit * disable that is caused when a sprite plane completely hides the primary * plane. @@ -844,11 +821,6 @@ intel_pre_disable_primary(struct drm_crtc *crtc) hsw_disable_ips(intel_crtc); } -static bool colorkey_enabled(struct intel_plane *intel_plane) -{ - return intel_plane->ckey.flags != I915_SET_COLORKEY_NONE; -} - static int intel_check_sprite_plane(struct drm_plane *plane, struct intel_plane_state *state) @@ -1022,23 +994,10 @@ finish: * If the sprite is completely covering the primary plane, * we can disable the primary and save power. */ - state->hides_primary = fb != NULL && drm_rect_equals(dst, clip) && - !colorkey_enabled(intel_plane); - WARN_ON(state->hides_primary && !state->visible && intel_crtc->active); - if (intel_crtc->active) { - if (intel_crtc->primary_enabled == state->hides_primary) - intel_crtc->atomic.wait_for_flips = true; - - if (intel_crtc->primary_enabled && state->hides_primary) - intel_crtc->atomic.pre_disable_primary = true; - intel_crtc->atomic.fb_bits |= INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe); - if (!intel_crtc->primary_enabled && !state->hides_primary) - intel_crtc->atomic.post_enable_primary = true; - if (intel_wm_need_update(plane, &state->base)) intel_crtc->atomic.update_wm = true; @@ -1081,8 +1040,6 @@ intel_commit_sprite_plane(struct drm_plane *plane, plane->fb = fb; if (intel_crtc->active) { - intel_crtc->primary_enabled = !state->hides_primary; - if (state->visible) { crtc_x = state->dst.x1; crtc_y = state->dst.y1; -- cgit v1.2.3 From a8ad0d8e179945a7c714fce834207e39d2957d9f Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 21 Apr 2015 17:12:51 +0300 Subject: drm/i915: Add a way to disable planes without updating state This is used by the next commit to disable all planes on a crtc without caring what type it is. Signed-off-by: Maarten Lankhorst Reviewed-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 38 +++++++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_sprite.c | 16 +++++++-------- 3 files changed, 44 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5c2047b6127b..7c0beef7f3ef 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2694,7 +2694,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, u32 reg = DSPCNTR(plane); int pixel_size; - if (!intel_crtc->primary_enabled) { + if (!intel_crtc->primary_enabled || !fb) { I915_WRITE(reg, 0); if (INTEL_INFO(dev)->gen >= 4) I915_WRITE(DSPSURF(plane), 0); @@ -2823,7 +2823,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, u32 reg = DSPCNTR(plane); int pixel_size; - if (!intel_crtc->primary_enabled) { + if (!intel_crtc->primary_enabled || !fb) { I915_WRITE(reg, 0); I915_WRITE(DSPSURF(plane), 0); POSTING_READ(reg); @@ -3102,7 +3102,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, plane = crtc->primary; plane_state = to_intel_plane_state(plane->state); - if (!intel_crtc->primary_enabled) { + if (!intel_crtc->primary_enabled || !fb) { I915_WRITE(PLANE_CTL(pipe, 0), 0); I915_WRITE(PLANE_SURF(pipe, 0), 0); POSTING_READ(PLANE_CTL(pipe, 0)); @@ -13378,6 +13378,20 @@ intel_commit_primary_plane(struct drm_plane *plane, } } +static void +intel_disable_primary_plane(struct drm_plane *plane, + struct drm_crtc *crtc, + bool force) +{ + struct drm_device *dev = plane->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!force) + to_intel_crtc(crtc)->primary_enabled = false; + + dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); +} + static void intel_begin_crtc_commit(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; @@ -13522,6 +13536,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, primary->plane = pipe; primary->check_plane = intel_check_primary_plane; primary->commit_plane = intel_commit_primary_plane; + primary->disable_plane = intel_disable_primary_plane; primary->ckey.flags = I915_SET_COLORKEY_NONE; if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) primary->plane = !pipe; @@ -13626,6 +13641,22 @@ finish: return ret; } +static void +intel_disable_cursor_plane(struct drm_plane *plane, + struct drm_crtc *crtc, + bool force) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + + if (!force) { + plane->fb = NULL; + intel_crtc->cursor_bo = NULL; + intel_crtc->cursor_addr = 0; + } + + intel_crtc_update_cursor(crtc, false); +} + static void intel_commit_cursor_plane(struct drm_plane *plane, struct intel_plane_state *state) @@ -13685,6 +13716,7 @@ static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, state->scaler_id = -1; cursor->check_plane = intel_check_cursor_plane; cursor->commit_plane = intel_commit_cursor_plane; + cursor->disable_plane = intel_disable_cursor_plane; drm_universal_plane_init(dev, &cursor->base, 0, &intel_plane_funcs, diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ade8384a52b4..9d69d7cfd17a 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -594,7 +594,7 @@ struct intel_plane { uint32_t x, uint32_t y, uint32_t src_w, uint32_t src_h); void (*disable_plane)(struct drm_plane *plane, - struct drm_crtc *crtc); + struct drm_crtc *crtc, bool force); int (*check_plane)(struct drm_plane *plane, struct intel_plane_state *state); void (*commit_plane)(struct drm_plane *plane, diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index be5527245bfc..95602da15984 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -272,11 +272,11 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, } static void -skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc) +skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force) { - struct drm_device *dev = drm_plane->dev; + struct drm_device *dev = dplane->dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_plane *intel_plane = to_intel_plane(drm_plane); + struct intel_plane *intel_plane = to_intel_plane(dplane); const int pipe = intel_plane->pipe; const int plane = intel_plane->plane + 1; @@ -286,7 +286,7 @@ skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc) I915_WRITE(PLANE_SURF(pipe, plane), 0); POSTING_READ(PLANE_SURF(pipe, plane)); - intel_update_sprite_watermarks(drm_plane, crtc, 0, 0, 0, false, false); + intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); } static void @@ -458,7 +458,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, } static void -vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) +vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force) { struct drm_device *dev = dplane->dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -604,7 +604,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, } static void -ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) +ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force) { struct drm_device *dev = plane->dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -735,7 +735,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, } static void -ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) +ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force) { struct drm_device *dev = plane->dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -1053,7 +1053,7 @@ intel_commit_sprite_plane(struct drm_plane *plane, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h); } else { - intel_plane->disable_plane(plane, crtc); + intel_plane->disable_plane(plane, crtc, false); } } } -- cgit v1.2.3 From 27321ae88c70104df1ade701e079932b54360885 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 21 Apr 2015 17:12:52 +0300 Subject: drm/i915: Use the disable callback for disabling planes. This allows disabling all planes affecting a crtc without caring what type it is. Signed-off-by: Maarten Lankhorst Reviewed-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 5 ++ drivers/gpu/drm/i915/intel_display.c | 91 ++++++------------------------------ 2 files changed, 20 insertions(+), 76 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 8136005d2c6e..87fe4f7d5ce5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -238,6 +238,11 @@ enum hpd_pin { #define for_each_crtc(dev, crtc) \ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) +#define for_each_intel_plane(dev, intel_plane) \ + list_for_each_entry(intel_plane, \ + &dev->mode_config.plane_list, \ + base.head) + #define for_each_intel_crtc(dev, intel_crtc) \ list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7c0beef7f3ef..a08cb14f076c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2254,32 +2254,6 @@ static void intel_enable_primary_hw_plane(struct drm_plane *plane, intel_wait_for_vblank(dev, intel_crtc->pipe); } -/** - * intel_disable_primary_hw_plane - disable the primary hardware plane - * @plane: plane to be disabled - * @crtc: crtc for the plane - * - * Disable @plane on @crtc, making sure that the pipe is running first. - */ -static void intel_disable_primary_hw_plane(struct drm_plane *plane, - struct drm_crtc *crtc) -{ - struct drm_device *dev = plane->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - - if (WARN_ON(!intel_crtc->active)) - return; - - if (!intel_crtc->primary_enabled) - return; - - intel_crtc->primary_enabled = false; - - dev_priv->display.update_primary_plane(crtc, plane->fb, - crtc->x, crtc->y); -} - static bool need_vtd_wa(struct drm_device *dev) { #ifdef CONFIG_INTEL_IOMMU @@ -4645,38 +4619,6 @@ static void intel_enable_sprite_planes(struct drm_crtc *crtc) } } -/* - * Disable a plane internally without actually modifying the plane's state. - * This will allow us to easily restore the plane later by just reprogramming - * its state. - */ -static void disable_plane_internal(struct drm_plane *plane) -{ - struct intel_plane *intel_plane = to_intel_plane(plane); - struct drm_plane_state *state = - plane->funcs->atomic_duplicate_state(plane); - struct intel_plane_state *intel_state = to_intel_plane_state(state); - - intel_state->visible = false; - intel_plane->commit_plane(plane, intel_state); - - intel_plane_destroy_state(plane, state); -} - -static void intel_disable_sprite_planes(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - enum pipe pipe = to_intel_crtc(crtc)->pipe; - struct drm_plane *plane; - struct intel_plane *intel_plane; - - drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { - intel_plane = to_intel_plane(plane); - if (plane->fb && intel_plane->pipe == pipe) - disable_plane_internal(plane); - } -} - void hsw_enable_ips(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; @@ -4830,6 +4772,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc) struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_plane *intel_plane; int pipe = intel_crtc->pipe; intel_crtc_wait_for_pending_flips(crtc); @@ -4840,9 +4783,15 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc) hsw_disable_ips(intel_crtc); intel_crtc_dpms_overlay(intel_crtc, false); - intel_crtc_update_cursor(crtc, false); - intel_disable_sprite_planes(crtc); - intel_disable_primary_hw_plane(crtc->primary, crtc); + intel_crtc->primary_enabled = false; + for_each_intel_plane(dev, intel_plane) { + if (intel_plane->pipe == pipe) { + struct drm_crtc *from = intel_plane->base.crtc; + + intel_plane->disable_plane(&intel_plane->base, + from ?: crtc, true); + } + } /* * FIXME: Once we grow proper nuclear flip support out of this we need @@ -13357,24 +13306,14 @@ intel_commit_primary_plane(struct drm_plane *plane, crtc->y = src->y1 >> 16; if (intel_crtc->active) { - if (state->visible) { + intel_crtc->primary_enabled = state->visible; + + if (state->visible) /* FIXME: kill this fastboot hack */ intel_update_pipe_size(intel_crtc); - intel_crtc->primary_enabled = true; - - dev_priv->display.update_primary_plane(crtc, plane->fb, - crtc->x, crtc->y); - } else { - /* - * If clipping results in a non-visible primary plane, - * we'll disable the primary plane. Note that this is - * a bit different than what happens if userspace - * explicitly disables the plane by passing fb=0 - * because plane->fb still gets set and pinned. - */ - intel_disable_primary_hw_plane(plane, crtc); - } + dev_priv->display.update_primary_plane(crtc, plane->fb, + crtc->x, crtc->y); } } -- cgit v1.2.3 From b70709a6f0e9176c2bc7ecf44acf015c7362ddc6 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 21 Apr 2015 17:12:53 +0300 Subject: drm/i915: get rid of primary_enabled and use atomic state This was an optimization from way back before we had primary plane support to be able to disable the primary plane. But with primary plane support userspace can tell the kernel this directly, so there's no big need for this any more. And it's getting in the way of the atomic conversion. If need be we can resurrect this later on properly again. Signed-off-by: Maarten Lankhorst Reviewed-by: Ander Conselvan de Oliveira [danvet: Explain why removing this is ok.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 50 ++++++++++++++++++++---------------- drivers/gpu/drm/i915/intel_drv.h | 1 - drivers/gpu/drm/i915/intel_fbc.c | 2 +- 3 files changed, 29 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a08cb14f076c..a912934e65a2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2236,11 +2236,7 @@ static void intel_enable_primary_hw_plane(struct drm_plane *plane, /* If the pipe isn't enabled, we can't pump pixels and may hang */ assert_pipe_enabled(dev_priv, intel_crtc->pipe); - - if (intel_crtc->primary_enabled) - return; - - intel_crtc->primary_enabled = true; + to_intel_plane_state(plane->state)->visible = true; dev_priv->display.update_primary_plane(crtc, plane->fb, crtc->x, crtc->y); @@ -2661,6 +2657,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct drm_plane *primary = crtc->primary; + bool visible = to_intel_plane_state(primary->state)->visible; struct drm_i915_gem_object *obj; int plane = intel_crtc->plane; unsigned long linear_offset; @@ -2668,7 +2666,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, u32 reg = DSPCNTR(plane); int pixel_size; - if (!intel_crtc->primary_enabled || !fb) { + if (!visible || !fb) { I915_WRITE(reg, 0); if (INTEL_INFO(dev)->gen >= 4) I915_WRITE(DSPSURF(plane), 0); @@ -2790,6 +2788,8 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct drm_plane *primary = crtc->primary; + bool visible = to_intel_plane_state(primary->state)->visible; struct drm_i915_gem_object *obj; int plane = intel_crtc->plane; unsigned long linear_offset; @@ -2797,7 +2797,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, u32 reg = DSPCNTR(plane); int pixel_size; - if (!intel_crtc->primary_enabled || !fb) { + if (!visible || !fb) { I915_WRITE(reg, 0); I915_WRITE(DSPSURF(plane), 0); POSTING_READ(reg); @@ -3059,6 +3059,8 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct drm_plane *plane = crtc->primary; + bool visible = to_intel_plane_state(plane->state)->visible; struct drm_i915_gem_object *obj; int pipe = intel_crtc->pipe; u32 plane_ctl, stride_div, stride; @@ -3066,17 +3068,15 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, unsigned int rotation; int x_offset, y_offset; unsigned long surf_addr; - struct drm_plane *plane; struct intel_crtc_state *crtc_state = intel_crtc->config; struct intel_plane_state *plane_state; int src_x = 0, src_y = 0, src_w = 0, src_h = 0; int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; int scaler_id = -1; - plane = crtc->primary; plane_state = to_intel_plane_state(plane->state); - if (!intel_crtc->primary_enabled || !fb) { + if (!visible || !fb) { I915_WRITE(PLANE_CTL(pipe, 0), 0); I915_WRITE(PLANE_SURF(pipe, 0), 0); POSTING_READ(PLANE_CTL(pipe, 0)); @@ -4783,7 +4783,6 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc) hsw_disable_ips(intel_crtc); intel_crtc_dpms_overlay(intel_crtc, false); - intel_crtc->primary_enabled = false; for_each_intel_plane(dev, intel_plane) { if (intel_plane->pipe == pipe) { struct drm_crtc *from = intel_plane->base.crtc; @@ -12891,6 +12890,9 @@ static int intel_crtc_set_config(struct drm_mode_set *set) } else if (config->fb_changed) { struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); struct drm_plane *primary = set->crtc->primary; + struct intel_plane_state *plane_state = + to_intel_plane_state(primary->state); + bool was_visible = plane_state->visible; int vdisplay, hdisplay; drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); @@ -12903,7 +12905,8 @@ static int intel_crtc_set_config(struct drm_mode_set *set) * We need to make sure the primary plane is re-enabled if it * has previously been turned off. */ - if (!intel_crtc->primary_enabled && ret == 0) { + plane_state = to_intel_plane_state(primary->state); + if (ret == 0 && !was_visible && plane_state->visible) { WARN_ON(!intel_crtc->active); intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); } @@ -13239,6 +13242,9 @@ intel_check_primary_plane(struct drm_plane *plane, return ret; if (intel_crtc->active) { + struct intel_plane_state *old_state = + to_intel_plane_state(plane->state); + intel_crtc->atomic.wait_for_flips = true; /* @@ -13251,20 +13257,20 @@ intel_check_primary_plane(struct drm_plane *plane, * one is done too late. We eventually need to unify * this. */ - if (intel_crtc->primary_enabled && + if (state->visible && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && dev_priv->fbc.crtc == intel_crtc && state->base.rotation != BIT(DRM_ROTATE_0)) { intel_crtc->atomic.disable_fbc = true; } - if (state->visible) { + if (state->visible && !old_state->visible) { /* * BDW signals flip done immediately if the plane * is disabled, even if the plane enable is already * armed to occur at the next vblank :( */ - if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled) + if (IS_BROADWELL(dev)) intel_crtc->atomic.wait_vblank = true; } @@ -13306,8 +13312,6 @@ intel_commit_primary_plane(struct drm_plane *plane, crtc->y = src->y1 >> 16; if (intel_crtc->active) { - intel_crtc->primary_enabled = state->visible; - if (state->visible) /* FIXME: kill this fastboot hack */ intel_update_pipe_size(intel_crtc); @@ -13325,9 +13329,6 @@ intel_disable_primary_plane(struct drm_plane *plane, struct drm_device *dev = plane->dev; struct drm_i915_private *dev_priv = dev->dev_private; - if (!force) - to_intel_crtc(crtc)->primary_enabled = false; - dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); } @@ -14791,8 +14792,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) * Temporarily change the plane mapping and disable everything * ... */ plane = crtc->plane; + to_intel_plane_state(crtc->base.primary->state)->visible = true; crtc->plane = !plane; - crtc->primary_enabled = true; dev_priv->display.crtc_disable(&crtc->base); crtc->plane = plane; @@ -14969,6 +14970,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) int i; for_each_intel_crtc(dev, crtc) { + struct drm_plane *primary = crtc->base.primary; + struct intel_plane_state *plane_state; + memset(crtc->config, 0, sizeof(*crtc->config)); crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; @@ -14978,7 +14982,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) crtc->base.state->enable = crtc->active; crtc->base.enabled = crtc->active; - crtc->primary_enabled = primary_get_hw_state(crtc); + + plane_state = to_intel_plane_state(primary->state); + plane_state->visible = primary_get_hw_state(crtc); DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", crtc->base.base.id, diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 9d69d7cfd17a..52673c74855b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -507,7 +507,6 @@ struct intel_crtc { */ bool active; unsigned long enabled_power_domains; - bool primary_enabled; /* is the primary plane (partially) visible? */ bool lowfreq_avail; struct intel_overlay *overlay; struct intel_unpin_work *unpin_work; diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 4165ce0644f7..6abb83432d4d 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -457,7 +457,7 @@ static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; if (intel_crtc_active(tmp_crtc) && - to_intel_crtc(tmp_crtc)->primary_enabled) { + to_intel_plane_state(tmp_crtc->primary->state)->visible) { if (one_pipe_only && crtc) { if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); -- cgit v1.2.3 From 87d4300a7dbc19634018e147b4753f3c9bb5f471 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 21 Apr 2015 17:12:54 +0300 Subject: drm/i915: Move intel_(pre_disable/post_enable)_primary to intel_display.c, and use it there. They're the same code, so why not? Signed-off-by: Maarten Lankhorst Reviewed-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 158 ++++++++++++++++++++++------------- drivers/gpu/drm/i915/intel_drv.h | 2 - drivers/gpu/drm/i915/intel_sprite.c | 68 --------------- 3 files changed, 102 insertions(+), 126 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a912934e65a2..cb0c025427b7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2240,14 +2240,6 @@ static void intel_enable_primary_hw_plane(struct drm_plane *plane, dev_priv->display.update_primary_plane(crtc, plane->fb, crtc->x, crtc->y); - - /* - * BDW signals flip done immediately if the plane - * is disabled, even if the plane enable is already - * armed to occur at the next vblank :( - */ - if (IS_BROADWELL(dev)) - intel_wait_for_vblank(dev, intel_crtc->pipe); } static bool need_vtd_wa(struct drm_device *dev) @@ -4742,17 +4734,38 @@ static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) */ } -static void intel_crtc_enable_planes(struct drm_crtc *crtc) +/** + * intel_post_enable_primary - Perform operations after enabling primary plane + * @crtc: the CRTC whose primary plane was just enabled + * + * Performs potentially sleeping operations that must be done after the primary + * plane is enabled, such as updating FBC and IPS. Note that this may be + * called due to an explicit primary plane update, or due to an implicit + * re-enable that is caused when a sprite plane is updated to no longer + * completely hide the primary plane. + */ +static void +intel_post_enable_primary(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_crtc->pipe; - intel_enable_primary_hw_plane(crtc->primary, crtc); - intel_enable_sprite_planes(crtc); - intel_crtc_update_cursor(crtc, true); - intel_crtc_dpms_overlay(intel_crtc, true); + /* + * BDW signals flip done immediately if the plane + * is disabled, even if the plane enable is already + * armed to occur at the next vblank :( + */ + if (IS_BROADWELL(dev)) + intel_wait_for_vblank(dev, pipe); + /* + * FIXME IPS should be fine as long as one plane is + * enabled, but in practice it seems to have problems + * when going from primary only to sprite only and vice + * versa. + */ hsw_enable_ips(intel_crtc); mutex_lock(&dev->struct_mutex); @@ -4760,27 +4773,95 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc) mutex_unlock(&dev->struct_mutex); /* - * FIXME: Once we grow proper nuclear flip support out of this we need - * to compute the mask of flip planes precisely. For the time being - * consider this a flip from a NULL plane. + * Gen2 reports pipe underruns whenever all planes are disabled. + * So don't enable underrun reporting before at least some planes + * are enabled. + * FIXME: Need to fix the logic to work when we turn off all planes + * but leave the pipe running. */ - intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); + if (IS_GEN2(dev)) + intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); + + /* Underruns don't raise interrupts, so check manually. */ + if (HAS_GMCH_DISPLAY(dev)) + i9xx_check_fifo_underruns(dev_priv); } -static void intel_crtc_disable_planes(struct drm_crtc *crtc) +/** + * intel_pre_disable_primary - Perform operations before disabling primary plane + * @crtc: the CRTC whose primary plane is to be disabled + * + * Performs potentially sleeping operations that must be done before the + * primary plane is disabled, such as updating FBC and IPS. Note that this may + * be called due to an explicit primary plane update, or due to an implicit + * disable that is caused when a sprite plane completely hides the primary + * plane. + */ +static void +intel_pre_disable_primary(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_plane *intel_plane; int pipe = intel_crtc->pipe; - intel_crtc_wait_for_pending_flips(crtc); + /* + * Gen2 reports pipe underruns whenever all planes are disabled. + * So diasble underrun reporting before all the planes get disabled. + * FIXME: Need to fix the logic to work when we turn off all planes + * but leave the pipe running. + */ + if (IS_GEN2(dev)) + intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); + + /* + * Vblank time updates from the shadow to live plane control register + * are blocked if the memory self-refresh mode is active at that + * moment. So to make sure the plane gets truly disabled, disable + * first the self-refresh mode. The self-refresh enable bit in turn + * will be checked/applied by the HW only at the next frame start + * event which is after the vblank start event, so we need to have a + * wait-for-vblank between disabling the plane and the pipe. + */ + if (HAS_GMCH_DISPLAY(dev)) + intel_set_memory_cxsr(dev_priv, false); + mutex_lock(&dev->struct_mutex); if (dev_priv->fbc.crtc == intel_crtc) intel_fbc_disable(dev); + mutex_unlock(&dev->struct_mutex); + /* + * FIXME IPS should be fine as long as one plane is + * enabled, but in practice it seems to have problems + * when going from primary only to sprite only and vice + * versa. + */ hsw_disable_ips(intel_crtc); +} + +static void intel_crtc_enable_planes(struct drm_crtc *crtc) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + + intel_enable_primary_hw_plane(crtc->primary, crtc); + intel_enable_sprite_planes(crtc); + intel_crtc_update_cursor(crtc, true); + intel_crtc_dpms_overlay(intel_crtc, true); + + intel_post_enable_primary(crtc); +} + +static void intel_crtc_disable_planes(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_plane *intel_plane; + int pipe = intel_crtc->pipe; + + intel_crtc_wait_for_pending_flips(crtc); + + intel_pre_disable_primary(crtc); intel_crtc_dpms_overlay(intel_crtc, false); for_each_intel_plane(dev, intel_plane) { @@ -5839,9 +5920,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) encoder->enable(encoder); intel_crtc_enable_planes(crtc); - - /* Underruns don't raise interrupts, so check manually. */ - i9xx_check_fifo_underruns(dev_priv); } static void i9xx_set_pll_dividers(struct intel_crtc *crtc) @@ -5900,19 +5978,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) encoder->enable(encoder); intel_crtc_enable_planes(crtc); - - /* - * Gen2 reports pipe underruns whenever all planes are disabled. - * So don't enable underrun reporting before at least some planes - * are enabled. - * FIXME: Need to fix the logic to work when we turn off all planes - * but leave the pipe running. - */ - if (IS_GEN2(dev)) - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); - - /* Underruns don't raise interrupts, so check manually. */ - i9xx_check_fifo_underruns(dev_priv); } static void i9xx_pfit_disable(struct intel_crtc *crtc) @@ -5941,25 +6006,6 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) if (!intel_crtc->active) return; - /* - * Gen2 reports pipe underruns whenever all planes are disabled. - * So diasble underrun reporting before all the planes get disabled. - * FIXME: Need to fix the logic to work when we turn off all planes - * but leave the pipe running. - */ - if (IS_GEN2(dev)) - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); - - /* - * Vblank time updates from the shadow to live plane control register - * are blocked if the memory self-refresh mode is active at that - * moment. So to make sure the plane gets truly disabled, disable - * first the self-refresh mode. The self-refresh enable bit in turn - * will be checked/applied by the HW only at the next frame start - * event which is after the vblank start event, so we need to have a - * wait-for-vblank between disabling the plane and the pipe. - */ - intel_set_memory_cxsr(dev_priv, false); intel_crtc_disable_planes(crtc); /* @@ -12908,7 +12954,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set) plane_state = to_intel_plane_state(primary->state); if (ret == 0 && !was_visible && plane_state->visible) { WARN_ON(!intel_crtc->active); - intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); + intel_post_enable_primary(set->crtc); } /* diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 52673c74855b..af697520a5cf 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1389,8 +1389,6 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data, bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count); void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count); -void intel_post_enable_primary(struct drm_crtc *crtc); -void intel_pre_disable_primary(struct drm_crtc *crtc); /* intel_tv.c */ void intel_tv_init(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 95602da15984..f215e223aa4a 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -753,74 +753,6 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force) intel_flush_primary_plane(dev_priv, intel_crtc->plane); } -/** - * intel_post_enable_primary - Perform operations after enabling primary plane - * @crtc: the CRTC whose primary plane was just enabled - * - * Performs potentially sleeping operations that must be done after the primary - * plane is enabled, such as updating FBC and IPS. Note that this may be - * called due to an explicit primary plane update, or due to an implicit - * re-enable that is caused when a sprite plane is updated to no longer - * completely hide the primary plane. - */ -void -intel_post_enable_primary(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - - /* - * BDW signals flip done immediately if the plane - * is disabled, even if the plane enable is already - * armed to occur at the next vblank :( - */ - if (IS_BROADWELL(dev)) - intel_wait_for_vblank(dev, intel_crtc->pipe); - - /* - * FIXME IPS should be fine as long as one plane is - * enabled, but in practice it seems to have problems - * when going from primary only to sprite only and vice - * versa. - */ - hsw_enable_ips(intel_crtc); - - mutex_lock(&dev->struct_mutex); - intel_fbc_update(dev); - mutex_unlock(&dev->struct_mutex); -} - -/** - * intel_pre_disable_primary - Perform operations before disabling primary plane - * @crtc: the CRTC whose primary plane is to be disabled - * - * Performs potentially sleeping operations that must be done before the - * primary plane is disabled, such as updating FBC and IPS. Note that this may - * be called due to an explicit primary plane update, or due to an implicit - * disable that is caused when a sprite plane completely hides the primary - * plane. - */ -void -intel_pre_disable_primary(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - - mutex_lock(&dev->struct_mutex); - if (dev_priv->fbc.crtc == intel_crtc) - intel_fbc_disable(dev); - mutex_unlock(&dev->struct_mutex); - - /* - * FIXME IPS should be fine as long as one plane is - * enabled, but in practice it seems to have problems - * when going from primary only to sprite only and vice - * versa. - */ - hsw_disable_ips(intel_crtc); -} - static int intel_check_sprite_plane(struct drm_plane *plane, struct intel_plane_state *state) -- cgit v1.2.3 From 7cac945fbebceb99b68f357cde10622441b5510f Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 21 Apr 2015 17:12:55 +0300 Subject: drm/i915: Rename intel_crtc_dpms_overlay. To make it clear that it isn't called during crtc enable. Signed-off-by: Maarten Lankhorst Reviewed-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cb0c025427b7..63db21a39d81 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4716,9 +4716,9 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc) hsw_enable_ips(intel_crtc); } -static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) +static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) { - if (!enable && intel_crtc->overlay) { + if (intel_crtc->overlay) { struct drm_device *dev = intel_crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -4847,7 +4847,6 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc) intel_enable_primary_hw_plane(crtc->primary, crtc); intel_enable_sprite_planes(crtc); intel_crtc_update_cursor(crtc, true); - intel_crtc_dpms_overlay(intel_crtc, true); intel_post_enable_primary(crtc); } @@ -4863,7 +4862,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc) intel_pre_disable_primary(crtc); - intel_crtc_dpms_overlay(intel_crtc, false); + intel_crtc_dpms_overlay_disable(intel_crtc); for_each_intel_plane(dev, intel_plane) { if (intel_plane->pipe == pipe) { struct drm_crtc *from = intel_plane->base.crtc; -- cgit v1.2.3 From ce22dba92de22e951dee2ff89937a39754d2dd91 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 21 Apr 2015 17:12:56 +0300 Subject: drm/i915: Move toggling planes out of crtc enable/disable. This makes disabling planes more explicit. Signed-off-by: Maarten Lankhorst [anderco: fixed warning due to using drm_crtc instead of intel_crtc] Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 6 ++--- drivers/gpu/drm/i915/intel_display.c | 46 ++++++++++++++++++++++-------------- drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 31 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 1afbce2c591e..adbbddab42c6 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3611,8 +3611,7 @@ static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); - dev_priv->display.crtc_disable(&crtc->base); - dev_priv->display.crtc_enable(&crtc->base); + intel_crtc_reset(crtc); } drm_modeset_unlock_all(dev); } @@ -3633,8 +3632,7 @@ static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) if (crtc->config->pch_pfit.force_thru) { crtc->config->pch_pfit.force_thru = false; - dev_priv->display.crtc_disable(&crtc->base); - dev_priv->display.crtc_enable(&crtc->base); + intel_crtc_reset(crtc); intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 63db21a39d81..d5d648030af0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -107,6 +107,8 @@ static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_cr struct intel_crtc_state *crtc_state); static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, int num_connectors); +static void intel_crtc_enable_planes(struct drm_crtc *crtc); +static void intel_crtc_disable_planes(struct drm_crtc *crtc); static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) { @@ -3206,6 +3208,19 @@ static void intel_update_primary_planes(struct drm_device *dev) } } +void intel_crtc_reset(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + if (!crtc->active) + return; + + intel_crtc_disable_planes(&crtc->base); + dev_priv->display.crtc_disable(&crtc->base); + dev_priv->display.crtc_enable(&crtc->base); + intel_crtc_enable_planes(&crtc->base); +} + void intel_prepare_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); @@ -3226,8 +3241,11 @@ void intel_prepare_reset(struct drm_device *dev) * g33 docs say we should at least disable all the planes. */ for_each_intel_crtc(dev, crtc) { - if (crtc->active) - dev_priv->display.crtc_disable(&crtc->base); + if (!crtc->active) + continue; + + intel_crtc_disable_planes(&crtc->base); + dev_priv->display.crtc_disable(&crtc->base); } } @@ -4842,8 +4860,6 @@ intel_pre_disable_primary(struct drm_crtc *crtc) static void intel_crtc_enable_planes(struct drm_crtc *crtc) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - intel_enable_primary_hw_plane(crtc->primary, crtc); intel_enable_sprite_planes(crtc); intel_crtc_update_cursor(crtc, true); @@ -4949,8 +4965,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) if (HAS_PCH_CPT(dev)) cpt_verify_modeset(dev, intel_crtc->pipe); - - intel_crtc_enable_planes(crtc); } /* IPS only exists on ULT machines and is tied to pipe A. */ @@ -5074,7 +5088,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) /* If we change the relative order between pipe/planes enabling, we need * to change the workaround. */ haswell_mode_set_planes_workaround(intel_crtc); - intel_crtc_enable_planes(crtc); } static void ironlake_pfit_disable(struct intel_crtc *crtc) @@ -5104,8 +5117,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) if (!intel_crtc->active) return; - intel_crtc_disable_planes(crtc); - for_each_encoder_on_crtc(dev, crtc, encoder) encoder->disable(encoder); @@ -5168,8 +5179,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) if (!intel_crtc->active) return; - intel_crtc_disable_planes(crtc); - for_each_encoder_on_crtc(dev, crtc, encoder) { intel_opregion_notify_encoder(encoder, false); encoder->disable(encoder); @@ -5917,8 +5926,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) for_each_encoder_on_crtc(dev, crtc, encoder) encoder->enable(encoder); - - intel_crtc_enable_planes(crtc); } static void i9xx_set_pll_dividers(struct intel_crtc *crtc) @@ -5975,8 +5982,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) for_each_encoder_on_crtc(dev, crtc, encoder) encoder->enable(encoder); - - intel_crtc_enable_planes(crtc); } static void i9xx_pfit_disable(struct intel_crtc *crtc) @@ -6005,8 +6010,6 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) if (!intel_crtc->active) return; - intel_crtc_disable_planes(crtc); - /* * On gen2 planes are double buffered but the pipe isn't, so we must * wait for planes to fully turn off before disabling the pipe. @@ -6070,9 +6073,11 @@ void intel_crtc_control(struct drm_crtc *crtc, bool enable) intel_crtc->enabled_power_domains = domains; dev_priv->display.crtc_enable(crtc); + intel_crtc_enable_planes(crtc); } } else { if (intel_crtc->active) { + intel_crtc_disable_planes(crtc); dev_priv->display.crtc_disable(crtc); domains = intel_crtc->enabled_power_domains; @@ -6107,6 +6112,7 @@ static void intel_crtc_disable(struct drm_crtc *crtc) /* crtc should still be enabled when we disable it. */ WARN_ON(!crtc->state->enable); + intel_crtc_disable_planes(crtc); dev_priv->display.crtc_disable(crtc); dev_priv->display.off(crtc); @@ -12346,8 +12352,10 @@ static int __intel_set_mode(struct drm_crtc *crtc, intel_crtc_disable(&intel_crtc->base); for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { - if (intel_crtc->base.state->enable) + if (intel_crtc->base.state->enable) { + intel_crtc_disable_planes(&intel_crtc->base); dev_priv->display.crtc_disable(&intel_crtc->base); + } } /* crtc->mode is already used by the ->mode_set callbacks, hence we need @@ -12395,6 +12403,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, update_scanline_offset(intel_crtc); dev_priv->display.crtc_enable(&intel_crtc->base); + intel_crtc_enable_planes(&intel_crtc->base); } /* FIXME: add subpixel order */ @@ -14839,6 +14848,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) plane = crtc->plane; to_intel_plane_state(crtc->base.primary->state)->visible = true; crtc->plane = !plane; + intel_crtc_disable_planes(&crtc->base); dev_priv->display.crtc_disable(&crtc->base); crtc->plane = plane; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index af697520a5cf..6fe36ddbb42f 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -994,6 +994,7 @@ void intel_mark_busy(struct drm_device *dev); void intel_mark_idle(struct drm_device *dev); void intel_crtc_restore_mode(struct drm_crtc *crtc); void intel_crtc_control(struct drm_crtc *crtc, bool enable); +void intel_crtc_reset(struct intel_crtc *crtc); void intel_crtc_update_dpms(struct drm_crtc *crtc); void intel_encoder_destroy(struct drm_encoder *encoder); int intel_connector_init(struct intel_connector *); -- cgit v1.2.3 From e5d958ef42ff99ab2cf7980f4b7317d3bbd8793f Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:12:57 +0300 Subject: drm/i915: Don't check for NULL before freeing state This is not necessary after the below commit. commit a0211bb482c346820506c546a6a58b8357999a99 Author: Ander Conselvan de Oliveira Date: Mon Mar 30 14:05:43 2015 +0300 drm/atomic: Don't try to free a NULL state Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d5d648030af0..1375f53cdc95 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9860,10 +9860,8 @@ retry: fail: intel_crtc->new_enabled = crtc->state->enable; fail_unlock: - if (state) { - drm_atomic_state_free(state); - state = NULL; - } + drm_atomic_state_free(state); + state = NULL; if (ret == -EDEADLK) { drm_modeset_backoff(ctx); @@ -13003,8 +13001,7 @@ fail: } out_config: - if (state) - drm_atomic_state_free(state); + drm_atomic_state_free(state); intel_set_config_free(config); return ret; -- cgit v1.2.3 From f0c60574eb1216b0904c0d696c64d5096d6e4913 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:12:58 +0300 Subject: drm/i915: Call drm helpers when duplicating crtc and plane states Use the helpers introduced by the commit below to properly initialize the duplicated states. commit f5e7840b0c4368f8cdbb055188c2a0eef50c3052 Author: Thierry Reding Date: Wed Jan 28 14:54:32 2015 +0100 drm/atomic: Add helpers for state-subclassing drivers Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_atomic.c | 8 ++++++-- drivers/gpu/drm/i915/intel_atomic_plane.c | 4 ++-- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index cb6d5f2d9b60..7ed8033aae60 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -250,8 +250,12 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) crtc_state = kmemdup(intel_crtc->config, sizeof(*intel_crtc->config), GFP_KERNEL); - if (crtc_state) - crtc_state->base.crtc = crtc; + if (!crtc_state) + return NULL; + + __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base); + + crtc_state->base.crtc = crtc; return &crtc_state->base; } diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index dc8e1360fb20..77462e1360bc 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -85,8 +85,8 @@ intel_plane_duplicate_state(struct drm_plane *plane) return NULL; state = &intel_state->base; - if (state->fb) - drm_framebuffer_reference(state->fb); + + __drm_atomic_helper_plane_duplicate_state(plane, state); return state; } -- cgit v1.2.3 From da3ced29869a1e11720b71bf9354f7a548596338 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:12:59 +0300 Subject: drm/i915: Use for_each_connector_in_state helper macro Simplifies looping over connector states a bit. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 9 +++-- drivers/gpu/drm/i915/intel_display.c | 72 +++++++++++------------------------- drivers/gpu/drm/i915/intel_dp_mst.c | 13 ++++--- drivers/gpu/drm/i915/intel_hdmi.c | 7 +--- 4 files changed, 36 insertions(+), 65 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index b8eabc65dc27..ec5d2eaef43c 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -584,17 +584,18 @@ intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct intel_encoder *ret = NULL; struct drm_atomic_state *state; + struct drm_connector *connector; + struct drm_connector_state *connector_state; int num_encoders = 0; int i; state = crtc_state->base.state; - for (i = 0; i < state->num_connector; i++) { - if (!state->connectors[i] || - state->connector_states[i]->crtc != crtc_state->base.crtc) + for_each_connector_in_state(state, connector, connector_state, i) { + if (connector_state->crtc != crtc_state->base.crtc) continue; - ret = to_intel_encoder(state->connector_states[i]->best_encoder); + ret = to_intel_encoder(connector_state->best_encoder); num_encoders++; } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1375f53cdc95..b1f5038221d5 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -453,15 +453,12 @@ static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, int type) { struct drm_atomic_state *state = crtc_state->base.state; + struct drm_connector *connector; struct drm_connector_state *connector_state; struct intel_encoder *encoder; int i, num_connectors = 0; - for (i = 0; i < state->num_connector; i++) { - if (!state->connectors[i]) - continue; - - connector_state = state->connector_states[i]; + for_each_connector_in_state(state, connector, connector_state, i) { if (connector_state->crtc != crtc_state->base.crtc) continue; @@ -7461,14 +7458,11 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, struct intel_encoder *encoder; const intel_limit_t *limit; struct drm_atomic_state *state = crtc_state->base.state; + struct drm_connector *connector; struct drm_connector_state *connector_state; int i; - for (i = 0; i < state->num_connector; i++) { - if (!state->connectors[i]) - continue; - - connector_state = state->connector_states[i]; + for_each_connector_in_state(state, connector, connector_state, i) { if (connector_state->crtc != &crtc->base) continue; @@ -8152,16 +8146,13 @@ static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) struct drm_device *dev = crtc_state->base.crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_atomic_state *state = crtc_state->base.state; + struct drm_connector *connector; struct drm_connector_state *connector_state; struct intel_encoder *encoder; int num_connectors = 0, i; bool is_lvds = false; - for (i = 0; i < state->num_connector; i++) { - if (!state->connectors[i]) - continue; - - connector_state = state->connector_states[i]; + for_each_connector_in_state(state, connector, connector_state, i) { if (connector_state->crtc != crtc_state->base.crtc) continue; @@ -8415,17 +8406,14 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_atomic_state *state = crtc_state->base.state; + struct drm_connector *connector; struct drm_connector_state *connector_state; struct intel_encoder *encoder; uint32_t dpll; int factor, num_connectors = 0, i; bool is_lvds = false, is_sdvo = false; - for (i = 0; i < state->num_connector; i++) { - if (!state->connectors[i]) - continue; - - connector_state = state->connector_states[i]; + for_each_connector_in_state(state, connector, connector_state, i) { if (connector_state->crtc != crtc_state->base.crtc) continue; @@ -11149,7 +11137,8 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_atomic_state *state; - struct intel_connector *connector; + struct drm_connector *connector; + struct drm_connector_state *connector_state; int bpp, i; if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) @@ -11165,15 +11154,12 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc, state = pipe_config->base.state; /* Clamp display bpp to EDID value */ - for (i = 0; i < state->num_connector; i++) { - if (!state->connectors[i]) - continue; - - connector = to_intel_connector(state->connectors[i]); - if (state->connector_states[i]->crtc != &crtc->base) + for_each_connector_in_state(state, connector, connector_state, i) { + if (connector_state->crtc != &crtc->base) continue; - connected_sink_compute_bpp(connector, pipe_config); + connected_sink_compute_bpp(to_intel_connector(connector), + pipe_config); } return bpp; @@ -11300,14 +11286,11 @@ static bool check_single_encoder_cloning(struct drm_atomic_state *state, struct intel_encoder *encoder) { struct intel_encoder *source_encoder; + struct drm_connector *connector; struct drm_connector_state *connector_state; int i; - for (i = 0; i < state->num_connector; i++) { - if (!state->connectors[i]) - continue; - - connector_state = state->connector_states[i]; + for_each_connector_in_state(state, connector, connector_state, i) { if (connector_state->crtc != &crtc->base) continue; @@ -11324,14 +11307,11 @@ static bool check_encoder_cloning(struct drm_atomic_state *state, struct intel_crtc *crtc) { struct intel_encoder *encoder; + struct drm_connector *connector; struct drm_connector_state *connector_state; int i; - for (i = 0; i < state->num_connector; i++) { - if (!state->connectors[i]) - continue; - - connector_state = state->connector_states[i]; + for_each_connector_in_state(state, connector, connector_state, i) { if (connector_state->crtc != &crtc->base) continue; @@ -11347,6 +11327,7 @@ static bool check_digital_port_conflicts(struct drm_atomic_state *state) { struct drm_device *dev = state->dev; struct intel_encoder *encoder; + struct drm_connector *connector; struct drm_connector_state *connector_state; unsigned int used_ports = 0; int i; @@ -11356,11 +11337,7 @@ static bool check_digital_port_conflicts(struct drm_atomic_state *state) * list to detect the problem on ddi platforms * where there's just one encoder per digital port. */ - for (i = 0; i < state->num_connector; i++) { - if (!state->connectors[i]) - continue; - - connector_state = state->connector_states[i]; + for_each_connector_in_state(state, connector, connector_state, i) { if (!connector_state->best_encoder) continue; @@ -11411,7 +11388,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, struct drm_atomic_state *state) { struct intel_encoder *encoder; - struct intel_connector *connector; + struct drm_connector *connector; struct drm_connector_state *connector_state; struct intel_crtc_state *pipe_config; int base_bpp, ret = -EINVAL; @@ -11489,12 +11466,7 @@ encoder_retry: * adjust it according to limitations or connector properties, and also * a chance to reject the mode entirely. */ - for (i = 0; i < state->num_connector; i++) { - connector = to_intel_connector(state->connectors[i]); - if (!connector) - continue; - - connector_state = state->connector_states[i]; + for_each_connector_in_state(state, connector, connector_state, i) { if (connector_state->crtc != crtc) continue; diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 3945057c5bbe..6e4cc5334f47 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -40,7 +40,9 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, int bpp, i; int lane_count, slots, rate; struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; - struct intel_connector *found = NULL; + struct drm_connector *drm_connector; + struct intel_connector *connector, *found = NULL; + struct drm_connector_state *connector_state; int mst_pbn; pipe_config->dp_encoder_is_mst = true; @@ -70,12 +72,11 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, state = pipe_config->base.state; - for (i = 0; i < state->num_connector; i++) { - if (!state->connectors[i]) - continue; + for_each_connector_in_state(state, drm_connector, connector_state, i) { + connector = to_intel_connector(drm_connector); - if (state->connector_states[i]->best_encoder == &encoder->base) { - found = to_intel_connector(state->connectors[i]); + if (connector_state->best_encoder == &encoder->base) { + found = connector; break; } } diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 65bc3867dda2..590d46b124e0 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -964,6 +964,7 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) struct drm_device *dev = crtc_state->base.crtc->dev; struct drm_atomic_state *state; struct intel_encoder *encoder; + struct drm_connector *connector; struct drm_connector_state *connector_state; int count = 0, count_hdmi = 0; int i; @@ -973,11 +974,7 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) state = crtc_state->base.state; - for (i = 0; i < state->num_connector; i++) { - if (!state->connectors[i]) - continue; - - connector_state = state->connector_states[i]; + for_each_connector_in_state(state, connector, connector_state, i) { if (connector_state->crtc != crtc_state->base.crtc) continue; -- cgit v1.2.3 From 462a425aa541703a320b15f7f7f5b64de7e0eb47 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:00 +0300 Subject: drm/i915: Extract mode_changed computation out of stage_output_config() This should make the conversion to atomic easier, by splitting the initialization of the atomic state from the logic that decides if a modeset is needed. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 73 ++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b1f5038221d5..3207b0c1546f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12607,6 +12607,10 @@ static void intel_set_config_compute_mode_changes(struct drm_mode_set *set, struct intel_set_config *config) { + struct drm_device *dev = set->crtc->dev; + struct intel_connector *connector; + struct intel_encoder *encoder; + struct intel_crtc *crtc; /* We should be able to check here if the fb has the same properties * and then just flip_or_move it */ @@ -12650,6 +12654,36 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set, config->mode_changed = true; } + for_each_intel_connector(dev, connector) { + if (&connector->new_encoder->base == connector->base.encoder) + continue; + + config->mode_changed = true; + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", + connector->base.base.id, + connector->base.name); + } + + for_each_intel_encoder(dev, encoder) { + if (&encoder->new_crtc->base == encoder->base.crtc) + continue; + + DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", + encoder->base.base.id, + encoder->base.name); + config->mode_changed = true; + } + + for_each_intel_crtc(dev, crtc) { + if (crtc->new_enabled == crtc->base.state->enable) + continue; + + DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", + crtc->base.base.id, + crtc->new_enabled ? "en" : "dis"); + config->mode_changed = true; + } + DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", set->crtc->base.id, config->mode_changed, config->fb_changed); } @@ -12657,7 +12691,6 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set, static int intel_modeset_stage_output_state(struct drm_device *dev, struct drm_mode_set *set, - struct intel_set_config *config, struct drm_atomic_state *state) { struct intel_connector *connector; @@ -12693,14 +12726,6 @@ intel_modeset_stage_output_state(struct drm_device *dev, connector->base.base.id, connector->base.name); } - - - if (&connector->new_encoder->base != connector->base.encoder) { - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", - connector->base.base.id, - connector->base.name); - config->mode_changed = true; - } } /* connector->new_encoder is now updated for all connectors. */ @@ -12753,15 +12778,6 @@ intel_modeset_stage_output_state(struct drm_device *dev, encoder->new_crtc = NULL; else if (num_connectors > 1) return -EINVAL; - - /* Only now check for crtc changes so we don't miss encoders - * that will be disabled. */ - if (&encoder->new_crtc->base != encoder->base.crtc) { - DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", - encoder->base.base.id, - encoder->base.name); - config->mode_changed = true; - } } /* Now we've also updated encoder->new_crtc for all encoders. */ for_each_intel_connector(dev, connector) { @@ -12787,13 +12803,6 @@ intel_modeset_stage_output_state(struct drm_device *dev, break; } } - - if (crtc->new_enabled != crtc->base.state->enable) { - DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", - crtc->base.base.id, - crtc->new_enabled ? "en" : "dis"); - config->mode_changed = true; - } } return 0; @@ -12865,12 +12874,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set) save_set.y = set->crtc->y; save_set.fb = set->crtc->primary->fb; - /* Compute whether we need a full modeset, only an fb base update or no - * change at all. In the future we might also check whether only the - * mode changed, e.g. for LVDS where we only change the panel fitter in - * such cases. */ - intel_set_config_compute_mode_changes(set, config); - state = drm_atomic_state_alloc(dev); if (!state) { ret = -ENOMEM; @@ -12879,10 +12882,16 @@ static int intel_crtc_set_config(struct drm_mode_set *set) state->acquire_ctx = dev->mode_config.acquire_ctx; - ret = intel_modeset_stage_output_state(dev, set, config, state); + ret = intel_modeset_stage_output_state(dev, set, state); if (ret) goto fail; + /* Compute whether we need a full modeset, only an fb base update or no + * change at all. In the future we might also check whether only the + * mode changed, e.g. for LVDS where we only change the panel fitter in + * such cases. */ + intel_set_config_compute_mode_changes(set, config); + pipe_config = intel_modeset_compute_config(set->crtc, set->mode, state, &modeset_pipes, -- cgit v1.2.3 From 4be0731786de10d0e9ae1d159504c83c6b052647 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:01 +0300 Subject: drm/i915: Add crtc states before calling compute_config() The function intel_modeset_compute_config() needs to eventually become part of atomic_check(). At that point, all the affected crtcs need to be in the atomic state with the new values. So move the logic of adding crtc states out of that function. v2: Set crtc_state->enable in all cases. (Ander) Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 52 +++++++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3207b0c1546f..afdc065e0af1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9716,6 +9716,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector, struct drm_mode_config *config = &dev->mode_config; struct drm_atomic_state *state = NULL; struct drm_connector_state *connector_state; + struct intel_crtc_state *crtc_state; int ret, i = -1; DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", @@ -9811,6 +9812,14 @@ retry: connector_state->crtc = crtc; connector_state->best_encoder = &intel_encoder->base; + crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); + if (IS_ERR(crtc_state)) { + ret = PTR_ERR(crtc_state); + goto fail; + } + + crtc_state->base.enable = true; + if (!mode) mode = &load_detect_mode; @@ -9871,6 +9880,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct drm_atomic_state *state; struct drm_connector_state *connector_state; + struct intel_crtc_state *crtc_state; DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", connector->base.id, connector->name, @@ -9887,6 +9897,10 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, if (IS_ERR(connector_state)) goto fail; + crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); + if (IS_ERR(crtc_state)) + goto fail; + to_intel_connector(connector)->new_encoder = NULL; intel_encoder->new_crtc = NULL; intel_crtc->new_enabled = false; @@ -9894,6 +9908,8 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, connector_state->best_encoder = NULL; connector_state->crtc = NULL; + crtc_state->base.enable = false; + intel_set_mode(crtc, NULL, 0, 0, NULL, state); drm_atomic_state_free(state); @@ -12200,14 +12216,6 @@ intel_modeset_compute_config(struct drm_crtc *crtc, intel_modeset_affected_pipes(crtc, modeset_pipes, prepare_pipes, disable_pipes); - for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) { - pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); - if (IS_ERR(pipe_config)) - return pipe_config; - - pipe_config->base.enable = false; - } - /* * Note this needs changes when we start tracking multiple modes * and crtcs. At that point we'll need to compute the whole config @@ -12224,8 +12232,6 @@ intel_modeset_compute_config(struct drm_crtc *crtc, if (IS_ERR(pipe_config)) return pipe_config; - pipe_config->base.enable = true; - intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, "[modeset]"); } @@ -12450,9 +12456,11 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_atomic_state *state; + struct intel_crtc *intel_crtc; struct intel_encoder *encoder; struct intel_connector *connector; struct drm_connector_state *connector_state; + struct intel_crtc_state *crtc_state; state = drm_atomic_state_alloc(dev); if (!state) { @@ -12490,6 +12498,21 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc) } } + for_each_intel_crtc(dev, intel_crtc) { + if (intel_crtc->new_enabled == intel_crtc->base.enabled) + continue; + + crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); + if (IS_ERR(crtc_state)) { + DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n", + intel_crtc->base.base.id, + PTR_ERR(crtc_state)); + continue; + } + + crtc_state->base.enable = intel_crtc->new_enabled; + } + intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, state); @@ -12697,6 +12720,7 @@ intel_modeset_stage_output_state(struct drm_device *dev, struct drm_connector_state *connector_state; struct intel_encoder *encoder; struct intel_crtc *crtc; + struct intel_crtc_state *crtc_state; int ro; /* The upper layers ensure that we either disable a crtc or have a list @@ -12803,6 +12827,14 @@ intel_modeset_stage_output_state(struct drm_device *dev, break; } } + + if (crtc->new_enabled != crtc->base.state->enable) { + crtc_state = intel_atomic_get_crtc_state(state, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + crtc_state->base.enable = crtc->new_enabled; + } } return 0; -- cgit v1.2.3 From 548ee15b38ff5f6d7561f9e633efa20e7d7383b6 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:02 +0300 Subject: drm/i915: Don't pretend we can calculate multiple pipe_configs The code in intel_modeset_pipe_config() still needs changes before it can calculate more than just one pipe_config, and pretending it can will only make those changes more difficult. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 45 +++++++++++++++--------------------- 1 file changed, 19 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index afdc065e0af1..0d18a436e34c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11398,33 +11398,29 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) crtc_state->scaler_state = scaler_state; } -static struct intel_crtc_state * +static int intel_modeset_pipe_config(struct drm_crtc *crtc, struct drm_display_mode *mode, - struct drm_atomic_state *state) + struct drm_atomic_state *state, + struct intel_crtc_state *pipe_config) { struct intel_encoder *encoder; struct drm_connector *connector; struct drm_connector_state *connector_state; - struct intel_crtc_state *pipe_config; int base_bpp, ret = -EINVAL; int i; bool retry = true; if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); - return ERR_PTR(-EINVAL); + return -EINVAL; } if (!check_digital_port_conflicts(state)) { DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); - return ERR_PTR(-EINVAL); + return -EINVAL; } - pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); - if (IS_ERR(pipe_config)) - return pipe_config; - clear_intel_crtc_state(pipe_config); pipe_config->base.crtc = crtc; @@ -11521,9 +11517,9 @@ encoder_retry: DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", base_bpp, pipe_config->pipe_bpp, pipe_config->dither); - return pipe_config; + return 0; fail: - return ERR_PTR(ret); + return ret; } /* Computes which crtcs are affected and sets the relevant bits in the mask. For @@ -12204,9 +12200,7 @@ intel_modeset_compute_config(struct drm_crtc *crtc, unsigned *prepare_pipes, unsigned *disable_pipes) { - struct drm_device *dev = crtc->dev; - struct intel_crtc_state *pipe_config = NULL; - struct intel_crtc *intel_crtc; + struct intel_crtc_state *pipe_config; int ret = 0; ret = drm_atomic_add_affected_connectors(state, crtc); @@ -12222,21 +12216,20 @@ intel_modeset_compute_config(struct drm_crtc *crtc, * (i.e. one pipe_config for each crtc) rather than just the one * for this crtc. */ - for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) { - /* FIXME: For now we still expect modeset_pipes has at most - * one bit set. */ - if (WARN_ON(&intel_crtc->base != crtc)) - continue; + pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); + if (IS_ERR(pipe_config)) + return pipe_config; - pipe_config = intel_modeset_pipe_config(crtc, mode, state); - if (IS_ERR(pipe_config)) - return pipe_config; + if (!(*modeset_pipes & (1 << to_intel_crtc(crtc)->pipe))) + return pipe_config; - intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, - "[modeset]"); - } + ret = intel_modeset_pipe_config(crtc, mode, state, pipe_config); + if (ret) + return ERR_PTR(ret); + + intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]"); - return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));; + return pipe_config; } static int __intel_set_mode_setup_plls(struct drm_atomic_state *state, -- cgit v1.2.3 From 4fed33f6485be65b1e8155c843987030a2ae74fa Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:03 +0300 Subject: drm/i915: Calculate a new pipe_config based on new enabled state With the current implementation of intel_modeset_affected_pipes(), if a pipe will be enabled then it is in modeset_pipes. We'll remove that mask in a follow up patch, but want to preserve this behavior, so just make that explicit. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0d18a436e34c..aa445386b21f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12220,7 +12220,7 @@ intel_modeset_compute_config(struct drm_crtc *crtc, if (IS_ERR(pipe_config)) return pipe_config; - if (!(*modeset_pipes & (1 << to_intel_crtc(crtc)->pipe))) + if (!pipe_config->base.enable) return pipe_config; ret = intel_modeset_pipe_config(crtc, mode, state, pipe_config); -- cgit v1.2.3 From 0a9ab303b87a94115e361a7f3a15d9f481bc453b Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:04 +0300 Subject: drm/i915: Remove all *_pipes flags from modeset Set the mode_changed field on the crtc_states and use that instead. Note that even though this patch doesn't completely replace the logic in intel_modeset_affected_pipes(), that logic was never fully used to its full extent. Since the commit mentioned below, modeset_pipes and prepare_pipes would only contain at most the pipe for which the set_crtc ioctl was called. We can grow back that logic when the time comes. commit b6c5164d7bf624f3e1b750787ddb983150c5117c Author: Daniel Vetter Date: Fri Apr 12 18:48:43 2013 +0200 drm/i915: Fixup Oops in the pipe config computation v2: Don't set mode_changed unconditionally for modeset_crtc. (Ander) Check for needs_modeset() before trying to allocate a PLL. (Ander) Only call .crtc_enable() for pipes that were disabled. (Maarten) Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 311 +++++++++++++++-------------------- 1 file changed, 132 insertions(+), 179 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index aa445386b21f..62163d4e9b5f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5752,13 +5752,13 @@ static int intel_mode_max_pixclk(struct drm_atomic_state *state) return max_pixclk; } -static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, - unsigned *prepare_pipes) +static int valleyview_modeset_global_pipes(struct drm_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->dev); - struct intel_crtc *intel_crtc; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; int max_pixclk = intel_mode_max_pixclk(state); - int cdclk; + int cdclk, i; if (max_pixclk < 0) return max_pixclk; @@ -5771,10 +5771,20 @@ static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, if (cdclk == dev_priv->cdclk_freq) return 0; + /* add all active pipes to the state */ + for_each_crtc(state->dev, crtc) { + if (!crtc->state->enable) + continue; + + crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } + /* disable/enable all currently active pipes while we change cdclk */ - for_each_intel_crtc(state->dev, intel_crtc) - if (intel_crtc->base.state->enable) - *prepare_pipes |= (1 << intel_crtc->pipe); + for_each_crtc_in_state(state, crtc, crtc_state, i) + if (crtc_state->enable) + crtc_state->mode_changed = true; return 0; } @@ -11522,94 +11532,6 @@ fail: return ret; } -/* Computes which crtcs are affected and sets the relevant bits in the mask. For - * simplicity we use the crtc's pipe number (because it's easier to obtain). */ -static void -intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, - unsigned *prepare_pipes, unsigned *disable_pipes) -{ - struct intel_crtc *intel_crtc; - struct drm_device *dev = crtc->dev; - struct intel_encoder *encoder; - struct intel_connector *connector; - struct drm_crtc *tmp_crtc; - - *disable_pipes = *modeset_pipes = *prepare_pipes = 0; - - /* Check which crtcs have changed outputs connected to them, these need - * to be part of the prepare_pipes mask. We don't (yet) support global - * modeset across multiple crtcs, so modeset_pipes will only have one - * bit set at most. */ - for_each_intel_connector(dev, connector) { - if (connector->base.encoder == &connector->new_encoder->base) - continue; - - if (connector->base.encoder) { - tmp_crtc = connector->base.encoder->crtc; - - *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; - } - - if (connector->new_encoder) - *prepare_pipes |= - 1 << connector->new_encoder->new_crtc->pipe; - } - - for_each_intel_encoder(dev, encoder) { - if (encoder->base.crtc == &encoder->new_crtc->base) - continue; - - if (encoder->base.crtc) { - tmp_crtc = encoder->base.crtc; - - *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; - } - - if (encoder->new_crtc) - *prepare_pipes |= 1 << encoder->new_crtc->pipe; - } - - /* Check for pipes that will be enabled/disabled ... */ - for_each_intel_crtc(dev, intel_crtc) { - if (intel_crtc->base.state->enable == intel_crtc->new_enabled) - continue; - - if (!intel_crtc->new_enabled) - *disable_pipes |= 1 << intel_crtc->pipe; - else - *prepare_pipes |= 1 << intel_crtc->pipe; - } - - - /* set_mode is also used to update properties on life display pipes. */ - intel_crtc = to_intel_crtc(crtc); - if (intel_crtc->new_enabled) - *prepare_pipes |= 1 << intel_crtc->pipe; - - /* - * For simplicity do a full modeset on any pipe where the output routing - * changed. We could be more clever, but that would require us to be - * more careful with calling the relevant encoder->mode_set functions. - */ - if (*prepare_pipes) - *modeset_pipes = *prepare_pipes; - - /* ... and mask these out. */ - *modeset_pipes &= ~(*disable_pipes); - *prepare_pipes &= ~(*disable_pipes); - - /* - * HACK: We don't (yet) fully support global modesets. intel_set_config - * obies this rule, but the modeset restore mode of - * intel_modeset_setup_hw_state does not. - */ - *modeset_pipes &= 1 << intel_crtc->pipe; - *prepare_pipes &= 1 << intel_crtc->pipe; - - DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", - *modeset_pipes, *prepare_pipes, *disable_pipes); -} - static bool intel_crtc_in_use(struct drm_crtc *crtc) { struct drm_encoder *encoder; @@ -11622,13 +11544,22 @@ static bool intel_crtc_in_use(struct drm_crtc *crtc) return false; } +static bool +needs_modeset(struct drm_crtc_state *state) +{ + return state->mode_changed || state->active_changed; +} + static void -intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) +intel_modeset_update_state(struct drm_atomic_state *state) { + struct drm_device *dev = state->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_encoder *intel_encoder; - struct intel_crtc *intel_crtc; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; struct drm_connector *connector; + int i; intel_shared_dpll_commit(dev_priv); @@ -11636,26 +11567,36 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) if (!intel_encoder->base.crtc) continue; - intel_crtc = to_intel_crtc(intel_encoder->base.crtc); + for_each_crtc_in_state(state, crtc, crtc_state, i) + if (crtc == intel_encoder->base.crtc) + break; - if (prepare_pipes & (1 << intel_crtc->pipe)) + if (crtc != intel_encoder->base.crtc) + continue; + + if (crtc_state->enable && needs_modeset(crtc_state)) intel_encoder->connectors_active = false; } intel_modeset_commit_output_state(dev); /* Double check state. */ - for_each_intel_crtc(dev, intel_crtc) { - WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); + for_each_crtc(dev, crtc) { + WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc)); } list_for_each_entry(connector, &dev->mode_config.connector_list, head) { if (!connector->encoder || !connector->encoder->crtc) continue; - intel_crtc = to_intel_crtc(connector->encoder->crtc); + for_each_crtc_in_state(state, crtc, crtc_state, i) + if (crtc == connector->encoder->crtc) + break; + + if (crtc != connector->encoder->crtc) + continue; - if (prepare_pipes & (1 << intel_crtc->pipe)) { + if (crtc_state->enable && needs_modeset(crtc_state)) { struct drm_property *dpms_property = dev->mode_config.dpms_property; @@ -12192,13 +12133,28 @@ static void update_scanline_offset(struct intel_crtc *crtc) crtc->scanline_offset = 1; } +static void +intel_atomic_modeset_compute_changed_flags(struct drm_atomic_state *state, + struct drm_crtc *modeset_crtc) +{ + struct drm_crtc_state *crtc_state; + struct drm_crtc *crtc; + int i; + + for_each_crtc_in_state(state, crtc, crtc_state, i) { + if (crtc_state->enable != crtc->state->enable) + crtc_state->mode_changed = true; + + /* FIXME: Do we need to always set mode_changed for + * modeset_crtc if it is enabled? modeset_affect_pipes() + * did that. */ + } +} + static struct intel_crtc_state * intel_modeset_compute_config(struct drm_crtc *crtc, struct drm_display_mode *mode, - struct drm_atomic_state *state, - unsigned *modeset_pipes, - unsigned *prepare_pipes, - unsigned *disable_pipes) + struct drm_atomic_state *state) { struct intel_crtc_state *pipe_config; int ret = 0; @@ -12207,8 +12163,7 @@ intel_modeset_compute_config(struct drm_crtc *crtc, if (ret) return ERR_PTR(ret); - intel_modeset_affected_pipes(crtc, modeset_pipes, - prepare_pipes, disable_pipes); + intel_atomic_modeset_compute_changed_flags(state, crtc); /* * Note this needs changes when we start tracking multiple modes @@ -12232,33 +12187,41 @@ intel_modeset_compute_config(struct drm_crtc *crtc, return pipe_config; } -static int __intel_set_mode_setup_plls(struct drm_atomic_state *state, - unsigned modeset_pipes, - unsigned disable_pipes) +static int __intel_set_mode_setup_plls(struct drm_atomic_state *state) { struct drm_device *dev = state->dev; struct drm_i915_private *dev_priv = to_i915(dev); - unsigned clear_pipes = modeset_pipes | disable_pipes; + unsigned clear_pipes = 0; struct intel_crtc *intel_crtc; + struct intel_crtc_state *intel_crtc_state; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; int ret = 0; + int i; if (!dev_priv->display.crtc_compute_clock) return 0; + for_each_crtc_in_state(state, crtc, crtc_state, i) { + intel_crtc = to_intel_crtc(crtc); + + if (needs_modeset(crtc_state)) + clear_pipes |= 1 << intel_crtc->pipe; + } + ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); if (ret) goto done; - for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { - struct intel_crtc_state *crtc_state = - intel_atomic_get_crtc_state(state, intel_crtc); - - /* Modeset pipes should have a new state by now */ - if (WARN_ON(IS_ERR(crtc_state))) + for_each_crtc_in_state(state, crtc, crtc_state, i) { + if (!needs_modeset(crtc_state) || !crtc_state->enable) continue; + intel_crtc = to_intel_crtc(crtc); + intel_crtc_state = to_intel_crtc_state(crtc_state); + ret = dev_priv->display.crtc_compute_clock(intel_crtc, - crtc_state); + intel_crtc_state); if (ret) { intel_shared_dpll_abort_config(dev_priv); goto done; @@ -12269,21 +12232,21 @@ done: return ret; } -static int __intel_set_mode(struct drm_crtc *crtc, +static int __intel_set_mode(struct drm_crtc *modeset_crtc, struct drm_display_mode *mode, int x, int y, struct drm_framebuffer *fb, - struct intel_crtc_state *pipe_config, - unsigned modeset_pipes, - unsigned prepare_pipes, - unsigned disable_pipes) + struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->dev; + struct drm_device *dev = modeset_crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_display_mode *saved_mode; struct drm_atomic_state *state = pipe_config->base.state; struct intel_crtc_state *crtc_state_copy = NULL; struct intel_crtc *intel_crtc; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; int ret = 0; + int i; saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); if (!saved_mode) @@ -12295,7 +12258,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, goto done; } - *saved_mode = crtc->mode; + *saved_mode = modeset_crtc->mode; /* * See if the config requires any additional preparation, e.g. @@ -12305,25 +12268,24 @@ static int __intel_set_mode(struct drm_crtc *crtc, * adjusted_mode bits in the crtc directly. */ if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { - ret = valleyview_modeset_global_pipes(state, &prepare_pipes); + ret = valleyview_modeset_global_pipes(state); if (ret) goto done; - - /* may have added more to prepare_pipes than we should */ - prepare_pipes &= ~disable_pipes; } - ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes); + ret = __intel_set_mode_setup_plls(state); if (ret) goto done; - for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) - intel_crtc_disable(&intel_crtc->base); + for_each_crtc_in_state(state, crtc, crtc_state, i) { + if (!needs_modeset(crtc_state)) + continue; - for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { - if (intel_crtc->base.state->enable) { - intel_crtc_disable_planes(&intel_crtc->base); - dev_priv->display.crtc_disable(&intel_crtc->base); + if (!crtc_state->enable) { + intel_crtc_disable(crtc); + } else if (crtc->state->enable) { + intel_crtc_disable_planes(crtc); + dev_priv->display.crtc_disable(crtc); } } @@ -12334,32 +12296,36 @@ static int __intel_set_mode(struct drm_crtc *crtc, * pipes; here we assume a single modeset_pipe and only track the * single crtc and mode. */ - if (modeset_pipes) { - crtc->mode = *mode; + if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) { + modeset_crtc->mode = *mode; /* mode_set/enable/disable functions rely on a correct pipe * config. */ - intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); + intel_crtc_set_state(to_intel_crtc(modeset_crtc), pipe_config); /* * Calculate and store various constants which * are later needed by vblank and swap-completion * timestamping. They are derived from true hwmode. */ - drm_calc_timestamping_constants(crtc, + drm_calc_timestamping_constants(modeset_crtc, &pipe_config->base.adjusted_mode); } /* Only after disabling all output pipelines that will be changed can we * update the the output configuration. */ - intel_modeset_update_state(dev, prepare_pipes); + intel_modeset_update_state(state); modeset_update_crtc_power_domains(state); - for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { - struct drm_plane *primary = intel_crtc->base.primary; + if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) { + struct drm_plane *primary; int vdisplay, hdisplay; + intel_crtc = to_intel_crtc(modeset_crtc); + primary = intel_crtc->base.primary; + drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); + ret = drm_plane_helper_update(primary, &intel_crtc->base, fb, 0, 0, hdisplay, vdisplay, @@ -12368,20 +12334,23 @@ static int __intel_set_mode(struct drm_crtc *crtc, } /* Now enable the clocks, plane, pipe, and connectors that we set up. */ - for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { - update_scanline_offset(intel_crtc); + for_each_crtc_in_state(state, crtc, crtc_state, i) { + if (!needs_modeset(crtc_state) || !crtc_state->enable) + continue; + + update_scanline_offset(to_intel_crtc(crtc)); - dev_priv->display.crtc_enable(&intel_crtc->base); - intel_crtc_enable_planes(&intel_crtc->base); + dev_priv->display.crtc_enable(crtc); + intel_crtc_enable_planes(crtc); } /* FIXME: add subpixel order */ done: - if (ret && crtc->state->enable) - crtc->mode = *saved_mode; + if (ret && modeset_crtc->state->enable) + modeset_crtc->mode = *saved_mode; if (ret == 0 && pipe_config) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_crtc *intel_crtc = to_intel_crtc(modeset_crtc); /* The pipe_config will be freed with the atomic state, so * make a copy. */ @@ -12397,18 +12366,14 @@ done: return ret; } -static int intel_set_mode_pipes(struct drm_crtc *crtc, - struct drm_display_mode *mode, - int x, int y, struct drm_framebuffer *fb, - struct intel_crtc_state *pipe_config, - unsigned modeset_pipes, - unsigned prepare_pipes, - unsigned disable_pipes) +static int intel_set_mode_with_config(struct drm_crtc *crtc, + struct drm_display_mode *mode, + int x, int y, struct drm_framebuffer *fb, + struct intel_crtc_state *pipe_config) { int ret; - ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, - prepare_pipes, disable_pipes); + ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config); if (ret == 0) intel_modeset_check_state(crtc->dev); @@ -12422,22 +12387,15 @@ static int intel_set_mode(struct drm_crtc *crtc, struct drm_atomic_state *state) { struct intel_crtc_state *pipe_config; - unsigned modeset_pipes, prepare_pipes, disable_pipes; int ret = 0; - pipe_config = intel_modeset_compute_config(crtc, mode, state, - &modeset_pipes, - &prepare_pipes, - &disable_pipes); - + pipe_config = intel_modeset_compute_config(crtc, mode, state); if (IS_ERR(pipe_config)) { ret = PTR_ERR(pipe_config); goto out; } - ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, - modeset_pipes, prepare_pipes, - disable_pipes); + ret = intel_set_mode_with_config(crtc, mode, x, y, fb, pipe_config); if (ret) goto out; @@ -12863,7 +12821,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set) struct drm_atomic_state *state = NULL; struct intel_set_config *config; struct intel_crtc_state *pipe_config; - unsigned modeset_pipes, prepare_pipes, disable_pipes; int ret; BUG_ON(!set); @@ -12918,10 +12875,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set) intel_set_config_compute_mode_changes(set, config); pipe_config = intel_modeset_compute_config(set->crtc, set->mode, - state, - &modeset_pipes, - &prepare_pipes, - &disable_pipes); + state); if (IS_ERR(pipe_config)) { ret = PTR_ERR(pipe_config); goto fail; @@ -12941,10 +12895,9 @@ static int intel_crtc_set_config(struct drm_mode_set *set) intel_update_pipe_size(to_intel_crtc(set->crtc)); if (config->mode_changed) { - ret = intel_set_mode_pipes(set->crtc, set->mode, - set->x, set->y, set->fb, pipe_config, - modeset_pipes, prepare_pipes, - disable_pipes); + ret = intel_set_mode_with_config(set->crtc, set->mode, + set->x, set->y, set->fb, + pipe_config); } else if (config->fb_changed) { struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); struct drm_plane *primary = set->crtc->primary; -- cgit v1.2.3 From e13be6651743b6cebdd29d4049dcd52b3ece4274 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:05 +0300 Subject: drm/i915: Remove saved_mode from __intel_set_mode() There's no way that function can fail after it sets crtc->mode anymore, so there's no need to save the old mode for the failure case. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 62163d4e9b5f..e47dddf4aacb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12239,7 +12239,6 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, { struct drm_device *dev = modeset_crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct drm_display_mode *saved_mode; struct drm_atomic_state *state = pipe_config->base.state; struct intel_crtc_state *crtc_state_copy = NULL; struct intel_crtc *intel_crtc; @@ -12248,18 +12247,12 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, int ret = 0; int i; - saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); - if (!saved_mode) - return -ENOMEM; - crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); if (!crtc_state_copy) { ret = -ENOMEM; goto done; } - *saved_mode = modeset_crtc->mode; - /* * See if the config requires any additional preparation, e.g. * to adjust global state with pipes off. We need to do this @@ -12346,9 +12339,6 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, /* FIXME: add subpixel order */ done: - if (ret && modeset_crtc->state->enable) - modeset_crtc->mode = *saved_mode; - if (ret == 0 && pipe_config) { struct intel_crtc *intel_crtc = to_intel_crtc(modeset_crtc); @@ -12362,7 +12352,6 @@ done: kfree(crtc_state_copy); } - kfree(saved_mode); return ret; } -- cgit v1.2.3 From 054518ddff87565022bf1eb1578fcb00e42cc847 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:06 +0300 Subject: drm/i915: Move compute part of __intel_set_mode() to separate function The first function calls done in that function can still cause changes to the atomic state and may fail. This should eventually be part of our atomic check function, while the rest of the code in __intel_set_mode() is the commit hook. So this makes the legacy mode set more atomic-y. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 47 +++++++++++++++++++++++------------- 1 file changed, 30 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e47dddf4aacb..9655f1f1ae85 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12232,6 +12232,32 @@ done: return ret; } +/* Code that should eventually be part of atomic_check() */ +static int __intel_set_mode_checks(struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + int ret; + + /* + * See if the config requires any additional preparation, e.g. + * to adjust global state with pipes off. We need to do this + * here so we can get the modeset_pipe updated config for the new + * mode set on this crtc. For other crtcs we need to use the + * adjusted_mode bits in the crtc directly. + */ + if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { + ret = valleyview_modeset_global_pipes(state); + if (ret) + return ret; + } + + ret = __intel_set_mode_setup_plls(state); + if (ret) + return ret; + + return 0; +} + static int __intel_set_mode(struct drm_crtc *modeset_crtc, struct drm_display_mode *mode, int x, int y, struct drm_framebuffer *fb, @@ -12247,29 +12273,16 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, int ret = 0; int i; + ret = __intel_set_mode_checks(state); + if (ret < 0) + return ret; + crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); if (!crtc_state_copy) { ret = -ENOMEM; goto done; } - /* - * See if the config requires any additional preparation, e.g. - * to adjust global state with pipes off. We need to do this - * here so we can get the modeset_pipe updated config for the new - * mode set on this crtc. For other crtcs we need to use the - * adjusted_mode bits in the crtc directly. - */ - if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { - ret = valleyview_modeset_global_pipes(state); - if (ret) - goto done; - } - - ret = __intel_set_mode_setup_plls(state); - if (ret) - goto done; - for_each_crtc_in_state(state, crtc, crtc_state, i) { if (!needs_modeset(crtc_state)) continue; -- cgit v1.2.3 From 9eb45f228f24a2d1d98cb526e149aa18ba1f5ef5 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:07 +0300 Subject: drm/i915: Simplify error handling in __intel_set_mode() The remaining parts of the failure path could only be reached if the allocation of crtc_state_copy would fail. In that case, there is nothing to undo, so just get rid of the label for error handling and return an error code immediately. We also always allocate a pipe_config, even if the pipe is being disabled, so the remaining part of what was the error/done case can be simplified a little too. v2: Ignore return value from drm_plane_helper_update(). (Ander) Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9655f1f1ae85..9aa90abab4ba 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12278,10 +12278,8 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, return ret; crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); - if (!crtc_state_copy) { - ret = -ENOMEM; - goto done; - } + if (!crtc_state_copy) + return -ENOMEM; for_each_crtc_in_state(state, crtc, crtc_state, i) { if (!needs_modeset(crtc_state)) @@ -12337,6 +12335,7 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, hdisplay, vdisplay, x << 16, y << 16, hdisplay << 16, vdisplay << 16); + WARN_ON(ret != 0); } /* Now enable the clocks, plane, pipe, and connectors that we set up. */ @@ -12351,21 +12350,16 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, } /* FIXME: add subpixel order */ -done: - if (ret == 0 && pipe_config) { - struct intel_crtc *intel_crtc = to_intel_crtc(modeset_crtc); - - /* The pipe_config will be freed with the atomic state, so - * make a copy. */ - memcpy(crtc_state_copy, intel_crtc->config, - sizeof *crtc_state_copy); - intel_crtc->config = crtc_state_copy; - intel_crtc->base.state = &crtc_state_copy->base; - } else { - kfree(crtc_state_copy); - } - return ret; + intel_crtc = to_intel_crtc(modeset_crtc); + + /* The pipe_config will be freed with the atomic state, so + * make a copy. */ + memcpy(crtc_state_copy, intel_crtc->config, sizeof *crtc_state_copy); + intel_crtc->config = crtc_state_copy; + intel_crtc->base.state = &crtc_state_copy->base; + + return 0; } static int intel_set_mode_with_config(struct drm_crtc *crtc, -- cgit v1.2.3 From 561c8bda8fd1c536231eac8032e3792715f7db87 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:08 +0300 Subject: drm/i915: Don't modeset with old mode when set_crtc fails The modeset code is now properly divided in two phases, so that it only changes hardware state if it succeeds, so there's no ill-effect that needs to be undone on failure anymore. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 48 ------------------------------------ 1 file changed, 48 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9aa90abab4ba..36775a30664a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12787,33 +12787,9 @@ intel_modeset_stage_output_state(struct drm_device *dev, return 0; } -static void disable_crtc_nofb(struct intel_crtc *crtc) -{ - struct drm_device *dev = crtc->base.dev; - struct intel_encoder *encoder; - struct intel_connector *connector; - - DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", - pipe_name(crtc->pipe)); - - for_each_intel_connector(dev, connector) { - if (connector->new_encoder && - connector->new_encoder->new_crtc == crtc) - connector->new_encoder = NULL; - } - - for_each_intel_encoder(dev, encoder) { - if (encoder->new_crtc == crtc) - encoder->new_crtc = NULL; - } - - crtc->new_enabled = false; -} - static int intel_crtc_set_config(struct drm_mode_set *set) { struct drm_device *dev; - struct drm_mode_set save_set; struct drm_atomic_state *state = NULL; struct intel_set_config *config; struct intel_crtc_state *pipe_config; @@ -12846,12 +12822,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set) if (ret) goto out_config; - save_set.crtc = set->crtc; - save_set.mode = &set->crtc->mode; - save_set.x = set->crtc->x; - save_set.y = set->crtc->y; - save_set.fb = set->crtc->primary->fb; - state = drm_atomic_state_alloc(dev); if (!state) { ret = -ENOMEM; @@ -12935,24 +12905,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set) set->crtc->base.id, ret); fail: intel_set_config_restore_state(dev, config); - - drm_atomic_state_clear(state); - - /* - * HACK: if the pipe was on, but we didn't have a framebuffer, - * force the pipe off to avoid oopsing in the modeset code - * due to fb==NULL. This should only happen during boot since - * we don't yet reconstruct the FB from the hardware state. - */ - if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) - disable_crtc_nofb(to_intel_crtc(save_set.crtc)); - - /* Try to restore the config */ - if (config->mode_changed && - intel_set_mode(save_set.crtc, save_set.mode, - save_set.x, save_set.y, save_set.fb, - state)) - DRM_ERROR("failed to restore config after modeset failure\n"); } out_config: -- cgit v1.2.3 From d3a40d1bc8aea935c2df4634e374aecdc4fdbfc2 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:09 +0300 Subject: drm/i915: Add primary plane to atomic state in legacy modeset Add the primary plane state to the legacy modeset atomic state and use it when configuring the primary plane in __intel_set_mode(). This is a first step towards merging the flip path in intel_crtc_set_config() and __intel_set_mode(). v2: Set crtc to NULL if fb is NULL. (Maarten) Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 83 ++++++++++++++++++++++++++++++------ 1 file changed, 71 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 36775a30664a..44f6d5965f98 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9710,6 +9710,41 @@ mode_fits_in_fbdev(struct drm_device *dev, #endif } +static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, + struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_framebuffer *fb, + int x, int y) +{ + struct drm_plane_state *plane_state; + int hdisplay, vdisplay; + int ret; + + plane_state = drm_atomic_get_plane_state(state, crtc->primary); + if (IS_ERR(plane_state)) + return PTR_ERR(plane_state); + + if (mode) + drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); + else + hdisplay = vdisplay = 0; + + ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); + if (ret) + return ret; + drm_atomic_set_fb_for_plane(plane_state, fb); + plane_state->crtc_x = 0; + plane_state->crtc_y = 0; + plane_state->crtc_w = hdisplay; + plane_state->crtc_h = vdisplay; + plane_state->src_x = x << 16; + plane_state->src_y = y << 16; + plane_state->src_w = hdisplay << 16; + plane_state->src_h = vdisplay << 16; + + return 0; +} + bool intel_get_load_detect_pipe(struct drm_connector *connector, struct drm_display_mode *mode, struct intel_load_detect_pipe *old, @@ -9852,6 +9887,10 @@ retry: goto fail; } + ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); + if (ret) + goto fail; + if (intel_set_mode(crtc, mode, 0, 0, fb, state)) { DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); if (old->release_fb) @@ -9891,6 +9930,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, struct drm_atomic_state *state; struct drm_connector_state *connector_state; struct intel_crtc_state *crtc_state; + int ret; DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", connector->base.id, connector->name, @@ -9920,6 +9960,11 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, crtc_state->base.enable = false; + ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, + 0, 0); + if (ret) + goto fail; + intel_set_mode(crtc, NULL, 0, 0, NULL, state); drm_atomic_state_free(state); @@ -12270,6 +12315,8 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, struct intel_crtc *intel_crtc; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; + struct drm_plane *plane; + struct drm_plane_state *plane_state; int ret = 0; int i; @@ -12321,20 +12368,24 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, modeset_update_crtc_power_domains(state); - if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) { - struct drm_plane *primary; - int vdisplay, hdisplay; - - intel_crtc = to_intel_crtc(modeset_crtc); - primary = intel_crtc->base.primary; + for_each_plane_in_state(state, plane, plane_state, i) { + if (WARN_ON(plane != modeset_crtc->primary)) + continue; - drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); + /* Primary plane is disabled in intel_crtc_disable() */ + if (!pipe_config->base.enable) + continue; - ret = drm_plane_helper_update(primary, &intel_crtc->base, - fb, 0, 0, - hdisplay, vdisplay, - x << 16, y << 16, - hdisplay << 16, vdisplay << 16); + ret = drm_plane_helper_update(plane, plane_state->crtc, + plane_state->fb, + plane_state->crtc_x, + plane_state->crtc_y, + plane_state->crtc_w, + plane_state->crtc_h, + plane_state->src_x, + plane_state->src_y, + plane_state->src_w, + plane_state->src_h); WARN_ON(ret != 0); } @@ -12460,6 +12511,9 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc) crtc_state->base.enable = intel_crtc->new_enabled; } + intel_modeset_setup_plane_state(state, crtc, &crtc->mode, + crtc->primary->fb, crtc->x, crtc->y); + intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, state); @@ -12834,6 +12888,11 @@ static int intel_crtc_set_config(struct drm_mode_set *set) if (ret) goto fail; + ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode, + set->fb, set->x, set->y); + if (ret) + goto fail; + /* Compute whether we need a full modeset, only an fb base update or no * change at all. In the future we might also check whether only the * mode changed, e.g. for LVDS where we only change the panel fitter in -- cgit v1.2.3 From cf6d0d76cf797494b95e4971f662c6311ff92320 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:10 +0300 Subject: drm/i915: Delete fb, x and y parameters from mode set functions We don't need to pass it down the call chain anymore now that the plane state is set up properly. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 44f6d5965f98..daf3467a7934 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -83,7 +83,6 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, - int x, int y, struct drm_framebuffer *old_fb, struct drm_atomic_state *state); static int intel_framebuffer_init(struct drm_device *dev, struct intel_framebuffer *ifb, @@ -9891,7 +9890,7 @@ retry: if (ret) goto fail; - if (intel_set_mode(crtc, mode, 0, 0, fb, state)) { + if (intel_set_mode(crtc, mode, state)) { DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); if (old->release_fb) old->release_fb->funcs->destroy(old->release_fb); @@ -9965,7 +9964,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, if (ret) goto fail; - intel_set_mode(crtc, NULL, 0, 0, NULL, state); + intel_set_mode(crtc, NULL, state); drm_atomic_state_free(state); @@ -12305,7 +12304,6 @@ static int __intel_set_mode_checks(struct drm_atomic_state *state) static int __intel_set_mode(struct drm_crtc *modeset_crtc, struct drm_display_mode *mode, - int x, int y, struct drm_framebuffer *fb, struct intel_crtc_state *pipe_config) { struct drm_device *dev = modeset_crtc->dev; @@ -12415,12 +12413,11 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, static int intel_set_mode_with_config(struct drm_crtc *crtc, struct drm_display_mode *mode, - int x, int y, struct drm_framebuffer *fb, struct intel_crtc_state *pipe_config) { int ret; - ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config); + ret = __intel_set_mode(crtc, mode, pipe_config); if (ret == 0) intel_modeset_check_state(crtc->dev); @@ -12430,7 +12427,6 @@ static int intel_set_mode_with_config(struct drm_crtc *crtc, static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, - int x, int y, struct drm_framebuffer *fb, struct drm_atomic_state *state) { struct intel_crtc_state *pipe_config; @@ -12442,7 +12438,7 @@ static int intel_set_mode(struct drm_crtc *crtc, goto out; } - ret = intel_set_mode_with_config(crtc, mode, x, y, fb, pipe_config); + ret = intel_set_mode_with_config(crtc, mode, pipe_config); if (ret) goto out; @@ -12514,8 +12510,7 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc) intel_modeset_setup_plane_state(state, crtc, &crtc->mode, crtc->primary->fb, crtc->x, crtc->y); - intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, - state); + intel_set_mode(crtc, &crtc->mode, state); drm_atomic_state_free(state); } @@ -12921,7 +12916,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set) if (config->mode_changed) { ret = intel_set_mode_with_config(set->crtc, set->mode, - set->x, set->y, set->fb, pipe_config); } else if (config->fb_changed) { struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); -- cgit v1.2.3 From 8d8c9b519733c1f4ee6e0362f1e15244579873ae Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:11 +0300 Subject: drm/i915: Don't use struct intel_set_config *_changed flags Use the similar fields in crtc_state instead, so that this code can be moved to our future implementation of atomic_check(). Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 66 +++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index daf3467a7934..fe9f545412ec 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12226,6 +12226,18 @@ intel_modeset_compute_config(struct drm_crtc *crtc, if (ret) return ERR_PTR(ret); + /* Check things that can only be changed through modeset */ + if (pipe_config->has_audio != + to_intel_crtc(crtc)->config->has_audio) + pipe_config->base.mode_changed = true; + + /* + * Note we have an issue here with infoframes: current code + * only updates them on the full mode set path per hw + * requirements. So here we should be checking for any + * required changes and forcing a mode set. + */ + intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]"); return pipe_config; @@ -12624,7 +12636,7 @@ is_crtc_connector_off(struct drm_mode_set *set) static void intel_set_config_compute_mode_changes(struct drm_mode_set *set, - struct intel_set_config *config) + struct intel_crtc_state *pipe_config) { struct drm_device *dev = set->crtc->dev; struct intel_connector *connector; @@ -12634,7 +12646,7 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set, /* We should be able to check here if the fb has the same properties * and then just flip_or_move it */ if (is_crtc_connector_off(set)) { - config->mode_changed = true; + pipe_config->base.mode_changed = true; } else if (set->crtc->primary->fb != set->fb) { /* * If we have no fb, we can only flip as long as the crtc is @@ -12648,36 +12660,36 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set, if (intel_crtc->active) { DRM_DEBUG_KMS("crtc has no fb, will flip\n"); - config->fb_changed = true; + pipe_config->base.planes_changed = true; } else { DRM_DEBUG_KMS("inactive crtc, full mode set\n"); - config->mode_changed = true; + pipe_config->base.mode_changed = true; } } else if (set->fb == NULL) { - config->mode_changed = true; + pipe_config->base.mode_changed = true; } else if (set->fb->pixel_format != set->crtc->primary->fb->pixel_format) { - config->mode_changed = true; + pipe_config->base.mode_changed = true; } else { - config->fb_changed = true; + pipe_config->base.planes_changed = true; } } if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) - config->fb_changed = true; + pipe_config->base.planes_changed = true; if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { DRM_DEBUG_KMS("modes are different, full mode set\n"); drm_mode_debug_printmodeline(&set->crtc->mode); drm_mode_debug_printmodeline(set->mode); - config->mode_changed = true; + pipe_config->base.mode_changed = true; } for_each_intel_connector(dev, connector) { if (&connector->new_encoder->base == connector->base.encoder) continue; - config->mode_changed = true; + pipe_config->base.mode_changed = true; DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", connector->base.base.id, connector->base.name); @@ -12690,7 +12702,7 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set, DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", encoder->base.base.id, encoder->base.name); - config->mode_changed = true; + pipe_config->base.mode_changed = true; } for_each_intel_crtc(dev, crtc) { @@ -12700,11 +12712,12 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set, DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", crtc->base.base.id, crtc->new_enabled ? "en" : "dis"); - config->mode_changed = true; + pipe_config->base.mode_changed = true; } DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", - set->crtc->base.id, config->mode_changed, config->fb_changed); + set->crtc->base.id, pipe_config->base.mode_changed, + pipe_config->base.planes_changed); } static int @@ -12888,36 +12901,25 @@ static int intel_crtc_set_config(struct drm_mode_set *set) if (ret) goto fail; - /* Compute whether we need a full modeset, only an fb base update or no - * change at all. In the future we might also check whether only the - * mode changed, e.g. for LVDS where we only change the panel fitter in - * such cases. */ - intel_set_config_compute_mode_changes(set, config); - pipe_config = intel_modeset_compute_config(set->crtc, set->mode, state); if (IS_ERR(pipe_config)) { ret = PTR_ERR(pipe_config); goto fail; - } else if (pipe_config) { - if (pipe_config->has_audio != - to_intel_crtc(set->crtc)->config->has_audio) - config->mode_changed = true; - - /* - * Note we have an issue here with infoframes: current code - * only updates them on the full mode set path per hw - * requirements. So here we should be checking for any - * required changes and forcing a mode set. - */ } + /* Compute whether we need a full modeset, only an fb base update or no + * change at all. In the future we might also check whether only the + * mode changed, e.g. for LVDS where we only change the panel fitter in + * such cases. */ + intel_set_config_compute_mode_changes(set, pipe_config); + intel_update_pipe_size(to_intel_crtc(set->crtc)); - if (config->mode_changed) { + if (pipe_config->base.mode_changed) { ret = intel_set_mode_with_config(set->crtc, set->mode, pipe_config); - } else if (config->fb_changed) { + } else if (pipe_config->base.planes_changed) { struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); struct drm_plane *primary = set->crtc->primary; struct intel_plane_state *plane_state = -- cgit v1.2.3 From 41227c8c52bccef5ceb86b2ab1a2ffc4be04c44e Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:12 +0300 Subject: drm/i915: Don't use staged config to calculate mode_changed flags Use the atomic state instead. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 49 ++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fe9f545412ec..fea807ce77d3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12638,10 +12638,12 @@ static void intel_set_config_compute_mode_changes(struct drm_mode_set *set, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = set->crtc->dev; - struct intel_connector *connector; - struct intel_encoder *encoder; - struct intel_crtc *crtc; + struct drm_atomic_state *state; + struct drm_connector *connector; + struct drm_connector_state *connector_state; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; + int i; /* We should be able to check here if the fb has the same properties * and then just flip_or_move it */ @@ -12685,33 +12687,32 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set, pipe_config->base.mode_changed = true; } - for_each_intel_connector(dev, connector) { - if (&connector->new_encoder->base == connector->base.encoder) - continue; - - pipe_config->base.mode_changed = true; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", - connector->base.base.id, - connector->base.name); - } + state = pipe_config->base.state; - for_each_intel_encoder(dev, encoder) { - if (&encoder->new_crtc->base == encoder->base.crtc) - continue; + for_each_connector_in_state(state, connector, connector_state, i) { + if (connector_state->best_encoder != + connector->state->best_encoder) { + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", + connector->base.id, + connector->name); + pipe_config->base.mode_changed = true; + } - DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", - encoder->base.base.id, - encoder->base.name); - pipe_config->base.mode_changed = true; + if (connector_state->crtc != connector->state->crtc) { + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] crtc changed, full mode switch\n", + connector->base.id, + connector->name); + pipe_config->base.mode_changed = true; + } } - for_each_intel_crtc(dev, crtc) { - if (crtc->new_enabled == crtc->base.state->enable) + for_each_crtc_in_state(state, crtc, crtc_state, i) { + if (crtc_state->enable == crtc->state->enable) continue; DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", - crtc->base.base.id, - crtc->new_enabled ? "en" : "dis"); + crtc->base.id, + crtc_state->enable ? "en" : "dis"); pipe_config->base.mode_changed = true; } -- cgit v1.2.3 From bb54662350662815b4bfc2ff4464330a2dbd7041 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:13 +0300 Subject: drm/i915: Unify modeset and flip paths of intel_crtc_set_config() Call intel_set_mode() uncondionally from intel_crtc_set_config(), since the former function is now properly wired to ignore all the modesets if the mode_changed and active_changed flags are false in crtc_state. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 37 +++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fea807ce77d3..d1f737a8ad9e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12850,12 +12850,21 @@ intel_modeset_stage_output_state(struct drm_device *dev, return 0; } +static bool primary_plane_visible(struct drm_crtc *crtc) +{ + struct intel_plane_state *plane_state = + to_intel_plane_state(crtc->primary->state); + + return plane_state->visible; +} + static int intel_crtc_set_config(struct drm_mode_set *set) { struct drm_device *dev; struct drm_atomic_state *state = NULL; struct intel_set_config *config; struct intel_crtc_state *pipe_config; + bool primary_plane_was_visible; int ret; BUG_ON(!set); @@ -12917,29 +12926,23 @@ static int intel_crtc_set_config(struct drm_mode_set *set) intel_update_pipe_size(to_intel_crtc(set->crtc)); - if (pipe_config->base.mode_changed) { - ret = intel_set_mode_with_config(set->crtc, set->mode, - pipe_config); - } else if (pipe_config->base.planes_changed) { + primary_plane_was_visible = primary_plane_visible(set->crtc); + + ret = intel_set_mode_with_config(set->crtc, set->mode, + pipe_config); + + if (ret == 0 && + pipe_config->base.enable && + pipe_config->base.planes_changed && + !needs_modeset(&pipe_config->base)) { struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); - struct drm_plane *primary = set->crtc->primary; - struct intel_plane_state *plane_state = - to_intel_plane_state(primary->state); - bool was_visible = plane_state->visible; - int vdisplay, hdisplay; - - drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); - ret = drm_plane_helper_update(primary, set->crtc, set->fb, - 0, 0, hdisplay, vdisplay, - set->x << 16, set->y << 16, - hdisplay << 16, vdisplay << 16); /* * We need to make sure the primary plane is re-enabled if it * has previously been turned off. */ - plane_state = to_intel_plane_state(primary->state); - if (ret == 0 && !was_visible && plane_state->visible) { + if (ret == 0 && !primary_plane_was_visible && + primary_plane_visible(set->crtc)) { WARN_ON(!intel_crtc->active); intel_post_enable_primary(set->crtc); } -- cgit v1.2.3 From b78852646450f3cb1e0677c1ae8a56875dd22562 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:14 +0300 Subject: drm/i915: Simplify intel_set_config_compute_mode_changes() a bit Add a helper function to make the code slightly more readable. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 44 ++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d1f737a8ad9e..20c0b94b8fcb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12721,6 +12721,18 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set, pipe_config->base.planes_changed); } +static bool intel_connector_in_mode_set(struct intel_connector *connector, + struct drm_mode_set *set) +{ + int ro; + + for (ro = 0; ro < set->num_connectors; ro++) + if (set->connectors[ro] == &connector->base) + return true; + + return false; +} + static int intel_modeset_stage_output_state(struct drm_device *dev, struct drm_mode_set *set, @@ -12731,7 +12743,6 @@ intel_modeset_stage_output_state(struct drm_device *dev, struct intel_encoder *encoder; struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; - int ro; /* The upper layers ensure that we either disable a crtc or have a list * of connectors. For paranoia, double-check this. */ @@ -12739,21 +12750,22 @@ intel_modeset_stage_output_state(struct drm_device *dev, WARN_ON(set->fb && (set->num_connectors == 0)); for_each_intel_connector(dev, connector) { - /* Otherwise traverse passed in connector list and get encoders - * for them. */ - for (ro = 0; ro < set->num_connectors; ro++) { - if (set->connectors[ro] == &connector->base) { - connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); - break; - } + bool in_mode_set = intel_connector_in_mode_set(connector, set); + + if (in_mode_set) { + int pipe = to_intel_crtc(set->crtc)->pipe; + connector->new_encoder = + intel_find_encoder(connector, pipe); } + if (!connector->base.encoder || + connector->base.encoder->crtc != set->crtc) + continue; + /* If we disable the crtc, disable all its connectors. Also, if * the connector is on the changing crtc but not on the new * connector list, disable it. */ - if ((!set->fb || ro == set->num_connectors) && - connector->base.encoder && - connector->base.encoder->crtc == set->crtc) { + if (!set->fb || !in_mode_set) { connector->new_encoder = NULL; DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", @@ -12770,12 +12782,10 @@ intel_modeset_stage_output_state(struct drm_device *dev, if (!connector->new_encoder) continue; - new_crtc = connector->new_encoder->base.crtc; - - for (ro = 0; ro < set->num_connectors; ro++) { - if (set->connectors[ro] == &connector->base) - new_crtc = set->crtc; - } + if (intel_connector_in_mode_set(connector, set)) + new_crtc = set->crtc; + else + new_crtc = connector->new_encoder->base.crtc; /* Make sure the new CRTC will work with the encoder */ if (!drm_encoder_crtc_ok(&connector->new_encoder->base, -- cgit v1.2.3 From d5432a9d19b61ba6a2b3d88f3026e0ca60eb57a1 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:15 +0300 Subject: drm/i915: Stage new modeset state straight into atomic state The logic that stages the state before the modeset was still updating first the old staged config and then populating the atomic state based on that. Change this to use only the atomic state. Note that now the staged config is updated in the function intel_modeset_commit_output_state(). This is done so that the modeset check and the force restore path in the hw state read out code continue to work. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 170 +++++++++++++++++------------------ 1 file changed, 85 insertions(+), 85 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 20c0b94b8fcb..80555800f5f4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11152,27 +11152,47 @@ static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) * intel_modeset_commit_output_state * * This function copies the stage display pipe configuration to the real one. + * + * FIXME: we want to replace this with a proper state swap in the future */ -static void intel_modeset_commit_output_state(struct drm_device *dev) +static void intel_modeset_commit_output_state(struct drm_atomic_state *state) { - struct intel_crtc *crtc; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; + struct drm_connector *connector; + struct drm_connector_state *connector_state; struct intel_encoder *encoder; - struct intel_connector *connector; + struct intel_connector *intel_connector; + int i; - for_each_intel_connector(dev, connector) { - connector->base.encoder = &connector->new_encoder->base; + for_each_connector_in_state(state, connector, connector_state, i) { + *connector->state = *connector_state; + + connector->encoder = connector_state->best_encoder; + if (connector->encoder) + connector->encoder->crtc = connector_state->crtc; } - for_each_intel_encoder(dev, encoder) { - encoder->base.crtc = &encoder->new_crtc->base; + /* Update crtc of disabled encoders */ + for_each_intel_encoder(state->dev, encoder) { + int num_connectors = 0; + + for_each_intel_connector(state->dev, intel_connector) + if (intel_connector->base.encoder == &encoder->base) + num_connectors++; + + if (num_connectors == 0) + encoder->base.crtc = NULL; } - for_each_intel_crtc(dev, crtc) { - crtc->base.state->enable = crtc->new_enabled; - crtc->base.enabled = crtc->new_enabled; + for_each_crtc_in_state(state, crtc, crtc_state, i) { + crtc->state->enable = crtc_state->enable; + crtc->enabled = crtc_state->enable; } - intel_modeset_update_connector_atomic_state(dev); + /* Copy the new configuration to the staged state, to keep the few + * pieces of code that haven't been converted yet happy */ + intel_modeset_update_staged_output_state(state->dev); } static void @@ -11622,7 +11642,7 @@ intel_modeset_update_state(struct drm_atomic_state *state) intel_encoder->connectors_active = false; } - intel_modeset_commit_output_state(dev); + intel_modeset_commit_output_state(state); /* Double check state. */ for_each_crtc(dev, crtc) { @@ -12739,10 +12759,11 @@ intel_modeset_stage_output_state(struct drm_device *dev, struct drm_atomic_state *state) { struct intel_connector *connector; + struct drm_connector *drm_connector; struct drm_connector_state *connector_state; - struct intel_encoder *encoder; - struct intel_crtc *crtc; - struct intel_crtc_state *crtc_state; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; + int i, ret; /* The upper layers ensure that we either disable a crtc or have a list * of connectors. For paranoia, double-check this. */ @@ -12752,21 +12773,28 @@ intel_modeset_stage_output_state(struct drm_device *dev, for_each_intel_connector(dev, connector) { bool in_mode_set = intel_connector_in_mode_set(connector, set); + if (!in_mode_set && connector->base.state->crtc != set->crtc) + continue; + + connector_state = + drm_atomic_get_connector_state(state, &connector->base); + if (IS_ERR(connector_state)) + return PTR_ERR(connector_state); + if (in_mode_set) { int pipe = to_intel_crtc(set->crtc)->pipe; - connector->new_encoder = - intel_find_encoder(connector, pipe); + connector_state->best_encoder = + &intel_find_encoder(connector, pipe)->base; } - if (!connector->base.encoder || - connector->base.encoder->crtc != set->crtc) + if (connector->base.state->crtc != set->crtc) continue; /* If we disable the crtc, disable all its connectors. Also, if * the connector is on the changing crtc but not on the new * connector list, disable it. */ if (!set->fb || !in_mode_set) { - connector->new_encoder = NULL; + connector_state->best_encoder = NULL; DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", connector->base.base.id, @@ -12775,86 +12803,58 @@ intel_modeset_stage_output_state(struct drm_device *dev, } /* connector->new_encoder is now updated for all connectors. */ - /* Update crtc of enabled connectors. */ - for_each_intel_connector(dev, connector) { - struct drm_crtc *new_crtc; + for_each_connector_in_state(state, drm_connector, connector_state, i) { + connector = to_intel_connector(drm_connector); + + if (!connector_state->best_encoder) { + ret = drm_atomic_set_crtc_for_connector(connector_state, + NULL); + if (ret) + return ret; - if (!connector->new_encoder) continue; + } - if (intel_connector_in_mode_set(connector, set)) - new_crtc = set->crtc; - else - new_crtc = connector->new_encoder->base.crtc; + if (intel_connector_in_mode_set(connector, set)) { + struct drm_crtc *crtc = connector->base.state->crtc; + + /* If this connector was in a previous crtc, add it + * to the state. We might need to disable it. */ + if (crtc) { + crtc_state = + drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } + + ret = drm_atomic_set_crtc_for_connector(connector_state, + set->crtc); + if (ret) + return ret; + } /* Make sure the new CRTC will work with the encoder */ - if (!drm_encoder_crtc_ok(&connector->new_encoder->base, - new_crtc)) { + if (!drm_encoder_crtc_ok(connector_state->best_encoder, + connector_state->crtc)) { return -EINVAL; } - connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); - - connector_state = - drm_atomic_get_connector_state(state, &connector->base); - if (IS_ERR(connector_state)) - return PTR_ERR(connector_state); - - connector_state->crtc = new_crtc; - connector_state->best_encoder = &connector->new_encoder->base; DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", connector->base.base.id, connector->base.name, - new_crtc->base.id); - } - - /* Check for any encoders that needs to be disabled. */ - for_each_intel_encoder(dev, encoder) { - int num_connectors = 0; - for_each_intel_connector(dev, connector) { - if (connector->new_encoder == encoder) { - WARN_ON(!connector->new_encoder->new_crtc); - num_connectors++; - } - } - - if (num_connectors == 0) - encoder->new_crtc = NULL; - else if (num_connectors > 1) - return -EINVAL; - } - /* Now we've also updated encoder->new_crtc for all encoders. */ - for_each_intel_connector(dev, connector) { - connector_state = - drm_atomic_get_connector_state(state, &connector->base); - if (IS_ERR(connector_state)) - return PTR_ERR(connector_state); + connector_state->crtc->base.id); - if (connector->new_encoder) { - if (connector->new_encoder != connector->encoder) - connector->encoder = connector->new_encoder; - } else { - connector_state->crtc = NULL; - connector_state->best_encoder = NULL; - } + if (connector_state->best_encoder != &connector->encoder->base) + connector->encoder = + to_intel_encoder(connector_state->best_encoder); } - for_each_intel_crtc(dev, crtc) { - crtc->new_enabled = false; - - for_each_intel_encoder(dev, encoder) { - if (encoder->new_crtc == crtc) { - crtc->new_enabled = true; - break; - } - } - if (crtc->new_enabled != crtc->base.state->enable) { - crtc_state = intel_atomic_get_crtc_state(state, crtc); - if (IS_ERR(crtc_state)) - return PTR_ERR(crtc_state); + for_each_crtc_in_state(state, crtc, crtc_state, i) { + ret = drm_atomic_add_affected_connectors(state, crtc); + if (ret) + return ret; - crtc_state->base.enable = crtc->new_enabled; - } + crtc_state->enable = drm_atomic_connectors_for_crtc(state, crtc); } return 0; -- cgit v1.2.3 From 7cbf41d6105fe55074c03582831da72923d0874b Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:16 +0300 Subject: drm/i915: Remove save/restore logic from intel_crtc_set_config() This is no longer necessary since we only update the staged config on successfull modeset. The new configuration is stored in an atomic state struct which is freed in case of failure. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 113 ++--------------------------------- drivers/gpu/drm/i915/intel_drv.h | 9 --- 2 files changed, 6 insertions(+), 116 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 80555800f5f4..210e7c4f881b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12549,91 +12549,6 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc) #undef for_each_intel_crtc_masked -static void intel_set_config_free(struct intel_set_config *config) -{ - if (!config) - return; - - kfree(config->save_connector_encoders); - kfree(config->save_encoder_crtcs); - kfree(config->save_crtc_enabled); - kfree(config); -} - -static int intel_set_config_save_state(struct drm_device *dev, - struct intel_set_config *config) -{ - struct drm_crtc *crtc; - struct drm_encoder *encoder; - struct drm_connector *connector; - int count; - - config->save_crtc_enabled = - kcalloc(dev->mode_config.num_crtc, - sizeof(bool), GFP_KERNEL); - if (!config->save_crtc_enabled) - return -ENOMEM; - - config->save_encoder_crtcs = - kcalloc(dev->mode_config.num_encoder, - sizeof(struct drm_crtc *), GFP_KERNEL); - if (!config->save_encoder_crtcs) - return -ENOMEM; - - config->save_connector_encoders = - kcalloc(dev->mode_config.num_connector, - sizeof(struct drm_encoder *), GFP_KERNEL); - if (!config->save_connector_encoders) - return -ENOMEM; - - /* Copy data. Note that driver private data is not affected. - * Should anything bad happen only the expected state is - * restored, not the drivers personal bookkeeping. - */ - count = 0; - for_each_crtc(dev, crtc) { - config->save_crtc_enabled[count++] = crtc->state->enable; - } - - count = 0; - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - config->save_encoder_crtcs[count++] = encoder->crtc; - } - - count = 0; - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - config->save_connector_encoders[count++] = connector->encoder; - } - - return 0; -} - -static void intel_set_config_restore_state(struct drm_device *dev, - struct intel_set_config *config) -{ - struct intel_crtc *crtc; - struct intel_encoder *encoder; - struct intel_connector *connector; - int count; - - count = 0; - for_each_intel_crtc(dev, crtc) { - crtc->new_enabled = config->save_crtc_enabled[count++]; - } - - count = 0; - for_each_intel_encoder(dev, encoder) { - encoder->new_crtc = - to_intel_crtc(config->save_encoder_crtcs[count++]); - } - - count = 0; - for_each_intel_connector(dev, connector) { - connector->new_encoder = - to_intel_encoder(config->save_connector_encoders[count++]); - } -} - static bool is_crtc_connector_off(struct drm_mode_set *set) { @@ -12872,7 +12787,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set) { struct drm_device *dev; struct drm_atomic_state *state = NULL; - struct intel_set_config *config; struct intel_crtc_state *pipe_config; bool primary_plane_was_visible; int ret; @@ -12895,37 +12809,26 @@ static int intel_crtc_set_config(struct drm_mode_set *set) dev = set->crtc->dev; - ret = -ENOMEM; - config = kzalloc(sizeof(*config), GFP_KERNEL); - if (!config) - goto out_config; - - ret = intel_set_config_save_state(dev, config); - if (ret) - goto out_config; - state = drm_atomic_state_alloc(dev); - if (!state) { - ret = -ENOMEM; - goto out_config; - } + if (!state) + return -ENOMEM; state->acquire_ctx = dev->mode_config.acquire_ctx; ret = intel_modeset_stage_output_state(dev, set, state); if (ret) - goto fail; + goto out; ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode, set->fb, set->x, set->y); if (ret) - goto fail; + goto out; pipe_config = intel_modeset_compute_config(set->crtc, set->mode, state); if (IS_ERR(pipe_config)) { ret = PTR_ERR(pipe_config); - goto fail; + goto out; } /* Compute whether we need a full modeset, only an fb base update or no @@ -12972,14 +12875,10 @@ static int intel_crtc_set_config(struct drm_mode_set *set) if (ret) { DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", set->crtc->base.id, ret); -fail: - intel_set_config_restore_state(dev, config); } -out_config: +out: drm_atomic_state_free(state); - - intel_set_config_free(config); return ret; } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 6fe36ddbb42f..930ea6916d9f 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -813,15 +813,6 @@ struct intel_unpin_work { bool enable_stall_check; }; -struct intel_set_config { - struct drm_encoder **save_connector_encoders; - struct drm_crtc **save_encoder_crtcs; - bool *save_crtc_enabled; - - bool fb_changed; - bool mode_changed; -}; - struct intel_load_detect_pipe { struct drm_framebuffer *release_fb; bool load_detect_temp; -- cgit v1.2.3 From 0f63cca2afdc38877e86acfa9821020f6e2213fd Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:17 +0300 Subject: drm/i915: Update crtc state active flag based on DPMS In a follow up patch the function that computes mode changes will be replaced with the one from the atomic helpers. To preserve the behavior of legacy modeset forcing DPMS on, that function will need to detect a change in the active state of the crtc, so that has to be kept up to date. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 210e7c4f881b..44b3b5a7ad34 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6107,6 +6107,8 @@ void intel_crtc_update_dpms(struct drm_crtc *crtc) enable |= intel_encoder->connectors_active; intel_crtc_control(crtc, enable); + + crtc->state->active = enable; } static void intel_crtc_disable(struct drm_crtc *crtc) -- cgit v1.2.3 From 840bfe953384a134c8639f2964d9b74bfa671e16 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:18 +0300 Subject: drm/atomic: Make mode_fixup() optional for check_modeset() So the i915 driver can use the same logic for setting mode and active changed flags, without having to implement encoder helpers and the mode_fixup() callback. Cc: dri-devel@lists.freedestkop.org Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Acked-by: Dave Airlie Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic_helper.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 5d30592c83cd..5e68c3c7d5cf 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -280,6 +280,8 @@ mode_fixup(struct drm_atomic_state *state) */ encoder = conn_state->best_encoder; funcs = encoder->helper_private; + if (!funcs) + continue; if (encoder->bridge && encoder->bridge->funcs->mode_fixup) { ret = encoder->bridge->funcs->mode_fixup( @@ -317,6 +319,9 @@ mode_fixup(struct drm_atomic_state *state) continue; funcs = crtc->helper_private; + if (!funcs->mode_fixup) + continue; + ret = funcs->mode_fixup(crtc, &crtc_state->mode, &crtc_state->adjusted_mode); if (!ret) { -- cgit v1.2.3 From 8c7b5ccb729870e606321b3703e2c2e698c49a95 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:19 +0300 Subject: drm/i915: Use atomic helpers for computing changed flags Replace the drivers own logic for computing mode_changed, active_changed and planes_changed flags with the check_modeset() atomic helper. Since that function needs to compare the crtc's new mode with the current, this patch also moves the set up of crtc_state->mode earlier in the call chain. Note that for the call to check_plane() to work properly, we need to check new plane state against new crtc state. But since we still use the plane update helper, which doesn't have a full atomic state, we need to hack around that in intel_plane_atomic_check(). Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_atomic_plane.c | 16 ++- drivers/gpu/drm/i915/intel_display.c | 197 ++++++------------------------ 2 files changed, 52 insertions(+), 161 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index 77462e1360bc..86ba4b2c3a65 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -111,6 +111,7 @@ static int intel_plane_atomic_check(struct drm_plane *plane, { struct drm_crtc *crtc = state->crtc; struct intel_crtc *intel_crtc; + struct intel_crtc_state *crtc_state; struct intel_plane *intel_plane = to_intel_plane(plane); struct intel_plane_state *intel_state = to_intel_plane_state(state); @@ -126,6 +127,17 @@ static int intel_plane_atomic_check(struct drm_plane *plane, if (!crtc) return 0; + /* FIXME: temporary hack necessary while we still use the plane update + * helper. */ + if (state->state) { + crtc_state = + intel_atomic_get_crtc_state(state->state, intel_crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } else { + crtc_state = intel_crtc->config; + } + /* * The original src/dest coordinates are stored in state->base, but * we want to keep another copy internal to our driver that we can @@ -144,9 +156,9 @@ static int intel_plane_atomic_check(struct drm_plane *plane, intel_state->clip.x1 = 0; intel_state->clip.y1 = 0; intel_state->clip.x2 = - intel_crtc->active ? intel_crtc->config->pipe_src_w : 0; + crtc_state->base.active ? crtc_state->pipe_src_w : 0; intel_state->clip.y2 = - intel_crtc->active ? intel_crtc->config->pipe_src_h : 0; + crtc_state->base.active ? crtc_state->pipe_src_h : 0; /* * Disabling a plane is always okay; we just need to update diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 44b3b5a7ad34..db450772b4a5 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -82,7 +82,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, static void ironlake_pch_clock_get(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); -static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, +static int intel_set_mode(struct drm_crtc *crtc, struct drm_atomic_state *state); static int intel_framebuffer_init(struct drm_device *dev, struct intel_framebuffer *ifb, @@ -9892,7 +9892,9 @@ retry: if (ret) goto fail; - if (intel_set_mode(crtc, mode, state)) { + drm_mode_copy(&crtc_state->base.mode, mode); + + if (intel_set_mode(crtc, state)) { DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); if (old->release_fb) old->release_fb->funcs->destroy(old->release_fb); @@ -9966,7 +9968,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, if (ret) goto fail; - intel_set_mode(crtc, NULL, state); + intel_set_mode(crtc, state); drm_atomic_state_free(state); @@ -11476,7 +11478,6 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) static int intel_modeset_pipe_config(struct drm_crtc *crtc, - struct drm_display_mode *mode, struct drm_atomic_state *state, struct intel_crtc_state *pipe_config) { @@ -11499,10 +11500,6 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, clear_intel_crtc_state(pipe_config); - pipe_config->base.crtc = crtc; - drm_mode_copy(&pipe_config->base.adjusted_mode, mode); - drm_mode_copy(&pipe_config->base.mode, mode); - pipe_config->cpu_transcoder = (enum transcoder) to_intel_crtc(crtc)->pipe; pipe_config->shared_dpll = DPLL_ID_PRIVATE; @@ -12199,27 +12196,8 @@ static void update_scanline_offset(struct intel_crtc *crtc) crtc->scanline_offset = 1; } -static void -intel_atomic_modeset_compute_changed_flags(struct drm_atomic_state *state, - struct drm_crtc *modeset_crtc) -{ - struct drm_crtc_state *crtc_state; - struct drm_crtc *crtc; - int i; - - for_each_crtc_in_state(state, crtc, crtc_state, i) { - if (crtc_state->enable != crtc->state->enable) - crtc_state->mode_changed = true; - - /* FIXME: Do we need to always set mode_changed for - * modeset_crtc if it is enabled? modeset_affect_pipes() - * did that. */ - } -} - static struct intel_crtc_state * intel_modeset_compute_config(struct drm_crtc *crtc, - struct drm_display_mode *mode, struct drm_atomic_state *state) { struct intel_crtc_state *pipe_config; @@ -12229,7 +12207,9 @@ intel_modeset_compute_config(struct drm_crtc *crtc, if (ret) return ERR_PTR(ret); - intel_atomic_modeset_compute_changed_flags(state, crtc); + ret = drm_atomic_helper_check_modeset(state->dev, state); + if (ret) + return ERR_PTR(ret); /* * Note this needs changes when we start tracking multiple modes @@ -12244,7 +12224,7 @@ intel_modeset_compute_config(struct drm_crtc *crtc, if (!pipe_config->base.enable) return pipe_config; - ret = intel_modeset_pipe_config(crtc, mode, state, pipe_config); + ret = intel_modeset_pipe_config(crtc, state, pipe_config); if (ret) return ERR_PTR(ret); @@ -12262,6 +12242,10 @@ intel_modeset_compute_config(struct drm_crtc *crtc, intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]"); + ret = drm_atomic_helper_check_planes(state->dev, state); + if (ret) + return ERR_PTR(ret); + return pipe_config; } @@ -12337,7 +12321,6 @@ static int __intel_set_mode_checks(struct drm_atomic_state *state) } static int __intel_set_mode(struct drm_crtc *modeset_crtc, - struct drm_display_mode *mode, struct intel_crtc_state *pipe_config) { struct drm_device *dev = modeset_crtc->dev; @@ -12380,7 +12363,7 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, * single crtc and mode. */ if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) { - modeset_crtc->mode = *mode; + modeset_crtc->mode = pipe_config->base.mode; /* mode_set/enable/disable functions rely on a correct pipe * config. */ intel_crtc_set_state(to_intel_crtc(modeset_crtc), pipe_config); @@ -12446,12 +12429,11 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, } static int intel_set_mode_with_config(struct drm_crtc *crtc, - struct drm_display_mode *mode, struct intel_crtc_state *pipe_config) { int ret; - ret = __intel_set_mode(crtc, mode, pipe_config); + ret = __intel_set_mode(crtc, pipe_config); if (ret == 0) intel_modeset_check_state(crtc->dev); @@ -12460,19 +12442,18 @@ static int intel_set_mode_with_config(struct drm_crtc *crtc, } static int intel_set_mode(struct drm_crtc *crtc, - struct drm_display_mode *mode, struct drm_atomic_state *state) { struct intel_crtc_state *pipe_config; int ret = 0; - pipe_config = intel_modeset_compute_config(crtc, mode, state); + pipe_config = intel_modeset_compute_config(crtc, state); if (IS_ERR(pipe_config)) { ret = PTR_ERR(pipe_config); goto out; } - ret = intel_set_mode_with_config(crtc, mode, pipe_config); + ret = intel_set_mode_with_config(crtc, pipe_config); if (ret) goto out; @@ -12539,125 +12520,21 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc) } crtc_state->base.enable = intel_crtc->new_enabled; + + if (&intel_crtc->base == crtc) + drm_mode_copy(&crtc_state->base.mode, &crtc->mode); } intel_modeset_setup_plane_state(state, crtc, &crtc->mode, crtc->primary->fb, crtc->x, crtc->y); - intel_set_mode(crtc, &crtc->mode, state); + intel_set_mode(crtc, state); drm_atomic_state_free(state); } #undef for_each_intel_crtc_masked -static bool -is_crtc_connector_off(struct drm_mode_set *set) -{ - int i; - - if (set->num_connectors == 0) - return false; - - if (WARN_ON(set->connectors == NULL)) - return false; - - for (i = 0; i < set->num_connectors; i++) - if (set->connectors[i]->encoder && - set->connectors[i]->encoder->crtc == set->crtc && - set->connectors[i]->dpms != DRM_MODE_DPMS_ON) - return true; - - return false; -} - -static void -intel_set_config_compute_mode_changes(struct drm_mode_set *set, - struct intel_crtc_state *pipe_config) -{ - struct drm_atomic_state *state; - struct drm_connector *connector; - struct drm_connector_state *connector_state; - struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; - int i; - - /* We should be able to check here if the fb has the same properties - * and then just flip_or_move it */ - if (is_crtc_connector_off(set)) { - pipe_config->base.mode_changed = true; - } else if (set->crtc->primary->fb != set->fb) { - /* - * If we have no fb, we can only flip as long as the crtc is - * active, otherwise we need a full mode set. The crtc may - * be active if we've only disabled the primary plane, or - * in fastboot situations. - */ - if (set->crtc->primary->fb == NULL) { - struct intel_crtc *intel_crtc = - to_intel_crtc(set->crtc); - - if (intel_crtc->active) { - DRM_DEBUG_KMS("crtc has no fb, will flip\n"); - pipe_config->base.planes_changed = true; - } else { - DRM_DEBUG_KMS("inactive crtc, full mode set\n"); - pipe_config->base.mode_changed = true; - } - } else if (set->fb == NULL) { - pipe_config->base.mode_changed = true; - } else if (set->fb->pixel_format != - set->crtc->primary->fb->pixel_format) { - pipe_config->base.mode_changed = true; - } else { - pipe_config->base.planes_changed = true; - } - } - - if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) - pipe_config->base.planes_changed = true; - - if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { - DRM_DEBUG_KMS("modes are different, full mode set\n"); - drm_mode_debug_printmodeline(&set->crtc->mode); - drm_mode_debug_printmodeline(set->mode); - pipe_config->base.mode_changed = true; - } - - state = pipe_config->base.state; - - for_each_connector_in_state(state, connector, connector_state, i) { - if (connector_state->best_encoder != - connector->state->best_encoder) { - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", - connector->base.id, - connector->name); - pipe_config->base.mode_changed = true; - } - - if (connector_state->crtc != connector->state->crtc) { - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] crtc changed, full mode switch\n", - connector->base.id, - connector->name); - pipe_config->base.mode_changed = true; - } - } - - for_each_crtc_in_state(state, crtc, crtc_state, i) { - if (crtc_state->enable == crtc->state->enable) - continue; - - DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", - crtc->base.id, - crtc_state->enable ? "en" : "dis"); - pipe_config->base.mode_changed = true; - } - - DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", - set->crtc->base.id, pipe_config->base.mode_changed, - pipe_config->base.planes_changed); -} - static bool intel_connector_in_mode_set(struct intel_connector *connector, struct drm_mode_set *set) { @@ -12774,6 +12651,21 @@ intel_modeset_stage_output_state(struct drm_device *dev, crtc_state->enable = drm_atomic_connectors_for_crtc(state, crtc); } + ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode, + set->fb, set->x, set->y); + if (ret) + return ret; + + crtc_state = drm_atomic_get_crtc_state(state, set->crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + if (set->mode) + drm_mode_copy(&crtc_state->mode, set->mode); + + if (set->num_connectors) + crtc_state->active = true; + return 0; } @@ -12821,30 +12713,17 @@ static int intel_crtc_set_config(struct drm_mode_set *set) if (ret) goto out; - ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode, - set->fb, set->x, set->y); - if (ret) - goto out; - - pipe_config = intel_modeset_compute_config(set->crtc, set->mode, - state); + pipe_config = intel_modeset_compute_config(set->crtc, state); if (IS_ERR(pipe_config)) { ret = PTR_ERR(pipe_config); goto out; } - /* Compute whether we need a full modeset, only an fb base update or no - * change at all. In the future we might also check whether only the - * mode changed, e.g. for LVDS where we only change the panel fitter in - * such cases. */ - intel_set_config_compute_mode_changes(set, pipe_config); - intel_update_pipe_size(to_intel_crtc(set->crtc)); primary_plane_was_visible = primary_plane_visible(set->crtc); - ret = intel_set_mode_with_config(set->crtc, set->mode, - pipe_config); + ret = intel_set_mode_with_config(set->crtc, pipe_config); if (ret == 0 && pipe_config->base.enable && -- cgit v1.2.3 From 2bfb4627580ae91d2978e1c071ed1a4b5039f2fd Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:20 +0300 Subject: drm/i915: Take ownership of atomic state on success in intel_set_mode() To match the behavior of ->atomic_commit(). Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index db450772b4a5..e3e4a04a18bf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9968,9 +9968,9 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, if (ret) goto fail; - intel_set_mode(crtc, state); - - drm_atomic_state_free(state); + ret = intel_set_mode(crtc, state); + if (ret) + goto fail; if (old->release_fb) { drm_framebuffer_unregister_private(old->release_fb); @@ -12425,6 +12425,8 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, intel_crtc->config = crtc_state_copy; intel_crtc->base.state = &crtc_state_copy->base; + drm_atomic_state_free(state); + return 0; } @@ -12470,6 +12472,7 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc) struct intel_connector *connector; struct drm_connector_state *connector_state; struct intel_crtc_state *crtc_state; + int ret; state = drm_atomic_state_alloc(dev); if (!state) { @@ -12528,9 +12531,9 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc) intel_modeset_setup_plane_state(state, crtc, &crtc->mode, crtc->primary->fb, crtc->x, crtc->y); - intel_set_mode(crtc, state); - - drm_atomic_state_free(state); + ret = intel_set_mode(crtc, state); + if (ret) + drm_atomic_state_free(state); } #undef for_each_intel_crtc_masked @@ -12759,7 +12762,8 @@ static int intel_crtc_set_config(struct drm_mode_set *set) } out: - drm_atomic_state_free(state); + if (ret) + drm_atomic_state_free(state); return ret; } -- cgit v1.2.3 From 4978cc93d9ac240b435ce60431aef24239b4c270 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:21 +0300 Subject: drm/i915: Preserve shared DPLL information in new pipe_config When a new pipe_config is calculated, the fields related to shared dplls are reset, under the assumption that they will be recalculated as part of the modeset, which is true with the current state of the code. As we convert to atomic, however, it will be possible to calculate a new pipe_config and skip the modeset. In that case, after the state swap we still want the shared dplls to be preserved. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e3e4a04a18bf..b392ce3dd6c1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11467,13 +11467,21 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) { struct drm_crtc_state tmp_state; struct intel_crtc_scaler_state scaler_state; + struct intel_dpll_hw_state dpll_hw_state; + enum intel_dpll_id shared_dpll; /* Clear only the intel specific part of the crtc state excluding scalers */ tmp_state = crtc_state->base; scaler_state = crtc_state->scaler_state; + shared_dpll = crtc_state->shared_dpll; + dpll_hw_state = crtc_state->dpll_hw_state; + memset(crtc_state, 0, sizeof *crtc_state); + crtc_state->base = tmp_state; crtc_state->scaler_state = scaler_state; + crtc_state->shared_dpll = shared_dpll; + crtc_state->dpll_hw_state = dpll_hw_state; } static int @@ -11502,7 +11510,6 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, pipe_config->cpu_transcoder = (enum transcoder) to_intel_crtc(crtc)->pipe; - pipe_config->shared_dpll = DPLL_ID_PRIVATE; /* * Sanitize sync polarity flags based on requested ones. If neither @@ -12266,9 +12273,14 @@ static int __intel_set_mode_setup_plls(struct drm_atomic_state *state) for_each_crtc_in_state(state, crtc, crtc_state, i) { intel_crtc = to_intel_crtc(crtc); + intel_crtc_state = to_intel_crtc_state(crtc_state); - if (needs_modeset(crtc_state)) + if (needs_modeset(crtc_state)) { clear_pipes |= 1 << intel_crtc->pipe; + intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; + memset(&intel_crtc_state->dpll_hw_state, 0, + sizeof(intel_crtc_state->dpll_hw_state)); + } } ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); -- cgit v1.2.3 From d4afb8cc3a6a68fe2eddf027b80826d3b7f5b304 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:22 +0300 Subject: drm/i915: Don't use plane update helper in legacy mode set Use lower level calls to better integrate with the modeset code and allow a full state swap in a follow up patch. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 47 +++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b392ce3dd6c1..73cd69c53db2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12332,6 +12332,23 @@ static int __intel_set_mode_checks(struct drm_atomic_state *state) return 0; } +static void __intel_set_mode_swap_plane_state(struct drm_device *dev, + struct drm_atomic_state *state) +{ + int i; + + for (i = 0; i < dev->mode_config.num_total_plane; i++) { + struct drm_plane *plane = state->planes[i]; + + if (!plane) + continue; + + plane->state->state = state; + swap(state->plane_states[i], plane->state); + plane->state->state = NULL; + } +} + static int __intel_set_mode(struct drm_crtc *modeset_crtc, struct intel_crtc_state *pipe_config) { @@ -12342,8 +12359,6 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, struct intel_crtc *intel_crtc; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; - struct drm_plane *plane; - struct drm_plane_state *plane_state; int ret = 0; int i; @@ -12351,6 +12366,10 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, if (ret < 0) return ret; + ret = drm_atomic_helper_prepare_planes(dev, state); + if (ret) + return ret; + crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); if (!crtc_state_copy) return -ENOMEM; @@ -12395,26 +12414,8 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, modeset_update_crtc_power_domains(state); - for_each_plane_in_state(state, plane, plane_state, i) { - if (WARN_ON(plane != modeset_crtc->primary)) - continue; - - /* Primary plane is disabled in intel_crtc_disable() */ - if (!pipe_config->base.enable) - continue; - - ret = drm_plane_helper_update(plane, plane_state->crtc, - plane_state->fb, - plane_state->crtc_x, - plane_state->crtc_y, - plane_state->crtc_w, - plane_state->crtc_h, - plane_state->src_x, - plane_state->src_y, - plane_state->src_w, - plane_state->src_h); - WARN_ON(ret != 0); - } + __intel_set_mode_swap_plane_state(dev, state); + drm_atomic_helper_commit_planes(dev, state); /* Now enable the clocks, plane, pipe, and connectors that we set up. */ for_each_crtc_in_state(state, crtc, crtc_state, i) { @@ -12437,6 +12438,8 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, intel_crtc->config = crtc_state_copy; intel_crtc->base.state = &crtc_state_copy->base; + drm_atomic_helper_cleanup_planes(dev, state); + drm_atomic_state_free(state); return 0; -- cgit v1.2.3 From a821fc46bc7bb6d4cf9a5f8d2787fd70231c2c10 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:23 +0300 Subject: drm/i915: Swap atomic state in legacy modeset Replace the commit output state function with a simple swap of states. Note that we still need to reconcile the legacy state after the swap, since there are still code that relies on those. Also note that even though changes to the state of a crtc different than the one passed as an argument to __intel_set_mode() will be saved, the modeset logic still deals with only one crtc. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 117 ++++++++++++----------------------- 1 file changed, 39 insertions(+), 78 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 73cd69c53db2..e4983c19829e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5728,16 +5728,21 @@ static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, return 144000; } -/* compute the max pixel clock for new configuration */ -static int intel_mode_max_pixclk(struct drm_atomic_state *state) +/* Compute the max pixel clock for new configuration. Uses atomic state if + * that's non-NULL, look at current state otherwise. */ +static int intel_mode_max_pixclk(struct drm_device *dev, + struct drm_atomic_state *state) { - struct drm_device *dev = state->dev; struct intel_crtc *intel_crtc; struct intel_crtc_state *crtc_state; int max_pixclk = 0; for_each_intel_crtc(dev, intel_crtc) { - crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); + if (state) + crtc_state = + intel_atomic_get_crtc_state(state, intel_crtc); + else + crtc_state = intel_crtc->config; if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); @@ -5756,7 +5761,7 @@ static int valleyview_modeset_global_pipes(struct drm_atomic_state *state) struct drm_i915_private *dev_priv = to_i915(state->dev); struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; - int max_pixclk = intel_mode_max_pixclk(state); + int max_pixclk = intel_mode_max_pixclk(state->dev, state); int cdclk, i; if (max_pixclk < 0) @@ -5824,18 +5829,15 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); } -static void valleyview_modeset_global_resources(struct drm_atomic_state *state) +static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state) { - struct drm_device *dev = state->dev; + struct drm_device *dev = old_state->dev; struct drm_i915_private *dev_priv = dev->dev_private; - int max_pixclk = intel_mode_max_pixclk(state); + int max_pixclk = intel_mode_max_pixclk(dev, NULL); int req_cdclk; - /* The only reason this can fail is if we fail to add the crtc_state - * to the atomic state. But that can't happen since the call to - * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which - * can't have failed otherwise the mode set would be aborted) added all - * the states already. */ + /* The path in intel_mode_max_pixclk() with a NULL atomic state should + * never fail. */ if (WARN_ON(max_pixclk < 0)) return; @@ -9154,11 +9156,11 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv) intel_prepare_ddi(dev); } -static void broxton_modeset_global_resources(struct drm_atomic_state *state) +static void broxton_modeset_global_resources(struct drm_atomic_state *old_state) { - struct drm_device *dev = state->dev; + struct drm_device *dev = old_state->dev; struct drm_i915_private *dev_priv = dev->dev_private; - int max_pixclk = intel_mode_max_pixclk(state); + int max_pixclk = intel_mode_max_pixclk(dev, NULL); int req_cdclk; /* see the comment in valleyview_modeset_global_resources */ @@ -11152,46 +11154,36 @@ static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) } } -/** - * intel_modeset_commit_output_state - * - * This function copies the stage display pipe configuration to the real one. - * - * FIXME: we want to replace this with a proper state swap in the future +/* Fixup legacy state after an atomic state swap. */ -static void intel_modeset_commit_output_state(struct drm_atomic_state *state) +static void intel_modeset_fixup_state(struct drm_atomic_state *state) { - struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; - struct drm_connector *connector; - struct drm_connector_state *connector_state; + struct intel_crtc *crtc; struct intel_encoder *encoder; - struct intel_connector *intel_connector; - int i; - - for_each_connector_in_state(state, connector, connector_state, i) { - *connector->state = *connector_state; + struct intel_connector *connector; - connector->encoder = connector_state->best_encoder; - if (connector->encoder) - connector->encoder->crtc = connector_state->crtc; + for_each_intel_connector(state->dev, connector) { + connector->base.encoder = connector->base.state->best_encoder; + if (connector->base.encoder) + connector->base.encoder->crtc = + connector->base.state->crtc; } /* Update crtc of disabled encoders */ for_each_intel_encoder(state->dev, encoder) { int num_connectors = 0; - for_each_intel_connector(state->dev, intel_connector) - if (intel_connector->base.encoder == &encoder->base) + for_each_intel_connector(state->dev, connector) + if (connector->base.encoder == &encoder->base) num_connectors++; if (num_connectors == 0) encoder->base.crtc = NULL; } - for_each_crtc_in_state(state, crtc, crtc_state, i) { - crtc->state->enable = crtc_state->enable; - crtc->enabled = crtc_state->enable; + for_each_intel_crtc(state->dev, crtc) { + crtc->base.enabled = crtc->base.state->enable; + crtc->config = to_intel_crtc_state(crtc->base.state); } /* Copy the new configuration to the staged state, to keep the few @@ -11648,7 +11640,8 @@ intel_modeset_update_state(struct drm_atomic_state *state) intel_encoder->connectors_active = false; } - intel_modeset_commit_output_state(state); + drm_atomic_helper_swap_state(state->dev, state); + intel_modeset_fixup_state(state); /* Double check state. */ for_each_crtc(dev, crtc) { @@ -11666,7 +11659,7 @@ intel_modeset_update_state(struct drm_atomic_state *state) if (crtc != connector->encoder->crtc) continue; - if (crtc_state->enable && needs_modeset(crtc_state)) { + if (crtc->state->enable && needs_modeset(crtc->state)) { struct drm_property *dpms_property = dev->mode_config.dpms_property; @@ -12332,31 +12325,12 @@ static int __intel_set_mode_checks(struct drm_atomic_state *state) return 0; } -static void __intel_set_mode_swap_plane_state(struct drm_device *dev, - struct drm_atomic_state *state) -{ - int i; - - for (i = 0; i < dev->mode_config.num_total_plane; i++) { - struct drm_plane *plane = state->planes[i]; - - if (!plane) - continue; - - plane->state->state = state; - swap(state->plane_states[i], plane->state); - plane->state->state = NULL; - } -} - static int __intel_set_mode(struct drm_crtc *modeset_crtc, struct intel_crtc_state *pipe_config) { struct drm_device *dev = modeset_crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_atomic_state *state = pipe_config->base.state; - struct intel_crtc_state *crtc_state_copy = NULL; - struct intel_crtc *intel_crtc; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; int ret = 0; @@ -12370,10 +12344,6 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, if (ret) return ret; - crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); - if (!crtc_state_copy) - return -ENOMEM; - for_each_crtc_in_state(state, crtc, crtc_state, i) { if (!needs_modeset(crtc_state)) continue; @@ -12395,9 +12365,6 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, */ if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) { modeset_crtc->mode = pipe_config->base.mode; - /* mode_set/enable/disable functions rely on a correct pipe - * config. */ - intel_crtc_set_state(to_intel_crtc(modeset_crtc), pipe_config); /* * Calculate and store various constants which @@ -12412,14 +12379,16 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, * update the the output configuration. */ intel_modeset_update_state(state); + /* The state has been swaped above, so state actually contains the + * old state now. */ + modeset_update_crtc_power_domains(state); - __intel_set_mode_swap_plane_state(dev, state); drm_atomic_helper_commit_planes(dev, state); /* Now enable the clocks, plane, pipe, and connectors that we set up. */ for_each_crtc_in_state(state, crtc, crtc_state, i) { - if (!needs_modeset(crtc_state) || !crtc_state->enable) + if (!needs_modeset(crtc->state) || !crtc->state->enable) continue; update_scanline_offset(to_intel_crtc(crtc)); @@ -12430,14 +12399,6 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, /* FIXME: add subpixel order */ - intel_crtc = to_intel_crtc(modeset_crtc); - - /* The pipe_config will be freed with the atomic state, so - * make a copy. */ - memcpy(crtc_state_copy, intel_crtc->config, sizeof *crtc_state_copy); - intel_crtc->config = crtc_state_copy; - intel_crtc->base.state = &crtc_state_copy->base; - drm_atomic_helper_cleanup_planes(dev, state); drm_atomic_state_free(state); -- cgit v1.2.3 From 550acefd229dc3ef1be00c3355ecccca8fe8bf2b Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Tue, 21 Apr 2015 17:13:24 +0300 Subject: drm/i915: Get rid of intel_crtc_set_state() Now that we do proper state swaps, we don't depend on this function anymore to keep the state in sync. Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e4983c19829e..b5806400d40e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10256,14 +10256,6 @@ void intel_mark_idle(struct drm_device *dev) intel_runtime_pm_put(dev_priv); } -static void intel_crtc_set_state(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state) -{ - kfree(crtc->config); - crtc->config = crtc_state; - crtc->base.state = &crtc_state->base; -} - static void intel_crtc_destroy(struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); @@ -10280,7 +10272,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc) kfree(work); } - intel_crtc_set_state(intel_crtc, NULL); drm_crtc_cleanup(crtc); kfree(intel_crtc); @@ -13502,7 +13493,8 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); if (!crtc_state) goto fail; - intel_crtc_set_state(intel_crtc, crtc_state); + intel_crtc->config = crtc_state; + intel_crtc->base.state = &crtc_state->base; crtc_state->base.crtc = &intel_crtc->base; /* initialize shared scalers */ -- cgit v1.2.3 From 637a9c63f84263ebfdb27440b81d6e18e5d35754 Mon Sep 17 00:00:00 2001 From: Sonika Jindal Date: Thu, 7 May 2015 09:52:08 +0530 Subject: drm/i915: Rename dp rates array as per platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Renaming gen9_rates to skl_rates because other platforms may have different supported rates. Signed-off-by: Sonika Jindal Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index d0a88602efab..b4c5b9bb6207 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -90,8 +90,8 @@ static const struct dp_link_dpll chv_dpll[] = { { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } }; -/* Skylake supports following rates */ -static const int gen9_rates[] = { 162000, 216000, 270000, + +static const int skl_rates[] = { 162000, 216000, 270000, 324000, 432000, 540000 }; static const int chv_rates[] = { 162000, 202500, 210000, 216000, 243000, 270000, 324000, 405000, @@ -1167,9 +1167,9 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) static int intel_dp_source_rates(struct drm_device *dev, const int **source_rates) { - if (INTEL_INFO(dev)->gen >= 9) { - *source_rates = gen9_rates; - return ARRAY_SIZE(gen9_rates); + if (IS_SKYLAKE(dev)) { + *source_rates = skl_rates; + return ARRAY_SIZE(skl_rates); } else if (IS_CHERRYVIEW(dev)) { *source_rates = chv_rates; return ARRAY_SIZE(chv_rates); -- cgit v1.2.3 From 432be69d9d7e7e23f994422690639f3aa1d6abc2 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 7 May 2015 12:14:55 +0100 Subject: drm/i915: Remove locking for get-caching query Reading a single value from the object, the locking only provides futile protection against userspace races. The locking is useless so remove it. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index c378f0421145..9c195cc9065b 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3842,17 +3842,10 @@ int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, { struct drm_i915_gem_caching *args = data; struct drm_i915_gem_object *obj; - int ret; - - ret = i915_mutex_lock_interruptible(dev); - if (ret) - return ret; obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); - if (&obj->base == NULL) { - ret = -ENOENT; - goto unlock; - } + if (&obj->base == NULL) + return -ENOENT; switch (obj->cache_level) { case I915_CACHE_LLC: @@ -3869,10 +3862,8 @@ int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, break; } - drm_gem_object_unreference(&obj->base); -unlock: - mutex_unlock(&dev->struct_mutex); - return ret; + drm_gem_object_unreference_unlocked(&obj->base); + return 0; } int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, -- cgit v1.2.3 From b0e6f6d4b073f11c351163adf98fc7d7eb972541 Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Thu, 7 May 2015 14:15:29 +0100 Subject: drm/i915/bxt: Mark WaDisablePartialInstShootdown as for Broxton also. Signed-off-by: Nick Hoath Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 7ef9a29405cd..49e46106aa90 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -919,7 +919,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) struct drm_device *dev = ring->dev; struct drm_i915_private *dev_priv = dev->dev_private; - /* WaDisablePartialInstShootdown:skl */ + /* WaDisablePartialInstShootdown:skl,bxt */ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); -- cgit v1.2.3 From a119a6e66e0a57fcab927514cd6dbd148490d6d5 Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Thu, 7 May 2015 14:15:30 +0100 Subject: drm/i915/bxt: Mark workaround as for Skylake & Broxton Signed-off-by: Nick Hoath Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 49e46106aa90..cdbdf49bbab9 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -923,7 +923,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); - /* Syncing dependencies between camera and graphics */ + /* Syncing dependencies between camera and graphics:skl,bxt */ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); -- cgit v1.2.3 From d2a31dbd67d44ac9b9435fddba5a99696298afa6 Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Thu, 7 May 2015 14:15:31 +0100 Subject: drm/i915/bxt: Enable WaDisableDgMirrorFixInHalfSliceChicken5 for Broxton Signed-off-by: Nick Hoath Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index cdbdf49bbab9..4b0d48bccb9b 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -927,9 +927,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); - if (INTEL_REVID(dev) == SKL_REVID_A0 || - INTEL_REVID(dev) == SKL_REVID_B0) { - /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */ + if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || + INTEL_REVID(dev) == SKL_REVID_B0)) || + (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { + /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, GEN9_DG_MIRROR_FIX_ENABLE); } -- cgit v1.2.3 From a13d215fe75d0b98b9841654b56dcd6e8cc796e4 Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Thu, 7 May 2015 14:15:32 +0100 Subject: drm/i915/bxt: Enable WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken for Broxton Signed-off-by: Nick Hoath Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 4b0d48bccb9b..8404e0c318e7 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -935,8 +935,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) GEN9_DG_MIRROR_FIX_ENABLE); } - if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) { - /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */ + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || + (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, GEN9_RHWO_OPTIMIZATION_DISABLE); WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0, -- cgit v1.2.3 From 27a1b688d9f1fa2abd14bfe6a8729a19fb3b1b25 Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Thu, 7 May 2015 14:15:33 +0100 Subject: drm/i915/bxt: Enable WaEnableYV12BugFixInHalfSliceChicken7 for Broxton Signed-off-by: Nick Hoath Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 8404e0c318e7..e8eeea190687 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -944,8 +944,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) DISABLE_PIXEL_MASK_CAMMING); } - if (INTEL_REVID(dev) >= SKL_REVID_C0) { - /* WaEnableYV12BugFixInHalfSliceChicken7:skl */ + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) || + IS_BROXTON(dev)) { + /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */ WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, GEN9_ENABLE_YV12_BUGFIX); } -- cgit v1.2.3 From b62adbd1ea1f65e82ac7b3ec79f9f4873e193a10 Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Thu, 7 May 2015 14:15:34 +0100 Subject: drm/i915/bxt: Move WaForceEnableNonCoherent to Skylake only Signed-off-by: Nick Hoath Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index e8eeea190687..885932488282 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -951,17 +951,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) GEN9_ENABLE_YV12_BUGFIX); } - if (INTEL_REVID(dev) <= SKL_REVID_D0) { - /* - *Use Force Non-Coherent whenever executing a 3D context. This - * is a workaround for a possible hang in the unlikely event - * a TLB invalidation occurs during a PSD flush. - */ - /* WaForceEnableNonCoherent:skl */ - WA_SET_BIT_MASKED(HDC_CHICKEN0, - HDC_FORCE_NON_COHERENT); - } - /* Wa4x4STCOptimizationDisable:skl */ WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); @@ -1039,6 +1028,17 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) WA_SET_BIT_MASKED(HIZ_CHICKEN, BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); + if (INTEL_REVID(dev) <= SKL_REVID_D0) { + /* + *Use Force Non-Coherent whenever executing a 3D context. This + * is a workaround for a possible hang in the unlikely event + * a TLB invalidation occurs during a PSD flush. + */ + /* WaForceEnableNonCoherent:skl */ + WA_SET_BIT_MASKED(HDC_CHICKEN0, + HDC_FORCE_NON_COHERENT); + } + return skl_tune_iz_hashing(ring); } -- cgit v1.2.3 From 5068368c2e3455c91f8c0c1a8f39eb511b184822 Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Thu, 7 May 2015 14:15:35 +0100 Subject: drm/i915/bxt: Mark Wa4x4STCOptimizationDisable as for Broxton also. Signed-off-by: Nick Hoath Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 885932488282..cf516ad1b029 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -951,7 +951,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) GEN9_ENABLE_YV12_BUGFIX); } - /* Wa4x4STCOptimizationDisable:skl */ + /* Wa4x4STCOptimizationDisable:skl,bxt */ WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); /* WaDisablePartialResolveInVc:skl */ -- cgit v1.2.3 From 27160c96e1897c541fa72a86fcfa2f2f67f73876 Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Thu, 7 May 2015 14:15:36 +0100 Subject: drm/i915/bxt: Mark WaDisablePartialResolveInVc as for Broxton also. Signed-off-by: Nick Hoath Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index cf516ad1b029..e74feedd6bee 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -954,7 +954,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) /* Wa4x4STCOptimizationDisable:skl,bxt */ WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); - /* WaDisablePartialResolveInVc:skl */ + /* WaDisablePartialResolveInVc:skl,bxt */ WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); /* WaCcsTlbPrefetchDisable:skl */ -- cgit v1.2.3 From 16be17af2ae9fd1544b5d0c58b4facf198031cb8 Mon Sep 17 00:00:00 2001 From: Nick Hoath Date: Thu, 7 May 2015 14:15:37 +0100 Subject: drm/i915/bxt: Mark WaCcsTlbPrefetchDisable as for Broxton also. Signed-off-by: Nick Hoath Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index e74feedd6bee..9b96ed7de9bb 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -957,7 +957,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) /* WaDisablePartialResolveInVc:skl,bxt */ WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); - /* WaCcsTlbPrefetchDisable:skl */ + /* WaCcsTlbPrefetchDisable:skl,bxt */ WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, GEN9_CCS_TLB_PREFETCH_ENABLE); -- cgit v1.2.3 From 91e6711e30c55d7493eed5c3852764e38a782cad Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Wed, 6 May 2015 14:33:58 +0300 Subject: drm/i915: Do not make assumptions on GGTT VMA sizes GGTT VMA sizes might be smaller than the whole object size due to different GGTT views. v2: - Separate GGTT view constraint calculations from normal view constraint calculations (Chris Wilson) v3: - Do not bother with debug wording. (Tvrtko Ursulin) v4: - Clearer logic for calculating map_and_fenceable (Tvrtko Ursulin) Cc: Chris Wilson Cc: Tvrtko Ursulin Signed-off-by: Joonas Lahtinen Reviewed-by: Tvrtko Ursulin [danvet: Drop BUG_ON, it's redudant.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 74 +++++++++++++++++++++++++------------ drivers/gpu/drm/i915/i915_gem_gtt.c | 20 ++++++++++ drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++ 3 files changed, 74 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 9c195cc9065b..18307dfdc679 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3498,7 +3498,8 @@ static bool i915_gem_valid_gtt_space(struct i915_vma *vma, } /** - * Finds free space in the GTT aperture and binds the object there. + * Finds free space in the GTT aperture and binds the object or a view of it + * there. */ static struct i915_vma * i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, @@ -3517,36 +3518,60 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, struct i915_vma *vma; int ret; - if(WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) - return ERR_PTR(-EINVAL); + if (i915_is_ggtt(vm)) { + u32 view_size; + + if (WARN_ON(!ggtt_view)) + return ERR_PTR(-EINVAL); - fence_size = i915_gem_get_gtt_size(dev, - obj->base.size, - obj->tiling_mode); - fence_alignment = i915_gem_get_gtt_alignment(dev, - obj->base.size, - obj->tiling_mode, true); - unfenced_alignment = - i915_gem_get_gtt_alignment(dev, - obj->base.size, - obj->tiling_mode, false); + view_size = i915_ggtt_view_size(obj, ggtt_view); + + fence_size = i915_gem_get_gtt_size(dev, + view_size, + obj->tiling_mode); + fence_alignment = i915_gem_get_gtt_alignment(dev, + view_size, + obj->tiling_mode, + true); + unfenced_alignment = i915_gem_get_gtt_alignment(dev, + view_size, + obj->tiling_mode, + false); + size = flags & PIN_MAPPABLE ? fence_size : view_size; + } else { + fence_size = i915_gem_get_gtt_size(dev, + obj->base.size, + obj->tiling_mode); + fence_alignment = i915_gem_get_gtt_alignment(dev, + obj->base.size, + obj->tiling_mode, + true); + unfenced_alignment = + i915_gem_get_gtt_alignment(dev, + obj->base.size, + obj->tiling_mode, + false); + size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; + } if (alignment == 0) alignment = flags & PIN_MAPPABLE ? fence_alignment : unfenced_alignment; if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { - DRM_DEBUG("Invalid object alignment requested %u\n", alignment); + DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", + ggtt_view ? ggtt_view->type : 0, + alignment); return ERR_PTR(-EINVAL); } - size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; - - /* If the object is bigger than the entire aperture, reject it early - * before evicting everything in a vain attempt to find space. + /* If binding the object/GGTT view requires more space than the entire + * aperture has, reject it early before evicting everything in a vain + * attempt to find space. */ - if (obj->base.size > end) { - DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", - obj->base.size, + if (size > end) { + DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n", + ggtt_view ? ggtt_view->type : 0, + size, flags & PIN_MAPPABLE ? "mappable" : "total", end); return ERR_PTR(-E2BIG); @@ -4199,7 +4224,8 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj, return ret; } - if ((bound ^ vma->bound) & GLOBAL_BIND) { + if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && + (bound ^ vma->bound) & GLOBAL_BIND) { bool mappable, fenceable; u32 fence_size, fence_alignment; @@ -4218,9 +4244,9 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj, dev_priv->gtt.mappable_end); obj->map_and_fenceable = mappable && fenceable; - } - WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); + WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); + } vma->pin_count++; return 0; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 8fee6789fae2..2b7c77b987bc 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2838,3 +2838,23 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, return 0; } + +/** + * i915_ggtt_view_size - Get the size of a GGTT view. + * @obj: Object the view is of. + * @view: The view in question. + * + * @return The size of the GGTT view in bytes. + */ +size_t +i915_ggtt_view_size(struct drm_i915_gem_object *obj, + const struct i915_ggtt_view *view) +{ + if (view->type == I915_GGTT_VIEW_NORMAL || + view->type == I915_GGTT_VIEW_ROTATED) { + return obj->base.size; + } else { + WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type); + return obj->base.size; + } +} diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 4e6cac575cd8..34b7cca3df13 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -498,4 +498,8 @@ i915_ggtt_view_equal(const struct i915_ggtt_view *a, return a->type == b->type; } +size_t +i915_ggtt_view_size(struct drm_i915_gem_object *obj, + const struct i915_ggtt_view *view); + #endif -- cgit v1.2.3 From a6631ae1fd868b893986f3a613c231e34877b7b5 Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Wed, 6 May 2015 14:34:58 +0300 Subject: drm/i915: Consider object pinned if any VMA is pinned Do not skip special GGTT views when considering whether an object is pinned or not. Wrong behaviour was introduced in; commit ec7adb6ee79c8c9fe64d63ad638a31cd62e55515 Author: Joonas Lahtinen Date: Mon Mar 16 14:11:13 2015 +0200 drm/i915: Do not use ggtt_view with (aliasing) PPGTT Cc: Daniel Vetter Cc: Tvrtko Ursulin Signed-off-by: Joonas Lahtinen Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 18307dfdc679..04d18bc7bf53 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5244,13 +5244,10 @@ unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { struct i915_vma *vma; - list_for_each_entry(vma, &obj->vma_list, vma_link) { - if (i915_is_ggtt(vma->vm) && - vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) - continue; + list_for_each_entry(vma, &obj->vma_list, vma_link) if (vma->pin_count > 0) return true; - } + return false; } -- cgit v1.2.3 From 8bd7ef1638611db5f4fe47813758588b610ee5aa Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Wed, 6 May 2015 14:35:38 +0300 Subject: drm/i915: Add a partial GGTT view type Partial view type allows manipulating parts of huge BOs through the GGTT, which was not previously possible due to constraint that whole object had to be mapped for any access to it through GGTT. v2: - Retain error value from sg_alloc_table (Tvrtko Ursulin) - Do not zero already zeroed variable (Tvrtko Ursulin) - Use more common variable types for page size/offset (Tvrtko Ursulin) v3: - Only compare additional view parameters when need to (Tvrtko Ursulin) v4: - Do zero out the variable that needs to be (bug introduced in v2). Cc: Tvrtko Ursulin Signed-off-by: Joonas Lahtinen Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 46 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_gtt.h | 16 +++++++++++-- 2 files changed, 60 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 2b7c77b987bc..e3bcc3ba7e40 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2753,6 +2753,47 @@ err_st_alloc: return ERR_PTR(ret); } +static struct sg_table * +intel_partial_pages(const struct i915_ggtt_view *view, + struct drm_i915_gem_object *obj) +{ + struct sg_table *st; + struct scatterlist *sg; + struct sg_page_iter obj_sg_iter; + int ret = -ENOMEM; + + st = kmalloc(sizeof(*st), GFP_KERNEL); + if (!st) + goto err_st_alloc; + + ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL); + if (ret) + goto err_sg_alloc; + + sg = st->sgl; + st->nents = 0; + for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents, + view->params.partial.offset) + { + if (st->nents >= view->params.partial.size) + break; + + sg_set_page(sg, NULL, PAGE_SIZE, 0); + sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter); + sg_dma_len(sg) = PAGE_SIZE; + + sg = sg_next(sg); + st->nents++; + } + + return st; + +err_sg_alloc: + kfree(st); +err_st_alloc: + return ERR_PTR(ret); +} + static int i915_get_ggtt_vma_pages(struct i915_vma *vma) { @@ -2766,6 +2807,9 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma) else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) vma->ggtt_view.pages = intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); + else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) + vma->ggtt_view.pages = + intel_partial_pages(&vma->ggtt_view, vma->obj); else WARN_ONCE(1, "GGTT view %u not implemented!\n", vma->ggtt_view.type); @@ -2853,6 +2897,8 @@ i915_ggtt_view_size(struct drm_i915_gem_object *obj, if (view->type == I915_GGTT_VIEW_NORMAL || view->type == I915_GGTT_VIEW_ROTATED) { return obj->base.size; + } else if (view->type == I915_GGTT_VIEW_PARTIAL) { + return view->params.partial.size << PAGE_SHIFT; } else { WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type); return obj->base.size; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 34b7cca3df13..0d46dd20bf71 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -117,7 +117,8 @@ typedef uint64_t gen8_pde_t; enum i915_ggtt_view_type { I915_GGTT_VIEW_NORMAL = 0, - I915_GGTT_VIEW_ROTATED + I915_GGTT_VIEW_ROTATED, + I915_GGTT_VIEW_PARTIAL, }; struct intel_rotation_info { @@ -130,6 +131,13 @@ struct intel_rotation_info { struct i915_ggtt_view { enum i915_ggtt_view_type type; + union { + struct { + unsigned long offset; + unsigned int size; + } partial; + } params; + struct sg_table *pages; union { @@ -495,7 +503,11 @@ i915_ggtt_view_equal(const struct i915_ggtt_view *a, if (WARN_ON(!a || !b)) return false; - return a->type == b->type; + if (a->type != b->type) + return false; + if (a->type == I915_GGTT_VIEW_PARTIAL) + return !memcmp(&a->params, &b->params, sizeof(a->params)); + return true; } size_t -- cgit v1.2.3 From c5ad54cf7dd8922bd1cee2d5871aebf73dc9638e Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Wed, 6 May 2015 14:36:09 +0300 Subject: drm/i915: Use partial view in mmap fault handler Use partial view for huge BOs (bigger than half the mappable aperture) in fault handler so that they can be accessed withough trying to make room for them by evicting other objects. v2: - Only use partial views in the case where early rejection was previously done. - Account variable type changes from previous reroll. v3: - Add a comment about overwriting existing page entries. (Tvrtko Ursulin) - Whitespace fixes. Cc: Chris Wilson Cc: Tvrtko Ursulin Signed-off-by: Joonas Lahtinen Reviewed-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 73 ++++++++++++++++++++++++++++------------- 1 file changed, 51 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 04d18bc7bf53..b45f93bb030e 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1635,6 +1635,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); struct drm_device *dev = obj->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; + struct i915_ggtt_view view = i915_ggtt_view_normal; pgoff_t page_offset; unsigned long pfn; int ret = 0; @@ -1667,8 +1668,21 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) goto unlock; } - /* Now bind it into the GTT if needed */ - ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); + /* Use a partial view if the object is bigger than the aperture. */ + if (obj->base.size >= dev_priv->gtt.mappable_end) { + static const unsigned int chunk_size = 256; // 1 MiB + memset(&view, 0, sizeof(view)); + view.type = I915_GGTT_VIEW_PARTIAL; + view.params.partial.offset = rounddown(page_offset, chunk_size); + view.params.partial.size = + min_t(unsigned int, + chunk_size, + (vma->vm_end - vma->vm_start)/PAGE_SIZE - + view.params.partial.offset); + } + + /* Now pin it into the GTT if needed */ + ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); if (ret) goto unlock; @@ -1681,30 +1695,50 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) goto unpin; /* Finally, remap it using the new GTT offset */ - pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); + pfn = dev_priv->gtt.mappable_base + + i915_gem_obj_ggtt_offset_view(obj, &view); pfn >>= PAGE_SHIFT; - if (!obj->fault_mappable) { - unsigned long size = min_t(unsigned long, - vma->vm_end - vma->vm_start, - obj->base.size); - int i; + if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { + /* Overriding existing pages in partial view does not cause + * us any trouble as TLBs are still valid because the fault + * is due to userspace losing part of the mapping or never + * having accessed it before (at this partials' range). + */ + unsigned long base = vma->vm_start + + (view.params.partial.offset << PAGE_SHIFT); + unsigned int i; - for (i = 0; i < size >> PAGE_SHIFT; i++) { - ret = vm_insert_pfn(vma, - (unsigned long)vma->vm_start + i * PAGE_SIZE, - pfn + i); + for (i = 0; i < view.params.partial.size; i++) { + ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); if (ret) break; } obj->fault_mappable = true; - } else - ret = vm_insert_pfn(vma, - (unsigned long)vmf->virtual_address, - pfn + page_offset); + } else { + if (!obj->fault_mappable) { + unsigned long size = min_t(unsigned long, + vma->vm_end - vma->vm_start, + obj->base.size); + int i; + + for (i = 0; i < size >> PAGE_SHIFT; i++) { + ret = vm_insert_pfn(vma, + (unsigned long)vma->vm_start + i * PAGE_SIZE, + pfn + i); + if (ret) + break; + } + + obj->fault_mappable = true; + } else + ret = vm_insert_pfn(vma, + (unsigned long)vmf->virtual_address, + pfn + page_offset); + } unpin: - i915_gem_object_ggtt_unpin(obj); + i915_gem_object_ggtt_unpin_view(obj, &view); unlock: mutex_unlock(&dev->struct_mutex); out: @@ -1897,11 +1931,6 @@ i915_gem_mmap_gtt(struct drm_file *file, goto unlock; } - if (obj->base.size > dev_priv->gtt.mappable_end) { - ret = -E2BIG; - goto out; - } - if (obj->madv != I915_MADV_WILLNEED) { DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); ret = -EFAULT; -- cgit v1.2.3 From ebf7ed1a5bf859b092396c66a072c2cb797358bf Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Thu, 7 May 2015 18:38:37 +0100 Subject: drm/i915/skl: Re-indent part of skl_ddi_calculate_wrpll() A part of this function was indented with 2 tabs and 1 space instead of just 2 tabs. We're going to touch that code, so start by re-indenting it. Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 64 ++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index ec5d2eaef43c..807e15d41a1b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1189,69 +1189,69 @@ found: if (min_dco_index > 2) { WARN(1, "No valid values found for the given pixel clock\n"); } else { - wrpll_params->central_freq = dco_central_freq[min_dco_index]; + wrpll_params->central_freq = dco_central_freq[min_dco_index]; - switch (dco_central_freq[min_dco_index]) { - case 9600000000ULL: + switch (dco_central_freq[min_dco_index]) { + case 9600000000ULL: wrpll_params->central_freq = 0; break; - case 9000000000ULL: + case 9000000000ULL: wrpll_params->central_freq = 1; break; - case 8400000000ULL: + case 8400000000ULL: wrpll_params->central_freq = 3; - } + } - switch (candidate_p0[min_dco_index]) { - case 1: + switch (candidate_p0[min_dco_index]) { + case 1: wrpll_params->pdiv = 0; break; - case 2: + case 2: wrpll_params->pdiv = 1; break; - case 3: + case 3: wrpll_params->pdiv = 2; break; - case 7: + case 7: wrpll_params->pdiv = 4; break; - default: + default: WARN(1, "Incorrect PDiv\n"); - } + } - switch (candidate_p2[min_dco_index]) { - case 5: + switch (candidate_p2[min_dco_index]) { + case 5: wrpll_params->kdiv = 0; break; - case 2: + case 2: wrpll_params->kdiv = 1; break; - case 3: + case 3: wrpll_params->kdiv = 2; break; - case 1: + case 1: wrpll_params->kdiv = 3; break; - default: + default: WARN(1, "Incorrect KDiv\n"); - } + } - wrpll_params->qdiv_ratio = candidate_p1[min_dco_index]; - wrpll_params->qdiv_mode = + wrpll_params->qdiv_ratio = candidate_p1[min_dco_index]; + wrpll_params->qdiv_mode = (wrpll_params->qdiv_ratio == 1) ? 0 : 1; - dco_freq = candidate_p0[min_dco_index] * - candidate_p1[min_dco_index] * - candidate_p2[min_dco_index] * afe_clock; + dco_freq = candidate_p0[min_dco_index] * + candidate_p1[min_dco_index] * + candidate_p2[min_dco_index] * afe_clock; /* - * Intermediate values are in Hz. - * Divide by MHz to match bsepc - */ - wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1))); - wrpll_params->dco_fraction = - div_u64(((div_u64(dco_freq, 24) - - wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1)); + * Intermediate values are in Hz. + * Divide by MHz to match bsepc + */ + wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1))); + wrpll_params->dco_fraction = + div_u64(((div_u64(dco_freq, 24) - + wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1)); } } -- cgit v1.2.3 From 90d469067d0808ddbd9be2c97a4a8e14037b5e46 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Thu, 7 May 2015 14:31:28 -0700 Subject: drm/i915: Set crtc_state->active to false when CRTC is disabled (v2) With the recent modeset internal rework, we wind up setting crtc_state->enable to false, but leave crtc_state->active as true, which is incorrect. This mismatch gets caught by drm_atomic_crtc_check() and causes subsequent atomic operations (such as plane updates while the CRTC is disabled) to fail. Bisect points to commit dad9a7d6d96630182fb52aae7c3856e9e7285e13 Author: Ander Conselvan de Oliveira Date: Tue Apr 21 17:13:19 2015 +0300 drm/i915: Use atomic helpers for computing changed flags as the commit that actually triggers the regression. v2: Update to alter in-flight state rather than already-committed state (first version was accidentally based on a midpoint of Ander's modeset rework series, before his final patches that add proper state swapping to the legacy modeset path). Cc: Ander Conselvan de Oliveira Cc: Maarten Lankhorst Testcase: igt/kms_universal_plane Signed-off-by: Matt Roper Reviewed-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b5806400d40e..fd228a27a7d0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12340,6 +12340,7 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, continue; if (!crtc_state->enable) { + crtc_state->active = false; intel_crtc_disable(crtc); } else if (crtc->state->enable) { intel_crtc_disable_planes(crtc); -- cgit v1.2.3 From ac935a8b6db00079e2de65cadf4c735ed8f0175b Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 1 Apr 2015 14:22:58 -0700 Subject: drm/i915/vlv: remove wait for previous GFX clk disable request Looks like it was introduced in: commit 650ad970a39f8b6164fe8613edc150f585315289 Author: Imre Deak Date: Fri Apr 18 16:35:02 2014 +0300 drm/i915: vlv: factor out vlv_force_gfx_clock and check for pending force-of but I'm not sure why. It has caused problems for us in the past (see 85250ddff7a6 "drm/i915/chv: Remove Wait for a previous gfx force-off" and 8d4eee9cd7a1 "drm/i915: vlv: increase timeout when forcing on the GFX clock") and doesn't seem to be required, so let's just drop it. References: https://bugs.freedesktop.org/show_bug.cgi?id=89611 Signed-off-by: Jesse Barnes Tested-by: Darren Hart Reviewed-by: Deepak S Cc: stable@vger.kernel.org # c9c52e24194a: drm/i915/chv: Remove Wait ... Cc: stable@vger.kernel.org Signed-off-by: Jani Nikula [danvet: Repick this commit from 5df0582bf036bb5f9a8ad8db5884fe13a55347d1 becuase Dave Airlie lost it in his merge commit e1dee1973c74a0408b108d88c57a15be8a2d6d84.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 334bcc1badaa..6bb6c47db49f 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1286,21 +1286,7 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) u32 val; int err; - val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); - #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) - /* Wait for a previous force-off to settle */ - if (force_on && !IS_CHERRYVIEW(dev_priv->dev)) { - /* WARN_ON only for the Valleyview */ - WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on); - - err = wait_for(!COND, 20); - if (err) { - DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n", - I915_READ(VLV_GTLC_SURVIVABILITY_REG)); - return err; - } - } val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); val &= ~VLV_GFX_CLK_FORCE_ON_BIT; -- cgit v1.2.3 From d2ed34362a52c9f0c4d77325fb25bb729704be45 Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Mon, 20 Apr 2015 19:22:53 +0100 Subject: drm: Introduce helper for replacing blob properties Introduce a common helper for the pattern of: - allocate new blob property - potentially free old blob property - replace content of indicative property with new blob ID - change member pointer on modeset object Signed-off-by: Daniel Stone Cc: Dave Airlie Reviewed-by: Maarten Lankhorst [danvet: Squash in fixup from Daniel for the kerneldoc, reported by 0day builder.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 155 +++++++++++++++++++++++++++++++-------------- 1 file changed, 106 insertions(+), 49 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 66671e040ba0..fd14db401517 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -4238,6 +4238,83 @@ static void drm_property_destroy_blob(struct drm_device *dev, kfree(blob); } +/** + * drm_property_replace_global_blob - atomically replace existing blob property + * @dev: drm device + * @replace: location of blob property pointer to be replaced + * @length: length of data for new blob, or 0 for no data + * @data: content for new blob, or NULL for no data + * @obj_holds_id: optional object for property holding blob ID + * @prop_holds_id: optional property holding blob ID + * @return 0 on success or error on failure + * + * This function will atomically replace a global property in the blob list, + * optionally updating a property which holds the ID of that property. It is + * guaranteed to be atomic: no caller will be allowed to see intermediate + * results, and either the entire operation will succeed and clean up the + * previous property, or it will fail and the state will be unchanged. + * + * If length is 0 or data is NULL, no new blob will be created, and the holding + * property, if specified, will be set to 0. + * + * Access to the replace pointer is assumed to be protected by the caller, e.g. + * by holding the relevant modesetting object lock for its parent. + * + * For example, a drm_connector has a 'PATH' property, which contains the ID + * of a blob property with the value of the MST path information. Calling this + * function with replace pointing to the connector's path_blob_ptr, length and + * data set for the new path information, obj_holds_id set to the connector's + * base object, and prop_holds_id set to the path property name, will perform + * a completely atomic update. The access to path_blob_ptr is protected by the + * caller holding a lock on the connector. + */ +static int drm_property_replace_global_blob(struct drm_device *dev, + struct drm_property_blob **replace, + size_t length, + const void *data, + struct drm_mode_object *obj_holds_id, + struct drm_property *prop_holds_id) +{ + struct drm_property_blob *new_blob = NULL; + struct drm_property_blob *old_blob = NULL; + int ret; + + WARN_ON(replace == NULL); + + old_blob = *replace; + + if (length && data) { + new_blob = drm_property_create_blob(dev, length, data); + if (!new_blob) + return -EINVAL; + } + + /* This does not need to be synchronised with blob_lock, as the + * get_properties ioctl locks all modesetting objects, and + * obj_holds_id must be locked before calling here, so we cannot + * have its value out of sync with the list membership modified + * below under blob_lock. */ + if (obj_holds_id) { + ret = drm_object_property_set_value(obj_holds_id, + prop_holds_id, + new_blob ? + new_blob->base.id : 0); + if (ret != 0) + goto err_created; + } + + if (old_blob) + drm_property_destroy_blob(dev, old_blob); + + *replace = new_blob; + + return 0; + +err_created: + drm_property_destroy_blob(dev, new_blob); + return ret; +} + /** * drm_mode_getblob_ioctl - get the contents of a blob property value * @dev: DRM device @@ -4287,7 +4364,7 @@ done: /** * drm_mode_connector_set_path_property - set tile property on connector * @connector: connector to set property on. - * @path: path to use for property. + * @path: path to use for property; must not be NULL. * * This creates a property to expose to userspace to specify a * connector path. This is mainly used for DisplayPort MST where @@ -4301,20 +4378,14 @@ int drm_mode_connector_set_path_property(struct drm_connector *connector, const char *path) { struct drm_device *dev = connector->dev; - size_t size = strlen(path) + 1; int ret; - if (connector->path_blob_ptr) - drm_property_destroy_blob(dev, connector->path_blob_ptr); - - connector->path_blob_ptr = drm_property_create_blob(connector->dev, - size, path); - if (!connector->path_blob_ptr) - return -EINVAL; - - ret = drm_object_property_set_value(&connector->base, - dev->mode_config.path_property, - connector->path_blob_ptr->base.id); + ret = drm_property_replace_global_blob(dev, + &connector->path_blob_ptr, + strlen(path) + 1, + path, + &connector->base, + dev->mode_config.path_property); return ret; } EXPORT_SYMBOL(drm_mode_connector_set_path_property); @@ -4333,16 +4404,16 @@ EXPORT_SYMBOL(drm_mode_connector_set_path_property); int drm_mode_connector_set_tile_property(struct drm_connector *connector) { struct drm_device *dev = connector->dev; - int ret, size; char tile[256]; - - if (connector->tile_blob_ptr) - drm_property_destroy_blob(dev, connector->tile_blob_ptr); + int ret; if (!connector->has_tile) { - connector->tile_blob_ptr = NULL; - ret = drm_object_property_set_value(&connector->base, - dev->mode_config.tile_property, 0); + ret = drm_property_replace_global_blob(dev, + &connector->tile_blob_ptr, + 0, + NULL, + &connector->base, + dev->mode_config.tile_property); return ret; } @@ -4351,16 +4422,13 @@ int drm_mode_connector_set_tile_property(struct drm_connector *connector) connector->num_h_tile, connector->num_v_tile, connector->tile_h_loc, connector->tile_v_loc, connector->tile_h_size, connector->tile_v_size); - size = strlen(tile) + 1; - connector->tile_blob_ptr = drm_property_create_blob(connector->dev, - size, tile); - if (!connector->tile_blob_ptr) - return -EINVAL; - - ret = drm_object_property_set_value(&connector->base, - dev->mode_config.tile_property, - connector->tile_blob_ptr->base.id); + ret = drm_property_replace_global_blob(dev, + &connector->tile_blob_ptr, + strlen(tile) + 1, + tile, + &connector->base, + dev->mode_config.tile_property); return ret; } EXPORT_SYMBOL(drm_mode_connector_set_tile_property); @@ -4380,33 +4448,22 @@ int drm_mode_connector_update_edid_property(struct drm_connector *connector, const struct edid *edid) { struct drm_device *dev = connector->dev; - size_t size; + size_t size = 0; int ret; /* ignore requests to set edid when overridden */ if (connector->override_edid) return 0; - if (connector->edid_blob_ptr) - drm_property_destroy_blob(dev, connector->edid_blob_ptr); - - /* Delete edid, when there is none. */ - if (!edid) { - connector->edid_blob_ptr = NULL; - ret = drm_object_property_set_value(&connector->base, dev->mode_config.edid_property, 0); - return ret; - } - - size = EDID_LENGTH * (1 + edid->extensions); - connector->edid_blob_ptr = drm_property_create_blob(connector->dev, - size, edid); - if (!connector->edid_blob_ptr) - return -EINVAL; - - ret = drm_object_property_set_value(&connector->base, - dev->mode_config.edid_property, - connector->edid_blob_ptr->base.id); + if (edid) + size = EDID_LENGTH + (1 + edid->extensions); + ret = drm_property_replace_global_blob(dev, + &connector->edid_blob_ptr, + size, + edid, + &connector->base, + dev->mode_config.edid_property); return ret; } EXPORT_SYMBOL(drm_mode_connector_update_edid_property); -- cgit v1.2.3 From 8fb6e7a579670d5b71fc0d5641c1523b3df612e8 Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Mon, 20 Apr 2015 19:22:54 +0100 Subject: drm: Introduce blob_lock Create a new global blob_lock mutex, which protects the blob property list from insertion and/or deletion. Signed-off-by: Daniel Stone Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 18 +++++++++++++++--- include/drm/drm_crtc.h | 3 +++ 2 files changed, 18 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index fd14db401517..3b6573527e7f 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -4216,25 +4216,34 @@ drm_property_create_blob(struct drm_device *dev, size_t length, if (!blob) return NULL; + blob->length = length; + + memcpy(blob->data, data, length); + + mutex_lock(&dev->mode_config.blob_lock); + ret = drm_mode_object_get(dev, &blob->base, DRM_MODE_OBJECT_BLOB); if (ret) { kfree(blob); + mutex_unlock(&dev->mode_config.blob_lock); return NULL; } - blob->length = length; + list_add_tail(&blob->head, &dev->mode_config.property_blob_list); - memcpy(blob->data, data, length); + mutex_unlock(&dev->mode_config.blob_lock); - list_add_tail(&blob->head, &dev->mode_config.property_blob_list); return blob; } static void drm_property_destroy_blob(struct drm_device *dev, struct drm_property_blob *blob) { + mutex_lock(&dev->mode_config.blob_lock); drm_mode_object_put(dev, &blob->base); list_del(&blob->head); + mutex_unlock(&dev->mode_config.blob_lock); + kfree(blob); } @@ -4341,6 +4350,7 @@ int drm_mode_getblob_ioctl(struct drm_device *dev, return -EINVAL; drm_modeset_lock_all(dev); + mutex_lock(&dev->mode_config.blob_lock); blob = drm_property_blob_find(dev, out_resp->blob_id); if (!blob) { ret = -ENOENT; @@ -4357,6 +4367,7 @@ int drm_mode_getblob_ioctl(struct drm_device *dev, out_resp->length = blob->length; done: + mutex_unlock(&dev->mode_config.blob_lock); drm_modeset_unlock_all(dev); return ret; } @@ -5490,6 +5501,7 @@ void drm_mode_config_init(struct drm_device *dev) drm_modeset_lock_init(&dev->mode_config.connection_mutex); mutex_init(&dev->mode_config.idr_mutex); mutex_init(&dev->mode_config.fb_lock); + mutex_init(&dev->mode_config.blob_lock); INIT_LIST_HEAD(&dev->mode_config.fb_list); INIT_LIST_HEAD(&dev->mode_config.crtc_list); INIT_LIST_HEAD(&dev->mode_config.connector_list); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index ca71c03143d1..55ed8f9f45be 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1048,6 +1048,7 @@ struct drm_mode_group { * @poll_running: track polling status for this device * @output_poll_work: delayed work for polling in process context * @property_blob_list: list of all the blob property objects + * @blob_lock: mutex for blob property allocation and management * @*_property: core property tracking * @preferred_depth: preferred RBG pixel depth, used by fb helpers * @prefer_shadow: hint to userspace to prefer shadow-fb rendering @@ -1103,6 +1104,8 @@ struct drm_mode_config { bool delayed_event; struct delayed_work output_poll_work; + struct mutex blob_lock; + /* pointers to standard properties */ struct list_head property_blob_list; struct drm_property *edid_property; -- cgit v1.2.3 From 2e523e98bb593950de2c749d4ceb45cc20313c1a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 Apr 2015 18:21:27 +0300 Subject: drm/i915: Implement chv display PHY lane stagger setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set up the chv display PHY lane stagger registers according to "Programming Guide for 1273 CHV eDP/DP/HDMI Display PHY" v1.04 Signed-off-by: Ville Syrjälä Reviewed-by: Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++++++ drivers/gpu/drm/i915/intel_dp.c | 35 +++++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_hdmi.c | 35 +++++++++++++++++++++++++++++++++-- 3 files changed, 79 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 60ef5406fe57..98f10810bdbd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -961,6 +961,7 @@ enum skl_disp_power_wells { #define _VLV_PCS_DW11_CH0 0x822c #define _VLV_PCS_DW11_CH1 0x842c +#define DPIO_TX2_STAGGER_MASK(x) ((x)<<24) #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) @@ -973,8 +974,20 @@ enum skl_disp_power_wells { #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) +#define _VLV_PCS01_DW12_CH0 0x0230 +#define _VLV_PCS23_DW12_CH0 0x0430 +#define _VLV_PCS01_DW12_CH1 0x2630 +#define _VLV_PCS23_DW12_CH1 0x2830 +#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) +#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) + #define _VLV_PCS_DW12_CH0 0x8230 #define _VLV_PCS_DW12_CH1 0x8430 +#define DPIO_TX2_STAGGER_MULT(x) ((x)<<20) +#define DPIO_TX1_STAGGER_MULT(x) ((x)<<16) +#define DPIO_TX1_STAGGER_MASK(x) ((x)<<8) +#define DPIO_LANESTAGGER_STRAP_OVRD (1<<6) +#define DPIO_LANESTAGGER_STRAP(x) ((x)<<0) #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) #define _VLV_PCS_DW14_CH0 0x8238 diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index b4c5b9bb6207..2b1ed66c748f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2732,7 +2732,7 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) to_intel_crtc(encoder->base.crtc); enum dpio_channel ch = vlv_dport_to_channel(dport); int pipe = intel_crtc->pipe; - int data, i; + int data, i, stagger; u32 val; mutex_lock(&dev_priv->dpio_lock); @@ -2772,7 +2772,38 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) } /* Data lane stagger programming */ - /* FIXME: Fix up value only after power analysis */ + if (intel_crtc->config->port_clock > 270000) + stagger = 0x18; + else if (intel_crtc->config->port_clock > 135000) + stagger = 0xd; + else if (intel_crtc->config->port_clock > 67500) + stagger = 0x7; + else if (intel_crtc->config->port_clock > 33750) + stagger = 0x4; + else + stagger = 0x2; + + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); + val |= DPIO_TX2_STAGGER_MASK(0x1f); + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); + + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); + val |= DPIO_TX2_STAGGER_MASK(0x1f); + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); + + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), + DPIO_LANESTAGGER_STRAP(stagger) | + DPIO_LANESTAGGER_STRAP_OVRD | + DPIO_TX1_STAGGER_MASK(0x1f) | + DPIO_TX1_STAGGER_MULT(6) | + DPIO_TX2_STAGGER_MULT(0)); + + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), + DPIO_LANESTAGGER_STRAP(stagger) | + DPIO_LANESTAGGER_STRAP_OVRD | + DPIO_TX1_STAGGER_MASK(0x1f) | + DPIO_TX1_STAGGER_MULT(7) | + DPIO_TX2_STAGGER_MULT(5)); mutex_unlock(&dev_priv->dpio_lock); diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 590d46b124e0..86355f1c6f21 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1487,7 +1487,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) &intel_crtc->config->base.adjusted_mode; enum dpio_channel ch = vlv_dport_to_channel(dport); int pipe = intel_crtc->pipe; - int data, i; + int data, i, stagger; u32 val; mutex_lock(&dev_priv->dpio_lock); @@ -1527,7 +1527,38 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) } /* Data lane stagger programming */ - /* FIXME: Fix up value only after power analysis */ + if (intel_crtc->config->port_clock > 270000) + stagger = 0x18; + else if (intel_crtc->config->port_clock > 135000) + stagger = 0xd; + else if (intel_crtc->config->port_clock > 67500) + stagger = 0x7; + else if (intel_crtc->config->port_clock > 33750) + stagger = 0x4; + else + stagger = 0x2; + + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); + val |= DPIO_TX2_STAGGER_MASK(0x1f); + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); + + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); + val |= DPIO_TX2_STAGGER_MASK(0x1f); + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); + + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), + DPIO_LANESTAGGER_STRAP(stagger) | + DPIO_LANESTAGGER_STRAP_OVRD | + DPIO_TX1_STAGGER_MASK(0x1f) | + DPIO_TX1_STAGGER_MULT(6) | + DPIO_TX2_STAGGER_MULT(0)); + + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), + DPIO_LANESTAGGER_STRAP(stagger) | + DPIO_LANESTAGGER_STRAP_OVRD | + DPIO_TX1_STAGGER_MASK(0x1f) | + DPIO_TX1_STAGGER_MULT(7) | + DPIO_TX2_STAGGER_MULT(5)); /* Clear calc init */ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); -- cgit v1.2.3 From 70722468872b0752abaff54d34ed16af0d95cb9f Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 Apr 2015 18:21:28 +0300 Subject: drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sometimes (exactly when is a bit unclear) DISPLAY_PHY_CONTROL appears to get corrupted. The values I've managed to read from it seem to have some pattern but vary quite a lot. The corruption doesn't seem to just happen when the register is accessed, but can also happen spontaneosly during modeset. When this happens during a modeset things go south and the display doesn't light up. I've managed to hit the problemn when toggling HDMI on port D on and off. When things get corrupted the display doesn't light up, but as soon as I manually write the correct value to the register the display comes up. First I was suspicious that we ourselves accidentally overwrite it with garbage, but didn't catch anything with the reg_rw tracepoint. Also I sprinkled check all over the modeset path to see exactly when the corruption happens, and eg. the read back value was fine just before intel_dp_set_m(), and corrupted immediately after it. I also made my check function repair the register value whenever it was wrong, and with this approach the corruption repeated several times during the modeset operation, always seeming to trigger in the same exact calls to the check function, while other calls to the function never caught anything. So far I've not seen this problem occurring when carefully avoiding all read accesses to DISPLAY_PHY_CONTROL. Not sure if that's just pure luck or an actual workaround, but we can hope it works. So let's avoid reading the register and instead track the desired value of the register in dev_priv. v2: Read out the power well state to determine initial register value v3: Use DPIO_CHx names instead of raw numbers Signed-off-by: Ville Syrjälä Reviewed-by: Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 5 ++++- drivers/gpu/drm/i915/intel_runtime_pm.c | 36 ++++++++++++++++++++++++++++----- 3 files changed, 37 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 87fe4f7d5ce5..1321956ec066 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1782,6 +1782,8 @@ struct drm_i915_private { u32 fdi_rx_config; + u32 chv_phy_control; + u32 suspend_count; struct i915_suspend_saved_registers regfile; struct vlv_s0ix_state vlv_s0ix_state; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 98f10810bdbd..58627a319416 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2137,7 +2137,10 @@ enum skl_disp_power_wells { #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) #define DPLL_PORTD_READY_MASK (0xf) #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) -#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) +#define PHY_CH_SU_PSR 0x1 +#define PHY_CH_DEEP_PSR 0x7 +#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2)) +#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index bd7ad1d2d5f5..3d7352577bdc 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -949,8 +949,8 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) DRM_ERROR("Display PHY %d is not power up\n", phy); - I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) | - PHY_COM_LANE_RESET_DEASSERT(phy)); + dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); + I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); } static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, @@ -970,8 +970,8 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, assert_pll_disabled(dev_priv, PIPE_C); } - I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) & - ~PHY_COM_LANE_RESET_DEASSERT(phy)); + dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); + I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); vlv_set_power_well(dev_priv, power_well, false); } @@ -1719,6 +1719,30 @@ static void intel_power_domains_resume(struct drm_i915_private *dev_priv) mutex_unlock(&power_domains->lock); } +static void chv_phy_control_init(struct drm_i915_private *dev_priv) +{ + struct i915_power_well *cmn_bc = + lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); + struct i915_power_well *cmn_d = + lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); + + /* + * DISPLAY_PHY_CONTROL can get corrupted if read. As a + * workaround never ever read DISPLAY_PHY_CONTROL, and + * instead maintain a shadow copy ourselves. Use the actual + * power well state to reconstruct the expected initial + * value. + */ + dev_priv->chv_phy_control = + PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH0) | + PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH1) | + PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY1, DPIO_CH0); + if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) + dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); + if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) + dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); +} + static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) { struct i915_power_well *cmn = @@ -1761,7 +1785,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) power_domains->initializing = true; - if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { + if (IS_CHERRYVIEW(dev)) { + chv_phy_control_init(dev_priv); + } else if (IS_VALLEYVIEW(dev)) { mutex_lock(&power_domains->lock); vlv_cmnlane_wa(dev_priv); mutex_unlock(&power_domains->lock); -- cgit v1.2.3 From 71849b67e788ca8899982df7adf21f61f44cb474 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 Apr 2015 18:21:29 +0300 Subject: Revert "drm/i915: Hack to tie both common lanes together on chv" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With recent hardware/firmware there don't appear to be any glitches on the other PHY when we toggle the cmnreset for the other PHY. So detangle the cmnlane power wells from one another and let them be controlled independently. This reverts commit 3dd7b97458e8aa2d8985b46622d226fa635071e7. Signed-off-by: Ville Syrjälä Reviewed-by: Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 3d7352577bdc..317b9b43d1c1 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1464,23 +1464,13 @@ static struct i915_power_well chv_power_wells[] = { #endif { .name = "dpio-common-bc", - /* - * XXX: cmnreset for one PHY seems to disturb the other. - * As a workaround keep both powered on at the same - * time for now. - */ - .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, + .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, .data = PUNIT_POWER_WELL_DPIO_CMN_BC, .ops = &chv_dpio_cmn_power_well_ops, }, { .name = "dpio-common-d", - /* - * XXX: cmnreset for one PHY seems to disturb the other. - * As a workaround keep both powered on at the same - * time for now. - */ - .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, + .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, .data = PUNIT_POWER_WELL_DPIO_CMN_D, .ops = &chv_dpio_cmn_power_well_ops, }, -- cgit v1.2.3 From e7ded2d74673c2cdabd1f80da8c8a1b7b531e84a Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Fri, 8 May 2015 14:37:39 +0300 Subject: drm/i915: Reject huge tiled objects We do not yet support tiled objects bigger than the mappable aperture size so reject them. Reported-by: Chris Wilson Signed-off-by: Joonas Lahtinen [danvet: Rework the check a bit to avoid warnings.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index b45f93bb030e..f128ed8d6f65 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1669,8 +1669,10 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) } /* Use a partial view if the object is bigger than the aperture. */ - if (obj->base.size >= dev_priv->gtt.mappable_end) { + if (obj->base.size >= dev_priv->gtt.mappable_end && + obj->tiling_mode == I915_TILING_NONE) { static const unsigned int chunk_size = 256; // 1 MiB + memset(&view, 0, sizeof(view)); view.type = I915_GGTT_VIEW_PARTIAL; view.params.partial.offset = rounddown(page_offset, chunk_size); -- cgit v1.2.3 From ac6f2e29bb08a2313b0480c6cea94b01ab274970 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 8 May 2015 16:15:41 +0200 Subject: drm/edid: Kerneldoc for newly added edid_corrupt Also treat it as a proper boolean. Cc: Todd Previte Cc: Paulo Zanoni Cc: dri-devel@lists.freedesktop.org Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_edid.c | 8 ++++---- drivers/gpu/drm/i915/intel_dp.c | 2 +- include/drm/drm_crtc.h | 1 + 3 files changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index be6713c2fc9d..e426223482fb 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1064,7 +1064,7 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, int score = drm_edid_header_is_valid(raw_edid); if (score == 8) { if (edid_corrupt) - *edid_corrupt = 0; + *edid_corrupt = false; } else if (score >= edid_fixup) { /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 * The corrupt flag needs to be set here otherwise, the @@ -1072,12 +1072,12 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, * checksum is correct and the test fails */ if (edid_corrupt) - *edid_corrupt = 1; + *edid_corrupt = true; DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); memcpy(raw_edid, edid_header, sizeof(edid_header)); } else { if (edid_corrupt) - *edid_corrupt = 1; + *edid_corrupt = true; goto bad; } } @@ -1089,7 +1089,7 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, } if (edid_corrupt) - *edid_corrupt = 1; + *edid_corrupt = true; /* allow CEA to slide through, switches mangle this */ if (raw_edid[0] != 0x02) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2b1ed66c748f..9cf9208aeaff 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4120,7 +4120,7 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) struct drm_connector *connector = &intel_connector->base; if (intel_connector->detect_edid == NULL || - connector->edid_corrupt == 1 || + connector->edid_corrupt || intel_dp->aux.i2c_defer_count > 6) { /* Check EDID read for NACKs, DEFERs and corruption * (DP CTS 1.2 Core r1.1) diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index b9fcdc824997..0a4a040d6bb7 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -647,6 +647,7 @@ struct drm_encoder { * @audio_latency: audio latency info from ELD, if found * @null_edid_counter: track sinks that give us all zeros for the EDID * @bad_edid_counter: track sinks that give us an EDID with invalid checksum + * @edid_corrupt: indicates whether the last read EDID was corrupt * @debugfs_entry: debugfs directory for this connector * @state: current atomic state for this connector * @has_tile: is this connector connected to a tiled monitor -- cgit v1.2.3 From c7c7372edc4ebc173ad359aeb5752e9ce09f2741 Mon Sep 17 00:00:00 2001 From: "Rebecca N. Palmer" Date: Fri, 8 May 2015 14:26:50 +0100 Subject: drm/i915: Fix possible security hole in command parsing i915_parse_cmds returns -EACCES on chained batches, which "tells the caller to abort and dispatch the workload as a non-secure batch", but the mechanism implementing that was broken when flags |= I915_DISPATCH_SECURE was moved from i915_gem_execbuffer_parse to i915_gem_do_execbuffer (17cabf571e50677d980e9ab2a43c5f11213003ae): i915_gem_execbuffer_parse returns the original batch_obj in this case, and i915_gem_do_execbuffer doesn't check for that. Don't set the secure bit in this case to make sure such batches don't run with elevated priviledges. Signed-off-by: Rebecca Palmer Reviewed-by: Mika Kuoppala [danvet: Stitch together commit message. Also remove a comment as suggested by Mika. And style-align the comment while at it.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 31 ++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 7ab63d9d7dc5..560c79a8a43d 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1540,28 +1540,39 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, } if (i915_needs_cmd_parser(ring) && args->batch_len) { - batch_obj = i915_gem_execbuffer_parse(ring, + struct drm_i915_gem_object *parsed_batch_obj; + + parsed_batch_obj = i915_gem_execbuffer_parse(ring, &shadow_exec_entry, eb, batch_obj, args->batch_start_offset, args->batch_len, file->is_master); - if (IS_ERR(batch_obj)) { - ret = PTR_ERR(batch_obj); + if (IS_ERR(parsed_batch_obj)) { + ret = PTR_ERR(parsed_batch_obj); goto err; } /* - * Set the DISPATCH_SECURE bit to remove the NON_SECURE - * bit from MI_BATCH_BUFFER_START commands issued in the - * dispatch_execbuffer implementations. We specifically - * don't want that set when the command parser is - * enabled. + * parsed_batch_obj == batch_obj means batch not fully parsed: + * Accept, but don't promote to secure. */ - dispatch_flags |= I915_DISPATCH_SECURE; - exec_start = 0; + if (parsed_batch_obj != batch_obj) { + /* + * Batch parsed and accepted: + * + * Set the DISPATCH_SECURE bit to remove the NON_SECURE + * bit from MI_BATCH_BUFFER_START commands issued in + * the dispatch_execbuffer implementations. We + * specifically don't want that set on batches the + * command parser has accepted. + */ + dispatch_flags |= I915_DISPATCH_SECURE; + exec_start = 0; + batch_obj = parsed_batch_obj; + } } batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; -- cgit v1.2.3 From 9b6de0a1552175620ced3a7a7a552d4e7a379538 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 Apr 2015 18:21:31 +0300 Subject: drm/i915: Only wait for required lanes in vlv_wait_port_ready() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently vlv_wait_port_ready() waits for all four lanes on the appropriate channel. This no longer works on CHV when the unused lanes may be power gated. So pass in a mask of lanes that the caller is expecting to be ready. Signed-off-by: Ville Syrjälä Reviewed-by: Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 10 ++++++---- drivers/gpu/drm/i915/intel_dp.c | 4 +++- drivers/gpu/drm/i915/intel_drv.h | 3 ++- drivers/gpu/drm/i915/intel_hdmi.c | 4 ++-- 4 files changed, 13 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fd228a27a7d0..22e6644f755e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1844,7 +1844,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) } void vlv_wait_port_ready(struct drm_i915_private *dev_priv, - struct intel_digital_port *dport) + struct intel_digital_port *dport, + unsigned int expected_mask) { u32 port_mask; int dpll_reg; @@ -1857,6 +1858,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, case PORT_C: port_mask = DPLL_PORTC_READY_MASK; dpll_reg = DPLL(0); + expected_mask <<= 4; break; case PORT_D: port_mask = DPLL_PORTD_READY_MASK; @@ -1866,9 +1868,9 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, BUG(); } - if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) - WARN(1, "timed out waiting for port %c ready: 0x%08x\n", - port_name(dport->port), I915_READ(dpll_reg)); + if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) + WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", + port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); } static void intel_prepare_shared_dpll(struct intel_crtc *crtc) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 9cf9208aeaff..82dcc6ed8b1d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2497,6 +2497,7 @@ static void intel_enable_dp(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); uint32_t dp_reg = I915_READ(intel_dp->output_reg); + unsigned int lane_mask = 0x0; if (WARN_ON(dp_reg & DP_PORT_EN)) return; @@ -2515,7 +2516,8 @@ static void intel_enable_dp(struct intel_encoder *encoder) pps_unlock(intel_dp); if (IS_VALLEYVIEW(dev)) - vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp)); + vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), + lane_mask); intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); intel_dp_start_link_train(intel_dp); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 930ea6916d9f..ea3368e83626 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1013,7 +1013,8 @@ intel_wait_for_vblank(struct drm_device *dev, int pipe) } int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); void vlv_wait_port_ready(struct drm_i915_private *dev_priv, - struct intel_digital_port *dport); + struct intel_digital_port *dport, + unsigned int expected_mask); bool intel_get_load_detect_pipe(struct drm_connector *connector, struct drm_display_mode *mode, struct intel_load_detect_pipe *old, diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 86355f1c6f21..d04e6dc97fe5 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1324,7 +1324,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) intel_enable_hdmi(encoder); - vlv_wait_port_ready(dev_priv, dport); + vlv_wait_port_ready(dev_priv, dport, 0x0); } static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) @@ -1641,7 +1641,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) intel_enable_hdmi(encoder); - vlv_wait_port_ready(dev_priv, dport); + vlv_wait_port_ready(dev_priv, dport, 0x0); } static void intel_hdmi_destroy(struct drm_connector *connector) -- cgit v1.2.3 From 214a2b7fab215b1e979fbae51225b01b8fc58288 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 8 May 2015 17:38:19 +0200 Subject: drm/i915: Update DRIVER_DATE to 20150508 Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1321956ec066..acfa4fc93803 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -56,7 +56,7 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20150423" +#define DRIVER_DATE "20150508" #undef WARN_ON /* Many gcc seem to no see through this and fall over :( */ -- cgit v1.2.3 From cc7297dcb440eb9d2e50a8c26dc7e7b37ef37e25 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 1 Apr 2015 14:22:58 -0700 Subject: drm/i915/vlv: remove wait for previous GFX clk disable request Looks like it was introduced in: commit 650ad970a39f8b6164fe8613edc150f585315289 Author: Imre Deak Date: Fri Apr 18 16:35:02 2014 +0300 drm/i915: vlv: factor out vlv_force_gfx_clock and check for pending force-of but I'm not sure why. It has caused problems for us in the past (see 85250ddff7a6 "drm/i915/chv: Remove Wait for a previous gfx force-off" and 8d4eee9cd7a1 "drm/i915: vlv: increase timeout when forcing on the GFX clock") and doesn't seem to be required, so let's just drop it. [airlied: I messed up a merge - readd this] References: https://bugs.freedesktop.org/show_bug.cgi?id=89611 Signed-off-by: Jesse Barnes Tested-by: Darren Hart Reviewed-by: Deepak S Cc: stable@vger.kernel.org # c9c52e24194a: drm/i915/chv: Remove Wait ... Cc: stable@vger.kernel.org Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6e9ab2fb1647..e70adfd3b2d1 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1240,21 +1240,7 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) u32 val; int err; - val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); - #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) - /* Wait for a previous force-off to settle */ - if (force_on && !IS_CHERRYVIEW(dev_priv->dev)) { - /* WARN_ON only for the Valleyview */ - WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on); - - err = wait_for(!COND, 20); - if (err) { - DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n", - I915_READ(VLV_GTLC_SURVIVABILITY_REG)); - return err; - } - } val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); val &= ~VLV_GFX_CLK_FORCE_ON_BIT; -- cgit v1.2.3 From 6bcacf51d050d412e5c302e0dd5e582212c5f7be Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Mon, 20 Apr 2015 19:22:55 +0100 Subject: drm: Add reference counting to blob properties Reference-count drm_property_blob objects, changing the API to ref/unref. Signed-off-by: Daniel Stone Reviewed-by: Maarten Lankhorst [danvet: Squash in kerneldoc fixup from Daniel Stone.] [danvet: Squash in Oops fix from Thiery Reding.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 163 +++++++++++++++++++++++++++++++++++++++++---- include/drm/drm_crtc.h | 17 ++--- 2 files changed, 158 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 3b6573527e7f..2e26988a9762 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -352,7 +352,9 @@ static struct drm_mode_object *_object_find(struct drm_device *dev, if (obj && obj->id != id) obj = NULL; /* don't leak out unref'd fb's */ - if (obj && (obj->type == DRM_MODE_OBJECT_FB)) + if (obj && + (obj->type == DRM_MODE_OBJECT_FB || + obj->type == DRM_MODE_OBJECT_BLOB)) obj = NULL; mutex_unlock(&dev->mode_config.idr_mutex); @@ -377,7 +379,7 @@ struct drm_mode_object *drm_mode_object_find(struct drm_device *dev, /* Framebuffers are reference counted and need their own lookup * function.*/ - WARN_ON(type == DRM_MODE_OBJECT_FB); + WARN_ON(type == DRM_MODE_OBJECT_FB || type == DRM_MODE_OBJECT_BLOB); obj = _object_find(dev, id, type); return obj; } @@ -4202,7 +4204,7 @@ done: return ret; } -static struct drm_property_blob * +struct drm_property_blob * drm_property_create_blob(struct drm_device *dev, size_t length, const void *data) { @@ -4217,6 +4219,7 @@ drm_property_create_blob(struct drm_device *dev, size_t length, return NULL; blob->length = length; + blob->dev = dev; memcpy(blob->data, data, length); @@ -4229,24 +4232,146 @@ drm_property_create_blob(struct drm_device *dev, size_t length, return NULL; } + kref_init(&blob->refcount); + list_add_tail(&blob->head, &dev->mode_config.property_blob_list); mutex_unlock(&dev->mode_config.blob_lock); return blob; } +EXPORT_SYMBOL(drm_property_create_blob); -static void drm_property_destroy_blob(struct drm_device *dev, - struct drm_property_blob *blob) +/** + * drm_property_free_blob - Blob property destructor + * + * Internal free function for blob properties; must not be used directly. + * + * @param kref Reference + */ +static void drm_property_free_blob(struct kref *kref) { - mutex_lock(&dev->mode_config.blob_lock); - drm_mode_object_put(dev, &blob->base); + struct drm_property_blob *blob = + container_of(kref, struct drm_property_blob, refcount); + + WARN_ON(!mutex_is_locked(&blob->dev->mode_config.blob_lock)); + list_del(&blob->head); - mutex_unlock(&dev->mode_config.blob_lock); + drm_mode_object_put(blob->dev, &blob->base); kfree(blob); } +/** + * drm_property_unreference_blob - Unreference a blob property + * + * Drop a reference on a blob property. May free the object. + * + * @param blob Pointer to blob property + */ +void drm_property_unreference_blob(struct drm_property_blob *blob) +{ + struct drm_device *dev; + + if (!blob) + return; + + dev = blob->dev; + + DRM_DEBUG("%p: blob ID: %d (%d)\n", blob, blob->base.id, atomic_read(&blob->refcount.refcount)); + + if (kref_put_mutex(&blob->refcount, drm_property_free_blob, + &dev->mode_config.blob_lock)) + mutex_unlock(&dev->mode_config.blob_lock); + else + might_lock(&dev->mode_config.blob_lock); + +} +EXPORT_SYMBOL(drm_property_unreference_blob); + +/** + * drm_property_unreference_blob_locked - Unreference a blob property with blob_lock held + * + * Drop a reference on a blob property. May free the object. This must be + * called with blob_lock held. + * + * @param dev Device the blob was created on + * @param blob Pointer to blob property + */ +static void drm_property_unreference_blob_locked(struct drm_property_blob *blob) +{ + if (!blob) + return; + + DRM_DEBUG("%p: blob ID: %d (%d)\n", blob, blob->base.id, atomic_read(&blob->refcount.refcount)); + + kref_put(&blob->refcount, drm_property_free_blob); +} + +/** + * drm_property_reference_blob - Take a reference on an existing property + * + * Take a new reference on an existing blob property. + * + * @param blob Pointer to blob property + */ +struct drm_property_blob *drm_property_reference_blob(struct drm_property_blob *blob) +{ + DRM_DEBUG("%p: blob ID: %d (%d)\n", blob, blob->base.id, atomic_read(&blob->refcount.refcount)); + kref_get(&blob->refcount); + return blob; +} +EXPORT_SYMBOL(drm_property_reference_blob); + +/* + * Like drm_property_lookup_blob, but does not return an additional reference. + * Must be called with blob_lock held. + */ +static struct drm_property_blob *__drm_property_lookup_blob(struct drm_device *dev, + uint32_t id) +{ + struct drm_mode_object *obj = NULL; + struct drm_property_blob *blob; + + WARN_ON(!mutex_is_locked(&dev->mode_config.blob_lock)); + + mutex_lock(&dev->mode_config.idr_mutex); + obj = idr_find(&dev->mode_config.crtc_idr, id); + if (!obj || (obj->type != DRM_MODE_OBJECT_BLOB) || (obj->id != id)) + blob = NULL; + else + blob = obj_to_blob(obj); + mutex_unlock(&dev->mode_config.idr_mutex); + + return blob; +} + +/** + * drm_property_lookup_blob - look up a blob property and take a reference + * @dev: drm device + * @id: id of the blob property + * + * If successful, this takes an additional reference to the blob property. + * callers need to make sure to eventually unreference the returned property + * again, using @drm_property_unreference_blob. + */ +struct drm_property_blob *drm_property_lookup_blob(struct drm_device *dev, + uint32_t id) +{ + struct drm_property_blob *blob; + + mutex_lock(&dev->mode_config.blob_lock); + blob = __drm_property_lookup_blob(dev, id); + if (blob) { + if (!kref_get_unless_zero(&blob->refcount)) + blob = NULL; + } + mutex_unlock(&dev->mode_config.blob_lock); + + return blob; +} +EXPORT_SYMBOL(drm_property_lookup_blob); + /** * drm_property_replace_global_blob - atomically replace existing blob property * @dev: drm device @@ -4313,14 +4438,14 @@ static int drm_property_replace_global_blob(struct drm_device *dev, } if (old_blob) - drm_property_destroy_blob(dev, old_blob); + drm_property_unreference_blob(old_blob); *replace = new_blob; return 0; err_created: - drm_property_destroy_blob(dev, new_blob); + drm_property_unreference_blob(new_blob); return ret; } @@ -4351,7 +4476,7 @@ int drm_mode_getblob_ioctl(struct drm_device *dev, drm_modeset_lock_all(dev); mutex_lock(&dev->mode_config.blob_lock); - blob = drm_property_blob_find(dev, out_resp->blob_id); + blob = __drm_property_lookup_blob(dev, out_resp->blob_id); if (!blob) { ret = -ENOENT; goto done; @@ -4515,8 +4640,18 @@ bool drm_property_change_valid_get(struct drm_property *property, valid_mask |= (1ULL << property->values[i]); return !(value & ~valid_mask); } else if (drm_property_type_is(property, DRM_MODE_PROP_BLOB)) { - /* Only the driver knows */ - return true; + struct drm_property_blob *blob; + + if (value == 0) + return true; + + blob = drm_property_lookup_blob(property->dev, value); + if (blob) { + *ref = &blob->base; + return true; + } else { + return false; + } } else if (drm_property_type_is(property, DRM_MODE_PROP_OBJECT)) { /* a zero value for an object property translates to null: */ if (value == 0) @@ -5566,7 +5701,7 @@ void drm_mode_config_cleanup(struct drm_device *dev) list_for_each_entry_safe(blob, bt, &dev->mode_config.property_blob_list, head) { - drm_property_destroy_blob(dev, blob); + drm_property_unreference_blob(blob); } /* diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 55ed8f9f45be..5626191f3af0 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -216,6 +216,8 @@ struct drm_framebuffer { struct drm_property_blob { struct drm_mode_object base; + struct drm_device *dev; + struct kref refcount; struct list_head head; size_t length; unsigned char data[]; @@ -1365,6 +1367,13 @@ struct drm_property *drm_property_create_object(struct drm_device *dev, int flags, const char *name, uint32_t type); struct drm_property *drm_property_create_bool(struct drm_device *dev, int flags, const char *name); +struct drm_property_blob *drm_property_create_blob(struct drm_device *dev, + size_t length, + const void *data); +struct drm_property_blob *drm_property_lookup_blob(struct drm_device *dev, + uint32_t id); +struct drm_property_blob *drm_property_reference_blob(struct drm_property_blob *blob); +void drm_property_unreference_blob(struct drm_property_blob *blob); extern void drm_property_destroy(struct drm_device *dev, struct drm_property *property); extern int drm_property_add_enum(struct drm_property *property, int index, uint64_t value, const char *name); @@ -1528,14 +1537,6 @@ static inline struct drm_property *drm_property_find(struct drm_device *dev, return mo ? obj_to_property(mo) : NULL; } -static inline struct drm_property_blob * -drm_property_blob_find(struct drm_device *dev, uint32_t id) -{ - struct drm_mode_object *mo; - mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_BLOB); - return mo ? obj_to_blob(mo) : NULL; -} - /* Plane list iterator for legacy (overlay only) planes. */ #define drm_for_each_legacy_plane(plane, planelist) \ list_for_each_entry(plane, planelist, head) \ -- cgit v1.2.3 From 98515035d09fe943539c1967bbae06398f4375f5 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Fri, 8 May 2015 17:13:45 +0900 Subject: drm/prime: Allow internal imports without import_sg_table Currently drm_gem_prime_import() checks if gem_prime_import_sg_table() is implemented in DRM driver ops. However it is not necessary for internal imports (i.e. dma_buf->ops == &drm_gem_prime_dmabuf_ops and obj->dev == dev), which only increment reference count on respective GEM objects. This patch makes the helper check this condition only in case of external imports fo rwhich importing sg table is indeed needed. Signed-off-by: Tomasz Figa Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_prime.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c index 7fec191b45f7..162dd29b2451 100644 --- a/drivers/gpu/drm/drm_prime.c +++ b/drivers/gpu/drm/drm_prime.c @@ -502,9 +502,6 @@ struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev, struct drm_gem_object *obj; int ret; - if (!dev->driver->gem_prime_import_sg_table) - return ERR_PTR(-EINVAL); - if (dma_buf->ops == &drm_gem_prime_dmabuf_ops) { obj = dma_buf->priv; if (obj->dev == dev) { @@ -517,6 +514,9 @@ struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev, } } + if (!dev->driver->gem_prime_import_sg_table) + return ERR_PTR(-EINVAL); + attach = dma_buf_attach(dma_buf, dev->dev); if (IS_ERR(attach)) return ERR_CAST(attach); -- cgit v1.2.3 From 4d53dc0c02c1ad74dbeda89a9245f7fe15d45d02 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 8 May 2015 17:45:07 +0300 Subject: drm/edid: Add CEA modes before inferred modes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently we're adding CEA modes after the inferred modes, which means we might get multiple modes that are very close to each other, but slightly different, which seems a bit silly. That's because duplicate mode check that occurs when adding inferred modes would not consider CEA modes as potential duplicates. Reverse the order so that CEA modes get added before inferred modes, and are thus considered potential duplicates. Or as ajax put it on irc: "< ajax> the point of the "pick a timing formula" heuristic was to generate something the sink could _likely_ sink. if it tells us timings it can sink explicitly then second-guessing seems dumb." Cc: Adam Jackson Signed-off-by: Ville Syrjälä Reviewed-by: Adam Jackson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_edid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index e7a140056d15..314a364c5d95 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3744,10 +3744,10 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) num_modes += add_cvt_modes(connector, edid); num_modes += add_standard_modes(connector, edid); num_modes += add_established_modes(connector, edid); - if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) - num_modes += add_inferred_modes(connector, edid); num_modes += add_cea_modes(connector, edid); num_modes += add_alternate_cea_modes(connector, edid); + if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) + num_modes += add_inferred_modes(connector, edid); if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) edid_fixup_preferred(connector, quirks); -- cgit v1.2.3 From 7d4d3a5849126e64867185d651c76a2998dcdf3a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 May 2015 12:14:52 +0300 Subject: drm/sysfs: add a helper for extracting connector type from kobject MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reduces duplication in the patches to follow. No functional changes. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_sysfs.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index ffc305fc2076..33466999b59a 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -407,17 +407,23 @@ static struct attribute *connector_opt_dev_attrs[] = { NULL }; -static umode_t connector_opt_dev_is_visible(struct kobject *kobj, - struct attribute *attr, int idx) +/* Connector type related helpers */ +static int kobj_connector_type(struct kobject *kobj) { struct device *dev = kobj_to_dev(kobj); struct drm_connector *connector = to_drm_connector(dev); + return connector->connector_type; +} + +static umode_t connector_opt_dev_is_visible(struct kobject *kobj, + struct attribute *attr, int idx) +{ /* * In the long run it maybe a good idea to make one set of * optionals per connector type. */ - switch (connector->connector_type) { + switch (kobj_connector_type(kobj)) { case DRM_MODE_CONNECTOR_DVII: case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_SVIDEO: -- cgit v1.2.3 From fe6fcdd61d31eec8aad8cea66a4e826d5c5561b1 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 May 2015 12:14:53 +0300 Subject: drm/sysfs: make optional attribute groups per connector type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split DVI-I and TV-out (which remains a group of types). As an intermediate step, still share the attributes themselves between the two. No user visible changes. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_sysfs.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index 33466999b59a..674c3df56ea0 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -401,7 +401,7 @@ static struct attribute *connector_dev_attrs[] = { static DEVICE_ATTR_RO(subconnector); static DEVICE_ATTR_RO(select_subconnector); -static struct attribute *connector_opt_dev_attrs[] = { +static struct attribute *connector_tv_dev_attrs[] = { &dev_attr_subconnector.attr, &dev_attr_select_subconnector.attr, NULL @@ -416,15 +416,17 @@ static int kobj_connector_type(struct kobject *kobj) return connector->connector_type; } -static umode_t connector_opt_dev_is_visible(struct kobject *kobj, - struct attribute *attr, int idx) +static umode_t connector_is_dvii(struct kobject *kobj, + struct attribute *attr, int idx) +{ + return kobj_connector_type(kobj) == DRM_MODE_CONNECTOR_DVII ? + attr->mode : 0; +} + +static umode_t connector_is_tv(struct kobject *kobj, + struct attribute *attr, int idx) { - /* - * In the long run it maybe a good idea to make one set of - * optionals per connector type. - */ switch (kobj_connector_type(kobj)) { - case DRM_MODE_CONNECTOR_DVII: case DRM_MODE_CONNECTOR_Composite: case DRM_MODE_CONNECTOR_SVIDEO: case DRM_MODE_CONNECTOR_Component: @@ -452,14 +454,20 @@ static const struct attribute_group connector_dev_group = { .bin_attrs = connector_bin_attrs, }; -static const struct attribute_group connector_opt_dev_group = { - .attrs = connector_opt_dev_attrs, - .is_visible = connector_opt_dev_is_visible, +static const struct attribute_group connector_tv_dev_group = { + .attrs = connector_tv_dev_attrs, + .is_visible = connector_is_tv, +}; + +static const struct attribute_group connector_dvii_dev_group = { + .attrs = connector_tv_dev_attrs, /* same as tv */ + .is_visible = connector_is_dvii, }; static const struct attribute_group *connector_dev_groups[] = { &connector_dev_group, - &connector_opt_dev_group, + &connector_tv_dev_group, + &connector_dvii_dev_group, NULL }; -- cgit v1.2.3 From 4bb4637b26a28c724a9edaed2290ffed7e0dcc8f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 May 2015 12:14:54 +0300 Subject: drm/sysfs: split DVI-I and TV-out attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The show methods for the attributes of DVI-I and TV-out types have a bunch of code to deal with the differences between the two. Just split the attributes into connector type specific ones. No functional changes. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_sysfs.c | 148 ++++++++++++++++++++++++++++++-------------- 1 file changed, 101 insertions(+), 47 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index 674c3df56ea0..34e4fbcf44ba 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -302,33 +302,28 @@ static ssize_t modes_show(struct device *device, return written; } -static ssize_t subconnector_show(struct device *device, - struct device_attribute *attr, - char *buf) +static ssize_t tv_subconnector_show(struct device *device, + struct device_attribute *attr, + char *buf) { struct drm_connector *connector = to_drm_connector(device); struct drm_device *dev = connector->dev; - struct drm_property *prop = NULL; + struct drm_property *prop; uint64_t subconnector; - int is_tv = 0; int ret; switch (connector->connector_type) { - case DRM_MODE_CONNECTOR_DVII: - prop = dev->mode_config.dvi_i_subconnector_property; - break; - case DRM_MODE_CONNECTOR_Composite: - case DRM_MODE_CONNECTOR_SVIDEO: - case DRM_MODE_CONNECTOR_Component: - case DRM_MODE_CONNECTOR_TV: - prop = dev->mode_config.tv_subconnector_property; - is_tv = 1; - break; - default: - DRM_ERROR("Wrong connector type for this property\n"); - return 0; + case DRM_MODE_CONNECTOR_Composite: + case DRM_MODE_CONNECTOR_SVIDEO: + case DRM_MODE_CONNECTOR_Component: + case DRM_MODE_CONNECTOR_TV: + break; + default: + DRM_ERROR("Wrong connector type for this property\n"); + return 0; } + prop = dev->mode_config.tv_subconnector_property; if (!prop) { DRM_ERROR("Unable to find subconnector property\n"); return 0; @@ -338,38 +333,90 @@ static ssize_t subconnector_show(struct device *device, if (ret) return 0; - return snprintf(buf, PAGE_SIZE, "%s", is_tv ? - drm_get_tv_subconnector_name((int)subconnector) : - drm_get_dvi_i_subconnector_name((int)subconnector)); + return snprintf(buf, PAGE_SIZE, "%s", + drm_get_tv_subconnector_name((int)subconnector)); } -static ssize_t select_subconnector_show(struct device *device, - struct device_attribute *attr, - char *buf) +static ssize_t tv_select_subconnector_show(struct device *device, + struct device_attribute *attr, + char *buf) { struct drm_connector *connector = to_drm_connector(device); struct drm_device *dev = connector->dev; - struct drm_property *prop = NULL; + struct drm_property *prop; uint64_t subconnector; - int is_tv = 0; int ret; switch (connector->connector_type) { - case DRM_MODE_CONNECTOR_DVII: - prop = dev->mode_config.dvi_i_select_subconnector_property; - break; - case DRM_MODE_CONNECTOR_Composite: - case DRM_MODE_CONNECTOR_SVIDEO: - case DRM_MODE_CONNECTOR_Component: - case DRM_MODE_CONNECTOR_TV: - prop = dev->mode_config.tv_select_subconnector_property; - is_tv = 1; - break; - default: - DRM_ERROR("Wrong connector type for this property\n"); - return 0; + case DRM_MODE_CONNECTOR_Composite: + case DRM_MODE_CONNECTOR_SVIDEO: + case DRM_MODE_CONNECTOR_Component: + case DRM_MODE_CONNECTOR_TV: + break; + default: + DRM_ERROR("Wrong connector type for this property\n"); + return 0; + } + + prop = dev->mode_config.tv_select_subconnector_property; + if (!prop) { + DRM_ERROR("Unable to find select subconnector property\n"); + return 0; + } + + ret = drm_object_property_get_value(&connector->base, prop, &subconnector); + if (ret) + return 0; + + return snprintf(buf, PAGE_SIZE, "%s", + drm_get_tv_select_name((int)subconnector)); +} + +static ssize_t dvii_subconnector_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct drm_connector *connector = to_drm_connector(device); + struct drm_device *dev = connector->dev; + struct drm_property *prop; + uint64_t subconnector; + int ret; + + if (connector->connector_type != DRM_MODE_CONNECTOR_DVII) { + DRM_ERROR("Wrong connector type for this property\n"); + return 0; + } + + prop = dev->mode_config.dvi_i_subconnector_property; + if (!prop) { + DRM_ERROR("Unable to find subconnector property\n"); + return 0; + } + + ret = drm_object_property_get_value(&connector->base, prop, &subconnector); + if (ret) + return 0; + + return snprintf(buf, PAGE_SIZE, "%s", + drm_get_dvi_i_subconnector_name((int)subconnector)); +} + +static ssize_t dvii_select_subconnector_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct drm_connector *connector = to_drm_connector(device); + struct drm_device *dev = connector->dev; + struct drm_property *prop; + uint64_t subconnector; + int ret; + + if (connector->connector_type != DRM_MODE_CONNECTOR_DVII) { + DRM_ERROR("Wrong connector type for this property\n"); + return 0; } + prop = dev->mode_config.dvi_i_select_subconnector_property; if (!prop) { DRM_ERROR("Unable to find select subconnector property\n"); return 0; @@ -379,8 +426,7 @@ static ssize_t select_subconnector_show(struct device *device, if (ret) return 0; - return snprintf(buf, PAGE_SIZE, "%s", is_tv ? - drm_get_tv_select_name((int)subconnector) : + return snprintf(buf, PAGE_SIZE, "%s", drm_get_dvi_i_select_name((int)subconnector)); } @@ -397,13 +443,21 @@ static struct attribute *connector_dev_attrs[] = { NULL }; -/* These attributes are for both DVI-I connectors and all types of tv-out. */ -static DEVICE_ATTR_RO(subconnector); -static DEVICE_ATTR_RO(select_subconnector); +static DEVICE_ATTR_RO(tv_subconnector); +static DEVICE_ATTR_RO(tv_select_subconnector); static struct attribute *connector_tv_dev_attrs[] = { - &dev_attr_subconnector.attr, - &dev_attr_select_subconnector.attr, + &dev_attr_tv_subconnector.attr, + &dev_attr_tv_select_subconnector.attr, + NULL +}; + +static DEVICE_ATTR_RO(dvii_subconnector); +static DEVICE_ATTR_RO(dvii_select_subconnector); + +static struct attribute *connector_dvii_dev_attrs[] = { + &dev_attr_dvii_subconnector.attr, + &dev_attr_dvii_select_subconnector.attr, NULL }; @@ -460,7 +514,7 @@ static const struct attribute_group connector_tv_dev_group = { }; static const struct attribute_group connector_dvii_dev_group = { - .attrs = connector_tv_dev_attrs, /* same as tv */ + .attrs = connector_dvii_dev_attrs, .is_visible = connector_is_dvii, }; -- cgit v1.2.3 From cbfa9faea1f6cb2b5d271acb1d4a08295f075b87 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 May 2015 12:14:55 +0300 Subject: drm/sysfs: remove unnecessary connector type checks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These attributes should be exposed for the matching connector types only, so checking is redundant. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_sysfs.c | 32 -------------------------------- 1 file changed, 32 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index 34e4fbcf44ba..487ddf5ffe51 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -312,17 +312,6 @@ static ssize_t tv_subconnector_show(struct device *device, uint64_t subconnector; int ret; - switch (connector->connector_type) { - case DRM_MODE_CONNECTOR_Composite: - case DRM_MODE_CONNECTOR_SVIDEO: - case DRM_MODE_CONNECTOR_Component: - case DRM_MODE_CONNECTOR_TV: - break; - default: - DRM_ERROR("Wrong connector type for this property\n"); - return 0; - } - prop = dev->mode_config.tv_subconnector_property; if (!prop) { DRM_ERROR("Unable to find subconnector property\n"); @@ -347,17 +336,6 @@ static ssize_t tv_select_subconnector_show(struct device *device, uint64_t subconnector; int ret; - switch (connector->connector_type) { - case DRM_MODE_CONNECTOR_Composite: - case DRM_MODE_CONNECTOR_SVIDEO: - case DRM_MODE_CONNECTOR_Component: - case DRM_MODE_CONNECTOR_TV: - break; - default: - DRM_ERROR("Wrong connector type for this property\n"); - return 0; - } - prop = dev->mode_config.tv_select_subconnector_property; if (!prop) { DRM_ERROR("Unable to find select subconnector property\n"); @@ -382,11 +360,6 @@ static ssize_t dvii_subconnector_show(struct device *device, uint64_t subconnector; int ret; - if (connector->connector_type != DRM_MODE_CONNECTOR_DVII) { - DRM_ERROR("Wrong connector type for this property\n"); - return 0; - } - prop = dev->mode_config.dvi_i_subconnector_property; if (!prop) { DRM_ERROR("Unable to find subconnector property\n"); @@ -411,11 +384,6 @@ static ssize_t dvii_select_subconnector_show(struct device *device, uint64_t subconnector; int ret; - if (connector->connector_type != DRM_MODE_CONNECTOR_DVII) { - DRM_ERROR("Wrong connector type for this property\n"); - return 0; - } - prop = dev->mode_config.dvi_i_select_subconnector_property; if (!prop) { DRM_ERROR("Unable to find select subconnector property\n"); -- cgit v1.2.3 From 3d51d2d2f52cb4a4d903f6a604027dc94c5bb9eb Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 12 May 2015 15:21:06 +0200 Subject: drm/atomic-helpers: Update vblank timestamping constants The atomic helpers don't call drm_calc_timestamping_constants, which is a regression compared to the crtc helpers. Fix this. Noticed while reviewing i915 atomic patches from Maarten. v2: Also check state->enable to avoid a warning in dmesg. Reported by Maarten. Cc: Maarten Lankhorst Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic_helper.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 5d30592c83cd..d414e9eea9d8 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -657,6 +657,10 @@ set_routing_links(struct drm_device *dev, struct drm_atomic_state *old_state) crtc->enabled = crtc->state->enable; crtc->x = crtc->primary->state->src_x >> 16; crtc->y = crtc->primary->state->src_y >> 16; + + if (crtc->state->enable) + drm_calc_timestamping_constants(crtc, + &crtc->state->adjusted_mode); } } -- cgit v1.2.3 From 4c18d3010bb722e6ab7d0b80fcf78dd6f95a5a15 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 12 May 2015 15:27:37 +0200 Subject: drm/atomic-helpers: Export drm_atomic_helper_update_legacy_modeset_state This is useful for drivers which have their own modeset infrastructure but want to reuse most of the legacy state frobbery from the helpers. i915 wants this. v2: Add header declaration. Cc: Maarten Lankhorst Reviewed-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic_helper.c | 23 ++++++++++++++++++++--- include/drm/drm_atomic_helper.h | 4 ++++ 2 files changed, 24 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index d414e9eea9d8..1bcd700e3baa 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -619,8 +619,22 @@ disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state) } } -static void -set_routing_links(struct drm_device *dev, struct drm_atomic_state *old_state) +/** + * drm_atomic_helper_update_legacy_modeset_state - update legacy modeset state + * @dev: DRM device + * @old_state: atomic state object with old state structures + * + * This function updates all the various legacy modeset state pointers in + * connectors, encoders and crtcs. It also updates the timestamping constants + * used for precise vblank timestamps by calling + * drm_calc_timestamping_constants(). + * + * Drivers can use this for building their own atomic commit if they don't have + * a pure helper-based modeset implementation. + */ +void +drm_atomic_helper_update_legacy_modeset_state(struct drm_device *dev, + struct drm_atomic_state *old_state) { struct drm_connector *connector; struct drm_connector_state *old_conn_state; @@ -663,6 +677,7 @@ set_routing_links(struct drm_device *dev, struct drm_atomic_state *old_state) &crtc->state->adjusted_mode); } } +EXPORT_SYMBOL(drm_atomic_helper_update_legacy_modeset_state); static void crtc_set_mode(struct drm_device *dev, struct drm_atomic_state *old_state) @@ -741,7 +756,9 @@ void drm_atomic_helper_commit_modeset_disables(struct drm_device *dev, struct drm_atomic_state *old_state) { disable_outputs(dev, old_state); - set_routing_links(dev, old_state); + + drm_atomic_helper_update_legacy_modeset_state(dev, old_state); + crtc_set_mode(dev, old_state); } EXPORT_SYMBOL(drm_atomic_helper_commit_modeset_disables); diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h index d665781eb542..6ee0ee5b6143 100644 --- a/include/drm/drm_atomic_helper.h +++ b/include/drm/drm_atomic_helper.h @@ -43,6 +43,10 @@ int drm_atomic_helper_commit(struct drm_device *dev, void drm_atomic_helper_wait_for_vblanks(struct drm_device *dev, struct drm_atomic_state *old_state); +void +drm_atomic_helper_update_legacy_modeset_state(struct drm_device *dev, + struct drm_atomic_state *old_state); + void drm_atomic_helper_commit_modeset_disables(struct drm_device *dev, struct drm_atomic_state *state); void drm_atomic_helper_commit_modeset_enables(struct drm_device *dev, -- cgit v1.2.3 From b588c92b66c52b6dca293ce554878e8af8fb58cb Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Wed, 13 May 2015 09:56:00 +0200 Subject: drm/i915: get rid of -Iinclude/drm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This results in a warning when building out of tree: "cc1: warning: include/drm: No such file or directory [enabled by default]" Most code already uses #include correctly, so fix the instances that don't. Reported-by: Ville Syrjälä Signed-off-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/Makefile | 2 -- drivers/gpu/drm/i915/i915_gem_userptr.c | 4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index a69002e2257d..957434492864 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -2,8 +2,6 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -ccflags-y := -Iinclude/drm - # Please keep these build lists sorted! # core driver code diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c index 1719078c763a..4039ede158be 100644 --- a/drivers/gpu/drm/i915/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c @@ -22,8 +22,8 @@ * */ -#include "drmP.h" -#include "i915_drm.h" +#include +#include #include "i915_drv.h" #include "i915_trace.h" #include "intel_drv.h" -- cgit v1.2.3 From f9be5f20115441488c8ef1391ef70b681135f0ad Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Wed, 13 May 2015 09:56:01 +0200 Subject: drm/core: get rid of -Iinclude/drm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This results in a warning when building out of tree: "cc1: warning: include/drm: No such file or directory [enabled by default]" Most code already uses #include correctly, so fix the instances that don't. Reported-by: Ville Syrjälä Signed-off-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/Makefile | 2 -- drivers/gpu/drm/drm_flip_work.c | 4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 7d4944e1a60c..4de8d9b006ec 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -2,8 +2,6 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -ccflags-y := -Iinclude/drm - drm-y := drm_auth.o drm_bufs.o drm_cache.o \ drm_context.o drm_dma.o \ drm_fops.o drm_gem.o drm_ioctl.o drm_irq.o \ diff --git a/drivers/gpu/drm/drm_flip_work.c b/drivers/gpu/drm/drm_flip_work.c index 43d9b950ef9f..12dea16f22a8 100644 --- a/drivers/gpu/drm/drm_flip_work.c +++ b/drivers/gpu/drm/drm_flip_work.c @@ -21,8 +21,8 @@ * SOFTWARE. */ -#include "drmP.h" -#include "drm_flip_work.h" +#include +#include /** * drm_flip_work_allocate_task - allocate a flip-work task -- cgit v1.2.3 From 1b26a5e1932beb34c4213934d8faf02217fc40e4 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Wed, 13 May 2015 10:37:25 +0200 Subject: drm/atomic: add drm_atomic_get_existing_*_state helpers There are cases where we want to test if a given object is part of the state, but don't want to add them if they're not. Signed-off-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic.c | 18 +++++++--------- include/drm/drm_atomic.h | 50 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 6e3b78ee7d16..c6277a4a1f2f 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -203,13 +203,12 @@ struct drm_crtc_state * drm_atomic_get_crtc_state(struct drm_atomic_state *state, struct drm_crtc *crtc) { - int ret, index; + int ret, index = drm_crtc_index(crtc); struct drm_crtc_state *crtc_state; - index = drm_crtc_index(crtc); - - if (state->crtc_states[index]) - return state->crtc_states[index]; + crtc_state = drm_atomic_get_existing_crtc_state(state, crtc); + if (crtc_state) + return crtc_state; ret = drm_modeset_lock(&crtc->mutex, state->acquire_ctx); if (ret) @@ -337,13 +336,12 @@ struct drm_plane_state * drm_atomic_get_plane_state(struct drm_atomic_state *state, struct drm_plane *plane) { - int ret, index; + int ret, index = drm_plane_index(plane); struct drm_plane_state *plane_state; - index = drm_plane_index(plane); - - if (state->plane_states[index]) - return state->plane_states[index]; + plane_state = drm_atomic_get_existing_plane_state(state, plane); + if (plane_state) + return plane_state; ret = drm_modeset_lock(&plane->mutex, state->acquire_ctx); if (ret) diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index c157103492b0..d78543067700 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -54,6 +54,56 @@ int drm_atomic_connector_set_property(struct drm_connector *connector, struct drm_connector_state *state, struct drm_property *property, uint64_t val); +/** + * drm_atomic_get_existing_crtc_state - get crtc state, if it exists + * @state: global atomic state object + * @crtc: crtc to grab + * + * This function returns the crtc state for the given crtc, or NULL + * if the crtc is not part of the global atomic state. + */ +static inline struct drm_crtc_state * +drm_atomic_get_existing_crtc_state(struct drm_atomic_state *state, + struct drm_crtc *crtc) +{ + return state->crtc_states[drm_crtc_index(crtc)]; +} + +/** + * drm_atomic_get_existing_plane_state - get plane state, if it exists + * @state: global atomic state object + * @plane: plane to grab + * + * This function returns the plane state for the given plane, or NULL + * if the plane is not part of the global atomic state. + */ +static inline struct drm_plane_state * +drm_atomic_get_existing_plane_state(struct drm_atomic_state *state, + struct drm_plane *plane) +{ + return state->plane_states[drm_plane_index(plane)]; +} + +/** + * drm_atomic_get_existing_connector_state - get connector state, if it exists + * @state: global atomic state object + * @connector: connector to grab + * + * This function returns the connector state for the given connector, + * or NULL if the connector is not part of the global atomic state. + */ +static inline struct drm_connector_state * +drm_atomic_get_existing_connector_state(struct drm_atomic_state *state, + struct drm_connector *connector) +{ + int index = drm_connector_index(connector); + + if (index >= state->num_connector) + return NULL; + + return state->connector_states[index]; +} + int __must_check drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state, struct drm_crtc *crtc); -- cgit v1.2.3 From cf88fca50230042d97651ed71a2bffec111956f4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 2 Apr 2015 19:11:04 -0300 Subject: drm/bridge: dw-hdmi: Staticize dw_hdmi_bridge_funcs Staticize dw_hdmi_bridge_funcs to fix the following sparse warning: drivers/gpu/drm/bridge/dw_hdmi.c:1458:25: warning: symbol 'dw_hdmi_bridge_funcs' was not declared. Should it be static? Signed-off-by: Fabio Estevam Signed-off-by: Thierry Reding --- drivers/gpu/drm/bridge/dw_hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c index 49cafb61d290..594f84c763cf 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.c +++ b/drivers/gpu/drm/bridge/dw_hdmi.c @@ -1457,7 +1457,7 @@ static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { .best_encoder = dw_hdmi_connector_best_encoder, }; -struct drm_bridge_funcs dw_hdmi_bridge_funcs = { +static struct drm_bridge_funcs dw_hdmi_bridge_funcs = { .enable = dw_hdmi_bridge_enable, .disable = dw_hdmi_bridge_disable, .pre_enable = dw_hdmi_bridge_nop, -- cgit v1.2.3 From 394e5b6d8651db92fd55eac78747a3b13d40f7b7 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 14 May 2015 16:31:29 +0200 Subject: drm/bridge: ptn3460: Fix I2C ID table to match the reported modalias I2C drivers that support OF, have both an I2C and OF device ID tables that are used to fill the supported module aliases. But currently the I2C core only uses the OF table to match a device with a driver and the aliases information are always reported in the form i2c:. The client->name is used as the name postfix and when booting with OF this is obtained with of_modalias_node() which drops the compatible string vendor prefix. So for I2C drivers, the I2C and OF device ID tables should be keep in sync in order to make module auto-loading to work but the I2C device entries shouldn't have the vendor prefix since that is not reported. Before this patch: MODALIAS=i2c:ptn3460 $ modinfo | grep alias alias: i2c:nxp,ptn3460 alias: of:N*T*Cnxp,ptn3460* After this patch: MODALIAS=i2c:ptn3460 $ modinfo | grep alias alias: i2c:ptn3460 alias: of:N*T*Cnxp,ptn3460* Signed-off-by: Javier Martinez Canillas Reviewed-by: Doug Anderson Signed-off-by: Thierry Reding --- drivers/gpu/drm/bridge/ptn3460.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/bridge/ptn3460.c b/drivers/gpu/drm/bridge/ptn3460.c index 9d2f053382e1..2cc15419088d 100644 --- a/drivers/gpu/drm/bridge/ptn3460.c +++ b/drivers/gpu/drm/bridge/ptn3460.c @@ -389,7 +389,7 @@ static int ptn3460_remove(struct i2c_client *client) } static const struct i2c_device_id ptn3460_i2c_table[] = { - {"nxp,ptn3460", 0}, + {"ptn3460", 0}, {}, }; MODULE_DEVICE_TABLE(i2c, ptn3460_i2c_table); -- cgit v1.2.3 From 744b058827b3db9a4f6027522dd9c73a208c2d31 Mon Sep 17 00:00:00 2001 From: Gustavo Padovan Date: Fri, 15 May 2015 16:12:27 -0300 Subject: drm/atomic: remove duplicated assignment of old_plane_state old_plane_state is already assigned to old_state->plane_states[i] inside for_each_plane_in_state(). Here we remove an the extra assignment. Signed-off-by: Gustavo Padovan Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic_helper.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 1bcd700e3baa..dc67ff671917 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -1151,8 +1151,6 @@ void drm_atomic_helper_commit_planes(struct drm_device *dev, if (!funcs) continue; - old_plane_state = old_state->plane_states[i]; - /* * Special-case disabling the plane if drivers support it. */ -- cgit v1.2.3 From 036ef5733ba433760a3512bb5f7a155946e2df05 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Mon, 18 May 2015 10:06:40 +0200 Subject: drm/atomic: Allow drivers to subclass drm_atomic_state, v3 Drivers may need to store the state of shared resources, such as PLLs or FIFO space, into the atomic state. Allow this by making it possible to subclass drm_atomic_state. Changes since v1: - Change member names for functions to atomic_state_(alloc,clear) - Change __drm_atomic_state_new to drm_atomic_state_init - Allow free function to be overridden too, in case extra memory is allocated in alloc. Changes since v2: - Rename *_default_free to default_release, to make clear it doesn't free the state object itself. Cc: dri-devel@lists.freedesktop.org Acked-by: Ander Conselvan de Oliveira Signed-off-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic.c | 116 ++++++++++++++++++++++++++++++++----------- include/drm/drm_atomic.h | 5 ++ include/drm/drm_crtc.h | 6 +++ 3 files changed, 99 insertions(+), 28 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index c6277a4a1f2f..cd1b16b25716 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -30,7 +30,15 @@ #include #include -static void kfree_state(struct drm_atomic_state *state) +/** + * drm_atomic_state_default_release - + * release memory initialized by drm_atomic_state_init + * @state: atomic state + * + * Free all the memory allocated by drm_atomic_state_init. + * This is useful for drivers that subclass the atomic state. + */ +void drm_atomic_state_default_release(struct drm_atomic_state *state) { kfree(state->connectors); kfree(state->connector_states); @@ -38,24 +46,20 @@ static void kfree_state(struct drm_atomic_state *state) kfree(state->crtc_states); kfree(state->planes); kfree(state->plane_states); - kfree(state); } +EXPORT_SYMBOL(drm_atomic_state_default_release); /** - * drm_atomic_state_alloc - allocate atomic state + * drm_atomic_state_init - init new atomic state * @dev: DRM device + * @state: atomic state * - * This allocates an empty atomic state to track updates. + * Default implementation for filling in a new atomic state. + * This is useful for drivers that subclass the atomic state. */ -struct drm_atomic_state * -drm_atomic_state_alloc(struct drm_device *dev) +int +drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state *state) { - struct drm_atomic_state *state; - - state = kzalloc(sizeof(*state), GFP_KERNEL); - if (!state) - return NULL; - /* TODO legacy paths should maybe do a better job about * setting this appropriately? */ @@ -92,31 +96,50 @@ drm_atomic_state_alloc(struct drm_device *dev) state->dev = dev; - DRM_DEBUG_ATOMIC("Allocate atomic state %p\n", state); + DRM_DEBUG_ATOMIC("Allocated atomic state %p\n", state); - return state; + return 0; fail: - kfree_state(state); + drm_atomic_state_default_release(state); + return -ENOMEM; +} +EXPORT_SYMBOL(drm_atomic_state_init); + +/** + * drm_atomic_state_alloc - allocate atomic state + * @dev: DRM device + * + * This allocates an empty atomic state to track updates. + */ +struct drm_atomic_state * +drm_atomic_state_alloc(struct drm_device *dev) +{ + struct drm_mode_config *config = &dev->mode_config; + struct drm_atomic_state *state; + + if (!config->funcs->atomic_state_alloc) { + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (!state) + return NULL; + if (drm_atomic_state_init(dev, state) < 0) { + kfree(state); + return NULL; + } + return state; + } - return NULL; + return config->funcs->atomic_state_alloc(dev); } EXPORT_SYMBOL(drm_atomic_state_alloc); /** - * drm_atomic_state_clear - clear state object + * drm_atomic_state_default_clear - clear base atomic state * @state: atomic state * - * When the w/w mutex algorithm detects a deadlock we need to back off and drop - * all locks. So someone else could sneak in and change the current modeset - * configuration. Which means that all the state assembled in @state is no - * longer an atomic update to the current state, but to some arbitrary earlier - * state. Which could break assumptions the driver's ->atomic_check likely - * relies on. - * - * Hence we must clear all cached state and completely start over, using this - * function. + * Default implementation for clearing atomic state. + * This is useful for drivers that subclass the atomic state. */ -void drm_atomic_state_clear(struct drm_atomic_state *state) +void drm_atomic_state_default_clear(struct drm_atomic_state *state) { struct drm_device *dev = state->dev; struct drm_mode_config *config = &dev->mode_config; @@ -162,6 +185,32 @@ void drm_atomic_state_clear(struct drm_atomic_state *state) state->plane_states[i] = NULL; } } +EXPORT_SYMBOL(drm_atomic_state_default_clear); + +/** + * drm_atomic_state_clear - clear state object + * @state: atomic state + * + * When the w/w mutex algorithm detects a deadlock we need to back off and drop + * all locks. So someone else could sneak in and change the current modeset + * configuration. Which means that all the state assembled in @state is no + * longer an atomic update to the current state, but to some arbitrary earlier + * state. Which could break assumptions the driver's ->atomic_check likely + * relies on. + * + * Hence we must clear all cached state and completely start over, using this + * function. + */ +void drm_atomic_state_clear(struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + struct drm_mode_config *config = &dev->mode_config; + + if (config->funcs->atomic_state_clear) + config->funcs->atomic_state_clear(state); + else + drm_atomic_state_default_clear(state); +} EXPORT_SYMBOL(drm_atomic_state_clear); /** @@ -173,14 +222,25 @@ EXPORT_SYMBOL(drm_atomic_state_clear); */ void drm_atomic_state_free(struct drm_atomic_state *state) { + struct drm_device *dev; + struct drm_mode_config *config; + if (!state) return; + dev = state->dev; + config = &dev->mode_config; + drm_atomic_state_clear(state); DRM_DEBUG_ATOMIC("Freeing atomic state %p\n", state); - kfree_state(state); + if (config->funcs->atomic_state_free) { + config->funcs->atomic_state_free(state); + } else { + drm_atomic_state_default_release(state); + kfree(state); + } } EXPORT_SYMBOL(drm_atomic_state_free); diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index d78543067700..f0d3a7387d99 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -35,6 +35,11 @@ drm_atomic_state_alloc(struct drm_device *dev); void drm_atomic_state_clear(struct drm_atomic_state *state); void drm_atomic_state_free(struct drm_atomic_state *state); +int __must_check +drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state *state); +void drm_atomic_state_default_clear(struct drm_atomic_state *state); +void drm_atomic_state_default_release(struct drm_atomic_state *state); + struct drm_crtc_state * __must_check drm_atomic_get_crtc_state(struct drm_atomic_state *state, struct drm_crtc *crtc); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 5626191f3af0..37c44f27cb9f 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -979,6 +979,9 @@ struct drm_mode_set { * @atomic_check: check whether a given atomic state update is possible * @atomic_commit: commit an atomic state update previously verified with * atomic_check() + * @atomic_state_alloc: allocate a new atomic state + * @atomic_state_clear: clear the atomic state + * @atomic_state_free: free the atomic state * * Some global (i.e. not per-CRTC, connector, etc) mode setting functions that * involve drivers. @@ -994,6 +997,9 @@ struct drm_mode_config_funcs { int (*atomic_commit)(struct drm_device *dev, struct drm_atomic_state *a, bool async); + struct drm_atomic_state *(*atomic_state_alloc)(struct drm_device *dev); + void (*atomic_state_clear)(struct drm_atomic_state *state); + void (*atomic_state_free)(struct drm_atomic_state *state); }; /** -- cgit v1.2.3 From a92bf307b56288c056dea7dc3dc05bb6d3cf71d8 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 19 May 2015 09:03:49 +0200 Subject: drm/bridge: ps8622: Pass flags to devm_gpiod_get() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since 39b2bbe3d715 (gpio: add flags argument to gpiod_get*() functions) which appeared in v3.17-rc1, the gpiod_get* functions take an additional parameter that allows to specify direction and initial value for output. Use this to simplify the driver. Furthermore this is one caller less that stops us making the flags argument to gpiod_get*() mandatory. Signed-off-by: Uwe Kleine-König Signed-off-by: Thierry Reding --- drivers/gpu/drm/bridge/ps8622.c | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/bridge/ps8622.c b/drivers/gpu/drm/bridge/ps8622.c index e895aa7ea353..9534607cbd10 100644 --- a/drivers/gpu/drm/bridge/ps8622.c +++ b/drivers/gpu/drm/bridge/ps8622.c @@ -581,31 +581,21 @@ static int ps8622_probe(struct i2c_client *client, ps8622->v12 = NULL; } - ps8622->gpio_slp = devm_gpiod_get(dev, "sleep"); + ps8622->gpio_slp = devm_gpiod_get(dev, "sleep", GPIOD_OUT_HIGH); if (IS_ERR(ps8622->gpio_slp)) { ret = PTR_ERR(ps8622->gpio_slp); dev_err(dev, "cannot get gpio_slp %d\n", ret); return ret; } - ret = gpiod_direction_output(ps8622->gpio_slp, 1); - if (ret) { - dev_err(dev, "cannot configure gpio_slp\n"); - return ret; - } - ps8622->gpio_rst = devm_gpiod_get(dev, "reset"); - if (IS_ERR(ps8622->gpio_rst)) { - ret = PTR_ERR(ps8622->gpio_rst); - dev_err(dev, "cannot get gpio_rst %d\n", ret); - return ret; - } /* * Assert the reset pin high to avoid the bridge being * initialized prematurely */ - ret = gpiod_direction_output(ps8622->gpio_rst, 1); - if (ret) { - dev_err(dev, "cannot configure gpio_rst\n"); + ps8622->gpio_rst = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(ps8622->gpio_rst)) { + ret = PTR_ERR(ps8622->gpio_rst); + dev_err(dev, "cannot get gpio_rst %d\n", ret); return ret; } -- cgit v1.2.3 From c06ea0ada75bd0ea6b92d592e7f69e64455520b4 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 19 May 2015 09:15:56 +0200 Subject: drm/bridge: ptn3460: Pass flags to devm_gpiod_get() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since 39b2bbe3d715 (gpio: add flags argument to gpiod_get*() functions) which appeared in v3.17-rc1, the gpiod_get* functions take an additional parameter that allows to specify direction and initial value for output. Use this to simplify the driver. Furthermore this is one caller less that stops us making the flags argument to gpiod_get*() mandatory. Signed-off-by: Uwe Kleine-König Signed-off-by: Thierry Reding --- drivers/gpu/drm/bridge/ptn3460.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/bridge/ptn3460.c b/drivers/gpu/drm/bridge/ptn3460.c index 2cc15419088d..ee7ba3cecf71 100644 --- a/drivers/gpu/drm/bridge/ptn3460.c +++ b/drivers/gpu/drm/bridge/ptn3460.c @@ -330,32 +330,23 @@ static int ptn3460_probe(struct i2c_client *client, ptn_bridge->client = client; - ptn_bridge->gpio_pd_n = devm_gpiod_get(&client->dev, "powerdown"); + ptn_bridge->gpio_pd_n = devm_gpiod_get(&client->dev, "powerdown", + GPIOD_OUT_HIGH); if (IS_ERR(ptn_bridge->gpio_pd_n)) { ret = PTR_ERR(ptn_bridge->gpio_pd_n); dev_err(dev, "cannot get gpio_pd_n %d\n", ret); return ret; } - ret = gpiod_direction_output(ptn_bridge->gpio_pd_n, 1); - if (ret) { - DRM_ERROR("cannot configure gpio_pd_n\n"); - return ret; - } - - ptn_bridge->gpio_rst_n = devm_gpiod_get(&client->dev, "reset"); - if (IS_ERR(ptn_bridge->gpio_rst_n)) { - ret = PTR_ERR(ptn_bridge->gpio_rst_n); - DRM_ERROR("cannot get gpio_rst_n %d\n", ret); - return ret; - } /* * Request the reset pin low to avoid the bridge being * initialized prematurely */ - ret = gpiod_direction_output(ptn_bridge->gpio_rst_n, 0); - if (ret) { - DRM_ERROR("cannot configure gpio_rst_n\n"); + ptn_bridge->gpio_rst_n = devm_gpiod_get(&client->dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(ptn_bridge->gpio_rst_n)) { + ret = PTR_ERR(ptn_bridge->gpio_rst_n); + DRM_ERROR("cannot get gpio_rst_n %d\n", ret); return ret; } -- cgit v1.2.3 From 1549fcd15cab5e59beb7203583e0a70349dda7c1 Mon Sep 17 00:00:00 2001 From: Firo Yang Date: Thu, 23 Apr 2015 17:58:05 +0800 Subject: drm/amdkfd: Remove unessary void pointer cast kmalloc() returns a void pointer - no need to cast it in drivers/gpu/drm/amd/amdkfd/kfd_process.c::kfd_process_destroy_delayed() Signed-off-by: Firo Yang Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 945d6226dc51..4d7bc95a95d9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -203,8 +203,7 @@ static void kfd_process_destroy_delayed(struct rcu_head *rcu) mmdrop(p->mm); - work = (struct kfd_process_release_work *) - kmalloc(sizeof(struct kfd_process_release_work), GFP_ATOMIC); + work = kmalloc(sizeof(struct kfd_process_release_work), GFP_ATOMIC); if (work) { INIT_WORK((struct work_struct *) work, kfd_process_wq_release); -- cgit v1.2.3 From 8856d8e048aa12ee056e24046e22fea7c77817a6 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Mon, 4 May 2015 15:53:15 +0300 Subject: drm/amdkfd: reformat some debug prints Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 15 +++++++-------- drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 5 +++-- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 17e56dcc8540..e621eba63126 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -142,14 +142,13 @@ int kfd_doorbell_mmap(struct kfd_process *process, struct vm_area_struct *vma) vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - pr_debug("kfd: mapping doorbell page in kfd_doorbell_mmap\n" - " target user address == 0x%08llX\n" - " physical address == 0x%08llX\n" - " vm_flags == 0x%04lX\n" - " size == 0x%04lX\n", - (unsigned long long) vma->vm_start, address, vma->vm_flags, - doorbell_process_allocation()); - + pr_debug("mapping doorbell page:\n"); + pr_debug(" target user address == 0x%08llX\n", + (unsigned long long) vma->vm_start); + pr_debug(" physical address == 0x%08llX\n", address); + pr_debug(" vm_flags == 0x%04lX\n", vma->vm_flags); + pr_debug(" size == 0x%04lX\n", + doorbell_process_allocation()); return io_remap_pfn_range(vma, vma->vm_start, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index c7d298e62c96..8fa894100290 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c @@ -215,8 +215,9 @@ static int acquire_packet_buffer(struct kernel_queue *kq, queue_address = (unsigned int *)kq->pq_kernel_addr; queue_size_dwords = kq->queue->properties.queue_size / sizeof(uint32_t); - pr_debug("amdkfd: In func %s\nrptr: %d\nwptr: %d\nqueue_address 0x%p\n", - __func__, rptr, wptr, queue_address); + pr_debug("rptr: %d\n", rptr); + pr_debug("wptr: %d\n", wptr); + pr_debug("queue_address 0x%p\n", queue_address); available_size = (rptr - 1 - wptr + queue_size_dwords) % queue_size_dwords; -- cgit v1.2.3 From d42af779fb2cf23bbe218c91b44f4979f18bc910 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Tue, 5 May 2015 11:51:31 +0300 Subject: drm/amdkfd: Use new struct for asic specific ops This patch creates a new structure for asic specific operations, instead of using the existing structure of operations. This is done to make the code flow more logic, readable and maintainable. The change is done only to the device queue manager module at this point. Signed-off-by: Oded Gabbay Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 18 +++++++++++++++--- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c | 2 +- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c | 2 +- 3 files changed, 17 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 488f51d19427..650ae1c9ceca 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -120,6 +120,18 @@ struct device_queue_manager_ops { uint64_t alternate_aperture_size); }; +struct device_queue_manager_asic_ops { + int (*register_process)(struct device_queue_manager *dqm, + struct qcm_process_device *qpd); + int (*initialize)(struct device_queue_manager *dqm); + bool (*set_cache_memory_policy)(struct device_queue_manager *dqm, + struct qcm_process_device *qpd, + enum cache_policy default_policy, + enum cache_policy alternate_policy, + void __user *alternate_aperture_base, + uint64_t alternate_aperture_size); +}; + /** * struct device_queue_manager * @@ -134,7 +146,7 @@ struct device_queue_manager_ops { struct device_queue_manager { struct device_queue_manager_ops ops; - struct device_queue_manager_ops ops_asic_specific; + struct device_queue_manager_asic_ops ops_asic_specific; struct mqd_manager *mqds[KFD_MQD_TYPE_MAX]; struct packet_manager packets; @@ -157,8 +169,8 @@ struct device_queue_manager { bool active_runlist; }; -void device_queue_manager_init_cik(struct device_queue_manager_ops *ops); -void device_queue_manager_init_vi(struct device_queue_manager_ops *ops); +void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops); +void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops); void program_sh_mem_settings(struct device_queue_manager *dqm, struct qcm_process_device *qpd); int init_pipelines(struct device_queue_manager *dqm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c index 5469efe0523e..292d13ff3ef5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c @@ -34,7 +34,7 @@ static int register_process_cik(struct device_queue_manager *dqm, struct qcm_process_device *qpd); static int initialize_cpsch_cik(struct device_queue_manager *dqm); -void device_queue_manager_init_cik(struct device_queue_manager_ops *ops) +void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops) { ops->set_cache_memory_policy = set_cache_memory_policy_cik; ops->register_process = register_process_cik; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c index 20553dcd257d..8b00ccf1f795 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c @@ -33,7 +33,7 @@ static int register_process_vi(struct device_queue_manager *dqm, struct qcm_process_device *qpd); static int initialize_cpsch_vi(struct device_queue_manager *dqm); -void device_queue_manager_init_vi(struct device_queue_manager_ops *ops) +void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops) { pr_warn("amdkfd: VI DQM is not currently supported\n"); -- cgit v1.2.3 From 3e3f6e1a90a890e0cea4ec6d6f98e1fa94255de8 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Tue, 5 May 2015 11:51:39 +0300 Subject: drm/amdkfd: make the sdma vm init to be asic specific Signed-off-by: Oded Gabbay Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 15 +-------------- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 3 +++ .../gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c | 16 ++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c | 8 ++++++++ 4 files changed, 28 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 69af73f15310..1eb102295de0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -614,19 +614,6 @@ static void deallocate_sdma_queue(struct device_queue_manager *dqm, set_bit(sdma_queue_id, (unsigned long *)&dqm->sdma_bitmap); } -static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, - struct qcm_process_device *qpd) -{ - uint32_t value = SDMA_ATC; - - if (q->process->is_32bit_user_mode) - value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd)); - else - value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64( - qpd_to_pdd(qpd))); - q->properties.sdma_vm_addr = value; -} - static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm, struct queue *q, struct qcm_process_device *qpd) @@ -649,7 +636,7 @@ static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm, pr_debug(" sdma queue id: %d\n", q->properties.sdma_queue_id); pr_debug(" sdma engine id: %d\n", q->properties.sdma_engine_id); - init_sdma_vm(dqm, q, qpd); + dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd); retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj, &q->gart_mqd_addr, &q->properties); if (retval != 0) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 650ae1c9ceca..57278e2d72e0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -130,6 +130,9 @@ struct device_queue_manager_asic_ops { enum cache_policy alternate_policy, void __user *alternate_aperture_base, uint64_t alternate_aperture_size); + void (*init_sdma_vm)(struct device_queue_manager *dqm, + struct queue *q, + struct qcm_process_device *qpd); }; /** diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c index 292d13ff3ef5..9ce8a20a7aff 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c @@ -33,12 +33,15 @@ static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, static int register_process_cik(struct device_queue_manager *dqm, struct qcm_process_device *qpd); static int initialize_cpsch_cik(struct device_queue_manager *dqm); +static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd); void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops) { ops->set_cache_memory_policy = set_cache_memory_policy_cik; ops->register_process = register_process_cik; ops->initialize = initialize_cpsch_cik; + ops->init_sdma_vm = init_sdma_vm; } static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) @@ -129,6 +132,19 @@ static int register_process_cik(struct device_queue_manager *dqm, return 0; } +static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd) +{ + uint32_t value = SDMA_ATC; + + if (q->process->is_32bit_user_mode) + value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd)); + else + value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64( + qpd_to_pdd(qpd))); + q->properties.sdma_vm_addr = value; +} + static int initialize_cpsch_cik(struct device_queue_manager *dqm) { return init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm)); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c index 8b00ccf1f795..4c15212a3899 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c @@ -32,6 +32,8 @@ static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, static int register_process_vi(struct device_queue_manager *dqm, struct qcm_process_device *qpd); static int initialize_cpsch_vi(struct device_queue_manager *dqm); +static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd); void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops) { @@ -40,6 +42,7 @@ void device_queue_manager_init_vi(struct device_queue_manager_asic_ops *ops) ops->set_cache_memory_policy = set_cache_memory_policy_vi; ops->register_process = register_process_vi; ops->initialize = initialize_cpsch_vi; + ops->init_sdma_vm = init_sdma_vm; } static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, @@ -58,6 +61,11 @@ static int register_process_vi(struct device_queue_manager *dqm, return -1; } +static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd) +{ +} + static int initialize_cpsch_vi(struct device_queue_manager *dqm) { return 0; -- cgit v1.2.3 From d36b94fcf0c812b04fff483e1b423f7d5042766e Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Thu, 5 Mar 2015 15:13:18 +0200 Subject: drm/radeon: Add init interrupt kfd->kgd interface This patch adds a new interface function to the kfd->kgd interface. The function is kgd_init_interrupts() and its function is to initialize a pipe's interrupts. The function currently enables the timestamp interrupt and the bad opcode interrupt. Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 2 ++ drivers/gpu/drm/radeon/cik_reg.h | 2 ++ drivers/gpu/drm/radeon/cikd.h | 1 + drivers/gpu/drm/radeon/radeon_kfd.c | 21 ++++++++++++++++++++- 4 files changed, 25 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index dabd94446b7b..4ea21ae88b07 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -144,6 +144,8 @@ struct kfd2kgd_calls { int (*init_pipeline)(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr); + int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id); + int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr); diff --git a/drivers/gpu/drm/radeon/cik_reg.h b/drivers/gpu/drm/radeon/cik_reg.h index f667347d8157..0ec5d53eb6fb 100644 --- a/drivers/gpu/drm/radeon/cik_reg.h +++ b/drivers/gpu/drm/radeon/cik_reg.h @@ -149,6 +149,8 @@ #define KFD_CIK_SDMA_QUEUE_OFFSET 0x200 +#define CPC_INT_CNTL 0xC2D0 + #define CP_HQD_IQ_RPTR 0xC970u #define AQL_ENABLE (1U << 0) #define SDMA0_RLC0_RB_CNTL 0xD400u diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index 0089d837a8e3..b33ba3b0808b 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h @@ -1335,6 +1335,7 @@ # define CNTX_EMPTY_INT_ENABLE (1 << 20) # define PRIV_INSTR_INT_ENABLE (1 << 22) # define PRIV_REG_INT_ENABLE (1 << 23) +# define OPCODE_ERROR_INT_ENABLE (1 << 24) # define TIME_STAMP_INT_ENABLE (1 << 26) # define CP_RINGID2_INT_ENABLE (1 << 29) # define CP_RINGID1_INT_ENABLE (1 << 30) diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c index 3db23007cdf4..813a416db538 100644 --- a/drivers/gpu/drm/radeon/radeon_kfd.c +++ b/drivers/gpu/drm/radeon/radeon_kfd.c @@ -66,7 +66,7 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr); - +static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr); static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); @@ -89,6 +89,7 @@ static const struct kfd2kgd_calls kfd2kgd = { .program_sh_mem_settings = kgd_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, .init_pipeline = kgd_init_pipeline, + .init_interrupts = kgd_init_interrupts, .hqd_load = kgd_hqd_load, .hqd_sdma_load = kgd_hqd_sdma_load, .hqd_is_occupied = kgd_hqd_is_occupied, @@ -407,6 +408,24 @@ static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, return 0; } +static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) +{ + uint32_t mec; + uint32_t pipe; + + mec = (pipe_id / CIK_PIPE_PER_MEC) + 1; + pipe = (pipe_id % CIK_PIPE_PER_MEC); + + lock_srbm(kgd, mec, pipe, 0, 0); + + write_register(kgd, CPC_INT_CNTL, + TIME_STAMP_INT_ENABLE | OPCODE_ERROR_INT_ENABLE); + + unlock_srbm(kgd); + + return 0; +} + static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m) { uint32_t retval; -- cgit v1.2.3 From 2249d55827c9e5d5731d7a8622ecd366d8756bbb Mon Sep 17 00:00:00 2001 From: Andrew Lewycky Date: Thu, 17 Jul 2014 01:37:30 +0300 Subject: drm/amdkfd: Add interrupt handling module This patch adds the interrupt handling module, kfd_interrupt.c, and its related members in different data structures to the amdkfd driver. The amdkfd interrupt module maintains an internal interrupt ring per amdkfd device. The internal interrupt ring contains interrupts that needs further handling. The extra handling is deferred to a later time through a workqueue. There's no acknowledgment for the interrupts we use. The hardware simply queues a new interrupt each time without waiting. The fixed-size internal queue means that it's possible for us to lose interrupts because we have no back-pressure to the hardware. However, only interrupts that are "wanted" by amdkfd, are copied into the amdkfd s/w interrupt ring, in order to minimize the chances for overflow of the ring. Signed-off-by: Andrew Lewycky Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_device.c | 22 ++- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 15 ++ drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 181 +++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 17 ++ 5 files changed, 235 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 0f4960148126..cd09c05ee7e4 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -12,5 +12,6 @@ amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \ kfd_kernel_queue_vi.o kfd_packet_manager.o \ kfd_process_queue_manager.o kfd_device_queue_manager.o \ kfd_device_queue_manager_cik.o kfd_device_queue_manager_vi.o \ + kfd_interrupt.o obj-$(CONFIG_HSA_AMD) += amdkfd.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index ca7f2d3af2ff..13c30a099684 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -235,6 +235,13 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, goto kfd_topology_add_device_error; } + if (kfd_interrupt_init(kfd)) { + dev_err(kfd_device, + "Error initializing interrupts for device (%x:%x)\n", + kfd->pdev->vendor, kfd->pdev->device); + goto kfd_interrupt_error; + } + if (!device_iommu_pasid_init(kfd)) { dev_err(kfd_device, "Error initializing iommuv2 for device (%x:%x)\n", @@ -273,6 +280,8 @@ dqm_start_error: device_queue_manager_error: amd_iommu_free_device(kfd->pdev); device_iommu_pasid_error: + kfd_interrupt_exit(kfd); +kfd_interrupt_error: kfd_topology_remove_device(kfd); kfd_topology_add_device_error: kfd_gtt_sa_fini(kfd); @@ -290,6 +299,7 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) if (kfd->init_complete) { device_queue_manager_uninit(kfd->dqm); amd_iommu_free_device(kfd->pdev); + kfd_interrupt_exit(kfd); kfd_topology_remove_device(kfd); kfd_gtt_sa_fini(kfd); kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem); @@ -333,7 +343,17 @@ int kgd2kfd_resume(struct kfd_dev *kfd) /* This is called directly from KGD at ISR. */ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) { - /* Process interrupts / schedule work as necessary */ + if (!kfd->init_complete) + return; + + spin_lock(&kfd->interrupt_lock); + + if (kfd->interrupts_active + && interrupt_is_wanted(kfd, ih_ring_entry) + && enqueue_ih_ring_entry(kfd, ih_ring_entry)) + schedule_work(&kfd->interrupt_work); + + spin_unlock(&kfd->interrupt_lock); } static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 1eb102295de0..078092c5a59f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -522,6 +522,17 @@ int init_pipelines(struct device_queue_manager *dqm, return 0; } +static void init_interrupts(struct device_queue_manager *dqm) +{ + unsigned int i; + + BUG_ON(dqm == NULL); + + for (i = 0 ; i < get_pipes_num(dqm) ; i++) + dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, + i + get_first_pipe(dqm)); +} + static int init_scheduler(struct device_queue_manager *dqm) { int retval; @@ -581,6 +592,7 @@ static void uninitialize_nocpsch(struct device_queue_manager *dqm) static int start_nocpsch(struct device_queue_manager *dqm) { + init_interrupts(dqm); return 0; } @@ -737,6 +749,9 @@ static int start_cpsch(struct device_queue_manager *dqm) dqm->fence_addr = dqm->fence_mem->cpu_ptr; dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; + + init_interrupts(dqm); + list_for_each_entry(node, &dqm->queues, list) if (node->qpd->pqm->process && dqm->dev) kfd_bind_process_to_device(dqm->dev, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c new file mode 100644 index 000000000000..5383dd05710d --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c @@ -0,0 +1,181 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * KFD Interrupts. + * + * AMD GPUs deliver interrupts by pushing an interrupt description onto the + * interrupt ring and then sending an interrupt. KGD receives the interrupt + * in ISR and sends us a pointer to each new entry on the interrupt ring. + * + * We generally can't process interrupt-signaled events from ISR, so we call + * out to each interrupt client module (currently only the scheduler) to ask if + * each interrupt is interesting. If they return true, then it requires further + * processing so we copy it to an internal interrupt ring and call each + * interrupt client again from a work-queue. + * + * There's no acknowledgment for the interrupts we use. The hardware simply + * queues a new interrupt each time without waiting. + * + * The fixed-size internal queue means that it's possible for us to lose + * interrupts because we have no back-pressure to the hardware. + */ + +#include +#include +#include "kfd_priv.h" + +#define KFD_INTERRUPT_RING_SIZE 1024 + +static void interrupt_wq(struct work_struct *); + +int kfd_interrupt_init(struct kfd_dev *kfd) +{ + void *interrupt_ring = kmalloc_array(KFD_INTERRUPT_RING_SIZE, + kfd->device_info->ih_ring_entry_size, + GFP_KERNEL); + if (!interrupt_ring) + return -ENOMEM; + + kfd->interrupt_ring = interrupt_ring; + kfd->interrupt_ring_size = + KFD_INTERRUPT_RING_SIZE * kfd->device_info->ih_ring_entry_size; + atomic_set(&kfd->interrupt_ring_wptr, 0); + atomic_set(&kfd->interrupt_ring_rptr, 0); + + spin_lock_init(&kfd->interrupt_lock); + + INIT_WORK(&kfd->interrupt_work, interrupt_wq); + + kfd->interrupts_active = true; + + /* + * After this function returns, the interrupt will be enabled. This + * barrier ensures that the interrupt running on a different processor + * sees all the above writes. + */ + smp_wmb(); + + return 0; +} + +void kfd_interrupt_exit(struct kfd_dev *kfd) +{ + /* + * Stop the interrupt handler from writing to the ring and scheduling + * workqueue items. The spinlock ensures that any interrupt running + * after we have unlocked sees interrupts_active = false. + */ + unsigned long flags; + + spin_lock_irqsave(&kfd->interrupt_lock, flags); + kfd->interrupts_active = false; + spin_unlock_irqrestore(&kfd->interrupt_lock, flags); + + /* + * Flush_scheduled_work ensures that there are no outstanding + * work-queue items that will access interrupt_ring. New work items + * can't be created because we stopped interrupt handling above. + */ + flush_scheduled_work(); + + kfree(kfd->interrupt_ring); +} + +/* + * This assumes that it can't be called concurrently with itself + * but only with dequeue_ih_ring_entry. + */ +bool enqueue_ih_ring_entry(struct kfd_dev *kfd, const void *ih_ring_entry) +{ + unsigned int rptr = atomic_read(&kfd->interrupt_ring_rptr); + unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr); + + if ((rptr - wptr) % kfd->interrupt_ring_size == + kfd->device_info->ih_ring_entry_size) { + /* This is very bad, the system is likely to hang. */ + dev_err_ratelimited(kfd_chardev(), + "Interrupt ring overflow, dropping interrupt.\n"); + return false; + } + + memcpy(kfd->interrupt_ring + wptr, ih_ring_entry, + kfd->device_info->ih_ring_entry_size); + + wptr = (wptr + kfd->device_info->ih_ring_entry_size) % + kfd->interrupt_ring_size; + smp_wmb(); /* Ensure memcpy'd data is visible before wptr update. */ + atomic_set(&kfd->interrupt_ring_wptr, wptr); + + return true; +} + +/* + * This assumes that it can't be called concurrently with itself + * but only with enqueue_ih_ring_entry. + */ +static bool dequeue_ih_ring_entry(struct kfd_dev *kfd, void *ih_ring_entry) +{ + /* + * Assume that wait queues have an implicit barrier, i.e. anything that + * happened in the ISR before it queued work is visible. + */ + + unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr); + unsigned int rptr = atomic_read(&kfd->interrupt_ring_rptr); + + if (rptr == wptr) + return false; + + memcpy(ih_ring_entry, kfd->interrupt_ring + rptr, + kfd->device_info->ih_ring_entry_size); + + rptr = (rptr + kfd->device_info->ih_ring_entry_size) % + kfd->interrupt_ring_size; + + /* + * Ensure the rptr write update is not visible until + * memcpy has finished reading. + */ + smp_mb(); + atomic_set(&kfd->interrupt_ring_rptr, rptr); + + return true; +} + +static void interrupt_wq(struct work_struct *work) +{ + struct kfd_dev *dev = container_of(work, struct kfd_dev, + interrupt_work); + + uint32_t ih_ring_entry[DIV_ROUND_UP( + dev->device_info->ih_ring_entry_size, + sizeof(uint32_t))]; + + while (dequeue_ih_ring_entry(dev, ih_ring_entry)) + ; +} + +bool interrupt_is_wanted(struct kfd_dev *dev, const uint32_t *ih_ring_entry) +{ + return false; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index f21fccebd75b..34c766208e8a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -161,10 +161,23 @@ struct kfd_dev { unsigned int gtt_sa_chunk_size; unsigned int gtt_sa_num_of_chunks; + /* Interrupts */ + void *interrupt_ring; + size_t interrupt_ring_size; + atomic_t interrupt_ring_rptr; + atomic_t interrupt_ring_wptr; + struct work_struct interrupt_work; + spinlock_t interrupt_lock; + /* QCM Device instance */ struct device_queue_manager *dqm; bool init_complete; + /* + * Interrupts of interest to KFD are copied + * from the HW ring into a SW ring. + */ + bool interrupts_active; }; /* KGD2KFD callbacks */ @@ -555,7 +568,11 @@ struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev); struct kfd_dev *kfd_topology_enum_kfd_devices(uint8_t idx); /* Interrupts */ +int kfd_interrupt_init(struct kfd_dev *dev); +void kfd_interrupt_exit(struct kfd_dev *dev); void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); +bool enqueue_ih_ring_entry(struct kfd_dev *kfd, const void *ih_ring_entry); +bool interrupt_is_wanted(struct kfd_dev *dev, const uint32_t *ih_ring_entry); /* Power Management */ void kgd2kfd_suspend(struct kfd_dev *kfd); -- cgit v1.2.3 From 29a5d3eb9a7612b26ba098a0db65e54372612d07 Mon Sep 17 00:00:00 2001 From: Andrew Lewycky Date: Sun, 7 Dec 2014 17:05:11 +0200 Subject: drm/amdkfd: add events IOCTL set definitions - AMDKFD_IOC_CREATE_EVENT: Creates a new event of a specified type - AMDKFD_IOC_DESTROY_EVENT: Destroys an existing event - AMDKFD_IOC_SET_EVENT: Signal an existing event - AMDKFD_IOC_RESET_EVENT: Reset an existing event - AMDKFD_IOC_WAIT_EVENTS: Wait on event(s) until they are signaled v2: - Move the limit of the signal events to kfd_ioctl.h so it can be used by userspace v3: - Change all bool fields in struct kfd_memory_exception_failure to uint32_t Signed-off-by: Andrew Lewycky Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 45 +++++++++++++++ include/uapi/linux/kfd_ioctl.h | 96 +++++++++++++++++++++++++++++++- 2 files changed, 139 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 19a4fba46e4e..9933b2efe5dd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -514,6 +514,36 @@ static int kfd_ioctl_get_process_apertures(struct file *filp, return 0; } +static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p, + void *data) +{ + return -ENODEV; +} + +static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p, + void *data) +{ + return -ENODEV; +} + +static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p, + void *data) +{ + return -ENODEV; +} + +static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p, + void *data) +{ + return -ENODEV; +} + +static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, + void *data) +{ + return -ENODEV; +} + #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, .cmd_drv = 0, .name = #ioctl} @@ -539,6 +569,21 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE, kfd_ioctl_update_queue, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT, + kfd_ioctl_create_event, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT, + kfd_ioctl_destroy_event, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT, + kfd_ioctl_set_event, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT, + kfd_ioctl_reset_event, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS, + kfd_ioctl_wait_events, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index af94f31e33ac..4ca35a8f9891 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -27,7 +27,7 @@ #include #define KFD_IOCTL_MAJOR_VERSION 1 -#define KFD_IOCTL_MINOR_VERSION 0 +#define KFD_IOCTL_MINOR_VERSION 1 struct kfd_ioctl_get_version_args { uint32_t major_version; /* from KFD */ @@ -128,6 +128,83 @@ struct kfd_ioctl_get_process_apertures_args { uint32_t pad; }; +/* Matching HSA_EVENTTYPE */ +#define KFD_IOC_EVENT_SIGNAL 0 +#define KFD_IOC_EVENT_NODECHANGE 1 +#define KFD_IOC_EVENT_DEVICESTATECHANGE 2 +#define KFD_IOC_EVENT_HW_EXCEPTION 3 +#define KFD_IOC_EVENT_SYSTEM_EVENT 4 +#define KFD_IOC_EVENT_DEBUG_EVENT 5 +#define KFD_IOC_EVENT_PROFILE_EVENT 6 +#define KFD_IOC_EVENT_QUEUE_EVENT 7 +#define KFD_IOC_EVENT_MEMORY 8 + +#define KFD_IOC_WAIT_RESULT_COMPLETE 0 +#define KFD_IOC_WAIT_RESULT_TIMEOUT 1 +#define KFD_IOC_WAIT_RESULT_FAIL 2 + +#define KFD_SIGNAL_EVENT_LIMIT 256 + +struct kfd_ioctl_create_event_args { + uint64_t event_page_offset; /* from KFD */ + uint32_t event_trigger_data; /* from KFD - signal events only */ + uint32_t event_type; /* to KFD */ + uint32_t auto_reset; /* to KFD */ + uint32_t node_id; /* to KFD - only valid for certain + event types */ + uint32_t event_id; /* from KFD */ + uint32_t event_slot_index; /* from KFD */ +}; + +struct kfd_ioctl_destroy_event_args { + uint32_t event_id; /* to KFD */ + uint32_t pad; +}; + +struct kfd_ioctl_set_event_args { + uint32_t event_id; /* to KFD */ + uint32_t pad; +}; + +struct kfd_ioctl_reset_event_args { + uint32_t event_id; /* to KFD */ + uint32_t pad; +}; + +struct kfd_memory_exception_failure { + uint32_t NotPresent; /* Page not present or supervisor privilege */ + uint32_t ReadOnly; /* Write access to a read-only page */ + uint32_t NoExecute; /* Execute access to a page marked NX */ + uint32_t pad; +}; + +/* memory exception data*/ +struct kfd_hsa_memory_exception_data { + struct kfd_memory_exception_failure failure; + uint64_t va; + uint32_t gpu_id; + uint32_t pad; +}; + +/* Event data*/ +struct kfd_event_data { + union { + struct kfd_hsa_memory_exception_data memory_exception_data; + }; /* From KFD */ + uint64_t kfd_event_data_ext; /* pointer to an extension structure + for future exception types */ + uint32_t event_id; /* to KFD */ + uint32_t pad; +}; + +struct kfd_ioctl_wait_events_args { + uint64_t events_ptr; /* to KFD */ + uint32_t num_events; /* to KFD */ + uint32_t wait_for_all; /* to KFD */ + uint32_t timeout; /* to KFD */ + uint32_t wait_result; /* from KFD */ +}; + #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -155,7 +232,22 @@ struct kfd_ioctl_get_process_apertures_args { #define AMDKFD_IOC_UPDATE_QUEUE \ AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) +#define AMDKFD_IOC_CREATE_EVENT \ + AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) + +#define AMDKFD_IOC_DESTROY_EVENT \ + AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) + +#define AMDKFD_IOC_SET_EVENT \ + AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) + +#define AMDKFD_IOC_RESET_EVENT \ + AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) + +#define AMDKFD_IOC_WAIT_EVENTS \ + AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) + #define AMDKFD_COMMAND_START 0x01 -#define AMDKFD_COMMAND_END 0x08 +#define AMDKFD_COMMAND_END 0x0D #endif -- cgit v1.2.3 From f3a398183f7b9ef78f6b71ee9f7641e046403bcb Mon Sep 17 00:00:00 2001 From: Andrew Lewycky Date: Sun, 10 May 2015 12:15:46 +0300 Subject: drm/amdkfd: Add the events module This patch adds the events module (kfd_events.c) and the interrupt handle module for Kaveri (cik_event_interrupt.c). The patch updates the interrupt_is_wanted(), so that it now calls the interrupt isr function specific for the device that received the interrupt. That function(implemented in cik_event_interrupt.c) returns whether this interrupt is of interest to us or not. The patch also updates the interrupt_wq(), so that it now calls the device's specific wq function, which checks the interrupt source and tries to signal relevant events. v2: Increase limit of signal events to 4096 per process Remove bitfields from struct cik_ih_ring_entry Rename radeon_kfd_event_mmap to kfd_event_mmap Add debug prints to allocate_free_slot and allocate_signal_page Make allocate_event_notification_slot return a correct value Add warning prints to create_signal_event Remove error print from IOCTL path Reformatted debug prints in kfd_event_mmap Map correct size (as received from mmap) in kfd_event_mmap v3: Reduce limit of signal events back to 256 per process Fix allocation of kernel memory for signal events Signed-off-by: Andrew Lewycky Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/Makefile | 2 +- drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c | 63 ++ drivers/gpu/drm/amd/amdkfd/cik_int.h | 40 ++ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 16 +- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_events.c | 799 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_events.h | 76 +++ drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 11 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 47 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 24 + 10 files changed, 1074 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c create mode 100644 drivers/gpu/drm/amd/amdkfd/cik_int.h create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_events.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_events.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index cd09c05ee7e4..652d25478fd5 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -12,6 +12,6 @@ amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \ kfd_kernel_queue_vi.o kfd_packet_manager.o \ kfd_process_queue_manager.o kfd_device_queue_manager.o \ kfd_device_queue_manager_cik.o kfd_device_queue_manager_vi.o \ - kfd_interrupt.o + kfd_interrupt.o kfd_events.o cik_event_interrupt.o obj-$(CONFIG_HSA_AMD) += amdkfd.o diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c new file mode 100644 index 000000000000..629510ac16bc --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c @@ -0,0 +1,63 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "kfd_priv.h" +#include "kfd_events.h" +#include "cik_int.h" + +static bool cik_event_interrupt_isr(struct kfd_dev *dev, + const uint32_t *ih_ring_entry) +{ + unsigned int pasid; + const struct cik_ih_ring_entry *ihre = + (const struct cik_ih_ring_entry *)ih_ring_entry; + + pasid = (ihre->ring_id & 0xffff0000) >> 16; + + /* Do not process in ISR, just request it to be forwarded to WQ. */ + return (pasid != 0) && + (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE || + ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG); +} + +static void cik_event_interrupt_wq(struct kfd_dev *dev, + const uint32_t *ih_ring_entry) +{ + unsigned int pasid; + const struct cik_ih_ring_entry *ihre = + (const struct cik_ih_ring_entry *)ih_ring_entry; + + pasid = (ihre->ring_id & 0xffff0000) >> 16; + + if (pasid == 0) + return; + + if (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE) + kfd_signal_event_interrupt(pasid, 0, 0); + else if (ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG) + kfd_signal_event_interrupt(pasid, ihre->data & 0xFF, 8); +} + +const struct kfd_event_interrupt_class event_interrupt_class_cik = { + .interrupt_isr = cik_event_interrupt_isr, + .interrupt_wq = cik_event_interrupt_wq, +}; diff --git a/drivers/gpu/drm/amd/amdkfd/cik_int.h b/drivers/gpu/drm/amd/amdkfd/cik_int.h new file mode 100644 index 000000000000..bbef9e23ab19 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/cik_int.h @@ -0,0 +1,40 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef HSA_RADEON_CIK_INT_H_INCLUDED +#define HSA_RADEON_CIK_INT_H_INCLUDED + +#include + +struct cik_ih_ring_entry { + uint32_t source_id; + uint32_t data; + uint32_t ring_id; + uint32_t reserved; +}; + +#define CIK_INTSRC_DEQUEUE_COMPLETE 0xC6 +#define CIK_INTSRC_CP_END_OF_PIPE 0xB5 +#define CIK_INTSRC_SQ_INTERRUPT_MSG 0xEF + +#endif + diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 9933b2efe5dd..6dd89481b42d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -289,8 +289,10 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, args->queue_id = queue_id; + /* Return gpu_id as doorbell offset for mmap usage */ - args->doorbell_offset = args->gpu_id << PAGE_SHIFT; + args->doorbell_offset = (KFD_MMAP_DOORBELL_MASK | args->gpu_id); + args->doorbell_offset <<= PAGE_SHIFT; mutex_unlock(&p->mutex); @@ -684,5 +686,15 @@ static int kfd_mmap(struct file *filp, struct vm_area_struct *vma) if (IS_ERR(process)) return PTR_ERR(process); - return kfd_doorbell_mmap(process, vma); + if ((vma->vm_pgoff & KFD_MMAP_DOORBELL_MASK) == + KFD_MMAP_DOORBELL_MASK) { + vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_DOORBELL_MASK; + return kfd_doorbell_mmap(process, vma); + } else if ((vma->vm_pgoff & KFD_MMAP_EVENTS_MASK) == + KFD_MMAP_EVENTS_MASK) { + vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_EVENTS_MASK; + return kfd_event_mmap(process, vma); + } + + return -EFAULT; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 13c30a099684..4c0316957a57 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -34,6 +34,7 @@ static const struct kfd_device_info kaveri_device_info = { .asic_family = CHIP_KAVERI, .max_pasid_bits = 16, .ih_ring_entry_size = 4 * sizeof(uint32_t), + .event_interrupt_class = &event_interrupt_class_cik, .mqd_size_aligned = MQD_SIZE_ALIGNED }; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c new file mode 100644 index 000000000000..23ffa966f3c2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -0,0 +1,799 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "kfd_priv.h" +#include "kfd_events.h" + +/* + * A task can only be on a single wait_queue at a time, but we need to support + * waiting on multiple events (any/all). + * Instead of each event simply having a wait_queue with sleeping tasks, it + * has a singly-linked list of tasks. + * A thread that wants to sleep creates an array of these, one for each event + * and adds one to each event's waiter chain. + */ +struct kfd_event_waiter { + struct list_head waiters; + struct task_struct *sleeping_task; + + /* Transitions to true when the event this belongs to is signaled. */ + bool activated; +}; + +/* + * Over-complicated pooled allocator for event notification slots. + * + * Each signal event needs a 64-bit signal slot where the signaler will write + * a 1 before sending an interrupt.l (This is needed because some interrupts + * do not contain enough spare data bits to identify an event.) + * We get whole pages from vmalloc and map them to the process VA. + * Individual signal events are then allocated a slot in a page. + */ + +struct signal_page { + struct list_head event_pages; /* kfd_process.signal_event_pages */ + uint64_t *kernel_address; + uint64_t __user *user_address; + uint32_t page_index; /* Index into the mmap aperture. */ + unsigned int free_slots; + unsigned long used_slot_bitmap[0]; +}; + +#define SLOTS_PER_PAGE KFD_SIGNAL_EVENT_LIMIT +#define SLOT_BITMAP_SIZE BITS_TO_LONGS(SLOTS_PER_PAGE) +#define BITS_PER_PAGE (ilog2(SLOTS_PER_PAGE)+1) +#define SIGNAL_PAGE_SIZE (sizeof(struct signal_page) + \ + SLOT_BITMAP_SIZE * sizeof(long)) + +/* + * For signal events, the event ID is used as the interrupt user data. + * For SQ s_sendmsg interrupts, this is limited to 8 bits. + */ + +#define INTERRUPT_DATA_BITS 8 +#define SIGNAL_EVENT_ID_SLOT_SHIFT 0 + +static uint64_t *page_slots(struct signal_page *page) +{ + return page->kernel_address; +} + +static bool allocate_free_slot(struct kfd_process *process, + struct signal_page **out_page, + unsigned int *out_slot_index) +{ + struct signal_page *page; + + list_for_each_entry(page, &process->signal_event_pages, event_pages) { + if (page->free_slots > 0) { + unsigned int slot = + find_first_zero_bit(page->used_slot_bitmap, + SLOTS_PER_PAGE); + + __set_bit(slot, page->used_slot_bitmap); + page->free_slots--; + + page_slots(page)[slot] = UNSIGNALED_EVENT_SLOT; + + *out_page = page; + *out_slot_index = slot; + + pr_debug("allocated event signal slot in page %p, slot %d\n", + page, slot); + + return true; + } + } + + pr_debug("No free event signal slots were found for process %p\n", + process); + + return false; +} + +#define list_tail_entry(head, type, member) \ + list_entry((head)->prev, type, member) + +static bool allocate_signal_page(struct file *devkfd, struct kfd_process *p) +{ + void *backing_store; + struct signal_page *page; + + page = kzalloc(SIGNAL_PAGE_SIZE, GFP_KERNEL); + if (!page) + goto fail_alloc_signal_page; + + page->free_slots = SLOTS_PER_PAGE; + + backing_store = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO, + get_order(KFD_SIGNAL_EVENT_LIMIT * 8)); + if (!backing_store) + goto fail_alloc_signal_store; + + /* prevent user-mode info leaks */ + memset(backing_store, (uint8_t) UNSIGNALED_EVENT_SLOT, + KFD_SIGNAL_EVENT_LIMIT * 8); + + page->kernel_address = backing_store; + + if (list_empty(&p->signal_event_pages)) + page->page_index = 0; + else + page->page_index = list_tail_entry(&p->signal_event_pages, + struct signal_page, + event_pages)->page_index + 1; + + pr_debug("allocated new event signal page at %p, for process %p\n", + page, p); + pr_debug("page index is %d\n", page->page_index); + + list_add(&page->event_pages, &p->signal_event_pages); + + return true; + +fail_alloc_signal_store: + kfree(page); +fail_alloc_signal_page: + return false; +} + +static bool allocate_event_notification_slot(struct file *devkfd, + struct kfd_process *p, + struct signal_page **page, + unsigned int *signal_slot_index) +{ + bool ret; + + ret = allocate_free_slot(p, page, signal_slot_index); + if (ret == false) { + ret = allocate_signal_page(devkfd, p); + if (ret == true) + ret = allocate_free_slot(p, page, signal_slot_index); + } + + return ret; +} + +/* Assumes that the process's event_mutex is locked. */ +static void release_event_notification_slot(struct signal_page *page, + size_t slot_index) +{ + __clear_bit(slot_index, page->used_slot_bitmap); + page->free_slots++; + + /* We don't free signal pages, they are retained by the process + * and reused until it exits. */ +} + +static struct signal_page *lookup_signal_page_by_index(struct kfd_process *p, + unsigned int page_index) +{ + struct signal_page *page; + + /* + * This is safe because we don't delete signal pages until the + * process exits. + */ + list_for_each_entry(page, &p->signal_event_pages, event_pages) + if (page->page_index == page_index) + return page; + + return NULL; +} + +/* + * Assumes that p->event_mutex is held and of course that p is not going + * away (current or locked). + */ +static struct kfd_event *lookup_event_by_id(struct kfd_process *p, uint32_t id) +{ + struct kfd_event *ev; + + hash_for_each_possible(p->events, ev, events, id) + if (ev->event_id == id) + return ev; + + return NULL; +} + +static u32 make_signal_event_id(struct signal_page *page, + unsigned int signal_slot_index) +{ + return page->page_index | + (signal_slot_index << SIGNAL_EVENT_ID_SLOT_SHIFT); +} + +/* + * Produce a kfd event id for a nonsignal event. + * These are arbitrary numbers, so we do a sequential search through + * the hash table for an unused number. + */ +static u32 make_nonsignal_event_id(struct kfd_process *p) +{ + u32 id; + + for (id = p->next_nonsignal_event_id; + id < KFD_LAST_NONSIGNAL_EVENT_ID && + lookup_event_by_id(p, id) != NULL; + id++) + ; + + if (id < KFD_LAST_NONSIGNAL_EVENT_ID) { + + /* + * What if id == LAST_NONSIGNAL_EVENT_ID - 1? + * Then next_nonsignal_event_id = LAST_NONSIGNAL_EVENT_ID so + * the first loop fails immediately and we proceed with the + * wraparound loop below. + */ + p->next_nonsignal_event_id = id + 1; + + return id; + } + + for (id = KFD_FIRST_NONSIGNAL_EVENT_ID; + id < KFD_LAST_NONSIGNAL_EVENT_ID && + lookup_event_by_id(p, id) != NULL; + id++) + ; + + + if (id < KFD_LAST_NONSIGNAL_EVENT_ID) { + p->next_nonsignal_event_id = id + 1; + return id; + } + + p->next_nonsignal_event_id = KFD_FIRST_NONSIGNAL_EVENT_ID; + return 0; +} + +static struct kfd_event *lookup_event_by_page_slot(struct kfd_process *p, + struct signal_page *page, + unsigned int signal_slot) +{ + return lookup_event_by_id(p, make_signal_event_id(page, signal_slot)); +} + +static int create_signal_event(struct file *devkfd, + struct kfd_process *p, + struct kfd_event *ev) +{ + if (p->signal_event_count == KFD_SIGNAL_EVENT_LIMIT) { + pr_warn("amdkfd: Signal event wasn't created because limit was reached\n"); + return -ENOMEM; + } + + if (!allocate_event_notification_slot(devkfd, p, &ev->signal_page, + &ev->signal_slot_index)) { + pr_warn("amdkfd: Signal event wasn't created because out of kernel memory\n"); + return -ENOMEM; + } + + p->signal_event_count++; + + ev->user_signal_address = + &ev->signal_page->user_address[ev->signal_slot_index]; + + ev->event_id = make_signal_event_id(ev->signal_page, + ev->signal_slot_index); + + pr_debug("signal event number %zu created with id %d, address %p\n", + p->signal_event_count, ev->event_id, + ev->user_signal_address); + + return 0; +} + +/* + * No non-signal events are supported yet. + * We create them as events that never signal. + * Set event calls from user-mode are failed. + */ +static int create_other_event(struct kfd_process *p, struct kfd_event *ev) +{ + ev->event_id = make_nonsignal_event_id(p); + if (ev->event_id == 0) + return -ENOMEM; + + return 0; +} + +void kfd_event_init_process(struct kfd_process *p) +{ + mutex_init(&p->event_mutex); + hash_init(p->events); + INIT_LIST_HEAD(&p->signal_event_pages); + p->next_nonsignal_event_id = KFD_FIRST_NONSIGNAL_EVENT_ID; + p->signal_event_count = 0; +} + +static void destroy_event(struct kfd_process *p, struct kfd_event *ev) +{ + if (ev->signal_page != NULL) { + release_event_notification_slot(ev->signal_page, + ev->signal_slot_index); + p->signal_event_count--; + } + + /* + * Abandon the list of waiters. Individual waiting threads will + * clean up their own data. + */ + list_del(&ev->waiters); + + hash_del(&ev->events); + kfree(ev); +} + +static void destroy_events(struct kfd_process *p) +{ + struct kfd_event *ev; + struct hlist_node *tmp; + unsigned int hash_bkt; + + hash_for_each_safe(p->events, hash_bkt, tmp, ev, events) + destroy_event(p, ev); +} + +/* + * We assume that the process is being destroyed and there is no need to + * unmap the pages or keep bookkeeping data in order. + */ +static void shutdown_signal_pages(struct kfd_process *p) +{ + struct signal_page *page, *tmp; + + list_for_each_entry_safe(page, tmp, &p->signal_event_pages, + event_pages) { + free_pages((unsigned long)page->kernel_address, + get_order(KFD_SIGNAL_EVENT_LIMIT * 8)); + kfree(page); + } +} + +void kfd_event_free_process(struct kfd_process *p) +{ + destroy_events(p); + shutdown_signal_pages(p); +} + +static bool event_can_be_gpu_signaled(const struct kfd_event *ev) +{ + return ev->type == KFD_EVENT_TYPE_SIGNAL || + ev->type == KFD_EVENT_TYPE_DEBUG; +} + +static bool event_can_be_cpu_signaled(const struct kfd_event *ev) +{ + return ev->type == KFD_EVENT_TYPE_SIGNAL; +} + +int kfd_event_create(struct file *devkfd, struct kfd_process *p, + uint32_t event_type, bool auto_reset, uint32_t node_id, + uint32_t *event_id, uint32_t *event_trigger_data, + uint64_t *event_page_offset, uint32_t *event_slot_index) +{ + int ret = 0; + struct kfd_event *ev = kzalloc(sizeof(*ev), GFP_KERNEL); + + if (!ev) + return -ENOMEM; + + ev->type = event_type; + ev->auto_reset = auto_reset; + ev->signaled = false; + + INIT_LIST_HEAD(&ev->waiters); + + *event_page_offset = 0; + + mutex_lock(&p->event_mutex); + + switch (event_type) { + case KFD_EVENT_TYPE_SIGNAL: + case KFD_EVENT_TYPE_DEBUG: + ret = create_signal_event(devkfd, p, ev); + if (!ret) { + *event_page_offset = (ev->signal_page->page_index | + KFD_MMAP_EVENTS_MASK); + *event_page_offset <<= PAGE_SHIFT; + *event_slot_index = ev->signal_slot_index; + } + break; + default: + ret = create_other_event(p, ev); + break; + } + + if (!ret) { + hash_add(p->events, &ev->events, ev->event_id); + + *event_id = ev->event_id; + *event_trigger_data = ev->event_id; + } else { + kfree(ev); + } + + mutex_unlock(&p->event_mutex); + + return ret; +} + +/* Assumes that p is current. */ +int kfd_event_destroy(struct kfd_process *p, uint32_t event_id) +{ + struct kfd_event *ev; + int ret = 0; + + mutex_lock(&p->event_mutex); + + ev = lookup_event_by_id(p, event_id); + + if (ev) + destroy_event(p, ev); + else + ret = -EINVAL; + + mutex_unlock(&p->event_mutex); + return ret; +} + +static void set_event(struct kfd_event *ev) +{ + struct kfd_event_waiter *waiter; + struct kfd_event_waiter *next; + + /* Auto reset if the list is non-empty and we're waking someone. */ + ev->signaled = !ev->auto_reset || list_empty(&ev->waiters); + + list_for_each_entry_safe(waiter, next, &ev->waiters, waiters) { + waiter->activated = true; + + /* _init because free_waiters will call list_del */ + list_del_init(&waiter->waiters); + + wake_up_process(waiter->sleeping_task); + } +} + +/* Assumes that p is current. */ +int kfd_set_event(struct kfd_process *p, uint32_t event_id) +{ + int ret = 0; + struct kfd_event *ev; + + mutex_lock(&p->event_mutex); + + ev = lookup_event_by_id(p, event_id); + + if (ev && event_can_be_cpu_signaled(ev)) + set_event(ev); + else + ret = -EINVAL; + + mutex_unlock(&p->event_mutex); + return ret; +} + +static void reset_event(struct kfd_event *ev) +{ + ev->signaled = false; +} + +/* Assumes that p is current. */ +int kfd_reset_event(struct kfd_process *p, uint32_t event_id) +{ + int ret = 0; + struct kfd_event *ev; + + mutex_lock(&p->event_mutex); + + ev = lookup_event_by_id(p, event_id); + + if (ev && event_can_be_cpu_signaled(ev)) + reset_event(ev); + else + ret = -EINVAL; + + mutex_unlock(&p->event_mutex); + return ret; + +} + +static void acknowledge_signal(struct kfd_process *p, struct kfd_event *ev) +{ + page_slots(ev->signal_page)[ev->signal_slot_index] = + UNSIGNALED_EVENT_SLOT; +} + +static bool is_slot_signaled(struct signal_page *page, unsigned int index) +{ + return page_slots(page)[index] != UNSIGNALED_EVENT_SLOT; +} + +static void set_event_from_interrupt(struct kfd_process *p, + struct kfd_event *ev) +{ + if (ev && event_can_be_gpu_signaled(ev)) { + acknowledge_signal(p, ev); + set_event(ev); + } +} + +void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, + uint32_t valid_id_bits) +{ + struct kfd_event *ev; + + /* + * Because we are called from arbitrary context (workqueue) as opposed + * to process context, kfd_process could attempt to exit while we are + * running so the lookup function returns a locked process. + */ + struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); + + if (!p) + return; /* Presumably process exited. */ + + mutex_lock(&p->event_mutex); + + if (valid_id_bits >= INTERRUPT_DATA_BITS) { + /* Partial ID is a full ID. */ + ev = lookup_event_by_id(p, partial_id); + set_event_from_interrupt(p, ev); + } else { + /* + * Partial ID is in fact partial. For now we completely + * ignore it, but we could use any bits we did receive to + * search faster. + */ + struct signal_page *page; + unsigned i; + + list_for_each_entry(page, &p->signal_event_pages, event_pages) + for (i = 0; i < SLOTS_PER_PAGE; i++) + if (is_slot_signaled(page, i)) { + ev = lookup_event_by_page_slot(p, + page, i); + set_event_from_interrupt(p, ev); + } + } + + mutex_unlock(&p->event_mutex); + mutex_unlock(&p->mutex); +} + +static struct kfd_event_waiter *alloc_event_waiters(uint32_t num_events) +{ + struct kfd_event_waiter *event_waiters; + uint32_t i; + + event_waiters = kmalloc_array(num_events, + sizeof(struct kfd_event_waiter), + GFP_KERNEL); + + for (i = 0; (event_waiters) && (i < num_events) ; i++) { + INIT_LIST_HEAD(&event_waiters[i].waiters); + event_waiters[i].sleeping_task = current; + event_waiters[i].activated = false; + } + + return event_waiters; +} + +static int init_event_waiter(struct kfd_process *p, + struct kfd_event_waiter *waiter, + uint32_t event_id) +{ + struct kfd_event *ev = lookup_event_by_id(p, event_id); + + if (!ev) + return -EINVAL; + + waiter->activated = ev->signaled; + ev->signaled = ev->signaled && !ev->auto_reset; + + list_add(&waiter->waiters, &ev->waiters); + + return 0; +} + +static bool test_event_condition(bool all, uint32_t num_events, + struct kfd_event_waiter *event_waiters) +{ + uint32_t i; + uint32_t activated_count = 0; + + for (i = 0; i < num_events; i++) { + if (event_waiters[i].activated) { + if (!all) + return true; + + activated_count++; + } + } + + return activated_count == num_events; +} + +static long user_timeout_to_jiffies(uint32_t user_timeout_ms) +{ + if (user_timeout_ms == KFD_EVENT_TIMEOUT_IMMEDIATE) + return 0; + + if (user_timeout_ms == KFD_EVENT_TIMEOUT_INFINITE) + return MAX_SCHEDULE_TIMEOUT; + + /* + * msecs_to_jiffies interprets all values above 2^31-1 as infinite, + * but we consider them finite. + * This hack is wrong, but nobody is likely to notice. + */ + user_timeout_ms = min_t(uint32_t, user_timeout_ms, 0x7FFFFFFF); + + return msecs_to_jiffies(user_timeout_ms) + 1; +} + +static void free_waiters(uint32_t num_events, struct kfd_event_waiter *waiters) +{ + uint32_t i; + + for (i = 0; i < num_events; i++) + list_del(&waiters[i].waiters); + + kfree(waiters); +} + +int kfd_wait_on_events(struct kfd_process *p, + uint32_t num_events, const uint32_t __user *event_ids, + bool all, uint32_t user_timeout_ms, + enum kfd_event_wait_result *wait_result) +{ + uint32_t i; + int ret = 0; + struct kfd_event_waiter *event_waiters = NULL; + long timeout = user_timeout_to_jiffies(user_timeout_ms); + + mutex_lock(&p->event_mutex); + + event_waiters = alloc_event_waiters(num_events); + if (!event_waiters) { + ret = -ENOMEM; + goto fail; + } + + for (i = 0; i < num_events; i++) { + uint32_t event_id; + + ret = get_user(event_id, &event_ids[i]); + if (ret) + goto fail; + + ret = init_event_waiter(p, &event_waiters[i], event_id); + if (ret) + goto fail; + } + + mutex_unlock(&p->event_mutex); + + while (true) { + if (fatal_signal_pending(current)) { + ret = -EINTR; + break; + } + + if (signal_pending(current)) { + /* + * This is wrong when a nonzero, non-infinite timeout + * is specified. We need to use + * ERESTARTSYS_RESTARTBLOCK, but struct restart_block + * contains a union with data for each user and it's + * in generic kernel code that I don't want to + * touch yet. + */ + ret = -ERESTARTSYS; + break; + } + + if (test_event_condition(all, num_events, event_waiters)) { + *wait_result = KFD_WAIT_COMPLETE; + break; + } + + if (timeout <= 0) { + *wait_result = KFD_WAIT_TIMEOUT; + break; + } + + timeout = schedule_timeout_interruptible(timeout); + } + __set_current_state(TASK_RUNNING); + + mutex_lock(&p->event_mutex); + free_waiters(num_events, event_waiters); + mutex_unlock(&p->event_mutex); + + return ret; + +fail: + if (event_waiters) + free_waiters(num_events, event_waiters); + + mutex_unlock(&p->event_mutex); + + *wait_result = KFD_WAIT_ERROR; + + return ret; +} + +int kfd_event_mmap(struct kfd_process *p, struct vm_area_struct *vma) +{ + + unsigned int page_index; + unsigned long pfn; + struct signal_page *page; + + /* check required size is logical */ + if (get_order(KFD_SIGNAL_EVENT_LIMIT * 8) != + get_order(vma->vm_end - vma->vm_start)) { + pr_err("amdkfd: event page mmap requested illegal size\n"); + return -EINVAL; + } + + page_index = vma->vm_pgoff; + + page = lookup_signal_page_by_index(p, page_index); + if (!page) { + /* Probably KFD bug, but mmap is user-accessible. */ + pr_debug("signal page could not be found for page_index %u\n", + page_index); + return -EINVAL; + } + + pfn = __pa(page->kernel_address); + pfn >>= PAGE_SHIFT; + + vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE + | VM_DONTDUMP | VM_PFNMAP; + + pr_debug("mapping signal page\n"); + pr_debug(" start user address == 0x%08lx\n", vma->vm_start); + pr_debug(" end user address == 0x%08lx\n", vma->vm_end); + pr_debug(" pfn == 0x%016lX\n", pfn); + pr_debug(" vm_flags == 0x%08lX\n", vma->vm_flags); + pr_debug(" size == 0x%08lX\n", + vma->vm_end - vma->vm_start); + + page->user_address = (uint64_t __user *)vma->vm_start; + + /* mapping the page to user process */ + return remap_pfn_range(vma, vma->vm_start, pfn, + vma->vm_end - vma->vm_start, vma->vm_page_prot); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_events.h new file mode 100644 index 000000000000..d9b5b381af0b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.h @@ -0,0 +1,76 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef KFD_EVENTS_H_INCLUDED +#define KFD_EVENTS_H_INCLUDED + +#include +#include +#include +#include +#include "kfd_priv.h" + +#define KFD_EVENT_ID_NONSIGNAL_MASK 0x80000000U +#define KFD_FIRST_NONSIGNAL_EVENT_ID KFD_EVENT_ID_NONSIGNAL_MASK +#define KFD_LAST_NONSIGNAL_EVENT_ID UINT_MAX + +/* + * Written into kfd_signal_slot_t to indicate that the event is not signaled. + * Since the event protocol may need to write the event ID into memory, this + * must not be a valid event ID. + * For the sake of easy memset-ing, this must be a byte pattern. + */ +#define UNSIGNALED_EVENT_SLOT ((uint64_t)-1) + +struct kfd_event_waiter; +struct signal_page; + +struct kfd_event { + /* All events in process, rooted at kfd_process.events. */ + struct hlist_node events; + + u32 event_id; + + bool signaled; + bool auto_reset; + + int type; + + struct list_head waiters; /* List of kfd_event_waiter by waiters. */ + + /* Only for signal events. */ + struct signal_page *signal_page; + unsigned int signal_slot_index; + uint64_t __user *user_signal_address; +}; + +#define KFD_EVENT_TIMEOUT_IMMEDIATE 0 +#define KFD_EVENT_TIMEOUT_INFINITE 0xFFFFFFFFu + +/* Matching HSA_EVENTTYPE */ +#define KFD_EVENT_TYPE_SIGNAL 0 +#define KFD_EVENT_TYPE_DEBUG 5 + +extern void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, + uint32_t valid_id_bits); + +#endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c index 5383dd05710d..7f134aa9bfd3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c @@ -172,10 +172,17 @@ static void interrupt_wq(struct work_struct *work) sizeof(uint32_t))]; while (dequeue_ih_ring_entry(dev, ih_ring_entry)) - ; + dev->device_info->event_interrupt_class->interrupt_wq(dev, + ih_ring_entry); } bool interrupt_is_wanted(struct kfd_dev *dev, const uint32_t *ih_ring_entry) { - return false; + /* integer and bitwise OR so there is no boolean short-circuiting */ + unsigned wanted = 0; + + wanted |= dev->device_info->event_interrupt_class->interrupt_isr(dev, + ih_ring_entry); + + return wanted != 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 34c766208e8a..0ff9a3daf385 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -35,6 +35,9 @@ #define KFD_SYSFS_FILE_MODE 0444 +#define KFD_MMAP_DOORBELL_MASK 0x8000000000000 +#define KFD_MMAP_EVENTS_MASK 0x4000000000000 + /* * When working with cp scheduler we should assign the HIQ manually or via * the radeon driver to a fixed hqd slot, here are the fixed HIQ hqd slot @@ -108,8 +111,16 @@ enum asic_family_type { CHIP_CARRIZO }; +struct kfd_event_interrupt_class { + bool (*interrupt_isr)(struct kfd_dev *dev, + const uint32_t *ih_ring_entry); + void (*interrupt_wq)(struct kfd_dev *dev, + const uint32_t *ih_ring_entry); +}; + struct kfd_device_info { unsigned int asic_family; + const struct kfd_event_interrupt_class *event_interrupt_class; unsigned int max_pasid_bits; size_t ih_ring_entry_size; uint8_t num_of_watch_points; @@ -490,6 +501,15 @@ struct kfd_process { /*Is the user space process 32 bit?*/ bool is_32bit_user_mode; + + /* Event-related data */ + struct mutex event_mutex; + /* All events in process hashed by ID, linked on kfd_event.events. */ + DECLARE_HASHTABLE(events, 4); + struct list_head signal_event_pages; /* struct slot_page_header. + event_pages */ + u32 next_nonsignal_event_id; + size_t signal_event_count; }; /** @@ -514,6 +534,7 @@ void kfd_process_create_wq(void); void kfd_process_destroy_wq(void); struct kfd_process *kfd_create_process(const struct task_struct *); struct kfd_process *kfd_get_process(const struct task_struct *); +struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid); struct kfd_process_device *kfd_bind_process_to_device(struct kfd_dev *dev, struct kfd_process *p); @@ -659,4 +680,30 @@ uint64_t kfd_get_number_elems(struct kfd_dev *kfd); phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev, struct kfd_process *process); +/* Events */ +extern const struct kfd_event_interrupt_class event_interrupt_class_cik; + +enum kfd_event_wait_result { + KFD_WAIT_COMPLETE, + KFD_WAIT_TIMEOUT, + KFD_WAIT_ERROR +}; + +void kfd_event_init_process(struct kfd_process *p); +void kfd_event_free_process(struct kfd_process *p); +int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma); +int kfd_wait_on_events(struct kfd_process *p, + uint32_t num_events, const uint32_t __user *event_ids, + bool all, uint32_t user_timeout_ms, + enum kfd_event_wait_result *wait_result); +void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, + uint32_t valid_id_bits); +int kfd_set_event(struct kfd_process *p, uint32_t event_id); +int kfd_reset_event(struct kfd_process *p, uint32_t event_id); +int kfd_event_create(struct file *devkfd, struct kfd_process *p, + uint32_t event_type, bool auto_reset, uint32_t node_id, + uint32_t *event_id, uint32_t *event_trigger_data, + uint64_t *event_page_offset, uint32_t *event_slot_index); +int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); + #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 4d7bc95a95d9..dc910af2bb3c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -178,6 +178,8 @@ static void kfd_process_wq_release(struct work_struct *work) kfree(pdd); } + kfd_event_free_process(p); + kfd_pasid_free(p->pasid); mutex_unlock(&p->mutex); @@ -288,6 +290,8 @@ static struct kfd_process *create_process(const struct task_struct *thread) INIT_LIST_HEAD(&process->per_device_data); + kfd_event_init_process(process); + err = pqm_init(&process->pqm, process); if (err != 0) goto err_process_pqm_init; @@ -430,3 +434,23 @@ bool kfd_has_process_device_data(struct kfd_process *p) { return !(list_empty(&p->per_device_data)); } + +/* This returns with process->mutex locked. */ +struct kfd_process *kfd_lookup_process_by_pasid(unsigned int pasid) +{ + struct kfd_process *p; + unsigned int temp; + + int idx = srcu_read_lock(&kfd_processes_srcu); + + hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { + if (p->pasid == pasid) { + mutex_lock(&p->mutex); + break; + } + } + + srcu_read_unlock(&kfd_processes_srcu, idx); + + return p; +} -- cgit v1.2.3 From 59d3e8be87a14c6a0d91c683e63d9b31734525ae Mon Sep 17 00:00:00 2001 From: Alexey Skidanov Date: Tue, 14 Apr 2015 18:05:49 +0300 Subject: drm/amdkfd: Add memory exception handling This patch adds Peripheral Page Request (PPR) failure processing and reporting. Bad address or pointer to a system memory block with inappropriate read/write permission cause such PPR failure during a user queue processing. PPR request handling is done by IOMMU driver notifying AMDKFD module on PPR failure. The process triggering a PPR failure will be notified by appropriate event or SIGTERM signal will be sent to it. v3: - Change all bool fields in struct kfd_memory_exception_failure to uint32_t Signed-off-by: Alexey Skidanov Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 29 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_events.c | 155 ++++++++++++++++++++++++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_events.h | 7 ++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +- 4 files changed, 187 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 4c0316957a57..52cab0f53ebc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -182,6 +182,32 @@ static void iommu_pasid_shutdown_callback(struct pci_dev *pdev, int pasid) kfd_unbind_process_from_device(dev, pasid); } +/* + * This function called by IOMMU driver on PPR failure + */ +static int iommu_invalid_ppr_cb(struct pci_dev *pdev, int pasid, + unsigned long address, u16 flags) +{ + struct kfd_dev *dev; + + dev_warn(kfd_device, + "Invalid PPR device %x:%x.%x pasid %d address 0x%lX flags 0x%X", + PCI_BUS_NUM(pdev->devfn), + PCI_SLOT(pdev->devfn), + PCI_FUNC(pdev->devfn), + pasid, + address, + flags); + + dev = kfd_device_by_pci_dev(pdev); + BUG_ON(dev == NULL); + + kfd_signal_iommu_event(dev, pasid, address, + flags & PPR_FAULT_WRITE, flags & PPR_FAULT_EXEC); + + return AMD_IOMMU_INV_PRI_RSP_INVALID; +} + bool kgd2kfd_device_init(struct kfd_dev *kfd, const struct kgd2kfd_shared_resources *gpu_resources) { @@ -251,6 +277,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, } amd_iommu_set_invalidate_ctx_cb(kfd->pdev, iommu_pasid_shutdown_callback); + amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb); kfd->dqm = device_queue_manager_init(kfd); if (!kfd->dqm) { @@ -316,6 +343,7 @@ void kgd2kfd_suspend(struct kfd_dev *kfd) if (kfd->init_complete) { kfd->dqm->ops.stop(kfd->dqm); amd_iommu_set_invalidate_ctx_cb(kfd->pdev, NULL); + amd_iommu_set_invalid_ppr_cb(kfd->pdev, NULL); amd_iommu_free_device(kfd->pdev); } } @@ -335,6 +363,7 @@ int kgd2kfd_resume(struct kfd_dev *kfd) return -ENXIO; amd_iommu_set_invalidate_ctx_cb(kfd->pdev, iommu_pasid_shutdown_callback); + amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb); kfd->dqm->ops.start(kfd->dqm); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 23ffa966f3c2..fa13d3efc616 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -30,6 +30,7 @@ #include #include "kfd_priv.h" #include "kfd_events.h" +#include /* * A task can only be on a single wait_queue at a time, but we need to support @@ -45,6 +46,10 @@ struct kfd_event_waiter { /* Transitions to true when the event this belongs to is signaled. */ bool activated; + + /* Event */ + struct kfd_event *event; + uint32_t input_index; }; /* @@ -609,14 +614,17 @@ static struct kfd_event_waiter *alloc_event_waiters(uint32_t num_events) } static int init_event_waiter(struct kfd_process *p, - struct kfd_event_waiter *waiter, - uint32_t event_id) + struct kfd_event_waiter *waiter, + uint32_t event_id, + uint32_t input_index) { struct kfd_event *ev = lookup_event_by_id(p, event_id); if (!ev) return -EINVAL; + waiter->event = ev; + waiter->input_index = input_index; waiter->activated = ev->signaled; ev->signaled = ev->signaled && !ev->auto_reset; @@ -643,6 +651,38 @@ static bool test_event_condition(bool all, uint32_t num_events, return activated_count == num_events; } +/* + * Copy event specific data, if defined. + * Currently only memory exception events have additional data to copy to user + */ +static bool copy_signaled_event_data(uint32_t num_events, + struct kfd_event_waiter *event_waiters, + struct kfd_event_data __user *data) +{ + struct kfd_hsa_memory_exception_data *src; + struct kfd_hsa_memory_exception_data __user *dst; + struct kfd_event_waiter *waiter; + struct kfd_event *event; + uint32_t i; + + for (i = 0; i < num_events; i++) { + waiter = &event_waiters[i]; + event = waiter->event; + if (waiter->activated && event->type == KFD_EVENT_TYPE_MEMORY) { + dst = &data[waiter->input_index].memory_exception_data; + src = &event->memory_exception_data; + if (copy_to_user(dst, src, + sizeof(struct kfd_hsa_memory_exception_data))) + return false; + } + } + + return true; + +} + + + static long user_timeout_to_jiffies(uint32_t user_timeout_ms) { if (user_timeout_ms == KFD_EVENT_TIMEOUT_IMMEDIATE) @@ -672,10 +712,12 @@ static void free_waiters(uint32_t num_events, struct kfd_event_waiter *waiters) } int kfd_wait_on_events(struct kfd_process *p, - uint32_t num_events, const uint32_t __user *event_ids, + uint32_t num_events, void __user *data, bool all, uint32_t user_timeout_ms, enum kfd_event_wait_result *wait_result) { + struct kfd_event_data __user *events = + (struct kfd_event_data __user *) data; uint32_t i; int ret = 0; struct kfd_event_waiter *event_waiters = NULL; @@ -690,13 +732,14 @@ int kfd_wait_on_events(struct kfd_process *p, } for (i = 0; i < num_events; i++) { - uint32_t event_id; + struct kfd_event_data event_data; - ret = get_user(event_id, &event_ids[i]); - if (ret) + if (copy_from_user(&event_data, &events[i], + sizeof(struct kfd_event_data))) goto fail; - ret = init_event_waiter(p, &event_waiters[i], event_id); + ret = init_event_waiter(p, &event_waiters[i], + event_data.event_id, i); if (ret) goto fail; } @@ -723,7 +766,11 @@ int kfd_wait_on_events(struct kfd_process *p, } if (test_event_condition(all, num_events, event_waiters)) { - *wait_result = KFD_WAIT_COMPLETE; + if (copy_signaled_event_data(num_events, + event_waiters, events)) + *wait_result = KFD_WAIT_COMPLETE; + else + *wait_result = KFD_WAIT_ERROR; break; } @@ -797,3 +844,95 @@ int kfd_event_mmap(struct kfd_process *p, struct vm_area_struct *vma) return remap_pfn_range(vma, vma->vm_start, pfn, vma->vm_end - vma->vm_start, vma->vm_page_prot); } + +/* + * Assumes that p->event_mutex is held and of course + * that p is not going away (current or locked). + */ +static void lookup_events_by_type_and_signal(struct kfd_process *p, + int type, void *event_data) +{ + struct kfd_hsa_memory_exception_data *ev_data; + struct kfd_event *ev; + int bkt; + bool send_signal = true; + + ev_data = (struct kfd_hsa_memory_exception_data *) event_data; + + hash_for_each(p->events, bkt, ev, events) + if (ev->type == type) { + send_signal = false; + dev_dbg(kfd_device, + "Event found: id %X type %d", + ev->event_id, ev->type); + set_event(ev); + if (ev->type == KFD_EVENT_TYPE_MEMORY && ev_data) + ev->memory_exception_data = *ev_data; + } + + /* Send SIGTERM no event of type "type" has been found*/ + if (send_signal) { + dev_warn(kfd_device, + "Sending SIGTERM to HSA Process with PID %d ", + p->lead_thread->pid); + send_sig(SIGTERM, p->lead_thread, 0); + } +} + +void kfd_signal_iommu_event(struct kfd_dev *dev, unsigned int pasid, + unsigned long address, bool is_write_requested, + bool is_execute_requested) +{ + struct kfd_hsa_memory_exception_data memory_exception_data; + struct vm_area_struct *vma; + + /* + * Because we are called from arbitrary context (workqueue) as opposed + * to process context, kfd_process could attempt to exit while we are + * running so the lookup function returns a locked process. + */ + struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); + + if (!p) + return; /* Presumably process exited. */ + + memset(&memory_exception_data, 0, sizeof(memory_exception_data)); + + down_read(&p->mm->mmap_sem); + vma = find_vma(p->mm, address); + + memory_exception_data.gpu_id = dev->id; + memory_exception_data.va = address; + /* Set failure reason */ + memory_exception_data.failure.NotPresent = 1; + memory_exception_data.failure.NoExecute = 0; + memory_exception_data.failure.ReadOnly = 0; + if (vma) { + if (vma->vm_start > address) { + memory_exception_data.failure.NotPresent = 1; + memory_exception_data.failure.NoExecute = 0; + memory_exception_data.failure.ReadOnly = 0; + } else { + memory_exception_data.failure.NotPresent = 0; + if (is_write_requested && !(vma->vm_flags & VM_WRITE)) + memory_exception_data.failure.ReadOnly = 1; + else + memory_exception_data.failure.ReadOnly = 0; + if (is_execute_requested && !(vma->vm_flags & VM_EXEC)) + memory_exception_data.failure.NoExecute = 1; + else + memory_exception_data.failure.NoExecute = 0; + } + } + + up_read(&p->mm->mmap_sem); + + mutex_lock(&p->event_mutex); + + /* Lookup events by type and signal them */ + lookup_events_by_type_and_signal(p, KFD_EVENT_TYPE_MEMORY, + &memory_exception_data); + + mutex_unlock(&p->event_mutex); + mutex_unlock(&p->mutex); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_events.h index d9b5b381af0b..691cf8573dc1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.h @@ -28,6 +28,7 @@ #include #include #include "kfd_priv.h" +#include #define KFD_EVENT_ID_NONSIGNAL_MASK 0x80000000U #define KFD_FIRST_NONSIGNAL_EVENT_ID KFD_EVENT_ID_NONSIGNAL_MASK @@ -61,6 +62,11 @@ struct kfd_event { struct signal_page *signal_page; unsigned int signal_slot_index; uint64_t __user *user_signal_address; + + /* type specific data */ + union { + struct kfd_hsa_memory_exception_data memory_exception_data; + }; }; #define KFD_EVENT_TIMEOUT_IMMEDIATE 0 @@ -69,6 +75,7 @@ struct kfd_event { /* Matching HSA_EVENTTYPE */ #define KFD_EVENT_TYPE_SIGNAL 0 #define KFD_EVENT_TYPE_DEBUG 5 +#define KFD_EVENT_TYPE_MEMORY 8 extern void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, uint32_t valid_id_bits); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 0ff9a3daf385..35945032fff9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -693,11 +693,14 @@ void kfd_event_init_process(struct kfd_process *p); void kfd_event_free_process(struct kfd_process *p); int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma); int kfd_wait_on_events(struct kfd_process *p, - uint32_t num_events, const uint32_t __user *event_ids, + uint32_t num_events, void __user *data, bool all, uint32_t user_timeout_ms, enum kfd_event_wait_result *wait_result); void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, uint32_t valid_id_bits); +void kfd_signal_iommu_event(struct kfd_dev *dev, + unsigned int pasid, unsigned long address, + bool is_write_requested, bool is_execute_requested); int kfd_set_event(struct kfd_process *p, uint32_t event_id); int kfd_reset_event(struct kfd_process *p, uint32_t event_id); int kfd_event_create(struct file *devkfd, struct kfd_process *p, -- cgit v1.2.3 From 930c5ff4390221cccf368b305c04351fbcf0dfcf Mon Sep 17 00:00:00 2001 From: Alexey Skidanov Date: Tue, 25 Nov 2014 10:34:31 +0200 Subject: drm/amdkfd: Add bad opcode exception handling Signed-off-by: Alexey Skidanov Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c | 5 ++++- drivers/gpu/drm/amd/amdkfd/cik_int.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_events.c | 21 +++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_events.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ 5 files changed, 29 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c index 629510ac16bc..211fc48697fa 100644 --- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c +++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c @@ -36,7 +36,8 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev, /* Do not process in ISR, just request it to be forwarded to WQ. */ return (pasid != 0) && (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE || - ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG); + ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG || + ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE); } static void cik_event_interrupt_wq(struct kfd_dev *dev, @@ -55,6 +56,8 @@ static void cik_event_interrupt_wq(struct kfd_dev *dev, kfd_signal_event_interrupt(pasid, 0, 0); else if (ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG) kfd_signal_event_interrupt(pasid, ihre->data & 0xFF, 8); + else if (ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE) + kfd_signal_hw_exception_event(pasid); } const struct kfd_event_interrupt_class event_interrupt_class_cik = { diff --git a/drivers/gpu/drm/amd/amdkfd/cik_int.h b/drivers/gpu/drm/amd/amdkfd/cik_int.h index bbef9e23ab19..79a16d24c1b8 100644 --- a/drivers/gpu/drm/amd/amdkfd/cik_int.h +++ b/drivers/gpu/drm/amd/amdkfd/cik_int.h @@ -34,6 +34,7 @@ struct cik_ih_ring_entry { #define CIK_INTSRC_DEQUEUE_COMPLETE 0xC6 #define CIK_INTSRC_CP_END_OF_PIPE 0xB5 +#define CIK_INTSRC_CP_BAD_OPCODE 0xB7 #define CIK_INTSRC_SQ_INTERRUPT_MSG 0xEF #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index fa13d3efc616..5c3a81e667a8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -936,3 +936,24 @@ void kfd_signal_iommu_event(struct kfd_dev *dev, unsigned int pasid, mutex_unlock(&p->event_mutex); mutex_unlock(&p->mutex); } + +void kfd_signal_hw_exception_event(unsigned int pasid) +{ + /* + * Because we are called from arbitrary context (workqueue) as opposed + * to process context, kfd_process could attempt to exit while we are + * running so the lookup function returns a locked process. + */ + struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); + + if (!p) + return; /* Presumably process exited. */ + + mutex_lock(&p->event_mutex); + + /* Lookup events by type and signal them */ + lookup_events_by_type_and_signal(p, KFD_EVENT_TYPE_HW_EXCEPTION, NULL); + + mutex_unlock(&p->event_mutex); + mutex_unlock(&p->mutex); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_events.h index 691cf8573dc1..28f6838b1f4c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.h @@ -74,6 +74,7 @@ struct kfd_event { /* Matching HSA_EVENTTYPE */ #define KFD_EVENT_TYPE_SIGNAL 0 +#define KFD_EVENT_TYPE_HW_EXCEPTION 3 #define KFD_EVENT_TYPE_DEBUG 5 #define KFD_EVENT_TYPE_MEMORY 8 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 35945032fff9..9383494b429e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -682,6 +682,7 @@ phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev, /* Events */ extern const struct kfd_event_interrupt_class event_interrupt_class_cik; +extern const struct kfd_device_global_init_class device_global_init_class_cik; enum kfd_event_wait_result { KFD_WAIT_COMPLETE, @@ -701,6 +702,7 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, void kfd_signal_iommu_event(struct kfd_dev *dev, unsigned int pasid, unsigned long address, bool is_write_requested, bool is_execute_requested); +void kfd_signal_hw_exception_event(unsigned int pasid); int kfd_set_event(struct kfd_process *p, uint32_t event_id); int kfd_reset_event(struct kfd_process *p, uint32_t event_id); int kfd_event_create(struct file *devkfd, struct kfd_process *p, -- cgit v1.2.3 From 81663016dbfd53e29d1b5c5ddbc9b12ae1d66474 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Wed, 24 Dec 2014 13:30:52 +0200 Subject: drm/amdkfd: Add module parameter of send_sigterm This patch adds a new kernel module parameter to amdkfd, called send_sigterm. This parameter specifies whether amdkfd should send the SIGTERM signal to an HSA process, when the following conditions occur: 1. The GPU triggers an exception regarding a kernel that was issued by this process. 2. The HSA process isn't waiting on an event that handles this exception. The default behavior is not to send a SIGTERM and suffice with a dmesg error print. Reviewed-by: Ben Goz Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 12 +++++++++--- drivers/gpu/drm/amd/amdkfd/kfd_module.c | 5 +++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 ++++++ 3 files changed, 20 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 5c3a81e667a8..3cb37d220f60 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -872,10 +872,16 @@ static void lookup_events_by_type_and_signal(struct kfd_process *p, /* Send SIGTERM no event of type "type" has been found*/ if (send_signal) { - dev_warn(kfd_device, - "Sending SIGTERM to HSA Process with PID %d ", + if (send_sigterm) { + dev_warn(kfd_device, + "Sending SIGTERM to HSA Process with PID %d ", + p->lead_thread->pid); + send_sig(SIGTERM, p->lead_thread, 0); + } else { + dev_err(kfd_device, + "HSA Process (PID %d) got unhandled exception", p->lead_thread->pid); - send_sig(SIGTERM, p->lead_thread, 0); + } } } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 4e0a68f13a77..e4fc96ec4073 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -54,6 +54,11 @@ module_param(max_num_of_queues_per_device, int, 0444); MODULE_PARM_DESC(max_num_of_queues_per_device, "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); +int send_sigterm; +module_param(send_sigterm, int, 0444); +MODULE_PARM_DESC(send_sigterm, + "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); + bool kgd2kfd_init(unsigned interface_version, const struct kgd2kfd_calls **g2f) { /* diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 9383494b429e..b6f838f56589 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -74,6 +74,12 @@ extern int max_num_of_queues_per_device; /* Kernel module parameter to specify the scheduling policy */ extern int sched_policy; +/* + * Kernel module parameter to specify whether to send sigterm to HSA process on + * unhandled exception + */ +extern int send_sigterm; + /** * enum kfd_sched_policy * -- cgit v1.2.3 From 8377396b5db166c56a90b400317f26954901c994 Mon Sep 17 00:00:00 2001 From: Andrew Lewycky Date: Tue, 9 Sep 2014 15:22:05 +0300 Subject: drm/amdkfd: Implement events IOCTLs Signed-off-by: Andrew Lewycky Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 36 +++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 6dd89481b42d..b2c6109bd7af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -519,31 +519,57 @@ static int kfd_ioctl_get_process_apertures(struct file *filp, static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p, void *data) { - return -ENODEV; + struct kfd_ioctl_create_event_args *args = data; + int err; + + err = kfd_event_create(filp, p, args->event_type, + args->auto_reset != 0, args->node_id, + &args->event_id, &args->event_trigger_data, + &args->event_page_offset, + &args->event_slot_index); + + return err; } static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p, void *data) { - return -ENODEV; + struct kfd_ioctl_destroy_event_args *args = data; + + return kfd_event_destroy(p, args->event_id); } static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p, void *data) { - return -ENODEV; + struct kfd_ioctl_set_event_args *args = data; + + return kfd_set_event(p, args->event_id); } static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p, void *data) { - return -ENODEV; + struct kfd_ioctl_reset_event_args *args = data; + + return kfd_reset_event(p, args->event_id); } static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, void *data) { - return -ENODEV; + struct kfd_ioctl_wait_events_args *args = data; + enum kfd_event_wait_result wait_result; + int err; + + err = kfd_wait_on_events(p, args->num_events, + (void __user *)args->events_ptr, + (args->wait_for_all != 0), + args->timeout, &wait_result); + + args->wait_result = wait_result; + + return err; } #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ -- cgit v1.2.3 From 7591cd2cd59d77c52141d9c2c759c14f981c1a13 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Tue, 21 Apr 2015 15:09:48 +0300 Subject: drm/amdkfd: change driver version to 0.7.2 Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_module.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index e4fc96ec4073..ca8410e8683d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -29,10 +29,10 @@ #define KFD_DRIVER_AUTHOR "AMD Inc. and others" #define KFD_DRIVER_DESC "Standalone HSA driver for AMD's GPUs" -#define KFD_DRIVER_DATE "20150122" +#define KFD_DRIVER_DATE "20150421" #define KFD_DRIVER_MAJOR 0 #define KFD_DRIVER_MINOR 7 -#define KFD_DRIVER_PATCHLEVEL 1 +#define KFD_DRIVER_PATCHLEVEL 2 static const struct kgd2kfd_calls kgd2kfd = { .exit = kgd2kfd_exit, -- cgit v1.2.3 From 5e024f31be3734aed0a5ead7002de16029ec3bc1 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 8 May 2015 17:46:40 +0200 Subject: drm/i915: Remove unused variable from i915_gem_mmap_gtt Lost in commit c5ad54cf7dd8922bd1cee2d5871aebf73dc9638e Author: Joonas Lahtinen Date: Wed May 6 14:36:09 2015 +0300 drm/i915: Use partial view in mmap fault handler Cc: Joonas Lahtinen Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f128ed8d6f65..fb48e7277252 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1919,7 +1919,6 @@ i915_gem_mmap_gtt(struct drm_file *file, uint32_t handle, uint64_t *offset) { - struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj; int ret; -- cgit v1.2.3 From 7e35ab88d8ec652803eb2965c00e3ed9967c4f9d Mon Sep 17 00:00:00 2001 From: Masanari Iida Date: Sun, 10 May 2015 01:00:23 +0900 Subject: drm/i915: Fix typo in intel_runtime_pm.c This patch fix spelling typo in intel_runtime_pm.c Signed-off-by: Masanari Iida Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 317b9b43d1c1..3800be4ad76b 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -771,7 +771,7 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv, vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); if (wait_for(COND, 100)) - DRM_ERROR("timout setting power well state %08x (%08x)\n", + DRM_ERROR("timeout setting power well state %08x (%08x)\n", state, vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); @@ -1029,7 +1029,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); if (wait_for(COND, 100)) - DRM_ERROR("timout setting power well state %08x (%08x)\n", + DRM_ERROR("timeout setting power well state %08x (%08x)\n", state, vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); -- cgit v1.2.3 From 2cd601c620ccf7be1e8e317e2e208d395d309237 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Mon, 27 Apr 2015 15:47:37 -0700 Subject: drm/i915: Adding dbuf support for skl nv12 format. Skylake nv12 format requires dbuf (aka. ddb) calculations and programming for each of y and uv sub-planes. Made minor changes to reuse current dbuf calculations and programming for uv plane. i.e., with this change, existing computation is used for either packed format or uv portion of nv12 depending on incoming format. Added new code for dbuf computation and programming for y plane. This patch is a pre-requisite for adding NV12 format support. Actual nv12 support is coming in later patches. Signed-off-by: Chandra Konduru Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/i915_reg.h | 11 ++++++ drivers/gpu/drm/i915/intel_drv.h | 8 ++++ drivers/gpu/drm/i915/intel_pm.c | 79 ++++++++++++++++++++++++++++++++++------ 4 files changed, 88 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index acfa4fc93803..6b3142a99171 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1468,7 +1468,8 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, struct skl_ddb_allocation { struct skl_ddb_entry pipe[I915_MAX_PIPES]; - struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; + struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ + struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */ struct skl_ddb_entry cursor[I915_MAX_PIPES]; }; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 58627a319416..344d132c51ae 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5167,6 +5167,8 @@ enum skl_disp_power_wells { #define _PLANE_KEYMAX_2_A 0x702a0 #define _PLANE_BUF_CFG_1_A 0x7027c #define _PLANE_BUF_CFG_2_A 0x7037c +#define _PLANE_NV12_BUF_CFG_1_A 0x70278 +#define _PLANE_NV12_BUF_CFG_2_A 0x70378 #define _PLANE_CTL_1_B 0x71180 #define _PLANE_CTL_2_B 0x71280 @@ -5253,6 +5255,15 @@ enum skl_disp_power_wells { #define PLANE_BUF_CFG(pipe, plane) \ _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) +#define _PLANE_NV12_BUF_CFG_1_B 0x71278 +#define _PLANE_NV12_BUF_CFG_2_B 0x71378 +#define _PLANE_NV12_BUF_CFG_1(pipe) \ + _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) +#define _PLANE_NV12_BUF_CFG_2(pipe) \ + _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) +#define PLANE_NV12_BUF_CFG(pipe, plane) \ + _PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) + /* SKL new cursor registers */ #define _CUR_BUF_CFG_A 0x7017c #define _CUR_BUF_CFG_B 0x7117c diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ea3368e83626..638fc45edbb3 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -555,7 +555,15 @@ struct intel_crtc { struct intel_plane_wm_parameters { uint32_t horiz_pixels; uint32_t vert_pixels; + /* + * For packed pixel formats: + * bytes_per_pixel - holds bytes per pixel + * For planar pixel formats: + * bytes_per_pixel - holds bytes per pixel for uv-plane + * y_bytes_per_pixel - holds bytes per pixel for y-plane + */ uint8_t bytes_per_pixel; + uint8_t y_bytes_per_pixel; bool enabled; bool scaled; u64 tiling; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7006f94b94c1..af2606098cf9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2639,8 +2639,18 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, } static unsigned int -skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p) +skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y) { + + /* for planar format */ + if (p->y_bytes_per_pixel) { + if (y) /* y-plane data rate */ + return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel; + else /* uv-plane data rate */ + return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel; + } + + /* for packed formats */ return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; } @@ -2663,7 +2673,10 @@ skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, if (!p->enabled) continue; - total_data_rate += skl_plane_relative_data_rate(p); + total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */ + if (p->y_bytes_per_pixel) { + total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */ + } } return total_data_rate; @@ -2682,6 +2695,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; uint16_t alloc_size, start, cursor_blocks; uint16_t minimum[I915_MAX_PLANES]; + uint16_t y_minimum[I915_MAX_PLANES]; unsigned int total_data_rate; int plane; @@ -2710,6 +2724,8 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, minimum[plane] = 8; alloc_size -= minimum[plane]; + y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0; + alloc_size -= y_minimum[plane]; } /* @@ -2723,16 +2739,17 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, start = alloc->start; for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { const struct intel_plane_wm_parameters *p; - unsigned int data_rate; - uint16_t plane_blocks; + unsigned int data_rate, y_data_rate; + uint16_t plane_blocks, y_plane_blocks = 0; p = ¶ms->plane[plane]; if (!p->enabled) continue; - data_rate = skl_plane_relative_data_rate(p); + data_rate = skl_plane_relative_data_rate(p, 0); /* + * allocation for (packed formats) or (uv-plane part of planar format): * promote the expression to 64 bits to avoid overflowing, the * result is < available as data_rate / total_data_rate < 1 */ @@ -2744,6 +2761,22 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, ddb->plane[pipe][plane].end = start + plane_blocks; start += plane_blocks; + + /* + * allocation for y_plane part of planar format: + */ + if (p->y_bytes_per_pixel) { + y_data_rate = skl_plane_relative_data_rate(p, 1); + y_plane_blocks = y_minimum[plane]; + y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, + total_data_rate); + + ddb->y_plane[pipe][plane].start = start; + ddb->y_plane[pipe][plane].end = start + y_plane_blocks; + + start += y_plane_blocks; + } + } } @@ -2856,13 +2889,18 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); fb = crtc->primary->state->fb; + /* For planar: Bpp is for uv plane, y_Bpp is for y plane */ if (fb) { p->plane[0].enabled = true; - p->plane[0].bytes_per_pixel = fb->bits_per_pixel / 8; + p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? + drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8; + p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? + drm_format_plane_cpp(fb->pixel_format, 0) : 0; p->plane[0].tiling = fb->modifier[0]; } else { p->plane[0].enabled = false; p->plane[0].bytes_per_pixel = 0; + p->plane[0].y_bytes_per_pixel = 0; p->plane[0].tiling = DRM_FORMAT_MOD_NONE; } p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; @@ -2870,6 +2908,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, p->plane[0].rotation = crtc->primary->state->rotation; fb = crtc->cursor->state->fb; + p->cursor.y_bytes_per_pixel = 0; if (fb) { p->cursor.enabled = true; p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8; @@ -2905,22 +2944,25 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, uint32_t plane_bytes_per_line, plane_blocks_per_line; uint32_t res_blocks, res_lines; uint32_t selected_result; + uint8_t bytes_per_pixel; if (latency == 0 || !p->active || !p_params->enabled) return false; + bytes_per_pixel = p_params->y_bytes_per_pixel ? + p_params->y_bytes_per_pixel : + p_params->bytes_per_pixel; method1 = skl_wm_method1(p->pixel_rate, - p_params->bytes_per_pixel, + bytes_per_pixel, latency); method2 = skl_wm_method2(p->pixel_rate, p->pipe_htotal, p_params->horiz_pixels, - p_params->bytes_per_pixel, + bytes_per_pixel, p_params->tiling, latency); - plane_bytes_per_line = p_params->horiz_pixels * - p_params->bytes_per_pixel; + plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel; plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || @@ -3137,10 +3179,14 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv, new->plane_trans[pipe][i]); I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]); - for (i = 0; i < intel_num_planes(crtc); i++) + for (i = 0; i < intel_num_planes(crtc); i++) { skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, i), &new->ddb.plane[pipe][i]); + skl_ddb_entry_write(dev_priv, + PLANE_NV12_BUF_CFG(pipe, i), + &new->ddb.y_plane[pipe][i]); + } skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), &new->ddb.cursor[pipe]); @@ -3298,6 +3344,7 @@ static bool skl_update_pipe_wm(struct drm_crtc *crtc, return false; intel_crtc->wm.skl_active = *pipe_wm; + return true; } @@ -3391,8 +3438,16 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, intel_plane->wm.scaled = scaled; intel_plane->wm.horiz_pixels = sprite_width; intel_plane->wm.vert_pixels = sprite_height; - intel_plane->wm.bytes_per_pixel = pixel_size; intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; + + /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */ + intel_plane->wm.bytes_per_pixel = + (fb && fb->pixel_format == DRM_FORMAT_NV12) ? + drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size; + intel_plane->wm.y_bytes_per_pixel = + (fb && fb->pixel_format == DRM_FORMAT_NV12) ? + drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0; + /* * Framebuffer can be NULL on plane disable, but it does not * matter for watermarks if we assume no tiling in that case. -- cgit v1.2.3 From 49d6fa210e9a87bd83697692753604cbcaf103ae Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Mon, 11 May 2015 10:45:15 +0200 Subject: drm/i915: Always keep crtc_state->active in sync with enable With the recent modeset internal rework, we wind up setting crtc_state->enable to false, but leave crtc_state->active as true following a drmModeSetCrtc(fb=0), which is incorrect. This mismatch gets caught by drm_atomic_crtc_check() and causes subsequent atomic operations (such as plane updates while the CRTC is disabled) to fail. Bisect points to commit dad9a7d6d96630182fb52aae7c3856e9e7285e13 Author: Ander Conselvan de Oliveira Date: Tue Apr 21 17:13:19 2015 +0300 drm/i915: Use atomic helpers for computing changed flags as the commit that actually triggers the regression. The difference compared to (which this patch reverts) commit 90d469067d0808ddbd9be2c97a4a8e14037b5e46 Author: Matt Roper Date: Thu May 7 14:31:28 2015 -0700 drm/i915: Set crtc_state->active to false when CRTC is disabled (v2) is that we know keep state->active/enable in sync for all legacy modeset paths, as it should be. Cc: Matt Roper Cc: Ander Conselvan de Oliveira Reported-and-Tested-by: Kenneth Graunke Signed-off-by: Maarten Lankhorst [danvet: Directly squash in the revert and augment the commit message.] Signed-off-by: Daniel Vetter Revert "drm/i915: Set crtc_state->active to false when CRTC is disabled (v2)" This reverts commit 90d469067d0808ddbd9be2c97a4a8e14037b5e46. --- drivers/gpu/drm/i915/intel_display.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 240092afc392..4a043a558871 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9868,7 +9868,7 @@ retry: goto fail; } - crtc_state->base.enable = true; + crtc_state->base.active = crtc_state->base.enable = true; if (!mode) mode = &load_detect_mode; @@ -9965,7 +9965,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, connector_state->best_encoder = NULL; connector_state->crtc = NULL; - crtc_state->base.enable = false; + crtc_state->base.enable = crtc_state->base.active = false; ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, 0, 0); @@ -12342,7 +12342,6 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc, continue; if (!crtc_state->enable) { - crtc_state->active = false; intel_crtc_disable(crtc); } else if (crtc->state->enable) { intel_crtc_disable_planes(crtc); @@ -12492,7 +12491,8 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc) continue; } - crtc_state->base.enable = intel_crtc->new_enabled; + crtc_state->base.active = crtc_state->base.enable = + intel_crtc->new_enabled; if (&intel_crtc->base == crtc) drm_mode_copy(&crtc_state->base.mode, &crtc->mode); @@ -12617,11 +12617,16 @@ intel_modeset_stage_output_state(struct drm_device *dev, } for_each_crtc_in_state(state, crtc, crtc_state, i) { + bool has_connectors; + ret = drm_atomic_add_affected_connectors(state, crtc); if (ret) return ret; - crtc_state->enable = drm_atomic_connectors_for_crtc(state, crtc); + has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc); + if (has_connectors != crtc_state->enable) + crtc_state->enable = + crtc_state->active = has_connectors; } ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode, @@ -14595,6 +14600,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) WARN_ON(crtc->active); crtc->base.state->enable = false; + crtc->base.state->active = false; crtc->base.enabled = false; } @@ -14623,6 +14629,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) crtc->active ? "enabled" : "disabled"); crtc->base.state->enable = crtc->active; + crtc->base.state->active = crtc->active; crtc->base.enabled = crtc->active; /* Because we only establish the connector -> encoder -> @@ -14761,6 +14768,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) crtc->config); crtc->base.state->enable = crtc->active; + crtc->base.state->active = crtc->active; crtc->base.enabled = crtc->active; plane_state = to_intel_plane_state(primary->state); -- cgit v1.2.3 From b6e742f652791919ce5c8e05a1d664bcbc5111a6 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Sat, 9 May 2015 02:05:55 +0100 Subject: drm/i915: Be optimistic about future display engines having 7 WM levels As we're doing throughout the code, being optimistic that platform n + 1 will mostly reuse the same things as platform n allows us to minimize the enabling work needed. This time, it's about the number of WM levels. Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index af2606098cf9..f08264ca1d30 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1946,7 +1946,7 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) int ilk_wm_max_level(const struct drm_device *dev) { /* how many WM levels are we expecting */ - if (IS_GEN9(dev)) + if (INTEL_INFO(dev)->gen >= 9) return 7; else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) return 4; -- cgit v1.2.3 From a7f6e231150c93c4e15f258f0d4b1ffe97da3971 Mon Sep 17 00:00:00 2001 From: Deepak S Date: Sat, 9 May 2015 18:04:44 +0530 Subject: drm/i915/vlv: Remove wait for for punit to updates freq. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When GPU is idle on VLV, Request freq to punit should be good enough to get the voltage back to VNN. Also, make sure gfx clock force applies before requesting the freq fot vlv. v2: Do forcewake before setting idle frequency (ville) Update function comments to match the code (Deepak) v3: Fix get/put across idle frequency Request. (Ville) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75244 suggested-by: Jesse Barnes Signed-off-by: Deepak S Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 41 +++++++++++------------------------------ 1 file changed, 11 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f08264ca1d30..d22bba98d83f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4097,51 +4097,32 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); } -/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down +/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down * * * If Gfx is Idle, then - * 1. Mask Turbo interrupts - * 2. Bring up Gfx clock - * 3. Change the freq to Rpn and wait till P-Unit updates freq - * 4. Clear the Force GFX CLK ON bit so that Gfx can down - * 5. Unmask Turbo interrupts + * 1. Forcewake Media well. + * 2. Request idle freq. + * 3. Release Forcewake of Media well. */ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; u32 val = dev_priv->rps.idle_freq; - /* CHV and latest VLV don't need to force the gfx clock */ - if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) { + /* CHV don't need to force the gfx clock */ + if (IS_CHERRYVIEW(dev)) { valleyview_set_rps(dev_priv->dev, val); return; } - /* - * When we are idle. Drop to min voltage state. - */ - if (dev_priv->rps.cur_freq <= val) return; - /* Mask turbo interrupt so that they will not come in between */ - I915_WRITE(GEN6_PMINTRMSK, - gen6_sanitize_rps_pm_mask(dev_priv, ~0)); - - vlv_force_gfx_clock(dev_priv, true); - - dev_priv->rps.cur_freq = val; - - vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); - - if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) - & GENFREQSTATUS) == 0, 100)) - DRM_ERROR("timed out waiting for Punit\n"); - - gen6_set_rps_thresholds(dev_priv, val); - vlv_force_gfx_clock(dev_priv, false); - - I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); + /* Wake up the media well, as that takes a lot less + * power than the Render well. */ + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); + valleyview_set_rps(dev_priv->dev, val); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); } void gen6_rps_busy(struct drm_i915_private *dev_priv) -- cgit v1.2.3 From 4a7624f664a239a11dfa71ccd9e741df29047508 Mon Sep 17 00:00:00 2001 From: Deepak S Date: Sat, 9 May 2015 18:11:54 +0530 Subject: drm/i915/chv: Extend set idle rps wa to chv MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is observed on BSW that requesting a new frequency from Punit does nothing when the GPU is in rc6, and if we let GPU enter rc6 with a high frequency, Vnn remains slightly higher than at minimum frequency. Extending vlv_set_rps_idle() workaround on CHV/BSW. v2: Update commit msg (Ville) suggested-by: Ville Syrjälä Signed-off-by: Deepak S Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d22bba98d83f..2b016f2e3465 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4106,15 +4106,8 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) */ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; u32 val = dev_priv->rps.idle_freq; - /* CHV don't need to force the gfx clock */ - if (IS_CHERRYVIEW(dev)) { - valleyview_set_rps(dev_priv->dev, val); - return; - } - if (dev_priv->rps.cur_freq <= val) return; -- cgit v1.2.3 From 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44 Mon Sep 17 00:00:00 2001 From: Deepak S Date: Sat, 9 May 2015 18:15:46 +0530 Subject: drm/i915/chv: Set min freq to efficient frequency on chv MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After feedback from the hardware team, now we set the GPU min/idel freq to RPe. Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the frequency to RPn, punit is failing to change the vgg input voltage to minimum :( Since Punit validates the rps range [RPe, RP0]. This patch removes unused cherryview_rps_min_freq function. v2: Change commit message v3: set min_freq before idle_freq (chris) v4: Squash 'Remove unused rps min function' patch Signed-off-by: Deepak S Acked-by: Chris Wilson Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2b016f2e3465..a70b2d1fc844 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4743,24 +4743,6 @@ static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) return rp1; } -static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) -{ - struct drm_device *dev = dev_priv->dev; - u32 val, rpn; - - if (dev->pdev->revision >= 0x20) { - val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); - rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) & - FB_GFX_FREQ_FUSE_MASK); - } else { /* For pre-production hardware */ - val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); - rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & - PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK); - } - - return rpn; -} - static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) { u32 val, rp1; @@ -5012,7 +4994,8 @@ static void cherryview_init_gt_powersave(struct drm_device *dev) intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), dev_priv->rps.rp1_freq); - dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); + /* PUnit validated range is only [RPe, RP0] */ + dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), dev_priv->rps.min_freq); -- cgit v1.2.3 From 2eb49a69b47fb6d8dd17ad3d75620f6ed3f3e0b8 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Fri, 8 May 2015 13:02:36 +0100 Subject: drm/i915: Remove duplicated intel_tile_height declaration Signed-off-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_drv.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 638fc45edbb3..29262228f264 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1067,9 +1067,6 @@ intel_rotation_90_or_270(unsigned int rotation) return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)); } -unsigned int -intel_tile_height(struct drm_device *dev, uint32_t bits_per_pixel, - uint64_t fb_modifier); void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane); -- cgit v1.2.3 From 2614f17d2d2dcf2f8c1a2f4f0ada056ed60d7d8f Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Fri, 8 May 2015 20:22:46 -0700 Subject: drm/i915: call intel_tile_height with correct parameter In skylake update plane functions, intel_tile_height() is called with bits_per_pixel instead of pixel_format. Correcting it. Signed-off-by: Chandra Konduru Reviewed-by: Tvrtko Ursulin [danvet: Fixup alignment.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_sprite.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4a043a558871..da64f0ed7b93 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3115,7 +3115,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, if (intel_rotation_90_or_270(rotation)) { /* stride = Surface height in tiles */ - tile_height = intel_tile_height(dev, fb->bits_per_pixel, + tile_height = intel_tile_height(dev, fb->pixel_format, fb->modifier[0]); stride = DIV_ROUND_UP(fb->height, tile_height); x_offset = stride * tile_height - y - src_h; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index f215e223aa4a..497e7953ad4d 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -229,8 +229,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, if (intel_rotation_90_or_270(rotation)) { /* stride: Surface height in tiles */ - tile_height = intel_tile_height(dev, fb->bits_per_pixel, - fb->modifier[0]); + tile_height = intel_tile_height(dev, fb->pixel_format, + fb->modifier[0]); stride = DIV_ROUND_UP(fb->height, tile_height); plane_size = (src_w << 16) | src_h; x_offset = stride * tile_height - y - (src_h + 1); -- cgit v1.2.3 From 779949f4b1968d28229e7375fd199f54ed883dc4 Mon Sep 17 00:00:00 2001 From: Peter Antoine Date: Mon, 11 May 2015 16:03:27 +0100 Subject: drm/i915: Warn when execlists changes context without IRQs If an batch ends while the IRQs are not turned on the notification can go missing and the GPU can hang. So generate a warning in this case. Signed-off-by: Peter Antoine Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_lrc.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 0fa9209ff556..0413b8f85c55 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -394,6 +394,12 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring) assert_spin_locked(&ring->execlist_lock); + /* + * If irqs are not active generate a warning as batches that finish + * without the irqs may get lost and a GPU Hang may occur. + */ + WARN_ON(!intel_irqs_enabled(ring->dev->dev_private)); + if (list_empty(&ring->execlist_queue)) return; -- cgit v1.2.3 From 2e2f351dbf29681d54a3a0f1003c5bb9bc832072 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 13:41:14 +0100 Subject: drm/i915: Remove domain flubbing from i915_gem_object_finish_gpu() We no longer interpolate domains in the same manner, and even if we did, we should trust setting either of the other write domains would trigger an invalidation rather than force it. Remove the tweaking of the read_domains since it serves no purpose and use i915_gem_object_wait_rendering() directly. Note that this goes back to commit a8198eea156df47e0e843ac5c7d4c8774e121c42 Author: Chris Wilson Date: Wed Apr 13 22:04:09 2011 +0100 drm/i915: Introduce i915_gem_object_finish_gpu() and gpu domain tracking died in commit cc889e0f6ce6a63c62db17d702ecfed86d58083f Author: Daniel Vetter Date: Wed Jun 13 20:45:19 2012 +0200 drm/i915: disable flushing_list/gpu_write_list which is more than 1 year older. Signed-off-by: Chris Wilson [danvet: Add notes with information dug out of git history.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 4 +++- drivers/gpu/drm/i915/i915_gem.c | 26 +++----------------------- drivers/gpu/drm/i915/intel_display.c | 13 ++++++++----- 3 files changed, 14 insertions(+), 29 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6b3142a99171..1b539057b264 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2821,7 +2821,6 @@ static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) void i915_gem_reset(struct drm_device *dev); bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); -int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); int __must_check i915_gem_init(struct drm_device *dev); int i915_gem_init_rings(struct drm_device *dev); int __must_check i915_gem_init_hw(struct drm_device *dev); @@ -2843,6 +2842,9 @@ int __i915_wait_request(struct drm_i915_gem_request *req, int __must_check i915_wait_request(struct drm_i915_gem_request *req); int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); int __must_check +i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, + bool readonly); +int __must_check i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write); int __must_check diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fb48e7277252..5ff96f94c2ee 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -40,9 +40,6 @@ static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); -static __must_check int -i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, - bool readonly); static void i915_gem_object_retire(struct drm_i915_gem_object *obj); @@ -1397,7 +1394,7 @@ i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) * Ensures that all rendering to the object has completed and the object is * safe to unbind from the GTT or access from the CPU. */ -static __must_check int +int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, bool readonly) { @@ -3078,7 +3075,7 @@ int i915_vma_unbind(struct i915_vma *vma) BUG_ON(obj->pages == NULL); - ret = i915_gem_object_finish_gpu(obj); + ret = i915_gem_object_wait_rendering(obj, false); if (ret) return ret; /* Continue on if we fail due to EIO, the GPU is hung so we @@ -3853,7 +3850,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, } if (i915_gem_obj_bound_any(obj)) { - ret = i915_gem_object_finish_gpu(obj); + ret = i915_gem_object_wait_rendering(obj, false); if (ret) return ret; @@ -4044,23 +4041,6 @@ i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, obj->pin_display--; } -int -i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) -{ - int ret; - - if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) - return 0; - - ret = i915_gem_object_wait_rendering(obj, false); - if (ret) - return ret; - - /* Ensure that we invalidate the GPU's caches and TLBs. */ - obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; - return 0; -} - /** * Moves a single object to the CPU read, and possibly write domain. * diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index da64f0ed7b93..c890e03939fa 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3295,27 +3295,30 @@ void intel_finish_reset(struct drm_device *dev) drm_modeset_unlock_all(dev); } -static int +static void intel_finish_fb(struct drm_framebuffer *old_fb) { struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); - struct drm_i915_private *dev_priv = obj->base.dev->dev_private; + struct drm_i915_private *dev_priv = to_i915(obj->base.dev); bool was_interruptible = dev_priv->mm.interruptible; int ret; /* Big Hammer, we also need to ensure that any pending * MI_WAIT_FOR_EVENT inside a user batch buffer on the * current scanout is retired before unpinning the old - * framebuffer. + * framebuffer. Note that we rely on userspace rendering + * into the buffer attached to the pipe they are waiting + * on. If not, userspace generates a GPU hang with IPEHR + * point to the MI_WAIT_FOR_EVENT. * * This should only fail upon a hung GPU, in which case we * can safely continue. */ dev_priv->mm.interruptible = false; - ret = i915_gem_object_finish_gpu(obj); + ret = i915_gem_object_wait_rendering(obj, true); dev_priv->mm.interruptible = was_interruptible; - return ret; + WARN_ON(ret); } static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) -- cgit v1.2.3 From d94b5030d26b4f45510a092262bc2b542a00bd7c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 13:41:15 +0100 Subject: drm/i915: Ensure cache flushes prior to doing CS flips Synchronising to an object active on the same ring is a no-op, for the benefit of execbuffer scheduler. However, for CS flips this means that we can forgo checking whether the last write request of the object is actually queued and more importantly whether the cache flush for the write was emitted. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c890e03939fa..3c8801cecd3f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11040,6 +11040,12 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, i915_gem_request_assign(&work->flip_queued_req, obj->last_write_req); } else { + if (obj->last_write_req) { + ret = i915_gem_check_olr(obj->last_write_req); + if (ret) + goto cleanup_unpin; + } + ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags); if (ret) -- cgit v1.2.3 From b2cfe0ab63ad2de90a72ae6e5c05d05600f8c144 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 13:41:16 +0100 Subject: drm/i915: Fix race on unreferencing the wrong mmio-flip-request As we perform the mmio-flip without any locking and then try to acquire the struct_mutex prior to dereferencing the request, it is possible for userspace to queue a new pageflip before the worker can finish clearing the old state - and then it will clear the new flip request. The result is that the new flip could be completed before the GPU has finished rendering. The bugs stems from removing the seqno checking in commit 536f5b5e86b225dab94c7ff8061ae482b6077387 Author: Ander Conselvan de Oliveira Date: Thu Nov 6 11:03:40 2014 +0200 drm/i915: Make mmio flip wait for seqno in the work function Signed-off-by: Chris Wilson Cc: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 6 ++++-- drivers/gpu/drm/i915/intel_display.c | 39 ++++++++++++++++++------------------ drivers/gpu/drm/i915/intel_drv.h | 4 ++-- 3 files changed, 25 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1b539057b264..6a66d6b7d33b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2161,10 +2161,12 @@ i915_gem_request_get_ring(struct drm_i915_gem_request *req) return req ? req->ring : NULL; } -static inline void +static inline struct drm_i915_gem_request * i915_gem_request_reference(struct drm_i915_gem_request *req) { - kref_get(&req->ref); + if (req) + kref_get(&req->ref); + return req; } static inline void diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3c8801cecd3f..f2ec1d6f9c6a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10793,22 +10793,18 @@ static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) static void intel_mmio_flip_work_func(struct work_struct *work) { - struct intel_crtc *crtc = - container_of(work, struct intel_crtc, mmio_flip.work); - struct intel_mmio_flip *mmio_flip; + struct intel_mmio_flip *mmio_flip = + container_of(work, struct intel_mmio_flip, work); - mmio_flip = &crtc->mmio_flip; - if (mmio_flip->req) - WARN_ON(__i915_wait_request(mmio_flip->req, - crtc->reset_counter, - false, NULL, NULL) != 0); + if (mmio_flip->rq) + WARN_ON(__i915_wait_request(mmio_flip->rq, + mmio_flip->crtc->reset_counter, + false, NULL, NULL)); - intel_do_mmio_flip(crtc); - if (mmio_flip->req) { - mutex_lock(&crtc->base.dev->struct_mutex); - i915_gem_request_assign(&mmio_flip->req, NULL); - mutex_unlock(&crtc->base.dev->struct_mutex); - } + intel_do_mmio_flip(mmio_flip->crtc); + + i915_gem_request_unreference__unlocked(mmio_flip->rq); + kfree(mmio_flip); } static int intel_queue_mmio_flip(struct drm_device *dev, @@ -10818,12 +10814,17 @@ static int intel_queue_mmio_flip(struct drm_device *dev, struct intel_engine_cs *ring, uint32_t flags) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_mmio_flip *mmio_flip; + + mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); + if (mmio_flip == NULL) + return -ENOMEM; - i915_gem_request_assign(&intel_crtc->mmio_flip.req, - obj->last_write_req); + mmio_flip->rq = i915_gem_request_reference(obj->last_write_req); + mmio_flip->crtc = to_intel_crtc(crtc); - schedule_work(&intel_crtc->mmio_flip.work); + INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); + schedule_work(&mmio_flip->work); return 0; } @@ -13564,8 +13565,6 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; - INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); - drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 29262228f264..47bc729043c5 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -459,8 +459,9 @@ struct intel_pipe_wm { }; struct intel_mmio_flip { - struct drm_i915_gem_request *req; struct work_struct work; + struct drm_i915_gem_request *rq; + struct intel_crtc *crtc; }; struct skl_pipe_wm { @@ -544,7 +545,6 @@ struct intel_crtc { } wm; int scanline_offset; - struct intel_mmio_flip mmio_flip; struct intel_crtc_atomic_commit atomic; -- cgit v1.2.3 From af99ceda2d09ca57f6f3de2f71ae0d32a51c7016 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Mon, 11 May 2015 14:35:47 -0700 Subject: drm/i915: Make scaler_id check in check_crtc_state work for all gens During check_crtc_state, scaler_id mispatch is being reported for HSW. This is applicable for skl+ and not for HSW. It is introduced by commit id: commit a1b2278e4dfcd2dbea85e319ebf73a6b7b2f180b Author: Chandra Konduru Date: Tue Apr 7 15:28:45 2015 -0700 drm/i915: skylake panel fitting using shared scalers This patch will make sure that we leave scaler_id as 0 for platforms before skl and set for skl+ only. This way scaler_id check during check_crtc_state will pass for both prior to skl and skl+ platforms. v2: -Leave scaler_id as 0 for gen < 9 (Daniel) Signed-off-by: Chandra Konduru References: http://lists.freedesktop.org/archives/intel-gfx/2015-May/065741.html Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f2ec1d6f9c6a..895d7c762584 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9356,6 +9356,12 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, } pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); + + if (INTEL_INFO(dev)->gen >= 9) { + pipe_config->scaler_state.scaler_id = -1; + pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); + } + if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { if (INTEL_INFO(dev)->gen == 9) skylake_get_pfit_config(crtc, pipe_config); @@ -9363,10 +9369,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, ironlake_get_pfit_config(crtc, pipe_config); else MISSING_CASE(INTEL_INFO(dev)->gen); - - } else { - pipe_config->scaler_state.scaler_id = -1; - pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); } if (IS_HASWELL(dev)) @@ -13266,8 +13268,8 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, primary->max_downscale = 1; if (INTEL_INFO(dev)->gen >= 9) { primary->can_scale = true; + state->scaler_id = -1; } - state->scaler_id = -1; primary->pipe = pipe; primary->plane = pipe; primary->check_plane = intel_check_primary_plane; @@ -13449,7 +13451,6 @@ static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, cursor->max_downscale = 1; cursor->pipe = pipe; cursor->plane = pipe; - state->scaler_id = -1; cursor->check_plane = intel_check_cursor_plane; cursor->commit_plane = intel_commit_cursor_plane; cursor->disable_plane = intel_disable_cursor_plane; @@ -13472,6 +13473,9 @@ static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, state->base.rotation); } + if (INTEL_INFO(dev)->gen >=9) + state->scaler_id = -1; + drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); return &cursor->base; -- cgit v1.2.3 From f3e06f1156f1adf17dc44144ad3b774c2d414e47 Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Tue, 12 May 2015 10:35:08 +0300 Subject: drm/i915/gtt: Fix the boundary check for vm area MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The check for start + length >= total_vm_size is wrong since start + length can be exactly the size of the vm. Fix the check to allow allocation to boundary. Fixes a regression in commit 4dd738e9cd79 ("drm/i915: Fix 32b overflow check in gen8_ppgtt_alloc_page_directories") Testcase: igt/gem_evict_everything/swapping-interruptible Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90399 Tested-by: Lu Hua Cc: Chris Wilson Cc: Dave Gordon Cc: Ville Syrjälä Cc: Michel Thierry Signed-off-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index e3bcc3ba7e40..17b7df0b561f 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -757,7 +757,7 @@ static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES)); /* FIXME: upper bound must not overflow 32 bits */ - WARN_ON((start + length) >= (1ULL << 32)); + WARN_ON((start + length) > (1ULL << 32)); gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { if (pd) -- cgit v1.2.3 From 8fc3b42ef3818d463f70d2df7c3ffd08faf39055 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 11 May 2015 20:49:09 +0300 Subject: drm/i915: Remove excess inline keywords MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove some inline keywords. One of the functions has clearly outgrown it anyway, so let's just leave it to the compiler. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9da955e4f355..9c5371b7d3b9 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1386,7 +1386,7 @@ static int i915_port_to_hotplug_shift(enum port port) } } -static inline enum port get_port_from_pin(enum hpd_pin pin) +static enum port get_port_from_pin(enum hpd_pin pin) { switch (pin) { case HPD_PORT_B: @@ -1400,10 +1400,10 @@ static inline enum port get_port_from_pin(enum hpd_pin pin) } } -static inline void intel_hpd_irq_handler(struct drm_device *dev, - u32 hotplug_trigger, - u32 dig_hotplug_reg, - const u32 hpd[HPD_NUM_PINS]) +static void intel_hpd_irq_handler(struct drm_device *dev, + u32 hotplug_trigger, + u32 dig_hotplug_reg, + const u32 hpd[HPD_NUM_PINS]) { struct drm_i915_private *dev_priv = dev->dev_private; int i; -- cgit v1.2.3 From 4bca26d0a6518d51a9abe64fbde4b12f04c74053 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 11 May 2015 20:49:10 +0300 Subject: drm/i915: Use HOTPLUG_INT_STATUS_G4X on VLV/CHV MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use HOTPLUG_INT_STATUS_G4X instead of HOTPLUG_INT_STATUS_I915 on VLV/CHV so that we don't confuse the AUX status bits with SDVO status bits. Avoid pointless log spam as below while handling AUX interrupts: [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000 [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000 [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000 [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000 [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000 [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064 Note that there's no functional issue, it's just that the sdvo bits overlap with the dp aux bits. Hence every time we receive an aux interrupt we also think there's an sdvo hpd interrupt, but due to lack of any sdvo encoders nothing ever happens because of that. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula [danvet: Add Ville's explanation why nothing functional really changes.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9c5371b7d3b9..557af8877a2e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -79,7 +79,7 @@ static const u32 hpd_status_g4x[HPD_NUM_PINS] = { [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS }; -static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */ +static const u32 hpd_status_i915[HPD_NUM_PINS] = { [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, @@ -1743,7 +1743,7 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev) */ POSTING_READ(PORT_HOTPLUG_STAT); - if (IS_G4X(dev)) { + if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x); -- cgit v1.2.3 From e8ef3b4c9dadd4ca4a58282927cd2a9b34804089 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 15 Apr 2015 15:18:28 +0300 Subject: drm/i915: constify find_section in VBT parsing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make input and output of find_section const, and fix the fallout. We shouldn't modify the VBT, so make the compiler help us here. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_bios.c | 60 ++++++++++++++++++++------------------- 1 file changed, 31 insertions(+), 29 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index cee596d0a6a2..5876e7cb132d 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -36,10 +36,11 @@ static int panel_type; -static void * -find_section(struct bdb_header *bdb, int section_id) +static const void * +find_section(const void *_bdb, int section_id) { - u8 *base = (u8 *)bdb; + const struct bdb_header *bdb = _bdb; + const u8 *base = _bdb; int index = 0; u16 total, current_size; u8 current_id; @@ -53,7 +54,7 @@ find_section(struct bdb_header *bdb, int section_id) current_id = *(base + index); index++; - current_size = *((u16 *)(base + index)); + current_size = *((const u16 *)(base + index)); index += 2; if (index + current_size > total) @@ -69,7 +70,7 @@ find_section(struct bdb_header *bdb, int section_id) } static u16 -get_blocksize(void *p) +get_blocksize(const void *p) { u16 *block_ptr, block_size; @@ -350,7 +351,7 @@ static void parse_sdvo_panel_data(struct drm_i915_private *dev_priv, struct bdb_header *bdb) { - struct lvds_dvo_timing *dvo_timing; + const struct lvds_dvo_timing *dvo_timing; struct drm_display_mode *panel_fixed_mode; int index; @@ -361,7 +362,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv, } if (index == -1) { - struct bdb_sdvo_lvds_options *sdvo_lvds_options; + const struct bdb_sdvo_lvds_options *sdvo_lvds_options; sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS); if (!sdvo_lvds_options) @@ -405,7 +406,7 @@ parse_general_features(struct drm_i915_private *dev_priv, struct bdb_header *bdb) { struct drm_device *dev = dev_priv->dev; - struct bdb_general_features *general; + const struct bdb_general_features *general; general = find_section(bdb, BDB_GENERAL_FEATURES); if (general) { @@ -430,7 +431,7 @@ static void parse_general_definitions(struct drm_i915_private *dev_priv, struct bdb_header *bdb) { - struct bdb_general_definitions *general; + const struct bdb_general_definitions *general; general = find_section(bdb, BDB_GENERAL_DEFINITIONS); if (general) { @@ -447,10 +448,10 @@ parse_general_definitions(struct drm_i915_private *dev_priv, } } -static union child_device_config * -child_device_ptr(struct bdb_general_definitions *p_defs, int i) +static const union child_device_config * +child_device_ptr(const struct bdb_general_definitions *p_defs, int i) { - return (void *) &p_defs->devices[i * p_defs->child_dev_size]; + return (const void *) &p_defs->devices[i * p_defs->child_dev_size]; } static void @@ -458,8 +459,8 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, struct bdb_header *bdb) { struct sdvo_device_mapping *p_mapping; - struct bdb_general_definitions *p_defs; - union child_device_config *p_child; + const struct bdb_general_definitions *p_defs; + const union child_device_config *p_child; int i, child_device_num, count; u16 block_size; @@ -547,7 +548,7 @@ static void parse_driver_features(struct drm_i915_private *dev_priv, struct bdb_header *bdb) { - struct bdb_driver_features *driver; + const struct bdb_driver_features *driver; driver = find_section(bdb, BDB_DRIVER_FEATURES); if (!driver) @@ -573,9 +574,9 @@ parse_driver_features(struct drm_i915_private *dev_priv, static void parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb) { - struct bdb_edp *edp; - struct edp_power_seq *edp_pps; - struct edp_link_params *edp_link_params; + const struct bdb_edp *edp; + const struct edp_power_seq *edp_pps; + const struct edp_link_params *edp_link_params; edp = find_section(bdb, BDB_EDP); if (!edp) { @@ -685,8 +686,8 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb) static void parse_psr(struct drm_i915_private *dev_priv, struct bdb_header *bdb) { - struct bdb_psr *psr; - struct psr_table *psr_table; + const struct bdb_psr *psr; + const struct psr_table *psr_table; psr = find_section(bdb, BDB_PSR); if (!psr) { @@ -796,11 +797,12 @@ static u8 *goto_next_sequence(u8 *data, int *size) static void parse_mipi(struct drm_i915_private *dev_priv, struct bdb_header *bdb) { - struct bdb_mipi_config *start; - struct bdb_mipi_sequence *sequence; - struct mipi_config *config; - struct mipi_pps_data *pps; - u8 *data, *seq_data; + const struct bdb_mipi_config *start; + const struct bdb_mipi_sequence *sequence; + const struct mipi_config *config; + const struct mipi_pps_data *pps; + u8 *data; + const u8 *seq_data; int i, panel_id, seq_size; u16 block_size; @@ -1068,8 +1070,9 @@ static void parse_device_mapping(struct drm_i915_private *dev_priv, struct bdb_header *bdb) { - struct bdb_general_definitions *p_defs; - union child_device_config *p_child, *child_dev_ptr; + const struct bdb_general_definitions *p_defs; + const union child_device_config *p_child; + union child_device_config *child_dev_ptr; int i, child_device_num, count; u16 block_size; @@ -1126,8 +1129,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv, child_dev_ptr = dev_priv->vbt.child_dev + count; count++; - memcpy((void *)child_dev_ptr, (void *)p_child, - sizeof(*p_child)); + memcpy(child_dev_ptr, p_child, sizeof(*p_child)); } return; } -- cgit v1.2.3 From dcb58a40caeb77b937d7930eafc5bd22373a754e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 May 2015 15:41:32 +0300 Subject: drm/i915: constify validate_vbt in VBT parsing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make input and output of validate_vbt const, and fix the fallout. We shouldn't modify the VBT, so make the compiler help us here. v2: use pointer arithmetics on void* to simplify (Ville) Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_bios.c | 49 ++++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 5876e7cb132d..cbd16c01959a 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -205,7 +205,7 @@ get_lvds_fp_timing(const struct bdb_header *bdb, /* Try to find integrated panel data */ static void parse_lfp_panel_data(struct drm_i915_private *dev_priv, - struct bdb_header *bdb) + const struct bdb_header *bdb) { const struct bdb_lvds_options *lvds_options; const struct bdb_lvds_lfp_data *lvds_lfp_data; @@ -311,7 +311,8 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv, } static void -parse_lfp_backlight(struct drm_i915_private *dev_priv, struct bdb_header *bdb) +parse_lfp_backlight(struct drm_i915_private *dev_priv, + const struct bdb_header *bdb) { const struct bdb_lfp_backlight_data *backlight_data; const struct bdb_lfp_backlight_data_entry *entry; @@ -349,7 +350,7 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv, struct bdb_header *bdb) /* Try to find sdvo panel data */ static void parse_sdvo_panel_data(struct drm_i915_private *dev_priv, - struct bdb_header *bdb) + const struct bdb_header *bdb) { const struct lvds_dvo_timing *dvo_timing; struct drm_display_mode *panel_fixed_mode; @@ -403,7 +404,7 @@ static int intel_bios_ssc_frequency(struct drm_device *dev, static void parse_general_features(struct drm_i915_private *dev_priv, - struct bdb_header *bdb) + const struct bdb_header *bdb) { struct drm_device *dev = dev_priv->dev; const struct bdb_general_features *general; @@ -429,7 +430,7 @@ parse_general_features(struct drm_i915_private *dev_priv, static void parse_general_definitions(struct drm_i915_private *dev_priv, - struct bdb_header *bdb) + const struct bdb_header *bdb) { const struct bdb_general_definitions *general; @@ -456,7 +457,7 @@ child_device_ptr(const struct bdb_general_definitions *p_defs, int i) static void parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, - struct bdb_header *bdb) + const struct bdb_header *bdb) { struct sdvo_device_mapping *p_mapping; const struct bdb_general_definitions *p_defs; @@ -546,7 +547,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, static void parse_driver_features(struct drm_i915_private *dev_priv, - struct bdb_header *bdb) + const struct bdb_header *bdb) { const struct bdb_driver_features *driver; @@ -572,7 +573,7 @@ parse_driver_features(struct drm_i915_private *dev_priv, } static void -parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb) +parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) { const struct bdb_edp *edp; const struct edp_power_seq *edp_pps; @@ -684,7 +685,7 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb) } static void -parse_psr(struct drm_i915_private *dev_priv, struct bdb_header *bdb) +parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) { const struct bdb_psr *psr; const struct psr_table *psr_table; @@ -795,7 +796,7 @@ static u8 *goto_next_sequence(u8 *data, int *size) } static void -parse_mipi(struct drm_i915_private *dev_priv, struct bdb_header *bdb) +parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) { const struct bdb_mipi_config *start; const struct bdb_mipi_sequence *sequence; @@ -946,7 +947,7 @@ err: } static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, - struct bdb_header *bdb) + const struct bdb_header *bdb) { union child_device_config *it, *child = NULL; struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; @@ -1048,7 +1049,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, } static void parse_ddi_ports(struct drm_i915_private *dev_priv, - struct bdb_header *bdb) + const struct bdb_header *bdb) { struct drm_device *dev = dev_priv->dev; enum port port; @@ -1068,7 +1069,7 @@ static void parse_ddi_ports(struct drm_i915_private *dev_priv, static void parse_device_mapping(struct drm_i915_private *dev_priv, - struct bdb_header *bdb) + const struct bdb_header *bdb) { const struct bdb_general_definitions *p_defs; const union child_device_config *p_child; @@ -1198,19 +1199,20 @@ static const struct dmi_system_id intel_no_opregion_vbt[] = { { } }; -static struct bdb_header *validate_vbt(char *base, size_t size, - struct vbt_header *vbt, - const char *source) +static const struct bdb_header *validate_vbt(const void *base, size_t size, + const void *_vbt, + const char *source) { + const struct vbt_header *vbt = _vbt; size_t offset; - struct bdb_header *bdb; + const struct bdb_header *bdb; if (vbt == NULL) { DRM_DEBUG_DRIVER("VBT signature missing\n"); return NULL; } - offset = (char *)vbt - base; + offset = _vbt - base; if (offset + sizeof(struct vbt_header) > size) { DRM_DEBUG_DRIVER("VBT header incomplete\n"); return NULL; @@ -1227,7 +1229,7 @@ static struct bdb_header *validate_vbt(char *base, size_t size, return NULL; } - bdb = (struct bdb_header *)(base + offset); + bdb = base + offset; if (offset + bdb->bdb_size > size) { DRM_DEBUG_DRIVER("BDB incomplete\n"); return NULL; @@ -1252,7 +1254,7 @@ intel_parse_bios(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct pci_dev *pdev = dev->pdev; - struct bdb_header *bdb = NULL; + const struct bdb_header *bdb = NULL; u8 __iomem *bios = NULL; if (HAS_PCH_NOP(dev)) @@ -1262,9 +1264,8 @@ intel_parse_bios(struct drm_device *dev) /* XXX Should this validation be moved to intel_opregion.c? */ if (!dmi_check_system(intel_no_opregion_vbt) && dev_priv->opregion.vbt) - bdb = validate_vbt((char *)dev_priv->opregion.header, OPREGION_SIZE, - (struct vbt_header *)dev_priv->opregion.vbt, - "OpRegion"); + bdb = validate_vbt(dev_priv->opregion.header, OPREGION_SIZE, + dev_priv->opregion.vbt, "OpRegion"); if (bdb == NULL) { size_t i, size; @@ -1277,7 +1278,7 @@ intel_parse_bios(struct drm_device *dev) for (i = 0; i + 4 < size; i++) { if (memcmp(bios + i, "$VBT", 4) == 0) { bdb = validate_vbt(bios, size, - (struct vbt_header *)(bios + i), + bios + i, "PCI ROM"); break; } -- cgit v1.2.3 From c1bad5b6524b2da842f34862ff9c9c57434b35a8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 6 May 2015 15:33:43 +0300 Subject: drm/i915: don't register invalid gmbus pins for bdw Do not expose invalid gmbus pins as i2c devices to userspace. Signed-off-by: Jani Nikula Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_i2c.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 3daa7e322326..76070c4e76b3 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -49,6 +49,13 @@ static const struct gmbus_pin gmbus_pins[] = { [GMBUS_PIN_DPD] = { "dpd", GPIOF }, }; +static const struct gmbus_pin gmbus_pins_bdw[] = { + [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, + [GMBUS_PIN_DPC] = { "dpc", GPIOD }, + [GMBUS_PIN_DPB] = { "dpb", GPIOE }, + [GMBUS_PIN_DPD] = { "dpd", GPIOF }, +}; + static const struct gmbus_pin gmbus_pins_bxt[] = { [GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB }, [GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC }, @@ -61,6 +68,8 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, { if (IS_BROXTON(dev_priv)) return &gmbus_pins_bxt[pin]; + else if (IS_BROADWELL(dev_priv)) + return &gmbus_pins_bdw[pin]; else return &gmbus_pins[pin]; } @@ -72,6 +81,8 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, if (IS_BROXTON(dev_priv)) size = ARRAY_SIZE(gmbus_pins_bxt); + else if (IS_BROADWELL(dev_priv)) + size = ARRAY_SIZE(gmbus_pins_bdw); else size = ARRAY_SIZE(gmbus_pins); -- cgit v1.2.3 From 6364e67e4a2013cae4c7415d0398033cfed21cc3 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 6 May 2015 15:33:44 +0300 Subject: drm/i915: don't register invalid gmbus pins for skl Do not expose invalid gmbus pins as i2c devices to userspace. Signed-off-by: Jani Nikula Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_i2c.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 76070c4e76b3..92072f56e418 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -56,6 +56,12 @@ static const struct gmbus_pin gmbus_pins_bdw[] = { [GMBUS_PIN_DPD] = { "dpd", GPIOF }, }; +static const struct gmbus_pin gmbus_pins_skl[] = { + [GMBUS_PIN_DPC] = { "dpc", GPIOD }, + [GMBUS_PIN_DPB] = { "dpb", GPIOE }, + [GMBUS_PIN_DPD] = { "dpd", GPIOF }, +}; + static const struct gmbus_pin gmbus_pins_bxt[] = { [GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB }, [GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC }, @@ -68,6 +74,8 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, { if (IS_BROXTON(dev_priv)) return &gmbus_pins_bxt[pin]; + else if (IS_SKYLAKE(dev_priv)) + return &gmbus_pins_skl[pin]; else if (IS_BROADWELL(dev_priv)) return &gmbus_pins_bdw[pin]; else @@ -81,6 +89,8 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, if (IS_BROXTON(dev_priv)) size = ARRAY_SIZE(gmbus_pins_bxt); + else if (IS_SKYLAKE(dev_priv)) + size = ARRAY_SIZE(gmbus_pins_skl); else if (IS_BROADWELL(dev_priv)) size = ARRAY_SIZE(gmbus_pins_bdw); else -- cgit v1.2.3 From 7471bf4e0e7ef6c71e1fc7b2574fb8fb19ffb6ee Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 12 May 2015 15:23:09 +0300 Subject: drm/i915: clean up dsi pll calculation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Improve readability. No functional changes. v2: use more rational types (Ville) Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dsi_pll.c | 53 ++++++++++++------------------------ 1 file changed, 17 insertions(+), 36 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index 3622d0bafdf8..cfd527765156 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -162,53 +162,34 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) #endif -static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp) +static int dsi_calc_mnp(int target_dsi_clk, struct dsi_mnp *dsi_mnp) { - u32 m, n, p; - u32 ref_clk; - u32 error; - u32 tmp_error; - int target_dsi_clk; - int calc_dsi_clk; - u32 calc_m; - u32 calc_p; + unsigned int calc_m = 0, calc_p = 0; + unsigned int m, n, p; + int ref_clk = 25000; + int delta = target_dsi_clk; u32 m_seed; - /* dsi_clk is expected in KHZ */ - if (dsi_clk < 300000 || dsi_clk > 1150000) { + /* target_dsi_clk is expected in kHz */ + if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { DRM_ERROR("DSI CLK Out of Range\n"); return -ECHRNG; } - ref_clk = 25000; - target_dsi_clk = dsi_clk; - error = 0xFFFFFFFF; - tmp_error = 0xFFFFFFFF; - calc_m = 0; - calc_p = 0; - - for (m = 62; m <= 92; m++) { - for (p = 2; p <= 6; p++) { - /* Find the optimal m and p divisors - with minimal error +/- the required clock */ - calc_dsi_clk = (m * ref_clk) / p; - if (calc_dsi_clk == target_dsi_clk) { - calc_m = m; - calc_p = p; - error = 0; - break; - } else - tmp_error = abs(target_dsi_clk - calc_dsi_clk); - - if (tmp_error < error) { - error = tmp_error; + for (m = 62; m <= 92 && delta; m++) { + for (p = 2; p <= 6 && delta; p++) { + /* + * Find the optimal m and p divisors with minimal delta + * +/- the required clock + */ + int calc_dsi_clk = (m * ref_clk) / p; + int d = abs(target_dsi_clk - calc_dsi_clk); + if (d < delta) { + delta = d; calc_m = m; calc_p = p; } } - - if (error == 0) - break; } m_seed = lfsr_converts[calc_m - 62]; -- cgit v1.2.3 From b250a4c43c0c3c3f1831d81e7292468ca02f7a5e Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 12 May 2015 16:13:13 +0100 Subject: drm/i915/skl: Leave a new line between variable declarations and code Cc: Chandra Konduru Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 895d7c762584..f533519e0e30 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2954,6 +2954,7 @@ void skl_detach_scalers(struct intel_crtc *intel_crtc) u32 skl_plane_ctl_format(uint32_t pixel_format) { u32 plane_ctl_format = 0; + switch (pixel_format) { case DRM_FORMAT_RGB565: plane_ctl_format = PLANE_CTL_FORMAT_RGB_565; @@ -3004,6 +3005,7 @@ u32 skl_plane_ctl_format(uint32_t pixel_format) u32 skl_plane_ctl_tiling(uint64_t fb_modifier) { u32 plane_ctl_tiling = 0; + switch (fb_modifier) { case DRM_FORMAT_MOD_NONE: break; @@ -3025,6 +3027,7 @@ u32 skl_plane_ctl_tiling(uint64_t fb_modifier) u32 skl_plane_ctl_rotation(unsigned int rotation) { u32 plane_ctl_rotation = 0; + switch (rotation) { case BIT(DRM_ROTATE_0): break; -- cgit v1.2.3 From 8cfcba415e8c0b29fc99d2b0316b868a6a88c2c5 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 12 May 2015 16:13:14 +0100 Subject: drm/i915/skl: Add a new line before return We usually use a new line before those kind of return statements. Also the various skl_plane_ctl*() functions weren't consistent. Cc: Chandra Konduru Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f533519e0e30..c6419e81832b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2999,6 +2999,7 @@ u32 skl_plane_ctl_format(uint32_t pixel_format) default: BUG(); } + return plane_ctl_format; } @@ -3021,6 +3022,7 @@ u32 skl_plane_ctl_tiling(uint64_t fb_modifier) default: MISSING_CASE(fb_modifier); } + return plane_ctl_tiling; } -- cgit v1.2.3 From 65438bcce59756d06d4df398cb1e4b7d82b4c7bc Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 12 May 2015 16:13:15 +0100 Subject: drm/i915/skl: Rename a local variable to fit in 80 chars No reason to not follow the 80 chars rule, renaming the local variable makes it easy. Cc: Chandra Konduru Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c6419e81832b..e2b01d9b504b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2953,17 +2953,17 @@ void skl_detach_scalers(struct intel_crtc *intel_crtc) u32 skl_plane_ctl_format(uint32_t pixel_format) { - u32 plane_ctl_format = 0; + u32 format = 0; switch (pixel_format) { case DRM_FORMAT_RGB565: - plane_ctl_format = PLANE_CTL_FORMAT_RGB_565; + format = PLANE_CTL_FORMAT_RGB_565; break; case DRM_FORMAT_XBGR8888: - plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; + format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; break; case DRM_FORMAT_XRGB8888: - plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888; + format = PLANE_CTL_FORMAT_XRGB_8888; break; /* * XXX: For ARBG/ABGR formats we default to expecting scanout buffers @@ -2971,36 +2971,36 @@ u32 skl_plane_ctl_format(uint32_t pixel_format) * DRM_FORMAT) for user-space to configure that. */ case DRM_FORMAT_ABGR8888: - plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | + format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | PLANE_CTL_ALPHA_SW_PREMULTIPLY; break; case DRM_FORMAT_ARGB8888: - plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | + format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; break; case DRM_FORMAT_XRGB2101010: - plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010; + format = PLANE_CTL_FORMAT_XRGB_2101010; break; case DRM_FORMAT_XBGR2101010: - plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; + format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; break; case DRM_FORMAT_YUYV: - plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; + format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; break; case DRM_FORMAT_YVYU: - plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; + format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; break; case DRM_FORMAT_UYVY: - plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; + format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; break; case DRM_FORMAT_VYUY: - plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; + format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; break; default: BUG(); } - return plane_ctl_format; + return format; } u32 skl_plane_ctl_tiling(uint64_t fb_modifier) -- cgit v1.2.3 From 4249eeef4e0f8b81683930a028cb839cc748786e Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 12 May 2015 16:13:16 +0100 Subject: drm/i915/skl: Replace BUG() by MISSING_CASE() in skl_plane_ctl_format() Let's be consistent with the others skl_plane_ctl_*() functions and use a MISSING_CASE(). Not only that, but it's a rude to BUG() the whole machine here. Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e2b01d9b504b..49d722795ab7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2997,7 +2997,7 @@ u32 skl_plane_ctl_format(uint32_t pixel_format) format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; break; default: - BUG(); + MISSING_CASE(pixel_format); } return format; -- cgit v1.2.3 From d161cf7a6e7e2a134e0f0b393c197e5eb8554a97 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 12 May 2015 16:13:17 +0100 Subject: drm/i915/skl: Support the advertized index format We advertize C8 in the primary plane formats didn't have the corresponding code to set PLANE_CTL accordingly. Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 49d722795ab7..dadb52a4c26c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2956,6 +2956,9 @@ u32 skl_plane_ctl_format(uint32_t pixel_format) u32 format = 0; switch (pixel_format) { + case DRM_FORMAT_C8: + format = PLANE_CTL_FORMAT_INDEXED; + break; case DRM_FORMAT_RGB565: format = PLANE_CTL_FORMAT_RGB_565; break; -- cgit v1.2.3 From 568db4f2536fe5a1a9ce491b17c3d0011d5506d2 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 12 May 2015 16:13:18 +0100 Subject: drm/i915: Don't use the intel_ prefix for gen-specific data We now prefix our functions/enums/data with the first platform it has been introduced. Do that for the primary plane formats. Signed-off-by: Damien Lespiau [danvet: s/gen2/i8xx/ and s/gen4/i965/ ...] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index dadb52a4c26c..23765d2c2ea4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -53,14 +53,14 @@ DRM_FORMAT_ARGB8888 /* Primary plane formats for gen <= 3 */ -static const uint32_t intel_primary_formats_gen2[] = { +static const uint32_t i8xx_primary_formats[] = { COMMON_PRIMARY_FORMATS, DRM_FORMAT_XRGB1555, DRM_FORMAT_ARGB1555, }; /* Primary plane formats for gen >= 4 */ -static const uint32_t intel_primary_formats_gen4[] = { +static const uint32_t i965_primary_formats[] = { COMMON_PRIMARY_FORMATS, \ DRM_FORMAT_XBGR8888, DRM_FORMAT_ABGR8888, @@ -13288,11 +13288,11 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, primary->plane = !pipe; if (INTEL_INFO(dev)->gen <= 3) { - intel_primary_formats = intel_primary_formats_gen2; - num_formats = ARRAY_SIZE(intel_primary_formats_gen2); + intel_primary_formats = i8xx_primary_formats; + num_formats = ARRAY_SIZE(i8xx_primary_formats); } else { - intel_primary_formats = intel_primary_formats_gen4; - num_formats = ARRAY_SIZE(intel_primary_formats_gen4); + intel_primary_formats = i965_primary_formats; + num_formats = ARRAY_SIZE(i965_primary_formats); } drm_universal_plane_init(dev, &primary->base, 0, -- cgit v1.2.3 From dada2d53d88a0071aa75a81023a177411fc6c54d Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 12 May 2015 16:13:22 +0100 Subject: drm/i915: Make the sprite formats const Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_sprite.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 497e7953ad4d..3f70d59dc712 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1052,7 +1052,7 @@ int intel_plane_restore(struct drm_plane *plane) plane->state->src_w, plane->state->src_h); } -static uint32_t ilk_plane_formats[] = { +static const uint32_t ilk_plane_formats[] = { DRM_FORMAT_XRGB8888, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU, @@ -1060,7 +1060,7 @@ static uint32_t ilk_plane_formats[] = { DRM_FORMAT_VYUY, }; -static uint32_t snb_plane_formats[] = { +static const uint32_t snb_plane_formats[] = { DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, DRM_FORMAT_YUYV, @@ -1069,7 +1069,7 @@ static uint32_t snb_plane_formats[] = { DRM_FORMAT_VYUY, }; -static uint32_t vlv_plane_formats[] = { +static const uint32_t vlv_plane_formats[] = { DRM_FORMAT_RGB565, DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888, -- cgit v1.2.3 From 5a1cc6550dc6620e67b792a27da8bbd03a09cafb Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 12 May 2015 21:07:37 +0300 Subject: drm/edid: fix a debug message There is an extra semi-colon on the if statement so the debug output always says "Failed to write EDID checksum" even when it didn't fail. Fixes: 559be30cb74d ('drm/i915: Implement the intel_dp_autotest_edid function for DP EDID complaince tests') Signed-off-by: Dan Carpenter Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index eca82cff40b9..75bccd6ca75b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4142,7 +4142,7 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) if (!drm_dp_dpcd_write(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, &intel_connector->detect_edid->checksum, - 1)); + 1)) DRM_DEBUG_KMS("Failed to write EDID checksum\n"); test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; -- cgit v1.2.3 From 5c1a88754c766b6a66bcd5600de15e4b4baa795a Mon Sep 17 00:00:00 2001 From: Mika Kuoppala Date: Fri, 15 May 2015 13:09:21 +0300 Subject: drm/i915: Don't read dpcd for disconnected ports Reading from disconnected ports will spit out timeout error on the dmesg. Skip the attempted read if the port is not connected and avoid confusing users/testcases about expected timeouts. This new dpcd debugfs entry was introduced by commit aa7471d228eb ("drm/i915: add i915 specific connector debugfs file for DPCD") v2 by Jani: move the check at the top, out of the loop. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90060 Tested-by: yex.tian@intel.com Cc: Jani Nikula Cc: Bob Paauwe Signed-off-by: Mika Kuoppala Signed-off-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index adbbddab42c6..a32b669bab89 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -5154,6 +5154,9 @@ static int i915_dpcd_show(struct seq_file *m, void *data) ssize_t err; int i; + if (connector->status != connector_status_connected) + return -ENODEV; + for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { const struct dpcd_block *b = &i915_dpcd_debug[i]; size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); -- cgit v1.2.3 From aa9145c4fa283da09adb88d65784a39bc454b239 Mon Sep 17 00:00:00 2001 From: Animesh Manna Date: Wed, 13 May 2015 22:13:29 +0530 Subject: drm/i915/skl: Documentation for CSR firmware Added docbook info regarding context save and restore (CSR) firmware support added from gen9 onwards to drive newly added DMC (Display microcontroller) in display engine. v1: Initial version as RFC. v2: Used "DOC:" tag for csr description based on review comment from Daniel. Signed-off-by: Animesh Manna Signed-off-by: A.Sunil Kamath Signed-off-by: Daniel Vetter --- Documentation/DocBook/drm.tmpl | 7 +++++- drivers/gpu/drm/i915/intel_csr.c | 53 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 7c68ecc800a1..b6fc354a20e7 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -4153,6 +4153,12 @@ int num_ioctls;
+ + + CSR firmware support for DMC +!Pdrivers/gpu/drm/i915/intel_csr.c csr support for dmc +!Idrivers/gpu/drm/i915/intel_csr.c + @@ -4204,7 +4210,6 @@ int num_ioctls; !Idrivers/gpu/drm/i915/i915_gem_shrinker.c - Tracing diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 9311cddb86e6..5cb8cc18994a 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -25,6 +25,22 @@ #include "i915_drv.h" #include "i915_reg.h" +/** + * DOC: csr support for dmc + * + * Display Context Save and Restore (CSR) firmware support added from gen9 + * onwards to drive newly added DMC (Display microcontroller) in display + * engine to save and restore the state of display engine when it enter into + * low-power state and comes back to normal. + * + * Firmware loading status will be one of the below states: FW_UNINITIALIZED, + * FW_LOADED, FW_FAILED. + * + * Once the firmware is written into the registers status will be moved from + * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will + * be moved to FW_FAILED. + */ + #define I915_CSR_SKL "i915/skl_dmc_ver4.bin" MODULE_FIRMWARE(I915_CSR_SKL); @@ -183,6 +199,14 @@ static char intel_get_substepping(struct drm_device *dev) return -ENODATA; } +/** + * intel_csr_load_status_get() - to get firmware loading status. + * @dev_priv: i915 device. + * + * This function helps to get the firmware loading status. + * + * Return: Firmware loading status. + */ enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv) { enum csr_state state; @@ -194,6 +218,13 @@ enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv) return state; } +/** + * intel_csr_load_status_set() - help to set firmware loading status. + * @dev_priv: i915 device. + * @state: enumeration of firmware loading status. + * + * Set the firmware loading status. + */ void intel_csr_load_status_set(struct drm_i915_private *dev_priv, enum csr_state state) { @@ -202,6 +233,14 @@ void intel_csr_load_status_set(struct drm_i915_private *dev_priv, mutex_unlock(&dev_priv->csr_lock); } +/** + * intel_csr_load_program() - write the firmware from memory to register. + * @dev: drm device. + * + * CSR firmware is read from a .bin file and kept in internal memory one time. + * Everytime display comes back from low power state this function is called to + * copy the firmware from internal memory to registers. + */ void intel_csr_load_program(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -359,6 +398,13 @@ out: release_firmware(fw); } +/** + * intel_csr_ucode_init() - initialize the firmware loading. + * @dev: drm device. + * + * This function is called at the time of loading the display driver to read + * firmware from a .bin file and copied into a internal memory. + */ void intel_csr_ucode_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -393,6 +439,13 @@ void intel_csr_ucode_init(struct drm_device *dev) } } +/** + * intel_csr_ucode_fini() - unload the CSR firmware. + * @dev: drm device. + * + * Firmmware unloading includes freeing the internal momory and reset the + * firmware loading status. + */ void intel_csr_ucode_fini(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; -- cgit v1.2.3 From a856c5bdf40c218ef1875147455d9d24d01c11c9 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 13 May 2015 10:35:25 +0300 Subject: drm/i915/dsi: add support for DSI PLL N1 divisor values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently DSI PLL N1 is hardcoded off. Make it possible to use it later. This should have no functional changes for now. v2: s/ffz(~(n))/ffs(n) - 1/ (Ville) Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dsi_pll.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index cfd527765156..9688d996af31 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -165,7 +165,7 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) static int dsi_calc_mnp(int target_dsi_clk, struct dsi_mnp *dsi_mnp) { unsigned int calc_m = 0, calc_p = 0; - unsigned int m, n, p; + unsigned int m, n = 1, p; int ref_clk = 25000; int delta = target_dsi_clk; u32 m_seed; @@ -182,7 +182,7 @@ static int dsi_calc_mnp(int target_dsi_clk, struct dsi_mnp *dsi_mnp) * Find the optimal m and p divisors with minimal delta * +/- the required clock */ - int calc_dsi_clk = (m * ref_clk) / p; + int calc_dsi_clk = (m * ref_clk) / (p * n); int d = abs(target_dsi_clk - calc_dsi_clk); if (d < delta) { delta = d; @@ -192,10 +192,11 @@ static int dsi_calc_mnp(int target_dsi_clk, struct dsi_mnp *dsi_mnp) } } + /* register has log2(N1), this works fine for powers of two */ + n = ffs(n) - 1; m_seed = lfsr_converts[calc_m - 62]; - n = 1; dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); - dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT | + dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT | m_seed << DSI_PLL_M1_DIV_SHIFT; return 0; @@ -312,7 +313,7 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); u32 dsi_clock, pclk; u32 pll_ctl, pll_div; - u32 m = 0, p = 0; + u32 m = 0, p = 0, n; int refclk = 25000; int i; @@ -327,6 +328,10 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); + /* N1 divisor */ + n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; + n = 1 << n; /* register has log2(N1) */ + /* mask out the other bits and extract the M1 divisor */ pll_div &= DSI_PLL_M1_DIV_MASK; pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; @@ -354,7 +359,7 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) m = i + 62; - dsi_clock = (m * refclk) / p; + dsi_clock = (m * refclk) / (p * n); /* pixel_format and pipe_bpp should agree */ assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); -- cgit v1.2.3 From c34ce3d19544dc5595938816af675e1e05b95920 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Fri, 15 May 2015 15:07:02 +0100 Subject: drm/i915/skl: Remove unnecessary local variables in skl_plane_ctl*() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Ville noticed in another patch we we didn't need them at all, so remove them. It's worth saying that it makes no difference to code generated as gcc is clever enough to optimize it out. v2: Remove 'break' after 'return' in switches (Ville) Suggested-by: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 66 ++++++++++++------------------------ 1 file changed, 21 insertions(+), 45 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 23765d2c2ea4..62cf92658915 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2953,103 +2953,79 @@ void skl_detach_scalers(struct intel_crtc *intel_crtc) u32 skl_plane_ctl_format(uint32_t pixel_format) { - u32 format = 0; - switch (pixel_format) { case DRM_FORMAT_C8: - format = PLANE_CTL_FORMAT_INDEXED; - break; + return PLANE_CTL_FORMAT_INDEXED; case DRM_FORMAT_RGB565: - format = PLANE_CTL_FORMAT_RGB_565; - break; + return PLANE_CTL_FORMAT_RGB_565; case DRM_FORMAT_XBGR8888: - format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; - break; + return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; case DRM_FORMAT_XRGB8888: - format = PLANE_CTL_FORMAT_XRGB_8888; - break; + return PLANE_CTL_FORMAT_XRGB_8888; /* * XXX: For ARBG/ABGR formats we default to expecting scanout buffers * to be already pre-multiplied. We need to add a knob (or a different * DRM_FORMAT) for user-space to configure that. */ case DRM_FORMAT_ABGR8888: - format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | + return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | PLANE_CTL_ALPHA_SW_PREMULTIPLY; - break; case DRM_FORMAT_ARGB8888: - format = PLANE_CTL_FORMAT_XRGB_8888 | + return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; - break; case DRM_FORMAT_XRGB2101010: - format = PLANE_CTL_FORMAT_XRGB_2101010; - break; + return PLANE_CTL_FORMAT_XRGB_2101010; case DRM_FORMAT_XBGR2101010: - format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; - break; + return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; case DRM_FORMAT_YUYV: - format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; - break; + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; case DRM_FORMAT_YVYU: - format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; - break; + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; case DRM_FORMAT_UYVY: - format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; - break; + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; case DRM_FORMAT_VYUY: - format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; - break; + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; default: MISSING_CASE(pixel_format); } - return format; + return 0; } u32 skl_plane_ctl_tiling(uint64_t fb_modifier) { - u32 plane_ctl_tiling = 0; - switch (fb_modifier) { case DRM_FORMAT_MOD_NONE: break; case I915_FORMAT_MOD_X_TILED: - plane_ctl_tiling = PLANE_CTL_TILED_X; - break; + return PLANE_CTL_TILED_X; case I915_FORMAT_MOD_Y_TILED: - plane_ctl_tiling = PLANE_CTL_TILED_Y; - break; + return PLANE_CTL_TILED_Y; case I915_FORMAT_MOD_Yf_TILED: - plane_ctl_tiling = PLANE_CTL_TILED_YF; - break; + return PLANE_CTL_TILED_YF; default: MISSING_CASE(fb_modifier); } - return plane_ctl_tiling; + return 0; } u32 skl_plane_ctl_rotation(unsigned int rotation) { - u32 plane_ctl_rotation = 0; - switch (rotation) { case BIT(DRM_ROTATE_0): break; case BIT(DRM_ROTATE_90): - plane_ctl_rotation = PLANE_CTL_ROTATE_90; - break; + return PLANE_CTL_ROTATE_90; case BIT(DRM_ROTATE_180): - plane_ctl_rotation = PLANE_CTL_ROTATE_180; - break; + return PLANE_CTL_ROTATE_180; case BIT(DRM_ROTATE_270): - plane_ctl_rotation = PLANE_CTL_ROTATE_270; - break; + return PLANE_CTL_ROTATE_270; default: MISSING_CASE(rotation); } - return plane_ctl_rotation; + return 0; } static void skylake_update_primary_plane(struct drm_crtc *crtc, -- cgit v1.2.3 From 4d70f38a760ad2879d2ebd84001c92980180f630 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 13 May 2015 15:34:03 +0300 Subject: drm/i915/bios: remove a redundant NULL pointer check We never pass a non-NULL vbt to validate_vbt, and we can safely expect the callers to not change. Signed-off-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_bios.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index cbd16c01959a..d39c41cf45a7 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -1207,11 +1207,6 @@ static const struct bdb_header *validate_vbt(const void *base, size_t size, size_t offset; const struct bdb_header *bdb; - if (vbt == NULL) { - DRM_DEBUG_DRIVER("VBT signature missing\n"); - return NULL; - } - offset = _vbt - base; if (offset + sizeof(struct vbt_header) > size) { DRM_DEBUG_DRIVER("VBT header incomplete\n"); -- cgit v1.2.3 From b34a991a2bf5b9bf0b8abcae7d0f8593fd59e909 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 13 May 2015 15:34:04 +0300 Subject: drm/i915/bios: abstract finding VBT in BIOS to a separate function Improve clarity. No functional changes. Signed-off-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_bios.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index d39c41cf45a7..6e018ba53035 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -1235,6 +1235,22 @@ static const struct bdb_header *validate_vbt(const void *base, size_t size, return bdb; } +static const struct bdb_header *find_vbt(void *bios, size_t size) +{ + const struct bdb_header *bdb = NULL; + size_t i; + + /* Scour memory looking for the VBT signature. */ + for (i = 0; i + 4 < size; i++) { + if (memcmp(bios + i, "$VBT", 4) == 0) { + bdb = validate_vbt(bios, size, bios + i, "PCI ROM"); + break; + } + } + + return bdb; +} + /** * intel_parse_bios - find VBT and initialize settings from the BIOS * @dev: DRM device @@ -1263,22 +1279,13 @@ intel_parse_bios(struct drm_device *dev) dev_priv->opregion.vbt, "OpRegion"); if (bdb == NULL) { - size_t i, size; + size_t size; bios = pci_map_rom(pdev, &size); if (!bios) return -1; - /* Scour memory looking for the VBT signature */ - for (i = 0; i + 4 < size; i++) { - if (memcmp(bios + i, "$VBT", 4) == 0) { - bdb = validate_vbt(bios, size, - bios + i, - "PCI ROM"); - break; - } - } - + bdb = find_vbt(bios, size); if (!bdb) { pci_unmap_rom(pdev, bios); return -1; -- cgit v1.2.3 From 0ec463d3102f379443fa6429298461f73aa5db41 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Wed, 13 May 2015 16:51:08 +0100 Subject: drm/i915: Output scaler related pipe config debug in a single line Just so it is grouped logically in line with other data and makes a rather verbose output a bit shorter. Signed-off-by: Tvrtko Ursulin Cc: Chandra Konduru Reviewed-by: Damien Lespiau Reviewed-by: Chandra Konduru Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 62cf92658915..489af1f095e9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11299,9 +11299,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); DRM_DEBUG_KMS("pipe src size: %dx%d\n", pipe_config->pipe_src_w, pipe_config->pipe_src_h); - DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers); - DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users); - DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id); + DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", + crtc->num_scalers, + pipe_config->scaler_state.scaler_users, + pipe_config->scaler_state.scaler_id); DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", pipe_config->gmch_pfit.control, pipe_config->gmch_pfit.pgm_ratios, -- cgit v1.2.3 From acbb47939011f9f64b68592045350c15259e4bd4 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 13 May 2015 15:34:05 +0300 Subject: drm/i915/bios: be more explicit about discarding iomem address space Add one explicit discard of __iomem address space qualifier in validate_vbt(), and respect it otherwise. This adds clarity in the code, and reduces the sparse warnings from the module to just one. Quoting Daniel, "The vbt really is plain old memory. Except that it's reserved in the e820 table as something special and hence treated as io range by the kernel. But it is memory, hence casting away the __iomem is imo the right approach." Signed-off-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_bios.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 6e018ba53035..198fc3c3291b 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -1199,15 +1199,22 @@ static const struct dmi_system_id intel_no_opregion_vbt[] = { { } }; -static const struct bdb_header *validate_vbt(const void *base, size_t size, - const void *_vbt, +static const struct bdb_header *validate_vbt(const void __iomem *_base, + size_t size, + const void __iomem *_vbt, const char *source) { - const struct vbt_header *vbt = _vbt; - size_t offset; + /* + * This is the one place where we explicitly discard the address space + * (__iomem) of the BIOS/VBT. (And this will cause a sparse complaint.) + * From now on everything is based on 'base', and treated as regular + * memory. + */ + const void *base = (const void *) _base; + size_t offset = _vbt - _base; + const struct vbt_header *vbt = base + offset; const struct bdb_header *bdb; - offset = _vbt - base; if (offset + sizeof(struct vbt_header) > size) { DRM_DEBUG_DRIVER("VBT header incomplete\n"); return NULL; @@ -1235,14 +1242,14 @@ static const struct bdb_header *validate_vbt(const void *base, size_t size, return bdb; } -static const struct bdb_header *find_vbt(void *bios, size_t size) +static const struct bdb_header *find_vbt(void __iomem *bios, size_t size) { const struct bdb_header *bdb = NULL; size_t i; /* Scour memory looking for the VBT signature. */ for (i = 0; i + 4 < size; i++) { - if (memcmp(bios + i, "$VBT", 4) == 0) { + if (ioread32(bios + i) == *((const u32 *) "$VBT")) { bdb = validate_vbt(bios, size, bios + i, "PCI ROM"); break; } -- cgit v1.2.3 From dd3cd74acf12723045a64f1f2c6298ac7b34a5d5 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Fri, 15 May 2015 13:34:29 +0300 Subject: drm/i915: Don't overwrite (e)DP PLL selection on SKL In the following commit, the place where the contents of dpll_hw_state in crtc_state where zeroed was changed. Prior to that commit, it happened when the new state was allocated, but now that happens just before the call the .crtc_compute_clock() hook. The DP code for SKL, however, sets up the (private) PLL in the encoder compute config function that has already run by the time that memset() is reached, causing the previous value to be lost. This patch fixes the issue by moving the memset() down the call chain, so that it is only called if the values in dpll_hw_state are going to be updated. commit 4978cc93d9ac240b435ce60431aef24239b4c270 Author: Ander Conselvan de Oliveira Date: Tue Apr 21 17:13:21 2015 +0300 drm/i915: Preserve shared DPLL information in new pipe_config Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90462 Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Damien Lespiau Reported-and-tested-by: Tvrtko Ursulin Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 9 +++++++++ drivers/gpu/drm/i915/intel_display.c | 8 ++++++-- drivers/gpu/drm/i915/intel_dp.c | 3 +++ 3 files changed, 18 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 807e15d41a1b..c82c981758ec 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1087,6 +1087,9 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc, WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p); + memset(&crtc_state->dpll_hw_state, 0, + sizeof(crtc_state->dpll_hw_state)); + crtc_state->dpll_hw_state.wrpll = val; pll = intel_get_shared_dpll(intel_crtc, crtc_state); @@ -1309,6 +1312,9 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc, } else /* eDP */ return true; + memset(&crtc_state->dpll_hw_state, 0, + sizeof(crtc_state->dpll_hw_state)); + crtc_state->dpll_hw_state.ctrl1 = ctrl1; crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; @@ -1419,6 +1425,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, } } + memset(&crtc_state->dpll_hw_state, 0, + sizeof(crtc_state->dpll_hw_state)); + crtc_state->dpll_hw_state.ebb0 = PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 489af1f095e9..0d8369d0dfaa 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7464,6 +7464,9 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, struct drm_connector_state *connector_state; int i; + memset(&crtc_state->dpll_hw_state, 0, + sizeof(crtc_state->dpll_hw_state)); + for_each_connector_in_state(state, connector, connector_state, i) { if (connector_state->crtc != &crtc->base) continue; @@ -8505,6 +8508,9 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, bool is_lvds = false; struct intel_shared_dpll *pll; + memset(&crtc_state->dpll_hw_state, 0, + sizeof(crtc_state->dpll_hw_state)); + is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), @@ -12261,8 +12267,6 @@ static int __intel_set_mode_setup_plls(struct drm_atomic_state *state) if (needs_modeset(crtc_state)) { clear_pipes |= 1 << intel_crtc->pipe; intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; - memset(&intel_crtc_state->dpll_hw_state, 0, - sizeof(intel_crtc_state->dpll_hw_state)); } } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 75bccd6ca75b..f99cca80867c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1097,6 +1097,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock) { u32 ctrl1; + memset(&pipe_config->dpll_hw_state, 0, + sizeof(pipe_config->dpll_hw_state)); + pipe_config->ddi_pll_sel = SKL_DPLL0; pipe_config->dpll_hw_state.cfgcr1 = 0; pipe_config->dpll_hw_state.cfgcr2 = 0; -- cgit v1.2.3 From 415ff0f6eb612465e5b7dd3b8a440aa2601b60a5 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 14 May 2015 13:38:31 +0100 Subject: drm/i915: Dump some DPLL fields in pipe config debug v2: Split strings to 80 char, add ddi_pll_sel and fixed typo. (Damien Lespiau) Signed-off-by: Tvrtko Ursulin Cc: Damien Lespiau Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0d8369d0dfaa..620fdd8077dd 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11320,6 +11320,39 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); + if (IS_BROXTON(dev)) { + DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, " + "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " + "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n", + pipe_config->ddi_pll_sel, + pipe_config->dpll_hw_state.ebb0, + pipe_config->dpll_hw_state.pll0, + pipe_config->dpll_hw_state.pll1, + pipe_config->dpll_hw_state.pll2, + pipe_config->dpll_hw_state.pll3, + pipe_config->dpll_hw_state.pll6, + pipe_config->dpll_hw_state.pll8, + pipe_config->dpll_hw_state.pcsdw12); + } else if (IS_SKYLAKE(dev)) { + DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " + "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", + pipe_config->ddi_pll_sel, + pipe_config->dpll_hw_state.ctrl1, + pipe_config->dpll_hw_state.cfgcr1, + pipe_config->dpll_hw_state.cfgcr2); + } else if (HAS_DDI(dev)) { + DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", + pipe_config->ddi_pll_sel, + pipe_config->dpll_hw_state.wrpll); + } else { + DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " + "fp0: 0x%x, fp1: 0x%x\n", + pipe_config->dpll_hw_state.dpll, + pipe_config->dpll_hw_state.dpll_md, + pipe_config->dpll_hw_state.fp0, + pipe_config->dpll_hw_state.fp1); + } + DRM_DEBUG_KMS("planes on this crtc\n"); list_for_each_entry(plane, &dev->mode_config.plane_list, head) { intel_plane = to_intel_plane(plane); -- cgit v1.2.3 From 8504c74c7ae48b4b8ed1f1c0acf67482a7f45c93 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Fri, 15 May 2015 11:51:50 +0300 Subject: drm/i915: Preserve ddi_pll_sel when allocating new pipe_config When the modeset code is reached with a CRTC that only needs a flip, the code that assigns PLLs is skipped. But since there is still a state swap for that CRTC, the current PLL assignment needs to be preserved. I missed the ddi_pll_sel field in the following commit, which causes warnings in DDI platforms. commit 4978cc93d9ac240b435ce60431aef24239b4c270 Author: Ander Conselvan de Oliveira Date: Tue Apr 21 17:13:21 2015 +0300 drm/i915: Preserve shared DPLL information in new pipe_config Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90410 Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 620fdd8077dd..24f9b3fc6d80 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11490,12 +11490,14 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) struct intel_crtc_scaler_state scaler_state; struct intel_dpll_hw_state dpll_hw_state; enum intel_dpll_id shared_dpll; + uint32_t ddi_pll_sel; /* Clear only the intel specific part of the crtc state excluding scalers */ tmp_state = crtc_state->base; scaler_state = crtc_state->scaler_state; shared_dpll = crtc_state->shared_dpll; dpll_hw_state = crtc_state->dpll_hw_state; + ddi_pll_sel = crtc_state->ddi_pll_sel; memset(crtc_state, 0, sizeof *crtc_state); @@ -11503,6 +11505,7 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) crtc_state->scaler_state = scaler_state; crtc_state->shared_dpll = shared_dpll; crtc_state->dpll_hw_state = dpll_hw_state; + crtc_state->ddi_pll_sel = ddi_pll_sel; } static int -- cgit v1.2.3 From 281400ff0fff07fc37af5ccccc79f47a8d7e8929 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 15 May 2015 11:42:21 +0100 Subject: drm/i915: Use uninterruptible mutex_lock for userptr bo creation Mika encountered one pathological scenario under X where acquiring all the mm locks (required to insert a mmu notifier) was very slow, so slow that by the time we tried to lock the struct_mutex with the usual call to i915_mutex_lock_interruptible(), X's signal timer had fired causing us to restart the ioctl (and so looped indefinitely). While I suspect this is the result of another bug (something leaking mm perhaps?) we can forgo the error checking and interuptible nature of the lock here so we only have to pay the expense once and get on with it. This does expose the userptr creation routine to a driver livelock though by not being interruptible. Signed-off-by: Chris Wilson Cc: Mika Kuoppala [danvet: Init ret to avoid issues reported by PRTS.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_userptr.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c index 4039ede158be..1f4e5a32a16e 100644 --- a/drivers/gpu/drm/i915/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c @@ -219,11 +219,14 @@ i915_mmu_notifier_add(struct drm_device *dev, struct i915_mmu_object *mo) { struct interval_tree_node *it; - int ret; + int ret = 0; - ret = i915_mutex_lock_interruptible(dev); - if (ret) - return ret; + /* By this point we have already done a lot of expensive setup that + * we do not want to repeat just because the caller (e.g. X) has a + * signal pending (and partly because of that expensive setup, X + * using an interrupt timer is likely to get stuck in an EINTR loop). + */ + mutex_lock(&dev->struct_mutex); /* Make sure we drop the final active reference (and thereby * remove the objects from the interval tree) before we do -- cgit v1.2.3 From 67fe7dc5d928de6111062cf73cf13e287b2d55c4 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Fri, 15 May 2015 19:06:00 +0100 Subject: drm/i915: Remove the COMMON_PRIMARY_FORMATS defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit That define makes it hard to figure out what is the actual list of formats at a glance. Expand it then. Suggested-by: Ville Syrjälä Signed-off-by: Damien Lespiau Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 24f9b3fc6d80..9543f947084a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -45,24 +45,23 @@ #include #include -/* Primary plane formats supported by all gen */ -#define COMMON_PRIMARY_FORMATS \ - DRM_FORMAT_C8, \ - DRM_FORMAT_RGB565, \ - DRM_FORMAT_XRGB8888, \ - DRM_FORMAT_ARGB8888 - /* Primary plane formats for gen <= 3 */ static const uint32_t i8xx_primary_formats[] = { - COMMON_PRIMARY_FORMATS, + DRM_FORMAT_C8, + DRM_FORMAT_RGB565, DRM_FORMAT_XRGB1555, DRM_FORMAT_ARGB1555, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, }; /* Primary plane formats for gen >= 4 */ static const uint32_t i965_primary_formats[] = { - COMMON_PRIMARY_FORMATS, \ + DRM_FORMAT_C8, + DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, -- cgit v1.2.3 From 7531208b16a22415aea44a5774931a0783c19daa Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Fri, 15 May 2015 19:06:01 +0100 Subject: drm/i915: Remove ARBG/ABGR 2101010 on platform not supporting those formats MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We just have have VLV and CHV sprites programming the hardware differently for the ABGR2101010 so keep them working. Signed-off-by: Damien Lespiau Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9543f947084a..73f5e5b01125 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -64,9 +64,7 @@ static const uint32_t i965_primary_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, DRM_FORMAT_XRGB2101010, - DRM_FORMAT_ARGB2101010, DRM_FORMAT_XBGR2101010, - DRM_FORMAT_ABGR2101010, }; /* Cursor formats */ @@ -2716,11 +2714,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, dspcntr |= DISPPLANE_RGBX888; break; case DRM_FORMAT_XRGB2101010: - case DRM_FORMAT_ARGB2101010: dspcntr |= DISPPLANE_BGRX101010; break; case DRM_FORMAT_XBGR2101010: - case DRM_FORMAT_ABGR2101010: dspcntr |= DISPPLANE_RGBX101010; break; default: @@ -2824,11 +2820,9 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, dspcntr |= DISPPLANE_RGBX888; break; case DRM_FORMAT_XRGB2101010: - case DRM_FORMAT_ARGB2101010: dspcntr |= DISPPLANE_BGRX101010; break; case DRM_FORMAT_XBGR2101010: - case DRM_FORMAT_ABGR2101010: dspcntr |= DISPPLANE_RGBX101010; break; default: @@ -4518,9 +4512,7 @@ skl_update_scaler_users( case DRM_FORMAT_ABGR8888: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_XRGB2101010: - case DRM_FORMAT_ARGB2101010: case DRM_FORMAT_XBGR2101010: - case DRM_FORMAT_ABGR2101010: case DRM_FORMAT_YUYV: case DRM_FORMAT_YVYU: case DRM_FORMAT_UYVY: @@ -13999,15 +13991,20 @@ static int intel_framebuffer_init(struct drm_device *dev, case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: case DRM_FORMAT_XRGB2101010: - case DRM_FORMAT_ARGB2101010: case DRM_FORMAT_XBGR2101010: - case DRM_FORMAT_ABGR2101010: if (INTEL_INFO(dev)->gen < 4) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format)); return -EINVAL; } break; + case DRM_FORMAT_ABGR2101010: + if (!IS_VALLEYVIEW(dev)) { + DRM_DEBUG("unsupported pixel format: %s\n", + drm_get_format_name(mode_cmd->pixel_format)); + return -EINVAL; + } + break; case DRM_FORMAT_YUYV: case DRM_FORMAT_UYVY: case DRM_FORMAT_YVYU: -- cgit v1.2.3 From 54f0ceef2c66cb6fa5f349c28b94cd1fae9ddab2 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Fri, 15 May 2015 19:06:03 +0100 Subject: drm/i915: Don't expose ARGB1555 on gen2/3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Damien Lespiau Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 73f5e5b01125..8a3d93639181 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -50,7 +50,6 @@ static const uint32_t i8xx_primary_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_RGB565, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, }; @@ -2699,7 +2698,6 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, dspcntr |= DISPPLANE_8BPP; break; case DRM_FORMAT_XRGB1555: - case DRM_FORMAT_ARGB1555: dspcntr |= DISPPLANE_BGRX555; break; case DRM_FORMAT_RGB565: @@ -13981,7 +13979,6 @@ static int intel_framebuffer_init(struct drm_device *dev, case DRM_FORMAT_ARGB8888: break; case DRM_FORMAT_XRGB1555: - case DRM_FORMAT_ARGB1555: if (INTEL_INFO(dev)->gen > 3) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format)); -- cgit v1.2.3 From b2f505be3e5f41306b02bb570a74d71348756ced Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 18 May 2015 16:01:45 +0300 Subject: drm/i915/dp: make link rate printing prettier Turn [drm:intel_dp_print_rates] source rates: 162000,270000,540000, [drm:intel_dp_print_rates] sink rates: 162000,270000, [drm:intel_dp_print_rates] common rates: 162000,270000, into [drm:intel_dp_print_rates] source rates: 162000, 270000, 540000 [drm:intel_dp_print_rates] sink rates: 162000, 270000 [drm:intel_dp_print_rates] common rates: 162000, 270000 Signed-off-by: Jani Nikula Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index f99cca80867c..6e9f14ef2d2d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1269,7 +1269,7 @@ static void snprintf_int_array(char *str, size_t len, str[0] = '\0'; for (i = 0; i < nelem; i++) { - int r = snprintf(str, len, "%d,", array[i]); + int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); if (r >= len) return; str += r; -- cgit v1.2.3 From 0c9b371550f40f8273a835f1e1055445cc3e2498 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 18 May 2015 17:10:01 +0300 Subject: drm/i915: add HAS_DP_MST feature test macro Be in line with other features that we have. Signed-off-by: Jani Nikula Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/intel_dp.c | 10 ++++------ 2 files changed, 7 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6a66d6b7d33b..11e0059abd2c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2448,6 +2448,9 @@ struct drm_i915_cmd_table { #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) +#define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ + INTEL_INFO(dev)->gen >= 9) + #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 6e9f14ef2d2d..0edc30516497 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5817,12 +5817,10 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_dp_aux_init(intel_dp, intel_connector); /* init MST on ports that can support it */ - if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { - if (port == PORT_B || port == PORT_C || port == PORT_D) { - intel_dp_mst_encoder_init(intel_dig_port, - intel_connector->base.base.id); - } - } + if (HAS_DP_MST(dev) && + (port == PORT_B || port == PORT_C || port == PORT_D)) + intel_dp_mst_encoder_init(intel_dig_port, + intel_connector->base.base.id); if (!intel_edp_init_connector(intel_dp, intel_connector)) { drm_dp_aux_unregister(&intel_dp->aux); -- cgit v1.2.3 From b6dc71f38a84e36c5445b95f9f7a2dac6b25636f Mon Sep 17 00:00:00 2001 From: Vandana Kannan Date: Wed, 13 May 2015 12:18:52 +0530 Subject: drm/i915/bxt: Port PLL programming BUN BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to VCO frequencies. Program i_lockthresh in PORT_PLL_9. VCO calculated based on the formula: Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz) Fast Clock = Desired Output / 2 VCO = Fast Clock * P1 * P2 Prop_coeff, int_coeff, and tdctargetcnt modified according to above calculation. BUN 2: Port PLLs require additional programming at certain frequencies - DCO amplitude in PORT_PLL_10 Review comments from Siva which were addressed in the initial version of the patch. - Change PORT_PLL_LOCK_THRESHOLD to PORT_PLL_LOCK_THRESHOLD_MASK - Calculate for HDMI - Correct values for vco = 5.4 - return in case of invalid vco range v2: Imre's review comments addressed - change dcoampovr_en to dcoampovr_en_h - change PORT_PLL_DCO_AMP_OVR_EN to PORT_PLL_DCO_AMP_OVR_EN_H - Correct lane stagger value for 324MHz - Make coef common for HDMI and DP - remove superfluous comments v3: Imre's comments addressed - Remove Prop_coeff, int_coeff, tdctargetcnt, dcoampovr_en, gain_ctl, dcoampovr_en_h from bxt_clk_div and make them local variables. Signed-off-by: Vandana Kannan Reviewed-by: Sivakumar Thulasimani [v1] Cc: Sivakumar Thulasimani Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 6 +++ drivers/gpu/drm/i915/intel_ddi.c | 79 ++++++++++++++++++++++++++++------------ 3 files changed, 63 insertions(+), 24 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 11e0059abd2c..840f08fa5fb3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -309,7 +309,7 @@ struct intel_dpll_hw_state { uint32_t cfgcr1, cfgcr2; /* bxt */ - uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pcsdw12; + uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12; }; struct intel_shared_dpll_config { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 344d132c51ae..04b9f2b4c042 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1204,6 +1204,12 @@ enum skl_disp_power_wells { #define PORT_PLL_GAIN_CTL(x) ((x) << 16) /* PORT_PLL_8_A */ #define PORT_PLL_TARGET_CNT_MASK 0x3FF +/* PORT_PLL_9_A */ +#define PORT_PLL_LOCK_THRESHOLD_MASK 0xe +/* PORT_PLL_10_A */ +#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27) +#define PORT_PLL_DCO_AMP_MASK 0x3c00 +#define PORT_PLL_DCO_AMP(x) (x<<10) #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \ _PORT_PLL_0_B, \ _PORT_PLL_0_C) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index c82c981758ec..d2a8c640782f 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1340,22 +1340,18 @@ struct bxt_clk_div { uint32_t m2_frac; bool m2_frac_en; uint32_t n; - uint32_t prop_coef; - uint32_t int_coef; - uint32_t gain_ctl; - uint32_t targ_cnt; uint32_t lanestagger; }; /* pre-calculated values for DP linkrates */ static struct bxt_clk_div bxt_dp_clk_val[7] = { - /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, - /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd}, - /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18}, - /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, - /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd}, - /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, - /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18} + /* 162 */ {4, 2, 32, 1677722, 1, 1, 0xd}, + /* 270 */ {4, 1, 27, 0, 0, 1, 0xd}, + /* 540 */ {2, 1, 27, 0, 0, 1, 0x18}, + /* 216 */ {3, 2, 32, 1677722, 1, 1, 0xd}, + /* 243 */ {4, 1, 24, 1258291, 1, 1, 0xd}, + /* 324 */ {4, 1, 32, 1677722, 1, 1, 0x18}, + /* 432 */ {3, 1, 32, 1677722, 1, 1, 0x18} }; static bool @@ -1366,6 +1362,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, { struct intel_shared_dpll *pll; struct bxt_clk_div clk_div = {0}; + int vco = 0; + uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; + uint32_t dcoampovr_en_h, dco_amp; if (intel_encoder->type == INTEL_OUTPUT_HDMI) { intel_clock_t best_clock; @@ -1389,11 +1388,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); clk_div.m2_frac_en = clk_div.m2_frac != 0; - /* FIXME: set coef, gain, targcnt based on freq band */ - clk_div.prop_coef = 5; - clk_div.int_coef = 11; - clk_div.gain_ctl = 2; - clk_div.targ_cnt = 9; + vco = best_clock.vco; if (clock > 270000) clk_div.lanestagger = 0x18; else if (clock > 135000) @@ -1423,6 +1418,32 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, clk_div = bxt_dp_clk_val[0]; DRM_ERROR("Unknown link rate\n"); } + vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; + } + + dco_amp = 15; + dcoampovr_en_h = 0; + if (vco >= 6200000 && vco <= 6480000) { + prop_coef = 4; + int_coef = 9; + gain_ctl = 3; + targ_cnt = 8; + } else if ((vco > 5400000 && vco < 6200000) || + (vco >= 4800000 && vco < 5400000)) { + prop_coef = 5; + int_coef = 11; + gain_ctl = 3; + targ_cnt = 9; + if (vco >= 4800000 && vco < 5400000) + dcoampovr_en_h = 1; + } else if (vco == 5400000) { + prop_coef = 3; + int_coef = 8; + gain_ctl = 1; + targ_cnt = 9; + } else { + DRM_ERROR("Invalid VCO\n"); + return false; } memset(&crtc_state->dpll_hw_state, 0, @@ -1439,11 +1460,16 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, PORT_PLL_M2_FRAC_ENABLE; crtc_state->dpll_hw_state.pll6 = - clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef); + prop_coef | PORT_PLL_INT_COEFF(int_coef); crtc_state->dpll_hw_state.pll6 |= - PORT_PLL_GAIN_CTL(clk_div.gain_ctl); + PORT_PLL_GAIN_CTL(gain_ctl); + + crtc_state->dpll_hw_state.pll8 = targ_cnt; - crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt; + if (dcoampovr_en_h) + crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H; + + crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); crtc_state->dpll_hw_state.pcsdw12 = LANESTAGGER_STRAP_OVRD | clk_div.lanestagger; @@ -2376,10 +2402,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, temp |= pll->config.hw_state.pll8; I915_WRITE(BXT_PORT_PLL(port, 8), temp); - /* - * FIXME: program PORT_PLL_9/i_lockthresh according to the latest - * specification update. - */ + temp = I915_READ(BXT_PORT_PLL(port, 9)); + temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; + temp |= (5 << 1); + I915_WRITE(BXT_PORT_PLL(port, 9), temp); + + temp = I915_READ(BXT_PORT_PLL(port, 10)); + temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; + temp &= ~PORT_PLL_DCO_AMP_MASK; + temp |= pll->config.hw_state.pll10; + I915_WRITE(BXT_PORT_PLL(port, 10), temp); /* Recalibrate with new settings */ temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); @@ -2443,6 +2475,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); + hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); /* * While we write to the group register to program all lanes at once we * can read only lane registers. We configure all lanes the same way, so -- cgit v1.2.3 From e0681e3841118b470b312b7c62c90af9364fce8d Mon Sep 17 00:00:00 2001 From: Vandana Kannan Date: Wed, 13 May 2015 12:20:35 +0530 Subject: drm/i915/bxt: Move around lane stagger calculation Making lane stagger calculation common for HDMI and DP v2: Imre's comments addressed - Remove lane stagger from bxt_clk_div and make it a local variable in ddi_pll_select Signed-off-by: Vandana Kannan Reviewed-by: Imre Deak Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index d2a8c640782f..d602db25eb33 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1340,18 +1340,17 @@ struct bxt_clk_div { uint32_t m2_frac; bool m2_frac_en; uint32_t n; - uint32_t lanestagger; }; /* pre-calculated values for DP linkrates */ static struct bxt_clk_div bxt_dp_clk_val[7] = { - /* 162 */ {4, 2, 32, 1677722, 1, 1, 0xd}, - /* 270 */ {4, 1, 27, 0, 0, 1, 0xd}, - /* 540 */ {2, 1, 27, 0, 0, 1, 0x18}, - /* 216 */ {3, 2, 32, 1677722, 1, 1, 0xd}, - /* 243 */ {4, 1, 24, 1258291, 1, 1, 0xd}, - /* 324 */ {4, 1, 32, 1677722, 1, 1, 0x18}, - /* 432 */ {3, 1, 32, 1677722, 1, 1, 0x18} + /* 162 */ {4, 2, 32, 1677722, 1, 1}, + /* 270 */ {4, 1, 27, 0, 0, 1}, + /* 540 */ {2, 1, 27, 0, 0, 1}, + /* 216 */ {3, 2, 32, 1677722, 1, 1}, + /* 243 */ {4, 1, 24, 1258291, 1, 1}, + /* 324 */ {4, 1, 32, 1677722, 1, 1}, + /* 432 */ {3, 1, 32, 1677722, 1, 1} }; static bool @@ -1364,7 +1363,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, struct bxt_clk_div clk_div = {0}; int vco = 0; uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; - uint32_t dcoampovr_en_h, dco_amp; + uint32_t dcoampovr_en_h, dco_amp, lanestagger; if (intel_encoder->type == INTEL_OUTPUT_HDMI) { intel_clock_t best_clock; @@ -1389,16 +1388,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, clk_div.m2_frac_en = clk_div.m2_frac != 0; vco = best_clock.vco; - if (clock > 270000) - clk_div.lanestagger = 0x18; - else if (clock > 135000) - clk_div.lanestagger = 0x0d; - else if (clock > 67000) - clk_div.lanestagger = 0x07; - else if (clock > 33000) - clk_div.lanestagger = 0x04; - else - clk_div.lanestagger = 0x02; } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || intel_encoder->type == INTEL_OUTPUT_EDP) { struct drm_encoder *encoder = &intel_encoder->base; @@ -1449,6 +1438,17 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state)); + if (clock > 270000) + lanestagger = 0x18; + else if (clock > 135000) + lanestagger = 0x0d; + else if (clock > 67000) + lanestagger = 0x07; + else if (clock > 33000) + lanestagger = 0x04; + else + lanestagger = 0x02; + crtc_state->dpll_hw_state.ebb0 = PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; @@ -1472,7 +1472,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); crtc_state->dpll_hw_state.pcsdw12 = - LANESTAGGER_STRAP_OVRD | clk_div.lanestagger; + LANESTAGGER_STRAP_OVRD | lanestagger; pll = intel_get_shared_dpll(intel_crtc, crtc_state); if (pll == NULL) { -- cgit v1.2.3 From c965d99557fd48e8c57d793ec22458e508cbf676 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Mon, 18 May 2015 19:53:48 +0100 Subject: drm/i915: Fix 'suspedn' typo Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 51149fb75e96..5cc57f2ec192 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -989,7 +989,7 @@ static int i915_pm_suspend_late(struct device *dev) struct drm_device *drm_dev = dev_to_i915(dev)->dev; /* - * We have a suspedn ordering issue with the snd-hda driver also + * We have a suspend ordering issue with the snd-hda driver also * requiring our device to be power up. Due to the lack of a * parent/child relationship we currently solve this with an late * suspend hook. -- cgit v1.2.3 From 6c0fd451bdde9a6d0ac408bd078351890228e465 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Tue, 19 May 2015 12:29:16 +0100 Subject: drm/i915: Tighten the exposure ARGB/ABGR 8888 formats MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ARGB8888 is used for cursors on all platforms so we need to allow it everywhere. ABGR8888 is currently only honoured: - on VLV/CHV in sprite planes - on SKL+ for primary and sprite planes so only allow it for those platforms. Note that we only support ARGB8888/ABGR8888 on the primary plane for SKL/BXT because we have in line of sight the pipe bottom color on those platforms and because the primary plane programming on VLV/CHV doesn't anything different for those formats today. v2: Fix the logic to forbid the creation ABGR2101010 fbs (Ville) v3: Still allow the creation of ARGB8888 fbs now that cursor planes use real fb objects (found by PRTS). Reviewed-by: Ville Syrjälä Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8a3d93639181..9d2d6fbbf3e3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -51,11 +51,19 @@ static const uint32_t i8xx_primary_formats[] = { DRM_FORMAT_RGB565, DRM_FORMAT_XRGB1555, DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, }; /* Primary plane formats for gen >= 4 */ static const uint32_t i965_primary_formats[] = { + DRM_FORMAT_C8, + DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_XRGB2101010, + DRM_FORMAT_XBGR2101010, +}; + +static const uint32_t skl_primary_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, @@ -2704,11 +2712,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, dspcntr |= DISPPLANE_BGRX565; break; case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_ARGB8888: dspcntr |= DISPPLANE_BGRX888; break; case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: dspcntr |= DISPPLANE_RGBX888; break; case DRM_FORMAT_XRGB2101010: @@ -2810,11 +2816,9 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, dspcntr |= DISPPLANE_BGRX565; break; case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_ARGB8888: dspcntr |= DISPPLANE_BGRX888; break; case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: dspcntr |= DISPPLANE_RGBX888; break; case DRM_FORMAT_XRGB2101010: @@ -13293,12 +13297,15 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) primary->plane = !pipe; - if (INTEL_INFO(dev)->gen <= 3) { - intel_primary_formats = i8xx_primary_formats; - num_formats = ARRAY_SIZE(i8xx_primary_formats); - } else { + if (INTEL_INFO(dev)->gen >= 9) { + intel_primary_formats = skl_primary_formats; + num_formats = ARRAY_SIZE(skl_primary_formats); + } else if (INTEL_INFO(dev)->gen >= 4) { intel_primary_formats = i965_primary_formats; num_formats = ARRAY_SIZE(i965_primary_formats); + } else { + intel_primary_formats = i8xx_primary_formats; + num_formats = ARRAY_SIZE(i8xx_primary_formats); } drm_universal_plane_init(dev, &primary->base, 0, @@ -13985,8 +13992,14 @@ static int intel_framebuffer_init(struct drm_device *dev, return -EINVAL; } break; - case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: + if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { + DRM_DEBUG("unsupported pixel format: %s\n", + drm_get_format_name(mode_cmd->pixel_format)); + return -EINVAL; + } + break; + case DRM_FORMAT_XBGR8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_XBGR2101010: if (INTEL_INFO(dev)->gen < 4) { -- cgit v1.2.3 From 5a2ae95e0b80d1769c24a0c7fbc7ae766cb706c1 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 19 May 2015 15:04:59 +0300 Subject: drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A Also make the WA comment consistent with the rest, where the stepping info is not shown. Signed-off-by: Imre Deak Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 9b96ed7de9bb..461b9befa776 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -961,12 +961,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, GEN9_CCS_TLB_PREFETCH_ENABLE); - /* - * FIXME: don't apply the following on BXT for stepping C. On BXT A0 - * the flag reads back as 0. - */ - /* WaDisableMaskBasedCammingInRCC:sklC,bxtA */ - if (INTEL_REVID(dev) == SKL_REVID_C0 || IS_BROXTON(dev)) + /* WaDisableMaskBasedCammingInRCC:skl,bxt */ + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || + (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, PIXEL_MASK_CAMMING_DISABLE); -- cgit v1.2.3 From b88baa2a4616bd8fcd6203b3bc1b8cd90e232cb0 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 19 May 2015 15:05:00 +0300 Subject: drm/i915/skl: add F0 stepping ID Signed-off-by: Imre Deak Reviewed-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 840f08fa5fb3..731b5cedf11d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2378,6 +2378,7 @@ struct drm_i915_cmd_table { #define SKL_REVID_C0 (0x2) #define SKL_REVID_D0 (0x3) #define SKL_REVID_E0 (0x4) +#define SKL_REVID_F0 (0x5) #define BXT_REVID_A0 (0x0) #define BXT_REVID_B0 (0x3) -- cgit v1.2.3 From 7546a38411fc3eb9e0ff1252718b0bf6579c87f6 Mon Sep 17 00:00:00 2001 From: Ander Conselvan de Oliveira Date: Wed, 20 May 2015 09:03:27 +0300 Subject: drm/i915: Update comment in clear_intel_crtc_state() Explain why a few fields of the new pipe_config have their values preserved, while the others are zeroed. Signed-off-by: Ander Conselvan de Oliveira Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9d2d6fbbf3e3..4a34709794f0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11485,7 +11485,11 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) enum intel_dpll_id shared_dpll; uint32_t ddi_pll_sel; - /* Clear only the intel specific part of the crtc state excluding scalers */ + /* FIXME: before the switch to atomic started, a new pipe_config was + * kzalloc'd. Code that depends on any field being zero should be + * fixed, so that the crtc_state can be safely duplicated. For now, + * only fields that are know to not cause problems are preserved. */ + tmp_state = crtc_state->base; scaler_state = crtc_state->scaler_state; shared_dpll = crtc_state->shared_dpll; -- cgit v1.2.3 From 1e8df16778b0d8fd8102b3ee799b028f8f961089 Mon Sep 17 00:00:00 2001 From: Sonika Jindal Date: Wed, 20 May 2015 13:40:48 +0530 Subject: drm/i915/skl: Swapping 90 and 270 to be compliant with Xrandr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since DRM_ROTATE is counter clockwise (which is compliant with Xrandr), and HW rotation is clockwise, swapping 90/270 to work as expected from userspace. v2: Rebased Suggested-by: Ville Syrjälä Cc: Ville Syrjälä Signed-off-by: Sonika Jindal Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4a34709794f0..c97b4963e5c1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3010,12 +3010,16 @@ u32 skl_plane_ctl_rotation(unsigned int rotation) switch (rotation) { case BIT(DRM_ROTATE_0): break; + /* + * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr + * while i915 HW rotation is clockwise, thats why this swapping. + */ case BIT(DRM_ROTATE_90): - return PLANE_CTL_ROTATE_90; + return PLANE_CTL_ROTATE_270; case BIT(DRM_ROTATE_180): return PLANE_CTL_ROTATE_180; case BIT(DRM_ROTATE_270): - return PLANE_CTL_ROTATE_270; + return PLANE_CTL_ROTATE_90; default: MISSING_CASE(rotation); } -- cgit v1.2.3 From a9a6b73a1c1191ef9e1339c61231144dd2cb1f2b Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Wed, 20 May 2015 14:45:14 +0100 Subject: drm/i915/bxt: Also add bxt_resume_prepare() to the S3/S4 path Currently bxt_resume_prepare() is only used in the runtime-resume path. Add it to the full S3/S4 path as well. v2: Rebase on top of the vlv_resume_prepare() shuffling around Cc: Imre Deak Reviewed-by: Imre Deak (v1) Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5cc57f2ec192..77f981822c67 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -595,6 +595,7 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv); static int vlv_resume_prepare(struct drm_i915_private *dev_priv, bool rpm_resume); static int skl_resume_prepare(struct drm_i915_private *dev_priv); +static int bxt_resume_prepare(struct drm_i915_private *dev_priv); static int i915_drm_suspend(struct drm_device *dev) @@ -815,10 +816,12 @@ static int i915_drm_resume_early(struct drm_device *dev) intel_uncore_early_sanitize(dev, true); - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - hsw_disable_pc8(dev_priv); + if (IS_BROXTON(dev)) + ret = bxt_resume_prepare(dev_priv); else if (IS_SKYLAKE(dev_priv)) ret = skl_resume_prepare(dev_priv); + else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) + hsw_disable_pc8(dev_priv); intel_uncore_sanitize(dev); intel_power_domains_init_hw(dev_priv); -- cgit v1.2.3 From ff0b187f92f61503c8af67d3dc5e6e91fbe2f9cc Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Wed, 20 May 2015 14:45:15 +0100 Subject: drm/i915: Add a space after ', ' and don't capitalize mid-sentence Couldn't let it go! Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 77f981822c67..442dd6c3d8d2 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -812,7 +812,8 @@ static int i915_drm_resume_early(struct drm_device *dev) if (IS_VALLEYVIEW(dev_priv)) ret = vlv_resume_prepare(dev_priv, false); if (ret) - DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret); + DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", + ret); intel_uncore_early_sanitize(dev, true); -- cgit v1.2.3 From 16e44e3e93c429b44a1441049ce89208fd3e0d28 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Wed, 20 May 2015 14:45:16 +0100 Subject: drm/i915: Kill the dev variable in intel_suspend_complete() The macros we use there are the magic ones that can take either dev or dev_priv. We'd like to move as much as possible towards dev_priv though. Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 442dd6c3d8d2..93191c1fd18e 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1590,16 +1590,15 @@ static int intel_runtime_resume(struct device *device) */ static int intel_suspend_complete(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; int ret; - if (IS_BROXTON(dev)) + if (IS_BROXTON(dev_priv)) ret = bxt_suspend_complete(dev_priv); - else if (IS_SKYLAKE(dev)) + else if (IS_SKYLAKE(dev_priv)) ret = skl_suspend_complete(dev_priv); - else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) + else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) ret = hsw_suspend_complete(dev_priv); - else if (IS_VALLEYVIEW(dev)) + else if (IS_VALLEYVIEW(dev_priv)) ret = vlv_suspend_complete(dev_priv); else ret = 0; -- cgit v1.2.3 From 5296b7f9d0e1ac31a9bc3044f04af18a521b9459 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 20 May 2015 20:51:41 +0100 Subject: drm/i2c: tda998x: fix compiler warning for ssize_t Stephen Rothwell reports that he sees a compiler warning on x86_64: drivers/gpu/drm/i2c/tda998x_drv.c: In function 'tda998x_write_avi': drivers/gpu/drm/i2c/tda998x_drv.c:647:3: warning: format '%d' expects argument of type 'int', but argument 3 has type 'ssize_t' [-Wformat=] dev_err(&priv->hdmi->dev, "hdmi_avi_infoframe_pack() failed: %d\n", len); ^ Fix this by using the appropriate length modifier. Signed-off-by: Russell King --- drivers/gpu/drm/i2c/tda998x_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c index fbc9c1facdfe..290a69d2315a 100644 --- a/drivers/gpu/drm/i2c/tda998x_drv.c +++ b/drivers/gpu/drm/i2c/tda998x_drv.c @@ -620,7 +620,8 @@ tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode) len = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf)); if (len < 0) { - dev_err(&priv->hdmi->dev, "hdmi_avi_infoframe_pack() failed: %d\n", len); + dev_err(&priv->hdmi->dev, + "hdmi_avi_infoframe_pack() failed: %zd\n", len); return; } -- cgit v1.2.3 From de28d0212a3ea7b92a9795cd0e5bfc7d15214677 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 19 May 2015 16:41:01 +0200 Subject: drm/atomic: add commit_planes_on_crtc helper drm_atomic_helper_commit_planes calls all atomic_begin's first, then updates all planes, finally calling atomic_flush. Some drivers may want to things like disabling irq's from their atomic_begin, in which case a second call to atomic_begin will splat. By using commit_planes_on_crtc on each crtc in the atomic state they'll evade that issue. Signed-off-by: Maarten Lankhorst [danvet: Extend kerneldoc a bit as discussed with Maarten on irc.] [danvet: Squash in fixup to check for crtc_funcs in all places. Reported by Dan Carpenter.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic_helper.c | 62 +++++++++++++++++++++++++++++++++++++ include/drm/drm_atomic_helper.h | 1 + 2 files changed, 63 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index b82ef6262469..424a98bfa686 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -1127,6 +1127,10 @@ EXPORT_SYMBOL(drm_atomic_helper_prepare_planes); * * It still requires the global state object @old_state to know which planes and * crtcs need to be updated though. + * + * Note that this function does all plane updates across all CRTCs in one step. + * If the hardware can't support this approach look at + * drm_atomic_helper_commit_planes_on_crtc() instead. */ void drm_atomic_helper_commit_planes(struct drm_device *dev, struct drm_atomic_state *old_state) @@ -1180,6 +1184,64 @@ void drm_atomic_helper_commit_planes(struct drm_device *dev, } EXPORT_SYMBOL(drm_atomic_helper_commit_planes); +/** + * drm_atomic_helper_commit_planes_on_crtc - commit plane state for a crtc + * @old_crtc_state: atomic state object with the old crtc state + * + * This function commits the new plane state using the plane and atomic helper + * functions for planes on the specific crtc. It assumes that the atomic state + * has already been pushed into the relevant object state pointers, since this + * step can no longer fail. + * + * This function is useful when plane updates should be done crtc-by-crtc + * instead of one global step like drm_atomic_helper_commit_planes() does. + * + * This function can only be savely used when planes are not allowed to move + * between different CRTCs because this function doesn't handle inter-CRTC + * depencies. Callers need to ensure that either no such depencies exist, + * resolve them through ordering of commit calls or through some other means. + */ +void +drm_atomic_helper_commit_planes_on_crtc(struct drm_crtc_state *old_crtc_state) +{ + const struct drm_crtc_helper_funcs *crtc_funcs; + struct drm_crtc *crtc = old_crtc_state->crtc; + struct drm_atomic_state *old_state = old_crtc_state->state; + struct drm_plane *plane; + unsigned plane_mask; + + plane_mask = old_crtc_state->plane_mask; + plane_mask |= crtc->state->plane_mask; + + crtc_funcs = crtc->helper_private; + if (crtc_funcs && crtc_funcs->atomic_begin) + crtc_funcs->atomic_begin(crtc); + + drm_for_each_plane_mask(plane, crtc->dev, plane_mask) { + struct drm_plane_state *old_plane_state = + drm_atomic_get_existing_plane_state(old_state, plane); + const struct drm_plane_helper_funcs *plane_funcs; + + plane_funcs = plane->helper_private; + + if (!old_plane_state || !plane_funcs) + continue; + + WARN_ON(plane->state->crtc && plane->state->crtc != crtc); + + if (drm_atomic_plane_disabling(plane, old_plane_state) && + plane_funcs->atomic_disable) + plane_funcs->atomic_disable(plane, old_plane_state); + else if (plane->state->crtc || + drm_atomic_plane_disabling(plane, old_plane_state)) + plane_funcs->atomic_update(plane, old_plane_state); + } + + if (crtc_funcs && crtc_funcs->atomic_flush) + crtc_funcs->atomic_flush(crtc); +} +EXPORT_SYMBOL(drm_atomic_helper_commit_planes_on_crtc); + /** * drm_atomic_helper_cleanup_planes - cleanup plane resources after commit * @dev: DRM device diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h index 6ee0ee5b6143..cc1fee8a12d0 100644 --- a/include/drm/drm_atomic_helper.h +++ b/include/drm/drm_atomic_helper.h @@ -58,6 +58,7 @@ void drm_atomic_helper_commit_planes(struct drm_device *dev, struct drm_atomic_state *state); void drm_atomic_helper_cleanup_planes(struct drm_device *dev, struct drm_atomic_state *old_state); +void drm_atomic_helper_commit_planes_on_crtc(struct drm_crtc_state *old_crtc_state); void drm_atomic_helper_swap_state(struct drm_device *dev, struct drm_atomic_state *state); -- cgit v1.2.3 From e01e9f75a0c4e6cdbf1f139e37e9161408e49b7c Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 19 May 2015 16:41:02 +0200 Subject: drm/atomic: add drm_atomic_add_affected_planes This is a convenience function to add all planes for a crtc, similar to add_affected_connectors. This will be used in drm_atomic_helper_check_modeset, but drivers can call it too when they need to recalculate all state. Signed-off-by: Maarten Lankhorst [danvet: Amend kerneldoc a bit.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic.c | 39 +++++++++++++++++++++++++++++++++++++++ include/drm/drm_atomic.h | 4 ++++ 2 files changed, 43 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index cd1b16b25716..3134f506b762 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -955,6 +955,45 @@ drm_atomic_add_affected_connectors(struct drm_atomic_state *state, } EXPORT_SYMBOL(drm_atomic_add_affected_connectors); +/** + * drm_atomic_add_affected_planes - add planes for crtc + * @state: atomic state + * @crtc: DRM crtc + * + * This function walks the current configuration and adds all planes + * currently used by @crtc to the atomic configuration @state. This is useful + * when an atomic commit also needs to check all currently enabled plane on + * @crtc, e.g. when changing the mode. It's also useful when re-enabling a CRTC + * to avoid special code to force-enable all planes. + * + * Since acquiring a plane state will always also acquire the w/w mutex of the + * current CRTC for that plane (if there is any) adding all the plane states for + * a CRTC will not reduce parallism of atomic updates. + * + * Returns: + * 0 on success or can fail with -EDEADLK or -ENOMEM. When the error is EDEADLK + * then the w/w mutex code has detected a deadlock and the entire atomic + * sequence must be restarted. All other errors are fatal. + */ +int +drm_atomic_add_affected_planes(struct drm_atomic_state *state, + struct drm_crtc *crtc) +{ + struct drm_plane *plane; + + WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc)); + + drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { + struct drm_plane_state *plane_state = + drm_atomic_get_plane_state(state, plane); + + if (IS_ERR(plane_state)) + return PTR_ERR(plane_state); + } + return 0; +} +EXPORT_SYMBOL(drm_atomic_add_affected_planes); + /** * drm_atomic_connectors_for_crtc - count number of connected outputs * @state: atomic state diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index f0d3a7387d99..e89db0c377ba 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -120,6 +120,10 @@ drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state, int __must_check drm_atomic_add_affected_connectors(struct drm_atomic_state *state, struct drm_crtc *crtc); +int __must_check +drm_atomic_add_affected_planes(struct drm_atomic_state *state, + struct drm_crtc *crtc); + int drm_atomic_connectors_for_crtc(struct drm_atomic_state *state, struct drm_crtc *crtc); -- cgit v1.2.3 From 57744aa7cfb5969c5a0621f4cfa45bb83d391064 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Tue, 19 May 2015 16:41:03 +0200 Subject: drm/atomic: add all affected planes in drm_atomic_helper_check_modeset Drivers may need to recalculate plane state when a modeset occurs, not reliably adding them might cause hard to debug bugs. Signed-off-by: Maarten Lankhorst Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic_helper.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 424a98bfa686..21259e70adee 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -429,6 +429,10 @@ drm_atomic_helper_check_modeset(struct drm_device *dev, if (ret != 0) return ret; + ret = drm_atomic_add_affected_planes(state, crtc); + if (ret != 0) + return ret; + num_connectors = drm_atomic_connectors_for_crtc(state, crtc); -- cgit v1.2.3 From 118182e9d7d5afa0c7c10f568afb46ab78b462e9 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 20 May 2015 14:12:47 +0100 Subject: drm/i915: Force clean compilation with -Werror Our driver compiles clean (nowadays thanks to 0day) but for me, at least, it would be beneficial if the compiler threw an error rather than a warning when it found a piece of suspect code. (I use this to compile-check patch series and want to break on the first compiler error in order to fix the patch.) v2: Kick off a new "Debugging" submenu for i915.ko Signed-off-by: Chris Wilson Acked-by: Jani Nikula [danvet: Add "DRM i915" to the menu name as requested by Chris.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/Kconfig | 8 ++++++++ drivers/gpu/drm/i915/Kconfig.debug | 5 +++++ drivers/gpu/drm/i915/Makefile | 2 ++ 3 files changed, 15 insertions(+) create mode 100644 drivers/gpu/drm/i915/Kconfig.debug (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 74acca9bcd9d..5e3aa87e8f48 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -71,3 +71,11 @@ config DRM_I915_PRELIMINARY_HW_SUPPORT option changes the default for that module option. If in doubt, say "N". + +menu "DRM i915 Debugging" + +depends on DRM_I915 + +source drivers/gpu/drm/i915/Kconfig.debug + +endmenu diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug new file mode 100644 index 000000000000..070a03527bc5 --- /dev/null +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -0,0 +1,5 @@ +config DRM_I915_WERROR + bool "Force GCC to throw an error instead of a warning when compiling" + default n + ---help--- + Add -Werror to the build flags for (and only for) i915.ko diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index b7ddf48e1d75..93d99b744531 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -2,6 +2,8 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. +subdir-ccflags-$(CONFIG_DRM_I915_WERROR) := -Werror + # Please keep these build lists sorted! # core driver code -- cgit v1.2.3 From 862e686ce40299250d21ba425ea5078e947397ff Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Thu, 21 May 2015 11:03:16 +0530 Subject: drm: bridge: Allow daisy chaining of bridges Allow drm_bridge objects to link to each other in order to form an encoder chain. The requirement for creating a chain of bridges comes because the MSM drm driver uses up its encoder and bridge objects for blocks within the SoC itself. There isn't anything left to use if the SoC display output is connected to an external encoder IC. Having an additional bridge connected to the existing bridge helps here. In general, it is possible for platforms to have multiple devices between the encoder and the connector/panel that require some sort of configuration. We create drm bridge helper functions corresponding to each op in 'drm_bridge_funcs'. These helpers call the corresponding 'drm_bridge_funcs' op for the entire chain of bridges. These helpers are used internally by drm_atomic_helper.c and drm_crtc_helper.c. The drm_bridge_enable/pre_enable helpers execute enable/pre_enable ops of the bridge closet to the encoder, and proceed until the last bridge in the chain is enabled. The same holds for drm_bridge_mode_set/mode_fixup helpers. The drm_bridge_disable/post_disable helpers disable the last bridge in the chain first, and proceed until the first bridge in the chain is disabled. drm_bridge_attach() remains the same. As before, the driver calling this function should make sure it has set the links correctly. The order in which the bridges are connected to each other determines the order in which the calls are made. One requirement is that every bridge in the chain should point the parent encoder object. This is required since bridge drivers expect a valid encoder pointer in drm_bridge. For example, consider a chain where an encoder's output is connected to bridge1, and bridge1's output is connected to bridge2: /* Like before, attach bridge to an encoder */ bridge1->encoder = encoder; ret = drm_bridge_attach(dev, bridge1); .. /* * set the first bridge's 'next' bridge to bridge2, set its encoder * as bridge1's encoder */ bridge1->next = bridge2 bridge2->encoder = bridge1->encoder; ret = drm_bridge_attach(dev, bridge2); ... ... This method of bridge chaining isn't intrusive and existing drivers that use drm_bridge will behave the same way as before. The bridge helpers also cleans up the atomic and crtc helper files a bit. Reviewed-by: Jani Nikula Reviewed-by: Rob Clark Reviewed-by: Daniel Vetter Signed-off-by: Archit Taneja Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic_helper.c | 29 +++---- drivers/gpu/drm/drm_bridge.c | 147 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/drm_crtc_helper.c | 54 +++++-------- include/drm/drm_crtc.h | 14 ++++ 4 files changed, 191 insertions(+), 53 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 21259e70adee..a64bacdcf263 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -283,14 +283,11 @@ mode_fixup(struct drm_atomic_state *state) if (!funcs) continue; - if (encoder->bridge && encoder->bridge->funcs->mode_fixup) { - ret = encoder->bridge->funcs->mode_fixup( - encoder->bridge, &crtc_state->mode, - &crtc_state->adjusted_mode); - if (!ret) { - DRM_DEBUG_ATOMIC("Bridge fixup failed\n"); - return -EINVAL; - } + ret = drm_bridge_mode_fixup(encoder->bridge, &crtc_state->mode, + &crtc_state->adjusted_mode); + if (!ret) { + DRM_DEBUG_ATOMIC("Bridge fixup failed\n"); + return -EINVAL; } if (funcs->atomic_check) { @@ -587,8 +584,7 @@ disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state) * Each encoder has at most one connector (since we always steal * it away), so we won't call disable hooks twice. */ - if (encoder->bridge) - encoder->bridge->funcs->disable(encoder->bridge); + drm_bridge_disable(encoder->bridge); /* Right function depends upon target state. */ if (connector->state->crtc && funcs->prepare) @@ -598,8 +594,7 @@ disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state) else funcs->dpms(encoder, DRM_MODE_DPMS_OFF); - if (encoder->bridge) - encoder->bridge->funcs->post_disable(encoder->bridge); + drm_bridge_post_disable(encoder->bridge); } for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { @@ -741,9 +736,7 @@ crtc_set_mode(struct drm_device *dev, struct drm_atomic_state *old_state) if (funcs->mode_set) funcs->mode_set(encoder, mode, adjusted_mode); - if (encoder->bridge && encoder->bridge->funcs->mode_set) - encoder->bridge->funcs->mode_set(encoder->bridge, - mode, adjusted_mode); + drm_bridge_mode_set(encoder->bridge, mode, adjusted_mode); } } @@ -839,16 +832,14 @@ void drm_atomic_helper_commit_modeset_enables(struct drm_device *dev, * Each encoder has at most one connector (since we always steal * it away), so we won't call enable hooks twice. */ - if (encoder->bridge) - encoder->bridge->funcs->pre_enable(encoder->bridge); + drm_bridge_pre_enable(encoder->bridge); if (funcs->enable) funcs->enable(encoder); else funcs->commit(encoder); - if (encoder->bridge) - encoder->bridge->funcs->enable(encoder->bridge); + drm_bridge_enable(encoder->bridge); } } EXPORT_SYMBOL(drm_atomic_helper_commit_modeset_enables); diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index eaa5790c2a6f..c3a85ce5a7c4 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -66,6 +66,153 @@ int drm_bridge_attach(struct drm_device *dev, struct drm_bridge *bridge) } EXPORT_SYMBOL(drm_bridge_attach); +/** + * drm_bridge_mode_fixup - fixup proposed mode for all bridges in the + * encoder chain + * @bridge: bridge control structure + * @mode: desired mode to be set for the bridge + * @adjusted_mode: updated mode that works for this bridge + * + * Calls 'mode_fixup' drm_bridge_funcs op for all the bridges in the + * encoder chain, starting from the first bridge to the last. + * + * Note: the bridge passed should be the one closest to the encoder + * + * RETURNS: + * true on success, false on failure + */ +bool drm_bridge_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + bool ret = true; + + if (!bridge) + return true; + + if (bridge->funcs->mode_fixup) + ret = bridge->funcs->mode_fixup(bridge, mode, adjusted_mode); + + ret = ret && drm_bridge_mode_fixup(bridge->next, mode, adjusted_mode); + + return ret; +} +EXPORT_SYMBOL(drm_bridge_mode_fixup); + +/** + * drm_bridge_disable - calls 'disable' drm_bridge_funcs op for all + * bridges in the encoder chain. + * @bridge: bridge control structure + * + * Calls 'disable' drm_bridge_funcs op for all the bridges in the encoder + * chain, starting from the last bridge to the first. These are called before + * calling the encoder's prepare op. + * + * Note: the bridge passed should be the one closest to the encoder + */ +void drm_bridge_disable(struct drm_bridge *bridge) +{ + if (!bridge) + return; + + drm_bridge_disable(bridge->next); + + bridge->funcs->disable(bridge); +} +EXPORT_SYMBOL(drm_bridge_disable); + +/** + * drm_bridge_post_disable - calls 'post_disable' drm_bridge_funcs op for + * all bridges in the encoder chain. + * @bridge: bridge control structure + * + * Calls 'post_disable' drm_bridge_funcs op for all the bridges in the + * encoder chain, starting from the first bridge to the last. These are called + * after completing the encoder's prepare op. + * + * Note: the bridge passed should be the one closest to the encoder + */ +void drm_bridge_post_disable(struct drm_bridge *bridge) +{ + if (!bridge) + return; + + bridge->funcs->post_disable(bridge); + + drm_bridge_post_disable(bridge->next); +} +EXPORT_SYMBOL(drm_bridge_post_disable); + +/** + * drm_bridge_mode_set - set proposed mode for all bridges in the + * encoder chain + * @bridge: bridge control structure + * @mode: desired mode to be set for the bridge + * @adjusted_mode: updated mode that works for this bridge + * + * Calls 'mode_set' drm_bridge_funcs op for all the bridges in the + * encoder chain, starting from the first bridge to the last. + * + * Note: the bridge passed should be the one closest to the encoder + */ +void drm_bridge_mode_set(struct drm_bridge *bridge, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + if (!bridge) + return; + + if (bridge->funcs->mode_set) + bridge->funcs->mode_set(bridge, mode, adjusted_mode); + + drm_bridge_mode_set(bridge->next, mode, adjusted_mode); +} +EXPORT_SYMBOL(drm_bridge_mode_set); + +/** + * drm_bridge_pre_enable - calls 'pre_enable' drm_bridge_funcs op for all + * bridges in the encoder chain. + * @bridge: bridge control structure + * + * Calls 'pre_enable' drm_bridge_funcs op for all the bridges in the encoder + * chain, starting from the last bridge to the first. These are called + * before calling the encoder's commit op. + * + * Note: the bridge passed should be the one closest to the encoder + */ +void drm_bridge_pre_enable(struct drm_bridge *bridge) +{ + if (!bridge) + return; + + drm_bridge_pre_enable(bridge->next); + + bridge->funcs->pre_enable(bridge); +} +EXPORT_SYMBOL(drm_bridge_pre_enable); + +/** + * drm_bridge_enable - calls 'enable' drm_bridge_funcs op for all bridges + * in the encoder chain. + * @bridge: bridge control structure + * + * Calls 'enable' drm_bridge_funcs op for all the bridges in the encoder + * chain, starting from the first bridge to the last. These are called + * after completing the encoder's commit op. + * + * Note that the bridge passed should be the one closest to the encoder + */ +void drm_bridge_enable(struct drm_bridge *bridge) +{ + if (!bridge) + return; + + bridge->funcs->enable(bridge); + + drm_bridge_enable(bridge->next); +} +EXPORT_SYMBOL(drm_bridge_enable); + #ifdef CONFIG_OF struct drm_bridge *of_drm_find_bridge(struct device_node *np) { diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index d727b73fba3a..f2f42b17967a 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -163,16 +163,14 @@ drm_encoder_disable(struct drm_encoder *encoder) { const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; - if (encoder->bridge) - encoder->bridge->funcs->disable(encoder->bridge); + drm_bridge_disable(encoder->bridge); if (encoder_funcs->disable) (*encoder_funcs->disable)(encoder); else (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF); - if (encoder->bridge) - encoder->bridge->funcs->post_disable(encoder->bridge); + drm_bridge_post_disable(encoder->bridge); } static void __drm_helper_disable_unused_functions(struct drm_device *dev) @@ -312,13 +310,11 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, if (encoder->crtc != crtc) continue; - if (encoder->bridge && encoder->bridge->funcs->mode_fixup) { - ret = encoder->bridge->funcs->mode_fixup( - encoder->bridge, mode, adjusted_mode); - if (!ret) { - DRM_DEBUG_KMS("Bridge fixup failed\n"); - goto done; - } + ret = drm_bridge_mode_fixup(encoder->bridge, + mode, adjusted_mode); + if (!ret) { + DRM_DEBUG_KMS("Bridge fixup failed\n"); + goto done; } encoder_funcs = encoder->helper_private; @@ -343,15 +339,13 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, if (encoder->crtc != crtc) continue; - if (encoder->bridge) - encoder->bridge->funcs->disable(encoder->bridge); + drm_bridge_disable(encoder->bridge); encoder_funcs = encoder->helper_private; /* Disable the encoders as the first thing we do. */ encoder_funcs->prepare(encoder); - if (encoder->bridge) - encoder->bridge->funcs->post_disable(encoder->bridge); + drm_bridge_post_disable(encoder->bridge); } drm_crtc_prepare_encoders(dev); @@ -376,9 +370,7 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, encoder_funcs = encoder->helper_private; encoder_funcs->mode_set(encoder, mode, adjusted_mode); - if (encoder->bridge && encoder->bridge->funcs->mode_set) - encoder->bridge->funcs->mode_set(encoder->bridge, mode, - adjusted_mode); + drm_bridge_mode_set(encoder->bridge, mode, adjusted_mode); } /* Now enable the clocks, plane, pipe, and connectors that we set up. */ @@ -389,14 +381,12 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, if (encoder->crtc != crtc) continue; - if (encoder->bridge) - encoder->bridge->funcs->pre_enable(encoder->bridge); + drm_bridge_pre_enable(encoder->bridge); encoder_funcs = encoder->helper_private; encoder_funcs->commit(encoder); - if (encoder->bridge) - encoder->bridge->funcs->enable(encoder->bridge); + drm_bridge_enable(encoder->bridge); } /* Calculate and store various constants which @@ -735,23 +725,19 @@ static void drm_helper_encoder_dpms(struct drm_encoder *encoder, int mode) struct drm_bridge *bridge = encoder->bridge; const struct drm_encoder_helper_funcs *encoder_funcs; - if (bridge) { - if (mode == DRM_MODE_DPMS_ON) - bridge->funcs->pre_enable(bridge); - else - bridge->funcs->disable(bridge); - } + if (mode == DRM_MODE_DPMS_ON) + drm_bridge_pre_enable(bridge); + else + drm_bridge_disable(bridge); encoder_funcs = encoder->helper_private; if (encoder_funcs->dpms) encoder_funcs->dpms(encoder, mode); - if (bridge) { - if (mode == DRM_MODE_DPMS_ON) - bridge->funcs->enable(bridge); - else - bridge->funcs->post_disable(bridge); - } + if (mode == DRM_MODE_DPMS_ON) + drm_bridge_enable(bridge); + else + drm_bridge_post_disable(bridge); } static int drm_helper_choose_crtc_dpms(struct drm_crtc *crtc) diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index bff25b0cada9..dace1b635685 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -903,6 +903,8 @@ struct drm_bridge_funcs { /** * struct drm_bridge - central DRM bridge control structure * @dev: DRM device this bridge belongs to + * @encoder: encoder to which this bridge is connected + * @next: the next bridge in the encoder chain * @of_node: device node pointer to the bridge * @list: to keep track of all added bridges * @base: base mode object @@ -912,6 +914,7 @@ struct drm_bridge_funcs { struct drm_bridge { struct drm_device *dev; struct drm_encoder *encoder; + struct drm_bridge *next; #ifdef CONFIG_OF struct device_node *of_node; #endif @@ -1247,6 +1250,17 @@ extern void drm_bridge_remove(struct drm_bridge *bridge); extern struct drm_bridge *of_drm_find_bridge(struct device_node *np); extern int drm_bridge_attach(struct drm_device *dev, struct drm_bridge *bridge); +bool drm_bridge_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); +void drm_bridge_disable(struct drm_bridge *bridge); +void drm_bridge_post_disable(struct drm_bridge *bridge); +void drm_bridge_mode_set(struct drm_bridge *bridge, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); +void drm_bridge_pre_enable(struct drm_bridge *bridge); +void drm_bridge_enable(struct drm_bridge *bridge); + extern int drm_encoder_init(struct drm_device *dev, struct drm_encoder *encoder, const struct drm_encoder_funcs *funcs, -- cgit v1.2.3 From 2331b4e476e0dc705825c8f5462fa1274b6d3b97 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Thu, 21 May 2015 11:03:17 +0530 Subject: drm/DocBook: Add more drm_bridge documentation Add DOC sections giving an overview of drm_bridge and how to fill up the drm_bridge_funcs ops. Add these to drm.tpml in DocBook. Add headerdocs for funcs in drm_bridge.c that don't have them yet. Signed-off-by: Archit Taneja [danvet: Amend kerneldoc as discussed with Archit.] Signed-off-by: Daniel Vetter --- Documentation/DocBook/drm.tmpl | 12 ++++++ drivers/gpu/drm/drm_bridge.c | 95 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 107 insertions(+) (limited to 'drivers') diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 7c68ecc800a1..5d9d851d8623 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -2439,6 +2439,18 @@ void intel_crt_init(struct drm_device *dev) Tile group !Pdrivers/gpu/drm/drm_crtc.c Tile group + + Bridges + + Overview +!Pdrivers/gpu/drm/drm_bridge.c overview + + + Default bridge callback sequence +!Pdrivers/gpu/drm/drm_bridge.c bridge callbacks + +!Edrivers/gpu/drm/drm_bridge.c + diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index c3a85ce5a7c4..6b8f7211e543 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -28,9 +28,42 @@ #include "drm/drmP.h" +/** + * DOC: overview + * + * drm_bridge represents a device that hangs on to an encoder. These are handy + * when a regular drm_encoder entity isn't enough to represent the entire + * encoder chain. + * + * A bridge is always associated to a single drm_encoder at a time, but can be + * either connected to it directly, or through an intermediate bridge: + * + * encoder ---> bridge B ---> bridge A + * + * Here, the output of the encoder feeds to bridge B, and that furthers feeds to + * bridge A. + * + * The driver using the bridge is responsible to make the associations between + * the encoder and bridges. Once these links are made, the bridges will + * participate along with encoder functions to perform mode_set/enable/disable + * through the ops provided in drm_bridge_funcs. + * + * drm_bridge, like drm_panel, aren't drm_mode_object entities like planes, + * crtcs, encoders or connectors. They just provide additional hooks to get the + * desired output at the end of the encoder chain. + */ + static DEFINE_MUTEX(bridge_lock); static LIST_HEAD(bridge_list); +/** + * drm_bridge_add - add the given bridge to the global bridge list + * + * @bridge: bridge control structure + * + * RETURNS: + * Unconditionally returns Zero. + */ int drm_bridge_add(struct drm_bridge *bridge) { mutex_lock(&bridge_lock); @@ -41,6 +74,11 @@ int drm_bridge_add(struct drm_bridge *bridge) } EXPORT_SYMBOL(drm_bridge_add); +/** + * drm_bridge_remove - remove the given bridge from the global bridge list + * + * @bridge: bridge control structure + */ void drm_bridge_remove(struct drm_bridge *bridge) { mutex_lock(&bridge_lock); @@ -49,6 +87,21 @@ void drm_bridge_remove(struct drm_bridge *bridge) } EXPORT_SYMBOL(drm_bridge_remove); +/** + * drm_bridge_attach - associate given bridge to our DRM device + * + * @dev: DRM device + * @bridge: bridge control structure + * + * called by a kms driver to link one of our encoder/bridge to the given + * bridge. + * + * Note that setting up links between the bridge and our encoder/bridge + * objects needs to be handled by the kms driver itself + * + * RETURNS: + * Zero on success, error code on failure + */ int drm_bridge_attach(struct drm_device *dev, struct drm_bridge *bridge) { if (!dev || !bridge) @@ -66,6 +119,39 @@ int drm_bridge_attach(struct drm_device *dev, struct drm_bridge *bridge) } EXPORT_SYMBOL(drm_bridge_attach); +/** + * DOC: bridge callbacks + * + * The drm_bridge_funcs ops are populated by the bridge driver. The drm + * internals(atomic and crtc helpers) use the helpers defined in drm_bridge.c + * These helpers call a specific drm_bridge_funcs op for all the bridges + * during encoder configuration. + * + * When creating a bridge driver, one can implement drm_bridge_funcs op with + * the help of these rough rules: + * + * pre_enable: this contains things needed to be done for the bridge before + * its clock and timings are enabled by its source. For a bridge, its source + * is generally the encoder or bridge just before it in the encoder chain. + * + * enable: this contains things needed to be done for the bridge once its + * source is enabled. In other words, enable is called once the source is + * ready with clock and timing needed by the bridge. + * + * disable: this contains things needed to be done for the bridge assuming + * that its source is still enabled, i.e. clock and timings are still on. + * + * post_disable: this contains things needed to be done for the bridge once + * its source is disabled, i.e. once clocks and timings are off. + * + * mode_fixup: this should fixup the given mode for the bridge. It is called + * after the encoder's mode fixup. mode_fixup can also reject a mode completely + * if it's unsuitable for the hardware. + * + * mode_set: this sets up the mode for the bridge. It assumes that its source + * (an encoder or a bridge) has set the mode too. + */ + /** * drm_bridge_mode_fixup - fixup proposed mode for all bridges in the * encoder chain @@ -214,6 +300,15 @@ void drm_bridge_enable(struct drm_bridge *bridge) EXPORT_SYMBOL(drm_bridge_enable); #ifdef CONFIG_OF +/** + * of_drm_find_bridge - find the bridge corresponding to the device node in + * the global bridge list + * + * @np: device node + * + * RETURNS: + * drm_bridge control struct on success, NULL on failure + */ struct drm_bridge *of_drm_find_bridge(struct device_node *np) { struct drm_bridge *bridge; -- cgit v1.2.3 From 2a0ee94fef9aa87f23070693764175982700f0f5 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 19 May 2015 17:05:41 +0300 Subject: drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+ On B0 and C0 steppings the workaround enable bit would be overriden by default, so the overriding must be disabled. The WA was added in commit 83a24979c40ebbf0fa0cd14df16f74142f373cd3 Author: Nick Hoath Date: Fri Apr 10 13:12:26 2015 +0100 drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent Spotted-by: Mika Kuoppala Signed-off-by: Imre Deak Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++-- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 04b9f2b4c042..3f94f38eec1f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5791,6 +5791,7 @@ enum skl_disp_power_wells { /* GEN8 chicken */ #define HDC_CHICKEN0 0x7300 +#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 461b9befa776..a071b1062e30 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1043,6 +1043,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t tmp; gen9_init_workarounds(ring); @@ -1058,8 +1059,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) } /* WaForceContextSaveRestoreNonCoherent:bxt */ - WA_SET_BIT_MASKED(HDC_CHICKEN0, - HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); + tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; + if (INTEL_REVID(dev) >= BXT_REVID_B0) + tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; + WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); return 0; } -- cgit v1.2.3 From 8ea6f8926b367725f0c13ff82f251074de9d95b4 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 19 May 2015 17:05:42 +0300 Subject: drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent v2: - set the override disable flag too on stepping F0 (mika) Signed-off-by: Imre Deak Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a071b1062e30..6ab5765c3061 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -918,6 +918,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t tmp; /* WaDisablePartialInstShootdown:skl,bxt */ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, @@ -967,6 +968,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, PIXEL_MASK_CAMMING_DISABLE); + /* WaForceContextSaveRestoreNonCoherent:skl,bxt */ + tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) || + (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0)) + tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; + WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); + return 0; } @@ -1043,7 +1051,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; struct drm_i915_private *dev_priv = dev->dev_private; - uint32_t tmp; gen9_init_workarounds(ring); @@ -1058,12 +1065,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); } - /* WaForceContextSaveRestoreNonCoherent:bxt */ - tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; - if (INTEL_REVID(dev) >= BXT_REVID_B0) - tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; - WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); - return 0; } -- cgit v1.2.3 From eed29a5b21557476bbd8b141946a8dfe5aacc4f3 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 21 May 2015 14:21:25 +0200 Subject: drm/i915: s/\/req/g The merged seqno->request conversion from John called request variables req, but some (not all) of Chris' recent patches changed those to just rq. We've had a lenghty (and inconclusive) discussion on irc which is the more meaningful name with maybe at most a slight bias towards req. Given that the "don't change names without good reason to avoid conflicts" rule applies, so lets go back to a req everywhere for consistency. I'll sed any patches for which this will cause conflicts before applying. Cc: Chris Wilson Cc: John Harrison [danvet: s/origina/merged/ as pointed out by Chris - the first mass-conversion patch was from Chris, the merged one from John.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++++------- drivers/gpu/drm/i915/i915_gem.c | 32 ++++++++++++++++---------------- drivers/gpu/drm/i915/intel_display.c | 8 ++++---- drivers/gpu/drm/i915/intel_drv.h | 4 ++-- drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++-------- 5 files changed, 37 insertions(+), 37 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index a32b669bab89..f465af1b02f8 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -665,7 +665,7 @@ static int i915_gem_request_info(struct seq_file *m, void *data) struct drm_device *dev = node->minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_engine_cs *ring; - struct drm_i915_gem_request *rq; + struct drm_i915_gem_request *req; int ret, any, i; ret = mutex_lock_interruptible(&dev->struct_mutex); @@ -677,22 +677,22 @@ static int i915_gem_request_info(struct seq_file *m, void *data) int count; count = 0; - list_for_each_entry(rq, &ring->request_list, list) + list_for_each_entry(req, &ring->request_list, list) count++; if (count == 0) continue; seq_printf(m, "%s requests: %d\n", ring->name, count); - list_for_each_entry(rq, &ring->request_list, list) { + list_for_each_entry(req, &ring->request_list, list) { struct task_struct *task; rcu_read_lock(); task = NULL; - if (rq->pid) - task = pid_task(rq->pid, PIDTYPE_PID); + if (req->pid) + task = pid_task(req->pid, PIDTYPE_PID); seq_printf(m, " %x @ %d: %s [%d]\n", - rq->seqno, - (int) (jiffies - rq->emitted_jiffies), + req->seqno, + (int) (jiffies - req->emitted_jiffies), task ? task->comm : "", task ? task->pid : -1); rcu_read_unlock(); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 5ff96f94c2ee..fa4429144cb9 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1178,16 +1178,16 @@ static bool missed_irq(struct drm_i915_private *dev_priv, return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); } -static int __i915_spin_request(struct drm_i915_gem_request *rq) +static int __i915_spin_request(struct drm_i915_gem_request *req) { unsigned long timeout; - if (i915_gem_request_get_ring(rq)->irq_refcount) + if (i915_gem_request_get_ring(req)->irq_refcount) return -EBUSY; timeout = jiffies + 1; while (!need_resched()) { - if (i915_gem_request_completed(rq, true)) + if (i915_gem_request_completed(req, true)) return 0; if (time_after_eq(jiffies, timeout)) @@ -1195,7 +1195,7 @@ static int __i915_spin_request(struct drm_i915_gem_request *rq) cpu_relax_lowlatency(); } - if (i915_gem_request_completed(rq, false)) + if (i915_gem_request_completed(req, false)) return 0; return -EAGAIN; @@ -2572,37 +2572,37 @@ int i915_gem_request_alloc(struct intel_engine_cs *ring, struct intel_context *ctx) { struct drm_i915_private *dev_priv = to_i915(ring->dev); - struct drm_i915_gem_request *rq; + struct drm_i915_gem_request *req; int ret; if (ring->outstanding_lazy_request) return 0; - rq = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); - if (rq == NULL) + req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); + if (req == NULL) return -ENOMEM; - kref_init(&rq->ref); - rq->i915 = dev_priv; + kref_init(&req->ref); + req->i915 = dev_priv; - ret = i915_gem_get_seqno(ring->dev, &rq->seqno); + ret = i915_gem_get_seqno(ring->dev, &req->seqno); if (ret) { - kfree(rq); + kfree(req); return ret; } - rq->ring = ring; + req->ring = ring; if (i915.enable_execlists) - ret = intel_logical_ring_alloc_request_extras(rq, ctx); + ret = intel_logical_ring_alloc_request_extras(req, ctx); else - ret = intel_ring_alloc_request_extras(rq); + ret = intel_ring_alloc_request_extras(req); if (ret) { - kfree(rq); + kfree(req); return ret; } - ring->outstanding_lazy_request = rq; + ring->outstanding_lazy_request = req; return 0; } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c97b4963e5c1..7ef22db8cbbf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10785,14 +10785,14 @@ static void intel_mmio_flip_work_func(struct work_struct *work) struct intel_mmio_flip *mmio_flip = container_of(work, struct intel_mmio_flip, work); - if (mmio_flip->rq) - WARN_ON(__i915_wait_request(mmio_flip->rq, + if (mmio_flip->req) + WARN_ON(__i915_wait_request(mmio_flip->req, mmio_flip->crtc->reset_counter, false, NULL, NULL)); intel_do_mmio_flip(mmio_flip->crtc); - i915_gem_request_unreference__unlocked(mmio_flip->rq); + i915_gem_request_unreference__unlocked(mmio_flip->req); kfree(mmio_flip); } @@ -10809,7 +10809,7 @@ static int intel_queue_mmio_flip(struct drm_device *dev, if (mmio_flip == NULL) return -ENOMEM; - mmio_flip->rq = i915_gem_request_reference(obj->last_write_req); + mmio_flip->req = i915_gem_request_reference(obj->last_write_req); mmio_flip->crtc = to_intel_crtc(crtc); INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 47bc729043c5..c3c42ead4b46 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -460,7 +460,7 @@ struct intel_pipe_wm { struct intel_mmio_flip { struct work_struct work; - struct drm_i915_gem_request *rq; + struct drm_i915_gem_request *req; struct intel_crtc *crtc; }; @@ -1366,7 +1366,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv); void gen6_rps_boost(struct drm_i915_private *dev_priv, struct drm_i915_file_private *file_priv); void intel_queue_rps_boost_for_request(struct drm_device *dev, - struct drm_i915_gem_request *rq); + struct drm_i915_gem_request *req); void ilk_wm_get_hw_state(struct drm_device *dev); void skl_wm_get_hw_state(struct drm_device *dev); void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a70b2d1fc844..5dda008698a2 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6842,34 +6842,34 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) struct request_boost { struct work_struct work; - struct drm_i915_gem_request *rq; + struct drm_i915_gem_request *req; }; static void __intel_rps_boost_work(struct work_struct *work) { struct request_boost *boost = container_of(work, struct request_boost, work); - if (!i915_gem_request_completed(boost->rq, true)) - gen6_rps_boost(to_i915(boost->rq->ring->dev), NULL); + if (!i915_gem_request_completed(boost->req, true)) + gen6_rps_boost(to_i915(boost->req->ring->dev), NULL); - i915_gem_request_unreference__unlocked(boost->rq); + i915_gem_request_unreference__unlocked(boost->req); kfree(boost); } void intel_queue_rps_boost_for_request(struct drm_device *dev, - struct drm_i915_gem_request *rq) + struct drm_i915_gem_request *req) { struct request_boost *boost; - if (rq == NULL || INTEL_INFO(dev)->gen < 6) + if (req == NULL || INTEL_INFO(dev)->gen < 6) return; boost = kmalloc(sizeof(*boost), GFP_ATOMIC); if (boost == NULL) return; - i915_gem_request_reference(rq); - boost->rq = rq; + i915_gem_request_reference(req); + boost->req = req; INIT_WORK(&boost->work, __intel_rps_boost_work); queue_work(to_i915(dev)->wq, &boost->work); -- cgit v1.2.3 From b47161858ba13c9c7e03333132230d66e008dd55 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 13:41:17 +0100 Subject: drm/i915: Implement inter-engine read-read optimisations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, we only track the last request globally across all engines. This prevents us from issuing concurrent read requests on e.g. the RCS and BCS engines (or more likely the render and media engines). Without semaphores, we incur costly stalls as we synchronise between rings - greatly impacting the current performance of Broadwell versus Haswell in certain workloads (like video decode). With the introduction of reference counted requests, it is much easier to track the last request per ring, as well as the last global write request so that we can optimise inter-engine read read requests (as well as better optimise certain CPU waits). v2: Fix inverted readonly condition for nonblocking waits. v3: Handle non-continguous engine array after waits v4: Rebase, tidy, rewrite ring list debugging v5: Use obj->active as a bitfield, it looks cool v6: Micro-optimise, mostly involving moving code around v7: Fix retire-requests-upto for execlists (and multiple rq->ringbuf) v8: Rebase v9: Refactor i915_gem_object_sync() to allow the compiler to better optimise it. Benchmark: igt/gem_read_read_speed hsw:gt3e (with semaphores): Before: Time to read-read 1024k: 275.794µs After: Time to read-read 1024k: 123.260µs hsw:gt3e (w/o semaphores): Before: Time to read-read 1024k: 230.433µs After: Time to read-read 1024k: 124.593µs bdw-u (w/o semaphores): Before After Time to read-read 1x1: 26.274µs 10.350µs Time to read-read 128x128: 40.097µs 21.366µs Time to read-read 256x256: 77.087µs 42.608µs Time to read-read 512x512: 281.999µs 181.155µs Time to read-read 1024x1024: 1196.141µs 1118.223µs Time to read-read 2048x2048: 5639.072µs 5225.837µs Time to read-read 4096x4096: 22401.662µs 21137.067µs Time to read-read 8192x8192: 89617.735µs 85637.681µs Testcase: igt/gem_concurrent_blit (read-read and friends) Cc: Lionel Landwerlin Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Reviewed-by: Tvrtko Ursulin [v8] [danvet: s/\/req/g] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 16 +- drivers/gpu/drm/i915/i915_drv.h | 19 +- drivers/gpu/drm/i915/i915_gem.c | 540 ++++++++++++++++++++------------ drivers/gpu/drm/i915/i915_gem_context.c | 2 - drivers/gpu/drm/i915/i915_gem_debug.c | 92 ++---- drivers/gpu/drm/i915/i915_gpu_error.c | 19 +- drivers/gpu/drm/i915/intel_display.c | 6 +- drivers/gpu/drm/i915/intel_lrc.c | 19 +- drivers/gpu/drm/i915/intel_overlay.c | 2 - drivers/gpu/drm/i915/intel_ringbuffer.c | 26 +- 10 files changed, 416 insertions(+), 325 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f465af1b02f8..5fceb9400a91 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -120,10 +120,13 @@ static inline const char *get_global_flag(struct drm_i915_gem_object *obj) static void describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) { + struct drm_i915_private *dev_priv = to_i915(obj->base.dev); + struct intel_engine_cs *ring; struct i915_vma *vma; int pin_count = 0; + int i; - seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s", + seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ", &obj->base, obj->active ? "*" : " ", get_pin_flag(obj), @@ -131,8 +134,11 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) get_global_flag(obj), obj->base.size / 1024, obj->base.read_domains, - obj->base.write_domain, - i915_gem_request_get_seqno(obj->last_read_req), + obj->base.write_domain); + for_each_ring(ring, dev_priv, i) + seq_printf(m, "%x ", + i915_gem_request_get_seqno(obj->last_read_req[i])); + seq_printf(m, "] %x %x%s%s%s", i915_gem_request_get_seqno(obj->last_write_req), i915_gem_request_get_seqno(obj->last_fenced_req), i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), @@ -169,9 +175,9 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) *t = '\0'; seq_printf(m, " (%s mappable)", s); } - if (obj->last_read_req != NULL) + if (obj->last_write_req != NULL) seq_printf(m, " (%s)", - i915_gem_request_get_ring(obj->last_read_req)->name); + i915_gem_request_get_ring(obj->last_write_req)->name); if (obj->frontbuffer_bits) seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 731b5cedf11d..8ddc36de1a6a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -508,7 +508,7 @@ struct drm_i915_error_state { struct drm_i915_error_buffer { u32 size; u32 name; - u32 rseqno, wseqno; + u32 rseqno[I915_NUM_RINGS], wseqno; u32 gtt_offset; u32 read_domains; u32 write_domain; @@ -1939,7 +1939,7 @@ struct drm_i915_gem_object { struct drm_mm_node *stolen; struct list_head global_list; - struct list_head ring_list; + struct list_head ring_list[I915_NUM_RINGS]; /** Used in execbuf to temporarily hold a ref */ struct list_head obj_exec_link; @@ -1950,7 +1950,7 @@ struct drm_i915_gem_object { * rendering and so a non-zero seqno), and is not set if it i s on * inactive (ready to be unbound) list. */ - unsigned int active:1; + unsigned int active:I915_NUM_RINGS; /** * This is set if the object has been written to since last bound @@ -2021,8 +2021,17 @@ struct drm_i915_gem_object { void *dma_buf_vmapping; int vmapping_count; - /** Breadcrumb of last rendering to the buffer. */ - struct drm_i915_gem_request *last_read_req; + /** Breadcrumb of last rendering to the buffer. + * There can only be one writer, but we allow for multiple readers. + * If there is a writer that necessarily implies that all other + * read requests are complete - but we may only be lazily clearing + * the read requests. A read request is naturally the most recent + * request on a ring, so we may have two different write and read + * requests on one ring where the write request is older than the + * read request. This allows for the CPU to read from an active + * buffer by only waiting for the write to complete. + * */ + struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; struct drm_i915_gem_request *last_write_req; /** Breadcrumb of last fenced GPU access to the buffer. */ struct drm_i915_gem_request *last_fenced_req; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fa4429144cb9..76ab4f18d618 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -38,11 +38,14 @@ #include #include +#define RQ_BUG_ON(expr) + static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); static void -i915_gem_object_retire(struct drm_i915_gem_object *obj); - +i915_gem_object_retire__write(struct drm_i915_gem_object *obj); +static void +i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); static void i915_gem_write_fence(struct drm_device *dev, int reg, struct drm_i915_gem_object *obj); static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, @@ -515,8 +518,6 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, ret = i915_gem_object_wait_rendering(obj, true); if (ret) return ret; - - i915_gem_object_retire(obj); } ret = i915_gem_object_get_pages(obj); @@ -936,8 +937,6 @@ i915_gem_shmem_pwrite(struct drm_device *dev, ret = i915_gem_object_wait_rendering(obj, false); if (ret) return ret; - - i915_gem_object_retire(obj); } /* Same trick applies to invalidate partially written cachelines read * before writing. */ @@ -1236,6 +1235,9 @@ int __i915_wait_request(struct drm_i915_gem_request *req, WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); + if (list_empty(&req->list)) + return 0; + if (i915_gem_request_completed(req, true)) return 0; @@ -1335,6 +1337,63 @@ out: return ret; } +static inline void +i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) +{ + struct drm_i915_file_private *file_priv = request->file_priv; + + if (!file_priv) + return; + + spin_lock(&file_priv->mm.lock); + list_del(&request->client_list); + request->file_priv = NULL; + spin_unlock(&file_priv->mm.lock); +} + +static void i915_gem_request_retire(struct drm_i915_gem_request *request) +{ + trace_i915_gem_request_retire(request); + + /* We know the GPU must have read the request to have + * sent us the seqno + interrupt, so use the position + * of tail of the request to update the last known position + * of the GPU head. + * + * Note this requires that we are always called in request + * completion order. + */ + request->ringbuf->last_retired_head = request->postfix; + + list_del_init(&request->list); + i915_gem_request_remove_from_client(request); + + put_pid(request->pid); + + i915_gem_request_unreference(request); +} + +static void +__i915_gem_request_retire__upto(struct drm_i915_gem_request *req) +{ + struct intel_engine_cs *engine = req->ring; + struct drm_i915_gem_request *tmp; + + lockdep_assert_held(&engine->dev->struct_mutex); + + if (list_empty(&req->list)) + return; + + do { + tmp = list_first_entry(&engine->request_list, + typeof(*tmp), list); + + i915_gem_request_retire(tmp); + } while (tmp != req); + + WARN_ON(i915_verify_lists(engine->dev)); +} + /** * Waits for a request to be signaled, and cleans up the * request and object lists appropriately for that event. @@ -1345,7 +1404,6 @@ i915_wait_request(struct drm_i915_gem_request *req) struct drm_device *dev; struct drm_i915_private *dev_priv; bool interruptible; - unsigned reset_counter; int ret; BUG_ON(req == NULL); @@ -1364,29 +1422,13 @@ i915_wait_request(struct drm_i915_gem_request *req) if (ret) return ret; - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); - i915_gem_request_reference(req); - ret = __i915_wait_request(req, reset_counter, + ret = __i915_wait_request(req, + atomic_read(&dev_priv->gpu_error.reset_counter), interruptible, NULL, NULL); - i915_gem_request_unreference(req); - return ret; -} - -static int -i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) -{ - if (!obj->active) - return 0; - - /* Manually manage the write flush as we may have not yet - * retired the buffer. - * - * Note that the last_write_req is always the earlier of - * the two (read/write) requests, so if we haved successfully waited, - * we know we have passed the last write. - */ - i915_gem_request_assign(&obj->last_write_req, NULL); + if (ret) + return ret; + __i915_gem_request_retire__upto(req); return 0; } @@ -1398,18 +1440,52 @@ int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, bool readonly) { - struct drm_i915_gem_request *req; - int ret; + int ret, i; - req = readonly ? obj->last_write_req : obj->last_read_req; - if (!req) + if (!obj->active) return 0; - ret = i915_wait_request(req); - if (ret) - return ret; + if (readonly) { + if (obj->last_write_req != NULL) { + ret = i915_wait_request(obj->last_write_req); + if (ret) + return ret; + + i = obj->last_write_req->ring->id; + if (obj->last_read_req[i] == obj->last_write_req) + i915_gem_object_retire__read(obj, i); + else + i915_gem_object_retire__write(obj); + } + } else { + for (i = 0; i < I915_NUM_RINGS; i++) { + if (obj->last_read_req[i] == NULL) + continue; + + ret = i915_wait_request(obj->last_read_req[i]); + if (ret) + return ret; + + i915_gem_object_retire__read(obj, i); + } + RQ_BUG_ON(obj->active); + } + + return 0; +} + +static void +i915_gem_object_retire_request(struct drm_i915_gem_object *obj, + struct drm_i915_gem_request *req) +{ + int ring = req->ring->id; + + if (obj->last_read_req[ring] == req) + i915_gem_object_retire__read(obj, ring); + else if (obj->last_write_req == req) + i915_gem_object_retire__write(obj); - return i915_gem_object_wait_rendering__tail(obj); + __i915_gem_request_retire__upto(req); } /* A nonblocking variant of the above wait. This is a highly dangerous routine @@ -1420,37 +1496,66 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, struct drm_i915_file_private *file_priv, bool readonly) { - struct drm_i915_gem_request *req; struct drm_device *dev = obj->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_gem_request *requests[I915_NUM_RINGS]; unsigned reset_counter; - int ret; + int ret, i, n = 0; BUG_ON(!mutex_is_locked(&dev->struct_mutex)); BUG_ON(!dev_priv->mm.interruptible); - req = readonly ? obj->last_write_req : obj->last_read_req; - if (!req) + if (!obj->active) return 0; ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); if (ret) return ret; - ret = i915_gem_check_olr(req); - if (ret) - return ret; - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); - i915_gem_request_reference(req); + + if (readonly) { + struct drm_i915_gem_request *req; + + req = obj->last_write_req; + if (req == NULL) + return 0; + + ret = i915_gem_check_olr(req); + if (ret) + goto err; + + requests[n++] = i915_gem_request_reference(req); + } else { + for (i = 0; i < I915_NUM_RINGS; i++) { + struct drm_i915_gem_request *req; + + req = obj->last_read_req[i]; + if (req == NULL) + continue; + + ret = i915_gem_check_olr(req); + if (ret) + goto err; + + requests[n++] = i915_gem_request_reference(req); + } + } + mutex_unlock(&dev->struct_mutex); - ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv); + for (i = 0; ret == 0 && i < n; i++) + ret = __i915_wait_request(requests[i], reset_counter, true, + NULL, file_priv); mutex_lock(&dev->struct_mutex); - i915_gem_request_unreference(req); - if (ret) - return ret; - return i915_gem_object_wait_rendering__tail(obj); +err: + for (i = 0; i < n; i++) { + if (ret == 0) + i915_gem_object_retire_request(obj, requests[i]); + i915_gem_request_unreference(requests[i]); + } + + return ret; } /** @@ -2231,78 +2336,58 @@ i915_gem_object_get_pages(struct drm_i915_gem_object *obj) return 0; } -static void -i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, - struct intel_engine_cs *ring) +void i915_vma_move_to_active(struct i915_vma *vma, + struct intel_engine_cs *ring) { - struct drm_i915_gem_request *req; - struct intel_engine_cs *old_ring; - - BUG_ON(ring == NULL); - - req = intel_ring_get_request(ring); - old_ring = i915_gem_request_get_ring(obj->last_read_req); - - if (old_ring != ring && obj->last_write_req) { - /* Keep the request relative to the current ring */ - i915_gem_request_assign(&obj->last_write_req, req); - } + struct drm_i915_gem_object *obj = vma->obj; /* Add a reference if we're newly entering the active list. */ - if (!obj->active) { + if (obj->active == 0) drm_gem_object_reference(&obj->base); - obj->active = 1; - } + obj->active |= intel_ring_flag(ring); - list_move_tail(&obj->ring_list, &ring->active_list); + list_move_tail(&obj->ring_list[ring->id], &ring->active_list); + i915_gem_request_assign(&obj->last_read_req[ring->id], + intel_ring_get_request(ring)); - i915_gem_request_assign(&obj->last_read_req, req); + list_move_tail(&vma->mm_list, &vma->vm->active_list); } -void i915_vma_move_to_active(struct i915_vma *vma, - struct intel_engine_cs *ring) +static void +i915_gem_object_retire__write(struct drm_i915_gem_object *obj) { - list_move_tail(&vma->mm_list, &vma->vm->active_list); - return i915_gem_object_move_to_active(vma->obj, ring); + RQ_BUG_ON(obj->last_write_req == NULL); + RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring))); + + i915_gem_request_assign(&obj->last_write_req, NULL); + intel_fb_obj_flush(obj, true); } static void -i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) +i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) { struct i915_vma *vma; - BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); - BUG_ON(!obj->active); + RQ_BUG_ON(obj->last_read_req[ring] == NULL); + RQ_BUG_ON(!(obj->active & (1 << ring))); + + list_del_init(&obj->ring_list[ring]); + i915_gem_request_assign(&obj->last_read_req[ring], NULL); + + if (obj->last_write_req && obj->last_write_req->ring->id == ring) + i915_gem_object_retire__write(obj); + + obj->active &= ~(1 << ring); + if (obj->active) + return; list_for_each_entry(vma, &obj->vma_list, vma_link) { if (!list_empty(&vma->mm_list)) list_move_tail(&vma->mm_list, &vma->vm->inactive_list); } - intel_fb_obj_flush(obj, true); - - list_del_init(&obj->ring_list); - - i915_gem_request_assign(&obj->last_read_req, NULL); - i915_gem_request_assign(&obj->last_write_req, NULL); - obj->base.write_domain = 0; - i915_gem_request_assign(&obj->last_fenced_req, NULL); - - obj->active = 0; drm_gem_object_unreference(&obj->base); - - WARN_ON(i915_verify_lists(dev)); -} - -static void -i915_gem_object_retire(struct drm_i915_gem_object *obj) -{ - if (obj->last_read_req == NULL) - return; - - if (i915_gem_request_completed(obj->last_read_req, true)) - i915_gem_object_move_to_inactive(obj); } static int @@ -2479,20 +2564,6 @@ int __i915_add_request(struct intel_engine_cs *ring, return 0; } -static inline void -i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) -{ - struct drm_i915_file_private *file_priv = request->file_priv; - - if (!file_priv) - return; - - spin_lock(&file_priv->mm.lock); - list_del(&request->client_list); - request->file_priv = NULL; - spin_unlock(&file_priv->mm.lock); -} - static bool i915_context_is_banned(struct drm_i915_private *dev_priv, const struct intel_context *ctx) { @@ -2538,16 +2609,6 @@ static void i915_set_reset_status(struct drm_i915_private *dev_priv, } } -static void i915_gem_free_request(struct drm_i915_gem_request *request) -{ - list_del(&request->list); - i915_gem_request_remove_from_client(request); - - put_pid(request->pid); - - i915_gem_request_unreference(request); -} - void i915_gem_request_free(struct kref *req_ref) { struct drm_i915_gem_request *req = container_of(req_ref, @@ -2648,9 +2709,9 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, obj = list_first_entry(&ring->active_list, struct drm_i915_gem_object, - ring_list); + ring_list[ring->id]); - i915_gem_object_move_to_inactive(obj); + i915_gem_object_retire__read(obj, ring->id); } /* @@ -2686,7 +2747,7 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, struct drm_i915_gem_request, list); - i915_gem_free_request(request); + i915_gem_request_retire(request); } /* This may not have been flushed before the reset, so clean it now */ @@ -2734,6 +2795,8 @@ void i915_gem_reset(struct drm_device *dev) i915_gem_context_reset(dev); i915_gem_restore_fences(dev); + + WARN_ON(i915_verify_lists(dev)); } /** @@ -2742,11 +2805,11 @@ void i915_gem_reset(struct drm_device *dev) void i915_gem_retire_requests_ring(struct intel_engine_cs *ring) { - if (list_empty(&ring->request_list)) - return; - WARN_ON(i915_verify_lists(ring->dev)); + if (list_empty(&ring->active_list)) + return; + /* Retire requests first as we use it above for the early return. * If we retire requests last, we may use a later seqno and so clear * the requests lists without clearing the active list, leading to @@ -2762,16 +2825,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring) if (!i915_gem_request_completed(request, true)) break; - trace_i915_gem_request_retire(request); - - /* We know the GPU must have read the request to have - * sent us the seqno + interrupt, so use the position - * of tail of the request to update the last known position - * of the GPU head. - */ - request->ringbuf->last_retired_head = request->postfix; - - i915_gem_free_request(request); + i915_gem_request_retire(request); } /* Move any buffers on the active list that are no longer referenced @@ -2783,12 +2837,12 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring) obj = list_first_entry(&ring->active_list, struct drm_i915_gem_object, - ring_list); + ring_list[ring->id]); - if (!i915_gem_request_completed(obj->last_read_req, true)) + if (!list_empty(&obj->last_read_req[ring->id]->list)) break; - i915_gem_object_move_to_inactive(obj); + i915_gem_object_retire__read(obj, ring->id); } if (unlikely(ring->trace_irq_req && @@ -2883,17 +2937,30 @@ i915_gem_idle_work_handler(struct work_struct *work) static int i915_gem_object_flush_active(struct drm_i915_gem_object *obj) { - struct intel_engine_cs *ring; - int ret; + int ret, i; + + if (!obj->active) + return 0; - if (obj->active) { - ring = i915_gem_request_get_ring(obj->last_read_req); + for (i = 0; i < I915_NUM_RINGS; i++) { + struct drm_i915_gem_request *req; - ret = i915_gem_check_olr(obj->last_read_req); + req = obj->last_read_req[i]; + if (req == NULL) + continue; + + if (list_empty(&req->list)) + goto retire; + + ret = i915_gem_check_olr(req); if (ret) return ret; - i915_gem_retire_requests_ring(ring); + if (i915_gem_request_completed(req, true)) { + __i915_gem_request_retire__upto(req); +retire: + i915_gem_object_retire__read(obj, i); + } } return 0; @@ -2927,9 +2994,10 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_wait *args = data; struct drm_i915_gem_object *obj; - struct drm_i915_gem_request *req; + struct drm_i915_gem_request *req[I915_NUM_RINGS]; unsigned reset_counter; - int ret = 0; + int i, n = 0; + int ret; if (args->flags != 0) return -EINVAL; @@ -2949,11 +3017,9 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) if (ret) goto out; - if (!obj->active || !obj->last_read_req) + if (!obj->active) goto out; - req = obj->last_read_req; - /* Do this after OLR check to make sure we make forward progress polling * on this IOCTL with a timeout == 0 (like busy ioctl) */ @@ -2964,13 +3030,23 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) drm_gem_object_unreference(&obj->base); reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); - i915_gem_request_reference(req); + + for (i = 0; i < I915_NUM_RINGS; i++) { + if (obj->last_read_req[i] == NULL) + continue; + + req[n++] = i915_gem_request_reference(obj->last_read_req[i]); + } + mutex_unlock(&dev->struct_mutex); - ret = __i915_wait_request(req, reset_counter, true, - args->timeout_ns > 0 ? &args->timeout_ns : NULL, - file->driver_priv); - i915_gem_request_unreference__unlocked(req); + for (i = 0; i < n; i++) { + if (ret == 0) + ret = __i915_wait_request(req[i], reset_counter, true, + args->timeout_ns > 0 ? &args->timeout_ns : NULL, + file->driver_priv); + i915_gem_request_unreference__unlocked(req[i]); + } return ret; out: @@ -2979,6 +3055,56 @@ out: return ret; } +static int +__i915_gem_object_sync(struct drm_i915_gem_object *obj, + struct intel_engine_cs *to, + struct drm_i915_gem_request *req) +{ + struct intel_engine_cs *from; + int ret; + + from = i915_gem_request_get_ring(req); + if (to == from) + return 0; + + if (i915_gem_request_completed(req, true)) + return 0; + + ret = i915_gem_check_olr(req); + if (ret) + return ret; + + if (!i915_semaphore_is_enabled(obj->base.dev)) { + ret = __i915_wait_request(req, + atomic_read(&to_i915(obj->base.dev)->gpu_error.reset_counter), + to_i915(obj->base.dev)->mm.interruptible, NULL, NULL); + if (ret) + return ret; + + i915_gem_object_retire_request(obj, req); + } else { + int idx = intel_ring_sync_index(from, to); + u32 seqno = i915_gem_request_get_seqno(req); + + if (seqno <= from->semaphore.sync_seqno[idx]) + return 0; + + trace_i915_gem_ring_sync_to(from, to, req); + ret = to->semaphore.sync_to(to, from, seqno); + if (ret) + return ret; + + /* We use last_read_req because sync_to() + * might have just caused seqno wrap under + * the radar. + */ + from->semaphore.sync_seqno[idx] = + i915_gem_request_get_seqno(obj->last_read_req[from->id]); + } + + return 0; +} + /** * i915_gem_object_sync - sync an object to a ring. * @@ -2987,7 +3113,17 @@ out: * * This code is meant to abstract object synchronization with the GPU. * Calling with NULL implies synchronizing the object with the CPU - * rather than a particular GPU ring. + * rather than a particular GPU ring. Conceptually we serialise writes + * between engines inside the GPU. We only allow on engine to write + * into a buffer at any time, but multiple readers. To ensure each has + * a coherent view of memory, we must: + * + * - If there is an outstanding write request to the object, the new + * request must wait for it to complete (either CPU or in hw, requests + * on the same ring will be naturally ordered). + * + * - If we are a write request (pending_write_domain is set), the new + * request must wait for outstanding read requests to complete. * * Returns 0 if successful, else propagates up the lower layer error. */ @@ -2995,41 +3131,32 @@ int i915_gem_object_sync(struct drm_i915_gem_object *obj, struct intel_engine_cs *to) { - struct intel_engine_cs *from; - u32 seqno; - int ret, idx; + const bool readonly = obj->base.pending_write_domain == 0; + struct drm_i915_gem_request *req[I915_NUM_RINGS]; + int ret, i, n; - from = i915_gem_request_get_ring(obj->last_read_req); - - if (from == NULL || to == from) - return 0; - - if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) - return i915_gem_object_wait_rendering(obj, false); - - idx = intel_ring_sync_index(from, to); - - seqno = i915_gem_request_get_seqno(obj->last_read_req); - /* Optimization: Avoid semaphore sync when we are sure we already - * waited for an object with higher seqno */ - if (seqno <= from->semaphore.sync_seqno[idx]) + if (!obj->active) return 0; - ret = i915_gem_check_olr(obj->last_read_req); - if (ret) - return ret; + if (to == NULL) + return i915_gem_object_wait_rendering(obj, readonly); - trace_i915_gem_ring_sync_to(from, to, obj->last_read_req); - ret = to->semaphore.sync_to(to, from, seqno); - if (!ret) - /* We use last_read_req because sync_to() - * might have just caused seqno wrap under - * the radar. - */ - from->semaphore.sync_seqno[idx] = - i915_gem_request_get_seqno(obj->last_read_req); + n = 0; + if (readonly) { + if (obj->last_write_req) + req[n++] = obj->last_write_req; + } else { + for (i = 0; i < I915_NUM_RINGS; i++) + if (obj->last_read_req[i]) + req[n++] = obj->last_read_req[i]; + } + for (i = 0; i < n; i++) { + ret = __i915_gem_object_sync(obj, to, req[i]); + if (ret) + return ret; + } - return ret; + return 0; } static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) @@ -3115,10 +3242,6 @@ int i915_vma_unbind(struct i915_vma *vma) /* Since the unbound list is global, only move to that list if * no more VMAs exist. */ if (list_empty(&obj->vma_list)) { - /* Throw away the active reference before - * moving to the unbound list. */ - i915_gem_object_retire(obj); - i915_gem_gtt_finish_object(obj); list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); } @@ -3151,6 +3274,7 @@ int i915_gpu_idle(struct drm_device *dev) return ret; } + WARN_ON(i915_verify_lists(dev)); return 0; } @@ -3773,8 +3897,6 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) if (ret) return ret; - i915_gem_object_retire(obj); - /* Flush and acquire obj->pages so that we are coherent through * direct access in memory with previous cached writes through * shmemfs and that our cache domain tracking remains valid. @@ -3972,11 +4094,9 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, u32 old_read_domains, old_write_domain; int ret; - if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) { - ret = i915_gem_object_sync(obj, pipelined); - if (ret) - return ret; - } + ret = i915_gem_object_sync(obj, pipelined); + if (ret) + return ret; /* Mark the pin_display early so that we account for the * display coherency whilst setting up the cache domains. @@ -4060,7 +4180,6 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) if (ret) return ret; - i915_gem_object_retire(obj); i915_gem_object_flush_gtt_write_domain(obj); old_write_domain = obj->base.write_domain; @@ -4349,15 +4468,15 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data, * necessary flushes here. */ ret = i915_gem_object_flush_active(obj); + if (ret) + goto unref; - args->busy = obj->active; - if (obj->last_read_req) { - struct intel_engine_cs *ring; - BUILD_BUG_ON(I915_NUM_RINGS > 16); - ring = i915_gem_request_get_ring(obj->last_read_req); - args->busy |= intel_ring_flag(ring) << 16; - } + BUILD_BUG_ON(I915_NUM_RINGS > 16); + args->busy = obj->active << 16; + if (obj->last_write_req) + args->busy |= obj->last_write_req->ring->id; +unref: drm_gem_object_unreference(&obj->base); unlock: mutex_unlock(&dev->struct_mutex); @@ -4431,8 +4550,11 @@ unlock: void i915_gem_object_init(struct drm_i915_gem_object *obj, const struct drm_i915_gem_object_ops *ops) { + int i; + INIT_LIST_HEAD(&obj->global_list); - INIT_LIST_HEAD(&obj->ring_list); + for (i = 0; i < I915_NUM_RINGS; i++) + INIT_LIST_HEAD(&obj->ring_list[i]); INIT_LIST_HEAD(&obj->obj_exec_link); INIT_LIST_HEAD(&obj->vma_list); INIT_LIST_HEAD(&obj->batch_pool_link); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 5a47eb5e3c5d..8867818b1401 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -753,8 +753,6 @@ static int do_switch(struct intel_engine_cs *ring, * swapped, but there is no way to do that yet. */ from->legacy_hw_ctx.rcs_state->dirty = 1; - BUG_ON(i915_gem_request_get_ring( - from->legacy_hw_ctx.rcs_state->last_read_req) != ring); /* obj is kept alive until the next request by its active ref */ i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); diff --git a/drivers/gpu/drm/i915/i915_gem_debug.c b/drivers/gpu/drm/i915/i915_gem_debug.c index f462d1b51d97..17299d04189f 100644 --- a/drivers/gpu/drm/i915/i915_gem_debug.c +++ b/drivers/gpu/drm/i915/i915_gem_debug.c @@ -34,82 +34,34 @@ int i915_verify_lists(struct drm_device *dev) { static int warned; - struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_gem_object *obj; + struct intel_engine_cs *ring; int err = 0; + int i; if (warned) return 0; - list_for_each_entry(obj, &dev_priv->render_ring.active_list, list) { - if (obj->base.dev != dev || - !atomic_read(&obj->base.refcount.refcount)) { - DRM_ERROR("freed render active %p\n", obj); - err++; - break; - } else if (!obj->active || - (obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) { - DRM_ERROR("invalid render active %p (a %d r %x)\n", - obj, - obj->active, - obj->base.read_domains); - err++; - } else if (obj->base.write_domain && list_empty(&obj->gpu_write_list)) { - DRM_ERROR("invalid render active %p (w %x, gwl %d)\n", - obj, - obj->base.write_domain, - !list_empty(&obj->gpu_write_list)); - err++; - } - } - - list_for_each_entry(obj, &dev_priv->mm.flushing_list, list) { - if (obj->base.dev != dev || - !atomic_read(&obj->base.refcount.refcount)) { - DRM_ERROR("freed flushing %p\n", obj); - err++; - break; - } else if (!obj->active || - (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 || - list_empty(&obj->gpu_write_list)) { - DRM_ERROR("invalid flushing %p (a %d w %x gwl %d)\n", - obj, - obj->active, - obj->base.write_domain, - !list_empty(&obj->gpu_write_list)); - err++; - } - } - - list_for_each_entry(obj, &dev_priv->mm.gpu_write_list, gpu_write_list) { - if (obj->base.dev != dev || - !atomic_read(&obj->base.refcount.refcount)) { - DRM_ERROR("freed gpu write %p\n", obj); - err++; - break; - } else if (!obj->active || - (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) { - DRM_ERROR("invalid gpu write %p (a %d w %x)\n", - obj, - obj->active, - obj->base.write_domain); - err++; - } - } - - list_for_each_entry(obj, &i915_gtt_vm->inactive_list, list) { - if (obj->base.dev != dev || - !atomic_read(&obj->base.refcount.refcount)) { - DRM_ERROR("freed inactive %p\n", obj); - err++; - break; - } else if (obj->pin_count || obj->active || - (obj->base.write_domain & I915_GEM_GPU_DOMAINS)) { - DRM_ERROR("invalid inactive %p (p %d a %d w %x)\n", - obj, - obj->pin_count, obj->active, - obj->base.write_domain); - err++; + for_each_ring(ring, dev_priv, i) { + list_for_each_entry(obj, &ring->active_list, ring_list[ring->id]) { + if (obj->base.dev != dev || + !atomic_read(&obj->base.refcount.refcount)) { + DRM_ERROR("%s: freed active obj %p\n", + ring->name, obj); + err++; + break; + } else if (!obj->active || + obj->last_read_req[ring->id] == NULL) { + DRM_ERROR("%s: invalid active obj %p\n", + ring->name, obj); + err++; + } else if (obj->base.write_domain) { + DRM_ERROR("%s: invalid write obj %p (w %x)\n", + ring->name, + obj, obj->base.write_domain); + err++; + } } } diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index a3e330d2a1d8..6f4256918f76 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -192,15 +192,20 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m, struct drm_i915_error_buffer *err, int count) { + int i; + err_printf(m, " %s [%d]:\n", name, count); while (count--) { - err_printf(m, " %08x %8u %02x %02x %x %x", + err_printf(m, " %08x %8u %02x %02x [ ", err->gtt_offset, err->size, err->read_domains, - err->write_domain, - err->rseqno, err->wseqno); + err->write_domain); + for (i = 0; i < I915_NUM_RINGS; i++) + err_printf(m, "%02x ", err->rseqno[i]); + + err_printf(m, "] %02x", err->wseqno); err_puts(m, pin_flag(err->pinned)); err_puts(m, tiling_flag(err->tiling)); err_puts(m, dirty_flag(err->dirty)); @@ -681,10 +686,12 @@ static void capture_bo(struct drm_i915_error_buffer *err, struct i915_vma *vma) { struct drm_i915_gem_object *obj = vma->obj; + int i; err->size = obj->base.size; err->name = obj->base.name; - err->rseqno = i915_gem_request_get_seqno(obj->last_read_req); + for (i = 0; i < I915_NUM_RINGS; i++) + err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]); err->wseqno = i915_gem_request_get_seqno(obj->last_write_req); err->gtt_offset = vma->node.start; err->read_domains = obj->base.read_domains; @@ -697,8 +704,8 @@ static void capture_bo(struct drm_i915_error_buffer *err, err->dirty = obj->dirty; err->purgeable = obj->madv != I915_MADV_WILLNEED; err->userptr = obj->userptr.mm != NULL; - err->ring = obj->last_read_req ? - i915_gem_request_get_ring(obj->last_read_req)->id : -1; + err->ring = obj->last_write_req ? + i915_gem_request_get_ring(obj->last_write_req)->id : -1; err->cache_level = obj->cache_level; } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7ef22db8cbbf..53ae5978491d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10682,7 +10682,7 @@ static bool use_mmio_flip(struct intel_engine_cs *ring, else if (i915.enable_execlists) return true; else - return ring != i915_gem_request_get_ring(obj->last_read_req); + return ring != i915_gem_request_get_ring(obj->last_write_req); } static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) @@ -10998,7 +10998,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { ring = &dev_priv->ring[BCS]; } else if (INTEL_INFO(dev)->gen >= 7) { - ring = i915_gem_request_get_ring(obj->last_read_req); + ring = i915_gem_request_get_ring(obj->last_write_req); if (ring == NULL || ring->id != RCS) ring = &dev_priv->ring[BCS]; } else { @@ -11014,7 +11014,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, */ ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, crtc->primary->state, - mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring); + mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring); if (ret) goto cleanup_pending; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 0413b8f85c55..a169cca48496 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -679,7 +679,8 @@ static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, { struct intel_engine_cs *ring = ringbuf->ring; struct drm_i915_gem_request *request; - int ret, new_space; + unsigned space; + int ret; if (intel_ring_space(ringbuf) >= bytes) return 0; @@ -690,14 +691,13 @@ static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, * from multiple ringbuffers. Here, we must ignore any that * aren't from the ringbuffer we're considering. */ - struct intel_context *ctx = request->ctx; - if (ctx->engine[ring->id].ringbuf != ringbuf) + if (request->ringbuf != ringbuf) continue; /* Would completion of this request free enough space? */ - new_space = __intel_ring_space(request->postfix, ringbuf->tail, - ringbuf->size); - if (new_space >= bytes) + space = __intel_ring_space(request->postfix, ringbuf->tail, + ringbuf->size); + if (space >= bytes) break; } @@ -708,11 +708,8 @@ static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, if (ret) return ret; - i915_gem_retire_requests_ring(ring); - - WARN_ON(intel_ring_space(ringbuf) < new_space); - - return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC; + ringbuf->space = space; + return 0; } /* diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 5fd2d5ac02e2..25c8ec697da1 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -228,7 +228,6 @@ static int intel_overlay_do_wait_request(struct intel_overlay *overlay, ret = i915_wait_request(overlay->last_flip_req); if (ret) return ret; - i915_gem_retire_requests(dev); i915_gem_request_assign(&overlay->last_flip_req, NULL); return 0; @@ -376,7 +375,6 @@ static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) ret = i915_wait_request(overlay->last_flip_req); if (ret) return ret; - i915_gem_retire_requests(overlay->dev); if (overlay->flip_tail) overlay->flip_tail(overlay); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 6ab5765c3061..052265ae8de1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2103,15 +2103,16 @@ static int ring_wait_for_space(struct intel_engine_cs *ring, int n) { struct intel_ringbuffer *ringbuf = ring->buffer; struct drm_i915_gem_request *request; - int ret, new_space; + unsigned space; + int ret; if (intel_ring_space(ringbuf) >= n) return 0; list_for_each_entry(request, &ring->request_list, list) { - new_space = __intel_ring_space(request->postfix, ringbuf->tail, - ringbuf->size); - if (new_space >= n) + space = __intel_ring_space(request->postfix, ringbuf->tail, + ringbuf->size); + if (space >= n) break; } @@ -2122,10 +2123,7 @@ static int ring_wait_for_space(struct intel_engine_cs *ring, int n) if (ret) return ret; - i915_gem_retire_requests_ring(ring); - - WARN_ON(intel_ring_space(ringbuf) < new_space); - + ringbuf->space = space; return 0; } @@ -2169,10 +2167,14 @@ int intel_ring_idle(struct intel_engine_cs *ring) return 0; req = list_entry(ring->request_list.prev, - struct drm_i915_gem_request, - list); - - return i915_wait_request(req); + struct drm_i915_gem_request, + list); + + /* Make sure we do not trigger any retires */ + return __i915_wait_request(req, + atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter), + to_i915(ring->dev)->mm.interruptible, + NULL, NULL); } int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) -- cgit v1.2.3 From 03ade51185596a1d1028531c78fda557f244d676 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 13:41:18 +0100 Subject: drm/i915: Inline check required for object syncing prior to execbuf This trims a little overhead from the common case of not needing to synchronize between rings. v2: execlists is special and likes to duplicate code. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +++++++--- drivers/gpu/drm/i915/intel_lrc.c | 9 ++++++--- 2 files changed, 13 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 560c79a8a43d..bd0e4bda2c64 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -889,6 +889,7 @@ static int i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring, struct list_head *vmas) { + const unsigned other_rings = ~intel_ring_flag(ring); struct i915_vma *vma; uint32_t flush_domains = 0; bool flush_chipset = false; @@ -896,9 +897,12 @@ i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring, list_for_each_entry(vma, vmas, exec_list) { struct drm_i915_gem_object *obj = vma->obj; - ret = i915_gem_object_sync(obj, ring); - if (ret) - return ret; + + if (obj->active & other_rings) { + ret = i915_gem_object_sync(obj, ring); + if (ret) + return ret; + } if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) flush_chipset |= i915_gem_clflush_object(obj, false); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index a169cca48496..96ae90affad5 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -628,6 +628,7 @@ static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, struct list_head *vmas) { struct intel_engine_cs *ring = ringbuf->ring; + const unsigned other_rings = ~intel_ring_flag(ring); struct i915_vma *vma; uint32_t flush_domains = 0; bool flush_chipset = false; @@ -636,9 +637,11 @@ static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, list_for_each_entry(vma, vmas, exec_list) { struct drm_i915_gem_object *obj = vma->obj; - ret = i915_gem_object_sync(obj, ring); - if (ret) - return ret; + if (obj->active & other_rings) { + ret = i915_gem_object_sync(obj, ring); + if (ret) + return ret; + } if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) flush_chipset |= i915_gem_clflush_object(obj, false); -- cgit v1.2.3 From a6f766f3975185af66a31a2cea2cd38721645999 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 13:41:20 +0100 Subject: drm/i915: Limit ring synchronisation (sw sempahores) RPS boosts Ring switches can occur many times per frame, and are often out of control, causing frequent RPS boosting for no practical benefit. Treat the sw semaphore synchronisation as a separate client and only allow it to boost once per busy/idle cycle. Signed-off-by: Chris Wilson [danvet: s/rq/req/] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 34 ++++++++++++++++++---------------- drivers/gpu/drm/i915/i915_gem.c | 7 +++++-- drivers/gpu/drm/i915/intel_pm.c | 1 + 4 files changed, 25 insertions(+), 18 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 5fceb9400a91..2ac71483cf12 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2311,6 +2311,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) list_empty(&file_priv->rps_boost) ? "" : ", active"); rcu_read_unlock(); } + seq_printf(m, "Semaphore boosts: %d\n", dev_priv->rps.semaphores.rps_boosts); seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); mutex_unlock(&dev_priv->rps.hw_lock); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 8ddc36de1a6a..2c44ca752e36 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -272,6 +272,22 @@ struct drm_i915_private; struct i915_mm_struct; struct i915_mmu_object; +struct drm_i915_file_private { + struct drm_i915_private *dev_priv; + struct drm_file *file; + + struct { + spinlock_t lock; + struct list_head request_list; + } mm; + struct idr context_idr; + + struct list_head rps_boost; + struct intel_engine_cs *bsd_ring; + + unsigned rps_boosts; +}; + enum intel_dpll_id { DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ /* real shared dpll ids must be >= 0 */ @@ -1070,6 +1086,8 @@ struct intel_gen6_power_mgmt { struct list_head clients; unsigned boosts; + struct drm_i915_file_private semaphores; + /* manual wa residency calculations */ struct intel_rps_ei up_ei, down_ei; @@ -2216,22 +2234,6 @@ static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, * a later patch when the call to i915_seqno_passed() is obsoleted... */ -struct drm_i915_file_private { - struct drm_i915_private *dev_priv; - struct drm_file *file; - - struct { - spinlock_t lock; - struct list_head request_list; - } mm; - struct idr context_idr; - - struct list_head rps_boost; - struct intel_engine_cs *bsd_ring; - - unsigned rps_boosts; -}; - /* * A command that requires special handling by the command parser. */ diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 76ab4f18d618..4ad9e262bbc0 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3075,9 +3075,12 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj, return ret; if (!i915_semaphore_is_enabled(obj->base.dev)) { + struct drm_i915_private *i915 = to_i915(obj->base.dev); ret = __i915_wait_request(req, - atomic_read(&to_i915(obj->base.dev)->gpu_error.reset_counter), - to_i915(obj->base.dev)->mm.interruptible, NULL, NULL); + atomic_read(&i915->gpu_error.reset_counter), + i915->mm.interruptible, + NULL, + &i915->rps.semaphores); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5dda008698a2..da7120ddb485 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6884,6 +6884,7 @@ void intel_pm_setup(struct drm_device *dev) INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, intel_gen6_powersave_work); INIT_LIST_HEAD(&dev_priv->rps.clients); + INIT_LIST_HEAD(&dev_priv->rps.semaphores.rps_boost); dev_priv->pm.suspended = false; } -- cgit v1.2.3 From bcafc4e38b6ad03f48989b7ecaff03845b5b7acf Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 13:41:21 +0100 Subject: drm/i915: Limit mmio flip RPS boosts Since we will often pageflip to an active surface, we will often have to wait for the surface to be written before issuing the flip. Also we are likely to wait on that surface in plenty of time before the vblank. Since we have a mechanism for boosting when a flip misses the expected vblank, curtain the number of times we RPS boost when simply waiting for mmioflip. Signed-off-by: Chris Wilson [danvet: s/rq/req/] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 4 +++- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 1 + 5 files changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2ac71483cf12..21257faa3f8f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2312,6 +2312,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) rcu_read_unlock(); } seq_printf(m, "Semaphore boosts: %d\n", dev_priv->rps.semaphores.rps_boosts); + seq_printf(m, "MMIO flip boosts: %d\n", dev_priv->rps.mmioflips.rps_boosts); seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); mutex_unlock(&dev_priv->rps.hw_lock); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2c44ca752e36..64d632941e06 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1087,6 +1087,7 @@ struct intel_gen6_power_mgmt { unsigned boosts; struct drm_i915_file_private semaphores; + struct drm_i915_file_private mmioflips; /* manual wa residency calculations */ struct intel_rps_ei up_ei, down_ei; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 53ae5978491d..048565572764 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10788,7 +10788,8 @@ static void intel_mmio_flip_work_func(struct work_struct *work) if (mmio_flip->req) WARN_ON(__i915_wait_request(mmio_flip->req, mmio_flip->crtc->reset_counter, - false, NULL, NULL)); + false, NULL, + &mmio_flip->i915->rps.mmioflips)); intel_do_mmio_flip(mmio_flip->crtc); @@ -10809,6 +10810,7 @@ static int intel_queue_mmio_flip(struct drm_device *dev, if (mmio_flip == NULL) return -ENOMEM; + mmio_flip->i915 = to_i915(dev); mmio_flip->req = i915_gem_request_reference(obj->last_write_req); mmio_flip->crtc = to_intel_crtc(crtc); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index c3c42ead4b46..5afe1fe2bd6e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -460,6 +460,7 @@ struct intel_pipe_wm { struct intel_mmio_flip { struct work_struct work; + struct drm_i915_private *i915; struct drm_i915_gem_request *req; struct intel_crtc *crtc; }; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index da7120ddb485..48e86255b7c8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6885,6 +6885,7 @@ void intel_pm_setup(struct drm_device *dev) intel_gen6_powersave_work); INIT_LIST_HEAD(&dev_priv->rps.clients); INIT_LIST_HEAD(&dev_priv->rps.semaphores.rps_boost); + INIT_LIST_HEAD(&dev_priv->rps.mmioflips.rps_boost); dev_priv->pm.suspended = false; } -- cgit v1.2.3 From 2e1b873072dfe3bbcc158a9c21acde1ab0d36c55 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 13:41:22 +0100 Subject: drm/i915: Convert RPS tracking to a intel_rps_client struct Now that we have internal clients, rather than faking a whole drm_i915_file_private just for tracking RPS boosts, create a new struct intel_rps_client and pass it along when waiting. Signed-off-by: Chris Wilson [danvet: s/rq/req/] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 12 ++++++++---- drivers/gpu/drm/i915/i915_drv.h | 13 +++++++------ drivers/gpu/drm/i915/i915_gem.c | 24 +++++++++++++++--------- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 14 +++++++------- 5 files changed, 38 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 21257faa3f8f..c68421a035cc 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2307,12 +2307,16 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) seq_printf(m, "%s [%d]: %d boosts%s\n", task ? task->comm : "", task ? task->pid : -1, - file_priv->rps_boosts, - list_empty(&file_priv->rps_boost) ? "" : ", active"); + file_priv->rps.boosts, + list_empty(&file_priv->rps.link) ? "" : ", active"); rcu_read_unlock(); } - seq_printf(m, "Semaphore boosts: %d\n", dev_priv->rps.semaphores.rps_boosts); - seq_printf(m, "MMIO flip boosts: %d\n", dev_priv->rps.mmioflips.rps_boosts); + seq_printf(m, "Semaphore boosts: %d%s\n", + dev_priv->rps.semaphores.boosts, + list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active"); + seq_printf(m, "MMIO flip boosts: %d%s\n", + dev_priv->rps.mmioflips.boosts, + list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); mutex_unlock(&dev_priv->rps.hw_lock); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 64d632941e06..b4eebd04565c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -282,10 +282,12 @@ struct drm_i915_file_private { } mm; struct idr context_idr; - struct list_head rps_boost; - struct intel_engine_cs *bsd_ring; + struct intel_rps_client { + struct list_head link; + unsigned boosts; + } rps; - unsigned rps_boosts; + struct intel_engine_cs *bsd_ring; }; enum intel_dpll_id { @@ -1086,8 +1088,7 @@ struct intel_gen6_power_mgmt { struct list_head clients; unsigned boosts; - struct drm_i915_file_private semaphores; - struct drm_i915_file_private mmioflips; + struct intel_rps_client semaphores, mmioflips; /* manual wa residency calculations */ struct intel_rps_ei up_ei, down_ei; @@ -2856,7 +2857,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req, unsigned reset_counter, bool interruptible, s64 *timeout, - struct drm_i915_file_private *file_priv); + struct intel_rps_client *rps); int __must_check i915_wait_request(struct drm_i915_gem_request *req); int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); int __must_check diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 4ad9e262bbc0..289178b7e684 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1221,7 +1221,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req, unsigned reset_counter, bool interruptible, s64 *timeout, - struct drm_i915_file_private *file_priv) + struct intel_rps_client *rps) { struct intel_engine_cs *ring = i915_gem_request_get_ring(req); struct drm_device *dev = ring->dev; @@ -1244,8 +1244,8 @@ int __i915_wait_request(struct drm_i915_gem_request *req, timeout_expire = timeout ? jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; - if (INTEL_INFO(dev)->gen >= 6) - gen6_rps_boost(dev_priv, file_priv); + if (INTEL_INFO(dev_priv)->gen >= 6) + gen6_rps_boost(dev_priv, rps); /* Record current time in case interrupted by signal, or wedged */ trace_i915_gem_request_wait_begin(req); @@ -1493,7 +1493,7 @@ i915_gem_object_retire_request(struct drm_i915_gem_object *obj, */ static __must_check int i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, - struct drm_i915_file_private *file_priv, + struct intel_rps_client *rps, bool readonly) { struct drm_device *dev = obj->base.dev; @@ -1545,7 +1545,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, mutex_unlock(&dev->struct_mutex); for (i = 0; ret == 0 && i < n; i++) ret = __i915_wait_request(requests[i], reset_counter, true, - NULL, file_priv); + NULL, rps); mutex_lock(&dev->struct_mutex); err: @@ -1558,6 +1558,12 @@ err: return ret; } +static struct intel_rps_client *to_rps_client(struct drm_file *file) +{ + struct drm_i915_file_private *fpriv = file->driver_priv; + return &fpriv->rps; +} + /** * Called when user space prepares to use an object with the CPU, either * through the mmap ioctl's mapping or a GTT mapping. @@ -1600,7 +1606,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, * to catch cases where we are gazumped. */ ret = i915_gem_object_wait_rendering__nonblocking(obj, - file->driver_priv, + to_rps_client(file), !write_domain); if (ret) goto unref; @@ -5216,9 +5222,9 @@ void i915_gem_release(struct drm_device *dev, struct drm_file *file) } spin_unlock(&file_priv->mm.lock); - if (!list_empty(&file_priv->rps_boost)) { + if (!list_empty(&file_priv->rps.link)) { mutex_lock(&to_i915(dev)->rps.hw_lock); - list_del(&file_priv->rps_boost); + list_del(&file_priv->rps.link); mutex_unlock(&to_i915(dev)->rps.hw_lock); } } @@ -5237,7 +5243,7 @@ int i915_gem_open(struct drm_device *dev, struct drm_file *file) file->driver_priv = file_priv; file_priv->dev_priv = dev->dev_private; file_priv->file = file; - INIT_LIST_HEAD(&file_priv->rps_boost); + INIT_LIST_HEAD(&file_priv->rps.link); spin_lock_init(&file_priv->mm.lock); INIT_LIST_HEAD(&file_priv->mm.request_list); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 5afe1fe2bd6e..6968e7483863 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1365,7 +1365,7 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv); void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); void gen6_rps_idle(struct drm_i915_private *dev_priv); void gen6_rps_boost(struct drm_i915_private *dev_priv, - struct drm_i915_file_private *file_priv); + struct intel_rps_client *rps); void intel_queue_rps_boost_for_request(struct drm_device *dev, struct drm_i915_gem_request *req); void ilk_wm_get_hw_state(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 48e86255b7c8..b676fe81c563 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4150,7 +4150,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv) } void gen6_rps_boost(struct drm_i915_private *dev_priv, - struct drm_i915_file_private *file_priv) + struct intel_rps_client *rps) { u32 val; @@ -4159,13 +4159,13 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv, if (dev_priv->rps.enabled && dev_priv->mm.busy && dev_priv->rps.cur_freq < val && - (file_priv == NULL || list_empty(&file_priv->rps_boost))) { + (rps == NULL || list_empty(&rps->link))) { intel_set_rps(dev_priv->dev, val); dev_priv->rps.last_adj = 0; - if (file_priv != NULL) { - list_add(&file_priv->rps_boost, &dev_priv->rps.clients); - file_priv->rps_boosts++; + if (rps != NULL) { + list_add(&rps->link, &dev_priv->rps.clients); + rps->boosts++; } else dev_priv->rps.boosts++; } @@ -6884,8 +6884,8 @@ void intel_pm_setup(struct drm_device *dev) INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, intel_gen6_powersave_work); INIT_LIST_HEAD(&dev_priv->rps.clients); - INIT_LIST_HEAD(&dev_priv->rps.semaphores.rps_boost); - INIT_LIST_HEAD(&dev_priv->rps.mmioflips.rps_boost); + INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); + INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); dev_priv->pm.suspended = false; } -- cgit v1.2.3 From f5a4c67d52e42ad4e76c27287fb7e4a06e11e3fc Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 13:41:23 +0100 Subject: drm/i915: Don't downclock whilst we have clients waiting for GPU results If we have clients stalled waiting for requests, ignore the GPU if it signals that it should downclock due to low load. This helps prevent the automatic timeout from causing extremely long running batches from taking even longer. Signed-off-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_irq.c | 14 ++++++++++++++ 2 files changed, 35 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index c68421a035cc..fece922718e2 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2282,6 +2282,18 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) return 0; } +static int count_irq_waiters(struct drm_i915_private *i915) +{ + struct intel_engine_cs *ring; + int count = 0; + int i; + + for_each_ring(ring, i915, i) + count += ring->irq_refcount; + + return count; +} + static int i915_rps_boost_info(struct seq_file *m, void *data) { struct drm_info_node *node = m->private; @@ -2298,6 +2310,15 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) if (ret) goto unlock; + seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); + seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); + seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); + seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n", + intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), + intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), + intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), + intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), + intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); list_for_each_entry_reverse(file, &dev->filelist, lhead) { struct drm_i915_file_private *file_priv = file->driver_priv; struct task_struct *task; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 557af8877a2e..707e2ca8fbd8 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1070,6 +1070,18 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) return events; } +static bool any_waiters(struct drm_i915_private *dev_priv) +{ + struct intel_engine_cs *ring; + int i; + + for_each_ring(ring, dev_priv, i) + if (ring->irq_refcount) + return true; + + return false; +} + static void gen6_pm_rps_work(struct work_struct *work) { struct drm_i915_private *dev_priv = @@ -1114,6 +1126,8 @@ static void gen6_pm_rps_work(struct work_struct *work) new_delay = dev_priv->rps.efficient_freq; adj = 0; } + } else if (any_waiters(dev_priv)) { + adj = 0; } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) new_delay = dev_priv->rps.efficient_freq; -- cgit v1.2.3 From e61b995841e6d165b77209c2bdf9c96ae0c16b89 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 27 Apr 2015 13:41:24 +0100 Subject: drm/i915: Free RPS boosts for all laggards If the client stalls on a congested request, chosen to be 20ms old to match throttling, allow the client a free RPS boost. Signed-off-by: Chris Wilson [danvet: s/rq/req/] [danvet: s/0/NULL/ reported by 0-day build] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 3 ++- drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++---- 3 files changed, 19 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 289178b7e684..50e49a3d7e51 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1245,7 +1245,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req, jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; if (INTEL_INFO(dev_priv)->gen >= 6) - gen6_rps_boost(dev_priv, rps); + gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); /* Record current time in case interrupted by signal, or wedged */ trace_i915_gem_request_wait_begin(req); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 6968e7483863..e94cb6e16456 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1365,7 +1365,8 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv); void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); void gen6_rps_idle(struct drm_i915_private *dev_priv); void gen6_rps_boost(struct drm_i915_private *dev_priv, - struct intel_rps_client *rps); + struct intel_rps_client *rps, + unsigned long submitted); void intel_queue_rps_boost_for_request(struct drm_device *dev, struct drm_i915_gem_request *req); void ilk_wm_get_hw_state(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b676fe81c563..6414b27692d4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4150,10 +4150,17 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv) } void gen6_rps_boost(struct drm_i915_private *dev_priv, - struct intel_rps_client *rps) + struct intel_rps_client *rps, + unsigned long submitted) { u32 val; + /* Force a RPS boost (and don't count it against the client) if + * the GPU is severely congested. + */ + if (rps && time_after(jiffies, submitted + msecs_to_jiffies(20))) + rps = NULL; + mutex_lock(&dev_priv->rps.hw_lock); val = dev_priv->rps.max_freq_softlimit; if (dev_priv->rps.enabled && @@ -6848,11 +6855,13 @@ struct request_boost { static void __intel_rps_boost_work(struct work_struct *work) { struct request_boost *boost = container_of(work, struct request_boost, work); + struct drm_i915_gem_request *req = boost->req; - if (!i915_gem_request_completed(boost->req, true)) - gen6_rps_boost(to_i915(boost->req->ring->dev), NULL); + if (!i915_gem_request_completed(req, true)) + gen6_rps_boost(to_i915(req->ring->dev), NULL, + req->emitted_jiffies); - i915_gem_request_unreference__unlocked(boost->req); + i915_gem_request_unreference__unlocked(req); kfree(boost); } @@ -6864,6 +6873,9 @@ void intel_queue_rps_boost_for_request(struct drm_device *dev, if (req == NULL || INTEL_INFO(dev)->gen < 6) return; + if (i915_gem_request_completed(req, true)) + return; + boost = kmalloc(sizeof(*boost), GFP_ATOMIC); if (boost == NULL) return; -- cgit v1.2.3 From 5d96d8afcfbb1500272756747e0bfcdbebf3b070 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Thu, 21 May 2015 16:37:48 +0100 Subject: drm/i915/skl: Deinit/init the display at suspend/resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need to re-init the display hardware when going out of suspend. This includes: - Hooking the PCH to the reset logic - Restoring CDCDLK - Enabling the DDB power Among those, only the CDCDLK one is a bit tricky. There's some complexity in that: - DPLL0 (which is the source for CDCLK) has two VCOs, each with a set of supported frequencies. As eDP also uses DPLL0 for its link rate, once DPLL0 is on, we restrict the possible eDP link rates the chosen VCO. - CDCLK also limits the bandwidth available to push pixels. So, as a first step, this commit restore what the BIOS set, until I can do more testing. In case that's of interest for the reviewer, I've unit tested the function that derives the decimal frequency field: #include #include #include #define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x))) static const struct dpll_freq { unsigned int freq; unsigned int decimal; } freqs[] = { { .freq = 308570, .decimal = 0b01001100111}, { .freq = 337500, .decimal = 0b01010100001}, { .freq = 432000, .decimal = 0b01101011110}, { .freq = 450000, .decimal = 0b01110000010}, { .freq = 540000, .decimal = 0b10000110110}, { .freq = 617140, .decimal = 0b10011010000}, { .freq = 675000, .decimal = 0b10101000100}, }; static void intbits(unsigned int v) { int i; for(i = 10; i >= 0; i--) putchar('0' + ((v >> i) & 1)); } static unsigned int freq_decimal(unsigned int freq /* in kHz */) { return (freq - 1000) / 500; } static void test_freq(const struct dpll_freq *entry) { unsigned int decimal = freq_decimal(entry->freq); printf("freq: %d, expected: ", entry->freq); intbits(entry->decimal); printf(", got: "); intbits(decimal); putchar('\n'); assert(decimal == entry->decimal); } int main(int argc, char **argv) { int i; for (i = 0; i < ARRAY_SIZE(freqs); i++) test_freq(&freqs[i]); return 0; } v2: - Rebase on top of -nightly - Use (freq - 1000) / 500 for the decimal frequency (Ville) - Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville) - Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to be consistent with the BXT code (Ville) - Store boot CDCLK in ddi_pll_init (Ville) - Merge dev_priv's skl_boot_cdclk into cdclk_freq - Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville) - Replace various '0' by SKL_DPLL0 to be a bit more explicit that we're programming DPLL0 - Busy poll the PCU before doing the frequency change. It takes about 3/4 cycles, each separated by 10us, to get the ACK from the CPU (Ville) v3: - Restore dev_priv->skl_boot_cdclk, leaving unification with dev_priv->cdclk_freq for a later patch (Daniel, Ville) Reviewed-by: Ville Syrjälä Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 3 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_ddi.c | 8 +- drivers/gpu/drm/i915/intel_display.c | 208 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 + 6 files changed, 223 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 93191c1fd18e..884b4f9b81c4 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1047,6 +1047,8 @@ static int skl_suspend_complete(struct drm_i915_private *dev_priv) */ intel_csr_load_status_set(dev_priv, FW_UNINITIALIZED); + skl_uninit_cdclk(dev_priv); + return 0; } @@ -1093,6 +1095,7 @@ static int skl_resume_prepare(struct drm_i915_private *dev_priv) { struct drm_device *dev = dev_priv->dev; + skl_init_cdclk(dev_priv); intel_csr_load_program(dev); return 0; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b4eebd04565c..44d592f3b67c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1705,6 +1705,7 @@ struct drm_i915_private { int num_fence_regs; /* 8 on pre-965, 16 otherwise */ unsigned int fsb_freq, mem_freq, is_ddr3; + unsigned int skl_boot_cdclk; unsigned int cdclk_freq; unsigned int hpll_freq; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3f94f38eec1f..c799b993c15d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6699,6 +6699,9 @@ enum skl_disp_power_wells { #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 +#define SKL_PCODE_CDCLK_CONTROL 0x7 +#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 +#define SKL_CDCLK_READY_FOR_CHANGE 0x1 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 #define GEN6_READ_OC_PARAMS 0xc diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index d602db25eb33..cacb07b7a8f1 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2510,6 +2510,7 @@ void intel_ddi_pll_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; uint32_t val = I915_READ(LCPLL_CTL); + int cdclk_freq; if (IS_SKYLAKE(dev)) skl_shared_dplls_init(dev_priv); @@ -2518,12 +2519,15 @@ void intel_ddi_pll_init(struct drm_device *dev) else hsw_shared_dplls_init(dev_priv); - DRM_DEBUG_KMS("CDCLK running at %dKHz\n", - dev_priv->display.get_display_clock_speed(dev)); + cdclk_freq = dev_priv->display.get_display_clock_speed(dev); + DRM_DEBUG_KMS("CDCLK running at %dKHz\n", cdclk_freq); if (IS_SKYLAKE(dev)) { + dev_priv->skl_boot_cdclk = cdclk_freq; if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) DRM_ERROR("LCPLL1 is disabled\n"); + else + intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); } else if (IS_BROXTON(dev)) { broxton_init_cdclk(dev); broxton_ddi_phy_init(dev); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 048565572764..268043f65dd8 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5527,6 +5527,214 @@ void broxton_uninit_cdclk(struct drm_device *dev) intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); } +static const struct skl_cdclk_entry { + unsigned int freq; + unsigned int vco; +} skl_cdclk_frequencies[] = { + { .freq = 308570, .vco = 8640 }, + { .freq = 337500, .vco = 8100 }, + { .freq = 432000, .vco = 8640 }, + { .freq = 450000, .vco = 8100 }, + { .freq = 540000, .vco = 8100 }, + { .freq = 617140, .vco = 8640 }, + { .freq = 675000, .vco = 8100 }, +}; + +static unsigned int skl_cdclk_decimal(unsigned int freq) +{ + return (freq - 1000) / 500; +} + +static unsigned int skl_cdclk_get_vco(unsigned int freq) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { + const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; + + if (e->freq == freq) + return e->vco; + } + + return 8100; +} + +static void +skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) +{ + unsigned int min_freq; + u32 val; + + /* select the minimum CDCLK before enabling DPLL 0 */ + val = I915_READ(CDCLK_CTL); + val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; + val |= CDCLK_FREQ_337_308; + + if (required_vco == 8640) + min_freq = 308570; + else + min_freq = 337500; + + val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); + + I915_WRITE(CDCLK_CTL, val); + POSTING_READ(CDCLK_CTL); + + /* + * We always enable DPLL0 with the lowest link rate possible, but still + * taking into account the VCO required to operate the eDP panel at the + * desired frequency. The usual DP link rates operate with a VCO of + * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. + * The modeset code is responsible for the selection of the exact link + * rate later on, with the constraint of choosing a frequency that + * works with required_vco. + */ + val = I915_READ(DPLL_CTRL1); + + val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | + DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); + val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); + if (required_vco == 8640) + val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, + SKL_DPLL0); + else + val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, + SKL_DPLL0); + + I915_WRITE(DPLL_CTRL1, val); + POSTING_READ(DPLL_CTRL1); + + I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); + + if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) + DRM_ERROR("DPLL0 not locked\n"); +} + +static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) +{ + int ret; + u32 val; + + /* inform PCU we want to change CDCLK */ + val = SKL_CDCLK_PREPARE_FOR_CHANGE; + mutex_lock(&dev_priv->rps.hw_lock); + ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); + mutex_unlock(&dev_priv->rps.hw_lock); + + return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); +} + +static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) +{ + unsigned int i; + + for (i = 0; i < 15; i++) { + if (skl_cdclk_pcu_ready(dev_priv)) + return true; + udelay(10); + } + + return false; +} + +static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) +{ + u32 freq_select, pcu_ack; + + DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); + + if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { + DRM_ERROR("failed to inform PCU about cdclk change\n"); + return; + } + + /* set CDCLK_CTL */ + switch(freq) { + case 450000: + case 432000: + freq_select = CDCLK_FREQ_450_432; + pcu_ack = 1; + break; + case 540000: + freq_select = CDCLK_FREQ_540; + pcu_ack = 2; + break; + case 308570: + case 337500: + default: + freq_select = CDCLK_FREQ_337_308; + pcu_ack = 0; + break; + case 617140: + case 675000: + freq_select = CDCLK_FREQ_675_617; + pcu_ack = 3; + break; + } + + I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); + POSTING_READ(CDCLK_CTL); + + /* inform PCU of the change */ + mutex_lock(&dev_priv->rps.hw_lock); + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); + mutex_unlock(&dev_priv->rps.hw_lock); +} + +void skl_uninit_cdclk(struct drm_i915_private *dev_priv) +{ + /* disable DBUF power */ + I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); + POSTING_READ(DBUF_CTL); + + udelay(10); + + if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) + DRM_ERROR("DBuf power disable timeout\n"); + + /* disable DPLL0 */ + I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); + if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) + DRM_ERROR("Couldn't disable DPLL0\n"); + + intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); +} + +void skl_init_cdclk(struct drm_i915_private *dev_priv) +{ + u32 val; + unsigned int required_vco; + + /* enable PCH reset handshake */ + val = I915_READ(HSW_NDE_RSTWRN_OPT); + I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); + + /* enable PG1 and Misc I/O */ + intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); + + /* DPLL0 already enabed !? */ + if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) { + DRM_DEBUG_DRIVER("DPLL0 already running\n"); + return; + } + + /* enable DPLL0 */ + required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); + skl_dpll0_enable(dev_priv, required_vco); + + /* set CDCLK to the frequency the BIOS chose */ + skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); + + /* enable DBUF power */ + I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); + POSTING_READ(DBUF_CTL); + + udelay(10); + + if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) + DRM_ERROR("DBuf power enable timeout\n"); +} + /* returns HPLL frequency in kHz */ static int valleyview_get_vco(struct drm_i915_private *dev_priv) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index e94cb6e16456..02d83178bd03 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1118,6 +1118,8 @@ void broxton_ddi_phy_init(struct drm_device *dev); void broxton_ddi_phy_uninit(struct drm_device *dev); void bxt_enable_dc9(struct drm_i915_private *dev_priv); void bxt_disable_dc9(struct drm_i915_private *dev_priv); +void skl_init_cdclk(struct drm_i915_private *dev_priv); +void skl_uninit_cdclk(struct drm_i915_private *dev_priv); void intel_dp_get_m_n(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); -- cgit v1.2.3 From ccbaefa09d73f8724b3040b80a2521454af61ae4 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:27 +0300 Subject: drm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The IBX 12bpc port enable toggle is only relevant when enabling the port, not when disabling it. Also this code doesn't actually toggle anything, and essentially just writes the port register one extra time. Furthermore CPT/PPT don't need such workarounds and yet we include them. Just kill it. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_hdmi.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index d04e6dc97fe5..91e152c15271 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -904,14 +904,6 @@ static void intel_disable_hdmi(struct intel_encoder *encoder) } } - /* HW workaround, need to toggle enable bit off and on for 12bpc, but - * we do this anyway which shows more stable in testing. - */ - if (HAS_PCH_SPLIT(dev)) { - I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); - POSTING_READ(intel_hdmi->hdmi_reg); - } - temp &= ~enable_bits; I915_WRITE(intel_hdmi->hdmi_reg, temp); -- cgit v1.2.3 From c52bcef72afafd89cc3bb71313581ad56eecf725 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:28 +0300 Subject: drm/i915: Remove the double register write from intel_disable_hdmi() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit IBX can have problems with the first write to the port register getting masked when enabling the port. We are trying to apply the workaround also when disabling the port where it's not needed, and we also try to apply it for CPT/PPT as well which don't need it. Just kill it. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes [danvet: Resolve conflict with the remove CHV if block.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_hdmi.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 91e152c15271..d148e09db901 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -908,14 +908,6 @@ static void intel_disable_hdmi(struct intel_encoder *encoder) I915_WRITE(intel_hdmi->hdmi_reg, temp); POSTING_READ(intel_hdmi->hdmi_reg); - - /* HW workaround, need to write this twice for issue that may result - * in first write getting masked. - */ - if (HAS_PCH_SPLIT(dev)) { - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); - } } static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) -- cgit v1.2.3 From 39e5fa8886f9d52e5ebbd70af3e0fd14492e8c60 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:29 +0300 Subject: drm/i915: Clarfify the DP code platform checks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit intel_dp.c is a mess with all the checks for different platform/PCH variants and ports. Try to clean it up by recognizing the following facts: - IVB port A, and CPT port B/C/D are always the special cases - VLV/CHV don't have port A - Using the same kind of logic everywhere makes things much easier to parse So let's move the IVB port A and PCH port B/C/D checks to be done first, and let the other cases fall through, and always check for these things using the same logic. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 46 ++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 0edc30516497..4c7c3f3558e1 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1570,7 +1570,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder) /* Split out the IBX/CPU vs CPT settings */ - if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { + if (IS_GEN7(dev) && port == PORT_A) { if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) intel_dp->DP |= DP_SYNC_HS_HIGH; if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) @@ -1581,7 +1581,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder) intel_dp->DP |= DP_ENHANCED_FRAMING; intel_dp->DP |= crtc->pipe << 29; - } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { + } else if (HAS_PCH_CPT(dev) && port != PORT_A) { + intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; + } else { if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) intel_dp->DP |= intel_dp->color_range; @@ -1594,14 +1596,10 @@ static void intel_dp_prepare(struct intel_encoder *encoder) if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) intel_dp->DP |= DP_ENHANCED_FRAMING; - if (!IS_CHERRYVIEW(dev)) { - if (crtc->pipe == 1) - intel_dp->DP |= DP_PIPEB_SELECT; - } else { + if (IS_CHERRYVIEW(dev)) intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); - } - } else { - intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; + else if (crtc->pipe == PIPE_B) + intel_dp->DP |= DP_PIPEB_SELECT; } } @@ -2185,13 +2183,9 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder, if (!(tmp & DP_PORT_EN)) return false; - if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { + if (IS_GEN7(dev) && port == PORT_A) { *pipe = PORT_TO_PIPE_CPT(tmp); - } else if (IS_CHERRYVIEW(dev)) { - *pipe = DP_PORT_TO_PIPE_CHV(tmp); - } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { - *pipe = PORT_TO_PIPE(tmp); - } else { + } else if (HAS_PCH_CPT(dev) && port != PORT_A) { u32 trans_sel; u32 trans_dp; int i; @@ -2220,6 +2214,10 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder, DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg); + } else if (IS_CHERRYVIEW(dev)) { + *pipe = DP_PORT_TO_PIPE_CHV(tmp); + } else { + *pipe = PORT_TO_PIPE(tmp); } return true; @@ -2240,24 +2238,24 @@ static void intel_dp_get_config(struct intel_encoder *encoder, pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; - if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { - if (tmp & DP_SYNC_HS_HIGH) + if (HAS_PCH_CPT(dev) && port != PORT_A) { + tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); + if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) flags |= DRM_MODE_FLAG_PHSYNC; else flags |= DRM_MODE_FLAG_NHSYNC; - if (tmp & DP_SYNC_VS_HIGH) + if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) flags |= DRM_MODE_FLAG_PVSYNC; else flags |= DRM_MODE_FLAG_NVSYNC; } else { - tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); - if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) + if (tmp & DP_SYNC_HS_HIGH) flags |= DRM_MODE_FLAG_PHSYNC; else flags |= DRM_MODE_FLAG_NHSYNC; - if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) + if (tmp & DP_SYNC_VS_HIGH) flags |= DRM_MODE_FLAG_PVSYNC; else flags |= DRM_MODE_FLAG_NVSYNC; @@ -2422,7 +2420,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, } I915_WRITE(DP_TP_CTL(port), temp); - } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { + } else if ((IS_GEN7(dev) && port == PORT_A) || + (HAS_PCH_CPT(dev) && port != PORT_A)) { *DP &= ~DP_LINK_TRAIN_MASK_CPT; switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { @@ -3864,7 +3863,8 @@ intel_dp_link_down(struct intel_dp *intel_dp) DRM_DEBUG_KMS("\n"); - if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { + if ((IS_GEN7(dev) && port == PORT_A) || + (HAS_PCH_CPT(dev) && port != PORT_A)) { DP &= ~DP_LINK_TRAIN_MASK_CPT; I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); } else { -- cgit v1.2.3 From adc289d749cf5b70bc5476045cc683f68898dba2 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:30 +0300 Subject: drm/i915: Clean up the CPT DP .get_hw_state() port readout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define a TRANS_DP_PIPE_TO_PORT() to make the CPT DP .get_hw_state() pipe readout neater. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_dp.c | 26 +++++--------------------- 2 files changed, 6 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c799b993c15d..85088a3cf295 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6440,6 +6440,7 @@ enum skl_disp_power_wells { #define TRANS_DP_PORT_SEL_D (2<<29) #define TRANS_DP_PORT_SEL_NONE (3<<29) #define TRANS_DP_PORT_SEL_MASK (3<<29) +#define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B) #define TRANS_DP_AUDIO_ONLY (1<<26) #define TRANS_DP_ENH_FRAMING (1<<18) #define TRANS_DP_8BPC (0<<9) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 4c7c3f3558e1..227e77ed879b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2186,28 +2186,12 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder, if (IS_GEN7(dev) && port == PORT_A) { *pipe = PORT_TO_PIPE_CPT(tmp); } else if (HAS_PCH_CPT(dev) && port != PORT_A) { - u32 trans_sel; - u32 trans_dp; - int i; - - switch (intel_dp->output_reg) { - case PCH_DP_B: - trans_sel = TRANS_DP_PORT_SEL_B; - break; - case PCH_DP_C: - trans_sel = TRANS_DP_PORT_SEL_C; - break; - case PCH_DP_D: - trans_sel = TRANS_DP_PORT_SEL_D; - break; - default: - return true; - } + enum pipe p; - for_each_pipe(dev_priv, i) { - trans_dp = I915_READ(TRANS_DP_CTL(i)); - if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { - *pipe = i; + for_each_pipe(dev_priv, p) { + u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); + if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { + *pipe = p; return true; } } -- cgit v1.2.3 From e3ef4479bb05dce255750ff10ec97c8675c0771b Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:31 +0300 Subject: drm/i915: Fix DP enhanced framing for CPT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently we're always enabling enhanced framing on CPT even if the sink doesn't support it. Fix this up by actaully looking at what the sink tells us. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 +-- drivers/gpu/drm/i915/intel_dp.c | 9 +++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 268043f65dd8..52de4110c8e9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4168,8 +4168,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) temp &= ~(TRANS_DP_PORT_SEL_MASK | TRANS_DP_SYNC_MASK | TRANS_DP_BPC_MASK); - temp |= (TRANS_DP_OUTPUT_ENABLE | - TRANS_DP_ENH_FRAMING); + temp |= TRANS_DP_OUTPUT_ENABLE; temp |= bpc << 9; /* same format but at 11:9 */ if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 227e77ed879b..d86e1f951666 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1582,7 +1582,16 @@ static void intel_dp_prepare(struct intel_encoder *encoder) intel_dp->DP |= crtc->pipe << 29; } else if (HAS_PCH_CPT(dev) && port != PORT_A) { + u32 trans_dp; + intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; + + trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) + trans_dp |= TRANS_DP_ENH_FRAMING; + else + trans_dp &= ~TRANS_DP_ENH_FRAMING; + I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); } else { if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) intel_dp->DP |= intel_dp->color_range; -- cgit v1.2.3 From e8504ee293f62b380b55b727d2da7aa429db8f8d Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:33 +0300 Subject: drm/i915: Write the SDVO reg twice on IBX MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On IBX the SDVO/HDMI register write may be masked when enabling the port, so it may need to written twice. The HDMI code does this, but the SDVO code does not. Add the workaround to the SDVO code as well. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_sdvo.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 0a0625761f42..e3e9c98eaf52 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -243,6 +243,14 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) if (intel_sdvo->sdvo_reg == PCH_SDVOB) { I915_WRITE(intel_sdvo->sdvo_reg, val); POSTING_READ(intel_sdvo->sdvo_reg); + /* + * HW workaround, need to write this twice for issue + * that may result in first write getting masked. + */ + if (HAS_PCH_IBX(dev)) { + I915_WRITE(intel_sdvo->sdvo_reg, val); + POSTING_READ(intel_sdvo->sdvo_reg); + } return; } -- cgit v1.2.3 From 1612c8bd4cef20dd06e8622bb8ab9bbe9f90c0e5 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:34 +0300 Subject: drm/i915: Fix the IBX transcoder B workarounds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently the IBX transcoder B workarounds are not working correctly. Well, the HDMI one seems to be working somewhat, but the DP one is definitely busted. After a bit of experimentation it looks like the best way to make this work is first disable the port on transcoder B, and then re-enable it transcoder A, and immediately disable it again. We can also clean up the code by noting that we can't be called without a valid crtc. And also note that port A on ILK does not need the workaround, so let's check for that one too. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 37 ++++++++++++++++------------- drivers/gpu/drm/i915/intel_hdmi.c | 50 ++++++++++++++++++--------------------- drivers/gpu/drm/i915/intel_sdvo.c | 41 +++++++++++++------------------- 3 files changed, 60 insertions(+), 68 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index d86e1f951666..abd442af4127 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3843,6 +3843,7 @@ static void intel_dp_link_down(struct intel_dp *intel_dp) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); enum port port = intel_dig_port->port; struct drm_device *dev = intel_dig_port->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -3859,34 +3860,38 @@ intel_dp_link_down(struct intel_dp *intel_dp) if ((IS_GEN7(dev) && port == PORT_A) || (HAS_PCH_CPT(dev) && port != PORT_A)) { DP &= ~DP_LINK_TRAIN_MASK_CPT; - I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); + DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; } else { if (IS_CHERRYVIEW(dev)) DP &= ~DP_LINK_TRAIN_MASK_CHV; else DP &= ~DP_LINK_TRAIN_MASK; - I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); + DP |= DP_LINK_TRAIN_PAT_IDLE; } + I915_WRITE(intel_dp->output_reg, DP); POSTING_READ(intel_dp->output_reg); - if (HAS_PCH_IBX(dev) && - I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { - /* Hardware workaround: leaving our transcoder select - * set to transcoder B while it's off will prevent the - * corresponding HDMI output on transcoder A. - * - * Combine this with another hardware workaround: - * transcoder select bit can only be cleared while the - * port is enabled. - */ - DP &= ~DP_PIPEB_SELECT; + DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); + I915_WRITE(intel_dp->output_reg, DP); + POSTING_READ(intel_dp->output_reg); + + /* + * HW workaround for IBX, we need to move the port + * to transcoder A after disabling it to allow the + * matching HDMI port to be enabled on transcoder A. + */ + if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { + /* always enable with pattern 1 (as per spec) */ + DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); + DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; + I915_WRITE(intel_dp->output_reg, DP); + POSTING_READ(intel_dp->output_reg); + + DP &= ~DP_PORT_EN; I915_WRITE(intel_dp->output_reg, DP); POSTING_READ(intel_dp->output_reg); } - DP &= ~DP_AUDIO_OUTPUT_ENABLE; - I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); - POSTING_READ(intel_dp->output_reg); msleep(intel_dp->panel_power_down_delay); } diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index d148e09db901..fb2dc84e1061 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -873,41 +873,37 @@ static void intel_disable_hdmi(struct intel_encoder *encoder) struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); u32 temp; - u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; if (crtc->config->has_audio) intel_audio_codec_disable(encoder); temp = I915_READ(intel_hdmi->hdmi_reg); - /* HW workaround for IBX, we need to move the port to transcoder A - * before disabling it. */ - if (HAS_PCH_IBX(dev)) { - struct drm_crtc *crtc = encoder->base.crtc; - int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; - - if (temp & SDVO_PIPE_B_SELECT) { - temp &= ~SDVO_PIPE_B_SELECT; - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); - - /* Again we need to write this twice. */ - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); - - /* Transcoder selection bits only update - * effectively on vblank. */ - if (crtc) - intel_wait_for_vblank(dev, pipe); - else - msleep(50); - } - } - - temp &= ~enable_bits; - + temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); I915_WRITE(intel_hdmi->hdmi_reg, temp); POSTING_READ(intel_hdmi->hdmi_reg); + + /* + * HW workaround for IBX, we need to move the port + * to transcoder A after disabling it to allow the + * matching DP port to be enabled on transcoder A. + */ + if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { + temp &= ~SDVO_PIPE_B_SELECT; + temp |= SDVO_ENABLE; + /* + * HW workaround, need to write this twice for issue + * that may result in first write getting masked. + */ + I915_WRITE(intel_hdmi->hdmi_reg, temp); + POSTING_READ(intel_hdmi->hdmi_reg); + I915_WRITE(intel_hdmi->hdmi_reg, temp); + POSTING_READ(intel_hdmi->hdmi_reg); + + temp &= ~SDVO_ENABLE; + I915_WRITE(intel_hdmi->hdmi_reg, temp); + POSTING_READ(intel_hdmi->hdmi_reg); + } } static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index e3e9c98eaf52..4a876914f212 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1437,6 +1437,7 @@ static void intel_disable_sdvo(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_sdvo *intel_sdvo = to_sdvo(encoder); + struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); u32 temp; intel_sdvo_set_active_outputs(intel_sdvo, 0); @@ -1445,32 +1446,22 @@ static void intel_disable_sdvo(struct intel_encoder *encoder) DRM_MODE_DPMS_OFF); temp = I915_READ(intel_sdvo->sdvo_reg); - if ((temp & SDVO_ENABLE) != 0) { - /* HW workaround for IBX, we need to move the port to - * transcoder A before disabling it. */ - if (HAS_PCH_IBX(encoder->base.dev)) { - struct drm_crtc *crtc = encoder->base.crtc; - int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; - - if (temp & SDVO_PIPE_B_SELECT) { - temp &= ~SDVO_PIPE_B_SELECT; - I915_WRITE(intel_sdvo->sdvo_reg, temp); - POSTING_READ(intel_sdvo->sdvo_reg); - - /* Again we need to write this twice. */ - I915_WRITE(intel_sdvo->sdvo_reg, temp); - POSTING_READ(intel_sdvo->sdvo_reg); - - /* Transcoder selection bits only update - * effectively on vblank. */ - if (crtc) - intel_wait_for_vblank(encoder->base.dev, pipe); - else - msleep(50); - } - } - intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); + temp &= ~SDVO_ENABLE; + intel_sdvo_write_sdvox(intel_sdvo, temp); + + /* + * HW workaround for IBX, we need to move the port + * to transcoder A after disabling it to allow the + * matching DP port to be enabled on transcoder A. + */ + if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { + temp &= ~SDVO_PIPE_B_SELECT; + temp |= SDVO_ENABLE; + intel_sdvo_write_sdvox(intel_sdvo, temp); + + temp &= ~SDVO_ENABLE; + intel_sdvo_write_sdvox(intel_sdvo, temp); } } -- cgit v1.2.3 From a4790cec3adf5eec91f397b1884706a71c70730f Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:35 +0300 Subject: drm/i915: Disable HDMI port after the pipe on PCH platforms MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BSpec says we should disable all ports after the pipe on PCH platforms. Do so. Fixes a pipe off timeout on ILK now caused by the transcoder B workaround. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_hdmi.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index fb2dc84e1061..e7e90610cc6f 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -874,9 +874,6 @@ static void intel_disable_hdmi(struct intel_encoder *encoder) struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); u32 temp; - if (crtc->config->has_audio) - intel_audio_codec_disable(encoder); - temp = I915_READ(intel_hdmi->hdmi_reg); temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); @@ -906,6 +903,29 @@ static void intel_disable_hdmi(struct intel_encoder *encoder) } } +static void g4x_disable_hdmi(struct intel_encoder *encoder) +{ + struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); + + if (crtc->config->has_audio) + intel_audio_codec_disable(encoder); + + intel_disable_hdmi(encoder); +} + +static void pch_disable_hdmi(struct intel_encoder *encoder) +{ + struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); + + if (crtc->config->has_audio) + intel_audio_codec_disable(encoder); +} + +static void pch_post_disable_hdmi(struct intel_encoder *encoder) +{ + intel_disable_hdmi(encoder); +} + static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) { struct drm_device *dev = intel_hdmi_to_dev(hdmi); @@ -1786,7 +1806,12 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) DRM_MODE_ENCODER_TMDS); intel_encoder->compute_config = intel_hdmi_compute_config; - intel_encoder->disable = intel_disable_hdmi; + if (HAS_PCH_SPLIT(dev)) { + intel_encoder->disable = pch_disable_hdmi; + intel_encoder->post_disable = pch_post_disable_hdmi; + } else { + intel_encoder->disable = g4x_disable_hdmi; + } intel_encoder->get_hw_state = intel_hdmi_get_hw_state; intel_encoder->get_config = intel_hdmi_get_config; if (IS_CHERRYVIEW(dev)) { -- cgit v1.2.3 From 3c65d1d1bb92ea959e8bce3eeae90fe5c3daa58a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:36 +0300 Subject: drm/i915: Disable SDVO port after the pipe on PCH platforms MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While at it also remove the redundant/unneeded w/a like done for hdmi already. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes [danvet: Mention that this also removes the unneeded w/a, as suggested by Jesse.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_sdvo.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 4a876914f212..d24ef75596a1 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1465,6 +1465,15 @@ static void intel_disable_sdvo(struct intel_encoder *encoder) } } +static void pch_disable_sdvo(struct intel_encoder *encoder) +{ +} + +static void pch_post_disable_sdvo(struct intel_encoder *encoder) +{ + intel_disable_sdvo(encoder); +} + static void intel_enable_sdvo(struct intel_encoder *encoder) { struct drm_device *dev = encoder->base.dev; @@ -1477,14 +1486,9 @@ static void intel_enable_sdvo(struct intel_encoder *encoder) bool success; temp = I915_READ(intel_sdvo->sdvo_reg); - if ((temp & SDVO_ENABLE) == 0) { - /* HW workaround for IBX, we need to move the port - * to transcoder A before disabling it, so restore it here. */ - if (HAS_PCH_IBX(dev)) - temp |= SDVO_PIPE_SEL(intel_crtc->pipe); + temp |= SDVO_ENABLE; + intel_sdvo_write_sdvox(intel_sdvo, temp); - intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); - } for (i = 0; i < 2; i++) intel_wait_for_vblank(dev, intel_crtc->pipe); @@ -2987,7 +2991,12 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) } intel_encoder->compute_config = intel_sdvo_compute_config; - intel_encoder->disable = intel_disable_sdvo; + if (HAS_PCH_SPLIT(dev)) { + intel_encoder->disable = pch_disable_sdvo; + intel_encoder->post_disable = pch_post_disable_sdvo; + } else { + intel_encoder->disable = intel_disable_sdvo; + } intel_encoder->pre_enable = intel_sdvo_pre_enable; intel_encoder->enable = intel_enable_sdvo; intel_encoder->get_hw_state = intel_sdvo_get_hw_state; -- cgit v1.2.3 From 1ea56e269e136544c0a76dc831c5edc27c47cb3c Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:37 +0300 Subject: drm/i915: Disable CRT port after pipe on PCH platforms MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Follow the BSpec sequence for the CRT port as well on PCH platforms, ie. disable the pipe before the port. Didn't bother looking at DDI in detail yet, so leave that one be even though the CRT is a PCH port there. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_crt.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 93bb5159d093..521af2c069cb 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -207,6 +207,14 @@ static void intel_disable_crt(struct intel_encoder *encoder) intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); } +static void pch_disable_crt(struct intel_encoder *encoder) +{ +} + +static void pch_post_disable_crt(struct intel_encoder *encoder) +{ + intel_disable_crt(encoder); +} static void hsw_crt_post_disable(struct intel_encoder *encoder) { @@ -888,7 +896,12 @@ void intel_crt_init(struct drm_device *dev) crt->adpa_reg = ADPA; crt->base.compute_config = intel_crt_compute_config; - crt->base.disable = intel_disable_crt; + if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) { + crt->base.disable = pch_disable_crt; + crt->base.post_disable = pch_post_disable_crt; + } else { + crt->base.disable = intel_disable_crt; + } crt->base.enable = intel_enable_crt; if (I915_HAS_HOTPLUG(dev)) crt->base.hpd_pin = HPD_CRT; -- cgit v1.2.3 From 5a74f70a733fc79a37ee8462ae59de6897d17eed Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 5 May 2015 17:17:38 +0300 Subject: drm/i915: Disable FDI RX/TX before the ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bspec says we should disable the FDI RX/TX before disabling the PCH ports. Do so. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 52de4110c8e9..db665922edc2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5111,13 +5111,14 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) ironlake_pfit_disable(intel_crtc); + if (intel_crtc->config->has_pch_encoder) + ironlake_fdi_disable(crtc); + for_each_encoder_on_crtc(dev, crtc, encoder) if (encoder->post_disable) encoder->post_disable(encoder); if (intel_crtc->config->has_pch_encoder) { - ironlake_fdi_disable(crtc); - ironlake_disable_pch_transcoder(dev_priv, pipe); if (HAS_PCH_CPT(dev)) { -- cgit v1.2.3 From 7ad0dbab20678709ca268afa54189cf49b058f15 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 19 May 2015 20:32:55 +0300 Subject: drm/i915: Use ilk_init_lp_watermarks() on BDW MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We're not using ilk_init_lp_watermarks() on BDW for some reason. Probably due to the BDW patches and the relevant WM patches landing roughlly at the same time. Fix it up. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6414b27692d4..cfc748086088 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6175,9 +6175,7 @@ static void broadwell_init_clock_gating(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; enum pipe pipe; - I915_WRITE(WM3_LP_ILK, 0); - I915_WRITE(WM2_LP_ILK, 0); - I915_WRITE(WM1_LP_ILK, 0); + ilk_init_lp_watermarks(dev); /* WaSwitchSolVfFArbitrationPriority:bdw */ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); -- cgit v1.2.3 From 4d487cff19975d65234902e4abed8724a7b5b94b Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 19 May 2015 20:32:56 +0300 Subject: drm/i915: Move WaProgramL3SqcReg1Default:bdw to init_clock_gating() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GEN8_L3SQCREG1 isn't saved in the context (verified by going through a context dump), and so we shouldn't be using the ring w/a code to initialize it. Also Bspec explicitly talks about MMIO and writing it with the CPU. Additionally there's another w/a WaTempDisableDOPClkGating:bdw which tells us to disable DOP clock gating around the GEN8_L3SQCREG1 write to make sure everyone notices the change. So let's do that as well. Cc: Rodrigo Vivi Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.c | 3 --- 2 files changed, 10 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index cfc748086088..85ba52bacfea 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6174,6 +6174,7 @@ static void broadwell_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; enum pipe pipe; + uint32_t misccpctl; ilk_init_lp_watermarks(dev); @@ -6204,6 +6205,15 @@ static void broadwell_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); + /* + * WaProgramL3SqcReg1Default:bdw + * WaTempDisableDOPClkGating:bdw + */ + misccpctl = I915_READ(GEN7_MISCCPCTL); + I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); + I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); + I915_WRITE(GEN7_MISCCPCTL, misccpctl); + lpt_init_clock_gating(dev); } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 052265ae8de1..d934f857394d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -853,9 +853,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4); - /* WaProgramL3SqcReg1Default:bdw */ - WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); - return 0; } -- cgit v1.2.3 From 6d50b0650fb46050d883d1b439a8681178cb2326 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 19 May 2015 20:32:57 +0300 Subject: drm/i915: Enable GTT caching on gen8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GTT caching was disabled by default on gen8 due to not working with big pages. Some information suggests that it got fixed, but still GTT caching has been left disabled by default. Or could be it just meant that the default was changed to off, and hence the problem got solved. Enable GTT caching in the hopes of some performance increase. Whether or not the big pages issue has been fixed is irrelevant at this stage since we don't use big pages. This gives me a 1-2% improvement in xonotic on my BSW. Haven't tried BDW, but supposedly it has larger TLBs so might not benefit as much. On HSW GTT caching is enabled by default. Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++++ 2 files changed, 15 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 85088a3cf295..607766d0a15d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1461,6 +1461,8 @@ enum skl_disp_power_wells { #define RING_HWS_PGA(base) ((base)+0x80) #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) +#define HSW_GTT_CACHE_EN 0x4024 +#define GTT_CACHE_EN_ALL 0xF0007FFF #define GEN7_WR_WATERMARK 0x4028 #define GEN7_GFX_PRIO_CTRL 0x402C #define ARB_MODE 0x4030 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 85ba52bacfea..84809a67fac8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6214,6 +6214,13 @@ static void broadwell_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); I915_WRITE(GEN7_MISCCPCTL, misccpctl); + /* + * WaGttCachingOffByDefault:bdw + * GTT cache may not work with big pages, so if those + * are ever enabled GTT cache may need to be disabled. + */ + I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); + lpt_init_clock_gating(dev); } @@ -6489,6 +6496,12 @@ static void cherryview_init_clock_gating(struct drm_device *dev) /* WaDisableSDEUnitClockGating:chv */ I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); + + /* + * GTT cache may not work with big pages, so if those + * are ever enabled GTT cache may need to be disabled. + */ + I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); } static void g4x_init_clock_gating(struct drm_device *dev) -- cgit v1.2.3 From 225c228a028388b215e1f8a18546af2c2802bbb5 Mon Sep 17 00:00:00 2001 From: Chandra Konduru Date: Mon, 18 May 2015 16:18:44 -0700 Subject: drm/i915/skl: don't fail colorkey + scaler request MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is a mplayer video failure reported with xv. This is because there is a request to do both plane scaling and colorkey. Because skl hw doesn't support plane scaling and colorkey at the same time, request is failed which is expected behavior. To make xv operate, this patch allows colorkey continue to work without using scaler. Then behavior would be similar to platforms without plane scaler support. Signed-off-by: Chandra Konduru Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90449 [danvet: change can_scale to bool as requested by Ville.] Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 14 +++++++++----- drivers/gpu/drm/i915/intel_sprite.c | 30 +++++++++++++++++++++--------- 2 files changed, 30 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index db665922edc2..657a33366e92 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4502,9 +4502,10 @@ skl_update_scaler_users( } /* check colorkey */ - if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) { - DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed", - intel_plane->base.base.id); + if (WARN_ON(intel_plane && + intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) { + DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey", + intel_plane->base.base.id, src_w, src_h, dst_w, dst_h); return -EINVAL; } @@ -13261,8 +13262,11 @@ intel_check_primary_plane(struct drm_plane *plane, intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; if (INTEL_INFO(dev)->gen >= 9) { - min_scale = 1; - max_scale = skl_max_scale(intel_crtc, crtc_state); + /* use scaler when colorkey is not required */ + if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) { + min_scale = 1; + max_scale = skl_max_scale(intel_crtc, crtc_state); + } can_position = true; } diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 3f70d59dc712..2a90308cc9c0 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -770,6 +770,7 @@ intel_check_sprite_plane(struct drm_plane *plane, const struct drm_rect *clip = &state->clip; int hscale, vscale; int max_scale, min_scale; + bool can_scale; int pixel_size; int ret; @@ -794,18 +795,29 @@ intel_check_sprite_plane(struct drm_plane *plane, return -EINVAL; } + /* setup can_scale, min_scale, max_scale */ + if (INTEL_INFO(dev)->gen >= 9) { + /* use scaler when colorkey is not required */ + if (intel_plane->ckey.flags == I915_SET_COLORKEY_NONE) { + can_scale = 1; + min_scale = 1; + max_scale = skl_max_scale(intel_crtc, crtc_state); + } else { + can_scale = 0; + min_scale = DRM_PLANE_HELPER_NO_SCALING; + max_scale = DRM_PLANE_HELPER_NO_SCALING; + } + } else { + can_scale = intel_plane->can_scale; + max_scale = intel_plane->max_downscale << 16; + min_scale = intel_plane->can_scale ? 1 : (1 << 16); + } + /* * FIXME the following code does a bunch of fuzzy adjustments to the * coordinates and sizes. We probably need some way to decide whether * more strict checking should be done instead. */ - max_scale = intel_plane->max_downscale << 16; - min_scale = intel_plane->can_scale ? 1 : (1 << 16); - - if (INTEL_INFO(dev)->gen >= 9) { - min_scale = 1; - max_scale = skl_max_scale(intel_crtc, crtc_state); - } drm_rect_rotate(src, fb->width << 16, fb->height << 16, state->base.rotation); @@ -876,7 +888,7 @@ intel_check_sprite_plane(struct drm_plane *plane, * Must keep src and dst the * same if we can't scale. */ - if (!intel_plane->can_scale) + if (!can_scale) crtc_w &= ~1; if (crtc_w == 0) @@ -888,7 +900,7 @@ intel_check_sprite_plane(struct drm_plane *plane, if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { unsigned int width_bytes; - WARN_ON(!intel_plane->can_scale); + WARN_ON(!can_scale); /* FIXME interlacing min height is 6 */ -- cgit v1.2.3 From 9a0c1e2770b839b806bae6bc8f93001f86bc0cf3 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 21 May 2015 21:01:45 +0100 Subject: drm/i915: Use the correct destructor for freeing requests on error After allocating from the slab cache, we then need to free the request back into the slab cache upon error (and not call kfree as that leads to eventual memory corruption). Fixes regression from commit efab6d8dd158fdccbe6a030f89fbf9ca0a9564e4 Author: Chris Wilson Date: Tue Apr 7 16:20:57 2015 +0100 drm/i915: Use a separate slab for requests Signed-off-by: Chris Wilson Cc: Daniel Vetter Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 50e49a3d7e51..0ce3e4b3059e 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2653,10 +2653,8 @@ int i915_gem_request_alloc(struct intel_engine_cs *ring, req->i915 = dev_priv; ret = i915_gem_get_seqno(ring->dev, &req->seqno); - if (ret) { - kfree(req); - return ret; - } + if (ret) + goto err; req->ring = ring; @@ -2664,13 +2662,15 @@ int i915_gem_request_alloc(struct intel_engine_cs *ring, ret = intel_logical_ring_alloc_request_extras(req, ctx); else ret = intel_ring_alloc_request_extras(req); - if (ret) { - kfree(req); - return ret; - } + if (ret) + goto err; ring->outstanding_lazy_request = req; return 0; + +err: + kmem_cache_free(dev_priv->requests, req); + return ret; } struct drm_i915_gem_request * -- cgit v1.2.3 From d0bc54f2f012d8c8c3b4315f51f408ff3d938031 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 21 May 2015 21:01:48 +0100 Subject: drm/i915: Introduce DRM_I915_THROTTLE_JIFFIES As Daniel commented on commit b7ffe1362c5f468b853223acc9268804aa92afc8 Author: Chris Wilson Date: Mon Apr 27 13:41:24 2015 +0100 drm/i915: Free RPS boosts for all laggards it is better to be explicit when sharing hardcoded values such as throttle/boost timeouts. Make it so! Signed-off-by: Chris Wilson Cc: Daniel Vetter Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 6 ++++++ drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 44d592f3b67c..1038f5c7f15b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -279,6 +279,12 @@ struct drm_i915_file_private { struct { spinlock_t lock; struct list_head request_list; +/* 20ms is a fairly arbitrary limit (greater than the average frame time) + * chosen to prevent the CPU getting more than a frame ahead of the GPU + * (when using lax throttling for the frontbuffer). We also use it to + * offer free GPU waitboosts for severely congested workloads. + */ +#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) } mm; struct idr context_idr; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 0ce3e4b3059e..cc206f199d66 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4239,7 +4239,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) { struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_file_private *file_priv = file->driver_priv; - unsigned long recent_enough = jiffies - msecs_to_jiffies(20); + unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; struct drm_i915_gem_request *request, *target = NULL; unsigned reset_counter; int ret; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 84809a67fac8..55d993110d51 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4158,7 +4158,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv, /* Force a RPS boost (and don't count it against the client) if * the GPU is severely congested. */ - if (rps && time_after(jiffies, submitted + msecs_to_jiffies(20))) + if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) rps = NULL; mutex_lock(&dev_priv->rps.hw_lock); -- cgit v1.2.3 From dd0150026901b3fc73bd76bb423bacf5cc10393d Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 22 May 2015 10:25:57 +0200 Subject: drm/panel: simple: Add support for LG LB070WV8 800x480 7" panel This adds support for the LG LB070WV8 7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Heiko Schocher Signed-off-by: Thierry Reding --- .../devicetree/bindings/panel/lg,lb070wv8.txt | 7 ++++++ drivers/gpu/drm/panel/panel-simple.c | 27 ++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/lg,lb070wv8.txt (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/panel/lg,lb070wv8.txt b/Documentation/devicetree/bindings/panel/lg,lb070wv8.txt new file mode 100644 index 000000000000..a7588e5259cf --- /dev/null +++ b/Documentation/devicetree/bindings/panel/lg,lb070wv8.txt @@ -0,0 +1,7 @@ +LG 7" (800x480 pixels) TFT LCD panel + +Required properties: +- compatible: should be "lg,lb070wv8" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 30904a9b2a4c..a06d9d353bec 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -872,6 +872,30 @@ static const struct panel_desc innolux_zj070na_01p = { }, }; +static const struct drm_display_mode lg_lb070wv8_mode = { + .clock = 33246, + .hdisplay = 800, + .hsync_start = 800 + 88, + .hsync_end = 800 + 88 + 80, + .htotal = 800 + 88 + 80 + 88, + .vdisplay = 480, + .vsync_start = 480 + 10, + .vsync_end = 480 + 10 + 25, + .vtotal = 480 + 10 + 25 + 10, + .vrefresh = 60, +}; + +static const struct panel_desc lg_lb070wv8 = { + .modes = &lg_lb070wv8_mode, + .num_modes = 1, + .bpc = 16, + .size = { + .width = 151, + .height = 91, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, +}; + static const struct drm_display_mode lg_lp129qe_mode = { .clock = 285250, .hdisplay = 2560, @@ -1055,6 +1079,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "innolux,zj070na-01p", .data = &innolux_zj070na_01p, + }, { + .compatible = "lg,lb070wv8", + .data = &lg_lb070wv8, }, { .compatible = "lg,lp129qe", .data = &lg_lp129qe, -- cgit v1.2.3 From f102c16ebbeb40ba2f2a7ba4703ed3e2fc013c68 Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Fri, 22 May 2015 13:34:44 +0100 Subject: drm: kerneldoc fixes for blob properties Change '@param foo' to '@foo:' to fit kerneldoc style. 672cb1d6ae mistakenly added an extra parameter to the kerneldoc for drm_property_unreference_blob which wasn't actually present. Signed-off-by: Daniel Stone Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 4059f065c854..7e5085fe4b75 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -4270,7 +4270,7 @@ EXPORT_SYMBOL(drm_property_create_blob); * * Internal free function for blob properties; must not be used directly. * - * @param kref Reference + * @kref: Reference */ static void drm_property_free_blob(struct kref *kref) { @@ -4290,7 +4290,7 @@ static void drm_property_free_blob(struct kref *kref) * * Drop a reference on a blob property. May free the object. * - * @param blob Pointer to blob property + * @blob: Pointer to blob property */ void drm_property_unreference_blob(struct drm_property_blob *blob) { @@ -4318,8 +4318,7 @@ EXPORT_SYMBOL(drm_property_unreference_blob); * Drop a reference on a blob property. May free the object. This must be * called with blob_lock held. * - * @param dev Device the blob was created on - * @param blob Pointer to blob property + * @blob: Pointer to blob property */ static void drm_property_unreference_blob_locked(struct drm_property_blob *blob) { @@ -4336,7 +4335,7 @@ static void drm_property_unreference_blob_locked(struct drm_property_blob *blob) * * Take a new reference on an existing blob property. * - * @param blob Pointer to blob property + * @blob: Pointer to blob property */ struct drm_property_blob *drm_property_reference_blob(struct drm_property_blob *blob) { -- cgit v1.2.3 From 9f658b7b62e7aefc1ee067136126eca3f58cabfd Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Fri, 22 May 2015 13:34:45 +0100 Subject: drm/crtc_helper: Replace open-coded CRTC state helpers Rather than open-coding our own CRTC state helpers, use the atomic helpers added in f5e7840b0c, and make our freeing behaviour consistent as well. Signed-off-by: Daniel Stone Tested-by: Sean Paul Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc_helper.c | 42 ++++++++++++++++++--------------------- 1 file changed, 19 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index f2f42b17967a..9297a61a7c95 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -927,14 +927,15 @@ int drm_helper_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mod if (crtc->funcs->atomic_duplicate_state) crtc_state = crtc->funcs->atomic_duplicate_state(crtc); - else if (crtc->state) - crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), - GFP_KERNEL); - else + else { crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); - if (!crtc_state) - return -ENOMEM; - crtc_state->crtc = crtc; + if (!crtc_state) + return -ENOMEM; + if (crtc->state) + __drm_atomic_helper_crtc_duplicate_state(crtc, crtc_state); + else + crtc_state->crtc = crtc; + } crtc_state->enable = true; crtc_state->planes_changed = true; @@ -944,30 +945,25 @@ int drm_helper_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mod if (crtc_funcs->atomic_check) { ret = crtc_funcs->atomic_check(crtc, crtc_state); - if (ret) { - if (crtc->funcs->atomic_destroy_state) { - crtc->funcs->atomic_destroy_state(crtc, - crtc_state); - } else { - kfree(crtc_state); - } - - return ret; - } + if (ret) + goto out; } swap(crtc->state, crtc_state); crtc_funcs->mode_set_nofb(crtc); - if (crtc_state) { - if (crtc->funcs->atomic_destroy_state) - crtc->funcs->atomic_destroy_state(crtc, crtc_state); - else - kfree(crtc_state); + ret = drm_helper_crtc_mode_set_base(crtc, x, y, old_fb); + +out: + if (crtc->funcs->atomic_destroy_state) + crtc->funcs->atomic_destroy_state(crtc, crtc_state); + else { + __drm_atomic_helper_crtc_destroy_state(crtc, crtc_state); + kfree(crtc_state); } - return drm_helper_crtc_mode_set_base(crtc, x, y, old_fb); + return ret; } EXPORT_SYMBOL(drm_helper_crtc_mode_set); -- cgit v1.2.3 From 7dec9a9648f825a0698fd875d2834b597f122bd6 Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Fri, 22 May 2015 13:34:47 +0100 Subject: drm/mode: Validate modes inside drm_crtc_convert_umode The only user of convert_umode was also performing mode validation, so do that in the same place. Signed-off-by: Daniel Stone Tested-by: Sean Paul Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 7e5085fe4b75..baad4e856006 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -1785,11 +1785,15 @@ static void drm_crtc_convert_to_umode(struct drm_mode_modeinfo *out, static int drm_crtc_convert_umode(struct drm_display_mode *out, const struct drm_mode_modeinfo *in) { - if (in->clock > INT_MAX || in->vrefresh > INT_MAX) - return -ERANGE; + int ret = -EINVAL; + + if (in->clock > INT_MAX || in->vrefresh > INT_MAX) { + ret = -ERANGE; + goto out; + } if ((in->flags & DRM_MODE_FLAG_3D_MASK) > DRM_MODE_FLAG_3D_MAX) - return -EINVAL; + goto out; out->clock = in->clock; out->hdisplay = in->hdisplay; @@ -1808,7 +1812,14 @@ static int drm_crtc_convert_umode(struct drm_display_mode *out, strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN); out->name[DRM_DISPLAY_MODE_LEN-1] = 0; - return 0; + out->status = drm_mode_validate_basic(out); + if (out->status != MODE_OK) + goto out; + + ret = 0; + +out: + return ret; } /** @@ -2821,12 +2832,6 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, goto out; } - mode->status = drm_mode_validate_basic(mode); - if (mode->status != MODE_OK) { - ret = -EINVAL; - goto out; - } - drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); /* -- cgit v1.2.3 From 934a8a899a7275ed187810fe9a15a93397e88c6b Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Fri, 22 May 2015 13:34:48 +0100 Subject: drm/mode: Unstatic kernel-userspace mode conversion Move the drm_display_mode <-> drm_mode_modeinfo conversion functions from drm_crtc.c to drm_modes.c, and make them non-static so that others can use them. Signed-off-by: Daniel Stone Tested-by: Sean Paul Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 95 ++------------------------------------------- drivers/gpu/drm/drm_modes.c | 87 +++++++++++++++++++++++++++++++++++++++++ include/drm/drm_modes.h | 4 ++ 3 files changed, 95 insertions(+), 91 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index baad4e856006..f6b0332aad7f 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -1735,93 +1735,6 @@ void drm_reinit_primary_mode_group(struct drm_device *dev) } EXPORT_SYMBOL(drm_reinit_primary_mode_group); -/** - * drm_crtc_convert_to_umode - convert a drm_display_mode into a modeinfo - * @out: drm_mode_modeinfo struct to return to the user - * @in: drm_display_mode to use - * - * Convert a drm_display_mode into a drm_mode_modeinfo structure to return to - * the user. - */ -static void drm_crtc_convert_to_umode(struct drm_mode_modeinfo *out, - const struct drm_display_mode *in) -{ - WARN(in->hdisplay > USHRT_MAX || in->hsync_start > USHRT_MAX || - in->hsync_end > USHRT_MAX || in->htotal > USHRT_MAX || - in->hskew > USHRT_MAX || in->vdisplay > USHRT_MAX || - in->vsync_start > USHRT_MAX || in->vsync_end > USHRT_MAX || - in->vtotal > USHRT_MAX || in->vscan > USHRT_MAX, - "timing values too large for mode info\n"); - - out->clock = in->clock; - out->hdisplay = in->hdisplay; - out->hsync_start = in->hsync_start; - out->hsync_end = in->hsync_end; - out->htotal = in->htotal; - out->hskew = in->hskew; - out->vdisplay = in->vdisplay; - out->vsync_start = in->vsync_start; - out->vsync_end = in->vsync_end; - out->vtotal = in->vtotal; - out->vscan = in->vscan; - out->vrefresh = in->vrefresh; - out->flags = in->flags; - out->type = in->type; - strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN); - out->name[DRM_DISPLAY_MODE_LEN-1] = 0; -} - -/** - * drm_crtc_convert_umode - convert a modeinfo into a drm_display_mode - * @out: drm_display_mode to return to the user - * @in: drm_mode_modeinfo to use - * - * Convert a drm_mode_modeinfo into a drm_display_mode structure to return to - * the caller. - * - * Returns: - * Zero on success, negative errno on failure. - */ -static int drm_crtc_convert_umode(struct drm_display_mode *out, - const struct drm_mode_modeinfo *in) -{ - int ret = -EINVAL; - - if (in->clock > INT_MAX || in->vrefresh > INT_MAX) { - ret = -ERANGE; - goto out; - } - - if ((in->flags & DRM_MODE_FLAG_3D_MASK) > DRM_MODE_FLAG_3D_MAX) - goto out; - - out->clock = in->clock; - out->hdisplay = in->hdisplay; - out->hsync_start = in->hsync_start; - out->hsync_end = in->hsync_end; - out->htotal = in->htotal; - out->hskew = in->hskew; - out->vdisplay = in->vdisplay; - out->vsync_start = in->vsync_start; - out->vsync_end = in->vsync_end; - out->vtotal = in->vtotal; - out->vscan = in->vscan; - out->vrefresh = in->vrefresh; - out->flags = in->flags; - out->type = in->type; - strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN); - out->name[DRM_DISPLAY_MODE_LEN-1] = 0; - - out->status = drm_mode_validate_basic(out); - if (out->status != MODE_OK) - goto out; - - ret = 0; - -out: - return ret; -} - /** * drm_mode_getresources - get graphics configuration * @dev: drm device for the ioctl @@ -2048,7 +1961,7 @@ int drm_mode_getcrtc(struct drm_device *dev, crtc_resp->x = crtc->primary->state->src_x >> 16; crtc_resp->y = crtc->primary->state->src_y >> 16; if (crtc->state->enable) { - drm_crtc_convert_to_umode(&crtc_resp->mode, &crtc->state->mode); + drm_mode_convert_to_umode(&crtc_resp->mode, &crtc->state->mode); crtc_resp->mode_valid = 1; } else { @@ -2058,7 +1971,7 @@ int drm_mode_getcrtc(struct drm_device *dev, crtc_resp->x = crtc->x; crtc_resp->y = crtc->y; if (crtc->enabled) { - drm_crtc_convert_to_umode(&crtc_resp->mode, &crtc->mode); + drm_mode_convert_to_umode(&crtc_resp->mode, &crtc->mode); crtc_resp->mode_valid = 1; } else { @@ -2215,7 +2128,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data, if (!drm_mode_expose_to_userspace(mode, file_priv)) continue; - drm_crtc_convert_to_umode(&u_mode, mode); + drm_mode_convert_to_umode(&u_mode, mode); if (copy_to_user(mode_ptr + copied, &u_mode, sizeof(u_mode))) { ret = -EFAULT; @@ -2826,7 +2739,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, goto out; } - ret = drm_crtc_convert_umode(mode, &crtc_req->mode); + ret = drm_mode_convert_umode(mode, &crtc_req->mode); if (ret) { DRM_DEBUG_KMS("Invalid mode\n"); goto out; diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 213b11ea69b5..cd74a0953f42 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -1405,3 +1405,90 @@ drm_mode_create_from_cmdline_mode(struct drm_device *dev, return mode; } EXPORT_SYMBOL(drm_mode_create_from_cmdline_mode); + +/** + * drm_crtc_convert_to_umode - convert a drm_display_mode into a modeinfo + * @out: drm_mode_modeinfo struct to return to the user + * @in: drm_display_mode to use + * + * Convert a drm_display_mode into a drm_mode_modeinfo structure to return to + * the user. + */ +void drm_mode_convert_to_umode(struct drm_mode_modeinfo *out, + const struct drm_display_mode *in) +{ + WARN(in->hdisplay > USHRT_MAX || in->hsync_start > USHRT_MAX || + in->hsync_end > USHRT_MAX || in->htotal > USHRT_MAX || + in->hskew > USHRT_MAX || in->vdisplay > USHRT_MAX || + in->vsync_start > USHRT_MAX || in->vsync_end > USHRT_MAX || + in->vtotal > USHRT_MAX || in->vscan > USHRT_MAX, + "timing values too large for mode info\n"); + + out->clock = in->clock; + out->hdisplay = in->hdisplay; + out->hsync_start = in->hsync_start; + out->hsync_end = in->hsync_end; + out->htotal = in->htotal; + out->hskew = in->hskew; + out->vdisplay = in->vdisplay; + out->vsync_start = in->vsync_start; + out->vsync_end = in->vsync_end; + out->vtotal = in->vtotal; + out->vscan = in->vscan; + out->vrefresh = in->vrefresh; + out->flags = in->flags; + out->type = in->type; + strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN); + out->name[DRM_DISPLAY_MODE_LEN-1] = 0; +} + +/** + * drm_crtc_convert_umode - convert a modeinfo into a drm_display_mode + * @out: drm_display_mode to return to the user + * @in: drm_mode_modeinfo to use + * + * Convert a drm_mode_modeinfo into a drm_display_mode structure to return to + * the caller. + * + * Returns: + * Zero on success, negative errno on failure. + */ +int drm_mode_convert_umode(struct drm_display_mode *out, + const struct drm_mode_modeinfo *in) +{ + int ret = -EINVAL; + + if (in->clock > INT_MAX || in->vrefresh > INT_MAX) { + ret = -ERANGE; + goto out; + } + + if ((in->flags & DRM_MODE_FLAG_3D_MASK) > DRM_MODE_FLAG_3D_MAX) + goto out; + + out->clock = in->clock; + out->hdisplay = in->hdisplay; + out->hsync_start = in->hsync_start; + out->hsync_end = in->hsync_end; + out->htotal = in->htotal; + out->hskew = in->hskew; + out->vdisplay = in->vdisplay; + out->vsync_start = in->vsync_start; + out->vsync_end = in->vsync_end; + out->vtotal = in->vtotal; + out->vscan = in->vscan; + out->vrefresh = in->vrefresh; + out->flags = in->flags; + out->type = in->type; + strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN); + out->name[DRM_DISPLAY_MODE_LEN-1] = 0; + + out->status = drm_mode_validate_basic(out); + if (out->status != MODE_OK) + goto out; + + ret = 0; + +out: + return ret; +} \ No newline at end of file diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h index 0616188c7801..08a8cac9e555 100644 --- a/include/drm/drm_modes.h +++ b/include/drm/drm_modes.h @@ -182,6 +182,10 @@ struct drm_cmdline_mode; struct drm_display_mode *drm_mode_create(struct drm_device *dev); void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode); +void drm_mode_convert_to_umode(struct drm_mode_modeinfo *out, + const struct drm_display_mode *in); +int drm_mode_convert_umode(struct drm_display_mode *out, + const struct drm_mode_modeinfo *in); void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode); void drm_mode_debug_printmodeline(const struct drm_display_mode *mode); -- cgit v1.2.3 From 99531d9bb76c649df15311c717deefdff7cc5b7b Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Fri, 22 May 2015 13:34:49 +0100 Subject: drm: Allow creating blob properties without copy Make the data parameter to drm_property_create_blob optional; if omitted, the copy will be skipped and the data will be empty. Signed-off-by: Daniel Stone Reviewed-by: Maarten Lankhorst Tested-by: Sean Paul Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index f6b0332aad7f..0844108e19e0 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -4145,6 +4145,16 @@ done: return ret; } +/** + * drm_property_create_blob - Create new blob property + * + * Creates a new blob property for a specified DRM device, optionally + * copying data. + * + * @dev: DRM device to create property for + * @length: Length to allocate for blob data + * @data: If specified, copies data into blob + */ struct drm_property_blob * drm_property_create_blob(struct drm_device *dev, size_t length, const void *data) @@ -4152,7 +4162,7 @@ drm_property_create_blob(struct drm_device *dev, size_t length, struct drm_property_blob *blob; int ret; - if (!length || !data) + if (!length) return NULL; blob = kzalloc(sizeof(struct drm_property_blob)+length, GFP_KERNEL); @@ -4162,7 +4172,8 @@ drm_property_create_blob(struct drm_device *dev, size_t length, blob->length = length; blob->dev = dev; - memcpy(blob->data, data, length); + if (data) + memcpy(blob->data, data, length); mutex_lock(&dev->mode_config.blob_lock); -- cgit v1.2.3 From 10e8cb7e79391071b950a28a4d85790dd38fb714 Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Fri, 22 May 2015 13:34:50 +0100 Subject: drm: Return error value from blob creation Change drm_property_create_blob to return an ERR_PTR-encoded error on failure, so we can pass the failure reason down. Signed-off-by: Daniel Stone Cc: Maarten Lankhorst Tested-by: Sean Paul Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 0844108e19e0..f661589b1dea 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -4154,6 +4154,10 @@ done: * @dev: DRM device to create property for * @length: Length to allocate for blob data * @data: If specified, copies data into blob + * + * Returns: + * New blob property with a single reference on success, or an ERR_PTR + * value on failure. */ struct drm_property_blob * drm_property_create_blob(struct drm_device *dev, size_t length, @@ -4163,11 +4167,11 @@ drm_property_create_blob(struct drm_device *dev, size_t length, int ret; if (!length) - return NULL; + return ERR_PTR(-EINVAL); blob = kzalloc(sizeof(struct drm_property_blob)+length, GFP_KERNEL); if (!blob) - return NULL; + return ERR_PTR(-ENOMEM); blob->length = length; blob->dev = dev; @@ -4181,7 +4185,7 @@ drm_property_create_blob(struct drm_device *dev, size_t length, if (ret) { kfree(blob); mutex_unlock(&dev->mode_config.blob_lock); - return NULL; + return ERR_PTR(-EINVAL); } kref_init(&blob->refcount); @@ -4370,8 +4374,8 @@ static int drm_property_replace_global_blob(struct drm_device *dev, if (length && data) { new_blob = drm_property_create_blob(dev, length, data); - if (!new_blob) - return -EINVAL; + if (IS_ERR(new_blob)) + return PTR_ERR(new_blob); } /* This does not need to be synchronised with blob_lock, as the -- cgit v1.2.3 From e2f5d2ea479b9b2619965d43db70939589afe43a Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Fri, 22 May 2015 13:34:51 +0100 Subject: drm/mode: Add user blob-creation ioctl Add an ioctl which allows users to create blob properties from supplied data. Currently this only supports modes, creating a drm_display_mode from the userspace drm_mode_modeinfo. v2: Removed size/type checks. Rebased on new patches to allow error propagation from create_blob, as well as avoiding double-allocation. Signed-off-by: Daniel Stone Reviewed-by: Maarten Lankhorst Tested-by: Sean Paul Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 139 +++++++++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/drm_fops.c | 5 +- drivers/gpu/drm/drm_ioctl.c | 2 + include/drm/drmP.h | 4 ++ include/drm/drm_crtc.h | 9 ++- include/uapi/drm/drm.h | 2 + include/uapi/drm/drm_mode.h | 20 +++++++ 7 files changed, 176 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index f661589b1dea..e548c50edc94 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -4173,6 +4173,9 @@ drm_property_create_blob(struct drm_device *dev, size_t length, if (!blob) return ERR_PTR(-ENOMEM); + /* This must be explicitly initialised, so we can safely call list_del + * on it in the removal handler, even if it isn't in a file list. */ + INIT_LIST_HEAD(&blob->head_file); blob->length = length; blob->dev = dev; @@ -4190,7 +4193,8 @@ drm_property_create_blob(struct drm_device *dev, size_t length, kref_init(&blob->refcount); - list_add_tail(&blob->head, &dev->mode_config.property_blob_list); + list_add_tail(&blob->head_global, + &dev->mode_config.property_blob_list); mutex_unlock(&dev->mode_config.blob_lock); @@ -4212,7 +4216,8 @@ static void drm_property_free_blob(struct kref *kref) WARN_ON(!mutex_is_locked(&blob->dev->mode_config.blob_lock)); - list_del(&blob->head); + list_del(&blob->head_global); + list_del(&blob->head_file); drm_mode_object_put(blob->dev, &blob->base); kfree(blob); @@ -4263,6 +4268,26 @@ static void drm_property_unreference_blob_locked(struct drm_property_blob *blob) kref_put(&blob->refcount, drm_property_free_blob); } +/** + * drm_property_destroy_user_blobs - destroy all blobs created by this client + * @dev: DRM device + * @file_priv: destroy all blobs owned by this file handle + */ +void drm_property_destroy_user_blobs(struct drm_device *dev, + struct drm_file *file_priv) +{ + struct drm_property_blob *blob, *bt; + + mutex_lock(&dev->mode_config.blob_lock); + + list_for_each_entry_safe(blob, bt, &file_priv->blobs, head_file) { + list_del_init(&blob->head_file); + drm_property_unreference_blob_locked(blob); + } + + mutex_unlock(&dev->mode_config.blob_lock); +} + /** * drm_property_reference_blob - Take a reference on an existing property * @@ -4452,6 +4477,114 @@ done: return ret; } +/** + * drm_mode_createblob_ioctl - create a new blob property + * @dev: DRM device + * @data: ioctl data + * @file_priv: DRM file info + * + * This function creates a new blob property with user-defined values. In order + * to give us sensible validation and checking when creating, rather than at + * every potential use, we also require a type to be provided upfront. + * + * Called by the user via ioctl. + * + * Returns: + * Zero on success, negative errno on failure. + */ +int drm_mode_createblob_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv) +{ + struct drm_mode_create_blob *out_resp = data; + struct drm_property_blob *blob; + void __user *blob_ptr; + int ret = 0; + + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + return -EINVAL; + + blob = drm_property_create_blob(dev, out_resp->length, NULL); + if (IS_ERR(blob)) + return PTR_ERR(blob); + + blob_ptr = (void __user *)(unsigned long)out_resp->data; + if (copy_from_user(blob->data, blob_ptr, out_resp->length)) { + ret = -EFAULT; + goto out_blob; + } + + /* Dropping the lock between create_blob and our access here is safe + * as only the same file_priv can remove the blob; at this point, it is + * not associated with any file_priv. */ + mutex_lock(&dev->mode_config.blob_lock); + out_resp->blob_id = blob->base.id; + list_add_tail(&file_priv->blobs, &blob->head_file); + mutex_unlock(&dev->mode_config.blob_lock); + + return 0; + +out_blob: + drm_property_unreference_blob(blob); + return ret; +} + +/** + * drm_mode_destroyblob_ioctl - destroy a user blob property + * @dev: DRM device + * @data: ioctl data + * @file_priv: DRM file info + * + * Destroy an existing user-defined blob property. + * + * Called by the user via ioctl. + * + * Returns: + * Zero on success, negative errno on failure. + */ +int drm_mode_destroyblob_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv) +{ + struct drm_mode_destroy_blob *out_resp = data; + struct drm_property_blob *blob = NULL, *bt; + bool found = false; + int ret = 0; + + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + return -EINVAL; + + mutex_lock(&dev->mode_config.blob_lock); + blob = __drm_property_lookup_blob(dev, out_resp->blob_id); + if (!blob) { + ret = -ENOENT; + goto err; + } + + /* Ensure the property was actually created by this user. */ + list_for_each_entry(bt, &file_priv->blobs, head_file) { + if (bt == blob) { + found = true; + break; + } + } + + if (!found) { + ret = -EPERM; + goto err; + } + + /* We must drop head_file here, because we may not be the last + * reference on the blob. */ + list_del_init(&blob->head_file); + drm_property_unreference_blob_locked(blob); + mutex_unlock(&dev->mode_config.blob_lock); + + return 0; + +err: + mutex_unlock(&dev->mode_config.blob_lock); + return ret; +} + /** * drm_mode_connector_set_path_property - set tile property on connector * @connector: connector to set property on. @@ -5655,7 +5788,7 @@ void drm_mode_config_cleanup(struct drm_device *dev) } list_for_each_entry_safe(blob, bt, &dev->mode_config.property_blob_list, - head) { + head_global) { drm_property_unreference_blob(blob); } diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c index 0f6a5c8801e3..c59ce4d0ef75 100644 --- a/drivers/gpu/drm/drm_fops.c +++ b/drivers/gpu/drm/drm_fops.c @@ -167,6 +167,7 @@ static int drm_open_helper(struct file *filp, struct drm_minor *minor) INIT_LIST_HEAD(&priv->lhead); INIT_LIST_HEAD(&priv->fbs); mutex_init(&priv->fbs_lock); + INIT_LIST_HEAD(&priv->blobs); INIT_LIST_HEAD(&priv->event_list); init_waitqueue_head(&priv->event_wait); priv->event_space = 4096; /* set aside 4k for event buffer */ @@ -405,8 +406,10 @@ int drm_release(struct inode *inode, struct file *filp) drm_events_release(file_priv); - if (drm_core_check_feature(dev, DRIVER_MODESET)) + if (drm_core_check_feature(dev, DRIVER_MODESET)) { drm_fb_release(file_priv); + drm_property_destroy_user_blobs(dev, file_priv); + } if (drm_core_check_feature(dev, DRIVER_GEM)) drm_gem_release(dev, file_priv); diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 266dcd6cdf3b..9bac1b7479af 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -641,6 +641,8 @@ static const struct drm_ioctl_desc drm_ioctls[] = { DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_SETPROPERTY, drm_mode_obj_set_property_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR2, drm_mode_cursor2_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_ATOMIC, drm_mode_atomic_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATEPROPBLOB, drm_mode_createblob_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROYPROPBLOB, drm_mode_destroyblob_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED), }; #define DRM_CORE_IOCTL_COUNT ARRAY_SIZE( drm_ioctls ) diff --git a/include/drm/drmP.h b/include/drm/drmP.h index df6d9970d9a4..9fa6366f47c2 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -326,6 +326,10 @@ struct drm_file { struct list_head fbs; struct mutex fbs_lock; + /** User-created blob properties; this retains a reference on the + * property. */ + struct list_head blobs; + wait_queue_head_t event_wait; struct list_head event_list; int event_space; diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index dace1b635685..72b60dbe0891 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -218,7 +218,8 @@ struct drm_property_blob { struct drm_mode_object base; struct drm_device *dev; struct kref refcount; - struct list_head head; + struct list_head head_global; + struct list_head head_file; size_t length; unsigned char data[]; }; @@ -1315,6 +1316,8 @@ extern const char *drm_get_dvi_i_select_name(int val); extern const char *drm_get_tv_subconnector_name(int val); extern const char *drm_get_tv_select_name(int val); extern void drm_fb_release(struct drm_file *file_priv); +extern void drm_property_destroy_user_blobs(struct drm_device *dev, + struct drm_file *file_priv); extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group); extern void drm_mode_group_destroy(struct drm_mode_group *group); extern void drm_reinit_primary_mode_group(struct drm_device *dev); @@ -1460,6 +1463,10 @@ extern int drm_mode_getproperty_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); extern int drm_mode_getblob_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); +extern int drm_mode_createblob_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv); +extern int drm_mode_destroyblob_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv); extern int drm_mode_connector_property_set_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); extern int drm_mode_getencoder(struct drm_device *dev, diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index ff6ef62d084b..3801584a0c53 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -786,6 +786,8 @@ struct drm_prime_handle { #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) #define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) #define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) +#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) +#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) /** * Device specific ioctls should only be in their respective headers diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index dbeba949462a..359107ab629e 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -558,4 +558,24 @@ struct drm_mode_atomic { __u64 user_data; }; +/** + * Create a new 'blob' data property, copying length bytes from data pointer, + * and returning new blob ID. + */ +struct drm_mode_create_blob { + /** Pointer to data to copy. */ + __u64 data; + /** Length of data to copy. */ + __u32 length; + /** Return: new property ID. */ + __u32 blob_id; +}; + +/** + * Destroy a user-created blob property. + */ +struct drm_mode_destroy_blob { + __u32 blob_id; +}; + #endif -- cgit v1.2.3 From 82d5b58f13fcc5459cd9c61a9d6d4a07328a31dc Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 22 May 2015 19:45:27 +0200 Subject: drm/i915: Update DRIVER_DATE to 20150522 Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1038f5c7f15b..9adfd124ad2d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -56,7 +56,7 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20150508" +#define DRIVER_DATE "20150522" #undef WARN_ON /* Many gcc seem to no see through this and fall over :( */ -- cgit v1.2.3 From a1d0503d26ea2ef04f3f013d379e8f4d29c27127 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 14 May 2015 00:31:07 +0300 Subject: drm: adv7511: Fix crash in IRQ handler when no encoder is associated The ADV7511 is probed before its slave encoder init function associates it with an encoder. This creates a time window during which hot plug detection interrupts can occur with an encoder, resulting in a crash in the IRQ handler. Fix this by ignoring hot plug detection IRQs when no encoder is associated yet. Signed-off-by: Laurent Pinchart Acked-by: Lars-Peter Clausen --- drivers/gpu/drm/i2c/adv7511.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i2c/adv7511.c b/drivers/gpu/drm/i2c/adv7511.c index b728523e194f..2aaa3c88999e 100644 --- a/drivers/gpu/drm/i2c/adv7511.c +++ b/drivers/gpu/drm/i2c/adv7511.c @@ -438,7 +438,7 @@ static int adv7511_irq_process(struct adv7511 *adv7511) regmap_write(adv7511->regmap, ADV7511_REG_INT(0), irq0); regmap_write(adv7511->regmap, ADV7511_REG_INT(1), irq1); - if (irq0 & ADV7511_INT0_HDP) + if (irq0 & ADV7511_INT0_HDP && adv7511->encoder) drm_helper_hpd_irq_event(adv7511->encoder->dev); if (irq0 & ADV7511_INT0_EDID_READY || irq1 & ADV7511_INT1_DDC_ERROR) { -- cgit v1.2.3 From bce9936a0d7f6570aaa64a41e6ff902716aabfa6 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 29 Apr 2015 01:11:57 +0300 Subject: drm: rcar-du: Document the rcar_du_crtc structure Document the structure fields using kerneldoc. Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h index 5d9aa9b33769..4b95d9d08c49 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h @@ -22,6 +22,20 @@ struct rcar_du_group; +/** + * struct rcar_du_crtc - the CRTC, representing a DU superposition processor + * @crtc: base DRM CRTC + * @clock: the CRTC functional clock + * @extclock: external pixel dot clock (optional) + * @mmio_offset: offset of the CRTC registers in the DU MMIO block + * @index: CRTC software and hardware index + * @started: whether the CRTC has been started and is running + * @event: event to post when the pending page flip completes + * @flip_wait: wait queue used to signal page flip completion + * @outputs: bitmask of the outputs (enum rcar_du_output) driven by this CRTC + * @enabled: whether the CRTC is enabled, used to control system resume + * @group: CRTC group this CRTC belongs to + */ struct rcar_du_crtc { struct drm_crtc crtc; -- cgit v1.2.3 From 0855c6827f822b51b2b4fc86d1085f47463cb5c9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 29 Apr 2015 00:12:40 +0300 Subject: drm: rcar-du: Document the rcar_du_plane_state structure Document the structure fields using kerneldoc. Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_plane.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/rcar-du/rcar_du_plane.h index abff0ebeb195..2beb67acdb38 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.h @@ -46,11 +46,20 @@ struct rcar_du_planes { struct drm_property *zpos; }; +/** + * struct rcar_du_plane_state - Driver-specific plane state + * @state: base DRM plane state + * @format: information about the pixel format used by the plane + * @hwindex: 0-based hardware plane index, -1 means unused + * @alpha: value of the plane alpha property + * @colorkey: value of the plane colorkey property + * @zpos: value of the plane zpos property + */ struct rcar_du_plane_state { struct drm_plane_state state; const struct rcar_du_format_info *format; - int hwindex; /* 0-based, -1 means unused */ + int hwindex; unsigned int alpha; unsigned int colorkey; -- cgit v1.2.3 From 9f6aee952b18d9910912d7cedae9bd26bd901ac3 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 28 Apr 2015 23:59:29 +0300 Subject: drm: rcar-du: Move properties from rcar_du_planes to rcar_du_device The plane property objects are instantiated once per CRTC group, while they should be instantiated once globally for the device. Fix this and move them to the rcar_du_device structure. Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_drv.h | 6 +++++ drivers/gpu/drm/rcar-du/rcar_du_kms.c | 29 +++++++++++++++++++++ drivers/gpu/drm/rcar-du/rcar_du_plane.c | 46 +++++++++------------------------ drivers/gpu/drm/rcar-du/rcar_du_plane.h | 4 --- 4 files changed, 47 insertions(+), 38 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h index c7c538dd2e68..9f34fc86436a 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h @@ -83,6 +83,12 @@ struct rcar_du_device { struct rcar_du_group groups[RCAR_DU_MAX_GROUPS]; + struct { + struct drm_property *alpha; + struct drm_property *colorkey; + struct drm_property *zpos; + } props; + unsigned int dpad0_source; struct rcar_du_lvdsenc *lvds[RCAR_DU_MAX_LVDS]; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c index 93117f159a3b..5fd6f8c07ec2 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c @@ -648,6 +648,31 @@ static int rcar_du_encoders_init(struct rcar_du_device *rcdu) return num_encoders; } +static int rcar_du_properties_init(struct rcar_du_device *rcdu) +{ + rcdu->props.alpha = + drm_property_create_range(rcdu->ddev, 0, "alpha", 0, 255); + if (rcdu->props.alpha == NULL) + return -ENOMEM; + + /* The color key is expressed as an RGB888 triplet stored in a 32-bit + * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0) + * or enable source color keying (1). + */ + rcdu->props.colorkey = + drm_property_create_range(rcdu->ddev, 0, "colorkey", + 0, 0x01ffffff); + if (rcdu->props.colorkey == NULL) + return -ENOMEM; + + rcdu->props.zpos = + drm_property_create_range(rcdu->ddev, 0, "zpos", 1, 7); + if (rcdu->props.zpos == NULL) + return -ENOMEM; + + return 0; +} + int rcar_du_modeset_init(struct rcar_du_device *rcdu) { static const unsigned int mmio_offsets[] = { @@ -672,6 +697,10 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu) rcdu->num_crtcs = rcdu->info->num_crtcs; + ret = rcar_du_properties_init(rcdu); + if (ret < 0) + return ret; + /* Initialize the groups. */ num_groups = DIV_ROUND_UP(rcdu->num_crtcs, 2); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c index 210e5c3fd982..b5565417f673 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c @@ -328,14 +328,13 @@ static int rcar_du_plane_atomic_set_property(struct drm_plane *plane, uint64_t val) { struct rcar_du_plane_state *rstate = to_rcar_du_plane_state(state); - struct rcar_du_plane *rplane = to_rcar_plane(plane); - struct rcar_du_group *rgrp = rplane->group; + struct rcar_du_device *rcdu = to_rcar_plane(plane)->group->dev; - if (property == rgrp->planes.alpha) + if (property == rcdu->props.alpha) rstate->alpha = val; - else if (property == rgrp->planes.colorkey) + else if (property == rcdu->props.colorkey) rstate->colorkey = val; - else if (property == rgrp->planes.zpos) + else if (property == rcdu->props.zpos) rstate->zpos = val; else return -EINVAL; @@ -349,14 +348,13 @@ static int rcar_du_plane_atomic_get_property(struct drm_plane *plane, { const struct rcar_du_plane_state *rstate = container_of(state, const struct rcar_du_plane_state, state); - struct rcar_du_plane *rplane = to_rcar_plane(plane); - struct rcar_du_group *rgrp = rplane->group; + struct rcar_du_device *rcdu = to_rcar_plane(plane)->group->dev; - if (property == rgrp->planes.alpha) + if (property == rcdu->props.alpha) *val = rstate->alpha; - else if (property == rgrp->planes.colorkey) + else if (property == rcdu->props.colorkey) *val = rstate->colorkey; - else if (property == rgrp->planes.zpos) + else if (property == rcdu->props.zpos) *val = rstate->zpos; else return -EINVAL; @@ -399,27 +397,7 @@ int rcar_du_planes_init(struct rcar_du_group *rgrp) unsigned int i; int ret; - planes->alpha = - drm_property_create_range(rcdu->ddev, 0, "alpha", 0, 255); - if (planes->alpha == NULL) - return -ENOMEM; - - /* The color key is expressed as an RGB888 triplet stored in a 32-bit - * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0) - * or enable source color keying (1). - */ - planes->colorkey = - drm_property_create_range(rcdu->ddev, 0, "colorkey", - 0, 0x01ffffff); - if (planes->colorkey == NULL) - return -ENOMEM; - - planes->zpos = - drm_property_create_range(rcdu->ddev, 0, "zpos", 1, 7); - if (planes->zpos == NULL) - return -ENOMEM; - - /* Create one primary plane per in this group CRTC and seven overlay + /* Create one primary plane per CRTC in this group and seven overlay * planes. */ num_crtcs = min(rcdu->num_crtcs - 2 * rgrp->index, 2U); @@ -448,12 +426,12 @@ int rcar_du_planes_init(struct rcar_du_group *rgrp) continue; drm_object_attach_property(&plane->plane.base, - planes->alpha, 255); + rcdu->props.alpha, 255); drm_object_attach_property(&plane->plane.base, - planes->colorkey, + rcdu->props.colorkey, RCAR_DU_COLORKEY_NONE); drm_object_attach_property(&plane->plane.base, - planes->zpos, 1); + rcdu->props.zpos, 1); } return 0; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/rcar-du/rcar_du_plane.h index 2beb67acdb38..6b17b1f4f414 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.h @@ -40,10 +40,6 @@ static inline struct rcar_du_plane *to_rcar_plane(struct drm_plane *plane) struct rcar_du_planes { struct rcar_du_plane planes[RCAR_DU_NUM_KMS_PLANES]; - - struct drm_property *alpha; - struct drm_property *colorkey; - struct drm_property *zpos; }; /** -- cgit v1.2.3 From 99caede11d84af4c0a16fd07f7d7ce9de94f6109 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 29 Apr 2015 00:05:56 +0300 Subject: drm: rcar-du: Embed rcar_du_planes structure into rcar_du_group The rcar_du_planes structure contains a single field and is only instantiated in the rcar_du_group structure. Embed it directly and remove the rcar_du_planes structure. Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 10 +++++----- drivers/gpu/drm/rcar-du/rcar_du_group.h | 2 +- drivers/gpu/drm/rcar-du/rcar_du_kms.c | 6 +++--- drivers/gpu/drm/rcar-du/rcar_du_plane.c | 3 +-- drivers/gpu/drm/rcar-du/rcar_du_plane.h | 4 ---- 5 files changed, 10 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 7d0b8ef9bea2..b5f66b78cbb2 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -213,8 +213,8 @@ static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc) u32 dptsr = 0; u32 dspr = 0; - for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) { - struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i]; + for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes); ++i) { + struct rcar_du_plane *plane = &rcrtc->group->planes[i]; unsigned int j; if (plane->plane.state->crtc != &rcrtc->crtc) @@ -427,8 +427,8 @@ void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc) rcar_du_crtc_start(rcrtc); /* Commit the planes state. */ - for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) { - struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i]; + for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes); ++i) { + struct rcar_du_plane *plane = &rcrtc->group->planes[i]; if (plane->plane.state->crtc != &rcrtc->crtc) continue; @@ -592,7 +592,7 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index) rcrtc->enabled = false; ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, - &rgrp->planes.planes[index % 2].plane, + &rgrp->planes[index % 2].plane, NULL, &crtc_funcs); if (ret < 0) return ret; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.h b/drivers/gpu/drm/rcar-du/rcar_du_group.h index ed36433fbe84..ea02bb02f3e1 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.h @@ -40,7 +40,7 @@ struct rcar_du_group { struct mutex lock; - struct rcar_du_planes planes; + struct rcar_du_plane planes[RCAR_DU_NUM_KMS_PLANES]; }; u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c index 5fd6f8c07ec2..4012afacab5f 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c @@ -291,7 +291,7 @@ static int rcar_du_atomic_check(struct drm_device *dev, * plane(s) as freed. */ if (!plane_state->format) { - index = plane - plane->group->planes.planes; + index = plane - plane->group->planes; group_freed_planes[plane->group->index] |= 1 << index; plane_state->hwindex = -1; continue; @@ -304,7 +304,7 @@ static int rcar_du_atomic_check(struct drm_device *dev, groups |= 1 << plane->group->index; needs_realloc = true; - index = plane - plane->group->planes.planes; + index = plane - plane->group->planes; group_freed_planes[plane->group->index] |= 1 << index; plane_state->hwindex = -1; } @@ -327,7 +327,7 @@ static int rcar_du_atomic_check(struct drm_device *dev, unsigned int used_planes = 0; for (i = 0; i < RCAR_DU_NUM_KMS_PLANES; ++i) { - struct rcar_du_plane *plane = &group->planes.planes[i]; + struct rcar_du_plane *plane = &group->planes[i]; struct rcar_du_plane_state *plane_state; struct drm_plane_state *s; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c index b5565417f673..99fefcaf6597 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c @@ -389,7 +389,6 @@ static const uint32_t formats[] = { int rcar_du_planes_init(struct rcar_du_group *rgrp) { - struct rcar_du_planes *planes = &rgrp->planes; struct rcar_du_device *rcdu = rgrp->dev; unsigned int num_planes; unsigned int num_crtcs; @@ -409,7 +408,7 @@ int rcar_du_planes_init(struct rcar_du_group *rgrp) enum drm_plane_type type = i < num_crtcs ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY; - struct rcar_du_plane *plane = &planes->planes[i]; + struct rcar_du_plane *plane = &rgrp->planes[i]; plane->group = rgrp; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/rcar-du/rcar_du_plane.h index 6b17b1f4f414..d1fb9b16a060 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.h @@ -38,10 +38,6 @@ static inline struct rcar_du_plane *to_rcar_plane(struct drm_plane *plane) return container_of(plane, struct rcar_du_plane, plane); } -struct rcar_du_planes { - struct rcar_du_plane planes[RCAR_DU_NUM_KMS_PLANES]; -}; - /** * struct rcar_du_plane_state - Driver-specific plane state * @state: base DRM plane state -- cgit v1.2.3 From ec69a40645c829fcec613b437f72451205ff601f Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 29 Apr 2015 00:48:17 +0300 Subject: drm: rcar-du: Rename to_rcar_du_plane_state to to_rcar_plane_state All other cast functions are named without using "du", make the plane state cast consistent with them. Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 6 +++--- drivers/gpu/drm/rcar-du/rcar_du_kms.c | 8 ++++---- drivers/gpu/drm/rcar-du/rcar_du_plane.c | 16 ++++++++-------- drivers/gpu/drm/rcar-du/rcar_du_plane.h | 2 +- 4 files changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index b5f66b78cbb2..15f8d145a133 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -195,13 +195,13 @@ void rcar_du_crtc_route_output(struct drm_crtc *crtc, static unsigned int plane_zpos(struct rcar_du_plane *plane) { - return to_rcar_du_plane_state(plane->plane.state)->zpos; + return to_rcar_plane_state(plane->plane.state)->zpos; } static const struct rcar_du_format_info * plane_format(struct rcar_du_plane *plane) { - return to_rcar_du_plane_state(plane->plane.state)->format; + return to_rcar_plane_state(plane->plane.state)->format; } static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc) @@ -234,7 +234,7 @@ static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc) for (i = 0; i < num_planes; ++i) { struct rcar_du_plane *plane = planes[i]; struct drm_plane_state *state = plane->plane.state; - unsigned int index = to_rcar_du_plane_state(state)->hwindex; + unsigned int index = to_rcar_plane_state(state)->hwindex; prio -= 4; dspr |= (index + 1) << prio; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c index 4012afacab5f..14d457047c40 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c @@ -221,7 +221,7 @@ static bool rcar_du_plane_needs_realloc(struct rcar_du_plane *plane, { const struct rcar_du_format_info *cur_format; - cur_format = to_rcar_du_plane_state(plane->plane.state)->format; + cur_format = to_rcar_plane_state(plane->plane.state)->format; /* Lowering the number of planes doesn't strictly require reallocation * as the extra hardware plane will be freed when committing, but doing @@ -284,7 +284,7 @@ static int rcar_du_atomic_check(struct drm_device *dev, continue; plane = to_rcar_plane(state->planes[i]); - plane_state = to_rcar_du_plane_state(state->plane_states[i]); + plane_state = to_rcar_plane_state(state->plane_states[i]); /* If the plane is being disabled we don't need to go through * the full reallocation procedure. Just mark the hardware @@ -345,7 +345,7 @@ static int rcar_du_atomic_check(struct drm_device *dev, if (group_freed_planes[index] & (1 << i)) continue; - plane_state = to_rcar_du_plane_state(plane->plane.state); + plane_state = to_rcar_plane_state(plane->plane.state); used_planes |= rcar_du_plane_hwmask(plane_state); } @@ -363,7 +363,7 @@ static int rcar_du_atomic_check(struct drm_device *dev, continue; plane = to_rcar_plane(state->planes[i]); - plane_state = to_rcar_du_plane_state(state->plane_states[i]); + plane_state = to_rcar_plane_state(state->plane_states[i]); /* Skip planes that are being disabled or don't need to be * reallocated. diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c index 99fefcaf6597..d3ed528fa56d 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c @@ -45,7 +45,7 @@ static void rcar_du_plane_write(struct rcar_du_group *rgrp, static void rcar_du_plane_setup_fb(struct rcar_du_plane *plane) { struct rcar_du_plane_state *state = - to_rcar_du_plane_state(plane->plane.state); + to_rcar_plane_state(plane->plane.state); struct drm_framebuffer *fb = plane->plane.state->fb; struct rcar_du_group *rgrp = plane->group; unsigned int src_x = state->state.src_x >> 16; @@ -109,7 +109,7 @@ static void rcar_du_plane_setup_mode(struct rcar_du_plane *plane, unsigned int index) { struct rcar_du_plane_state *state = - to_rcar_du_plane_state(plane->plane.state); + to_rcar_plane_state(plane->plane.state); struct rcar_du_group *rgrp = plane->group; u32 colorkey; u32 pnmr; @@ -172,7 +172,7 @@ static void __rcar_du_plane_setup(struct rcar_du_plane *plane, unsigned int index) { struct rcar_du_plane_state *state = - to_rcar_du_plane_state(plane->plane.state); + to_rcar_plane_state(plane->plane.state); struct rcar_du_group *rgrp = plane->group; u32 ddcr2 = PnDDCR2_CODE; u32 ddcr4; @@ -222,7 +222,7 @@ static void __rcar_du_plane_setup(struct rcar_du_plane *plane, void rcar_du_plane_setup(struct rcar_du_plane *plane) { struct rcar_du_plane_state *state = - to_rcar_du_plane_state(plane->plane.state); + to_rcar_plane_state(plane->plane.state); __rcar_du_plane_setup(plane, state->hwindex); if (state->format->planes == 2) @@ -234,7 +234,7 @@ void rcar_du_plane_setup(struct rcar_du_plane *plane) static int rcar_du_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { - struct rcar_du_plane_state *rstate = to_rcar_du_plane_state(state); + struct rcar_du_plane_state *rstate = to_rcar_plane_state(state); struct rcar_du_plane *rplane = to_rcar_plane(plane); struct rcar_du_device *rcdu = rplane->group->dev; @@ -302,7 +302,7 @@ rcar_du_plane_atomic_duplicate_state(struct drm_plane *plane) struct rcar_du_plane_state *state; struct rcar_du_plane_state *copy; - state = to_rcar_du_plane_state(plane->state); + state = to_rcar_plane_state(plane->state); copy = kmemdup(state, sizeof(*state), GFP_KERNEL); if (copy == NULL) return NULL; @@ -319,7 +319,7 @@ static void rcar_du_plane_atomic_destroy_state(struct drm_plane *plane, if (state->fb) drm_framebuffer_unreference(state->fb); - kfree(to_rcar_du_plane_state(state)); + kfree(to_rcar_plane_state(state)); } static int rcar_du_plane_atomic_set_property(struct drm_plane *plane, @@ -327,7 +327,7 @@ static int rcar_du_plane_atomic_set_property(struct drm_plane *plane, struct drm_property *property, uint64_t val) { - struct rcar_du_plane_state *rstate = to_rcar_du_plane_state(state); + struct rcar_du_plane_state *rstate = to_rcar_plane_state(state); struct rcar_du_device *rcdu = to_rcar_plane(plane)->group->dev; if (property == rcdu->props.alpha) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/rcar-du/rcar_du_plane.h index d1fb9b16a060..9732bff1911b 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.h @@ -59,7 +59,7 @@ struct rcar_du_plane_state { }; static inline struct rcar_du_plane_state * -to_rcar_du_plane_state(struct drm_plane_state *state) +to_rcar_plane_state(struct drm_plane_state *state) { return container_of(state, struct rcar_du_plane_state, state); } -- cgit v1.2.3 From 08058611958bc161b1de991b494373b8bce56e6b Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 25 Feb 2015 22:31:52 +0200 Subject: drm: rcar-du: Add plane allocation debugging Plane allocation is a complex process, add debugging statements to help finding out what could might wrong. Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_kms.c | 38 ++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c index 14d457047c40..ade135008e98 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c @@ -286,11 +286,16 @@ static int rcar_du_atomic_check(struct drm_device *dev, plane = to_rcar_plane(state->planes[i]); plane_state = to_rcar_plane_state(state->plane_states[i]); + dev_dbg(rcdu->dev, "%s: checking plane (%u,%u)\n", __func__, + plane->group->index, plane - plane->group->planes); + /* If the plane is being disabled we don't need to go through * the full reallocation procedure. Just mark the hardware * plane(s) as freed. */ if (!plane_state->format) { + dev_dbg(rcdu->dev, "%s: plane is being disabled\n", + __func__); index = plane - plane->group->planes; group_freed_planes[plane->group->index] |= 1 << index; plane_state->hwindex = -1; @@ -301,6 +306,8 @@ static int rcar_du_atomic_check(struct drm_device *dev, * mark the hardware plane(s) as free. */ if (rcar_du_plane_needs_realloc(plane, plane_state)) { + dev_dbg(rcdu->dev, "%s: plane needs reallocation\n", + __func__); groups |= 1 << plane->group->index; needs_realloc = true; @@ -326,6 +333,9 @@ static int rcar_du_atomic_check(struct drm_device *dev, struct rcar_du_group *group = &rcdu->groups[index]; unsigned int used_planes = 0; + dev_dbg(rcdu->dev, "%s: finding free planes for group %u\n", + __func__, index); + for (i = 0; i < RCAR_DU_NUM_KMS_PLANES; ++i) { struct rcar_du_plane *plane = &group->planes[i]; struct rcar_du_plane_state *plane_state; @@ -342,15 +352,31 @@ static int rcar_du_atomic_check(struct drm_device *dev, * above. Use the local freed planes list to check for * that condition instead. */ - if (group_freed_planes[index] & (1 << i)) + if (group_freed_planes[index] & (1 << i)) { + dev_dbg(rcdu->dev, + "%s: plane (%u,%u) has been freed, skipping\n", + __func__, plane->group->index, + plane - plane->group->planes); continue; + } plane_state = to_rcar_plane_state(plane->plane.state); used_planes |= rcar_du_plane_hwmask(plane_state); + + dev_dbg(rcdu->dev, + "%s: plane (%u,%u) uses %u hwplanes (index %d)\n", + __func__, plane->group->index, + plane - plane->group->planes, + plane_state->format ? + plane_state->format->planes : 0, + plane_state->hwindex); } group_free_planes[index] = 0xff & ~used_planes; groups &= ~(1 << index); + + dev_dbg(rcdu->dev, "%s: group %u free planes mask 0x%02x\n", + __func__, index, group_free_planes[index]); } /* Reallocate hardware planes for each plane that needs it. */ @@ -365,6 +391,9 @@ static int rcar_du_atomic_check(struct drm_device *dev, plane = to_rcar_plane(state->planes[i]); plane_state = to_rcar_plane_state(state->plane_states[i]); + dev_dbg(rcdu->dev, "%s: allocating plane (%u,%u)\n", __func__, + plane->group->index, plane - plane->group->planes); + /* Skip planes that are being disabled or don't need to be * reallocated. */ @@ -380,10 +409,17 @@ static int rcar_du_atomic_check(struct drm_device *dev, return idx; } + dev_dbg(rcdu->dev, "%s: allocated %u hwplanes (index %u)\n", + __func__, plane_state->format->planes, idx); + plane_state->hwindex = idx; group_free_planes[plane->group->index] &= ~rcar_du_plane_hwmask(plane_state); + + dev_dbg(rcdu->dev, "%s: group %u free planes mask 0x%02x\n", + __func__, plane->group->index, + group_free_planes[plane->group->index]); } return 0; -- cgit v1.2.3 From 2a57e9b5af2b96c45d8c73d34416e5dfa5dd38d9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 28 Apr 2015 18:01:45 +0300 Subject: drm: rcar-du: Keep plane to CRTC associations when disabling a plane Changing the plane to CRTC associations requires restarting the CRTC group, creating visible flicker. Mitigate the issue by changing plane association only when a plane becomes enabled, not when it get disabled. Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 48 +++++++++++++++++++-------------- drivers/gpu/drm/rcar-du/rcar_du_group.c | 6 +++++ drivers/gpu/drm/rcar-du/rcar_du_group.h | 4 ++- 3 files changed, 37 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 15f8d145a133..620a2c51185c 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -208,9 +208,10 @@ static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc) { struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES]; unsigned int num_planes = 0; + unsigned int dptsr_planes; + unsigned int hwplanes = 0; unsigned int prio = 0; unsigned int i; - u32 dptsr = 0; u32 dspr = 0; for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes); ++i) { @@ -238,37 +239,44 @@ static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc) prio -= 4; dspr |= (index + 1) << prio; - dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index); + hwplanes |= 1 << index; if (plane_format(plane)->planes == 2) { index = (index + 1) % 8; prio -= 4; dspr |= (index + 1) << prio; - dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index); + hwplanes |= 1 << index; } } - /* Select display timing and dot clock generator 2 for planes associated - * with superposition controller 2. + /* Update the planes to display timing and dot clock generator + * associations. + * + * Updating the DPTSR register requires restarting the CRTC group, + * resulting in visible flicker. To mitigate the issue only update the + * association if needed by enabled planes. Planes being disabled will + * keep their current association. + * + * To mitigate the issue further we could pre-associate planes with + * CRTCs, either with a fixed 4/4 split, or through a module parameter. */ - if (rcrtc->index % 2) { - /* The DPTSR register is updated when the display controller is - * stopped. We thus need to restart the DU. Once again, sorry - * for the flicker. One way to mitigate the issue would be to - * pre-associate planes with CRTCs (either with a fixed 4/4 - * split, or through a module parameter). Flicker would then - * occur only if we need to break the pre-association. - */ - mutex_lock(&rcrtc->group->lock); - if (rcar_du_group_read(rcrtc->group, DPTSR) != dptsr) { - rcar_du_group_write(rcrtc->group, DPTSR, dptsr); - if (rcrtc->group->used_crtcs) - rcar_du_group_restart(rcrtc->group); - } - mutex_unlock(&rcrtc->group->lock); + mutex_lock(&rcrtc->group->lock); + + dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes + : rcrtc->group->dptsr_planes & ~hwplanes; + + if (dptsr_planes != rcrtc->group->dptsr_planes) { + rcar_du_group_write(rcrtc->group, DPTSR, + (dptsr_planes << 16) | dptsr_planes); + rcrtc->group->dptsr_planes = dptsr_planes; + + if (rcrtc->group->used_crtcs) + rcar_du_group_restart(rcrtc->group); } + mutex_unlock(&rcrtc->group->lock); + rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, dspr); } diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index 1bdc0ee0c248..7fd39a7d91c8 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -85,6 +85,12 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. */ rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS); + + /* Apply planes to CRTCs association. */ + mutex_lock(&rgrp->lock); + rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) | + rgrp->dptsr_planes); + mutex_unlock(&rgrp->lock); } /* diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.h b/drivers/gpu/drm/rcar-du/rcar_du_group.h index ea02bb02f3e1..4f6c37c8d336 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.h @@ -27,7 +27,8 @@ struct rcar_du_device; * @index: group index * @use_count: number of users of the group (rcar_du_group_(get|put)) * @used_crtcs: number of CRTCs currently in use - * @lock: protects the DPTSR register + * @lock: protects the dptsr_planes field and the DPTSR register + * @dptsr_planes: bitmask of planes driven by dot-clock and timing generator 1 * @planes: planes handled by the group */ struct rcar_du_group { @@ -39,6 +40,7 @@ struct rcar_du_group { unsigned int used_crtcs; struct mutex lock; + unsigned int dptsr_planes; struct rcar_du_plane planes[RCAR_DU_NUM_KMS_PLANES]; }; -- cgit v1.2.3 From c8af99b60421c184cab1c3a849debce1463ec792 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 29 Apr 2015 00:51:01 +0300 Subject: drm: rcar-du: Consider plane to CRTC associations in the plane allocator Hardware planes are driven by the timing generator of the CRTC they are associated to. Changing the association requires restarting the CRTC group that the plane belongs to, resulting in flicker on the other CRTC. To avoid flicker as much as possible, try to allocate planes first from the free planes already associated with the target CRTC. If allocation fails then fall back to allocation from all free planes. Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_kms.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c index ade135008e98..2c6cf691d163 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c @@ -383,6 +383,8 @@ static int rcar_du_atomic_check(struct drm_device *dev, for (i = 0; i < dev->mode_config.num_total_plane; ++i) { struct rcar_du_plane_state *plane_state; struct rcar_du_plane *plane; + unsigned int crtc_planes; + unsigned int free; int idx; if (!state->planes[i]) @@ -401,8 +403,21 @@ static int rcar_du_atomic_check(struct drm_device *dev, !rcar_du_plane_needs_realloc(plane, plane_state)) continue; + /* Try to allocate the plane from the free planes currently + * associated with the target CRTC to avoid restarting the CRTC + * group and thus minimize flicker. If it fails fall back to + * allocating from all free planes. + */ + crtc_planes = to_rcar_crtc(plane_state->state.crtc)->index % 2 + ? plane->group->dptsr_planes + : ~plane->group->dptsr_planes; + free = group_free_planes[plane->group->index]; + idx = rcar_du_plane_hwalloc(plane_state->format->planes, - group_free_planes[plane->group->index]); + free & crtc_planes); + if (idx < 0) + idx = rcar_du_plane_hwalloc(plane_state->format->planes, + free); if (idx < 0) { dev_dbg(rcdu->dev, "%s: no available hardware plane\n", __func__); @@ -749,6 +764,11 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu) rgrp->mmio_offset = mmio_offsets[i]; rgrp->index = i; + /* Pre-associate all hardware planes with the first CRTC in the + * group. + */ + rgrp->dptsr_planes = 0; + ret = rcar_du_planes_init(rgrp); if (ret < 0) return ret; -- cgit v1.2.3 From fe6fbe9a024e149e4230a338700d24db8806183a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 28 Apr 2015 17:36:33 +0300 Subject: drm: rcar-du: Store the number of CRTCs per group in the group structure The number of CRTCs in a group is only used to implement plane initialization for now, but is also needed to implement pre-association of planes to CRTCs. Store it in the group structure instead of computing it on demand. Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_group.h | 2 ++ drivers/gpu/drm/rcar-du/rcar_du_kms.c | 1 + drivers/gpu/drm/rcar-du/rcar_du_plane.c | 6 ++---- 3 files changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.h b/drivers/gpu/drm/rcar-du/rcar_du_group.h index 4f6c37c8d336..7b414b31c3be 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.h @@ -25,6 +25,7 @@ struct rcar_du_device; * @dev: the DU device * @mmio_offset: registers offset in the device memory map * @index: group index + * @num_crtcs: number of CRTCs in this group (1 or 2) * @use_count: number of users of the group (rcar_du_group_(get|put)) * @used_crtcs: number of CRTCs currently in use * @lock: protects the dptsr_planes field and the DPTSR register @@ -36,6 +37,7 @@ struct rcar_du_group { unsigned int mmio_offset; unsigned int index; + unsigned int num_crtcs; unsigned int use_count; unsigned int used_crtcs; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c index 2c6cf691d163..fec5f4d794da 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c @@ -763,6 +763,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu) rgrp->dev = rcdu; rgrp->mmio_offset = mmio_offsets[i]; rgrp->index = i; + rgrp->num_crtcs = min(rcdu->num_crtcs - 2 * i, 2U); /* Pre-associate all hardware planes with the first CRTC in the * group. diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c index d3ed528fa56d..3e30d84b798f 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c @@ -391,7 +391,6 @@ int rcar_du_planes_init(struct rcar_du_group *rgrp) { struct rcar_du_device *rcdu = rgrp->dev; unsigned int num_planes; - unsigned int num_crtcs; unsigned int crtcs; unsigned int i; int ret; @@ -399,13 +398,12 @@ int rcar_du_planes_init(struct rcar_du_group *rgrp) /* Create one primary plane per CRTC in this group and seven overlay * planes. */ - num_crtcs = min(rcdu->num_crtcs - 2 * rgrp->index, 2U); - num_planes = num_crtcs + 7; + num_planes = rgrp->num_crtcs + 7; crtcs = ((1 << rcdu->num_crtcs) - 1) & (3 << (2 * rgrp->index)); for (i = 0; i < num_planes; ++i) { - enum drm_plane_type type = i < num_crtcs + enum drm_plane_type type = i < rgrp->num_crtcs ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY; struct rcar_du_plane *plane = &rgrp->planes[i]; -- cgit v1.2.3 From 2610abfb3a72f6e5444a710b695c9460138f9326 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 28 Apr 2015 22:00:28 +0300 Subject: drm: rcar-du: Split planes pre-association 4/4 between CRTCs If we have more than one CRTCs in a group pre-associate planes 0-3 with CRTC 0 and planes 4-7 with CRTC 1 to minimize flicker occurring when the association is changed. The pre-association could be controlled by a module parameter if needed. Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 --- drivers/gpu/drm/rcar-du/rcar_du_kms.c | 7 ++++--- 2 files changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 620a2c51185c..e6a32c4e4040 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -257,9 +257,6 @@ static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc) * resulting in visible flicker. To mitigate the issue only update the * association if needed by enabled planes. Planes being disabled will * keep their current association. - * - * To mitigate the issue further we could pre-associate planes with - * CRTCs, either with a fixed 4/4 split, or through a module parameter. */ mutex_lock(&rcrtc->group->lock); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c index fec5f4d794da..20859aae882e 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c @@ -765,10 +765,11 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu) rgrp->index = i; rgrp->num_crtcs = min(rcdu->num_crtcs - 2 * i, 2U); - /* Pre-associate all hardware planes with the first CRTC in the - * group. + /* If we have more than one CRTCs in this group pre-associate + * planes 0-3 with CRTC 0 and planes 4-7 with CRTC 1 to minimize + * flicker occurring when the association is changed. */ - rgrp->dptsr_planes = 0; + rgrp->dptsr_planes = rgrp->num_crtcs > 1 ? 0xf0 : 0; ret = rcar_du_planes_init(rgrp); if (ret < 0) -- cgit v1.2.3 From 908d759b210effb33d927a8cb6603a16448474e4 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Tue, 26 May 2015 07:46:21 +0200 Subject: Revert "drm/i915: Force clean compilation with -Werror" This reverts commit 118182e9d7d5afa0c7c10f568afb46ab78b462e9. It's causing too much trouble when compile-testing for non-i915 folks. Cc: Chris Wilson Cc: Jani Nikula Cc: Andrew Morton Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/Kconfig | 8 -------- drivers/gpu/drm/i915/Kconfig.debug | 5 ----- drivers/gpu/drm/i915/Makefile | 2 -- 3 files changed, 15 deletions(-) delete mode 100644 drivers/gpu/drm/i915/Kconfig.debug (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 5e3aa87e8f48..74acca9bcd9d 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -71,11 +71,3 @@ config DRM_I915_PRELIMINARY_HW_SUPPORT option changes the default for that module option. If in doubt, say "N". - -menu "DRM i915 Debugging" - -depends on DRM_I915 - -source drivers/gpu/drm/i915/Kconfig.debug - -endmenu diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug deleted file mode 100644 index 070a03527bc5..000000000000 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ /dev/null @@ -1,5 +0,0 @@ -config DRM_I915_WERROR - bool "Force GCC to throw an error instead of a warning when compiling" - default n - ---help--- - Add -Werror to the build flags for (and only for) i915.ko diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 93d99b744531..b7ddf48e1d75 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -2,8 +2,6 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -subdir-ccflags-$(CONFIG_DRM_I915_WERROR) := -Werror - # Please keep these build lists sorted! # core driver code -- cgit v1.2.3 From da9b2a381a32c2a287f99e4be2f372587c53ef14 Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Mon, 25 May 2015 19:11:49 +0100 Subject: drm: Retain reference to blob properties in lookup When we look up a blob property, make sure we retain a reference to the blob for the lifetime. v2: Use DRM_MODE_PROP_BLOB, not PROP_OBJECT + OBJECT_BLOB. Signed-off-by: Daniel Stone Tested-by: Sean Paul Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index e548c50edc94..2de6edf821c7 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -4775,7 +4775,8 @@ void drm_property_change_valid_put(struct drm_property *property, if (drm_property_type_is(property, DRM_MODE_PROP_OBJECT)) { if (property->values[0] == DRM_MODE_OBJECT_FB) drm_framebuffer_unreference(obj_to_fb(ref)); - } + } else if (drm_property_type_is(property, DRM_MODE_PROP_BLOB)) + drm_property_unreference_blob(obj_to_blob(ref)); } /** -- cgit v1.2.3 From bbe16a40e23a65626904aa22fbfc3240a65d21d1 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 20 May 2015 16:53:53 +0200 Subject: drm: check for garbage in unused addfb2 fields Unfortunately old userspace didn't clear this properly, but since we've added fb modifiers that's fixed. Checking properly that unused fields is important for abi extensions, and just right now there's a bunch of discussions going on about how exactly the additional aux planes for render compression should be specified. So let's first make sure that the values in those additional fields can be indeed used. Cc: Thierry Reding Testcase: igt/kms_addfb/unused-* Reviewed-by: Thierry Reding Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_crtc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 2de6edf821c7..098c94e53fdf 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -3249,6 +3249,32 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r) } } + for (i = num_planes; i < 4; i++) { + if (r->modifier[i]) { + DRM_DEBUG_KMS("non-zero modifier for unused plane %d\n", i); + return -EINVAL; + } + + /* Pre-FB_MODIFIERS userspace didn't clear the structs properly. */ + if (!(r->flags & DRM_MODE_FB_MODIFIERS)) + continue; + + if (r->handles[i]) { + DRM_DEBUG_KMS("buffer object handle for unused plane %d\n", i); + return -EINVAL; + } + + if (r->pitches[i]) { + DRM_DEBUG_KMS("non-zero pitch for unused plane %d\n", i); + return -EINVAL; + } + + if (r->offsets[i]) { + DRM_DEBUG_KMS("non-zero offset for unused plane %d\n", i); + return -EINVAL; + } + } + return 0; } -- cgit v1.2.3 From 819364da20fd914aba2fd03e95ee0467286752f5 Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Tue, 26 May 2015 14:36:48 +0100 Subject: drm: Add drm_atomic_set_mode_for_crtc Add a new helper, to be used later for blob property management, that sets the mode for a CRTC state, as well as updating the CRTC enable/active state at the same time. v2: Do not touch active/mode_changed in CRTC state. Document return value. Remove stray drm_atomic_set_mode_prop_for_crtc declaration. v3: Remove i915 changes, and leave it directly bashing crtc_state->mode for the meantime. Signed-off-by: Daniel Stone Tested-by: Sean Paul Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic.c | 36 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/drm_atomic_helper.c | 11 ++++++++--- drivers/gpu/drm/drm_crtc_helper.c | 5 +++-- include/drm/drm_atomic.h | 3 +++ 4 files changed, 50 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 3134f506b762..e749287390a3 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -289,6 +289,42 @@ drm_atomic_get_crtc_state(struct drm_atomic_state *state, } EXPORT_SYMBOL(drm_atomic_get_crtc_state); +/** + * drm_atomic_set_mode_for_crtc - set mode for CRTC + * @state: the CRTC whose incoming state to update + * @mode: kernel-internal mode to use for the CRTC, or NULL to disable + * + * Set a mode (originating from the kernel) on the desired CRTC state. Does + * not change any other state properties, including enable, active, or + * mode_changed. + * + * RETURNS: + * Zero on success, error code on failure. Cannot return -EDEADLK. + */ +int drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state, + struct drm_display_mode *mode) +{ + /* Early return for no change. */ + if (mode && memcmp(&state->mode, mode, sizeof(*mode)) == 0) + return 0; + + if (mode) { + drm_mode_copy(&state->mode, mode); + state->enable = true; + DRM_DEBUG_ATOMIC("Set [MODE:%s] for CRTC state %p\n", + mode->name, state); + } else { + memset(&state->mode, 0, sizeof(state->mode)); + state->enable = false; + DRM_DEBUG_ATOMIC("Set [NOMODE] for CRTC state %p\n", + state); + } + + return 0; +} +EXPORT_SYMBOL(drm_atomic_set_mode_for_crtc); + + /** * drm_atomic_crtc_set_property - set property on CRTC * @crtc: the drm CRTC to set a property on diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index a64bacdcf263..e69d4847e237 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -1607,7 +1607,10 @@ retry: WARN_ON(set->fb); WARN_ON(set->num_connectors); - crtc_state->enable = false; + ret = drm_atomic_set_mode_for_crtc(crtc_state, NULL); + if (ret != 0) + goto fail; + crtc_state->active = false; ret = drm_atomic_set_crtc_for_plane(primary_state, NULL); @@ -1622,9 +1625,11 @@ retry: WARN_ON(!set->fb); WARN_ON(!set->num_connectors); - crtc_state->enable = true; + ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode); + if (ret != 0) + goto fail; + crtc_state->active = true; - drm_mode_copy(&crtc_state->mode, set->mode); ret = drm_atomic_set_crtc_for_plane(primary_state, crtc); if (ret != 0) diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 9297a61a7c95..393114df88a3 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -937,10 +937,11 @@ int drm_helper_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mod crtc_state->crtc = crtc; } - crtc_state->enable = true; crtc_state->planes_changed = true; crtc_state->mode_changed = true; - drm_mode_copy(&crtc_state->mode, mode); + ret = drm_atomic_set_mode_for_crtc(crtc_state, mode); + if (ret) + goto out; drm_mode_copy(&crtc_state->adjusted_mode, adjusted_mode); if (crtc_funcs->atomic_check) { diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index e89db0c377ba..1e8c61f23294 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -109,6 +109,9 @@ drm_atomic_get_existing_connector_state(struct drm_atomic_state *state, return state->connector_states[index]; } +int __must_check +drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state, + struct drm_display_mode *mode); int __must_check drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state, struct drm_crtc *crtc); -- cgit v1.2.3 From 99cf4a29fa24461bbfe22125967188a18383eb5c Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Mon, 25 May 2015 19:11:51 +0100 Subject: drm/atomic: Add current-mode blob to CRTC state Add a blob property tracking the current mode to the CRTC state, and ensure it is properly updated and referenced. v2: Continue using crtc_state->mode inside getcrtc, instead of reading out the mode blob. Use IS_ERR and PTR_ERR from create_blob. Move set_mode_prop_for_crtc to later patch where it actually gets used. Enforce !!state->enable == !!state->mode_blob inside drm_atomic_crtc_check. Signed-off-by: Daniel Stone Tested-by: Sean Paul Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic.c | 32 +++++++++++++++++++++++++++++++- drivers/gpu/drm/drm_atomic_helper.c | 11 ++++++----- include/drm/drm_crtc.h | 3 +++ 3 files changed, 40 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index e749287390a3..327ccc71012f 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -304,11 +304,25 @@ EXPORT_SYMBOL(drm_atomic_get_crtc_state); int drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state, struct drm_display_mode *mode) { + struct drm_mode_modeinfo umode; + /* Early return for no change. */ if (mode && memcmp(&state->mode, mode, sizeof(*mode)) == 0) return 0; + if (state->mode_blob) + drm_property_unreference_blob(state->mode_blob); + state->mode_blob = NULL; + if (mode) { + drm_mode_convert_to_umode(&umode, mode); + state->mode_blob = + drm_property_create_blob(state->crtc->dev, + sizeof(umode), + &umode); + if (IS_ERR(state->mode_blob)) + return PTR_ERR(state->mode_blob); + drm_mode_copy(&state->mode, mode); state->enable = true; DRM_DEBUG_ATOMIC("Set [MODE:%s] for CRTC state %p\n", @@ -324,7 +338,6 @@ int drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state, } EXPORT_SYMBOL(drm_atomic_set_mode_for_crtc); - /** * drm_atomic_crtc_set_property - set property on CRTC * @crtc: the drm CRTC to set a property on @@ -410,6 +423,23 @@ static int drm_atomic_crtc_check(struct drm_crtc *crtc, return -EINVAL; } + /* The state->enable vs. state->mode_blob checks can be WARN_ON, + * as this is a kernel-internal detail that userspace should never + * be able to trigger. */ + if (drm_core_check_feature(crtc->dev, DRIVER_ATOMIC) && + WARN_ON(state->enable && !state->mode_blob)) { + DRM_DEBUG_ATOMIC("[CRTC:%d] enabled without mode blob\n", + crtc->base.id); + return -EINVAL; + } + + if (drm_core_check_feature(crtc->dev, DRIVER_ATOMIC) && + WARN_ON(!state->enable && state->mode_blob)) { + DRM_DEBUG_ATOMIC("[CRTC:%d] disabled with mode blob\n", + crtc->base.id); + return -EINVAL; + } + return 0; } diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index e69d4847e237..a900858fa265 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -2044,6 +2044,8 @@ EXPORT_SYMBOL(drm_atomic_helper_connector_dpms); */ void drm_atomic_helper_crtc_reset(struct drm_crtc *crtc) { + if (crtc->state && crtc->state->mode_blob) + drm_property_unreference_blob(crtc->state->mode_blob); kfree(crtc->state); crtc->state = kzalloc(sizeof(*crtc->state), GFP_KERNEL); @@ -2065,6 +2067,8 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, { memcpy(state, crtc->state, sizeof(*state)); + if (state->mode_blob) + drm_property_reference_blob(state->mode_blob); state->mode_changed = false; state->active_changed = false; state->planes_changed = false; @@ -2107,11 +2111,8 @@ EXPORT_SYMBOL(drm_atomic_helper_crtc_duplicate_state); void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) { - /* - * This is currently a placeholder so that drivers that subclass the - * state will automatically do the right thing if code is ever added - * to this function. - */ + if (state->mode_blob) + drm_property_unreference_blob(state->mode_blob); } EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 72b60dbe0891..c54fa4add792 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -299,6 +299,9 @@ struct drm_crtc_state { struct drm_display_mode mode; + /* blob property to expose current mode to atomic userspace */ + struct drm_property_blob *mode_blob; + struct drm_pending_vblank_event *event; struct drm_atomic_state *state; -- cgit v1.2.3 From 955f3c334f0fb2b843efad5cc6d3b7e141e9d666 Mon Sep 17 00:00:00 2001 From: Daniel Stone Date: Mon, 25 May 2015 19:11:52 +0100 Subject: drm/atomic: Add MODE_ID property Atomic modesetting: now with modesetting support. v2: Moved drm_atomic_set_mode_prop_for_crtc from previous patch; removed state->active fiddling, documented return code. Changed property type to DRM_MODE_PROP_BLOB. Signed-off-by: Daniel Stone Tested-by: Sean Paul Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_atomic.c | 57 +++++++++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/drm_crtc.c | 8 +++++++ include/drm/drm_atomic.h | 3 +++ include/drm/drm_crtc.h | 1 + 4 files changed, 68 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 327ccc71012f..c7e59b074e62 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -338,6 +338,51 @@ int drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state, } EXPORT_SYMBOL(drm_atomic_set_mode_for_crtc); +/** + * drm_atomic_set_mode_prop_for_crtc - set mode for CRTC + * @state: the CRTC whose incoming state to update + * @blob: pointer to blob property to use for mode + * + * Set a mode (originating from a blob property) on the desired CRTC state. + * This function will take a reference on the blob property for the CRTC state, + * and release the reference held on the state's existing mode property, if any + * was set. + * + * RETURNS: + * Zero on success, error code on failure. Cannot return -EDEADLK. + */ +int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state, + struct drm_property_blob *blob) +{ + if (blob == state->mode_blob) + return 0; + + if (state->mode_blob) + drm_property_unreference_blob(state->mode_blob); + state->mode_blob = NULL; + + if (blob) { + if (blob->length != sizeof(struct drm_mode_modeinfo) || + drm_mode_convert_umode(&state->mode, + (const struct drm_mode_modeinfo *) + blob->data)) + return -EINVAL; + + state->mode_blob = drm_property_reference_blob(blob); + state->enable = true; + DRM_DEBUG_ATOMIC("Set [MODE:%s] for CRTC state %p\n", + state->mode.name, state); + } else { + memset(&state->mode, 0, sizeof(state->mode)); + state->enable = false; + DRM_DEBUG_ATOMIC("Set [NOMODE] for CRTC state %p\n", + state); + } + + return 0; +} +EXPORT_SYMBOL(drm_atomic_set_mode_prop_for_crtc); + /** * drm_atomic_crtc_set_property - set property on CRTC * @crtc: the drm CRTC to set a property on @@ -360,10 +405,18 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc, { struct drm_device *dev = crtc->dev; struct drm_mode_config *config = &dev->mode_config; + int ret; - /* FIXME: Mode prop is missing, which also controls ->enable. */ if (property == config->prop_active) state->active = val; + else if (property == config->prop_mode_id) { + struct drm_property_blob *mode = + drm_property_lookup_blob(dev, val); + ret = drm_atomic_set_mode_prop_for_crtc(state, mode); + if (mode) + drm_property_unreference_blob(mode); + return ret; + } else if (crtc->funcs->atomic_set_property) return crtc->funcs->atomic_set_property(crtc, state, property, val); else @@ -388,6 +441,8 @@ int drm_atomic_crtc_get_property(struct drm_crtc *crtc, if (property == config->prop_active) *val = state->active; + else if (property == config->prop_mode_id) + *val = (state->mode_blob) ? state->mode_blob->base.id : 0; else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 098c94e53fdf..77f87b23a6e7 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -688,6 +688,7 @@ int drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc, if (drm_core_check_feature(dev, DRIVER_ATOMIC)) { drm_object_attach_property(&crtc->base, config->prop_active, 0); + drm_object_attach_property(&crtc->base, config->prop_mode_id, 0); } return 0; @@ -1454,6 +1455,13 @@ static int drm_mode_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.prop_active = prop; + prop = drm_property_create(dev, + DRM_MODE_PROP_ATOMIC | DRM_MODE_PROP_BLOB, + "MODE_ID", 0); + if (!prop) + return -ENOMEM; + dev->mode_config.prop_mode_id = prop; + return 0; } diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index 1e8c61f23294..55f46049e4a0 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -113,6 +113,9 @@ int __must_check drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state, struct drm_display_mode *mode); int __must_check +drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state, + struct drm_property_blob *blob); +int __must_check drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state, struct drm_crtc *crtc); void drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state, diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index c54fa4add792..3b4d8a4a23fb 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1146,6 +1146,7 @@ struct drm_mode_config { struct drm_property *prop_fb_id; struct drm_property *prop_crtc_id; struct drm_property *prop_active; + struct drm_property *prop_mode_id; /* DVI-I properties */ struct drm_property *dvi_i_subconnector_property; -- cgit v1.2.3 From 72b9076b2887add930d3b102760f09d02ffbfbe7 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Wed, 29 Apr 2015 19:40:33 +0200 Subject: drm/radeon: add a GPU reset counter queryable by userspace MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Userspace will be able to tell whether a GPU reset occured by comparing an old referece value of the counter with a new value. Reviewed-by: Christian König Signed-off-by: Marek Olšák Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_device.c | 2 ++ drivers/gpu/drm/radeon/radeon_drv.c | 3 ++- drivers/gpu/drm/radeon/radeon_kms.c | 3 +++ include/uapi/drm/radeon_drm.h | 1 + 5 files changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 46eb0fa75a61..352870cbb8b8 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -2435,6 +2435,7 @@ struct radeon_device { atomic64_t vram_usage; atomic64_t gtt_usage; atomic64_t num_bytes_moved; + atomic_t gpu_reset_counter; /* ACPI interface */ struct radeon_atif atif; struct radeon_atcs atcs; diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index b7ca4c514621..13e207e0dff0 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -1725,6 +1725,8 @@ int radeon_gpu_reset(struct radeon_device *rdev) return 0; } + atomic_inc(&rdev->gpu_reset_counter); + radeon_save_bios_scratch_regs(rdev); /* block TTM */ resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 7d620d4b3f31..5751446677d3 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -90,9 +90,10 @@ * CS to GPU on >= r600 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support * 2.42.0 - Add VCE/VUI (Video Usability Information) support + * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER */ #define KMS_DRIVER_MAJOR 2 -#define KMS_DRIVER_MINOR 42 +#define KMS_DRIVER_MINOR 43 #define KMS_DRIVER_PATCHLEVEL 0 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); int radeon_driver_unload_kms(struct drm_device *dev); diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index 7b2a7335cc5d..9632e886ddc3 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -576,6 +576,9 @@ static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file if (radeon_get_allowed_info_register(rdev, *value, value)) return -EINVAL; break; + case RADEON_INFO_GPU_RESET_COUNTER: + *value = atomic_read(&rdev->gpu_reset_counter); + break; default: DRM_DEBUG_KMS("Invalid request %d\n", info->request); return -EINVAL; diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h index 871e73f99a4d..573cb86a3d6e 100644 --- a/include/uapi/drm/radeon_drm.h +++ b/include/uapi/drm/radeon_drm.h @@ -1038,6 +1038,7 @@ struct drm_radeon_cs { #define RADEON_INFO_CURRENT_GPU_SCLK 0x22 #define RADEON_INFO_CURRENT_GPU_MCLK 0x23 #define RADEON_INFO_READ_REG 0x24 +#define RADEON_INFO_GPU_RESET_COUNTER 0x25 struct drm_radeon_info { uint32_t request; -- cgit v1.2.3 From fa0cf2f246bb1cac502ba7c36082ad7a7b6deb40 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 May 2015 22:01:47 +0200 Subject: drm/radeon: rework VCE FW size calculation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Previously we were completely over allocating, fix this by actually implementing the size calculation. Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon.h | 2 -- drivers/gpu/drm/radeon/radeon_asic.h | 1 + drivers/gpu/drm/radeon/radeon_vce.c | 3 +-- drivers/gpu/drm/radeon/vce_v2_0.c | 16 +++++++++++++--- 4 files changed, 15 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 352870cbb8b8..5999560d4284 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1709,8 +1709,6 @@ int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, * VCE */ #define RADEON_MAX_VCE_HANDLES 16 -#define RADEON_VCE_STACK_SIZE (1024*1024) -#define RADEON_VCE_HEAP_SIZE (4*1024*1024) struct radeon_vce { struct radeon_bo *vcpu_bo; diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index a3ca8cd305c5..cb7787fedf1b 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -974,6 +974,7 @@ int vce_v1_0_init(struct radeon_device *rdev); int vce_v1_0_start(struct radeon_device *rdev); /* vce v2.0 */ +unsigned vce_v2_0_bo_size(struct radeon_device *rdev); int vce_v2_0_resume(struct radeon_device *rdev); #endif diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index 0de5711ac508..5b952bdfa68d 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c @@ -123,8 +123,7 @@ int radeon_vce_init(struct radeon_device *rdev) /* allocate firmware, stack and heap BO */ - size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) + - RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE; + size = vce_v2_0_bo_size(rdev); r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 0, NULL, NULL, &rdev->vce.vcpu_bo); diff --git a/drivers/gpu/drm/radeon/vce_v2_0.c b/drivers/gpu/drm/radeon/vce_v2_0.c index fbbe78fbd087..cdeaab7c7b1e 100644 --- a/drivers/gpu/drm/radeon/vce_v2_0.c +++ b/drivers/gpu/drm/radeon/vce_v2_0.c @@ -31,6 +31,10 @@ #include "radeon_asic.h" #include "cikd.h" +#define VCE_V2_0_FW_SIZE (256 * 1024) +#define VCE_V2_0_STACK_SIZE (64 * 1024) +#define VCE_V2_0_DATA_SIZE (23552 * RADEON_MAX_VCE_HANDLES) + static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) { u32 tmp; @@ -140,6 +144,12 @@ static void vce_v2_0_init_cg(struct radeon_device *rdev) WREG32(VCE_CLOCK_GATING_B, tmp); } +unsigned vce_v2_0_bo_size(struct radeon_device *rdev) +{ + WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE); + return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE; +} + int vce_v2_0_resume(struct radeon_device *rdev) { uint64_t addr = rdev->vce.gpu_addr; @@ -159,17 +169,17 @@ int vce_v2_0_resume(struct radeon_device *rdev) WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8); addr &= 0xff; - size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size); + size = VCE_V2_0_FW_SIZE; WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); WREG32(VCE_VCPU_CACHE_SIZE0, size); addr += size; - size = RADEON_VCE_STACK_SIZE; + size = VCE_V2_0_STACK_SIZE; WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); WREG32(VCE_VCPU_CACHE_SIZE1, size); addr += size; - size = RADEON_VCE_HEAP_SIZE; + size = VCE_V2_0_DATA_SIZE; WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); WREG32(VCE_VCPU_CACHE_SIZE2, size); -- cgit v1.2.3 From c11d75c87a60c6f6493a55acc029ff644b1bc1a8 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 May 2015 22:01:48 +0200 Subject: drm/radeon: allow some more VCE firmware versions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They seem to work fine with the kernel interface. Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_vce.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index 5b952bdfa68d..aa5d9bac70fa 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c @@ -118,7 +118,9 @@ int radeon_vce_init(struct radeon_device *rdev) rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8); /* we can only work with this fw version for now */ - if (rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8))) + if ((rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8))) && + (rdev->vce.fw_version != ((50 << 24) | (0 << 16) | (1 << 8))) && + (rdev->vce.fw_version != ((50 << 24) | (1 << 16) | (2 << 8)))) return -EINVAL; /* allocate firmware, stack and heap BO */ -- cgit v1.2.3 From b7af630c13adc4be3bd8725f3a6e22fd89cb2938 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 May 2015 22:01:49 +0200 Subject: drm/radeon: implement si_set_vce_clocks v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For setting clocks with VCE v1.0 v2: (chk) rebased on current tree Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon.h | 7 ++ drivers/gpu/drm/radeon/radeon_asic.c | 1 + drivers/gpu/drm/radeon/radeon_asic.h | 1 + drivers/gpu/drm/radeon/si.c | 121 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/sid.h | 27 ++++++++ 5 files changed, 157 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 5999560d4284..3d74fdcac4bf 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -2578,6 +2578,13 @@ static inline struct radeon_fence *to_radeon_fence(struct fence *f) tmp_ |= ((val) & ~(mask)); \ WREG32_PLL(reg, tmp_); \ } while (0) +#define WREG32_SMC_P(reg, val, mask) \ + do { \ + uint32_t tmp_ = RREG32_SMC(reg); \ + tmp_ &= (mask); \ + tmp_ |= ((val) & ~(mask)); \ + WREG32_SMC(reg, tmp_); \ + } while (0) #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 8dbf5083c4ff..4227b30b5ce6 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -1973,6 +1973,7 @@ static struct radeon_asic si_asic = { .set_pcie_lanes = &r600_set_pcie_lanes, .set_clock_gating = NULL, .set_uvd_clocks = &si_set_uvd_clocks, + .set_vce_clocks = &si_set_vce_clocks, .get_temperature = &si_get_temp, }, .dpm = { diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index cb7787fedf1b..0469d440764b 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -745,6 +745,7 @@ void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, u32 si_get_xclk(struct radeon_device *rdev); uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); +int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); int si_get_temp(struct radeon_device *rdev); int si_get_allowed_info_register(struct radeon_device *rdev, u32 reg, u32 *val); diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 5326f753e107..0c04f6d1faf8 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -7675,3 +7675,124 @@ static void si_program_aspm(struct radeon_device *rdev) } } } + +int si_vce_send_vcepll_ctlreq(struct radeon_device *rdev) +{ + unsigned i; + + /* make sure VCEPLL_CTLREQ is deasserted */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); + + mdelay(10); + + /* assert UPLL_CTLREQ */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); + + /* wait for CTLACK and CTLACK2 to get asserted */ + for (i = 0; i < 100; ++i) { + uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; + if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) + break; + mdelay(10); + } + + /* deassert UPLL_CTLREQ */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); + + if (i == 100) { + DRM_ERROR("Timeout setting UVD clocks!\n"); + return -ETIMEDOUT; + } + + return 0; +} + +int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) +{ + unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; + int r; + + /* bypass evclk and ecclk with bclk */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, + EVCLK_SRC_SEL(1) | ECCLK_SRC_SEL(1), + ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK)); + + /* put PLL in bypass mode */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK, + ~VCEPLL_BYPASS_EN_MASK); + + if (!evclk || !ecclk) { + /* keep the Bypass mode, put PLL to sleep */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, + ~VCEPLL_SLEEP_MASK); + return 0; + } + + r = radeon_uvd_calc_upll_dividers(rdev, evclk, ecclk, 125000, 250000, + 16384, 0x03FFFFFF, 0, 128, 5, + &fb_div, &evclk_div, &ecclk_div); + if (r) + return r; + + /* set RESET_ANTI_MUX to 0 */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); + + /* set VCO_MODE to 1 */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK, + ~VCEPLL_VCO_MODE_MASK); + + /* toggle VCEPLL_SLEEP to 1 then back to 0 */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, + ~VCEPLL_SLEEP_MASK); + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK); + + /* deassert VCEPLL_RESET */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); + + mdelay(1); + + r = si_vce_send_vcepll_ctlreq(rdev); + if (r) + return r; + + /* assert VCEPLL_RESET again */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK); + + /* disable spread spectrum. */ + WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); + + /* set feedback divider */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK); + + /* set ref divider to 0 */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK); + + /* set PDIV_A and PDIV_B */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, + VCEPLL_PDIV_A(evclk_div) | VCEPLL_PDIV_B(ecclk_div), + ~(VCEPLL_PDIV_A_MASK | VCEPLL_PDIV_B_MASK)); + + /* give the PLL some time to settle */ + mdelay(15); + + /* deassert PLL_RESET */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); + + mdelay(15); + + /* switch from bypass mode to normal mode */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK); + + r = si_vce_send_vcepll_ctlreq(rdev); + if (r) + return r; + + /* switch VCLK and DCLK selection */ + WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, + EVCLK_SRC_SEL(16) | ECCLK_SRC_SEL(16), + ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK)); + + mdelay(100); + + return 0; +} diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 3afac3013983..1630440c5136 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h @@ -1917,4 +1917,31 @@ #define VCE_CMD_IB_AUTO 0x00000005 #define VCE_CMD_SEMAPHORE 0x00000006 +/* discrete vce clocks */ +#define CG_VCEPLL_FUNC_CNTL 0xc0030600 +# define VCEPLL_RESET_MASK 0x00000001 +# define VCEPLL_SLEEP_MASK 0x00000002 +# define VCEPLL_BYPASS_EN_MASK 0x00000004 +# define VCEPLL_CTLREQ_MASK 0x00000008 +# define VCEPLL_VCO_MODE_MASK 0x00000600 +# define VCEPLL_REF_DIV_MASK 0x003F0000 +# define VCEPLL_CTLACK_MASK 0x40000000 +# define VCEPLL_CTLACK2_MASK 0x80000000 +#define CG_VCEPLL_FUNC_CNTL_2 0xc0030601 +# define VCEPLL_PDIV_A(x) ((x) << 0) +# define VCEPLL_PDIV_A_MASK 0x0000007F +# define VCEPLL_PDIV_B(x) ((x) << 8) +# define VCEPLL_PDIV_B_MASK 0x00007F00 +# define EVCLK_SRC_SEL(x) ((x) << 20) +# define EVCLK_SRC_SEL_MASK 0x01F00000 +# define ECCLK_SRC_SEL(x) ((x) << 25) +# define ECCLK_SRC_SEL_MASK 0x3E000000 +#define CG_VCEPLL_FUNC_CNTL_3 0xc0030602 +# define VCEPLL_FB_DIV(x) ((x) << 0) +# define VCEPLL_FB_DIV_MASK 0x01FFFFFF +#define CG_VCEPLL_FUNC_CNTL_4 0xc0030603 +#define CG_VCEPLL_FUNC_CNTL_5 0xc0030604 +#define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606 +# define VCEPLL_SSEN_MASK 0x00000001 + #endif -- cgit v1.2.3 From 0fda42ac40ac7edf62ebb750be41a34902d2fdfb Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 11 May 2015 22:01:50 +0200 Subject: drm/radeon: implement tn_set_vce_clocks This implements the function to set the vce clocks on TN hardware. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ni.c | 31 +++++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/nid.h | 7 +++++++ drivers/gpu/drm/radeon/radeon_asic.c | 1 + drivers/gpu/drm/radeon/radeon_asic.h | 1 + 4 files changed, 40 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index aba2f428c0a8..a6d940fc44e8 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -2554,3 +2554,34 @@ void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write(ring, 0x0); } + +int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) +{ + struct atom_clock_dividers dividers; + int r, i; + + r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + ecclk, false, ÷rs); + if (r) + return r; + + for (i = 0; i < 100; i++) { + if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK)); + + for (i = 0; i < 100; i++) { + if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + return 0; +} diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h index 3b290838918c..47eb49b77d32 100644 --- a/drivers/gpu/drm/radeon/nid.h +++ b/drivers/gpu/drm/radeon/nid.h @@ -46,6 +46,13 @@ #define DMIF_ADDR_CONFIG 0xBD4 +/* fusion vce clocks */ +#define CG_ECLK_CNTL 0x620 +# define ECLK_DIVIDER_MASK 0x7f +# define ECLK_DIR_CNTL_EN (1 << 8) +#define CG_ECLK_STATUS 0x624 +# define ECLK_STATUS (1 << 0) + /* DCE6 only */ #define DMIF_ADDR_CALC 0xC00 diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 4227b30b5ce6..b37b22bdf579 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -1838,6 +1838,7 @@ static struct radeon_asic trinity_asic = { .set_pcie_lanes = NULL, .set_clock_gating = NULL, .set_uvd_clocks = &sumo_set_uvd_clocks, + .set_vce_clocks = &tn_set_vce_clocks, .get_temperature = &tn_get_temp, }, .dpm = { diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 0469d440764b..629f2910a33e 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -694,6 +694,7 @@ int trinity_dpm_force_performance_level(struct radeon_device *rdev, void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev); u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev); +int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); /* DCE6 - SI */ void dce6_bandwidth_update(struct radeon_device *rdev); -- cgit v1.2.3 From 11fe3d6edb40b9ea888bf0c5630f2550af60e20d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 11 May 2015 22:01:51 +0200 Subject: drm/radeon/dpm: add vce dpm support for TN Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/trinity_dpm.c | 76 ++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c index a5b02c575d77..e0d07802a906 100644 --- a/drivers/gpu/drm/radeon/trinity_dpm.c +++ b/drivers/gpu/drm/radeon/trinity_dpm.c @@ -985,6 +985,15 @@ static void trinity_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev trinity_setup_uvd_clocks(rdev, new_rps, old_rps); } +static void trinity_set_vce_clock(struct radeon_device *rdev, + struct radeon_ps *new_rps, + struct radeon_ps *old_rps) +{ + if ((old_rps->evclk != new_rps->evclk) || + (old_rps->ecclk != new_rps->ecclk)) + radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); +} + static void trinity_program_ttt(struct radeon_device *rdev) { struct trinity_power_info *pi = trinity_get_pi(rdev); @@ -1246,6 +1255,7 @@ int trinity_dpm_set_power_state(struct radeon_device *rdev) trinity_force_level_0(rdev); trinity_unforce_levels(rdev); trinity_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); + trinity_set_vce_clock(rdev, new_ps, old_ps); } trinity_release_mutex(rdev); @@ -1483,7 +1493,35 @@ static void trinity_adjust_uvd_state(struct radeon_device *rdev, } } +static int trinity_get_vce_clock_voltage(struct radeon_device *rdev, + u32 evclk, u32 ecclk, u16 *voltage) +{ + u32 i; + int ret = -EINVAL; + struct radeon_vce_clock_voltage_dependency_table *table = + &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + + if (((evclk == 0) && (ecclk == 0)) || + (table && (table->count == 0))) { + *voltage = 0; + return 0; + } + + for (i = 0; i < table->count; i++) { + if ((evclk <= table->entries[i].evclk) && + (ecclk <= table->entries[i].ecclk)) { + *voltage = table->entries[i].v; + ret = 0; + break; + } + } + + /* if no match return the highest voltage */ + if (ret) + *voltage = table->entries[table->count - 1].v; + return ret; +} static void trinity_apply_state_adjust_rules(struct radeon_device *rdev, struct radeon_ps *new_rps, @@ -1496,6 +1534,7 @@ static void trinity_apply_state_adjust_rules(struct radeon_device *rdev, u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ u32 i; + u16 min_vce_voltage; bool force_high; u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; @@ -1504,6 +1543,14 @@ static void trinity_apply_state_adjust_rules(struct radeon_device *rdev, trinity_adjust_uvd_state(rdev, new_rps); + if (new_rps->vce_active) { + new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; + new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; + } else { + new_rps->evclk = 0; + new_rps->ecclk = 0; + } + for (i = 0; i < ps->num_levels; i++) { if (ps->levels[i].vddc_index < min_voltage) ps->levels[i].vddc_index = min_voltage; @@ -1512,6 +1559,17 @@ static void trinity_apply_state_adjust_rules(struct radeon_device *rdev, ps->levels[i].sclk = trinity_get_valid_engine_clock(rdev, min_sclk); + /* patch in vce limits */ + if (new_rps->vce_active) { + /* sclk */ + if (ps->levels[i].sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) + ps->levels[i].sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; + /* vddc */ + trinity_get_vce_clock_voltage(rdev, new_rps->evclk, new_rps->ecclk, &min_vce_voltage); + if (ps->levels[i].vddc_index < min_vce_voltage) + ps->levels[i].vddc_index = min_vce_voltage; + } + ps->levels[i].ds_divider_index = sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr); @@ -1733,6 +1791,19 @@ static int trinity_parse_power_table(struct radeon_device *rdev) power_state_offset += 2 + power_state->v2.ucNumDPMLevels; } rdev->pm.dpm.num_ps = state_array->ucNumEntries; + + /* fill in the vce power states */ + for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { + u32 sclk; + clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; + clock_info = (union pplib_clock_info *) + &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; + sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); + sclk |= clock_info->sumo.ucEngineClockHigh << 16; + rdev->pm.dpm.vce_states[i].sclk = sclk; + rdev->pm.dpm.vce_states[i].mclk = 0; + } + return 0; } @@ -1914,6 +1985,10 @@ int trinity_dpm_init(struct radeon_device *rdev) if (ret) return ret; + ret = r600_parse_extended_power_table(rdev); + if (ret) + return ret; + ret = trinity_parse_power_table(rdev); if (ret) return ret; @@ -2000,6 +2075,7 @@ void trinity_dpm_fini(struct radeon_device *rdev) } kfree(rdev->pm.dpm.ps); kfree(rdev->pm.dpm.priv); + r600_free_extended_power_table(rdev); } u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low) -- cgit v1.2.3 From 11586cf04030e936e4549c7beb5e87f3f7267f80 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 11 May 2015 22:01:52 +0200 Subject: drm/radeon/dpm: add vce support for SI Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/si_dpm.c | 102 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 98 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index ff8b83f5e929..69cd4ca91685 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c @@ -2928,6 +2928,56 @@ static struct si_dpm_quirk si_dpm_quirk_list[] = { { 0, 0, 0, 0 }, }; +static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, + u16 vce_voltage) +{ + u16 highest_leakage = 0; + struct si_power_info *si_pi = si_get_pi(rdev); + int i; + + for (i = 0; i < si_pi->leakage_voltage.count; i++){ + if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) + highest_leakage = si_pi->leakage_voltage.entries[i].voltage; + } + + if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) + return highest_leakage; + + return vce_voltage; +} + +static int si_get_vce_clock_voltage(struct radeon_device *rdev, + u32 evclk, u32 ecclk, u16 *voltage) +{ + u32 i; + int ret = -EINVAL; + struct radeon_vce_clock_voltage_dependency_table *table = + &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + + if (((evclk == 0) && (ecclk == 0)) || + (table && (table->count == 0))) { + *voltage = 0; + return 0; + } + + for (i = 0; i < table->count; i++) { + if ((evclk <= table->entries[i].evclk) && + (ecclk <= table->entries[i].ecclk)) { + *voltage = table->entries[i].v; + ret = 0; + break; + } + } + + /* if no match return the highest voltage */ + if (ret) + *voltage = table->entries[table->count - 1].v; + + *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); + + return ret; +} + static void si_apply_state_adjust_rules(struct radeon_device *rdev, struct radeon_ps *rps) { @@ -2936,7 +2986,7 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, bool disable_mclk_switching = false; bool disable_sclk_switching = false; u32 mclk, sclk; - u16 vddc, vddci; + u16 vddc, vddci, min_vce_voltage = 0; u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; u32 max_sclk = 0, max_mclk = 0; int i; @@ -2955,6 +3005,16 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, ++p; } + if (rps->vce_active) { + rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; + rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; + si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, + &min_vce_voltage); + } else { + rps->evclk = 0; + rps->ecclk = 0; + } + if ((rdev->pm.dpm.new_active_crtc_count > 1) || ni_dpm_vblank_too_short(rdev)) disable_mclk_switching = true; @@ -3035,6 +3095,13 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, vddc = ps->performance_levels[0].vddc; } + if (rps->vce_active) { + if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) + sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; + if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) + mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; + } + /* adjusted low state */ ps->performance_levels[0].sclk = sclk; ps->performance_levels[0].mclk = mclk; @@ -3084,6 +3151,8 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, &ps->performance_levels[i]); for (i = 0; i < ps->performance_level_count; i++) { + if (ps->performance_levels[i].vddc < min_vce_voltage) + ps->performance_levels[i].vddc = min_vce_voltage; btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, ps->performance_levels[i].sclk, max_limits->vddc, &ps->performance_levels[i].vddc); @@ -3110,7 +3179,6 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) ps->dc_compatible = false; } - } #if 0 @@ -5859,6 +5927,15 @@ static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, } } +static void si_set_vce_clock(struct radeon_device *rdev, + struct radeon_ps *new_rps, + struct radeon_ps *old_rps) +{ + if ((old_rps->evclk != new_rps->evclk) || + (old_rps->ecclk != new_rps->ecclk)) + radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); +} + void si_dpm_setup_asic(struct radeon_device *rdev) { int r; @@ -6547,6 +6624,7 @@ int si_dpm_set_power_state(struct radeon_device *rdev) return ret; } ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); + si_set_vce_clock(rdev, new_ps, old_ps); if (eg_pi->pcie_performance_request) si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); @@ -6793,6 +6871,21 @@ static int si_parse_power_table(struct radeon_device *rdev) power_state_offset += 2 + power_state->v2.ucNumDPMLevels; } rdev->pm.dpm.num_ps = state_array->ucNumEntries; + + /* fill in the vce power states */ + for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { + u32 sclk, mclk; + clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; + clock_info = (union pplib_clock_info *) + &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; + sclk = le16_to_cpu(clock_info->si.usEngineClockLow); + sclk |= clock_info->si.ucEngineClockHigh << 16; + mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); + mclk |= clock_info->si.ucMemoryClockHigh << 16; + rdev->pm.dpm.vce_states[i].sclk = sclk; + rdev->pm.dpm.vce_states[i].mclk = mclk; + } + return 0; } @@ -6837,10 +6930,11 @@ int si_dpm_init(struct radeon_device *rdev) if (ret) return ret; - ret = si_parse_power_table(rdev); + ret = r600_parse_extended_power_table(rdev); if (ret) return ret; - ret = r600_parse_extended_power_table(rdev); + + ret = si_parse_power_table(rdev); if (ret) return ret; -- cgit v1.2.3 From a918efab631a5112d9d168700458317ad77f269c Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 May 2015 22:01:53 +0200 Subject: drm/radeon: add VCE 1.0 support v4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initial support for VCE 1.0 using newest firmware. v2: rebased v3: fix for TN v4: fix FW size calculation Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ni.c | 46 ++++++++++++ drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_asic.c | 17 +++++ drivers/gpu/drm/radeon/radeon_asic.h | 3 + drivers/gpu/drm/radeon/radeon_vce.c | 23 +++++- drivers/gpu/drm/radeon/si.c | 46 ++++++++++++ drivers/gpu/drm/radeon/sid.h | 1 + drivers/gpu/drm/radeon/vce_v1_0.c | 140 +++++++++++++++++++++++++++++++++++ 8 files changed, 274 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index a6d940fc44e8..9269e188cd92 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -2041,6 +2041,25 @@ static int cayman_startup(struct radeon_device *rdev) if (r) rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; + if (rdev->family == CHIP_ARUBA) { + r = radeon_vce_resume(rdev); + if (!r) + r = vce_v1_0_resume(rdev); + + if (!r) + r = radeon_fence_driver_start_ring(rdev, + TN_RING_TYPE_VCE1_INDEX); + if (!r) + r = radeon_fence_driver_start_ring(rdev, + TN_RING_TYPE_VCE2_INDEX); + + if (r) { + dev_err(rdev->dev, "VCE init error (%d).\n", r); + rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; + rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; + } + } + r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); if (r) { dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); @@ -2118,6 +2137,19 @@ static int cayman_startup(struct radeon_device *rdev) DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); } + ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; + if (ring->ring_size) + r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); + + ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; + if (ring->ring_size) + r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); + + if (!r) + r = vce_v1_0_init(rdev); + else if (r != -ENOENT) + DRM_ERROR("radeon: failed initializing VCE (%d).\n", r); + r = radeon_ib_pool_init(rdev); if (r) { dev_err(rdev->dev, "IB initialization failed (%d).\n", r); @@ -2273,6 +2305,19 @@ int cayman_init(struct radeon_device *rdev) r600_ring_init(rdev, ring, 4096); } + if (rdev->family == CHIP_ARUBA) { + r = radeon_vce_init(rdev); + if (!r) { + ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; + ring->ring_obj = NULL; + r600_ring_init(rdev, ring, 4096); + + ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; + ring->ring_obj = NULL; + r600_ring_init(rdev, ring, 4096); + } + } + rdev->ih.ring_obj = NULL; r600_ih_ring_init(rdev, 64 * 1024); @@ -2326,6 +2371,7 @@ void cayman_fini(struct radeon_device *rdev) radeon_irq_kms_fini(rdev); uvd_v1_0_fini(rdev); radeon_uvd_fini(rdev); + radeon_vce_fini(rdev); cayman_pcie_gart_fini(rdev); r600_vram_scratch_fini(rdev); radeon_gem_fini(rdev); diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 3d74fdcac4bf..ccebf6279c05 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1719,6 +1719,7 @@ struct radeon_vce { struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; unsigned img_size[RADEON_MAX_VCE_HANDLES]; struct delayed_work idle_work; + uint32_t keyselect; }; int radeon_vce_init(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index b37b22bdf579..eaf909e7feb3 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -1761,6 +1761,19 @@ static struct radeon_asic cayman_asic = { }, }; +static struct radeon_asic_ring trinity_vce_ring = { + .ib_execute = &radeon_vce_ib_execute, + .emit_fence = &radeon_vce_fence_emit, + .emit_semaphore = &radeon_vce_semaphore_emit, + .cs_parse = &radeon_vce_cs_parse, + .ring_test = &radeon_vce_ring_test, + .ib_test = &radeon_vce_ib_test, + .is_lockup = &radeon_ring_test_lockup, + .get_rptr = &vce_v1_0_get_rptr, + .get_wptr = &vce_v1_0_get_wptr, + .set_wptr = &vce_v1_0_set_wptr, +}; + static struct radeon_asic trinity_asic = { .init = &cayman_init, .fini = &cayman_fini, @@ -1794,6 +1807,8 @@ static struct radeon_asic trinity_asic = { [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, + [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, + [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, }, .irq = { .set = &evergreen_irq_set, @@ -1930,6 +1945,8 @@ static struct radeon_asic si_asic = { [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, + [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, + [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, }, .irq = { .set = &si_irq_set, diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 629f2910a33e..e0aa33262eac 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -972,6 +972,9 @@ uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, struct radeon_ring *ring); void vce_v1_0_set_wptr(struct radeon_device *rdev, struct radeon_ring *ring); +int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data); +unsigned vce_v1_0_bo_size(struct radeon_device *rdev); +int vce_v1_0_resume(struct radeon_device *rdev); int vce_v1_0_init(struct radeon_device *rdev); int vce_v1_0_start(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index aa5d9bac70fa..574f62bbd215 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c @@ -38,8 +38,10 @@ #define VCE_IDLE_TIMEOUT_MS 1000 /* Firmware Names */ +#define FIRMWARE_TAHITI "radeon/TAHITI_vce.bin" #define FIRMWARE_BONAIRE "radeon/BONAIRE_vce.bin" +MODULE_FIRMWARE(FIRMWARE_TAHITI); MODULE_FIRMWARE(FIRMWARE_BONAIRE); static void radeon_vce_idle_work_handler(struct work_struct *work); @@ -63,6 +65,14 @@ int radeon_vce_init(struct radeon_device *rdev) INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler); switch (rdev->family) { + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_VERDE: + case CHIP_OLAND: + case CHIP_ARUBA: + fw_name = FIRMWARE_TAHITI; + break; + case CHIP_BONAIRE: case CHIP_KAVERI: case CHIP_KABINI: @@ -125,7 +135,10 @@ int radeon_vce_init(struct radeon_device *rdev) /* allocate firmware, stack and heap BO */ - size = vce_v2_0_bo_size(rdev); + if (rdev->family < CHIP_BONAIRE) + size = vce_v1_0_bo_size(rdev); + else + size = vce_v2_0_bo_size(rdev); r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 0, NULL, NULL, &rdev->vce.vcpu_bo); @@ -226,13 +239,17 @@ int radeon_vce_resume(struct radeon_device *rdev) return r; } - memcpy(cpu_addr, rdev->vce_fw->data, rdev->vce_fw->size); + memset(cpu_addr, 0, radeon_bo_size(rdev->vce.vcpu_bo)); + if (rdev->family < CHIP_BONAIRE) + r = vce_v1_0_load_fw(rdev, cpu_addr); + else + memcpy(cpu_addr, rdev->vce_fw->data, rdev->vce_fw->size); radeon_bo_kunmap(rdev->vce.vcpu_bo); radeon_bo_unreserve(rdev->vce.vcpu_bo); - return 0; + return r; } /** diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 0c04f6d1faf8..34c3739c87cf 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -6907,6 +6907,22 @@ static int si_startup(struct radeon_device *rdev) rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; } + r = radeon_vce_resume(rdev); + if (!r) { + r = vce_v1_0_resume(rdev); + if (!r) + r = radeon_fence_driver_start_ring(rdev, + TN_RING_TYPE_VCE1_INDEX); + if (!r) + r = radeon_fence_driver_start_ring(rdev, + TN_RING_TYPE_VCE2_INDEX); + } + if (r) { + dev_err(rdev->dev, "VCE init error (%d).\n", r); + rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; + rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; + } + /* Enable IRQ */ if (!rdev->irq.installed) { r = radeon_irq_kms_init(rdev); @@ -6975,6 +6991,23 @@ static int si_startup(struct radeon_device *rdev) } } + r = -ENOENT; + + ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; + if (ring->ring_size) + r = radeon_ring_init(rdev, ring, ring->ring_size, 0, + VCE_CMD_NO_OP); + + ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; + if (ring->ring_size) + r = radeon_ring_init(rdev, ring, ring->ring_size, 0, + VCE_CMD_NO_OP); + + if (!r) + r = vce_v1_0_init(rdev); + else if (r != -ENOENT) + DRM_ERROR("radeon: failed initializing VCE (%d).\n", r); + r = radeon_ib_pool_init(rdev); if (r) { dev_err(rdev->dev, "IB initialization failed (%d).\n", r); @@ -7033,6 +7066,7 @@ int si_suspend(struct radeon_device *rdev) if (rdev->has_uvd) { uvd_v1_0_fini(rdev); radeon_uvd_suspend(rdev); + radeon_vce_suspend(rdev); } si_fini_pg(rdev); si_fini_cg(rdev); @@ -7140,6 +7174,17 @@ int si_init(struct radeon_device *rdev) } } + r = radeon_vce_init(rdev); + if (!r) { + ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; + ring->ring_obj = NULL; + r600_ring_init(rdev, ring, 4096); + + ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; + ring->ring_obj = NULL; + r600_ring_init(rdev, ring, 4096); + } + rdev->ih.ring_obj = NULL; r600_ih_ring_init(rdev, 64 * 1024); @@ -7191,6 +7236,7 @@ void si_fini(struct radeon_device *rdev) if (rdev->has_uvd) { uvd_v1_0_fini(rdev); radeon_uvd_fini(rdev); + radeon_vce_fini(rdev); } si_pcie_gart_fini(rdev); r600_vram_scratch_fini(rdev); diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 1630440c5136..4823a075f0c3 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h @@ -1879,6 +1879,7 @@ #define VCE_VCPU_CACHE_SIZE1 0x20030 #define VCE_VCPU_CACHE_OFFSET2 0x20034 #define VCE_VCPU_CACHE_SIZE2 0x20038 +#define VCE_VCPU_SCRATCH7 0x200dc #define VCE_SOFT_RESET 0x20120 #define VCE_ECPU_SOFT_RESET (1 << 0) #define VCE_FME_SOFT_RESET (1 << 2) diff --git a/drivers/gpu/drm/radeon/vce_v1_0.c b/drivers/gpu/drm/radeon/vce_v1_0.c index b44d9c842f7b..81dd39b8de1c 100644 --- a/drivers/gpu/drm/radeon/vce_v1_0.c +++ b/drivers/gpu/drm/radeon/vce_v1_0.c @@ -31,6 +31,23 @@ #include "radeon_asic.h" #include "sid.h" +#define VCE_V1_0_FW_SIZE (256 * 1024) +#define VCE_V1_0_STACK_SIZE (64 * 1024) +#define VCE_V1_0_DATA_SIZE (7808 * (RADEON_MAX_VCE_HANDLES + 1)) + +struct vce_v1_0_fw_signature +{ + int32_t off; + uint32_t len; + int32_t num; + struct { + uint32_t chip_id; + uint32_t keyselect; + uint32_t nonce[4]; + uint32_t sigval[4]; + } val[8]; +}; + /** * vce_v1_0_get_rptr - get read pointer * @@ -82,6 +99,129 @@ void vce_v1_0_set_wptr(struct radeon_device *rdev, WREG32(VCE_RB_WPTR2, ring->wptr); } +int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data) +{ + struct vce_v1_0_fw_signature *sign = (void*)rdev->vce_fw->data; + uint32_t chip_id; + int i; + + switch (rdev->family) { + case CHIP_TAHITI: + chip_id = 0x01000014; + break; + case CHIP_VERDE: + chip_id = 0x01000015; + break; + case CHIP_PITCAIRN: + case CHIP_OLAND: + chip_id = 0x01000016; + break; + case CHIP_ARUBA: + chip_id = 0x01000017; + break; + default: + return -EINVAL; + } + + for (i = 0; i < sign->num; ++i) { + if (sign->val[i].chip_id == chip_id) + break; + } + + if (i == sign->num) + return -EINVAL; + + data += (256 - 64) / 4; + data[0] = sign->val[i].nonce[0]; + data[1] = sign->val[i].nonce[1]; + data[2] = sign->val[i].nonce[2]; + data[3] = sign->val[i].nonce[3]; + data[4] = sign->len + 64; + + memset(&data[5], 0, 44); + memcpy(&data[16], &sign[1], rdev->vce_fw->size - sizeof(*sign)); + + data += data[4] / 4; + data[0] = sign->val[i].sigval[0]; + data[1] = sign->val[i].sigval[1]; + data[2] = sign->val[i].sigval[2]; + data[3] = sign->val[i].sigval[3]; + + rdev->vce.keyselect = sign->val[i].keyselect; + + return 0; +} + +unsigned vce_v1_0_bo_size(struct radeon_device *rdev) +{ + WARN_ON(VCE_V1_0_FW_SIZE < rdev->vce_fw->size); + return VCE_V1_0_FW_SIZE + VCE_V1_0_STACK_SIZE + VCE_V1_0_DATA_SIZE; +} + +int vce_v1_0_resume(struct radeon_device *rdev) +{ + uint64_t addr = rdev->vce.gpu_addr; + uint32_t size; + int i; + + WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); + WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); + WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); + WREG32(VCE_CLOCK_GATING_B, 0); + + WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); + + WREG32(VCE_LMI_CTRL, 0x00398000); + WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); + WREG32(VCE_LMI_SWAP_CNTL, 0); + WREG32(VCE_LMI_SWAP_CNTL1, 0); + WREG32(VCE_LMI_VM_CTRL, 0); + + WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES); + + addr += 256; + size = VCE_V1_0_FW_SIZE; + WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); + WREG32(VCE_VCPU_CACHE_SIZE0, size); + + addr += size; + size = VCE_V1_0_STACK_SIZE; + WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); + WREG32(VCE_VCPU_CACHE_SIZE1, size); + + addr += size; + size = VCE_V1_0_DATA_SIZE; + WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); + WREG32(VCE_VCPU_CACHE_SIZE2, size); + + WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); + + WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect); + + for (i = 0; i < 10; ++i) { + mdelay(10); + if (RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_DONE) + break; + } + + if (i == 10) + return -ETIMEDOUT; + + if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_PASS)) + return -EINVAL; + + for (i = 0; i < 10; ++i) { + mdelay(10); + if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_BUSY)) + break; + } + + if (i == 10) + return -ETIMEDOUT; + + return 0; +} + /** * vce_v1_0_start - start VCE block * -- cgit v1.2.3 From d55a43a3e9258c01a6cac2f3081b3ceaa8e58020 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 11 May 2015 22:01:54 +0200 Subject: drm/radeon: add support for vce 1.0 clock gating Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_asic.c | 2 ++ drivers/gpu/drm/radeon/sid.h | 1 + drivers/gpu/drm/radeon/vce_v1_0.c | 57 ++++++++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index eaf909e7feb3..f2421bc3e901 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -2455,6 +2455,8 @@ int radeon_asic_init(struct radeon_device *rdev) /* set num crtcs */ rdev->num_crtc = 4; rdev->has_uvd = true; + rdev->cg_flags = + RADEON_CG_SUPPORT_VCE_MGCG; break; case CHIP_TAHITI: case CHIP_PITCAIRN: diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 4823a075f0c3..4c4a7218a3bd 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h @@ -1894,6 +1894,7 @@ #define VCE_RB_RPTR 0x2018c #define VCE_RB_WPTR 0x20190 #define VCE_CLOCK_GATING_A 0x202f8 +# define CGC_DYN_CLOCK_MODE (1 << 16) #define VCE_CLOCK_GATING_B 0x202fc #define VCE_UENC_CLOCK_GATING 0x205bc #define VCE_UENC_REG_CLOCK_GATING 0x205c0 diff --git a/drivers/gpu/drm/radeon/vce_v1_0.c b/drivers/gpu/drm/radeon/vce_v1_0.c index 81dd39b8de1c..07a0d378e122 100644 --- a/drivers/gpu/drm/radeon/vce_v1_0.c +++ b/drivers/gpu/drm/radeon/vce_v1_0.c @@ -99,6 +99,61 @@ void vce_v1_0_set_wptr(struct radeon_device *rdev, WREG32(VCE_RB_WPTR2, ring->wptr); } +void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable) +{ + u32 tmp; + + if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) { + tmp = RREG32(VCE_CLOCK_GATING_A); + tmp |= CGC_DYN_CLOCK_MODE; + WREG32(VCE_CLOCK_GATING_A, tmp); + + tmp = RREG32(VCE_UENC_CLOCK_GATING); + tmp &= ~0x1ff000; + tmp |= 0xff800000; + WREG32(VCE_UENC_CLOCK_GATING, tmp); + + tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); + tmp &= ~0x3ff; + WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); + } else { + tmp = RREG32(VCE_CLOCK_GATING_A); + tmp &= ~CGC_DYN_CLOCK_MODE; + WREG32(VCE_CLOCK_GATING_A, tmp); + + tmp = RREG32(VCE_UENC_CLOCK_GATING); + tmp |= 0x1ff000; + tmp &= ~0xff800000; + WREG32(VCE_UENC_CLOCK_GATING, tmp); + + tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); + tmp |= 0x3ff; + WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); + } +} + +static void vce_v1_0_init_cg(struct radeon_device *rdev) +{ + u32 tmp; + + tmp = RREG32(VCE_CLOCK_GATING_A); + tmp |= CGC_DYN_CLOCK_MODE; + WREG32(VCE_CLOCK_GATING_A, tmp); + + tmp = RREG32(VCE_CLOCK_GATING_B); + tmp |= 0x1e; + tmp &= ~0xe100e1; + WREG32(VCE_CLOCK_GATING_B, tmp); + + tmp = RREG32(VCE_UENC_CLOCK_GATING); + tmp &= ~0xff9ff000; + WREG32(VCE_UENC_CLOCK_GATING, tmp); + + tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); + tmp &= ~0x3ff; + WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); +} + int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data) { struct vce_v1_0_fw_signature *sign = (void*)rdev->vce_fw->data; @@ -219,6 +274,8 @@ int vce_v1_0_resume(struct radeon_device *rdev) if (i == 10) return -ETIMEDOUT; + vce_v1_0_init_cg(rdev); + return 0; } -- cgit v1.2.3 From 84bcd469592eadbf731c07ed7f6654dc71bbe059 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 11 May 2015 22:01:55 +0200 Subject: drm/radeon/tn/si: enable/disable vce cg when encoding v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some of the vce clocks are automatic, others need to be manually enabled. For ease, just disable cg when vce is active. v2: rebased, call vce_v1_0_enable_mgcg directly Signed-off-by: Alex Deucher Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/si_dpm.c | 9 ++++++++- drivers/gpu/drm/radeon/trinity_dpm.c | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index 69cd4ca91685..1dbdf3230dae 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c @@ -1740,6 +1740,7 @@ struct ni_power_info *ni_get_pi(struct radeon_device *rdev); struct ni_ps *ni_get_ps(struct radeon_ps *rps); extern int si_mc_load_microcode(struct radeon_device *rdev); +extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); static int si_populate_voltage_value(struct radeon_device *rdev, const struct atom_voltage_table *table, @@ -5932,8 +5933,14 @@ static void si_set_vce_clock(struct radeon_device *rdev, struct radeon_ps *old_rps) { if ((old_rps->evclk != new_rps->evclk) || - (old_rps->ecclk != new_rps->ecclk)) + (old_rps->ecclk != new_rps->ecclk)) { + /* turn the clocks on when encoding, off otherwise */ + if (new_rps->evclk || new_rps->ecclk) + vce_v1_0_enable_mgcg(rdev, false); + else + vce_v1_0_enable_mgcg(rdev, true); radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); + } } void si_dpm_setup_asic(struct radeon_device *rdev) diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c index e0d07802a906..d34bfcdab9be 100644 --- a/drivers/gpu/drm/radeon/trinity_dpm.c +++ b/drivers/gpu/drm/radeon/trinity_dpm.c @@ -336,6 +336,7 @@ static const u32 trinity_override_mgpg_sequences[] = 0x00000204, 0x00000000, }; +extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); static void trinity_program_clk_gating_hw_sequence(struct radeon_device *rdev, const u32 *seq, u32 count); static void trinity_override_dynamic_mg_powergating(struct radeon_device *rdev); @@ -990,8 +991,14 @@ static void trinity_set_vce_clock(struct radeon_device *rdev, struct radeon_ps *old_rps) { if ((old_rps->evclk != new_rps->evclk) || - (old_rps->ecclk != new_rps->ecclk)) + (old_rps->ecclk != new_rps->ecclk)) { + /* turn the clocks on when encoding, off otherwise */ + if (new_rps->evclk || new_rps->ecclk) + vce_v1_0_enable_mgcg(rdev, false); + else + vce_v1_0_enable_mgcg(rdev, true); radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); + } } static void trinity_program_ttt(struct radeon_device *rdev) -- cgit v1.2.3 From a10e04f4c54f02d397f429765acb09d81d344587 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Tue, 19 May 2015 18:37:52 -0700 Subject: drm/radeon: Use DECLARE_BITMAP Use the generic mechanism to declare a bitmap instead of unsigned long. Signed-off-by: Joe Perches Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index ccebf6279c05..b0b73f2edfc9 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -719,7 +719,7 @@ struct radeon_doorbell { resource_size_t size; u32 __iomem *ptr; u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ - unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; + DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); }; int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); -- cgit v1.2.3 From 0c3a88407ef2be8bb7c302c298d6ff58ebde4a43 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 14 May 2015 12:47:45 -0400 Subject: drm/radeon: make dpcd parameters const Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_dp.c | 8 ++++---- drivers/gpu/drm/radeon/radeon_mode.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 3e3290c203c6..ed173d30f1c0 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -253,7 +253,7 @@ void radeon_dp_aux_init(struct radeon_connector *radeon_connector) #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 -static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], +static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count, u8 train_set[4]) { @@ -311,7 +311,7 @@ static int dp_get_max_dp_pix_clock(int link_rate, /***** radeon specific DP functions *****/ int radeon_dp_get_max_link_rate(struct drm_connector *connector, - u8 dpcd[DP_DPCD_SIZE]) + const u8 dpcd[DP_DPCD_SIZE]) { int max_link_rate; @@ -328,7 +328,7 @@ int radeon_dp_get_max_link_rate(struct drm_connector *connector, * if the max lane# < low rate lane# then use max lane# instead. */ static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, - u8 dpcd[DP_DPCD_SIZE], + const u8 dpcd[DP_DPCD_SIZE], int pix_clock) { int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); @@ -347,7 +347,7 @@ static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, } static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, - u8 dpcd[DP_DPCD_SIZE], + const u8 dpcd[DP_DPCD_SIZE], int pix_clock) { int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index fa91a17b81b6..6de5459316b5 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -754,7 +754,7 @@ extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, struct drm_connector *connector); int radeon_dp_get_max_link_rate(struct drm_connector *connector, - u8 *dpcd); + const u8 *dpcd); extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, u8 power_state); extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); -- cgit v1.2.3 From 39fa10f7e21574a70cecf1fed0f9b36535aa68a0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 15 May 2015 11:48:52 -0400 Subject: drm/radeon: take the mode_config mutex when dealing with hpds (v2) Since we are messing with state in the worker. v2: drop the changes in the mst worker Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/radeon_irq_kms.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c index 7162c935371c..f682e5351252 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -79,10 +79,12 @@ static void radeon_hotplug_work_func(struct work_struct *work) struct drm_mode_config *mode_config = &dev->mode_config; struct drm_connector *connector; + mutex_lock(&mode_config->mutex); if (mode_config->num_connector) { list_for_each_entry(connector, &mode_config->connector_list, head) radeon_connector_hotplug(connector); } + mutex_unlock(&mode_config->mutex); /* Just fire off a uevent and let userspace tell us what to do */ drm_helper_hpd_irq_event(dev); } -- cgit v1.2.3 From 8d3afd7d0e666b932e6fa15901e6280fe829a786 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 21 May 2015 21:01:47 +0100 Subject: drm/i915: Use spinlocks for checking when to waitboost In commit 1854d5ca0dd7a9fc11243ff220a3e93fce2b4d3e Author: Chris Wilson Date: Tue Apr 7 16:20:32 2015 +0100 drm/i915: Deminish contribution of wait-boosting from clients we removed an atomic timer based check for allowing waitboosting and moved it below the mutex taken during RPS. However, that mutex can be held for long periods of time on Vallyview/Cherryview as communication with the PCU is slow. As clients may frequently wait for results (e.g. such as tranform feedback) we introduced contention between the client and the RPS worker. We can take advantage of the RPS worker, by switching the wait boost decision to use spin locks and defer the actual reclocking to the worker. Fixes a regression of up to 45% on Baytrail and Baswell! v2 (Daniel): - Use max_freq_softlimit instead of the not-yet-merged boost frequency. - Don't inject a fake irq into the boost work, instead treat client_boost as just another legit waker. v3: Drop the now unused mask (Chris). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90112 Signed-off-by: Chris Wilson (v1) Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_debugfs.c | 17 +++-------------- drivers/gpu/drm/i915/i915_drv.h | 9 +++++++-- drivers/gpu/drm/i915/i915_gem.c | 4 ++-- drivers/gpu/drm/i915/i915_irq.c | 19 +++++++++++++------ drivers/gpu/drm/i915/intel_pm.c | 31 ++++++++++++++++++++----------- 5 files changed, 45 insertions(+), 35 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index fece922718e2..88cc793c46d3 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2300,15 +2300,6 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) struct drm_device *dev = node->minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_file *file; - int ret; - - ret = mutex_lock_interruptible(&dev->struct_mutex); - if (ret) - return ret; - - ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); - if (ret) - goto unlock; seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); @@ -2319,6 +2310,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); + spin_lock(&dev_priv->rps.client_lock); list_for_each_entry_reverse(file, &dev->filelist, lhead) { struct drm_i915_file_private *file_priv = file->driver_priv; struct task_struct *task; @@ -2339,12 +2331,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) dev_priv->rps.mmioflips.boosts, list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); + spin_unlock(&dev_priv->rps.client_lock); - mutex_unlock(&dev_priv->rps.hw_lock); -unlock: - mutex_unlock(&dev->struct_mutex); - - return ret; + return 0; } static int i915_llc(struct seq_file *m, void *data) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9adfd124ad2d..3f6cad96ee91 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1089,9 +1089,12 @@ struct intel_gen6_power_mgmt { int last_adj; enum { LOW_POWER, BETWEEN, HIGH_POWER } power; + spinlock_t client_lock; + struct list_head clients; + bool client_boost; + bool enabled; struct delayed_work delayed_resume_work; - struct list_head clients; unsigned boosts; struct intel_rps_client semaphores, mmioflips; @@ -1101,7 +1104,9 @@ struct intel_gen6_power_mgmt { /* * Protects RPS/RC6 register access and PCU communication. - * Must be taken after struct_mutex if nested. + * Must be taken after struct_mutex if nested. Note that + * this lock may be held for long periods of time when + * talking to hw - so only take it when talking to hw! */ struct mutex hw_lock; }; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index cc206f199d66..be35f0486202 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5223,9 +5223,9 @@ void i915_gem_release(struct drm_device *dev, struct drm_file *file) spin_unlock(&file_priv->mm.lock); if (!list_empty(&file_priv->rps.link)) { - mutex_lock(&to_i915(dev)->rps.hw_lock); + spin_lock(&to_i915(dev)->rps.client_lock); list_del(&file_priv->rps.link); - mutex_unlock(&to_i915(dev)->rps.hw_lock); + spin_unlock(&to_i915(dev)->rps.client_lock); } } diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 707e2ca8fbd8..e6bb72dca3ff 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1086,8 +1086,9 @@ static void gen6_pm_rps_work(struct work_struct *work) { struct drm_i915_private *dev_priv = container_of(work, struct drm_i915_private, rps.work); + bool client_boost; + int new_delay, adj, min, max; u32 pm_iir; - int new_delay, adj; spin_lock_irq(&dev_priv->irq_lock); /* Speed up work cancelation during disabling rps interrupts. */ @@ -1099,12 +1100,14 @@ static void gen6_pm_rps_work(struct work_struct *work) dev_priv->rps.pm_iir = 0; /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); + client_boost = dev_priv->rps.client_boost; + dev_priv->rps.client_boost = false; spin_unlock_irq(&dev_priv->irq_lock); /* Make sure we didn't queue anything we're not going to process. */ WARN_ON(pm_iir & ~dev_priv->pm_rps_events); - if ((pm_iir & dev_priv->pm_rps_events) == 0) + if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) return; mutex_lock(&dev_priv->rps.hw_lock); @@ -1113,7 +1116,13 @@ static void gen6_pm_rps_work(struct work_struct *work) adj = dev_priv->rps.last_adj; new_delay = dev_priv->rps.cur_freq; - if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { + min = dev_priv->rps.min_freq_softlimit; + max = dev_priv->rps.max_freq_softlimit; + + if (client_boost) { + new_delay = dev_priv->rps.max_freq_softlimit; + adj = 0; + } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { if (adj > 0) adj *= 2; else /* CHV needs even encode values */ @@ -1149,9 +1158,7 @@ static void gen6_pm_rps_work(struct work_struct *work) * interrupt */ new_delay += adj; - new_delay = clamp_t(int, new_delay, - dev_priv->rps.min_freq_softlimit, - dev_priv->rps.max_freq_softlimit); + new_delay = clamp_t(int, new_delay, min, max); intel_set_rps(dev_priv->dev, new_delay); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 55d993110d51..79843215d90c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4143,17 +4143,25 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv) dev_priv->rps.last_adj = 0; I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); } + mutex_unlock(&dev_priv->rps.hw_lock); + spin_lock(&dev_priv->rps.client_lock); while (!list_empty(&dev_priv->rps.clients)) list_del_init(dev_priv->rps.clients.next); - mutex_unlock(&dev_priv->rps.hw_lock); + spin_unlock(&dev_priv->rps.client_lock); } void gen6_rps_boost(struct drm_i915_private *dev_priv, struct intel_rps_client *rps, unsigned long submitted) { - u32 val; + /* This is intentionally racy! We peek at the state here, then + * validate inside the RPS worker. + */ + if (!(dev_priv->mm.busy && + dev_priv->rps.enabled && + dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) + return; /* Force a RPS boost (and don't count it against the client) if * the GPU is severely congested. @@ -4161,14 +4169,14 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv, if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) rps = NULL; - mutex_lock(&dev_priv->rps.hw_lock); - val = dev_priv->rps.max_freq_softlimit; - if (dev_priv->rps.enabled && - dev_priv->mm.busy && - dev_priv->rps.cur_freq < val && - (rps == NULL || list_empty(&rps->link))) { - intel_set_rps(dev_priv->dev, val); - dev_priv->rps.last_adj = 0; + spin_lock(&dev_priv->rps.client_lock); + if (rps == NULL || list_empty(&rps->link)) { + spin_lock_irq(&dev_priv->irq_lock); + if (dev_priv->rps.interrupts_enabled) { + dev_priv->rps.client_boost = true; + queue_work(dev_priv->wq, &dev_priv->rps.work); + } + spin_unlock_irq(&dev_priv->irq_lock); if (rps != NULL) { list_add(&rps->link, &dev_priv->rps.clients); @@ -4176,7 +4184,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv, } else dev_priv->rps.boosts++; } - mutex_unlock(&dev_priv->rps.hw_lock); + spin_unlock(&dev_priv->rps.client_lock); } void intel_set_rps(struct drm_device *dev, u8 val) @@ -6913,6 +6921,7 @@ void intel_pm_setup(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; mutex_init(&dev_priv->rps.hw_lock); + spin_lock_init(&dev_priv->rps.client_lock); INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, intel_gen6_powersave_work); -- cgit v1.2.3 From de9cb5f20a50f2811caf909ee254699fd2228910 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Thu, 26 Feb 2015 10:12:41 +0200 Subject: drm/tilcdc: Fix module unloading Force crtc dpms off before destroying the crtc instead of just checking the dpms state. This fixes warning message and frozen picture after tilcdc module unloading. Signed-off-by: Jyri Sarha Acked-by: Tomi Valkeinen --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index c73588483be0..c2d5980b9965 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -135,11 +135,12 @@ static void stop(struct drm_crtc *crtc) tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); } +static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode); static void tilcdc_crtc_destroy(struct drm_crtc *crtc) { struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); - WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON); + tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); drm_crtc_cleanup(crtc); drm_flip_work_cleanup(&tilcdc_crtc->unref_work); -- cgit v1.2.3 From 6730201f4fdcfbb1e6ec5ec374e6ef95e5bf9662 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Tue, 24 Feb 2015 15:24:31 +0200 Subject: drm/tilcdc: Remove tilcdc slave support for tda998x driver Remove tilcdc slave support for tda998x driver. The tilcdc slave support would conflicts with componentized use of tda998x. Signed-off-by: Jyri Sarha Acked-by: Tomi Valkeinen --- .../devicetree/bindings/drm/tilcdc/slave.txt | 18 - drivers/gpu/drm/tilcdc/Makefile | 1 - drivers/gpu/drm/tilcdc/tilcdc_drv.c | 13 - drivers/gpu/drm/tilcdc/tilcdc_drv.h | 1 - drivers/gpu/drm/tilcdc/tilcdc_slave.c | 411 --------------------- drivers/gpu/drm/tilcdc/tilcdc_slave.h | 26 -- 6 files changed, 470 deletions(-) delete mode 100644 Documentation/devicetree/bindings/drm/tilcdc/slave.txt delete mode 100644 drivers/gpu/drm/tilcdc/tilcdc_slave.c delete mode 100644 drivers/gpu/drm/tilcdc/tilcdc_slave.h (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/drm/tilcdc/slave.txt b/Documentation/devicetree/bindings/drm/tilcdc/slave.txt deleted file mode 100644 index 3d2c52460dca..000000000000 --- a/Documentation/devicetree/bindings/drm/tilcdc/slave.txt +++ /dev/null @@ -1,18 +0,0 @@ -Device-Tree bindings for tilcdc DRM encoder slave output driver - -Required properties: - - compatible: value should be "ti,tilcdc,slave". - - i2c: the phandle for the i2c device the encoder slave is connected to - -Recommended properties: - - pinctrl-names, pinctrl-0: the pincontrol settings to configure - muxing properly for pins that connect to TFP410 device - -Example: - - hdmi { - compatible = "ti,tilcdc,slave"; - i2c = <&i2c0>; - pinctrl-names = "default"; - pinctrl-0 = <&nxp_hdmi_bonelt_pins>; - }; diff --git a/drivers/gpu/drm/tilcdc/Makefile b/drivers/gpu/drm/tilcdc/Makefile index 7d2eefe94bf7..44485f9d3c88 100644 --- a/drivers/gpu/drm/tilcdc/Makefile +++ b/drivers/gpu/drm/tilcdc/Makefile @@ -6,7 +6,6 @@ endif tilcdc-y := \ tilcdc_crtc.o \ tilcdc_tfp410.o \ - tilcdc_slave.o \ tilcdc_panel.o \ tilcdc_drv.o diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index 095fca91525c..0f1e09986f56 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -20,13 +20,11 @@ #include "tilcdc_drv.h" #include "tilcdc_regs.h" #include "tilcdc_tfp410.h" -#include "tilcdc_slave.h" #include "tilcdc_panel.h" #include "drm_fb_helper.h" static LIST_HEAD(module_list); -static bool slave_probing; void tilcdc_module_init(struct tilcdc_module *mod, const char *name, const struct tilcdc_module_ops *funcs) @@ -42,11 +40,6 @@ void tilcdc_module_cleanup(struct tilcdc_module *mod) list_del(&mod->list); } -void tilcdc_slave_probedefer(bool defered) -{ - slave_probing = defered; -} - static struct of_device_id tilcdc_of_match[]; static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev, @@ -620,10 +613,6 @@ static int tilcdc_pdev_probe(struct platform_device *pdev) return -ENXIO; } - /* defer probing if slave is in deferred probing */ - if (slave_probing == true) - return -EPROBE_DEFER; - return drm_platform_init(&tilcdc_driver, pdev); } @@ -654,7 +643,6 @@ static int __init tilcdc_drm_init(void) { DBG("init"); tilcdc_tfp410_init(); - tilcdc_slave_init(); tilcdc_panel_init(); return platform_driver_register(&tilcdc_platform_driver); } @@ -664,7 +652,6 @@ static void __exit tilcdc_drm_fini(void) DBG("fini"); platform_driver_unregister(&tilcdc_platform_driver); tilcdc_panel_fini(); - tilcdc_slave_fini(); tilcdc_tfp410_fini(); } diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h b/drivers/gpu/drm/tilcdc/tilcdc_drv.h index 7596c144a9fb..633651238dbb 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h @@ -116,7 +116,6 @@ struct tilcdc_module { void tilcdc_module_init(struct tilcdc_module *mod, const char *name, const struct tilcdc_module_ops *funcs); void tilcdc_module_cleanup(struct tilcdc_module *mod); -void tilcdc_slave_probedefer(bool defered); /* Panel config that needs to be set in the crtc, but is not coming from * the mode timings. The display module is expected to call diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave.c b/drivers/gpu/drm/tilcdc/tilcdc_slave.c deleted file mode 100644 index 3775fd49dac4..000000000000 --- a/drivers/gpu/drm/tilcdc/tilcdc_slave.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments - * Author: Rob Clark - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include -#include -#include -#include - -#include "tilcdc_drv.h" - -struct slave_module { - struct tilcdc_module base; - struct i2c_adapter *i2c; -}; -#define to_slave_module(x) container_of(x, struct slave_module, base) - -static const struct tilcdc_panel_info slave_info = { - .bpp = 16, - .ac_bias = 255, - .ac_bias_intrpt = 0, - .dma_burst_sz = 16, - .fdd = 0x80, - .tft_alt_mode = 0, - .sync_edge = 0, - .sync_ctrl = 1, - .raster_order = 0, -}; - - -/* - * Encoder: - */ - -struct slave_encoder { - struct drm_encoder_slave base; - struct slave_module *mod; -}; -#define to_slave_encoder(x) container_of(to_encoder_slave(x), struct slave_encoder, base) - -static inline struct drm_encoder_slave_funcs * -get_slave_funcs(struct drm_encoder *enc) -{ - return to_encoder_slave(enc)->slave_funcs; -} - -static void slave_encoder_destroy(struct drm_encoder *encoder) -{ - struct slave_encoder *slave_encoder = to_slave_encoder(encoder); - if (get_slave_funcs(encoder)) - get_slave_funcs(encoder)->destroy(encoder); - drm_encoder_cleanup(encoder); - kfree(slave_encoder); -} - -static void slave_encoder_prepare(struct drm_encoder *encoder) -{ - drm_i2c_encoder_prepare(encoder); - tilcdc_crtc_set_panel_info(encoder->crtc, &slave_info); -} - -static bool slave_encoder_fixup(struct drm_encoder *encoder, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - /* - * tilcdc does not generate VESA-complient sync but aligns - * VS on the second edge of HS instead of first edge. - * We use adjusted_mode, to fixup sync by aligning both rising - * edges and add HSKEW offset to let the slave encoder fix it up. - */ - adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; - adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; - - if (mode->flags & DRM_MODE_FLAG_NHSYNC) { - adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; - adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; - } else { - adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; - adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; - } - - return drm_i2c_encoder_mode_fixup(encoder, mode, adjusted_mode); -} - - -static const struct drm_encoder_funcs slave_encoder_funcs = { - .destroy = slave_encoder_destroy, -}; - -static const struct drm_encoder_helper_funcs slave_encoder_helper_funcs = { - .dpms = drm_i2c_encoder_dpms, - .mode_fixup = slave_encoder_fixup, - .prepare = slave_encoder_prepare, - .commit = drm_i2c_encoder_commit, - .mode_set = drm_i2c_encoder_mode_set, - .save = drm_i2c_encoder_save, - .restore = drm_i2c_encoder_restore, -}; - -static const struct i2c_board_info info = { - I2C_BOARD_INFO("tda998x", 0x70) -}; - -static struct drm_encoder *slave_encoder_create(struct drm_device *dev, - struct slave_module *mod) -{ - struct slave_encoder *slave_encoder; - struct drm_encoder *encoder; - int ret; - - slave_encoder = kzalloc(sizeof(*slave_encoder), GFP_KERNEL); - if (!slave_encoder) { - dev_err(dev->dev, "allocation failed\n"); - return NULL; - } - - slave_encoder->mod = mod; - - encoder = &slave_encoder->base.base; - encoder->possible_crtcs = 1; - - ret = drm_encoder_init(dev, encoder, &slave_encoder_funcs, - DRM_MODE_ENCODER_TMDS); - if (ret) - goto fail; - - drm_encoder_helper_add(encoder, &slave_encoder_helper_funcs); - - ret = drm_i2c_encoder_init(dev, to_encoder_slave(encoder), mod->i2c, &info); - if (ret) - goto fail; - - return encoder; - -fail: - slave_encoder_destroy(encoder); - return NULL; -} - -/* - * Connector: - */ - -struct slave_connector { - struct drm_connector base; - - struct drm_encoder *encoder; /* our connected encoder */ - struct slave_module *mod; -}; -#define to_slave_connector(x) container_of(x, struct slave_connector, base) - -static void slave_connector_destroy(struct drm_connector *connector) -{ - struct slave_connector *slave_connector = to_slave_connector(connector); - drm_connector_unregister(connector); - drm_connector_cleanup(connector); - kfree(slave_connector); -} - -static enum drm_connector_status slave_connector_detect( - struct drm_connector *connector, - bool force) -{ - struct drm_encoder *encoder = to_slave_connector(connector)->encoder; - return get_slave_funcs(encoder)->detect(encoder, connector); -} - -static int slave_connector_get_modes(struct drm_connector *connector) -{ - struct drm_encoder *encoder = to_slave_connector(connector)->encoder; - return get_slave_funcs(encoder)->get_modes(encoder, connector); -} - -static int slave_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - struct drm_encoder *encoder = to_slave_connector(connector)->encoder; - struct tilcdc_drm_private *priv = connector->dev->dev_private; - int ret; - - ret = tilcdc_crtc_mode_valid(priv->crtc, mode); - if (ret != MODE_OK) - return ret; - - return get_slave_funcs(encoder)->mode_valid(encoder, mode); -} - -static struct drm_encoder *slave_connector_best_encoder( - struct drm_connector *connector) -{ - struct slave_connector *slave_connector = to_slave_connector(connector); - return slave_connector->encoder; -} - -static int slave_connector_set_property(struct drm_connector *connector, - struct drm_property *property, uint64_t value) -{ - struct drm_encoder *encoder = to_slave_connector(connector)->encoder; - return get_slave_funcs(encoder)->set_property(encoder, - connector, property, value); -} - -static const struct drm_connector_funcs slave_connector_funcs = { - .destroy = slave_connector_destroy, - .dpms = drm_helper_connector_dpms, - .detect = slave_connector_detect, - .fill_modes = drm_helper_probe_single_connector_modes, - .set_property = slave_connector_set_property, -}; - -static const struct drm_connector_helper_funcs slave_connector_helper_funcs = { - .get_modes = slave_connector_get_modes, - .mode_valid = slave_connector_mode_valid, - .best_encoder = slave_connector_best_encoder, -}; - -static struct drm_connector *slave_connector_create(struct drm_device *dev, - struct slave_module *mod, struct drm_encoder *encoder) -{ - struct slave_connector *slave_connector; - struct drm_connector *connector; - int ret; - - slave_connector = kzalloc(sizeof(*slave_connector), GFP_KERNEL); - if (!slave_connector) { - dev_err(dev->dev, "allocation failed\n"); - return NULL; - } - - slave_connector->encoder = encoder; - slave_connector->mod = mod; - - connector = &slave_connector->base; - - drm_connector_init(dev, connector, &slave_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA); - drm_connector_helper_add(connector, &slave_connector_helper_funcs); - - connector->polled = DRM_CONNECTOR_POLL_CONNECT | - DRM_CONNECTOR_POLL_DISCONNECT; - - connector->interlace_allowed = 0; - connector->doublescan_allowed = 0; - - get_slave_funcs(encoder)->create_resources(encoder, connector); - - ret = drm_mode_connector_attach_encoder(connector, encoder); - if (ret) - goto fail; - - drm_connector_register(connector); - - return connector; - -fail: - slave_connector_destroy(connector); - return NULL; -} - -/* - * Module: - */ - -static int slave_modeset_init(struct tilcdc_module *mod, struct drm_device *dev) -{ - struct slave_module *slave_mod = to_slave_module(mod); - struct tilcdc_drm_private *priv = dev->dev_private; - struct drm_encoder *encoder; - struct drm_connector *connector; - - encoder = slave_encoder_create(dev, slave_mod); - if (!encoder) - return -ENOMEM; - - connector = slave_connector_create(dev, slave_mod, encoder); - if (!connector) - return -ENOMEM; - - priv->encoders[priv->num_encoders++] = encoder; - priv->connectors[priv->num_connectors++] = connector; - - return 0; -} - -static const struct tilcdc_module_ops slave_module_ops = { - .modeset_init = slave_modeset_init, -}; - -/* - * Device: - */ - -static struct of_device_id slave_of_match[]; - -static int slave_probe(struct platform_device *pdev) -{ - struct device_node *node = pdev->dev.of_node; - struct device_node *i2c_node; - struct slave_module *slave_mod; - struct tilcdc_module *mod; - struct pinctrl *pinctrl; - uint32_t i2c_phandle; - struct i2c_adapter *slavei2c; - int ret = -EINVAL; - - /* bail out early if no DT data: */ - if (!node) { - dev_err(&pdev->dev, "device-tree data is missing\n"); - return -ENXIO; - } - - /* Bail out early if i2c not specified */ - if (of_property_read_u32(node, "i2c", &i2c_phandle)) { - dev_err(&pdev->dev, "could not get i2c bus phandle\n"); - return ret; - } - - i2c_node = of_find_node_by_phandle(i2c_phandle); - if (!i2c_node) { - dev_err(&pdev->dev, "could not get i2c bus node\n"); - return ret; - } - - /* but defer the probe if it can't be initialized it might come later */ - slavei2c = of_find_i2c_adapter_by_node(i2c_node); - of_node_put(i2c_node); - - if (!slavei2c) { - ret = -EPROBE_DEFER; - tilcdc_slave_probedefer(true); - dev_err(&pdev->dev, "could not get i2c\n"); - return ret; - } - - slave_mod = kzalloc(sizeof(*slave_mod), GFP_KERNEL); - if (!slave_mod) { - ret = -ENOMEM; - goto fail_adapter; - } - - mod = &slave_mod->base; - pdev->dev.platform_data = mod; - - mod->preferred_bpp = slave_info.bpp; - - slave_mod->i2c = slavei2c; - - tilcdc_module_init(mod, "slave", &slave_module_ops); - - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); - if (IS_ERR(pinctrl)) - dev_warn(&pdev->dev, "pins are not configured\n"); - - tilcdc_slave_probedefer(false); - - return 0; - -fail_adapter: - i2c_put_adapter(slavei2c); - return ret; -} - -static int slave_remove(struct platform_device *pdev) -{ - struct tilcdc_module *mod = dev_get_platdata(&pdev->dev); - struct slave_module *slave_mod = to_slave_module(mod); - - tilcdc_module_cleanup(mod); - kfree(slave_mod); - - return 0; -} - -static struct of_device_id slave_of_match[] = { - { .compatible = "ti,tilcdc,slave", }, - { }, -}; - -struct platform_driver slave_driver = { - .probe = slave_probe, - .remove = slave_remove, - .driver = { - .owner = THIS_MODULE, - .name = "slave", - .of_match_table = slave_of_match, - }, -}; - -int __init tilcdc_slave_init(void) -{ - return platform_driver_register(&slave_driver); -} - -void __exit tilcdc_slave_fini(void) -{ - platform_driver_unregister(&slave_driver); -} diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave.h b/drivers/gpu/drm/tilcdc/tilcdc_slave.h deleted file mode 100644 index 2f8504848320..000000000000 --- a/drivers/gpu/drm/tilcdc/tilcdc_slave.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2012 Texas Instruments - * Author: Rob Clark - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#ifndef __TILCDC_SLAVE_H__ -#define __TILCDC_SLAVE_H__ - -/* sub-module for i2c slave encoder output */ - -int tilcdc_slave_init(void); -void tilcdc_slave_fini(void); - -#endif /* __TILCDC_SLAVE_H__ */ -- cgit v1.2.3 From 103cd8bc1c80ec0a12ef438c4493f7c26edc71bd Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Tue, 10 Feb 2015 14:13:23 +0200 Subject: drm/tilcdc: Add support for external tda998x encoder Add support for an external compontised DRM encoder. The external encoder can be connected to tilcdc trough device tree graph binding. The binding document for tilcdc has been updated. The current implementation supports only tda998x encoder. To be able to filter out the unsupported video modes the tilcdc driver needs to hijack the external connectors helper functions. The tilcdc installes new helper functions that are otherwise identical to orignals, but the mode_valid() call-back check the mode first localy, before calling the original call-back. The tilcdc dirver restores the original helper functions before it is unbound from the external device. I got the idea and some lines of code from Jean-Francois Moine's "drm/tilcdc: Change the interface with the tda998x driver"-patch. Signed-off-by: Jyri Sarha Acked-by: Tomi Valkeinen --- .../devicetree/bindings/drm/tilcdc/tilcdc.txt | 27 ++++ drivers/gpu/drm/tilcdc/Makefile | 1 + drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 33 ++++ drivers/gpu/drm/tilcdc/tilcdc_drv.c | 85 +++++++++-- drivers/gpu/drm/tilcdc/tilcdc_drv.h | 5 + drivers/gpu/drm/tilcdc/tilcdc_external.c | 166 +++++++++++++++++++++ drivers/gpu/drm/tilcdc/tilcdc_external.h | 25 ++++ 7 files changed, 329 insertions(+), 13 deletions(-) create mode 100644 drivers/gpu/drm/tilcdc/tilcdc_external.c create mode 100644 drivers/gpu/drm/tilcdc/tilcdc_external.h (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/drm/tilcdc/tilcdc.txt b/Documentation/devicetree/bindings/drm/tilcdc/tilcdc.txt index fff10da5e927..2136ee81e061 100644 --- a/Documentation/devicetree/bindings/drm/tilcdc/tilcdc.txt +++ b/Documentation/devicetree/bindings/drm/tilcdc/tilcdc.txt @@ -18,6 +18,12 @@ Optional properties: - max-pixelclock: The maximum pixel clock that can be supported by the lcd controller in KHz. +Optional nodes: + + - port/ports: to describe a connection to an external encoder. The + binding follows Documentation/devicetree/bindings/graph.txt and + suppors a single port with a single endpoint. + Example: fb: fb@4830e000 { @@ -26,4 +32,25 @@ Example: interrupt-parent = <&intc>; interrupts = <36>; ti,hwmods = "lcdc"; + + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; + }; + + tda19988: tda19988 { + compatible = "nxp,tda998x"; + reg = <0x70>; + + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + port { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; + }; }; diff --git a/drivers/gpu/drm/tilcdc/Makefile b/drivers/gpu/drm/tilcdc/Makefile index 44485f9d3c88..e1f738b02c1f 100644 --- a/drivers/gpu/drm/tilcdc/Makefile +++ b/drivers/gpu/drm/tilcdc/Makefile @@ -7,6 +7,7 @@ tilcdc-y := \ tilcdc_crtc.o \ tilcdc_tfp410.o \ tilcdc_panel.o \ + tilcdc_external.o \ tilcdc_drv.o obj-$(CONFIG_DRM_TILCDC) += tilcdc.o diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index c2d5980b9965..7d07733bdc86 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -37,6 +37,9 @@ struct tilcdc_crtc { /* for deferred fb unref's: */ struct drm_flip_work unref_work; + + /* Only set if an external encoder is connected */ + bool simulate_vesa_sync; }; #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) @@ -214,6 +217,28 @@ static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { + struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); + + if (!tilcdc_crtc->simulate_vesa_sync) + return true; + + /* + * tilcdc does not generate VESA-compliant sync but aligns + * VS on the second edge of HS instead of first edge. + * We use adjusted_mode, to fixup sync by aligning both rising + * edges and add HSKEW offset to fix the sync. + */ + adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; + adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; + + if (mode->flags & DRM_MODE_FLAG_NHSYNC) { + adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; + adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; + } else { + adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; + adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; + } + return true; } @@ -534,6 +559,14 @@ void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, tilcdc_crtc->info = info; } +void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, + bool simulate_vesa_sync) +{ + struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); + + tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync; +} + void tilcdc_crtc_update_clk(struct drm_crtc *crtc) { struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index 0f1e09986f56..fcc0508c58c0 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -17,10 +17,13 @@ /* LCDC DRM driver, based on da8xx-fb */ +#include + #include "tilcdc_drv.h" #include "tilcdc_regs.h" #include "tilcdc_tfp410.h" #include "tilcdc_panel.h" +#include "tilcdc_external.h" #include "drm_fb_helper.h" @@ -73,13 +76,6 @@ static int modeset_init(struct drm_device *dev) mod->funcs->modeset_init(mod, dev); } - if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) { - /* oh nos! */ - dev_err(dev->dev, "no encoders/connectors found\n"); - drm_mode_config_cleanup(dev); - return -ENXIO; - } - dev->mode_config.min_width = 0; dev->mode_config.min_height = 0; dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc); @@ -114,6 +110,8 @@ static int tilcdc_unload(struct drm_device *dev) { struct tilcdc_drm_private *priv = dev->dev_private; + tilcdc_remove_external_encoders(dev); + drm_fbdev_cma_fini(priv->fbdev); drm_kms_helper_poll_fini(dev); drm_mode_config_cleanup(dev); @@ -164,6 +162,9 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags) dev->dev_private = priv; + priv->is_componentized = + tilcdc_get_external_components(dev->dev, NULL) > 0; + priv->wq = alloc_ordered_workqueue("tilcdc", 0); if (!priv->wq) { ret = -ENOMEM; @@ -253,10 +254,28 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags) goto fail_cpufreq_unregister; } + platform_set_drvdata(pdev, dev); + + if (priv->is_componentized) { + ret = component_bind_all(dev->dev, dev); + if (ret < 0) + goto fail_mode_config_cleanup; + + ret = tilcdc_add_external_encoders(dev, &bpp); + if (ret < 0) + goto fail_component_cleanup; + } + + if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) { + dev_err(dev->dev, "no encoders/connectors found\n"); + ret = -ENXIO; + goto fail_external_cleanup; + } + ret = drm_vblank_init(dev, 1); if (ret < 0) { dev_err(dev->dev, "failed to initialize vblank\n"); - goto fail_mode_config_cleanup; + goto fail_external_cleanup; } pm_runtime_get_sync(dev->dev); @@ -267,9 +286,6 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags) goto fail_vblank_cleanup; } - platform_set_drvdata(pdev, dev); - - list_for_each_entry(mod, &module_list, list) { DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp); bpp = mod->preferred_bpp; @@ -300,6 +316,13 @@ fail_vblank_cleanup: fail_mode_config_cleanup: drm_mode_config_cleanup(dev); +fail_component_cleanup: + if (priv->is_componentized) + component_unbind_all(dev->dev, dev); + +fail_external_cleanup: + tilcdc_remove_external_encoders(dev); + fail_cpufreq_unregister: pm_runtime_disable(dev->dev); #ifdef CONFIG_CPU_FREQ @@ -605,20 +628,56 @@ static const struct dev_pm_ops tilcdc_pm_ops = { * Platform driver: */ +static int tilcdc_bind(struct device *dev) +{ + return drm_platform_init(&tilcdc_driver, to_platform_device(dev)); +} + +static void tilcdc_unbind(struct device *dev) +{ + drm_put_dev(dev_get_drvdata(dev)); +} + +static const struct component_master_ops tilcdc_comp_ops = { + .bind = tilcdc_bind, + .unbind = tilcdc_unbind, +}; + static int tilcdc_pdev_probe(struct platform_device *pdev) { + struct component_match *match = NULL; + int ret; + /* bail out early if no DT data: */ if (!pdev->dev.of_node) { dev_err(&pdev->dev, "device-tree data is missing\n"); return -ENXIO; } - return drm_platform_init(&tilcdc_driver, pdev); + ret = tilcdc_get_external_components(&pdev->dev, &match); + if (ret < 0) + return ret; + else if (ret == 0) + return drm_platform_init(&tilcdc_driver, pdev); + else + return component_master_add_with_match(&pdev->dev, + &tilcdc_comp_ops, + match); } static int tilcdc_pdev_remove(struct platform_device *pdev) { - drm_put_dev(platform_get_drvdata(pdev)); + struct drm_device *ddev = dev_get_drvdata(&pdev->dev); + struct tilcdc_drm_private *priv = ddev->dev_private; + + /* Check if a subcomponent has already triggered the unloading. */ + if (!priv) + return 0; + + if (priv->is_componentized) + component_master_del(&pdev->dev, &tilcdc_comp_ops); + else + drm_put_dev(platform_get_drvdata(pdev)); return 0; } diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h b/drivers/gpu/drm/tilcdc/tilcdc_drv.h index 633651238dbb..e863ad0d26fe 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h @@ -85,6 +85,9 @@ struct tilcdc_drm_private { unsigned int num_connectors; struct drm_connector *connectors[8]; + const struct drm_connector_helper_funcs *connector_funcs[8]; + + bool is_componentized; }; /* Sub-module for display. Since we don't know at compile time what panels @@ -165,6 +168,8 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc); void tilcdc_crtc_update_clk(struct drm_crtc *crtc); void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, const struct tilcdc_panel_info *info); +void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, + bool simulate_vesa_sync); int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode); int tilcdc_crtc_max_width(struct drm_crtc *crtc); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_external.c b/drivers/gpu/drm/tilcdc/tilcdc_external.c new file mode 100644 index 000000000000..03acb4f99982 --- /dev/null +++ b/drivers/gpu/drm/tilcdc/tilcdc_external.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2015 Texas Instruments + * Author: Jyri Sarha + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + */ + +#include +#include + +#include "tilcdc_drv.h" +#include "tilcdc_external.h" + +static const struct tilcdc_panel_info panel_info_tda998x = { + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .invert_pxl_clk = 1, + .sync_edge = 1, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static int tilcdc_external_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct tilcdc_drm_private *priv = connector->dev->dev_private; + int ret, i; + + ret = tilcdc_crtc_mode_valid(priv->crtc, mode); + if (ret != MODE_OK) + return ret; + + for (i = 0; i < priv->num_connectors && + priv->connectors[i] != connector; i++) + ; + + BUG_ON(priv->connectors[i] != connector); + BUG_ON(!priv->connector_funcs[i]); + + /* If the connector has its own mode_valid call it. */ + if (!IS_ERR(priv->connector_funcs[i]) && + priv->connector_funcs[i]->mode_valid) + return priv->connector_funcs[i]->mode_valid(connector, mode); + + return MODE_OK; +} + +static int tilcdc_add_external_encoder(struct drm_device *dev, int *bpp, + struct drm_connector *connector) +{ + struct tilcdc_drm_private *priv = dev->dev_private; + struct drm_connector_helper_funcs *connector_funcs; + + priv->connectors[priv->num_connectors] = connector; + priv->encoders[priv->num_encoders++] = connector->encoder; + + /* Only tda998x is supported at the moment. */ + tilcdc_crtc_set_simulate_vesa_sync(priv->crtc, true); + tilcdc_crtc_set_panel_info(priv->crtc, &panel_info_tda998x); + *bpp = panel_info_tda998x.bpp; + + connector_funcs = devm_kzalloc(dev->dev, sizeof(*connector_funcs), + GFP_KERNEL); + if (!connector_funcs) + return -ENOMEM; + + /* connector->helper_private contains always struct + * connector_helper_funcs pointer. For tilcdc crtc to have a + * say if a specific mode is Ok, we need to install our own + * helper functions. In our helper functions we copy + * everything else but use our own mode_valid() (above). + */ + if (connector->helper_private) { + priv->connector_funcs[priv->num_connectors] = + connector->helper_private; + *connector_funcs = *priv->connector_funcs[priv->num_connectors]; + } else { + priv->connector_funcs[priv->num_connectors] = ERR_PTR(-ENOENT); + } + connector_funcs->mode_valid = tilcdc_external_mode_valid; + drm_connector_helper_add(connector, connector_funcs); + priv->num_connectors++; + + dev_dbg(dev->dev, "External encoder '%s' connected\n", + connector->encoder->name); + + return 0; +} + +int tilcdc_add_external_encoders(struct drm_device *dev, int *bpp) +{ + struct tilcdc_drm_private *priv = dev->dev_private; + struct drm_connector *connector; + int num_internal_connectors = priv->num_connectors; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + bool found = false; + int i, ret; + + for (i = 0; i < num_internal_connectors; i++) + if (connector == priv->connectors[i]) + found = true; + if (!found) { + ret = tilcdc_add_external_encoder(dev, bpp, connector); + if (ret) + return ret; + } + } + return 0; +} + +void tilcdc_remove_external_encoders(struct drm_device *dev) +{ + struct tilcdc_drm_private *priv = dev->dev_private; + int i; + + /* Restore the original helper functions, if any. */ + for (i = 0; i < priv->num_connectors; i++) + if (IS_ERR(priv->connector_funcs[i])) + drm_connector_helper_add(priv->connectors[i], NULL); + else if (priv->connector_funcs[i]) + drm_connector_helper_add(priv->connectors[i], + priv->connector_funcs[i]); +} + +static int dev_match_of(struct device *dev, void *data) +{ + return dev->of_node == data; +} + +int tilcdc_get_external_components(struct device *dev, + struct component_match **match) +{ + struct device_node *ep = NULL; + int count = 0; + + while ((ep = of_graph_get_next_endpoint(dev->of_node, ep))) { + struct device_node *node; + + node = of_graph_get_remote_port_parent(ep); + if (!node && !of_device_is_available(node)) { + of_node_put(node); + continue; + } + + dev_dbg(dev, "Subdevice node '%s' found\n", node->name); + if (match) + component_match_add(dev, match, dev_match_of, node); + of_node_put(node); + count++; + } + + if (count > 1) { + dev_err(dev, "Only one external encoder is supported\n"); + return -EINVAL; + } + + return count; +} diff --git a/drivers/gpu/drm/tilcdc/tilcdc_external.h b/drivers/gpu/drm/tilcdc/tilcdc_external.h new file mode 100644 index 000000000000..6aabe2788760 --- /dev/null +++ b/drivers/gpu/drm/tilcdc/tilcdc_external.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2015 Texas Instruments + * Author: Jyri Sarha + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef __TILCDC_EXTERNAL_H__ +#define __TILCDC_EXTERNAL_H__ + +int tilcdc_add_external_encoders(struct drm_device *dev, int *bpp); +void tilcdc_remove_external_encoders(struct drm_device *dev); +int tilcdc_get_external_components(struct device *dev, + struct component_match **match); +#endif /* __TILCDC_SLAVE_H__ */ -- cgit v1.2.3 From e3487e07b88e4a6c3782e87416b62d5d8978936a Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 27 May 2015 10:39:52 +0300 Subject: drm/tilcdc: use pm_runtime_irq_safe() tilcdc calls runtime PM get/put functions everywhere. Some of those places will be called in irq context, crashing the driver. As a quick fix, use pm_runtime_irq_safe() for tilcdc. Signed-off-by: Tomi Valkeinen Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_drv.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index fcc0508c58c0..0f283a3b932c 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -227,6 +227,7 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags) DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); pm_runtime_enable(dev->dev); + pm_runtime_irq_safe(dev->dev); /* Determine LCD IP Version */ pm_runtime_get_sync(dev->dev); -- cgit v1.2.3 From 4e7221580223ec779748d3d515ba1435bda69459 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Wed, 18 Feb 2015 11:24:03 +0200 Subject: drm/tilcdc: Add DRM_TILCDC_SLAVE_COMPAT for ti,tilcdc,slave binding support Adds a CONFIG_DRM_TILCDC_SLAVE_COMPAT module for "ti,tilcdc,slave" node conversion. The implementation is in tilcdc_slave_compat.c and it uses tilcdc_slave_compat.dts as a basis for creating a DTS overlay. The DTS overlay adds an external tda998x encoder to tilcdc that corresponds to the old tda998x based slave encoder. Signed-off-by: Jyri Sarha Acked-by: Tomi Valkeinen --- drivers/gpu/drm/tilcdc/Kconfig | 12 ++ drivers/gpu/drm/tilcdc/Makefile | 3 + drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c | 270 +++++++++++++++++++++++++ drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts | 72 +++++++ drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h | 25 +++ 5 files changed, 382 insertions(+) create mode 100644 drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c create mode 100644 drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts create mode 100644 drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h (limited to 'drivers') diff --git a/drivers/gpu/drm/tilcdc/Kconfig b/drivers/gpu/drm/tilcdc/Kconfig index 8394a0b3993e..78beafb0742c 100644 --- a/drivers/gpu/drm/tilcdc/Kconfig +++ b/drivers/gpu/drm/tilcdc/Kconfig @@ -12,3 +12,15 @@ config DRM_TILCDC Choose this option if you have an TI SoC with LCDC display controller, for example AM33xx in beagle-bone, DA8xx, or OMAP-L1xx. This driver replaces the FB_DA8XX fbdev driver. + +config DRM_TILCDC_SLAVE_COMPAT + bool "Support device tree blobs using TI LCDC Slave binding" + depends on DRM_TILCDC + default y + select OF_RESOLVE + select OF_OVERLAY + help + Choose this option if you need a kernel that is compatible + with device tree blobs using the obsolete "ti,tilcdc,slave" + binding. If you find "ti,tilcdc,slave"-string from your DTB, + you probably need this. Otherwise you do not. diff --git a/drivers/gpu/drm/tilcdc/Makefile b/drivers/gpu/drm/tilcdc/Makefile index e1f738b02c1f..deeca4869d94 100644 --- a/drivers/gpu/drm/tilcdc/Makefile +++ b/drivers/gpu/drm/tilcdc/Makefile @@ -3,6 +3,9 @@ ifeq (, $(findstring -W,$(EXTRA_CFLAGS))) ccflags-y += -Werror endif +obj-$(CONFIG_DRM_TILCDC_SLAVE_COMPAT) += tilcdc_slave_compat.o \ + tilcdc_slave_compat.dtb.o + tilcdc-y := \ tilcdc_crtc.o \ tilcdc_tfp410.o \ diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c new file mode 100644 index 000000000000..106679bca6cb --- /dev/null +++ b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c @@ -0,0 +1,270 @@ +/* + * Copyright (C) 2015 Texas Instruments + * Author: Jyri Sarha + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + */ + +/* + * To support the old "ti,tilcdc,slave" binding the binding has to be + * transformed to the new external encoder binding. + */ + +#include +#include +#include +#include +#include +#include + +#include "tilcdc_slave_compat.h" + +struct kfree_table { + int total; + int num; + void **table; +}; + +static int __init kfree_table_init(struct kfree_table *kft) +{ + kft->total = 32; + kft->num = 0; + kft->table = kmalloc(kft->total * sizeof(*kft->table), + GFP_KERNEL); + if (!kft->table) + return -ENOMEM; + + return 0; +} + +static int __init kfree_table_add(struct kfree_table *kft, void *p) +{ + if (kft->num == kft->total) { + void **old = kft->table; + + kft->total *= 2; + kft->table = krealloc(old, kft->total * sizeof(*kft->table), + GFP_KERNEL); + if (!kft->table) { + kft->table = old; + kfree(p); + return -ENOMEM; + } + } + kft->table[kft->num++] = p; + return 0; +} + +static void __init kfree_table_free(struct kfree_table *kft) +{ + int i; + + for (i = 0; i < kft->num; i++) + kfree(kft->table[i]); + + kfree(kft->table); +} + +static +struct property * __init tilcdc_prop_dup(const struct property *prop, + struct kfree_table *kft) +{ + struct property *nprop; + + nprop = kzalloc(sizeof(*nprop), GFP_KERNEL); + if (!nprop || kfree_table_add(kft, nprop)) + return NULL; + + nprop->name = kstrdup(prop->name, GFP_KERNEL); + if (!nprop->name || kfree_table_add(kft, nprop->name)) + return NULL; + + nprop->value = kmemdup(prop->value, prop->length, GFP_KERNEL); + if (!nprop->value || kfree_table_add(kft, nprop->value)) + return NULL; + + nprop->length = prop->length; + + return nprop; +} + +static void __init tilcdc_copy_props(struct device_node *from, + struct device_node *to, + const char * const props[], + struct kfree_table *kft) +{ + struct property *prop; + int i; + + for (i = 0; props[i]; i++) { + prop = of_find_property(from, props[i], NULL); + if (!prop) + continue; + + prop = tilcdc_prop_dup(prop, kft); + if (!prop) + continue; + + prop->next = to->properties; + to->properties = prop; + } +} + +static int __init tilcdc_prop_str_update(struct property *prop, + const char *str, + struct kfree_table *kft) +{ + prop->value = kstrdup(str, GFP_KERNEL); + if (kfree_table_add(kft, prop->value) || !prop->value) + return -ENOMEM; + prop->length = strlen(str)+1; + return 0; +} + +static void __init tilcdc_node_disable(struct device_node *node) +{ + struct property *prop; + + prop = kzalloc(sizeof(*prop), GFP_KERNEL); + if (!prop) + return; + + prop->name = "status"; + prop->value = "disabled"; + prop->length = strlen((char *)prop->value)+1; + + of_update_property(node, prop); +} + +struct device_node * __init tilcdc_get_overlay(struct kfree_table *kft) +{ + const int size = __dtb_tilcdc_slave_compat_end - + __dtb_tilcdc_slave_compat_begin; + static void *overlay_data; + struct device_node *overlay; + int ret; + + if (!size) { + pr_warn("%s: No overlay data\n", __func__); + return NULL; + } + + overlay_data = kmemdup(__dtb_tilcdc_slave_compat_begin, + size, GFP_KERNEL); + if (!overlay_data || kfree_table_add(kft, overlay_data)) + return NULL; + + of_fdt_unflatten_tree(overlay_data, &overlay); + if (!overlay) { + pr_warn("%s: Unfattening overlay tree failed\n", __func__); + return NULL; + } + + of_node_set_flag(overlay, OF_DETACHED); + ret = of_resolve_phandles(overlay); + if (ret) { + pr_err("%s: Failed to resolve phandles: %d\n", __func__, ret); + return NULL; + } + + return overlay; +} + +static const struct of_device_id tilcdc_slave_of_match[] __initconst = { + { .compatible = "ti,tilcdc,slave", }, + {}, +}; + +static const struct of_device_id tilcdc_of_match[] __initconst = { + { .compatible = "ti,am33xx-tilcdc", }, + {}, +}; + +static const struct of_device_id tilcdc_tda998x_of_match[] __initconst = { + { .compatible = "nxp,tda998x", }, + {}, +}; + +static const char * const tilcdc_slave_props[] __initconst = { + "pinctrl-names", + "pinctrl-0", + "pinctrl-1", + NULL +}; + +void __init tilcdc_convert_slave_node(void) +{ + struct device_node *slave = NULL, *lcdc = NULL; + struct device_node *i2c = NULL, *fragment = NULL; + struct device_node *overlay, *encoder; + struct property *prop; + /* For all memory needed for the overlay tree. This memory can + be freed after the overlay has been applied. */ + struct kfree_table kft; + int ret; + + if (kfree_table_init(&kft)) + goto out; + + lcdc = of_find_matching_node(NULL, tilcdc_of_match); + slave = of_find_matching_node(NULL, tilcdc_slave_of_match); + + if (!slave || !of_device_is_available(lcdc)) + goto out; + + i2c = of_parse_phandle(slave, "i2c", 0); + if (!i2c) { + pr_err("%s: Can't find i2c node trough phandle\n", __func__); + goto out; + } + + overlay = tilcdc_get_overlay(&kft); + if (!overlay) + goto out; + + encoder = of_find_matching_node(overlay, tilcdc_tda998x_of_match); + if (!encoder) { + pr_err("%s: Failed to find tda998x node\n", __func__); + goto out; + } + + tilcdc_copy_props(slave, encoder, tilcdc_slave_props, &kft); + + for_each_child_of_node(overlay, fragment) { + prop = of_find_property(fragment, "target-path", NULL); + if (!prop) + continue; + if (!strncmp("i2c", (char *)prop->value, prop->length)) + if (tilcdc_prop_str_update(prop, i2c->full_name, &kft)) + goto out; + if (!strncmp("lcdc", (char *)prop->value, prop->length)) + if (tilcdc_prop_str_update(prop, lcdc->full_name, &kft)) + goto out; + } + + tilcdc_node_disable(slave); + + ret = of_overlay_create(overlay); + if (ret) + pr_err("%s: Creating overlay failed: %d\n", __func__, ret); + else + pr_info("%s: ti,tilcdc,slave node successfully converted\n", + __func__); +out: + kfree_table_free(&kft); + of_node_put(i2c); + of_node_put(slave); + of_node_put(lcdc); + of_node_put(fragment); +} + +int __init tilcdc_slave_compat_init(void) +{ + tilcdc_convert_slave_node(); + return 0; +} + +subsys_initcall(tilcdc_slave_compat_init); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts new file mode 100644 index 000000000000..693f8b0aea2d --- /dev/null +++ b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts @@ -0,0 +1,72 @@ +/* + * DTS overlay for converting ti,tilcdc,slave binding to new binding. + * + * Copyright (C) 2015 Texas Instruments Inc. + * Author: Jyri Sarha + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + */ + +/* + * target-path property values are simple tags that are replaced with + * correct values in tildcdc_slave_compat.c. Some properties are also + * copied over from the ti,tilcdc,slave node. + */ + +/dts-v1/; +/ { + fragment@0 { + target-path = "i2c"; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + tda19988 { + compatible = "nxp,tda998x"; + reg = <0x70>; + status = "okay"; + + port { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcd_0>; + }; + }; + }; + }; + }; + + fragment@1 { + target-path = "lcdc"; + __overlay__ { + port { + lcd_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; + }; + }; + + __local_fixups__ { + fragment@0 { + __overlay__ { + tda19988 { + port { + endpoint@0 { + remote-endpoint = <0>; + }; + }; + }; + }; + }; + fragment@1 { + __overlay__ { + port { + endpoint@0 { + remote-endpoint = <0>; + }; + }; + }; + }; + }; +}; diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h new file mode 100644 index 000000000000..403d35d87d0b --- /dev/null +++ b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2015 Texas Instruments + * Author: Jyri Sarha + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ +/* This header declares the symbols defined in tilcdc_slave_compat.dts */ + +#ifndef __TILCDC_SLAVE_COMPAT_H__ +#define __TILCDC_SLAVE_COMPAT_H__ + +extern uint8_t __dtb_tilcdc_slave_compat_begin[]; +extern uint8_t __dtb_tilcdc_slave_compat_end[]; + +#endif /* __TILCDC_SLAVE_COMPAT_H__ */ -- cgit v1.2.3 From c87d2453a1c08da778103d56fd84df37920889e9 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Wed, 18 Feb 2015 12:26:50 +0200 Subject: drm/tilcdc: Force building of DRM_TILCDC_SLAVE_COMPAT If I read Documentation/kbuild/makefiles.txt section 3.6 right, this patch should not be needed. However, without this patch the objects needed for DRM_TILCDC_SLAVE_COMPAT are not linked, if DRM_TILCDC is built as module. Signed-off-by: Jyri Sarha Acked-by: Tomi Valkeinen --- drivers/gpu/drm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 7d4944e1a60c..6081fa64b2d9 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -60,7 +60,7 @@ obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc/ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/ obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/ obj-$(CONFIG_DRM_OMAP) += omapdrm/ -obj-$(CONFIG_DRM_TILCDC) += tilcdc/ +obj-y += tilcdc/ obj-$(CONFIG_DRM_QXL) += qxl/ obj-$(CONFIG_DRM_BOCHS) += bochs/ obj-$(CONFIG_DRM_MSM) += msm/ -- cgit v1.2.3 From 5ceecb2fa720c01a97e6fa2353c2b8f1e8d69f1f Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Tue, 26 May 2015 17:53:38 +0900 Subject: drm: Fix off-by-one in vblank hardware counter wraparound handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dev->max_vblank_count contains the largest value that can be represented by the hardware counter. When the hardware counter wraps around, we have to add that value + 1 to get the same value as if the hardware counter didn't wrap around. Signed-off-by: Michel Dänzer Reviewed-by: Christian König Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_irq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index 1967e7fc9805..6f02b4b560b8 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -130,7 +130,7 @@ static void drm_update_vblank_count(struct drm_device *dev, int crtc) /* * Interrupts were disabled prior to this call, so deal with counter * wrap if needed. - * NOTE! It's possible we lost a full dev->max_vblank_count events + * NOTE! It's possible we lost a full dev->max_vblank_count + 1 events * here if the register is small or we had vblank interrupts off for * a long time. * @@ -147,7 +147,7 @@ static void drm_update_vblank_count(struct drm_device *dev, int crtc) /* Deal with counter wrap */ diff = cur_vblank - vblank->last; if (cur_vblank < vblank->last) { - diff += dev->max_vblank_count; + diff += dev->max_vblank_count + 1; DRM_DEBUG("last_vblank[%d]=0x%x, cur_vblank=0x%x => diff=0x%x\n", crtc, vblank->last, cur_vblank, diff); -- cgit v1.2.3 From d63f820f39ee7b3f8dd4ac04ff27511fbf653e9a Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Mon, 27 Apr 2015 12:31:44 +0100 Subject: drm/i915: Remove unnecessary null check in execlists_context_unqueue commit 53292cdb066950611e5bc2e0eb109c7edb42af78 ("drm/i915: Workaround to avoid lite restore with HEAD==TAIL") added a check for req0 != null which is unnecessary. The only way req0 could be null is if the list was empty, and this is already addressed at the beginning of execlists_context_unqueue(). Reported-by: Dan Carpenter Signed-off-by: Michel Thierry Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 96ae90affad5..9f5485ddcbe6 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -427,7 +427,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring) * WaIdleLiteRestore: make sure we never cause a lite * restore with HEAD==TAIL */ - if (req0 && req0->elsp_submitted) { + if (req0->elsp_submitted) { /* * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL * as we resubmit the request. See gen8_emit_request() -- cgit v1.2.3 From 010621936103fcfc15375ccdc92c0f583923d489 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 18 May 2015 11:11:48 -0400 Subject: drm/radeon: clean up radeon_audio_enable - make it static - fix mask/bool handling for last param Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/radeon_audio.c | 18 +++++++++--------- drivers/gpu/drm/radeon/radeon_audio.h | 2 -- 2 files changed, 9 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_audio.c b/drivers/gpu/drm/radeon/radeon_audio.c index dcb779647c57..abbc154b1bff 100644 --- a/drivers/gpu/drm/radeon/radeon_audio.c +++ b/drivers/gpu/drm/radeon/radeon_audio.c @@ -242,6 +242,13 @@ static struct radeon_audio_funcs dce6_dp_funcs = { .dpms = evergreen_dp_enable, }; +static void radeon_audio_enable(struct radeon_device *rdev, + struct r600_audio_pin *pin, u8 enable_mask) +{ + if (rdev->audio.funcs->enable) + rdev->audio.funcs->enable(rdev, pin, enable_mask); +} + static void radeon_audio_interface_init(struct radeon_device *rdev) { if (ASIC_IS_DCE6(rdev)) { @@ -307,7 +314,7 @@ int radeon_audio_init(struct radeon_device *rdev) /* disable audio. it will be set up later */ for (i = 0; i < rdev->audio.num_pins; i++) - radeon_audio_enable(rdev, &rdev->audio.pin[i], false); + radeon_audio_enable(rdev, &rdev->audio.pin[i], 0); return 0; } @@ -443,13 +450,6 @@ static void radeon_audio_select_pin(struct drm_encoder *encoder) radeon_encoder->audio->select_pin(encoder); } -void radeon_audio_enable(struct radeon_device *rdev, - struct r600_audio_pin *pin, u8 enable_mask) -{ - if (rdev->audio.funcs->enable) - rdev->audio.funcs->enable(rdev, pin, enable_mask); -} - void radeon_audio_detect(struct drm_connector *connector, enum drm_connector_status status) { @@ -505,7 +505,7 @@ void radeon_audio_fini(struct radeon_device *rdev) return; for (i = 0; i < rdev->audio.num_pins; i++) - radeon_audio_enable(rdev, &rdev->audio.pin[i], false); + radeon_audio_enable(rdev, &rdev->audio.pin[i], 0); rdev->audio.enabled = false; } diff --git a/drivers/gpu/drm/radeon/radeon_audio.h b/drivers/gpu/drm/radeon/radeon_audio.h index c92d059ab204..8438304f7139 100644 --- a/drivers/gpu/drm/radeon/radeon_audio.h +++ b/drivers/gpu/drm/radeon/radeon_audio.h @@ -74,8 +74,6 @@ u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, void radeon_audio_endpoint_wreg(struct radeon_device *rdev, u32 offset, u32 reg, u32 v); struct r600_audio_pin *radeon_audio_get_pin(struct drm_encoder *encoder); -void radeon_audio_enable(struct radeon_device *rdev, - struct r600_audio_pin *pin, u8 enable_mask); void radeon_audio_fini(struct radeon_device *rdev); void radeon_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode); -- cgit v1.2.3 From 161ab658a611df14fb0365b7b70a8c5fed3e4870 Mon Sep 17 00:00:00 2001 From: Christian König Date: Tue, 26 May 2015 12:24:15 +0200 Subject: drm/radeon: stop using addr to check for BO move MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is theoretically possible that a swapped out BO gets the same GTT address, but different backing pages while being swapped in. Instead just use another VA state to note updated areas. Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon.h | 4 ++- drivers/gpu/drm/radeon/radeon_vm.c | 53 +++++++++++++++++++++----------------- 2 files changed, 32 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index b0b73f2edfc9..2ffca1d920d4 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -467,7 +467,6 @@ struct radeon_bo_va { /* protected by bo being reserved */ struct list_head bo_list; uint32_t flags; - uint64_t addr; struct radeon_fence *last_pt_update; unsigned ref_count; @@ -941,6 +940,9 @@ struct radeon_vm { /* BOs freed, but not yet updated in the PT */ struct list_head freed; + /* BOs cleared in the PT */ + struct list_head cleared; + /* contains the page directory */ struct radeon_bo *page_directory; unsigned max_pde_used; diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c index de42fc4a22b8..9739ded91b7a 100644 --- a/drivers/gpu/drm/radeon/radeon_vm.c +++ b/drivers/gpu/drm/radeon/radeon_vm.c @@ -331,7 +331,6 @@ struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, bo_va->it.start = 0; bo_va->it.last = 0; bo_va->flags = 0; - bo_va->addr = 0; bo_va->ref_count = 1; INIT_LIST_HEAD(&bo_va->bo_list); INIT_LIST_HEAD(&bo_va->vm_status); @@ -491,9 +490,11 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev, } if (bo_va->it.start || bo_va->it.last) { - if (bo_va->addr) { + spin_lock(&vm->status_lock); + if (list_empty(&bo_va->vm_status)) { /* add a clone of the bo_va to clear the old address */ struct radeon_bo_va *tmp; + spin_unlock(&vm->status_lock); tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); if (!tmp) { mutex_unlock(&vm->mutex); @@ -502,14 +503,11 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev, tmp->it.start = bo_va->it.start; tmp->it.last = bo_va->it.last; tmp->vm = vm; - tmp->addr = bo_va->addr; tmp->bo = radeon_bo_ref(bo_va->bo); spin_lock(&vm->status_lock); list_add(&tmp->vm_status, &vm->freed); - spin_unlock(&vm->status_lock); - - bo_va->addr = 0; } + spin_unlock(&vm->status_lock); interval_tree_remove(&bo_va->it, &vm->va); bo_va->it.start = 0; @@ -520,10 +518,12 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev, bo_va->it.start = soffset; bo_va->it.last = eoffset - 1; interval_tree_insert(&bo_va->it, &vm->va); + spin_lock(&vm->status_lock); + list_add(&bo_va->vm_status, &vm->cleared); + spin_unlock(&vm->status_lock); } bo_va->flags = flags; - bo_va->addr = 0; soffset >>= radeon_vm_block_size; eoffset >>= radeon_vm_block_size; @@ -921,7 +921,16 @@ int radeon_vm_bo_update(struct radeon_device *rdev, } spin_lock(&vm->status_lock); - list_del_init(&bo_va->vm_status); + if (mem) { + if (list_empty(&bo_va->vm_status)) { + spin_unlock(&vm->status_lock); + return 0; + } + list_del_init(&bo_va->vm_status); + } else { + list_del(&bo_va->vm_status); + list_add(&bo_va->vm_status, &vm->cleared); + } spin_unlock(&vm->status_lock); bo_va->flags &= ~RADEON_VM_PAGE_VALID; @@ -947,10 +956,6 @@ int radeon_vm_bo_update(struct radeon_device *rdev, addr = 0; } - if (addr == bo_va->addr) - return 0; - bo_va->addr = addr; - trace_radeon_vm_bo_update(bo_va); nptes = bo_va->it.last - bo_va->it.start + 1; @@ -1038,7 +1043,7 @@ int radeon_vm_clear_freed(struct radeon_device *rdev, struct radeon_vm *vm) { struct radeon_bo_va *bo_va; - int r; + int r = 0; spin_lock(&vm->status_lock); while (!list_empty(&vm->freed)) { @@ -1049,14 +1054,15 @@ int radeon_vm_clear_freed(struct radeon_device *rdev, r = radeon_vm_bo_update(rdev, bo_va, NULL); radeon_bo_unref(&bo_va->bo); radeon_fence_unref(&bo_va->last_pt_update); + spin_lock(&vm->status_lock); + list_del(&bo_va->vm_status); kfree(bo_va); if (r) - return r; + break; - spin_lock(&vm->status_lock); } spin_unlock(&vm->status_lock); - return 0; + return r; } @@ -1114,14 +1120,14 @@ void radeon_vm_bo_rmv(struct radeon_device *rdev, mutex_lock(&vm->mutex); if (bo_va->it.start || bo_va->it.last) interval_tree_remove(&bo_va->it, &vm->va); - spin_lock(&vm->status_lock); - list_del(&bo_va->vm_status); - if (bo_va->addr) { + spin_lock(&vm->status_lock); + if (list_empty(&bo_va->vm_status)) { bo_va->bo = radeon_bo_ref(bo_va->bo); list_add(&bo_va->vm_status, &vm->freed); } else { radeon_fence_unref(&bo_va->last_pt_update); + list_del(&bo_va->vm_status); kfree(bo_va); } spin_unlock(&vm->status_lock); @@ -1144,12 +1150,10 @@ void radeon_vm_bo_invalidate(struct radeon_device *rdev, struct radeon_bo_va *bo_va; list_for_each_entry(bo_va, &bo->va, bo_list) { - if (bo_va->addr) { - spin_lock(&bo_va->vm->status_lock); - list_del(&bo_va->vm_status); + spin_lock(&bo_va->vm->status_lock); + if (list_empty(&bo_va->vm_status)) list_add(&bo_va->vm_status, &bo_va->vm->invalidated); - spin_unlock(&bo_va->vm->status_lock); - } + spin_unlock(&bo_va->vm->status_lock); } } @@ -1179,6 +1183,7 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm) spin_lock_init(&vm->status_lock); INIT_LIST_HEAD(&vm->invalidated); INIT_LIST_HEAD(&vm->freed); + INIT_LIST_HEAD(&vm->cleared); pd_size = radeon_vm_directory_size(rdev); pd_entries = radeon_vm_num_pdes(rdev); -- cgit v1.2.3 From b0b9bb4dd51f396dcf843831905f729e74b0c8c0 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Tue, 26 May 2015 17:53:39 +0900 Subject: drm/radeon: Fix max_vblank_count value for current display engines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The value was much too low, which could cause the userspace visible vblank counter to move backwards when the hardware counter wrapped around. Reviewed-by: Christian König Signed-off-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_irq_kms.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c index f682e5351252..1162bfa464f3 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -145,7 +145,13 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev) */ int radeon_driver_irq_postinstall_kms(struct drm_device *dev) { - dev->max_vblank_count = 0x001fffff; + struct radeon_device *rdev = dev->dev_private; + + if (ASIC_IS_AVIVO(rdev)) + dev->max_vblank_count = 0x00ffffff; + else + dev->max_vblank_count = 0x001fffff; + return 0; } -- cgit v1.2.3 From bc284542dad88046eefa3a8d4d9907529c4af9e0 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 26 May 2015 20:22:38 +0300 Subject: drm/i915: Use the default 600ns LDO programming sequence delay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not sure which LDO programming sequence delay should be used for the CHV PHY, but the spec says that 600ns is "Used by default for initial bringup", and the BIOS seems to use that, so let's do the same. Reviewed-by: Deepak S Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++ 2 files changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 607766d0a15d..e5910b76043e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2145,6 +2145,10 @@ enum skl_disp_power_wells { #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) #define DPLL_PORTD_READY_MASK (0xf) #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) +#define PHY_LDO_DELAY_0NS 0x0 +#define PHY_LDO_DELAY_200NS 0x1 +#define PHY_LDO_DELAY_600NS 0x2 +#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23)) #define PHY_CH_SU_PSR 0x1 #define PHY_CH_DEEP_PSR 0x7 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2)) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 3800be4ad76b..720b0c63b63c 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1724,6 +1724,8 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) * value. */ dev_priv->chv_phy_control = + PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | + PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH0) | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH1) | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY1, DPIO_CH0); -- cgit v1.2.3 From fde61e4b80ff23a379210a5780e59ace4bd915e6 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 26 May 2015 20:22:39 +0300 Subject: drm/i915: Throw out WIP CHV power well definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Expecting CHV power wells to be just an extended versions of the VLV power wells, a bunch of commented out power wells were added in anticipation when Punit folks would implement it all. Turns out they never did, and instead CHV has fewer power wells than VLV. Rip out all the #if 0'ed junk that's not needed. v2: Rename the "pipe-a" well to "display" to match VLV Clarify the pipe A power well relationship to pipes B and C (Deepak) Reviewed-by: Deepak S Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 4 -- drivers/gpu/drm/i915/intel_runtime_pm.c | 98 ++------------------------------- 2 files changed, 4 insertions(+), 98 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e5910b76043e..6d3fead3a358 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -595,10 +595,6 @@ enum punit_power_well { PUNIT_POWER_WELL_DPIO_RX0 = 10, PUNIT_POWER_WELL_DPIO_RX1 = 11, PUNIT_POWER_WELL_DPIO_CMN_D = 12, - /* FIXME: guesswork below */ - PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, - PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, - PUNIT_POWER_WELL_DPIO_RX2 = 15, PUNIT_POWER_WELL_NUM, }; diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 720b0c63b63c..1a45385f4d66 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1233,18 +1233,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT(POWER_DOMAIN_AUX_C) | \ BIT(POWER_DOMAIN_INIT)) -#define CHV_PIPE_A_POWER_DOMAINS ( \ - BIT(POWER_DOMAIN_PIPE_A) | \ - BIT(POWER_DOMAIN_INIT)) - -#define CHV_PIPE_B_POWER_DOMAINS ( \ - BIT(POWER_DOMAIN_PIPE_B) | \ - BIT(POWER_DOMAIN_INIT)) - -#define CHV_PIPE_C_POWER_DOMAINS ( \ - BIT(POWER_DOMAIN_PIPE_C) | \ - BIT(POWER_DOMAIN_INIT)) - #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ @@ -1260,17 +1248,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT(POWER_DOMAIN_AUX_D) | \ BIT(POWER_DOMAIN_INIT)) -#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ - BIT(POWER_DOMAIN_AUX_D) | \ - BIT(POWER_DOMAIN_INIT)) - -#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ - BIT(POWER_DOMAIN_AUX_D) | \ - BIT(POWER_DOMAIN_INIT)) - static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { .sync_hw = i9xx_always_on_power_well_noop, .enable = i9xx_always_on_power_well_noop, @@ -1428,40 +1405,17 @@ static struct i915_power_well chv_power_wells[] = { .domains = VLV_ALWAYS_ON_POWER_DOMAINS, .ops = &i9xx_always_on_power_well_ops, }, -#if 0 { .name = "display", - .domains = VLV_DISPLAY_POWER_DOMAINS, - .data = PUNIT_POWER_WELL_DISP2D, - .ops = &vlv_display_power_well_ops, - }, -#endif - { - .name = "pipe-a", /* - * FIXME: pipe A power well seems to be the new disp2d well. - * At least all registers seem to be housed there. Figure - * out if this a a temporary situation in pre-production - * hardware or a permanent state of affairs. + * Pipe A power well is the new disp2d well. Pipe B and C + * power wells don't actually exist. Pipe A power well is + * required for any pipe to work. */ - .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, + .domains = VLV_DISPLAY_POWER_DOMAINS, .data = PIPE_A, .ops = &chv_pipe_power_well_ops, }, -#if 0 - { - .name = "pipe-b", - .domains = CHV_PIPE_B_POWER_DOMAINS, - .data = PIPE_B, - .ops = &chv_pipe_power_well_ops, - }, - { - .name = "pipe-c", - .domains = CHV_PIPE_C_POWER_DOMAINS, - .data = PIPE_C, - .ops = &chv_pipe_power_well_ops, - }, -#endif { .name = "dpio-common-bc", .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, @@ -1474,50 +1428,6 @@ static struct i915_power_well chv_power_wells[] = { .data = PUNIT_POWER_WELL_DPIO_CMN_D, .ops = &chv_dpio_cmn_power_well_ops, }, -#if 0 - { - .name = "dpio-tx-b-01", - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, - }, - { - .name = "dpio-tx-b-23", - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, - }, - { - .name = "dpio-tx-c-01", - .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, - }, - { - .name = "dpio-tx-c-23", - .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, - }, - { - .name = "dpio-tx-d-01", - .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | - CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, - }, - { - .name = "dpio-tx-d-23", - .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | - CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, - }, -#endif }; static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, -- cgit v1.2.3 From b12ce1d84fd6ba36914ace0d27a0e675e284e6ae Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 26 May 2015 20:27:23 +0300 Subject: drm/i915: Kill intel_flush_primary_plane() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The primary plane frobbing was removed from the sprite code in commit ecce87ea3ab55ad0dc64460e6422c357d158a55e Author: Maarten Lankhorst Date: Tue Apr 21 17:12:50 2015 +0300 drm/i915: Remove implicitly disabling primary plane for now but the intel_flush_primary_plane() calls were left behind. Replace them with straight forward POSTING_READ() of the sprite surface address register. The other user of intel_flush_primary_plane() is g4x_disable_trickle_feed() where we can just inline the steps directly. This allows intel_flush_primary_plane() to be killed off. Cc: Maarten Lankhorst Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 14 -------------- drivers/gpu/drm/i915/intel_drv.h | 2 -- drivers/gpu/drm/i915/intel_pm.c | 6 ++++-- drivers/gpu/drm/i915/intel_sprite.c | 30 +++++++----------------------- 4 files changed, 11 insertions(+), 41 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 657a33366e92..27792c1f98c0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2210,20 +2210,6 @@ static void intel_disable_pipe(struct intel_crtc *crtc) intel_wait_for_pipe_off(crtc); } -/* - * Plane regs are double buffered, going from enabled->disabled needs a - * trigger in order to latch. The display address reg provides this. - */ -void intel_flush_primary_plane(struct drm_i915_private *dev_priv, - enum plane plane) -{ - struct drm_device *dev = dev_priv->dev; - u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); - - I915_WRITE(reg, I915_READ(reg)); - POSTING_READ(reg); -} - /** * intel_enable_primary_hw_plane - enable the primary plane on a given pipe * @plane: plane to be enabled diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 02d83178bd03..2afb31a46275 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1383,8 +1383,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); /* intel_sprite.c */ int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); -void intel_flush_primary_plane(struct drm_i915_private *dev_priv, - enum plane plane); int intel_plane_restore(struct drm_plane *plane); int intel_sprite_set_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 79843215d90c..148ebf5df811 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5886,13 +5886,15 @@ static void ibx_init_clock_gating(struct drm_device *dev) static void g4x_disable_trickle_feed(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int pipe; + enum pipe pipe; for_each_pipe(dev_priv, pipe) { I915_WRITE(DSPCNTR(pipe), I915_READ(DSPCNTR(pipe)) | DISPPLANE_TRICKLE_FEED_DISABLE); - intel_flush_primary_plane(dev_priv, pipe); + + I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); + POSTING_READ(DSPSURF(pipe)); } } diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 2a90308cc9c0..8193a35388d7 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -282,7 +282,6 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force) I915_WRITE(PLANE_CTL(pipe, plane), 0); - /* Activate double buffered register update */ I915_WRITE(PLANE_SURF(pipe, plane), 0); POSTING_READ(PLANE_SURF(pipe, plane)); @@ -339,7 +338,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, struct drm_device *dev = dplane->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_plane *intel_plane = to_intel_plane(dplane); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct drm_i915_gem_object *obj = intel_fb_obj(fb); int pipe = intel_plane->pipe; int plane = intel_plane->plane; @@ -453,8 +451,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, I915_WRITE(SPCNTR(pipe, plane), sprctl); I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); - - intel_flush_primary_plane(dev_priv, intel_crtc->plane); + POSTING_READ(SPSURF(pipe, plane)); } static void @@ -463,21 +460,17 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force) struct drm_device *dev = dplane->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_plane *intel_plane = to_intel_plane(dplane); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_plane->pipe; int plane = intel_plane->plane; I915_WRITE(SPCNTR(pipe, plane), 0); - /* Activate double buffered register update */ I915_WRITE(SPSURF(pipe, plane), 0); - - intel_flush_primary_plane(dev_priv, intel_crtc->plane); + POSTING_READ(SPSURF(pipe, plane)); intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); } - static void ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, struct drm_framebuffer *fb, @@ -489,7 +482,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, struct drm_device *dev = plane->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_plane *intel_plane = to_intel_plane(plane); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct drm_i915_gem_object *obj = intel_fb_obj(fb); enum pipe pipe = intel_plane->pipe; u32 sprctl, sprscale = 0; @@ -599,8 +591,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, I915_WRITE(SPRCTL(pipe), sprctl); I915_WRITE(SPRSURF(pipe), i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); - - intel_flush_primary_plane(dev_priv, intel_crtc->plane); + POSTING_READ(SPRSURF(pipe)); } static void @@ -609,17 +600,15 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force) struct drm_device *dev = plane->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_plane *intel_plane = to_intel_plane(plane); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_plane->pipe; I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); /* Can't leave the scaler enabled... */ if (intel_plane->can_scale) I915_WRITE(SPRSCALE(pipe), 0); - /* Activate double buffered register update */ - I915_WRITE(SPRSURF(pipe), 0); - intel_flush_primary_plane(dev_priv, intel_crtc->plane); + I915_WRITE(SPRSURF(pipe), 0); + POSTING_READ(SPRSURF(pipe)); } static void @@ -633,7 +622,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, struct drm_device *dev = plane->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_plane *intel_plane = to_intel_plane(plane); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct drm_i915_gem_object *obj = intel_fb_obj(fb); int pipe = intel_plane->pipe; unsigned long dvssurf_offset, linear_offset; @@ -730,8 +718,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, I915_WRITE(DVSCNTR(pipe), dvscntr); I915_WRITE(DVSSURF(pipe), i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); - - intel_flush_primary_plane(dev_priv, intel_crtc->plane); + POSTING_READ(DVSSURF(pipe)); } static void @@ -740,17 +727,14 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force) struct drm_device *dev = plane->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_plane *intel_plane = to_intel_plane(plane); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_plane->pipe; I915_WRITE(DVSCNTR(pipe), 0); /* Disable the scaler */ I915_WRITE(DVSSCALE(pipe), 0); - /* Flush double buffered register updates */ I915_WRITE(DVSSURF(pipe), 0); - - intel_flush_primary_plane(dev_priv, intel_crtc->plane); + POSTING_READ(DVSSURF(pipe)); } static int -- cgit v1.2.3 From a580516d9fcb09b86337895e483c93ad6c1ce4b5 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 26 May 2015 20:42:30 +0300 Subject: drm/i915: s/dpio_lock/sb_lock/ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename dpio_lock to sb_lock to inform the reader that its primary purpose is to protect the sideband mailbox rather than some DPIO state. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_dma.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 4 +-- drivers/gpu/drm/i915/intel_display.c | 56 +++++++++++++++--------------- drivers/gpu/drm/i915/intel_dp.c | 28 +++++++-------- drivers/gpu/drm/i915/intel_dsi.c | 8 ++--- drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 4 +-- drivers/gpu/drm/i915/intel_dsi_pll.c | 14 ++++---- drivers/gpu/drm/i915/intel_hdmi.c | 24 ++++++------- drivers/gpu/drm/i915/intel_pm.c | 4 +-- drivers/gpu/drm/i915/intel_sideband.c | 18 +++++----- 10 files changed, 81 insertions(+), 81 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index a238889630d8..d2df321ba634 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -814,7 +814,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) spin_lock_init(&dev_priv->uncore.lock); spin_lock_init(&dev_priv->mm.object_stat_lock); spin_lock_init(&dev_priv->mmio_flip_lock); - mutex_init(&dev_priv->dpio_lock); + mutex_init(&dev_priv->sb_lock); mutex_init(&dev_priv->modeset_restore_lock); mutex_init(&dev_priv->csr_lock); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3f6cad96ee91..72f5a3f9dbf2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1666,8 +1666,8 @@ struct drm_i915_private { /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ struct pm_qos_request pm_qos; - /* DPIO indirect register protection */ - struct mutex dpio_lock; + /* Sideband mailbox protection */ + struct mutex sb_lock; /** Cached value of IMR to avoid reads in updating the bitfield */ union { diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 27792c1f98c0..72b652940edd 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1140,9 +1140,9 @@ static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) u32 val; bool cur_state; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); cur_state = val & DSI_PLL_VCO_EN; I915_STATE_WARN(cur_state != state, @@ -1661,7 +1661,7 @@ static void chv_enable_pll(struct intel_crtc *crtc, BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* Enable back the 10bit clock to display controller */ tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); @@ -1684,7 +1684,7 @@ static void chv_enable_pll(struct intel_crtc *crtc, I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); POSTING_READ(DPLL_MD(pipe)); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static int intel_num_dvo_pipes(struct drm_device *dev) @@ -1826,7 +1826,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) I915_WRITE(DPLL(pipe), val); POSTING_READ(DPLL(pipe)); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* Disable 10bit clock to display controller */ val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); @@ -1844,7 +1844,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); } - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } void vlv_wait_port_ready(struct drm_i915_private *dev_priv, @@ -3939,7 +3939,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc) u32 divsel, phaseinc, auxdiv, phasedir = 0; u32 temp; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* It is necessary to ungate the pixclk gate prior to programming * the divisors, and gate it back when it is done. @@ -4016,7 +4016,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc) I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, @@ -5728,10 +5728,10 @@ static int valleyview_get_vco(struct drm_i915_private *dev_priv) int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; /* Obtain SKU information */ - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & CCK_FUSE_HPLL_FREQ_MASK; - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); return vco_freq[hpll_freq] * 1000; } @@ -5785,7 +5785,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* adjust cdclk divider */ val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); val &= ~DISPLAY_FREQUENCY_VALUES; @@ -5796,10 +5796,10 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), 50)) DRM_ERROR("timed out waiting for CDclk change\n"); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* adjust self-refresh exit latency value */ val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); val &= ~0x7f; @@ -5813,7 +5813,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) else val |= 3000 / 250; /* 3.0 usec */ vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); vlv_update_cdclk(dev); } @@ -6741,9 +6741,9 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev) if (dev_priv->hpll_freq == 0) dev_priv->hpll_freq = valleyview_get_vco(dev_priv); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); divider = val & DISPLAY_FREQUENCY_VALUES; @@ -7085,7 +7085,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc, u32 bestn, bestm1, bestm2, bestp1, bestp2; u32 coreclk, reg_val; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); bestn = pipe_config->dpll.n; bestm1 = pipe_config->dpll.m1; @@ -7163,7 +7163,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc, vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static void chv_update_pll(struct intel_crtc *crtc, @@ -7208,7 +7208,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, I915_WRITE(dpll_reg, pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* p1 and p2 divider */ vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), @@ -7281,7 +7281,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | DPIO_AFC_RECAL); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } /** @@ -7782,9 +7782,9 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc, if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) return; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; clock.m2 = mdiv & DPIO_M2DIV_MASK; @@ -7878,12 +7878,12 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; int refclk = 100000; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); @@ -8249,7 +8249,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, with_fdi, "LP PCH doesn't have FDI\n")) with_fdi = false; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); tmp &= ~SBI_SSCCTL_DISABLE; @@ -8275,7 +8275,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } /* Sequence to disable CLKOUT_DP */ @@ -8284,7 +8284,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; uint32_t reg, tmp; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? SBI_GEN0 : SBI_DBUFF0; @@ -8303,7 +8303,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev) intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); } - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static void lpt_init_pch_refclk(struct drm_device *dev) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index abd442af4127..5b01f81aec48 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2355,7 +2355,7 @@ static void chv_post_disable_dp(struct intel_encoder *encoder) intel_dp_link_down(intel_dp); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* Propagate soft reset to data lane reset */ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); @@ -2374,7 +2374,7 @@ static void chv_post_disable_dp(struct intel_encoder *encoder) val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static void @@ -2671,7 +2671,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder) int pipe = intel_crtc->pipe; u32 val; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); val = 0; @@ -2684,7 +2684,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder) vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); intel_enable_dp(encoder); } @@ -2702,7 +2702,7 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) intel_dp_prepare(encoder); /* Program Tx lane resets to default */ - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); @@ -2716,7 +2716,7 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static void chv_pre_enable_dp(struct intel_encoder *encoder) @@ -2732,7 +2732,7 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) int data, i, stagger; u32 val; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* allow hardware to manage TX FIFO reset source */ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); @@ -2802,7 +2802,7 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) DPIO_TX1_STAGGER_MULT(7) | DPIO_TX2_STAGGER_MULT(5)); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); intel_enable_dp(encoder); } @@ -2820,7 +2820,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) intel_dp_prepare(encoder); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* program left/right clock distribution */ if (pipe != PIPE_B) { @@ -2870,7 +2870,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) val |= CHV_CMN_USEDCLKCHANNEL; vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } /* @@ -3095,7 +3095,7 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) return 0; } - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), @@ -3104,7 +3104,7 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); return 0; } @@ -3191,7 +3191,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp) return 0; } - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* Clear calc init */ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); @@ -3278,7 +3278,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp) val |= DPIO_LRC_BYPASS; vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); return 0; } diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 51966426addf..b5a5558ecd63 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -239,7 +239,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, static void band_gap_reset(struct drm_i915_private *dev_priv) { - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); vlv_flisdsi_write(dev_priv, 0x08, 0x0001); vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); @@ -248,7 +248,7 @@ static void band_gap_reset(struct drm_i915_private *dev_priv) vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); vlv_flisdsi_write(dev_priv, 0x08, 0x0000); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static inline bool is_vid_mode(struct intel_dsi *intel_dsi) @@ -346,11 +346,11 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) DRM_DEBUG_KMS("\n"); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* program rcomp for compliance, reduce from 50 ohms to 45 ohms * needed everytime after power gate */ vlv_flisdsi_write(dev_priv, 0x04, 0x0004); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); /* bandgap reset is needed after everytime we do power gate */ band_gap_reset(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index d2cd8d5b27a1..a5e99ac305da 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -212,7 +212,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) function = gtable[gpio].function_reg; pad = gtable[gpio].pad_reg; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); if (!gtable[gpio].init) { /* program the function */ /* FIXME: remove constant below */ @@ -224,7 +224,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) /* pull up/down */ vlv_gpio_nc_write(dev_priv, pad, val); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); return data; } diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index 9688d996af31..d20cf37b6901 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -244,7 +244,7 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder) DRM_DEBUG_KMS("\n"); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); vlv_configure_dsi_pll(encoder); @@ -258,11 +258,11 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder) if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_LOCK, 20)) { - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); DRM_ERROR("DSI PLL lock failed\n"); return; } - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); DRM_DEBUG_KMS("DSI PLL locked\n"); } @@ -274,14 +274,14 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder) DRM_DEBUG_KMS("\n"); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); tmp &= ~DSI_PLL_VCO_EN; tmp |= DSI_PLL_LDO_GATE; vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) @@ -319,10 +319,10 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) DRM_DEBUG_KMS("\n"); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); /* mask out other bits and extract the P1 divisor */ pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index e7e90610cc6f..4117092ab2e3 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1293,7 +1293,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) u32 val; /* Enable clock channels for this port */ - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); val = 0; if (pipe) @@ -1316,7 +1316,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) /* Program lane clock */ vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); intel_hdmi->set_infoframes(&encoder->base, intel_crtc->config->has_hdmi_sink, @@ -1340,7 +1340,7 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) intel_hdmi_prepare(encoder); /* Program Tx lane resets to default */ - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); @@ -1357,7 +1357,7 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) @@ -1373,7 +1373,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) intel_hdmi_prepare(encoder); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* program left/right clock distribution */ if (pipe != PIPE_B) { @@ -1423,7 +1423,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) val |= CHV_CMN_USEDCLKCHANNEL; vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static void vlv_hdmi_post_disable(struct intel_encoder *encoder) @@ -1436,10 +1436,10 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder) int pipe = intel_crtc->pipe; /* Reset lanes to avoid HDMI flicker (VLV w/a) */ - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static void chv_hdmi_post_disable(struct intel_encoder *encoder) @@ -1453,7 +1453,7 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder) enum pipe pipe = intel_crtc->pipe; u32 val; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* Propagate soft reset to data lane reset */ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); @@ -1472,7 +1472,7 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder) val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } static void chv_hdmi_pre_enable(struct intel_encoder *encoder) @@ -1490,7 +1490,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) int data, i, stagger; u32 val; - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); /* allow hardware to manage TX FIFO reset source */ val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); @@ -1633,7 +1633,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) val |= DPIO_LRC_BYPASS; vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); intel_hdmi->set_infoframes(&encoder->base, intel_crtc->config->has_hdmi_sink, diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 148ebf5df811..c5914564939c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4964,9 +4964,9 @@ static void cherryview_init_gt_powersave(struct drm_device *dev) mutex_lock(&dev_priv->rps.hw_lock); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); val = vlv_cck_read(dev_priv, CCK_FUSE_REG); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); switch ((val >> 2) & 0x7) { case 0: diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index 693ce8281970..8831fc579ade 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -49,7 +49,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | (bar << IOSF_BAR_SHIFT); - WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); + WARN_ON(!mutex_is_locked(&dev_priv->sb_lock)); if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n", @@ -81,10 +81,10 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr) WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr, &val); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); return val; } @@ -93,10 +93,10 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val) { WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr, &val); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); } u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg) @@ -121,10 +121,10 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); - mutex_lock(&dev_priv->dpio_lock); + mutex_lock(&dev_priv->sb_lock); vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC, SB_CRRDDA_NP, addr, &val); - mutex_unlock(&dev_priv->dpio_lock); + mutex_unlock(&dev_priv->sb_lock); return val; } @@ -213,7 +213,7 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, enum intel_sbi_destination destination) { u32 value = 0; - WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); + WARN_ON(!mutex_is_locked(&dev_priv->sb_lock)); if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) { @@ -243,7 +243,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, { u32 tmp; - WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); + WARN_ON(!mutex_is_locked(&dev_priv->sb_lock)); if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) { -- cgit v1.2.3 From 54433e91a6d92c98f21233b58ffb3ebf053611a8 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 26 May 2015 20:42:31 +0300 Subject: drm/i915: Adjust sideband locking a bit for CHV/VLV MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit chv_enable_pll() doesn't need to hold sb_lock for the entire duration of the function. Drop the lock as soon as possible. valleyview_set_cdclk() does a potential lock+unlock+lock+unlock cycle with sb_lock. Grab the lock a few lines earlier so we can make do with a single lock+unlock cycle always. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 72b652940edd..067b1dee1b90 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1668,6 +1668,8 @@ static void chv_enable_pll(struct intel_crtc *crtc, tmp |= DPIO_DCLKP_EN; vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); + mutex_unlock(&dev_priv->sb_lock); + /* * Need to wait > 100ns between dclkp clock enable bit and PLL enable. */ @@ -1683,8 +1685,6 @@ static void chv_enable_pll(struct intel_crtc *crtc, /* not sure when this should be written */ I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); POSTING_READ(DPLL_MD(pipe)); - - mutex_unlock(&dev_priv->sb_lock); } static int intel_num_dvo_pipes(struct drm_device *dev) @@ -5780,12 +5780,13 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) } mutex_unlock(&dev_priv->rps.hw_lock); + mutex_lock(&dev_priv->sb_lock); + if (cdclk == 400000) { u32 divider; divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; - mutex_lock(&dev_priv->sb_lock); /* adjust cdclk divider */ val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); val &= ~DISPLAY_FREQUENCY_VALUES; @@ -5796,10 +5797,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), 50)) DRM_ERROR("timed out waiting for CDclk change\n"); - mutex_unlock(&dev_priv->sb_lock); } - mutex_lock(&dev_priv->sb_lock); /* adjust self-refresh exit latency value */ val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); val &= ~0x7f; @@ -5813,6 +5812,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) else val |= 3000 / 250; /* 3.0 usec */ vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); + mutex_unlock(&dev_priv->sb_lock); vlv_update_cdclk(dev); -- cgit v1.2.3 From 5e3daaca09f5158eff9c92290faa1d2001ecc6e4 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 28 May 2015 09:38:45 +0200 Subject: drm/i915: Disable 12bpc hdmi for now MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's totally broken, and since commit d328c9d78d64ca11e744fe227096990430a88477 Author: Daniel Vetter Date: Fri Apr 10 16:22:37 2015 +0200 drm/i915: Select starting pipe bpp irrespective or the primary plane the kernel will try to use it even for the common rgb888 framebuffers. Ville has patches to fix it all up properly, but unfortunately they're stuck in review limbo. And since the 4.2 feature cutoff has passed we need to somehow handle this regression. Cc: Ville Syrjälä Cc: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_hdmi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 4117092ab2e3..e97731aab6dc 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1036,7 +1036,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, */ if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && clock_12bpc <= portclock_limit && - hdmi_12bpc_possible(pipe_config)) { + hdmi_12bpc_possible(pipe_config) && + 0 /* FIXME 12bpc support totally broken */) { DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); desired_bpp = 12*3; -- cgit v1.2.3 From 4373f0f24ed52549d4d6a0d7e155301476ec0a36 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Mon, 25 May 2015 18:52:29 -0300 Subject: drm/i915: disable IPS while getting the sink CRCs This commit is the "sink CRC" version of: commit 8c740dcea254a1472df2c0ac5ac585412a2507ec Author: Paulo Zanoni Date: Fri Oct 17 18:42:03 2014 -0300 drm/i915: disable IPS while getting the pipe CRCs. For some unknown reason, when IPS gets enabled, the sink CRC changes. Since hsw_enable_ips() doesn't really guarantee to enable IPS (it depends on package C-states), we can't really predict if IPS is enabled or disabled while running our CRC tests, so let's just completely disable IPS while sink CRCs are being used. If we find a way to make IPS not change the pipe CRC result, we may want to fix IPS and then revert this patch (and 8c740dcea too). While this doesn't happen, let's merge this patch, so the IGT tests relying on sink CRCs can work properly. This was discovered while developing a new IGT test, which will probably be called kms_frontbuffer_tracking. Testcase: igt/kms_frontbuffer_tracking (not on upstream IGT yet) Cc: Rodrigo Vivi Signed-off-by: Paulo Zanoni Reviewed-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 66 ++++++++++++++++++++++++++++------------- 1 file changed, 45 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5b01f81aec48..280c282da9bd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4041,46 +4041,70 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) u8 buf; int test_crc_count; int attempts = 6; + int ret = 0; - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) - return -EIO; + hsw_disable_ips(intel_crtc); - if (!(buf & DP_TEST_CRC_SUPPORTED)) - return -ENOTTY; + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) { + ret = -EIO; + goto out; + } + + if (!(buf & DP_TEST_CRC_SUPPORTED)) { + ret = -ENOTTY; + goto out; + } - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) - return -EIO; + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { + ret = -EIO; + goto out; + } if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, - buf | DP_TEST_SINK_START) < 0) - return -EIO; + buf | DP_TEST_SINK_START) < 0) { + ret = -EIO; + goto out; + } + + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) { + ret = -EIO; + goto out; + } - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) - return -EIO; test_crc_count = buf & DP_TEST_COUNT_MASK; do { if (drm_dp_dpcd_readb(&intel_dp->aux, - DP_TEST_SINK_MISC, &buf) < 0) - return -EIO; + DP_TEST_SINK_MISC, &buf) < 0) { + ret = -EIO; + goto out; + } intel_wait_for_vblank(dev, intel_crtc->pipe); } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count); if (attempts == 0) { DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n"); - return -ETIMEDOUT; + ret = -ETIMEDOUT; + goto out; } - if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) - return -EIO; + if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { + ret = -EIO; + goto out; + } - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) - return -EIO; + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { + ret = -EIO; + goto out; + } if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, - buf & ~DP_TEST_SINK_START) < 0) - return -EIO; - - return 0; + buf & ~DP_TEST_SINK_START) < 0) { + ret = -EIO; + goto out; + } +out: + hsw_enable_ips(intel_crtc); + return ret; } static bool -- cgit v1.2.3 From 9e5acbc21380ca8bd470ec23c139dd4e245a221d Mon Sep 17 00:00:00 2001 From: Denys Vlasenko Date: Wed, 20 May 2015 13:02:37 +0200 Subject: radeon: Deinline indirect register accessor functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch deinlines indirect register accessor functions. These functions perform two mmio accesses, framed by spin lock/unlock. Spin lock/unlock by itself takes more than 50 cycles in ideal case (if lock is exclusively cached on current CPU). With this .config: http://busybox.net/~vda/kernel_config, after uninlining these functions have sizes and callsite counts as follows: r600_uvd_ctx_rreg: 111 bytes, 4 callsites r600_uvd_ctx_wreg: 113 bytes, 5 callsites eg_pif_phy0_rreg: 106 bytes, 13 callsites eg_pif_phy0_wreg: 108 bytes, 13 callsites eg_pif_phy1_rreg: 107 bytes, 13 callsites eg_pif_phy1_wreg: 108 bytes, 13 callsites rv370_pcie_rreg: 111 bytes, 21 callsites rv370_pcie_wreg: 113 bytes, 24 callsites r600_rcu_rreg: 111 bytes, 16 callsites r600_rcu_wreg: 113 bytes, 25 callsites cik_didt_rreg: 106 bytes, 10 callsites cik_didt_wreg: 107 bytes, 10 callsites tn_smc_rreg: 106 bytes, 126 callsites tn_smc_wreg: 107 bytes, 116 callsites eg_cg_rreg: 107 bytes, 20 callsites eg_cg_wreg: 108 bytes, 52 callsites Functions r100_mm_rreg() and r100_mm_rreg() have a fast path and a locked (slow) path. This patch deinlines only slow path. r100_mm_rreg_slow: 78 bytes, 2083 callsites r100_mm_wreg_slow: 81 bytes, 3570 callsites Reduction in code size is more than 65,000 bytes: text data bss dec hex filename 85740176 22294680 20627456 128662312 7ab3b28 vmlinux.before 85674192 22294776 20627456 128598664 7aa4288 vmlinux Signed-off-by: Denys Vlasenko Cc: Christian König Cc: Alex Deucher Cc: linux-kernel@vger.kernel.org Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cik.c | 25 +++++ drivers/gpu/drm/radeon/evergreen.c | 69 ++++++++++++ drivers/gpu/drm/radeon/ni.c | 25 +++++ drivers/gpu/drm/radeon/r100.c | 22 ++++ drivers/gpu/drm/radeon/r300.c | 25 +++++ drivers/gpu/drm/radeon/r600.c | 47 ++++++++ drivers/gpu/drm/radeon/radeon.h | 225 +++++-------------------------------- 7 files changed, 241 insertions(+), 197 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index a0c35bbc8546..d3a22f212948 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -174,6 +174,31 @@ int cik_get_allowed_info_register(struct radeon_device *rdev, } } +/* + * Indirect registers accessor + */ +u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&rdev->didt_idx_lock, flags); + WREG32(CIK_DIDT_IND_INDEX, (reg)); + r = RREG32(CIK_DIDT_IND_DATA); + spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); + return r; +} + +void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&rdev->didt_idx_lock, flags); + WREG32(CIK_DIDT_IND_INDEX, (reg)); + WREG32(CIK_DIDT_IND_DATA, (v)); + spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); +} + /* get temperature in millidegrees */ int ci_get_temp(struct radeon_device *rdev) { diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 05e6d6ef5963..5397bed26b86 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -35,6 +35,75 @@ #include "evergreen_blit_shaders.h" #include "radeon_ucode.h" +/* + * Indirect registers accessor + */ +u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&rdev->cg_idx_lock, flags); + WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); + r = RREG32(EVERGREEN_CG_IND_DATA); + spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); + return r; +} + +void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&rdev->cg_idx_lock, flags); + WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); + WREG32(EVERGREEN_CG_IND_DATA, (v)); + spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); +} + +u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&rdev->pif_idx_lock, flags); + WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); + r = RREG32(EVERGREEN_PIF_PHY0_DATA); + spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); + return r; +} + +void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&rdev->pif_idx_lock, flags); + WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); + WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); + spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); +} + +u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&rdev->pif_idx_lock, flags); + WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); + r = RREG32(EVERGREEN_PIF_PHY1_DATA); + spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); + return r; +} + +void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&rdev->pif_idx_lock, flags); + WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); + WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); + spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); +} + static const u32 crtc_offsets[6] = { EVERGREEN_CRTC0_REGISTER_OFFSET, diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 9269e188cd92..75977d7e177e 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -36,6 +36,31 @@ #include "radeon_ucode.h" #include "clearstate_cayman.h" +/* + * Indirect registers accessor + */ +u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&rdev->smc_idx_lock, flags); + WREG32(TN_SMC_IND_INDEX_0, (reg)); + r = RREG32(TN_SMC_IND_DATA_0); + spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); + return r; +} + +void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&rdev->smc_idx_lock, flags); + WREG32(TN_SMC_IND_INDEX_0, (reg)); + WREG32(TN_SMC_IND_DATA_0, (v)); + spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); +} + static const u32 tn_rlc_save_restore_register_list[] = { 0x98fc, diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 04f2514f7564..238b13f045c1 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -4090,6 +4090,28 @@ int r100_init(struct radeon_device *rdev) return 0; } +uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg) +{ + unsigned long flags; + uint32_t ret; + + spin_lock_irqsave(&rdev->mmio_idx_lock, flags); + writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); + ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); + spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); + return ret; +} + +void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v) +{ + unsigned long flags; + + spin_lock_irqsave(&rdev->mmio_idx_lock, flags); + writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); + writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); + spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); +} + u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) { if (reg < rdev->rio_mem_size) diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 08d68f3e13e9..718b12b03b57 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -49,6 +49,31 @@ * tell. (Jerome Glisse) */ +/* + * Indirect registers accessor + */ +uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) +{ + unsigned long flags; + uint32_t r; + + spin_lock_irqsave(&rdev->pcie_idx_lock, flags); + WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); + r = RREG32(RADEON_PCIE_DATA); + spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); + return r; +} + +void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) +{ + unsigned long flags; + + spin_lock_irqsave(&rdev->pcie_idx_lock, flags); + WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); + WREG32(RADEON_PCIE_DATA, (v)); + spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); +} + /* * rv370,rv380 PCIE GART */ diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 25b4ac967742..d0ff93256bb0 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -108,6 +108,53 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev); extern int evergreen_rlc_resume(struct radeon_device *rdev); extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev); +/* + * Indirect registers accessor + */ +u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&rdev->rcu_idx_lock, flags); + WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); + r = RREG32(R600_RCU_DATA); + spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); + return r; +} + +void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&rdev->rcu_idx_lock, flags); + WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); + WREG32(R600_RCU_DATA, (v)); + spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); +} + +u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&rdev->uvd_idx_lock, flags); + WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); + r = RREG32(R600_UVD_CTX_DATA); + spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); + return r; +} + +void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&rdev->uvd_idx_lock, flags); + WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); + WREG32(R600_UVD_CTX_DATA, (v)); + spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); +} + /** * r600_get_allowed_info_register - fetch the register for the info ioctl * diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 2ffca1d920d4..4d2d0579fd49 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -2474,38 +2474,24 @@ int radeon_gpu_wait_for_idle(struct radeon_device *rdev); #define RADEON_MIN_MMIO_SIZE 0x10000 +uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); +void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, bool always_indirect) { /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) return readl(((void __iomem *)rdev->rmmio) + reg); - else { - unsigned long flags; - uint32_t ret; - - spin_lock_irqsave(&rdev->mmio_idx_lock, flags); - writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); - ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); - spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); - - return ret; - } + else + return r100_mm_rreg_slow(rdev, reg); } - static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, bool always_indirect) { if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) writel(v, ((void __iomem *)rdev->rmmio) + reg); - else { - unsigned long flags; - - spin_lock_irqsave(&rdev->mmio_idx_lock, flags); - writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); - writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); - spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); - } + else + r100_mm_wreg_slow(rdev, reg, v); } u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); @@ -2596,184 +2582,29 @@ static inline struct radeon_fence *to_radeon_fence(struct fence *f) #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) /* - * Indirect registers accessor + * Indirect registers accessors. + * They used to be inlined, but this increases code size by ~65 kbytes. + * Since each performs a pair of MMIO ops + * within a spin_lock_irqsave/spin_unlock_irqrestore region, + * the cost of call+ret is almost negligible. MMIO and locking + * costs several dozens of cycles each at best, call+ret is ~5 cycles. */ -static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) -{ - unsigned long flags; - uint32_t r; - - spin_lock_irqsave(&rdev->pcie_idx_lock, flags); - WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); - r = RREG32(RADEON_PCIE_DATA); - spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); - return r; -} - -static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) -{ - unsigned long flags; - - spin_lock_irqsave(&rdev->pcie_idx_lock, flags); - WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); - WREG32(RADEON_PCIE_DATA, (v)); - spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); -} - -static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) -{ - unsigned long flags; - u32 r; - - spin_lock_irqsave(&rdev->smc_idx_lock, flags); - WREG32(TN_SMC_IND_INDEX_0, (reg)); - r = RREG32(TN_SMC_IND_DATA_0); - spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); - return r; -} - -static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) -{ - unsigned long flags; - - spin_lock_irqsave(&rdev->smc_idx_lock, flags); - WREG32(TN_SMC_IND_INDEX_0, (reg)); - WREG32(TN_SMC_IND_DATA_0, (v)); - spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); -} - -static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) -{ - unsigned long flags; - u32 r; - - spin_lock_irqsave(&rdev->rcu_idx_lock, flags); - WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); - r = RREG32(R600_RCU_DATA); - spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); - return r; -} - -static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) -{ - unsigned long flags; - - spin_lock_irqsave(&rdev->rcu_idx_lock, flags); - WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); - WREG32(R600_RCU_DATA, (v)); - spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); -} - -static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) -{ - unsigned long flags; - u32 r; - - spin_lock_irqsave(&rdev->cg_idx_lock, flags); - WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); - r = RREG32(EVERGREEN_CG_IND_DATA); - spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); - return r; -} - -static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) -{ - unsigned long flags; - - spin_lock_irqsave(&rdev->cg_idx_lock, flags); - WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); - WREG32(EVERGREEN_CG_IND_DATA, (v)); - spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); -} - -static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) -{ - unsigned long flags; - u32 r; - - spin_lock_irqsave(&rdev->pif_idx_lock, flags); - WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); - r = RREG32(EVERGREEN_PIF_PHY0_DATA); - spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); - return r; -} - -static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) -{ - unsigned long flags; - - spin_lock_irqsave(&rdev->pif_idx_lock, flags); - WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); - WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); - spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); -} - -static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) -{ - unsigned long flags; - u32 r; - - spin_lock_irqsave(&rdev->pif_idx_lock, flags); - WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); - r = RREG32(EVERGREEN_PIF_PHY1_DATA); - spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); - return r; -} - -static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) -{ - unsigned long flags; - - spin_lock_irqsave(&rdev->pif_idx_lock, flags); - WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); - WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); - spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); -} - -static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) -{ - unsigned long flags; - u32 r; - - spin_lock_irqsave(&rdev->uvd_idx_lock, flags); - WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); - r = RREG32(R600_UVD_CTX_DATA); - spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); - return r; -} - -static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) -{ - unsigned long flags; - - spin_lock_irqsave(&rdev->uvd_idx_lock, flags); - WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); - WREG32(R600_UVD_CTX_DATA, (v)); - spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); -} - - -static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) -{ - unsigned long flags; - u32 r; - - spin_lock_irqsave(&rdev->didt_idx_lock, flags); - WREG32(CIK_DIDT_IND_INDEX, (reg)); - r = RREG32(CIK_DIDT_IND_DATA); - spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); - return r; -} - -static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) -{ - unsigned long flags; - - spin_lock_irqsave(&rdev->didt_idx_lock, flags); - WREG32(CIK_DIDT_IND_INDEX, (reg)); - WREG32(CIK_DIDT_IND_DATA, (v)); - spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); -} +uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); +void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); +u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); +void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); +u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); +void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); +u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); +void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); +u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); +void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); +u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); +void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); +u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); +void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); +u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); +void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); void r100_pll_errata_after_index(struct radeon_device *rdev); -- cgit v1.2.3 From 2f15791c28af9b2114cf3422c48aba6701d91df3 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 28 May 2015 10:36:27 +0100 Subject: drm: clean up drm_mm debugfs output The drm_mm debugfs output is difficult to read as two different formats are used for the addresses: 0x00000080000000-0x0000008000b000: 45056: used 0x8000b000-0x80016000: 45056: free 0x00000080016000-0x0000008001b000: 20480: used 0x8001b000-0x817a1000: 24666112: free 0x000000817a1000-0x000000817a8000: 28672: used 0x000000817a8000-0x00000081ba8000: 4194304: used Fix this by using %#018llx for all addresses, thus making the output: 0x0000000080000000-0x000000008000b000: 45056: used 0x000000008000b000-0x0000000080016000: 45056: free 0x0000000080016000-0x000000008001b000: 20480: used 0x000000008001b000-0x00000000817a1000: 24666112: free 0x00000000817a1000-0x00000000817a8000: 28672: used 0x00000000817a8000-0x0000000081ba8000: 4194304: used Signed-off-by: Russell King Reviewed-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_mm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 1134526286c8..3427b115e2bb 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -825,7 +825,7 @@ static u64 drm_mm_dump_hole(struct seq_file *m, struct drm_mm_node *entry) hole_start = drm_mm_hole_node_start(entry); hole_end = drm_mm_hole_node_end(entry); hole_size = hole_end - hole_start; - seq_printf(m, "%#llx-%#llx: %llu: free\n", hole_start, + seq_printf(m, "%#018llx-%#018llx: %llu: free\n", hole_start, hole_end, hole_size); return hole_size; } @@ -846,7 +846,7 @@ int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm) total_free += drm_mm_dump_hole(m, &mm->head_node); drm_mm_for_each_node(entry, mm) { - seq_printf(m, "%#016llx-%#016llx: %llu: used\n", entry->start, + seq_printf(m, "%#018llx-%#018llx: %llu: used\n", entry->start, entry->start + entry->size, entry->size); total_used += entry->size; total_free += drm_mm_dump_hole(m, entry); -- cgit v1.2.3 From 2d847d45b2c988038194140fa3def4ac1342cb67 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Thu, 28 May 2015 10:21:16 -0700 Subject: drm/i915: Return the frontbuffer flip to enable intel_crtc_enable_planes. Without this frontbuffer flip when enabling planes PSR got compromised and wasn't being enabled waiting forever on the flush that never arrived. Another solution would to create a enable_cursor function and split this frontbuffer flip among the different plane enable and disable functions. But if necessary this can be done in a follow up work. For now let's just fix the regression. It was removed by: commit 87d4300a7dbc19634018e147b4753f3c9bb5f471 Author: Maarten Lankhorst Date: Tue Apr 21 17:12:54 2015 +0300 drm/i915: Move intel_(pre_disable/post_enable)_primary to intel_display.c, and use it there. Cc: Maarten Lankhorst Signed-off-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 067b1dee1b90..4e3f302d86f7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4828,11 +4828,22 @@ intel_pre_disable_primary(struct drm_crtc *crtc) static void intel_crtc_enable_planes(struct drm_crtc *crtc) { + struct drm_device *dev = crtc->dev; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + intel_enable_primary_hw_plane(crtc->primary, crtc); intel_enable_sprite_planes(crtc); intel_crtc_update_cursor(crtc, true); intel_post_enable_primary(crtc); + + /* + * FIXME: Once we grow proper nuclear flip support out of this we need + * to compute the mask of flip planes precisely. For the time being + * consider this a flip to a NULL plane. + */ + intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); } static void intel_crtc_disable_planes(struct drm_crtc *crtc) -- cgit v1.2.3 From d9a946b52350bb070fe70f92c3ddd13355c0ca08 Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Thu, 28 May 2015 10:26:58 -0700 Subject: drm/i915: Another fbdev hack to avoid PSR on fbcon. With unified modeset and flip paths introduced recently when switching to fbcon PSR was being disabled on fb_set_par path but re-enabled on fb_pan_display one, causing missed screen updates and un unusable console. Regression introduced with: commit bb54662350662815b4bfc2ff4464330a2dbd7041 Author: Ander Conselvan de Oliveira Date: Tue Apr 21 17:13:13 2015 +0300 drm/i915: Unify modeset and flip paths of intel_crtc_set_config() Cc: Ander Conselvan de Oliveira Signed-off-by: Rodrigo Vivi Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_fbdev.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index 4e7e7da2e03b..6372cfc7d053 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c +++ b/drivers/gpu/drm/i915/intel_fbdev.c @@ -96,6 +96,32 @@ static int intel_fbdev_blank(int blank, struct fb_info *info) return ret; } +static int intel_fbdev_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct intel_fbdev *ifbdev = + container_of(fb_helper, struct intel_fbdev, helper); + + int ret; + ret = drm_fb_helper_pan_display(var, info); + + if (ret == 0) { + /* + * FIXME: fbdev presumes that all callbacks also work from + * atomic contexts and relies on that for emergency oops + * printing. KMS totally doesn't do that and the locking here is + * by far not the only place this goes wrong. Ignore this for + * now until we solve this for real. + */ + mutex_lock(&fb_helper->dev->struct_mutex); + intel_fb_obj_invalidate(ifbdev->fb->obj, NULL, ORIGIN_GTT); + mutex_unlock(&fb_helper->dev->struct_mutex); + } + + return ret; +} + static struct fb_ops intelfb_ops = { .owner = THIS_MODULE, .fb_check_var = drm_fb_helper_check_var, @@ -103,7 +129,7 @@ static struct fb_ops intelfb_ops = { .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit, - .fb_pan_display = drm_fb_helper_pan_display, + .fb_pan_display = intel_fbdev_pan_display, .fb_blank = intel_fbdev_blank, .fb_setcmap = drm_fb_helper_setcmap, .fb_debug_enter = drm_fb_helper_debug_enter, -- cgit v1.2.3 From 501fd70fcaebc911b6b96a7b331e6960e5af67e7 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Fri, 29 May 2015 14:15:05 +0100 Subject: drm/i915: limit PPGTT size to 2GB in 32-bit platforms We already set this limit for the GGTT. This is a temporary patch until a full replacement of size_t variables (inadequate in 32-bit kernel) is in place. Regression from: commit a4e0bedca678c81eea4cd79a4bd502335639f73a Author: Michel Thierry Date: Wed Apr 8 12:13:35 2015 +0100 drm/i915: Use complete address space in true PPGTT v2: Prettify code and explain why this is needed. (Chris) v3: Don't hide the compilation warning in 32-bit. (Chris) Suggested-by: Daniel Vetter Cc: Mika Kuoppala Cc: Chris Wilson Signed-off-by: Michel Thierry Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 17b7df0b561f..619dad1b2386 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -952,6 +952,13 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) ppgtt->base.start = 0; ppgtt->base.total = 1ULL << 32; + if (IS_ENABLED(CONFIG_X86_32)) + /* While we have a proliferation of size_t variables + * we cannot represent the full ppgtt size on 32bit, + * so limit it to the same size as the GGTT (currently + * 2GiB). + */ + ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total; ppgtt->base.cleanup = gen8_ppgtt_cleanup; ppgtt->base.allocate_va_range = gen8_alloc_va_range; ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; -- cgit v1.2.3 From 1c34d824bd750f4a4287639fee8335ec51530024 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Fri, 15 May 2015 16:09:54 +0900 Subject: drm/ttm: dma: Don't crash on memory in the vmalloc range dma_alloc_coherent() can return memory in the vmalloc range. virt_to_page() cannot handle such addresses and crashes. This patch detects such cases and obtains the struct page * using vmalloc_to_page() instead. Signed-off-by: Alexandre Courbot Acked-by: Konrad Rzeszutek Wilk Signed-off-by: Dave Airlie --- drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c index 01e1d27eb078..3077f1554099 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c @@ -342,9 +342,12 @@ static struct dma_page *__ttm_dma_alloc_page(struct dma_pool *pool) d_page->vaddr = dma_alloc_coherent(pool->dev, pool->size, &d_page->dma, pool->gfp_flags); - if (d_page->vaddr) - d_page->p = virt_to_page(d_page->vaddr); - else { + if (d_page->vaddr) { + if (is_vmalloc_addr(d_page->vaddr)) + d_page->p = vmalloc_to_page(d_page->vaddr); + else + d_page->p = virt_to_page(d_page->vaddr); + } else { kfree(d_page); d_page = NULL; } -- cgit v1.2.3 From 06b718c01208d8f5fff9216c95d5b20984804df7 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 11 Nov 2014 09:17:00 +0100 Subject: break kconfig dependency loop After adding virtio-gpu I get this funky kconfig dependency loop. scripts/kconfig/conf --oldconfig Kconfig drivers/video/fbdev/Kconfig:5:error: recursive dependency detected! drivers/video/fbdev/Kconfig:5: symbol FB is selected by DRM_KMS_FB_HELPER drivers/gpu/drm/Kconfig:34: symbol DRM_KMS_FB_HELPER is selected by DRM_VIRTIO_GPU drivers/gpu/drm/virtio/Kconfig:1: symbol DRM_VIRTIO_GPU depends on VIRTIO drivers/virtio/Kconfig:1: symbol VIRTIO is selected by REMOTEPROC drivers/remoteproc/Kconfig:4: symbol REMOTEPROC is selected by OMAP_REMOTEPROC drivers/remoteproc/Kconfig:12: symbol OMAP_REMOTEPROC depends on OMAP_IOMMU drivers/iommu/Kconfig:141: symbol OMAP_IOMMU is selected by VIDEO_OMAP3 drivers/media/platform/Kconfig:96: symbol VIDEO_OMAP3 depends on VIDEO_V4L2 drivers/media/v4l2-core/Kconfig:6: symbol VIDEO_V4L2 depends on I2C drivers/i2c/Kconfig:7: symbol I2C is selected by FB_DDC drivers/video/fbdev/Kconfig:59: symbol FB_DDC is selected by FB_CYBER2000_DDC drivers/video/fbdev/Kconfig:374: symbol FB_CYBER2000_DDC depends on FB_CYBER2000 drivers/video/fbdev/Kconfig:362: symbol FB_CYBER2000 depends on FB Making VIDEO_OMAP3 depend on OMAP_IOMMU instead of selecting it breaks the loop, which looks like the best way to handle it to me. Updated OMAP_IOMMU help text accordingly. Signed-off-by: Gerd Hoffmann Acked-by: Mauro Carvalho Chehab --- drivers/iommu/Kconfig | 3 +++ drivers/media/platform/Kconfig | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 1ae4e547b419..a5c8d5e62871 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -178,6 +178,9 @@ config OMAP_IOMMU depends on ARM && MMU depends on ARCH_OMAP2PLUS || COMPILE_TEST select IOMMU_API + ---help--- + The OMAP3 media platform drivers depend on iommu support, + if you need them say Y here. config OMAP_IOMMU_DEBUG bool "Export OMAP IOMMU internals in DebugFS" diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 421f53188c6c..19306f7229c0 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -87,8 +87,8 @@ config VIDEO_OMAP3 tristate "OMAP 3 Camera support" depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API && ARCH_OMAP3 depends on HAS_DMA + depends on OMAP_IOMMU select ARM_DMA_USE_IOMMU - select OMAP_IOMMU select VIDEOBUF2_DMA_CONTIG select MFD_SYSCON ---help--- -- cgit v1.2.3 From 16e3247da7f71f8c31f4330f739f6192a00c8b51 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 30 Mar 2015 12:50:50 +0200 Subject: drm_vblank_get: don't WARN_ON in case vblanks are not initialized Signed-off-by: Gerd Hoffmann Reviewed-by: Alex Deucher --- drivers/gpu/drm/drm_irq.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index 1967e7fc9805..dd3fd1259950 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -1056,6 +1056,9 @@ int drm_vblank_get(struct drm_device *dev, int crtc) unsigned long irqflags; int ret = 0; + if (!dev->num_crtcs) + return -EINVAL; + if (WARN_ON(crtc >= dev->num_crtcs)) return -EINVAL; -- cgit v1.2.3 From f761d8bd80e648979a3d189089576bda4a59d6c4 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Tue, 19 May 2015 18:37:51 -0700 Subject: drm/amdkfd: Use DECLARE_BITMAP Use the generic mechanism to declare a bitmap instead of unsigned long. It seems that "struct kfd_process.allocated_queue_bitmap" is unused. Maybe it could be deleted instead. Signed-off-by: Joe Perches Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index b6f838f56589..816c7a1f3294 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -167,8 +167,8 @@ struct kfd_dev { const struct kfd2kgd_calls *kfd2kgd; struct mutex doorbell_mutex; - unsigned long doorbell_available_index[DIV_ROUND_UP( - KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, BITS_PER_LONG)]; + DECLARE_BITMAP(doorbell_available_index, + KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); void *gtt_mem; uint64_t gtt_start_gpu_addr; @@ -503,8 +503,6 @@ struct kfd_process { /* Size is queue_array_size, up to MAX_PROCESS_QUEUES. */ struct kfd_queue **queues; - unsigned long allocated_queue_bitmap[DIV_ROUND_UP(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, BITS_PER_LONG)]; - /*Is the user space process 32 bit?*/ bool is_32bit_user_mode; -- cgit v1.2.3 From a6186f4d6f5d4755a38f57005160a30acda8e081 Mon Sep 17 00:00:00 2001 From: Yair Shachar Date: Sun, 28 Sep 2014 11:51:15 +0300 Subject: drm/radeon: Add H/W debugger kfd->kgd functions This patch adds new interface functions to the kfd2kgd interface file. The new functions allow to perform H/W debugger operations by writing to GPU registers. Signed-off-by: Yair Shachar Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 13 +++ drivers/gpu/drm/radeon/cik_reg.h | 56 +++++++++++- drivers/gpu/drm/radeon/radeon_kfd.c | 113 ++++++++++++++++++++++++ 3 files changed, 181 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 4ea21ae88b07..afde1b75eeee 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -163,6 +163,19 @@ struct kfd2kgd_calls { int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd, unsigned int timeout); + int (*address_watch_disable)(struct kgd_dev *kgd); + int (*address_watch_execute)(struct kgd_dev *kgd, + unsigned int watch_point_id, + uint32_t cntl_val, + uint32_t addr_hi, + uint32_t addr_lo); + int (*wave_control_execute)(struct kgd_dev *kgd, + uint32_t gfx_index_val, + uint32_t sq_cmd); + uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd, + unsigned int watch_point_id, + unsigned int reg_offset); + uint16_t (*get_fw_version)(struct kgd_dev *kgd, enum kgd_engine_type type); }; diff --git a/drivers/gpu/drm/radeon/cik_reg.h b/drivers/gpu/drm/radeon/cik_reg.h index 0ec5d53eb6fb..4e883fdc59d8 100644 --- a/drivers/gpu/drm/radeon/cik_reg.h +++ b/drivers/gpu/drm/radeon/cik_reg.h @@ -149,10 +149,30 @@ #define KFD_CIK_SDMA_QUEUE_OFFSET 0x200 +#define SQ_IND_INDEX 0x8DE0 +#define SQ_CMD 0x8DEC +#define SQ_IND_DATA 0x8DE4 + +/* + * The TCP_WATCHx_xxxx addresses that are shown here are in dwords, + * and that's why they are multiplied by 4 + */ +#define TCP_WATCH0_ADDR_H (0x32A0*4) +#define TCP_WATCH1_ADDR_H (0x32A3*4) +#define TCP_WATCH2_ADDR_H (0x32A6*4) +#define TCP_WATCH3_ADDR_H (0x32A9*4) +#define TCP_WATCH0_ADDR_L (0x32A1*4) +#define TCP_WATCH1_ADDR_L (0x32A4*4) +#define TCP_WATCH2_ADDR_L (0x32A7*4) +#define TCP_WATCH3_ADDR_L (0x32AA*4) +#define TCP_WATCH0_CNTL (0x32A2*4) +#define TCP_WATCH1_CNTL (0x32A5*4) +#define TCP_WATCH2_CNTL (0x32A8*4) +#define TCP_WATCH3_CNTL (0x32AB*4) + #define CPC_INT_CNTL 0xC2D0 #define CP_HQD_IQ_RPTR 0xC970u -#define AQL_ENABLE (1U << 0) #define SDMA0_RLC0_RB_CNTL 0xD400u #define SDMA_RB_VMID(x) (x << 24) #define SDMA0_RLC0_RB_BASE 0xD404u @@ -186,4 +206,38 @@ #define SDMA0_CNTL 0xD010 #define SDMA1_CNTL 0xD810 +enum { + MAX_TRAPID = 8, /* 3 bits in the bitfield. */ + MAX_WATCH_ADDRESSES = 4 +}; + +enum { + ADDRESS_WATCH_REG_ADDR_HI = 0, + ADDRESS_WATCH_REG_ADDR_LO, + ADDRESS_WATCH_REG_CNTL, + ADDRESS_WATCH_REG_MAX +}; + +enum { /* not defined in the CI/KV reg file */ + ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL, + ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF, + ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000, + /* extend the mask to 26 bits in order to match the low address field */ + ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6, + ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF +}; + +union TCP_WATCH_CNTL_BITS { + struct { + uint32_t mask:24; + uint32_t vmid:4; + uint32_t atc:1; + uint32_t mode:2; + uint32_t valid:1; + } bitfields, bits; + uint32_t u32All; + signed int i32All; + float f32All; +}; + #endif diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c index 813a416db538..fd9590de2605 100644 --- a/drivers/gpu/drm/radeon/radeon_kfd.c +++ b/drivers/gpu/drm/radeon/radeon_kfd.c @@ -34,6 +34,13 @@ #define CIK_PIPE_PER_MEC (4) +static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = { + TCP_WATCH0_ADDR_H, TCP_WATCH0_ADDR_L, TCP_WATCH0_CNTL, + TCP_WATCH1_ADDR_H, TCP_WATCH1_ADDR_L, TCP_WATCH1_CNTL, + TCP_WATCH2_ADDR_H, TCP_WATCH2_ADDR_L, TCP_WATCH2_CNTL, + TCP_WATCH3_ADDR_H, TCP_WATCH3_ADDR_L, TCP_WATCH3_CNTL +}; + struct kgd_mem { struct radeon_bo *bo; uint64_t gpu_addr; @@ -79,6 +86,18 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, unsigned int timeout); +static int kgd_address_watch_disable(struct kgd_dev *kgd); +static int kgd_address_watch_execute(struct kgd_dev *kgd, + unsigned int watch_point_id, + uint32_t cntl_val, + uint32_t addr_hi, + uint32_t addr_lo); +static int kgd_wave_control_execute(struct kgd_dev *kgd, + uint32_t gfx_index_val, + uint32_t sq_cmd); +static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, + unsigned int watch_point_id, + unsigned int reg_offset); static const struct kfd2kgd_calls kfd2kgd = { .init_gtt_mem_allocation = alloc_gtt_mem, @@ -96,6 +115,10 @@ static const struct kfd2kgd_calls kfd2kgd = { .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, .hqd_destroy = kgd_hqd_destroy, .hqd_sdma_destroy = kgd_hqd_sdma_destroy, + .address_watch_disable = kgd_address_watch_disable, + .address_watch_execute = kgd_address_watch_execute, + .wave_control_execute = kgd_wave_control_execute, + .address_watch_get_offset = kgd_address_watch_get_offset, .get_fw_version = get_fw_version }; @@ -665,6 +688,96 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, return 0; } +static int kgd_address_watch_disable(struct kgd_dev *kgd) +{ + union TCP_WATCH_CNTL_BITS cntl; + unsigned int i; + + cntl.u32All = 0; + + cntl.bitfields.valid = 0; + cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; + cntl.bitfields.atc = 1; + + /* Turning off this address until we set all the registers */ + for (i = 0; i < MAX_WATCH_ADDRESSES; i++) + write_register(kgd, + watchRegs[i * ADDRESS_WATCH_REG_MAX + + ADDRESS_WATCH_REG_CNTL], + cntl.u32All); + + return 0; +} + +static int kgd_address_watch_execute(struct kgd_dev *kgd, + unsigned int watch_point_id, + uint32_t cntl_val, + uint32_t addr_hi, + uint32_t addr_lo) +{ + union TCP_WATCH_CNTL_BITS cntl; + + cntl.u32All = cntl_val; + + /* Turning off this watch point until we set all the registers */ + cntl.bitfields.valid = 0; + write_register(kgd, + watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + + ADDRESS_WATCH_REG_CNTL], + cntl.u32All); + + write_register(kgd, + watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + + ADDRESS_WATCH_REG_ADDR_HI], + addr_hi); + + write_register(kgd, + watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + + ADDRESS_WATCH_REG_ADDR_LO], + addr_lo); + + /* Enable the watch point */ + cntl.bitfields.valid = 1; + + write_register(kgd, + watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + + ADDRESS_WATCH_REG_CNTL], + cntl.u32All); + + return 0; +} + +static int kgd_wave_control_execute(struct kgd_dev *kgd, + uint32_t gfx_index_val, + uint32_t sq_cmd) +{ + struct radeon_device *rdev = get_radeon_device(kgd); + uint32_t data; + + mutex_lock(&rdev->grbm_idx_mutex); + + write_register(kgd, GRBM_GFX_INDEX, gfx_index_val); + write_register(kgd, SQ_CMD, sq_cmd); + + /* Restore the GRBM_GFX_INDEX register */ + + data = INSTANCE_BROADCAST_WRITES | SH_BROADCAST_WRITES | + SE_BROADCAST_WRITES; + + write_register(kgd, GRBM_GFX_INDEX, data); + + mutex_unlock(&rdev->grbm_idx_mutex); + + return 0; +} + +static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, + unsigned int watch_point_id, + unsigned int reg_offset) +{ + return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset]; +} + static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) { struct radeon_device *rdev = (struct radeon_device *) kgd; -- cgit v1.2.3 From aef11009c45ca594c18ecc822f101e3908ca3fb4 Mon Sep 17 00:00:00 2001 From: Yair Shachar Date: Sun, 7 Dec 2014 17:05:22 +0200 Subject: drm/amdkfd: add H/W debugger IOCTL set definitions This patch adds four new IOCTLs to amdkfd. These IOCTLs expose a H/W debugger functionality to the userspace. The IOCTLs are: - AMDKFD_IOC_DBG_REGISTER: The purpose of this IOCTL is to notify amdkfd that a process wants to use GPU debugging facilities on itself only. It is expected that this IOCTL would be called before any other H/W debugger requests are sent to amdkfd and for each GPU where the H/W debugging needs to be enabled. The use of this IOCTL ensures that only one instance of a debugger is active in the system. - AMDKFD_IOC_DBG_UNREGISTER: This IOCTL detaches the debugger/debugged process from the H/W Debug which was established by the AMDKFD_IOC_DBG_REGISTER IOCTL. - AMDKFD_IOC_DBG_ADDRESS_WATCH: This IOCTL allows to set different watchpoints with various conditions as indicated by the IOCTL's arguments. The available number of watchpoints is retrieved from topology. This operation is confined to the current debugged process, which was registered through AMDKFD_IOC_DBG_REGISTER. - AMDKFD_IOC_DBG_WAVE_CONTROL: This IOCTL allows to control a wavefront as indicated by the IOCTL's arguments. For example, you can halt/resume or kill either a single wavefront or a set of wavefronts. This operation is confined to the current debugged process, which was registered through AMDKFD_IOC_DBG_REGISTER. Because the arguments for the address watch IOCTL and wave control IOCTL are dynamic, meaning that they could vary in size, the userspace passes a pointer to a structure (in userspace) that contains the value of the arguments. The kernel driver is responsible to parse this structure and validate its contents. v2: change void* to uint64_t inside ioctl arguments Signed-off-by: Yair Shachar Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 54 ++++++++++++++++++++++++++++++++ include/uapi/linux/kfd_ioctl.h | 43 +++++++++++++++++++++++-- 2 files changed, 95 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index b2c6109bd7af..b358e910378f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -432,6 +432,48 @@ out: return err; } +static int kfd_ioctl_dbg_register(struct file *filep, + struct kfd_process *p, void *data) +{ + long status = -EFAULT; + + return status; +} + +static int kfd_ioctl_dbg_unrgesiter(struct file *filep, + struct kfd_process *p, void *data) +{ + long status = -EFAULT; + + return status; +} + +/* + * Parse and generate variable size data structure for address watch. + * Total size of the buffer and # watch points is limited in order + * to prevent kernel abuse. (no bearing to the much smaller HW limitation + * which is enforced by dbgdev module) + * please also note that the watch address itself are not "copied from user", + * since it be set into the HW in user mode values. + * + */ +static int kfd_ioctl_dbg_address_watch(struct file *filep, + struct kfd_process *p, void *data) +{ + long status = -EFAULT; + + return status; +} + +/* Parse and generate fixed size data structure for wave control */ +static int kfd_ioctl_dbg_wave_control(struct file *filep, + struct kfd_process *p, void *data) +{ + long status = -EFAULT; + + return status; +} + static int kfd_ioctl_get_clock_counters(struct file *filep, struct kfd_process *p, void *data) { @@ -612,6 +654,18 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS, kfd_ioctl_wait_events, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER, + kfd_ioctl_dbg_register, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER, + kfd_ioctl_dbg_unrgesiter, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH, + kfd_ioctl_dbg_address_watch, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL, + kfd_ioctl_dbg_wave_control, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 4ca35a8f9891..d6833426fdef 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -128,6 +128,32 @@ struct kfd_ioctl_get_process_apertures_args { uint32_t pad; }; +#define MAX_ALLOWED_NUM_POINTS 100 +#define MAX_ALLOWED_AW_BUFF_SIZE 4096 +#define MAX_ALLOWED_WAC_BUFF_SIZE 128 + +struct kfd_ioctl_dbg_register_args { + uint32_t gpu_id; /* to KFD */ + uint32_t pad; +}; + +struct kfd_ioctl_dbg_unregister_args { + uint32_t gpu_id; /* to KFD */ + uint32_t pad; +}; + +struct kfd_ioctl_dbg_address_watch_args { + uint64_t content_ptr; /* a pointer to the actual content */ + uint32_t gpu_id; /* to KFD */ + uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */ +}; + +struct kfd_ioctl_dbg_wave_control_args { + uint64_t content_ptr; /* a pointer to the actual content */ + uint32_t gpu_id; /* to KFD */ + uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */ +}; + /* Matching HSA_EVENTTYPE */ #define KFD_IOC_EVENT_SIGNAL 0 #define KFD_IOC_EVENT_NODECHANGE 1 @@ -198,7 +224,8 @@ struct kfd_event_data { }; struct kfd_ioctl_wait_events_args { - uint64_t events_ptr; /* to KFD */ + uint64_t events_ptr; /* pointed to struct + kfd_event_data array, to KFD */ uint32_t num_events; /* to KFD */ uint32_t wait_for_all; /* to KFD */ uint32_t timeout; /* to KFD */ @@ -247,7 +274,19 @@ struct kfd_ioctl_wait_events_args { #define AMDKFD_IOC_WAIT_EVENTS \ AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) +#define AMDKFD_IOC_DBG_REGISTER \ + AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) + +#define AMDKFD_IOC_DBG_UNREGISTER \ + AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) + +#define AMDKFD_IOC_DBG_ADDRESS_WATCH \ + AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) + +#define AMDKFD_IOC_DBG_WAVE_CONTROL \ + AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) + #define AMDKFD_COMMAND_START 0x01 -#define AMDKFD_COMMAND_END 0x0D +#define AMDKFD_COMMAND_END 0x11 #endif -- cgit v1.2.3 From 992839ad64f21ff4e5ed0a71691098ab7cfcb9dc Mon Sep 17 00:00:00 2001 From: Yair Shachar Date: Wed, 20 May 2015 13:43:04 +0300 Subject: drm/amdkfd: Add static user-mode queues support This patch adds support for static user-mode queues in QCM. Queues which are designated as static can NOT be preempted by the CP microcode when it is executing its scheduling algorithm. This is needed for supporting the debugger feature, because we can't allow the CP to preempt queues which are currently being debugged. The number of queues that can be designated as static is limited by the number of HQDs (Hardware Queue Descriptors). Signed-off-by: Yair Shachar Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 + .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 38 ++++++++++++++---- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 6 +++ drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 46 +++++++++++++++++----- drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h | 6 ++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 + .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 16 ++++++++ 7 files changed, 97 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 52cab0f53ebc..f1f86db27f73 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -33,6 +33,8 @@ static const struct kfd_device_info kaveri_device_info = { .asic_family = CHIP_KAVERI, .max_pasid_bits = 16, + /* max num of queues for KV.TODO should be a dynamic value */ + .max_no_of_hqd = 24, .ih_ring_entry_size = 4 * sizeof(uint32_t), .event_interrupt_class = &event_interrupt_class_cik, .mqd_size_aligned = MQD_SIZE_ALIGNED diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 4e215bd4d41f..a5dc8228b6b1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -45,7 +45,8 @@ static int create_compute_queue_nocpsch(struct device_queue_manager *dqm, struct qcm_process_device *qpd); static int execute_queues_cpsch(struct device_queue_manager *dqm, bool lock); -static int destroy_queues_cpsch(struct device_queue_manager *dqm, bool lock); +static int destroy_queues_cpsch(struct device_queue_manager *dqm, + bool preempt_static_queues, bool lock); static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm, struct queue *q, @@ -775,7 +776,7 @@ static int stop_cpsch(struct device_queue_manager *dqm) BUG_ON(!dqm); - destroy_queues_cpsch(dqm, true); + destroy_queues_cpsch(dqm, true, true); list_for_each_entry(node, &dqm->queues, list) { pdd = qpd_to_pdd(node->qpd); @@ -829,7 +830,8 @@ static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, pr_debug("kfd: In %s\n", __func__); mutex_lock(&dqm->lock); - destroy_queues_cpsch(dqm, false); + /* here we actually preempt the DIQ */ + destroy_queues_cpsch(dqm, true, false); list_del(&kq->list); dqm->queue_count--; qpd->is_debug = false; @@ -935,13 +937,15 @@ static int destroy_sdma_queues(struct device_queue_manager *dqm, unsigned int sdma_engine) { return pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA, - KFD_PREEMPT_TYPE_FILTER_ALL_QUEUES, 0, false, + KFD_PREEMPT_TYPE_FILTER_DYNAMIC_QUEUES, 0, false, sdma_engine); } -static int destroy_queues_cpsch(struct device_queue_manager *dqm, bool lock) +static int destroy_queues_cpsch(struct device_queue_manager *dqm, + bool preempt_static_queues, bool lock) { int retval; + enum kfd_preempt_type_filter preempt_type; BUG_ON(!dqm); @@ -960,8 +964,12 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, bool lock) destroy_sdma_queues(dqm, 1); } + preempt_type = preempt_static_queues ? + KFD_PREEMPT_TYPE_FILTER_ALL_QUEUES : + KFD_PREEMPT_TYPE_FILTER_DYNAMIC_QUEUES; + retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE, - KFD_PREEMPT_TYPE_FILTER_ALL_QUEUES, 0, false, 0); + preempt_type, 0, false, 0); if (retval != 0) goto out; @@ -989,7 +997,7 @@ static int execute_queues_cpsch(struct device_queue_manager *dqm, bool lock) if (lock) mutex_lock(&dqm->lock); - retval = destroy_queues_cpsch(dqm, false); + retval = destroy_queues_cpsch(dqm, false, false); if (retval != 0) { pr_err("kfd: the cp might be in an unrecoverable state due to an unsuccessful queues preemption"); goto out; @@ -1024,13 +1032,27 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, { int retval; struct mqd_manager *mqd; + bool preempt_all_queues; BUG_ON(!dqm || !qpd || !q); + preempt_all_queues = false; + retval = 0; /* remove queue from list to prevent rescheduling after preemption */ mutex_lock(&dqm->lock); + + if (qpd->is_debug) { + /* + * error, currently we do not allow to destroy a queue + * of a currently debugged process + */ + retval = -EBUSY; + goto failed_try_destroy_debugged_queue; + + } + mqd = dqm->ops.get_mqd_manager(dqm, get_mqd_type_from_queue_type(q->properties.type)); if (!mqd) { @@ -1062,6 +1084,8 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, return 0; failed: +failed_try_destroy_debugged_queue: + mutex_unlock(&dqm->lock); return retval; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 57278e2d72e0..ec4036a09f3e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -88,9 +88,11 @@ struct device_queue_manager_ops { struct queue *q, struct qcm_process_device *qpd, int *allocate_vmid); + int (*destroy_queue)(struct device_queue_manager *dqm, struct qcm_process_device *qpd, struct queue *q); + int (*update_queue)(struct device_queue_manager *dqm, struct queue *q); @@ -100,8 +102,10 @@ struct device_queue_manager_ops { int (*register_process)(struct device_queue_manager *dqm, struct qcm_process_device *qpd); + int (*unregister_process)(struct device_queue_manager *dqm, struct qcm_process_device *qpd); + int (*initialize)(struct device_queue_manager *dqm); int (*start)(struct device_queue_manager *dqm); int (*stop)(struct device_queue_manager *dqm); @@ -109,9 +113,11 @@ struct device_queue_manager_ops { int (*create_kernel_queue)(struct device_queue_manager *dqm, struct kernel_queue *kq, struct qcm_process_device *qpd); + void (*destroy_kernel_queue)(struct device_queue_manager *dqm, struct kernel_queue *kq, struct qcm_process_device *qpd); + bool (*set_cache_memory_policy)(struct device_queue_manager *dqm, struct qcm_process_device *qpd, enum cache_policy default_policy, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index e2533d875f43..99b6d28a11c3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -163,7 +163,7 @@ static int pm_create_map_process(struct packet_manager *pm, uint32_t *buffer, num_queues = 0; list_for_each_entry(cur, &qpd->queues_list, list) num_queues++; - packet->bitfields10.num_queues = num_queues; + packet->bitfields10.num_queues = (qpd->is_debug) ? 0 : num_queues; packet->sh_mem_config = qpd->sh_mem_config; packet->sh_mem_bases = qpd->sh_mem_bases; @@ -177,9 +177,10 @@ static int pm_create_map_process(struct packet_manager *pm, uint32_t *buffer, } static int pm_create_map_queue(struct packet_manager *pm, uint32_t *buffer, - struct queue *q) + struct queue *q, bool is_static) { struct pm4_map_queues *packet; + bool use_static = is_static; BUG_ON(!pm || !buffer || !q); @@ -209,6 +210,7 @@ static int pm_create_map_queue(struct packet_manager *pm, uint32_t *buffer, case KFD_QUEUE_TYPE_SDMA: packet->bitfields2.engine_sel = engine_sel__mes_map_queues__sdma0; + use_static = false; /* no static queues under SDMA */ break; default: BUG(); @@ -218,6 +220,9 @@ static int pm_create_map_queue(struct packet_manager *pm, uint32_t *buffer, packet->mes_map_queues_ordinals[0].bitfields3.doorbell_offset = q->properties.doorbell_off; + packet->mes_map_queues_ordinals[0].bitfields3.is_static = + (use_static == true) ? 1 : 0; + packet->mes_map_queues_ordinals[0].mqd_addr_lo = lower_32_bits(q->gart_mqd_addr); @@ -271,9 +276,11 @@ static int pm_create_runlist_ib(struct packet_manager *pm, pm_release_ib(pm); return -ENOMEM; } + retval = pm_create_map_process(pm, &rl_buffer[rl_wptr], qpd); if (retval != 0) return retval; + proccesses_mapped++; inc_wptr(&rl_wptr, sizeof(struct pm4_map_process), alloc_size_bytes); @@ -281,23 +288,36 @@ static int pm_create_runlist_ib(struct packet_manager *pm, list_for_each_entry(kq, &qpd->priv_queue_list, list) { if (kq->queue->properties.is_active != true) continue; + + pr_debug("kfd: static_queue, mapping kernel q %d, is debug status %d\n", + kq->queue->queue, qpd->is_debug); + retval = pm_create_map_queue(pm, &rl_buffer[rl_wptr], - kq->queue); + kq->queue, qpd->is_debug); if (retval != 0) return retval; - inc_wptr(&rl_wptr, sizeof(struct pm4_map_queues), - alloc_size_bytes); + + inc_wptr(&rl_wptr, + sizeof(struct pm4_map_queues), + alloc_size_bytes); } list_for_each_entry(q, &qpd->queues_list, list) { if (q->properties.is_active != true) continue; - retval = pm_create_map_queue(pm, - &rl_buffer[rl_wptr], q); + + pr_debug("kfd: static_queue, mapping user queue %d, is debug status %d\n", + q->queue, qpd->is_debug); + + retval = pm_create_map_queue(pm, &rl_buffer[rl_wptr], + q, qpd->is_debug); + if (retval != 0) return retval; - inc_wptr(&rl_wptr, sizeof(struct pm4_map_queues), - alloc_size_bytes); + + inc_wptr(&rl_wptr, + sizeof(struct pm4_map_queues), + alloc_size_bytes); } } @@ -488,7 +508,8 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, packet = (struct pm4_unmap_queues *)buffer; memset(buffer, 0, sizeof(struct pm4_unmap_queues)); - + pr_debug("kfd: static_queue: unmapping queues: mode is %d , reset is %d , type is %d\n", + mode, reset, type); packet->header.u32all = build_pm4_header(IT_UNMAP_QUEUES, sizeof(struct pm4_unmap_queues)); switch (type) { @@ -529,6 +550,11 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, packet->bitfields2.queue_sel = queue_sel__mes_unmap_queues__perform_request_on_all_active_queues; break; + case KFD_PREEMPT_TYPE_FILTER_DYNAMIC_QUEUES: + /* in this case, we do not preempt static queues */ + packet->bitfields2.queue_sel = + queue_sel__mes_unmap_queues__perform_request_on_dynamic_queues_only; + break; default: BUG(); break; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h index 071ad5724bd2..5b393f3e34a9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h @@ -237,7 +237,8 @@ struct pm4_map_queues { struct { union { struct { - uint32_t reserved5:2; + uint32_t is_static:1; + uint32_t reserved5:1; uint32_t doorbell_offset:21; uint32_t reserved6:3; uint32_t queue:6; @@ -328,7 +329,8 @@ enum unmap_queues_action_enum { enum unmap_queues_queue_sel_enum { queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, - queue_sel__mes_unmap_queues__perform_request_on_all_active_queues = 2 + queue_sel__mes_unmap_queues__perform_request_on_all_active_queues = 2, + queue_sel__mes_unmap_queues__perform_request_on_dynamic_queues_only = 3 }; enum unmap_queues_engine_sel_enum { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 816c7a1f3294..eda7281c4a07 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -128,6 +128,7 @@ struct kfd_device_info { unsigned int asic_family; const struct kfd_event_interrupt_class *event_interrupt_class; unsigned int max_pasid_bits; + unsigned int max_no_of_hqd; size_t ih_ring_entry_size; uint8_t num_of_watch_points; uint16_t mqd_size_aligned; @@ -231,6 +232,7 @@ struct device *kfd_chardev(void); enum kfd_preempt_type_filter { KFD_PREEMPT_TYPE_FILTER_SINGLE_QUEUE, KFD_PREEMPT_TYPE_FILTER_ALL_QUEUES, + KFD_PREEMPT_TYPE_FILTER_DYNAMIC_QUEUES, KFD_PREEMPT_TYPE_FILTER_BY_PASID }; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 530b82c4e78b..85b7fecd1c5d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -158,6 +158,8 @@ int pqm_create_queue(struct process_queue_manager *pqm, struct queue *q; struct process_queue_node *pqn; struct kernel_queue *kq; + int num_queues = 0; + struct queue *cur; BUG_ON(!pqm || !dev || !properties || !qid); @@ -172,6 +174,20 @@ int pqm_create_queue(struct process_queue_manager *pqm, return -1; } + /* + * for debug process, verify that it is within the static queues limit + * currently limit is set to half of the total avail HQD slots + * If we are just about to create DIQ, the is_debug flag is not set yet + * Hence we also check the type as well + */ + if ((pdd->qpd.is_debug) || + (type == KFD_QUEUE_TYPE_DIQ)) { + list_for_each_entry(cur, &pdd->qpd.queues_list, list) + num_queues++; + if (num_queues >= dev->device_info->max_no_of_hqd/2) + return (-ENOSPC); + } + retval = find_available_queue_slot(pqm, qid); if (retval != 0) return retval; -- cgit v1.2.3 From fbeb661bfa895dc14ea1f093edc5e6e80f1b6a95 Mon Sep 17 00:00:00 2001 From: Yair Shachar Date: Wed, 20 May 2015 13:48:26 +0300 Subject: drm/amdkfd: Add skeleton H/W debugger module support This patch adds the skeleton H/W debugger module support. This code enables registration and unregistration of a single HSA process at a time. The module saves the process's pasid and use it to verify that only the registered process is allowed to execute debugger operations through the kernel driver. v2: rename get_dbgmgr_mutex to kfd_get_dbgmgr_mutex to namespace it Signed-off-by: Yair Shachar Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/Makefile | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c | 142 ++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h | 193 ++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c | 135 ++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h | 287 ++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 + drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h | 290 +++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 + .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +- 9 files changed, 1058 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 652d25478fd5..28551153ec6d 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -12,6 +12,7 @@ amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \ kfd_kernel_queue_vi.o kfd_packet_manager.o \ kfd_process_queue_manager.o kfd_device_queue_manager.o \ kfd_device_queue_manager_cik.o kfd_device_queue_manager_vi.o \ - kfd_interrupt.o kfd_events.o cik_event_interrupt.o + kfd_interrupt.o kfd_events.o cik_event_interrupt.o \ + kfd_dbgdev.o kfd_dbgmgr.o obj-$(CONFIG_HSA_AMD) += amdkfd.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c new file mode 100644 index 000000000000..eed4a8345b7e --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c @@ -0,0 +1,142 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "kfd_pm4_headers.h" +#include "kfd_pm4_headers_diq.h" +#include "kfd_kernel_queue.h" +#include "kfd_priv.h" +#include "kfd_pm4_opcodes.h" +#include "cik_regs.h" +#include "kfd_dbgmgr.h" +#include "kfd_dbgdev.h" +#include "kfd_device_queue_manager.h" +#include "../../radeon/cik_reg.h" + +static void dbgdev_address_watch_disable_nodiq(struct kfd_dev *dev) +{ + BUG_ON(!dev || !dev->kfd2kgd); + + dev->kfd2kgd->address_watch_disable(dev->kgd); +} + +static int dbgdev_register_nodiq(struct kfd_dbgdev *dbgdev) +{ + BUG_ON(!dbgdev); + + /* + * no action is needed in this case, + * just make sure diq will not be used + */ + + dbgdev->kq = NULL; + + return 0; +} + +static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev) +{ + struct queue_properties properties; + unsigned int qid; + struct kernel_queue *kq = NULL; + int status; + + BUG_ON(!dbgdev || !dbgdev->pqm || !dbgdev->dev); + + status = pqm_create_queue(dbgdev->pqm, dbgdev->dev, NULL, + &properties, 0, KFD_QUEUE_TYPE_DIQ, + &qid); + + if (status) { + pr_err("amdkfd: Failed to create DIQ\n"); + return status; + } + + pr_debug("DIQ Created with queue id: %d\n", qid); + + kq = pqm_get_kernel_queue(dbgdev->pqm, qid); + + if (kq == NULL) { + pr_err("amdkfd: Error getting DIQ\n"); + pqm_destroy_queue(dbgdev->pqm, qid); + return -EFAULT; + } + + dbgdev->kq = kq; + + return status; +} + +static int dbgdev_unregister_nodiq(struct kfd_dbgdev *dbgdev) +{ + BUG_ON(!dbgdev || !dbgdev->dev); + + /* disable watch address */ + dbgdev_address_watch_disable_nodiq(dbgdev->dev); + return 0; +} + +static int dbgdev_unregister_diq(struct kfd_dbgdev *dbgdev) +{ + /* todo - disable address watch */ + int status; + + BUG_ON(!dbgdev || !dbgdev->pqm || !dbgdev->kq); + + status = pqm_destroy_queue(dbgdev->pqm, + dbgdev->kq->queue->properties.queue_id); + dbgdev->kq = NULL; + + return status; +} + +void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev, + enum DBGDEV_TYPE type) +{ + BUG_ON(!pdbgdev || !pdev); + + pdbgdev->dev = pdev; + pdbgdev->kq = NULL; + pdbgdev->type = type; + pdbgdev->pqm = NULL; + + switch (type) { + case DBGDEV_TYPE_NODIQ: + pdbgdev->dbgdev_register = dbgdev_register_nodiq; + pdbgdev->dbgdev_unregister = dbgdev_unregister_nodiq; + break; + case DBGDEV_TYPE_DIQ: + default: + pdbgdev->dbgdev_register = dbgdev_register_diq; + pdbgdev->dbgdev_unregister = dbgdev_unregister_diq; + break; + } + +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h new file mode 100644 index 000000000000..4b0dd5aa5306 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h @@ -0,0 +1,193 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef KFD_DBGDEV_H_ +#define KFD_DBGDEV_H_ + +enum { + SQ_CMD_VMID_OFFSET = 28, + ADDRESS_WATCH_CNTL_OFFSET = 24 +}; + +enum { + PRIV_QUEUE_SYNC_TIME_MS = 200 +}; + +/* CONTEXT reg space definition */ +enum { + CONTEXT_REG_BASE = 0xA000, + CONTEXT_REG_END = 0xA400, + CONTEXT_REG_SIZE = CONTEXT_REG_END - CONTEXT_REG_BASE +}; + +/* USER CONFIG reg space definition */ +enum { + USERCONFIG_REG_BASE = 0xC000, + USERCONFIG_REG_END = 0x10000, + USERCONFIG_REG_SIZE = USERCONFIG_REG_END - USERCONFIG_REG_BASE +}; + +/* CONFIG reg space definition */ +enum { + CONFIG_REG_BASE = 0x2000, /* in dwords */ + CONFIG_REG_END = 0x2B00, + CONFIG_REG_SIZE = CONFIG_REG_END - CONFIG_REG_BASE +}; + +/* SH reg space definition */ +enum { + SH_REG_BASE = 0x2C00, + SH_REG_END = 0x3000, + SH_REG_SIZE = SH_REG_END - SH_REG_BASE +}; + +enum SQ_IND_CMD_CMD { + SQ_IND_CMD_CMD_NULL = 0x00000000, + SQ_IND_CMD_CMD_HALT = 0x00000001, + SQ_IND_CMD_CMD_RESUME = 0x00000002, + SQ_IND_CMD_CMD_KILL = 0x00000003, + SQ_IND_CMD_CMD_DEBUG = 0x00000004, + SQ_IND_CMD_CMD_TRAP = 0x00000005, +}; + +enum SQ_IND_CMD_MODE { + SQ_IND_CMD_MODE_SINGLE = 0x00000000, + SQ_IND_CMD_MODE_BROADCAST = 0x00000001, + SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002, + SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003, + SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004, +}; + +union SQ_IND_INDEX_BITS { + struct { + uint32_t wave_id:4; + uint32_t simd_id:2; + uint32_t thread_id:6; + uint32_t:1; + uint32_t force_read:1; + uint32_t read_timeout:1; + uint32_t unindexed:1; + uint32_t index:16; + + } bitfields, bits; + uint32_t u32All; + signed int i32All; + float f32All; +}; + +union SQ_IND_CMD_BITS { + struct { + uint32_t data:32; + } bitfields, bits; + uint32_t u32All; + signed int i32All; + float f32All; +}; + +union SQ_CMD_BITS { + struct { + uint32_t cmd:3; + uint32_t:1; + uint32_t mode:3; + uint32_t check_vmid:1; + uint32_t trap_id:3; + uint32_t:5; + uint32_t wave_id:4; + uint32_t simd_id:2; + uint32_t:2; + uint32_t queue_id:3; + uint32_t:1; + uint32_t vm_id:4; + } bitfields, bits; + uint32_t u32All; + signed int i32All; + float f32All; +}; + +union SQ_IND_DATA_BITS { + struct { + uint32_t data:32; + } bitfields, bits; + uint32_t u32All; + signed int i32All; + float f32All; +}; + +union GRBM_GFX_INDEX_BITS { + struct { + uint32_t instance_index:8; + uint32_t sh_index:8; + uint32_t se_index:8; + uint32_t:5; + uint32_t sh_broadcast_writes:1; + uint32_t instance_broadcast_writes:1; + uint32_t se_broadcast_writes:1; + } bitfields, bits; + uint32_t u32All; + signed int i32All; + float f32All; +}; + +union TCP_WATCH_ADDR_H_BITS { + struct { + uint32_t addr:16; + uint32_t:16; + + } bitfields, bits; + uint32_t u32All; + signed int i32All; + float f32All; +}; + +union TCP_WATCH_ADDR_L_BITS { + struct { + uint32_t:6; + uint32_t addr:26; + } bitfields, bits; + uint32_t u32All; + signed int i32All; + float f32All; +}; + +enum { + QUEUESTATE__INVALID = 0, /* so by default we'll get invalid state */ + QUEUESTATE__ACTIVE_COMPLETION_PENDING, + QUEUESTATE__ACTIVE +}; + +union ULARGE_INTEGER { + struct { + uint32_t low_part; + uint32_t high_part; + } u; + unsigned long long quad_part; +}; + + +#define KFD_CIK_VMID_START_OFFSET (8) +#define KFD_CIK_VMID_END_OFFSET (KFD_CIK_VMID_START_OFFSET + (8)) + + +void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev, + enum DBGDEV_TYPE type); + +#endif /* KFD_DBGDEV_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c new file mode 100644 index 000000000000..959be983ac45 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c @@ -0,0 +1,135 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include +#include +#include +#include +#include + +#include "kfd_priv.h" +#include "cik_regs.h" +#include "kfd_pm4_headers.h" +#include "kfd_pm4_headers_diq.h" +#include "kfd_dbgmgr.h" +#include "kfd_dbgdev.h" + +static DEFINE_MUTEX(kfd_dbgmgr_mutex); + +struct mutex *kfd_get_dbgmgr_mutex(void) +{ + return &kfd_dbgmgr_mutex; +} + + +static void kfd_dbgmgr_uninitialize(struct kfd_dbgmgr *pmgr) +{ + BUG_ON(!pmgr); + + kfree(pmgr->dbgdev); + + pmgr->dbgdev = NULL; + pmgr->pasid = 0; + pmgr->dev = NULL; +} + +void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr) +{ + if (pmgr != NULL) { + kfd_dbgmgr_uninitialize(pmgr); + kfree(pmgr); + } +} + +bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev) +{ + enum DBGDEV_TYPE type = DBGDEV_TYPE_DIQ; + struct kfd_dbgmgr *new_buff; + + BUG_ON(pdev == NULL); + BUG_ON(!pdev->init_complete); + + new_buff = kfd_alloc_struct(new_buff); + if (!new_buff) { + pr_err("amdkfd: Failed to allocate dbgmgr instance\n"); + return false; + } + + new_buff->pasid = 0; + new_buff->dev = pdev; + new_buff->dbgdev = kfd_alloc_struct(new_buff->dbgdev); + if (!new_buff->dbgdev) { + pr_err("amdkfd: Failed to allocate dbgdev instance\n"); + kfree(new_buff); + return false; + } + + /* get actual type of DBGDevice cpsch or not */ + if (sched_policy == KFD_SCHED_POLICY_NO_HWS) + type = DBGDEV_TYPE_NODIQ; + + kfd_dbgdev_init(new_buff->dbgdev, pdev, type); + *ppmgr = new_buff; + + return true; +} + +long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p) +{ + BUG_ON(!p || !pmgr || !pmgr->dbgdev); + + if (pmgr->pasid != 0) { + pr_debug("H/W debugger is already active using pasid %d\n", + pmgr->pasid); + return -EBUSY; + } + + /* remember pasid */ + pmgr->pasid = p->pasid; + + /* provide the pqm for diq generation */ + pmgr->dbgdev->pqm = &p->pqm; + + /* activate the actual registering */ + pmgr->dbgdev->dbgdev_register(pmgr->dbgdev); + + return 0; +} + +long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p) +{ + BUG_ON(!p || !pmgr || !pmgr->dbgdev); + + /* Is the requests coming from the already registered process? */ + if (pmgr->pasid != p->pasid) { + pr_debug("H/W debugger is not registered by calling pasid %d\n", + p->pasid); + return -EINVAL; + } + + pmgr->dbgdev->dbgdev_unregister(pmgr->dbgdev); + + pmgr->pasid = 0; + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h new file mode 100644 index 000000000000..250cf88ce6d0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h @@ -0,0 +1,287 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_DBGMGR_H_ +#define KFD_DBGMGR_H_ + +#include "kfd_priv.h" + +/* must align with hsakmttypes definition */ +#pragma pack(push, 4) + +enum HSA_DBG_WAVEOP { + HSA_DBG_WAVEOP_HALT = 1, /* Halts a wavefront */ + HSA_DBG_WAVEOP_RESUME = 2, /* Resumes a wavefront */ + HSA_DBG_WAVEOP_KILL = 3, /* Kills a wavefront */ + HSA_DBG_WAVEOP_DEBUG = 4, /* Causes wavefront to enter + debug mode */ + HSA_DBG_WAVEOP_TRAP = 5, /* Causes wavefront to take + a trap */ + HSA_DBG_NUM_WAVEOP = 5, + HSA_DBG_MAX_WAVEOP = 0xFFFFFFFF +}; + +enum HSA_DBG_WAVEMODE { + /* send command to a single wave */ + HSA_DBG_WAVEMODE_SINGLE = 0, + /* + * Broadcast to all wavefronts of all processes is not + * supported for HSA user mode + */ + + /* send to waves within current process */ + HSA_DBG_WAVEMODE_BROADCAST_PROCESS = 2, + /* send to waves within current process on CU */ + HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU = 3, + HSA_DBG_NUM_WAVEMODE = 3, + HSA_DBG_MAX_WAVEMODE = 0xFFFFFFFF +}; + +enum HSA_DBG_WAVEMSG_TYPE { + HSA_DBG_WAVEMSG_AUTO = 0, + HSA_DBG_WAVEMSG_USER = 1, + HSA_DBG_WAVEMSG_ERROR = 2, + HSA_DBG_NUM_WAVEMSG, + HSA_DBG_MAX_WAVEMSG = 0xFFFFFFFF +}; + +enum HSA_DBG_WATCH_MODE { + HSA_DBG_WATCH_READ = 0, /* Read operations only */ + HSA_DBG_WATCH_NONREAD = 1, /* Write or Atomic operations only */ + HSA_DBG_WATCH_ATOMIC = 2, /* Atomic Operations only */ + HSA_DBG_WATCH_ALL = 3, /* Read, Write or Atomic operations */ + HSA_DBG_WATCH_NUM, + HSA_DBG_WATCH_SIZE = 0xFFFFFFFF +}; + +/* This structure is hardware specific and may change in the future */ +struct HsaDbgWaveMsgAMDGen2 { + union { + struct ui32 { + uint32_t UserData:8; /* user data */ + uint32_t ShaderArray:1; /* Shader array */ + uint32_t Priv:1; /* Privileged */ + uint32_t Reserved0:4; /* This field is reserved, + should be 0 */ + uint32_t WaveId:4; /* wave id */ + uint32_t SIMD:2; /* SIMD id */ + uint32_t HSACU:4; /* Compute unit */ + uint32_t ShaderEngine:2;/* Shader engine */ + uint32_t MessageType:2; /* see HSA_DBG_WAVEMSG_TYPE */ + uint32_t Reserved1:4; /* This field is reserved, + should be 0 */ + } ui32; + uint32_t Value; + }; + uint32_t Reserved2; +}; + +union HsaDbgWaveMessageAMD { + struct HsaDbgWaveMsgAMDGen2 WaveMsgInfoGen2; + /* for future HsaDbgWaveMsgAMDGen3; */ +}; + +struct HsaDbgWaveMessage { + void *MemoryVA; /* ptr to associated host-accessible data */ + union HsaDbgWaveMessageAMD DbgWaveMsg; +}; + +/* + * TODO: This definitions to be MOVED to kfd_event, once it is implemented. + * + * HSA sync primitive, Event and HW Exception notification API definitions. + * The API functions allow the runtime to define a so-called sync-primitive, + * a SW object combining a user-mode provided "syncvar" and a scheduler event + * that can be signaled through a defined GPU interrupt. A syncvar is + * a process virtual memory location of a certain size that can be accessed + * by CPU and GPU shader code within the process to set and query the content + * within that memory. The definition of the content is determined by the HSA + * runtime and potentially GPU shader code interfacing with the HSA runtime. + * The syncvar values may be commonly written through an PM4 WRITE_DATA packet + * in the user mode instruction stream. The OS scheduler event is typically + * associated and signaled by an interrupt issued by the GPU, but other HSA + * system interrupt conditions from other HW (e.g. IOMMUv2) may be surfaced + * by the KFD by this mechanism, too. */ + +/* these are the new definitions for events */ +enum HSA_EVENTTYPE { + HSA_EVENTTYPE_SIGNAL = 0, /* user-mode generated GPU signal */ + HSA_EVENTTYPE_NODECHANGE = 1, /* HSA node change (attach/detach) */ + HSA_EVENTTYPE_DEVICESTATECHANGE = 2, /* HSA device state change + (start/stop) */ + HSA_EVENTTYPE_HW_EXCEPTION = 3, /* GPU shader exception event */ + HSA_EVENTTYPE_SYSTEM_EVENT = 4, /* GPU SYSCALL with parameter info */ + HSA_EVENTTYPE_DEBUG_EVENT = 5, /* GPU signal for debugging */ + HSA_EVENTTYPE_PROFILE_EVENT = 6,/* GPU signal for profiling */ + HSA_EVENTTYPE_QUEUE_EVENT = 7, /* GPU signal queue idle state + (EOP pm4) */ + /* ... */ + HSA_EVENTTYPE_MAXID, + HSA_EVENTTYPE_TYPE_SIZE = 0xFFFFFFFF +}; + +/* Sub-definitions for various event types: Syncvar */ +struct HsaSyncVar { + union SyncVar { + void *UserData; /* pointer to user mode data */ + uint64_t UserDataPtrValue; /* 64bit compatibility of value */ + } SyncVar; + uint64_t SyncVarSize; +}; + +/* Sub-definitions for various event types: NodeChange */ + +enum HSA_EVENTTYPE_NODECHANGE_FLAGS { + HSA_EVENTTYPE_NODECHANGE_ADD = 0, + HSA_EVENTTYPE_NODECHANGE_REMOVE = 1, + HSA_EVENTTYPE_NODECHANGE_SIZE = 0xFFFFFFFF +}; + +struct HsaNodeChange { + /* HSA node added/removed on the platform */ + enum HSA_EVENTTYPE_NODECHANGE_FLAGS Flags; +}; + +/* Sub-definitions for various event types: DeviceStateChange */ +enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS { + /* device started (and available) */ + HSA_EVENTTYPE_DEVICESTATUSCHANGE_START = 0, + /* device stopped (i.e. unavailable) */ + HSA_EVENTTYPE_DEVICESTATUSCHANGE_STOP = 1, + HSA_EVENTTYPE_DEVICESTATUSCHANGE_SIZE = 0xFFFFFFFF +}; + +enum HSA_DEVICE { + HSA_DEVICE_CPU = 0, + HSA_DEVICE_GPU = 1, + MAX_HSA_DEVICE = 2 +}; + +struct HsaDeviceStateChange { + uint32_t NodeId; /* F-NUMA node that contains the device */ + enum HSA_DEVICE Device; /* device type: GPU or CPU */ + enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS Flags; /* event flags */ +}; + +struct HsaEventData { + enum HSA_EVENTTYPE EventType; /* event type */ + union EventData { + /* + * return data associated with HSA_EVENTTYPE_SIGNAL + * and other events + */ + struct HsaSyncVar SyncVar; + + /* data associated with HSA_EVENTTYPE_NODE_CHANGE */ + struct HsaNodeChange NodeChangeState; + + /* data associated with HSA_EVENTTYPE_DEVICE_STATE_CHANGE */ + struct HsaDeviceStateChange DeviceState; + } EventData; + + /* the following data entries are internal to the KFD & thunk itself */ + + /* internal thunk store for Event data (OsEventHandle) */ + uint64_t HWData1; + /* internal thunk store for Event data (HWAddress) */ + uint64_t HWData2; + /* internal thunk store for Event data (HWData) */ + uint32_t HWData3; +}; + +struct HsaEventDescriptor { + /* event type to allocate */ + enum HSA_EVENTTYPE EventType; + /* H-NUMA node containing GPU device that is event source */ + uint32_t NodeId; + /* pointer to user mode syncvar data, syncvar->UserDataPtrValue + * may be NULL + */ + struct HsaSyncVar SyncVar; +}; + +struct HsaEvent { + uint32_t EventId; + struct HsaEventData EventData; +}; + +#pragma pack(pop) + +enum DBGDEV_TYPE { + DBGDEV_TYPE_ILLEGAL = 0, + DBGDEV_TYPE_NODIQ = 1, + DBGDEV_TYPE_DIQ = 2, + DBGDEV_TYPE_TEST = 3 +}; + +struct dbg_address_watch_info { + struct kfd_process *process; + enum HSA_DBG_WATCH_MODE *watch_mode; + uint64_t *watch_address; + uint64_t *watch_mask; + struct HsaEvent *watch_event; + uint32_t num_watch_points; +}; + +struct dbg_wave_control_info { + struct kfd_process *process; + uint32_t trapId; + enum HSA_DBG_WAVEOP operand; + enum HSA_DBG_WAVEMODE mode; + struct HsaDbgWaveMessage dbgWave_msg; +}; + +struct kfd_dbgdev { + + /* The device that owns this data. */ + struct kfd_dev *dev; + + /* kernel queue for DIQ */ + struct kernel_queue *kq; + + /* a pointer to the pqm of the calling process */ + struct process_queue_manager *pqm; + + /* type of debug device ( DIQ, non DIQ, etc. ) */ + enum DBGDEV_TYPE type; + + /* virtualized function pointers to device dbg */ + int (*dbgdev_register)(struct kfd_dbgdev *dbgdev); + int (*dbgdev_unregister)(struct kfd_dbgdev *dbgdev); + +}; + +struct kfd_dbgmgr { + unsigned int pasid; + struct kfd_dev *dev; + struct kfd_dbgdev *dbgdev; +}; + +/* prototypes for debug manager functions */ +struct mutex *kfd_get_dbgmgr_mutex(void); +void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr); +bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev); +long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p); +long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p); + +#endif /* KFD_DBGMGR_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index f1f86db27f73..1d1e2e952a79 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -37,6 +37,7 @@ static const struct kfd_device_info kaveri_device_info = { .max_no_of_hqd = 24, .ih_ring_entry_size = 4 * sizeof(uint32_t), .event_interrupt_class = &event_interrupt_class_cik, + .num_of_watch_points = 4, .mqd_size_aligned = MQD_SIZE_ALIGNED }; @@ -296,6 +297,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, goto dqm_start_error; } + kfd->dbgmgr = NULL; + kfd->init_complete = true; dev_info(kfd_device, "added device (%x:%x)\n", kfd->pdev->vendor, kfd->pdev->device); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h new file mode 100644 index 000000000000..a0ff34878163 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h @@ -0,0 +1,290 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_PM4_HEADERS_DIQ_H_ +#define KFD_PM4_HEADERS_DIQ_H_ + +/*--------------------_INDIRECT_BUFFER-------------------- */ + +#ifndef _PM4__INDIRECT_BUFFER_DEFINED +#define _PM4__INDIRECT_BUFFER_DEFINED +enum _INDIRECT_BUFFER_cache_policy_enum { + cache_policy___indirect_buffer__lru = 0, + cache_policy___indirect_buffer__stream = 1, + cache_policy___indirect_buffer__bypass = 2 +}; + +enum { + IT_INDIRECT_BUFFER_PASID = 0x5C +}; + +struct pm4__indirect_buffer_pasid { + union { + union PM4_MES_TYPE_3_HEADER header; /* header */ + unsigned int ordinal1; + }; + + union { + struct { + unsigned int reserved1:2; + unsigned int ib_base_lo:30; + } bitfields2; + unsigned int ordinal2; + }; + + union { + struct { + unsigned int ib_base_hi:16; + unsigned int reserved2:16; + } bitfields3; + unsigned int ordinal3; + }; + + union { + unsigned int control; + unsigned int ordinal4; + }; + + union { + struct { + unsigned int pasid:10; + unsigned int reserved4:22; + } bitfields5; + unsigned int ordinal5; + }; + +}; + +#endif + +/*--------------------_RELEASE_MEM-------------------- */ + +#ifndef _PM4__RELEASE_MEM_DEFINED +#define _PM4__RELEASE_MEM_DEFINED +enum _RELEASE_MEM_event_index_enum { + event_index___release_mem__end_of_pipe = 5, + event_index___release_mem__shader_done = 6 +}; + +enum _RELEASE_MEM_cache_policy_enum { + cache_policy___release_mem__lru = 0, + cache_policy___release_mem__stream = 1, + cache_policy___release_mem__bypass = 2 +}; + +enum _RELEASE_MEM_dst_sel_enum { + dst_sel___release_mem__memory_controller = 0, + dst_sel___release_mem__tc_l2 = 1, + dst_sel___release_mem__queue_write_pointer_register = 2, + dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3 +}; + +enum _RELEASE_MEM_int_sel_enum { + int_sel___release_mem__none = 0, + int_sel___release_mem__send_interrupt_only = 1, + int_sel___release_mem__send_interrupt_after_write_confirm = 2, + int_sel___release_mem__send_data_after_write_confirm = 3 +}; + +enum _RELEASE_MEM_data_sel_enum { + data_sel___release_mem__none = 0, + data_sel___release_mem__send_32_bit_low = 1, + data_sel___release_mem__send_64_bit_data = 2, + data_sel___release_mem__send_gpu_clock_counter = 3, + data_sel___release_mem__send_cp_perfcounter_hi_lo = 4, + data_sel___release_mem__store_gds_data_to_memory = 5 +}; + +struct pm4__release_mem { + union { + union PM4_MES_TYPE_3_HEADER header; /*header */ + unsigned int ordinal1; + }; + + union { + struct { + unsigned int event_type:6; + unsigned int reserved1:2; + enum _RELEASE_MEM_event_index_enum event_index:4; + unsigned int tcl1_vol_action_ena:1; + unsigned int tc_vol_action_ena:1; + unsigned int reserved2:1; + unsigned int tc_wb_action_ena:1; + unsigned int tcl1_action_ena:1; + unsigned int tc_action_ena:1; + unsigned int reserved3:6; + unsigned int atc:1; + enum _RELEASE_MEM_cache_policy_enum cache_policy:2; + unsigned int reserved4:5; + } bitfields2; + unsigned int ordinal2; + }; + + union { + struct { + unsigned int reserved5:16; + enum _RELEASE_MEM_dst_sel_enum dst_sel:2; + unsigned int reserved6:6; + enum _RELEASE_MEM_int_sel_enum int_sel:3; + unsigned int reserved7:2; + enum _RELEASE_MEM_data_sel_enum data_sel:3; + } bitfields3; + unsigned int ordinal3; + }; + + union { + struct { + unsigned int reserved8:2; + unsigned int address_lo_32b:30; + } bitfields4; + struct { + unsigned int reserved9:3; + unsigned int address_lo_64b:29; + } bitfields5; + unsigned int ordinal4; + }; + + unsigned int address_hi; + + unsigned int data_lo; + + unsigned int data_hi; + +}; +#endif + + +/*--------------------_SET_CONFIG_REG-------------------- */ + +#ifndef _PM4__SET_CONFIG_REG_DEFINED +#define _PM4__SET_CONFIG_REG_DEFINED + +struct pm4__set_config_reg { + union { + union PM4_MES_TYPE_3_HEADER header; /*header */ + unsigned int ordinal1; + }; + + union { + struct { + unsigned int reg_offset:16; + unsigned int reserved1:7; + unsigned int vmid_shift:5; + unsigned int insert_vmid:1; + unsigned int reserved2:3; + } bitfields2; + unsigned int ordinal2; + }; + + unsigned int reg_data[1]; /*1..N of these fields */ + +}; +#endif + +/*--------------------_WAIT_REG_MEM-------------------- */ + +#ifndef _PM4__WAIT_REG_MEM_DEFINED +#define _PM4__WAIT_REG_MEM_DEFINED +enum _WAIT_REG_MEM_function_enum { + function___wait_reg_mem__always_pass = 0, + function___wait_reg_mem__less_than_ref_value = 1, + function___wait_reg_mem__less_than_equal_to_the_ref_value = 2, + function___wait_reg_mem__equal_to_the_reference_value = 3, + function___wait_reg_mem__not_equal_reference_value = 4, + function___wait_reg_mem__greater_than_or_equal_reference_value = 5, + function___wait_reg_mem__greater_than_reference_value = 6, + function___wait_reg_mem__reserved = 7 +}; + +enum _WAIT_REG_MEM_mem_space_enum { + mem_space___wait_reg_mem__register_space = 0, + mem_space___wait_reg_mem__memory_space = 1 +}; + +enum _WAIT_REG_MEM_operation_enum { + operation___wait_reg_mem__wait_reg_mem = 0, + operation___wait_reg_mem__wr_wait_wr_reg = 1 +}; + +struct pm4__wait_reg_mem { + union { + union PM4_MES_TYPE_3_HEADER header; /*header */ + unsigned int ordinal1; + }; + + union { + struct { + enum _WAIT_REG_MEM_function_enum function:3; + unsigned int reserved1:1; + enum _WAIT_REG_MEM_mem_space_enum mem_space:2; + enum _WAIT_REG_MEM_operation_enum operation:2; + unsigned int reserved2:24; + } bitfields2; + unsigned int ordinal2; + }; + + union { + struct { + unsigned int reserved3:2; + unsigned int memory_poll_addr_lo:30; + } bitfields3; + struct { + unsigned int register_poll_addr:16; + unsigned int reserved4:16; + } bitfields4; + struct { + unsigned int register_write_addr:16; + unsigned int reserved5:16; + } bitfields5; + unsigned int ordinal3; + }; + + union { + struct { + unsigned int poll_address_hi:16; + unsigned int reserved6:16; + } bitfields6; + struct { + unsigned int register_write_addr:16; + unsigned int reserved7:16; + } bitfields7; + unsigned int ordinal4; + }; + + unsigned int reference; + + unsigned int mask; + + union { + struct { + unsigned int poll_interval:16; + unsigned int reserved8:16; + } bitfields8; + unsigned int ordinal7; + }; + +}; +#endif + + +#endif /* KFD_PM4_HEADERS_DIQ_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index eda7281c4a07..a65a28157333 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -196,6 +196,9 @@ struct kfd_dev { * from the HW ring into a SW ring. */ bool interrupts_active; + + /* Debug manager */ + struct kfd_dbgmgr *dbgmgr; }; /* KGD2KFD callbacks */ @@ -650,6 +653,8 @@ int pqm_create_queue(struct process_queue_manager *pqm, int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid); int pqm_update_queue(struct process_queue_manager *pqm, unsigned int qid, struct queue_properties *p); +struct kernel_queue *pqm_get_kernel_queue(struct process_queue_manager *pqm, + unsigned int qid); /* Packet Manager */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 85b7fecd1c5d..7b69070f7ecc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -357,7 +357,7 @@ int pqm_update_queue(struct process_queue_manager *pqm, unsigned int qid, return 0; } -static __attribute__((unused)) struct kernel_queue *pqm_get_kernel_queue( +struct kernel_queue *pqm_get_kernel_queue( struct process_queue_manager *pqm, unsigned int qid) { -- cgit v1.2.3 From 788bf83db3017f083ebb84c93f101607c769c3a7 Mon Sep 17 00:00:00 2001 From: Yair Shachar Date: Wed, 20 May 2015 13:58:12 +0300 Subject: drm/amdkfd: Add wave control operation to debugger The wave control operation supports several command types executed upon existing wave fronts that belong to the currently debugged process. The available commands are: HALT - Freeze wave front(s) execution RESUME - Resume freezed wave front(s) execution KILL - Kill existing wave front(s) Signed-off-by: Yair Shachar Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c | 405 +++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c | 16 + drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h | 5 +- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 + 5 files changed, 430 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c index eed4a8345b7e..ee33b86e493d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c @@ -47,6 +47,125 @@ static void dbgdev_address_watch_disable_nodiq(struct kfd_dev *dev) dev->kfd2kgd->address_watch_disable(dev->kgd); } +static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, + unsigned int pasid, uint64_t vmid0_address, + uint32_t *packet_buff, size_t size_in_bytes) +{ + struct pm4__release_mem *rm_packet; + struct pm4__indirect_buffer_pasid *ib_packet; + struct kfd_mem_obj *mem_obj; + size_t pq_packets_size_in_bytes; + union ULARGE_INTEGER *largep; + union ULARGE_INTEGER addr; + struct kernel_queue *kq; + uint64_t *rm_state; + unsigned int *ib_packet_buff; + int status; + + BUG_ON(!dbgdev || !dbgdev->kq || !packet_buff || !size_in_bytes); + + kq = dbgdev->kq; + + pq_packets_size_in_bytes = sizeof(struct pm4__release_mem) + + sizeof(struct pm4__indirect_buffer_pasid); + + /* + * We acquire a buffer from DIQ + * The receive packet buff will be sitting on the Indirect Buffer + * and in the PQ we put the IB packet + sync packet(s). + */ + status = kq->ops.acquire_packet_buffer(kq, + pq_packets_size_in_bytes / sizeof(uint32_t), + &ib_packet_buff); + if (status != 0) { + pr_err("amdkfd: acquire_packet_buffer failed\n"); + return status; + } + + memset(ib_packet_buff, 0, pq_packets_size_in_bytes); + + ib_packet = (struct pm4__indirect_buffer_pasid *) (ib_packet_buff); + + ib_packet->header.count = 3; + ib_packet->header.opcode = IT_INDIRECT_BUFFER_PASID; + ib_packet->header.type = PM4_TYPE_3; + + largep = (union ULARGE_INTEGER *) &vmid0_address; + + ib_packet->bitfields2.ib_base_lo = largep->u.low_part >> 2; + ib_packet->bitfields3.ib_base_hi = largep->u.high_part; + + ib_packet->control = (1 << 23) | (1 << 31) | + ((size_in_bytes / sizeof(uint32_t)) & 0xfffff); + + ib_packet->bitfields5.pasid = pasid; + + /* + * for now we use release mem for GPU-CPU synchronization + * Consider WaitRegMem + WriteData as a better alternative + * we get a GART allocations ( gpu/cpu mapping), + * for the sync variable, and wait until: + * (a) Sync with HW + * (b) Sync var is written by CP to mem. + */ + rm_packet = (struct pm4__release_mem *) (ib_packet_buff + + (sizeof(struct pm4__indirect_buffer_pasid) / + sizeof(unsigned int))); + + status = kfd_gtt_sa_allocate(dbgdev->dev, sizeof(uint64_t), + &mem_obj); + + if (status != 0) { + pr_err("amdkfd: Failed to allocate GART memory\n"); + kq->ops.rollback_packet(kq); + return status; + } + + rm_state = (uint64_t *) mem_obj->cpu_ptr; + + *rm_state = QUEUESTATE__ACTIVE_COMPLETION_PENDING; + + rm_packet->header.opcode = IT_RELEASE_MEM; + rm_packet->header.type = PM4_TYPE_3; + rm_packet->header.count = sizeof(struct pm4__release_mem) / + sizeof(unsigned int) - 2; + + rm_packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT; + rm_packet->bitfields2.event_index = + event_index___release_mem__end_of_pipe; + + rm_packet->bitfields2.cache_policy = cache_policy___release_mem__lru; + rm_packet->bitfields2.atc = 0; + rm_packet->bitfields2.tc_wb_action_ena = 1; + + addr.quad_part = mem_obj->gpu_addr; + + rm_packet->bitfields4.address_lo_32b = addr.u.low_part >> 2; + rm_packet->address_hi = addr.u.high_part; + + rm_packet->bitfields3.data_sel = + data_sel___release_mem__send_64_bit_data; + + rm_packet->bitfields3.int_sel = + int_sel___release_mem__send_data_after_write_confirm; + + rm_packet->bitfields3.dst_sel = + dst_sel___release_mem__memory_controller; + + rm_packet->data_lo = QUEUESTATE__ACTIVE; + + kq->ops.submit_packet(kq); + + /* Wait till CP writes sync code: */ + status = amdkfd_fence_wait_timeout( + (unsigned int *) rm_state, + QUEUESTATE__ACTIVE, 1500); + + kfd_gtt_sa_free(dbgdev->dev, mem_obj); + + return status; +} + static int dbgdev_register_nodiq(struct kfd_dbgdev *dbgdev) { BUG_ON(!dbgdev); @@ -117,6 +236,290 @@ static int dbgdev_unregister_diq(struct kfd_dbgdev *dbgdev) return status; } +static int dbgdev_wave_control_set_registers( + struct dbg_wave_control_info *wac_info, + union SQ_CMD_BITS *in_reg_sq_cmd, + union GRBM_GFX_INDEX_BITS *in_reg_gfx_index) +{ + int status; + union SQ_CMD_BITS reg_sq_cmd; + union GRBM_GFX_INDEX_BITS reg_gfx_index; + struct HsaDbgWaveMsgAMDGen2 *pMsg; + + BUG_ON(!wac_info || !in_reg_sq_cmd || !in_reg_gfx_index); + + reg_sq_cmd.u32All = 0; + reg_gfx_index.u32All = 0; + pMsg = &wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2; + + switch (wac_info->mode) { + /* Send command to single wave */ + case HSA_DBG_WAVEMODE_SINGLE: + /* + * Limit access to the process waves only, + * by setting vmid check + */ + reg_sq_cmd.bits.check_vmid = 1; + reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD; + reg_sq_cmd.bits.wave_id = pMsg->ui32.WaveId; + reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_SINGLE; + + reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray; + reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine; + reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU; + + break; + + /* Send command to all waves with matching VMID */ + case HSA_DBG_WAVEMODE_BROADCAST_PROCESS: + + reg_gfx_index.bits.sh_broadcast_writes = 1; + reg_gfx_index.bits.se_broadcast_writes = 1; + reg_gfx_index.bits.instance_broadcast_writes = 1; + + reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; + + break; + + /* Send command to all CU waves with matching VMID */ + case HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU: + + reg_sq_cmd.bits.check_vmid = 1; + reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST; + + reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray; + reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine; + reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU; + + break; + + default: + return -EINVAL; + } + + switch (wac_info->operand) { + case HSA_DBG_WAVEOP_HALT: + reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_HALT; + break; + + case HSA_DBG_WAVEOP_RESUME: + reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_RESUME; + break; + + case HSA_DBG_WAVEOP_KILL: + reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL; + break; + + case HSA_DBG_WAVEOP_DEBUG: + reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_DEBUG; + break; + + case HSA_DBG_WAVEOP_TRAP: + if (wac_info->trapId < MAX_TRAPID) { + reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_TRAP; + reg_sq_cmd.bits.trap_id = wac_info->trapId; + } else { + status = -EINVAL; + } + break; + + default: + status = -EINVAL; + break; + } + + if (status == 0) { + *in_reg_sq_cmd = reg_sq_cmd; + *in_reg_gfx_index = reg_gfx_index; + } + + return status; +} + +static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev, + struct dbg_wave_control_info *wac_info) +{ + + int status; + union SQ_CMD_BITS reg_sq_cmd; + union GRBM_GFX_INDEX_BITS reg_gfx_index; + struct kfd_mem_obj *mem_obj; + uint32_t *packet_buff_uint; + struct pm4__set_config_reg *packets_vec; + size_t ib_size = sizeof(struct pm4__set_config_reg) * 3; + + BUG_ON(!dbgdev || !wac_info); + + reg_sq_cmd.u32All = 0; + + status = dbgdev_wave_control_set_registers(wac_info, ®_sq_cmd, + ®_gfx_index); + if (status) { + pr_err("amdkfd: Failed to set wave control registers\n"); + return status; + } + + /* we do not control the VMID in DIQ,so reset it to a known value */ + reg_sq_cmd.bits.vm_id = 0; + + pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *"); + + pr_debug("\t\t mode is: %u\n", wac_info->mode); + pr_debug("\t\t operand is: %u\n", wac_info->operand); + pr_debug("\t\t trap id is: %u\n", wac_info->trapId); + pr_debug("\t\t msg value is: %u\n", + wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value); + pr_debug("\t\t vmid is: N/A\n"); + + pr_debug("\t\t chk_vmid is : %u\n", reg_sq_cmd.bitfields.check_vmid); + pr_debug("\t\t command is : %u\n", reg_sq_cmd.bitfields.cmd); + pr_debug("\t\t queue id is : %u\n", reg_sq_cmd.bitfields.queue_id); + pr_debug("\t\t simd id is : %u\n", reg_sq_cmd.bitfields.simd_id); + pr_debug("\t\t mode is : %u\n", reg_sq_cmd.bitfields.mode); + pr_debug("\t\t vm_id is : %u\n", reg_sq_cmd.bitfields.vm_id); + pr_debug("\t\t wave_id is : %u\n", reg_sq_cmd.bitfields.wave_id); + + pr_debug("\t\t ibw is : %u\n", + reg_gfx_index.bitfields.instance_broadcast_writes); + pr_debug("\t\t ii is : %u\n", + reg_gfx_index.bitfields.instance_index); + pr_debug("\t\t sebw is : %u\n", + reg_gfx_index.bitfields.se_broadcast_writes); + pr_debug("\t\t se_ind is : %u\n", reg_gfx_index.bitfields.se_index); + pr_debug("\t\t sh_ind is : %u\n", reg_gfx_index.bitfields.sh_index); + pr_debug("\t\t sbw is : %u\n", + reg_gfx_index.bitfields.sh_broadcast_writes); + + pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *"); + + status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj); + + if (status != 0) { + pr_err("amdkfd: Failed to allocate GART memory\n"); + return status; + } + + packet_buff_uint = mem_obj->cpu_ptr; + + memset(packet_buff_uint, 0, ib_size); + + packets_vec = (struct pm4__set_config_reg *) packet_buff_uint; + packets_vec[0].header.count = 1; + packets_vec[0].header.opcode = IT_SET_UCONFIG_REG; + packets_vec[0].header.type = PM4_TYPE_3; + packets_vec[0].bitfields2.reg_offset = + GRBM_GFX_INDEX / (sizeof(uint32_t)) - + USERCONFIG_REG_BASE; + + packets_vec[0].bitfields2.insert_vmid = 0; + packets_vec[0].reg_data[0] = reg_gfx_index.u32All; + + packets_vec[1].header.count = 1; + packets_vec[1].header.opcode = IT_SET_CONFIG_REG; + packets_vec[1].header.type = PM4_TYPE_3; + packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) - + CONFIG_REG_BASE; + + packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET; + packets_vec[1].bitfields2.insert_vmid = 1; + packets_vec[1].reg_data[0] = reg_sq_cmd.u32All; + + /* Restore the GRBM_GFX_INDEX register */ + + reg_gfx_index.u32All = 0; + reg_gfx_index.bits.sh_broadcast_writes = 1; + reg_gfx_index.bits.instance_broadcast_writes = 1; + reg_gfx_index.bits.se_broadcast_writes = 1; + + + packets_vec[2].ordinal1 = packets_vec[0].ordinal1; + packets_vec[2].bitfields2.reg_offset = + GRBM_GFX_INDEX / (sizeof(uint32_t)) - + USERCONFIG_REG_BASE; + + packets_vec[2].bitfields2.insert_vmid = 0; + packets_vec[2].reg_data[0] = reg_gfx_index.u32All; + + status = dbgdev_diq_submit_ib( + dbgdev, + wac_info->process->pasid, + mem_obj->gpu_addr, + packet_buff_uint, + ib_size); + + if (status != 0) + pr_err("amdkfd: Failed to submit IB to DIQ\n"); + + kfd_gtt_sa_free(dbgdev->dev, mem_obj); + + return status; +} + +static int dbgdev_wave_control_nodiq(struct kfd_dbgdev *dbgdev, + struct dbg_wave_control_info *wac_info) +{ + int status; + union SQ_CMD_BITS reg_sq_cmd; + union GRBM_GFX_INDEX_BITS reg_gfx_index; + struct kfd_process_device *pdd; + + BUG_ON(!dbgdev || !dbgdev->dev || !wac_info); + + reg_sq_cmd.u32All = 0; + + /* taking the VMID for that process on the safe way using PDD */ + pdd = kfd_get_process_device_data(dbgdev->dev, wac_info->process); + + if (!pdd) { + pr_err("amdkfd: Failed to get pdd for wave control no DIQ\n"); + return -EFAULT; + } + status = dbgdev_wave_control_set_registers(wac_info, ®_sq_cmd, + ®_gfx_index); + if (status) { + pr_err("amdkfd: Failed to set wave control registers\n"); + return status; + } + + /* for non DIQ we need to patch the VMID: */ + + reg_sq_cmd.bits.vm_id = pdd->qpd.vmid; + + pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *"); + + pr_debug("\t\t mode is: %u\n", wac_info->mode); + pr_debug("\t\t operand is: %u\n", wac_info->operand); + pr_debug("\t\t trap id is: %u\n", wac_info->trapId); + pr_debug("\t\t msg value is: %u\n", + wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value); + pr_debug("\t\t vmid is: %u\n", pdd->qpd.vmid); + + pr_debug("\t\t chk_vmid is : %u\n", reg_sq_cmd.bitfields.check_vmid); + pr_debug("\t\t command is : %u\n", reg_sq_cmd.bitfields.cmd); + pr_debug("\t\t queue id is : %u\n", reg_sq_cmd.bitfields.queue_id); + pr_debug("\t\t simd id is : %u\n", reg_sq_cmd.bitfields.simd_id); + pr_debug("\t\t mode is : %u\n", reg_sq_cmd.bitfields.mode); + pr_debug("\t\t vm_id is : %u\n", reg_sq_cmd.bitfields.vm_id); + pr_debug("\t\t wave_id is : %u\n", reg_sq_cmd.bitfields.wave_id); + + pr_debug("\t\t ibw is : %u\n", + reg_gfx_index.bitfields.instance_broadcast_writes); + pr_debug("\t\t ii is : %u\n", + reg_gfx_index.bitfields.instance_index); + pr_debug("\t\t sebw is : %u\n", + reg_gfx_index.bitfields.se_broadcast_writes); + pr_debug("\t\t se_ind is : %u\n", reg_gfx_index.bitfields.se_index); + pr_debug("\t\t sh_ind is : %u\n", reg_gfx_index.bitfields.sh_index); + pr_debug("\t\t sbw is : %u\n", + reg_gfx_index.bitfields.sh_broadcast_writes); + + pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *"); + + return dbgdev->dev->kfd2kgd->wave_control_execute(dbgdev->dev->kgd, + reg_gfx_index.u32All, + reg_sq_cmd.u32All); +} + void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev, enum DBGDEV_TYPE type) { @@ -131,11 +534,13 @@ void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev, case DBGDEV_TYPE_NODIQ: pdbgdev->dbgdev_register = dbgdev_register_nodiq; pdbgdev->dbgdev_unregister = dbgdev_unregister_nodiq; + pdbgdev->dbgdev_wave_control = dbgdev_wave_control_nodiq; break; case DBGDEV_TYPE_DIQ: default: pdbgdev->dbgdev_register = dbgdev_register_diq; pdbgdev->dbgdev_unregister = dbgdev_unregister_diq; + pdbgdev->dbgdev_wave_control = dbgdev_wave_control_diq; break; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c index 959be983ac45..7e2c8e2ed959 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c @@ -133,3 +133,19 @@ long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p) return 0; } + +long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr, + struct dbg_wave_control_info *wac_info) +{ + BUG_ON(!pmgr || !pmgr->dbgdev || !wac_info); + + /* Is the requests coming from the already registered process? */ + if (pmgr->pasid != wac_info->process->pasid) { + pr_debug("H/W debugger support was not registered for requester pasid %d\n", + wac_info->process->pasid); + return -EINVAL; + } + + return (long) pmgr->dbgdev->dbgdev_wave_control(pmgr->dbgdev, wac_info); +} + diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h index 250cf88ce6d0..6da9d36e7a85 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h @@ -268,6 +268,8 @@ struct kfd_dbgdev { /* virtualized function pointers to device dbg */ int (*dbgdev_register)(struct kfd_dbgdev *dbgdev); int (*dbgdev_unregister)(struct kfd_dbgdev *dbgdev); + int (*dbgdev_wave_control)(struct kfd_dbgdev *dbgdev, + struct dbg_wave_control_info *wac_info); }; @@ -283,5 +285,6 @@ void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr); bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev); long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p); long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p); - +long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr, + struct dbg_wave_control_info *wac_info); #endif /* KFD_DBGMGR_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index a5dc8228b6b1..b08ec05658fe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -915,7 +915,7 @@ out: return retval; } -static int amdkfd_fence_wait_timeout(unsigned int *fence_addr, +int amdkfd_fence_wait_timeout(unsigned int *fence_addr, unsigned int fence_value, unsigned long timeout) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index a65a28157333..cd1f033c7488 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -656,6 +656,10 @@ int pqm_update_queue(struct process_queue_manager *pqm, unsigned int qid, struct kernel_queue *pqm_get_kernel_queue(struct process_queue_manager *pqm, unsigned int qid); +int amdkfd_fence_wait_timeout(unsigned int *fence_addr, + unsigned int fence_value, + unsigned long timeout); + /* Packet Manager */ #define KFD_HIQ_TIMEOUT (500) -- cgit v1.2.3 From e2e9afc4a3d4a256da37821992c4de5ad469a010 Mon Sep 17 00:00:00 2001 From: Yair Shachar Date: Wed, 20 May 2015 13:59:17 +0300 Subject: drm/amdkfd: Add address watch operation to debugger The address watch operation gives the ability to specify watch points which will generate a shader breakpoint, based on a specified single address or range of addresses. There is support for read/write/any access modes. Signed-off-by: Yair Shachar Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c | 274 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c | 17 ++ drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h | 4 + 3 files changed, 295 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c index ee33b86e493d..00d8fcfa17ea 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c @@ -236,6 +236,278 @@ static int dbgdev_unregister_diq(struct kfd_dbgdev *dbgdev) return status; } +static void dbgdev_address_watch_set_registers( + const struct dbg_address_watch_info *adw_info, + union TCP_WATCH_ADDR_H_BITS *addrHi, + union TCP_WATCH_ADDR_L_BITS *addrLo, + union TCP_WATCH_CNTL_BITS *cntl, + unsigned int index, unsigned int vmid) +{ + union ULARGE_INTEGER addr; + + BUG_ON(!adw_info || !addrHi || !addrLo || !cntl); + + addr.quad_part = 0; + addrHi->u32All = 0; + addrLo->u32All = 0; + cntl->u32All = 0; + + if (adw_info->watch_mask != NULL) + cntl->bitfields.mask = + (uint32_t) (adw_info->watch_mask[index] & + ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK); + else + cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; + + addr.quad_part = (unsigned long long) adw_info->watch_address[index]; + + addrHi->bitfields.addr = addr.u.high_part & + ADDRESS_WATCH_REG_ADDHIGH_MASK; + addrLo->bitfields.addr = + (addr.u.low_part >> ADDRESS_WATCH_REG_ADDLOW_SHIFT); + + cntl->bitfields.mode = adw_info->watch_mode[index]; + cntl->bitfields.vmid = (uint32_t) vmid; + /* for now assume it is an ATC address */ + cntl->u32All |= ADDRESS_WATCH_REG_CNTL_ATC_BIT; + + pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask); + pr_debug("\t\t%20s %08x\n", "set reg add high :", + addrHi->bitfields.addr); + pr_debug("\t\t%20s %08x\n", "set reg add low :", + addrLo->bitfields.addr); +} + +static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev, + struct dbg_address_watch_info *adw_info) +{ + union TCP_WATCH_ADDR_H_BITS addrHi; + union TCP_WATCH_ADDR_L_BITS addrLo; + union TCP_WATCH_CNTL_BITS cntl; + struct kfd_process_device *pdd; + unsigned int i; + + BUG_ON(!dbgdev || !dbgdev->dev || !adw_info); + + /* taking the vmid for that process on the safe way using pdd */ + pdd = kfd_get_process_device_data(dbgdev->dev, + adw_info->process); + if (!pdd) { + pr_err("amdkfd: Failed to get pdd for wave control no DIQ\n"); + return -EFAULT; + } + + addrHi.u32All = 0; + addrLo.u32All = 0; + cntl.u32All = 0; + + if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) || + (adw_info->num_watch_points == 0)) { + pr_err("amdkfd: num_watch_points is invalid\n"); + return -EINVAL; + } + + if ((adw_info->watch_mode == NULL) || + (adw_info->watch_address == NULL)) { + pr_err("amdkfd: adw_info fields are not valid\n"); + return -EINVAL; + } + + for (i = 0 ; i < adw_info->num_watch_points ; i++) { + dbgdev_address_watch_set_registers(adw_info, &addrHi, &addrLo, + &cntl, i, pdd->qpd.vmid); + + pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *"); + pr_debug("\t\t%20s %08x\n", "register index :", i); + pr_debug("\t\t%20s %08x\n", "vmid is :", pdd->qpd.vmid); + pr_debug("\t\t%20s %08x\n", "Address Low is :", + addrLo.bitfields.addr); + pr_debug("\t\t%20s %08x\n", "Address high is :", + addrHi.bitfields.addr); + pr_debug("\t\t%20s %08x\n", "Address high is :", + addrHi.bitfields.addr); + pr_debug("\t\t%20s %08x\n", "Control Mask is :", + cntl.bitfields.mask); + pr_debug("\t\t%20s %08x\n", "Control Mode is :", + cntl.bitfields.mode); + pr_debug("\t\t%20s %08x\n", "Control Vmid is :", + cntl.bitfields.vmid); + pr_debug("\t\t%20s %08x\n", "Control atc is :", + cntl.bitfields.atc); + pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *"); + + pdd->dev->kfd2kgd->address_watch_execute( + dbgdev->dev->kgd, + i, + cntl.u32All, + addrHi.u32All, + addrLo.u32All); + } + + return 0; +} + +static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, + struct dbg_address_watch_info *adw_info) +{ + struct pm4__set_config_reg *packets_vec; + union TCP_WATCH_ADDR_H_BITS addrHi; + union TCP_WATCH_ADDR_L_BITS addrLo; + union TCP_WATCH_CNTL_BITS cntl; + struct kfd_mem_obj *mem_obj; + unsigned int aw_reg_add_dword; + uint32_t *packet_buff_uint; + unsigned int i; + int status; + size_t ib_size = sizeof(struct pm4__set_config_reg) * 4; + /* we do not control the vmid in DIQ mode, just a place holder */ + unsigned int vmid = 0; + + BUG_ON(!dbgdev || !dbgdev->dev || !adw_info); + + addrHi.u32All = 0; + addrLo.u32All = 0; + cntl.u32All = 0; + + if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) || + (adw_info->num_watch_points == 0)) { + pr_err("amdkfd: num_watch_points is invalid\n"); + return -EINVAL; + } + + if ((NULL == adw_info->watch_mode) || + (NULL == adw_info->watch_address)) { + pr_err("amdkfd: adw_info fields are not valid\n"); + return -EINVAL; + } + + status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj); + + if (status != 0) { + pr_err("amdkfd: Failed to allocate GART memory\n"); + return status; + } + + packet_buff_uint = mem_obj->cpu_ptr; + + memset(packet_buff_uint, 0, ib_size); + + packets_vec = (struct pm4__set_config_reg *) (packet_buff_uint); + + packets_vec[0].header.count = 1; + packets_vec[0].header.opcode = IT_SET_CONFIG_REG; + packets_vec[0].header.type = PM4_TYPE_3; + packets_vec[0].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET; + packets_vec[0].bitfields2.insert_vmid = 1; + packets_vec[1].ordinal1 = packets_vec[0].ordinal1; + packets_vec[1].bitfields2.insert_vmid = 0; + packets_vec[2].ordinal1 = packets_vec[0].ordinal1; + packets_vec[2].bitfields2.insert_vmid = 0; + packets_vec[3].ordinal1 = packets_vec[0].ordinal1; + packets_vec[3].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET; + packets_vec[3].bitfields2.insert_vmid = 1; + + for (i = 0; i < adw_info->num_watch_points; i++) { + dbgdev_address_watch_set_registers(adw_info, + &addrHi, + &addrLo, + &cntl, + i, + vmid); + + pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *"); + pr_debug("\t\t%20s %08x\n", "register index :", i); + pr_debug("\t\t%20s %08x\n", "vmid is :", vmid); + pr_debug("\t\t%20s %p\n", "Add ptr is :", + adw_info->watch_address); + pr_debug("\t\t%20s %08llx\n", "Add is :", + adw_info->watch_address[i]); + pr_debug("\t\t%20s %08x\n", "Address Low is :", + addrLo.bitfields.addr); + pr_debug("\t\t%20s %08x\n", "Address high is :", + addrHi.bitfields.addr); + pr_debug("\t\t%20s %08x\n", "Control Mask is :", + cntl.bitfields.mask); + pr_debug("\t\t%20s %08x\n", "Control Mode is :", + cntl.bitfields.mode); + pr_debug("\t\t%20s %08x\n", "Control Vmid is :", + cntl.bitfields.vmid); + pr_debug("\t\t%20s %08x\n", "Control atc is :", + cntl.bitfields.atc); + pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *"); + + aw_reg_add_dword = + dbgdev->dev->kfd2kgd->address_watch_get_offset( + dbgdev->dev->kgd, + i, + ADDRESS_WATCH_REG_CNTL); + + aw_reg_add_dword /= sizeof(uint32_t); + + packets_vec[0].bitfields2.reg_offset = + aw_reg_add_dword - CONFIG_REG_BASE; + + packets_vec[0].reg_data[0] = cntl.u32All; + + aw_reg_add_dword = + dbgdev->dev->kfd2kgd->address_watch_get_offset( + dbgdev->dev->kgd, + i, + ADDRESS_WATCH_REG_ADDR_HI); + + aw_reg_add_dword /= sizeof(uint32_t); + + packets_vec[1].bitfields2.reg_offset = + aw_reg_add_dword - CONFIG_REG_BASE; + packets_vec[1].reg_data[0] = addrHi.u32All; + + aw_reg_add_dword = + dbgdev->dev->kfd2kgd->address_watch_get_offset( + dbgdev->dev->kgd, + i, + ADDRESS_WATCH_REG_ADDR_LO); + + aw_reg_add_dword /= sizeof(uint32_t); + + packets_vec[2].bitfields2.reg_offset = + aw_reg_add_dword - CONFIG_REG_BASE; + packets_vec[2].reg_data[0] = addrLo.u32All; + + /* enable watch flag if address is not zero*/ + if (adw_info->watch_address[i] > 0) + cntl.bitfields.valid = 1; + else + cntl.bitfields.valid = 0; + + aw_reg_add_dword = + dbgdev->dev->kfd2kgd->address_watch_get_offset( + dbgdev->dev->kgd, + i, + ADDRESS_WATCH_REG_CNTL); + + aw_reg_add_dword /= sizeof(uint32_t); + + packets_vec[3].bitfields2.reg_offset = + aw_reg_add_dword - CONFIG_REG_BASE; + packets_vec[3].reg_data[0] = cntl.u32All; + + status = dbgdev_diq_submit_ib( + dbgdev, + adw_info->process->pasid, + mem_obj->gpu_addr, + packet_buff_uint, + ib_size); + + if (status != 0) { + pr_err("amdkfd: Failed to submit IB to DIQ\n"); + break; + } + } + + kfd_gtt_sa_free(dbgdev->dev, mem_obj); + return status; +} + static int dbgdev_wave_control_set_registers( struct dbg_wave_control_info *wac_info, union SQ_CMD_BITS *in_reg_sq_cmd, @@ -535,12 +807,14 @@ void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev, pdbgdev->dbgdev_register = dbgdev_register_nodiq; pdbgdev->dbgdev_unregister = dbgdev_unregister_nodiq; pdbgdev->dbgdev_wave_control = dbgdev_wave_control_nodiq; + pdbgdev->dbgdev_address_watch = dbgdev_address_watch_nodiq; break; case DBGDEV_TYPE_DIQ: default: pdbgdev->dbgdev_register = dbgdev_register_diq; pdbgdev->dbgdev_unregister = dbgdev_unregister_diq; pdbgdev->dbgdev_wave_control = dbgdev_wave_control_diq; + pdbgdev->dbgdev_address_watch = dbgdev_address_watch_diq; break; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c index 7e2c8e2ed959..56d676396342 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c @@ -149,3 +149,20 @@ long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr, return (long) pmgr->dbgdev->dbgdev_wave_control(pmgr->dbgdev, wac_info); } +long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr, + struct dbg_address_watch_info *adw_info) +{ + BUG_ON(!pmgr || !pmgr->dbgdev || !adw_info); + + + /* Is the requests coming from the already registered process? */ + if (pmgr->pasid != adw_info->process->pasid) { + pr_debug("H/W debugger support was not registered for requester pasid %d\n", + adw_info->process->pasid); + return -EINVAL; + } + + return (long) pmgr->dbgdev->dbgdev_address_watch(pmgr->dbgdev, + adw_info); +} + diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h index 6da9d36e7a85..257a745ad0b5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h @@ -268,6 +268,8 @@ struct kfd_dbgdev { /* virtualized function pointers to device dbg */ int (*dbgdev_register)(struct kfd_dbgdev *dbgdev); int (*dbgdev_unregister)(struct kfd_dbgdev *dbgdev); + int (*dbgdev_address_watch)(struct kfd_dbgdev *dbgdev, + struct dbg_address_watch_info *adw_info); int (*dbgdev_wave_control)(struct kfd_dbgdev *dbgdev, struct dbg_wave_control_info *wac_info); @@ -287,4 +289,6 @@ long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p); long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p); long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr, struct dbg_wave_control_info *wac_info); +long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr, + struct dbg_address_watch_info *adw_info); #endif /* KFD_DBGMGR_H_ */ -- cgit v1.2.3 From 037ed9a2ac262e496bb0ddc924895e5f72969961 Mon Sep 17 00:00:00 2001 From: Yair Shachar Date: Wed, 20 May 2015 14:08:55 +0300 Subject: drm/amdkfd: Implement (un)register debugger IOCTLs v2: rename get_dbgmgr_mutex to kfd_get_dbgmgr_mutex to namespace it Signed-off-by: Yair Shachar Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 72 +++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index b358e910378f..54a3e2923863 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -35,6 +35,7 @@ #include #include "kfd_priv.h" #include "kfd_device_queue_manager.h" +#include "kfd_dbgmgr.h" static long kfd_ioctl(struct file *, unsigned int, unsigned long); static int kfd_open(struct inode *, struct file *); @@ -435,7 +436,53 @@ out: static int kfd_ioctl_dbg_register(struct file *filep, struct kfd_process *p, void *data) { - long status = -EFAULT; + struct kfd_ioctl_dbg_register_args *args = data; + struct kfd_dev *dev; + struct kfd_dbgmgr *dbgmgr_ptr; + struct kfd_process_device *pdd; + bool create_ok; + long status = 0; + + dev = kfd_device_by_id(args->gpu_id); + if (dev == NULL) + return -EINVAL; + + if (dev->device_info->asic_family == CHIP_CARRIZO) { + pr_debug("kfd_ioctl_dbg_register not supported on CZ\n"); + return -EINVAL; + } + + mutex_lock(kfd_get_dbgmgr_mutex()); + mutex_lock(&p->mutex); + + /* + * make sure that we have pdd, if this the first queue created for + * this process + */ + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + mutex_unlock(&p->mutex); + mutex_unlock(kfd_get_dbgmgr_mutex()); + return PTR_ERR(pdd); + } + + if (dev->dbgmgr == NULL) { + /* In case of a legal call, we have no dbgmgr yet */ + create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev); + if (create_ok) { + status = kfd_dbgmgr_register(dbgmgr_ptr, p); + if (status != 0) + kfd_dbgmgr_destroy(dbgmgr_ptr); + else + dev->dbgmgr = dbgmgr_ptr; + } + } else { + pr_debug("debugger already registered\n"); + status = -EINVAL; + } + + mutex_unlock(&p->mutex); + mutex_unlock(kfd_get_dbgmgr_mutex()); return status; } @@ -443,7 +490,28 @@ static int kfd_ioctl_dbg_register(struct file *filep, static int kfd_ioctl_dbg_unrgesiter(struct file *filep, struct kfd_process *p, void *data) { - long status = -EFAULT; + struct kfd_ioctl_dbg_unregister_args *args = data; + struct kfd_dev *dev; + long status; + + dev = kfd_device_by_id(args->gpu_id); + if (dev == NULL) + return -EINVAL; + + if (dev->device_info->asic_family == CHIP_CARRIZO) { + pr_debug("kfd_ioctl_dbg_unrgesiter not supported on CZ\n"); + return -EINVAL; + } + + mutex_lock(kfd_get_dbgmgr_mutex()); + + status = kfd_dbgmgr_unregister(dev->dbgmgr, p); + if (status == 0) { + kfd_dbgmgr_destroy(dev->dbgmgr); + dev->dbgmgr = NULL; + } + + mutex_unlock(kfd_get_dbgmgr_mutex()); return status; } -- cgit v1.2.3 From 9448458998e27be7fcb9ebc58200be45a6429451 Mon Sep 17 00:00:00 2001 From: Yair Shachar Date: Wed, 20 May 2015 14:09:24 +0300 Subject: drm/amdkfd: Implement wave control debugger IOCTL v2: - rename get_dbgmgr_mutex to kfd_get_dbgmgr_mutex to namespace it - change void* to uint64_t inside ioctl arguments - use kmalloc instead of kzalloc because we use copy_from_user immediately after it Signed-off-by: Yair Shachar Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 88 +++++++++++++++++++++++++++++++- 1 file changed, 87 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 54a3e2923863..9e5261de0716 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -537,7 +537,93 @@ static int kfd_ioctl_dbg_address_watch(struct file *filep, static int kfd_ioctl_dbg_wave_control(struct file *filep, struct kfd_process *p, void *data) { - long status = -EFAULT; + struct kfd_ioctl_dbg_wave_control_args *args = data; + struct kfd_dev *dev; + struct dbg_wave_control_info wac_info; + unsigned char *args_buff; + uint32_t computed_buff_size; + long status; + void __user *cmd_from_user; + unsigned int args_idx = 0; + + memset((void *) &wac_info, 0, sizeof(struct dbg_wave_control_info)); + + /* we use compact form, independent of the packing attribute value */ + computed_buff_size = sizeof(*args) + + sizeof(wac_info.mode) + + sizeof(wac_info.operand) + + sizeof(wac_info.dbgWave_msg.DbgWaveMsg) + + sizeof(wac_info.dbgWave_msg.MemoryVA) + + sizeof(wac_info.trapId); + + dev = kfd_device_by_id(args->gpu_id); + if (dev == NULL) + return -EINVAL; + + if (dev->device_info->asic_family == CHIP_CARRIZO) { + pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n"); + return -EINVAL; + } + + /* input size must match the computed "compact" size */ + if (args->buf_size_in_bytes != computed_buff_size) { + pr_debug("size mismatch, computed : actual %u : %u\n", + args->buf_size_in_bytes, computed_buff_size); + return -EINVAL; + } + + cmd_from_user = (void __user *) args->content_ptr; + + if (cmd_from_user == NULL) + return -EINVAL; + + /* this is the actual buffer to work with */ + + args_buff = kmalloc(args->buf_size_in_bytes - sizeof(*args), + GFP_KERNEL); + + if (args_buff == NULL) + return -ENOMEM; + + /* Now copy the entire buffer from user */ + status = copy_from_user(args_buff, cmd_from_user, + args->buf_size_in_bytes - sizeof(*args)); + if (status != 0) { + pr_debug("Failed to copy wave control user data\n"); + kfree(args_buff); + return -EINVAL; + } + + /* move ptr to the start of the "pay-load" area */ + wac_info.process = p; + + wac_info.operand = *((enum HSA_DBG_WAVEOP *)(&args_buff[args_idx])); + args_idx += sizeof(wac_info.operand); + + wac_info.mode = *((enum HSA_DBG_WAVEMODE *)(&args_buff[args_idx])); + args_idx += sizeof(wac_info.mode); + + wac_info.trapId = *((uint32_t *)(&args_buff[args_idx])); + args_idx += sizeof(wac_info.trapId); + + wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value = + *((uint32_t *)(&args_buff[args_idx])); + wac_info.dbgWave_msg.MemoryVA = NULL; + + mutex_lock(kfd_get_dbgmgr_mutex()); + + pr_debug("Calling dbg manager process %p, operand %u, mode %u, trapId %u, message %u\n", + wac_info.process, wac_info.operand, + wac_info.mode, wac_info.trapId, + wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value); + + status = kfd_dbgmgr_wave_control(dev->dbgmgr, &wac_info); + + pr_debug("Returned status of dbg manager is %ld\n", status); + + mutex_unlock(kfd_get_dbgmgr_mutex()); + + kfree(args_buff); return status; } -- cgit v1.2.3 From f8bd13338a9a42358158954251969e66934ec3d1 Mon Sep 17 00:00:00 2001 From: Yair Shachar Date: Wed, 20 May 2015 14:09:39 +0300 Subject: drm/amdkfd: Implement address watch debugger IOCTL v2: - rename get_dbgmgr_mutex to kfd_get_dbgmgr_mutex to namespace it - change void* to uint64_t inside ioctl arguments - use kmalloc instead of kzalloc because we use copy_from_user immediately after it Signed-off-by: Yair Shachar Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 102 ++++++++++++++++++++++++++++++- 1 file changed, 101 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 9e5261de0716..96c904b3acb7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -528,7 +528,107 @@ static int kfd_ioctl_dbg_unrgesiter(struct file *filep, static int kfd_ioctl_dbg_address_watch(struct file *filep, struct kfd_process *p, void *data) { - long status = -EFAULT; + struct kfd_ioctl_dbg_address_watch_args *args = data; + struct kfd_dev *dev; + struct dbg_address_watch_info aw_info; + unsigned char *args_buff; + long status; + void __user *cmd_from_user; + uint64_t watch_mask_value = 0; + unsigned int args_idx = 0; + + memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info)); + + dev = kfd_device_by_id(args->gpu_id); + if (dev == NULL) + return -EINVAL; + + if (dev->device_info->asic_family == CHIP_CARRIZO) { + pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n"); + return -EINVAL; + } + + cmd_from_user = (void __user *) args->content_ptr; + + /* Validate arguments */ + + if ((args->buf_size_in_bytes > MAX_ALLOWED_AW_BUFF_SIZE) || + (args->buf_size_in_bytes <= sizeof(*args)) || + (cmd_from_user == NULL)) + return -EINVAL; + + /* this is the actual buffer to work with */ + + args_buff = kmalloc(args->buf_size_in_bytes - + sizeof(*args), GFP_KERNEL); + if (args_buff == NULL) + return -ENOMEM; + + status = copy_from_user(args_buff, cmd_from_user, + args->buf_size_in_bytes - sizeof(*args)); + + if (status != 0) { + pr_debug("Failed to copy address watch user data\n"); + kfree(args_buff); + return -EINVAL; + } + + aw_info.process = p; + + aw_info.num_watch_points = *((uint32_t *)(&args_buff[args_idx])); + args_idx += sizeof(aw_info.num_watch_points); + + aw_info.watch_mode = (enum HSA_DBG_WATCH_MODE *) &args_buff[args_idx]; + args_idx += sizeof(enum HSA_DBG_WATCH_MODE) * aw_info.num_watch_points; + + /* + * set watch address base pointer to point on the array base + * within args_buff + */ + aw_info.watch_address = (uint64_t *) &args_buff[args_idx]; + + /* skip over the addresses buffer */ + args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points; + + if (args_idx >= args->buf_size_in_bytes) { + kfree(args_buff); + return -EINVAL; + } + + watch_mask_value = (uint64_t) args_buff[args_idx]; + + if (watch_mask_value > 0) { + /* + * There is an array of masks. + * set watch mask base pointer to point on the array base + * within args_buff + */ + aw_info.watch_mask = (uint64_t *) &args_buff[args_idx]; + + /* skip over the masks buffer */ + args_idx += sizeof(aw_info.watch_mask) * + aw_info.num_watch_points; + } else { + /* just the NULL mask, set to NULL and skip over it */ + aw_info.watch_mask = NULL; + args_idx += sizeof(aw_info.watch_mask); + } + + if (args_idx > args->buf_size_in_bytes) { + kfree(args_buff); + return -EINVAL; + } + + /* Currently HSA Event is not supported for DBG */ + aw_info.watch_event = NULL; + + mutex_lock(kfd_get_dbgmgr_mutex()); + + status = kfd_dbgmgr_address_watch(dev->dbgmgr, &aw_info); + + mutex_unlock(kfd_get_dbgmgr_mutex()); + + kfree(args_buff); return status; } -- cgit v1.2.3 From edad40239ffcaafd7eb56e4060d472aa5af2df21 Mon Sep 17 00:00:00 2001 From: Alexey Skidanov Date: Tue, 19 May 2015 19:25:01 +0300 Subject: drm/radeon: Add ATC VMID<-->PASID functions to kfd->kgd This patch adds three new interfaces to kfd2kgd interface file of radeon. The interfaces are: - Check if a specific VMID has a valid PASID mapping - Retrieve the PASID which is mapped to a specific VMID - Issue a VMID invalidation request to the ATC Signed-off-by: Alexey Skidanov Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 8 ++++++ drivers/gpu/drm/radeon/cikd.h | 9 ++++-- drivers/gpu/drm/radeon/radeon_kfd.c | 38 +++++++++++++++++++++++-- 3 files changed, 50 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index afde1b75eeee..9080daa116b6 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -175,6 +175,14 @@ struct kfd2kgd_calls { uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd, unsigned int watch_point_id, unsigned int reg_offset); + bool (*get_atc_vmid_pasid_mapping_valid)( + struct kgd_dev *kgd, + uint8_t vmid); + uint16_t (*get_atc_vmid_pasid_mapping_pasid)( + struct kgd_dev *kgd, + uint8_t vmid); + void (*write_vmid_invalidate_request)(struct kgd_dev *kgd, + uint8_t vmid); uint16_t (*get_fw_version)(struct kgd_dev *kgd, enum kgd_engine_type type); diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index b33ba3b0808b..391ff9d5d706 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h @@ -2148,9 +2148,12 @@ #define VCE_CMD_IB_AUTO 0x00000005 #define VCE_CMD_SEMAPHORE 0x00000006 -#define ATC_VMID0_PASID_MAPPING 0x339Cu -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u -#define ATC_VMID_PASID_MAPPING_VALID (1U << 31) +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u +#define ATC_VMID0_PASID_MAPPING 0x339Cu +#define ATC_VMID_PASID_MAPPING_PASID_MASK (0xFFFF) +#define ATC_VMID_PASID_MAPPING_PASID_SHIFT 0 +#define ATC_VMID_PASID_MAPPING_VALID_MASK (0x1 << 31) +#define ATC_VMID_PASID_MAPPING_VALID_SHIFT 31 #define ATC_VM_APERTURE0_CNTL 0x3310u #define ATS_ACCESS_MODE_NEVER 0 diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c index fd9590de2605..e476c331f3fa 100644 --- a/drivers/gpu/drm/radeon/radeon_kfd.c +++ b/drivers/gpu/drm/radeon/radeon_kfd.c @@ -99,6 +99,11 @@ static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, unsigned int watch_point_id, unsigned int reg_offset); +static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid); +static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, + uint8_t vmid); +static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid); + static const struct kfd2kgd_calls kfd2kgd = { .init_gtt_mem_allocation = alloc_gtt_mem, .free_gtt_mem = free_gtt_mem, @@ -119,6 +124,9 @@ static const struct kfd2kgd_calls kfd2kgd = { .address_watch_execute = kgd_address_watch_execute, .wave_control_execute = kgd_wave_control_execute, .address_watch_get_offset = kgd_address_watch_get_offset, + .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid, + .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid, + .write_vmid_invalidate_request = write_vmid_invalidate_request, .get_fw_version = get_fw_version }; @@ -395,8 +403,8 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, * the SW cleared it. * So the protocol is to always wait & clear. */ - uint32_t pasid_mapping = (pasid == 0) ? 0 : - (uint32_t)pasid | ATC_VMID_PASID_MAPPING_VALID; + uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | + ATC_VMID_PASID_MAPPING_VALID_MASK; write_register(kgd, ATC_VMID0_PASID_MAPPING + vmid*sizeof(uint32_t), pasid_mapping); @@ -778,6 +786,32 @@ static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset]; } +static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid) +{ + uint32_t reg; + struct radeon_device *rdev = (struct radeon_device *) kgd; + + reg = RREG32(ATC_VMID0_PASID_MAPPING + vmid*4); + return reg & ATC_VMID_PASID_MAPPING_VALID_MASK; +} + +static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, + uint8_t vmid) +{ + uint32_t reg; + struct radeon_device *rdev = (struct radeon_device *) kgd; + + reg = RREG32(ATC_VMID0_PASID_MAPPING + vmid*4); + return reg & ATC_VMID_PASID_MAPPING_PASID_MASK; +} + +static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid) +{ + struct radeon_device *rdev = (struct radeon_device *) kgd; + + return WREG32(VM_INVALIDATE_REQUEST, 1 << vmid); +} + static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) { struct radeon_device *rdev = (struct radeon_device *) kgd; -- cgit v1.2.3 From c3447e815062bb48d70a5afa0567fd6f30bc7f1b Mon Sep 17 00:00:00 2001 From: Ben Goz Date: Wed, 20 May 2015 18:05:44 +0300 Subject: drm/amdkfd: Enforce kill all waves on process termination This commit makes sure that on process termination, after we're destroying all the active queues, we're killing all the existing wave front of the current process. By doing this we're making sure that if any of the CUs were blocked by infinite loop we're enforcing it to end the shader explicitly. Signed-off-by: Ben Goz Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c | 65 ++++++++++++++++++++++ .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 8 ++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 7 +++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 11 ++++ 4 files changed, 90 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c index 00d8fcfa17ea..96153f28d73f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c @@ -792,6 +792,71 @@ static int dbgdev_wave_control_nodiq(struct kfd_dbgdev *dbgdev, reg_sq_cmd.u32All); } +int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p) +{ + int status = 0; + unsigned int vmid; + union SQ_CMD_BITS reg_sq_cmd; + union GRBM_GFX_INDEX_BITS reg_gfx_index; + struct kfd_process_device *pdd; + struct dbg_wave_control_info wac_info; + int temp; + int first_vmid_to_scan = 8; + int last_vmid_to_scan = 15; + + first_vmid_to_scan = ffs(dev->shared_resources.compute_vmid_bitmap) - 1; + temp = dev->shared_resources.compute_vmid_bitmap >> first_vmid_to_scan; + last_vmid_to_scan = first_vmid_to_scan + ffz(temp); + + reg_sq_cmd.u32All = 0; + status = 0; + + wac_info.mode = HSA_DBG_WAVEMODE_BROADCAST_PROCESS; + wac_info.operand = HSA_DBG_WAVEOP_KILL; + + pr_debug("Killing all process wavefronts\n"); + + /* Scan all registers in the range ATC_VMID8_PASID_MAPPING .. + * ATC_VMID15_PASID_MAPPING + * to check which VMID the current process is mapped to. */ + + for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) { + if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_valid + (dev->kgd, vmid)) { + if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_valid + (dev->kgd, vmid) == p->pasid) { + pr_debug("Killing wave fronts of vmid %d and pasid %d\n", + vmid, p->pasid); + break; + } + } + } + + if (vmid > last_vmid_to_scan) { + pr_err("amdkfd: didn't found vmid for pasid (%d)\n", p->pasid); + return -EFAULT; + } + + /* taking the VMID for that process on the safe way using PDD */ + pdd = kfd_get_process_device_data(dev, p); + if (!pdd) + return -EFAULT; + + status = dbgdev_wave_control_set_registers(&wac_info, ®_sq_cmd, + ®_gfx_index); + if (status != 0) + return -EINVAL; + + /* for non DIQ we need to patch the VMID: */ + reg_sq_cmd.bits.vm_id = vmid; + + dev->kfd2kgd->wave_control_execute(dev->kgd, + reg_gfx_index.u32All, + reg_sq_cmd.u32All); + + return 0; +} + void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev, enum DBGDEV_TYPE type) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index b08ec05658fe..547b0a589693 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -946,6 +946,7 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, { int retval; enum kfd_preempt_type_filter preempt_type; + struct kfd_process *p; BUG_ON(!dqm); @@ -977,8 +978,13 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr, KFD_FENCE_COMPLETED); /* should be timed out */ - amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED, + retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED, QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS); + if (retval != 0) { + p = kfd_get_process(current); + p->reset_wavefronts = true; + goto out; + } pm_release_ib(&dqm->packets); dqm->active_runlist = false; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index cd1f033c7488..cb79046e5c80 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -519,6 +519,11 @@ struct kfd_process { event_pages */ u32 next_nonsignal_event_id; size_t signal_event_count; + /* + * This flag tells if we should reset all wavefronts on + * process termination + */ + bool reset_wavefronts; }; /** @@ -726,4 +731,6 @@ int kfd_event_create(struct file *devkfd, struct kfd_process *p, uint64_t *event_page_offset, uint32_t *event_slot_index); int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); +int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p); + #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index dc910af2bb3c..56b904f5bdb1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -31,6 +31,7 @@ struct mm_struct; #include "kfd_priv.h" +#include "kfd_dbgmgr.h" /* * Initial size for the array of queues. @@ -172,6 +173,9 @@ static void kfd_process_wq_release(struct work_struct *work) pr_debug("Releasing pdd (topology id %d) for process (pasid %d) in workqueue\n", pdd->dev->id, p->pasid); + if (p->reset_wavefronts) + dbgdev_wave_reset_wavefronts(pdd->dev, p); + amd_iommu_unbind_pasid(pdd->dev->pdev, p->pasid); list_del(&pdd->per_device_list); @@ -301,6 +305,8 @@ static struct kfd_process *create_process(const struct task_struct *thread) if (kfd_init_apertures(process) != 0) goto err_init_apretures; + process->reset_wavefronts = false; + return process; err_init_apretures: @@ -399,7 +405,12 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid) mutex_lock(&p->mutex); + if ((dev->dbgmgr) && (dev->dbgmgr->pasid == p->pasid)) + kfd_dbgmgr_destroy(dev->dbgmgr); + pqm_uninit(&p->pqm); + if (p->reset_wavefronts) + dbgdev_wave_reset_wavefronts(dev, p); pdd = kfd_get_process_device_data(dev, p); -- cgit v1.2.3 From dc5698e80cf724770283e10414054662bdf6ccfa Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Sep 2013 10:02:56 +1000 Subject: Add virtio gpu driver. This patch adds a kms driver for the virtio gpu. The xorg modesetting driver can handle the device just fine, the framebuffer for fbcon is there too. Qemu patches for the host side are under review currently. The pci version of the device comes in two variants: with and without vga compatibility. The former has a extra memory bar for the vga framebuffer, the later is a pure virtio device. The only concern for this driver is that in the virtio-vga case we have to kick out the firmware framebuffer. Initial revision has only 2d support, 3d (virgl) support requires some more work on the qemu side and will be added later. Signed-off-by: Dave Airlie Signed-off-by: Gerd Hoffmann Acked-by: Michael S. Tsirkin --- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/virtio/Kconfig | 14 + drivers/gpu/drm/virtio/Makefile | 11 + drivers/gpu/drm/virtio/virtgpu_debugfs.c | 64 ++++ drivers/gpu/drm/virtio/virtgpu_display.c | 473 ++++++++++++++++++++++++ drivers/gpu/drm/virtio/virtgpu_drm_bus.c | 91 +++++ drivers/gpu/drm/virtio/virtgpu_drv.c | 136 +++++++ drivers/gpu/drm/virtio/virtgpu_drv.h | 350 ++++++++++++++++++ drivers/gpu/drm/virtio/virtgpu_fb.c | 431 ++++++++++++++++++++++ drivers/gpu/drm/virtio/virtgpu_fence.c | 119 ++++++ drivers/gpu/drm/virtio/virtgpu_gem.c | 140 +++++++ drivers/gpu/drm/virtio/virtgpu_kms.c | 173 +++++++++ drivers/gpu/drm/virtio/virtgpu_object.c | 170 +++++++++ drivers/gpu/drm/virtio/virtgpu_plane.c | 120 ++++++ drivers/gpu/drm/virtio/virtgpu_ttm.c | 469 +++++++++++++++++++++++ drivers/gpu/drm/virtio/virtgpu_vq.c | 614 +++++++++++++++++++++++++++++++ include/drm/drmP.h | 1 + include/uapi/linux/Kbuild | 1 + include/uapi/linux/virtio_gpu.h | 204 ++++++++++ include/uapi/linux/virtio_ids.h | 1 + 21 files changed, 3585 insertions(+) create mode 100644 drivers/gpu/drm/virtio/Kconfig create mode 100644 drivers/gpu/drm/virtio/Makefile create mode 100644 drivers/gpu/drm/virtio/virtgpu_debugfs.c create mode 100644 drivers/gpu/drm/virtio/virtgpu_display.c create mode 100644 drivers/gpu/drm/virtio/virtgpu_drm_bus.c create mode 100644 drivers/gpu/drm/virtio/virtgpu_drv.c create mode 100644 drivers/gpu/drm/virtio/virtgpu_drv.h create mode 100644 drivers/gpu/drm/virtio/virtgpu_fb.c create mode 100644 drivers/gpu/drm/virtio/virtgpu_fence.c create mode 100644 drivers/gpu/drm/virtio/virtgpu_gem.c create mode 100644 drivers/gpu/drm/virtio/virtgpu_kms.c create mode 100644 drivers/gpu/drm/virtio/virtgpu_object.c create mode 100644 drivers/gpu/drm/virtio/virtgpu_plane.c create mode 100644 drivers/gpu/drm/virtio/virtgpu_ttm.c create mode 100644 drivers/gpu/drm/virtio/virtgpu_vq.c create mode 100644 include/uapi/linux/virtio_gpu.h (limited to 'drivers') diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 47f2ce81b412..d4b65457122d 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -206,6 +206,8 @@ source "drivers/gpu/drm/qxl/Kconfig" source "drivers/gpu/drm/bochs/Kconfig" +source "drivers/gpu/drm/virtio/Kconfig" + source "drivers/gpu/drm/msm/Kconfig" source "drivers/gpu/drm/tegra/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 4de8d9b006ec..8e75f8194bde 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_DRM_OMAP) += omapdrm/ obj-$(CONFIG_DRM_TILCDC) += tilcdc/ obj-$(CONFIG_DRM_QXL) += qxl/ obj-$(CONFIG_DRM_BOCHS) += bochs/ +obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio/ obj-$(CONFIG_DRM_MSM) += msm/ obj-$(CONFIG_DRM_TEGRA) += tegra/ obj-$(CONFIG_DRM_STI) += sti/ diff --git a/drivers/gpu/drm/virtio/Kconfig b/drivers/gpu/drm/virtio/Kconfig new file mode 100644 index 000000000000..9983eadb81b6 --- /dev/null +++ b/drivers/gpu/drm/virtio/Kconfig @@ -0,0 +1,14 @@ +config DRM_VIRTIO_GPU + tristate "Virtio GPU driver" + depends on DRM && VIRTIO + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select DRM_KMS_HELPER + select DRM_KMS_FB_HELPER + select DRM_TTM + help + This is the virtual GPU driver for virtio. It can be used with + QEMU based VMMs (like KVM or Xen). + + If unsure say M. diff --git a/drivers/gpu/drm/virtio/Makefile b/drivers/gpu/drm/virtio/Makefile new file mode 100644 index 000000000000..2ee1602d77d4 --- /dev/null +++ b/drivers/gpu/drm/virtio/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for the drm device driver. This driver provides support for the +# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. + +ccflags-y := -Iinclude/drm + +virtio-gpu-y := virtgpu_drv.o virtgpu_kms.o virtgpu_drm_bus.o virtgpu_gem.o \ + virtgpu_fb.o virtgpu_display.o virtgpu_vq.o virtgpu_ttm.o \ + virtgpu_fence.o virtgpu_object.o virtgpu_debugfs.o virtgpu_plane.o + +obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio-gpu.o diff --git a/drivers/gpu/drm/virtio/virtgpu_debugfs.c b/drivers/gpu/drm/virtio/virtgpu_debugfs.c new file mode 100644 index 000000000000..db8b49101a8b --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_debugfs.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "drmP.h" +#include "virtgpu_drv.h" + +static int +virtio_gpu_debugfs_irq_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct virtio_gpu_device *vgdev = node->minor->dev->dev_private; + + seq_printf(m, "fence %ld %lld\n", + atomic64_read(&vgdev->fence_drv.last_seq), + vgdev->fence_drv.sync_seq); + return 0; +} + +static struct drm_info_list virtio_gpu_debugfs_list[] = { + { "irq_fence", virtio_gpu_debugfs_irq_info, 0, NULL }, +}; + +#define VIRTIO_GPU_DEBUGFS_ENTRIES ARRAY_SIZE(virtio_gpu_debugfs_list) + +int +virtio_gpu_debugfs_init(struct drm_minor *minor) +{ + drm_debugfs_create_files(virtio_gpu_debugfs_list, + VIRTIO_GPU_DEBUGFS_ENTRIES, + minor->debugfs_root, minor); + return 0; +} + +void +virtio_gpu_debugfs_takedown(struct drm_minor *minor) +{ + drm_debugfs_remove_files(virtio_gpu_debugfs_list, + VIRTIO_GPU_DEBUGFS_ENTRIES, + minor); +} diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c b/drivers/gpu/drm/virtio/virtgpu_display.c new file mode 100644 index 000000000000..4e160efc9402 --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_display.c @@ -0,0 +1,473 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Authors: + * Dave Airlie + * Alon Levy + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "virtgpu_drv.h" +#include +#include + +#define XRES_MIN 320 +#define YRES_MIN 200 + +#define XRES_DEF 1024 +#define YRES_DEF 768 + +#define XRES_MAX 8192 +#define YRES_MAX 8192 + +static void virtio_gpu_crtc_gamma_set(struct drm_crtc *crtc, + u16 *red, u16 *green, u16 *blue, + uint32_t start, uint32_t size) +{ + /* TODO */ +} + +static void +virtio_gpu_hide_cursor(struct virtio_gpu_device *vgdev, + struct virtio_gpu_output *output) +{ + output->cursor.hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR); + output->cursor.resource_id = 0; + virtio_gpu_cursor_ping(vgdev, output); +} + +static int virtio_gpu_crtc_cursor_set(struct drm_crtc *crtc, + struct drm_file *file_priv, + uint32_t handle, + uint32_t width, + uint32_t height, + int32_t hot_x, int32_t hot_y) +{ + struct virtio_gpu_device *vgdev = crtc->dev->dev_private; + struct virtio_gpu_output *output = + container_of(crtc, struct virtio_gpu_output, crtc); + struct drm_gem_object *gobj = NULL; + struct virtio_gpu_object *qobj = NULL; + struct virtio_gpu_fence *fence = NULL; + int ret = 0; + + if (handle == 0) { + virtio_gpu_hide_cursor(vgdev, output); + return 0; + } + + /* lookup the cursor */ + gobj = drm_gem_object_lookup(crtc->dev, file_priv, handle); + if (gobj == NULL) + return -ENOENT; + + qobj = gem_to_virtio_gpu_obj(gobj); + + if (!qobj->hw_res_handle) { + ret = -EINVAL; + goto out; + } + + virtio_gpu_cmd_transfer_to_host_2d(vgdev, qobj->hw_res_handle, 0, + cpu_to_le32(64), + cpu_to_le32(64), + 0, 0, &fence); + + output->cursor.hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR); + output->cursor.resource_id = cpu_to_le32(qobj->hw_res_handle); + output->cursor.hot_x = cpu_to_le32(hot_x); + output->cursor.hot_y = cpu_to_le32(hot_y); + virtio_gpu_cursor_ping(vgdev, output); + ret = 0; + +out: + drm_gem_object_unreference_unlocked(gobj); + return ret; +} + +static int virtio_gpu_crtc_cursor_move(struct drm_crtc *crtc, + int x, int y) +{ + struct virtio_gpu_device *vgdev = crtc->dev->dev_private; + struct virtio_gpu_output *output = + container_of(crtc, struct virtio_gpu_output, crtc); + + output->cursor.hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR); + output->cursor.pos.x = cpu_to_le32(x); + output->cursor.pos.y = cpu_to_le32(y); + virtio_gpu_cursor_ping(vgdev, output); + return 0; +} + +static const struct drm_crtc_funcs virtio_gpu_crtc_funcs = { + .cursor_set2 = virtio_gpu_crtc_cursor_set, + .cursor_move = virtio_gpu_crtc_cursor_move, + .gamma_set = virtio_gpu_crtc_gamma_set, + .set_config = drm_atomic_helper_set_config, + .destroy = drm_crtc_cleanup, + +#if 0 /* not (yet) working without vblank support according to docs */ + .page_flip = drm_atomic_helper_page_flip, +#endif + .reset = drm_atomic_helper_crtc_reset, + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, +}; + +static void virtio_gpu_user_framebuffer_destroy(struct drm_framebuffer *fb) +{ + struct virtio_gpu_framebuffer *virtio_gpu_fb + = to_virtio_gpu_framebuffer(fb); + + if (virtio_gpu_fb->obj) + drm_gem_object_unreference_unlocked(virtio_gpu_fb->obj); + drm_framebuffer_cleanup(fb); + kfree(virtio_gpu_fb); +} + +static int +virtio_gpu_framebuffer_surface_dirty(struct drm_framebuffer *fb, + struct drm_file *file_priv, + unsigned flags, unsigned color, + struct drm_clip_rect *clips, + unsigned num_clips) +{ + struct virtio_gpu_framebuffer *virtio_gpu_fb + = to_virtio_gpu_framebuffer(fb); + + return virtio_gpu_surface_dirty(virtio_gpu_fb, clips, num_clips); +} + +static const struct drm_framebuffer_funcs virtio_gpu_fb_funcs = { + .destroy = virtio_gpu_user_framebuffer_destroy, + .dirty = virtio_gpu_framebuffer_surface_dirty, +}; + +int +virtio_gpu_framebuffer_init(struct drm_device *dev, + struct virtio_gpu_framebuffer *vgfb, + struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj) +{ + int ret; + struct virtio_gpu_object *bo; + vgfb->obj = obj; + + bo = gem_to_virtio_gpu_obj(obj); + + ret = drm_framebuffer_init(dev, &vgfb->base, &virtio_gpu_fb_funcs); + if (ret) { + vgfb->obj = NULL; + return ret; + } + drm_helper_mode_fill_fb_struct(&vgfb->base, mode_cmd); + + spin_lock_init(&vgfb->dirty_lock); + vgfb->x1 = vgfb->y1 = INT_MAX; + vgfb->x2 = vgfb->y2 = 0; + return 0; +} + +static bool virtio_gpu_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static void virtio_gpu_crtc_mode_set_nofb(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct virtio_gpu_device *vgdev = dev->dev_private; + struct virtio_gpu_output *output = drm_crtc_to_virtio_gpu_output(crtc); + + virtio_gpu_cmd_set_scanout(vgdev, output->index, 0, + crtc->mode.hdisplay, + crtc->mode.vdisplay, 0, 0); +} + +static void virtio_gpu_crtc_enable(struct drm_crtc *crtc) +{ +} + +static void virtio_gpu_crtc_disable(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct virtio_gpu_device *vgdev = dev->dev_private; + struct virtio_gpu_output *output = drm_crtc_to_virtio_gpu_output(crtc); + + virtio_gpu_cmd_set_scanout(vgdev, output->index, 0, 0, 0, 0, 0); +} + +static int virtio_gpu_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + return 0; +} + +static const struct drm_crtc_helper_funcs virtio_gpu_crtc_helper_funcs = { + .enable = virtio_gpu_crtc_enable, + .disable = virtio_gpu_crtc_disable, + .mode_fixup = virtio_gpu_crtc_mode_fixup, + .mode_set_nofb = virtio_gpu_crtc_mode_set_nofb, + .atomic_check = virtio_gpu_crtc_atomic_check, +}; + +static bool virtio_gpu_enc_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static void virtio_gpu_enc_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ +} + +static void virtio_gpu_enc_enable(struct drm_encoder *encoder) +{ +} + +static void virtio_gpu_enc_disable(struct drm_encoder *encoder) +{ +} + +static int virtio_gpu_conn_get_modes(struct drm_connector *connector) +{ + struct virtio_gpu_output *output = + drm_connector_to_virtio_gpu_output(connector); + struct drm_display_mode *mode = NULL; + int count, width, height; + + width = le32_to_cpu(output->info.r.width); + height = le32_to_cpu(output->info.r.height); + count = drm_add_modes_noedid(connector, XRES_MAX, YRES_MAX); + + if (width == 0 || height == 0) { + width = XRES_DEF; + height = YRES_DEF; + drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF); + } else { + DRM_DEBUG("add mode: %dx%d\n", width, height); + mode = drm_cvt_mode(connector->dev, width, height, 60, + false, false, false); + mode->type |= DRM_MODE_TYPE_PREFERRED; + drm_mode_probed_add(connector, mode); + count++; + } + + return count; +} + +static int virtio_gpu_conn_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct virtio_gpu_output *output = + drm_connector_to_virtio_gpu_output(connector); + int width, height; + + width = le32_to_cpu(output->info.r.width); + height = le32_to_cpu(output->info.r.height); + + if (!(mode->type & DRM_MODE_TYPE_PREFERRED)) + return MODE_OK; + if (mode->hdisplay == XRES_DEF && mode->vdisplay == YRES_DEF) + return MODE_OK; + if (mode->hdisplay <= width && mode->hdisplay >= width - 16 && + mode->vdisplay <= height && mode->vdisplay >= height - 16) + return MODE_OK; + + DRM_DEBUG("del mode: %dx%d\n", mode->hdisplay, mode->vdisplay); + return MODE_BAD; +} + +static struct drm_encoder* +virtio_gpu_best_encoder(struct drm_connector *connector) +{ + struct virtio_gpu_output *virtio_gpu_output = + drm_connector_to_virtio_gpu_output(connector); + + return &virtio_gpu_output->enc; +} + +static const struct drm_encoder_helper_funcs virtio_gpu_enc_helper_funcs = { + .mode_fixup = virtio_gpu_enc_mode_fixup, + .mode_set = virtio_gpu_enc_mode_set, + .enable = virtio_gpu_enc_enable, + .disable = virtio_gpu_enc_disable, +}; + +static const struct drm_connector_helper_funcs virtio_gpu_conn_helper_funcs = { + .get_modes = virtio_gpu_conn_get_modes, + .mode_valid = virtio_gpu_conn_mode_valid, + .best_encoder = virtio_gpu_best_encoder, +}; + +static void virtio_gpu_conn_save(struct drm_connector *connector) +{ + DRM_DEBUG("\n"); +} + +static void virtio_gpu_conn_restore(struct drm_connector *connector) +{ + DRM_DEBUG("\n"); +} + +static enum drm_connector_status virtio_gpu_conn_detect( + struct drm_connector *connector, + bool force) +{ + struct virtio_gpu_output *output = + drm_connector_to_virtio_gpu_output(connector); + + if (output->info.enabled) + return connector_status_connected; + else + return connector_status_disconnected; +} + +static void virtio_gpu_conn_destroy(struct drm_connector *connector) +{ + struct virtio_gpu_output *virtio_gpu_output = + drm_connector_to_virtio_gpu_output(connector); + + drm_connector_unregister(connector); + drm_connector_cleanup(connector); + kfree(virtio_gpu_output); +} + +static const struct drm_connector_funcs virtio_gpu_connector_funcs = { + .dpms = drm_atomic_helper_connector_dpms, + .save = virtio_gpu_conn_save, + .restore = virtio_gpu_conn_restore, + .detect = virtio_gpu_conn_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = virtio_gpu_conn_destroy, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_encoder_funcs virtio_gpu_enc_funcs = { + .destroy = drm_encoder_cleanup, +}; + +static int vgdev_output_init(struct virtio_gpu_device *vgdev, int index) +{ + struct drm_device *dev = vgdev->ddev; + struct virtio_gpu_output *output = vgdev->outputs + index; + struct drm_connector *connector = &output->conn; + struct drm_encoder *encoder = &output->enc; + struct drm_crtc *crtc = &output->crtc; + struct drm_plane *plane; + + output->index = index; + if (index == 0) { + output->info.enabled = cpu_to_le32(true); + output->info.r.width = cpu_to_le32(XRES_DEF); + output->info.r.height = cpu_to_le32(YRES_DEF); + } + + plane = virtio_gpu_plane_init(vgdev, index); + if (IS_ERR(plane)) + return PTR_ERR(plane); + drm_crtc_init_with_planes(dev, crtc, plane, NULL, + &virtio_gpu_crtc_funcs); + drm_mode_crtc_set_gamma_size(crtc, 256); + drm_crtc_helper_add(crtc, &virtio_gpu_crtc_helper_funcs); + plane->crtc = crtc; + + drm_connector_init(dev, connector, &virtio_gpu_connector_funcs, + DRM_MODE_CONNECTOR_VIRTUAL); + drm_connector_helper_add(connector, &virtio_gpu_conn_helper_funcs); + + drm_encoder_init(dev, encoder, &virtio_gpu_enc_funcs, + DRM_MODE_ENCODER_VIRTUAL); + drm_encoder_helper_add(encoder, &virtio_gpu_enc_helper_funcs); + encoder->possible_crtcs = 1 << index; + + drm_mode_connector_attach_encoder(connector, encoder); + drm_connector_register(connector); + return 0; +} + +static struct drm_framebuffer * +virtio_gpu_user_framebuffer_create(struct drm_device *dev, + struct drm_file *file_priv, + struct drm_mode_fb_cmd2 *mode_cmd) +{ + struct drm_gem_object *obj = NULL; + struct virtio_gpu_framebuffer *virtio_gpu_fb; + int ret; + + /* lookup object associated with res handle */ + obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); + if (!obj) + return ERR_PTR(-EINVAL); + + virtio_gpu_fb = kzalloc(sizeof(*virtio_gpu_fb), GFP_KERNEL); + if (virtio_gpu_fb == NULL) + return ERR_PTR(-ENOMEM); + + ret = virtio_gpu_framebuffer_init(dev, virtio_gpu_fb, mode_cmd, obj); + if (ret) { + kfree(virtio_gpu_fb); + if (obj) + drm_gem_object_unreference_unlocked(obj); + return NULL; + } + + return &virtio_gpu_fb->base; +} + +static const struct drm_mode_config_funcs virtio_gpu_mode_funcs = { + .fb_create = virtio_gpu_user_framebuffer_create, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, +}; + +int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev) +{ + int i; + + drm_mode_config_init(vgdev->ddev); + vgdev->ddev->mode_config.funcs = (void *)&virtio_gpu_mode_funcs; + + /* modes will be validated against the framebuffer size */ + vgdev->ddev->mode_config.min_width = XRES_MIN; + vgdev->ddev->mode_config.min_height = YRES_MIN; + vgdev->ddev->mode_config.max_width = XRES_MAX; + vgdev->ddev->mode_config.max_height = YRES_MAX; + + for (i = 0 ; i < vgdev->num_scanouts; ++i) + vgdev_output_init(vgdev, i); + + drm_mode_config_reset(vgdev->ddev); + return 0; +} + +void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev) +{ + virtio_gpu_fbdev_fini(vgdev); + drm_mode_config_cleanup(vgdev->ddev); +} diff --git a/drivers/gpu/drm/virtio/virtgpu_drm_bus.c b/drivers/gpu/drm/virtio/virtgpu_drm_bus.c new file mode 100644 index 000000000000..f4ec816e9468 --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_drm_bus.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "virtgpu_drv.h" + +int drm_virtio_set_busid(struct drm_device *dev, struct drm_master *master) +{ + struct pci_dev *pdev = dev->pdev; + + if (pdev) { + return drm_pci_set_busid(dev, master); + } + return 0; +} + +int drm_virtio_init(struct drm_driver *driver, struct virtio_device *vdev) +{ + struct drm_device *dev; + int ret; + + dev = drm_dev_alloc(driver, &vdev->dev); + if (!dev) + return -ENOMEM; + dev->virtdev = vdev; + vdev->priv = dev; + + if (strcmp(vdev->dev.parent->bus->name, "pci") == 0) { + struct pci_dev *pdev = to_pci_dev(vdev->dev.parent); + bool vga = (pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA; + + if (vga) { + /* + * Need to make sure we don't have two drivers + * for the same hardware here. Some day we + * will simply kick out the firmware + * (vesa/efi) framebuffer. + * + * Virtual hardware specs for virtio-vga are + * not finalized yet, therefore we can't add + * code for that yet. + * + * So ignore the device for the time being, + * and suggest to the user use the device + * variant without vga compatibility mode. + */ + DRM_ERROR("virtio-vga not (yet) supported\n"); + DRM_ERROR("please use virtio-gpu-pci instead\n"); + ret = -ENODEV; + goto err_free; + } + dev->pdev = pdev; + } + + ret = drm_dev_register(dev, 0); + if (ret) + goto err_free; + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", driver->name, + driver->major, driver->minor, driver->patchlevel, + driver->date, dev->primary->index); + + return 0; + +err_free: + drm_dev_unref(dev); + return ret; +} diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.c b/drivers/gpu/drm/virtio/virtgpu_drv.c new file mode 100644 index 000000000000..7d9610aaeff9 --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_drv.c @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Authors: + * Dave Airlie + * Gerd Hoffmann + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include "drmP.h" +#include "drm/drm.h" + +#include "virtgpu_drv.h" +static struct drm_driver driver; + +static int virtio_gpu_modeset = -1; + +MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); +module_param_named(modeset, virtio_gpu_modeset, int, 0400); + +static int virtio_gpu_probe(struct virtio_device *vdev) +{ +#ifdef CONFIG_VGA_CONSOLE + if (vgacon_text_force() && virtio_gpu_modeset == -1) + return -EINVAL; +#endif + + if (virtio_gpu_modeset == 0) + return -EINVAL; + + return drm_virtio_init(&driver, vdev); +} + +static void virtio_gpu_remove(struct virtio_device *vdev) +{ + struct drm_device *dev = vdev->priv; + drm_put_dev(dev); +} + +static void virtio_gpu_config_changed(struct virtio_device *vdev) +{ + struct drm_device *dev = vdev->priv; + struct virtio_gpu_device *vgdev = dev->dev_private; + + schedule_work(&vgdev->config_changed_work); +} + +static struct virtio_device_id id_table[] = { + { VIRTIO_ID_GPU, VIRTIO_DEV_ANY_ID }, + { 0 }, +}; + +static unsigned int features[] = { +}; +static struct virtio_driver virtio_gpu_driver = { + .feature_table = features, + .feature_table_size = ARRAY_SIZE(features), + .driver.name = KBUILD_MODNAME, + .driver.owner = THIS_MODULE, + .id_table = id_table, + .probe = virtio_gpu_probe, + .remove = virtio_gpu_remove, + .config_changed = virtio_gpu_config_changed +}; + +module_virtio_driver(virtio_gpu_driver); + +MODULE_DEVICE_TABLE(virtio, id_table); +MODULE_DESCRIPTION("Virtio GPU driver"); +MODULE_LICENSE("GPL and additional rights"); +MODULE_AUTHOR("Dave Airlie "); +MODULE_AUTHOR("Gerd Hoffmann "); +MODULE_AUTHOR("Alon Levy"); + +static const struct file_operations virtio_gpu_driver_fops = { + .owner = THIS_MODULE, + .open = drm_open, + .mmap = virtio_gpu_mmap, + .poll = drm_poll, + .read = drm_read, + .unlocked_ioctl = drm_ioctl, + .release = drm_release, +#ifdef CONFIG_COMPAT + .compat_ioctl = drm_compat_ioctl, +#endif + .llseek = noop_llseek, +}; + + +static struct drm_driver driver = { + .driver_features = DRIVER_MODESET | DRIVER_GEM, + .set_busid = drm_virtio_set_busid, + .load = virtio_gpu_driver_load, + .unload = virtio_gpu_driver_unload, + + .dumb_create = virtio_gpu_mode_dumb_create, + .dumb_map_offset = virtio_gpu_mode_dumb_mmap, + .dumb_destroy = virtio_gpu_mode_dumb_destroy, + +#if defined(CONFIG_DEBUG_FS) + .debugfs_init = virtio_gpu_debugfs_init, + .debugfs_cleanup = virtio_gpu_debugfs_takedown, +#endif + + .gem_free_object = virtio_gpu_gem_free_object, + .fops = &virtio_gpu_driver_fops, + + .name = DRIVER_NAME, + .desc = DRIVER_DESC, + .date = DRIVER_DATE, + .major = DRIVER_MAJOR, + .minor = DRIVER_MINOR, + .patchlevel = DRIVER_PATCHLEVEL, +}; diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h b/drivers/gpu/drm/virtio/virtgpu_drv.h new file mode 100644 index 000000000000..e5a2c092460b --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_drv.h @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VIRTIO_DRV_H +#define VIRTIO_DRV_H + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "virtio_gpu" +#define DRIVER_DESC "virtio GPU" +#define DRIVER_DATE "0" + +#define DRIVER_MAJOR 0 +#define DRIVER_MINOR 0 +#define DRIVER_PATCHLEVEL 1 + +/* virtgpu_drm_bus.c */ +int drm_virtio_set_busid(struct drm_device *dev, struct drm_master *master); +int drm_virtio_init(struct drm_driver *driver, struct virtio_device *vdev); + +struct virtio_gpu_object { + struct drm_gem_object gem_base; + uint32_t hw_res_handle; + + struct sg_table *pages; + void *vmap; + bool dumb; + struct ttm_place placement_code; + struct ttm_placement placement; + struct ttm_buffer_object tbo; + struct ttm_bo_kmap_obj kmap; +}; +#define gem_to_virtio_gpu_obj(gobj) \ + container_of((gobj), struct virtio_gpu_object, gem_base) + +struct virtio_gpu_vbuffer; +struct virtio_gpu_device; + +typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer *vbuf); + +struct virtio_gpu_fence_driver { + atomic64_t last_seq; + uint64_t sync_seq; + struct list_head fences; + spinlock_t lock; +}; + +struct virtio_gpu_fence { + struct fence f; + struct virtio_gpu_fence_driver *drv; + struct list_head node; + uint64_t seq; +}; +#define to_virtio_fence(x) \ + container_of(x, struct virtio_gpu_fence, f) + +struct virtio_gpu_vbuffer { + char *buf; + int size; + + void *data_buf; + uint32_t data_size; + + char *resp_buf; + int resp_size; + + virtio_gpu_resp_cb resp_cb; + + struct list_head list; +}; + +struct virtio_gpu_output { + int index; + struct drm_crtc crtc; + struct drm_connector conn; + struct drm_encoder enc; + struct virtio_gpu_display_one info; + struct virtio_gpu_update_cursor cursor; + int cur_x; + int cur_y; +}; +#define drm_crtc_to_virtio_gpu_output(x) \ + container_of(x, struct virtio_gpu_output, crtc) +#define drm_connector_to_virtio_gpu_output(x) \ + container_of(x, struct virtio_gpu_output, conn) +#define drm_encoder_to_virtio_gpu_output(x) \ + container_of(x, struct virtio_gpu_output, enc) + +struct virtio_gpu_framebuffer { + struct drm_framebuffer base; + struct drm_gem_object *obj; + int x1, y1, x2, y2; /* dirty rect */ + spinlock_t dirty_lock; + uint32_t hw_res_handle; +}; +#define to_virtio_gpu_framebuffer(x) \ + container_of(x, struct virtio_gpu_framebuffer, base) + +struct virtio_gpu_mman { + struct ttm_bo_global_ref bo_global_ref; + struct drm_global_reference mem_global_ref; + bool mem_global_referenced; + struct ttm_bo_device bdev; +}; + +struct virtio_gpu_fbdev; + +struct virtio_gpu_queue { + struct virtqueue *vq; + spinlock_t qlock; + wait_queue_head_t ack_queue; + struct work_struct dequeue_work; +}; + +struct virtio_gpu_device { + struct device *dev; + struct drm_device *ddev; + + struct virtio_device *vdev; + + struct virtio_gpu_mman mman; + + /* pointer to fbdev info structure */ + struct virtio_gpu_fbdev *vgfbdev; + struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS]; + uint32_t num_scanouts; + + struct virtio_gpu_queue ctrlq; + struct virtio_gpu_queue cursorq; + struct list_head free_vbufs; + void *vbufs; + bool vqs_ready; + + struct idr resource_idr; + spinlock_t resource_idr_lock; + + wait_queue_head_t resp_wq; + /* current display info */ + spinlock_t display_info_lock; + + struct virtio_gpu_fence_driver fence_drv; + + struct idr ctx_id_idr; + spinlock_t ctx_id_idr_lock; + + struct work_struct config_changed_work; +}; + +struct virtio_gpu_fpriv { + uint32_t ctx_id; +}; + +/* virtio_ioctl.c */ +#define DRM_VIRTIO_NUM_IOCTLS 10 +extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS]; + +/* virtio_kms.c */ +int virtio_gpu_driver_load(struct drm_device *dev, unsigned long flags); +int virtio_gpu_driver_unload(struct drm_device *dev); + +/* virtio_gem.c */ +void virtio_gpu_gem_free_object(struct drm_gem_object *gem_obj); +int virtio_gpu_gem_init(struct virtio_gpu_device *vgdev); +void virtio_gpu_gem_fini(struct virtio_gpu_device *vgdev); +int virtio_gpu_gem_create(struct drm_file *file, + struct drm_device *dev, + uint64_t size, + struct drm_gem_object **obj_p, + uint32_t *handle_p); +struct virtio_gpu_object *virtio_gpu_alloc_object(struct drm_device *dev, + size_t size, bool kernel, + bool pinned); +int virtio_gpu_mode_dumb_create(struct drm_file *file_priv, + struct drm_device *dev, + struct drm_mode_create_dumb *args); +int virtio_gpu_mode_dumb_destroy(struct drm_file *file_priv, + struct drm_device *dev, + uint32_t handle); +int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv, + struct drm_device *dev, + uint32_t handle, uint64_t *offset_p); + +/* virtio_fb */ +#define VIRTIO_GPUFB_CONN_LIMIT 1 +int virtio_gpu_fbdev_init(struct virtio_gpu_device *vgdev); +void virtio_gpu_fbdev_fini(struct virtio_gpu_device *vgdev); +int virtio_gpu_surface_dirty(struct virtio_gpu_framebuffer *qfb, + struct drm_clip_rect *clips, + unsigned num_clips); +/* virtio vg */ +int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev); +void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev); +void virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev, + uint32_t *resid); +void virtio_gpu_resource_id_put(struct virtio_gpu_device *vgdev, uint32_t id); +void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev, + uint32_t resource_id, + uint32_t format, + uint32_t width, + uint32_t height); +void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev, + uint32_t resource_id); +void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev, + uint32_t resource_id, uint64_t offset, + __le32 width, __le32 height, + __le32 x, __le32 y, + struct virtio_gpu_fence **fence); +void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev, + uint32_t resource_id, + uint32_t x, uint32_t y, + uint32_t width, uint32_t height); +void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev, + uint32_t scanout_id, uint32_t resource_id, + uint32_t width, uint32_t height, + uint32_t x, uint32_t y); +int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev, + struct virtio_gpu_object *obj, + uint32_t resource_id, + struct virtio_gpu_fence **fence); +int virtio_gpu_attach_status_page(struct virtio_gpu_device *vgdev); +int virtio_gpu_detach_status_page(struct virtio_gpu_device *vgdev); +void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev, + struct virtio_gpu_output *output); +int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev); +void virtio_gpu_cmd_resource_inval_backing(struct virtio_gpu_device *vgdev, + uint32_t resource_id); +void virtio_gpu_ctrl_ack(struct virtqueue *vq); +void virtio_gpu_cursor_ack(struct virtqueue *vq); +void virtio_gpu_dequeue_ctrl_func(struct work_struct *work); +void virtio_gpu_dequeue_cursor_func(struct work_struct *work); + +/* virtio_gpu_display.c */ +int virtio_gpu_framebuffer_init(struct drm_device *dev, + struct virtio_gpu_framebuffer *vgfb, + struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj); +int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev); +void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev); + +/* virtio_gpu_plane.c */ +struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev, + int index); + +/* virtio_gpu_ttm.c */ +int virtio_gpu_ttm_init(struct virtio_gpu_device *vgdev); +void virtio_gpu_ttm_fini(struct virtio_gpu_device *vgdev); +int virtio_gpu_mmap(struct file *filp, struct vm_area_struct *vma); + +/* virtio_gpu_fence.c */ +int virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev, + struct virtio_gpu_ctrl_hdr *cmd_hdr, + struct virtio_gpu_fence **fence); +void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev, + u64 last_seq); + +/* virtio_gpu_object */ +int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, + unsigned long size, bool kernel, bool pinned, + struct virtio_gpu_object **bo_ptr); +int virtio_gpu_object_kmap(struct virtio_gpu_object *bo, void **ptr); +int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev, + struct virtio_gpu_object *bo); +void virtio_gpu_object_free_sg_table(struct virtio_gpu_object *bo); +int virtio_gpu_object_wait(struct virtio_gpu_object *bo, bool no_wait); + +static inline struct virtio_gpu_object* +virtio_gpu_object_ref(struct virtio_gpu_object *bo) +{ + ttm_bo_reference(&bo->tbo); + return bo; +} + +static inline void virtio_gpu_object_unref(struct virtio_gpu_object **bo) +{ + struct ttm_buffer_object *tbo; + + if ((*bo) == NULL) + return; + tbo = &((*bo)->tbo); + ttm_bo_unref(&tbo); + if (tbo == NULL) + *bo = NULL; +} + +static inline u64 virtio_gpu_object_mmap_offset(struct virtio_gpu_object *bo) +{ + return drm_vma_node_offset_addr(&bo->tbo.vma_node); +} + +static inline int virtio_gpu_object_reserve(struct virtio_gpu_object *bo, + bool no_wait) +{ + int r; + + r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL); + if (unlikely(r != 0)) { + if (r != -ERESTARTSYS) { + struct virtio_gpu_device *qdev = + bo->gem_base.dev->dev_private; + dev_err(qdev->dev, "%p reserve failed\n", bo); + } + return r; + } + return 0; +} + +static inline void virtio_gpu_object_unreserve(struct virtio_gpu_object *bo) +{ + ttm_bo_unreserve(&bo->tbo); +} + +/* virgl debufs */ +int virtio_gpu_debugfs_init(struct drm_minor *minor); +void virtio_gpu_debugfs_takedown(struct drm_minor *minor); + +#endif diff --git a/drivers/gpu/drm/virtio/virtgpu_fb.c b/drivers/gpu/drm/virtio/virtgpu_fb.c new file mode 100644 index 000000000000..25bf333d5a45 --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_fb.c @@ -0,0 +1,431 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "virtgpu_drv.h" + +#define VIRTIO_GPU_FBCON_POLL_PERIOD (HZ / 60) + +struct virtio_gpu_fbdev { + struct drm_fb_helper helper; + struct virtio_gpu_framebuffer vgfb; + struct list_head fbdev_list; + struct virtio_gpu_device *vgdev; + struct delayed_work work; +}; + +static int virtio_gpu_dirty_update(struct virtio_gpu_framebuffer *fb, + bool store, int x, int y, + int width, int height) +{ + struct drm_device *dev = fb->base.dev; + struct virtio_gpu_device *vgdev = dev->dev_private; + bool store_for_later = false; + int bpp = fb->base.bits_per_pixel / 8; + int x2, y2; + unsigned long flags; + struct virtio_gpu_object *obj = gem_to_virtio_gpu_obj(fb->obj); + + if ((width <= 0) || + (x + width > fb->base.width) || + (y + height > fb->base.height)) { + DRM_DEBUG("values out of range %dx%d+%d+%d, fb %dx%d\n", + width, height, x, y, + fb->base.width, fb->base.height); + return -EINVAL; + } + + /* + * Can be called with pretty much any context (console output + * path). If we are in atomic just store the dirty rect info + * to send out the update later. + * + * Can't test inside spin lock. + */ + if (in_atomic() || store) + store_for_later = true; + + x2 = x + width - 1; + y2 = y + height - 1; + + spin_lock_irqsave(&fb->dirty_lock, flags); + + if (fb->y1 < y) + y = fb->y1; + if (fb->y2 > y2) + y2 = fb->y2; + if (fb->x1 < x) + x = fb->x1; + if (fb->x2 > x2) + x2 = fb->x2; + + if (store_for_later) { + fb->x1 = x; + fb->x2 = x2; + fb->y1 = y; + fb->y2 = y2; + spin_unlock_irqrestore(&fb->dirty_lock, flags); + return 0; + } + + fb->x1 = fb->y1 = INT_MAX; + fb->x2 = fb->y2 = 0; + + spin_unlock_irqrestore(&fb->dirty_lock, flags); + + { + uint32_t offset; + uint32_t w = x2 - x + 1; + uint32_t h = y2 - y + 1; + + offset = (y * fb->base.pitches[0]) + x * bpp; + + virtio_gpu_cmd_transfer_to_host_2d(vgdev, obj->hw_res_handle, + offset, + cpu_to_le32(w), + cpu_to_le32(h), + cpu_to_le32(x), + cpu_to_le32(y), + NULL); + + } + virtio_gpu_cmd_resource_flush(vgdev, obj->hw_res_handle, + x, y, x2 - x + 1, y2 - y + 1); + return 0; +} + +int virtio_gpu_surface_dirty(struct virtio_gpu_framebuffer *vgfb, + struct drm_clip_rect *clips, + unsigned num_clips) +{ + struct virtio_gpu_device *vgdev = vgfb->base.dev->dev_private; + struct virtio_gpu_object *obj = gem_to_virtio_gpu_obj(vgfb->obj); + struct drm_clip_rect norect; + struct drm_clip_rect *clips_ptr; + int left, right, top, bottom; + int i; + int inc = 1; + if (!num_clips) { + num_clips = 1; + clips = &norect; + norect.x1 = norect.y1 = 0; + norect.x2 = vgfb->base.width; + norect.y2 = vgfb->base.height; + } + left = clips->x1; + right = clips->x2; + top = clips->y1; + bottom = clips->y2; + + /* skip the first clip rect */ + for (i = 1, clips_ptr = clips + inc; + i < num_clips; i++, clips_ptr += inc) { + left = min_t(int, left, (int)clips_ptr->x1); + right = max_t(int, right, (int)clips_ptr->x2); + top = min_t(int, top, (int)clips_ptr->y1); + bottom = max_t(int, bottom, (int)clips_ptr->y2); + } + + if (obj->dumb) + return virtio_gpu_dirty_update(vgfb, false, left, top, + right - left, bottom - top); + + virtio_gpu_cmd_resource_flush(vgdev, obj->hw_res_handle, + left, top, right - left, bottom - top); + return 0; +} + +static void virtio_gpu_fb_dirty_work(struct work_struct *work) +{ + struct delayed_work *delayed_work = to_delayed_work(work); + struct virtio_gpu_fbdev *vfbdev = + container_of(delayed_work, struct virtio_gpu_fbdev, work); + struct virtio_gpu_framebuffer *vgfb = &vfbdev->vgfb; + + virtio_gpu_dirty_update(&vfbdev->vgfb, false, vgfb->x1, vgfb->y1, + vgfb->x2 - vgfb->x1, vgfb->y2 - vgfb->y1); +} + +static void virtio_gpu_3d_fillrect(struct fb_info *info, + const struct fb_fillrect *rect) +{ + struct virtio_gpu_fbdev *vfbdev = info->par; + sys_fillrect(info, rect); + virtio_gpu_dirty_update(&vfbdev->vgfb, true, rect->dx, rect->dy, + rect->width, rect->height); + schedule_delayed_work(&vfbdev->work, VIRTIO_GPU_FBCON_POLL_PERIOD); +} + +static void virtio_gpu_3d_copyarea(struct fb_info *info, + const struct fb_copyarea *area) +{ + struct virtio_gpu_fbdev *vfbdev = info->par; + sys_copyarea(info, area); + virtio_gpu_dirty_update(&vfbdev->vgfb, true, area->dx, area->dy, + area->width, area->height); + schedule_delayed_work(&vfbdev->work, VIRTIO_GPU_FBCON_POLL_PERIOD); +} + +static void virtio_gpu_3d_imageblit(struct fb_info *info, + const struct fb_image *image) +{ + struct virtio_gpu_fbdev *vfbdev = info->par; + sys_imageblit(info, image); + virtio_gpu_dirty_update(&vfbdev->vgfb, true, image->dx, image->dy, + image->width, image->height); + schedule_delayed_work(&vfbdev->work, VIRTIO_GPU_FBCON_POLL_PERIOD); +} + +static struct fb_ops virtio_gpufb_ops = { + .owner = THIS_MODULE, + .fb_check_var = drm_fb_helper_check_var, + .fb_set_par = drm_fb_helper_set_par, /* TODO: copy vmwgfx */ + .fb_fillrect = virtio_gpu_3d_fillrect, + .fb_copyarea = virtio_gpu_3d_copyarea, + .fb_imageblit = virtio_gpu_3d_imageblit, + .fb_pan_display = drm_fb_helper_pan_display, + .fb_blank = drm_fb_helper_blank, + .fb_setcmap = drm_fb_helper_setcmap, + .fb_debug_enter = drm_fb_helper_debug_enter, + .fb_debug_leave = drm_fb_helper_debug_leave, +}; + +static int virtio_gpu_vmap_fb(struct virtio_gpu_device *vgdev, + struct virtio_gpu_object *obj) +{ + return virtio_gpu_object_kmap(obj, NULL); +} + +static int virtio_gpufb_create(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes) +{ + struct virtio_gpu_fbdev *vfbdev = + container_of(helper, struct virtio_gpu_fbdev, helper); + struct drm_device *dev = helper->dev; + struct virtio_gpu_device *vgdev = dev->dev_private; + struct fb_info *info; + struct drm_framebuffer *fb; + struct drm_mode_fb_cmd2 mode_cmd = {}; + struct virtio_gpu_object *obj; + struct device *device = vgdev->dev; + uint32_t resid, format, size; + int ret; + + mode_cmd.width = sizes->surface_width; + mode_cmd.height = sizes->surface_height; + mode_cmd.pitches[0] = mode_cmd.width * 4; + mode_cmd.pixel_format = drm_mode_legacy_fb_format(32, 24); + + switch (mode_cmd.pixel_format) { +#ifdef __BIG_ENDIAN + case DRM_FORMAT_XRGB8888: + format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM; + break; + case DRM_FORMAT_ARGB8888: + format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM; + break; + case DRM_FORMAT_BGRX8888: + format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM; + break; + case DRM_FORMAT_BGRA8888: + format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM; + break; + case DRM_FORMAT_RGBX8888: + format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM; + break; + case DRM_FORMAT_RGBA8888: + format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM; + break; + case DRM_FORMAT_XBGR8888: + format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM; + break; + case DRM_FORMAT_ABGR8888: + format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM; + break; +#else + case DRM_FORMAT_XRGB8888: + format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM; + break; + case DRM_FORMAT_ARGB8888: + format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM; + break; + case DRM_FORMAT_BGRX8888: + format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM; + break; + case DRM_FORMAT_BGRA8888: + format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM; + break; + case DRM_FORMAT_RGBX8888: + format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM; + break; + case DRM_FORMAT_RGBA8888: + format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM; + break; + case DRM_FORMAT_XBGR8888: + format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM; + break; + case DRM_FORMAT_ABGR8888: + format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM; + break; +#endif + default: + DRM_ERROR("failed to find virtio gpu format for %d\n", + mode_cmd.pixel_format); + return -EINVAL; + } + + size = mode_cmd.pitches[0] * mode_cmd.height; + obj = virtio_gpu_alloc_object(dev, size, false, true); + if (!obj) + return -ENOMEM; + + virtio_gpu_resource_id_get(vgdev, &resid); + virtio_gpu_cmd_create_resource(vgdev, resid, format, + mode_cmd.width, mode_cmd.height); + + ret = virtio_gpu_vmap_fb(vgdev, obj); + if (ret) { + DRM_ERROR("failed to vmap fb %d\n", ret); + goto err_obj_vmap; + } + + /* attach the object to the resource */ + ret = virtio_gpu_object_attach(vgdev, obj, resid, NULL); + if (ret) + goto err_obj_attach; + + info = framebuffer_alloc(0, device); + if (!info) { + ret = -ENOMEM; + goto err_fb_alloc; + } + + ret = fb_alloc_cmap(&info->cmap, 256, 0); + if (ret) { + ret = -ENOMEM; + goto err_fb_alloc_cmap; + } + + info->par = helper; + + ret = virtio_gpu_framebuffer_init(dev, &vfbdev->vgfb, + &mode_cmd, &obj->gem_base); + if (ret) + goto err_fb_init; + + fb = &vfbdev->vgfb.base; + + vfbdev->helper.fb = fb; + vfbdev->helper.fbdev = info; + + strcpy(info->fix.id, "virtiodrmfb"); + info->flags = FBINFO_DEFAULT; + info->fbops = &virtio_gpufb_ops; + info->pixmap.flags = FB_PIXMAP_SYSTEM; + + info->screen_base = obj->vmap; + info->screen_size = obj->gem_base.size; + drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); + drm_fb_helper_fill_var(info, &vfbdev->helper, + sizes->fb_width, sizes->fb_height); + + info->fix.mmio_start = 0; + info->fix.mmio_len = 0; + return 0; + +err_fb_init: + fb_dealloc_cmap(&info->cmap); +err_fb_alloc_cmap: + framebuffer_release(info); +err_fb_alloc: + virtio_gpu_cmd_resource_inval_backing(vgdev, resid); +err_obj_attach: +err_obj_vmap: + virtio_gpu_gem_free_object(&obj->gem_base); + return ret; +} + +static int virtio_gpu_fbdev_destroy(struct drm_device *dev, + struct virtio_gpu_fbdev *vgfbdev) +{ + struct fb_info *info; + struct virtio_gpu_framebuffer *vgfb = &vgfbdev->vgfb; + + if (vgfbdev->helper.fbdev) { + info = vgfbdev->helper.fbdev; + + unregister_framebuffer(info); + framebuffer_release(info); + } + if (vgfb->obj) + vgfb->obj = NULL; + drm_fb_helper_fini(&vgfbdev->helper); + drm_framebuffer_cleanup(&vgfb->base); + + return 0; +} +static struct drm_fb_helper_funcs virtio_gpu_fb_helper_funcs = { + .fb_probe = virtio_gpufb_create, +}; + +int virtio_gpu_fbdev_init(struct virtio_gpu_device *vgdev) +{ + struct virtio_gpu_fbdev *vgfbdev; + int bpp_sel = 32; /* TODO: parameter from somewhere? */ + int ret; + + vgfbdev = kzalloc(sizeof(struct virtio_gpu_fbdev), GFP_KERNEL); + if (!vgfbdev) + return -ENOMEM; + + vgfbdev->vgdev = vgdev; + vgdev->vgfbdev = vgfbdev; + INIT_DELAYED_WORK(&vgfbdev->work, virtio_gpu_fb_dirty_work); + + drm_fb_helper_prepare(vgdev->ddev, &vgfbdev->helper, + &virtio_gpu_fb_helper_funcs); + ret = drm_fb_helper_init(vgdev->ddev, &vgfbdev->helper, + vgdev->num_scanouts, + VIRTIO_GPUFB_CONN_LIMIT); + if (ret) { + kfree(vgfbdev); + return ret; + } + + drm_fb_helper_single_add_all_connectors(&vgfbdev->helper); + drm_fb_helper_initial_config(&vgfbdev->helper, bpp_sel); + return 0; +} + +void virtio_gpu_fbdev_fini(struct virtio_gpu_device *vgdev) +{ + if (!vgdev->vgfbdev) + return; + + virtio_gpu_fbdev_destroy(vgdev->ddev, vgdev->vgfbdev); + kfree(vgdev->vgfbdev); + vgdev->vgfbdev = NULL; +} diff --git a/drivers/gpu/drm/virtio/virtgpu_fence.c b/drivers/gpu/drm/virtio/virtgpu_fence.c new file mode 100644 index 000000000000..1da632631dac --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_fence.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "virtgpu_drv.h" + +static const char *virtio_get_driver_name(struct fence *f) +{ + return "virtio_gpu"; +} + +static const char *virtio_get_timeline_name(struct fence *f) +{ + return "controlq"; +} + +static bool virtio_enable_signaling(struct fence *f) +{ + return true; +} + +static bool virtio_signaled(struct fence *f) +{ + struct virtio_gpu_fence *fence = to_virtio_fence(f); + + if (atomic64_read(&fence->drv->last_seq) >= fence->seq) + return true; + return false; +} + +static void virtio_fence_value_str(struct fence *f, char *str, int size) +{ + struct virtio_gpu_fence *fence = to_virtio_fence(f); + + snprintf(str, size, "%llu", fence->seq); +} + +static void virtio_timeline_value_str(struct fence *f, char *str, int size) +{ + struct virtio_gpu_fence *fence = to_virtio_fence(f); + + snprintf(str, size, "%lu", atomic64_read(&fence->drv->last_seq)); +} + +static const struct fence_ops virtio_fence_ops = { + .get_driver_name = virtio_get_driver_name, + .get_timeline_name = virtio_get_timeline_name, + .enable_signaling = virtio_enable_signaling, + .signaled = virtio_signaled, + .wait = fence_default_wait, + .fence_value_str = virtio_fence_value_str, + .timeline_value_str = virtio_timeline_value_str, +}; + +int virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev, + struct virtio_gpu_ctrl_hdr *cmd_hdr, + struct virtio_gpu_fence **fence) +{ + struct virtio_gpu_fence_driver *drv = &vgdev->fence_drv; + unsigned long irq_flags; + + *fence = kmalloc(sizeof(struct virtio_gpu_fence), GFP_KERNEL); + if ((*fence) == NULL) + return -ENOMEM; + + spin_lock_irqsave(&drv->lock, irq_flags); + (*fence)->drv = drv; + (*fence)->seq = ++drv->sync_seq; + fence_init(&(*fence)->f, &virtio_fence_ops, &drv->lock, + 0, (*fence)->seq); + fence_get(&(*fence)->f); + list_add_tail(&(*fence)->node, &drv->fences); + spin_unlock_irqrestore(&drv->lock, irq_flags); + + cmd_hdr->flags |= cpu_to_le32(VIRTIO_GPU_FLAG_FENCE); + cmd_hdr->fence_id = cpu_to_le64((*fence)->seq); + return 0; +} + +void virtio_gpu_fence_event_process(struct virtio_gpu_device *vgdev, + u64 last_seq) +{ + struct virtio_gpu_fence_driver *drv = &vgdev->fence_drv; + struct virtio_gpu_fence *fence, *tmp; + unsigned long irq_flags; + + spin_lock_irqsave(&drv->lock, irq_flags); + atomic64_set(&vgdev->fence_drv.last_seq, last_seq); + list_for_each_entry_safe(fence, tmp, &drv->fences, node) { + if (last_seq < fence->seq) + continue; + fence_signal_locked(&fence->f); + list_del(&fence->node); + fence_put(&fence->f); + } + spin_unlock_irqrestore(&drv->lock, irq_flags); +} diff --git a/drivers/gpu/drm/virtio/virtgpu_gem.c b/drivers/gpu/drm/virtio/virtgpu_gem.c new file mode 100644 index 000000000000..cfa0d27150bd --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_gem.c @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "virtgpu_drv.h" + +void virtio_gpu_gem_free_object(struct drm_gem_object *gem_obj) +{ + struct virtio_gpu_object *obj = gem_to_virtio_gpu_obj(gem_obj); + + if (obj) + virtio_gpu_object_unref(&obj); +} + +struct virtio_gpu_object *virtio_gpu_alloc_object(struct drm_device *dev, + size_t size, bool kernel, + bool pinned) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + struct virtio_gpu_object *obj; + int ret; + + ret = virtio_gpu_object_create(vgdev, size, kernel, pinned, &obj); + if (ret) + return ERR_PTR(ret); + + return obj; +} + +int virtio_gpu_gem_create(struct drm_file *file, + struct drm_device *dev, + uint64_t size, + struct drm_gem_object **obj_p, + uint32_t *handle_p) +{ + struct virtio_gpu_object *obj; + int ret; + u32 handle; + + obj = virtio_gpu_alloc_object(dev, size, false, false); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + ret = drm_gem_handle_create(file, &obj->gem_base, &handle); + if (ret) { + drm_gem_object_release(&obj->gem_base); + return ret; + } + + *obj_p = &obj->gem_base; + + /* drop reference from allocate - handle holds it now */ + drm_gem_object_unreference_unlocked(&obj->gem_base); + + *handle_p = handle; + return 0; +} + +int virtio_gpu_mode_dumb_create(struct drm_file *file_priv, + struct drm_device *dev, + struct drm_mode_create_dumb *args) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + struct drm_gem_object *gobj; + struct virtio_gpu_object *obj; + int ret; + uint32_t pitch; + uint32_t resid; + + pitch = args->width * ((args->bpp + 1) / 8); + args->size = pitch * args->height; + args->size = ALIGN(args->size, PAGE_SIZE); + + ret = virtio_gpu_gem_create(file_priv, dev, args->size, &gobj, + &args->handle); + if (ret) + goto fail; + + virtio_gpu_resource_id_get(vgdev, &resid); + virtio_gpu_cmd_create_resource(vgdev, resid, + 2, args->width, args->height); + + /* attach the object to the resource */ + obj = gem_to_virtio_gpu_obj(gobj); + ret = virtio_gpu_object_attach(vgdev, obj, resid, NULL); + if (ret) + goto fail; + + obj->dumb = true; + args->pitch = pitch; + return ret; + +fail: + return ret; +} + +int virtio_gpu_mode_dumb_destroy(struct drm_file *file_priv, + struct drm_device *dev, + uint32_t handle) +{ + return drm_gem_handle_delete(file_priv, handle); +} + +int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv, + struct drm_device *dev, + uint32_t handle, uint64_t *offset_p) +{ + struct drm_gem_object *gobj; + struct virtio_gpu_object *obj; + BUG_ON(!offset_p); + gobj = drm_gem_object_lookup(dev, file_priv, handle); + if (gobj == NULL) + return -ENOENT; + obj = gem_to_virtio_gpu_obj(gobj); + *offset_p = virtio_gpu_object_mmap_offset(obj); + drm_gem_object_unreference_unlocked(gobj); + return 0; +} diff --git a/drivers/gpu/drm/virtio/virtgpu_kms.c b/drivers/gpu/drm/virtio/virtgpu_kms.c new file mode 100644 index 000000000000..132405f15389 --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_kms.c @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include "virtgpu_drv.h" + +static int virtio_gpu_fbdev = 1; + +MODULE_PARM_DESC(fbdev, "Disable/Enable framebuffer device & console"); +module_param_named(fbdev, virtio_gpu_fbdev, int, 0400); + +static void virtio_gpu_config_changed_work_func(struct work_struct *work) +{ + struct virtio_gpu_device *vgdev = + container_of(work, struct virtio_gpu_device, + config_changed_work); + u32 events_read, events_clear = 0; + + /* read the config space */ + virtio_cread(vgdev->vdev, struct virtio_gpu_config, + events_read, &events_read); + if (events_read & VIRTIO_GPU_EVENT_DISPLAY) { + virtio_gpu_cmd_get_display_info(vgdev); + drm_helper_hpd_irq_event(vgdev->ddev); + events_clear |= VIRTIO_GPU_EVENT_DISPLAY; + } + virtio_cwrite(vgdev->vdev, struct virtio_gpu_config, + events_clear, &events_clear); +} + +static void virtio_gpu_init_vq(struct virtio_gpu_queue *vgvq, + void (*work_func)(struct work_struct *work)) +{ + spin_lock_init(&vgvq->qlock); + init_waitqueue_head(&vgvq->ack_queue); + INIT_WORK(&vgvq->dequeue_work, work_func); +} + +int virtio_gpu_driver_load(struct drm_device *dev, unsigned long flags) +{ + static vq_callback_t *callbacks[] = { + virtio_gpu_ctrl_ack, virtio_gpu_cursor_ack + }; + static const char *names[] = { "control", "cursor" }; + + struct virtio_gpu_device *vgdev; + /* this will expand later */ + struct virtqueue *vqs[2]; + u32 num_scanouts; + int ret; + + if (!virtio_has_feature(dev->virtdev, VIRTIO_F_VERSION_1)) + return -ENODEV; + + vgdev = kzalloc(sizeof(struct virtio_gpu_device), GFP_KERNEL); + if (!vgdev) + return -ENOMEM; + + vgdev->ddev = dev; + dev->dev_private = vgdev; + vgdev->vdev = dev->virtdev; + vgdev->dev = dev->dev; + + spin_lock_init(&vgdev->display_info_lock); + spin_lock_init(&vgdev->ctx_id_idr_lock); + idr_init(&vgdev->ctx_id_idr); + spin_lock_init(&vgdev->resource_idr_lock); + idr_init(&vgdev->resource_idr); + init_waitqueue_head(&vgdev->resp_wq); + virtio_gpu_init_vq(&vgdev->ctrlq, virtio_gpu_dequeue_ctrl_func); + virtio_gpu_init_vq(&vgdev->cursorq, virtio_gpu_dequeue_cursor_func); + + spin_lock_init(&vgdev->fence_drv.lock); + INIT_LIST_HEAD(&vgdev->fence_drv.fences); + INIT_WORK(&vgdev->config_changed_work, + virtio_gpu_config_changed_work_func); + + ret = vgdev->vdev->config->find_vqs(vgdev->vdev, 2, vqs, + callbacks, names); + if (ret) { + DRM_ERROR("failed to find virt queues\n"); + goto err_vqs; + } + vgdev->ctrlq.vq = vqs[0]; + vgdev->cursorq.vq = vqs[1]; + ret = virtio_gpu_alloc_vbufs(vgdev); + if (ret) { + DRM_ERROR("failed to alloc vbufs\n"); + goto err_vbufs; + } + + ret = virtio_gpu_ttm_init(vgdev); + if (ret) { + DRM_ERROR("failed to init ttm %d\n", ret); + goto err_ttm; + } + + /* get display info */ + virtio_cread(vgdev->vdev, struct virtio_gpu_config, + num_scanouts, &num_scanouts); + vgdev->num_scanouts = min_t(uint32_t, num_scanouts, + VIRTIO_GPU_MAX_SCANOUTS); + if (!vgdev->num_scanouts) { + DRM_ERROR("num_scanouts is zero\n"); + ret = -EINVAL; + goto err_scanouts; + } + + ret = virtio_gpu_modeset_init(vgdev); + if (ret) + goto err_modeset; + + virtio_device_ready(vgdev->vdev); + vgdev->vqs_ready = true; + + if (virtio_gpu_fbdev) + virtio_gpu_fbdev_init(vgdev); + virtio_gpu_cmd_get_display_info(vgdev); + + return 0; + +err_modeset: +err_scanouts: + virtio_gpu_ttm_fini(vgdev); +err_ttm: + virtio_gpu_free_vbufs(vgdev); +err_vbufs: + vgdev->vdev->config->del_vqs(vgdev->vdev); +err_vqs: + kfree(vgdev); + return ret; +} + +int virtio_gpu_driver_unload(struct drm_device *dev) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + + vgdev->vqs_ready = false; + flush_work(&vgdev->ctrlq.dequeue_work); + flush_work(&vgdev->cursorq.dequeue_work); + flush_work(&vgdev->config_changed_work); + vgdev->vdev->config->del_vqs(vgdev->vdev); + + virtio_gpu_modeset_fini(vgdev); + virtio_gpu_ttm_fini(vgdev); + virtio_gpu_free_vbufs(vgdev); + kfree(vgdev); + return 0; +} diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c b/drivers/gpu/drm/virtio/virtgpu_object.c new file mode 100644 index 000000000000..2c624c784c1d --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_object.c @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "virtgpu_drv.h" + +static void virtio_gpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) +{ + struct virtio_gpu_object *bo; + struct virtio_gpu_device *vgdev; + + bo = container_of(tbo, struct virtio_gpu_object, tbo); + vgdev = (struct virtio_gpu_device *)bo->gem_base.dev->dev_private; + + if (bo->hw_res_handle) + virtio_gpu_cmd_unref_resource(vgdev, bo->hw_res_handle); + if (bo->pages) + virtio_gpu_object_free_sg_table(bo); + drm_gem_object_release(&bo->gem_base); + kfree(bo); +} + +static void virtio_gpu_init_ttm_placement(struct virtio_gpu_object *vgbo, + bool pinned) +{ + u32 c = 1; + u32 pflag = pinned ? TTM_PL_FLAG_NO_EVICT : 0; + + vgbo->placement.placement = &vgbo->placement_code; + vgbo->placement.busy_placement = &vgbo->placement_code; + vgbo->placement_code.fpfn = 0; + vgbo->placement_code.lpfn = 0; + vgbo->placement_code.flags = + TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT | pflag; + vgbo->placement.num_placement = c; + vgbo->placement.num_busy_placement = c; + +} + +int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, + unsigned long size, bool kernel, bool pinned, + struct virtio_gpu_object **bo_ptr) +{ + struct virtio_gpu_object *bo; + enum ttm_bo_type type; + size_t acc_size; + int ret; + + if (kernel) + type = ttm_bo_type_kernel; + else + type = ttm_bo_type_device; + *bo_ptr = NULL; + + acc_size = ttm_bo_dma_acc_size(&vgdev->mman.bdev, size, + sizeof(struct virtio_gpu_object)); + + bo = kzalloc(sizeof(struct virtio_gpu_object), GFP_KERNEL); + if (bo == NULL) + return -ENOMEM; + size = roundup(size, PAGE_SIZE); + ret = drm_gem_object_init(vgdev->ddev, &bo->gem_base, size); + if (ret != 0) + goto err_gem_init; + bo->dumb = false; + virtio_gpu_init_ttm_placement(bo, pinned); + + ret = ttm_bo_init(&vgdev->mman.bdev, &bo->tbo, size, type, + &bo->placement, 0, !kernel, NULL, acc_size, + NULL, NULL, &virtio_gpu_ttm_bo_destroy); + if (ret != 0) + goto err_ttm_init; + + *bo_ptr = bo; + return 0; + +err_ttm_init: + drm_gem_object_release(&bo->gem_base); +err_gem_init: + kfree(bo); + return ret; +} + +int virtio_gpu_object_kmap(struct virtio_gpu_object *bo, void **ptr) +{ + bool is_iomem; + int r; + + if (bo->vmap) { + if (ptr) + *ptr = bo->vmap; + return 0; + } + r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); + if (r) + return r; + bo->vmap = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); + if (ptr) + *ptr = bo->vmap; + return 0; +} + +int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev, + struct virtio_gpu_object *bo) +{ + int ret; + struct page **pages = bo->tbo.ttm->pages; + int nr_pages = bo->tbo.num_pages; + + /* wtf swapping */ + if (bo->pages) + return 0; + + if (bo->tbo.ttm->state == tt_unpopulated) + bo->tbo.ttm->bdev->driver->ttm_tt_populate(bo->tbo.ttm); + bo->pages = kmalloc(sizeof(struct sg_table), GFP_KERNEL); + if (!bo->pages) + goto out; + + ret = sg_alloc_table_from_pages(bo->pages, pages, nr_pages, 0, + nr_pages << PAGE_SHIFT, GFP_KERNEL); + if (ret) + goto out; + return 0; +out: + kfree(bo->pages); + bo->pages = NULL; + return -ENOMEM; +} + +void virtio_gpu_object_free_sg_table(struct virtio_gpu_object *bo) +{ + sg_free_table(bo->pages); + kfree(bo->pages); + bo->pages = NULL; +} + +int virtio_gpu_object_wait(struct virtio_gpu_object *bo, bool no_wait) +{ + int r; + + r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL); + if (unlikely(r != 0)) + return r; + r = ttm_bo_wait(&bo->tbo, true, true, no_wait); + ttm_bo_unreserve(&bo->tbo); + return r; +} + diff --git a/drivers/gpu/drm/virtio/virtgpu_plane.c b/drivers/gpu/drm/virtio/virtgpu_plane.c new file mode 100644 index 000000000000..4a74129c5708 --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_plane.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "virtgpu_drv.h" +#include +#include + +static const uint32_t virtio_gpu_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_RGBX8888, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ABGR8888, +}; + +static void virtio_gpu_plane_destroy(struct drm_plane *plane) +{ + kfree(plane); +} + +static const struct drm_plane_funcs virtio_gpu_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = virtio_gpu_plane_destroy, + .reset = drm_atomic_helper_plane_reset, + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, +}; + +static int virtio_gpu_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + return 0; +} + +static void virtio_gpu_plane_atomic_update(struct drm_plane *plane, + struct drm_plane_state *old_state) +{ + struct drm_device *dev = plane->dev; + struct virtio_gpu_device *vgdev = dev->dev_private; + struct virtio_gpu_output *output = drm_crtc_to_virtio_gpu_output(plane->crtc); + struct virtio_gpu_framebuffer *vgfb; + struct virtio_gpu_object *bo; + uint32_t handle; + + if (plane->fb) { + vgfb = to_virtio_gpu_framebuffer(plane->fb); + bo = gem_to_virtio_gpu_obj(vgfb->obj); + handle = bo->hw_res_handle; + } else { + handle = 0; + } + + DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d\n", handle, + plane->state->crtc_w, plane->state->crtc_h, + plane->state->crtc_x, plane->state->crtc_y); + virtio_gpu_cmd_set_scanout(vgdev, output->index, handle, + plane->state->crtc_w, + plane->state->crtc_h, + plane->state->crtc_x, + plane->state->crtc_y); +} + + +static const struct drm_plane_helper_funcs virtio_gpu_plane_helper_funcs = { + .atomic_check = virtio_gpu_plane_atomic_check, + .atomic_update = virtio_gpu_plane_atomic_update, +}; + +struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev, + int index) +{ + struct drm_device *dev = vgdev->ddev; + struct drm_plane *plane; + int ret; + + plane = kzalloc(sizeof(*plane), GFP_KERNEL); + if (!plane) + return ERR_PTR(-ENOMEM); + + ret = drm_universal_plane_init(dev, plane, 1 << index, + &virtio_gpu_plane_funcs, + virtio_gpu_formats, + ARRAY_SIZE(virtio_gpu_formats), + DRM_PLANE_TYPE_PRIMARY); + if (ret) + goto err_plane_init; + + drm_plane_helper_add(plane, &virtio_gpu_plane_helper_funcs); + return plane; + +err_plane_init: + kfree(plane); + return ERR_PTR(ret); +} diff --git a/drivers/gpu/drm/virtio/virtgpu_ttm.c b/drivers/gpu/drm/virtio/virtgpu_ttm.c new file mode 100644 index 000000000000..e0e74c6bb959 --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_ttm.c @@ -0,0 +1,469 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Authors: + * Dave Airlie + * Alon Levy + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "virtgpu_drv.h" + +#include + +#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) + +static struct +virtio_gpu_device *virtio_gpu_get_vgdev(struct ttm_bo_device *bdev) +{ + struct virtio_gpu_mman *mman; + struct virtio_gpu_device *vgdev; + + mman = container_of(bdev, struct virtio_gpu_mman, bdev); + vgdev = container_of(mman, struct virtio_gpu_device, mman); + return vgdev; +} + +static int virtio_gpu_ttm_mem_global_init(struct drm_global_reference *ref) +{ + return ttm_mem_global_init(ref->object); +} + +static void virtio_gpu_ttm_mem_global_release(struct drm_global_reference *ref) +{ + ttm_mem_global_release(ref->object); +} + +static int virtio_gpu_ttm_global_init(struct virtio_gpu_device *vgdev) +{ + struct drm_global_reference *global_ref; + int r; + + vgdev->mman.mem_global_referenced = false; + global_ref = &vgdev->mman.mem_global_ref; + global_ref->global_type = DRM_GLOBAL_TTM_MEM; + global_ref->size = sizeof(struct ttm_mem_global); + global_ref->init = &virtio_gpu_ttm_mem_global_init; + global_ref->release = &virtio_gpu_ttm_mem_global_release; + + r = drm_global_item_ref(global_ref); + if (r != 0) { + DRM_ERROR("Failed setting up TTM memory accounting " + "subsystem.\n"); + return r; + } + + vgdev->mman.bo_global_ref.mem_glob = + vgdev->mman.mem_global_ref.object; + global_ref = &vgdev->mman.bo_global_ref.ref; + global_ref->global_type = DRM_GLOBAL_TTM_BO; + global_ref->size = sizeof(struct ttm_bo_global); + global_ref->init = &ttm_bo_global_init; + global_ref->release = &ttm_bo_global_release; + r = drm_global_item_ref(global_ref); + if (r != 0) { + DRM_ERROR("Failed setting up TTM BO subsystem.\n"); + drm_global_item_unref(&vgdev->mman.mem_global_ref); + return r; + } + + vgdev->mman.mem_global_referenced = true; + return 0; +} + +static void virtio_gpu_ttm_global_fini(struct virtio_gpu_device *vgdev) +{ + if (vgdev->mman.mem_global_referenced) { + drm_global_item_unref(&vgdev->mman.bo_global_ref.ref); + drm_global_item_unref(&vgdev->mman.mem_global_ref); + vgdev->mman.mem_global_referenced = false; + } +} + +#if 0 +/* + * Hmm, seems to not do anything useful. Leftover debug hack? + * Something like printing pagefaults to kernel log? + */ +static struct vm_operations_struct virtio_gpu_ttm_vm_ops; +static const struct vm_operations_struct *ttm_vm_ops; + +static int virtio_gpu_ttm_fault(struct vm_area_struct *vma, + struct vm_fault *vmf) +{ + struct ttm_buffer_object *bo; + struct virtio_gpu_device *vgdev; + int r; + + bo = (struct ttm_buffer_object *)vma->vm_private_data; + if (bo == NULL) + return VM_FAULT_NOPAGE; + vgdev = virtio_gpu_get_vgdev(bo->bdev); + r = ttm_vm_ops->fault(vma, vmf); + return r; +} +#endif + +int virtio_gpu_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct drm_file *file_priv; + struct virtio_gpu_device *vgdev; + int r; + + file_priv = filp->private_data; + vgdev = file_priv->minor->dev->dev_private; + if (vgdev == NULL) { + DRM_ERROR( + "filp->private_data->minor->dev->dev_private == NULL\n"); + return -EINVAL; + } + r = ttm_bo_mmap(filp, vma, &vgdev->mman.bdev); +#if 0 + if (unlikely(r != 0)) + return r; + if (unlikely(ttm_vm_ops == NULL)) { + ttm_vm_ops = vma->vm_ops; + virtio_gpu_ttm_vm_ops = *ttm_vm_ops; + virtio_gpu_ttm_vm_ops.fault = &virtio_gpu_ttm_fault; + } + vma->vm_ops = &virtio_gpu_ttm_vm_ops; + return 0; +#else + return r; +#endif +} + +static int virtio_gpu_invalidate_caches(struct ttm_bo_device *bdev, + uint32_t flags) +{ + return 0; +} + +static int ttm_bo_man_get_node(struct ttm_mem_type_manager *man, + struct ttm_buffer_object *bo, + const struct ttm_place *place, + struct ttm_mem_reg *mem) +{ + mem->mm_node = (void *)1; + return 0; +} + +static void ttm_bo_man_put_node(struct ttm_mem_type_manager *man, + struct ttm_mem_reg *mem) +{ + mem->mm_node = (void *)NULL; + return; +} + +static int ttm_bo_man_init(struct ttm_mem_type_manager *man, + unsigned long p_size) +{ + return 0; +} + +static int ttm_bo_man_takedown(struct ttm_mem_type_manager *man) +{ + return 0; +} + +static void ttm_bo_man_debug(struct ttm_mem_type_manager *man, + const char *prefix) +{ +} + +static const struct ttm_mem_type_manager_func virtio_gpu_bo_manager_func = { + ttm_bo_man_init, + ttm_bo_man_takedown, + ttm_bo_man_get_node, + ttm_bo_man_put_node, + ttm_bo_man_debug +}; + +static int virtio_gpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, + struct ttm_mem_type_manager *man) +{ + struct virtio_gpu_device *vgdev; + + vgdev = virtio_gpu_get_vgdev(bdev); + + switch (type) { + case TTM_PL_SYSTEM: + /* System memory */ + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; + man->available_caching = TTM_PL_MASK_CACHING; + man->default_caching = TTM_PL_FLAG_CACHED; + break; + case TTM_PL_TT: + man->func = &virtio_gpu_bo_manager_func; + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; + man->available_caching = TTM_PL_MASK_CACHING; + man->default_caching = TTM_PL_FLAG_CACHED; + break; + default: + DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); + return -EINVAL; + } + return 0; +} + +static void virtio_gpu_evict_flags(struct ttm_buffer_object *bo, + struct ttm_placement *placement) +{ + static struct ttm_place placements = { + .fpfn = 0, + .lpfn = 0, + .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM, + }; + + placement->placement = &placements; + placement->busy_placement = &placements; + placement->num_placement = 1; + placement->num_busy_placement = 1; + return; +} + +static int virtio_gpu_verify_access(struct ttm_buffer_object *bo, + struct file *filp) +{ + return 0; +} + +static int virtio_gpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, + struct ttm_mem_reg *mem) +{ + struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; + + mem->bus.addr = NULL; + mem->bus.offset = 0; + mem->bus.size = mem->num_pages << PAGE_SHIFT; + mem->bus.base = 0; + mem->bus.is_iomem = false; + if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) + return -EINVAL; + switch (mem->mem_type) { + case TTM_PL_SYSTEM: + case TTM_PL_TT: + /* system memory */ + return 0; + default: + return -EINVAL; + } + return 0; +} + +static void virtio_gpu_ttm_io_mem_free(struct ttm_bo_device *bdev, + struct ttm_mem_reg *mem) +{ +} + +/* + * TTM backend functions. + */ +struct virtio_gpu_ttm_tt { + struct ttm_dma_tt ttm; + struct virtio_gpu_device *vgdev; + u64 offset; +}; + +static int virtio_gpu_ttm_backend_bind(struct ttm_tt *ttm, + struct ttm_mem_reg *bo_mem) +{ + struct virtio_gpu_ttm_tt *gtt = (void *)ttm; + + gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); + if (!ttm->num_pages) + WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", + ttm->num_pages, bo_mem, ttm); + + /* Not implemented */ + return 0; +} + +static int virtio_gpu_ttm_backend_unbind(struct ttm_tt *ttm) +{ + /* Not implemented */ + return 0; +} + +static void virtio_gpu_ttm_backend_destroy(struct ttm_tt *ttm) +{ + struct virtio_gpu_ttm_tt *gtt = (void *)ttm; + + ttm_dma_tt_fini(>t->ttm); + kfree(gtt); +} + +static struct ttm_backend_func virtio_gpu_backend_func = { + .bind = &virtio_gpu_ttm_backend_bind, + .unbind = &virtio_gpu_ttm_backend_unbind, + .destroy = &virtio_gpu_ttm_backend_destroy, +}; + +static int virtio_gpu_ttm_tt_populate(struct ttm_tt *ttm) +{ + if (ttm->state != tt_unpopulated) + return 0; + + return ttm_pool_populate(ttm); +} + +static void virtio_gpu_ttm_tt_unpopulate(struct ttm_tt *ttm) +{ + ttm_pool_unpopulate(ttm); +} + +static struct ttm_tt *virtio_gpu_ttm_tt_create(struct ttm_bo_device *bdev, + unsigned long size, + uint32_t page_flags, + struct page *dummy_read_page) +{ + struct virtio_gpu_device *vgdev; + struct virtio_gpu_ttm_tt *gtt; + + vgdev = virtio_gpu_get_vgdev(bdev); + gtt = kzalloc(sizeof(struct virtio_gpu_ttm_tt), GFP_KERNEL); + if (gtt == NULL) + return NULL; + gtt->ttm.ttm.func = &virtio_gpu_backend_func; + gtt->vgdev = vgdev; + if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, + dummy_read_page)) { + kfree(gtt); + return NULL; + } + return >t->ttm.ttm; +} + +static void virtio_gpu_move_null(struct ttm_buffer_object *bo, + struct ttm_mem_reg *new_mem) +{ + struct ttm_mem_reg *old_mem = &bo->mem; + + BUG_ON(old_mem->mm_node != NULL); + *old_mem = *new_mem; + new_mem->mm_node = NULL; +} + +static int virtio_gpu_bo_move(struct ttm_buffer_object *bo, + bool evict, bool interruptible, + bool no_wait_gpu, + struct ttm_mem_reg *new_mem) +{ + virtio_gpu_move_null(bo, new_mem); + return 0; +} + +static void virtio_gpu_bo_move_notify(struct ttm_buffer_object *tbo, + struct ttm_mem_reg *new_mem) +{ + struct virtio_gpu_object *bo; + struct virtio_gpu_device *vgdev; + + bo = container_of(tbo, struct virtio_gpu_object, tbo); + vgdev = (struct virtio_gpu_device *)bo->gem_base.dev->dev_private; + + if (!new_mem || (new_mem->placement & TTM_PL_FLAG_SYSTEM)) { + if (bo->hw_res_handle) + virtio_gpu_cmd_resource_inval_backing(vgdev, + bo->hw_res_handle); + + } else if (new_mem->placement & TTM_PL_FLAG_TT) { + if (bo->hw_res_handle) { + virtio_gpu_object_attach(vgdev, bo, bo->hw_res_handle, + NULL); + } + } +} + +static void virtio_gpu_bo_swap_notify(struct ttm_buffer_object *tbo) +{ + struct virtio_gpu_object *bo; + struct virtio_gpu_device *vgdev; + + bo = container_of(tbo, struct virtio_gpu_object, tbo); + vgdev = (struct virtio_gpu_device *)bo->gem_base.dev->dev_private; + + if (bo->pages) + virtio_gpu_object_free_sg_table(bo); +} + +static struct ttm_bo_driver virtio_gpu_bo_driver = { + .ttm_tt_create = &virtio_gpu_ttm_tt_create, + .ttm_tt_populate = &virtio_gpu_ttm_tt_populate, + .ttm_tt_unpopulate = &virtio_gpu_ttm_tt_unpopulate, + .invalidate_caches = &virtio_gpu_invalidate_caches, + .init_mem_type = &virtio_gpu_init_mem_type, + .evict_flags = &virtio_gpu_evict_flags, + .move = &virtio_gpu_bo_move, + .verify_access = &virtio_gpu_verify_access, + .io_mem_reserve = &virtio_gpu_ttm_io_mem_reserve, + .io_mem_free = &virtio_gpu_ttm_io_mem_free, + .move_notify = &virtio_gpu_bo_move_notify, + .swap_notify = &virtio_gpu_bo_swap_notify, +}; + +int virtio_gpu_ttm_init(struct virtio_gpu_device *vgdev) +{ + int r; + + r = virtio_gpu_ttm_global_init(vgdev); + if (r) + return r; + /* No others user of address space so set it to 0 */ + r = ttm_bo_device_init(&vgdev->mman.bdev, + vgdev->mman.bo_global_ref.ref.object, + &virtio_gpu_bo_driver, + vgdev->ddev->anon_inode->i_mapping, + DRM_FILE_PAGE_OFFSET, 0); + if (r) { + DRM_ERROR("failed initializing buffer object driver(%d).\n", r); + goto err_dev_init; + return r; + } + + r = ttm_bo_init_mm(&vgdev->mman.bdev, TTM_PL_TT, 0); + if (r) { + DRM_ERROR("Failed initializing GTT heap.\n"); + goto err_mm_init; + return r; + } + return 0; + +err_mm_init: + ttm_bo_device_release(&vgdev->mman.bdev); +err_dev_init: + virtio_gpu_ttm_global_fini(vgdev); + return r; +} + +void virtio_gpu_ttm_fini(struct virtio_gpu_device *vgdev) +{ + ttm_bo_device_release(&vgdev->mman.bdev); + virtio_gpu_ttm_global_fini(vgdev); + DRM_INFO("virtio_gpu: ttm finalized\n"); +} diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c b/drivers/gpu/drm/virtio/virtgpu_vq.c new file mode 100644 index 000000000000..8fa6513eb3bc --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_vq.c @@ -0,0 +1,614 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Authors: + * Dave Airlie + * Gerd Hoffmann + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "virtgpu_drv.h" +#include +#include +#include + +#define MAX_INLINE_CMD_SIZE 96 +#define MAX_INLINE_RESP_SIZE 24 +#define VBUFFER_SIZE (sizeof(struct virtio_gpu_vbuffer) \ + + MAX_INLINE_CMD_SIZE \ + + MAX_INLINE_RESP_SIZE) + +void virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev, + uint32_t *resid) +{ + int handle; + + idr_preload(GFP_KERNEL); + spin_lock(&vgdev->resource_idr_lock); + handle = idr_alloc(&vgdev->resource_idr, NULL, 1, 0, GFP_NOWAIT); + spin_unlock(&vgdev->resource_idr_lock); + idr_preload_end(); + *resid = handle; +} + +void virtio_gpu_resource_id_put(struct virtio_gpu_device *vgdev, uint32_t id) +{ + spin_lock(&vgdev->resource_idr_lock); + idr_remove(&vgdev->resource_idr, id); + spin_unlock(&vgdev->resource_idr_lock); +} + +void virtio_gpu_ctrl_ack(struct virtqueue *vq) +{ + struct drm_device *dev = vq->vdev->priv; + struct virtio_gpu_device *vgdev = dev->dev_private; + schedule_work(&vgdev->ctrlq.dequeue_work); +} + +void virtio_gpu_cursor_ack(struct virtqueue *vq) +{ + struct drm_device *dev = vq->vdev->priv; + struct virtio_gpu_device *vgdev = dev->dev_private; + schedule_work(&vgdev->cursorq.dequeue_work); +} + +int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev) +{ + struct virtio_gpu_vbuffer *vbuf; + int i, size, count = 0; + void *ptr; + + INIT_LIST_HEAD(&vgdev->free_vbufs); + count += virtqueue_get_vring_size(vgdev->ctrlq.vq); + count += virtqueue_get_vring_size(vgdev->cursorq.vq); + size = count * VBUFFER_SIZE; + DRM_INFO("virtio vbuffers: %d bufs, %zdB each, %dkB total.\n", + count, VBUFFER_SIZE, size / 1024); + + vgdev->vbufs = kzalloc(size, GFP_KERNEL); + if (!vgdev->vbufs) + return -ENOMEM; + + for (i = 0, ptr = vgdev->vbufs; + i < count; + i++, ptr += VBUFFER_SIZE) { + vbuf = ptr; + list_add(&vbuf->list, &vgdev->free_vbufs); + } + return 0; +} + +void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev) +{ + struct virtio_gpu_vbuffer *vbuf; + int i, count = 0; + + count += virtqueue_get_vring_size(vgdev->ctrlq.vq); + count += virtqueue_get_vring_size(vgdev->cursorq.vq); + + for (i = 0; i < count; i++) { + if (WARN_ON(list_empty(&vgdev->free_vbufs))) + return; + vbuf = list_first_entry(&vgdev->free_vbufs, + struct virtio_gpu_vbuffer, list); + list_del(&vbuf->list); + } + kfree(vgdev->vbufs); +} + +static struct virtio_gpu_vbuffer* +virtio_gpu_get_vbuf(struct virtio_gpu_device *vgdev, + int size, int resp_size, void *resp_buf, + virtio_gpu_resp_cb resp_cb) +{ + struct virtio_gpu_vbuffer *vbuf; + + BUG_ON(list_empty(&vgdev->free_vbufs)); + vbuf = list_first_entry(&vgdev->free_vbufs, + struct virtio_gpu_vbuffer, list); + list_del(&vbuf->list); + memset(vbuf, 0, VBUFFER_SIZE); + + BUG_ON(size > MAX_INLINE_CMD_SIZE); + vbuf->buf = (void *)vbuf + sizeof(*vbuf); + vbuf->size = size; + + vbuf->resp_cb = resp_cb; + vbuf->resp_size = resp_size; + if (resp_size <= MAX_INLINE_RESP_SIZE) + vbuf->resp_buf = (void *)vbuf->buf + size; + else + vbuf->resp_buf = resp_buf; + BUG_ON(!vbuf->resp_buf); + return vbuf; +} + +static void *virtio_gpu_alloc_cmd(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer **vbuffer_p, + int size) +{ + struct virtio_gpu_vbuffer *vbuf; + + vbuf = virtio_gpu_get_vbuf(vgdev, size, + sizeof(struct virtio_gpu_ctrl_hdr), + NULL, NULL); + if (IS_ERR(vbuf)) { + *vbuffer_p = NULL; + return ERR_CAST(vbuf); + } + *vbuffer_p = vbuf; + return vbuf->buf; +} + +static struct virtio_gpu_update_cursor* +virtio_gpu_alloc_cursor(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer **vbuffer_p) +{ + struct virtio_gpu_vbuffer *vbuf; + + vbuf = virtio_gpu_get_vbuf + (vgdev, sizeof(struct virtio_gpu_update_cursor), + 0, NULL, NULL); + if (IS_ERR(vbuf)) { + *vbuffer_p = NULL; + return ERR_CAST(vbuf); + } + *vbuffer_p = vbuf; + return (struct virtio_gpu_update_cursor *)vbuf->buf; +} + +static void *virtio_gpu_alloc_cmd_resp(struct virtio_gpu_device *vgdev, + virtio_gpu_resp_cb cb, + struct virtio_gpu_vbuffer **vbuffer_p, + int cmd_size, int resp_size, + void *resp_buf) +{ + struct virtio_gpu_vbuffer *vbuf; + + vbuf = virtio_gpu_get_vbuf(vgdev, cmd_size, + resp_size, resp_buf, cb); + if (IS_ERR(vbuf)) { + *vbuffer_p = NULL; + return ERR_CAST(vbuf); + } + *vbuffer_p = vbuf; + return (struct virtio_gpu_command *)vbuf->buf; +} + +static void free_vbuf(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer *vbuf) +{ + if (vbuf->resp_size > MAX_INLINE_RESP_SIZE) + kfree(vbuf->resp_buf); + kfree(vbuf->data_buf); + list_add(&vbuf->list, &vgdev->free_vbufs); +} + +static void reclaim_vbufs(struct virtqueue *vq, struct list_head *reclaim_list) +{ + struct virtio_gpu_vbuffer *vbuf; + unsigned int len; + int freed = 0; + + while ((vbuf = virtqueue_get_buf(vq, &len))) { + list_add_tail(&vbuf->list, reclaim_list); + freed++; + } + if (freed == 0) + DRM_DEBUG("Huh? zero vbufs reclaimed"); +} + +void virtio_gpu_dequeue_ctrl_func(struct work_struct *work) +{ + struct virtio_gpu_device *vgdev = + container_of(work, struct virtio_gpu_device, + ctrlq.dequeue_work); + struct list_head reclaim_list; + struct virtio_gpu_vbuffer *entry, *tmp; + struct virtio_gpu_ctrl_hdr *resp; + u64 fence_id = 0; + + INIT_LIST_HEAD(&reclaim_list); + spin_lock(&vgdev->ctrlq.qlock); + do { + virtqueue_disable_cb(vgdev->ctrlq.vq); + reclaim_vbufs(vgdev->ctrlq.vq, &reclaim_list); + + } while (!virtqueue_enable_cb(vgdev->ctrlq.vq)); + spin_unlock(&vgdev->ctrlq.qlock); + + list_for_each_entry_safe(entry, tmp, &reclaim_list, list) { + resp = (struct virtio_gpu_ctrl_hdr *)entry->resp_buf; + if (resp->type != cpu_to_le32(VIRTIO_GPU_RESP_OK_NODATA)) + DRM_DEBUG("response 0x%x\n", le32_to_cpu(resp->type)); + if (resp->flags & cpu_to_le32(VIRTIO_GPU_FLAG_FENCE)) { + u64 f = le64_to_cpu(resp->fence_id); + + if (fence_id > f) { + DRM_ERROR("%s: Oops: fence %llx -> %llx\n", + __func__, fence_id, f); + } else { + fence_id = f; + } + } + if (entry->resp_cb) + entry->resp_cb(vgdev, entry); + + list_del(&entry->list); + free_vbuf(vgdev, entry); + } + wake_up(&vgdev->ctrlq.ack_queue); + + if (fence_id) + virtio_gpu_fence_event_process(vgdev, fence_id); +} + +void virtio_gpu_dequeue_cursor_func(struct work_struct *work) +{ + struct virtio_gpu_device *vgdev = + container_of(work, struct virtio_gpu_device, + cursorq.dequeue_work); + struct list_head reclaim_list; + struct virtio_gpu_vbuffer *entry, *tmp; + + INIT_LIST_HEAD(&reclaim_list); + spin_lock(&vgdev->cursorq.qlock); + do { + virtqueue_disable_cb(vgdev->cursorq.vq); + reclaim_vbufs(vgdev->cursorq.vq, &reclaim_list); + } while (!virtqueue_enable_cb(vgdev->cursorq.vq)); + spin_unlock(&vgdev->cursorq.qlock); + + list_for_each_entry_safe(entry, tmp, &reclaim_list, list) { + list_del(&entry->list); + free_vbuf(vgdev, entry); + } + wake_up(&vgdev->cursorq.ack_queue); +} + +static int virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer *vbuf) +{ + struct virtqueue *vq = vgdev->ctrlq.vq; + struct scatterlist *sgs[3], vcmd, vout, vresp; + int outcnt = 0, incnt = 0; + int ret; + + if (!vgdev->vqs_ready) + return -ENODEV; + + sg_init_one(&vcmd, vbuf->buf, vbuf->size); + sgs[outcnt+incnt] = &vcmd; + outcnt++; + + if (vbuf->data_size) { + sg_init_one(&vout, vbuf->data_buf, vbuf->data_size); + sgs[outcnt + incnt] = &vout; + outcnt++; + } + + if (vbuf->resp_size) { + sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size); + sgs[outcnt + incnt] = &vresp; + incnt++; + } + + spin_lock(&vgdev->ctrlq.qlock); +retry: + ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC); + if (ret == -ENOSPC) { + spin_unlock(&vgdev->ctrlq.qlock); + wait_event(vgdev->ctrlq.ack_queue, vq->num_free); + spin_lock(&vgdev->ctrlq.qlock); + goto retry; + } else { + virtqueue_kick(vq); + } + spin_unlock(&vgdev->ctrlq.qlock); + + if (!ret) + ret = vq->num_free; + return ret; +} + +static int virtio_gpu_queue_cursor(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer *vbuf) +{ + struct virtqueue *vq = vgdev->cursorq.vq; + struct scatterlist *sgs[1], ccmd; + int ret; + int outcnt; + + if (!vgdev->vqs_ready) + return -ENODEV; + + sg_init_one(&ccmd, vbuf->buf, vbuf->size); + sgs[0] = &ccmd; + outcnt = 1; + + spin_lock(&vgdev->cursorq.qlock); +retry: + ret = virtqueue_add_sgs(vq, sgs, outcnt, 0, vbuf, GFP_ATOMIC); + if (ret == -ENOSPC) { + spin_unlock(&vgdev->cursorq.qlock); + wait_event(vgdev->cursorq.ack_queue, vq->num_free); + spin_lock(&vgdev->cursorq.qlock); + goto retry; + } else { + virtqueue_kick(vq); + } + + spin_unlock(&vgdev->cursorq.qlock); + + if (!ret) + ret = vq->num_free; + return ret; +} + +/* just create gem objects for userspace and long lived objects, + just use dma_alloced pages for the queue objects? */ + +/* create a basic resource */ +void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev, + uint32_t resource_id, + uint32_t format, + uint32_t width, + uint32_t height) +{ + struct virtio_gpu_resource_create_2d *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_2D); + cmd_p->resource_id = cpu_to_le32(resource_id); + cmd_p->format = cpu_to_le32(format); + cmd_p->width = cpu_to_le32(width); + cmd_p->height = cpu_to_le32(height); + + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); +} + +void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev, + uint32_t resource_id) +{ + struct virtio_gpu_resource_unref *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_UNREF); + cmd_p->resource_id = cpu_to_le32(resource_id); + + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); +} + +void virtio_gpu_cmd_resource_inval_backing(struct virtio_gpu_device *vgdev, + uint32_t resource_id) +{ + struct virtio_gpu_resource_detach_backing *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING); + cmd_p->resource_id = cpu_to_le32(resource_id); + + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); +} + +void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev, + uint32_t scanout_id, uint32_t resource_id, + uint32_t width, uint32_t height, + uint32_t x, uint32_t y) +{ + struct virtio_gpu_set_scanout *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SET_SCANOUT); + cmd_p->resource_id = cpu_to_le32(resource_id); + cmd_p->scanout_id = cpu_to_le32(scanout_id); + cmd_p->r.width = cpu_to_le32(width); + cmd_p->r.height = cpu_to_le32(height); + cmd_p->r.x = cpu_to_le32(x); + cmd_p->r.y = cpu_to_le32(y); + + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); +} + +void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev, + uint32_t resource_id, + uint32_t x, uint32_t y, + uint32_t width, uint32_t height) +{ + struct virtio_gpu_resource_flush *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_FLUSH); + cmd_p->resource_id = cpu_to_le32(resource_id); + cmd_p->r.width = cpu_to_le32(width); + cmd_p->r.height = cpu_to_le32(height); + cmd_p->r.x = cpu_to_le32(x); + cmd_p->r.y = cpu_to_le32(y); + + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); +} + +void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev, + uint32_t resource_id, uint64_t offset, + __le32 width, __le32 height, + __le32 x, __le32 y, + struct virtio_gpu_fence **fence) +{ + struct virtio_gpu_transfer_to_host_2d *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D); + cmd_p->resource_id = cpu_to_le32(resource_id); + cmd_p->offset = cpu_to_le64(offset); + cmd_p->r.width = width; + cmd_p->r.height = height; + cmd_p->r.x = x; + cmd_p->r.y = y; + + if (fence) + virtio_gpu_fence_emit(vgdev, &cmd_p->hdr, fence); + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); +} + +static void +virtio_gpu_cmd_resource_attach_backing(struct virtio_gpu_device *vgdev, + uint32_t resource_id, + struct virtio_gpu_mem_entry *ents, + uint32_t nents, + struct virtio_gpu_fence **fence) +{ + struct virtio_gpu_resource_attach_backing *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING); + cmd_p->resource_id = cpu_to_le32(resource_id); + cmd_p->nr_entries = cpu_to_le32(nents); + + vbuf->data_buf = ents; + vbuf->data_size = sizeof(*ents) * nents; + + if (fence) + virtio_gpu_fence_emit(vgdev, &cmd_p->hdr, fence); + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); +} + +static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer *vbuf) +{ + struct virtio_gpu_resp_display_info *resp = + (struct virtio_gpu_resp_display_info *)vbuf->resp_buf; + int i; + + spin_lock(&vgdev->display_info_lock); + for (i = 0; i < vgdev->num_scanouts; i++) { + vgdev->outputs[i].info = resp->pmodes[i]; + if (resp->pmodes[i].enabled) { + DRM_DEBUG("output %d: %dx%d+%d+%d", i, + le32_to_cpu(resp->pmodes[i].r.width), + le32_to_cpu(resp->pmodes[i].r.height), + le32_to_cpu(resp->pmodes[i].r.x), + le32_to_cpu(resp->pmodes[i].r.y)); + } else { + DRM_DEBUG("output %d: disabled", i); + } + } + + spin_unlock(&vgdev->display_info_lock); + wake_up(&vgdev->resp_wq); + + if (!drm_helper_hpd_irq_event(vgdev->ddev)) + drm_kms_helper_hotplug_event(vgdev->ddev); +} + +int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev) +{ + struct virtio_gpu_ctrl_hdr *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + void *resp_buf; + + resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_display_info), + GFP_KERNEL); + if (!resp_buf) + return -ENOMEM; + + cmd_p = virtio_gpu_alloc_cmd_resp + (vgdev, &virtio_gpu_cmd_get_display_info_cb, &vbuf, + sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_display_info), + resp_buf); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->type = cpu_to_le32(VIRTIO_GPU_CMD_GET_DISPLAY_INFO); + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); + return 0; +} + +int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev, + struct virtio_gpu_object *obj, + uint32_t resource_id, + struct virtio_gpu_fence **fence) +{ + struct virtio_gpu_mem_entry *ents; + struct scatterlist *sg; + int si; + + if (!obj->pages) { + int ret; + ret = virtio_gpu_object_get_sg_table(vgdev, obj); + if (ret) + return ret; + } + + /* gets freed when the ring has consumed it */ + ents = kmalloc_array(obj->pages->nents, + sizeof(struct virtio_gpu_mem_entry), + GFP_KERNEL); + if (!ents) { + DRM_ERROR("failed to allocate ent list\n"); + return -ENOMEM; + } + + for_each_sg(obj->pages->sgl, sg, obj->pages->nents, si) { + ents[si].addr = cpu_to_le64(sg_phys(sg)); + ents[si].length = cpu_to_le32(sg->length); + ents[si].padding = 0; + } + + virtio_gpu_cmd_resource_attach_backing(vgdev, resource_id, + ents, obj->pages->nents, + fence); + obj->hw_res_handle = resource_id; + return 0; +} + +void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev, + struct virtio_gpu_output *output) +{ + struct virtio_gpu_vbuffer *vbuf; + struct virtio_gpu_update_cursor *cur_p; + + output->cursor.pos.scanout_id = cpu_to_le32(output->index); + cur_p = virtio_gpu_alloc_cursor(vgdev, &vbuf); + memcpy(cur_p, &output->cursor, sizeof(output->cursor)); + virtio_gpu_queue_cursor(vgdev, vbuf); +} diff --git a/include/drm/drmP.h b/include/drm/drmP.h index df6d9970d9a4..59ce5587ed90 100644 --- a/include/drm/drmP.h +++ b/include/drm/drmP.h @@ -814,6 +814,7 @@ struct drm_device { #endif struct platform_device *platformdev; /**< Platform device struture */ + struct virtio_device *virtdev; struct drm_sg_mem *sg; /**< Scatter gather memory */ unsigned int num_crtcs; /**< Number of CRTCs on this device */ diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild index 1a0006a76b00..4460e5820b0e 100644 --- a/include/uapi/linux/Kbuild +++ b/include/uapi/linux/Kbuild @@ -430,6 +430,7 @@ header-y += virtio_balloon.h header-y += virtio_blk.h header-y += virtio_config.h header-y += virtio_console.h +header-y += virtio_gpu.h header-y += virtio_ids.h header-y += virtio_input.h header-y += virtio_net.h diff --git a/include/uapi/linux/virtio_gpu.h b/include/uapi/linux/virtio_gpu.h new file mode 100644 index 000000000000..571c4cbd3f93 --- /dev/null +++ b/include/uapi/linux/virtio_gpu.h @@ -0,0 +1,204 @@ +/* + * Virtio GPU Device + * + * Copyright Red Hat, Inc. 2013-2014 + * + * Authors: + * Dave Airlie + * Gerd Hoffmann + * + * This header is BSD licensed so anyone can use the definitions + * to implement compatible drivers/servers: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of IBM nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef VIRTIO_GPU_HW_H +#define VIRTIO_GPU_HW_H + +enum virtio_gpu_ctrl_type { + VIRTIO_GPU_UNDEFINED = 0, + + /* 2d commands */ + VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, + VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, + VIRTIO_GPU_CMD_RESOURCE_UNREF, + VIRTIO_GPU_CMD_SET_SCANOUT, + VIRTIO_GPU_CMD_RESOURCE_FLUSH, + VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, + VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, + VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, + + /* cursor commands */ + VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, + VIRTIO_GPU_CMD_MOVE_CURSOR, + + /* success responses */ + VIRTIO_GPU_RESP_OK_NODATA = 0x1100, + VIRTIO_GPU_RESP_OK_DISPLAY_INFO, + + /* error responses */ + VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, + VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, + VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, + VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, + VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, + VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, +}; + +#define VIRTIO_GPU_FLAG_FENCE (1 << 0) + +struct virtio_gpu_ctrl_hdr { + __le32 type; + __le32 flags; + __le64 fence_id; + __le32 ctx_id; + __le32 padding; +}; + +/* data passed in the cursor vq */ + +struct virtio_gpu_cursor_pos { + __le32 scanout_id; + __le32 x; + __le32 y; + __le32 padding; +}; + +/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */ +struct virtio_gpu_update_cursor { + struct virtio_gpu_ctrl_hdr hdr; + struct virtio_gpu_cursor_pos pos; /* update & move */ + __le32 resource_id; /* update only */ + __le32 hot_x; /* update only */ + __le32 hot_y; /* update only */ + __le32 padding; +}; + +/* data passed in the control vq, 2d related */ + +struct virtio_gpu_rect { + __le32 x; + __le32 y; + __le32 width; + __le32 height; +}; + +/* VIRTIO_GPU_CMD_RESOURCE_UNREF */ +struct virtio_gpu_resource_unref { + struct virtio_gpu_ctrl_hdr hdr; + __le32 resource_id; + __le32 padding; +}; + +/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */ +struct virtio_gpu_resource_create_2d { + struct virtio_gpu_ctrl_hdr hdr; + __le32 resource_id; + __le32 format; + __le32 width; + __le32 height; +}; + +/* VIRTIO_GPU_CMD_SET_SCANOUT */ +struct virtio_gpu_set_scanout { + struct virtio_gpu_ctrl_hdr hdr; + struct virtio_gpu_rect r; + __le32 scanout_id; + __le32 resource_id; +}; + +/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */ +struct virtio_gpu_resource_flush { + struct virtio_gpu_ctrl_hdr hdr; + struct virtio_gpu_rect r; + __le32 resource_id; + __le32 padding; +}; + +/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */ +struct virtio_gpu_transfer_to_host_2d { + struct virtio_gpu_ctrl_hdr hdr; + struct virtio_gpu_rect r; + __le64 offset; + __le32 resource_id; + __le32 padding; +}; + +struct virtio_gpu_mem_entry { + __le64 addr; + __le32 length; + __le32 padding; +}; + +/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */ +struct virtio_gpu_resource_attach_backing { + struct virtio_gpu_ctrl_hdr hdr; + __le32 resource_id; + __le32 nr_entries; +}; + +/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */ +struct virtio_gpu_resource_detach_backing { + struct virtio_gpu_ctrl_hdr hdr; + __le32 resource_id; + __le32 padding; +}; + +/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */ +#define VIRTIO_GPU_MAX_SCANOUTS 16 +struct virtio_gpu_resp_display_info { + struct virtio_gpu_ctrl_hdr hdr; + struct virtio_gpu_display_one { + struct virtio_gpu_rect r; + __le32 enabled; + __le32 flags; + } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; +}; + +#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) + +struct virtio_gpu_config { + __u32 events_read; + __u32 events_clear; + __u32 num_scanouts; + __u32 reserved; +}; + +/* simple formats for fbcon/X use */ +enum virtio_gpu_formats { + VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, + VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, + VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, + VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, + + VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, + VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, + + VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, + VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, +}; + +#endif diff --git a/include/uapi/linux/virtio_ids.h b/include/uapi/linux/virtio_ids.h index 5f60aa4be50a..77925f587b15 100644 --- a/include/uapi/linux/virtio_ids.h +++ b/include/uapi/linux/virtio_ids.h @@ -39,6 +39,7 @@ #define VIRTIO_ID_9P 9 /* 9p virtio console */ #define VIRTIO_ID_RPROC_SERIAL 11 /* virtio remoteproc serial link */ #define VIRTIO_ID_CAIF 12 /* Virtio caif */ +#define VIRTIO_ID_GPU 16 /* virtio GPU */ #define VIRTIO_ID_INPUT 18 /* virtio input */ #endif /* _LINUX_VIRTIO_IDS_H */ -- cgit v1.2.3 From 9b5edbf7a462b7c846e9d4675b9b72b7a4e84de9 Mon Sep 17 00:00:00 2001 From: Maarten Lankhorst Date: Mon, 1 Jun 2015 08:59:53 +0200 Subject: drm/atomic: Clear crtc_state->active in drm_atomic_helper_set_config. This fixes some regressions in i915 when converting to atomic. set_config failed with -EINVAL, and I received the following warning in dmesg: [drm:drm_atomic_crtc_check] [CRTC:20] active without enabled Solve this by clearing active when a crtc is disabled. Because crtc_state->enable implies that connectors are active the change from disabled->enabled can only happen for the crtc that's being set_config'd, and checking for !crtc_state->enable is sufficient here. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Rob Clark Signed-off-by: Maarten Lankhorst Signed-off-by: Dave Airlie --- drivers/gpu/drm/drm_atomic_helper.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index a900858fa265..536ae4da4665 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -1563,6 +1563,8 @@ static int update_output_state(struct drm_atomic_state *state, crtc_state->enable = drm_atomic_connectors_for_crtc(state, crtc); + if (!crtc_state->enable) + crtc_state->active = false; } return 0; -- cgit v1.2.3 From 054e4c60fe7871b95e827097a6b575592beb5bd3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:06:12 -0400 Subject: drm/amdgpu: add BIF 4.1 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the BIF (Bus InterFace) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h | 921 ++ .../drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h | 10250 +++++++++++++++++++ 2 files changed, 11171 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h new file mode 100644 index 000000000000..a761ba07f937 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h @@ -0,0 +1,921 @@ +/* + * BIF_4_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_4_1_D_H +#define BIF_4_1_D_H + +#define mmMM_INDEX 0x0 +#define mmMM_INDEX_HI 0x6 +#define mmMM_DATA 0x1 +#define mmBUS_CNTL 0x1508 +#define mmCONFIG_CNTL 0x1509 +#define mmCONFIG_MEMSIZE 0x150a +#define mmCONFIG_F0_BASE 0x150b +#define mmCONFIG_APER_SIZE 0x150c +#define mmCONFIG_REG_APER_SIZE 0x150d +#define mmBIF_SCRATCH0 0x150e +#define mmBIF_SCRATCH1 0x150f +#define mmBX_RESET_EN 0x1514 +#define mmMM_CFGREGS_CNTL 0x1513 +#define mmHW_DEBUG 0x1515 +#define mmMASTER_CREDIT_CNTL 0x1516 +#define mmSLAVE_REQ_CREDIT_CNTL 0x1517 +#define mmBX_RESET_CNTL 0x1518 +#define mmINTERRUPT_CNTL 0x151a +#define mmINTERRUPT_CNTL2 0x151b +#define mmBIF_DEBUG_CNTL 0x151c +#define mmBIF_DEBUG_MUX 0x151d +#define mmBIF_DEBUG_OUT 0x151e +#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 +#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 +#define mmCLKREQB_PAD_CNTL 0x1521 +#define mmSMBUS_SLV_CNTL 0x14fd +#define mmSMBUS_SLV_CNTL1 0x14fe +#define mmSMBDAT_PAD_CNTL 0x1522 +#define mmSMBCLK_PAD_CNTL 0x1523 +#define mmBIF_XDMA_LO 0x14c0 +#define mmBIF_XDMA_HI 0x14c1 +#define mmBIF_FEATURES_CONTROL_MISC 0x14c2 +#define mmBIF_DOORBELL_CNTL 0x14c3 +#define mmBIF_SLVARB_MODE 0x14c4 +#define mmBIF_FB_EN 0x1524 +#define mmBIF_BUSNUM_CNTL1 0x1525 +#define mmBIF_BUSNUM_LIST0 0x1526 +#define mmBIF_BUSNUM_LIST1 0x1527 +#define mmBIF_BUSNUM_CNTL2 0x152b +#define mmBIF_BUSY_DELAY_CNTR 0x1529 +#define mmBIF_PERFMON_CNTL 0x152c +#define mmBIF_PERFCOUNTER0_RESULT 0x152d +#define mmBIF_PERFCOUNTER1_RESULT 0x152e +#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 +#define mmGPU_HDP_FLUSH_REQ 0x1537 +#define mmGPU_HDP_FLUSH_DONE 0x1538 +#define mmSLAVE_HANG_ERROR 0x153b +#define mmCAPTURE_HOST_BUSNUM 0x153c +#define mmHOST_BUSNUM 0x153d +#define mmPEER_REG_RANGE0 0x153e +#define mmPEER_REG_RANGE1 0x153f +#define mmPEER0_FB_OFFSET_HI 0x14f3 +#define mmPEER0_FB_OFFSET_LO 0x14f2 +#define mmPEER1_FB_OFFSET_HI 0x14f1 +#define mmPEER1_FB_OFFSET_LO 0x14f0 +#define mmPEER2_FB_OFFSET_HI 0x14ef +#define mmPEER2_FB_OFFSET_LO 0x14ee +#define mmPEER3_FB_OFFSET_HI 0x14ed +#define mmPEER3_FB_OFFSET_LO 0x14ec +#define mmDBG_BYPASS_SRBM_ACCESS 0x14eb +#define mmSMBUS_BACO_DUMMY 0x14c6 +#define mmBIF_DEVFUNCNUM_LIST0 0x14e8 +#define mmBIF_DEVFUNCNUM_LIST1 0x14e7 +#define mmBACO_CNTL 0x14e5 +#define mmBF_ANA_ISO_CNTL 0x14c7 +#define mmMEM_TYPE_CNTL 0x14e4 +#define mmBIF_BACO_DEBUG 0x14df +#define mmBIF_BACO_DEBUG_LATCH 0x14dc +#define mmBACO_CNTL_MISC 0x14db +#define mmBIF_SSA_PWR_STATUS 0x14c8 +#define mmBIF_SSA_GFX0_LOWER 0x14ca +#define mmBIF_SSA_GFX0_UPPER 0x14cb +#define mmBIF_SSA_GFX1_LOWER 0x14cc +#define mmBIF_SSA_GFX1_UPPER 0x14cd +#define mmBIF_SSA_GFX2_LOWER 0x14ce +#define mmBIF_SSA_GFX2_UPPER 0x14cf +#define mmBIF_SSA_GFX3_LOWER 0x14d0 +#define mmBIF_SSA_GFX3_UPPER 0x14d1 +#define mmBIF_SSA_DISP_LOWER 0x14d2 +#define mmBIF_SSA_DISP_UPPER 0x14d3 +#define mmBIF_SSA_MC_LOWER 0x14d4 +#define mmBIF_SSA_MC_UPPER 0x14d5 +#define mmIMPCTL_RESET 0x14f5 +#define mmGARLIC_FLUSH_CNTL 0x1401 +#define mmGARLIC_FLUSH_ADDR_START_0 0x1402 +#define mmGARLIC_FLUSH_ADDR_START_1 0x1404 +#define mmGARLIC_FLUSH_ADDR_START_2 0x1406 +#define mmGARLIC_FLUSH_ADDR_START_3 0x1408 +#define mmGARLIC_FLUSH_ADDR_START_4 0x140a +#define mmGARLIC_FLUSH_ADDR_START_5 0x140c +#define mmGARLIC_FLUSH_ADDR_START_6 0x140e +#define mmGARLIC_FLUSH_ADDR_START_7 0x1410 +#define mmGARLIC_FLUSH_ADDR_END_0 0x1403 +#define mmGARLIC_FLUSH_ADDR_END_1 0x1405 +#define mmGARLIC_FLUSH_ADDR_END_2 0x1407 +#define mmGARLIC_FLUSH_ADDR_END_3 0x1409 +#define mmGARLIC_FLUSH_ADDR_END_4 0x140b +#define mmGARLIC_FLUSH_ADDR_END_5 0x140d +#define mmGARLIC_FLUSH_ADDR_END_6 0x140f +#define mmGARLIC_FLUSH_ADDR_END_7 0x1411 +#define mmGARLIC_FLUSH_REQ 0x1412 +#define mmGPU_GARLIC_FLUSH_REQ 0x1413 +#define mmGPU_GARLIC_FLUSH_DONE 0x1414 +#define mmGARLIC_COHE_CP_RB0_WPTR 0x1415 +#define mmGARLIC_COHE_CP_RB1_WPTR 0x1416 +#define mmGARLIC_COHE_CP_RB2_WPTR 0x1417 +#define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418 +#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419 +#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a +#define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b +#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c +#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d +#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e +#define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f +#define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420 +#define mmGARLIC_COHE_VCE_RB_WPTR 0x1421 +#define mmBIOS_SCRATCH_0 0x5c9 +#define mmBIOS_SCRATCH_1 0x5ca +#define mmBIOS_SCRATCH_2 0x5cb +#define mmBIOS_SCRATCH_3 0x5cc +#define mmBIOS_SCRATCH_4 0x5cd +#define mmBIOS_SCRATCH_5 0x5ce +#define mmBIOS_SCRATCH_6 0x5cf +#define mmBIOS_SCRATCH_7 0x5d0 +#define mmBIOS_SCRATCH_8 0x5d1 +#define mmBIOS_SCRATCH_9 0x5d2 +#define mmBIOS_SCRATCH_10 0x5d3 +#define mmBIOS_SCRATCH_11 0x5d4 +#define mmBIOS_SCRATCH_12 0x5d5 +#define mmBIOS_SCRATCH_13 0x5d6 +#define mmBIOS_SCRATCH_14 0x5d7 +#define mmBIOS_SCRATCH_15 0x5d8 +#define mmVENDOR_ID 0x0 +#define mmDEVICE_ID 0x0 +#define mmCOMMAND 0x1 +#define mmSTATUS 0x1 +#define mmREVISION_ID 0x2 +#define mmPROG_INTERFACE 0x2 +#define mmSUB_CLASS 0x2 +#define mmBASE_CLASS 0x2 +#define mmCACHE_LINE 0x3 +#define mmLATENCY 0x3 +#define mmHEADER 0x3 +#define mmBIST 0x3 +#define mmBASE_ADDR_1 0x4 +#define mmBASE_ADDR_2 0x5 +#define mmBASE_ADDR_3 0x6 +#define mmBASE_ADDR_4 0x7 +#define mmBASE_ADDR_5 0x8 +#define mmBASE_ADDR_6 0x9 +#define mmROM_BASE_ADDR 0xc +#define mmCAP_PTR 0xd +#define mmINTERRUPT_LINE 0xf +#define mmINTERRUPT_PIN 0xf +#define mmADAPTER_ID 0xb +#define mmMIN_GRANT 0xf +#define mmMAX_LATENCY 0xf +#define mmVENDOR_CAP_LIST 0x12 +#define mmADAPTER_ID_W 0x13 +#define mmPMI_CAP_LIST 0x14 +#define mmPMI_CAP 0x14 +#define mmPMI_STATUS_CNTL 0x15 +#define mmPCIE_CAP_LIST 0x16 +#define mmPCIE_CAP 0x16 +#define mmDEVICE_CAP 0x17 +#define mmDEVICE_CNTL 0x18 +#define mmDEVICE_STATUS 0x18 +#define mmLINK_CAP 0x19 +#define mmLINK_CNTL 0x1a +#define mmLINK_STATUS 0x1a +#define mmDEVICE_CAP2 0x1f +#define mmDEVICE_CNTL2 0x20 +#define mmDEVICE_STATUS2 0x20 +#define mmLINK_CAP2 0x21 +#define mmLINK_CNTL2 0x22 +#define mmLINK_STATUS2 0x22 +#define mmMSI_CAP_LIST 0x28 +#define mmMSI_MSG_CNTL 0x28 +#define mmMSI_MSG_ADDR_LO 0x29 +#define mmMSI_MSG_ADDR_HI 0x2a +#define mmMSI_MSG_DATA_64 0x2b +#define mmMSI_MSG_DATA 0x2a +#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40 +#define mmPCIE_VENDOR_SPECIFIC_HDR 0x41 +#define mmPCIE_VENDOR_SPECIFIC1 0x42 +#define mmPCIE_VENDOR_SPECIFIC2 0x43 +#define mmPCIE_VC_ENH_CAP_LIST 0x44 +#define mmPCIE_PORT_VC_CAP_REG1 0x45 +#define mmPCIE_PORT_VC_CAP_REG2 0x46 +#define mmPCIE_PORT_VC_CNTL 0x47 +#define mmPCIE_PORT_VC_STATUS 0x47 +#define mmPCIE_VC0_RESOURCE_CAP 0x48 +#define mmPCIE_VC0_RESOURCE_CNTL 0x49 +#define mmPCIE_VC0_RESOURCE_STATUS 0x4a +#define mmPCIE_VC1_RESOURCE_CAP 0x4b +#define mmPCIE_VC1_RESOURCE_CNTL 0x4c +#define mmPCIE_VC1_RESOURCE_STATUS 0x4d +#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50 +#define mmPCIE_DEV_SERIAL_NUM_DW1 0x51 +#define mmPCIE_DEV_SERIAL_NUM_DW2 0x52 +#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54 +#define mmPCIE_UNCORR_ERR_STATUS 0x55 +#define mmPCIE_UNCORR_ERR_MASK 0x56 +#define mmPCIE_UNCORR_ERR_SEVERITY 0x57 +#define mmPCIE_CORR_ERR_STATUS 0x58 +#define mmPCIE_CORR_ERR_MASK 0x59 +#define mmPCIE_ADV_ERR_CAP_CNTL 0x5a +#define mmPCIE_HDR_LOG0 0x5b +#define mmPCIE_HDR_LOG1 0x5c +#define mmPCIE_HDR_LOG2 0x5d +#define mmPCIE_HDR_LOG3 0x5e +#define mmPCIE_TLP_PREFIX_LOG0 0x62 +#define mmPCIE_TLP_PREFIX_LOG1 0x63 +#define mmPCIE_TLP_PREFIX_LOG2 0x64 +#define mmPCIE_TLP_PREFIX_LOG3 0x65 +#define mmPCIE_BAR_ENH_CAP_LIST 0x80 +#define mmPCIE_BAR1_CAP 0x81 +#define mmPCIE_BAR1_CNTL 0x82 +#define mmPCIE_BAR2_CAP 0x83 +#define mmPCIE_BAR2_CNTL 0x84 +#define mmPCIE_BAR3_CAP 0x85 +#define mmPCIE_BAR3_CNTL 0x86 +#define mmPCIE_BAR4_CAP 0x87 +#define mmPCIE_BAR4_CNTL 0x88 +#define mmPCIE_BAR5_CAP 0x89 +#define mmPCIE_BAR5_CNTL 0x8a +#define mmPCIE_BAR6_CAP 0x8b +#define mmPCIE_BAR6_CNTL 0x8c +#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90 +#define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91 +#define mmPCIE_PWR_BUDGET_DATA 0x92 +#define mmPCIE_PWR_BUDGET_CAP 0x93 +#define mmPCIE_DPA_ENH_CAP_LIST 0x94 +#define mmPCIE_DPA_CAP 0x95 +#define mmPCIE_DPA_LATENCY_INDICATOR 0x96 +#define mmPCIE_DPA_STATUS 0x97 +#define mmPCIE_DPA_CNTL 0x97 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99 +#define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c +#define mmPCIE_LINK_CNTL3 0x9d +#define mmPCIE_LANE_ERROR_STATUS 0x9e +#define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f +#define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f +#define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0 +#define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0 +#define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1 +#define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1 +#define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2 +#define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2 +#define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3 +#define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3 +#define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4 +#define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4 +#define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5 +#define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5 +#define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6 +#define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6 +#define mmPCIE_ACS_ENH_CAP_LIST 0xa8 +#define mmPCIE_ACS_CAP 0xa9 +#define mmPCIE_ACS_CNTL 0xa9 +#define mmPCIE_ATS_ENH_CAP_LIST 0xac +#define mmPCIE_ATS_CAP 0xad +#define mmPCIE_ATS_CNTL 0xad +#define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0 +#define mmPCIE_PAGE_REQ_CNTL 0xb1 +#define mmPCIE_PAGE_REQ_STATUS 0xb1 +#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2 +#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3 +#define mmPCIE_PASID_ENH_CAP_LIST 0xb4 +#define mmPCIE_PASID_CAP 0xb5 +#define mmPCIE_PASID_CNTL 0xb5 +#define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8 +#define mmPCIE_TPH_REQR_CAP 0xb9 +#define mmPCIE_TPH_REQR_CNTL 0xba +#define mmPCIE_MC_ENH_CAP_LIST 0xbc +#define mmPCIE_MC_CAP 0xbd +#define mmPCIE_MC_CNTL 0xbd +#define mmPCIE_MC_ADDR0 0xbe +#define mmPCIE_MC_ADDR1 0xbf +#define mmPCIE_MC_RCV0 0xc0 +#define mmPCIE_MC_RCV1 0xc1 +#define mmPCIE_MC_BLOCK_ALL0 0xc2 +#define mmPCIE_MC_BLOCK_ALL1 0xc3 +#define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4 +#define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5 +#define mmPCIE_LTR_ENH_CAP_LIST 0xc8 +#define mmPCIE_LTR_CAP 0xc9 +#define mmPCIE_INDEX 0xe +#define mmPCIE_DATA 0xf +#define mmPCIE_INDEX_2 0xc +#define mmPCIE_DATA_2 0xd +#define ixPCIE_RESERVED 0x1400000 +#define ixPCIE_SCRATCH 0x1400001 +#define ixPCIE_HW_DEBUG 0x1400002 +#define ixPCIE_RX_NUM_NAK 0x140000e +#define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f +#define ixPCIE_CNTL 0x1400010 +#define ixPCIE_CONFIG_CNTL 0x1400011 +#define ixPCIE_DEBUG_CNTL 0x1400012 +#define ixPCIE_INT_CNTL 0x140001a +#define ixPCIE_INT_STATUS 0x140001b +#define ixPCIE_CNTL2 0x140001c +#define ixPCIE_RX_CNTL2 0x140001d +#define ixPCIE_TX_F0_ATTR_CNTL 0x140001e +#define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f +#define ixPCIE_CI_CNTL 0x1400020 +#define ixPCIE_BUS_CNTL 0x1400021 +#define ixPCIE_LC_STATE6 0x1400022 +#define ixPCIE_LC_STATE7 0x1400023 +#define ixPCIE_LC_STATE8 0x1400024 +#define ixPCIE_LC_STATE9 0x1400025 +#define ixPCIE_LC_STATE10 0x1400026 +#define ixPCIE_LC_STATE11 0x1400027 +#define ixPCIE_LC_STATUS1 0x1400028 +#define ixPCIE_LC_STATUS2 0x1400029 +#define ixPCIE_WPR_CNTL 0x1400030 +#define ixPCIE_RX_LAST_TLP0 0x1400031 +#define ixPCIE_RX_LAST_TLP1 0x1400032 +#define ixPCIE_RX_LAST_TLP2 0x1400033 +#define ixPCIE_RX_LAST_TLP3 0x1400034 +#define ixPCIE_TX_LAST_TLP0 0x1400035 +#define ixPCIE_TX_LAST_TLP1 0x1400036 +#define ixPCIE_TX_LAST_TLP2 0x1400037 +#define ixPCIE_TX_LAST_TLP3 0x1400038 +#define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a +#define ixPCIE_I2C_REG_DATA 0x140003b +#define ixPCIE_CFG_CNTL 0x140003c +#define ixPCIE_P_CNTL 0x1400040 +#define ixPCIE_P_BUF_STATUS 0x1400041 +#define ixPCIE_P_DECODER_STATUS 0x1400042 +#define ixPCIE_P_MISC_STATUS 0x1400043 +#define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050 +#define ixPCIE_OBFF_CNTL 0x1400061 +#define ixPCIE_TX_LTR_CNTL 0x1400060 +#define ixPCIE_PERF_COUNT_CNTL 0x1400080 +#define ixPCIE_PERF_CNTL_TXCLK 0x1400081 +#define ixPCIE_PERF_COUNT0_TXCLK 0x1400082 +#define ixPCIE_PERF_COUNT1_TXCLK 0x1400083 +#define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084 +#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085 +#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086 +#define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087 +#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088 +#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089 +#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a +#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b +#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c +#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d +#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e +#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f +#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 +#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 +#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 +#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 +#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 +#define ixPCIE_PERF_CNTL_TXCLK2 0x1400095 +#define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096 +#define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097 +#define ixPCIE_STRAP_F0 0x14000b0 +#define ixPCIE_STRAP_F1 0x14000b1 +#define ixPCIE_STRAP_F2 0x14000b2 +#define ixPCIE_STRAP_F3 0x14000b3 +#define ixPCIE_STRAP_F4 0x14000b4 +#define ixPCIE_STRAP_F5 0x14000b5 +#define ixPCIE_STRAP_F6 0x14000b6 +#define ixPCIE_STRAP_F7 0x14000b7 +#define ixPCIE_STRAP_MISC 0x14000c0 +#define ixPCIE_STRAP_MISC2 0x14000c1 +#define ixPCIE_STRAP_PI 0x14000c2 +#define ixPCIE_STRAP_I2C_BD 0x14000c4 +#define ixPCIE_PRBS_CLR 0x14000c8 +#define ixPCIE_PRBS_STATUS1 0x14000c9 +#define ixPCIE_PRBS_STATUS2 0x14000ca +#define ixPCIE_PRBS_FREERUN 0x14000cb +#define ixPCIE_PRBS_MISC 0x14000cc +#define ixPCIE_PRBS_USER_PATTERN 0x14000cd +#define ixPCIE_PRBS_LO_BITCNT 0x14000ce +#define ixPCIE_PRBS_HI_BITCNT 0x14000cf +#define ixPCIE_PRBS_ERRCNT_0 0x14000d0 +#define ixPCIE_PRBS_ERRCNT_1 0x14000d1 +#define ixPCIE_PRBS_ERRCNT_2 0x14000d2 +#define ixPCIE_PRBS_ERRCNT_3 0x14000d3 +#define ixPCIE_PRBS_ERRCNT_4 0x14000d4 +#define ixPCIE_PRBS_ERRCNT_5 0x14000d5 +#define ixPCIE_PRBS_ERRCNT_6 0x14000d6 +#define ixPCIE_PRBS_ERRCNT_7 0x14000d7 +#define ixPCIE_PRBS_ERRCNT_8 0x14000d8 +#define ixPCIE_PRBS_ERRCNT_9 0x14000d9 +#define ixPCIE_PRBS_ERRCNT_10 0x14000da +#define ixPCIE_PRBS_ERRCNT_11 0x14000db +#define ixPCIE_PRBS_ERRCNT_12 0x14000dc +#define ixPCIE_PRBS_ERRCNT_13 0x14000dd +#define ixPCIE_PRBS_ERRCNT_14 0x14000de +#define ixPCIE_PRBS_ERRCNT_15 0x14000df +#define ixPCIE_F0_DPA_CAP 0x14000e0 +#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4 +#define ixPCIE_F0_DPA_CNTL 0x14000e5 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee +#define ixPCIEP_RESERVED 0x10010000 +#define ixPCIEP_SCRATCH 0x10010001 +#define ixPCIEP_HW_DEBUG 0x10010002 +#define ixPCIEP_PORT_CNTL 0x10010010 +#define ixPCIE_TX_CNTL 0x10010020 +#define ixPCIE_TX_REQUESTER_ID 0x10010021 +#define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022 +#define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023 +#define ixPCIE_TX_SEQ 0x10010024 +#define ixPCIE_TX_REPLAY 0x10010025 +#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026 +#define ixPCIE_TX_CREDITS_ADVT_P 0x10010030 +#define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031 +#define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032 +#define ixPCIE_TX_CREDITS_INIT_P 0x10010033 +#define ixPCIE_TX_CREDITS_INIT_NP 0x10010034 +#define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035 +#define ixPCIE_TX_CREDITS_STATUS 0x10010036 +#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037 +#define ixPCIE_P_PORT_LANE_STATUS 0x10010050 +#define ixPCIE_FC_P 0x10010060 +#define ixPCIE_FC_NP 0x10010061 +#define ixPCIE_FC_CPL 0x10010062 +#define ixPCIE_ERR_CNTL 0x1001006a +#define ixPCIE_RX_CNTL 0x10010070 +#define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071 +#define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072 +#define ixPCIE_RX_CNTL3 0x10010074 +#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080 +#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081 +#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082 +#define ixPCIE_LC_CNTL 0x100100a0 +#define ixPCIE_LC_CNTL2 0x100100b1 +#define ixPCIE_LC_CNTL3 0x100100b5 +#define ixPCIE_LC_CNTL4 0x100100b6 +#define ixPCIE_LC_CNTL5 0x100100b7 +#define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2 +#define ixPCIE_LC_TRAINING_CNTL 0x100100a1 +#define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2 +#define ixPCIE_LC_N_FTS_CNTL 0x100100a3 +#define ixPCIE_LC_SPEED_CNTL 0x100100a4 +#define ixPCIE_LC_CDR_CNTL 0x100100b3 +#define ixPCIE_LC_LANE_CNTL 0x100100b4 +#define ixPCIE_LC_FORCE_COEFF 0x100100b8 +#define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9 +#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba +#define ixPCIE_LC_STATE0 0x100100a5 +#define ixPCIE_LC_STATE1 0x100100a6 +#define ixPCIE_LC_STATE2 0x100100a7 +#define ixPCIE_LC_STATE3 0x100100a8 +#define ixPCIE_LC_STATE4 0x100100a9 +#define ixPCIE_LC_STATE5 0x100100aa +#define ixPCIEP_STRAP_LC 0x100100c0 +#define ixPCIEP_STRAP_MISC 0x100100c1 +#define ixPCIEP_BCH_ECC_CNTL 0x100100d0 +#define ixPB0_GLB_CTRL_REG0 0x1200004 +#define ixPB0_GLB_CTRL_REG1 0x1200008 +#define ixPB0_GLB_CTRL_REG2 0x120000c +#define ixPB0_GLB_CTRL_REG3 0x1200010 +#define ixPB0_GLB_CTRL_REG4 0x1200014 +#define ixPB0_GLB_CTRL_REG5 0x1200018 +#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c +#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020 +#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024 +#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028 +#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c +#define ixPB0_GLB_OVRD_REG0 0x1200030 +#define ixPB0_GLB_OVRD_REG1 0x1200034 +#define ixPB0_GLB_OVRD_REG2 0x1200038 +#define ixPB0_HW_DEBUG 0x1202004 +#define ixPB0_STRAP_GLB_REG0 0x1202020 +#define ixPB0_STRAP_TX_REG0 0x1202024 +#define ixPB0_STRAP_RX_REG0 0x1202028 +#define ixPB0_STRAP_RX_REG1 0x120202c +#define ixPB0_STRAP_PLL_REG0 0x1202030 +#define ixPB0_STRAP_PIN_REG0 0x1202034 +#define ixPB0_DFT_JIT_INJ_REG0 0x1203000 +#define ixPB0_DFT_JIT_INJ_REG1 0x1203004 +#define ixPB0_DFT_JIT_INJ_REG2 0x1203008 +#define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c +#define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010 +#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000 +#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010 +#define ixPB0_PLL_RO0_CTRL_REG0 0x1204440 +#define ixPB0_PLL_RO0_OVRD_REG0 0x1204450 +#define ixPB0_PLL_RO0_OVRD_REG1 0x1204454 +#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460 +#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464 +#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468 +#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c +#define ixPB0_PLL_LC0_CTRL_REG0 0x1204480 +#define ixPB0_PLL_LC0_OVRD_REG0 0x1204490 +#define ixPB0_PLL_LC0_OVRD_REG1 0x1204494 +#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500 +#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504 +#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508 +#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c +#define ixPB0_RX_GLB_CTRL_REG0 0x1206000 +#define ixPB0_RX_GLB_CTRL_REG1 0x1206004 +#define ixPB0_RX_GLB_CTRL_REG2 0x1206008 +#define ixPB0_RX_GLB_CTRL_REG3 0x120600c +#define ixPB0_RX_GLB_CTRL_REG4 0x1206010 +#define ixPB0_RX_GLB_CTRL_REG5 0x1206014 +#define ixPB0_RX_GLB_CTRL_REG6 0x1206018 +#define ixPB0_RX_GLB_CTRL_REG7 0x120601c +#define ixPB0_RX_GLB_CTRL_REG8 0x1206020 +#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028 +#define ixPB0_RX_GLB_OVRD_REG0 0x1206030 +#define ixPB0_RX_GLB_OVRD_REG1 0x1206034 +#define ixPB0_RX_LANE0_CTRL_REG0 0x1206440 +#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448 +#define ixPB0_RX_LANE1_CTRL_REG0 0x1206480 +#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488 +#define ixPB0_RX_LANE2_CTRL_REG0 0x1206500 +#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508 +#define ixPB0_RX_LANE3_CTRL_REG0 0x1206600 +#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608 +#define ixPB0_RX_LANE4_CTRL_REG0 0x1206800 +#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848 +#define ixPB0_RX_LANE5_CTRL_REG0 0x1206880 +#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888 +#define ixPB0_RX_LANE6_CTRL_REG0 0x1206900 +#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908 +#define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00 +#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08 +#define ixPB0_RX_LANE8_CTRL_REG0 0x1207440 +#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448 +#define ixPB0_RX_LANE9_CTRL_REG0 0x1207480 +#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488 +#define ixPB0_RX_LANE10_CTRL_REG0 0x1207500 +#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508 +#define ixPB0_RX_LANE11_CTRL_REG0 0x1207600 +#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608 +#define ixPB0_RX_LANE12_CTRL_REG0 0x1207840 +#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848 +#define ixPB0_RX_LANE13_CTRL_REG0 0x1207880 +#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888 +#define ixPB0_RX_LANE14_CTRL_REG0 0x1207900 +#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908 +#define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00 +#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08 +#define ixPB0_TX_GLB_CTRL_REG0 0x1208000 +#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004 +#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020 +#define ixPB0_TX_GLB_OVRD_REG0 0x1208030 +#define ixPB0_TX_GLB_OVRD_REG1 0x1208034 +#define ixPB0_TX_GLB_OVRD_REG2 0x1208038 +#define ixPB0_TX_GLB_OVRD_REG3 0x120803c +#define ixPB0_TX_GLB_OVRD_REG4 0x1208040 +#define ixPB0_TX_LANE0_CTRL_REG0 0x1208440 +#define ixPB0_TX_LANE0_OVRD_REG0 0x1208444 +#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448 +#define ixPB0_TX_LANE1_CTRL_REG0 0x1208480 +#define ixPB0_TX_LANE1_OVRD_REG0 0x1208484 +#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488 +#define ixPB0_TX_LANE2_CTRL_REG0 0x1208500 +#define ixPB0_TX_LANE2_OVRD_REG0 0x1208504 +#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508 +#define ixPB0_TX_LANE3_CTRL_REG0 0x1208600 +#define ixPB0_TX_LANE3_OVRD_REG0 0x1208604 +#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608 +#define ixPB0_TX_LANE4_CTRL_REG0 0x1208840 +#define ixPB0_TX_LANE4_OVRD_REG0 0x1208844 +#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848 +#define ixPB0_TX_LANE5_CTRL_REG0 0x1208880 +#define ixPB0_TX_LANE5_OVRD_REG0 0x1208884 +#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888 +#define ixPB0_TX_LANE6_CTRL_REG0 0x1208900 +#define ixPB0_TX_LANE6_OVRD_REG0 0x1208904 +#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908 +#define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00 +#define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04 +#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08 +#define ixPB0_TX_LANE8_CTRL_REG0 0x1209440 +#define ixPB0_TX_LANE8_OVRD_REG0 0x1209444 +#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448 +#define ixPB0_TX_LANE9_CTRL_REG0 0x1209480 +#define ixPB0_TX_LANE9_OVRD_REG0 0x1209484 +#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488 +#define ixPB0_TX_LANE10_CTRL_REG0 0x1209500 +#define ixPB0_TX_LANE10_OVRD_REG0 0x1209504 +#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508 +#define ixPB0_TX_LANE11_CTRL_REG0 0x1209600 +#define ixPB0_TX_LANE11_OVRD_REG0 0x1209604 +#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608 +#define ixPB0_TX_LANE12_CTRL_REG0 0x1209840 +#define ixPB0_TX_LANE12_OVRD_REG0 0x1209844 +#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848 +#define ixPB0_TX_LANE13_CTRL_REG0 0x1209880 +#define ixPB0_TX_LANE13_OVRD_REG0 0x1209884 +#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888 +#define ixPB0_TX_LANE14_CTRL_REG0 0x1209900 +#define ixPB0_TX_LANE14_OVRD_REG0 0x1209904 +#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908 +#define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00 +#define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04 +#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08 +#define ixPB1_GLB_CTRL_REG0 0x2200004 +#define ixPB1_GLB_CTRL_REG1 0x2200008 +#define ixPB1_GLB_CTRL_REG2 0x220000c +#define ixPB1_GLB_CTRL_REG3 0x2200010 +#define ixPB1_GLB_CTRL_REG4 0x2200014 +#define ixPB1_GLB_CTRL_REG5 0x2200018 +#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c +#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020 +#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024 +#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028 +#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c +#define ixPB1_GLB_OVRD_REG0 0x2200030 +#define ixPB1_GLB_OVRD_REG1 0x2200034 +#define ixPB1_GLB_OVRD_REG2 0x2200038 +#define ixPB1_HW_DEBUG 0x2202004 +#define ixPB1_STRAP_GLB_REG0 0x2202020 +#define ixPB1_STRAP_TX_REG0 0x2202024 +#define ixPB1_STRAP_RX_REG0 0x2202028 +#define ixPB1_STRAP_RX_REG1 0x220202c +#define ixPB1_STRAP_PLL_REG0 0x2202030 +#define ixPB1_STRAP_PIN_REG0 0x2202034 +#define ixPB1_DFT_JIT_INJ_REG0 0x2203000 +#define ixPB1_DFT_JIT_INJ_REG1 0x2203004 +#define ixPB1_DFT_JIT_INJ_REG2 0x2203008 +#define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c +#define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010 +#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000 +#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010 +#define ixPB1_PLL_RO0_CTRL_REG0 0x2204440 +#define ixPB1_PLL_RO0_OVRD_REG0 0x2204450 +#define ixPB1_PLL_RO0_OVRD_REG1 0x2204454 +#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460 +#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464 +#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468 +#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c +#define ixPB1_PLL_LC0_CTRL_REG0 0x2204480 +#define ixPB1_PLL_LC0_OVRD_REG0 0x2204490 +#define ixPB1_PLL_LC0_OVRD_REG1 0x2204494 +#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500 +#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504 +#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508 +#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c +#define ixPB1_RX_GLB_CTRL_REG0 0x2206000 +#define ixPB1_RX_GLB_CTRL_REG1 0x2206004 +#define ixPB1_RX_GLB_CTRL_REG2 0x2206008 +#define ixPB1_RX_GLB_CTRL_REG3 0x220600c +#define ixPB1_RX_GLB_CTRL_REG4 0x2206010 +#define ixPB1_RX_GLB_CTRL_REG5 0x2206014 +#define ixPB1_RX_GLB_CTRL_REG6 0x2206018 +#define ixPB1_RX_GLB_CTRL_REG7 0x220601c +#define ixPB1_RX_GLB_CTRL_REG8 0x2206020 +#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028 +#define ixPB1_RX_GLB_OVRD_REG0 0x2206030 +#define ixPB1_RX_GLB_OVRD_REG1 0x2206034 +#define ixPB1_RX_LANE0_CTRL_REG0 0x2206440 +#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448 +#define ixPB1_RX_LANE1_CTRL_REG0 0x2206480 +#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488 +#define ixPB1_RX_LANE2_CTRL_REG0 0x2206500 +#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508 +#define ixPB1_RX_LANE3_CTRL_REG0 0x2206600 +#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608 +#define ixPB1_RX_LANE4_CTRL_REG0 0x2206800 +#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848 +#define ixPB1_RX_LANE5_CTRL_REG0 0x2206880 +#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888 +#define ixPB1_RX_LANE6_CTRL_REG0 0x2206900 +#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908 +#define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00 +#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08 +#define ixPB1_RX_LANE8_CTRL_REG0 0x2207440 +#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448 +#define ixPB1_RX_LANE9_CTRL_REG0 0x2207480 +#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488 +#define ixPB1_RX_LANE10_CTRL_REG0 0x2207500 +#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508 +#define ixPB1_RX_LANE11_CTRL_REG0 0x2207600 +#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608 +#define ixPB1_RX_LANE12_CTRL_REG0 0x2207840 +#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848 +#define ixPB1_RX_LANE13_CTRL_REG0 0x2207880 +#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888 +#define ixPB1_RX_LANE14_CTRL_REG0 0x2207900 +#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908 +#define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00 +#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08 +#define ixPB1_TX_GLB_CTRL_REG0 0x2208000 +#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004 +#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020 +#define ixPB1_TX_GLB_OVRD_REG0 0x2208030 +#define ixPB1_TX_GLB_OVRD_REG1 0x2208034 +#define ixPB1_TX_GLB_OVRD_REG2 0x2208038 +#define ixPB1_TX_GLB_OVRD_REG3 0x220803c +#define ixPB1_TX_GLB_OVRD_REG4 0x2208040 +#define ixPB1_TX_LANE0_CTRL_REG0 0x2208440 +#define ixPB1_TX_LANE0_OVRD_REG0 0x2208444 +#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448 +#define ixPB1_TX_LANE1_CTRL_REG0 0x2208480 +#define ixPB1_TX_LANE1_OVRD_REG0 0x2208484 +#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488 +#define ixPB1_TX_LANE2_CTRL_REG0 0x2208500 +#define ixPB1_TX_LANE2_OVRD_REG0 0x2208504 +#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508 +#define ixPB1_TX_LANE3_CTRL_REG0 0x2208600 +#define ixPB1_TX_LANE3_OVRD_REG0 0x2208604 +#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608 +#define ixPB1_TX_LANE4_CTRL_REG0 0x2208840 +#define ixPB1_TX_LANE4_OVRD_REG0 0x2208844 +#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848 +#define ixPB1_TX_LANE5_CTRL_REG0 0x2208880 +#define ixPB1_TX_LANE5_OVRD_REG0 0x2208884 +#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888 +#define ixPB1_TX_LANE6_CTRL_REG0 0x2208900 +#define ixPB1_TX_LANE6_OVRD_REG0 0x2208904 +#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908 +#define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00 +#define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04 +#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08 +#define ixPB1_TX_LANE8_CTRL_REG0 0x2209440 +#define ixPB1_TX_LANE8_OVRD_REG0 0x2209444 +#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448 +#define ixPB1_TX_LANE9_CTRL_REG0 0x2209480 +#define ixPB1_TX_LANE9_OVRD_REG0 0x2209484 +#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488 +#define ixPB1_TX_LANE10_CTRL_REG0 0x2209500 +#define ixPB1_TX_LANE10_OVRD_REG0 0x2209504 +#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508 +#define ixPB1_TX_LANE11_CTRL_REG0 0x2209600 +#define ixPB1_TX_LANE11_OVRD_REG0 0x2209604 +#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608 +#define ixPB1_TX_LANE12_CTRL_REG0 0x2209840 +#define ixPB1_TX_LANE12_OVRD_REG0 0x2209844 +#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848 +#define ixPB1_TX_LANE13_CTRL_REG0 0x2209880 +#define ixPB1_TX_LANE13_OVRD_REG0 0x2209884 +#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888 +#define ixPB1_TX_LANE14_CTRL_REG0 0x2209900 +#define ixPB1_TX_LANE14_OVRD_REG0 0x2209904 +#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908 +#define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00 +#define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04 +#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08 +#define ixPB0_PIF_SCRATCH 0x1100001 +#define ixPB0_PIF_HW_DEBUG 0x1100002 +#define ixPB0_PIF_PRG6 0x1100003 +#define ixPB0_PIF_PRG7 0x1100004 +#define ixPB0_PIF_CNTL 0x1100010 +#define ixPB0_PIF_PAIRING 0x1100011 +#define ixPB0_PIF_PWRDOWN_0 0x1100012 +#define ixPB0_PIF_PWRDOWN_1 0x1100013 +#define ixPB0_PIF_CNTL2 0x1100014 +#define ixPB0_PIF_TXPHYSTATUS 0x1100015 +#define ixPB0_PIF_SC_CTL 0x1100016 +#define ixPB0_PIF_PWRDOWN_2 0x1100017 +#define ixPB0_PIF_PWRDOWN_3 0x1100018 +#define ixPB0_PIF_SC_CTL2 0x1100019 +#define ixPB0_PIF_PRG0 0x110001a +#define ixPB0_PIF_PRG1 0x110001b +#define ixPB0_PIF_PRG2 0x110001c +#define ixPB0_PIF_PRG3 0x110001d +#define ixPB0_PIF_PRG4 0x110001e +#define ixPB0_PIF_PRG5 0x110001f +#define ixPB0_PIF_PDNB_OVERRIDE_0 0x1100020 +#define ixPB0_PIF_PDNB_OVERRIDE_1 0x1100021 +#define ixPB0_PIF_PDNB_OVERRIDE_2 0x1100022 +#define ixPB0_PIF_PDNB_OVERRIDE_3 0x1100023 +#define ixPB0_PIF_PDNB_OVERRIDE_4 0x1100024 +#define ixPB0_PIF_PDNB_OVERRIDE_5 0x1100025 +#define ixPB0_PIF_PDNB_OVERRIDE_6 0x1100026 +#define ixPB0_PIF_PDNB_OVERRIDE_7 0x1100027 +#define ixPB0_PIF_SEQ_STATUS_0 0x1100028 +#define ixPB0_PIF_SEQ_STATUS_1 0x1100029 +#define ixPB0_PIF_SEQ_STATUS_2 0x110002a +#define ixPB0_PIF_SEQ_STATUS_3 0x110002b +#define ixPB0_PIF_SEQ_STATUS_4 0x110002c +#define ixPB0_PIF_SEQ_STATUS_5 0x110002d +#define ixPB0_PIF_SEQ_STATUS_6 0x110002e +#define ixPB0_PIF_SEQ_STATUS_7 0x110002f +#define ixPB0_PIF_PDNB_OVERRIDE_8 0x1100030 +#define ixPB0_PIF_PDNB_OVERRIDE_9 0x1100031 +#define ixPB0_PIF_PDNB_OVERRIDE_10 0x1100032 +#define ixPB0_PIF_PDNB_OVERRIDE_11 0x1100033 +#define ixPB0_PIF_PDNB_OVERRIDE_12 0x1100034 +#define ixPB0_PIF_PDNB_OVERRIDE_13 0x1100035 +#define ixPB0_PIF_PDNB_OVERRIDE_14 0x1100036 +#define ixPB0_PIF_PDNB_OVERRIDE_15 0x1100037 +#define ixPB0_PIF_SEQ_STATUS_8 0x1100038 +#define ixPB0_PIF_SEQ_STATUS_9 0x1100039 +#define ixPB0_PIF_SEQ_STATUS_10 0x110003a +#define ixPB0_PIF_SEQ_STATUS_11 0x110003b +#define ixPB0_PIF_SEQ_STATUS_12 0x110003c +#define ixPB0_PIF_SEQ_STATUS_13 0x110003d +#define ixPB0_PIF_SEQ_STATUS_14 0x110003e +#define ixPB0_PIF_SEQ_STATUS_15 0x110003f +#define ixPB1_PIF_SCRATCH 0x2100001 +#define ixPB1_PIF_HW_DEBUG 0x2100002 +#define ixPB1_PIF_PRG6 0x2100003 +#define ixPB1_PIF_PRG7 0x2100004 +#define ixPB1_PIF_CNTL 0x2100010 +#define ixPB1_PIF_PAIRING 0x2100011 +#define ixPB1_PIF_PWRDOWN_0 0x2100012 +#define ixPB1_PIF_PWRDOWN_1 0x2100013 +#define ixPB1_PIF_CNTL2 0x2100014 +#define ixPB1_PIF_TXPHYSTATUS 0x2100015 +#define ixPB1_PIF_SC_CTL 0x2100016 +#define ixPB1_PIF_PWRDOWN_2 0x2100017 +#define ixPB1_PIF_PWRDOWN_3 0x2100018 +#define ixPB1_PIF_SC_CTL2 0x2100019 +#define ixPB1_PIF_PRG0 0x210001a +#define ixPB1_PIF_PRG1 0x210001b +#define ixPB1_PIF_PRG2 0x210001c +#define ixPB1_PIF_PRG3 0x210001d +#define ixPB1_PIF_PRG4 0x210001e +#define ixPB1_PIF_PRG5 0x210001f +#define ixPB1_PIF_PDNB_OVERRIDE_0 0x2100020 +#define ixPB1_PIF_PDNB_OVERRIDE_1 0x2100021 +#define ixPB1_PIF_PDNB_OVERRIDE_2 0x2100022 +#define ixPB1_PIF_PDNB_OVERRIDE_3 0x2100023 +#define ixPB1_PIF_PDNB_OVERRIDE_4 0x2100024 +#define ixPB1_PIF_PDNB_OVERRIDE_5 0x2100025 +#define ixPB1_PIF_PDNB_OVERRIDE_6 0x2100026 +#define ixPB1_PIF_PDNB_OVERRIDE_7 0x2100027 +#define ixPB1_PIF_SEQ_STATUS_0 0x2100028 +#define ixPB1_PIF_SEQ_STATUS_1 0x2100029 +#define ixPB1_PIF_SEQ_STATUS_2 0x210002a +#define ixPB1_PIF_SEQ_STATUS_3 0x210002b +#define ixPB1_PIF_SEQ_STATUS_4 0x210002c +#define ixPB1_PIF_SEQ_STATUS_5 0x210002d +#define ixPB1_PIF_SEQ_STATUS_6 0x210002e +#define ixPB1_PIF_SEQ_STATUS_7 0x210002f +#define ixPB1_PIF_PDNB_OVERRIDE_8 0x2100030 +#define ixPB1_PIF_PDNB_OVERRIDE_9 0x2100031 +#define ixPB1_PIF_PDNB_OVERRIDE_10 0x2100032 +#define ixPB1_PIF_PDNB_OVERRIDE_11 0x2100033 +#define ixPB1_PIF_PDNB_OVERRIDE_12 0x2100034 +#define ixPB1_PIF_PDNB_OVERRIDE_13 0x2100035 +#define ixPB1_PIF_PDNB_OVERRIDE_14 0x2100036 +#define ixPB1_PIF_PDNB_OVERRIDE_15 0x2100037 +#define ixPB1_PIF_SEQ_STATUS_8 0x2100038 +#define ixPB1_PIF_SEQ_STATUS_9 0x2100039 +#define ixPB1_PIF_SEQ_STATUS_10 0x210003a +#define ixPB1_PIF_SEQ_STATUS_11 0x210003b +#define ixPB1_PIF_SEQ_STATUS_12 0x210003c +#define ixPB1_PIF_SEQ_STATUS_13 0x210003d +#define ixPB1_PIF_SEQ_STATUS_14 0x210003e +#define ixPB1_PIF_SEQ_STATUS_15 0x210003f +#define mmBIF_RFE_SNOOP_REG 0x27 +#define mmBIF_RFE_WARMRST_CNTL 0x1459 +#define mmBIF_RFE_SOFTRST_CNTL 0x1441 +#define mmBIF_RFE_IMPRST_CNTL 0x1458 +#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442 +#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443 +#define mmBIF_PWDN_COMMAND 0x1444 +#define mmBIF_PWDN_STATUS 0x1445 +#define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446 +#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447 +#define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448 +#define mmBIF_RFE_MST_TMOUT_STATUS 0x144b +#define mmBIF_RFE_MMCFG_CNTL 0x144c +#define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455 +#define mmBIF_IMPCTL_SMPLCNTL 0x1450 +#define mmBIF_IMPCTL_RXCNTL 0x1451 +#define mmBIF_IMPCTL_TXCNTL_pd 0x1452 +#define mmBIF_IMPCTL_TXCNTL_pu 0x1453 +#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454 +#define mmBIF_CLOCKS_BITS 0x1489 +#define mmBIF_LNCNT_RESET 0x1488 +#define mmLNCNT_CONTROL 0x1487 +#define mmNEW_REFCLKB_TIMER 0x1485 +#define mmNEW_REFCLKB_TIMER_1 0x1484 +#define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483 +#define mmBIF_RESET_EN 0x1482 +#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481 +#define mmBIF_BACO_MSIC 0x1480 +#define mmBIF_RESET_CNTL 0x1486 +#define mmBIF_RFE_CNTL_MISC 0x148c + +#endif /* BIF_4_1_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h new file mode 100644 index 000000000000..8fbfd0261d27 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h @@ -0,0 +1,10250 @@ +/* + * BIF_4_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_4_1_SH_MASK_H +#define BIF_4_1_SH_MASK_H + +#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff +#define MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define MM_INDEX__MM_APER_MASK 0x80000000 +#define MM_INDEX__MM_APER__SHIFT 0x1f +#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff +#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define MM_DATA__MM_DATA_MASK 0xffffffff +#define MM_DATA__MM_DATA__SHIFT 0x0 +#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1 +#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0 +#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2 +#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1 +#define BUS_CNTL__PMI_IO_DIS_MASK 0x4 +#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8 +#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define BUS_CNTL__PMI_BM_DIS_MASK 0x10 +#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define BUS_CNTL__PMI_INT_DIS_MASK 0x20 +#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5 +#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40 +#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80 +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100 +#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8 +#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00 +#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BUS_CNTL__SET_MC_TC_MASK 0xe000 +#define BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000 +#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000 +#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000 +#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1 +#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define CONFIG_CNTL__VGA_DIS_MASK 0x2 +#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1 +#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4 +#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18 +#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff +#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff +#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff +#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff +#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff +#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff +#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BX_RESET_EN__COR_RESET_EN_MASK 0x1 +#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 +#define BX_RESET_EN__REG_RESET_EN_MASK 0x2 +#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 +#define BX_RESET_EN__STY_RESET_EN_MASK 0x4 +#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7 +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8 +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3 +#define HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000 +#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 +#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000 +#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 +#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000 +#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 +#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000 +#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 +#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000 +#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 +#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000 +#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 +#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000 +#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 +#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000 +#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 +#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 +#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 +#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 +#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 +#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 +#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a +#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 +#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b +#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 +#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c +#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 +#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d +#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 +#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e +#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 +#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f +#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f +#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0 +#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000 +#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10 +#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f +#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0 +#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0 +#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5 +#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00 +#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa +#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000 +#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf +#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000 +#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14 +#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000 +#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19 +#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1 +#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1 +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2 +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8 +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0 +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100 +#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00 +#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9 +#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000 +#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1 +#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0 +#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2 +#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1 +#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4 +#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2 +#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8 +#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6 +#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80 +#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0 +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00 +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8 +#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff +#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0 +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1 +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1 +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define SMBUS_SLV_CNTL__SMB_SOFT_RESET_MASK 0x1 +#define SMBUS_SLV_CNTL__SMB_SOFT_RESET__SHIFT 0x0 +#define SMBUS_SLV_CNTL__SMB_SLV_ADR_MASK 0xfe +#define SMBUS_SLV_CNTL__SMB_SLV_ADR__SHIFT 0x1 +#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_THRESHOLD_MASK 0x3fffff +#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_THRESHOLD__SHIFT 0x0 +#define SMBUS_SLV_CNTL1__SMB_XTALIN_FREQUENCY_SEL_MASK 0x1000000 +#define SMBUS_SLV_CNTL1__SMB_XTALIN_FREQUENCY_SEL__SHIFT 0x18 +#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_DIS_MASK 0x2000000 +#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_DIS__SHIFT 0x19 +#define SMBUS_SLV_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0xfc000000 +#define SMBUS_SLV_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x1a +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x1 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x0 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x2 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x1 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x4 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x2 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x18 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x3 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x20 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x5 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x40 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x6 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x80 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x7 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x100 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x8 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x200 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x9 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x400 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x800 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0xb +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x1000 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0xc +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x1 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x0 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x2 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x1 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x4 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x2 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x18 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x3 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x20 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x5 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x40 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x6 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x80 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x7 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x100 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x8 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x200 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x9 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x400 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x800 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0xb +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x1000 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0xc +#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff +#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000 +#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff +#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1 +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2 +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4 +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8 +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10 +#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 +#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80 +#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7 +#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100 +#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8 +#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200 +#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 +#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400 +#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa +#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800 +#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb +#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1 +#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2 +#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4 +#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8 +#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3 +#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0 +#define BIF_FB_EN__FB_READ_EN_MASK 0x1 +#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2 +#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff +#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define BIF_BUSNUM_LIST0__ID0_MASK 0xff +#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00 +#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000 +#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000 +#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define BIF_BUSNUM_LIST1__ID4_MASK 0xff +#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00 +#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000 +#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000 +#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000 +#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000 +#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 +#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1 +#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2 +#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00 +#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8 +#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000 +#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd +#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff +#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 +#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff +#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 +#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe +#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1 +#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1 +#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2 +#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4 +#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8 +#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10 +#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20 +#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40 +#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80 +#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100 +#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200 +#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400 +#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800 +#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1 +#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2 +#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4 +#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8 +#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10 +#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20 +#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40 +#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80 +#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100 +#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200 +#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400 +#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800 +#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1 +#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0 +#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2 +#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1 +#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4 +#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2 +#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8 +#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3 +#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10 +#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4 +#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20 +#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5 +#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80 +#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7 +#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100 +#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8 +#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200 +#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9 +#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1 +#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define HOST_BUSNUM__HOST_ID_MASK 0xffff +#define HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff +#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000 +#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff +#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000 +#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff +#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff +#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000 +#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff +#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff +#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000 +#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff +#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff +#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000 +#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff +#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff +#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000 +#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1 +#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0 +#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD_MASK 0x1e +#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD__SHIFT 0x1 +#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff +#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define BACO_CNTL__BACO_EN_MASK 0x1 +#define BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2 +#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1 +#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4 +#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2 +#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8 +#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BACO_CNTL__BACO_RESET_EN_MASK 0x10 +#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4 +#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20 +#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5 +#define BACO_CNTL__BACO_MODE_MASK 0x40 +#define BACO_CNTL__BACO_MODE__SHIFT 0x6 +#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80 +#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7 +#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100 +#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8 +#define BACO_CNTL__PWRGOOD_BF_MASK 0x200 +#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9 +#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400 +#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa +#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800 +#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb +#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000 +#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc +#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000 +#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd +#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000 +#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10 +#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000 +#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11 +#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1 +#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0 +#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2 +#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1 +#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1 +#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1 +#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0 +#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1 +#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0 +#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1 +#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2 +#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc +#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2 +#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS_MASK 0x1 +#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS__SHIFT 0x0 +#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS_MASK 0x2 +#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS__SHIFT 0x1 +#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS_MASK 0x4 +#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS__SHIFT 0x2 +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER_MASK 0x3fffc +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER__SHIFT 0x2 +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN_MASK 0x40000000 +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN__SHIFT 0x1e +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN_MASK 0x80000000 +#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN__SHIFT 0x1f +#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER_MASK 0x3fffc +#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER__SHIFT 0x2 +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER_MASK 0x3fffc +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER__SHIFT 0x2 +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK 0x40000000 +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN__SHIFT 0x1e +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN_MASK 0x80000000 +#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN__SHIFT 0x1f +#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER_MASK 0x3fffc +#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER__SHIFT 0x2 +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER_MASK 0x3fffc +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER__SHIFT 0x2 +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN_MASK 0x40000000 +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN__SHIFT 0x1e +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN_MASK 0x80000000 +#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN__SHIFT 0x1f +#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER_MASK 0x3fffc +#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER__SHIFT 0x2 +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER_MASK 0x3fffc +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER__SHIFT 0x2 +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN_MASK 0x40000000 +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN__SHIFT 0x1e +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN_MASK 0x80000000 +#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN__SHIFT 0x1f +#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER_MASK 0x3fffc +#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER__SHIFT 0x2 +#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER_MASK 0x3fffc +#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER__SHIFT 0x2 +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN_MASK 0x40000000 +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN__SHIFT 0x1e +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN_MASK 0x80000000 +#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN__SHIFT 0x1f +#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER_MASK 0x3fffc +#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER__SHIFT 0x2 +#define BIF_SSA_MC_LOWER__SSA_MC_LOWER_MASK 0x3fffc +#define BIF_SSA_MC_LOWER__SSA_MC_LOWER__SHIFT 0x2 +#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN_MASK 0x20000000 +#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT 0x1d +#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN_MASK 0x40000000 +#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN__SHIFT 0x1e +#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN_MASK 0x80000000 +#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN__SHIFT 0x1f +#define BIF_SSA_MC_UPPER__SSA_MC_UPPER_MASK 0x3fffc +#define BIF_SSA_MC_UPPER__SSA_MC_UPPER__SHIFT 0x2 +#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1 +#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0 +#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1 +#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0 +#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2 +#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1 +#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4 +#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2 +#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8 +#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3 +#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10 +#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4 +#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20 +#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5 +#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40 +#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6 +#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80 +#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9 +#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400 +#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800 +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000 +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc +#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000 +#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd +#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000 +#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe +#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000 +#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10 +#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000 +#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e +#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000 +#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f +#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1 +#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1 +#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2 +#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1 +#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4 +#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2 +#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8 +#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3 +#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10 +#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4 +#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20 +#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5 +#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40 +#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6 +#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80 +#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7 +#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100 +#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8 +#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200 +#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9 +#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400 +#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa +#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800 +#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb +#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1 +#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2 +#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1 +#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4 +#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2 +#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8 +#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3 +#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10 +#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4 +#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20 +#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5 +#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40 +#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6 +#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80 +#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7 +#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100 +#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8 +#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200 +#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9 +#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400 +#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa +#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800 +#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb +#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT 0x2 +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define VENDOR_ID__VENDOR_ID_MASK 0xffff +#define VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define DEVICE_ID__DEVICE_ID_MASK 0xffff +#define DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define COMMAND__IO_ACCESS_EN_MASK 0x1 +#define COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define COMMAND__BUS_MASTER_EN_MASK 0x4 +#define COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define COMMAND__AD_STEPPING_MASK 0x80 +#define COMMAND__AD_STEPPING__SHIFT 0x7 +#define COMMAND__SERR_EN_MASK 0x100 +#define COMMAND__SERR_EN__SHIFT 0x8 +#define COMMAND__FAST_B2B_EN_MASK 0x200 +#define COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define COMMAND__INT_DIS_MASK 0x400 +#define COMMAND__INT_DIS__SHIFT 0xa +#define STATUS__INT_STATUS_MASK 0x8 +#define STATUS__INT_STATUS__SHIFT 0x3 +#define STATUS__CAP_LIST_MASK 0x10 +#define STATUS__CAP_LIST__SHIFT 0x4 +#define STATUS__PCI_66_EN_MASK 0x20 +#define STATUS__PCI_66_EN__SHIFT 0x5 +#define STATUS__FAST_BACK_CAPABLE_MASK 0x80 +#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100 +#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define STATUS__DEVSEL_TIMING_MASK 0x600 +#define STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800 +#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000 +#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000 +#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000 +#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000 +#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define REVISION_ID__MINOR_REV_ID_MASK 0xf +#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff +#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define SUB_CLASS__SUB_CLASS_MASK 0xff +#define SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BASE_CLASS__BASE_CLASS_MASK 0xff +#define BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define LATENCY__LATENCY_TIMER_MASK 0xff +#define LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define HEADER__HEADER_TYPE_MASK 0x7f +#define HEADER__HEADER_TYPE__SHIFT 0x0 +#define HEADER__DEVICE_TYPE_MASK 0x80 +#define HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIST__BIST_COMP_MASK 0xf +#define BIST__BIST_COMP__SHIFT 0x0 +#define BIST__BIST_STRT_MASK 0x40 +#define BIST__BIST_STRT__SHIFT 0x6 +#define BIST__BIST_CAP_MASK 0x80 +#define BIST__BIST_CAP__SHIFT 0x7 +#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff +#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CAP_PTR__CAP_PTR_MASK 0xff +#define CAP_PTR__CAP_PTR__SHIFT 0x0 +#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff +#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000 +#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define MIN_GRANT__MIN_GNT_MASK 0xff +#define MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define MAX_LATENCY__MAX_LAT_MASK 0xff +#define MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff +#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000 +#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000 +#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define PMI_CAP_LIST__CAP_ID_MASK 0xff +#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PMI_CAP__VERSION_MASK 0x7 +#define PMI_CAP__VERSION__SHIFT 0x0 +#define PMI_CAP__PME_CLOCK_MASK 0x8 +#define PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20 +#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define PMI_CAP__AUX_CURRENT_MASK 0x1c0 +#define PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define PMI_CAP__D1_SUPPORT_MASK 0x200 +#define PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define PMI_CAP__D2_SUPPORT_MASK 0x400 +#define PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define PMI_CAP__PME_SUPPORT_MASK 0xf800 +#define PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PCIE_CAP__VERSION_MASK 0xf +#define PCIE_CAP__VERSION__SHIFT 0x0 +#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0 +#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100 +#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00 +#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000 +#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define DEVICE_STATUS__CORR_ERR_MASK 0x1 +#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2 +#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define DEVICE_STATUS__FATAL_ERR_MASK 0x4 +#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define DEVICE_STATUS__USR_DETECTED_MASK 0x8 +#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define DEVICE_STATUS__AUX_PWR_MASK 0x10 +#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20 +#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define LINK_CAP__LINK_SPEED_MASK 0xf +#define LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define LINK_CNTL__PM_CONTROL_MASK 0x3 +#define LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define LINK_CNTL__LINK_DIS_MASK 0x10 +#define LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf +#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0 +#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define LINK_STATUS__LINK_TRAINING_MASK 0x800 +#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000 +#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define LINK_STATUS__DL_ACTIVE_MASK 0x2000 +#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000 +#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000 +#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define DEVICE_STATUS2__RESERVED_MASK 0xffff +#define DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define LINK_CAP2__RESERVED__SHIFT 0x9 +#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1 +#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2 +#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4 +#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8 +#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10 +#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20 +#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define MSI_CAP_LIST__CAP_ID_MASK 0xff +#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define MSI_MSG_CNTL__MSI_EN_MASK 0x1 +#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe +#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70 +#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80 +#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1 +#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 +#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 +#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 +#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 +#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff +#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300 +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00 +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000 +#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000 +#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000 +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1 +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f +#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 +#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f +#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100 +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f +#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1 +#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2 +#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4 +#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8 +#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10 +#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20 +#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40 +#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f +#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20 +#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40 +#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define PCIE_ATS_CNTL__STU_MASK 0x1f +#define PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000 +#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1 +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2 +#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1 +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2 +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100 +#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000 +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2 +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4 +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00 +#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1 +#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2 +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4 +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1 +#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 +#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2 +#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 +#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4 +#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 +#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100 +#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 +#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00 +#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f +#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000 +#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff +#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff +#define PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff +#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0 +#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff +#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0 +#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff +#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff +#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff +#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 +#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1 +#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 +#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80 +#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100 +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200 +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00 +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000 +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf +#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000 +#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000 +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000 +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000 +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 +#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x100000 +#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x14 +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000 +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000 +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000 +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 +#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000 +#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 +#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000 +#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000 +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000 +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000 +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff +#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 +#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100 +#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 +#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000 +#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 +#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1 +#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2 +#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4 +#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8 +#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10 +#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40 +#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80 +#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7 +#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100 +#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8 +#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1 +#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2 +#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4 +#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8 +#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10 +#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40 +#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80 +#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7 +#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100 +#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8 +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1 +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 +#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0 +#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 +#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800 +#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb +#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 +#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 +#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000 +#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 +#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000 +#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 +#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000 +#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 +#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000 +#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 +#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000 +#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000 +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4 +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8 +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10 +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0 +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100 +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200 +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc +#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000 +#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd +#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40 +#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80 +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000 +#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc +#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f +#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 +#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00 +#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 +#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000 +#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 +#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000 +#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 +#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f +#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 +#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00 +#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 +#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000 +#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 +#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000 +#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 +#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f +#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 +#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00 +#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 +#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000 +#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 +#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000 +#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 +#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f +#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 +#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00 +#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 +#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000 +#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 +#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000 +#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 +#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f +#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 +#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00 +#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 +#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000 +#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 +#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000 +#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 +#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f +#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 +#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00 +#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 +#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000 +#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 +#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000 +#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2 +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0 +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000 +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1 +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8 +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10 +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20 +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40 +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 +#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff +#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1 +#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 +#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2 +#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 +#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4 +#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2 +#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8 +#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3 +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10 +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20 +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40 +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80 +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100 +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 +#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000 +#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000 +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000 +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe +#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000 +#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000 +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000 +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 +#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1 +#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1 +#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4 +#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2 +#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8 +#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc +#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000 +#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10 +#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000 +#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11 +#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000 +#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12 +#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000 +#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 +#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1 +#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2 +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4 +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 +#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8 +#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10 +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 +#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20 +#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40 +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80 +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100 +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200 +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400 +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800 +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000 +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc +#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000 +#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd +#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000 +#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe +#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000 +#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000 +#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000 +#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x1 +#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x0 +#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2 +#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4 +#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2 +#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8 +#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3 +#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10 +#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4 +#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20 +#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5 +#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40 +#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6 +#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80 +#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7 +#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100 +#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8 +#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200 +#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9 +#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400 +#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa +#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800 +#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb +#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000 +#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc +#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000 +#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd +#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000 +#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe +#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000 +#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000 +#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x1 +#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x0 +#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2 +#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4 +#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2 +#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8 +#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3 +#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10 +#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4 +#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20 +#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5 +#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40 +#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6 +#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80 +#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7 +#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100 +#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8 +#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200 +#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9 +#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400 +#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa +#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800 +#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb +#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000 +#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc +#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000 +#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd +#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000 +#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe +#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000 +#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000 +#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_F7__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F7__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0xf +#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x0 +#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10 +#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 +#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00 +#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8 +#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000 +#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd +#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000 +#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe +#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000 +#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000 +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000 +#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19 +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000 +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000 +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000 +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000 +#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e +#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000 +#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2 +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4 +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8 +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 +#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10 +#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1 +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 +#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80 +#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 +#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff +#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 +#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000 +#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 +#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000 +#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 +#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff +#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 +#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1 +#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 +#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x6 +#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x8 +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x3 +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x10 +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x4 +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x60 +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x5 +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0xf80 +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x7 +#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000 +#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000 +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 +#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 +#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 +#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff +#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f +#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000 +#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000 +#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000 +#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define PCIE_FC_P__PD_CREDITS_MASK 0xff +#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc +#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd +#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define PB0_GLB_CTRL_REG0__BACKUP_MASK 0xffff +#define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x0 +#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000 +#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10 +#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000 +#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14 +#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000 +#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17 +#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000 +#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18 +#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000 +#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19 +#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000 +#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a +#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000 +#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8 +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000 +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000 +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000 +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16 +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000 +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17 +#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000 +#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e +#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000 +#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1 +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0 +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19 +#define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f +#define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7 +#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600 +#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9 +#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800 +#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb +#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000 +#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc +#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000 +#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe +#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000 +#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12 +#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000 +#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15 +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000 +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16 +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000 +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17 +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000 +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000 +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c +#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000 +#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12 +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000 +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16 +#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000 +#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a +#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000 +#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b +#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000 +#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c +#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff +#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x8 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x3 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc +#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000 +#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x30000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x300000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x14 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x3000000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x18 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x1c +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x30000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x300000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x14 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x3000000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x18 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x1c +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x30000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x300000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x14 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x3000000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x18 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x1c +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x30000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x300000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x14 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x3000000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x18 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x1c +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e +#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff +#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0 +#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000 +#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10 +#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1 +#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0 +#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2 +#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3 +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000 +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000 +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1 +#define PB0_HW_DEBUG__PB0_HW_00_DEBUG_MASK 0x1 +#define PB0_HW_DEBUG__PB0_HW_00_DEBUG__SHIFT 0x0 +#define PB0_HW_DEBUG__PB0_HW_01_DEBUG_MASK 0x2 +#define PB0_HW_DEBUG__PB0_HW_01_DEBUG__SHIFT 0x1 +#define PB0_HW_DEBUG__PB0_HW_02_DEBUG_MASK 0x4 +#define PB0_HW_DEBUG__PB0_HW_02_DEBUG__SHIFT 0x2 +#define PB0_HW_DEBUG__PB0_HW_03_DEBUG_MASK 0x8 +#define PB0_HW_DEBUG__PB0_HW_03_DEBUG__SHIFT 0x3 +#define PB0_HW_DEBUG__PB0_HW_04_DEBUG_MASK 0x10 +#define PB0_HW_DEBUG__PB0_HW_04_DEBUG__SHIFT 0x4 +#define PB0_HW_DEBUG__PB0_HW_05_DEBUG_MASK 0x20 +#define PB0_HW_DEBUG__PB0_HW_05_DEBUG__SHIFT 0x5 +#define PB0_HW_DEBUG__PB0_HW_06_DEBUG_MASK 0x40 +#define PB0_HW_DEBUG__PB0_HW_06_DEBUG__SHIFT 0x6 +#define PB0_HW_DEBUG__PB0_HW_07_DEBUG_MASK 0x80 +#define PB0_HW_DEBUG__PB0_HW_07_DEBUG__SHIFT 0x7 +#define PB0_HW_DEBUG__PB0_HW_08_DEBUG_MASK 0x100 +#define PB0_HW_DEBUG__PB0_HW_08_DEBUG__SHIFT 0x8 +#define PB0_HW_DEBUG__PB0_HW_09_DEBUG_MASK 0x200 +#define PB0_HW_DEBUG__PB0_HW_09_DEBUG__SHIFT 0x9 +#define PB0_HW_DEBUG__PB0_HW_10_DEBUG_MASK 0x400 +#define PB0_HW_DEBUG__PB0_HW_10_DEBUG__SHIFT 0xa +#define PB0_HW_DEBUG__PB0_HW_11_DEBUG_MASK 0x800 +#define PB0_HW_DEBUG__PB0_HW_11_DEBUG__SHIFT 0xb +#define PB0_HW_DEBUG__PB0_HW_12_DEBUG_MASK 0x1000 +#define PB0_HW_DEBUG__PB0_HW_12_DEBUG__SHIFT 0xc +#define PB0_HW_DEBUG__PB0_HW_13_DEBUG_MASK 0x2000 +#define PB0_HW_DEBUG__PB0_HW_13_DEBUG__SHIFT 0xd +#define PB0_HW_DEBUG__PB0_HW_14_DEBUG_MASK 0x4000 +#define PB0_HW_DEBUG__PB0_HW_14_DEBUG__SHIFT 0xe +#define PB0_HW_DEBUG__PB0_HW_15_DEBUG_MASK 0x8000 +#define PB0_HW_DEBUG__PB0_HW_15_DEBUG__SHIFT 0xf +#define PB0_HW_DEBUG__PB0_HW_16_DEBUG_MASK 0x10000 +#define PB0_HW_DEBUG__PB0_HW_16_DEBUG__SHIFT 0x10 +#define PB0_HW_DEBUG__PB0_HW_17_DEBUG_MASK 0x20000 +#define PB0_HW_DEBUG__PB0_HW_17_DEBUG__SHIFT 0x11 +#define PB0_HW_DEBUG__PB0_HW_18_DEBUG_MASK 0x40000 +#define PB0_HW_DEBUG__PB0_HW_18_DEBUG__SHIFT 0x12 +#define PB0_HW_DEBUG__PB0_HW_19_DEBUG_MASK 0x80000 +#define PB0_HW_DEBUG__PB0_HW_19_DEBUG__SHIFT 0x13 +#define PB0_HW_DEBUG__PB0_HW_20_DEBUG_MASK 0x100000 +#define PB0_HW_DEBUG__PB0_HW_20_DEBUG__SHIFT 0x14 +#define PB0_HW_DEBUG__PB0_HW_21_DEBUG_MASK 0x200000 +#define PB0_HW_DEBUG__PB0_HW_21_DEBUG__SHIFT 0x15 +#define PB0_HW_DEBUG__PB0_HW_22_DEBUG_MASK 0x400000 +#define PB0_HW_DEBUG__PB0_HW_22_DEBUG__SHIFT 0x16 +#define PB0_HW_DEBUG__PB0_HW_23_DEBUG_MASK 0x800000 +#define PB0_HW_DEBUG__PB0_HW_23_DEBUG__SHIFT 0x17 +#define PB0_HW_DEBUG__PB0_HW_24_DEBUG_MASK 0x1000000 +#define PB0_HW_DEBUG__PB0_HW_24_DEBUG__SHIFT 0x18 +#define PB0_HW_DEBUG__PB0_HW_25_DEBUG_MASK 0x2000000 +#define PB0_HW_DEBUG__PB0_HW_25_DEBUG__SHIFT 0x19 +#define PB0_HW_DEBUG__PB0_HW_26_DEBUG_MASK 0x4000000 +#define PB0_HW_DEBUG__PB0_HW_26_DEBUG__SHIFT 0x1a +#define PB0_HW_DEBUG__PB0_HW_27_DEBUG_MASK 0x8000000 +#define PB0_HW_DEBUG__PB0_HW_27_DEBUG__SHIFT 0x1b +#define PB0_HW_DEBUG__PB0_HW_28_DEBUG_MASK 0x10000000 +#define PB0_HW_DEBUG__PB0_HW_28_DEBUG__SHIFT 0x1c +#define PB0_HW_DEBUG__PB0_HW_29_DEBUG_MASK 0x20000000 +#define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT 0x1d +#define PB0_HW_DEBUG__PB0_HW_30_DEBUG_MASK 0x40000000 +#define PB0_HW_DEBUG__PB0_HW_30_DEBUG__SHIFT 0x1e +#define PB0_HW_DEBUG__PB0_HW_31_DEBUG_MASK 0x80000000 +#define PB0_HW_DEBUG__PB0_HW_31_DEBUG__SHIFT 0x1f +#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2 +#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1 +#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4 +#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2 +#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8 +#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3 +#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60 +#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5 +#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80 +#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7 +#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000 +#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc +#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000 +#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd +#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000 +#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf +#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000 +#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c +#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000 +#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5 +#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40 +#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7 +#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300 +#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8 +#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00 +#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18 +#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000 +#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1 +#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c +#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2 +#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60 +#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4 +#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000 +#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18 +#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2 +#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1 +#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4 +#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2 +#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f +#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0 +#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80 +#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7 +#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00 +#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8 +#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000 +#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14 +#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000 +#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15 +#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000 +#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16 +#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000 +#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17 +#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000 +#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18 +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0 +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100 +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8 +#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000 +#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10 +#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000 +#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11 +#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000 +#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14 +#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff +#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0 +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1 +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0 +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1 +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0 +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00 +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8 +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000 +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x10000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x10 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x20000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x11 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x40000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x12 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x80000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x13 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x100000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x14 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x200000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x15 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x400000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x16 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x800000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x17 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4 +#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800 +#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x300 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x8 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x300 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x8 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x300 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x8 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x300 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x8 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3 +#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10 +#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x300 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x8 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x300 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x8 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x300 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x8 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x300 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x8 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x1e +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d +#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000 +#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000 +#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d +#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000 +#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x1e +#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000 +#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a +#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000 +#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b +#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000 +#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8 +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000 +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000 +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd +#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x20000 +#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x11 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d +#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3 +#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc +#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x1 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x0 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x2 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x1 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x4 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x2 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x8 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x3 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x10 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x4 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x20 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x5 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x40 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x6 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x80 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x7 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x100 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x8 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x200 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x9 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x400 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0xa +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x800 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0xb +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x1000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0xc +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x2000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0xd +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x4000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0xe +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x8000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0xf +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x10000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x10 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x20000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x11 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x40000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x12 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x80000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x13 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x100000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x14 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x200000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x15 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x400000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x16 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x800000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x17 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000 +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000 +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10 +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000 +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11 +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000 +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16 +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x800000 +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x17 +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x1000000 +#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x18 +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000 +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000 +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1 +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0 +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2 +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1 +#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff +#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0 +#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00 +#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa +#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000 +#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc +#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000 +#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x70 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x4 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9 +#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff +#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0 +#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00 +#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa +#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000 +#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc +#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000 +#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x70 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x4 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9 +#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff +#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0 +#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00 +#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa +#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000 +#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc +#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000 +#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x70 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x4 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9 +#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff +#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0 +#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00 +#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa +#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000 +#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc +#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000 +#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x70 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x4 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9 +#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff +#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0 +#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00 +#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa +#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000 +#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc +#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000 +#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x70 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x4 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9 +#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff +#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0 +#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00 +#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa +#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000 +#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc +#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 +#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x70 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x4 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9 +#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff +#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0 +#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00 +#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa +#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000 +#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc +#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000 +#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x70 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x4 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9 +#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff +#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0 +#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00 +#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa +#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000 +#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc +#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000 +#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x70 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x4 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9 +#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff +#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0 +#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00 +#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa +#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000 +#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc +#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000 +#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x70 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x4 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9 +#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff +#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0 +#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00 +#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa +#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000 +#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc +#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000 +#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x70 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x4 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9 +#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff +#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0 +#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00 +#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa +#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000 +#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc +#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000 +#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x70 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x4 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9 +#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff +#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0 +#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00 +#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa +#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000 +#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc +#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000 +#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x70 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x4 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9 +#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff +#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0 +#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00 +#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa +#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000 +#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc +#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000 +#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x70 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x4 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9 +#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff +#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0 +#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00 +#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa +#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000 +#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc +#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000 +#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x70 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x4 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9 +#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff +#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0 +#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00 +#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa +#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000 +#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc +#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000 +#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x70 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x4 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9 +#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff +#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0 +#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00 +#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa +#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000 +#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc +#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000 +#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x70 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x4 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9 +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7 +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0 +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38 +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe +#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000 +#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11 +#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000 +#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13 +#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000 +#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14 +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000 +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15 +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000 +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16 +#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000 +#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17 +#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x1000000 +#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x18 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x1 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x0 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x2 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x1 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x4 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x2 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x8 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x3 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x10 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x4 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x20 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x5 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x40 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x6 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x80 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x7 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x100 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x8 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x200 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x9 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x400 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0xa +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x800 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0xb +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x1000 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0xc +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x2000 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0xd +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x4000 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0xe +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x8000 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0xf +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000 +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000 +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000 +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000 +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19 +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000 +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000 +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000 +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000 +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000 +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000 +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1 +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0 +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2 +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2 +#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8 +#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x8 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x3 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2 +#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8 +#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x8 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x3 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2 +#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8 +#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x8 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x3 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2 +#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8 +#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x8 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x3 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2 +#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8 +#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x8 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x3 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2 +#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8 +#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x8 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x3 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2 +#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8 +#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x8 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x3 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2 +#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8 +#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x8 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x3 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2 +#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8 +#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x8 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x3 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2 +#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8 +#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x8 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x3 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2 +#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8 +#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x8 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x3 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2 +#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8 +#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x8 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x3 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2 +#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8 +#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x8 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x3 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2 +#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8 +#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x8 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x3 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2 +#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8 +#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x8 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x3 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2 +#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8 +#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x8 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x3 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa +#define PB1_GLB_CTRL_REG0__BACKUP_MASK 0xffff +#define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x0 +#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000 +#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10 +#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000 +#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14 +#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000 +#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17 +#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000 +#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18 +#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000 +#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19 +#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000 +#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a +#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000 +#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8 +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000 +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000 +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000 +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16 +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000 +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17 +#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000 +#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e +#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000 +#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1 +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0 +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19 +#define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f +#define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7 +#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600 +#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9 +#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800 +#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb +#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000 +#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc +#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000 +#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe +#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000 +#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12 +#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000 +#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15 +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000 +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16 +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000 +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17 +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000 +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000 +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c +#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000 +#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12 +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000 +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16 +#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000 +#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a +#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000 +#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b +#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000 +#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c +#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff +#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x8 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x3 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc +#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000 +#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x30000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x300000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x14 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x3000000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x18 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x1c +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x30000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x300000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x14 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x3000000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x18 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x1c +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x30000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x300000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x14 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x3000000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x18 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x1c +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x30000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x300000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x14 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x3000000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x18 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x1c +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e +#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff +#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0 +#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000 +#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10 +#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1 +#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0 +#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2 +#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3 +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000 +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000 +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1 +#define PB1_HW_DEBUG__PB1_HW_00_DEBUG_MASK 0x1 +#define PB1_HW_DEBUG__PB1_HW_00_DEBUG__SHIFT 0x0 +#define PB1_HW_DEBUG__PB1_HW_01_DEBUG_MASK 0x2 +#define PB1_HW_DEBUG__PB1_HW_01_DEBUG__SHIFT 0x1 +#define PB1_HW_DEBUG__PB1_HW_02_DEBUG_MASK 0x4 +#define PB1_HW_DEBUG__PB1_HW_02_DEBUG__SHIFT 0x2 +#define PB1_HW_DEBUG__PB1_HW_03_DEBUG_MASK 0x8 +#define PB1_HW_DEBUG__PB1_HW_03_DEBUG__SHIFT 0x3 +#define PB1_HW_DEBUG__PB1_HW_04_DEBUG_MASK 0x10 +#define PB1_HW_DEBUG__PB1_HW_04_DEBUG__SHIFT 0x4 +#define PB1_HW_DEBUG__PB1_HW_05_DEBUG_MASK 0x20 +#define PB1_HW_DEBUG__PB1_HW_05_DEBUG__SHIFT 0x5 +#define PB1_HW_DEBUG__PB1_HW_06_DEBUG_MASK 0x40 +#define PB1_HW_DEBUG__PB1_HW_06_DEBUG__SHIFT 0x6 +#define PB1_HW_DEBUG__PB1_HW_07_DEBUG_MASK 0x80 +#define PB1_HW_DEBUG__PB1_HW_07_DEBUG__SHIFT 0x7 +#define PB1_HW_DEBUG__PB1_HW_08_DEBUG_MASK 0x100 +#define PB1_HW_DEBUG__PB1_HW_08_DEBUG__SHIFT 0x8 +#define PB1_HW_DEBUG__PB1_HW_09_DEBUG_MASK 0x200 +#define PB1_HW_DEBUG__PB1_HW_09_DEBUG__SHIFT 0x9 +#define PB1_HW_DEBUG__PB1_HW_10_DEBUG_MASK 0x400 +#define PB1_HW_DEBUG__PB1_HW_10_DEBUG__SHIFT 0xa +#define PB1_HW_DEBUG__PB1_HW_11_DEBUG_MASK 0x800 +#define PB1_HW_DEBUG__PB1_HW_11_DEBUG__SHIFT 0xb +#define PB1_HW_DEBUG__PB1_HW_12_DEBUG_MASK 0x1000 +#define PB1_HW_DEBUG__PB1_HW_12_DEBUG__SHIFT 0xc +#define PB1_HW_DEBUG__PB1_HW_13_DEBUG_MASK 0x2000 +#define PB1_HW_DEBUG__PB1_HW_13_DEBUG__SHIFT 0xd +#define PB1_HW_DEBUG__PB1_HW_14_DEBUG_MASK 0x4000 +#define PB1_HW_DEBUG__PB1_HW_14_DEBUG__SHIFT 0xe +#define PB1_HW_DEBUG__PB1_HW_15_DEBUG_MASK 0x8000 +#define PB1_HW_DEBUG__PB1_HW_15_DEBUG__SHIFT 0xf +#define PB1_HW_DEBUG__PB1_HW_16_DEBUG_MASK 0x10000 +#define PB1_HW_DEBUG__PB1_HW_16_DEBUG__SHIFT 0x10 +#define PB1_HW_DEBUG__PB1_HW_17_DEBUG_MASK 0x20000 +#define PB1_HW_DEBUG__PB1_HW_17_DEBUG__SHIFT 0x11 +#define PB1_HW_DEBUG__PB1_HW_18_DEBUG_MASK 0x40000 +#define PB1_HW_DEBUG__PB1_HW_18_DEBUG__SHIFT 0x12 +#define PB1_HW_DEBUG__PB1_HW_19_DEBUG_MASK 0x80000 +#define PB1_HW_DEBUG__PB1_HW_19_DEBUG__SHIFT 0x13 +#define PB1_HW_DEBUG__PB1_HW_20_DEBUG_MASK 0x100000 +#define PB1_HW_DEBUG__PB1_HW_20_DEBUG__SHIFT 0x14 +#define PB1_HW_DEBUG__PB1_HW_21_DEBUG_MASK 0x200000 +#define PB1_HW_DEBUG__PB1_HW_21_DEBUG__SHIFT 0x15 +#define PB1_HW_DEBUG__PB1_HW_22_DEBUG_MASK 0x400000 +#define PB1_HW_DEBUG__PB1_HW_22_DEBUG__SHIFT 0x16 +#define PB1_HW_DEBUG__PB1_HW_23_DEBUG_MASK 0x800000 +#define PB1_HW_DEBUG__PB1_HW_23_DEBUG__SHIFT 0x17 +#define PB1_HW_DEBUG__PB1_HW_24_DEBUG_MASK 0x1000000 +#define PB1_HW_DEBUG__PB1_HW_24_DEBUG__SHIFT 0x18 +#define PB1_HW_DEBUG__PB1_HW_25_DEBUG_MASK 0x2000000 +#define PB1_HW_DEBUG__PB1_HW_25_DEBUG__SHIFT 0x19 +#define PB1_HW_DEBUG__PB1_HW_26_DEBUG_MASK 0x4000000 +#define PB1_HW_DEBUG__PB1_HW_26_DEBUG__SHIFT 0x1a +#define PB1_HW_DEBUG__PB1_HW_27_DEBUG_MASK 0x8000000 +#define PB1_HW_DEBUG__PB1_HW_27_DEBUG__SHIFT 0x1b +#define PB1_HW_DEBUG__PB1_HW_28_DEBUG_MASK 0x10000000 +#define PB1_HW_DEBUG__PB1_HW_28_DEBUG__SHIFT 0x1c +#define PB1_HW_DEBUG__PB1_HW_29_DEBUG_MASK 0x20000000 +#define PB1_HW_DEBUG__PB1_HW_29_DEBUG__SHIFT 0x1d +#define PB1_HW_DEBUG__PB1_HW_30_DEBUG_MASK 0x40000000 +#define PB1_HW_DEBUG__PB1_HW_30_DEBUG__SHIFT 0x1e +#define PB1_HW_DEBUG__PB1_HW_31_DEBUG_MASK 0x80000000 +#define PB1_HW_DEBUG__PB1_HW_31_DEBUG__SHIFT 0x1f +#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2 +#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1 +#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4 +#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2 +#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8 +#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3 +#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60 +#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5 +#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80 +#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7 +#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000 +#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc +#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000 +#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd +#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000 +#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf +#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000 +#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c +#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000 +#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5 +#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40 +#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7 +#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300 +#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8 +#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00 +#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18 +#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000 +#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1 +#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c +#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2 +#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60 +#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4 +#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000 +#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18 +#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2 +#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1 +#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4 +#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2 +#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f +#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0 +#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80 +#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7 +#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00 +#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8 +#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000 +#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14 +#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000 +#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15 +#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000 +#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16 +#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000 +#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17 +#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000 +#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18 +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0 +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100 +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8 +#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000 +#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10 +#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000 +#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11 +#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000 +#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14 +#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff +#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0 +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1 +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0 +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1 +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0 +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00 +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8 +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000 +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x10000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x10 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x20000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x11 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x40000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x12 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x80000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x13 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x100000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x14 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x200000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x15 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x400000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x16 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x800000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x17 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4 +#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800 +#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x300 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x8 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x300 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x8 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x300 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x8 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x300 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x8 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3 +#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10 +#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x300 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x8 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x300 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x8 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x300 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x8 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x300 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x8 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x1e +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d +#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000 +#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000 +#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d +#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000 +#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x1e +#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000 +#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a +#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000 +#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b +#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000 +#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8 +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000 +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000 +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd +#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x20000 +#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x11 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d +#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3 +#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc +#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x1 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x0 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x2 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x1 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x4 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x2 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x8 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x3 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x10 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x4 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x20 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x5 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x40 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x6 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x80 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x7 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x100 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x8 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x200 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x9 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x400 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0xa +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x800 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0xb +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x1000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0xc +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x2000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0xd +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x4000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0xe +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x8000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0xf +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x10000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x10 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x20000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x11 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x40000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x12 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x80000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x13 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x100000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x14 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x200000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x15 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x400000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x16 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x800000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x17 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000 +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000 +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10 +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000 +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11 +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000 +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16 +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x800000 +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x17 +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x1000000 +#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x18 +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000 +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000 +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1 +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0 +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2 +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1 +#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff +#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0 +#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00 +#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa +#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000 +#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc +#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000 +#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x70 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x4 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9 +#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff +#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0 +#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00 +#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa +#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000 +#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc +#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000 +#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x70 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x4 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9 +#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff +#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0 +#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00 +#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa +#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000 +#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc +#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000 +#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x70 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x4 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9 +#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff +#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0 +#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00 +#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa +#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000 +#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc +#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000 +#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x70 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x4 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9 +#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff +#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0 +#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00 +#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa +#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000 +#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc +#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000 +#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x70 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x4 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9 +#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff +#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0 +#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00 +#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa +#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000 +#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc +#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 +#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x70 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x4 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9 +#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff +#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0 +#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00 +#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa +#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000 +#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc +#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000 +#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x70 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x4 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9 +#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff +#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0 +#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00 +#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa +#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000 +#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc +#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000 +#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x70 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x4 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9 +#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff +#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0 +#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00 +#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa +#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000 +#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc +#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000 +#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x70 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x4 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9 +#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff +#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0 +#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00 +#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa +#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000 +#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc +#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000 +#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x70 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x4 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9 +#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff +#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0 +#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00 +#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa +#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000 +#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc +#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000 +#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x70 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x4 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9 +#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff +#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0 +#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00 +#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa +#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000 +#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc +#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000 +#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x70 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x4 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9 +#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff +#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0 +#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00 +#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa +#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000 +#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc +#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000 +#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x70 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x4 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9 +#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff +#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0 +#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00 +#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa +#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000 +#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc +#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000 +#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x70 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x4 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9 +#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff +#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0 +#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00 +#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa +#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000 +#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc +#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000 +#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x70 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x4 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9 +#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff +#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0 +#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00 +#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa +#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000 +#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc +#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000 +#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x70 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x4 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9 +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7 +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0 +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38 +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe +#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000 +#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11 +#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000 +#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13 +#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000 +#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14 +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000 +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15 +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000 +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16 +#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000 +#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17 +#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x1000000 +#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x18 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x1 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x0 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x2 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x1 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x4 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x2 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x8 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x3 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x10 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x4 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x20 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x5 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x40 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x6 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x80 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x7 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x100 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x8 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x200 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x9 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x400 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0xa +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x800 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0xb +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x1000 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0xc +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x2000 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0xd +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x4000 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0xe +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x8000 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0xf +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000 +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000 +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000 +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000 +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19 +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000 +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000 +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000 +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000 +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000 +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000 +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1 +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0 +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2 +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2 +#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8 +#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x8 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x3 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2 +#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8 +#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x8 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x3 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2 +#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8 +#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x8 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x3 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2 +#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8 +#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x8 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x3 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2 +#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8 +#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x8 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x3 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2 +#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8 +#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x8 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x3 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2 +#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8 +#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x8 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x3 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2 +#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8 +#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x8 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x3 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2 +#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8 +#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x8 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x3 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2 +#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8 +#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x8 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x3 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2 +#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8 +#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x8 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x3 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2 +#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8 +#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x8 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x3 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2 +#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8 +#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x8 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x3 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2 +#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8 +#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x8 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x3 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2 +#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8 +#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x8 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x3 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2 +#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8 +#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x8 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x3 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa +#define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff +#define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG_MASK 0x1 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG__SHIFT 0x0 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG_MASK 0x2 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG__SHIFT 0x1 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG_MASK 0x4 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG__SHIFT 0x2 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG_MASK 0x8 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG__SHIFT 0x3 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG_MASK 0x10 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG__SHIFT 0x4 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG_MASK 0x20 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG__SHIFT 0x5 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG_MASK 0x40 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG__SHIFT 0x6 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG_MASK 0x80 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG__SHIFT 0x7 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG_MASK 0x100 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG__SHIFT 0x8 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG_MASK 0x200 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG__SHIFT 0x9 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG_MASK 0x400 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG__SHIFT 0xa +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG_MASK 0x800 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG__SHIFT 0xb +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG_MASK 0x1000 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG__SHIFT 0xc +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG_MASK 0x2000 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG__SHIFT 0xd +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG_MASK 0x4000 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG__SHIFT 0xe +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG_MASK 0x8000 +#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG__SHIFT 0xf +#define PB0_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY_MASK 0x3ffff +#define PB0_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY__SHIFT 0x0 +#define PB0_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY_MASK 0x3ffff +#define PB0_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY__SHIFT 0x0 +#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x1 +#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x0 +#define PB0_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x2 +#define PB0_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x1 +#define PB0_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x4 +#define PB0_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x2 +#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x8 +#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x3 +#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x10 +#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x4 +#define PB0_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x20 +#define PB0_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x5 +#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x40 +#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x6 +#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x80 +#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x7 +#define PB0_PIF_CNTL__DIVINIT_MODE_MASK 0x100 +#define PB0_PIF_CNTL__DIVINIT_MODE__SHIFT 0x8 +#define PB0_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x200 +#define PB0_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x9 +#define PB0_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x400 +#define PB0_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0xa +#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x800 +#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0xb +#define PB0_PIF_CNTL__DIVINIT_ENABLE_MASK 0x1000 +#define PB0_PIF_CNTL__DIVINIT_ENABLE__SHIFT 0xc +#define PB0_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x2000 +#define PB0_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0xd +#define PB0_PIF_CNTL__PLL0_IN_GEN3_MODE_MASK 0x4000 +#define PB0_PIF_CNTL__PLL0_IN_GEN3_MODE__SHIFT 0xe +#define PB0_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN_MASK 0x8000 +#define PB0_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN__SHIFT 0xf +#define PB0_PIF_CNTL__TXGND_TIME_MASK 0x10000 +#define PB0_PIF_CNTL__TXGND_TIME__SHIFT 0x10 +#define PB0_PIF_CNTL__LS2_EXIT_TIME_MASK 0xe0000 +#define PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x11 +#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x700000 +#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x14 +#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x800000 +#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x17 +#define PB0_PIF_CNTL__RXEN_GATER_MASK 0xf000000 +#define PB0_PIF_CNTL__RXEN_GATER__SHIFT 0x18 +#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000 +#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x1c +#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000 +#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x1d +#define PB0_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN_MASK 0x40000000 +#define PB0_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN__SHIFT 0x1e +#define PB0_PIF_PAIRING__X2_LANE_1_0_MASK 0x1 +#define PB0_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x0 +#define PB0_PIF_PAIRING__X2_LANE_3_2_MASK 0x2 +#define PB0_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x1 +#define PB0_PIF_PAIRING__X2_LANE_5_4_MASK 0x4 +#define PB0_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x2 +#define PB0_PIF_PAIRING__X2_LANE_7_6_MASK 0x8 +#define PB0_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x3 +#define PB0_PIF_PAIRING__X2_LANE_9_8_MASK 0x10 +#define PB0_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x4 +#define PB0_PIF_PAIRING__X2_LANE_11_10_MASK 0x20 +#define PB0_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x5 +#define PB0_PIF_PAIRING__X2_LANE_13_12_MASK 0x40 +#define PB0_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x6 +#define PB0_PIF_PAIRING__X2_LANE_15_14_MASK 0x80 +#define PB0_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x7 +#define PB0_PIF_PAIRING__X4_LANE_3_0_MASK 0x100 +#define PB0_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x8 +#define PB0_PIF_PAIRING__X4_LANE_7_4_MASK 0x200 +#define PB0_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x9 +#define PB0_PIF_PAIRING__X4_LANE_11_8_MASK 0x400 +#define PB0_PIF_PAIRING__X4_LANE_11_8__SHIFT 0xa +#define PB0_PIF_PAIRING__X4_LANE_15_12_MASK 0x800 +#define PB0_PIF_PAIRING__X4_LANE_15_12__SHIFT 0xb +#define PB0_PIF_PAIRING__X8_LANE_7_0_MASK 0x10000 +#define PB0_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x10 +#define PB0_PIF_PAIRING__X8_LANE_15_8_MASK 0x20000 +#define PB0_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x11 +#define PB0_PIF_PAIRING__X16_LANE_15_0_MASK 0x100000 +#define PB0_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x14 +#define PB0_PIF_PAIRING__MULTI_PIF_MASK 0x2000000 +#define PB0_PIF_PAIRING__MULTI_PIF__SHIFT 0x19 +#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x7 +#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x0 +#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x8 +#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x3 +#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x70 +#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x4 +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x380 +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x7 +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x1c00 +#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0xa +#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x10000 +#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x10 +#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x7000000 +#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x18 +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000 +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x1c +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000 +#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x1d +#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x7 +#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x0 +#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x8 +#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x3 +#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x70 +#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x4 +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x380 +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x7 +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x1c00 +#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0xa +#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x10000 +#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x10 +#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x7000000 +#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x18 +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000 +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x1c +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000 +#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x1d +#define PB0_PIF_CNTL2__RXDETECT_PRG_EN_MASK 0x1 +#define PB0_PIF_CNTL2__RXDETECT_PRG_EN__SHIFT 0x0 +#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x6 +#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x1 +#define PB0_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN_MASK 0x8 +#define PB0_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN__SHIFT 0x3 +#define PB0_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN_MASK 0x10 +#define PB0_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN__SHIFT 0x4 +#define PB0_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN_MASK 0x20 +#define PB0_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN__SHIFT 0x5 +#define PB0_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN_MASK 0x40 +#define PB0_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN__SHIFT 0x6 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x80 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x7 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x100 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x8 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x200 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x9 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x400 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0xa +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x800 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0xb +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x1000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0xc +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x2000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0xd +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x4000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0xe +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x8000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0xf +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x10000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x10 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x20000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x11 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x40000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x12 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x80000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x13 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x100000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x14 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x200000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x15 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x400000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x16 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x800000 +#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x17 +#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x7000000 +#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x18 +#define PB0_PIF_CNTL2__RX_STAGGERING_MODE_MASK 0x8000000 +#define PB0_PIF_CNTL2__RX_STAGGERING_MODE__SHIFT 0x1b +#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN_MASK 0x10000000 +#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN__SHIFT 0x1c +#define PB0_PIF_CNTL2__RX_STAGGERING_DISABLE_MASK 0x20000000 +#define PB0_PIF_CNTL2__RX_STAGGERING_DISABLE__SHIFT 0x1d +#define PB0_PIF_CNTL2__PLL1_ALWAYS_ON_EN_MASK 0x40000000 +#define PB0_PIF_CNTL2__PLL1_ALWAYS_ON_EN__SHIFT 0x1e +#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN_MASK 0x80000000 +#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN__SHIFT 0x1f +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x1 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x0 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x2 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x1 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x4 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x2 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x8 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x3 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x10 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x4 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x20 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x5 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x40 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x6 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x80 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x7 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x100 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x8 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x200 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x9 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x400 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0xa +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x800 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0xb +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x1000 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0xc +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x2000 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0xd +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x4000 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0xe +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x8000 +#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0xf +#define PB0_PIF_SC_CTL__SC_CALIBRATION_MASK 0x1 +#define PB0_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x0 +#define PB0_PIF_SC_CTL__SC_RXDETECT_MASK 0x2 +#define PB0_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x1 +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x4 +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x2 +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x8 +#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x3 +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x10 +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x4 +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x20 +#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x5 +#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x40 +#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x6 +#define PB0_PIF_SC_CTL__SC_PHASE_1_MASK 0x100 +#define PB0_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x8 +#define PB0_PIF_SC_CTL__SC_PHASE_2_MASK 0x200 +#define PB0_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x9 +#define PB0_PIF_SC_CTL__SC_PHASE_3_MASK 0x400 +#define PB0_PIF_SC_CTL__SC_PHASE_3__SHIFT 0xa +#define PB0_PIF_SC_CTL__SC_PHASE_4_MASK 0x800 +#define PB0_PIF_SC_CTL__SC_PHASE_4__SHIFT 0xb +#define PB0_PIF_SC_CTL__SC_PHASE_5_MASK 0x1000 +#define PB0_PIF_SC_CTL__SC_PHASE_5__SHIFT 0xc +#define PB0_PIF_SC_CTL__SC_PHASE_6_MASK 0x2000 +#define PB0_PIF_SC_CTL__SC_PHASE_6__SHIFT 0xd +#define PB0_PIF_SC_CTL__SC_PHASE_7_MASK 0x4000 +#define PB0_PIF_SC_CTL__SC_PHASE_7__SHIFT 0xe +#define PB0_PIF_SC_CTL__SC_PHASE_8_MASK 0x8000 +#define PB0_PIF_SC_CTL__SC_PHASE_8__SHIFT 0xf +#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x10000 +#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x10 +#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x20000 +#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x11 +#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x40000 +#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x12 +#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x80000 +#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x13 +#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x100000 +#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x14 +#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x200000 +#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x15 +#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x400000 +#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x16 +#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x800000 +#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x17 +#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x1000000 +#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x18 +#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x2000000 +#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x19 +#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x4000000 +#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x1a +#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x8000000 +#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x1b +#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000 +#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x1c +#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000 +#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x1d +#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000 +#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x1e +#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000 +#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x1f +#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x7 +#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x0 +#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x8 +#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x3 +#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x70 +#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x4 +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x380 +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x7 +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x1c00 +#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0xa +#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x10000 +#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x10 +#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x7000000 +#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x18 +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000 +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x1c +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000 +#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x1d +#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x7 +#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x0 +#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x8 +#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x3 +#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x70 +#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x4 +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x380 +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x7 +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x1c00 +#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0xa +#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x10000 +#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x10 +#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x7000000 +#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x18 +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000 +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x1c +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000 +#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x1d +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0_MASK 0x1 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0__SHIFT 0x0 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK 0x2 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1__SHIFT 0x1 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2_MASK 0x4 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT 0x2 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3_MASK 0x8 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3__SHIFT 0x3 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4_MASK 0x10 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4__SHIFT 0x4 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5_MASK 0x20 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5__SHIFT 0x5 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6_MASK 0x40 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6__SHIFT 0x6 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7_MASK 0x80 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7__SHIFT 0x7 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8_MASK 0x100 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8__SHIFT 0x8 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9_MASK 0x200 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9__SHIFT 0x9 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10_MASK 0x400 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10__SHIFT 0xa +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11_MASK 0x800 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11__SHIFT 0xb +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12_MASK 0x1000 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12__SHIFT 0xc +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13_MASK 0x2000 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13__SHIFT 0xd +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14_MASK 0x4000 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14__SHIFT 0xe +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15_MASK 0x8000 +#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15__SHIFT 0xf +#define PB0_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME_MASK 0x3ffff +#define PB0_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME__SHIFT 0x0 +#define PB0_PIF_PRG1__PRG_PLL_RAMP_UP_TIME_MASK 0x3ffff +#define PB0_PIF_PRG1__PRG_PLL_RAMP_UP_TIME__SHIFT 0x0 +#define PB0_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY_MASK 0x3ffff +#define PB0_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY__SHIFT 0x0 +#define PB0_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY_MASK 0x3ffff +#define PB0_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY__SHIFT 0x0 +#define PB0_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY_MASK 0x3ffff +#define PB0_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY__SHIFT 0x0 +#define PB0_PIF_PRG5__PRG_LS2_EXIT_TIME_MASK 0x3ffff +#define PB0_PIF_PRG5__PRG_LS2_EXIT_TIME__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0xf +#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0xf +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x1 +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x0 +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0xe +#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x1 +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x10 +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x4 +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0xe0 +#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x5 +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x100 +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x8 +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x200 +#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x9 +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x400 +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0xa +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x3800 +#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0xb +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x4000 +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0xe +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x38000 +#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0xf +#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x8 +#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x1 +#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x0 +#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x2 +#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x1 +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x4 +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x2 +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x8 +#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x3 +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x10 +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x4 +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x20 +#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x5 +#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x40 +#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x6 +#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x700 +#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x8 +#define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff +#define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG_MASK 0x1 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG__SHIFT 0x0 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG_MASK 0x2 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG__SHIFT 0x1 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG_MASK 0x4 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG__SHIFT 0x2 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG_MASK 0x8 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG__SHIFT 0x3 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG_MASK 0x10 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG__SHIFT 0x4 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG_MASK 0x20 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG__SHIFT 0x5 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG_MASK 0x40 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG__SHIFT 0x6 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG_MASK 0x80 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG__SHIFT 0x7 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG_MASK 0x100 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG__SHIFT 0x8 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG_MASK 0x200 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG__SHIFT 0x9 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG_MASK 0x400 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG__SHIFT 0xa +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG_MASK 0x800 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG__SHIFT 0xb +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG_MASK 0x1000 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG__SHIFT 0xc +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG_MASK 0x2000 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG__SHIFT 0xd +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG_MASK 0x4000 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG__SHIFT 0xe +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG_MASK 0x8000 +#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG__SHIFT 0xf +#define PB1_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY_MASK 0x3ffff +#define PB1_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY__SHIFT 0x0 +#define PB1_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY_MASK 0x3ffff +#define PB1_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY__SHIFT 0x0 +#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x1 +#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x0 +#define PB1_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x2 +#define PB1_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x1 +#define PB1_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x4 +#define PB1_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x2 +#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x8 +#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x3 +#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x10 +#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x4 +#define PB1_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x20 +#define PB1_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x5 +#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x40 +#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x6 +#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x80 +#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x7 +#define PB1_PIF_CNTL__DIVINIT_MODE_MASK 0x100 +#define PB1_PIF_CNTL__DIVINIT_MODE__SHIFT 0x8 +#define PB1_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x200 +#define PB1_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x9 +#define PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x400 +#define PB1_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0xa +#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x800 +#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0xb +#define PB1_PIF_CNTL__DIVINIT_ENABLE_MASK 0x1000 +#define PB1_PIF_CNTL__DIVINIT_ENABLE__SHIFT 0xc +#define PB1_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x2000 +#define PB1_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0xd +#define PB1_PIF_CNTL__PLL0_IN_GEN3_MODE_MASK 0x4000 +#define PB1_PIF_CNTL__PLL0_IN_GEN3_MODE__SHIFT 0xe +#define PB1_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN_MASK 0x8000 +#define PB1_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN__SHIFT 0xf +#define PB1_PIF_CNTL__TXGND_TIME_MASK 0x10000 +#define PB1_PIF_CNTL__TXGND_TIME__SHIFT 0x10 +#define PB1_PIF_CNTL__LS2_EXIT_TIME_MASK 0xe0000 +#define PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x11 +#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x700000 +#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x14 +#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x800000 +#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x17 +#define PB1_PIF_CNTL__RXEN_GATER_MASK 0xf000000 +#define PB1_PIF_CNTL__RXEN_GATER__SHIFT 0x18 +#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000 +#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x1c +#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000 +#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x1d +#define PB1_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN_MASK 0x40000000 +#define PB1_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN__SHIFT 0x1e +#define PB1_PIF_PAIRING__X2_LANE_1_0_MASK 0x1 +#define PB1_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x0 +#define PB1_PIF_PAIRING__X2_LANE_3_2_MASK 0x2 +#define PB1_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x1 +#define PB1_PIF_PAIRING__X2_LANE_5_4_MASK 0x4 +#define PB1_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x2 +#define PB1_PIF_PAIRING__X2_LANE_7_6_MASK 0x8 +#define PB1_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x3 +#define PB1_PIF_PAIRING__X2_LANE_9_8_MASK 0x10 +#define PB1_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x4 +#define PB1_PIF_PAIRING__X2_LANE_11_10_MASK 0x20 +#define PB1_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x5 +#define PB1_PIF_PAIRING__X2_LANE_13_12_MASK 0x40 +#define PB1_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x6 +#define PB1_PIF_PAIRING__X2_LANE_15_14_MASK 0x80 +#define PB1_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x7 +#define PB1_PIF_PAIRING__X4_LANE_3_0_MASK 0x100 +#define PB1_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x8 +#define PB1_PIF_PAIRING__X4_LANE_7_4_MASK 0x200 +#define PB1_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x9 +#define PB1_PIF_PAIRING__X4_LANE_11_8_MASK 0x400 +#define PB1_PIF_PAIRING__X4_LANE_11_8__SHIFT 0xa +#define PB1_PIF_PAIRING__X4_LANE_15_12_MASK 0x800 +#define PB1_PIF_PAIRING__X4_LANE_15_12__SHIFT 0xb +#define PB1_PIF_PAIRING__X8_LANE_7_0_MASK 0x10000 +#define PB1_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x10 +#define PB1_PIF_PAIRING__X8_LANE_15_8_MASK 0x20000 +#define PB1_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x11 +#define PB1_PIF_PAIRING__X16_LANE_15_0_MASK 0x100000 +#define PB1_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x14 +#define PB1_PIF_PAIRING__MULTI_PIF_MASK 0x2000000 +#define PB1_PIF_PAIRING__MULTI_PIF__SHIFT 0x19 +#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x7 +#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x0 +#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x8 +#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x3 +#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x70 +#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x4 +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x380 +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x7 +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x1c00 +#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0xa +#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x10000 +#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x10 +#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x7000000 +#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x18 +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000 +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x1c +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000 +#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x1d +#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x7 +#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x0 +#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x8 +#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x3 +#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x70 +#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x4 +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x380 +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x7 +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x1c00 +#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0xa +#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x10000 +#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x10 +#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x7000000 +#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x18 +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000 +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x1c +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000 +#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x1d +#define PB1_PIF_CNTL2__RXDETECT_PRG_EN_MASK 0x1 +#define PB1_PIF_CNTL2__RXDETECT_PRG_EN__SHIFT 0x0 +#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x6 +#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x1 +#define PB1_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN_MASK 0x8 +#define PB1_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN__SHIFT 0x3 +#define PB1_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN_MASK 0x10 +#define PB1_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN__SHIFT 0x4 +#define PB1_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN_MASK 0x20 +#define PB1_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN__SHIFT 0x5 +#define PB1_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN_MASK 0x40 +#define PB1_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN__SHIFT 0x6 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x80 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x7 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x100 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x8 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x200 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x9 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x400 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0xa +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x800 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0xb +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x1000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0xc +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x2000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0xd +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x4000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0xe +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x8000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0xf +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x10000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x10 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x20000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x11 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x40000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x12 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x80000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x13 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x100000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x14 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x200000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x15 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x400000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x16 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x800000 +#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x17 +#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x7000000 +#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x18 +#define PB1_PIF_CNTL2__RX_STAGGERING_MODE_MASK 0x8000000 +#define PB1_PIF_CNTL2__RX_STAGGERING_MODE__SHIFT 0x1b +#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN_MASK 0x10000000 +#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN__SHIFT 0x1c +#define PB1_PIF_CNTL2__RX_STAGGERING_DISABLE_MASK 0x20000000 +#define PB1_PIF_CNTL2__RX_STAGGERING_DISABLE__SHIFT 0x1d +#define PB1_PIF_CNTL2__PLL1_ALWAYS_ON_EN_MASK 0x40000000 +#define PB1_PIF_CNTL2__PLL1_ALWAYS_ON_EN__SHIFT 0x1e +#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN_MASK 0x80000000 +#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN__SHIFT 0x1f +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x1 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x0 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x2 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x1 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x4 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x2 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x8 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x3 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x10 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x4 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x20 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x5 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x40 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x6 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x80 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x7 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x100 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x8 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x200 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x9 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x400 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0xa +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x800 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0xb +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x1000 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0xc +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x2000 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0xd +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x4000 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0xe +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x8000 +#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0xf +#define PB1_PIF_SC_CTL__SC_CALIBRATION_MASK 0x1 +#define PB1_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x0 +#define PB1_PIF_SC_CTL__SC_RXDETECT_MASK 0x2 +#define PB1_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x1 +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x4 +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x2 +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x8 +#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x3 +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x10 +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x4 +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x20 +#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x5 +#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x40 +#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x6 +#define PB1_PIF_SC_CTL__SC_PHASE_1_MASK 0x100 +#define PB1_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x8 +#define PB1_PIF_SC_CTL__SC_PHASE_2_MASK 0x200 +#define PB1_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x9 +#define PB1_PIF_SC_CTL__SC_PHASE_3_MASK 0x400 +#define PB1_PIF_SC_CTL__SC_PHASE_3__SHIFT 0xa +#define PB1_PIF_SC_CTL__SC_PHASE_4_MASK 0x800 +#define PB1_PIF_SC_CTL__SC_PHASE_4__SHIFT 0xb +#define PB1_PIF_SC_CTL__SC_PHASE_5_MASK 0x1000 +#define PB1_PIF_SC_CTL__SC_PHASE_5__SHIFT 0xc +#define PB1_PIF_SC_CTL__SC_PHASE_6_MASK 0x2000 +#define PB1_PIF_SC_CTL__SC_PHASE_6__SHIFT 0xd +#define PB1_PIF_SC_CTL__SC_PHASE_7_MASK 0x4000 +#define PB1_PIF_SC_CTL__SC_PHASE_7__SHIFT 0xe +#define PB1_PIF_SC_CTL__SC_PHASE_8_MASK 0x8000 +#define PB1_PIF_SC_CTL__SC_PHASE_8__SHIFT 0xf +#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x10000 +#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x10 +#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x20000 +#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x11 +#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x40000 +#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x12 +#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x80000 +#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x13 +#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x100000 +#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x14 +#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x200000 +#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x15 +#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x400000 +#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x16 +#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x800000 +#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x17 +#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x1000000 +#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x18 +#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x2000000 +#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x19 +#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x4000000 +#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x1a +#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x8000000 +#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x1b +#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000 +#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x1c +#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000 +#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x1d +#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000 +#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x1e +#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000 +#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x1f +#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x7 +#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x0 +#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x8 +#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x3 +#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x70 +#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x4 +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x380 +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x7 +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x1c00 +#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0xa +#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x10000 +#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x10 +#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x7000000 +#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x18 +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000 +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x1c +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000 +#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x1d +#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x7 +#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x0 +#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x8 +#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x3 +#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x70 +#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x4 +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x380 +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x7 +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x1c00 +#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0xa +#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x10000 +#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x10 +#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x7000000 +#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x18 +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000 +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x1c +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000 +#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x1d +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0_MASK 0x1 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0__SHIFT 0x0 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK 0x2 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1__SHIFT 0x1 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2_MASK 0x4 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT 0x2 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3_MASK 0x8 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3__SHIFT 0x3 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4_MASK 0x10 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4__SHIFT 0x4 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5_MASK 0x20 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5__SHIFT 0x5 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6_MASK 0x40 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6__SHIFT 0x6 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7_MASK 0x80 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7__SHIFT 0x7 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8_MASK 0x100 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8__SHIFT 0x8 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9_MASK 0x200 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9__SHIFT 0x9 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10_MASK 0x400 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10__SHIFT 0xa +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11_MASK 0x800 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11__SHIFT 0xb +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12_MASK 0x1000 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12__SHIFT 0xc +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13_MASK 0x2000 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13__SHIFT 0xd +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14_MASK 0x4000 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14__SHIFT 0xe +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15_MASK 0x8000 +#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15__SHIFT 0xf +#define PB1_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME_MASK 0x3ffff +#define PB1_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME__SHIFT 0x0 +#define PB1_PIF_PRG1__PRG_PLL_RAMP_UP_TIME_MASK 0x3ffff +#define PB1_PIF_PRG1__PRG_PLL_RAMP_UP_TIME__SHIFT 0x0 +#define PB1_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY_MASK 0x3ffff +#define PB1_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY__SHIFT 0x0 +#define PB1_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY_MASK 0x3ffff +#define PB1_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY__SHIFT 0x0 +#define PB1_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY_MASK 0x3ffff +#define PB1_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY__SHIFT 0x0 +#define PB1_PIF_PRG5__PRG_LS2_EXIT_TIME_MASK 0x3ffff +#define PB1_PIF_PRG5__PRG_LS2_EXIT_TIME__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0xf +#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0xf +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x1 +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x0 +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0xe +#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x1 +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x10 +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x4 +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0xe0 +#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x5 +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x100 +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x8 +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x200 +#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x9 +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x400 +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0xa +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x3800 +#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0xb +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x4000 +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0xe +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x38000 +#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0xf +#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x8 +#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x1 +#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x0 +#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x2 +#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x1 +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x4 +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x2 +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x8 +#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x3 +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x10 +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x4 +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x20 +#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x5 +#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x40 +#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x6 +#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x700 +#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x8 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1 +#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1 +#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0 +#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2 +#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1 +#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff +#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0 +#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000 +#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e +#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000 +#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f +#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1 +#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst_MASK 0x1 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst__SHIFT 0x0 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK 0x2 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst__SHIFT 0x1 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst_MASK 0x1 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst__SHIFT 0x0 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK 0x2 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst__SHIFT 0x1 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x4 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x2 +#define BIF_PWDN_COMMAND__REG_BU_pw_cmd_MASK 0x1 +#define BIF_PWDN_COMMAND__REG_BU_pw_cmd__SHIFT 0x0 +#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK 0x2 +#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd__SHIFT 0x1 +#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x4 +#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x2 +#define BIF_PWDN_STATUS__BU_REG_pw_status_MASK 0x1 +#define BIF_PWDN_STATUS__BU_REG_pw_status__SHIFT 0x0 +#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK 0x2 +#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status__SHIFT 0x1 +#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x4 +#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x2 +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer_MASK 0xff +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer__SHIFT 0x0 +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer_MASK 0xf00 +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer__SHIFT 0x8 +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer_MASK 0xff0000 +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer__SHIFT 0x10 +#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout_MASK 0x1000000 +#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout__SHIFT 0x18 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer_MASK 0xff +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer__SHIFT 0x0 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer_MASK 0xf00 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer__SHIFT 0x8 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer_MASK 0xff0000 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer__SHIFT 0x10 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout_MASK 0x1000000 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout__SHIFT 0x18 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10 +#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000 +#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18 +#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1 +#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0 +#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x1 +#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x0 +#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe +#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x1 +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x10 +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x4 +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe0 +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x5 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_MASK 0x1e +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL__SHIFT 0x1 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN_MASK 0x20 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN__SHIFT 0x5 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD_MASK 0x3c0 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD__SHIFT 0x6 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD_MASK 0x400 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD__SHIFT 0xa +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU_MASK 0x7800 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU__SHIFT 0xb +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU_MASK 0x8000 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU__SHIFT 0xf +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN_MASK 0x10000 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN__SHIFT 0x10 +#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE_MASK 0x1 +#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE__SHIFT 0x0 +#define BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK 0x2 +#define BIF_IMPCTL_SMPLCNTL__RxPDNB__SHIFT 0x1 +#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd_MASK 0x4 +#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT 0x2 +#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu_MASK 0x8 +#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu__SHIFT 0x3 +#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD_MASK 0x1f00 +#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD__SHIFT 0x8 +#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES_MASK 0x2000 +#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES__SHIFT 0xd +#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE_MASK 0x4000 +#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE__SHIFT 0xe +#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME_MASK 0xf8000 +#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME__SHIFT 0xf +#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH_MASK 0x3f00000 +#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH__SHIFT 0x14 +#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH_MASK 0xfc000000 +#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH__SHIFT 0x1a +#define BIF_IMPCTL_RXCNTL__RX_ADJUST_MASK 0x7 +#define BIF_IMPCTL_RXCNTL__RX_ADJUST__SHIFT 0x0 +#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH_MASK 0x8 +#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH__SHIFT 0x3 +#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT_MASK 0x10 +#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT__SHIFT 0x4 +#define BIF_IMPCTL_RXCNTL__SUSPEND_MASK 0x40 +#define BIF_IMPCTL_RXCNTL__SUSPEND__SHIFT 0x6 +#define BIF_IMPCTL_RXCNTL__FORCE_RST_MASK 0x80 +#define BIF_IMPCTL_RXCNTL__FORCE_RST__SHIFT 0x7 +#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH_MASK 0xf00 +#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH__SHIFT 0x8 +#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_MASK 0x1000 +#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ__SHIFT 0xc +#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH_MASK 0x1e000 +#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH__SHIFT 0xd +#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_MASK 0x20000 +#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ__SHIFT 0x11 +#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED_MASK 0x40000 +#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED__SHIFT 0x12 +#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL_MASK 0x80000 +#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL__SHIFT 0x13 +#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_MASK 0xf00000 +#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK__SHIFT 0x14 +#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG_MASK 0x10000000 +#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG__SHIFT 0x1c +#define BIF_IMPCTL_RXCNTL__CAL_DONE_MASK 0x20000000 +#define BIF_IMPCTL_RXCNTL__CAL_DONE__SHIFT 0x1d +#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd_MASK 0x7 +#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd__SHIFT 0x0 +#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd_MASK 0x8 +#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd__SHIFT 0x3 +#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd_MASK 0xf00 +#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd__SHIFT 0x8 +#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd_MASK 0x1000 +#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd__SHIFT 0xc +#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd_MASK 0x1e000 +#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd__SHIFT 0xd +#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd_MASK 0x20000 +#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd__SHIFT 0x11 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd_MASK 0x40000 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd__SHIFT 0x12 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd_MASK 0x80000 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd__SHIFT 0x13 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd_MASK 0xf00000 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd__SHIFT 0x14 +#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd_MASK 0x10000000 +#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd__SHIFT 0x1c +#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu_MASK 0x7 +#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu__SHIFT 0x0 +#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu_MASK 0x8 +#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu__SHIFT 0x3 +#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu_MASK 0xf00 +#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu__SHIFT 0x8 +#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu_MASK 0x1000 +#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu__SHIFT 0xc +#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu_MASK 0x1e000 +#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu__SHIFT 0xd +#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu_MASK 0x20000 +#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu__SHIFT 0x11 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu_MASK 0x40000 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu__SHIFT 0x12 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu_MASK 0x80000 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu__SHIFT 0x13 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu_MASK 0xf00000 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu__SHIFT 0x14 +#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu_MASK 0x10000000 +#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu__SHIFT 0x1c +#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD_MASK 0xffffffff +#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD__SHIFT 0x0 +#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK_MASK 0x1 +#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0 +#define BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK 0x1 +#define BIF_LNCNT_RESET__RESET_LNCNT_EN__SHIFT 0x0 +#define LNCNT_CONTROL__LNCNT_ACC_MODE_MASK 0x1 +#define LNCNT_CONTROL__LNCNT_ACC_MODE__SHIFT 0x0 +#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE_MASK 0x6 +#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE__SHIFT 0x1 +#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x1 +#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x0 +#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x1ffffe +#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x1 +#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x200000 +#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x15 +#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x3ff +#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x0 +#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x400 +#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0xa +#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x3ff +#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x0 +#define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x2 +#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x1 +#define BIF_RESET_EN__PHY_RESET_EN_MASK 0x4 +#define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x2 +#define BIF_RESET_EN__COR_RESET_EN_MASK 0x8 +#define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x3 +#define BIF_RESET_EN__REG_RESET_EN_MASK 0x10 +#define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x4 +#define BIF_RESET_EN__STY_RESET_EN_MASK 0x20 +#define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x5 +#define BIF_RESET_EN__CFG_RESET_EN_MASK 0x40 +#define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x6 +#define BIF_RESET_EN__DRV_RESET_EN_MASK 0x80 +#define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x7 +#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x100 +#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x8 +#define BIF_RESET_EN__HOT_RESET_EN_MASK 0x200 +#define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x9 +#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x400 +#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0xa +#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x800 +#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0xb +#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x3f000 +#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0xc +#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0xc0000 +#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x12 +#define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x100000 +#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x14 +#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x200000 +#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x15 +#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x400000 +#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x16 +#define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x800000 +#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x17 +#define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x1000000 +#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x18 +#define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x2000000 +#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x19 +#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0xc000000 +#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a +#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000 +#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c +#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000 +#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x7 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x0 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x38 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x3 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x3c0 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x6 +#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x1 +#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x0 +#define BIF_BACO_MSIC__BACO_LINK_RST_SEL_MASK 0x6 +#define BIF_BACO_MSIC__BACO_LINK_RST_SEL__SHIFT 0x1 +#define BIF_RESET_CNTL__STRAP_EN_MASK 0x1 +#define BIF_RESET_CNTL__STRAP_EN__SHIFT 0x0 +#define BIF_RESET_CNTL__RST_DONE_MASK 0x2 +#define BIF_RESET_CNTL__RST_DONE__SHIFT 0x1 +#define BIF_RESET_CNTL__LINK_TRAIN_EN_MASK 0x4 +#define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x2 +#define BIF_RESET_CNTL__STRAP_ALL_VALID_MASK 0x8 +#define BIF_RESET_CNTL__STRAP_ALL_VALID__SHIFT 0x3 +#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST_MASK 0x100 +#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST__SHIFT 0x8 +#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS_MASK 0x200 +#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9 +#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode_MASK 0x1 +#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0 +#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK 0x2 +#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1 +#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4 +#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2 +#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8 +#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3 + +#endif /* BIF_4_1_SH_MASK_H */ -- cgit v1.2.3 From 848ebfd731f0fa500b653d2a41af8d5cf769266b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:15:36 -0400 Subject: drm/amdgpu: add BIF 5.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the BIF (Bus InterFace) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h | 1068 ++ .../drm/amd/include/asic_reg/bif/bif_5_0_enum.h | 1198 ++ .../drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h | 11494 +++++++++++++++++++ 3 files changed, 13760 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h new file mode 100644 index 000000000000..92b6ba0047af --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h @@ -0,0 +1,1068 @@ +/* + * BIF_5_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_5_0_D_H +#define BIF_5_0_D_H + +#define mmMM_INDEX 0x0 +#define mmMM_INDEX_HI 0x6 +#define mmMM_DATA 0x1 +#define mmBIF_MM_INDACCESS_CNTL 0x1500 +#define mmBIF_DOORBELL_APER_EN 0x1501 +#define mmBUS_CNTL 0x1508 +#define mmCONFIG_CNTL 0x1509 +#define mmCONFIG_MEMSIZE 0x150a +#define mmCONFIG_RESERVED 0x1502 +#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 +#define mmCONFIG_F0_BASE 0x150b +#define mmCONFIG_APER_SIZE 0x150c +#define mmCONFIG_REG_APER_SIZE 0x150d +#define mmBIF_SCRATCH0 0x150e +#define mmBIF_SCRATCH1 0x150f +#define mmBIF_RLC_INTR_CNTL 0x1510 +#define mmBIF_BME_STATUS 0x1511 +#define mmBIF_ATOMIC_ERR_LOG 0x1512 +#define mmBX_RESET_EN 0x1514 +#define mmMM_CFGREGS_CNTL 0x1513 +#define mmHW_DEBUG 0x1515 +#define mmMASTER_CREDIT_CNTL 0x1516 +#define mmSLAVE_REQ_CREDIT_CNTL 0x1517 +#define mmBX_RESET_CNTL 0x1518 +#define mmINTERRUPT_CNTL 0x151a +#define mmINTERRUPT_CNTL2 0x151b +#define mmBIF_DEBUG_CNTL 0x151c +#define mmBIF_DEBUG_MUX 0x151d +#define mmBIF_DEBUG_OUT 0x151e +#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 +#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 +#define mmCLKREQB_PAD_CNTL 0x1521 +#define mmCLKREQB_PERF_COUNTER 0x1522 +#define mmBIF_XDMA_LO 0x14c0 +#define mmBIF_XDMA_HI 0x14c1 +#define mmBIF_FEATURES_CONTROL_MISC 0x14c2 +#define mmBIF_DOORBELL_CNTL 0x14c3 +#define mmBIF_SLVARB_MODE 0x14c4 +#define mmBIF_CLK_CTRL 0x14c5 +#define mmBIF_FB_EN 0x1524 +#define mmBIF_BUSNUM_CNTL1 0x1525 +#define mmBIF_BUSNUM_LIST0 0x1526 +#define mmBIF_BUSNUM_LIST1 0x1527 +#define mmBIF_BUSNUM_CNTL2 0x152b +#define mmBIF_BUSY_DELAY_CNTR 0x1529 +#define mmBIF_PERFMON_CNTL 0x152c +#define mmBIF_PERFCOUNTER0_RESULT 0x152d +#define mmBIF_PERFCOUNTER1_RESULT 0x152e +#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 +#define mmGPU_HDP_FLUSH_REQ 0x1537 +#define mmGPU_HDP_FLUSH_DONE 0x1538 +#define mmSLAVE_HANG_ERROR 0x153b +#define mmCAPTURE_HOST_BUSNUM 0x153c +#define mmHOST_BUSNUM 0x153d +#define mmPEER_REG_RANGE0 0x153e +#define mmPEER_REG_RANGE1 0x153f +#define mmPEER0_FB_OFFSET_HI 0x14f3 +#define mmPEER0_FB_OFFSET_LO 0x14f2 +#define mmPEER1_FB_OFFSET_HI 0x14f1 +#define mmPEER1_FB_OFFSET_LO 0x14f0 +#define mmPEER2_FB_OFFSET_HI 0x14ef +#define mmPEER2_FB_OFFSET_LO 0x14ee +#define mmPEER3_FB_OFFSET_HI 0x14ed +#define mmPEER3_FB_OFFSET_LO 0x14ec +#define mmDBG_SMB_BYPASS_SRBM_ACCESS 0x14eb +#define mmBIF_MST_TRANS_PENDING 0x14ea +#define mmBIF_SLV_TRANS_PENDING 0x14e9 +#define mmBIF_DEVFUNCNUM_LIST0 0x14e8 +#define mmBIF_DEVFUNCNUM_LIST1 0x14e7 +#define mmBACO_CNTL 0x14e5 +#define mmBF_ANA_ISO_CNTL 0x14c7 +#define mmMEM_TYPE_CNTL 0x14e4 +#define mmBIF_BACO_DEBUG 0x14df +#define mmBIF_BACO_DEBUG_LATCH 0x14dc +#define mmBACO_CNTL_MISC 0x14db +#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8 +#define mmBIF_VDDGFX_GFX0_LOWER 0x1428 +#define mmBIF_VDDGFX_GFX0_UPPER 0x1429 +#define mmBIF_VDDGFX_GFX1_LOWER 0x142a +#define mmBIF_VDDGFX_GFX1_UPPER 0x142b +#define mmBIF_VDDGFX_GFX2_LOWER 0x142c +#define mmBIF_VDDGFX_GFX2_UPPER 0x142d +#define mmBIF_VDDGFX_GFX3_LOWER 0x142e +#define mmBIF_VDDGFX_GFX3_UPPER 0x142f +#define mmBIF_VDDGFX_GFX4_LOWER 0x1430 +#define mmBIF_VDDGFX_GFX4_UPPER 0x1431 +#define mmBIF_VDDGFX_GFX5_LOWER 0x1432 +#define mmBIF_VDDGFX_GFX5_UPPER 0x1433 +#define mmBIF_VDDGFX_RSV1_LOWER 0x1434 +#define mmBIF_VDDGFX_RSV1_UPPER 0x1435 +#define mmBIF_VDDGFX_RSV2_LOWER 0x1436 +#define mmBIF_VDDGFX_RSV2_UPPER 0x1437 +#define mmBIF_VDDGFX_RSV3_LOWER 0x1438 +#define mmBIF_VDDGFX_RSV3_UPPER 0x1439 +#define mmBIF_VDDGFX_RSV4_LOWER 0x143a +#define mmBIF_VDDGFX_RSV4_UPPER 0x143b +#define mmBIF_VDDGFX_FB_CMP 0x143c +#define mmBIF_SMU_INDEX 0x143d +#define mmBIF_SMU_DATA 0x143e +#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc +#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd +#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe +#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff +#define mmIMPCTL_RESET 0x14f5 +#define mmGARLIC_FLUSH_CNTL 0x1401 +#define mmGARLIC_FLUSH_ADDR_START_0 0x1402 +#define mmGARLIC_FLUSH_ADDR_START_1 0x1404 +#define mmGARLIC_FLUSH_ADDR_START_2 0x1406 +#define mmGARLIC_FLUSH_ADDR_START_3 0x1408 +#define mmGARLIC_FLUSH_ADDR_START_4 0x140a +#define mmGARLIC_FLUSH_ADDR_START_5 0x140c +#define mmGARLIC_FLUSH_ADDR_START_6 0x140e +#define mmGARLIC_FLUSH_ADDR_START_7 0x1410 +#define mmGARLIC_FLUSH_ADDR_END_0 0x1403 +#define mmGARLIC_FLUSH_ADDR_END_1 0x1405 +#define mmGARLIC_FLUSH_ADDR_END_2 0x1407 +#define mmGARLIC_FLUSH_ADDR_END_3 0x1409 +#define mmGARLIC_FLUSH_ADDR_END_4 0x140b +#define mmGARLIC_FLUSH_ADDR_END_5 0x140d +#define mmGARLIC_FLUSH_ADDR_END_6 0x140f +#define mmGARLIC_FLUSH_ADDR_END_7 0x1411 +#define mmGARLIC_FLUSH_REQ 0x1412 +#define mmGPU_GARLIC_FLUSH_REQ 0x1413 +#define mmGPU_GARLIC_FLUSH_DONE 0x1414 +#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426 +#define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427 +#define mmBIOS_SCRATCH_0 0x5c9 +#define mmBIOS_SCRATCH_1 0x5ca +#define mmBIOS_SCRATCH_2 0x5cb +#define mmBIOS_SCRATCH_3 0x5cc +#define mmBIOS_SCRATCH_4 0x5cd +#define mmBIOS_SCRATCH_5 0x5ce +#define mmBIOS_SCRATCH_6 0x5cf +#define mmBIOS_SCRATCH_7 0x5d0 +#define mmBIOS_SCRATCH_8 0x5d1 +#define mmBIOS_SCRATCH_9 0x5d2 +#define mmBIOS_SCRATCH_10 0x5d3 +#define mmBIOS_SCRATCH_11 0x5d4 +#define mmBIOS_SCRATCH_12 0x5d5 +#define mmBIOS_SCRATCH_13 0x5d6 +#define mmBIOS_SCRATCH_14 0x5d7 +#define mmBIOS_SCRATCH_15 0x5d8 +#define mmBIF_RB_CNTL 0x1530 +#define mmBIF_RB_BASE 0x1531 +#define mmBIF_RB_RPTR 0x1532 +#define mmBIF_RB_WPTR 0x1533 +#define mmBIF_RB_WPTR_ADDR_HI 0x1534 +#define mmBIF_RB_WPTR_ADDR_LO 0x1535 +#define mmMAILBOX_INDEX 0x14c6 +#define mmMAILBOX_MSGBUF_TRN_DW0 0x14c8 +#define mmMAILBOX_MSGBUF_TRN_DW1 0x14c9 +#define mmMAILBOX_MSGBUF_TRN_DW2 0x14ca +#define mmMAILBOX_MSGBUF_TRN_DW3 0x14cb +#define mmMAILBOX_MSGBUF_RCV_DW0 0x14cc +#define mmMAILBOX_MSGBUF_RCV_DW1 0x14cd +#define mmMAILBOX_MSGBUF_RCV_DW2 0x14ce +#define mmMAILBOX_MSGBUF_RCV_DW3 0x14cf +#define mmMAILBOX_CONTROL 0x14d0 +#define mmMAILBOX_INT_CNTL 0x14d1 +#define mmBIF_VIRT_RESET_REQ 0x14d2 +#define mmVM_INIT_STATUS 0x14d3 +#define mmBIF_GPUIOV_RESET_NOTIFICATION 0x14d5 +#define mmBIF_GPUIOV_VM_INIT_STATUS 0x14d6 +#define mmBIF_GPUIOV_FB_TOTAL_FB_INFO 0x14d8 +#define mmBIF_GPUIOV_GPU_IDLE_LATENCY 0x141c +#define mmBIF_GPUIOV_MMIO_MAP_RANGE0 0x141d +#define mmBIF_GPUIOV_MMIO_MAP_RANGE1 0x141e +#define mmBIF_GPUIOV_MMIO_MAP_RANGE2 0x141f +#define mmBIF_GPUIOV_MMIO_MAP_RANGE3 0x1420 +#define mmBIF_GPUIOV_MMIO_MAP_RANGE4 0x1421 +#define mmBIF_GPUIOV_MMIO_MAP_RANGE5 0x1422 +#define mmBIF_GPU_IDLE_LATENCY 0x1415 +#define mmBIF_MMIO_MAP_RANGE0 0x1416 +#define mmBIF_MMIO_MAP_RANGE1 0x1417 +#define mmBIF_MMIO_MAP_RANGE2 0x1418 +#define mmBIF_MMIO_MAP_RANGE3 0x1419 +#define mmBIF_MMIO_MAP_RANGE4 0x141a +#define mmBIF_MMIO_MAP_RANGE5 0x141b +#define mmVENDOR_ID 0x0 +#define mmDEVICE_ID 0x0 +#define mmCOMMAND 0x1 +#define mmSTATUS 0x1 +#define mmREVISION_ID 0x2 +#define mmPROG_INTERFACE 0x2 +#define mmSUB_CLASS 0x2 +#define mmBASE_CLASS 0x2 +#define mmCACHE_LINE 0x3 +#define mmLATENCY 0x3 +#define mmHEADER 0x3 +#define mmBIST 0x3 +#define mmBASE_ADDR_1 0x4 +#define mmBASE_ADDR_2 0x5 +#define mmBASE_ADDR_3 0x6 +#define mmBASE_ADDR_4 0x7 +#define mmBASE_ADDR_5 0x8 +#define mmBASE_ADDR_6 0x9 +#define mmROM_BASE_ADDR 0xc +#define mmCAP_PTR 0xd +#define mmINTERRUPT_LINE 0xf +#define mmINTERRUPT_PIN 0xf +#define mmADAPTER_ID 0xb +#define mmMIN_GRANT 0xf +#define mmMAX_LATENCY 0xf +#define mmVENDOR_CAP_LIST 0x12 +#define mmADAPTER_ID_W 0x13 +#define mmPMI_CAP_LIST 0x14 +#define mmPMI_CAP 0x14 +#define mmPMI_STATUS_CNTL 0x15 +#define mmPCIE_CAP_LIST 0x16 +#define mmPCIE_CAP 0x16 +#define mmDEVICE_CAP 0x17 +#define mmDEVICE_CNTL 0x18 +#define mmDEVICE_STATUS 0x18 +#define mmLINK_CAP 0x19 +#define mmLINK_CNTL 0x1a +#define mmLINK_STATUS 0x1a +#define mmDEVICE_CAP2 0x1f +#define mmDEVICE_CNTL2 0x20 +#define mmDEVICE_STATUS2 0x20 +#define mmLINK_CAP2 0x21 +#define mmLINK_CNTL2 0x22 +#define mmLINK_STATUS2 0x22 +#define mmMSI_CAP_LIST 0x28 +#define mmMSI_MSG_CNTL 0x28 +#define mmMSI_MSG_ADDR_LO 0x29 +#define mmMSI_MSG_ADDR_HI 0x2a +#define mmMSI_MSG_DATA_64 0x2b +#define mmMSI_MSG_DATA 0x2a +#define mmMSI_MASK 0x2b +#define mmMSI_PENDING 0x2c +#define mmMSI_MASK_64 0x2c +#define mmMSI_PENDING_64 0x2d +#define mmMSIX_CAP_LIST 0x30 +#define mmMSIX_MSG_CNTL 0x30 +#define mmMSIX_TABLE 0x31 +#define mmMSIX_PBA 0x32 +#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40 +#define mmPCIE_VENDOR_SPECIFIC_HDR 0x41 +#define mmPCIE_VENDOR_SPECIFIC1 0x42 +#define mmPCIE_VENDOR_SPECIFIC2 0x43 +#define mmPCIE_VC_ENH_CAP_LIST 0x44 +#define mmPCIE_PORT_VC_CAP_REG1 0x45 +#define mmPCIE_PORT_VC_CAP_REG2 0x46 +#define mmPCIE_PORT_VC_CNTL 0x47 +#define mmPCIE_PORT_VC_STATUS 0x47 +#define mmPCIE_VC0_RESOURCE_CAP 0x48 +#define mmPCIE_VC0_RESOURCE_CNTL 0x49 +#define mmPCIE_VC0_RESOURCE_STATUS 0x4a +#define mmPCIE_VC1_RESOURCE_CAP 0x4b +#define mmPCIE_VC1_RESOURCE_CNTL 0x4c +#define mmPCIE_VC1_RESOURCE_STATUS 0x4d +#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50 +#define mmPCIE_DEV_SERIAL_NUM_DW1 0x51 +#define mmPCIE_DEV_SERIAL_NUM_DW2 0x52 +#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54 +#define mmPCIE_UNCORR_ERR_STATUS 0x55 +#define mmPCIE_UNCORR_ERR_MASK 0x56 +#define mmPCIE_UNCORR_ERR_SEVERITY 0x57 +#define mmPCIE_CORR_ERR_STATUS 0x58 +#define mmPCIE_CORR_ERR_MASK 0x59 +#define mmPCIE_ADV_ERR_CAP_CNTL 0x5a +#define mmPCIE_HDR_LOG0 0x5b +#define mmPCIE_HDR_LOG1 0x5c +#define mmPCIE_HDR_LOG2 0x5d +#define mmPCIE_HDR_LOG3 0x5e +#define mmPCIE_TLP_PREFIX_LOG0 0x62 +#define mmPCIE_TLP_PREFIX_LOG1 0x63 +#define mmPCIE_TLP_PREFIX_LOG2 0x64 +#define mmPCIE_TLP_PREFIX_LOG3 0x65 +#define mmPCIE_BAR_ENH_CAP_LIST 0x80 +#define mmPCIE_BAR1_CAP 0x81 +#define mmPCIE_BAR1_CNTL 0x82 +#define mmPCIE_BAR2_CAP 0x83 +#define mmPCIE_BAR2_CNTL 0x84 +#define mmPCIE_BAR3_CAP 0x85 +#define mmPCIE_BAR3_CNTL 0x86 +#define mmPCIE_BAR4_CAP 0x87 +#define mmPCIE_BAR4_CNTL 0x88 +#define mmPCIE_BAR5_CAP 0x89 +#define mmPCIE_BAR5_CNTL 0x8a +#define mmPCIE_BAR6_CAP 0x8b +#define mmPCIE_BAR6_CNTL 0x8c +#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90 +#define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91 +#define mmPCIE_PWR_BUDGET_DATA 0x92 +#define mmPCIE_PWR_BUDGET_CAP 0x93 +#define mmPCIE_DPA_ENH_CAP_LIST 0x94 +#define mmPCIE_DPA_CAP 0x95 +#define mmPCIE_DPA_LATENCY_INDICATOR 0x96 +#define mmPCIE_DPA_STATUS 0x97 +#define mmPCIE_DPA_CNTL 0x97 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99 +#define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c +#define mmPCIE_LINK_CNTL3 0x9d +#define mmPCIE_LANE_ERROR_STATUS 0x9e +#define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f +#define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f +#define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0 +#define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0 +#define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1 +#define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1 +#define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2 +#define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2 +#define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3 +#define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3 +#define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4 +#define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4 +#define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5 +#define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5 +#define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6 +#define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6 +#define mmPCIE_ACS_ENH_CAP_LIST 0xa8 +#define mmPCIE_ACS_CAP 0xa9 +#define mmPCIE_ACS_CNTL 0xa9 +#define mmPCIE_ATS_ENH_CAP_LIST 0xac +#define mmPCIE_ATS_CAP 0xad +#define mmPCIE_ATS_CNTL 0xad +#define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0 +#define mmPCIE_PAGE_REQ_CNTL 0xb1 +#define mmPCIE_PAGE_REQ_STATUS 0xb1 +#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2 +#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3 +#define mmPCIE_PASID_ENH_CAP_LIST 0xb4 +#define mmPCIE_PASID_CAP 0xb5 +#define mmPCIE_PASID_CNTL 0xb5 +#define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8 +#define mmPCIE_TPH_REQR_CAP 0xb9 +#define mmPCIE_TPH_REQR_CNTL 0xba +#define mmPCIE_MC_ENH_CAP_LIST 0xbc +#define mmPCIE_MC_CAP 0xbd +#define mmPCIE_MC_CNTL 0xbd +#define mmPCIE_MC_ADDR0 0xbe +#define mmPCIE_MC_ADDR1 0xbf +#define mmPCIE_MC_RCV0 0xc0 +#define mmPCIE_MC_RCV1 0xc1 +#define mmPCIE_MC_BLOCK_ALL0 0xc2 +#define mmPCIE_MC_BLOCK_ALL1 0xc3 +#define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4 +#define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5 +#define mmPCIE_LTR_ENH_CAP_LIST 0xc8 +#define mmPCIE_LTR_CAP 0xc9 +#define mmPCIE_ARI_ENH_CAP_LIST 0xca +#define mmPCIE_ARI_CAP 0xcb +#define mmPCIE_ARI_CNTL 0xcb +#define mmPCIE_SRIOV_ENH_CAP_LIST 0xcc +#define mmPCIE_SRIOV_CAP 0xcd +#define mmPCIE_SRIOV_CONTROL 0xce +#define mmPCIE_SRIOV_STATUS 0xce +#define mmPCIE_SRIOV_INITIAL_VFS 0xcf +#define mmPCIE_SRIOV_TOTAL_VFS 0xcf +#define mmPCIE_SRIOV_NUM_VFS 0xd0 +#define mmPCIE_SRIOV_FUNC_DEP_LINK 0xd0 +#define mmPCIE_SRIOV_FIRST_VF_OFFSET 0xd1 +#define mmPCIE_SRIOV_VF_STRIDE 0xd1 +#define mmPCIE_SRIOV_VF_DEVICE_ID 0xd2 +#define mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xd3 +#define mmPCIE_SRIOV_SYSTEM_PAGE_SIZE 0xd4 +#define mmPCIE_SRIOV_VF_BASE_ADDR_0 0xd5 +#define mmPCIE_SRIOV_VF_BASE_ADDR_1 0xd6 +#define mmPCIE_SRIOV_VF_BASE_ADDR_2 0xd7 +#define mmPCIE_SRIOV_VF_BASE_ADDR_3 0xd8 +#define mmPCIE_SRIOV_VF_BASE_ADDR_4 0xd9 +#define mmPCIE_SRIOV_VF_BASE_ADDR_5 0xda +#define mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xdb +#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x100 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x101 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x102 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC 0x103 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS 0x104 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x105 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION 0x106 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS 0x107 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x108 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x109 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS 0x10a +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x10b +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x10c +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x10d +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x10e +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x10f +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x110 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x111 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x112 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x113 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x114 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x115 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x116 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x117 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x118 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x119 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x11a +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x11b +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT 0x11c +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0 0x11d +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1 0x11e +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2 0x11f +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3 0x120 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4 0x121 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5 0x122 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0 0x124 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1 0x125 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2 0x126 +#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3 0x127 +#define mmPCIE_INDEX 0xe +#define mmPCIE_DATA 0xf +#define mmPCIE_INDEX_2 0xc +#define mmPCIE_DATA_2 0xd +#define ixPCIE_HOLD_TRAINING_A 0x1500820 +#define ixLNCNT_CONTROL 0x1508030 +#define ixCFG_LNC_WINDOW 0x1508031 +#define ixLNCNT_QUAN_THRD 0x1508032 +#define ixLNCNT_WEIGHT 0x1508033 +#define ixLNC_TOTAL_WACC 0x1508034 +#define ixLNC_BW_WACC 0x1508035 +#define ixLNC_CMN_WACC 0x1508036 +#define mmPCIE_EFUSE 0xfc0 +#define mmPCIE_EFUSE2 0xfc1 +#define mmPCIE_EFUSE3 0xfc2 +#define mmPCIE_EFUSE4 0xfc3 +#define mmPCIE_EFUSE5 0xfc4 +#define mmPCIE_EFUSE6 0xfc5 +#define mmPCIE_EFUSE7 0xfc6 +#define ixPCIE_WRAP_SCRATCH1 0x1308001 +#define ixPCIE_WRAP_SCRATCH2 0x1308002 +#define ixPCIE_WRAP_REG_TARG_MISC 0x1308005 +#define ixPCIE_WRAP_DTM_MISC 0x1308006 +#define ixPCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007 +#define ixPCIE_WRAP_MISC 0x1308008 +#define ixPCIE_WRAP_PIF_MISC 0x1308009 +#define ixPCIE_RXDET_OVERRIDE 0x130800a +#define ixREG_ADAPT_pciecore0_CONTROL 0x1308090 +#define ixREG_ADAPT_pwregt_CONTROL 0x1308096 +#define ixREG_ADAPT_pwregr_CONTROL 0x1308097 +#define ixREG_ADAPT_pif0_CONTROL 0x1308098 +#define ixPCIE_RESERVED 0x1400000 +#define ixPCIE_SCRATCH 0x1400001 +#define ixPCIE_HW_DEBUG 0x1400002 +#define ixPCIE_RX_NUM_NAK 0x140000e +#define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f +#define ixPCIE_CNTL 0x1400010 +#define ixPCIE_CONFIG_CNTL 0x1400011 +#define ixPCIE_DEBUG_CNTL 0x1400012 +#define ixPCIE_INT_CNTL 0x140001a +#define ixPCIE_INT_STATUS 0x140001b +#define ixPCIE_CNTL2 0x140001c +#define ixPCIE_RX_CNTL2 0x140001d +#define ixPCIE_TX_F0_ATTR_CNTL 0x140001e +#define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f +#define ixPCIE_CI_CNTL 0x1400020 +#define ixPCIE_BUS_CNTL 0x1400021 +#define ixPCIE_LC_STATE6 0x1400022 +#define ixPCIE_LC_STATE7 0x1400023 +#define ixPCIE_LC_STATE8 0x1400024 +#define ixPCIE_LC_STATE9 0x1400025 +#define ixPCIE_LC_STATE10 0x1400026 +#define ixPCIE_LC_STATE11 0x1400027 +#define ixPCIE_LC_STATUS1 0x1400028 +#define ixPCIE_LC_STATUS2 0x1400029 +#define ixPCIE_WPR_CNTL 0x1400030 +#define ixPCIE_RX_LAST_TLP0 0x1400031 +#define ixPCIE_RX_LAST_TLP1 0x1400032 +#define ixPCIE_RX_LAST_TLP2 0x1400033 +#define ixPCIE_RX_LAST_TLP3 0x1400034 +#define ixPCIE_TX_LAST_TLP0 0x1400035 +#define ixPCIE_TX_LAST_TLP1 0x1400036 +#define ixPCIE_TX_LAST_TLP2 0x1400037 +#define ixPCIE_TX_LAST_TLP3 0x1400038 +#define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a +#define ixPCIE_I2C_REG_DATA 0x140003b +#define ixPCIE_CFG_CNTL 0x140003c +#define ixPCIE_LC_PM_CNTL 0x140003d +#define ixPCIE_P_CNTL 0x1400040 +#define ixPCIE_P_BUF_STATUS 0x1400041 +#define ixPCIE_P_DECODER_STATUS 0x1400042 +#define ixPCIE_P_MISC_STATUS 0x1400043 +#define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050 +#define ixPCIE_OBFF_CNTL 0x1400061 +#define ixPCIE_TX_LTR_CNTL 0x1400060 +#define ixPCIE_IDLE_STATUS 0x1400062 +#define ixPCIE_PERF_COUNT_CNTL 0x1400080 +#define ixPCIE_PERF_CNTL_TXCLK 0x1400081 +#define ixPCIE_PERF_COUNT0_TXCLK 0x1400082 +#define ixPCIE_PERF_COUNT1_TXCLK 0x1400083 +#define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084 +#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085 +#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086 +#define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087 +#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088 +#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089 +#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a +#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b +#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c +#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d +#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e +#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f +#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 +#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 +#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 +#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 +#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 +#define ixPCIE_PERF_CNTL_TXCLK2 0x1400095 +#define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096 +#define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097 +#define ixPCIE_STRAP_F0 0x14000b0 +#define ixPCIE_STRAP_F1 0x14000b1 +#define ixPCIE_STRAP_F2 0x14000b2 +#define ixPCIE_STRAP_F3 0x14000b3 +#define ixPCIE_STRAP_F4 0x14000b4 +#define ixPCIE_STRAP_F5 0x14000b5 +#define ixPCIE_STRAP_F6 0x14000b6 +#define ixPCIE_STRAP_MSIX 0x14000b7 +#define ixPCIE_STRAP_MISC 0x14000c0 +#define ixPCIE_STRAP_MISC2 0x14000c1 +#define ixPCIE_STRAP_PI 0x14000c2 +#define ixPCIE_STRAP_I2C_BD 0x14000c4 +#define ixPCIE_PRBS_CLR 0x14000c8 +#define ixPCIE_PRBS_STATUS1 0x14000c9 +#define ixPCIE_PRBS_STATUS2 0x14000ca +#define ixPCIE_PRBS_FREERUN 0x14000cb +#define ixPCIE_PRBS_MISC 0x14000cc +#define ixPCIE_PRBS_USER_PATTERN 0x14000cd +#define ixPCIE_PRBS_LO_BITCNT 0x14000ce +#define ixPCIE_PRBS_HI_BITCNT 0x14000cf +#define ixPCIE_PRBS_ERRCNT_0 0x14000d0 +#define ixPCIE_PRBS_ERRCNT_1 0x14000d1 +#define ixPCIE_PRBS_ERRCNT_2 0x14000d2 +#define ixPCIE_PRBS_ERRCNT_3 0x14000d3 +#define ixPCIE_PRBS_ERRCNT_4 0x14000d4 +#define ixPCIE_PRBS_ERRCNT_5 0x14000d5 +#define ixPCIE_PRBS_ERRCNT_6 0x14000d6 +#define ixPCIE_PRBS_ERRCNT_7 0x14000d7 +#define ixPCIE_PRBS_ERRCNT_8 0x14000d8 +#define ixPCIE_PRBS_ERRCNT_9 0x14000d9 +#define ixPCIE_PRBS_ERRCNT_10 0x14000da +#define ixPCIE_PRBS_ERRCNT_11 0x14000db +#define ixPCIE_PRBS_ERRCNT_12 0x14000dc +#define ixPCIE_PRBS_ERRCNT_13 0x14000dd +#define ixPCIE_PRBS_ERRCNT_14 0x14000de +#define ixPCIE_PRBS_ERRCNT_15 0x14000df +#define ixPCIE_F0_DPA_CAP 0x14000e0 +#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4 +#define ixPCIE_F0_DPA_CNTL 0x14000e5 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee +#define mmSWRST_COMMAND_STATUS 0x14a0 +#define mmSWRST_GENERAL_CONTROL 0x14a1 +#define mmSWRST_COMMAND_0 0x14a2 +#define mmSWRST_COMMAND_1 0x14a3 +#define mmSWRST_CONTROL_0 0x14a4 +#define mmSWRST_CONTROL_1 0x14a5 +#define mmSWRST_CONTROL_2 0x14a6 +#define mmSWRST_CONTROL_3 0x14a7 +#define mmSWRST_CONTROL_4 0x14a8 +#define mmSWRST_CONTROL_5 0x14a9 +#define mmSWRST_CONTROL_6 0x14aa +#define mmSWRST_EP_COMMAND_0 0x14ab +#define mmSWRST_EP_CONTROL_0 0x14ac +#define mmCPM_CONTROL 0x14b8 +#define mmGSKT_CONTROL 0x14bf +#define ixLM_CONTROL 0x1400120 +#define ixLM_PCIETXMUX0 0x1400121 +#define ixLM_PCIETXMUX1 0x1400122 +#define ixLM_PCIETXMUX2 0x1400123 +#define ixLM_PCIETXMUX3 0x1400124 +#define ixLM_PCIERXMUX0 0x1400125 +#define ixLM_PCIERXMUX1 0x1400126 +#define ixLM_PCIERXMUX2 0x1400127 +#define ixLM_PCIERXMUX3 0x1400128 +#define ixLM_LANEENABLE 0x1400129 +#define ixLM_PRBSCONTROL 0x140012a +#define ixLM_POWERCONTROL 0x140012b +#define ixLM_POWERCONTROL1 0x140012c +#define ixLM_POWERCONTROL2 0x140012d +#define ixLM_POWERCONTROL3 0x140012e +#define ixLM_POWERCONTROL4 0x140012f +#define ixPB0_GLB_CTRL_REG0 0x1200004 +#define ixPB0_GLB_CTRL_REG1 0x1200008 +#define ixPB0_GLB_CTRL_REG2 0x120000c +#define ixPB0_GLB_CTRL_REG3 0x1200010 +#define ixPB0_GLB_CTRL_REG4 0x1200014 +#define ixPB0_GLB_CTRL_REG5 0x1200018 +#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c +#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020 +#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024 +#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028 +#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c +#define ixPB0_GLB_OVRD_REG0 0x1200030 +#define ixPB0_GLB_OVRD_REG1 0x1200034 +#define ixPB0_GLB_OVRD_REG2 0x1200038 +#define ixPB0_HW_DEBUG 0x1202004 +#define ixPB0_STRAP_GLB_REG0 0x1202020 +#define ixPB0_STRAP_TX_REG0 0x1202024 +#define ixPB0_STRAP_RX_REG0 0x1202028 +#define ixPB0_STRAP_RX_REG1 0x120202c +#define ixPB0_STRAP_PLL_REG0 0x1202030 +#define ixPB0_STRAP_PIN_REG0 0x1202034 +#define ixPB0_STRAP_GLB_REG1 0x1202038 +#define ixPB0_STRAP_GLB_REG2 0x120203c +#define ixPB0_DFT_JIT_INJ_REG0 0x1203000 +#define ixPB0_DFT_JIT_INJ_REG1 0x1203004 +#define ixPB0_DFT_JIT_INJ_REG2 0x1203008 +#define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c +#define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010 +#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000 +#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010 +#define ixPB0_PLL_RO0_CTRL_REG0 0x1204440 +#define ixPB0_PLL_RO0_OVRD_REG0 0x1204450 +#define ixPB0_PLL_RO0_OVRD_REG1 0x1204454 +#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460 +#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464 +#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468 +#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c +#define ixPB0_PLL_LC0_CTRL_REG0 0x1204480 +#define ixPB0_PLL_LC0_OVRD_REG0 0x1204490 +#define ixPB0_PLL_LC0_OVRD_REG1 0x1204494 +#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500 +#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504 +#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508 +#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c +#define ixPB0_RX_GLB_CTRL_REG0 0x1206000 +#define ixPB0_RX_GLB_CTRL_REG1 0x1206004 +#define ixPB0_RX_GLB_CTRL_REG2 0x1206008 +#define ixPB0_RX_GLB_CTRL_REG3 0x120600c +#define ixPB0_RX_GLB_CTRL_REG4 0x1206010 +#define ixPB0_RX_GLB_CTRL_REG5 0x1206014 +#define ixPB0_RX_GLB_CTRL_REG6 0x1206018 +#define ixPB0_RX_GLB_CTRL_REG7 0x120601c +#define ixPB0_RX_GLB_CTRL_REG8 0x1206020 +#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028 +#define ixPB0_RX_GLB_OVRD_REG0 0x1206030 +#define ixPB0_RX_GLB_OVRD_REG1 0x1206034 +#define ixPB0_RX_LANE0_CTRL_REG0 0x1206440 +#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448 +#define ixPB0_RX_LANE1_CTRL_REG0 0x1206480 +#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488 +#define ixPB0_RX_LANE2_CTRL_REG0 0x1206500 +#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508 +#define ixPB0_RX_LANE3_CTRL_REG0 0x1206600 +#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608 +#define ixPB0_RX_LANE4_CTRL_REG0 0x1206800 +#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848 +#define ixPB0_RX_LANE5_CTRL_REG0 0x1206880 +#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888 +#define ixPB0_RX_LANE6_CTRL_REG0 0x1206900 +#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908 +#define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00 +#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08 +#define ixPB0_RX_LANE8_CTRL_REG0 0x1207440 +#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448 +#define ixPB0_RX_LANE9_CTRL_REG0 0x1207480 +#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488 +#define ixPB0_RX_LANE10_CTRL_REG0 0x1207500 +#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508 +#define ixPB0_RX_LANE11_CTRL_REG0 0x1207600 +#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608 +#define ixPB0_RX_LANE12_CTRL_REG0 0x1207840 +#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848 +#define ixPB0_RX_LANE13_CTRL_REG0 0x1207880 +#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888 +#define ixPB0_RX_LANE14_CTRL_REG0 0x1207900 +#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908 +#define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00 +#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08 +#define ixPB0_TX_GLB_CTRL_REG0 0x1208000 +#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004 +#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018 +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c +#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020 +#define ixPB0_TX_GLB_OVRD_REG0 0x1208030 +#define ixPB0_TX_GLB_OVRD_REG1 0x1208034 +#define ixPB0_TX_GLB_OVRD_REG2 0x1208038 +#define ixPB0_TX_GLB_OVRD_REG3 0x120803c +#define ixPB0_TX_GLB_OVRD_REG4 0x1208040 +#define ixPB0_TX_LANE0_CTRL_REG0 0x1208440 +#define ixPB0_TX_LANE0_OVRD_REG0 0x1208444 +#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448 +#define ixPB0_TX_LANE1_CTRL_REG0 0x1208480 +#define ixPB0_TX_LANE1_OVRD_REG0 0x1208484 +#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488 +#define ixPB0_TX_LANE2_CTRL_REG0 0x1208500 +#define ixPB0_TX_LANE2_OVRD_REG0 0x1208504 +#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508 +#define ixPB0_TX_LANE3_CTRL_REG0 0x1208600 +#define ixPB0_TX_LANE3_OVRD_REG0 0x1208604 +#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608 +#define ixPB0_TX_LANE4_CTRL_REG0 0x1208840 +#define ixPB0_TX_LANE4_OVRD_REG0 0x1208844 +#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848 +#define ixPB0_TX_LANE5_CTRL_REG0 0x1208880 +#define ixPB0_TX_LANE5_OVRD_REG0 0x1208884 +#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888 +#define ixPB0_TX_LANE6_CTRL_REG0 0x1208900 +#define ixPB0_TX_LANE6_OVRD_REG0 0x1208904 +#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908 +#define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00 +#define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04 +#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08 +#define ixPB0_TX_LANE8_CTRL_REG0 0x1209440 +#define ixPB0_TX_LANE8_OVRD_REG0 0x1209444 +#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448 +#define ixPB0_TX_LANE9_CTRL_REG0 0x1209480 +#define ixPB0_TX_LANE9_OVRD_REG0 0x1209484 +#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488 +#define ixPB0_TX_LANE10_CTRL_REG0 0x1209500 +#define ixPB0_TX_LANE10_OVRD_REG0 0x1209504 +#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508 +#define ixPB0_TX_LANE11_CTRL_REG0 0x1209600 +#define ixPB0_TX_LANE11_OVRD_REG0 0x1209604 +#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608 +#define ixPB0_TX_LANE12_CTRL_REG0 0x1209840 +#define ixPB0_TX_LANE12_OVRD_REG0 0x1209844 +#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848 +#define ixPB0_TX_LANE13_CTRL_REG0 0x1209880 +#define ixPB0_TX_LANE13_OVRD_REG0 0x1209884 +#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888 +#define ixPB0_TX_LANE14_CTRL_REG0 0x1209900 +#define ixPB0_TX_LANE14_OVRD_REG0 0x1209904 +#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908 +#define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00 +#define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04 +#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08 +#define ixPB1_GLB_CTRL_REG0 0x2200004 +#define ixPB1_GLB_CTRL_REG1 0x2200008 +#define ixPB1_GLB_CTRL_REG2 0x220000c +#define ixPB1_GLB_CTRL_REG3 0x2200010 +#define ixPB1_GLB_CTRL_REG4 0x2200014 +#define ixPB1_GLB_CTRL_REG5 0x2200018 +#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c +#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020 +#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024 +#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028 +#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c +#define ixPB1_GLB_OVRD_REG0 0x2200030 +#define ixPB1_GLB_OVRD_REG1 0x2200034 +#define ixPB1_GLB_OVRD_REG2 0x2200038 +#define ixPB1_HW_DEBUG 0x2202004 +#define ixPB1_STRAP_GLB_REG0 0x2202020 +#define ixPB1_STRAP_TX_REG0 0x2202024 +#define ixPB1_STRAP_RX_REG0 0x2202028 +#define ixPB1_STRAP_RX_REG1 0x220202c +#define ixPB1_STRAP_PLL_REG0 0x2202030 +#define ixPB1_STRAP_PIN_REG0 0x2202034 +#define ixPB1_STRAP_GLB_REG1 0x2202038 +#define ixPB1_STRAP_GLB_REG2 0x220203c +#define ixPB1_DFT_JIT_INJ_REG0 0x2203000 +#define ixPB1_DFT_JIT_INJ_REG1 0x2203004 +#define ixPB1_DFT_JIT_INJ_REG2 0x2203008 +#define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c +#define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010 +#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000 +#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010 +#define ixPB1_PLL_RO0_CTRL_REG0 0x2204440 +#define ixPB1_PLL_RO0_OVRD_REG0 0x2204450 +#define ixPB1_PLL_RO0_OVRD_REG1 0x2204454 +#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460 +#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464 +#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468 +#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c +#define ixPB1_PLL_LC0_CTRL_REG0 0x2204480 +#define ixPB1_PLL_LC0_OVRD_REG0 0x2204490 +#define ixPB1_PLL_LC0_OVRD_REG1 0x2204494 +#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500 +#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504 +#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508 +#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c +#define ixPB1_RX_GLB_CTRL_REG0 0x2206000 +#define ixPB1_RX_GLB_CTRL_REG1 0x2206004 +#define ixPB1_RX_GLB_CTRL_REG2 0x2206008 +#define ixPB1_RX_GLB_CTRL_REG3 0x220600c +#define ixPB1_RX_GLB_CTRL_REG4 0x2206010 +#define ixPB1_RX_GLB_CTRL_REG5 0x2206014 +#define ixPB1_RX_GLB_CTRL_REG6 0x2206018 +#define ixPB1_RX_GLB_CTRL_REG7 0x220601c +#define ixPB1_RX_GLB_CTRL_REG8 0x2206020 +#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028 +#define ixPB1_RX_GLB_OVRD_REG0 0x2206030 +#define ixPB1_RX_GLB_OVRD_REG1 0x2206034 +#define ixPB1_RX_LANE0_CTRL_REG0 0x2206440 +#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448 +#define ixPB1_RX_LANE1_CTRL_REG0 0x2206480 +#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488 +#define ixPB1_RX_LANE2_CTRL_REG0 0x2206500 +#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508 +#define ixPB1_RX_LANE3_CTRL_REG0 0x2206600 +#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608 +#define ixPB1_RX_LANE4_CTRL_REG0 0x2206800 +#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848 +#define ixPB1_RX_LANE5_CTRL_REG0 0x2206880 +#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888 +#define ixPB1_RX_LANE6_CTRL_REG0 0x2206900 +#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908 +#define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00 +#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08 +#define ixPB1_RX_LANE8_CTRL_REG0 0x2207440 +#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448 +#define ixPB1_RX_LANE9_CTRL_REG0 0x2207480 +#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488 +#define ixPB1_RX_LANE10_CTRL_REG0 0x2207500 +#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508 +#define ixPB1_RX_LANE11_CTRL_REG0 0x2207600 +#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608 +#define ixPB1_RX_LANE12_CTRL_REG0 0x2207840 +#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848 +#define ixPB1_RX_LANE13_CTRL_REG0 0x2207880 +#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888 +#define ixPB1_RX_LANE14_CTRL_REG0 0x2207900 +#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908 +#define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00 +#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08 +#define ixPB1_TX_GLB_CTRL_REG0 0x2208000 +#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004 +#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018 +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c +#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020 +#define ixPB1_TX_GLB_OVRD_REG0 0x2208030 +#define ixPB1_TX_GLB_OVRD_REG1 0x2208034 +#define ixPB1_TX_GLB_OVRD_REG2 0x2208038 +#define ixPB1_TX_GLB_OVRD_REG3 0x220803c +#define ixPB1_TX_GLB_OVRD_REG4 0x2208040 +#define ixPB1_TX_LANE0_CTRL_REG0 0x2208440 +#define ixPB1_TX_LANE0_OVRD_REG0 0x2208444 +#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448 +#define ixPB1_TX_LANE1_CTRL_REG0 0x2208480 +#define ixPB1_TX_LANE1_OVRD_REG0 0x2208484 +#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488 +#define ixPB1_TX_LANE2_CTRL_REG0 0x2208500 +#define ixPB1_TX_LANE2_OVRD_REG0 0x2208504 +#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508 +#define ixPB1_TX_LANE3_CTRL_REG0 0x2208600 +#define ixPB1_TX_LANE3_OVRD_REG0 0x2208604 +#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608 +#define ixPB1_TX_LANE4_CTRL_REG0 0x2208840 +#define ixPB1_TX_LANE4_OVRD_REG0 0x2208844 +#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848 +#define ixPB1_TX_LANE5_CTRL_REG0 0x2208880 +#define ixPB1_TX_LANE5_OVRD_REG0 0x2208884 +#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888 +#define ixPB1_TX_LANE6_CTRL_REG0 0x2208900 +#define ixPB1_TX_LANE6_OVRD_REG0 0x2208904 +#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908 +#define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00 +#define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04 +#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08 +#define ixPB1_TX_LANE8_CTRL_REG0 0x2209440 +#define ixPB1_TX_LANE8_OVRD_REG0 0x2209444 +#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448 +#define ixPB1_TX_LANE9_CTRL_REG0 0x2209480 +#define ixPB1_TX_LANE9_OVRD_REG0 0x2209484 +#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488 +#define ixPB1_TX_LANE10_CTRL_REG0 0x2209500 +#define ixPB1_TX_LANE10_OVRD_REG0 0x2209504 +#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508 +#define ixPB1_TX_LANE11_CTRL_REG0 0x2209600 +#define ixPB1_TX_LANE11_OVRD_REG0 0x2209604 +#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608 +#define ixPB1_TX_LANE12_CTRL_REG0 0x2209840 +#define ixPB1_TX_LANE12_OVRD_REG0 0x2209844 +#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848 +#define ixPB1_TX_LANE13_CTRL_REG0 0x2209880 +#define ixPB1_TX_LANE13_OVRD_REG0 0x2209884 +#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888 +#define ixPB1_TX_LANE14_CTRL_REG0 0x2209900 +#define ixPB1_TX_LANE14_OVRD_REG0 0x2209904 +#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908 +#define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00 +#define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04 +#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08 +#define ixPB0_PIF_SCRATCH 0x1100001 +#define ixPB0_PIF_HW_DEBUG 0x1100002 +#define ixPB0_PIF_STRAP_0 0x1100003 +#define ixPB0_PIF_CTRL 0x1100004 +#define ixPB0_PIF_TX_CTRL 0x1100008 +#define ixPB0_PIF_TX_CTRL2 0x1100009 +#define ixPB0_PIF_RX_CTRL 0x110000a +#define ixPB0_PIF_RX_CTRL2 0x110000b +#define ixPB0_PIF_GLB_OVRD 0x110000c +#define ixPB0_PIF_GLB_OVRD2 0x110000d +#define ixPB0_PIF_BIF_CMD_STATUS 0x1100010 +#define ixPB0_PIF_CMD_BUS_CTRL 0x1100011 +#define ixPB0_PIF_CMD_BUS_GLB_OVRD 0x1100013 +#define ixPB0_PIF_LANE0_OVRD 0x1100014 +#define ixPB0_PIF_LANE0_OVRD2 0x1100015 +#define ixPB0_PIF_LANE1_OVRD 0x1100016 +#define ixPB0_PIF_LANE1_OVRD2 0x1100017 +#define ixPB0_PIF_LANE2_OVRD 0x1100018 +#define ixPB0_PIF_LANE2_OVRD2 0x1100019 +#define ixPB0_PIF_LANE3_OVRD 0x110001a +#define ixPB0_PIF_LANE3_OVRD2 0x110001b +#define ixPB0_PIF_LANE4_OVRD 0x110001c +#define ixPB0_PIF_LANE4_OVRD2 0x110001d +#define ixPB0_PIF_LANE5_OVRD 0x110001e +#define ixPB0_PIF_LANE5_OVRD2 0x110001f +#define ixPB0_PIF_LANE6_OVRD 0x1100020 +#define ixPB0_PIF_LANE6_OVRD2 0x1100021 +#define ixPB0_PIF_LANE7_OVRD 0x1100022 +#define ixPB0_PIF_LANE7_OVRD2 0x1100023 +#define ixPB1_PIF_SCRATCH 0x2100001 +#define ixPB1_PIF_HW_DEBUG 0x2100002 +#define ixPB1_PIF_STRAP_0 0x2100003 +#define ixPB1_PIF_CTRL 0x2100004 +#define ixPB1_PIF_TX_CTRL 0x2100008 +#define ixPB1_PIF_TX_CTRL2 0x2100009 +#define ixPB1_PIF_RX_CTRL 0x210000a +#define ixPB1_PIF_RX_CTRL2 0x210000b +#define ixPB1_PIF_GLB_OVRD 0x210000c +#define ixPB1_PIF_GLB_OVRD2 0x210000d +#define ixPB1_PIF_BIF_CMD_STATUS 0x2100010 +#define ixPB1_PIF_CMD_BUS_CTRL 0x2100011 +#define ixPB1_PIF_CMD_BUS_GLB_OVRD 0x2100013 +#define ixPB1_PIF_LANE0_OVRD 0x2100014 +#define ixPB1_PIF_LANE0_OVRD2 0x2100015 +#define ixPB1_PIF_LANE1_OVRD 0x2100016 +#define ixPB1_PIF_LANE1_OVRD2 0x2100017 +#define ixPB1_PIF_LANE2_OVRD 0x2100018 +#define ixPB1_PIF_LANE2_OVRD2 0x2100019 +#define ixPB1_PIF_LANE3_OVRD 0x210001a +#define ixPB1_PIF_LANE3_OVRD2 0x210001b +#define ixPB1_PIF_LANE4_OVRD 0x210001c +#define ixPB1_PIF_LANE4_OVRD2 0x210001d +#define ixPB1_PIF_LANE5_OVRD 0x210001e +#define ixPB1_PIF_LANE5_OVRD2 0x210001f +#define ixPB1_PIF_LANE6_OVRD 0x2100020 +#define ixPB1_PIF_LANE6_OVRD2 0x2100021 +#define ixPB1_PIF_LANE7_OVRD 0x2100022 +#define ixPB1_PIF_LANE7_OVRD2 0x2100023 +#define ixPCIEP_RESERVED 0x10010000 +#define ixPCIEP_SCRATCH 0x10010001 +#define ixPCIEP_HW_DEBUG 0x10010002 +#define ixPCIEP_PORT_CNTL 0x10010010 +#define ixPCIE_TX_CNTL 0x10010020 +#define ixPCIE_TX_REQUESTER_ID 0x10010021 +#define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022 +#define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023 +#define ixPCIE_TX_SEQ 0x10010024 +#define ixPCIE_TX_REPLAY 0x10010025 +#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026 +#define ixPCIE_TX_CREDITS_ADVT_P 0x10010030 +#define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031 +#define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032 +#define ixPCIE_TX_CREDITS_INIT_P 0x10010033 +#define ixPCIE_TX_CREDITS_INIT_NP 0x10010034 +#define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035 +#define ixPCIE_TX_CREDITS_STATUS 0x10010036 +#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037 +#define ixPCIE_P_PORT_LANE_STATUS 0x10010050 +#define ixPCIE_FC_P 0x10010060 +#define ixPCIE_FC_NP 0x10010061 +#define ixPCIE_FC_CPL 0x10010062 +#define ixPCIE_ERR_CNTL 0x1001006a +#define ixPCIE_RX_CNTL 0x10010070 +#define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071 +#define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072 +#define ixPCIE_RX_CNTL3 0x10010074 +#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080 +#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081 +#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082 +#define ixPCIEP_ERROR_INJECT_PHYSICAL 0x10010083 +#define ixPCIEP_ERROR_INJECT_TRANSACTION 0x10010084 +#define ixPCIEP_SRIOV_PRIV_CTRL 0x10010085 +#define ixPCIE_LC_CNTL 0x100100a0 +#define ixPCIE_LC_CNTL2 0x100100b1 +#define ixPCIE_LC_CNTL3 0x100100b5 +#define ixPCIE_LC_CNTL4 0x100100b6 +#define ixPCIE_LC_CNTL5 0x100100b7 +#define ixPCIE_LC_CNTL6 0x100100bb +#define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2 +#define ixPCIE_LC_TRAINING_CNTL 0x100100a1 +#define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2 +#define ixPCIE_LC_N_FTS_CNTL 0x100100a3 +#define ixPCIE_LC_SPEED_CNTL 0x100100a4 +#define ixPCIE_LC_CDR_CNTL 0x100100b3 +#define ixPCIE_LC_LANE_CNTL 0x100100b4 +#define ixPCIE_LC_FORCE_COEFF 0x100100b8 +#define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9 +#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba +#define ixPCIE_LC_STATE0 0x100100a5 +#define ixPCIE_LC_STATE1 0x100100a6 +#define ixPCIE_LC_STATE2 0x100100a7 +#define ixPCIE_LC_STATE3 0x100100a8 +#define ixPCIE_LC_STATE4 0x100100a9 +#define ixPCIE_LC_STATE5 0x100100aa +#define ixPCIEP_STRAP_LC 0x100100c0 +#define ixPCIEP_STRAP_MISC 0x100100c1 +#define ixPCIEP_BCH_ECC_CNTL 0x100100d0 +#define ixPCIEP_HPGI_PRIVATE 0x100100d2 +#define ixPCIEP_HPGI 0x100100da +#define mmPCIEMSIX_VECT0_ADDR_LO 0x6000 +#define mmPCIEMSIX_VECT0_ADDR_HI 0x6001 +#define mmPCIEMSIX_VECT0_MSG_DATA 0x6002 +#define mmPCIEMSIX_VECT0_CONTROL 0x6003 +#define mmPCIEMSIX_VECT1_ADDR_LO 0x6004 +#define mmPCIEMSIX_VECT1_ADDR_HI 0x6005 +#define mmPCIEMSIX_VECT1_MSG_DATA 0x6006 +#define mmPCIEMSIX_VECT1_CONTROL 0x6007 +#define mmPCIEMSIX_VECT2_ADDR_LO 0x6008 +#define mmPCIEMSIX_VECT2_ADDR_HI 0x6009 +#define mmPCIEMSIX_VECT2_MSG_DATA 0x600a +#define mmPCIEMSIX_VECT2_CONTROL 0x600b +#define mmPCIEMSIX_VECT3_ADDR_LO 0x600c +#define mmPCIEMSIX_VECT3_ADDR_HI 0x600d +#define mmPCIEMSIX_VECT3_MSG_DATA 0x600e +#define mmPCIEMSIX_VECT3_CONTROL 0x600f +#define mmPCIEMSIX_PBA 0x6200 +#define mmBIF_RFE_SNOOP_REG 0x27 +#define mmBIF_RFE_WARMRST_CNTL 0x1459 +#define mmBIF_RFE_SOFTRST_CNTL 0x1441 +#define mmBIF_RFE_IMPRST_CNTL 0x1458 +#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442 +#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443 +#define mmBIF_PWDN_COMMAND 0x1444 +#define mmBIF_PWDN_STATUS 0x1445 +#define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446 +#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447 +#define mmBIF_RFE_MST_SMBUS_CMDSTATUS 0x1448 +#define mmBIF_RFE_MST_BX_CMDSTATUS 0x1449 +#define mmBIF_RFE_MST_TMOUT_STATUS 0x144b +#define mmBIF_RFE_MMCFG_CNTL 0x144c +#define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455 +#define mmBIF_IMPCTL_SMPLCNTL 0x1450 +#define mmBIF_IMPCTL_RXCNTL 0x1451 +#define mmBIF_IMPCTL_TXCNTL_pd 0x1452 +#define mmBIF_IMPCTL_TXCNTL_pu 0x1453 +#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454 + +#endif /* BIF_5_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h new file mode 100644 index 000000000000..46b75f4bbc36 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h @@ -0,0 +1,1198 @@ +/* + * BIF_5_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_5_0_ENUM_H +#define BIF_5_0_ENUM_H + +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_scf2 = 0x2, + DBG_CLIENT_BLKID_mcd5 = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_sx30 = 0x5, + DBG_CLIENT_BLKID_mcd2 = 0x6, + DBG_CLIENT_BLKID_bci1 = 0x7, + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, + DBG_CLIENT_BLKID_mcc0 = 0x9, + DBG_CLIENT_BLKID_uvdf_0 = 0xa, + DBG_CLIENT_BLKID_uvdf_1 = 0xb, + DBG_CLIENT_BLKID_uvdf_2 = 0xc, + DBG_CLIENT_BLKID_uvdi_0 = 0xd, + DBG_CLIENT_BLKID_bci0 = 0xe, + DBG_CLIENT_BLKID_vcec0_0 = 0xf, + DBG_CLIENT_BLKID_cb100 = 0x10, + DBG_CLIENT_BLKID_cb001 = 0x11, + DBG_CLIENT_BLKID_mcd4 = 0x12, + DBG_CLIENT_BLKID_tmonw00 = 0x13, + DBG_CLIENT_BLKID_cb101 = 0x14, + DBG_CLIENT_BLKID_sx10 = 0x15, + DBG_CLIENT_BLKID_cb301 = 0x16, + DBG_CLIENT_BLKID_tmonw01 = 0x17, + DBG_CLIENT_BLKID_vcea0_0 = 0x18, + DBG_CLIENT_BLKID_vcea0_1 = 0x19, + DBG_CLIENT_BLKID_vcea0_2 = 0x1a, + DBG_CLIENT_BLKID_vcea0_3 = 0x1b, + DBG_CLIENT_BLKID_scf1 = 0x1c, + DBG_CLIENT_BLKID_sx20 = 0x1d, + DBG_CLIENT_BLKID_spim1 = 0x1e, + DBG_CLIENT_BLKID_pa10 = 0x1f, + DBG_CLIENT_BLKID_pa00 = 0x20, + DBG_CLIENT_BLKID_gmcon = 0x21, + DBG_CLIENT_BLKID_mcb = 0x22, + DBG_CLIENT_BLKID_vgt0 = 0x23, + DBG_CLIENT_BLKID_pc0 = 0x24, + DBG_CLIENT_BLKID_bci2 = 0x25, + DBG_CLIENT_BLKID_uvdb_0 = 0x26, + DBG_CLIENT_BLKID_spim3 = 0x27, + DBG_CLIENT_BLKID_cpc_0 = 0x28, + DBG_CLIENT_BLKID_cpc_1 = 0x29, + DBG_CLIENT_BLKID_uvdm_0 = 0x2a, + DBG_CLIENT_BLKID_uvdm_1 = 0x2b, + DBG_CLIENT_BLKID_uvdm_2 = 0x2c, + DBG_CLIENT_BLKID_uvdm_3 = 0x2d, + DBG_CLIENT_BLKID_cb000 = 0x2e, + DBG_CLIENT_BLKID_spim0 = 0x2f, + DBG_CLIENT_BLKID_mcc2 = 0x30, + DBG_CLIENT_BLKID_ds0 = 0x31, + DBG_CLIENT_BLKID_srbm = 0x32, + DBG_CLIENT_BLKID_ih = 0x33, + DBG_CLIENT_BLKID_sem = 0x34, + DBG_CLIENT_BLKID_sdma_0 = 0x35, + DBG_CLIENT_BLKID_sdma_1 = 0x36, + DBG_CLIENT_BLKID_hdp = 0x37, + DBG_CLIENT_BLKID_acp_0 = 0x38, + DBG_CLIENT_BLKID_acp_1 = 0x39, + DBG_CLIENT_BLKID_cb200 = 0x3a, + DBG_CLIENT_BLKID_scf3 = 0x3b, + DBG_CLIENT_BLKID_vceb1_0 = 0x3c, + DBG_CLIENT_BLKID_vcea1_0 = 0x3d, + DBG_CLIENT_BLKID_vcea1_1 = 0x3e, + DBG_CLIENT_BLKID_vcea1_2 = 0x3f, + DBG_CLIENT_BLKID_vcea1_3 = 0x40, + DBG_CLIENT_BLKID_bci3 = 0x41, + DBG_CLIENT_BLKID_mcd0 = 0x42, + DBG_CLIENT_BLKID_pa11 = 0x43, + DBG_CLIENT_BLKID_pa01 = 0x44, + DBG_CLIENT_BLKID_cb201 = 0x45, + DBG_CLIENT_BLKID_spim2 = 0x46, + DBG_CLIENT_BLKID_vgt2 = 0x47, + DBG_CLIENT_BLKID_pc2 = 0x48, + DBG_CLIENT_BLKID_smu_0 = 0x49, + DBG_CLIENT_BLKID_smu_1 = 0x4a, + DBG_CLIENT_BLKID_smu_2 = 0x4b, + DBG_CLIENT_BLKID_cb1 = 0x4c, + DBG_CLIENT_BLKID_ia0 = 0x4d, + DBG_CLIENT_BLKID_wd = 0x4e, + DBG_CLIENT_BLKID_ia1 = 0x4f, + DBG_CLIENT_BLKID_vcec1_0 = 0x50, + DBG_CLIENT_BLKID_scf0 = 0x51, + DBG_CLIENT_BLKID_vgt1 = 0x52, + DBG_CLIENT_BLKID_pc1 = 0x53, + DBG_CLIENT_BLKID_cb0 = 0x54, + DBG_CLIENT_BLKID_gdc_one_0 = 0x55, + DBG_CLIENT_BLKID_gdc_one_1 = 0x56, + DBG_CLIENT_BLKID_gdc_one_2 = 0x57, + DBG_CLIENT_BLKID_gdc_one_3 = 0x58, + DBG_CLIENT_BLKID_gdc_one_4 = 0x59, + DBG_CLIENT_BLKID_gdc_one_5 = 0x5a, + DBG_CLIENT_BLKID_gdc_one_6 = 0x5b, + DBG_CLIENT_BLKID_gdc_one_7 = 0x5c, + DBG_CLIENT_BLKID_gdc_one_8 = 0x5d, + DBG_CLIENT_BLKID_gdc_one_9 = 0x5e, + DBG_CLIENT_BLKID_gdc_one_10 = 0x5f, + DBG_CLIENT_BLKID_gdc_one_11 = 0x60, + DBG_CLIENT_BLKID_gdc_one_12 = 0x61, + DBG_CLIENT_BLKID_gdc_one_13 = 0x62, + DBG_CLIENT_BLKID_gdc_one_14 = 0x63, + DBG_CLIENT_BLKID_gdc_one_15 = 0x64, + DBG_CLIENT_BLKID_gdc_one_16 = 0x65, + DBG_CLIENT_BLKID_gdc_one_17 = 0x66, + DBG_CLIENT_BLKID_gdc_one_18 = 0x67, + DBG_CLIENT_BLKID_gdc_one_19 = 0x68, + DBG_CLIENT_BLKID_gdc_one_20 = 0x69, + DBG_CLIENT_BLKID_gdc_one_21 = 0x6a, + DBG_CLIENT_BLKID_gdc_one_22 = 0x6b, + DBG_CLIENT_BLKID_gdc_one_23 = 0x6c, + DBG_CLIENT_BLKID_gdc_one_24 = 0x6d, + DBG_CLIENT_BLKID_gdc_one_25 = 0x6e, + DBG_CLIENT_BLKID_gdc_one_26 = 0x6f, + DBG_CLIENT_BLKID_gdc_one_27 = 0x70, + DBG_CLIENT_BLKID_gdc_one_28 = 0x71, + DBG_CLIENT_BLKID_gdc_one_29 = 0x72, + DBG_CLIENT_BLKID_gdc_one_30 = 0x73, + DBG_CLIENT_BLKID_gdc_one_31 = 0x74, + DBG_CLIENT_BLKID_gdc_one_32 = 0x75, + DBG_CLIENT_BLKID_gdc_one_33 = 0x76, + DBG_CLIENT_BLKID_gdc_one_34 = 0x77, + DBG_CLIENT_BLKID_gdc_one_35 = 0x78, + DBG_CLIENT_BLKID_vceb0_0 = 0x79, + DBG_CLIENT_BLKID_vgt3 = 0x7a, + DBG_CLIENT_BLKID_pc3 = 0x7b, + DBG_CLIENT_BLKID_mcd3 = 0x7c, + DBG_CLIENT_BLKID_uvdu_0 = 0x7d, + DBG_CLIENT_BLKID_uvdu_1 = 0x7e, + DBG_CLIENT_BLKID_uvdu_2 = 0x7f, + DBG_CLIENT_BLKID_uvdu_3 = 0x80, + DBG_CLIENT_BLKID_uvdu_4 = 0x81, + DBG_CLIENT_BLKID_uvdu_5 = 0x82, + DBG_CLIENT_BLKID_uvdu_6 = 0x83, + DBG_CLIENT_BLKID_cb300 = 0x84, + DBG_CLIENT_BLKID_mcd1 = 0x85, + DBG_CLIENT_BLKID_sx00 = 0x86, + DBG_CLIENT_BLKID_uvdc_0 = 0x87, + DBG_CLIENT_BLKID_uvdc_1 = 0x88, + DBG_CLIENT_BLKID_mcc3 = 0x89, + DBG_CLIENT_BLKID_cpg_0 = 0x8a, + DBG_CLIENT_BLKID_cpg_1 = 0x8b, + DBG_CLIENT_BLKID_gck = 0x8c, + DBG_CLIENT_BLKID_mcc1 = 0x8d, + DBG_CLIENT_BLKID_cpf_0 = 0x8e, + DBG_CLIENT_BLKID_cpf_1 = 0x8f, + DBG_CLIENT_BLKID_rlc = 0x90, + DBG_CLIENT_BLKID_grbm = 0x91, + DBG_CLIENT_BLKID_sammsp = 0x92, + DBG_CLIENT_BLKID_dci_pg = 0x93, + DBG_CLIENT_BLKID_dci_0 = 0x94, + DBG_CLIENT_BLKID_dccg0_0 = 0x95, + DBG_CLIENT_BLKID_dccg0_1 = 0x96, + DBG_CLIENT_BLKID_dcfe01_0 = 0x97, + DBG_CLIENT_BLKID_dcfe02_0 = 0x98, + DBG_CLIENT_BLKID_dcfe03_0 = 0x99, + DBG_CLIENT_BLKID_dcfe04_0 = 0x9a, + DBG_CLIENT_BLKID_dcfe05_0 = 0x9b, + DBG_CLIENT_BLKID_dcfe06_0 = 0x9c, + DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* BIF_5_0_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h new file mode 100644 index 000000000000..adc71b01f793 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h @@ -0,0 +1,11494 @@ +/* + * BIF_5_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_5_0_SH_MASK_H +#define BIF_5_0_SH_MASK_H + +#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff +#define MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define MM_INDEX__MM_APER_MASK 0x80000000 +#define MM_INDEX__MM_APER__SHIFT 0x1f +#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff +#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define MM_DATA__MM_DATA_MASK 0xffffffff +#define MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2 +#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x1 +#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1 +#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0 +#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2 +#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1 +#define BUS_CNTL__PMI_IO_DIS_MASK 0x4 +#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8 +#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define BUS_CNTL__PMI_BM_DIS_MASK 0x10 +#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define BUS_CNTL__PMI_INT_DIS_MASK 0x20 +#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5 +#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40 +#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80 +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100 +#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8 +#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00 +#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BUS_CNTL__SET_MC_TC_MASK 0xe000 +#define BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000 +#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000 +#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000 +#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1 +#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define CONFIG_CNTL__VGA_DIS_MASK 0x2 +#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1 +#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4 +#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18 +#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff +#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xffffffff +#define CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x1 +#define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000 +#define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff +#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff +#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff +#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff +#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff +#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT_MASK 0x1 +#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT__SHIFT 0x0 +#define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT_MASK 0x100 +#define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT__SHIFT 0x8 +#define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x1 +#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x10000 +#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x1 +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x2 +#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x10000 +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x20000 +#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BX_RESET_EN__COR_RESET_EN_MASK 0x1 +#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 +#define BX_RESET_EN__REG_RESET_EN_MASK 0x2 +#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 +#define BX_RESET_EN__STY_RESET_EN_MASK 0x4 +#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 +#define BX_RESET_EN__FLR_TWICE_EN_MASK 0x100 +#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 +#define BX_RESET_EN__FLR_TIMER_SEL_MASK 0x600 +#define BX_RESET_EN__FLR_TIMER_SEL__SHIFT 0x9 +#define BX_RESET_EN__DB_APER_RESET_EN_MASK 0x8000 +#define BX_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x10000 +#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BX_RESET_EN__PF_FLR_NEWHDL_EN_MASK 0x20000 +#define BX_RESET_EN__PF_FLR_NEWHDL_EN__SHIFT 0x11 +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7 +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8 +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3 +#define HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000 +#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 +#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000 +#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 +#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000 +#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 +#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000 +#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 +#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000 +#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 +#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000 +#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 +#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000 +#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 +#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000 +#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 +#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 +#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 +#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 +#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 +#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 +#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a +#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 +#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b +#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 +#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c +#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 +#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d +#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 +#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e +#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 +#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f +#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f +#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0 +#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000 +#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10 +#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f +#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0 +#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0 +#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5 +#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00 +#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa +#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000 +#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf +#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000 +#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14 +#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000 +#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19 +#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1 +#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1 +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2 +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8 +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0 +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100 +#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00 +#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9 +#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000 +#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd +#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000 +#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1 +#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0 +#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2 +#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1 +#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4 +#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2 +#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8 +#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6 +#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80 +#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0 +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00 +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8 +#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff +#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0 +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1 +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1 +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x2000 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER_MASK 0xff000000 +#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18 +#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER_MASK 0xffffffff +#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0 +#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff +#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000 +#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff +#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1 +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2 +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4 +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8 +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10 +#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 +#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80 +#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7 +#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100 +#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8 +#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200 +#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 +#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400 +#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa +#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800 +#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb +#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000 +#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x2000 +#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x8000 +#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x10000 +#define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x10 +#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x20000 +#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 +#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x40000 +#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 +#define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN_MASK 0x80000 +#define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN__SHIFT 0x13 +#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS_MASK 0x100000 +#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS__SHIFT 0x14 +#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS_MASK 0x200000 +#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS__SHIFT 0x15 +#define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS_MASK 0x400000 +#define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS__SHIFT 0x16 +#define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS_MASK 0x800000 +#define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS__SHIFT 0x17 +#define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS_MASK 0x1000000 +#define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS__SHIFT 0x18 +#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1 +#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2 +#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4 +#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8 +#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x10 +#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x20 +#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5 +#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000 +#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x1000000 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x2000000 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x4000000 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x8000000 +#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3 +#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0 +#define BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK 0x1 +#define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0 +#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS_MASK 0x2 +#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1 +#define BIF_FB_EN__FB_READ_EN_MASK 0x1 +#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2 +#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff +#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define BIF_BUSNUM_LIST0__ID0_MASK 0xff +#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00 +#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000 +#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000 +#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define BIF_BUSNUM_LIST1__ID4_MASK 0xff +#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00 +#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000 +#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000 +#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000 +#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000 +#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 +#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1 +#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2 +#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00 +#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8 +#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000 +#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd +#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff +#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 +#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff +#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 +#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe +#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1 +#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1 +#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2 +#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4 +#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8 +#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10 +#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20 +#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40 +#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80 +#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100 +#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200 +#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400 +#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800 +#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1 +#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2 +#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4 +#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8 +#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10 +#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20 +#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40 +#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80 +#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100 +#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200 +#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400 +#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800 +#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1 +#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0 +#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2 +#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1 +#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4 +#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2 +#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8 +#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3 +#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10 +#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4 +#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20 +#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5 +#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80 +#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7 +#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100 +#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8 +#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200 +#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9 +#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1 +#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define HOST_BUSNUM__HOST_ID_MASK 0xffff +#define HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff +#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000 +#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff +#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000 +#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff +#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff +#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000 +#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff +#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff +#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000 +#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff +#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff +#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000 +#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff +#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff +#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000 +#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN_MASK 0x1 +#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN__SHIFT 0x0 +#define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0xffffffff +#define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0xffffffff +#define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define BACO_CNTL__BACO_EN_MASK 0x1 +#define BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2 +#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1 +#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4 +#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2 +#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8 +#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BACO_CNTL__BACO_RESET_EN_MASK 0x10 +#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4 +#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20 +#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5 +#define BACO_CNTL__BACO_MODE_MASK 0x40 +#define BACO_CNTL__BACO_MODE__SHIFT 0x6 +#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80 +#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7 +#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100 +#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8 +#define BACO_CNTL__PWRGOOD_BF_MASK 0x200 +#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9 +#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400 +#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa +#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800 +#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb +#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000 +#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc +#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000 +#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd +#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000 +#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10 +#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000 +#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11 +#define BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK 0x40000 +#define BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT 0x12 +#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1 +#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0 +#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2 +#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1 +#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1 +#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1 +#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0 +#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1 +#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0 +#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1 +#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2 +#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc +#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2 +#define BACO_CNTL_MISC__BACO_REFCLK_SEL_MASK 0x10 +#define BACO_CNTL_MISC__BACO_REFCLK_SEL__SHIFT 0x4 +#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x1 +#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x1 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x10 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x20 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 +#define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK 0x7fffc +#define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2 +#define BIF_SMU_DATA__BIF_SMU_DATA_MASK 0x7fffc +#define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000 +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f +#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000 +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f +#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 +#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1 +#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0 +#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1 +#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0 +#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2 +#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1 +#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4 +#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2 +#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8 +#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3 +#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10 +#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4 +#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20 +#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5 +#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40 +#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6 +#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80 +#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9 +#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400 +#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800 +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000 +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc +#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000 +#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd +#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000 +#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe +#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK 0x8000 +#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT 0xf +#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000 +#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10 +#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK 0x20000 +#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT 0x11 +#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK 0x40000 +#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT 0x12 +#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000 +#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e +#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000 +#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f +#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1 +#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1 +#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2 +#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1 +#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4 +#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2 +#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8 +#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3 +#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10 +#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4 +#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20 +#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5 +#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40 +#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6 +#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80 +#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7 +#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100 +#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8 +#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200 +#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9 +#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400 +#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa +#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800 +#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb +#define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK 0x1000 +#define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT 0xc +#define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK 0x2000 +#define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd +#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1 +#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2 +#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1 +#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4 +#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2 +#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8 +#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3 +#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10 +#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4 +#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20 +#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5 +#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40 +#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6 +#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80 +#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7 +#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100 +#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8 +#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200 +#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9 +#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400 +#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa +#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800 +#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb +#define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK 0x1000 +#define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT 0xc +#define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK 0x2000 +#define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd +#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x7fffc +#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x7fffc +#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_RB_CNTL__RB_ENABLE_MASK 0x1 +#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_RB_CNTL__RB_SIZE_MASK 0x3e +#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 +#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00 +#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x20000 +#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 +#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_RB_BASE__ADDR_MASK 0xffffffff +#define BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_RB_RPTR__OFFSET_MASK 0x3fffc +#define BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x1 +#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_RB_WPTR__OFFSET_MASK 0x3fffc +#define BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0xff +#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0xf +#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xffffffff +#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xffffffff +#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xffffffff +#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xffffffff +#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xffffffff +#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xffffffff +#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xffffffff +#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xffffffff +#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x1 +#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x2 +#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x100 +#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x200 +#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x1 +#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x2 +#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF_MASK 0xffff +#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF__SHIFT 0x0 +#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF_MASK 0x80000000 +#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF__SHIFT 0x1f +#define VM_INIT_STATUS__VM_INIT_STATUS_MASK 0x1 +#define VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0 +#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff +#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0 +#define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff +#define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0 +#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE_MASK 0xffff +#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED_MASK 0xffff0000 +#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff +#define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0 +#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff +#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0 +#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000 +#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10 +#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff +#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0 +#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000 +#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10 +#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff +#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0 +#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000 +#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10 +#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff +#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0 +#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000 +#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10 +#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff +#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0 +#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000 +#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10 +#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff +#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0 +#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000 +#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10 +#define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff +#define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0 +#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff +#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0 +#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000 +#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10 +#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff +#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0 +#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000 +#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10 +#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff +#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0 +#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000 +#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10 +#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff +#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0 +#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000 +#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10 +#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff +#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0 +#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000 +#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10 +#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff +#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0 +#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000 +#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10 +#define VENDOR_ID__VENDOR_ID_MASK 0xffff +#define VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define DEVICE_ID__DEVICE_ID_MASK 0xffff +#define DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define COMMAND__IO_ACCESS_EN_MASK 0x1 +#define COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define COMMAND__BUS_MASTER_EN_MASK 0x4 +#define COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define COMMAND__AD_STEPPING_MASK 0x80 +#define COMMAND__AD_STEPPING__SHIFT 0x7 +#define COMMAND__SERR_EN_MASK 0x100 +#define COMMAND__SERR_EN__SHIFT 0x8 +#define COMMAND__FAST_B2B_EN_MASK 0x200 +#define COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define COMMAND__INT_DIS_MASK 0x400 +#define COMMAND__INT_DIS__SHIFT 0xa +#define STATUS__INT_STATUS_MASK 0x8 +#define STATUS__INT_STATUS__SHIFT 0x3 +#define STATUS__CAP_LIST_MASK 0x10 +#define STATUS__CAP_LIST__SHIFT 0x4 +#define STATUS__PCI_66_EN_MASK 0x20 +#define STATUS__PCI_66_EN__SHIFT 0x5 +#define STATUS__FAST_BACK_CAPABLE_MASK 0x80 +#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100 +#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define STATUS__DEVSEL_TIMING_MASK 0x600 +#define STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800 +#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000 +#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000 +#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000 +#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000 +#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define REVISION_ID__MINOR_REV_ID_MASK 0xf +#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff +#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define SUB_CLASS__SUB_CLASS_MASK 0xff +#define SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BASE_CLASS__BASE_CLASS_MASK 0xff +#define BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define LATENCY__LATENCY_TIMER_MASK 0xff +#define LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define HEADER__HEADER_TYPE_MASK 0x7f +#define HEADER__HEADER_TYPE__SHIFT 0x0 +#define HEADER__DEVICE_TYPE_MASK 0x80 +#define HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIST__BIST_COMP_MASK 0xf +#define BIST__BIST_COMP__SHIFT 0x0 +#define BIST__BIST_STRT_MASK 0x40 +#define BIST__BIST_STRT__SHIFT 0x6 +#define BIST__BIST_CAP_MASK 0x80 +#define BIST__BIST_CAP__SHIFT 0x7 +#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff +#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CAP_PTR__CAP_PTR_MASK 0xff +#define CAP_PTR__CAP_PTR__SHIFT 0x0 +#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff +#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000 +#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define MIN_GRANT__MIN_GNT_MASK 0xff +#define MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define MAX_LATENCY__MAX_LAT_MASK 0xff +#define MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff +#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000 +#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000 +#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define PMI_CAP_LIST__CAP_ID_MASK 0xff +#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PMI_CAP__VERSION_MASK 0x7 +#define PMI_CAP__VERSION__SHIFT 0x0 +#define PMI_CAP__PME_CLOCK_MASK 0x8 +#define PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20 +#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define PMI_CAP__AUX_CURRENT_MASK 0x1c0 +#define PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define PMI_CAP__D1_SUPPORT_MASK 0x200 +#define PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define PMI_CAP__D2_SUPPORT_MASK 0x400 +#define PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define PMI_CAP__PME_SUPPORT_MASK 0xf800 +#define PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PCIE_CAP__VERSION_MASK 0xf +#define PCIE_CAP__VERSION__SHIFT 0x0 +#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0 +#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100 +#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00 +#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000 +#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define DEVICE_STATUS__CORR_ERR_MASK 0x1 +#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2 +#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define DEVICE_STATUS__FATAL_ERR_MASK 0x4 +#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define DEVICE_STATUS__USR_DETECTED_MASK 0x8 +#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define DEVICE_STATUS__AUX_PWR_MASK 0x10 +#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20 +#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define LINK_CAP__LINK_SPEED_MASK 0xf +#define LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define LINK_CNTL__PM_CONTROL_MASK 0x3 +#define LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define LINK_CNTL__LINK_DIS_MASK 0x10 +#define LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf +#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0 +#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define LINK_STATUS__LINK_TRAINING_MASK 0x800 +#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000 +#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define LINK_STATUS__DL_ACTIVE_MASK 0x2000 +#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000 +#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000 +#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 +#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 +#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 +#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 +#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 +#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 +#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define DEVICE_STATUS2__RESERVED_MASK 0xffff +#define DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define LINK_CAP2__RESERVED__SHIFT 0x9 +#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1 +#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2 +#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4 +#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8 +#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10 +#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20 +#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define MSI_CAP_LIST__CAP_ID_MASK 0xff +#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define MSI_MSG_CNTL__MSI_EN_MASK 0x1 +#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe +#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70 +#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80 +#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x100 +#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define MSI_MASK__MSI_MASK_MASK 0xffffffff +#define MSI_MASK__MSI_MASK__SHIFT 0x0 +#define MSI_PENDING__MSI_PENDING_MASK 0xffffffff +#define MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define MSI_MASK_64__MSI_MASK_64_MASK 0xffffffff +#define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define MSI_PENDING_64__MSI_PENDING_64_MASK 0xffffffff +#define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define MSIX_CAP_LIST__CAP_ID_MASK 0xff +#define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define MSIX_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x7ff +#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000 +#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000 +#define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x7 +#define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xfffffff8 +#define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define MSIX_PBA__MSIX_PBA_BIR_MASK 0x7 +#define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xfffffff8 +#define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1 +#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 +#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 +#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 +#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 +#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff +#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300 +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00 +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000 +#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000 +#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000 +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1 +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f +#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 +#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f +#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100 +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f +#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1 +#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2 +#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4 +#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8 +#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10 +#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20 +#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40 +#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f +#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20 +#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40 +#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define PCIE_ATS_CNTL__STU_MASK 0x1f +#define PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000 +#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1 +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2 +#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1 +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2 +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100 +#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000 +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2 +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4 +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00 +#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1 +#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2 +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4 +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1 +#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 +#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2 +#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 +#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4 +#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 +#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100 +#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 +#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00 +#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f +#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000 +#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x1 +#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x2 +#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xff00 +#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x1 +#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x2 +#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x70 +#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x1 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x2 +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xffe00000 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x1 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x2 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x4 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x8 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x10 +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x1 +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xffff +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xffff +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xffff +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xff +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xffff +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xffff +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xffff +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xffffffff +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xffffffff +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xffffffff +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xffffffff +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xffffffff +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xffffffff +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xffffffff +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xffffffff +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xffffffff +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0xf0000 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xfff00000 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0xf0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xfff00000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL_MASK 0xff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID_MASK 0xff00 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID_MASK 0xff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS_MASK 0xff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE_MASK 0x7f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x80 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET_MASK 0xfffc0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET_MASK 0xff00 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET_MASK 0xff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET_MASK 0xff000000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER_MASK 0xffff0000 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA__SHIFT 0x0 +#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff +#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff +#define PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff +#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0 +#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff +#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0 +#define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A_MASK 0x1 +#define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A__SHIFT 0x0 +#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1 +#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0 +#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2 +#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1 +#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4 +#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2 +#define LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8 +#define LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3 +#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10 +#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4 +#define CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff +#define CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0 +#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7 +#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0 +#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70 +#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4 +#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff +#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0 +#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000 +#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10 +#define LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff +#define LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0 +#define LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff +#define LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0 +#define LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff +#define LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0 +#define PCIE_EFUSE__PCIE_EFUSE_VALID_MASK 0x2 +#define PCIE_EFUSE__PCIE_EFUSE_VALID__SHIFT 0x1 +#define PCIE_EFUSE__PPHY_EFUSE_VALID_MASK 0x4 +#define PCIE_EFUSE__PPHY_EFUSE_VALID__SHIFT 0x2 +#define PCIE_EFUSE__SPARE_5_3_EFUSE0_MASK 0x38 +#define PCIE_EFUSE__SPARE_5_3_EFUSE0__SHIFT 0x3 +#define PCIE_EFUSE__ISTRAP_ARBEN0_MASK 0x40 +#define PCIE_EFUSE__ISTRAP_ARBEN0__SHIFT 0x6 +#define PCIE_EFUSE__SPARE_26_7_EFUSE0_MASK 0x7ffff80 +#define PCIE_EFUSE__SPARE_26_7_EFUSE0__SHIFT 0x7 +#define PCIE_EFUSE__CHIP_BIF_MODE_MASK 0x8000000 +#define PCIE_EFUSE__CHIP_BIF_MODE__SHIFT 0x1b +#define PCIE_EFUSE__SPARE_31_28_EFUSE0_MASK 0xf0000000 +#define PCIE_EFUSE__SPARE_31_28_EFUSE0__SHIFT 0x1c +#define PCIE_EFUSE2__SPARE_31_1_EFUSE2_MASK 0xfffffffe +#define PCIE_EFUSE2__SPARE_31_1_EFUSE2__SHIFT 0x1 +#define PCIE_EFUSE3__STRAP_CEC_ID_MASK 0x1fffe +#define PCIE_EFUSE3__STRAP_CEC_ID__SHIFT 0x1 +#define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3_MASK 0x20000 +#define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3__SHIFT 0x11 +#define PCIE_EFUSE3__SPARE_14_PCIEFUSE3_MASK 0xfffc0000 +#define PCIE_EFUSE3__SPARE_14_PCIEFUSE3__SHIFT 0x12 +#define PCIE_EFUSE4__CC_WRITE_DISABLE_MASK 0x1 +#define PCIE_EFUSE4__CC_WRITE_DISABLE__SHIFT 0x0 +#define PCIE_EFUSE4__SPARE_3_PCIEFUSE4_MASK 0xe +#define PCIE_EFUSE4__SPARE_3_PCIEFUSE4__SHIFT 0x1 +#define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID_MASK 0xffff0 +#define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID__SHIFT 0x4 +#define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID_MASK 0xf00000 +#define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID__SHIFT 0x14 +#define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID_MASK 0xf000000 +#define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID__SHIFT 0x18 +#define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK 0xf0000000 +#define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT 0x1c +#define PCIE_EFUSE5__STRAP_AZALIA_DID_MASK 0x1fffe +#define PCIE_EFUSE5__STRAP_AZALIA_DID__SHIFT 0x1 +#define PCIE_EFUSE5__SPARE_16_PCIEFUSE5_MASK 0xfffe0000 +#define PCIE_EFUSE5__SPARE_16_PCIEFUSE5__SHIFT 0x11 +#define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES_MASK 0x1fffe +#define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES__SHIFT 0x1 +#define PCIE_EFUSE6__SPARE_15_PCIEFUSE6_MASK 0xfffe0000 +#define PCIE_EFUSE6__SPARE_15_PCIEFUSE6__SHIFT 0x11 +#define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID_MASK 0x1fffe +#define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID__SHIFT 0x1 +#define PCIE_EFUSE7__SPARE_15_PCIEFUSE7_MASK 0xfffe0000 +#define PCIE_EFUSE7__SPARE_15_PCIEFUSE7__SHIFT 0x11 +#define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff +#define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0 +#define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff +#define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0 +#define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1 +#define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0 +#define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1 +#define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0 +#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1 +#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0 +#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2 +#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1 +#define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY_MASK 0x2 +#define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY__SHIFT 0x1 +#define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4 +#define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2 +#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7 +#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0 +#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70 +#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4 +#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80 +#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7 +#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100 +#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8 +#define PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xffff +#define PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0 +#define PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000 +#define PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10 +#define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1 +#define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0 +#define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1 +#define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0 +#define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1 +#define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0 +#define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1 +#define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0 +#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff +#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff +#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff +#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 +#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1 +#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 +#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80 +#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100 +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200 +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00 +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000 +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf +#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000 +#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000 +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000 +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000 +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 +#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000 +#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14 +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000 +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000 +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000 +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 +#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000 +#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 +#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000 +#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000 +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000 +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000 +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff +#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 +#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100 +#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 +#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000 +#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 +#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1 +#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2 +#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4 +#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8 +#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10 +#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40 +#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80 +#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7 +#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100 +#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8 +#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1 +#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2 +#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4 +#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8 +#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10 +#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40 +#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80 +#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7 +#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100 +#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8 +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1 +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 +#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0 +#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 +#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800 +#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb +#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000 +#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc +#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000 +#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd +#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000 +#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe +#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 +#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 +#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000 +#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 +#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000 +#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 +#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000 +#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 +#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000 +#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 +#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000 +#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000 +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 +#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000 +#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d +#define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000 +#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e +#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000 +#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 +#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000 +#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc +#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000 +#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd +#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000 +#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 +#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000 +#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4 +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8 +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10 +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0 +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100 +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200 +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc +#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000 +#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd +#define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH_MASK 0x70000 +#define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH__SHIFT 0x10 +#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40 +#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80 +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000 +#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc +#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f +#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 +#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00 +#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 +#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000 +#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 +#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000 +#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 +#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f +#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 +#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00 +#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 +#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000 +#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 +#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000 +#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 +#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f +#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 +#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00 +#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 +#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000 +#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 +#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000 +#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 +#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f +#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 +#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00 +#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 +#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000 +#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 +#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000 +#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 +#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f +#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 +#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00 +#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 +#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000 +#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 +#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000 +#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 +#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f +#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 +#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00 +#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 +#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000 +#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 +#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000 +#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2 +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0 +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000 +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1 +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8 +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10 +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20 +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40 +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 +#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff +#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1 +#define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0 +#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1 +#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 +#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2 +#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 +#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4 +#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2 +#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8 +#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3 +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10 +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20 +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40 +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80 +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100 +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 +#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000 +#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000 +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000 +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe +#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000 +#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000 +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000 +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 +#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1 +#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1 +#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4 +#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2 +#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8 +#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc +#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000 +#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10 +#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000 +#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11 +#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000 +#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12 +#define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0_MASK 0x80000 +#define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13 +#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000 +#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x10000 +#define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS_MASK 0x1 +#define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS__SHIFT 0x0 +#define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS_MASK 0x2 +#define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS__SHIFT 0x1 +#define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS_MASK 0x4 +#define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS__SHIFT 0x2 +#define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE_MASK 0x8 +#define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE__SHIFT 0x3 +#define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE_MASK 0x10 +#define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE__SHIFT 0x4 +#define PCIE_IDLE_STATUS__TX_PBUF_IDLE_MASK 0x20 +#define PCIE_IDLE_STATUS__TX_PBUF_IDLE__SHIFT 0x5 +#define PCIE_IDLE_STATUS__TX_NPBUF_IDLE_MASK 0x40 +#define PCIE_IDLE_STATUS__TX_NPBUF_IDLE__SHIFT 0x6 +#define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE_MASK 0x80 +#define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE__SHIFT 0x7 +#define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE_MASK 0x100 +#define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE__SHIFT 0x8 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 +#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1 +#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2 +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4 +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 +#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8 +#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10 +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 +#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20 +#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40 +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80 +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100 +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200 +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400 +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800 +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000 +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc +#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000 +#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd +#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000 +#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe +#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000 +#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000 +#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000 +#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000 +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12 +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000 +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13 +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000 +#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14 +#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000 +#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000 +#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18 +#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 +#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b +#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000 +#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c +#define PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000 +#define PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d +#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000 +#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e +#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2 +#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4 +#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2 +#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8 +#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3 +#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10 +#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4 +#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20 +#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5 +#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40 +#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6 +#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80 +#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7 +#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100 +#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8 +#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200 +#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9 +#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400 +#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa +#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800 +#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb +#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000 +#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc +#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000 +#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd +#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000 +#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe +#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000 +#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000 +#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN_MASK 0x40000 +#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN__SHIFT 0x12 +#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN_MASK 0x80000 +#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN__SHIFT 0x13 +#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN_MASK 0x100000 +#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN__SHIFT 0x14 +#define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP_MASK 0xe00000 +#define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP__SHIFT 0x15 +#define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 +#define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b +#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2 +#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4 +#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2 +#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8 +#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3 +#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10 +#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4 +#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20 +#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5 +#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40 +#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6 +#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80 +#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7 +#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100 +#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8 +#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200 +#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9 +#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400 +#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa +#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800 +#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb +#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000 +#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc +#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000 +#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd +#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000 +#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe +#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000 +#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000 +#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN_MASK 0x40000 +#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN__SHIFT 0x12 +#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN_MASK 0x80000 +#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN__SHIFT 0x13 +#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN_MASK 0x100000 +#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN__SHIFT 0x14 +#define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP_MASK 0xe00000 +#define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP__SHIFT 0x15 +#define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 +#define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b +#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN_MASK 0x1 +#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN__SHIFT 0x0 +#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR_MASK 0xe +#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR__SHIFT 0x1 +#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET_MASK 0xfffff000 +#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET__SHIFT 0xc +#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10 +#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 +#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00 +#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8 +#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000 +#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd +#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000 +#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe +#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000 +#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000 +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000 +#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19 +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000 +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000 +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000 +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000 +#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e +#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000 +#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2 +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4 +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8 +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 +#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10 +#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1 +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 +#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80 +#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 +#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff +#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 +#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000 +#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 +#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000 +#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 +#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000 +#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 +#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff +#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 +#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1 +#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 +#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe +#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10 +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4 +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20 +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5 +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0 +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6 +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00 +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8 +#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000 +#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000 +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 +#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 +#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 +#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff +#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f +#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x100 +#define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1 +#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0 +#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2 +#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1 +#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000 +#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10 +#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000 +#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11 +#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1 +#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0 +#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2 +#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1 +#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c +#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2 +#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100 +#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8 +#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200 +#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9 +#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400 +#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa +#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000 +#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc +#define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000 +#define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd +#define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000 +#define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe +#define SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000 +#define SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10 +#define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000 +#define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11 +#define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN_MASK 0x10000000 +#define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN__SHIFT 0x1c +#define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR_MASK 0x60000000 +#define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR__SHIFT 0x1d +#define SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000 +#define SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf +#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000 +#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10 +#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000 +#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11 +#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000 +#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12 +#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000 +#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13 +#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000 +#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14 +#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000 +#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15 +#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000 +#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16 +#define SWRST_COMMAND_1__SWITCHCLK_MASK 0x1 +#define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0 +#define SWRST_COMMAND_1__RESETPCFG_MASK 0x2 +#define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1 +#define SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4 +#define SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2 +#define SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8 +#define SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3 +#define SWRST_COMMAND_1__RESETSRBM0_MASK 0x10 +#define SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4 +#define SWRST_COMMAND_1__RESETSRBM1_MASK 0x20 +#define SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5 +#define SWRST_COMMAND_1__RESETLC_MASK 0x40 +#define SWRST_COMMAND_1__RESETLC__SHIFT 0x6 +#define SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100 +#define SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8 +#define SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200 +#define SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9 +#define SWRST_COMMAND_1__RESETMNTR_MASK 0x2000 +#define SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd +#define SWRST_COMMAND_1__RESETHLTR_MASK 0x4000 +#define SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe +#define SWRST_COMMAND_1__RESETCPM_MASK 0x8000 +#define SWRST_COMMAND_1__RESETCPM__SHIFT 0xf +#define SWRST_COMMAND_1__RESETPIF0_MASK 0x10000 +#define SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10 +#define SWRST_COMMAND_1__RESETPIF1_MASK 0x20000 +#define SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11 +#define SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000 +#define SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14 +#define SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000 +#define SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15 +#define SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000 +#define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18 +#define SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000 +#define SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19 +#define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000 +#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c +#define SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000 +#define SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d +#define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000 +#define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf +#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000 +#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10 +#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000 +#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11 +#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000 +#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12 +#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000 +#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13 +#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000 +#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14 +#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000 +#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15 +#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000 +#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16 +#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1 +#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0 +#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2 +#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1 +#define SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4 +#define SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2 +#define SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8 +#define SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3 +#define SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10 +#define SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4 +#define SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20 +#define SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5 +#define SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40 +#define SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6 +#define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100 +#define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8 +#define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200 +#define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9 +#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000 +#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd +#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000 +#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe +#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000 +#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf +#define SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000 +#define SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10 +#define SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000 +#define SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11 +#define SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000 +#define SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14 +#define SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000 +#define SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15 +#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000 +#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18 +#define SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000 +#define SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19 +#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000 +#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c +#define SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000 +#define SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d +#define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000 +#define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf +#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000 +#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10 +#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000 +#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11 +#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000 +#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12 +#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000 +#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13 +#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000 +#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14 +#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000 +#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15 +#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000 +#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16 +#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1 +#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0 +#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2 +#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1 +#define SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4 +#define SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2 +#define SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8 +#define SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3 +#define SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10 +#define SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4 +#define SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20 +#define SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5 +#define SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40 +#define SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6 +#define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100 +#define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8 +#define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200 +#define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9 +#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000 +#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd +#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000 +#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe +#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000 +#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf +#define SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000 +#define SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10 +#define SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000 +#define SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11 +#define SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000 +#define SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14 +#define SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000 +#define SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15 +#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000 +#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18 +#define SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000 +#define SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19 +#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000 +#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c +#define SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000 +#define SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d +#define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000 +#define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe +#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000 +#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10 +#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000 +#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11 +#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000 +#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12 +#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000 +#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13 +#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000 +#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14 +#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000 +#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15 +#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000 +#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16 +#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1 +#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0 +#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2 +#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1 +#define SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4 +#define SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2 +#define SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8 +#define SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3 +#define SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10 +#define SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4 +#define SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20 +#define SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5 +#define SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40 +#define SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6 +#define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100 +#define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8 +#define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200 +#define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9 +#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000 +#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd +#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000 +#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe +#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000 +#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf +#define SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000 +#define SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10 +#define SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000 +#define SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11 +#define SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000 +#define SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14 +#define SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000 +#define SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15 +#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000 +#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18 +#define SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000 +#define SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19 +#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000 +#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c +#define SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000 +#define SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d +#define SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1 +#define SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0 +#define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100 +#define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8 +#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x1 +#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0 +#define SWRST_EP_COMMAND_0__EP_SOFT_RESET_MASK 0x2 +#define SWRST_EP_COMMAND_0__EP_SOFT_RESET__SHIFT 0x1 +#define SWRST_EP_COMMAND_0__EP_DRV_RESET_MASK 0x4 +#define SWRST_EP_COMMAND_0__EP_DRV_RESET__SHIFT 0x2 +#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x100 +#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8 +#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x200 +#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9 +#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x400 +#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa +#define SWRST_EP_COMMAND_0__EP_FLR0_RESET_MASK 0x10000 +#define SWRST_EP_COMMAND_0__EP_FLR0_RESET__SHIFT 0x10 +#define SWRST_EP_COMMAND_0__EP_FLR1_RESET_MASK 0x20000 +#define SWRST_EP_COMMAND_0__EP_FLR1_RESET__SHIFT 0x11 +#define SWRST_EP_COMMAND_0__EP_FLR2_RESET_MASK 0x40000 +#define SWRST_EP_COMMAND_0__EP_FLR2_RESET__SHIFT 0x12 +#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x1 +#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0 +#define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN_MASK 0x2 +#define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN__SHIFT 0x1 +#define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN_MASK 0x4 +#define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN__SHIFT 0x2 +#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x100 +#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8 +#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x200 +#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9 +#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x400 +#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa +#define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN_MASK 0x10000 +#define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN__SHIFT 0x10 +#define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN_MASK 0x20000 +#define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN__SHIFT 0x11 +#define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN_MASK 0x40000 +#define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN__SHIFT 0x12 +#define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN_MASK 0x80000 +#define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN__SHIFT 0x13 +#define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST_MASK 0xf00000 +#define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST__SHIFT 0x14 +#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1 +#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0 +#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2 +#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1 +#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4 +#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2 +#define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8 +#define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3 +#define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10 +#define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4 +#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20 +#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5 +#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40 +#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6 +#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80 +#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7 +#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100 +#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8 +#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200 +#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9 +#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400 +#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa +#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800 +#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb +#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000 +#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc +#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000 +#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd +#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000 +#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe +#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000 +#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf +#define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000 +#define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10 +#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000 +#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11 +#define CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000 +#define CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14 +#define CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000 +#define CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15 +#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000 +#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16 +#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000 +#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17 +#define CPM_CONTROL__SPARE_REGS_MASK 0xff000000 +#define CPM_CONTROL__SPARE_REGS__SHIFT 0x18 +#define GSKT_CONTROL__GSKT_TxFifoBypass_MASK 0x1 +#define GSKT_CONTROL__GSKT_TxFifoBypass__SHIFT 0x0 +#define GSKT_CONTROL__GSKT_TxFifoDelay_MASK 0x2 +#define GSKT_CONTROL__GSKT_TxFifoDelay__SHIFT 0x1 +#define GSKT_CONTROL__GSKT_TxFifoDelay2_MASK 0x4 +#define GSKT_CONTROL__GSKT_TxFifoDelay2__SHIFT 0x2 +#define GSKT_CONTROL__GSKT_SpareRegs_MASK 0xf8 +#define GSKT_CONTROL__GSKT_SpareRegs__SHIFT 0x3 +#define LM_CONTROL__LoopbackSelect_MASK 0x1e +#define LM_CONTROL__LoopbackSelect__SHIFT 0x1 +#define LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20 +#define LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5 +#define LM_CONTROL__LoopbackHalfRate_MASK 0xc0 +#define LM_CONTROL__LoopbackHalfRate__SHIFT 0x6 +#define LM_CONTROL__LoopbackFifoPtr_MASK 0x700 +#define LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8 +#define LM_PCIETXMUX0__TXLANE0_MASK 0xff +#define LM_PCIETXMUX0__TXLANE0__SHIFT 0x0 +#define LM_PCIETXMUX0__TXLANE1_MASK 0xff00 +#define LM_PCIETXMUX0__TXLANE1__SHIFT 0x8 +#define LM_PCIETXMUX0__TXLANE2_MASK 0xff0000 +#define LM_PCIETXMUX0__TXLANE2__SHIFT 0x10 +#define LM_PCIETXMUX0__TXLANE3_MASK 0xff000000 +#define LM_PCIETXMUX0__TXLANE3__SHIFT 0x18 +#define LM_PCIETXMUX1__TXLANE4_MASK 0xff +#define LM_PCIETXMUX1__TXLANE4__SHIFT 0x0 +#define LM_PCIETXMUX1__TXLANE5_MASK 0xff00 +#define LM_PCIETXMUX1__TXLANE5__SHIFT 0x8 +#define LM_PCIETXMUX1__TXLANE6_MASK 0xff0000 +#define LM_PCIETXMUX1__TXLANE6__SHIFT 0x10 +#define LM_PCIETXMUX1__TXLANE7_MASK 0xff000000 +#define LM_PCIETXMUX1__TXLANE7__SHIFT 0x18 +#define LM_PCIETXMUX2__TXLANE8_MASK 0xff +#define LM_PCIETXMUX2__TXLANE8__SHIFT 0x0 +#define LM_PCIETXMUX2__TXLANE9_MASK 0xff00 +#define LM_PCIETXMUX2__TXLANE9__SHIFT 0x8 +#define LM_PCIETXMUX2__TXLANE10_MASK 0xff0000 +#define LM_PCIETXMUX2__TXLANE10__SHIFT 0x10 +#define LM_PCIETXMUX2__TXLANE11_MASK 0xff000000 +#define LM_PCIETXMUX2__TXLANE11__SHIFT 0x18 +#define LM_PCIETXMUX3__TXLANE12_MASK 0xff +#define LM_PCIETXMUX3__TXLANE12__SHIFT 0x0 +#define LM_PCIETXMUX3__TXLANE13_MASK 0xff00 +#define LM_PCIETXMUX3__TXLANE13__SHIFT 0x8 +#define LM_PCIETXMUX3__TXLANE14_MASK 0xff0000 +#define LM_PCIETXMUX3__TXLANE14__SHIFT 0x10 +#define LM_PCIETXMUX3__TXLANE15_MASK 0xff000000 +#define LM_PCIETXMUX3__TXLANE15__SHIFT 0x18 +#define LM_PCIERXMUX0__RXLANE0_MASK 0xff +#define LM_PCIERXMUX0__RXLANE0__SHIFT 0x0 +#define LM_PCIERXMUX0__RXLANE1_MASK 0xff00 +#define LM_PCIERXMUX0__RXLANE1__SHIFT 0x8 +#define LM_PCIERXMUX0__RXLANE2_MASK 0xff0000 +#define LM_PCIERXMUX0__RXLANE2__SHIFT 0x10 +#define LM_PCIERXMUX0__RXLANE3_MASK 0xff000000 +#define LM_PCIERXMUX0__RXLANE3__SHIFT 0x18 +#define LM_PCIERXMUX1__RXLANE4_MASK 0xff +#define LM_PCIERXMUX1__RXLANE4__SHIFT 0x0 +#define LM_PCIERXMUX1__RXLANE5_MASK 0xff00 +#define LM_PCIERXMUX1__RXLANE5__SHIFT 0x8 +#define LM_PCIERXMUX1__RXLANE6_MASK 0xff0000 +#define LM_PCIERXMUX1__RXLANE6__SHIFT 0x10 +#define LM_PCIERXMUX1__RXLANE7_MASK 0xff000000 +#define LM_PCIERXMUX1__RXLANE7__SHIFT 0x18 +#define LM_PCIERXMUX2__RXLANE8_MASK 0xff +#define LM_PCIERXMUX2__RXLANE8__SHIFT 0x0 +#define LM_PCIERXMUX2__RXLANE9_MASK 0xff00 +#define LM_PCIERXMUX2__RXLANE9__SHIFT 0x8 +#define LM_PCIERXMUX2__RXLANE10_MASK 0xff0000 +#define LM_PCIERXMUX2__RXLANE10__SHIFT 0x10 +#define LM_PCIERXMUX2__RXLANE11_MASK 0xff000000 +#define LM_PCIERXMUX2__RXLANE11__SHIFT 0x18 +#define LM_PCIERXMUX3__RXLANE12_MASK 0xff +#define LM_PCIERXMUX3__RXLANE12__SHIFT 0x0 +#define LM_PCIERXMUX3__RXLANE13_MASK 0xff00 +#define LM_PCIERXMUX3__RXLANE13__SHIFT 0x8 +#define LM_PCIERXMUX3__RXLANE14_MASK 0xff0000 +#define LM_PCIERXMUX3__RXLANE14__SHIFT 0x10 +#define LM_PCIERXMUX3__RXLANE15_MASK 0xff000000 +#define LM_PCIERXMUX3__RXLANE15__SHIFT 0x18 +#define LM_LANEENABLE__LANE_enable_MASK 0xffff +#define LM_LANEENABLE__LANE_enable__SHIFT 0x0 +#define LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff +#define LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0 +#define LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000 +#define LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c +#define LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000 +#define LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d +#define LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000 +#define LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e +#define LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000 +#define LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f +#define LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7 +#define LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0 +#define LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38 +#define LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3 +#define LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0 +#define LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6 +#define LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700 +#define LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8 +#define LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800 +#define LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb +#define LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000 +#define LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe +#define LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000 +#define LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10 +#define LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000 +#define LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13 +#define LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000 +#define LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16 +#define LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000 +#define LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18 +#define LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000 +#define LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b +#define LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000 +#define LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e +#define LM_POWERCONTROL1__LMTxEn0_MASK 0x1 +#define LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0 +#define LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2 +#define LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1 +#define LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c +#define LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2 +#define LM_POWERCONTROL1__LMSkipBit0_MASK 0x20 +#define LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5 +#define LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40 +#define LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6 +#define LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80 +#define LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7 +#define LM_POWERCONTROL1__LMDeemph0_MASK 0x100 +#define LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8 +#define LM_POWERCONTROL1__LMTxEn1_MASK 0x200 +#define LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9 +#define LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400 +#define LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa +#define LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800 +#define LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb +#define LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000 +#define LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe +#define LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000 +#define LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf +#define LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000 +#define LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10 +#define LM_POWERCONTROL1__LMDeemph1_MASK 0x20000 +#define LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11 +#define LM_POWERCONTROL1__LMTxEn2_MASK 0x40000 +#define LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12 +#define LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000 +#define LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13 +#define LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000 +#define LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14 +#define LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000 +#define LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17 +#define LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000 +#define LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18 +#define LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000 +#define LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19 +#define LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000 +#define LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a +#define LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000 +#define LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b +#define LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000 +#define LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d +#define LM_POWERCONTROL2__LMTxEn3_MASK 0x1 +#define LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0 +#define LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2 +#define LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1 +#define LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c +#define LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2 +#define LM_POWERCONTROL2__LMSkipBit3_MASK 0x20 +#define LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5 +#define LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40 +#define LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6 +#define LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80 +#define LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7 +#define LM_POWERCONTROL2__LMDeemph3_MASK 0x100 +#define LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8 +#define LM_POWERCONTROL2__TxCoeffID2_MASK 0x600 +#define LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9 +#define LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800 +#define LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb +#define LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000 +#define LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd +#define LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000 +#define LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13 +#define LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000 +#define LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19 +#define LM_POWERCONTROL3__TxCoeff3_MASK 0x3f +#define LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0 +#define LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0 +#define LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6 +#define LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000 +#define LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc +#define LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000 +#define LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12 +#define LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000 +#define LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18 +#define LM_POWERCONTROL4__LinkNum0_MASK 0x7 +#define LM_POWERCONTROL4__LinkNum0__SHIFT 0x0 +#define LM_POWERCONTROL4__LinkNum1_MASK 0x38 +#define LM_POWERCONTROL4__LinkNum1__SHIFT 0x3 +#define LM_POWERCONTROL4__LinkNum2_MASK 0x1c0 +#define LM_POWERCONTROL4__LinkNum2__SHIFT 0x6 +#define LM_POWERCONTROL4__LinkNum3_MASK 0xe00 +#define LM_POWERCONTROL4__LinkNum3__SHIFT 0x9 +#define LM_POWERCONTROL4__LaneNum0_MASK 0xf000 +#define LM_POWERCONTROL4__LaneNum0__SHIFT 0xc +#define LM_POWERCONTROL4__LaneNum1_MASK 0xf0000 +#define LM_POWERCONTROL4__LaneNum1__SHIFT 0x10 +#define LM_POWERCONTROL4__LaneNum2_MASK 0xf00000 +#define LM_POWERCONTROL4__LaneNum2__SHIFT 0x14 +#define LM_POWERCONTROL4__LaneNum3_MASK 0xf000000 +#define LM_POWERCONTROL4__LaneNum3__SHIFT 0x18 +#define LM_POWERCONTROL4__SpcMode0_MASK 0x10000000 +#define LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c +#define LM_POWERCONTROL4__SpcMode1_MASK 0x20000000 +#define LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d +#define LM_POWERCONTROL4__SpcMode2_MASK 0x40000000 +#define LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e +#define LM_POWERCONTROL4__SpcMode3_MASK 0x80000000 +#define LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f +#define PB0_GLB_CTRL_REG0__BACKUP_MASK 0xffff +#define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x0 +#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000 +#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10 +#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000 +#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14 +#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000 +#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17 +#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000 +#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18 +#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000 +#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19 +#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000 +#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a +#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000 +#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00 +#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8 +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000 +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000 +#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000 +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16 +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000 +#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17 +#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000 +#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e +#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000 +#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1 +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0 +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe +#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00 +#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000 +#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000 +#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19 +#define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f +#define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180 +#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7 +#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600 +#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9 +#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800 +#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb +#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000 +#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc +#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000 +#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe +#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000 +#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12 +#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000 +#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15 +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000 +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16 +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000 +#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17 +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000 +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000 +#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c +#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000 +#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000 +#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12 +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000 +#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16 +#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000 +#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a +#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000 +#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b +#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000 +#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c +#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff +#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK 0x8 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT 0x3 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000 +#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc +#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000 +#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000 +#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf +#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK 0x30000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12 +#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK 0x300000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT 0x14 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16 +#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK 0x3000000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT 0x18 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a +#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK 0x30000000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT 0x1c +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000 +#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf +#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK 0x30000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12 +#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK 0x300000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT 0x14 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16 +#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK 0x3000000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT 0x18 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a +#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK 0x30000000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT 0x1c +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000 +#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf +#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK 0x30000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12 +#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK 0x300000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT 0x14 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16 +#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK 0x3000000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT 0x18 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a +#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK 0x30000000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT 0x1c +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000 +#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT 0x0 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT 0x1 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK 0x4 +#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf +#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK 0x30000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT 0x10 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12 +#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK 0x300000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT 0x14 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16 +#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK 0x3000000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT 0x18 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a +#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK 0x30000000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT 0x1c +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000 +#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e +#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff +#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0 +#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000 +#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10 +#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1 +#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0 +#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2 +#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8 +#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3 +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000 +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000 +#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2 +#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1 +#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK 0x4 +#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2 +#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK 0x8 +#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT 0x3 +#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK 0x10 +#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT 0x4 +#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK 0x20 +#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT 0x5 +#define PB0_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PB0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PB0_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PB0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PB0_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PB0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PB0_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PB0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PB0_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PB0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PB0_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PB0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PB0_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PB0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PB0_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PB0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PB0_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PB0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PB0_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PB0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PB0_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PB0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PB0_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PB0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PB0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PB0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PB0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PB0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PB0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PB0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PB0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PB0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PB0_HW_DEBUG__HW_16_DEBUG_MASK 0x10000 +#define PB0_HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 +#define PB0_HW_DEBUG__HW_17_DEBUG_MASK 0x20000 +#define PB0_HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 +#define PB0_HW_DEBUG__HW_18_DEBUG_MASK 0x40000 +#define PB0_HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 +#define PB0_HW_DEBUG__HW_19_DEBUG_MASK 0x80000 +#define PB0_HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 +#define PB0_HW_DEBUG__HW_20_DEBUG_MASK 0x100000 +#define PB0_HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 +#define PB0_HW_DEBUG__HW_21_DEBUG_MASK 0x200000 +#define PB0_HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 +#define PB0_HW_DEBUG__HW_22_DEBUG_MASK 0x400000 +#define PB0_HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 +#define PB0_HW_DEBUG__HW_23_DEBUG_MASK 0x800000 +#define PB0_HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 +#define PB0_HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 +#define PB0_HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 +#define PB0_HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 +#define PB0_HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 +#define PB0_HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 +#define PB0_HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a +#define PB0_HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 +#define PB0_HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b +#define PB0_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 +#define PB0_HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c +#define PB0_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 +#define PB0_HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d +#define PB0_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 +#define PB0_HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e +#define PB0_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 +#define PB0_HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f +#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2 +#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1 +#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4 +#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2 +#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8 +#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3 +#define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK 0x10 +#define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT 0x4 +#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60 +#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5 +#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80 +#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7 +#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000 +#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc +#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000 +#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd +#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000 +#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf +#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000 +#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000 +#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c +#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000 +#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000 +#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5 +#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40 +#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7 +#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300 +#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8 +#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00 +#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18 +#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000 +#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000 +#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1 +#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c +#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2 +#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60 +#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000 +#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4 +#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000 +#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000 +#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18 +#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2 +#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1 +#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4 +#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2 +#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK 0x6 +#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT 0x1 +#define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK 0x18 +#define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT 0x3 +#define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK 0x60 +#define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT 0x5 +#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK 0x80 +#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT 0x7 +#define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK 0x300 +#define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT 0x8 +#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK 0x400 +#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT 0xa +#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK 0x1800 +#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT 0xb +#define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK 0x1c +#define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2 +#define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK 0x60 +#define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT 0x5 +#define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK 0x180 +#define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT 0x7 +#define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK 0x600 +#define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT 0x9 +#define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK 0x1800 +#define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT 0xb +#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK 0x10000000 +#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT 0x1c +#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK 0x20000000 +#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT 0x1d +#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK 0xc0000000 +#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT 0x1e +#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f +#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0 +#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80 +#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7 +#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00 +#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8 +#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000 +#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14 +#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000 +#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15 +#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000 +#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16 +#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000 +#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17 +#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000 +#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18 +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0 +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100 +#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8 +#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000 +#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10 +#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000 +#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11 +#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000 +#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14 +#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff +#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0 +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1 +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0 +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e +#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1 +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0 +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00 +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8 +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000 +#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK 0x8000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT 0xf +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK 0x10000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x10 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK 0x20000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT 0x11 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK 0x40000 +#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x12 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0 +#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4 +#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800 +#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000 +#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000 +#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK 0x300 +#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT 0x8 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK 0x300 +#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT 0x8 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK 0x300 +#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT 0x8 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK 0x300 +#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT 0x8 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8 +#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3 +#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10 +#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000 +#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200 +#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000 +#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70 +#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70 +#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70 +#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70 +#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000 +#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000 +#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d +#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000 +#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000 +#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000 +#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2 +#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK 0x18 +#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT 0x3 +#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK 0x60 +#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT 0x5 +#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK 0x180 +#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT 0x7 +#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK 0xe00 +#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT 0x9 +#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK 0x3000 +#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT 0xc +#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK 0xc000 +#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT 0xe +#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK 0x30000 +#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT 0x10 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000 +#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000 +#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000 +#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d +#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000 +#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000 +#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000 +#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a +#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000 +#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b +#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000 +#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK 0x20000000 +#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT 0x1d +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8 +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000 +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000 +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK 0x4000 +#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT 0xe +#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK 0x10000 +#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT 0x10 +#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK 0x20000 +#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT 0x11 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000 +#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d +#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3 +#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0 +#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc +#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2 +#define PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK 0x10 +#define PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT 0x4 +#define PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK 0x20 +#define PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT 0x5 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK 0x1 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT 0x0 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT 0x1 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK 0x4 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK 0x8 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT 0x3 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK 0x10 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT 0x4 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK 0x20 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT 0x5 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK 0x40 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT 0x6 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK 0x80 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT 0x7 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK 0x100 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT 0x8 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK 0x200 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT 0x9 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK 0x400 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT 0xa +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK 0x800 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT 0xb +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK 0x1000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT 0xc +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK 0x2000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT 0xd +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK 0x4000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT 0xe +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK 0x8000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT 0xf +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK 0x10000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT 0x10 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK 0x20000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT 0x11 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK 0x40000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT 0x12 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK 0x80000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT 0x13 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK 0x100000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT 0x14 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK 0x200000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT 0x15 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK 0x400000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT 0x16 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK 0x800000 +#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT 0x17 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000 +#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000 +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000 +#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10 +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000 +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11 +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000 +#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000 +#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000 +#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16 +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000 +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000 +#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000 +#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1 +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0 +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2 +#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1 +#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff +#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0 +#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00 +#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa +#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000 +#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc +#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000 +#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd +#define PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK 0x4000 +#define PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT 0xe +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK 0x40 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT 0x6 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK 0x3fc00 +#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT 0xa +#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff +#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0 +#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00 +#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa +#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000 +#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc +#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000 +#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd +#define PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK 0x4000 +#define PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT 0xe +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK 0x40 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT 0x6 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK 0x3fc00 +#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT 0xa +#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff +#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0 +#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00 +#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa +#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000 +#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc +#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000 +#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd +#define PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK 0x4000 +#define PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT 0xe +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK 0x40 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT 0x6 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK 0x3fc00 +#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT 0xa +#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff +#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0 +#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00 +#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa +#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000 +#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc +#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000 +#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd +#define PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK 0x4000 +#define PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT 0xe +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK 0x40 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT 0x6 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK 0x3fc00 +#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT 0xa +#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff +#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0 +#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00 +#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa +#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000 +#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc +#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000 +#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd +#define PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK 0x4000 +#define PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT 0xe +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK 0x40 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT 0x6 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK 0x3fc00 +#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT 0xa +#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff +#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0 +#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00 +#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa +#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000 +#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc +#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 +#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd +#define PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK 0x4000 +#define PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT 0xe +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK 0x40 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT 0x6 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK 0x3fc00 +#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT 0xa +#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff +#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0 +#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00 +#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa +#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000 +#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc +#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000 +#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd +#define PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK 0x4000 +#define PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT 0xe +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK 0x40 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT 0x6 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK 0x3fc00 +#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT 0xa +#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff +#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0 +#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00 +#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa +#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000 +#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc +#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000 +#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd +#define PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK 0x4000 +#define PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT 0xe +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK 0x40 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT 0x6 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK 0x3fc00 +#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT 0xa +#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff +#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0 +#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00 +#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa +#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000 +#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc +#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000 +#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd +#define PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK 0x4000 +#define PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT 0xe +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK 0x40 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT 0x6 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK 0x3fc00 +#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT 0xa +#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff +#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0 +#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00 +#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa +#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000 +#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc +#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000 +#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd +#define PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK 0x4000 +#define PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT 0xe +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK 0x40 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT 0x6 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK 0x3fc00 +#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT 0xa +#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff +#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0 +#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00 +#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa +#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000 +#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc +#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000 +#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd +#define PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK 0x4000 +#define PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT 0xe +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK 0x40 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT 0x6 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK 0x3fc00 +#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT 0xa +#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff +#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0 +#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00 +#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa +#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000 +#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc +#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000 +#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd +#define PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK 0x4000 +#define PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT 0xe +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK 0x40 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT 0x6 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK 0x3fc00 +#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT 0xa +#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff +#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0 +#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00 +#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa +#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000 +#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc +#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000 +#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd +#define PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK 0x4000 +#define PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT 0xe +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK 0x40 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT 0x6 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK 0x3fc00 +#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT 0xa +#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff +#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0 +#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00 +#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa +#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000 +#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc +#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000 +#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd +#define PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK 0x4000 +#define PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT 0xe +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK 0x40 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT 0x6 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK 0x3fc00 +#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT 0xa +#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff +#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0 +#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00 +#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa +#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000 +#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc +#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000 +#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd +#define PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK 0x4000 +#define PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT 0xe +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK 0x40 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT 0x6 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK 0x3fc00 +#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT 0xa +#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff +#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0 +#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00 +#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa +#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000 +#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc +#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000 +#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd +#define PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK 0x4000 +#define PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT 0xe +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK 0x40 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT 0x6 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK 0x3fc00 +#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT 0xa +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7 +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0 +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38 +#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000 +#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe +#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000 +#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11 +#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000 +#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13 +#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000 +#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14 +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000 +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15 +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000 +#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16 +#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000 +#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17 +#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK 0x1000000 +#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT 0x18 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000 +#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK 0x1 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT 0x0 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT 0x1 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK 0x4 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK 0x8 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT 0x3 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK 0x100 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT 0x8 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK 0x200 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT 0x9 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK 0x400 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT 0xa +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK 0x800 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT 0xb +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK 0x1000 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT 0xc +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK 0x2000 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT 0xd +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK 0x4000 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT 0xe +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK 0x8000 +#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT 0xf +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000 +#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000 +#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000 +#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000 +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000 +#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000 +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000 +#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19 +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000 +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000 +#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000 +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000 +#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000 +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000 +#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1 +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0 +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2 +#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000 +#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000 +#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20 +#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4 +#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2 +#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8 +#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2 +#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20 +#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80 +#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00 +#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4 +#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2 +#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8 +#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2 +#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20 +#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80 +#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00 +#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4 +#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2 +#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8 +#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2 +#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20 +#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80 +#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00 +#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4 +#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2 +#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8 +#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2 +#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20 +#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80 +#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00 +#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4 +#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2 +#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8 +#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2 +#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20 +#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80 +#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00 +#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4 +#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2 +#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8 +#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2 +#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20 +#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80 +#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00 +#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4 +#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2 +#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8 +#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2 +#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20 +#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80 +#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00 +#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4 +#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2 +#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8 +#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2 +#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20 +#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80 +#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00 +#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4 +#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2 +#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8 +#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2 +#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20 +#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80 +#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00 +#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4 +#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2 +#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8 +#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2 +#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20 +#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80 +#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00 +#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4 +#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2 +#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8 +#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2 +#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20 +#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80 +#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00 +#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4 +#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2 +#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8 +#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2 +#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20 +#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80 +#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00 +#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4 +#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2 +#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8 +#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2 +#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20 +#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80 +#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00 +#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4 +#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2 +#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8 +#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2 +#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20 +#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80 +#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00 +#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4 +#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2 +#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8 +#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2 +#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20 +#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80 +#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00 +#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4 +#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2 +#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8 +#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2 +#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20 +#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80 +#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00 +#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa +#define PB1_GLB_CTRL_REG0__BACKUP_MASK 0xffff +#define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x0 +#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000 +#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10 +#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000 +#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14 +#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000 +#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17 +#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000 +#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18 +#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000 +#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19 +#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000 +#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a +#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000 +#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00 +#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8 +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000 +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000 +#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000 +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16 +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000 +#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17 +#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000 +#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e +#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000 +#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1 +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0 +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe +#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00 +#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000 +#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000 +#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19 +#define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f +#define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180 +#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7 +#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600 +#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9 +#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800 +#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb +#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000 +#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc +#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000 +#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe +#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000 +#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12 +#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000 +#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15 +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000 +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16 +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000 +#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17 +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000 +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000 +#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c +#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000 +#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000 +#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12 +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000 +#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16 +#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000 +#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a +#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000 +#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b +#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000 +#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c +#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff +#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK 0x8 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT 0x3 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000 +#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc +#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000 +#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000 +#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf +#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK 0x30000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12 +#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK 0x300000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT 0x14 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16 +#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK 0x3000000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT 0x18 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a +#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK 0x30000000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT 0x1c +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000 +#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf +#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK 0x30000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12 +#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK 0x300000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT 0x14 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16 +#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK 0x3000000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT 0x18 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a +#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK 0x30000000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT 0x1c +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000 +#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf +#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK 0x30000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12 +#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK 0x300000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT 0x14 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16 +#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK 0x3000000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT 0x18 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a +#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK 0x30000000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT 0x1c +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000 +#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT 0x0 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT 0x1 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK 0x4 +#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf +#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK 0x30000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT 0x10 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12 +#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK 0x300000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT 0x14 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16 +#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK 0x3000000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT 0x18 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a +#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK 0x30000000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT 0x1c +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000 +#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e +#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff +#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0 +#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000 +#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10 +#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1 +#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0 +#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2 +#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8 +#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3 +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000 +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000 +#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2 +#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1 +#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK 0x4 +#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2 +#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK 0x8 +#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT 0x3 +#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK 0x10 +#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT 0x4 +#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK 0x20 +#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT 0x5 +#define PB1_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PB1_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PB1_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PB1_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PB1_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PB1_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PB1_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PB1_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PB1_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PB1_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PB1_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PB1_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PB1_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PB1_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PB1_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PB1_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PB1_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PB1_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PB1_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PB1_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PB1_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PB1_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PB1_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PB1_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PB1_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PB1_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PB1_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PB1_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PB1_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PB1_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PB1_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PB1_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PB1_HW_DEBUG__HW_16_DEBUG_MASK 0x10000 +#define PB1_HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 +#define PB1_HW_DEBUG__HW_17_DEBUG_MASK 0x20000 +#define PB1_HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 +#define PB1_HW_DEBUG__HW_18_DEBUG_MASK 0x40000 +#define PB1_HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 +#define PB1_HW_DEBUG__HW_19_DEBUG_MASK 0x80000 +#define PB1_HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 +#define PB1_HW_DEBUG__HW_20_DEBUG_MASK 0x100000 +#define PB1_HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 +#define PB1_HW_DEBUG__HW_21_DEBUG_MASK 0x200000 +#define PB1_HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 +#define PB1_HW_DEBUG__HW_22_DEBUG_MASK 0x400000 +#define PB1_HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 +#define PB1_HW_DEBUG__HW_23_DEBUG_MASK 0x800000 +#define PB1_HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 +#define PB1_HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 +#define PB1_HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 +#define PB1_HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 +#define PB1_HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 +#define PB1_HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 +#define PB1_HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a +#define PB1_HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 +#define PB1_HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b +#define PB1_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 +#define PB1_HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c +#define PB1_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 +#define PB1_HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d +#define PB1_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 +#define PB1_HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e +#define PB1_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 +#define PB1_HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f +#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2 +#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1 +#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4 +#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2 +#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8 +#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3 +#define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK 0x10 +#define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT 0x4 +#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60 +#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5 +#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80 +#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7 +#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000 +#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc +#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000 +#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd +#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000 +#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf +#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000 +#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000 +#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c +#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000 +#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000 +#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5 +#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40 +#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7 +#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300 +#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8 +#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00 +#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18 +#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000 +#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000 +#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1 +#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c +#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2 +#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60 +#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000 +#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4 +#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000 +#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000 +#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18 +#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2 +#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1 +#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4 +#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2 +#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK 0x6 +#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT 0x1 +#define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK 0x18 +#define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT 0x3 +#define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK 0x60 +#define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT 0x5 +#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK 0x80 +#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT 0x7 +#define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK 0x300 +#define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT 0x8 +#define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK 0x400 +#define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT 0xa +#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK 0x1800 +#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT 0xb +#define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK 0x1c +#define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2 +#define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK 0x60 +#define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT 0x5 +#define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK 0x180 +#define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT 0x7 +#define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK 0x600 +#define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT 0x9 +#define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK 0x1800 +#define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT 0xb +#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK 0x10000000 +#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT 0x1c +#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK 0x20000000 +#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT 0x1d +#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK 0xc0000000 +#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT 0x1e +#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f +#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0 +#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80 +#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7 +#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00 +#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8 +#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000 +#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14 +#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000 +#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15 +#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000 +#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16 +#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000 +#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17 +#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000 +#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18 +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0 +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100 +#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8 +#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000 +#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10 +#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000 +#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11 +#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000 +#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14 +#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff +#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0 +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1 +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0 +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e +#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1 +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0 +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00 +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8 +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000 +#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK 0x8000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT 0xf +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK 0x10000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x10 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK 0x20000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT 0x11 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK 0x40000 +#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x12 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0 +#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4 +#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800 +#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000 +#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000 +#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK 0x300 +#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT 0x8 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK 0x300 +#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT 0x8 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK 0x300 +#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT 0x8 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK 0x300 +#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT 0x8 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8 +#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3 +#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10 +#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000 +#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200 +#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000 +#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70 +#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70 +#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70 +#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70 +#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000 +#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000 +#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d +#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000 +#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000 +#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000 +#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2 +#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK 0x18 +#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT 0x3 +#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK 0x60 +#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT 0x5 +#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK 0x180 +#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT 0x7 +#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK 0xe00 +#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT 0x9 +#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK 0x3000 +#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT 0xc +#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK 0xc000 +#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT 0xe +#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK 0x30000 +#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT 0x10 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000 +#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000 +#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000 +#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d +#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000 +#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000 +#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000 +#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a +#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000 +#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b +#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000 +#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK 0x20000000 +#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT 0x1d +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8 +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000 +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000 +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK 0x4000 +#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT 0xe +#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK 0x10000 +#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT 0x10 +#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK 0x20000 +#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT 0x11 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000 +#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d +#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3 +#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0 +#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc +#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2 +#define PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK 0x10 +#define PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT 0x4 +#define PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK 0x20 +#define PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT 0x5 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK 0x1 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT 0x0 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT 0x1 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK 0x4 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK 0x8 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT 0x3 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK 0x10 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT 0x4 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK 0x20 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT 0x5 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK 0x40 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT 0x6 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK 0x80 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT 0x7 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK 0x100 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT 0x8 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK 0x200 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT 0x9 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK 0x400 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT 0xa +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK 0x800 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT 0xb +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK 0x1000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT 0xc +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK 0x2000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT 0xd +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK 0x4000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT 0xe +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK 0x8000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT 0xf +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK 0x10000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT 0x10 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK 0x20000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT 0x11 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK 0x40000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT 0x12 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK 0x80000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT 0x13 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK 0x100000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT 0x14 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK 0x200000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT 0x15 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK 0x400000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT 0x16 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK 0x800000 +#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT 0x17 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000 +#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000 +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000 +#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10 +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000 +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11 +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000 +#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000 +#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000 +#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16 +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000 +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000 +#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000 +#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1 +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0 +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2 +#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1 +#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff +#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0 +#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00 +#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa +#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000 +#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc +#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000 +#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd +#define PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK 0x4000 +#define PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT 0xe +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK 0x40 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT 0x6 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK 0x3fc00 +#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT 0xa +#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff +#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0 +#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00 +#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa +#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000 +#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc +#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000 +#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd +#define PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK 0x4000 +#define PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT 0xe +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK 0x40 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT 0x6 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK 0x3fc00 +#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT 0xa +#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff +#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0 +#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00 +#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa +#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000 +#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc +#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000 +#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd +#define PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK 0x4000 +#define PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT 0xe +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK 0x40 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT 0x6 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK 0x3fc00 +#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT 0xa +#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff +#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0 +#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00 +#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa +#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000 +#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc +#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000 +#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd +#define PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK 0x4000 +#define PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT 0xe +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK 0x40 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT 0x6 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK 0x3fc00 +#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT 0xa +#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff +#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0 +#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00 +#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa +#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000 +#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc +#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000 +#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd +#define PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK 0x4000 +#define PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT 0xe +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK 0x40 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT 0x6 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK 0x3fc00 +#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT 0xa +#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff +#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0 +#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00 +#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa +#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000 +#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc +#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000 +#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd +#define PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK 0x4000 +#define PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT 0xe +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK 0x40 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT 0x6 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK 0x3fc00 +#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT 0xa +#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff +#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0 +#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00 +#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa +#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000 +#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc +#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000 +#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd +#define PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK 0x4000 +#define PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT 0xe +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK 0x40 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT 0x6 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK 0x3fc00 +#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT 0xa +#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff +#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0 +#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00 +#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa +#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000 +#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc +#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000 +#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd +#define PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK 0x4000 +#define PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT 0xe +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK 0x40 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT 0x6 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK 0x3fc00 +#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT 0xa +#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff +#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0 +#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00 +#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa +#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000 +#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc +#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000 +#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd +#define PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK 0x4000 +#define PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT 0xe +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK 0x40 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT 0x6 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK 0x3fc00 +#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT 0xa +#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff +#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0 +#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00 +#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa +#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000 +#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc +#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000 +#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd +#define PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK 0x4000 +#define PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT 0xe +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK 0x40 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT 0x6 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK 0x3fc00 +#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT 0xa +#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff +#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0 +#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00 +#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa +#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000 +#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc +#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000 +#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd +#define PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK 0x4000 +#define PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT 0xe +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK 0x40 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT 0x6 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK 0x3fc00 +#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT 0xa +#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff +#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0 +#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00 +#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa +#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000 +#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc +#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000 +#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd +#define PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK 0x4000 +#define PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT 0xe +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK 0x40 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT 0x6 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK 0x3fc00 +#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT 0xa +#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff +#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0 +#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00 +#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa +#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000 +#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc +#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000 +#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd +#define PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK 0x4000 +#define PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT 0xe +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK 0x40 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT 0x6 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK 0x3fc00 +#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT 0xa +#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff +#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0 +#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00 +#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa +#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000 +#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc +#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000 +#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd +#define PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK 0x4000 +#define PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT 0xe +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK 0x40 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT 0x6 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK 0x3fc00 +#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT 0xa +#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff +#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0 +#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00 +#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa +#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000 +#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc +#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000 +#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd +#define PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK 0x4000 +#define PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT 0xe +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK 0x40 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT 0x6 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK 0x3fc00 +#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT 0xa +#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff +#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0 +#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00 +#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa +#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000 +#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc +#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000 +#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd +#define PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK 0x4000 +#define PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT 0xe +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK 0x40 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT 0x6 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK 0x3fc00 +#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT 0xa +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7 +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0 +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38 +#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000 +#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe +#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000 +#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11 +#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000 +#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13 +#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000 +#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14 +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000 +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15 +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000 +#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16 +#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000 +#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17 +#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK 0x1000000 +#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT 0x18 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000 +#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK 0x1 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT 0x0 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT 0x1 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK 0x4 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK 0x8 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT 0x3 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK 0x100 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT 0x8 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK 0x200 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT 0x9 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK 0x400 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT 0xa +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK 0x800 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT 0xb +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK 0x1000 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT 0xc +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK 0x2000 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT 0xd +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK 0x4000 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT 0xe +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK 0x8000 +#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT 0xf +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000 +#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000 +#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000 +#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000 +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000 +#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000 +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000 +#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19 +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000 +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000 +#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000 +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000 +#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000 +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000 +#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1 +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0 +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2 +#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000 +#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000 +#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20 +#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4 +#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2 +#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8 +#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2 +#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20 +#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80 +#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00 +#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4 +#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2 +#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8 +#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2 +#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20 +#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80 +#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00 +#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4 +#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2 +#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8 +#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2 +#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20 +#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80 +#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00 +#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4 +#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2 +#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8 +#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2 +#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20 +#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80 +#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00 +#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4 +#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2 +#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8 +#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2 +#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20 +#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80 +#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00 +#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4 +#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2 +#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8 +#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2 +#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20 +#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80 +#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00 +#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4 +#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2 +#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8 +#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2 +#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20 +#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80 +#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00 +#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4 +#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2 +#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8 +#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2 +#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20 +#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80 +#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00 +#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4 +#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2 +#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8 +#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2 +#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20 +#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80 +#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00 +#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4 +#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2 +#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8 +#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2 +#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20 +#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80 +#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00 +#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4 +#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2 +#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8 +#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2 +#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20 +#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80 +#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00 +#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4 +#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2 +#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8 +#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2 +#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20 +#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80 +#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00 +#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4 +#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2 +#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8 +#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2 +#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20 +#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80 +#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00 +#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4 +#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2 +#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8 +#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2 +#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20 +#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80 +#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00 +#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4 +#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2 +#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8 +#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2 +#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20 +#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80 +#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00 +#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4 +#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2 +#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8 +#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2 +#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20 +#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80 +#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00 +#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa +#define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff +#define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0 +#define PB0_PIF_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PB0_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PB0_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PB0_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PB0_PIF_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PB0_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PB0_PIF_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PB0_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PB0_PIF_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PB0_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PB0_PIF_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PB0_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PB0_PIF_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PB0_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PB0_PIF_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PB0_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PB0_PIF_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PB0_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PB0_PIF_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PB0_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PB0_PIF_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PB0_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PB0_PIF_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PB0_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PB0_PIF_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PB0_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PB0_PIF_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PB0_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PB0_PIF_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PB0_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PB0_PIF_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PB0_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2 +#define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1 +#define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4 +#define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2 +#define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8 +#define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3 +#define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10 +#define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4 +#define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20 +#define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5 +#define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0 +#define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6 +#define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300 +#define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8 +#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400 +#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa +#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800 +#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb +#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000 +#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc +#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000 +#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd +#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000 +#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe +#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000 +#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf +#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000 +#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10 +#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1 +#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0 +#define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2 +#define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1 +#define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4 +#define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2 +#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8 +#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3 +#define PB0_PIF_CTRL__PHY_RST_PWROK_VDD_MASK 0x10 +#define PB0_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4 +#define PB0_PIF_CTRL__PIF_PLL_STATUS_MASK 0xc0 +#define PB0_PIF_CTRL__PIF_PLL_STATUS__SHIFT 0x6 +#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100 +#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8 +#define PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200 +#define PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9 +#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400 +#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa +#define PB0_PIF_CTRL__PIF_PG_EXIT_MODE_MASK 0x800 +#define PB0_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb +#define PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000 +#define PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc +#define PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000 +#define PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd +#define PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000 +#define PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe +#define PB0_PIF_TX_CTRL__TXPWR_IN_S2_MASK 0x7 +#define PB0_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0 +#define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38 +#define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3 +#define PB0_PIF_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0 +#define PB0_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6 +#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00 +#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9 +#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000 +#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc +#define PB0_PIF_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000 +#define PB0_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf +#define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000 +#define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12 +#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000 +#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15 +#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000 +#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16 +#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000 +#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17 +#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000 +#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18 +#define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7 +#define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0 +#define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38 +#define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3 +#define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0 +#define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6 +#define PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200 +#define PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 +#define PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 +#define PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa +#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000 +#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10 +#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000 +#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11 +#define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000 +#define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15 +#define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000 +#define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16 +#define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000 +#define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19 +#define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000 +#define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a +#define PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000 +#define PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d +#define PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000 +#define PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e +#define PB0_PIF_RX_CTRL__RXPWR_IN_S2_MASK 0x7 +#define PB0_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0 +#define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38 +#define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3 +#define PB0_PIF_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0 +#define PB0_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6 +#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00 +#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9 +#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000 +#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc +#define PB0_PIF_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000 +#define PB0_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf +#define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000 +#define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12 +#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000 +#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15 +#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000 +#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16 +#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000 +#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17 +#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000 +#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18 +#define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000 +#define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19 +#define PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000 +#define PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a +#define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7 +#define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0 +#define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38 +#define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3 +#define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0 +#define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6 +#define PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200 +#define PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 +#define PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 +#define PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa +#define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000 +#define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10 +#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000 +#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11 +#define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000 +#define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13 +#define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000 +#define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15 +#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000 +#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18 +#define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000 +#define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19 +#define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000 +#define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000 +#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10 +#define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1 +#define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0 +#define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2 +#define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1 +#define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4 +#define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2 +#define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8 +#define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3 +#define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10 +#define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4 +#define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20 +#define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5 +#define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40 +#define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6 +#define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80 +#define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7 +#define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100 +#define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8 +#define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200 +#define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9 +#define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400 +#define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa +#define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800 +#define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb +#define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000 +#define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10 +#define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000 +#define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11 +#define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000 +#define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80 +#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7 +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100 +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8 +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200 +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9 +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400 +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800 +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000 +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000 +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000 +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000 +#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000 +#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3 +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0 +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2 +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10 +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4 +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60 +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5 +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80 +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7 +#define PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100 +#define PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8 +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200 +#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9 +#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1 +#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0 +#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2 +#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1 +#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4 +#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2 +#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38 +#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3 +#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40 +#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6 +#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180 +#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7 +#define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200 +#define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000 +#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17 +#define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1 +#define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0 +#define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2 +#define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1 +#define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4 +#define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2 +#define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8 +#define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3 +#define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10 +#define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4 +#define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20 +#define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5 +#define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40 +#define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6 +#define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80 +#define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7 +#define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100 +#define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8 +#define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200 +#define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9 +#define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400 +#define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa +#define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800 +#define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb +#define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000 +#define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc +#define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000 +#define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd +#define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000 +#define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe +#define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000 +#define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf +#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000 +#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10 +#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000 +#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11 +#define PB0_PIF_LANE0_OVRD2__GANGMODE_0_MASK 0x7 +#define PB0_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0 +#define PB0_PIF_LANE0_OVRD2__FREQDIV_0_MASK 0x18 +#define PB0_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3 +#define PB0_PIF_LANE0_OVRD2__LINKSPEED_0_MASK 0x60 +#define PB0_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5 +#define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80 +#define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7 +#define PB0_PIF_LANE0_OVRD2__TXPWR_0_MASK 0x700 +#define PB0_PIF_LANE0_OVRD2__TXPWR_0__SHIFT 0x8 +#define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800 +#define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb +#define PB0_PIF_LANE0_OVRD2__RXPWR_0_MASK 0xe000 +#define PB0_PIF_LANE0_OVRD2__RXPWR_0__SHIFT 0xd +#define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000 +#define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10 +#define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000 +#define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12 +#define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000 +#define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13 +#define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000 +#define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14 +#define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000 +#define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15 +#define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000 +#define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16 +#define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000 +#define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17 +#define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000 +#define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18 +#define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000 +#define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a +#define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1 +#define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0 +#define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2 +#define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1 +#define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4 +#define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2 +#define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8 +#define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3 +#define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10 +#define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4 +#define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20 +#define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5 +#define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40 +#define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6 +#define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80 +#define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7 +#define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100 +#define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8 +#define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200 +#define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9 +#define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400 +#define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa +#define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800 +#define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb +#define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000 +#define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc +#define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000 +#define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd +#define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000 +#define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe +#define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000 +#define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf +#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000 +#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10 +#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000 +#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11 +#define PB0_PIF_LANE1_OVRD2__GANGMODE_1_MASK 0x7 +#define PB0_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0 +#define PB0_PIF_LANE1_OVRD2__FREQDIV_1_MASK 0x18 +#define PB0_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3 +#define PB0_PIF_LANE1_OVRD2__LINKSPEED_1_MASK 0x60 +#define PB0_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5 +#define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80 +#define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7 +#define PB0_PIF_LANE1_OVRD2__TXPWR_1_MASK 0x700 +#define PB0_PIF_LANE1_OVRD2__TXPWR_1__SHIFT 0x8 +#define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800 +#define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb +#define PB0_PIF_LANE1_OVRD2__RXPWR_1_MASK 0xe000 +#define PB0_PIF_LANE1_OVRD2__RXPWR_1__SHIFT 0xd +#define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000 +#define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10 +#define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000 +#define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12 +#define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000 +#define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13 +#define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000 +#define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14 +#define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000 +#define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15 +#define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000 +#define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16 +#define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000 +#define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17 +#define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000 +#define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18 +#define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000 +#define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a +#define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1 +#define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0 +#define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2 +#define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1 +#define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4 +#define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2 +#define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8 +#define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3 +#define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10 +#define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4 +#define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20 +#define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5 +#define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40 +#define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6 +#define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80 +#define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7 +#define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100 +#define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8 +#define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200 +#define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9 +#define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400 +#define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa +#define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800 +#define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb +#define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000 +#define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc +#define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000 +#define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd +#define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000 +#define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe +#define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000 +#define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf +#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000 +#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10 +#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000 +#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11 +#define PB0_PIF_LANE2_OVRD2__GANGMODE_2_MASK 0x7 +#define PB0_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0 +#define PB0_PIF_LANE2_OVRD2__FREQDIV_2_MASK 0x18 +#define PB0_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3 +#define PB0_PIF_LANE2_OVRD2__LINKSPEED_2_MASK 0x60 +#define PB0_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5 +#define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80 +#define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7 +#define PB0_PIF_LANE2_OVRD2__TXPWR_2_MASK 0x700 +#define PB0_PIF_LANE2_OVRD2__TXPWR_2__SHIFT 0x8 +#define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800 +#define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb +#define PB0_PIF_LANE2_OVRD2__RXPWR_2_MASK 0xe000 +#define PB0_PIF_LANE2_OVRD2__RXPWR_2__SHIFT 0xd +#define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000 +#define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10 +#define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000 +#define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12 +#define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000 +#define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13 +#define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000 +#define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14 +#define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000 +#define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15 +#define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000 +#define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16 +#define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000 +#define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17 +#define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000 +#define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18 +#define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000 +#define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a +#define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1 +#define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0 +#define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2 +#define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1 +#define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4 +#define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2 +#define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8 +#define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3 +#define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10 +#define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4 +#define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20 +#define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5 +#define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40 +#define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6 +#define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80 +#define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7 +#define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100 +#define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8 +#define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200 +#define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9 +#define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400 +#define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa +#define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800 +#define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb +#define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000 +#define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc +#define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000 +#define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd +#define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000 +#define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe +#define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000 +#define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf +#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000 +#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10 +#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000 +#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11 +#define PB0_PIF_LANE3_OVRD2__GANGMODE_3_MASK 0x7 +#define PB0_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0 +#define PB0_PIF_LANE3_OVRD2__FREQDIV_3_MASK 0x18 +#define PB0_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3 +#define PB0_PIF_LANE3_OVRD2__LINKSPEED_3_MASK 0x60 +#define PB0_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5 +#define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80 +#define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7 +#define PB0_PIF_LANE3_OVRD2__TXPWR_3_MASK 0x700 +#define PB0_PIF_LANE3_OVRD2__TXPWR_3__SHIFT 0x8 +#define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800 +#define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb +#define PB0_PIF_LANE3_OVRD2__RXPWR_3_MASK 0xe000 +#define PB0_PIF_LANE3_OVRD2__RXPWR_3__SHIFT 0xd +#define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000 +#define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10 +#define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000 +#define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12 +#define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000 +#define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13 +#define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000 +#define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14 +#define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000 +#define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15 +#define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000 +#define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16 +#define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000 +#define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17 +#define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000 +#define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18 +#define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000 +#define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a +#define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1 +#define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0 +#define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2 +#define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1 +#define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4 +#define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2 +#define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8 +#define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3 +#define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10 +#define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4 +#define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20 +#define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5 +#define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40 +#define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6 +#define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80 +#define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7 +#define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100 +#define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8 +#define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200 +#define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9 +#define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400 +#define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa +#define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800 +#define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb +#define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000 +#define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc +#define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000 +#define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd +#define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000 +#define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe +#define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000 +#define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf +#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000 +#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10 +#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000 +#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11 +#define PB0_PIF_LANE4_OVRD2__GANGMODE_4_MASK 0x7 +#define PB0_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0 +#define PB0_PIF_LANE4_OVRD2__FREQDIV_4_MASK 0x18 +#define PB0_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3 +#define PB0_PIF_LANE4_OVRD2__LINKSPEED_4_MASK 0x60 +#define PB0_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5 +#define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80 +#define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7 +#define PB0_PIF_LANE4_OVRD2__TXPWR_4_MASK 0x700 +#define PB0_PIF_LANE4_OVRD2__TXPWR_4__SHIFT 0x8 +#define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800 +#define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb +#define PB0_PIF_LANE4_OVRD2__RXPWR_4_MASK 0xe000 +#define PB0_PIF_LANE4_OVRD2__RXPWR_4__SHIFT 0xd +#define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000 +#define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10 +#define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000 +#define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12 +#define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000 +#define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13 +#define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000 +#define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14 +#define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000 +#define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15 +#define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000 +#define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16 +#define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000 +#define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17 +#define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000 +#define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18 +#define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000 +#define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a +#define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1 +#define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0 +#define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2 +#define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1 +#define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4 +#define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2 +#define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8 +#define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3 +#define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10 +#define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4 +#define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20 +#define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5 +#define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40 +#define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6 +#define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80 +#define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7 +#define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100 +#define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8 +#define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200 +#define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9 +#define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400 +#define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa +#define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800 +#define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb +#define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000 +#define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc +#define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000 +#define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd +#define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000 +#define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe +#define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000 +#define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf +#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000 +#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10 +#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000 +#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11 +#define PB0_PIF_LANE5_OVRD2__GANGMODE_5_MASK 0x7 +#define PB0_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0 +#define PB0_PIF_LANE5_OVRD2__FREQDIV_5_MASK 0x18 +#define PB0_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3 +#define PB0_PIF_LANE5_OVRD2__LINKSPEED_5_MASK 0x60 +#define PB0_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5 +#define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80 +#define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7 +#define PB0_PIF_LANE5_OVRD2__TXPWR_5_MASK 0x700 +#define PB0_PIF_LANE5_OVRD2__TXPWR_5__SHIFT 0x8 +#define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800 +#define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb +#define PB0_PIF_LANE5_OVRD2__RXPWR_5_MASK 0xe000 +#define PB0_PIF_LANE5_OVRD2__RXPWR_5__SHIFT 0xd +#define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000 +#define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10 +#define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000 +#define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12 +#define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000 +#define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13 +#define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000 +#define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14 +#define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000 +#define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15 +#define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000 +#define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16 +#define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000 +#define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17 +#define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000 +#define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18 +#define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000 +#define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a +#define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1 +#define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0 +#define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2 +#define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1 +#define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4 +#define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2 +#define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8 +#define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3 +#define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10 +#define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4 +#define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20 +#define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5 +#define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40 +#define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6 +#define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80 +#define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7 +#define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100 +#define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8 +#define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200 +#define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9 +#define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400 +#define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa +#define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800 +#define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb +#define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000 +#define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc +#define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000 +#define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd +#define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000 +#define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe +#define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000 +#define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf +#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000 +#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10 +#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000 +#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11 +#define PB0_PIF_LANE6_OVRD2__GANGMODE_6_MASK 0x7 +#define PB0_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0 +#define PB0_PIF_LANE6_OVRD2__FREQDIV_6_MASK 0x18 +#define PB0_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3 +#define PB0_PIF_LANE6_OVRD2__LINKSPEED_6_MASK 0x60 +#define PB0_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5 +#define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80 +#define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7 +#define PB0_PIF_LANE6_OVRD2__TXPWR_6_MASK 0x700 +#define PB0_PIF_LANE6_OVRD2__TXPWR_6__SHIFT 0x8 +#define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800 +#define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb +#define PB0_PIF_LANE6_OVRD2__RXPWR_6_MASK 0xe000 +#define PB0_PIF_LANE6_OVRD2__RXPWR_6__SHIFT 0xd +#define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000 +#define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10 +#define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000 +#define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12 +#define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000 +#define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13 +#define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000 +#define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14 +#define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000 +#define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15 +#define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000 +#define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16 +#define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000 +#define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17 +#define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000 +#define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18 +#define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000 +#define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a +#define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1 +#define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0 +#define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2 +#define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1 +#define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4 +#define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2 +#define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8 +#define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3 +#define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10 +#define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4 +#define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20 +#define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5 +#define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40 +#define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6 +#define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80 +#define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7 +#define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100 +#define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8 +#define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200 +#define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9 +#define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400 +#define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa +#define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800 +#define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb +#define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000 +#define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc +#define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000 +#define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd +#define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000 +#define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe +#define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000 +#define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf +#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000 +#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10 +#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000 +#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11 +#define PB0_PIF_LANE7_OVRD2__GANGMODE_7_MASK 0x7 +#define PB0_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0 +#define PB0_PIF_LANE7_OVRD2__FREQDIV_7_MASK 0x18 +#define PB0_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3 +#define PB0_PIF_LANE7_OVRD2__LINKSPEED_7_MASK 0x60 +#define PB0_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5 +#define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80 +#define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7 +#define PB0_PIF_LANE7_OVRD2__TXPWR_7_MASK 0x700 +#define PB0_PIF_LANE7_OVRD2__TXPWR_7__SHIFT 0x8 +#define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800 +#define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb +#define PB0_PIF_LANE7_OVRD2__RXPWR_7_MASK 0xe000 +#define PB0_PIF_LANE7_OVRD2__RXPWR_7__SHIFT 0xd +#define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000 +#define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10 +#define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000 +#define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12 +#define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000 +#define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13 +#define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000 +#define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14 +#define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000 +#define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15 +#define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000 +#define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16 +#define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000 +#define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17 +#define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000 +#define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18 +#define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000 +#define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a +#define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff +#define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0 +#define PB1_PIF_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PB1_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PB1_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PB1_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PB1_PIF_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PB1_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PB1_PIF_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PB1_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PB1_PIF_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PB1_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PB1_PIF_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PB1_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PB1_PIF_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PB1_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PB1_PIF_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PB1_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PB1_PIF_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PB1_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PB1_PIF_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PB1_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PB1_PIF_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PB1_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PB1_PIF_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PB1_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PB1_PIF_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PB1_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PB1_PIF_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PB1_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PB1_PIF_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PB1_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PB1_PIF_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PB1_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2 +#define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1 +#define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4 +#define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2 +#define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8 +#define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3 +#define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10 +#define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4 +#define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20 +#define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5 +#define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0 +#define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6 +#define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300 +#define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8 +#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400 +#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa +#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800 +#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb +#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000 +#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc +#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000 +#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd +#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000 +#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe +#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000 +#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf +#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000 +#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10 +#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1 +#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0 +#define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2 +#define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1 +#define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4 +#define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2 +#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8 +#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3 +#define PB1_PIF_CTRL__PHY_RST_PWROK_VDD_MASK 0x10 +#define PB1_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4 +#define PB1_PIF_CTRL__PIF_PLL_STATUS_MASK 0xc0 +#define PB1_PIF_CTRL__PIF_PLL_STATUS__SHIFT 0x6 +#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100 +#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8 +#define PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200 +#define PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9 +#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400 +#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa +#define PB1_PIF_CTRL__PIF_PG_EXIT_MODE_MASK 0x800 +#define PB1_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb +#define PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000 +#define PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc +#define PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000 +#define PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd +#define PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000 +#define PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe +#define PB1_PIF_TX_CTRL__TXPWR_IN_S2_MASK 0x7 +#define PB1_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0 +#define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38 +#define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3 +#define PB1_PIF_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0 +#define PB1_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6 +#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00 +#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9 +#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000 +#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc +#define PB1_PIF_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000 +#define PB1_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf +#define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000 +#define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12 +#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000 +#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15 +#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000 +#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16 +#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000 +#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17 +#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000 +#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18 +#define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7 +#define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0 +#define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38 +#define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3 +#define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0 +#define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6 +#define PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200 +#define PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 +#define PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 +#define PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa +#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000 +#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10 +#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000 +#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11 +#define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000 +#define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15 +#define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000 +#define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16 +#define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000 +#define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19 +#define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000 +#define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a +#define PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000 +#define PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d +#define PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000 +#define PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e +#define PB1_PIF_RX_CTRL__RXPWR_IN_S2_MASK 0x7 +#define PB1_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0 +#define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38 +#define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3 +#define PB1_PIF_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0 +#define PB1_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6 +#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00 +#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9 +#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000 +#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc +#define PB1_PIF_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000 +#define PB1_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf +#define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000 +#define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12 +#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000 +#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15 +#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000 +#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16 +#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000 +#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17 +#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000 +#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18 +#define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000 +#define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19 +#define PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000 +#define PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a +#define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7 +#define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0 +#define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38 +#define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3 +#define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0 +#define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6 +#define PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200 +#define PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 +#define PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 +#define PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa +#define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000 +#define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10 +#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000 +#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11 +#define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000 +#define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13 +#define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000 +#define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15 +#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000 +#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18 +#define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000 +#define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19 +#define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000 +#define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000 +#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10 +#define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1 +#define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0 +#define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2 +#define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1 +#define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4 +#define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2 +#define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8 +#define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3 +#define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10 +#define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4 +#define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20 +#define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5 +#define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40 +#define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6 +#define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80 +#define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7 +#define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100 +#define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8 +#define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200 +#define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9 +#define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400 +#define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa +#define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800 +#define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb +#define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000 +#define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10 +#define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000 +#define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11 +#define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000 +#define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80 +#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7 +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100 +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8 +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200 +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9 +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400 +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800 +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000 +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000 +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000 +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000 +#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000 +#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3 +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0 +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2 +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10 +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4 +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60 +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5 +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80 +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7 +#define PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100 +#define PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8 +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200 +#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9 +#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1 +#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0 +#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2 +#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1 +#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4 +#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2 +#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38 +#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3 +#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40 +#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6 +#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180 +#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7 +#define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200 +#define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000 +#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17 +#define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1 +#define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0 +#define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2 +#define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1 +#define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4 +#define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2 +#define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8 +#define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3 +#define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10 +#define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4 +#define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20 +#define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5 +#define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40 +#define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6 +#define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80 +#define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7 +#define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100 +#define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8 +#define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200 +#define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9 +#define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400 +#define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa +#define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800 +#define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb +#define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000 +#define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc +#define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000 +#define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd +#define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000 +#define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe +#define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000 +#define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf +#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000 +#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10 +#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000 +#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11 +#define PB1_PIF_LANE0_OVRD2__GANGMODE_0_MASK 0x7 +#define PB1_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0 +#define PB1_PIF_LANE0_OVRD2__FREQDIV_0_MASK 0x18 +#define PB1_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3 +#define PB1_PIF_LANE0_OVRD2__LINKSPEED_0_MASK 0x60 +#define PB1_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5 +#define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80 +#define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7 +#define PB1_PIF_LANE0_OVRD2__TXPWR_0_MASK 0x700 +#define PB1_PIF_LANE0_OVRD2__TXPWR_0__SHIFT 0x8 +#define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800 +#define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb +#define PB1_PIF_LANE0_OVRD2__RXPWR_0_MASK 0xe000 +#define PB1_PIF_LANE0_OVRD2__RXPWR_0__SHIFT 0xd +#define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000 +#define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10 +#define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000 +#define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12 +#define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000 +#define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13 +#define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000 +#define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14 +#define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000 +#define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15 +#define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000 +#define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16 +#define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000 +#define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17 +#define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000 +#define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18 +#define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000 +#define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a +#define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1 +#define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0 +#define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2 +#define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1 +#define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4 +#define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2 +#define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8 +#define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3 +#define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10 +#define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4 +#define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20 +#define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5 +#define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40 +#define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6 +#define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80 +#define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7 +#define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100 +#define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8 +#define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200 +#define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9 +#define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400 +#define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa +#define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800 +#define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb +#define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000 +#define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc +#define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000 +#define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd +#define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000 +#define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe +#define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000 +#define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf +#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000 +#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10 +#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000 +#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11 +#define PB1_PIF_LANE1_OVRD2__GANGMODE_1_MASK 0x7 +#define PB1_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0 +#define PB1_PIF_LANE1_OVRD2__FREQDIV_1_MASK 0x18 +#define PB1_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3 +#define PB1_PIF_LANE1_OVRD2__LINKSPEED_1_MASK 0x60 +#define PB1_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5 +#define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80 +#define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7 +#define PB1_PIF_LANE1_OVRD2__TXPWR_1_MASK 0x700 +#define PB1_PIF_LANE1_OVRD2__TXPWR_1__SHIFT 0x8 +#define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800 +#define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb +#define PB1_PIF_LANE1_OVRD2__RXPWR_1_MASK 0xe000 +#define PB1_PIF_LANE1_OVRD2__RXPWR_1__SHIFT 0xd +#define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000 +#define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10 +#define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000 +#define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12 +#define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000 +#define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13 +#define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000 +#define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14 +#define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000 +#define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15 +#define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000 +#define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16 +#define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000 +#define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17 +#define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000 +#define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18 +#define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000 +#define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a +#define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1 +#define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0 +#define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2 +#define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1 +#define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4 +#define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2 +#define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8 +#define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3 +#define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10 +#define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4 +#define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20 +#define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5 +#define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40 +#define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6 +#define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80 +#define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7 +#define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100 +#define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8 +#define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200 +#define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9 +#define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400 +#define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa +#define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800 +#define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb +#define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000 +#define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc +#define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000 +#define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd +#define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000 +#define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe +#define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000 +#define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf +#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000 +#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10 +#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000 +#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11 +#define PB1_PIF_LANE2_OVRD2__GANGMODE_2_MASK 0x7 +#define PB1_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0 +#define PB1_PIF_LANE2_OVRD2__FREQDIV_2_MASK 0x18 +#define PB1_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3 +#define PB1_PIF_LANE2_OVRD2__LINKSPEED_2_MASK 0x60 +#define PB1_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5 +#define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80 +#define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7 +#define PB1_PIF_LANE2_OVRD2__TXPWR_2_MASK 0x700 +#define PB1_PIF_LANE2_OVRD2__TXPWR_2__SHIFT 0x8 +#define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800 +#define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb +#define PB1_PIF_LANE2_OVRD2__RXPWR_2_MASK 0xe000 +#define PB1_PIF_LANE2_OVRD2__RXPWR_2__SHIFT 0xd +#define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000 +#define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10 +#define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000 +#define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12 +#define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000 +#define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13 +#define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000 +#define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14 +#define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000 +#define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15 +#define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000 +#define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16 +#define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000 +#define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17 +#define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000 +#define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18 +#define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000 +#define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a +#define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1 +#define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0 +#define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2 +#define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1 +#define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4 +#define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2 +#define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8 +#define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3 +#define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10 +#define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4 +#define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20 +#define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5 +#define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40 +#define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6 +#define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80 +#define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7 +#define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100 +#define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8 +#define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200 +#define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9 +#define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400 +#define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa +#define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800 +#define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb +#define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000 +#define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc +#define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000 +#define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd +#define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000 +#define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe +#define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000 +#define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf +#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000 +#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10 +#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000 +#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11 +#define PB1_PIF_LANE3_OVRD2__GANGMODE_3_MASK 0x7 +#define PB1_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0 +#define PB1_PIF_LANE3_OVRD2__FREQDIV_3_MASK 0x18 +#define PB1_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3 +#define PB1_PIF_LANE3_OVRD2__LINKSPEED_3_MASK 0x60 +#define PB1_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5 +#define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80 +#define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7 +#define PB1_PIF_LANE3_OVRD2__TXPWR_3_MASK 0x700 +#define PB1_PIF_LANE3_OVRD2__TXPWR_3__SHIFT 0x8 +#define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800 +#define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb +#define PB1_PIF_LANE3_OVRD2__RXPWR_3_MASK 0xe000 +#define PB1_PIF_LANE3_OVRD2__RXPWR_3__SHIFT 0xd +#define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000 +#define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10 +#define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000 +#define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12 +#define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000 +#define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13 +#define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000 +#define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14 +#define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000 +#define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15 +#define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000 +#define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16 +#define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000 +#define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17 +#define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000 +#define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18 +#define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000 +#define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a +#define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1 +#define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0 +#define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2 +#define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1 +#define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4 +#define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2 +#define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8 +#define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3 +#define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10 +#define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4 +#define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20 +#define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5 +#define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40 +#define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6 +#define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80 +#define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7 +#define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100 +#define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8 +#define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200 +#define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9 +#define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400 +#define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa +#define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800 +#define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb +#define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000 +#define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc +#define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000 +#define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd +#define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000 +#define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe +#define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000 +#define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf +#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000 +#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10 +#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000 +#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11 +#define PB1_PIF_LANE4_OVRD2__GANGMODE_4_MASK 0x7 +#define PB1_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0 +#define PB1_PIF_LANE4_OVRD2__FREQDIV_4_MASK 0x18 +#define PB1_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3 +#define PB1_PIF_LANE4_OVRD2__LINKSPEED_4_MASK 0x60 +#define PB1_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5 +#define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80 +#define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7 +#define PB1_PIF_LANE4_OVRD2__TXPWR_4_MASK 0x700 +#define PB1_PIF_LANE4_OVRD2__TXPWR_4__SHIFT 0x8 +#define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800 +#define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb +#define PB1_PIF_LANE4_OVRD2__RXPWR_4_MASK 0xe000 +#define PB1_PIF_LANE4_OVRD2__RXPWR_4__SHIFT 0xd +#define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000 +#define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10 +#define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000 +#define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12 +#define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000 +#define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13 +#define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000 +#define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14 +#define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000 +#define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15 +#define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000 +#define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16 +#define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000 +#define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17 +#define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000 +#define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18 +#define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000 +#define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a +#define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1 +#define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0 +#define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2 +#define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1 +#define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4 +#define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2 +#define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8 +#define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3 +#define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10 +#define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4 +#define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20 +#define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5 +#define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40 +#define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6 +#define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80 +#define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7 +#define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100 +#define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8 +#define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200 +#define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9 +#define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400 +#define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa +#define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800 +#define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb +#define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000 +#define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc +#define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000 +#define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd +#define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000 +#define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe +#define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000 +#define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf +#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000 +#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10 +#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000 +#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11 +#define PB1_PIF_LANE5_OVRD2__GANGMODE_5_MASK 0x7 +#define PB1_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0 +#define PB1_PIF_LANE5_OVRD2__FREQDIV_5_MASK 0x18 +#define PB1_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3 +#define PB1_PIF_LANE5_OVRD2__LINKSPEED_5_MASK 0x60 +#define PB1_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5 +#define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80 +#define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7 +#define PB1_PIF_LANE5_OVRD2__TXPWR_5_MASK 0x700 +#define PB1_PIF_LANE5_OVRD2__TXPWR_5__SHIFT 0x8 +#define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800 +#define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb +#define PB1_PIF_LANE5_OVRD2__RXPWR_5_MASK 0xe000 +#define PB1_PIF_LANE5_OVRD2__RXPWR_5__SHIFT 0xd +#define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000 +#define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10 +#define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000 +#define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12 +#define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000 +#define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13 +#define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000 +#define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14 +#define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000 +#define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15 +#define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000 +#define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16 +#define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000 +#define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17 +#define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000 +#define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18 +#define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000 +#define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a +#define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1 +#define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0 +#define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2 +#define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1 +#define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4 +#define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2 +#define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8 +#define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3 +#define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10 +#define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4 +#define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20 +#define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5 +#define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40 +#define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6 +#define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80 +#define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7 +#define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100 +#define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8 +#define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200 +#define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9 +#define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400 +#define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa +#define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800 +#define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb +#define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000 +#define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc +#define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000 +#define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd +#define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000 +#define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe +#define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000 +#define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf +#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000 +#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10 +#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000 +#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11 +#define PB1_PIF_LANE6_OVRD2__GANGMODE_6_MASK 0x7 +#define PB1_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0 +#define PB1_PIF_LANE6_OVRD2__FREQDIV_6_MASK 0x18 +#define PB1_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3 +#define PB1_PIF_LANE6_OVRD2__LINKSPEED_6_MASK 0x60 +#define PB1_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5 +#define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80 +#define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7 +#define PB1_PIF_LANE6_OVRD2__TXPWR_6_MASK 0x700 +#define PB1_PIF_LANE6_OVRD2__TXPWR_6__SHIFT 0x8 +#define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800 +#define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb +#define PB1_PIF_LANE6_OVRD2__RXPWR_6_MASK 0xe000 +#define PB1_PIF_LANE6_OVRD2__RXPWR_6__SHIFT 0xd +#define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000 +#define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10 +#define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000 +#define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12 +#define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000 +#define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13 +#define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000 +#define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14 +#define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000 +#define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15 +#define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000 +#define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16 +#define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000 +#define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17 +#define PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000 +#define PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18 +#define PB1_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000 +#define PB1_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a +#define PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1 +#define PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0 +#define PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2 +#define PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1 +#define PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4 +#define PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2 +#define PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8 +#define PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3 +#define PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10 +#define PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4 +#define PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20 +#define PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5 +#define PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40 +#define PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6 +#define PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80 +#define PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7 +#define PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100 +#define PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8 +#define PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200 +#define PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9 +#define PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400 +#define PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa +#define PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800 +#define PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb +#define PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000 +#define PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc +#define PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000 +#define PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd +#define PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000 +#define PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe +#define PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000 +#define PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf +#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000 +#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10 +#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000 +#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11 +#define PB1_PIF_LANE7_OVRD2__GANGMODE_7_MASK 0x7 +#define PB1_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0 +#define PB1_PIF_LANE7_OVRD2__FREQDIV_7_MASK 0x18 +#define PB1_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3 +#define PB1_PIF_LANE7_OVRD2__LINKSPEED_7_MASK 0x60 +#define PB1_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5 +#define PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80 +#define PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7 +#define PB1_PIF_LANE7_OVRD2__TXPWR_7_MASK 0x700 +#define PB1_PIF_LANE7_OVRD2__TXPWR_7__SHIFT 0x8 +#define PB1_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800 +#define PB1_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb +#define PB1_PIF_LANE7_OVRD2__RXPWR_7_MASK 0xe000 +#define PB1_PIF_LANE7_OVRD2__RXPWR_7__SHIFT 0xd +#define PB1_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000 +#define PB1_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10 +#define PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000 +#define PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12 +#define PB1_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000 +#define PB1_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13 +#define PB1_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000 +#define PB1_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14 +#define PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000 +#define PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15 +#define PB1_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000 +#define PB1_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16 +#define PB1_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000 +#define PB1_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17 +#define PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000 +#define PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18 +#define PB1_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000 +#define PB1_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a +#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000 +#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000 +#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000 +#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define PCIE_FC_P__PD_CREDITS_MASK 0xff +#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc +#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd +#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 +#define PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 +#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 +#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 +#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE_MASK 0x3 +#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE__SHIFT 0x0 +#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0xc +#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x2 +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 +#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 +#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 +#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 +#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 +#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 +#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 +#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 +#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 +#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 +#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 +#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 +#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 +#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 +#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 +#define PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 +#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 +#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 +#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 +#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 +#define PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 +#define PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc +#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff +#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xffffffff +#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x1 +#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc +#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff +#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xffffffff +#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x1 +#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc +#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff +#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xffffffff +#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x1 +#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc +#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff +#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xffffffff +#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x1 +#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xf +#define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1 +#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1 +#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0 +#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2 +#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1 +#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff +#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0 +#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000 +#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e +#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000 +#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f +#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1 +#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst_MASK 0x1 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst__SHIFT 0x0 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK 0x2 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst__SHIFT 0x1 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst_MASK 0x1 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst__SHIFT 0x0 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK 0x2 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst__SHIFT 0x1 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst_MASK 0x4 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst__SHIFT 0x2 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x8 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x3 +#define BIF_PWDN_COMMAND__REG_BU_pw_cmd_MASK 0x1 +#define BIF_PWDN_COMMAND__REG_BU_pw_cmd__SHIFT 0x0 +#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK 0x2 +#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd__SHIFT 0x1 +#define BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd_MASK 0x4 +#define BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd__SHIFT 0x2 +#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x8 +#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x3 +#define BIF_PWDN_STATUS__BU_REG_pw_status_MASK 0x1 +#define BIF_PWDN_STATUS__BU_REG_pw_status__SHIFT 0x0 +#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK 0x2 +#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status__SHIFT 0x1 +#define BIF_PWDN_STATUS__SMBUS_REG_pw_status_MASK 0x4 +#define BIF_PWDN_STATUS__SMBUS_REG_pw_status__SHIFT 0x2 +#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x8 +#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x3 +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer_MASK 0xff +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer__SHIFT 0x0 +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer_MASK 0xf00 +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer__SHIFT 0x8 +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer_MASK 0xff0000 +#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer__SHIFT 0x10 +#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout_MASK 0x1000000 +#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout__SHIFT 0x18 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer_MASK 0xff +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer__SHIFT 0x0 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer_MASK 0xf00 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer__SHIFT 0x8 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer_MASK 0xff0000 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer__SHIFT 0x10 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout_MASK 0x1000000 +#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout__SHIFT 0x18 +#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer_MASK 0xff +#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer__SHIFT 0x0 +#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer_MASK 0xf00 +#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer__SHIFT 0x8 +#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer_MASK 0xff0000 +#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer__SHIFT 0x10 +#define BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout_MASK 0x1000000 +#define BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout__SHIFT 0x18 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10 +#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000 +#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18 +#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1 +#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0 +#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x1 +#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x0 +#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe +#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x1 +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x10 +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x4 +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe0 +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x5 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_MASK 0x1e +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL__SHIFT 0x1 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN_MASK 0x20 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN__SHIFT 0x5 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD_MASK 0x3c0 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD__SHIFT 0x6 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD_MASK 0x400 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD__SHIFT 0xa +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU_MASK 0x7800 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU__SHIFT 0xb +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU_MASK 0x8000 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU__SHIFT 0xf +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN_MASK 0x10000 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN__SHIFT 0x10 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM_MASK 0x20000 +#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM__SHIFT 0x11 +#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE_MASK 0x1 +#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE__SHIFT 0x0 +#define BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK 0x2 +#define BIF_IMPCTL_SMPLCNTL__RxPDNB__SHIFT 0x1 +#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd_MASK 0x4 +#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT 0x2 +#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu_MASK 0x8 +#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu__SHIFT 0x3 +#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD_MASK 0x1f00 +#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD__SHIFT 0x8 +#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES_MASK 0x2000 +#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES__SHIFT 0xd +#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE_MASK 0x4000 +#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE__SHIFT 0xe +#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME_MASK 0xf8000 +#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME__SHIFT 0xf +#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH_MASK 0x3f00000 +#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH__SHIFT 0x14 +#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH_MASK 0xfc000000 +#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH__SHIFT 0x1a +#define BIF_IMPCTL_RXCNTL__RX_ADJUST_MASK 0x7 +#define BIF_IMPCTL_RXCNTL__RX_ADJUST__SHIFT 0x0 +#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH_MASK 0x8 +#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH__SHIFT 0x3 +#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT_MASK 0x10 +#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT__SHIFT 0x4 +#define BIF_IMPCTL_RXCNTL__SUSPEND_MASK 0x40 +#define BIF_IMPCTL_RXCNTL__SUSPEND__SHIFT 0x6 +#define BIF_IMPCTL_RXCNTL__FORCE_RST_MASK 0x80 +#define BIF_IMPCTL_RXCNTL__FORCE_RST__SHIFT 0x7 +#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH_MASK 0xf00 +#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH__SHIFT 0x8 +#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_MASK 0x1000 +#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ__SHIFT 0xc +#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH_MASK 0x1e000 +#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH__SHIFT 0xd +#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_MASK 0x20000 +#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ__SHIFT 0x11 +#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED_MASK 0x40000 +#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED__SHIFT 0x12 +#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL_MASK 0x80000 +#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL__SHIFT 0x13 +#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_MASK 0xf00000 +#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK__SHIFT 0x14 +#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG_MASK 0x10000000 +#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG__SHIFT 0x1c +#define BIF_IMPCTL_RXCNTL__CAL_DONE_MASK 0x20000000 +#define BIF_IMPCTL_RXCNTL__CAL_DONE__SHIFT 0x1d +#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd_MASK 0x7 +#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd__SHIFT 0x0 +#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd_MASK 0x8 +#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd__SHIFT 0x3 +#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd_MASK 0xf00 +#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd__SHIFT 0x8 +#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd_MASK 0x1000 +#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd__SHIFT 0xc +#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd_MASK 0x1e000 +#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd__SHIFT 0xd +#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd_MASK 0x20000 +#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd__SHIFT 0x11 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd_MASK 0x40000 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd__SHIFT 0x12 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd_MASK 0x80000 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd__SHIFT 0x13 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd_MASK 0xf00000 +#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd__SHIFT 0x14 +#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd_MASK 0x10000000 +#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd__SHIFT 0x1c +#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu_MASK 0x7 +#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu__SHIFT 0x0 +#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu_MASK 0x8 +#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu__SHIFT 0x3 +#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu_MASK 0xf00 +#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu__SHIFT 0x8 +#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu_MASK 0x1000 +#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu__SHIFT 0xc +#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu_MASK 0x1e000 +#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu__SHIFT 0xd +#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu_MASK 0x20000 +#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu__SHIFT 0x11 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu_MASK 0x40000 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu__SHIFT 0x12 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu_MASK 0x80000 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu__SHIFT 0x13 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu_MASK 0xf00000 +#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu__SHIFT 0x14 +#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu_MASK 0x10000000 +#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu__SHIFT 0x1c +#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD_MASK 0xffffffff +#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD__SHIFT 0x0 + +#endif /* BIF_5_0_SH_MASK_H */ -- cgit v1.2.3 From 3e5343bd7c33f3ec00758d5ed8fa1c868eb2fc37 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:16:08 -0400 Subject: drm/amdgpu: add BIF 5.1 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the BIF (Bus InterFace) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h | 3577 ++ .../drm/amd/include/asic_reg/bif/bif_5_1_enum.h | 1068 + .../drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h | 33080 +++++++++++++++++++ 3 files changed, 37725 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h new file mode 100644 index 000000000000..b52c9aaa5581 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h @@ -0,0 +1,3577 @@ +/* + * BIF_5_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_5_1_D_H +#define BIF_5_1_D_H + +#define mmMM_INDEX 0x0 +#define mmMM_INDEX_HI 0x6 +#define mmMM_DATA 0x1 +#define mmBIF_MM_INDACCESS_CNTL 0x1500 +#define mmBUS_CNTL 0x1508 +#define mmCONFIG_CNTL 0x1509 +#define mmCONFIG_MEMSIZE 0x150a +#define mmCONFIG_F0_BASE 0x150b +#define mmCONFIG_APER_SIZE 0x150c +#define mmCONFIG_REG_APER_SIZE 0x150d +#define mmBIF_SCRATCH0 0x150e +#define mmBIF_SCRATCH1 0x150f +#define mmBX_RESET_EN 0x1514 +#define mmMM_CFGREGS_CNTL 0x1513 +#define mmHW_DEBUG 0x1515 +#define mmMASTER_CREDIT_CNTL 0x1516 +#define mmSLAVE_REQ_CREDIT_CNTL 0x1517 +#define mmBX_RESET_CNTL 0x1518 +#define mmINTERRUPT_CNTL 0x151a +#define mmINTERRUPT_CNTL2 0x151b +#define mmBIF_DEBUG_CNTL 0x151c +#define mmBIF_DEBUG_MUX 0x151d +#define mmBIF_DEBUG_OUT 0x151e +#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 +#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 +#define mmCLKREQB_PAD_CNTL 0x1521 +#define mmSMBDAT_PAD_CNTL 0x1522 +#define mmSMBCLK_PAD_CNTL 0x1523 +#define mmBIF_XDMA_LO 0x14c0 +#define mmBIF_XDMA_HI 0x14c1 +#define mmBIF_FEATURES_CONTROL_MISC 0x14c2 +#define mmBIF_DOORBELL_CNTL 0x14c3 +#define mmBIF_SLVARB_MODE 0x14c4 +#define mmBIF_FB_EN 0x1524 +#define mmBIF_BUSNUM_CNTL1 0x1525 +#define mmBIF_BUSNUM_LIST0 0x1526 +#define mmBIF_BUSNUM_LIST1 0x1527 +#define mmBIF_BUSNUM_CNTL2 0x152b +#define mmBIF_BUSY_DELAY_CNTR 0x1529 +#define mmBIF_PERFMON_CNTL 0x152c +#define mmBIF_PERFCOUNTER0_RESULT 0x152d +#define mmBIF_PERFCOUNTER1_RESULT 0x152e +#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 +#define mmGPU_HDP_FLUSH_REQ 0x1537 +#define mmGPU_HDP_FLUSH_DONE 0x1538 +#define mmSLAVE_HANG_ERROR 0x153b +#define mmCAPTURE_HOST_BUSNUM 0x153c +#define mmHOST_BUSNUM 0x153d +#define mmPEER_REG_RANGE0 0x153e +#define mmPEER_REG_RANGE1 0x153f +#define mmPEER0_FB_OFFSET_HI 0x14f3 +#define mmPEER0_FB_OFFSET_LO 0x14f2 +#define mmPEER1_FB_OFFSET_HI 0x14f1 +#define mmPEER1_FB_OFFSET_LO 0x14f0 +#define mmPEER2_FB_OFFSET_HI 0x14ef +#define mmPEER2_FB_OFFSET_LO 0x14ee +#define mmPEER3_FB_OFFSET_HI 0x14ed +#define mmPEER3_FB_OFFSET_LO 0x14ec +#define mmDBG_BYPASS_SRBM_ACCESS 0x14eb +#define mmSMBUS_BACO_DUMMY 0x14c6 +#define mmBIF_DEVFUNCNUM_LIST0 0x14e8 +#define mmBIF_DEVFUNCNUM_LIST1 0x14e7 +#define mmBACO_CNTL 0x14e5 +#define mmBF_ANA_ISO_CNTL 0x14c7 +#define mmMEM_TYPE_CNTL 0x14e4 +#define mmBIF_BACO_DEBUG 0x14df +#define mmBIF_BACO_DEBUG_LATCH 0x14dc +#define mmBACO_CNTL_MISC 0x14db +#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8 +#define mmBIF_VDDGFX_GFX0_LOWER 0x1428 +#define mmBIF_VDDGFX_GFX0_UPPER 0x1429 +#define mmBIF_VDDGFX_GFX1_LOWER 0x142a +#define mmBIF_VDDGFX_GFX1_UPPER 0x142b +#define mmBIF_VDDGFX_GFX2_LOWER 0x142c +#define mmBIF_VDDGFX_GFX2_UPPER 0x142d +#define mmBIF_VDDGFX_GFX3_LOWER 0x142e +#define mmBIF_VDDGFX_GFX3_UPPER 0x142f +#define mmBIF_VDDGFX_GFX4_LOWER 0x1430 +#define mmBIF_VDDGFX_GFX4_UPPER 0x1431 +#define mmBIF_VDDGFX_GFX5_LOWER 0x1432 +#define mmBIF_VDDGFX_GFX5_UPPER 0x1433 +#define mmBIF_VDDGFX_RSV1_LOWER 0x1434 +#define mmBIF_VDDGFX_RSV1_UPPER 0x1435 +#define mmBIF_VDDGFX_RSV2_LOWER 0x1436 +#define mmBIF_VDDGFX_RSV2_UPPER 0x1437 +#define mmBIF_VDDGFX_RSV3_LOWER 0x1438 +#define mmBIF_VDDGFX_RSV3_UPPER 0x1439 +#define mmBIF_VDDGFX_RSV4_LOWER 0x143a +#define mmBIF_VDDGFX_RSV4_UPPER 0x143b +#define mmBIF_VDDGFX_FB_CMP 0x143c +#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc +#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd +#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe +#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff +#define mmBIF_SMU_INDEX 0x143d +#define mmBIF_SMU_DATA 0x143e +#define mmIMPCTL_RESET 0x14f5 +#define mmGARLIC_FLUSH_CNTL 0x1401 +#define mmGARLIC_FLUSH_ADDR_START_0 0x1402 +#define mmGARLIC_FLUSH_ADDR_START_1 0x1404 +#define mmGARLIC_FLUSH_ADDR_START_2 0x1406 +#define mmGARLIC_FLUSH_ADDR_START_3 0x1408 +#define mmGARLIC_FLUSH_ADDR_START_4 0x140a +#define mmGARLIC_FLUSH_ADDR_START_5 0x140c +#define mmGARLIC_FLUSH_ADDR_START_6 0x140e +#define mmGARLIC_FLUSH_ADDR_START_7 0x1410 +#define mmGARLIC_FLUSH_ADDR_END_0 0x1403 +#define mmGARLIC_FLUSH_ADDR_END_1 0x1405 +#define mmGARLIC_FLUSH_ADDR_END_2 0x1407 +#define mmGARLIC_FLUSH_ADDR_END_3 0x1409 +#define mmGARLIC_FLUSH_ADDR_END_4 0x140b +#define mmGARLIC_FLUSH_ADDR_END_5 0x140d +#define mmGARLIC_FLUSH_ADDR_END_6 0x140f +#define mmGARLIC_FLUSH_ADDR_END_7 0x1411 +#define mmGARLIC_FLUSH_REQ 0x1412 +#define mmGPU_GARLIC_FLUSH_REQ 0x1413 +#define mmGPU_GARLIC_FLUSH_DONE 0x1414 +#define mmGARLIC_COHE_CP_RB0_WPTR 0x1415 +#define mmGARLIC_COHE_CP_RB1_WPTR 0x1416 +#define mmGARLIC_COHE_CP_RB2_WPTR 0x1417 +#define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418 +#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419 +#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a +#define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b +#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c +#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d +#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e +#define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f +#define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420 +#define mmGARLIC_COHE_VCE_RB_WPTR 0x1421 +#define mmGARLIC_COHE_SDMA2_GFX_RB_WPTR 0x1422 +#define mmGARLIC_COHE_SDMA3_GFX_RB_WPTR 0x1423 +#define mmGARLIC_COHE_CP_DMA_PIO_COMMAND 0x1424 +#define mmGARLIC_COHE_GARLIC_FLUSH_REQ 0x1425 +#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426 +#define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427 +#define mmBIOS_SCRATCH_0 0x5c9 +#define mmBIOS_SCRATCH_1 0x5ca +#define mmBIOS_SCRATCH_2 0x5cb +#define mmBIOS_SCRATCH_3 0x5cc +#define mmBIOS_SCRATCH_4 0x5cd +#define mmBIOS_SCRATCH_5 0x5ce +#define mmBIOS_SCRATCH_6 0x5cf +#define mmBIOS_SCRATCH_7 0x5d0 +#define mmBIOS_SCRATCH_8 0x5d1 +#define mmBIOS_SCRATCH_9 0x5d2 +#define mmBIOS_SCRATCH_10 0x5d3 +#define mmBIOS_SCRATCH_11 0x5d4 +#define mmBIOS_SCRATCH_12 0x5d5 +#define mmBIOS_SCRATCH_13 0x5d6 +#define mmBIOS_SCRATCH_14 0x5d7 +#define mmBIOS_SCRATCH_15 0x5d8 +#define mmBIF_RB_CNTL 0x1530 +#define mmBIF_RB_BASE 0x1531 +#define mmBIF_RB_RPTR 0x1532 +#define mmBIF_RB_WPTR 0x1533 +#define mmBIF_RB_WPTR_ADDR_HI 0x1534 +#define mmBIF_RB_WPTR_ADDR_LO 0x1535 +#define mmVENDOR_ID 0x0 +#define mmDEVICE_ID 0x0 +#define mmCOMMAND 0x1 +#define mmSTATUS 0x1 +#define mmREVISION_ID 0x2 +#define mmPROG_INTERFACE 0x2 +#define mmSUB_CLASS 0x2 +#define mmBASE_CLASS 0x2 +#define mmCACHE_LINE 0x3 +#define mmLATENCY 0x3 +#define mmHEADER 0x3 +#define mmBIST 0x3 +#define mmBASE_ADDR_1 0x4 +#define mmBASE_ADDR_2 0x5 +#define mmBASE_ADDR_3 0x6 +#define mmBASE_ADDR_4 0x7 +#define mmBASE_ADDR_5 0x8 +#define mmBASE_ADDR_6 0x9 +#define mmROM_BASE_ADDR 0xc +#define mmCAP_PTR 0xd +#define mmINTERRUPT_LINE 0xf +#define mmINTERRUPT_PIN 0xf +#define mmADAPTER_ID 0xb +#define mmMIN_GRANT 0xf +#define mmMAX_LATENCY 0xf +#define mmVENDOR_CAP_LIST 0x12 +#define mmADAPTER_ID_W 0x13 +#define mmPMI_CAP_LIST 0x14 +#define mmPMI_CAP 0x14 +#define mmPMI_STATUS_CNTL 0x15 +#define mmPCIE_CAP_LIST 0x16 +#define mmPCIE_CAP 0x16 +#define mmDEVICE_CAP 0x17 +#define mmDEVICE_CNTL 0x18 +#define mmDEVICE_STATUS 0x18 +#define mmLINK_CAP 0x19 +#define mmLINK_CNTL 0x1a +#define mmLINK_STATUS 0x1a +#define mmDEVICE_CAP2 0x1f +#define mmDEVICE_CNTL2 0x20 +#define mmDEVICE_STATUS2 0x20 +#define mmLINK_CAP2 0x21 +#define mmLINK_CNTL2 0x22 +#define mmLINK_STATUS2 0x22 +#define mmMSI_CAP_LIST 0x28 +#define mmMSI_MSG_CNTL 0x28 +#define mmMSI_MSG_ADDR_LO 0x29 +#define mmMSI_MSG_ADDR_HI 0x2a +#define mmMSI_MSG_DATA_64 0x2b +#define mmMSI_MSG_DATA 0x2a +#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40 +#define mmPCIE_VENDOR_SPECIFIC_HDR 0x41 +#define mmPCIE_VENDOR_SPECIFIC1 0x42 +#define mmPCIE_VENDOR_SPECIFIC2 0x43 +#define mmPCIE_VC_ENH_CAP_LIST 0x44 +#define mmPCIE_PORT_VC_CAP_REG1 0x45 +#define mmPCIE_PORT_VC_CAP_REG2 0x46 +#define mmPCIE_PORT_VC_CNTL 0x47 +#define mmPCIE_PORT_VC_STATUS 0x47 +#define mmPCIE_VC0_RESOURCE_CAP 0x48 +#define mmPCIE_VC0_RESOURCE_CNTL 0x49 +#define mmPCIE_VC0_RESOURCE_STATUS 0x4a +#define mmPCIE_VC1_RESOURCE_CAP 0x4b +#define mmPCIE_VC1_RESOURCE_CNTL 0x4c +#define mmPCIE_VC1_RESOURCE_STATUS 0x4d +#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50 +#define mmPCIE_DEV_SERIAL_NUM_DW1 0x51 +#define mmPCIE_DEV_SERIAL_NUM_DW2 0x52 +#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54 +#define mmPCIE_UNCORR_ERR_STATUS 0x55 +#define mmPCIE_UNCORR_ERR_MASK 0x56 +#define mmPCIE_UNCORR_ERR_SEVERITY 0x57 +#define mmPCIE_CORR_ERR_STATUS 0x58 +#define mmPCIE_CORR_ERR_MASK 0x59 +#define mmPCIE_ADV_ERR_CAP_CNTL 0x5a +#define mmPCIE_HDR_LOG0 0x5b +#define mmPCIE_HDR_LOG1 0x5c +#define mmPCIE_HDR_LOG2 0x5d +#define mmPCIE_HDR_LOG3 0x5e +#define mmPCIE_TLP_PREFIX_LOG0 0x62 +#define mmPCIE_TLP_PREFIX_LOG1 0x63 +#define mmPCIE_TLP_PREFIX_LOG2 0x64 +#define mmPCIE_TLP_PREFIX_LOG3 0x65 +#define mmPCIE_BAR_ENH_CAP_LIST 0x80 +#define mmPCIE_BAR1_CAP 0x81 +#define mmPCIE_BAR1_CNTL 0x82 +#define mmPCIE_BAR2_CAP 0x83 +#define mmPCIE_BAR2_CNTL 0x84 +#define mmPCIE_BAR3_CAP 0x85 +#define mmPCIE_BAR3_CNTL 0x86 +#define mmPCIE_BAR4_CAP 0x87 +#define mmPCIE_BAR4_CNTL 0x88 +#define mmPCIE_BAR5_CAP 0x89 +#define mmPCIE_BAR5_CNTL 0x8a +#define mmPCIE_BAR6_CAP 0x8b +#define mmPCIE_BAR6_CNTL 0x8c +#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90 +#define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91 +#define mmPCIE_PWR_BUDGET_DATA 0x92 +#define mmPCIE_PWR_BUDGET_CAP 0x93 +#define mmPCIE_DPA_ENH_CAP_LIST 0x94 +#define mmPCIE_DPA_CAP 0x95 +#define mmPCIE_DPA_LATENCY_INDICATOR 0x96 +#define mmPCIE_DPA_STATUS 0x97 +#define mmPCIE_DPA_CNTL 0x97 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99 +#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99 +#define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c +#define mmPCIE_LINK_CNTL3 0x9d +#define mmPCIE_LANE_ERROR_STATUS 0x9e +#define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f +#define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f +#define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0 +#define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0 +#define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1 +#define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1 +#define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2 +#define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2 +#define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3 +#define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3 +#define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4 +#define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4 +#define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5 +#define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5 +#define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6 +#define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6 +#define mmPCIE_ACS_ENH_CAP_LIST 0xa8 +#define mmPCIE_ACS_CAP 0xa9 +#define mmPCIE_ACS_CNTL 0xa9 +#define mmPCIE_ATS_ENH_CAP_LIST 0xac +#define mmPCIE_ATS_CAP 0xad +#define mmPCIE_ATS_CNTL 0xad +#define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0 +#define mmPCIE_PAGE_REQ_CNTL 0xb1 +#define mmPCIE_PAGE_REQ_STATUS 0xb1 +#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2 +#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3 +#define mmPCIE_PASID_ENH_CAP_LIST 0xb4 +#define mmPCIE_PASID_CAP 0xb5 +#define mmPCIE_PASID_CNTL 0xb5 +#define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8 +#define mmPCIE_TPH_REQR_CAP 0xb9 +#define mmPCIE_TPH_REQR_CNTL 0xba +#define mmPCIE_MC_ENH_CAP_LIST 0xbc +#define mmPCIE_MC_CAP 0xbd +#define mmPCIE_MC_CNTL 0xbd +#define mmPCIE_MC_ADDR0 0xbe +#define mmPCIE_MC_ADDR1 0xbf +#define mmPCIE_MC_RCV0 0xc0 +#define mmPCIE_MC_RCV1 0xc1 +#define mmPCIE_MC_BLOCK_ALL0 0xc2 +#define mmPCIE_MC_BLOCK_ALL1 0xc3 +#define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4 +#define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5 +#define mmPCIE_LTR_ENH_CAP_LIST 0xc8 +#define mmPCIE_LTR_CAP 0xc9 +#define ixMM_INDEX_IND 0x1090000 +#define ixMM_INDEX_HI_IND 0x1090006 +#define ixMM_DATA_IND 0x1090001 +#define ixBIF_MM_INDACCESS_CNTL_IND 0x1091500 +#define ixBUS_CNTL_IND 0x1091508 +#define ixCONFIG_CNTL_IND 0x1091509 +#define ixCONFIG_MEMSIZE_IND 0x109150a +#define ixCONFIG_F0_BASE_IND 0x109150b +#define ixCONFIG_APER_SIZE_IND 0x109150c +#define ixCONFIG_REG_APER_SIZE_IND 0x109150d +#define ixBIF_SCRATCH0_IND 0x109150e +#define ixBIF_SCRATCH1_IND 0x109150f +#define ixBX_RESET_EN_IND 0x1091514 +#define ixMM_CFGREGS_CNTL_IND 0x1091513 +#define ixHW_DEBUG_IND 0x1091515 +#define ixMASTER_CREDIT_CNTL_IND 0x1091516 +#define ixSLAVE_REQ_CREDIT_CNTL_IND 0x1091517 +#define ixBX_RESET_CNTL_IND 0x1091518 +#define ixINTERRUPT_CNTL_IND 0x109151a +#define ixINTERRUPT_CNTL2_IND 0x109151b +#define ixBIF_DEBUG_CNTL_IND 0x109151c +#define ixBIF_DEBUG_MUX_IND 0x109151d +#define ixBIF_DEBUG_OUT_IND 0x109151e +#define ixHDP_REG_COHERENCY_FLUSH_CNTL_IND 0x1091528 +#define ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND 0x1091520 +#define ixCLKREQB_PAD_CNTL_IND 0x1091521 +#define ixSMBDAT_PAD_CNTL_IND 0x1091522 +#define ixSMBCLK_PAD_CNTL_IND 0x1091523 +#define ixBIF_XDMA_LO_IND 0x10914c0 +#define ixBIF_XDMA_HI_IND 0x10914c1 +#define ixBIF_FEATURES_CONTROL_MISC_IND 0x10914c2 +#define ixBIF_DOORBELL_CNTL_IND 0x10914c3 +#define ixBIF_SLVARB_MODE_IND 0x10914c4 +#define ixBIF_FB_EN_IND 0x1091524 +#define ixBIF_BUSNUM_CNTL1_IND 0x1091525 +#define ixBIF_BUSNUM_LIST0_IND 0x1091526 +#define ixBIF_BUSNUM_LIST1_IND 0x1091527 +#define ixBIF_BUSNUM_CNTL2_IND 0x109152b +#define ixBIF_BUSY_DELAY_CNTR_IND 0x1091529 +#define ixBIF_PERFMON_CNTL_IND 0x109152c +#define ixBIF_PERFCOUNTER0_RESULT_IND 0x109152d +#define ixBIF_PERFCOUNTER1_RESULT_IND 0x109152e +#define ixSLAVE_HANG_PROTECTION_CNTL_IND 0x1091536 +#define ixGPU_HDP_FLUSH_REQ_IND 0x1091537 +#define ixGPU_HDP_FLUSH_DONE_IND 0x1091538 +#define ixSLAVE_HANG_ERROR_IND 0x109153b +#define ixCAPTURE_HOST_BUSNUM_IND 0x109153c +#define ixHOST_BUSNUM_IND 0x109153d +#define ixPEER_REG_RANGE0_IND 0x109153e +#define ixPEER_REG_RANGE1_IND 0x109153f +#define ixPEER0_FB_OFFSET_HI_IND 0x10914f3 +#define ixPEER0_FB_OFFSET_LO_IND 0x10914f2 +#define ixPEER1_FB_OFFSET_HI_IND 0x10914f1 +#define ixPEER1_FB_OFFSET_LO_IND 0x10914f0 +#define ixPEER2_FB_OFFSET_HI_IND 0x10914ef +#define ixPEER2_FB_OFFSET_LO_IND 0x10914ee +#define ixPEER3_FB_OFFSET_HI_IND 0x10914ed +#define ixPEER3_FB_OFFSET_LO_IND 0x10914ec +#define ixDBG_BYPASS_SRBM_ACCESS_IND 0x10914eb +#define ixSMBUS_BACO_DUMMY_IND 0x10914c6 +#define ixBIF_DEVFUNCNUM_LIST0_IND 0x10914e8 +#define ixBIF_DEVFUNCNUM_LIST1_IND 0x10914e7 +#define ixBACO_CNTL_IND 0x10914e5 +#define ixBF_ANA_ISO_CNTL_IND 0x10914c7 +#define ixMEM_TYPE_CNTL_IND 0x10914e4 +#define ixBIF_BACO_DEBUG_IND 0x10914df +#define ixBIF_BACO_DEBUG_LATCH_IND 0x10914dc +#define ixBACO_CNTL_MISC_IND 0x10914db +#define ixSMU_BIF_VDDGFX_PWR_STATUS_IND 0x10914f8 +#define ixBIF_VDDGFX_GFX0_LOWER_IND 0x1091428 +#define ixBIF_VDDGFX_GFX0_UPPER_IND 0x1091429 +#define ixBIF_VDDGFX_GFX1_LOWER_IND 0x109142a +#define ixBIF_VDDGFX_GFX1_UPPER_IND 0x109142b +#define ixBIF_VDDGFX_GFX2_LOWER_IND 0x109142c +#define ixBIF_VDDGFX_GFX2_UPPER_IND 0x109142d +#define ixBIF_VDDGFX_GFX3_LOWER_IND 0x109142e +#define ixBIF_VDDGFX_GFX3_UPPER_IND 0x109142f +#define ixBIF_VDDGFX_GFX4_LOWER_IND 0x1091430 +#define ixBIF_VDDGFX_GFX4_UPPER_IND 0x1091431 +#define ixBIF_VDDGFX_GFX5_LOWER_IND 0x1091432 +#define ixBIF_VDDGFX_GFX5_UPPER_IND 0x1091433 +#define ixBIF_VDDGFX_RSV1_LOWER_IND 0x1091434 +#define ixBIF_VDDGFX_RSV1_UPPER_IND 0x1091435 +#define ixBIF_VDDGFX_RSV2_LOWER_IND 0x1091436 +#define ixBIF_VDDGFX_RSV2_UPPER_IND 0x1091437 +#define ixBIF_VDDGFX_RSV3_LOWER_IND 0x1091438 +#define ixBIF_VDDGFX_RSV3_UPPER_IND 0x1091439 +#define ixBIF_VDDGFX_RSV4_LOWER_IND 0x109143a +#define ixBIF_VDDGFX_RSV4_UPPER_IND 0x109143b +#define ixBIF_VDDGFX_FB_CMP_IND 0x109143c +#define ixBIF_DOORBELL_GBLAPER1_LOWER_IND 0x10914fc +#define ixBIF_DOORBELL_GBLAPER1_UPPER_IND 0x10914fd +#define ixBIF_DOORBELL_GBLAPER2_LOWER_IND 0x10914fe +#define ixBIF_DOORBELL_GBLAPER2_UPPER_IND 0x10914ff +#define ixBIF_SMU_INDEX_IND 0x109143d +#define ixBIF_SMU_DATA_IND 0x109143e +#define ixIMPCTL_RESET_IND 0x10914f5 +#define ixGARLIC_FLUSH_CNTL_IND 0x1091401 +#define ixGARLIC_FLUSH_REQ_IND 0x1091412 +#define ixGPU_GARLIC_FLUSH_REQ_IND 0x1091413 +#define ixGPU_GARLIC_FLUSH_DONE_IND 0x1091414 +#define ixGARLIC_COHE_CP_RB0_WPTR_IND 0x1091415 +#define ixGARLIC_COHE_CP_RB1_WPTR_IND 0x1091416 +#define ixGARLIC_COHE_CP_RB2_WPTR_IND 0x1091417 +#define ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND 0x1091418 +#define ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND 0x1091419 +#define ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND 0x109141a +#define ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND 0x109141b +#define ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND 0x109141c +#define ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND 0x109141d +#define ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND 0x109141e +#define ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND 0x109141f +#define ixGARLIC_COHE_VCE_RB_WPTR2_IND 0x1091420 +#define ixGARLIC_COHE_VCE_RB_WPTR_IND 0x1091421 +#define ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND 0x1091422 +#define ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND 0x1091423 +#define ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND 0x1091424 +#define ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND 0x1091425 +#define ixREMAP_HDP_MEM_FLUSH_CNTL_IND 0x1091426 +#define ixREMAP_HDP_REG_FLUSH_CNTL_IND 0x1091427 +#define ixBIOS_SCRATCH_0_IND 0x10905c9 +#define ixBIOS_SCRATCH_1_IND 0x10905ca +#define ixBIOS_SCRATCH_2_IND 0x10905cb +#define ixBIOS_SCRATCH_3_IND 0x10905cc +#define ixBIOS_SCRATCH_4_IND 0x10905cd +#define ixBIOS_SCRATCH_5_IND 0x10905ce +#define ixBIOS_SCRATCH_6_IND 0x10905cf +#define ixBIOS_SCRATCH_7_IND 0x10905d0 +#define ixBIOS_SCRATCH_8_IND 0x10905d1 +#define ixBIOS_SCRATCH_9_IND 0x10905d2 +#define ixBIOS_SCRATCH_10_IND 0x10905d3 +#define ixBIOS_SCRATCH_11_IND 0x10905d4 +#define ixBIOS_SCRATCH_12_IND 0x10905d5 +#define ixBIOS_SCRATCH_13_IND 0x10905d6 +#define ixBIOS_SCRATCH_14_IND 0x10905d7 +#define ixBIOS_SCRATCH_15_IND 0x10905d8 +#define ixBIF_RB_CNTL_IND 0x1091530 +#define ixBIF_RB_BASE_IND 0x1091531 +#define ixBIF_RB_RPTR_IND 0x1091532 +#define ixBIF_RB_WPTR_IND 0x1091533 +#define ixBIF_RB_WPTR_ADDR_HI_IND 0x1091534 +#define ixBIF_RB_WPTR_ADDR_LO_IND 0x1091535 +#define mmNB_GBIF_INDEX 0x34 +#define mmNB_GBIF_DATA 0x35 +#define mmPCIE_INDEX 0xe +#define mmPCIE_DATA 0xf +#define mmPCIE_INDEX_2 0xc +#define mmPCIE_DATA_2 0xd +#define ixPCIE_RESERVED 0x1400000 +#define ixPCIE_SCRATCH 0x1400001 +#define ixPCIE_HW_DEBUG 0x1400002 +#define ixPCIE_RX_NUM_NAK 0x140000e +#define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f +#define ixPCIE_CNTL 0x1400010 +#define ixPCIE_CONFIG_CNTL 0x1400011 +#define ixPCIE_DEBUG_CNTL 0x1400012 +#define ixPCIE_INT_CNTL 0x140001a +#define ixPCIE_INT_STATUS 0x140001b +#define ixPCIE_CNTL2 0x140001c +#define ixPCIE_RX_CNTL2 0x140001d +#define ixPCIE_TX_F0_ATTR_CNTL 0x140001e +#define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f +#define ixPCIE_CI_CNTL 0x1400020 +#define ixPCIE_BUS_CNTL 0x1400021 +#define ixPCIE_LC_STATE6 0x1400022 +#define ixPCIE_LC_STATE7 0x1400023 +#define ixPCIE_LC_STATE8 0x1400024 +#define ixPCIE_LC_STATE9 0x1400025 +#define ixPCIE_LC_STATE10 0x1400026 +#define ixPCIE_LC_STATE11 0x1400027 +#define ixPCIE_LC_STATUS1 0x1400028 +#define ixPCIE_LC_STATUS2 0x1400029 +#define ixPCIE_WPR_CNTL 0x1400030 +#define ixPCIE_RX_LAST_TLP0 0x1400031 +#define ixPCIE_RX_LAST_TLP1 0x1400032 +#define ixPCIE_RX_LAST_TLP2 0x1400033 +#define ixPCIE_RX_LAST_TLP3 0x1400034 +#define ixPCIE_TX_LAST_TLP0 0x1400035 +#define ixPCIE_TX_LAST_TLP1 0x1400036 +#define ixPCIE_TX_LAST_TLP2 0x1400037 +#define ixPCIE_TX_LAST_TLP3 0x1400038 +#define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a +#define ixPCIE_I2C_REG_DATA 0x140003b +#define ixPCIE_CFG_CNTL 0x140003c +#define ixPCIE_P_CNTL 0x1400040 +#define ixPCIE_P_BUF_STATUS 0x1400041 +#define ixPCIE_P_DECODER_STATUS 0x1400042 +#define ixPCIE_P_MISC_STATUS 0x1400043 +#define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050 +#define ixPCIE_OBFF_CNTL 0x1400061 +#define ixPCIE_TX_LTR_CNTL 0x1400060 +#define ixPCIE_PERF_COUNT_CNTL 0x1400080 +#define ixPCIE_PERF_CNTL_TXCLK 0x1400081 +#define ixPCIE_PERF_COUNT0_TXCLK 0x1400082 +#define ixPCIE_PERF_COUNT1_TXCLK 0x1400083 +#define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084 +#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085 +#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086 +#define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087 +#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088 +#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089 +#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a +#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b +#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c +#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d +#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e +#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f +#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 +#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 +#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 +#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 +#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 +#define ixPCIE_PERF_CNTL_TXCLK2 0x1400095 +#define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096 +#define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097 +#define ixPCIE_STRAP_F0 0x14000b0 +#define ixPCIE_STRAP_F1 0x14000b1 +#define ixPCIE_STRAP_F2 0x14000b2 +#define ixPCIE_STRAP_F3 0x14000b3 +#define ixPCIE_STRAP_F4 0x14000b4 +#define ixPCIE_STRAP_F5 0x14000b5 +#define ixPCIE_STRAP_F6 0x14000b6 +#define ixPCIE_STRAP_F7 0x14000b7 +#define ixPCIE_STRAP_MISC 0x14000c0 +#define ixPCIE_STRAP_MISC2 0x14000c1 +#define ixPCIE_STRAP_PI 0x14000c2 +#define ixPCIE_STRAP_I2C_BD 0x14000c4 +#define ixPCIE_PRBS_CLR 0x14000c8 +#define ixPCIE_PRBS_STATUS1 0x14000c9 +#define ixPCIE_PRBS_STATUS2 0x14000ca +#define ixPCIE_PRBS_FREERUN 0x14000cb +#define ixPCIE_PRBS_MISC 0x14000cc +#define ixPCIE_PRBS_USER_PATTERN 0x14000cd +#define ixPCIE_PRBS_LO_BITCNT 0x14000ce +#define ixPCIE_PRBS_HI_BITCNT 0x14000cf +#define ixPCIE_PRBS_ERRCNT_0 0x14000d0 +#define ixPCIE_PRBS_ERRCNT_1 0x14000d1 +#define ixPCIE_PRBS_ERRCNT_2 0x14000d2 +#define ixPCIE_PRBS_ERRCNT_3 0x14000d3 +#define ixPCIE_PRBS_ERRCNT_4 0x14000d4 +#define ixPCIE_PRBS_ERRCNT_5 0x14000d5 +#define ixPCIE_PRBS_ERRCNT_6 0x14000d6 +#define ixPCIE_PRBS_ERRCNT_7 0x14000d7 +#define ixPCIE_PRBS_ERRCNT_8 0x14000d8 +#define ixPCIE_PRBS_ERRCNT_9 0x14000d9 +#define ixPCIE_PRBS_ERRCNT_10 0x14000da +#define ixPCIE_PRBS_ERRCNT_11 0x14000db +#define ixPCIE_PRBS_ERRCNT_12 0x14000dc +#define ixPCIE_PRBS_ERRCNT_13 0x14000dd +#define ixPCIE_PRBS_ERRCNT_14 0x14000de +#define ixPCIE_PRBS_ERRCNT_15 0x14000df +#define ixPCIE_F0_DPA_CAP 0x14000e0 +#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4 +#define ixPCIE_F0_DPA_CNTL 0x14000e5 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9 +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed +#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee +#define ixPCIEP_RESERVED 0x10010000 +#define ixPCIEP_SCRATCH 0x10010001 +#define ixPCIEP_HW_DEBUG 0x10010002 +#define ixPCIEP_PORT_CNTL 0x10010010 +#define ixPCIE_TX_CNTL 0x10010020 +#define ixPCIE_TX_REQUESTER_ID 0x10010021 +#define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022 +#define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023 +#define ixPCIE_TX_SEQ 0x10010024 +#define ixPCIE_TX_REPLAY 0x10010025 +#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026 +#define ixPCIE_TX_CREDITS_ADVT_P 0x10010030 +#define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031 +#define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032 +#define ixPCIE_TX_CREDITS_INIT_P 0x10010033 +#define ixPCIE_TX_CREDITS_INIT_NP 0x10010034 +#define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035 +#define ixPCIE_TX_CREDITS_STATUS 0x10010036 +#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037 +#define ixPCIE_P_PORT_LANE_STATUS 0x10010050 +#define ixPCIE_FC_P 0x10010060 +#define ixPCIE_FC_NP 0x10010061 +#define ixPCIE_FC_CPL 0x10010062 +#define ixPCIE_ERR_CNTL 0x1001006a +#define ixPCIE_RX_CNTL 0x10010070 +#define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071 +#define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072 +#define ixPCIE_RX_CNTL3 0x10010074 +#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080 +#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081 +#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082 +#define ixPCIE_LC_CNTL 0x100100a0 +#define ixPCIE_LC_CNTL2 0x100100b1 +#define ixPCIE_LC_CNTL3 0x100100b5 +#define ixPCIE_LC_CNTL4 0x100100b6 +#define ixPCIE_LC_CNTL5 0x100100b7 +#define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2 +#define ixPCIE_LC_TRAINING_CNTL 0x100100a1 +#define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2 +#define ixPCIE_LC_N_FTS_CNTL 0x100100a3 +#define ixPCIE_LC_SPEED_CNTL 0x100100a4 +#define ixPCIE_LC_CDR_CNTL 0x100100b3 +#define ixPCIE_LC_LANE_CNTL 0x100100b4 +#define ixPCIE_LC_FORCE_COEFF 0x100100b8 +#define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9 +#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba +#define ixPCIE_LC_STATE0 0x100100a5 +#define ixPCIE_LC_STATE1 0x100100a6 +#define ixPCIE_LC_STATE2 0x100100a7 +#define ixPCIE_LC_STATE3 0x100100a8 +#define ixPCIE_LC_STATE4 0x100100a9 +#define ixPCIE_LC_STATE5 0x100100aa +#define ixPCIEP_STRAP_LC 0x100100c0 +#define ixPCIEP_STRAP_MISC 0x100100c1 +#define ixPCIEP_BCH_ECC_CNTL 0x100100d0 +#define mmBIF_RFE_SNOOP_REG 0x27 +#define mmBIF_RFE_WARMRST_CNTL 0x1459 +#define mmBIF_RFE_SOFTRST_CNTL 0x1441 +#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442 +#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443 +#define mmBIF_PWDN_COMMAND 0x1444 +#define mmBIF_PWDN_STATUS 0x1445 +#define mmBIF_RFE_MST_FBU_CMDSTATUS 0x1446 +#define mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS 0x1447 +#define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448 +#define mmBIF_RFE_MST_TMOUT_STATUS 0x144b +#define mmBIF_RFE_MMCFG_CNTL 0x144c +#define ixBIF_CLOCKS_BITS_IND 0x1301489 +#define ixBIF_LNCNT_RESET_IND 0x1301488 +#define ixLNCNT_CONTROL_IND 0x1301487 +#define ixNEW_REFCLKB_TIMER_IND 0x1301485 +#define ixNEW_REFCLKB_TIMER_1_IND 0x1301484 +#define ixBIF_CLK_PDWN_DELAY_TIMER_IND 0x1301483 +#define ixBIF_RESET_EN_IND 0x1301482 +#define ixBIF_PIF_TXCLK_SWITCH_TIMER_IND 0x1301481 +#define ixBIF_BACO_MSIC_IND 0x1301480 +#define ixBIF_RESET_CNTL_IND 0x1301486 +#define ixBIF_RFE_CNTL_MISC_IND 0x130148c +#define ixBIF_MEM_PG_CNTL_IND 0x130148a +#define mmNB_GBIF_INDEX 0x34 +#define mmNB_GBIF_DATA 0x35 +#define mmBIF_CLOCKS_BITS 0x1489 +#define mmBIF_LNCNT_RESET 0x1488 +#define mmLNCNT_CONTROL 0x1487 +#define mmNEW_REFCLKB_TIMER 0x1485 +#define mmNEW_REFCLKB_TIMER_1 0x1484 +#define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483 +#define mmBIF_RESET_EN 0x1482 +#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481 +#define mmBIF_BACO_MSIC 0x1480 +#define mmBIF_RESET_CNTL 0x1486 +#define mmBIF_RFE_CNTL_MISC 0x148c +#define mmBIF_MEM_PG_CNTL 0x148a +#define mmC_PCIE_P_INDEX 0x38 +#define mmC_PCIE_P_DATA 0x39 +#define ixD2F1_PCIE_PORT_INDEX 0x2000038 +#define ixD2F1_PCIE_PORT_DATA 0x2000039 +#define ixD2F1_PCIEP_RESERVED 0x0 +#define ixD2F1_PCIEP_SCRATCH 0x1 +#define ixD2F1_PCIEP_HW_DEBUG 0x2 +#define ixD2F1_PCIEP_PORT_CNTL 0x10 +#define ixD2F1_PCIE_TX_CNTL 0x20 +#define ixD2F1_PCIE_TX_REQUESTER_ID 0x21 +#define ixD2F1_PCIE_TX_VENDOR_SPECIFIC 0x22 +#define ixD2F1_PCIE_TX_REQUEST_NUM_CNTL 0x23 +#define ixD2F1_PCIE_TX_SEQ 0x24 +#define ixD2F1_PCIE_TX_REPLAY 0x25 +#define ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT 0x26 +#define ixD2F1_PCIE_TX_CREDITS_ADVT_P 0x30 +#define ixD2F1_PCIE_TX_CREDITS_ADVT_NP 0x31 +#define ixD2F1_PCIE_TX_CREDITS_ADVT_CPL 0x32 +#define ixD2F1_PCIE_TX_CREDITS_INIT_P 0x33 +#define ixD2F1_PCIE_TX_CREDITS_INIT_NP 0x34 +#define ixD2F1_PCIE_TX_CREDITS_INIT_CPL 0x35 +#define ixD2F1_PCIE_TX_CREDITS_STATUS 0x36 +#define ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 +#define ixD2F1_PCIE_P_PORT_LANE_STATUS 0x50 +#define ixD2F1_PCIE_FC_P 0x60 +#define ixD2F1_PCIE_FC_NP 0x61 +#define ixD2F1_PCIE_FC_CPL 0x62 +#define ixD2F1_PCIE_ERR_CNTL 0x6a +#define ixD2F1_PCIE_RX_CNTL 0x70 +#define ixD2F1_PCIE_RX_EXPECTED_SEQNUM 0x71 +#define ixD2F1_PCIE_RX_VENDOR_SPECIFIC 0x72 +#define ixD2F1_PCIE_RX_CNTL3 0x74 +#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P 0x80 +#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 +#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 +#define ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL 0x83 +#define ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION 0x84 +#define ixD2F1_PCIE_LC_CNTL 0xa0 +#define ixD2F1_PCIE_LC_CNTL2 0xb1 +#define ixD2F1_PCIE_LC_CNTL3 0xb5 +#define ixD2F1_PCIE_LC_CNTL4 0xb6 +#define ixD2F1_PCIE_LC_CNTL5 0xb7 +#define ixD2F1_PCIE_LC_CNTL6 0xbb +#define ixD2F1_PCIE_LC_BW_CHANGE_CNTL 0xb2 +#define ixD2F1_PCIE_LC_TRAINING_CNTL 0xa1 +#define ixD2F1_PCIE_LC_LINK_WIDTH_CNTL 0xa2 +#define ixD2F1_PCIE_LC_N_FTS_CNTL 0xa3 +#define ixD2F1_PCIE_LC_SPEED_CNTL 0xa4 +#define ixD2F1_PCIE_LC_CDR_CNTL 0xb3 +#define ixD2F1_PCIE_LC_LANE_CNTL 0xb4 +#define ixD2F1_PCIE_LC_FORCE_COEFF 0xb8 +#define ixD2F1_PCIE_LC_BEST_EQ_SETTINGS 0xb9 +#define ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba +#define ixD2F1_PCIE_LC_STATE0 0xa5 +#define ixD2F1_PCIE_LC_STATE1 0xa6 +#define ixD2F1_PCIE_LC_STATE2 0xa7 +#define ixD2F1_PCIE_LC_STATE3 0xa8 +#define ixD2F1_PCIE_LC_STATE4 0xa9 +#define ixD2F1_PCIE_LC_STATE5 0xaa +#define ixD2F1_PCIEP_STRAP_LC 0xc0 +#define ixD2F1_PCIEP_STRAP_MISC 0xc1 +#define ixD2F1_PCIEP_BCH_ECC_CNTL 0xd0 +#define ixD2F1_PCIEP_HPGI_PRIVATE 0xd2 +#define ixD2F1_PCIEP_HPGI 0xda +#define ixD2F1_VENDOR_ID 0x2000000 +#define ixD2F1_DEVICE_ID 0x2000000 +#define ixD2F1_COMMAND 0x2000001 +#define ixD2F1_STATUS 0x2000001 +#define ixD2F1_REVISION_ID 0x2000002 +#define ixD2F1_PROG_INTERFACE 0x2000002 +#define ixD2F1_SUB_CLASS 0x2000002 +#define ixD2F1_BASE_CLASS 0x2000002 +#define ixD2F1_CACHE_LINE 0x2000003 +#define ixD2F1_LATENCY 0x2000003 +#define ixD2F1_HEADER 0x2000003 +#define ixD2F1_BIST 0x2000003 +#define ixD2F1_SUB_BUS_NUMBER_LATENCY 0x2000006 +#define ixD2F1_IO_BASE_LIMIT 0x2000007 +#define ixD2F1_SECONDARY_STATUS 0x2000007 +#define ixD2F1_MEM_BASE_LIMIT 0x2000008 +#define ixD2F1_PREF_BASE_LIMIT 0x2000009 +#define ixD2F1_PREF_BASE_UPPER 0x200000a +#define ixD2F1_PREF_LIMIT_UPPER 0x200000b +#define ixD2F1_IO_BASE_LIMIT_HI 0x200000c +#define ixD2F1_IRQ_BRIDGE_CNTL 0x200000f +#define ixD2F1_CAP_PTR 0x200000d +#define ixD2F1_INTERRUPT_LINE 0x200000f +#define ixD2F1_INTERRUPT_PIN 0x200000f +#define ixD2F1_EXT_BRIDGE_CNTL 0x2000010 +#define ixD2F1_PMI_CAP_LIST 0x2000014 +#define ixD2F1_PMI_CAP 0x2000014 +#define ixD2F1_PMI_STATUS_CNTL 0x2000015 +#define ixD2F1_PCIE_CAP_LIST 0x2000016 +#define ixD2F1_PCIE_CAP 0x2000016 +#define ixD2F1_DEVICE_CAP 0x2000017 +#define ixD2F1_DEVICE_CNTL 0x2000018 +#define ixD2F1_DEVICE_STATUS 0x2000018 +#define ixD2F1_LINK_CAP 0x2000019 +#define ixD2F1_LINK_CNTL 0x200001a +#define ixD2F1_LINK_STATUS 0x200001a +#define ixD2F1_SLOT_CAP 0x200001b +#define ixD2F1_SLOT_CNTL 0x200001c +#define ixD2F1_SLOT_STATUS 0x200001c +#define ixD2F1_ROOT_CNTL 0x200001d +#define ixD2F1_ROOT_CAP 0x200001d +#define ixD2F1_ROOT_STATUS 0x200001e +#define ixD2F1_DEVICE_CAP2 0x200001f +#define ixD2F1_DEVICE_CNTL2 0x2000020 +#define ixD2F1_DEVICE_STATUS2 0x2000020 +#define ixD2F1_LINK_CAP2 0x2000021 +#define ixD2F1_LINK_CNTL2 0x2000022 +#define ixD2F1_LINK_STATUS2 0x2000022 +#define ixD2F1_SLOT_CAP2 0x2000023 +#define ixD2F1_SLOT_CNTL2 0x2000024 +#define ixD2F1_SLOT_STATUS2 0x2000024 +#define ixD2F1_MSI_CAP_LIST 0x2000028 +#define ixD2F1_MSI_MSG_CNTL 0x2000028 +#define ixD2F1_MSI_MSG_ADDR_LO 0x2000029 +#define ixD2F1_MSI_MSG_ADDR_HI 0x200002a +#define ixD2F1_MSI_MSG_DATA_64 0x200002b +#define ixD2F1_MSI_MSG_DATA 0x200002a +#define ixD2F1_SSID_CAP_LIST 0x2000030 +#define ixD2F1_SSID_CAP 0x2000031 +#define ixD2F1_MSI_MAP_CAP_LIST 0x2000032 +#define ixD2F1_MSI_MAP_CAP 0x2000032 +#define ixD2F1_MSI_MAP_ADDR_LO 0x2000033 +#define ixD2F1_MSI_MAP_ADDR_HI 0x2000034 +#define ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x2000040 +#define ixD2F1_PCIE_VENDOR_SPECIFIC_HDR 0x2000041 +#define ixD2F1_PCIE_VENDOR_SPECIFIC1 0x2000042 +#define ixD2F1_PCIE_VENDOR_SPECIFIC2 0x2000043 +#define ixD2F1_PCIE_VC_ENH_CAP_LIST 0x2000044 +#define ixD2F1_PCIE_PORT_VC_CAP_REG1 0x2000045 +#define ixD2F1_PCIE_PORT_VC_CAP_REG2 0x2000046 +#define ixD2F1_PCIE_PORT_VC_CNTL 0x2000047 +#define ixD2F1_PCIE_PORT_VC_STATUS 0x2000047 +#define ixD2F1_PCIE_VC0_RESOURCE_CAP 0x2000048 +#define ixD2F1_PCIE_VC0_RESOURCE_CNTL 0x2000049 +#define ixD2F1_PCIE_VC0_RESOURCE_STATUS 0x200004a +#define ixD2F1_PCIE_VC1_RESOURCE_CAP 0x200004b +#define ixD2F1_PCIE_VC1_RESOURCE_CNTL 0x200004c +#define ixD2F1_PCIE_VC1_RESOURCE_STATUS 0x200004d +#define ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x2000050 +#define ixD2F1_PCIE_DEV_SERIAL_NUM_DW1 0x2000051 +#define ixD2F1_PCIE_DEV_SERIAL_NUM_DW2 0x2000052 +#define ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x2000054 +#define ixD2F1_PCIE_UNCORR_ERR_STATUS 0x2000055 +#define ixD2F1_PCIE_UNCORR_ERR_MASK 0x2000056 +#define ixD2F1_PCIE_UNCORR_ERR_SEVERITY 0x2000057 +#define ixD2F1_PCIE_CORR_ERR_STATUS 0x2000058 +#define ixD2F1_PCIE_CORR_ERR_MASK 0x2000059 +#define ixD2F1_PCIE_ADV_ERR_CAP_CNTL 0x200005a +#define ixD2F1_PCIE_HDR_LOG0 0x200005b +#define ixD2F1_PCIE_HDR_LOG1 0x200005c +#define ixD2F1_PCIE_HDR_LOG2 0x200005d +#define ixD2F1_PCIE_HDR_LOG3 0x200005e +#define ixD2F1_PCIE_ROOT_ERR_CMD 0x200005f +#define ixD2F1_PCIE_ROOT_ERR_STATUS 0x2000060 +#define ixD2F1_PCIE_ERR_SRC_ID 0x2000061 +#define ixD2F1_PCIE_TLP_PREFIX_LOG0 0x2000062 +#define ixD2F1_PCIE_TLP_PREFIX_LOG1 0x2000063 +#define ixD2F1_PCIE_TLP_PREFIX_LOG2 0x2000064 +#define ixD2F1_PCIE_TLP_PREFIX_LOG3 0x2000065 +#define ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST 0x200009c +#define ixD2F1_PCIE_LINK_CNTL3 0x200009d +#define ixD2F1_PCIE_LANE_ERROR_STATUS 0x200009e +#define ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL 0x200009f +#define ixD2F1_PCIE_LANE_1_EQUALIZATION_CNTL 0x200009f +#define ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL 0x20000a0 +#define ixD2F1_PCIE_LANE_3_EQUALIZATION_CNTL 0x20000a0 +#define ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL 0x20000a1 +#define ixD2F1_PCIE_LANE_5_EQUALIZATION_CNTL 0x20000a1 +#define ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL 0x20000a2 +#define ixD2F1_PCIE_LANE_7_EQUALIZATION_CNTL 0x20000a2 +#define ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL 0x20000a3 +#define ixD2F1_PCIE_LANE_9_EQUALIZATION_CNTL 0x20000a3 +#define ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL 0x20000a4 +#define ixD2F1_PCIE_LANE_11_EQUALIZATION_CNTL 0x20000a4 +#define ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL 0x20000a5 +#define ixD2F1_PCIE_LANE_13_EQUALIZATION_CNTL 0x20000a5 +#define ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL 0x20000a6 +#define ixD2F1_PCIE_LANE_15_EQUALIZATION_CNTL 0x20000a6 +#define ixD2F1_PCIE_ACS_ENH_CAP_LIST 0x20000a8 +#define ixD2F1_PCIE_ACS_CAP 0x20000a9 +#define ixD2F1_PCIE_ACS_CNTL 0x20000a9 +#define ixD2F1_PCIE_MC_ENH_CAP_LIST 0x20000bc +#define ixD2F1_PCIE_MC_CAP 0x20000bd +#define ixD2F1_PCIE_MC_CNTL 0x20000bd +#define ixD2F1_PCIE_MC_ADDR0 0x20000be +#define ixD2F1_PCIE_MC_ADDR1 0x20000bf +#define ixD2F1_PCIE_MC_RCV0 0x20000c0 +#define ixD2F1_PCIE_MC_RCV1 0x20000c1 +#define ixD2F1_PCIE_MC_BLOCK_ALL0 0x20000c2 +#define ixD2F1_PCIE_MC_BLOCK_ALL1 0x20000c3 +#define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x20000c4 +#define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x20000c5 +#define ixD2F1_PCIE_MC_OVERLAY_BAR0 0x20000c6 +#define ixD2F1_PCIE_MC_OVERLAY_BAR1 0x20000c7 +#define ixD2F2_PCIE_PORT_INDEX 0x3000038 +#define ixD2F2_PCIE_PORT_DATA 0x3000039 +#define ixD2F2_PCIEP_RESERVED 0x0 +#define ixD2F2_PCIEP_SCRATCH 0x1 +#define ixD2F2_PCIEP_HW_DEBUG 0x2 +#define ixD2F2_PCIEP_PORT_CNTL 0x10 +#define ixD2F2_PCIE_TX_CNTL 0x20 +#define ixD2F2_PCIE_TX_REQUESTER_ID 0x21 +#define ixD2F2_PCIE_TX_VENDOR_SPECIFIC 0x22 +#define ixD2F2_PCIE_TX_REQUEST_NUM_CNTL 0x23 +#define ixD2F2_PCIE_TX_SEQ 0x24 +#define ixD2F2_PCIE_TX_REPLAY 0x25 +#define ixD2F2_PCIE_TX_ACK_LATENCY_LIMIT 0x26 +#define ixD2F2_PCIE_TX_CREDITS_ADVT_P 0x30 +#define ixD2F2_PCIE_TX_CREDITS_ADVT_NP 0x31 +#define ixD2F2_PCIE_TX_CREDITS_ADVT_CPL 0x32 +#define ixD2F2_PCIE_TX_CREDITS_INIT_P 0x33 +#define ixD2F2_PCIE_TX_CREDITS_INIT_NP 0x34 +#define ixD2F2_PCIE_TX_CREDITS_INIT_CPL 0x35 +#define ixD2F2_PCIE_TX_CREDITS_STATUS 0x36 +#define ixD2F2_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 +#define ixD2F2_PCIE_P_PORT_LANE_STATUS 0x50 +#define ixD2F2_PCIE_FC_P 0x60 +#define ixD2F2_PCIE_FC_NP 0x61 +#define ixD2F2_PCIE_FC_CPL 0x62 +#define ixD2F2_PCIE_ERR_CNTL 0x6a +#define ixD2F2_PCIE_RX_CNTL 0x70 +#define ixD2F2_PCIE_RX_EXPECTED_SEQNUM 0x71 +#define ixD2F2_PCIE_RX_VENDOR_SPECIFIC 0x72 +#define ixD2F2_PCIE_RX_CNTL3 0x74 +#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_P 0x80 +#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 +#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 +#define ixD2F2_PCIEP_ERROR_INJECT_PHYSICAL 0x83 +#define ixD2F2_PCIEP_ERROR_INJECT_TRANSACTION 0x84 +#define ixD2F2_PCIE_LC_CNTL 0xa0 +#define ixD2F2_PCIE_LC_CNTL2 0xb1 +#define ixD2F2_PCIE_LC_CNTL3 0xb5 +#define ixD2F2_PCIE_LC_CNTL4 0xb6 +#define ixD2F2_PCIE_LC_CNTL5 0xb7 +#define ixD2F2_PCIE_LC_CNTL6 0xbb +#define ixD2F2_PCIE_LC_BW_CHANGE_CNTL 0xb2 +#define ixD2F2_PCIE_LC_TRAINING_CNTL 0xa1 +#define ixD2F2_PCIE_LC_LINK_WIDTH_CNTL 0xa2 +#define ixD2F2_PCIE_LC_N_FTS_CNTL 0xa3 +#define ixD2F2_PCIE_LC_SPEED_CNTL 0xa4 +#define ixD2F2_PCIE_LC_CDR_CNTL 0xb3 +#define ixD2F2_PCIE_LC_LANE_CNTL 0xb4 +#define ixD2F2_PCIE_LC_FORCE_COEFF 0xb8 +#define ixD2F2_PCIE_LC_BEST_EQ_SETTINGS 0xb9 +#define ixD2F2_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba +#define ixD2F2_PCIE_LC_STATE0 0xa5 +#define ixD2F2_PCIE_LC_STATE1 0xa6 +#define ixD2F2_PCIE_LC_STATE2 0xa7 +#define ixD2F2_PCIE_LC_STATE3 0xa8 +#define ixD2F2_PCIE_LC_STATE4 0xa9 +#define ixD2F2_PCIE_LC_STATE5 0xaa +#define ixD2F2_PCIEP_STRAP_LC 0xc0 +#define ixD2F2_PCIEP_STRAP_MISC 0xc1 +#define ixD2F2_PCIEP_BCH_ECC_CNTL 0xd0 +#define ixD2F2_PCIEP_HPGI_PRIVATE 0xd2 +#define ixD2F2_PCIEP_HPGI 0xda +#define ixD2F2_VENDOR_ID 0x3000000 +#define ixD2F2_DEVICE_ID 0x3000000 +#define ixD2F2_COMMAND 0x3000001 +#define ixD2F2_STATUS 0x3000001 +#define ixD2F2_REVISION_ID 0x3000002 +#define ixD2F2_PROG_INTERFACE 0x3000002 +#define ixD2F2_SUB_CLASS 0x3000002 +#define ixD2F2_BASE_CLASS 0x3000002 +#define ixD2F2_CACHE_LINE 0x3000003 +#define ixD2F2_LATENCY 0x3000003 +#define ixD2F2_HEADER 0x3000003 +#define ixD2F2_BIST 0x3000003 +#define ixD2F2_SUB_BUS_NUMBER_LATENCY 0x3000006 +#define ixD2F2_IO_BASE_LIMIT 0x3000007 +#define ixD2F2_SECONDARY_STATUS 0x3000007 +#define ixD2F2_MEM_BASE_LIMIT 0x3000008 +#define ixD2F2_PREF_BASE_LIMIT 0x3000009 +#define ixD2F2_PREF_BASE_UPPER 0x300000a +#define ixD2F2_PREF_LIMIT_UPPER 0x300000b +#define ixD2F2_IO_BASE_LIMIT_HI 0x300000c +#define ixD2F2_IRQ_BRIDGE_CNTL 0x300000f +#define ixD2F2_CAP_PTR 0x300000d +#define ixD2F2_INTERRUPT_LINE 0x300000f +#define ixD2F2_INTERRUPT_PIN 0x300000f +#define ixD2F2_EXT_BRIDGE_CNTL 0x3000010 +#define ixD2F2_PMI_CAP_LIST 0x3000014 +#define ixD2F2_PMI_CAP 0x3000014 +#define ixD2F2_PMI_STATUS_CNTL 0x3000015 +#define ixD2F2_PCIE_CAP_LIST 0x3000016 +#define ixD2F2_PCIE_CAP 0x3000016 +#define ixD2F2_DEVICE_CAP 0x3000017 +#define ixD2F2_DEVICE_CNTL 0x3000018 +#define ixD2F2_DEVICE_STATUS 0x3000018 +#define ixD2F2_LINK_CAP 0x3000019 +#define ixD2F2_LINK_CNTL 0x300001a +#define ixD2F2_LINK_STATUS 0x300001a +#define ixD2F2_SLOT_CAP 0x300001b +#define ixD2F2_SLOT_CNTL 0x300001c +#define ixD2F2_SLOT_STATUS 0x300001c +#define ixD2F2_ROOT_CNTL 0x300001d +#define ixD2F2_ROOT_CAP 0x300001d +#define ixD2F2_ROOT_STATUS 0x300001e +#define ixD2F2_DEVICE_CAP2 0x300001f +#define ixD2F2_DEVICE_CNTL2 0x3000020 +#define ixD2F2_DEVICE_STATUS2 0x3000020 +#define ixD2F2_LINK_CAP2 0x3000021 +#define ixD2F2_LINK_CNTL2 0x3000022 +#define ixD2F2_LINK_STATUS2 0x3000022 +#define ixD2F2_SLOT_CAP2 0x3000023 +#define ixD2F2_SLOT_CNTL2 0x3000024 +#define ixD2F2_SLOT_STATUS2 0x3000024 +#define ixD2F2_MSI_CAP_LIST 0x3000028 +#define ixD2F2_MSI_MSG_CNTL 0x3000028 +#define ixD2F2_MSI_MSG_ADDR_LO 0x3000029 +#define ixD2F2_MSI_MSG_ADDR_HI 0x300002a +#define ixD2F2_MSI_MSG_DATA_64 0x300002b +#define ixD2F2_MSI_MSG_DATA 0x300002a +#define ixD2F2_SSID_CAP_LIST 0x3000030 +#define ixD2F2_SSID_CAP 0x3000031 +#define ixD2F2_MSI_MAP_CAP_LIST 0x3000032 +#define ixD2F2_MSI_MAP_CAP 0x3000032 +#define ixD2F2_MSI_MAP_ADDR_LO 0x3000033 +#define ixD2F2_MSI_MAP_ADDR_HI 0x3000034 +#define ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3000040 +#define ixD2F2_PCIE_VENDOR_SPECIFIC_HDR 0x3000041 +#define ixD2F2_PCIE_VENDOR_SPECIFIC1 0x3000042 +#define ixD2F2_PCIE_VENDOR_SPECIFIC2 0x3000043 +#define ixD2F2_PCIE_VC_ENH_CAP_LIST 0x3000044 +#define ixD2F2_PCIE_PORT_VC_CAP_REG1 0x3000045 +#define ixD2F2_PCIE_PORT_VC_CAP_REG2 0x3000046 +#define ixD2F2_PCIE_PORT_VC_CNTL 0x3000047 +#define ixD2F2_PCIE_PORT_VC_STATUS 0x3000047 +#define ixD2F2_PCIE_VC0_RESOURCE_CAP 0x3000048 +#define ixD2F2_PCIE_VC0_RESOURCE_CNTL 0x3000049 +#define ixD2F2_PCIE_VC0_RESOURCE_STATUS 0x300004a +#define ixD2F2_PCIE_VC1_RESOURCE_CAP 0x300004b +#define ixD2F2_PCIE_VC1_RESOURCE_CNTL 0x300004c +#define ixD2F2_PCIE_VC1_RESOURCE_STATUS 0x300004d +#define ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3000050 +#define ixD2F2_PCIE_DEV_SERIAL_NUM_DW1 0x3000051 +#define ixD2F2_PCIE_DEV_SERIAL_NUM_DW2 0x3000052 +#define ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3000054 +#define ixD2F2_PCIE_UNCORR_ERR_STATUS 0x3000055 +#define ixD2F2_PCIE_UNCORR_ERR_MASK 0x3000056 +#define ixD2F2_PCIE_UNCORR_ERR_SEVERITY 0x3000057 +#define ixD2F2_PCIE_CORR_ERR_STATUS 0x3000058 +#define ixD2F2_PCIE_CORR_ERR_MASK 0x3000059 +#define ixD2F2_PCIE_ADV_ERR_CAP_CNTL 0x300005a +#define ixD2F2_PCIE_HDR_LOG0 0x300005b +#define ixD2F2_PCIE_HDR_LOG1 0x300005c +#define ixD2F2_PCIE_HDR_LOG2 0x300005d +#define ixD2F2_PCIE_HDR_LOG3 0x300005e +#define ixD2F2_PCIE_ROOT_ERR_CMD 0x300005f +#define ixD2F2_PCIE_ROOT_ERR_STATUS 0x3000060 +#define ixD2F2_PCIE_ERR_SRC_ID 0x3000061 +#define ixD2F2_PCIE_TLP_PREFIX_LOG0 0x3000062 +#define ixD2F2_PCIE_TLP_PREFIX_LOG1 0x3000063 +#define ixD2F2_PCIE_TLP_PREFIX_LOG2 0x3000064 +#define ixD2F2_PCIE_TLP_PREFIX_LOG3 0x3000065 +#define ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST 0x300009c +#define ixD2F2_PCIE_LINK_CNTL3 0x300009d +#define ixD2F2_PCIE_LANE_ERROR_STATUS 0x300009e +#define ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL 0x300009f +#define ixD2F2_PCIE_LANE_1_EQUALIZATION_CNTL 0x300009f +#define ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL 0x30000a0 +#define ixD2F2_PCIE_LANE_3_EQUALIZATION_CNTL 0x30000a0 +#define ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL 0x30000a1 +#define ixD2F2_PCIE_LANE_5_EQUALIZATION_CNTL 0x30000a1 +#define ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL 0x30000a2 +#define ixD2F2_PCIE_LANE_7_EQUALIZATION_CNTL 0x30000a2 +#define ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL 0x30000a3 +#define ixD2F2_PCIE_LANE_9_EQUALIZATION_CNTL 0x30000a3 +#define ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL 0x30000a4 +#define ixD2F2_PCIE_LANE_11_EQUALIZATION_CNTL 0x30000a4 +#define ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL 0x30000a5 +#define ixD2F2_PCIE_LANE_13_EQUALIZATION_CNTL 0x30000a5 +#define ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL 0x30000a6 +#define ixD2F2_PCIE_LANE_15_EQUALIZATION_CNTL 0x30000a6 +#define ixD2F2_PCIE_ACS_ENH_CAP_LIST 0x30000a8 +#define ixD2F2_PCIE_ACS_CAP 0x30000a9 +#define ixD2F2_PCIE_ACS_CNTL 0x30000a9 +#define ixD2F2_PCIE_MC_ENH_CAP_LIST 0x30000bc +#define ixD2F2_PCIE_MC_CAP 0x30000bd +#define ixD2F2_PCIE_MC_CNTL 0x30000bd +#define ixD2F2_PCIE_MC_ADDR0 0x30000be +#define ixD2F2_PCIE_MC_ADDR1 0x30000bf +#define ixD2F2_PCIE_MC_RCV0 0x30000c0 +#define ixD2F2_PCIE_MC_RCV1 0x30000c1 +#define ixD2F2_PCIE_MC_BLOCK_ALL0 0x30000c2 +#define ixD2F2_PCIE_MC_BLOCK_ALL1 0x30000c3 +#define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x30000c4 +#define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x30000c5 +#define ixD2F2_PCIE_MC_OVERLAY_BAR0 0x30000c6 +#define ixD2F2_PCIE_MC_OVERLAY_BAR1 0x30000c7 +#define ixD2F3_PCIE_PORT_INDEX 0x4000038 +#define ixD2F3_PCIE_PORT_DATA 0x4000039 +#define ixD2F3_PCIEP_RESERVED 0x0 +#define ixD2F3_PCIEP_SCRATCH 0x1 +#define ixD2F3_PCIEP_HW_DEBUG 0x2 +#define ixD2F3_PCIEP_PORT_CNTL 0x10 +#define ixD2F3_PCIE_TX_CNTL 0x20 +#define ixD2F3_PCIE_TX_REQUESTER_ID 0x21 +#define ixD2F3_PCIE_TX_VENDOR_SPECIFIC 0x22 +#define ixD2F3_PCIE_TX_REQUEST_NUM_CNTL 0x23 +#define ixD2F3_PCIE_TX_SEQ 0x24 +#define ixD2F3_PCIE_TX_REPLAY 0x25 +#define ixD2F3_PCIE_TX_ACK_LATENCY_LIMIT 0x26 +#define ixD2F3_PCIE_TX_CREDITS_ADVT_P 0x30 +#define ixD2F3_PCIE_TX_CREDITS_ADVT_NP 0x31 +#define ixD2F3_PCIE_TX_CREDITS_ADVT_CPL 0x32 +#define ixD2F3_PCIE_TX_CREDITS_INIT_P 0x33 +#define ixD2F3_PCIE_TX_CREDITS_INIT_NP 0x34 +#define ixD2F3_PCIE_TX_CREDITS_INIT_CPL 0x35 +#define ixD2F3_PCIE_TX_CREDITS_STATUS 0x36 +#define ixD2F3_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 +#define ixD2F3_PCIE_P_PORT_LANE_STATUS 0x50 +#define ixD2F3_PCIE_FC_P 0x60 +#define ixD2F3_PCIE_FC_NP 0x61 +#define ixD2F3_PCIE_FC_CPL 0x62 +#define ixD2F3_PCIE_ERR_CNTL 0x6a +#define ixD2F3_PCIE_RX_CNTL 0x70 +#define ixD2F3_PCIE_RX_EXPECTED_SEQNUM 0x71 +#define ixD2F3_PCIE_RX_VENDOR_SPECIFIC 0x72 +#define ixD2F3_PCIE_RX_CNTL3 0x74 +#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_P 0x80 +#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 +#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 +#define ixD2F3_PCIEP_ERROR_INJECT_PHYSICAL 0x83 +#define ixD2F3_PCIEP_ERROR_INJECT_TRANSACTION 0x84 +#define ixD2F3_PCIE_LC_CNTL 0xa0 +#define ixD2F3_PCIE_LC_CNTL2 0xb1 +#define ixD2F3_PCIE_LC_CNTL3 0xb5 +#define ixD2F3_PCIE_LC_CNTL4 0xb6 +#define ixD2F3_PCIE_LC_CNTL5 0xb7 +#define ixD2F3_PCIE_LC_CNTL6 0xbb +#define ixD2F3_PCIE_LC_BW_CHANGE_CNTL 0xb2 +#define ixD2F3_PCIE_LC_TRAINING_CNTL 0xa1 +#define ixD2F3_PCIE_LC_LINK_WIDTH_CNTL 0xa2 +#define ixD2F3_PCIE_LC_N_FTS_CNTL 0xa3 +#define ixD2F3_PCIE_LC_SPEED_CNTL 0xa4 +#define ixD2F3_PCIE_LC_CDR_CNTL 0xb3 +#define ixD2F3_PCIE_LC_LANE_CNTL 0xb4 +#define ixD2F3_PCIE_LC_FORCE_COEFF 0xb8 +#define ixD2F3_PCIE_LC_BEST_EQ_SETTINGS 0xb9 +#define ixD2F3_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba +#define ixD2F3_PCIE_LC_STATE0 0xa5 +#define ixD2F3_PCIE_LC_STATE1 0xa6 +#define ixD2F3_PCIE_LC_STATE2 0xa7 +#define ixD2F3_PCIE_LC_STATE3 0xa8 +#define ixD2F3_PCIE_LC_STATE4 0xa9 +#define ixD2F3_PCIE_LC_STATE5 0xaa +#define ixD2F3_PCIEP_STRAP_LC 0xc0 +#define ixD2F3_PCIEP_STRAP_MISC 0xc1 +#define ixD2F3_PCIEP_BCH_ECC_CNTL 0xd0 +#define ixD2F3_PCIEP_HPGI_PRIVATE 0xd2 +#define ixD2F3_PCIEP_HPGI 0xda +#define ixD2F3_VENDOR_ID 0x4000000 +#define ixD2F3_DEVICE_ID 0x4000000 +#define ixD2F3_COMMAND 0x4000001 +#define ixD2F3_STATUS 0x4000001 +#define ixD2F3_REVISION_ID 0x4000002 +#define ixD2F3_PROG_INTERFACE 0x4000002 +#define ixD2F3_SUB_CLASS 0x4000002 +#define ixD2F3_BASE_CLASS 0x4000002 +#define ixD2F3_CACHE_LINE 0x4000003 +#define ixD2F3_LATENCY 0x4000003 +#define ixD2F3_HEADER 0x4000003 +#define ixD2F3_BIST 0x4000003 +#define ixD2F3_SUB_BUS_NUMBER_LATENCY 0x4000006 +#define ixD2F3_IO_BASE_LIMIT 0x4000007 +#define ixD2F3_SECONDARY_STATUS 0x4000007 +#define ixD2F3_MEM_BASE_LIMIT 0x4000008 +#define ixD2F3_PREF_BASE_LIMIT 0x4000009 +#define ixD2F3_PREF_BASE_UPPER 0x400000a +#define ixD2F3_PREF_LIMIT_UPPER 0x400000b +#define ixD2F3_IO_BASE_LIMIT_HI 0x400000c +#define ixD2F3_IRQ_BRIDGE_CNTL 0x400000f +#define ixD2F3_CAP_PTR 0x400000d +#define ixD2F3_INTERRUPT_LINE 0x400000f +#define ixD2F3_INTERRUPT_PIN 0x400000f +#define ixD2F3_EXT_BRIDGE_CNTL 0x4000010 +#define ixD2F3_PMI_CAP_LIST 0x4000014 +#define ixD2F3_PMI_CAP 0x4000014 +#define ixD2F3_PMI_STATUS_CNTL 0x4000015 +#define ixD2F3_PCIE_CAP_LIST 0x4000016 +#define ixD2F3_PCIE_CAP 0x4000016 +#define ixD2F3_DEVICE_CAP 0x4000017 +#define ixD2F3_DEVICE_CNTL 0x4000018 +#define ixD2F3_DEVICE_STATUS 0x4000018 +#define ixD2F3_LINK_CAP 0x4000019 +#define ixD2F3_LINK_CNTL 0x400001a +#define ixD2F3_LINK_STATUS 0x400001a +#define ixD2F3_SLOT_CAP 0x400001b +#define ixD2F3_SLOT_CNTL 0x400001c +#define ixD2F3_SLOT_STATUS 0x400001c +#define ixD2F3_ROOT_CNTL 0x400001d +#define ixD2F3_ROOT_CAP 0x400001d +#define ixD2F3_ROOT_STATUS 0x400001e +#define ixD2F3_DEVICE_CAP2 0x400001f +#define ixD2F3_DEVICE_CNTL2 0x4000020 +#define ixD2F3_DEVICE_STATUS2 0x4000020 +#define ixD2F3_LINK_CAP2 0x4000021 +#define ixD2F3_LINK_CNTL2 0x4000022 +#define ixD2F3_LINK_STATUS2 0x4000022 +#define ixD2F3_SLOT_CAP2 0x4000023 +#define ixD2F3_SLOT_CNTL2 0x4000024 +#define ixD2F3_SLOT_STATUS2 0x4000024 +#define ixD2F3_MSI_CAP_LIST 0x4000028 +#define ixD2F3_MSI_MSG_CNTL 0x4000028 +#define ixD2F3_MSI_MSG_ADDR_LO 0x4000029 +#define ixD2F3_MSI_MSG_ADDR_HI 0x400002a +#define ixD2F3_MSI_MSG_DATA_64 0x400002b +#define ixD2F3_MSI_MSG_DATA 0x400002a +#define ixD2F3_SSID_CAP_LIST 0x4000030 +#define ixD2F3_SSID_CAP 0x4000031 +#define ixD2F3_MSI_MAP_CAP_LIST 0x4000032 +#define ixD2F3_MSI_MAP_CAP 0x4000032 +#define ixD2F3_MSI_MAP_ADDR_LO 0x4000033 +#define ixD2F3_MSI_MAP_ADDR_HI 0x4000034 +#define ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x4000040 +#define ixD2F3_PCIE_VENDOR_SPECIFIC_HDR 0x4000041 +#define ixD2F3_PCIE_VENDOR_SPECIFIC1 0x4000042 +#define ixD2F3_PCIE_VENDOR_SPECIFIC2 0x4000043 +#define ixD2F3_PCIE_VC_ENH_CAP_LIST 0x4000044 +#define ixD2F3_PCIE_PORT_VC_CAP_REG1 0x4000045 +#define ixD2F3_PCIE_PORT_VC_CAP_REG2 0x4000046 +#define ixD2F3_PCIE_PORT_VC_CNTL 0x4000047 +#define ixD2F3_PCIE_PORT_VC_STATUS 0x4000047 +#define ixD2F3_PCIE_VC0_RESOURCE_CAP 0x4000048 +#define ixD2F3_PCIE_VC0_RESOURCE_CNTL 0x4000049 +#define ixD2F3_PCIE_VC0_RESOURCE_STATUS 0x400004a +#define ixD2F3_PCIE_VC1_RESOURCE_CAP 0x400004b +#define ixD2F3_PCIE_VC1_RESOURCE_CNTL 0x400004c +#define ixD2F3_PCIE_VC1_RESOURCE_STATUS 0x400004d +#define ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x4000050 +#define ixD2F3_PCIE_DEV_SERIAL_NUM_DW1 0x4000051 +#define ixD2F3_PCIE_DEV_SERIAL_NUM_DW2 0x4000052 +#define ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x4000054 +#define ixD2F3_PCIE_UNCORR_ERR_STATUS 0x4000055 +#define ixD2F3_PCIE_UNCORR_ERR_MASK 0x4000056 +#define ixD2F3_PCIE_UNCORR_ERR_SEVERITY 0x4000057 +#define ixD2F3_PCIE_CORR_ERR_STATUS 0x4000058 +#define ixD2F3_PCIE_CORR_ERR_MASK 0x4000059 +#define ixD2F3_PCIE_ADV_ERR_CAP_CNTL 0x400005a +#define ixD2F3_PCIE_HDR_LOG0 0x400005b +#define ixD2F3_PCIE_HDR_LOG1 0x400005c +#define ixD2F3_PCIE_HDR_LOG2 0x400005d +#define ixD2F3_PCIE_HDR_LOG3 0x400005e +#define ixD2F3_PCIE_ROOT_ERR_CMD 0x400005f +#define ixD2F3_PCIE_ROOT_ERR_STATUS 0x4000060 +#define ixD2F3_PCIE_ERR_SRC_ID 0x4000061 +#define ixD2F3_PCIE_TLP_PREFIX_LOG0 0x4000062 +#define ixD2F3_PCIE_TLP_PREFIX_LOG1 0x4000063 +#define ixD2F3_PCIE_TLP_PREFIX_LOG2 0x4000064 +#define ixD2F3_PCIE_TLP_PREFIX_LOG3 0x4000065 +#define ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST 0x400009c +#define ixD2F3_PCIE_LINK_CNTL3 0x400009d +#define ixD2F3_PCIE_LANE_ERROR_STATUS 0x400009e +#define ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL 0x400009f +#define ixD2F3_PCIE_LANE_1_EQUALIZATION_CNTL 0x400009f +#define ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL 0x40000a0 +#define ixD2F3_PCIE_LANE_3_EQUALIZATION_CNTL 0x40000a0 +#define ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL 0x40000a1 +#define ixD2F3_PCIE_LANE_5_EQUALIZATION_CNTL 0x40000a1 +#define ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL 0x40000a2 +#define ixD2F3_PCIE_LANE_7_EQUALIZATION_CNTL 0x40000a2 +#define ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL 0x40000a3 +#define ixD2F3_PCIE_LANE_9_EQUALIZATION_CNTL 0x40000a3 +#define ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL 0x40000a4 +#define ixD2F3_PCIE_LANE_11_EQUALIZATION_CNTL 0x40000a4 +#define ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL 0x40000a5 +#define ixD2F3_PCIE_LANE_13_EQUALIZATION_CNTL 0x40000a5 +#define ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL 0x40000a6 +#define ixD2F3_PCIE_LANE_15_EQUALIZATION_CNTL 0x40000a6 +#define ixD2F3_PCIE_ACS_ENH_CAP_LIST 0x40000a8 +#define ixD2F3_PCIE_ACS_CAP 0x40000a9 +#define ixD2F3_PCIE_ACS_CNTL 0x40000a9 +#define ixD2F3_PCIE_MC_ENH_CAP_LIST 0x40000bc +#define ixD2F3_PCIE_MC_CAP 0x40000bd +#define ixD2F3_PCIE_MC_CNTL 0x40000bd +#define ixD2F3_PCIE_MC_ADDR0 0x40000be +#define ixD2F3_PCIE_MC_ADDR1 0x40000bf +#define ixD2F3_PCIE_MC_RCV0 0x40000c0 +#define ixD2F3_PCIE_MC_RCV1 0x40000c1 +#define ixD2F3_PCIE_MC_BLOCK_ALL0 0x40000c2 +#define ixD2F3_PCIE_MC_BLOCK_ALL1 0x40000c3 +#define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0 0x40000c4 +#define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1 0x40000c5 +#define ixD2F3_PCIE_MC_OVERLAY_BAR0 0x40000c6 +#define ixD2F3_PCIE_MC_OVERLAY_BAR1 0x40000c7 +#define ixD2F4_PCIE_PORT_INDEX 0x5000038 +#define ixD2F4_PCIE_PORT_DATA 0x5000039 +#define ixD2F4_PCIEP_RESERVED 0x0 +#define ixD2F4_PCIEP_SCRATCH 0x1 +#define ixD2F4_PCIEP_HW_DEBUG 0x2 +#define ixD2F4_PCIEP_PORT_CNTL 0x10 +#define ixD2F4_PCIE_TX_CNTL 0x20 +#define ixD2F4_PCIE_TX_REQUESTER_ID 0x21 +#define ixD2F4_PCIE_TX_VENDOR_SPECIFIC 0x22 +#define ixD2F4_PCIE_TX_REQUEST_NUM_CNTL 0x23 +#define ixD2F4_PCIE_TX_SEQ 0x24 +#define ixD2F4_PCIE_TX_REPLAY 0x25 +#define ixD2F4_PCIE_TX_ACK_LATENCY_LIMIT 0x26 +#define ixD2F4_PCIE_TX_CREDITS_ADVT_P 0x30 +#define ixD2F4_PCIE_TX_CREDITS_ADVT_NP 0x31 +#define ixD2F4_PCIE_TX_CREDITS_ADVT_CPL 0x32 +#define ixD2F4_PCIE_TX_CREDITS_INIT_P 0x33 +#define ixD2F4_PCIE_TX_CREDITS_INIT_NP 0x34 +#define ixD2F4_PCIE_TX_CREDITS_INIT_CPL 0x35 +#define ixD2F4_PCIE_TX_CREDITS_STATUS 0x36 +#define ixD2F4_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 +#define ixD2F4_PCIE_P_PORT_LANE_STATUS 0x50 +#define ixD2F4_PCIE_FC_P 0x60 +#define ixD2F4_PCIE_FC_NP 0x61 +#define ixD2F4_PCIE_FC_CPL 0x62 +#define ixD2F4_PCIE_ERR_CNTL 0x6a +#define ixD2F4_PCIE_RX_CNTL 0x70 +#define ixD2F4_PCIE_RX_EXPECTED_SEQNUM 0x71 +#define ixD2F4_PCIE_RX_VENDOR_SPECIFIC 0x72 +#define ixD2F4_PCIE_RX_CNTL3 0x74 +#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_P 0x80 +#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 +#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 +#define ixD2F4_PCIEP_ERROR_INJECT_PHYSICAL 0x83 +#define ixD2F4_PCIEP_ERROR_INJECT_TRANSACTION 0x84 +#define ixD2F4_PCIE_LC_CNTL 0xa0 +#define ixD2F4_PCIE_LC_CNTL2 0xb1 +#define ixD2F4_PCIE_LC_CNTL3 0xb5 +#define ixD2F4_PCIE_LC_CNTL4 0xb6 +#define ixD2F4_PCIE_LC_CNTL5 0xb7 +#define ixD2F4_PCIE_LC_CNTL6 0xbb +#define ixD2F4_PCIE_LC_BW_CHANGE_CNTL 0xb2 +#define ixD2F4_PCIE_LC_TRAINING_CNTL 0xa1 +#define ixD2F4_PCIE_LC_LINK_WIDTH_CNTL 0xa2 +#define ixD2F4_PCIE_LC_N_FTS_CNTL 0xa3 +#define ixD2F4_PCIE_LC_SPEED_CNTL 0xa4 +#define ixD2F4_PCIE_LC_CDR_CNTL 0xb3 +#define ixD2F4_PCIE_LC_LANE_CNTL 0xb4 +#define ixD2F4_PCIE_LC_FORCE_COEFF 0xb8 +#define ixD2F4_PCIE_LC_BEST_EQ_SETTINGS 0xb9 +#define ixD2F4_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba +#define ixD2F4_PCIE_LC_STATE0 0xa5 +#define ixD2F4_PCIE_LC_STATE1 0xa6 +#define ixD2F4_PCIE_LC_STATE2 0xa7 +#define ixD2F4_PCIE_LC_STATE3 0xa8 +#define ixD2F4_PCIE_LC_STATE4 0xa9 +#define ixD2F4_PCIE_LC_STATE5 0xaa +#define ixD2F4_PCIEP_STRAP_LC 0xc0 +#define ixD2F4_PCIEP_STRAP_MISC 0xc1 +#define ixD2F4_PCIEP_BCH_ECC_CNTL 0xd0 +#define ixD2F4_PCIEP_HPGI_PRIVATE 0xd2 +#define ixD2F4_PCIEP_HPGI 0xda +#define ixD2F4_VENDOR_ID 0x5000000 +#define ixD2F4_DEVICE_ID 0x5000000 +#define ixD2F4_COMMAND 0x5000001 +#define ixD2F4_STATUS 0x5000001 +#define ixD2F4_REVISION_ID 0x5000002 +#define ixD2F4_PROG_INTERFACE 0x5000002 +#define ixD2F4_SUB_CLASS 0x5000002 +#define ixD2F4_BASE_CLASS 0x5000002 +#define ixD2F4_CACHE_LINE 0x5000003 +#define ixD2F4_LATENCY 0x5000003 +#define ixD2F4_HEADER 0x5000003 +#define ixD2F4_BIST 0x5000003 +#define ixD2F4_SUB_BUS_NUMBER_LATENCY 0x5000006 +#define ixD2F4_IO_BASE_LIMIT 0x5000007 +#define ixD2F4_SECONDARY_STATUS 0x5000007 +#define ixD2F4_MEM_BASE_LIMIT 0x5000008 +#define ixD2F4_PREF_BASE_LIMIT 0x5000009 +#define ixD2F4_PREF_BASE_UPPER 0x500000a +#define ixD2F4_PREF_LIMIT_UPPER 0x500000b +#define ixD2F4_IO_BASE_LIMIT_HI 0x500000c +#define ixD2F4_IRQ_BRIDGE_CNTL 0x500000f +#define ixD2F4_CAP_PTR 0x500000d +#define ixD2F4_INTERRUPT_LINE 0x500000f +#define ixD2F4_INTERRUPT_PIN 0x500000f +#define ixD2F4_EXT_BRIDGE_CNTL 0x5000010 +#define ixD2F4_PMI_CAP_LIST 0x5000014 +#define ixD2F4_PMI_CAP 0x5000014 +#define ixD2F4_PMI_STATUS_CNTL 0x5000015 +#define ixD2F4_PCIE_CAP_LIST 0x5000016 +#define ixD2F4_PCIE_CAP 0x5000016 +#define ixD2F4_DEVICE_CAP 0x5000017 +#define ixD2F4_DEVICE_CNTL 0x5000018 +#define ixD2F4_DEVICE_STATUS 0x5000018 +#define ixD2F4_LINK_CAP 0x5000019 +#define ixD2F4_LINK_CNTL 0x500001a +#define ixD2F4_LINK_STATUS 0x500001a +#define ixD2F4_SLOT_CAP 0x500001b +#define ixD2F4_SLOT_CNTL 0x500001c +#define ixD2F4_SLOT_STATUS 0x500001c +#define ixD2F4_ROOT_CNTL 0x500001d +#define ixD2F4_ROOT_CAP 0x500001d +#define ixD2F4_ROOT_STATUS 0x500001e +#define ixD2F4_DEVICE_CAP2 0x500001f +#define ixD2F4_DEVICE_CNTL2 0x5000020 +#define ixD2F4_DEVICE_STATUS2 0x5000020 +#define ixD2F4_LINK_CAP2 0x5000021 +#define ixD2F4_LINK_CNTL2 0x5000022 +#define ixD2F4_LINK_STATUS2 0x5000022 +#define ixD2F4_SLOT_CAP2 0x5000023 +#define ixD2F4_SLOT_CNTL2 0x5000024 +#define ixD2F4_SLOT_STATUS2 0x5000024 +#define ixD2F4_MSI_CAP_LIST 0x5000028 +#define ixD2F4_MSI_MSG_CNTL 0x5000028 +#define ixD2F4_MSI_MSG_ADDR_LO 0x5000029 +#define ixD2F4_MSI_MSG_ADDR_HI 0x500002a +#define ixD2F4_MSI_MSG_DATA_64 0x500002b +#define ixD2F4_MSI_MSG_DATA 0x500002a +#define ixD2F4_SSID_CAP_LIST 0x5000030 +#define ixD2F4_SSID_CAP 0x5000031 +#define ixD2F4_MSI_MAP_CAP_LIST 0x5000032 +#define ixD2F4_MSI_MAP_CAP 0x5000032 +#define ixD2F4_MSI_MAP_ADDR_LO 0x5000033 +#define ixD2F4_MSI_MAP_ADDR_HI 0x5000034 +#define ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x5000040 +#define ixD2F4_PCIE_VENDOR_SPECIFIC_HDR 0x5000041 +#define ixD2F4_PCIE_VENDOR_SPECIFIC1 0x5000042 +#define ixD2F4_PCIE_VENDOR_SPECIFIC2 0x5000043 +#define ixD2F4_PCIE_VC_ENH_CAP_LIST 0x5000044 +#define ixD2F4_PCIE_PORT_VC_CAP_REG1 0x5000045 +#define ixD2F4_PCIE_PORT_VC_CAP_REG2 0x5000046 +#define ixD2F4_PCIE_PORT_VC_CNTL 0x5000047 +#define ixD2F4_PCIE_PORT_VC_STATUS 0x5000047 +#define ixD2F4_PCIE_VC0_RESOURCE_CAP 0x5000048 +#define ixD2F4_PCIE_VC0_RESOURCE_CNTL 0x5000049 +#define ixD2F4_PCIE_VC0_RESOURCE_STATUS 0x500004a +#define ixD2F4_PCIE_VC1_RESOURCE_CAP 0x500004b +#define ixD2F4_PCIE_VC1_RESOURCE_CNTL 0x500004c +#define ixD2F4_PCIE_VC1_RESOURCE_STATUS 0x500004d +#define ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x5000050 +#define ixD2F4_PCIE_DEV_SERIAL_NUM_DW1 0x5000051 +#define ixD2F4_PCIE_DEV_SERIAL_NUM_DW2 0x5000052 +#define ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x5000054 +#define ixD2F4_PCIE_UNCORR_ERR_STATUS 0x5000055 +#define ixD2F4_PCIE_UNCORR_ERR_MASK 0x5000056 +#define ixD2F4_PCIE_UNCORR_ERR_SEVERITY 0x5000057 +#define ixD2F4_PCIE_CORR_ERR_STATUS 0x5000058 +#define ixD2F4_PCIE_CORR_ERR_MASK 0x5000059 +#define ixD2F4_PCIE_ADV_ERR_CAP_CNTL 0x500005a +#define ixD2F4_PCIE_HDR_LOG0 0x500005b +#define ixD2F4_PCIE_HDR_LOG1 0x500005c +#define ixD2F4_PCIE_HDR_LOG2 0x500005d +#define ixD2F4_PCIE_HDR_LOG3 0x500005e +#define ixD2F4_PCIE_ROOT_ERR_CMD 0x500005f +#define ixD2F4_PCIE_ROOT_ERR_STATUS 0x5000060 +#define ixD2F4_PCIE_ERR_SRC_ID 0x5000061 +#define ixD2F4_PCIE_TLP_PREFIX_LOG0 0x5000062 +#define ixD2F4_PCIE_TLP_PREFIX_LOG1 0x5000063 +#define ixD2F4_PCIE_TLP_PREFIX_LOG2 0x5000064 +#define ixD2F4_PCIE_TLP_PREFIX_LOG3 0x5000065 +#define ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST 0x500009c +#define ixD2F4_PCIE_LINK_CNTL3 0x500009d +#define ixD2F4_PCIE_LANE_ERROR_STATUS 0x500009e +#define ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL 0x500009f +#define ixD2F4_PCIE_LANE_1_EQUALIZATION_CNTL 0x500009f +#define ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL 0x50000a0 +#define ixD2F4_PCIE_LANE_3_EQUALIZATION_CNTL 0x50000a0 +#define ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL 0x50000a1 +#define ixD2F4_PCIE_LANE_5_EQUALIZATION_CNTL 0x50000a1 +#define ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL 0x50000a2 +#define ixD2F4_PCIE_LANE_7_EQUALIZATION_CNTL 0x50000a2 +#define ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL 0x50000a3 +#define ixD2F4_PCIE_LANE_9_EQUALIZATION_CNTL 0x50000a3 +#define ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL 0x50000a4 +#define ixD2F4_PCIE_LANE_11_EQUALIZATION_CNTL 0x50000a4 +#define ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL 0x50000a5 +#define ixD2F4_PCIE_LANE_13_EQUALIZATION_CNTL 0x50000a5 +#define ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL 0x50000a6 +#define ixD2F4_PCIE_LANE_15_EQUALIZATION_CNTL 0x50000a6 +#define ixD2F4_PCIE_ACS_ENH_CAP_LIST 0x50000a8 +#define ixD2F4_PCIE_ACS_CAP 0x50000a9 +#define ixD2F4_PCIE_ACS_CNTL 0x50000a9 +#define ixD2F4_PCIE_MC_ENH_CAP_LIST 0x50000bc +#define ixD2F4_PCIE_MC_CAP 0x50000bd +#define ixD2F4_PCIE_MC_CNTL 0x50000bd +#define ixD2F4_PCIE_MC_ADDR0 0x50000be +#define ixD2F4_PCIE_MC_ADDR1 0x50000bf +#define ixD2F4_PCIE_MC_RCV0 0x50000c0 +#define ixD2F4_PCIE_MC_RCV1 0x50000c1 +#define ixD2F4_PCIE_MC_BLOCK_ALL0 0x50000c2 +#define ixD2F4_PCIE_MC_BLOCK_ALL1 0x50000c3 +#define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0 0x50000c4 +#define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1 0x50000c5 +#define ixD2F4_PCIE_MC_OVERLAY_BAR0 0x50000c6 +#define ixD2F4_PCIE_MC_OVERLAY_BAR1 0x50000c7 +#define ixD2F5_PCIE_PORT_INDEX 0x6000038 +#define ixD2F5_PCIE_PORT_DATA 0x6000039 +#define ixD2F5_PCIEP_RESERVED 0x0 +#define ixD2F5_PCIEP_SCRATCH 0x1 +#define ixD2F5_PCIEP_HW_DEBUG 0x2 +#define ixD2F5_PCIEP_PORT_CNTL 0x10 +#define ixD2F5_PCIE_TX_CNTL 0x20 +#define ixD2F5_PCIE_TX_REQUESTER_ID 0x21 +#define ixD2F5_PCIE_TX_VENDOR_SPECIFIC 0x22 +#define ixD2F5_PCIE_TX_REQUEST_NUM_CNTL 0x23 +#define ixD2F5_PCIE_TX_SEQ 0x24 +#define ixD2F5_PCIE_TX_REPLAY 0x25 +#define ixD2F5_PCIE_TX_ACK_LATENCY_LIMIT 0x26 +#define ixD2F5_PCIE_TX_CREDITS_ADVT_P 0x30 +#define ixD2F5_PCIE_TX_CREDITS_ADVT_NP 0x31 +#define ixD2F5_PCIE_TX_CREDITS_ADVT_CPL 0x32 +#define ixD2F5_PCIE_TX_CREDITS_INIT_P 0x33 +#define ixD2F5_PCIE_TX_CREDITS_INIT_NP 0x34 +#define ixD2F5_PCIE_TX_CREDITS_INIT_CPL 0x35 +#define ixD2F5_PCIE_TX_CREDITS_STATUS 0x36 +#define ixD2F5_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 +#define ixD2F5_PCIE_P_PORT_LANE_STATUS 0x50 +#define ixD2F5_PCIE_FC_P 0x60 +#define ixD2F5_PCIE_FC_NP 0x61 +#define ixD2F5_PCIE_FC_CPL 0x62 +#define ixD2F5_PCIE_ERR_CNTL 0x6a +#define ixD2F5_PCIE_RX_CNTL 0x70 +#define ixD2F5_PCIE_RX_EXPECTED_SEQNUM 0x71 +#define ixD2F5_PCIE_RX_VENDOR_SPECIFIC 0x72 +#define ixD2F5_PCIE_RX_CNTL3 0x74 +#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_P 0x80 +#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 +#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 +#define ixD2F5_PCIEP_ERROR_INJECT_PHYSICAL 0x83 +#define ixD2F5_PCIEP_ERROR_INJECT_TRANSACTION 0x84 +#define ixD2F5_PCIE_LC_CNTL 0xa0 +#define ixD2F5_PCIE_LC_CNTL2 0xb1 +#define ixD2F5_PCIE_LC_CNTL3 0xb5 +#define ixD2F5_PCIE_LC_CNTL4 0xb6 +#define ixD2F5_PCIE_LC_CNTL5 0xb7 +#define ixD2F5_PCIE_LC_CNTL6 0xbb +#define ixD2F5_PCIE_LC_BW_CHANGE_CNTL 0xb2 +#define ixD2F5_PCIE_LC_TRAINING_CNTL 0xa1 +#define ixD2F5_PCIE_LC_LINK_WIDTH_CNTL 0xa2 +#define ixD2F5_PCIE_LC_N_FTS_CNTL 0xa3 +#define ixD2F5_PCIE_LC_SPEED_CNTL 0xa4 +#define ixD2F5_PCIE_LC_CDR_CNTL 0xb3 +#define ixD2F5_PCIE_LC_LANE_CNTL 0xb4 +#define ixD2F5_PCIE_LC_FORCE_COEFF 0xb8 +#define ixD2F5_PCIE_LC_BEST_EQ_SETTINGS 0xb9 +#define ixD2F5_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba +#define ixD2F5_PCIE_LC_STATE0 0xa5 +#define ixD2F5_PCIE_LC_STATE1 0xa6 +#define ixD2F5_PCIE_LC_STATE2 0xa7 +#define ixD2F5_PCIE_LC_STATE3 0xa8 +#define ixD2F5_PCIE_LC_STATE4 0xa9 +#define ixD2F5_PCIE_LC_STATE5 0xaa +#define ixD2F5_PCIEP_STRAP_LC 0xc0 +#define ixD2F5_PCIEP_STRAP_MISC 0xc1 +#define ixD2F5_PCIEP_BCH_ECC_CNTL 0xd0 +#define ixD2F5_PCIEP_HPGI_PRIVATE 0xd2 +#define ixD2F5_PCIEP_HPGI 0xda +#define ixD2F5_VENDOR_ID 0x6000000 +#define ixD2F5_DEVICE_ID 0x6000000 +#define ixD2F5_COMMAND 0x6000001 +#define ixD2F5_STATUS 0x6000001 +#define ixD2F5_REVISION_ID 0x6000002 +#define ixD2F5_PROG_INTERFACE 0x6000002 +#define ixD2F5_SUB_CLASS 0x6000002 +#define ixD2F5_BASE_CLASS 0x6000002 +#define ixD2F5_CACHE_LINE 0x6000003 +#define ixD2F5_LATENCY 0x6000003 +#define ixD2F5_HEADER 0x6000003 +#define ixD2F5_BIST 0x6000003 +#define ixD2F5_SUB_BUS_NUMBER_LATENCY 0x6000006 +#define ixD2F5_IO_BASE_LIMIT 0x6000007 +#define ixD2F5_SECONDARY_STATUS 0x6000007 +#define ixD2F5_MEM_BASE_LIMIT 0x6000008 +#define ixD2F5_PREF_BASE_LIMIT 0x6000009 +#define ixD2F5_PREF_BASE_UPPER 0x600000a +#define ixD2F5_PREF_LIMIT_UPPER 0x600000b +#define ixD2F5_IO_BASE_LIMIT_HI 0x600000c +#define ixD2F5_IRQ_BRIDGE_CNTL 0x600000f +#define ixD2F5_CAP_PTR 0x600000d +#define ixD2F5_INTERRUPT_LINE 0x600000f +#define ixD2F5_INTERRUPT_PIN 0x600000f +#define ixD2F5_EXT_BRIDGE_CNTL 0x6000010 +#define ixD2F5_PMI_CAP_LIST 0x6000014 +#define ixD2F5_PMI_CAP 0x6000014 +#define ixD2F5_PMI_STATUS_CNTL 0x6000015 +#define ixD2F5_PCIE_CAP_LIST 0x6000016 +#define ixD2F5_PCIE_CAP 0x6000016 +#define ixD2F5_DEVICE_CAP 0x6000017 +#define ixD2F5_DEVICE_CNTL 0x6000018 +#define ixD2F5_DEVICE_STATUS 0x6000018 +#define ixD2F5_LINK_CAP 0x6000019 +#define ixD2F5_LINK_CNTL 0x600001a +#define ixD2F5_LINK_STATUS 0x600001a +#define ixD2F5_SLOT_CAP 0x600001b +#define ixD2F5_SLOT_CNTL 0x600001c +#define ixD2F5_SLOT_STATUS 0x600001c +#define ixD2F5_ROOT_CNTL 0x600001d +#define ixD2F5_ROOT_CAP 0x600001d +#define ixD2F5_ROOT_STATUS 0x600001e +#define ixD2F5_DEVICE_CAP2 0x600001f +#define ixD2F5_DEVICE_CNTL2 0x6000020 +#define ixD2F5_DEVICE_STATUS2 0x6000020 +#define ixD2F5_LINK_CAP2 0x6000021 +#define ixD2F5_LINK_CNTL2 0x6000022 +#define ixD2F5_LINK_STATUS2 0x6000022 +#define ixD2F5_SLOT_CAP2 0x6000023 +#define ixD2F5_SLOT_CNTL2 0x6000024 +#define ixD2F5_SLOT_STATUS2 0x6000024 +#define ixD2F5_MSI_CAP_LIST 0x6000028 +#define ixD2F5_MSI_MSG_CNTL 0x6000028 +#define ixD2F5_MSI_MSG_ADDR_LO 0x6000029 +#define ixD2F5_MSI_MSG_ADDR_HI 0x600002a +#define ixD2F5_MSI_MSG_DATA_64 0x600002b +#define ixD2F5_MSI_MSG_DATA 0x600002a +#define ixD2F5_SSID_CAP_LIST 0x6000030 +#define ixD2F5_SSID_CAP 0x6000031 +#define ixD2F5_MSI_MAP_CAP_LIST 0x6000032 +#define ixD2F5_MSI_MAP_CAP 0x6000032 +#define ixD2F5_MSI_MAP_ADDR_LO 0x6000033 +#define ixD2F5_MSI_MAP_ADDR_HI 0x6000034 +#define ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x6000040 +#define ixD2F5_PCIE_VENDOR_SPECIFIC_HDR 0x6000041 +#define ixD2F5_PCIE_VENDOR_SPECIFIC1 0x6000042 +#define ixD2F5_PCIE_VENDOR_SPECIFIC2 0x6000043 +#define ixD2F5_PCIE_VC_ENH_CAP_LIST 0x6000044 +#define ixD2F5_PCIE_PORT_VC_CAP_REG1 0x6000045 +#define ixD2F5_PCIE_PORT_VC_CAP_REG2 0x6000046 +#define ixD2F5_PCIE_PORT_VC_CNTL 0x6000047 +#define ixD2F5_PCIE_PORT_VC_STATUS 0x6000047 +#define ixD2F5_PCIE_VC0_RESOURCE_CAP 0x6000048 +#define ixD2F5_PCIE_VC0_RESOURCE_CNTL 0x6000049 +#define ixD2F5_PCIE_VC0_RESOURCE_STATUS 0x600004a +#define ixD2F5_PCIE_VC1_RESOURCE_CAP 0x600004b +#define ixD2F5_PCIE_VC1_RESOURCE_CNTL 0x600004c +#define ixD2F5_PCIE_VC1_RESOURCE_STATUS 0x600004d +#define ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x6000050 +#define ixD2F5_PCIE_DEV_SERIAL_NUM_DW1 0x6000051 +#define ixD2F5_PCIE_DEV_SERIAL_NUM_DW2 0x6000052 +#define ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x6000054 +#define ixD2F5_PCIE_UNCORR_ERR_STATUS 0x6000055 +#define ixD2F5_PCIE_UNCORR_ERR_MASK 0x6000056 +#define ixD2F5_PCIE_UNCORR_ERR_SEVERITY 0x6000057 +#define ixD2F5_PCIE_CORR_ERR_STATUS 0x6000058 +#define ixD2F5_PCIE_CORR_ERR_MASK 0x6000059 +#define ixD2F5_PCIE_ADV_ERR_CAP_CNTL 0x600005a +#define ixD2F5_PCIE_HDR_LOG0 0x600005b +#define ixD2F5_PCIE_HDR_LOG1 0x600005c +#define ixD2F5_PCIE_HDR_LOG2 0x600005d +#define ixD2F5_PCIE_HDR_LOG3 0x600005e +#define ixD2F5_PCIE_ROOT_ERR_CMD 0x600005f +#define ixD2F5_PCIE_ROOT_ERR_STATUS 0x6000060 +#define ixD2F5_PCIE_ERR_SRC_ID 0x6000061 +#define ixD2F5_PCIE_TLP_PREFIX_LOG0 0x6000062 +#define ixD2F5_PCIE_TLP_PREFIX_LOG1 0x6000063 +#define ixD2F5_PCIE_TLP_PREFIX_LOG2 0x6000064 +#define ixD2F5_PCIE_TLP_PREFIX_LOG3 0x6000065 +#define ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST 0x600009c +#define ixD2F5_PCIE_LINK_CNTL3 0x600009d +#define ixD2F5_PCIE_LANE_ERROR_STATUS 0x600009e +#define ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL 0x600009f +#define ixD2F5_PCIE_LANE_1_EQUALIZATION_CNTL 0x600009f +#define ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL 0x60000a0 +#define ixD2F5_PCIE_LANE_3_EQUALIZATION_CNTL 0x60000a0 +#define ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL 0x60000a1 +#define ixD2F5_PCIE_LANE_5_EQUALIZATION_CNTL 0x60000a1 +#define ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL 0x60000a2 +#define ixD2F5_PCIE_LANE_7_EQUALIZATION_CNTL 0x60000a2 +#define ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL 0x60000a3 +#define ixD2F5_PCIE_LANE_9_EQUALIZATION_CNTL 0x60000a3 +#define ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL 0x60000a4 +#define ixD2F5_PCIE_LANE_11_EQUALIZATION_CNTL 0x60000a4 +#define ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL 0x60000a5 +#define ixD2F5_PCIE_LANE_13_EQUALIZATION_CNTL 0x60000a5 +#define ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL 0x60000a6 +#define ixD2F5_PCIE_LANE_15_EQUALIZATION_CNTL 0x60000a6 +#define ixD2F5_PCIE_ACS_ENH_CAP_LIST 0x60000a8 +#define ixD2F5_PCIE_ACS_CAP 0x60000a9 +#define ixD2F5_PCIE_ACS_CNTL 0x60000a9 +#define ixD2F5_PCIE_MC_ENH_CAP_LIST 0x60000bc +#define ixD2F5_PCIE_MC_CAP 0x60000bd +#define ixD2F5_PCIE_MC_CNTL 0x60000bd +#define ixD2F5_PCIE_MC_ADDR0 0x60000be +#define ixD2F5_PCIE_MC_ADDR1 0x60000bf +#define ixD2F5_PCIE_MC_RCV0 0x60000c0 +#define ixD2F5_PCIE_MC_RCV1 0x60000c1 +#define ixD2F5_PCIE_MC_BLOCK_ALL0 0x60000c2 +#define ixD2F5_PCIE_MC_BLOCK_ALL1 0x60000c3 +#define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0 0x60000c4 +#define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1 0x60000c5 +#define ixD2F5_PCIE_MC_OVERLAY_BAR0 0x60000c6 +#define ixD2F5_PCIE_MC_OVERLAY_BAR1 0x60000c7 +#define ixD3F1_PCIE_PORT_INDEX 0x7000038 +#define ixD3F1_PCIE_PORT_DATA 0x7000039 +#define ixD3F1_PCIEP_RESERVED 0x0 +#define ixD3F1_PCIEP_SCRATCH 0x1 +#define ixD3F1_PCIEP_HW_DEBUG 0x2 +#define ixD3F1_PCIEP_PORT_CNTL 0x10 +#define ixD3F1_PCIE_TX_CNTL 0x20 +#define ixD3F1_PCIE_TX_REQUESTER_ID 0x21 +#define ixD3F1_PCIE_TX_VENDOR_SPECIFIC 0x22 +#define ixD3F1_PCIE_TX_REQUEST_NUM_CNTL 0x23 +#define ixD3F1_PCIE_TX_SEQ 0x24 +#define ixD3F1_PCIE_TX_REPLAY 0x25 +#define ixD3F1_PCIE_TX_ACK_LATENCY_LIMIT 0x26 +#define ixD3F1_PCIE_TX_CREDITS_ADVT_P 0x30 +#define ixD3F1_PCIE_TX_CREDITS_ADVT_NP 0x31 +#define ixD3F1_PCIE_TX_CREDITS_ADVT_CPL 0x32 +#define ixD3F1_PCIE_TX_CREDITS_INIT_P 0x33 +#define ixD3F1_PCIE_TX_CREDITS_INIT_NP 0x34 +#define ixD3F1_PCIE_TX_CREDITS_INIT_CPL 0x35 +#define ixD3F1_PCIE_TX_CREDITS_STATUS 0x36 +#define ixD3F1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 +#define ixD3F1_PCIE_P_PORT_LANE_STATUS 0x50 +#define ixD3F1_PCIE_FC_P 0x60 +#define ixD3F1_PCIE_FC_NP 0x61 +#define ixD3F1_PCIE_FC_CPL 0x62 +#define ixD3F1_PCIE_ERR_CNTL 0x6a +#define ixD3F1_PCIE_RX_CNTL 0x70 +#define ixD3F1_PCIE_RX_EXPECTED_SEQNUM 0x71 +#define ixD3F1_PCIE_RX_VENDOR_SPECIFIC 0x72 +#define ixD3F1_PCIE_RX_CNTL3 0x74 +#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_P 0x80 +#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 +#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 +#define ixD3F1_PCIEP_ERROR_INJECT_PHYSICAL 0x83 +#define ixD3F1_PCIEP_ERROR_INJECT_TRANSACTION 0x84 +#define ixD3F1_PCIE_LC_CNTL 0xa0 +#define ixD3F1_PCIE_LC_CNTL2 0xb1 +#define ixD3F1_PCIE_LC_CNTL3 0xb5 +#define ixD3F1_PCIE_LC_CNTL4 0xb6 +#define ixD3F1_PCIE_LC_CNTL5 0xb7 +#define ixD3F1_PCIE_LC_CNTL6 0xbb +#define ixD3F1_PCIE_LC_BW_CHANGE_CNTL 0xb2 +#define ixD3F1_PCIE_LC_TRAINING_CNTL 0xa1 +#define ixD3F1_PCIE_LC_LINK_WIDTH_CNTL 0xa2 +#define ixD3F1_PCIE_LC_N_FTS_CNTL 0xa3 +#define ixD3F1_PCIE_LC_SPEED_CNTL 0xa4 +#define ixD3F1_PCIE_LC_CDR_CNTL 0xb3 +#define ixD3F1_PCIE_LC_LANE_CNTL 0xb4 +#define ixD3F1_PCIE_LC_FORCE_COEFF 0xb8 +#define ixD3F1_PCIE_LC_BEST_EQ_SETTINGS 0xb9 +#define ixD3F1_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba +#define ixD3F1_PCIE_LC_STATE0 0xa5 +#define ixD3F1_PCIE_LC_STATE1 0xa6 +#define ixD3F1_PCIE_LC_STATE2 0xa7 +#define ixD3F1_PCIE_LC_STATE3 0xa8 +#define ixD3F1_PCIE_LC_STATE4 0xa9 +#define ixD3F1_PCIE_LC_STATE5 0xaa +#define ixD3F1_PCIEP_STRAP_LC 0xc0 +#define ixD3F1_PCIEP_STRAP_MISC 0xc1 +#define ixD3F1_PCIEP_BCH_ECC_CNTL 0xd0 +#define ixD3F1_PCIEP_HPGI_PRIVATE 0xd2 +#define ixD3F1_PCIEP_HPGI 0xda +#define ixD3F1_VENDOR_ID 0x7000000 +#define ixD3F1_DEVICE_ID 0x7000000 +#define ixD3F1_COMMAND 0x7000001 +#define ixD3F1_STATUS 0x7000001 +#define ixD3F1_REVISION_ID 0x7000002 +#define ixD3F1_PROG_INTERFACE 0x7000002 +#define ixD3F1_SUB_CLASS 0x7000002 +#define ixD3F1_BASE_CLASS 0x7000002 +#define ixD3F1_CACHE_LINE 0x7000003 +#define ixD3F1_LATENCY 0x7000003 +#define ixD3F1_HEADER 0x7000003 +#define ixD3F1_BIST 0x7000003 +#define ixD3F1_SUB_BUS_NUMBER_LATENCY 0x7000006 +#define ixD3F1_IO_BASE_LIMIT 0x7000007 +#define ixD3F1_SECONDARY_STATUS 0x7000007 +#define ixD3F1_MEM_BASE_LIMIT 0x7000008 +#define ixD3F1_PREF_BASE_LIMIT 0x7000009 +#define ixD3F1_PREF_BASE_UPPER 0x700000a +#define ixD3F1_PREF_LIMIT_UPPER 0x700000b +#define ixD3F1_IO_BASE_LIMIT_HI 0x700000c +#define ixD3F1_IRQ_BRIDGE_CNTL 0x700000f +#define ixD3F1_CAP_PTR 0x700000d +#define ixD3F1_INTERRUPT_LINE 0x700000f +#define ixD3F1_INTERRUPT_PIN 0x700000f +#define ixD3F1_EXT_BRIDGE_CNTL 0x7000010 +#define ixD3F1_PMI_CAP_LIST 0x7000014 +#define ixD3F1_PMI_CAP 0x7000014 +#define ixD3F1_PMI_STATUS_CNTL 0x7000015 +#define ixD3F1_PCIE_CAP_LIST 0x7000016 +#define ixD3F1_PCIE_CAP 0x7000016 +#define ixD3F1_DEVICE_CAP 0x7000017 +#define ixD3F1_DEVICE_CNTL 0x7000018 +#define ixD3F1_DEVICE_STATUS 0x7000018 +#define ixD3F1_LINK_CAP 0x7000019 +#define ixD3F1_LINK_CNTL 0x700001a +#define ixD3F1_LINK_STATUS 0x700001a +#define ixD3F1_SLOT_CAP 0x700001b +#define ixD3F1_SLOT_CNTL 0x700001c +#define ixD3F1_SLOT_STATUS 0x700001c +#define ixD3F1_ROOT_CNTL 0x700001d +#define ixD3F1_ROOT_CAP 0x700001d +#define ixD3F1_ROOT_STATUS 0x700001e +#define ixD3F1_DEVICE_CAP2 0x700001f +#define ixD3F1_DEVICE_CNTL2 0x7000020 +#define ixD3F1_DEVICE_STATUS2 0x7000020 +#define ixD3F1_LINK_CAP2 0x7000021 +#define ixD3F1_LINK_CNTL2 0x7000022 +#define ixD3F1_LINK_STATUS2 0x7000022 +#define ixD3F1_SLOT_CAP2 0x7000023 +#define ixD3F1_SLOT_CNTL2 0x7000024 +#define ixD3F1_SLOT_STATUS2 0x7000024 +#define ixD3F1_MSI_CAP_LIST 0x7000028 +#define ixD3F1_MSI_MSG_CNTL 0x7000028 +#define ixD3F1_MSI_MSG_ADDR_LO 0x7000029 +#define ixD3F1_MSI_MSG_ADDR_HI 0x700002a +#define ixD3F1_MSI_MSG_DATA_64 0x700002b +#define ixD3F1_MSI_MSG_DATA 0x700002a +#define ixD3F1_SSID_CAP_LIST 0x7000030 +#define ixD3F1_SSID_CAP 0x7000031 +#define ixD3F1_MSI_MAP_CAP_LIST 0x7000032 +#define ixD3F1_MSI_MAP_CAP 0x7000032 +#define ixD3F1_MSI_MAP_ADDR_LO 0x7000033 +#define ixD3F1_MSI_MAP_ADDR_HI 0x7000034 +#define ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x7000040 +#define ixD3F1_PCIE_VENDOR_SPECIFIC_HDR 0x7000041 +#define ixD3F1_PCIE_VENDOR_SPECIFIC1 0x7000042 +#define ixD3F1_PCIE_VENDOR_SPECIFIC2 0x7000043 +#define ixD3F1_PCIE_VC_ENH_CAP_LIST 0x7000044 +#define ixD3F1_PCIE_PORT_VC_CAP_REG1 0x7000045 +#define ixD3F1_PCIE_PORT_VC_CAP_REG2 0x7000046 +#define ixD3F1_PCIE_PORT_VC_CNTL 0x7000047 +#define ixD3F1_PCIE_PORT_VC_STATUS 0x7000047 +#define ixD3F1_PCIE_VC0_RESOURCE_CAP 0x7000048 +#define ixD3F1_PCIE_VC0_RESOURCE_CNTL 0x7000049 +#define ixD3F1_PCIE_VC0_RESOURCE_STATUS 0x700004a +#define ixD3F1_PCIE_VC1_RESOURCE_CAP 0x700004b +#define ixD3F1_PCIE_VC1_RESOURCE_CNTL 0x700004c +#define ixD3F1_PCIE_VC1_RESOURCE_STATUS 0x700004d +#define ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x7000050 +#define ixD3F1_PCIE_DEV_SERIAL_NUM_DW1 0x7000051 +#define ixD3F1_PCIE_DEV_SERIAL_NUM_DW2 0x7000052 +#define ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x7000054 +#define ixD3F1_PCIE_UNCORR_ERR_STATUS 0x7000055 +#define ixD3F1_PCIE_UNCORR_ERR_MASK 0x7000056 +#define ixD3F1_PCIE_UNCORR_ERR_SEVERITY 0x7000057 +#define ixD3F1_PCIE_CORR_ERR_STATUS 0x7000058 +#define ixD3F1_PCIE_CORR_ERR_MASK 0x7000059 +#define ixD3F1_PCIE_ADV_ERR_CAP_CNTL 0x700005a +#define ixD3F1_PCIE_HDR_LOG0 0x700005b +#define ixD3F1_PCIE_HDR_LOG1 0x700005c +#define ixD3F1_PCIE_HDR_LOG2 0x700005d +#define ixD3F1_PCIE_HDR_LOG3 0x700005e +#define ixD3F1_PCIE_ROOT_ERR_CMD 0x700005f +#define ixD3F1_PCIE_ROOT_ERR_STATUS 0x7000060 +#define ixD3F1_PCIE_ERR_SRC_ID 0x7000061 +#define ixD3F1_PCIE_TLP_PREFIX_LOG0 0x7000062 +#define ixD3F1_PCIE_TLP_PREFIX_LOG1 0x7000063 +#define ixD3F1_PCIE_TLP_PREFIX_LOG2 0x7000064 +#define ixD3F1_PCIE_TLP_PREFIX_LOG3 0x7000065 +#define ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST 0x700009c +#define ixD3F1_PCIE_LINK_CNTL3 0x700009d +#define ixD3F1_PCIE_LANE_ERROR_STATUS 0x700009e +#define ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL 0x700009f +#define ixD3F1_PCIE_LANE_1_EQUALIZATION_CNTL 0x700009f +#define ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL 0x70000a0 +#define ixD3F1_PCIE_LANE_3_EQUALIZATION_CNTL 0x70000a0 +#define ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL 0x70000a1 +#define ixD3F1_PCIE_LANE_5_EQUALIZATION_CNTL 0x70000a1 +#define ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL 0x70000a2 +#define ixD3F1_PCIE_LANE_7_EQUALIZATION_CNTL 0x70000a2 +#define ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL 0x70000a3 +#define ixD3F1_PCIE_LANE_9_EQUALIZATION_CNTL 0x70000a3 +#define ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL 0x70000a4 +#define ixD3F1_PCIE_LANE_11_EQUALIZATION_CNTL 0x70000a4 +#define ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL 0x70000a5 +#define ixD3F1_PCIE_LANE_13_EQUALIZATION_CNTL 0x70000a5 +#define ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL 0x70000a6 +#define ixD3F1_PCIE_LANE_15_EQUALIZATION_CNTL 0x70000a6 +#define ixD3F1_PCIE_ACS_ENH_CAP_LIST 0x70000a8 +#define ixD3F1_PCIE_ACS_CAP 0x70000a9 +#define ixD3F1_PCIE_ACS_CNTL 0x70000a9 +#define ixD3F1_PCIE_MC_ENH_CAP_LIST 0x70000bc +#define ixD3F1_PCIE_MC_CAP 0x70000bd +#define ixD3F1_PCIE_MC_CNTL 0x70000bd +#define ixD3F1_PCIE_MC_ADDR0 0x70000be +#define ixD3F1_PCIE_MC_ADDR1 0x70000bf +#define ixD3F1_PCIE_MC_RCV0 0x70000c0 +#define ixD3F1_PCIE_MC_RCV1 0x70000c1 +#define ixD3F1_PCIE_MC_BLOCK_ALL0 0x70000c2 +#define ixD3F1_PCIE_MC_BLOCK_ALL1 0x70000c3 +#define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x70000c4 +#define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x70000c5 +#define ixD3F1_PCIE_MC_OVERLAY_BAR0 0x70000c6 +#define ixD3F1_PCIE_MC_OVERLAY_BAR1 0x70000c7 +#define ixD3F2_PCIE_PORT_INDEX 0x8000038 +#define ixD3F2_PCIE_PORT_DATA 0x8000039 +#define ixD3F2_PCIEP_RESERVED 0x0 +#define ixD3F2_PCIEP_SCRATCH 0x1 +#define ixD3F2_PCIEP_HW_DEBUG 0x2 +#define ixD3F2_PCIEP_PORT_CNTL 0x10 +#define ixD3F2_PCIE_TX_CNTL 0x20 +#define ixD3F2_PCIE_TX_REQUESTER_ID 0x21 +#define ixD3F2_PCIE_TX_VENDOR_SPECIFIC 0x22 +#define ixD3F2_PCIE_TX_REQUEST_NUM_CNTL 0x23 +#define ixD3F2_PCIE_TX_SEQ 0x24 +#define ixD3F2_PCIE_TX_REPLAY 0x25 +#define ixD3F2_PCIE_TX_ACK_LATENCY_LIMIT 0x26 +#define ixD3F2_PCIE_TX_CREDITS_ADVT_P 0x30 +#define ixD3F2_PCIE_TX_CREDITS_ADVT_NP 0x31 +#define ixD3F2_PCIE_TX_CREDITS_ADVT_CPL 0x32 +#define ixD3F2_PCIE_TX_CREDITS_INIT_P 0x33 +#define ixD3F2_PCIE_TX_CREDITS_INIT_NP 0x34 +#define ixD3F2_PCIE_TX_CREDITS_INIT_CPL 0x35 +#define ixD3F2_PCIE_TX_CREDITS_STATUS 0x36 +#define ixD3F2_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 +#define ixD3F2_PCIE_P_PORT_LANE_STATUS 0x50 +#define ixD3F2_PCIE_FC_P 0x60 +#define ixD3F2_PCIE_FC_NP 0x61 +#define ixD3F2_PCIE_FC_CPL 0x62 +#define ixD3F2_PCIE_ERR_CNTL 0x6a +#define ixD3F2_PCIE_RX_CNTL 0x70 +#define ixD3F2_PCIE_RX_EXPECTED_SEQNUM 0x71 +#define ixD3F2_PCIE_RX_VENDOR_SPECIFIC 0x72 +#define ixD3F2_PCIE_RX_CNTL3 0x74 +#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_P 0x80 +#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 +#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 +#define ixD3F2_PCIEP_ERROR_INJECT_PHYSICAL 0x83 +#define ixD3F2_PCIEP_ERROR_INJECT_TRANSACTION 0x84 +#define ixD3F2_PCIE_LC_CNTL 0xa0 +#define ixD3F2_PCIE_LC_CNTL2 0xb1 +#define ixD3F2_PCIE_LC_CNTL3 0xb5 +#define ixD3F2_PCIE_LC_CNTL4 0xb6 +#define ixD3F2_PCIE_LC_CNTL5 0xb7 +#define ixD3F2_PCIE_LC_CNTL6 0xbb +#define ixD3F2_PCIE_LC_BW_CHANGE_CNTL 0xb2 +#define ixD3F2_PCIE_LC_TRAINING_CNTL 0xa1 +#define ixD3F2_PCIE_LC_LINK_WIDTH_CNTL 0xa2 +#define ixD3F2_PCIE_LC_N_FTS_CNTL 0xa3 +#define ixD3F2_PCIE_LC_SPEED_CNTL 0xa4 +#define ixD3F2_PCIE_LC_CDR_CNTL 0xb3 +#define ixD3F2_PCIE_LC_LANE_CNTL 0xb4 +#define ixD3F2_PCIE_LC_FORCE_COEFF 0xb8 +#define ixD3F2_PCIE_LC_BEST_EQ_SETTINGS 0xb9 +#define ixD3F2_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba +#define ixD3F2_PCIE_LC_STATE0 0xa5 +#define ixD3F2_PCIE_LC_STATE1 0xa6 +#define ixD3F2_PCIE_LC_STATE2 0xa7 +#define ixD3F2_PCIE_LC_STATE3 0xa8 +#define ixD3F2_PCIE_LC_STATE4 0xa9 +#define ixD3F2_PCIE_LC_STATE5 0xaa +#define ixD3F2_PCIEP_STRAP_LC 0xc0 +#define ixD3F2_PCIEP_STRAP_MISC 0xc1 +#define ixD3F2_PCIEP_BCH_ECC_CNTL 0xd0 +#define ixD3F2_PCIEP_HPGI_PRIVATE 0xd2 +#define ixD3F2_PCIEP_HPGI 0xda +#define ixD3F2_VENDOR_ID 0x8000000 +#define ixD3F2_DEVICE_ID 0x8000000 +#define ixD3F2_COMMAND 0x8000001 +#define ixD3F2_STATUS 0x8000001 +#define ixD3F2_REVISION_ID 0x8000002 +#define ixD3F2_PROG_INTERFACE 0x8000002 +#define ixD3F2_SUB_CLASS 0x8000002 +#define ixD3F2_BASE_CLASS 0x8000002 +#define ixD3F2_CACHE_LINE 0x8000003 +#define ixD3F2_LATENCY 0x8000003 +#define ixD3F2_HEADER 0x8000003 +#define ixD3F2_BIST 0x8000003 +#define ixD3F2_SUB_BUS_NUMBER_LATENCY 0x8000006 +#define ixD3F2_IO_BASE_LIMIT 0x8000007 +#define ixD3F2_SECONDARY_STATUS 0x8000007 +#define ixD3F2_MEM_BASE_LIMIT 0x8000008 +#define ixD3F2_PREF_BASE_LIMIT 0x8000009 +#define ixD3F2_PREF_BASE_UPPER 0x800000a +#define ixD3F2_PREF_LIMIT_UPPER 0x800000b +#define ixD3F2_IO_BASE_LIMIT_HI 0x800000c +#define ixD3F2_IRQ_BRIDGE_CNTL 0x800000f +#define ixD3F2_CAP_PTR 0x800000d +#define ixD3F2_INTERRUPT_LINE 0x800000f +#define ixD3F2_INTERRUPT_PIN 0x800000f +#define ixD3F2_EXT_BRIDGE_CNTL 0x8000010 +#define ixD3F2_PMI_CAP_LIST 0x8000014 +#define ixD3F2_PMI_CAP 0x8000014 +#define ixD3F2_PMI_STATUS_CNTL 0x8000015 +#define ixD3F2_PCIE_CAP_LIST 0x8000016 +#define ixD3F2_PCIE_CAP 0x8000016 +#define ixD3F2_DEVICE_CAP 0x8000017 +#define ixD3F2_DEVICE_CNTL 0x8000018 +#define ixD3F2_DEVICE_STATUS 0x8000018 +#define ixD3F2_LINK_CAP 0x8000019 +#define ixD3F2_LINK_CNTL 0x800001a +#define ixD3F2_LINK_STATUS 0x800001a +#define ixD3F2_SLOT_CAP 0x800001b +#define ixD3F2_SLOT_CNTL 0x800001c +#define ixD3F2_SLOT_STATUS 0x800001c +#define ixD3F2_ROOT_CNTL 0x800001d +#define ixD3F2_ROOT_CAP 0x800001d +#define ixD3F2_ROOT_STATUS 0x800001e +#define ixD3F2_DEVICE_CAP2 0x800001f +#define ixD3F2_DEVICE_CNTL2 0x8000020 +#define ixD3F2_DEVICE_STATUS2 0x8000020 +#define ixD3F2_LINK_CAP2 0x8000021 +#define ixD3F2_LINK_CNTL2 0x8000022 +#define ixD3F2_LINK_STATUS2 0x8000022 +#define ixD3F2_SLOT_CAP2 0x8000023 +#define ixD3F2_SLOT_CNTL2 0x8000024 +#define ixD3F2_SLOT_STATUS2 0x8000024 +#define ixD3F2_MSI_CAP_LIST 0x8000028 +#define ixD3F2_MSI_MSG_CNTL 0x8000028 +#define ixD3F2_MSI_MSG_ADDR_LO 0x8000029 +#define ixD3F2_MSI_MSG_ADDR_HI 0x800002a +#define ixD3F2_MSI_MSG_DATA_64 0x800002b +#define ixD3F2_MSI_MSG_DATA 0x800002a +#define ixD3F2_SSID_CAP_LIST 0x8000030 +#define ixD3F2_SSID_CAP 0x8000031 +#define ixD3F2_MSI_MAP_CAP_LIST 0x8000032 +#define ixD3F2_MSI_MAP_CAP 0x8000032 +#define ixD3F2_MSI_MAP_ADDR_LO 0x8000033 +#define ixD3F2_MSI_MAP_ADDR_HI 0x8000034 +#define ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x8000040 +#define ixD3F2_PCIE_VENDOR_SPECIFIC_HDR 0x8000041 +#define ixD3F2_PCIE_VENDOR_SPECIFIC1 0x8000042 +#define ixD3F2_PCIE_VENDOR_SPECIFIC2 0x8000043 +#define ixD3F2_PCIE_VC_ENH_CAP_LIST 0x8000044 +#define ixD3F2_PCIE_PORT_VC_CAP_REG1 0x8000045 +#define ixD3F2_PCIE_PORT_VC_CAP_REG2 0x8000046 +#define ixD3F2_PCIE_PORT_VC_CNTL 0x8000047 +#define ixD3F2_PCIE_PORT_VC_STATUS 0x8000047 +#define ixD3F2_PCIE_VC0_RESOURCE_CAP 0x8000048 +#define ixD3F2_PCIE_VC0_RESOURCE_CNTL 0x8000049 +#define ixD3F2_PCIE_VC0_RESOURCE_STATUS 0x800004a +#define ixD3F2_PCIE_VC1_RESOURCE_CAP 0x800004b +#define ixD3F2_PCIE_VC1_RESOURCE_CNTL 0x800004c +#define ixD3F2_PCIE_VC1_RESOURCE_STATUS 0x800004d +#define ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x8000050 +#define ixD3F2_PCIE_DEV_SERIAL_NUM_DW1 0x8000051 +#define ixD3F2_PCIE_DEV_SERIAL_NUM_DW2 0x8000052 +#define ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x8000054 +#define ixD3F2_PCIE_UNCORR_ERR_STATUS 0x8000055 +#define ixD3F2_PCIE_UNCORR_ERR_MASK 0x8000056 +#define ixD3F2_PCIE_UNCORR_ERR_SEVERITY 0x8000057 +#define ixD3F2_PCIE_CORR_ERR_STATUS 0x8000058 +#define ixD3F2_PCIE_CORR_ERR_MASK 0x8000059 +#define ixD3F2_PCIE_ADV_ERR_CAP_CNTL 0x800005a +#define ixD3F2_PCIE_HDR_LOG0 0x800005b +#define ixD3F2_PCIE_HDR_LOG1 0x800005c +#define ixD3F2_PCIE_HDR_LOG2 0x800005d +#define ixD3F2_PCIE_HDR_LOG3 0x800005e +#define ixD3F2_PCIE_ROOT_ERR_CMD 0x800005f +#define ixD3F2_PCIE_ROOT_ERR_STATUS 0x8000060 +#define ixD3F2_PCIE_ERR_SRC_ID 0x8000061 +#define ixD3F2_PCIE_TLP_PREFIX_LOG0 0x8000062 +#define ixD3F2_PCIE_TLP_PREFIX_LOG1 0x8000063 +#define ixD3F2_PCIE_TLP_PREFIX_LOG2 0x8000064 +#define ixD3F2_PCIE_TLP_PREFIX_LOG3 0x8000065 +#define ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST 0x800009c +#define ixD3F2_PCIE_LINK_CNTL3 0x800009d +#define ixD3F2_PCIE_LANE_ERROR_STATUS 0x800009e +#define ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL 0x800009f +#define ixD3F2_PCIE_LANE_1_EQUALIZATION_CNTL 0x800009f +#define ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL 0x80000a0 +#define ixD3F2_PCIE_LANE_3_EQUALIZATION_CNTL 0x80000a0 +#define ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL 0x80000a1 +#define ixD3F2_PCIE_LANE_5_EQUALIZATION_CNTL 0x80000a1 +#define ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL 0x80000a2 +#define ixD3F2_PCIE_LANE_7_EQUALIZATION_CNTL 0x80000a2 +#define ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL 0x80000a3 +#define ixD3F2_PCIE_LANE_9_EQUALIZATION_CNTL 0x80000a3 +#define ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL 0x80000a4 +#define ixD3F2_PCIE_LANE_11_EQUALIZATION_CNTL 0x80000a4 +#define ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL 0x80000a5 +#define ixD3F2_PCIE_LANE_13_EQUALIZATION_CNTL 0x80000a5 +#define ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL 0x80000a6 +#define ixD3F2_PCIE_LANE_15_EQUALIZATION_CNTL 0x80000a6 +#define ixD3F2_PCIE_ACS_ENH_CAP_LIST 0x80000a8 +#define ixD3F2_PCIE_ACS_CAP 0x80000a9 +#define ixD3F2_PCIE_ACS_CNTL 0x80000a9 +#define ixD3F2_PCIE_MC_ENH_CAP_LIST 0x80000bc +#define ixD3F2_PCIE_MC_CAP 0x80000bd +#define ixD3F2_PCIE_MC_CNTL 0x80000bd +#define ixD3F2_PCIE_MC_ADDR0 0x80000be +#define ixD3F2_PCIE_MC_ADDR1 0x80000bf +#define ixD3F2_PCIE_MC_RCV0 0x80000c0 +#define ixD3F2_PCIE_MC_RCV1 0x80000c1 +#define ixD3F2_PCIE_MC_BLOCK_ALL0 0x80000c2 +#define ixD3F2_PCIE_MC_BLOCK_ALL1 0x80000c3 +#define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x80000c4 +#define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x80000c5 +#define ixD3F2_PCIE_MC_OVERLAY_BAR0 0x80000c6 +#define ixD3F2_PCIE_MC_OVERLAY_BAR1 0x80000c7 +#define ixD3F3_PCIE_PORT_INDEX 0x9000038 +#define ixD3F3_PCIE_PORT_DATA 0x9000039 +#define ixD3F3_PCIEP_RESERVED 0x0 +#define ixD3F3_PCIEP_SCRATCH 0x1 +#define ixD3F3_PCIEP_HW_DEBUG 0x2 +#define ixD3F3_PCIEP_PORT_CNTL 0x10 +#define ixD3F3_PCIE_TX_CNTL 0x20 +#define ixD3F3_PCIE_TX_REQUESTER_ID 0x21 +#define ixD3F3_PCIE_TX_VENDOR_SPECIFIC 0x22 +#define ixD3F3_PCIE_TX_REQUEST_NUM_CNTL 0x23 +#define ixD3F3_PCIE_TX_SEQ 0x24 +#define ixD3F3_PCIE_TX_REPLAY 0x25 +#define ixD3F3_PCIE_TX_ACK_LATENCY_LIMIT 0x26 +#define ixD3F3_PCIE_TX_CREDITS_ADVT_P 0x30 +#define ixD3F3_PCIE_TX_CREDITS_ADVT_NP 0x31 +#define ixD3F3_PCIE_TX_CREDITS_ADVT_CPL 0x32 +#define ixD3F3_PCIE_TX_CREDITS_INIT_P 0x33 +#define ixD3F3_PCIE_TX_CREDITS_INIT_NP 0x34 +#define ixD3F3_PCIE_TX_CREDITS_INIT_CPL 0x35 +#define ixD3F3_PCIE_TX_CREDITS_STATUS 0x36 +#define ixD3F3_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 +#define ixD3F3_PCIE_P_PORT_LANE_STATUS 0x50 +#define ixD3F3_PCIE_FC_P 0x60 +#define ixD3F3_PCIE_FC_NP 0x61 +#define ixD3F3_PCIE_FC_CPL 0x62 +#define ixD3F3_PCIE_ERR_CNTL 0x6a +#define ixD3F3_PCIE_RX_CNTL 0x70 +#define ixD3F3_PCIE_RX_EXPECTED_SEQNUM 0x71 +#define ixD3F3_PCIE_RX_VENDOR_SPECIFIC 0x72 +#define ixD3F3_PCIE_RX_CNTL3 0x74 +#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_P 0x80 +#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 +#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 +#define ixD3F3_PCIEP_ERROR_INJECT_PHYSICAL 0x83 +#define ixD3F3_PCIEP_ERROR_INJECT_TRANSACTION 0x84 +#define ixD3F3_PCIE_LC_CNTL 0xa0 +#define ixD3F3_PCIE_LC_CNTL2 0xb1 +#define ixD3F3_PCIE_LC_CNTL3 0xb5 +#define ixD3F3_PCIE_LC_CNTL4 0xb6 +#define ixD3F3_PCIE_LC_CNTL5 0xb7 +#define ixD3F3_PCIE_LC_CNTL6 0xbb +#define ixD3F3_PCIE_LC_BW_CHANGE_CNTL 0xb2 +#define ixD3F3_PCIE_LC_TRAINING_CNTL 0xa1 +#define ixD3F3_PCIE_LC_LINK_WIDTH_CNTL 0xa2 +#define ixD3F3_PCIE_LC_N_FTS_CNTL 0xa3 +#define ixD3F3_PCIE_LC_SPEED_CNTL 0xa4 +#define ixD3F3_PCIE_LC_CDR_CNTL 0xb3 +#define ixD3F3_PCIE_LC_LANE_CNTL 0xb4 +#define ixD3F3_PCIE_LC_FORCE_COEFF 0xb8 +#define ixD3F3_PCIE_LC_BEST_EQ_SETTINGS 0xb9 +#define ixD3F3_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba +#define ixD3F3_PCIE_LC_STATE0 0xa5 +#define ixD3F3_PCIE_LC_STATE1 0xa6 +#define ixD3F3_PCIE_LC_STATE2 0xa7 +#define ixD3F3_PCIE_LC_STATE3 0xa8 +#define ixD3F3_PCIE_LC_STATE4 0xa9 +#define ixD3F3_PCIE_LC_STATE5 0xaa +#define ixD3F3_PCIEP_STRAP_LC 0xc0 +#define ixD3F3_PCIEP_STRAP_MISC 0xc1 +#define ixD3F3_PCIEP_BCH_ECC_CNTL 0xd0 +#define ixD3F3_PCIEP_HPGI_PRIVATE 0xd2 +#define ixD3F3_PCIEP_HPGI 0xda +#define ixD3F3_VENDOR_ID 0x9000000 +#define ixD3F3_DEVICE_ID 0x9000000 +#define ixD3F3_COMMAND 0x9000001 +#define ixD3F3_STATUS 0x9000001 +#define ixD3F3_REVISION_ID 0x9000002 +#define ixD3F3_PROG_INTERFACE 0x9000002 +#define ixD3F3_SUB_CLASS 0x9000002 +#define ixD3F3_BASE_CLASS 0x9000002 +#define ixD3F3_CACHE_LINE 0x9000003 +#define ixD3F3_LATENCY 0x9000003 +#define ixD3F3_HEADER 0x9000003 +#define ixD3F3_BIST 0x9000003 +#define ixD3F3_SUB_BUS_NUMBER_LATENCY 0x9000006 +#define ixD3F3_IO_BASE_LIMIT 0x9000007 +#define ixD3F3_SECONDARY_STATUS 0x9000007 +#define ixD3F3_MEM_BASE_LIMIT 0x9000008 +#define ixD3F3_PREF_BASE_LIMIT 0x9000009 +#define ixD3F3_PREF_BASE_UPPER 0x900000a +#define ixD3F3_PREF_LIMIT_UPPER 0x900000b +#define ixD3F3_IO_BASE_LIMIT_HI 0x900000c +#define ixD3F3_IRQ_BRIDGE_CNTL 0x900000f +#define ixD3F3_CAP_PTR 0x900000d +#define ixD3F3_INTERRUPT_LINE 0x900000f +#define ixD3F3_INTERRUPT_PIN 0x900000f +#define ixD3F3_EXT_BRIDGE_CNTL 0x9000010 +#define ixD3F3_PMI_CAP_LIST 0x9000014 +#define ixD3F3_PMI_CAP 0x9000014 +#define ixD3F3_PMI_STATUS_CNTL 0x9000015 +#define ixD3F3_PCIE_CAP_LIST 0x9000016 +#define ixD3F3_PCIE_CAP 0x9000016 +#define ixD3F3_DEVICE_CAP 0x9000017 +#define ixD3F3_DEVICE_CNTL 0x9000018 +#define ixD3F3_DEVICE_STATUS 0x9000018 +#define ixD3F3_LINK_CAP 0x9000019 +#define ixD3F3_LINK_CNTL 0x900001a +#define ixD3F3_LINK_STATUS 0x900001a +#define ixD3F3_SLOT_CAP 0x900001b +#define ixD3F3_SLOT_CNTL 0x900001c +#define ixD3F3_SLOT_STATUS 0x900001c +#define ixD3F3_ROOT_CNTL 0x900001d +#define ixD3F3_ROOT_CAP 0x900001d +#define ixD3F3_ROOT_STATUS 0x900001e +#define ixD3F3_DEVICE_CAP2 0x900001f +#define ixD3F3_DEVICE_CNTL2 0x9000020 +#define ixD3F3_DEVICE_STATUS2 0x9000020 +#define ixD3F3_LINK_CAP2 0x9000021 +#define ixD3F3_LINK_CNTL2 0x9000022 +#define ixD3F3_LINK_STATUS2 0x9000022 +#define ixD3F3_SLOT_CAP2 0x9000023 +#define ixD3F3_SLOT_CNTL2 0x9000024 +#define ixD3F3_SLOT_STATUS2 0x9000024 +#define ixD3F3_MSI_CAP_LIST 0x9000028 +#define ixD3F3_MSI_MSG_CNTL 0x9000028 +#define ixD3F3_MSI_MSG_ADDR_LO 0x9000029 +#define ixD3F3_MSI_MSG_ADDR_HI 0x900002a +#define ixD3F3_MSI_MSG_DATA_64 0x900002b +#define ixD3F3_MSI_MSG_DATA 0x900002a +#define ixD3F3_SSID_CAP_LIST 0x9000030 +#define ixD3F3_SSID_CAP 0x9000031 +#define ixD3F3_MSI_MAP_CAP_LIST 0x9000032 +#define ixD3F3_MSI_MAP_CAP 0x9000032 +#define ixD3F3_MSI_MAP_ADDR_LO 0x9000033 +#define ixD3F3_MSI_MAP_ADDR_HI 0x9000034 +#define ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x9000040 +#define ixD3F3_PCIE_VENDOR_SPECIFIC_HDR 0x9000041 +#define ixD3F3_PCIE_VENDOR_SPECIFIC1 0x9000042 +#define ixD3F3_PCIE_VENDOR_SPECIFIC2 0x9000043 +#define ixD3F3_PCIE_VC_ENH_CAP_LIST 0x9000044 +#define ixD3F3_PCIE_PORT_VC_CAP_REG1 0x9000045 +#define ixD3F3_PCIE_PORT_VC_CAP_REG2 0x9000046 +#define ixD3F3_PCIE_PORT_VC_CNTL 0x9000047 +#define ixD3F3_PCIE_PORT_VC_STATUS 0x9000047 +#define ixD3F3_PCIE_VC0_RESOURCE_CAP 0x9000048 +#define ixD3F3_PCIE_VC0_RESOURCE_CNTL 0x9000049 +#define ixD3F3_PCIE_VC0_RESOURCE_STATUS 0x900004a +#define ixD3F3_PCIE_VC1_RESOURCE_CAP 0x900004b +#define ixD3F3_PCIE_VC1_RESOURCE_CNTL 0x900004c +#define ixD3F3_PCIE_VC1_RESOURCE_STATUS 0x900004d +#define ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x9000050 +#define ixD3F3_PCIE_DEV_SERIAL_NUM_DW1 0x9000051 +#define ixD3F3_PCIE_DEV_SERIAL_NUM_DW2 0x9000052 +#define ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x9000054 +#define ixD3F3_PCIE_UNCORR_ERR_STATUS 0x9000055 +#define ixD3F3_PCIE_UNCORR_ERR_MASK 0x9000056 +#define ixD3F3_PCIE_UNCORR_ERR_SEVERITY 0x9000057 +#define ixD3F3_PCIE_CORR_ERR_STATUS 0x9000058 +#define ixD3F3_PCIE_CORR_ERR_MASK 0x9000059 +#define ixD3F3_PCIE_ADV_ERR_CAP_CNTL 0x900005a +#define ixD3F3_PCIE_HDR_LOG0 0x900005b +#define ixD3F3_PCIE_HDR_LOG1 0x900005c +#define ixD3F3_PCIE_HDR_LOG2 0x900005d +#define ixD3F3_PCIE_HDR_LOG3 0x900005e +#define ixD3F3_PCIE_ROOT_ERR_CMD 0x900005f +#define ixD3F3_PCIE_ROOT_ERR_STATUS 0x9000060 +#define ixD3F3_PCIE_ERR_SRC_ID 0x9000061 +#define ixD3F3_PCIE_TLP_PREFIX_LOG0 0x9000062 +#define ixD3F3_PCIE_TLP_PREFIX_LOG1 0x9000063 +#define ixD3F3_PCIE_TLP_PREFIX_LOG2 0x9000064 +#define ixD3F3_PCIE_TLP_PREFIX_LOG3 0x9000065 +#define ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST 0x900009c +#define ixD3F3_PCIE_LINK_CNTL3 0x900009d +#define ixD3F3_PCIE_LANE_ERROR_STATUS 0x900009e +#define ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL 0x900009f +#define ixD3F3_PCIE_LANE_1_EQUALIZATION_CNTL 0x900009f +#define ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL 0x90000a0 +#define ixD3F3_PCIE_LANE_3_EQUALIZATION_CNTL 0x90000a0 +#define ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL 0x90000a1 +#define ixD3F3_PCIE_LANE_5_EQUALIZATION_CNTL 0x90000a1 +#define ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL 0x90000a2 +#define ixD3F3_PCIE_LANE_7_EQUALIZATION_CNTL 0x90000a2 +#define ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL 0x90000a3 +#define ixD3F3_PCIE_LANE_9_EQUALIZATION_CNTL 0x90000a3 +#define ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL 0x90000a4 +#define ixD3F3_PCIE_LANE_11_EQUALIZATION_CNTL 0x90000a4 +#define ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL 0x90000a5 +#define ixD3F3_PCIE_LANE_13_EQUALIZATION_CNTL 0x90000a5 +#define ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL 0x90000a6 +#define ixD3F3_PCIE_LANE_15_EQUALIZATION_CNTL 0x90000a6 +#define ixD3F3_PCIE_ACS_ENH_CAP_LIST 0x90000a8 +#define ixD3F3_PCIE_ACS_CAP 0x90000a9 +#define ixD3F3_PCIE_ACS_CNTL 0x90000a9 +#define ixD3F3_PCIE_MC_ENH_CAP_LIST 0x90000bc +#define ixD3F3_PCIE_MC_CAP 0x90000bd +#define ixD3F3_PCIE_MC_CNTL 0x90000bd +#define ixD3F3_PCIE_MC_ADDR0 0x90000be +#define ixD3F3_PCIE_MC_ADDR1 0x90000bf +#define ixD3F3_PCIE_MC_RCV0 0x90000c0 +#define ixD3F3_PCIE_MC_RCV1 0x90000c1 +#define ixD3F3_PCIE_MC_BLOCK_ALL0 0x90000c2 +#define ixD3F3_PCIE_MC_BLOCK_ALL1 0x90000c3 +#define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0 0x90000c4 +#define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1 0x90000c5 +#define ixD3F3_PCIE_MC_OVERLAY_BAR0 0x90000c6 +#define ixD3F3_PCIE_MC_OVERLAY_BAR1 0x90000c7 +#define ixD3F4_PCIE_PORT_INDEX 0xa000038 +#define ixD3F4_PCIE_PORT_DATA 0xa000039 +#define ixD3F4_PCIEP_RESERVED 0x0 +#define ixD3F4_PCIEP_SCRATCH 0x1 +#define ixD3F4_PCIEP_HW_DEBUG 0x2 +#define ixD3F4_PCIEP_PORT_CNTL 0x10 +#define ixD3F4_PCIE_TX_CNTL 0x20 +#define ixD3F4_PCIE_TX_REQUESTER_ID 0x21 +#define ixD3F4_PCIE_TX_VENDOR_SPECIFIC 0x22 +#define ixD3F4_PCIE_TX_REQUEST_NUM_CNTL 0x23 +#define ixD3F4_PCIE_TX_SEQ 0x24 +#define ixD3F4_PCIE_TX_REPLAY 0x25 +#define ixD3F4_PCIE_TX_ACK_LATENCY_LIMIT 0x26 +#define ixD3F4_PCIE_TX_CREDITS_ADVT_P 0x30 +#define ixD3F4_PCIE_TX_CREDITS_ADVT_NP 0x31 +#define ixD3F4_PCIE_TX_CREDITS_ADVT_CPL 0x32 +#define ixD3F4_PCIE_TX_CREDITS_INIT_P 0x33 +#define ixD3F4_PCIE_TX_CREDITS_INIT_NP 0x34 +#define ixD3F4_PCIE_TX_CREDITS_INIT_CPL 0x35 +#define ixD3F4_PCIE_TX_CREDITS_STATUS 0x36 +#define ixD3F4_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 +#define ixD3F4_PCIE_P_PORT_LANE_STATUS 0x50 +#define ixD3F4_PCIE_FC_P 0x60 +#define ixD3F4_PCIE_FC_NP 0x61 +#define ixD3F4_PCIE_FC_CPL 0x62 +#define ixD3F4_PCIE_ERR_CNTL 0x6a +#define ixD3F4_PCIE_RX_CNTL 0x70 +#define ixD3F4_PCIE_RX_EXPECTED_SEQNUM 0x71 +#define ixD3F4_PCIE_RX_VENDOR_SPECIFIC 0x72 +#define ixD3F4_PCIE_RX_CNTL3 0x74 +#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_P 0x80 +#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 +#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 +#define ixD3F4_PCIEP_ERROR_INJECT_PHYSICAL 0x83 +#define ixD3F4_PCIEP_ERROR_INJECT_TRANSACTION 0x84 +#define ixD3F4_PCIE_LC_CNTL 0xa0 +#define ixD3F4_PCIE_LC_CNTL2 0xb1 +#define ixD3F4_PCIE_LC_CNTL3 0xb5 +#define ixD3F4_PCIE_LC_CNTL4 0xb6 +#define ixD3F4_PCIE_LC_CNTL5 0xb7 +#define ixD3F4_PCIE_LC_CNTL6 0xbb +#define ixD3F4_PCIE_LC_BW_CHANGE_CNTL 0xb2 +#define ixD3F4_PCIE_LC_TRAINING_CNTL 0xa1 +#define ixD3F4_PCIE_LC_LINK_WIDTH_CNTL 0xa2 +#define ixD3F4_PCIE_LC_N_FTS_CNTL 0xa3 +#define ixD3F4_PCIE_LC_SPEED_CNTL 0xa4 +#define ixD3F4_PCIE_LC_CDR_CNTL 0xb3 +#define ixD3F4_PCIE_LC_LANE_CNTL 0xb4 +#define ixD3F4_PCIE_LC_FORCE_COEFF 0xb8 +#define ixD3F4_PCIE_LC_BEST_EQ_SETTINGS 0xb9 +#define ixD3F4_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba +#define ixD3F4_PCIE_LC_STATE0 0xa5 +#define ixD3F4_PCIE_LC_STATE1 0xa6 +#define ixD3F4_PCIE_LC_STATE2 0xa7 +#define ixD3F4_PCIE_LC_STATE3 0xa8 +#define ixD3F4_PCIE_LC_STATE4 0xa9 +#define ixD3F4_PCIE_LC_STATE5 0xaa +#define ixD3F4_PCIEP_STRAP_LC 0xc0 +#define ixD3F4_PCIEP_STRAP_MISC 0xc1 +#define ixD3F4_PCIEP_BCH_ECC_CNTL 0xd0 +#define ixD3F4_PCIEP_HPGI_PRIVATE 0xd2 +#define ixD3F4_PCIEP_HPGI 0xda +#define ixD3F4_VENDOR_ID 0xa000000 +#define ixD3F4_DEVICE_ID 0xa000000 +#define ixD3F4_COMMAND 0xa000001 +#define ixD3F4_STATUS 0xa000001 +#define ixD3F4_REVISION_ID 0xa000002 +#define ixD3F4_PROG_INTERFACE 0xa000002 +#define ixD3F4_SUB_CLASS 0xa000002 +#define ixD3F4_BASE_CLASS 0xa000002 +#define ixD3F4_CACHE_LINE 0xa000003 +#define ixD3F4_LATENCY 0xa000003 +#define ixD3F4_HEADER 0xa000003 +#define ixD3F4_BIST 0xa000003 +#define ixD3F4_SUB_BUS_NUMBER_LATENCY 0xa000006 +#define ixD3F4_IO_BASE_LIMIT 0xa000007 +#define ixD3F4_SECONDARY_STATUS 0xa000007 +#define ixD3F4_MEM_BASE_LIMIT 0xa000008 +#define ixD3F4_PREF_BASE_LIMIT 0xa000009 +#define ixD3F4_PREF_BASE_UPPER 0xa00000a +#define ixD3F4_PREF_LIMIT_UPPER 0xa00000b +#define ixD3F4_IO_BASE_LIMIT_HI 0xa00000c +#define ixD3F4_IRQ_BRIDGE_CNTL 0xa00000f +#define ixD3F4_CAP_PTR 0xa00000d +#define ixD3F4_INTERRUPT_LINE 0xa00000f +#define ixD3F4_INTERRUPT_PIN 0xa00000f +#define ixD3F4_EXT_BRIDGE_CNTL 0xa000010 +#define ixD3F4_PMI_CAP_LIST 0xa000014 +#define ixD3F4_PMI_CAP 0xa000014 +#define ixD3F4_PMI_STATUS_CNTL 0xa000015 +#define ixD3F4_PCIE_CAP_LIST 0xa000016 +#define ixD3F4_PCIE_CAP 0xa000016 +#define ixD3F4_DEVICE_CAP 0xa000017 +#define ixD3F4_DEVICE_CNTL 0xa000018 +#define ixD3F4_DEVICE_STATUS 0xa000018 +#define ixD3F4_LINK_CAP 0xa000019 +#define ixD3F4_LINK_CNTL 0xa00001a +#define ixD3F4_LINK_STATUS 0xa00001a +#define ixD3F4_SLOT_CAP 0xa00001b +#define ixD3F4_SLOT_CNTL 0xa00001c +#define ixD3F4_SLOT_STATUS 0xa00001c +#define ixD3F4_ROOT_CNTL 0xa00001d +#define ixD3F4_ROOT_CAP 0xa00001d +#define ixD3F4_ROOT_STATUS 0xa00001e +#define ixD3F4_DEVICE_CAP2 0xa00001f +#define ixD3F4_DEVICE_CNTL2 0xa000020 +#define ixD3F4_DEVICE_STATUS2 0xa000020 +#define ixD3F4_LINK_CAP2 0xa000021 +#define ixD3F4_LINK_CNTL2 0xa000022 +#define ixD3F4_LINK_STATUS2 0xa000022 +#define ixD3F4_SLOT_CAP2 0xa000023 +#define ixD3F4_SLOT_CNTL2 0xa000024 +#define ixD3F4_SLOT_STATUS2 0xa000024 +#define ixD3F4_MSI_CAP_LIST 0xa000028 +#define ixD3F4_MSI_MSG_CNTL 0xa000028 +#define ixD3F4_MSI_MSG_ADDR_LO 0xa000029 +#define ixD3F4_MSI_MSG_ADDR_HI 0xa00002a +#define ixD3F4_MSI_MSG_DATA_64 0xa00002b +#define ixD3F4_MSI_MSG_DATA 0xa00002a +#define ixD3F4_SSID_CAP_LIST 0xa000030 +#define ixD3F4_SSID_CAP 0xa000031 +#define ixD3F4_MSI_MAP_CAP_LIST 0xa000032 +#define ixD3F4_MSI_MAP_CAP 0xa000032 +#define ixD3F4_MSI_MAP_ADDR_LO 0xa000033 +#define ixD3F4_MSI_MAP_ADDR_HI 0xa000034 +#define ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xa000040 +#define ixD3F4_PCIE_VENDOR_SPECIFIC_HDR 0xa000041 +#define ixD3F4_PCIE_VENDOR_SPECIFIC1 0xa000042 +#define ixD3F4_PCIE_VENDOR_SPECIFIC2 0xa000043 +#define ixD3F4_PCIE_VC_ENH_CAP_LIST 0xa000044 +#define ixD3F4_PCIE_PORT_VC_CAP_REG1 0xa000045 +#define ixD3F4_PCIE_PORT_VC_CAP_REG2 0xa000046 +#define ixD3F4_PCIE_PORT_VC_CNTL 0xa000047 +#define ixD3F4_PCIE_PORT_VC_STATUS 0xa000047 +#define ixD3F4_PCIE_VC0_RESOURCE_CAP 0xa000048 +#define ixD3F4_PCIE_VC0_RESOURCE_CNTL 0xa000049 +#define ixD3F4_PCIE_VC0_RESOURCE_STATUS 0xa00004a +#define ixD3F4_PCIE_VC1_RESOURCE_CAP 0xa00004b +#define ixD3F4_PCIE_VC1_RESOURCE_CNTL 0xa00004c +#define ixD3F4_PCIE_VC1_RESOURCE_STATUS 0xa00004d +#define ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xa000050 +#define ixD3F4_PCIE_DEV_SERIAL_NUM_DW1 0xa000051 +#define ixD3F4_PCIE_DEV_SERIAL_NUM_DW2 0xa000052 +#define ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xa000054 +#define ixD3F4_PCIE_UNCORR_ERR_STATUS 0xa000055 +#define ixD3F4_PCIE_UNCORR_ERR_MASK 0xa000056 +#define ixD3F4_PCIE_UNCORR_ERR_SEVERITY 0xa000057 +#define ixD3F4_PCIE_CORR_ERR_STATUS 0xa000058 +#define ixD3F4_PCIE_CORR_ERR_MASK 0xa000059 +#define ixD3F4_PCIE_ADV_ERR_CAP_CNTL 0xa00005a +#define ixD3F4_PCIE_HDR_LOG0 0xa00005b +#define ixD3F4_PCIE_HDR_LOG1 0xa00005c +#define ixD3F4_PCIE_HDR_LOG2 0xa00005d +#define ixD3F4_PCIE_HDR_LOG3 0xa00005e +#define ixD3F4_PCIE_ROOT_ERR_CMD 0xa00005f +#define ixD3F4_PCIE_ROOT_ERR_STATUS 0xa000060 +#define ixD3F4_PCIE_ERR_SRC_ID 0xa000061 +#define ixD3F4_PCIE_TLP_PREFIX_LOG0 0xa000062 +#define ixD3F4_PCIE_TLP_PREFIX_LOG1 0xa000063 +#define ixD3F4_PCIE_TLP_PREFIX_LOG2 0xa000064 +#define ixD3F4_PCIE_TLP_PREFIX_LOG3 0xa000065 +#define ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST 0xa00009c +#define ixD3F4_PCIE_LINK_CNTL3 0xa00009d +#define ixD3F4_PCIE_LANE_ERROR_STATUS 0xa00009e +#define ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL 0xa00009f +#define ixD3F4_PCIE_LANE_1_EQUALIZATION_CNTL 0xa00009f +#define ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL 0xa0000a0 +#define ixD3F4_PCIE_LANE_3_EQUALIZATION_CNTL 0xa0000a0 +#define ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL 0xa0000a1 +#define ixD3F4_PCIE_LANE_5_EQUALIZATION_CNTL 0xa0000a1 +#define ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL 0xa0000a2 +#define ixD3F4_PCIE_LANE_7_EQUALIZATION_CNTL 0xa0000a2 +#define ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL 0xa0000a3 +#define ixD3F4_PCIE_LANE_9_EQUALIZATION_CNTL 0xa0000a3 +#define ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL 0xa0000a4 +#define ixD3F4_PCIE_LANE_11_EQUALIZATION_CNTL 0xa0000a4 +#define ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL 0xa0000a5 +#define ixD3F4_PCIE_LANE_13_EQUALIZATION_CNTL 0xa0000a5 +#define ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL 0xa0000a6 +#define ixD3F4_PCIE_LANE_15_EQUALIZATION_CNTL 0xa0000a6 +#define ixD3F4_PCIE_ACS_ENH_CAP_LIST 0xa0000a8 +#define ixD3F4_PCIE_ACS_CAP 0xa0000a9 +#define ixD3F4_PCIE_ACS_CNTL 0xa0000a9 +#define ixD3F4_PCIE_MC_ENH_CAP_LIST 0xa0000bc +#define ixD3F4_PCIE_MC_CAP 0xa0000bd +#define ixD3F4_PCIE_MC_CNTL 0xa0000bd +#define ixD3F4_PCIE_MC_ADDR0 0xa0000be +#define ixD3F4_PCIE_MC_ADDR1 0xa0000bf +#define ixD3F4_PCIE_MC_RCV0 0xa0000c0 +#define ixD3F4_PCIE_MC_RCV1 0xa0000c1 +#define ixD3F4_PCIE_MC_BLOCK_ALL0 0xa0000c2 +#define ixD3F4_PCIE_MC_BLOCK_ALL1 0xa0000c3 +#define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0 0xa0000c4 +#define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1 0xa0000c5 +#define ixD3F4_PCIE_MC_OVERLAY_BAR0 0xa0000c6 +#define ixD3F4_PCIE_MC_OVERLAY_BAR1 0xa0000c7 +#define ixD3F5_PCIE_PORT_INDEX 0xb000038 +#define ixD3F5_PCIE_PORT_DATA 0xb000039 +#define ixD3F5_PCIEP_RESERVED 0x0 +#define ixD3F5_PCIEP_SCRATCH 0x1 +#define ixD3F5_PCIEP_HW_DEBUG 0x2 +#define ixD3F5_PCIEP_PORT_CNTL 0x10 +#define ixD3F5_PCIE_TX_CNTL 0x20 +#define ixD3F5_PCIE_TX_REQUESTER_ID 0x21 +#define ixD3F5_PCIE_TX_VENDOR_SPECIFIC 0x22 +#define ixD3F5_PCIE_TX_REQUEST_NUM_CNTL 0x23 +#define ixD3F5_PCIE_TX_SEQ 0x24 +#define ixD3F5_PCIE_TX_REPLAY 0x25 +#define ixD3F5_PCIE_TX_ACK_LATENCY_LIMIT 0x26 +#define ixD3F5_PCIE_TX_CREDITS_ADVT_P 0x30 +#define ixD3F5_PCIE_TX_CREDITS_ADVT_NP 0x31 +#define ixD3F5_PCIE_TX_CREDITS_ADVT_CPL 0x32 +#define ixD3F5_PCIE_TX_CREDITS_INIT_P 0x33 +#define ixD3F5_PCIE_TX_CREDITS_INIT_NP 0x34 +#define ixD3F5_PCIE_TX_CREDITS_INIT_CPL 0x35 +#define ixD3F5_PCIE_TX_CREDITS_STATUS 0x36 +#define ixD3F5_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 +#define ixD3F5_PCIE_P_PORT_LANE_STATUS 0x50 +#define ixD3F5_PCIE_FC_P 0x60 +#define ixD3F5_PCIE_FC_NP 0x61 +#define ixD3F5_PCIE_FC_CPL 0x62 +#define ixD3F5_PCIE_ERR_CNTL 0x6a +#define ixD3F5_PCIE_RX_CNTL 0x70 +#define ixD3F5_PCIE_RX_EXPECTED_SEQNUM 0x71 +#define ixD3F5_PCIE_RX_VENDOR_SPECIFIC 0x72 +#define ixD3F5_PCIE_RX_CNTL3 0x74 +#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_P 0x80 +#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 +#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 +#define ixD3F5_PCIEP_ERROR_INJECT_PHYSICAL 0x83 +#define ixD3F5_PCIEP_ERROR_INJECT_TRANSACTION 0x84 +#define ixD3F5_PCIE_LC_CNTL 0xa0 +#define ixD3F5_PCIE_LC_CNTL2 0xb1 +#define ixD3F5_PCIE_LC_CNTL3 0xb5 +#define ixD3F5_PCIE_LC_CNTL4 0xb6 +#define ixD3F5_PCIE_LC_CNTL5 0xb7 +#define ixD3F5_PCIE_LC_CNTL6 0xbb +#define ixD3F5_PCIE_LC_BW_CHANGE_CNTL 0xb2 +#define ixD3F5_PCIE_LC_TRAINING_CNTL 0xa1 +#define ixD3F5_PCIE_LC_LINK_WIDTH_CNTL 0xa2 +#define ixD3F5_PCIE_LC_N_FTS_CNTL 0xa3 +#define ixD3F5_PCIE_LC_SPEED_CNTL 0xa4 +#define ixD3F5_PCIE_LC_CDR_CNTL 0xb3 +#define ixD3F5_PCIE_LC_LANE_CNTL 0xb4 +#define ixD3F5_PCIE_LC_FORCE_COEFF 0xb8 +#define ixD3F5_PCIE_LC_BEST_EQ_SETTINGS 0xb9 +#define ixD3F5_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba +#define ixD3F5_PCIE_LC_STATE0 0xa5 +#define ixD3F5_PCIE_LC_STATE1 0xa6 +#define ixD3F5_PCIE_LC_STATE2 0xa7 +#define ixD3F5_PCIE_LC_STATE3 0xa8 +#define ixD3F5_PCIE_LC_STATE4 0xa9 +#define ixD3F5_PCIE_LC_STATE5 0xaa +#define ixD3F5_PCIEP_STRAP_LC 0xc0 +#define ixD3F5_PCIEP_STRAP_MISC 0xc1 +#define ixD3F5_PCIEP_BCH_ECC_CNTL 0xd0 +#define ixD3F5_PCIEP_HPGI_PRIVATE 0xd2 +#define ixD3F5_PCIEP_HPGI 0xda +#define ixD3F5_VENDOR_ID 0xb000000 +#define ixD3F5_DEVICE_ID 0xb000000 +#define ixD3F5_COMMAND 0xb000001 +#define ixD3F5_STATUS 0xb000001 +#define ixD3F5_REVISION_ID 0xb000002 +#define ixD3F5_PROG_INTERFACE 0xb000002 +#define ixD3F5_SUB_CLASS 0xb000002 +#define ixD3F5_BASE_CLASS 0xb000002 +#define ixD3F5_CACHE_LINE 0xb000003 +#define ixD3F5_LATENCY 0xb000003 +#define ixD3F5_HEADER 0xb000003 +#define ixD3F5_BIST 0xb000003 +#define ixD3F5_SUB_BUS_NUMBER_LATENCY 0xb000006 +#define ixD3F5_IO_BASE_LIMIT 0xb000007 +#define ixD3F5_SECONDARY_STATUS 0xb000007 +#define ixD3F5_MEM_BASE_LIMIT 0xb000008 +#define ixD3F5_PREF_BASE_LIMIT 0xb000009 +#define ixD3F5_PREF_BASE_UPPER 0xb00000a +#define ixD3F5_PREF_LIMIT_UPPER 0xb00000b +#define ixD3F5_IO_BASE_LIMIT_HI 0xb00000c +#define ixD3F5_IRQ_BRIDGE_CNTL 0xb00000f +#define ixD3F5_CAP_PTR 0xb00000d +#define ixD3F5_INTERRUPT_LINE 0xb00000f +#define ixD3F5_INTERRUPT_PIN 0xb00000f +#define ixD3F5_EXT_BRIDGE_CNTL 0xb000010 +#define ixD3F5_PMI_CAP_LIST 0xb000014 +#define ixD3F5_PMI_CAP 0xb000014 +#define ixD3F5_PMI_STATUS_CNTL 0xb000015 +#define ixD3F5_PCIE_CAP_LIST 0xb000016 +#define ixD3F5_PCIE_CAP 0xb000016 +#define ixD3F5_DEVICE_CAP 0xb000017 +#define ixD3F5_DEVICE_CNTL 0xb000018 +#define ixD3F5_DEVICE_STATUS 0xb000018 +#define ixD3F5_LINK_CAP 0xb000019 +#define ixD3F5_LINK_CNTL 0xb00001a +#define ixD3F5_LINK_STATUS 0xb00001a +#define ixD3F5_SLOT_CAP 0xb00001b +#define ixD3F5_SLOT_CNTL 0xb00001c +#define ixD3F5_SLOT_STATUS 0xb00001c +#define ixD3F5_ROOT_CNTL 0xb00001d +#define ixD3F5_ROOT_CAP 0xb00001d +#define ixD3F5_ROOT_STATUS 0xb00001e +#define ixD3F5_DEVICE_CAP2 0xb00001f +#define ixD3F5_DEVICE_CNTL2 0xb000020 +#define ixD3F5_DEVICE_STATUS2 0xb000020 +#define ixD3F5_LINK_CAP2 0xb000021 +#define ixD3F5_LINK_CNTL2 0xb000022 +#define ixD3F5_LINK_STATUS2 0xb000022 +#define ixD3F5_SLOT_CAP2 0xb000023 +#define ixD3F5_SLOT_CNTL2 0xb000024 +#define ixD3F5_SLOT_STATUS2 0xb000024 +#define ixD3F5_MSI_CAP_LIST 0xb000028 +#define ixD3F5_MSI_MSG_CNTL 0xb000028 +#define ixD3F5_MSI_MSG_ADDR_LO 0xb000029 +#define ixD3F5_MSI_MSG_ADDR_HI 0xb00002a +#define ixD3F5_MSI_MSG_DATA_64 0xb00002b +#define ixD3F5_MSI_MSG_DATA 0xb00002a +#define ixD3F5_SSID_CAP_LIST 0xb000030 +#define ixD3F5_SSID_CAP 0xb000031 +#define ixD3F5_MSI_MAP_CAP_LIST 0xb000032 +#define ixD3F5_MSI_MAP_CAP 0xb000032 +#define ixD3F5_MSI_MAP_ADDR_LO 0xb000033 +#define ixD3F5_MSI_MAP_ADDR_HI 0xb000034 +#define ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xb000040 +#define ixD3F5_PCIE_VENDOR_SPECIFIC_HDR 0xb000041 +#define ixD3F5_PCIE_VENDOR_SPECIFIC1 0xb000042 +#define ixD3F5_PCIE_VENDOR_SPECIFIC2 0xb000043 +#define ixD3F5_PCIE_VC_ENH_CAP_LIST 0xb000044 +#define ixD3F5_PCIE_PORT_VC_CAP_REG1 0xb000045 +#define ixD3F5_PCIE_PORT_VC_CAP_REG2 0xb000046 +#define ixD3F5_PCIE_PORT_VC_CNTL 0xb000047 +#define ixD3F5_PCIE_PORT_VC_STATUS 0xb000047 +#define ixD3F5_PCIE_VC0_RESOURCE_CAP 0xb000048 +#define ixD3F5_PCIE_VC0_RESOURCE_CNTL 0xb000049 +#define ixD3F5_PCIE_VC0_RESOURCE_STATUS 0xb00004a +#define ixD3F5_PCIE_VC1_RESOURCE_CAP 0xb00004b +#define ixD3F5_PCIE_VC1_RESOURCE_CNTL 0xb00004c +#define ixD3F5_PCIE_VC1_RESOURCE_STATUS 0xb00004d +#define ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xb000050 +#define ixD3F5_PCIE_DEV_SERIAL_NUM_DW1 0xb000051 +#define ixD3F5_PCIE_DEV_SERIAL_NUM_DW2 0xb000052 +#define ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xb000054 +#define ixD3F5_PCIE_UNCORR_ERR_STATUS 0xb000055 +#define ixD3F5_PCIE_UNCORR_ERR_MASK 0xb000056 +#define ixD3F5_PCIE_UNCORR_ERR_SEVERITY 0xb000057 +#define ixD3F5_PCIE_CORR_ERR_STATUS 0xb000058 +#define ixD3F5_PCIE_CORR_ERR_MASK 0xb000059 +#define ixD3F5_PCIE_ADV_ERR_CAP_CNTL 0xb00005a +#define ixD3F5_PCIE_HDR_LOG0 0xb00005b +#define ixD3F5_PCIE_HDR_LOG1 0xb00005c +#define ixD3F5_PCIE_HDR_LOG2 0xb00005d +#define ixD3F5_PCIE_HDR_LOG3 0xb00005e +#define ixD3F5_PCIE_ROOT_ERR_CMD 0xb00005f +#define ixD3F5_PCIE_ROOT_ERR_STATUS 0xb000060 +#define ixD3F5_PCIE_ERR_SRC_ID 0xb000061 +#define ixD3F5_PCIE_TLP_PREFIX_LOG0 0xb000062 +#define ixD3F5_PCIE_TLP_PREFIX_LOG1 0xb000063 +#define ixD3F5_PCIE_TLP_PREFIX_LOG2 0xb000064 +#define ixD3F5_PCIE_TLP_PREFIX_LOG3 0xb000065 +#define ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST 0xb00009c +#define ixD3F5_PCIE_LINK_CNTL3 0xb00009d +#define ixD3F5_PCIE_LANE_ERROR_STATUS 0xb00009e +#define ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL 0xb00009f +#define ixD3F5_PCIE_LANE_1_EQUALIZATION_CNTL 0xb00009f +#define ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL 0xb0000a0 +#define ixD3F5_PCIE_LANE_3_EQUALIZATION_CNTL 0xb0000a0 +#define ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL 0xb0000a1 +#define ixD3F5_PCIE_LANE_5_EQUALIZATION_CNTL 0xb0000a1 +#define ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL 0xb0000a2 +#define ixD3F5_PCIE_LANE_7_EQUALIZATION_CNTL 0xb0000a2 +#define ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL 0xb0000a3 +#define ixD3F5_PCIE_LANE_9_EQUALIZATION_CNTL 0xb0000a3 +#define ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL 0xb0000a4 +#define ixD3F5_PCIE_LANE_11_EQUALIZATION_CNTL 0xb0000a4 +#define ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL 0xb0000a5 +#define ixD3F5_PCIE_LANE_13_EQUALIZATION_CNTL 0xb0000a5 +#define ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL 0xb0000a6 +#define ixD3F5_PCIE_LANE_15_EQUALIZATION_CNTL 0xb0000a6 +#define ixD3F5_PCIE_ACS_ENH_CAP_LIST 0xb0000a8 +#define ixD3F5_PCIE_ACS_CAP 0xb0000a9 +#define ixD3F5_PCIE_ACS_CNTL 0xb0000a9 +#define ixD3F5_PCIE_MC_ENH_CAP_LIST 0xb0000bc +#define ixD3F5_PCIE_MC_CAP 0xb0000bd +#define ixD3F5_PCIE_MC_CNTL 0xb0000bd +#define ixD3F5_PCIE_MC_ADDR0 0xb0000be +#define ixD3F5_PCIE_MC_ADDR1 0xb0000bf +#define ixD3F5_PCIE_MC_RCV0 0xb0000c0 +#define ixD3F5_PCIE_MC_RCV1 0xb0000c1 +#define ixD3F5_PCIE_MC_BLOCK_ALL0 0xb0000c2 +#define ixD3F5_PCIE_MC_BLOCK_ALL1 0xb0000c3 +#define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0 0xb0000c4 +#define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1 0xb0000c5 +#define ixD3F5_PCIE_MC_OVERLAY_BAR0 0xb0000c6 +#define ixD3F5_PCIE_MC_OVERLAY_BAR1 0xb0000c7 +#define mmC_PCIE_INDEX 0x28 +#define mmPCIE_WRAPPER0_C_PCIE_INDEX 0x28 +#define mmPCIE_WRAPPER1_C_PCIE_INDEX 0x38 +#define mmC_PCIE_DATA 0x29 +#define mmPCIE_WRAPPER0_C_PCIE_DATA 0x29 +#define mmPCIE_WRAPPER1_C_PCIE_DATA 0x39 +#define mmRFE_SNOOP_RST 0x3c +#define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1 0x1500000 +#define ixPSX80_WRP_BIF_STRAP_PI_CNTL 0x1500001 +#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE 0x1500002 +#define ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE 0x1500003 +#define ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE 0x1500004 +#define ixPSX80_WRP_BIF_STRAP_TEST_DFT 0x1500005 +#define ixPSX80_WRP_BIF_STRAP_ID 0x1500006 +#define ixPSX80_WRP_BIF_STRAP_REV_ID 0x1500007 +#define ixPSX80_WRP_BIF_STRAP_I2C_CNTL 0x1500008 +#define ixPSX80_WRP_BIF_INT_CNTL 0x1500009 +#define ixPSX80_WRP_BIF_STRAP_ACS 0x150000a +#define ixPSX80_WRP_BIF_STRAP_PM 0x150000b +#define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2 0x150000c +#define ixPSX80_WRP_BIF_SERIAL_NUM 0x1500045 +#define ixPSX80_WRP_BIF_SSID 0x1500046 +#define ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL 0x1500050 +#define ixPSX80_WRP_PCIE_LINK_CONFIG 0x1500080 +#define ixPSX80_WRP_PCIE_HOLD_TRAINING_A 0x1500800 +#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A 0x1500801 +#define ixPSX80_WRP_BIF_STRAP_ASPM_A 0x1500802 +#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A 0x1500803 +#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_A 0x1500804 +#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A 0x1500805 +#define ixPSX80_WRP_PCIE_PORT_IS_SB_A 0x1500813 +#define ixPSX80_WRP_PCIE_HOLD_TRAINING_B 0x1500900 +#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B 0x1500901 +#define ixPSX80_WRP_BIF_STRAP_ASPM_B 0x1500902 +#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B 0x1500903 +#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_B 0x1500904 +#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B 0x1500905 +#define ixPSX80_WRP_PCIE_PORT_IS_SB_B 0x1500913 +#define ixPSX80_WRP_PCIE_HOLD_TRAINING_C 0x1500a00 +#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C 0x1500a01 +#define ixPSX80_WRP_BIF_STRAP_ASPM_C 0x1500a02 +#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C 0x1500a03 +#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_C 0x1500a04 +#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C 0x1500a05 +#define ixPSX80_WRP_PCIE_PORT_IS_SB_C 0x1500a13 +#define ixPSX80_WRP_PCIE_HOLD_TRAINING_D 0x1500b00 +#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D 0x1500b01 +#define ixPSX80_WRP_BIF_STRAP_ASPM_D 0x1500b02 +#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D 0x1500b03 +#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_D 0x1500b04 +#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D 0x1500b05 +#define ixPSX80_WRP_PCIE_PORT_IS_SB_D 0x1500b13 +#define ixPSX80_WRP_PCIE_HOLD_TRAINING_E 0x1500c00 +#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E 0x1500c01 +#define ixPSX80_WRP_BIF_STRAP_ASPM_E 0x1500c02 +#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E 0x1500c03 +#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_E 0x1500c04 +#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E 0x1500c05 +#define ixPSX80_WRP_PCIE_PORT_IS_SB_E 0x1500c13 +#define ixPSX80_WRP_LNCNT_CONTROL 0x1508030 +#define ixPSX80_WRP_CFG_LNC_WINDOW 0x1508031 +#define ixPSX80_WRP_LNCNT_QUAN_THRD 0x1508032 +#define ixPSX80_WRP_LNCNT_WEIGHT 0x1508033 +#define ixPSX80_WRP_LNC_TOTAL_WACC 0x1508034 +#define ixPSX80_WRP_LNC_BW_WACC 0x1508035 +#define ixPSX80_WRP_LNC_CMN_WACC 0x1508036 +#define ixPSX80_WRP_PCIE_EFUSE 0x150fff0 +#define ixPSX80_WRP_PCIE_EFUSE2 0x150fff1 +#define ixPSX80_WRP_PCIE_EFUSE3 0x150fff2 +#define ixPSX80_WRP_PCIE_EFUSE4 0x150fff3 +#define ixPSX80_WRP_PCIE_EFUSE5 0x150fff4 +#define ixPSX80_WRP_PCIE_EFUSE6 0x150fff5 +#define ixPSX80_WRP_PCIE_EFUSE7 0x150fff6 +#define ixPSX80_WRP_PCIE_WRAP_SCRATCH1 0x1308001 +#define ixPSX80_WRP_PCIE_WRAP_SCRATCH2 0x1308002 +#define ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC 0x1308005 +#define ixPSX80_WRP_PCIE_WRAP_DTM_MISC 0x1308006 +#define ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007 +#define ixPSX80_WRP_PCIE_WRAP_MISC 0x1308008 +#define ixPSX80_WRP_PCIE_WRAP_PIF_MISC 0x1308009 +#define ixPSX80_WRP_PCIE_RXDET_OVERRIDE 0x130800a +#define ixPSX80_WRP_IMPCTL_CNTL_PIF0 0x1308070 +#define ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL 0x1308090 +#define ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL 0x1308096 +#define ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL 0x1308097 +#define ixPSX80_WRP_REG_ADAPT_pif0_CONTROL 0x1308098 +#define ixPSX80_WRP_BIOSTIMER_CMD 0x13080f0 +#define ixPSX80_WRP_BIOSTIMER_CNTL 0x13080f1 +#define ixPSX80_WRP_BIOSTIMER_DEBUG 0x13080f2 +#define ixPSX80_WRP_DTM_RX_BP_CNTL 0x130ffe0 +#define ixPSX80_WRP_DTM_CNTL 0x130ffe1 +#define ixPSX80_WRP_DTM_CNTL_LEGACY 0x130ffe2 +#define ixPSX80_WRP_DTM_STI_LCLK_CTRL 0x130ffe3 +#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x 0x130ffe4 +#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt 0x130ffe5 +#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x 0x130ffe6 +#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt 0x130ffe7 +#define ixPSX80_WRP_DELAYLINE_COMMAND 0x130ffd0 +#define ixPSX80_WRP_DELAYLINE_STATUS 0x130ffd1 +#define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1 0x1510000 +#define ixPSX81_WRP_BIF_STRAP_PI_CNTL 0x1510001 +#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE 0x1510002 +#define ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE 0x1510003 +#define ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE 0x1510004 +#define ixPSX81_WRP_BIF_STRAP_TEST_DFT 0x1510005 +#define ixPSX81_WRP_BIF_STRAP_ID 0x1510006 +#define ixPSX81_WRP_BIF_STRAP_REV_ID 0x1510007 +#define ixPSX81_WRP_BIF_STRAP_I2C_CNTL 0x1510008 +#define ixPSX81_WRP_BIF_INT_CNTL 0x1510009 +#define ixPSX81_WRP_BIF_STRAP_ACS 0x151000a +#define ixPSX81_WRP_BIF_STRAP_PM 0x151000b +#define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2 0x151000c +#define ixPSX81_WRP_BIF_SERIAL_NUM 0x1510045 +#define ixPSX81_WRP_BIF_SSID 0x1510046 +#define ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL 0x1510050 +#define ixPSX81_WRP_PCIE_LINK_CONFIG 0x1510080 +#define ixPSX81_WRP_PCIE_HOLD_TRAINING_A 0x1510800 +#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A 0x1510801 +#define ixPSX81_WRP_BIF_STRAP_ASPM_A 0x1510802 +#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A 0x1510803 +#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_A 0x1510804 +#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A 0x1510805 +#define ixPSX81_WRP_PCIE_PORT_IS_SB_A 0x1510813 +#define ixPSX81_WRP_PCIE_HOLD_TRAINING_B 0x1510900 +#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B 0x1510901 +#define ixPSX81_WRP_BIF_STRAP_ASPM_B 0x1510902 +#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B 0x1510903 +#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_B 0x1510904 +#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B 0x1510905 +#define ixPSX81_WRP_PCIE_PORT_IS_SB_B 0x1510913 +#define ixPSX81_WRP_PCIE_HOLD_TRAINING_C 0x1510a00 +#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C 0x1510a01 +#define ixPSX81_WRP_BIF_STRAP_ASPM_C 0x1510a02 +#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C 0x1510a03 +#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_C 0x1510a04 +#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C 0x1510a05 +#define ixPSX81_WRP_PCIE_PORT_IS_SB_C 0x1510a13 +#define ixPSX81_WRP_PCIE_HOLD_TRAINING_D 0x1510b00 +#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D 0x1510b01 +#define ixPSX81_WRP_BIF_STRAP_ASPM_D 0x1510b02 +#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D 0x1510b03 +#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_D 0x1510b04 +#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D 0x1510b05 +#define ixPSX81_WRP_PCIE_PORT_IS_SB_D 0x1510b13 +#define ixPSX81_WRP_PCIE_HOLD_TRAINING_E 0x1510c00 +#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E 0x1510c01 +#define ixPSX81_WRP_BIF_STRAP_ASPM_E 0x1510c02 +#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E 0x1510c03 +#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_E 0x1510c04 +#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E 0x1510c05 +#define ixPSX81_WRP_PCIE_PORT_IS_SB_E 0x1510c13 +#define ixPSX81_WRP_LNCNT_CONTROL 0x1518030 +#define ixPSX81_WRP_CFG_LNC_WINDOW 0x1518031 +#define ixPSX81_WRP_LNCNT_QUAN_THRD 0x1518032 +#define ixPSX81_WRP_LNCNT_WEIGHT 0x1518033 +#define ixPSX81_WRP_LNC_TOTAL_WACC 0x1518034 +#define ixPSX81_WRP_LNC_BW_WACC 0x1518035 +#define ixPSX81_WRP_LNC_CMN_WACC 0x1518036 +#define ixPSX81_WRP_PCIE_EFUSE 0x151fff0 +#define ixPSX81_WRP_PCIE_EFUSE2 0x151fff1 +#define ixPSX81_WRP_PCIE_EFUSE3 0x151fff2 +#define ixPSX81_WRP_PCIE_EFUSE4 0x151fff3 +#define ixPSX81_WRP_PCIE_EFUSE5 0x151fff4 +#define ixPSX81_WRP_PCIE_EFUSE6 0x151fff5 +#define ixPSX81_WRP_PCIE_EFUSE7 0x151fff6 +#define ixPSX81_WRP_PCIE_WRAP_SCRATCH1 0x1318001 +#define ixPSX81_WRP_PCIE_WRAP_SCRATCH2 0x1318002 +#define ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC 0x1318005 +#define ixPSX81_WRP_PCIE_WRAP_DTM_MISC 0x1318006 +#define ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1318007 +#define ixPSX81_WRP_PCIE_WRAP_MISC 0x1318008 +#define ixPSX81_WRP_PCIE_WRAP_PIF_MISC 0x1318009 +#define ixPSX81_WRP_PCIE_RXDET_OVERRIDE 0x131800a +#define ixPSX81_WRP_IMPCTL_CNTL_PIF0 0x1318070 +#define ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL 0x1318090 +#define ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL 0x1318096 +#define ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL 0x1318097 +#define ixPSX81_WRP_REG_ADAPT_pif0_CONTROL 0x1318098 +#define ixPSX81_WRP_BIOSTIMER_CMD 0x13180f0 +#define ixPSX81_WRP_BIOSTIMER_CNTL 0x13180f1 +#define ixPSX81_WRP_BIOSTIMER_DEBUG 0x13180f2 +#define ixPSX81_WRP_DTM_RX_BP_CNTL 0x131ffe0 +#define ixPSX81_WRP_DTM_CNTL 0x131ffe1 +#define ixPSX81_WRP_DTM_CNTL_LEGACY 0x131ffe2 +#define ixPSX81_WRP_DTM_STI_LCLK_CTRL 0x131ffe3 +#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x 0x131ffe4 +#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt 0x131ffe5 +#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x 0x131ffe6 +#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt 0x131ffe7 +#define ixPSX81_WRP_DELAYLINE_COMMAND 0x131ffd0 +#define ixPSX81_WRP_DELAYLINE_STATUS 0x131ffd1 +#define ixRFE_WARMRST_CNTL 0x1085164 +#define ixRFE_SOFTRST_CNTL 0x1080001 +#define ixRFE_IMPRST_CNTL 0x1085160 +#define ixRFE_CLIENT_SOFTRST_TRIGGER 0x1080004 +#define ixRFE_MASTER_SOFTRST_TRIGGER 0x1080005 +#define ixRFE_PWDN_COMMAND 0x1080010 +#define ixRFE_PWDN_STATUS 0x1080011 +#define ixRFE_MST_PCIEW0_CMDSTATUS 0x1080020 +#define ixRFE_MST_PCIEW1_CMDSTATUS 0x1080021 +#define ixRFE_MST_RWREG_RFEWRC_CMDSTATUS 0x1080022 +#define ixRFE_MST_TMOUT_STATUS 0x108003f +#define ixRFE_IMPARBH_STATUS 0x1085140 +#define ixRFE_IMPARBH_CONTROL 0x1080083 +#define ixPSX80_BIF_PCIE_RESERVED 0x1400000 +#define ixPSX80_BIF_PCIE_SCRATCH 0x1400001 +#define ixPSX80_BIF_PCIE_HW_DEBUG 0x1400002 +#define ixPSX80_BIF_PCIE_RX_NUM_NAK 0x140000e +#define ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED 0x140000f +#define ixPSX80_BIF_PCIE_CNTL 0x1400010 +#define ixPSX80_BIF_PCIE_CONFIG_CNTL 0x1400011 +#define ixPSX80_BIF_PCIE_DEBUG_CNTL 0x1400012 +#define ixPSX80_BIF_PCIE_CNTL2 0x140001c +#define ixPSX80_BIF_PCIE_RX_CNTL2 0x140001d +#define ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL 0x140001e +#define ixPSX80_BIF_PCIE_CI_CNTL 0x1400020 +#define ixPSX80_BIF_PCIE_BUS_CNTL 0x1400021 +#define ixPSX80_BIF_PCIE_LC_STATE6 0x1400022 +#define ixPSX80_BIF_PCIE_LC_STATE7 0x1400023 +#define ixPSX80_BIF_PCIE_LC_STATE8 0x1400024 +#define ixPSX80_BIF_PCIE_LC_STATE9 0x1400025 +#define ixPSX80_BIF_PCIE_LC_STATE10 0x1400026 +#define ixPSX80_BIF_PCIE_LC_STATE11 0x1400027 +#define ixPSX80_BIF_PCIE_LC_STATUS1 0x1400028 +#define ixPSX80_BIF_PCIE_LC_STATUS2 0x1400029 +#define ixPSX80_BIF_PCIE_WPR_CNTL 0x1400030 +#define ixPSX80_BIF_PCIE_RX_LAST_TLP0 0x1400031 +#define ixPSX80_BIF_PCIE_RX_LAST_TLP1 0x1400032 +#define ixPSX80_BIF_PCIE_RX_LAST_TLP2 0x1400033 +#define ixPSX80_BIF_PCIE_RX_LAST_TLP3 0x1400034 +#define ixPSX80_BIF_PCIE_TX_LAST_TLP0 0x1400035 +#define ixPSX80_BIF_PCIE_TX_LAST_TLP1 0x1400036 +#define ixPSX80_BIF_PCIE_TX_LAST_TLP2 0x1400037 +#define ixPSX80_BIF_PCIE_TX_LAST_TLP3 0x1400038 +#define ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND 0x140003a +#define ixPSX80_BIF_PCIE_I2C_REG_DATA 0x140003b +#define ixPSX80_BIF_PCIE_CFG_CNTL 0x140003c +#define ixPSX80_BIF_PCIE_LC_PM_CNTL 0x140003d +#define ixPSX80_BIF_PCIE_P_CNTL 0x1400040 +#define ixPSX80_BIF_PCIE_P_BUF_STATUS 0x1400041 +#define ixPSX80_BIF_PCIE_P_DECODER_STATUS 0x1400042 +#define ixPSX80_BIF_PCIE_P_MISC_STATUS 0x1400043 +#define ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET 0x1400050 +#define ixPSX80_BIF_PCIE_PERF_COUNT_CNTL 0x1400080 +#define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK 0x1400081 +#define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK 0x1400082 +#define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK 0x1400083 +#define ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK 0x1400084 +#define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK 0x1400085 +#define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK 0x1400086 +#define ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK 0x1400087 +#define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK 0x1400088 +#define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK 0x1400089 +#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK 0x140008a +#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK 0x140008b +#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK 0x140008c +#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d +#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e +#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f +#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 +#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 +#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 +#define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 +#define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 +#define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2 0x1400095 +#define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2 0x1400096 +#define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2 0x1400097 +#define ixPSX80_BIF_PCIE_STRAP_F0 0x14000b0 +#define ixPSX80_BIF_PCIE_STRAP_MISC 0x14000c0 +#define ixPSX80_BIF_PCIE_STRAP_MISC2 0x14000c1 +#define ixPSX80_BIF_PCIE_STRAP_PI 0x14000c2 +#define ixPSX80_BIF_PCIE_STRAP_I2C_BD 0x14000c4 +#define ixPSX80_BIF_PCIE_PRBS_CLR 0x14000c8 +#define ixPSX80_BIF_PCIE_PRBS_STATUS1 0x14000c9 +#define ixPSX80_BIF_PCIE_PRBS_STATUS2 0x14000ca +#define ixPSX80_BIF_PCIE_PRBS_FREERUN 0x14000cb +#define ixPSX80_BIF_PCIE_PRBS_MISC 0x14000cc +#define ixPSX80_BIF_PCIE_PRBS_USER_PATTERN 0x14000cd +#define ixPSX80_BIF_PCIE_PRBS_LO_BITCNT 0x14000ce +#define ixPSX80_BIF_PCIE_PRBS_HI_BITCNT 0x14000cf +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_0 0x14000d0 +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_1 0x14000d1 +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_2 0x14000d2 +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_3 0x14000d3 +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_4 0x14000d4 +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_5 0x14000d5 +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_6 0x14000d6 +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_7 0x14000d7 +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_8 0x14000d8 +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_9 0x14000d9 +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_10 0x14000da +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_11 0x14000db +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_12 0x14000dc +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_13 0x14000dd +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_14 0x14000de +#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_15 0x14000df +#define ixPSX80_BIF_SWRST_COMMAND_STATUS 0x1400100 +#define ixPSX80_BIF_SWRST_GENERAL_CONTROL 0x1400101 +#define ixPSX80_BIF_SWRST_COMMAND_0 0x1400102 +#define ixPSX80_BIF_SWRST_COMMAND_1 0x1400103 +#define ixPSX80_BIF_SWRST_CONTROL_0 0x1400104 +#define ixPSX80_BIF_SWRST_CONTROL_1 0x1400105 +#define ixPSX80_BIF_SWRST_CONTROL_2 0x1400106 +#define ixPSX80_BIF_SWRST_CONTROL_3 0x1400107 +#define ixPSX80_BIF_SWRST_CONTROL_4 0x1400108 +#define ixPSX80_BIF_SWRST_CONTROL_5 0x1400109 +#define ixPSX80_BIF_SWRST_CONTROL_6 0x140010a +#define ixPSX80_BIF_CPM_CONTROL 0x1400118 +#define ixPSX80_BIF_LM_CONTROL 0x1400120 +#define ixPSX80_BIF_LM_PCIETXMUX0 0x1400121 +#define ixPSX80_BIF_LM_PCIETXMUX1 0x1400122 +#define ixPSX80_BIF_LM_PCIETXMUX2 0x1400123 +#define ixPSX80_BIF_LM_PCIETXMUX3 0x1400124 +#define ixPSX80_BIF_LM_PCIERXMUX0 0x1400125 +#define ixPSX80_BIF_LM_PCIERXMUX1 0x1400126 +#define ixPSX80_BIF_LM_PCIERXMUX2 0x1400127 +#define ixPSX80_BIF_LM_PCIERXMUX3 0x1400128 +#define ixPSX80_BIF_LM_LANEENABLE 0x1400129 +#define ixPSX80_BIF_LM_PRBSCONTROL 0x140012a +#define ixPSX80_BIF_LM_POWERCONTROL 0x140012b +#define ixPSX80_BIF_LM_POWERCONTROL1 0x140012c +#define ixPSX80_BIF_LM_POWERCONTROL2 0x140012d +#define ixPSX80_BIF_LM_POWERCONTROL3 0x140012e +#define ixPSX80_BIF_LM_POWERCONTROL4 0x140012f +#define ixPSX81_BIF_PCIE_RESERVED 0x1410000 +#define ixPSX81_BIF_PCIE_SCRATCH 0x1410001 +#define ixPSX81_BIF_PCIE_HW_DEBUG 0x1410002 +#define ixPSX81_BIF_PCIE_RX_NUM_NAK 0x141000e +#define ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED 0x141000f +#define ixPSX81_BIF_PCIE_CNTL 0x1410010 +#define ixPSX81_BIF_PCIE_CONFIG_CNTL 0x1410011 +#define ixPSX81_BIF_PCIE_DEBUG_CNTL 0x1410012 +#define ixPSX81_BIF_PCIE_CNTL2 0x141001c +#define ixPSX81_BIF_PCIE_RX_CNTL2 0x141001d +#define ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL 0x141001e +#define ixPSX81_BIF_PCIE_CI_CNTL 0x1410020 +#define ixPSX81_BIF_PCIE_BUS_CNTL 0x1410021 +#define ixPSX81_BIF_PCIE_LC_STATE6 0x1410022 +#define ixPSX81_BIF_PCIE_LC_STATE7 0x1410023 +#define ixPSX81_BIF_PCIE_LC_STATE8 0x1410024 +#define ixPSX81_BIF_PCIE_LC_STATE9 0x1410025 +#define ixPSX81_BIF_PCIE_LC_STATE10 0x1410026 +#define ixPSX81_BIF_PCIE_LC_STATE11 0x1410027 +#define ixPSX81_BIF_PCIE_LC_STATUS1 0x1410028 +#define ixPSX81_BIF_PCIE_LC_STATUS2 0x1410029 +#define ixPSX81_BIF_PCIE_WPR_CNTL 0x1410030 +#define ixPSX81_BIF_PCIE_RX_LAST_TLP0 0x1410031 +#define ixPSX81_BIF_PCIE_RX_LAST_TLP1 0x1410032 +#define ixPSX81_BIF_PCIE_RX_LAST_TLP2 0x1410033 +#define ixPSX81_BIF_PCIE_RX_LAST_TLP3 0x1410034 +#define ixPSX81_BIF_PCIE_TX_LAST_TLP0 0x1410035 +#define ixPSX81_BIF_PCIE_TX_LAST_TLP1 0x1410036 +#define ixPSX81_BIF_PCIE_TX_LAST_TLP2 0x1410037 +#define ixPSX81_BIF_PCIE_TX_LAST_TLP3 0x1410038 +#define ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND 0x141003a +#define ixPSX81_BIF_PCIE_I2C_REG_DATA 0x141003b +#define ixPSX81_BIF_PCIE_CFG_CNTL 0x141003c +#define ixPSX81_BIF_PCIE_LC_PM_CNTL 0x141003d +#define ixPSX81_BIF_PCIE_P_CNTL 0x1410040 +#define ixPSX81_BIF_PCIE_P_BUF_STATUS 0x1410041 +#define ixPSX81_BIF_PCIE_P_DECODER_STATUS 0x1410042 +#define ixPSX81_BIF_PCIE_P_MISC_STATUS 0x1410043 +#define ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET 0x1410050 +#define ixPSX81_BIF_PCIE_PERF_COUNT_CNTL 0x1410080 +#define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK 0x1410081 +#define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK 0x1410082 +#define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK 0x1410083 +#define ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK 0x1410084 +#define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK 0x1410085 +#define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK 0x1410086 +#define ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK 0x1410087 +#define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK 0x1410088 +#define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK 0x1410089 +#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK 0x141008a +#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK 0x141008b +#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK 0x141008c +#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK 0x141008d +#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK 0x141008e +#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK 0x141008f +#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK 0x1410090 +#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1410091 +#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1410092 +#define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1410093 +#define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1410094 +#define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2 0x1410095 +#define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2 0x1410096 +#define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2 0x1410097 +#define ixPSX81_BIF_PCIE_STRAP_F0 0x14100b0 +#define ixPSX81_BIF_PCIE_STRAP_MISC 0x14100c0 +#define ixPSX81_BIF_PCIE_STRAP_MISC2 0x14100c1 +#define ixPSX81_BIF_PCIE_STRAP_PI 0x14100c2 +#define ixPSX81_BIF_PCIE_STRAP_I2C_BD 0x14100c4 +#define ixPSX81_BIF_PCIE_PRBS_CLR 0x14100c8 +#define ixPSX81_BIF_PCIE_PRBS_STATUS1 0x14100c9 +#define ixPSX81_BIF_PCIE_PRBS_STATUS2 0x14100ca +#define ixPSX81_BIF_PCIE_PRBS_FREERUN 0x14100cb +#define ixPSX81_BIF_PCIE_PRBS_MISC 0x14100cc +#define ixPSX81_BIF_PCIE_PRBS_USER_PATTERN 0x14100cd +#define ixPSX81_BIF_PCIE_PRBS_LO_BITCNT 0x14100ce +#define ixPSX81_BIF_PCIE_PRBS_HI_BITCNT 0x14100cf +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_0 0x14100d0 +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_1 0x14100d1 +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_2 0x14100d2 +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_3 0x14100d3 +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_4 0x14100d4 +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_5 0x14100d5 +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_6 0x14100d6 +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_7 0x14100d7 +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_8 0x14100d8 +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_9 0x14100d9 +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_10 0x14100da +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_11 0x14100db +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_12 0x14100dc +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_13 0x14100dd +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_14 0x14100de +#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_15 0x14100df +#define ixPSX81_BIF_SWRST_COMMAND_STATUS 0x1410100 +#define ixPSX81_BIF_SWRST_GENERAL_CONTROL 0x1410101 +#define ixPSX81_BIF_SWRST_COMMAND_0 0x1410102 +#define ixPSX81_BIF_SWRST_COMMAND_1 0x1410103 +#define ixPSX81_BIF_SWRST_CONTROL_0 0x1410104 +#define ixPSX81_BIF_SWRST_CONTROL_1 0x1410105 +#define ixPSX81_BIF_SWRST_CONTROL_2 0x1410106 +#define ixPSX81_BIF_SWRST_CONTROL_3 0x1410107 +#define ixPSX81_BIF_SWRST_CONTROL_4 0x1410108 +#define ixPSX81_BIF_SWRST_CONTROL_5 0x1410109 +#define ixPSX81_BIF_SWRST_CONTROL_6 0x141010a +#define ixPSX81_BIF_CPM_CONTROL 0x1410118 +#define ixPSX81_BIF_LM_CONTROL 0x1410120 +#define ixPSX81_BIF_LM_PCIETXMUX0 0x1410121 +#define ixPSX81_BIF_LM_PCIETXMUX1 0x1410122 +#define ixPSX81_BIF_LM_PCIETXMUX2 0x1410123 +#define ixPSX81_BIF_LM_PCIETXMUX3 0x1410124 +#define ixPSX81_BIF_LM_PCIERXMUX0 0x1410125 +#define ixPSX81_BIF_LM_PCIERXMUX1 0x1410126 +#define ixPSX81_BIF_LM_PCIERXMUX2 0x1410127 +#define ixPSX81_BIF_LM_PCIERXMUX3 0x1410128 +#define ixPSX81_BIF_LM_LANEENABLE 0x1410129 +#define ixPSX81_BIF_LM_PRBSCONTROL 0x141012a +#define ixPSX81_BIF_LM_POWERCONTROL 0x141012b +#define ixPSX81_BIF_LM_POWERCONTROL1 0x141012c +#define ixPSX81_BIF_LM_POWERCONTROL2 0x141012d +#define ixPSX81_BIF_LM_POWERCONTROL3 0x141012e +#define ixPSX81_BIF_LM_POWERCONTROL4 0x141012f +#define ixPSX80_PHY0_COM_COMMON_FUSE1 0x1206200 +#define ixPSX80_PHY0_COM_COMMON_FUSE2 0x1206201 +#define ixPSX80_PHY0_COM_COMMON_FUSE3 0x1206202 +#define ixPSX80_PHY0_COM_COMMON_ELECIDLE 0x1206204 +#define ixPSX80_PHY0_COM_COMMON_DFX 0x1206205 +#define ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM 0x1206206 +#define ixPSX80_PHY0_COM_COMMON_SELDEEMPH35 0x1206207 +#define ixPSX80_PHY0_COM_COMMON_SELDEEMPH60 0x1206208 +#define ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT 0x1206209 +#define ixPSX80_PHY0_COM_COMMON_ADAPTCTL1 0x120620a +#define ixPSX80_PHY0_COM_COMMON_ADAPTCTL2 0x120620b +#define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL 0x120620c +#define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1 0x120620d +#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL 0x120620e +#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1 0x120620f +#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1 0x1206210 +#define ixPSX80_PHY0_COM_COMMON_LNCNTRL 0x1206211 +#define ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG 0x1206212 +#define ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG 0x1206213 +#define ixPSX80_PHY0_COM_COMMON_CDR_PHCTL 0x1206214 +#define ixPSX80_PHY0_COM_COMMON_CDR_FRCTL 0x1206215 +#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST 0x120fe00 +#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0 0x1200000 +#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1 0x1200100 +#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2 0x1200200 +#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3 0x1200300 +#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4 0x1200400 +#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5 0x1200500 +#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6 0x1200600 +#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7 0x1200700 +#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST 0x120fe01 +#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0 0x1200001 +#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1 0x1200101 +#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2 0x1200201 +#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3 0x1200301 +#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4 0x1200401 +#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5 0x1200501 +#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6 0x1200601 +#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7 0x1200701 +#define ixPSX80_PHY0_RX_RX_CTL_BROADCAST 0x120fe02 +#define ixPSX80_PHY0_RX_RX_CTL_LANE0 0x1200002 +#define ixPSX80_PHY0_RX_RX_CTL_LANE1 0x1200102 +#define ixPSX80_PHY0_RX_RX_CTL_LANE2 0x1200202 +#define ixPSX80_PHY0_RX_RX_CTL_LANE3 0x1200302 +#define ixPSX80_PHY0_RX_RX_CTL_LANE4 0x1200402 +#define ixPSX80_PHY0_RX_RX_CTL_LANE5 0x1200502 +#define ixPSX80_PHY0_RX_RX_CTL_LANE6 0x1200602 +#define ixPSX80_PHY0_RX_RX_CTL_LANE7 0x1200702 +#define ixPSX80_PHY0_RX_DLL_CTL_BROADCAST 0x120fe03 +#define ixPSX80_PHY0_RX_DLL_CTL_LANE0 0x1200003 +#define ixPSX80_PHY0_RX_DLL_CTL_LANE1 0x1200103 +#define ixPSX80_PHY0_RX_DLL_CTL_LANE2 0x1200203 +#define ixPSX80_PHY0_RX_DLL_CTL_LANE3 0x1200303 +#define ixPSX80_PHY0_RX_DLL_CTL_LANE4 0x1200403 +#define ixPSX80_PHY0_RX_DLL_CTL_LANE5 0x1200503 +#define ixPSX80_PHY0_RX_DLL_CTL_LANE6 0x1200603 +#define ixPSX80_PHY0_RX_DLL_CTL_LANE7 0x1200703 +#define ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST 0x120fe04 +#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE0 0x1200004 +#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE1 0x1200104 +#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE2 0x1200204 +#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE3 0x1200304 +#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE4 0x1200404 +#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE5 0x1200504 +#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE6 0x1200604 +#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE7 0x1200704 +#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST 0x120fe05 +#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0 0x1200005 +#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1 0x1200105 +#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2 0x1200205 +#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3 0x1200305 +#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4 0x1200405 +#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5 0x1200505 +#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6 0x1200605 +#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7 0x1200705 +#define ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST 0x120fe0a +#define ixPSX80_PHY0_RX_ADAPTCTL_LANE0 0x120000a +#define ixPSX80_PHY0_RX_ADAPTCTL_LANE1 0x120010a +#define ixPSX80_PHY0_RX_ADAPTCTL_LANE2 0x120020a +#define ixPSX80_PHY0_RX_ADAPTCTL_LANE3 0x120030a +#define ixPSX80_PHY0_RX_ADAPTCTL_LANE4 0x120040a +#define ixPSX80_PHY0_RX_ADAPTCTL_LANE5 0x120050a +#define ixPSX80_PHY0_RX_ADAPTCTL_LANE6 0x120060a +#define ixPSX80_PHY0_RX_ADAPTCTL_LANE7 0x120070a +#define ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST 0x120fe0b +#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE0 0x120000b +#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE1 0x120010b +#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE2 0x120020b +#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE3 0x120030b +#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE4 0x120040b +#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE5 0x120050b +#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE6 0x120060b +#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE7 0x120070b +#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST 0x120fe0c +#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0 0x120000c +#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1 0x120010c +#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2 0x120020c +#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3 0x120030c +#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4 0x120040c +#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5 0x120050c +#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6 0x120060c +#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7 0x120070c +#define ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST 0x120fe0d +#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0 0x120000d +#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1 0x120010d +#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2 0x120020d +#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3 0x120030d +#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4 0x120040d +#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5 0x120050d +#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6 0x120060d +#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7 0x120070d +#define ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST 0x120fe0e +#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE0 0x120000e +#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE1 0x120010e +#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE2 0x120020e +#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE3 0x120030e +#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE4 0x120040e +#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE5 0x120050e +#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE6 0x120060e +#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE7 0x120070e +#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST 0x120ff00 +#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0 0x1202000 +#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1 0x1202100 +#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2 0x1202200 +#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3 0x1202300 +#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4 0x1202400 +#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5 0x1202500 +#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6 0x1202600 +#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7 0x1202700 +#define ixPSX80_PHY0_TX_DFX_BROADCAST 0x120ff01 +#define ixPSX80_PHY0_TX_DFX_LANE0 0x1202001 +#define ixPSX80_PHY0_TX_DFX_LANE1 0x1202101 +#define ixPSX80_PHY0_TX_DFX_LANE2 0x1202201 +#define ixPSX80_PHY0_TX_DFX_LANE3 0x1202301 +#define ixPSX80_PHY0_TX_DFX_LANE4 0x1202401 +#define ixPSX80_PHY0_TX_DFX_LANE5 0x1202501 +#define ixPSX80_PHY0_TX_DFX_LANE6 0x1202601 +#define ixPSX80_PHY0_TX_DFX_LANE7 0x1202701 +#define ixPSX80_PHY0_TX_DEEMPH_BROADCAST 0x120ff02 +#define ixPSX80_PHY0_TX_DEEMPH_LANE0 0x1202002 +#define ixPSX80_PHY0_TX_DEEMPH_LANE1 0x1202102 +#define ixPSX80_PHY0_TX_DEEMPH_LANE2 0x1202202 +#define ixPSX80_PHY0_TX_DEEMPH_LANE3 0x1202302 +#define ixPSX80_PHY0_TX_DEEMPH_LANE4 0x1202402 +#define ixPSX80_PHY0_TX_DEEMPH_LANE5 0x1202502 +#define ixPSX80_PHY0_TX_DEEMPH_LANE6 0x1202602 +#define ixPSX80_PHY0_TX_DEEMPH_LANE7 0x1202702 +#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST 0x120ff03 +#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0 0x1202003 +#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1 0x1202103 +#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2 0x1202203 +#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3 0x1202303 +#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4 0x1202403 +#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5 0x1202503 +#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6 0x1202603 +#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7 0x1202703 +#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST 0x120ff04 +#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0 0x1202004 +#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1 0x1202104 +#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2 0x1202204 +#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3 0x1202304 +#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4 0x1202404 +#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5 0x1202504 +#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6 0x1202604 +#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7 0x1202704 +#define ixPSX80_PHY0_TX_TXCNTRL_BROADCAST 0x120ff06 +#define ixPSX80_PHY0_TX_TXCNTRL_LANE0 0x1202006 +#define ixPSX80_PHY0_TX_TXCNTRL_LANE1 0x1202106 +#define ixPSX80_PHY0_TX_TXCNTRL_LANE2 0x1202206 +#define ixPSX80_PHY0_TX_TXCNTRL_LANE3 0x1202306 +#define ixPSX80_PHY0_TX_TXCNTRL_LANE4 0x1202406 +#define ixPSX80_PHY0_TX_TXCNTRL_LANE5 0x1202506 +#define ixPSX80_PHY0_TX_TXCNTRL_LANE6 0x1202606 +#define ixPSX80_PHY0_TX_TXCNTRL_LANE7 0x1202706 +#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST 0x120ff07 +#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x1202007 +#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x1202107 +#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x1202207 +#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x1202307 +#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4 0x1202407 +#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5 0x1202507 +#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6 0x1202607 +#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7 0x1202707 +#define ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn 0x1204180 +#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt 0x1204101 +#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl 0x1204102 +#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1 0x1204103 +#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2 0x1204104 +#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode 0x1204105 +#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl 0x1204108 +#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3 0x1204109 +#define ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess 0x120410a +#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4 0x120410b +#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5 0x120410c +#define ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn 0x1204080 +#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt 0x1204001 +#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl 0x1204002 +#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1 0x1204003 +#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2 0x1204004 +#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode 0x1204005 +#define ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl 0x1204007 +#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl 0x1204008 +#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3 0x1204009 +#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4 0x120400b +#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5 0x120400c +#define ixPSX81_PHY0_COM_COMMON_FUSE1 0x1216200 +#define ixPSX81_PHY0_COM_COMMON_FUSE2 0x1216201 +#define ixPSX81_PHY0_COM_COMMON_FUSE3 0x1216202 +#define ixPSX81_PHY0_COM_COMMON_ELECIDLE 0x1216204 +#define ixPSX81_PHY0_COM_COMMON_DFX 0x1216205 +#define ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM 0x1216206 +#define ixPSX81_PHY0_COM_COMMON_SELDEEMPH35 0x1216207 +#define ixPSX81_PHY0_COM_COMMON_SELDEEMPH60 0x1216208 +#define ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT 0x1216209 +#define ixPSX81_PHY0_COM_COMMON_ADAPTCTL1 0x121620a +#define ixPSX81_PHY0_COM_COMMON_ADAPTCTL2 0x121620b +#define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL 0x121620c +#define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1 0x121620d +#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL 0x121620e +#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1 0x121620f +#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1 0x1216210 +#define ixPSX81_PHY0_COM_COMMON_LNCNTRL 0x1216211 +#define ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG 0x1216212 +#define ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG 0x1216213 +#define ixPSX81_PHY0_COM_COMMON_CDR_PHCTL 0x1216214 +#define ixPSX81_PHY0_COM_COMMON_CDR_FRCTL 0x1216215 +#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST 0x121fe00 +#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0 0x1210000 +#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1 0x1210100 +#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2 0x1210200 +#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3 0x1210300 +#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4 0x1210400 +#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5 0x1210500 +#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6 0x1210600 +#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7 0x1210700 +#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST 0x121fe01 +#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0 0x1210001 +#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1 0x1210101 +#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2 0x1210201 +#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3 0x1210301 +#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4 0x1210401 +#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5 0x1210501 +#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6 0x1210601 +#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7 0x1210701 +#define ixPSX81_PHY0_RX_RX_CTL_BROADCAST 0x121fe02 +#define ixPSX81_PHY0_RX_RX_CTL_LANE0 0x1210002 +#define ixPSX81_PHY0_RX_RX_CTL_LANE1 0x1210102 +#define ixPSX81_PHY0_RX_RX_CTL_LANE2 0x1210202 +#define ixPSX81_PHY0_RX_RX_CTL_LANE3 0x1210302 +#define ixPSX81_PHY0_RX_RX_CTL_LANE4 0x1210402 +#define ixPSX81_PHY0_RX_RX_CTL_LANE5 0x1210502 +#define ixPSX81_PHY0_RX_RX_CTL_LANE6 0x1210602 +#define ixPSX81_PHY0_RX_RX_CTL_LANE7 0x1210702 +#define ixPSX81_PHY0_RX_DLL_CTL_BROADCAST 0x121fe03 +#define ixPSX81_PHY0_RX_DLL_CTL_LANE0 0x1210003 +#define ixPSX81_PHY0_RX_DLL_CTL_LANE1 0x1210103 +#define ixPSX81_PHY0_RX_DLL_CTL_LANE2 0x1210203 +#define ixPSX81_PHY0_RX_DLL_CTL_LANE3 0x1210303 +#define ixPSX81_PHY0_RX_DLL_CTL_LANE4 0x1210403 +#define ixPSX81_PHY0_RX_DLL_CTL_LANE5 0x1210503 +#define ixPSX81_PHY0_RX_DLL_CTL_LANE6 0x1210603 +#define ixPSX81_PHY0_RX_DLL_CTL_LANE7 0x1210703 +#define ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST 0x121fe04 +#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE0 0x1210004 +#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE1 0x1210104 +#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE2 0x1210204 +#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE3 0x1210304 +#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE4 0x1210404 +#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE5 0x1210504 +#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE6 0x1210604 +#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE7 0x1210704 +#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST 0x121fe05 +#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0 0x1210005 +#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1 0x1210105 +#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2 0x1210205 +#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3 0x1210305 +#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4 0x1210405 +#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5 0x1210505 +#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6 0x1210605 +#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7 0x1210705 +#define ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST 0x121fe0a +#define ixPSX81_PHY0_RX_ADAPTCTL_LANE0 0x121000a +#define ixPSX81_PHY0_RX_ADAPTCTL_LANE1 0x121010a +#define ixPSX81_PHY0_RX_ADAPTCTL_LANE2 0x121020a +#define ixPSX81_PHY0_RX_ADAPTCTL_LANE3 0x121030a +#define ixPSX81_PHY0_RX_ADAPTCTL_LANE4 0x121040a +#define ixPSX81_PHY0_RX_ADAPTCTL_LANE5 0x121050a +#define ixPSX81_PHY0_RX_ADAPTCTL_LANE6 0x121060a +#define ixPSX81_PHY0_RX_ADAPTCTL_LANE7 0x121070a +#define ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST 0x121fe0b +#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE0 0x121000b +#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE1 0x121010b +#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE2 0x121020b +#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE3 0x121030b +#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE4 0x121040b +#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE5 0x121050b +#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE6 0x121060b +#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE7 0x121070b +#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST 0x121fe0c +#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0 0x121000c +#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1 0x121010c +#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2 0x121020c +#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3 0x121030c +#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4 0x121040c +#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5 0x121050c +#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6 0x121060c +#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7 0x121070c +#define ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST 0x121fe0d +#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0 0x121000d +#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1 0x121010d +#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2 0x121020d +#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3 0x121030d +#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4 0x121040d +#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5 0x121050d +#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6 0x121060d +#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7 0x121070d +#define ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST 0x121fe0e +#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE0 0x121000e +#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE1 0x121010e +#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE2 0x121020e +#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE3 0x121030e +#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE4 0x121040e +#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE5 0x121050e +#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE6 0x121060e +#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE7 0x121070e +#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST 0x121ff00 +#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0 0x1212000 +#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1 0x1212100 +#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2 0x1212200 +#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3 0x1212300 +#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4 0x1212400 +#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5 0x1212500 +#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6 0x1212600 +#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7 0x1212700 +#define ixPSX81_PHY0_TX_DFX_BROADCAST 0x121ff01 +#define ixPSX81_PHY0_TX_DFX_LANE0 0x1212001 +#define ixPSX81_PHY0_TX_DFX_LANE1 0x1212101 +#define ixPSX81_PHY0_TX_DFX_LANE2 0x1212201 +#define ixPSX81_PHY0_TX_DFX_LANE3 0x1212301 +#define ixPSX81_PHY0_TX_DFX_LANE4 0x1212401 +#define ixPSX81_PHY0_TX_DFX_LANE5 0x1212501 +#define ixPSX81_PHY0_TX_DFX_LANE6 0x1212601 +#define ixPSX81_PHY0_TX_DFX_LANE7 0x1212701 +#define ixPSX81_PHY0_TX_DEEMPH_BROADCAST 0x121ff02 +#define ixPSX81_PHY0_TX_DEEMPH_LANE0 0x1212002 +#define ixPSX81_PHY0_TX_DEEMPH_LANE1 0x1212102 +#define ixPSX81_PHY0_TX_DEEMPH_LANE2 0x1212202 +#define ixPSX81_PHY0_TX_DEEMPH_LANE3 0x1212302 +#define ixPSX81_PHY0_TX_DEEMPH_LANE4 0x1212402 +#define ixPSX81_PHY0_TX_DEEMPH_LANE5 0x1212502 +#define ixPSX81_PHY0_TX_DEEMPH_LANE6 0x1212602 +#define ixPSX81_PHY0_TX_DEEMPH_LANE7 0x1212702 +#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST 0x121ff03 +#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0 0x1212003 +#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1 0x1212103 +#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2 0x1212203 +#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3 0x1212303 +#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4 0x1212403 +#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5 0x1212503 +#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6 0x1212603 +#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7 0x1212703 +#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST 0x121ff04 +#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0 0x1212004 +#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1 0x1212104 +#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2 0x1212204 +#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3 0x1212304 +#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4 0x1212404 +#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5 0x1212504 +#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6 0x1212604 +#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7 0x1212704 +#define ixPSX81_PHY0_TX_TXCNTRL_BROADCAST 0x121ff06 +#define ixPSX81_PHY0_TX_TXCNTRL_LANE0 0x1212006 +#define ixPSX81_PHY0_TX_TXCNTRL_LANE1 0x1212106 +#define ixPSX81_PHY0_TX_TXCNTRL_LANE2 0x1212206 +#define ixPSX81_PHY0_TX_TXCNTRL_LANE3 0x1212306 +#define ixPSX81_PHY0_TX_TXCNTRL_LANE4 0x1212406 +#define ixPSX81_PHY0_TX_TXCNTRL_LANE5 0x1212506 +#define ixPSX81_PHY0_TX_TXCNTRL_LANE6 0x1212606 +#define ixPSX81_PHY0_TX_TXCNTRL_LANE7 0x1212706 +#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST 0x121ff07 +#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x1212007 +#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x1212107 +#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x1212207 +#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x1212307 +#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4 0x1212407 +#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5 0x1212507 +#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6 0x1212607 +#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7 0x1212707 +#define ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn 0x1214180 +#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt 0x1214101 +#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl 0x1214102 +#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1 0x1214103 +#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2 0x1214104 +#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode 0x1214105 +#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl 0x1214108 +#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3 0x1214109 +#define ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess 0x121410a +#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4 0x121410b +#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5 0x121410c +#define ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn 0x1214080 +#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt 0x1214001 +#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl 0x1214002 +#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1 0x1214003 +#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2 0x1214004 +#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode 0x1214005 +#define ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl 0x1214007 +#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl 0x1214008 +#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3 0x1214009 +#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4 0x121400b +#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5 0x121400c +#define ixPSX80_PIF0_SCRATCH 0x1100001 +#define ixPSX80_PIF0_HW_DEBUG 0x1100002 +#define ixPSX80_PIF0_STRAP_0 0x1100003 +#define ixPSX80_PIF0_CTRL 0x1100004 +#define ixPSX80_PIF0_TX_CTRL 0x1100008 +#define ixPSX80_PIF0_TX_CTRL2 0x1100009 +#define ixPSX80_PIF0_RX_CTRL 0x110000a +#define ixPSX80_PIF0_RX_CTRL2 0x110000b +#define ixPSX80_PIF0_GLB_OVRD 0x110000c +#define ixPSX80_PIF0_GLB_OVRD2 0x110000d +#define ixPSX80_PIF0_BIF_CMD_STATUS 0x1100010 +#define ixPSX80_PIF0_CMD_BUS_CTRL 0x1100011 +#define ixPSX80_PIF0_CMD_BUS_GLB_OVRD 0x1100013 +#define ixPSX80_PIF0_LANE0_OVRD 0x1100014 +#define ixPSX80_PIF0_LANE0_OVRD2 0x1100015 +#define ixPSX80_PIF0_LANE1_OVRD 0x1100016 +#define ixPSX80_PIF0_LANE1_OVRD2 0x1100017 +#define ixPSX80_PIF0_LANE2_OVRD 0x1100018 +#define ixPSX80_PIF0_LANE2_OVRD2 0x1100019 +#define ixPSX80_PIF0_LANE3_OVRD 0x110001a +#define ixPSX80_PIF0_LANE3_OVRD2 0x110001b +#define ixPSX80_PIF0_LANE4_OVRD 0x110001c +#define ixPSX80_PIF0_LANE4_OVRD2 0x110001d +#define ixPSX80_PIF0_LANE5_OVRD 0x110001e +#define ixPSX80_PIF0_LANE5_OVRD2 0x110001f +#define ixPSX80_PIF0_LANE6_OVRD 0x1100020 +#define ixPSX80_PIF0_LANE6_OVRD2 0x1100021 +#define ixPSX80_PIF0_LANE7_OVRD 0x1100022 +#define ixPSX80_PIF0_LANE7_OVRD2 0x1100023 +#define ixPSX81_PIF0_SCRATCH 0x1110001 +#define ixPSX81_PIF0_HW_DEBUG 0x1110002 +#define ixPSX81_PIF0_STRAP_0 0x1110003 +#define ixPSX81_PIF0_CTRL 0x1110004 +#define ixPSX81_PIF0_TX_CTRL 0x1110008 +#define ixPSX81_PIF0_TX_CTRL2 0x1110009 +#define ixPSX81_PIF0_RX_CTRL 0x111000a +#define ixPSX81_PIF0_RX_CTRL2 0x111000b +#define ixPSX81_PIF0_GLB_OVRD 0x111000c +#define ixPSX81_PIF0_GLB_OVRD2 0x111000d +#define ixPSX81_PIF0_BIF_CMD_STATUS 0x1110010 +#define ixPSX81_PIF0_CMD_BUS_CTRL 0x1110011 +#define ixPSX81_PIF0_CMD_BUS_GLB_OVRD 0x1110013 +#define ixPSX81_PIF0_LANE0_OVRD 0x1110014 +#define ixPSX81_PIF0_LANE0_OVRD2 0x1110015 +#define ixPSX81_PIF0_LANE1_OVRD 0x1110016 +#define ixPSX81_PIF0_LANE1_OVRD2 0x1110017 +#define ixPSX81_PIF0_LANE2_OVRD 0x1110018 +#define ixPSX81_PIF0_LANE2_OVRD2 0x1110019 +#define ixPSX81_PIF0_LANE3_OVRD 0x111001a +#define ixPSX81_PIF0_LANE3_OVRD2 0x111001b +#define ixPSX81_PIF0_LANE4_OVRD 0x111001c +#define ixPSX81_PIF0_LANE4_OVRD2 0x111001d +#define ixPSX81_PIF0_LANE5_OVRD 0x111001e +#define ixPSX81_PIF0_LANE5_OVRD2 0x111001f +#define ixPSX81_PIF0_LANE6_OVRD 0x1110020 +#define ixPSX81_PIF0_LANE6_OVRD2 0x1110021 +#define ixPSX81_PIF0_LANE7_OVRD 0x1110022 +#define ixPSX81_PIF0_LANE7_OVRD2 0x1110023 + +#endif /* BIF_5_1_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h new file mode 100644 index 000000000000..d8d5ae0b341f --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h @@ -0,0 +1,1068 @@ +/* + * BIF_5_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_5_1_ENUM_H +#define BIF_5_1_ENUM_H + +typedef enum DebugBlockId { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_UVDU = 0xd, + DBG_BLOCK_ID_SQA = 0xe, + DBG_BLOCK_ID_SDMA0 = 0xf, + DBG_BLOCK_ID_SDMA1 = 0x10, + DBG_BLOCK_ID_SPIM = 0x11, + DBG_BLOCK_ID_GDS = 0x12, + DBG_BLOCK_ID_VC0 = 0x13, + DBG_BLOCK_ID_VC1 = 0x14, + DBG_BLOCK_ID_PA0 = 0x15, + DBG_BLOCK_ID_PA1 = 0x16, + DBG_BLOCK_ID_CP0 = 0x17, + DBG_BLOCK_ID_CP1 = 0x18, + DBG_BLOCK_ID_CP2 = 0x19, + DBG_BLOCK_ID_XBR = 0x1a, + DBG_BLOCK_ID_UVDM = 0x1b, + DBG_BLOCK_ID_VGT0 = 0x1c, + DBG_BLOCK_ID_VGT1 = 0x1d, + DBG_BLOCK_ID_IA = 0x1e, + DBG_BLOCK_ID_SXM0 = 0x1f, + DBG_BLOCK_ID_SXM1 = 0x20, + DBG_BLOCK_ID_SCT0 = 0x21, + DBG_BLOCK_ID_SCT1 = 0x22, + DBG_BLOCK_ID_SPM0 = 0x23, + DBG_BLOCK_ID_SPM1 = 0x24, + DBG_BLOCK_ID_UNUSED0 = 0x25, + DBG_BLOCK_ID_UNUSED1 = 0x26, + DBG_BLOCK_ID_TCAA = 0x27, + DBG_BLOCK_ID_TCAB = 0x28, + DBG_BLOCK_ID_TCCA = 0x29, + DBG_BLOCK_ID_TCCB = 0x2a, + DBG_BLOCK_ID_MCC0 = 0x2b, + DBG_BLOCK_ID_MCC1 = 0x2c, + DBG_BLOCK_ID_MCC2 = 0x2d, + DBG_BLOCK_ID_MCC3 = 0x2e, + DBG_BLOCK_ID_SXS0 = 0x2f, + DBG_BLOCK_ID_SXS1 = 0x30, + DBG_BLOCK_ID_SXS2 = 0x31, + DBG_BLOCK_ID_SXS3 = 0x32, + DBG_BLOCK_ID_SXS4 = 0x33, + DBG_BLOCK_ID_SXS5 = 0x34, + DBG_BLOCK_ID_SXS6 = 0x35, + DBG_BLOCK_ID_SXS7 = 0x36, + DBG_BLOCK_ID_SXS8 = 0x37, + DBG_BLOCK_ID_SXS9 = 0x38, + DBG_BLOCK_ID_BCI0 = 0x39, + DBG_BLOCK_ID_BCI1 = 0x3a, + DBG_BLOCK_ID_BCI2 = 0x3b, + DBG_BLOCK_ID_BCI3 = 0x3c, + DBG_BLOCK_ID_MCB = 0x3d, + DBG_BLOCK_ID_UNUSED6 = 0x3e, + DBG_BLOCK_ID_SQA00 = 0x3f, + DBG_BLOCK_ID_SQA01 = 0x40, + DBG_BLOCK_ID_SQA02 = 0x41, + DBG_BLOCK_ID_SQA10 = 0x42, + DBG_BLOCK_ID_SQA11 = 0x43, + DBG_BLOCK_ID_SQA12 = 0x44, + DBG_BLOCK_ID_UNUSED7 = 0x45, + DBG_BLOCK_ID_UNUSED8 = 0x46, + DBG_BLOCK_ID_SQB00 = 0x47, + DBG_BLOCK_ID_SQB01 = 0x48, + DBG_BLOCK_ID_SQB10 = 0x49, + DBG_BLOCK_ID_SQB11 = 0x4a, + DBG_BLOCK_ID_SQ00 = 0x4b, + DBG_BLOCK_ID_SQ01 = 0x4c, + DBG_BLOCK_ID_SQ10 = 0x4d, + DBG_BLOCK_ID_SQ11 = 0x4e, + DBG_BLOCK_ID_CB00 = 0x4f, + DBG_BLOCK_ID_CB01 = 0x50, + DBG_BLOCK_ID_CB02 = 0x51, + DBG_BLOCK_ID_CB03 = 0x52, + DBG_BLOCK_ID_CB04 = 0x53, + DBG_BLOCK_ID_UNUSED9 = 0x54, + DBG_BLOCK_ID_UNUSED10 = 0x55, + DBG_BLOCK_ID_UNUSED11 = 0x56, + DBG_BLOCK_ID_CB10 = 0x57, + DBG_BLOCK_ID_CB11 = 0x58, + DBG_BLOCK_ID_CB12 = 0x59, + DBG_BLOCK_ID_CB13 = 0x5a, + DBG_BLOCK_ID_CB14 = 0x5b, + DBG_BLOCK_ID_UNUSED12 = 0x5c, + DBG_BLOCK_ID_UNUSED13 = 0x5d, + DBG_BLOCK_ID_UNUSED14 = 0x5e, + DBG_BLOCK_ID_TCP0 = 0x5f, + DBG_BLOCK_ID_TCP1 = 0x60, + DBG_BLOCK_ID_TCP2 = 0x61, + DBG_BLOCK_ID_TCP3 = 0x62, + DBG_BLOCK_ID_TCP4 = 0x63, + DBG_BLOCK_ID_TCP5 = 0x64, + DBG_BLOCK_ID_TCP6 = 0x65, + DBG_BLOCK_ID_TCP7 = 0x66, + DBG_BLOCK_ID_TCP8 = 0x67, + DBG_BLOCK_ID_TCP9 = 0x68, + DBG_BLOCK_ID_TCP10 = 0x69, + DBG_BLOCK_ID_TCP11 = 0x6a, + DBG_BLOCK_ID_TCP12 = 0x6b, + DBG_BLOCK_ID_TCP13 = 0x6c, + DBG_BLOCK_ID_TCP14 = 0x6d, + DBG_BLOCK_ID_TCP15 = 0x6e, + DBG_BLOCK_ID_TCP16 = 0x6f, + DBG_BLOCK_ID_TCP17 = 0x70, + DBG_BLOCK_ID_TCP18 = 0x71, + DBG_BLOCK_ID_TCP19 = 0x72, + DBG_BLOCK_ID_TCP20 = 0x73, + DBG_BLOCK_ID_TCP21 = 0x74, + DBG_BLOCK_ID_TCP22 = 0x75, + DBG_BLOCK_ID_TCP23 = 0x76, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, + DBG_BLOCK_ID_DB00 = 0x7f, + DBG_BLOCK_ID_DB01 = 0x80, + DBG_BLOCK_ID_DB02 = 0x81, + DBG_BLOCK_ID_DB03 = 0x82, + DBG_BLOCK_ID_DB04 = 0x83, + DBG_BLOCK_ID_UNUSED15 = 0x84, + DBG_BLOCK_ID_UNUSED16 = 0x85, + DBG_BLOCK_ID_UNUSED17 = 0x86, + DBG_BLOCK_ID_DB10 = 0x87, + DBG_BLOCK_ID_DB11 = 0x88, + DBG_BLOCK_ID_DB12 = 0x89, + DBG_BLOCK_ID_DB13 = 0x8a, + DBG_BLOCK_ID_DB14 = 0x8b, + DBG_BLOCK_ID_UNUSED18 = 0x8c, + DBG_BLOCK_ID_UNUSED19 = 0x8d, + DBG_BLOCK_ID_UNUSED20 = 0x8e, + DBG_BLOCK_ID_TCC0 = 0x8f, + DBG_BLOCK_ID_TCC1 = 0x90, + DBG_BLOCK_ID_TCC2 = 0x91, + DBG_BLOCK_ID_TCC3 = 0x92, + DBG_BLOCK_ID_TCC4 = 0x93, + DBG_BLOCK_ID_TCC5 = 0x94, + DBG_BLOCK_ID_TCC6 = 0x95, + DBG_BLOCK_ID_TCC7 = 0x96, + DBG_BLOCK_ID_SPS00 = 0x97, + DBG_BLOCK_ID_SPS01 = 0x98, + DBG_BLOCK_ID_SPS02 = 0x99, + DBG_BLOCK_ID_SPS10 = 0x9a, + DBG_BLOCK_ID_SPS11 = 0x9b, + DBG_BLOCK_ID_SPS12 = 0x9c, + DBG_BLOCK_ID_UNUSED21 = 0x9d, + DBG_BLOCK_ID_UNUSED22 = 0x9e, + DBG_BLOCK_ID_TA00 = 0x9f, + DBG_BLOCK_ID_TA01 = 0xa0, + DBG_BLOCK_ID_TA02 = 0xa1, + DBG_BLOCK_ID_TA03 = 0xa2, + DBG_BLOCK_ID_TA04 = 0xa3, + DBG_BLOCK_ID_TA05 = 0xa4, + DBG_BLOCK_ID_TA06 = 0xa5, + DBG_BLOCK_ID_TA07 = 0xa6, + DBG_BLOCK_ID_TA08 = 0xa7, + DBG_BLOCK_ID_TA09 = 0xa8, + DBG_BLOCK_ID_TA0A = 0xa9, + DBG_BLOCK_ID_TA0B = 0xaa, + DBG_BLOCK_ID_UNUSED23 = 0xab, + DBG_BLOCK_ID_UNUSED24 = 0xac, + DBG_BLOCK_ID_UNUSED25 = 0xad, + DBG_BLOCK_ID_UNUSED26 = 0xae, + DBG_BLOCK_ID_TA10 = 0xaf, + DBG_BLOCK_ID_TA11 = 0xb0, + DBG_BLOCK_ID_TA12 = 0xb1, + DBG_BLOCK_ID_TA13 = 0xb2, + DBG_BLOCK_ID_TA14 = 0xb3, + DBG_BLOCK_ID_TA15 = 0xb4, + DBG_BLOCK_ID_TA16 = 0xb5, + DBG_BLOCK_ID_TA17 = 0xb6, + DBG_BLOCK_ID_TA18 = 0xb7, + DBG_BLOCK_ID_TA19 = 0xb8, + DBG_BLOCK_ID_TA1A = 0xb9, + DBG_BLOCK_ID_TA1B = 0xba, + DBG_BLOCK_ID_UNUSED27 = 0xbb, + DBG_BLOCK_ID_UNUSED28 = 0xbc, + DBG_BLOCK_ID_UNUSED29 = 0xbd, + DBG_BLOCK_ID_UNUSED30 = 0xbe, + DBG_BLOCK_ID_TD00 = 0xbf, + DBG_BLOCK_ID_TD01 = 0xc0, + DBG_BLOCK_ID_TD02 = 0xc1, + DBG_BLOCK_ID_TD03 = 0xc2, + DBG_BLOCK_ID_TD04 = 0xc3, + DBG_BLOCK_ID_TD05 = 0xc4, + DBG_BLOCK_ID_TD06 = 0xc5, + DBG_BLOCK_ID_TD07 = 0xc6, + DBG_BLOCK_ID_TD08 = 0xc7, + DBG_BLOCK_ID_TD09 = 0xc8, + DBG_BLOCK_ID_TD0A = 0xc9, + DBG_BLOCK_ID_TD0B = 0xca, + DBG_BLOCK_ID_UNUSED31 = 0xcb, + DBG_BLOCK_ID_UNUSED32 = 0xcc, + DBG_BLOCK_ID_UNUSED33 = 0xcd, + DBG_BLOCK_ID_UNUSED34 = 0xce, + DBG_BLOCK_ID_TD10 = 0xcf, + DBG_BLOCK_ID_TD11 = 0xd0, + DBG_BLOCK_ID_TD12 = 0xd1, + DBG_BLOCK_ID_TD13 = 0xd2, + DBG_BLOCK_ID_TD14 = 0xd3, + DBG_BLOCK_ID_TD15 = 0xd4, + DBG_BLOCK_ID_TD16 = 0xd5, + DBG_BLOCK_ID_TD17 = 0xd6, + DBG_BLOCK_ID_TD18 = 0xd7, + DBG_BLOCK_ID_TD19 = 0xd8, + DBG_BLOCK_ID_TD1A = 0xd9, + DBG_BLOCK_ID_TD1B = 0xda, + DBG_BLOCK_ID_UNUSED35 = 0xdb, + DBG_BLOCK_ID_UNUSED36 = 0xdc, + DBG_BLOCK_ID_UNUSED37 = 0xdd, + DBG_BLOCK_ID_UNUSED38 = 0xde, + DBG_BLOCK_ID_LDS00 = 0xdf, + DBG_BLOCK_ID_LDS01 = 0xe0, + DBG_BLOCK_ID_LDS02 = 0xe1, + DBG_BLOCK_ID_LDS03 = 0xe2, + DBG_BLOCK_ID_LDS04 = 0xe3, + DBG_BLOCK_ID_LDS05 = 0xe4, + DBG_BLOCK_ID_LDS06 = 0xe5, + DBG_BLOCK_ID_LDS07 = 0xe6, + DBG_BLOCK_ID_LDS08 = 0xe7, + DBG_BLOCK_ID_LDS09 = 0xe8, + DBG_BLOCK_ID_LDS0A = 0xe9, + DBG_BLOCK_ID_LDS0B = 0xea, + DBG_BLOCK_ID_UNUSED39 = 0xeb, + DBG_BLOCK_ID_UNUSED40 = 0xec, + DBG_BLOCK_ID_UNUSED41 = 0xed, + DBG_BLOCK_ID_UNUSED42 = 0xee, + DBG_BLOCK_ID_LDS10 = 0xef, + DBG_BLOCK_ID_LDS11 = 0xf0, + DBG_BLOCK_ID_LDS12 = 0xf1, + DBG_BLOCK_ID_LDS13 = 0xf2, + DBG_BLOCK_ID_LDS14 = 0xf3, + DBG_BLOCK_ID_LDS15 = 0xf4, + DBG_BLOCK_ID_LDS16 = 0xf5, + DBG_BLOCK_ID_LDS17 = 0xf6, + DBG_BLOCK_ID_LDS18 = 0xf7, + DBG_BLOCK_ID_LDS19 = 0xf8, + DBG_BLOCK_ID_LDS1A = 0xf9, + DBG_BLOCK_ID_LDS1B = 0xfa, + DBG_BLOCK_ID_UNUSED43 = 0xfb, + DBG_BLOCK_ID_UNUSED44 = 0xfc, + DBG_BLOCK_ID_UNUSED45 = 0xfd, + DBG_BLOCK_ID_UNUSED46 = 0xfe, +} DebugBlockId; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_UVD_BY2 = 0x7, + DBG_BLOCK_ID_SDMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_VC0_BY2 = 0xa, + DBG_BLOCK_ID_PA_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_PC0_BY2 = 0xe, + DBG_BLOCK_ID_BCI0_BY2 = 0xf, + DBG_BLOCK_ID_SXM0_BY2 = 0x10, + DBG_BLOCK_ID_SCT0_BY2 = 0x11, + DBG_BLOCK_ID_SPM0_BY2 = 0x12, + DBG_BLOCK_ID_BCI2_BY2 = 0x13, + DBG_BLOCK_ID_TCA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_MCD_BY2 = 0x18, + DBG_BLOCK_ID_MCD2_BY2 = 0x19, + DBG_BLOCK_ID_MCD4_BY2 = 0x1a, + DBG_BLOCK_ID_MCB_BY2 = 0x1b, + DBG_BLOCK_ID_SQA_BY2 = 0x1c, + DBG_BLOCK_ID_SQA02_BY2 = 0x1d, + DBG_BLOCK_ID_SQA11_BY2 = 0x1e, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, + DBG_BLOCK_ID_SQB_BY2 = 0x20, + DBG_BLOCK_ID_SQB10_BY2 = 0x21, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, + DBG_BLOCK_ID_CB_BY2 = 0x24, + DBG_BLOCK_ID_CB02_BY2 = 0x25, + DBG_BLOCK_ID_CB10_BY2 = 0x26, + DBG_BLOCK_ID_CB12_BY2 = 0x27, + DBG_BLOCK_ID_SXS_BY2 = 0x28, + DBG_BLOCK_ID_SXS2_BY2 = 0x29, + DBG_BLOCK_ID_SXS4_BY2 = 0x2a, + DBG_BLOCK_ID_SXS6_BY2 = 0x2b, + DBG_BLOCK_ID_DB_BY2 = 0x2c, + DBG_BLOCK_ID_DB02_BY2 = 0x2d, + DBG_BLOCK_ID_DB10_BY2 = 0x2e, + DBG_BLOCK_ID_DB12_BY2 = 0x2f, + DBG_BLOCK_ID_TCP_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_TCC_BY2 = 0x40, + DBG_BLOCK_ID_TCC2_BY2 = 0x41, + DBG_BLOCK_ID_TCC4_BY2 = 0x42, + DBG_BLOCK_ID_TCC6_BY2 = 0x43, + DBG_BLOCK_ID_SPS_BY2 = 0x44, + DBG_BLOCK_ID_SPS02_BY2 = 0x45, + DBG_BLOCK_ID_SPS11_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, + DBG_BLOCK_ID_TA_BY2 = 0x48, + DBG_BLOCK_ID_TA02_BY2 = 0x49, + DBG_BLOCK_ID_TA04_BY2 = 0x4a, + DBG_BLOCK_ID_TA06_BY2 = 0x4b, + DBG_BLOCK_ID_TA08_BY2 = 0x4c, + DBG_BLOCK_ID_TA0A_BY2 = 0x4d, + DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, + DBG_BLOCK_ID_TA10_BY2 = 0x50, + DBG_BLOCK_ID_TA12_BY2 = 0x51, + DBG_BLOCK_ID_TA14_BY2 = 0x52, + DBG_BLOCK_ID_TA16_BY2 = 0x53, + DBG_BLOCK_ID_TA18_BY2 = 0x54, + DBG_BLOCK_ID_TA1A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, + DBG_BLOCK_ID_TD_BY2 = 0x58, + DBG_BLOCK_ID_TD02_BY2 = 0x59, + DBG_BLOCK_ID_TD04_BY2 = 0x5a, + DBG_BLOCK_ID_TD06_BY2 = 0x5b, + DBG_BLOCK_ID_TD08_BY2 = 0x5c, + DBG_BLOCK_ID_TD0A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, + DBG_BLOCK_ID_TD10_BY2 = 0x60, + DBG_BLOCK_ID_TD12_BY2 = 0x61, + DBG_BLOCK_ID_TD14_BY2 = 0x62, + DBG_BLOCK_ID_TD16_BY2 = 0x63, + DBG_BLOCK_ID_TD18_BY2 = 0x64, + DBG_BLOCK_ID_TD1A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, + DBG_BLOCK_ID_LDS_BY2 = 0x68, + DBG_BLOCK_ID_LDS02_BY2 = 0x69, + DBG_BLOCK_ID_LDS04_BY2 = 0x6a, + DBG_BLOCK_ID_LDS06_BY2 = 0x6b, + DBG_BLOCK_ID_LDS08_BY2 = 0x6c, + DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, + DBG_BLOCK_ID_LDS10_BY2 = 0x70, + DBG_BLOCK_ID_LDS12_BY2 = 0x71, + DBG_BLOCK_ID_LDS14_BY2 = 0x72, + DBG_BLOCK_ID_LDS16_BY2 = 0x73, + DBG_BLOCK_ID_LDS18_BY2 = 0x74, + DBG_BLOCK_ID_LDS1A_BY2 = 0x75, + DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, + DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_SDMA0_BY4 = 0x4, + DBG_BLOCK_ID_VC0_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, + DBG_BLOCK_ID_SXM0_BY4 = 0x8, + DBG_BLOCK_ID_SPM0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC_BY4 = 0xb, + DBG_BLOCK_ID_MCD_BY4 = 0xc, + DBG_BLOCK_ID_MCD4_BY4 = 0xd, + DBG_BLOCK_ID_SQA_BY4 = 0xe, + DBG_BLOCK_ID_SQA11_BY4 = 0xf, + DBG_BLOCK_ID_SQB_BY4 = 0x10, + DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, + DBG_BLOCK_ID_CB_BY4 = 0x12, + DBG_BLOCK_ID_CB10_BY4 = 0x13, + DBG_BLOCK_ID_SXS_BY4 = 0x14, + DBG_BLOCK_ID_SXS4_BY4 = 0x15, + DBG_BLOCK_ID_DB_BY4 = 0x16, + DBG_BLOCK_ID_DB10_BY4 = 0x17, + DBG_BLOCK_ID_TCP_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_TCC_BY4 = 0x20, + DBG_BLOCK_ID_TCC4_BY4 = 0x21, + DBG_BLOCK_ID_SPS_BY4 = 0x22, + DBG_BLOCK_ID_SPS11_BY4 = 0x23, + DBG_BLOCK_ID_TA_BY4 = 0x24, + DBG_BLOCK_ID_TA04_BY4 = 0x25, + DBG_BLOCK_ID_TA08_BY4 = 0x26, + DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, + DBG_BLOCK_ID_TA10_BY4 = 0x28, + DBG_BLOCK_ID_TA14_BY4 = 0x29, + DBG_BLOCK_ID_TA18_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, + DBG_BLOCK_ID_TD_BY4 = 0x2c, + DBG_BLOCK_ID_TD04_BY4 = 0x2d, + DBG_BLOCK_ID_TD08_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, + DBG_BLOCK_ID_TD10_BY4 = 0x30, + DBG_BLOCK_ID_TD14_BY4 = 0x31, + DBG_BLOCK_ID_TD18_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, + DBG_BLOCK_ID_LDS_BY4 = 0x34, + DBG_BLOCK_ID_LDS04_BY4 = 0x35, + DBG_BLOCK_ID_LDS08_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, + DBG_BLOCK_ID_LDS10_BY4 = 0x38, + DBG_BLOCK_ID_LDS14_BY4 = 0x39, + DBG_BLOCK_ID_LDS18_BY4 = 0x3a, + DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_SDMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_SXM0_BY8 = 0x4, + DBG_BLOCK_ID_TCA_BY8 = 0x5, + DBG_BLOCK_ID_MCD_BY8 = 0x6, + DBG_BLOCK_ID_SQA_BY8 = 0x7, + DBG_BLOCK_ID_SQB_BY8 = 0x8, + DBG_BLOCK_ID_CB_BY8 = 0x9, + DBG_BLOCK_ID_SXS_BY8 = 0xa, + DBG_BLOCK_ID_DB_BY8 = 0xb, + DBG_BLOCK_ID_TCP_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_TCC_BY8 = 0x10, + DBG_BLOCK_ID_SPS_BY8 = 0x11, + DBG_BLOCK_ID_TA_BY8 = 0x12, + DBG_BLOCK_ID_TA08_BY8 = 0x13, + DBG_BLOCK_ID_TA10_BY8 = 0x14, + DBG_BLOCK_ID_TA18_BY8 = 0x15, + DBG_BLOCK_ID_TD_BY8 = 0x16, + DBG_BLOCK_ID_TD08_BY8 = 0x17, + DBG_BLOCK_ID_TD10_BY8 = 0x18, + DBG_BLOCK_ID_TD18_BY8 = 0x19, + DBG_BLOCK_ID_LDS_BY8 = 0x1a, + DBG_BLOCK_ID_LDS08_BY8 = 0x1b, + DBG_BLOCK_ID_LDS10_BY8 = 0x1c, + DBG_BLOCK_ID_LDS18_BY8 = 0x1d, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_SDMA0_BY16 = 0x1, + DBG_BLOCK_ID_SXM_BY16 = 0x2, + DBG_BLOCK_ID_MCD_BY16 = 0x3, + DBG_BLOCK_ID_SQB_BY16 = 0x4, + DBG_BLOCK_ID_SXS_BY16 = 0x5, + DBG_BLOCK_ID_TCP_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_TCC_BY16 = 0x8, + DBG_BLOCK_ID_TA_BY16 = 0x9, + DBG_BLOCK_ID_TA10_BY16 = 0xa, + DBG_BLOCK_ID_TD_BY16 = 0xb, + DBG_BLOCK_ID_TD10_BY16 = 0xc, + DBG_BLOCK_ID_LDS_BY16 = 0xd, + DBG_BLOCK_ID_LDS10_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* BIF_5_1_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h new file mode 100644 index 000000000000..ee1da0cbc84d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h @@ -0,0 +1,33080 @@ +/* + * BIF_5_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef BIF_5_1_SH_MASK_H +#define BIF_5_1_SH_MASK_H + +#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff +#define MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define MM_INDEX__MM_APER_MASK 0x80000000 +#define MM_INDEX__MM_APER__SHIFT 0x1f +#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff +#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define MM_DATA__MM_DATA_MASK 0xffffffff +#define MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2 +#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1 +#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0 +#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2 +#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1 +#define BUS_CNTL__PMI_IO_DIS_MASK 0x4 +#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8 +#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define BUS_CNTL__PMI_BM_DIS_MASK 0x10 +#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define BUS_CNTL__PMI_INT_DIS_MASK 0x20 +#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5 +#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40 +#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80 +#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100 +#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8 +#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00 +#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BUS_CNTL__SET_MC_TC_MASK 0xe000 +#define BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000 +#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000 +#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000 +#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1 +#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define CONFIG_CNTL__VGA_DIS_MASK 0x2 +#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1 +#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4 +#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18 +#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff +#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff +#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff +#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff +#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff +#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff +#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BX_RESET_EN__COR_RESET_EN_MASK 0x1 +#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 +#define BX_RESET_EN__REG_RESET_EN_MASK 0x2 +#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 +#define BX_RESET_EN__STY_RESET_EN_MASK 0x4 +#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7 +#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8 +#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3 +#define HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000 +#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 +#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000 +#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 +#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000 +#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 +#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000 +#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 +#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000 +#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 +#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000 +#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 +#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000 +#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 +#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000 +#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 +#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 +#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 +#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 +#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 +#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 +#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a +#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 +#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b +#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 +#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c +#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 +#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d +#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 +#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e +#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 +#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f +#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f +#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0 +#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000 +#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10 +#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f +#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0 +#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0 +#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5 +#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00 +#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa +#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000 +#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf +#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000 +#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14 +#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000 +#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19 +#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1 +#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1 +#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2 +#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8 +#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0 +#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100 +#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00 +#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9 +#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000 +#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd +#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000 +#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff +#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1 +#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0 +#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2 +#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1 +#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4 +#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2 +#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8 +#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20 +#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6 +#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80 +#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000 +#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000 +#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0 +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00 +#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8 +#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff +#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0 +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1 +#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1 +#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000 +#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x1 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x0 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x2 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x1 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x4 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x2 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x18 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x3 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x20 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x5 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x40 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x6 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x80 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x7 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x100 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x8 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x200 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x9 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x400 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x800 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0xb +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x1000 +#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0xc +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x1 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x0 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x2 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x1 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x4 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x2 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x18 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x3 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x20 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x5 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x40 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x6 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x80 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x7 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x100 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x8 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x200 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x9 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x400 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x800 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0xb +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x1000 +#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0xc +#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff +#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000 +#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff +#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1 +#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2 +#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4 +#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8 +#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10 +#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40 +#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 +#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80 +#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7 +#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100 +#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8 +#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200 +#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 +#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400 +#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa +#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800 +#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb +#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000 +#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1 +#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2 +#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4 +#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8 +#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x10 +#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x20 +#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5 +#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000 +#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3 +#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0 +#define BIF_FB_EN__FB_READ_EN_MASK 0x1 +#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2 +#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff +#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define BIF_BUSNUM_LIST0__ID0_MASK 0xff +#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00 +#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000 +#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000 +#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define BIF_BUSNUM_LIST1__ID4_MASK 0xff +#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00 +#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000 +#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000 +#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100 +#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000 +#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000 +#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f +#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 +#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1 +#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4 +#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2 +#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00 +#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8 +#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000 +#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd +#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff +#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 +#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff +#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 +#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe +#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1 +#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1 +#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2 +#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4 +#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8 +#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10 +#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20 +#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40 +#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80 +#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100 +#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200 +#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400 +#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800 +#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1 +#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2 +#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4 +#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8 +#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10 +#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20 +#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40 +#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80 +#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100 +#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200 +#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400 +#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800 +#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1 +#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0 +#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2 +#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1 +#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4 +#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2 +#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8 +#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3 +#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10 +#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4 +#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20 +#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5 +#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80 +#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7 +#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100 +#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8 +#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200 +#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9 +#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1 +#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define HOST_BUSNUM__HOST_ID_MASK 0xffff +#define HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff +#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000 +#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff +#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000 +#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff +#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff +#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000 +#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff +#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff +#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000 +#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff +#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff +#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000 +#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff +#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff +#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000 +#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1 +#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0 +#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD_MASK 0x1e +#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD__SHIFT 0x1 +#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff +#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000 +#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000 +#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define BACO_CNTL__BACO_EN_MASK 0x1 +#define BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2 +#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1 +#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4 +#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2 +#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8 +#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BACO_CNTL__BACO_RESET_EN_MASK 0x10 +#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4 +#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20 +#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5 +#define BACO_CNTL__BACO_MODE_MASK 0x40 +#define BACO_CNTL__BACO_MODE__SHIFT 0x6 +#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80 +#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7 +#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100 +#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8 +#define BACO_CNTL__PWRGOOD_BF_MASK 0x200 +#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9 +#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400 +#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa +#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800 +#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb +#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000 +#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc +#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000 +#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd +#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000 +#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10 +#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000 +#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11 +#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1 +#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0 +#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2 +#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1 +#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1 +#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1 +#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0 +#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1 +#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0 +#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1 +#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2 +#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc +#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2 +#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x1 +#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x1 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x10 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x20 +#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000 +#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f +#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000 +#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f +#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 +#define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK 0x7fffc +#define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2 +#define BIF_SMU_DATA__BIF_SMU_DATA_MASK 0x7fffc +#define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2 +#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1 +#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0 +#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1 +#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0 +#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2 +#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1 +#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4 +#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2 +#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8 +#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3 +#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10 +#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4 +#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20 +#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5 +#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40 +#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6 +#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80 +#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200 +#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9 +#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400 +#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800 +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000 +#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc +#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000 +#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd +#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000 +#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe +#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK 0x8000 +#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT 0xf +#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000 +#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10 +#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK 0x20000 +#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT 0x11 +#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK 0x40000 +#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT 0x12 +#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000 +#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e +#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000 +#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f +#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1 +#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0 +#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2 +#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1 +#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc +#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2 +#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1 +#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1 +#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2 +#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1 +#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4 +#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2 +#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8 +#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3 +#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10 +#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4 +#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20 +#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5 +#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40 +#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6 +#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80 +#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7 +#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100 +#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8 +#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200 +#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9 +#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400 +#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa +#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800 +#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb +#define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK 0x1000 +#define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT 0xc +#define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK 0x2000 +#define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd +#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1 +#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2 +#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1 +#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4 +#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2 +#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8 +#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3 +#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10 +#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4 +#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20 +#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5 +#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40 +#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6 +#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80 +#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7 +#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100 +#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8 +#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200 +#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9 +#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400 +#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa +#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800 +#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb +#define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK 0x1000 +#define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT 0xc +#define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK 0x2000 +#define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd +#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS__SHIFT 0x2 +#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x7fffc +#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x7fffc +#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff +#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff +#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff +#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff +#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff +#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff +#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff +#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff +#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff +#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff +#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff +#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff +#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff +#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff +#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff +#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff +#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_RB_CNTL__RB_ENABLE_MASK 0x1 +#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_RB_CNTL__RB_SIZE_MASK 0x3e +#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 +#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00 +#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x20000 +#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 +#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_RB_BASE__ADDR_MASK 0xffffffff +#define BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_RB_RPTR__OFFSET_MASK 0x3fffc +#define BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x1 +#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_RB_WPTR__OFFSET_MASK 0x3fffc +#define BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0xff +#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VENDOR_ID__VENDOR_ID_MASK 0xffff +#define VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define DEVICE_ID__DEVICE_ID_MASK 0xffff +#define DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define COMMAND__IO_ACCESS_EN_MASK 0x1 +#define COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define COMMAND__BUS_MASTER_EN_MASK 0x4 +#define COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define COMMAND__AD_STEPPING_MASK 0x80 +#define COMMAND__AD_STEPPING__SHIFT 0x7 +#define COMMAND__SERR_EN_MASK 0x100 +#define COMMAND__SERR_EN__SHIFT 0x8 +#define COMMAND__FAST_B2B_EN_MASK 0x200 +#define COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define COMMAND__INT_DIS_MASK 0x400 +#define COMMAND__INT_DIS__SHIFT 0xa +#define STATUS__INT_STATUS_MASK 0x8 +#define STATUS__INT_STATUS__SHIFT 0x3 +#define STATUS__CAP_LIST_MASK 0x10 +#define STATUS__CAP_LIST__SHIFT 0x4 +#define STATUS__PCI_66_EN_MASK 0x20 +#define STATUS__PCI_66_EN__SHIFT 0x5 +#define STATUS__FAST_BACK_CAPABLE_MASK 0x80 +#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100 +#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define STATUS__DEVSEL_TIMING_MASK 0x600 +#define STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800 +#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000 +#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000 +#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000 +#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000 +#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define REVISION_ID__MINOR_REV_ID_MASK 0xf +#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff +#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define SUB_CLASS__SUB_CLASS_MASK 0xff +#define SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BASE_CLASS__BASE_CLASS_MASK 0xff +#define BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define LATENCY__LATENCY_TIMER_MASK 0xff +#define LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define HEADER__HEADER_TYPE_MASK 0x7f +#define HEADER__HEADER_TYPE__SHIFT 0x0 +#define HEADER__DEVICE_TYPE_MASK 0x80 +#define HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIST__BIST_COMP_MASK 0xf +#define BIST__BIST_COMP__SHIFT 0x0 +#define BIST__BIST_STRT_MASK 0x40 +#define BIST__BIST_STRT__SHIFT 0x6 +#define BIST__BIST_CAP_MASK 0x80 +#define BIST__BIST_CAP__SHIFT 0x7 +#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff +#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff +#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CAP_PTR__CAP_PTR_MASK 0xff +#define CAP_PTR__CAP_PTR__SHIFT 0x0 +#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff +#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000 +#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define MIN_GRANT__MIN_GNT_MASK 0xff +#define MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define MAX_LATENCY__MAX_LAT_MASK 0xff +#define MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff +#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000 +#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000 +#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define PMI_CAP_LIST__CAP_ID_MASK 0xff +#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PMI_CAP__VERSION_MASK 0x7 +#define PMI_CAP__VERSION__SHIFT 0x0 +#define PMI_CAP__PME_CLOCK_MASK 0x8 +#define PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20 +#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define PMI_CAP__AUX_CURRENT_MASK 0x1c0 +#define PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define PMI_CAP__D1_SUPPORT_MASK 0x200 +#define PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define PMI_CAP__D2_SUPPORT_MASK 0x400 +#define PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define PMI_CAP__PME_SUPPORT_MASK 0xf800 +#define PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define PCIE_CAP__VERSION_MASK 0xf +#define PCIE_CAP__VERSION__SHIFT 0x0 +#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0 +#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100 +#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00 +#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000 +#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define DEVICE_STATUS__CORR_ERR_MASK 0x1 +#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2 +#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define DEVICE_STATUS__FATAL_ERR_MASK 0x4 +#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define DEVICE_STATUS__USR_DETECTED_MASK 0x8 +#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define DEVICE_STATUS__AUX_PWR_MASK 0x10 +#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20 +#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define LINK_CAP__LINK_SPEED_MASK 0xf +#define LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define LINK_CNTL__PM_CONTROL_MASK 0x3 +#define LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define LINK_CNTL__LINK_DIS_MASK 0x10 +#define LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf +#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0 +#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define LINK_STATUS__LINK_TRAINING_MASK 0x800 +#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000 +#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define LINK_STATUS__DL_ACTIVE_MASK 0x2000 +#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000 +#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000 +#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define DEVICE_STATUS2__RESERVED_MASK 0xffff +#define DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define LINK_CAP2__RESERVED__SHIFT 0x9 +#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1 +#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2 +#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4 +#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8 +#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10 +#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20 +#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +#define MSI_CAP_LIST__CAP_ID_MASK 0xff +#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define MSI_MSG_CNTL__MSI_EN_MASK 0x1 +#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe +#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70 +#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80 +#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1 +#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 +#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 +#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 +#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 +#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 +#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7 +#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0 +#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00 +#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff +#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff +#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300 +#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00 +#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000 +#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000 +#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000 +#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1 +#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f +#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 +#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 +#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 +#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff +#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f +#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100 +#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f +#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1 +#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2 +#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4 +#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8 +#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10 +#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20 +#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40 +#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f +#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20 +#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40 +#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define PCIE_ATS_CNTL__STU_MASK 0x1f +#define PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000 +#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1 +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2 +#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1 +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2 +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100 +#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000 +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2 +#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4 +#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00 +#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1 +#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2 +#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4 +#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1 +#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 +#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2 +#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 +#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4 +#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 +#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100 +#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000 +#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300 +#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 +#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00 +#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f +#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000 +#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00 +#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000 +#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define MM_INDEX_IND__MM_OFFSET_MASK 0x7fffffff +#define MM_INDEX_IND__MM_OFFSET__SHIFT 0x0 +#define MM_INDEX_IND__MM_APER_MASK 0x80000000 +#define MM_INDEX_IND__MM_APER__SHIFT 0x1f +#define MM_INDEX_HI_IND__MM_OFFSET_HI_MASK 0xffffffff +#define MM_INDEX_HI_IND__MM_OFFSET_HI__SHIFT 0x0 +#define MM_DATA_IND__MM_DATA_MASK 0xffffffff +#define MM_DATA_IND__MM_DATA__SHIFT 0x0 +#define BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS_MASK 0x2 +#define BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS__SHIFT 0x1 +#define BUS_CNTL_IND__BIOS_ROM_WRT_EN_MASK 0x1 +#define BUS_CNTL_IND__BIOS_ROM_WRT_EN__SHIFT 0x0 +#define BUS_CNTL_IND__BIOS_ROM_DIS_MASK 0x2 +#define BUS_CNTL_IND__BIOS_ROM_DIS__SHIFT 0x1 +#define BUS_CNTL_IND__PMI_IO_DIS_MASK 0x4 +#define BUS_CNTL_IND__PMI_IO_DIS__SHIFT 0x2 +#define BUS_CNTL_IND__PMI_MEM_DIS_MASK 0x8 +#define BUS_CNTL_IND__PMI_MEM_DIS__SHIFT 0x3 +#define BUS_CNTL_IND__PMI_BM_DIS_MASK 0x10 +#define BUS_CNTL_IND__PMI_BM_DIS__SHIFT 0x4 +#define BUS_CNTL_IND__PMI_INT_DIS_MASK 0x20 +#define BUS_CNTL_IND__PMI_INT_DIS__SHIFT 0x5 +#define BUS_CNTL_IND__VGA_REG_COHERENCY_DIS_MASK 0x40 +#define BUS_CNTL_IND__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS_MASK 0x80 +#define BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100 +#define BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8 +#define BUS_CNTL_IND__SET_AZ_TC_MASK 0x1c00 +#define BUS_CNTL_IND__SET_AZ_TC__SHIFT 0xa +#define BUS_CNTL_IND__SET_MC_TC_MASK 0xe000 +#define BUS_CNTL_IND__SET_MC_TC__SHIFT 0xd +#define BUS_CNTL_IND__ZERO_BE_WR_EN_MASK 0x10000 +#define BUS_CNTL_IND__ZERO_BE_WR_EN__SHIFT 0x10 +#define BUS_CNTL_IND__ZERO_BE_RD_EN_MASK 0x20000 +#define BUS_CNTL_IND__ZERO_BE_RD_EN__SHIFT 0x11 +#define BUS_CNTL_IND__RD_STALL_IO_WR_MASK 0x40000 +#define BUS_CNTL_IND__RD_STALL_IO_WR__SHIFT 0x12 +#define CONFIG_CNTL_IND__CFG_VGA_RAM_EN_MASK 0x1 +#define CONFIG_CNTL_IND__CFG_VGA_RAM_EN__SHIFT 0x0 +#define CONFIG_CNTL_IND__VGA_DIS_MASK 0x2 +#define CONFIG_CNTL_IND__VGA_DIS__SHIFT 0x1 +#define CONFIG_CNTL_IND__GENMO_MONO_ADDRESS_B_MASK 0x4 +#define CONFIG_CNTL_IND__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define CONFIG_CNTL_IND__GRPH_ADRSEL_MASK 0x18 +#define CONFIG_CNTL_IND__GRPH_ADRSEL__SHIFT 0x3 +#define CONFIG_MEMSIZE_IND__CONFIG_MEMSIZE_MASK 0xffffffff +#define CONFIG_MEMSIZE_IND__CONFIG_MEMSIZE__SHIFT 0x0 +#define CONFIG_F0_BASE_IND__F0_BASE_MASK 0xffffffff +#define CONFIG_F0_BASE_IND__F0_BASE__SHIFT 0x0 +#define CONFIG_APER_SIZE_IND__APER_SIZE_MASK 0xffffffff +#define CONFIG_APER_SIZE_IND__APER_SIZE__SHIFT 0x0 +#define CONFIG_REG_APER_SIZE_IND__REG_APER_SIZE_MASK 0xfffff +#define CONFIG_REG_APER_SIZE_IND__REG_APER_SIZE__SHIFT 0x0 +#define BIF_SCRATCH0_IND__BIF_SCRATCH0_MASK 0xffffffff +#define BIF_SCRATCH0_IND__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_SCRATCH1_IND__BIF_SCRATCH1_MASK 0xffffffff +#define BIF_SCRATCH1_IND__BIF_SCRATCH1__SHIFT 0x0 +#define BX_RESET_EN_IND__COR_RESET_EN_MASK 0x1 +#define BX_RESET_EN_IND__COR_RESET_EN__SHIFT 0x0 +#define BX_RESET_EN_IND__REG_RESET_EN_MASK 0x2 +#define BX_RESET_EN_IND__REG_RESET_EN__SHIFT 0x1 +#define BX_RESET_EN_IND__STY_RESET_EN_MASK 0x4 +#define BX_RESET_EN_IND__STY_RESET_EN__SHIFT 0x2 +#define MM_CFGREGS_CNTL_IND__MM_CFG_FUNC_SEL_MASK 0x7 +#define MM_CFGREGS_CNTL_IND__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define MM_CFGREGS_CNTL_IND__MM_WR_TO_CFG_EN_MASK 0x8 +#define MM_CFGREGS_CNTL_IND__MM_WR_TO_CFG_EN__SHIFT 0x3 +#define HW_DEBUG_IND__HW_00_DEBUG_MASK 0x1 +#define HW_DEBUG_IND__HW_00_DEBUG__SHIFT 0x0 +#define HW_DEBUG_IND__HW_01_DEBUG_MASK 0x2 +#define HW_DEBUG_IND__HW_01_DEBUG__SHIFT 0x1 +#define HW_DEBUG_IND__HW_02_DEBUG_MASK 0x4 +#define HW_DEBUG_IND__HW_02_DEBUG__SHIFT 0x2 +#define HW_DEBUG_IND__HW_03_DEBUG_MASK 0x8 +#define HW_DEBUG_IND__HW_03_DEBUG__SHIFT 0x3 +#define HW_DEBUG_IND__HW_04_DEBUG_MASK 0x10 +#define HW_DEBUG_IND__HW_04_DEBUG__SHIFT 0x4 +#define HW_DEBUG_IND__HW_05_DEBUG_MASK 0x20 +#define HW_DEBUG_IND__HW_05_DEBUG__SHIFT 0x5 +#define HW_DEBUG_IND__HW_06_DEBUG_MASK 0x40 +#define HW_DEBUG_IND__HW_06_DEBUG__SHIFT 0x6 +#define HW_DEBUG_IND__HW_07_DEBUG_MASK 0x80 +#define HW_DEBUG_IND__HW_07_DEBUG__SHIFT 0x7 +#define HW_DEBUG_IND__HW_08_DEBUG_MASK 0x100 +#define HW_DEBUG_IND__HW_08_DEBUG__SHIFT 0x8 +#define HW_DEBUG_IND__HW_09_DEBUG_MASK 0x200 +#define HW_DEBUG_IND__HW_09_DEBUG__SHIFT 0x9 +#define HW_DEBUG_IND__HW_10_DEBUG_MASK 0x400 +#define HW_DEBUG_IND__HW_10_DEBUG__SHIFT 0xa +#define HW_DEBUG_IND__HW_11_DEBUG_MASK 0x800 +#define HW_DEBUG_IND__HW_11_DEBUG__SHIFT 0xb +#define HW_DEBUG_IND__HW_12_DEBUG_MASK 0x1000 +#define HW_DEBUG_IND__HW_12_DEBUG__SHIFT 0xc +#define HW_DEBUG_IND__HW_13_DEBUG_MASK 0x2000 +#define HW_DEBUG_IND__HW_13_DEBUG__SHIFT 0xd +#define HW_DEBUG_IND__HW_14_DEBUG_MASK 0x4000 +#define HW_DEBUG_IND__HW_14_DEBUG__SHIFT 0xe +#define HW_DEBUG_IND__HW_15_DEBUG_MASK 0x8000 +#define HW_DEBUG_IND__HW_15_DEBUG__SHIFT 0xf +#define HW_DEBUG_IND__HW_16_DEBUG_MASK 0x10000 +#define HW_DEBUG_IND__HW_16_DEBUG__SHIFT 0x10 +#define HW_DEBUG_IND__HW_17_DEBUG_MASK 0x20000 +#define HW_DEBUG_IND__HW_17_DEBUG__SHIFT 0x11 +#define HW_DEBUG_IND__HW_18_DEBUG_MASK 0x40000 +#define HW_DEBUG_IND__HW_18_DEBUG__SHIFT 0x12 +#define HW_DEBUG_IND__HW_19_DEBUG_MASK 0x80000 +#define HW_DEBUG_IND__HW_19_DEBUG__SHIFT 0x13 +#define HW_DEBUG_IND__HW_20_DEBUG_MASK 0x100000 +#define HW_DEBUG_IND__HW_20_DEBUG__SHIFT 0x14 +#define HW_DEBUG_IND__HW_21_DEBUG_MASK 0x200000 +#define HW_DEBUG_IND__HW_21_DEBUG__SHIFT 0x15 +#define HW_DEBUG_IND__HW_22_DEBUG_MASK 0x400000 +#define HW_DEBUG_IND__HW_22_DEBUG__SHIFT 0x16 +#define HW_DEBUG_IND__HW_23_DEBUG_MASK 0x800000 +#define HW_DEBUG_IND__HW_23_DEBUG__SHIFT 0x17 +#define HW_DEBUG_IND__HW_24_DEBUG_MASK 0x1000000 +#define HW_DEBUG_IND__HW_24_DEBUG__SHIFT 0x18 +#define HW_DEBUG_IND__HW_25_DEBUG_MASK 0x2000000 +#define HW_DEBUG_IND__HW_25_DEBUG__SHIFT 0x19 +#define HW_DEBUG_IND__HW_26_DEBUG_MASK 0x4000000 +#define HW_DEBUG_IND__HW_26_DEBUG__SHIFT 0x1a +#define HW_DEBUG_IND__HW_27_DEBUG_MASK 0x8000000 +#define HW_DEBUG_IND__HW_27_DEBUG__SHIFT 0x1b +#define HW_DEBUG_IND__HW_28_DEBUG_MASK 0x10000000 +#define HW_DEBUG_IND__HW_28_DEBUG__SHIFT 0x1c +#define HW_DEBUG_IND__HW_29_DEBUG_MASK 0x20000000 +#define HW_DEBUG_IND__HW_29_DEBUG__SHIFT 0x1d +#define HW_DEBUG_IND__HW_30_DEBUG_MASK 0x40000000 +#define HW_DEBUG_IND__HW_30_DEBUG__SHIFT 0x1e +#define HW_DEBUG_IND__HW_31_DEBUG_MASK 0x80000000 +#define HW_DEBUG_IND__HW_31_DEBUG__SHIFT 0x1f +#define MASTER_CREDIT_CNTL_IND__BIF_MC_RDRET_CREDIT_MASK 0x7f +#define MASTER_CREDIT_CNTL_IND__BIF_MC_RDRET_CREDIT__SHIFT 0x0 +#define MASTER_CREDIT_CNTL_IND__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000 +#define MASTER_CREDIT_CNTL_IND__BIF_AZ_RDRET_CREDIT__SHIFT 0x10 +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_SRBM_REQ_CREDIT_MASK 0x1f +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_SRBM_REQ_CREDIT__SHIFT 0x0 +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_VGA_REQ_CREDIT_MASK 0x1e0 +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_VGA_REQ_CREDIT__SHIFT 0x5 +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_HDP_REQ_CREDIT_MASK 0x7c00 +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_HDP_REQ_CREDIT__SHIFT 0xa +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_ROM_REQ_CREDIT_MASK 0x8000 +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_ROM_REQ_CREDIT__SHIFT 0xf +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_AZ_REQ_CREDIT_MASK 0x100000 +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_AZ_REQ_CREDIT__SHIFT 0x14 +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000 +#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_XDMA_REQ_CREDIT__SHIFT 0x19 +#define BX_RESET_CNTL_IND__LINK_TRAIN_EN_MASK 0x1 +#define BX_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT 0x0 +#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE_MASK 0x1 +#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN_MASK 0x2 +#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN__SHIFT 0x1 +#define INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN_MASK 0x8 +#define INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR_MASK 0xf0 +#define INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define INTERRUPT_CNTL_IND__GEN_IH_INT_EN_MASK 0x100 +#define INTERRUPT_CNTL_IND__GEN_IH_INT_EN__SHIFT 0x8 +#define INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN_MASK 0x1e00 +#define INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN__SHIFT 0x9 +#define INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT_MASK 0x6000 +#define INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd +#define INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000 +#define INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR_MASK 0xffffffff +#define INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_DEBUG_CNTL_IND__DEBUG_EN_MASK 0x1 +#define BIF_DEBUG_CNTL_IND__DEBUG_EN__SHIFT 0x0 +#define BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN_MASK 0x2 +#define BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN__SHIFT 0x1 +#define BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN_MASK 0x4 +#define BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN__SHIFT 0x2 +#define BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL_MASK 0x8 +#define BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL__SHIFT 0x3 +#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1_MASK 0x10 +#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1__SHIFT 0x4 +#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2_MASK 0x20 +#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2__SHIFT 0x5 +#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN_MASK 0x40 +#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN__SHIFT 0x6 +#define BIF_DEBUG_CNTL_IND__DEBUG_SWAP_MASK 0x80 +#define BIF_DEBUG_CNTL_IND__DEBUG_SWAP__SHIFT 0x7 +#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1_MASK 0x1f00 +#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1__SHIFT 0x8 +#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2_MASK 0x1f0000 +#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2__SHIFT 0x10 +#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP_MASK 0x1000000 +#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP__SHIFT 0x18 +#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL_MASK 0xc0000000 +#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL__SHIFT 0x1e +#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1_MASK 0x3f +#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1__SHIFT 0x0 +#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2_MASK 0x3f00 +#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2__SHIFT 0x8 +#define BIF_DEBUG_OUT_IND__DEBUG_OUTPUT_MASK 0x1ffff +#define BIF_DEBUG_OUT_IND__DEBUG_OUTPUT__SHIFT 0x0 +#define HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR_MASK 0x1 +#define HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR_MASK 0x1 +#define HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_A_MASK 0x1 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_A__SHIFT 0x0 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SEL_MASK 0x2 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SEL__SHIFT 0x1 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_MODE_MASK 0x4 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_MODE__SHIFT 0x2 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SPARE_MASK 0x18 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN0_MASK 0x20 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN0__SHIFT 0x5 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN1_MASK 0x40 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN1__SHIFT 0x6 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN2_MASK 0x80 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN2__SHIFT 0x7 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN3_MASK 0x100 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN3__SHIFT 0x8 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SLEWN_MASK 0x200 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_WAKE_MASK 0x400 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_WAKE__SHIFT 0xa +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SCHMEN_MASK 0x800 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_CNTL_EN_MASK 0x1000 +#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_A_MASK 0x1 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_A__SHIFT 0x0 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SEL_MASK 0x2 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SEL__SHIFT 0x1 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_MODE_MASK 0x4 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_MODE__SHIFT 0x2 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SPARE_MASK 0x18 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SPARE__SHIFT 0x3 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN0_MASK 0x20 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN0__SHIFT 0x5 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN1_MASK 0x40 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN1__SHIFT 0x6 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN2_MASK 0x80 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN2__SHIFT 0x7 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN3_MASK 0x100 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN3__SHIFT 0x8 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SLEWN_MASK 0x200 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SLEWN__SHIFT 0x9 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_WAKE_MASK 0x400 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_WAKE__SHIFT 0xa +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SCHMEN_MASK 0x800 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SCHMEN__SHIFT 0xb +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_CNTL_EN_MASK 0x1000 +#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_CNTL_EN__SHIFT 0xc +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_A_MASK 0x1 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_A__SHIFT 0x0 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SEL_MASK 0x2 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SEL__SHIFT 0x1 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_MODE_MASK 0x4 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_MODE__SHIFT 0x2 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SPARE_MASK 0x18 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SPARE__SHIFT 0x3 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN0_MASK 0x20 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN0__SHIFT 0x5 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN1_MASK 0x40 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN1__SHIFT 0x6 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN2_MASK 0x80 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN2__SHIFT 0x7 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN3_MASK 0x100 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN3__SHIFT 0x8 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SLEWN_MASK 0x200 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SLEWN__SHIFT 0x9 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_WAKE_MASK 0x400 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_WAKE__SHIFT 0xa +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SCHMEN_MASK 0x800 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SCHMEN__SHIFT 0xb +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_CNTL_EN_MASK 0x1000 +#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_CNTL_EN__SHIFT 0xc +#define BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff +#define BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define BIF_XDMA_LO_IND__BIF_XDMA_APER_EN_MASK 0x80000000 +#define BIF_XDMA_LO_IND__BIF_XDMA_APER_EN__SHIFT 0x1f +#define BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff +#define BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS_MASK 0x1 +#define BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS_MASK 0x2 +#define BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS_MASK 0x4 +#define BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS_MASK 0x8 +#define BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10 +#define BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 +#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20 +#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 +#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40 +#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 +#define BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80 +#define BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7 +#define BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100 +#define BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8 +#define BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200 +#define BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 +#define BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400 +#define BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa +#define BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800 +#define BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb +#define BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000 +#define BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_DOORBELL_CNTL_IND__SELF_RING_DIS_MASK 0x1 +#define BIF_DOORBELL_CNTL_IND__SELF_RING_DIS__SHIFT 0x0 +#define BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS_MASK 0x2 +#define BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN_MASK 0x4 +#define BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8 +#define BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN_MASK 0x10 +#define BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS_MASK 0x20 +#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5 +#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000 +#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_SLVARB_MODE_IND__SLVARB_MODE_MASK 0x3 +#define BIF_SLVARB_MODE_IND__SLVARB_MODE__SHIFT 0x0 +#define BIF_FB_EN_IND__FB_READ_EN_MASK 0x1 +#define BIF_FB_EN_IND__FB_READ_EN__SHIFT 0x0 +#define BIF_FB_EN_IND__FB_WRITE_EN_MASK 0x2 +#define BIF_FB_EN_IND__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BUSNUM_CNTL1_IND__ID_MASK_MASK 0xff +#define BIF_BUSNUM_CNTL1_IND__ID_MASK__SHIFT 0x0 +#define BIF_BUSNUM_LIST0_IND__ID0_MASK 0xff +#define BIF_BUSNUM_LIST0_IND__ID0__SHIFT 0x0 +#define BIF_BUSNUM_LIST0_IND__ID1_MASK 0xff00 +#define BIF_BUSNUM_LIST0_IND__ID1__SHIFT 0x8 +#define BIF_BUSNUM_LIST0_IND__ID2_MASK 0xff0000 +#define BIF_BUSNUM_LIST0_IND__ID2__SHIFT 0x10 +#define BIF_BUSNUM_LIST0_IND__ID3_MASK 0xff000000 +#define BIF_BUSNUM_LIST0_IND__ID3__SHIFT 0x18 +#define BIF_BUSNUM_LIST1_IND__ID4_MASK 0xff +#define BIF_BUSNUM_LIST1_IND__ID4__SHIFT 0x0 +#define BIF_BUSNUM_LIST1_IND__ID5_MASK 0xff00 +#define BIF_BUSNUM_LIST1_IND__ID5__SHIFT 0x8 +#define BIF_BUSNUM_LIST1_IND__ID6_MASK 0xff0000 +#define BIF_BUSNUM_LIST1_IND__ID6__SHIFT 0x10 +#define BIF_BUSNUM_LIST1_IND__ID7_MASK 0xff000000 +#define BIF_BUSNUM_LIST1_IND__ID7__SHIFT 0x18 +#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL_MASK 0xff +#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL__SHIFT 0x0 +#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN_MASK 0x100 +#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN__SHIFT 0x8 +#define BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL_MASK 0x10000 +#define BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL__SHIFT 0x10 +#define BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000 +#define BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT_MASK 0x3f +#define BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT__SHIFT 0x0 +#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN_MASK 0x1 +#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN__SHIFT 0x0 +#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0_MASK 0x2 +#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0__SHIFT 0x1 +#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1_MASK 0x4 +#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1__SHIFT 0x2 +#define BIF_PERFMON_CNTL_IND__PERF_SEL0_MASK 0x1f00 +#define BIF_PERFMON_CNTL_IND__PERF_SEL0__SHIFT 0x8 +#define BIF_PERFMON_CNTL_IND__PERF_SEL1_MASK 0x3e000 +#define BIF_PERFMON_CNTL_IND__PERF_SEL1__SHIFT 0xd +#define BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT_MASK 0xffffffff +#define BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT__SHIFT 0x0 +#define BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT_MASK 0xffffffff +#define BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT__SHIFT 0x0 +#define SLAVE_HANG_PROTECTION_CNTL_IND__HANG_PROTECTION_TIMER_SEL_MASK 0xe +#define SLAVE_HANG_PROTECTION_CNTL_IND__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1 +#define GPU_HDP_FLUSH_REQ_IND__CP0_MASK 0x1 +#define GPU_HDP_FLUSH_REQ_IND__CP0__SHIFT 0x0 +#define GPU_HDP_FLUSH_REQ_IND__CP1_MASK 0x2 +#define GPU_HDP_FLUSH_REQ_IND__CP1__SHIFT 0x1 +#define GPU_HDP_FLUSH_REQ_IND__CP2_MASK 0x4 +#define GPU_HDP_FLUSH_REQ_IND__CP2__SHIFT 0x2 +#define GPU_HDP_FLUSH_REQ_IND__CP3_MASK 0x8 +#define GPU_HDP_FLUSH_REQ_IND__CP3__SHIFT 0x3 +#define GPU_HDP_FLUSH_REQ_IND__CP4_MASK 0x10 +#define GPU_HDP_FLUSH_REQ_IND__CP4__SHIFT 0x4 +#define GPU_HDP_FLUSH_REQ_IND__CP5_MASK 0x20 +#define GPU_HDP_FLUSH_REQ_IND__CP5__SHIFT 0x5 +#define GPU_HDP_FLUSH_REQ_IND__CP6_MASK 0x40 +#define GPU_HDP_FLUSH_REQ_IND__CP6__SHIFT 0x6 +#define GPU_HDP_FLUSH_REQ_IND__CP7_MASK 0x80 +#define GPU_HDP_FLUSH_REQ_IND__CP7__SHIFT 0x7 +#define GPU_HDP_FLUSH_REQ_IND__CP8_MASK 0x100 +#define GPU_HDP_FLUSH_REQ_IND__CP8__SHIFT 0x8 +#define GPU_HDP_FLUSH_REQ_IND__CP9_MASK 0x200 +#define GPU_HDP_FLUSH_REQ_IND__CP9__SHIFT 0x9 +#define GPU_HDP_FLUSH_REQ_IND__SDMA0_MASK 0x400 +#define GPU_HDP_FLUSH_REQ_IND__SDMA0__SHIFT 0xa +#define GPU_HDP_FLUSH_REQ_IND__SDMA1_MASK 0x800 +#define GPU_HDP_FLUSH_REQ_IND__SDMA1__SHIFT 0xb +#define GPU_HDP_FLUSH_DONE_IND__CP0_MASK 0x1 +#define GPU_HDP_FLUSH_DONE_IND__CP0__SHIFT 0x0 +#define GPU_HDP_FLUSH_DONE_IND__CP1_MASK 0x2 +#define GPU_HDP_FLUSH_DONE_IND__CP1__SHIFT 0x1 +#define GPU_HDP_FLUSH_DONE_IND__CP2_MASK 0x4 +#define GPU_HDP_FLUSH_DONE_IND__CP2__SHIFT 0x2 +#define GPU_HDP_FLUSH_DONE_IND__CP3_MASK 0x8 +#define GPU_HDP_FLUSH_DONE_IND__CP3__SHIFT 0x3 +#define GPU_HDP_FLUSH_DONE_IND__CP4_MASK 0x10 +#define GPU_HDP_FLUSH_DONE_IND__CP4__SHIFT 0x4 +#define GPU_HDP_FLUSH_DONE_IND__CP5_MASK 0x20 +#define GPU_HDP_FLUSH_DONE_IND__CP5__SHIFT 0x5 +#define GPU_HDP_FLUSH_DONE_IND__CP6_MASK 0x40 +#define GPU_HDP_FLUSH_DONE_IND__CP6__SHIFT 0x6 +#define GPU_HDP_FLUSH_DONE_IND__CP7_MASK 0x80 +#define GPU_HDP_FLUSH_DONE_IND__CP7__SHIFT 0x7 +#define GPU_HDP_FLUSH_DONE_IND__CP8_MASK 0x100 +#define GPU_HDP_FLUSH_DONE_IND__CP8__SHIFT 0x8 +#define GPU_HDP_FLUSH_DONE_IND__CP9_MASK 0x200 +#define GPU_HDP_FLUSH_DONE_IND__CP9__SHIFT 0x9 +#define GPU_HDP_FLUSH_DONE_IND__SDMA0_MASK 0x400 +#define GPU_HDP_FLUSH_DONE_IND__SDMA0__SHIFT 0xa +#define GPU_HDP_FLUSH_DONE_IND__SDMA1_MASK 0x800 +#define GPU_HDP_FLUSH_DONE_IND__SDMA1__SHIFT 0xb +#define SLAVE_HANG_ERROR_IND__SRBM_HANG_ERROR_MASK 0x1 +#define SLAVE_HANG_ERROR_IND__SRBM_HANG_ERROR__SHIFT 0x0 +#define SLAVE_HANG_ERROR_IND__HDP_HANG_ERROR_MASK 0x2 +#define SLAVE_HANG_ERROR_IND__HDP_HANG_ERROR__SHIFT 0x1 +#define SLAVE_HANG_ERROR_IND__VGA_HANG_ERROR_MASK 0x4 +#define SLAVE_HANG_ERROR_IND__VGA_HANG_ERROR__SHIFT 0x2 +#define SLAVE_HANG_ERROR_IND__ROM_HANG_ERROR_MASK 0x8 +#define SLAVE_HANG_ERROR_IND__ROM_HANG_ERROR__SHIFT 0x3 +#define SLAVE_HANG_ERROR_IND__AUDIO_HANG_ERROR_MASK 0x10 +#define SLAVE_HANG_ERROR_IND__AUDIO_HANG_ERROR__SHIFT 0x4 +#define SLAVE_HANG_ERROR_IND__CEC_HANG_ERROR_MASK 0x20 +#define SLAVE_HANG_ERROR_IND__CEC_HANG_ERROR__SHIFT 0x5 +#define SLAVE_HANG_ERROR_IND__XDMA_HANG_ERROR_MASK 0x80 +#define SLAVE_HANG_ERROR_IND__XDMA_HANG_ERROR__SHIFT 0x7 +#define SLAVE_HANG_ERROR_IND__DOORBELL_HANG_ERROR_MASK 0x100 +#define SLAVE_HANG_ERROR_IND__DOORBELL_HANG_ERROR__SHIFT 0x8 +#define SLAVE_HANG_ERROR_IND__GARLIC_HANG_ERROR_MASK 0x200 +#define SLAVE_HANG_ERROR_IND__GARLIC_HANG_ERROR__SHIFT 0x9 +#define CAPTURE_HOST_BUSNUM_IND__CHECK_EN_MASK 0x1 +#define CAPTURE_HOST_BUSNUM_IND__CHECK_EN__SHIFT 0x0 +#define HOST_BUSNUM_IND__HOST_ID_MASK 0xffff +#define HOST_BUSNUM_IND__HOST_ID__SHIFT 0x0 +#define PEER_REG_RANGE0_IND__START_ADDR_MASK 0xffff +#define PEER_REG_RANGE0_IND__START_ADDR__SHIFT 0x0 +#define PEER_REG_RANGE0_IND__END_ADDR_MASK 0xffff0000 +#define PEER_REG_RANGE0_IND__END_ADDR__SHIFT 0x10 +#define PEER_REG_RANGE1_IND__START_ADDR_MASK 0xffff +#define PEER_REG_RANGE1_IND__START_ADDR__SHIFT 0x0 +#define PEER_REG_RANGE1_IND__END_ADDR_MASK 0xffff0000 +#define PEER_REG_RANGE1_IND__END_ADDR__SHIFT 0x10 +#define PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI_MASK 0xfffff +#define PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO_MASK 0xfffff +#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN_MASK 0x80000000 +#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN__SHIFT 0x1f +#define PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI_MASK 0xfffff +#define PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO_MASK 0xfffff +#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN_MASK 0x80000000 +#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN__SHIFT 0x1f +#define PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI_MASK 0xfffff +#define PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO_MASK 0xfffff +#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN_MASK 0x80000000 +#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN__SHIFT 0x1f +#define PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI_MASK 0xfffff +#define PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO_MASK 0xfffff +#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN_MASK 0x80000000 +#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN__SHIFT 0x1f +#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1 +#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0 +#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD_MASK 0x1e +#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD__SHIFT 0x1 +#define SMBUS_BACO_DUMMY_IND__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff +#define SMBUS_BACO_DUMMY_IND__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0_MASK 0xff +#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1_MASK 0xff00 +#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1__SHIFT 0x8 +#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2_MASK 0xff0000 +#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2__SHIFT 0x10 +#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3_MASK 0xff000000 +#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3__SHIFT 0x18 +#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4_MASK 0xff +#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4__SHIFT 0x0 +#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5_MASK 0xff00 +#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5__SHIFT 0x8 +#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6_MASK 0xff0000 +#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6__SHIFT 0x10 +#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7_MASK 0xff000000 +#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7__SHIFT 0x18 +#define BACO_CNTL_IND__BACO_EN_MASK 0x1 +#define BACO_CNTL_IND__BACO_EN__SHIFT 0x0 +#define BACO_CNTL_IND__BACO_BCLK_OFF_MASK 0x2 +#define BACO_CNTL_IND__BACO_BCLK_OFF__SHIFT 0x1 +#define BACO_CNTL_IND__BACO_ISO_DIS_MASK 0x4 +#define BACO_CNTL_IND__BACO_ISO_DIS__SHIFT 0x2 +#define BACO_CNTL_IND__BACO_POWER_OFF_MASK 0x8 +#define BACO_CNTL_IND__BACO_POWER_OFF__SHIFT 0x3 +#define BACO_CNTL_IND__BACO_RESET_EN_MASK 0x10 +#define BACO_CNTL_IND__BACO_RESET_EN__SHIFT 0x4 +#define BACO_CNTL_IND__BACO_HANG_PROTECTION_EN_MASK 0x20 +#define BACO_CNTL_IND__BACO_HANG_PROTECTION_EN__SHIFT 0x5 +#define BACO_CNTL_IND__BACO_MODE_MASK 0x40 +#define BACO_CNTL_IND__BACO_MODE__SHIFT 0x6 +#define BACO_CNTL_IND__BACO_ANA_ISO_DIS_MASK 0x80 +#define BACO_CNTL_IND__BACO_ANA_ISO_DIS__SHIFT 0x7 +#define BACO_CNTL_IND__RCU_BIF_CONFIG_DONE_MASK 0x100 +#define BACO_CNTL_IND__RCU_BIF_CONFIG_DONE__SHIFT 0x8 +#define BACO_CNTL_IND__PWRGOOD_BF_MASK 0x200 +#define BACO_CNTL_IND__PWRGOOD_BF__SHIFT 0x9 +#define BACO_CNTL_IND__PWRGOOD_GPIO_MASK 0x400 +#define BACO_CNTL_IND__PWRGOOD_GPIO__SHIFT 0xa +#define BACO_CNTL_IND__PWRGOOD_MEM_MASK 0x800 +#define BACO_CNTL_IND__PWRGOOD_MEM__SHIFT 0xb +#define BACO_CNTL_IND__PWRGOOD_DVO_MASK 0x1000 +#define BACO_CNTL_IND__PWRGOOD_DVO__SHIFT 0xc +#define BACO_CNTL_IND__PWRGOOD_IDSC_MASK 0x2000 +#define BACO_CNTL_IND__PWRGOOD_IDSC__SHIFT 0xd +#define BACO_CNTL_IND__BACO_POWER_OFF_DRAM_MASK 0x10000 +#define BACO_CNTL_IND__BACO_POWER_OFF_DRAM__SHIFT 0x10 +#define BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000 +#define BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11 +#define BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK_MASK 0x1 +#define BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK__SHIFT 0x0 +#define BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK_MASK 0x2 +#define BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1 +#define MEM_TYPE_CNTL_IND__BF_MEM_PHY_G5_G3_MASK 0x1 +#define MEM_TYPE_CNTL_IND__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG_MASK 0x1 +#define BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0 +#define BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG_MASK 0x1 +#define BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG__SHIFT 0x0 +#define BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS_MASK 0x1 +#define BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS_MASK 0x2 +#define BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL_MASK 0xc +#define BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2 +#define SMU_BIF_VDDGFX_PWR_STATUS_IND__VDDGFX_GFX_PWR_OFF_MASK 0x1 +#define SMU_BIF_VDDGFX_PWR_STATUS_IND__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 +#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc +#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 +#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000 +#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e +#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000 +#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f +#define BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc +#define BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN_MASK 0x1 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN_MASK 0x2 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN_MASK 0x10 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN_MASK 0x20 +#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 +#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN_MASK 0x80000000 +#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN__SHIFT 0x1f +#define BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 +#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN_MASK 0x80000000 +#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN__SHIFT 0x1f +#define BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER_MASK 0xffc +#define BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 +#define BIF_SMU_INDEX_IND__BIF_SMU_INDEX_MASK 0x7fffc +#define BIF_SMU_INDEX_IND__BIF_SMU_INDEX__SHIFT 0x2 +#define BIF_SMU_DATA_IND__BIF_SMU_DATA_MASK 0x7fffc +#define BIF_SMU_DATA_IND__BIF_SMU_DATA__SHIFT 0x2 +#define IMPCTL_RESET_IND__IMP_SW_RESET_MASK 0x1 +#define IMPCTL_RESET_IND__IMP_SW_RESET__SHIFT 0x0 +#define GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR_MASK 0x1 +#define GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR__SHIFT 0x0 +#define GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR_MASK 0x2 +#define GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR__SHIFT 0x1 +#define GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR_MASK 0x4 +#define GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR__SHIFT 0x2 +#define GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR_MASK 0x8 +#define GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR__SHIFT 0x3 +#define GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR_MASK 0x10 +#define GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR__SHIFT 0x4 +#define GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR_MASK 0x20 +#define GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR__SHIFT 0x5 +#define GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND_MASK 0x40 +#define GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND__SHIFT 0x6 +#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND_MASK 0x80 +#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND__SHIFT 0x7 +#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR_MASK 0x100 +#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR__SHIFT 0x8 +#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR_MASK 0x200 +#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR__SHIFT 0x9 +#define GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR_MASK 0x400 +#define GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR__SHIFT 0xa +#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2_MASK 0x800 +#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2__SHIFT 0xb +#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR_MASK 0x1000 +#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR__SHIFT 0xc +#define GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL_MASK 0x2000 +#define GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL__SHIFT 0xd +#define GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL_MASK 0x4000 +#define GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL__SHIFT 0xe +#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND_MASK 0x8000 +#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND__SHIFT 0xf +#define GARLIC_FLUSH_CNTL_IND__DISPLAY_MASK 0x10000 +#define GARLIC_FLUSH_CNTL_IND__DISPLAY__SHIFT 0x10 +#define GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR_MASK 0x20000 +#define GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR__SHIFT 0x11 +#define GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR_MASK 0x40000 +#define GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR__SHIFT 0x12 +#define GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE_MASK 0x40000000 +#define GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE__SHIFT 0x1e +#define GARLIC_FLUSH_CNTL_IND__DISABLE_ALL_MASK 0x80000000 +#define GARLIC_FLUSH_CNTL_IND__DISABLE_ALL__SHIFT 0x1f +#define GARLIC_FLUSH_REQ_IND__FLUSH_REQ_MASK 0x1 +#define GARLIC_FLUSH_REQ_IND__FLUSH_REQ__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_REQ_IND__CP0_MASK 0x1 +#define GPU_GARLIC_FLUSH_REQ_IND__CP0__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_REQ_IND__CP1_MASK 0x2 +#define GPU_GARLIC_FLUSH_REQ_IND__CP1__SHIFT 0x1 +#define GPU_GARLIC_FLUSH_REQ_IND__CP2_MASK 0x4 +#define GPU_GARLIC_FLUSH_REQ_IND__CP2__SHIFT 0x2 +#define GPU_GARLIC_FLUSH_REQ_IND__CP3_MASK 0x8 +#define GPU_GARLIC_FLUSH_REQ_IND__CP3__SHIFT 0x3 +#define GPU_GARLIC_FLUSH_REQ_IND__CP4_MASK 0x10 +#define GPU_GARLIC_FLUSH_REQ_IND__CP4__SHIFT 0x4 +#define GPU_GARLIC_FLUSH_REQ_IND__CP5_MASK 0x20 +#define GPU_GARLIC_FLUSH_REQ_IND__CP5__SHIFT 0x5 +#define GPU_GARLIC_FLUSH_REQ_IND__CP6_MASK 0x40 +#define GPU_GARLIC_FLUSH_REQ_IND__CP6__SHIFT 0x6 +#define GPU_GARLIC_FLUSH_REQ_IND__CP7_MASK 0x80 +#define GPU_GARLIC_FLUSH_REQ_IND__CP7__SHIFT 0x7 +#define GPU_GARLIC_FLUSH_REQ_IND__CP8_MASK 0x100 +#define GPU_GARLIC_FLUSH_REQ_IND__CP8__SHIFT 0x8 +#define GPU_GARLIC_FLUSH_REQ_IND__CP9_MASK 0x200 +#define GPU_GARLIC_FLUSH_REQ_IND__CP9__SHIFT 0x9 +#define GPU_GARLIC_FLUSH_REQ_IND__SDMA0_MASK 0x400 +#define GPU_GARLIC_FLUSH_REQ_IND__SDMA0__SHIFT 0xa +#define GPU_GARLIC_FLUSH_REQ_IND__SDMA1_MASK 0x800 +#define GPU_GARLIC_FLUSH_REQ_IND__SDMA1__SHIFT 0xb +#define GPU_GARLIC_FLUSH_REQ_IND__SDMA2_MASK 0x1000 +#define GPU_GARLIC_FLUSH_REQ_IND__SDMA2__SHIFT 0xc +#define GPU_GARLIC_FLUSH_REQ_IND__SDMA3_MASK 0x2000 +#define GPU_GARLIC_FLUSH_REQ_IND__SDMA3__SHIFT 0xd +#define GPU_GARLIC_FLUSH_DONE_IND__CP0_MASK 0x1 +#define GPU_GARLIC_FLUSH_DONE_IND__CP0__SHIFT 0x0 +#define GPU_GARLIC_FLUSH_DONE_IND__CP1_MASK 0x2 +#define GPU_GARLIC_FLUSH_DONE_IND__CP1__SHIFT 0x1 +#define GPU_GARLIC_FLUSH_DONE_IND__CP2_MASK 0x4 +#define GPU_GARLIC_FLUSH_DONE_IND__CP2__SHIFT 0x2 +#define GPU_GARLIC_FLUSH_DONE_IND__CP3_MASK 0x8 +#define GPU_GARLIC_FLUSH_DONE_IND__CP3__SHIFT 0x3 +#define GPU_GARLIC_FLUSH_DONE_IND__CP4_MASK 0x10 +#define GPU_GARLIC_FLUSH_DONE_IND__CP4__SHIFT 0x4 +#define GPU_GARLIC_FLUSH_DONE_IND__CP5_MASK 0x20 +#define GPU_GARLIC_FLUSH_DONE_IND__CP5__SHIFT 0x5 +#define GPU_GARLIC_FLUSH_DONE_IND__CP6_MASK 0x40 +#define GPU_GARLIC_FLUSH_DONE_IND__CP6__SHIFT 0x6 +#define GPU_GARLIC_FLUSH_DONE_IND__CP7_MASK 0x80 +#define GPU_GARLIC_FLUSH_DONE_IND__CP7__SHIFT 0x7 +#define GPU_GARLIC_FLUSH_DONE_IND__CP8_MASK 0x100 +#define GPU_GARLIC_FLUSH_DONE_IND__CP8__SHIFT 0x8 +#define GPU_GARLIC_FLUSH_DONE_IND__CP9_MASK 0x200 +#define GPU_GARLIC_FLUSH_DONE_IND__CP9__SHIFT 0x9 +#define GPU_GARLIC_FLUSH_DONE_IND__SDMA0_MASK 0x400 +#define GPU_GARLIC_FLUSH_DONE_IND__SDMA0__SHIFT 0xa +#define GPU_GARLIC_FLUSH_DONE_IND__SDMA1_MASK 0x800 +#define GPU_GARLIC_FLUSH_DONE_IND__SDMA1__SHIFT 0xb +#define GPU_GARLIC_FLUSH_DONE_IND__SDMA2_MASK 0x1000 +#define GPU_GARLIC_FLUSH_DONE_IND__SDMA2__SHIFT 0xc +#define GPU_GARLIC_FLUSH_DONE_IND__SDMA3_MASK 0x2000 +#define GPU_GARLIC_FLUSH_DONE_IND__SDMA3__SHIFT 0xd +#define GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS__SHIFT 0x2 +#define GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS_MASK 0x7fffc +#define GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS__SHIFT 0x2 +#define REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS_MASK 0x7fffc +#define REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2 +#define REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS_MASK 0x7fffc +#define REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2 +#define BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0_MASK 0xffffffff +#define BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1_MASK 0xffffffff +#define BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2_MASK 0xffffffff +#define BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3_MASK 0xffffffff +#define BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4_MASK 0xffffffff +#define BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5_MASK 0xffffffff +#define BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6_MASK 0xffffffff +#define BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7_MASK 0xffffffff +#define BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8_MASK 0xffffffff +#define BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9_MASK 0xffffffff +#define BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10_MASK 0xffffffff +#define BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11_MASK 0xffffffff +#define BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12_MASK 0xffffffff +#define BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13_MASK 0xffffffff +#define BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14_MASK 0xffffffff +#define BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15_MASK 0xffffffff +#define BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_RB_CNTL_IND__RB_ENABLE_MASK 0x1 +#define BIF_RB_CNTL_IND__RB_ENABLE__SHIFT 0x0 +#define BIF_RB_CNTL_IND__RB_SIZE_MASK 0x3e +#define BIF_RB_CNTL_IND__RB_SIZE__SHIFT 0x1 +#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE_MASK 0x100 +#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER_MASK 0x3e00 +#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_RB_CNTL_IND__BIF_RB_TRAN_MASK 0x20000 +#define BIF_RB_CNTL_IND__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 +#define BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_RB_BASE_IND__ADDR_MASK 0xffffffff +#define BIF_RB_BASE_IND__ADDR__SHIFT 0x0 +#define BIF_RB_RPTR_IND__OFFSET_MASK 0x3fffc +#define BIF_RB_RPTR_IND__OFFSET__SHIFT 0x2 +#define BIF_RB_WPTR_IND__BIF_RB_OVERFLOW_MASK 0x1 +#define BIF_RB_WPTR_IND__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_RB_WPTR_IND__OFFSET_MASK 0x3fffc +#define BIF_RB_WPTR_IND__OFFSET__SHIFT 0x2 +#define BIF_RB_WPTR_ADDR_HI_IND__ADDR_MASK 0xff +#define BIF_RB_WPTR_ADDR_HI_IND__ADDR__SHIFT 0x0 +#define BIF_RB_WPTR_ADDR_LO_IND__ADDR_MASK 0xfffffffc +#define BIF_RB_WPTR_ADDR_LO_IND__ADDR__SHIFT 0x2 +#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR_MASK 0xffffffff +#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR__SHIFT 0x0 +#define NB_GBIF_DATA__NB_GBIF_DATA_MASK 0xffffffff +#define NB_GBIF_DATA__NB_GBIF_DATA__SHIFT 0x0 +#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff +#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff +#define PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff +#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0 +#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff +#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0 +#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff +#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff +#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff +#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff +#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 +#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1 +#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe +#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 +#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80 +#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100 +#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200 +#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00 +#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000 +#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf +#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000 +#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000 +#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000 +#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000 +#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 +#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x100000 +#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x14 +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000 +#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000 +#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000 +#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 +#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000 +#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 +#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000 +#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000 +#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf +#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000 +#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000 +#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000 +#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000 +#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff +#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 +#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100 +#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 +#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000 +#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 +#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1 +#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2 +#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4 +#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8 +#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10 +#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40 +#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80 +#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7 +#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100 +#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8 +#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1 +#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2 +#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4 +#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8 +#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10 +#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40 +#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80 +#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7 +#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100 +#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8 +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1 +#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e +#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 +#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0 +#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 +#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800 +#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb +#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 +#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 +#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000 +#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 +#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000 +#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 +#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000 +#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000 +#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 +#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000 +#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 +#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000 +#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000 +#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20 +#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000 +#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000 +#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000 +#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4 +#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8 +#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10 +#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0 +#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100 +#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200 +#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000 +#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc +#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000 +#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd +#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40 +#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80 +#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000 +#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc +#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f +#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 +#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00 +#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 +#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000 +#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 +#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000 +#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 +#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f +#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 +#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00 +#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 +#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000 +#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 +#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000 +#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 +#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f +#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 +#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00 +#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 +#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000 +#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 +#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000 +#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 +#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f +#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 +#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00 +#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 +#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000 +#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 +#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000 +#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 +#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f +#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 +#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00 +#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 +#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000 +#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 +#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000 +#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 +#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f +#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 +#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00 +#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 +#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000 +#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 +#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000 +#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1 +#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2 +#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c +#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0 +#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff +#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000 +#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1 +#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4 +#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8 +#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10 +#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20 +#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40 +#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff +#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff +#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff +#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff +#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff +#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff +#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff +#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff +#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff +#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 +#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff +#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4 +#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1 +#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 +#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2 +#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 +#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4 +#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2 +#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8 +#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3 +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10 +#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20 +#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40 +#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80 +#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100 +#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 +#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000 +#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000 +#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000 +#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe +#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000 +#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff +#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000 +#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff +#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff +#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000 +#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00 +#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 +#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1 +#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1 +#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4 +#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2 +#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8 +#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000 +#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc +#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000 +#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10 +#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000 +#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11 +#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000 +#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12 +#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000 +#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000 +#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4 +#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000 +#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000 +#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff +#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00 +#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000 +#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff +#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff +#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 +#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1 +#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2 +#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4 +#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 +#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8 +#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10 +#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 +#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20 +#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40 +#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80 +#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100 +#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200 +#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400 +#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800 +#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000 +#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc +#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000 +#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd +#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000 +#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe +#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000 +#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000 +#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000 +#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x1 +#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x0 +#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2 +#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4 +#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2 +#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8 +#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3 +#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10 +#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4 +#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20 +#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5 +#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40 +#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6 +#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80 +#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7 +#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100 +#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8 +#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200 +#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9 +#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400 +#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa +#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800 +#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb +#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000 +#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc +#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000 +#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd +#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000 +#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe +#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000 +#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000 +#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x1 +#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x0 +#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2 +#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4 +#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2 +#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8 +#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3 +#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10 +#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4 +#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20 +#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5 +#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40 +#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6 +#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80 +#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7 +#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100 +#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8 +#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200 +#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9 +#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400 +#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa +#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800 +#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb +#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000 +#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc +#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000 +#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd +#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000 +#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe +#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000 +#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000 +#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_F7__RESERVED_MASK 0xffffffff +#define PCIE_STRAP_F7__RESERVED__SHIFT 0x0 +#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0xf +#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x0 +#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10 +#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 +#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00 +#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8 +#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000 +#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd +#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000 +#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe +#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000 +#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000 +#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000 +#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19 +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000 +#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000 +#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000 +#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000 +#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e +#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000 +#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2 +#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4 +#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8 +#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 +#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10 +#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1 +#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000 +#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f +#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 +#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80 +#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 +#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff +#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 +#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000 +#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff +#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 +#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000 +#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff +#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 +#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff +#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 +#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1 +#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 +#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x6 +#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x8 +#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x3 +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x10 +#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x4 +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x60 +#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x5 +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0xf80 +#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x7 +#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000 +#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000 +#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff +#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff +#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff +#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff +#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 +#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 +#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 +#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 +#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff +#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f +#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff +#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000 +#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000 +#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000 +#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define PCIE_FC_P__PD_CREDITS_MASK 0xff +#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc +#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000 +#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd +#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2 +#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1 +#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1 +#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0 +#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff +#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0 +#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000 +#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e +#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000 +#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst_MASK 0x1 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst__SHIFT 0x0 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst_MASK 0x2 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst__SHIFT 0x1 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst_MASK 0x4 +#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst__SHIFT 0x2 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst_MASK 0x1 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst__SHIFT 0x0 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst_MASK 0x2 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst__SHIFT 0x1 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x4 +#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x2 +#define BIF_PWDN_COMMAND__REG_FBU_pw_cmd_MASK 0x1 +#define BIF_PWDN_COMMAND__REG_FBU_pw_cmd__SHIFT 0x0 +#define BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd_MASK 0x2 +#define BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd__SHIFT 0x1 +#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x4 +#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x2 +#define BIF_PWDN_STATUS__FBU_REG_pw_status_MASK 0x1 +#define BIF_PWDN_STATUS__FBU_REG_pw_status__SHIFT 0x0 +#define BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status_MASK 0x2 +#define BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status__SHIFT 0x1 +#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x4 +#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x2 +#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer_MASK 0xff +#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer__SHIFT 0x0 +#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer_MASK 0xf00 +#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer__SHIFT 0x8 +#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer_MASK 0xff0000 +#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer__SHIFT 0x10 +#define BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout_MASK 0x1000000 +#define BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout__SHIFT 0x18 +#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer_MASK 0xff +#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer__SHIFT 0x0 +#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer_MASK 0xf00 +#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer__SHIFT 0x8 +#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer_MASK 0xff0000 +#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer__SHIFT 0x10 +#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout_MASK 0x1000000 +#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout__SHIFT 0x18 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000 +#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10 +#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000 +#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18 +#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1 +#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0 +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK 0x1 +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT 0x0 +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK 0xe +#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT 0x1 +#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK 0x10 +#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT 0x4 +#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK 0xe0 +#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT 0x5 +#define BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK_MASK 0x1 +#define BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0 +#define BIF_LNCNT_RESET_IND__RESET_LNCNT_EN_MASK 0x1 +#define BIF_LNCNT_RESET_IND__RESET_LNCNT_EN__SHIFT 0x0 +#define LNCNT_CONTROL_IND__LNCNT_ACC_MODE_MASK 0x1 +#define LNCNT_CONTROL_IND__LNCNT_ACC_MODE__SHIFT 0x0 +#define LNCNT_CONTROL_IND__LNCNT_REF_TIMEBASE_MASK 0x6 +#define LNCNT_CONTROL_IND__LNCNT_REF_TIMEBASE__SHIFT 0x1 +#define NEW_REFCLKB_TIMER_IND__REG_STOP_REFCLK_EN_MASK 0x1 +#define NEW_REFCLKB_TIMER_IND__REG_STOP_REFCLK_EN__SHIFT 0x0 +#define NEW_REFCLKB_TIMER_IND__STOP_REFCLK_TIMER_MASK 0x1ffffe +#define NEW_REFCLKB_TIMER_IND__STOP_REFCLK_TIMER__SHIFT 0x1 +#define NEW_REFCLKB_TIMER_IND__REFCLK_ON_MASK 0x200000 +#define NEW_REFCLKB_TIMER_IND__REFCLK_ON__SHIFT 0x15 +#define NEW_REFCLKB_TIMER_1_IND__PHY_PLL_PDWN_TIMER_MASK 0x3ff +#define NEW_REFCLKB_TIMER_1_IND__PHY_PLL_PDWN_TIMER__SHIFT 0x0 +#define NEW_REFCLKB_TIMER_1_IND__PLL0_PDNB_EN_MASK 0x400 +#define NEW_REFCLKB_TIMER_1_IND__PLL0_PDNB_EN__SHIFT 0xa +#define BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER_MASK 0x3ff +#define BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER__SHIFT 0x0 +#define BIF_RESET_EN_IND__SOFT_RST_MODE_MASK 0x2 +#define BIF_RESET_EN_IND__SOFT_RST_MODE__SHIFT 0x1 +#define BIF_RESET_EN_IND__PHY_RESET_EN_MASK 0x4 +#define BIF_RESET_EN_IND__PHY_RESET_EN__SHIFT 0x2 +#define BIF_RESET_EN_IND__COR_RESET_EN_MASK 0x8 +#define BIF_RESET_EN_IND__COR_RESET_EN__SHIFT 0x3 +#define BIF_RESET_EN_IND__REG_RESET_EN_MASK 0x10 +#define BIF_RESET_EN_IND__REG_RESET_EN__SHIFT 0x4 +#define BIF_RESET_EN_IND__STY_RESET_EN_MASK 0x20 +#define BIF_RESET_EN_IND__STY_RESET_EN__SHIFT 0x5 +#define BIF_RESET_EN_IND__CFG_RESET_EN_MASK 0x40 +#define BIF_RESET_EN_IND__CFG_RESET_EN__SHIFT 0x6 +#define BIF_RESET_EN_IND__DRV_RESET_EN_MASK 0x80 +#define BIF_RESET_EN_IND__DRV_RESET_EN__SHIFT 0x7 +#define BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN_MASK 0x100 +#define BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN__SHIFT 0x8 +#define BIF_RESET_EN_IND__HOT_RESET_EN_MASK 0x200 +#define BIF_RESET_EN_IND__HOT_RESET_EN__SHIFT 0x9 +#define BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN_MASK 0x400 +#define BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN__SHIFT 0xa +#define BIF_RESET_EN_IND__LINK_DOWN_RESET_EN_MASK 0x800 +#define BIF_RESET_EN_IND__LINK_DOWN_RESET_EN__SHIFT 0xb +#define BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH_MASK 0x3f000 +#define BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH__SHIFT 0xc +#define BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL_MASK 0xc0000 +#define BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL__SHIFT 0x12 +#define BIF_RESET_EN_IND__PIF_RSTB_EN_MASK 0x100000 +#define BIF_RESET_EN_IND__PIF_RSTB_EN__SHIFT 0x14 +#define BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN_MASK 0x200000 +#define BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN__SHIFT 0x15 +#define BIF_RESET_EN_IND__BIF_COR_RESET_EN_MASK 0x400000 +#define BIF_RESET_EN_IND__BIF_COR_RESET_EN__SHIFT 0x16 +#define BIF_RESET_EN_IND__FUNC0_FLR_EN_MASK 0x800000 +#define BIF_RESET_EN_IND__FUNC0_FLR_EN__SHIFT 0x17 +#define BIF_RESET_EN_IND__FUNC1_FLR_EN_MASK 0x1000000 +#define BIF_RESET_EN_IND__FUNC1_FLR_EN__SHIFT 0x18 +#define BIF_RESET_EN_IND__FUNC2_FLR_EN_MASK 0x2000000 +#define BIF_RESET_EN_IND__FUNC2_FLR_EN__SHIFT 0x19 +#define BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL_MASK 0xc000000 +#define BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a +#define BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL_MASK 0x30000000 +#define BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c +#define BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000 +#define BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e +#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER_MASK 0x7 +#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER__SHIFT 0x0 +#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER_MASK 0x38 +#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER__SHIFT 0x3 +#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER_MASK 0x3c0 +#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER__SHIFT 0x6 +#define BIF_BACO_MSIC_IND__BIF_XTALIN_SEL_MASK 0x1 +#define BIF_BACO_MSIC_IND__BIF_XTALIN_SEL__SHIFT 0x0 +#define BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL_MASK 0x6 +#define BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL__SHIFT 0x1 +#define BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS_MASK 0x10 +#define BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS__SHIFT 0x4 +#define BIF_RESET_CNTL_IND__STRAP_EN_MASK 0x1 +#define BIF_RESET_CNTL_IND__STRAP_EN__SHIFT 0x0 +#define BIF_RESET_CNTL_IND__RST_DONE_MASK 0x2 +#define BIF_RESET_CNTL_IND__RST_DONE__SHIFT 0x1 +#define BIF_RESET_CNTL_IND__LINK_TRAIN_EN_MASK 0x4 +#define BIF_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT 0x2 +#define BIF_RESET_CNTL_IND__STRAP_ALL_VALID_MASK 0x8 +#define BIF_RESET_CNTL_IND__STRAP_ALL_VALID__SHIFT 0x3 +#define BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST_MASK 0x100 +#define BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST__SHIFT 0x8 +#define BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS_MASK 0x200 +#define BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9 +#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode_MASK 0x1 +#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0 +#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode_MASK 0x2 +#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1 +#define BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4 +#define BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2 +#define BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8 +#define BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3 +#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN_MASK 0x1 +#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN__SHIFT 0x0 +#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER_MASK 0xffff0000 +#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER__SHIFT 0x10 +#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR_MASK 0xffffffff +#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR__SHIFT 0x0 +#define NB_GBIF_DATA__NB_GBIF_DATA_MASK 0xffffffff +#define NB_GBIF_DATA__NB_GBIF_DATA__SHIFT 0x0 +#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK_MASK 0x1 +#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0 +#define BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK 0x1 +#define BIF_LNCNT_RESET__RESET_LNCNT_EN__SHIFT 0x0 +#define LNCNT_CONTROL__LNCNT_ACC_MODE_MASK 0x1 +#define LNCNT_CONTROL__LNCNT_ACC_MODE__SHIFT 0x0 +#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE_MASK 0x6 +#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE__SHIFT 0x1 +#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x1 +#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x0 +#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x1ffffe +#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x1 +#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x200000 +#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x15 +#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x3ff +#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x0 +#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x400 +#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0xa +#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x3ff +#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x0 +#define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x2 +#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x1 +#define BIF_RESET_EN__PHY_RESET_EN_MASK 0x4 +#define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x2 +#define BIF_RESET_EN__COR_RESET_EN_MASK 0x8 +#define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x3 +#define BIF_RESET_EN__REG_RESET_EN_MASK 0x10 +#define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x4 +#define BIF_RESET_EN__STY_RESET_EN_MASK 0x20 +#define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x5 +#define BIF_RESET_EN__CFG_RESET_EN_MASK 0x40 +#define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x6 +#define BIF_RESET_EN__DRV_RESET_EN_MASK 0x80 +#define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x7 +#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x100 +#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x8 +#define BIF_RESET_EN__HOT_RESET_EN_MASK 0x200 +#define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x9 +#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x400 +#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0xa +#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x800 +#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0xb +#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x3f000 +#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0xc +#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0xc0000 +#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x12 +#define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x100000 +#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x14 +#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x200000 +#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x15 +#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x400000 +#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x16 +#define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x800000 +#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x17 +#define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x1000000 +#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x18 +#define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x2000000 +#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x19 +#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0xc000000 +#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a +#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000 +#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c +#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000 +#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x7 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x0 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x38 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x3 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x3c0 +#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x6 +#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x1 +#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x0 +#define BIF_BACO_MSIC__BACO_LINK_RST_SEL_MASK 0x6 +#define BIF_BACO_MSIC__BACO_LINK_RST_SEL__SHIFT 0x1 +#define BIF_BACO_MSIC__ACPI_BACO_MUX_DIS_MASK 0x10 +#define BIF_BACO_MSIC__ACPI_BACO_MUX_DIS__SHIFT 0x4 +#define BIF_RESET_CNTL__STRAP_EN_MASK 0x1 +#define BIF_RESET_CNTL__STRAP_EN__SHIFT 0x0 +#define BIF_RESET_CNTL__RST_DONE_MASK 0x2 +#define BIF_RESET_CNTL__RST_DONE__SHIFT 0x1 +#define BIF_RESET_CNTL__LINK_TRAIN_EN_MASK 0x4 +#define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x2 +#define BIF_RESET_CNTL__STRAP_ALL_VALID_MASK 0x8 +#define BIF_RESET_CNTL__STRAP_ALL_VALID__SHIFT 0x3 +#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST_MASK 0x100 +#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST__SHIFT 0x8 +#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS_MASK 0x200 +#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9 +#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode_MASK 0x1 +#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0 +#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK 0x2 +#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1 +#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4 +#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2 +#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8 +#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3 +#define BIF_MEM_PG_CNTL__BIF_MEM_SD_EN_MASK 0x1 +#define BIF_MEM_PG_CNTL__BIF_MEM_SD_EN__SHIFT 0x0 +#define BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER_MASK 0xffff0000 +#define BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER__SHIFT 0x10 +#define C_PCIE_P_INDEX__PCIE_INDEX_MASK 0xffffffff +#define C_PCIE_P_INDEX__PCIE_INDEX__SHIFT 0x0 +#define C_PCIE_P_DATA__PCIE_DATA_MASK 0xffffffff +#define C_PCIE_P_DATA__PCIE_DATA__SHIFT 0x0 +#define D2F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff +#define D2F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 +#define D2F1_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff +#define D2F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 +#define D2F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define D2F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define D2F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define D2F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define D2F1_PCIE_FC_P__PD_CREDITS_MASK 0xff +#define D2F1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define D2F1_PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define D2F1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define D2F1_PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define D2F1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define D2F1_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define D2F1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define D2F1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define D2F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define D2F1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define D2F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define D2F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 +#define D2F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 +#define D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 +#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 +#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define D2F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define D2F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 +#define D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 +#define D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define D2F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define D2F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 +#define D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 +#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 +#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 +#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 +#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 +#define D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 +#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 +#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 +#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 +#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 +#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 +#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define D2F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 +#define D2F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 +#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 +#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 +#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 +#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 +#define D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 +#define D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define D2F1_VENDOR_ID__VENDOR_ID_MASK 0xffff +#define D2F1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define D2F1_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 +#define D2F1_DEVICE_ID__DEVICE_ID__SHIFT 0x10 +#define D2F1_COMMAND__IO_ACCESS_EN_MASK 0x1 +#define D2F1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define D2F1_COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define D2F1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define D2F1_COMMAND__BUS_MASTER_EN_MASK 0x4 +#define D2F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define D2F1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define D2F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define D2F1_COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define D2F1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define D2F1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define D2F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define D2F1_COMMAND__AD_STEPPING_MASK 0x80 +#define D2F1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define D2F1_COMMAND__SERR_EN_MASK 0x100 +#define D2F1_COMMAND__SERR_EN__SHIFT 0x8 +#define D2F1_COMMAND__FAST_B2B_EN_MASK 0x200 +#define D2F1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define D2F1_COMMAND__INT_DIS_MASK 0x400 +#define D2F1_COMMAND__INT_DIS__SHIFT 0xa +#define D2F1_STATUS__INT_STATUS_MASK 0x80000 +#define D2F1_STATUS__INT_STATUS__SHIFT 0x13 +#define D2F1_STATUS__CAP_LIST_MASK 0x100000 +#define D2F1_STATUS__CAP_LIST__SHIFT 0x14 +#define D2F1_STATUS__PCI_66_EN_MASK 0x200000 +#define D2F1_STATUS__PCI_66_EN__SHIFT 0x15 +#define D2F1_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D2F1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D2F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D2F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D2F1_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D2F1_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D2F1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D2F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D2F1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D2F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D2F1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D2F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D2F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define D2F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e +#define D2F1_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D2F1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D2F1_REVISION_ID__MINOR_REV_ID_MASK 0xf +#define D2F1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define D2F1_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define D2F1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define D2F1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 +#define D2F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 +#define D2F1_SUB_CLASS__SUB_CLASS_MASK 0xff0000 +#define D2F1_SUB_CLASS__SUB_CLASS__SHIFT 0x10 +#define D2F1_BASE_CLASS__BASE_CLASS_MASK 0xff000000 +#define D2F1_BASE_CLASS__BASE_CLASS__SHIFT 0x18 +#define D2F1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define D2F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define D2F1_LATENCY__LATENCY_TIMER_MASK 0xff00 +#define D2F1_LATENCY__LATENCY_TIMER__SHIFT 0x8 +#define D2F1_HEADER__HEADER_TYPE_MASK 0x7f0000 +#define D2F1_HEADER__HEADER_TYPE__SHIFT 0x10 +#define D2F1_HEADER__DEVICE_TYPE_MASK 0x800000 +#define D2F1_HEADER__DEVICE_TYPE__SHIFT 0x17 +#define D2F1_BIST__BIST_COMP_MASK 0xf000000 +#define D2F1_BIST__BIST_COMP__SHIFT 0x18 +#define D2F1_BIST__BIST_STRT_MASK 0x40000000 +#define D2F1_BIST__BIST_STRT__SHIFT 0x1e +#define D2F1_BIST__BIST_CAP_MASK 0x80000000 +#define D2F1_BIST__BIST_CAP__SHIFT 0x1f +#define D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff +#define D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 +#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 +#define D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 +#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define D2F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf +#define D2F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define D2F1_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 +#define D2F1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 +#define D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define D2F1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 +#define D2F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define D2F1_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 +#define D2F1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 +#define D2F1_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 +#define D2F1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 +#define D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D2F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D2F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 +#define D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e +#define D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf +#define D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 +#define D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 +#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 +#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf +#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 +#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 +#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 +#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff +#define D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff +#define D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff +#define D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 +#define D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 +#define D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 +#define D2F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 +#define D2F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 +#define D2F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 +#define D2F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 +#define D2F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 +#define D2F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 +#define D2F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 +#define D2F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 +#define D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 +#define D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 +#define D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 +#define D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 +#define D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 +#define D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 +#define D2F1_CAP_PTR__CAP_PTR_MASK 0xff +#define D2F1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define D2F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define D2F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define D2F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 +#define D2F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 +#define D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 +#define D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define D2F1_PMI_CAP_LIST__CAP_ID_MASK 0xff +#define D2F1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F1_PMI_CAP__VERSION_MASK 0x70000 +#define D2F1_PMI_CAP__VERSION__SHIFT 0x10 +#define D2F1_PMI_CAP__PME_CLOCK_MASK 0x80000 +#define D2F1_PMI_CAP__PME_CLOCK__SHIFT 0x13 +#define D2F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 +#define D2F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 +#define D2F1_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 +#define D2F1_PMI_CAP__AUX_CURRENT__SHIFT 0x16 +#define D2F1_PMI_CAP__D1_SUPPORT_MASK 0x2000000 +#define D2F1_PMI_CAP__D1_SUPPORT__SHIFT 0x19 +#define D2F1_PMI_CAP__D2_SUPPORT_MASK 0x4000000 +#define D2F1_PMI_CAP__D2_SUPPORT__SHIFT 0x1a +#define D2F1_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 +#define D2F1_PMI_CAP__PME_SUPPORT__SHIFT 0x1b +#define D2F1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define D2F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define D2F1_PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define D2F1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define D2F1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define D2F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define D2F1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define D2F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define D2F1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define D2F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define D2F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define D2F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define D2F1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define D2F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define D2F1_PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define D2F1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F1_PCIE_CAP__VERSION_MASK 0xf0000 +#define D2F1_PCIE_CAP__VERSION__SHIFT 0x10 +#define D2F1_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 +#define D2F1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 +#define D2F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 +#define D2F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 +#define D2F1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 +#define D2F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 +#define D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define D2F1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define D2F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define D2F1_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define D2F1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define D2F1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define D2F1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define D2F1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define D2F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define D2F1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define D2F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define D2F1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define D2F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define D2F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define D2F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define D2F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define D2F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define D2F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define D2F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define D2F1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define D2F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 +#define D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define D2F1_DEVICE_STATUS__CORR_ERR_MASK 0x10000 +#define D2F1_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 +#define D2F1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 +#define D2F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 +#define D2F1_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 +#define D2F1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 +#define D2F1_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 +#define D2F1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 +#define D2F1_DEVICE_STATUS__AUX_PWR_MASK 0x100000 +#define D2F1_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 +#define D2F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 +#define D2F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 +#define D2F1_LINK_CAP__LINK_SPEED_MASK 0xf +#define D2F1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define D2F1_LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define D2F1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define D2F1_LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define D2F1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define D2F1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define D2F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define D2F1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define D2F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define D2F1_LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define D2F1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define D2F1_LINK_CNTL__PM_CONTROL_MASK 0x3 +#define D2F1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define D2F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define D2F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define D2F1_LINK_CNTL__LINK_DIS_MASK 0x10 +#define D2F1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define D2F1_LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define D2F1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define D2F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define D2F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define D2F1_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define D2F1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define D2F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 +#define D2F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 +#define D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 +#define D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 +#define D2F1_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 +#define D2F1_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b +#define D2F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 +#define D2F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c +#define D2F1_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 +#define D2F1_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d +#define D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 +#define D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e +#define D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 +#define D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f +#define D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 +#define D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 +#define D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define D2F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 +#define D2F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 +#define D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 +#define D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define D2F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 +#define D2F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define D2F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 +#define D2F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 +#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 +#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 +#define D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 +#define D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 +#define D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 +#define D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 +#define D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 +#define D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 +#define D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 +#define D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define D2F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 +#define D2F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 +#define D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 +#define D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 +#define D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 +#define D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 +#define D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 +#define D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 +#define D2F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 +#define D2F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 +#define D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 +#define D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 +#define D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 +#define D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 +#define D2F1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 +#define D2F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 +#define D2F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 +#define D2F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 +#define D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 +#define D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 +#define D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 +#define D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 +#define D2F1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 +#define D2F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 +#define D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 +#define D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 +#define D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 +#define D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define D2F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 +#define D2F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 +#define D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 +#define D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 +#define D2F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff +#define D2F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define D2F1_ROOT_STATUS__PME_STATUS_MASK 0x10000 +#define D2F1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define D2F1_ROOT_STATUS__PME_PENDING_MASK 0x20000 +#define D2F1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 +#define D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 +#define D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 +#define D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 +#define D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define D2F1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define D2F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define D2F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define D2F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 +#define D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 +#define D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define D2F1_DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define D2F1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define D2F1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define D2F1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define D2F1_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 +#define D2F1_DEVICE_STATUS2__RESERVED__SHIFT 0x10 +#define D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define D2F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define D2F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define D2F1_LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define D2F1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define D2F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define D2F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define D2F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define D2F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define D2F1_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define D2F1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define D2F1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define D2F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 +#define D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 +#define D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 +#define D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 +#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 +#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 +#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 +#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 +#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 +#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 +#define D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 +#define D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 +#define D2F1_SLOT_CAP2__RESERVED_MASK 0xffffffff +#define D2F1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define D2F1_SLOT_CNTL2__RESERVED_MASK 0xffff +#define D2F1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define D2F1_SLOT_STATUS2__RESERVED_MASK 0xffff0000 +#define D2F1_SLOT_STATUS2__RESERVED__SHIFT 0x10 +#define D2F1_MSI_CAP_LIST__CAP_ID_MASK 0xff +#define D2F1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F1_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 +#define D2F1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 +#define D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 +#define D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 +#define D2F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 +#define D2F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 +#define D2F1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 +#define D2F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 +#define D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 +#define D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 +#define D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define D2F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define D2F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define D2F1_MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define D2F1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define D2F1_SSID_CAP_LIST__CAP_ID_MASK 0xff +#define D2F1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define D2F1_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 +#define D2F1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define D2F1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff +#define D2F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F1_MSI_MAP_CAP__EN_MASK 0x10000 +#define D2F1_MSI_MAP_CAP__EN__SHIFT 0x10 +#define D2F1_MSI_MAP_CAP__FIXD_MASK 0x20000 +#define D2F1_MSI_MAP_CAP__FIXD__SHIFT 0x11 +#define D2F1_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 +#define D2F1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b +#define D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 +#define D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff +#define D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define D2F1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define D2F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define D2F1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define D2F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define D2F1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define D2F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define D2F1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define D2F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 +#define D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 +#define D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 +#define D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 +#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 +#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 +#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 +#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 +#define D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 +#define D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 +#define D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 +#define D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff +#define D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 +#define D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define D2F1_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define D2F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define D2F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define D2F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 +#define D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 +#define D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 +#define D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 +#define D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 +#define D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 +#define D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 +#define D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 +#define D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 +#define D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 +#define D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 +#define D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 +#define D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 +#define D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 +#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define D2F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define D2F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 +#define D2F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 +#define D2F1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 +#define D2F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f +#define D2F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define D2F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define D2F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define D2F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define D2F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define D2F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f +#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 +#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff +#define D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define D2F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff +#define D2F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 +#define D2F2_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff +#define D2F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 +#define D2F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define D2F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define D2F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define D2F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define D2F2_PCIE_FC_P__PD_CREDITS_MASK 0xff +#define D2F2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define D2F2_PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define D2F2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define D2F2_PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define D2F2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define D2F2_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define D2F2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define D2F2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define D2F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define D2F2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define D2F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define D2F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 +#define D2F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 +#define D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 +#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 +#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define D2F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define D2F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 +#define D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 +#define D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define D2F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define D2F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 +#define D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 +#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 +#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 +#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 +#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 +#define D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 +#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 +#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 +#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 +#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 +#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 +#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define D2F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 +#define D2F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 +#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 +#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 +#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 +#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 +#define D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 +#define D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define D2F2_VENDOR_ID__VENDOR_ID_MASK 0xffff +#define D2F2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define D2F2_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 +#define D2F2_DEVICE_ID__DEVICE_ID__SHIFT 0x10 +#define D2F2_COMMAND__IO_ACCESS_EN_MASK 0x1 +#define D2F2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define D2F2_COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define D2F2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define D2F2_COMMAND__BUS_MASTER_EN_MASK 0x4 +#define D2F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define D2F2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define D2F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define D2F2_COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define D2F2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define D2F2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define D2F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define D2F2_COMMAND__AD_STEPPING_MASK 0x80 +#define D2F2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define D2F2_COMMAND__SERR_EN_MASK 0x100 +#define D2F2_COMMAND__SERR_EN__SHIFT 0x8 +#define D2F2_COMMAND__FAST_B2B_EN_MASK 0x200 +#define D2F2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define D2F2_COMMAND__INT_DIS_MASK 0x400 +#define D2F2_COMMAND__INT_DIS__SHIFT 0xa +#define D2F2_STATUS__INT_STATUS_MASK 0x80000 +#define D2F2_STATUS__INT_STATUS__SHIFT 0x13 +#define D2F2_STATUS__CAP_LIST_MASK 0x100000 +#define D2F2_STATUS__CAP_LIST__SHIFT 0x14 +#define D2F2_STATUS__PCI_66_EN_MASK 0x200000 +#define D2F2_STATUS__PCI_66_EN__SHIFT 0x15 +#define D2F2_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D2F2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D2F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D2F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D2F2_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D2F2_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D2F2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D2F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D2F2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D2F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D2F2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D2F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D2F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define D2F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e +#define D2F2_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D2F2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D2F2_REVISION_ID__MINOR_REV_ID_MASK 0xf +#define D2F2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define D2F2_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define D2F2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define D2F2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 +#define D2F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 +#define D2F2_SUB_CLASS__SUB_CLASS_MASK 0xff0000 +#define D2F2_SUB_CLASS__SUB_CLASS__SHIFT 0x10 +#define D2F2_BASE_CLASS__BASE_CLASS_MASK 0xff000000 +#define D2F2_BASE_CLASS__BASE_CLASS__SHIFT 0x18 +#define D2F2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define D2F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define D2F2_LATENCY__LATENCY_TIMER_MASK 0xff00 +#define D2F2_LATENCY__LATENCY_TIMER__SHIFT 0x8 +#define D2F2_HEADER__HEADER_TYPE_MASK 0x7f0000 +#define D2F2_HEADER__HEADER_TYPE__SHIFT 0x10 +#define D2F2_HEADER__DEVICE_TYPE_MASK 0x800000 +#define D2F2_HEADER__DEVICE_TYPE__SHIFT 0x17 +#define D2F2_BIST__BIST_COMP_MASK 0xf000000 +#define D2F2_BIST__BIST_COMP__SHIFT 0x18 +#define D2F2_BIST__BIST_STRT_MASK 0x40000000 +#define D2F2_BIST__BIST_STRT__SHIFT 0x1e +#define D2F2_BIST__BIST_CAP_MASK 0x80000000 +#define D2F2_BIST__BIST_CAP__SHIFT 0x1f +#define D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff +#define D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 +#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 +#define D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 +#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define D2F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf +#define D2F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define D2F2_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 +#define D2F2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 +#define D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define D2F2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 +#define D2F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define D2F2_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 +#define D2F2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 +#define D2F2_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 +#define D2F2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 +#define D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D2F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D2F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 +#define D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e +#define D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf +#define D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 +#define D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 +#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 +#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf +#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 +#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 +#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 +#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff +#define D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff +#define D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff +#define D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 +#define D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 +#define D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 +#define D2F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 +#define D2F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 +#define D2F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 +#define D2F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 +#define D2F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 +#define D2F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 +#define D2F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 +#define D2F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 +#define D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 +#define D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 +#define D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 +#define D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 +#define D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 +#define D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 +#define D2F2_CAP_PTR__CAP_PTR_MASK 0xff +#define D2F2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define D2F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define D2F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define D2F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 +#define D2F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 +#define D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 +#define D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define D2F2_PMI_CAP_LIST__CAP_ID_MASK 0xff +#define D2F2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F2_PMI_CAP__VERSION_MASK 0x70000 +#define D2F2_PMI_CAP__VERSION__SHIFT 0x10 +#define D2F2_PMI_CAP__PME_CLOCK_MASK 0x80000 +#define D2F2_PMI_CAP__PME_CLOCK__SHIFT 0x13 +#define D2F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 +#define D2F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 +#define D2F2_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 +#define D2F2_PMI_CAP__AUX_CURRENT__SHIFT 0x16 +#define D2F2_PMI_CAP__D1_SUPPORT_MASK 0x2000000 +#define D2F2_PMI_CAP__D1_SUPPORT__SHIFT 0x19 +#define D2F2_PMI_CAP__D2_SUPPORT_MASK 0x4000000 +#define D2F2_PMI_CAP__D2_SUPPORT__SHIFT 0x1a +#define D2F2_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 +#define D2F2_PMI_CAP__PME_SUPPORT__SHIFT 0x1b +#define D2F2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define D2F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define D2F2_PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define D2F2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define D2F2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define D2F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define D2F2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define D2F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define D2F2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define D2F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define D2F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define D2F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define D2F2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define D2F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define D2F2_PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define D2F2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F2_PCIE_CAP__VERSION_MASK 0xf0000 +#define D2F2_PCIE_CAP__VERSION__SHIFT 0x10 +#define D2F2_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 +#define D2F2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 +#define D2F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 +#define D2F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 +#define D2F2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 +#define D2F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 +#define D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define D2F2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define D2F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define D2F2_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define D2F2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define D2F2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define D2F2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define D2F2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define D2F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define D2F2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define D2F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define D2F2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define D2F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define D2F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define D2F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define D2F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define D2F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define D2F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define D2F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define D2F2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define D2F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 +#define D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define D2F2_DEVICE_STATUS__CORR_ERR_MASK 0x10000 +#define D2F2_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 +#define D2F2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 +#define D2F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 +#define D2F2_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 +#define D2F2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 +#define D2F2_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 +#define D2F2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 +#define D2F2_DEVICE_STATUS__AUX_PWR_MASK 0x100000 +#define D2F2_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 +#define D2F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 +#define D2F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 +#define D2F2_LINK_CAP__LINK_SPEED_MASK 0xf +#define D2F2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define D2F2_LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define D2F2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define D2F2_LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define D2F2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define D2F2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define D2F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define D2F2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define D2F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define D2F2_LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define D2F2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define D2F2_LINK_CNTL__PM_CONTROL_MASK 0x3 +#define D2F2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define D2F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define D2F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define D2F2_LINK_CNTL__LINK_DIS_MASK 0x10 +#define D2F2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define D2F2_LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define D2F2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define D2F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define D2F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define D2F2_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define D2F2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define D2F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 +#define D2F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 +#define D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 +#define D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 +#define D2F2_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 +#define D2F2_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b +#define D2F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 +#define D2F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c +#define D2F2_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 +#define D2F2_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d +#define D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 +#define D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e +#define D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 +#define D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f +#define D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 +#define D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 +#define D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define D2F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 +#define D2F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 +#define D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 +#define D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define D2F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 +#define D2F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define D2F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 +#define D2F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 +#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 +#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 +#define D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 +#define D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 +#define D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 +#define D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 +#define D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 +#define D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 +#define D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 +#define D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define D2F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 +#define D2F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 +#define D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 +#define D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 +#define D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 +#define D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 +#define D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 +#define D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 +#define D2F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 +#define D2F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 +#define D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 +#define D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 +#define D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 +#define D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 +#define D2F2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 +#define D2F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 +#define D2F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 +#define D2F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 +#define D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 +#define D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 +#define D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 +#define D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 +#define D2F2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 +#define D2F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 +#define D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 +#define D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 +#define D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 +#define D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define D2F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 +#define D2F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 +#define D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 +#define D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 +#define D2F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff +#define D2F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define D2F2_ROOT_STATUS__PME_STATUS_MASK 0x10000 +#define D2F2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define D2F2_ROOT_STATUS__PME_PENDING_MASK 0x20000 +#define D2F2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 +#define D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 +#define D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 +#define D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 +#define D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define D2F2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define D2F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define D2F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define D2F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 +#define D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 +#define D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define D2F2_DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define D2F2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define D2F2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define D2F2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define D2F2_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 +#define D2F2_DEVICE_STATUS2__RESERVED__SHIFT 0x10 +#define D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define D2F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define D2F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define D2F2_LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define D2F2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define D2F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define D2F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define D2F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define D2F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define D2F2_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define D2F2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define D2F2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define D2F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 +#define D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 +#define D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 +#define D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 +#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 +#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 +#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 +#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 +#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 +#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 +#define D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 +#define D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 +#define D2F2_SLOT_CAP2__RESERVED_MASK 0xffffffff +#define D2F2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define D2F2_SLOT_CNTL2__RESERVED_MASK 0xffff +#define D2F2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define D2F2_SLOT_STATUS2__RESERVED_MASK 0xffff0000 +#define D2F2_SLOT_STATUS2__RESERVED__SHIFT 0x10 +#define D2F2_MSI_CAP_LIST__CAP_ID_MASK 0xff +#define D2F2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F2_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 +#define D2F2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 +#define D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 +#define D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 +#define D2F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 +#define D2F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 +#define D2F2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 +#define D2F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 +#define D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 +#define D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 +#define D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define D2F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define D2F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define D2F2_MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define D2F2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define D2F2_SSID_CAP_LIST__CAP_ID_MASK 0xff +#define D2F2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define D2F2_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 +#define D2F2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define D2F2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff +#define D2F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F2_MSI_MAP_CAP__EN_MASK 0x10000 +#define D2F2_MSI_MAP_CAP__EN__SHIFT 0x10 +#define D2F2_MSI_MAP_CAP__FIXD_MASK 0x20000 +#define D2F2_MSI_MAP_CAP__FIXD__SHIFT 0x11 +#define D2F2_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 +#define D2F2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b +#define D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 +#define D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff +#define D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define D2F2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define D2F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define D2F2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define D2F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define D2F2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define D2F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define D2F2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define D2F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 +#define D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 +#define D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 +#define D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 +#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 +#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 +#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 +#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 +#define D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 +#define D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 +#define D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 +#define D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff +#define D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 +#define D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define D2F2_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define D2F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define D2F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define D2F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 +#define D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 +#define D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 +#define D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 +#define D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 +#define D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 +#define D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 +#define D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 +#define D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 +#define D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 +#define D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 +#define D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 +#define D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 +#define D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 +#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define D2F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define D2F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 +#define D2F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 +#define D2F2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 +#define D2F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f +#define D2F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define D2F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define D2F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define D2F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define D2F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define D2F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f +#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 +#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff +#define D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define D2F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff +#define D2F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 +#define D2F3_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff +#define D2F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 +#define D2F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define D2F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define D2F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define D2F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define D2F3_PCIE_FC_P__PD_CREDITS_MASK 0xff +#define D2F3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define D2F3_PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define D2F3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define D2F3_PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define D2F3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define D2F3_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define D2F3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define D2F3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define D2F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define D2F3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define D2F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define D2F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 +#define D2F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 +#define D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 +#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 +#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define D2F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define D2F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 +#define D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 +#define D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define D2F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define D2F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 +#define D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 +#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 +#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 +#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 +#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 +#define D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 +#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 +#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 +#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 +#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 +#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 +#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define D2F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 +#define D2F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 +#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 +#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 +#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 +#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 +#define D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 +#define D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define D2F3_VENDOR_ID__VENDOR_ID_MASK 0xffff +#define D2F3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define D2F3_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 +#define D2F3_DEVICE_ID__DEVICE_ID__SHIFT 0x10 +#define D2F3_COMMAND__IO_ACCESS_EN_MASK 0x1 +#define D2F3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define D2F3_COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define D2F3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define D2F3_COMMAND__BUS_MASTER_EN_MASK 0x4 +#define D2F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define D2F3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define D2F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define D2F3_COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define D2F3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define D2F3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define D2F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define D2F3_COMMAND__AD_STEPPING_MASK 0x80 +#define D2F3_COMMAND__AD_STEPPING__SHIFT 0x7 +#define D2F3_COMMAND__SERR_EN_MASK 0x100 +#define D2F3_COMMAND__SERR_EN__SHIFT 0x8 +#define D2F3_COMMAND__FAST_B2B_EN_MASK 0x200 +#define D2F3_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define D2F3_COMMAND__INT_DIS_MASK 0x400 +#define D2F3_COMMAND__INT_DIS__SHIFT 0xa +#define D2F3_STATUS__INT_STATUS_MASK 0x80000 +#define D2F3_STATUS__INT_STATUS__SHIFT 0x13 +#define D2F3_STATUS__CAP_LIST_MASK 0x100000 +#define D2F3_STATUS__CAP_LIST__SHIFT 0x14 +#define D2F3_STATUS__PCI_66_EN_MASK 0x200000 +#define D2F3_STATUS__PCI_66_EN__SHIFT 0x15 +#define D2F3_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D2F3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D2F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D2F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D2F3_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D2F3_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D2F3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D2F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D2F3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D2F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D2F3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D2F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D2F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define D2F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e +#define D2F3_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D2F3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D2F3_REVISION_ID__MINOR_REV_ID_MASK 0xf +#define D2F3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define D2F3_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define D2F3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define D2F3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 +#define D2F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 +#define D2F3_SUB_CLASS__SUB_CLASS_MASK 0xff0000 +#define D2F3_SUB_CLASS__SUB_CLASS__SHIFT 0x10 +#define D2F3_BASE_CLASS__BASE_CLASS_MASK 0xff000000 +#define D2F3_BASE_CLASS__BASE_CLASS__SHIFT 0x18 +#define D2F3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define D2F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define D2F3_LATENCY__LATENCY_TIMER_MASK 0xff00 +#define D2F3_LATENCY__LATENCY_TIMER__SHIFT 0x8 +#define D2F3_HEADER__HEADER_TYPE_MASK 0x7f0000 +#define D2F3_HEADER__HEADER_TYPE__SHIFT 0x10 +#define D2F3_HEADER__DEVICE_TYPE_MASK 0x800000 +#define D2F3_HEADER__DEVICE_TYPE__SHIFT 0x17 +#define D2F3_BIST__BIST_COMP_MASK 0xf000000 +#define D2F3_BIST__BIST_COMP__SHIFT 0x18 +#define D2F3_BIST__BIST_STRT_MASK 0x40000000 +#define D2F3_BIST__BIST_STRT__SHIFT 0x1e +#define D2F3_BIST__BIST_CAP_MASK 0x80000000 +#define D2F3_BIST__BIST_CAP__SHIFT 0x1f +#define D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff +#define D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 +#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 +#define D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 +#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define D2F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf +#define D2F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define D2F3_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 +#define D2F3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 +#define D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define D2F3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 +#define D2F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define D2F3_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 +#define D2F3_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 +#define D2F3_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 +#define D2F3_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 +#define D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D2F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D2F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 +#define D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e +#define D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf +#define D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 +#define D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 +#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 +#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf +#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 +#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 +#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 +#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff +#define D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff +#define D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff +#define D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 +#define D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 +#define D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 +#define D2F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 +#define D2F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 +#define D2F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 +#define D2F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 +#define D2F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 +#define D2F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 +#define D2F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 +#define D2F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 +#define D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 +#define D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 +#define D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 +#define D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 +#define D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 +#define D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 +#define D2F3_CAP_PTR__CAP_PTR_MASK 0xff +#define D2F3_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define D2F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define D2F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define D2F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 +#define D2F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 +#define D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 +#define D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define D2F3_PMI_CAP_LIST__CAP_ID_MASK 0xff +#define D2F3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F3_PMI_CAP__VERSION_MASK 0x70000 +#define D2F3_PMI_CAP__VERSION__SHIFT 0x10 +#define D2F3_PMI_CAP__PME_CLOCK_MASK 0x80000 +#define D2F3_PMI_CAP__PME_CLOCK__SHIFT 0x13 +#define D2F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 +#define D2F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 +#define D2F3_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 +#define D2F3_PMI_CAP__AUX_CURRENT__SHIFT 0x16 +#define D2F3_PMI_CAP__D1_SUPPORT_MASK 0x2000000 +#define D2F3_PMI_CAP__D1_SUPPORT__SHIFT 0x19 +#define D2F3_PMI_CAP__D2_SUPPORT_MASK 0x4000000 +#define D2F3_PMI_CAP__D2_SUPPORT__SHIFT 0x1a +#define D2F3_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 +#define D2F3_PMI_CAP__PME_SUPPORT__SHIFT 0x1b +#define D2F3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define D2F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define D2F3_PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define D2F3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define D2F3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define D2F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define D2F3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define D2F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define D2F3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define D2F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define D2F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define D2F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define D2F3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define D2F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define D2F3_PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define D2F3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F3_PCIE_CAP__VERSION_MASK 0xf0000 +#define D2F3_PCIE_CAP__VERSION__SHIFT 0x10 +#define D2F3_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 +#define D2F3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 +#define D2F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 +#define D2F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 +#define D2F3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 +#define D2F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 +#define D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define D2F3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define D2F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define D2F3_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define D2F3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define D2F3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define D2F3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define D2F3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define D2F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define D2F3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define D2F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define D2F3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define D2F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define D2F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define D2F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define D2F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define D2F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define D2F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define D2F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define D2F3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define D2F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 +#define D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define D2F3_DEVICE_STATUS__CORR_ERR_MASK 0x10000 +#define D2F3_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 +#define D2F3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 +#define D2F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 +#define D2F3_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 +#define D2F3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 +#define D2F3_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 +#define D2F3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 +#define D2F3_DEVICE_STATUS__AUX_PWR_MASK 0x100000 +#define D2F3_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 +#define D2F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 +#define D2F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 +#define D2F3_LINK_CAP__LINK_SPEED_MASK 0xf +#define D2F3_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define D2F3_LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define D2F3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define D2F3_LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define D2F3_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define D2F3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define D2F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define D2F3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define D2F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define D2F3_LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define D2F3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define D2F3_LINK_CNTL__PM_CONTROL_MASK 0x3 +#define D2F3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define D2F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define D2F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define D2F3_LINK_CNTL__LINK_DIS_MASK 0x10 +#define D2F3_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define D2F3_LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define D2F3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define D2F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define D2F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define D2F3_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define D2F3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define D2F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 +#define D2F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 +#define D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 +#define D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 +#define D2F3_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 +#define D2F3_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b +#define D2F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 +#define D2F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c +#define D2F3_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 +#define D2F3_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d +#define D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 +#define D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e +#define D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 +#define D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f +#define D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 +#define D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 +#define D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define D2F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 +#define D2F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 +#define D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 +#define D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define D2F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 +#define D2F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define D2F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 +#define D2F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 +#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 +#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 +#define D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 +#define D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 +#define D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 +#define D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 +#define D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 +#define D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 +#define D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 +#define D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define D2F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 +#define D2F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 +#define D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 +#define D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 +#define D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 +#define D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 +#define D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 +#define D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 +#define D2F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 +#define D2F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 +#define D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 +#define D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 +#define D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 +#define D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 +#define D2F3_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 +#define D2F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 +#define D2F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 +#define D2F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 +#define D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 +#define D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 +#define D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 +#define D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 +#define D2F3_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 +#define D2F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 +#define D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 +#define D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 +#define D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 +#define D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define D2F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 +#define D2F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 +#define D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 +#define D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 +#define D2F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff +#define D2F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define D2F3_ROOT_STATUS__PME_STATUS_MASK 0x10000 +#define D2F3_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define D2F3_ROOT_STATUS__PME_PENDING_MASK 0x20000 +#define D2F3_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 +#define D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 +#define D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 +#define D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 +#define D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define D2F3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define D2F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define D2F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define D2F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 +#define D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 +#define D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define D2F3_DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define D2F3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define D2F3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define D2F3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define D2F3_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 +#define D2F3_DEVICE_STATUS2__RESERVED__SHIFT 0x10 +#define D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define D2F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define D2F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define D2F3_LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define D2F3_LINK_CAP2__RESERVED__SHIFT 0x9 +#define D2F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define D2F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define D2F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define D2F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define D2F3_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define D2F3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define D2F3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define D2F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 +#define D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 +#define D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 +#define D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 +#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 +#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 +#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 +#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 +#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 +#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 +#define D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 +#define D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 +#define D2F3_SLOT_CAP2__RESERVED_MASK 0xffffffff +#define D2F3_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define D2F3_SLOT_CNTL2__RESERVED_MASK 0xffff +#define D2F3_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define D2F3_SLOT_STATUS2__RESERVED_MASK 0xffff0000 +#define D2F3_SLOT_STATUS2__RESERVED__SHIFT 0x10 +#define D2F3_MSI_CAP_LIST__CAP_ID_MASK 0xff +#define D2F3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F3_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 +#define D2F3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 +#define D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 +#define D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 +#define D2F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 +#define D2F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 +#define D2F3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 +#define D2F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 +#define D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 +#define D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 +#define D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define D2F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define D2F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define D2F3_MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define D2F3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define D2F3_SSID_CAP_LIST__CAP_ID_MASK 0xff +#define D2F3_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F3_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define D2F3_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 +#define D2F3_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define D2F3_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff +#define D2F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F3_MSI_MAP_CAP__EN_MASK 0x10000 +#define D2F3_MSI_MAP_CAP__EN__SHIFT 0x10 +#define D2F3_MSI_MAP_CAP__FIXD_MASK 0x20000 +#define D2F3_MSI_MAP_CAP__FIXD__SHIFT 0x11 +#define D2F3_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 +#define D2F3_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b +#define D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 +#define D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff +#define D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define D2F3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define D2F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define D2F3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define D2F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define D2F3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define D2F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define D2F3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define D2F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 +#define D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 +#define D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 +#define D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 +#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 +#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 +#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 +#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 +#define D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 +#define D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 +#define D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 +#define D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff +#define D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 +#define D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define D2F3_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define D2F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define D2F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define D2F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 +#define D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 +#define D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 +#define D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 +#define D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 +#define D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 +#define D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 +#define D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 +#define D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 +#define D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 +#define D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 +#define D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 +#define D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 +#define D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 +#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define D2F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define D2F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 +#define D2F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 +#define D2F3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 +#define D2F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f +#define D2F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define D2F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define D2F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define D2F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define D2F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define D2F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f +#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 +#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff +#define D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define D2F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff +#define D2F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 +#define D2F4_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff +#define D2F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 +#define D2F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define D2F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define D2F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define D2F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define D2F4_PCIE_FC_P__PD_CREDITS_MASK 0xff +#define D2F4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define D2F4_PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define D2F4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define D2F4_PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define D2F4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define D2F4_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define D2F4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define D2F4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define D2F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define D2F4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define D2F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define D2F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 +#define D2F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 +#define D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 +#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 +#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define D2F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define D2F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 +#define D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 +#define D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define D2F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define D2F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 +#define D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 +#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 +#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 +#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 +#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 +#define D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 +#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 +#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 +#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 +#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 +#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 +#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define D2F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 +#define D2F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 +#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 +#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 +#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 +#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 +#define D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 +#define D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define D2F4_VENDOR_ID__VENDOR_ID_MASK 0xffff +#define D2F4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define D2F4_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 +#define D2F4_DEVICE_ID__DEVICE_ID__SHIFT 0x10 +#define D2F4_COMMAND__IO_ACCESS_EN_MASK 0x1 +#define D2F4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define D2F4_COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define D2F4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define D2F4_COMMAND__BUS_MASTER_EN_MASK 0x4 +#define D2F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define D2F4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define D2F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define D2F4_COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define D2F4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define D2F4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define D2F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define D2F4_COMMAND__AD_STEPPING_MASK 0x80 +#define D2F4_COMMAND__AD_STEPPING__SHIFT 0x7 +#define D2F4_COMMAND__SERR_EN_MASK 0x100 +#define D2F4_COMMAND__SERR_EN__SHIFT 0x8 +#define D2F4_COMMAND__FAST_B2B_EN_MASK 0x200 +#define D2F4_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define D2F4_COMMAND__INT_DIS_MASK 0x400 +#define D2F4_COMMAND__INT_DIS__SHIFT 0xa +#define D2F4_STATUS__INT_STATUS_MASK 0x80000 +#define D2F4_STATUS__INT_STATUS__SHIFT 0x13 +#define D2F4_STATUS__CAP_LIST_MASK 0x100000 +#define D2F4_STATUS__CAP_LIST__SHIFT 0x14 +#define D2F4_STATUS__PCI_66_EN_MASK 0x200000 +#define D2F4_STATUS__PCI_66_EN__SHIFT 0x15 +#define D2F4_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D2F4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D2F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D2F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D2F4_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D2F4_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D2F4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D2F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D2F4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D2F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D2F4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D2F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D2F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define D2F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e +#define D2F4_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D2F4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D2F4_REVISION_ID__MINOR_REV_ID_MASK 0xf +#define D2F4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define D2F4_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define D2F4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define D2F4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 +#define D2F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 +#define D2F4_SUB_CLASS__SUB_CLASS_MASK 0xff0000 +#define D2F4_SUB_CLASS__SUB_CLASS__SHIFT 0x10 +#define D2F4_BASE_CLASS__BASE_CLASS_MASK 0xff000000 +#define D2F4_BASE_CLASS__BASE_CLASS__SHIFT 0x18 +#define D2F4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define D2F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define D2F4_LATENCY__LATENCY_TIMER_MASK 0xff00 +#define D2F4_LATENCY__LATENCY_TIMER__SHIFT 0x8 +#define D2F4_HEADER__HEADER_TYPE_MASK 0x7f0000 +#define D2F4_HEADER__HEADER_TYPE__SHIFT 0x10 +#define D2F4_HEADER__DEVICE_TYPE_MASK 0x800000 +#define D2F4_HEADER__DEVICE_TYPE__SHIFT 0x17 +#define D2F4_BIST__BIST_COMP_MASK 0xf000000 +#define D2F4_BIST__BIST_COMP__SHIFT 0x18 +#define D2F4_BIST__BIST_STRT_MASK 0x40000000 +#define D2F4_BIST__BIST_STRT__SHIFT 0x1e +#define D2F4_BIST__BIST_CAP_MASK 0x80000000 +#define D2F4_BIST__BIST_CAP__SHIFT 0x1f +#define D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff +#define D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 +#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 +#define D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 +#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define D2F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf +#define D2F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define D2F4_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 +#define D2F4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 +#define D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define D2F4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 +#define D2F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define D2F4_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 +#define D2F4_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 +#define D2F4_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 +#define D2F4_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 +#define D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D2F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D2F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 +#define D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e +#define D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf +#define D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 +#define D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 +#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 +#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf +#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 +#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 +#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 +#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff +#define D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff +#define D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff +#define D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 +#define D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 +#define D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 +#define D2F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 +#define D2F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 +#define D2F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 +#define D2F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 +#define D2F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 +#define D2F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 +#define D2F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 +#define D2F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 +#define D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 +#define D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 +#define D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 +#define D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 +#define D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 +#define D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 +#define D2F4_CAP_PTR__CAP_PTR_MASK 0xff +#define D2F4_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define D2F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define D2F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define D2F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 +#define D2F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 +#define D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 +#define D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define D2F4_PMI_CAP_LIST__CAP_ID_MASK 0xff +#define D2F4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F4_PMI_CAP__VERSION_MASK 0x70000 +#define D2F4_PMI_CAP__VERSION__SHIFT 0x10 +#define D2F4_PMI_CAP__PME_CLOCK_MASK 0x80000 +#define D2F4_PMI_CAP__PME_CLOCK__SHIFT 0x13 +#define D2F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 +#define D2F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 +#define D2F4_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 +#define D2F4_PMI_CAP__AUX_CURRENT__SHIFT 0x16 +#define D2F4_PMI_CAP__D1_SUPPORT_MASK 0x2000000 +#define D2F4_PMI_CAP__D1_SUPPORT__SHIFT 0x19 +#define D2F4_PMI_CAP__D2_SUPPORT_MASK 0x4000000 +#define D2F4_PMI_CAP__D2_SUPPORT__SHIFT 0x1a +#define D2F4_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 +#define D2F4_PMI_CAP__PME_SUPPORT__SHIFT 0x1b +#define D2F4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define D2F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define D2F4_PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define D2F4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define D2F4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define D2F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define D2F4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define D2F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define D2F4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define D2F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define D2F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define D2F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define D2F4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define D2F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define D2F4_PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define D2F4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F4_PCIE_CAP__VERSION_MASK 0xf0000 +#define D2F4_PCIE_CAP__VERSION__SHIFT 0x10 +#define D2F4_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 +#define D2F4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 +#define D2F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 +#define D2F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 +#define D2F4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 +#define D2F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 +#define D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define D2F4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define D2F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define D2F4_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define D2F4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define D2F4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define D2F4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define D2F4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define D2F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define D2F4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define D2F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define D2F4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define D2F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define D2F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define D2F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define D2F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define D2F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define D2F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define D2F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define D2F4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define D2F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 +#define D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define D2F4_DEVICE_STATUS__CORR_ERR_MASK 0x10000 +#define D2F4_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 +#define D2F4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 +#define D2F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 +#define D2F4_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 +#define D2F4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 +#define D2F4_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 +#define D2F4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 +#define D2F4_DEVICE_STATUS__AUX_PWR_MASK 0x100000 +#define D2F4_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 +#define D2F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 +#define D2F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 +#define D2F4_LINK_CAP__LINK_SPEED_MASK 0xf +#define D2F4_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define D2F4_LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define D2F4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define D2F4_LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define D2F4_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define D2F4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define D2F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define D2F4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define D2F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define D2F4_LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define D2F4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define D2F4_LINK_CNTL__PM_CONTROL_MASK 0x3 +#define D2F4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define D2F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define D2F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define D2F4_LINK_CNTL__LINK_DIS_MASK 0x10 +#define D2F4_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define D2F4_LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define D2F4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define D2F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define D2F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define D2F4_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define D2F4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define D2F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 +#define D2F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 +#define D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 +#define D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 +#define D2F4_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 +#define D2F4_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b +#define D2F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 +#define D2F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c +#define D2F4_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 +#define D2F4_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d +#define D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 +#define D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e +#define D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 +#define D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f +#define D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 +#define D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 +#define D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define D2F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 +#define D2F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 +#define D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 +#define D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define D2F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 +#define D2F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define D2F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 +#define D2F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 +#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 +#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 +#define D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 +#define D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 +#define D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 +#define D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 +#define D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 +#define D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 +#define D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 +#define D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define D2F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 +#define D2F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 +#define D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 +#define D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 +#define D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 +#define D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 +#define D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 +#define D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 +#define D2F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 +#define D2F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 +#define D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 +#define D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 +#define D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 +#define D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 +#define D2F4_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 +#define D2F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 +#define D2F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 +#define D2F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 +#define D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 +#define D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 +#define D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 +#define D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 +#define D2F4_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 +#define D2F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 +#define D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 +#define D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 +#define D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 +#define D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define D2F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 +#define D2F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 +#define D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 +#define D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 +#define D2F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff +#define D2F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define D2F4_ROOT_STATUS__PME_STATUS_MASK 0x10000 +#define D2F4_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define D2F4_ROOT_STATUS__PME_PENDING_MASK 0x20000 +#define D2F4_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 +#define D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 +#define D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 +#define D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 +#define D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define D2F4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define D2F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define D2F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define D2F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 +#define D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 +#define D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define D2F4_DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define D2F4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define D2F4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define D2F4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define D2F4_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 +#define D2F4_DEVICE_STATUS2__RESERVED__SHIFT 0x10 +#define D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define D2F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define D2F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define D2F4_LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define D2F4_LINK_CAP2__RESERVED__SHIFT 0x9 +#define D2F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define D2F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define D2F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define D2F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define D2F4_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define D2F4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define D2F4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define D2F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 +#define D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 +#define D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 +#define D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 +#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 +#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 +#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 +#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 +#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 +#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 +#define D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 +#define D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 +#define D2F4_SLOT_CAP2__RESERVED_MASK 0xffffffff +#define D2F4_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define D2F4_SLOT_CNTL2__RESERVED_MASK 0xffff +#define D2F4_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define D2F4_SLOT_STATUS2__RESERVED_MASK 0xffff0000 +#define D2F4_SLOT_STATUS2__RESERVED__SHIFT 0x10 +#define D2F4_MSI_CAP_LIST__CAP_ID_MASK 0xff +#define D2F4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F4_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 +#define D2F4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 +#define D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 +#define D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 +#define D2F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 +#define D2F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 +#define D2F4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 +#define D2F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 +#define D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 +#define D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 +#define D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define D2F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define D2F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define D2F4_MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define D2F4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define D2F4_SSID_CAP_LIST__CAP_ID_MASK 0xff +#define D2F4_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F4_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define D2F4_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 +#define D2F4_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define D2F4_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff +#define D2F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F4_MSI_MAP_CAP__EN_MASK 0x10000 +#define D2F4_MSI_MAP_CAP__EN__SHIFT 0x10 +#define D2F4_MSI_MAP_CAP__FIXD_MASK 0x20000 +#define D2F4_MSI_MAP_CAP__FIXD__SHIFT 0x11 +#define D2F4_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 +#define D2F4_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b +#define D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 +#define D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff +#define D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define D2F4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define D2F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define D2F4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define D2F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define D2F4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define D2F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define D2F4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define D2F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 +#define D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 +#define D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 +#define D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 +#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 +#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 +#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 +#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 +#define D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 +#define D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 +#define D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 +#define D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff +#define D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 +#define D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define D2F4_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define D2F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define D2F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define D2F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 +#define D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 +#define D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 +#define D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 +#define D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 +#define D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 +#define D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 +#define D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 +#define D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 +#define D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 +#define D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 +#define D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 +#define D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 +#define D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 +#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define D2F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define D2F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 +#define D2F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 +#define D2F4_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 +#define D2F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f +#define D2F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define D2F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define D2F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define D2F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define D2F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define D2F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f +#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 +#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff +#define D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define D2F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff +#define D2F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 +#define D2F5_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff +#define D2F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 +#define D2F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define D2F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define D2F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define D2F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define D2F5_PCIE_FC_P__PD_CREDITS_MASK 0xff +#define D2F5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define D2F5_PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define D2F5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define D2F5_PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define D2F5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define D2F5_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define D2F5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define D2F5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define D2F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define D2F5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define D2F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define D2F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 +#define D2F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 +#define D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 +#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 +#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define D2F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define D2F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 +#define D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 +#define D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define D2F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define D2F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 +#define D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 +#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 +#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 +#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 +#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 +#define D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 +#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 +#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 +#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 +#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 +#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 +#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define D2F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 +#define D2F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 +#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 +#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 +#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 +#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 +#define D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 +#define D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define D2F5_VENDOR_ID__VENDOR_ID_MASK 0xffff +#define D2F5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define D2F5_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 +#define D2F5_DEVICE_ID__DEVICE_ID__SHIFT 0x10 +#define D2F5_COMMAND__IO_ACCESS_EN_MASK 0x1 +#define D2F5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define D2F5_COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define D2F5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define D2F5_COMMAND__BUS_MASTER_EN_MASK 0x4 +#define D2F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define D2F5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define D2F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define D2F5_COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define D2F5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define D2F5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define D2F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define D2F5_COMMAND__AD_STEPPING_MASK 0x80 +#define D2F5_COMMAND__AD_STEPPING__SHIFT 0x7 +#define D2F5_COMMAND__SERR_EN_MASK 0x100 +#define D2F5_COMMAND__SERR_EN__SHIFT 0x8 +#define D2F5_COMMAND__FAST_B2B_EN_MASK 0x200 +#define D2F5_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define D2F5_COMMAND__INT_DIS_MASK 0x400 +#define D2F5_COMMAND__INT_DIS__SHIFT 0xa +#define D2F5_STATUS__INT_STATUS_MASK 0x80000 +#define D2F5_STATUS__INT_STATUS__SHIFT 0x13 +#define D2F5_STATUS__CAP_LIST_MASK 0x100000 +#define D2F5_STATUS__CAP_LIST__SHIFT 0x14 +#define D2F5_STATUS__PCI_66_EN_MASK 0x200000 +#define D2F5_STATUS__PCI_66_EN__SHIFT 0x15 +#define D2F5_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D2F5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D2F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D2F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D2F5_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D2F5_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D2F5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D2F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D2F5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D2F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D2F5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D2F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D2F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define D2F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e +#define D2F5_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D2F5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D2F5_REVISION_ID__MINOR_REV_ID_MASK 0xf +#define D2F5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define D2F5_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define D2F5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define D2F5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 +#define D2F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 +#define D2F5_SUB_CLASS__SUB_CLASS_MASK 0xff0000 +#define D2F5_SUB_CLASS__SUB_CLASS__SHIFT 0x10 +#define D2F5_BASE_CLASS__BASE_CLASS_MASK 0xff000000 +#define D2F5_BASE_CLASS__BASE_CLASS__SHIFT 0x18 +#define D2F5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define D2F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define D2F5_LATENCY__LATENCY_TIMER_MASK 0xff00 +#define D2F5_LATENCY__LATENCY_TIMER__SHIFT 0x8 +#define D2F5_HEADER__HEADER_TYPE_MASK 0x7f0000 +#define D2F5_HEADER__HEADER_TYPE__SHIFT 0x10 +#define D2F5_HEADER__DEVICE_TYPE_MASK 0x800000 +#define D2F5_HEADER__DEVICE_TYPE__SHIFT 0x17 +#define D2F5_BIST__BIST_COMP_MASK 0xf000000 +#define D2F5_BIST__BIST_COMP__SHIFT 0x18 +#define D2F5_BIST__BIST_STRT_MASK 0x40000000 +#define D2F5_BIST__BIST_STRT__SHIFT 0x1e +#define D2F5_BIST__BIST_CAP_MASK 0x80000000 +#define D2F5_BIST__BIST_CAP__SHIFT 0x1f +#define D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff +#define D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 +#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 +#define D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 +#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define D2F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf +#define D2F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define D2F5_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 +#define D2F5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 +#define D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define D2F5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 +#define D2F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define D2F5_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 +#define D2F5_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 +#define D2F5_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 +#define D2F5_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 +#define D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D2F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D2F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 +#define D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e +#define D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf +#define D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 +#define D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 +#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 +#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf +#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 +#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 +#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 +#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff +#define D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff +#define D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff +#define D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 +#define D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 +#define D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 +#define D2F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 +#define D2F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 +#define D2F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 +#define D2F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 +#define D2F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 +#define D2F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 +#define D2F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 +#define D2F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 +#define D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 +#define D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 +#define D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 +#define D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 +#define D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 +#define D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 +#define D2F5_CAP_PTR__CAP_PTR_MASK 0xff +#define D2F5_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define D2F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define D2F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define D2F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 +#define D2F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 +#define D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 +#define D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define D2F5_PMI_CAP_LIST__CAP_ID_MASK 0xff +#define D2F5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F5_PMI_CAP__VERSION_MASK 0x70000 +#define D2F5_PMI_CAP__VERSION__SHIFT 0x10 +#define D2F5_PMI_CAP__PME_CLOCK_MASK 0x80000 +#define D2F5_PMI_CAP__PME_CLOCK__SHIFT 0x13 +#define D2F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 +#define D2F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 +#define D2F5_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 +#define D2F5_PMI_CAP__AUX_CURRENT__SHIFT 0x16 +#define D2F5_PMI_CAP__D1_SUPPORT_MASK 0x2000000 +#define D2F5_PMI_CAP__D1_SUPPORT__SHIFT 0x19 +#define D2F5_PMI_CAP__D2_SUPPORT_MASK 0x4000000 +#define D2F5_PMI_CAP__D2_SUPPORT__SHIFT 0x1a +#define D2F5_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 +#define D2F5_PMI_CAP__PME_SUPPORT__SHIFT 0x1b +#define D2F5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define D2F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define D2F5_PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define D2F5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define D2F5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define D2F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define D2F5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define D2F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define D2F5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define D2F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define D2F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define D2F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define D2F5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define D2F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define D2F5_PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define D2F5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F5_PCIE_CAP__VERSION_MASK 0xf0000 +#define D2F5_PCIE_CAP__VERSION__SHIFT 0x10 +#define D2F5_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 +#define D2F5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 +#define D2F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 +#define D2F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 +#define D2F5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 +#define D2F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 +#define D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define D2F5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define D2F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define D2F5_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define D2F5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define D2F5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define D2F5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define D2F5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define D2F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define D2F5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define D2F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define D2F5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define D2F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define D2F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define D2F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define D2F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define D2F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define D2F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define D2F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define D2F5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define D2F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 +#define D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define D2F5_DEVICE_STATUS__CORR_ERR_MASK 0x10000 +#define D2F5_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 +#define D2F5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 +#define D2F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 +#define D2F5_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 +#define D2F5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 +#define D2F5_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 +#define D2F5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 +#define D2F5_DEVICE_STATUS__AUX_PWR_MASK 0x100000 +#define D2F5_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 +#define D2F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 +#define D2F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 +#define D2F5_LINK_CAP__LINK_SPEED_MASK 0xf +#define D2F5_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define D2F5_LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define D2F5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define D2F5_LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define D2F5_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define D2F5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define D2F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define D2F5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define D2F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define D2F5_LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define D2F5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define D2F5_LINK_CNTL__PM_CONTROL_MASK 0x3 +#define D2F5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define D2F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define D2F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define D2F5_LINK_CNTL__LINK_DIS_MASK 0x10 +#define D2F5_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define D2F5_LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define D2F5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define D2F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define D2F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define D2F5_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define D2F5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define D2F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 +#define D2F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 +#define D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 +#define D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 +#define D2F5_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 +#define D2F5_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b +#define D2F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 +#define D2F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c +#define D2F5_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 +#define D2F5_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d +#define D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 +#define D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e +#define D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 +#define D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f +#define D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 +#define D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 +#define D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define D2F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 +#define D2F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 +#define D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 +#define D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define D2F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 +#define D2F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define D2F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 +#define D2F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 +#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 +#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 +#define D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 +#define D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 +#define D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 +#define D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 +#define D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 +#define D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 +#define D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 +#define D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define D2F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 +#define D2F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 +#define D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 +#define D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 +#define D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 +#define D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 +#define D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 +#define D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 +#define D2F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 +#define D2F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 +#define D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 +#define D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 +#define D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 +#define D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 +#define D2F5_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 +#define D2F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 +#define D2F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 +#define D2F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 +#define D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 +#define D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 +#define D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 +#define D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 +#define D2F5_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 +#define D2F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 +#define D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 +#define D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 +#define D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 +#define D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define D2F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 +#define D2F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 +#define D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 +#define D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 +#define D2F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff +#define D2F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define D2F5_ROOT_STATUS__PME_STATUS_MASK 0x10000 +#define D2F5_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define D2F5_ROOT_STATUS__PME_PENDING_MASK 0x20000 +#define D2F5_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 +#define D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 +#define D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 +#define D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 +#define D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define D2F5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define D2F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define D2F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define D2F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 +#define D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 +#define D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define D2F5_DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define D2F5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define D2F5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define D2F5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define D2F5_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 +#define D2F5_DEVICE_STATUS2__RESERVED__SHIFT 0x10 +#define D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define D2F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define D2F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define D2F5_LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define D2F5_LINK_CAP2__RESERVED__SHIFT 0x9 +#define D2F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define D2F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define D2F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define D2F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define D2F5_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define D2F5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define D2F5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define D2F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 +#define D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 +#define D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 +#define D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 +#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 +#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 +#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 +#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 +#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 +#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 +#define D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 +#define D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 +#define D2F5_SLOT_CAP2__RESERVED_MASK 0xffffffff +#define D2F5_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define D2F5_SLOT_CNTL2__RESERVED_MASK 0xffff +#define D2F5_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define D2F5_SLOT_STATUS2__RESERVED_MASK 0xffff0000 +#define D2F5_SLOT_STATUS2__RESERVED__SHIFT 0x10 +#define D2F5_MSI_CAP_LIST__CAP_ID_MASK 0xff +#define D2F5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F5_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 +#define D2F5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 +#define D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 +#define D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 +#define D2F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 +#define D2F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 +#define D2F5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 +#define D2F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 +#define D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 +#define D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 +#define D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define D2F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define D2F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define D2F5_MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define D2F5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define D2F5_SSID_CAP_LIST__CAP_ID_MASK 0xff +#define D2F5_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F5_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define D2F5_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 +#define D2F5_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define D2F5_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff +#define D2F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D2F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D2F5_MSI_MAP_CAP__EN_MASK 0x10000 +#define D2F5_MSI_MAP_CAP__EN__SHIFT 0x10 +#define D2F5_MSI_MAP_CAP__FIXD_MASK 0x20000 +#define D2F5_MSI_MAP_CAP__FIXD__SHIFT 0x11 +#define D2F5_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 +#define D2F5_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b +#define D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 +#define D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff +#define D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define D2F5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define D2F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define D2F5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define D2F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define D2F5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define D2F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define D2F5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define D2F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 +#define D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 +#define D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 +#define D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 +#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 +#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 +#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 +#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 +#define D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 +#define D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 +#define D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 +#define D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff +#define D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 +#define D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define D2F5_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define D2F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define D2F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define D2F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 +#define D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 +#define D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 +#define D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 +#define D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 +#define D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 +#define D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 +#define D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 +#define D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 +#define D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 +#define D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 +#define D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 +#define D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 +#define D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 +#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D2F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define D2F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define D2F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 +#define D2F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 +#define D2F5_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 +#define D2F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f +#define D2F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define D2F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define D2F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define D2F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define D2F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define D2F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f +#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 +#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff +#define D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define D3F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff +#define D3F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 +#define D3F1_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff +#define D3F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 +#define D3F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define D3F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define D3F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define D3F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define D3F1_PCIE_FC_P__PD_CREDITS_MASK 0xff +#define D3F1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define D3F1_PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define D3F1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define D3F1_PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define D3F1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define D3F1_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define D3F1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define D3F1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define D3F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define D3F1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define D3F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define D3F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 +#define D3F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 +#define D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 +#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 +#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define D3F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define D3F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 +#define D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 +#define D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define D3F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define D3F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 +#define D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 +#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 +#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 +#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 +#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 +#define D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 +#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 +#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 +#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 +#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 +#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 +#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define D3F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 +#define D3F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 +#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 +#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 +#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 +#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 +#define D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 +#define D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define D3F1_VENDOR_ID__VENDOR_ID_MASK 0xffff +#define D3F1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define D3F1_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 +#define D3F1_DEVICE_ID__DEVICE_ID__SHIFT 0x10 +#define D3F1_COMMAND__IO_ACCESS_EN_MASK 0x1 +#define D3F1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define D3F1_COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define D3F1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define D3F1_COMMAND__BUS_MASTER_EN_MASK 0x4 +#define D3F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define D3F1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define D3F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define D3F1_COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define D3F1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define D3F1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define D3F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define D3F1_COMMAND__AD_STEPPING_MASK 0x80 +#define D3F1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define D3F1_COMMAND__SERR_EN_MASK 0x100 +#define D3F1_COMMAND__SERR_EN__SHIFT 0x8 +#define D3F1_COMMAND__FAST_B2B_EN_MASK 0x200 +#define D3F1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define D3F1_COMMAND__INT_DIS_MASK 0x400 +#define D3F1_COMMAND__INT_DIS__SHIFT 0xa +#define D3F1_STATUS__INT_STATUS_MASK 0x80000 +#define D3F1_STATUS__INT_STATUS__SHIFT 0x13 +#define D3F1_STATUS__CAP_LIST_MASK 0x100000 +#define D3F1_STATUS__CAP_LIST__SHIFT 0x14 +#define D3F1_STATUS__PCI_66_EN_MASK 0x200000 +#define D3F1_STATUS__PCI_66_EN__SHIFT 0x15 +#define D3F1_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D3F1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D3F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D3F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D3F1_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D3F1_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D3F1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D3F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D3F1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D3F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D3F1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D3F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D3F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define D3F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e +#define D3F1_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D3F1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D3F1_REVISION_ID__MINOR_REV_ID_MASK 0xf +#define D3F1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define D3F1_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define D3F1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define D3F1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 +#define D3F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 +#define D3F1_SUB_CLASS__SUB_CLASS_MASK 0xff0000 +#define D3F1_SUB_CLASS__SUB_CLASS__SHIFT 0x10 +#define D3F1_BASE_CLASS__BASE_CLASS_MASK 0xff000000 +#define D3F1_BASE_CLASS__BASE_CLASS__SHIFT 0x18 +#define D3F1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define D3F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define D3F1_LATENCY__LATENCY_TIMER_MASK 0xff00 +#define D3F1_LATENCY__LATENCY_TIMER__SHIFT 0x8 +#define D3F1_HEADER__HEADER_TYPE_MASK 0x7f0000 +#define D3F1_HEADER__HEADER_TYPE__SHIFT 0x10 +#define D3F1_HEADER__DEVICE_TYPE_MASK 0x800000 +#define D3F1_HEADER__DEVICE_TYPE__SHIFT 0x17 +#define D3F1_BIST__BIST_COMP_MASK 0xf000000 +#define D3F1_BIST__BIST_COMP__SHIFT 0x18 +#define D3F1_BIST__BIST_STRT_MASK 0x40000000 +#define D3F1_BIST__BIST_STRT__SHIFT 0x1e +#define D3F1_BIST__BIST_CAP_MASK 0x80000000 +#define D3F1_BIST__BIST_CAP__SHIFT 0x1f +#define D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff +#define D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 +#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 +#define D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 +#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define D3F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf +#define D3F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define D3F1_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 +#define D3F1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 +#define D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define D3F1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 +#define D3F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define D3F1_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 +#define D3F1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 +#define D3F1_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 +#define D3F1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 +#define D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D3F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D3F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 +#define D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e +#define D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf +#define D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 +#define D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 +#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 +#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf +#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 +#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 +#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 +#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff +#define D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff +#define D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff +#define D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 +#define D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 +#define D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 +#define D3F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 +#define D3F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 +#define D3F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 +#define D3F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 +#define D3F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 +#define D3F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 +#define D3F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 +#define D3F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 +#define D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 +#define D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 +#define D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 +#define D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 +#define D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 +#define D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 +#define D3F1_CAP_PTR__CAP_PTR_MASK 0xff +#define D3F1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define D3F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define D3F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define D3F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 +#define D3F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 +#define D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 +#define D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define D3F1_PMI_CAP_LIST__CAP_ID_MASK 0xff +#define D3F1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F1_PMI_CAP__VERSION_MASK 0x70000 +#define D3F1_PMI_CAP__VERSION__SHIFT 0x10 +#define D3F1_PMI_CAP__PME_CLOCK_MASK 0x80000 +#define D3F1_PMI_CAP__PME_CLOCK__SHIFT 0x13 +#define D3F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 +#define D3F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 +#define D3F1_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 +#define D3F1_PMI_CAP__AUX_CURRENT__SHIFT 0x16 +#define D3F1_PMI_CAP__D1_SUPPORT_MASK 0x2000000 +#define D3F1_PMI_CAP__D1_SUPPORT__SHIFT 0x19 +#define D3F1_PMI_CAP__D2_SUPPORT_MASK 0x4000000 +#define D3F1_PMI_CAP__D2_SUPPORT__SHIFT 0x1a +#define D3F1_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 +#define D3F1_PMI_CAP__PME_SUPPORT__SHIFT 0x1b +#define D3F1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define D3F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define D3F1_PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define D3F1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define D3F1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define D3F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define D3F1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define D3F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define D3F1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define D3F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define D3F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define D3F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define D3F1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define D3F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define D3F1_PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define D3F1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F1_PCIE_CAP__VERSION_MASK 0xf0000 +#define D3F1_PCIE_CAP__VERSION__SHIFT 0x10 +#define D3F1_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 +#define D3F1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 +#define D3F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 +#define D3F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 +#define D3F1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 +#define D3F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 +#define D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define D3F1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define D3F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define D3F1_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define D3F1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define D3F1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define D3F1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define D3F1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define D3F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define D3F1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define D3F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define D3F1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define D3F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define D3F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define D3F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define D3F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define D3F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define D3F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define D3F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define D3F1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define D3F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 +#define D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define D3F1_DEVICE_STATUS__CORR_ERR_MASK 0x10000 +#define D3F1_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 +#define D3F1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 +#define D3F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 +#define D3F1_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 +#define D3F1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 +#define D3F1_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 +#define D3F1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 +#define D3F1_DEVICE_STATUS__AUX_PWR_MASK 0x100000 +#define D3F1_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 +#define D3F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 +#define D3F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 +#define D3F1_LINK_CAP__LINK_SPEED_MASK 0xf +#define D3F1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define D3F1_LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define D3F1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define D3F1_LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define D3F1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define D3F1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define D3F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define D3F1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define D3F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define D3F1_LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define D3F1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define D3F1_LINK_CNTL__PM_CONTROL_MASK 0x3 +#define D3F1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define D3F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define D3F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define D3F1_LINK_CNTL__LINK_DIS_MASK 0x10 +#define D3F1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define D3F1_LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define D3F1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define D3F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define D3F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define D3F1_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define D3F1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define D3F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 +#define D3F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 +#define D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 +#define D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 +#define D3F1_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 +#define D3F1_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b +#define D3F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 +#define D3F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c +#define D3F1_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 +#define D3F1_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d +#define D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 +#define D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e +#define D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 +#define D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f +#define D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 +#define D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 +#define D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define D3F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 +#define D3F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 +#define D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 +#define D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define D3F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 +#define D3F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define D3F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 +#define D3F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 +#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 +#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 +#define D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 +#define D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 +#define D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 +#define D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 +#define D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 +#define D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 +#define D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 +#define D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define D3F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 +#define D3F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 +#define D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 +#define D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 +#define D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 +#define D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 +#define D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 +#define D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 +#define D3F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 +#define D3F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 +#define D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 +#define D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 +#define D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 +#define D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 +#define D3F1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 +#define D3F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 +#define D3F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 +#define D3F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 +#define D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 +#define D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 +#define D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 +#define D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 +#define D3F1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 +#define D3F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 +#define D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 +#define D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 +#define D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 +#define D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define D3F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 +#define D3F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 +#define D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 +#define D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 +#define D3F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff +#define D3F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define D3F1_ROOT_STATUS__PME_STATUS_MASK 0x10000 +#define D3F1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define D3F1_ROOT_STATUS__PME_PENDING_MASK 0x20000 +#define D3F1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 +#define D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 +#define D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 +#define D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 +#define D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define D3F1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define D3F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define D3F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define D3F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 +#define D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 +#define D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define D3F1_DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define D3F1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define D3F1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define D3F1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define D3F1_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 +#define D3F1_DEVICE_STATUS2__RESERVED__SHIFT 0x10 +#define D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define D3F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define D3F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define D3F1_LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define D3F1_LINK_CAP2__RESERVED__SHIFT 0x9 +#define D3F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define D3F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define D3F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define D3F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define D3F1_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define D3F1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define D3F1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define D3F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 +#define D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 +#define D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 +#define D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 +#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 +#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 +#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 +#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 +#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 +#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 +#define D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 +#define D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 +#define D3F1_SLOT_CAP2__RESERVED_MASK 0xffffffff +#define D3F1_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define D3F1_SLOT_CNTL2__RESERVED_MASK 0xffff +#define D3F1_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define D3F1_SLOT_STATUS2__RESERVED_MASK 0xffff0000 +#define D3F1_SLOT_STATUS2__RESERVED__SHIFT 0x10 +#define D3F1_MSI_CAP_LIST__CAP_ID_MASK 0xff +#define D3F1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F1_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 +#define D3F1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 +#define D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 +#define D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 +#define D3F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 +#define D3F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 +#define D3F1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 +#define D3F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 +#define D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 +#define D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 +#define D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define D3F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define D3F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define D3F1_MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define D3F1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define D3F1_SSID_CAP_LIST__CAP_ID_MASK 0xff +#define D3F1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define D3F1_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 +#define D3F1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define D3F1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff +#define D3F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F1_MSI_MAP_CAP__EN_MASK 0x10000 +#define D3F1_MSI_MAP_CAP__EN__SHIFT 0x10 +#define D3F1_MSI_MAP_CAP__FIXD_MASK 0x20000 +#define D3F1_MSI_MAP_CAP__FIXD__SHIFT 0x11 +#define D3F1_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 +#define D3F1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b +#define D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 +#define D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff +#define D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define D3F1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define D3F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define D3F1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define D3F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define D3F1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define D3F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define D3F1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define D3F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 +#define D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 +#define D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 +#define D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 +#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 +#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 +#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 +#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 +#define D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 +#define D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 +#define D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 +#define D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff +#define D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 +#define D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define D3F1_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define D3F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define D3F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define D3F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 +#define D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 +#define D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 +#define D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 +#define D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 +#define D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 +#define D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 +#define D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 +#define D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 +#define D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 +#define D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 +#define D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 +#define D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 +#define D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 +#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define D3F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define D3F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 +#define D3F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 +#define D3F1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 +#define D3F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f +#define D3F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define D3F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define D3F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define D3F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define D3F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define D3F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f +#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 +#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff +#define D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define D3F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff +#define D3F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 +#define D3F2_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff +#define D3F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 +#define D3F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define D3F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define D3F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define D3F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define D3F2_PCIE_FC_P__PD_CREDITS_MASK 0xff +#define D3F2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define D3F2_PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define D3F2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define D3F2_PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define D3F2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define D3F2_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define D3F2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define D3F2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define D3F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define D3F2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define D3F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define D3F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 +#define D3F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 +#define D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 +#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 +#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define D3F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define D3F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 +#define D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 +#define D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define D3F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define D3F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 +#define D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 +#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 +#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 +#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 +#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 +#define D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 +#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 +#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 +#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 +#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 +#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 +#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define D3F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 +#define D3F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 +#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 +#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 +#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 +#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 +#define D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 +#define D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define D3F2_VENDOR_ID__VENDOR_ID_MASK 0xffff +#define D3F2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define D3F2_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 +#define D3F2_DEVICE_ID__DEVICE_ID__SHIFT 0x10 +#define D3F2_COMMAND__IO_ACCESS_EN_MASK 0x1 +#define D3F2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define D3F2_COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define D3F2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define D3F2_COMMAND__BUS_MASTER_EN_MASK 0x4 +#define D3F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define D3F2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define D3F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define D3F2_COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define D3F2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define D3F2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define D3F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define D3F2_COMMAND__AD_STEPPING_MASK 0x80 +#define D3F2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define D3F2_COMMAND__SERR_EN_MASK 0x100 +#define D3F2_COMMAND__SERR_EN__SHIFT 0x8 +#define D3F2_COMMAND__FAST_B2B_EN_MASK 0x200 +#define D3F2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define D3F2_COMMAND__INT_DIS_MASK 0x400 +#define D3F2_COMMAND__INT_DIS__SHIFT 0xa +#define D3F2_STATUS__INT_STATUS_MASK 0x80000 +#define D3F2_STATUS__INT_STATUS__SHIFT 0x13 +#define D3F2_STATUS__CAP_LIST_MASK 0x100000 +#define D3F2_STATUS__CAP_LIST__SHIFT 0x14 +#define D3F2_STATUS__PCI_66_EN_MASK 0x200000 +#define D3F2_STATUS__PCI_66_EN__SHIFT 0x15 +#define D3F2_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D3F2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D3F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D3F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D3F2_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D3F2_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D3F2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D3F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D3F2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D3F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D3F2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D3F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D3F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define D3F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e +#define D3F2_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D3F2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D3F2_REVISION_ID__MINOR_REV_ID_MASK 0xf +#define D3F2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define D3F2_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define D3F2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define D3F2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 +#define D3F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 +#define D3F2_SUB_CLASS__SUB_CLASS_MASK 0xff0000 +#define D3F2_SUB_CLASS__SUB_CLASS__SHIFT 0x10 +#define D3F2_BASE_CLASS__BASE_CLASS_MASK 0xff000000 +#define D3F2_BASE_CLASS__BASE_CLASS__SHIFT 0x18 +#define D3F2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define D3F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define D3F2_LATENCY__LATENCY_TIMER_MASK 0xff00 +#define D3F2_LATENCY__LATENCY_TIMER__SHIFT 0x8 +#define D3F2_HEADER__HEADER_TYPE_MASK 0x7f0000 +#define D3F2_HEADER__HEADER_TYPE__SHIFT 0x10 +#define D3F2_HEADER__DEVICE_TYPE_MASK 0x800000 +#define D3F2_HEADER__DEVICE_TYPE__SHIFT 0x17 +#define D3F2_BIST__BIST_COMP_MASK 0xf000000 +#define D3F2_BIST__BIST_COMP__SHIFT 0x18 +#define D3F2_BIST__BIST_STRT_MASK 0x40000000 +#define D3F2_BIST__BIST_STRT__SHIFT 0x1e +#define D3F2_BIST__BIST_CAP_MASK 0x80000000 +#define D3F2_BIST__BIST_CAP__SHIFT 0x1f +#define D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff +#define D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 +#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 +#define D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 +#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define D3F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf +#define D3F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define D3F2_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 +#define D3F2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 +#define D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define D3F2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 +#define D3F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define D3F2_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 +#define D3F2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 +#define D3F2_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 +#define D3F2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 +#define D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D3F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D3F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 +#define D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e +#define D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf +#define D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 +#define D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 +#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 +#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf +#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 +#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 +#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 +#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff +#define D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff +#define D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff +#define D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 +#define D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 +#define D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 +#define D3F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 +#define D3F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 +#define D3F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 +#define D3F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 +#define D3F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 +#define D3F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 +#define D3F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 +#define D3F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 +#define D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 +#define D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 +#define D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 +#define D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 +#define D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 +#define D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 +#define D3F2_CAP_PTR__CAP_PTR_MASK 0xff +#define D3F2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define D3F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define D3F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define D3F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 +#define D3F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 +#define D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 +#define D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define D3F2_PMI_CAP_LIST__CAP_ID_MASK 0xff +#define D3F2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F2_PMI_CAP__VERSION_MASK 0x70000 +#define D3F2_PMI_CAP__VERSION__SHIFT 0x10 +#define D3F2_PMI_CAP__PME_CLOCK_MASK 0x80000 +#define D3F2_PMI_CAP__PME_CLOCK__SHIFT 0x13 +#define D3F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 +#define D3F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 +#define D3F2_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 +#define D3F2_PMI_CAP__AUX_CURRENT__SHIFT 0x16 +#define D3F2_PMI_CAP__D1_SUPPORT_MASK 0x2000000 +#define D3F2_PMI_CAP__D1_SUPPORT__SHIFT 0x19 +#define D3F2_PMI_CAP__D2_SUPPORT_MASK 0x4000000 +#define D3F2_PMI_CAP__D2_SUPPORT__SHIFT 0x1a +#define D3F2_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 +#define D3F2_PMI_CAP__PME_SUPPORT__SHIFT 0x1b +#define D3F2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define D3F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define D3F2_PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define D3F2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define D3F2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define D3F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define D3F2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define D3F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define D3F2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define D3F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define D3F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define D3F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define D3F2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define D3F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define D3F2_PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define D3F2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F2_PCIE_CAP__VERSION_MASK 0xf0000 +#define D3F2_PCIE_CAP__VERSION__SHIFT 0x10 +#define D3F2_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 +#define D3F2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 +#define D3F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 +#define D3F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 +#define D3F2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 +#define D3F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 +#define D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define D3F2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define D3F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define D3F2_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define D3F2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define D3F2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define D3F2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define D3F2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define D3F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define D3F2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define D3F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define D3F2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define D3F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define D3F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define D3F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define D3F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define D3F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define D3F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define D3F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define D3F2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define D3F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 +#define D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define D3F2_DEVICE_STATUS__CORR_ERR_MASK 0x10000 +#define D3F2_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 +#define D3F2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 +#define D3F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 +#define D3F2_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 +#define D3F2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 +#define D3F2_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 +#define D3F2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 +#define D3F2_DEVICE_STATUS__AUX_PWR_MASK 0x100000 +#define D3F2_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 +#define D3F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 +#define D3F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 +#define D3F2_LINK_CAP__LINK_SPEED_MASK 0xf +#define D3F2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define D3F2_LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define D3F2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define D3F2_LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define D3F2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define D3F2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define D3F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define D3F2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define D3F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define D3F2_LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define D3F2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define D3F2_LINK_CNTL__PM_CONTROL_MASK 0x3 +#define D3F2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define D3F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define D3F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define D3F2_LINK_CNTL__LINK_DIS_MASK 0x10 +#define D3F2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define D3F2_LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define D3F2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define D3F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define D3F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define D3F2_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define D3F2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define D3F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 +#define D3F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 +#define D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 +#define D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 +#define D3F2_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 +#define D3F2_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b +#define D3F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 +#define D3F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c +#define D3F2_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 +#define D3F2_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d +#define D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 +#define D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e +#define D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 +#define D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f +#define D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 +#define D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 +#define D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define D3F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 +#define D3F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 +#define D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 +#define D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define D3F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 +#define D3F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define D3F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 +#define D3F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 +#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 +#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 +#define D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 +#define D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 +#define D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 +#define D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 +#define D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 +#define D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 +#define D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 +#define D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define D3F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 +#define D3F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 +#define D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 +#define D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 +#define D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 +#define D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 +#define D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 +#define D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 +#define D3F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 +#define D3F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 +#define D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 +#define D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 +#define D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 +#define D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 +#define D3F2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 +#define D3F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 +#define D3F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 +#define D3F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 +#define D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 +#define D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 +#define D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 +#define D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 +#define D3F2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 +#define D3F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 +#define D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 +#define D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 +#define D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 +#define D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define D3F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 +#define D3F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 +#define D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 +#define D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 +#define D3F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff +#define D3F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define D3F2_ROOT_STATUS__PME_STATUS_MASK 0x10000 +#define D3F2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define D3F2_ROOT_STATUS__PME_PENDING_MASK 0x20000 +#define D3F2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 +#define D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 +#define D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 +#define D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 +#define D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define D3F2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define D3F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define D3F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define D3F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 +#define D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 +#define D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define D3F2_DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define D3F2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define D3F2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define D3F2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define D3F2_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 +#define D3F2_DEVICE_STATUS2__RESERVED__SHIFT 0x10 +#define D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define D3F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define D3F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define D3F2_LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define D3F2_LINK_CAP2__RESERVED__SHIFT 0x9 +#define D3F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define D3F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define D3F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define D3F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define D3F2_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define D3F2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define D3F2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define D3F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 +#define D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 +#define D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 +#define D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 +#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 +#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 +#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 +#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 +#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 +#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 +#define D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 +#define D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 +#define D3F2_SLOT_CAP2__RESERVED_MASK 0xffffffff +#define D3F2_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define D3F2_SLOT_CNTL2__RESERVED_MASK 0xffff +#define D3F2_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define D3F2_SLOT_STATUS2__RESERVED_MASK 0xffff0000 +#define D3F2_SLOT_STATUS2__RESERVED__SHIFT 0x10 +#define D3F2_MSI_CAP_LIST__CAP_ID_MASK 0xff +#define D3F2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F2_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 +#define D3F2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 +#define D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 +#define D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 +#define D3F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 +#define D3F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 +#define D3F2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 +#define D3F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 +#define D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 +#define D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 +#define D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define D3F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define D3F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define D3F2_MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define D3F2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define D3F2_SSID_CAP_LIST__CAP_ID_MASK 0xff +#define D3F2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define D3F2_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 +#define D3F2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define D3F2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff +#define D3F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F2_MSI_MAP_CAP__EN_MASK 0x10000 +#define D3F2_MSI_MAP_CAP__EN__SHIFT 0x10 +#define D3F2_MSI_MAP_CAP__FIXD_MASK 0x20000 +#define D3F2_MSI_MAP_CAP__FIXD__SHIFT 0x11 +#define D3F2_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 +#define D3F2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b +#define D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 +#define D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff +#define D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define D3F2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define D3F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define D3F2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define D3F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define D3F2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define D3F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define D3F2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define D3F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 +#define D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 +#define D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 +#define D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 +#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 +#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 +#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 +#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 +#define D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 +#define D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 +#define D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 +#define D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff +#define D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 +#define D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define D3F2_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define D3F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define D3F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define D3F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 +#define D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 +#define D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 +#define D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 +#define D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 +#define D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 +#define D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 +#define D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 +#define D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 +#define D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 +#define D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 +#define D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 +#define D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 +#define D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 +#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define D3F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define D3F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 +#define D3F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 +#define D3F2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 +#define D3F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f +#define D3F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define D3F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define D3F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define D3F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define D3F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define D3F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f +#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 +#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff +#define D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define D3F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff +#define D3F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 +#define D3F3_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff +#define D3F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 +#define D3F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define D3F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define D3F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define D3F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define D3F3_PCIE_FC_P__PD_CREDITS_MASK 0xff +#define D3F3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define D3F3_PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define D3F3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define D3F3_PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define D3F3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define D3F3_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define D3F3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define D3F3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define D3F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define D3F3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define D3F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define D3F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 +#define D3F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 +#define D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 +#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 +#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define D3F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define D3F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 +#define D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 +#define D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define D3F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define D3F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 +#define D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 +#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 +#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 +#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 +#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 +#define D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 +#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 +#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 +#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 +#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 +#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 +#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define D3F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 +#define D3F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 +#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 +#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 +#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 +#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 +#define D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 +#define D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define D3F3_VENDOR_ID__VENDOR_ID_MASK 0xffff +#define D3F3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define D3F3_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 +#define D3F3_DEVICE_ID__DEVICE_ID__SHIFT 0x10 +#define D3F3_COMMAND__IO_ACCESS_EN_MASK 0x1 +#define D3F3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define D3F3_COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define D3F3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define D3F3_COMMAND__BUS_MASTER_EN_MASK 0x4 +#define D3F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define D3F3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define D3F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define D3F3_COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define D3F3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define D3F3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define D3F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define D3F3_COMMAND__AD_STEPPING_MASK 0x80 +#define D3F3_COMMAND__AD_STEPPING__SHIFT 0x7 +#define D3F3_COMMAND__SERR_EN_MASK 0x100 +#define D3F3_COMMAND__SERR_EN__SHIFT 0x8 +#define D3F3_COMMAND__FAST_B2B_EN_MASK 0x200 +#define D3F3_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define D3F3_COMMAND__INT_DIS_MASK 0x400 +#define D3F3_COMMAND__INT_DIS__SHIFT 0xa +#define D3F3_STATUS__INT_STATUS_MASK 0x80000 +#define D3F3_STATUS__INT_STATUS__SHIFT 0x13 +#define D3F3_STATUS__CAP_LIST_MASK 0x100000 +#define D3F3_STATUS__CAP_LIST__SHIFT 0x14 +#define D3F3_STATUS__PCI_66_EN_MASK 0x200000 +#define D3F3_STATUS__PCI_66_EN__SHIFT 0x15 +#define D3F3_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D3F3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D3F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D3F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D3F3_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D3F3_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D3F3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D3F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D3F3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D3F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D3F3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D3F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D3F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define D3F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e +#define D3F3_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D3F3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D3F3_REVISION_ID__MINOR_REV_ID_MASK 0xf +#define D3F3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define D3F3_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define D3F3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define D3F3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 +#define D3F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 +#define D3F3_SUB_CLASS__SUB_CLASS_MASK 0xff0000 +#define D3F3_SUB_CLASS__SUB_CLASS__SHIFT 0x10 +#define D3F3_BASE_CLASS__BASE_CLASS_MASK 0xff000000 +#define D3F3_BASE_CLASS__BASE_CLASS__SHIFT 0x18 +#define D3F3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define D3F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define D3F3_LATENCY__LATENCY_TIMER_MASK 0xff00 +#define D3F3_LATENCY__LATENCY_TIMER__SHIFT 0x8 +#define D3F3_HEADER__HEADER_TYPE_MASK 0x7f0000 +#define D3F3_HEADER__HEADER_TYPE__SHIFT 0x10 +#define D3F3_HEADER__DEVICE_TYPE_MASK 0x800000 +#define D3F3_HEADER__DEVICE_TYPE__SHIFT 0x17 +#define D3F3_BIST__BIST_COMP_MASK 0xf000000 +#define D3F3_BIST__BIST_COMP__SHIFT 0x18 +#define D3F3_BIST__BIST_STRT_MASK 0x40000000 +#define D3F3_BIST__BIST_STRT__SHIFT 0x1e +#define D3F3_BIST__BIST_CAP_MASK 0x80000000 +#define D3F3_BIST__BIST_CAP__SHIFT 0x1f +#define D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff +#define D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 +#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 +#define D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 +#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define D3F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf +#define D3F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define D3F3_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 +#define D3F3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 +#define D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define D3F3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 +#define D3F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define D3F3_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 +#define D3F3_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 +#define D3F3_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 +#define D3F3_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 +#define D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D3F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D3F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 +#define D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e +#define D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf +#define D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 +#define D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 +#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 +#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf +#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 +#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 +#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 +#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff +#define D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff +#define D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff +#define D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 +#define D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 +#define D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 +#define D3F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 +#define D3F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 +#define D3F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 +#define D3F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 +#define D3F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 +#define D3F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 +#define D3F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 +#define D3F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 +#define D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 +#define D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 +#define D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 +#define D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 +#define D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 +#define D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 +#define D3F3_CAP_PTR__CAP_PTR_MASK 0xff +#define D3F3_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define D3F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define D3F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define D3F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 +#define D3F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 +#define D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 +#define D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define D3F3_PMI_CAP_LIST__CAP_ID_MASK 0xff +#define D3F3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F3_PMI_CAP__VERSION_MASK 0x70000 +#define D3F3_PMI_CAP__VERSION__SHIFT 0x10 +#define D3F3_PMI_CAP__PME_CLOCK_MASK 0x80000 +#define D3F3_PMI_CAP__PME_CLOCK__SHIFT 0x13 +#define D3F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 +#define D3F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 +#define D3F3_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 +#define D3F3_PMI_CAP__AUX_CURRENT__SHIFT 0x16 +#define D3F3_PMI_CAP__D1_SUPPORT_MASK 0x2000000 +#define D3F3_PMI_CAP__D1_SUPPORT__SHIFT 0x19 +#define D3F3_PMI_CAP__D2_SUPPORT_MASK 0x4000000 +#define D3F3_PMI_CAP__D2_SUPPORT__SHIFT 0x1a +#define D3F3_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 +#define D3F3_PMI_CAP__PME_SUPPORT__SHIFT 0x1b +#define D3F3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define D3F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define D3F3_PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define D3F3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define D3F3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define D3F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define D3F3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define D3F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define D3F3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define D3F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define D3F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define D3F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define D3F3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define D3F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define D3F3_PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define D3F3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F3_PCIE_CAP__VERSION_MASK 0xf0000 +#define D3F3_PCIE_CAP__VERSION__SHIFT 0x10 +#define D3F3_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 +#define D3F3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 +#define D3F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 +#define D3F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 +#define D3F3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 +#define D3F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 +#define D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define D3F3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define D3F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define D3F3_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define D3F3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define D3F3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define D3F3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define D3F3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define D3F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define D3F3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define D3F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define D3F3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define D3F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define D3F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define D3F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define D3F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define D3F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define D3F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define D3F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define D3F3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define D3F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 +#define D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define D3F3_DEVICE_STATUS__CORR_ERR_MASK 0x10000 +#define D3F3_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 +#define D3F3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 +#define D3F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 +#define D3F3_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 +#define D3F3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 +#define D3F3_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 +#define D3F3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 +#define D3F3_DEVICE_STATUS__AUX_PWR_MASK 0x100000 +#define D3F3_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 +#define D3F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 +#define D3F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 +#define D3F3_LINK_CAP__LINK_SPEED_MASK 0xf +#define D3F3_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define D3F3_LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define D3F3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define D3F3_LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define D3F3_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define D3F3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define D3F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define D3F3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define D3F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define D3F3_LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define D3F3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define D3F3_LINK_CNTL__PM_CONTROL_MASK 0x3 +#define D3F3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define D3F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define D3F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define D3F3_LINK_CNTL__LINK_DIS_MASK 0x10 +#define D3F3_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define D3F3_LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define D3F3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define D3F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define D3F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define D3F3_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define D3F3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define D3F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 +#define D3F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 +#define D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 +#define D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 +#define D3F3_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 +#define D3F3_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b +#define D3F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 +#define D3F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c +#define D3F3_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 +#define D3F3_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d +#define D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 +#define D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e +#define D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 +#define D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f +#define D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 +#define D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 +#define D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define D3F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 +#define D3F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 +#define D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 +#define D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define D3F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 +#define D3F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define D3F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 +#define D3F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 +#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 +#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 +#define D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 +#define D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 +#define D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 +#define D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 +#define D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 +#define D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 +#define D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 +#define D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define D3F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 +#define D3F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 +#define D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 +#define D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 +#define D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 +#define D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 +#define D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 +#define D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 +#define D3F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 +#define D3F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 +#define D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 +#define D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 +#define D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 +#define D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 +#define D3F3_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 +#define D3F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 +#define D3F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 +#define D3F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 +#define D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 +#define D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 +#define D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 +#define D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 +#define D3F3_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 +#define D3F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 +#define D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 +#define D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 +#define D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 +#define D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define D3F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 +#define D3F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 +#define D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 +#define D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 +#define D3F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff +#define D3F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define D3F3_ROOT_STATUS__PME_STATUS_MASK 0x10000 +#define D3F3_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define D3F3_ROOT_STATUS__PME_PENDING_MASK 0x20000 +#define D3F3_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 +#define D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 +#define D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 +#define D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 +#define D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define D3F3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define D3F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define D3F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define D3F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 +#define D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 +#define D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define D3F3_DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define D3F3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define D3F3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define D3F3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define D3F3_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 +#define D3F3_DEVICE_STATUS2__RESERVED__SHIFT 0x10 +#define D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define D3F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define D3F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define D3F3_LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define D3F3_LINK_CAP2__RESERVED__SHIFT 0x9 +#define D3F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define D3F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define D3F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define D3F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define D3F3_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define D3F3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define D3F3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define D3F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 +#define D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 +#define D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 +#define D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 +#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 +#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 +#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 +#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 +#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 +#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 +#define D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 +#define D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 +#define D3F3_SLOT_CAP2__RESERVED_MASK 0xffffffff +#define D3F3_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define D3F3_SLOT_CNTL2__RESERVED_MASK 0xffff +#define D3F3_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define D3F3_SLOT_STATUS2__RESERVED_MASK 0xffff0000 +#define D3F3_SLOT_STATUS2__RESERVED__SHIFT 0x10 +#define D3F3_MSI_CAP_LIST__CAP_ID_MASK 0xff +#define D3F3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F3_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 +#define D3F3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 +#define D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 +#define D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 +#define D3F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 +#define D3F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 +#define D3F3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 +#define D3F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 +#define D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 +#define D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 +#define D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define D3F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define D3F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define D3F3_MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define D3F3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define D3F3_SSID_CAP_LIST__CAP_ID_MASK 0xff +#define D3F3_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F3_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define D3F3_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 +#define D3F3_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define D3F3_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff +#define D3F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F3_MSI_MAP_CAP__EN_MASK 0x10000 +#define D3F3_MSI_MAP_CAP__EN__SHIFT 0x10 +#define D3F3_MSI_MAP_CAP__FIXD_MASK 0x20000 +#define D3F3_MSI_MAP_CAP__FIXD__SHIFT 0x11 +#define D3F3_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 +#define D3F3_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b +#define D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 +#define D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff +#define D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define D3F3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define D3F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define D3F3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define D3F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define D3F3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define D3F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define D3F3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define D3F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 +#define D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 +#define D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 +#define D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 +#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 +#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 +#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 +#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 +#define D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 +#define D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 +#define D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 +#define D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff +#define D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 +#define D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define D3F3_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define D3F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define D3F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define D3F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 +#define D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 +#define D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 +#define D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 +#define D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 +#define D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 +#define D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 +#define D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 +#define D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 +#define D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 +#define D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 +#define D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 +#define D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 +#define D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 +#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define D3F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define D3F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 +#define D3F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 +#define D3F3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 +#define D3F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f +#define D3F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define D3F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define D3F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define D3F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define D3F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define D3F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f +#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 +#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff +#define D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define D3F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff +#define D3F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 +#define D3F4_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff +#define D3F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 +#define D3F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define D3F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define D3F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define D3F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define D3F4_PCIE_FC_P__PD_CREDITS_MASK 0xff +#define D3F4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define D3F4_PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define D3F4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define D3F4_PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define D3F4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define D3F4_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define D3F4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define D3F4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define D3F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define D3F4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define D3F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define D3F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 +#define D3F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 +#define D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 +#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 +#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define D3F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define D3F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 +#define D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 +#define D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define D3F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define D3F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 +#define D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 +#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 +#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 +#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 +#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 +#define D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 +#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 +#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 +#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 +#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 +#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 +#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define D3F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 +#define D3F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 +#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 +#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 +#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 +#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 +#define D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 +#define D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define D3F4_VENDOR_ID__VENDOR_ID_MASK 0xffff +#define D3F4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define D3F4_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 +#define D3F4_DEVICE_ID__DEVICE_ID__SHIFT 0x10 +#define D3F4_COMMAND__IO_ACCESS_EN_MASK 0x1 +#define D3F4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define D3F4_COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define D3F4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define D3F4_COMMAND__BUS_MASTER_EN_MASK 0x4 +#define D3F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define D3F4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define D3F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define D3F4_COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define D3F4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define D3F4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define D3F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define D3F4_COMMAND__AD_STEPPING_MASK 0x80 +#define D3F4_COMMAND__AD_STEPPING__SHIFT 0x7 +#define D3F4_COMMAND__SERR_EN_MASK 0x100 +#define D3F4_COMMAND__SERR_EN__SHIFT 0x8 +#define D3F4_COMMAND__FAST_B2B_EN_MASK 0x200 +#define D3F4_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define D3F4_COMMAND__INT_DIS_MASK 0x400 +#define D3F4_COMMAND__INT_DIS__SHIFT 0xa +#define D3F4_STATUS__INT_STATUS_MASK 0x80000 +#define D3F4_STATUS__INT_STATUS__SHIFT 0x13 +#define D3F4_STATUS__CAP_LIST_MASK 0x100000 +#define D3F4_STATUS__CAP_LIST__SHIFT 0x14 +#define D3F4_STATUS__PCI_66_EN_MASK 0x200000 +#define D3F4_STATUS__PCI_66_EN__SHIFT 0x15 +#define D3F4_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D3F4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D3F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D3F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D3F4_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D3F4_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D3F4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D3F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D3F4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D3F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D3F4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D3F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D3F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define D3F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e +#define D3F4_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D3F4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D3F4_REVISION_ID__MINOR_REV_ID_MASK 0xf +#define D3F4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define D3F4_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define D3F4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define D3F4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 +#define D3F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 +#define D3F4_SUB_CLASS__SUB_CLASS_MASK 0xff0000 +#define D3F4_SUB_CLASS__SUB_CLASS__SHIFT 0x10 +#define D3F4_BASE_CLASS__BASE_CLASS_MASK 0xff000000 +#define D3F4_BASE_CLASS__BASE_CLASS__SHIFT 0x18 +#define D3F4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define D3F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define D3F4_LATENCY__LATENCY_TIMER_MASK 0xff00 +#define D3F4_LATENCY__LATENCY_TIMER__SHIFT 0x8 +#define D3F4_HEADER__HEADER_TYPE_MASK 0x7f0000 +#define D3F4_HEADER__HEADER_TYPE__SHIFT 0x10 +#define D3F4_HEADER__DEVICE_TYPE_MASK 0x800000 +#define D3F4_HEADER__DEVICE_TYPE__SHIFT 0x17 +#define D3F4_BIST__BIST_COMP_MASK 0xf000000 +#define D3F4_BIST__BIST_COMP__SHIFT 0x18 +#define D3F4_BIST__BIST_STRT_MASK 0x40000000 +#define D3F4_BIST__BIST_STRT__SHIFT 0x1e +#define D3F4_BIST__BIST_CAP_MASK 0x80000000 +#define D3F4_BIST__BIST_CAP__SHIFT 0x1f +#define D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff +#define D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 +#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 +#define D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 +#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define D3F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf +#define D3F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define D3F4_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 +#define D3F4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 +#define D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define D3F4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 +#define D3F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define D3F4_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 +#define D3F4_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 +#define D3F4_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 +#define D3F4_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 +#define D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D3F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D3F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 +#define D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e +#define D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf +#define D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 +#define D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 +#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 +#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf +#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 +#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 +#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 +#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff +#define D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff +#define D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff +#define D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 +#define D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 +#define D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 +#define D3F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 +#define D3F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 +#define D3F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 +#define D3F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 +#define D3F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 +#define D3F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 +#define D3F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 +#define D3F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 +#define D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 +#define D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 +#define D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 +#define D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 +#define D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 +#define D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 +#define D3F4_CAP_PTR__CAP_PTR_MASK 0xff +#define D3F4_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define D3F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define D3F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define D3F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 +#define D3F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 +#define D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 +#define D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define D3F4_PMI_CAP_LIST__CAP_ID_MASK 0xff +#define D3F4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F4_PMI_CAP__VERSION_MASK 0x70000 +#define D3F4_PMI_CAP__VERSION__SHIFT 0x10 +#define D3F4_PMI_CAP__PME_CLOCK_MASK 0x80000 +#define D3F4_PMI_CAP__PME_CLOCK__SHIFT 0x13 +#define D3F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 +#define D3F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 +#define D3F4_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 +#define D3F4_PMI_CAP__AUX_CURRENT__SHIFT 0x16 +#define D3F4_PMI_CAP__D1_SUPPORT_MASK 0x2000000 +#define D3F4_PMI_CAP__D1_SUPPORT__SHIFT 0x19 +#define D3F4_PMI_CAP__D2_SUPPORT_MASK 0x4000000 +#define D3F4_PMI_CAP__D2_SUPPORT__SHIFT 0x1a +#define D3F4_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 +#define D3F4_PMI_CAP__PME_SUPPORT__SHIFT 0x1b +#define D3F4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define D3F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define D3F4_PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define D3F4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define D3F4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define D3F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define D3F4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define D3F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define D3F4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define D3F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define D3F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define D3F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define D3F4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define D3F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define D3F4_PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define D3F4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F4_PCIE_CAP__VERSION_MASK 0xf0000 +#define D3F4_PCIE_CAP__VERSION__SHIFT 0x10 +#define D3F4_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 +#define D3F4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 +#define D3F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 +#define D3F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 +#define D3F4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 +#define D3F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 +#define D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define D3F4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define D3F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define D3F4_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define D3F4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define D3F4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define D3F4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define D3F4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define D3F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define D3F4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define D3F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define D3F4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define D3F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define D3F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define D3F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define D3F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define D3F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define D3F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define D3F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define D3F4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define D3F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 +#define D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define D3F4_DEVICE_STATUS__CORR_ERR_MASK 0x10000 +#define D3F4_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 +#define D3F4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 +#define D3F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 +#define D3F4_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 +#define D3F4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 +#define D3F4_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 +#define D3F4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 +#define D3F4_DEVICE_STATUS__AUX_PWR_MASK 0x100000 +#define D3F4_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 +#define D3F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 +#define D3F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 +#define D3F4_LINK_CAP__LINK_SPEED_MASK 0xf +#define D3F4_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define D3F4_LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define D3F4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define D3F4_LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define D3F4_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define D3F4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define D3F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define D3F4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define D3F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define D3F4_LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define D3F4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define D3F4_LINK_CNTL__PM_CONTROL_MASK 0x3 +#define D3F4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define D3F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define D3F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define D3F4_LINK_CNTL__LINK_DIS_MASK 0x10 +#define D3F4_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define D3F4_LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define D3F4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define D3F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define D3F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define D3F4_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define D3F4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define D3F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 +#define D3F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 +#define D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 +#define D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 +#define D3F4_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 +#define D3F4_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b +#define D3F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 +#define D3F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c +#define D3F4_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 +#define D3F4_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d +#define D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 +#define D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e +#define D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 +#define D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f +#define D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 +#define D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 +#define D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define D3F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 +#define D3F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 +#define D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 +#define D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define D3F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 +#define D3F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define D3F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 +#define D3F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 +#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 +#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 +#define D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 +#define D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 +#define D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 +#define D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 +#define D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 +#define D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 +#define D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 +#define D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define D3F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 +#define D3F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 +#define D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 +#define D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 +#define D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 +#define D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 +#define D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 +#define D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 +#define D3F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 +#define D3F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 +#define D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 +#define D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 +#define D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 +#define D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 +#define D3F4_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 +#define D3F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 +#define D3F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 +#define D3F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 +#define D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 +#define D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 +#define D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 +#define D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 +#define D3F4_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 +#define D3F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 +#define D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 +#define D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 +#define D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 +#define D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define D3F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 +#define D3F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 +#define D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 +#define D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 +#define D3F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff +#define D3F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define D3F4_ROOT_STATUS__PME_STATUS_MASK 0x10000 +#define D3F4_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define D3F4_ROOT_STATUS__PME_PENDING_MASK 0x20000 +#define D3F4_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 +#define D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 +#define D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 +#define D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 +#define D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define D3F4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define D3F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define D3F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define D3F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 +#define D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 +#define D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define D3F4_DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define D3F4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define D3F4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define D3F4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define D3F4_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 +#define D3F4_DEVICE_STATUS2__RESERVED__SHIFT 0x10 +#define D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define D3F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define D3F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define D3F4_LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define D3F4_LINK_CAP2__RESERVED__SHIFT 0x9 +#define D3F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define D3F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define D3F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define D3F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define D3F4_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define D3F4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define D3F4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define D3F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 +#define D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 +#define D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 +#define D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 +#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 +#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 +#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 +#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 +#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 +#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 +#define D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 +#define D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 +#define D3F4_SLOT_CAP2__RESERVED_MASK 0xffffffff +#define D3F4_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define D3F4_SLOT_CNTL2__RESERVED_MASK 0xffff +#define D3F4_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define D3F4_SLOT_STATUS2__RESERVED_MASK 0xffff0000 +#define D3F4_SLOT_STATUS2__RESERVED__SHIFT 0x10 +#define D3F4_MSI_CAP_LIST__CAP_ID_MASK 0xff +#define D3F4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F4_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 +#define D3F4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 +#define D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 +#define D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 +#define D3F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 +#define D3F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 +#define D3F4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 +#define D3F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 +#define D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 +#define D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 +#define D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define D3F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define D3F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define D3F4_MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define D3F4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define D3F4_SSID_CAP_LIST__CAP_ID_MASK 0xff +#define D3F4_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F4_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define D3F4_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 +#define D3F4_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define D3F4_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff +#define D3F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F4_MSI_MAP_CAP__EN_MASK 0x10000 +#define D3F4_MSI_MAP_CAP__EN__SHIFT 0x10 +#define D3F4_MSI_MAP_CAP__FIXD_MASK 0x20000 +#define D3F4_MSI_MAP_CAP__FIXD__SHIFT 0x11 +#define D3F4_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 +#define D3F4_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b +#define D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 +#define D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff +#define D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define D3F4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define D3F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define D3F4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define D3F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define D3F4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define D3F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define D3F4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define D3F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 +#define D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 +#define D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 +#define D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 +#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 +#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 +#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 +#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 +#define D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 +#define D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 +#define D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 +#define D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff +#define D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 +#define D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define D3F4_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define D3F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define D3F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define D3F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 +#define D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 +#define D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 +#define D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 +#define D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 +#define D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 +#define D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 +#define D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 +#define D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 +#define D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 +#define D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 +#define D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 +#define D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 +#define D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 +#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define D3F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define D3F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 +#define D3F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 +#define D3F4_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 +#define D3F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f +#define D3F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define D3F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define D3F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define D3F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define D3F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define D3F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f +#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 +#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff +#define D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define D3F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff +#define D3F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 +#define D3F5_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff +#define D3F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 +#define D3F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff +#define D3F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff +#define D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +#define D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 +#define D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 +#define D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 +#define D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 +#define D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 +#define D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 +#define D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 +#define D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 +#define D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 +#define D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 +#define D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 +#define D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 +#define D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 +#define D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 +#define D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 +#define D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 +#define D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 +#define D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 +#define D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 +#define D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 +#define D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 +#define D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 +#define D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe +#define D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 +#define D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf +#define D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 +#define D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 +#define D3F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 +#define D3F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 +#define D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 +#define D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 +#define D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 +#define D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 +#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 +#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 +#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 +#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff +#define D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 +#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 +#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 +#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 +#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e +#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 +#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f +#define D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff +#define D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 +#define D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 +#define D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 +#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 +#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 +#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 +#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf +#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 +#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 +#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff +#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 +#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 +#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc +#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff +#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 +#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 +#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 +#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff +#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 +#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 +#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 +#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff +#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 +#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 +#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 +#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff +#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 +#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 +#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 +#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff +#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 +#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 +#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 +#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff +#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 +#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 +#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 +#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 +#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 +#define D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 +#define D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 +#define D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e +#define D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 +#define D3F5_PCIE_FC_P__PD_CREDITS_MASK 0xff +#define D3F5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 +#define D3F5_PCIE_FC_P__PH_CREDITS_MASK 0xff00 +#define D3F5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 +#define D3F5_PCIE_FC_NP__NPD_CREDITS_MASK 0xff +#define D3F5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 +#define D3F5_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 +#define D3F5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 +#define D3F5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff +#define D3F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 +#define D3F5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 +#define D3F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 +#define D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 +#define D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 +#define D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 +#define D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 +#define D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 +#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 +#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 +#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 +#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 +#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 +#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 +#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 +#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 +#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 +#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 +#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 +#define D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe +#define D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 +#define D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf +#define D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 +#define D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 +#define D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 +#define D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 +#define D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc +#define D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 +#define D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd +#define D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 +#define D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe +#define D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 +#define D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf +#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 +#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 +#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 +#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 +#define D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 +#define D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 +#define D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define D3F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 +#define D3F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 +#define D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff +#define D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 +#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff +#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 +#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 +#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 +#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 +#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 +#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 +#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 +#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 +#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 +#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 +#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 +#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 +#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 +#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 +#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 +#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 +#define D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 +#define D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 +#define D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 +#define D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 +#define D3F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 +#define D3F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 +#define D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 +#define D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 +#define D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 +#define D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 +#define D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 +#define D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc +#define D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 +#define D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 +#define D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 +#define D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 +#define D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 +#define D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 +#define D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 +#define D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 +#define D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 +#define D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 +#define D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 +#define D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 +#define D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 +#define D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 +#define D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 +#define D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 +#define D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 +#define D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 +#define D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 +#define D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b +#define D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 +#define D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c +#define D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 +#define D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d +#define D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 +#define D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e +#define D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 +#define D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f +#define D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f +#define D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 +#define D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 +#define D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 +#define D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 +#define D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 +#define D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 +#define D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 +#define D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 +#define D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 +#define D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 +#define D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa +#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 +#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb +#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 +#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc +#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 +#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd +#define D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 +#define D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe +#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 +#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 +#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 +#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 +#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 +#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 +#define D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 +#define D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 +#define D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 +#define D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 +#define D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 +#define D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 +#define D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 +#define D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 +#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 +#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 +#define D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 +#define D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 +#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 +#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a +#define D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 +#define D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 +#define D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c +#define D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 +#define D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d +#define D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 +#define D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f +#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 +#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 +#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 +#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 +#define D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 +#define D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 +#define D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 +#define D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 +#define D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 +#define D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 +#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 +#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 +#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 +#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 +#define D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 +#define D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 +#define D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 +#define D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa +#define D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 +#define D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb +#define D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 +#define D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc +#define D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 +#define D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe +#define D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 +#define D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 +#define D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 +#define D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 +#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 +#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 +#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 +#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 +#define D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 +#define D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 +#define D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 +#define D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 +#define D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 +#define D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 +#define D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 +#define D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 +#define D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 +#define D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a +#define D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 +#define D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e +#define D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 +#define D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f +#define D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 +#define D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 +#define D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 +#define D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 +#define D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 +#define D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 +#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 +#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 +#define D3F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 +#define D3F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 +#define D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 +#define D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 +#define D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 +#define D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 +#define D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 +#define D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 +#define D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 +#define D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa +#define D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 +#define D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb +#define D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 +#define D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc +#define D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 +#define D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd +#define D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 +#define D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe +#define D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 +#define D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf +#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 +#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 +#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 +#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 +#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 +#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 +#define D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 +#define D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 +#define D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 +#define D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 +#define D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 +#define D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 +#define D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 +#define D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 +#define D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 +#define D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a +#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f +#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 +#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 +#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 +#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 +#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc +#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 +#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 +#define D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 +#define D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 +#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 +#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 +#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 +#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 +#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 +#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 +#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 +#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 +#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d +#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff +#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 +#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 +#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 +#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 +#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 +#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 +#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 +#define D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 +#define D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa +#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc +#define D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd +#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf +#define D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a +#define D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b +#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c +#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d +#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e +#define D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 +#define D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f +#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff +#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 +#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 +#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc +#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 +#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 +#define D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff +#define D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 +#define D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 +#define D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 +#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 +#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 +#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e +#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 +#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 +#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 +#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 +#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd +#define D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 +#define D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 +#define D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 +#define D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 +#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf +#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 +#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 +#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 +#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 +#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa +#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 +#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 +#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 +#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 +#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 +#define D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f +#define D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 +#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 +#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 +#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 +#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 +#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 +#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 +#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f +#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 +#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 +#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 +#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 +#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 +#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 +#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 +#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f +#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 +#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 +#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 +#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 +#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 +#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 +#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 +#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f +#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 +#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 +#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 +#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 +#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 +#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 +#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 +#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f +#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 +#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 +#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 +#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 +#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 +#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 +#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 +#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f +#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 +#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 +#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 +#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 +#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 +#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 +#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 +#define D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 +#define D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 +#define D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc +#define D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 +#define D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 +#define D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 +#define D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 +#define D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 +#define D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 +#define D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 +#define D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 +#define D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb +#define D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 +#define D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc +#define D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 +#define D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd +#define D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 +#define D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe +#define D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 +#define D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf +#define D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 +#define D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 +#define D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 +#define D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 +#define D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 +#define D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 +#define D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 +#define D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 +#define D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 +#define D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 +#define D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 +#define D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 +#define D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 +#define D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 +#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 +#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 +#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 +#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 +#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 +#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 +#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 +#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 +#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 +#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 +#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 +#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 +#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 +#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 +#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 +#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 +#define D3F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 +#define D3F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 +#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 +#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 +#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 +#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 +#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 +#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa +#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 +#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb +#define D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 +#define D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf +#define D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 +#define D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 +#define D3F5_VENDOR_ID__VENDOR_ID_MASK 0xffff +#define D3F5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define D3F5_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 +#define D3F5_DEVICE_ID__DEVICE_ID__SHIFT 0x10 +#define D3F5_COMMAND__IO_ACCESS_EN_MASK 0x1 +#define D3F5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define D3F5_COMMAND__MEM_ACCESS_EN_MASK 0x2 +#define D3F5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define D3F5_COMMAND__BUS_MASTER_EN_MASK 0x4 +#define D3F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define D3F5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 +#define D3F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 +#define D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define D3F5_COMMAND__PAL_SNOOP_EN_MASK 0x20 +#define D3F5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define D3F5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 +#define D3F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define D3F5_COMMAND__AD_STEPPING_MASK 0x80 +#define D3F5_COMMAND__AD_STEPPING__SHIFT 0x7 +#define D3F5_COMMAND__SERR_EN_MASK 0x100 +#define D3F5_COMMAND__SERR_EN__SHIFT 0x8 +#define D3F5_COMMAND__FAST_B2B_EN_MASK 0x200 +#define D3F5_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define D3F5_COMMAND__INT_DIS_MASK 0x400 +#define D3F5_COMMAND__INT_DIS__SHIFT 0xa +#define D3F5_STATUS__INT_STATUS_MASK 0x80000 +#define D3F5_STATUS__INT_STATUS__SHIFT 0x13 +#define D3F5_STATUS__CAP_LIST_MASK 0x100000 +#define D3F5_STATUS__CAP_LIST__SHIFT 0x14 +#define D3F5_STATUS__PCI_66_EN_MASK 0x200000 +#define D3F5_STATUS__PCI_66_EN__SHIFT 0x15 +#define D3F5_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D3F5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D3F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D3F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D3F5_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D3F5_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D3F5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D3F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D3F5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D3F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D3F5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D3F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D3F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 +#define D3F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e +#define D3F5_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D3F5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D3F5_REVISION_ID__MINOR_REV_ID_MASK 0xf +#define D3F5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define D3F5_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 +#define D3F5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define D3F5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 +#define D3F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 +#define D3F5_SUB_CLASS__SUB_CLASS_MASK 0xff0000 +#define D3F5_SUB_CLASS__SUB_CLASS__SHIFT 0x10 +#define D3F5_BASE_CLASS__BASE_CLASS_MASK 0xff000000 +#define D3F5_BASE_CLASS__BASE_CLASS__SHIFT 0x18 +#define D3F5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff +#define D3F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define D3F5_LATENCY__LATENCY_TIMER_MASK 0xff00 +#define D3F5_LATENCY__LATENCY_TIMER__SHIFT 0x8 +#define D3F5_HEADER__HEADER_TYPE_MASK 0x7f0000 +#define D3F5_HEADER__HEADER_TYPE__SHIFT 0x10 +#define D3F5_HEADER__DEVICE_TYPE_MASK 0x800000 +#define D3F5_HEADER__DEVICE_TYPE__SHIFT 0x17 +#define D3F5_BIST__BIST_COMP_MASK 0xf000000 +#define D3F5_BIST__BIST_COMP__SHIFT 0x18 +#define D3F5_BIST__BIST_STRT_MASK 0x40000000 +#define D3F5_BIST__BIST_STRT__SHIFT 0x1e +#define D3F5_BIST__BIST_CAP_MASK 0x80000000 +#define D3F5_BIST__BIST_CAP__SHIFT 0x1f +#define D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff +#define D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 +#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 +#define D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 +#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define D3F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf +#define D3F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define D3F5_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 +#define D3F5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 +#define D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define D3F5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 +#define D3F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define D3F5_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 +#define D3F5_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 +#define D3F5_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 +#define D3F5_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 +#define D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 +#define D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 +#define D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 +#define D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 +#define D3F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 +#define D3F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 +#define D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 +#define D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b +#define D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 +#define D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c +#define D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 +#define D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d +#define D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 +#define D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e +#define D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 +#define D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f +#define D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf +#define D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 +#define D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 +#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 +#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf +#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 +#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 +#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 +#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff +#define D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff +#define D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff +#define D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 +#define D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 +#define D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 +#define D3F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 +#define D3F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 +#define D3F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 +#define D3F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 +#define D3F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 +#define D3F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 +#define D3F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 +#define D3F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 +#define D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 +#define D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 +#define D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 +#define D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 +#define D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 +#define D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 +#define D3F5_CAP_PTR__CAP_PTR_MASK 0xff +#define D3F5_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define D3F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff +#define D3F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define D3F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 +#define D3F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 +#define D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 +#define D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define D3F5_PMI_CAP_LIST__CAP_ID_MASK 0xff +#define D3F5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F5_PMI_CAP__VERSION_MASK 0x70000 +#define D3F5_PMI_CAP__VERSION__SHIFT 0x10 +#define D3F5_PMI_CAP__PME_CLOCK_MASK 0x80000 +#define D3F5_PMI_CAP__PME_CLOCK__SHIFT 0x13 +#define D3F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 +#define D3F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 +#define D3F5_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 +#define D3F5_PMI_CAP__AUX_CURRENT__SHIFT 0x16 +#define D3F5_PMI_CAP__D1_SUPPORT_MASK 0x2000000 +#define D3F5_PMI_CAP__D1_SUPPORT__SHIFT 0x19 +#define D3F5_PMI_CAP__D2_SUPPORT_MASK 0x4000000 +#define D3F5_PMI_CAP__D2_SUPPORT__SHIFT 0x1a +#define D3F5_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 +#define D3F5_PMI_CAP__PME_SUPPORT__SHIFT 0x1b +#define D3F5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 +#define D3F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 +#define D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define D3F5_PMI_STATUS_CNTL__PME_EN_MASK 0x100 +#define D3F5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define D3F5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 +#define D3F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define D3F5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 +#define D3F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define D3F5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 +#define D3F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 +#define D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define D3F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 +#define D3F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define D3F5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 +#define D3F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define D3F5_PCIE_CAP_LIST__CAP_ID_MASK 0xff +#define D3F5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F5_PCIE_CAP__VERSION_MASK 0xf0000 +#define D3F5_PCIE_CAP__VERSION__SHIFT 0x10 +#define D3F5_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 +#define D3F5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 +#define D3F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 +#define D3F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 +#define D3F5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 +#define D3F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 +#define D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 +#define D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define D3F5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 +#define D3F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define D3F5_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 +#define D3F5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 +#define D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 +#define D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 +#define D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 +#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 +#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define D3F5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 +#define D3F5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define D3F5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 +#define D3F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 +#define D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define D3F5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 +#define D3F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define D3F5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 +#define D3F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define D3F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 +#define D3F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 +#define D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define D3F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 +#define D3F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 +#define D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define D3F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 +#define D3F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define D3F5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 +#define D3F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 +#define D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 +#define D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define D3F5_DEVICE_STATUS__CORR_ERR_MASK 0x10000 +#define D3F5_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 +#define D3F5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 +#define D3F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 +#define D3F5_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 +#define D3F5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 +#define D3F5_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 +#define D3F5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 +#define D3F5_DEVICE_STATUS__AUX_PWR_MASK 0x100000 +#define D3F5_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 +#define D3F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 +#define D3F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 +#define D3F5_LINK_CAP__LINK_SPEED_MASK 0xf +#define D3F5_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define D3F5_LINK_CAP__LINK_WIDTH_MASK 0x3f0 +#define D3F5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define D3F5_LINK_CAP__PM_SUPPORT_MASK 0xc00 +#define D3F5_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define D3F5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 +#define D3F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define D3F5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 +#define D3F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 +#define D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 +#define D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 +#define D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 +#define D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 +#define D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define D3F5_LINK_CAP__PORT_NUMBER_MASK 0xff000000 +#define D3F5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define D3F5_LINK_CNTL__PM_CONTROL_MASK 0x3 +#define D3F5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define D3F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 +#define D3F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define D3F5_LINK_CNTL__LINK_DIS_MASK 0x10 +#define D3F5_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define D3F5_LINK_CNTL__RETRAIN_LINK_MASK 0x20 +#define D3F5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define D3F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 +#define D3F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define D3F5_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 +#define D3F5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 +#define D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 +#define D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 +#define D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 +#define D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define D3F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 +#define D3F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 +#define D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 +#define D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 +#define D3F5_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 +#define D3F5_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b +#define D3F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 +#define D3F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c +#define D3F5_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 +#define D3F5_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d +#define D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 +#define D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e +#define D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 +#define D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f +#define D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 +#define D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 +#define D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define D3F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 +#define D3F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 +#define D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 +#define D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define D3F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 +#define D3F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define D3F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 +#define D3F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 +#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 +#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 +#define D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 +#define D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 +#define D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 +#define D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 +#define D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 +#define D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 +#define D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 +#define D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define D3F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 +#define D3F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 +#define D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 +#define D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 +#define D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 +#define D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 +#define D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 +#define D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 +#define D3F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 +#define D3F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 +#define D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 +#define D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 +#define D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 +#define D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 +#define D3F5_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 +#define D3F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 +#define D3F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 +#define D3F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 +#define D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 +#define D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 +#define D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 +#define D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 +#define D3F5_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 +#define D3F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 +#define D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 +#define D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 +#define D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 +#define D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define D3F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 +#define D3F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 +#define D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 +#define D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 +#define D3F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff +#define D3F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define D3F5_ROOT_STATUS__PME_STATUS_MASK 0x10000 +#define D3F5_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define D3F5_ROOT_STATUS__PME_PENDING_MASK 0x20000 +#define D3F5_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf +#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 +#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 +#define D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 +#define D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 +#define D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 +#define D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 +#define D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 +#define D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define D3F5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 +#define D3F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 +#define D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define D3F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 +#define D3F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 +#define D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 +#define D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 +#define D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf +#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 +#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 +#define D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 +#define D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 +#define D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 +#define D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 +#define D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define D3F5_DEVICE_CNTL2__LTR_EN_MASK 0x400 +#define D3F5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define D3F5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 +#define D3F5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 +#define D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define D3F5_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 +#define D3F5_DEVICE_STATUS2__RESERVED__SHIFT 0x10 +#define D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe +#define D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define D3F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 +#define D3F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define D3F5_LINK_CAP2__RESERVED_MASK 0xfffffe00 +#define D3F5_LINK_CAP2__RESERVED__SHIFT 0x9 +#define D3F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf +#define D3F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define D3F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 +#define D3F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 +#define D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 +#define D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define D3F5_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 +#define D3F5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 +#define D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define D3F5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 +#define D3F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 +#define D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 +#define D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 +#define D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 +#define D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 +#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 +#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 +#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 +#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 +#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 +#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 +#define D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 +#define D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 +#define D3F5_SLOT_CAP2__RESERVED_MASK 0xffffffff +#define D3F5_SLOT_CAP2__RESERVED__SHIFT 0x0 +#define D3F5_SLOT_CNTL2__RESERVED_MASK 0xffff +#define D3F5_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define D3F5_SLOT_STATUS2__RESERVED_MASK 0xffff0000 +#define D3F5_SLOT_STATUS2__RESERVED__SHIFT 0x10 +#define D3F5_MSI_CAP_LIST__CAP_ID_MASK 0xff +#define D3F5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F5_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 +#define D3F5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 +#define D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 +#define D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 +#define D3F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 +#define D3F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 +#define D3F5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 +#define D3F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 +#define D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 +#define D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 +#define D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc +#define D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff +#define D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define D3F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff +#define D3F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define D3F5_MSI_MSG_DATA__MSI_DATA_MASK 0xffff +#define D3F5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define D3F5_SSID_CAP_LIST__CAP_ID_MASK 0xff +#define D3F5_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F5_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff +#define D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define D3F5_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 +#define D3F5_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define D3F5_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff +#define D3F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 +#define D3F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define D3F5_MSI_MAP_CAP__EN_MASK 0x10000 +#define D3F5_MSI_MAP_CAP__EN__SHIFT 0x10 +#define D3F5_MSI_MAP_CAP__FIXD_MASK 0x20000 +#define D3F5_MSI_MAP_CAP__FIXD__SHIFT 0x11 +#define D3F5_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 +#define D3F5_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b +#define D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 +#define D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 +#define D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff +#define D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 +#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff +#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 +#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 +#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff +#define D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff +#define D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 +#define D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 +#define D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 +#define D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 +#define D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff +#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 +#define D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe +#define D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff +#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 +#define D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 +#define D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 +#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 +#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe +#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 +#define D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 +#define D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 +#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 +#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 +#define D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 +#define D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 +#define D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 +#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff +#define D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff +#define D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 +#define D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 +#define D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 +#define D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 +#define D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 +#define D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 +#define D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 +#define D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 +#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 +#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 +#define D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 +#define D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 +#define D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 +#define D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 +#define D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 +#define D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 +#define D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 +#define D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 +#define D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 +#define D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 +#define D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 +#define D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 +#define D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 +#define D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 +#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 +#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 +#define D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 +#define D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 +#define D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 +#define D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 +#define D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 +#define D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 +#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 +#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 +#define D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 +#define D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 +#define D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 +#define D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define D3F5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff +#define D3F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define D3F5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff +#define D3F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define D3F5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff +#define D3F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define D3F5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff +#define D3F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 +#define D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 +#define D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 +#define D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 +#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 +#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 +#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 +#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 +#define D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 +#define D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 +#define D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 +#define D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff +#define D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 +#define D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff +#define D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff +#define D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff +#define D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff +#define D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 +#define D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 +#define D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define D3F5_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc +#define D3F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +#define D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff +#define D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define D3F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 +#define D3F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf +#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 +#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 +#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 +#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 +#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 +#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 +#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 +#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 +#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 +#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 +#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 +#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c +#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 +#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f +#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 +#define D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 +#define D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 +#define D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 +#define D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 +#define D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 +#define D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 +#define D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 +#define D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 +#define D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 +#define D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 +#define D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 +#define D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 +#define D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 +#define D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 +#define D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 +#define D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 +#define D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 +#define D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 +#define D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 +#define D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 +#define D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 +#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff +#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 +#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 +#define D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define D3F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f +#define D3F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 +#define D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define D3F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 +#define D3F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 +#define D3F5_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 +#define D3F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f +#define D3F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f +#define D3F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 +#define D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff +#define D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define D3F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff +#define D3F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define D3F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff +#define D3F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff +#define D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff +#define D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff +#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff +#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f +#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 +#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 +#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 +#define D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff +#define D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 +#define C_PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff +#define C_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define C_PCIE_DATA__PCIE_DATA_MASK 0xffffffff +#define C_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT 0x1 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK 0x4 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK 0x8 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT 0x3 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK 0x200 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK 0x800 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT 0xb +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK 0x2000 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT 0xd +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK 0x200000 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT 0x15 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK 0x800000 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT 0x17 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK 0x10000000 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT 0x1c +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK 0x20000000 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT 0x1d +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK 0xc0000000 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT 0x1e +#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK 0x1ff8 +#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT 0x3 +#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK 0x6000 +#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT 0xd +#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK 0x1f8000 +#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT 0xf +#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK 0x200000 +#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT 0x15 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT 0x1 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK 0xc +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK 0x10 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT 0x4 +#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK 0x400 +#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT 0xa +#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK 0x800 +#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT 0xb +#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK 0x2000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT 0xd +#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK 0x4000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT 0xe +#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x18000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0xf +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK 0x1 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT 0x1 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK 0x4 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK 0x10 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK 0x40 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT 0x6 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK 0x200 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK 0x1000 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT 0xc +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK 0x10000 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT 0x10 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK 0x20000 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT 0x11 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK 0x40000 +#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT 0x12 +#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK 0x4000000 +#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT 0x1a +#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK 0xc0000000 +#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT 0x1e +#define PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK 0x1 +#define PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK 0x1 +#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2 +#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT 0x1 +#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK 0x4 +#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK 0x1 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK 0x4 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x8 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x3 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK 0x70 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT 0x4 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT 0x8 +#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK 0xffff +#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT 0x0 +#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK 0xffff0000 +#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT 0x10 +#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x7 +#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0 +#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x38 +#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x3 +#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK 0x3c0 +#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x6 +#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK 0x3c00 +#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT 0xa +#define PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK 0xf +#define PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT 0x0 +#define PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK 0x1 +#define PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 +#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK 0xc000 +#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT 0xe +#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 +#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 +#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 +#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 +#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 +#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 +#define PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK 0x1 +#define PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT 0x0 +#define PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK 0x1 +#define PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 +#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK 0xc000 +#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT 0xe +#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 +#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 +#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 +#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 +#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 +#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 +#define PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK 0x1 +#define PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT 0x0 +#define PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK 0x1 +#define PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 +#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK 0xc000 +#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT 0xe +#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 +#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 +#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 +#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 +#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 +#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 +#define PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK 0x1 +#define PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT 0x0 +#define PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK 0x1 +#define PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 +#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK 0xc000 +#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT 0xe +#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 +#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 +#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 +#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 +#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 +#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 +#define PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK 0x1 +#define PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT 0x0 +#define PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK 0x1 +#define PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 +#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 +#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK 0xc000 +#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT 0xe +#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 +#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 +#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 +#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 +#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 +#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 +#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK 0x80 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 +#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 +#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 +#define PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK 0x1 +#define PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT 0x0 +#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1 +#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0 +#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2 +#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1 +#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4 +#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2 +#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8 +#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3 +#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10 +#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4 +#define PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff +#define PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0 +#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7 +#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0 +#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70 +#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4 +#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff +#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0 +#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000 +#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10 +#define PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff +#define PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0 +#define PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff +#define PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0 +#define PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff +#define PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0 +#define PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK 0xffffffff +#define PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT 0x0 +#define PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK 0xffffffff +#define PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT 0x0 +#define PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK 0xffffffff +#define PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT 0x0 +#define PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK 0xffffffff +#define PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT 0x0 +#define PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK 0xffffffff +#define PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT 0x0 +#define PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK 0xffffffff +#define PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT 0x0 +#define PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK 0xffffffff +#define PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT 0x0 +#define PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff +#define PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0 +#define PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff +#define PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0 +#define PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1 +#define PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0 +#define PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1 +#define PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0 +#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1 +#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0 +#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2 +#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1 +#define PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2 +#define PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT 0x1 +#define PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4 +#define PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2 +#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7 +#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0 +#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70 +#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4 +#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80 +#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7 +#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100 +#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8 +#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xff +#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0 +#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000 +#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10 +#define PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK 0x1 +#define PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT 0x0 +#define PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK 0x800 +#define PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT 0xb +#define PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1 +#define PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0 +#define PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1 +#define PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0 +#define PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1 +#define PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0 +#define PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1 +#define PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0 +#define PSX80_WRP_BIOSTIMER_CMD__Microseconds_MASK 0xffffffff +#define PSX80_WRP_BIOSTIMER_CMD__Microseconds__SHIFT 0x0 +#define PSX80_WRP_BIOSTIMER_CNTL__ClockRate_MASK 0xff +#define PSX80_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT 0x0 +#define PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK 0xffffffff +#define PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT 0x0 +#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK 0xff +#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT 0x0 +#define PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK 0xf0000 +#define PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT 0x10 +#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK 0xf00000 +#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT 0x14 +#define PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK 0x1f000000 +#define PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT 0x18 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy0_MASK 0x1 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT 0x0 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT 0x1 +#define PSX80_WRP_DTM_CNTL__Determinism_En_DTM_MASK 0x4 +#define PSX80_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy2_MASK 0x8 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT 0x3 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy3_MASK 0x10 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT 0x4 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy4_MASK 0x20 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT 0x5 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy5_MASK 0x40 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT 0x6 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy6_MASK 0x80 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT 0x7 +#define PSX80_WRP_DTM_CNTL__TxClk1x_Cntl_MASK 0x300 +#define PSX80_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT 0x8 +#define PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK 0xc00 +#define PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT 0xa +#define PSX80_WRP_DTM_CNTL__refClk_Cntl_MASK 0x3000 +#define PSX80_WRP_DTM_CNTL__refClk_Cntl__SHIFT 0xc +#define PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK 0xc000 +#define PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT 0xe +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy7_MASK 0x10000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT 0x10 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy8_MASK 0x20000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT 0x11 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy9_MASK 0x40000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT 0x12 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy10_MASK 0x80000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT 0x13 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy11_MASK 0x100000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT 0x14 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy12_MASK 0x200000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT 0x15 +#define PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK 0xc00000 +#define PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT 0x16 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy13_MASK 0x1000000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT 0x18 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy14_MASK 0x2000000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT 0x19 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy15_MASK 0x4000000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT 0x1a +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy16_MASK 0x8000000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT 0x1b +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy17_MASK 0x10000000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT 0x1c +#define PSX80_WRP_DTM_CNTL__Warm_RstTimer_MASK 0x60000000 +#define PSX80_WRP_DTM_CNTL__Warm_RstTimer__SHIFT 0x1d +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy18_MASK 0x80000000 +#define PSX80_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT 0x1f +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK 0x1 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT 0x0 +#define PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2 +#define PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT 0x1 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK 0x4 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK 0x8 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT 0x3 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK 0x30 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT 0x4 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK 0xc0 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT 0x6 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK 0x300 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT 0x8 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK 0xf000 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT 0xc +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK 0xf0000 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT 0x10 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK 0xf00000 +#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT 0x14 +#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK 0x1ff +#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT 0x0 +#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK 0x3fe00 +#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT 0x9 +#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK 0x7fc0000 +#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT 0x12 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK 0xff +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT 0x0 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK 0xff00 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT 0x8 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK 0xff0000 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT 0x10 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK 0xff +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT 0x0 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK 0xff00 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT 0x8 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK 0xff0000 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT 0x10 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK 0xff +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT 0x0 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK 0xff00 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT 0x8 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK 0xff0000 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT 0x10 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK 0xff +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT 0x0 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK 0xff00 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT 0x8 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK 0xff0000 +#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT 0x10 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK 0x1 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT 0x0 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT 0x1 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK 0x4 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK 0x8 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT 0x3 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK 0xff00 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT 0x8 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK 0x10000 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT 0x10 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK 0x20000 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT 0x11 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK 0x40000 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT 0x12 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK 0x100000 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT 0x14 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK 0x200000 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT 0x15 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK 0xf0000000 +#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT 0x1c +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK 0x1 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT 0x0 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT 0x1 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK 0x4 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK 0x8 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT 0x3 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK 0x10 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT 0x4 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK 0xff00 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT 0x8 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK 0xff0000 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT 0x10 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK 0x1f000000 +#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT 0x18 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT 0x1 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK 0x4 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK 0x8 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT 0x3 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK 0x200 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK 0x800 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT 0xb +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK 0x2000 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT 0xd +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK 0x200000 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT 0x15 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK 0x800000 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT 0x17 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK 0x10000000 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT 0x1c +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK 0x20000000 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT 0x1d +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK 0xc0000000 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT 0x1e +#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK 0x1ff8 +#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT 0x3 +#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK 0x6000 +#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT 0xd +#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK 0x1f8000 +#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT 0xf +#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK 0x200000 +#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT 0x15 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT 0x1 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK 0xc +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK 0x10 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT 0x4 +#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK 0x400 +#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT 0xa +#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK 0x800 +#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT 0xb +#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK 0x2000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT 0xd +#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK 0x4000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT 0xe +#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x18000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0xf +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK 0x1 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT 0x1 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK 0x4 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK 0x10 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT 0x4 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK 0x40 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT 0x6 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK 0x200 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK 0x1000 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT 0xc +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK 0x10000 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT 0x10 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK 0x20000 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT 0x11 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK 0x40000 +#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT 0x12 +#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK 0x4000000 +#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT 0x1a +#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK 0xc0000000 +#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT 0x1e +#define PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK 0x1 +#define PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK 0x1 +#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2 +#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT 0x1 +#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK 0x4 +#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK 0x1 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK 0x4 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x8 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x3 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK 0x70 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT 0x4 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT 0x8 +#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK 0xffff +#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT 0x0 +#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK 0xffff0000 +#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT 0x10 +#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x7 +#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0 +#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x38 +#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x3 +#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK 0x3c0 +#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x6 +#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK 0x3c00 +#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT 0xa +#define PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK 0xf +#define PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT 0x0 +#define PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK 0x1 +#define PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 +#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK 0xc000 +#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT 0xe +#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 +#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 +#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 +#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 +#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 +#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 +#define PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK 0x1 +#define PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT 0x0 +#define PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK 0x1 +#define PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 +#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK 0xc000 +#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT 0xe +#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 +#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 +#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 +#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 +#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 +#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 +#define PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK 0x1 +#define PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT 0x0 +#define PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK 0x1 +#define PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 +#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK 0xc000 +#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT 0xe +#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 +#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 +#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 +#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 +#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 +#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 +#define PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK 0x1 +#define PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT 0x0 +#define PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK 0x1 +#define PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 +#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK 0xc000 +#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT 0xe +#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 +#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 +#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 +#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 +#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 +#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 +#define PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK 0x1 +#define PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT 0x0 +#define PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK 0x1 +#define PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 +#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 +#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK 0xc000 +#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT 0xe +#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 +#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 +#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 +#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 +#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 +#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 +#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK 0x80 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 +#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 +#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 +#define PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK 0x1 +#define PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT 0x0 +#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1 +#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0 +#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2 +#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1 +#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4 +#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2 +#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8 +#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3 +#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10 +#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4 +#define PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff +#define PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0 +#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7 +#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0 +#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70 +#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4 +#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff +#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0 +#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000 +#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10 +#define PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff +#define PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0 +#define PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff +#define PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0 +#define PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff +#define PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0 +#define PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK 0xffffffff +#define PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT 0x0 +#define PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK 0xffffffff +#define PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT 0x0 +#define PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK 0xffffffff +#define PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT 0x0 +#define PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK 0xffffffff +#define PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT 0x0 +#define PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK 0xffffffff +#define PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT 0x0 +#define PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK 0xffffffff +#define PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT 0x0 +#define PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK 0xffffffff +#define PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT 0x0 +#define PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff +#define PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0 +#define PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff +#define PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0 +#define PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1 +#define PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0 +#define PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1 +#define PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0 +#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1 +#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0 +#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2 +#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1 +#define PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2 +#define PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT 0x1 +#define PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4 +#define PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2 +#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7 +#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0 +#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70 +#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4 +#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80 +#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7 +#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100 +#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8 +#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xff +#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0 +#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000 +#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10 +#define PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK 0x1 +#define PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT 0x0 +#define PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK 0x800 +#define PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT 0xb +#define PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1 +#define PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0 +#define PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1 +#define PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0 +#define PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1 +#define PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0 +#define PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1 +#define PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0 +#define PSX81_WRP_BIOSTIMER_CMD__Microseconds_MASK 0xffffffff +#define PSX81_WRP_BIOSTIMER_CMD__Microseconds__SHIFT 0x0 +#define PSX81_WRP_BIOSTIMER_CNTL__ClockRate_MASK 0xff +#define PSX81_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT 0x0 +#define PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK 0xffffffff +#define PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT 0x0 +#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK 0xff +#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT 0x0 +#define PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK 0xf0000 +#define PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT 0x10 +#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK 0xf00000 +#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT 0x14 +#define PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK 0x1f000000 +#define PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT 0x18 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy0_MASK 0x1 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT 0x0 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT 0x1 +#define PSX81_WRP_DTM_CNTL__Determinism_En_DTM_MASK 0x4 +#define PSX81_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy2_MASK 0x8 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT 0x3 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy3_MASK 0x10 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT 0x4 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy4_MASK 0x20 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT 0x5 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy5_MASK 0x40 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT 0x6 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy6_MASK 0x80 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT 0x7 +#define PSX81_WRP_DTM_CNTL__TxClk1x_Cntl_MASK 0x300 +#define PSX81_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT 0x8 +#define PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK 0xc00 +#define PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT 0xa +#define PSX81_WRP_DTM_CNTL__refClk_Cntl_MASK 0x3000 +#define PSX81_WRP_DTM_CNTL__refClk_Cntl__SHIFT 0xc +#define PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK 0xc000 +#define PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT 0xe +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy7_MASK 0x10000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT 0x10 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy8_MASK 0x20000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT 0x11 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy9_MASK 0x40000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT 0x12 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy10_MASK 0x80000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT 0x13 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy11_MASK 0x100000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT 0x14 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy12_MASK 0x200000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT 0x15 +#define PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK 0xc00000 +#define PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT 0x16 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy13_MASK 0x1000000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT 0x18 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy14_MASK 0x2000000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT 0x19 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy15_MASK 0x4000000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT 0x1a +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy16_MASK 0x8000000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT 0x1b +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy17_MASK 0x10000000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT 0x1c +#define PSX81_WRP_DTM_CNTL__Warm_RstTimer_MASK 0x60000000 +#define PSX81_WRP_DTM_CNTL__Warm_RstTimer__SHIFT 0x1d +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy18_MASK 0x80000000 +#define PSX81_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT 0x1f +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK 0x1 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT 0x0 +#define PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2 +#define PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT 0x1 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK 0x4 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK 0x8 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT 0x3 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK 0x30 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT 0x4 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK 0xc0 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT 0x6 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK 0x300 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT 0x8 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK 0xf000 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT 0xc +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK 0xf0000 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT 0x10 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK 0xf00000 +#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT 0x14 +#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK 0x1ff +#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT 0x0 +#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK 0x3fe00 +#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT 0x9 +#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK 0x7fc0000 +#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT 0x12 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK 0xff +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT 0x0 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK 0xff00 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT 0x8 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK 0xff0000 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT 0x10 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK 0xff +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT 0x0 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK 0xff00 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT 0x8 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK 0xff0000 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT 0x10 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK 0xff +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT 0x0 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK 0xff00 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT 0x8 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK 0xff0000 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT 0x10 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK 0xff +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT 0x0 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK 0xff00 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT 0x8 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK 0xff0000 +#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT 0x10 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK 0x1 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT 0x0 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT 0x1 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK 0x4 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK 0x8 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT 0x3 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK 0xff00 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT 0x8 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK 0x10000 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT 0x10 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK 0x20000 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT 0x11 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK 0x40000 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT 0x12 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK 0x100000 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT 0x14 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK 0x200000 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT 0x15 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK 0xf0000000 +#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT 0x1c +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK 0x1 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT 0x0 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT 0x1 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK 0x4 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK 0x8 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT 0x3 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK 0x10 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT 0x4 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK 0xff00 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT 0x8 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK 0xff0000 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT 0x10 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK 0x1f000000 +#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT 0x18 +#define RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1 +#define RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0 +#define RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2 +#define RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1 +#define RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff +#define RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0 +#define RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000 +#define RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e +#define RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000 +#define RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f +#define RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1 +#define RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0 +#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst_MASK 0x1 +#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst__SHIFT 0x0 +#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst_MASK 0x2 +#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst__SHIFT 0x1 +#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst_MASK 0x4 +#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst__SHIFT 0x2 +#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst_MASK 0x1 +#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst__SHIFT 0x0 +#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst_MASK 0x2 +#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst__SHIFT 0x1 +#define RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst_MASK 0x4 +#define RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst__SHIFT 0x2 +#define RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd_MASK 0x1 +#define RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd__SHIFT 0x0 +#define RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd_MASK 0x2 +#define RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd__SHIFT 0x1 +#define RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd_MASK 0x4 +#define RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd__SHIFT 0x2 +#define RFE_PWDN_STATUS__PCIEW0_REG_pw_status_MASK 0x1 +#define RFE_PWDN_STATUS__PCIEW0_REG_pw_status__SHIFT 0x0 +#define RFE_PWDN_STATUS__PCIEW1_REG_pw_status_MASK 0x2 +#define RFE_PWDN_STATUS__PCIEW1_REG_pw_status__SHIFT 0x1 +#define RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status_MASK 0x4 +#define RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status__SHIFT 0x2 +#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer_MASK 0xff +#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer__SHIFT 0x0 +#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer_MASK 0xf00 +#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer__SHIFT 0x8 +#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer_MASK 0xff0000 +#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer__SHIFT 0x10 +#define RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout_MASK 0x1000000 +#define RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout__SHIFT 0x18 +#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer_MASK 0xff +#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer__SHIFT 0x0 +#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer_MASK 0xf00 +#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer__SHIFT 0x8 +#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer_MASK 0xff0000 +#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer__SHIFT 0x10 +#define RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout_MASK 0x1000000 +#define RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout__SHIFT 0x18 +#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer_MASK 0xff +#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer__SHIFT 0x0 +#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer_MASK 0xf00 +#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer__SHIFT 0x8 +#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer_MASK 0xff0000 +#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer__SHIFT 0x10 +#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout_MASK 0x1000000 +#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout__SHIFT 0x18 +#define RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1 +#define RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0 +#define RFE_IMPARBH_STATUS__IMPAH_REG_calDone_MASK 0x1 +#define RFE_IMPARBH_STATUS__IMPAH_REG_calDone__SHIFT 0x0 +#define RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer_MASK 0x3ff +#define RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer__SHIFT 0x0 +#define PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff +#define PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff +#define PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff +#define PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 +#define PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff +#define PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 +#define PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1 +#define PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe +#define PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 +#define PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80 +#define PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100 +#define PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200 +#define PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 +#define PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00 +#define PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa +#define PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf +#define PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000 +#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 +#define PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000 +#define PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 +#define PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000 +#define PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 +#define PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000 +#define PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000 +#define PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f +#define PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf +#define PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000 +#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff +#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 +#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100 +#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 +#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000 +#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 +#define PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1 +#define PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 +#define PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e +#define PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 +#define PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0 +#define PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 +#define PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800 +#define PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb +#define PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000 +#define PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc +#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000 +#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd +#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000 +#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe +#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 +#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 +#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000 +#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 +#define PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000 +#define PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 +#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000 +#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 +#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000 +#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 +#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000 +#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 +#define PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000 +#define PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 +#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000 +#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 +#define PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000 +#define PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 +#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000 +#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d +#define PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000 +#define PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e +#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000 +#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 +#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000 +#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc +#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000 +#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd +#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000 +#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe +#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000 +#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 +#define PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000 +#define PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3 +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30 +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0 +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300 +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00 +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000 +#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4 +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8 +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 +#define PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10 +#define PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0 +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100 +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 +#define PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200 +#define PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400 +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800 +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000 +#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc +#define PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40 +#define PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 +#define PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80 +#define PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000 +#define PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc +#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f +#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 +#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00 +#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 +#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000 +#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 +#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000 +#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 +#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f +#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 +#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00 +#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 +#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000 +#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 +#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000 +#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 +#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f +#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 +#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00 +#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 +#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000 +#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 +#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000 +#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 +#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f +#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 +#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00 +#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 +#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000 +#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 +#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000 +#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 +#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f +#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 +#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00 +#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 +#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000 +#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 +#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000 +#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 +#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f +#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 +#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00 +#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 +#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000 +#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 +#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000 +#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 +#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1 +#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 +#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2 +#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 +#define PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c +#define PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 +#define PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0 +#define PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 +#define PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff +#define PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 +#define PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000 +#define PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40 +#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 +#define PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff +#define PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 +#define PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff +#define PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 +#define PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff +#define PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 +#define PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff +#define PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 +#define PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff +#define PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 +#define PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff +#define PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 +#define PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff +#define PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 +#define PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff +#define PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 +#define PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff +#define PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 +#define PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff +#define PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 +#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1 +#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2 +#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4 +#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1 +#define PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0 +#define PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1 +#define PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 +#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2 +#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 +#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4 +#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2 +#define PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8 +#define PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3 +#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10 +#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 +#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20 +#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 +#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40 +#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 +#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80 +#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 +#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100 +#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 +#define PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000 +#define PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc +#define PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000 +#define PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd +#define PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000 +#define PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe +#define PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000 +#define PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 +#define PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff +#define PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 +#define PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000 +#define PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 +#define PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff +#define PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 +#define PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff +#define PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 +#define PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000 +#define PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 +#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff +#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 +#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00 +#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 +#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1 +#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2 +#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 +#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4 +#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff +#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff +#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000 +#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000 +#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 +#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 +#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff +#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000 +#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10 +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000 +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000 +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19 +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000 +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000 +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000 +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000 +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000 +#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f +#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x1 +#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0 +#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2 +#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 +#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4 +#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8 +#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 +#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10 +#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1 +#define PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 +#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000 +#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c +#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000 +#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d +#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f +#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 +#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80 +#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 +#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff +#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000 +#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 +#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000 +#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 +#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff +#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000 +#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 +#define PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff +#define PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff +#define PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK 0x1 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000 +#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 +#define PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff +#define PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff +#define PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 +#define PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff +#define PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 +#define PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1 +#define PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0 +#define PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2 +#define PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1 +#define PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000 +#define PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10 +#define PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000 +#define PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c +#define PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa +#define PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc +#define PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd +#define PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe +#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000 +#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11 +#define PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000 +#define PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000 +#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16 +#define PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK 0x1 +#define PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0 +#define PSX80_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2 +#define PSX80_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1 +#define PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4 +#define PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2 +#define PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8 +#define PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3 +#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK 0x10 +#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4 +#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK 0x20 +#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5 +#define PSX80_BIF_SWRST_COMMAND_1__RESETLC_MASK 0x40 +#define PSX80_BIF_SWRST_COMMAND_1__RESETLC__SHIFT 0x6 +#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100 +#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8 +#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200 +#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9 +#define PSX80_BIF_SWRST_COMMAND_1__RESETMNTR_MASK 0x2000 +#define PSX80_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd +#define PSX80_BIF_SWRST_COMMAND_1__RESETHLTR_MASK 0x4000 +#define PSX80_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe +#define PSX80_BIF_SWRST_COMMAND_1__RESETCPM_MASK 0x8000 +#define PSX80_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT 0xf +#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF0_MASK 0x10000 +#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10 +#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF1_MASK 0x20000 +#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11 +#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000 +#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14 +#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000 +#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15 +#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000 +#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18 +#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000 +#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19 +#define PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000 +#define PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c +#define PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000 +#define PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d +#define PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000 +#define PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000 +#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16 +#define PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1 +#define PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0 +#define PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2 +#define PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1 +#define PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4 +#define PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2 +#define PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8 +#define PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3 +#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10 +#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4 +#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20 +#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5 +#define PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40 +#define PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6 +#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100 +#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8 +#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200 +#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9 +#define PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000 +#define PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd +#define PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000 +#define PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe +#define PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000 +#define PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf +#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000 +#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10 +#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000 +#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11 +#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000 +#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14 +#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000 +#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15 +#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000 +#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18 +#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000 +#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19 +#define PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000 +#define PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c +#define PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000 +#define PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d +#define PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000 +#define PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000 +#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16 +#define PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1 +#define PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0 +#define PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2 +#define PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1 +#define PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4 +#define PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2 +#define PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8 +#define PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3 +#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10 +#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4 +#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20 +#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5 +#define PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40 +#define PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6 +#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100 +#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8 +#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200 +#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9 +#define PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000 +#define PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd +#define PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000 +#define PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe +#define PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000 +#define PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf +#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000 +#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10 +#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000 +#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11 +#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000 +#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14 +#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000 +#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15 +#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000 +#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18 +#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000 +#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19 +#define PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000 +#define PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c +#define PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000 +#define PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d +#define PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000 +#define PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000 +#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16 +#define PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1 +#define PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6 +#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100 +#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8 +#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200 +#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000 +#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19 +#define PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000 +#define PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c +#define PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000 +#define PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d +#define PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1 +#define PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0 +#define PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100 +#define PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8 +#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1 +#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0 +#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2 +#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1 +#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4 +#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2 +#define PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8 +#define PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3 +#define PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10 +#define PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4 +#define PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20 +#define PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5 +#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40 +#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6 +#define PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80 +#define PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7 +#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100 +#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8 +#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200 +#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9 +#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400 +#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa +#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800 +#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb +#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000 +#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc +#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000 +#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd +#define PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000 +#define PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe +#define PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000 +#define PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf +#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000 +#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10 +#define PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000 +#define PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11 +#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000 +#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14 +#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000 +#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15 +#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000 +#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16 +#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000 +#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17 +#define PSX80_BIF_CPM_CONTROL__SPARE_REGS_MASK 0xff000000 +#define PSX80_BIF_CPM_CONTROL__SPARE_REGS__SHIFT 0x18 +#define PSX80_BIF_LM_CONTROL__LoopbackSelect_MASK 0x1e +#define PSX80_BIF_LM_CONTROL__LoopbackSelect__SHIFT 0x1 +#define PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20 +#define PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5 +#define PSX80_BIF_LM_CONTROL__LoopbackHalfRate_MASK 0xc0 +#define PSX80_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT 0x6 +#define PSX80_BIF_LM_CONTROL__LoopbackFifoPtr_MASK 0x700 +#define PSX80_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8 +#define PSX80_BIF_LM_PCIETXMUX0__TXLANE0_MASK 0xff +#define PSX80_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT 0x0 +#define PSX80_BIF_LM_PCIETXMUX0__TXLANE1_MASK 0xff00 +#define PSX80_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT 0x8 +#define PSX80_BIF_LM_PCIETXMUX0__TXLANE2_MASK 0xff0000 +#define PSX80_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT 0x10 +#define PSX80_BIF_LM_PCIETXMUX0__TXLANE3_MASK 0xff000000 +#define PSX80_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT 0x18 +#define PSX80_BIF_LM_PCIETXMUX1__TXLANE4_MASK 0xff +#define PSX80_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT 0x0 +#define PSX80_BIF_LM_PCIETXMUX1__TXLANE5_MASK 0xff00 +#define PSX80_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT 0x8 +#define PSX80_BIF_LM_PCIETXMUX1__TXLANE6_MASK 0xff0000 +#define PSX80_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT 0x10 +#define PSX80_BIF_LM_PCIETXMUX1__TXLANE7_MASK 0xff000000 +#define PSX80_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT 0x18 +#define PSX80_BIF_LM_PCIETXMUX2__TXLANE8_MASK 0xff +#define PSX80_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT 0x0 +#define PSX80_BIF_LM_PCIETXMUX2__TXLANE9_MASK 0xff00 +#define PSX80_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT 0x8 +#define PSX80_BIF_LM_PCIETXMUX2__TXLANE10_MASK 0xff0000 +#define PSX80_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT 0x10 +#define PSX80_BIF_LM_PCIETXMUX2__TXLANE11_MASK 0xff000000 +#define PSX80_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT 0x18 +#define PSX80_BIF_LM_PCIETXMUX3__TXLANE12_MASK 0xff +#define PSX80_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT 0x0 +#define PSX80_BIF_LM_PCIETXMUX3__TXLANE13_MASK 0xff00 +#define PSX80_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT 0x8 +#define PSX80_BIF_LM_PCIETXMUX3__TXLANE14_MASK 0xff0000 +#define PSX80_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT 0x10 +#define PSX80_BIF_LM_PCIETXMUX3__TXLANE15_MASK 0xff000000 +#define PSX80_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT 0x18 +#define PSX80_BIF_LM_PCIERXMUX0__RXLANE0_MASK 0xff +#define PSX80_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT 0x0 +#define PSX80_BIF_LM_PCIERXMUX0__RXLANE1_MASK 0xff00 +#define PSX80_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT 0x8 +#define PSX80_BIF_LM_PCIERXMUX0__RXLANE2_MASK 0xff0000 +#define PSX80_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT 0x10 +#define PSX80_BIF_LM_PCIERXMUX0__RXLANE3_MASK 0xff000000 +#define PSX80_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT 0x18 +#define PSX80_BIF_LM_PCIERXMUX1__RXLANE4_MASK 0xff +#define PSX80_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT 0x0 +#define PSX80_BIF_LM_PCIERXMUX1__RXLANE5_MASK 0xff00 +#define PSX80_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT 0x8 +#define PSX80_BIF_LM_PCIERXMUX1__RXLANE6_MASK 0xff0000 +#define PSX80_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT 0x10 +#define PSX80_BIF_LM_PCIERXMUX1__RXLANE7_MASK 0xff000000 +#define PSX80_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT 0x18 +#define PSX80_BIF_LM_PCIERXMUX2__RXLANE8_MASK 0xff +#define PSX80_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT 0x0 +#define PSX80_BIF_LM_PCIERXMUX2__RXLANE9_MASK 0xff00 +#define PSX80_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT 0x8 +#define PSX80_BIF_LM_PCIERXMUX2__RXLANE10_MASK 0xff0000 +#define PSX80_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT 0x10 +#define PSX80_BIF_LM_PCIERXMUX2__RXLANE11_MASK 0xff000000 +#define PSX80_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT 0x18 +#define PSX80_BIF_LM_PCIERXMUX3__RXLANE12_MASK 0xff +#define PSX80_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT 0x0 +#define PSX80_BIF_LM_PCIERXMUX3__RXLANE13_MASK 0xff00 +#define PSX80_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT 0x8 +#define PSX80_BIF_LM_PCIERXMUX3__RXLANE14_MASK 0xff0000 +#define PSX80_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT 0x10 +#define PSX80_BIF_LM_PCIERXMUX3__RXLANE15_MASK 0xff000000 +#define PSX80_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT 0x18 +#define PSX80_BIF_LM_LANEENABLE__LANE_enable_MASK 0xffff +#define PSX80_BIF_LM_LANEENABLE__LANE_enable__SHIFT 0x0 +#define PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff +#define PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0 +#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000 +#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c +#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000 +#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d +#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000 +#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e +#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000 +#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f +#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7 +#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0 +#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38 +#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3 +#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0 +#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6 +#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700 +#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8 +#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800 +#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb +#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000 +#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe +#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000 +#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10 +#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000 +#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13 +#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000 +#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16 +#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000 +#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18 +#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000 +#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b +#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000 +#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e +#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn0_MASK 0x1 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2 +#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK 0x20 +#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5 +#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40 +#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7 +#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph0_MASK 0x100 +#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn1_MASK 0x200 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb +#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000 +#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe +#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000 +#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10 +#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph1_MASK 0x20000 +#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn2_MASK 0x40000 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14 +#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000 +#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17 +#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000 +#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000 +#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19 +#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000 +#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a +#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000 +#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b +#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000 +#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d +#define PSX80_BIF_LM_POWERCONTROL2__LMTxEn3_MASK 0x1 +#define PSX80_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0 +#define PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2 +#define PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1 +#define PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c +#define PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2 +#define PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK 0x20 +#define PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5 +#define PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40 +#define PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6 +#define PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80 +#define PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7 +#define PSX80_BIF_LM_POWERCONTROL2__LMDeemph3_MASK 0x100 +#define PSX80_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8 +#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK 0x600 +#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9 +#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800 +#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb +#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000 +#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd +#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000 +#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13 +#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000 +#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19 +#define PSX80_BIF_LM_POWERCONTROL3__TxCoeff3_MASK 0x3f +#define PSX80_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0 +#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0 +#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6 +#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000 +#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc +#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000 +#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12 +#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000 +#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18 +#define PSX80_BIF_LM_POWERCONTROL4__LinkNum0_MASK 0x7 +#define PSX80_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT 0x0 +#define PSX80_BIF_LM_POWERCONTROL4__LinkNum1_MASK 0x38 +#define PSX80_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT 0x3 +#define PSX80_BIF_LM_POWERCONTROL4__LinkNum2_MASK 0x1c0 +#define PSX80_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT 0x6 +#define PSX80_BIF_LM_POWERCONTROL4__LinkNum3_MASK 0xe00 +#define PSX80_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT 0x9 +#define PSX80_BIF_LM_POWERCONTROL4__LaneNum0_MASK 0xf000 +#define PSX80_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT 0xc +#define PSX80_BIF_LM_POWERCONTROL4__LaneNum1_MASK 0xf0000 +#define PSX80_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT 0x10 +#define PSX80_BIF_LM_POWERCONTROL4__LaneNum2_MASK 0xf00000 +#define PSX80_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT 0x14 +#define PSX80_BIF_LM_POWERCONTROL4__LaneNum3_MASK 0xf000000 +#define PSX80_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT 0x18 +#define PSX80_BIF_LM_POWERCONTROL4__SpcMode0_MASK 0x10000000 +#define PSX80_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c +#define PSX80_BIF_LM_POWERCONTROL4__SpcMode1_MASK 0x20000000 +#define PSX80_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d +#define PSX80_BIF_LM_POWERCONTROL4__SpcMode2_MASK 0x40000000 +#define PSX80_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e +#define PSX80_BIF_LM_POWERCONTROL4__SpcMode3_MASK 0x80000000 +#define PSX80_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f +#define PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff +#define PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff +#define PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff +#define PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 +#define PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff +#define PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 +#define PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1 +#define PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe +#define PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 +#define PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80 +#define PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100 +#define PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200 +#define PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 +#define PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00 +#define PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa +#define PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf +#define PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000 +#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 +#define PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000 +#define PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 +#define PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000 +#define PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 +#define PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000 +#define PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000 +#define PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f +#define PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf +#define PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000 +#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff +#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 +#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100 +#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 +#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000 +#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 +#define PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1 +#define PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 +#define PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e +#define PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 +#define PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0 +#define PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 +#define PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800 +#define PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb +#define PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000 +#define PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc +#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000 +#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd +#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000 +#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe +#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 +#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 +#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000 +#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 +#define PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000 +#define PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 +#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000 +#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 +#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000 +#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 +#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000 +#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 +#define PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000 +#define PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 +#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000 +#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 +#define PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000 +#define PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 +#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000 +#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d +#define PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000 +#define PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e +#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000 +#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 +#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000 +#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc +#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000 +#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd +#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000 +#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe +#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000 +#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 +#define PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000 +#define PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3 +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30 +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0 +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300 +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00 +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000 +#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4 +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8 +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 +#define PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10 +#define PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0 +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100 +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 +#define PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200 +#define PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400 +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800 +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000 +#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc +#define PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40 +#define PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 +#define PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80 +#define PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000 +#define PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc +#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f +#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 +#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00 +#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 +#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000 +#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 +#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000 +#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 +#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f +#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 +#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00 +#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 +#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000 +#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 +#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000 +#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 +#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f +#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 +#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00 +#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 +#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000 +#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 +#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000 +#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 +#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f +#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 +#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00 +#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 +#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000 +#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 +#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000 +#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 +#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f +#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 +#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00 +#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 +#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000 +#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 +#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000 +#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 +#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f +#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 +#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00 +#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 +#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000 +#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 +#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000 +#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 +#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1 +#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 +#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2 +#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 +#define PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c +#define PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 +#define PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0 +#define PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 +#define PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff +#define PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 +#define PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000 +#define PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40 +#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 +#define PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff +#define PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 +#define PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff +#define PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 +#define PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff +#define PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 +#define PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff +#define PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 +#define PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff +#define PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 +#define PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff +#define PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 +#define PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff +#define PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 +#define PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff +#define PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 +#define PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff +#define PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 +#define PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff +#define PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 +#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1 +#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2 +#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4 +#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1 +#define PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0 +#define PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1 +#define PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 +#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2 +#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 +#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4 +#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2 +#define PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8 +#define PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3 +#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10 +#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 +#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20 +#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 +#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40 +#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 +#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80 +#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 +#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100 +#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 +#define PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000 +#define PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc +#define PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000 +#define PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd +#define PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000 +#define PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe +#define PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000 +#define PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 +#define PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff +#define PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 +#define PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000 +#define PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 +#define PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff +#define PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 +#define PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff +#define PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 +#define PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000 +#define PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 +#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff +#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 +#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00 +#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 +#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1 +#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2 +#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 +#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4 +#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff +#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff +#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000 +#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 +#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000 +#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000 +#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 +#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 +#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff +#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000 +#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10 +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000 +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000 +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19 +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000 +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000 +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000 +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000 +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000 +#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f +#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x1 +#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0 +#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2 +#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 +#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4 +#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8 +#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 +#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10 +#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1 +#define PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 +#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000 +#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c +#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000 +#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d +#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f +#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 +#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80 +#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 +#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff +#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000 +#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 +#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000 +#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 +#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff +#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000 +#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 +#define PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff +#define PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff +#define PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK 0x1 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000 +#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 +#define PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff +#define PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff +#define PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 +#define PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff +#define PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 +#define PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1 +#define PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0 +#define PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2 +#define PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1 +#define PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000 +#define PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10 +#define PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000 +#define PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c +#define PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa +#define PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc +#define PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd +#define PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe +#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000 +#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11 +#define PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000 +#define PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000 +#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16 +#define PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK 0x1 +#define PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0 +#define PSX81_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2 +#define PSX81_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1 +#define PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4 +#define PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2 +#define PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8 +#define PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3 +#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK 0x10 +#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4 +#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK 0x20 +#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5 +#define PSX81_BIF_SWRST_COMMAND_1__RESETLC_MASK 0x40 +#define PSX81_BIF_SWRST_COMMAND_1__RESETLC__SHIFT 0x6 +#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100 +#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8 +#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200 +#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9 +#define PSX81_BIF_SWRST_COMMAND_1__RESETMNTR_MASK 0x2000 +#define PSX81_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd +#define PSX81_BIF_SWRST_COMMAND_1__RESETHLTR_MASK 0x4000 +#define PSX81_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe +#define PSX81_BIF_SWRST_COMMAND_1__RESETCPM_MASK 0x8000 +#define PSX81_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT 0xf +#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF0_MASK 0x10000 +#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10 +#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF1_MASK 0x20000 +#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11 +#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000 +#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14 +#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000 +#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15 +#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000 +#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18 +#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000 +#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19 +#define PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000 +#define PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c +#define PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000 +#define PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d +#define PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000 +#define PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000 +#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16 +#define PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1 +#define PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0 +#define PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2 +#define PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1 +#define PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4 +#define PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2 +#define PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8 +#define PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3 +#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10 +#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4 +#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20 +#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5 +#define PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40 +#define PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6 +#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100 +#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8 +#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200 +#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9 +#define PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000 +#define PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd +#define PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000 +#define PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe +#define PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000 +#define PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf +#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000 +#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10 +#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000 +#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11 +#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000 +#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14 +#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000 +#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15 +#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000 +#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18 +#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000 +#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19 +#define PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000 +#define PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c +#define PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000 +#define PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d +#define PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000 +#define PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000 +#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16 +#define PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1 +#define PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0 +#define PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2 +#define PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1 +#define PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4 +#define PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2 +#define PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8 +#define PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3 +#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10 +#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4 +#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20 +#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5 +#define PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40 +#define PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6 +#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100 +#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8 +#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200 +#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9 +#define PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000 +#define PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd +#define PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000 +#define PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe +#define PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000 +#define PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf +#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000 +#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10 +#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000 +#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11 +#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000 +#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14 +#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000 +#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15 +#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000 +#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18 +#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000 +#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19 +#define PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000 +#define PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c +#define PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000 +#define PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d +#define PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000 +#define PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000 +#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16 +#define PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1 +#define PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6 +#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100 +#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8 +#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200 +#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000 +#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19 +#define PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000 +#define PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c +#define PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000 +#define PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d +#define PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1 +#define PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0 +#define PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100 +#define PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8 +#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1 +#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0 +#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2 +#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1 +#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4 +#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2 +#define PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8 +#define PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3 +#define PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10 +#define PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4 +#define PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20 +#define PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5 +#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40 +#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6 +#define PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80 +#define PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7 +#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100 +#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8 +#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200 +#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9 +#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400 +#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa +#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800 +#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb +#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000 +#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc +#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000 +#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd +#define PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000 +#define PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe +#define PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000 +#define PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf +#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000 +#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10 +#define PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000 +#define PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11 +#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000 +#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14 +#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000 +#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15 +#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000 +#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16 +#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000 +#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17 +#define PSX81_BIF_CPM_CONTROL__SPARE_REGS_MASK 0xff000000 +#define PSX81_BIF_CPM_CONTROL__SPARE_REGS__SHIFT 0x18 +#define PSX81_BIF_LM_CONTROL__LoopbackSelect_MASK 0x1e +#define PSX81_BIF_LM_CONTROL__LoopbackSelect__SHIFT 0x1 +#define PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20 +#define PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5 +#define PSX81_BIF_LM_CONTROL__LoopbackHalfRate_MASK 0xc0 +#define PSX81_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT 0x6 +#define PSX81_BIF_LM_CONTROL__LoopbackFifoPtr_MASK 0x700 +#define PSX81_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8 +#define PSX81_BIF_LM_PCIETXMUX0__TXLANE0_MASK 0xff +#define PSX81_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT 0x0 +#define PSX81_BIF_LM_PCIETXMUX0__TXLANE1_MASK 0xff00 +#define PSX81_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT 0x8 +#define PSX81_BIF_LM_PCIETXMUX0__TXLANE2_MASK 0xff0000 +#define PSX81_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT 0x10 +#define PSX81_BIF_LM_PCIETXMUX0__TXLANE3_MASK 0xff000000 +#define PSX81_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT 0x18 +#define PSX81_BIF_LM_PCIETXMUX1__TXLANE4_MASK 0xff +#define PSX81_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT 0x0 +#define PSX81_BIF_LM_PCIETXMUX1__TXLANE5_MASK 0xff00 +#define PSX81_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT 0x8 +#define PSX81_BIF_LM_PCIETXMUX1__TXLANE6_MASK 0xff0000 +#define PSX81_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT 0x10 +#define PSX81_BIF_LM_PCIETXMUX1__TXLANE7_MASK 0xff000000 +#define PSX81_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT 0x18 +#define PSX81_BIF_LM_PCIETXMUX2__TXLANE8_MASK 0xff +#define PSX81_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT 0x0 +#define PSX81_BIF_LM_PCIETXMUX2__TXLANE9_MASK 0xff00 +#define PSX81_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT 0x8 +#define PSX81_BIF_LM_PCIETXMUX2__TXLANE10_MASK 0xff0000 +#define PSX81_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT 0x10 +#define PSX81_BIF_LM_PCIETXMUX2__TXLANE11_MASK 0xff000000 +#define PSX81_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT 0x18 +#define PSX81_BIF_LM_PCIETXMUX3__TXLANE12_MASK 0xff +#define PSX81_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT 0x0 +#define PSX81_BIF_LM_PCIETXMUX3__TXLANE13_MASK 0xff00 +#define PSX81_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT 0x8 +#define PSX81_BIF_LM_PCIETXMUX3__TXLANE14_MASK 0xff0000 +#define PSX81_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT 0x10 +#define PSX81_BIF_LM_PCIETXMUX3__TXLANE15_MASK 0xff000000 +#define PSX81_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT 0x18 +#define PSX81_BIF_LM_PCIERXMUX0__RXLANE0_MASK 0xff +#define PSX81_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT 0x0 +#define PSX81_BIF_LM_PCIERXMUX0__RXLANE1_MASK 0xff00 +#define PSX81_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT 0x8 +#define PSX81_BIF_LM_PCIERXMUX0__RXLANE2_MASK 0xff0000 +#define PSX81_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT 0x10 +#define PSX81_BIF_LM_PCIERXMUX0__RXLANE3_MASK 0xff000000 +#define PSX81_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT 0x18 +#define PSX81_BIF_LM_PCIERXMUX1__RXLANE4_MASK 0xff +#define PSX81_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT 0x0 +#define PSX81_BIF_LM_PCIERXMUX1__RXLANE5_MASK 0xff00 +#define PSX81_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT 0x8 +#define PSX81_BIF_LM_PCIERXMUX1__RXLANE6_MASK 0xff0000 +#define PSX81_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT 0x10 +#define PSX81_BIF_LM_PCIERXMUX1__RXLANE7_MASK 0xff000000 +#define PSX81_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT 0x18 +#define PSX81_BIF_LM_PCIERXMUX2__RXLANE8_MASK 0xff +#define PSX81_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT 0x0 +#define PSX81_BIF_LM_PCIERXMUX2__RXLANE9_MASK 0xff00 +#define PSX81_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT 0x8 +#define PSX81_BIF_LM_PCIERXMUX2__RXLANE10_MASK 0xff0000 +#define PSX81_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT 0x10 +#define PSX81_BIF_LM_PCIERXMUX2__RXLANE11_MASK 0xff000000 +#define PSX81_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT 0x18 +#define PSX81_BIF_LM_PCIERXMUX3__RXLANE12_MASK 0xff +#define PSX81_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT 0x0 +#define PSX81_BIF_LM_PCIERXMUX3__RXLANE13_MASK 0xff00 +#define PSX81_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT 0x8 +#define PSX81_BIF_LM_PCIERXMUX3__RXLANE14_MASK 0xff0000 +#define PSX81_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT 0x10 +#define PSX81_BIF_LM_PCIERXMUX3__RXLANE15_MASK 0xff000000 +#define PSX81_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT 0x18 +#define PSX81_BIF_LM_LANEENABLE__LANE_enable_MASK 0xffff +#define PSX81_BIF_LM_LANEENABLE__LANE_enable__SHIFT 0x0 +#define PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff +#define PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0 +#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000 +#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c +#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000 +#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d +#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000 +#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e +#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000 +#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f +#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7 +#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0 +#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38 +#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3 +#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0 +#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6 +#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700 +#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8 +#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800 +#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb +#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000 +#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe +#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000 +#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10 +#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000 +#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13 +#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000 +#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16 +#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000 +#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18 +#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000 +#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b +#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000 +#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e +#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn0_MASK 0x1 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2 +#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK 0x20 +#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5 +#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40 +#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7 +#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph0_MASK 0x100 +#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn1_MASK 0x200 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb +#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000 +#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe +#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000 +#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10 +#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph1_MASK 0x20000 +#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn2_MASK 0x40000 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14 +#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000 +#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17 +#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000 +#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000 +#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19 +#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000 +#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a +#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000 +#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b +#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000 +#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d +#define PSX81_BIF_LM_POWERCONTROL2__LMTxEn3_MASK 0x1 +#define PSX81_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0 +#define PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2 +#define PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1 +#define PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c +#define PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2 +#define PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK 0x20 +#define PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5 +#define PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40 +#define PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6 +#define PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80 +#define PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7 +#define PSX81_BIF_LM_POWERCONTROL2__LMDeemph3_MASK 0x100 +#define PSX81_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8 +#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK 0x600 +#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9 +#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800 +#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb +#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000 +#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd +#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000 +#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13 +#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000 +#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19 +#define PSX81_BIF_LM_POWERCONTROL3__TxCoeff3_MASK 0x3f +#define PSX81_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0 +#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0 +#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6 +#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000 +#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc +#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000 +#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12 +#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000 +#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18 +#define PSX81_BIF_LM_POWERCONTROL4__LinkNum0_MASK 0x7 +#define PSX81_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT 0x0 +#define PSX81_BIF_LM_POWERCONTROL4__LinkNum1_MASK 0x38 +#define PSX81_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT 0x3 +#define PSX81_BIF_LM_POWERCONTROL4__LinkNum2_MASK 0x1c0 +#define PSX81_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT 0x6 +#define PSX81_BIF_LM_POWERCONTROL4__LinkNum3_MASK 0xe00 +#define PSX81_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT 0x9 +#define PSX81_BIF_LM_POWERCONTROL4__LaneNum0_MASK 0xf000 +#define PSX81_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT 0xc +#define PSX81_BIF_LM_POWERCONTROL4__LaneNum1_MASK 0xf0000 +#define PSX81_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT 0x10 +#define PSX81_BIF_LM_POWERCONTROL4__LaneNum2_MASK 0xf00000 +#define PSX81_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT 0x14 +#define PSX81_BIF_LM_POWERCONTROL4__LaneNum3_MASK 0xf000000 +#define PSX81_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT 0x18 +#define PSX81_BIF_LM_POWERCONTROL4__SpcMode0_MASK 0x10000000 +#define PSX81_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c +#define PSX81_BIF_LM_POWERCONTROL4__SpcMode1_MASK 0x20000000 +#define PSX81_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d +#define PSX81_BIF_LM_POWERCONTROL4__SpcMode2_MASK 0x40000000 +#define PSX81_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e +#define PSX81_BIF_LM_POWERCONTROL4__SpcMode3_MASK 0x80000000 +#define PSX81_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK 0x1 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK 0x6 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT 0x1 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK 0x8 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT 0x3 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK 0xf0 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT 0x4 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK 0x100 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT 0x8 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x600 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0x9 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x1800 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0xb +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK 0xc0000 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT 0x12 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK 0xfff00000 +#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT 0x14 +#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK 0x1 +#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK 0xfffffffe +#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT 0x1 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK 0x1 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK 0xe +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT 0x1 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK 0x3f0 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT 0x4 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK 0xfc00 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT 0xa +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK 0xf0000 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT 0x10 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK 0xf00000 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT 0x14 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK 0xf000000 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT 0x18 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK 0x10000000 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT 0x1c +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK 0xe0000000 +#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d +#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK 0x1 +#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2 +#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT 0x1 +#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK 0x4 +#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2 +#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK 0x3f0 +#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT 0x4 +#define PSX80_PHY0_COM_COMMON_DFX__nelb_en_MASK 0x1 +#define PSX80_PHY0_COM_COMMON_DFX__nelb_en__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_DFX__prbs_seed_MASK 0x7fe +#define PSX80_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT 0x1 +#define PSX80_PHY0_COM_COMMON_DFX__force_cdr_en_MASK 0x800 +#define PSX80_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT 0xb +#define PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK 0x2000 +#define PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT 0xd +#define PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK 0x8000 +#define PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT 0xf +#define PSX80_PHY0_COM_COMMON_DFX__dsm_sel_MASK 0x7e0000 +#define PSX80_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT 0x11 +#define PSX80_PHY0_COM_COMMON_DFX__dsm_en_MASK 0xf000000 +#define PSX80_PHY0_COM_COMMON_DFX__dsm_en__SHIFT 0x18 +#define PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK 0x20000000 +#define PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT 0x1d +#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff +#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00 +#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 +#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000 +#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 +#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000 +#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK 0xff +#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK 0xff00 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT 0x8 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK 0xff0000 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT 0x10 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK 0xff000000 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT 0x18 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK 0xff +#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK 0xff00 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT 0x8 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK 0xff0000 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT 0x10 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK 0xff000000 +#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT 0x18 +#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf +#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0 +#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK 0x7 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK 0xf0 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT 0x4 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK 0x1e00 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT 0x9 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK 0x3c000 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT 0xe +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK 0x780000 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT 0x13 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK 0x1e000000 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT 0x19 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK 0xe0000000 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT 0x1d +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK 0x3 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK 0x78 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT 0x3 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK 0xf00 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT 0x8 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK 0x1e000 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT 0xd +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK 0x3c0000 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT 0x12 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK 0x3800000 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT 0x17 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK 0x38000000 +#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT 0x1b +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK 0x1f +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK 0x7c0 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT 0x6 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK 0xe000 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT 0xd +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK 0xe0000 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT 0x11 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK 0xfc00000 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT 0x16 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK 0x3f +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK 0xf00 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT 0x8 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK 0x1e000 +#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT 0xd +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK 0x1ff +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK 0xff800 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT 0xb +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK 0x7fc00000 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT 0x16 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK 0x3f +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK 0x1f80 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT 0x7 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK 0x7 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK 0x1c0 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT 0x6 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK 0x3fffc00 +#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT 0xa +#define PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK 0x20 +#define PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT 0x5 +#define PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK 0xc0 +#define PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT 0x6 +#define PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK 0x300 +#define PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT 0x8 +#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK 0x1f +#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK 0x40 +#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT 0x6 +#define PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK 0x70 +#define PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT 0x4 +#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK 0x1 +#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK 0x780 +#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT 0x7 +#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK 0x7e000 +#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT 0xd +#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK 0x1 +#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT 0x0 +#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK 0x3c +#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2 +#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK 0x780 +#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT 0x7 +#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK 0x1ff000 +#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT 0xc +#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK 0xc00000 +#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT 0x16 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK 0x7 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK 0x18 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK 0x20 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT 0x5 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK 0x7 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK 0x18 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK 0x20 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT 0x5 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK 0x7 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK 0x18 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK 0x20 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT 0x5 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK 0x7 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK 0x18 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK 0x20 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT 0x5 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK 0x7 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK 0x18 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK 0x20 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT 0x5 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK 0x7 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK 0x18 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK 0x20 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT 0x5 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK 0x7 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK 0x18 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK 0x20 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT 0x5 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK 0x7 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK 0x18 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK 0x20 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT 0x5 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK 0x7 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK 0x18 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK 0x20 +#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT 0x5 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK 0x6 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK 0x8 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK 0x6 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK 0x8 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK 0x6 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK 0x8 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK 0x6 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK 0x8 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK 0x6 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK 0x8 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK 0x6 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK 0x8 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK 0x6 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK 0x8 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK 0x6 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK 0x8 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK 0x6 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT 0x1 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK 0x8 +#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK 0x1 +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT 0x0 +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK 0x1fe +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT 0x1 +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK 0x1800 +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT 0xb +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK 0x2000 +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT 0xd +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK 0x8000 +#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT 0xf +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT 0x0 +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK 0x1fe +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK 0x1800 +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT 0xb +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK 0x2000 +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT 0xd +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK 0x8000 +#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT 0xf +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT 0x0 +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK 0x1fe +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK 0x1800 +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT 0xb +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK 0x2000 +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT 0xd +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK 0x8000 +#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT 0xf +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT 0x0 +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK 0x1fe +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK 0x1800 +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT 0xb +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK 0x2000 +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT 0xd +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK 0x8000 +#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT 0xf +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT 0x0 +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK 0x1fe +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK 0x1800 +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT 0xb +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK 0x2000 +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT 0xd +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK 0x8000 +#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT 0xf +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT 0x0 +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK 0x1fe +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK 0x1800 +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT 0xb +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK 0x2000 +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT 0xd +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK 0x8000 +#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT 0xf +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT 0x0 +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK 0x1fe +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK 0x1800 +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT 0xb +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK 0x2000 +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT 0xd +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK 0x8000 +#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT 0xf +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT 0x0 +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK 0x1fe +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK 0x1800 +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT 0xb +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK 0x2000 +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT 0xd +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK 0x8000 +#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT 0xf +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT 0x0 +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK 0x1fe +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT 0x1 +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK 0x1800 +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT 0xb +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK 0x2000 +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT 0xd +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK 0x8000 +#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT 0xf +#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK 0x7 +#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK 0x20 +#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT 0x5 +#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK 0x80 +#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK 0x20 +#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT 0x5 +#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK 0x80 +#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK 0x20 +#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT 0x5 +#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK 0x80 +#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK 0x20 +#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT 0x5 +#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK 0x80 +#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK 0x20 +#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT 0x5 +#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK 0x80 +#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK 0x20 +#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT 0x5 +#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK 0x80 +#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK 0x20 +#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT 0x5 +#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK 0x80 +#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK 0x20 +#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT 0x5 +#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK 0x80 +#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK 0x7 +#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK 0x20 +#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT 0x5 +#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK 0x80 +#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT 0x7 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT 0x0 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK 0x10 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT 0x4 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK 0x20 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT 0x5 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK 0x40 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT 0x6 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK 0x80 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT 0x7 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK 0x100 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT 0x8 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK 0x400 +#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT 0xa +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT 0x0 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK 0x10 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT 0x4 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK 0x20 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT 0x5 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK 0x40 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT 0x6 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK 0x80 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT 0x7 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK 0x100 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT 0x8 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK 0x400 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT 0xa +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT 0x0 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK 0x10 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT 0x4 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK 0x20 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT 0x5 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK 0x40 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT 0x6 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK 0x80 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT 0x7 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK 0x100 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT 0x8 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK 0x400 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT 0xa +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT 0x0 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK 0x10 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT 0x4 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK 0x20 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT 0x5 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK 0x40 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT 0x6 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK 0x80 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT 0x7 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK 0x100 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT 0x8 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK 0x400 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT 0xa +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT 0x0 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK 0x10 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT 0x4 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK 0x20 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT 0x5 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK 0x40 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT 0x6 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK 0x80 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT 0x7 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK 0x100 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT 0x8 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK 0x400 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT 0xa +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT 0x0 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK 0x10 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT 0x4 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK 0x20 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT 0x5 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK 0x40 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT 0x6 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK 0x80 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT 0x7 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK 0x100 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT 0x8 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK 0x400 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT 0xa +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT 0x0 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK 0x10 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT 0x4 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK 0x20 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT 0x5 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK 0x40 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT 0x6 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK 0x80 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT 0x7 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK 0x100 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT 0x8 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK 0x400 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT 0xa +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT 0x0 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK 0x10 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT 0x4 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK 0x20 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT 0x5 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK 0x40 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT 0x6 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK 0x80 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT 0x7 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK 0x100 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT 0x8 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK 0x400 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT 0xa +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT 0x0 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT 0x1 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK 0x10 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT 0x4 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK 0x20 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT 0x5 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK 0x40 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT 0x6 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK 0x80 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT 0x7 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK 0x100 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT 0x8 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK 0x400 +#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT 0xa +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT 0x0 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK 0x1f8 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT 0x3 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK 0x400 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT 0xa +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT 0x0 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK 0x1f8 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT 0x3 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK 0x400 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT 0xa +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT 0x0 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK 0x1f8 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT 0x3 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK 0x400 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT 0xa +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT 0x0 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK 0x1f8 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT 0x3 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK 0x400 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT 0xa +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT 0x0 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK 0x1f8 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT 0x3 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK 0x400 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT 0xa +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT 0x0 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK 0x1f8 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT 0x3 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK 0x400 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT 0xa +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT 0x0 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK 0x1f8 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT 0x3 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK 0x400 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT 0xa +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT 0x0 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK 0x1f8 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT 0x3 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK 0x400 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT 0xa +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT 0x0 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK 0x1f8 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT 0x3 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK 0x400 +#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT 0xa +#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK 0x3ff +#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK 0xe000 +#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT 0xd +#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK 0x3ff +#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK 0xe000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT 0xd +#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK 0x3ff +#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK 0xe000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT 0xd +#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK 0x3ff +#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK 0xe000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT 0xd +#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK 0x3ff +#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK 0xe000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT 0xd +#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK 0x3ff +#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK 0xe000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT 0xd +#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK 0x3ff +#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK 0xe000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT 0xd +#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK 0x3ff +#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK 0xe000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT 0xd +#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK 0x3ff +#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK 0xe000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT 0xd +#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT 0x0 +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK 0x1fe +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK 0x800 +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT 0xb +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK 0x1000 +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT 0xc +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK 0x2000 +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT 0xd +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK 0x4000 +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT 0xe +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK 0x10000 +#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT 0x10 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT 0x0 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK 0x1fe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK 0x800 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT 0xb +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK 0x1000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT 0xc +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK 0x2000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT 0xd +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK 0x4000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT 0xe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK 0x10000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT 0x10 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT 0x0 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK 0x1fe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK 0x800 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT 0xb +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK 0x1000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT 0xc +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK 0x2000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT 0xd +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK 0x4000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT 0xe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK 0x10000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT 0x10 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT 0x0 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK 0x1fe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK 0x800 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT 0xb +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK 0x1000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT 0xc +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK 0x2000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT 0xd +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK 0x4000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT 0xe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK 0x10000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT 0x10 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT 0x0 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK 0x1fe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK 0x800 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT 0xb +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK 0x1000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT 0xc +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK 0x2000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT 0xd +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK 0x4000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT 0xe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK 0x10000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT 0x10 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT 0x0 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK 0x1fe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK 0x800 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT 0xb +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK 0x1000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT 0xc +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK 0x2000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT 0xd +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK 0x4000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT 0xe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK 0x10000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT 0x10 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT 0x0 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK 0x1fe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK 0x800 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT 0xb +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK 0x1000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT 0xc +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK 0x2000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT 0xd +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK 0x4000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT 0xe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK 0x10000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT 0x10 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT 0x0 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK 0x1fe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK 0x800 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT 0xb +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK 0x1000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT 0xc +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK 0x2000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT 0xd +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK 0x4000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT 0xe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK 0x10000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT 0x10 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT 0x0 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK 0x1fe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT 0x1 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK 0x800 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT 0xb +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK 0x1000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT 0xc +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK 0x2000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT 0xd +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK 0x4000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT 0xe +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK 0x10000 +#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT 0x10 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK 0x40 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT 0x6 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK 0x80 +#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT 0x7 +#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK 0xf +#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK 0x80000 +#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK 0x100000 +#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT 0x14 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK 0xf +#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK 0x80000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK 0x100000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT 0x14 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK 0xf +#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK 0x80000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK 0x100000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT 0x14 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK 0xf +#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK 0x80000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK 0x100000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT 0x14 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK 0xf +#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK 0x80000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK 0x100000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT 0x14 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK 0xf +#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK 0x80000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK 0x100000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT 0x14 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK 0xf +#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK 0x80000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK 0x100000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT 0x14 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK 0xf +#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK 0x80000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK 0x100000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT 0x14 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK 0xf +#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK 0x80000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK 0x100000 +#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT 0x14 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK 0x7 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK 0x18 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK 0x7 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK 0x18 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK 0x7 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK 0x18 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK 0x7 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK 0x18 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK 0x7 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK 0x18 +#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT 0x3 +#define PSX80_PHY0_TX_DFX_BROADCAST__obs_en_MASK 0x1 +#define PSX80_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT 0x0 +#define PSX80_PHY0_TX_DFX_BROADCAST__obs_sel_MASK 0x4 +#define PSX80_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2 +#define PSX80_PHY0_TX_DFX_BROADCAST__felb_en_MASK 0x10 +#define PSX80_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT 0x4 +#define PSX80_PHY0_TX_DFX_BROADCAST__prbs_en_MASK 0x100 +#define PSX80_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT 0x8 +#define PSX80_PHY0_TX_DFX_LANE0__obs_en_MASK 0x1 +#define PSX80_PHY0_TX_DFX_LANE0__obs_en__SHIFT 0x0 +#define PSX80_PHY0_TX_DFX_LANE0__obs_sel_MASK 0x4 +#define PSX80_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2 +#define PSX80_PHY0_TX_DFX_LANE0__felb_en_MASK 0x10 +#define PSX80_PHY0_TX_DFX_LANE0__felb_en__SHIFT 0x4 +#define PSX80_PHY0_TX_DFX_LANE0__prbs_en_MASK 0x100 +#define PSX80_PHY0_TX_DFX_LANE0__prbs_en__SHIFT 0x8 +#define PSX80_PHY0_TX_DFX_LANE1__obs_en_MASK 0x1 +#define PSX80_PHY0_TX_DFX_LANE1__obs_en__SHIFT 0x0 +#define PSX80_PHY0_TX_DFX_LANE1__obs_sel_MASK 0x4 +#define PSX80_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2 +#define PSX80_PHY0_TX_DFX_LANE1__felb_en_MASK 0x10 +#define PSX80_PHY0_TX_DFX_LANE1__felb_en__SHIFT 0x4 +#define PSX80_PHY0_TX_DFX_LANE1__prbs_en_MASK 0x100 +#define PSX80_PHY0_TX_DFX_LANE1__prbs_en__SHIFT 0x8 +#define PSX80_PHY0_TX_DFX_LANE2__obs_en_MASK 0x1 +#define PSX80_PHY0_TX_DFX_LANE2__obs_en__SHIFT 0x0 +#define PSX80_PHY0_TX_DFX_LANE2__obs_sel_MASK 0x4 +#define PSX80_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2 +#define PSX80_PHY0_TX_DFX_LANE2__felb_en_MASK 0x10 +#define PSX80_PHY0_TX_DFX_LANE2__felb_en__SHIFT 0x4 +#define PSX80_PHY0_TX_DFX_LANE2__prbs_en_MASK 0x100 +#define PSX80_PHY0_TX_DFX_LANE2__prbs_en__SHIFT 0x8 +#define PSX80_PHY0_TX_DFX_LANE3__obs_en_MASK 0x1 +#define PSX80_PHY0_TX_DFX_LANE3__obs_en__SHIFT 0x0 +#define PSX80_PHY0_TX_DFX_LANE3__obs_sel_MASK 0x4 +#define PSX80_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2 +#define PSX80_PHY0_TX_DFX_LANE3__felb_en_MASK 0x10 +#define PSX80_PHY0_TX_DFX_LANE3__felb_en__SHIFT 0x4 +#define PSX80_PHY0_TX_DFX_LANE3__prbs_en_MASK 0x100 +#define PSX80_PHY0_TX_DFX_LANE3__prbs_en__SHIFT 0x8 +#define PSX80_PHY0_TX_DFX_LANE4__obs_en_MASK 0x1 +#define PSX80_PHY0_TX_DFX_LANE4__obs_en__SHIFT 0x0 +#define PSX80_PHY0_TX_DFX_LANE4__obs_sel_MASK 0x4 +#define PSX80_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2 +#define PSX80_PHY0_TX_DFX_LANE4__felb_en_MASK 0x10 +#define PSX80_PHY0_TX_DFX_LANE4__felb_en__SHIFT 0x4 +#define PSX80_PHY0_TX_DFX_LANE4__prbs_en_MASK 0x100 +#define PSX80_PHY0_TX_DFX_LANE4__prbs_en__SHIFT 0x8 +#define PSX80_PHY0_TX_DFX_LANE5__obs_en_MASK 0x1 +#define PSX80_PHY0_TX_DFX_LANE5__obs_en__SHIFT 0x0 +#define PSX80_PHY0_TX_DFX_LANE5__obs_sel_MASK 0x4 +#define PSX80_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2 +#define PSX80_PHY0_TX_DFX_LANE5__felb_en_MASK 0x10 +#define PSX80_PHY0_TX_DFX_LANE5__felb_en__SHIFT 0x4 +#define PSX80_PHY0_TX_DFX_LANE5__prbs_en_MASK 0x100 +#define PSX80_PHY0_TX_DFX_LANE5__prbs_en__SHIFT 0x8 +#define PSX80_PHY0_TX_DFX_LANE6__obs_en_MASK 0x1 +#define PSX80_PHY0_TX_DFX_LANE6__obs_en__SHIFT 0x0 +#define PSX80_PHY0_TX_DFX_LANE6__obs_sel_MASK 0x4 +#define PSX80_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2 +#define PSX80_PHY0_TX_DFX_LANE6__felb_en_MASK 0x10 +#define PSX80_PHY0_TX_DFX_LANE6__felb_en__SHIFT 0x4 +#define PSX80_PHY0_TX_DFX_LANE6__prbs_en_MASK 0x100 +#define PSX80_PHY0_TX_DFX_LANE6__prbs_en__SHIFT 0x8 +#define PSX80_PHY0_TX_DFX_LANE7__obs_en_MASK 0x1 +#define PSX80_PHY0_TX_DFX_LANE7__obs_en__SHIFT 0x0 +#define PSX80_PHY0_TX_DFX_LANE7__obs_sel_MASK 0x4 +#define PSX80_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2 +#define PSX80_PHY0_TX_DFX_LANE7__felb_en_MASK 0x10 +#define PSX80_PHY0_TX_DFX_LANE7__felb_en__SHIFT 0x4 +#define PSX80_PHY0_TX_DFX_LANE7__prbs_en_MASK 0x100 +#define PSX80_PHY0_TX_DFX_LANE7__prbs_en__SHIFT 0x8 +#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK 0xff +#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT 0x0 +#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK 0x3f00 +#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT 0x8 +#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK 0xff0000 +#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT 0x10 +#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK 0xff +#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT 0x0 +#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK 0x3f00 +#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT 0x8 +#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK 0xff0000 +#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT 0x10 +#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK 0xff +#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT 0x0 +#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK 0x3f00 +#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT 0x8 +#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK 0xff0000 +#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT 0x10 +#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK 0xff +#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT 0x0 +#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK 0x3f00 +#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT 0x8 +#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK 0xff0000 +#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT 0x10 +#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK 0xff +#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT 0x0 +#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK 0x3f00 +#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT 0x8 +#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK 0xff0000 +#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT 0x10 +#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK 0xff +#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT 0x0 +#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK 0x3f00 +#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT 0x8 +#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK 0xff0000 +#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT 0x10 +#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK 0xff +#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT 0x0 +#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK 0x3f00 +#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT 0x8 +#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK 0xff0000 +#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT 0x10 +#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK 0xff +#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT 0x0 +#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK 0x3f00 +#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT 0x8 +#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK 0xff0000 +#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT 0x10 +#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK 0xff +#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT 0x0 +#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK 0x3f00 +#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT 0x8 +#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK 0xff0000 +#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT 0x10 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK 0x7 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT 0x0 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK 0x8 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT 0x3 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK 0x7 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT 0x0 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK 0x8 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT 0x3 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK 0x7 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT 0x0 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK 0x8 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT 0x3 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK 0x7 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT 0x0 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK 0x8 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT 0x3 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK 0x7 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT 0x0 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK 0x8 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT 0x3 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK 0x7 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT 0x0 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK 0x8 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT 0x3 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK 0x7 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT 0x0 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK 0x8 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT 0x3 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK 0x7 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT 0x0 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK 0x8 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT 0x3 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK 0x7 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT 0x0 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK 0x8 +#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT 0x3 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK 0x1f +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT 0x0 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK 0x40 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT 0x6 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK 0x100 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT 0x8 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK 0x400 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT 0xa +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK 0x1000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT 0xc +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK 0x7f0000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT 0x10 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK 0x1f +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT 0x0 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK 0x40 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT 0x6 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK 0x100 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT 0x8 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK 0x400 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT 0xa +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK 0x1000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT 0xc +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK 0x7f0000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT 0x10 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK 0x1f +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT 0x0 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK 0x40 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT 0x6 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK 0x100 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT 0x8 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK 0x400 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT 0xa +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK 0x1000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT 0xc +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK 0x7f0000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT 0x10 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK 0x1f +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT 0x0 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK 0x40 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT 0x6 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK 0x100 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT 0x8 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK 0x400 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT 0xa +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK 0x1000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT 0xc +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK 0x7f0000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT 0x10 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK 0x1f +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT 0x0 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK 0x40 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT 0x6 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK 0x100 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT 0x8 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK 0x400 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT 0xa +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK 0x1000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT 0xc +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK 0x7f0000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT 0x10 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK 0x1f +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT 0x0 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK 0x40 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT 0x6 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK 0x100 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT 0x8 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK 0x400 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT 0xa +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK 0x1000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT 0xc +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK 0x7f0000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT 0x10 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK 0x1f +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT 0x0 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK 0x40 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT 0x6 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK 0x100 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT 0x8 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK 0x400 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT 0xa +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK 0x1000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT 0xc +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK 0x7f0000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT 0x10 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK 0x1f +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT 0x0 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK 0x40 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT 0x6 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK 0x100 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT 0x8 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK 0x400 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT 0xa +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK 0x1000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT 0xc +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK 0x7f0000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT 0x10 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK 0x1f +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT 0x0 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK 0x40 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT 0x6 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK 0x100 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT 0x8 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK 0x400 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT 0xa +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK 0x1000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT 0xc +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK 0x7f0000 +#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT 0x10 +#define PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK 0x800 +#define PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT 0xb +#define PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK 0x800 +#define PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT 0xb +#define PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK 0x800 +#define PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT 0xb +#define PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK 0x800 +#define PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT 0xb +#define PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK 0x800 +#define PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT 0xb +#define PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK 0x800 +#define PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT 0xb +#define PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK 0x800 +#define PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT 0xb +#define PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK 0x800 +#define PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT 0xb +#define PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK 0x800 +#define PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT 0xb +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK 0x6 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK 0x8 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK 0xe0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT 0x5 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x6 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK 0x8 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x6 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK 0x8 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x6 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK 0x8 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x6 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK 0x8 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK 0x6 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK 0x8 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK 0xe0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT 0x5 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK 0x6 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK 0x8 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK 0xe0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT 0x5 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK 0x6 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK 0x8 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK 0xe0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT 0x5 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT 0x0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK 0x6 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT 0x1 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK 0x8 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT 0x3 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK 0xe0 +#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT 0x5 +#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK 0x7 +#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0 +#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10 +#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK 0xff +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT 0x0 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK 0x3c00 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT 0xa +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK 0x3fc000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT 0xe +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK 0x3c00000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT 0x16 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK 0x4000000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT 0x1a +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK 0x10000000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK 0x20000000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT 0x1d +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT 0xb +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK 0x3ffff +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT 0x0 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK 0x40000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT 0x12 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK 0x7f +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT 0x0 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK 0x80 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT 0x7 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK 0x100 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT 0x8 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK 0x200 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT 0x9 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK 0x400 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT 0xa +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK 0x800 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT 0xb +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK 0x1 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT 0x0 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT 0x1 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK 0x4 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK 0x8 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT 0x3 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x4 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK 0x60 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT 0x5 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK 0x4000000 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT 0x1a +#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK 0x1 +#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT 0x0 +#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK 0x1e +#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT 0x1 +#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK 0xf00 +#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT 0x8 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK 0xffff +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00 +#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8 +#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK 0x7 +#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0 +#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10 +#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK 0xff +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT 0x0 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK 0x700 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT 0x8 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK 0x3000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT 0xc +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK 0x3c000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT 0xe +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK 0x3c0000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT 0x12 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK 0x3c00000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT 0x16 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK 0x4000000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT 0x1a +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK 0x10000000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK 0x20000000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT 0x1d +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT 0xb +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK 0x3ffff +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT 0x0 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK 0x40000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT 0x12 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc +#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd +#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11 +#define PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK 0xff +#define PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT 0x0 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK 0x3800000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT 0x17 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK 0x3fff +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT 0x0 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK 0x8000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT 0xf +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x10 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK 0xe0000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT 0x11 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK 0x4000000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT 0x1a +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK 0x8000000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT 0x1b +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK 0x20000000 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x1d +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK 0xffff +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00 +#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK 0x1 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK 0x6 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT 0x1 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK 0x8 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT 0x3 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK 0xf0 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT 0x4 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK 0x100 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT 0x8 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x600 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0x9 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x1800 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0xb +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK 0xc0000 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT 0x12 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK 0xfff00000 +#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT 0x14 +#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK 0x1 +#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK 0xfffffffe +#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT 0x1 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK 0x1 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK 0xe +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT 0x1 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK 0x3f0 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT 0x4 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK 0xfc00 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT 0xa +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK 0xf0000 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT 0x10 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK 0xf00000 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT 0x14 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK 0xf000000 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT 0x18 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK 0x10000000 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT 0x1c +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK 0xe0000000 +#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d +#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK 0x1 +#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2 +#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT 0x1 +#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK 0x4 +#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2 +#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK 0x3f0 +#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT 0x4 +#define PSX81_PHY0_COM_COMMON_DFX__nelb_en_MASK 0x1 +#define PSX81_PHY0_COM_COMMON_DFX__nelb_en__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_DFX__prbs_seed_MASK 0x7fe +#define PSX81_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT 0x1 +#define PSX81_PHY0_COM_COMMON_DFX__force_cdr_en_MASK 0x800 +#define PSX81_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT 0xb +#define PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK 0x2000 +#define PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT 0xd +#define PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK 0x8000 +#define PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT 0xf +#define PSX81_PHY0_COM_COMMON_DFX__dsm_sel_MASK 0x7e0000 +#define PSX81_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT 0x11 +#define PSX81_PHY0_COM_COMMON_DFX__dsm_en_MASK 0xf000000 +#define PSX81_PHY0_COM_COMMON_DFX__dsm_en__SHIFT 0x18 +#define PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK 0x20000000 +#define PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT 0x1d +#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff +#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00 +#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 +#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000 +#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 +#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000 +#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK 0xff +#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK 0xff00 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT 0x8 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK 0xff0000 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT 0x10 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK 0xff000000 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT 0x18 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK 0xff +#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK 0xff00 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT 0x8 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK 0xff0000 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT 0x10 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK 0xff000000 +#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT 0x18 +#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf +#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0 +#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK 0x7 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK 0xf0 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT 0x4 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK 0x1e00 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT 0x9 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK 0x3c000 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT 0xe +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK 0x780000 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT 0x13 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK 0x1e000000 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT 0x19 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK 0xe0000000 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT 0x1d +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK 0x3 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK 0x78 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT 0x3 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK 0xf00 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT 0x8 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK 0x1e000 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT 0xd +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK 0x3c0000 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT 0x12 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK 0x3800000 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT 0x17 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK 0x38000000 +#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT 0x1b +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK 0x1f +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK 0x7c0 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT 0x6 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK 0xe000 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT 0xd +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK 0xe0000 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT 0x11 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK 0xfc00000 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT 0x16 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK 0x3f +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK 0xf00 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT 0x8 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK 0x1e000 +#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT 0xd +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK 0x1ff +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK 0xff800 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT 0xb +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK 0x7fc00000 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT 0x16 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK 0x3f +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK 0x1f80 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT 0x7 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK 0x7 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK 0x1c0 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT 0x6 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK 0x3fffc00 +#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT 0xa +#define PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK 0x20 +#define PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT 0x5 +#define PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK 0xc0 +#define PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT 0x6 +#define PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK 0x300 +#define PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT 0x8 +#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK 0x1f +#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK 0x40 +#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT 0x6 +#define PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK 0x70 +#define PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT 0x4 +#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK 0x1 +#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK 0x780 +#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT 0x7 +#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK 0x7e000 +#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT 0xd +#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK 0x1 +#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT 0x0 +#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK 0x3c +#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2 +#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK 0x780 +#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT 0x7 +#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK 0x1ff000 +#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT 0xc +#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK 0xc00000 +#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT 0x16 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK 0x7 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK 0x18 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK 0x20 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT 0x5 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK 0x7 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK 0x18 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK 0x20 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT 0x5 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK 0x7 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK 0x18 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK 0x20 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT 0x5 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK 0x7 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK 0x18 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK 0x20 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT 0x5 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK 0x7 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK 0x18 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK 0x20 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT 0x5 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK 0x7 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK 0x18 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK 0x20 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT 0x5 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK 0x7 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK 0x18 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK 0x20 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT 0x5 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK 0x7 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK 0x18 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK 0x20 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT 0x5 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK 0x7 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK 0x18 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK 0x20 +#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT 0x5 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK 0x6 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK 0x8 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK 0x6 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK 0x8 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK 0x6 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK 0x8 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK 0x6 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK 0x8 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK 0x6 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK 0x8 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK 0x6 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK 0x8 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK 0x6 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK 0x8 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK 0x6 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK 0x8 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK 0x6 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT 0x1 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK 0x8 +#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK 0x1 +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT 0x0 +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK 0x1fe +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT 0x1 +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK 0x1800 +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT 0xb +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK 0x2000 +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT 0xd +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK 0x8000 +#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT 0xf +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT 0x0 +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK 0x1fe +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK 0x1800 +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT 0xb +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK 0x2000 +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT 0xd +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK 0x8000 +#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT 0xf +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT 0x0 +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK 0x1fe +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK 0x1800 +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT 0xb +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK 0x2000 +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT 0xd +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK 0x8000 +#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT 0xf +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT 0x0 +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK 0x1fe +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK 0x1800 +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT 0xb +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK 0x2000 +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT 0xd +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK 0x8000 +#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT 0xf +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT 0x0 +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK 0x1fe +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK 0x1800 +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT 0xb +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK 0x2000 +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT 0xd +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK 0x8000 +#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT 0xf +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT 0x0 +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK 0x1fe +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK 0x1800 +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT 0xb +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK 0x2000 +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT 0xd +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK 0x8000 +#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT 0xf +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT 0x0 +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK 0x1fe +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK 0x1800 +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT 0xb +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK 0x2000 +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT 0xd +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK 0x8000 +#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT 0xf +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT 0x0 +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK 0x1fe +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK 0x1800 +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT 0xb +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK 0x2000 +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT 0xd +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK 0x8000 +#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT 0xf +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT 0x0 +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK 0x1fe +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT 0x1 +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK 0x1800 +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT 0xb +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK 0x2000 +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT 0xd +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK 0x4000 +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT 0xe +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK 0x8000 +#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT 0xf +#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK 0x7 +#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK 0x20 +#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT 0x5 +#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK 0x80 +#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK 0x20 +#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT 0x5 +#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK 0x80 +#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK 0x20 +#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT 0x5 +#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK 0x80 +#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK 0x20 +#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT 0x5 +#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK 0x80 +#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK 0x20 +#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT 0x5 +#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK 0x80 +#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK 0x20 +#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT 0x5 +#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK 0x80 +#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK 0x20 +#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT 0x5 +#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK 0x80 +#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK 0x20 +#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT 0x5 +#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK 0x80 +#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK 0x7 +#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK 0x10 +#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT 0x4 +#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK 0x20 +#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT 0x5 +#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK 0x80 +#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT 0x7 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT 0x0 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK 0x10 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT 0x4 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK 0x20 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT 0x5 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK 0x40 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT 0x6 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK 0x80 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT 0x7 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK 0x100 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT 0x8 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK 0x400 +#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT 0xa +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT 0x0 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK 0x10 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT 0x4 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK 0x20 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT 0x5 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK 0x40 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT 0x6 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK 0x80 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT 0x7 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK 0x100 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT 0x8 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK 0x400 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT 0xa +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT 0x0 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK 0x10 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT 0x4 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK 0x20 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT 0x5 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK 0x40 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT 0x6 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK 0x80 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT 0x7 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK 0x100 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT 0x8 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK 0x400 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT 0xa +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT 0x0 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK 0x10 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT 0x4 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK 0x20 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT 0x5 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK 0x40 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT 0x6 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK 0x80 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT 0x7 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK 0x100 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT 0x8 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK 0x400 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT 0xa +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT 0x0 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK 0x10 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT 0x4 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK 0x20 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT 0x5 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK 0x40 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT 0x6 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK 0x80 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT 0x7 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK 0x100 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT 0x8 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK 0x400 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT 0xa +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT 0x0 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK 0x10 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT 0x4 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK 0x20 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT 0x5 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK 0x40 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT 0x6 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK 0x80 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT 0x7 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK 0x100 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT 0x8 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK 0x400 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT 0xa +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT 0x0 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK 0x10 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT 0x4 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK 0x20 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT 0x5 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK 0x40 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT 0x6 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK 0x80 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT 0x7 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK 0x100 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT 0x8 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK 0x400 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT 0xa +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT 0x0 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK 0x10 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT 0x4 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK 0x20 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT 0x5 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK 0x40 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT 0x6 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK 0x80 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT 0x7 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK 0x100 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT 0x8 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK 0x400 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT 0xa +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT 0x0 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT 0x1 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK 0x10 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT 0x4 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK 0x20 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT 0x5 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK 0x40 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT 0x6 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK 0x80 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT 0x7 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK 0x100 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT 0x8 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK 0x400 +#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT 0xa +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT 0x0 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK 0x1f8 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT 0x3 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK 0x400 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT 0xa +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT 0x0 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK 0x1f8 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT 0x3 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK 0x400 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT 0xa +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT 0x0 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK 0x1f8 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT 0x3 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK 0x400 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT 0xa +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT 0x0 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK 0x1f8 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT 0x3 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK 0x400 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT 0xa +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT 0x0 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK 0x1f8 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT 0x3 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK 0x400 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT 0xa +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT 0x0 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK 0x1f8 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT 0x3 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK 0x400 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT 0xa +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT 0x0 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK 0x1f8 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT 0x3 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK 0x400 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT 0xa +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT 0x0 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK 0x1f8 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT 0x3 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK 0x400 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT 0xa +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT 0x0 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT 0x1 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK 0x4 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK 0x1f8 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT 0x3 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK 0x400 +#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT 0xa +#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK 0x3ff +#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK 0xe000 +#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT 0xd +#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK 0x3ff +#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK 0xe000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT 0xd +#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK 0x3ff +#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK 0xe000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT 0xd +#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK 0x3ff +#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK 0xe000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT 0xd +#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK 0x3ff +#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK 0xe000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT 0xd +#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK 0x3ff +#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK 0xe000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT 0xd +#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK 0x3ff +#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK 0xe000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT 0xd +#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK 0x3ff +#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK 0xe000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT 0xd +#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK 0x3ff +#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK 0xe000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT 0xd +#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK 0x20000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT 0x11 +#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK 0x180000 +#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT 0x0 +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK 0x1fe +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK 0x800 +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT 0xb +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK 0x1000 +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT 0xc +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK 0x2000 +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT 0xd +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK 0x4000 +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT 0xe +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK 0x10000 +#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT 0x10 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT 0x0 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK 0x1fe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK 0x800 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT 0xb +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK 0x1000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT 0xc +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK 0x2000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT 0xd +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK 0x4000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT 0xe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK 0x10000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT 0x10 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT 0x0 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK 0x1fe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK 0x800 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT 0xb +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK 0x1000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT 0xc +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK 0x2000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT 0xd +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK 0x4000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT 0xe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK 0x10000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT 0x10 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT 0x0 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK 0x1fe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK 0x800 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT 0xb +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK 0x1000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT 0xc +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK 0x2000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT 0xd +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK 0x4000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT 0xe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK 0x10000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT 0x10 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT 0x0 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK 0x1fe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK 0x800 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT 0xb +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK 0x1000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT 0xc +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK 0x2000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT 0xd +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK 0x4000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT 0xe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK 0x10000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT 0x10 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT 0x0 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK 0x1fe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK 0x800 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT 0xb +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK 0x1000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT 0xc +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK 0x2000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT 0xd +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK 0x4000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT 0xe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK 0x10000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT 0x10 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT 0x0 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK 0x1fe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK 0x800 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT 0xb +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK 0x1000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT 0xc +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK 0x2000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT 0xd +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK 0x4000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT 0xe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK 0x10000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT 0x10 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT 0x0 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK 0x1fe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK 0x800 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT 0xb +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK 0x1000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT 0xc +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK 0x2000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT 0xd +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK 0x4000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT 0xe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK 0x10000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT 0x10 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT 0x0 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK 0x1fe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT 0x1 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK 0x800 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT 0xb +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK 0x1000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT 0xc +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK 0x2000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT 0xd +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK 0x4000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT 0xe +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK 0x10000 +#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT 0x10 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT 0x0 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT 0x1 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK 0x40 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT 0x6 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK 0x80 +#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT 0x7 +#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK 0xf +#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK 0x80000 +#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK 0x100000 +#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT 0x14 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK 0xf +#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK 0x80000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK 0x100000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT 0x14 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK 0xf +#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK 0x80000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK 0x100000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT 0x14 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK 0xf +#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK 0x80000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK 0x100000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT 0x14 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK 0xf +#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK 0x80000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK 0x100000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT 0x14 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK 0xf +#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK 0x80000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK 0x100000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT 0x14 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK 0xf +#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK 0x80000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK 0x100000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT 0x14 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK 0xf +#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK 0x80000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK 0x100000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT 0x14 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK 0xf +#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT 0x0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK 0x1ffc0 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT 0x6 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK 0x80000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT 0x13 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK 0x100000 +#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT 0x14 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK 0x7 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK 0x18 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK 0x7 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK 0x18 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK 0x7 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK 0x18 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK 0x7 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK 0x18 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK 0x7 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK 0x18 +#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT 0x3 +#define PSX81_PHY0_TX_DFX_BROADCAST__obs_en_MASK 0x1 +#define PSX81_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT 0x0 +#define PSX81_PHY0_TX_DFX_BROADCAST__obs_sel_MASK 0x4 +#define PSX81_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2 +#define PSX81_PHY0_TX_DFX_BROADCAST__felb_en_MASK 0x10 +#define PSX81_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT 0x4 +#define PSX81_PHY0_TX_DFX_BROADCAST__prbs_en_MASK 0x100 +#define PSX81_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT 0x8 +#define PSX81_PHY0_TX_DFX_LANE0__obs_en_MASK 0x1 +#define PSX81_PHY0_TX_DFX_LANE0__obs_en__SHIFT 0x0 +#define PSX81_PHY0_TX_DFX_LANE0__obs_sel_MASK 0x4 +#define PSX81_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2 +#define PSX81_PHY0_TX_DFX_LANE0__felb_en_MASK 0x10 +#define PSX81_PHY0_TX_DFX_LANE0__felb_en__SHIFT 0x4 +#define PSX81_PHY0_TX_DFX_LANE0__prbs_en_MASK 0x100 +#define PSX81_PHY0_TX_DFX_LANE0__prbs_en__SHIFT 0x8 +#define PSX81_PHY0_TX_DFX_LANE1__obs_en_MASK 0x1 +#define PSX81_PHY0_TX_DFX_LANE1__obs_en__SHIFT 0x0 +#define PSX81_PHY0_TX_DFX_LANE1__obs_sel_MASK 0x4 +#define PSX81_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2 +#define PSX81_PHY0_TX_DFX_LANE1__felb_en_MASK 0x10 +#define PSX81_PHY0_TX_DFX_LANE1__felb_en__SHIFT 0x4 +#define PSX81_PHY0_TX_DFX_LANE1__prbs_en_MASK 0x100 +#define PSX81_PHY0_TX_DFX_LANE1__prbs_en__SHIFT 0x8 +#define PSX81_PHY0_TX_DFX_LANE2__obs_en_MASK 0x1 +#define PSX81_PHY0_TX_DFX_LANE2__obs_en__SHIFT 0x0 +#define PSX81_PHY0_TX_DFX_LANE2__obs_sel_MASK 0x4 +#define PSX81_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2 +#define PSX81_PHY0_TX_DFX_LANE2__felb_en_MASK 0x10 +#define PSX81_PHY0_TX_DFX_LANE2__felb_en__SHIFT 0x4 +#define PSX81_PHY0_TX_DFX_LANE2__prbs_en_MASK 0x100 +#define PSX81_PHY0_TX_DFX_LANE2__prbs_en__SHIFT 0x8 +#define PSX81_PHY0_TX_DFX_LANE3__obs_en_MASK 0x1 +#define PSX81_PHY0_TX_DFX_LANE3__obs_en__SHIFT 0x0 +#define PSX81_PHY0_TX_DFX_LANE3__obs_sel_MASK 0x4 +#define PSX81_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2 +#define PSX81_PHY0_TX_DFX_LANE3__felb_en_MASK 0x10 +#define PSX81_PHY0_TX_DFX_LANE3__felb_en__SHIFT 0x4 +#define PSX81_PHY0_TX_DFX_LANE3__prbs_en_MASK 0x100 +#define PSX81_PHY0_TX_DFX_LANE3__prbs_en__SHIFT 0x8 +#define PSX81_PHY0_TX_DFX_LANE4__obs_en_MASK 0x1 +#define PSX81_PHY0_TX_DFX_LANE4__obs_en__SHIFT 0x0 +#define PSX81_PHY0_TX_DFX_LANE4__obs_sel_MASK 0x4 +#define PSX81_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2 +#define PSX81_PHY0_TX_DFX_LANE4__felb_en_MASK 0x10 +#define PSX81_PHY0_TX_DFX_LANE4__felb_en__SHIFT 0x4 +#define PSX81_PHY0_TX_DFX_LANE4__prbs_en_MASK 0x100 +#define PSX81_PHY0_TX_DFX_LANE4__prbs_en__SHIFT 0x8 +#define PSX81_PHY0_TX_DFX_LANE5__obs_en_MASK 0x1 +#define PSX81_PHY0_TX_DFX_LANE5__obs_en__SHIFT 0x0 +#define PSX81_PHY0_TX_DFX_LANE5__obs_sel_MASK 0x4 +#define PSX81_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2 +#define PSX81_PHY0_TX_DFX_LANE5__felb_en_MASK 0x10 +#define PSX81_PHY0_TX_DFX_LANE5__felb_en__SHIFT 0x4 +#define PSX81_PHY0_TX_DFX_LANE5__prbs_en_MASK 0x100 +#define PSX81_PHY0_TX_DFX_LANE5__prbs_en__SHIFT 0x8 +#define PSX81_PHY0_TX_DFX_LANE6__obs_en_MASK 0x1 +#define PSX81_PHY0_TX_DFX_LANE6__obs_en__SHIFT 0x0 +#define PSX81_PHY0_TX_DFX_LANE6__obs_sel_MASK 0x4 +#define PSX81_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2 +#define PSX81_PHY0_TX_DFX_LANE6__felb_en_MASK 0x10 +#define PSX81_PHY0_TX_DFX_LANE6__felb_en__SHIFT 0x4 +#define PSX81_PHY0_TX_DFX_LANE6__prbs_en_MASK 0x100 +#define PSX81_PHY0_TX_DFX_LANE6__prbs_en__SHIFT 0x8 +#define PSX81_PHY0_TX_DFX_LANE7__obs_en_MASK 0x1 +#define PSX81_PHY0_TX_DFX_LANE7__obs_en__SHIFT 0x0 +#define PSX81_PHY0_TX_DFX_LANE7__obs_sel_MASK 0x4 +#define PSX81_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2 +#define PSX81_PHY0_TX_DFX_LANE7__felb_en_MASK 0x10 +#define PSX81_PHY0_TX_DFX_LANE7__felb_en__SHIFT 0x4 +#define PSX81_PHY0_TX_DFX_LANE7__prbs_en_MASK 0x100 +#define PSX81_PHY0_TX_DFX_LANE7__prbs_en__SHIFT 0x8 +#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK 0xff +#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT 0x0 +#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK 0x3f00 +#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT 0x8 +#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK 0xff0000 +#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT 0x10 +#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK 0xff +#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT 0x0 +#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK 0x3f00 +#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT 0x8 +#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK 0xff0000 +#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT 0x10 +#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK 0xff +#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT 0x0 +#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK 0x3f00 +#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT 0x8 +#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK 0xff0000 +#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT 0x10 +#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK 0xff +#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT 0x0 +#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK 0x3f00 +#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT 0x8 +#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK 0xff0000 +#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT 0x10 +#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK 0xff +#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT 0x0 +#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK 0x3f00 +#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT 0x8 +#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK 0xff0000 +#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT 0x10 +#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK 0xff +#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT 0x0 +#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK 0x3f00 +#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT 0x8 +#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK 0xff0000 +#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT 0x10 +#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK 0xff +#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT 0x0 +#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK 0x3f00 +#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT 0x8 +#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK 0xff0000 +#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT 0x10 +#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK 0xff +#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT 0x0 +#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK 0x3f00 +#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT 0x8 +#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK 0xff0000 +#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT 0x10 +#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK 0xff +#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT 0x0 +#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK 0x3f00 +#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT 0x8 +#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK 0xff0000 +#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT 0x10 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK 0x7 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT 0x0 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK 0x8 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT 0x3 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK 0x7 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT 0x0 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK 0x8 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT 0x3 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK 0x7 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT 0x0 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK 0x8 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT 0x3 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK 0x7 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT 0x0 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK 0x8 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT 0x3 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK 0x7 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT 0x0 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK 0x8 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT 0x3 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK 0x7 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT 0x0 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK 0x8 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT 0x3 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK 0x7 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT 0x0 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK 0x8 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT 0x3 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK 0x7 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT 0x0 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK 0x8 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT 0x3 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK 0x7 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT 0x0 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK 0x8 +#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT 0x3 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK 0x1f +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT 0x0 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK 0x40 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT 0x6 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK 0x100 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT 0x8 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK 0x400 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT 0xa +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK 0x1000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT 0xc +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK 0x7f0000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT 0x10 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK 0x1f +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT 0x0 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK 0x40 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT 0x6 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK 0x100 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT 0x8 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK 0x400 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT 0xa +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK 0x1000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT 0xc +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK 0x7f0000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT 0x10 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK 0x1f +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT 0x0 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK 0x40 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT 0x6 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK 0x100 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT 0x8 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK 0x400 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT 0xa +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK 0x1000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT 0xc +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK 0x7f0000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT 0x10 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK 0x1f +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT 0x0 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK 0x40 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT 0x6 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK 0x100 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT 0x8 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK 0x400 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT 0xa +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK 0x1000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT 0xc +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK 0x7f0000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT 0x10 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK 0x1f +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT 0x0 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK 0x40 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT 0x6 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK 0x100 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT 0x8 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK 0x400 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT 0xa +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK 0x1000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT 0xc +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK 0x7f0000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT 0x10 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK 0x1f +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT 0x0 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK 0x40 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT 0x6 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK 0x100 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT 0x8 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK 0x400 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT 0xa +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK 0x1000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT 0xc +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK 0x7f0000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT 0x10 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK 0x1f +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT 0x0 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK 0x40 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT 0x6 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK 0x100 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT 0x8 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK 0x400 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT 0xa +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK 0x1000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT 0xc +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK 0x7f0000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT 0x10 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK 0x1f +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT 0x0 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK 0x40 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT 0x6 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK 0x100 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT 0x8 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK 0x400 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT 0xa +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK 0x1000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT 0xc +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK 0x7f0000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT 0x10 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK 0x1f +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT 0x0 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK 0x40 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT 0x6 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK 0x100 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT 0x8 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK 0x400 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT 0xa +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK 0x1000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT 0xc +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK 0x7f0000 +#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT 0x10 +#define PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK 0x800 +#define PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT 0xb +#define PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK 0x800 +#define PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT 0xb +#define PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK 0x800 +#define PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT 0xb +#define PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK 0x800 +#define PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT 0xb +#define PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK 0x800 +#define PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT 0xb +#define PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK 0x800 +#define PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT 0xb +#define PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK 0x800 +#define PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT 0xb +#define PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK 0x800 +#define PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT 0xb +#define PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK 0x800 +#define PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT 0xb +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK 0x6 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK 0x8 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK 0xe0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT 0x5 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x6 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK 0x8 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x6 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK 0x8 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x6 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK 0x8 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x6 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK 0x8 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK 0x6 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK 0x8 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK 0xe0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT 0x5 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK 0x6 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK 0x8 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK 0xe0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT 0x5 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK 0x6 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK 0x8 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK 0xe0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT 0x5 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT 0x0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK 0x6 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT 0x1 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK 0x8 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT 0x3 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK 0xe0 +#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT 0x5 +#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK 0x7 +#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0 +#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10 +#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK 0xff +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT 0x0 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK 0x3c00 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT 0xa +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK 0x3fc000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT 0xe +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK 0x3c00000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT 0x16 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK 0x4000000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT 0x1a +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK 0x10000000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK 0x20000000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT 0x1d +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT 0xb +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK 0x3ffff +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT 0x0 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK 0x40000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT 0x12 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK 0x7f +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT 0x0 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK 0x80 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT 0x7 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK 0x100 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT 0x8 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK 0x200 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT 0x9 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK 0x400 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT 0xa +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK 0x800 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT 0xb +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK 0x1 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT 0x0 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT 0x1 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK 0x4 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK 0x8 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT 0x3 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x4 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK 0x60 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT 0x5 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK 0x4000000 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT 0x1a +#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK 0x1 +#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT 0x0 +#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK 0x1e +#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT 0x1 +#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK 0xf00 +#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT 0x8 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK 0xffff +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00 +#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8 +#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK 0x7 +#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0 +#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10 +#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK 0xff +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT 0x0 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK 0x700 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT 0x8 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK 0x3000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT 0xc +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK 0x3c000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT 0xe +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK 0x3c0000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT 0x12 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK 0x3c00000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT 0x16 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK 0x4000000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT 0x1a +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK 0x10000000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK 0x20000000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT 0x1d +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT 0xb +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK 0x3ffff +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT 0x0 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK 0x40000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT 0x12 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc +#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd +#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11 +#define PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK 0xff +#define PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT 0x0 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK 0x3800000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT 0x17 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK 0x3fff +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT 0x0 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK 0x8000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT 0xf +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x10 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK 0xe0000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT 0x11 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK 0x4000000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT 0x1a +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK 0x8000000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT 0x1b +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK 0x20000000 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x1d +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK 0xffff +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00 +#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8 +#define PSX80_PIF0_SCRATCH__PIF_SCRATCH_MASK 0xffffffff +#define PSX80_PIF0_SCRATCH__PIF_SCRATCH__SHIFT 0x0 +#define PSX80_PIF0_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PSX80_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PSX80_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PSX80_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PSX80_PIF0_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PSX80_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PSX80_PIF0_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PSX80_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PSX80_PIF0_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PSX80_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PSX80_PIF0_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PSX80_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PSX80_PIF0_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PSX80_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PSX80_PIF0_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PSX80_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PSX80_PIF0_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PSX80_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PSX80_PIF0_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PSX80_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PSX80_PIF0_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PSX80_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PSX80_PIF0_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PSX80_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PSX80_PIF0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PSX80_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PSX80_PIF0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PSX80_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PSX80_PIF0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PSX80_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PSX80_PIF0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PSX80_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2 +#define PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1 +#define PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4 +#define PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2 +#define PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8 +#define PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3 +#define PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10 +#define PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4 +#define PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20 +#define PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5 +#define PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0 +#define PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6 +#define PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300 +#define PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8 +#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400 +#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa +#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800 +#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb +#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000 +#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc +#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000 +#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd +#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000 +#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe +#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000 +#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf +#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000 +#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10 +#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1 +#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0 +#define PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2 +#define PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1 +#define PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4 +#define PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2 +#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8 +#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3 +#define PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK 0x10 +#define PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4 +#define PSX80_PIF0_CTRL__PIF_PLL_STATUS_MASK 0xc0 +#define PSX80_PIF0_CTRL__PIF_PLL_STATUS__SHIFT 0x6 +#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100 +#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8 +#define PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200 +#define PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9 +#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400 +#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa +#define PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK 0x800 +#define PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb +#define PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000 +#define PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc +#define PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000 +#define PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd +#define PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000 +#define PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_S2_MASK 0x7 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000 +#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16 +#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000 +#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17 +#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000 +#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18 +#define PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7 +#define PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0 +#define PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38 +#define PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3 +#define PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0 +#define PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6 +#define PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200 +#define PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 +#define PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 +#define PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa +#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000 +#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10 +#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000 +#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11 +#define PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000 +#define PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15 +#define PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000 +#define PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16 +#define PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000 +#define PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19 +#define PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000 +#define PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a +#define PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000 +#define PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d +#define PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000 +#define PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_S2_MASK 0x7 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000 +#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16 +#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000 +#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17 +#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000 +#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18 +#define PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000 +#define PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19 +#define PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000 +#define PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a +#define PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7 +#define PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0 +#define PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38 +#define PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3 +#define PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0 +#define PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6 +#define PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200 +#define PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 +#define PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 +#define PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa +#define PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000 +#define PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10 +#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000 +#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11 +#define PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000 +#define PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13 +#define PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000 +#define PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15 +#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000 +#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18 +#define PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000 +#define PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19 +#define PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000 +#define PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000 +#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80 +#define PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7 +#define PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100 +#define PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8 +#define PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200 +#define PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9 +#define PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400 +#define PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa +#define PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800 +#define PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb +#define PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000 +#define PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10 +#define PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000 +#define PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11 +#define PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000 +#define PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80 +#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7 +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100 +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8 +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200 +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9 +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400 +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800 +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000 +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000 +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000 +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000 +#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000 +#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3 +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0 +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2 +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10 +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4 +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60 +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5 +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80 +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7 +#define PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100 +#define PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8 +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200 +#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000 +#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17 +#define PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1 +#define PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0 +#define PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2 +#define PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1 +#define PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4 +#define PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2 +#define PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8 +#define PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3 +#define PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10 +#define PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4 +#define PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20 +#define PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5 +#define PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40 +#define PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6 +#define PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80 +#define PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7 +#define PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100 +#define PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8 +#define PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200 +#define PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9 +#define PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400 +#define PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa +#define PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800 +#define PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb +#define PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000 +#define PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc +#define PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000 +#define PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd +#define PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000 +#define PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe +#define PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000 +#define PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf +#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000 +#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10 +#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000 +#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11 +#define PSX80_PIF0_LANE0_OVRD2__GANGMODE_0_MASK 0x7 +#define PSX80_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0 +#define PSX80_PIF0_LANE0_OVRD2__FREQDIV_0_MASK 0x18 +#define PSX80_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3 +#define PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK 0x60 +#define PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5 +#define PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80 +#define PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7 +#define PSX80_PIF0_LANE0_OVRD2__TXPWR_0_MASK 0x700 +#define PSX80_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT 0x8 +#define PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800 +#define PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb +#define PSX80_PIF0_LANE0_OVRD2__RXPWR_0_MASK 0xe000 +#define PSX80_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT 0xd +#define PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000 +#define PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10 +#define PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000 +#define PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12 +#define PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000 +#define PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13 +#define PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000 +#define PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14 +#define PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000 +#define PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15 +#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000 +#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16 +#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000 +#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17 +#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000 +#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18 +#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000 +#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a +#define PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1 +#define PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0 +#define PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2 +#define PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1 +#define PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4 +#define PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2 +#define PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8 +#define PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3 +#define PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10 +#define PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4 +#define PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20 +#define PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5 +#define PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40 +#define PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6 +#define PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80 +#define PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7 +#define PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100 +#define PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8 +#define PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200 +#define PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9 +#define PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400 +#define PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa +#define PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800 +#define PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb +#define PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000 +#define PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc +#define PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000 +#define PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd +#define PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000 +#define PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe +#define PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000 +#define PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf +#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000 +#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10 +#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000 +#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11 +#define PSX80_PIF0_LANE1_OVRD2__GANGMODE_1_MASK 0x7 +#define PSX80_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0 +#define PSX80_PIF0_LANE1_OVRD2__FREQDIV_1_MASK 0x18 +#define PSX80_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3 +#define PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK 0x60 +#define PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5 +#define PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80 +#define PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7 +#define PSX80_PIF0_LANE1_OVRD2__TXPWR_1_MASK 0x700 +#define PSX80_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT 0x8 +#define PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800 +#define PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb +#define PSX80_PIF0_LANE1_OVRD2__RXPWR_1_MASK 0xe000 +#define PSX80_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT 0xd +#define PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000 +#define PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10 +#define PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000 +#define PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12 +#define PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000 +#define PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13 +#define PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000 +#define PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14 +#define PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000 +#define PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15 +#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000 +#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16 +#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000 +#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17 +#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000 +#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18 +#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000 +#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a +#define PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1 +#define PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0 +#define PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2 +#define PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1 +#define PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4 +#define PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2 +#define PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8 +#define PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3 +#define PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10 +#define PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4 +#define PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20 +#define PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5 +#define PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40 +#define PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6 +#define PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80 +#define PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7 +#define PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100 +#define PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8 +#define PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200 +#define PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9 +#define PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400 +#define PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa +#define PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800 +#define PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb +#define PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000 +#define PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc +#define PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000 +#define PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd +#define PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000 +#define PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe +#define PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000 +#define PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf +#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000 +#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10 +#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000 +#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11 +#define PSX80_PIF0_LANE2_OVRD2__GANGMODE_2_MASK 0x7 +#define PSX80_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0 +#define PSX80_PIF0_LANE2_OVRD2__FREQDIV_2_MASK 0x18 +#define PSX80_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3 +#define PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK 0x60 +#define PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5 +#define PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80 +#define PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7 +#define PSX80_PIF0_LANE2_OVRD2__TXPWR_2_MASK 0x700 +#define PSX80_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT 0x8 +#define PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800 +#define PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb +#define PSX80_PIF0_LANE2_OVRD2__RXPWR_2_MASK 0xe000 +#define PSX80_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT 0xd +#define PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000 +#define PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10 +#define PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000 +#define PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12 +#define PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000 +#define PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13 +#define PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000 +#define PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14 +#define PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000 +#define PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15 +#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000 +#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16 +#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000 +#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17 +#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000 +#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18 +#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000 +#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a +#define PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1 +#define PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0 +#define PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2 +#define PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1 +#define PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4 +#define PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2 +#define PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8 +#define PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3 +#define PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10 +#define PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4 +#define PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20 +#define PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5 +#define PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40 +#define PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6 +#define PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80 +#define PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7 +#define PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100 +#define PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8 +#define PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200 +#define PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9 +#define PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400 +#define PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa +#define PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800 +#define PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb +#define PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000 +#define PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc +#define PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000 +#define PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd +#define PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000 +#define PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe +#define PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000 +#define PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf +#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000 +#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10 +#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000 +#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11 +#define PSX80_PIF0_LANE3_OVRD2__GANGMODE_3_MASK 0x7 +#define PSX80_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0 +#define PSX80_PIF0_LANE3_OVRD2__FREQDIV_3_MASK 0x18 +#define PSX80_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3 +#define PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK 0x60 +#define PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5 +#define PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80 +#define PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7 +#define PSX80_PIF0_LANE3_OVRD2__TXPWR_3_MASK 0x700 +#define PSX80_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT 0x8 +#define PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800 +#define PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb +#define PSX80_PIF0_LANE3_OVRD2__RXPWR_3_MASK 0xe000 +#define PSX80_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT 0xd +#define PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000 +#define PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10 +#define PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000 +#define PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12 +#define PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000 +#define PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13 +#define PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000 +#define PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14 +#define PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000 +#define PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15 +#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000 +#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16 +#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000 +#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17 +#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000 +#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18 +#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000 +#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a +#define PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1 +#define PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0 +#define PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2 +#define PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1 +#define PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4 +#define PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2 +#define PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8 +#define PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3 +#define PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10 +#define PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4 +#define PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20 +#define PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5 +#define PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40 +#define PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6 +#define PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80 +#define PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7 +#define PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100 +#define PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8 +#define PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200 +#define PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9 +#define PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400 +#define PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa +#define PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800 +#define PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb +#define PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000 +#define PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc +#define PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000 +#define PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd +#define PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000 +#define PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe +#define PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000 +#define PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf +#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000 +#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10 +#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000 +#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11 +#define PSX80_PIF0_LANE4_OVRD2__GANGMODE_4_MASK 0x7 +#define PSX80_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0 +#define PSX80_PIF0_LANE4_OVRD2__FREQDIV_4_MASK 0x18 +#define PSX80_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3 +#define PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK 0x60 +#define PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5 +#define PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80 +#define PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7 +#define PSX80_PIF0_LANE4_OVRD2__TXPWR_4_MASK 0x700 +#define PSX80_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT 0x8 +#define PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800 +#define PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb +#define PSX80_PIF0_LANE4_OVRD2__RXPWR_4_MASK 0xe000 +#define PSX80_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT 0xd +#define PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000 +#define PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10 +#define PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000 +#define PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12 +#define PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000 +#define PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13 +#define PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000 +#define PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14 +#define PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000 +#define PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15 +#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000 +#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16 +#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000 +#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17 +#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000 +#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18 +#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000 +#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a +#define PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1 +#define PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0 +#define PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2 +#define PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1 +#define PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4 +#define PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2 +#define PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8 +#define PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3 +#define PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10 +#define PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4 +#define PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20 +#define PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5 +#define PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40 +#define PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6 +#define PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80 +#define PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7 +#define PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100 +#define PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8 +#define PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200 +#define PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9 +#define PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400 +#define PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa +#define PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800 +#define PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb +#define PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000 +#define PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc +#define PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000 +#define PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd +#define PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000 +#define PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe +#define PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000 +#define PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf +#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000 +#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10 +#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000 +#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11 +#define PSX80_PIF0_LANE5_OVRD2__GANGMODE_5_MASK 0x7 +#define PSX80_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0 +#define PSX80_PIF0_LANE5_OVRD2__FREQDIV_5_MASK 0x18 +#define PSX80_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3 +#define PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK 0x60 +#define PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5 +#define PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80 +#define PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7 +#define PSX80_PIF0_LANE5_OVRD2__TXPWR_5_MASK 0x700 +#define PSX80_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT 0x8 +#define PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800 +#define PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb +#define PSX80_PIF0_LANE5_OVRD2__RXPWR_5_MASK 0xe000 +#define PSX80_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT 0xd +#define PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000 +#define PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10 +#define PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000 +#define PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12 +#define PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000 +#define PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13 +#define PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000 +#define PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14 +#define PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000 +#define PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15 +#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000 +#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16 +#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000 +#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17 +#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000 +#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18 +#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000 +#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a +#define PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1 +#define PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0 +#define PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2 +#define PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1 +#define PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4 +#define PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2 +#define PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8 +#define PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3 +#define PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10 +#define PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4 +#define PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20 +#define PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5 +#define PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40 +#define PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6 +#define PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80 +#define PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7 +#define PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100 +#define PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8 +#define PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200 +#define PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9 +#define PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400 +#define PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa +#define PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800 +#define PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb +#define PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000 +#define PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc +#define PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000 +#define PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd +#define PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000 +#define PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe +#define PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000 +#define PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf +#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000 +#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10 +#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000 +#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11 +#define PSX80_PIF0_LANE6_OVRD2__GANGMODE_6_MASK 0x7 +#define PSX80_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0 +#define PSX80_PIF0_LANE6_OVRD2__FREQDIV_6_MASK 0x18 +#define PSX80_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3 +#define PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK 0x60 +#define PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5 +#define PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80 +#define PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7 +#define PSX80_PIF0_LANE6_OVRD2__TXPWR_6_MASK 0x700 +#define PSX80_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT 0x8 +#define PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800 +#define PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb +#define PSX80_PIF0_LANE6_OVRD2__RXPWR_6_MASK 0xe000 +#define PSX80_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT 0xd +#define PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000 +#define PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10 +#define PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000 +#define PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12 +#define PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000 +#define PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13 +#define PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000 +#define PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14 +#define PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000 +#define PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15 +#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000 +#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16 +#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000 +#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17 +#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000 +#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18 +#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000 +#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a +#define PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1 +#define PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0 +#define PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2 +#define PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1 +#define PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4 +#define PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2 +#define PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8 +#define PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3 +#define PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10 +#define PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4 +#define PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20 +#define PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5 +#define PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40 +#define PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6 +#define PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80 +#define PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7 +#define PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100 +#define PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8 +#define PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200 +#define PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9 +#define PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400 +#define PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa +#define PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800 +#define PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb +#define PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000 +#define PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc +#define PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000 +#define PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd +#define PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000 +#define PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe +#define PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000 +#define PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf +#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000 +#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10 +#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000 +#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11 +#define PSX80_PIF0_LANE7_OVRD2__GANGMODE_7_MASK 0x7 +#define PSX80_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0 +#define PSX80_PIF0_LANE7_OVRD2__FREQDIV_7_MASK 0x18 +#define PSX80_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3 +#define PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK 0x60 +#define PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5 +#define PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80 +#define PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7 +#define PSX80_PIF0_LANE7_OVRD2__TXPWR_7_MASK 0x700 +#define PSX80_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT 0x8 +#define PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800 +#define PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb +#define PSX80_PIF0_LANE7_OVRD2__RXPWR_7_MASK 0xe000 +#define PSX80_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT 0xd +#define PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000 +#define PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10 +#define PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000 +#define PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12 +#define PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000 +#define PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13 +#define PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000 +#define PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14 +#define PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000 +#define PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15 +#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000 +#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16 +#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000 +#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17 +#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000 +#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18 +#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000 +#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a +#define PSX81_PIF0_SCRATCH__PIF_SCRATCH_MASK 0xffffffff +#define PSX81_PIF0_SCRATCH__PIF_SCRATCH__SHIFT 0x0 +#define PSX81_PIF0_HW_DEBUG__HW_00_DEBUG_MASK 0x1 +#define PSX81_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 +#define PSX81_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2 +#define PSX81_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 +#define PSX81_PIF0_HW_DEBUG__HW_02_DEBUG_MASK 0x4 +#define PSX81_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 +#define PSX81_PIF0_HW_DEBUG__HW_03_DEBUG_MASK 0x8 +#define PSX81_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 +#define PSX81_PIF0_HW_DEBUG__HW_04_DEBUG_MASK 0x10 +#define PSX81_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 +#define PSX81_PIF0_HW_DEBUG__HW_05_DEBUG_MASK 0x20 +#define PSX81_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 +#define PSX81_PIF0_HW_DEBUG__HW_06_DEBUG_MASK 0x40 +#define PSX81_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 +#define PSX81_PIF0_HW_DEBUG__HW_07_DEBUG_MASK 0x80 +#define PSX81_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 +#define PSX81_PIF0_HW_DEBUG__HW_08_DEBUG_MASK 0x100 +#define PSX81_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 +#define PSX81_PIF0_HW_DEBUG__HW_09_DEBUG_MASK 0x200 +#define PSX81_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 +#define PSX81_PIF0_HW_DEBUG__HW_10_DEBUG_MASK 0x400 +#define PSX81_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa +#define PSX81_PIF0_HW_DEBUG__HW_11_DEBUG_MASK 0x800 +#define PSX81_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb +#define PSX81_PIF0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 +#define PSX81_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc +#define PSX81_PIF0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 +#define PSX81_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd +#define PSX81_PIF0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 +#define PSX81_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe +#define PSX81_PIF0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 +#define PSX81_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf +#define PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2 +#define PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1 +#define PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4 +#define PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2 +#define PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8 +#define PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3 +#define PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10 +#define PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4 +#define PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20 +#define PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5 +#define PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0 +#define PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6 +#define PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300 +#define PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8 +#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400 +#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa +#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800 +#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb +#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000 +#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc +#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000 +#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd +#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000 +#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe +#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000 +#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf +#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000 +#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10 +#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1 +#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0 +#define PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2 +#define PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1 +#define PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4 +#define PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2 +#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8 +#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3 +#define PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK 0x10 +#define PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4 +#define PSX81_PIF0_CTRL__PIF_PLL_STATUS_MASK 0xc0 +#define PSX81_PIF0_CTRL__PIF_PLL_STATUS__SHIFT 0x6 +#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100 +#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8 +#define PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200 +#define PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9 +#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400 +#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa +#define PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK 0x800 +#define PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb +#define PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000 +#define PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc +#define PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000 +#define PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd +#define PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000 +#define PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_S2_MASK 0x7 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000 +#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16 +#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000 +#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17 +#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000 +#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18 +#define PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7 +#define PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0 +#define PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38 +#define PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3 +#define PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0 +#define PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6 +#define PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200 +#define PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 +#define PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 +#define PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa +#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000 +#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10 +#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000 +#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11 +#define PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000 +#define PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15 +#define PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000 +#define PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16 +#define PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000 +#define PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19 +#define PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000 +#define PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a +#define PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000 +#define PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d +#define PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000 +#define PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_S2_MASK 0x7 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000 +#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16 +#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000 +#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17 +#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000 +#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18 +#define PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000 +#define PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19 +#define PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000 +#define PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a +#define PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7 +#define PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0 +#define PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38 +#define PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3 +#define PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0 +#define PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6 +#define PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200 +#define PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 +#define PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 +#define PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa +#define PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000 +#define PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10 +#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000 +#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11 +#define PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000 +#define PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13 +#define PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000 +#define PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15 +#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000 +#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18 +#define PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000 +#define PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19 +#define PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000 +#define PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000 +#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80 +#define PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7 +#define PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100 +#define PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8 +#define PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200 +#define PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9 +#define PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400 +#define PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa +#define PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800 +#define PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb +#define PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000 +#define PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10 +#define PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000 +#define PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11 +#define PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000 +#define PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80 +#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7 +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100 +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8 +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200 +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9 +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400 +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800 +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000 +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000 +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000 +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000 +#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000 +#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3 +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0 +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2 +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10 +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4 +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60 +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5 +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80 +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7 +#define PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100 +#define PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8 +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200 +#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000 +#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17 +#define PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1 +#define PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0 +#define PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2 +#define PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1 +#define PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4 +#define PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2 +#define PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8 +#define PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3 +#define PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10 +#define PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4 +#define PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20 +#define PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5 +#define PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40 +#define PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6 +#define PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80 +#define PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7 +#define PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100 +#define PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8 +#define PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200 +#define PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9 +#define PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400 +#define PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa +#define PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800 +#define PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb +#define PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000 +#define PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc +#define PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000 +#define PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd +#define PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000 +#define PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe +#define PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000 +#define PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf +#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000 +#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10 +#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000 +#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11 +#define PSX81_PIF0_LANE0_OVRD2__GANGMODE_0_MASK 0x7 +#define PSX81_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0 +#define PSX81_PIF0_LANE0_OVRD2__FREQDIV_0_MASK 0x18 +#define PSX81_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3 +#define PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK 0x60 +#define PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5 +#define PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80 +#define PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7 +#define PSX81_PIF0_LANE0_OVRD2__TXPWR_0_MASK 0x700 +#define PSX81_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT 0x8 +#define PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800 +#define PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb +#define PSX81_PIF0_LANE0_OVRD2__RXPWR_0_MASK 0xe000 +#define PSX81_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT 0xd +#define PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000 +#define PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10 +#define PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000 +#define PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12 +#define PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000 +#define PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13 +#define PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000 +#define PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14 +#define PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000 +#define PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15 +#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000 +#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16 +#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000 +#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17 +#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000 +#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18 +#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000 +#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a +#define PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1 +#define PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0 +#define PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2 +#define PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1 +#define PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4 +#define PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2 +#define PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8 +#define PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3 +#define PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10 +#define PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4 +#define PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20 +#define PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5 +#define PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40 +#define PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6 +#define PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80 +#define PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7 +#define PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100 +#define PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8 +#define PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200 +#define PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9 +#define PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400 +#define PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa +#define PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800 +#define PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb +#define PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000 +#define PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc +#define PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000 +#define PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd +#define PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000 +#define PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe +#define PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000 +#define PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf +#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000 +#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10 +#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000 +#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11 +#define PSX81_PIF0_LANE1_OVRD2__GANGMODE_1_MASK 0x7 +#define PSX81_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0 +#define PSX81_PIF0_LANE1_OVRD2__FREQDIV_1_MASK 0x18 +#define PSX81_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3 +#define PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK 0x60 +#define PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5 +#define PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80 +#define PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7 +#define PSX81_PIF0_LANE1_OVRD2__TXPWR_1_MASK 0x700 +#define PSX81_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT 0x8 +#define PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800 +#define PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb +#define PSX81_PIF0_LANE1_OVRD2__RXPWR_1_MASK 0xe000 +#define PSX81_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT 0xd +#define PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000 +#define PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10 +#define PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000 +#define PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12 +#define PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000 +#define PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13 +#define PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000 +#define PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14 +#define PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000 +#define PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15 +#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000 +#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16 +#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000 +#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17 +#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000 +#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18 +#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000 +#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a +#define PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1 +#define PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0 +#define PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2 +#define PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1 +#define PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4 +#define PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2 +#define PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8 +#define PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3 +#define PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10 +#define PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4 +#define PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20 +#define PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5 +#define PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40 +#define PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6 +#define PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80 +#define PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7 +#define PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100 +#define PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8 +#define PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200 +#define PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9 +#define PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400 +#define PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa +#define PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800 +#define PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb +#define PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000 +#define PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc +#define PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000 +#define PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd +#define PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000 +#define PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe +#define PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000 +#define PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf +#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000 +#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10 +#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000 +#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11 +#define PSX81_PIF0_LANE2_OVRD2__GANGMODE_2_MASK 0x7 +#define PSX81_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0 +#define PSX81_PIF0_LANE2_OVRD2__FREQDIV_2_MASK 0x18 +#define PSX81_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3 +#define PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK 0x60 +#define PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5 +#define PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80 +#define PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7 +#define PSX81_PIF0_LANE2_OVRD2__TXPWR_2_MASK 0x700 +#define PSX81_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT 0x8 +#define PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800 +#define PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb +#define PSX81_PIF0_LANE2_OVRD2__RXPWR_2_MASK 0xe000 +#define PSX81_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT 0xd +#define PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000 +#define PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10 +#define PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000 +#define PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12 +#define PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000 +#define PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13 +#define PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000 +#define PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14 +#define PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000 +#define PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15 +#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000 +#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16 +#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000 +#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17 +#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000 +#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18 +#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000 +#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a +#define PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1 +#define PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0 +#define PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2 +#define PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1 +#define PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4 +#define PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2 +#define PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8 +#define PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3 +#define PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10 +#define PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4 +#define PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20 +#define PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5 +#define PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40 +#define PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6 +#define PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80 +#define PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7 +#define PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100 +#define PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8 +#define PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200 +#define PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9 +#define PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400 +#define PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa +#define PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800 +#define PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb +#define PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000 +#define PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc +#define PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000 +#define PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd +#define PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000 +#define PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe +#define PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000 +#define PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf +#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000 +#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10 +#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000 +#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11 +#define PSX81_PIF0_LANE3_OVRD2__GANGMODE_3_MASK 0x7 +#define PSX81_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0 +#define PSX81_PIF0_LANE3_OVRD2__FREQDIV_3_MASK 0x18 +#define PSX81_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3 +#define PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK 0x60 +#define PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5 +#define PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80 +#define PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7 +#define PSX81_PIF0_LANE3_OVRD2__TXPWR_3_MASK 0x700 +#define PSX81_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT 0x8 +#define PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800 +#define PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb +#define PSX81_PIF0_LANE3_OVRD2__RXPWR_3_MASK 0xe000 +#define PSX81_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT 0xd +#define PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000 +#define PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10 +#define PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000 +#define PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12 +#define PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000 +#define PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13 +#define PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000 +#define PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14 +#define PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000 +#define PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15 +#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000 +#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16 +#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000 +#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17 +#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000 +#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18 +#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000 +#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a +#define PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1 +#define PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0 +#define PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2 +#define PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1 +#define PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4 +#define PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2 +#define PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8 +#define PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3 +#define PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10 +#define PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4 +#define PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20 +#define PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5 +#define PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40 +#define PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6 +#define PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80 +#define PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7 +#define PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100 +#define PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8 +#define PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200 +#define PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9 +#define PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400 +#define PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa +#define PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800 +#define PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb +#define PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000 +#define PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc +#define PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000 +#define PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd +#define PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000 +#define PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe +#define PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000 +#define PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf +#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000 +#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10 +#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000 +#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11 +#define PSX81_PIF0_LANE4_OVRD2__GANGMODE_4_MASK 0x7 +#define PSX81_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0 +#define PSX81_PIF0_LANE4_OVRD2__FREQDIV_4_MASK 0x18 +#define PSX81_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3 +#define PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK 0x60 +#define PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5 +#define PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80 +#define PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7 +#define PSX81_PIF0_LANE4_OVRD2__TXPWR_4_MASK 0x700 +#define PSX81_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT 0x8 +#define PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800 +#define PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb +#define PSX81_PIF0_LANE4_OVRD2__RXPWR_4_MASK 0xe000 +#define PSX81_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT 0xd +#define PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000 +#define PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10 +#define PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000 +#define PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12 +#define PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000 +#define PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13 +#define PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000 +#define PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14 +#define PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000 +#define PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15 +#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000 +#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16 +#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000 +#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17 +#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000 +#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18 +#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000 +#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a +#define PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1 +#define PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0 +#define PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2 +#define PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1 +#define PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4 +#define PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2 +#define PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8 +#define PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3 +#define PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10 +#define PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4 +#define PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20 +#define PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5 +#define PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40 +#define PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6 +#define PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80 +#define PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7 +#define PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100 +#define PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8 +#define PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200 +#define PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9 +#define PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400 +#define PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa +#define PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800 +#define PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb +#define PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000 +#define PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc +#define PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000 +#define PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd +#define PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000 +#define PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe +#define PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000 +#define PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf +#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000 +#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10 +#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000 +#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11 +#define PSX81_PIF0_LANE5_OVRD2__GANGMODE_5_MASK 0x7 +#define PSX81_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0 +#define PSX81_PIF0_LANE5_OVRD2__FREQDIV_5_MASK 0x18 +#define PSX81_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3 +#define PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK 0x60 +#define PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5 +#define PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80 +#define PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7 +#define PSX81_PIF0_LANE5_OVRD2__TXPWR_5_MASK 0x700 +#define PSX81_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT 0x8 +#define PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800 +#define PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb +#define PSX81_PIF0_LANE5_OVRD2__RXPWR_5_MASK 0xe000 +#define PSX81_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT 0xd +#define PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000 +#define PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10 +#define PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000 +#define PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12 +#define PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000 +#define PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13 +#define PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000 +#define PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14 +#define PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000 +#define PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15 +#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000 +#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16 +#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000 +#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17 +#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000 +#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18 +#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000 +#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a +#define PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1 +#define PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0 +#define PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2 +#define PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1 +#define PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4 +#define PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2 +#define PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8 +#define PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3 +#define PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10 +#define PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4 +#define PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20 +#define PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5 +#define PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40 +#define PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6 +#define PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80 +#define PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7 +#define PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100 +#define PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8 +#define PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200 +#define PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9 +#define PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400 +#define PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa +#define PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800 +#define PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb +#define PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000 +#define PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc +#define PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000 +#define PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd +#define PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000 +#define PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe +#define PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000 +#define PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf +#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000 +#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10 +#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000 +#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11 +#define PSX81_PIF0_LANE6_OVRD2__GANGMODE_6_MASK 0x7 +#define PSX81_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0 +#define PSX81_PIF0_LANE6_OVRD2__FREQDIV_6_MASK 0x18 +#define PSX81_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3 +#define PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK 0x60 +#define PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5 +#define PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80 +#define PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7 +#define PSX81_PIF0_LANE6_OVRD2__TXPWR_6_MASK 0x700 +#define PSX81_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT 0x8 +#define PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800 +#define PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb +#define PSX81_PIF0_LANE6_OVRD2__RXPWR_6_MASK 0xe000 +#define PSX81_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT 0xd +#define PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000 +#define PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10 +#define PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000 +#define PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12 +#define PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000 +#define PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13 +#define PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000 +#define PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14 +#define PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000 +#define PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15 +#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000 +#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16 +#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000 +#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17 +#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000 +#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18 +#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000 +#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a +#define PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1 +#define PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0 +#define PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2 +#define PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1 +#define PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4 +#define PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2 +#define PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8 +#define PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3 +#define PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10 +#define PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4 +#define PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20 +#define PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5 +#define PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40 +#define PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6 +#define PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80 +#define PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7 +#define PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100 +#define PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8 +#define PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200 +#define PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9 +#define PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400 +#define PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa +#define PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800 +#define PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb +#define PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000 +#define PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc +#define PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000 +#define PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd +#define PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000 +#define PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe +#define PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000 +#define PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf +#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000 +#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10 +#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000 +#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11 +#define PSX81_PIF0_LANE7_OVRD2__GANGMODE_7_MASK 0x7 +#define PSX81_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0 +#define PSX81_PIF0_LANE7_OVRD2__FREQDIV_7_MASK 0x18 +#define PSX81_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3 +#define PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK 0x60 +#define PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5 +#define PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80 +#define PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7 +#define PSX81_PIF0_LANE7_OVRD2__TXPWR_7_MASK 0x700 +#define PSX81_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT 0x8 +#define PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800 +#define PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb +#define PSX81_PIF0_LANE7_OVRD2__RXPWR_7_MASK 0xe000 +#define PSX81_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT 0xd +#define PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000 +#define PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10 +#define PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000 +#define PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12 +#define PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000 +#define PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13 +#define PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000 +#define PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14 +#define PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000 +#define PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15 +#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000 +#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16 +#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000 +#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17 +#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000 +#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18 +#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000 +#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a + +#endif /* BIF_5_1_SH_MASK_H */ -- cgit v1.2.3 From 26159c86dd004ef1295da9f68439ae50f3e8e60a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:17:19 -0400 Subject: drm/amdgpu: add DCE 8.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the DCE (Display and Composition Engine) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h | 5703 ++++++++ .../drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h | 13109 +++++++++++++++++++ 2 files changed, 18812 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h new file mode 100644 index 000000000000..dc52ea0df4b4 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h @@ -0,0 +1,5703 @@ +/* + * DCE_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_8_0_D_H +#define DCE_8_0_D_H + +#define mmPIPE0_PG_CONFIG 0x1760 +#define mmPIPE0_PG_ENABLE 0x1761 +#define mmPIPE0_PG_STATUS 0x1762 +#define mmPIPE1_PG_CONFIG 0x1764 +#define mmPIPE1_PG_ENABLE 0x1765 +#define mmPIPE1_PG_STATUS 0x1766 +#define mmPIPE2_PG_CONFIG 0x1768 +#define mmPIPE2_PG_ENABLE 0x1769 +#define mmPIPE2_PG_STATUS 0x176a +#define mmPIPE3_PG_CONFIG 0x176c +#define mmPIPE3_PG_ENABLE 0x176d +#define mmPIPE3_PG_STATUS 0x176e +#define mmPIPE4_PG_CONFIG 0x1770 +#define mmPIPE4_PG_ENABLE 0x1771 +#define mmPIPE4_PG_STATUS 0x1772 +#define mmPIPE5_PG_CONFIG 0x1774 +#define mmPIPE5_PG_ENABLE 0x1775 +#define mmPIPE5_PG_STATUS 0x1776 +#define mmDC_IP_REQUEST_CNTL 0x1778 +#define mmDC_PGFSM_CONFIG_REG 0x177c +#define mmDC_PGFSM_WRITE_REG 0x177d +#define mmDC_PGCNTL_STATUS_REG 0x177e +#define mmDCPG_TEST_DEBUG_INDEX 0x1779 +#define mmDCPG_TEST_DEBUG_DATA 0x177b +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 +#define mmBL1_PWM_USER_LEVEL 0x1629 +#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a +#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b +#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d +#define mmBL1_PWM_ABM_CNTL 0x162e +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f +#define mmBL1_PWM_GRP2_REG_LOCK 0x1630 +#define mmDC_ABM1_CNTL 0x1638 +#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e +#define mmDC_ABM1_ACE_THRES_12 0x163f +#define mmDC_ABM1_ACE_THRES_34 0x1640 +#define mmDC_ABM1_ACE_CNTL_MISC 0x1641 +#define mmDC_ABM1_DEBUG_MISC 0x1649 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a +#define mmDC_ABM1_HG_MISC_CTRL 0x164b +#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c +#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e +#define mmDC_ABM1_LS_PIXEL_COUNT 0x164f +#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 +#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 +#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a +#define mmDC_ABM1_HG_RESULT_1 0x165b +#define mmDC_ABM1_HG_RESULT_2 0x165c +#define mmDC_ABM1_HG_RESULT_3 0x165d +#define mmDC_ABM1_HG_RESULT_4 0x165e +#define mmDC_ABM1_HG_RESULT_5 0x165f +#define mmDC_ABM1_HG_RESULT_6 0x1660 +#define mmDC_ABM1_HG_RESULT_7 0x1661 +#define mmDC_ABM1_HG_RESULT_8 0x1662 +#define mmDC_ABM1_HG_RESULT_9 0x1663 +#define mmDC_ABM1_HG_RESULT_10 0x1664 +#define mmDC_ABM1_HG_RESULT_11 0x1665 +#define mmDC_ABM1_HG_RESULT_12 0x1666 +#define mmDC_ABM1_HG_RESULT_13 0x1667 +#define mmDC_ABM1_HG_RESULT_14 0x1668 +#define mmDC_ABM1_HG_RESULT_15 0x1669 +#define mmDC_ABM1_HG_RESULT_16 0x166a +#define mmDC_ABM1_HG_RESULT_17 0x166b +#define mmDC_ABM1_HG_RESULT_18 0x166c +#define mmDC_ABM1_HG_RESULT_19 0x166d +#define mmDC_ABM1_HG_RESULT_20 0x166e +#define mmDC_ABM1_HG_RESULT_21 0x166f +#define mmDC_ABM1_HG_RESULT_22 0x1670 +#define mmDC_ABM1_HG_RESULT_23 0x1671 +#define mmDC_ABM1_HG_RESULT_24 0x1672 +#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b +#define mmDC_ABM1_BL_MASTER_LOCK 0x169c +#define mmABM_TEST_DEBUG_INDEX 0x169e +#define mmABM_TEST_DEBUG_DATA 0x169f +#define mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c +#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c +#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1e7c +#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417c +#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447c +#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477c +#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4a7c +#define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d +#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d +#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1e7d +#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417d +#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447d +#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477d +#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4a7d +#define mmDCFE_DBG_SEL 0x1b7e +#define mmCRTC0_DCFE_DBG_SEL 0x1b7e +#define mmCRTC1_DCFE_DBG_SEL 0x1e7e +#define mmCRTC2_DCFE_DBG_SEL 0x417e +#define mmCRTC3_DCFE_DBG_SEL 0x447e +#define mmCRTC4_DCFE_DBG_SEL 0x477e +#define mmCRTC5_DCFE_DBG_SEL 0x4a7e +#define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f +#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f +#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1e7f +#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417f +#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447f +#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477f +#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4a7f +#define mmCRTC_H_TOTAL 0x1b80 +#define mmCRTC0_CRTC_H_TOTAL 0x1b80 +#define mmCRTC1_CRTC_H_TOTAL 0x1e80 +#define mmCRTC2_CRTC_H_TOTAL 0x4180 +#define mmCRTC3_CRTC_H_TOTAL 0x4480 +#define mmCRTC4_CRTC_H_TOTAL 0x4780 +#define mmCRTC5_CRTC_H_TOTAL 0x4a80 +#define mmCRTC_H_BLANK_START_END 0x1b81 +#define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 +#define mmCRTC1_CRTC_H_BLANK_START_END 0x1e81 +#define mmCRTC2_CRTC_H_BLANK_START_END 0x4181 +#define mmCRTC3_CRTC_H_BLANK_START_END 0x4481 +#define mmCRTC4_CRTC_H_BLANK_START_END 0x4781 +#define mmCRTC5_CRTC_H_BLANK_START_END 0x4a81 +#define mmCRTC_H_SYNC_A 0x1b82 +#define mmCRTC0_CRTC_H_SYNC_A 0x1b82 +#define mmCRTC1_CRTC_H_SYNC_A 0x1e82 +#define mmCRTC2_CRTC_H_SYNC_A 0x4182 +#define mmCRTC3_CRTC_H_SYNC_A 0x4482 +#define mmCRTC4_CRTC_H_SYNC_A 0x4782 +#define mmCRTC5_CRTC_H_SYNC_A 0x4a82 +#define mmCRTC_H_SYNC_A_CNTL 0x1b83 +#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 +#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1e83 +#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183 +#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483 +#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783 +#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4a83 +#define mmCRTC_H_SYNC_B 0x1b84 +#define mmCRTC0_CRTC_H_SYNC_B 0x1b84 +#define mmCRTC1_CRTC_H_SYNC_B 0x1e84 +#define mmCRTC2_CRTC_H_SYNC_B 0x4184 +#define mmCRTC3_CRTC_H_SYNC_B 0x4484 +#define mmCRTC4_CRTC_H_SYNC_B 0x4784 +#define mmCRTC5_CRTC_H_SYNC_B 0x4a84 +#define mmCRTC_H_SYNC_B_CNTL 0x1b85 +#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 +#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1e85 +#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185 +#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485 +#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785 +#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4a85 +#define mmCRTC_VBI_END 0x1b86 +#define mmCRTC0_CRTC_VBI_END 0x1b86 +#define mmCRTC1_CRTC_VBI_END 0x1e86 +#define mmCRTC2_CRTC_VBI_END 0x4186 +#define mmCRTC3_CRTC_VBI_END 0x4486 +#define mmCRTC4_CRTC_VBI_END 0x4786 +#define mmCRTC5_CRTC_VBI_END 0x4a86 +#define mmCRTC_V_TOTAL 0x1b87 +#define mmCRTC0_CRTC_V_TOTAL 0x1b87 +#define mmCRTC1_CRTC_V_TOTAL 0x1e87 +#define mmCRTC2_CRTC_V_TOTAL 0x4187 +#define mmCRTC3_CRTC_V_TOTAL 0x4487 +#define mmCRTC4_CRTC_V_TOTAL 0x4787 +#define mmCRTC5_CRTC_V_TOTAL 0x4a87 +#define mmCRTC_V_TOTAL_MIN 0x1b88 +#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 +#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1e88 +#define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188 +#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488 +#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788 +#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4a88 +#define mmCRTC_V_TOTAL_MAX 0x1b89 +#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 +#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1e89 +#define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189 +#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489 +#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789 +#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4a89 +#define mmCRTC_V_TOTAL_CONTROL 0x1b8a +#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a +#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1e8a +#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418a +#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448a +#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478a +#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4a8a +#define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b +#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b +#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1e8b +#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418b +#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448b +#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478b +#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4a8b +#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1e8c +#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418c +#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448c +#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478c +#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4a8c +#define mmCRTC_V_BLANK_START_END 0x1b8d +#define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d +#define mmCRTC1_CRTC_V_BLANK_START_END 0x1e8d +#define mmCRTC2_CRTC_V_BLANK_START_END 0x418d +#define mmCRTC3_CRTC_V_BLANK_START_END 0x448d +#define mmCRTC4_CRTC_V_BLANK_START_END 0x478d +#define mmCRTC5_CRTC_V_BLANK_START_END 0x4a8d +#define mmCRTC_V_SYNC_A 0x1b8e +#define mmCRTC0_CRTC_V_SYNC_A 0x1b8e +#define mmCRTC1_CRTC_V_SYNC_A 0x1e8e +#define mmCRTC2_CRTC_V_SYNC_A 0x418e +#define mmCRTC3_CRTC_V_SYNC_A 0x448e +#define mmCRTC4_CRTC_V_SYNC_A 0x478e +#define mmCRTC5_CRTC_V_SYNC_A 0x4a8e +#define mmCRTC_V_SYNC_A_CNTL 0x1b8f +#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f +#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1e8f +#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418f +#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448f +#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478f +#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4a8f +#define mmCRTC_V_SYNC_B 0x1b90 +#define mmCRTC0_CRTC_V_SYNC_B 0x1b90 +#define mmCRTC1_CRTC_V_SYNC_B 0x1e90 +#define mmCRTC2_CRTC_V_SYNC_B 0x4190 +#define mmCRTC3_CRTC_V_SYNC_B 0x4490 +#define mmCRTC4_CRTC_V_SYNC_B 0x4790 +#define mmCRTC5_CRTC_V_SYNC_B 0x4a90 +#define mmCRTC_V_SYNC_B_CNTL 0x1b91 +#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 +#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1e91 +#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191 +#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491 +#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791 +#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4a91 +#define mmCRTC_DTMTEST_CNTL 0x1b92 +#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 +#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1e92 +#define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192 +#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492 +#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792 +#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4a92 +#define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1e93 +#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193 +#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493 +#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793 +#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4a93 +#define mmCRTC_TRIGA_CNTL 0x1b94 +#define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 +#define mmCRTC1_CRTC_TRIGA_CNTL 0x1e94 +#define mmCRTC2_CRTC_TRIGA_CNTL 0x4194 +#define mmCRTC3_CRTC_TRIGA_CNTL 0x4494 +#define mmCRTC4_CRTC_TRIGA_CNTL 0x4794 +#define mmCRTC5_CRTC_TRIGA_CNTL 0x4a94 +#define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1e95 +#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195 +#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495 +#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795 +#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4a95 +#define mmCRTC_TRIGB_CNTL 0x1b96 +#define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 +#define mmCRTC1_CRTC_TRIGB_CNTL 0x1e96 +#define mmCRTC2_CRTC_TRIGB_CNTL 0x4196 +#define mmCRTC3_CRTC_TRIGB_CNTL 0x4496 +#define mmCRTC4_CRTC_TRIGB_CNTL 0x4796 +#define mmCRTC5_CRTC_TRIGB_CNTL 0x4a96 +#define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1e97 +#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197 +#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497 +#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797 +#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4a97 +#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1e98 +#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 +#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498 +#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 +#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4a98 +#define mmCRTC_FLOW_CONTROL 0x1b99 +#define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 +#define mmCRTC1_CRTC_FLOW_CONTROL 0x1e99 +#define mmCRTC2_CRTC_FLOW_CONTROL 0x4199 +#define mmCRTC3_CRTC_FLOW_CONTROL 0x4499 +#define mmCRTC4_CRTC_FLOW_CONTROL 0x4799 +#define mmCRTC5_CRTC_FLOW_CONTROL 0x4a99 +#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9b +#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9b +#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1e9b +#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419b +#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449b +#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479b +#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4a9b +#define mmCRTC_CONTROL 0x1b9c +#define mmCRTC0_CRTC_CONTROL 0x1b9c +#define mmCRTC1_CRTC_CONTROL 0x1e9c +#define mmCRTC2_CRTC_CONTROL 0x419c +#define mmCRTC3_CRTC_CONTROL 0x449c +#define mmCRTC4_CRTC_CONTROL 0x479c +#define mmCRTC5_CRTC_CONTROL 0x4a9c +#define mmCRTC_BLANK_CONTROL 0x1b9d +#define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d +#define mmCRTC1_CRTC_BLANK_CONTROL 0x1e9d +#define mmCRTC2_CRTC_BLANK_CONTROL 0x419d +#define mmCRTC3_CRTC_BLANK_CONTROL 0x449d +#define mmCRTC4_CRTC_BLANK_CONTROL 0x479d +#define mmCRTC5_CRTC_BLANK_CONTROL 0x4a9d +#define mmCRTC_INTERLACE_CONTROL 0x1b9e +#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e +#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1e9e +#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419e +#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449e +#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479e +#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4a9e +#define mmCRTC_INTERLACE_STATUS 0x1b9f +#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f +#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1e9f +#define mmCRTC2_CRTC_INTERLACE_STATUS 0x419f +#define mmCRTC3_CRTC_INTERLACE_STATUS 0x449f +#define mmCRTC4_CRTC_INTERLACE_STATUS 0x479f +#define mmCRTC5_CRTC_INTERLACE_STATUS 0x4a9f +#define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1ea0 +#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x41a0 +#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x44a0 +#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x47a0 +#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x4aa0 +#define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1ea1 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x41a1 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x44a1 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x47a1 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x4aa1 +#define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1ea2 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x41a2 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x44a2 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x47a2 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x4aa2 +#define mmCRTC_STATUS 0x1ba3 +#define mmCRTC0_CRTC_STATUS 0x1ba3 +#define mmCRTC1_CRTC_STATUS 0x1ea3 +#define mmCRTC2_CRTC_STATUS 0x41a3 +#define mmCRTC3_CRTC_STATUS 0x44a3 +#define mmCRTC4_CRTC_STATUS 0x47a3 +#define mmCRTC5_CRTC_STATUS 0x4aa3 +#define mmCRTC_STATUS_POSITION 0x1ba4 +#define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 +#define mmCRTC1_CRTC_STATUS_POSITION 0x1ea4 +#define mmCRTC2_CRTC_STATUS_POSITION 0x41a4 +#define mmCRTC3_CRTC_STATUS_POSITION 0x44a4 +#define mmCRTC4_CRTC_STATUS_POSITION 0x47a4 +#define mmCRTC5_CRTC_STATUS_POSITION 0x4aa4 +#define mmCRTC_NOM_VERT_POSITION 0x1ba5 +#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 +#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1ea5 +#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41a5 +#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44a5 +#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47a5 +#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4aa5 +#define mmCRTC_STATUS_FRAME_COUNT 0x1ba6 +#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 +#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1ea6 +#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41a6 +#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44a6 +#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47a6 +#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4aa6 +#define mmCRTC_STATUS_VF_COUNT 0x1ba7 +#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 +#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1ea7 +#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41a7 +#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44a7 +#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47a7 +#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4aa7 +#define mmCRTC_STATUS_HV_COUNT 0x1ba8 +#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 +#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1ea8 +#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41a8 +#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44a8 +#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47a8 +#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4aa8 +#define mmCRTC_COUNT_CONTROL 0x1ba9 +#define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 +#define mmCRTC1_CRTC_COUNT_CONTROL 0x1ea9 +#define mmCRTC2_CRTC_COUNT_CONTROL 0x41a9 +#define mmCRTC3_CRTC_COUNT_CONTROL 0x44a9 +#define mmCRTC4_CRTC_COUNT_CONTROL 0x47a9 +#define mmCRTC5_CRTC_COUNT_CONTROL 0x4aa9 +#define mmCRTC_COUNT_RESET 0x1baa +#define mmCRTC0_CRTC_COUNT_RESET 0x1baa +#define mmCRTC1_CRTC_COUNT_RESET 0x1eaa +#define mmCRTC2_CRTC_COUNT_RESET 0x41aa +#define mmCRTC3_CRTC_COUNT_RESET 0x44aa +#define mmCRTC4_CRTC_COUNT_RESET 0x47aa +#define mmCRTC5_CRTC_COUNT_RESET 0x4aaa +#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1eab +#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab +#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44ab +#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab +#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4aab +#define mmCRTC_VERT_SYNC_CONTROL 0x1bac +#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac +#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1eac +#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41ac +#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44ac +#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47ac +#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4aac +#define mmCRTC_STEREO_STATUS 0x1bad +#define mmCRTC0_CRTC_STEREO_STATUS 0x1bad +#define mmCRTC1_CRTC_STEREO_STATUS 0x1ead +#define mmCRTC2_CRTC_STEREO_STATUS 0x41ad +#define mmCRTC3_CRTC_STEREO_STATUS 0x44ad +#define mmCRTC4_CRTC_STEREO_STATUS 0x47ad +#define mmCRTC5_CRTC_STEREO_STATUS 0x4aad +#define mmCRTC_STEREO_CONTROL 0x1bae +#define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae +#define mmCRTC1_CRTC_STEREO_CONTROL 0x1eae +#define mmCRTC2_CRTC_STEREO_CONTROL 0x41ae +#define mmCRTC3_CRTC_STEREO_CONTROL 0x44ae +#define mmCRTC4_CRTC_STEREO_CONTROL 0x47ae +#define mmCRTC5_CRTC_STEREO_CONTROL 0x4aae +#define mmCRTC_SNAPSHOT_STATUS 0x1baf +#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf +#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1eaf +#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41af +#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44af +#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47af +#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4aaf +#define mmCRTC_SNAPSHOT_CONTROL 0x1bb0 +#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 +#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1eb0 +#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41b0 +#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44b0 +#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47b0 +#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4ab0 +#define mmCRTC_SNAPSHOT_POSITION 0x1bb1 +#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 +#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1eb1 +#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41b1 +#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44b1 +#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47b1 +#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4ab1 +#define mmCRTC_SNAPSHOT_FRAME 0x1bb2 +#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 +#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1eb2 +#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41b2 +#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44b2 +#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47b2 +#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4ab2 +#define mmCRTC_START_LINE_CONTROL 0x1bb3 +#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 +#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1eb3 +#define mmCRTC2_CRTC_START_LINE_CONTROL 0x41b3 +#define mmCRTC3_CRTC_START_LINE_CONTROL 0x44b3 +#define mmCRTC4_CRTC_START_LINE_CONTROL 0x47b3 +#define mmCRTC5_CRTC_START_LINE_CONTROL 0x4ab3 +#define mmCRTC_INTERRUPT_CONTROL 0x1bb4 +#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 +#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1eb4 +#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41b4 +#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44b4 +#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47b4 +#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4ab4 +#define mmCRTC_UPDATE_LOCK 0x1bb5 +#define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 +#define mmCRTC1_CRTC_UPDATE_LOCK 0x1eb5 +#define mmCRTC2_CRTC_UPDATE_LOCK 0x41b5 +#define mmCRTC3_CRTC_UPDATE_LOCK 0x44b5 +#define mmCRTC4_CRTC_UPDATE_LOCK 0x47b5 +#define mmCRTC5_CRTC_UPDATE_LOCK 0x4ab5 +#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1eb6 +#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 +#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44b6 +#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6 +#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4ab6 +#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1eb7 +#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 +#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44b7 +#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7 +#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4ab7 +#define mmCRTC_TEST_PATTERN_CONTROL 0x1bba +#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba +#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1eba +#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41ba +#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44ba +#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47ba +#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4aba +#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1ebb +#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41bb +#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44bb +#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47bb +#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4abb +#define mmCRTC_TEST_PATTERN_COLOR 0x1bbc +#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc +#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1ebc +#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41bc +#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44bc +#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47bc +#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4abc +#define mmMASTER_UPDATE_LOCK 0x1bbd +#define mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd +#define mmCRTC1_MASTER_UPDATE_LOCK 0x1ebd +#define mmCRTC2_MASTER_UPDATE_LOCK 0x41bd +#define mmCRTC3_MASTER_UPDATE_LOCK 0x44bd +#define mmCRTC4_MASTER_UPDATE_LOCK 0x47bd +#define mmCRTC5_MASTER_UPDATE_LOCK 0x4abd +#define mmMASTER_UPDATE_MODE 0x1bbe +#define mmCRTC0_MASTER_UPDATE_MODE 0x1bbe +#define mmCRTC1_MASTER_UPDATE_MODE 0x1ebe +#define mmCRTC2_MASTER_UPDATE_MODE 0x41be +#define mmCRTC3_MASTER_UPDATE_MODE 0x44be +#define mmCRTC4_MASTER_UPDATE_MODE 0x47be +#define mmCRTC5_MASTER_UPDATE_MODE 0x4abe +#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1ebf +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44bf +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4abf +#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1ec0 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44c0 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4ac0 +#define mmCRTC_MVP_STATUS 0x1bc1 +#define mmCRTC0_CRTC_MVP_STATUS 0x1bc1 +#define mmCRTC1_CRTC_MVP_STATUS 0x1ec1 +#define mmCRTC2_CRTC_MVP_STATUS 0x41c1 +#define mmCRTC3_CRTC_MVP_STATUS 0x44c1 +#define mmCRTC4_CRTC_MVP_STATUS 0x47c1 +#define mmCRTC5_CRTC_MVP_STATUS 0x4ac1 +#define mmCRTC_MASTER_EN 0x1bc2 +#define mmCRTC0_CRTC_MASTER_EN 0x1bc2 +#define mmCRTC1_CRTC_MASTER_EN 0x1ec2 +#define mmCRTC2_CRTC_MASTER_EN 0x41c2 +#define mmCRTC3_CRTC_MASTER_EN 0x44c2 +#define mmCRTC4_CRTC_MASTER_EN 0x47c2 +#define mmCRTC5_CRTC_MASTER_EN 0x4ac2 +#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1ec3 +#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 +#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44c3 +#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3 +#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4ac3 +#define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1ec4 +#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41c4 +#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44c4 +#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47c4 +#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4ac4 +#define mmCRTC_OVERSCAN_COLOR 0x1bc8 +#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 +#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1ec8 +#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41c8 +#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44c8 +#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47c8 +#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4ac8 +#define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1ec9 +#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x41c9 +#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x44c9 +#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x47c9 +#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x4ac9 +#define mmCRTC_BLANK_DATA_COLOR 0x1bca +#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca +#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1eca +#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41ca +#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44ca +#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47ca +#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4aca +#define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1ecb +#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x41cb +#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x44cb +#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x47cb +#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x4acb +#define mmCRTC_BLACK_COLOR 0x1bcc +#define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc +#define mmCRTC1_CRTC_BLACK_COLOR 0x1ecc +#define mmCRTC2_CRTC_BLACK_COLOR 0x41cc +#define mmCRTC3_CRTC_BLACK_COLOR 0x44cc +#define mmCRTC4_CRTC_BLACK_COLOR 0x47cc +#define mmCRTC5_CRTC_BLACK_COLOR 0x4acc +#define mmCRTC_BLACK_COLOR_EXT 0x1bcd +#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd +#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1ecd +#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x41cd +#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x44cd +#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x47cd +#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x4acd +#define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1ece +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x44ce +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x4ace +#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1ecf +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x44cf +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x4acf +#define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1ed0 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x44d0 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x4ad0 +#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1ed1 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x44d1 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x4ad1 +#define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1ed2 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x44d2 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x4ad2 +#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1ed3 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x44d3 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x4ad3 +#define mmCRTC_CRC_CNTL 0x1bd4 +#define mmCRTC0_CRTC_CRC_CNTL 0x1bd4 +#define mmCRTC1_CRTC_CRC_CNTL 0x1ed4 +#define mmCRTC2_CRTC_CRC_CNTL 0x41d4 +#define mmCRTC3_CRTC_CRC_CNTL 0x44d4 +#define mmCRTC4_CRTC_CRC_CNTL 0x47d4 +#define mmCRTC5_CRTC_CRC_CNTL 0x4ad4 +#define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1ed5 +#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 +#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x44d5 +#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5 +#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x4ad5 +#define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1ed6 +#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 +#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x44d6 +#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6 +#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x4ad6 +#define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1ed7 +#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 +#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x44d7 +#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7 +#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x4ad7 +#define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1ed8 +#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 +#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x44d8 +#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8 +#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x4ad8 +#define mmCRTC_CRC0_DATA_RG 0x1bd9 +#define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 +#define mmCRTC1_CRTC_CRC0_DATA_RG 0x1ed9 +#define mmCRTC2_CRTC_CRC0_DATA_RG 0x41d9 +#define mmCRTC3_CRTC_CRC0_DATA_RG 0x44d9 +#define mmCRTC4_CRTC_CRC0_DATA_RG 0x47d9 +#define mmCRTC5_CRTC_CRC0_DATA_RG 0x4ad9 +#define mmCRTC_CRC0_DATA_B 0x1bda +#define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda +#define mmCRTC1_CRTC_CRC0_DATA_B 0x1eda +#define mmCRTC2_CRTC_CRC0_DATA_B 0x41da +#define mmCRTC3_CRTC_CRC0_DATA_B 0x44da +#define mmCRTC4_CRTC_CRC0_DATA_B 0x47da +#define mmCRTC5_CRTC_CRC0_DATA_B 0x4ada +#define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1edb +#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db +#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x44db +#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db +#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x4adb +#define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1edc +#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc +#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x44dc +#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc +#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x4adc +#define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1edd +#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd +#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x44dd +#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd +#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x4add +#define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1ede +#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de +#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x44de +#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de +#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x4ade +#define mmCRTC_CRC1_DATA_RG 0x1bdf +#define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf +#define mmCRTC1_CRTC_CRC1_DATA_RG 0x1edf +#define mmCRTC2_CRTC_CRC1_DATA_RG 0x41df +#define mmCRTC3_CRTC_CRC1_DATA_RG 0x44df +#define mmCRTC4_CRTC_CRC1_DATA_RG 0x47df +#define mmCRTC5_CRTC_CRC1_DATA_RG 0x4adf +#define mmCRTC_CRC1_DATA_B 0x1be0 +#define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 +#define mmCRTC1_CRTC_CRC1_DATA_B 0x1ee0 +#define mmCRTC2_CRTC_CRC1_DATA_B 0x41e0 +#define mmCRTC3_CRTC_CRC1_DATA_B 0x44e0 +#define mmCRTC4_CRTC_CRC1_DATA_B 0x47e0 +#define mmCRTC5_CRTC_CRC1_DATA_B 0x4ae0 +#define mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1ee1 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x44e1 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x4ae1 +#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1ee2 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x44e2 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x4ae2 +#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1ee3 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x44e3 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x4ae3 +#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1ee4 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x44e4 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x4ae4 +#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1ee5 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x44e5 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x4ae5 +#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1ee6 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x44e6 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x4ae6 +#define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1ee7 +#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x41e7 +#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x44e7 +#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x47e7 +#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x4ae7 +#define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1e78 +#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178 +#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478 +#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778 +#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4a78 +#define mmCRTC_GSL_VSYNC_GAP 0x1b79 +#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 +#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1e79 +#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179 +#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479 +#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779 +#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4a79 +#define mmCRTC_GSL_WINDOW 0x1b7a +#define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a +#define mmCRTC1_CRTC_GSL_WINDOW 0x1e7a +#define mmCRTC2_CRTC_GSL_WINDOW 0x417a +#define mmCRTC3_CRTC_GSL_WINDOW 0x447a +#define mmCRTC4_CRTC_GSL_WINDOW 0x477a +#define mmCRTC5_CRTC_GSL_WINDOW 0x4a7a +#define mmCRTC_GSL_CONTROL 0x1b7b +#define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b +#define mmCRTC1_CRTC_GSL_CONTROL 0x1e7b +#define mmCRTC2_CRTC_GSL_CONTROL 0x417b +#define mmCRTC3_CRTC_GSL_CONTROL 0x447b +#define mmCRTC4_CRTC_GSL_CONTROL 0x477b +#define mmCRTC5_CRTC_GSL_CONTROL 0x4a7b +#define mmCRTC_TEST_DEBUG_INDEX 0x1bc6 +#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 +#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1ec6 +#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41c6 +#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44c6 +#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47c6 +#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4ac6 +#define mmCRTC_TEST_DEBUG_DATA 0x1bc7 +#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 +#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1ec7 +#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41c7 +#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44c7 +#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47c7 +#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4ac7 +#define mmDAC_ENABLE 0x19e4 +#define mmDAC_SOURCE_SELECT 0x19e5 +#define mmDAC_CRC_EN 0x19e6 +#define mmDAC_CRC_CONTROL 0x19e7 +#define mmDAC_CRC_SIG_RGB_MASK 0x19e8 +#define mmDAC_CRC_SIG_CONTROL_MASK 0x19e9 +#define mmDAC_CRC_SIG_RGB 0x19ea +#define mmDAC_CRC_SIG_CONTROL 0x19eb +#define mmDAC_SYNC_TRISTATE_CONTROL 0x19ec +#define mmDAC_STEREOSYNC_SELECT 0x19ed +#define mmDAC_AUTODETECT_CONTROL 0x19ee +#define mmDAC_AUTODETECT_CONTROL2 0x19ef +#define mmDAC_AUTODETECT_CONTROL3 0x19f0 +#define mmDAC_AUTODETECT_STATUS 0x19f1 +#define mmDAC_AUTODETECT_INT_CONTROL 0x19f2 +#define mmDAC_FORCE_OUTPUT_CNTL 0x19f3 +#define mmDAC_FORCE_DATA 0x19f4 +#define mmDAC_POWERDOWN 0x19f5 +#define mmDAC_CONTROL 0x19f6 +#define mmDAC_COMPARATOR_ENABLE 0x19f7 +#define mmDAC_COMPARATOR_OUTPUT 0x19f8 +#define mmDAC_PWR_CNTL 0x19f9 +#define mmDAC_DFT_CONFIG 0x19fa +#define mmDAC_FIFO_STATUS 0x19fb +#define mmPERFCOUNTER_CNTL 0x170 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x1870 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1b24 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1e24 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x4124 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x4424 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4724 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4a24 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4c40 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4d14 +#define mmPERFCOUNTER_STATE 0x171 +#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 +#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x1871 +#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x1b25 +#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1e25 +#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x4125 +#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x4425 +#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4725 +#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4a25 +#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4c41 +#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4d15 +#define mmPERFMON_CNTL 0x173 +#define mmDC_PERFMON0_PERFMON_CNTL 0x173 +#define mmDC_PERFMON1_PERFMON_CNTL 0x1873 +#define mmDC_PERFMON2_PERFMON_CNTL 0x1b27 +#define mmDC_PERFMON3_PERFMON_CNTL 0x1e27 +#define mmDC_PERFMON4_PERFMON_CNTL 0x4127 +#define mmDC_PERFMON5_PERFMON_CNTL 0x4427 +#define mmDC_PERFMON6_PERFMON_CNTL 0x4727 +#define mmDC_PERFMON7_PERFMON_CNTL 0x4a27 +#define mmDC_PERFMON8_PERFMON_CNTL 0x4c43 +#define mmDC_PERFMON9_PERFMON_CNTL 0x4d17 +#define mmPERFMON_CVALUE_INT_MISC 0x172 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x1872 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1b26 +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1e26 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x4126 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x4426 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4726 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4a26 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4c42 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4d16 +#define mmPERFMON_CVALUE_LOW 0x174 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x1874 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1b28 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1e28 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x4128 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x4428 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4728 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4a28 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4c44 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4d18 +#define mmPERFMON_HI 0x175 +#define mmDC_PERFMON0_PERFMON_HI 0x175 +#define mmDC_PERFMON1_PERFMON_HI 0x1875 +#define mmDC_PERFMON2_PERFMON_HI 0x1b29 +#define mmDC_PERFMON3_PERFMON_HI 0x1e29 +#define mmDC_PERFMON4_PERFMON_HI 0x4129 +#define mmDC_PERFMON5_PERFMON_HI 0x4429 +#define mmDC_PERFMON6_PERFMON_HI 0x4729 +#define mmDC_PERFMON7_PERFMON_HI 0x4a29 +#define mmDC_PERFMON8_PERFMON_HI 0x4c45 +#define mmDC_PERFMON9_PERFMON_HI 0x4d19 +#define mmPERFMON_LOW 0x176 +#define mmDC_PERFMON0_PERFMON_LOW 0x176 +#define mmDC_PERFMON1_PERFMON_LOW 0x1876 +#define mmDC_PERFMON2_PERFMON_LOW 0x1b2a +#define mmDC_PERFMON3_PERFMON_LOW 0x1e2a +#define mmDC_PERFMON4_PERFMON_LOW 0x412a +#define mmDC_PERFMON5_PERFMON_LOW 0x442a +#define mmDC_PERFMON6_PERFMON_LOW 0x472a +#define mmDC_PERFMON7_PERFMON_LOW 0x4a2a +#define mmDC_PERFMON8_PERFMON_LOW 0x4c46 +#define mmDC_PERFMON9_PERFMON_LOW 0x4d1a +#define mmPERFMON_TEST_DEBUG_INDEX 0x177 +#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 +#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x1877 +#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x1b2b +#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1e2b +#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x412b +#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x442b +#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x472b +#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x4a2b +#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x4c47 +#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x4d1b +#define mmPERFMON_TEST_DEBUG_DATA 0x178 +#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 +#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x1878 +#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x1b2c +#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1e2c +#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x412c +#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x442c +#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x472c +#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x4a2c +#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x4c48 +#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x4d1c +#define mmVGA25_PPLL_REF_DIV 0xd8 +#define mmVGA28_PPLL_REF_DIV 0xd9 +#define mmVGA41_PPLL_REF_DIV 0xda +#define mmVGA25_PPLL_FB_DIV 0xdc +#define mmVGA28_PPLL_FB_DIV 0xdd +#define mmVGA41_PPLL_FB_DIV 0xde +#define mmVGA25_PPLL_POST_DIV 0xe0 +#define mmVGA28_PPLL_POST_DIV 0xe1 +#define mmVGA41_PPLL_POST_DIV 0xe2 +#define mmVGA25_PPLL_ANALOG 0xe4 +#define mmVGA28_PPLL_ANALOG 0xe5 +#define mmVGA41_PPLL_ANALOG 0xe6 +#define mmDPREFCLK_CNTL 0x118 +#define mmSCANIN_SOFT_RESET 0x11e +#define mmDCCG_GTC_CNTL 0x120 +#define mmDCCG_GTC_DTO_INCR 0x121 +#define mmDCCG_GTC_DTO_MODULO 0x122 +#define mmDCCG_GTC_CURRENT 0x123 +#define mmDCCG_DS_DTO_INCR 0x113 +#define mmDCCG_DS_DTO_MODULO 0x114 +#define mmDCCG_DS_CNTL 0x115 +#define mmDCCG_DS_HW_CAL_INTERVAL 0x116 +#define mmDCCG_DS_DEBUG_CNTL 0x112 +#define mmDMCU_SMU_INTERRUPT_CNTL 0x12c +#define mmSMU_CONTROL 0x12d +#define mmSMU_INTERRUPT_CONTROL 0x12e +#define mmDAC_CLK_ENABLE 0x128 +#define mmDVO_CLK_ENABLE 0x129 +#define mmDCCG_GATE_DISABLE_CNTL 0x134 +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 +#define mmSCLK_CGTT_BLK_CTRL_REG 0x136 +#define mmDCCG_CAC_STATUS 0x137 +#define mmPIXCLK1_RESYNC_CNTL 0x138 +#define mmPIXCLK2_RESYNC_CNTL 0x139 +#define mmPIXCLK0_RESYNC_CNTL 0x13a +#define mmMICROSECOND_TIME_BASE_DIV 0x13b +#define mmDCCG_DISP_CNTL_REG 0x13f +#define mmDISPPLL_BG_CNTL 0x13c +#define mmDIG_SOFT_RESET 0x13d +#define mmMILLISECOND_TIME_BASE_DIV 0x130 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x131 +#define mmLIGHT_SLEEP_CNTL 0x132 +#define mmDCCG_PERFMON_CNTL 0x133 +#define mmCRTC0_PIXEL_RATE_CNTL 0x140 +#define mmDP_DTO0_PHASE 0x141 +#define mmDP_DTO0_MODULO 0x142 +#define mmCRTC1_PIXEL_RATE_CNTL 0x144 +#define mmDP_DTO1_PHASE 0x145 +#define mmDP_DTO1_MODULO 0x146 +#define mmCRTC2_PIXEL_RATE_CNTL 0x148 +#define mmDP_DTO2_PHASE 0x149 +#define mmDP_DTO2_MODULO 0x14a +#define mmCRTC3_PIXEL_RATE_CNTL 0x14c +#define mmDP_DTO3_PHASE 0x14d +#define mmDP_DTO3_MODULO 0x14e +#define mmCRTC4_PIXEL_RATE_CNTL 0x150 +#define mmDP_DTO4_PHASE 0x151 +#define mmDP_DTO4_MODULO 0x152 +#define mmCRTC5_PIXEL_RATE_CNTL 0x154 +#define mmDP_DTO5_PHASE 0x155 +#define mmDP_DTO5_MODULO 0x156 +#define mmDCFE0_SOFT_RESET 0x158 +#define mmDCFE1_SOFT_RESET 0x159 +#define mmDCFE2_SOFT_RESET 0x15a +#define mmDCFE3_SOFT_RESET 0x15b +#define mmDCFE4_SOFT_RESET 0x15c +#define mmDCFE5_SOFT_RESET 0x15d +#define mmDCI_SOFT_RESET 0x15e +#define mmDCCG_SOFT_RESET 0x15f +#define mmSYMCLKA_CLOCK_ENABLE 0x160 +#define mmSYMCLKB_CLOCK_ENABLE 0x161 +#define mmSYMCLKC_CLOCK_ENABLE 0x162 +#define mmSYMCLKD_CLOCK_ENABLE 0x163 +#define mmSYMCLKE_CLOCK_ENABLE 0x164 +#define mmSYMCLKF_CLOCK_ENABLE 0x165 +#define mmSYMCLKG_CLOCK_ENABLE 0x117 +#define mmUNIPHY_SOFT_RESET 0x166 +#define mmDCO_SOFT_RESET 0x167 +#define mmDVOACLKD_CNTL 0x168 +#define mmDVOACLKC_MVP_CNTL 0x169 +#define mmDVOACLKC_CNTL 0x16a +#define mmDCCG_AUDIO_DTO_SOURCE 0x16b +#define mmDCCG_AUDIO_DTO0_PHASE 0x16c +#define mmDCCG_AUDIO_DTO0_MODULE 0x16d +#define mmDCCG_AUDIO_DTO1_PHASE 0x16e +#define mmDCCG_AUDIO_DTO1_MODULE 0x16f +#define mmDCCG_TEST_DEBUG_INDEX 0x17c +#define mmDCCG_TEST_DEBUG_DATA 0x17d +#define mmDCCG_TEST_CLK_SEL 0x17e +#define mmPLL_REF_DIV 0x1700 +#define mmDCCG_PLL0_PLL_REF_DIV 0x1700 +#define mmDCCG_PLL1_PLL_REF_DIV 0x1714 +#define mmDCCG_PLL2_PLL_REF_DIV 0x1728 +#define mmDCCG_PLL3_PLL_REF_DIV 0x173c +#define mmPLL_FB_DIV 0x1701 +#define mmDCCG_PLL0_PLL_FB_DIV 0x1701 +#define mmDCCG_PLL1_PLL_FB_DIV 0x1715 +#define mmDCCG_PLL2_PLL_FB_DIV 0x1729 +#define mmDCCG_PLL3_PLL_FB_DIV 0x173d +#define mmPLL_POST_DIV 0x1702 +#define mmDCCG_PLL0_PLL_POST_DIV 0x1702 +#define mmDCCG_PLL1_PLL_POST_DIV 0x1716 +#define mmDCCG_PLL2_PLL_POST_DIV 0x172a +#define mmDCCG_PLL3_PLL_POST_DIV 0x173e +#define mmPLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1717 +#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x172b +#define mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC 0x173f +#define mmPLL_SS_CNTL 0x1704 +#define mmDCCG_PLL0_PLL_SS_CNTL 0x1704 +#define mmDCCG_PLL1_PLL_SS_CNTL 0x1718 +#define mmDCCG_PLL2_PLL_SS_CNTL 0x172c +#define mmDCCG_PLL3_PLL_SS_CNTL 0x1740 +#define mmPLL_DS_CNTL 0x1705 +#define mmDCCG_PLL0_PLL_DS_CNTL 0x1705 +#define mmDCCG_PLL1_PLL_DS_CNTL 0x1719 +#define mmDCCG_PLL2_PLL_DS_CNTL 0x172d +#define mmDCCG_PLL3_PLL_DS_CNTL 0x1741 +#define mmPLL_IDCLK_CNTL 0x1706 +#define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706 +#define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x171a +#define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x172e +#define mmDCCG_PLL3_PLL_IDCLK_CNTL 0x1742 +#define mmPLL_CNTL 0x1707 +#define mmDCCG_PLL0_PLL_CNTL 0x1707 +#define mmDCCG_PLL1_PLL_CNTL 0x171b +#define mmDCCG_PLL2_PLL_CNTL 0x172f +#define mmDCCG_PLL3_PLL_CNTL 0x1743 +#define mmPLL_ANALOG 0x1708 +#define mmDCCG_PLL0_PLL_ANALOG 0x1708 +#define mmDCCG_PLL1_PLL_ANALOG 0x171c +#define mmDCCG_PLL2_PLL_ANALOG 0x1730 +#define mmDCCG_PLL3_PLL_ANALOG 0x1744 +#define mmPLL_ANALOG_CNTL 0x1711 +#define mmDCCG_PLL0_PLL_ANALOG_CNTL 0x1711 +#define mmDCCG_PLL1_PLL_ANALOG_CNTL 0x1725 +#define mmDCCG_PLL2_PLL_ANALOG_CNTL 0x1739 +#define mmDCCG_PLL3_PLL_ANALOG_CNTL 0x174d +#define mmPLL_VREG_CNTL 0x1709 +#define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709 +#define mmDCCG_PLL1_PLL_VREG_CNTL 0x171d +#define mmDCCG_PLL2_PLL_VREG_CNTL 0x1731 +#define mmDCCG_PLL3_PLL_VREG_CNTL 0x1745 +#define mmPLL_XOR_LOCK 0x1710 +#define mmDCCG_PLL0_PLL_XOR_LOCK 0x1710 +#define mmDCCG_PLL1_PLL_XOR_LOCK 0x1724 +#define mmDCCG_PLL2_PLL_XOR_LOCK 0x1738 +#define mmDCCG_PLL3_PLL_XOR_LOCK 0x174c +#define mmPLL_UNLOCK_DETECT_CNTL 0x170a +#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a +#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171e +#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x1732 +#define mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL 0x1746 +#define mmPLL_DEBUG_CNTL 0x170b +#define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170b +#define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171f +#define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x1733 +#define mmDCCG_PLL3_PLL_DEBUG_CNTL 0x1747 +#define mmPLL_UPDATE_LOCK 0x170c +#define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170c +#define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x1720 +#define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x1734 +#define mmDCCG_PLL3_PLL_UPDATE_LOCK 0x1748 +#define mmPLL_UPDATE_CNTL 0x170d +#define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170d +#define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x1721 +#define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x1735 +#define mmDCCG_PLL3_PLL_UPDATE_CNTL 0x1749 +#define mmPLL_DISPCLK_DTO_CNTL 0x170e +#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170e +#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x1722 +#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x1736 +#define mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL 0x174a +#define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170f +#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170f +#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1723 +#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1737 +#define mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE 0x174b +#define mmDENTIST_DISPCLK_CNTL 0x124 +#define mmDCDEBUG_BUS_CLK1_SEL 0x1860 +#define mmDCDEBUG_BUS_CLK2_SEL 0x1861 +#define mmDCDEBUG_BUS_CLK3_SEL 0x1862 +#define mmDCDEBUG_BUS_CLK4_SEL 0x1863 +#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186a +#define mmDCDEBUG_OUT_CNTL 0x186b +#define mmDCDEBUG_OUT_DATA 0x186e +#define mmDMIF_ADDR_CONFIG 0x2f5 +#define mmDMIF_CONTROL 0x2f6 +#define mmDMIF_STATUS 0x2f7 +#define mmDMIF_HW_DEBUG 0x2f8 +#define mmDMIF_ARBITRATION_CONTROL 0x2f9 +#define mmPIPE0_ARBITRATION_CONTROL3 0x2fa +#define mmPIPE1_ARBITRATION_CONTROL3 0x2fb +#define mmPIPE2_ARBITRATION_CONTROL3 0x2fc +#define mmPIPE3_ARBITRATION_CONTROL3 0x2fd +#define mmPIPE4_ARBITRATION_CONTROL3 0x2fe +#define mmPIPE5_ARBITRATION_CONTROL3 0x2ff +#define mmDMIF_TEST_DEBUG_INDEX 0x312 +#define mmDMIF_TEST_DEBUG_DATA 0x313 +#define ixDMIF_DEBUG02_CORE0 0x2 +#define ixDMIF_DEBUG02_CORE1 0xa +#define mmDMIF_ADDR_CALC 0x300 +#define mmDMIF_STATUS2 0x301 +#define mmPIPE0_MAX_REQUESTS 0x302 +#define mmPIPE1_MAX_REQUESTS 0x303 +#define mmPIPE2_MAX_REQUESTS 0x304 +#define mmPIPE3_MAX_REQUESTS 0x305 +#define mmPIPE4_MAX_REQUESTS 0x306 +#define mmPIPE5_MAX_REQUESTS 0x307 +#define mmLOW_POWER_TILING_CONTROL 0x325 +#define mmMCIF_CONTROL 0x314 +#define mmMCIF_WRITE_COMBINE_CONTROL 0x315 +#define mmMCIF_TEST_DEBUG_INDEX 0x316 +#define mmMCIF_TEST_DEBUG_DATA 0x317 +#define ixIDDCCIF02_DBG_DCCIF_C 0x9 +#define ixIDDCCIF04_DBG_DCCIF_E 0xb +#define ixIDDCCIF05_DBG_DCCIF_F 0xc +#define mmMCIF_VMID 0x318 +#define mmMCIF_MEM_CONTROL 0x319 +#define mmCC_DC_PIPE_DIS 0x177f +#define mmMC_DC_INTERFACE_NACK_STATUS 0x31c +#define mmDC_RBBMIF_RDWR_CNTL1 0x31a +#define mmDC_RBBMIF_RDWR_CNTL2 0x31d +#define mmDC_RBBMIF_RDWR_CNTL3 0x311 +#define mmDCI_MEM_PWR_STATE 0x31b +#define mmDCI_MEM_PWR_STATE2 0x322 +#define mmDCI_CLK_CNTL 0x31e +#define mmDCCG_VPCLK_CNTL 0x31f +#define mmDCI_MEM_PWR_CNTL 0x326 +#define mmDC_XDMA_INTERFACE_CNTL 0x327 +#define mmDCI_TEST_DEBUG_INDEX 0x320 +#define mmDCI_TEST_DEBUG_DATA 0x321 +#define mmDCI_DEBUG_CONFIG 0x323 +#define mmPIPE0_DMIF_BUFFER_CONTROL 0x328 +#define mmPIPE1_DMIF_BUFFER_CONTROL 0x330 +#define mmPIPE2_DMIF_BUFFER_CONTROL 0x338 +#define mmPIPE3_DMIF_BUFFER_CONTROL 0x340 +#define mmPIPE4_DMIF_BUFFER_CONTROL 0x348 +#define mmPIPE5_DMIF_BUFFER_CONTROL 0x350 +#define mmMCIF_BUFMGR_SW_CONTROL 0x358 +#define mmMCIF_BUFMGR_STATUS 0x35a +#define mmMCIF_BUF_PITCH 0x35b +#define mmMCIF_BUF_1_ADDR_Y_LOW 0x35c +#define mmMCIF_BUF_2_ADDR_Y_LOW 0x360 +#define mmMCIF_BUF_3_ADDR_Y_LOW 0x364 +#define mmMCIF_BUF_4_ADDR_Y_LOW 0x368 +#define mmMCIF_BUF_1_ADDR_UP 0x35d +#define mmMCIF_BUF_2_ADDR_UP 0x361 +#define mmMCIF_BUF_3_ADDR_UP 0x365 +#define mmMCIF_BUF_4_ADDR_UP 0x369 +#define mmMCIF_BUF_1_ADDR_C_LOW 0x35e +#define mmMCIF_BUF_2_ADDR_C_LOW 0x362 +#define mmMCIF_BUF_3_ADDR_C_LOW 0x366 +#define mmMCIF_BUF_4_ADDR_C_LOW 0x36a +#define mmMCIF_BUF_1_STATUS 0x35f +#define mmMCIF_BUF_2_STATUS 0x363 +#define mmMCIF_BUF_3_STATUS 0x367 +#define mmMCIF_BUF_4_STATUS 0x36b +#define mmMCIF_SI_ARBITRATION_CONTROL 0x36c +#define mmMCIF_URGENCY_WATERMARK 0x36d +#define mmDC_GENERICA 0x1900 +#define mmDC_GENERICB 0x1901 +#define mmDC_PAD_EXTERN_SIG 0x1902 +#define mmDC_REF_CLK_CNTL 0x1903 +#define mmDC_GPIO_DEBUG 0x1904 +#define mmDCO_MEM_POWER_STATE 0x1906 +#define mmDCO_MEM_POWER_STATE_2 0x193a +#define mmDCO_LIGHT_SLEEP_DIS 0x1907 +#define mmUNIPHY_IMPCAL_LINKA 0x1908 +#define mmUNIPHY_IMPCAL_LINKB 0x1909 +#define mmUNIPHY_IMPCAL_PERIOD 0x190a +#define mmAUXP_IMPCAL 0x190b +#define mmAUXN_IMPCAL 0x190c +#define mmDCIO_IMPCAL_CNTL_AB 0x190d +#define mmUNIPHY_IMPCAL_PSW_AB 0x190e +#define mmUNIPHY_IMPCAL_LINKC 0x190f +#define mmUNIPHY_IMPCAL_LINKD 0x1910 +#define mmDCIO_IMPCAL_CNTL_CD 0x1911 +#define mmUNIPHY_IMPCAL_PSW_CD 0x1912 +#define mmUNIPHY_IMPCAL_LINKE 0x1913 +#define mmUNIPHY_IMPCAL_LINKF 0x1914 +#define mmDCIO_IMPCAL_CNTL_EF 0x1915 +#define mmUNIPHY_IMPCAL_PSW_EF 0x1916 +#define mmDC_PINSTRAPS 0x1917 +#define mmDC_DVODATA_CONFIG 0x1905 +#define mmLVTMA_PWRSEQ_CNTL 0x1919 +#define mmLVTMA_PWRSEQ_STATE 0x191a +#define mmLVTMA_PWRSEQ_REF_DIV 0x191b +#define mmLVTMA_PWRSEQ_DELAY1 0x191c +#define mmLVTMA_PWRSEQ_DELAY2 0x191d +#define mmBL_PWM_CNTL 0x191e +#define mmBL_PWM_CNTL2 0x191f +#define mmBL_PWM_PERIOD_CNTL 0x1920 +#define mmBL_PWM_GRP1_REG_LOCK 0x1921 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923 +#define mmDCIO_GSL0_CNTL 0x1924 +#define mmDCIO_GSL1_CNTL 0x1925 +#define mmDCIO_GSL2_CNTL 0x1926 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927 +#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928 +#define mmDC_GPU_TIMER_READ 0x1929 +#define mmDC_GPU_TIMER_READ_CNTL 0x192a +#define mmDCO_CLK_CNTL 0x192b +#define mmDCO_CLK_RAMP_CNTL 0x192c +#define mmDCIO_DEBUG 0x192e +#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x1937 +#define mmDCIO_TEST_DEBUG_INDEX 0x192f +#define mmDCIO_TEST_DEBUG_DATA 0x1930 +#define ixDCIO_DEBUG1 0x1 +#define ixDCIO_DEBUG2 0x2 +#define ixDCIO_DEBUG3 0x3 +#define ixDCIO_DEBUG4 0x4 +#define ixDCIO_DEBUG5 0x5 +#define ixDCIO_DEBUG6 0x6 +#define ixDCIO_DEBUG7 0x7 +#define ixDCIO_DEBUG8 0x8 +#define ixDCIO_DEBUG9 0x9 +#define ixDCIO_DEBUGA 0xa +#define ixDCIO_DEBUGB 0xb +#define ixDCIO_DEBUGC 0xc +#define ixDCIO_DEBUGD 0xd +#define ixDCIO_DEBUGE 0xe +#define ixDCIO_DEBUGF 0xf +#define ixDCIO_DEBUG10 0x10 +#define ixDCIO_DEBUG11 0x11 +#define ixDCIO_DEBUG12 0x12 +#define ixDCIO_DEBUG13 0x13 +#define ixDCIO_DEBUG14 0x14 +#define ixDCIO_DEBUG15 0x15 +#define ixDCIO_DEBUG_ID 0x0 +#define mmDC_GPIO_GENERIC_MASK 0x1944 +#define mmDC_GPIO_GENERIC_A 0x1945 +#define mmDC_GPIO_GENERIC_EN 0x1946 +#define mmDC_GPIO_GENERIC_Y 0x1947 +#define mmDC_GPIO_DVODATA_MASK 0x1948 +#define mmDC_GPIO_DVODATA_A 0x1949 +#define mmDC_GPIO_DVODATA_EN 0x194a +#define mmDC_GPIO_DVODATA_Y 0x194b +#define mmDC_GPIO_DDC1_MASK 0x194c +#define mmDC_GPIO_DDC1_A 0x194d +#define mmDC_GPIO_DDC1_EN 0x194e +#define mmDC_GPIO_DDC1_Y 0x194f +#define mmDC_GPIO_DDC2_MASK 0x1950 +#define mmDC_GPIO_DDC2_A 0x1951 +#define mmDC_GPIO_DDC2_EN 0x1952 +#define mmDC_GPIO_DDC2_Y 0x1953 +#define mmDC_GPIO_DDC3_MASK 0x1954 +#define mmDC_GPIO_DDC3_A 0x1955 +#define mmDC_GPIO_DDC3_EN 0x1956 +#define mmDC_GPIO_DDC3_Y 0x1957 +#define mmDC_GPIO_DDC4_MASK 0x1958 +#define mmDC_GPIO_DDC4_A 0x1959 +#define mmDC_GPIO_DDC4_EN 0x195a +#define mmDC_GPIO_DDC4_Y 0x195b +#define mmDC_GPIO_DDC5_MASK 0x195c +#define mmDC_GPIO_DDC5_A 0x195d +#define mmDC_GPIO_DDC5_EN 0x195e +#define mmDC_GPIO_DDC5_Y 0x195f +#define mmDC_GPIO_DDC6_MASK 0x1960 +#define mmDC_GPIO_DDC6_A 0x1961 +#define mmDC_GPIO_DDC6_EN 0x1962 +#define mmDC_GPIO_DDC6_Y 0x1963 +#define mmDC_GPIO_DDCVGA_MASK 0x1970 +#define mmDC_GPIO_DDCVGA_A 0x1971 +#define mmDC_GPIO_DDCVGA_EN 0x1972 +#define mmDC_GPIO_DDCVGA_Y 0x1973 +#define mmDC_GPIO_SYNCA_MASK 0x1964 +#define mmDC_GPIO_SYNCA_A 0x1965 +#define mmDC_GPIO_SYNCA_EN 0x1966 +#define mmDC_GPIO_SYNCA_Y 0x1967 +#define mmDC_GPIO_GENLK_MASK 0x1968 +#define mmDC_GPIO_GENLK_A 0x1969 +#define mmDC_GPIO_GENLK_EN 0x196a +#define mmDC_GPIO_GENLK_Y 0x196b +#define mmDC_GPIO_HPD_MASK 0x196c +#define mmDC_GPIO_HPD_A 0x196d +#define mmDC_GPIO_HPD_EN 0x196e +#define mmDC_GPIO_HPD_Y 0x196f +#define mmDC_GPIO_PWRSEQ_MASK 0x1940 +#define mmDC_GPIO_PWRSEQ_A 0x1941 +#define mmDC_GPIO_PWRSEQ_EN 0x1942 +#define mmDC_GPIO_PWRSEQ_Y 0x1943 +#define mmDC_GPIO_PAD_STRENGTH_1 0x1978 +#define mmDC_GPIO_PAD_STRENGTH_2 0x1979 +#define mmPHY_AUX_CNTL 0x197f +#define mmDC_GPIO_I2CPAD_A 0x1975 +#define mmDC_GPIO_I2CPAD_EN 0x1976 +#define mmDC_GPIO_I2CPAD_Y 0x1977 +#define mmDC_GPIO_I2CPAD_STRENGTH 0x197a +#define mmDVO_STRENGTH_CONTROL 0x197b +#define mmDVO_VREF_CONTROL 0x197c +#define mmDVO_SKEW_ADJUST 0x197d +#define mmUNIPHYAB_TPG_CONTROL 0x1931 +#define mmUNIPHYAB_TPG_SEED 0x1932 +#define mmUNIPHYCD_TPG_CONTROL 0x1933 +#define mmUNIPHYCD_TPG_SEED 0x1934 +#define mmUNIPHYEF_TPG_CONTROL 0x1935 +#define mmUNIPHYEF_TPG_SEED 0x1936 +#define mmUNIPHYGH_TPG_CONTROL 0x1938 +#define mmUNIPHYGH_TPG_SEED 0x1939 +#define mmDC_GPIO_I2S_SPDIF_MASK 0x193c +#define mmDC_GPIO_I2S_SPDIF_A 0x193d +#define mmDC_GPIO_I2S_SPDIF_EN 0x193e +#define mmDC_GPIO_I2S_SPDIF_Y 0x193f +#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x193b +#define mmDAC_MACRO_CNTL_RESERVED0 0x19fc +#define mmDAC_MACRO_CNTL_RESERVED1 0x19fd +#define mmDAC_MACRO_CNTL_RESERVED2 0x19fe +#define mmDAC_MACRO_CNTL_RESERVED3 0x19ff +#define mmUNIPHY_TX_CONTROL1 0x1980 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19a0 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19b0 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19c0 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19d0 +#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1 0x4df0 +#define mmUNIPHY_TX_CONTROL2 0x1981 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19a1 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19b1 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19c1 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19d1 +#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2 0x4df1 +#define mmUNIPHY_TX_CONTROL3 0x1982 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19a2 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19b2 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19c2 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19d2 +#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3 0x4df2 +#define mmUNIPHY_TX_CONTROL4 0x1983 +#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983 +#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993 +#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19a3 +#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19b3 +#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19c3 +#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19d3 +#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4 0x4df3 +#define mmUNIPHY_POWER_CONTROL 0x1984 +#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984 +#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994 +#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19a4 +#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19b4 +#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19c4 +#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19d4 +#define mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL 0x4df4 +#define mmUNIPHY_PLL_FBDIV 0x1985 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19a5 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19b5 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19c5 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19d5 +#define mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV 0x4df5 +#define mmUNIPHY_PLL_CONTROL1 0x1986 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19a6 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19b6 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19c6 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19d6 +#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4df6 +#define mmUNIPHY_PLL_CONTROL2 0x1987 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19a7 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19b7 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19c7 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19d7 +#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4df7 +#define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19a8 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19b8 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19c8 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19d8 +#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4df8 +#define mmUNIPHY_PLL_SS_CNTL 0x1989 +#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989 +#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999 +#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19a9 +#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19b9 +#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19c9 +#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19d9 +#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4df9 +#define mmUNIPHY_DATA_SYNCHRONIZATION 0x198a +#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198a +#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199a +#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19aa +#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19ba +#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19ca +#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19da +#define mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x4dfa +#define mmUNIPHY_REG_TEST_OUTPUT 0x198b +#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198b +#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199b +#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19ab +#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19bb +#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19cb +#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19db +#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x4dfb +#define mmUNIPHY_ANG_BIST_CNTL 0x198c +#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198c +#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199c +#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19ac +#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19bc +#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19cc +#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19dc +#define mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x4dfc +#define mmUNIPHY_LINK_CNTL 0x198d +#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198d +#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199d +#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19ad +#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19bd +#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19cd +#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19dd +#define mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL 0x4dfd +#define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198e +#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198e +#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199e +#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19ae +#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19be +#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19ce +#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19de +#define mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL 0x4dfe +#define mmUNIPHY_REG_TEST_OUTPUT2 0x198f +#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x198f +#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x199f +#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x19af +#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x19bf +#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x19cf +#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x19df +#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x4dff +#define mmGRPH_ENABLE 0x1a00 +#define mmDCP0_GRPH_ENABLE 0x1a00 +#define mmDCP1_GRPH_ENABLE 0x1d00 +#define mmDCP2_GRPH_ENABLE 0x4000 +#define mmDCP3_GRPH_ENABLE 0x4300 +#define mmDCP4_GRPH_ENABLE 0x4600 +#define mmDCP5_GRPH_ENABLE 0x4900 +#define mmGRPH_CONTROL 0x1a01 +#define mmDCP0_GRPH_CONTROL 0x1a01 +#define mmDCP1_GRPH_CONTROL 0x1d01 +#define mmDCP2_GRPH_CONTROL 0x4001 +#define mmDCP3_GRPH_CONTROL 0x4301 +#define mmDCP4_GRPH_CONTROL 0x4601 +#define mmDCP5_GRPH_CONTROL 0x4901 +#define mmGRPH_LUT_10BIT_BYPASS 0x1a02 +#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 +#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1d02 +#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002 +#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302 +#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602 +#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902 +#define mmGRPH_SWAP_CNTL 0x1a03 +#define mmDCP0_GRPH_SWAP_CNTL 0x1a03 +#define mmDCP1_GRPH_SWAP_CNTL 0x1d03 +#define mmDCP2_GRPH_SWAP_CNTL 0x4003 +#define mmDCP3_GRPH_SWAP_CNTL 0x4303 +#define mmDCP4_GRPH_SWAP_CNTL 0x4603 +#define mmDCP5_GRPH_SWAP_CNTL 0x4903 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1d04 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1d05 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905 +#define mmGRPH_PITCH 0x1a06 +#define mmDCP0_GRPH_PITCH 0x1a06 +#define mmDCP1_GRPH_PITCH 0x1d06 +#define mmDCP2_GRPH_PITCH 0x4006 +#define mmDCP3_GRPH_PITCH 0x4306 +#define mmDCP4_GRPH_PITCH 0x4606 +#define mmDCP5_GRPH_PITCH 0x4906 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1d07 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d08 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908 +#define mmGRPH_SURFACE_OFFSET_X 0x1a09 +#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 +#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1d09 +#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009 +#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309 +#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609 +#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909 +#define mmGRPH_SURFACE_OFFSET_Y 0x1a0a +#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a +#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1d0a +#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400a +#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430a +#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460a +#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490a +#define mmGRPH_X_START 0x1a0b +#define mmDCP0_GRPH_X_START 0x1a0b +#define mmDCP1_GRPH_X_START 0x1d0b +#define mmDCP2_GRPH_X_START 0x400b +#define mmDCP3_GRPH_X_START 0x430b +#define mmDCP4_GRPH_X_START 0x460b +#define mmDCP5_GRPH_X_START 0x490b +#define mmGRPH_Y_START 0x1a0c +#define mmDCP0_GRPH_Y_START 0x1a0c +#define mmDCP1_GRPH_Y_START 0x1d0c +#define mmDCP2_GRPH_Y_START 0x400c +#define mmDCP3_GRPH_Y_START 0x430c +#define mmDCP4_GRPH_Y_START 0x460c +#define mmDCP5_GRPH_Y_START 0x490c +#define mmGRPH_X_END 0x1a0d +#define mmDCP0_GRPH_X_END 0x1a0d +#define mmDCP1_GRPH_X_END 0x1d0d +#define mmDCP2_GRPH_X_END 0x400d +#define mmDCP3_GRPH_X_END 0x430d +#define mmDCP4_GRPH_X_END 0x460d +#define mmDCP5_GRPH_X_END 0x490d +#define mmGRPH_Y_END 0x1a0e +#define mmDCP0_GRPH_Y_END 0x1a0e +#define mmDCP1_GRPH_Y_END 0x1d0e +#define mmDCP2_GRPH_Y_END 0x400e +#define mmDCP3_GRPH_Y_END 0x430e +#define mmDCP4_GRPH_Y_END 0x460e +#define mmDCP5_GRPH_Y_END 0x490e +#define mmINPUT_GAMMA_CONTROL 0x1a10 +#define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 +#define mmDCP1_INPUT_GAMMA_CONTROL 0x1d10 +#define mmDCP2_INPUT_GAMMA_CONTROL 0x4010 +#define mmDCP3_INPUT_GAMMA_CONTROL 0x4310 +#define mmDCP4_INPUT_GAMMA_CONTROL 0x4610 +#define mmDCP5_INPUT_GAMMA_CONTROL 0x4910 +#define mmGRPH_UPDATE 0x1a11 +#define mmDCP0_GRPH_UPDATE 0x1a11 +#define mmDCP1_GRPH_UPDATE 0x1d11 +#define mmDCP2_GRPH_UPDATE 0x4011 +#define mmDCP3_GRPH_UPDATE 0x4311 +#define mmDCP4_GRPH_UPDATE 0x4611 +#define mmDCP5_GRPH_UPDATE 0x4911 +#define mmGRPH_FLIP_CONTROL 0x1a12 +#define mmDCP0_GRPH_FLIP_CONTROL 0x1a12 +#define mmDCP1_GRPH_FLIP_CONTROL 0x1d12 +#define mmDCP2_GRPH_FLIP_CONTROL 0x4012 +#define mmDCP3_GRPH_FLIP_CONTROL 0x4312 +#define mmDCP4_GRPH_FLIP_CONTROL 0x4612 +#define mmDCP5_GRPH_FLIP_CONTROL 0x4912 +#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1d13 +#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013 +#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313 +#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613 +#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913 +#define mmGRPH_DFQ_CONTROL 0x1a14 +#define mmDCP0_GRPH_DFQ_CONTROL 0x1a14 +#define mmDCP1_GRPH_DFQ_CONTROL 0x1d14 +#define mmDCP2_GRPH_DFQ_CONTROL 0x4014 +#define mmDCP3_GRPH_DFQ_CONTROL 0x4314 +#define mmDCP4_GRPH_DFQ_CONTROL 0x4614 +#define mmDCP5_GRPH_DFQ_CONTROL 0x4914 +#define mmGRPH_DFQ_STATUS 0x1a15 +#define mmDCP0_GRPH_DFQ_STATUS 0x1a15 +#define mmDCP1_GRPH_DFQ_STATUS 0x1d15 +#define mmDCP2_GRPH_DFQ_STATUS 0x4015 +#define mmDCP3_GRPH_DFQ_STATUS 0x4315 +#define mmDCP4_GRPH_DFQ_STATUS 0x4615 +#define mmDCP5_GRPH_DFQ_STATUS 0x4915 +#define mmGRPH_INTERRUPT_STATUS 0x1a16 +#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 +#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1d16 +#define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016 +#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316 +#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616 +#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916 +#define mmGRPH_INTERRUPT_CONTROL 0x1a17 +#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 +#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1d17 +#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017 +#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317 +#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617 +#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917 +#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1d18 +#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 +#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318 +#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618 +#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918 +#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1d19 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919 +#define mmGRPH_COMPRESS_PITCH 0x1a1a +#define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a +#define mmDCP1_GRPH_COMPRESS_PITCH 0x1d1a +#define mmDCP2_GRPH_COMPRESS_PITCH 0x401a +#define mmDCP3_GRPH_COMPRESS_PITCH 0x431a +#define mmDCP4_GRPH_COMPRESS_PITCH 0x461a +#define mmDCP5_GRPH_COMPRESS_PITCH 0x491a +#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1d1b +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431b +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461b +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491b +#define mmOVL_ENABLE 0x1a1c +#define mmDCP0_OVL_ENABLE 0x1a1c +#define mmDCP1_OVL_ENABLE 0x1d1c +#define mmDCP2_OVL_ENABLE 0x401c +#define mmDCP3_OVL_ENABLE 0x431c +#define mmDCP4_OVL_ENABLE 0x461c +#define mmDCP5_OVL_ENABLE 0x491c +#define mmOVL_CONTROL1 0x1a1d +#define mmDCP0_OVL_CONTROL1 0x1a1d +#define mmDCP1_OVL_CONTROL1 0x1d1d +#define mmDCP2_OVL_CONTROL1 0x401d +#define mmDCP3_OVL_CONTROL1 0x431d +#define mmDCP4_OVL_CONTROL1 0x461d +#define mmDCP5_OVL_CONTROL1 0x491d +#define mmOVL_CONTROL2 0x1a1e +#define mmDCP0_OVL_CONTROL2 0x1a1e +#define mmDCP1_OVL_CONTROL2 0x1d1e +#define mmDCP2_OVL_CONTROL2 0x401e +#define mmDCP3_OVL_CONTROL2 0x431e +#define mmDCP4_OVL_CONTROL2 0x461e +#define mmDCP5_OVL_CONTROL2 0x491e +#define mmOVL_SWAP_CNTL 0x1a1f +#define mmDCP0_OVL_SWAP_CNTL 0x1a1f +#define mmDCP1_OVL_SWAP_CNTL 0x1d1f +#define mmDCP2_OVL_SWAP_CNTL 0x401f +#define mmDCP3_OVL_SWAP_CNTL 0x431f +#define mmDCP4_OVL_SWAP_CNTL 0x461f +#define mmDCP5_OVL_SWAP_CNTL 0x491f +#define mmOVL_SURFACE_ADDRESS 0x1a20 +#define mmDCP0_OVL_SURFACE_ADDRESS 0x1a20 +#define mmDCP1_OVL_SURFACE_ADDRESS 0x1d20 +#define mmDCP2_OVL_SURFACE_ADDRESS 0x4020 +#define mmDCP3_OVL_SURFACE_ADDRESS 0x4320 +#define mmDCP4_OVL_SURFACE_ADDRESS 0x4620 +#define mmDCP5_OVL_SURFACE_ADDRESS 0x4920 +#define mmOVL_PITCH 0x1a21 +#define mmDCP0_OVL_PITCH 0x1a21 +#define mmDCP1_OVL_PITCH 0x1d21 +#define mmDCP2_OVL_PITCH 0x4021 +#define mmDCP3_OVL_PITCH 0x4321 +#define mmDCP4_OVL_PITCH 0x4621 +#define mmDCP5_OVL_PITCH 0x4921 +#define mmOVL_SURFACE_ADDRESS_HIGH 0x1a22 +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22 +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1d22 +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022 +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322 +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622 +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922 +#define mmOVL_SURFACE_OFFSET_X 0x1a23 +#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23 +#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1d23 +#define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023 +#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323 +#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623 +#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923 +#define mmOVL_SURFACE_OFFSET_Y 0x1a24 +#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24 +#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1d24 +#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024 +#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324 +#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624 +#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924 +#define mmOVL_START 0x1a25 +#define mmDCP0_OVL_START 0x1a25 +#define mmDCP1_OVL_START 0x1d25 +#define mmDCP2_OVL_START 0x4025 +#define mmDCP3_OVL_START 0x4325 +#define mmDCP4_OVL_START 0x4625 +#define mmDCP5_OVL_START 0x4925 +#define mmOVL_END 0x1a26 +#define mmDCP0_OVL_END 0x1a26 +#define mmDCP1_OVL_END 0x1d26 +#define mmDCP2_OVL_END 0x4026 +#define mmDCP3_OVL_END 0x4326 +#define mmDCP4_OVL_END 0x4626 +#define mmDCP5_OVL_END 0x4926 +#define mmOVL_UPDATE 0x1a27 +#define mmDCP0_OVL_UPDATE 0x1a27 +#define mmDCP1_OVL_UPDATE 0x1d27 +#define mmDCP2_OVL_UPDATE 0x4027 +#define mmDCP3_OVL_UPDATE 0x4327 +#define mmDCP4_OVL_UPDATE 0x4627 +#define mmDCP5_OVL_UPDATE 0x4927 +#define mmOVL_SURFACE_ADDRESS_INUSE 0x1a28 +#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28 +#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1d28 +#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028 +#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328 +#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628 +#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928 +#define mmOVL_DFQ_CONTROL 0x1a29 +#define mmDCP0_OVL_DFQ_CONTROL 0x1a29 +#define mmDCP1_OVL_DFQ_CONTROL 0x1d29 +#define mmDCP2_OVL_DFQ_CONTROL 0x4029 +#define mmDCP3_OVL_DFQ_CONTROL 0x4329 +#define mmDCP4_OVL_DFQ_CONTROL 0x4629 +#define mmDCP5_OVL_DFQ_CONTROL 0x4929 +#define mmOVL_DFQ_STATUS 0x1a2a +#define mmDCP0_OVL_DFQ_STATUS 0x1a2a +#define mmDCP1_OVL_DFQ_STATUS 0x1d2a +#define mmDCP2_OVL_DFQ_STATUS 0x402a +#define mmDCP3_OVL_DFQ_STATUS 0x432a +#define mmDCP4_OVL_DFQ_STATUS 0x462a +#define mmDCP5_OVL_DFQ_STATUS 0x492a +#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1d2b +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432b +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462b +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492b +#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c +#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c +#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1d2c +#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402c +#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432c +#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462c +#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492c +#define mmPRESCALE_GRPH_CONTROL 0x1a2d +#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d +#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1d2d +#define mmDCP2_PRESCALE_GRPH_CONTROL 0x402d +#define mmDCP3_PRESCALE_GRPH_CONTROL 0x432d +#define mmDCP4_PRESCALE_GRPH_CONTROL 0x462d +#define mmDCP5_PRESCALE_GRPH_CONTROL 0x492d +#define mmPRESCALE_VALUES_GRPH_R 0x1a2e +#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e +#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1d2e +#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402e +#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432e +#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462e +#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492e +#define mmPRESCALE_VALUES_GRPH_G 0x1a2f +#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f +#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1d2f +#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402f +#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432f +#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462f +#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492f +#define mmPRESCALE_VALUES_GRPH_B 0x1a30 +#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 +#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1d30 +#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030 +#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330 +#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630 +#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930 +#define mmPRESCALE_OVL_CONTROL 0x1a31 +#define mmDCP0_PRESCALE_OVL_CONTROL 0x1a31 +#define mmDCP1_PRESCALE_OVL_CONTROL 0x1d31 +#define mmDCP2_PRESCALE_OVL_CONTROL 0x4031 +#define mmDCP3_PRESCALE_OVL_CONTROL 0x4331 +#define mmDCP4_PRESCALE_OVL_CONTROL 0x4631 +#define mmDCP5_PRESCALE_OVL_CONTROL 0x4931 +#define mmPRESCALE_VALUES_OVL_CB 0x1a32 +#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32 +#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1d32 +#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032 +#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332 +#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632 +#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932 +#define mmPRESCALE_VALUES_OVL_Y 0x1a33 +#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33 +#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1d33 +#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033 +#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333 +#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633 +#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933 +#define mmPRESCALE_VALUES_OVL_CR 0x1a34 +#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34 +#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1d34 +#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034 +#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334 +#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634 +#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934 +#define mmINPUT_CSC_CONTROL 0x1a35 +#define mmDCP0_INPUT_CSC_CONTROL 0x1a35 +#define mmDCP1_INPUT_CSC_CONTROL 0x1d35 +#define mmDCP2_INPUT_CSC_CONTROL 0x4035 +#define mmDCP3_INPUT_CSC_CONTROL 0x4335 +#define mmDCP4_INPUT_CSC_CONTROL 0x4635 +#define mmDCP5_INPUT_CSC_CONTROL 0x4935 +#define mmINPUT_CSC_C11_C12 0x1a36 +#define mmDCP0_INPUT_CSC_C11_C12 0x1a36 +#define mmDCP1_INPUT_CSC_C11_C12 0x1d36 +#define mmDCP2_INPUT_CSC_C11_C12 0x4036 +#define mmDCP3_INPUT_CSC_C11_C12 0x4336 +#define mmDCP4_INPUT_CSC_C11_C12 0x4636 +#define mmDCP5_INPUT_CSC_C11_C12 0x4936 +#define mmINPUT_CSC_C13_C14 0x1a37 +#define mmDCP0_INPUT_CSC_C13_C14 0x1a37 +#define mmDCP1_INPUT_CSC_C13_C14 0x1d37 +#define mmDCP2_INPUT_CSC_C13_C14 0x4037 +#define mmDCP3_INPUT_CSC_C13_C14 0x4337 +#define mmDCP4_INPUT_CSC_C13_C14 0x4637 +#define mmDCP5_INPUT_CSC_C13_C14 0x4937 +#define mmINPUT_CSC_C21_C22 0x1a38 +#define mmDCP0_INPUT_CSC_C21_C22 0x1a38 +#define mmDCP1_INPUT_CSC_C21_C22 0x1d38 +#define mmDCP2_INPUT_CSC_C21_C22 0x4038 +#define mmDCP3_INPUT_CSC_C21_C22 0x4338 +#define mmDCP4_INPUT_CSC_C21_C22 0x4638 +#define mmDCP5_INPUT_CSC_C21_C22 0x4938 +#define mmINPUT_CSC_C23_C24 0x1a39 +#define mmDCP0_INPUT_CSC_C23_C24 0x1a39 +#define mmDCP1_INPUT_CSC_C23_C24 0x1d39 +#define mmDCP2_INPUT_CSC_C23_C24 0x4039 +#define mmDCP3_INPUT_CSC_C23_C24 0x4339 +#define mmDCP4_INPUT_CSC_C23_C24 0x4639 +#define mmDCP5_INPUT_CSC_C23_C24 0x4939 +#define mmINPUT_CSC_C31_C32 0x1a3a +#define mmDCP0_INPUT_CSC_C31_C32 0x1a3a +#define mmDCP1_INPUT_CSC_C31_C32 0x1d3a +#define mmDCP2_INPUT_CSC_C31_C32 0x403a +#define mmDCP3_INPUT_CSC_C31_C32 0x433a +#define mmDCP4_INPUT_CSC_C31_C32 0x463a +#define mmDCP5_INPUT_CSC_C31_C32 0x493a +#define mmINPUT_CSC_C33_C34 0x1a3b +#define mmDCP0_INPUT_CSC_C33_C34 0x1a3b +#define mmDCP1_INPUT_CSC_C33_C34 0x1d3b +#define mmDCP2_INPUT_CSC_C33_C34 0x403b +#define mmDCP3_INPUT_CSC_C33_C34 0x433b +#define mmDCP4_INPUT_CSC_C33_C34 0x463b +#define mmDCP5_INPUT_CSC_C33_C34 0x493b +#define mmOUTPUT_CSC_CONTROL 0x1a3c +#define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c +#define mmDCP1_OUTPUT_CSC_CONTROL 0x1d3c +#define mmDCP2_OUTPUT_CSC_CONTROL 0x403c +#define mmDCP3_OUTPUT_CSC_CONTROL 0x433c +#define mmDCP4_OUTPUT_CSC_CONTROL 0x463c +#define mmDCP5_OUTPUT_CSC_CONTROL 0x493c +#define mmOUTPUT_CSC_C11_C12 0x1a3d +#define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d +#define mmDCP1_OUTPUT_CSC_C11_C12 0x1d3d +#define mmDCP2_OUTPUT_CSC_C11_C12 0x403d +#define mmDCP3_OUTPUT_CSC_C11_C12 0x433d +#define mmDCP4_OUTPUT_CSC_C11_C12 0x463d +#define mmDCP5_OUTPUT_CSC_C11_C12 0x493d +#define mmOUTPUT_CSC_C13_C14 0x1a3e +#define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e +#define mmDCP1_OUTPUT_CSC_C13_C14 0x1d3e +#define mmDCP2_OUTPUT_CSC_C13_C14 0x403e +#define mmDCP3_OUTPUT_CSC_C13_C14 0x433e +#define mmDCP4_OUTPUT_CSC_C13_C14 0x463e +#define mmDCP5_OUTPUT_CSC_C13_C14 0x493e +#define mmOUTPUT_CSC_C21_C22 0x1a3f +#define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f +#define mmDCP1_OUTPUT_CSC_C21_C22 0x1d3f +#define mmDCP2_OUTPUT_CSC_C21_C22 0x403f +#define mmDCP3_OUTPUT_CSC_C21_C22 0x433f +#define mmDCP4_OUTPUT_CSC_C21_C22 0x463f +#define mmDCP5_OUTPUT_CSC_C21_C22 0x493f +#define mmOUTPUT_CSC_C23_C24 0x1a40 +#define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 +#define mmDCP1_OUTPUT_CSC_C23_C24 0x1d40 +#define mmDCP2_OUTPUT_CSC_C23_C24 0x4040 +#define mmDCP3_OUTPUT_CSC_C23_C24 0x4340 +#define mmDCP4_OUTPUT_CSC_C23_C24 0x4640 +#define mmDCP5_OUTPUT_CSC_C23_C24 0x4940 +#define mmOUTPUT_CSC_C31_C32 0x1a41 +#define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 +#define mmDCP1_OUTPUT_CSC_C31_C32 0x1d41 +#define mmDCP2_OUTPUT_CSC_C31_C32 0x4041 +#define mmDCP3_OUTPUT_CSC_C31_C32 0x4341 +#define mmDCP4_OUTPUT_CSC_C31_C32 0x4641 +#define mmDCP5_OUTPUT_CSC_C31_C32 0x4941 +#define mmOUTPUT_CSC_C33_C34 0x1a42 +#define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 +#define mmDCP1_OUTPUT_CSC_C33_C34 0x1d42 +#define mmDCP2_OUTPUT_CSC_C33_C34 0x4042 +#define mmDCP3_OUTPUT_CSC_C33_C34 0x4342 +#define mmDCP4_OUTPUT_CSC_C33_C34 0x4642 +#define mmDCP5_OUTPUT_CSC_C33_C34 0x4942 +#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1d43 +#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043 +#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343 +#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643 +#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943 +#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1d44 +#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044 +#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344 +#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644 +#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944 +#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1d45 +#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045 +#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345 +#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645 +#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945 +#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1d46 +#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046 +#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346 +#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646 +#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946 +#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1d47 +#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047 +#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347 +#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647 +#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947 +#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1d48 +#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048 +#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348 +#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648 +#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948 +#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1d49 +#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049 +#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349 +#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649 +#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949 +#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1d4a +#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404a +#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434a +#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464a +#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494a +#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1d4b +#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404b +#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434b +#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464b +#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494b +#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1d4c +#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404c +#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434c +#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464c +#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494c +#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1d4d +#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404d +#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434d +#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464d +#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494d +#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1d4e +#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404e +#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434e +#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464e +#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494e +#define mmDENORM_CONTROL 0x1a50 +#define mmDCP0_DENORM_CONTROL 0x1a50 +#define mmDCP1_DENORM_CONTROL 0x1d50 +#define mmDCP2_DENORM_CONTROL 0x4050 +#define mmDCP3_DENORM_CONTROL 0x4350 +#define mmDCP4_DENORM_CONTROL 0x4650 +#define mmDCP5_DENORM_CONTROL 0x4950 +#define mmOUT_ROUND_CONTROL 0x1a51 +#define mmDCP0_OUT_ROUND_CONTROL 0x1a51 +#define mmDCP1_OUT_ROUND_CONTROL 0x1d51 +#define mmDCP2_OUT_ROUND_CONTROL 0x4051 +#define mmDCP3_OUT_ROUND_CONTROL 0x4351 +#define mmDCP4_OUT_ROUND_CONTROL 0x4651 +#define mmDCP5_OUT_ROUND_CONTROL 0x4951 +#define mmOUT_CLAMP_CONTROL_R_CR 0x1a52 +#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 +#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1d52 +#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x4052 +#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4352 +#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4652 +#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4952 +#define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c +#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c +#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1d9c +#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x409c +#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x439c +#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x469c +#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x499c +#define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d +#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d +#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1d9d +#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x409d +#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x439d +#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x469d +#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x499d +#define mmKEY_CONTROL 0x1a53 +#define mmDCP0_KEY_CONTROL 0x1a53 +#define mmDCP1_KEY_CONTROL 0x1d53 +#define mmDCP2_KEY_CONTROL 0x4053 +#define mmDCP3_KEY_CONTROL 0x4353 +#define mmDCP4_KEY_CONTROL 0x4653 +#define mmDCP5_KEY_CONTROL 0x4953 +#define mmKEY_RANGE_ALPHA 0x1a54 +#define mmDCP0_KEY_RANGE_ALPHA 0x1a54 +#define mmDCP1_KEY_RANGE_ALPHA 0x1d54 +#define mmDCP2_KEY_RANGE_ALPHA 0x4054 +#define mmDCP3_KEY_RANGE_ALPHA 0x4354 +#define mmDCP4_KEY_RANGE_ALPHA 0x4654 +#define mmDCP5_KEY_RANGE_ALPHA 0x4954 +#define mmKEY_RANGE_RED 0x1a55 +#define mmDCP0_KEY_RANGE_RED 0x1a55 +#define mmDCP1_KEY_RANGE_RED 0x1d55 +#define mmDCP2_KEY_RANGE_RED 0x4055 +#define mmDCP3_KEY_RANGE_RED 0x4355 +#define mmDCP4_KEY_RANGE_RED 0x4655 +#define mmDCP5_KEY_RANGE_RED 0x4955 +#define mmKEY_RANGE_GREEN 0x1a56 +#define mmDCP0_KEY_RANGE_GREEN 0x1a56 +#define mmDCP1_KEY_RANGE_GREEN 0x1d56 +#define mmDCP2_KEY_RANGE_GREEN 0x4056 +#define mmDCP3_KEY_RANGE_GREEN 0x4356 +#define mmDCP4_KEY_RANGE_GREEN 0x4656 +#define mmDCP5_KEY_RANGE_GREEN 0x4956 +#define mmKEY_RANGE_BLUE 0x1a57 +#define mmDCP0_KEY_RANGE_BLUE 0x1a57 +#define mmDCP1_KEY_RANGE_BLUE 0x1d57 +#define mmDCP2_KEY_RANGE_BLUE 0x4057 +#define mmDCP3_KEY_RANGE_BLUE 0x4357 +#define mmDCP4_KEY_RANGE_BLUE 0x4657 +#define mmDCP5_KEY_RANGE_BLUE 0x4957 +#define mmDEGAMMA_CONTROL 0x1a58 +#define mmDCP0_DEGAMMA_CONTROL 0x1a58 +#define mmDCP1_DEGAMMA_CONTROL 0x1d58 +#define mmDCP2_DEGAMMA_CONTROL 0x4058 +#define mmDCP3_DEGAMMA_CONTROL 0x4358 +#define mmDCP4_DEGAMMA_CONTROL 0x4658 +#define mmDCP5_DEGAMMA_CONTROL 0x4958 +#define mmGAMUT_REMAP_CONTROL 0x1a59 +#define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 +#define mmDCP1_GAMUT_REMAP_CONTROL 0x1d59 +#define mmDCP2_GAMUT_REMAP_CONTROL 0x4059 +#define mmDCP3_GAMUT_REMAP_CONTROL 0x4359 +#define mmDCP4_GAMUT_REMAP_CONTROL 0x4659 +#define mmDCP5_GAMUT_REMAP_CONTROL 0x4959 +#define mmGAMUT_REMAP_C11_C12 0x1a5a +#define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a +#define mmDCP1_GAMUT_REMAP_C11_C12 0x1d5a +#define mmDCP2_GAMUT_REMAP_C11_C12 0x405a +#define mmDCP3_GAMUT_REMAP_C11_C12 0x435a +#define mmDCP4_GAMUT_REMAP_C11_C12 0x465a +#define mmDCP5_GAMUT_REMAP_C11_C12 0x495a +#define mmGAMUT_REMAP_C13_C14 0x1a5b +#define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b +#define mmDCP1_GAMUT_REMAP_C13_C14 0x1d5b +#define mmDCP2_GAMUT_REMAP_C13_C14 0x405b +#define mmDCP3_GAMUT_REMAP_C13_C14 0x435b +#define mmDCP4_GAMUT_REMAP_C13_C14 0x465b +#define mmDCP5_GAMUT_REMAP_C13_C14 0x495b +#define mmGAMUT_REMAP_C21_C22 0x1a5c +#define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c +#define mmDCP1_GAMUT_REMAP_C21_C22 0x1d5c +#define mmDCP2_GAMUT_REMAP_C21_C22 0x405c +#define mmDCP3_GAMUT_REMAP_C21_C22 0x435c +#define mmDCP4_GAMUT_REMAP_C21_C22 0x465c +#define mmDCP5_GAMUT_REMAP_C21_C22 0x495c +#define mmGAMUT_REMAP_C23_C24 0x1a5d +#define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d +#define mmDCP1_GAMUT_REMAP_C23_C24 0x1d5d +#define mmDCP2_GAMUT_REMAP_C23_C24 0x405d +#define mmDCP3_GAMUT_REMAP_C23_C24 0x435d +#define mmDCP4_GAMUT_REMAP_C23_C24 0x465d +#define mmDCP5_GAMUT_REMAP_C23_C24 0x495d +#define mmGAMUT_REMAP_C31_C32 0x1a5e +#define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e +#define mmDCP1_GAMUT_REMAP_C31_C32 0x1d5e +#define mmDCP2_GAMUT_REMAP_C31_C32 0x405e +#define mmDCP3_GAMUT_REMAP_C31_C32 0x435e +#define mmDCP4_GAMUT_REMAP_C31_C32 0x465e +#define mmDCP5_GAMUT_REMAP_C31_C32 0x495e +#define mmGAMUT_REMAP_C33_C34 0x1a5f +#define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f +#define mmDCP1_GAMUT_REMAP_C33_C34 0x1d5f +#define mmDCP2_GAMUT_REMAP_C33_C34 0x405f +#define mmDCP3_GAMUT_REMAP_C33_C34 0x435f +#define mmDCP4_GAMUT_REMAP_C33_C34 0x465f +#define mmDCP5_GAMUT_REMAP_C33_C34 0x495f +#define mmDCP_SPATIAL_DITHER_CNTL 0x1a60 +#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 +#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1d60 +#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060 +#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360 +#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660 +#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960 +#define mmDCP_RANDOM_SEEDS 0x1a61 +#define mmDCP0_DCP_RANDOM_SEEDS 0x1a61 +#define mmDCP1_DCP_RANDOM_SEEDS 0x1d61 +#define mmDCP2_DCP_RANDOM_SEEDS 0x4061 +#define mmDCP3_DCP_RANDOM_SEEDS 0x4361 +#define mmDCP4_DCP_RANDOM_SEEDS 0x4661 +#define mmDCP5_DCP_RANDOM_SEEDS 0x4961 +#define mmDCP_FP_CONVERTED_FIELD 0x1a65 +#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 +#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1d65 +#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065 +#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365 +#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665 +#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965 +#define mmCUR_CONTROL 0x1a66 +#define mmDCP0_CUR_CONTROL 0x1a66 +#define mmDCP1_CUR_CONTROL 0x1d66 +#define mmDCP2_CUR_CONTROL 0x4066 +#define mmDCP3_CUR_CONTROL 0x4366 +#define mmDCP4_CUR_CONTROL 0x4666 +#define mmDCP5_CUR_CONTROL 0x4966 +#define mmCUR_SURFACE_ADDRESS 0x1a67 +#define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 +#define mmDCP1_CUR_SURFACE_ADDRESS 0x1d67 +#define mmDCP2_CUR_SURFACE_ADDRESS 0x4067 +#define mmDCP3_CUR_SURFACE_ADDRESS 0x4367 +#define mmDCP4_CUR_SURFACE_ADDRESS 0x4667 +#define mmDCP5_CUR_SURFACE_ADDRESS 0x4967 +#define mmCUR_SIZE 0x1a68 +#define mmDCP0_CUR_SIZE 0x1a68 +#define mmDCP1_CUR_SIZE 0x1d68 +#define mmDCP2_CUR_SIZE 0x4068 +#define mmDCP3_CUR_SIZE 0x4368 +#define mmDCP4_CUR_SIZE 0x4668 +#define mmDCP5_CUR_SIZE 0x4968 +#define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1d69 +#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069 +#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369 +#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669 +#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969 +#define mmCUR_POSITION 0x1a6a +#define mmDCP0_CUR_POSITION 0x1a6a +#define mmDCP1_CUR_POSITION 0x1d6a +#define mmDCP2_CUR_POSITION 0x406a +#define mmDCP3_CUR_POSITION 0x436a +#define mmDCP4_CUR_POSITION 0x466a +#define mmDCP5_CUR_POSITION 0x496a +#define mmCUR_HOT_SPOT 0x1a6b +#define mmDCP0_CUR_HOT_SPOT 0x1a6b +#define mmDCP1_CUR_HOT_SPOT 0x1d6b +#define mmDCP2_CUR_HOT_SPOT 0x406b +#define mmDCP3_CUR_HOT_SPOT 0x436b +#define mmDCP4_CUR_HOT_SPOT 0x466b +#define mmDCP5_CUR_HOT_SPOT 0x496b +#define mmCUR_COLOR1 0x1a6c +#define mmDCP0_CUR_COLOR1 0x1a6c +#define mmDCP1_CUR_COLOR1 0x1d6c +#define mmDCP2_CUR_COLOR1 0x406c +#define mmDCP3_CUR_COLOR1 0x436c +#define mmDCP4_CUR_COLOR1 0x466c +#define mmDCP5_CUR_COLOR1 0x496c +#define mmCUR_COLOR2 0x1a6d +#define mmDCP0_CUR_COLOR2 0x1a6d +#define mmDCP1_CUR_COLOR2 0x1d6d +#define mmDCP2_CUR_COLOR2 0x406d +#define mmDCP3_CUR_COLOR2 0x436d +#define mmDCP4_CUR_COLOR2 0x466d +#define mmDCP5_CUR_COLOR2 0x496d +#define mmCUR_UPDATE 0x1a6e +#define mmDCP0_CUR_UPDATE 0x1a6e +#define mmDCP1_CUR_UPDATE 0x1d6e +#define mmDCP2_CUR_UPDATE 0x406e +#define mmDCP3_CUR_UPDATE 0x436e +#define mmDCP4_CUR_UPDATE 0x466e +#define mmDCP5_CUR_UPDATE 0x496e +#define mmCUR2_CONTROL 0x1a6f +#define mmDCP0_CUR2_CONTROL 0x1a6f +#define mmDCP1_CUR2_CONTROL 0x1d6f +#define mmDCP2_CUR2_CONTROL 0x406f +#define mmDCP3_CUR2_CONTROL 0x436f +#define mmDCP4_CUR2_CONTROL 0x466f +#define mmDCP5_CUR2_CONTROL 0x496f +#define mmCUR2_SURFACE_ADDRESS 0x1a70 +#define mmDCP0_CUR2_SURFACE_ADDRESS 0x1a70 +#define mmDCP1_CUR2_SURFACE_ADDRESS 0x1d70 +#define mmDCP2_CUR2_SURFACE_ADDRESS 0x4070 +#define mmDCP3_CUR2_SURFACE_ADDRESS 0x4370 +#define mmDCP4_CUR2_SURFACE_ADDRESS 0x4670 +#define mmDCP5_CUR2_SURFACE_ADDRESS 0x4970 +#define mmCUR2_SIZE 0x1a71 +#define mmDCP0_CUR2_SIZE 0x1a71 +#define mmDCP1_CUR2_SIZE 0x1d71 +#define mmDCP2_CUR2_SIZE 0x4071 +#define mmDCP3_CUR2_SIZE 0x4371 +#define mmDCP4_CUR2_SIZE 0x4671 +#define mmDCP5_CUR2_SIZE 0x4971 +#define mmCUR2_SURFACE_ADDRESS_HIGH 0x1a72 +#define mmDCP0_CUR2_SURFACE_ADDRESS_HIGH 0x1a72 +#define mmDCP1_CUR2_SURFACE_ADDRESS_HIGH 0x1d72 +#define mmDCP2_CUR2_SURFACE_ADDRESS_HIGH 0x4072 +#define mmDCP3_CUR2_SURFACE_ADDRESS_HIGH 0x4372 +#define mmDCP4_CUR2_SURFACE_ADDRESS_HIGH 0x4672 +#define mmDCP5_CUR2_SURFACE_ADDRESS_HIGH 0x4972 +#define mmCUR2_POSITION 0x1a73 +#define mmDCP0_CUR2_POSITION 0x1a73 +#define mmDCP1_CUR2_POSITION 0x1d73 +#define mmDCP2_CUR2_POSITION 0x4073 +#define mmDCP3_CUR2_POSITION 0x4373 +#define mmDCP4_CUR2_POSITION 0x4673 +#define mmDCP5_CUR2_POSITION 0x4973 +#define mmCUR2_HOT_SPOT 0x1a74 +#define mmDCP0_CUR2_HOT_SPOT 0x1a74 +#define mmDCP1_CUR2_HOT_SPOT 0x1d74 +#define mmDCP2_CUR2_HOT_SPOT 0x4074 +#define mmDCP3_CUR2_HOT_SPOT 0x4374 +#define mmDCP4_CUR2_HOT_SPOT 0x4674 +#define mmDCP5_CUR2_HOT_SPOT 0x4974 +#define mmCUR2_COLOR1 0x1a75 +#define mmDCP0_CUR2_COLOR1 0x1a75 +#define mmDCP1_CUR2_COLOR1 0x1d75 +#define mmDCP2_CUR2_COLOR1 0x4075 +#define mmDCP3_CUR2_COLOR1 0x4375 +#define mmDCP4_CUR2_COLOR1 0x4675 +#define mmDCP5_CUR2_COLOR1 0x4975 +#define mmCUR2_COLOR2 0x1a76 +#define mmDCP0_CUR2_COLOR2 0x1a76 +#define mmDCP1_CUR2_COLOR2 0x1d76 +#define mmDCP2_CUR2_COLOR2 0x4076 +#define mmDCP3_CUR2_COLOR2 0x4376 +#define mmDCP4_CUR2_COLOR2 0x4676 +#define mmDCP5_CUR2_COLOR2 0x4976 +#define mmCUR2_UPDATE 0x1a77 +#define mmDCP0_CUR2_UPDATE 0x1a77 +#define mmDCP1_CUR2_UPDATE 0x1d77 +#define mmDCP2_CUR2_UPDATE 0x4077 +#define mmDCP3_CUR2_UPDATE 0x4377 +#define mmDCP4_CUR2_UPDATE 0x4677 +#define mmDCP5_CUR2_UPDATE 0x4977 +#define mmCUR_REQUEST_FILTER_CNTL 0x1a99 +#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 +#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1d99 +#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099 +#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399 +#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699 +#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999 +#define mmCUR_STEREO_CONTROL 0x1a9a +#define mmDCP0_CUR_STEREO_CONTROL 0x1a9a +#define mmDCP1_CUR_STEREO_CONTROL 0x1d9a +#define mmDCP2_CUR_STEREO_CONTROL 0x409a +#define mmDCP3_CUR_STEREO_CONTROL 0x439a +#define mmDCP4_CUR_STEREO_CONTROL 0x469a +#define mmDCP5_CUR_STEREO_CONTROL 0x499a +#define mmCUR2_STEREO_CONTROL 0x1a9b +#define mmDCP0_CUR2_STEREO_CONTROL 0x1a9b +#define mmDCP1_CUR2_STEREO_CONTROL 0x1d9b +#define mmDCP2_CUR2_STEREO_CONTROL 0x409b +#define mmDCP3_CUR2_STEREO_CONTROL 0x439b +#define mmDCP4_CUR2_STEREO_CONTROL 0x469b +#define mmDCP5_CUR2_STEREO_CONTROL 0x499b +#define mmDC_LUT_RW_MODE 0x1a78 +#define mmDCP0_DC_LUT_RW_MODE 0x1a78 +#define mmDCP1_DC_LUT_RW_MODE 0x1d78 +#define mmDCP2_DC_LUT_RW_MODE 0x4078 +#define mmDCP3_DC_LUT_RW_MODE 0x4378 +#define mmDCP4_DC_LUT_RW_MODE 0x4678 +#define mmDCP5_DC_LUT_RW_MODE 0x4978 +#define mmDC_LUT_RW_INDEX 0x1a79 +#define mmDCP0_DC_LUT_RW_INDEX 0x1a79 +#define mmDCP1_DC_LUT_RW_INDEX 0x1d79 +#define mmDCP2_DC_LUT_RW_INDEX 0x4079 +#define mmDCP3_DC_LUT_RW_INDEX 0x4379 +#define mmDCP4_DC_LUT_RW_INDEX 0x4679 +#define mmDCP5_DC_LUT_RW_INDEX 0x4979 +#define mmDC_LUT_SEQ_COLOR 0x1a7a +#define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a +#define mmDCP1_DC_LUT_SEQ_COLOR 0x1d7a +#define mmDCP2_DC_LUT_SEQ_COLOR 0x407a +#define mmDCP3_DC_LUT_SEQ_COLOR 0x437a +#define mmDCP4_DC_LUT_SEQ_COLOR 0x467a +#define mmDCP5_DC_LUT_SEQ_COLOR 0x497a +#define mmDC_LUT_PWL_DATA 0x1a7b +#define mmDCP0_DC_LUT_PWL_DATA 0x1a7b +#define mmDCP1_DC_LUT_PWL_DATA 0x1d7b +#define mmDCP2_DC_LUT_PWL_DATA 0x407b +#define mmDCP3_DC_LUT_PWL_DATA 0x437b +#define mmDCP4_DC_LUT_PWL_DATA 0x467b +#define mmDCP5_DC_LUT_PWL_DATA 0x497b +#define mmDC_LUT_30_COLOR 0x1a7c +#define mmDCP0_DC_LUT_30_COLOR 0x1a7c +#define mmDCP1_DC_LUT_30_COLOR 0x1d7c +#define mmDCP2_DC_LUT_30_COLOR 0x407c +#define mmDCP3_DC_LUT_30_COLOR 0x437c +#define mmDCP4_DC_LUT_30_COLOR 0x467c +#define mmDCP5_DC_LUT_30_COLOR 0x497c +#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1d7d +#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407d +#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437d +#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467d +#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497d +#define mmDC_LUT_WRITE_EN_MASK 0x1a7e +#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e +#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1d7e +#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407e +#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437e +#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467e +#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497e +#define mmDC_LUT_AUTOFILL 0x1a7f +#define mmDCP0_DC_LUT_AUTOFILL 0x1a7f +#define mmDCP1_DC_LUT_AUTOFILL 0x1d7f +#define mmDCP2_DC_LUT_AUTOFILL 0x407f +#define mmDCP3_DC_LUT_AUTOFILL 0x437f +#define mmDCP4_DC_LUT_AUTOFILL 0x467f +#define mmDCP5_DC_LUT_AUTOFILL 0x497f +#define mmDC_LUT_CONTROL 0x1a80 +#define mmDCP0_DC_LUT_CONTROL 0x1a80 +#define mmDCP1_DC_LUT_CONTROL 0x1d80 +#define mmDCP2_DC_LUT_CONTROL 0x4080 +#define mmDCP3_DC_LUT_CONTROL 0x4380 +#define mmDCP4_DC_LUT_CONTROL 0x4680 +#define mmDCP5_DC_LUT_CONTROL 0x4980 +#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1d81 +#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081 +#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381 +#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681 +#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981 +#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1d82 +#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082 +#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382 +#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682 +#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982 +#define mmDC_LUT_BLACK_OFFSET_RED 0x1a83 +#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 +#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1d83 +#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083 +#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383 +#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683 +#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983 +#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1d84 +#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084 +#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384 +#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684 +#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984 +#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1d85 +#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085 +#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385 +#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685 +#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985 +#define mmDC_LUT_WHITE_OFFSET_RED 0x1a86 +#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 +#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1d86 +#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086 +#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386 +#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686 +#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986 +#define mmDCP_CRC_CONTROL 0x1a87 +#define mmDCP0_DCP_CRC_CONTROL 0x1a87 +#define mmDCP1_DCP_CRC_CONTROL 0x1d87 +#define mmDCP2_DCP_CRC_CONTROL 0x4087 +#define mmDCP3_DCP_CRC_CONTROL 0x4387 +#define mmDCP4_DCP_CRC_CONTROL 0x4687 +#define mmDCP5_DCP_CRC_CONTROL 0x4987 +#define mmDCP_CRC_MASK 0x1a88 +#define mmDCP0_DCP_CRC_MASK 0x1a88 +#define mmDCP1_DCP_CRC_MASK 0x1d88 +#define mmDCP2_DCP_CRC_MASK 0x4088 +#define mmDCP3_DCP_CRC_MASK 0x4388 +#define mmDCP4_DCP_CRC_MASK 0x4688 +#define mmDCP5_DCP_CRC_MASK 0x4988 +#define mmDCP_CRC_CURRENT 0x1a89 +#define mmDCP0_DCP_CRC_CURRENT 0x1a89 +#define mmDCP1_DCP_CRC_CURRENT 0x1d89 +#define mmDCP2_DCP_CRC_CURRENT 0x4089 +#define mmDCP3_DCP_CRC_CURRENT 0x4389 +#define mmDCP4_DCP_CRC_CURRENT 0x4689 +#define mmDCP5_DCP_CRC_CURRENT 0x4989 +#define mmDCP_CRC_LAST 0x1a8b +#define mmDCP0_DCP_CRC_LAST 0x1a8b +#define mmDCP1_DCP_CRC_LAST 0x1d8b +#define mmDCP2_DCP_CRC_LAST 0x408b +#define mmDCP3_DCP_CRC_LAST 0x438b +#define mmDCP4_DCP_CRC_LAST 0x468b +#define mmDCP5_DCP_CRC_LAST 0x498b +#define mmDCP_DEBUG 0x1a8d +#define mmDCP0_DCP_DEBUG 0x1a8d +#define mmDCP1_DCP_DEBUG 0x1d8d +#define mmDCP2_DCP_DEBUG 0x408d +#define mmDCP3_DCP_DEBUG 0x438d +#define mmDCP4_DCP_DEBUG 0x468d +#define mmDCP5_DCP_DEBUG 0x498d +#define mmGRPH_FLIP_RATE_CNTL 0x1a8e +#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e +#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1d8e +#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x408e +#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x438e +#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x468e +#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x498e +#define mmDCP_GSL_CONTROL 0x1a90 +#define mmDCP0_DCP_GSL_CONTROL 0x1a90 +#define mmDCP1_DCP_GSL_CONTROL 0x1d90 +#define mmDCP2_DCP_GSL_CONTROL 0x4090 +#define mmDCP3_DCP_GSL_CONTROL 0x4390 +#define mmDCP4_DCP_GSL_CONTROL 0x4690 +#define mmDCP5_DCP_GSL_CONTROL 0x4990 +#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1d91 +#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 +#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391 +#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691 +#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991 +#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92 +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92 +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1d92 +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392 +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692 +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992 +#define mmOVL_STEREOSYNC_FLIP 0x1a93 +#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93 +#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1d93 +#define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093 +#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393 +#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693 +#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993 +#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d94 +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394 +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694 +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994 +#define mmDCP_TEST_DEBUG_INDEX 0x1a95 +#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 +#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1d95 +#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095 +#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395 +#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695 +#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995 +#define mmDCP_TEST_DEBUG_DATA 0x1a96 +#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 +#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1d96 +#define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096 +#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396 +#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696 +#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996 +#define mmGRPH_STEREOSYNC_FLIP 0x1a97 +#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 +#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1d97 +#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097 +#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397 +#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697 +#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997 +#define mmDCP_DEBUG2 0x1a98 +#define mmDCP0_DCP_DEBUG2 0x1a98 +#define mmDCP1_DCP_DEBUG2 0x1d98 +#define mmDCP2_DCP_DEBUG2 0x4098 +#define mmDCP3_DCP_DEBUG2 0x4398 +#define mmDCP4_DCP_DEBUG2 0x4698 +#define mmDCP5_DCP_DEBUG2 0x4998 +#define mmHW_ROTATION 0x1a9e +#define mmDCP0_HW_ROTATION 0x1a9e +#define mmDCP1_HW_ROTATION 0x1d9e +#define mmDCP2_HW_ROTATION 0x409e +#define mmDCP3_HW_ROTATION 0x439e +#define mmDCP4_HW_ROTATION 0x469e +#define mmDCP5_HW_ROTATION 0x499e +#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1d9f +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x439f +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x469f +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x499f +#define mmREGAMMA_CONTROL 0x1aa0 +#define mmDCP0_REGAMMA_CONTROL 0x1aa0 +#define mmDCP1_REGAMMA_CONTROL 0x1da0 +#define mmDCP2_REGAMMA_CONTROL 0x40a0 +#define mmDCP3_REGAMMA_CONTROL 0x43a0 +#define mmDCP4_REGAMMA_CONTROL 0x46a0 +#define mmDCP5_REGAMMA_CONTROL 0x49a0 +#define mmREGAMMA_LUT_INDEX 0x1aa1 +#define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 +#define mmDCP1_REGAMMA_LUT_INDEX 0x1da1 +#define mmDCP2_REGAMMA_LUT_INDEX 0x40a1 +#define mmDCP3_REGAMMA_LUT_INDEX 0x43a1 +#define mmDCP4_REGAMMA_LUT_INDEX 0x46a1 +#define mmDCP5_REGAMMA_LUT_INDEX 0x49a1 +#define mmREGAMMA_LUT_DATA 0x1aa2 +#define mmDCP0_REGAMMA_LUT_DATA 0x1aa2 +#define mmDCP1_REGAMMA_LUT_DATA 0x1da2 +#define mmDCP2_REGAMMA_LUT_DATA 0x40a2 +#define mmDCP3_REGAMMA_LUT_DATA 0x43a2 +#define mmDCP4_REGAMMA_LUT_DATA 0x46a2 +#define mmDCP5_REGAMMA_LUT_DATA 0x49a2 +#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1da3 +#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 +#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43a3 +#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46a3 +#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49a3 +#define mmREGAMMA_CNTLA_START_CNTL 0x1aa4 +#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 +#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1da4 +#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40a4 +#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43a4 +#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46a4 +#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49a4 +#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1da5 +#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 +#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43a5 +#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46a5 +#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49a5 +#define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1da6 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40a6 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43a6 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46a6 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49a6 +#define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1da7 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40a7 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43a7 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46a7 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49a7 +#define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1da8 +#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40a8 +#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43a8 +#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46a8 +#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49a8 +#define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1da9 +#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40a9 +#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43a9 +#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46a9 +#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49a9 +#define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa +#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa +#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1daa +#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40aa +#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43aa +#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46aa +#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49aa +#define mmREGAMMA_CNTLA_REGION_6_7 0x1aab +#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab +#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1dab +#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40ab +#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43ab +#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46ab +#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49ab +#define mmREGAMMA_CNTLA_REGION_8_9 0x1aac +#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac +#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1dac +#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40ac +#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43ac +#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46ac +#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49ac +#define mmREGAMMA_CNTLA_REGION_10_11 0x1aad +#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad +#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1dad +#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40ad +#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43ad +#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46ad +#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49ad +#define mmREGAMMA_CNTLA_REGION_12_13 0x1aae +#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae +#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1dae +#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40ae +#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43ae +#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46ae +#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49ae +#define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf +#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf +#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1daf +#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40af +#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43af +#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46af +#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49af +#define mmREGAMMA_CNTLB_START_CNTL 0x1ab0 +#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 +#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1db0 +#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40b0 +#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43b0 +#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46b0 +#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49b0 +#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1db1 +#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 +#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43b1 +#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46b1 +#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49b1 +#define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1db2 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40b2 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43b2 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46b2 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49b2 +#define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1db3 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40b3 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43b3 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46b3 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49b3 +#define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1db4 +#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40b4 +#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43b4 +#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46b4 +#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49b4 +#define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1db5 +#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40b5 +#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43b5 +#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46b5 +#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49b5 +#define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1db6 +#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40b6 +#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43b6 +#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46b6 +#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49b6 +#define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1db7 +#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40b7 +#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43b7 +#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46b7 +#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49b7 +#define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1db8 +#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40b8 +#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43b8 +#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46b8 +#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49b8 +#define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1db9 +#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40b9 +#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43b9 +#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46b9 +#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49b9 +#define mmREGAMMA_CNTLB_REGION_12_13 0x1aba +#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba +#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1dba +#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40ba +#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43ba +#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46ba +#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49ba +#define mmREGAMMA_CNTLB_REGION_14_15 0x1abb +#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb +#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1dbb +#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40bb +#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43bb +#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46bb +#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49bb +#define mmALPHA_CONTROL 0x1abc +#define mmDCP0_ALPHA_CONTROL 0x1abc +#define mmDCP1_ALPHA_CONTROL 0x1dbc +#define mmDCP2_ALPHA_CONTROL 0x40bc +#define mmDCP3_ALPHA_CONTROL 0x43bc +#define mmDCP4_ALPHA_CONTROL 0x46bc +#define mmDCP5_ALPHA_CONTROL 0x49bc +#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1dbd +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x43bd +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x46bd +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x49bd +#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1dbe +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x43be +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x46be +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x49be +#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1dbf +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x43bf +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x46bf +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x49bf +#define mmDIG_FE_CNTL 0x1c00 +#define mmDIG0_DIG_FE_CNTL 0x1c00 +#define mmDIG1_DIG_FE_CNTL 0x1f00 +#define mmDIG2_DIG_FE_CNTL 0x4200 +#define mmDIG3_DIG_FE_CNTL 0x4500 +#define mmDIG4_DIG_FE_CNTL 0x4800 +#define mmDIG5_DIG_FE_CNTL 0x4b00 +#define mmDIG6_DIG_FE_CNTL 0x4e00 +#define mmDIG_OUTPUT_CRC_CNTL 0x1c01 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1c01 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1f01 +#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201 +#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501 +#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801 +#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4b01 +#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x4e01 +#define mmDIG_OUTPUT_CRC_RESULT 0x1c02 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1c02 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1f02 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4b02 +#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x4e02 +#define mmDIG_CLOCK_PATTERN 0x1c03 +#define mmDIG0_DIG_CLOCK_PATTERN 0x1c03 +#define mmDIG1_DIG_CLOCK_PATTERN 0x1f03 +#define mmDIG2_DIG_CLOCK_PATTERN 0x4203 +#define mmDIG3_DIG_CLOCK_PATTERN 0x4503 +#define mmDIG4_DIG_CLOCK_PATTERN 0x4803 +#define mmDIG5_DIG_CLOCK_PATTERN 0x4b03 +#define mmDIG6_DIG_CLOCK_PATTERN 0x4e03 +#define mmDIG_TEST_PATTERN 0x1c04 +#define mmDIG0_DIG_TEST_PATTERN 0x1c04 +#define mmDIG1_DIG_TEST_PATTERN 0x1f04 +#define mmDIG2_DIG_TEST_PATTERN 0x4204 +#define mmDIG3_DIG_TEST_PATTERN 0x4504 +#define mmDIG4_DIG_TEST_PATTERN 0x4804 +#define mmDIG5_DIG_TEST_PATTERN 0x4b04 +#define mmDIG6_DIG_TEST_PATTERN 0x4e04 +#define mmDIG_RANDOM_PATTERN_SEED 0x1c05 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1c05 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1f05 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4b05 +#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x4e05 +#define mmDIG_FIFO_STATUS 0x1c0a +#define mmDIG0_DIG_FIFO_STATUS 0x1c0a +#define mmDIG1_DIG_FIFO_STATUS 0x1f0a +#define mmDIG2_DIG_FIFO_STATUS 0x420a +#define mmDIG3_DIG_FIFO_STATUS 0x450a +#define mmDIG4_DIG_FIFO_STATUS 0x480a +#define mmDIG5_DIG_FIFO_STATUS 0x4b0a +#define mmDIG6_DIG_FIFO_STATUS 0x4e0a +#define mmDIG_DISPCLK_SWITCH_CNTL 0x1c08 +#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1c08 +#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1f08 +#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208 +#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508 +#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808 +#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4b08 +#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x4e08 +#define mmDIG_DISPCLK_SWITCH_STATUS 0x1c09 +#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1c09 +#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1f09 +#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209 +#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509 +#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809 +#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4b09 +#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x4e09 +#define mmHDMI_CONTROL 0x1c0c +#define mmDIG0_HDMI_CONTROL 0x1c0c +#define mmDIG1_HDMI_CONTROL 0x1f0c +#define mmDIG2_HDMI_CONTROL 0x420c +#define mmDIG3_HDMI_CONTROL 0x450c +#define mmDIG4_HDMI_CONTROL 0x480c +#define mmDIG5_HDMI_CONTROL 0x4b0c +#define mmDIG6_HDMI_CONTROL 0x4e0c +#define mmHDMI_STATUS 0x1c0d +#define mmDIG0_HDMI_STATUS 0x1c0d +#define mmDIG1_HDMI_STATUS 0x1f0d +#define mmDIG2_HDMI_STATUS 0x420d +#define mmDIG3_HDMI_STATUS 0x450d +#define mmDIG4_HDMI_STATUS 0x480d +#define mmDIG5_HDMI_STATUS 0x4b0d +#define mmDIG6_HDMI_STATUS 0x4e0d +#define mmHDMI_AUDIO_PACKET_CONTROL 0x1c0e +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1c0e +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1f0e +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420e +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450e +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480e +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4b0e +#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x4e0e +#define mmHDMI_ACR_PACKET_CONTROL 0x1c0f +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1c0f +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1f0f +#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420f +#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450f +#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480f +#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4b0f +#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x4e0f +#define mmHDMI_VBI_PACKET_CONTROL 0x1c10 +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1c10 +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1f10 +#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210 +#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510 +#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810 +#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4b10 +#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x4e10 +#define mmHDMI_INFOFRAME_CONTROL0 0x1c11 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1c11 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1f11 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811 +#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4b11 +#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x4e11 +#define mmHDMI_INFOFRAME_CONTROL1 0x1c12 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1c12 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1f12 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812 +#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4b12 +#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x4e12 +#define mmHDMI_GENERIC_PACKET_CONTROL0 0x1c13 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1c13 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1f13 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4b13 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x4e13 +#define mmAFMT_INTERRUPT_STATUS 0x1c14 +#define mmDIG0_AFMT_INTERRUPT_STATUS 0x1c14 +#define mmDIG1_AFMT_INTERRUPT_STATUS 0x1f14 +#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214 +#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514 +#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814 +#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4b14 +#define mmDIG6_AFMT_INTERRUPT_STATUS 0x4e14 +#define mmHDMI_GC 0x1c16 +#define mmDIG0_HDMI_GC 0x1c16 +#define mmDIG1_HDMI_GC 0x1f16 +#define mmDIG2_HDMI_GC 0x4216 +#define mmDIG3_HDMI_GC 0x4516 +#define mmDIG4_HDMI_GC 0x4816 +#define mmDIG5_HDMI_GC 0x4b16 +#define mmDIG6_HDMI_GC 0x4e16 +#define mmAFMT_AUDIO_PACKET_CONTROL2 0x1c17 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1c17 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1f17 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4b17 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x4e17 +#define mmAFMT_ISRC1_0 0x1c18 +#define mmDIG0_AFMT_ISRC1_0 0x1c18 +#define mmDIG1_AFMT_ISRC1_0 0x1f18 +#define mmDIG2_AFMT_ISRC1_0 0x4218 +#define mmDIG3_AFMT_ISRC1_0 0x4518 +#define mmDIG4_AFMT_ISRC1_0 0x4818 +#define mmDIG5_AFMT_ISRC1_0 0x4b18 +#define mmDIG6_AFMT_ISRC1_0 0x4e18 +#define mmAFMT_ISRC1_1 0x1c19 +#define mmDIG0_AFMT_ISRC1_1 0x1c19 +#define mmDIG1_AFMT_ISRC1_1 0x1f19 +#define mmDIG2_AFMT_ISRC1_1 0x4219 +#define mmDIG3_AFMT_ISRC1_1 0x4519 +#define mmDIG4_AFMT_ISRC1_1 0x4819 +#define mmDIG5_AFMT_ISRC1_1 0x4b19 +#define mmDIG6_AFMT_ISRC1_1 0x4e19 +#define mmAFMT_ISRC1_2 0x1c1a +#define mmDIG0_AFMT_ISRC1_2 0x1c1a +#define mmDIG1_AFMT_ISRC1_2 0x1f1a +#define mmDIG2_AFMT_ISRC1_2 0x421a +#define mmDIG3_AFMT_ISRC1_2 0x451a +#define mmDIG4_AFMT_ISRC1_2 0x481a +#define mmDIG5_AFMT_ISRC1_2 0x4b1a +#define mmDIG6_AFMT_ISRC1_2 0x4e1a +#define mmAFMT_ISRC1_3 0x1c1b +#define mmDIG0_AFMT_ISRC1_3 0x1c1b +#define mmDIG1_AFMT_ISRC1_3 0x1f1b +#define mmDIG2_AFMT_ISRC1_3 0x421b +#define mmDIG3_AFMT_ISRC1_3 0x451b +#define mmDIG4_AFMT_ISRC1_3 0x481b +#define mmDIG5_AFMT_ISRC1_3 0x4b1b +#define mmDIG6_AFMT_ISRC1_3 0x4e1b +#define mmAFMT_ISRC1_4 0x1c1c +#define mmDIG0_AFMT_ISRC1_4 0x1c1c +#define mmDIG1_AFMT_ISRC1_4 0x1f1c +#define mmDIG2_AFMT_ISRC1_4 0x421c +#define mmDIG3_AFMT_ISRC1_4 0x451c +#define mmDIG4_AFMT_ISRC1_4 0x481c +#define mmDIG5_AFMT_ISRC1_4 0x4b1c +#define mmDIG6_AFMT_ISRC1_4 0x4e1c +#define mmAFMT_ISRC2_0 0x1c1d +#define mmDIG0_AFMT_ISRC2_0 0x1c1d +#define mmDIG1_AFMT_ISRC2_0 0x1f1d +#define mmDIG2_AFMT_ISRC2_0 0x421d +#define mmDIG3_AFMT_ISRC2_0 0x451d +#define mmDIG4_AFMT_ISRC2_0 0x481d +#define mmDIG5_AFMT_ISRC2_0 0x4b1d +#define mmDIG6_AFMT_ISRC2_0 0x4e1d +#define mmAFMT_ISRC2_1 0x1c1e +#define mmDIG0_AFMT_ISRC2_1 0x1c1e +#define mmDIG1_AFMT_ISRC2_1 0x1f1e +#define mmDIG2_AFMT_ISRC2_1 0x421e +#define mmDIG3_AFMT_ISRC2_1 0x451e +#define mmDIG4_AFMT_ISRC2_1 0x481e +#define mmDIG5_AFMT_ISRC2_1 0x4b1e +#define mmDIG6_AFMT_ISRC2_1 0x4e1e +#define mmAFMT_ISRC2_2 0x1c1f +#define mmDIG0_AFMT_ISRC2_2 0x1c1f +#define mmDIG1_AFMT_ISRC2_2 0x1f1f +#define mmDIG2_AFMT_ISRC2_2 0x421f +#define mmDIG3_AFMT_ISRC2_2 0x451f +#define mmDIG4_AFMT_ISRC2_2 0x481f +#define mmDIG5_AFMT_ISRC2_2 0x4b1f +#define mmDIG6_AFMT_ISRC2_2 0x4e1f +#define mmAFMT_ISRC2_3 0x1c20 +#define mmDIG0_AFMT_ISRC2_3 0x1c20 +#define mmDIG1_AFMT_ISRC2_3 0x1f20 +#define mmDIG2_AFMT_ISRC2_3 0x4220 +#define mmDIG3_AFMT_ISRC2_3 0x4520 +#define mmDIG4_AFMT_ISRC2_3 0x4820 +#define mmDIG5_AFMT_ISRC2_3 0x4b20 +#define mmDIG6_AFMT_ISRC2_3 0x4e20 +#define mmAFMT_AVI_INFO0 0x1c21 +#define mmDIG0_AFMT_AVI_INFO0 0x1c21 +#define mmDIG1_AFMT_AVI_INFO0 0x1f21 +#define mmDIG2_AFMT_AVI_INFO0 0x4221 +#define mmDIG3_AFMT_AVI_INFO0 0x4521 +#define mmDIG4_AFMT_AVI_INFO0 0x4821 +#define mmDIG5_AFMT_AVI_INFO0 0x4b21 +#define mmDIG6_AFMT_AVI_INFO0 0x4e21 +#define mmAFMT_AVI_INFO1 0x1c22 +#define mmDIG0_AFMT_AVI_INFO1 0x1c22 +#define mmDIG1_AFMT_AVI_INFO1 0x1f22 +#define mmDIG2_AFMT_AVI_INFO1 0x4222 +#define mmDIG3_AFMT_AVI_INFO1 0x4522 +#define mmDIG4_AFMT_AVI_INFO1 0x4822 +#define mmDIG5_AFMT_AVI_INFO1 0x4b22 +#define mmDIG6_AFMT_AVI_INFO1 0x4e22 +#define mmAFMT_AVI_INFO2 0x1c23 +#define mmDIG0_AFMT_AVI_INFO2 0x1c23 +#define mmDIG1_AFMT_AVI_INFO2 0x1f23 +#define mmDIG2_AFMT_AVI_INFO2 0x4223 +#define mmDIG3_AFMT_AVI_INFO2 0x4523 +#define mmDIG4_AFMT_AVI_INFO2 0x4823 +#define mmDIG5_AFMT_AVI_INFO2 0x4b23 +#define mmDIG6_AFMT_AVI_INFO2 0x4e23 +#define mmAFMT_AVI_INFO3 0x1c24 +#define mmDIG0_AFMT_AVI_INFO3 0x1c24 +#define mmDIG1_AFMT_AVI_INFO3 0x1f24 +#define mmDIG2_AFMT_AVI_INFO3 0x4224 +#define mmDIG3_AFMT_AVI_INFO3 0x4524 +#define mmDIG4_AFMT_AVI_INFO3 0x4824 +#define mmDIG5_AFMT_AVI_INFO3 0x4b24 +#define mmDIG6_AFMT_AVI_INFO3 0x4e24 +#define mmAFMT_MPEG_INFO0 0x1c25 +#define mmDIG0_AFMT_MPEG_INFO0 0x1c25 +#define mmDIG1_AFMT_MPEG_INFO0 0x1f25 +#define mmDIG2_AFMT_MPEG_INFO0 0x4225 +#define mmDIG3_AFMT_MPEG_INFO0 0x4525 +#define mmDIG4_AFMT_MPEG_INFO0 0x4825 +#define mmDIG5_AFMT_MPEG_INFO0 0x4b25 +#define mmDIG6_AFMT_MPEG_INFO0 0x4e25 +#define mmAFMT_MPEG_INFO1 0x1c26 +#define mmDIG0_AFMT_MPEG_INFO1 0x1c26 +#define mmDIG1_AFMT_MPEG_INFO1 0x1f26 +#define mmDIG2_AFMT_MPEG_INFO1 0x4226 +#define mmDIG3_AFMT_MPEG_INFO1 0x4526 +#define mmDIG4_AFMT_MPEG_INFO1 0x4826 +#define mmDIG5_AFMT_MPEG_INFO1 0x4b26 +#define mmDIG6_AFMT_MPEG_INFO1 0x4e26 +#define mmAFMT_GENERIC_HDR 0x1c27 +#define mmDIG0_AFMT_GENERIC_HDR 0x1c27 +#define mmDIG1_AFMT_GENERIC_HDR 0x1f27 +#define mmDIG2_AFMT_GENERIC_HDR 0x4227 +#define mmDIG3_AFMT_GENERIC_HDR 0x4527 +#define mmDIG4_AFMT_GENERIC_HDR 0x4827 +#define mmDIG5_AFMT_GENERIC_HDR 0x4b27 +#define mmDIG6_AFMT_GENERIC_HDR 0x4e27 +#define mmAFMT_GENERIC_0 0x1c28 +#define mmDIG0_AFMT_GENERIC_0 0x1c28 +#define mmDIG1_AFMT_GENERIC_0 0x1f28 +#define mmDIG2_AFMT_GENERIC_0 0x4228 +#define mmDIG3_AFMT_GENERIC_0 0x4528 +#define mmDIG4_AFMT_GENERIC_0 0x4828 +#define mmDIG5_AFMT_GENERIC_0 0x4b28 +#define mmDIG6_AFMT_GENERIC_0 0x4e28 +#define mmAFMT_GENERIC_1 0x1c29 +#define mmDIG0_AFMT_GENERIC_1 0x1c29 +#define mmDIG1_AFMT_GENERIC_1 0x1f29 +#define mmDIG2_AFMT_GENERIC_1 0x4229 +#define mmDIG3_AFMT_GENERIC_1 0x4529 +#define mmDIG4_AFMT_GENERIC_1 0x4829 +#define mmDIG5_AFMT_GENERIC_1 0x4b29 +#define mmDIG6_AFMT_GENERIC_1 0x4e29 +#define mmAFMT_GENERIC_2 0x1c2a +#define mmDIG0_AFMT_GENERIC_2 0x1c2a +#define mmDIG1_AFMT_GENERIC_2 0x1f2a +#define mmDIG2_AFMT_GENERIC_2 0x422a +#define mmDIG3_AFMT_GENERIC_2 0x452a +#define mmDIG4_AFMT_GENERIC_2 0x482a +#define mmDIG5_AFMT_GENERIC_2 0x4b2a +#define mmDIG6_AFMT_GENERIC_2 0x4e2a +#define mmAFMT_GENERIC_3 0x1c2b +#define mmDIG0_AFMT_GENERIC_3 0x1c2b +#define mmDIG1_AFMT_GENERIC_3 0x1f2b +#define mmDIG2_AFMT_GENERIC_3 0x422b +#define mmDIG3_AFMT_GENERIC_3 0x452b +#define mmDIG4_AFMT_GENERIC_3 0x482b +#define mmDIG5_AFMT_GENERIC_3 0x4b2b +#define mmDIG6_AFMT_GENERIC_3 0x4e2b +#define mmAFMT_GENERIC_4 0x1c2c +#define mmDIG0_AFMT_GENERIC_4 0x1c2c +#define mmDIG1_AFMT_GENERIC_4 0x1f2c +#define mmDIG2_AFMT_GENERIC_4 0x422c +#define mmDIG3_AFMT_GENERIC_4 0x452c +#define mmDIG4_AFMT_GENERIC_4 0x482c +#define mmDIG5_AFMT_GENERIC_4 0x4b2c +#define mmDIG6_AFMT_GENERIC_4 0x4e2c +#define mmAFMT_GENERIC_5 0x1c2d +#define mmDIG0_AFMT_GENERIC_5 0x1c2d +#define mmDIG1_AFMT_GENERIC_5 0x1f2d +#define mmDIG2_AFMT_GENERIC_5 0x422d +#define mmDIG3_AFMT_GENERIC_5 0x452d +#define mmDIG4_AFMT_GENERIC_5 0x482d +#define mmDIG5_AFMT_GENERIC_5 0x4b2d +#define mmDIG6_AFMT_GENERIC_5 0x4e2d +#define mmAFMT_GENERIC_6 0x1c2e +#define mmDIG0_AFMT_GENERIC_6 0x1c2e +#define mmDIG1_AFMT_GENERIC_6 0x1f2e +#define mmDIG2_AFMT_GENERIC_6 0x422e +#define mmDIG3_AFMT_GENERIC_6 0x452e +#define mmDIG4_AFMT_GENERIC_6 0x482e +#define mmDIG5_AFMT_GENERIC_6 0x4b2e +#define mmDIG6_AFMT_GENERIC_6 0x4e2e +#define mmAFMT_GENERIC_7 0x1c2f +#define mmDIG0_AFMT_GENERIC_7 0x1c2f +#define mmDIG1_AFMT_GENERIC_7 0x1f2f +#define mmDIG2_AFMT_GENERIC_7 0x422f +#define mmDIG3_AFMT_GENERIC_7 0x452f +#define mmDIG4_AFMT_GENERIC_7 0x482f +#define mmDIG5_AFMT_GENERIC_7 0x4b2f +#define mmDIG6_AFMT_GENERIC_7 0x4e2f +#define mmHDMI_GENERIC_PACKET_CONTROL1 0x1c30 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1c30 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1f30 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4b30 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x4e30 +#define mmHDMI_ACR_32_0 0x1c37 +#define mmDIG0_HDMI_ACR_32_0 0x1c37 +#define mmDIG1_HDMI_ACR_32_0 0x1f37 +#define mmDIG2_HDMI_ACR_32_0 0x4237 +#define mmDIG3_HDMI_ACR_32_0 0x4537 +#define mmDIG4_HDMI_ACR_32_0 0x4837 +#define mmDIG5_HDMI_ACR_32_0 0x4b37 +#define mmDIG6_HDMI_ACR_32_0 0x4e37 +#define mmHDMI_ACR_32_1 0x1c38 +#define mmDIG0_HDMI_ACR_32_1 0x1c38 +#define mmDIG1_HDMI_ACR_32_1 0x1f38 +#define mmDIG2_HDMI_ACR_32_1 0x4238 +#define mmDIG3_HDMI_ACR_32_1 0x4538 +#define mmDIG4_HDMI_ACR_32_1 0x4838 +#define mmDIG5_HDMI_ACR_32_1 0x4b38 +#define mmDIG6_HDMI_ACR_32_1 0x4e38 +#define mmHDMI_ACR_44_0 0x1c39 +#define mmDIG0_HDMI_ACR_44_0 0x1c39 +#define mmDIG1_HDMI_ACR_44_0 0x1f39 +#define mmDIG2_HDMI_ACR_44_0 0x4239 +#define mmDIG3_HDMI_ACR_44_0 0x4539 +#define mmDIG4_HDMI_ACR_44_0 0x4839 +#define mmDIG5_HDMI_ACR_44_0 0x4b39 +#define mmDIG6_HDMI_ACR_44_0 0x4e39 +#define mmHDMI_ACR_44_1 0x1c3a +#define mmDIG0_HDMI_ACR_44_1 0x1c3a +#define mmDIG1_HDMI_ACR_44_1 0x1f3a +#define mmDIG2_HDMI_ACR_44_1 0x423a +#define mmDIG3_HDMI_ACR_44_1 0x453a +#define mmDIG4_HDMI_ACR_44_1 0x483a +#define mmDIG5_HDMI_ACR_44_1 0x4b3a +#define mmDIG6_HDMI_ACR_44_1 0x4e3a +#define mmHDMI_ACR_48_0 0x1c3b +#define mmDIG0_HDMI_ACR_48_0 0x1c3b +#define mmDIG1_HDMI_ACR_48_0 0x1f3b +#define mmDIG2_HDMI_ACR_48_0 0x423b +#define mmDIG3_HDMI_ACR_48_0 0x453b +#define mmDIG4_HDMI_ACR_48_0 0x483b +#define mmDIG5_HDMI_ACR_48_0 0x4b3b +#define mmDIG6_HDMI_ACR_48_0 0x4e3b +#define mmHDMI_ACR_48_1 0x1c3c +#define mmDIG0_HDMI_ACR_48_1 0x1c3c +#define mmDIG1_HDMI_ACR_48_1 0x1f3c +#define mmDIG2_HDMI_ACR_48_1 0x423c +#define mmDIG3_HDMI_ACR_48_1 0x453c +#define mmDIG4_HDMI_ACR_48_1 0x483c +#define mmDIG5_HDMI_ACR_48_1 0x4b3c +#define mmDIG6_HDMI_ACR_48_1 0x4e3c +#define mmHDMI_ACR_STATUS_0 0x1c3d +#define mmDIG0_HDMI_ACR_STATUS_0 0x1c3d +#define mmDIG1_HDMI_ACR_STATUS_0 0x1f3d +#define mmDIG2_HDMI_ACR_STATUS_0 0x423d +#define mmDIG3_HDMI_ACR_STATUS_0 0x453d +#define mmDIG4_HDMI_ACR_STATUS_0 0x483d +#define mmDIG5_HDMI_ACR_STATUS_0 0x4b3d +#define mmDIG6_HDMI_ACR_STATUS_0 0x4e3d +#define mmHDMI_ACR_STATUS_1 0x1c3e +#define mmDIG0_HDMI_ACR_STATUS_1 0x1c3e +#define mmDIG1_HDMI_ACR_STATUS_1 0x1f3e +#define mmDIG2_HDMI_ACR_STATUS_1 0x423e +#define mmDIG3_HDMI_ACR_STATUS_1 0x453e +#define mmDIG4_HDMI_ACR_STATUS_1 0x483e +#define mmDIG5_HDMI_ACR_STATUS_1 0x4b3e +#define mmDIG6_HDMI_ACR_STATUS_1 0x4e3e +#define mmAFMT_AUDIO_INFO0 0x1c3f +#define mmDIG0_AFMT_AUDIO_INFO0 0x1c3f +#define mmDIG1_AFMT_AUDIO_INFO0 0x1f3f +#define mmDIG2_AFMT_AUDIO_INFO0 0x423f +#define mmDIG3_AFMT_AUDIO_INFO0 0x453f +#define mmDIG4_AFMT_AUDIO_INFO0 0x483f +#define mmDIG5_AFMT_AUDIO_INFO0 0x4b3f +#define mmDIG6_AFMT_AUDIO_INFO0 0x4e3f +#define mmAFMT_AUDIO_INFO1 0x1c40 +#define mmDIG0_AFMT_AUDIO_INFO1 0x1c40 +#define mmDIG1_AFMT_AUDIO_INFO1 0x1f40 +#define mmDIG2_AFMT_AUDIO_INFO1 0x4240 +#define mmDIG3_AFMT_AUDIO_INFO1 0x4540 +#define mmDIG4_AFMT_AUDIO_INFO1 0x4840 +#define mmDIG5_AFMT_AUDIO_INFO1 0x4b40 +#define mmDIG6_AFMT_AUDIO_INFO1 0x4e40 +#define mmAFMT_60958_0 0x1c41 +#define mmDIG0_AFMT_60958_0 0x1c41 +#define mmDIG1_AFMT_60958_0 0x1f41 +#define mmDIG2_AFMT_60958_0 0x4241 +#define mmDIG3_AFMT_60958_0 0x4541 +#define mmDIG4_AFMT_60958_0 0x4841 +#define mmDIG5_AFMT_60958_0 0x4b41 +#define mmDIG6_AFMT_60958_0 0x4e41 +#define mmAFMT_60958_1 0x1c42 +#define mmDIG0_AFMT_60958_1 0x1c42 +#define mmDIG1_AFMT_60958_1 0x1f42 +#define mmDIG2_AFMT_60958_1 0x4242 +#define mmDIG3_AFMT_60958_1 0x4542 +#define mmDIG4_AFMT_60958_1 0x4842 +#define mmDIG5_AFMT_60958_1 0x4b42 +#define mmDIG6_AFMT_60958_1 0x4e42 +#define mmAFMT_AUDIO_CRC_CONTROL 0x1c43 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1c43 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1f43 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843 +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4b43 +#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x4e43 +#define mmAFMT_RAMP_CONTROL0 0x1c44 +#define mmDIG0_AFMT_RAMP_CONTROL0 0x1c44 +#define mmDIG1_AFMT_RAMP_CONTROL0 0x1f44 +#define mmDIG2_AFMT_RAMP_CONTROL0 0x4244 +#define mmDIG3_AFMT_RAMP_CONTROL0 0x4544 +#define mmDIG4_AFMT_RAMP_CONTROL0 0x4844 +#define mmDIG5_AFMT_RAMP_CONTROL0 0x4b44 +#define mmDIG6_AFMT_RAMP_CONTROL0 0x4e44 +#define mmAFMT_RAMP_CONTROL1 0x1c45 +#define mmDIG0_AFMT_RAMP_CONTROL1 0x1c45 +#define mmDIG1_AFMT_RAMP_CONTROL1 0x1f45 +#define mmDIG2_AFMT_RAMP_CONTROL1 0x4245 +#define mmDIG3_AFMT_RAMP_CONTROL1 0x4545 +#define mmDIG4_AFMT_RAMP_CONTROL1 0x4845 +#define mmDIG5_AFMT_RAMP_CONTROL1 0x4b45 +#define mmDIG6_AFMT_RAMP_CONTROL1 0x4e45 +#define mmAFMT_RAMP_CONTROL2 0x1c46 +#define mmDIG0_AFMT_RAMP_CONTROL2 0x1c46 +#define mmDIG1_AFMT_RAMP_CONTROL2 0x1f46 +#define mmDIG2_AFMT_RAMP_CONTROL2 0x4246 +#define mmDIG3_AFMT_RAMP_CONTROL2 0x4546 +#define mmDIG4_AFMT_RAMP_CONTROL2 0x4846 +#define mmDIG5_AFMT_RAMP_CONTROL2 0x4b46 +#define mmDIG6_AFMT_RAMP_CONTROL2 0x4e46 +#define mmAFMT_RAMP_CONTROL3 0x1c47 +#define mmDIG0_AFMT_RAMP_CONTROL3 0x1c47 +#define mmDIG1_AFMT_RAMP_CONTROL3 0x1f47 +#define mmDIG2_AFMT_RAMP_CONTROL3 0x4247 +#define mmDIG3_AFMT_RAMP_CONTROL3 0x4547 +#define mmDIG4_AFMT_RAMP_CONTROL3 0x4847 +#define mmDIG5_AFMT_RAMP_CONTROL3 0x4b47 +#define mmDIG6_AFMT_RAMP_CONTROL3 0x4e47 +#define mmAFMT_60958_2 0x1c48 +#define mmDIG0_AFMT_60958_2 0x1c48 +#define mmDIG1_AFMT_60958_2 0x1f48 +#define mmDIG2_AFMT_60958_2 0x4248 +#define mmDIG3_AFMT_60958_2 0x4548 +#define mmDIG4_AFMT_60958_2 0x4848 +#define mmDIG5_AFMT_60958_2 0x4b48 +#define mmDIG6_AFMT_60958_2 0x4e48 +#define mmAFMT_AUDIO_CRC_RESULT 0x1c49 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1c49 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1f49 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4b49 +#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x4e49 +#define mmAFMT_STATUS 0x1c4a +#define mmDIG0_AFMT_STATUS 0x1c4a +#define mmDIG1_AFMT_STATUS 0x1f4a +#define mmDIG2_AFMT_STATUS 0x424a +#define mmDIG3_AFMT_STATUS 0x454a +#define mmDIG4_AFMT_STATUS 0x484a +#define mmDIG5_AFMT_STATUS 0x4b4a +#define mmDIG6_AFMT_STATUS 0x4e4a +#define mmAFMT_AUDIO_PACKET_CONTROL 0x1c4b +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1c4b +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1f4b +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424b +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454b +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484b +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4b4b +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x4e4b +#define mmAFMT_VBI_PACKET_CONTROL 0x1c4c +#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1c4c +#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1f4c +#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424c +#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454c +#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484c +#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4b4c +#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x4e4c +#define mmAFMT_INFOFRAME_CONTROL0 0x1c4d +#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1c4d +#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1f4d +#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424d +#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454d +#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484d +#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4b4d +#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x4e4d +#define mmAFMT_AUDIO_SRC_CONTROL 0x1c4f +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1c4f +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1f4f +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424f +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454f +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484f +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4b4f +#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x4e4f +#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1c52 +#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1c52 +#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1f52 +#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252 +#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552 +#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852 +#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4b52 +#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x4e52 +#define mmDIG_BE_CNTL 0x1c50 +#define mmDIG0_DIG_BE_CNTL 0x1c50 +#define mmDIG1_DIG_BE_CNTL 0x1f50 +#define mmDIG2_DIG_BE_CNTL 0x4250 +#define mmDIG3_DIG_BE_CNTL 0x4550 +#define mmDIG4_DIG_BE_CNTL 0x4850 +#define mmDIG5_DIG_BE_CNTL 0x4b50 +#define mmDIG6_DIG_BE_CNTL 0x4e50 +#define mmDIG_BE_EN_CNTL 0x1c51 +#define mmDIG0_DIG_BE_EN_CNTL 0x1c51 +#define mmDIG1_DIG_BE_EN_CNTL 0x1f51 +#define mmDIG2_DIG_BE_EN_CNTL 0x4251 +#define mmDIG3_DIG_BE_EN_CNTL 0x4551 +#define mmDIG4_DIG_BE_EN_CNTL 0x4851 +#define mmDIG5_DIG_BE_EN_CNTL 0x4b51 +#define mmDIG6_DIG_BE_EN_CNTL 0x4e51 +#define mmTMDS_CNTL 0x1c7c +#define mmDIG0_TMDS_CNTL 0x1c7c +#define mmDIG1_TMDS_CNTL 0x1f7c +#define mmDIG2_TMDS_CNTL 0x427c +#define mmDIG3_TMDS_CNTL 0x457c +#define mmDIG4_TMDS_CNTL 0x487c +#define mmDIG5_TMDS_CNTL 0x4b7c +#define mmDIG6_TMDS_CNTL 0x4e7c +#define mmTMDS_CONTROL_CHAR 0x1c7d +#define mmDIG0_TMDS_CONTROL_CHAR 0x1c7d +#define mmDIG1_TMDS_CONTROL_CHAR 0x1f7d +#define mmDIG2_TMDS_CONTROL_CHAR 0x427d +#define mmDIG3_TMDS_CONTROL_CHAR 0x457d +#define mmDIG4_TMDS_CONTROL_CHAR 0x487d +#define mmDIG5_TMDS_CONTROL_CHAR 0x4b7d +#define mmDIG6_TMDS_CONTROL_CHAR 0x4e7d +#define mmTMDS_CONTROL0_FEEDBACK 0x1c7e +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1c7e +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1f7e +#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427e +#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457e +#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487e +#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4b7e +#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x4e7e +#define mmTMDS_STEREOSYNC_CTL_SEL 0x1c7f +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1c7f +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1f7f +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427f +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457f +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487f +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4b7f +#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x4e7f +#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1c80 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1c80 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1f80 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b80 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e80 +#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1c81 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1c81 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1f81 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b81 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e81 +#define mmTMDS_DEBUG 0x1c82 +#define mmDIG0_TMDS_DEBUG 0x1c82 +#define mmDIG1_TMDS_DEBUG 0x1f82 +#define mmDIG2_TMDS_DEBUG 0x4282 +#define mmDIG3_TMDS_DEBUG 0x4582 +#define mmDIG4_TMDS_DEBUG 0x4882 +#define mmDIG5_TMDS_DEBUG 0x4b82 +#define mmDIG6_TMDS_DEBUG 0x4e82 +#define mmTMDS_CTL_BITS 0x1c83 +#define mmDIG0_TMDS_CTL_BITS 0x1c83 +#define mmDIG1_TMDS_CTL_BITS 0x1f83 +#define mmDIG2_TMDS_CTL_BITS 0x4283 +#define mmDIG3_TMDS_CTL_BITS 0x4583 +#define mmDIG4_TMDS_CTL_BITS 0x4883 +#define mmDIG5_TMDS_CTL_BITS 0x4b83 +#define mmDIG6_TMDS_CTL_BITS 0x4e83 +#define mmTMDS_DCBALANCER_CONTROL 0x1c84 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1c84 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1f84 +#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284 +#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584 +#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884 +#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4b84 +#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x4e84 +#define mmTMDS_CTL0_1_GEN_CNTL 0x1c86 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1c86 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1f86 +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286 +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586 +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886 +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4b86 +#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x4e86 +#define mmTMDS_CTL2_3_GEN_CNTL 0x1c87 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1c87 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1f87 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4b87 +#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x4e87 +#define mmLVDS_DATA_CNTL 0x1c8c +#define mmDIG0_LVDS_DATA_CNTL 0x1c8c +#define mmDIG1_LVDS_DATA_CNTL 0x1f8c +#define mmDIG2_LVDS_DATA_CNTL 0x428c +#define mmDIG3_LVDS_DATA_CNTL 0x458c +#define mmDIG4_LVDS_DATA_CNTL 0x488c +#define mmDIG5_LVDS_DATA_CNTL 0x4b8c +#define mmDIG6_LVDS_DATA_CNTL 0x4e8c +#define mmDIG_LANE_ENABLE 0x1c8d +#define mmDIG0_DIG_LANE_ENABLE 0x1c8d +#define mmDIG1_DIG_LANE_ENABLE 0x1f8d +#define mmDIG2_DIG_LANE_ENABLE 0x428d +#define mmDIG3_DIG_LANE_ENABLE 0x458d +#define mmDIG4_DIG_LANE_ENABLE 0x488d +#define mmDIG5_DIG_LANE_ENABLE 0x4b8d +#define mmDIG6_DIG_LANE_ENABLE 0x4e8d +#define mmDOUT_SCRATCH0 0x1844 +#define mmDOUT_SCRATCH1 0x1845 +#define mmDOUT_SCRATCH2 0x1846 +#define mmDOUT_SCRATCH3 0x1847 +#define mmDOUT_SCRATCH4 0x1848 +#define mmDOUT_SCRATCH5 0x1849 +#define mmDOUT_SCRATCH6 0x184a +#define mmDOUT_SCRATCH7 0x184b +#define mmDOUT_DCE_VCE_CONTROL 0x18ff +#define mmDC_HPD1_INT_STATUS 0x1807 +#define mmDC_HPD1_INT_CONTROL 0x1808 +#define mmDC_HPD1_CONTROL 0x1809 +#define mmDC_HPD2_INT_STATUS 0x180a +#define mmDC_HPD2_INT_CONTROL 0x180b +#define mmDC_HPD2_CONTROL 0x180c +#define mmDC_HPD3_INT_STATUS 0x180d +#define mmDC_HPD3_INT_CONTROL 0x180e +#define mmDC_HPD3_CONTROL 0x180f +#define mmDC_HPD4_INT_STATUS 0x1810 +#define mmDC_HPD4_INT_CONTROL 0x1811 +#define mmDC_HPD4_CONTROL 0x1812 +#define mmDC_HPD5_INT_STATUS 0x1813 +#define mmDC_HPD5_INT_CONTROL 0x1814 +#define mmDC_HPD5_CONTROL 0x1815 +#define mmDC_HPD6_INT_STATUS 0x1816 +#define mmDC_HPD6_INT_CONTROL 0x1817 +#define mmDC_HPD6_CONTROL 0x1818 +#define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864 +#define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865 +#define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866 +#define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867 +#define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868 +#define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869 +#define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18bc +#define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18bd +#define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18be +#define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18fc +#define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18fd +#define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18fe +#define mmDC_I2C_CONTROL 0x1819 +#define mmDC_I2C_ARBITRATION 0x181a +#define mmDC_I2C_INTERRUPT_CONTROL 0x181b +#define mmDC_I2C_SW_STATUS 0x181c +#define mmDC_I2C_DDC1_HW_STATUS 0x181d +#define mmDC_I2C_DDC2_HW_STATUS 0x181e +#define mmDC_I2C_DDC3_HW_STATUS 0x181f +#define mmDC_I2C_DDC4_HW_STATUS 0x1820 +#define mmDC_I2C_DDC5_HW_STATUS 0x1821 +#define mmDC_I2C_DDC6_HW_STATUS 0x1822 +#define mmDC_I2C_DDC1_SPEED 0x1823 +#define mmDC_I2C_DDC1_SETUP 0x1824 +#define mmDC_I2C_DDC2_SPEED 0x1825 +#define mmDC_I2C_DDC2_SETUP 0x1826 +#define mmDC_I2C_DDC3_SPEED 0x1827 +#define mmDC_I2C_DDC3_SETUP 0x1828 +#define mmDC_I2C_DDC4_SPEED 0x1829 +#define mmDC_I2C_DDC4_SETUP 0x182a +#define mmDC_I2C_DDC5_SPEED 0x182b +#define mmDC_I2C_DDC5_SETUP 0x182c +#define mmDC_I2C_DDC6_SPEED 0x182d +#define mmDC_I2C_DDC6_SETUP 0x182e +#define mmDC_I2C_TRANSACTION0 0x182f +#define mmDC_I2C_TRANSACTION1 0x1830 +#define mmDC_I2C_TRANSACTION2 0x1831 +#define mmDC_I2C_TRANSACTION3 0x1832 +#define mmDC_I2C_DATA 0x1833 +#define mmGENERIC_I2C_CONTROL 0x1834 +#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835 +#define mmGENERIC_I2C_STATUS 0x1836 +#define mmGENERIC_I2C_SPEED 0x1837 +#define mmGENERIC_I2C_SETUP 0x1838 +#define mmGENERIC_I2C_TRANSACTION 0x1839 +#define mmGENERIC_I2C_DATA 0x183a +#define mmGENERIC_I2C_PIN_SELECTION 0x183b +#define mmGENERIC_I2C_PIN_DEBUG 0x183c +#define mmDISP_INTERRUPT_STATUS 0x183d +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183e +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183f +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854 +#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x19e0 +#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x19e1 +#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x19e2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x19e3 +#define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841 +#define mmDISP_TIMER_CONTROL 0x1842 +#define mmDC_I2C_DDCVGA_HW_STATUS 0x1855 +#define mmDC_I2C_DDCVGA_SPEED 0x1856 +#define mmDC_I2C_DDCVGA_SETUP 0x1857 +#define mmDC_I2C_EDID_DETECT_CTRL 0x186f +#define mmDISPOUT_STEREOSYNC_SEL 0x18bf +#define mmDOUT_TEST_DEBUG_INDEX 0x184d +#define mmDOUT_TEST_DEBUG_DATA 0x184e +#define ixDP_AUX1_DEBUG_A 0x10 +#define ixDP_AUX1_DEBUG_B 0x11 +#define ixDP_AUX1_DEBUG_C 0x12 +#define ixDP_AUX1_DEBUG_D 0x13 +#define ixDP_AUX1_DEBUG_E 0x14 +#define ixDP_AUX1_DEBUG_F 0x15 +#define ixDP_AUX1_DEBUG_G 0x16 +#define ixDP_AUX1_DEBUG_H 0x17 +#define ixDP_AUX1_DEBUG_I 0x18 +#define ixDP_AUX1_DEBUG_J 0x19 +#define ixDP_AUX1_DEBUG_K 0x1a +#define ixDP_AUX1_DEBUG_L 0x1b +#define ixDP_AUX1_DEBUG_M 0x1c +#define ixDP_AUX1_DEBUG_N 0x1d +#define ixDP_AUX1_DEBUG_O 0x1e +#define ixDP_AUX1_DEBUG_P 0x1f +#define ixDP_AUX1_DEBUG_Q 0x90 +#define ixDP_AUX2_DEBUG_A 0x20 +#define ixDP_AUX2_DEBUG_B 0x21 +#define ixDP_AUX2_DEBUG_C 0x22 +#define ixDP_AUX2_DEBUG_D 0x23 +#define ixDP_AUX2_DEBUG_E 0x24 +#define ixDP_AUX2_DEBUG_F 0x25 +#define ixDP_AUX2_DEBUG_G 0x26 +#define ixDP_AUX2_DEBUG_H 0x27 +#define ixDP_AUX2_DEBUG_I 0x28 +#define ixDP_AUX2_DEBUG_J 0x29 +#define ixDP_AUX2_DEBUG_K 0x2a +#define ixDP_AUX2_DEBUG_L 0x2b +#define ixDP_AUX2_DEBUG_M 0x2c +#define ixDP_AUX2_DEBUG_N 0x2d +#define ixDP_AUX2_DEBUG_O 0x2e +#define ixDP_AUX2_DEBUG_P 0x2f +#define ixDP_AUX2_DEBUG_Q 0x91 +#define ixDP_AUX3_DEBUG_A 0x30 +#define ixDP_AUX3_DEBUG_B 0x31 +#define ixDP_AUX3_DEBUG_C 0x32 +#define ixDP_AUX3_DEBUG_D 0x33 +#define ixDP_AUX3_DEBUG_E 0x34 +#define ixDP_AUX3_DEBUG_F 0x35 +#define ixDP_AUX3_DEBUG_G 0x36 +#define ixDP_AUX3_DEBUG_H 0x37 +#define ixDP_AUX3_DEBUG_I 0x38 +#define ixDP_AUX3_DEBUG_J 0x39 +#define ixDP_AUX3_DEBUG_K 0x3a +#define ixDP_AUX3_DEBUG_L 0x3b +#define ixDP_AUX3_DEBUG_M 0x3c +#define ixDP_AUX3_DEBUG_N 0x3d +#define ixDP_AUX3_DEBUG_O 0x3e +#define ixDP_AUX3_DEBUG_P 0x3f +#define ixDP_AUX3_DEBUG_Q 0x92 +#define ixDP_AUX4_DEBUG_A 0x40 +#define ixDP_AUX4_DEBUG_B 0x41 +#define ixDP_AUX4_DEBUG_C 0x42 +#define ixDP_AUX4_DEBUG_D 0x43 +#define ixDP_AUX4_DEBUG_E 0x44 +#define ixDP_AUX4_DEBUG_F 0x45 +#define ixDP_AUX4_DEBUG_G 0x46 +#define ixDP_AUX4_DEBUG_H 0x47 +#define ixDP_AUX4_DEBUG_I 0x48 +#define ixDP_AUX4_DEBUG_J 0x49 +#define ixDP_AUX4_DEBUG_K 0x4a +#define ixDP_AUX4_DEBUG_L 0x4b +#define ixDP_AUX4_DEBUG_M 0x4c +#define ixDP_AUX4_DEBUG_N 0x4d +#define ixDP_AUX4_DEBUG_O 0x4e +#define ixDP_AUX4_DEBUG_P 0x4f +#define ixDP_AUX4_DEBUG_Q 0x93 +#define ixDP_AUX5_DEBUG_A 0x70 +#define ixDP_AUX5_DEBUG_B 0x71 +#define ixDP_AUX5_DEBUG_C 0x72 +#define ixDP_AUX5_DEBUG_D 0x73 +#define ixDP_AUX5_DEBUG_E 0x74 +#define ixDP_AUX5_DEBUG_F 0x75 +#define ixDP_AUX5_DEBUG_G 0x76 +#define ixDP_AUX5_DEBUG_H 0x77 +#define ixDP_AUX5_DEBUG_I 0x78 +#define ixDP_AUX5_DEBUG_J 0x79 +#define ixDP_AUX5_DEBUG_K 0x7a +#define ixDP_AUX5_DEBUG_L 0x7b +#define ixDP_AUX5_DEBUG_M 0x7c +#define ixDP_AUX5_DEBUG_N 0x7d +#define ixDP_AUX5_DEBUG_O 0x7f +#define ixDP_AUX5_DEBUG_P 0x94 +#define ixDP_AUX5_DEBUG_Q 0x95 +#define ixDP_AUX6_DEBUG_A 0x80 +#define ixDP_AUX6_DEBUG_B 0x81 +#define ixDP_AUX6_DEBUG_C 0x82 +#define ixDP_AUX6_DEBUG_D 0x83 +#define ixDP_AUX6_DEBUG_E 0x84 +#define ixDP_AUX6_DEBUG_F 0x85 +#define ixDP_AUX6_DEBUG_G 0x86 +#define ixDP_AUX6_DEBUG_H 0x87 +#define ixDP_AUX6_DEBUG_I 0x88 +#define ixDP_AUX6_DEBUG_J 0x89 +#define ixDP_AUX6_DEBUG_K 0x8a +#define ixDP_AUX6_DEBUG_L 0x8b +#define ixDP_AUX6_DEBUG_M 0x8c +#define ixDP_AUX6_DEBUG_N 0x8d +#define ixDP_AUX6_DEBUG_O 0x8f +#define ixDP_AUX6_DEBUG_P 0x96 +#define ixDP_AUX6_DEBUG_Q 0x97 +#define mmDMCU_CTRL 0x1600 +#define mmDMCU_STATUS 0x1601 +#define mmDMCU_PC_START_ADDR 0x1602 +#define mmDMCU_FW_START_ADDR 0x1603 +#define mmDMCU_FW_END_ADDR 0x1604 +#define mmDMCU_FW_ISR_START_ADDR 0x1605 +#define mmDMCU_FW_CS_HI 0x1606 +#define mmDMCU_FW_CS_LO 0x1607 +#define mmDMCU_RAM_ACCESS_CTRL 0x1608 +#define mmDMCU_ERAM_WR_CTRL 0x1609 +#define mmDMCU_ERAM_WR_DATA 0x160a +#define mmDMCU_ERAM_RD_CTRL 0x160b +#define mmDMCU_ERAM_RD_DATA 0x160c +#define mmDMCU_IRAM_WR_CTRL 0x160d +#define mmDMCU_IRAM_WR_DATA 0x160e +#define mmDMCU_IRAM_RD_CTRL 0x160f +#define mmDMCU_IRAM_RD_DATA 0x1610 +#define mmDMCU_EVENT_TRIGGER 0x1611 +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 +#define mmDMCU_INTERRUPT_STATUS 0x1614 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 +#define mmDC_DMCU_SCRATCH 0x1618 +#define mmDMCU_INT_CNT 0x1619 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a +#define mmDMCU_UC_CLK_GATING_CNTL 0x161b +#define mmMASTER_COMM_DATA_REG1 0x161c +#define mmMASTER_COMM_DATA_REG2 0x161d +#define mmMASTER_COMM_DATA_REG3 0x161e +#define mmMASTER_COMM_CMD_REG 0x161f +#define mmMASTER_COMM_CNTL_REG 0x1620 +#define mmSLAVE_COMM_DATA_REG1 0x1621 +#define mmSLAVE_COMM_DATA_REG2 0x1622 +#define mmSLAVE_COMM_DATA_REG3 0x1623 +#define mmSLAVE_COMM_CMD_REG 0x1624 +#define mmSLAVE_COMM_CNTL_REG 0x1625 +#define mmDMCU_TEST_DEBUG_INDEX 0x1626 +#define mmDMCU_TEST_DEBUG_DATA 0x1627 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1750 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1751 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1752 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1753 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1754 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1755 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1756 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1757 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1758 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1759 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x175a +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x175b +#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x175c +#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x175d +#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x175e +#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x175f +#define mmDP_LINK_CNTL 0x1cc0 +#define mmDP0_DP_LINK_CNTL 0x1cc0 +#define mmDP1_DP_LINK_CNTL 0x1fc0 +#define mmDP2_DP_LINK_CNTL 0x42c0 +#define mmDP3_DP_LINK_CNTL 0x45c0 +#define mmDP4_DP_LINK_CNTL 0x48c0 +#define mmDP5_DP_LINK_CNTL 0x4bc0 +#define mmDP6_DP_LINK_CNTL 0x4ec0 +#define mmDP_PIXEL_FORMAT 0x1cc1 +#define mmDP0_DP_PIXEL_FORMAT 0x1cc1 +#define mmDP1_DP_PIXEL_FORMAT 0x1fc1 +#define mmDP2_DP_PIXEL_FORMAT 0x42c1 +#define mmDP3_DP_PIXEL_FORMAT 0x45c1 +#define mmDP4_DP_PIXEL_FORMAT 0x48c1 +#define mmDP5_DP_PIXEL_FORMAT 0x4bc1 +#define mmDP6_DP_PIXEL_FORMAT 0x4ec1 +#define mmDP_MSA_COLORIMETRY 0x1cda +#define mmDP0_DP_MSA_COLORIMETRY 0x1cda +#define mmDP1_DP_MSA_COLORIMETRY 0x1fda +#define mmDP2_DP_MSA_COLORIMETRY 0x42da +#define mmDP3_DP_MSA_COLORIMETRY 0x45da +#define mmDP4_DP_MSA_COLORIMETRY 0x48da +#define mmDP5_DP_MSA_COLORIMETRY 0x4bda +#define mmDP6_DP_MSA_COLORIMETRY 0x4eda +#define mmDP_CONFIG 0x1cc2 +#define mmDP0_DP_CONFIG 0x1cc2 +#define mmDP1_DP_CONFIG 0x1fc2 +#define mmDP2_DP_CONFIG 0x42c2 +#define mmDP3_DP_CONFIG 0x45c2 +#define mmDP4_DP_CONFIG 0x48c2 +#define mmDP5_DP_CONFIG 0x4bc2 +#define mmDP6_DP_CONFIG 0x4ec2 +#define mmDP_VID_STREAM_CNTL 0x1cc3 +#define mmDP0_DP_VID_STREAM_CNTL 0x1cc3 +#define mmDP1_DP_VID_STREAM_CNTL 0x1fc3 +#define mmDP2_DP_VID_STREAM_CNTL 0x42c3 +#define mmDP3_DP_VID_STREAM_CNTL 0x45c3 +#define mmDP4_DP_VID_STREAM_CNTL 0x48c3 +#define mmDP5_DP_VID_STREAM_CNTL 0x4bc3 +#define mmDP6_DP_VID_STREAM_CNTL 0x4ec3 +#define mmDP_STEER_FIFO 0x1cc4 +#define mmDP0_DP_STEER_FIFO 0x1cc4 +#define mmDP1_DP_STEER_FIFO 0x1fc4 +#define mmDP2_DP_STEER_FIFO 0x42c4 +#define mmDP3_DP_STEER_FIFO 0x45c4 +#define mmDP4_DP_STEER_FIFO 0x48c4 +#define mmDP5_DP_STEER_FIFO 0x4bc4 +#define mmDP6_DP_STEER_FIFO 0x4ec4 +#define mmDP_MSA_MISC 0x1cc5 +#define mmDP0_DP_MSA_MISC 0x1cc5 +#define mmDP1_DP_MSA_MISC 0x1fc5 +#define mmDP2_DP_MSA_MISC 0x42c5 +#define mmDP3_DP_MSA_MISC 0x45c5 +#define mmDP4_DP_MSA_MISC 0x48c5 +#define mmDP5_DP_MSA_MISC 0x4bc5 +#define mmDP6_DP_MSA_MISC 0x4ec5 +#define mmDP_VID_TIMING 0x1cc9 +#define mmDP0_DP_VID_TIMING 0x1cc9 +#define mmDP1_DP_VID_TIMING 0x1fc9 +#define mmDP2_DP_VID_TIMING 0x42c9 +#define mmDP3_DP_VID_TIMING 0x45c9 +#define mmDP4_DP_VID_TIMING 0x48c9 +#define mmDP5_DP_VID_TIMING 0x4bc9 +#define mmDP6_DP_VID_TIMING 0x4ec9 +#define mmDP_VID_N 0x1cca +#define mmDP0_DP_VID_N 0x1cca +#define mmDP1_DP_VID_N 0x1fca +#define mmDP2_DP_VID_N 0x42ca +#define mmDP3_DP_VID_N 0x45ca +#define mmDP4_DP_VID_N 0x48ca +#define mmDP5_DP_VID_N 0x4bca +#define mmDP6_DP_VID_N 0x4eca +#define mmDP_VID_M 0x1ccb +#define mmDP0_DP_VID_M 0x1ccb +#define mmDP1_DP_VID_M 0x1fcb +#define mmDP2_DP_VID_M 0x42cb +#define mmDP3_DP_VID_M 0x45cb +#define mmDP4_DP_VID_M 0x48cb +#define mmDP5_DP_VID_M 0x4bcb +#define mmDP6_DP_VID_M 0x4ecb +#define mmDP_LINK_FRAMING_CNTL 0x1ccc +#define mmDP0_DP_LINK_FRAMING_CNTL 0x1ccc +#define mmDP1_DP_LINK_FRAMING_CNTL 0x1fcc +#define mmDP2_DP_LINK_FRAMING_CNTL 0x42cc +#define mmDP3_DP_LINK_FRAMING_CNTL 0x45cc +#define mmDP4_DP_LINK_FRAMING_CNTL 0x48cc +#define mmDP5_DP_LINK_FRAMING_CNTL 0x4bcc +#define mmDP6_DP_LINK_FRAMING_CNTL 0x4ecc +#define mmDP_HBR2_EYE_PATTERN 0x1cc8 +#define mmDP0_DP_HBR2_EYE_PATTERN 0x1cc8 +#define mmDP1_DP_HBR2_EYE_PATTERN 0x1fc8 +#define mmDP2_DP_HBR2_EYE_PATTERN 0x42c8 +#define mmDP3_DP_HBR2_EYE_PATTERN 0x45c8 +#define mmDP4_DP_HBR2_EYE_PATTERN 0x48c8 +#define mmDP5_DP_HBR2_EYE_PATTERN 0x4bc8 +#define mmDP6_DP_HBR2_EYE_PATTERN 0x4ec8 +#define mmDP_VID_MSA_VBID 0x1ccd +#define mmDP0_DP_VID_MSA_VBID 0x1ccd +#define mmDP1_DP_VID_MSA_VBID 0x1fcd +#define mmDP2_DP_VID_MSA_VBID 0x42cd +#define mmDP3_DP_VID_MSA_VBID 0x45cd +#define mmDP4_DP_VID_MSA_VBID 0x48cd +#define mmDP5_DP_VID_MSA_VBID 0x4bcd +#define mmDP6_DP_VID_MSA_VBID 0x4ecd +#define mmDP_VID_INTERRUPT_CNTL 0x1ccf +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x1ccf +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1fcf +#define mmDP2_DP_VID_INTERRUPT_CNTL 0x42cf +#define mmDP3_DP_VID_INTERRUPT_CNTL 0x45cf +#define mmDP4_DP_VID_INTERRUPT_CNTL 0x48cf +#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4bcf +#define mmDP6_DP_VID_INTERRUPT_CNTL 0x4ecf +#define mmDP_DPHY_CNTL 0x1cd0 +#define mmDP0_DP_DPHY_CNTL 0x1cd0 +#define mmDP1_DP_DPHY_CNTL 0x1fd0 +#define mmDP2_DP_DPHY_CNTL 0x42d0 +#define mmDP3_DP_DPHY_CNTL 0x45d0 +#define mmDP4_DP_DPHY_CNTL 0x48d0 +#define mmDP5_DP_DPHY_CNTL 0x4bd0 +#define mmDP6_DP_DPHY_CNTL 0x4ed0 +#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1cd1 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1cd1 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1fd1 +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42d1 +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45d1 +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48d1 +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4bd1 +#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x4ed1 +#define mmDP_DPHY_SYM0 0x1cd2 +#define mmDP0_DP_DPHY_SYM0 0x1cd2 +#define mmDP1_DP_DPHY_SYM0 0x1fd2 +#define mmDP2_DP_DPHY_SYM0 0x42d2 +#define mmDP3_DP_DPHY_SYM0 0x45d2 +#define mmDP4_DP_DPHY_SYM0 0x48d2 +#define mmDP5_DP_DPHY_SYM0 0x4bd2 +#define mmDP6_DP_DPHY_SYM0 0x4ed2 +#define mmDP_DPHY_SYM1 0x1ce0 +#define mmDP0_DP_DPHY_SYM1 0x1ce0 +#define mmDP1_DP_DPHY_SYM1 0x1fe0 +#define mmDP2_DP_DPHY_SYM1 0x42e0 +#define mmDP3_DP_DPHY_SYM1 0x45e0 +#define mmDP4_DP_DPHY_SYM1 0x48e0 +#define mmDP5_DP_DPHY_SYM1 0x4be0 +#define mmDP6_DP_DPHY_SYM1 0x4ee0 +#define mmDP_DPHY_SYM2 0x1cdf +#define mmDP0_DP_DPHY_SYM2 0x1cdf +#define mmDP1_DP_DPHY_SYM2 0x1fdf +#define mmDP2_DP_DPHY_SYM2 0x42df +#define mmDP3_DP_DPHY_SYM2 0x45df +#define mmDP4_DP_DPHY_SYM2 0x48df +#define mmDP5_DP_DPHY_SYM2 0x4bdf +#define mmDP6_DP_DPHY_SYM2 0x4edf +#define mmDP_DPHY_8B10B_CNTL 0x1cd3 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x1cd3 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x1fd3 +#define mmDP2_DP_DPHY_8B10B_CNTL 0x42d3 +#define mmDP3_DP_DPHY_8B10B_CNTL 0x45d3 +#define mmDP4_DP_DPHY_8B10B_CNTL 0x48d3 +#define mmDP5_DP_DPHY_8B10B_CNTL 0x4bd3 +#define mmDP6_DP_DPHY_8B10B_CNTL 0x4ed3 +#define mmDP_DPHY_PRBS_CNTL 0x1cd4 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x1cd4 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x1fd4 +#define mmDP2_DP_DPHY_PRBS_CNTL 0x42d4 +#define mmDP3_DP_DPHY_PRBS_CNTL 0x45d4 +#define mmDP4_DP_DPHY_PRBS_CNTL 0x48d4 +#define mmDP5_DP_DPHY_PRBS_CNTL 0x4bd4 +#define mmDP6_DP_DPHY_PRBS_CNTL 0x4ed4 +#define mmDP_DPHY_CRC_EN 0x1cd6 +#define mmDP0_DP_DPHY_CRC_EN 0x1cd6 +#define mmDP1_DP_DPHY_CRC_EN 0x1fd6 +#define mmDP2_DP_DPHY_CRC_EN 0x42d6 +#define mmDP3_DP_DPHY_CRC_EN 0x45d6 +#define mmDP4_DP_DPHY_CRC_EN 0x48d6 +#define mmDP5_DP_DPHY_CRC_EN 0x4bd6 +#define mmDP6_DP_DPHY_CRC_EN 0x4ed6 +#define mmDP_DPHY_CRC_CNTL 0x1cd7 +#define mmDP0_DP_DPHY_CRC_CNTL 0x1cd7 +#define mmDP1_DP_DPHY_CRC_CNTL 0x1fd7 +#define mmDP2_DP_DPHY_CRC_CNTL 0x42d7 +#define mmDP3_DP_DPHY_CRC_CNTL 0x45d7 +#define mmDP4_DP_DPHY_CRC_CNTL 0x48d7 +#define mmDP5_DP_DPHY_CRC_CNTL 0x4bd7 +#define mmDP6_DP_DPHY_CRC_CNTL 0x4ed7 +#define mmDP_DPHY_CRC_RESULT 0x1cd8 +#define mmDP0_DP_DPHY_CRC_RESULT 0x1cd8 +#define mmDP1_DP_DPHY_CRC_RESULT 0x1fd8 +#define mmDP2_DP_DPHY_CRC_RESULT 0x42d8 +#define mmDP3_DP_DPHY_CRC_RESULT 0x45d8 +#define mmDP4_DP_DPHY_CRC_RESULT 0x48d8 +#define mmDP5_DP_DPHY_CRC_RESULT 0x4bd8 +#define mmDP6_DP_DPHY_CRC_RESULT 0x4ed8 +#define mmDP_DPHY_CRC_MST_CNTL 0x1cc6 +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1cc6 +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1fc6 +#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42c6 +#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45c6 +#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48c6 +#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4bc6 +#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x4ec6 +#define mmDP_DPHY_CRC_MST_STATUS 0x1cc7 +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1cc7 +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1fc7 +#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42c7 +#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45c7 +#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48c7 +#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4bc7 +#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x4ec7 +#define mmDP_DPHY_FAST_TRAINING 0x1cce +#define mmDP0_DP_DPHY_FAST_TRAINING 0x1cce +#define mmDP1_DP_DPHY_FAST_TRAINING 0x1fce +#define mmDP2_DP_DPHY_FAST_TRAINING 0x42ce +#define mmDP3_DP_DPHY_FAST_TRAINING 0x45ce +#define mmDP4_DP_DPHY_FAST_TRAINING 0x48ce +#define mmDP5_DP_DPHY_FAST_TRAINING 0x4bce +#define mmDP6_DP_DPHY_FAST_TRAINING 0x4ece +#define mmDP_DPHY_FAST_TRAINING_STATUS 0x1ce9 +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1ce9 +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1fe9 +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42e9 +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45e9 +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48e9 +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4be9 +#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x4ee9 +#define mmDP_MSA_V_TIMING_OVERRIDE1 0x1cea +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1cea +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1fea +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42ea +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45ea +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48ea +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4bea +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x4eea +#define mmDP_MSA_V_TIMING_OVERRIDE2 0x1ceb +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1ceb +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1feb +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42eb +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45eb +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48eb +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4beb +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x4eeb +#define mmDP_SEC_CNTL 0x1ca0 +#define mmDP0_DP_SEC_CNTL 0x1ca0 +#define mmDP1_DP_SEC_CNTL 0x1fa0 +#define mmDP2_DP_SEC_CNTL 0x42a0 +#define mmDP3_DP_SEC_CNTL 0x45a0 +#define mmDP4_DP_SEC_CNTL 0x48a0 +#define mmDP5_DP_SEC_CNTL 0x4ba0 +#define mmDP6_DP_SEC_CNTL 0x4ea0 +#define mmDP_SEC_CNTL1 0x1cab +#define mmDP0_DP_SEC_CNTL1 0x1cab +#define mmDP1_DP_SEC_CNTL1 0x1fab +#define mmDP2_DP_SEC_CNTL1 0x42ab +#define mmDP3_DP_SEC_CNTL1 0x45ab +#define mmDP4_DP_SEC_CNTL1 0x48ab +#define mmDP5_DP_SEC_CNTL1 0x4bab +#define mmDP6_DP_SEC_CNTL1 0x4eab +#define mmDP_SEC_FRAMING1 0x1ca1 +#define mmDP0_DP_SEC_FRAMING1 0x1ca1 +#define mmDP1_DP_SEC_FRAMING1 0x1fa1 +#define mmDP2_DP_SEC_FRAMING1 0x42a1 +#define mmDP3_DP_SEC_FRAMING1 0x45a1 +#define mmDP4_DP_SEC_FRAMING1 0x48a1 +#define mmDP5_DP_SEC_FRAMING1 0x4ba1 +#define mmDP6_DP_SEC_FRAMING1 0x4ea1 +#define mmDP_SEC_FRAMING2 0x1ca2 +#define mmDP0_DP_SEC_FRAMING2 0x1ca2 +#define mmDP1_DP_SEC_FRAMING2 0x1fa2 +#define mmDP2_DP_SEC_FRAMING2 0x42a2 +#define mmDP3_DP_SEC_FRAMING2 0x45a2 +#define mmDP4_DP_SEC_FRAMING2 0x48a2 +#define mmDP5_DP_SEC_FRAMING2 0x4ba2 +#define mmDP6_DP_SEC_FRAMING2 0x4ea2 +#define mmDP_SEC_FRAMING3 0x1ca3 +#define mmDP0_DP_SEC_FRAMING3 0x1ca3 +#define mmDP1_DP_SEC_FRAMING3 0x1fa3 +#define mmDP2_DP_SEC_FRAMING3 0x42a3 +#define mmDP3_DP_SEC_FRAMING3 0x45a3 +#define mmDP4_DP_SEC_FRAMING3 0x48a3 +#define mmDP5_DP_SEC_FRAMING3 0x4ba3 +#define mmDP6_DP_SEC_FRAMING3 0x4ea3 +#define mmDP_SEC_FRAMING4 0x1ca4 +#define mmDP0_DP_SEC_FRAMING4 0x1ca4 +#define mmDP1_DP_SEC_FRAMING4 0x1fa4 +#define mmDP2_DP_SEC_FRAMING4 0x42a4 +#define mmDP3_DP_SEC_FRAMING4 0x45a4 +#define mmDP4_DP_SEC_FRAMING4 0x48a4 +#define mmDP5_DP_SEC_FRAMING4 0x4ba4 +#define mmDP6_DP_SEC_FRAMING4 0x4ea4 +#define mmDP_SEC_AUD_N 0x1ca5 +#define mmDP0_DP_SEC_AUD_N 0x1ca5 +#define mmDP1_DP_SEC_AUD_N 0x1fa5 +#define mmDP2_DP_SEC_AUD_N 0x42a5 +#define mmDP3_DP_SEC_AUD_N 0x45a5 +#define mmDP4_DP_SEC_AUD_N 0x48a5 +#define mmDP5_DP_SEC_AUD_N 0x4ba5 +#define mmDP6_DP_SEC_AUD_N 0x4ea5 +#define mmDP_SEC_AUD_N_READBACK 0x1ca6 +#define mmDP0_DP_SEC_AUD_N_READBACK 0x1ca6 +#define mmDP1_DP_SEC_AUD_N_READBACK 0x1fa6 +#define mmDP2_DP_SEC_AUD_N_READBACK 0x42a6 +#define mmDP3_DP_SEC_AUD_N_READBACK 0x45a6 +#define mmDP4_DP_SEC_AUD_N_READBACK 0x48a6 +#define mmDP5_DP_SEC_AUD_N_READBACK 0x4ba6 +#define mmDP6_DP_SEC_AUD_N_READBACK 0x4ea6 +#define mmDP_SEC_AUD_M 0x1ca7 +#define mmDP0_DP_SEC_AUD_M 0x1ca7 +#define mmDP1_DP_SEC_AUD_M 0x1fa7 +#define mmDP2_DP_SEC_AUD_M 0x42a7 +#define mmDP3_DP_SEC_AUD_M 0x45a7 +#define mmDP4_DP_SEC_AUD_M 0x48a7 +#define mmDP5_DP_SEC_AUD_M 0x4ba7 +#define mmDP6_DP_SEC_AUD_M 0x4ea7 +#define mmDP_SEC_AUD_M_READBACK 0x1ca8 +#define mmDP0_DP_SEC_AUD_M_READBACK 0x1ca8 +#define mmDP1_DP_SEC_AUD_M_READBACK 0x1fa8 +#define mmDP2_DP_SEC_AUD_M_READBACK 0x42a8 +#define mmDP3_DP_SEC_AUD_M_READBACK 0x45a8 +#define mmDP4_DP_SEC_AUD_M_READBACK 0x48a8 +#define mmDP5_DP_SEC_AUD_M_READBACK 0x4ba8 +#define mmDP6_DP_SEC_AUD_M_READBACK 0x4ea8 +#define mmDP_SEC_TIMESTAMP 0x1ca9 +#define mmDP0_DP_SEC_TIMESTAMP 0x1ca9 +#define mmDP1_DP_SEC_TIMESTAMP 0x1fa9 +#define mmDP2_DP_SEC_TIMESTAMP 0x42a9 +#define mmDP3_DP_SEC_TIMESTAMP 0x45a9 +#define mmDP4_DP_SEC_TIMESTAMP 0x48a9 +#define mmDP5_DP_SEC_TIMESTAMP 0x4ba9 +#define mmDP6_DP_SEC_TIMESTAMP 0x4ea9 +#define mmDP_SEC_PACKET_CNTL 0x1caa +#define mmDP0_DP_SEC_PACKET_CNTL 0x1caa +#define mmDP1_DP_SEC_PACKET_CNTL 0x1faa +#define mmDP2_DP_SEC_PACKET_CNTL 0x42aa +#define mmDP3_DP_SEC_PACKET_CNTL 0x45aa +#define mmDP4_DP_SEC_PACKET_CNTL 0x48aa +#define mmDP5_DP_SEC_PACKET_CNTL 0x4baa +#define mmDP6_DP_SEC_PACKET_CNTL 0x4eaa +#define mmDP_MSE_RATE_CNTL 0x1ce1 +#define mmDP0_DP_MSE_RATE_CNTL 0x1ce1 +#define mmDP1_DP_MSE_RATE_CNTL 0x1fe1 +#define mmDP2_DP_MSE_RATE_CNTL 0x42e1 +#define mmDP3_DP_MSE_RATE_CNTL 0x45e1 +#define mmDP4_DP_MSE_RATE_CNTL 0x48e1 +#define mmDP5_DP_MSE_RATE_CNTL 0x4be1 +#define mmDP6_DP_MSE_RATE_CNTL 0x4ee1 +#define mmDP_MSE_RATE_UPDATE 0x1ce3 +#define mmDP0_DP_MSE_RATE_UPDATE 0x1ce3 +#define mmDP1_DP_MSE_RATE_UPDATE 0x1fe3 +#define mmDP2_DP_MSE_RATE_UPDATE 0x42e3 +#define mmDP3_DP_MSE_RATE_UPDATE 0x45e3 +#define mmDP4_DP_MSE_RATE_UPDATE 0x48e3 +#define mmDP5_DP_MSE_RATE_UPDATE 0x4be3 +#define mmDP6_DP_MSE_RATE_UPDATE 0x4ee3 +#define mmDP_MSE_SAT0 0x1ce4 +#define mmDP0_DP_MSE_SAT0 0x1ce4 +#define mmDP1_DP_MSE_SAT0 0x1fe4 +#define mmDP2_DP_MSE_SAT0 0x42e4 +#define mmDP3_DP_MSE_SAT0 0x45e4 +#define mmDP4_DP_MSE_SAT0 0x48e4 +#define mmDP5_DP_MSE_SAT0 0x4be4 +#define mmDP6_DP_MSE_SAT0 0x4ee4 +#define mmDP_MSE_SAT1 0x1ce5 +#define mmDP0_DP_MSE_SAT1 0x1ce5 +#define mmDP1_DP_MSE_SAT1 0x1fe5 +#define mmDP2_DP_MSE_SAT1 0x42e5 +#define mmDP3_DP_MSE_SAT1 0x45e5 +#define mmDP4_DP_MSE_SAT1 0x48e5 +#define mmDP5_DP_MSE_SAT1 0x4be5 +#define mmDP6_DP_MSE_SAT1 0x4ee5 +#define mmDP_MSE_SAT2 0x1ce6 +#define mmDP0_DP_MSE_SAT2 0x1ce6 +#define mmDP1_DP_MSE_SAT2 0x1fe6 +#define mmDP2_DP_MSE_SAT2 0x42e6 +#define mmDP3_DP_MSE_SAT2 0x45e6 +#define mmDP4_DP_MSE_SAT2 0x48e6 +#define mmDP5_DP_MSE_SAT2 0x4be6 +#define mmDP6_DP_MSE_SAT2 0x4ee6 +#define mmDP_MSE_SAT_UPDATE 0x1ce7 +#define mmDP0_DP_MSE_SAT_UPDATE 0x1ce7 +#define mmDP1_DP_MSE_SAT_UPDATE 0x1fe7 +#define mmDP2_DP_MSE_SAT_UPDATE 0x42e7 +#define mmDP3_DP_MSE_SAT_UPDATE 0x45e7 +#define mmDP4_DP_MSE_SAT_UPDATE 0x48e7 +#define mmDP5_DP_MSE_SAT_UPDATE 0x4be7 +#define mmDP6_DP_MSE_SAT_UPDATE 0x4ee7 +#define mmDP_MSE_LINK_TIMING 0x1ce8 +#define mmDP0_DP_MSE_LINK_TIMING 0x1ce8 +#define mmDP1_DP_MSE_LINK_TIMING 0x1fe8 +#define mmDP2_DP_MSE_LINK_TIMING 0x42e8 +#define mmDP3_DP_MSE_LINK_TIMING 0x45e8 +#define mmDP4_DP_MSE_LINK_TIMING 0x48e8 +#define mmDP5_DP_MSE_LINK_TIMING 0x4be8 +#define mmDP6_DP_MSE_LINK_TIMING 0x4ee8 +#define mmDP_MSE_MISC_CNTL 0x1cdb +#define mmDP0_DP_MSE_MISC_CNTL 0x1cdb +#define mmDP1_DP_MSE_MISC_CNTL 0x1fdb +#define mmDP2_DP_MSE_MISC_CNTL 0x42db +#define mmDP3_DP_MSE_MISC_CNTL 0x45db +#define mmDP4_DP_MSE_MISC_CNTL 0x48db +#define mmDP5_DP_MSE_MISC_CNTL 0x4bdb +#define mmDP6_DP_MSE_MISC_CNTL 0x4edb +#define mmDP_TEST_DEBUG_INDEX 0x1cfc +#define mmDP0_DP_TEST_DEBUG_INDEX 0x1cfc +#define mmDP1_DP_TEST_DEBUG_INDEX 0x1ffc +#define mmDP2_DP_TEST_DEBUG_INDEX 0x42fc +#define mmDP3_DP_TEST_DEBUG_INDEX 0x45fc +#define mmDP4_DP_TEST_DEBUG_INDEX 0x48fc +#define mmDP5_DP_TEST_DEBUG_INDEX 0x4bfc +#define mmDP6_DP_TEST_DEBUG_INDEX 0x4efc +#define mmDP_TEST_DEBUG_DATA 0x1cfd +#define mmDP0_DP_TEST_DEBUG_DATA 0x1cfd +#define mmDP1_DP_TEST_DEBUG_DATA 0x1ffd +#define mmDP2_DP_TEST_DEBUG_DATA 0x42fd +#define mmDP3_DP_TEST_DEBUG_DATA 0x45fd +#define mmDP4_DP_TEST_DEBUG_DATA 0x48fd +#define mmDP5_DP_TEST_DEBUG_DATA 0x4bfd +#define mmDP6_DP_TEST_DEBUG_DATA 0x4efd +#define mmAUX_CONTROL 0x1880 +#define mmDP_AUX0_AUX_CONTROL 0x1880 +#define mmDP_AUX1_AUX_CONTROL 0x1894 +#define mmDP_AUX2_AUX_CONTROL 0x18a8 +#define mmDP_AUX3_AUX_CONTROL 0x18c0 +#define mmDP_AUX4_AUX_CONTROL 0x18d4 +#define mmDP_AUX5_AUX_CONTROL 0x18e8 +#define mmAUX_SW_CONTROL 0x1881 +#define mmDP_AUX0_AUX_SW_CONTROL 0x1881 +#define mmDP_AUX1_AUX_SW_CONTROL 0x1895 +#define mmDP_AUX2_AUX_SW_CONTROL 0x18a9 +#define mmDP_AUX3_AUX_SW_CONTROL 0x18c1 +#define mmDP_AUX4_AUX_SW_CONTROL 0x18d5 +#define mmDP_AUX5_AUX_SW_CONTROL 0x18e9 +#define mmAUX_ARB_CONTROL 0x1882 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x1882 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x1896 +#define mmDP_AUX2_AUX_ARB_CONTROL 0x18aa +#define mmDP_AUX3_AUX_ARB_CONTROL 0x18c2 +#define mmDP_AUX4_AUX_ARB_CONTROL 0x18d6 +#define mmDP_AUX5_AUX_ARB_CONTROL 0x18ea +#define mmAUX_INTERRUPT_CONTROL 0x1883 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897 +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18ab +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18c3 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18d7 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18eb +#define mmAUX_SW_STATUS 0x1884 +#define mmDP_AUX0_AUX_SW_STATUS 0x1884 +#define mmDP_AUX1_AUX_SW_STATUS 0x1898 +#define mmDP_AUX2_AUX_SW_STATUS 0x18ac +#define mmDP_AUX3_AUX_SW_STATUS 0x18c4 +#define mmDP_AUX4_AUX_SW_STATUS 0x18d8 +#define mmDP_AUX5_AUX_SW_STATUS 0x18ec +#define mmAUX_LS_STATUS 0x1885 +#define mmDP_AUX0_AUX_LS_STATUS 0x1885 +#define mmDP_AUX1_AUX_LS_STATUS 0x1899 +#define mmDP_AUX2_AUX_LS_STATUS 0x18ad +#define mmDP_AUX3_AUX_LS_STATUS 0x18c5 +#define mmDP_AUX4_AUX_LS_STATUS 0x18d9 +#define mmDP_AUX5_AUX_LS_STATUS 0x18ed +#define mmAUX_SW_DATA 0x1886 +#define mmDP_AUX0_AUX_SW_DATA 0x1886 +#define mmDP_AUX1_AUX_SW_DATA 0x189a +#define mmDP_AUX2_AUX_SW_DATA 0x18ae +#define mmDP_AUX3_AUX_SW_DATA 0x18c6 +#define mmDP_AUX4_AUX_SW_DATA 0x18da +#define mmDP_AUX5_AUX_SW_DATA 0x18ee +#define mmAUX_LS_DATA 0x1887 +#define mmDP_AUX0_AUX_LS_DATA 0x1887 +#define mmDP_AUX1_AUX_LS_DATA 0x189b +#define mmDP_AUX2_AUX_LS_DATA 0x18af +#define mmDP_AUX3_AUX_LS_DATA 0x18c7 +#define mmDP_AUX4_AUX_LS_DATA 0x18db +#define mmDP_AUX5_AUX_LS_DATA 0x18ef +#define mmAUX_DPHY_TX_REF_CONTROL 0x1888 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189c +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18b0 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18c8 +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18dc +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18f0 +#define mmAUX_DPHY_TX_CONTROL 0x1889 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189d +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18b1 +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18c9 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18dd +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18f1 +#define mmAUX_DPHY_RX_CONTROL0 0x188a +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188a +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189e +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18b2 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18ca +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18de +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18f2 +#define mmAUX_DPHY_RX_CONTROL1 0x188b +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188b +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189f +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18b3 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18cb +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18df +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18f3 +#define mmAUX_DPHY_TX_STATUS 0x188c +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188c +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18a0 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18b4 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18cc +#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18e0 +#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18f4 +#define mmAUX_DPHY_RX_STATUS 0x188d +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188d +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18a1 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18b5 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18cd +#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18e1 +#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18f5 +#define mmAUX_GTC_SYNC_CONTROL 0x188e +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188e +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18a2 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18b6 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18ce +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18e2 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18f6 +#define mmAUX_GTC_SYNC_ERROR_CONTROL 0x188f +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x188f +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x18a3 +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x18b7 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x18cf +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x18e3 +#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x18f7 +#define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x1890 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1890 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18a4 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18b8 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18d0 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18e4 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18f8 +#define mmAUX_GTC_SYNC_STATUS 0x1891 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1891 +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x18a5 +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x18b9 +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x18d1 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x18e5 +#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x18f9 +#define mmAUX_GTC_SYNC_DATA 0x1892 +#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1892 +#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18a6 +#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18ba +#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18d2 +#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18e6 +#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18fa +#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893 +#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893 +#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18a7 +#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18bb +#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18d3 +#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18e7 +#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18fb +#define mmDVO_ENABLE 0x1858 +#define mmDVO_SOURCE_SELECT 0x1859 +#define mmDVO_OUTPUT 0x185a +#define mmDVO_CONTROL 0x185b +#define mmDVO_CRC_EN 0x185c +#define mmDVO_CRC2_SIG_MASK 0x185d +#define mmDVO_CRC2_SIG_RESULT 0x185e +#define mmDVO_FIFO_ERROR_STATUS 0x185f +#define mmFBC_CNTL 0x16d0 +#define mmFBC_IDLE_MASK 0x16d1 +#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16d2 +#define mmFBC_START_STOP_DELAY 0x16d3 +#define mmFBC_COMP_CNTL 0x16d4 +#define mmFBC_COMP_MODE 0x16d5 +#define mmFBC_DEBUG0 0x16d6 +#define mmFBC_DEBUG1 0x16d7 +#define mmFBC_DEBUG2 0x16d8 +#define mmFBC_IND_LUT0 0x16d9 +#define mmFBC_IND_LUT1 0x16da +#define mmFBC_IND_LUT2 0x16db +#define mmFBC_IND_LUT3 0x16dc +#define mmFBC_IND_LUT4 0x16dd +#define mmFBC_IND_LUT5 0x16de +#define mmFBC_IND_LUT6 0x16df +#define mmFBC_IND_LUT7 0x16e0 +#define mmFBC_IND_LUT8 0x16e1 +#define mmFBC_IND_LUT9 0x16e2 +#define mmFBC_IND_LUT10 0x16e3 +#define mmFBC_IND_LUT11 0x16e4 +#define mmFBC_IND_LUT12 0x16e5 +#define mmFBC_IND_LUT13 0x16e6 +#define mmFBC_IND_LUT14 0x16e7 +#define mmFBC_IND_LUT15 0x16e8 +#define mmFBC_CSM_REGION_OFFSET_01 0x16e9 +#define mmFBC_CSM_REGION_OFFSET_23 0x16ea +#define mmFBC_CLIENT_REGION_MASK 0x16eb +#define mmFBC_DEBUG_COMP 0x16ec +#define mmFBC_DEBUG_CSR 0x16ed +#define mmFBC_DEBUG_CSR_RDATA 0x16ee +#define mmFBC_DEBUG_CSR_WDATA 0x16ef +#define mmFBC_DEBUG_CSR_RDATA_HI 0x16f6 +#define mmFBC_DEBUG_CSR_WDATA_HI 0x16f7 +#define mmFBC_MISC 0x16f0 +#define mmFBC_STATUS 0x16f1 +#define mmFBC_TEST_DEBUG_INDEX 0x16f4 +#define mmFBC_TEST_DEBUG_DATA 0x16f5 +#define mmFMT_CLAMP_COMPONENT_R 0x1be8 +#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 +#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1ee8 +#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x41e8 +#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x44e8 +#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x47e8 +#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x4ae8 +#define mmFMT_CLAMP_COMPONENT_G 0x1be9 +#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 +#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1ee9 +#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x41e9 +#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x44e9 +#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x47e9 +#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x4ae9 +#define mmFMT_CLAMP_COMPONENT_B 0x1bea +#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea +#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1eea +#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x41ea +#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x44ea +#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x47ea +#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x4aea +#define mmFMT_DYNAMIC_EXP_CNTL 0x1bed +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1eed +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ed +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ed +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ed +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4aed +#define mmFMT_CONTROL 0x1bee +#define mmFMT0_FMT_CONTROL 0x1bee +#define mmFMT1_FMT_CONTROL 0x1eee +#define mmFMT2_FMT_CONTROL 0x41ee +#define mmFMT3_FMT_CONTROL 0x44ee +#define mmFMT4_FMT_CONTROL 0x47ee +#define mmFMT5_FMT_CONTROL 0x4aee +#define mmFMT_FORCE_OUTPUT_CNTL 0x1bef +#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef +#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1eef +#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41ef +#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44ef +#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47ef +#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4aef +#define mmFMT_FORCE_DATA_0_1 0x1bf0 +#define mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0 +#define mmFMT1_FMT_FORCE_DATA_0_1 0x1ef0 +#define mmFMT2_FMT_FORCE_DATA_0_1 0x41f0 +#define mmFMT3_FMT_FORCE_DATA_0_1 0x44f0 +#define mmFMT4_FMT_FORCE_DATA_0_1 0x47f0 +#define mmFMT5_FMT_FORCE_DATA_0_1 0x4af0 +#define mmFMT_FORCE_DATA_2_3 0x1bf1 +#define mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1 +#define mmFMT1_FMT_FORCE_DATA_2_3 0x1ef1 +#define mmFMT2_FMT_FORCE_DATA_2_3 0x41f1 +#define mmFMT3_FMT_FORCE_DATA_2_3 0x44f1 +#define mmFMT4_FMT_FORCE_DATA_2_3 0x47f1 +#define mmFMT5_FMT_FORCE_DATA_2_3 0x4af1 +#define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1ef2 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41f2 +#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44f2 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47f2 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4af2 +#define mmFMT_DITHER_RAND_R_SEED 0x1bf3 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1ef3 +#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41f3 +#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44f3 +#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47f3 +#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4af3 +#define mmFMT_DITHER_RAND_G_SEED 0x1bf4 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1ef4 +#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41f4 +#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44f4 +#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47f4 +#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4af4 +#define mmFMT_DITHER_RAND_B_SEED 0x1bf5 +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1ef5 +#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41f5 +#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44f5 +#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47f5 +#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4af5 +#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ef6 +#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 +#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44f6 +#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47f6 +#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4af6 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ef7 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44f7 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47f7 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4af7 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ef8 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44f8 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47f8 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4af8 +#define mmFMT_CLAMP_CNTL 0x1bf9 +#define mmFMT0_FMT_CLAMP_CNTL 0x1bf9 +#define mmFMT1_FMT_CLAMP_CNTL 0x1ef9 +#define mmFMT2_FMT_CLAMP_CNTL 0x41f9 +#define mmFMT3_FMT_CLAMP_CNTL 0x44f9 +#define mmFMT4_FMT_CLAMP_CNTL 0x47f9 +#define mmFMT5_FMT_CLAMP_CNTL 0x4af9 +#define mmFMT_CRC_CNTL 0x1bfa +#define mmFMT0_FMT_CRC_CNTL 0x1bfa +#define mmFMT1_FMT_CRC_CNTL 0x1efa +#define mmFMT2_FMT_CRC_CNTL 0x41fa +#define mmFMT3_FMT_CRC_CNTL 0x44fa +#define mmFMT4_FMT_CRC_CNTL 0x47fa +#define mmFMT5_FMT_CRC_CNTL 0x4afa +#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1efb +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44fb +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47fb +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4afb +#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1efc +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44fc +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47fc +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4afc +#define mmFMT_CRC_SIG_RED_GREEN 0x1bfd +#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd +#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1efd +#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41fd +#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44fd +#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47fd +#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4afd +#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1efe +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41fe +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44fe +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47fe +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4afe +#define mmFMT_DEBUG_CNTL 0x1bff +#define mmFMT0_FMT_DEBUG_CNTL 0x1bff +#define mmFMT1_FMT_DEBUG_CNTL 0x1eff +#define mmFMT2_FMT_DEBUG_CNTL 0x41ff +#define mmFMT3_FMT_DEBUG_CNTL 0x44ff +#define mmFMT4_FMT_DEBUG_CNTL 0x47ff +#define mmFMT5_FMT_DEBUG_CNTL 0x4aff +#define mmFMT_TEST_DEBUG_INDEX 0x1beb +#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb +#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1eeb +#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41eb +#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44eb +#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47eb +#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4aeb +#define mmFMT_TEST_DEBUG_DATA 0x1bec +#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec +#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1eec +#define mmFMT2_FMT_TEST_DEBUG_DATA 0x41ec +#define mmFMT3_FMT_TEST_DEBUG_DATA 0x44ec +#define mmFMT4_FMT_TEST_DEBUG_DATA 0x47ec +#define mmFMT5_FMT_TEST_DEBUG_DATA 0x4aec +#define ixFMT_DEBUG0 0x1 +#define ixFMT_DEBUG1 0x2 +#define ixFMT_DEBUG2 0x3 +#define ixFMT_DEBUG_ID 0x0 +#define mmLB_DATA_FORMAT 0x1ac0 +#define mmLB0_LB_DATA_FORMAT 0x1ac0 +#define mmLB1_LB_DATA_FORMAT 0x1dc0 +#define mmLB2_LB_DATA_FORMAT 0x40c0 +#define mmLB3_LB_DATA_FORMAT 0x43c0 +#define mmLB4_LB_DATA_FORMAT 0x46c0 +#define mmLB5_LB_DATA_FORMAT 0x49c0 +#define mmLB_MEMORY_CTRL 0x1ac1 +#define mmLB0_LB_MEMORY_CTRL 0x1ac1 +#define mmLB1_LB_MEMORY_CTRL 0x1dc1 +#define mmLB2_LB_MEMORY_CTRL 0x40c1 +#define mmLB3_LB_MEMORY_CTRL 0x43c1 +#define mmLB4_LB_MEMORY_CTRL 0x46c1 +#define mmLB5_LB_MEMORY_CTRL 0x49c1 +#define mmLB_MEMORY_SIZE_STATUS 0x1ac2 +#define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 +#define mmLB1_LB_MEMORY_SIZE_STATUS 0x1dc2 +#define mmLB2_LB_MEMORY_SIZE_STATUS 0x40c2 +#define mmLB3_LB_MEMORY_SIZE_STATUS 0x43c2 +#define mmLB4_LB_MEMORY_SIZE_STATUS 0x46c2 +#define mmLB5_LB_MEMORY_SIZE_STATUS 0x49c2 +#define mmLB_DESKTOP_HEIGHT 0x1ac3 +#define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 +#define mmLB1_LB_DESKTOP_HEIGHT 0x1dc3 +#define mmLB2_LB_DESKTOP_HEIGHT 0x40c3 +#define mmLB3_LB_DESKTOP_HEIGHT 0x43c3 +#define mmLB4_LB_DESKTOP_HEIGHT 0x46c3 +#define mmLB5_LB_DESKTOP_HEIGHT 0x49c3 +#define mmLB_VLINE_START_END 0x1ac4 +#define mmLB0_LB_VLINE_START_END 0x1ac4 +#define mmLB1_LB_VLINE_START_END 0x1dc4 +#define mmLB2_LB_VLINE_START_END 0x40c4 +#define mmLB3_LB_VLINE_START_END 0x43c4 +#define mmLB4_LB_VLINE_START_END 0x46c4 +#define mmLB5_LB_VLINE_START_END 0x49c4 +#define mmLB_VLINE2_START_END 0x1ac5 +#define mmLB0_LB_VLINE2_START_END 0x1ac5 +#define mmLB1_LB_VLINE2_START_END 0x1dc5 +#define mmLB2_LB_VLINE2_START_END 0x40c5 +#define mmLB3_LB_VLINE2_START_END 0x43c5 +#define mmLB4_LB_VLINE2_START_END 0x46c5 +#define mmLB5_LB_VLINE2_START_END 0x49c5 +#define mmLB_V_COUNTER 0x1ac6 +#define mmLB0_LB_V_COUNTER 0x1ac6 +#define mmLB1_LB_V_COUNTER 0x1dc6 +#define mmLB2_LB_V_COUNTER 0x40c6 +#define mmLB3_LB_V_COUNTER 0x43c6 +#define mmLB4_LB_V_COUNTER 0x46c6 +#define mmLB5_LB_V_COUNTER 0x49c6 +#define mmLB_SNAPSHOT_V_COUNTER 0x1ac7 +#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 +#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1dc7 +#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x40c7 +#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x43c7 +#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x46c7 +#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x49c7 +#define mmLB_INTERRUPT_MASK 0x1ac8 +#define mmLB0_LB_INTERRUPT_MASK 0x1ac8 +#define mmLB1_LB_INTERRUPT_MASK 0x1dc8 +#define mmLB2_LB_INTERRUPT_MASK 0x40c8 +#define mmLB3_LB_INTERRUPT_MASK 0x43c8 +#define mmLB4_LB_INTERRUPT_MASK 0x46c8 +#define mmLB5_LB_INTERRUPT_MASK 0x49c8 +#define mmLB_VLINE_STATUS 0x1ac9 +#define mmLB0_LB_VLINE_STATUS 0x1ac9 +#define mmLB1_LB_VLINE_STATUS 0x1dc9 +#define mmLB2_LB_VLINE_STATUS 0x40c9 +#define mmLB3_LB_VLINE_STATUS 0x43c9 +#define mmLB4_LB_VLINE_STATUS 0x46c9 +#define mmLB5_LB_VLINE_STATUS 0x49c9 +#define mmLB_VLINE2_STATUS 0x1aca +#define mmLB0_LB_VLINE2_STATUS 0x1aca +#define mmLB1_LB_VLINE2_STATUS 0x1dca +#define mmLB2_LB_VLINE2_STATUS 0x40ca +#define mmLB3_LB_VLINE2_STATUS 0x43ca +#define mmLB4_LB_VLINE2_STATUS 0x46ca +#define mmLB5_LB_VLINE2_STATUS 0x49ca +#define mmLB_VBLANK_STATUS 0x1acb +#define mmLB0_LB_VBLANK_STATUS 0x1acb +#define mmLB1_LB_VBLANK_STATUS 0x1dcb +#define mmLB2_LB_VBLANK_STATUS 0x40cb +#define mmLB3_LB_VBLANK_STATUS 0x43cb +#define mmLB4_LB_VBLANK_STATUS 0x46cb +#define mmLB5_LB_VBLANK_STATUS 0x49cb +#define mmLB_SYNC_RESET_SEL 0x1acc +#define mmLB0_LB_SYNC_RESET_SEL 0x1acc +#define mmLB1_LB_SYNC_RESET_SEL 0x1dcc +#define mmLB2_LB_SYNC_RESET_SEL 0x40cc +#define mmLB3_LB_SYNC_RESET_SEL 0x43cc +#define mmLB4_LB_SYNC_RESET_SEL 0x46cc +#define mmLB5_LB_SYNC_RESET_SEL 0x49cc +#define mmLB_BLACK_KEYER_R_CR 0x1acd +#define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd +#define mmLB1_LB_BLACK_KEYER_R_CR 0x1dcd +#define mmLB2_LB_BLACK_KEYER_R_CR 0x40cd +#define mmLB3_LB_BLACK_KEYER_R_CR 0x43cd +#define mmLB4_LB_BLACK_KEYER_R_CR 0x46cd +#define mmLB5_LB_BLACK_KEYER_R_CR 0x49cd +#define mmLB_BLACK_KEYER_G_Y 0x1ace +#define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace +#define mmLB1_LB_BLACK_KEYER_G_Y 0x1dce +#define mmLB2_LB_BLACK_KEYER_G_Y 0x40ce +#define mmLB3_LB_BLACK_KEYER_G_Y 0x43ce +#define mmLB4_LB_BLACK_KEYER_G_Y 0x46ce +#define mmLB5_LB_BLACK_KEYER_G_Y 0x49ce +#define mmLB_BLACK_KEYER_B_CB 0x1acf +#define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf +#define mmLB1_LB_BLACK_KEYER_B_CB 0x1dcf +#define mmLB2_LB_BLACK_KEYER_B_CB 0x40cf +#define mmLB3_LB_BLACK_KEYER_B_CB 0x43cf +#define mmLB4_LB_BLACK_KEYER_B_CB 0x46cf +#define mmLB5_LB_BLACK_KEYER_B_CB 0x49cf +#define mmLB_KEYER_COLOR_CTRL 0x1ad0 +#define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 +#define mmLB1_LB_KEYER_COLOR_CTRL 0x1dd0 +#define mmLB2_LB_KEYER_COLOR_CTRL 0x40d0 +#define mmLB3_LB_KEYER_COLOR_CTRL 0x43d0 +#define mmLB4_LB_KEYER_COLOR_CTRL 0x46d0 +#define mmLB5_LB_KEYER_COLOR_CTRL 0x49d0 +#define mmLB_KEYER_COLOR_R_CR 0x1ad1 +#define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 +#define mmLB1_LB_KEYER_COLOR_R_CR 0x1dd1 +#define mmLB2_LB_KEYER_COLOR_R_CR 0x40d1 +#define mmLB3_LB_KEYER_COLOR_R_CR 0x43d1 +#define mmLB4_LB_KEYER_COLOR_R_CR 0x46d1 +#define mmLB5_LB_KEYER_COLOR_R_CR 0x49d1 +#define mmLB_KEYER_COLOR_G_Y 0x1ad2 +#define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 +#define mmLB1_LB_KEYER_COLOR_G_Y 0x1dd2 +#define mmLB2_LB_KEYER_COLOR_G_Y 0x40d2 +#define mmLB3_LB_KEYER_COLOR_G_Y 0x43d2 +#define mmLB4_LB_KEYER_COLOR_G_Y 0x46d2 +#define mmLB5_LB_KEYER_COLOR_G_Y 0x49d2 +#define mmLB_KEYER_COLOR_B_CB 0x1ad3 +#define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 +#define mmLB1_LB_KEYER_COLOR_B_CB 0x1dd3 +#define mmLB2_LB_KEYER_COLOR_B_CB 0x40d3 +#define mmLB3_LB_KEYER_COLOR_B_CB 0x43d3 +#define mmLB4_LB_KEYER_COLOR_B_CB 0x46d3 +#define mmLB5_LB_KEYER_COLOR_B_CB 0x49d3 +#define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1dd4 +#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x40d4 +#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x43d4 +#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x46d4 +#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x49d4 +#define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1dd5 +#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x40d5 +#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x43d5 +#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x46d5 +#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x49d5 +#define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1dd6 +#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x40d6 +#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x43d6 +#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x46d6 +#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x49d6 +#define mmLB_BUFFER_LEVEL_STATUS 0x1ad7 +#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 +#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1dd7 +#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x40d7 +#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x43d7 +#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x46d7 +#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x49d7 +#define mmLB_BUFFER_URGENCY_CTRL 0x1ad8 +#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 +#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1dd8 +#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x40d8 +#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x43d8 +#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x46d8 +#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x49d8 +#define mmLB_BUFFER_URGENCY_STATUS 0x1ad9 +#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 +#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1dd9 +#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x40d9 +#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x43d9 +#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x46d9 +#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x49d9 +#define mmLB_BUFFER_STATUS 0x1ada +#define mmLB0_LB_BUFFER_STATUS 0x1ada +#define mmLB1_LB_BUFFER_STATUS 0x1dda +#define mmLB2_LB_BUFFER_STATUS 0x40da +#define mmLB3_LB_BUFFER_STATUS 0x43da +#define mmLB4_LB_BUFFER_STATUS 0x46da +#define mmLB5_LB_BUFFER_STATUS 0x49da +#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1ddc +#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc +#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43dc +#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46dc +#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49dc +#define mmMVP_AFR_FLIP_MODE 0x1ae0 +#define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 +#define mmLB1_MVP_AFR_FLIP_MODE 0x1de0 +#define mmLB2_MVP_AFR_FLIP_MODE 0x40e0 +#define mmLB3_MVP_AFR_FLIP_MODE 0x43e0 +#define mmLB4_MVP_AFR_FLIP_MODE 0x46e0 +#define mmLB5_MVP_AFR_FLIP_MODE 0x49e0 +#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1de1 +#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 +#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43e1 +#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46e1 +#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49e1 +#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1de2 +#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40e2 +#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43e2 +#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46e2 +#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49e2 +#define mmDC_MVP_LB_CONTROL 0x1ae3 +#define mmLB0_DC_MVP_LB_CONTROL 0x1ae3 +#define mmLB1_DC_MVP_LB_CONTROL 0x1de3 +#define mmLB2_DC_MVP_LB_CONTROL 0x40e3 +#define mmLB3_DC_MVP_LB_CONTROL 0x43e3 +#define mmLB4_DC_MVP_LB_CONTROL 0x46e3 +#define mmLB5_DC_MVP_LB_CONTROL 0x49e3 +#define mmLB_DEBUG 0x1ae4 +#define mmLB0_LB_DEBUG 0x1ae4 +#define mmLB1_LB_DEBUG 0x1de4 +#define mmLB2_LB_DEBUG 0x40e4 +#define mmLB3_LB_DEBUG 0x43e4 +#define mmLB4_LB_DEBUG 0x46e4 +#define mmLB5_LB_DEBUG 0x49e4 +#define mmLB_DEBUG2 0x1ae5 +#define mmLB0_LB_DEBUG2 0x1ae5 +#define mmLB1_LB_DEBUG2 0x1de5 +#define mmLB2_LB_DEBUG2 0x40e5 +#define mmLB3_LB_DEBUG2 0x43e5 +#define mmLB4_LB_DEBUG2 0x46e5 +#define mmLB5_LB_DEBUG2 0x49e5 +#define mmLB_DEBUG3 0x1ae6 +#define mmLB0_LB_DEBUG3 0x1ae6 +#define mmLB1_LB_DEBUG3 0x1de6 +#define mmLB2_LB_DEBUG3 0x40e6 +#define mmLB3_LB_DEBUG3 0x43e6 +#define mmLB4_LB_DEBUG3 0x46e6 +#define mmLB5_LB_DEBUG3 0x49e6 +#define mmLB_TEST_DEBUG_INDEX 0x1afe +#define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe +#define mmLB1_LB_TEST_DEBUG_INDEX 0x1dfe +#define mmLB2_LB_TEST_DEBUG_INDEX 0x40fe +#define mmLB3_LB_TEST_DEBUG_INDEX 0x43fe +#define mmLB4_LB_TEST_DEBUG_INDEX 0x46fe +#define mmLB5_LB_TEST_DEBUG_INDEX 0x49fe +#define mmLB_TEST_DEBUG_DATA 0x1aff +#define mmLB0_LB_TEST_DEBUG_DATA 0x1aff +#define mmLB1_LB_TEST_DEBUG_DATA 0x1dff +#define mmLB2_LB_TEST_DEBUG_DATA 0x40ff +#define mmLB3_LB_TEST_DEBUG_DATA 0x43ff +#define mmLB4_LB_TEST_DEBUG_DATA 0x46ff +#define mmLB5_LB_TEST_DEBUG_DATA 0x49ff +#define mmMVP_CONTROL1 0x1680 +#define mmMVP_CONTROL2 0x1681 +#define mmMVP_FIFO_CONTROL 0x1682 +#define mmMVP_FIFO_STATUS 0x1683 +#define mmMVP_SLAVE_STATUS 0x1684 +#define mmMVP_INBAND_CNTL_CAP 0x1685 +#define mmMVP_BLACK_KEYER 0x1686 +#define mmMVP_CRC_CNTL 0x1687 +#define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688 +#define mmMVP_CRC_RESULT_RED 0x1689 +#define mmMVP_CONTROL3 0x168a +#define mmMVP_RECEIVE_CNT_CNTL1 0x168b +#define mmMVP_RECEIVE_CNT_CNTL2 0x168c +#define mmMVP_DEBUG 0x168f +#define mmMVP_TEST_DEBUG_INDEX 0x168d +#define mmMVP_TEST_DEBUG_DATA 0x168e +#define ixMVP_DEBUG_12 0xc +#define ixMVP_DEBUG_13 0xd +#define ixMVP_DEBUG_14 0xe +#define ixMVP_DEBUG_15 0xf +#define ixMVP_DEBUG_16 0x10 +#define ixMVP_DEBUG_17 0x11 +#define mmSCL_COEF_RAM_SELECT 0x1b40 +#define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 +#define mmSCL1_SCL_COEF_RAM_SELECT 0x1e40 +#define mmSCL2_SCL_COEF_RAM_SELECT 0x4140 +#define mmSCL3_SCL_COEF_RAM_SELECT 0x4440 +#define mmSCL4_SCL_COEF_RAM_SELECT 0x4740 +#define mmSCL5_SCL_COEF_RAM_SELECT 0x4a40 +#define mmSCL_COEF_RAM_TAP_DATA 0x1b41 +#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 +#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1e41 +#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 +#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 +#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 +#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4a41 +#define mmSCL_MODE 0x1b42 +#define mmSCL0_SCL_MODE 0x1b42 +#define mmSCL1_SCL_MODE 0x1e42 +#define mmSCL2_SCL_MODE 0x4142 +#define mmSCL3_SCL_MODE 0x4442 +#define mmSCL4_SCL_MODE 0x4742 +#define mmSCL5_SCL_MODE 0x4a42 +#define mmSCL_TAP_CONTROL 0x1b43 +#define mmSCL0_SCL_TAP_CONTROL 0x1b43 +#define mmSCL1_SCL_TAP_CONTROL 0x1e43 +#define mmSCL2_SCL_TAP_CONTROL 0x4143 +#define mmSCL3_SCL_TAP_CONTROL 0x4443 +#define mmSCL4_SCL_TAP_CONTROL 0x4743 +#define mmSCL5_SCL_TAP_CONTROL 0x4a43 +#define mmSCL_CONTROL 0x1b44 +#define mmSCL0_SCL_CONTROL 0x1b44 +#define mmSCL1_SCL_CONTROL 0x1e44 +#define mmSCL2_SCL_CONTROL 0x4144 +#define mmSCL3_SCL_CONTROL 0x4444 +#define mmSCL4_SCL_CONTROL 0x4744 +#define mmSCL5_SCL_CONTROL 0x4a44 +#define mmSCL_BYPASS_CONTROL 0x1b45 +#define mmSCL0_SCL_BYPASS_CONTROL 0x1b45 +#define mmSCL1_SCL_BYPASS_CONTROL 0x1e45 +#define mmSCL2_SCL_BYPASS_CONTROL 0x4145 +#define mmSCL3_SCL_BYPASS_CONTROL 0x4445 +#define mmSCL4_SCL_BYPASS_CONTROL 0x4745 +#define mmSCL5_SCL_BYPASS_CONTROL 0x4a45 +#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1e46 +#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146 +#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446 +#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746 +#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4a46 +#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1e47 +#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147 +#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447 +#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747 +#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4a47 +#define mmSCL_HORZ_FILTER_CONTROL 0x1b48 +#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 +#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1e48 +#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x4148 +#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4448 +#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4748 +#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4a48 +#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1e49 +#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 +#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4449 +#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4749 +#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4a49 +#define mmSCL_HORZ_FILTER_INIT 0x1b4a +#define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a +#define mmSCL1_SCL_HORZ_FILTER_INIT 0x1e4a +#define mmSCL2_SCL_HORZ_FILTER_INIT 0x414a +#define mmSCL3_SCL_HORZ_FILTER_INIT 0x444a +#define mmSCL4_SCL_HORZ_FILTER_INIT 0x474a +#define mmSCL5_SCL_HORZ_FILTER_INIT 0x4a4a +#define mmSCL_VERT_FILTER_CONTROL 0x1b4b +#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b +#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1e4b +#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414b +#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444b +#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474b +#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4a4b +#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1e4c +#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414c +#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444c +#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474c +#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4a4c +#define mmSCL_VERT_FILTER_INIT 0x1b4d +#define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d +#define mmSCL1_SCL_VERT_FILTER_INIT 0x1e4d +#define mmSCL2_SCL_VERT_FILTER_INIT 0x414d +#define mmSCL3_SCL_VERT_FILTER_INIT 0x444d +#define mmSCL4_SCL_VERT_FILTER_INIT 0x474d +#define mmSCL5_SCL_VERT_FILTER_INIT 0x4a4d +#define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e +#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e +#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1e4e +#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x414e +#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x444e +#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x474e +#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4a4e +#define mmSCL_ROUND_OFFSET 0x1b4f +#define mmSCL0_SCL_ROUND_OFFSET 0x1b4f +#define mmSCL1_SCL_ROUND_OFFSET 0x1e4f +#define mmSCL2_SCL_ROUND_OFFSET 0x414f +#define mmSCL3_SCL_ROUND_OFFSET 0x444f +#define mmSCL4_SCL_ROUND_OFFSET 0x474f +#define mmSCL5_SCL_ROUND_OFFSET 0x4a4f +#define mmSCL_UPDATE 0x1b51 +#define mmSCL0_SCL_UPDATE 0x1b51 +#define mmSCL1_SCL_UPDATE 0x1e51 +#define mmSCL2_SCL_UPDATE 0x4151 +#define mmSCL3_SCL_UPDATE 0x4451 +#define mmSCL4_SCL_UPDATE 0x4751 +#define mmSCL5_SCL_UPDATE 0x4a51 +#define mmSCL_F_SHARP_CONTROL 0x1b53 +#define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 +#define mmSCL1_SCL_F_SHARP_CONTROL 0x1e53 +#define mmSCL2_SCL_F_SHARP_CONTROL 0x4153 +#define mmSCL3_SCL_F_SHARP_CONTROL 0x4453 +#define mmSCL4_SCL_F_SHARP_CONTROL 0x4753 +#define mmSCL5_SCL_F_SHARP_CONTROL 0x4a53 +#define mmSCL_ALU_CONTROL 0x1b54 +#define mmSCL0_SCL_ALU_CONTROL 0x1b54 +#define mmSCL1_SCL_ALU_CONTROL 0x1e54 +#define mmSCL2_SCL_ALU_CONTROL 0x4154 +#define mmSCL3_SCL_ALU_CONTROL 0x4454 +#define mmSCL4_SCL_ALU_CONTROL 0x4754 +#define mmSCL5_SCL_ALU_CONTROL 0x4a54 +#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1e55 +#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 +#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 +#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 +#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4a55 +#define mmVIEWPORT_START 0x1b5c +#define mmSCL0_VIEWPORT_START 0x1b5c +#define mmSCL1_VIEWPORT_START 0x1e5c +#define mmSCL2_VIEWPORT_START 0x415c +#define mmSCL3_VIEWPORT_START 0x445c +#define mmSCL4_VIEWPORT_START 0x475c +#define mmSCL5_VIEWPORT_START 0x4a5c +#define mmVIEWPORT_SIZE 0x1b5d +#define mmSCL0_VIEWPORT_SIZE 0x1b5d +#define mmSCL1_VIEWPORT_SIZE 0x1e5d +#define mmSCL2_VIEWPORT_SIZE 0x415d +#define mmSCL3_VIEWPORT_SIZE 0x445d +#define mmSCL4_VIEWPORT_SIZE 0x475d +#define mmSCL5_VIEWPORT_SIZE 0x4a5d +#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1e5e +#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415e +#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445e +#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475e +#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4a5e +#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1e5f +#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415f +#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445f +#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475f +#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4a5f +#define mmSCL_MODE_CHANGE_DET1 0x1b60 +#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 +#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1e60 +#define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160 +#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460 +#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760 +#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4a60 +#define mmSCL_MODE_CHANGE_DET2 0x1b61 +#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 +#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1e61 +#define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161 +#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461 +#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761 +#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4a61 +#define mmSCL_MODE_CHANGE_DET3 0x1b62 +#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 +#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1e62 +#define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162 +#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462 +#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762 +#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4a62 +#define mmSCL_MODE_CHANGE_MASK 0x1b63 +#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 +#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1e63 +#define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163 +#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463 +#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763 +#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4a63 +#define mmSCL_DEBUG2 0x1b69 +#define mmSCL0_SCL_DEBUG2 0x1b69 +#define mmSCL1_SCL_DEBUG2 0x1e69 +#define mmSCL2_SCL_DEBUG2 0x4169 +#define mmSCL3_SCL_DEBUG2 0x4469 +#define mmSCL4_SCL_DEBUG2 0x4769 +#define mmSCL5_SCL_DEBUG2 0x4a69 +#define mmSCL_DEBUG 0x1b6a +#define mmSCL0_SCL_DEBUG 0x1b6a +#define mmSCL1_SCL_DEBUG 0x1e6a +#define mmSCL2_SCL_DEBUG 0x416a +#define mmSCL3_SCL_DEBUG 0x446a +#define mmSCL4_SCL_DEBUG 0x476a +#define mmSCL5_SCL_DEBUG 0x4a6a +#define mmSCL_TEST_DEBUG_INDEX 0x1b6b +#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b +#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1e6b +#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416b +#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446b +#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476b +#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4a6b +#define mmSCL_TEST_DEBUG_DATA 0x1b6c +#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c +#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1e6c +#define mmSCL2_SCL_TEST_DEBUG_DATA 0x416c +#define mmSCL3_SCL_TEST_DEBUG_DATA 0x446c +#define mmSCL4_SCL_TEST_DEBUG_DATA 0x476c +#define mmSCL5_SCL_TEST_DEBUG_DATA 0x4a6c +#define mmGENMO_WT 0xf0 +#define mmGENMO_RD 0xf3 +#define mmGENENB 0xf0 +#define mmGENFC_WT 0xee +#define mmVGA0_GENFC_WT 0xee +#define mmVGA1_GENFC_WT 0xf6 +#define mmGENFC_RD 0xf2 +#define mmGENS0 0xf0 +#define mmGENS1 0xee +#define mmVGA0_GENS1 0xee +#define mmVGA1_GENS1 0xf6 +#define mmDAC_DATA 0xf2 +#define mmDAC_MASK 0xf1 +#define mmDAC_R_INDEX 0xf1 +#define mmDAC_W_INDEX 0xf2 +#define mmSEQ8_IDX 0xf1 +#define mmSEQ8_DATA 0xf1 +#define ixSEQ00 0x0 +#define ixSEQ01 0x1 +#define ixSEQ02 0x2 +#define ixSEQ03 0x3 +#define ixSEQ04 0x4 +#define mmCRTC8_IDX 0xed +#define mmVGA0_CRTC8_IDX 0xed +#define mmVGA1_CRTC8_IDX 0xf5 +#define mmCRTC8_DATA 0xed +#define mmVGA0_CRTC8_DATA 0xed +#define mmVGA1_CRTC8_DATA 0xf5 +#define ixCRT00 0x0 +#define ixCRT01 0x1 +#define ixCRT02 0x2 +#define ixCRT03 0x3 +#define ixCRT04 0x4 +#define ixCRT05 0x5 +#define ixCRT06 0x6 +#define ixCRT07 0x7 +#define ixCRT08 0x8 +#define ixCRT09 0x9 +#define ixCRT0A 0xa +#define ixCRT0B 0xb +#define ixCRT0C 0xc +#define ixCRT0D 0xd +#define ixCRT0E 0xe +#define ixCRT0F 0xf +#define ixCRT10 0x10 +#define ixCRT11 0x11 +#define ixCRT12 0x12 +#define ixCRT13 0x13 +#define ixCRT14 0x14 +#define ixCRT15 0x15 +#define ixCRT16 0x16 +#define ixCRT17 0x17 +#define ixCRT18 0x18 +#define ixCRT1E 0x1e +#define ixCRT1F 0x1f +#define ixCRT22 0x22 +#define mmGRPH8_IDX 0xf3 +#define mmGRPH8_DATA 0xf3 +#define ixGRA00 0x0 +#define ixGRA01 0x1 +#define ixGRA02 0x2 +#define ixGRA03 0x3 +#define ixGRA04 0x4 +#define ixGRA05 0x5 +#define ixGRA06 0x6 +#define ixGRA07 0x7 +#define ixGRA08 0x8 +#define mmATTRX 0xf0 +#define mmATTRDW 0xf0 +#define mmATTRDR 0xf0 +#define ixATTR00 0x0 +#define ixATTR01 0x1 +#define ixATTR02 0x2 +#define ixATTR03 0x3 +#define ixATTR04 0x4 +#define ixATTR05 0x5 +#define ixATTR06 0x6 +#define ixATTR07 0x7 +#define ixATTR08 0x8 +#define ixATTR09 0x9 +#define ixATTR0A 0xa +#define ixATTR0B 0xb +#define ixATTR0C 0xc +#define ixATTR0D 0xd +#define ixATTR0E 0xe +#define ixATTR0F 0xf +#define ixATTR10 0x10 +#define ixATTR11 0x11 +#define ixATTR12 0x12 +#define ixATTR13 0x13 +#define ixATTR14 0x14 +#define mmVGA_RENDER_CONTROL 0xc0 +#define mmVGA_SOURCE_SELECT 0xfc +#define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 +#define mmVGA_MODE_CONTROL 0xc2 +#define mmVGA_SURFACE_PITCH_SELECT 0xc3 +#define mmVGA_MEMORY_BASE_ADDRESS 0xc4 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 +#define mmVGA_HDP_CONTROL 0xca +#define mmVGA_CACHE_CONTROL 0xcb +#define mmD1VGA_CONTROL 0xcc +#define mmD2VGA_CONTROL 0xce +#define mmD3VGA_CONTROL 0xf8 +#define mmD4VGA_CONTROL 0xf9 +#define mmD5VGA_CONTROL 0xfa +#define mmD6VGA_CONTROL 0xfb +#define mmVGA_HW_DEBUG 0xcf +#define mmVGA_STATUS 0xd0 +#define mmVGA_INTERRUPT_CONTROL 0xd1 +#define mmVGA_STATUS_CLEAR 0xd2 +#define mmVGA_INTERRUPT_STATUS 0xd3 +#define mmVGA_MAIN_CONTROL 0xd4 +#define mmVGA_TEST_CONTROL 0xd5 +#define mmVGA_DEBUG_READBACK_INDEX 0xd6 +#define mmVGA_DEBUG_READBACK_DATA 0xd7 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x12 +#define mmVGA_MEM_READ_PAGE_ADDR 0x13 +#define mmVGA_TEST_DEBUG_INDEX 0xc5 +#define mmVGA_TEST_DEBUG_DATA 0xc7 +#define ixVGADCC_DBG_DCCIF_C 0x7e +#define mmBPHYC_DAC_MACRO_CNTL 0x19fd +#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19fe +#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1e30 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4a30 +#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1e31 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4a31 +#define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 +#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 +#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1e32 +#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x4132 +#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4432 +#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4732 +#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4a32 +#define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 +#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 +#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1e33 +#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133 +#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433 +#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733 +#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4a33 +#define mmDPG_PIPE_DPM_CONTROL 0x1b34 +#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 +#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1e34 +#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134 +#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434 +#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734 +#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4a34 +#define mmDPG_PIPE_STUTTER_CONTROL 0x1b35 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1e35 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4a35 +#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1e36 +#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 +#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436 +#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4a36 +#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1e37 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4a37 +#define mmDPG_REPEATER_PROGRAM 0x1b3a +#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a +#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1e3a +#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x413a +#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x443a +#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x473a +#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x4a3a +#define mmDPG_HW_DEBUG_A 0x1b3b +#define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b +#define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1e3b +#define mmDMIF_PG2_DPG_HW_DEBUG_A 0x413b +#define mmDMIF_PG3_DPG_HW_DEBUG_A 0x443b +#define mmDMIF_PG4_DPG_HW_DEBUG_A 0x473b +#define mmDMIF_PG5_DPG_HW_DEBUG_A 0x4a3b +#define mmDPG_HW_DEBUG_B 0x1b3c +#define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c +#define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1e3c +#define mmDMIF_PG2_DPG_HW_DEBUG_B 0x413c +#define mmDMIF_PG3_DPG_HW_DEBUG_B 0x443c +#define mmDMIF_PG4_DPG_HW_DEBUG_B 0x473c +#define mmDMIF_PG5_DPG_HW_DEBUG_B 0x4a3c +#define mmDPG_TEST_DEBUG_INDEX 0x1b38 +#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 +#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1e38 +#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138 +#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438 +#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738 +#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4a38 +#define mmDPG_TEST_DEBUG_DATA 0x1b39 +#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 +#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1e39 +#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139 +#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439 +#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739 +#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4a39 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17d2 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17d3 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17d5 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17d6 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17d7 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17d8 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17d9 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17da +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17db +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17dc +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17dd +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17de +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17d4 +#define mmAZALIA_F0_CODEC_DEBUG 0x17df +#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x17e1 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x17e2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x17e3 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x17e4 +#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x17e5 +#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x17e6 +#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x17e7 +#define mmGLOBAL_CAPABILITIES 0x0 +#define mmMINOR_VERSION 0x0 +#define mmMAJOR_VERSION 0x0 +#define mmOUTPUT_PAYLOAD_CAPABILITY 0x1 +#define mmINPUT_PAYLOAD_CAPABILITY 0x1 +#define mmGLOBAL_CONTROL 0x2 +#define mmWAKE_ENABLE 0x3 +#define mmSTATE_CHANGE_STATUS 0x3 +#define mmGLOBAL_STATUS 0x4 +#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define mmINTERRUPT_CONTROL 0x8 +#define mmINTERRUPT_STATUS 0x9 +#define mmWALL_CLOCK_COUNTER 0xc +#define mmSTREAM_SYNCHRONIZATION 0xe +#define mmCORB_LOWER_BASE_ADDRESS 0x10 +#define mmCORB_UPPER_BASE_ADDRESS 0x11 +#define mmCORB_WRITE_POINTER 0x12 +#define mmCORB_READ_POINTER 0x12 +#define mmCORB_CONTROL 0x13 +#define mmCORB_STATUS 0x13 +#define mmCORB_SIZE 0x13 +#define mmRIRB_LOWER_BASE_ADDRESS 0x14 +#define mmRIRB_UPPER_BASE_ADDRESS 0x15 +#define mmRIRB_WRITE_POINTER 0x16 +#define mmRESPONSE_INTERRUPT_COUNT 0x16 +#define mmRIRB_CONTROL 0x17 +#define mmRIRB_STATUS 0x17 +#define mmRIRB_SIZE 0x17 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 +#define mmIMMEDIATE_COMMAND_STATUS 0x1a +#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c +#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d +#define mmWALL_CLOCK_COUNTER_ALIAS 0x80c +#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 +#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 +#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 +#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 +#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 +#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 +#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 +#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 +#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAUDIO_DESCRIPTOR0 0x1 +#define ixAUDIO_DESCRIPTOR1 0x2 +#define ixAUDIO_DESCRIPTOR2 0x3 +#define ixAUDIO_DESCRIPTOR3 0x4 +#define ixAUDIO_DESCRIPTOR4 0x5 +#define ixAUDIO_DESCRIPTOR5 0x6 +#define ixAUDIO_DESCRIPTOR6 0x7 +#define ixAUDIO_DESCRIPTOR7 0x8 +#define ixAUDIO_DESCRIPTOR8 0x9 +#define ixAUDIO_DESCRIPTOR9 0xa +#define ixAUDIO_DESCRIPTOR10 0xb +#define ixAUDIO_DESCRIPTOR11 0xc +#define ixAUDIO_DESCRIPTOR12 0xd +#define ixAUDIO_DESCRIPTOR13 0xe +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 +#define ixSINK_DESCRIPTION0 0x5 +#define ixSINK_DESCRIPTION1 0x6 +#define ixSINK_DESCRIPTION2 0x7 +#define ixSINK_DESCRIPTION3 0x8 +#define ixSINK_DESCRIPTION4 0x9 +#define ixSINK_DESCRIPTION5 0xa +#define ixSINK_DESCRIPTION6 0xb +#define ixSINK_DESCRIPTION7 0xc +#define ixSINK_DESCRIPTION8 0xd +#define ixSINK_DESCRIPTION9 0xe +#define ixSINK_DESCRIPTION10 0xf +#define ixSINK_DESCRIPTION11 0x10 +#define ixSINK_DESCRIPTION12 0x11 +#define ixSINK_DESCRIPTION13 0x12 +#define ixSINK_DESCRIPTION14 0x13 +#define ixSINK_DESCRIPTION15 0x14 +#define ixSINK_DESCRIPTION16 0x15 +#define ixSINK_DESCRIPTION17 0x16 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17b9 +#define mmAZALIA_AUDIO_DTO 0x17ba +#define mmAZALIA_AUDIO_DTO_CONTROL 0x17bb +#define mmAZALIA_SCLK_CONTROL 0x17bc +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17bd +#define mmAZALIA_DATA_DMA_CONTROL 0x17be +#define mmAZALIA_BDL_DMA_CONTROL 0x17bf +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17c0 +#define mmAZALIA_CORB_DMA_CONTROL 0x17c1 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17c9 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17ca +#define mmAZALIA_GLOBAL_CAPABILITIES 0x17cb +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17cc +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17cd +#define mmAZALIA_CONTROLLER_DEBUG 0x17cf +#define mmAZALIA_CRC0_CONTROL0 0x17ae +#define mmAZALIA_CRC0_CONTROL1 0x17af +#define mmAZALIA_CRC0_CONTROL2 0x17b0 +#define mmAZALIA_CRC0_CONTROL3 0x17b1 +#define mmAZALIA_CRC0_RESULT 0x17b2 +#define ixAZALIA_CRC0_CHANNEL0 0x0 +#define ixAZALIA_CRC0_CHANNEL1 0x1 +#define ixAZALIA_CRC0_CHANNEL2 0x2 +#define ixAZALIA_CRC0_CHANNEL3 0x3 +#define ixAZALIA_CRC0_CHANNEL4 0x4 +#define ixAZALIA_CRC0_CHANNEL5 0x5 +#define ixAZALIA_CRC0_CHANNEL6 0x6 +#define ixAZALIA_CRC0_CHANNEL7 0x7 +#define mmAZALIA_CRC1_CONTROL0 0x17b3 +#define mmAZALIA_CRC1_CONTROL1 0x17b4 +#define mmAZALIA_CRC1_CONTROL2 0x17b5 +#define mmAZALIA_CRC1_CONTROL3 0x17b6 +#define mmAZALIA_CRC1_RESULT 0x17b7 +#define ixAZALIA_CRC1_CHANNEL0 0x0 +#define ixAZALIA_CRC1_CHANNEL1 0x1 +#define ixAZALIA_CRC1_CHANNEL2 0x2 +#define ixAZALIA_CRC1_CHANNEL3 0x3 +#define ixAZALIA_CRC1_CHANNEL4 0x4 +#define ixAZALIA_CRC1_CHANNEL5 0x5 +#define ixAZALIA_CRC1_CHANNEL6 0x6 +#define ixAZALIA_CRC1_CHANNEL7 0x7 +#define mmAZ_TEST_DEBUG_INDEX 0x17d0 +#define mmAZ_TEST_DEBUG_DATA 0x17d1 +#define mmAZALIA_STREAM_INDEX 0x17e8 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17e8 +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17ec +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17f0 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17f4 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17f8 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17fc +#define mmAZALIA_STREAM_DATA 0x17e9 +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17e9 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ed +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17f1 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17f5 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17f9 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17fd +#define ixAZALIA_FIFO_SIZE_CONTROL 0x0 +#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 +#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 +#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 +#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 +#define ixAZALIA_STREAM_DEBUG 0x5 +#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178c +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179e +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a4 +#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178d +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179f +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a5 +#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 +#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 +#define mmBLND_CONTROL 0x1b6d +#define mmBLND0_BLND_CONTROL 0x1b6d +#define mmBLND1_BLND_CONTROL 0x1e6d +#define mmBLND2_BLND_CONTROL 0x416d +#define mmBLND3_BLND_CONTROL 0x446d +#define mmBLND4_BLND_CONTROL 0x476d +#define mmBLND5_BLND_CONTROL 0x4a6d +#define mmSM_CONTROL2 0x1b6e +#define mmBLND0_SM_CONTROL2 0x1b6e +#define mmBLND1_SM_CONTROL2 0x1e6e +#define mmBLND2_SM_CONTROL2 0x416e +#define mmBLND3_SM_CONTROL2 0x446e +#define mmBLND4_SM_CONTROL2 0x476e +#define mmBLND5_SM_CONTROL2 0x4a6e +#define mmPTI_CONTROL 0x1b6f +#define mmBLND0_PTI_CONTROL 0x1b6f +#define mmBLND1_PTI_CONTROL 0x1e6f +#define mmBLND2_PTI_CONTROL 0x416f +#define mmBLND3_PTI_CONTROL 0x446f +#define mmBLND4_PTI_CONTROL 0x476f +#define mmBLND5_PTI_CONTROL 0x4a6f +#define mmBLND_UPDATE 0x1b70 +#define mmBLND0_BLND_UPDATE 0x1b70 +#define mmBLND1_BLND_UPDATE 0x1e70 +#define mmBLND2_BLND_UPDATE 0x4170 +#define mmBLND3_BLND_UPDATE 0x4470 +#define mmBLND4_BLND_UPDATE 0x4770 +#define mmBLND5_BLND_UPDATE 0x4a70 +#define mmBLND_UNDERFLOW_INTERRUPT 0x1b71 +#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 +#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1e71 +#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x4171 +#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4471 +#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4771 +#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4a71 +#define mmBLND_V_UPDATE_LOCK 0x1b73 +#define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 +#define mmBLND1_BLND_V_UPDATE_LOCK 0x1e73 +#define mmBLND2_BLND_V_UPDATE_LOCK 0x4173 +#define mmBLND3_BLND_V_UPDATE_LOCK 0x4473 +#define mmBLND4_BLND_V_UPDATE_LOCK 0x4773 +#define mmBLND5_BLND_V_UPDATE_LOCK 0x4a73 +#define mmBLND_REG_UPDATE_STATUS 0x1b77 +#define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 +#define mmBLND1_BLND_REG_UPDATE_STATUS 0x1e77 +#define mmBLND2_BLND_REG_UPDATE_STATUS 0x4177 +#define mmBLND3_BLND_REG_UPDATE_STATUS 0x4477 +#define mmBLND4_BLND_REG_UPDATE_STATUS 0x4777 +#define mmBLND5_BLND_REG_UPDATE_STATUS 0x4a77 +#define mmBLND_DEBUG 0x1b74 +#define mmBLND0_BLND_DEBUG 0x1b74 +#define mmBLND1_BLND_DEBUG 0x1e74 +#define mmBLND2_BLND_DEBUG 0x4174 +#define mmBLND3_BLND_DEBUG 0x4474 +#define mmBLND4_BLND_DEBUG 0x4774 +#define mmBLND5_BLND_DEBUG 0x4a74 +#define mmBLND_TEST_DEBUG_INDEX 0x1b75 +#define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 +#define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1e75 +#define mmBLND2_BLND_TEST_DEBUG_INDEX 0x4175 +#define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4475 +#define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4775 +#define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4a75 +#define mmBLND_TEST_DEBUG_DATA 0x1b76 +#define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 +#define mmBLND1_BLND_TEST_DEBUG_DATA 0x1e76 +#define mmBLND2_BLND_TEST_DEBUG_DATA 0x4176 +#define mmBLND3_BLND_TEST_DEBUG_DATA 0x4476 +#define mmBLND4_BLND_TEST_DEBUG_DATA 0x4776 +#define mmBLND5_BLND_TEST_DEBUG_DATA 0x4a76 +#define mmSI_ENABLE 0x4c00 +#define mmSI_EC_CONFIG 0x4c01 +#define mmCNV_MODE 0x4c02 +#define mmCNV_WINDOW_START 0x4c03 +#define mmCNV_WINDOW_SIZE 0x4c04 +#define mmCNV_UPDATE 0x4c05 +#define mmCNV_SOURCE_SIZE 0x4c06 +#define mmCNV_CSC_CONTROL 0x4c07 +#define mmCNV_CSC_C11_C12 0x4c08 +#define mmCNV_CSC_C13_C14 0x4c09 +#define mmCNV_CSC_C21_C22 0x4c0a +#define mmCNV_CSC_C23_C24 0x4c0b +#define mmCNV_CSC_C31_C32 0x4c0c +#define mmCNV_CSC_C33_C34 0x4c0d +#define mmCNV_CSC_ROUND_OFFSET_R 0x4c0e +#define mmCNV_CSC_ROUND_OFFSET_G 0x4c0f +#define mmCNV_CSC_ROUND_OFFSET_B 0x4c10 +#define mmCNV_CSC_CLAMP_R 0x4c11 +#define mmCNV_CSC_CLAMP_G 0x4c12 +#define mmCNV_CSC_CLAMP_B 0x4c13 +#define mmCNV_TEST_CNTL 0x4c14 +#define mmCNV_TEST_CRC_RED 0x4c15 +#define mmCNV_TEST_CRC_GREEN 0x4c16 +#define mmCNV_TEST_CRC_BLUE 0x4c17 +#define mmSI_DEBUG_CTRL 0x4c18 +#define mmSI_DBG_MODE 0x4c1b +#define mmSI_HARD_DEBUG 0x4c1c +#define mmCNV_TEST_DEBUG_INDEX 0x4c19 +#define mmCNV_TEST_DEBUG_DATA 0x4c1a +#define mmSISCL_COEF_RAM_SELECT 0x4c20 +#define mmSISCL_COEF_RAM_TAP_DATA 0x4c21 +#define mmSISCL_MODE 0x4c22 +#define mmSISCL_TAP_CONTROL 0x4c23 +#define mmSISCL_DEST_SIZE 0x4c24 +#define mmSISCL_HORZ_FILTER_SCALE_RATIO 0x4c25 +#define mmSISCL_HORZ_FILTER_INIT_Y_RGB 0x4c26 +#define mmSISCL_HORZ_FILTER_INIT_CBCR 0x4c27 +#define mmSISCL_VERT_FILTER_SCALE_RATIO 0x4c28 +#define mmSISCL_VERT_FILTER_INIT_Y_RGB 0x4c29 +#define mmSISCL_VERT_FILTER_INIT_CBCR 0x4c2a +#define mmSISCL_ROUND_OFFSET 0x4c2b +#define mmSISCL_CLAMP 0x4c2c +#define mmSISCL_OVERFLOW_STATUS 0x4c2d +#define mmSISCL_COEF_RAM_CONFLICT_STATUS 0x4c2e +#define mmSISCL_OUTSIDE_PIX_STRATEGY 0x4c2f +#define mmSISCL_TEST_CNTL 0x4c30 +#define mmSISCL_TEST_CRC_RED 0x4c31 +#define mmSISCL_TEST_CRC_GREEN 0x4c32 +#define mmSISCL_TEST_CRC_BLUE 0x4c33 +#define mmSISCL_BACKPRESSURE_CNT_EN 0x4c36 +#define mmSISCL_MCIF_BACKPRESSURE_CNT 0x4c37 +#define mmSISCL_TEST_DEBUG_INDEX 0x4c34 +#define mmSISCL_TEST_DEBUG_DATA 0x4c35 +#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 +#define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 +#define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 +#define mmXDMA_INTERRUPT 0x3e3 +#define mmXDMA_CLOCK_GATING_CNTL 0x3e4 +#define mmXDMA_MEM_POWER_CNTL 0x3e6 +#define mmXDMA_IF_BIF_STATUS 0x3e7 +#define mmXDMA_PERF_MEAS_STATUS 0x3e8 +#define mmXDMA_IF_STATUS 0x3e9 +#define mmXDMA_TEST_DEBUG_INDEX 0x3ea +#define mmXDMA_TEST_DEBUG_DATA 0x3eb +#define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 +#define mmXDMA_PG_CONTROL 0x3f9 +#define mmXDMA_PG_WDATA 0x3fa +#define mmXDMA_PG_STATUS 0x3fb +#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc +#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd + +#endif /* DCE_8_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h new file mode 100644 index 000000000000..8a2930734477 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h @@ -0,0 +1,13109 @@ +/* + * DCE_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_8_0_SH_MASK_H +#define DCE_8_0_SH_MASK_H + +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1 +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0 +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1 +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0 +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1 +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0 +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0 +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1 +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0 +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1 +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0 +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1 +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0 +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1 +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0 +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1 +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0 +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1 +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0 +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1 +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0 +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1 +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0 +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1 +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0 +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1 +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4 +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2 +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000 +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0 +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1 +#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000 +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1 +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0 +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100 +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8 +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000 +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14 +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000 +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x18 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x1f +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10 +#define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0xf +#define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x0 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x1 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS_MASK 0x2 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x4 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x2 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x8 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x3 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x10 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x20 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x40 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x300 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x8 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE_MASK 0xc00 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0xa +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x3000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0xc +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0xc000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0xe +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x30000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x10 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0xc0000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x12 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x300000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x14 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0xc00000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x16 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x3000000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x18 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x1c +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x1d +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000 +#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x1e +#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x1fff +#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x1fff +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x1fff +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0 +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000 +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x1fff +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0 +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000 +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11 +#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x1fff +#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0 +#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000 +#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10 +#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x1fff +#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x1fff +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0 +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x1fff +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0 +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000 +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000 +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000 +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x1fff +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x1fff +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1 +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x1fff +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10 +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1 +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x1fff +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1 +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1 +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1 +#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 +#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 +#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 +#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1 +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff +#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1 +#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0 +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2 +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1 +#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4 +#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2 +#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8 +#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3 +#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10 +#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4 +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20 +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000 +#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10 +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000 +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11 +#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000 +#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12 +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x1fff +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0 +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000 +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10 +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x1fff +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0 +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0 +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffff +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0 +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffff +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1 +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0 +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1 +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000 +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1 +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10 +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x1fff +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3 +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x1fff +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x100 +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x8 +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xf0000 +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x10 +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000 +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14 +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000 +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1 +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1 +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10 +#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1 +#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0 +#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100 +#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8 +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14 +#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1 +#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x1fff +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x1fff0000 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x1fff +#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x1fff +#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 +#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 +#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 +#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 +#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 +#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 +#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 +#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc +#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 +#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 +#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 +#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 +#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 +#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x1fff +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x1fff0000 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x1fff +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x1fff0000 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x1fff +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x1fff0000 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x1fff +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x1fff0000 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff +#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 +#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff +#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x1fff +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x1fff0000 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x1fff +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x1fff0000 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x1fff +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x1fff0000 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x1fff +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x1fff0000 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff +#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 +#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff +#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x1fff +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x1fff0000 +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x1fff +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x1fff0000 +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x1fff +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x1fff +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0 +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000 +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 +#define DAC_ENABLE__DAC_ENABLE_MASK 0x1 +#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1 +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3 +#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1 +#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0 +#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000 +#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x100 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x8 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14 +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14 +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x1000000 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x18 +#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff +#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0 +#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1 +#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10 +#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000 +#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18 +#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1 +#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0 +#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100 +#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3 +#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3 +#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0 +#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000 +#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10 +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0 +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000 +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17 +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18 +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3 +#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xf0 +#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x4 +#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00 +#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000 +#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff +#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define PERFMON_HI__PERFMON_HI_MASK 0xffff +#define PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000 +#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff +#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff +#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0 +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0 +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0 +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10 +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18 +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18 +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__DPREFCLK_CLOCK_EN_MASK 0x10 +#define DPREFCLK_CNTL__DPREFCLK_CLOCK_EN__SHIFT 0x4 +#define SCANIN_SOFT_RESET__SCANIN_SOFT_RESET_MASK 0x1 +#define SCANIN_SOFT_RESET__SCANIN_SOFT_RESET__SHIFT 0x0 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 +#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1 +#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0 +#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2 +#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1 +#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4 +#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2 +#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8 +#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3 +#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10 +#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4 +#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20 +#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5 +#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000 +#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0 +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10 +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4 +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20 +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x100 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x200 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x400 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x800 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x1000 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x2000 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE_MASK 0x4000 +#define DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE__SHIFT 0xe +#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x10000 +#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x100000 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000 +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x7000000 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000 +#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x1c +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK 0x1000 +#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT 0xc +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000 +#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1 +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30 +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4 +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1 +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30 +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30 +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1 +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0 +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0 +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000 +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000 +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x1 +#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x0 +#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x100 +#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700 +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff +#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0 +#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff +#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff +#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0 +#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff +#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0 +#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x2 +#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x4 +#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x8 +#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x3 +#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x10 +#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x4 +#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x2 +#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x4 +#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x8 +#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x3 +#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x10 +#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x4 +#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x2 +#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x4 +#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x8 +#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x3 +#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x10 +#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x4 +#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x2 +#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x4 +#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x8 +#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x3 +#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x10 +#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x4 +#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x2 +#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x4 +#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x8 +#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x3 +#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x10 +#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x4 +#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x2 +#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x4 +#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x8 +#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x3 +#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x10 +#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x4 +#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1 +#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 +#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2 +#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1 +#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4 +#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2 +#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8 +#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3 +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10 +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4 +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20 +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5 +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40 +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6 +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80 +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7 +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100 +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8 +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200 +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9 +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000 +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000 +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET_MASK 0x4000 +#define DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET_MASK 0x8000 +#define DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET__SHIFT 0xf +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x10 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8 +#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x1 +#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x0 +#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x2 +#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x1 +#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x4 +#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x2 +#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x8 +#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x3 +#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x10 +#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x4 +#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x20 +#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x5 +#define UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x40 +#define UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0x6 +#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1 +#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0 +#define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x2 +#define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x1 +#define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4 +#define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8 +#define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10 +#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4 +#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20 +#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5 +#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40 +#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6 +#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000 +#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10 +#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000 +#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11 +#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000 +#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12 +#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000 +#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13 +#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000 +#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14 +#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000 +#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15 +#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000 +#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18 +#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000 +#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19 +#define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x4000000 +#define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x1a +#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000 +#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b +#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000 +#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x1c +#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000 +#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x1d +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x7 +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x1f00 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8 +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x10000 +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x20000 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11 +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x40000 +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x7 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x1f00 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x10000 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x20000 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x40000 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x100000 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14 +#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x3000000 +#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18 +#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000 +#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x7 +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x1f00 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8 +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x10000 +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x20000 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11 +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x40000 +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x1000 +#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0xc +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c +#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff +#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0 +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000 +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000 +#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10 +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7 +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10 +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8 +#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000 +#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc +#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000 +#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000 +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10 +#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff +#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0 +#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000 +#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10 +#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000 +#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12 +#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000 +#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3 +#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x10 +#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x4 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10 +#define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000 +#define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14 +#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000 +#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16 +#define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000 +#define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18 +#define PLL_CNTL__PLL_RESET_MASK 0x1 +#define PLL_CNTL__PLL_RESET__SHIFT 0x0 +#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2 +#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1 +#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4 +#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2 +#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8 +#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3 +#define PLL_CNTL__PLL_VCOREF_MASK 0x30 +#define PLL_CNTL__PLL_VCOREF__SHIFT 0x4 +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40 +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6 +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80 +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7 +#define PLL_CNTL__PLL_CALREF_MASK 0x300 +#define PLL_CNTL__PLL_CALREF__SHIFT 0x8 +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400 +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa +#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800 +#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000 +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd +#define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000 +#define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe +#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000 +#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10 +#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000 +#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13 +#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000 +#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14 +#define PLL_CNTL__PLL_LOCKED_MASK 0x200000 +#define PLL_CNTL__PLL_LOCKED__SHIFT 0x15 +#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000 +#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18 +#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000 +#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a +#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f +#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0 +#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60 +#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5 +#define PLL_ANALOG__PLL_CP_MASK 0xf00 +#define PLL_ANALOG__PLL_CP__SHIFT 0x8 +#define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000 +#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc +#define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000 +#define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15 +#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000 +#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18 +#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1 +#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0 +#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e +#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1 +#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0 +#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5 +#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff +#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0 +#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000 +#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14 +#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000 +#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a +#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000 +#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c +#define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1 +#define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0 +#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2 +#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1 +#define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00 +#define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x8 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x3 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8 +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1 +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0 +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0 +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4 +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00 +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1 +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0 +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1 +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0 +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100 +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8 +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000 +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x1ff +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x0 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x10000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x10 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x60000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x11 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x100000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x14 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x200000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x15 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x400000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x16 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000 +#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x18 +#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x1ff +#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18 +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0xf +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x1f0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x4 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf0000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x10 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x20 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x5 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x40 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x6 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x80 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x7 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0xfff00 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x8 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x300000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x14 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x400000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x16 +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0 +#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3 +#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0 +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4 +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2 +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10 +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4 +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700 +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8 +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000 +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000 +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10 +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000 +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18 +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000 +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x3f +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0 +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x3f00 +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x700000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14 +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x7000000 +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18 +#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000 +#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0 +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0 +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000 +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10 +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff +#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11 +#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff +#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11 +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000 +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1 +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0 +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2 +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1 +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4 +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2 +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8 +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3 +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10 +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4 +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20 +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5 +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100 +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8 +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200 +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9 +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10 +#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3 +#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0 +#define MCIF_CONTROL__MCIF_SCANIN_DISABLE_MASK 0x8 +#define MCIF_CONTROL__MCIF_SCANIN_DISABLE__SHIFT 0x3 +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10 +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4 +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100 +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8 +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000 +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc +#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000 +#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10 +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000 +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00 +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0 +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0 +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0 +#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf +#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0 +#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0 +#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0xf +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x0 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x20 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x5 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x3c0 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x6 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x800 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0xb +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0xf000 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0xc +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x20000 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x11 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x3c0000 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x12 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x800000 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x17 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0xf000000 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x18 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x20000000 +#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x1d +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY_MASK 0xf +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY__SHIFT 0x0 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS_MASK 0x20 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS__SHIFT 0x5 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY_MASK 0x3c0 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY__SHIFT 0x6 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS_MASK 0x800 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS__SHIFT 0xb +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY_MASK 0xf000 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY__SHIFT 0xc +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS_MASK 0x20000 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS__SHIFT 0x11 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x3c0000 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x12 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x800000 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x17 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0xf000000 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x18 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x20000000 +#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x1d +#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY_MASK 0xf +#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY__SHIFT 0x0 +#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS_MASK 0x20 +#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS__SHIFT 0x5 +#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY_MASK 0x1ffff000 +#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY__SHIFT 0xc +#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x3 +#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x0 +#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0xc +#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x2 +#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x30 +#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x4 +#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0xc0 +#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x6 +#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x300 +#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x8 +#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0xc00 +#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0xa +#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x3000 +#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0xc +#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0xc000 +#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0xe +#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x30000 +#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x10 +#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0xc0000 +#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x12 +#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x300000 +#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x14 +#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0xc00000 +#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x16 +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x3000000 +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x18 +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0xc000000 +#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x1a +#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000 +#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x1c +#define DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE_MASK 0xc0000000 +#define DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE__SHIFT 0x1e +#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x3 +#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x0 +#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0xc +#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x2 +#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x30 +#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x4 +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0 +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20 +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5 +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40 +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6 +#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80 +#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7 +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100 +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200 +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9 +#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x400 +#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0xa +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800 +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb +#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x1000 +#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0xc +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000 +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd +#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x4000 +#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0xe +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000 +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15 +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000 +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16 +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000 +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17 +#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000 +#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18 +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000 +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b +#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x1 +#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x0 +#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x2 +#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x1 +#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x4 +#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x2 +#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x8 +#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x3 +#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x10 +#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x4 +#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x20 +#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x5 +#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x100 +#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x200 +#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x400 +#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x800 +#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0xb +#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x1000 +#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0xc +#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x2000 +#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0xd +#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x4000 +#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0xe +#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x8000 +#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0xf +#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x10000 +#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x10 +#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x20000 +#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x11 +#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x40000 +#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x12 +#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x80000 +#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x13 +#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x100000 +#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x14 +#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x200000 +#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x15 +#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x400000 +#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x16 +#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x800000 +#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x17 +#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x1000000 +#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x18 +#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x2000000 +#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x19 +#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x4000000 +#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x1a +#define DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE_MASK 0x8000000 +#define DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x1b +#define DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE_MASK 0x10000000 +#define DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x1c +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x1 +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x2 +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x4 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x2 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x8 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x3 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x10 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x20 +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x40 +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x6 +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x80 +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x7 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x100 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x8 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x200 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x9 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x400 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0xa +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x800 +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0xb +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000 +#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0xc +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0xc000 +#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0xe +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x30000 +#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x10 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc0000 +#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x12 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x300000 +#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x14 +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0xc00000 +#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x16 +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x3f +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x0 +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x700 +#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x8 +#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x10000 +#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x10 +#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x100000 +#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x14 +#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x200000 +#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x15 +#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x400000 +#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x16 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0xf +#define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x0 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_ENABLE_MASK 0x1 +#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_EN_MASK 0x10 +#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_ACK_MASK 0x20 +#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_SLICE_INT_EN_MASK 0x40 +#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_LOCK_MASK 0xf00 +#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_SW_INT_STATUS_MASK 0x2 +#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_BUF_MASK 0x70 +#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_BUFTAG_MASK 0xf00 +#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_LINE_MASK 0x1fff000 +#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_LINE__SHIFT 0xc +#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_NEXT_BUF_MASK 0x70000000 +#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_BUF_PITCH__MCIF_BUF_LUMA_PITCH_MASK 0xffff +#define MCIF_BUF_PITCH__MCIF_BUF_LUMA_PITCH__SHIFT 0x0 +#define MCIF_BUF_PITCH__MCIF_BUF_CHROMA_PITCH_MASK 0xffff0000 +#define MCIF_BUF_PITCH__MCIF_BUF_CHROMA_PITCH__SHIFT 0x10 +#define MCIF_BUF_1_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff +#define MCIF_BUF_1_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 +#define MCIF_BUF_2_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff +#define MCIF_BUF_2_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 +#define MCIF_BUF_3_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff +#define MCIF_BUF_3_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 +#define MCIF_BUF_4_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff +#define MCIF_BUF_4_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 +#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff +#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 +#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 +#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 +#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff +#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 +#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 +#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 +#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff +#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 +#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 +#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 +#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff +#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 +#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 +#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 +#define MCIF_BUF_1_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff +#define MCIF_BUF_1_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 +#define MCIF_BUF_2_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff +#define MCIF_BUF_2_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 +#define MCIF_BUF_3_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff +#define MCIF_BUF_3_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 +#define MCIF_BUF_4_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff +#define MCIF_BUF_4_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 +#define MCIF_BUF_1_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 +#define MCIF_BUF_1_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 +#define MCIF_BUF_1_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 +#define MCIF_BUF_1_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 +#define MCIF_BUF_1_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 +#define MCIF_BUF_1_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 +#define MCIF_BUF_1_STATUS__MCIF_BUF_DISABLE_MASK 0x10 +#define MCIF_BUF_1_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 +#define MCIF_BUF_1_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 +#define MCIF_BUF_1_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 +#define MCIF_BUF_1_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 +#define MCIF_BUF_1_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 +#define MCIF_BUF_1_STATUS__MCIF_BUF_MODE_MASK 0x80 +#define MCIF_BUF_1_STATUS__MCIF_BUF_MODE__SHIFT 0x7 +#define MCIF_BUF_1_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 +#define MCIF_BUF_1_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 +#define MCIF_BUF_1_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 +#define MCIF_BUF_1_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc +#define MCIF_BUF_1_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 +#define MCIF_BUF_1_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 +#define MCIF_BUF_2_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 +#define MCIF_BUF_2_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 +#define MCIF_BUF_2_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 +#define MCIF_BUF_2_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 +#define MCIF_BUF_2_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 +#define MCIF_BUF_2_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 +#define MCIF_BUF_2_STATUS__MCIF_BUF_DISABLE_MASK 0x10 +#define MCIF_BUF_2_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 +#define MCIF_BUF_2_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 +#define MCIF_BUF_2_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 +#define MCIF_BUF_2_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 +#define MCIF_BUF_2_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 +#define MCIF_BUF_2_STATUS__MCIF_BUF_MODE_MASK 0x80 +#define MCIF_BUF_2_STATUS__MCIF_BUF_MODE__SHIFT 0x7 +#define MCIF_BUF_2_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 +#define MCIF_BUF_2_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 +#define MCIF_BUF_2_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 +#define MCIF_BUF_2_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc +#define MCIF_BUF_2_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 +#define MCIF_BUF_2_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 +#define MCIF_BUF_3_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 +#define MCIF_BUF_3_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 +#define MCIF_BUF_3_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 +#define MCIF_BUF_3_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 +#define MCIF_BUF_3_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 +#define MCIF_BUF_3_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 +#define MCIF_BUF_3_STATUS__MCIF_BUF_DISABLE_MASK 0x10 +#define MCIF_BUF_3_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 +#define MCIF_BUF_3_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 +#define MCIF_BUF_3_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 +#define MCIF_BUF_3_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 +#define MCIF_BUF_3_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 +#define MCIF_BUF_3_STATUS__MCIF_BUF_MODE_MASK 0x80 +#define MCIF_BUF_3_STATUS__MCIF_BUF_MODE__SHIFT 0x7 +#define MCIF_BUF_3_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 +#define MCIF_BUF_3_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 +#define MCIF_BUF_3_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 +#define MCIF_BUF_3_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc +#define MCIF_BUF_3_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 +#define MCIF_BUF_3_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 +#define MCIF_BUF_4_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 +#define MCIF_BUF_4_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 +#define MCIF_BUF_4_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 +#define MCIF_BUF_4_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 +#define MCIF_BUF_4_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 +#define MCIF_BUF_4_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 +#define MCIF_BUF_4_STATUS__MCIF_BUF_DISABLE_MASK 0x10 +#define MCIF_BUF_4_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 +#define MCIF_BUF_4_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 +#define MCIF_BUF_4_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 +#define MCIF_BUF_4_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 +#define MCIF_BUF_4_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 +#define MCIF_BUF_4_STATUS__MCIF_BUF_MODE_MASK 0x80 +#define MCIF_BUF_4_STATUS__MCIF_BUF_MODE__SHIFT 0x7 +#define MCIF_BUF_4_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 +#define MCIF_BUF_4_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 +#define MCIF_BUF_4_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 +#define MCIF_BUF_4_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc +#define MCIF_BUF_4_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 +#define MCIF_BUF_4_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 +#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT0_ARBITRATION_SLICE_MASK 0x3 +#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT0_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT1_ARBITRATION_SLICE_MASK 0x30 +#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT1_ARBITRATION_SLICE__SHIFT 0x4 +#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT0_URGENCY_WATERMARK_MASK 0xffff +#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0 +#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000 +#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10 +#define DC_GENERICA__GENERICA_EN_MASK 0x1 +#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 +#define DC_GENERICA__GENERICA_SEL_MASK 0xf00 +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x8 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICB__GENERICB_EN_MASK 0x1 +#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 +#define DC_GENERICB__GENERICB_SEL_MASK 0xf00 +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0 +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30 +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1 +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10 +#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000 +#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11 +#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x3 +#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x0 +#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0xc +#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x2 +#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x30 +#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x4 +#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0xc0 +#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x6 +#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x300 +#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x8 +#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0xc00 +#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0xa +#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x3000 +#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0xc +#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0xc000 +#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0xe +#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x30000 +#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x10 +#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0xc0000 +#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x12 +#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x300000 +#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x14 +#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0xc00000 +#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x16 +#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x3000000 +#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x18 +#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0xc000000 +#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x1a +#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000 +#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x1c +#define DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE_MASK 0x3 +#define DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE__SHIFT 0x0 +#define DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE_MASK 0xc +#define DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE__SHIFT 0x2 +#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x1 +#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x2 +#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x1 +#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x4 +#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x2 +#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x8 +#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x3 +#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x10 +#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x20 +#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x40 +#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x80 +#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x7 +#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x100 +#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x200 +#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x400 +#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x800 +#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0xb +#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x1000 +#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0xc +#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x2000 +#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0xd +#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x4000 +#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0xe +#define DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS_MASK 0x8000 +#define DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS__SHIFT 0xf +#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x10000 +#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x10 +#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x20000 +#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x11 +#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x40000 +#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x12 +#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x80000 +#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x13 +#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x100000 +#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x14 +#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x200000 +#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x15 +#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x400000 +#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x16 +#define DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS_MASK 0x800000 +#define DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS__SHIFT 0x17 +#define DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS_MASK 0x1000000 +#define DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0 +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1 +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000 +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1 +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000 +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c +#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0xc +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400 +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa +#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x800 +#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0xb +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000 +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000 +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000 +#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000 +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x1f +#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x0 +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20 +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5 +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40 +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6 +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80 +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7 +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100 +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8 +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200 +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9 +#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x1000 +#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0xc +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10 +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11 +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12 +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13 +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14 +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15 +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d +#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x20 +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x5 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x40 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x6 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x80 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x7 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x100 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x8 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x200 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x9 +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x1000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0xc +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x10000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x10 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x20000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x11 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x40000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x12 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x80000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x13 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x100000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x14 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x200000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x15 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x1000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x18 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x2000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x19 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x4000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x1a +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x8000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x1b +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x1c +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x1d +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS_MASK 0x40000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS__SHIFT 0x1e +#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0xc0 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0xc00 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x1000 +#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0xc +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x2000 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x8000 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0xf +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x10000 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x40000 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x100000 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x14 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x200000 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x15 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x800000 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x17 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x2000000 +#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x19 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x8000000 +#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b +#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff +#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0 +#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff +#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0 +#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff +#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0 +#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff +#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0 +#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff +#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0 +#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff +#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0 +#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff +#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0 +#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff +#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0 +#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff +#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0 +#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff +#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0 +#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff +#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0 +#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff +#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0 +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0 +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff +#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0 +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000 +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000 +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000 +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000 +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000 +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000 +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10 +#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000 +#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000 +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1 +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8 +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1 +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1 +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x1000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x18 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x4000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x1a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e +#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000 +#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000 +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe +#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000 +#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4 +#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0xf +#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0 +#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0xf0 +#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4 +#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0xf00 +#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8 +#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0xf000 +#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc +#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x70000 +#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10 +#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x700000 +#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14 +#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x7000000 +#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18 +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000 +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000 +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d +#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1 +#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0 +#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2 +#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1 +#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0 +#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4 +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x3ff +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x0 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x10000 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x10 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0xe0000 +#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x11 +#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x7fffff +#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x0 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x3ff +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x0 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x10000 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x10 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0xe0000 +#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x11 +#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x7fffff +#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x0 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x3ff +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x0 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x10000 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x10 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0xe0000 +#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x11 +#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x7fffff +#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x0 +#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN_MASK 0x3ff +#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN__SHIFT 0x0 +#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN_MASK 0x10000 +#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN__SHIFT 0x10 +#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL_MASK 0xe0000 +#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL__SHIFT 0x11 +#define UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED_MASK 0x7fffff +#define UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0xf +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x10 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x20 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x40 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x80 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x100 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x200 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x400 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x800 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x1000 +#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0xf +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x10 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x20 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x40 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x80 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x100 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x200 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x400 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x800 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x1000 +#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0xf +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x10 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x20 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x40 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x80 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x100 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x200 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x400 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x800 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x1000 +#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0xf +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x10 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x20 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x40 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x80 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x100 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x200 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x400 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x800 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x1000 +#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x7 +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_MASK 0x700 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x70000 +#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_MASK 0x7000000 +#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH__SHIFT 0x18 +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x7000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x70000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17 +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000 +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18 +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000 +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0 +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2 +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1 +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x4 +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0 +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x1000 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0xc +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x1c +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a +#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x30000 +#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x10 +#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff +#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0 +#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 +#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 +#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 +#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 +#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc +#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 +#define GRPH_CONTROL__GRPH_Z_MASK 0x30 +#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4 +#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0 +#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6 +#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 +#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 +#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800 +#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb +#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000 +#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000 +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12 +#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 +#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 +#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 +#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 +#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000 +#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10 +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00 +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff +#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0 +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0 +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0 +#define GRPH_X_START__GRPH_X_START_MASK 0x3fff +#define GRPH_X_START__GRPH_X_START__SHIFT 0x0 +#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff +#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0 +#define GRPH_X_END__GRPH_X_END_MASK 0x7fff +#define GRPH_X_END__GRPH_X_END__SHIFT 0x0 +#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff +#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0 +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x3 +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0 +#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x30 +#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x4 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100 +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8 +#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 +#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 +#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 +#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0 +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0 +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0 +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6 +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define OVL_ENABLE__OVL_ENABLE_MASK 0x1 +#define OVL_ENABLE__OVL_ENABLE__SHIFT 0x0 +#define OVL_ENABLE__OVLSCL_EN_MASK 0x100 +#define OVL_ENABLE__OVLSCL_EN__SHIFT 0x8 +#define OVL_CONTROL1__OVL_DEPTH_MASK 0x3 +#define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x0 +#define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0xc +#define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x2 +#define OVL_CONTROL1__OVL_Z_MASK 0x30 +#define OVL_CONTROL1__OVL_Z__SHIFT 0x4 +#define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0xc0 +#define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x6 +#define OVL_CONTROL1__OVL_FORMAT_MASK 0x700 +#define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x8 +#define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x1800 +#define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0xb +#define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0xe000 +#define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0xd +#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 +#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 +#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 +#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 +#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0xc0000 +#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x12 +#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0xf00000 +#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x14 +#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x1000000 +#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x18 +#define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000 +#define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x19 +#define OVL_CONTROL1__OVL_MICRO_TILE_MODE_MASK 0xc0000000 +#define OVL_CONTROL1__OVL_MICRO_TILE_MODE__SHIFT 0x1e +#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x1 +#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x0 +#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x3 +#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x0 +#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x30 +#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x4 +#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0xc0 +#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x6 +#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x300 +#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x8 +#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0xc00 +#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0xa +#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x1 +#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x0 +#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00 +#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x8 +#define OVL_PITCH__OVL_PITCH_MASK 0x7fff +#define OVL_PITCH__OVL_PITCH__SHIFT 0x0 +#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0xff +#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x3fff +#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x0 +#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x3fff +#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x0 +#define OVL_START__OVL_Y_START_MASK 0x3fff +#define OVL_START__OVL_Y_START__SHIFT 0x0 +#define OVL_START__OVL_X_START_MASK 0x3fff0000 +#define OVL_START__OVL_X_START__SHIFT 0x10 +#define OVL_END__OVL_Y_END_MASK 0x7fff +#define OVL_END__OVL_Y_END__SHIFT 0x0 +#define OVL_END__OVL_X_END_MASK 0x7fff0000 +#define OVL_END__OVL_X_END__SHIFT 0x10 +#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x1 +#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x0 +#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x2 +#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x1 +#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x10000 +#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x10 +#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 +#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x8 +#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x1 +#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x0 +#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x70 +#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x4 +#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x700 +#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 +#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0xf +#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x0 +#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 +#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x100 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x8 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x200 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x9 +#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff +#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x3ff +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x0 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0xffc00 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0xa +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x14 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x1f +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x1 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x0 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x2 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x1 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x4 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x2 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x8 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x3 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x10 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x4 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0xffff +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x0 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x10 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0xffff +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x0 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x10 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0xffff +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x0 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x10 +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3 +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0 +#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x30 +#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x4 +#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff +#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0 +#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000 +#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10 +#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff +#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0 +#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000 +#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10 +#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff +#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0 +#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000 +#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10 +#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff +#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0 +#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000 +#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10 +#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff +#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0 +#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000 +#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10 +#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff +#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0 +#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000 +#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x70 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x4 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10 +#define DENORM_CONTROL__DENORM_MODE_MASK 0x7 +#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0 +#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10 +#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4 +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10 +#define KEY_CONTROL__KEY_SELECT_MASK 0x1 +#define KEY_CONTROL__KEY_SELECT__SHIFT 0x0 +#define KEY_CONTROL__KEY_MODE_MASK 0x6 +#define KEY_CONTROL__KEY_MODE__SHIFT 0x1 +#define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000 +#define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x1c +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0 +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000 +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10 +#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff +#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0 +#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000 +#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10 +#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff +#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0 +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000 +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10 +#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff +#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0 +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000 +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10 +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3 +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0 +#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x30 +#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x4 +#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300 +#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8 +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000 +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3 +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0 +#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x30 +#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x4 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6 +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100 +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8 +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200 +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9 +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400 +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0xff +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0 +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0xff00 +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8 +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0xff0000 +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 +#define CUR_CONTROL__CURSOR_EN_MASK 0x1 +#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0 +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10 +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4 +#define CUR_CONTROL__CURSOR_MODE_MASK 0x300 +#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000 +#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10 +#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000 +#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14 +#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000 +#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18 +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f +#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000 +#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff +#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000 +#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff +#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0 +#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00 +#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8 +#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000 +#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10 +#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff +#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0 +#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00 +#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8 +#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000 +#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10 +#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1 +#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0 +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2 +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1 +#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000 +#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10 +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000 +#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19 +#define CUR2_CONTROL__CURSOR2_EN_MASK 0x1 +#define CUR2_CONTROL__CURSOR2_EN__SHIFT 0x0 +#define CUR2_CONTROL__CUR2_INV_TRANS_CLAMP_MASK 0x10 +#define CUR2_CONTROL__CUR2_INV_TRANS_CLAMP__SHIFT 0x4 +#define CUR2_CONTROL__CURSOR2_MODE_MASK 0x300 +#define CUR2_CONTROL__CURSOR2_MODE__SHIFT 0x8 +#define CUR2_CONTROL__CURSOR2_2X_MAGNIFY_MASK 0x10000 +#define CUR2_CONTROL__CURSOR2_2X_MAGNIFY__SHIFT 0x10 +#define CUR2_CONTROL__CURSOR2_FORCE_MC_ON_MASK 0x100000 +#define CUR2_CONTROL__CURSOR2_FORCE_MC_ON__SHIFT 0x14 +#define CUR2_CONTROL__CURSOR2_URGENT_CONTROL_MASK 0x7000000 +#define CUR2_CONTROL__CURSOR2_URGENT_CONTROL__SHIFT 0x18 +#define CUR2_SURFACE_ADDRESS__CURSOR2_SURFACE_ADDRESS_MASK 0xffffffff +#define CUR2_SURFACE_ADDRESS__CURSOR2_SURFACE_ADDRESS__SHIFT 0x0 +#define CUR2_SIZE__CURSOR2_HEIGHT_MASK 0x7f +#define CUR2_SIZE__CURSOR2_HEIGHT__SHIFT 0x0 +#define CUR2_SIZE__CURSOR2_WIDTH_MASK 0x7f0000 +#define CUR2_SIZE__CURSOR2_WIDTH__SHIFT 0x10 +#define CUR2_SURFACE_ADDRESS_HIGH__CURSOR2_SURFACE_ADDRESS_HIGH_MASK 0xff +#define CUR2_SURFACE_ADDRESS_HIGH__CURSOR2_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CUR2_POSITION__CURSOR2_Y_POSITION_MASK 0x3fff +#define CUR2_POSITION__CURSOR2_Y_POSITION__SHIFT 0x0 +#define CUR2_POSITION__CURSOR2_X_POSITION_MASK 0x3fff0000 +#define CUR2_POSITION__CURSOR2_X_POSITION__SHIFT 0x10 +#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_Y_MASK 0x7f +#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_Y__SHIFT 0x0 +#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_X_MASK 0x7f0000 +#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_X__SHIFT 0x10 +#define CUR2_COLOR1__CUR2_COLOR1_BLUE_MASK 0xff +#define CUR2_COLOR1__CUR2_COLOR1_BLUE__SHIFT 0x0 +#define CUR2_COLOR1__CUR2_COLOR1_GREEN_MASK 0xff00 +#define CUR2_COLOR1__CUR2_COLOR1_GREEN__SHIFT 0x8 +#define CUR2_COLOR1__CUR2_COLOR1_RED_MASK 0xff0000 +#define CUR2_COLOR1__CUR2_COLOR1_RED__SHIFT 0x10 +#define CUR2_COLOR2__CUR2_COLOR2_BLUE_MASK 0xff +#define CUR2_COLOR2__CUR2_COLOR2_BLUE__SHIFT 0x0 +#define CUR2_COLOR2__CUR2_COLOR2_GREEN_MASK 0xff00 +#define CUR2_COLOR2__CUR2_COLOR2_GREEN__SHIFT 0x8 +#define CUR2_COLOR2__CUR2_COLOR2_RED_MASK 0xff0000 +#define CUR2_COLOR2__CUR2_COLOR2_RED__SHIFT 0x10 +#define CUR2_UPDATE__CURSOR2_UPDATE_PENDING_MASK 0x1 +#define CUR2_UPDATE__CURSOR2_UPDATE_PENDING__SHIFT 0x0 +#define CUR2_UPDATE__CURSOR2_UPDATE_TAKEN_MASK 0x2 +#define CUR2_UPDATE__CURSOR2_UPDATE_TAKEN__SHIFT 0x1 +#define CUR2_UPDATE__CURSOR2_UPDATE_LOCK_MASK 0x10000 +#define CUR2_UPDATE__CURSOR2_UPDATE_LOCK__SHIFT 0x10 +#define CUR2_UPDATE__CURSOR2_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define CUR2_UPDATE__CURSOR2_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define CUR2_UPDATE__CURSOR2_UPDATE_STEREO_MODE_MASK 0x6000000 +#define CUR2_UPDATE__CURSOR2_UPDATE_STEREO_MODE__SHIFT 0x19 +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1 +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1 +#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0 +#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000 +#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10 +#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_EN_MASK 0x1 +#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_EN__SHIFT 0x0 +#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_OFFSET_YNX_MASK 0x2 +#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_OFFSET_YNX__SHIFT 0x1 +#define CUR2_STEREO_CONTROL__CURSOR2_PRIMARY_OFFSET_MASK 0x3ff0 +#define CUR2_STEREO_CONTROL__CURSOR2_PRIMARY_OFFSET__SHIFT 0x4 +#define CUR2_STEREO_CONTROL__CURSOR2_SECONDARY_OFFSET_MASK 0x3ff0000 +#define CUR2_STEREO_CONTROL__CURSOR2_SECONDARY_OFFSET__SHIFT 0x10 +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1 +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0 +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0 +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0 +#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff +#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0 +#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000 +#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14 +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1 +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0 +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7 +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1 +#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf +#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6 +#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00 +#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe +#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000 +#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16 +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0 +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1 +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0 +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2 +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300 +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8 +#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff +#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0 +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0 +#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff +#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0 +#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff +#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3 +#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1 +#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0 +#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2 +#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1 +#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4 +#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2 +#define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x300 +#define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x8 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000 +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10 +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000 +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18 +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000 +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0 +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0xf0 +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x1 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x0 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x1 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x0 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x300 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x8 +#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x10000 +#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x10 +#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x20000 +#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x11 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c +#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8 +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c +#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff +#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0 +#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7 +#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4 +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7 +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0 +#define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x70 +#define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x4 +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0 +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0 +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7 +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1 +#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0 +#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2 +#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e +#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7 +#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70 +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100 +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG_FE_CNTL__DIG_START_MASK 0x400 +#define DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x10000 +#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x10 +#define DIG_FE_CNTL__DIG_SWAP_MASK 0x40000 +#define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x12 +#define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x100000 +#define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x14 +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000 +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2 +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x4 +#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x2 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x100 +#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x8 +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000 +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000 +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1 +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100 +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000 +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000 +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1 +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1 +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10 +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100 +#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200 +#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1 +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000 +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000 +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000 +#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1 +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000 +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 +#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1 +#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4 +#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10 +#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00 +#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000 +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7 +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40 +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80 +#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000 +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff +#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000 +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff +#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000 +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff +#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000 +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff +#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1 +#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2 +#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4 +#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38 +#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0 +#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00 +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000 +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000 +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000 +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000 +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0 +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000 +#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000 +#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000 +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000 +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10 +#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100 +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000 +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000 +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400 +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7 +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00 +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000 +#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000 +#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1 +#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100 +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1 +#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10 +#define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x4 +#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x300 +#define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x8 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3 +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1 +#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11 +#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000 +#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18 +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000 +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19 +#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1 +#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100 +#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000 +#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000 +#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70 +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x1 +#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x0 +#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x10 +#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x4 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x100 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x8 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x200 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x9 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x400 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0xa +#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x7000 +#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0xc +#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x10000 +#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x10 +#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x20000 +#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x11 +#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x40000 +#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x12 +#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1 +#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2 +#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4 +#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8 +#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100 +#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffff +#define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x0 +#define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffff +#define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x0 +#define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffff +#define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x0 +#define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffff +#define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x0 +#define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffff +#define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x0 +#define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffff +#define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x0 +#define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffff +#define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x0 +#define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffff +#define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x0 +#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7 +#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0 +#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70 +#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4 +#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x1 +#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x0 +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x2 +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x1 +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x10 +#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x4 +#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x100 +#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x8 +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 +#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x1 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x0 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x100 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x8 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x10000 +#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x10 +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x100000 +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x14 +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x1000000 +#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x18 +#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x1fff +#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x0 +#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x3ff0000 +#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x10 +#define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000 +#define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x1c +#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x1 +#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x0 +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x2 +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x1 +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x10 +#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x4 +#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x100 +#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x8 +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 +#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x1 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x0 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x100 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x8 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x10000 +#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x10 +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x100000 +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x14 +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x1000000 +#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x18 +#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x1fff +#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x0 +#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x3ff0000 +#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x10 +#define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000 +#define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x1c +#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x1 +#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x0 +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x2 +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x1 +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x10 +#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x4 +#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x100 +#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x8 +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 +#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x1 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x0 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x100 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x8 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x10000 +#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x10 +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x100000 +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x14 +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x1000000 +#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x18 +#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x1fff +#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x0 +#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x3ff0000 +#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x10 +#define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000 +#define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x1c +#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x1 +#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x0 +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x2 +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x1 +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x10 +#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x4 +#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x100 +#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x8 +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 +#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x1 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x0 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x100 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x8 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x10000 +#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x10 +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x100000 +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x14 +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x1000000 +#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x18 +#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x1fff +#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x0 +#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x3ff0000 +#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x10 +#define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000 +#define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x1c +#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x1 +#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x0 +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x2 +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x1 +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x10 +#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x4 +#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x100 +#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x8 +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 +#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x1 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x0 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x100 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x8 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x10000 +#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x10 +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x100000 +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x14 +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x1000000 +#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x18 +#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x1fff +#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x0 +#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x3ff0000 +#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x10 +#define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000 +#define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x1c +#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x1 +#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x0 +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x2 +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x1 +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x10 +#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x4 +#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x100 +#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x8 +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 +#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x1 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x0 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x100 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x8 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x10000 +#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x10 +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x100000 +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x14 +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x1000000 +#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x18 +#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x1fff +#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x0 +#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x3ff0000 +#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x10 +#define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000 +#define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x1c +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0xff +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x1000000 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 +#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0xff +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x1000000 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 +#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0xff +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x1000000 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 +#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0xff +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x1000000 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 +#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0xff +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x1000000 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 +#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0xff +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x1000000 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 +#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0xff +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x0 +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0xff00000 +#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0xff +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x0 +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0xff00000 +#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0xff +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x0 +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0xff00000 +#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0xff +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x0 +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0xff00000 +#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0xff +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x0 +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0xff00000 +#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0xff +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x0 +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0xff00000 +#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1 +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000 +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000 +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000 +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000 +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000 +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1 +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3 +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1 +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100 +#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x8000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x1b +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7 +#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0 +#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000 +#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10 +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0xff +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffff +#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x0 +#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffff +#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x0 +#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffff +#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x0 +#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffff +#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x0 +#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffff +#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x0 +#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffff +#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x0 +#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffff +#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x0 +#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffff +#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x0 +#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffff +#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x0 +#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffff +#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x0 +#define DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J_MASK 0xffffffff +#define DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J__SHIFT 0x0 +#define DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K_MASK 0xffffffff +#define DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K__SHIFT 0x0 +#define DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L_MASK 0xffffffff +#define DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L__SHIFT 0x0 +#define DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M_MASK 0xffffffff +#define DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M__SHIFT 0x0 +#define DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N_MASK 0xffffffff +#define DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N__SHIFT 0x0 +#define DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O_MASK 0xffffffff +#define DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O__SHIFT 0x0 +#define DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P_MASK 0xffffffff +#define DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P__SHIFT 0x0 +#define DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q_MASK 0xffffffff +#define DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q__SHIFT 0x0 +#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffff +#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x0 +#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffff +#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x0 +#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffff +#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x0 +#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffff +#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x0 +#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffff +#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x0 +#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffff +#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x0 +#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffff +#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x0 +#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffff +#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x0 +#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffff +#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x0 +#define DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J_MASK 0xffffffff +#define DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J__SHIFT 0x0 +#define DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K_MASK 0xffffffff +#define DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K__SHIFT 0x0 +#define DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L_MASK 0xffffffff +#define DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L__SHIFT 0x0 +#define DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M_MASK 0xffffffff +#define DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M__SHIFT 0x0 +#define DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N_MASK 0xffffffff +#define DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N__SHIFT 0x0 +#define DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O_MASK 0xffffffff +#define DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O__SHIFT 0x0 +#define DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P_MASK 0xffffffff +#define DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P__SHIFT 0x0 +#define DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q_MASK 0xffffffff +#define DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q__SHIFT 0x0 +#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffff +#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x0 +#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffff +#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x0 +#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffff +#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x0 +#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffff +#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x0 +#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffff +#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x0 +#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffff +#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x0 +#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffff +#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x0 +#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffff +#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x0 +#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffff +#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x0 +#define DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J_MASK 0xffffffff +#define DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J__SHIFT 0x0 +#define DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K_MASK 0xffffffff +#define DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K__SHIFT 0x0 +#define DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L_MASK 0xffffffff +#define DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L__SHIFT 0x0 +#define DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M_MASK 0xffffffff +#define DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M__SHIFT 0x0 +#define DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N_MASK 0xffffffff +#define DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N__SHIFT 0x0 +#define DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O_MASK 0xffffffff +#define DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O__SHIFT 0x0 +#define DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P_MASK 0xffffffff +#define DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P__SHIFT 0x0 +#define DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q_MASK 0xffffffff +#define DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q__SHIFT 0x0 +#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffff +#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x0 +#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffff +#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x0 +#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffff +#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x0 +#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffff +#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x0 +#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffff +#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x0 +#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffff +#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x0 +#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffff +#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x0 +#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffff +#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x0 +#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffff +#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x0 +#define DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J_MASK 0xffffffff +#define DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J__SHIFT 0x0 +#define DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K_MASK 0xffffffff +#define DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K__SHIFT 0x0 +#define DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L_MASK 0xffffffff +#define DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L__SHIFT 0x0 +#define DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M_MASK 0xffffffff +#define DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M__SHIFT 0x0 +#define DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N_MASK 0xffffffff +#define DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N__SHIFT 0x0 +#define DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O_MASK 0xffffffff +#define DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O__SHIFT 0x0 +#define DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P_MASK 0xffffffff +#define DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P__SHIFT 0x0 +#define DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q_MASK 0xffffffff +#define DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q__SHIFT 0x0 +#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffff +#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x0 +#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffff +#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x0 +#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffff +#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x0 +#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffff +#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x0 +#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffff +#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x0 +#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffff +#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x0 +#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffff +#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x0 +#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffff +#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x0 +#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffff +#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x0 +#define DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J_MASK 0xffffffff +#define DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J__SHIFT 0x0 +#define DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K_MASK 0xffffffff +#define DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K__SHIFT 0x0 +#define DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L_MASK 0xffffffff +#define DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L__SHIFT 0x0 +#define DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M_MASK 0xffffffff +#define DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M__SHIFT 0x0 +#define DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N_MASK 0xffffffff +#define DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N__SHIFT 0x0 +#define DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O_MASK 0xffffffff +#define DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O__SHIFT 0x0 +#define DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P_MASK 0xffffffff +#define DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P__SHIFT 0x0 +#define DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q_MASK 0xffffffff +#define DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q__SHIFT 0x0 +#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffff +#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x0 +#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffff +#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x0 +#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffff +#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x0 +#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffff +#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x0 +#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffff +#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x0 +#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffff +#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x0 +#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffff +#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x0 +#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffff +#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x0 +#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffff +#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x0 +#define DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J_MASK 0xffffffff +#define DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J__SHIFT 0x0 +#define DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K_MASK 0xffffffff +#define DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K__SHIFT 0x0 +#define DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L_MASK 0xffffffff +#define DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L__SHIFT 0x0 +#define DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M_MASK 0xffffffff +#define DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M__SHIFT 0x0 +#define DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N_MASK 0xffffffff +#define DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N__SHIFT 0x0 +#define DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O_MASK 0xffffffff +#define DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O__SHIFT 0x0 +#define DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P_MASK 0xffffffff +#define DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P__SHIFT 0x0 +#define DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q_MASK 0xffffffff +#define DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q__SHIFT 0x0 +#define DMCU_CTRL__RESET_UC_MASK 0x1 +#define DMCU_CTRL__RESET_UC__SHIFT 0x0 +#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2 +#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 +#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10 +#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x16 +#define DMCU_STATUS__UC_IN_RESET_MASK 0x1 +#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 +#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2 +#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 +#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4 +#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 +#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0xff00 +#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x8 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x1 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x2 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x4 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x8 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x20 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800 +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800 +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000 +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000 +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000 +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000 +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000 +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x1000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0xc +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x2000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0xd +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x4000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0xe +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x8000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0xf +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x10000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x20000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x40000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x80000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x100000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x200000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x400000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x800000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d +#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff +#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10 +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100 +#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000 +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7 +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100 +#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8 +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000 +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10 +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000 +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8 +#define DP_CONFIG__DP_UDI_LANES_MASK 0x3 +#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1 +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78 +#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3 +#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00 +#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000 +#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000 +#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1 +#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0 +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100 +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000 +#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP_VID_N__DP_VID_N_MASK 0xffffff +#define DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP_VID_M__DP_VID_M_MASK 0xffffff +#define DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000 +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000 +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1 +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000 +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10 +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000 +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000 +#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000 +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3 +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff +#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00 +#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000 +#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff +#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00 +#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000 +#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff +#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00 +#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1 +#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10 +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100 +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1 +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2 +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x1fff0 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x1fff +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10 +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1 +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10 +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100 +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000 +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000 +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000 +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000 +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000 +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000 +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000 +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18 +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000 +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1 +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff +#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff +#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00 +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1 +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3 +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100 +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1 +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10 +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100 +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0 +#define AUX_CONTROL__AUX_EN_MASK 0x1 +#define AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100 +#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000 +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000 +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000 +#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000 +#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000 +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000 +#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000 +#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define AUX_CONTROL__SPARE_0_MASK 0x40000000 +#define AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define AUX_CONTROL__SPARE_1_MASK 0x80000000 +#define AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1 +#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4 +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0 +#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000 +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3 +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000 +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000 +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000 +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000 +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000 +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000 +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1 +#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2 +#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100 +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200 +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800 +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000 +#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e +#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1 +#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2 +#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100 +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200 +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800 +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000 +#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000 +#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000 +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1 +#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00 +#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000 +#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000 +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00 +#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000 +#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000 +#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1 +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70 +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000 +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7 +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00 +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1 +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0 +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00 +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1 +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0 +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0 +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4 +#define DVO_ENABLE__DVO_ENABLE_MASK 0x1 +#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0 +#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30 +#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4 +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7 +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0 +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000 +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10 +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3 +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0 +#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100 +#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8 +#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1 +#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0 +#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2 +#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1 +#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30 +#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4 +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100 +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8 +#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000 +#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10 +#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000 +#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11 +#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000 +#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12 +#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000 +#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14 +#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000 +#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15 +#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000 +#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16 +#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000 +#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18 +#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000 +#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f +#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000 +#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10 +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0 +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1 +#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0 +#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe +#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1 +#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000 +#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10 +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000 +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19 +#define FBC_CNTL__FBC_EN_MASK 0x80000000 +#define FBC_CNTL__FBC_EN__SHIFT 0x1f +#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff +#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0 +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0 +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0 +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80 +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7 +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00 +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8 +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14 +#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1 +#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0 +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100 +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8 +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200 +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9 +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400 +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800 +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb +#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000 +#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10 +#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff +#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0 +#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 +#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8 +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000 +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10 +#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000 +#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11 +#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000 +#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18 +#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff +#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0 +#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff +#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0 +#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff +#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0 +#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff +#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0 +#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff +#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0 +#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff +#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0 +#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff +#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0 +#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff +#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0 +#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff +#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0 +#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff +#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0 +#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff +#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0 +#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff +#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0 +#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff +#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0 +#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff +#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0 +#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff +#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0 +#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff +#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0 +#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff +#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0 +#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff +#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x3ff +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x3ff0000 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x3ff +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x3ff0000 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10 +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000 +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10 +#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3 +#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0 +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8 +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3 +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0 +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4 +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300 +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8 +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400 +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800 +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x3ff +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0 +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0 +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0 +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3 +#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0 +#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4 +#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2 +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8 +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3 +#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0 +#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4 +#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300 +#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8 +#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400 +#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa +#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800 +#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000 +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10 +#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000 +#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14 +#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000 +#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15 +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000 +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x1c +#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1 +#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1 +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10 +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4 +#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000 +#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000 +#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11 +#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000 +#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12 +#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000 +#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x1 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x0 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x700 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x8 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0xf000 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0xc +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x10000 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x10 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0xffff +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x0 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x10 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0xffff +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x0 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x10 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000 +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000 +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000 +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000 +#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000 +#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000 +#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0 +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1 +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000 +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1 +#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0 +#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2 +#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1 +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10 +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4 +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x100 +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x8 +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000 +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10 +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3 +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0 +#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff +#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0 +#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff +#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0 +#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff +#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0 +#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff +#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0 +#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 +#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 +#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 +#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 +#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 +#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 +#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000 +#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc +#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 +#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 +#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 +#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f +#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff +#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 +#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 +#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 +#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 +#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff +#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 +#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff +#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 +#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff +#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0 +#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000 +#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10 +#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000 +#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f +#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff +#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0 +#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 +#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10 +#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 +#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f +#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff +#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff +#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 +#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 +#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 +#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 +#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 +#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 +#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 +#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 +#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 +#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10 +#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 +#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000 +#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc +#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 +#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 +#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 +#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 +#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 +#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 +#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 +#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 +#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 +#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 +#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 +#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 +#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 +#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 +#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 +#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 +#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 +#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 +#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 +#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 +#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 +#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 +#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 +#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 +#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 +#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 +#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa +#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 +#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 +#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 +#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3 +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3 +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000 +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f +#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff +#define LB_DEBUG__LB_DEBUG__SHIFT 0x0 +#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff +#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0 +#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff +#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MVP_CONTROL1__MVP_EN_MASK 0x1 +#define MVP_CONTROL1__MVP_EN__SHIFT 0x0 +#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70 +#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9 +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400 +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa +#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000 +#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000 +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10 +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000 +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14 +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000 +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18 +#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000 +#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000 +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000 +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4 +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100 +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8 +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000 +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc +#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000 +#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10 +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000 +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14 +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000 +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18 +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000 +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10 +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000 +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000 +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0 +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000 +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10 +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1 +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0 +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10 +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4 +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00 +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14 +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0 +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00 +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8 +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000 +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10 +#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000 +#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000 +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000 +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0 +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000 +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10 +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0 +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1 +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0 +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100 +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14 +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000 +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0 +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000 +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5 +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40 +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6 +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80 +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7 +#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00 +#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0 +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6 +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6 +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe +#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe +#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1 +#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000 +#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19 +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000 +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a +#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000 +#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b +#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7 +#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6 +#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200 +#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9 +#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400 +#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800 +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000 +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc +#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000 +#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12 +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000 +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13 +#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000 +#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2 +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8 +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define SCL_MODE__SCL_MODE_MASK 0x3 +#define SCL_MODE__SCL_MODE__SHIFT 0x0 +#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 +#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 +#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00 +#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8 +#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 +#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3 +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1 +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0 +#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 +#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 +#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 +#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 +#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 +#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 +#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 +#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 +#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff +#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 +#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 +#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 +#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000 +#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 +#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 +#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 +#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 +#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 +#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 +#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3 +#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff +#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1 +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_WT__VGA_RAM_EN_MASK 0x2 +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_WT__VGA_CKSEL_MASK 0xc +#define GENMO_WT__VGA_CKSEL__SHIFT 0x2 +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20 +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1 +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_RD__VGA_RAM_EN_MASK 0x2 +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_RD__VGA_CKSEL_MASK 0xc +#define GENMO_RD__VGA_CKSEL__SHIFT 0x2 +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20 +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 +#define GENENB__BLK_IO_BASE_MASK 0xff +#define GENENB__BLK_IO_BASE__SHIFT 0x0 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x8 +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_RD__VSYNC_SEL_R_MASK 0x8 +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 +#define GENS0__SENSE_SWITCH_MASK 0x10 +#define GENS0__SENSE_SWITCH__SHIFT 0x4 +#define GENS0__CRT_INTR_MASK 0x80 +#define GENS0__CRT_INTR__SHIFT 0x7 +#define GENS1__NO_DISPLAY_MASK 0x1 +#define GENS1__NO_DISPLAY__SHIFT 0x0 +#define GENS1__VGA_VSTATUS_MASK 0x8 +#define GENS1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1__PIXEL_READ_BACK_MASK 0x30 +#define GENS1__PIXEL_READ_BACK__SHIFT 0x4 +#define DAC_DATA__DAC_DATA_MASK 0x3f +#define DAC_DATA__DAC_DATA__SHIFT 0x0 +#define DAC_MASK__DAC_MASK_MASK 0xff +#define DAC_MASK__DAC_MASK__SHIFT 0x0 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 +#define SEQ8_IDX__SEQ_IDX_MASK 0x7 +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 +#define SEQ8_DATA__SEQ_DATA_MASK 0xff +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 +#define SEQ00__SEQ_RST0B_MASK 0x1 +#define SEQ00__SEQ_RST0B__SHIFT 0x0 +#define SEQ00__SEQ_RST1B_MASK 0x2 +#define SEQ00__SEQ_RST1B__SHIFT 0x1 +#define SEQ01__SEQ_DOT8_MASK 0x1 +#define SEQ01__SEQ_DOT8__SHIFT 0x0 +#define SEQ01__SEQ_SHIFT2_MASK 0x4 +#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 +#define SEQ01__SEQ_PCLKBY2_MASK 0x8 +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 +#define SEQ01__SEQ_SHIFT4_MASK 0x10 +#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 +#define SEQ01__SEQ_MAXBW_MASK 0x20 +#define SEQ01__SEQ_MAXBW__SHIFT 0x5 +#define SEQ02__SEQ_MAP0_EN_MASK 0x1 +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 +#define SEQ02__SEQ_MAP1_EN_MASK 0x2 +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 +#define SEQ02__SEQ_MAP2_EN_MASK 0x4 +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 +#define SEQ02__SEQ_MAP3_EN_MASK 0x8 +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B1_MASK 0x1 +#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 +#define SEQ03__SEQ_FONT_B2_MASK 0x2 +#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 +#define SEQ03__SEQ_FONT_A1_MASK 0x4 +#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 +#define SEQ03__SEQ_FONT_A2_MASK 0x8 +#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B0_MASK 0x10 +#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 +#define SEQ03__SEQ_FONT_A0_MASK 0x20 +#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 +#define SEQ04__SEQ_256K_MASK 0x2 +#define SEQ04__SEQ_256K__SHIFT 0x1 +#define SEQ04__SEQ_ODDEVEN_MASK 0x4 +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 +#define SEQ04__SEQ_CHAIN_MASK 0x8 +#define SEQ04__SEQ_CHAIN__SHIFT 0x3 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_DATA__VCRTC_DATA_MASK 0xff +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 +#define CRT00__H_TOTAL_MASK 0xff +#define CRT00__H_TOTAL__SHIFT 0x0 +#define CRT01__H_DISP_END_MASK 0xff +#define CRT01__H_DISP_END__SHIFT 0x0 +#define CRT02__H_BLANK_START_MASK 0xff +#define CRT02__H_BLANK_START__SHIFT 0x0 +#define CRT03__H_BLANK_END_MASK 0x1f +#define CRT03__H_BLANK_END__SHIFT 0x0 +#define CRT03__H_DE_SKEW_MASK 0x60 +#define CRT03__H_DE_SKEW__SHIFT 0x5 +#define CRT03__CR10CR11_R_DIS_B_MASK 0x80 +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 +#define CRT04__H_SYNC_START_MASK 0xff +#define CRT04__H_SYNC_START__SHIFT 0x0 +#define CRT05__H_SYNC_END_MASK 0x1f +#define CRT05__H_SYNC_END__SHIFT 0x0 +#define CRT05__H_SYNC_SKEW_MASK 0x60 +#define CRT05__H_SYNC_SKEW__SHIFT 0x5 +#define CRT05__H_BLANK_END_B5_MASK 0x80 +#define CRT05__H_BLANK_END_B5__SHIFT 0x7 +#define CRT06__V_TOTAL_MASK 0xff +#define CRT06__V_TOTAL__SHIFT 0x0 +#define CRT07__V_TOTAL_B8_MASK 0x1 +#define CRT07__V_TOTAL_B8__SHIFT 0x0 +#define CRT07__V_DISP_END_B8_MASK 0x2 +#define CRT07__V_DISP_END_B8__SHIFT 0x1 +#define CRT07__V_SYNC_START_B8_MASK 0x4 +#define CRT07__V_SYNC_START_B8__SHIFT 0x2 +#define CRT07__V_BLANK_START_B8_MASK 0x8 +#define CRT07__V_BLANK_START_B8__SHIFT 0x3 +#define CRT07__LINE_CMP_B8_MASK 0x10 +#define CRT07__LINE_CMP_B8__SHIFT 0x4 +#define CRT07__V_TOTAL_B9_MASK 0x20 +#define CRT07__V_TOTAL_B9__SHIFT 0x5 +#define CRT07__V_DISP_END_B9_MASK 0x40 +#define CRT07__V_DISP_END_B9__SHIFT 0x6 +#define CRT07__V_SYNC_START_B9_MASK 0x80 +#define CRT07__V_SYNC_START_B9__SHIFT 0x7 +#define CRT08__ROW_SCAN_START_MASK 0x1f +#define CRT08__ROW_SCAN_START__SHIFT 0x0 +#define CRT08__BYTE_PAN_MASK 0x60 +#define CRT08__BYTE_PAN__SHIFT 0x5 +#define CRT09__MAX_ROW_SCAN_MASK 0x1f +#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 +#define CRT09__V_BLANK_START_B9_MASK 0x20 +#define CRT09__V_BLANK_START_B9__SHIFT 0x5 +#define CRT09__LINE_CMP_B9_MASK 0x40 +#define CRT09__LINE_CMP_B9__SHIFT 0x6 +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80 +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 +#define CRT0A__CURSOR_START_MASK 0x1f +#define CRT0A__CURSOR_START__SHIFT 0x0 +#define CRT0A__CURSOR_DISABLE_MASK 0x20 +#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 +#define CRT0B__CURSOR_END_MASK 0x1f +#define CRT0B__CURSOR_END__SHIFT 0x0 +#define CRT0B__CURSOR_SKEW_MASK 0x60 +#define CRT0B__CURSOR_SKEW__SHIFT 0x5 +#define CRT0C__DISP_START_MASK 0xff +#define CRT0C__DISP_START__SHIFT 0x0 +#define CRT0D__DISP_START_MASK 0xff +#define CRT0D__DISP_START__SHIFT 0x0 +#define CRT0E__CURSOR_LOC_HI_MASK 0xff +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 +#define CRT0F__CURSOR_LOC_LO_MASK 0xff +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 +#define CRT10__V_SYNC_START_MASK 0xff +#define CRT10__V_SYNC_START__SHIFT 0x0 +#define CRT11__V_SYNC_END_MASK 0xf +#define CRT11__V_SYNC_END__SHIFT 0x0 +#define CRT11__V_INTR_CLR_MASK 0x10 +#define CRT11__V_INTR_CLR__SHIFT 0x4 +#define CRT11__V_INTR_EN_MASK 0x20 +#define CRT11__V_INTR_EN__SHIFT 0x5 +#define CRT11__SEL5_REFRESH_CYC_MASK 0x40 +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 +#define CRT11__C0T7_WR_ONLY_MASK 0x80 +#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 +#define CRT12__V_DISP_END_MASK 0xff +#define CRT12__V_DISP_END__SHIFT 0x0 +#define CRT13__DISP_PITCH_MASK 0xff +#define CRT13__DISP_PITCH__SHIFT 0x0 +#define CRT14__UNDRLN_LOC_MASK 0x1f +#define CRT14__UNDRLN_LOC__SHIFT 0x0 +#define CRT14__ADDR_CNT_BY4_MASK 0x20 +#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 +#define CRT14__DOUBLE_WORD_MASK 0x40 +#define CRT14__DOUBLE_WORD__SHIFT 0x6 +#define CRT15__V_BLANK_START_MASK 0xff +#define CRT15__V_BLANK_START__SHIFT 0x0 +#define CRT16__V_BLANK_END_MASK 0xff +#define CRT16__V_BLANK_END__SHIFT 0x0 +#define CRT17__RA0_AS_A13B_MASK 0x1 +#define CRT17__RA0_AS_A13B__SHIFT 0x0 +#define CRT17__RA1_AS_A14B_MASK 0x2 +#define CRT17__RA1_AS_A14B__SHIFT 0x1 +#define CRT17__VCOUNT_BY2_MASK 0x4 +#define CRT17__VCOUNT_BY2__SHIFT 0x2 +#define CRT17__ADDR_CNT_BY2_MASK 0x8 +#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 +#define CRT17__WRAP_A15TOA0_MASK 0x20 +#define CRT17__WRAP_A15TOA0__SHIFT 0x5 +#define CRT17__BYTE_MODE_MASK 0x40 +#define CRT17__BYTE_MODE__SHIFT 0x6 +#define CRT17__CRTC_SYNC_EN_MASK 0x80 +#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 +#define CRT18__LINE_CMP_MASK 0xff +#define CRT18__LINE_CMP__SHIFT 0x0 +#define CRT1E__GRPH_DEC_RD1_MASK 0x2 +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 +#define CRT1F__GRPH_DEC_RD0_MASK 0xff +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 +#define CRT22__GRPH_LATCH_DATA_MASK 0xff +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 +#define GRPH8_IDX__GRPH_IDX_MASK 0xf +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 +#define GRPH8_DATA__GRPH_DATA_MASK 0xff +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET0_MASK 0x1 +#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET1_MASK 0x2 +#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 +#define GRA00__GRPH_SET_RESET2_MASK 0x4 +#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 +#define GRA00__GRPH_SET_RESET3_MASK 0x8 +#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1 +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2 +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4 +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8 +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 +#define GRA02__GRPH_CCOMP_MASK 0xf +#define GRA02__GRPH_CCOMP__SHIFT 0x0 +#define GRA03__GRPH_ROTATE_MASK 0x7 +#define GRA03__GRPH_ROTATE__SHIFT 0x0 +#define GRA03__GRPH_FN_SEL_MASK 0x18 +#define GRA03__GRPH_FN_SEL__SHIFT 0x3 +#define GRA04__GRPH_RMAP_MASK 0x3 +#define GRA04__GRPH_RMAP__SHIFT 0x0 +#define GRA05__GRPH_WRITE_MODE_MASK 0x3 +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 +#define GRA05__GRPH_READ1_MASK 0x8 +#define GRA05__GRPH_READ1__SHIFT 0x3 +#define GRA05__CGA_ODDEVEN_MASK 0x10 +#define GRA05__CGA_ODDEVEN__SHIFT 0x4 +#define GRA05__GRPH_OES_MASK 0x20 +#define GRA05__GRPH_OES__SHIFT 0x5 +#define GRA05__GRPH_PACK_MASK 0x40 +#define GRA05__GRPH_PACK__SHIFT 0x6 +#define GRA06__GRPH_GRAPHICS_MASK 0x1 +#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 +#define GRA06__GRPH_ODDEVEN_MASK 0x2 +#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 +#define GRA06__GRPH_ADRSEL_MASK 0xc +#define GRA06__GRPH_ADRSEL__SHIFT 0x2 +#define GRA07__GRPH_XCARE0_MASK 0x1 +#define GRA07__GRPH_XCARE0__SHIFT 0x0 +#define GRA07__GRPH_XCARE1_MASK 0x2 +#define GRA07__GRPH_XCARE1__SHIFT 0x1 +#define GRA07__GRPH_XCARE2_MASK 0x4 +#define GRA07__GRPH_XCARE2__SHIFT 0x2 +#define GRA07__GRPH_XCARE3_MASK 0x8 +#define GRA07__GRPH_XCARE3__SHIFT 0x3 +#define GRA08__GRPH_BMSK_MASK 0xff +#define GRA08__GRPH_BMSK__SHIFT 0x0 +#define ATTRX__ATTR_IDX_MASK 0x1f +#define ATTRX__ATTR_IDX__SHIFT 0x0 +#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20 +#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 +#define ATTRDW__ATTR_DATA_MASK 0xff +#define ATTRDW__ATTR_DATA__SHIFT 0x0 +#define ATTRDR__ATTR_DATA_MASK 0xff +#define ATTRDR__ATTR_DATA__SHIFT 0x0 +#define ATTR00__ATTR_PAL_MASK 0x3f +#define ATTR00__ATTR_PAL__SHIFT 0x0 +#define ATTR01__ATTR_PAL_MASK 0x3f +#define ATTR01__ATTR_PAL__SHIFT 0x0 +#define ATTR02__ATTR_PAL_MASK 0x3f +#define ATTR02__ATTR_PAL__SHIFT 0x0 +#define ATTR03__ATTR_PAL_MASK 0x3f +#define ATTR03__ATTR_PAL__SHIFT 0x0 +#define ATTR04__ATTR_PAL_MASK 0x3f +#define ATTR04__ATTR_PAL__SHIFT 0x0 +#define ATTR05__ATTR_PAL_MASK 0x3f +#define ATTR05__ATTR_PAL__SHIFT 0x0 +#define ATTR06__ATTR_PAL_MASK 0x3f +#define ATTR06__ATTR_PAL__SHIFT 0x0 +#define ATTR07__ATTR_PAL_MASK 0x3f +#define ATTR07__ATTR_PAL__SHIFT 0x0 +#define ATTR08__ATTR_PAL_MASK 0x3f +#define ATTR08__ATTR_PAL__SHIFT 0x0 +#define ATTR09__ATTR_PAL_MASK 0x3f +#define ATTR09__ATTR_PAL__SHIFT 0x0 +#define ATTR0A__ATTR_PAL_MASK 0x3f +#define ATTR0A__ATTR_PAL__SHIFT 0x0 +#define ATTR0B__ATTR_PAL_MASK 0x3f +#define ATTR0B__ATTR_PAL__SHIFT 0x0 +#define ATTR0C__ATTR_PAL_MASK 0x3f +#define ATTR0C__ATTR_PAL__SHIFT 0x0 +#define ATTR0D__ATTR_PAL_MASK 0x3f +#define ATTR0D__ATTR_PAL__SHIFT 0x0 +#define ATTR0E__ATTR_PAL_MASK 0x3f +#define ATTR0E__ATTR_PAL__SHIFT 0x0 +#define ATTR0F__ATTR_PAL_MASK 0x3f +#define ATTR0F__ATTR_PAL__SHIFT 0x0 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x1 +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 +#define ATTR10__ATTR_MONO_EN_MASK 0x2 +#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 +#define ATTR10__ATTR_LGRPH_EN_MASK 0x4 +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 +#define ATTR10__ATTR_BLINK_EN_MASK 0x8 +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 +#define ATTR10__ATTR_PANTOPONLY_MASK 0x20 +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 +#define ATTR10__ATTR_PCLKBY2_MASK 0x40 +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 +#define ATTR10__ATTR_CSEL_EN_MASK 0x80 +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 +#define ATTR11__ATTR_OVSC_MASK 0xff +#define ATTR11__ATTR_OVSC__SHIFT 0x0 +#define ATTR12__ATTR_MAP_EN_MASK 0xf +#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 +#define ATTR12__ATTR_VSMUX_MASK 0x30 +#define ATTR12__ATTR_VSMUX__SHIFT 0x4 +#define ATTR13__ATTR_PPAN_MASK 0xf +#define ATTR13__ATTR_PPAN__SHIFT 0x0 +#define ATTR14__ATTR_CSEL1_MASK 0x3 +#define ATTR14__ATTR_CSEL1__SHIFT 0x0 +#define ATTR14__ATTR_CSEL2_MASK 0xc +#define ATTR14__ATTR_CSEL2__SHIFT 0x2 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800 +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000 +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000 +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000 +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000 +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000 +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000 +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000 +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000 +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 +#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff +#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3 +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000 +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000 +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000 +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000 +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000 +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0 +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0 +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 +#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 +#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 +#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 +#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 +#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 +#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb +#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 +#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 +#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 +#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 +#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff +#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 +#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff +#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffff +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1 +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8 +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00 +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000 +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc +#define MINOR_VERSION__MINOR_VERSION_MASK 0xff +#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 +#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff +#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1 +#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 +#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2 +#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100 +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1 +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1 +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 +#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2 +#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE_MASK 0x1 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE_MASK 0x2 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE_MASK 0x4 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE_MASK 0x8 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE_MASK 0x10 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE_MASK 0x20 +#define INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000 +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f +#define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS_MASK 0x1 +#define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 +#define INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS_MASK 0x2 +#define INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 +#define INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS_MASK 0x4 +#define INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 +#define INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS_MASK 0x8 +#define INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 +#define INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS_MASK 0x10 +#define INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 +#define INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS_MASK 0x20 +#define INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000 +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000 +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1 +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2 +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4 +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8 +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10 +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20 +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff +#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_MASK 0x3 +#define CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 +#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1 +#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define RIRB_SIZE__RIRB_SIZE_MASK 0x3 +#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff +#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff +#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30 +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1 +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define BLND_CONTROL__BLND_MODE_MASK 0x300 +#define BLND_CONTROL__BLND_MODE__SHIFT 0x8 +#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000 +#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10 +#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000 +#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14 +#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000 +#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18 +#define SM_CONTROL2__SM_MODE_MASK 0x7 +#define SM_CONTROL2__SM_MODE__SHIFT 0x0 +#define SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10 +#define SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4 +#define SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20 +#define SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5 +#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300 +#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000 +#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000 +#define SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define PTI_CONTROL__PTI_ENABLE_MASK 0x1 +#define PTI_CONTROL__PTI_ENABLE__SHIFT 0x0 +#define PTI_CONTROL__PTI_NEW_PIXEL_GAP_MASK 0x30 +#define PTI_CONTROL__PTI_NEW_PIXEL_GAP__SHIFT 0x4 +#define PTI_CONTROL__BLND_NEW_PIXEL_MODE_MASK 0x40 +#define PTI_CONTROL__BLND_NEW_PIXEL_MODE__SHIFT 0x6 +#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1 +#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0 +#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100 +#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8 +#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000 +#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1 +#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK_MASK 0x100 +#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK__SHIFT 0x8 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18 +#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000 +#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c +#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING_MASK 0x1 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING__SHIFT 0x0 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING_MASK 0x2 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING__SHIFT 0x1 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING_MASK 0x4 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING_MASK 0x8 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING_MASK 0x10 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING__SHIFT 0x4 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING_MASK 0x20 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING__SHIFT 0x5 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING_MASK 0x40 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING__SHIFT 0x6 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING_MASK 0x80 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING__SHIFT 0x7 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING_MASK 0x100 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING__SHIFT 0x8 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING_MASK 0x200 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING__SHIFT 0x9 +#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1 +#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0 +#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe +#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff +#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0 +#define SI_ENABLE__SI_ENABLE_MASK 0x1 +#define SI_ENABLE__SI_ENABLE__SHIFT 0x0 +#define SI_EC_CONFIG__DISPCLK_R_SCANIN_GATE_DIS_MASK 0x1 +#define SI_EC_CONFIG__DISPCLK_R_SCANIN_GATE_DIS__SHIFT 0x0 +#define SI_EC_CONFIG__DISPCLK_G_SCANIN_GATE_DIS_MASK 0x2 +#define SI_EC_CONFIG__DISPCLK_G_SCANIN_GATE_DIS__SHIFT 0x1 +#define SI_EC_CONFIG__DISPCLK_G_SISCL_GATE_DIS_MASK 0x4 +#define SI_EC_CONFIG__DISPCLK_G_SISCL_GATE_DIS__SHIFT 0x2 +#define SI_EC_CONFIG__DISPCLK_R_SCANIN_RAMP_DIS_MASK 0x8 +#define SI_EC_CONFIG__DISPCLK_R_SCANIN_RAMP_DIS__SHIFT 0x3 +#define SI_EC_CONFIG__DISPCLK_G_SCANIN_RAMP_DIS_MASK 0x10 +#define SI_EC_CONFIG__DISPCLK_G_SCANIN_RAMP_DIS__SHIFT 0x4 +#define SI_EC_CONFIG__DISPCLK_G_SISCL_RAMP_DIS_MASK 0x20 +#define SI_EC_CONFIG__DISPCLK_G_SISCL_RAMP_DIS__SHIFT 0x5 +#define SI_EC_CONFIG__SI_LB_LS_DIS_MASK 0x40 +#define SI_EC_CONFIG__SI_LB_LS_DIS__SHIFT 0x6 +#define SI_EC_CONFIG__SI_LB_SD_DIS_MASK 0x80 +#define SI_EC_CONFIG__SI_LB_SD_DIS__SHIFT 0x7 +#define SI_EC_CONFIG__SI_LUT_LS_DIS_MASK 0x100 +#define SI_EC_CONFIG__SI_LUT_LS_DIS__SHIFT 0x8 +#define SI_EC_CONFIG__SCANIN_TEST_CLK_SEL_MASK 0xf000 +#define SI_EC_CONFIG__SCANIN_TEST_CLK_SEL__SHIFT 0xc +#define SI_EC_CONFIG__SI_RAM_PW_SAVE_MODE_MASK 0x800000 +#define SI_EC_CONFIG__SI_RAM_PW_SAVE_MODE__SHIFT 0x17 +#define SI_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000 +#define SI_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c +#define SI_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000 +#define SI_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e +#define CNV_MODE__CNV_INPUT_SRC_SELECT_MASK 0x3 +#define CNV_MODE__CNV_INPUT_SRC_SELECT__SHIFT 0x0 +#define CNV_MODE__CNV_INPUT_PIPE_SELECT_MASK 0x1c +#define CNV_MODE__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 +#define CNV_MODE__CNV_FRAME_COUNT_MASK 0x300 +#define CNV_MODE__CNV_FRAME_COUNT__SHIFT 0x8 +#define CNV_MODE__CNV_WINDOW_EN_MASK 0x1000 +#define CNV_MODE__CNV_WINDOW_EN__SHIFT 0xc +#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000 +#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 +#define CNV_MODE__CNV_STEREO_EYE_ORDER_MASK 0x40000 +#define CNV_MODE__CNV_STEREO_EYE_ORDER__SHIFT 0x12 +#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000 +#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 +#define CNV_MODE__CNV_FRAME_EN_MASK 0x80000000 +#define CNV_MODE__CNV_FRAME_EN__SHIFT 0x1f +#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff +#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 +#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000 +#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 +#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff +#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 +#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000 +#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 +#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1 +#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 +#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100 +#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 +#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000 +#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 +#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff +#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 +#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000 +#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 +#define CNV_CSC_CONTROL__CNV_CSC_bypass_MASK 0x1 +#define CNV_CSC_CONTROL__CNV_CSC_bypass__SHIFT 0x0 +#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff +#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 +#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000 +#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 +#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff +#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 +#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000 +#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 +#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff +#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 +#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000 +#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 +#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff +#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 +#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000 +#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 +#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff +#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 +#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000 +#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 +#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff +#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 +#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000 +#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 +#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 +#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 +#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 +#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10 +#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 +#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100 +#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 +#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000 +#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xffff +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x0 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xffff +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x0 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xffff +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x0 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 +#define SI_DEBUG_CTRL__SI_DEBUG_SEL_MASK 0x3 +#define SI_DEBUG_CTRL__SI_DEBUG_SEL__SHIFT 0x0 +#define SI_DBG_MODE__SI_DBG_MODE_EN_MASK 0x1 +#define SI_DBG_MODE__SI_DBG_MODE_EN__SHIFT 0x0 +#define SI_DBG_MODE__SI_DBG_DIN_FMT_MASK 0x2 +#define SI_DBG_MODE__SI_DBG_DIN_FMT__SHIFT 0x1 +#define SI_DBG_MODE__SI_DBG_36MODE_MASK 0x4 +#define SI_DBG_MODE__SI_DBG_36MODE__SHIFT 0x2 +#define SI_DBG_MODE__SI_DBG_CMAP_MASK 0x8 +#define SI_DBG_MODE__SI_DBG_CMAP__SHIFT 0x3 +#define SI_DBG_MODE__SI_DBG_PXLRATE_ERROR_MASK 0x100 +#define SI_DBG_MODE__SI_DBG_PXLRATE_ERROR__SHIFT 0x8 +#define SI_DBG_MODE__SI_DBG_SOURCE_WIDTH_MASK 0x7fff0000 +#define SI_DBG_MODE__SI_DBG_SOURCE_WIDTH__SHIFT 0x10 +#define SI_HARD_DEBUG__SI_HARD_DEBUG_MASK 0xffffffff +#define SI_HARD_DEBUG__SI_HARD_DEBUG__SHIFT 0x0 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff +#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0 +#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x7 +#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_PHASE_MASK 0xf00 +#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_PHASE__SHIFT 0x8 +#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_FILTER_TYPE_MASK 0x30000 +#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x3fff +#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 +#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3fff0000 +#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 +#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define SISCL_MODE__SISCL_MODE_MASK 0x3 +#define SISCL_MODE__SISCL_MODE__SHIFT 0x0 +#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_Y_RGB_MASK 0xf +#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0 +#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_CBCR_MASK 0xf0 +#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4 +#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_Y_RGB_MASK 0xf00 +#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8 +#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_CBCR_MASK 0xf000 +#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc +#define SISCL_DEST_SIZE__SISCL_DEST_HEIGHT_MASK 0x7fff +#define SISCL_DEST_SIZE__SISCL_DEST_HEIGHT__SHIFT 0x0 +#define SISCL_DEST_SIZE__SISCL_DEST_WIDTH_MASK 0x7fff0000 +#define SISCL_DEST_SIZE__SISCL_DEST_WIDTH__SHIFT 0x10 +#define SISCL_HORZ_FILTER_SCALE_RATIO__SISCL_H_SCALE_RATIO_MASK 0x7ffffff +#define SISCL_HORZ_FILTER_SCALE_RATIO__SISCL_H_SCALE_RATIO__SHIFT 0x0 +#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_FRAC_Y_RGB_MASK 0xffffff +#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0 +#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_INT_Y_RGB_MASK 0x1f000000 +#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_INT_Y_RGB__SHIFT 0x18 +#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_FRAC_CBCR_MASK 0xffffff +#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_FRAC_CBCR__SHIFT 0x0 +#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_INT_CBCR_MASK 0x1f000000 +#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_INT_CBCR__SHIFT 0x18 +#define SISCL_VERT_FILTER_SCALE_RATIO__SISCL_V_SCALE_RATIO_MASK 0x7ffffff +#define SISCL_VERT_FILTER_SCALE_RATIO__SISCL_V_SCALE_RATIO__SHIFT 0x0 +#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_FRAC_Y_RGB_MASK 0xffffff +#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0 +#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_INT_Y_RGB_MASK 0x1f000000 +#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_INT_Y_RGB__SHIFT 0x18 +#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_FRAC_CBCR_MASK 0xffffff +#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_FRAC_CBCR__SHIFT 0x0 +#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_INT_CBCR_MASK 0x1f000000 +#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_INT_CBCR__SHIFT 0x18 +#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_Y_RGB_MASK 0xffff +#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0 +#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 +#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_CBCR__SHIFT 0x10 +#define SISCL_CLAMP__SISCL_CLAMP_UPPER_Y_RGB_MASK 0xff +#define SISCL_CLAMP__SISCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0 +#define SISCL_CLAMP__SISCL_CLAMP_LOWER_Y_RGB_MASK 0xff00 +#define SISCL_CLAMP__SISCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8 +#define SISCL_CLAMP__SISCL_CLAMP_UPPER_CBCR_MASK 0xff0000 +#define SISCL_CLAMP__SISCL_CLAMP_UPPER_CBCR__SHIFT 0x10 +#define SISCL_CLAMP__SISCL_CLAMP_LOWER_CBCR_MASK 0xff000000 +#define SISCL_CLAMP__SISCL_CLAMP_LOWER_CBCR__SHIFT 0x18 +#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_FLAG_MASK 0x1 +#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_FLAG__SHIFT 0x0 +#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_ACK_MASK 0x100 +#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_ACK__SHIFT 0x8 +#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_MASK_MASK 0x1000 +#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_MASK__SHIFT 0xc +#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_STATUS_MASK 0x10000 +#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 +#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_TYPE_MASK 0x100000 +#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 +#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_FLAG_MASK 0x1 +#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_FLAG__SHIFT 0x0 +#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_ACK_MASK 0x100 +#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_ACK__SHIFT 0x8 +#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_MASK_MASK 0x1000 +#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_MASK__SHIFT 0xc +#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000 +#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 +#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_TYPE_MASK 0x100000 +#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14 +#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_OUTSIDE_PIX_STRATEGY_MASK 0x1 +#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0 +#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_B_CB_MASK 0xff00 +#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_B_CB__SHIFT 0x8 +#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_G_Y_MASK 0xff0000 +#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_G_Y__SHIFT 0x10 +#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_R_CR_MASK 0xff000000 +#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_R_CR__SHIFT 0x18 +#define SISCL_TEST_CNTL__SISCL_TEST_CRC_EN_MASK 0x10 +#define SISCL_TEST_CNTL__SISCL_TEST_CRC_EN__SHIFT 0x4 +#define SISCL_TEST_CNTL__SISCL_TEST_CRC_CONT_EN_MASK 0x100 +#define SISCL_TEST_CNTL__SISCL_TEST_CRC_CONT_EN__SHIFT 0x8 +#define SISCL_TEST_CNTL__SISCL_TEST_CRC_DE_ONLY_MASK 0x10000 +#define SISCL_TEST_CNTL__SISCL_TEST_CRC_DE_ONLY__SHIFT 0x10 +#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_RED_MASK_MASK 0xffff +#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_RED_MASK__SHIFT 0x0 +#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_SIG_RED_MASK 0xffff0000 +#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_SIG_RED__SHIFT 0x10 +#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_GREEN_MASK_MASK 0xffff +#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_GREEN_MASK__SHIFT 0x0 +#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_SIG_GREEN_MASK 0xffff0000 +#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_SIG_GREEN__SHIFT 0x10 +#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_BLUE_MASK_MASK 0xffff +#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_BLUE_MASK__SHIFT 0x0 +#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_SIG_BLUE_MASK 0xffff0000 +#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_SIG_BLUE__SHIFT 0x10 +#define SISCL_BACKPRESSURE_CNT_EN__SISCL_BACKPRESSURE_CNT_EN_MASK 0x1 +#define SISCL_BACKPRESSURE_CNT_EN__SISCL_BACKPRESSURE_CNT_EN__SHIFT 0x0 +#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_Y_MAX_BACKPRESSURE_MASK 0xffff +#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0 +#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_C_MAX_BACKPRESSURE_MASK 0xffff0000 +#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10 +#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_INDEX_MASK 0xff +#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_INDEX__SHIFT 0x0 +#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define SISCL_TEST_DEBUG_DATA__SISCL_TEST_DEBUG_DATA_MASK 0xffffffff +#define SISCL_TEST_DEBUG_DATA__SISCL_TEST_DEBUG_DATA__SHIFT 0x0 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x1000 +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0xc +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x2000 +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0xd +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x4000 +#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0xe +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x1 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x100 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x8 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x10000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x10 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x1000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x18 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x1e +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8 +#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff +#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0 +#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1 +#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf +#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff +#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0 +#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff +#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0 +#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff +#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0 +#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000 +#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18 +#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000 +#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19 +#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000 +#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9 +#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff +#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0 + +#endif /* DCE_8_0_SH_MASK_H */ -- cgit v1.2.3 From 36cfed855daf174f7551f0fdcd3157d8d7c5ba0b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:17:56 -0400 Subject: drm/amdgpu: add DCE 10.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the DCE (Display and Composition Engine) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h | 7350 ++++++++ .../drm/amd/include/asic_reg/dce/dce_10_0_enum.h | 1773 ++ .../amd/include/asic_reg/dce/dce_10_0_sh_mask.h | 16647 +++++++++++++++++++ 3 files changed, 25770 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h new file mode 100644 index 000000000000..95570dbd18bb --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h @@ -0,0 +1,7350 @@ +/* + * DCE_10_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_10_0_D_H +#define DCE_10_0_D_H + +#define mmPIPE0_PG_CONFIG 0x2c0 +#define mmPIPE0_PG_ENABLE 0x2c1 +#define mmPIPE0_PG_STATUS 0x2c2 +#define mmPIPE1_PG_CONFIG 0x2c3 +#define mmPIPE1_PG_ENABLE 0x2c4 +#define mmPIPE1_PG_STATUS 0x2c5 +#define mmPIPE2_PG_CONFIG 0x2c6 +#define mmPIPE2_PG_ENABLE 0x2c7 +#define mmPIPE2_PG_STATUS 0x2c8 +#define mmPIPE3_PG_CONFIG 0x2c9 +#define mmPIPE3_PG_ENABLE 0x2ca +#define mmPIPE3_PG_STATUS 0x2cb +#define mmPIPE4_PG_CONFIG 0x2cc +#define mmPIPE4_PG_ENABLE 0x2cd +#define mmPIPE4_PG_STATUS 0x2ce +#define mmPIPE5_PG_CONFIG 0x2cf +#define mmPIPE5_PG_ENABLE 0x2d0 +#define mmPIPE5_PG_STATUS 0x2d1 +#define mmDC_IP_REQUEST_CNTL 0x2d2 +#define mmDC_PGFSM_CONFIG_REG 0x2d3 +#define mmDC_PGFSM_WRITE_REG 0x2d4 +#define mmDC_PGCNTL_STATUS_REG 0x2d5 +#define mmDCPG_TEST_DEBUG_INDEX 0x2d6 +#define mmDCPG_TEST_DEBUG_DATA 0x2d7 +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 +#define mmBL1_PWM_USER_LEVEL 0x1629 +#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a +#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b +#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d +#define mmBL1_PWM_ABM_CNTL 0x162e +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f +#define mmBL1_PWM_GRP2_REG_LOCK 0x1630 +#define mmDC_ABM1_CNTL 0x1638 +#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e +#define mmDC_ABM1_ACE_THRES_12 0x163f +#define mmDC_ABM1_ACE_THRES_34 0x1640 +#define mmDC_ABM1_ACE_CNTL_MISC 0x1641 +#define mmDC_ABM1_DEBUG_MISC 0x1649 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a +#define mmDC_ABM1_HG_MISC_CTRL 0x164b +#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c +#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e +#define mmDC_ABM1_LS_PIXEL_COUNT 0x164f +#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 +#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 +#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a +#define mmDC_ABM1_HG_RESULT_1 0x165b +#define mmDC_ABM1_HG_RESULT_2 0x165c +#define mmDC_ABM1_HG_RESULT_3 0x165d +#define mmDC_ABM1_HG_RESULT_4 0x165e +#define mmDC_ABM1_HG_RESULT_5 0x165f +#define mmDC_ABM1_HG_RESULT_6 0x1660 +#define mmDC_ABM1_HG_RESULT_7 0x1661 +#define mmDC_ABM1_HG_RESULT_8 0x1662 +#define mmDC_ABM1_HG_RESULT_9 0x1663 +#define mmDC_ABM1_HG_RESULT_10 0x1664 +#define mmDC_ABM1_HG_RESULT_11 0x1665 +#define mmDC_ABM1_HG_RESULT_12 0x1666 +#define mmDC_ABM1_HG_RESULT_13 0x1667 +#define mmDC_ABM1_HG_RESULT_14 0x1668 +#define mmDC_ABM1_HG_RESULT_15 0x1669 +#define mmDC_ABM1_HG_RESULT_16 0x166a +#define mmDC_ABM1_HG_RESULT_17 0x166b +#define mmDC_ABM1_HG_RESULT_18 0x166c +#define mmDC_ABM1_HG_RESULT_19 0x166d +#define mmDC_ABM1_HG_RESULT_20 0x166e +#define mmDC_ABM1_HG_RESULT_21 0x166f +#define mmDC_ABM1_HG_RESULT_22 0x1670 +#define mmDC_ABM1_HG_RESULT_23 0x1671 +#define mmDC_ABM1_HG_RESULT_24 0x1672 +#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b +#define mmDC_ABM1_BL_MASTER_LOCK 0x169c +#define mmABM_TEST_DEBUG_INDEX 0x169e +#define mmABM_TEST_DEBUG_DATA 0x169f +#define mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c +#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c +#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1d7c +#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x1f7c +#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x417c +#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x437c +#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x457c +#define mmCRTC6_CRTC_DCFE_CLOCK_CONTROL 0x477c +#define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d +#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d +#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d +#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d +#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d +#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d +#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d +#define mmCRTC6_CRTC_H_BLANK_EARLY_NUM 0x477d +#define mmDCFE_DBG_SEL 0x1b7e +#define mmCRTC0_DCFE_DBG_SEL 0x1b7e +#define mmCRTC1_DCFE_DBG_SEL 0x1d7e +#define mmCRTC2_DCFE_DBG_SEL 0x1f7e +#define mmCRTC3_DCFE_DBG_SEL 0x417e +#define mmCRTC4_DCFE_DBG_SEL 0x437e +#define mmCRTC5_DCFE_DBG_SEL 0x457e +#define mmCRTC6_DCFE_DBG_SEL 0x477e +#define mmDCFE_MEM_PWR_CTRL 0x1b7f +#define mmCRTC0_DCFE_MEM_PWR_CTRL 0x1b7f +#define mmCRTC1_DCFE_MEM_PWR_CTRL 0x1d7f +#define mmCRTC2_DCFE_MEM_PWR_CTRL 0x1f7f +#define mmCRTC3_DCFE_MEM_PWR_CTRL 0x417f +#define mmCRTC4_DCFE_MEM_PWR_CTRL 0x437f +#define mmCRTC5_DCFE_MEM_PWR_CTRL 0x457f +#define mmCRTC6_DCFE_MEM_PWR_CTRL 0x477f +#define mmDCFE_MEM_PWR_CTRL2 0x1bb8 +#define mmCRTC0_DCFE_MEM_PWR_CTRL2 0x1bb8 +#define mmCRTC1_DCFE_MEM_PWR_CTRL2 0x1db8 +#define mmCRTC2_DCFE_MEM_PWR_CTRL2 0x1fb8 +#define mmCRTC3_DCFE_MEM_PWR_CTRL2 0x41b8 +#define mmCRTC4_DCFE_MEM_PWR_CTRL2 0x43b8 +#define mmCRTC5_DCFE_MEM_PWR_CTRL2 0x45b8 +#define mmCRTC6_DCFE_MEM_PWR_CTRL2 0x47b8 +#define mmDCFE_MEM_PWR_STATUS 0x1bb9 +#define mmCRTC0_DCFE_MEM_PWR_STATUS 0x1bb9 +#define mmCRTC1_DCFE_MEM_PWR_STATUS 0x1db9 +#define mmCRTC2_DCFE_MEM_PWR_STATUS 0x1fb9 +#define mmCRTC3_DCFE_MEM_PWR_STATUS 0x41b9 +#define mmCRTC4_DCFE_MEM_PWR_STATUS 0x43b9 +#define mmCRTC5_DCFE_MEM_PWR_STATUS 0x45b9 +#define mmCRTC6_DCFE_MEM_PWR_STATUS 0x47b9 +#define mmCRTC_H_TOTAL 0x1b80 +#define mmCRTC0_CRTC_H_TOTAL 0x1b80 +#define mmCRTC1_CRTC_H_TOTAL 0x1d80 +#define mmCRTC2_CRTC_H_TOTAL 0x1f80 +#define mmCRTC3_CRTC_H_TOTAL 0x4180 +#define mmCRTC4_CRTC_H_TOTAL 0x4380 +#define mmCRTC5_CRTC_H_TOTAL 0x4580 +#define mmCRTC6_CRTC_H_TOTAL 0x4780 +#define mmCRTC_H_BLANK_START_END 0x1b81 +#define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 +#define mmCRTC1_CRTC_H_BLANK_START_END 0x1d81 +#define mmCRTC2_CRTC_H_BLANK_START_END 0x1f81 +#define mmCRTC3_CRTC_H_BLANK_START_END 0x4181 +#define mmCRTC4_CRTC_H_BLANK_START_END 0x4381 +#define mmCRTC5_CRTC_H_BLANK_START_END 0x4581 +#define mmCRTC6_CRTC_H_BLANK_START_END 0x4781 +#define mmCRTC_H_SYNC_A 0x1b82 +#define mmCRTC0_CRTC_H_SYNC_A 0x1b82 +#define mmCRTC1_CRTC_H_SYNC_A 0x1d82 +#define mmCRTC2_CRTC_H_SYNC_A 0x1f82 +#define mmCRTC3_CRTC_H_SYNC_A 0x4182 +#define mmCRTC4_CRTC_H_SYNC_A 0x4382 +#define mmCRTC5_CRTC_H_SYNC_A 0x4582 +#define mmCRTC6_CRTC_H_SYNC_A 0x4782 +#define mmCRTC_H_SYNC_A_CNTL 0x1b83 +#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 +#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83 +#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83 +#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183 +#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383 +#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583 +#define mmCRTC6_CRTC_H_SYNC_A_CNTL 0x4783 +#define mmCRTC_H_SYNC_B 0x1b84 +#define mmCRTC0_CRTC_H_SYNC_B 0x1b84 +#define mmCRTC1_CRTC_H_SYNC_B 0x1d84 +#define mmCRTC2_CRTC_H_SYNC_B 0x1f84 +#define mmCRTC3_CRTC_H_SYNC_B 0x4184 +#define mmCRTC4_CRTC_H_SYNC_B 0x4384 +#define mmCRTC5_CRTC_H_SYNC_B 0x4584 +#define mmCRTC6_CRTC_H_SYNC_B 0x4784 +#define mmCRTC_H_SYNC_B_CNTL 0x1b85 +#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 +#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85 +#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85 +#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185 +#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385 +#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585 +#define mmCRTC6_CRTC_H_SYNC_B_CNTL 0x4785 +#define mmCRTC_VBI_END 0x1b86 +#define mmCRTC0_CRTC_VBI_END 0x1b86 +#define mmCRTC1_CRTC_VBI_END 0x1d86 +#define mmCRTC2_CRTC_VBI_END 0x1f86 +#define mmCRTC3_CRTC_VBI_END 0x4186 +#define mmCRTC4_CRTC_VBI_END 0x4386 +#define mmCRTC5_CRTC_VBI_END 0x4586 +#define mmCRTC6_CRTC_VBI_END 0x4786 +#define mmCRTC_V_TOTAL 0x1b87 +#define mmCRTC0_CRTC_V_TOTAL 0x1b87 +#define mmCRTC1_CRTC_V_TOTAL 0x1d87 +#define mmCRTC2_CRTC_V_TOTAL 0x1f87 +#define mmCRTC3_CRTC_V_TOTAL 0x4187 +#define mmCRTC4_CRTC_V_TOTAL 0x4387 +#define mmCRTC5_CRTC_V_TOTAL 0x4587 +#define mmCRTC6_CRTC_V_TOTAL 0x4787 +#define mmCRTC_V_TOTAL_MIN 0x1b88 +#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 +#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88 +#define mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88 +#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4188 +#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4388 +#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4588 +#define mmCRTC6_CRTC_V_TOTAL_MIN 0x4788 +#define mmCRTC_V_TOTAL_MAX 0x1b89 +#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 +#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89 +#define mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89 +#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4189 +#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4389 +#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4589 +#define mmCRTC6_CRTC_V_TOTAL_MAX 0x4789 +#define mmCRTC_V_TOTAL_CONTROL 0x1b8a +#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a +#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a +#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a +#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a +#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a +#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a +#define mmCRTC6_CRTC_V_TOTAL_CONTROL 0x478a +#define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b +#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b +#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b +#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b +#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b +#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b +#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b +#define mmCRTC6_CRTC_V_TOTAL_INT_STATUS 0x478b +#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c +#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c +#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c +#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c +#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c +#define mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS 0x478c +#define mmCRTC_V_BLANK_START_END 0x1b8d +#define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d +#define mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d +#define mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d +#define mmCRTC3_CRTC_V_BLANK_START_END 0x418d +#define mmCRTC4_CRTC_V_BLANK_START_END 0x438d +#define mmCRTC5_CRTC_V_BLANK_START_END 0x458d +#define mmCRTC6_CRTC_V_BLANK_START_END 0x478d +#define mmCRTC_V_SYNC_A 0x1b8e +#define mmCRTC0_CRTC_V_SYNC_A 0x1b8e +#define mmCRTC1_CRTC_V_SYNC_A 0x1d8e +#define mmCRTC2_CRTC_V_SYNC_A 0x1f8e +#define mmCRTC3_CRTC_V_SYNC_A 0x418e +#define mmCRTC4_CRTC_V_SYNC_A 0x438e +#define mmCRTC5_CRTC_V_SYNC_A 0x458e +#define mmCRTC6_CRTC_V_SYNC_A 0x478e +#define mmCRTC_V_SYNC_A_CNTL 0x1b8f +#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f +#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f +#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f +#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f +#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f +#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f +#define mmCRTC6_CRTC_V_SYNC_A_CNTL 0x478f +#define mmCRTC_V_SYNC_B 0x1b90 +#define mmCRTC0_CRTC_V_SYNC_B 0x1b90 +#define mmCRTC1_CRTC_V_SYNC_B 0x1d90 +#define mmCRTC2_CRTC_V_SYNC_B 0x1f90 +#define mmCRTC3_CRTC_V_SYNC_B 0x4190 +#define mmCRTC4_CRTC_V_SYNC_B 0x4390 +#define mmCRTC5_CRTC_V_SYNC_B 0x4590 +#define mmCRTC6_CRTC_V_SYNC_B 0x4790 +#define mmCRTC_V_SYNC_B_CNTL 0x1b91 +#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 +#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91 +#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91 +#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191 +#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391 +#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591 +#define mmCRTC6_CRTC_V_SYNC_B_CNTL 0x4791 +#define mmCRTC_DTMTEST_CNTL 0x1b92 +#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 +#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92 +#define mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92 +#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4192 +#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4392 +#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4592 +#define mmCRTC6_CRTC_DTMTEST_CNTL 0x4792 +#define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93 +#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93 +#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193 +#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393 +#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593 +#define mmCRTC6_CRTC_DTMTEST_STATUS_POSITION 0x4793 +#define mmCRTC_TRIGA_CNTL 0x1b94 +#define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 +#define mmCRTC1_CRTC_TRIGA_CNTL 0x1d94 +#define mmCRTC2_CRTC_TRIGA_CNTL 0x1f94 +#define mmCRTC3_CRTC_TRIGA_CNTL 0x4194 +#define mmCRTC4_CRTC_TRIGA_CNTL 0x4394 +#define mmCRTC5_CRTC_TRIGA_CNTL 0x4594 +#define mmCRTC6_CRTC_TRIGA_CNTL 0x4794 +#define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95 +#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95 +#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195 +#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395 +#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595 +#define mmCRTC6_CRTC_TRIGA_MANUAL_TRIG 0x4795 +#define mmCRTC_TRIGB_CNTL 0x1b96 +#define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 +#define mmCRTC1_CRTC_TRIGB_CNTL 0x1d96 +#define mmCRTC2_CRTC_TRIGB_CNTL 0x1f96 +#define mmCRTC3_CRTC_TRIGB_CNTL 0x4196 +#define mmCRTC4_CRTC_TRIGB_CNTL 0x4396 +#define mmCRTC5_CRTC_TRIGB_CNTL 0x4596 +#define mmCRTC6_CRTC_TRIGB_CNTL 0x4796 +#define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97 +#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97 +#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197 +#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397 +#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597 +#define mmCRTC6_CRTC_TRIGB_MANUAL_TRIG 0x4797 +#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98 +#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98 +#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 +#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398 +#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598 +#define mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 +#define mmCRTC_FLOW_CONTROL 0x1b99 +#define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 +#define mmCRTC1_CRTC_FLOW_CONTROL 0x1d99 +#define mmCRTC2_CRTC_FLOW_CONTROL 0x1f99 +#define mmCRTC3_CRTC_FLOW_CONTROL 0x4199 +#define mmCRTC4_CRTC_FLOW_CONTROL 0x4399 +#define mmCRTC5_CRTC_FLOW_CONTROL 0x4599 +#define mmCRTC6_CRTC_FLOW_CONTROL 0x4799 +#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a +#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a +#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a +#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a +#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a +#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a +#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a +#define mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE 0x479a +#define mmCRTC_AVSYNC_COUNTER 0x1b9b +#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b +#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b +#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b +#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b +#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b +#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b +#define mmCRTC6_CRTC_AVSYNC_COUNTER 0x479b +#define mmCRTC_CONTROL 0x1b9c +#define mmCRTC0_CRTC_CONTROL 0x1b9c +#define mmCRTC1_CRTC_CONTROL 0x1d9c +#define mmCRTC2_CRTC_CONTROL 0x1f9c +#define mmCRTC3_CRTC_CONTROL 0x419c +#define mmCRTC4_CRTC_CONTROL 0x439c +#define mmCRTC5_CRTC_CONTROL 0x459c +#define mmCRTC6_CRTC_CONTROL 0x479c +#define mmCRTC_BLANK_CONTROL 0x1b9d +#define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d +#define mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d +#define mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d +#define mmCRTC3_CRTC_BLANK_CONTROL 0x419d +#define mmCRTC4_CRTC_BLANK_CONTROL 0x439d +#define mmCRTC5_CRTC_BLANK_CONTROL 0x459d +#define mmCRTC6_CRTC_BLANK_CONTROL 0x479d +#define mmCRTC_INTERLACE_CONTROL 0x1b9e +#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e +#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e +#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e +#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e +#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e +#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e +#define mmCRTC6_CRTC_INTERLACE_CONTROL 0x479e +#define mmCRTC_INTERLACE_STATUS 0x1b9f +#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f +#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f +#define mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f +#define mmCRTC3_CRTC_INTERLACE_STATUS 0x419f +#define mmCRTC4_CRTC_INTERLACE_STATUS 0x439f +#define mmCRTC5_CRTC_INTERLACE_STATUS 0x459f +#define mmCRTC6_CRTC_INTERLACE_STATUS 0x479f +#define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0 +#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0 +#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0 +#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0 +#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0 +#define mmCRTC6_CRTC_FIELD_INDICATION_CONTROL 0x47a0 +#define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1 +#define mmCRTC6_CRTC_PIXEL_DATA_READBACK0 0x47a1 +#define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2 +#define mmCRTC6_CRTC_PIXEL_DATA_READBACK1 0x47a2 +#define mmCRTC_STATUS 0x1ba3 +#define mmCRTC0_CRTC_STATUS 0x1ba3 +#define mmCRTC1_CRTC_STATUS 0x1da3 +#define mmCRTC2_CRTC_STATUS 0x1fa3 +#define mmCRTC3_CRTC_STATUS 0x41a3 +#define mmCRTC4_CRTC_STATUS 0x43a3 +#define mmCRTC5_CRTC_STATUS 0x45a3 +#define mmCRTC6_CRTC_STATUS 0x47a3 +#define mmCRTC_STATUS_POSITION 0x1ba4 +#define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 +#define mmCRTC1_CRTC_STATUS_POSITION 0x1da4 +#define mmCRTC2_CRTC_STATUS_POSITION 0x1fa4 +#define mmCRTC3_CRTC_STATUS_POSITION 0x41a4 +#define mmCRTC4_CRTC_STATUS_POSITION 0x43a4 +#define mmCRTC5_CRTC_STATUS_POSITION 0x45a4 +#define mmCRTC6_CRTC_STATUS_POSITION 0x47a4 +#define mmCRTC_NOM_VERT_POSITION 0x1ba5 +#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 +#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5 +#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5 +#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5 +#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5 +#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5 +#define mmCRTC6_CRTC_NOM_VERT_POSITION 0x47a5 +#define mmCRTC_STATUS_FRAME_COUNT 0x1ba6 +#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 +#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6 +#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6 +#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6 +#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6 +#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6 +#define mmCRTC6_CRTC_STATUS_FRAME_COUNT 0x47a6 +#define mmCRTC_STATUS_VF_COUNT 0x1ba7 +#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 +#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7 +#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7 +#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7 +#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7 +#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7 +#define mmCRTC6_CRTC_STATUS_VF_COUNT 0x47a7 +#define mmCRTC_STATUS_HV_COUNT 0x1ba8 +#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 +#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8 +#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8 +#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8 +#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8 +#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8 +#define mmCRTC6_CRTC_STATUS_HV_COUNT 0x47a8 +#define mmCRTC_COUNT_CONTROL 0x1ba9 +#define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 +#define mmCRTC1_CRTC_COUNT_CONTROL 0x1da9 +#define mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9 +#define mmCRTC3_CRTC_COUNT_CONTROL 0x41a9 +#define mmCRTC4_CRTC_COUNT_CONTROL 0x43a9 +#define mmCRTC5_CRTC_COUNT_CONTROL 0x45a9 +#define mmCRTC6_CRTC_COUNT_CONTROL 0x47a9 +#define mmCRTC_COUNT_RESET 0x1baa +#define mmCRTC0_CRTC_COUNT_RESET 0x1baa +#define mmCRTC1_CRTC_COUNT_RESET 0x1daa +#define mmCRTC2_CRTC_COUNT_RESET 0x1faa +#define mmCRTC3_CRTC_COUNT_RESET 0x41aa +#define mmCRTC4_CRTC_COUNT_RESET 0x43aa +#define mmCRTC5_CRTC_COUNT_RESET 0x45aa +#define mmCRTC6_CRTC_COUNT_RESET 0x47aa +#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab +#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab +#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab +#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab +#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab +#define mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab +#define mmCRTC_VERT_SYNC_CONTROL 0x1bac +#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac +#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac +#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac +#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac +#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac +#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac +#define mmCRTC6_CRTC_VERT_SYNC_CONTROL 0x47ac +#define mmCRTC_STEREO_STATUS 0x1bad +#define mmCRTC0_CRTC_STEREO_STATUS 0x1bad +#define mmCRTC1_CRTC_STEREO_STATUS 0x1dad +#define mmCRTC2_CRTC_STEREO_STATUS 0x1fad +#define mmCRTC3_CRTC_STEREO_STATUS 0x41ad +#define mmCRTC4_CRTC_STEREO_STATUS 0x43ad +#define mmCRTC5_CRTC_STEREO_STATUS 0x45ad +#define mmCRTC6_CRTC_STEREO_STATUS 0x47ad +#define mmCRTC_STEREO_CONTROL 0x1bae +#define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae +#define mmCRTC1_CRTC_STEREO_CONTROL 0x1dae +#define mmCRTC2_CRTC_STEREO_CONTROL 0x1fae +#define mmCRTC3_CRTC_STEREO_CONTROL 0x41ae +#define mmCRTC4_CRTC_STEREO_CONTROL 0x43ae +#define mmCRTC5_CRTC_STEREO_CONTROL 0x45ae +#define mmCRTC6_CRTC_STEREO_CONTROL 0x47ae +#define mmCRTC_SNAPSHOT_STATUS 0x1baf +#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf +#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf +#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf +#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af +#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af +#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af +#define mmCRTC6_CRTC_SNAPSHOT_STATUS 0x47af +#define mmCRTC_SNAPSHOT_CONTROL 0x1bb0 +#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 +#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0 +#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0 +#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0 +#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0 +#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0 +#define mmCRTC6_CRTC_SNAPSHOT_CONTROL 0x47b0 +#define mmCRTC_SNAPSHOT_POSITION 0x1bb1 +#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 +#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1 +#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1 +#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1 +#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1 +#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1 +#define mmCRTC6_CRTC_SNAPSHOT_POSITION 0x47b1 +#define mmCRTC_SNAPSHOT_FRAME 0x1bb2 +#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 +#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2 +#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2 +#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2 +#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2 +#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2 +#define mmCRTC6_CRTC_SNAPSHOT_FRAME 0x47b2 +#define mmCRTC_START_LINE_CONTROL 0x1bb3 +#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 +#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3 +#define mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3 +#define mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3 +#define mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3 +#define mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3 +#define mmCRTC6_CRTC_START_LINE_CONTROL 0x47b3 +#define mmCRTC_INTERRUPT_CONTROL 0x1bb4 +#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 +#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4 +#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4 +#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4 +#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4 +#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4 +#define mmCRTC6_CRTC_INTERRUPT_CONTROL 0x47b4 +#define mmCRTC_UPDATE_LOCK 0x1bb5 +#define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 +#define mmCRTC1_CRTC_UPDATE_LOCK 0x1db5 +#define mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5 +#define mmCRTC3_CRTC_UPDATE_LOCK 0x41b5 +#define mmCRTC4_CRTC_UPDATE_LOCK 0x43b5 +#define mmCRTC5_CRTC_UPDATE_LOCK 0x45b5 +#define mmCRTC6_CRTC_UPDATE_LOCK 0x47b5 +#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6 +#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6 +#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 +#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6 +#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6 +#define mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6 +#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7 +#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7 +#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 +#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7 +#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7 +#define mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7 +#define mmCRTC_TEST_PATTERN_CONTROL 0x1bba +#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba +#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba +#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba +#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba +#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba +#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba +#define mmCRTC6_CRTC_TEST_PATTERN_CONTROL 0x47ba +#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb +#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb +#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb +#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb +#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb +#define mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS 0x47bb +#define mmCRTC_TEST_PATTERN_COLOR 0x1bbc +#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc +#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc +#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc +#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc +#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc +#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc +#define mmCRTC6_CRTC_TEST_PATTERN_COLOR 0x47bc +#define mmMASTER_UPDATE_LOCK 0x1bbd +#define mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd +#define mmCRTC1_MASTER_UPDATE_LOCK 0x1dbd +#define mmCRTC2_MASTER_UPDATE_LOCK 0x1fbd +#define mmCRTC3_MASTER_UPDATE_LOCK 0x41bd +#define mmCRTC4_MASTER_UPDATE_LOCK 0x43bd +#define mmCRTC5_MASTER_UPDATE_LOCK 0x45bd +#define mmCRTC6_MASTER_UPDATE_LOCK 0x47bd +#define mmMASTER_UPDATE_MODE 0x1bbe +#define mmCRTC0_MASTER_UPDATE_MODE 0x1bbe +#define mmCRTC1_MASTER_UPDATE_MODE 0x1dbe +#define mmCRTC2_MASTER_UPDATE_MODE 0x1fbe +#define mmCRTC3_MASTER_UPDATE_MODE 0x41be +#define mmCRTC4_MASTER_UPDATE_MODE 0x43be +#define mmCRTC5_MASTER_UPDATE_MODE 0x45be +#define mmCRTC6_MASTER_UPDATE_MODE 0x47be +#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf +#define mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf +#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0 +#define mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 +#define mmCRTC_MVP_STATUS 0x1bc1 +#define mmCRTC0_CRTC_MVP_STATUS 0x1bc1 +#define mmCRTC1_CRTC_MVP_STATUS 0x1dc1 +#define mmCRTC2_CRTC_MVP_STATUS 0x1fc1 +#define mmCRTC3_CRTC_MVP_STATUS 0x41c1 +#define mmCRTC4_CRTC_MVP_STATUS 0x43c1 +#define mmCRTC5_CRTC_MVP_STATUS 0x45c1 +#define mmCRTC6_CRTC_MVP_STATUS 0x47c1 +#define mmCRTC_MASTER_EN 0x1bc2 +#define mmCRTC0_CRTC_MASTER_EN 0x1bc2 +#define mmCRTC1_CRTC_MASTER_EN 0x1dc2 +#define mmCRTC2_CRTC_MASTER_EN 0x1fc2 +#define mmCRTC3_CRTC_MASTER_EN 0x41c2 +#define mmCRTC4_CRTC_MASTER_EN 0x43c2 +#define mmCRTC5_CRTC_MASTER_EN 0x45c2 +#define mmCRTC6_CRTC_MASTER_EN 0x47c2 +#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3 +#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3 +#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 +#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3 +#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3 +#define mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3 +#define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4 +#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4 +#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4 +#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4 +#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4 +#define mmCRTC6_CRTC_V_UPDATE_INT_STATUS 0x47c4 +#define mmCRTC_OVERSCAN_COLOR 0x1bc8 +#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 +#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8 +#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8 +#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8 +#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8 +#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8 +#define mmCRTC6_CRTC_OVERSCAN_COLOR 0x47c8 +#define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9 +#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9 +#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9 +#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9 +#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9 +#define mmCRTC6_CRTC_OVERSCAN_COLOR_EXT 0x47c9 +#define mmCRTC_BLANK_DATA_COLOR 0x1bca +#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca +#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca +#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca +#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca +#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca +#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca +#define mmCRTC6_CRTC_BLANK_DATA_COLOR 0x47ca +#define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb +#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb +#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb +#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb +#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb +#define mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT 0x47cb +#define mmCRTC_BLACK_COLOR 0x1bcc +#define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc +#define mmCRTC1_CRTC_BLACK_COLOR 0x1dcc +#define mmCRTC2_CRTC_BLACK_COLOR 0x1fcc +#define mmCRTC3_CRTC_BLACK_COLOR 0x41cc +#define mmCRTC4_CRTC_BLACK_COLOR 0x43cc +#define mmCRTC5_CRTC_BLACK_COLOR 0x45cc +#define mmCRTC6_CRTC_BLACK_COLOR 0x47cc +#define mmCRTC_BLACK_COLOR_EXT 0x1bcd +#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd +#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd +#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd +#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd +#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd +#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd +#define mmCRTC6_CRTC_BLACK_COLOR_EXT 0x47cd +#define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce +#define mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce +#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf +#define mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf +#define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0 +#define mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0 +#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1 +#define mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1 +#define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2 +#define mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2 +#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3 +#define mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3 +#define mmCRTC_CRC_CNTL 0x1bd4 +#define mmCRTC0_CRTC_CRC_CNTL 0x1bd4 +#define mmCRTC1_CRTC_CRC_CNTL 0x1dd4 +#define mmCRTC2_CRTC_CRC_CNTL 0x1fd4 +#define mmCRTC3_CRTC_CRC_CNTL 0x41d4 +#define mmCRTC4_CRTC_CRC_CNTL 0x43d4 +#define mmCRTC5_CRTC_CRC_CNTL 0x45d4 +#define mmCRTC6_CRTC_CRC_CNTL 0x47d4 +#define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5 +#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5 +#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 +#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5 +#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5 +#define mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5 +#define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6 +#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6 +#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 +#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6 +#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6 +#define mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6 +#define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7 +#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7 +#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 +#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7 +#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7 +#define mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7 +#define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8 +#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8 +#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 +#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8 +#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8 +#define mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8 +#define mmCRTC_CRC0_DATA_RG 0x1bd9 +#define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 +#define mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9 +#define mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9 +#define mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9 +#define mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9 +#define mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9 +#define mmCRTC6_CRTC_CRC0_DATA_RG 0x47d9 +#define mmCRTC_CRC0_DATA_B 0x1bda +#define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda +#define mmCRTC1_CRTC_CRC0_DATA_B 0x1dda +#define mmCRTC2_CRTC_CRC0_DATA_B 0x1fda +#define mmCRTC3_CRTC_CRC0_DATA_B 0x41da +#define mmCRTC4_CRTC_CRC0_DATA_B 0x43da +#define mmCRTC5_CRTC_CRC0_DATA_B 0x45da +#define mmCRTC6_CRTC_CRC0_DATA_B 0x47da +#define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb +#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb +#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db +#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db +#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db +#define mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db +#define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc +#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc +#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc +#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc +#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc +#define mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc +#define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd +#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd +#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd +#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd +#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd +#define mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd +#define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde +#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde +#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de +#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de +#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de +#define mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de +#define mmCRTC_CRC1_DATA_RG 0x1bdf +#define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf +#define mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf +#define mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf +#define mmCRTC3_CRTC_CRC1_DATA_RG 0x41df +#define mmCRTC4_CRTC_CRC1_DATA_RG 0x43df +#define mmCRTC5_CRTC_CRC1_DATA_RG 0x45df +#define mmCRTC6_CRTC_CRC1_DATA_RG 0x47df +#define mmCRTC_CRC1_DATA_B 0x1be0 +#define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 +#define mmCRTC1_CRTC_CRC1_DATA_B 0x1de0 +#define mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0 +#define mmCRTC3_CRTC_CRC1_DATA_B 0x41e0 +#define mmCRTC4_CRTC_CRC1_DATA_B 0x43e0 +#define mmCRTC5_CRTC_CRC1_DATA_B 0x45e0 +#define mmCRTC6_CRTC_CRC1_DATA_B 0x47e0 +#define mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1de1 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x1fe1 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x43e1 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x45e1 +#define mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1 +#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1de2 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1fe2 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x43e2 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x45e2 +#define mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2 +#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1de3 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1fe3 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x43e3 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x45e3 +#define mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3 +#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1de4 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1fe4 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x43e4 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x45e4 +#define mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4 +#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1de5 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1fe5 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x43e5 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x45e5 +#define mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5 +#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 +#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 +#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1de6 +#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1fe6 +#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6 +#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x43e6 +#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x45e6 +#define mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6 +#define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7 +#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7 +#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7 +#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7 +#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7 +#define mmCRTC6_CRTC_STATIC_SCREEN_CONTROL 0x47e7 +#define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78 +#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78 +#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178 +#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378 +#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578 +#define mmCRTC6_CRTC_3D_STRUCTURE_CONTROL 0x4778 +#define mmCRTC_GSL_VSYNC_GAP 0x1b79 +#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 +#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79 +#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79 +#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179 +#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379 +#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579 +#define mmCRTC6_CRTC_GSL_VSYNC_GAP 0x4779 +#define mmCRTC_GSL_WINDOW 0x1b7a +#define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a +#define mmCRTC1_CRTC_GSL_WINDOW 0x1d7a +#define mmCRTC2_CRTC_GSL_WINDOW 0x1f7a +#define mmCRTC3_CRTC_GSL_WINDOW 0x417a +#define mmCRTC4_CRTC_GSL_WINDOW 0x437a +#define mmCRTC5_CRTC_GSL_WINDOW 0x457a +#define mmCRTC6_CRTC_GSL_WINDOW 0x477a +#define mmCRTC_GSL_CONTROL 0x1b7b +#define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b +#define mmCRTC1_CRTC_GSL_CONTROL 0x1d7b +#define mmCRTC2_CRTC_GSL_CONTROL 0x1f7b +#define mmCRTC3_CRTC_GSL_CONTROL 0x417b +#define mmCRTC4_CRTC_GSL_CONTROL 0x437b +#define mmCRTC5_CRTC_GSL_CONTROL 0x457b +#define mmCRTC6_CRTC_GSL_CONTROL 0x477b +#define mmCRTC_TEST_DEBUG_INDEX 0x1bc6 +#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 +#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6 +#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6 +#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6 +#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6 +#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6 +#define mmCRTC6_CRTC_TEST_DEBUG_INDEX 0x47c6 +#define mmCRTC_TEST_DEBUG_DATA 0x1bc7 +#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 +#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7 +#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7 +#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7 +#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7 +#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7 +#define mmCRTC6_CRTC_TEST_DEBUG_DATA 0x47c7 +#define mmDAC_ENABLE 0x16aa +#define mmDAC_SOURCE_SELECT 0x16ab +#define mmDAC_CRC_EN 0x16ac +#define mmDAC_CRC_CONTROL 0x16ad +#define mmDAC_CRC_SIG_RGB_MASK 0x16ae +#define mmDAC_CRC_SIG_CONTROL_MASK 0x16af +#define mmDAC_CRC_SIG_RGB 0x16b0 +#define mmDAC_CRC_SIG_CONTROL 0x16b1 +#define mmDAC_SYNC_TRISTATE_CONTROL 0x16b2 +#define mmDAC_STEREOSYNC_SELECT 0x16b3 +#define mmDAC_AUTODETECT_CONTROL 0x16b4 +#define mmDAC_AUTODETECT_CONTROL2 0x16b5 +#define mmDAC_AUTODETECT_CONTROL3 0x16b6 +#define mmDAC_AUTODETECT_STATUS 0x16b7 +#define mmDAC_AUTODETECT_INT_CONTROL 0x16b8 +#define mmDAC_FORCE_OUTPUT_CNTL 0x16b9 +#define mmDAC_FORCE_DATA 0x16ba +#define mmDAC_POWERDOWN 0x16bb +#define mmDAC_CONTROL 0x16bc +#define mmDAC_COMPARATOR_ENABLE 0x16bd +#define mmDAC_COMPARATOR_OUTPUT 0x16be +#define mmDAC_PWR_CNTL 0x16bf +#define mmDAC_DFT_CONFIG 0x16c0 +#define mmDAC_FIFO_STATUS 0x16c1 +#define mmDAC_TEST_DEBUG_INDEX 0x16c2 +#define mmDAC_TEST_DEBUG_DATA 0x16c3 +#define mmPERFCOUNTER_CNTL 0x170 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68 +#define mmPERFCOUNTER_STATE 0x171 +#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 +#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x365 +#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9 +#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25 +#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25 +#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25 +#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125 +#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325 +#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525 +#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725 +#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1 +#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69 +#define mmPERFMON_CNTL 0x173 +#define mmDC_PERFMON0_PERFMON_CNTL 0x173 +#define mmDC_PERFMON1_PERFMON_CNTL 0x367 +#define mmDC_PERFMON2_PERFMON_CNTL 0x18cb +#define mmDC_PERFMON3_PERFMON_CNTL 0x1b27 +#define mmDC_PERFMON4_PERFMON_CNTL 0x1d27 +#define mmDC_PERFMON5_PERFMON_CNTL 0x1f27 +#define mmDC_PERFMON6_PERFMON_CNTL 0x4127 +#define mmDC_PERFMON7_PERFMON_CNTL 0x4327 +#define mmDC_PERFMON8_PERFMON_CNTL 0x4527 +#define mmDC_PERFMON9_PERFMON_CNTL 0x4727 +#define mmDC_PERFMON10_PERFMON_CNTL 0x59a3 +#define mmDC_PERFMON11_PERFMON_CNTL 0x5f6b +#define mmPERFMON_CNTL2 0x17a +#define mmDC_PERFMON0_PERFMON_CNTL2 0x17a +#define mmDC_PERFMON1_PERFMON_CNTL2 0x36e +#define mmDC_PERFMON2_PERFMON_CNTL2 0x18d2 +#define mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e +#define mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e +#define mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e +#define mmDC_PERFMON6_PERFMON_CNTL2 0x412e +#define mmDC_PERFMON7_PERFMON_CNTL2 0x432e +#define mmDC_PERFMON8_PERFMON_CNTL2 0x452e +#define mmDC_PERFMON9_PERFMON_CNTL2 0x472e +#define mmDC_PERFMON10_PERFMON_CNTL2 0x59aa +#define mmDC_PERFMON11_PERFMON_CNTL2 0x5f72 +#define mmPERFMON_CVALUE_INT_MISC 0x172 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726 +#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a +#define mmPERFMON_CVALUE_LOW 0x174 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728 +#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4 +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c +#define mmPERFMON_HI 0x175 +#define mmDC_PERFMON0_PERFMON_HI 0x175 +#define mmDC_PERFMON1_PERFMON_HI 0x369 +#define mmDC_PERFMON2_PERFMON_HI 0x18cd +#define mmDC_PERFMON3_PERFMON_HI 0x1b29 +#define mmDC_PERFMON4_PERFMON_HI 0x1d29 +#define mmDC_PERFMON5_PERFMON_HI 0x1f29 +#define mmDC_PERFMON6_PERFMON_HI 0x4129 +#define mmDC_PERFMON7_PERFMON_HI 0x4329 +#define mmDC_PERFMON8_PERFMON_HI 0x4529 +#define mmDC_PERFMON9_PERFMON_HI 0x4729 +#define mmDC_PERFMON10_PERFMON_HI 0x59a5 +#define mmDC_PERFMON11_PERFMON_HI 0x5f6d +#define mmPERFMON_LOW 0x176 +#define mmDC_PERFMON0_PERFMON_LOW 0x176 +#define mmDC_PERFMON1_PERFMON_LOW 0x36a +#define mmDC_PERFMON2_PERFMON_LOW 0x18ce +#define mmDC_PERFMON3_PERFMON_LOW 0x1b2a +#define mmDC_PERFMON4_PERFMON_LOW 0x1d2a +#define mmDC_PERFMON5_PERFMON_LOW 0x1f2a +#define mmDC_PERFMON6_PERFMON_LOW 0x412a +#define mmDC_PERFMON7_PERFMON_LOW 0x432a +#define mmDC_PERFMON8_PERFMON_LOW 0x452a +#define mmDC_PERFMON9_PERFMON_LOW 0x472a +#define mmDC_PERFMON10_PERFMON_LOW 0x59a6 +#define mmDC_PERFMON11_PERFMON_LOW 0x5f6e +#define mmPERFMON_TEST_DEBUG_INDEX 0x177 +#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 +#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b +#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf +#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b +#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b +#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b +#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b +#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b +#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b +#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b +#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7 +#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f +#define mmPERFMON_TEST_DEBUG_DATA 0x178 +#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 +#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c +#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0 +#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c +#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c +#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c +#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c +#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c +#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c +#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c +#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8 +#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70 +#define mmREFCLK_CNTL 0x109 +#define mmDCCG_CBUS_WRCMD_DELAY 0x110 +#define mmDPREFCLK_CNTL 0x118 +#define mmAVSYNC_COUNTER_WRITE 0x12a +#define mmAVSYNC_COUNTER_CONTROL 0x12b +#define mmAVSYNC_COUNTER_READ 0x12f +#define mmDCCG_GTC_CNTL 0x120 +#define mmDCCG_GTC_DTO_INCR 0x121 +#define mmDCCG_GTC_DTO_MODULO 0x122 +#define mmDCCG_GTC_CURRENT 0x123 +#define mmDCCG_DS_DTO_INCR 0x113 +#define mmDCCG_DS_DTO_MODULO 0x114 +#define mmDCCG_DS_CNTL 0x115 +#define mmDCCG_DS_HW_CAL_INTERVAL 0x116 +#define mmDCCG_DS_DEBUG_CNTL 0x112 +#define mmDMCU_SMU_INTERRUPT_CNTL 0x12c +#define mmSMU_CONTROL 0x12d +#define mmSMU_INTERRUPT_CONTROL 0x12e +#define mmDAC_CLK_ENABLE 0x128 +#define mmDVO_CLK_ENABLE 0x129 +#define mmDCCG_GATE_DISABLE_CNTL 0x134 +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 +#define mmSCLK_CGTT_BLK_CTRL_REG 0x136 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108 +#define mmREFCLK_CGTT_BLK_CTRL_REG 0x10b +#define mmDCCG_CAC_STATUS 0x137 +#define mmPIXCLK1_RESYNC_CNTL 0x138 +#define mmPIXCLK2_RESYNC_CNTL 0x139 +#define mmPIXCLK0_RESYNC_CNTL 0x13a +#define mmMICROSECOND_TIME_BASE_DIV 0x13b +#define mmDCCG_DISP_CNTL_REG 0x13f +#define mmMILLISECOND_TIME_BASE_DIV 0x130 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x131 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132 +#define mmDCCG_PERFMON_CNTL 0x133 +#define mmDCCG_PERFMON_CNTL2 0x10e +#define mmCRTC0_PIXEL_RATE_CNTL 0x140 +#define mmDP_DTO0_PHASE 0x141 +#define mmDP_DTO0_MODULO 0x142 +#define mmCRTC1_PIXEL_RATE_CNTL 0x144 +#define mmDP_DTO1_PHASE 0x145 +#define mmDP_DTO1_MODULO 0x146 +#define mmCRTC2_PIXEL_RATE_CNTL 0x148 +#define mmDP_DTO2_PHASE 0x149 +#define mmDP_DTO2_MODULO 0x14a +#define mmCRTC3_PIXEL_RATE_CNTL 0x14c +#define mmDP_DTO3_PHASE 0x14d +#define mmDP_DTO3_MODULO 0x14e +#define mmCRTC4_PIXEL_RATE_CNTL 0x150 +#define mmDP_DTO4_PHASE 0x151 +#define mmDP_DTO4_MODULO 0x152 +#define mmCRTC5_PIXEL_RATE_CNTL 0x154 +#define mmDP_DTO5_PHASE 0x155 +#define mmDP_DTO5_MODULO 0x156 +#define mmDCCG_SOFT_RESET 0x15f +#define mmSYMCLKA_CLOCK_ENABLE 0x160 +#define mmSYMCLKB_CLOCK_ENABLE 0x161 +#define mmSYMCLKC_CLOCK_ENABLE 0x162 +#define mmSYMCLKD_CLOCK_ENABLE 0x163 +#define mmSYMCLKE_CLOCK_ENABLE 0x164 +#define mmSYMCLKF_CLOCK_ENABLE 0x165 +#define mmDPDBG_CLK_FORCE_CONTROL 0x10d +#define mmDVOACLKD_CNTL 0x168 +#define mmDVOACLKC_MVP_CNTL 0x169 +#define mmDVOACLKC_CNTL 0x16a +#define mmDCCG_AUDIO_DTO_SOURCE 0x16b +#define mmDCCG_AUDIO_DTO0_PHASE 0x16c +#define mmDCCG_AUDIO_DTO0_MODULE 0x16d +#define mmDCCG_AUDIO_DTO1_PHASE 0x16e +#define mmDCCG_AUDIO_DTO1_MODULE 0x16f +#define mmDCCG_TEST_DEBUG_INDEX 0x17c +#define mmDCCG_TEST_DEBUG_DATA 0x17d +#define mmDCCG_TEST_CLK_SEL 0x17e +#define mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4 +#define mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5 +#define mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6 +#define mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7 +#define mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8 +#define mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9 +#define mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa +#define mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb +#define mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc +#define mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd +#define mmCPLL_MACRO_CNTL_RESERVED10 0x5fda +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe +#define mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff +#define mmPLL_MACRO_CNTL_RESERVED0 0x1700 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754 +#define mmPLL_MACRO_CNTL_RESERVED1 0x1701 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755 +#define mmPLL_MACRO_CNTL_RESERVED2 0x1702 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756 +#define mmPLL_MACRO_CNTL_RESERVED3 0x1703 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757 +#define mmPLL_MACRO_CNTL_RESERVED4 0x1704 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758 +#define mmPLL_MACRO_CNTL_RESERVED5 0x1705 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759 +#define mmPLL_MACRO_CNTL_RESERVED6 0x1706 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a +#define mmPLL_MACRO_CNTL_RESERVED7 0x1707 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b +#define mmPLL_MACRO_CNTL_RESERVED8 0x1708 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c +#define mmPLL_MACRO_CNTL_RESERVED9 0x1709 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d +#define mmPLL_MACRO_CNTL_RESERVED10 0x170a +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e +#define mmPLL_MACRO_CNTL_RESERVED11 0x170b +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f +#define mmPLL_MACRO_CNTL_RESERVED12 0x170c +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760 +#define mmPLL_MACRO_CNTL_RESERVED13 0x170d +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761 +#define mmPLL_MACRO_CNTL_RESERVED14 0x170e +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762 +#define mmPLL_MACRO_CNTL_RESERVED15 0x170f +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763 +#define mmPLL_MACRO_CNTL_RESERVED16 0x1710 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764 +#define mmPLL_MACRO_CNTL_RESERVED17 0x1711 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765 +#define mmPLL_MACRO_CNTL_RESERVED18 0x1712 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766 +#define mmPLL_MACRO_CNTL_RESERVED19 0x1713 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767 +#define mmPLL_MACRO_CNTL_RESERVED20 0x1714 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768 +#define mmPLL_MACRO_CNTL_RESERVED21 0x1715 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769 +#define mmPLL_MACRO_CNTL_RESERVED22 0x1716 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a +#define mmPLL_MACRO_CNTL_RESERVED23 0x1717 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b +#define mmPLL_MACRO_CNTL_RESERVED24 0x1718 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c +#define mmPLL_MACRO_CNTL_RESERVED25 0x1719 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d +#define mmPLL_MACRO_CNTL_RESERVED26 0x171a +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e +#define mmPLL_MACRO_CNTL_RESERVED27 0x171b +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f +#define mmPLL_MACRO_CNTL_RESERVED28 0x171c +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770 +#define mmPLL_MACRO_CNTL_RESERVED29 0x171d +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771 +#define mmPLL_MACRO_CNTL_RESERVED30 0x171e +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772 +#define mmPLL_MACRO_CNTL_RESERVED31 0x171f +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773 +#define mmPLL_MACRO_CNTL_RESERVED32 0x1720 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774 +#define mmPLL_MACRO_CNTL_RESERVED33 0x1721 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775 +#define mmPLL_MACRO_CNTL_RESERVED34 0x1722 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776 +#define mmPLL_MACRO_CNTL_RESERVED35 0x1723 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777 +#define mmPLL_MACRO_CNTL_RESERVED36 0x1724 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778 +#define mmPLL_MACRO_CNTL_RESERVED37 0x1725 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779 +#define mmPLL_MACRO_CNTL_RESERVED38 0x1726 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a +#define mmPLL_MACRO_CNTL_RESERVED39 0x1727 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b +#define mmPLL_MACRO_CNTL_RESERVED40 0x1728 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c +#define mmPLL_MACRO_CNTL_RESERVED41 0x1729 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d +#define mmDENTIST_DISPCLK_CNTL 0x124 +#define mmDCDEBUG_BUS_CLK1_SEL 0x16c4 +#define mmDCDEBUG_BUS_CLK2_SEL 0x16c5 +#define mmDCDEBUG_BUS_CLK3_SEL 0x16c6 +#define mmDCDEBUG_BUS_CLK4_SEL 0x16c7 +#define mmDCDEBUG_BUS_CLK5_SEL 0x16c8 +#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9 +#define mmDCDEBUG_OUT_CNTL 0x16ca +#define mmDCDEBUG_OUT_DATA 0x16cb +#define mmDMIF_ADDR_CONFIG 0x2f5 +#define mmDMIF_CONTROL 0x2f6 +#define mmDMIF_STATUS 0x2f7 +#define mmDMIF_HW_DEBUG 0x2f8 +#define mmDMIF_ARBITRATION_CONTROL 0x2f9 +#define mmPIPE0_ARBITRATION_CONTROL3 0x2fa +#define mmPIPE1_ARBITRATION_CONTROL3 0x2fb +#define mmPIPE2_ARBITRATION_CONTROL3 0x2fc +#define mmPIPE3_ARBITRATION_CONTROL3 0x2fd +#define mmPIPE4_ARBITRATION_CONTROL3 0x2fe +#define mmPIPE5_ARBITRATION_CONTROL3 0x2ff +#define mmPIPE6_ARBITRATION_CONTROL3 0x32a +#define mmPIPE7_ARBITRATION_CONTROL3 0x32b +#define mmDMIF_P_VMID 0x300 +#define mmDMIF_URG_OVERRIDE 0x329 +#define mmDMIF_TEST_DEBUG_INDEX 0x301 +#define mmDMIF_TEST_DEBUG_DATA 0x302 +#define ixDMIF_DEBUG02_CORE0 0x2 +#define ixDMIF_DEBUG02_CORE1 0xa +#define mmDMIF_ADDR_CALC 0x303 +#define mmDMIF_STATUS2 0x304 +#define mmPIPE0_MAX_REQUESTS 0x305 +#define mmPIPE1_MAX_REQUESTS 0x306 +#define mmPIPE2_MAX_REQUESTS 0x307 +#define mmPIPE3_MAX_REQUESTS 0x308 +#define mmPIPE4_MAX_REQUESTS 0x309 +#define mmPIPE5_MAX_REQUESTS 0x30a +#define mmPIPE6_MAX_REQUESTS 0x32c +#define mmPIPE7_MAX_REQUESTS 0x32d +#define mmLOW_POWER_TILING_CONTROL 0x30b +#define mmMCIF_CONTROL 0x30c +#define mmMCIF_WRITE_COMBINE_CONTROL 0x30d +#define mmMCIF_TEST_DEBUG_INDEX 0x30e +#define mmMCIF_TEST_DEBUG_DATA 0x30f +#define ixIDDCCIF02_DBG_DCCIF_C 0x9 +#define ixIDDCCIF04_DBG_DCCIF_E 0xb +#define ixIDDCCIF05_DBG_DCCIF_F 0xc +#define mmMCIF_VMID 0x310 +#define mmMCIF_MEM_CONTROL 0x311 +#define mmCC_DC_PIPE_DIS 0x312 +#define mmMC_DC_INTERFACE_NACK_STATUS 0x313 +#define mmRBBMIF_TIMEOUT 0x314 +#define mmRBBMIF_STATUS 0x315 +#define mmRBBMIF_TIMEOUT_DIS 0x316 +#define mmRBBMIF_STATUS_FLAG 0x327 +#define mmDCI_MEM_PWR_STATUS 0x317 +#define mmDCI_MEM_PWR_STATUS2 0x318 +#define mmDCI_CLK_CNTL 0x319 +#define mmDCI_MEM_PWR_CNTL 0x31b +#define mmDCI_MEM_PWR_CNTL2 0x31c +#define mmDCI_MEM_PWR_CNTL3 0x31d +#define mmDCI_SOFT_RESET 0x328 +#define mmDCI_TEST_DEBUG_INDEX 0x31e +#define mmDCI_TEST_DEBUG_DATA 0x31f +#define mmDCI_DEBUG_CONFIG 0x320 +#define mmPIPE0_DMIF_BUFFER_CONTROL 0x321 +#define mmPIPE1_DMIF_BUFFER_CONTROL 0x322 +#define mmPIPE2_DMIF_BUFFER_CONTROL 0x323 +#define mmPIPE3_DMIF_BUFFER_CONTROL 0x324 +#define mmPIPE4_DMIF_BUFFER_CONTROL 0x325 +#define mmPIPE5_DMIF_BUFFER_CONTROL 0x326 +#define mmDC_GENERICA 0x4800 +#define mmDC_GENERICB 0x4801 +#define mmDC_PAD_EXTERN_SIG 0x4802 +#define mmDC_REF_CLK_CNTL 0x4803 +#define mmDC_GPIO_DEBUG 0x4804 +#define mmUNIPHYA_LINK_CNTL 0x4805 +#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806 +#define mmUNIPHYB_LINK_CNTL 0x4807 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808 +#define mmUNIPHYC_LINK_CNTL 0x4809 +#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a +#define mmUNIPHYD_LINK_CNTL 0x480b +#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c +#define mmUNIPHYE_LINK_CNTL 0x480d +#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e +#define mmUNIPHYF_LINK_CNTL 0x480f +#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810 +#define mmUNIPHYG_LINK_CNTL 0x4811 +#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812 +#define mmUNIPHY_IMPCAL_LINKA 0x4838 +#define mmUNIPHY_IMPCAL_LINKB 0x4839 +#define mmUNIPHY_IMPCAL_LINKC 0x483f +#define mmUNIPHY_IMPCAL_LINKD 0x4840 +#define mmUNIPHY_IMPCAL_LINKE 0x4843 +#define mmUNIPHY_IMPCAL_LINKF 0x4844 +#define mmUNIPHY_IMPCAL_PERIOD 0x483a +#define mmAUXP_IMPCAL 0x483b +#define mmAUXN_IMPCAL 0x483c +#define mmDCIO_IMPCAL_CNTL 0x483d +#define mmUNIPHY_IMPCAL_PSW_AB 0x483e +#define mmDCIO_IMPCAL_CNTL_CD 0x4841 +#define mmUNIPHY_IMPCAL_PSW_CD 0x4842 +#define mmDCIO_IMPCAL_CNTL_EF 0x4845 +#define mmUNIPHY_IMPCAL_PSW_EF 0x4846 +#define mmDCIO_WRCMD_DELAY 0x4816 +#define mmDC_PINSTRAPS 0x4818 +#define mmDC_DVODATA_CONFIG 0x481a +#define mmLVTMA_PWRSEQ_CNTL 0x481b +#define mmLVTMA_PWRSEQ_STATE 0x481c +#define mmLVTMA_PWRSEQ_REF_DIV 0x481d +#define mmLVTMA_PWRSEQ_DELAY1 0x481e +#define mmLVTMA_PWRSEQ_DELAY2 0x481f +#define mmBL_PWM_CNTL 0x4820 +#define mmBL_PWM_CNTL2 0x4821 +#define mmBL_PWM_PERIOD_CNTL 0x4822 +#define mmBL_PWM_GRP1_REG_LOCK 0x4823 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x4824 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825 +#define mmDCIO_GSL0_CNTL 0x4826 +#define mmDCIO_GSL1_CNTL 0x4827 +#define mmDCIO_GSL2_CNTL 0x4828 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829 +#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a +#define mmDC_GPU_TIMER_READ 0x482b +#define mmDC_GPU_TIMER_READ_CNTL 0x482c +#define mmDCIO_CLOCK_CNTL 0x482d +#define mmDCIO_DEBUG 0x482f +#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830 +#define mmDBG_OUT_CNTL 0x4834 +#define mmDCIO_DEBUG_CONFIG 0x4835 +#define mmDCIO_SOFT_RESET 0x4836 +#define mmDCIO_DPHY_SEL 0x4837 +#define mmDCIO_TEST_DEBUG_INDEX 0x4831 +#define mmDCIO_TEST_DEBUG_DATA 0x4832 +#define ixDCIO_DEBUG1 0x1 +#define ixDCIO_DEBUG2 0x2 +#define ixDCIO_DEBUG3 0x3 +#define ixDCIO_DEBUG4 0x4 +#define ixDCIO_DEBUG5 0x5 +#define ixDCIO_DEBUG6 0x6 +#define ixDCIO_DEBUG7 0x7 +#define ixDCIO_DEBUG8 0x8 +#define ixDCIO_DEBUG9 0x9 +#define ixDCIO_DEBUGA 0xa +#define ixDCIO_DEBUGB 0xb +#define ixDCIO_DEBUGC 0xc +#define ixDCIO_DEBUGD 0xd +#define ixDCIO_DEBUGE 0xe +#define ixDCIO_DEBUGF 0xf +#define ixDCIO_DEBUG10 0x10 +#define ixDCIO_DEBUG11 0x11 +#define ixDCIO_DEBUG12 0x12 +#define ixDCIO_DEBUG13 0x13 +#define ixDCIO_DEBUG14 0x14 +#define ixDCIO_DEBUG15 0x15 +#define ixDCIO_DEBUG16 0x16 +#define ixDCIO_DEBUG_ID 0x0 +#define mmDC_GPIO_GENERIC_MASK 0x4860 +#define mmDC_GPIO_GENERIC_A 0x4861 +#define mmDC_GPIO_GENERIC_EN 0x4862 +#define mmDC_GPIO_GENERIC_Y 0x4863 +#define mmDC_GPIO_DVODATA_MASK 0x4864 +#define mmDC_GPIO_DVODATA_A 0x4865 +#define mmDC_GPIO_DVODATA_EN 0x4866 +#define mmDC_GPIO_DVODATA_Y 0x4867 +#define mmDC_GPIO_DDC1_MASK 0x4868 +#define mmDC_GPIO_DDC1_A 0x4869 +#define mmDC_GPIO_DDC1_EN 0x486a +#define mmDC_GPIO_DDC1_Y 0x486b +#define mmDC_GPIO_DDC2_MASK 0x486c +#define mmDC_GPIO_DDC2_A 0x486d +#define mmDC_GPIO_DDC2_EN 0x486e +#define mmDC_GPIO_DDC2_Y 0x486f +#define mmDC_GPIO_DDC3_MASK 0x4870 +#define mmDC_GPIO_DDC3_A 0x4871 +#define mmDC_GPIO_DDC3_EN 0x4872 +#define mmDC_GPIO_DDC3_Y 0x4873 +#define mmDC_GPIO_DDC4_MASK 0x4874 +#define mmDC_GPIO_DDC4_A 0x4875 +#define mmDC_GPIO_DDC4_EN 0x4876 +#define mmDC_GPIO_DDC4_Y 0x4877 +#define mmDC_GPIO_DDC5_MASK 0x4878 +#define mmDC_GPIO_DDC5_A 0x4879 +#define mmDC_GPIO_DDC5_EN 0x487a +#define mmDC_GPIO_DDC5_Y 0x487b +#define mmDC_GPIO_DDC6_MASK 0x487c +#define mmDC_GPIO_DDC6_A 0x487d +#define mmDC_GPIO_DDC6_EN 0x487e +#define mmDC_GPIO_DDC6_Y 0x487f +#define mmDC_GPIO_DDCVGA_MASK 0x4880 +#define mmDC_GPIO_DDCVGA_A 0x4881 +#define mmDC_GPIO_DDCVGA_EN 0x4882 +#define mmDC_GPIO_DDCVGA_Y 0x4883 +#define mmDC_GPIO_SYNCA_MASK 0x4884 +#define mmDC_GPIO_SYNCA_A 0x4885 +#define mmDC_GPIO_SYNCA_EN 0x4886 +#define mmDC_GPIO_SYNCA_Y 0x4887 +#define mmDC_GPIO_GENLK_MASK 0x4888 +#define mmDC_GPIO_GENLK_A 0x4889 +#define mmDC_GPIO_GENLK_EN 0x488a +#define mmDC_GPIO_GENLK_Y 0x488b +#define mmDC_GPIO_HPD_MASK 0x488c +#define mmDC_GPIO_HPD_A 0x488d +#define mmDC_GPIO_HPD_EN 0x488e +#define mmDC_GPIO_HPD_Y 0x488f +#define mmDC_GPIO_PWRSEQ_MASK 0x4890 +#define mmDC_GPIO_PWRSEQ_A 0x4891 +#define mmDC_GPIO_PWRSEQ_EN 0x4892 +#define mmDC_GPIO_PWRSEQ_Y 0x4893 +#define mmDC_GPIO_PAD_STRENGTH_1 0x4894 +#define mmDC_GPIO_PAD_STRENGTH_2 0x4895 +#define mmPHY_AUX_CNTL 0x4897 +#define mmDC_GPIO_I2CPAD_A 0x4899 +#define mmDC_GPIO_I2CPAD_EN 0x489a +#define mmDC_GPIO_I2CPAD_Y 0x489b +#define mmDC_GPIO_I2CPAD_STRENGTH 0x489c +#define mmDVO_STRENGTH_CONTROL 0x489d +#define mmDVO_VREF_CONTROL 0x489e +#define mmDVO_SKEW_ADJUST 0x489f +#define mmDAC_MACRO_CNTL_RESERVED0 0x48b8 +#define mmDAC_MACRO_CNTL_RESERVED1 0x48b9 +#define mmDAC_MACRO_CNTL_RESERVED2 0x48ba +#define mmDAC_MACRO_CNTL_RESERVED3 0x48bb +#define mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980 +#define mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981 +#define mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982 +#define mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983 +#define mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984 +#define mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985 +#define mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986 +#define mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987 +#define mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988 +#define mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989 +#define mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a +#define mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b +#define mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c +#define mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d +#define mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e +#define mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f +#define mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990 +#define mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991 +#define mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992 +#define mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993 +#define mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994 +#define mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995 +#define mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996 +#define mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997 +#define mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998 +#define mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999 +#define mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a +#define mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b +#define mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c +#define mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d +#define mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e +#define mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab +#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac +#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad +#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae +#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba +#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca +#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace +#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada +#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add +#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade +#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea +#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec +#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed +#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee +#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef +#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff +#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab +#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac +#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad +#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae +#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba +#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca +#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce +#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda +#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde +#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea +#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec +#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed +#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee +#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef +#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff +#define mmDPHY_MACRO_CNTL_RESERVED0 0x5d98 +#define mmDPHY_MACRO_CNTL_RESERVED1 0x5d99 +#define mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a +#define mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b +#define mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c +#define mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d +#define mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e +#define mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f +#define mmDPHY_MACRO_CNTL_RESERVED8 0x5da0 +#define mmDPHY_MACRO_CNTL_RESERVED9 0x5da1 +#define mmDPHY_MACRO_CNTL_RESERVED10 0x5da2 +#define mmDPHY_MACRO_CNTL_RESERVED11 0x5da3 +#define mmDPHY_MACRO_CNTL_RESERVED12 0x5da4 +#define mmDPHY_MACRO_CNTL_RESERVED13 0x5da5 +#define mmDPHY_MACRO_CNTL_RESERVED14 0x5da6 +#define mmDPHY_MACRO_CNTL_RESERVED15 0x5da7 +#define mmDPHY_MACRO_CNTL_RESERVED16 0x5da8 +#define mmDPHY_MACRO_CNTL_RESERVED17 0x5da9 +#define mmDPHY_MACRO_CNTL_RESERVED18 0x5daa +#define mmDPHY_MACRO_CNTL_RESERVED19 0x5dab +#define mmDPHY_MACRO_CNTL_RESERVED20 0x5dac +#define mmDPHY_MACRO_CNTL_RESERVED21 0x5dad +#define mmDPHY_MACRO_CNTL_RESERVED22 0x5dae +#define mmDPHY_MACRO_CNTL_RESERVED23 0x5daf +#define mmDPHY_MACRO_CNTL_RESERVED24 0x5db0 +#define mmDPHY_MACRO_CNTL_RESERVED25 0x5db1 +#define mmDPHY_MACRO_CNTL_RESERVED26 0x5db2 +#define mmDPHY_MACRO_CNTL_RESERVED27 0x5db3 +#define mmDPHY_MACRO_CNTL_RESERVED28 0x5db4 +#define mmDPHY_MACRO_CNTL_RESERVED29 0x5db5 +#define mmDPHY_MACRO_CNTL_RESERVED30 0x5db6 +#define mmDPHY_MACRO_CNTL_RESERVED31 0x5db7 +#define mmDPHY_MACRO_CNTL_RESERVED32 0x5db8 +#define mmDPHY_MACRO_CNTL_RESERVED33 0x5db9 +#define mmDPHY_MACRO_CNTL_RESERVED34 0x5dba +#define mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb +#define mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc +#define mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd +#define mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe +#define mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf +#define mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0 +#define mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1 +#define mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2 +#define mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3 +#define mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4 +#define mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5 +#define mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6 +#define mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7 +#define mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8 +#define mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9 +#define mmDPHY_MACRO_CNTL_RESERVED50 0x5dca +#define mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb +#define mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc +#define mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd +#define mmDPHY_MACRO_CNTL_RESERVED54 0x5dce +#define mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf +#define mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0 +#define mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1 +#define mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2 +#define mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3 +#define mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4 +#define mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5 +#define mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6 +#define mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7 +#define mmGRPH_ENABLE 0x1a00 +#define mmDCP0_GRPH_ENABLE 0x1a00 +#define mmDCP1_GRPH_ENABLE 0x1c00 +#define mmDCP2_GRPH_ENABLE 0x1e00 +#define mmDCP3_GRPH_ENABLE 0x4000 +#define mmDCP4_GRPH_ENABLE 0x4200 +#define mmDCP5_GRPH_ENABLE 0x4400 +#define mmGRPH_CONTROL 0x1a01 +#define mmDCP0_GRPH_CONTROL 0x1a01 +#define mmDCP1_GRPH_CONTROL 0x1c01 +#define mmDCP2_GRPH_CONTROL 0x1e01 +#define mmDCP3_GRPH_CONTROL 0x4001 +#define mmDCP4_GRPH_CONTROL 0x4201 +#define mmDCP5_GRPH_CONTROL 0x4401 +#define mmGRPH_LUT_10BIT_BYPASS 0x1a02 +#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 +#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02 +#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02 +#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002 +#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202 +#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402 +#define mmGRPH_SWAP_CNTL 0x1a03 +#define mmDCP0_GRPH_SWAP_CNTL 0x1a03 +#define mmDCP1_GRPH_SWAP_CNTL 0x1c03 +#define mmDCP2_GRPH_SWAP_CNTL 0x1e03 +#define mmDCP3_GRPH_SWAP_CNTL 0x4003 +#define mmDCP4_GRPH_SWAP_CNTL 0x4203 +#define mmDCP5_GRPH_SWAP_CNTL 0x4403 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405 +#define mmGRPH_PITCH 0x1a06 +#define mmDCP0_GRPH_PITCH 0x1a06 +#define mmDCP1_GRPH_PITCH 0x1c06 +#define mmDCP2_GRPH_PITCH 0x1e06 +#define mmDCP3_GRPH_PITCH 0x4006 +#define mmDCP4_GRPH_PITCH 0x4206 +#define mmDCP5_GRPH_PITCH 0x4406 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408 +#define mmGRPH_SURFACE_OFFSET_X 0x1a09 +#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 +#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09 +#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09 +#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009 +#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209 +#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409 +#define mmGRPH_SURFACE_OFFSET_Y 0x1a0a +#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a +#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a +#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a +#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a +#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a +#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a +#define mmGRPH_X_START 0x1a0b +#define mmDCP0_GRPH_X_START 0x1a0b +#define mmDCP1_GRPH_X_START 0x1c0b +#define mmDCP2_GRPH_X_START 0x1e0b +#define mmDCP3_GRPH_X_START 0x400b +#define mmDCP4_GRPH_X_START 0x420b +#define mmDCP5_GRPH_X_START 0x440b +#define mmGRPH_Y_START 0x1a0c +#define mmDCP0_GRPH_Y_START 0x1a0c +#define mmDCP1_GRPH_Y_START 0x1c0c +#define mmDCP2_GRPH_Y_START 0x1e0c +#define mmDCP3_GRPH_Y_START 0x400c +#define mmDCP4_GRPH_Y_START 0x420c +#define mmDCP5_GRPH_Y_START 0x440c +#define mmGRPH_X_END 0x1a0d +#define mmDCP0_GRPH_X_END 0x1a0d +#define mmDCP1_GRPH_X_END 0x1c0d +#define mmDCP2_GRPH_X_END 0x1e0d +#define mmDCP3_GRPH_X_END 0x400d +#define mmDCP4_GRPH_X_END 0x420d +#define mmDCP5_GRPH_X_END 0x440d +#define mmGRPH_Y_END 0x1a0e +#define mmDCP0_GRPH_Y_END 0x1a0e +#define mmDCP1_GRPH_Y_END 0x1c0e +#define mmDCP2_GRPH_Y_END 0x1e0e +#define mmDCP3_GRPH_Y_END 0x400e +#define mmDCP4_GRPH_Y_END 0x420e +#define mmDCP5_GRPH_Y_END 0x440e +#define mmINPUT_GAMMA_CONTROL 0x1a10 +#define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 +#define mmDCP1_INPUT_GAMMA_CONTROL 0x1c10 +#define mmDCP2_INPUT_GAMMA_CONTROL 0x1e10 +#define mmDCP3_INPUT_GAMMA_CONTROL 0x4010 +#define mmDCP4_INPUT_GAMMA_CONTROL 0x4210 +#define mmDCP5_INPUT_GAMMA_CONTROL 0x4410 +#define mmGRPH_UPDATE 0x1a11 +#define mmDCP0_GRPH_UPDATE 0x1a11 +#define mmDCP1_GRPH_UPDATE 0x1c11 +#define mmDCP2_GRPH_UPDATE 0x1e11 +#define mmDCP3_GRPH_UPDATE 0x4011 +#define mmDCP4_GRPH_UPDATE 0x4211 +#define mmDCP5_GRPH_UPDATE 0x4411 +#define mmGRPH_FLIP_CONTROL 0x1a12 +#define mmDCP0_GRPH_FLIP_CONTROL 0x1a12 +#define mmDCP1_GRPH_FLIP_CONTROL 0x1c12 +#define mmDCP2_GRPH_FLIP_CONTROL 0x1e12 +#define mmDCP3_GRPH_FLIP_CONTROL 0x4012 +#define mmDCP4_GRPH_FLIP_CONTROL 0x4212 +#define mmDCP5_GRPH_FLIP_CONTROL 0x4412 +#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13 +#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13 +#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013 +#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213 +#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413 +#define mmGRPH_DFQ_CONTROL 0x1a14 +#define mmDCP0_GRPH_DFQ_CONTROL 0x1a14 +#define mmDCP1_GRPH_DFQ_CONTROL 0x1c14 +#define mmDCP2_GRPH_DFQ_CONTROL 0x1e14 +#define mmDCP3_GRPH_DFQ_CONTROL 0x4014 +#define mmDCP4_GRPH_DFQ_CONTROL 0x4214 +#define mmDCP5_GRPH_DFQ_CONTROL 0x4414 +#define mmGRPH_DFQ_STATUS 0x1a15 +#define mmDCP0_GRPH_DFQ_STATUS 0x1a15 +#define mmDCP1_GRPH_DFQ_STATUS 0x1c15 +#define mmDCP2_GRPH_DFQ_STATUS 0x1e15 +#define mmDCP3_GRPH_DFQ_STATUS 0x4015 +#define mmDCP4_GRPH_DFQ_STATUS 0x4215 +#define mmDCP5_GRPH_DFQ_STATUS 0x4415 +#define mmGRPH_INTERRUPT_STATUS 0x1a16 +#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 +#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16 +#define mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16 +#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4016 +#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4216 +#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4416 +#define mmGRPH_INTERRUPT_CONTROL 0x1a17 +#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 +#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17 +#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17 +#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017 +#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217 +#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417 +#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18 +#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18 +#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 +#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218 +#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418 +#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419 +#define mmGRPH_COMPRESS_PITCH 0x1a1a +#define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a +#define mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a +#define mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a +#define mmDCP3_GRPH_COMPRESS_PITCH 0x401a +#define mmDCP4_GRPH_COMPRESS_PITCH 0x421a +#define mmDCP5_GRPH_COMPRESS_PITCH 0x441a +#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b +#define mmOVL_ENABLE 0x1a1c +#define mmDCP0_OVL_ENABLE 0x1a1c +#define mmDCP1_OVL_ENABLE 0x1c1c +#define mmDCP2_OVL_ENABLE 0x1e1c +#define mmDCP3_OVL_ENABLE 0x401c +#define mmDCP4_OVL_ENABLE 0x421c +#define mmDCP5_OVL_ENABLE 0x441c +#define mmOVL_CONTROL1 0x1a1d +#define mmDCP0_OVL_CONTROL1 0x1a1d +#define mmDCP1_OVL_CONTROL1 0x1c1d +#define mmDCP2_OVL_CONTROL1 0x1e1d +#define mmDCP3_OVL_CONTROL1 0x401d +#define mmDCP4_OVL_CONTROL1 0x421d +#define mmDCP5_OVL_CONTROL1 0x441d +#define mmOVL_CONTROL2 0x1a1e +#define mmDCP0_OVL_CONTROL2 0x1a1e +#define mmDCP1_OVL_CONTROL2 0x1c1e +#define mmDCP2_OVL_CONTROL2 0x1e1e +#define mmDCP3_OVL_CONTROL2 0x401e +#define mmDCP4_OVL_CONTROL2 0x421e +#define mmDCP5_OVL_CONTROL2 0x441e +#define mmOVL_SWAP_CNTL 0x1a1f +#define mmDCP0_OVL_SWAP_CNTL 0x1a1f +#define mmDCP1_OVL_SWAP_CNTL 0x1c1f +#define mmDCP2_OVL_SWAP_CNTL 0x1e1f +#define mmDCP3_OVL_SWAP_CNTL 0x401f +#define mmDCP4_OVL_SWAP_CNTL 0x421f +#define mmDCP5_OVL_SWAP_CNTL 0x441f +#define mmOVL_SURFACE_ADDRESS 0x1a20 +#define mmDCP0_OVL_SURFACE_ADDRESS 0x1a20 +#define mmDCP1_OVL_SURFACE_ADDRESS 0x1c20 +#define mmDCP2_OVL_SURFACE_ADDRESS 0x1e20 +#define mmDCP3_OVL_SURFACE_ADDRESS 0x4020 +#define mmDCP4_OVL_SURFACE_ADDRESS 0x4220 +#define mmDCP5_OVL_SURFACE_ADDRESS 0x4420 +#define mmOVL_PITCH 0x1a21 +#define mmDCP0_OVL_PITCH 0x1a21 +#define mmDCP1_OVL_PITCH 0x1c21 +#define mmDCP2_OVL_PITCH 0x1e21 +#define mmDCP3_OVL_PITCH 0x4021 +#define mmDCP4_OVL_PITCH 0x4221 +#define mmDCP5_OVL_PITCH 0x4421 +#define mmOVL_SURFACE_ADDRESS_HIGH 0x1a22 +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22 +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1c22 +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x1e22 +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4022 +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4222 +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4422 +#define mmOVL_SURFACE_OFFSET_X 0x1a23 +#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23 +#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1c23 +#define mmDCP2_OVL_SURFACE_OFFSET_X 0x1e23 +#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4023 +#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4223 +#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4423 +#define mmOVL_SURFACE_OFFSET_Y 0x1a24 +#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24 +#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1c24 +#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x1e24 +#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4024 +#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4224 +#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4424 +#define mmOVL_START 0x1a25 +#define mmDCP0_OVL_START 0x1a25 +#define mmDCP1_OVL_START 0x1c25 +#define mmDCP2_OVL_START 0x1e25 +#define mmDCP3_OVL_START 0x4025 +#define mmDCP4_OVL_START 0x4225 +#define mmDCP5_OVL_START 0x4425 +#define mmOVL_END 0x1a26 +#define mmDCP0_OVL_END 0x1a26 +#define mmDCP1_OVL_END 0x1c26 +#define mmDCP2_OVL_END 0x1e26 +#define mmDCP3_OVL_END 0x4026 +#define mmDCP4_OVL_END 0x4226 +#define mmDCP5_OVL_END 0x4426 +#define mmOVL_UPDATE 0x1a27 +#define mmDCP0_OVL_UPDATE 0x1a27 +#define mmDCP1_OVL_UPDATE 0x1c27 +#define mmDCP2_OVL_UPDATE 0x1e27 +#define mmDCP3_OVL_UPDATE 0x4027 +#define mmDCP4_OVL_UPDATE 0x4227 +#define mmDCP5_OVL_UPDATE 0x4427 +#define mmOVL_SURFACE_ADDRESS_INUSE 0x1a28 +#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28 +#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1c28 +#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x1e28 +#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4028 +#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4228 +#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4428 +#define mmOVL_DFQ_CONTROL 0x1a29 +#define mmDCP0_OVL_DFQ_CONTROL 0x1a29 +#define mmDCP1_OVL_DFQ_CONTROL 0x1c29 +#define mmDCP2_OVL_DFQ_CONTROL 0x1e29 +#define mmDCP3_OVL_DFQ_CONTROL 0x4029 +#define mmDCP4_OVL_DFQ_CONTROL 0x4229 +#define mmDCP5_OVL_DFQ_CONTROL 0x4429 +#define mmOVL_DFQ_STATUS 0x1a2a +#define mmDCP0_OVL_DFQ_STATUS 0x1a2a +#define mmDCP1_OVL_DFQ_STATUS 0x1c2a +#define mmDCP2_OVL_DFQ_STATUS 0x1e2a +#define mmDCP3_OVL_DFQ_STATUS 0x402a +#define mmDCP4_OVL_DFQ_STATUS 0x422a +#define mmDCP5_OVL_DFQ_STATUS 0x442a +#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b +#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b +#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1c2b +#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1e2b +#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b +#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x422b +#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x442b +#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c +#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c +#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1c2c +#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x1e2c +#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x402c +#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x422c +#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x442c +#define mmPRESCALE_GRPH_CONTROL 0x1a2d +#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d +#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d +#define mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d +#define mmDCP3_PRESCALE_GRPH_CONTROL 0x402d +#define mmDCP4_PRESCALE_GRPH_CONTROL 0x422d +#define mmDCP5_PRESCALE_GRPH_CONTROL 0x442d +#define mmPRESCALE_VALUES_GRPH_R 0x1a2e +#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e +#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e +#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e +#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e +#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e +#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e +#define mmPRESCALE_VALUES_GRPH_G 0x1a2f +#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f +#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f +#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f +#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f +#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f +#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f +#define mmPRESCALE_VALUES_GRPH_B 0x1a30 +#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 +#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30 +#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30 +#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030 +#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230 +#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430 +#define mmPRESCALE_OVL_CONTROL 0x1a31 +#define mmDCP0_PRESCALE_OVL_CONTROL 0x1a31 +#define mmDCP1_PRESCALE_OVL_CONTROL 0x1c31 +#define mmDCP2_PRESCALE_OVL_CONTROL 0x1e31 +#define mmDCP3_PRESCALE_OVL_CONTROL 0x4031 +#define mmDCP4_PRESCALE_OVL_CONTROL 0x4231 +#define mmDCP5_PRESCALE_OVL_CONTROL 0x4431 +#define mmPRESCALE_VALUES_OVL_CB 0x1a32 +#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32 +#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1c32 +#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x1e32 +#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4032 +#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4232 +#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4432 +#define mmPRESCALE_VALUES_OVL_Y 0x1a33 +#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33 +#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1c33 +#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x1e33 +#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4033 +#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4233 +#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4433 +#define mmPRESCALE_VALUES_OVL_CR 0x1a34 +#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34 +#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1c34 +#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x1e34 +#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4034 +#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4234 +#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4434 +#define mmINPUT_CSC_CONTROL 0x1a35 +#define mmDCP0_INPUT_CSC_CONTROL 0x1a35 +#define mmDCP1_INPUT_CSC_CONTROL 0x1c35 +#define mmDCP2_INPUT_CSC_CONTROL 0x1e35 +#define mmDCP3_INPUT_CSC_CONTROL 0x4035 +#define mmDCP4_INPUT_CSC_CONTROL 0x4235 +#define mmDCP5_INPUT_CSC_CONTROL 0x4435 +#define mmINPUT_CSC_C11_C12 0x1a36 +#define mmDCP0_INPUT_CSC_C11_C12 0x1a36 +#define mmDCP1_INPUT_CSC_C11_C12 0x1c36 +#define mmDCP2_INPUT_CSC_C11_C12 0x1e36 +#define mmDCP3_INPUT_CSC_C11_C12 0x4036 +#define mmDCP4_INPUT_CSC_C11_C12 0x4236 +#define mmDCP5_INPUT_CSC_C11_C12 0x4436 +#define mmINPUT_CSC_C13_C14 0x1a37 +#define mmDCP0_INPUT_CSC_C13_C14 0x1a37 +#define mmDCP1_INPUT_CSC_C13_C14 0x1c37 +#define mmDCP2_INPUT_CSC_C13_C14 0x1e37 +#define mmDCP3_INPUT_CSC_C13_C14 0x4037 +#define mmDCP4_INPUT_CSC_C13_C14 0x4237 +#define mmDCP5_INPUT_CSC_C13_C14 0x4437 +#define mmINPUT_CSC_C21_C22 0x1a38 +#define mmDCP0_INPUT_CSC_C21_C22 0x1a38 +#define mmDCP1_INPUT_CSC_C21_C22 0x1c38 +#define mmDCP2_INPUT_CSC_C21_C22 0x1e38 +#define mmDCP3_INPUT_CSC_C21_C22 0x4038 +#define mmDCP4_INPUT_CSC_C21_C22 0x4238 +#define mmDCP5_INPUT_CSC_C21_C22 0x4438 +#define mmINPUT_CSC_C23_C24 0x1a39 +#define mmDCP0_INPUT_CSC_C23_C24 0x1a39 +#define mmDCP1_INPUT_CSC_C23_C24 0x1c39 +#define mmDCP2_INPUT_CSC_C23_C24 0x1e39 +#define mmDCP3_INPUT_CSC_C23_C24 0x4039 +#define mmDCP4_INPUT_CSC_C23_C24 0x4239 +#define mmDCP5_INPUT_CSC_C23_C24 0x4439 +#define mmINPUT_CSC_C31_C32 0x1a3a +#define mmDCP0_INPUT_CSC_C31_C32 0x1a3a +#define mmDCP1_INPUT_CSC_C31_C32 0x1c3a +#define mmDCP2_INPUT_CSC_C31_C32 0x1e3a +#define mmDCP3_INPUT_CSC_C31_C32 0x403a +#define mmDCP4_INPUT_CSC_C31_C32 0x423a +#define mmDCP5_INPUT_CSC_C31_C32 0x443a +#define mmINPUT_CSC_C33_C34 0x1a3b +#define mmDCP0_INPUT_CSC_C33_C34 0x1a3b +#define mmDCP1_INPUT_CSC_C33_C34 0x1c3b +#define mmDCP2_INPUT_CSC_C33_C34 0x1e3b +#define mmDCP3_INPUT_CSC_C33_C34 0x403b +#define mmDCP4_INPUT_CSC_C33_C34 0x423b +#define mmDCP5_INPUT_CSC_C33_C34 0x443b +#define mmOUTPUT_CSC_CONTROL 0x1a3c +#define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c +#define mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c +#define mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c +#define mmDCP3_OUTPUT_CSC_CONTROL 0x403c +#define mmDCP4_OUTPUT_CSC_CONTROL 0x423c +#define mmDCP5_OUTPUT_CSC_CONTROL 0x443c +#define mmOUTPUT_CSC_C11_C12 0x1a3d +#define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d +#define mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d +#define mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d +#define mmDCP3_OUTPUT_CSC_C11_C12 0x403d +#define mmDCP4_OUTPUT_CSC_C11_C12 0x423d +#define mmDCP5_OUTPUT_CSC_C11_C12 0x443d +#define mmOUTPUT_CSC_C13_C14 0x1a3e +#define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e +#define mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e +#define mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e +#define mmDCP3_OUTPUT_CSC_C13_C14 0x403e +#define mmDCP4_OUTPUT_CSC_C13_C14 0x423e +#define mmDCP5_OUTPUT_CSC_C13_C14 0x443e +#define mmOUTPUT_CSC_C21_C22 0x1a3f +#define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f +#define mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f +#define mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f +#define mmDCP3_OUTPUT_CSC_C21_C22 0x403f +#define mmDCP4_OUTPUT_CSC_C21_C22 0x423f +#define mmDCP5_OUTPUT_CSC_C21_C22 0x443f +#define mmOUTPUT_CSC_C23_C24 0x1a40 +#define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 +#define mmDCP1_OUTPUT_CSC_C23_C24 0x1c40 +#define mmDCP2_OUTPUT_CSC_C23_C24 0x1e40 +#define mmDCP3_OUTPUT_CSC_C23_C24 0x4040 +#define mmDCP4_OUTPUT_CSC_C23_C24 0x4240 +#define mmDCP5_OUTPUT_CSC_C23_C24 0x4440 +#define mmOUTPUT_CSC_C31_C32 0x1a41 +#define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 +#define mmDCP1_OUTPUT_CSC_C31_C32 0x1c41 +#define mmDCP2_OUTPUT_CSC_C31_C32 0x1e41 +#define mmDCP3_OUTPUT_CSC_C31_C32 0x4041 +#define mmDCP4_OUTPUT_CSC_C31_C32 0x4241 +#define mmDCP5_OUTPUT_CSC_C31_C32 0x4441 +#define mmOUTPUT_CSC_C33_C34 0x1a42 +#define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 +#define mmDCP1_OUTPUT_CSC_C33_C34 0x1c42 +#define mmDCP2_OUTPUT_CSC_C33_C34 0x1e42 +#define mmDCP3_OUTPUT_CSC_C33_C34 0x4042 +#define mmDCP4_OUTPUT_CSC_C33_C34 0x4242 +#define mmDCP5_OUTPUT_CSC_C33_C34 0x4442 +#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43 +#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43 +#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043 +#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243 +#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443 +#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44 +#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44 +#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044 +#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244 +#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444 +#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45 +#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45 +#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045 +#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245 +#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445 +#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46 +#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46 +#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046 +#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246 +#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446 +#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47 +#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47 +#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047 +#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247 +#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447 +#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48 +#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48 +#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048 +#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248 +#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448 +#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49 +#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49 +#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049 +#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249 +#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449 +#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a +#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a +#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a +#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a +#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a +#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b +#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b +#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b +#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b +#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b +#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c +#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c +#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c +#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c +#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c +#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d +#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d +#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d +#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d +#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d +#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e +#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e +#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e +#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e +#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e +#define mmDENORM_CONTROL 0x1a50 +#define mmDCP0_DENORM_CONTROL 0x1a50 +#define mmDCP1_DENORM_CONTROL 0x1c50 +#define mmDCP2_DENORM_CONTROL 0x1e50 +#define mmDCP3_DENORM_CONTROL 0x4050 +#define mmDCP4_DENORM_CONTROL 0x4250 +#define mmDCP5_DENORM_CONTROL 0x4450 +#define mmOUT_ROUND_CONTROL 0x1a51 +#define mmDCP0_OUT_ROUND_CONTROL 0x1a51 +#define mmDCP1_OUT_ROUND_CONTROL 0x1c51 +#define mmDCP2_OUT_ROUND_CONTROL 0x1e51 +#define mmDCP3_OUT_ROUND_CONTROL 0x4051 +#define mmDCP4_OUT_ROUND_CONTROL 0x4251 +#define mmDCP5_OUT_ROUND_CONTROL 0x4451 +#define mmOUT_CLAMP_CONTROL_R_CR 0x1a52 +#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 +#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52 +#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52 +#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052 +#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252 +#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452 +#define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c +#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c +#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c +#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c +#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c +#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c +#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c +#define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d +#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d +#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d +#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d +#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d +#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d +#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d +#define mmKEY_CONTROL 0x1a53 +#define mmDCP0_KEY_CONTROL 0x1a53 +#define mmDCP1_KEY_CONTROL 0x1c53 +#define mmDCP2_KEY_CONTROL 0x1e53 +#define mmDCP3_KEY_CONTROL 0x4053 +#define mmDCP4_KEY_CONTROL 0x4253 +#define mmDCP5_KEY_CONTROL 0x4453 +#define mmKEY_RANGE_ALPHA 0x1a54 +#define mmDCP0_KEY_RANGE_ALPHA 0x1a54 +#define mmDCP1_KEY_RANGE_ALPHA 0x1c54 +#define mmDCP2_KEY_RANGE_ALPHA 0x1e54 +#define mmDCP3_KEY_RANGE_ALPHA 0x4054 +#define mmDCP4_KEY_RANGE_ALPHA 0x4254 +#define mmDCP5_KEY_RANGE_ALPHA 0x4454 +#define mmKEY_RANGE_RED 0x1a55 +#define mmDCP0_KEY_RANGE_RED 0x1a55 +#define mmDCP1_KEY_RANGE_RED 0x1c55 +#define mmDCP2_KEY_RANGE_RED 0x1e55 +#define mmDCP3_KEY_RANGE_RED 0x4055 +#define mmDCP4_KEY_RANGE_RED 0x4255 +#define mmDCP5_KEY_RANGE_RED 0x4455 +#define mmKEY_RANGE_GREEN 0x1a56 +#define mmDCP0_KEY_RANGE_GREEN 0x1a56 +#define mmDCP1_KEY_RANGE_GREEN 0x1c56 +#define mmDCP2_KEY_RANGE_GREEN 0x1e56 +#define mmDCP3_KEY_RANGE_GREEN 0x4056 +#define mmDCP4_KEY_RANGE_GREEN 0x4256 +#define mmDCP5_KEY_RANGE_GREEN 0x4456 +#define mmKEY_RANGE_BLUE 0x1a57 +#define mmDCP0_KEY_RANGE_BLUE 0x1a57 +#define mmDCP1_KEY_RANGE_BLUE 0x1c57 +#define mmDCP2_KEY_RANGE_BLUE 0x1e57 +#define mmDCP3_KEY_RANGE_BLUE 0x4057 +#define mmDCP4_KEY_RANGE_BLUE 0x4257 +#define mmDCP5_KEY_RANGE_BLUE 0x4457 +#define mmDEGAMMA_CONTROL 0x1a58 +#define mmDCP0_DEGAMMA_CONTROL 0x1a58 +#define mmDCP1_DEGAMMA_CONTROL 0x1c58 +#define mmDCP2_DEGAMMA_CONTROL 0x1e58 +#define mmDCP3_DEGAMMA_CONTROL 0x4058 +#define mmDCP4_DEGAMMA_CONTROL 0x4258 +#define mmDCP5_DEGAMMA_CONTROL 0x4458 +#define mmGAMUT_REMAP_CONTROL 0x1a59 +#define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 +#define mmDCP1_GAMUT_REMAP_CONTROL 0x1c59 +#define mmDCP2_GAMUT_REMAP_CONTROL 0x1e59 +#define mmDCP3_GAMUT_REMAP_CONTROL 0x4059 +#define mmDCP4_GAMUT_REMAP_CONTROL 0x4259 +#define mmDCP5_GAMUT_REMAP_CONTROL 0x4459 +#define mmGAMUT_REMAP_C11_C12 0x1a5a +#define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a +#define mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a +#define mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a +#define mmDCP3_GAMUT_REMAP_C11_C12 0x405a +#define mmDCP4_GAMUT_REMAP_C11_C12 0x425a +#define mmDCP5_GAMUT_REMAP_C11_C12 0x445a +#define mmGAMUT_REMAP_C13_C14 0x1a5b +#define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b +#define mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b +#define mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b +#define mmDCP3_GAMUT_REMAP_C13_C14 0x405b +#define mmDCP4_GAMUT_REMAP_C13_C14 0x425b +#define mmDCP5_GAMUT_REMAP_C13_C14 0x445b +#define mmGAMUT_REMAP_C21_C22 0x1a5c +#define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c +#define mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c +#define mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c +#define mmDCP3_GAMUT_REMAP_C21_C22 0x405c +#define mmDCP4_GAMUT_REMAP_C21_C22 0x425c +#define mmDCP5_GAMUT_REMAP_C21_C22 0x445c +#define mmGAMUT_REMAP_C23_C24 0x1a5d +#define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d +#define mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d +#define mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d +#define mmDCP3_GAMUT_REMAP_C23_C24 0x405d +#define mmDCP4_GAMUT_REMAP_C23_C24 0x425d +#define mmDCP5_GAMUT_REMAP_C23_C24 0x445d +#define mmGAMUT_REMAP_C31_C32 0x1a5e +#define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e +#define mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e +#define mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e +#define mmDCP3_GAMUT_REMAP_C31_C32 0x405e +#define mmDCP4_GAMUT_REMAP_C31_C32 0x425e +#define mmDCP5_GAMUT_REMAP_C31_C32 0x445e +#define mmGAMUT_REMAP_C33_C34 0x1a5f +#define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f +#define mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f +#define mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f +#define mmDCP3_GAMUT_REMAP_C33_C34 0x405f +#define mmDCP4_GAMUT_REMAP_C33_C34 0x425f +#define mmDCP5_GAMUT_REMAP_C33_C34 0x445f +#define mmDCP_SPATIAL_DITHER_CNTL 0x1a60 +#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 +#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60 +#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60 +#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060 +#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260 +#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460 +#define mmDCP_RANDOM_SEEDS 0x1a61 +#define mmDCP0_DCP_RANDOM_SEEDS 0x1a61 +#define mmDCP1_DCP_RANDOM_SEEDS 0x1c61 +#define mmDCP2_DCP_RANDOM_SEEDS 0x1e61 +#define mmDCP3_DCP_RANDOM_SEEDS 0x4061 +#define mmDCP4_DCP_RANDOM_SEEDS 0x4261 +#define mmDCP5_DCP_RANDOM_SEEDS 0x4461 +#define mmDCP_FP_CONVERTED_FIELD 0x1a65 +#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 +#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65 +#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65 +#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065 +#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265 +#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465 +#define mmCUR_CONTROL 0x1a66 +#define mmDCP0_CUR_CONTROL 0x1a66 +#define mmDCP1_CUR_CONTROL 0x1c66 +#define mmDCP2_CUR_CONTROL 0x1e66 +#define mmDCP3_CUR_CONTROL 0x4066 +#define mmDCP4_CUR_CONTROL 0x4266 +#define mmDCP5_CUR_CONTROL 0x4466 +#define mmCUR_SURFACE_ADDRESS 0x1a67 +#define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 +#define mmDCP1_CUR_SURFACE_ADDRESS 0x1c67 +#define mmDCP2_CUR_SURFACE_ADDRESS 0x1e67 +#define mmDCP3_CUR_SURFACE_ADDRESS 0x4067 +#define mmDCP4_CUR_SURFACE_ADDRESS 0x4267 +#define mmDCP5_CUR_SURFACE_ADDRESS 0x4467 +#define mmCUR_SIZE 0x1a68 +#define mmDCP0_CUR_SIZE 0x1a68 +#define mmDCP1_CUR_SIZE 0x1c68 +#define mmDCP2_CUR_SIZE 0x1e68 +#define mmDCP3_CUR_SIZE 0x4068 +#define mmDCP4_CUR_SIZE 0x4268 +#define mmDCP5_CUR_SIZE 0x4468 +#define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69 +#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69 +#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069 +#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269 +#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469 +#define mmCUR_POSITION 0x1a6a +#define mmDCP0_CUR_POSITION 0x1a6a +#define mmDCP1_CUR_POSITION 0x1c6a +#define mmDCP2_CUR_POSITION 0x1e6a +#define mmDCP3_CUR_POSITION 0x406a +#define mmDCP4_CUR_POSITION 0x426a +#define mmDCP5_CUR_POSITION 0x446a +#define mmCUR_HOT_SPOT 0x1a6b +#define mmDCP0_CUR_HOT_SPOT 0x1a6b +#define mmDCP1_CUR_HOT_SPOT 0x1c6b +#define mmDCP2_CUR_HOT_SPOT 0x1e6b +#define mmDCP3_CUR_HOT_SPOT 0x406b +#define mmDCP4_CUR_HOT_SPOT 0x426b +#define mmDCP5_CUR_HOT_SPOT 0x446b +#define mmCUR_COLOR1 0x1a6c +#define mmDCP0_CUR_COLOR1 0x1a6c +#define mmDCP1_CUR_COLOR1 0x1c6c +#define mmDCP2_CUR_COLOR1 0x1e6c +#define mmDCP3_CUR_COLOR1 0x406c +#define mmDCP4_CUR_COLOR1 0x426c +#define mmDCP5_CUR_COLOR1 0x446c +#define mmCUR_COLOR2 0x1a6d +#define mmDCP0_CUR_COLOR2 0x1a6d +#define mmDCP1_CUR_COLOR2 0x1c6d +#define mmDCP2_CUR_COLOR2 0x1e6d +#define mmDCP3_CUR_COLOR2 0x406d +#define mmDCP4_CUR_COLOR2 0x426d +#define mmDCP5_CUR_COLOR2 0x446d +#define mmCUR_UPDATE 0x1a6e +#define mmDCP0_CUR_UPDATE 0x1a6e +#define mmDCP1_CUR_UPDATE 0x1c6e +#define mmDCP2_CUR_UPDATE 0x1e6e +#define mmDCP3_CUR_UPDATE 0x406e +#define mmDCP4_CUR_UPDATE 0x426e +#define mmDCP5_CUR_UPDATE 0x446e +#define mmCUR_REQUEST_FILTER_CNTL 0x1a99 +#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 +#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99 +#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99 +#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099 +#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299 +#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499 +#define mmCUR_STEREO_CONTROL 0x1a9a +#define mmDCP0_CUR_STEREO_CONTROL 0x1a9a +#define mmDCP1_CUR_STEREO_CONTROL 0x1c9a +#define mmDCP2_CUR_STEREO_CONTROL 0x1e9a +#define mmDCP3_CUR_STEREO_CONTROL 0x409a +#define mmDCP4_CUR_STEREO_CONTROL 0x429a +#define mmDCP5_CUR_STEREO_CONTROL 0x449a +#define mmDC_LUT_RW_MODE 0x1a78 +#define mmDCP0_DC_LUT_RW_MODE 0x1a78 +#define mmDCP1_DC_LUT_RW_MODE 0x1c78 +#define mmDCP2_DC_LUT_RW_MODE 0x1e78 +#define mmDCP3_DC_LUT_RW_MODE 0x4078 +#define mmDCP4_DC_LUT_RW_MODE 0x4278 +#define mmDCP5_DC_LUT_RW_MODE 0x4478 +#define mmDC_LUT_RW_INDEX 0x1a79 +#define mmDCP0_DC_LUT_RW_INDEX 0x1a79 +#define mmDCP1_DC_LUT_RW_INDEX 0x1c79 +#define mmDCP2_DC_LUT_RW_INDEX 0x1e79 +#define mmDCP3_DC_LUT_RW_INDEX 0x4079 +#define mmDCP4_DC_LUT_RW_INDEX 0x4279 +#define mmDCP5_DC_LUT_RW_INDEX 0x4479 +#define mmDC_LUT_SEQ_COLOR 0x1a7a +#define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a +#define mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a +#define mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a +#define mmDCP3_DC_LUT_SEQ_COLOR 0x407a +#define mmDCP4_DC_LUT_SEQ_COLOR 0x427a +#define mmDCP5_DC_LUT_SEQ_COLOR 0x447a +#define mmDC_LUT_PWL_DATA 0x1a7b +#define mmDCP0_DC_LUT_PWL_DATA 0x1a7b +#define mmDCP1_DC_LUT_PWL_DATA 0x1c7b +#define mmDCP2_DC_LUT_PWL_DATA 0x1e7b +#define mmDCP3_DC_LUT_PWL_DATA 0x407b +#define mmDCP4_DC_LUT_PWL_DATA 0x427b +#define mmDCP5_DC_LUT_PWL_DATA 0x447b +#define mmDC_LUT_30_COLOR 0x1a7c +#define mmDCP0_DC_LUT_30_COLOR 0x1a7c +#define mmDCP1_DC_LUT_30_COLOR 0x1c7c +#define mmDCP2_DC_LUT_30_COLOR 0x1e7c +#define mmDCP3_DC_LUT_30_COLOR 0x407c +#define mmDCP4_DC_LUT_30_COLOR 0x427c +#define mmDCP5_DC_LUT_30_COLOR 0x447c +#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d +#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d +#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d +#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d +#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d +#define mmDC_LUT_WRITE_EN_MASK 0x1a7e +#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e +#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e +#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e +#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e +#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e +#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e +#define mmDC_LUT_AUTOFILL 0x1a7f +#define mmDCP0_DC_LUT_AUTOFILL 0x1a7f +#define mmDCP1_DC_LUT_AUTOFILL 0x1c7f +#define mmDCP2_DC_LUT_AUTOFILL 0x1e7f +#define mmDCP3_DC_LUT_AUTOFILL 0x407f +#define mmDCP4_DC_LUT_AUTOFILL 0x427f +#define mmDCP5_DC_LUT_AUTOFILL 0x447f +#define mmDC_LUT_CONTROL 0x1a80 +#define mmDCP0_DC_LUT_CONTROL 0x1a80 +#define mmDCP1_DC_LUT_CONTROL 0x1c80 +#define mmDCP2_DC_LUT_CONTROL 0x1e80 +#define mmDCP3_DC_LUT_CONTROL 0x4080 +#define mmDCP4_DC_LUT_CONTROL 0x4280 +#define mmDCP5_DC_LUT_CONTROL 0x4480 +#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81 +#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81 +#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081 +#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281 +#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481 +#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82 +#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82 +#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082 +#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282 +#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482 +#define mmDC_LUT_BLACK_OFFSET_RED 0x1a83 +#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 +#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83 +#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83 +#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083 +#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283 +#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483 +#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84 +#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84 +#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084 +#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284 +#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484 +#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85 +#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85 +#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085 +#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285 +#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485 +#define mmDC_LUT_WHITE_OFFSET_RED 0x1a86 +#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 +#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86 +#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86 +#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086 +#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286 +#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486 +#define mmDCP_CRC_CONTROL 0x1a87 +#define mmDCP0_DCP_CRC_CONTROL 0x1a87 +#define mmDCP1_DCP_CRC_CONTROL 0x1c87 +#define mmDCP2_DCP_CRC_CONTROL 0x1e87 +#define mmDCP3_DCP_CRC_CONTROL 0x4087 +#define mmDCP4_DCP_CRC_CONTROL 0x4287 +#define mmDCP5_DCP_CRC_CONTROL 0x4487 +#define mmDCP_CRC_MASK 0x1a88 +#define mmDCP0_DCP_CRC_MASK 0x1a88 +#define mmDCP1_DCP_CRC_MASK 0x1c88 +#define mmDCP2_DCP_CRC_MASK 0x1e88 +#define mmDCP3_DCP_CRC_MASK 0x4088 +#define mmDCP4_DCP_CRC_MASK 0x4288 +#define mmDCP5_DCP_CRC_MASK 0x4488 +#define mmDCP_CRC_CURRENT 0x1a89 +#define mmDCP0_DCP_CRC_CURRENT 0x1a89 +#define mmDCP1_DCP_CRC_CURRENT 0x1c89 +#define mmDCP2_DCP_CRC_CURRENT 0x1e89 +#define mmDCP3_DCP_CRC_CURRENT 0x4089 +#define mmDCP4_DCP_CRC_CURRENT 0x4289 +#define mmDCP5_DCP_CRC_CURRENT 0x4489 +#define mmDCP_CRC_LAST 0x1a8b +#define mmDCP0_DCP_CRC_LAST 0x1a8b +#define mmDCP1_DCP_CRC_LAST 0x1c8b +#define mmDCP2_DCP_CRC_LAST 0x1e8b +#define mmDCP3_DCP_CRC_LAST 0x408b +#define mmDCP4_DCP_CRC_LAST 0x428b +#define mmDCP5_DCP_CRC_LAST 0x448b +#define mmDCP_DEBUG 0x1a8d +#define mmDCP0_DCP_DEBUG 0x1a8d +#define mmDCP1_DCP_DEBUG 0x1c8d +#define mmDCP2_DCP_DEBUG 0x1e8d +#define mmDCP3_DCP_DEBUG 0x408d +#define mmDCP4_DCP_DEBUG 0x428d +#define mmDCP5_DCP_DEBUG 0x448d +#define mmGRPH_FLIP_RATE_CNTL 0x1a8e +#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e +#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e +#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e +#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e +#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e +#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e +#define mmDCP_GSL_CONTROL 0x1a90 +#define mmDCP0_DCP_GSL_CONTROL 0x1a90 +#define mmDCP1_DCP_GSL_CONTROL 0x1c90 +#define mmDCP2_DCP_GSL_CONTROL 0x1e90 +#define mmDCP3_DCP_GSL_CONTROL 0x4090 +#define mmDCP4_DCP_GSL_CONTROL 0x4290 +#define mmDCP5_DCP_GSL_CONTROL 0x4490 +#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91 +#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91 +#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 +#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291 +#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491 +#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92 +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92 +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1c92 +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x1e92 +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4292 +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4492 +#define mmOVL_STEREOSYNC_FLIP 0x1a93 +#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93 +#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1c93 +#define mmDCP2_OVL_STEREOSYNC_FLIP 0x1e93 +#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4093 +#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4293 +#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4493 +#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 +#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 +#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c94 +#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e94 +#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 +#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4294 +#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4494 +#define mmDCP_TEST_DEBUG_INDEX 0x1a95 +#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 +#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95 +#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95 +#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095 +#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295 +#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495 +#define mmDCP_TEST_DEBUG_DATA 0x1a96 +#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 +#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96 +#define mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96 +#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4096 +#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4296 +#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4496 +#define mmGRPH_STEREOSYNC_FLIP 0x1a97 +#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 +#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97 +#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97 +#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097 +#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297 +#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497 +#define mmDCP_DEBUG2 0x1a98 +#define mmDCP0_DCP_DEBUG2 0x1a98 +#define mmDCP1_DCP_DEBUG2 0x1c98 +#define mmDCP2_DCP_DEBUG2 0x1e98 +#define mmDCP3_DCP_DEBUG2 0x4098 +#define mmDCP4_DCP_DEBUG2 0x4298 +#define mmDCP5_DCP_DEBUG2 0x4498 +#define mmHW_ROTATION 0x1a9e +#define mmDCP0_HW_ROTATION 0x1a9e +#define mmDCP1_HW_ROTATION 0x1c9e +#define mmDCP2_HW_ROTATION 0x1e9e +#define mmDCP3_HW_ROTATION 0x409e +#define mmDCP4_HW_ROTATION 0x429e +#define mmDCP5_HW_ROTATION 0x449e +#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f +#define mmREGAMMA_CONTROL 0x1aa0 +#define mmDCP0_REGAMMA_CONTROL 0x1aa0 +#define mmDCP1_REGAMMA_CONTROL 0x1ca0 +#define mmDCP2_REGAMMA_CONTROL 0x1ea0 +#define mmDCP3_REGAMMA_CONTROL 0x40a0 +#define mmDCP4_REGAMMA_CONTROL 0x42a0 +#define mmDCP5_REGAMMA_CONTROL 0x44a0 +#define mmREGAMMA_LUT_INDEX 0x1aa1 +#define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 +#define mmDCP1_REGAMMA_LUT_INDEX 0x1ca1 +#define mmDCP2_REGAMMA_LUT_INDEX 0x1ea1 +#define mmDCP3_REGAMMA_LUT_INDEX 0x40a1 +#define mmDCP4_REGAMMA_LUT_INDEX 0x42a1 +#define mmDCP5_REGAMMA_LUT_INDEX 0x44a1 +#define mmREGAMMA_LUT_DATA 0x1aa2 +#define mmDCP0_REGAMMA_LUT_DATA 0x1aa2 +#define mmDCP1_REGAMMA_LUT_DATA 0x1ca2 +#define mmDCP2_REGAMMA_LUT_DATA 0x1ea2 +#define mmDCP3_REGAMMA_LUT_DATA 0x40a2 +#define mmDCP4_REGAMMA_LUT_DATA 0x42a2 +#define mmDCP5_REGAMMA_LUT_DATA 0x44a2 +#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3 +#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3 +#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 +#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3 +#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3 +#define mmREGAMMA_CNTLA_START_CNTL 0x1aa4 +#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 +#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4 +#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4 +#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4 +#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4 +#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4 +#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5 +#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5 +#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 +#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5 +#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5 +#define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6 +#define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7 +#define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8 +#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8 +#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8 +#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8 +#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8 +#define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9 +#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9 +#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9 +#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9 +#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9 +#define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa +#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa +#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa +#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa +#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa +#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa +#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa +#define mmREGAMMA_CNTLA_REGION_6_7 0x1aab +#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab +#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab +#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab +#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab +#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab +#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab +#define mmREGAMMA_CNTLA_REGION_8_9 0x1aac +#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac +#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac +#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac +#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac +#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac +#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac +#define mmREGAMMA_CNTLA_REGION_10_11 0x1aad +#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad +#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad +#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead +#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad +#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad +#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad +#define mmREGAMMA_CNTLA_REGION_12_13 0x1aae +#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae +#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae +#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae +#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae +#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae +#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae +#define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf +#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf +#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf +#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf +#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af +#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af +#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af +#define mmREGAMMA_CNTLB_START_CNTL 0x1ab0 +#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 +#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0 +#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0 +#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0 +#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0 +#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0 +#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1 +#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1 +#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 +#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1 +#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1 +#define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2 +#define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3 +#define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4 +#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4 +#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4 +#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4 +#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4 +#define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5 +#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5 +#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5 +#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5 +#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5 +#define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6 +#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6 +#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6 +#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6 +#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6 +#define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7 +#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7 +#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7 +#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7 +#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7 +#define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8 +#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8 +#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8 +#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8 +#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8 +#define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9 +#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9 +#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9 +#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9 +#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9 +#define mmREGAMMA_CNTLB_REGION_12_13 0x1aba +#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba +#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba +#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba +#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba +#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba +#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba +#define mmREGAMMA_CNTLB_REGION_14_15 0x1abb +#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb +#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb +#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb +#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb +#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb +#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb +#define mmALPHA_CONTROL 0x1abc +#define mmDCP0_ALPHA_CONTROL 0x1abc +#define mmDCP1_ALPHA_CONTROL 0x1cbc +#define mmDCP2_ALPHA_CONTROL 0x1ebc +#define mmDCP3_ALPHA_CONTROL 0x40bc +#define mmDCP4_ALPHA_CONTROL 0x42bc +#define mmDCP5_ALPHA_CONTROL 0x44bc +#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd +#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be +#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf +#define mmDIG_FE_CNTL 0x4a00 +#define mmDIG0_DIG_FE_CNTL 0x4a00 +#define mmDIG1_DIG_FE_CNTL 0x4b00 +#define mmDIG2_DIG_FE_CNTL 0x4c00 +#define mmDIG3_DIG_FE_CNTL 0x4d00 +#define mmDIG4_DIG_FE_CNTL 0x4e00 +#define mmDIG5_DIG_FE_CNTL 0x4f00 +#define mmDIG6_DIG_FE_CNTL 0x5400 +#define mmDIG_OUTPUT_CRC_CNTL 0x4a01 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01 +#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01 +#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01 +#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01 +#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01 +#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401 +#define mmDIG_OUTPUT_CRC_RESULT 0x4a02 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02 +#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402 +#define mmDIG_CLOCK_PATTERN 0x4a03 +#define mmDIG0_DIG_CLOCK_PATTERN 0x4a03 +#define mmDIG1_DIG_CLOCK_PATTERN 0x4b03 +#define mmDIG2_DIG_CLOCK_PATTERN 0x4c03 +#define mmDIG3_DIG_CLOCK_PATTERN 0x4d03 +#define mmDIG4_DIG_CLOCK_PATTERN 0x4e03 +#define mmDIG5_DIG_CLOCK_PATTERN 0x4f03 +#define mmDIG6_DIG_CLOCK_PATTERN 0x5403 +#define mmDIG_TEST_PATTERN 0x4a04 +#define mmDIG0_DIG_TEST_PATTERN 0x4a04 +#define mmDIG1_DIG_TEST_PATTERN 0x4b04 +#define mmDIG2_DIG_TEST_PATTERN 0x4c04 +#define mmDIG3_DIG_TEST_PATTERN 0x4d04 +#define mmDIG4_DIG_TEST_PATTERN 0x4e04 +#define mmDIG5_DIG_TEST_PATTERN 0x4f04 +#define mmDIG6_DIG_TEST_PATTERN 0x5404 +#define mmDIG_RANDOM_PATTERN_SEED 0x4a05 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05 +#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405 +#define mmDIG_FIFO_STATUS 0x4a06 +#define mmDIG0_DIG_FIFO_STATUS 0x4a06 +#define mmDIG1_DIG_FIFO_STATUS 0x4b06 +#define mmDIG2_DIG_FIFO_STATUS 0x4c06 +#define mmDIG3_DIG_FIFO_STATUS 0x4d06 +#define mmDIG4_DIG_FIFO_STATUS 0x4e06 +#define mmDIG5_DIG_FIFO_STATUS 0x4f06 +#define mmDIG6_DIG_FIFO_STATUS 0x5406 +#define mmDIG_DISPCLK_SWITCH_CNTL 0x4a07 +#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07 +#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07 +#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07 +#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07 +#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07 +#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07 +#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407 +#define mmDIG_DISPCLK_SWITCH_STATUS 0x4a08 +#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08 +#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08 +#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08 +#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08 +#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08 +#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08 +#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408 +#define mmHDMI_CONTROL 0x4a09 +#define mmDIG0_HDMI_CONTROL 0x4a09 +#define mmDIG1_HDMI_CONTROL 0x4b09 +#define mmDIG2_HDMI_CONTROL 0x4c09 +#define mmDIG3_HDMI_CONTROL 0x4d09 +#define mmDIG4_HDMI_CONTROL 0x4e09 +#define mmDIG5_HDMI_CONTROL 0x4f09 +#define mmDIG6_HDMI_CONTROL 0x5409 +#define mmHDMI_STATUS 0x4a0a +#define mmDIG0_HDMI_STATUS 0x4a0a +#define mmDIG1_HDMI_STATUS 0x4b0a +#define mmDIG2_HDMI_STATUS 0x4c0a +#define mmDIG3_HDMI_STATUS 0x4d0a +#define mmDIG4_HDMI_STATUS 0x4e0a +#define mmDIG5_HDMI_STATUS 0x4f0a +#define mmDIG6_HDMI_STATUS 0x540a +#define mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b +#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b +#define mmHDMI_ACR_PACKET_CONTROL 0x4a0c +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c +#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c +#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c +#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c +#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c +#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c +#define mmHDMI_VBI_PACKET_CONTROL 0x4a0d +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d +#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d +#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d +#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d +#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d +#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d +#define mmHDMI_INFOFRAME_CONTROL0 0x4a0e +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e +#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e +#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e +#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e +#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e +#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e +#define mmHDMI_INFOFRAME_CONTROL1 0x4a0f +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f +#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f +#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f +#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f +#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f +#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f +#define mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410 +#define mmAFMT_INTERRUPT_STATUS 0x4a11 +#define mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11 +#define mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11 +#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11 +#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11 +#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11 +#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11 +#define mmDIG6_AFMT_INTERRUPT_STATUS 0x5411 +#define mmHDMI_GC 0x4a13 +#define mmDIG0_HDMI_GC 0x4a13 +#define mmDIG1_HDMI_GC 0x4b13 +#define mmDIG2_HDMI_GC 0x4c13 +#define mmDIG3_HDMI_GC 0x4d13 +#define mmDIG4_HDMI_GC 0x4e13 +#define mmDIG5_HDMI_GC 0x4f13 +#define mmDIG6_HDMI_GC 0x5413 +#define mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414 +#define mmAFMT_ISRC1_0 0x4a15 +#define mmDIG0_AFMT_ISRC1_0 0x4a15 +#define mmDIG1_AFMT_ISRC1_0 0x4b15 +#define mmDIG2_AFMT_ISRC1_0 0x4c15 +#define mmDIG3_AFMT_ISRC1_0 0x4d15 +#define mmDIG4_AFMT_ISRC1_0 0x4e15 +#define mmDIG5_AFMT_ISRC1_0 0x4f15 +#define mmDIG6_AFMT_ISRC1_0 0x5415 +#define mmAFMT_ISRC1_1 0x4a16 +#define mmDIG0_AFMT_ISRC1_1 0x4a16 +#define mmDIG1_AFMT_ISRC1_1 0x4b16 +#define mmDIG2_AFMT_ISRC1_1 0x4c16 +#define mmDIG3_AFMT_ISRC1_1 0x4d16 +#define mmDIG4_AFMT_ISRC1_1 0x4e16 +#define mmDIG5_AFMT_ISRC1_1 0x4f16 +#define mmDIG6_AFMT_ISRC1_1 0x5416 +#define mmAFMT_ISRC1_2 0x4a17 +#define mmDIG0_AFMT_ISRC1_2 0x4a17 +#define mmDIG1_AFMT_ISRC1_2 0x4b17 +#define mmDIG2_AFMT_ISRC1_2 0x4c17 +#define mmDIG3_AFMT_ISRC1_2 0x4d17 +#define mmDIG4_AFMT_ISRC1_2 0x4e17 +#define mmDIG5_AFMT_ISRC1_2 0x4f17 +#define mmDIG6_AFMT_ISRC1_2 0x5417 +#define mmAFMT_ISRC1_3 0x4a18 +#define mmDIG0_AFMT_ISRC1_3 0x4a18 +#define mmDIG1_AFMT_ISRC1_3 0x4b18 +#define mmDIG2_AFMT_ISRC1_3 0x4c18 +#define mmDIG3_AFMT_ISRC1_3 0x4d18 +#define mmDIG4_AFMT_ISRC1_3 0x4e18 +#define mmDIG5_AFMT_ISRC1_3 0x4f18 +#define mmDIG6_AFMT_ISRC1_3 0x5418 +#define mmAFMT_ISRC1_4 0x4a19 +#define mmDIG0_AFMT_ISRC1_4 0x4a19 +#define mmDIG1_AFMT_ISRC1_4 0x4b19 +#define mmDIG2_AFMT_ISRC1_4 0x4c19 +#define mmDIG3_AFMT_ISRC1_4 0x4d19 +#define mmDIG4_AFMT_ISRC1_4 0x4e19 +#define mmDIG5_AFMT_ISRC1_4 0x4f19 +#define mmDIG6_AFMT_ISRC1_4 0x5419 +#define mmAFMT_ISRC2_0 0x4a1a +#define mmDIG0_AFMT_ISRC2_0 0x4a1a +#define mmDIG1_AFMT_ISRC2_0 0x4b1a +#define mmDIG2_AFMT_ISRC2_0 0x4c1a +#define mmDIG3_AFMT_ISRC2_0 0x4d1a +#define mmDIG4_AFMT_ISRC2_0 0x4e1a +#define mmDIG5_AFMT_ISRC2_0 0x4f1a +#define mmDIG6_AFMT_ISRC2_0 0x541a +#define mmAFMT_ISRC2_1 0x4a1b +#define mmDIG0_AFMT_ISRC2_1 0x4a1b +#define mmDIG1_AFMT_ISRC2_1 0x4b1b +#define mmDIG2_AFMT_ISRC2_1 0x4c1b +#define mmDIG3_AFMT_ISRC2_1 0x4d1b +#define mmDIG4_AFMT_ISRC2_1 0x4e1b +#define mmDIG5_AFMT_ISRC2_1 0x4f1b +#define mmDIG6_AFMT_ISRC2_1 0x541b +#define mmAFMT_ISRC2_2 0x4a1c +#define mmDIG0_AFMT_ISRC2_2 0x4a1c +#define mmDIG1_AFMT_ISRC2_2 0x4b1c +#define mmDIG2_AFMT_ISRC2_2 0x4c1c +#define mmDIG3_AFMT_ISRC2_2 0x4d1c +#define mmDIG4_AFMT_ISRC2_2 0x4e1c +#define mmDIG5_AFMT_ISRC2_2 0x4f1c +#define mmDIG6_AFMT_ISRC2_2 0x541c +#define mmAFMT_ISRC2_3 0x4a1d +#define mmDIG0_AFMT_ISRC2_3 0x4a1d +#define mmDIG1_AFMT_ISRC2_3 0x4b1d +#define mmDIG2_AFMT_ISRC2_3 0x4c1d +#define mmDIG3_AFMT_ISRC2_3 0x4d1d +#define mmDIG4_AFMT_ISRC2_3 0x4e1d +#define mmDIG5_AFMT_ISRC2_3 0x4f1d +#define mmDIG6_AFMT_ISRC2_3 0x541d +#define mmAFMT_AVI_INFO0 0x4a1e +#define mmDIG0_AFMT_AVI_INFO0 0x4a1e +#define mmDIG1_AFMT_AVI_INFO0 0x4b1e +#define mmDIG2_AFMT_AVI_INFO0 0x4c1e +#define mmDIG3_AFMT_AVI_INFO0 0x4d1e +#define mmDIG4_AFMT_AVI_INFO0 0x4e1e +#define mmDIG5_AFMT_AVI_INFO0 0x4f1e +#define mmDIG6_AFMT_AVI_INFO0 0x541e +#define mmAFMT_AVI_INFO1 0x4a1f +#define mmDIG0_AFMT_AVI_INFO1 0x4a1f +#define mmDIG1_AFMT_AVI_INFO1 0x4b1f +#define mmDIG2_AFMT_AVI_INFO1 0x4c1f +#define mmDIG3_AFMT_AVI_INFO1 0x4d1f +#define mmDIG4_AFMT_AVI_INFO1 0x4e1f +#define mmDIG5_AFMT_AVI_INFO1 0x4f1f +#define mmDIG6_AFMT_AVI_INFO1 0x541f +#define mmAFMT_AVI_INFO2 0x4a20 +#define mmDIG0_AFMT_AVI_INFO2 0x4a20 +#define mmDIG1_AFMT_AVI_INFO2 0x4b20 +#define mmDIG2_AFMT_AVI_INFO2 0x4c20 +#define mmDIG3_AFMT_AVI_INFO2 0x4d20 +#define mmDIG4_AFMT_AVI_INFO2 0x4e20 +#define mmDIG5_AFMT_AVI_INFO2 0x4f20 +#define mmDIG6_AFMT_AVI_INFO2 0x5420 +#define mmAFMT_AVI_INFO3 0x4a21 +#define mmDIG0_AFMT_AVI_INFO3 0x4a21 +#define mmDIG1_AFMT_AVI_INFO3 0x4b21 +#define mmDIG2_AFMT_AVI_INFO3 0x4c21 +#define mmDIG3_AFMT_AVI_INFO3 0x4d21 +#define mmDIG4_AFMT_AVI_INFO3 0x4e21 +#define mmDIG5_AFMT_AVI_INFO3 0x4f21 +#define mmDIG6_AFMT_AVI_INFO3 0x5421 +#define mmAFMT_MPEG_INFO0 0x4a22 +#define mmDIG0_AFMT_MPEG_INFO0 0x4a22 +#define mmDIG1_AFMT_MPEG_INFO0 0x4b22 +#define mmDIG2_AFMT_MPEG_INFO0 0x4c22 +#define mmDIG3_AFMT_MPEG_INFO0 0x4d22 +#define mmDIG4_AFMT_MPEG_INFO0 0x4e22 +#define mmDIG5_AFMT_MPEG_INFO0 0x4f22 +#define mmDIG6_AFMT_MPEG_INFO0 0x5422 +#define mmAFMT_MPEG_INFO1 0x4a23 +#define mmDIG0_AFMT_MPEG_INFO1 0x4a23 +#define mmDIG1_AFMT_MPEG_INFO1 0x4b23 +#define mmDIG2_AFMT_MPEG_INFO1 0x4c23 +#define mmDIG3_AFMT_MPEG_INFO1 0x4d23 +#define mmDIG4_AFMT_MPEG_INFO1 0x4e23 +#define mmDIG5_AFMT_MPEG_INFO1 0x4f23 +#define mmDIG6_AFMT_MPEG_INFO1 0x5423 +#define mmAFMT_GENERIC_HDR 0x4a24 +#define mmDIG0_AFMT_GENERIC_HDR 0x4a24 +#define mmDIG1_AFMT_GENERIC_HDR 0x4b24 +#define mmDIG2_AFMT_GENERIC_HDR 0x4c24 +#define mmDIG3_AFMT_GENERIC_HDR 0x4d24 +#define mmDIG4_AFMT_GENERIC_HDR 0x4e24 +#define mmDIG5_AFMT_GENERIC_HDR 0x4f24 +#define mmDIG6_AFMT_GENERIC_HDR 0x5424 +#define mmAFMT_GENERIC_0 0x4a25 +#define mmDIG0_AFMT_GENERIC_0 0x4a25 +#define mmDIG1_AFMT_GENERIC_0 0x4b25 +#define mmDIG2_AFMT_GENERIC_0 0x4c25 +#define mmDIG3_AFMT_GENERIC_0 0x4d25 +#define mmDIG4_AFMT_GENERIC_0 0x4e25 +#define mmDIG5_AFMT_GENERIC_0 0x4f25 +#define mmDIG6_AFMT_GENERIC_0 0x5425 +#define mmAFMT_GENERIC_1 0x4a26 +#define mmDIG0_AFMT_GENERIC_1 0x4a26 +#define mmDIG1_AFMT_GENERIC_1 0x4b26 +#define mmDIG2_AFMT_GENERIC_1 0x4c26 +#define mmDIG3_AFMT_GENERIC_1 0x4d26 +#define mmDIG4_AFMT_GENERIC_1 0x4e26 +#define mmDIG5_AFMT_GENERIC_1 0x4f26 +#define mmDIG6_AFMT_GENERIC_1 0x5426 +#define mmAFMT_GENERIC_2 0x4a27 +#define mmDIG0_AFMT_GENERIC_2 0x4a27 +#define mmDIG1_AFMT_GENERIC_2 0x4b27 +#define mmDIG2_AFMT_GENERIC_2 0x4c27 +#define mmDIG3_AFMT_GENERIC_2 0x4d27 +#define mmDIG4_AFMT_GENERIC_2 0x4e27 +#define mmDIG5_AFMT_GENERIC_2 0x4f27 +#define mmDIG6_AFMT_GENERIC_2 0x5427 +#define mmAFMT_GENERIC_3 0x4a28 +#define mmDIG0_AFMT_GENERIC_3 0x4a28 +#define mmDIG1_AFMT_GENERIC_3 0x4b28 +#define mmDIG2_AFMT_GENERIC_3 0x4c28 +#define mmDIG3_AFMT_GENERIC_3 0x4d28 +#define mmDIG4_AFMT_GENERIC_3 0x4e28 +#define mmDIG5_AFMT_GENERIC_3 0x4f28 +#define mmDIG6_AFMT_GENERIC_3 0x5428 +#define mmAFMT_GENERIC_4 0x4a29 +#define mmDIG0_AFMT_GENERIC_4 0x4a29 +#define mmDIG1_AFMT_GENERIC_4 0x4b29 +#define mmDIG2_AFMT_GENERIC_4 0x4c29 +#define mmDIG3_AFMT_GENERIC_4 0x4d29 +#define mmDIG4_AFMT_GENERIC_4 0x4e29 +#define mmDIG5_AFMT_GENERIC_4 0x4f29 +#define mmDIG6_AFMT_GENERIC_4 0x5429 +#define mmAFMT_GENERIC_5 0x4a2a +#define mmDIG0_AFMT_GENERIC_5 0x4a2a +#define mmDIG1_AFMT_GENERIC_5 0x4b2a +#define mmDIG2_AFMT_GENERIC_5 0x4c2a +#define mmDIG3_AFMT_GENERIC_5 0x4d2a +#define mmDIG4_AFMT_GENERIC_5 0x4e2a +#define mmDIG5_AFMT_GENERIC_5 0x4f2a +#define mmDIG6_AFMT_GENERIC_5 0x542a +#define mmAFMT_GENERIC_6 0x4a2b +#define mmDIG0_AFMT_GENERIC_6 0x4a2b +#define mmDIG1_AFMT_GENERIC_6 0x4b2b +#define mmDIG2_AFMT_GENERIC_6 0x4c2b +#define mmDIG3_AFMT_GENERIC_6 0x4d2b +#define mmDIG4_AFMT_GENERIC_6 0x4e2b +#define mmDIG5_AFMT_GENERIC_6 0x4f2b +#define mmDIG6_AFMT_GENERIC_6 0x542b +#define mmAFMT_GENERIC_7 0x4a2c +#define mmDIG0_AFMT_GENERIC_7 0x4a2c +#define mmDIG1_AFMT_GENERIC_7 0x4b2c +#define mmDIG2_AFMT_GENERIC_7 0x4c2c +#define mmDIG3_AFMT_GENERIC_7 0x4d2c +#define mmDIG4_AFMT_GENERIC_7 0x4e2c +#define mmDIG5_AFMT_GENERIC_7 0x4f2c +#define mmDIG6_AFMT_GENERIC_7 0x542c +#define mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d +#define mmHDMI_ACR_32_0 0x4a2e +#define mmDIG0_HDMI_ACR_32_0 0x4a2e +#define mmDIG1_HDMI_ACR_32_0 0x4b2e +#define mmDIG2_HDMI_ACR_32_0 0x4c2e +#define mmDIG3_HDMI_ACR_32_0 0x4d2e +#define mmDIG4_HDMI_ACR_32_0 0x4e2e +#define mmDIG5_HDMI_ACR_32_0 0x4f2e +#define mmDIG6_HDMI_ACR_32_0 0x542e +#define mmHDMI_ACR_32_1 0x4a2f +#define mmDIG0_HDMI_ACR_32_1 0x4a2f +#define mmDIG1_HDMI_ACR_32_1 0x4b2f +#define mmDIG2_HDMI_ACR_32_1 0x4c2f +#define mmDIG3_HDMI_ACR_32_1 0x4d2f +#define mmDIG4_HDMI_ACR_32_1 0x4e2f +#define mmDIG5_HDMI_ACR_32_1 0x4f2f +#define mmDIG6_HDMI_ACR_32_1 0x542f +#define mmHDMI_ACR_44_0 0x4a30 +#define mmDIG0_HDMI_ACR_44_0 0x4a30 +#define mmDIG1_HDMI_ACR_44_0 0x4b30 +#define mmDIG2_HDMI_ACR_44_0 0x4c30 +#define mmDIG3_HDMI_ACR_44_0 0x4d30 +#define mmDIG4_HDMI_ACR_44_0 0x4e30 +#define mmDIG5_HDMI_ACR_44_0 0x4f30 +#define mmDIG6_HDMI_ACR_44_0 0x5430 +#define mmHDMI_ACR_44_1 0x4a31 +#define mmDIG0_HDMI_ACR_44_1 0x4a31 +#define mmDIG1_HDMI_ACR_44_1 0x4b31 +#define mmDIG2_HDMI_ACR_44_1 0x4c31 +#define mmDIG3_HDMI_ACR_44_1 0x4d31 +#define mmDIG4_HDMI_ACR_44_1 0x4e31 +#define mmDIG5_HDMI_ACR_44_1 0x4f31 +#define mmDIG6_HDMI_ACR_44_1 0x5431 +#define mmHDMI_ACR_48_0 0x4a32 +#define mmDIG0_HDMI_ACR_48_0 0x4a32 +#define mmDIG1_HDMI_ACR_48_0 0x4b32 +#define mmDIG2_HDMI_ACR_48_0 0x4c32 +#define mmDIG3_HDMI_ACR_48_0 0x4d32 +#define mmDIG4_HDMI_ACR_48_0 0x4e32 +#define mmDIG5_HDMI_ACR_48_0 0x4f32 +#define mmDIG6_HDMI_ACR_48_0 0x5432 +#define mmHDMI_ACR_48_1 0x4a33 +#define mmDIG0_HDMI_ACR_48_1 0x4a33 +#define mmDIG1_HDMI_ACR_48_1 0x4b33 +#define mmDIG2_HDMI_ACR_48_1 0x4c33 +#define mmDIG3_HDMI_ACR_48_1 0x4d33 +#define mmDIG4_HDMI_ACR_48_1 0x4e33 +#define mmDIG5_HDMI_ACR_48_1 0x4f33 +#define mmDIG6_HDMI_ACR_48_1 0x5433 +#define mmHDMI_ACR_STATUS_0 0x4a34 +#define mmDIG0_HDMI_ACR_STATUS_0 0x4a34 +#define mmDIG1_HDMI_ACR_STATUS_0 0x4b34 +#define mmDIG2_HDMI_ACR_STATUS_0 0x4c34 +#define mmDIG3_HDMI_ACR_STATUS_0 0x4d34 +#define mmDIG4_HDMI_ACR_STATUS_0 0x4e34 +#define mmDIG5_HDMI_ACR_STATUS_0 0x4f34 +#define mmDIG6_HDMI_ACR_STATUS_0 0x5434 +#define mmHDMI_ACR_STATUS_1 0x4a35 +#define mmDIG0_HDMI_ACR_STATUS_1 0x4a35 +#define mmDIG1_HDMI_ACR_STATUS_1 0x4b35 +#define mmDIG2_HDMI_ACR_STATUS_1 0x4c35 +#define mmDIG3_HDMI_ACR_STATUS_1 0x4d35 +#define mmDIG4_HDMI_ACR_STATUS_1 0x4e35 +#define mmDIG5_HDMI_ACR_STATUS_1 0x4f35 +#define mmDIG6_HDMI_ACR_STATUS_1 0x5435 +#define mmAFMT_AUDIO_INFO0 0x4a36 +#define mmDIG0_AFMT_AUDIO_INFO0 0x4a36 +#define mmDIG1_AFMT_AUDIO_INFO0 0x4b36 +#define mmDIG2_AFMT_AUDIO_INFO0 0x4c36 +#define mmDIG3_AFMT_AUDIO_INFO0 0x4d36 +#define mmDIG4_AFMT_AUDIO_INFO0 0x4e36 +#define mmDIG5_AFMT_AUDIO_INFO0 0x4f36 +#define mmDIG6_AFMT_AUDIO_INFO0 0x5436 +#define mmAFMT_AUDIO_INFO1 0x4a37 +#define mmDIG0_AFMT_AUDIO_INFO1 0x4a37 +#define mmDIG1_AFMT_AUDIO_INFO1 0x4b37 +#define mmDIG2_AFMT_AUDIO_INFO1 0x4c37 +#define mmDIG3_AFMT_AUDIO_INFO1 0x4d37 +#define mmDIG4_AFMT_AUDIO_INFO1 0x4e37 +#define mmDIG5_AFMT_AUDIO_INFO1 0x4f37 +#define mmDIG6_AFMT_AUDIO_INFO1 0x5437 +#define mmAFMT_60958_0 0x4a38 +#define mmDIG0_AFMT_60958_0 0x4a38 +#define mmDIG1_AFMT_60958_0 0x4b38 +#define mmDIG2_AFMT_60958_0 0x4c38 +#define mmDIG3_AFMT_60958_0 0x4d38 +#define mmDIG4_AFMT_60958_0 0x4e38 +#define mmDIG5_AFMT_60958_0 0x4f38 +#define mmDIG6_AFMT_60958_0 0x5438 +#define mmAFMT_60958_1 0x4a39 +#define mmDIG0_AFMT_60958_1 0x4a39 +#define mmDIG1_AFMT_60958_1 0x4b39 +#define mmDIG2_AFMT_60958_1 0x4c39 +#define mmDIG3_AFMT_60958_1 0x4d39 +#define mmDIG4_AFMT_60958_1 0x4e39 +#define mmDIG5_AFMT_60958_1 0x4f39 +#define mmDIG6_AFMT_60958_1 0x5439 +#define mmAFMT_AUDIO_CRC_CONTROL 0x4a3a +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a +#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a +#define mmAFMT_RAMP_CONTROL0 0x4a3b +#define mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b +#define mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b +#define mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b +#define mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b +#define mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b +#define mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b +#define mmDIG6_AFMT_RAMP_CONTROL0 0x543b +#define mmAFMT_RAMP_CONTROL1 0x4a3c +#define mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c +#define mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c +#define mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c +#define mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c +#define mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c +#define mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c +#define mmDIG6_AFMT_RAMP_CONTROL1 0x543c +#define mmAFMT_RAMP_CONTROL2 0x4a3d +#define mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d +#define mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d +#define mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d +#define mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d +#define mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d +#define mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d +#define mmDIG6_AFMT_RAMP_CONTROL2 0x543d +#define mmAFMT_RAMP_CONTROL3 0x4a3e +#define mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e +#define mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e +#define mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e +#define mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e +#define mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e +#define mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e +#define mmDIG6_AFMT_RAMP_CONTROL3 0x543e +#define mmAFMT_60958_2 0x4a3f +#define mmDIG0_AFMT_60958_2 0x4a3f +#define mmDIG1_AFMT_60958_2 0x4b3f +#define mmDIG2_AFMT_60958_2 0x4c3f +#define mmDIG3_AFMT_60958_2 0x4d3f +#define mmDIG4_AFMT_60958_2 0x4e3f +#define mmDIG5_AFMT_60958_2 0x4f3f +#define mmDIG6_AFMT_60958_2 0x543f +#define mmAFMT_AUDIO_CRC_RESULT 0x4a40 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40 +#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440 +#define mmAFMT_STATUS 0x4a41 +#define mmDIG0_AFMT_STATUS 0x4a41 +#define mmDIG1_AFMT_STATUS 0x4b41 +#define mmDIG2_AFMT_STATUS 0x4c41 +#define mmDIG3_AFMT_STATUS 0x4d41 +#define mmDIG4_AFMT_STATUS 0x4e41 +#define mmDIG5_AFMT_STATUS 0x4f41 +#define mmDIG6_AFMT_STATUS 0x5441 +#define mmAFMT_AUDIO_PACKET_CONTROL 0x4a42 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442 +#define mmAFMT_VBI_PACKET_CONTROL 0x4a43 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43 +#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43 +#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443 +#define mmAFMT_INFOFRAME_CONTROL0 0x4a44 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44 +#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444 +#define mmAFMT_AUDIO_SRC_CONTROL 0x4a45 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45 +#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445 +#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46 +#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46 +#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46 +#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46 +#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46 +#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46 +#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46 +#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446 +#define mmDIG_BE_CNTL 0x4a47 +#define mmDIG0_DIG_BE_CNTL 0x4a47 +#define mmDIG1_DIG_BE_CNTL 0x4b47 +#define mmDIG2_DIG_BE_CNTL 0x4c47 +#define mmDIG3_DIG_BE_CNTL 0x4d47 +#define mmDIG4_DIG_BE_CNTL 0x4e47 +#define mmDIG5_DIG_BE_CNTL 0x4f47 +#define mmDIG6_DIG_BE_CNTL 0x5447 +#define mmDIG_BE_EN_CNTL 0x4a48 +#define mmDIG0_DIG_BE_EN_CNTL 0x4a48 +#define mmDIG1_DIG_BE_EN_CNTL 0x4b48 +#define mmDIG2_DIG_BE_EN_CNTL 0x4c48 +#define mmDIG3_DIG_BE_EN_CNTL 0x4d48 +#define mmDIG4_DIG_BE_EN_CNTL 0x4e48 +#define mmDIG5_DIG_BE_EN_CNTL 0x4f48 +#define mmDIG6_DIG_BE_EN_CNTL 0x5448 +#define mmTMDS_CNTL 0x4a6b +#define mmDIG0_TMDS_CNTL 0x4a6b +#define mmDIG1_TMDS_CNTL 0x4b6b +#define mmDIG2_TMDS_CNTL 0x4c6b +#define mmDIG3_TMDS_CNTL 0x4d6b +#define mmDIG4_TMDS_CNTL 0x4e6b +#define mmDIG5_TMDS_CNTL 0x4f6b +#define mmDIG6_TMDS_CNTL 0x546b +#define mmTMDS_CONTROL_CHAR 0x4a6c +#define mmDIG0_TMDS_CONTROL_CHAR 0x4a6c +#define mmDIG1_TMDS_CONTROL_CHAR 0x4b6c +#define mmDIG2_TMDS_CONTROL_CHAR 0x4c6c +#define mmDIG3_TMDS_CONTROL_CHAR 0x4d6c +#define mmDIG4_TMDS_CONTROL_CHAR 0x4e6c +#define mmDIG5_TMDS_CONTROL_CHAR 0x4f6c +#define mmDIG6_TMDS_CONTROL_CHAR 0x546c +#define mmTMDS_CONTROL0_FEEDBACK 0x4a6d +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d +#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d +#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d +#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d +#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d +#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d +#define mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e +#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e +#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f +#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470 +#define mmTMDS_DEBUG 0x4a71 +#define mmDIG0_TMDS_DEBUG 0x4a71 +#define mmDIG1_TMDS_DEBUG 0x4b71 +#define mmDIG2_TMDS_DEBUG 0x4c71 +#define mmDIG3_TMDS_DEBUG 0x4d71 +#define mmDIG4_TMDS_DEBUG 0x4e71 +#define mmDIG5_TMDS_DEBUG 0x4f71 +#define mmDIG6_TMDS_DEBUG 0x5471 +#define mmTMDS_CTL_BITS 0x4a72 +#define mmDIG0_TMDS_CTL_BITS 0x4a72 +#define mmDIG1_TMDS_CTL_BITS 0x4b72 +#define mmDIG2_TMDS_CTL_BITS 0x4c72 +#define mmDIG3_TMDS_CTL_BITS 0x4d72 +#define mmDIG4_TMDS_CTL_BITS 0x4e72 +#define mmDIG5_TMDS_CTL_BITS 0x4f72 +#define mmDIG6_TMDS_CTL_BITS 0x5472 +#define mmTMDS_DCBALANCER_CONTROL 0x4a73 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 +#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73 +#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73 +#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73 +#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 +#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473 +#define mmTMDS_CTL0_1_GEN_CNTL 0x4a75 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75 +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75 +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75 +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75 +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75 +#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475 +#define mmTMDS_CTL2_3_GEN_CNTL 0x4a76 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76 +#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476 +#define ixTMDS_DEBUG1 0x1 +#define ixTMDS_DEBUG2 0x2 +#define ixTMDS_DEBUG3 0x3 +#define ixTMDS_DEBUG7 0x4 +#define ixTMDS_DEBUG8 0x5 +#define ixTMDS_DEBUG9 0x6 +#define ixTMDS_DEBUG10 0x7 +#define ixTMDS_DEBUG11 0x8 +#define ixTMDS_DEBUG12 0x9 +#define ixTMDS_DEBUG13 0xa +#define mmLVDS_DATA_CNTL 0x4a78 +#define mmDIG0_LVDS_DATA_CNTL 0x4a78 +#define mmDIG1_LVDS_DATA_CNTL 0x4b78 +#define mmDIG2_LVDS_DATA_CNTL 0x4c78 +#define mmDIG3_LVDS_DATA_CNTL 0x4d78 +#define mmDIG4_LVDS_DATA_CNTL 0x4e78 +#define mmDIG5_LVDS_DATA_CNTL 0x4f78 +#define mmDIG6_LVDS_DATA_CNTL 0x5478 +#define mmDIG_LANE_ENABLE 0x4a79 +#define mmDIG0_DIG_LANE_ENABLE 0x4a79 +#define mmDIG1_DIG_LANE_ENABLE 0x4b79 +#define mmDIG2_DIG_LANE_ENABLE 0x4c79 +#define mmDIG3_DIG_LANE_ENABLE 0x4d79 +#define mmDIG4_DIG_LANE_ENABLE 0x4e79 +#define mmDIG5_DIG_LANE_ENABLE 0x4f79 +#define mmDIG6_DIG_LANE_ENABLE 0x5479 +#define mmDIG_TEST_DEBUG_INDEX 0x4a7a +#define mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a +#define mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a +#define mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a +#define mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a +#define mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a +#define mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a +#define mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a +#define mmDIG_TEST_DEBUG_DATA 0x4a7b +#define mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b +#define mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b +#define mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b +#define mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b +#define mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b +#define mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b +#define mmDIG6_DIG_TEST_DEBUG_DATA 0x547b +#define mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c +#define mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c +#define mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c +#define mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c +#define mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c +#define mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c +#define mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c +#define mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c +#define mmDIG_FE_TEST_DEBUG_DATA 0x4a7d +#define mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d +#define mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d +#define mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d +#define mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d +#define mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d +#define mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d +#define mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d +#define mmDMCU_CTRL 0x1600 +#define mmDMCU_STATUS 0x1601 +#define mmDMCU_PC_START_ADDR 0x1602 +#define mmDMCU_FW_START_ADDR 0x1603 +#define mmDMCU_FW_END_ADDR 0x1604 +#define mmDMCU_FW_ISR_START_ADDR 0x1605 +#define mmDMCU_FW_CS_HI 0x1606 +#define mmDMCU_FW_CS_LO 0x1607 +#define mmDMCU_RAM_ACCESS_CTRL 0x1608 +#define mmDMCU_ERAM_WR_CTRL 0x1609 +#define mmDMCU_ERAM_WR_DATA 0x160a +#define mmDMCU_ERAM_RD_CTRL 0x160b +#define mmDMCU_ERAM_RD_DATA 0x160c +#define mmDMCU_IRAM_WR_CTRL 0x160d +#define mmDMCU_IRAM_WR_DATA 0x160e +#define mmDMCU_IRAM_RD_CTRL 0x160f +#define mmDMCU_IRAM_RD_DATA 0x1610 +#define mmDMCU_EVENT_TRIGGER 0x1611 +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 +#define mmDMCU_INTERRUPT_STATUS 0x1614 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 +#define mmDC_DMCU_SCRATCH 0x1618 +#define mmDMCU_INT_CNT 0x1619 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a +#define mmDMCU_UC_CLK_GATING_CNTL 0x161b +#define mmMASTER_COMM_DATA_REG1 0x161c +#define mmMASTER_COMM_DATA_REG2 0x161d +#define mmMASTER_COMM_DATA_REG3 0x161e +#define mmMASTER_COMM_CMD_REG 0x161f +#define mmMASTER_COMM_CNTL_REG 0x1620 +#define mmSLAVE_COMM_DATA_REG1 0x1621 +#define mmSLAVE_COMM_DATA_REG2 0x1622 +#define mmSLAVE_COMM_DATA_REG3 0x1623 +#define mmSLAVE_COMM_CMD_REG 0x1624 +#define mmSLAVE_COMM_CNTL_REG 0x1625 +#define mmDMCU_TEST_DEBUG_INDEX 0x1626 +#define mmDMCU_TEST_DEBUG_DATA 0x1627 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673 +#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x167c +#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x167d +#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x167e +#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x167f +#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5 0x1633 +#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636 +#define mmDP_LINK_CNTL 0x4aa0 +#define mmDP0_DP_LINK_CNTL 0x4aa0 +#define mmDP1_DP_LINK_CNTL 0x4ba0 +#define mmDP2_DP_LINK_CNTL 0x4ca0 +#define mmDP3_DP_LINK_CNTL 0x4da0 +#define mmDP4_DP_LINK_CNTL 0x4ea0 +#define mmDP5_DP_LINK_CNTL 0x4fa0 +#define mmDP6_DP_LINK_CNTL 0x54a0 +#define mmDP_PIXEL_FORMAT 0x4aa1 +#define mmDP0_DP_PIXEL_FORMAT 0x4aa1 +#define mmDP1_DP_PIXEL_FORMAT 0x4ba1 +#define mmDP2_DP_PIXEL_FORMAT 0x4ca1 +#define mmDP3_DP_PIXEL_FORMAT 0x4da1 +#define mmDP4_DP_PIXEL_FORMAT 0x4ea1 +#define mmDP5_DP_PIXEL_FORMAT 0x4fa1 +#define mmDP6_DP_PIXEL_FORMAT 0x54a1 +#define mmDP_MSA_COLORIMETRY 0x4aa2 +#define mmDP0_DP_MSA_COLORIMETRY 0x4aa2 +#define mmDP1_DP_MSA_COLORIMETRY 0x4ba2 +#define mmDP2_DP_MSA_COLORIMETRY 0x4ca2 +#define mmDP3_DP_MSA_COLORIMETRY 0x4da2 +#define mmDP4_DP_MSA_COLORIMETRY 0x4ea2 +#define mmDP5_DP_MSA_COLORIMETRY 0x4fa2 +#define mmDP6_DP_MSA_COLORIMETRY 0x54a2 +#define mmDP_CONFIG 0x4aa3 +#define mmDP0_DP_CONFIG 0x4aa3 +#define mmDP1_DP_CONFIG 0x4ba3 +#define mmDP2_DP_CONFIG 0x4ca3 +#define mmDP3_DP_CONFIG 0x4da3 +#define mmDP4_DP_CONFIG 0x4ea3 +#define mmDP5_DP_CONFIG 0x4fa3 +#define mmDP6_DP_CONFIG 0x54a3 +#define mmDP_VID_STREAM_CNTL 0x4aa4 +#define mmDP0_DP_VID_STREAM_CNTL 0x4aa4 +#define mmDP1_DP_VID_STREAM_CNTL 0x4ba4 +#define mmDP2_DP_VID_STREAM_CNTL 0x4ca4 +#define mmDP3_DP_VID_STREAM_CNTL 0x4da4 +#define mmDP4_DP_VID_STREAM_CNTL 0x4ea4 +#define mmDP5_DP_VID_STREAM_CNTL 0x4fa4 +#define mmDP6_DP_VID_STREAM_CNTL 0x54a4 +#define mmDP_STEER_FIFO 0x4aa5 +#define mmDP0_DP_STEER_FIFO 0x4aa5 +#define mmDP1_DP_STEER_FIFO 0x4ba5 +#define mmDP2_DP_STEER_FIFO 0x4ca5 +#define mmDP3_DP_STEER_FIFO 0x4da5 +#define mmDP4_DP_STEER_FIFO 0x4ea5 +#define mmDP5_DP_STEER_FIFO 0x4fa5 +#define mmDP6_DP_STEER_FIFO 0x54a5 +#define mmDP_MSA_MISC 0x4aa6 +#define mmDP0_DP_MSA_MISC 0x4aa6 +#define mmDP1_DP_MSA_MISC 0x4ba6 +#define mmDP2_DP_MSA_MISC 0x4ca6 +#define mmDP3_DP_MSA_MISC 0x4da6 +#define mmDP4_DP_MSA_MISC 0x4ea6 +#define mmDP5_DP_MSA_MISC 0x4fa6 +#define mmDP6_DP_MSA_MISC 0x54a6 +#define mmDP_VID_TIMING 0x4aa8 +#define mmDP0_DP_VID_TIMING 0x4aa8 +#define mmDP1_DP_VID_TIMING 0x4ba8 +#define mmDP2_DP_VID_TIMING 0x4ca8 +#define mmDP3_DP_VID_TIMING 0x4da8 +#define mmDP4_DP_VID_TIMING 0x4ea8 +#define mmDP5_DP_VID_TIMING 0x4fa8 +#define mmDP6_DP_VID_TIMING 0x54a8 +#define mmDP_VID_N 0x4aa9 +#define mmDP0_DP_VID_N 0x4aa9 +#define mmDP1_DP_VID_N 0x4ba9 +#define mmDP2_DP_VID_N 0x4ca9 +#define mmDP3_DP_VID_N 0x4da9 +#define mmDP4_DP_VID_N 0x4ea9 +#define mmDP5_DP_VID_N 0x4fa9 +#define mmDP6_DP_VID_N 0x54a9 +#define mmDP_VID_M 0x4aaa +#define mmDP0_DP_VID_M 0x4aaa +#define mmDP1_DP_VID_M 0x4baa +#define mmDP2_DP_VID_M 0x4caa +#define mmDP3_DP_VID_M 0x4daa +#define mmDP4_DP_VID_M 0x4eaa +#define mmDP5_DP_VID_M 0x4faa +#define mmDP6_DP_VID_M 0x54aa +#define mmDP_LINK_FRAMING_CNTL 0x4aab +#define mmDP0_DP_LINK_FRAMING_CNTL 0x4aab +#define mmDP1_DP_LINK_FRAMING_CNTL 0x4bab +#define mmDP2_DP_LINK_FRAMING_CNTL 0x4cab +#define mmDP3_DP_LINK_FRAMING_CNTL 0x4dab +#define mmDP4_DP_LINK_FRAMING_CNTL 0x4eab +#define mmDP5_DP_LINK_FRAMING_CNTL 0x4fab +#define mmDP6_DP_LINK_FRAMING_CNTL 0x54ab +#define mmDP_HBR2_EYE_PATTERN 0x4aac +#define mmDP0_DP_HBR2_EYE_PATTERN 0x4aac +#define mmDP1_DP_HBR2_EYE_PATTERN 0x4bac +#define mmDP2_DP_HBR2_EYE_PATTERN 0x4cac +#define mmDP3_DP_HBR2_EYE_PATTERN 0x4dac +#define mmDP4_DP_HBR2_EYE_PATTERN 0x4eac +#define mmDP5_DP_HBR2_EYE_PATTERN 0x4fac +#define mmDP6_DP_HBR2_EYE_PATTERN 0x54ac +#define mmDP_VID_MSA_VBID 0x4aad +#define mmDP0_DP_VID_MSA_VBID 0x4aad +#define mmDP1_DP_VID_MSA_VBID 0x4bad +#define mmDP2_DP_VID_MSA_VBID 0x4cad +#define mmDP3_DP_VID_MSA_VBID 0x4dad +#define mmDP4_DP_VID_MSA_VBID 0x4ead +#define mmDP5_DP_VID_MSA_VBID 0x4fad +#define mmDP6_DP_VID_MSA_VBID 0x54ad +#define mmDP_VID_INTERRUPT_CNTL 0x4aae +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae +#define mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae +#define mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae +#define mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae +#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae +#define mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae +#define mmDP_DPHY_CNTL 0x4aaf +#define mmDP0_DP_DPHY_CNTL 0x4aaf +#define mmDP1_DP_DPHY_CNTL 0x4baf +#define mmDP2_DP_DPHY_CNTL 0x4caf +#define mmDP3_DP_DPHY_CNTL 0x4daf +#define mmDP4_DP_DPHY_CNTL 0x4eaf +#define mmDP5_DP_DPHY_CNTL 0x4faf +#define mmDP6_DP_DPHY_CNTL 0x54af +#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0 +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0 +#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0 +#define mmDP_DPHY_SYM0 0x4ab1 +#define mmDP0_DP_DPHY_SYM0 0x4ab1 +#define mmDP1_DP_DPHY_SYM0 0x4bb1 +#define mmDP2_DP_DPHY_SYM0 0x4cb1 +#define mmDP3_DP_DPHY_SYM0 0x4db1 +#define mmDP4_DP_DPHY_SYM0 0x4eb1 +#define mmDP5_DP_DPHY_SYM0 0x4fb1 +#define mmDP6_DP_DPHY_SYM0 0x54b1 +#define mmDP_DPHY_SYM1 0x4ab2 +#define mmDP0_DP_DPHY_SYM1 0x4ab2 +#define mmDP1_DP_DPHY_SYM1 0x4bb2 +#define mmDP2_DP_DPHY_SYM1 0x4cb2 +#define mmDP3_DP_DPHY_SYM1 0x4db2 +#define mmDP4_DP_DPHY_SYM1 0x4eb2 +#define mmDP5_DP_DPHY_SYM1 0x4fb2 +#define mmDP6_DP_DPHY_SYM1 0x54b2 +#define mmDP_DPHY_SYM2 0x4ab3 +#define mmDP0_DP_DPHY_SYM2 0x4ab3 +#define mmDP1_DP_DPHY_SYM2 0x4bb3 +#define mmDP2_DP_DPHY_SYM2 0x4cb3 +#define mmDP3_DP_DPHY_SYM2 0x4db3 +#define mmDP4_DP_DPHY_SYM2 0x4eb3 +#define mmDP5_DP_DPHY_SYM2 0x4fb3 +#define mmDP6_DP_DPHY_SYM2 0x54b3 +#define mmDP_DPHY_8B10B_CNTL 0x4ab4 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4 +#define mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4 +#define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 +#define mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4 +#define mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4 +#define mmDP6_DP_DPHY_8B10B_CNTL 0x54b4 +#define mmDP_DPHY_PRBS_CNTL 0x4ab5 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 +#define mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5 +#define mmDP3_DP_DPHY_PRBS_CNTL 0x4db5 +#define mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 +#define mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 +#define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 +#define mmDP_DPHY_CRC_EN 0x4ab7 +#define mmDP0_DP_DPHY_CRC_EN 0x4ab7 +#define mmDP1_DP_DPHY_CRC_EN 0x4bb7 +#define mmDP2_DP_DPHY_CRC_EN 0x4cb7 +#define mmDP3_DP_DPHY_CRC_EN 0x4db7 +#define mmDP4_DP_DPHY_CRC_EN 0x4eb7 +#define mmDP5_DP_DPHY_CRC_EN 0x4fb7 +#define mmDP6_DP_DPHY_CRC_EN 0x54b7 +#define mmDP_DPHY_CRC_CNTL 0x4ab8 +#define mmDP0_DP_DPHY_CRC_CNTL 0x4ab8 +#define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 +#define mmDP2_DP_DPHY_CRC_CNTL 0x4cb8 +#define mmDP3_DP_DPHY_CRC_CNTL 0x4db8 +#define mmDP4_DP_DPHY_CRC_CNTL 0x4eb8 +#define mmDP5_DP_DPHY_CRC_CNTL 0x4fb8 +#define mmDP6_DP_DPHY_CRC_CNTL 0x54b8 +#define mmDP_DPHY_CRC_RESULT 0x4ab9 +#define mmDP0_DP_DPHY_CRC_RESULT 0x4ab9 +#define mmDP1_DP_DPHY_CRC_RESULT 0x4bb9 +#define mmDP2_DP_DPHY_CRC_RESULT 0x4cb9 +#define mmDP3_DP_DPHY_CRC_RESULT 0x4db9 +#define mmDP4_DP_DPHY_CRC_RESULT 0x4eb9 +#define mmDP5_DP_DPHY_CRC_RESULT 0x4fb9 +#define mmDP6_DP_DPHY_CRC_RESULT 0x54b9 +#define mmDP_DPHY_CRC_MST_CNTL 0x4aba +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba +#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba +#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba +#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba +#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba +#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba +#define mmDP_DPHY_CRC_MST_STATUS 0x4abb +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb +#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb +#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb +#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb +#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb +#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb +#define mmDP_DPHY_FAST_TRAINING 0x4abc +#define mmDP0_DP_DPHY_FAST_TRAINING 0x4abc +#define mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc +#define mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc +#define mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc +#define mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc +#define mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc +#define mmDP6_DP_DPHY_FAST_TRAINING 0x54bc +#define mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd +#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd +#define mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be +#define mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf +#define mmDP_SEC_CNTL 0x4ac3 +#define mmDP0_DP_SEC_CNTL 0x4ac3 +#define mmDP1_DP_SEC_CNTL 0x4bc3 +#define mmDP2_DP_SEC_CNTL 0x4cc3 +#define mmDP3_DP_SEC_CNTL 0x4dc3 +#define mmDP4_DP_SEC_CNTL 0x4ec3 +#define mmDP5_DP_SEC_CNTL 0x4fc3 +#define mmDP6_DP_SEC_CNTL 0x54c3 +#define mmDP_SEC_CNTL1 0x4ac4 +#define mmDP0_DP_SEC_CNTL1 0x4ac4 +#define mmDP1_DP_SEC_CNTL1 0x4bc4 +#define mmDP2_DP_SEC_CNTL1 0x4cc4 +#define mmDP3_DP_SEC_CNTL1 0x4dc4 +#define mmDP4_DP_SEC_CNTL1 0x4ec4 +#define mmDP5_DP_SEC_CNTL1 0x4fc4 +#define mmDP6_DP_SEC_CNTL1 0x54c4 +#define mmDP_SEC_FRAMING1 0x4ac5 +#define mmDP0_DP_SEC_FRAMING1 0x4ac5 +#define mmDP1_DP_SEC_FRAMING1 0x4bc5 +#define mmDP2_DP_SEC_FRAMING1 0x4cc5 +#define mmDP3_DP_SEC_FRAMING1 0x4dc5 +#define mmDP4_DP_SEC_FRAMING1 0x4ec5 +#define mmDP5_DP_SEC_FRAMING1 0x4fc5 +#define mmDP6_DP_SEC_FRAMING1 0x54c5 +#define mmDP_SEC_FRAMING2 0x4ac6 +#define mmDP0_DP_SEC_FRAMING2 0x4ac6 +#define mmDP1_DP_SEC_FRAMING2 0x4bc6 +#define mmDP2_DP_SEC_FRAMING2 0x4cc6 +#define mmDP3_DP_SEC_FRAMING2 0x4dc6 +#define mmDP4_DP_SEC_FRAMING2 0x4ec6 +#define mmDP5_DP_SEC_FRAMING2 0x4fc6 +#define mmDP6_DP_SEC_FRAMING2 0x54c6 +#define mmDP_SEC_FRAMING3 0x4ac7 +#define mmDP0_DP_SEC_FRAMING3 0x4ac7 +#define mmDP1_DP_SEC_FRAMING3 0x4bc7 +#define mmDP2_DP_SEC_FRAMING3 0x4cc7 +#define mmDP3_DP_SEC_FRAMING3 0x4dc7 +#define mmDP4_DP_SEC_FRAMING3 0x4ec7 +#define mmDP5_DP_SEC_FRAMING3 0x4fc7 +#define mmDP6_DP_SEC_FRAMING3 0x54c7 +#define mmDP_SEC_FRAMING4 0x4ac8 +#define mmDP0_DP_SEC_FRAMING4 0x4ac8 +#define mmDP1_DP_SEC_FRAMING4 0x4bc8 +#define mmDP2_DP_SEC_FRAMING4 0x4cc8 +#define mmDP3_DP_SEC_FRAMING4 0x4dc8 +#define mmDP4_DP_SEC_FRAMING4 0x4ec8 +#define mmDP5_DP_SEC_FRAMING4 0x4fc8 +#define mmDP6_DP_SEC_FRAMING4 0x54c8 +#define mmDP_SEC_AUD_N 0x4ac9 +#define mmDP0_DP_SEC_AUD_N 0x4ac9 +#define mmDP1_DP_SEC_AUD_N 0x4bc9 +#define mmDP2_DP_SEC_AUD_N 0x4cc9 +#define mmDP3_DP_SEC_AUD_N 0x4dc9 +#define mmDP4_DP_SEC_AUD_N 0x4ec9 +#define mmDP5_DP_SEC_AUD_N 0x4fc9 +#define mmDP6_DP_SEC_AUD_N 0x54c9 +#define mmDP_SEC_AUD_N_READBACK 0x4aca +#define mmDP0_DP_SEC_AUD_N_READBACK 0x4aca +#define mmDP1_DP_SEC_AUD_N_READBACK 0x4bca +#define mmDP2_DP_SEC_AUD_N_READBACK 0x4cca +#define mmDP3_DP_SEC_AUD_N_READBACK 0x4dca +#define mmDP4_DP_SEC_AUD_N_READBACK 0x4eca +#define mmDP5_DP_SEC_AUD_N_READBACK 0x4fca +#define mmDP6_DP_SEC_AUD_N_READBACK 0x54ca +#define mmDP_SEC_AUD_M 0x4acb +#define mmDP0_DP_SEC_AUD_M 0x4acb +#define mmDP1_DP_SEC_AUD_M 0x4bcb +#define mmDP2_DP_SEC_AUD_M 0x4ccb +#define mmDP3_DP_SEC_AUD_M 0x4dcb +#define mmDP4_DP_SEC_AUD_M 0x4ecb +#define mmDP5_DP_SEC_AUD_M 0x4fcb +#define mmDP6_DP_SEC_AUD_M 0x54cb +#define mmDP_SEC_AUD_M_READBACK 0x4acc +#define mmDP0_DP_SEC_AUD_M_READBACK 0x4acc +#define mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc +#define mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc +#define mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc +#define mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc +#define mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc +#define mmDP6_DP_SEC_AUD_M_READBACK 0x54cc +#define mmDP_SEC_TIMESTAMP 0x4acd +#define mmDP0_DP_SEC_TIMESTAMP 0x4acd +#define mmDP1_DP_SEC_TIMESTAMP 0x4bcd +#define mmDP2_DP_SEC_TIMESTAMP 0x4ccd +#define mmDP3_DP_SEC_TIMESTAMP 0x4dcd +#define mmDP4_DP_SEC_TIMESTAMP 0x4ecd +#define mmDP5_DP_SEC_TIMESTAMP 0x4fcd +#define mmDP6_DP_SEC_TIMESTAMP 0x54cd +#define mmDP_SEC_PACKET_CNTL 0x4ace +#define mmDP0_DP_SEC_PACKET_CNTL 0x4ace +#define mmDP1_DP_SEC_PACKET_CNTL 0x4bce +#define mmDP2_DP_SEC_PACKET_CNTL 0x4cce +#define mmDP3_DP_SEC_PACKET_CNTL 0x4dce +#define mmDP4_DP_SEC_PACKET_CNTL 0x4ece +#define mmDP5_DP_SEC_PACKET_CNTL 0x4fce +#define mmDP6_DP_SEC_PACKET_CNTL 0x54ce +#define mmDP_MSE_RATE_CNTL 0x4acf +#define mmDP0_DP_MSE_RATE_CNTL 0x4acf +#define mmDP1_DP_MSE_RATE_CNTL 0x4bcf +#define mmDP2_DP_MSE_RATE_CNTL 0x4ccf +#define mmDP3_DP_MSE_RATE_CNTL 0x4dcf +#define mmDP4_DP_MSE_RATE_CNTL 0x4ecf +#define mmDP5_DP_MSE_RATE_CNTL 0x4fcf +#define mmDP6_DP_MSE_RATE_CNTL 0x54cf +#define mmDP_MSE_RATE_UPDATE 0x4ad1 +#define mmDP0_DP_MSE_RATE_UPDATE 0x4ad1 +#define mmDP1_DP_MSE_RATE_UPDATE 0x4bd1 +#define mmDP2_DP_MSE_RATE_UPDATE 0x4cd1 +#define mmDP3_DP_MSE_RATE_UPDATE 0x4dd1 +#define mmDP4_DP_MSE_RATE_UPDATE 0x4ed1 +#define mmDP5_DP_MSE_RATE_UPDATE 0x4fd1 +#define mmDP6_DP_MSE_RATE_UPDATE 0x54d1 +#define mmDP_MSE_SAT0 0x4ad2 +#define mmDP0_DP_MSE_SAT0 0x4ad2 +#define mmDP1_DP_MSE_SAT0 0x4bd2 +#define mmDP2_DP_MSE_SAT0 0x4cd2 +#define mmDP3_DP_MSE_SAT0 0x4dd2 +#define mmDP4_DP_MSE_SAT0 0x4ed2 +#define mmDP5_DP_MSE_SAT0 0x4fd2 +#define mmDP6_DP_MSE_SAT0 0x54d2 +#define mmDP_MSE_SAT1 0x4ad3 +#define mmDP0_DP_MSE_SAT1 0x4ad3 +#define mmDP1_DP_MSE_SAT1 0x4bd3 +#define mmDP2_DP_MSE_SAT1 0x4cd3 +#define mmDP3_DP_MSE_SAT1 0x4dd3 +#define mmDP4_DP_MSE_SAT1 0x4ed3 +#define mmDP5_DP_MSE_SAT1 0x4fd3 +#define mmDP6_DP_MSE_SAT1 0x54d3 +#define mmDP_MSE_SAT2 0x4ad4 +#define mmDP0_DP_MSE_SAT2 0x4ad4 +#define mmDP1_DP_MSE_SAT2 0x4bd4 +#define mmDP2_DP_MSE_SAT2 0x4cd4 +#define mmDP3_DP_MSE_SAT2 0x4dd4 +#define mmDP4_DP_MSE_SAT2 0x4ed4 +#define mmDP5_DP_MSE_SAT2 0x4fd4 +#define mmDP6_DP_MSE_SAT2 0x54d4 +#define mmDP_MSE_SAT_UPDATE 0x4ad5 +#define mmDP0_DP_MSE_SAT_UPDATE 0x4ad5 +#define mmDP1_DP_MSE_SAT_UPDATE 0x4bd5 +#define mmDP2_DP_MSE_SAT_UPDATE 0x4cd5 +#define mmDP3_DP_MSE_SAT_UPDATE 0x4dd5 +#define mmDP4_DP_MSE_SAT_UPDATE 0x4ed5 +#define mmDP5_DP_MSE_SAT_UPDATE 0x4fd5 +#define mmDP6_DP_MSE_SAT_UPDATE 0x54d5 +#define mmDP_MSE_LINK_TIMING 0x4ad6 +#define mmDP0_DP_MSE_LINK_TIMING 0x4ad6 +#define mmDP1_DP_MSE_LINK_TIMING 0x4bd6 +#define mmDP2_DP_MSE_LINK_TIMING 0x4cd6 +#define mmDP3_DP_MSE_LINK_TIMING 0x4dd6 +#define mmDP4_DP_MSE_LINK_TIMING 0x4ed6 +#define mmDP5_DP_MSE_LINK_TIMING 0x4fd6 +#define mmDP6_DP_MSE_LINK_TIMING 0x54d6 +#define mmDP_MSE_MISC_CNTL 0x4ad7 +#define mmDP0_DP_MSE_MISC_CNTL 0x4ad7 +#define mmDP1_DP_MSE_MISC_CNTL 0x4bd7 +#define mmDP2_DP_MSE_MISC_CNTL 0x4cd7 +#define mmDP3_DP_MSE_MISC_CNTL 0x4dd7 +#define mmDP4_DP_MSE_MISC_CNTL 0x4ed7 +#define mmDP5_DP_MSE_MISC_CNTL 0x4fd7 +#define mmDP6_DP_MSE_MISC_CNTL 0x54d7 +#define mmDP_TEST_DEBUG_INDEX 0x4ad8 +#define mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8 +#define mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8 +#define mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8 +#define mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8 +#define mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8 +#define mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8 +#define mmDP6_DP_TEST_DEBUG_INDEX 0x54d8 +#define mmDP_TEST_DEBUG_DATA 0x4ad9 +#define mmDP0_DP_TEST_DEBUG_DATA 0x4ad9 +#define mmDP1_DP_TEST_DEBUG_DATA 0x4bd9 +#define mmDP2_DP_TEST_DEBUG_DATA 0x4cd9 +#define mmDP3_DP_TEST_DEBUG_DATA 0x4dd9 +#define mmDP4_DP_TEST_DEBUG_DATA 0x4ed9 +#define mmDP5_DP_TEST_DEBUG_DATA 0x4fd9 +#define mmDP6_DP_TEST_DEBUG_DATA 0x54d9 +#define mmDP_FE_TEST_DEBUG_INDEX 0x4ada +#define mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada +#define mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda +#define mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda +#define mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda +#define mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda +#define mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda +#define mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da +#define mmDP_FE_TEST_DEBUG_DATA 0x4adb +#define mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb +#define mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb +#define mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb +#define mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb +#define mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb +#define mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb +#define mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db +#define mmAUX_CONTROL 0x5c00 +#define mmDP_AUX0_AUX_CONTROL 0x5c00 +#define mmDP_AUX1_AUX_CONTROL 0x5c1c +#define mmDP_AUX2_AUX_CONTROL 0x5c38 +#define mmDP_AUX3_AUX_CONTROL 0x5c54 +#define mmDP_AUX4_AUX_CONTROL 0x5c70 +#define mmDP_AUX5_AUX_CONTROL 0x5c8c +#define mmAUX_SW_CONTROL 0x5c01 +#define mmDP_AUX0_AUX_SW_CONTROL 0x5c01 +#define mmDP_AUX1_AUX_SW_CONTROL 0x5c1d +#define mmDP_AUX2_AUX_SW_CONTROL 0x5c39 +#define mmDP_AUX3_AUX_SW_CONTROL 0x5c55 +#define mmDP_AUX4_AUX_SW_CONTROL 0x5c71 +#define mmDP_AUX5_AUX_SW_CONTROL 0x5c8d +#define mmAUX_ARB_CONTROL 0x5c02 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x5c02 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e +#define mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a +#define mmDP_AUX3_AUX_ARB_CONTROL 0x5c56 +#define mmDP_AUX4_AUX_ARB_CONTROL 0x5c72 +#define mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e +#define mmAUX_INTERRUPT_CONTROL 0x5c03 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f +#define mmAUX_SW_STATUS 0x5c04 +#define mmDP_AUX0_AUX_SW_STATUS 0x5c04 +#define mmDP_AUX1_AUX_SW_STATUS 0x5c20 +#define mmDP_AUX2_AUX_SW_STATUS 0x5c3c +#define mmDP_AUX3_AUX_SW_STATUS 0x5c58 +#define mmDP_AUX4_AUX_SW_STATUS 0x5c74 +#define mmDP_AUX5_AUX_SW_STATUS 0x5c90 +#define mmAUX_LS_STATUS 0x5c05 +#define mmDP_AUX0_AUX_LS_STATUS 0x5c05 +#define mmDP_AUX1_AUX_LS_STATUS 0x5c21 +#define mmDP_AUX2_AUX_LS_STATUS 0x5c3d +#define mmDP_AUX3_AUX_LS_STATUS 0x5c59 +#define mmDP_AUX4_AUX_LS_STATUS 0x5c75 +#define mmDP_AUX5_AUX_LS_STATUS 0x5c91 +#define mmAUX_SW_DATA 0x5c06 +#define mmDP_AUX0_AUX_SW_DATA 0x5c06 +#define mmDP_AUX1_AUX_SW_DATA 0x5c22 +#define mmDP_AUX2_AUX_SW_DATA 0x5c3e +#define mmDP_AUX3_AUX_SW_DATA 0x5c5a +#define mmDP_AUX4_AUX_SW_DATA 0x5c76 +#define mmDP_AUX5_AUX_SW_DATA 0x5c92 +#define mmAUX_LS_DATA 0x5c07 +#define mmDP_AUX0_AUX_LS_DATA 0x5c07 +#define mmDP_AUX1_AUX_LS_DATA 0x5c23 +#define mmDP_AUX2_AUX_LS_DATA 0x5c3f +#define mmDP_AUX3_AUX_LS_DATA 0x5c5b +#define mmDP_AUX4_AUX_LS_DATA 0x5c77 +#define mmDP_AUX5_AUX_LS_DATA 0x5c93 +#define mmAUX_DPHY_TX_REF_CONTROL 0x5c08 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94 +#define mmAUX_DPHY_TX_CONTROL 0x5c09 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41 +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95 +#define mmAUX_DPHY_RX_CONTROL0 0x5c0a +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96 +#define mmAUX_DPHY_RX_CONTROL1 0x5c0b +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97 +#define mmAUX_DPHY_TX_STATUS 0x5c0c +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60 +#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c +#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98 +#define mmAUX_DPHY_RX_STATUS 0x5c0d +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61 +#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d +#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99 +#define mmAUX_GTC_SYNC_CONTROL 0x5c0e +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a +#define mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63 +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f +#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b +#define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c +#define mmAUX_GTC_SYNC_STATUS 0x5c11 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11 +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49 +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81 +#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d +#define mmAUX_GTC_SYNC_DATA 0x5c12 +#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12 +#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e +#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a +#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66 +#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82 +#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e +#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 +#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 +#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f +#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b +#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67 +#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83 +#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f +#define mmAUX_TEST_DEBUG_INDEX 0x5c14 +#define mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14 +#define mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30 +#define mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c +#define mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68 +#define mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84 +#define mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0 +#define mmAUX_TEST_DEBUG_DATA 0x5c15 +#define mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15 +#define mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31 +#define mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d +#define mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69 +#define mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85 +#define mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1 +#define ixDP_AUX_DEBUG_A 0x10 +#define ixDP_AUX_DEBUG_B 0x11 +#define ixDP_AUX_DEBUG_C 0x12 +#define ixDP_AUX_DEBUG_D 0x13 +#define ixDP_AUX_DEBUG_E 0x14 +#define ixDP_AUX_DEBUG_F 0x15 +#define ixDP_AUX_DEBUG_G 0x16 +#define ixDP_AUX_DEBUG_H 0x17 +#define ixDP_AUX_DEBUG_I 0x18 +#define ixDP_AUX_DEBUG_J 0x19 +#define ixDP_AUX_DEBUG_K 0x1a +#define ixDP_AUX_DEBUG_L 0x1b +#define ixDP_AUX_DEBUG_M 0x1c +#define ixDP_AUX_DEBUG_N 0x1d +#define ixDP_AUX_DEBUG_O 0x1e +#define ixDP_AUX_DEBUG_P 0x1f +#define ixDP_AUX_DEBUG_Q 0x20 +#define mmDVO_ENABLE 0x16a0 +#define mmDVO_SOURCE_SELECT 0x16a1 +#define mmDVO_OUTPUT 0x16a2 +#define mmDVO_CONTROL 0x16a3 +#define mmDVO_CRC_EN 0x16a4 +#define mmDVO_CRC2_SIG_MASK 0x16a5 +#define mmDVO_CRC2_SIG_RESULT 0x16a6 +#define mmDVO_FIFO_ERROR_STATUS 0x16a7 +#define mmDVO_TEST_DEBUG_INDEX 0x16a8 +#define mmDVO_TEST_DEBUG_DATA 0x16a9 +#define mmFBC_CNTL 0x280 +#define mmFBC_IDLE_MASK 0x281 +#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x282 +#define mmFBC_START_STOP_DELAY 0x283 +#define mmFBC_COMP_CNTL 0x284 +#define mmFBC_COMP_MODE 0x285 +#define mmFBC_DEBUG0 0x286 +#define mmFBC_DEBUG1 0x287 +#define mmFBC_DEBUG2 0x288 +#define mmFBC_IND_LUT0 0x289 +#define mmFBC_IND_LUT1 0x28a +#define mmFBC_IND_LUT2 0x28b +#define mmFBC_IND_LUT3 0x28c +#define mmFBC_IND_LUT4 0x28d +#define mmFBC_IND_LUT5 0x28e +#define mmFBC_IND_LUT6 0x28f +#define mmFBC_IND_LUT7 0x290 +#define mmFBC_IND_LUT8 0x291 +#define mmFBC_IND_LUT9 0x292 +#define mmFBC_IND_LUT10 0x293 +#define mmFBC_IND_LUT11 0x294 +#define mmFBC_IND_LUT12 0x295 +#define mmFBC_IND_LUT13 0x296 +#define mmFBC_IND_LUT14 0x297 +#define mmFBC_IND_LUT15 0x298 +#define mmFBC_CSM_REGION_OFFSET_01 0x299 +#define mmFBC_CSM_REGION_OFFSET_23 0x29a +#define mmFBC_CLIENT_REGION_MASK 0x29b +#define mmFBC_DEBUG_COMP 0x29c +#define mmFBC_DEBUG_CSR 0x29d +#define mmFBC_DEBUG_CSR_RDATA 0x29e +#define mmFBC_DEBUG_CSR_WDATA 0x29f +#define mmFBC_DEBUG_CSR_RDATA_HI 0x2a0 +#define mmFBC_DEBUG_CSR_WDATA_HI 0x2a1 +#define mmFBC_MISC 0x2a2 +#define mmFBC_STATUS 0x2a3 +#define mmFBC_TEST_DEBUG_INDEX 0x2a4 +#define mmFBC_TEST_DEBUG_DATA 0x2a5 +#define mmFMT_CLAMP_COMPONENT_R 0x1be8 +#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 +#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8 +#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8 +#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8 +#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8 +#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8 +#define mmFMT_CLAMP_COMPONENT_G 0x1be9 +#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 +#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9 +#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9 +#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9 +#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9 +#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9 +#define mmFMT_CLAMP_COMPONENT_B 0x1bea +#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea +#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea +#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea +#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea +#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea +#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea +#define mmFMT_DYNAMIC_EXP_CNTL 0x1bed +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed +#define mmFMT_CONTROL 0x1bee +#define mmFMT0_FMT_CONTROL 0x1bee +#define mmFMT1_FMT_CONTROL 0x1dee +#define mmFMT2_FMT_CONTROL 0x1fee +#define mmFMT3_FMT_CONTROL 0x41ee +#define mmFMT4_FMT_CONTROL 0x43ee +#define mmFMT5_FMT_CONTROL 0x45ee +#define mmFMT_FORCE_OUTPUT_CNTL 0x1bef +#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef +#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1def +#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x1fef +#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x41ef +#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x43ef +#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x45ef +#define mmFMT_FORCE_DATA_0_1 0x1bf0 +#define mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0 +#define mmFMT1_FMT_FORCE_DATA_0_1 0x1df0 +#define mmFMT2_FMT_FORCE_DATA_0_1 0x1ff0 +#define mmFMT3_FMT_FORCE_DATA_0_1 0x41f0 +#define mmFMT4_FMT_FORCE_DATA_0_1 0x43f0 +#define mmFMT5_FMT_FORCE_DATA_0_1 0x45f0 +#define mmFMT_FORCE_DATA_2_3 0x1bf1 +#define mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1 +#define mmFMT1_FMT_FORCE_DATA_2_3 0x1df1 +#define mmFMT2_FMT_FORCE_DATA_2_3 0x1ff1 +#define mmFMT3_FMT_FORCE_DATA_2_3 0x41f1 +#define mmFMT4_FMT_FORCE_DATA_2_3 0x43f1 +#define mmFMT5_FMT_FORCE_DATA_2_3 0x45f1 +#define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2 +#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2 +#define mmFMT_DITHER_RAND_R_SEED 0x1bf3 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3 +#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3 +#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3 +#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3 +#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3 +#define mmFMT_DITHER_RAND_G_SEED 0x1bf4 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4 +#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4 +#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4 +#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4 +#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4 +#define mmFMT_DITHER_RAND_B_SEED 0x1bf5 +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5 +#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5 +#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5 +#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5 +#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5 +#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6 +#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6 +#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 +#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6 +#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8 +#define mmFMT_CLAMP_CNTL 0x1bf9 +#define mmFMT0_FMT_CLAMP_CNTL 0x1bf9 +#define mmFMT1_FMT_CLAMP_CNTL 0x1df9 +#define mmFMT2_FMT_CLAMP_CNTL 0x1ff9 +#define mmFMT3_FMT_CLAMP_CNTL 0x41f9 +#define mmFMT4_FMT_CLAMP_CNTL 0x43f9 +#define mmFMT5_FMT_CLAMP_CNTL 0x45f9 +#define mmFMT_CRC_CNTL 0x1bfa +#define mmFMT0_FMT_CRC_CNTL 0x1bfa +#define mmFMT1_FMT_CRC_CNTL 0x1dfa +#define mmFMT2_FMT_CRC_CNTL 0x1ffa +#define mmFMT3_FMT_CRC_CNTL 0x41fa +#define mmFMT4_FMT_CRC_CNTL 0x43fa +#define mmFMT5_FMT_CRC_CNTL 0x45fa +#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb +#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc +#define mmFMT_CRC_SIG_RED_GREEN 0x1bfd +#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd +#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd +#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd +#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd +#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd +#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd +#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe +#define mmFMT_DEBUG_CNTL 0x1bff +#define mmFMT0_FMT_DEBUG_CNTL 0x1bff +#define mmFMT1_FMT_DEBUG_CNTL 0x1dff +#define mmFMT2_FMT_DEBUG_CNTL 0x1fff +#define mmFMT3_FMT_DEBUG_CNTL 0x41ff +#define mmFMT4_FMT_DEBUG_CNTL 0x43ff +#define mmFMT5_FMT_DEBUG_CNTL 0x45ff +#define mmFMT_TEST_DEBUG_INDEX 0x1beb +#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb +#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb +#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb +#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb +#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb +#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb +#define mmFMT_TEST_DEBUG_DATA 0x1bec +#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec +#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec +#define mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec +#define mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec +#define mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec +#define mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec +#define ixFMT_DEBUG0 0x1 +#define ixFMT_DEBUG1 0x2 +#define ixFMT_DEBUG2 0x3 +#define ixFMT_DEBUG_ID 0x0 +#define mmLB_DATA_FORMAT 0x1ac0 +#define mmLB0_LB_DATA_FORMAT 0x1ac0 +#define mmLB1_LB_DATA_FORMAT 0x1cc0 +#define mmLB2_LB_DATA_FORMAT 0x1ec0 +#define mmLB3_LB_DATA_FORMAT 0x40c0 +#define mmLB4_LB_DATA_FORMAT 0x42c0 +#define mmLB5_LB_DATA_FORMAT 0x44c0 +#define mmLB_MEMORY_CTRL 0x1ac1 +#define mmLB0_LB_MEMORY_CTRL 0x1ac1 +#define mmLB1_LB_MEMORY_CTRL 0x1cc1 +#define mmLB2_LB_MEMORY_CTRL 0x1ec1 +#define mmLB3_LB_MEMORY_CTRL 0x40c1 +#define mmLB4_LB_MEMORY_CTRL 0x42c1 +#define mmLB5_LB_MEMORY_CTRL 0x44c1 +#define mmLB_MEMORY_SIZE_STATUS 0x1ac2 +#define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 +#define mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2 +#define mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2 +#define mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2 +#define mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2 +#define mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2 +#define mmLB_DESKTOP_HEIGHT 0x1ac3 +#define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 +#define mmLB1_LB_DESKTOP_HEIGHT 0x1cc3 +#define mmLB2_LB_DESKTOP_HEIGHT 0x1ec3 +#define mmLB3_LB_DESKTOP_HEIGHT 0x40c3 +#define mmLB4_LB_DESKTOP_HEIGHT 0x42c3 +#define mmLB5_LB_DESKTOP_HEIGHT 0x44c3 +#define mmLB_VLINE_START_END 0x1ac4 +#define mmLB0_LB_VLINE_START_END 0x1ac4 +#define mmLB1_LB_VLINE_START_END 0x1cc4 +#define mmLB2_LB_VLINE_START_END 0x1ec4 +#define mmLB3_LB_VLINE_START_END 0x40c4 +#define mmLB4_LB_VLINE_START_END 0x42c4 +#define mmLB5_LB_VLINE_START_END 0x44c4 +#define mmLB_VLINE2_START_END 0x1ac5 +#define mmLB0_LB_VLINE2_START_END 0x1ac5 +#define mmLB1_LB_VLINE2_START_END 0x1cc5 +#define mmLB2_LB_VLINE2_START_END 0x1ec5 +#define mmLB3_LB_VLINE2_START_END 0x40c5 +#define mmLB4_LB_VLINE2_START_END 0x42c5 +#define mmLB5_LB_VLINE2_START_END 0x44c5 +#define mmLB_V_COUNTER 0x1ac6 +#define mmLB0_LB_V_COUNTER 0x1ac6 +#define mmLB1_LB_V_COUNTER 0x1cc6 +#define mmLB2_LB_V_COUNTER 0x1ec6 +#define mmLB3_LB_V_COUNTER 0x40c6 +#define mmLB4_LB_V_COUNTER 0x42c6 +#define mmLB5_LB_V_COUNTER 0x44c6 +#define mmLB_SNAPSHOT_V_COUNTER 0x1ac7 +#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 +#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7 +#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7 +#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7 +#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7 +#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7 +#define mmLB_INTERRUPT_MASK 0x1ac8 +#define mmLB0_LB_INTERRUPT_MASK 0x1ac8 +#define mmLB1_LB_INTERRUPT_MASK 0x1cc8 +#define mmLB2_LB_INTERRUPT_MASK 0x1ec8 +#define mmLB3_LB_INTERRUPT_MASK 0x40c8 +#define mmLB4_LB_INTERRUPT_MASK 0x42c8 +#define mmLB5_LB_INTERRUPT_MASK 0x44c8 +#define mmLB_VLINE_STATUS 0x1ac9 +#define mmLB0_LB_VLINE_STATUS 0x1ac9 +#define mmLB1_LB_VLINE_STATUS 0x1cc9 +#define mmLB2_LB_VLINE_STATUS 0x1ec9 +#define mmLB3_LB_VLINE_STATUS 0x40c9 +#define mmLB4_LB_VLINE_STATUS 0x42c9 +#define mmLB5_LB_VLINE_STATUS 0x44c9 +#define mmLB_VLINE2_STATUS 0x1aca +#define mmLB0_LB_VLINE2_STATUS 0x1aca +#define mmLB1_LB_VLINE2_STATUS 0x1cca +#define mmLB2_LB_VLINE2_STATUS 0x1eca +#define mmLB3_LB_VLINE2_STATUS 0x40ca +#define mmLB4_LB_VLINE2_STATUS 0x42ca +#define mmLB5_LB_VLINE2_STATUS 0x44ca +#define mmLB_VBLANK_STATUS 0x1acb +#define mmLB0_LB_VBLANK_STATUS 0x1acb +#define mmLB1_LB_VBLANK_STATUS 0x1ccb +#define mmLB2_LB_VBLANK_STATUS 0x1ecb +#define mmLB3_LB_VBLANK_STATUS 0x40cb +#define mmLB4_LB_VBLANK_STATUS 0x42cb +#define mmLB5_LB_VBLANK_STATUS 0x44cb +#define mmLB_SYNC_RESET_SEL 0x1acc +#define mmLB0_LB_SYNC_RESET_SEL 0x1acc +#define mmLB1_LB_SYNC_RESET_SEL 0x1ccc +#define mmLB2_LB_SYNC_RESET_SEL 0x1ecc +#define mmLB3_LB_SYNC_RESET_SEL 0x40cc +#define mmLB4_LB_SYNC_RESET_SEL 0x42cc +#define mmLB5_LB_SYNC_RESET_SEL 0x44cc +#define mmLB_BLACK_KEYER_R_CR 0x1acd +#define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd +#define mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd +#define mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd +#define mmLB3_LB_BLACK_KEYER_R_CR 0x40cd +#define mmLB4_LB_BLACK_KEYER_R_CR 0x42cd +#define mmLB5_LB_BLACK_KEYER_R_CR 0x44cd +#define mmLB_BLACK_KEYER_G_Y 0x1ace +#define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace +#define mmLB1_LB_BLACK_KEYER_G_Y 0x1cce +#define mmLB2_LB_BLACK_KEYER_G_Y 0x1ece +#define mmLB3_LB_BLACK_KEYER_G_Y 0x40ce +#define mmLB4_LB_BLACK_KEYER_G_Y 0x42ce +#define mmLB5_LB_BLACK_KEYER_G_Y 0x44ce +#define mmLB_BLACK_KEYER_B_CB 0x1acf +#define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf +#define mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf +#define mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf +#define mmLB3_LB_BLACK_KEYER_B_CB 0x40cf +#define mmLB4_LB_BLACK_KEYER_B_CB 0x42cf +#define mmLB5_LB_BLACK_KEYER_B_CB 0x44cf +#define mmLB_KEYER_COLOR_CTRL 0x1ad0 +#define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 +#define mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0 +#define mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0 +#define mmLB3_LB_KEYER_COLOR_CTRL 0x40d0 +#define mmLB4_LB_KEYER_COLOR_CTRL 0x42d0 +#define mmLB5_LB_KEYER_COLOR_CTRL 0x44d0 +#define mmLB_KEYER_COLOR_R_CR 0x1ad1 +#define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 +#define mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1 +#define mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1 +#define mmLB3_LB_KEYER_COLOR_R_CR 0x40d1 +#define mmLB4_LB_KEYER_COLOR_R_CR 0x42d1 +#define mmLB5_LB_KEYER_COLOR_R_CR 0x44d1 +#define mmLB_KEYER_COLOR_G_Y 0x1ad2 +#define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 +#define mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2 +#define mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2 +#define mmLB3_LB_KEYER_COLOR_G_Y 0x40d2 +#define mmLB4_LB_KEYER_COLOR_G_Y 0x42d2 +#define mmLB5_LB_KEYER_COLOR_G_Y 0x44d2 +#define mmLB_KEYER_COLOR_B_CB 0x1ad3 +#define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 +#define mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3 +#define mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3 +#define mmLB3_LB_KEYER_COLOR_B_CB 0x40d3 +#define mmLB4_LB_KEYER_COLOR_B_CB 0x42d3 +#define mmLB5_LB_KEYER_COLOR_B_CB 0x44d3 +#define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4 +#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4 +#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4 +#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4 +#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4 +#define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5 +#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5 +#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5 +#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5 +#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5 +#define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6 +#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6 +#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6 +#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6 +#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6 +#define mmLB_BUFFER_LEVEL_STATUS 0x1ad7 +#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 +#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7 +#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7 +#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7 +#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7 +#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7 +#define mmLB_BUFFER_URGENCY_CTRL 0x1ad8 +#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 +#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8 +#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8 +#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8 +#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8 +#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8 +#define mmLB_BUFFER_URGENCY_STATUS 0x1ad9 +#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 +#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9 +#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9 +#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9 +#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9 +#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9 +#define mmLB_BUFFER_STATUS 0x1ada +#define mmLB0_LB_BUFFER_STATUS 0x1ada +#define mmLB1_LB_BUFFER_STATUS 0x1cda +#define mmLB2_LB_BUFFER_STATUS 0x1eda +#define mmLB3_LB_BUFFER_STATUS 0x40da +#define mmLB4_LB_BUFFER_STATUS 0x42da +#define mmLB5_LB_BUFFER_STATUS 0x44da +#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc +#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc +#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc +#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc +#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc +#define mmMVP_AFR_FLIP_MODE 0x1ae0 +#define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 +#define mmLB1_MVP_AFR_FLIP_MODE 0x1ce0 +#define mmLB2_MVP_AFR_FLIP_MODE 0x1ee0 +#define mmLB3_MVP_AFR_FLIP_MODE 0x40e0 +#define mmLB4_MVP_AFR_FLIP_MODE 0x42e0 +#define mmLB5_MVP_AFR_FLIP_MODE 0x44e0 +#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1 +#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1 +#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 +#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1 +#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1 +#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2 +#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2 +#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2 +#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2 +#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2 +#define mmDC_MVP_LB_CONTROL 0x1ae3 +#define mmLB0_DC_MVP_LB_CONTROL 0x1ae3 +#define mmLB1_DC_MVP_LB_CONTROL 0x1ce3 +#define mmLB2_DC_MVP_LB_CONTROL 0x1ee3 +#define mmLB3_DC_MVP_LB_CONTROL 0x40e3 +#define mmLB4_DC_MVP_LB_CONTROL 0x42e3 +#define mmLB5_DC_MVP_LB_CONTROL 0x44e3 +#define mmLB_DEBUG 0x1ae4 +#define mmLB0_LB_DEBUG 0x1ae4 +#define mmLB1_LB_DEBUG 0x1ce4 +#define mmLB2_LB_DEBUG 0x1ee4 +#define mmLB3_LB_DEBUG 0x40e4 +#define mmLB4_LB_DEBUG 0x42e4 +#define mmLB5_LB_DEBUG 0x44e4 +#define mmLB_DEBUG2 0x1ae5 +#define mmLB0_LB_DEBUG2 0x1ae5 +#define mmLB1_LB_DEBUG2 0x1ce5 +#define mmLB2_LB_DEBUG2 0x1ee5 +#define mmLB3_LB_DEBUG2 0x40e5 +#define mmLB4_LB_DEBUG2 0x42e5 +#define mmLB5_LB_DEBUG2 0x44e5 +#define mmLB_DEBUG3 0x1ae6 +#define mmLB0_LB_DEBUG3 0x1ae6 +#define mmLB1_LB_DEBUG3 0x1ce6 +#define mmLB2_LB_DEBUG3 0x1ee6 +#define mmLB3_LB_DEBUG3 0x40e6 +#define mmLB4_LB_DEBUG3 0x42e6 +#define mmLB5_LB_DEBUG3 0x44e6 +#define mmLB_TEST_DEBUG_INDEX 0x1afe +#define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe +#define mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe +#define mmLB2_LB_TEST_DEBUG_INDEX 0x1efe +#define mmLB3_LB_TEST_DEBUG_INDEX 0x40fe +#define mmLB4_LB_TEST_DEBUG_INDEX 0x42fe +#define mmLB5_LB_TEST_DEBUG_INDEX 0x44fe +#define mmLB_TEST_DEBUG_DATA 0x1aff +#define mmLB0_LB_TEST_DEBUG_DATA 0x1aff +#define mmLB1_LB_TEST_DEBUG_DATA 0x1cff +#define mmLB2_LB_TEST_DEBUG_DATA 0x1eff +#define mmLB3_LB_TEST_DEBUG_DATA 0x40ff +#define mmLB4_LB_TEST_DEBUG_DATA 0x42ff +#define mmLB5_LB_TEST_DEBUG_DATA 0x44ff +#define mmLBV_DATA_FORMAT 0x463c +#define mmLBV_MEMORY_CTRL 0x463d +#define mmLBV_MEMORY_SIZE_STATUS 0x463e +#define mmLBV_DESKTOP_HEIGHT 0x463f +#define mmLBV_VLINE_START_END 0x4640 +#define mmLBV_VLINE2_START_END 0x4641 +#define mmLBV_V_COUNTER 0x4642 +#define mmLBV_SNAPSHOT_V_COUNTER 0x4643 +#define mmLBV_V_COUNTER_CHROMA 0x4644 +#define mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 +#define mmLBV_INTERRUPT_MASK 0x4646 +#define mmLBV_VLINE_STATUS 0x4647 +#define mmLBV_VLINE2_STATUS 0x4648 +#define mmLBV_VBLANK_STATUS 0x4649 +#define mmLBV_SYNC_RESET_SEL 0x464a +#define mmLBV_BLACK_KEYER_R_CR 0x464b +#define mmLBV_BLACK_KEYER_G_Y 0x464c +#define mmLBV_BLACK_KEYER_B_CB 0x464d +#define mmLBV_KEYER_COLOR_CTRL 0x464e +#define mmLBV_KEYER_COLOR_R_CR 0x464f +#define mmLBV_KEYER_COLOR_G_Y 0x4650 +#define mmLBV_KEYER_COLOR_B_CB 0x4651 +#define mmLBV_KEYER_COLOR_REP_R_CR 0x4652 +#define mmLBV_KEYER_COLOR_REP_G_Y 0x4653 +#define mmLBV_KEYER_COLOR_REP_B_CB 0x4654 +#define mmLBV_BUFFER_LEVEL_STATUS 0x4655 +#define mmLBV_BUFFER_URGENCY_CTRL 0x4656 +#define mmLBV_BUFFER_URGENCY_STATUS 0x4657 +#define mmLBV_BUFFER_STATUS 0x4658 +#define mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659 +#define mmLBV_DEBUG 0x465a +#define mmLBV_DEBUG2 0x465b +#define mmLBV_DEBUG3 0x465c +#define mmLBV_TEST_DEBUG_INDEX 0x4666 +#define mmLBV_TEST_DEBUG_DATA 0x4667 +#define mmMVP_CONTROL1 0x2ac +#define mmMVP_CONTROL2 0x2ad +#define mmMVP_FIFO_CONTROL 0x2ae +#define mmMVP_FIFO_STATUS 0x2af +#define mmMVP_SLAVE_STATUS 0x2b0 +#define mmMVP_INBAND_CNTL_CAP 0x2b1 +#define mmMVP_BLACK_KEYER 0x2b2 +#define mmMVP_CRC_CNTL 0x2b3 +#define mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4 +#define mmMVP_CRC_RESULT_RED 0x2b5 +#define mmMVP_CONTROL3 0x2b6 +#define mmMVP_RECEIVE_CNT_CNTL1 0x2b7 +#define mmMVP_RECEIVE_CNT_CNTL2 0x2b8 +#define mmMVP_DEBUG 0x2bb +#define mmMVP_TEST_DEBUG_INDEX 0x2b9 +#define mmMVP_TEST_DEBUG_DATA 0x2ba +#define ixMVP_DEBUG_12 0xc +#define ixMVP_DEBUG_13 0xd +#define ixMVP_DEBUG_14 0xe +#define ixMVP_DEBUG_15 0xf +#define ixMVP_DEBUG_16 0x10 +#define ixMVP_DEBUG_17 0x11 +#define mmSCL_COEF_RAM_SELECT 0x1b40 +#define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 +#define mmSCL1_SCL_COEF_RAM_SELECT 0x1d40 +#define mmSCL2_SCL_COEF_RAM_SELECT 0x1f40 +#define mmSCL3_SCL_COEF_RAM_SELECT 0x4140 +#define mmSCL4_SCL_COEF_RAM_SELECT 0x4340 +#define mmSCL5_SCL_COEF_RAM_SELECT 0x4540 +#define mmSCL_COEF_RAM_TAP_DATA 0x1b41 +#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 +#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41 +#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41 +#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141 +#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341 +#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 +#define mmSCL_MODE 0x1b42 +#define mmSCL0_SCL_MODE 0x1b42 +#define mmSCL1_SCL_MODE 0x1d42 +#define mmSCL2_SCL_MODE 0x1f42 +#define mmSCL3_SCL_MODE 0x4142 +#define mmSCL4_SCL_MODE 0x4342 +#define mmSCL5_SCL_MODE 0x4542 +#define mmSCL_TAP_CONTROL 0x1b43 +#define mmSCL0_SCL_TAP_CONTROL 0x1b43 +#define mmSCL1_SCL_TAP_CONTROL 0x1d43 +#define mmSCL2_SCL_TAP_CONTROL 0x1f43 +#define mmSCL3_SCL_TAP_CONTROL 0x4143 +#define mmSCL4_SCL_TAP_CONTROL 0x4343 +#define mmSCL5_SCL_TAP_CONTROL 0x4543 +#define mmSCL_CONTROL 0x1b44 +#define mmSCL0_SCL_CONTROL 0x1b44 +#define mmSCL1_SCL_CONTROL 0x1d44 +#define mmSCL2_SCL_CONTROL 0x1f44 +#define mmSCL3_SCL_CONTROL 0x4144 +#define mmSCL4_SCL_CONTROL 0x4344 +#define mmSCL5_SCL_CONTROL 0x4544 +#define mmSCL_BYPASS_CONTROL 0x1b45 +#define mmSCL0_SCL_BYPASS_CONTROL 0x1b45 +#define mmSCL1_SCL_BYPASS_CONTROL 0x1d45 +#define mmSCL2_SCL_BYPASS_CONTROL 0x1f45 +#define mmSCL3_SCL_BYPASS_CONTROL 0x4145 +#define mmSCL4_SCL_BYPASS_CONTROL 0x4345 +#define mmSCL5_SCL_BYPASS_CONTROL 0x4545 +#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46 +#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46 +#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146 +#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346 +#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546 +#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47 +#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47 +#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147 +#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347 +#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547 +#define mmSCL_HORZ_FILTER_CONTROL 0x1b48 +#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 +#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48 +#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48 +#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148 +#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348 +#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548 +#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49 +#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49 +#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 +#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349 +#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549 +#define mmSCL_HORZ_FILTER_INIT 0x1b4a +#define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a +#define mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a +#define mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a +#define mmSCL3_SCL_HORZ_FILTER_INIT 0x414a +#define mmSCL4_SCL_HORZ_FILTER_INIT 0x434a +#define mmSCL5_SCL_HORZ_FILTER_INIT 0x454a +#define mmSCL_VERT_FILTER_CONTROL 0x1b4b +#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b +#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b +#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b +#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b +#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b +#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b +#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c +#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c +#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c +#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c +#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c +#define mmSCL_VERT_FILTER_INIT 0x1b4d +#define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d +#define mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d +#define mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d +#define mmSCL3_SCL_VERT_FILTER_INIT 0x414d +#define mmSCL4_SCL_VERT_FILTER_INIT 0x434d +#define mmSCL5_SCL_VERT_FILTER_INIT 0x454d +#define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e +#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e +#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e +#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e +#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e +#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e +#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e +#define mmSCL_ROUND_OFFSET 0x1b4f +#define mmSCL0_SCL_ROUND_OFFSET 0x1b4f +#define mmSCL1_SCL_ROUND_OFFSET 0x1d4f +#define mmSCL2_SCL_ROUND_OFFSET 0x1f4f +#define mmSCL3_SCL_ROUND_OFFSET 0x414f +#define mmSCL4_SCL_ROUND_OFFSET 0x434f +#define mmSCL5_SCL_ROUND_OFFSET 0x454f +#define mmSCL_UPDATE 0x1b51 +#define mmSCL0_SCL_UPDATE 0x1b51 +#define mmSCL1_SCL_UPDATE 0x1d51 +#define mmSCL2_SCL_UPDATE 0x1f51 +#define mmSCL3_SCL_UPDATE 0x4151 +#define mmSCL4_SCL_UPDATE 0x4351 +#define mmSCL5_SCL_UPDATE 0x4551 +#define mmSCL_F_SHARP_CONTROL 0x1b53 +#define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 +#define mmSCL1_SCL_F_SHARP_CONTROL 0x1d53 +#define mmSCL2_SCL_F_SHARP_CONTROL 0x1f53 +#define mmSCL3_SCL_F_SHARP_CONTROL 0x4153 +#define mmSCL4_SCL_F_SHARP_CONTROL 0x4353 +#define mmSCL5_SCL_F_SHARP_CONTROL 0x4553 +#define mmSCL_ALU_CONTROL 0x1b54 +#define mmSCL0_SCL_ALU_CONTROL 0x1b54 +#define mmSCL1_SCL_ALU_CONTROL 0x1d54 +#define mmSCL2_SCL_ALU_CONTROL 0x1f54 +#define mmSCL3_SCL_ALU_CONTROL 0x4154 +#define mmSCL4_SCL_ALU_CONTROL 0x4354 +#define mmSCL5_SCL_ALU_CONTROL 0x4554 +#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55 +#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55 +#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 +#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355 +#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555 +#define mmVIEWPORT_START_SECONDARY 0x1b5b +#define mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b +#define mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b +#define mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b +#define mmSCL3_VIEWPORT_START_SECONDARY 0x415b +#define mmSCL4_VIEWPORT_START_SECONDARY 0x435b +#define mmSCL5_VIEWPORT_START_SECONDARY 0x455b +#define mmVIEWPORT_START 0x1b5c +#define mmSCL0_VIEWPORT_START 0x1b5c +#define mmSCL1_VIEWPORT_START 0x1d5c +#define mmSCL2_VIEWPORT_START 0x1f5c +#define mmSCL3_VIEWPORT_START 0x415c +#define mmSCL4_VIEWPORT_START 0x435c +#define mmSCL5_VIEWPORT_START 0x455c +#define mmVIEWPORT_SIZE 0x1b5d +#define mmSCL0_VIEWPORT_SIZE 0x1b5d +#define mmSCL1_VIEWPORT_SIZE 0x1d5d +#define mmSCL2_VIEWPORT_SIZE 0x1f5d +#define mmSCL3_VIEWPORT_SIZE 0x415d +#define mmSCL4_VIEWPORT_SIZE 0x435d +#define mmSCL5_VIEWPORT_SIZE 0x455d +#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e +#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e +#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e +#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e +#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e +#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f +#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f +#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f +#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f +#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f +#define mmSCL_MODE_CHANGE_DET1 0x1b60 +#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 +#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60 +#define mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60 +#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4160 +#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4360 +#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4560 +#define mmSCL_MODE_CHANGE_DET2 0x1b61 +#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 +#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61 +#define mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61 +#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4161 +#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4361 +#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4561 +#define mmSCL_MODE_CHANGE_DET3 0x1b62 +#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 +#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62 +#define mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62 +#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4162 +#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4362 +#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4562 +#define mmSCL_MODE_CHANGE_MASK 0x1b63 +#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 +#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63 +#define mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63 +#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4163 +#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4363 +#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4563 +#define mmSCL_DEBUG2 0x1b69 +#define mmSCL0_SCL_DEBUG2 0x1b69 +#define mmSCL1_SCL_DEBUG2 0x1d69 +#define mmSCL2_SCL_DEBUG2 0x1f69 +#define mmSCL3_SCL_DEBUG2 0x4169 +#define mmSCL4_SCL_DEBUG2 0x4369 +#define mmSCL5_SCL_DEBUG2 0x4569 +#define mmSCL_DEBUG 0x1b6a +#define mmSCL0_SCL_DEBUG 0x1b6a +#define mmSCL1_SCL_DEBUG 0x1d6a +#define mmSCL2_SCL_DEBUG 0x1f6a +#define mmSCL3_SCL_DEBUG 0x416a +#define mmSCL4_SCL_DEBUG 0x436a +#define mmSCL5_SCL_DEBUG 0x456a +#define mmSCL_TEST_DEBUG_INDEX 0x1b6b +#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b +#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b +#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b +#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b +#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b +#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b +#define mmSCL_TEST_DEBUG_DATA 0x1b6c +#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c +#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c +#define mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c +#define mmSCL3_SCL_TEST_DEBUG_DATA 0x416c +#define mmSCL4_SCL_TEST_DEBUG_DATA 0x436c +#define mmSCL5_SCL_TEST_DEBUG_DATA 0x456c +#define mmSCLV_COEF_RAM_SELECT 0x4670 +#define mmSCLV_COEF_RAM_TAP_DATA 0x4671 +#define mmSCLV_MODE 0x4672 +#define mmSCLV_TAP_CONTROL 0x4673 +#define mmSCLV_CONTROL 0x4674 +#define mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675 +#define mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676 +#define mmSCLV_HORZ_FILTER_CONTROL 0x4677 +#define mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678 +#define mmSCLV_HORZ_FILTER_INIT 0x4679 +#define mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a +#define mmSCLV_HORZ_FILTER_INIT_C 0x467b +#define mmSCLV_VERT_FILTER_CONTROL 0x467c +#define mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d +#define mmSCLV_VERT_FILTER_INIT 0x467e +#define mmSCLV_VERT_FILTER_INIT_BOT 0x467f +#define mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 +#define mmSCLV_VERT_FILTER_INIT_C 0x4681 +#define mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682 +#define mmSCLV_ROUND_OFFSET 0x4683 +#define mmSCLV_UPDATE 0x4684 +#define mmSCLV_ALU_CONTROL 0x4685 +#define mmSCLV_VIEWPORT_START 0x4686 +#define mmSCLV_VIEWPORT_START_SECONDARY 0x4687 +#define mmSCLV_VIEWPORT_SIZE 0x4688 +#define mmSCLV_VIEWPORT_START_C 0x4689 +#define mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a +#define mmSCLV_VIEWPORT_SIZE_C 0x468b +#define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c +#define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d +#define mmSCLV_MODE_CHANGE_DET1 0x468e +#define mmSCLV_MODE_CHANGE_DET2 0x468f +#define mmSCLV_MODE_CHANGE_DET3 0x4690 +#define mmSCLV_MODE_CHANGE_MASK 0x4691 +#define mmSCLV_DEBUG2 0x4692 +#define mmSCLV_DEBUG 0x4693 +#define mmSCLV_TEST_DEBUG_INDEX 0x4694 +#define mmSCLV_TEST_DEBUG_DATA 0x4695 +#define mmCOL_MAN_UPDATE 0x46a4 +#define mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5 +#define mmINPUT_CSC_C11_C12_A 0x46a6 +#define mmINPUT_CSC_C13_C14_A 0x46a7 +#define mmINPUT_CSC_C21_C22_A 0x46a8 +#define mmINPUT_CSC_C23_C24_A 0x46a9 +#define mmINPUT_CSC_C31_C32_A 0x46aa +#define mmINPUT_CSC_C33_C34_A 0x46ab +#define mmINPUT_CSC_C11_C12_B 0x46ac +#define mmINPUT_CSC_C13_C14_B 0x46ad +#define mmINPUT_CSC_C21_C22_B 0x46ae +#define mmINPUT_CSC_C23_C24_B 0x46af +#define mmINPUT_CSC_C31_C32_B 0x46b0 +#define mmINPUT_CSC_C33_C34_B 0x46b1 +#define mmPRESCALE_CONTROL 0x46b2 +#define mmPRESCALE_VALUES_R 0x46b3 +#define mmPRESCALE_VALUES_G 0x46b4 +#define mmPRESCALE_VALUES_B 0x46b5 +#define mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6 +#define mmOUTPUT_CSC_C11_C12_A 0x46b7 +#define mmOUTPUT_CSC_C13_C14_A 0x46b8 +#define mmOUTPUT_CSC_C21_C22_A 0x46b9 +#define mmOUTPUT_CSC_C23_C24_A 0x46ba +#define mmOUTPUT_CSC_C31_C32_A 0x46bb +#define mmOUTPUT_CSC_C33_C34_A 0x46bc +#define mmOUTPUT_CSC_C11_C12_B 0x46bd +#define mmOUTPUT_CSC_C13_C14_B 0x46be +#define mmOUTPUT_CSC_C21_C22_B 0x46bf +#define mmOUTPUT_CSC_C23_C24_B 0x46c0 +#define mmOUTPUT_CSC_C31_C32_B 0x46c1 +#define mmOUTPUT_CSC_C33_C34_B 0x46c2 +#define mmDENORM_CLAMP_CONTROL 0x46c3 +#define mmDENORM_CLAMP_RANGE_R_CR 0x46c4 +#define mmDENORM_CLAMP_RANGE_G_Y 0x46c5 +#define mmDENORM_CLAMP_RANGE_B_CB 0x46c6 +#define mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7 +#define mmGAMMA_CORR_CONTROL 0x46c8 +#define mmGAMMA_CORR_LUT_INDEX 0x46c9 +#define mmGAMMA_CORR_LUT_DATA 0x46ca +#define mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb +#define mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc +#define mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd +#define mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce +#define mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf +#define mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0 +#define mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1 +#define mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2 +#define mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3 +#define mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4 +#define mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5 +#define mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6 +#define mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7 +#define mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8 +#define mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 +#define mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da +#define mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db +#define mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc +#define mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd +#define mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de +#define mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df +#define mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0 +#define mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1 +#define mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2 +#define mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3 +#define mmCOL_MAN_TEST_DEBUG_INDEX 0x46e4 +#define mmCOL_MAN_TEST_DEBUG_DATA 0x46e5 +#define mmCOL_MAN_DEBUG_CONTROL 0x46e6 +#define mmUNP_GRPH_ENABLE 0x4600 +#define mmUNP_GRPH_CONTROL 0x4601 +#define mmUNP_GRPH_CONTROL_EXP 0x4603 +#define mmUNP_GRPH_SWAP_CNTL 0x4605 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 +#define mmUNP_GRPH_PITCH_L 0x4616 +#define mmUNP_GRPH_PITCH_C 0x4617 +#define mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618 +#define mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619 +#define mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a +#define mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b +#define mmUNP_GRPH_X_START_L 0x461c +#define mmUNP_GRPH_X_START_C 0x461d +#define mmUNP_GRPH_Y_START_L 0x461e +#define mmUNP_GRPH_Y_START_C 0x461f +#define mmUNP_GRPH_X_END_L 0x4620 +#define mmUNP_GRPH_X_END_C 0x4621 +#define mmUNP_GRPH_Y_END_L 0x4622 +#define mmUNP_GRPH_Y_END_C 0x4623 +#define mmUNP_GRPH_UPDATE 0x4624 +#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 +#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 +#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 +#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 +#define mmUNP_GRPH_DFQ_CONTROL 0x4629 +#define mmUNP_GRPH_DFQ_STATUS 0x462a +#define mmUNP_GRPH_INTERRUPT_STATUS 0x462b +#define mmUNP_GRPH_INTERRUPT_CONTROL 0x462c +#define mmUNP_GRPH_STEREOSYNC_FLIP 0x462e +#define mmUNP_GRPH_FLIP_RATE_CNTL 0x462f +#define mmUNP_CRC_CONTROL 0x4630 +#define mmUNP_CRC_MASK 0x4631 +#define mmUNP_CRC_CURRENT 0x4632 +#define mmUNP_CRC_LAST 0x4633 +#define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 +#define mmUNP_HW_ROTATION 0x4635 +#define mmUNP_DEBUG 0x4636 +#define mmUNP_DEBUG2 0x4637 +#define mmUNP_TEST_DEBUG_INDEX 0x4638 +#define mmUNP_TEST_DEBUG_DATA 0x4639 +#define mmGENMO_WT 0xf0 +#define mmGENMO_RD 0xf3 +#define mmGENENB 0xf0 +#define mmGENFC_WT 0xee +#define mmVGA0_GENFC_WT 0xee +#define mmVGA1_GENFC_WT 0xf6 +#define mmGENFC_RD 0xf2 +#define mmGENS0 0xf0 +#define mmGENS1 0xee +#define mmVGA0_GENS1 0xee +#define mmVGA1_GENS1 0xf6 +#define mmDAC_DATA 0xf2 +#define mmDAC_MASK 0xf1 +#define mmDAC_R_INDEX 0xf1 +#define mmDAC_W_INDEX 0xf2 +#define mmSEQ8_IDX 0xf1 +#define mmSEQ8_DATA 0xf1 +#define ixSEQ00 0x0 +#define ixSEQ01 0x1 +#define ixSEQ02 0x2 +#define ixSEQ03 0x3 +#define ixSEQ04 0x4 +#define mmCRTC8_IDX 0xed +#define mmVGA0_CRTC8_IDX 0xed +#define mmVGA1_CRTC8_IDX 0xf5 +#define mmCRTC8_DATA 0xed +#define mmVGA0_CRTC8_DATA 0xed +#define mmVGA1_CRTC8_DATA 0xf5 +#define ixCRT00 0x0 +#define ixCRT01 0x1 +#define ixCRT02 0x2 +#define ixCRT03 0x3 +#define ixCRT04 0x4 +#define ixCRT05 0x5 +#define ixCRT06 0x6 +#define ixCRT07 0x7 +#define ixCRT08 0x8 +#define ixCRT09 0x9 +#define ixCRT0A 0xa +#define ixCRT0B 0xb +#define ixCRT0C 0xc +#define ixCRT0D 0xd +#define ixCRT0E 0xe +#define ixCRT0F 0xf +#define ixCRT10 0x10 +#define ixCRT11 0x11 +#define ixCRT12 0x12 +#define ixCRT13 0x13 +#define ixCRT14 0x14 +#define ixCRT15 0x15 +#define ixCRT16 0x16 +#define ixCRT17 0x17 +#define ixCRT18 0x18 +#define ixCRT1E 0x1e +#define ixCRT1F 0x1f +#define ixCRT22 0x22 +#define mmGRPH8_IDX 0xf3 +#define mmGRPH8_DATA 0xf3 +#define ixGRA00 0x0 +#define ixGRA01 0x1 +#define ixGRA02 0x2 +#define ixGRA03 0x3 +#define ixGRA04 0x4 +#define ixGRA05 0x5 +#define ixGRA06 0x6 +#define ixGRA07 0x7 +#define ixGRA08 0x8 +#define mmATTRX 0xf0 +#define mmATTRDW 0xf0 +#define mmATTRDR 0xf0 +#define ixATTR00 0x0 +#define ixATTR01 0x1 +#define ixATTR02 0x2 +#define ixATTR03 0x3 +#define ixATTR04 0x4 +#define ixATTR05 0x5 +#define ixATTR06 0x6 +#define ixATTR07 0x7 +#define ixATTR08 0x8 +#define ixATTR09 0x9 +#define ixATTR0A 0xa +#define ixATTR0B 0xb +#define ixATTR0C 0xc +#define ixATTR0D 0xd +#define ixATTR0E 0xe +#define ixATTR0F 0xf +#define ixATTR10 0x10 +#define ixATTR11 0x11 +#define ixATTR12 0x12 +#define ixATTR13 0x13 +#define ixATTR14 0x14 +#define mmVGA_RENDER_CONTROL 0xc0 +#define mmVGA_SOURCE_SELECT 0xfc +#define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 +#define mmVGA_MODE_CONTROL 0xc2 +#define mmVGA_SURFACE_PITCH_SELECT 0xc3 +#define mmVGA_MEMORY_BASE_ADDRESS 0xc4 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 +#define mmVGA_HDP_CONTROL 0xca +#define mmVGA_CACHE_CONTROL 0xcb +#define mmD1VGA_CONTROL 0xcc +#define mmD2VGA_CONTROL 0xce +#define mmD3VGA_CONTROL 0xf8 +#define mmD4VGA_CONTROL 0xf9 +#define mmD5VGA_CONTROL 0xfa +#define mmD6VGA_CONTROL 0xfb +#define mmVGA_HW_DEBUG 0xcf +#define mmVGA_STATUS 0xd0 +#define mmVGA_INTERRUPT_CONTROL 0xd1 +#define mmVGA_STATUS_CLEAR 0xd2 +#define mmVGA_INTERRUPT_STATUS 0xd3 +#define mmVGA_MAIN_CONTROL 0xd4 +#define mmVGA_TEST_CONTROL 0xd5 +#define mmVGA_DEBUG_READBACK_INDEX 0xd6 +#define mmVGA_DEBUG_READBACK_DATA 0xd7 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x12 +#define mmVGA_MEM_READ_PAGE_ADDR 0x13 +#define mmVGA_TEST_DEBUG_INDEX 0xc5 +#define mmVGA_TEST_DEBUG_DATA 0xc7 +#define ixVGADCC_DBG_DCCIF_C 0x7e +#define mmBPHYC_DAC_MACRO_CNTL 0x48b9 +#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba +#define mmPLL_REF_DIV 0x1700 +#define mmBPHYC_PLL0_PLL_REF_DIV 0x1700 +#define mmBPHYC_PLL1_PLL_REF_DIV 0x172a +#define mmBPHYC_PLL2_PLL_REF_DIV 0x1754 +#define mmPLL_FB_DIV 0x1701 +#define mmBPHYC_PLL0_PLL_FB_DIV 0x1701 +#define mmBPHYC_PLL1_PLL_FB_DIV 0x172b +#define mmBPHYC_PLL2_PLL_FB_DIV 0x1755 +#define mmPLL_POST_DIV 0x1702 +#define mmBPHYC_PLL0_PLL_POST_DIV 0x1702 +#define mmBPHYC_PLL1_PLL_POST_DIV 0x172c +#define mmBPHYC_PLL2_PLL_POST_DIV 0x1756 +#define mmPLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d +#define mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757 +#define mmPLL_SS_CNTL 0x1704 +#define mmBPHYC_PLL0_PLL_SS_CNTL 0x1704 +#define mmBPHYC_PLL1_PLL_SS_CNTL 0x172e +#define mmBPHYC_PLL2_PLL_SS_CNTL 0x1758 +#define mmPLL_DS_CNTL 0x1705 +#define mmBPHYC_PLL0_PLL_DS_CNTL 0x1705 +#define mmBPHYC_PLL1_PLL_DS_CNTL 0x172f +#define mmBPHYC_PLL2_PLL_DS_CNTL 0x1759 +#define mmPLL_IDCLK_CNTL 0x1706 +#define mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706 +#define mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730 +#define mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a +#define mmPLL_CNTL 0x1707 +#define mmBPHYC_PLL0_PLL_CNTL 0x1707 +#define mmBPHYC_PLL1_PLL_CNTL 0x1731 +#define mmBPHYC_PLL2_PLL_CNTL 0x175b +#define mmPLL_ANALOG 0x1708 +#define mmBPHYC_PLL0_PLL_ANALOG 0x1708 +#define mmBPHYC_PLL1_PLL_ANALOG 0x1732 +#define mmBPHYC_PLL2_PLL_ANALOG 0x175c +#define mmPLL_VREG_CNTL 0x1709 +#define mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709 +#define mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733 +#define mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d +#define mmPLL_UNLOCK_DETECT_CNTL 0x170a +#define mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a +#define mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734 +#define mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e +#define mmPLL_DEBUG_CNTL 0x170b +#define mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b +#define mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735 +#define mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f +#define mmPLL_UPDATE_LOCK 0x170c +#define mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c +#define mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736 +#define mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760 +#define mmPLL_UPDATE_CNTL 0x170d +#define mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d +#define mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737 +#define mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761 +#define mmPLL_XOR_LOCK 0x1710 +#define mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710 +#define mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a +#define mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764 +#define mmPLL_ANALOG_CNTL 0x1711 +#define mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711 +#define mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b +#define mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765 +#define mmVGA25_PPLL_REF_DIV 0x1712 +#define mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712 +#define mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c +#define mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766 +#define mmVGA28_PPLL_REF_DIV 0x1713 +#define mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713 +#define mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d +#define mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767 +#define mmVGA41_PPLL_REF_DIV 0x1714 +#define mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714 +#define mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e +#define mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768 +#define mmVGA25_PPLL_FB_DIV 0x1715 +#define mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715 +#define mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f +#define mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769 +#define mmVGA28_PPLL_FB_DIV 0x1716 +#define mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716 +#define mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740 +#define mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a +#define mmVGA41_PPLL_FB_DIV 0x1717 +#define mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717 +#define mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741 +#define mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b +#define mmVGA25_PPLL_POST_DIV 0x1718 +#define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718 +#define mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742 +#define mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c +#define mmVGA28_PPLL_POST_DIV 0x1719 +#define mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719 +#define mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743 +#define mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d +#define mmVGA41_PPLL_POST_DIV 0x171a +#define mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a +#define mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744 +#define mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e +#define mmVGA25_PPLL_ANALOG 0x171b +#define mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b +#define mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745 +#define mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f +#define mmVGA28_PPLL_ANALOG 0x171c +#define mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c +#define mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746 +#define mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770 +#define mmVGA41_PPLL_ANALOG 0x171d +#define mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d +#define mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747 +#define mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771 +#define mmDISPPLL_BG_CNTL 0x171e +#define mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e +#define mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748 +#define mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772 +#define mmPPLL_DIV_UPDATE_DEBUG 0x171f +#define mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f +#define mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749 +#define mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773 +#define mmPPLL_STATUS_DEBUG 0x1720 +#define mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720 +#define mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a +#define mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774 +#define mmPPLL_DEBUG_MUX_CNTL 0x1721 +#define mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721 +#define mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b +#define mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775 +#define mmPPLL_SPARE0 0x1722 +#define mmBPHYC_PLL0_PPLL_SPARE0 0x1722 +#define mmBPHYC_PLL1_PPLL_SPARE0 0x174c +#define mmBPHYC_PLL2_PPLL_SPARE0 0x1776 +#define mmPPLL_SPARE1 0x1723 +#define mmBPHYC_PLL0_PPLL_SPARE1 0x1723 +#define mmBPHYC_PLL1_PPLL_SPARE1 0x174d +#define mmBPHYC_PLL2_PPLL_SPARE1 0x1777 +#define mmUNIPHY_TX_CONTROL1 0x48c0 +#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0 +#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0 +#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900 +#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920 +#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940 +#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960 +#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980 +#define mmUNIPHY_TX_CONTROL2 0x48c1 +#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1 +#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1 +#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901 +#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921 +#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941 +#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961 +#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981 +#define mmUNIPHY_TX_CONTROL3 0x48c2 +#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2 +#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2 +#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902 +#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922 +#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942 +#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962 +#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982 +#define mmUNIPHY_TX_CONTROL4 0x48c3 +#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3 +#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3 +#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903 +#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923 +#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943 +#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963 +#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983 +#define mmUNIPHY_POWER_CONTROL 0x48c4 +#define mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4 +#define mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4 +#define mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904 +#define mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924 +#define mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944 +#define mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964 +#define mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984 +#define mmUNIPHY_PLL_FBDIV 0x48c5 +#define mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5 +#define mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5 +#define mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905 +#define mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925 +#define mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945 +#define mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965 +#define mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985 +#define mmUNIPHY_PLL_CONTROL1 0x48c6 +#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6 +#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6 +#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906 +#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926 +#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946 +#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966 +#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986 +#define mmUNIPHY_PLL_CONTROL2 0x48c7 +#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7 +#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7 +#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907 +#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927 +#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947 +#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967 +#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987 +#define mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8 +#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8 +#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8 +#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908 +#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928 +#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948 +#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968 +#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988 +#define mmUNIPHY_PLL_SS_CNTL 0x48c9 +#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9 +#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9 +#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909 +#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929 +#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949 +#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969 +#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989 +#define mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca +#define mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca +#define mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea +#define mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a +#define mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a +#define mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a +#define mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a +#define mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a +#define mmUNIPHY_REG_TEST_OUTPUT 0x48cb +#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb +#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb +#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b +#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b +#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b +#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b +#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b +#define mmUNIPHY_ANG_BIST_CNTL 0x48cc +#define mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc +#define mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec +#define mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c +#define mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c +#define mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c +#define mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c +#define mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c +#define mmUNIPHY_REG_TEST_OUTPUT2 0x48cd +#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd +#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed +#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d +#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d +#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d +#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d +#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d +#define mmUNIPHY_TMDP_REG0 0x48ce +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e +#define mmUNIPHY_TMDP_REG1 0x48cf +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f +#define mmUNIPHY_TMDP_REG2 0x48d0 +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0 +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0 +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910 +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930 +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950 +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970 +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990 +#define mmUNIPHY_TMDP_REG3 0x48d1 +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1 +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1 +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911 +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931 +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951 +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971 +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991 +#define mmUNIPHY_TMDP_REG4 0x48d2 +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2 +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2 +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912 +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932 +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952 +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972 +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992 +#define mmUNIPHY_TMDP_REG5 0x48d3 +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3 +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3 +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913 +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933 +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953 +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973 +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993 +#define mmUNIPHY_TMDP_REG6 0x48d4 +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4 +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4 +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914 +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934 +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954 +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974 +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994 +#define mmUNIPHY_TPG_CONTROL 0x48d5 +#define mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5 +#define mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5 +#define mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915 +#define mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935 +#define mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955 +#define mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975 +#define mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995 +#define mmUNIPHY_TPG_SEED 0x48d6 +#define mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6 +#define mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6 +#define mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916 +#define mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936 +#define mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956 +#define mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976 +#define mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996 +#define mmUNIPHY_DEBUG 0x48d7 +#define mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7 +#define mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7 +#define mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917 +#define mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937 +#define mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957 +#define mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977 +#define mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997 +#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530 +#define mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 +#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531 +#define mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 +#define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 +#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 +#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32 +#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32 +#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132 +#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332 +#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532 +#define mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL 0x4732 +#define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 +#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 +#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33 +#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33 +#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133 +#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333 +#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533 +#define mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL 0x4733 +#define mmDPG_PIPE_DPM_CONTROL 0x1b34 +#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 +#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34 +#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34 +#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134 +#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334 +#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534 +#define mmDMIF_PG6_DPG_PIPE_DPM_CONTROL 0x4734 +#define mmDPG_PIPE_STUTTER_CONTROL 0x1b35 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535 +#define mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL 0x4735 +#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36 +#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36 +#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 +#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336 +#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536 +#define mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537 +#define mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define mmDPG_REPEATER_PROGRAM 0x1b3a +#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a +#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a +#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a +#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a +#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a +#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a +#define mmDMIF_PG6_DPG_REPEATER_PROGRAM 0x473a +#define mmDPG_HW_DEBUG_A 0x1b3b +#define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b +#define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b +#define mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b +#define mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b +#define mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b +#define mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b +#define mmDMIF_PG6_DPG_HW_DEBUG_A 0x473b +#define mmDPG_HW_DEBUG_B 0x1b3c +#define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c +#define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c +#define mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c +#define mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c +#define mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c +#define mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c +#define mmDMIF_PG6_DPG_HW_DEBUG_B 0x473c +#define mmDPG_HW_DEBUG_11 0x1b3d +#define mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d +#define mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d +#define mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d +#define mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d +#define mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d +#define mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d +#define mmDMIF_PG6_DPG_HW_DEBUG_11 0x473d +#define mmDPG_TEST_DEBUG_INDEX 0x1b38 +#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 +#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38 +#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38 +#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138 +#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338 +#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538 +#define mmDMIF_PG6_DPG_TEST_DEBUG_INDEX 0x4738 +#define mmDPG_TEST_DEBUG_DATA 0x1b39 +#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 +#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39 +#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39 +#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139 +#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339 +#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539 +#define mmDMIF_PG6_DPG_TEST_DEBUG_DATA 0x4739 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835 +#define mmAZALIA_F0_CODEC_DEBUG 0x1836 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a +#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b +#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c +#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d +#define mmGLOBAL_CAPABILITIES 0x0 +#define mmMINOR_VERSION 0x0 +#define mmMAJOR_VERSION 0x0 +#define mmOUTPUT_PAYLOAD_CAPABILITY 0x1 +#define mmINPUT_PAYLOAD_CAPABILITY 0x1 +#define mmGLOBAL_CONTROL 0x2 +#define mmWAKE_ENABLE 0x3 +#define mmSTATE_CHANGE_STATUS 0x3 +#define mmGLOBAL_STATUS 0x4 +#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define mmINTERRUPT_CONTROL 0x8 +#define mmINTERRUPT_STATUS 0x9 +#define mmWALL_CLOCK_COUNTER 0xc +#define mmSTREAM_SYNCHRONIZATION 0xe +#define mmCORB_LOWER_BASE_ADDRESS 0x10 +#define mmCORB_UPPER_BASE_ADDRESS 0x11 +#define mmCORB_WRITE_POINTER 0x12 +#define mmCORB_READ_POINTER 0x12 +#define mmCORB_CONTROL 0x13 +#define mmCORB_STATUS 0x13 +#define mmCORB_SIZE 0x13 +#define mmRIRB_LOWER_BASE_ADDRESS 0x14 +#define mmRIRB_UPPER_BASE_ADDRESS 0x15 +#define mmRIRB_WRITE_POINTER 0x16 +#define mmRESPONSE_INTERRUPT_COUNT 0x16 +#define mmRIRB_CONTROL 0x17 +#define mmRIRB_STATUS 0x17 +#define mmRIRB_SIZE 0x17 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 +#define mmIMMEDIATE_COMMAND_STATUS 0x1a +#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c +#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d +#define mmWALL_CLOCK_COUNTER_ALIAS 0x80c +#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 +#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 +#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 +#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 +#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 +#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 +#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 +#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 +#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAUDIO_DESCRIPTOR0 0x1 +#define ixAUDIO_DESCRIPTOR1 0x2 +#define ixAUDIO_DESCRIPTOR2 0x3 +#define ixAUDIO_DESCRIPTOR3 0x4 +#define ixAUDIO_DESCRIPTOR4 0x5 +#define ixAUDIO_DESCRIPTOR5 0x6 +#define ixAUDIO_DESCRIPTOR6 0x7 +#define ixAUDIO_DESCRIPTOR7 0x8 +#define ixAUDIO_DESCRIPTOR8 0x9 +#define ixAUDIO_DESCRIPTOR9 0xa +#define ixAUDIO_DESCRIPTOR10 0xb +#define ixAUDIO_DESCRIPTOR11 0xc +#define ixAUDIO_DESCRIPTOR12 0xd +#define ixAUDIO_DESCRIPTOR13 0xe +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 +#define ixSINK_DESCRIPTION0 0x5 +#define ixSINK_DESCRIPTION1 0x6 +#define ixSINK_DESCRIPTION2 0x7 +#define ixSINK_DESCRIPTION3 0x8 +#define ixSINK_DESCRIPTION4 0x9 +#define ixSINK_DESCRIPTION5 0xa +#define ixSINK_DESCRIPTION6 0xb +#define ixSINK_DESCRIPTION7 0xc +#define ixSINK_DESCRIPTION8 0xd +#define ixSINK_DESCRIPTION9 0xe +#define ixSINK_DESCRIPTION10 0xf +#define ixSINK_DESCRIPTION11 0x10 +#define ixSINK_DESCRIPTION12 0x11 +#define ixSINK_DESCRIPTION13 0x12 +#define ixSINK_DESCRIPTION14 0x13 +#define ixSINK_DESCRIPTION15 0x14 +#define ixSINK_DESCRIPTION16 0x15 +#define ixSINK_DESCRIPTION17 0x16 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4 +#define mmAZALIA_AUDIO_DTO 0x17e5 +#define mmAZALIA_AUDIO_DTO_CONTROL 0x17e6 +#define mmAZALIA_SCLK_CONTROL 0x17e7 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8 +#define mmAZALIA_DATA_DMA_CONTROL 0x17e9 +#define mmAZALIA_BDL_DMA_CONTROL 0x17ea +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb +#define mmAZALIA_CORB_DMA_CONTROL 0x17ec +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4 +#define mmAZALIA_GLOBAL_CAPABILITIES 0x17f5 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8 +#define mmAZALIA_CONTROLLER_DEBUG 0x17f9 +#define mmAZALIA_MEM_PWR_CTRL 0x1810 +#define mmAZALIA_MEM_PWR_STATUS 0x1811 +#define mmDCI_PG_DEBUG_CONFIG 0x1812 +#define mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb +#define mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc +#define mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd +#define mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe +#define mmAZALIA_INPUT_CRC0_RESULT 0x17ff +#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0 +#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 +#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 +#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x3 +#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x4 +#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 +#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x6 +#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x7 +#define mmAZALIA_INPUT_CRC1_CONTROL0 0x1800 +#define mmAZALIA_INPUT_CRC1_CONTROL1 0x1801 +#define mmAZALIA_INPUT_CRC1_CONTROL2 0x1802 +#define mmAZALIA_INPUT_CRC1_CONTROL3 0x1803 +#define mmAZALIA_INPUT_CRC1_RESULT 0x1804 +#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 +#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x1 +#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 +#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x3 +#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x4 +#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 +#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x6 +#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x7 +#define mmAZALIA_CRC0_CONTROL0 0x1805 +#define mmAZALIA_CRC0_CONTROL1 0x1806 +#define mmAZALIA_CRC0_CONTROL2 0x1807 +#define mmAZALIA_CRC0_CONTROL3 0x1808 +#define mmAZALIA_CRC0_RESULT 0x1809 +#define ixAZALIA_CRC0_CHANNEL0 0x0 +#define ixAZALIA_CRC0_CHANNEL1 0x1 +#define ixAZALIA_CRC0_CHANNEL2 0x2 +#define ixAZALIA_CRC0_CHANNEL3 0x3 +#define ixAZALIA_CRC0_CHANNEL4 0x4 +#define ixAZALIA_CRC0_CHANNEL5 0x5 +#define ixAZALIA_CRC0_CHANNEL6 0x6 +#define ixAZALIA_CRC0_CHANNEL7 0x7 +#define mmAZALIA_CRC1_CONTROL0 0x180a +#define mmAZALIA_CRC1_CONTROL1 0x180b +#define mmAZALIA_CRC1_CONTROL2 0x180c +#define mmAZALIA_CRC1_CONTROL3 0x180d +#define mmAZALIA_CRC1_RESULT 0x180e +#define ixAZALIA_CRC1_CHANNEL0 0x0 +#define ixAZALIA_CRC1_CHANNEL1 0x1 +#define ixAZALIA_CRC1_CHANNEL2 0x2 +#define ixAZALIA_CRC1_CHANNEL3 0x3 +#define ixAZALIA_CRC1_CHANNEL4 0x4 +#define ixAZALIA_CRC1_CHANNEL5 0x5 +#define ixAZALIA_CRC1_CHANNEL6 0x6 +#define ixAZALIA_CRC1_CHANNEL7 0x7 +#define mmAZ_TEST_DEBUG_INDEX 0x181f +#define mmAZ_TEST_DEBUG_DATA 0x1820 +#define mmAZALIA_STREAM_INDEX 0x1780 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780 +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0 +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2 +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4 +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6 +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8 +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce +#define mmAZALIA_STREAM_DATA 0x1781 +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b +#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d +#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f +#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3 +#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5 +#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7 +#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb +#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd +#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf +#define ixAZALIA_FIFO_SIZE_CONTROL 0x0 +#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 +#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 +#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 +#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 +#define ixAZALIA_STREAM_DEBUG 0x5 +#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4 +#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5 +#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 +#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a +#define ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b +#define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c +#define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d +#define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e +#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0 +#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define mmBLND_CONTROL 0x1b6d +#define mmBLND0_BLND_CONTROL 0x1b6d +#define mmBLND1_BLND_CONTROL 0x1d6d +#define mmBLND2_BLND_CONTROL 0x1f6d +#define mmBLND3_BLND_CONTROL 0x416d +#define mmBLND4_BLND_CONTROL 0x436d +#define mmBLND5_BLND_CONTROL 0x456d +#define mmBLND6_BLND_CONTROL 0x476d +#define mmSM_CONTROL2 0x1b6e +#define mmBLND0_SM_CONTROL2 0x1b6e +#define mmBLND1_SM_CONTROL2 0x1d6e +#define mmBLND2_SM_CONTROL2 0x1f6e +#define mmBLND3_SM_CONTROL2 0x416e +#define mmBLND4_SM_CONTROL2 0x436e +#define mmBLND5_SM_CONTROL2 0x456e +#define mmBLND6_SM_CONTROL2 0x476e +#define mmBLND_CONTROL2 0x1b6f +#define mmBLND0_BLND_CONTROL2 0x1b6f +#define mmBLND1_BLND_CONTROL2 0x1d6f +#define mmBLND2_BLND_CONTROL2 0x1f6f +#define mmBLND3_BLND_CONTROL2 0x416f +#define mmBLND4_BLND_CONTROL2 0x436f +#define mmBLND5_BLND_CONTROL2 0x456f +#define mmBLND6_BLND_CONTROL2 0x476f +#define mmBLND_UPDATE 0x1b70 +#define mmBLND0_BLND_UPDATE 0x1b70 +#define mmBLND1_BLND_UPDATE 0x1d70 +#define mmBLND2_BLND_UPDATE 0x1f70 +#define mmBLND3_BLND_UPDATE 0x4170 +#define mmBLND4_BLND_UPDATE 0x4370 +#define mmBLND5_BLND_UPDATE 0x4570 +#define mmBLND6_BLND_UPDATE 0x4770 +#define mmBLND_UNDERFLOW_INTERRUPT 0x1b71 +#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 +#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71 +#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71 +#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171 +#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371 +#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571 +#define mmBLND6_BLND_UNDERFLOW_INTERRUPT 0x4771 +#define mmBLND_V_UPDATE_LOCK 0x1b73 +#define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 +#define mmBLND1_BLND_V_UPDATE_LOCK 0x1d73 +#define mmBLND2_BLND_V_UPDATE_LOCK 0x1f73 +#define mmBLND3_BLND_V_UPDATE_LOCK 0x4173 +#define mmBLND4_BLND_V_UPDATE_LOCK 0x4373 +#define mmBLND5_BLND_V_UPDATE_LOCK 0x4573 +#define mmBLND6_BLND_V_UPDATE_LOCK 0x4773 +#define mmBLND_REG_UPDATE_STATUS 0x1b77 +#define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 +#define mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77 +#define mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77 +#define mmBLND3_BLND_REG_UPDATE_STATUS 0x4177 +#define mmBLND4_BLND_REG_UPDATE_STATUS 0x4377 +#define mmBLND5_BLND_REG_UPDATE_STATUS 0x4577 +#define mmBLND6_BLND_REG_UPDATE_STATUS 0x4777 +#define mmBLND_DEBUG 0x1b74 +#define mmBLND0_BLND_DEBUG 0x1b74 +#define mmBLND1_BLND_DEBUG 0x1d74 +#define mmBLND2_BLND_DEBUG 0x1f74 +#define mmBLND3_BLND_DEBUG 0x4174 +#define mmBLND4_BLND_DEBUG 0x4374 +#define mmBLND5_BLND_DEBUG 0x4574 +#define mmBLND6_BLND_DEBUG 0x4774 +#define mmBLND_TEST_DEBUG_INDEX 0x1b75 +#define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 +#define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75 +#define mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75 +#define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175 +#define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375 +#define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575 +#define mmBLND6_BLND_TEST_DEBUG_INDEX 0x4775 +#define mmBLND_TEST_DEBUG_DATA 0x1b76 +#define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 +#define mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76 +#define mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76 +#define mmBLND3_BLND_TEST_DEBUG_DATA 0x4176 +#define mmBLND4_BLND_TEST_DEBUG_DATA 0x4376 +#define mmBLND5_BLND_TEST_DEBUG_DATA 0x4576 +#define mmBLND6_BLND_TEST_DEBUG_DATA 0x4776 +#define mmWB_ENABLE 0x5e18 +#define mmWB_EC_CONFIG 0x5e19 +#define mmCNV_MODE 0x5e1a +#define mmCNV_WINDOW_START 0x5e1b +#define mmCNV_WINDOW_SIZE 0x5e1c +#define mmCNV_UPDATE 0x5e1d +#define mmCNV_SOURCE_SIZE 0x5e1e +#define mmCNV_CSC_CONTROL 0x5e1f +#define mmCNV_CSC_C11_C12 0x5e20 +#define mmCNV_CSC_C13_C14 0x5e21 +#define mmCNV_CSC_C21_C22 0x5e22 +#define mmCNV_CSC_C23_C24 0x5e23 +#define mmCNV_CSC_C31_C32 0x5e24 +#define mmCNV_CSC_C33_C34 0x5e25 +#define mmCNV_CSC_ROUND_OFFSET_R 0x5e26 +#define mmCNV_CSC_ROUND_OFFSET_G 0x5e27 +#define mmCNV_CSC_ROUND_OFFSET_B 0x5e28 +#define mmCNV_CSC_CLAMP_R 0x5e29 +#define mmCNV_CSC_CLAMP_G 0x5e2a +#define mmCNV_CSC_CLAMP_B 0x5e2b +#define mmCNV_TEST_CNTL 0x5e2c +#define mmCNV_TEST_CRC_RED 0x5e2d +#define mmCNV_TEST_CRC_GREEN 0x5e2e +#define mmCNV_TEST_CRC_BLUE 0x5e2f +#define mmWB_DEBUG_CTRL 0x5e30 +#define mmWB_DBG_MODE 0x5e31 +#define mmWB_HW_DEBUG 0x5e32 +#define mmCNV_INPUT_SELECT 0x5e33 +#define mmWB_SOFT_RESET 0x5e36 +#define mmCNV_TEST_DEBUG_INDEX 0x5e34 +#define mmCNV_TEST_DEBUG_DATA 0x5e35 +#define mmDCFE_CLOCK_CONTROL 0x1b00 +#define mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00 +#define mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00 +#define mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00 +#define mmDCFE3_DCFE_CLOCK_CONTROL 0x4100 +#define mmDCFE4_DCFE_CLOCK_CONTROL 0x4300 +#define mmDCFE5_DCFE_CLOCK_CONTROL 0x4500 +#define mmDCFE_SOFT_RESET 0x1b01 +#define mmDCFE0_DCFE_SOFT_RESET 0x1b01 +#define mmDCFE1_DCFE_SOFT_RESET 0x1d01 +#define mmDCFE2_DCFE_SOFT_RESET 0x1f01 +#define mmDCFE3_DCFE_SOFT_RESET 0x4101 +#define mmDCFE4_DCFE_SOFT_RESET 0x4301 +#define mmDCFE5_DCFE_SOFT_RESET 0x4501 +#define mmDCFE_DBG_CONFIG 0x1b02 +#define mmDCFE0_DCFE_DBG_CONFIG 0x1b02 +#define mmDCFE1_DCFE_DBG_CONFIG 0x1d02 +#define mmDCFE2_DCFE_DBG_CONFIG 0x1f02 +#define mmDCFE3_DCFE_DBG_CONFIG 0x4102 +#define mmDCFE4_DCFE_DBG_CONFIG 0x4302 +#define mmDCFE5_DCFE_DBG_CONFIG 0x4502 +#define mmDCFEV_CLOCK_CONTROL 0x46f4 +#define mmDCFEV_SOFT_RESET 0x46f5 +#define mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6 +#define mmDCFEV_DBG_CONFIG 0x46f7 +#define mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 +#define mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 +#define mmDC_HPD_INT_STATUS 0x1898 +#define mmHPD0_DC_HPD_INT_STATUS 0x1898 +#define mmHPD1_DC_HPD_INT_STATUS 0x18a0 +#define mmHPD2_DC_HPD_INT_STATUS 0x18a8 +#define mmHPD3_DC_HPD_INT_STATUS 0x18b0 +#define mmHPD4_DC_HPD_INT_STATUS 0x18b8 +#define mmHPD5_DC_HPD_INT_STATUS 0x18c0 +#define mmDC_HPD_INT_CONTROL 0x1899 +#define mmHPD0_DC_HPD_INT_CONTROL 0x1899 +#define mmHPD1_DC_HPD_INT_CONTROL 0x18a1 +#define mmHPD2_DC_HPD_INT_CONTROL 0x18a9 +#define mmHPD3_DC_HPD_INT_CONTROL 0x18b1 +#define mmHPD4_DC_HPD_INT_CONTROL 0x18b9 +#define mmHPD5_DC_HPD_INT_CONTROL 0x18c1 +#define mmDC_HPD_CONTROL 0x189a +#define mmHPD0_DC_HPD_CONTROL 0x189a +#define mmHPD1_DC_HPD_CONTROL 0x18a2 +#define mmHPD2_DC_HPD_CONTROL 0x18aa +#define mmHPD3_DC_HPD_CONTROL 0x18b2 +#define mmHPD4_DC_HPD_CONTROL 0x18ba +#define mmHPD5_DC_HPD_CONTROL 0x18c2 +#define mmDC_HPD_FAST_TRAIN_CNTL 0x189b +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3 +#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab +#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3 +#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb +#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3 +#define mmDC_HPD_TOGGLE_FILT_CNTL 0x189c +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4 +#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac +#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4 +#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc +#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4 +#define mmDCO_SCRATCH0 0x184e +#define mmDCO_SCRATCH1 0x184f +#define mmDCO_SCRATCH2 0x1850 +#define mmDCO_SCRATCH3 0x1851 +#define mmDCO_SCRATCH4 0x1852 +#define mmDCO_SCRATCH5 0x1853 +#define mmDCO_SCRATCH6 0x1854 +#define mmDCO_SCRATCH7 0x1855 +#define mmDCE_VCE_CONTROL 0x1856 +#define mmDISP_INTERRUPT_STATUS 0x1857 +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858 +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859 +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c +#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d +#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e +#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f +#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860 +#define mmDCO_MEM_PWR_STATUS 0x1861 +#define mmDCO_MEM_PWR_CTRL 0x1862 +#define mmDCO_MEM_PWR_CTRL2 0x1863 +#define mmDCO_CLK_CNTL 0x1864 +#define mmDCO_CLK_RAMP_CNTL 0x1865 +#define mmDPDBG_CNTL 0x1866 +#define mmDPDBG_INTERRUPT 0x1867 +#define mmDCO_POWER_MANAGEMENT_CNTL 0x1868 +#define mmDCO_SOFT_RESET 0x1871 +#define mmDIG_SOFT_RESET 0x1872 +#define mmDCO_STEREOSYNC_SEL 0x186e +#define mmDCO_TEST_DEBUG_INDEX 0x186f +#define mmDCO_TEST_DEBUG_DATA 0x1870 +#define mmDC_I2C_CONTROL 0x16d4 +#define mmDC_I2C_ARBITRATION 0x16d5 +#define mmDC_I2C_INTERRUPT_CONTROL 0x16d6 +#define mmDC_I2C_SW_STATUS 0x16d7 +#define mmDC_I2C_DDC1_HW_STATUS 0x16d8 +#define mmDC_I2C_DDC2_HW_STATUS 0x16d9 +#define mmDC_I2C_DDC3_HW_STATUS 0x16da +#define mmDC_I2C_DDC4_HW_STATUS 0x16db +#define mmDC_I2C_DDC5_HW_STATUS 0x16dc +#define mmDC_I2C_DDC6_HW_STATUS 0x16dd +#define mmDC_I2C_DDC1_SPEED 0x16de +#define mmDC_I2C_DDC1_SETUP 0x16df +#define mmDC_I2C_DDC2_SPEED 0x16e0 +#define mmDC_I2C_DDC2_SETUP 0x16e1 +#define mmDC_I2C_DDC3_SPEED 0x16e2 +#define mmDC_I2C_DDC3_SETUP 0x16e3 +#define mmDC_I2C_DDC4_SPEED 0x16e4 +#define mmDC_I2C_DDC4_SETUP 0x16e5 +#define mmDC_I2C_DDC5_SPEED 0x16e6 +#define mmDC_I2C_DDC5_SETUP 0x16e7 +#define mmDC_I2C_DDC6_SPEED 0x16e8 +#define mmDC_I2C_DDC6_SETUP 0x16e9 +#define mmDC_I2C_TRANSACTION0 0x16ea +#define mmDC_I2C_TRANSACTION1 0x16eb +#define mmDC_I2C_TRANSACTION2 0x16ec +#define mmDC_I2C_TRANSACTION3 0x16ed +#define mmDC_I2C_DATA 0x16ee +#define mmDC_I2C_DDCVGA_HW_STATUS 0x16ef +#define mmDC_I2C_DDCVGA_SPEED 0x16f0 +#define mmDC_I2C_DDCVGA_SETUP 0x16f1 +#define mmDC_I2C_EDID_DETECT_CTRL 0x16f2 +#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3 +#define mmGENERIC_I2C_CONTROL 0x16f4 +#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5 +#define mmGENERIC_I2C_STATUS 0x16f6 +#define mmGENERIC_I2C_SPEED 0x16f7 +#define mmGENERIC_I2C_SETUP 0x16f8 +#define mmGENERIC_I2C_TRANSACTION 0x16f9 +#define mmGENERIC_I2C_DATA 0x16fa +#define mmGENERIC_I2C_PIN_SELECTION 0x16fb +#define mmGENERIC_I2C_PIN_DEBUG 0x16fc +#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 +#define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 +#define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 +#define mmXDMA_INTERRUPT 0x3e3 +#define mmXDMA_CLOCK_GATING_CNTL 0x3e4 +#define mmXDMA_MEM_POWER_CNTL 0x3e6 +#define mmXDMA_IF_BIF_STATUS 0x3e7 +#define mmXDMA_PERF_MEAS_STATUS 0x3e8 +#define mmXDMA_IF_STATUS 0x3e9 +#define mmXDMA_TEST_DEBUG_INDEX 0x3ea +#define mmXDMA_TEST_DEBUG_DATA 0x3eb +#define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 +#define mmXDMA_PG_CONTROL 0x3f9 +#define mmXDMA_PG_WDATA 0x3fa +#define mmXDMA_PG_STATUS 0x3fb +#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc +#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd +#define mmXDMA_MSTR_CNTL 0x3ec +#define mmXDMA_MSTR_STATUS 0x3ed +#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 +#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 +#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 +#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 +#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 +#define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 +#define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 +#define mmXDMA_MSTR_PIPE_CNTL 0x400 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 +#define mmXDMA_MSTR_READ_COMMAND 0x401 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 +#define mmXDMA_MSTR_CHANNEL_DIM 0x402 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 +#define mmXDMA_MSTR_HEIGHT 0x403 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 +#define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 +#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 +#define mmXDMA_MSTR_CACHE 0x40a +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a +#define mmXDMA_MSTR_CHANNEL_START 0x40b +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b +#define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e +#define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f +#define mmXDMA_SLV_CNTL 0x460 +#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 +#define mmXDMA_SLV_SLS_PITCH 0x462 +#define mmXDMA_SLV_READ_URGENT_CNTL 0x463 +#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 +#define mmXDMA_SLV_WB_RATE_CNTL 0x465 +#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 +#define mmXDMA_SLV_READ_LATENCY_AVE 0x467 +#define mmXDMA_SLV_PCIE_NACK_STATUS 0x468 +#define mmXDMA_SLV_MEM_NACK_STATUS 0x469 +#define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a +#define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b +#define mmXDMA_SLV_FLIP_PENDING 0x46c +#define mmXDMA_SLV_CHANNEL_CNTL 0x470 +#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 +#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 +#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 +#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 +#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 +#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 +#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 +#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 +#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 +#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a +#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 +#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a +#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 +#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a + +#endif /* DCE_10_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h new file mode 100644 index 000000000000..061560e1be57 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h @@ -0,0 +1,1773 @@ +/* + * DCE_10_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_10_0_ENUM_H +#define DCE_10_0_ENUM_H + +typedef enum DCIO_DC_GENERICA_SEL { + DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0, + DCIO_GENERICA_SEL_STEREOSYNC = 0x1, + DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2, + DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3, + DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4, + DCIO_GENERICA_SEL_P1_PLLCLK = 0x5, + DCIO_GENERICA_SEL_P2_PLLCLK = 0x6, + DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7, + DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8, + DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9, + DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa, + DCIO_GENERICA_SEL_SYNCEN = 0xb, + DCIO_GENERICA_SEL_GENERICA_SCG = 0xc, + DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd, + DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe, + DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf, + DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10, + DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11, +} DCIO_DC_GENERICA_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { + DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0, + DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1, + DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2, + DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3, + DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4, + DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5, +} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { + DCIO_UNIPHYA_FBDIV_CLK = 0x0, + DCIO_UNIPHYB_FBDIV_CLK = 0x1, + DCIO_UNIPHYC_FBDIV_CLK = 0x2, + DCIO_UNIPHYD_FBDIV_CLK = 0x3, + DCIO_UNIPHYE_FBDIV_CLK = 0x4, + DCIO_UNIPHYF_FBDIV_CLK = 0x5, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { + DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0, + DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1, + DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2, + DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3, + DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4, + DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { + DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0, + DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1, + DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2, + DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3, + DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4, + DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; +typedef enum DCIO_DC_GENERICB_SEL { + DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0, + DCIO_GENERICB_SEL_STEREOSYNC = 0x1, + DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2, + DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3, + DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4, + DCIO_GENERICB_SEL_P1_PLLCLK = 0x5, + DCIO_GENERICB_SEL_P2_PLLCLK = 0x6, + DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7, + DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8, + DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9, + DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa, + DCIO_GENERICB_SEL_SYNCEN = 0xb, + DCIO_GENERICB_SEL_GENERICA_SCG = 0xc, + DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd, + DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe, + DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf, +} DCIO_DC_GENERICB_SEL; +typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL { + DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0, + DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6, + DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7, + DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc, + DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd, + DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe, + DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf, +} DCIO_DC_PAD_EXTERN_SIG_SEL; +typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS { + DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0, + DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1, + DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2, + DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3, +} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS; +typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL { + DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0, + DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1, + DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2, + DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3, +} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; +typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { + DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0, + DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1, + DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2, + DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3, +} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; +typedef enum DCIO_DC_GPIO_VIP_DEBUG { + DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0, + DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1, +} DCIO_DC_GPIO_VIP_DEBUG; +typedef enum DCIO_DC_GPIO_MACRO_DEBUG { + DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0, + DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1, + DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2, + DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3, +} DCIO_DC_GPIO_MACRO_DEBUG; +typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL { + DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0, + DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1, +} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL; +typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN { + DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0, + DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1, +} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN; +typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE { + DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0, + DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1, +} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; +typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION { + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7, +} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION; +typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { + DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0, + DCIO_UNIPHY_CHANNEL_INVERTED = 0x1, +} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; +typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0, + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1, + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2, + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3, +} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; +typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0, + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1, + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2, + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3, +} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; +typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN { + DCIO_VIP_MUX_EN_DVO = 0x0, + DCIO_VIP_MUX_EN_VIP = 0x1, +} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN; +typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN { + DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0, + DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, +} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN; +typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN { + DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0, + DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, +} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN { + DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0, + DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE { + DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0, + DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL { + DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0, + DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON { + DCIO_LVTMA_DIGON_OFF = 0x0, + DCIO_LVTMA_DIGON_ON = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL { + DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0, + DCIO_LVTMA_DIGON_POL_INVERT = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON { + DCIO_LVTMA_BLON_OFF = 0x0, + DCIO_LVTMA_BLON_ON = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL { + DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0, + DCIO_LVTMA_BLON_POL_INVERT = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL; +typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN { + DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0, + DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1, +} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN; +typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { + DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0, + DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1, +} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; +typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN { + DCIO_BL_PWM_DISABLE = 0x0, + DCIO_BL_PWM_ENABLE = 0x1, +} DCIO_BL_PWM_CNTL_BL_PWM_EN; +typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT { + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0, + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1, + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2, + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3, +} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; +typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { + DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0, + DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1, +} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; +typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN { + DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0, + DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1, +} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN; +typedef enum DCIO_BL_PWM_GRP1_REG_LOCK { + DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0, + DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1, +} DCIO_BL_PWM_GRP1_REG_LOCK; +typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START { + DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0, + DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1, +} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START; +typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5, +} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; +typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { + DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0, + DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1, +} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; +typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { + DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0, + DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1, +} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; +typedef enum DCIO_GSL_SEL { + DCIO_GSL_SEL_GROUP_0 = 0x0, + DCIO_GSL_SEL_GROUP_1 = 0x1, + DCIO_GSL_SEL_GROUP_2 = 0x2, +} DCIO_GSL_SEL; +typedef enum DCIO_GENLK_CLK_GSL_MASK { + DCIO_GENLK_CLK_GSL_MASK_NO = 0x0, + DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1, + DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2, +} DCIO_GENLK_CLK_GSL_MASK; +typedef enum DCIO_GENLK_VSYNC_GSL_MASK { + DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0, + DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1, + DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2, +} DCIO_GENLK_VSYNC_GSL_MASK; +typedef enum DCIO_SWAPLOCK_A_GSL_MASK { + DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0, + DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1, + DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2, +} DCIO_SWAPLOCK_A_GSL_MASK; +typedef enum DCIO_SWAPLOCK_B_GSL_MASK { + DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0, + DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1, + DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2, +} DCIO_SWAPLOCK_B_GSL_MASK; +typedef enum DCIO_GSL_VSYNC_SEL { + DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0, + DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1, + DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2, + DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3, + DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4, + DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5, +} DCIO_GSL_VSYNC_SEL; +typedef enum DCIO_GSL0_TIMING_SYNC_SEL { + DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0, + DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, + DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL0_TIMING_SYNC_SEL; +typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL { + DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL0_GLOBAL_UNLOCK_SEL; +typedef enum DCIO_GSL1_TIMING_SYNC_SEL { + DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0, + DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, + DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL1_TIMING_SYNC_SEL; +typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL { + DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL1_GLOBAL_UNLOCK_SEL; +typedef enum DCIO_GSL2_TIMING_SYNC_SEL { + DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0, + DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, + DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL2_TIMING_SYNC_SEL; +typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL { + DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL2_GLOBAL_UNLOCK_SEL; +typedef enum DCIO_DC_GPU_TIMER_START_POSITION { + DCIO_GPU_TIMER_START_0_END_27 = 0x0, + DCIO_GPU_TIMER_START_1_END_28 = 0x1, + DCIO_GPU_TIMER_START_2_END_29 = 0x2, + DCIO_GPU_TIMER_START_3_END_30 = 0x3, + DCIO_GPU_TIMER_START_4_END_31 = 0x4, + DCIO_GPU_TIMER_START_6_END_33 = 0x5, + DCIO_GPU_TIMER_START_8_END_35 = 0x6, + DCIO_GPU_TIMER_START_10_END_37 = 0x7, +} DCIO_DC_GPU_TIMER_START_POSITION; +typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { + DCIO_TEST_CLK_SEL_DISPCLK = 0x0, + DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1, + DCIO_TEST_CLK_SEL_SCLK = 0x2, +} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; +typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { + DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0, + DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1, +} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; +typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS { + DCIO_DISPCLK_R_DCIO_RAMP_DISABLE = 0x0, + DCIO_DISPCLK_R_DCIO_RAMP_ENABLE = 0x1, +} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS; +typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX { + DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0, + DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1, + DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2, + DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3, + DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4, + DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5, + DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6, + DCIO_EXT_VSYNC_MUX_GENERICB = 0x7, +} DCIO_DCO_DCFE_EXT_VSYNC_MUX; +typedef enum DCIO_DCO_EXT_VSYNC_MASK { + DCIO_EXT_VSYNC_MASK_NONE = 0x0, + DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1, + DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2, + DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3, + DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4, + DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5, + DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6, + DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7, +} DCIO_DCO_EXT_VSYNC_MASK; +typedef enum DCIO_DBG_OUT_PIN_SEL { + DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0, + DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1, +} DCIO_DBG_OUT_PIN_SEL; +typedef enum DCIO_DBG_OUT_12BIT_SEL { + DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0, + DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1, + DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2, + DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3, +} DCIO_DBG_OUT_12BIT_SEL; +typedef enum DCIO_DSYNC_SOFT_RESET { + DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0, + DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1, +} DCIO_DSYNC_SOFT_RESET; +typedef enum DCIO_DACA_SOFT_RESET { + DCIO_DACA_SOFT_RESET_DEASSERT = 0x0, + DCIO_DACA_SOFT_RESET_ASSERT = 0x1, +} DCIO_DACA_SOFT_RESET; +typedef enum DCIO_DCRXPHY_SOFT_RESET { + DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0, + DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1, +} DCIO_DCRXPHY_SOFT_RESET; +typedef enum DCIO_DPHY_LANE_SEL { + DCIO_DPHY_LANE_SEL_LANE0 = 0x0, + DCIO_DPHY_LANE_SEL_LANE1 = 0x1, + DCIO_DPHY_LANE_SEL_LANE2 = 0x2, + DCIO_DPHY_LANE_SEL_LANE3 = 0x3, +} DCIO_DPHY_LANE_SEL; +typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { + DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x6, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x7, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x8, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x9, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0xa, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0xb, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x12, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x13, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x14, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x15, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x16, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x17, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x1e, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x1f, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x20, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x21, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x22, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x23, +} DCIO_DC_GPU_TIMER_READ_SELECT; +typedef enum DCIO_IMPCAL_STEP_DELAY { + DCIO_IMPCAL_STEP_DELAY_1us = 0x0, + DCIO_IMPCAL_STEP_DELAY_2us = 0x1, + DCIO_IMPCAL_STEP_DELAY_3us = 0x2, + DCIO_IMPCAL_STEP_DELAY_4us = 0x3, + DCIO_IMPCAL_STEP_DELAY_5us = 0x4, + DCIO_IMPCAL_STEP_DELAY_6us = 0x5, + DCIO_IMPCAL_STEP_DELAY_7us = 0x6, + DCIO_IMPCAL_STEP_DELAY_8us = 0x7, + DCIO_IMPCAL_STEP_DELAY_9us = 0x8, + DCIO_IMPCAL_STEP_DELAY_10us = 0x9, + DCIO_IMPCAL_STEP_DELAY_11us = 0xa, + DCIO_IMPCAL_STEP_DELAY_12us = 0xb, + DCIO_IMPCAL_STEP_DELAY_13us = 0xc, + DCIO_IMPCAL_STEP_DELAY_14us = 0xd, + DCIO_IMPCAL_STEP_DELAY_15us = 0xe, + DCIO_IMPCAL_STEP_DELAY_16us = 0xf, +} DCIO_IMPCAL_STEP_DELAY; +typedef enum DCIO_UNIPHY_IMPCAL_SEL { + DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0, + DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1, +} DCIO_UNIPHY_IMPCAL_SEL; +typedef enum DCIOCHIP_HPD_SEL { + DCIOCHIP_HPD_SEL_ASYNC = 0x0, + DCIOCHIP_HPD_SEL_CLOCKED = 0x1, +} DCIOCHIP_HPD_SEL; +typedef enum DCIOCHIP_PAD_MODE { + DCIOCHIP_PAD_MODE_DDC = 0x0, + DCIOCHIP_PAD_MODE_DP = 0x1, +} DCIOCHIP_PAD_MODE; +typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE { + DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0, + DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1, +} DCIOCHIP_AUXSLAVE_PAD_MODE; +typedef enum DCIOCHIP_INVERT { + DCIOCHIP_POL_NON_INVERT = 0x0, + DCIOCHIP_POL_INVERT = 0x1, +} DCIOCHIP_INVERT; +typedef enum DCIOCHIP_PD_EN { + DCIOCHIP_PD_EN_NOTALLOW = 0x0, + DCIOCHIP_PD_EN_ALLOW = 0x1, +} DCIOCHIP_PD_EN; +typedef enum DCIOCHIP_GPIO_MASK_EN { + DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0, + DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1, +} DCIOCHIP_GPIO_MASK_EN; +typedef enum DCIOCHIP_MASK { + DCIOCHIP_MASK_DISABLE = 0x0, + DCIOCHIP_MASK_ENABLE = 0x1, +} DCIOCHIP_MASK; +typedef enum DCIOCHIP_GPIO_I2C_MASK { + DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0, + DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1, +} DCIOCHIP_GPIO_I2C_MASK; +typedef enum DCIOCHIP_GPIO_I2C_DRIVE { + DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0, + DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1, +} DCIOCHIP_GPIO_I2C_DRIVE; +typedef enum DCIOCHIP_GPIO_I2C_EN { + DCIOCHIP_GPIO_I2C_DISABLE = 0x0, + DCIOCHIP_GPIO_I2C_ENABLE = 0x1, +} DCIOCHIP_GPIO_I2C_EN; +typedef enum DCIOCHIP_MASK_4BIT { + DCIOCHIP_MASK_4BIT_DISABLE = 0x0, + DCIOCHIP_MASK_4BIT_ENABLE = 0xf, +} DCIOCHIP_MASK_4BIT; +typedef enum DCIOCHIP_ENABLE_4BIT { + DCIOCHIP_4BIT_DISABLE = 0x0, + DCIOCHIP_4BIT_ENABLE = 0xf, +} DCIOCHIP_ENABLE_4BIT; +typedef enum DCIOCHIP_MASK_5BIT { + DCIOCHIP_MASIK_5BIT_DISABLE = 0x0, + DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f, +} DCIOCHIP_MASK_5BIT; +typedef enum DCIOCHIP_ENABLE_5BIT { + DCIOCHIP_5BIT_DISABLE = 0x0, + DCIOCHIP_5BIT_ENABLE = 0x1f, +} DCIOCHIP_ENABLE_5BIT; +typedef enum DCIOCHIP_MASK_2BIT { + DCIOCHIP_MASK_2BIT_DISABLE = 0x0, + DCIOCHIP_MASK_2BIT_ENABLE = 0x3, +} DCIOCHIP_MASK_2BIT; +typedef enum DCIOCHIP_ENABLE_2BIT { + DCIOCHIP_2BIT_DISABLE = 0x0, + DCIOCHIP_2BIT_ENABLE = 0x3, +} DCIOCHIP_ENABLE_2BIT; +typedef enum DCIOCHIP_REF_27_SRC_SEL { + DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0, + DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1, + DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2, + DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3, +} DCIOCHIP_REF_27_SRC_SEL; +typedef enum DCIOCHIP_DVO_VREFPON { + DCIOCHIP_DVO_VREFPON_DISABLE = 0x0, + DCIOCHIP_DVO_VREFPON_ENABLE = 0x1, +} DCIOCHIP_DVO_VREFPON; +typedef enum DCIOCHIP_DVO_VREFSEL { + DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0, + DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1, +} DCIOCHIP_DVO_VREFSEL; +typedef enum COL_MAN_UPDATE_LOCK { + COL_MAN_UPDATE_UNLOCKED = 0x0, + COL_MAN_UPDATE_LOCKED = 0x1, +} COL_MAN_UPDATE_LOCK; +typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE { + COL_MAN_MULTIPLE_UPDATE = 0x0, + COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x1, +} COL_MAN_DISABLE_MULTIPLE_UPDATE; +typedef enum COL_MAN_INPUTCSC_MODE { + INPUTCSC_MODE_BYPASS = 0x0, + INPUTCSC_MODE_A = 0x1, + INPUTCSC_MODE_B = 0x2, + INPUTCSC_MODE_UNITY = 0x3, +} COL_MAN_INPUTCSC_MODE; +typedef enum COL_MAN_INPUTCSC_TYPE { + INPUTCSC_TYPE_12_0 = 0x0, + INPUTCSC_TYPE_10_2 = 0x1, + INPUTCSC_TYPE_8_4 = 0x2, +} COL_MAN_INPUTCSC_TYPE; +typedef enum COL_MAN_INPUTCSC_CONVERT { + INPUTCSC_ROUND = 0x0, + INPUTCSC_TRUNCATE = 0x1, +} COL_MAN_INPUTCSC_CONVERT; +typedef enum COL_MAN_PRESCALE_MODE { + PRESCALE_MODE_BYPASS = 0x0, + PRESCALE_MODE_PROGRAM = 0x1, + PRESCALE_MODE_UNITY = 0x2, +} COL_MAN_PRESCALE_MODE; +typedef enum COL_MAN_OUTPUT_CSC_MODE { + COL_MAN_OUTPUT_CSC_BYPASS = 0x0, + COL_MAN_OUTPUT_CSC_RGB = 0x1, + COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2, + COL_MAN_OUTPUT_CSC_YCrCb709 = 0x3, + COL_MAN_OUTPUT_CSC_A = 0x4, + COL_MAN_OUTPUT_CSC_B = 0x5, +} COL_MAN_OUTPUT_CSC_MODE; +typedef enum COL_MAN_DENORM_CLAMP_CONTROL { + DENORM_CLAMP_CONTROL_UNITY = 0x0, + DENORM_CLAMP_CONTROL_8 = 0x1, + DENORM_CLAMP_CONTROL_10 = 0x2, + DENORM_CLAMP_CONTROL_12 = 0x3, +} COL_MAN_DENORM_CLAMP_CONTROL; +typedef enum COL_MAN_GAMMA_CORR_CONTROL { + GAMMA_CORR_CONTROL_BYPASS = 0x0, + GAMMA_CORR_CONTROL_A = 0x1, + GAMMA_CORR_CONTROL_B = 0x2, +} COL_MAN_GAMMA_CORR_CONTROL; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_scf2 = 0x2, + DBG_CLIENT_BLKID_mcd5 = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_sx30 = 0x5, + DBG_CLIENT_BLKID_mcd2 = 0x6, + DBG_CLIENT_BLKID_bci1 = 0x7, + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, + DBG_CLIENT_BLKID_mcc0 = 0x9, + DBG_CLIENT_BLKID_uvdf_0 = 0xa, + DBG_CLIENT_BLKID_uvdf_1 = 0xb, + DBG_CLIENT_BLKID_uvdf_2 = 0xc, + DBG_CLIENT_BLKID_uvdi_0 = 0xd, + DBG_CLIENT_BLKID_bci0 = 0xe, + DBG_CLIENT_BLKID_vcec0_0 = 0xf, + DBG_CLIENT_BLKID_cb100 = 0x10, + DBG_CLIENT_BLKID_cb001 = 0x11, + DBG_CLIENT_BLKID_mcd4 = 0x12, + DBG_CLIENT_BLKID_tmonw00 = 0x13, + DBG_CLIENT_BLKID_cb101 = 0x14, + DBG_CLIENT_BLKID_sx10 = 0x15, + DBG_CLIENT_BLKID_cb301 = 0x16, + DBG_CLIENT_BLKID_tmonw01 = 0x17, + DBG_CLIENT_BLKID_vcea0_0 = 0x18, + DBG_CLIENT_BLKID_vcea0_1 = 0x19, + DBG_CLIENT_BLKID_vcea0_2 = 0x1a, + DBG_CLIENT_BLKID_vcea0_3 = 0x1b, + DBG_CLIENT_BLKID_scf1 = 0x1c, + DBG_CLIENT_BLKID_sx20 = 0x1d, + DBG_CLIENT_BLKID_spim1 = 0x1e, + DBG_CLIENT_BLKID_pa10 = 0x1f, + DBG_CLIENT_BLKID_pa00 = 0x20, + DBG_CLIENT_BLKID_gmcon = 0x21, + DBG_CLIENT_BLKID_mcb = 0x22, + DBG_CLIENT_BLKID_vgt0 = 0x23, + DBG_CLIENT_BLKID_pc0 = 0x24, + DBG_CLIENT_BLKID_bci2 = 0x25, + DBG_CLIENT_BLKID_uvdb_0 = 0x26, + DBG_CLIENT_BLKID_spim3 = 0x27, + DBG_CLIENT_BLKID_cpc_0 = 0x28, + DBG_CLIENT_BLKID_cpc_1 = 0x29, + DBG_CLIENT_BLKID_uvdm_0 = 0x2a, + DBG_CLIENT_BLKID_uvdm_1 = 0x2b, + DBG_CLIENT_BLKID_uvdm_2 = 0x2c, + DBG_CLIENT_BLKID_uvdm_3 = 0x2d, + DBG_CLIENT_BLKID_cb000 = 0x2e, + DBG_CLIENT_BLKID_spim0 = 0x2f, + DBG_CLIENT_BLKID_mcc2 = 0x30, + DBG_CLIENT_BLKID_ds0 = 0x31, + DBG_CLIENT_BLKID_srbm = 0x32, + DBG_CLIENT_BLKID_ih = 0x33, + DBG_CLIENT_BLKID_sem = 0x34, + DBG_CLIENT_BLKID_sdma_0 = 0x35, + DBG_CLIENT_BLKID_sdma_1 = 0x36, + DBG_CLIENT_BLKID_hdp = 0x37, + DBG_CLIENT_BLKID_acp_0 = 0x38, + DBG_CLIENT_BLKID_acp_1 = 0x39, + DBG_CLIENT_BLKID_cb200 = 0x3a, + DBG_CLIENT_BLKID_scf3 = 0x3b, + DBG_CLIENT_BLKID_vceb1_0 = 0x3c, + DBG_CLIENT_BLKID_vcea1_0 = 0x3d, + DBG_CLIENT_BLKID_vcea1_1 = 0x3e, + DBG_CLIENT_BLKID_vcea1_2 = 0x3f, + DBG_CLIENT_BLKID_vcea1_3 = 0x40, + DBG_CLIENT_BLKID_bci3 = 0x41, + DBG_CLIENT_BLKID_mcd0 = 0x42, + DBG_CLIENT_BLKID_pa11 = 0x43, + DBG_CLIENT_BLKID_pa01 = 0x44, + DBG_CLIENT_BLKID_cb201 = 0x45, + DBG_CLIENT_BLKID_spim2 = 0x46, + DBG_CLIENT_BLKID_vgt2 = 0x47, + DBG_CLIENT_BLKID_pc2 = 0x48, + DBG_CLIENT_BLKID_smu_0 = 0x49, + DBG_CLIENT_BLKID_smu_1 = 0x4a, + DBG_CLIENT_BLKID_smu_2 = 0x4b, + DBG_CLIENT_BLKID_cb1 = 0x4c, + DBG_CLIENT_BLKID_ia0 = 0x4d, + DBG_CLIENT_BLKID_wd = 0x4e, + DBG_CLIENT_BLKID_ia1 = 0x4f, + DBG_CLIENT_BLKID_vcec1_0 = 0x50, + DBG_CLIENT_BLKID_scf0 = 0x51, + DBG_CLIENT_BLKID_vgt1 = 0x52, + DBG_CLIENT_BLKID_pc1 = 0x53, + DBG_CLIENT_BLKID_cb0 = 0x54, + DBG_CLIENT_BLKID_gdc_one_0 = 0x55, + DBG_CLIENT_BLKID_gdc_one_1 = 0x56, + DBG_CLIENT_BLKID_gdc_one_2 = 0x57, + DBG_CLIENT_BLKID_gdc_one_3 = 0x58, + DBG_CLIENT_BLKID_gdc_one_4 = 0x59, + DBG_CLIENT_BLKID_gdc_one_5 = 0x5a, + DBG_CLIENT_BLKID_gdc_one_6 = 0x5b, + DBG_CLIENT_BLKID_gdc_one_7 = 0x5c, + DBG_CLIENT_BLKID_gdc_one_8 = 0x5d, + DBG_CLIENT_BLKID_gdc_one_9 = 0x5e, + DBG_CLIENT_BLKID_gdc_one_10 = 0x5f, + DBG_CLIENT_BLKID_gdc_one_11 = 0x60, + DBG_CLIENT_BLKID_gdc_one_12 = 0x61, + DBG_CLIENT_BLKID_gdc_one_13 = 0x62, + DBG_CLIENT_BLKID_gdc_one_14 = 0x63, + DBG_CLIENT_BLKID_gdc_one_15 = 0x64, + DBG_CLIENT_BLKID_gdc_one_16 = 0x65, + DBG_CLIENT_BLKID_gdc_one_17 = 0x66, + DBG_CLIENT_BLKID_gdc_one_18 = 0x67, + DBG_CLIENT_BLKID_gdc_one_19 = 0x68, + DBG_CLIENT_BLKID_gdc_one_20 = 0x69, + DBG_CLIENT_BLKID_gdc_one_21 = 0x6a, + DBG_CLIENT_BLKID_gdc_one_22 = 0x6b, + DBG_CLIENT_BLKID_gdc_one_23 = 0x6c, + DBG_CLIENT_BLKID_gdc_one_24 = 0x6d, + DBG_CLIENT_BLKID_gdc_one_25 = 0x6e, + DBG_CLIENT_BLKID_gdc_one_26 = 0x6f, + DBG_CLIENT_BLKID_gdc_one_27 = 0x70, + DBG_CLIENT_BLKID_gdc_one_28 = 0x71, + DBG_CLIENT_BLKID_gdc_one_29 = 0x72, + DBG_CLIENT_BLKID_gdc_one_30 = 0x73, + DBG_CLIENT_BLKID_gdc_one_31 = 0x74, + DBG_CLIENT_BLKID_gdc_one_32 = 0x75, + DBG_CLIENT_BLKID_gdc_one_33 = 0x76, + DBG_CLIENT_BLKID_gdc_one_34 = 0x77, + DBG_CLIENT_BLKID_gdc_one_35 = 0x78, + DBG_CLIENT_BLKID_vceb0_0 = 0x79, + DBG_CLIENT_BLKID_vgt3 = 0x7a, + DBG_CLIENT_BLKID_pc3 = 0x7b, + DBG_CLIENT_BLKID_mcd3 = 0x7c, + DBG_CLIENT_BLKID_uvdu_0 = 0x7d, + DBG_CLIENT_BLKID_uvdu_1 = 0x7e, + DBG_CLIENT_BLKID_uvdu_2 = 0x7f, + DBG_CLIENT_BLKID_uvdu_3 = 0x80, + DBG_CLIENT_BLKID_uvdu_4 = 0x81, + DBG_CLIENT_BLKID_uvdu_5 = 0x82, + DBG_CLIENT_BLKID_uvdu_6 = 0x83, + DBG_CLIENT_BLKID_cb300 = 0x84, + DBG_CLIENT_BLKID_mcd1 = 0x85, + DBG_CLIENT_BLKID_sx00 = 0x86, + DBG_CLIENT_BLKID_uvdc_0 = 0x87, + DBG_CLIENT_BLKID_uvdc_1 = 0x88, + DBG_CLIENT_BLKID_mcc3 = 0x89, + DBG_CLIENT_BLKID_cpg_0 = 0x8a, + DBG_CLIENT_BLKID_cpg_1 = 0x8b, + DBG_CLIENT_BLKID_gck = 0x8c, + DBG_CLIENT_BLKID_mcc1 = 0x8d, + DBG_CLIENT_BLKID_cpf_0 = 0x8e, + DBG_CLIENT_BLKID_cpf_1 = 0x8f, + DBG_CLIENT_BLKID_rlc = 0x90, + DBG_CLIENT_BLKID_grbm = 0x91, + DBG_CLIENT_BLKID_sammsp = 0x92, + DBG_CLIENT_BLKID_dci_pg = 0x93, + DBG_CLIENT_BLKID_dci_0 = 0x94, + DBG_CLIENT_BLKID_dccg0_0 = 0x95, + DBG_CLIENT_BLKID_dccg0_1 = 0x96, + DBG_CLIENT_BLKID_dcfe01_0 = 0x97, + DBG_CLIENT_BLKID_dcfe02_0 = 0x98, + DBG_CLIENT_BLKID_dcfe03_0 = 0x99, + DBG_CLIENT_BLKID_dcfe04_0 = 0x9a, + DBG_CLIENT_BLKID_dcfe05_0 = 0x9b, + DBG_CLIENT_BLKID_dcfe06_0 = 0x9c, + DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* DCE_10_0_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h new file mode 100644 index 000000000000..8a75eb9d732b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h @@ -0,0 +1,16647 @@ +/* + * DCE_10_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_10_0_SH_MASK_H +#define DCE_10_0_SH_MASK_H + +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1 +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0 +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1 +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0 +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1 +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0 +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0 +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1 +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0 +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1 +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0 +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1 +#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0 +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1 +#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0 +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1 +#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0 +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1 +#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0 +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1 +#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0 +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1 +#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0 +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1 +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0 +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1 +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4 +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2 +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000 +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0 +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1 +#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000 +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1 +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0 +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100 +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8 +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000 +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14 +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000 +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x18 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000 +#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x1f +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10 +#define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0xf +#define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x0 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x3 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x4 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x18 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x20 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0xc0 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x600 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x3000 +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x4000 +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x18000 +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000 +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0xc0000 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x100000 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x600000 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x800000 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x3000000 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x4000000 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000 +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000 +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d +#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x3 +#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0xc +#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2 +#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x30 +#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0xc0 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6 +#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x300 +#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8 +#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0xc00 +#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x3000 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0xc000 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x30000 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x40000 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12 +#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE_MASK 0x80000 +#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE__SHIFT 0x13 +#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS_MASK 0x100000 +#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS__SHIFT 0x14 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x600000 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x800000 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17 +#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3 +#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0xc +#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2 +#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x30 +#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0xc0 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x300 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8 +#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0xc00 +#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa +#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x3000 +#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc +#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0xc000 +#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe +#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x30000 +#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10 +#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000 +#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12 +#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x300000 +#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14 +#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0xc00000 +#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16 +#define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE_MASK 0x1000000 +#define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE__SHIFT 0x18 +#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff +#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0 +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000 +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0 +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000 +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11 +#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x3fff +#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0 +#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000 +#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10 +#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff +#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0 +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0 +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000 +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000 +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000 +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1 +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10 +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1 +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1 +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1 +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff +#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0 +#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1 +#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 +#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 +#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 +#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d +#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000 +#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e +#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000 +#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1 +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff +#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1 +#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0 +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2 +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1 +#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4 +#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2 +#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8 +#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3 +#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10 +#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4 +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20 +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000 +#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10 +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000 +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11 +#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000 +#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12 +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0 +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000 +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10 +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0 +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0 +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0 +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1 +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0 +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1 +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000 +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1 +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10 +#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14 +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3 +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x100 +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x8 +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000 +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000 +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14 +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000 +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1 +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1 +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10 +#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1 +#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0 +#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100 +#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000 +#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8 +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14 +#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1 +#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff +#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff +#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 +#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 +#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 +#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 +#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 +#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 +#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 +#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc +#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 +#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 +#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 +#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 +#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 +#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff +#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 +#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff +#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff +#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 +#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff +#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000 +#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x3fff +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3fff0000 +#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x3fff +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3fff0000 +#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000 +#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000 +#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000 +#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0 +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000 +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 +#define DAC_ENABLE__DAC_ENABLE_MASK 0x1 +#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1 +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3 +#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1 +#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0 +#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000 +#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x100 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14 +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14 +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x1000000 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18 +#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff +#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0 +#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1 +#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10 +#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000 +#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18 +#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1 +#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0 +#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100 +#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3 +#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3 +#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0 +#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000 +#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10 +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0 +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000 +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK 0xff +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK 0xffffffff +#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT 0x0 +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0xe00 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17 +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18 +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x4000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1a +#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x8000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x1b +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3 +#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xfc +#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x2 +#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00 +#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x1 +#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000 +#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff +#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define PERFMON_HI__PERFMON_HI_MASK 0xffff +#define PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000 +#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff +#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff +#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0 +#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x1 +#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0 +#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x2 +#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1 +#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0xf +#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x100 +#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8 +#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xffffffff +#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0 +#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x1 +#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0 +#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xffffffff +#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 +#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1 +#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0 +#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2 +#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1 +#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4 +#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2 +#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8 +#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3 +#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10 +#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4 +#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20 +#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5 +#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x40 +#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6 +#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000 +#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0 +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10 +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4 +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20 +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK 0x80 +#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT 0x7 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x100 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x10000 +#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x100000 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000 +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x800000 +#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x4000000 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x8000000 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000 +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000 +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000 +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK 0x1000 +#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT 0xc +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000 +#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0xf +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0xff0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0xf +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0xff0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1 +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30 +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4 +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1 +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30 +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30 +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x1 +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700 +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x1 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff +#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0 +#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff +#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff +#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0 +#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff +#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x2 +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000 +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x4000 +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x8000 +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x10000 +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x20000 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x40000 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x80000 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x100000 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x200000 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK 0x10 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT 0x4 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK 0x700 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT 0x8 +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x7 +#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x1f00 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8 +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x10000 +#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x20000 +#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11 +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x40000 +#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x7 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x1f00 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x10000 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x20000 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x40000 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x100000 +#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14 +#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x3000000 +#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18 +#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000 +#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x7 +#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x1f00 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8 +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x10000 +#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x20000 +#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11 +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x40000 +#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c +#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18 +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x1f +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x3e0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x5 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf8000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0xf +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x800000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x17 +#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK 0x1f000000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT 0x18 +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0 +#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3 +#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0 +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4 +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2 +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10 +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4 +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700 +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8 +#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800 +#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000 +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000 +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10 +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000 +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18 +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000 +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0xff +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0 +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0xff00 +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x700000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14 +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x7000000 +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18 +#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000 +#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0 +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0 +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000 +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10 +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0xf +#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0 +#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0xf0 +#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4 +#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0xf00 +#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8 +#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0xf000 +#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc +#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0xf0000 +#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10 +#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0xf00000 +#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14 +#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0xf000000 +#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18 +#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xf0000000 +#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x1 +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0 +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0xf0 +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff +#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11 +#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff +#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11 +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000 +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1 +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0 +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2 +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1 +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4 +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2 +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8 +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3 +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10 +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4 +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20 +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5 +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100 +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8 +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200 +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9 +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10 +#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3 +#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0 +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10 +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4 +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100 +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8 +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000 +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc +#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000 +#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10 +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000 +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00 +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0 +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0 +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0 +#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf +#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0 +#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0 +#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1 +#define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD_MASK 0x100 +#define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD__SHIFT 0x8 +#define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL_MASK 0x1e00 +#define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL__SHIFT 0x9 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0xfffff +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD_MASK 0xfff00000 +#define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD__SHIFT 0x14 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x7fff +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x10 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x20 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x40 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x80 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x100 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x200 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x400 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800 +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x1000 +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x2000 +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x4000 +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x7 +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 +#define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT_MASK 0x8 +#define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT__SHIFT 0x3 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x10 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x20 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x40 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x3 +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0 +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK 0xc +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT 0x2 +#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK 0x10 +#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT 0x4 +#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK 0x40 +#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT 0x6 +#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x100 +#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8 +#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x600 +#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9 +#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800 +#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb +#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x3000 +#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc +#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK 0xc000 +#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT 0xe +#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE_MASK 0x30000 +#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE__SHIFT 0x10 +#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE_MASK 0xc0000 +#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE__SHIFT 0x12 +#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 0x300000 +#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE__SHIFT 0x14 +#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x400000 +#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16 +#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000000 +#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18 +#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0xc000000 +#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a +#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000 +#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c +#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x3 +#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0 +#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0xc +#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2 +#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x10 +#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4 +#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x60 +#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5 +#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x180 +#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7 +#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x200 +#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9 +#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc00 +#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa +#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x3000 +#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc +#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x4000 +#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe +#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x18000 +#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf +#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000 +#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11 +#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x80000 +#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13 +#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x300000 +#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14 +#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0xc00000 +#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16 +#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x1000000 +#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18 +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0 +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20 +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5 +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40 +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6 +#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80 +#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7 +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100 +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200 +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9 +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800 +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000 +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd +#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x4000 +#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000 +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15 +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000 +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16 +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000 +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17 +#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000 +#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS_MASK 0x2000000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS__SHIFT 0x19 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS_MASK 0x4000000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS__SHIFT 0x1a +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000 +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x3 +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0 +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x4 +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK 0x8 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x3 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK 0x10 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT 0x4 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK 0x20 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT 0x5 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK 0x40 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT 0x6 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x80 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x100 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x600 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x1000 +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x2000 +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0xc000 +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x10000 +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK 0x60000 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT 0x11 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK 0x80000 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT 0x13 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x300000 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x400000 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x1800000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x2000000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19 +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0xc000000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000 +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000 +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x3 +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x4 +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x18 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x20 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x40 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x80 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x300 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x400 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x1800 +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x2000 +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x4000 +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x8000 +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x30000 +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10 +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x40000 +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x180000 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x200000 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x400000 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x800000 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x3000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x4000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x3 +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x4 +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x18 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x20 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x40 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x80 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x300 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x400 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x1800 +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x2000 +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x4000 +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x8000 +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf +#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x30000 +#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10 +#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0xc0000 +#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12 +#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x300000 +#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14 +#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x400000 +#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16 +#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x1800000 +#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x6000000 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b +#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000 +#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d +#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1 +#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 +#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2 +#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1 +#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4 +#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2 +#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8 +#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3 +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10 +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4 +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20 +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5 +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40 +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6 +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80 +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7 +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100 +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8 +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200 +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9 +#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x400 +#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa +#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x800 +#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000 +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc +#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x10000 +#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10 +#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x20000 +#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11 +#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x40000 +#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK 0x1 +#define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT 0x0 +#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK 0xf0 +#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT 0x4 +#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK 0xf00 +#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT 0x8 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define DC_GENERICA__GENERICA_EN_MASK 0x1 +#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 +#define DC_GENERICA__GENERICA_SEL_MASK 0xf80 +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICB__GENERICB_EN_MASK 0x1 +#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 +#define DC_GENERICB__GENERICB_SEL_MASK 0xf00 +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0 +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30 +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1 +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10 +#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000 +#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11 +#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000 +#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0 +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1 +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000 +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1 +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000 +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c +#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x78000 +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10 +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10 +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xf +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0 +#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0xf0 +#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4 +#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0xf00 +#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8 +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0xf000 +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400 +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000 +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000 +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0xe0000 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 +#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000 +#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000 +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x1f +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x20 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS_MASK 0x100 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS__SHIFT 0x8 +#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f +#define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK 0x1 +#define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT 0x0 +#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK 0x10 +#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT 0x4 +#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK 0x300 +#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT 0x8 +#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK 0xfff000 +#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT 0xc +#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x1 +#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x1 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x2 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x4 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x8 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x10 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x20 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x40 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x80 +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x100 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x200 +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x400 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x800 +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x1000 +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x2000 +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd +#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x10000 +#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10 +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x100000 +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14 +#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x1000000 +#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18 +#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x3 +#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 +#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0xc +#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2 +#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x30 +#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4 +#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0xc0 +#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK 0xc0 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK 0xc00 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK 0x1000 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT 0xc +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK 0x2000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK 0x8000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT 0xf +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK 0x10000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10 +#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11 +#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK 0x40000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK 0x100000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT 0x14 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK 0x200000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT 0x15 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16 +#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK 0x800000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT 0x17 +#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18 +#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK 0x2000000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT 0x19 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK 0x8000000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b +#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff +#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0 +#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff +#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0 +#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff +#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0 +#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff +#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0 +#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff +#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0 +#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff +#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0 +#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff +#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0 +#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff +#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0 +#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff +#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0 +#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff +#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0 +#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff +#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0 +#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff +#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0 +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0 +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff +#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0 +#define DCIO_DEBUG16__DCIO_DEBUG16_MASK 0xffffffff +#define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT 0x0 +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000 +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000 +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000 +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000 +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000 +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000 +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10 +#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000 +#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000 +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1 +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8 +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1 +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x2 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1 +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x2 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x4 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x8 +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3 +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x10 +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4 +#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x40 +#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 +#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x80 +#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x1000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x18 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x4000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x1a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0xf00 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0xf000 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x1 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x2 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x4 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x8 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x10 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x20 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x40 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x80 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7 +#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000 +#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x2000 +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000 +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe +#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000 +#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4 +#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0xf +#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0 +#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0xf0 +#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4 +#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0xf00 +#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8 +#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0xf000 +#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc +#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x70000 +#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10 +#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x700000 +#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14 +#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x7000000 +#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18 +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000 +#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000 +#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d +#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1 +#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0 +#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2 +#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1 +#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0 +#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4 +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 +#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 +#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 +#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 +#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc +#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 +#define GRPH_CONTROL__GRPH_Z_MASK 0x30 +#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4 +#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0 +#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6 +#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 +#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 +#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800 +#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb +#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000 +#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000 +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12 +#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 +#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 +#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 +#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 +#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000 +#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10 +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00 +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff +#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0 +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0 +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0 +#define GRPH_X_START__GRPH_X_START_MASK 0x3fff +#define GRPH_X_START__GRPH_X_START__SHIFT 0x0 +#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff +#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0 +#define GRPH_X_END__GRPH_X_END_MASK 0x7fff +#define GRPH_X_END__GRPH_X_END__SHIFT 0x0 +#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff +#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0 +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x3 +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0 +#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x30 +#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x4 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100 +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8 +#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 +#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 +#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 +#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0 +#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x2 +#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1 +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0 +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0 +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6 +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define OVL_ENABLE__OVL_ENABLE_MASK 0x1 +#define OVL_ENABLE__OVL_ENABLE__SHIFT 0x0 +#define OVL_ENABLE__OVLSCL_EN_MASK 0x100 +#define OVL_ENABLE__OVLSCL_EN__SHIFT 0x8 +#define OVL_CONTROL1__OVL_DEPTH_MASK 0x3 +#define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x0 +#define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0xc +#define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x2 +#define OVL_CONTROL1__OVL_Z_MASK 0x30 +#define OVL_CONTROL1__OVL_Z__SHIFT 0x4 +#define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0xc0 +#define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x6 +#define OVL_CONTROL1__OVL_FORMAT_MASK 0x700 +#define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x8 +#define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x1800 +#define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0xb +#define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0xe000 +#define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0xd +#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 +#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 +#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 +#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 +#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0xc0000 +#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x12 +#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0xf00000 +#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x14 +#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x1000000 +#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x18 +#define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000 +#define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x19 +#define OVL_CONTROL1__OVL_MICRO_TILE_MODE_MASK 0xc0000000 +#define OVL_CONTROL1__OVL_MICRO_TILE_MODE__SHIFT 0x1e +#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x1 +#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x0 +#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x3 +#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x0 +#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x30 +#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x4 +#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0xc0 +#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x6 +#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x300 +#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x8 +#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0xc00 +#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0xa +#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x1 +#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x0 +#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00 +#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x8 +#define OVL_PITCH__OVL_PITCH_MASK 0x7fff +#define OVL_PITCH__OVL_PITCH__SHIFT 0x0 +#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0xff +#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x3fff +#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x0 +#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x3fff +#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x0 +#define OVL_START__OVL_Y_START_MASK 0x3fff +#define OVL_START__OVL_Y_START__SHIFT 0x0 +#define OVL_START__OVL_X_START_MASK 0x3fff0000 +#define OVL_START__OVL_X_START__SHIFT 0x10 +#define OVL_END__OVL_Y_END_MASK 0x7fff +#define OVL_END__OVL_Y_END__SHIFT 0x0 +#define OVL_END__OVL_X_END_MASK 0x7fff0000 +#define OVL_END__OVL_X_END__SHIFT 0x10 +#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x1 +#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x0 +#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x2 +#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x1 +#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x10000 +#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x10 +#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 +#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x8 +#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x1 +#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x0 +#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x70 +#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x4 +#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x700 +#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 +#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0xf +#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x0 +#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 +#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x100 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x8 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x200 +#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x9 +#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff +#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x3ff +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x0 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0xffc00 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0xa +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x14 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000 +#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x1f +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x1 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x0 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x2 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x1 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x4 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x2 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x8 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x3 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x10 +#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x4 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0xffff +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x0 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000 +#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x10 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0xffff +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x0 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000 +#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x10 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0xffff +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x0 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000 +#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x10 +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3 +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0 +#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x30 +#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x4 +#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff +#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0 +#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000 +#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10 +#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff +#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0 +#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000 +#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10 +#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff +#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0 +#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000 +#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10 +#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff +#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0 +#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000 +#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10 +#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff +#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0 +#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000 +#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10 +#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff +#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0 +#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000 +#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x70 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x4 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10 +#define DENORM_CONTROL__DENORM_MODE_MASK 0x7 +#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0 +#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10 +#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4 +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10 +#define KEY_CONTROL__KEY_SELECT_MASK 0x1 +#define KEY_CONTROL__KEY_SELECT__SHIFT 0x0 +#define KEY_CONTROL__KEY_MODE_MASK 0x6 +#define KEY_CONTROL__KEY_MODE__SHIFT 0x1 +#define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000 +#define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x1c +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0 +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000 +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10 +#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff +#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0 +#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000 +#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10 +#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff +#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0 +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000 +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10 +#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff +#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0 +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000 +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10 +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3 +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0 +#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x30 +#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x4 +#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300 +#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8 +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000 +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3 +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0 +#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x30 +#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x4 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6 +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100 +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8 +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200 +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9 +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400 +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0xff +#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0 +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0xff00 +#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8 +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0xff0000 +#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 +#define CUR_CONTROL__CURSOR_EN_MASK 0x1 +#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0 +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10 +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4 +#define CUR_CONTROL__CURSOR_MODE_MASK 0x300 +#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000 +#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10 +#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000 +#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14 +#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000 +#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18 +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f +#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000 +#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff +#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000 +#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff +#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0 +#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00 +#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8 +#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000 +#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10 +#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff +#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0 +#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00 +#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8 +#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000 +#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10 +#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1 +#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0 +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2 +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1 +#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000 +#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10 +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000 +#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19 +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1 +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1 +#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0 +#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000 +#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10 +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1 +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0 +#define DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x10000 +#define DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10 +#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x20000 +#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11 +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0 +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0 +#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff +#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0 +#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000 +#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14 +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1 +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0 +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7 +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1 +#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf +#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6 +#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00 +#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe +#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000 +#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16 +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0 +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1 +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0 +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2 +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300 +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8 +#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff +#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0 +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0 +#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff +#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0 +#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff +#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3 +#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1 +#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0 +#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2 +#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1 +#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4 +#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2 +#define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x300 +#define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x8 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000 +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x60000 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x11 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x80000 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x13 +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000 +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18 +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000 +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0 +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x1f0 +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x1 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x0 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 +#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x1 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x0 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x300 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x8 +#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x10000 +#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x10 +#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x20000 +#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x11 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 +#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c +#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8 +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c +#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff +#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0 +#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7 +#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4 +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7 +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0 +#define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x70 +#define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x4 +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0 +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0 +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7 +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1 +#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0 +#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2 +#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e +#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7 +#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70 +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100 +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG_FE_CNTL__DIG_START_MASK 0x400 +#define DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000 +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000 +#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xc0000000 +#define DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2 +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x4 +#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x2 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x100 +#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x8 +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000 +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000 +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1 +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100 +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000 +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000 +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1 +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1 +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4 +#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8 +#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10 +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100 +#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200 +#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1 +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000 +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000 +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000 +#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1 +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000 +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 +#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1 +#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4 +#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10 +#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00 +#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000 +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7 +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40 +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80 +#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000 +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff +#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000 +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff +#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000 +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff +#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000 +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff +#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1 +#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2 +#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4 +#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38 +#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0 +#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00 +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000 +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000 +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000 +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000 +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0 +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000 +#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000 +#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000 +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000 +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10 +#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100 +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000 +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000 +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400 +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7 +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 +#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x1 +#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG_BE_CNTL__DIG_SWAP_MASK 0x2 +#define DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x4 +#define DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00 +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000 +#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000 +#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1 +#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100 +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1 +#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3 +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1 +#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11 +#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000 +#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18 +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000 +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19 +#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1 +#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100 +#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000 +#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000 +#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70 +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK_MASK 0x1 +#define TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN_MASK 0x2 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN__SHIFT 0x1 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN_MASK 0x4 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN__SHIFT 0x2 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN_MASK 0x8 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN__SHIFT 0x3 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN_MASK 0xff0 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN__SHIFT 0x4 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN_MASK 0x1000 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN__SHIFT 0xc +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN_MASK 0x2000 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN__SHIFT 0xd +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT_MASK 0x3fc000 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT__SHIFT 0xe +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE_MASK 0x400000 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE__SHIFT 0x16 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT_MASK 0x800000 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT__SHIFT 0x17 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT_MASK 0x1000000 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT__SHIFT 0x18 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT_MASK 0x2000000 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT__SHIFT 0x19 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT_MASK 0x4000000 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT__SHIFT 0x1a +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT_MASK 0x8000000 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT__SHIFT 0x1b +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT_MASK 0x10000000 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT__SHIFT 0x1c +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT_MASK 0x20000000 +#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT__SHIFT 0x1d +#define TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK_MASK 0x1 +#define TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN_MASK 0x2 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN__SHIFT 0x1 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN_MASK 0x4 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN__SHIFT 0x2 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN_MASK 0x8 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN__SHIFT 0x3 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN_MASK 0xff0 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN__SHIFT 0x4 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB_MASK 0x1ff000 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB__SHIFT 0xc +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX_MASK 0x200000 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX__SHIFT 0x15 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX_MASK 0xffc00000 +#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX__SHIFT 0x16 +#define TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK_MASK 0x1 +#define TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN_MASK 0x2 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN__SHIFT 0x1 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN_MASK 0xffc +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN__SHIFT 0x2 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN_MASK 0x1000 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN__SHIFT 0xc +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN_MASK 0x2000 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN__SHIFT 0xd +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN_MASK 0x4000 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN__SHIFT 0xe +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN_MASK 0x8000 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN__SHIFT 0xf +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN_MASK 0x100000 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN__SHIFT 0x14 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN_MASK 0x200000 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN__SHIFT 0x15 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT_MASK 0xffc00000 +#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT__SHIFT 0x16 +#define TMDS_DEBUG7__DBG_DIG_TMDS7_MASK 0xffffffff +#define TMDS_DEBUG7__DBG_DIG_TMDS7__SHIFT 0x0 +#define TMDS_DEBUG8__DBG_DIG_TMDS8_MASK 0xffffffff +#define TMDS_DEBUG8__DBG_DIG_TMDS8__SHIFT 0x0 +#define TMDS_DEBUG9__DBG_DIG_TMDS9_MASK 0xffffffff +#define TMDS_DEBUG9__DBG_DIG_TMDS9__SHIFT 0x0 +#define TMDS_DEBUG10__DBG_DIG_TMDS10_MASK 0xffffffff +#define TMDS_DEBUG10__DBG_DIG_TMDS10__SHIFT 0x0 +#define TMDS_DEBUG11__DBG_DIG_TMDS11_MASK 0xffffffff +#define TMDS_DEBUG11__DBG_DIG_TMDS11__SHIFT 0x0 +#define TMDS_DEBUG12__DBG_LVDS_DEBUG1_MASK 0xffffffff +#define TMDS_DEBUG12__DBG_LVDS_DEBUG1__SHIFT 0x0 +#define TMDS_DEBUG13__DBG_LVDS_DEBUG2_MASK 0xffffffff +#define TMDS_DEBUG13__DBG_LVDS_DEBUG2__SHIFT 0x0 +#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x1 +#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x0 +#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x10 +#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x4 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x100 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x8 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x200 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x9 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x400 +#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0xa +#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x7000 +#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0xc +#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x10000 +#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x10 +#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x20000 +#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x11 +#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x40000 +#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x12 +#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1 +#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2 +#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4 +#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8 +#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100 +#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK 0xff +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT 0x0 +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK 0xff +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK 0xffffffff +#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT 0x0 +#define DMCU_CTRL__RESET_UC_MASK 0x1 +#define DMCU_CTRL__RESET_UC__SHIFT 0x0 +#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2 +#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 +#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10 +#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffff0000 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10 +#define DMCU_STATUS__UC_IN_RESET_MASK 0x1 +#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 +#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2 +#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 +#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4 +#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 +#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0xff00 +#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x8 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x20 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x20 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800 +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800 +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000 +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000 +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000 +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000 +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000 +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK_MASK 0x10 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK_MASK 0x20 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x1000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0xc +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x2000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0xd +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x4000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0xe +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x8000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0xf +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x10000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x20000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x40000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x80000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x100000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x200000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x400000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x800000 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x20 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x40 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x80 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x200 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x400 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x800 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e +#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff +#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10 +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100 +#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000 +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7 +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100 +#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8 +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000 +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10 +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000 +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8 +#define DP_CONFIG__DP_UDI_LANES_MASK 0x3 +#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1 +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78 +#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3 +#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00 +#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000 +#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000 +#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1 +#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0 +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100 +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000 +#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP_VID_N__DP_VID_N_MASK 0xffffff +#define DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP_VID_M__DP_VID_M_MASK 0xffffff +#define DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000 +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000 +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1 +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000 +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10 +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000 +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000 +#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000 +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3 +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff +#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00 +#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000 +#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff +#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00 +#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000 +#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff +#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00 +#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1 +#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10 +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100 +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1 +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2 +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x3fff0 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x3fff +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3fff0000 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10 +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1 +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10 +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100 +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000 +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000 +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000 +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000 +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000 +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000 +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000 +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18 +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000 +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1 +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff +#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff +#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00 +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1 +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3 +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100 +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1 +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10 +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100 +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK 0x10000 +#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT 0x10 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0 +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK 0xff +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK 0xffffffff +#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT 0x0 +#define AUX_CONTROL__AUX_EN_MASK 0x1 +#define AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100 +#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000 +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000 +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000 +#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000 +#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000 +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000 +#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000 +#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define AUX_CONTROL__SPARE_0_MASK 0x40000000 +#define AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define AUX_CONTROL__SPARE_1_MASK 0x80000000 +#define AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1 +#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4 +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0 +#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000 +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3 +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000 +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000 +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000 +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000 +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000 +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000 +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1 +#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2 +#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100 +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200 +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800 +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000 +#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e +#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1 +#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2 +#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100 +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200 +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800 +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000 +#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000 +#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000 +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1 +#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00 +#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000 +#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000 +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00 +#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000 +#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000 +#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1 +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70 +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000 +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7 +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00 +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1 +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0 +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00 +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1 +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0 +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0 +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4 +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK 0xff +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT 0x0 +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK 0xffffffff +#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT 0x0 +#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xffffffff +#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xffffffff +#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xffffffff +#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xffffffff +#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xffffffff +#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xffffffff +#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xffffffff +#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xffffffff +#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xffffffff +#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xffffffff +#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK 0xffffffff +#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT 0x0 +#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK 0xffffffff +#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT 0x0 +#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK 0xffffffff +#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT 0x0 +#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK 0xffffffff +#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT 0x0 +#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK 0xffffffff +#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT 0x0 +#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK 0xffffffff +#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT 0x0 +#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK 0xffffffff +#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT 0x0 +#define DVO_ENABLE__DVO_ENABLE_MASK 0x1 +#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0 +#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30 +#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4 +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7 +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0 +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000 +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10 +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3 +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0 +#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100 +#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8 +#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1 +#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0 +#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2 +#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1 +#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30 +#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4 +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100 +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8 +#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000 +#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10 +#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000 +#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11 +#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000 +#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12 +#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000 +#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14 +#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000 +#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15 +#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000 +#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16 +#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000 +#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18 +#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000 +#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f +#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000 +#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10 +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0 +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK 0xff +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK 0xffffffff +#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT 0x0 +#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1 +#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0 +#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe +#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1 +#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000 +#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10 +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000 +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19 +#define FBC_CNTL__FBC_EN_MASK 0x80000000 +#define FBC_CNTL__FBC_EN__SHIFT 0x1f +#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff +#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0 +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0 +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0 +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80 +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7 +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00 +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8 +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14 +#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1 +#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0 +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100 +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8 +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200 +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9 +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400 +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800 +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb +#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000 +#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10 +#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff +#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0 +#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 +#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8 +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000 +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10 +#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000 +#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11 +#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000 +#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18 +#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff +#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0 +#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff +#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0 +#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff +#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0 +#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff +#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0 +#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff +#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0 +#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff +#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0 +#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff +#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0 +#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff +#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0 +#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff +#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0 +#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff +#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0 +#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff +#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0 +#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff +#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0 +#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff +#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0 +#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff +#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0 +#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff +#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0 +#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff +#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0 +#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff +#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0 +#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff +#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x3ff +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x3ff0000 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x3ff +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x3ff0000 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10 +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000 +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10 +#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3 +#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0 +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8 +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3 +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0 +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4 +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300 +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8 +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400 +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800 +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x3ff +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0 +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0 +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0 +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3 +#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0 +#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4 +#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2 +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8 +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3 +#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0 +#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4 +#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300 +#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8 +#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400 +#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa +#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800 +#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000 +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10 +#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000 +#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14 +#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000 +#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15 +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1f000000 +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18 +#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1 +#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1 +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10 +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0xf00 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x3000 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000 +#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000 +#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11 +#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000 +#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12 +#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000 +#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x1 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x0 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x700 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x8 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0xf000 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0xc +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x10000 +#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x10 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0xffff +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x0 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000 +#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x10 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0xffff +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x0 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000 +#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x10 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000 +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000 +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000 +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000 +#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000 +#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000 +#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0 +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1 +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000 +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1 +#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0 +#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2 +#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1 +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10 +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4 +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x100 +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8 +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000 +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10 +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3 +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0 +#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff +#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0 +#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff +#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0 +#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff +#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0 +#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff +#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0 +#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 +#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 +#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 +#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 +#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 +#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 +#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10 +#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4 +#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20 +#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5 +#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000 +#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc +#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 +#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 +#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 +#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f +#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff +#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 +#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 +#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 +#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 +#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff +#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 +#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff +#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 +#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff +#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0 +#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000 +#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10 +#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000 +#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f +#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff +#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0 +#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 +#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10 +#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 +#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f +#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff +#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff +#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 +#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 +#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 +#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 +#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 +#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 +#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 +#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 +#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 +#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10 +#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 +#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000 +#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc +#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 +#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 +#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 +#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 +#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 +#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 +#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 +#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 +#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 +#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 +#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 +#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 +#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 +#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 +#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 +#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 +#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 +#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 +#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 +#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 +#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 +#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 +#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 +#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 +#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 +#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 +#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa +#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 +#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 +#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 +#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3 +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3 +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000 +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f +#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff +#define LB_DEBUG__LB_DEBUG__SHIFT 0x0 +#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff +#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0 +#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff +#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 +#define LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 +#define LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 +#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 +#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 +#define LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 +#define LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 +#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10 +#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4 +#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20 +#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5 +#define LBV_DATA_FORMAT__DITHER_EN_MASK 0x40 +#define LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6 +#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x80 +#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7 +#define LBV_DATA_FORMAT__PREFETCH_MASK 0x1000 +#define LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc +#define LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 +#define LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 +#define LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 +#define LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f +#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff +#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 +#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 +#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 +#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 +#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff +#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 +#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff +#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 +#define LBV_VLINE_START_END__VLINE_START_MASK 0x3fff +#define LBV_VLINE_START_END__VLINE_START__SHIFT 0x0 +#define LBV_VLINE_START_END__VLINE_END_MASK 0x7fff0000 +#define LBV_VLINE_START_END__VLINE_END__SHIFT 0x10 +#define LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000 +#define LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f +#define LBV_VLINE2_START_END__VLINE2_START_MASK 0x3fff +#define LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0 +#define LBV_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 +#define LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10 +#define LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 +#define LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f +#define LBV_V_COUNTER__V_COUNTER_MASK 0x7fff +#define LBV_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff +#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 +#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x7fff +#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0 +#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x7fff +#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0 +#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 +#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 +#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 +#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 +#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 +#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 +#define LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 +#define LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 +#define LBV_VLINE_STATUS__VLINE_ACK_MASK 0x10 +#define LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 +#define LBV_VLINE_STATUS__VLINE_STAT_MASK 0x1000 +#define LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc +#define LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 +#define LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 +#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 +#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 +#define LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 +#define LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 +#define LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 +#define LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 +#define LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 +#define LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 +#define LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 +#define LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 +#define LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 +#define LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 +#define LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 +#define LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 +#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 +#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 +#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 +#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 +#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 +#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 +#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 +#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 +#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 +#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 +#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 +#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 +#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 +#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 +#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 +#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 +#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 +#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 +#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 +#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa +#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 +#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 +#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 +#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 +#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 +#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 +#define LBV_DEBUG__LB_DEBUG_MASK 0xffffffff +#define LBV_DEBUG__LB_DEBUG__SHIFT 0x0 +#define LBV_DEBUG2__LB_DEBUG2_MASK 0xffffffff +#define LBV_DEBUG2__LB_DEBUG2__SHIFT 0x0 +#define LBV_DEBUG3__LB_DEBUG3_MASK 0xffffffff +#define LBV_DEBUG3__LB_DEBUG3__SHIFT 0x0 +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff +#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MVP_CONTROL1__MVP_EN_MASK 0x1 +#define MVP_CONTROL1__MVP_EN__SHIFT 0x0 +#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70 +#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9 +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400 +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa +#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000 +#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000 +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10 +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000 +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14 +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000 +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18 +#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000 +#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000 +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000 +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4 +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100 +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8 +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000 +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc +#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000 +#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10 +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000 +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14 +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000 +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18 +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000 +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10 +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000 +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000 +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0 +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000 +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10 +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1 +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0 +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10 +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4 +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00 +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14 +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0 +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00 +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8 +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000 +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10 +#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000 +#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000 +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000 +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0 +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000 +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10 +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0 +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1 +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0 +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100 +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14 +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000 +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0 +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000 +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5 +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40 +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6 +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80 +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7 +#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00 +#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0 +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6 +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6 +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe +#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe +#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1 +#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000 +#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19 +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000 +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a +#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000 +#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b +#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7 +#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6 +#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200 +#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9 +#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400 +#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800 +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000 +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc +#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000 +#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12 +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000 +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13 +#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000 +#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2 +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8 +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define SCL_MODE__SCL_MODE_MASK 0x3 +#define SCL_MODE__SCL_MODE__SHIFT 0x0 +#define SCL_MODE__SCL_PSCL_EN_MASK 0x10 +#define SCL_MODE__SCL_PSCL_EN__SHIFT 0x4 +#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 +#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 +#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00 +#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8 +#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 +#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10 +#define SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4 +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3 +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1 +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0 +#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 +#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 +#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 +#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 +#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 +#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 +#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 +#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 +#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff +#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0 +#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000 +#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10 +#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff +#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 +#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 +#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 +#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000 +#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 +#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 +#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 +#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 +#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 +#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 +#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3 +#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff +#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x3 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x7f00 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x30000 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define SCLV_MODE__SCL_MODE_MASK 0x1 +#define SCLV_MODE__SCL_MODE__SHIFT 0x0 +#define SCLV_MODE__SCL_PSCL_EN_MASK 0x10 +#define SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4 +#define SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x300 +#define SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x70 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x700 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x7000 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc +#define SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 +#define SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10 +#define SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4 +#define SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x100 +#define SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8 +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 +#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff +#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x3ffffff +#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0xffffff +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0xf000000 +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff +#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x3ffffff +#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 +#define SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 +#define SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 +#define SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 +#define SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 +#define SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 +#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 +#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 +#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 +#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 +#define SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff +#define SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 +#define SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0 +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10 +#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x1fff +#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 +#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1fff0000 +#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 +#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x3fff +#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0 +#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10 +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x3fff +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0 +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10 +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x1fff +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0 +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1fff0000 +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10 +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 +#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 +#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 +#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff +#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 +#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 +#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 +#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 +#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 +#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 +#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 +#define SCLV_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 +#define SCLV_DEBUG2__SCL_DEBUG2__SHIFT 0x3 +#define SCLV_DEBUG__SCL_DEBUG_MASK 0xffffffff +#define SCLV_DEBUG__SCL_DEBUG__SHIFT 0x0 +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff +#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x1 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x2 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x10000 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10 +#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x3 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0xc +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x2 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x10 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x4 +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0xffff +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0 +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xffff0000 +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10 +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0xffff +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0 +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xffff0000 +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10 +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0xffff +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0 +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xffff0000 +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10 +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0xffff +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0 +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xffff0000 +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10 +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0xffff +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0 +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xffff0000 +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10 +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0xffff +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0 +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xffff0000 +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10 +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0xffff +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0 +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xffff0000 +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10 +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0xffff +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0 +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xffff0000 +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10 +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0xffff +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0 +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xffff0000 +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10 +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0xffff +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0 +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xffff0000 +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10 +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0xffff +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0 +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xffff0000 +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10 +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0xffff +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0 +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xffff0000 +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10 +#define PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x3 +#define PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0 +#define PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0xffff +#define PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0 +#define PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xffff0000 +#define PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10 +#define PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0xffff +#define PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0 +#define PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xffff0000 +#define PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10 +#define PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0xffff +#define PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0 +#define PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xffff0000 +#define PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10 +#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x7 +#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0xffff +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xffff0000 +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10 +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0xffff +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0 +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xffff0000 +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10 +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0xffff +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0 +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xffff0000 +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10 +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0xffff +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0 +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xffff0000 +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10 +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0xffff +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0 +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xffff0000 +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10 +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0xffff +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0 +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xffff0000 +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10 +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0xffff +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xffff0000 +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10 +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0xffff +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0 +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xffff0000 +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10 +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0xffff +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0 +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xffff0000 +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10 +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0xffff +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0 +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xffff0000 +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10 +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0xffff +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0 +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xffff0000 +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10 +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0xffff +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0 +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xffff0000 +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10 +#define DENORM_CLAMP_CONTROL__DENORM_FACTOR_MASK 0x3 +#define DENORM_CLAMP_CONTROL__DENORM_FACTOR__SHIFT 0x0 +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0xfff +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0 +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0xfff000 +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0xfff +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0 +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0xfff000 +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0xfff +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0 +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0xfff000 +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x3f00000 +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 +#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK 0x3 +#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT 0x0 +#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK 0x1ff +#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT 0x0 +#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK 0x7ffff +#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT 0x0 +#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK 0x7 +#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK 0x3ffff +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK 0xffff +#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK 0x3ffff +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK 0xffff +#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX_MASK 0xff +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX__SHIFT 0x0 +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA_MASK 0xffffffff +#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA__SHIFT 0x0 +#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE_MASK 0x1 +#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__SHIFT 0x0 +#define UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 +#define UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 +#define UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 +#define UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 +#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc +#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 +#define UNP_GRPH_CONTROL__GRPH_Z_MASK 0x30 +#define UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4 +#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0 +#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6 +#define UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 +#define UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 +#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800 +#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb +#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000 +#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd +#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 +#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 +#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 +#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 +#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000 +#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12 +#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 +#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 +#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 +#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 +#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000 +#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d +#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 +#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f +#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x7 +#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0 +#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 +#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 +#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 +#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 +#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 +#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 +#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 +#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L_MASK 0x1 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C_MASK 0x1 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L_MASK 0x1 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C_MASK 0x1 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L_MASK 0x1 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C_MASK 0x1 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L_MASK 0x1 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C_MASK 0x1 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x7fff +#define UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0 +#define UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x7fff +#define UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0 +#define UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x3fff +#define UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0 +#define UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x3fff +#define UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0 +#define UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x3fff +#define UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0 +#define UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x3fff +#define UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0 +#define UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x7fff +#define UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0 +#define UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x7fff +#define UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0 +#define UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x7fff +#define UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0 +#define UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x7fff +#define UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 +#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 +#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 +#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xffffff00 +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8 +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xffffff00 +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8 +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0xff +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0 +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0xff +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0 +#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1 +#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0 +#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70 +#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4 +#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700 +#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 +#define UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf +#define UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0 +#define UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 +#define UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 +#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100 +#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8 +#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200 +#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x30 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x100 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x3000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x40000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x80000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c +#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7 +#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0 +#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8 +#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3 +#define UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x1 +#define UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0 +#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x1c +#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2 +#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x300 +#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8 +#define UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xffffffff +#define UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0 +#define UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xffffffff +#define UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0 +#define UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xffffffff +#define UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0 +#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x1f0 +#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4 +#define UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x7 +#define UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0 +#define UNP_HW_ROTATION__PIXEL_DROP_MASK 0x10 +#define UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4 +#define UNP_HW_ROTATION__BUFFER_MODE_MASK 0x100 +#define UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8 +#define UNP_DEBUG__UNP_DEBUG_MASK 0xffffffff +#define UNP_DEBUG__UNP_DEBUG__SHIFT 0x0 +#define UNP_DEBUG2__UNP_DEBUG2_MASK 0xffffffff +#define UNP_DEBUG2__UNP_DEBUG2__SHIFT 0x0 +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK 0xff +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK 0xffffffff +#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT 0x0 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1 +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_WT__VGA_RAM_EN_MASK 0x2 +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_WT__VGA_CKSEL_MASK 0xc +#define GENMO_WT__VGA_CKSEL__SHIFT 0x2 +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20 +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1 +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_RD__VGA_RAM_EN_MASK 0x2 +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_RD__VGA_CKSEL_MASK 0xc +#define GENMO_RD__VGA_CKSEL__SHIFT 0x2 +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20 +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 +#define GENENB__BLK_IO_BASE_MASK 0xff +#define GENENB__BLK_IO_BASE__SHIFT 0x0 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x8 +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_RD__VSYNC_SEL_R_MASK 0x8 +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 +#define GENS0__SENSE_SWITCH_MASK 0x10 +#define GENS0__SENSE_SWITCH__SHIFT 0x4 +#define GENS0__CRT_INTR_MASK 0x80 +#define GENS0__CRT_INTR__SHIFT 0x7 +#define GENS1__NO_DISPLAY_MASK 0x1 +#define GENS1__NO_DISPLAY__SHIFT 0x0 +#define GENS1__VGA_VSTATUS_MASK 0x8 +#define GENS1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1__PIXEL_READ_BACK_MASK 0x30 +#define GENS1__PIXEL_READ_BACK__SHIFT 0x4 +#define DAC_DATA__DAC_DATA_MASK 0x3f +#define DAC_DATA__DAC_DATA__SHIFT 0x0 +#define DAC_MASK__DAC_MASK_MASK 0xff +#define DAC_MASK__DAC_MASK__SHIFT 0x0 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 +#define SEQ8_IDX__SEQ_IDX_MASK 0x7 +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 +#define SEQ8_DATA__SEQ_DATA_MASK 0xff +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 +#define SEQ00__SEQ_RST0B_MASK 0x1 +#define SEQ00__SEQ_RST0B__SHIFT 0x0 +#define SEQ00__SEQ_RST1B_MASK 0x2 +#define SEQ00__SEQ_RST1B__SHIFT 0x1 +#define SEQ01__SEQ_DOT8_MASK 0x1 +#define SEQ01__SEQ_DOT8__SHIFT 0x0 +#define SEQ01__SEQ_SHIFT2_MASK 0x4 +#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 +#define SEQ01__SEQ_PCLKBY2_MASK 0x8 +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 +#define SEQ01__SEQ_SHIFT4_MASK 0x10 +#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 +#define SEQ01__SEQ_MAXBW_MASK 0x20 +#define SEQ01__SEQ_MAXBW__SHIFT 0x5 +#define SEQ02__SEQ_MAP0_EN_MASK 0x1 +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 +#define SEQ02__SEQ_MAP1_EN_MASK 0x2 +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 +#define SEQ02__SEQ_MAP2_EN_MASK 0x4 +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 +#define SEQ02__SEQ_MAP3_EN_MASK 0x8 +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B1_MASK 0x1 +#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 +#define SEQ03__SEQ_FONT_B2_MASK 0x2 +#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 +#define SEQ03__SEQ_FONT_A1_MASK 0x4 +#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 +#define SEQ03__SEQ_FONT_A2_MASK 0x8 +#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B0_MASK 0x10 +#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 +#define SEQ03__SEQ_FONT_A0_MASK 0x20 +#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 +#define SEQ04__SEQ_256K_MASK 0x2 +#define SEQ04__SEQ_256K__SHIFT 0x1 +#define SEQ04__SEQ_ODDEVEN_MASK 0x4 +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 +#define SEQ04__SEQ_CHAIN_MASK 0x8 +#define SEQ04__SEQ_CHAIN__SHIFT 0x3 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_DATA__VCRTC_DATA_MASK 0xff +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 +#define CRT00__H_TOTAL_MASK 0xff +#define CRT00__H_TOTAL__SHIFT 0x0 +#define CRT01__H_DISP_END_MASK 0xff +#define CRT01__H_DISP_END__SHIFT 0x0 +#define CRT02__H_BLANK_START_MASK 0xff +#define CRT02__H_BLANK_START__SHIFT 0x0 +#define CRT03__H_BLANK_END_MASK 0x1f +#define CRT03__H_BLANK_END__SHIFT 0x0 +#define CRT03__H_DE_SKEW_MASK 0x60 +#define CRT03__H_DE_SKEW__SHIFT 0x5 +#define CRT03__CR10CR11_R_DIS_B_MASK 0x80 +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 +#define CRT04__H_SYNC_START_MASK 0xff +#define CRT04__H_SYNC_START__SHIFT 0x0 +#define CRT05__H_SYNC_END_MASK 0x1f +#define CRT05__H_SYNC_END__SHIFT 0x0 +#define CRT05__H_SYNC_SKEW_MASK 0x60 +#define CRT05__H_SYNC_SKEW__SHIFT 0x5 +#define CRT05__H_BLANK_END_B5_MASK 0x80 +#define CRT05__H_BLANK_END_B5__SHIFT 0x7 +#define CRT06__V_TOTAL_MASK 0xff +#define CRT06__V_TOTAL__SHIFT 0x0 +#define CRT07__V_TOTAL_B8_MASK 0x1 +#define CRT07__V_TOTAL_B8__SHIFT 0x0 +#define CRT07__V_DISP_END_B8_MASK 0x2 +#define CRT07__V_DISP_END_B8__SHIFT 0x1 +#define CRT07__V_SYNC_START_B8_MASK 0x4 +#define CRT07__V_SYNC_START_B8__SHIFT 0x2 +#define CRT07__V_BLANK_START_B8_MASK 0x8 +#define CRT07__V_BLANK_START_B8__SHIFT 0x3 +#define CRT07__LINE_CMP_B8_MASK 0x10 +#define CRT07__LINE_CMP_B8__SHIFT 0x4 +#define CRT07__V_TOTAL_B9_MASK 0x20 +#define CRT07__V_TOTAL_B9__SHIFT 0x5 +#define CRT07__V_DISP_END_B9_MASK 0x40 +#define CRT07__V_DISP_END_B9__SHIFT 0x6 +#define CRT07__V_SYNC_START_B9_MASK 0x80 +#define CRT07__V_SYNC_START_B9__SHIFT 0x7 +#define CRT08__ROW_SCAN_START_MASK 0x1f +#define CRT08__ROW_SCAN_START__SHIFT 0x0 +#define CRT08__BYTE_PAN_MASK 0x60 +#define CRT08__BYTE_PAN__SHIFT 0x5 +#define CRT09__MAX_ROW_SCAN_MASK 0x1f +#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 +#define CRT09__V_BLANK_START_B9_MASK 0x20 +#define CRT09__V_BLANK_START_B9__SHIFT 0x5 +#define CRT09__LINE_CMP_B9_MASK 0x40 +#define CRT09__LINE_CMP_B9__SHIFT 0x6 +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80 +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 +#define CRT0A__CURSOR_START_MASK 0x1f +#define CRT0A__CURSOR_START__SHIFT 0x0 +#define CRT0A__CURSOR_DISABLE_MASK 0x20 +#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 +#define CRT0B__CURSOR_END_MASK 0x1f +#define CRT0B__CURSOR_END__SHIFT 0x0 +#define CRT0B__CURSOR_SKEW_MASK 0x60 +#define CRT0B__CURSOR_SKEW__SHIFT 0x5 +#define CRT0C__DISP_START_MASK 0xff +#define CRT0C__DISP_START__SHIFT 0x0 +#define CRT0D__DISP_START_MASK 0xff +#define CRT0D__DISP_START__SHIFT 0x0 +#define CRT0E__CURSOR_LOC_HI_MASK 0xff +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 +#define CRT0F__CURSOR_LOC_LO_MASK 0xff +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 +#define CRT10__V_SYNC_START_MASK 0xff +#define CRT10__V_SYNC_START__SHIFT 0x0 +#define CRT11__V_SYNC_END_MASK 0xf +#define CRT11__V_SYNC_END__SHIFT 0x0 +#define CRT11__V_INTR_CLR_MASK 0x10 +#define CRT11__V_INTR_CLR__SHIFT 0x4 +#define CRT11__V_INTR_EN_MASK 0x20 +#define CRT11__V_INTR_EN__SHIFT 0x5 +#define CRT11__SEL5_REFRESH_CYC_MASK 0x40 +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 +#define CRT11__C0T7_WR_ONLY_MASK 0x80 +#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 +#define CRT12__V_DISP_END_MASK 0xff +#define CRT12__V_DISP_END__SHIFT 0x0 +#define CRT13__DISP_PITCH_MASK 0xff +#define CRT13__DISP_PITCH__SHIFT 0x0 +#define CRT14__UNDRLN_LOC_MASK 0x1f +#define CRT14__UNDRLN_LOC__SHIFT 0x0 +#define CRT14__ADDR_CNT_BY4_MASK 0x20 +#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 +#define CRT14__DOUBLE_WORD_MASK 0x40 +#define CRT14__DOUBLE_WORD__SHIFT 0x6 +#define CRT15__V_BLANK_START_MASK 0xff +#define CRT15__V_BLANK_START__SHIFT 0x0 +#define CRT16__V_BLANK_END_MASK 0xff +#define CRT16__V_BLANK_END__SHIFT 0x0 +#define CRT17__RA0_AS_A13B_MASK 0x1 +#define CRT17__RA0_AS_A13B__SHIFT 0x0 +#define CRT17__RA1_AS_A14B_MASK 0x2 +#define CRT17__RA1_AS_A14B__SHIFT 0x1 +#define CRT17__VCOUNT_BY2_MASK 0x4 +#define CRT17__VCOUNT_BY2__SHIFT 0x2 +#define CRT17__ADDR_CNT_BY2_MASK 0x8 +#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 +#define CRT17__WRAP_A15TOA0_MASK 0x20 +#define CRT17__WRAP_A15TOA0__SHIFT 0x5 +#define CRT17__BYTE_MODE_MASK 0x40 +#define CRT17__BYTE_MODE__SHIFT 0x6 +#define CRT17__CRTC_SYNC_EN_MASK 0x80 +#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 +#define CRT18__LINE_CMP_MASK 0xff +#define CRT18__LINE_CMP__SHIFT 0x0 +#define CRT1E__GRPH_DEC_RD1_MASK 0x2 +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 +#define CRT1F__GRPH_DEC_RD0_MASK 0xff +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 +#define CRT22__GRPH_LATCH_DATA_MASK 0xff +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 +#define GRPH8_IDX__GRPH_IDX_MASK 0xf +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 +#define GRPH8_DATA__GRPH_DATA_MASK 0xff +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET0_MASK 0x1 +#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET1_MASK 0x2 +#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 +#define GRA00__GRPH_SET_RESET2_MASK 0x4 +#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 +#define GRA00__GRPH_SET_RESET3_MASK 0x8 +#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1 +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2 +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4 +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8 +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 +#define GRA02__GRPH_CCOMP_MASK 0xf +#define GRA02__GRPH_CCOMP__SHIFT 0x0 +#define GRA03__GRPH_ROTATE_MASK 0x7 +#define GRA03__GRPH_ROTATE__SHIFT 0x0 +#define GRA03__GRPH_FN_SEL_MASK 0x18 +#define GRA03__GRPH_FN_SEL__SHIFT 0x3 +#define GRA04__GRPH_RMAP_MASK 0x3 +#define GRA04__GRPH_RMAP__SHIFT 0x0 +#define GRA05__GRPH_WRITE_MODE_MASK 0x3 +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 +#define GRA05__GRPH_READ1_MASK 0x8 +#define GRA05__GRPH_READ1__SHIFT 0x3 +#define GRA05__CGA_ODDEVEN_MASK 0x10 +#define GRA05__CGA_ODDEVEN__SHIFT 0x4 +#define GRA05__GRPH_OES_MASK 0x20 +#define GRA05__GRPH_OES__SHIFT 0x5 +#define GRA05__GRPH_PACK_MASK 0x40 +#define GRA05__GRPH_PACK__SHIFT 0x6 +#define GRA06__GRPH_GRAPHICS_MASK 0x1 +#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 +#define GRA06__GRPH_ODDEVEN_MASK 0x2 +#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 +#define GRA06__GRPH_ADRSEL_MASK 0xc +#define GRA06__GRPH_ADRSEL__SHIFT 0x2 +#define GRA07__GRPH_XCARE0_MASK 0x1 +#define GRA07__GRPH_XCARE0__SHIFT 0x0 +#define GRA07__GRPH_XCARE1_MASK 0x2 +#define GRA07__GRPH_XCARE1__SHIFT 0x1 +#define GRA07__GRPH_XCARE2_MASK 0x4 +#define GRA07__GRPH_XCARE2__SHIFT 0x2 +#define GRA07__GRPH_XCARE3_MASK 0x8 +#define GRA07__GRPH_XCARE3__SHIFT 0x3 +#define GRA08__GRPH_BMSK_MASK 0xff +#define GRA08__GRPH_BMSK__SHIFT 0x0 +#define ATTRX__ATTR_IDX_MASK 0x1f +#define ATTRX__ATTR_IDX__SHIFT 0x0 +#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20 +#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 +#define ATTRDW__ATTR_DATA_MASK 0xff +#define ATTRDW__ATTR_DATA__SHIFT 0x0 +#define ATTRDR__ATTR_DATA_MASK 0xff +#define ATTRDR__ATTR_DATA__SHIFT 0x0 +#define ATTR00__ATTR_PAL_MASK 0x3f +#define ATTR00__ATTR_PAL__SHIFT 0x0 +#define ATTR01__ATTR_PAL_MASK 0x3f +#define ATTR01__ATTR_PAL__SHIFT 0x0 +#define ATTR02__ATTR_PAL_MASK 0x3f +#define ATTR02__ATTR_PAL__SHIFT 0x0 +#define ATTR03__ATTR_PAL_MASK 0x3f +#define ATTR03__ATTR_PAL__SHIFT 0x0 +#define ATTR04__ATTR_PAL_MASK 0x3f +#define ATTR04__ATTR_PAL__SHIFT 0x0 +#define ATTR05__ATTR_PAL_MASK 0x3f +#define ATTR05__ATTR_PAL__SHIFT 0x0 +#define ATTR06__ATTR_PAL_MASK 0x3f +#define ATTR06__ATTR_PAL__SHIFT 0x0 +#define ATTR07__ATTR_PAL_MASK 0x3f +#define ATTR07__ATTR_PAL__SHIFT 0x0 +#define ATTR08__ATTR_PAL_MASK 0x3f +#define ATTR08__ATTR_PAL__SHIFT 0x0 +#define ATTR09__ATTR_PAL_MASK 0x3f +#define ATTR09__ATTR_PAL__SHIFT 0x0 +#define ATTR0A__ATTR_PAL_MASK 0x3f +#define ATTR0A__ATTR_PAL__SHIFT 0x0 +#define ATTR0B__ATTR_PAL_MASK 0x3f +#define ATTR0B__ATTR_PAL__SHIFT 0x0 +#define ATTR0C__ATTR_PAL_MASK 0x3f +#define ATTR0C__ATTR_PAL__SHIFT 0x0 +#define ATTR0D__ATTR_PAL_MASK 0x3f +#define ATTR0D__ATTR_PAL__SHIFT 0x0 +#define ATTR0E__ATTR_PAL_MASK 0x3f +#define ATTR0E__ATTR_PAL__SHIFT 0x0 +#define ATTR0F__ATTR_PAL_MASK 0x3f +#define ATTR0F__ATTR_PAL__SHIFT 0x0 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x1 +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 +#define ATTR10__ATTR_MONO_EN_MASK 0x2 +#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 +#define ATTR10__ATTR_LGRPH_EN_MASK 0x4 +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 +#define ATTR10__ATTR_BLINK_EN_MASK 0x8 +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 +#define ATTR10__ATTR_PANTOPONLY_MASK 0x20 +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 +#define ATTR10__ATTR_PCLKBY2_MASK 0x40 +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 +#define ATTR10__ATTR_CSEL_EN_MASK 0x80 +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 +#define ATTR11__ATTR_OVSC_MASK 0xff +#define ATTR11__ATTR_OVSC__SHIFT 0x0 +#define ATTR12__ATTR_MAP_EN_MASK 0xf +#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 +#define ATTR12__ATTR_VSMUX_MASK 0x30 +#define ATTR12__ATTR_VSMUX__SHIFT 0x4 +#define ATTR13__ATTR_PPAN_MASK 0xf +#define ATTR13__ATTR_PPAN__SHIFT 0x0 +#define ATTR14__ATTR_CSEL1_MASK 0x3 +#define ATTR14__ATTR_CSEL1__SHIFT 0x0 +#define ATTR14__ATTR_CSEL2_MASK 0xc +#define ATTR14__ATTR_CSEL2__SHIFT 0x2 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800 +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000 +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000 +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000 +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000 +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000 +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000 +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000 +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000 +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 +#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff +#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3 +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0xf000 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000 +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000 +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000 +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000 +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000 +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0 +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0 +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c +#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff +#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0 +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000 +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000 +#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10 +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7 +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10 +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8 +#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000 +#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc +#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000 +#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000 +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10 +#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff +#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0 +#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000 +#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10 +#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000 +#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12 +#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000 +#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3 +#define PLL_IDCLK_CNTL__PLL_IDCLK_EN_MASK 0x10 +#define PLL_IDCLK_CNTL__PLL_IDCLK_EN__SHIFT 0x4 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10 +#define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000 +#define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14 +#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000 +#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16 +#define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000 +#define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18 +#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR_MASK 0xc000000 +#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR__SHIFT 0x1a +#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR_MASK 0x30000000 +#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR__SHIFT 0x1c +#define PLL_CNTL__PLL_RESET_MASK 0x1 +#define PLL_CNTL__PLL_RESET__SHIFT 0x0 +#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2 +#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1 +#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4 +#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2 +#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8 +#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3 +#define PLL_CNTL__PLL_VCOREF_MASK 0x30 +#define PLL_CNTL__PLL_VCOREF__SHIFT 0x4 +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40 +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6 +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80 +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7 +#define PLL_CNTL__PLL_CALREF_MASK 0x300 +#define PLL_CNTL__PLL_CALREF__SHIFT 0x8 +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400 +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa +#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800 +#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000 +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd +#define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000 +#define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe +#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000 +#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10 +#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000 +#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13 +#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000 +#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14 +#define PLL_CNTL__PLL_LOCKED_MASK 0x200000 +#define PLL_CNTL__PLL_LOCKED__SHIFT 0x15 +#define PLL_CNTL__PLL_REFCLK_RECV_EN_MASK 0x400000 +#define PLL_CNTL__PLL_REFCLK_RECV_EN__SHIFT 0x16 +#define PLL_CNTL__PLL_REFCLK_RECV_SEL_MASK 0x800000 +#define PLL_CNTL__PLL_REFCLK_RECV_SEL__SHIFT 0x17 +#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000 +#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18 +#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000 +#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a +#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f +#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0 +#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60 +#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5 +#define PLL_ANALOG__PLL_CP_MASK 0xf00 +#define PLL_ANALOG__PLL_CP__SHIFT 0x8 +#define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000 +#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc +#define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000 +#define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15 +#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000 +#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18 +#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff +#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0 +#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000 +#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14 +#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000 +#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a +#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000 +#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8 +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1 +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0 +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0 +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4 +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00 +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1 +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0 +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1 +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0 +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100 +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8 +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000 +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10 +#define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1 +#define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0 +#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2 +#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1 +#define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00 +#define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8 +#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL_MASK 0xf0000 +#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL__SHIFT 0x10 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF_MASK 0x700000 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF__SHIFT 0x14 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB_MASK 0x3800000 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB__SHIFT 0x17 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS_MASK 0xc000000 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS__SHIFT 0x1a +#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN_MASK 0x10000000 +#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN__SHIFT 0x1c +#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1 +#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0 +#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e +#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1 +#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0 +#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5 +#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM_MASK 0x3e00 +#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM__SHIFT 0x9 +#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV_MASK 0x1c000 +#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV__SHIFT 0xe +#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL_MASK 0x20000 +#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL__SHIFT 0x11 +#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN_MASK 0x40000 +#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN__SHIFT 0x12 +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0 +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0 +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10 +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18 +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18 +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18 +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1 +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0 +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0 +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4 +#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED_MASK 0x1 +#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED__SHIFT 0x0 +#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED_MASK 0x2 +#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED__SHIFT 0x1 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING_MASK 0x4 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING__SHIFT 0x2 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE_MASK 0x18 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE__SHIFT 0x3 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE_MASK 0x20 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE__SHIFT 0x5 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ_MASK 0x40 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ__SHIFT 0x6 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK_MASK 0x80 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK__SHIFT 0x7 +#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS_MASK 0xffff +#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS__SHIFT 0x0 +#define PPLL_STATUS_DEBUG__PLL_UNLOCK_MASK 0x10000 +#define PPLL_STATUS_DEBUG__PLL_UNLOCK__SHIFT 0x10 +#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT_MASK 0x1e0000 +#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT__SHIFT 0x11 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB_MASK 0x1000000 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB__SHIFT 0x18 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S_MASK 0x2000000 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S__SHIFT 0x19 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V_MASK 0x4000000 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V__SHIFT 0x1a +#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK 0x1f +#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT 0x0 +#define PPLL_SPARE0__PLL_SPARE0_MASK 0xffffffff +#define PPLL_SPARE0__PLL_SPARE0__SHIFT 0x0 +#define PPLL_SPARE1__PLL_SPARE1_MASK 0xffffffff +#define PPLL_SPARE1__PLL_SPARE1__SHIFT 0x0 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0xf000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0xf0000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17 +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000 +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18 +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000 +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0 +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2 +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1 +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0xc +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0 +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19 +#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW_MASK 0x10000000 +#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW__SHIFT 0x1c +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a +#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff +#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0 +#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN_MASK 0x1 +#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN__SHIFT 0x0 +#define UNIPHY_TMDP_REG0__ICALRA_MODE_MASK 0x2 +#define UNIPHY_TMDP_REG0__ICALRA_MODE__SHIFT 0x1 +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG_MASK 0x7fc +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG__SHIFT 0x2 +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG_MASK 0xff800 +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG__SHIFT 0xb +#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL_MASK 0x100000 +#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL__SHIFT 0x14 +#define UNIPHY_TMDP_REG0__ITXA_PCALEN_MASK 0x200000 +#define UNIPHY_TMDP_REG0__ITXA_PCALEN__SHIFT 0x15 +#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN_MASK 0x400000 +#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN__SHIFT 0x16 +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN_MASK 0x800000 +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN__SHIFT 0x17 +#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL_MASK 0x3000000 +#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL__SHIFT 0x18 +#define UNIPHY_TMDP_REG0__ITXA_VSCALEN_MASK 0x4000000 +#define UNIPHY_TMDP_REG0__ITXA_VSCALEN__SHIFT 0x1a +#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL_MASK 0x78000000 +#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL__SHIFT 0x1b +#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN_MASK 0x80000000 +#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN__SHIFT 0x1f +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST_MASK 0x1f +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST__SHIFT 0x0 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ_MASK 0x1e0 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ__SHIFT 0x5 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ_MASK 0x1e00 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ__SHIFT 0x9 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ_MASK 0x1e000 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ__SHIFT 0xd +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN_MASK 0x20000 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN__SHIFT 0x11 +#define UNIPHY_TMDP_REG1__ITXA_IOCNTL_MASK 0xffc0000 +#define UNIPHY_TMDP_REG1__ITXA_IOCNTL__SHIFT 0x12 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL_MASK 0x10000000 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL__SHIFT 0x1c +#define UNIPHY_TMDP_REG1__ITX_EDPSEL_MASK 0xe0000000 +#define UNIPHY_TMDP_REG1__ITX_EDPSEL__SHIFT 0x1d +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN_MASK 0x1 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN__SHIFT 0x0 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN_MASK 0x2 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN__SHIFT 0x1 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_MASK 0x3c +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET__SHIFT 0x2 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN_MASK 0x40 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN__SHIFT 0x6 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_MASK 0x3f80 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE__SHIFT 0x7 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET_MASK 0x4000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET__SHIFT 0xe +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN_MASK 0x10000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN__SHIFT 0x10 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN_MASK 0x20000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN__SHIFT 0x11 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_MASK 0x3c0000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET__SHIFT 0x12 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN_MASK 0x400000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN__SHIFT 0x16 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_MASK 0x3f800000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE__SHIFT 0x17 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET_MASK 0x40000000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET__SHIFT 0x1e +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN_MASK 0x1 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN__SHIFT 0x0 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN_MASK 0x2 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN__SHIFT 0x1 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_MASK 0x3c +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET__SHIFT 0x2 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN_MASK 0x40 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN__SHIFT 0x6 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_MASK 0x3f80 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE__SHIFT 0x7 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET_MASK 0x4000 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET__SHIFT 0xe +#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ_MASK 0xf8000 +#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ__SHIFT 0xf +#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL_MASK 0x1f00000 +#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL__SHIFT 0x14 +#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL_MASK 0x3e000000 +#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL__SHIFT 0x19 +#define UNIPHY_TMDP_REG4__RESERVED_MASK 0x3fffff +#define UNIPHY_TMDP_REG4__RESERVED__SHIFT 0x0 +#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF_MASK 0x7fc00000 +#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF__SHIFT 0x16 +#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT_MASK 0x1 +#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT__SHIFT 0x0 +#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE_MASK 0x2 +#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE__SHIFT 0x1 +#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT_MASK 0x4 +#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT__SHIFT 0x2 +#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE_MASK 0x8 +#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE__SHIFT 0x3 +#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT_MASK 0x10 +#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT__SHIFT 0x4 +#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE_MASK 0x20 +#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE__SHIFT 0x5 +#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT_MASK 0x40 +#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT__SHIFT 0x6 +#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE_MASK 0x80 +#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE__SHIFT 0x7 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_MASK 0x1ff00 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN__SHIFT 0x8 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE_MASK 0x20000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE__SHIFT 0x11 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR_MASK 0x40000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR__SHIFT 0x12 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_MASK 0x780000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP__SHIFT 0x13 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE_MASK 0x800000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE__SHIFT 0x17 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR_MASK 0x1000000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR__SHIFT 0x18 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_MASK 0x3e000000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS__SHIFT 0x19 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE_MASK 0x40000000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE__SHIFT 0x1e +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR_MASK 0x80000000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR__SHIFT 0x1f +#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ_MASK 0x1 +#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ__SHIFT 0x0 +#define UNIPHY_TMDP_REG6__IRXA_OS_POLB_MASK 0x2 +#define UNIPHY_TMDP_REG6__IRXA_OS_POLB__SHIFT 0x1 +#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL_MASK 0x4 +#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL__SHIFT 0x2 +#define UNIPHY_TMDP_REG6__IRXA_SENADJ_MASK 0x78 +#define UNIPHY_TMDP_REG6__IRXA_SENADJ__SHIFT 0x3 +#define UNIPHY_TMDP_REG6__IRXA_CPSEL_MASK 0x780 +#define UNIPHY_TMDP_REG6__IRXA_CPSEL__SHIFT 0x7 +#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x800 +#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0xb +#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN_MASK 0x3ff +#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN__SHIFT 0x0 +#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN_MASK 0x10000 +#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN__SHIFT 0x10 +#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL_MASK 0xe0000 +#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL__SHIFT 0x11 +#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED_MASK 0x7fffff +#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED__SHIFT 0x0 +#define UNIPHY_DEBUG__DEBUG0_MASK 0x3ff000 +#define UNIPHY_DEBUG__DEBUG0__SHIFT 0xc +#define UNIPHY_DEBUG__DEBUG1_MASK 0x1c00000 +#define UNIPHY_DEBUG__DEBUG1__SHIFT 0x16 +#define UNIPHY_DEBUG__DBG_SEL_MASK 0x6000000 +#define UNIPHY_DEBUG__DBG_SEL__SHIFT 0x19 +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 +#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 +#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 +#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 +#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 +#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 +#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb +#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 +#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 +#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 +#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 +#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff +#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 +#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff +#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 +#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1 +#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x7 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK 0x3f +#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT 0x0 +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffc0 +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x6 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1 +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8 +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00 +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000 +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc +#define MINOR_VERSION__MINOR_VERSION_MASK 0xff +#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 +#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff +#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1 +#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 +#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2 +#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100 +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1 +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1 +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 +#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2 +#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 +#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff +#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0 +#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1 +#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 +#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x2 +#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 +#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x4 +#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 +#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x8 +#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 +#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x10 +#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 +#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x20 +#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 +#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x40 +#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6 +#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x80 +#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7 +#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x100 +#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8 +#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x200 +#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9 +#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x400 +#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa +#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x800 +#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb +#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x1000 +#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc +#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x2000 +#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd +#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x4000 +#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe +#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x8000 +#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000 +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f +#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x1 +#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 +#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x2 +#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 +#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x4 +#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 +#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x8 +#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 +#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x10 +#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 +#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x20 +#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 +#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x40 +#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6 +#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x80 +#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7 +#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x100 +#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8 +#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x200 +#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9 +#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x400 +#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa +#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x800 +#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb +#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x1000 +#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc +#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x2000 +#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd +#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x4000 +#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe +#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x8000 +#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000 +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000 +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1 +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2 +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4 +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8 +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10 +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20 +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 +#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x40 +#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6 +#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x80 +#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7 +#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x100 +#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8 +#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x200 +#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9 +#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x400 +#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa +#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x800 +#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb +#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x1000 +#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc +#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x2000 +#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd +#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x4000 +#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe +#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x8000 +#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff +#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_MASK 0x3 +#define CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 +#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1 +#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define RIRB_SIZE__RIRB_SIZE_MASK 0x3 +#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff +#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff +#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30 +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0xc +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0xc0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0xc +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0xc0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x1e0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0xff0000 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff0000 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x4 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x18 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x20 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0xc0 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x100 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x600 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x800 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x3000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x4000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x18000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x20000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0xc0000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x100000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x3 +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0xc +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x30 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0xc0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x300 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0xc00 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x3000 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc +#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK 0x1 +#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x1 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x1 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1 +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x3000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x1 +#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x1 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x10 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x100 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x1 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x10 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x100 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x1 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x10 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x100 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x3fff +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff +#define BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0 +#define BLND_CONTROL__BLND_MODE_MASK 0x300 +#define BLND_CONTROL__BLND_MODE__SHIFT 0x8 +#define BLND_CONTROL__BLND_STEREO_TYPE_MASK 0xc00 +#define BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa +#define BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000 +#define BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc +#define BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000 +#define BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd +#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000 +#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10 +#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000 +#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14 +#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000 +#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18 +#define SM_CONTROL2__SM_MODE_MASK 0x7 +#define SM_CONTROL2__SM_MODE__SHIFT 0x0 +#define SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10 +#define SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4 +#define SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20 +#define SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5 +#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300 +#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000 +#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000 +#define SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define BLND_CONTROL2__PTI_ENABLE_MASK 0x1 +#define BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0 +#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30 +#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4 +#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40 +#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6 +#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80 +#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7 +#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100 +#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8 +#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1 +#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0 +#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100 +#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8 +#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000 +#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1 +#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK_MASK 0x100 +#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK__SHIFT 0x8 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18 +#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000 +#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c +#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000 +#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d +#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000 +#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING_MASK 0x10 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING__SHIFT 0x4 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING_MASK 0x20 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING__SHIFT 0x5 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9 +#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400 +#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa +#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800 +#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb +#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1 +#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0 +#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe +#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff +#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0 +#define WB_ENABLE__WB_ENABLE_MASK 0x1 +#define WB_ENABLE__WB_ENABLE__SHIFT 0x0 +#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x1 +#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0 +#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x2 +#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1 +#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x4 +#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2 +#define WB_EC_CONFIG__DISPCLK_R_WB_RAMP_DIS_MASK 0x8 +#define WB_EC_CONFIG__DISPCLK_R_WB_RAMP_DIS__SHIFT 0x3 +#define WB_EC_CONFIG__DISPCLK_G_WB_RAMP_DIS_MASK 0x10 +#define WB_EC_CONFIG__DISPCLK_G_WB_RAMP_DIS__SHIFT 0x4 +#define WB_EC_CONFIG__DISPCLK_G_WBSCL_RAMP_DIS_MASK 0x20 +#define WB_EC_CONFIG__DISPCLK_G_WBSCL_RAMP_DIS__SHIFT 0x5 +#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x40 +#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x6 +#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x80 +#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x7 +#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x100 +#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x8 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x600 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0x9 +#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0xf000 +#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0xc +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x10000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0x10 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x60000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0x11 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x180000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x13 +#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x800000 +#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17 +#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000 +#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c +#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000 +#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e +#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x300 +#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8 +#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x1000 +#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc +#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x6000 +#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd +#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x8000 +#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf +#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000 +#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 +#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x40000 +#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12 +#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x80000 +#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13 +#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x100000 +#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14 +#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000 +#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 +#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000 +#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f +#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff +#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 +#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000 +#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 +#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff +#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 +#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000 +#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 +#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1 +#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 +#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100 +#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 +#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000 +#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 +#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff +#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 +#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000 +#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 +#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x1 +#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0 +#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff +#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 +#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000 +#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 +#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff +#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 +#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000 +#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 +#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff +#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 +#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000 +#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 +#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff +#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 +#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000 +#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 +#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff +#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 +#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000 +#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 +#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff +#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 +#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000 +#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 +#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 +#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 +#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 +#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10 +#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 +#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100 +#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 +#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000 +#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xfff0 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xfff0 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xfff0 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 +#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x1 +#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0 +#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0xc0 +#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6 +#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x1 +#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0 +#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x2 +#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1 +#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x4 +#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2 +#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x8 +#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3 +#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x100 +#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8 +#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7fff0000 +#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10 +#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xffffffff +#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0 +#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x3 +#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0 +#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x1c +#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 +#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x1 +#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff +#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10 +#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc +#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1f000000 +#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18 +#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000 +#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f +#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x2 +#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x4 +#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x8 +#define DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3 +#define DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10 +#define DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4 +#define DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK 0x1 +#define DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT 0x0 +#define DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK 0xf0 +#define DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT 0x4 +#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x8 +#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x80 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x200 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x800 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x2000 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x8000 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf +#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1f000000 +#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18 +#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000 +#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f +#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x2 +#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x4 +#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x8 +#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3 +#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10 +#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4 +#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x20 +#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5 +#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x40 +#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x8 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x10 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x20 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x40 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1f000000 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f +#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK 0x1 +#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT 0x0 +#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK 0xf0 +#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT 0x4 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x3 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x4 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x8 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x10 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x20 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x40 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x80 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x100 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x200 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x400 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x800 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x3 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0xc +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x30 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0xc0 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x300 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0xc00 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x3000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0xc000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x30000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0xc0000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12 +#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x1 +#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x2 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x10 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x100 +#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x1 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x100 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x10000 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x100000 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x1000000 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x1fff +#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x3ff0000 +#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000 +#define DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0xff +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x1000000 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0xff +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0xff00000 +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xffffffff +#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0 +#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xffffffff +#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0 +#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xffffffff +#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0 +#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xffffffff +#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0 +#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xffffffff +#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0 +#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xffffffff +#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0 +#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xffffffff +#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0 +#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xffffffff +#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0 +#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7 +#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0 +#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70 +#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b +#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x1 +#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 +#define DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE_MASK 0x2 +#define DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE__SHIFT 0x1 +#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x4 +#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2 +#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x8 +#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 +#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x10 +#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 +#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x20 +#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 +#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x40 +#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 +#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x80 +#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 +#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x100 +#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 +#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x200 +#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 +#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0xc00 +#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa +#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x3000 +#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc +#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0xc000 +#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe +#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x30000 +#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10 +#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0xc0000 +#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12 +#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x300000 +#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14 +#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0xc00000 +#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16 +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x1 +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x2 +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS_MASK 0x4 +#define DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x2 +#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x8 +#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3 +#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x10 +#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x20 +#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x40 +#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x80 +#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 +#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x100 +#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x200 +#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x400 +#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x1800 +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x2000 +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0xc000 +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x10000 +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x60000 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x80000 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x300000 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x400000 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x1800000 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x2000000 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19 +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0xc000000 +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000 +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000 +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000 +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f +#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x3 +#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x1f +#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x0 +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20 +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5 +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40 +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6 +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80 +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7 +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100 +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8 +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200 +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9 +#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x400 +#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10 +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11 +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12 +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13 +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14 +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15 +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d +#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e +#define DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS_MASK 0x10 +#define DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS__SHIFT 0x4 +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x20 +#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x5 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x40 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x6 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x80 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x7 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x100 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x8 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x200 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x9 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x10000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x10 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x20000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x11 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x40000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x12 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x80000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x13 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x100000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x14 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x200000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x15 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x1000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x18 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x2000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x19 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x4000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x1a +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x8000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x1b +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x1c +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x1d +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS_MASK 0x40000000 +#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS__SHIFT 0x1e +#define DPDBG_CNTL__DPDBG_ENABLE_MASK 0x1 +#define DPDBG_CNTL__DPDBG_ENABLE__SHIFT 0x0 +#define DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK 0x2 +#define DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT 0x1 +#define DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK 0x10 +#define DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT 0x4 +#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK 0x100 +#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT 0x8 +#define DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK 0xffff0000 +#define DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT 0x10 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK 0x1 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT 0x0 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK 0x2 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT 0x1 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK 0x100 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT 0x8 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK 0x10000 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT 0x10 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK 0x1000000 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT 0x18 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 +#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1 +#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0 +#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10 +#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4 +#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20 +#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5 +#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40 +#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6 +#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x1000 +#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc +#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000 +#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10 +#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000 +#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11 +#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000 +#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12 +#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000 +#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13 +#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000 +#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14 +#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000 +#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15 +#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000 +#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18 +#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000 +#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19 +#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000 +#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000 +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000 +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 +#define DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK 0x80000000 +#define DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT 0x1f +#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7 +#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0 +#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000 +#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10 +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK 0xff +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1 +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000 +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000 +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000 +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000 +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000 +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1 +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x20 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x40 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x80 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x100 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x200 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x400 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x800 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x1000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x2000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x4000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x8000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x10000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x20000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x40000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x80000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x100000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x200000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x400000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x800000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x1000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x2000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x4000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x8000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK 0x100 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK 0x200 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT 0x9 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK 0x400 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT 0xa +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK 0x800 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT 0xb +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x1000 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0xc +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3 +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x300 +#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE_MASK 0x3 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE__SHIFT 0x0 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE_MASK 0xc +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE__SHIFT 0x2 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE_MASK 0x180000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE__SHIFT 0x13 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS_MASK 0x200000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS__SHIFT 0x15 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE_MASK 0xc00000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE__SHIFT 0x16 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS_MASK 0x2000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS__SHIFT 0x19 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE_MASK 0xc000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE__SHIFT 0x1a +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS_MASK 0x10000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS__SHIFT 0x1c +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE_MASK 0x60000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE__SHIFT 0x1d +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS_MASK 0x80000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS__SHIFT 0x1f +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8 +#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff +#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0 +#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1 +#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf +#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff +#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0 +#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff +#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0 +#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff +#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0 +#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000 +#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18 +#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000 +#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19 +#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000 +#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN_MASK 0x400 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN__SHIFT 0xa +#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff +#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10 +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12 +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14 +#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15 +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0 +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10 +#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0 +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE_MASK 0x10000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE__SHIFT 0x1c +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP_MASK 0x60000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP__SHIFT 0x1d +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER_MASK 0x80000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER__SHIFT 0x1f +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10 +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 +#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff +#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0 +#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff +#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE_MASK 0x60000000 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE__SHIFT 0x1d +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS_MASK 0x80000000 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS__SHIFT 0x1f +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0 +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000 +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0 +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200 +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9 +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400 +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa +#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000 +#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000 +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13 +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000 +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14 +#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000 +#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18 +#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET_MASK 0x2000000 +#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET__SHIFT 0x19 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE_MASK 0xc00000 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE__SHIFT 0x16 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS_MASK 0x1000000 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS__SHIFT 0x18 +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0 +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1 +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18 +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0 +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 + +#endif /* DCE_10_0_SH_MASK_H */ -- cgit v1.2.3 From d180bab3a869c51c76cf90336b70296c36b3f3ef Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:18:28 -0400 Subject: drm/amdgpu: add DCE 11.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the DCE (Display and Composition Engine) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h | 7648 ++++++++ .../drm/amd/include/asic_reg/dce/dce_11_0_enum.h | 6129 +++++++ .../amd/include/asic_reg/dce/dce_11_0_sh_mask.h | 17557 +++++++++++++++++++ 3 files changed, 31334 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h new file mode 100644 index 000000000000..c39234ecedd0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h @@ -0,0 +1,7648 @@ +/* + * DCE_11_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_11_0_D_H +#define DCE_11_0_D_H + +#define mmPIPE0_PG_CONFIG 0x2c0 +#define mmPIPE0_PG_ENABLE 0x2c1 +#define mmPIPE0_PG_STATUS 0x2c2 +#define mmPIPE1_PG_CONFIG 0x2c3 +#define mmPIPE1_PG_ENABLE 0x2c4 +#define mmPIPE1_PG_STATUS 0x2c5 +#define mmPIPE2_PG_CONFIG 0x2c6 +#define mmPIPE2_PG_ENABLE 0x2c7 +#define mmPIPE2_PG_STATUS 0x2c8 +#define mmDCFEV0_PG_CONFIG 0x2db +#define mmDCFEV0_PG_ENABLE 0x2dc +#define mmDCFEV0_PG_STATUS 0x2dd +#define mmDCPG_INTERRUPT_STATUS 0x2de +#define mmDCPG_INTERRUPT_CONTROL 0x2df +#define mmDC_IP_REQUEST_CNTL 0x2d2 +#define mmDC_PGFSM_CONFIG_REG 0x2d3 +#define mmDC_PGFSM_WRITE_REG 0x2d4 +#define mmDC_PGCNTL_STATUS_REG 0x2d5 +#define mmDCPG_TEST_DEBUG_INDEX 0x2d6 +#define mmDCPG_TEST_DEBUG_DATA 0x2d7 +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 +#define mmBL1_PWM_USER_LEVEL 0x1629 +#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a +#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b +#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d +#define mmBL1_PWM_ABM_CNTL 0x162e +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f +#define mmBL1_PWM_GRP2_REG_LOCK 0x1630 +#define mmDC_ABM1_CNTL 0x1638 +#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e +#define mmDC_ABM1_ACE_THRES_12 0x163f +#define mmDC_ABM1_ACE_THRES_34 0x1640 +#define mmDC_ABM1_ACE_CNTL_MISC 0x1641 +#define mmDC_ABM1_DEBUG_MISC 0x1649 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a +#define mmDC_ABM1_HG_MISC_CTRL 0x164b +#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c +#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e +#define mmDC_ABM1_LS_PIXEL_COUNT 0x164f +#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 +#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 +#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a +#define mmDC_ABM1_HG_RESULT_1 0x165b +#define mmDC_ABM1_HG_RESULT_2 0x165c +#define mmDC_ABM1_HG_RESULT_3 0x165d +#define mmDC_ABM1_HG_RESULT_4 0x165e +#define mmDC_ABM1_HG_RESULT_5 0x165f +#define mmDC_ABM1_HG_RESULT_6 0x1660 +#define mmDC_ABM1_HG_RESULT_7 0x1661 +#define mmDC_ABM1_HG_RESULT_8 0x1662 +#define mmDC_ABM1_HG_RESULT_9 0x1663 +#define mmDC_ABM1_HG_RESULT_10 0x1664 +#define mmDC_ABM1_HG_RESULT_11 0x1665 +#define mmDC_ABM1_HG_RESULT_12 0x1666 +#define mmDC_ABM1_HG_RESULT_13 0x1667 +#define mmDC_ABM1_HG_RESULT_14 0x1668 +#define mmDC_ABM1_HG_RESULT_15 0x1669 +#define mmDC_ABM1_HG_RESULT_16 0x166a +#define mmDC_ABM1_HG_RESULT_17 0x166b +#define mmDC_ABM1_HG_RESULT_18 0x166c +#define mmDC_ABM1_HG_RESULT_19 0x166d +#define mmDC_ABM1_HG_RESULT_20 0x166e +#define mmDC_ABM1_HG_RESULT_21 0x166f +#define mmDC_ABM1_HG_RESULT_22 0x1670 +#define mmDC_ABM1_HG_RESULT_23 0x1671 +#define mmDC_ABM1_HG_RESULT_24 0x1672 +#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b +#define mmDC_ABM1_BL_MASTER_LOCK 0x169c +#define mmABM_TEST_DEBUG_INDEX 0x169e +#define mmABM_TEST_DEBUG_DATA 0x169f +#define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d +#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d +#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d +#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d +#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d +#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d +#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d +#define mmCRTC_H_TOTAL 0x1b80 +#define mmCRTC0_CRTC_H_TOTAL 0x1b80 +#define mmCRTC1_CRTC_H_TOTAL 0x1d80 +#define mmCRTC2_CRTC_H_TOTAL 0x1f80 +#define mmCRTC3_CRTC_H_TOTAL 0x4180 +#define mmCRTC4_CRTC_H_TOTAL 0x4380 +#define mmCRTC5_CRTC_H_TOTAL 0x4580 +#define mmCRTC_H_BLANK_START_END 0x1b81 +#define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 +#define mmCRTC1_CRTC_H_BLANK_START_END 0x1d81 +#define mmCRTC2_CRTC_H_BLANK_START_END 0x1f81 +#define mmCRTC3_CRTC_H_BLANK_START_END 0x4181 +#define mmCRTC4_CRTC_H_BLANK_START_END 0x4381 +#define mmCRTC5_CRTC_H_BLANK_START_END 0x4581 +#define mmCRTC_H_SYNC_A 0x1b82 +#define mmCRTC0_CRTC_H_SYNC_A 0x1b82 +#define mmCRTC1_CRTC_H_SYNC_A 0x1d82 +#define mmCRTC2_CRTC_H_SYNC_A 0x1f82 +#define mmCRTC3_CRTC_H_SYNC_A 0x4182 +#define mmCRTC4_CRTC_H_SYNC_A 0x4382 +#define mmCRTC5_CRTC_H_SYNC_A 0x4582 +#define mmCRTC_H_SYNC_A_CNTL 0x1b83 +#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 +#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83 +#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83 +#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183 +#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383 +#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583 +#define mmCRTC_H_SYNC_B 0x1b84 +#define mmCRTC0_CRTC_H_SYNC_B 0x1b84 +#define mmCRTC1_CRTC_H_SYNC_B 0x1d84 +#define mmCRTC2_CRTC_H_SYNC_B 0x1f84 +#define mmCRTC3_CRTC_H_SYNC_B 0x4184 +#define mmCRTC4_CRTC_H_SYNC_B 0x4384 +#define mmCRTC5_CRTC_H_SYNC_B 0x4584 +#define mmCRTC_H_SYNC_B_CNTL 0x1b85 +#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 +#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85 +#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85 +#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185 +#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385 +#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585 +#define mmCRTC_VBI_END 0x1b86 +#define mmCRTC0_CRTC_VBI_END 0x1b86 +#define mmCRTC1_CRTC_VBI_END 0x1d86 +#define mmCRTC2_CRTC_VBI_END 0x1f86 +#define mmCRTC3_CRTC_VBI_END 0x4186 +#define mmCRTC4_CRTC_VBI_END 0x4386 +#define mmCRTC5_CRTC_VBI_END 0x4586 +#define mmCRTC_V_TOTAL 0x1b87 +#define mmCRTC0_CRTC_V_TOTAL 0x1b87 +#define mmCRTC1_CRTC_V_TOTAL 0x1d87 +#define mmCRTC2_CRTC_V_TOTAL 0x1f87 +#define mmCRTC3_CRTC_V_TOTAL 0x4187 +#define mmCRTC4_CRTC_V_TOTAL 0x4387 +#define mmCRTC5_CRTC_V_TOTAL 0x4587 +#define mmCRTC_V_TOTAL_MIN 0x1b88 +#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 +#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88 +#define mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88 +#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4188 +#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4388 +#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4588 +#define mmCRTC_V_TOTAL_MAX 0x1b89 +#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 +#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89 +#define mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89 +#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4189 +#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4389 +#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4589 +#define mmCRTC_V_TOTAL_CONTROL 0x1b8a +#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a +#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a +#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a +#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a +#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a +#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a +#define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b +#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b +#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b +#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b +#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b +#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b +#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b +#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c +#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c +#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c +#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c +#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c +#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c +#define mmCRTC_V_BLANK_START_END 0x1b8d +#define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d +#define mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d +#define mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d +#define mmCRTC3_CRTC_V_BLANK_START_END 0x418d +#define mmCRTC4_CRTC_V_BLANK_START_END 0x438d +#define mmCRTC5_CRTC_V_BLANK_START_END 0x458d +#define mmCRTC_V_SYNC_A 0x1b8e +#define mmCRTC0_CRTC_V_SYNC_A 0x1b8e +#define mmCRTC1_CRTC_V_SYNC_A 0x1d8e +#define mmCRTC2_CRTC_V_SYNC_A 0x1f8e +#define mmCRTC3_CRTC_V_SYNC_A 0x418e +#define mmCRTC4_CRTC_V_SYNC_A 0x438e +#define mmCRTC5_CRTC_V_SYNC_A 0x458e +#define mmCRTC_V_SYNC_A_CNTL 0x1b8f +#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f +#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f +#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f +#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f +#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f +#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f +#define mmCRTC_V_SYNC_B 0x1b90 +#define mmCRTC0_CRTC_V_SYNC_B 0x1b90 +#define mmCRTC1_CRTC_V_SYNC_B 0x1d90 +#define mmCRTC2_CRTC_V_SYNC_B 0x1f90 +#define mmCRTC3_CRTC_V_SYNC_B 0x4190 +#define mmCRTC4_CRTC_V_SYNC_B 0x4390 +#define mmCRTC5_CRTC_V_SYNC_B 0x4590 +#define mmCRTC_V_SYNC_B_CNTL 0x1b91 +#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 +#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91 +#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91 +#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191 +#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391 +#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591 +#define mmCRTC_DTMTEST_CNTL 0x1b92 +#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 +#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92 +#define mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92 +#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4192 +#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4392 +#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4592 +#define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 +#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93 +#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93 +#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193 +#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393 +#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593 +#define mmCRTC_TRIGA_CNTL 0x1b94 +#define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 +#define mmCRTC1_CRTC_TRIGA_CNTL 0x1d94 +#define mmCRTC2_CRTC_TRIGA_CNTL 0x1f94 +#define mmCRTC3_CRTC_TRIGA_CNTL 0x4194 +#define mmCRTC4_CRTC_TRIGA_CNTL 0x4394 +#define mmCRTC5_CRTC_TRIGA_CNTL 0x4594 +#define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 +#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95 +#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95 +#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195 +#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395 +#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595 +#define mmCRTC_TRIGB_CNTL 0x1b96 +#define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 +#define mmCRTC1_CRTC_TRIGB_CNTL 0x1d96 +#define mmCRTC2_CRTC_TRIGB_CNTL 0x1f96 +#define mmCRTC3_CRTC_TRIGB_CNTL 0x4196 +#define mmCRTC4_CRTC_TRIGB_CNTL 0x4396 +#define mmCRTC5_CRTC_TRIGB_CNTL 0x4596 +#define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 +#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97 +#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97 +#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197 +#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397 +#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597 +#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 +#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98 +#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98 +#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 +#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398 +#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598 +#define mmCRTC_FLOW_CONTROL 0x1b99 +#define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 +#define mmCRTC1_CRTC_FLOW_CONTROL 0x1d99 +#define mmCRTC2_CRTC_FLOW_CONTROL 0x1f99 +#define mmCRTC3_CRTC_FLOW_CONTROL 0x4199 +#define mmCRTC4_CRTC_FLOW_CONTROL 0x4399 +#define mmCRTC5_CRTC_FLOW_CONTROL 0x4599 +#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a +#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a +#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a +#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a +#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a +#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a +#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a +#define mmCRTC_AVSYNC_COUNTER 0x1b9b +#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b +#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b +#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b +#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b +#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b +#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b +#define mmCRTC_CONTROL 0x1b9c +#define mmCRTC0_CRTC_CONTROL 0x1b9c +#define mmCRTC1_CRTC_CONTROL 0x1d9c +#define mmCRTC2_CRTC_CONTROL 0x1f9c +#define mmCRTC3_CRTC_CONTROL 0x419c +#define mmCRTC4_CRTC_CONTROL 0x439c +#define mmCRTC5_CRTC_CONTROL 0x459c +#define mmCRTC_BLANK_CONTROL 0x1b9d +#define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d +#define mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d +#define mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d +#define mmCRTC3_CRTC_BLANK_CONTROL 0x419d +#define mmCRTC4_CRTC_BLANK_CONTROL 0x439d +#define mmCRTC5_CRTC_BLANK_CONTROL 0x459d +#define mmCRTC_INTERLACE_CONTROL 0x1b9e +#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e +#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e +#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e +#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e +#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e +#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e +#define mmCRTC_INTERLACE_STATUS 0x1b9f +#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f +#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f +#define mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f +#define mmCRTC3_CRTC_INTERLACE_STATUS 0x419f +#define mmCRTC4_CRTC_INTERLACE_STATUS 0x439f +#define mmCRTC5_CRTC_INTERLACE_STATUS 0x459f +#define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 +#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0 +#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0 +#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0 +#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0 +#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0 +#define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1 +#define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 +#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2 +#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2 +#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2 +#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2 +#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2 +#define mmCRTC_STATUS 0x1ba3 +#define mmCRTC0_CRTC_STATUS 0x1ba3 +#define mmCRTC1_CRTC_STATUS 0x1da3 +#define mmCRTC2_CRTC_STATUS 0x1fa3 +#define mmCRTC3_CRTC_STATUS 0x41a3 +#define mmCRTC4_CRTC_STATUS 0x43a3 +#define mmCRTC5_CRTC_STATUS 0x45a3 +#define mmCRTC_STATUS_POSITION 0x1ba4 +#define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 +#define mmCRTC1_CRTC_STATUS_POSITION 0x1da4 +#define mmCRTC2_CRTC_STATUS_POSITION 0x1fa4 +#define mmCRTC3_CRTC_STATUS_POSITION 0x41a4 +#define mmCRTC4_CRTC_STATUS_POSITION 0x43a4 +#define mmCRTC5_CRTC_STATUS_POSITION 0x45a4 +#define mmCRTC_NOM_VERT_POSITION 0x1ba5 +#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 +#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5 +#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5 +#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5 +#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5 +#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5 +#define mmCRTC_STATUS_FRAME_COUNT 0x1ba6 +#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 +#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6 +#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6 +#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6 +#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6 +#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6 +#define mmCRTC_STATUS_VF_COUNT 0x1ba7 +#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 +#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7 +#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7 +#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7 +#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7 +#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7 +#define mmCRTC_STATUS_HV_COUNT 0x1ba8 +#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 +#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8 +#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8 +#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8 +#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8 +#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8 +#define mmCRTC_COUNT_CONTROL 0x1ba9 +#define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 +#define mmCRTC1_CRTC_COUNT_CONTROL 0x1da9 +#define mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9 +#define mmCRTC3_CRTC_COUNT_CONTROL 0x41a9 +#define mmCRTC4_CRTC_COUNT_CONTROL 0x43a9 +#define mmCRTC5_CRTC_COUNT_CONTROL 0x45a9 +#define mmCRTC_COUNT_RESET 0x1baa +#define mmCRTC0_CRTC_COUNT_RESET 0x1baa +#define mmCRTC1_CRTC_COUNT_RESET 0x1daa +#define mmCRTC2_CRTC_COUNT_RESET 0x1faa +#define mmCRTC3_CRTC_COUNT_RESET 0x41aa +#define mmCRTC4_CRTC_COUNT_RESET 0x43aa +#define mmCRTC5_CRTC_COUNT_RESET 0x45aa +#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab +#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab +#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab +#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab +#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab +#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab +#define mmCRTC_VERT_SYNC_CONTROL 0x1bac +#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac +#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac +#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac +#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac +#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac +#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac +#define mmCRTC_STEREO_STATUS 0x1bad +#define mmCRTC0_CRTC_STEREO_STATUS 0x1bad +#define mmCRTC1_CRTC_STEREO_STATUS 0x1dad +#define mmCRTC2_CRTC_STEREO_STATUS 0x1fad +#define mmCRTC3_CRTC_STEREO_STATUS 0x41ad +#define mmCRTC4_CRTC_STEREO_STATUS 0x43ad +#define mmCRTC5_CRTC_STEREO_STATUS 0x45ad +#define mmCRTC_STEREO_CONTROL 0x1bae +#define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae +#define mmCRTC1_CRTC_STEREO_CONTROL 0x1dae +#define mmCRTC2_CRTC_STEREO_CONTROL 0x1fae +#define mmCRTC3_CRTC_STEREO_CONTROL 0x41ae +#define mmCRTC4_CRTC_STEREO_CONTROL 0x43ae +#define mmCRTC5_CRTC_STEREO_CONTROL 0x45ae +#define mmCRTC_SNAPSHOT_STATUS 0x1baf +#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf +#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf +#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf +#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af +#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af +#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af +#define mmCRTC_SNAPSHOT_CONTROL 0x1bb0 +#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 +#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0 +#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0 +#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0 +#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0 +#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0 +#define mmCRTC_SNAPSHOT_POSITION 0x1bb1 +#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 +#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1 +#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1 +#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1 +#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1 +#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1 +#define mmCRTC_SNAPSHOT_FRAME 0x1bb2 +#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 +#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2 +#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2 +#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2 +#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2 +#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2 +#define mmCRTC_START_LINE_CONTROL 0x1bb3 +#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 +#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3 +#define mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3 +#define mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3 +#define mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3 +#define mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3 +#define mmCRTC_INTERRUPT_CONTROL 0x1bb4 +#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 +#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4 +#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4 +#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4 +#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4 +#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4 +#define mmCRTC_UPDATE_LOCK 0x1bb5 +#define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 +#define mmCRTC1_CRTC_UPDATE_LOCK 0x1db5 +#define mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5 +#define mmCRTC3_CRTC_UPDATE_LOCK 0x41b5 +#define mmCRTC4_CRTC_UPDATE_LOCK 0x43b5 +#define mmCRTC5_CRTC_UPDATE_LOCK 0x45b5 +#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 +#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6 +#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6 +#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 +#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6 +#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6 +#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 +#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7 +#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7 +#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 +#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7 +#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7 +#define mmCRTC_TEST_PATTERN_CONTROL 0x1bba +#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba +#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba +#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba +#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba +#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba +#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba +#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb +#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb +#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb +#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb +#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb +#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb +#define mmCRTC_TEST_PATTERN_COLOR 0x1bbc +#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc +#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc +#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc +#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc +#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc +#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc +#define mmCRTC_MASTER_UPDATE_LOCK 0x1bbd +#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x1bbd +#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x1dbd +#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x1fbd +#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x41bd +#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x43bd +#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x45bd +#define mmCRTC_MASTER_UPDATE_MODE 0x1bbe +#define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x1bbe +#define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x1dbe +#define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x1fbe +#define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x41be +#define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x43be +#define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x45be +#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf +#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 +#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0 +#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0 +#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 +#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0 +#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0 +#define mmCRTC_MVP_STATUS 0x1bc1 +#define mmCRTC0_CRTC_MVP_STATUS 0x1bc1 +#define mmCRTC1_CRTC_MVP_STATUS 0x1dc1 +#define mmCRTC2_CRTC_MVP_STATUS 0x1fc1 +#define mmCRTC3_CRTC_MVP_STATUS 0x41c1 +#define mmCRTC4_CRTC_MVP_STATUS 0x43c1 +#define mmCRTC5_CRTC_MVP_STATUS 0x45c1 +#define mmCRTC_MASTER_EN 0x1bc2 +#define mmCRTC0_CRTC_MASTER_EN 0x1bc2 +#define mmCRTC1_CRTC_MASTER_EN 0x1dc2 +#define mmCRTC2_CRTC_MASTER_EN 0x1fc2 +#define mmCRTC3_CRTC_MASTER_EN 0x41c2 +#define mmCRTC4_CRTC_MASTER_EN 0x43c2 +#define mmCRTC5_CRTC_MASTER_EN 0x45c2 +#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 +#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3 +#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3 +#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 +#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3 +#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3 +#define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 +#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4 +#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4 +#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4 +#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4 +#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4 +#define mmCRTC_OVERSCAN_COLOR 0x1bc8 +#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 +#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8 +#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8 +#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8 +#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8 +#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8 +#define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 +#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9 +#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9 +#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9 +#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9 +#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9 +#define mmCRTC_BLANK_DATA_COLOR 0x1bca +#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca +#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca +#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca +#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca +#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca +#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca +#define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb +#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb +#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb +#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb +#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb +#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb +#define mmCRTC_BLACK_COLOR 0x1bcc +#define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc +#define mmCRTC1_CRTC_BLACK_COLOR 0x1dcc +#define mmCRTC2_CRTC_BLACK_COLOR 0x1fcc +#define mmCRTC3_CRTC_BLACK_COLOR 0x41cc +#define mmCRTC4_CRTC_BLACK_COLOR 0x43cc +#define mmCRTC5_CRTC_BLACK_COLOR 0x45cc +#define mmCRTC_BLACK_COLOR_EXT 0x1bcd +#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd +#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd +#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd +#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd +#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd +#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd +#define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce +#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf +#define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0 +#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1 +#define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2 +#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 +#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3 +#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3 +#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 +#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3 +#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3 +#define mmCRTC_CRC_CNTL 0x1bd4 +#define mmCRTC0_CRTC_CRC_CNTL 0x1bd4 +#define mmCRTC1_CRTC_CRC_CNTL 0x1dd4 +#define mmCRTC2_CRTC_CRC_CNTL 0x1fd4 +#define mmCRTC3_CRTC_CRC_CNTL 0x41d4 +#define mmCRTC4_CRTC_CRC_CNTL 0x43d4 +#define mmCRTC5_CRTC_CRC_CNTL 0x45d4 +#define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 +#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5 +#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5 +#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 +#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5 +#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5 +#define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 +#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6 +#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6 +#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 +#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6 +#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6 +#define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 +#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7 +#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7 +#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 +#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7 +#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7 +#define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 +#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8 +#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8 +#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 +#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8 +#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8 +#define mmCRTC_CRC0_DATA_RG 0x1bd9 +#define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 +#define mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9 +#define mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9 +#define mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9 +#define mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9 +#define mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9 +#define mmCRTC_CRC0_DATA_B 0x1bda +#define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda +#define mmCRTC1_CRTC_CRC0_DATA_B 0x1dda +#define mmCRTC2_CRTC_CRC0_DATA_B 0x1fda +#define mmCRTC3_CRTC_CRC0_DATA_B 0x41da +#define mmCRTC4_CRTC_CRC0_DATA_B 0x43da +#define mmCRTC5_CRTC_CRC0_DATA_B 0x45da +#define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb +#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb +#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb +#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db +#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db +#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db +#define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc +#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc +#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc +#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc +#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc +#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc +#define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd +#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd +#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd +#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd +#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd +#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd +#define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde +#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde +#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde +#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de +#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de +#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de +#define mmCRTC_CRC1_DATA_RG 0x1bdf +#define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf +#define mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf +#define mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf +#define mmCRTC3_CRTC_CRC1_DATA_RG 0x41df +#define mmCRTC4_CRTC_CRC1_DATA_RG 0x43df +#define mmCRTC5_CRTC_CRC1_DATA_RG 0x45df +#define mmCRTC_CRC1_DATA_B 0x1be0 +#define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 +#define mmCRTC1_CRTC_CRC1_DATA_B 0x1de0 +#define mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0 +#define mmCRTC3_CRTC_CRC1_DATA_B 0x41e0 +#define mmCRTC4_CRTC_CRC1_DATA_B 0x43e0 +#define mmCRTC5_CRTC_CRC1_DATA_B 0x45e0 +#define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 +#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7 +#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7 +#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7 +#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7 +#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7 +#define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 +#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78 +#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78 +#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178 +#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378 +#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578 +#define mmCRTC_GSL_VSYNC_GAP 0x1b79 +#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 +#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79 +#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79 +#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179 +#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379 +#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579 +#define mmCRTC_GSL_WINDOW 0x1b7a +#define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a +#define mmCRTC1_CRTC_GSL_WINDOW 0x1d7a +#define mmCRTC2_CRTC_GSL_WINDOW 0x1f7a +#define mmCRTC3_CRTC_GSL_WINDOW 0x417a +#define mmCRTC4_CRTC_GSL_WINDOW 0x437a +#define mmCRTC5_CRTC_GSL_WINDOW 0x457a +#define mmCRTC_GSL_CONTROL 0x1b7b +#define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b +#define mmCRTC1_CRTC_GSL_CONTROL 0x1d7b +#define mmCRTC2_CRTC_GSL_CONTROL 0x1f7b +#define mmCRTC3_CRTC_GSL_CONTROL 0x417b +#define mmCRTC4_CRTC_GSL_CONTROL 0x437b +#define mmCRTC5_CRTC_GSL_CONTROL 0x457b +#define mmCRTC_TEST_DEBUG_INDEX 0x1bc6 +#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 +#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6 +#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6 +#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6 +#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6 +#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6 +#define mmCRTC_TEST_DEBUG_DATA 0x1bc7 +#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 +#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7 +#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7 +#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7 +#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7 +#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7 +#define mmDAC_ENABLE 0x16aa +#define mmDAC_SOURCE_SELECT 0x16ab +#define mmDAC_CRC_EN 0x16ac +#define mmDAC_CRC_CONTROL 0x16ad +#define mmDAC_CRC_SIG_RGB_MASK 0x16ae +#define mmDAC_CRC_SIG_CONTROL_MASK 0x16af +#define mmDAC_CRC_SIG_RGB 0x16b0 +#define mmDAC_CRC_SIG_CONTROL 0x16b1 +#define mmDAC_SYNC_TRISTATE_CONTROL 0x16b2 +#define mmDAC_STEREOSYNC_SELECT 0x16b3 +#define mmDAC_AUTODETECT_CONTROL 0x16b4 +#define mmDAC_AUTODETECT_CONTROL2 0x16b5 +#define mmDAC_AUTODETECT_CONTROL3 0x16b6 +#define mmDAC_AUTODETECT_STATUS 0x16b7 +#define mmDAC_AUTODETECT_INT_CONTROL 0x16b8 +#define mmDAC_FORCE_OUTPUT_CNTL 0x16b9 +#define mmDAC_FORCE_DATA 0x16ba +#define mmDAC_POWERDOWN 0x16bb +#define mmDAC_CONTROL 0x16bc +#define mmDAC_COMPARATOR_ENABLE 0x16bd +#define mmDAC_COMPARATOR_OUTPUT 0x16be +#define mmDAC_PWR_CNTL 0x16bf +#define mmDAC_DFT_CONFIG 0x16c0 +#define mmDAC_FIFO_STATUS 0x16c1 +#define mmDAC_TEST_DEBUG_INDEX 0x16c2 +#define mmDAC_TEST_DEBUG_DATA 0x16c3 +#define mmPERFCOUNTER_CNTL 0x170 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68 +#define mmPERFCOUNTER_STATE 0x171 +#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 +#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x365 +#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9 +#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25 +#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25 +#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25 +#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125 +#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325 +#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525 +#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725 +#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1 +#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69 +#define mmPERFMON_CNTL 0x173 +#define mmDC_PERFMON0_PERFMON_CNTL 0x173 +#define mmDC_PERFMON1_PERFMON_CNTL 0x367 +#define mmDC_PERFMON2_PERFMON_CNTL 0x18cb +#define mmDC_PERFMON3_PERFMON_CNTL 0x1b27 +#define mmDC_PERFMON4_PERFMON_CNTL 0x1d27 +#define mmDC_PERFMON5_PERFMON_CNTL 0x1f27 +#define mmDC_PERFMON6_PERFMON_CNTL 0x4127 +#define mmDC_PERFMON7_PERFMON_CNTL 0x4327 +#define mmDC_PERFMON8_PERFMON_CNTL 0x4527 +#define mmDC_PERFMON9_PERFMON_CNTL 0x4727 +#define mmDC_PERFMON10_PERFMON_CNTL 0x59a3 +#define mmDC_PERFMON11_PERFMON_CNTL 0x5f6b +#define mmPERFMON_CNTL2 0x17a +#define mmDC_PERFMON0_PERFMON_CNTL2 0x17a +#define mmDC_PERFMON1_PERFMON_CNTL2 0x36e +#define mmDC_PERFMON2_PERFMON_CNTL2 0x18d2 +#define mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e +#define mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e +#define mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e +#define mmDC_PERFMON6_PERFMON_CNTL2 0x412e +#define mmDC_PERFMON7_PERFMON_CNTL2 0x432e +#define mmDC_PERFMON8_PERFMON_CNTL2 0x452e +#define mmDC_PERFMON9_PERFMON_CNTL2 0x472e +#define mmDC_PERFMON10_PERFMON_CNTL2 0x59aa +#define mmDC_PERFMON11_PERFMON_CNTL2 0x5f72 +#define mmPERFMON_CVALUE_INT_MISC 0x172 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726 +#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a +#define mmPERFMON_CVALUE_LOW 0x174 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728 +#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4 +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c +#define mmPERFMON_HI 0x175 +#define mmDC_PERFMON0_PERFMON_HI 0x175 +#define mmDC_PERFMON1_PERFMON_HI 0x369 +#define mmDC_PERFMON2_PERFMON_HI 0x18cd +#define mmDC_PERFMON3_PERFMON_HI 0x1b29 +#define mmDC_PERFMON4_PERFMON_HI 0x1d29 +#define mmDC_PERFMON5_PERFMON_HI 0x1f29 +#define mmDC_PERFMON6_PERFMON_HI 0x4129 +#define mmDC_PERFMON7_PERFMON_HI 0x4329 +#define mmDC_PERFMON8_PERFMON_HI 0x4529 +#define mmDC_PERFMON9_PERFMON_HI 0x4729 +#define mmDC_PERFMON10_PERFMON_HI 0x59a5 +#define mmDC_PERFMON11_PERFMON_HI 0x5f6d +#define mmPERFMON_LOW 0x176 +#define mmDC_PERFMON0_PERFMON_LOW 0x176 +#define mmDC_PERFMON1_PERFMON_LOW 0x36a +#define mmDC_PERFMON2_PERFMON_LOW 0x18ce +#define mmDC_PERFMON3_PERFMON_LOW 0x1b2a +#define mmDC_PERFMON4_PERFMON_LOW 0x1d2a +#define mmDC_PERFMON5_PERFMON_LOW 0x1f2a +#define mmDC_PERFMON6_PERFMON_LOW 0x412a +#define mmDC_PERFMON7_PERFMON_LOW 0x432a +#define mmDC_PERFMON8_PERFMON_LOW 0x452a +#define mmDC_PERFMON9_PERFMON_LOW 0x472a +#define mmDC_PERFMON10_PERFMON_LOW 0x59a6 +#define mmDC_PERFMON11_PERFMON_LOW 0x5f6e +#define mmPERFMON_TEST_DEBUG_INDEX 0x177 +#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 +#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b +#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf +#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b +#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b +#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b +#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b +#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b +#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b +#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b +#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7 +#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f +#define mmPERFMON_TEST_DEBUG_DATA 0x178 +#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 +#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c +#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0 +#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c +#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c +#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c +#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c +#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c +#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c +#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c +#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8 +#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70 +#define mmREFCLK_CNTL 0x109 +#define mmDCCG_CBUS_WRCMD_DELAY 0x110 +#define mmDPREFCLK_CNTL 0x118 +#define mmDCE_VERSION 0x11e +#define mmAVSYNC_COUNTER_WRITE 0x12a +#define mmAVSYNC_COUNTER_CONTROL 0x12b +#define mmAVSYNC_COUNTER_READ 0x12f +#define mmDCCG_GTC_CNTL 0x120 +#define mmDCCG_GTC_DTO_INCR 0x121 +#define mmDCCG_GTC_DTO_MODULO 0x122 +#define mmDCCG_GTC_CURRENT 0x123 +#define mmDCCG_DS_DTO_INCR 0x113 +#define mmDCCG_DS_DTO_MODULO 0x114 +#define mmDCCG_DS_CNTL 0x115 +#define mmDCCG_DS_HW_CAL_INTERVAL 0x116 +#define mmDCCG_DS_DEBUG_CNTL 0x112 +#define mmDMCU_SMU_INTERRUPT_CNTL 0x12c +#define mmSMU_CONTROL 0x12d +#define mmSMU_INTERRUPT_CONTROL 0x12e +#define mmDAC_CLK_ENABLE 0x128 +#define mmDVO_CLK_ENABLE 0x129 +#define mmDCCG_GATE_DISABLE_CNTL 0x134 +#define mmDCCG_GATE_DISABLE_CNTL2 0x13c +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 +#define mmSCLK_CGTT_BLK_CTRL_REG 0x136 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108 +#define mmREFCLK_CGTT_BLK_CTRL_REG 0x10b +#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x13d +#define mmDCCG_CAC_STATUS 0x137 +#define mmPIXCLK1_RESYNC_CNTL 0x138 +#define mmPIXCLK2_RESYNC_CNTL 0x139 +#define mmPIXCLK0_RESYNC_CNTL 0x13a +#define mmPHYPLL_PIXCLK_CNTL 0x13e +#define mmMICROSECOND_TIME_BASE_DIV 0x13b +#define mmDCCG_DISP_CNTL_REG 0x13f +#define mmMILLISECOND_TIME_BASE_DIV 0x130 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x131 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132 +#define mmDCCG_PERFMON_CNTL 0x133 +#define mmDCCG_PERFMON_CNTL2 0x10e +#define mmCRTC0_PIXEL_RATE_CNTL 0x140 +#define mmDP_DTO0_PHASE 0x141 +#define mmDP_DTO0_MODULO 0x142 +#define mmCRTC1_PIXEL_RATE_CNTL 0x144 +#define mmDP_DTO1_PHASE 0x145 +#define mmDP_DTO1_MODULO 0x146 +#define mmCRTC2_PIXEL_RATE_CNTL 0x148 +#define mmDP_DTO2_PHASE 0x149 +#define mmDP_DTO2_MODULO 0x14a +#define mmCRTC3_PIXEL_RATE_CNTL 0x14c +#define mmDP_DTO3_PHASE 0x14d +#define mmDP_DTO3_MODULO 0x14e +#define mmCRTC4_PIXEL_RATE_CNTL 0x150 +#define mmDP_DTO4_PHASE 0x151 +#define mmDP_DTO4_MODULO 0x152 +#define mmCRTC5_PIXEL_RATE_CNTL 0x154 +#define mmDP_DTO5_PHASE 0x155 +#define mmDP_DTO5_MODULO 0x156 +#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x104 +#define mmDCCG_SOFT_RESET 0x15f +#define mmSYMCLKA_CLOCK_ENABLE 0x160 +#define mmSYMCLKB_CLOCK_ENABLE 0x161 +#define mmSYMCLKC_CLOCK_ENABLE 0x162 +#define mmSYMCLKD_CLOCK_ENABLE 0x163 +#define mmSYMCLKE_CLOCK_ENABLE 0x164 +#define mmSYMCLKF_CLOCK_ENABLE 0x165 +#define mmSYMCLKG_CLOCK_ENABLE 0x117 +#define mmDPDBG_CLK_FORCE_CONTROL 0x10d +#define mmDCCG_AUDIO_DTO_SOURCE 0x16b +#define mmDCCG_AUDIO_DTO0_PHASE 0x16c +#define mmDCCG_AUDIO_DTO0_MODULE 0x16d +#define mmDCCG_AUDIO_DTO1_PHASE 0x16e +#define mmDCCG_AUDIO_DTO1_MODULE 0x16f +#define mmDCCG_TEST_DEBUG_INDEX 0x17c +#define mmDCCG_TEST_DEBUG_DATA 0x17d +#define mmDCCG_TEST_CLK_SEL 0x17e +#define mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4 +#define mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5 +#define mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6 +#define mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7 +#define mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8 +#define mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9 +#define mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa +#define mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb +#define mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc +#define mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9 +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9 +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd +#define mmCPLL_MACRO_CNTL_RESERVED10 0x5fda +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe +#define mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb +#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb +#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7 +#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3 +#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff +#define mmPLL_MACRO_CNTL_RESERVED0 0x1700 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754 +#define mmPLL_MACRO_CNTL_RESERVED1 0x1701 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755 +#define mmPLL_MACRO_CNTL_RESERVED2 0x1702 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756 +#define mmPLL_MACRO_CNTL_RESERVED3 0x1703 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757 +#define mmPLL_MACRO_CNTL_RESERVED4 0x1704 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758 +#define mmPLL_MACRO_CNTL_RESERVED5 0x1705 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759 +#define mmPLL_MACRO_CNTL_RESERVED6 0x1706 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a +#define mmPLL_MACRO_CNTL_RESERVED7 0x1707 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b +#define mmPLL_MACRO_CNTL_RESERVED8 0x1708 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c +#define mmPLL_MACRO_CNTL_RESERVED9 0x1709 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d +#define mmPLL_MACRO_CNTL_RESERVED10 0x170a +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e +#define mmPLL_MACRO_CNTL_RESERVED11 0x170b +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f +#define mmPLL_MACRO_CNTL_RESERVED12 0x170c +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760 +#define mmPLL_MACRO_CNTL_RESERVED13 0x170d +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761 +#define mmPLL_MACRO_CNTL_RESERVED14 0x170e +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762 +#define mmPLL_MACRO_CNTL_RESERVED15 0x170f +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763 +#define mmPLL_MACRO_CNTL_RESERVED16 0x1710 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764 +#define mmPLL_MACRO_CNTL_RESERVED17 0x1711 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765 +#define mmPLL_MACRO_CNTL_RESERVED18 0x1712 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766 +#define mmPLL_MACRO_CNTL_RESERVED19 0x1713 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767 +#define mmPLL_MACRO_CNTL_RESERVED20 0x1714 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768 +#define mmPLL_MACRO_CNTL_RESERVED21 0x1715 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769 +#define mmPLL_MACRO_CNTL_RESERVED22 0x1716 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a +#define mmPLL_MACRO_CNTL_RESERVED23 0x1717 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b +#define mmPLL_MACRO_CNTL_RESERVED24 0x1718 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c +#define mmPLL_MACRO_CNTL_RESERVED25 0x1719 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d +#define mmPLL_MACRO_CNTL_RESERVED26 0x171a +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e +#define mmPLL_MACRO_CNTL_RESERVED27 0x171b +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f +#define mmPLL_MACRO_CNTL_RESERVED28 0x171c +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770 +#define mmPLL_MACRO_CNTL_RESERVED29 0x171d +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771 +#define mmPLL_MACRO_CNTL_RESERVED30 0x171e +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772 +#define mmPLL_MACRO_CNTL_RESERVED31 0x171f +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773 +#define mmPLL_MACRO_CNTL_RESERVED32 0x1720 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774 +#define mmPLL_MACRO_CNTL_RESERVED33 0x1721 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775 +#define mmPLL_MACRO_CNTL_RESERVED34 0x1722 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776 +#define mmPLL_MACRO_CNTL_RESERVED35 0x1723 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777 +#define mmPLL_MACRO_CNTL_RESERVED36 0x1724 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778 +#define mmPLL_MACRO_CNTL_RESERVED37 0x1725 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779 +#define mmPLL_MACRO_CNTL_RESERVED38 0x1726 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a +#define mmPLL_MACRO_CNTL_RESERVED39 0x1727 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b +#define mmPLL_MACRO_CNTL_RESERVED40 0x1728 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c +#define mmPLL_MACRO_CNTL_RESERVED41 0x1729 +#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729 +#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753 +#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d +#define mmDENTIST_DISPCLK_CNTL 0x124 +#define mmDCDEBUG_BUS_CLK1_SEL 0x16c4 +#define mmDCDEBUG_BUS_CLK2_SEL 0x16c5 +#define mmDCDEBUG_BUS_CLK3_SEL 0x16c6 +#define mmDCDEBUG_BUS_CLK4_SEL 0x16c7 +#define mmDCDEBUG_BUS_CLK5_SEL 0x16c8 +#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9 +#define mmDCDEBUG_OUT_CNTL 0x16ca +#define mmDCDEBUG_OUT_DATA 0x16cb +#define mmDMIF_ADDR_CONFIG 0x2f5 +#define mmDMIF_CONTROL 0x2f6 +#define mmDMIF_STATUS 0x2f7 +#define mmDMIF_HW_DEBUG 0x2f8 +#define mmDMIF_ARBITRATION_CONTROL 0x2f9 +#define mmPIPE0_ARBITRATION_CONTROL3 0x2fa +#define mmPIPE1_ARBITRATION_CONTROL3 0x2fb +#define mmPIPE2_ARBITRATION_CONTROL3 0x2fc +#define mmPIPE3_ARBITRATION_CONTROL3 0x2fd +#define mmPIPE4_ARBITRATION_CONTROL3 0x2fe +#define mmPIPE5_ARBITRATION_CONTROL3 0x2ff +#define mmPIPE6_ARBITRATION_CONTROL3 0x32a +#define mmPIPE7_ARBITRATION_CONTROL3 0x32b +#define mmDMIF_P_VMID 0x300 +#define mmDMIF_URG_OVERRIDE 0x329 +#define mmDMIF_TEST_DEBUG_INDEX 0x301 +#define mmDMIF_TEST_DEBUG_DATA 0x302 +#define ixDMIF_DEBUG02_CORE0 0x2 +#define ixDMIF_DEBUG02_CORE1 0xa +#define mmDMIF_ADDR_CALC 0x303 +#define mmDMIF_STATUS2 0x304 +#define mmPIPE0_MAX_REQUESTS 0x305 +#define mmPIPE1_MAX_REQUESTS 0x306 +#define mmPIPE2_MAX_REQUESTS 0x307 +#define mmPIPE3_MAX_REQUESTS 0x308 +#define mmPIPE4_MAX_REQUESTS 0x309 +#define mmPIPE5_MAX_REQUESTS 0x30a +#define mmPIPE6_MAX_REQUESTS 0x32c +#define mmPIPE7_MAX_REQUESTS 0x32d +#define mmDVMM_REG_RD_STATUS 0x32e +#define mmDVMM_REG_RD_DATA 0x32f +#define mmDVMM_PTE_REQ 0x330 +#define mmDVMM_CNTL 0x331 +#define mmDVMM_FAULT_STATUS 0x332 +#define mmDVMM_FAULT_ADDR 0x333 +#define mmLOW_POWER_TILING_CONTROL 0x30b +#define mmMCIF_CONTROL 0x30c +#define mmMCIF_WRITE_COMBINE_CONTROL 0x30d +#define mmMCIF_TEST_DEBUG_INDEX 0x30e +#define mmMCIF_TEST_DEBUG_DATA 0x30f +#define ixIDDCCIF02_DBG_DCCIF_C 0x9 +#define ixIDDCCIF04_DBG_DCCIF_E 0xb +#define ixIDDCCIF05_DBG_DCCIF_F 0xc +#define mmMCIF_VMID 0x310 +#define mmMCIF_MEM_CONTROL 0x311 +#define mmCC_DC_PIPE_DIS 0x312 +#define mmMC_DC_INTERFACE_NACK_STATUS 0x313 +#define mmRBBMIF_TIMEOUT 0x314 +#define mmRBBMIF_STATUS 0x315 +#define mmRBBMIF_TIMEOUT_DIS 0x316 +#define mmRBBMIF_STATUS_FLAG 0x327 +#define mmDCI_MEM_PWR_STATUS 0x317 +#define mmDCI_MEM_PWR_STATUS2 0x318 +#define mmDCI_CLK_CNTL 0x319 +#define mmDCI_CLK_RAMP_CNTL 0x31a +#define mmDCI_MEM_PWR_CNTL 0x31b +#define mmDCI_MEM_PWR_CNTL2 0x31c +#define mmDCI_MEM_PWR_CNTL3 0x31d +#define mmDVMM_PTE_PGMEM_CONTROL 0x335 +#define mmDVMM_PTE_PGMEM_STATE 0x336 +#define mmDCI_SOFT_RESET 0x328 +#define mmDCI_MISC 0x334 +#define mmDCI_TEST_DEBUG_INDEX 0x31e +#define mmDCI_TEST_DEBUG_DATA 0x31f +#define mmDCI_DEBUG_CONFIG 0x320 +#define mmPIPE0_DMIF_BUFFER_CONTROL 0x321 +#define mmPIPE1_DMIF_BUFFER_CONTROL 0x322 +#define mmPIPE2_DMIF_BUFFER_CONTROL 0x323 +#define mmPIPE3_DMIF_BUFFER_CONTROL 0x324 +#define mmPIPE4_DMIF_BUFFER_CONTROL 0x325 +#define mmPIPE5_DMIF_BUFFER_CONTROL 0x326 +#define mmDC_GENERICA 0x4800 +#define mmDC_GENERICB 0x4801 +#define mmDC_PAD_EXTERN_SIG 0x4802 +#define mmDC_REF_CLK_CNTL 0x4803 +#define mmDC_GPIO_DEBUG 0x4804 +#define mmUNIPHYA_LINK_CNTL 0x4805 +#define mmUNIPHYB_LINK_CNTL 0x4807 +#define mmUNIPHYC_LINK_CNTL 0x4809 +#define mmUNIPHYD_LINK_CNTL 0x480b +#define mmUNIPHYE_LINK_CNTL 0x480d +#define mmUNIPHYF_LINK_CNTL 0x480f +#define mmUNIPHYG_LINK_CNTL 0x4811 +#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808 +#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a +#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c +#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e +#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810 +#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812 +#define mmUNIPHYLPA_LINK_CNTL 0x4847 +#define mmUNIPHYLPB_LINK_CNTL 0x4848 +#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x4849 +#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x484a +#define mmUNIPHY_IMPCAL_LINKA 0x4838 +#define mmUNIPHY_IMPCAL_LINKB 0x4839 +#define mmUNIPHY_IMPCAL_LINKC 0x483f +#define mmUNIPHY_IMPCAL_LINKD 0x4840 +#define mmUNIPHY_IMPCAL_LINKE 0x4843 +#define mmUNIPHY_IMPCAL_LINKF 0x4844 +#define mmUNIPHY_IMPCAL_PERIOD 0x483a +#define mmAUXP_IMPCAL 0x483b +#define mmAUXN_IMPCAL 0x483c +#define mmDCIO_IMPCAL_CNTL 0x483d +#define mmUNIPHY_IMPCAL_PSW_AB 0x483e +#define mmDCIO_IMPCAL_CNTL_CD 0x4841 +#define mmUNIPHY_IMPCAL_PSW_CD 0x4842 +#define mmDCIO_IMPCAL_CNTL_EF 0x4845 +#define mmUNIPHY_IMPCAL_PSW_EF 0x4846 +#define mmDCIO_WRCMD_DELAY 0x4816 +#define mmDC_PINSTRAPS 0x4818 +#define mmDC_DVODATA_CONFIG 0x481a +#define mmLVTMA_PWRSEQ_CNTL 0x481b +#define mmLVTMA_PWRSEQ_STATE 0x481c +#define mmLVTMA_PWRSEQ_REF_DIV 0x481d +#define mmLVTMA_PWRSEQ_DELAY1 0x481e +#define mmLVTMA_PWRSEQ_DELAY2 0x481f +#define mmBL_PWM_CNTL 0x4820 +#define mmBL_PWM_CNTL2 0x4821 +#define mmBL_PWM_PERIOD_CNTL 0x4822 +#define mmBL_PWM_GRP1_REG_LOCK 0x4823 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x4824 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825 +#define mmDCIO_GSL0_CNTL 0x4826 +#define mmDCIO_GSL1_CNTL 0x4827 +#define mmDCIO_GSL2_CNTL 0x4828 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829 +#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a +#define mmDC_GPU_TIMER_READ 0x482b +#define mmDC_GPU_TIMER_READ_CNTL 0x482c +#define mmDCIO_CLOCK_CNTL 0x482d +#define mmDCIO_DEBUG 0x482f +#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830 +#define mmDBG_OUT_CNTL 0x4834 +#define mmDCIO_DEBUG_CONFIG 0x4835 +#define mmDCIO_SOFT_RESET 0x4836 +#define mmDCIO_DPHY_SEL 0x4837 +#define mmDCIO_TEST_DEBUG_INDEX 0x4831 +#define mmDCIO_TEST_DEBUG_DATA 0x4832 +#define ixDCIO_DEBUG1 0x1 +#define ixDCIO_DEBUG2 0x2 +#define ixDCIO_DEBUG3 0x3 +#define ixDCIO_DEBUG4 0x4 +#define ixDCIO_DEBUG5 0x5 +#define ixDCIO_DEBUG6 0x6 +#define ixDCIO_DEBUG7 0x7 +#define ixDCIO_DEBUG8 0x8 +#define ixDCIO_DEBUG9 0x9 +#define ixDCIO_DEBUGA 0xa +#define ixDCIO_DEBUGB 0xb +#define ixDCIO_DEBUGC 0xc +#define ixDCIO_DEBUGD 0xd +#define ixDCIO_DEBUGE 0xe +#define ixDCIO_DEBUGF 0xf +#define ixDCIO_DEBUG10 0x10 +#define ixDCIO_DEBUG11 0x11 +#define ixDCIO_DEBUG12 0x12 +#define ixDCIO_DEBUG13 0x13 +#define ixDCIO_DEBUG14 0x14 +#define ixDCIO_DEBUG15 0x15 +#define ixDCIO_DEBUG16 0x16 +#define ixDCIO_DEBUG17 0x17 +#define ixDCIO_DEBUG18 0x18 +#define ixDCIO_DEBUG19 0x19 +#define ixDCIO_DEBUG1A 0x1a +#define ixDCIO_DEBUG1B 0x1b +#define ixDCIO_DEBUG_ID 0x0 +#define mmDC_GPIO_GENERIC_MASK 0x4860 +#define mmDC_GPIO_GENERIC_A 0x4861 +#define mmDC_GPIO_GENERIC_EN 0x4862 +#define mmDC_GPIO_GENERIC_Y 0x4863 +#define mmDC_GPIO_DVODATA_MASK 0x4864 +#define mmDC_GPIO_DVODATA_A 0x4865 +#define mmDC_GPIO_DVODATA_EN 0x4866 +#define mmDC_GPIO_DVODATA_Y 0x4867 +#define mmDC_GPIO_DDC1_MASK 0x4868 +#define mmDC_GPIO_DDC1_A 0x4869 +#define mmDC_GPIO_DDC1_EN 0x486a +#define mmDC_GPIO_DDC1_Y 0x486b +#define mmDC_GPIO_DDC2_MASK 0x486c +#define mmDC_GPIO_DDC2_A 0x486d +#define mmDC_GPIO_DDC2_EN 0x486e +#define mmDC_GPIO_DDC2_Y 0x486f +#define mmDC_GPIO_DDC3_MASK 0x4870 +#define mmDC_GPIO_DDC3_A 0x4871 +#define mmDC_GPIO_DDC3_EN 0x4872 +#define mmDC_GPIO_DDC3_Y 0x4873 +#define mmDC_GPIO_DDC4_MASK 0x4874 +#define mmDC_GPIO_DDC4_A 0x4875 +#define mmDC_GPIO_DDC4_EN 0x4876 +#define mmDC_GPIO_DDC4_Y 0x4877 +#define mmDC_GPIO_DDC5_MASK 0x4878 +#define mmDC_GPIO_DDC5_A 0x4879 +#define mmDC_GPIO_DDC5_EN 0x487a +#define mmDC_GPIO_DDC5_Y 0x487b +#define mmDC_GPIO_DDC6_MASK 0x487c +#define mmDC_GPIO_DDC6_A 0x487d +#define mmDC_GPIO_DDC6_EN 0x487e +#define mmDC_GPIO_DDC6_Y 0x487f +#define mmDC_GPIO_DDCVGA_MASK 0x4880 +#define mmDC_GPIO_DDCVGA_A 0x4881 +#define mmDC_GPIO_DDCVGA_EN 0x4882 +#define mmDC_GPIO_DDCVGA_Y 0x4883 +#define mmDC_GPIO_SYNCA_MASK 0x4884 +#define mmDC_GPIO_SYNCA_A 0x4885 +#define mmDC_GPIO_SYNCA_EN 0x4886 +#define mmDC_GPIO_SYNCA_Y 0x4887 +#define mmDC_GPIO_GENLK_MASK 0x4888 +#define mmDC_GPIO_GENLK_A 0x4889 +#define mmDC_GPIO_GENLK_EN 0x488a +#define mmDC_GPIO_GENLK_Y 0x488b +#define mmDC_GPIO_HPD_MASK 0x488c +#define mmDC_GPIO_HPD_A 0x488d +#define mmDC_GPIO_HPD_EN 0x488e +#define mmDC_GPIO_HPD_Y 0x488f +#define mmDC_GPIO_PWRSEQ_MASK 0x4890 +#define mmDC_GPIO_PWRSEQ_A 0x4891 +#define mmDC_GPIO_PWRSEQ_EN 0x4892 +#define mmDC_GPIO_PWRSEQ_Y 0x4893 +#define mmDC_GPIO_PAD_STRENGTH_1 0x4894 +#define mmDC_GPIO_PAD_STRENGTH_2 0x4895 +#define mmPHY_AUX_CNTL 0x4897 +#define mmDC_GPIO_I2CPAD_MASK 0x4898 +#define mmDC_GPIO_I2CPAD_A 0x4899 +#define mmDC_GPIO_I2CPAD_EN 0x489a +#define mmDC_GPIO_I2CPAD_Y 0x489b +#define mmDC_GPIO_I2CPAD_STRENGTH 0x489c +#define mmDVO_VREF_CONTROL 0x489e +#define mmDVO_SKEW_ADJUST 0x489f +#define mmDAC_MACRO_CNTL_RESERVED0 0x48b8 +#define mmDAC_MACRO_CNTL_RESERVED1 0x48b9 +#define mmDAC_MACRO_CNTL_RESERVED2 0x48ba +#define mmDAC_MACRO_CNTL_RESERVED3 0x48bb +#define mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0 0x49c0 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x49e0 +#define mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1 0x49c1 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x49e1 +#define mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2 0x49c2 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x49e2 +#define mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3 0x49c3 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x49e3 +#define mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4 0x49c4 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x49e4 +#define mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5 0x49c5 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x49e5 +#define mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6 0x49c6 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x49e6 +#define mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7 0x49c7 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x49e7 +#define mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8 0x49c8 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x49e8 +#define mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9 0x49c9 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x49e9 +#define mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10 0x49ca +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x49ea +#define mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11 0x49cb +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x49eb +#define mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12 0x49cc +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x49ec +#define mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13 0x49cd +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x49ed +#define mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14 0x49ce +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x49ee +#define mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15 0x49cf +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x49ef +#define mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16 0x49d0 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x49f0 +#define mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17 0x49d1 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x49f1 +#define mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18 0x49d2 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x49f2 +#define mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19 0x49d3 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x49f3 +#define mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20 0x49d4 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x49f4 +#define mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21 0x49d5 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x49f5 +#define mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22 0x49d6 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x49f6 +#define mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23 0x49d7 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x49f7 +#define mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24 0x49d8 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x49f8 +#define mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9 +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9 +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9 +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919 +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939 +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959 +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979 +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999 +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25 0x49d9 +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x49f9 +#define mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26 0x49da +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x49fa +#define mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27 0x49db +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x49fb +#define mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28 0x49dc +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x49fc +#define mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29 0x49dd +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x49fd +#define mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30 0x49de +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x49fe +#define mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df +#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df +#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff +#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f +#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f +#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f +#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f +#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f +#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31 0x49df +#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x49ff +#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab +#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac +#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad +#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae +#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba +#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca +#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace +#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada +#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add +#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade +#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea +#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec +#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed +#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee +#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef +#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff +#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a +#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b +#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c +#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d +#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e +#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f +#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab +#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac +#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad +#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae +#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba +#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca +#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce +#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda +#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde +#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf +#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea +#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec +#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed +#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee +#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef +#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9 +#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa +#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb +#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc +#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd +#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe +#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff +#define mmDPHY_MACRO_CNTL_RESERVED0 0x5d98 +#define mmDPHY_MACRO_CNTL_RESERVED1 0x5d99 +#define mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a +#define mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b +#define mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c +#define mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d +#define mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e +#define mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f +#define mmDPHY_MACRO_CNTL_RESERVED8 0x5da0 +#define mmDPHY_MACRO_CNTL_RESERVED9 0x5da1 +#define mmDPHY_MACRO_CNTL_RESERVED10 0x5da2 +#define mmDPHY_MACRO_CNTL_RESERVED11 0x5da3 +#define mmDPHY_MACRO_CNTL_RESERVED12 0x5da4 +#define mmDPHY_MACRO_CNTL_RESERVED13 0x5da5 +#define mmDPHY_MACRO_CNTL_RESERVED14 0x5da6 +#define mmDPHY_MACRO_CNTL_RESERVED15 0x5da7 +#define mmDPHY_MACRO_CNTL_RESERVED16 0x5da8 +#define mmDPHY_MACRO_CNTL_RESERVED17 0x5da9 +#define mmDPHY_MACRO_CNTL_RESERVED18 0x5daa +#define mmDPHY_MACRO_CNTL_RESERVED19 0x5dab +#define mmDPHY_MACRO_CNTL_RESERVED20 0x5dac +#define mmDPHY_MACRO_CNTL_RESERVED21 0x5dad +#define mmDPHY_MACRO_CNTL_RESERVED22 0x5dae +#define mmDPHY_MACRO_CNTL_RESERVED23 0x5daf +#define mmDPHY_MACRO_CNTL_RESERVED24 0x5db0 +#define mmDPHY_MACRO_CNTL_RESERVED25 0x5db1 +#define mmDPHY_MACRO_CNTL_RESERVED26 0x5db2 +#define mmDPHY_MACRO_CNTL_RESERVED27 0x5db3 +#define mmDPHY_MACRO_CNTL_RESERVED28 0x5db4 +#define mmDPHY_MACRO_CNTL_RESERVED29 0x5db5 +#define mmDPHY_MACRO_CNTL_RESERVED30 0x5db6 +#define mmDPHY_MACRO_CNTL_RESERVED31 0x5db7 +#define mmDPHY_MACRO_CNTL_RESERVED32 0x5db8 +#define mmDPHY_MACRO_CNTL_RESERVED33 0x5db9 +#define mmDPHY_MACRO_CNTL_RESERVED34 0x5dba +#define mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb +#define mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc +#define mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd +#define mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe +#define mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf +#define mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0 +#define mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1 +#define mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2 +#define mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3 +#define mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4 +#define mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5 +#define mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6 +#define mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7 +#define mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8 +#define mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9 +#define mmDPHY_MACRO_CNTL_RESERVED50 0x5dca +#define mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb +#define mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc +#define mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd +#define mmDPHY_MACRO_CNTL_RESERVED54 0x5dce +#define mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf +#define mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0 +#define mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1 +#define mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2 +#define mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3 +#define mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4 +#define mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5 +#define mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6 +#define mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7 +#define mmGRPH_ENABLE 0x1a00 +#define mmDCP0_GRPH_ENABLE 0x1a00 +#define mmDCP1_GRPH_ENABLE 0x1c00 +#define mmDCP2_GRPH_ENABLE 0x1e00 +#define mmDCP3_GRPH_ENABLE 0x4000 +#define mmDCP4_GRPH_ENABLE 0x4200 +#define mmDCP5_GRPH_ENABLE 0x4400 +#define mmGRPH_CONTROL 0x1a01 +#define mmDCP0_GRPH_CONTROL 0x1a01 +#define mmDCP1_GRPH_CONTROL 0x1c01 +#define mmDCP2_GRPH_CONTROL 0x1e01 +#define mmDCP3_GRPH_CONTROL 0x4001 +#define mmDCP4_GRPH_CONTROL 0x4201 +#define mmDCP5_GRPH_CONTROL 0x4401 +#define mmGRPH_LUT_10BIT_BYPASS 0x1a02 +#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 +#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02 +#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02 +#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002 +#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202 +#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402 +#define mmGRPH_SWAP_CNTL 0x1a03 +#define mmDCP0_GRPH_SWAP_CNTL 0x1a03 +#define mmDCP1_GRPH_SWAP_CNTL 0x1c03 +#define mmDCP2_GRPH_SWAP_CNTL 0x1e03 +#define mmDCP3_GRPH_SWAP_CNTL 0x4003 +#define mmDCP4_GRPH_SWAP_CNTL 0x4203 +#define mmDCP5_GRPH_SWAP_CNTL 0x4403 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405 +#define mmGRPH_PITCH 0x1a06 +#define mmDCP0_GRPH_PITCH 0x1a06 +#define mmDCP1_GRPH_PITCH 0x1c06 +#define mmDCP2_GRPH_PITCH 0x1e06 +#define mmDCP3_GRPH_PITCH 0x4006 +#define mmDCP4_GRPH_PITCH 0x4206 +#define mmDCP5_GRPH_PITCH 0x4406 +#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 +#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07 +#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07 +#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 +#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207 +#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407 +#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 +#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08 +#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08 +#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 +#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208 +#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408 +#define mmGRPH_SURFACE_OFFSET_X 0x1a09 +#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 +#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09 +#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09 +#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009 +#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209 +#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409 +#define mmGRPH_SURFACE_OFFSET_Y 0x1a0a +#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a +#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a +#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a +#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a +#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a +#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a +#define mmGRPH_X_START 0x1a0b +#define mmDCP0_GRPH_X_START 0x1a0b +#define mmDCP1_GRPH_X_START 0x1c0b +#define mmDCP2_GRPH_X_START 0x1e0b +#define mmDCP3_GRPH_X_START 0x400b +#define mmDCP4_GRPH_X_START 0x420b +#define mmDCP5_GRPH_X_START 0x440b +#define mmGRPH_Y_START 0x1a0c +#define mmDCP0_GRPH_Y_START 0x1a0c +#define mmDCP1_GRPH_Y_START 0x1c0c +#define mmDCP2_GRPH_Y_START 0x1e0c +#define mmDCP3_GRPH_Y_START 0x400c +#define mmDCP4_GRPH_Y_START 0x420c +#define mmDCP5_GRPH_Y_START 0x440c +#define mmGRPH_X_END 0x1a0d +#define mmDCP0_GRPH_X_END 0x1a0d +#define mmDCP1_GRPH_X_END 0x1c0d +#define mmDCP2_GRPH_X_END 0x1e0d +#define mmDCP3_GRPH_X_END 0x400d +#define mmDCP4_GRPH_X_END 0x420d +#define mmDCP5_GRPH_X_END 0x440d +#define mmGRPH_Y_END 0x1a0e +#define mmDCP0_GRPH_Y_END 0x1a0e +#define mmDCP1_GRPH_Y_END 0x1c0e +#define mmDCP2_GRPH_Y_END 0x1e0e +#define mmDCP3_GRPH_Y_END 0x400e +#define mmDCP4_GRPH_Y_END 0x420e +#define mmDCP5_GRPH_Y_END 0x440e +#define mmINPUT_GAMMA_CONTROL 0x1a10 +#define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 +#define mmDCP1_INPUT_GAMMA_CONTROL 0x1c10 +#define mmDCP2_INPUT_GAMMA_CONTROL 0x1e10 +#define mmDCP3_INPUT_GAMMA_CONTROL 0x4010 +#define mmDCP4_INPUT_GAMMA_CONTROL 0x4210 +#define mmDCP5_INPUT_GAMMA_CONTROL 0x4410 +#define mmGRPH_UPDATE 0x1a11 +#define mmDCP0_GRPH_UPDATE 0x1a11 +#define mmDCP1_GRPH_UPDATE 0x1c11 +#define mmDCP2_GRPH_UPDATE 0x1e11 +#define mmDCP3_GRPH_UPDATE 0x4011 +#define mmDCP4_GRPH_UPDATE 0x4211 +#define mmDCP5_GRPH_UPDATE 0x4411 +#define mmGRPH_FLIP_CONTROL 0x1a12 +#define mmDCP0_GRPH_FLIP_CONTROL 0x1a12 +#define mmDCP1_GRPH_FLIP_CONTROL 0x1c12 +#define mmDCP2_GRPH_FLIP_CONTROL 0x1e12 +#define mmDCP3_GRPH_FLIP_CONTROL 0x4012 +#define mmDCP4_GRPH_FLIP_CONTROL 0x4212 +#define mmDCP5_GRPH_FLIP_CONTROL 0x4412 +#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 +#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13 +#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13 +#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013 +#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213 +#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413 +#define mmGRPH_DFQ_CONTROL 0x1a14 +#define mmDCP0_GRPH_DFQ_CONTROL 0x1a14 +#define mmDCP1_GRPH_DFQ_CONTROL 0x1c14 +#define mmDCP2_GRPH_DFQ_CONTROL 0x1e14 +#define mmDCP3_GRPH_DFQ_CONTROL 0x4014 +#define mmDCP4_GRPH_DFQ_CONTROL 0x4214 +#define mmDCP5_GRPH_DFQ_CONTROL 0x4414 +#define mmGRPH_DFQ_STATUS 0x1a15 +#define mmDCP0_GRPH_DFQ_STATUS 0x1a15 +#define mmDCP1_GRPH_DFQ_STATUS 0x1c15 +#define mmDCP2_GRPH_DFQ_STATUS 0x1e15 +#define mmDCP3_GRPH_DFQ_STATUS 0x4015 +#define mmDCP4_GRPH_DFQ_STATUS 0x4215 +#define mmDCP5_GRPH_DFQ_STATUS 0x4415 +#define mmGRPH_INTERRUPT_STATUS 0x1a16 +#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 +#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16 +#define mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16 +#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4016 +#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4216 +#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4416 +#define mmGRPH_INTERRUPT_CONTROL 0x1a17 +#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 +#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17 +#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17 +#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017 +#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217 +#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417 +#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 +#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18 +#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18 +#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 +#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218 +#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418 +#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19 +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19 +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219 +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419 +#define mmGRPH_COMPRESS_PITCH 0x1a1a +#define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a +#define mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a +#define mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a +#define mmDCP3_GRPH_COMPRESS_PITCH 0x401a +#define mmDCP4_GRPH_COMPRESS_PITCH 0x421a +#define mmDCP5_GRPH_COMPRESS_PITCH 0x441a +#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b +#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b +#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b +#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b +#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b +#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b +#define mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c +#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c +#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1c1c +#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1e1c +#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x401c +#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x421c +#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x441c +#define mmPRESCALE_GRPH_CONTROL 0x1a2d +#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d +#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d +#define mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d +#define mmDCP3_PRESCALE_GRPH_CONTROL 0x402d +#define mmDCP4_PRESCALE_GRPH_CONTROL 0x422d +#define mmDCP5_PRESCALE_GRPH_CONTROL 0x442d +#define mmPRESCALE_VALUES_GRPH_R 0x1a2e +#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e +#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e +#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e +#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e +#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e +#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e +#define mmPRESCALE_VALUES_GRPH_G 0x1a2f +#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f +#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f +#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f +#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f +#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f +#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f +#define mmPRESCALE_VALUES_GRPH_B 0x1a30 +#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 +#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30 +#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30 +#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030 +#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230 +#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430 +#define mmINPUT_CSC_CONTROL 0x1a35 +#define mmDCP0_INPUT_CSC_CONTROL 0x1a35 +#define mmDCP1_INPUT_CSC_CONTROL 0x1c35 +#define mmDCP2_INPUT_CSC_CONTROL 0x1e35 +#define mmDCP3_INPUT_CSC_CONTROL 0x4035 +#define mmDCP4_INPUT_CSC_CONTROL 0x4235 +#define mmDCP5_INPUT_CSC_CONTROL 0x4435 +#define mmINPUT_CSC_C11_C12 0x1a36 +#define mmDCP0_INPUT_CSC_C11_C12 0x1a36 +#define mmDCP1_INPUT_CSC_C11_C12 0x1c36 +#define mmDCP2_INPUT_CSC_C11_C12 0x1e36 +#define mmDCP3_INPUT_CSC_C11_C12 0x4036 +#define mmDCP4_INPUT_CSC_C11_C12 0x4236 +#define mmDCP5_INPUT_CSC_C11_C12 0x4436 +#define mmINPUT_CSC_C13_C14 0x1a37 +#define mmDCP0_INPUT_CSC_C13_C14 0x1a37 +#define mmDCP1_INPUT_CSC_C13_C14 0x1c37 +#define mmDCP2_INPUT_CSC_C13_C14 0x1e37 +#define mmDCP3_INPUT_CSC_C13_C14 0x4037 +#define mmDCP4_INPUT_CSC_C13_C14 0x4237 +#define mmDCP5_INPUT_CSC_C13_C14 0x4437 +#define mmINPUT_CSC_C21_C22 0x1a38 +#define mmDCP0_INPUT_CSC_C21_C22 0x1a38 +#define mmDCP1_INPUT_CSC_C21_C22 0x1c38 +#define mmDCP2_INPUT_CSC_C21_C22 0x1e38 +#define mmDCP3_INPUT_CSC_C21_C22 0x4038 +#define mmDCP4_INPUT_CSC_C21_C22 0x4238 +#define mmDCP5_INPUT_CSC_C21_C22 0x4438 +#define mmINPUT_CSC_C23_C24 0x1a39 +#define mmDCP0_INPUT_CSC_C23_C24 0x1a39 +#define mmDCP1_INPUT_CSC_C23_C24 0x1c39 +#define mmDCP2_INPUT_CSC_C23_C24 0x1e39 +#define mmDCP3_INPUT_CSC_C23_C24 0x4039 +#define mmDCP4_INPUT_CSC_C23_C24 0x4239 +#define mmDCP5_INPUT_CSC_C23_C24 0x4439 +#define mmINPUT_CSC_C31_C32 0x1a3a +#define mmDCP0_INPUT_CSC_C31_C32 0x1a3a +#define mmDCP1_INPUT_CSC_C31_C32 0x1c3a +#define mmDCP2_INPUT_CSC_C31_C32 0x1e3a +#define mmDCP3_INPUT_CSC_C31_C32 0x403a +#define mmDCP4_INPUT_CSC_C31_C32 0x423a +#define mmDCP5_INPUT_CSC_C31_C32 0x443a +#define mmINPUT_CSC_C33_C34 0x1a3b +#define mmDCP0_INPUT_CSC_C33_C34 0x1a3b +#define mmDCP1_INPUT_CSC_C33_C34 0x1c3b +#define mmDCP2_INPUT_CSC_C33_C34 0x1e3b +#define mmDCP3_INPUT_CSC_C33_C34 0x403b +#define mmDCP4_INPUT_CSC_C33_C34 0x423b +#define mmDCP5_INPUT_CSC_C33_C34 0x443b +#define mmOUTPUT_CSC_CONTROL 0x1a3c +#define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c +#define mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c +#define mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c +#define mmDCP3_OUTPUT_CSC_CONTROL 0x403c +#define mmDCP4_OUTPUT_CSC_CONTROL 0x423c +#define mmDCP5_OUTPUT_CSC_CONTROL 0x443c +#define mmOUTPUT_CSC_C11_C12 0x1a3d +#define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d +#define mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d +#define mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d +#define mmDCP3_OUTPUT_CSC_C11_C12 0x403d +#define mmDCP4_OUTPUT_CSC_C11_C12 0x423d +#define mmDCP5_OUTPUT_CSC_C11_C12 0x443d +#define mmOUTPUT_CSC_C13_C14 0x1a3e +#define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e +#define mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e +#define mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e +#define mmDCP3_OUTPUT_CSC_C13_C14 0x403e +#define mmDCP4_OUTPUT_CSC_C13_C14 0x423e +#define mmDCP5_OUTPUT_CSC_C13_C14 0x443e +#define mmOUTPUT_CSC_C21_C22 0x1a3f +#define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f +#define mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f +#define mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f +#define mmDCP3_OUTPUT_CSC_C21_C22 0x403f +#define mmDCP4_OUTPUT_CSC_C21_C22 0x423f +#define mmDCP5_OUTPUT_CSC_C21_C22 0x443f +#define mmOUTPUT_CSC_C23_C24 0x1a40 +#define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 +#define mmDCP1_OUTPUT_CSC_C23_C24 0x1c40 +#define mmDCP2_OUTPUT_CSC_C23_C24 0x1e40 +#define mmDCP3_OUTPUT_CSC_C23_C24 0x4040 +#define mmDCP4_OUTPUT_CSC_C23_C24 0x4240 +#define mmDCP5_OUTPUT_CSC_C23_C24 0x4440 +#define mmOUTPUT_CSC_C31_C32 0x1a41 +#define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 +#define mmDCP1_OUTPUT_CSC_C31_C32 0x1c41 +#define mmDCP2_OUTPUT_CSC_C31_C32 0x1e41 +#define mmDCP3_OUTPUT_CSC_C31_C32 0x4041 +#define mmDCP4_OUTPUT_CSC_C31_C32 0x4241 +#define mmDCP5_OUTPUT_CSC_C31_C32 0x4441 +#define mmOUTPUT_CSC_C33_C34 0x1a42 +#define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 +#define mmDCP1_OUTPUT_CSC_C33_C34 0x1c42 +#define mmDCP2_OUTPUT_CSC_C33_C34 0x1e42 +#define mmDCP3_OUTPUT_CSC_C33_C34 0x4042 +#define mmDCP4_OUTPUT_CSC_C33_C34 0x4242 +#define mmDCP5_OUTPUT_CSC_C33_C34 0x4442 +#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 +#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43 +#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43 +#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043 +#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243 +#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443 +#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 +#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44 +#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44 +#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044 +#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244 +#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444 +#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 +#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45 +#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45 +#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045 +#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245 +#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445 +#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 +#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46 +#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46 +#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046 +#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246 +#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446 +#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 +#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47 +#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47 +#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047 +#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247 +#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447 +#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 +#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48 +#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48 +#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048 +#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248 +#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448 +#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 +#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49 +#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49 +#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049 +#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249 +#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449 +#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a +#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a +#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a +#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a +#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a +#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a +#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b +#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b +#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b +#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b +#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b +#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b +#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c +#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c +#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c +#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c +#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c +#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c +#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d +#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d +#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d +#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d +#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d +#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d +#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e +#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e +#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e +#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e +#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e +#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e +#define mmDENORM_CONTROL 0x1a50 +#define mmDCP0_DENORM_CONTROL 0x1a50 +#define mmDCP1_DENORM_CONTROL 0x1c50 +#define mmDCP2_DENORM_CONTROL 0x1e50 +#define mmDCP3_DENORM_CONTROL 0x4050 +#define mmDCP4_DENORM_CONTROL 0x4250 +#define mmDCP5_DENORM_CONTROL 0x4450 +#define mmOUT_ROUND_CONTROL 0x1a51 +#define mmDCP0_OUT_ROUND_CONTROL 0x1a51 +#define mmDCP1_OUT_ROUND_CONTROL 0x1c51 +#define mmDCP2_OUT_ROUND_CONTROL 0x1e51 +#define mmDCP3_OUT_ROUND_CONTROL 0x4051 +#define mmDCP4_OUT_ROUND_CONTROL 0x4251 +#define mmDCP5_OUT_ROUND_CONTROL 0x4451 +#define mmOUT_CLAMP_CONTROL_R_CR 0x1a52 +#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 +#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52 +#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52 +#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052 +#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252 +#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452 +#define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c +#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c +#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c +#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c +#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c +#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c +#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c +#define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d +#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d +#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d +#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d +#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d +#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d +#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d +#define mmKEY_CONTROL 0x1a53 +#define mmDCP0_KEY_CONTROL 0x1a53 +#define mmDCP1_KEY_CONTROL 0x1c53 +#define mmDCP2_KEY_CONTROL 0x1e53 +#define mmDCP3_KEY_CONTROL 0x4053 +#define mmDCP4_KEY_CONTROL 0x4253 +#define mmDCP5_KEY_CONTROL 0x4453 +#define mmKEY_RANGE_ALPHA 0x1a54 +#define mmDCP0_KEY_RANGE_ALPHA 0x1a54 +#define mmDCP1_KEY_RANGE_ALPHA 0x1c54 +#define mmDCP2_KEY_RANGE_ALPHA 0x1e54 +#define mmDCP3_KEY_RANGE_ALPHA 0x4054 +#define mmDCP4_KEY_RANGE_ALPHA 0x4254 +#define mmDCP5_KEY_RANGE_ALPHA 0x4454 +#define mmKEY_RANGE_RED 0x1a55 +#define mmDCP0_KEY_RANGE_RED 0x1a55 +#define mmDCP1_KEY_RANGE_RED 0x1c55 +#define mmDCP2_KEY_RANGE_RED 0x1e55 +#define mmDCP3_KEY_RANGE_RED 0x4055 +#define mmDCP4_KEY_RANGE_RED 0x4255 +#define mmDCP5_KEY_RANGE_RED 0x4455 +#define mmKEY_RANGE_GREEN 0x1a56 +#define mmDCP0_KEY_RANGE_GREEN 0x1a56 +#define mmDCP1_KEY_RANGE_GREEN 0x1c56 +#define mmDCP2_KEY_RANGE_GREEN 0x1e56 +#define mmDCP3_KEY_RANGE_GREEN 0x4056 +#define mmDCP4_KEY_RANGE_GREEN 0x4256 +#define mmDCP5_KEY_RANGE_GREEN 0x4456 +#define mmKEY_RANGE_BLUE 0x1a57 +#define mmDCP0_KEY_RANGE_BLUE 0x1a57 +#define mmDCP1_KEY_RANGE_BLUE 0x1c57 +#define mmDCP2_KEY_RANGE_BLUE 0x1e57 +#define mmDCP3_KEY_RANGE_BLUE 0x4057 +#define mmDCP4_KEY_RANGE_BLUE 0x4257 +#define mmDCP5_KEY_RANGE_BLUE 0x4457 +#define mmDEGAMMA_CONTROL 0x1a58 +#define mmDCP0_DEGAMMA_CONTROL 0x1a58 +#define mmDCP1_DEGAMMA_CONTROL 0x1c58 +#define mmDCP2_DEGAMMA_CONTROL 0x1e58 +#define mmDCP3_DEGAMMA_CONTROL 0x4058 +#define mmDCP4_DEGAMMA_CONTROL 0x4258 +#define mmDCP5_DEGAMMA_CONTROL 0x4458 +#define mmGAMUT_REMAP_CONTROL 0x1a59 +#define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 +#define mmDCP1_GAMUT_REMAP_CONTROL 0x1c59 +#define mmDCP2_GAMUT_REMAP_CONTROL 0x1e59 +#define mmDCP3_GAMUT_REMAP_CONTROL 0x4059 +#define mmDCP4_GAMUT_REMAP_CONTROL 0x4259 +#define mmDCP5_GAMUT_REMAP_CONTROL 0x4459 +#define mmGAMUT_REMAP_C11_C12 0x1a5a +#define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a +#define mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a +#define mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a +#define mmDCP3_GAMUT_REMAP_C11_C12 0x405a +#define mmDCP4_GAMUT_REMAP_C11_C12 0x425a +#define mmDCP5_GAMUT_REMAP_C11_C12 0x445a +#define mmGAMUT_REMAP_C13_C14 0x1a5b +#define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b +#define mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b +#define mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b +#define mmDCP3_GAMUT_REMAP_C13_C14 0x405b +#define mmDCP4_GAMUT_REMAP_C13_C14 0x425b +#define mmDCP5_GAMUT_REMAP_C13_C14 0x445b +#define mmGAMUT_REMAP_C21_C22 0x1a5c +#define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c +#define mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c +#define mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c +#define mmDCP3_GAMUT_REMAP_C21_C22 0x405c +#define mmDCP4_GAMUT_REMAP_C21_C22 0x425c +#define mmDCP5_GAMUT_REMAP_C21_C22 0x445c +#define mmGAMUT_REMAP_C23_C24 0x1a5d +#define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d +#define mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d +#define mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d +#define mmDCP3_GAMUT_REMAP_C23_C24 0x405d +#define mmDCP4_GAMUT_REMAP_C23_C24 0x425d +#define mmDCP5_GAMUT_REMAP_C23_C24 0x445d +#define mmGAMUT_REMAP_C31_C32 0x1a5e +#define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e +#define mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e +#define mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e +#define mmDCP3_GAMUT_REMAP_C31_C32 0x405e +#define mmDCP4_GAMUT_REMAP_C31_C32 0x425e +#define mmDCP5_GAMUT_REMAP_C31_C32 0x445e +#define mmGAMUT_REMAP_C33_C34 0x1a5f +#define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f +#define mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f +#define mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f +#define mmDCP3_GAMUT_REMAP_C33_C34 0x405f +#define mmDCP4_GAMUT_REMAP_C33_C34 0x425f +#define mmDCP5_GAMUT_REMAP_C33_C34 0x445f +#define mmDCP_SPATIAL_DITHER_CNTL 0x1a60 +#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 +#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60 +#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60 +#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060 +#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260 +#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460 +#define mmDCP_FP_CONVERTED_FIELD 0x1a65 +#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 +#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65 +#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65 +#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065 +#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265 +#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465 +#define mmCUR_CONTROL 0x1a66 +#define mmDCP0_CUR_CONTROL 0x1a66 +#define mmDCP1_CUR_CONTROL 0x1c66 +#define mmDCP2_CUR_CONTROL 0x1e66 +#define mmDCP3_CUR_CONTROL 0x4066 +#define mmDCP4_CUR_CONTROL 0x4266 +#define mmDCP5_CUR_CONTROL 0x4466 +#define mmCUR_SURFACE_ADDRESS 0x1a67 +#define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 +#define mmDCP1_CUR_SURFACE_ADDRESS 0x1c67 +#define mmDCP2_CUR_SURFACE_ADDRESS 0x1e67 +#define mmDCP3_CUR_SURFACE_ADDRESS 0x4067 +#define mmDCP4_CUR_SURFACE_ADDRESS 0x4267 +#define mmDCP5_CUR_SURFACE_ADDRESS 0x4467 +#define mmCUR_SIZE 0x1a68 +#define mmDCP0_CUR_SIZE 0x1a68 +#define mmDCP1_CUR_SIZE 0x1c68 +#define mmDCP2_CUR_SIZE 0x1e68 +#define mmDCP3_CUR_SIZE 0x4068 +#define mmDCP4_CUR_SIZE 0x4268 +#define mmDCP5_CUR_SIZE 0x4468 +#define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 +#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69 +#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69 +#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069 +#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269 +#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469 +#define mmCUR_POSITION 0x1a6a +#define mmDCP0_CUR_POSITION 0x1a6a +#define mmDCP1_CUR_POSITION 0x1c6a +#define mmDCP2_CUR_POSITION 0x1e6a +#define mmDCP3_CUR_POSITION 0x406a +#define mmDCP4_CUR_POSITION 0x426a +#define mmDCP5_CUR_POSITION 0x446a +#define mmCUR_HOT_SPOT 0x1a6b +#define mmDCP0_CUR_HOT_SPOT 0x1a6b +#define mmDCP1_CUR_HOT_SPOT 0x1c6b +#define mmDCP2_CUR_HOT_SPOT 0x1e6b +#define mmDCP3_CUR_HOT_SPOT 0x406b +#define mmDCP4_CUR_HOT_SPOT 0x426b +#define mmDCP5_CUR_HOT_SPOT 0x446b +#define mmCUR_COLOR1 0x1a6c +#define mmDCP0_CUR_COLOR1 0x1a6c +#define mmDCP1_CUR_COLOR1 0x1c6c +#define mmDCP2_CUR_COLOR1 0x1e6c +#define mmDCP3_CUR_COLOR1 0x406c +#define mmDCP4_CUR_COLOR1 0x426c +#define mmDCP5_CUR_COLOR1 0x446c +#define mmCUR_COLOR2 0x1a6d +#define mmDCP0_CUR_COLOR2 0x1a6d +#define mmDCP1_CUR_COLOR2 0x1c6d +#define mmDCP2_CUR_COLOR2 0x1e6d +#define mmDCP3_CUR_COLOR2 0x406d +#define mmDCP4_CUR_COLOR2 0x426d +#define mmDCP5_CUR_COLOR2 0x446d +#define mmCUR_UPDATE 0x1a6e +#define mmDCP0_CUR_UPDATE 0x1a6e +#define mmDCP1_CUR_UPDATE 0x1c6e +#define mmDCP2_CUR_UPDATE 0x1e6e +#define mmDCP3_CUR_UPDATE 0x406e +#define mmDCP4_CUR_UPDATE 0x426e +#define mmDCP5_CUR_UPDATE 0x446e +#define mmCUR_REQUEST_FILTER_CNTL 0x1a99 +#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 +#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99 +#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99 +#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099 +#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299 +#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499 +#define mmCUR_STEREO_CONTROL 0x1a9a +#define mmDCP0_CUR_STEREO_CONTROL 0x1a9a +#define mmDCP1_CUR_STEREO_CONTROL 0x1c9a +#define mmDCP2_CUR_STEREO_CONTROL 0x1e9a +#define mmDCP3_CUR_STEREO_CONTROL 0x409a +#define mmDCP4_CUR_STEREO_CONTROL 0x429a +#define mmDCP5_CUR_STEREO_CONTROL 0x449a +#define mmDC_LUT_RW_MODE 0x1a78 +#define mmDCP0_DC_LUT_RW_MODE 0x1a78 +#define mmDCP1_DC_LUT_RW_MODE 0x1c78 +#define mmDCP2_DC_LUT_RW_MODE 0x1e78 +#define mmDCP3_DC_LUT_RW_MODE 0x4078 +#define mmDCP4_DC_LUT_RW_MODE 0x4278 +#define mmDCP5_DC_LUT_RW_MODE 0x4478 +#define mmDC_LUT_RW_INDEX 0x1a79 +#define mmDCP0_DC_LUT_RW_INDEX 0x1a79 +#define mmDCP1_DC_LUT_RW_INDEX 0x1c79 +#define mmDCP2_DC_LUT_RW_INDEX 0x1e79 +#define mmDCP3_DC_LUT_RW_INDEX 0x4079 +#define mmDCP4_DC_LUT_RW_INDEX 0x4279 +#define mmDCP5_DC_LUT_RW_INDEX 0x4479 +#define mmDC_LUT_SEQ_COLOR 0x1a7a +#define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a +#define mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a +#define mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a +#define mmDCP3_DC_LUT_SEQ_COLOR 0x407a +#define mmDCP4_DC_LUT_SEQ_COLOR 0x427a +#define mmDCP5_DC_LUT_SEQ_COLOR 0x447a +#define mmDC_LUT_PWL_DATA 0x1a7b +#define mmDCP0_DC_LUT_PWL_DATA 0x1a7b +#define mmDCP1_DC_LUT_PWL_DATA 0x1c7b +#define mmDCP2_DC_LUT_PWL_DATA 0x1e7b +#define mmDCP3_DC_LUT_PWL_DATA 0x407b +#define mmDCP4_DC_LUT_PWL_DATA 0x427b +#define mmDCP5_DC_LUT_PWL_DATA 0x447b +#define mmDC_LUT_30_COLOR 0x1a7c +#define mmDCP0_DC_LUT_30_COLOR 0x1a7c +#define mmDCP1_DC_LUT_30_COLOR 0x1c7c +#define mmDCP2_DC_LUT_30_COLOR 0x1e7c +#define mmDCP3_DC_LUT_30_COLOR 0x407c +#define mmDCP4_DC_LUT_30_COLOR 0x427c +#define mmDCP5_DC_LUT_30_COLOR 0x447c +#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d +#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d +#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d +#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d +#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d +#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d +#define mmDC_LUT_WRITE_EN_MASK 0x1a7e +#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e +#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e +#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e +#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e +#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e +#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e +#define mmDC_LUT_AUTOFILL 0x1a7f +#define mmDCP0_DC_LUT_AUTOFILL 0x1a7f +#define mmDCP1_DC_LUT_AUTOFILL 0x1c7f +#define mmDCP2_DC_LUT_AUTOFILL 0x1e7f +#define mmDCP3_DC_LUT_AUTOFILL 0x407f +#define mmDCP4_DC_LUT_AUTOFILL 0x427f +#define mmDCP5_DC_LUT_AUTOFILL 0x447f +#define mmDC_LUT_CONTROL 0x1a80 +#define mmDCP0_DC_LUT_CONTROL 0x1a80 +#define mmDCP1_DC_LUT_CONTROL 0x1c80 +#define mmDCP2_DC_LUT_CONTROL 0x1e80 +#define mmDCP3_DC_LUT_CONTROL 0x4080 +#define mmDCP4_DC_LUT_CONTROL 0x4280 +#define mmDCP5_DC_LUT_CONTROL 0x4480 +#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 +#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81 +#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81 +#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081 +#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281 +#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481 +#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 +#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82 +#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82 +#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082 +#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282 +#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482 +#define mmDC_LUT_BLACK_OFFSET_RED 0x1a83 +#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 +#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83 +#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83 +#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083 +#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283 +#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483 +#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 +#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84 +#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84 +#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084 +#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284 +#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484 +#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 +#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85 +#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85 +#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085 +#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285 +#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485 +#define mmDC_LUT_WHITE_OFFSET_RED 0x1a86 +#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 +#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86 +#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86 +#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086 +#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286 +#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486 +#define mmDCP_CRC_CONTROL 0x1a87 +#define mmDCP0_DCP_CRC_CONTROL 0x1a87 +#define mmDCP1_DCP_CRC_CONTROL 0x1c87 +#define mmDCP2_DCP_CRC_CONTROL 0x1e87 +#define mmDCP3_DCP_CRC_CONTROL 0x4087 +#define mmDCP4_DCP_CRC_CONTROL 0x4287 +#define mmDCP5_DCP_CRC_CONTROL 0x4487 +#define mmDCP_CRC_MASK 0x1a88 +#define mmDCP0_DCP_CRC_MASK 0x1a88 +#define mmDCP1_DCP_CRC_MASK 0x1c88 +#define mmDCP2_DCP_CRC_MASK 0x1e88 +#define mmDCP3_DCP_CRC_MASK 0x4088 +#define mmDCP4_DCP_CRC_MASK 0x4288 +#define mmDCP5_DCP_CRC_MASK 0x4488 +#define mmDCP_CRC_CURRENT 0x1a89 +#define mmDCP0_DCP_CRC_CURRENT 0x1a89 +#define mmDCP1_DCP_CRC_CURRENT 0x1c89 +#define mmDCP2_DCP_CRC_CURRENT 0x1e89 +#define mmDCP3_DCP_CRC_CURRENT 0x4089 +#define mmDCP4_DCP_CRC_CURRENT 0x4289 +#define mmDCP5_DCP_CRC_CURRENT 0x4489 +#define mmDVMM_PTE_CONTROL 0x1a8a +#define mmDCP0_DVMM_PTE_CONTROL 0x1a8a +#define mmDCP1_DVMM_PTE_CONTROL 0x1c8a +#define mmDCP2_DVMM_PTE_CONTROL 0x1e8a +#define mmDCP3_DVMM_PTE_CONTROL 0x408a +#define mmDCP4_DVMM_PTE_CONTROL 0x428a +#define mmDCP5_DVMM_PTE_CONTROL 0x448a +#define mmDCP_CRC_LAST 0x1a8b +#define mmDCP0_DCP_CRC_LAST 0x1a8b +#define mmDCP1_DCP_CRC_LAST 0x1c8b +#define mmDCP2_DCP_CRC_LAST 0x1e8b +#define mmDCP3_DCP_CRC_LAST 0x408b +#define mmDCP4_DCP_CRC_LAST 0x428b +#define mmDCP5_DCP_CRC_LAST 0x448b +#define mmDVMM_PTE_ARB_CONTROL 0x1a8c +#define mmDCP0_DVMM_PTE_ARB_CONTROL 0x1a8c +#define mmDCP1_DVMM_PTE_ARB_CONTROL 0x1c8c +#define mmDCP2_DVMM_PTE_ARB_CONTROL 0x1e8c +#define mmDCP3_DVMM_PTE_ARB_CONTROL 0x408c +#define mmDCP4_DVMM_PTE_ARB_CONTROL 0x428c +#define mmDCP5_DVMM_PTE_ARB_CONTROL 0x448c +#define mmDCP_DEBUG 0x1a8d +#define mmDCP0_DCP_DEBUG 0x1a8d +#define mmDCP1_DCP_DEBUG 0x1c8d +#define mmDCP2_DCP_DEBUG 0x1e8d +#define mmDCP3_DCP_DEBUG 0x408d +#define mmDCP4_DCP_DEBUG 0x428d +#define mmDCP5_DCP_DEBUG 0x448d +#define mmGRPH_FLIP_RATE_CNTL 0x1a8e +#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e +#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e +#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e +#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e +#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e +#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e +#define mmDCP_GSL_CONTROL 0x1a90 +#define mmDCP0_DCP_GSL_CONTROL 0x1a90 +#define mmDCP1_DCP_GSL_CONTROL 0x1c90 +#define mmDCP2_DCP_GSL_CONTROL 0x1e90 +#define mmDCP3_DCP_GSL_CONTROL 0x4090 +#define mmDCP4_DCP_GSL_CONTROL 0x4290 +#define mmDCP5_DCP_GSL_CONTROL 0x4490 +#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 +#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91 +#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91 +#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 +#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291 +#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491 +#define mmDCP_DEBUG_SG 0x1a92 +#define mmDCP0_DCP_DEBUG_SG 0x1a92 +#define mmDCP1_DCP_DEBUG_SG 0x1c92 +#define mmDCP2_DCP_DEBUG_SG 0x1e92 +#define mmDCP3_DCP_DEBUG_SG 0x4092 +#define mmDCP4_DCP_DEBUG_SG 0x4292 +#define mmDCP5_DCP_DEBUG_SG 0x4492 +#define mmDCP_DEBUG_SG2 0x1a94 +#define mmDCP0_DCP_DEBUG_SG2 0x1a94 +#define mmDCP1_DCP_DEBUG_SG2 0x1c94 +#define mmDCP2_DCP_DEBUG_SG2 0x1e94 +#define mmDCP3_DCP_DEBUG_SG2 0x4094 +#define mmDCP4_DCP_DEBUG_SG2 0x4294 +#define mmDCP5_DCP_DEBUG_SG2 0x4494 +#define mmDCP_DVMM_DEBUG 0x1a93 +#define mmDCP0_DCP_DVMM_DEBUG 0x1a93 +#define mmDCP1_DCP_DVMM_DEBUG 0x1c93 +#define mmDCP2_DCP_DVMM_DEBUG 0x1e93 +#define mmDCP3_DCP_DVMM_DEBUG 0x4093 +#define mmDCP4_DCP_DVMM_DEBUG 0x4293 +#define mmDCP5_DCP_DVMM_DEBUG 0x4493 +#define mmDCP_TEST_DEBUG_INDEX 0x1a95 +#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 +#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95 +#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95 +#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095 +#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295 +#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495 +#define mmDCP_TEST_DEBUG_DATA 0x1a96 +#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 +#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96 +#define mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96 +#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4096 +#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4296 +#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4496 +#define mmGRPH_STEREOSYNC_FLIP 0x1a97 +#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 +#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97 +#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97 +#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097 +#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297 +#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497 +#define mmDCP_DEBUG2 0x1a98 +#define mmDCP0_DCP_DEBUG2 0x1a98 +#define mmDCP1_DCP_DEBUG2 0x1c98 +#define mmDCP2_DCP_DEBUG2 0x1e98 +#define mmDCP3_DCP_DEBUG2 0x4098 +#define mmDCP4_DCP_DEBUG2 0x4298 +#define mmDCP5_DCP_DEBUG2 0x4498 +#define mmHW_ROTATION 0x1a9e +#define mmDCP0_HW_ROTATION 0x1a9e +#define mmDCP1_HW_ROTATION 0x1c9e +#define mmDCP2_HW_ROTATION 0x1e9e +#define mmDCP3_HW_ROTATION 0x409e +#define mmDCP4_HW_ROTATION 0x429e +#define mmDCP5_HW_ROTATION 0x449e +#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f +#define mmREGAMMA_CONTROL 0x1aa0 +#define mmDCP0_REGAMMA_CONTROL 0x1aa0 +#define mmDCP1_REGAMMA_CONTROL 0x1ca0 +#define mmDCP2_REGAMMA_CONTROL 0x1ea0 +#define mmDCP3_REGAMMA_CONTROL 0x40a0 +#define mmDCP4_REGAMMA_CONTROL 0x42a0 +#define mmDCP5_REGAMMA_CONTROL 0x44a0 +#define mmREGAMMA_LUT_INDEX 0x1aa1 +#define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 +#define mmDCP1_REGAMMA_LUT_INDEX 0x1ca1 +#define mmDCP2_REGAMMA_LUT_INDEX 0x1ea1 +#define mmDCP3_REGAMMA_LUT_INDEX 0x40a1 +#define mmDCP4_REGAMMA_LUT_INDEX 0x42a1 +#define mmDCP5_REGAMMA_LUT_INDEX 0x44a1 +#define mmREGAMMA_LUT_DATA 0x1aa2 +#define mmDCP0_REGAMMA_LUT_DATA 0x1aa2 +#define mmDCP1_REGAMMA_LUT_DATA 0x1ca2 +#define mmDCP2_REGAMMA_LUT_DATA 0x1ea2 +#define mmDCP3_REGAMMA_LUT_DATA 0x40a2 +#define mmDCP4_REGAMMA_LUT_DATA 0x42a2 +#define mmDCP5_REGAMMA_LUT_DATA 0x44a2 +#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 +#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3 +#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3 +#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 +#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3 +#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3 +#define mmREGAMMA_CNTLA_START_CNTL 0x1aa4 +#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 +#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4 +#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4 +#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4 +#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4 +#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4 +#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 +#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5 +#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5 +#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 +#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5 +#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5 +#define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6 +#define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 +#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7 +#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7 +#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7 +#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7 +#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7 +#define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 +#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8 +#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8 +#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8 +#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8 +#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8 +#define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 +#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9 +#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9 +#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9 +#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9 +#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9 +#define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa +#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa +#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa +#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa +#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa +#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa +#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa +#define mmREGAMMA_CNTLA_REGION_6_7 0x1aab +#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab +#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab +#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab +#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab +#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab +#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab +#define mmREGAMMA_CNTLA_REGION_8_9 0x1aac +#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac +#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac +#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac +#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac +#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac +#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac +#define mmREGAMMA_CNTLA_REGION_10_11 0x1aad +#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad +#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad +#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead +#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad +#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad +#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad +#define mmREGAMMA_CNTLA_REGION_12_13 0x1aae +#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae +#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae +#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae +#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae +#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae +#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae +#define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf +#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf +#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf +#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf +#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af +#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af +#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af +#define mmREGAMMA_CNTLB_START_CNTL 0x1ab0 +#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 +#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0 +#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0 +#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0 +#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0 +#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0 +#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 +#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1 +#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1 +#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 +#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1 +#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1 +#define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2 +#define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 +#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3 +#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3 +#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3 +#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3 +#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3 +#define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 +#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4 +#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4 +#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4 +#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4 +#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4 +#define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 +#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5 +#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5 +#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5 +#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5 +#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5 +#define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 +#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6 +#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6 +#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6 +#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6 +#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6 +#define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 +#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7 +#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7 +#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7 +#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7 +#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7 +#define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 +#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8 +#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8 +#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8 +#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8 +#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8 +#define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 +#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9 +#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9 +#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9 +#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9 +#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9 +#define mmREGAMMA_CNTLB_REGION_12_13 0x1aba +#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba +#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba +#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba +#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba +#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba +#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba +#define mmREGAMMA_CNTLB_REGION_14_15 0x1abb +#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb +#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb +#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb +#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb +#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb +#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb +#define mmALPHA_CONTROL 0x1abc +#define mmDCP0_ALPHA_CONTROL 0x1abc +#define mmDCP1_ALPHA_CONTROL 0x1cbc +#define mmDCP2_ALPHA_CONTROL 0x1ebc +#define mmDCP3_ALPHA_CONTROL 0x40bc +#define mmDCP4_ALPHA_CONTROL 0x42bc +#define mmDCP5_ALPHA_CONTROL 0x44bc +#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd +#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe +#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe +#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe +#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be +#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be +#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be +#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf +#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf +#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf +#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf +#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf +#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf +#define mmGRPH_SURFACE_COUNTER_CONTROL 0x1a0f +#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x1a0f +#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x1c0f +#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x1e0f +#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x400f +#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x420f +#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x440f +#define mmGRPH_SURFACE_COUNTER_OUTPUT 0x1a1d +#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x1a1d +#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x1c1d +#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x1e1d +#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x401d +#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x421d +#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x441d +#define mmDIG_FE_CNTL 0x4a00 +#define mmDIG0_DIG_FE_CNTL 0x4a00 +#define mmDIG1_DIG_FE_CNTL 0x4b00 +#define mmDIG2_DIG_FE_CNTL 0x4c00 +#define mmDIG3_DIG_FE_CNTL 0x4d00 +#define mmDIG4_DIG_FE_CNTL 0x4e00 +#define mmDIG5_DIG_FE_CNTL 0x4f00 +#define mmDIG6_DIG_FE_CNTL 0x5400 +#define mmDIG7_DIG_FE_CNTL 0x5600 +#define mmDIG8_DIG_FE_CNTL 0x5700 +#define mmDIG_OUTPUT_CRC_CNTL 0x4a01 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01 +#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01 +#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01 +#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01 +#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01 +#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401 +#define mmDIG7_DIG_OUTPUT_CRC_CNTL 0x5601 +#define mmDIG8_DIG_OUTPUT_CRC_CNTL 0x5701 +#define mmDIG_OUTPUT_CRC_RESULT 0x4a02 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02 +#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02 +#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402 +#define mmDIG7_DIG_OUTPUT_CRC_RESULT 0x5602 +#define mmDIG8_DIG_OUTPUT_CRC_RESULT 0x5702 +#define mmDIG_CLOCK_PATTERN 0x4a03 +#define mmDIG0_DIG_CLOCK_PATTERN 0x4a03 +#define mmDIG1_DIG_CLOCK_PATTERN 0x4b03 +#define mmDIG2_DIG_CLOCK_PATTERN 0x4c03 +#define mmDIG3_DIG_CLOCK_PATTERN 0x4d03 +#define mmDIG4_DIG_CLOCK_PATTERN 0x4e03 +#define mmDIG5_DIG_CLOCK_PATTERN 0x4f03 +#define mmDIG6_DIG_CLOCK_PATTERN 0x5403 +#define mmDIG7_DIG_CLOCK_PATTERN 0x5603 +#define mmDIG8_DIG_CLOCK_PATTERN 0x5703 +#define mmDIG_TEST_PATTERN 0x4a04 +#define mmDIG0_DIG_TEST_PATTERN 0x4a04 +#define mmDIG1_DIG_TEST_PATTERN 0x4b04 +#define mmDIG2_DIG_TEST_PATTERN 0x4c04 +#define mmDIG3_DIG_TEST_PATTERN 0x4d04 +#define mmDIG4_DIG_TEST_PATTERN 0x4e04 +#define mmDIG5_DIG_TEST_PATTERN 0x4f04 +#define mmDIG6_DIG_TEST_PATTERN 0x5404 +#define mmDIG7_DIG_TEST_PATTERN 0x5604 +#define mmDIG8_DIG_TEST_PATTERN 0x5704 +#define mmDIG_RANDOM_PATTERN_SEED 0x4a05 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05 +#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05 +#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405 +#define mmDIG7_DIG_RANDOM_PATTERN_SEED 0x5605 +#define mmDIG8_DIG_RANDOM_PATTERN_SEED 0x5705 +#define mmDIG_FIFO_STATUS 0x4a06 +#define mmDIG0_DIG_FIFO_STATUS 0x4a06 +#define mmDIG1_DIG_FIFO_STATUS 0x4b06 +#define mmDIG2_DIG_FIFO_STATUS 0x4c06 +#define mmDIG3_DIG_FIFO_STATUS 0x4d06 +#define mmDIG4_DIG_FIFO_STATUS 0x4e06 +#define mmDIG5_DIG_FIFO_STATUS 0x4f06 +#define mmDIG6_DIG_FIFO_STATUS 0x5406 +#define mmDIG7_DIG_FIFO_STATUS 0x5606 +#define mmDIG8_DIG_FIFO_STATUS 0x5706 +#define mmDIG_DISPCLK_SWITCH_CNTL 0x4a07 +#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07 +#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07 +#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07 +#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07 +#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07 +#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07 +#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407 +#define mmDIG7_DIG_DISPCLK_SWITCH_CNTL 0x5607 +#define mmDIG8_DIG_DISPCLK_SWITCH_CNTL 0x5707 +#define mmDIG_DISPCLK_SWITCH_STATUS 0x4a08 +#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08 +#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08 +#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08 +#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08 +#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08 +#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08 +#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408 +#define mmDIG7_DIG_DISPCLK_SWITCH_STATUS 0x5608 +#define mmDIG8_DIG_DISPCLK_SWITCH_STATUS 0x5708 +#define mmHDMI_CONTROL 0x4a09 +#define mmDIG0_HDMI_CONTROL 0x4a09 +#define mmDIG1_HDMI_CONTROL 0x4b09 +#define mmDIG2_HDMI_CONTROL 0x4c09 +#define mmDIG3_HDMI_CONTROL 0x4d09 +#define mmDIG4_HDMI_CONTROL 0x4e09 +#define mmDIG5_HDMI_CONTROL 0x4f09 +#define mmDIG6_HDMI_CONTROL 0x5409 +#define mmDIG7_HDMI_CONTROL 0x5609 +#define mmDIG8_HDMI_CONTROL 0x5709 +#define mmHDMI_STATUS 0x4a0a +#define mmDIG0_HDMI_STATUS 0x4a0a +#define mmDIG1_HDMI_STATUS 0x4b0a +#define mmDIG2_HDMI_STATUS 0x4c0a +#define mmDIG3_HDMI_STATUS 0x4d0a +#define mmDIG4_HDMI_STATUS 0x4e0a +#define mmDIG5_HDMI_STATUS 0x4f0a +#define mmDIG6_HDMI_STATUS 0x540a +#define mmDIG7_HDMI_STATUS 0x560a +#define mmDIG8_HDMI_STATUS 0x570a +#define mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b +#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b +#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b +#define mmDIG7_HDMI_AUDIO_PACKET_CONTROL 0x560b +#define mmDIG8_HDMI_AUDIO_PACKET_CONTROL 0x570b +#define mmHDMI_ACR_PACKET_CONTROL 0x4a0c +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c +#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c +#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c +#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c +#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c +#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c +#define mmDIG7_HDMI_ACR_PACKET_CONTROL 0x560c +#define mmDIG8_HDMI_ACR_PACKET_CONTROL 0x570c +#define mmHDMI_VBI_PACKET_CONTROL 0x4a0d +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d +#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d +#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d +#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d +#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d +#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d +#define mmDIG7_HDMI_VBI_PACKET_CONTROL 0x560d +#define mmDIG8_HDMI_VBI_PACKET_CONTROL 0x570d +#define mmHDMI_INFOFRAME_CONTROL0 0x4a0e +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e +#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e +#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e +#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e +#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e +#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e +#define mmDIG7_HDMI_INFOFRAME_CONTROL0 0x560e +#define mmDIG8_HDMI_INFOFRAME_CONTROL0 0x570e +#define mmHDMI_INFOFRAME_CONTROL1 0x4a0f +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f +#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f +#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f +#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f +#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f +#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f +#define mmDIG7_HDMI_INFOFRAME_CONTROL1 0x560f +#define mmDIG8_HDMI_INFOFRAME_CONTROL1 0x570f +#define mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10 +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10 +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410 +#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL0 0x5610 +#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL0 0x5710 +#define mmAFMT_INTERRUPT_STATUS 0x4a11 +#define mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11 +#define mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11 +#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11 +#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11 +#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11 +#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11 +#define mmDIG6_AFMT_INTERRUPT_STATUS 0x5411 +#define mmDIG7_AFMT_INTERRUPT_STATUS 0x5611 +#define mmDIG8_AFMT_INTERRUPT_STATUS 0x5711 +#define mmHDMI_GC 0x4a13 +#define mmDIG0_HDMI_GC 0x4a13 +#define mmDIG1_HDMI_GC 0x4b13 +#define mmDIG2_HDMI_GC 0x4c13 +#define mmDIG3_HDMI_GC 0x4d13 +#define mmDIG4_HDMI_GC 0x4e13 +#define mmDIG5_HDMI_GC 0x4f13 +#define mmDIG6_HDMI_GC 0x5413 +#define mmDIG7_HDMI_GC 0x5613 +#define mmDIG8_HDMI_GC 0x5713 +#define mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414 +#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL2 0x5614 +#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL2 0x5714 +#define mmAFMT_ISRC1_0 0x4a15 +#define mmDIG0_AFMT_ISRC1_0 0x4a15 +#define mmDIG1_AFMT_ISRC1_0 0x4b15 +#define mmDIG2_AFMT_ISRC1_0 0x4c15 +#define mmDIG3_AFMT_ISRC1_0 0x4d15 +#define mmDIG4_AFMT_ISRC1_0 0x4e15 +#define mmDIG5_AFMT_ISRC1_0 0x4f15 +#define mmDIG6_AFMT_ISRC1_0 0x5415 +#define mmDIG7_AFMT_ISRC1_0 0x5615 +#define mmDIG8_AFMT_ISRC1_0 0x5715 +#define mmAFMT_ISRC1_1 0x4a16 +#define mmDIG0_AFMT_ISRC1_1 0x4a16 +#define mmDIG1_AFMT_ISRC1_1 0x4b16 +#define mmDIG2_AFMT_ISRC1_1 0x4c16 +#define mmDIG3_AFMT_ISRC1_1 0x4d16 +#define mmDIG4_AFMT_ISRC1_1 0x4e16 +#define mmDIG5_AFMT_ISRC1_1 0x4f16 +#define mmDIG6_AFMT_ISRC1_1 0x5416 +#define mmDIG7_AFMT_ISRC1_1 0x5616 +#define mmDIG8_AFMT_ISRC1_1 0x5716 +#define mmAFMT_ISRC1_2 0x4a17 +#define mmDIG0_AFMT_ISRC1_2 0x4a17 +#define mmDIG1_AFMT_ISRC1_2 0x4b17 +#define mmDIG2_AFMT_ISRC1_2 0x4c17 +#define mmDIG3_AFMT_ISRC1_2 0x4d17 +#define mmDIG4_AFMT_ISRC1_2 0x4e17 +#define mmDIG5_AFMT_ISRC1_2 0x4f17 +#define mmDIG6_AFMT_ISRC1_2 0x5417 +#define mmDIG7_AFMT_ISRC1_2 0x5617 +#define mmDIG8_AFMT_ISRC1_2 0x5717 +#define mmAFMT_ISRC1_3 0x4a18 +#define mmDIG0_AFMT_ISRC1_3 0x4a18 +#define mmDIG1_AFMT_ISRC1_3 0x4b18 +#define mmDIG2_AFMT_ISRC1_3 0x4c18 +#define mmDIG3_AFMT_ISRC1_3 0x4d18 +#define mmDIG4_AFMT_ISRC1_3 0x4e18 +#define mmDIG5_AFMT_ISRC1_3 0x4f18 +#define mmDIG6_AFMT_ISRC1_3 0x5418 +#define mmDIG7_AFMT_ISRC1_3 0x5618 +#define mmDIG8_AFMT_ISRC1_3 0x5718 +#define mmAFMT_ISRC1_4 0x4a19 +#define mmDIG0_AFMT_ISRC1_4 0x4a19 +#define mmDIG1_AFMT_ISRC1_4 0x4b19 +#define mmDIG2_AFMT_ISRC1_4 0x4c19 +#define mmDIG3_AFMT_ISRC1_4 0x4d19 +#define mmDIG4_AFMT_ISRC1_4 0x4e19 +#define mmDIG5_AFMT_ISRC1_4 0x4f19 +#define mmDIG6_AFMT_ISRC1_4 0x5419 +#define mmDIG7_AFMT_ISRC1_4 0x5619 +#define mmDIG8_AFMT_ISRC1_4 0x5719 +#define mmAFMT_ISRC2_0 0x4a1a +#define mmDIG0_AFMT_ISRC2_0 0x4a1a +#define mmDIG1_AFMT_ISRC2_0 0x4b1a +#define mmDIG2_AFMT_ISRC2_0 0x4c1a +#define mmDIG3_AFMT_ISRC2_0 0x4d1a +#define mmDIG4_AFMT_ISRC2_0 0x4e1a +#define mmDIG5_AFMT_ISRC2_0 0x4f1a +#define mmDIG6_AFMT_ISRC2_0 0x541a +#define mmDIG7_AFMT_ISRC2_0 0x561a +#define mmDIG8_AFMT_ISRC2_0 0x571a +#define mmAFMT_ISRC2_1 0x4a1b +#define mmDIG0_AFMT_ISRC2_1 0x4a1b +#define mmDIG1_AFMT_ISRC2_1 0x4b1b +#define mmDIG2_AFMT_ISRC2_1 0x4c1b +#define mmDIG3_AFMT_ISRC2_1 0x4d1b +#define mmDIG4_AFMT_ISRC2_1 0x4e1b +#define mmDIG5_AFMT_ISRC2_1 0x4f1b +#define mmDIG6_AFMT_ISRC2_1 0x541b +#define mmDIG7_AFMT_ISRC2_1 0x561b +#define mmDIG8_AFMT_ISRC2_1 0x571b +#define mmAFMT_ISRC2_2 0x4a1c +#define mmDIG0_AFMT_ISRC2_2 0x4a1c +#define mmDIG1_AFMT_ISRC2_2 0x4b1c +#define mmDIG2_AFMT_ISRC2_2 0x4c1c +#define mmDIG3_AFMT_ISRC2_2 0x4d1c +#define mmDIG4_AFMT_ISRC2_2 0x4e1c +#define mmDIG5_AFMT_ISRC2_2 0x4f1c +#define mmDIG6_AFMT_ISRC2_2 0x541c +#define mmDIG7_AFMT_ISRC2_2 0x561c +#define mmDIG8_AFMT_ISRC2_2 0x571c +#define mmAFMT_ISRC2_3 0x4a1d +#define mmDIG0_AFMT_ISRC2_3 0x4a1d +#define mmDIG1_AFMT_ISRC2_3 0x4b1d +#define mmDIG2_AFMT_ISRC2_3 0x4c1d +#define mmDIG3_AFMT_ISRC2_3 0x4d1d +#define mmDIG4_AFMT_ISRC2_3 0x4e1d +#define mmDIG5_AFMT_ISRC2_3 0x4f1d +#define mmDIG6_AFMT_ISRC2_3 0x541d +#define mmDIG7_AFMT_ISRC2_3 0x561d +#define mmDIG8_AFMT_ISRC2_3 0x571d +#define mmAFMT_AVI_INFO0 0x4a1e +#define mmDIG0_AFMT_AVI_INFO0 0x4a1e +#define mmDIG1_AFMT_AVI_INFO0 0x4b1e +#define mmDIG2_AFMT_AVI_INFO0 0x4c1e +#define mmDIG3_AFMT_AVI_INFO0 0x4d1e +#define mmDIG4_AFMT_AVI_INFO0 0x4e1e +#define mmDIG5_AFMT_AVI_INFO0 0x4f1e +#define mmDIG6_AFMT_AVI_INFO0 0x541e +#define mmDIG7_AFMT_AVI_INFO0 0x561e +#define mmDIG8_AFMT_AVI_INFO0 0x571e +#define mmAFMT_AVI_INFO1 0x4a1f +#define mmDIG0_AFMT_AVI_INFO1 0x4a1f +#define mmDIG1_AFMT_AVI_INFO1 0x4b1f +#define mmDIG2_AFMT_AVI_INFO1 0x4c1f +#define mmDIG3_AFMT_AVI_INFO1 0x4d1f +#define mmDIG4_AFMT_AVI_INFO1 0x4e1f +#define mmDIG5_AFMT_AVI_INFO1 0x4f1f +#define mmDIG6_AFMT_AVI_INFO1 0x541f +#define mmDIG7_AFMT_AVI_INFO1 0x561f +#define mmDIG8_AFMT_AVI_INFO1 0x571f +#define mmAFMT_AVI_INFO2 0x4a20 +#define mmDIG0_AFMT_AVI_INFO2 0x4a20 +#define mmDIG1_AFMT_AVI_INFO2 0x4b20 +#define mmDIG2_AFMT_AVI_INFO2 0x4c20 +#define mmDIG3_AFMT_AVI_INFO2 0x4d20 +#define mmDIG4_AFMT_AVI_INFO2 0x4e20 +#define mmDIG5_AFMT_AVI_INFO2 0x4f20 +#define mmDIG6_AFMT_AVI_INFO2 0x5420 +#define mmDIG7_AFMT_AVI_INFO2 0x5620 +#define mmDIG8_AFMT_AVI_INFO2 0x5720 +#define mmAFMT_AVI_INFO3 0x4a21 +#define mmDIG0_AFMT_AVI_INFO3 0x4a21 +#define mmDIG1_AFMT_AVI_INFO3 0x4b21 +#define mmDIG2_AFMT_AVI_INFO3 0x4c21 +#define mmDIG3_AFMT_AVI_INFO3 0x4d21 +#define mmDIG4_AFMT_AVI_INFO3 0x4e21 +#define mmDIG5_AFMT_AVI_INFO3 0x4f21 +#define mmDIG6_AFMT_AVI_INFO3 0x5421 +#define mmDIG7_AFMT_AVI_INFO3 0x5621 +#define mmDIG8_AFMT_AVI_INFO3 0x5721 +#define mmAFMT_MPEG_INFO0 0x4a22 +#define mmDIG0_AFMT_MPEG_INFO0 0x4a22 +#define mmDIG1_AFMT_MPEG_INFO0 0x4b22 +#define mmDIG2_AFMT_MPEG_INFO0 0x4c22 +#define mmDIG3_AFMT_MPEG_INFO0 0x4d22 +#define mmDIG4_AFMT_MPEG_INFO0 0x4e22 +#define mmDIG5_AFMT_MPEG_INFO0 0x4f22 +#define mmDIG6_AFMT_MPEG_INFO0 0x5422 +#define mmDIG7_AFMT_MPEG_INFO0 0x5622 +#define mmDIG8_AFMT_MPEG_INFO0 0x5722 +#define mmAFMT_MPEG_INFO1 0x4a23 +#define mmDIG0_AFMT_MPEG_INFO1 0x4a23 +#define mmDIG1_AFMT_MPEG_INFO1 0x4b23 +#define mmDIG2_AFMT_MPEG_INFO1 0x4c23 +#define mmDIG3_AFMT_MPEG_INFO1 0x4d23 +#define mmDIG4_AFMT_MPEG_INFO1 0x4e23 +#define mmDIG5_AFMT_MPEG_INFO1 0x4f23 +#define mmDIG6_AFMT_MPEG_INFO1 0x5423 +#define mmDIG7_AFMT_MPEG_INFO1 0x5623 +#define mmDIG8_AFMT_MPEG_INFO1 0x5723 +#define mmAFMT_GENERIC_HDR 0x4a24 +#define mmDIG0_AFMT_GENERIC_HDR 0x4a24 +#define mmDIG1_AFMT_GENERIC_HDR 0x4b24 +#define mmDIG2_AFMT_GENERIC_HDR 0x4c24 +#define mmDIG3_AFMT_GENERIC_HDR 0x4d24 +#define mmDIG4_AFMT_GENERIC_HDR 0x4e24 +#define mmDIG5_AFMT_GENERIC_HDR 0x4f24 +#define mmDIG6_AFMT_GENERIC_HDR 0x5424 +#define mmDIG7_AFMT_GENERIC_HDR 0x5624 +#define mmDIG8_AFMT_GENERIC_HDR 0x5724 +#define mmAFMT_GENERIC_0 0x4a25 +#define mmDIG0_AFMT_GENERIC_0 0x4a25 +#define mmDIG1_AFMT_GENERIC_0 0x4b25 +#define mmDIG2_AFMT_GENERIC_0 0x4c25 +#define mmDIG3_AFMT_GENERIC_0 0x4d25 +#define mmDIG4_AFMT_GENERIC_0 0x4e25 +#define mmDIG5_AFMT_GENERIC_0 0x4f25 +#define mmDIG6_AFMT_GENERIC_0 0x5425 +#define mmDIG7_AFMT_GENERIC_0 0x5625 +#define mmDIG8_AFMT_GENERIC_0 0x5725 +#define mmAFMT_GENERIC_1 0x4a26 +#define mmDIG0_AFMT_GENERIC_1 0x4a26 +#define mmDIG1_AFMT_GENERIC_1 0x4b26 +#define mmDIG2_AFMT_GENERIC_1 0x4c26 +#define mmDIG3_AFMT_GENERIC_1 0x4d26 +#define mmDIG4_AFMT_GENERIC_1 0x4e26 +#define mmDIG5_AFMT_GENERIC_1 0x4f26 +#define mmDIG6_AFMT_GENERIC_1 0x5426 +#define mmDIG7_AFMT_GENERIC_1 0x5626 +#define mmDIG8_AFMT_GENERIC_1 0x5726 +#define mmAFMT_GENERIC_2 0x4a27 +#define mmDIG0_AFMT_GENERIC_2 0x4a27 +#define mmDIG1_AFMT_GENERIC_2 0x4b27 +#define mmDIG2_AFMT_GENERIC_2 0x4c27 +#define mmDIG3_AFMT_GENERIC_2 0x4d27 +#define mmDIG4_AFMT_GENERIC_2 0x4e27 +#define mmDIG5_AFMT_GENERIC_2 0x4f27 +#define mmDIG6_AFMT_GENERIC_2 0x5427 +#define mmDIG7_AFMT_GENERIC_2 0x5627 +#define mmDIG8_AFMT_GENERIC_2 0x5727 +#define mmAFMT_GENERIC_3 0x4a28 +#define mmDIG0_AFMT_GENERIC_3 0x4a28 +#define mmDIG1_AFMT_GENERIC_3 0x4b28 +#define mmDIG2_AFMT_GENERIC_3 0x4c28 +#define mmDIG3_AFMT_GENERIC_3 0x4d28 +#define mmDIG4_AFMT_GENERIC_3 0x4e28 +#define mmDIG5_AFMT_GENERIC_3 0x4f28 +#define mmDIG6_AFMT_GENERIC_3 0x5428 +#define mmDIG7_AFMT_GENERIC_3 0x5628 +#define mmDIG8_AFMT_GENERIC_3 0x5728 +#define mmAFMT_GENERIC_4 0x4a29 +#define mmDIG0_AFMT_GENERIC_4 0x4a29 +#define mmDIG1_AFMT_GENERIC_4 0x4b29 +#define mmDIG2_AFMT_GENERIC_4 0x4c29 +#define mmDIG3_AFMT_GENERIC_4 0x4d29 +#define mmDIG4_AFMT_GENERIC_4 0x4e29 +#define mmDIG5_AFMT_GENERIC_4 0x4f29 +#define mmDIG6_AFMT_GENERIC_4 0x5429 +#define mmDIG7_AFMT_GENERIC_4 0x5629 +#define mmDIG8_AFMT_GENERIC_4 0x5729 +#define mmAFMT_GENERIC_5 0x4a2a +#define mmDIG0_AFMT_GENERIC_5 0x4a2a +#define mmDIG1_AFMT_GENERIC_5 0x4b2a +#define mmDIG2_AFMT_GENERIC_5 0x4c2a +#define mmDIG3_AFMT_GENERIC_5 0x4d2a +#define mmDIG4_AFMT_GENERIC_5 0x4e2a +#define mmDIG5_AFMT_GENERIC_5 0x4f2a +#define mmDIG6_AFMT_GENERIC_5 0x542a +#define mmDIG7_AFMT_GENERIC_5 0x562a +#define mmDIG8_AFMT_GENERIC_5 0x572a +#define mmAFMT_GENERIC_6 0x4a2b +#define mmDIG0_AFMT_GENERIC_6 0x4a2b +#define mmDIG1_AFMT_GENERIC_6 0x4b2b +#define mmDIG2_AFMT_GENERIC_6 0x4c2b +#define mmDIG3_AFMT_GENERIC_6 0x4d2b +#define mmDIG4_AFMT_GENERIC_6 0x4e2b +#define mmDIG5_AFMT_GENERIC_6 0x4f2b +#define mmDIG6_AFMT_GENERIC_6 0x542b +#define mmDIG7_AFMT_GENERIC_6 0x562b +#define mmDIG8_AFMT_GENERIC_6 0x572b +#define mmAFMT_GENERIC_7 0x4a2c +#define mmDIG0_AFMT_GENERIC_7 0x4a2c +#define mmDIG1_AFMT_GENERIC_7 0x4b2c +#define mmDIG2_AFMT_GENERIC_7 0x4c2c +#define mmDIG3_AFMT_GENERIC_7 0x4d2c +#define mmDIG4_AFMT_GENERIC_7 0x4e2c +#define mmDIG5_AFMT_GENERIC_7 0x4f2c +#define mmDIG6_AFMT_GENERIC_7 0x542c +#define mmDIG7_AFMT_GENERIC_7 0x562c +#define mmDIG8_AFMT_GENERIC_7 0x572c +#define mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d +#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d +#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d +#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL1 0x562d +#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL1 0x572d +#define mmHDMI_ACR_32_0 0x4a2e +#define mmDIG0_HDMI_ACR_32_0 0x4a2e +#define mmDIG1_HDMI_ACR_32_0 0x4b2e +#define mmDIG2_HDMI_ACR_32_0 0x4c2e +#define mmDIG3_HDMI_ACR_32_0 0x4d2e +#define mmDIG4_HDMI_ACR_32_0 0x4e2e +#define mmDIG5_HDMI_ACR_32_0 0x4f2e +#define mmDIG6_HDMI_ACR_32_0 0x542e +#define mmDIG7_HDMI_ACR_32_0 0x562e +#define mmDIG8_HDMI_ACR_32_0 0x572e +#define mmHDMI_ACR_32_1 0x4a2f +#define mmDIG0_HDMI_ACR_32_1 0x4a2f +#define mmDIG1_HDMI_ACR_32_1 0x4b2f +#define mmDIG2_HDMI_ACR_32_1 0x4c2f +#define mmDIG3_HDMI_ACR_32_1 0x4d2f +#define mmDIG4_HDMI_ACR_32_1 0x4e2f +#define mmDIG5_HDMI_ACR_32_1 0x4f2f +#define mmDIG6_HDMI_ACR_32_1 0x542f +#define mmDIG7_HDMI_ACR_32_1 0x562f +#define mmDIG8_HDMI_ACR_32_1 0x572f +#define mmHDMI_ACR_44_0 0x4a30 +#define mmDIG0_HDMI_ACR_44_0 0x4a30 +#define mmDIG1_HDMI_ACR_44_0 0x4b30 +#define mmDIG2_HDMI_ACR_44_0 0x4c30 +#define mmDIG3_HDMI_ACR_44_0 0x4d30 +#define mmDIG4_HDMI_ACR_44_0 0x4e30 +#define mmDIG5_HDMI_ACR_44_0 0x4f30 +#define mmDIG6_HDMI_ACR_44_0 0x5430 +#define mmDIG7_HDMI_ACR_44_0 0x5630 +#define mmDIG8_HDMI_ACR_44_0 0x5730 +#define mmHDMI_ACR_44_1 0x4a31 +#define mmDIG0_HDMI_ACR_44_1 0x4a31 +#define mmDIG1_HDMI_ACR_44_1 0x4b31 +#define mmDIG2_HDMI_ACR_44_1 0x4c31 +#define mmDIG3_HDMI_ACR_44_1 0x4d31 +#define mmDIG4_HDMI_ACR_44_1 0x4e31 +#define mmDIG5_HDMI_ACR_44_1 0x4f31 +#define mmDIG6_HDMI_ACR_44_1 0x5431 +#define mmDIG7_HDMI_ACR_44_1 0x5631 +#define mmDIG8_HDMI_ACR_44_1 0x5731 +#define mmHDMI_ACR_48_0 0x4a32 +#define mmDIG0_HDMI_ACR_48_0 0x4a32 +#define mmDIG1_HDMI_ACR_48_0 0x4b32 +#define mmDIG2_HDMI_ACR_48_0 0x4c32 +#define mmDIG3_HDMI_ACR_48_0 0x4d32 +#define mmDIG4_HDMI_ACR_48_0 0x4e32 +#define mmDIG5_HDMI_ACR_48_0 0x4f32 +#define mmDIG6_HDMI_ACR_48_0 0x5432 +#define mmDIG7_HDMI_ACR_48_0 0x5632 +#define mmDIG8_HDMI_ACR_48_0 0x5732 +#define mmHDMI_ACR_48_1 0x4a33 +#define mmDIG0_HDMI_ACR_48_1 0x4a33 +#define mmDIG1_HDMI_ACR_48_1 0x4b33 +#define mmDIG2_HDMI_ACR_48_1 0x4c33 +#define mmDIG3_HDMI_ACR_48_1 0x4d33 +#define mmDIG4_HDMI_ACR_48_1 0x4e33 +#define mmDIG5_HDMI_ACR_48_1 0x4f33 +#define mmDIG6_HDMI_ACR_48_1 0x5433 +#define mmDIG7_HDMI_ACR_48_1 0x5633 +#define mmDIG8_HDMI_ACR_48_1 0x5733 +#define mmHDMI_ACR_STATUS_0 0x4a34 +#define mmDIG0_HDMI_ACR_STATUS_0 0x4a34 +#define mmDIG1_HDMI_ACR_STATUS_0 0x4b34 +#define mmDIG2_HDMI_ACR_STATUS_0 0x4c34 +#define mmDIG3_HDMI_ACR_STATUS_0 0x4d34 +#define mmDIG4_HDMI_ACR_STATUS_0 0x4e34 +#define mmDIG5_HDMI_ACR_STATUS_0 0x4f34 +#define mmDIG6_HDMI_ACR_STATUS_0 0x5434 +#define mmDIG7_HDMI_ACR_STATUS_0 0x5634 +#define mmDIG8_HDMI_ACR_STATUS_0 0x5734 +#define mmHDMI_ACR_STATUS_1 0x4a35 +#define mmDIG0_HDMI_ACR_STATUS_1 0x4a35 +#define mmDIG1_HDMI_ACR_STATUS_1 0x4b35 +#define mmDIG2_HDMI_ACR_STATUS_1 0x4c35 +#define mmDIG3_HDMI_ACR_STATUS_1 0x4d35 +#define mmDIG4_HDMI_ACR_STATUS_1 0x4e35 +#define mmDIG5_HDMI_ACR_STATUS_1 0x4f35 +#define mmDIG6_HDMI_ACR_STATUS_1 0x5435 +#define mmDIG7_HDMI_ACR_STATUS_1 0x5635 +#define mmDIG8_HDMI_ACR_STATUS_1 0x5735 +#define mmAFMT_AUDIO_INFO0 0x4a36 +#define mmDIG0_AFMT_AUDIO_INFO0 0x4a36 +#define mmDIG1_AFMT_AUDIO_INFO0 0x4b36 +#define mmDIG2_AFMT_AUDIO_INFO0 0x4c36 +#define mmDIG3_AFMT_AUDIO_INFO0 0x4d36 +#define mmDIG4_AFMT_AUDIO_INFO0 0x4e36 +#define mmDIG5_AFMT_AUDIO_INFO0 0x4f36 +#define mmDIG6_AFMT_AUDIO_INFO0 0x5436 +#define mmDIG7_AFMT_AUDIO_INFO0 0x5636 +#define mmDIG8_AFMT_AUDIO_INFO0 0x5736 +#define mmAFMT_AUDIO_INFO1 0x4a37 +#define mmDIG0_AFMT_AUDIO_INFO1 0x4a37 +#define mmDIG1_AFMT_AUDIO_INFO1 0x4b37 +#define mmDIG2_AFMT_AUDIO_INFO1 0x4c37 +#define mmDIG3_AFMT_AUDIO_INFO1 0x4d37 +#define mmDIG4_AFMT_AUDIO_INFO1 0x4e37 +#define mmDIG5_AFMT_AUDIO_INFO1 0x4f37 +#define mmDIG6_AFMT_AUDIO_INFO1 0x5437 +#define mmDIG7_AFMT_AUDIO_INFO1 0x5637 +#define mmDIG8_AFMT_AUDIO_INFO1 0x5737 +#define mmAFMT_60958_0 0x4a38 +#define mmDIG0_AFMT_60958_0 0x4a38 +#define mmDIG1_AFMT_60958_0 0x4b38 +#define mmDIG2_AFMT_60958_0 0x4c38 +#define mmDIG3_AFMT_60958_0 0x4d38 +#define mmDIG4_AFMT_60958_0 0x4e38 +#define mmDIG5_AFMT_60958_0 0x4f38 +#define mmDIG6_AFMT_60958_0 0x5438 +#define mmDIG7_AFMT_60958_0 0x5638 +#define mmDIG8_AFMT_60958_0 0x5738 +#define mmAFMT_60958_1 0x4a39 +#define mmDIG0_AFMT_60958_1 0x4a39 +#define mmDIG1_AFMT_60958_1 0x4b39 +#define mmDIG2_AFMT_60958_1 0x4c39 +#define mmDIG3_AFMT_60958_1 0x4d39 +#define mmDIG4_AFMT_60958_1 0x4e39 +#define mmDIG5_AFMT_60958_1 0x4f39 +#define mmDIG6_AFMT_60958_1 0x5439 +#define mmDIG7_AFMT_60958_1 0x5639 +#define mmDIG8_AFMT_60958_1 0x5739 +#define mmAFMT_AUDIO_CRC_CONTROL 0x4a3a +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a +#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a +#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a +#define mmDIG7_AFMT_AUDIO_CRC_CONTROL 0x563a +#define mmDIG8_AFMT_AUDIO_CRC_CONTROL 0x573a +#define mmAFMT_RAMP_CONTROL0 0x4a3b +#define mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b +#define mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b +#define mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b +#define mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b +#define mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b +#define mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b +#define mmDIG6_AFMT_RAMP_CONTROL0 0x543b +#define mmDIG7_AFMT_RAMP_CONTROL0 0x563b +#define mmDIG8_AFMT_RAMP_CONTROL0 0x573b +#define mmAFMT_RAMP_CONTROL1 0x4a3c +#define mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c +#define mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c +#define mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c +#define mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c +#define mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c +#define mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c +#define mmDIG6_AFMT_RAMP_CONTROL1 0x543c +#define mmDIG7_AFMT_RAMP_CONTROL1 0x563c +#define mmDIG8_AFMT_RAMP_CONTROL1 0x573c +#define mmAFMT_RAMP_CONTROL2 0x4a3d +#define mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d +#define mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d +#define mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d +#define mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d +#define mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d +#define mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d +#define mmDIG6_AFMT_RAMP_CONTROL2 0x543d +#define mmDIG7_AFMT_RAMP_CONTROL2 0x563d +#define mmDIG8_AFMT_RAMP_CONTROL2 0x573d +#define mmAFMT_RAMP_CONTROL3 0x4a3e +#define mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e +#define mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e +#define mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e +#define mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e +#define mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e +#define mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e +#define mmDIG6_AFMT_RAMP_CONTROL3 0x543e +#define mmDIG7_AFMT_RAMP_CONTROL3 0x563e +#define mmDIG8_AFMT_RAMP_CONTROL3 0x573e +#define mmAFMT_60958_2 0x4a3f +#define mmDIG0_AFMT_60958_2 0x4a3f +#define mmDIG1_AFMT_60958_2 0x4b3f +#define mmDIG2_AFMT_60958_2 0x4c3f +#define mmDIG3_AFMT_60958_2 0x4d3f +#define mmDIG4_AFMT_60958_2 0x4e3f +#define mmDIG5_AFMT_60958_2 0x4f3f +#define mmDIG6_AFMT_60958_2 0x543f +#define mmDIG7_AFMT_60958_2 0x563f +#define mmDIG8_AFMT_60958_2 0x573f +#define mmAFMT_AUDIO_CRC_RESULT 0x4a40 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40 +#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40 +#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440 +#define mmDIG7_AFMT_AUDIO_CRC_RESULT 0x5640 +#define mmDIG8_AFMT_AUDIO_CRC_RESULT 0x5740 +#define mmAFMT_STATUS 0x4a41 +#define mmDIG0_AFMT_STATUS 0x4a41 +#define mmDIG1_AFMT_STATUS 0x4b41 +#define mmDIG2_AFMT_STATUS 0x4c41 +#define mmDIG3_AFMT_STATUS 0x4d41 +#define mmDIG4_AFMT_STATUS 0x4e41 +#define mmDIG5_AFMT_STATUS 0x4f41 +#define mmDIG6_AFMT_STATUS 0x5441 +#define mmDIG7_AFMT_STATUS 0x5641 +#define mmDIG8_AFMT_STATUS 0x5741 +#define mmAFMT_AUDIO_PACKET_CONTROL 0x4a42 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42 +#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42 +#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442 +#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL 0x5642 +#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL 0x5742 +#define mmAFMT_VBI_PACKET_CONTROL 0x4a43 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43 +#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43 +#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443 +#define mmDIG7_AFMT_VBI_PACKET_CONTROL 0x5643 +#define mmDIG8_AFMT_VBI_PACKET_CONTROL 0x5743 +#define mmAFMT_INFOFRAME_CONTROL0 0x4a44 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44 +#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44 +#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444 +#define mmDIG7_AFMT_INFOFRAME_CONTROL0 0x5644 +#define mmDIG8_AFMT_INFOFRAME_CONTROL0 0x5744 +#define mmAFMT_AUDIO_SRC_CONTROL 0x4a45 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45 +#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45 +#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445 +#define mmDIG7_AFMT_AUDIO_SRC_CONTROL 0x5645 +#define mmDIG8_AFMT_AUDIO_SRC_CONTROL 0x5745 +#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46 +#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46 +#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46 +#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46 +#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46 +#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46 +#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46 +#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446 +#define mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL 0x5646 +#define mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL 0x5746 +#define mmAFMT_CNTL 0x4a7e +#define mmDIG0_AFMT_CNTL 0x4a7e +#define mmDIG1_AFMT_CNTL 0x4b7e +#define mmDIG2_AFMT_CNTL 0x4c7e +#define mmDIG3_AFMT_CNTL 0x4d7e +#define mmDIG4_AFMT_CNTL 0x4e7e +#define mmDIG5_AFMT_CNTL 0x4f7e +#define mmDIG6_AFMT_CNTL 0x547e +#define mmDIG7_AFMT_CNTL 0x567e +#define mmDIG8_AFMT_CNTL 0x577e +#define mmDIG_BE_CNTL 0x4a47 +#define mmDIG0_DIG_BE_CNTL 0x4a47 +#define mmDIG1_DIG_BE_CNTL 0x4b47 +#define mmDIG2_DIG_BE_CNTL 0x4c47 +#define mmDIG3_DIG_BE_CNTL 0x4d47 +#define mmDIG4_DIG_BE_CNTL 0x4e47 +#define mmDIG5_DIG_BE_CNTL 0x4f47 +#define mmDIG6_DIG_BE_CNTL 0x5447 +#define mmDIG7_DIG_BE_CNTL 0x5647 +#define mmDIG8_DIG_BE_CNTL 0x5747 +#define mmDIG_BE_EN_CNTL 0x4a48 +#define mmDIG0_DIG_BE_EN_CNTL 0x4a48 +#define mmDIG1_DIG_BE_EN_CNTL 0x4b48 +#define mmDIG2_DIG_BE_EN_CNTL 0x4c48 +#define mmDIG3_DIG_BE_EN_CNTL 0x4d48 +#define mmDIG4_DIG_BE_EN_CNTL 0x4e48 +#define mmDIG5_DIG_BE_EN_CNTL 0x4f48 +#define mmDIG6_DIG_BE_EN_CNTL 0x5448 +#define mmDIG7_DIG_BE_EN_CNTL 0x5648 +#define mmDIG8_DIG_BE_EN_CNTL 0x5748 +#define mmTMDS_CNTL 0x4a6b +#define mmDIG0_TMDS_CNTL 0x4a6b +#define mmDIG1_TMDS_CNTL 0x4b6b +#define mmDIG2_TMDS_CNTL 0x4c6b +#define mmDIG3_TMDS_CNTL 0x4d6b +#define mmDIG4_TMDS_CNTL 0x4e6b +#define mmDIG5_TMDS_CNTL 0x4f6b +#define mmDIG6_TMDS_CNTL 0x546b +#define mmDIG7_TMDS_CNTL 0x566b +#define mmDIG8_TMDS_CNTL 0x576b +#define mmTMDS_CONTROL_CHAR 0x4a6c +#define mmDIG0_TMDS_CONTROL_CHAR 0x4a6c +#define mmDIG1_TMDS_CONTROL_CHAR 0x4b6c +#define mmDIG2_TMDS_CONTROL_CHAR 0x4c6c +#define mmDIG3_TMDS_CONTROL_CHAR 0x4d6c +#define mmDIG4_TMDS_CONTROL_CHAR 0x4e6c +#define mmDIG5_TMDS_CONTROL_CHAR 0x4f6c +#define mmDIG6_TMDS_CONTROL_CHAR 0x546c +#define mmDIG7_TMDS_CONTROL_CHAR 0x566c +#define mmDIG8_TMDS_CONTROL_CHAR 0x576c +#define mmTMDS_CONTROL0_FEEDBACK 0x4a6d +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d +#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d +#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d +#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d +#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d +#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d +#define mmDIG7_TMDS_CONTROL0_FEEDBACK 0x566d +#define mmDIG8_TMDS_CONTROL0_FEEDBACK 0x576d +#define mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e +#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e +#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e +#define mmDIG7_TMDS_STEREOSYNC_CTL_SEL 0x566e +#define mmDIG8_TMDS_STEREOSYNC_CTL_SEL 0x576e +#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f +#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1 0x566f +#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1 0x576f +#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70 +#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70 +#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470 +#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3 0x5670 +#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3 0x5770 +#define mmTMDS_DEBUG 0x4a71 +#define mmDIG0_TMDS_DEBUG 0x4a71 +#define mmDIG1_TMDS_DEBUG 0x4b71 +#define mmDIG2_TMDS_DEBUG 0x4c71 +#define mmDIG3_TMDS_DEBUG 0x4d71 +#define mmDIG4_TMDS_DEBUG 0x4e71 +#define mmDIG5_TMDS_DEBUG 0x4f71 +#define mmDIG6_TMDS_DEBUG 0x5471 +#define mmDIG7_TMDS_DEBUG 0x5671 +#define mmDIG8_TMDS_DEBUG 0x5771 +#define mmTMDS_CTL_BITS 0x4a72 +#define mmDIG0_TMDS_CTL_BITS 0x4a72 +#define mmDIG1_TMDS_CTL_BITS 0x4b72 +#define mmDIG2_TMDS_CTL_BITS 0x4c72 +#define mmDIG3_TMDS_CTL_BITS 0x4d72 +#define mmDIG4_TMDS_CTL_BITS 0x4e72 +#define mmDIG5_TMDS_CTL_BITS 0x4f72 +#define mmDIG6_TMDS_CTL_BITS 0x5472 +#define mmDIG7_TMDS_CTL_BITS 0x5672 +#define mmDIG8_TMDS_CTL_BITS 0x5772 +#define mmTMDS_DCBALANCER_CONTROL 0x4a73 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 +#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73 +#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73 +#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73 +#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 +#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473 +#define mmDIG7_TMDS_DCBALANCER_CONTROL 0x5673 +#define mmDIG8_TMDS_DCBALANCER_CONTROL 0x5773 +#define mmTMDS_CTL0_1_GEN_CNTL 0x4a75 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75 +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75 +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75 +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75 +#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75 +#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475 +#define mmDIG7_TMDS_CTL0_1_GEN_CNTL 0x5675 +#define mmDIG8_TMDS_CTL0_1_GEN_CNTL 0x5775 +#define mmTMDS_CTL2_3_GEN_CNTL 0x4a76 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76 +#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76 +#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476 +#define mmDIG7_TMDS_CTL2_3_GEN_CNTL 0x5676 +#define mmDIG8_TMDS_CTL2_3_GEN_CNTL 0x5776 +#define mmDIG_VERSION 0x4a78 +#define mmDIG0_DIG_VERSION 0x4a78 +#define mmDIG1_DIG_VERSION 0x4b78 +#define mmDIG2_DIG_VERSION 0x4c78 +#define mmDIG3_DIG_VERSION 0x4d78 +#define mmDIG4_DIG_VERSION 0x4e78 +#define mmDIG5_DIG_VERSION 0x4f78 +#define mmDIG6_DIG_VERSION 0x5478 +#define mmDIG7_DIG_VERSION 0x5678 +#define mmDIG8_DIG_VERSION 0x5778 +#define mmDIG_LANE_ENABLE 0x4a79 +#define mmDIG0_DIG_LANE_ENABLE 0x4a79 +#define mmDIG1_DIG_LANE_ENABLE 0x4b79 +#define mmDIG2_DIG_LANE_ENABLE 0x4c79 +#define mmDIG3_DIG_LANE_ENABLE 0x4d79 +#define mmDIG4_DIG_LANE_ENABLE 0x4e79 +#define mmDIG5_DIG_LANE_ENABLE 0x4f79 +#define mmDIG6_DIG_LANE_ENABLE 0x5479 +#define mmDIG7_DIG_LANE_ENABLE 0x5679 +#define mmDIG8_DIG_LANE_ENABLE 0x5779 +#define mmDIG_TEST_DEBUG_INDEX 0x4a7a +#define mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a +#define mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a +#define mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a +#define mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a +#define mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a +#define mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a +#define mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a +#define mmDIG7_DIG_TEST_DEBUG_INDEX 0x567a +#define mmDIG8_DIG_TEST_DEBUG_INDEX 0x577a +#define mmDIG_TEST_DEBUG_DATA 0x4a7b +#define mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b +#define mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b +#define mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b +#define mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b +#define mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b +#define mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b +#define mmDIG6_DIG_TEST_DEBUG_DATA 0x547b +#define mmDIG7_DIG_TEST_DEBUG_DATA 0x567b +#define mmDIG8_DIG_TEST_DEBUG_DATA 0x577b +#define mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c +#define mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c +#define mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c +#define mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c +#define mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c +#define mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c +#define mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c +#define mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c +#define mmDIG7_DIG_FE_TEST_DEBUG_INDEX 0x567c +#define mmDIG8_DIG_FE_TEST_DEBUG_INDEX 0x577c +#define mmDIG_FE_TEST_DEBUG_DATA 0x4a7d +#define mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d +#define mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d +#define mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d +#define mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d +#define mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d +#define mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d +#define mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d +#define mmDIG7_DIG_FE_TEST_DEBUG_DATA 0x567d +#define mmDIG8_DIG_FE_TEST_DEBUG_DATA 0x577d +#define mmDMCU_CTRL 0x1600 +#define mmDMCU_STATUS 0x1601 +#define mmDMCU_PC_START_ADDR 0x1602 +#define mmDMCU_FW_START_ADDR 0x1603 +#define mmDMCU_FW_END_ADDR 0x1604 +#define mmDMCU_FW_ISR_START_ADDR 0x1605 +#define mmDMCU_FW_CS_HI 0x1606 +#define mmDMCU_FW_CS_LO 0x1607 +#define mmDMCU_RAM_ACCESS_CTRL 0x1608 +#define mmDMCU_ERAM_WR_CTRL 0x1609 +#define mmDMCU_ERAM_WR_DATA 0x160a +#define mmDMCU_ERAM_RD_CTRL 0x160b +#define mmDMCU_ERAM_RD_DATA 0x160c +#define mmDMCU_IRAM_WR_CTRL 0x160d +#define mmDMCU_IRAM_WR_DATA 0x160e +#define mmDMCU_IRAM_RD_CTRL 0x160f +#define mmDMCU_IRAM_RD_DATA 0x1610 +#define mmDMCU_EVENT_TRIGGER 0x1611 +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 +#define mmDMCU_INTERRUPT_STATUS 0x1614 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x1631 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x1632 +#define mmDC_DMCU_SCRATCH 0x1618 +#define mmDMCU_INT_CNT 0x1619 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a +#define mmDMCU_UC_CLK_GATING_CNTL 0x161b +#define mmMASTER_COMM_DATA_REG1 0x161c +#define mmMASTER_COMM_DATA_REG2 0x161d +#define mmMASTER_COMM_DATA_REG3 0x161e +#define mmMASTER_COMM_CMD_REG 0x161f +#define mmMASTER_COMM_CNTL_REG 0x1620 +#define mmSLAVE_COMM_DATA_REG1 0x1621 +#define mmSLAVE_COMM_DATA_REG2 0x1622 +#define mmSLAVE_COMM_DATA_REG3 0x1623 +#define mmSLAVE_COMM_CMD_REG 0x1624 +#define mmSLAVE_COMM_CNTL_REG 0x1625 +#define mmDMCU_TEST_DEBUG_INDEX 0x1626 +#define mmDMCU_TEST_DEBUG_DATA 0x1627 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673 +#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636 +#define mmDP_LINK_CNTL 0x4aa0 +#define mmDP0_DP_LINK_CNTL 0x4aa0 +#define mmDP1_DP_LINK_CNTL 0x4ba0 +#define mmDP2_DP_LINK_CNTL 0x4ca0 +#define mmDP3_DP_LINK_CNTL 0x4da0 +#define mmDP4_DP_LINK_CNTL 0x4ea0 +#define mmDP5_DP_LINK_CNTL 0x4fa0 +#define mmDP6_DP_LINK_CNTL 0x54a0 +#define mmDP7_DP_LINK_CNTL 0x56a0 +#define mmDP8_DP_LINK_CNTL 0x57a0 +#define mmDP_PIXEL_FORMAT 0x4aa1 +#define mmDP0_DP_PIXEL_FORMAT 0x4aa1 +#define mmDP1_DP_PIXEL_FORMAT 0x4ba1 +#define mmDP2_DP_PIXEL_FORMAT 0x4ca1 +#define mmDP3_DP_PIXEL_FORMAT 0x4da1 +#define mmDP4_DP_PIXEL_FORMAT 0x4ea1 +#define mmDP5_DP_PIXEL_FORMAT 0x4fa1 +#define mmDP6_DP_PIXEL_FORMAT 0x54a1 +#define mmDP7_DP_PIXEL_FORMAT 0x56a1 +#define mmDP8_DP_PIXEL_FORMAT 0x57a1 +#define mmDP_MSA_COLORIMETRY 0x4aa2 +#define mmDP0_DP_MSA_COLORIMETRY 0x4aa2 +#define mmDP1_DP_MSA_COLORIMETRY 0x4ba2 +#define mmDP2_DP_MSA_COLORIMETRY 0x4ca2 +#define mmDP3_DP_MSA_COLORIMETRY 0x4da2 +#define mmDP4_DP_MSA_COLORIMETRY 0x4ea2 +#define mmDP5_DP_MSA_COLORIMETRY 0x4fa2 +#define mmDP6_DP_MSA_COLORIMETRY 0x54a2 +#define mmDP7_DP_MSA_COLORIMETRY 0x56a2 +#define mmDP8_DP_MSA_COLORIMETRY 0x57a2 +#define mmDP_CONFIG 0x4aa3 +#define mmDP0_DP_CONFIG 0x4aa3 +#define mmDP1_DP_CONFIG 0x4ba3 +#define mmDP2_DP_CONFIG 0x4ca3 +#define mmDP3_DP_CONFIG 0x4da3 +#define mmDP4_DP_CONFIG 0x4ea3 +#define mmDP5_DP_CONFIG 0x4fa3 +#define mmDP6_DP_CONFIG 0x54a3 +#define mmDP7_DP_CONFIG 0x56a3 +#define mmDP8_DP_CONFIG 0x57a3 +#define mmDP_VID_STREAM_CNTL 0x4aa4 +#define mmDP0_DP_VID_STREAM_CNTL 0x4aa4 +#define mmDP1_DP_VID_STREAM_CNTL 0x4ba4 +#define mmDP2_DP_VID_STREAM_CNTL 0x4ca4 +#define mmDP3_DP_VID_STREAM_CNTL 0x4da4 +#define mmDP4_DP_VID_STREAM_CNTL 0x4ea4 +#define mmDP5_DP_VID_STREAM_CNTL 0x4fa4 +#define mmDP6_DP_VID_STREAM_CNTL 0x54a4 +#define mmDP7_DP_VID_STREAM_CNTL 0x56a4 +#define mmDP8_DP_VID_STREAM_CNTL 0x57a4 +#define mmDP_STEER_FIFO 0x4aa5 +#define mmDP0_DP_STEER_FIFO 0x4aa5 +#define mmDP1_DP_STEER_FIFO 0x4ba5 +#define mmDP2_DP_STEER_FIFO 0x4ca5 +#define mmDP3_DP_STEER_FIFO 0x4da5 +#define mmDP4_DP_STEER_FIFO 0x4ea5 +#define mmDP5_DP_STEER_FIFO 0x4fa5 +#define mmDP6_DP_STEER_FIFO 0x54a5 +#define mmDP7_DP_STEER_FIFO 0x56a5 +#define mmDP8_DP_STEER_FIFO 0x57a5 +#define mmDP_MSA_MISC 0x4aa6 +#define mmDP0_DP_MSA_MISC 0x4aa6 +#define mmDP1_DP_MSA_MISC 0x4ba6 +#define mmDP2_DP_MSA_MISC 0x4ca6 +#define mmDP3_DP_MSA_MISC 0x4da6 +#define mmDP4_DP_MSA_MISC 0x4ea6 +#define mmDP5_DP_MSA_MISC 0x4fa6 +#define mmDP6_DP_MSA_MISC 0x54a6 +#define mmDP7_DP_MSA_MISC 0x56a6 +#define mmDP8_DP_MSA_MISC 0x57a6 +#define mmDP_VID_TIMING 0x4aa8 +#define mmDP0_DP_VID_TIMING 0x4aa8 +#define mmDP1_DP_VID_TIMING 0x4ba8 +#define mmDP2_DP_VID_TIMING 0x4ca8 +#define mmDP3_DP_VID_TIMING 0x4da8 +#define mmDP4_DP_VID_TIMING 0x4ea8 +#define mmDP5_DP_VID_TIMING 0x4fa8 +#define mmDP6_DP_VID_TIMING 0x54a8 +#define mmDP7_DP_VID_TIMING 0x56a8 +#define mmDP8_DP_VID_TIMING 0x57a8 +#define mmDP_VID_N 0x4aa9 +#define mmDP0_DP_VID_N 0x4aa9 +#define mmDP1_DP_VID_N 0x4ba9 +#define mmDP2_DP_VID_N 0x4ca9 +#define mmDP3_DP_VID_N 0x4da9 +#define mmDP4_DP_VID_N 0x4ea9 +#define mmDP5_DP_VID_N 0x4fa9 +#define mmDP6_DP_VID_N 0x54a9 +#define mmDP7_DP_VID_N 0x56a9 +#define mmDP8_DP_VID_N 0x57a9 +#define mmDP_VID_M 0x4aaa +#define mmDP0_DP_VID_M 0x4aaa +#define mmDP1_DP_VID_M 0x4baa +#define mmDP2_DP_VID_M 0x4caa +#define mmDP3_DP_VID_M 0x4daa +#define mmDP4_DP_VID_M 0x4eaa +#define mmDP5_DP_VID_M 0x4faa +#define mmDP6_DP_VID_M 0x54aa +#define mmDP7_DP_VID_M 0x56aa +#define mmDP8_DP_VID_M 0x57aa +#define mmDP_LINK_FRAMING_CNTL 0x4aab +#define mmDP0_DP_LINK_FRAMING_CNTL 0x4aab +#define mmDP1_DP_LINK_FRAMING_CNTL 0x4bab +#define mmDP2_DP_LINK_FRAMING_CNTL 0x4cab +#define mmDP3_DP_LINK_FRAMING_CNTL 0x4dab +#define mmDP4_DP_LINK_FRAMING_CNTL 0x4eab +#define mmDP5_DP_LINK_FRAMING_CNTL 0x4fab +#define mmDP6_DP_LINK_FRAMING_CNTL 0x54ab +#define mmDP7_DP_LINK_FRAMING_CNTL 0x56ab +#define mmDP8_DP_LINK_FRAMING_CNTL 0x57ab +#define mmDP_HBR2_EYE_PATTERN 0x4aac +#define mmDP0_DP_HBR2_EYE_PATTERN 0x4aac +#define mmDP1_DP_HBR2_EYE_PATTERN 0x4bac +#define mmDP2_DP_HBR2_EYE_PATTERN 0x4cac +#define mmDP3_DP_HBR2_EYE_PATTERN 0x4dac +#define mmDP4_DP_HBR2_EYE_PATTERN 0x4eac +#define mmDP5_DP_HBR2_EYE_PATTERN 0x4fac +#define mmDP6_DP_HBR2_EYE_PATTERN 0x54ac +#define mmDP7_DP_HBR2_EYE_PATTERN 0x56ac +#define mmDP8_DP_HBR2_EYE_PATTERN 0x57ac +#define mmDP_VID_MSA_VBID 0x4aad +#define mmDP0_DP_VID_MSA_VBID 0x4aad +#define mmDP1_DP_VID_MSA_VBID 0x4bad +#define mmDP2_DP_VID_MSA_VBID 0x4cad +#define mmDP3_DP_VID_MSA_VBID 0x4dad +#define mmDP4_DP_VID_MSA_VBID 0x4ead +#define mmDP5_DP_VID_MSA_VBID 0x4fad +#define mmDP6_DP_VID_MSA_VBID 0x54ad +#define mmDP7_DP_VID_MSA_VBID 0x56ad +#define mmDP8_DP_VID_MSA_VBID 0x57ad +#define mmDP_VID_INTERRUPT_CNTL 0x4aae +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae +#define mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae +#define mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae +#define mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae +#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae +#define mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae +#define mmDP7_DP_VID_INTERRUPT_CNTL 0x56ae +#define mmDP8_DP_VID_INTERRUPT_CNTL 0x57ae +#define mmDP_DPHY_CNTL 0x4aaf +#define mmDP0_DP_DPHY_CNTL 0x4aaf +#define mmDP1_DP_DPHY_CNTL 0x4baf +#define mmDP2_DP_DPHY_CNTL 0x4caf +#define mmDP3_DP_DPHY_CNTL 0x4daf +#define mmDP4_DP_DPHY_CNTL 0x4eaf +#define mmDP5_DP_DPHY_CNTL 0x4faf +#define mmDP6_DP_DPHY_CNTL 0x54af +#define mmDP7_DP_DPHY_CNTL 0x56af +#define mmDP8_DP_DPHY_CNTL 0x57af +#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0 +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 +#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0 +#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0 +#define mmDP7_DP_DPHY_TRAINING_PATTERN_SEL 0x56b0 +#define mmDP8_DP_DPHY_TRAINING_PATTERN_SEL 0x57b0 +#define mmDP_DPHY_SYM0 0x4ab1 +#define mmDP0_DP_DPHY_SYM0 0x4ab1 +#define mmDP1_DP_DPHY_SYM0 0x4bb1 +#define mmDP2_DP_DPHY_SYM0 0x4cb1 +#define mmDP3_DP_DPHY_SYM0 0x4db1 +#define mmDP4_DP_DPHY_SYM0 0x4eb1 +#define mmDP5_DP_DPHY_SYM0 0x4fb1 +#define mmDP6_DP_DPHY_SYM0 0x54b1 +#define mmDP7_DP_DPHY_SYM0 0x56b1 +#define mmDP8_DP_DPHY_SYM0 0x57b1 +#define mmDP_DPHY_SYM1 0x4ab2 +#define mmDP0_DP_DPHY_SYM1 0x4ab2 +#define mmDP1_DP_DPHY_SYM1 0x4bb2 +#define mmDP2_DP_DPHY_SYM1 0x4cb2 +#define mmDP3_DP_DPHY_SYM1 0x4db2 +#define mmDP4_DP_DPHY_SYM1 0x4eb2 +#define mmDP5_DP_DPHY_SYM1 0x4fb2 +#define mmDP6_DP_DPHY_SYM1 0x54b2 +#define mmDP7_DP_DPHY_SYM1 0x56b2 +#define mmDP8_DP_DPHY_SYM1 0x57b2 +#define mmDP_DPHY_SYM2 0x4ab3 +#define mmDP0_DP_DPHY_SYM2 0x4ab3 +#define mmDP1_DP_DPHY_SYM2 0x4bb3 +#define mmDP2_DP_DPHY_SYM2 0x4cb3 +#define mmDP3_DP_DPHY_SYM2 0x4db3 +#define mmDP4_DP_DPHY_SYM2 0x4eb3 +#define mmDP5_DP_DPHY_SYM2 0x4fb3 +#define mmDP6_DP_DPHY_SYM2 0x54b3 +#define mmDP7_DP_DPHY_SYM2 0x56b3 +#define mmDP8_DP_DPHY_SYM2 0x57b3 +#define mmDP_DPHY_8B10B_CNTL 0x4ab4 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4 +#define mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4 +#define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 +#define mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4 +#define mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4 +#define mmDP6_DP_DPHY_8B10B_CNTL 0x54b4 +#define mmDP7_DP_DPHY_8B10B_CNTL 0x56b4 +#define mmDP8_DP_DPHY_8B10B_CNTL 0x57b4 +#define mmDP_DPHY_PRBS_CNTL 0x4ab5 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 +#define mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5 +#define mmDP3_DP_DPHY_PRBS_CNTL 0x4db5 +#define mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 +#define mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 +#define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 +#define mmDP7_DP_DPHY_PRBS_CNTL 0x56b5 +#define mmDP8_DP_DPHY_PRBS_CNTL 0x57b5 +#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4cdc +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc +#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc +#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54dc +#define mmDP7_DP_DPHY_BS_SR_SWAP_CNTL 0x56dc +#define mmDP8_DP_DPHY_BS_SR_SWAP_CNTL 0x57dc +#define mmDP_DPHY_CRC_EN 0x4ab7 +#define mmDP0_DP_DPHY_CRC_EN 0x4ab7 +#define mmDP1_DP_DPHY_CRC_EN 0x4bb7 +#define mmDP2_DP_DPHY_CRC_EN 0x4cb7 +#define mmDP3_DP_DPHY_CRC_EN 0x4db7 +#define mmDP4_DP_DPHY_CRC_EN 0x4eb7 +#define mmDP5_DP_DPHY_CRC_EN 0x4fb7 +#define mmDP6_DP_DPHY_CRC_EN 0x54b7 +#define mmDP7_DP_DPHY_CRC_EN 0x56b7 +#define mmDP8_DP_DPHY_CRC_EN 0x57b7 +#define mmDP_DPHY_CRC_CNTL 0x4ab8 +#define mmDP0_DP_DPHY_CRC_CNTL 0x4ab8 +#define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 +#define mmDP2_DP_DPHY_CRC_CNTL 0x4cb8 +#define mmDP3_DP_DPHY_CRC_CNTL 0x4db8 +#define mmDP4_DP_DPHY_CRC_CNTL 0x4eb8 +#define mmDP5_DP_DPHY_CRC_CNTL 0x4fb8 +#define mmDP6_DP_DPHY_CRC_CNTL 0x54b8 +#define mmDP7_DP_DPHY_CRC_CNTL 0x56b8 +#define mmDP8_DP_DPHY_CRC_CNTL 0x57b8 +#define mmDP_DPHY_CRC_RESULT 0x4ab9 +#define mmDP0_DP_DPHY_CRC_RESULT 0x4ab9 +#define mmDP1_DP_DPHY_CRC_RESULT 0x4bb9 +#define mmDP2_DP_DPHY_CRC_RESULT 0x4cb9 +#define mmDP3_DP_DPHY_CRC_RESULT 0x4db9 +#define mmDP4_DP_DPHY_CRC_RESULT 0x4eb9 +#define mmDP5_DP_DPHY_CRC_RESULT 0x4fb9 +#define mmDP6_DP_DPHY_CRC_RESULT 0x54b9 +#define mmDP7_DP_DPHY_CRC_RESULT 0x56b9 +#define mmDP8_DP_DPHY_CRC_RESULT 0x57b9 +#define mmDP_DPHY_CRC_MST_CNTL 0x4aba +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba +#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba +#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba +#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba +#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba +#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba +#define mmDP7_DP_DPHY_CRC_MST_CNTL 0x56ba +#define mmDP8_DP_DPHY_CRC_MST_CNTL 0x57ba +#define mmDP_DPHY_CRC_MST_STATUS 0x4abb +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb +#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb +#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb +#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb +#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb +#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb +#define mmDP7_DP_DPHY_CRC_MST_STATUS 0x56bb +#define mmDP8_DP_DPHY_CRC_MST_STATUS 0x57bb +#define mmDP_DPHY_FAST_TRAINING 0x4abc +#define mmDP0_DP_DPHY_FAST_TRAINING 0x4abc +#define mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc +#define mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc +#define mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc +#define mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc +#define mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc +#define mmDP6_DP_DPHY_FAST_TRAINING 0x54bc +#define mmDP7_DP_DPHY_FAST_TRAINING 0x56bc +#define mmDP8_DP_DPHY_FAST_TRAINING 0x57bc +#define mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd +#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd +#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd +#define mmDP7_DP_DPHY_FAST_TRAINING_STATUS 0x56bd +#define mmDP8_DP_DPHY_FAST_TRAINING_STATUS 0x57bd +#define mmDP_DPHY_HBR2_PATTERN_CONTROL 0x4add +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x4add +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x4bdd +#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x4cdd +#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x4ddd +#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x4edd +#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x4fdd +#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x54dd +#define mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL 0x56dd +#define mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL 0x57dd +#define mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be +#define mmDP7_DP_MSA_V_TIMING_OVERRIDE1 0x56be +#define mmDP8_DP_MSA_V_TIMING_OVERRIDE1 0x57be +#define mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf +#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf +#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf +#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf +#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf +#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf +#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf +#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf +#define mmDP7_DP_MSA_V_TIMING_OVERRIDE2 0x56bf +#define mmDP8_DP_MSA_V_TIMING_OVERRIDE2 0x57bf +#define mmDP_SEC_CNTL 0x4ac3 +#define mmDP0_DP_SEC_CNTL 0x4ac3 +#define mmDP1_DP_SEC_CNTL 0x4bc3 +#define mmDP2_DP_SEC_CNTL 0x4cc3 +#define mmDP3_DP_SEC_CNTL 0x4dc3 +#define mmDP4_DP_SEC_CNTL 0x4ec3 +#define mmDP5_DP_SEC_CNTL 0x4fc3 +#define mmDP6_DP_SEC_CNTL 0x54c3 +#define mmDP7_DP_SEC_CNTL 0x56c3 +#define mmDP8_DP_SEC_CNTL 0x57c3 +#define mmDP_SEC_CNTL1 0x4ac4 +#define mmDP0_DP_SEC_CNTL1 0x4ac4 +#define mmDP1_DP_SEC_CNTL1 0x4bc4 +#define mmDP2_DP_SEC_CNTL1 0x4cc4 +#define mmDP3_DP_SEC_CNTL1 0x4dc4 +#define mmDP4_DP_SEC_CNTL1 0x4ec4 +#define mmDP5_DP_SEC_CNTL1 0x4fc4 +#define mmDP6_DP_SEC_CNTL1 0x54c4 +#define mmDP7_DP_SEC_CNTL1 0x56c4 +#define mmDP8_DP_SEC_CNTL1 0x57c4 +#define mmDP_SEC_FRAMING1 0x4ac5 +#define mmDP0_DP_SEC_FRAMING1 0x4ac5 +#define mmDP1_DP_SEC_FRAMING1 0x4bc5 +#define mmDP2_DP_SEC_FRAMING1 0x4cc5 +#define mmDP3_DP_SEC_FRAMING1 0x4dc5 +#define mmDP4_DP_SEC_FRAMING1 0x4ec5 +#define mmDP5_DP_SEC_FRAMING1 0x4fc5 +#define mmDP6_DP_SEC_FRAMING1 0x54c5 +#define mmDP7_DP_SEC_FRAMING1 0x56c5 +#define mmDP8_DP_SEC_FRAMING1 0x57c5 +#define mmDP_SEC_FRAMING2 0x4ac6 +#define mmDP0_DP_SEC_FRAMING2 0x4ac6 +#define mmDP1_DP_SEC_FRAMING2 0x4bc6 +#define mmDP2_DP_SEC_FRAMING2 0x4cc6 +#define mmDP3_DP_SEC_FRAMING2 0x4dc6 +#define mmDP4_DP_SEC_FRAMING2 0x4ec6 +#define mmDP5_DP_SEC_FRAMING2 0x4fc6 +#define mmDP6_DP_SEC_FRAMING2 0x54c6 +#define mmDP7_DP_SEC_FRAMING2 0x56c6 +#define mmDP8_DP_SEC_FRAMING2 0x57c6 +#define mmDP_SEC_FRAMING3 0x4ac7 +#define mmDP0_DP_SEC_FRAMING3 0x4ac7 +#define mmDP1_DP_SEC_FRAMING3 0x4bc7 +#define mmDP2_DP_SEC_FRAMING3 0x4cc7 +#define mmDP3_DP_SEC_FRAMING3 0x4dc7 +#define mmDP4_DP_SEC_FRAMING3 0x4ec7 +#define mmDP5_DP_SEC_FRAMING3 0x4fc7 +#define mmDP6_DP_SEC_FRAMING3 0x54c7 +#define mmDP7_DP_SEC_FRAMING3 0x56c7 +#define mmDP8_DP_SEC_FRAMING3 0x57c7 +#define mmDP_SEC_FRAMING4 0x4ac8 +#define mmDP0_DP_SEC_FRAMING4 0x4ac8 +#define mmDP1_DP_SEC_FRAMING4 0x4bc8 +#define mmDP2_DP_SEC_FRAMING4 0x4cc8 +#define mmDP3_DP_SEC_FRAMING4 0x4dc8 +#define mmDP4_DP_SEC_FRAMING4 0x4ec8 +#define mmDP5_DP_SEC_FRAMING4 0x4fc8 +#define mmDP6_DP_SEC_FRAMING4 0x54c8 +#define mmDP7_DP_SEC_FRAMING4 0x56c8 +#define mmDP8_DP_SEC_FRAMING4 0x57c8 +#define mmDP_SEC_AUD_N 0x4ac9 +#define mmDP0_DP_SEC_AUD_N 0x4ac9 +#define mmDP1_DP_SEC_AUD_N 0x4bc9 +#define mmDP2_DP_SEC_AUD_N 0x4cc9 +#define mmDP3_DP_SEC_AUD_N 0x4dc9 +#define mmDP4_DP_SEC_AUD_N 0x4ec9 +#define mmDP5_DP_SEC_AUD_N 0x4fc9 +#define mmDP6_DP_SEC_AUD_N 0x54c9 +#define mmDP7_DP_SEC_AUD_N 0x56c9 +#define mmDP8_DP_SEC_AUD_N 0x57c9 +#define mmDP_SEC_AUD_N_READBACK 0x4aca +#define mmDP0_DP_SEC_AUD_N_READBACK 0x4aca +#define mmDP1_DP_SEC_AUD_N_READBACK 0x4bca +#define mmDP2_DP_SEC_AUD_N_READBACK 0x4cca +#define mmDP3_DP_SEC_AUD_N_READBACK 0x4dca +#define mmDP4_DP_SEC_AUD_N_READBACK 0x4eca +#define mmDP5_DP_SEC_AUD_N_READBACK 0x4fca +#define mmDP6_DP_SEC_AUD_N_READBACK 0x54ca +#define mmDP7_DP_SEC_AUD_N_READBACK 0x56ca +#define mmDP8_DP_SEC_AUD_N_READBACK 0x57ca +#define mmDP_SEC_AUD_M 0x4acb +#define mmDP0_DP_SEC_AUD_M 0x4acb +#define mmDP1_DP_SEC_AUD_M 0x4bcb +#define mmDP2_DP_SEC_AUD_M 0x4ccb +#define mmDP3_DP_SEC_AUD_M 0x4dcb +#define mmDP4_DP_SEC_AUD_M 0x4ecb +#define mmDP5_DP_SEC_AUD_M 0x4fcb +#define mmDP6_DP_SEC_AUD_M 0x54cb +#define mmDP7_DP_SEC_AUD_M 0x56cb +#define mmDP8_DP_SEC_AUD_M 0x57cb +#define mmDP_SEC_AUD_M_READBACK 0x4acc +#define mmDP0_DP_SEC_AUD_M_READBACK 0x4acc +#define mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc +#define mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc +#define mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc +#define mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc +#define mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc +#define mmDP6_DP_SEC_AUD_M_READBACK 0x54cc +#define mmDP7_DP_SEC_AUD_M_READBACK 0x56cc +#define mmDP8_DP_SEC_AUD_M_READBACK 0x57cc +#define mmDP_SEC_TIMESTAMP 0x4acd +#define mmDP0_DP_SEC_TIMESTAMP 0x4acd +#define mmDP1_DP_SEC_TIMESTAMP 0x4bcd +#define mmDP2_DP_SEC_TIMESTAMP 0x4ccd +#define mmDP3_DP_SEC_TIMESTAMP 0x4dcd +#define mmDP4_DP_SEC_TIMESTAMP 0x4ecd +#define mmDP5_DP_SEC_TIMESTAMP 0x4fcd +#define mmDP6_DP_SEC_TIMESTAMP 0x54cd +#define mmDP7_DP_SEC_TIMESTAMP 0x56cd +#define mmDP8_DP_SEC_TIMESTAMP 0x57cd +#define mmDP_SEC_PACKET_CNTL 0x4ace +#define mmDP0_DP_SEC_PACKET_CNTL 0x4ace +#define mmDP1_DP_SEC_PACKET_CNTL 0x4bce +#define mmDP2_DP_SEC_PACKET_CNTL 0x4cce +#define mmDP3_DP_SEC_PACKET_CNTL 0x4dce +#define mmDP4_DP_SEC_PACKET_CNTL 0x4ece +#define mmDP5_DP_SEC_PACKET_CNTL 0x4fce +#define mmDP6_DP_SEC_PACKET_CNTL 0x54ce +#define mmDP7_DP_SEC_PACKET_CNTL 0x56ce +#define mmDP8_DP_SEC_PACKET_CNTL 0x57ce +#define mmDP_MSE_RATE_CNTL 0x4acf +#define mmDP0_DP_MSE_RATE_CNTL 0x4acf +#define mmDP1_DP_MSE_RATE_CNTL 0x4bcf +#define mmDP2_DP_MSE_RATE_CNTL 0x4ccf +#define mmDP3_DP_MSE_RATE_CNTL 0x4dcf +#define mmDP4_DP_MSE_RATE_CNTL 0x4ecf +#define mmDP5_DP_MSE_RATE_CNTL 0x4fcf +#define mmDP6_DP_MSE_RATE_CNTL 0x54cf +#define mmDP7_DP_MSE_RATE_CNTL 0x56cf +#define mmDP8_DP_MSE_RATE_CNTL 0x57cf +#define mmDP_MSE_RATE_UPDATE 0x4ad1 +#define mmDP0_DP_MSE_RATE_UPDATE 0x4ad1 +#define mmDP1_DP_MSE_RATE_UPDATE 0x4bd1 +#define mmDP2_DP_MSE_RATE_UPDATE 0x4cd1 +#define mmDP3_DP_MSE_RATE_UPDATE 0x4dd1 +#define mmDP4_DP_MSE_RATE_UPDATE 0x4ed1 +#define mmDP5_DP_MSE_RATE_UPDATE 0x4fd1 +#define mmDP6_DP_MSE_RATE_UPDATE 0x54d1 +#define mmDP7_DP_MSE_RATE_UPDATE 0x56d1 +#define mmDP8_DP_MSE_RATE_UPDATE 0x57d1 +#define mmDP_MSE_SAT0 0x4ad2 +#define mmDP0_DP_MSE_SAT0 0x4ad2 +#define mmDP1_DP_MSE_SAT0 0x4bd2 +#define mmDP2_DP_MSE_SAT0 0x4cd2 +#define mmDP3_DP_MSE_SAT0 0x4dd2 +#define mmDP4_DP_MSE_SAT0 0x4ed2 +#define mmDP5_DP_MSE_SAT0 0x4fd2 +#define mmDP6_DP_MSE_SAT0 0x54d2 +#define mmDP7_DP_MSE_SAT0 0x56d2 +#define mmDP8_DP_MSE_SAT0 0x57d2 +#define mmDP_MSE_SAT1 0x4ad3 +#define mmDP0_DP_MSE_SAT1 0x4ad3 +#define mmDP1_DP_MSE_SAT1 0x4bd3 +#define mmDP2_DP_MSE_SAT1 0x4cd3 +#define mmDP3_DP_MSE_SAT1 0x4dd3 +#define mmDP4_DP_MSE_SAT1 0x4ed3 +#define mmDP5_DP_MSE_SAT1 0x4fd3 +#define mmDP6_DP_MSE_SAT1 0x54d3 +#define mmDP7_DP_MSE_SAT1 0x56d3 +#define mmDP8_DP_MSE_SAT1 0x57d3 +#define mmDP_MSE_SAT2 0x4ad4 +#define mmDP0_DP_MSE_SAT2 0x4ad4 +#define mmDP1_DP_MSE_SAT2 0x4bd4 +#define mmDP2_DP_MSE_SAT2 0x4cd4 +#define mmDP3_DP_MSE_SAT2 0x4dd4 +#define mmDP4_DP_MSE_SAT2 0x4ed4 +#define mmDP5_DP_MSE_SAT2 0x4fd4 +#define mmDP6_DP_MSE_SAT2 0x54d4 +#define mmDP7_DP_MSE_SAT2 0x56d4 +#define mmDP8_DP_MSE_SAT2 0x57d4 +#define mmDP_MSE_SAT_UPDATE 0x4ad5 +#define mmDP0_DP_MSE_SAT_UPDATE 0x4ad5 +#define mmDP1_DP_MSE_SAT_UPDATE 0x4bd5 +#define mmDP2_DP_MSE_SAT_UPDATE 0x4cd5 +#define mmDP3_DP_MSE_SAT_UPDATE 0x4dd5 +#define mmDP4_DP_MSE_SAT_UPDATE 0x4ed5 +#define mmDP5_DP_MSE_SAT_UPDATE 0x4fd5 +#define mmDP6_DP_MSE_SAT_UPDATE 0x54d5 +#define mmDP7_DP_MSE_SAT_UPDATE 0x56d5 +#define mmDP8_DP_MSE_SAT_UPDATE 0x57d5 +#define mmDP_MSE_LINK_TIMING 0x4ad6 +#define mmDP0_DP_MSE_LINK_TIMING 0x4ad6 +#define mmDP1_DP_MSE_LINK_TIMING 0x4bd6 +#define mmDP2_DP_MSE_LINK_TIMING 0x4cd6 +#define mmDP3_DP_MSE_LINK_TIMING 0x4dd6 +#define mmDP4_DP_MSE_LINK_TIMING 0x4ed6 +#define mmDP5_DP_MSE_LINK_TIMING 0x4fd6 +#define mmDP6_DP_MSE_LINK_TIMING 0x54d6 +#define mmDP7_DP_MSE_LINK_TIMING 0x56d6 +#define mmDP8_DP_MSE_LINK_TIMING 0x57d6 +#define mmDP_MSE_MISC_CNTL 0x4ad7 +#define mmDP0_DP_MSE_MISC_CNTL 0x4ad7 +#define mmDP1_DP_MSE_MISC_CNTL 0x4bd7 +#define mmDP2_DP_MSE_MISC_CNTL 0x4cd7 +#define mmDP3_DP_MSE_MISC_CNTL 0x4dd7 +#define mmDP4_DP_MSE_MISC_CNTL 0x4ed7 +#define mmDP5_DP_MSE_MISC_CNTL 0x4fd7 +#define mmDP6_DP_MSE_MISC_CNTL 0x54d7 +#define mmDP7_DP_MSE_MISC_CNTL 0x56d7 +#define mmDP8_DP_MSE_MISC_CNTL 0x57d7 +#define mmDP_TEST_DEBUG_INDEX 0x4ad8 +#define mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8 +#define mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8 +#define mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8 +#define mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8 +#define mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8 +#define mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8 +#define mmDP6_DP_TEST_DEBUG_INDEX 0x54d8 +#define mmDP7_DP_TEST_DEBUG_INDEX 0x56d8 +#define mmDP8_DP_TEST_DEBUG_INDEX 0x57d8 +#define mmDP_TEST_DEBUG_DATA 0x4ad9 +#define mmDP0_DP_TEST_DEBUG_DATA 0x4ad9 +#define mmDP1_DP_TEST_DEBUG_DATA 0x4bd9 +#define mmDP2_DP_TEST_DEBUG_DATA 0x4cd9 +#define mmDP3_DP_TEST_DEBUG_DATA 0x4dd9 +#define mmDP4_DP_TEST_DEBUG_DATA 0x4ed9 +#define mmDP5_DP_TEST_DEBUG_DATA 0x4fd9 +#define mmDP6_DP_TEST_DEBUG_DATA 0x54d9 +#define mmDP7_DP_TEST_DEBUG_DATA 0x56d9 +#define mmDP8_DP_TEST_DEBUG_DATA 0x57d9 +#define mmDP_FE_TEST_DEBUG_INDEX 0x4ada +#define mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada +#define mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda +#define mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda +#define mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda +#define mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda +#define mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda +#define mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da +#define mmDP7_DP_FE_TEST_DEBUG_INDEX 0x56da +#define mmDP8_DP_FE_TEST_DEBUG_INDEX 0x57da +#define mmDP_FE_TEST_DEBUG_DATA 0x4adb +#define mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb +#define mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb +#define mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb +#define mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb +#define mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb +#define mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb +#define mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db +#define mmDP7_DP_FE_TEST_DEBUG_DATA 0x56db +#define mmDP8_DP_FE_TEST_DEBUG_DATA 0x57db +#define mmAUX_CONTROL 0x5c00 +#define mmDP_AUX0_AUX_CONTROL 0x5c00 +#define mmDP_AUX1_AUX_CONTROL 0x5c1c +#define mmDP_AUX2_AUX_CONTROL 0x5c38 +#define mmDP_AUX3_AUX_CONTROL 0x5c54 +#define mmDP_AUX4_AUX_CONTROL 0x5c70 +#define mmDP_AUX5_AUX_CONTROL 0x5c8c +#define mmAUX_SW_CONTROL 0x5c01 +#define mmDP_AUX0_AUX_SW_CONTROL 0x5c01 +#define mmDP_AUX1_AUX_SW_CONTROL 0x5c1d +#define mmDP_AUX2_AUX_SW_CONTROL 0x5c39 +#define mmDP_AUX3_AUX_SW_CONTROL 0x5c55 +#define mmDP_AUX4_AUX_SW_CONTROL 0x5c71 +#define mmDP_AUX5_AUX_SW_CONTROL 0x5c8d +#define mmAUX_ARB_CONTROL 0x5c02 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x5c02 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e +#define mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a +#define mmDP_AUX3_AUX_ARB_CONTROL 0x5c56 +#define mmDP_AUX4_AUX_ARB_CONTROL 0x5c72 +#define mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e +#define mmAUX_INTERRUPT_CONTROL 0x5c03 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73 +#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f +#define mmAUX_SW_STATUS 0x5c04 +#define mmDP_AUX0_AUX_SW_STATUS 0x5c04 +#define mmDP_AUX1_AUX_SW_STATUS 0x5c20 +#define mmDP_AUX2_AUX_SW_STATUS 0x5c3c +#define mmDP_AUX3_AUX_SW_STATUS 0x5c58 +#define mmDP_AUX4_AUX_SW_STATUS 0x5c74 +#define mmDP_AUX5_AUX_SW_STATUS 0x5c90 +#define mmAUX_LS_STATUS 0x5c05 +#define mmDP_AUX0_AUX_LS_STATUS 0x5c05 +#define mmDP_AUX1_AUX_LS_STATUS 0x5c21 +#define mmDP_AUX2_AUX_LS_STATUS 0x5c3d +#define mmDP_AUX3_AUX_LS_STATUS 0x5c59 +#define mmDP_AUX4_AUX_LS_STATUS 0x5c75 +#define mmDP_AUX5_AUX_LS_STATUS 0x5c91 +#define mmAUX_SW_DATA 0x5c06 +#define mmDP_AUX0_AUX_SW_DATA 0x5c06 +#define mmDP_AUX1_AUX_SW_DATA 0x5c22 +#define mmDP_AUX2_AUX_SW_DATA 0x5c3e +#define mmDP_AUX3_AUX_SW_DATA 0x5c5a +#define mmDP_AUX4_AUX_SW_DATA 0x5c76 +#define mmDP_AUX5_AUX_SW_DATA 0x5c92 +#define mmAUX_LS_DATA 0x5c07 +#define mmDP_AUX0_AUX_LS_DATA 0x5c07 +#define mmDP_AUX1_AUX_LS_DATA 0x5c23 +#define mmDP_AUX2_AUX_LS_DATA 0x5c3f +#define mmDP_AUX3_AUX_LS_DATA 0x5c5b +#define mmDP_AUX4_AUX_LS_DATA 0x5c77 +#define mmDP_AUX5_AUX_LS_DATA 0x5c93 +#define mmAUX_DPHY_TX_REF_CONTROL 0x5c08 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78 +#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94 +#define mmAUX_DPHY_TX_CONTROL 0x5c09 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41 +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79 +#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95 +#define mmAUX_DPHY_RX_CONTROL0 0x5c0a +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96 +#define mmAUX_DPHY_RX_CONTROL1 0x5c0b +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b +#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97 +#define mmAUX_DPHY_TX_STATUS 0x5c0c +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60 +#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c +#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98 +#define mmAUX_DPHY_RX_STATUS 0x5c0d +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61 +#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d +#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99 +#define mmAUX_GTC_SYNC_CONTROL 0x5c0e +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a +#define mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63 +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f +#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b +#define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80 +#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c +#define mmAUX_GTC_SYNC_STATUS 0x5c11 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11 +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49 +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81 +#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d +#define mmAUX_GTC_SYNC_DATA 0x5c12 +#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12 +#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e +#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a +#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66 +#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82 +#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e +#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 +#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 +#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f +#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b +#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67 +#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83 +#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f +#define mmAUX_TEST_DEBUG_INDEX 0x5c14 +#define mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14 +#define mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30 +#define mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c +#define mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68 +#define mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84 +#define mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0 +#define mmAUX_TEST_DEBUG_DATA 0x5c15 +#define mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15 +#define mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31 +#define mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d +#define mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69 +#define mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85 +#define mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1 +#define ixDP_AUX_DEBUG_A 0x10 +#define ixDP_AUX_DEBUG_B 0x11 +#define ixDP_AUX_DEBUG_C 0x12 +#define ixDP_AUX_DEBUG_D 0x13 +#define ixDP_AUX_DEBUG_E 0x14 +#define ixDP_AUX_DEBUG_F 0x15 +#define ixDP_AUX_DEBUG_G 0x16 +#define ixDP_AUX_DEBUG_H 0x17 +#define ixDP_AUX_DEBUG_I 0x18 +#define ixDP_AUX_DEBUG_J 0x19 +#define ixDP_AUX_DEBUG_K 0x1a +#define ixDP_AUX_DEBUG_L 0x1b +#define ixDP_AUX_DEBUG_M 0x1c +#define ixDP_AUX_DEBUG_N 0x1d +#define ixDP_AUX_DEBUG_O 0x1e +#define ixDP_AUX_DEBUG_P 0x1f +#define ixDP_AUX_DEBUG_Q 0x20 +#define mmDVO_ENABLE 0x16a0 +#define mmDVO_SOURCE_SELECT 0x16a1 +#define mmDVO_OUTPUT 0x16a2 +#define mmDVO_CONTROL 0x16a3 +#define mmDVO_CRC_EN 0x16a4 +#define mmDVO_CRC2_SIG_MASK 0x16a5 +#define mmDVO_CRC2_SIG_RESULT 0x16a6 +#define mmDVO_FIFO_ERROR_STATUS 0x16a7 +#define mmDVO_TEST_DEBUG_INDEX 0x16a8 +#define mmDVO_TEST_DEBUG_DATA 0x16a9 +#define mmFBC_CNTL 0x280 +#define mmFBC_IDLE_MASK 0x281 +#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x282 +#define mmFBC_START_STOP_DELAY 0x283 +#define mmFBC_COMP_CNTL 0x284 +#define mmFBC_COMP_MODE 0x285 +#define mmFBC_DEBUG0 0x286 +#define mmFBC_DEBUG1 0x287 +#define mmFBC_DEBUG2 0x288 +#define mmFBC_IND_LUT0 0x289 +#define mmFBC_IND_LUT1 0x28a +#define mmFBC_IND_LUT2 0x28b +#define mmFBC_IND_LUT3 0x28c +#define mmFBC_IND_LUT4 0x28d +#define mmFBC_IND_LUT5 0x28e +#define mmFBC_IND_LUT6 0x28f +#define mmFBC_IND_LUT7 0x290 +#define mmFBC_IND_LUT8 0x291 +#define mmFBC_IND_LUT9 0x292 +#define mmFBC_IND_LUT10 0x293 +#define mmFBC_IND_LUT11 0x294 +#define mmFBC_IND_LUT12 0x295 +#define mmFBC_IND_LUT13 0x296 +#define mmFBC_IND_LUT14 0x297 +#define mmFBC_IND_LUT15 0x298 +#define mmFBC_CSM_REGION_OFFSET_01 0x299 +#define mmFBC_CSM_REGION_OFFSET_23 0x29a +#define mmFBC_CLIENT_REGION_MASK 0x29b +#define mmFBC_DEBUG_COMP 0x29c +#define mmFBC_DEBUG_CSR 0x29d +#define mmFBC_DEBUG_CSR_RDATA 0x29e +#define mmFBC_DEBUG_CSR_WDATA 0x29f +#define mmFBC_DEBUG_CSR_RDATA_HI 0x2a0 +#define mmFBC_DEBUG_CSR_WDATA_HI 0x2a1 +#define mmFBC_MISC 0x2a2 +#define mmFBC_STATUS 0x2a3 +#define mmFBC_TEST_DEBUG_INDEX 0x2a4 +#define mmFBC_TEST_DEBUG_DATA 0x2a5 +#define mmFMT_CLAMP_COMPONENT_R 0x1be8 +#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 +#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8 +#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8 +#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8 +#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8 +#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8 +#define mmFMT_CLAMP_COMPONENT_G 0x1be9 +#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 +#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9 +#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9 +#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9 +#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9 +#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9 +#define mmFMT_CLAMP_COMPONENT_B 0x1bea +#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea +#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea +#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea +#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea +#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea +#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea +#define mmFMT_DYNAMIC_EXP_CNTL 0x1bed +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed +#define mmFMT_CONTROL 0x1bee +#define mmFMT0_FMT_CONTROL 0x1bee +#define mmFMT1_FMT_CONTROL 0x1dee +#define mmFMT2_FMT_CONTROL 0x1fee +#define mmFMT3_FMT_CONTROL 0x41ee +#define mmFMT4_FMT_CONTROL 0x43ee +#define mmFMT5_FMT_CONTROL 0x45ee +#define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2 +#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2 +#define mmFMT_DITHER_RAND_R_SEED 0x1bf3 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3 +#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3 +#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3 +#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3 +#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3 +#define mmFMT_DITHER_RAND_G_SEED 0x1bf4 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4 +#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4 +#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4 +#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4 +#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4 +#define mmFMT_DITHER_RAND_B_SEED 0x1bf5 +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5 +#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5 +#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5 +#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5 +#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5 +#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 +#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6 +#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6 +#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 +#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6 +#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7 +#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 +#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8 +#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8 +#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 +#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8 +#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8 +#define mmFMT_CLAMP_CNTL 0x1bf9 +#define mmFMT0_FMT_CLAMP_CNTL 0x1bf9 +#define mmFMT1_FMT_CLAMP_CNTL 0x1df9 +#define mmFMT2_FMT_CLAMP_CNTL 0x1ff9 +#define mmFMT3_FMT_CLAMP_CNTL 0x41f9 +#define mmFMT4_FMT_CLAMP_CNTL 0x43f9 +#define mmFMT5_FMT_CLAMP_CNTL 0x45f9 +#define mmFMT_CRC_CNTL 0x1bfa +#define mmFMT0_FMT_CRC_CNTL 0x1bfa +#define mmFMT1_FMT_CRC_CNTL 0x1dfa +#define mmFMT2_FMT_CRC_CNTL 0x1ffa +#define mmFMT3_FMT_CRC_CNTL 0x41fa +#define mmFMT4_FMT_CRC_CNTL 0x43fa +#define mmFMT5_FMT_CRC_CNTL 0x45fa +#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb +#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb +#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb +#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb +#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb +#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb +#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc +#define mmFMT_CRC_SIG_RED_GREEN 0x1bfd +#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd +#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd +#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd +#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd +#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd +#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd +#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe +#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe +#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe +#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe +#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe +#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe +#define mmFMT_DEBUG_CNTL 0x1bff +#define mmFMT0_FMT_DEBUG_CNTL 0x1bff +#define mmFMT1_FMT_DEBUG_CNTL 0x1dff +#define mmFMT2_FMT_DEBUG_CNTL 0x1fff +#define mmFMT3_FMT_DEBUG_CNTL 0x41ff +#define mmFMT4_FMT_DEBUG_CNTL 0x43ff +#define mmFMT5_FMT_DEBUG_CNTL 0x45ff +#define mmFMT_TEST_DEBUG_INDEX 0x1beb +#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb +#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb +#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb +#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb +#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb +#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb +#define mmFMT_TEST_DEBUG_DATA 0x1bec +#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec +#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec +#define mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec +#define mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec +#define mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec +#define mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec +#define ixFMT_DEBUG0 0x1 +#define ixFMT_DEBUG1 0x2 +#define ixFMT_DEBUG2 0x3 +#define ixFMT_DEBUG_ID 0x0 +#define mmLB_DATA_FORMAT 0x1ac0 +#define mmLB0_LB_DATA_FORMAT 0x1ac0 +#define mmLB1_LB_DATA_FORMAT 0x1cc0 +#define mmLB2_LB_DATA_FORMAT 0x1ec0 +#define mmLB3_LB_DATA_FORMAT 0x40c0 +#define mmLB4_LB_DATA_FORMAT 0x42c0 +#define mmLB5_LB_DATA_FORMAT 0x44c0 +#define mmLB_MEMORY_CTRL 0x1ac1 +#define mmLB0_LB_MEMORY_CTRL 0x1ac1 +#define mmLB1_LB_MEMORY_CTRL 0x1cc1 +#define mmLB2_LB_MEMORY_CTRL 0x1ec1 +#define mmLB3_LB_MEMORY_CTRL 0x40c1 +#define mmLB4_LB_MEMORY_CTRL 0x42c1 +#define mmLB5_LB_MEMORY_CTRL 0x44c1 +#define mmLB_MEMORY_SIZE_STATUS 0x1ac2 +#define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 +#define mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2 +#define mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2 +#define mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2 +#define mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2 +#define mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2 +#define mmLB_DESKTOP_HEIGHT 0x1ac3 +#define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 +#define mmLB1_LB_DESKTOP_HEIGHT 0x1cc3 +#define mmLB2_LB_DESKTOP_HEIGHT 0x1ec3 +#define mmLB3_LB_DESKTOP_HEIGHT 0x40c3 +#define mmLB4_LB_DESKTOP_HEIGHT 0x42c3 +#define mmLB5_LB_DESKTOP_HEIGHT 0x44c3 +#define mmLB_VLINE_START_END 0x1ac4 +#define mmLB0_LB_VLINE_START_END 0x1ac4 +#define mmLB1_LB_VLINE_START_END 0x1cc4 +#define mmLB2_LB_VLINE_START_END 0x1ec4 +#define mmLB3_LB_VLINE_START_END 0x40c4 +#define mmLB4_LB_VLINE_START_END 0x42c4 +#define mmLB5_LB_VLINE_START_END 0x44c4 +#define mmLB_VLINE2_START_END 0x1ac5 +#define mmLB0_LB_VLINE2_START_END 0x1ac5 +#define mmLB1_LB_VLINE2_START_END 0x1cc5 +#define mmLB2_LB_VLINE2_START_END 0x1ec5 +#define mmLB3_LB_VLINE2_START_END 0x40c5 +#define mmLB4_LB_VLINE2_START_END 0x42c5 +#define mmLB5_LB_VLINE2_START_END 0x44c5 +#define mmLB_V_COUNTER 0x1ac6 +#define mmLB0_LB_V_COUNTER 0x1ac6 +#define mmLB1_LB_V_COUNTER 0x1cc6 +#define mmLB2_LB_V_COUNTER 0x1ec6 +#define mmLB3_LB_V_COUNTER 0x40c6 +#define mmLB4_LB_V_COUNTER 0x42c6 +#define mmLB5_LB_V_COUNTER 0x44c6 +#define mmLB_SNAPSHOT_V_COUNTER 0x1ac7 +#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 +#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7 +#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7 +#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7 +#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7 +#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7 +#define mmLB_INTERRUPT_MASK 0x1ac8 +#define mmLB0_LB_INTERRUPT_MASK 0x1ac8 +#define mmLB1_LB_INTERRUPT_MASK 0x1cc8 +#define mmLB2_LB_INTERRUPT_MASK 0x1ec8 +#define mmLB3_LB_INTERRUPT_MASK 0x40c8 +#define mmLB4_LB_INTERRUPT_MASK 0x42c8 +#define mmLB5_LB_INTERRUPT_MASK 0x44c8 +#define mmLB_VLINE_STATUS 0x1ac9 +#define mmLB0_LB_VLINE_STATUS 0x1ac9 +#define mmLB1_LB_VLINE_STATUS 0x1cc9 +#define mmLB2_LB_VLINE_STATUS 0x1ec9 +#define mmLB3_LB_VLINE_STATUS 0x40c9 +#define mmLB4_LB_VLINE_STATUS 0x42c9 +#define mmLB5_LB_VLINE_STATUS 0x44c9 +#define mmLB_VLINE2_STATUS 0x1aca +#define mmLB0_LB_VLINE2_STATUS 0x1aca +#define mmLB1_LB_VLINE2_STATUS 0x1cca +#define mmLB2_LB_VLINE2_STATUS 0x1eca +#define mmLB3_LB_VLINE2_STATUS 0x40ca +#define mmLB4_LB_VLINE2_STATUS 0x42ca +#define mmLB5_LB_VLINE2_STATUS 0x44ca +#define mmLB_VBLANK_STATUS 0x1acb +#define mmLB0_LB_VBLANK_STATUS 0x1acb +#define mmLB1_LB_VBLANK_STATUS 0x1ccb +#define mmLB2_LB_VBLANK_STATUS 0x1ecb +#define mmLB3_LB_VBLANK_STATUS 0x40cb +#define mmLB4_LB_VBLANK_STATUS 0x42cb +#define mmLB5_LB_VBLANK_STATUS 0x44cb +#define mmLB_SYNC_RESET_SEL 0x1acc +#define mmLB0_LB_SYNC_RESET_SEL 0x1acc +#define mmLB1_LB_SYNC_RESET_SEL 0x1ccc +#define mmLB2_LB_SYNC_RESET_SEL 0x1ecc +#define mmLB3_LB_SYNC_RESET_SEL 0x40cc +#define mmLB4_LB_SYNC_RESET_SEL 0x42cc +#define mmLB5_LB_SYNC_RESET_SEL 0x44cc +#define mmLB_BLACK_KEYER_R_CR 0x1acd +#define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd +#define mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd +#define mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd +#define mmLB3_LB_BLACK_KEYER_R_CR 0x40cd +#define mmLB4_LB_BLACK_KEYER_R_CR 0x42cd +#define mmLB5_LB_BLACK_KEYER_R_CR 0x44cd +#define mmLB_BLACK_KEYER_G_Y 0x1ace +#define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace +#define mmLB1_LB_BLACK_KEYER_G_Y 0x1cce +#define mmLB2_LB_BLACK_KEYER_G_Y 0x1ece +#define mmLB3_LB_BLACK_KEYER_G_Y 0x40ce +#define mmLB4_LB_BLACK_KEYER_G_Y 0x42ce +#define mmLB5_LB_BLACK_KEYER_G_Y 0x44ce +#define mmLB_BLACK_KEYER_B_CB 0x1acf +#define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf +#define mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf +#define mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf +#define mmLB3_LB_BLACK_KEYER_B_CB 0x40cf +#define mmLB4_LB_BLACK_KEYER_B_CB 0x42cf +#define mmLB5_LB_BLACK_KEYER_B_CB 0x44cf +#define mmLB_KEYER_COLOR_CTRL 0x1ad0 +#define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 +#define mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0 +#define mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0 +#define mmLB3_LB_KEYER_COLOR_CTRL 0x40d0 +#define mmLB4_LB_KEYER_COLOR_CTRL 0x42d0 +#define mmLB5_LB_KEYER_COLOR_CTRL 0x44d0 +#define mmLB_KEYER_COLOR_R_CR 0x1ad1 +#define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 +#define mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1 +#define mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1 +#define mmLB3_LB_KEYER_COLOR_R_CR 0x40d1 +#define mmLB4_LB_KEYER_COLOR_R_CR 0x42d1 +#define mmLB5_LB_KEYER_COLOR_R_CR 0x44d1 +#define mmLB_KEYER_COLOR_G_Y 0x1ad2 +#define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 +#define mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2 +#define mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2 +#define mmLB3_LB_KEYER_COLOR_G_Y 0x40d2 +#define mmLB4_LB_KEYER_COLOR_G_Y 0x42d2 +#define mmLB5_LB_KEYER_COLOR_G_Y 0x44d2 +#define mmLB_KEYER_COLOR_B_CB 0x1ad3 +#define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 +#define mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3 +#define mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3 +#define mmLB3_LB_KEYER_COLOR_B_CB 0x40d3 +#define mmLB4_LB_KEYER_COLOR_B_CB 0x42d3 +#define mmLB5_LB_KEYER_COLOR_B_CB 0x44d3 +#define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 +#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4 +#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4 +#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4 +#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4 +#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4 +#define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 +#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5 +#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5 +#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5 +#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5 +#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5 +#define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 +#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6 +#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6 +#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6 +#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6 +#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6 +#define mmLB_BUFFER_LEVEL_STATUS 0x1ad7 +#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 +#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7 +#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7 +#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7 +#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7 +#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7 +#define mmLB_BUFFER_URGENCY_CTRL 0x1ad8 +#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 +#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8 +#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8 +#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8 +#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8 +#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8 +#define mmLB_BUFFER_URGENCY_STATUS 0x1ad9 +#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 +#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9 +#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9 +#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9 +#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9 +#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9 +#define mmLB_BUFFER_STATUS 0x1ada +#define mmLB0_LB_BUFFER_STATUS 0x1ada +#define mmLB1_LB_BUFFER_STATUS 0x1cda +#define mmLB2_LB_BUFFER_STATUS 0x1eda +#define mmLB3_LB_BUFFER_STATUS 0x40da +#define mmLB4_LB_BUFFER_STATUS 0x42da +#define mmLB5_LB_BUFFER_STATUS 0x44da +#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc +#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc +#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc +#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc +#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc +#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc +#define mmMVP_AFR_FLIP_MODE 0x1ae0 +#define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 +#define mmLB1_MVP_AFR_FLIP_MODE 0x1ce0 +#define mmLB2_MVP_AFR_FLIP_MODE 0x1ee0 +#define mmLB3_MVP_AFR_FLIP_MODE 0x40e0 +#define mmLB4_MVP_AFR_FLIP_MODE 0x42e0 +#define mmLB5_MVP_AFR_FLIP_MODE 0x44e0 +#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 +#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1 +#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1 +#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 +#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1 +#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1 +#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 +#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2 +#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2 +#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2 +#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2 +#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2 +#define mmDC_MVP_LB_CONTROL 0x1ae3 +#define mmLB0_DC_MVP_LB_CONTROL 0x1ae3 +#define mmLB1_DC_MVP_LB_CONTROL 0x1ce3 +#define mmLB2_DC_MVP_LB_CONTROL 0x1ee3 +#define mmLB3_DC_MVP_LB_CONTROL 0x40e3 +#define mmLB4_DC_MVP_LB_CONTROL 0x42e3 +#define mmLB5_DC_MVP_LB_CONTROL 0x44e3 +#define mmLB_DEBUG 0x1ae4 +#define mmLB0_LB_DEBUG 0x1ae4 +#define mmLB1_LB_DEBUG 0x1ce4 +#define mmLB2_LB_DEBUG 0x1ee4 +#define mmLB3_LB_DEBUG 0x40e4 +#define mmLB4_LB_DEBUG 0x42e4 +#define mmLB5_LB_DEBUG 0x44e4 +#define mmLB_DEBUG2 0x1ae5 +#define mmLB0_LB_DEBUG2 0x1ae5 +#define mmLB1_LB_DEBUG2 0x1ce5 +#define mmLB2_LB_DEBUG2 0x1ee5 +#define mmLB3_LB_DEBUG2 0x40e5 +#define mmLB4_LB_DEBUG2 0x42e5 +#define mmLB5_LB_DEBUG2 0x44e5 +#define mmLB_DEBUG3 0x1ae6 +#define mmLB0_LB_DEBUG3 0x1ae6 +#define mmLB1_LB_DEBUG3 0x1ce6 +#define mmLB2_LB_DEBUG3 0x1ee6 +#define mmLB3_LB_DEBUG3 0x40e6 +#define mmLB4_LB_DEBUG3 0x42e6 +#define mmLB5_LB_DEBUG3 0x44e6 +#define mmLB_TEST_DEBUG_INDEX 0x1afe +#define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe +#define mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe +#define mmLB2_LB_TEST_DEBUG_INDEX 0x1efe +#define mmLB3_LB_TEST_DEBUG_INDEX 0x40fe +#define mmLB4_LB_TEST_DEBUG_INDEX 0x42fe +#define mmLB5_LB_TEST_DEBUG_INDEX 0x44fe +#define mmLB_TEST_DEBUG_DATA 0x1aff +#define mmLB0_LB_TEST_DEBUG_DATA 0x1aff +#define mmLB1_LB_TEST_DEBUG_DATA 0x1cff +#define mmLB2_LB_TEST_DEBUG_DATA 0x1eff +#define mmLB3_LB_TEST_DEBUG_DATA 0x40ff +#define mmLB4_LB_TEST_DEBUG_DATA 0x42ff +#define mmLB5_LB_TEST_DEBUG_DATA 0x44ff +#define mmLBV_DATA_FORMAT 0x463c +#define mmLBV_MEMORY_CTRL 0x463d +#define mmLBV_MEMORY_SIZE_STATUS 0x463e +#define mmLBV_DESKTOP_HEIGHT 0x463f +#define mmLBV_VLINE_START_END 0x4640 +#define mmLBV_VLINE2_START_END 0x4641 +#define mmLBV_V_COUNTER 0x4642 +#define mmLBV_SNAPSHOT_V_COUNTER 0x4643 +#define mmLBV_V_COUNTER_CHROMA 0x4644 +#define mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 +#define mmLBV_INTERRUPT_MASK 0x4646 +#define mmLBV_VLINE_STATUS 0x4647 +#define mmLBV_VLINE2_STATUS 0x4648 +#define mmLBV_VBLANK_STATUS 0x4649 +#define mmLBV_SYNC_RESET_SEL 0x464a +#define mmLBV_BLACK_KEYER_R_CR 0x464b +#define mmLBV_BLACK_KEYER_G_Y 0x464c +#define mmLBV_BLACK_KEYER_B_CB 0x464d +#define mmLBV_KEYER_COLOR_CTRL 0x464e +#define mmLBV_KEYER_COLOR_R_CR 0x464f +#define mmLBV_KEYER_COLOR_G_Y 0x4650 +#define mmLBV_KEYER_COLOR_B_CB 0x4651 +#define mmLBV_KEYER_COLOR_REP_R_CR 0x4652 +#define mmLBV_KEYER_COLOR_REP_G_Y 0x4653 +#define mmLBV_KEYER_COLOR_REP_B_CB 0x4654 +#define mmLBV_BUFFER_LEVEL_STATUS 0x4655 +#define mmLBV_BUFFER_URGENCY_CTRL 0x4656 +#define mmLBV_BUFFER_URGENCY_STATUS 0x4657 +#define mmLBV_BUFFER_STATUS 0x4658 +#define mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659 +#define mmLBV_DEBUG 0x465a +#define mmLBV_DEBUG2 0x465b +#define mmLBV_DEBUG3 0x465c +#define mmLBV_TEST_DEBUG_INDEX 0x4666 +#define mmLBV_TEST_DEBUG_DATA 0x4667 +#define mmMVP_CONTROL1 0x2ac +#define mmMVP_CONTROL2 0x2ad +#define mmMVP_FIFO_CONTROL 0x2ae +#define mmMVP_FIFO_STATUS 0x2af +#define mmMVP_SLAVE_STATUS 0x2b0 +#define mmMVP_INBAND_CNTL_CAP 0x2b1 +#define mmMVP_BLACK_KEYER 0x2b2 +#define mmMVP_CRC_CNTL 0x2b3 +#define mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4 +#define mmMVP_CRC_RESULT_RED 0x2b5 +#define mmMVP_CONTROL3 0x2b6 +#define mmMVP_RECEIVE_CNT_CNTL1 0x2b7 +#define mmMVP_RECEIVE_CNT_CNTL2 0x2b8 +#define mmMVP_DEBUG 0x2bb +#define mmMVP_TEST_DEBUG_INDEX 0x2b9 +#define mmMVP_TEST_DEBUG_DATA 0x2ba +#define ixMVP_DEBUG_12 0xc +#define ixMVP_DEBUG_13 0xd +#define ixMVP_DEBUG_14 0xe +#define ixMVP_DEBUG_15 0xf +#define ixMVP_DEBUG_16 0x10 +#define ixMVP_DEBUG_17 0x11 +#define mmSCL_COEF_RAM_SELECT 0x1b40 +#define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 +#define mmSCL1_SCL_COEF_RAM_SELECT 0x1d40 +#define mmSCL2_SCL_COEF_RAM_SELECT 0x1f40 +#define mmSCL3_SCL_COEF_RAM_SELECT 0x4140 +#define mmSCL4_SCL_COEF_RAM_SELECT 0x4340 +#define mmSCL5_SCL_COEF_RAM_SELECT 0x4540 +#define mmSCL_COEF_RAM_TAP_DATA 0x1b41 +#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 +#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41 +#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41 +#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141 +#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341 +#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 +#define mmSCL_MODE 0x1b42 +#define mmSCL0_SCL_MODE 0x1b42 +#define mmSCL1_SCL_MODE 0x1d42 +#define mmSCL2_SCL_MODE 0x1f42 +#define mmSCL3_SCL_MODE 0x4142 +#define mmSCL4_SCL_MODE 0x4342 +#define mmSCL5_SCL_MODE 0x4542 +#define mmSCL_TAP_CONTROL 0x1b43 +#define mmSCL0_SCL_TAP_CONTROL 0x1b43 +#define mmSCL1_SCL_TAP_CONTROL 0x1d43 +#define mmSCL2_SCL_TAP_CONTROL 0x1f43 +#define mmSCL3_SCL_TAP_CONTROL 0x4143 +#define mmSCL4_SCL_TAP_CONTROL 0x4343 +#define mmSCL5_SCL_TAP_CONTROL 0x4543 +#define mmSCL_CONTROL 0x1b44 +#define mmSCL0_SCL_CONTROL 0x1b44 +#define mmSCL1_SCL_CONTROL 0x1d44 +#define mmSCL2_SCL_CONTROL 0x1f44 +#define mmSCL3_SCL_CONTROL 0x4144 +#define mmSCL4_SCL_CONTROL 0x4344 +#define mmSCL5_SCL_CONTROL 0x4544 +#define mmSCL_BYPASS_CONTROL 0x1b45 +#define mmSCL0_SCL_BYPASS_CONTROL 0x1b45 +#define mmSCL1_SCL_BYPASS_CONTROL 0x1d45 +#define mmSCL2_SCL_BYPASS_CONTROL 0x1f45 +#define mmSCL3_SCL_BYPASS_CONTROL 0x4145 +#define mmSCL4_SCL_BYPASS_CONTROL 0x4345 +#define mmSCL5_SCL_BYPASS_CONTROL 0x4545 +#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 +#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46 +#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46 +#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146 +#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346 +#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546 +#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 +#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47 +#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47 +#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147 +#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347 +#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547 +#define mmSCL_HORZ_FILTER_CONTROL 0x1b48 +#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 +#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48 +#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48 +#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148 +#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348 +#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548 +#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 +#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49 +#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49 +#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 +#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349 +#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549 +#define mmSCL_HORZ_FILTER_INIT 0x1b4a +#define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a +#define mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a +#define mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a +#define mmSCL3_SCL_HORZ_FILTER_INIT 0x414a +#define mmSCL4_SCL_HORZ_FILTER_INIT 0x434a +#define mmSCL5_SCL_HORZ_FILTER_INIT 0x454a +#define mmSCL_VERT_FILTER_CONTROL 0x1b4b +#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b +#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b +#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b +#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b +#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b +#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b +#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c +#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c +#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c +#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c +#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c +#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c +#define mmSCL_VERT_FILTER_INIT 0x1b4d +#define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d +#define mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d +#define mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d +#define mmSCL3_SCL_VERT_FILTER_INIT 0x414d +#define mmSCL4_SCL_VERT_FILTER_INIT 0x434d +#define mmSCL5_SCL_VERT_FILTER_INIT 0x454d +#define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e +#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e +#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e +#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e +#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e +#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e +#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e +#define mmSCL_ROUND_OFFSET 0x1b4f +#define mmSCL0_SCL_ROUND_OFFSET 0x1b4f +#define mmSCL1_SCL_ROUND_OFFSET 0x1d4f +#define mmSCL2_SCL_ROUND_OFFSET 0x1f4f +#define mmSCL3_SCL_ROUND_OFFSET 0x414f +#define mmSCL4_SCL_ROUND_OFFSET 0x434f +#define mmSCL5_SCL_ROUND_OFFSET 0x454f +#define mmSCL_UPDATE 0x1b51 +#define mmSCL0_SCL_UPDATE 0x1b51 +#define mmSCL1_SCL_UPDATE 0x1d51 +#define mmSCL2_SCL_UPDATE 0x1f51 +#define mmSCL3_SCL_UPDATE 0x4151 +#define mmSCL4_SCL_UPDATE 0x4351 +#define mmSCL5_SCL_UPDATE 0x4551 +#define mmSCL_F_SHARP_CONTROL 0x1b53 +#define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 +#define mmSCL1_SCL_F_SHARP_CONTROL 0x1d53 +#define mmSCL2_SCL_F_SHARP_CONTROL 0x1f53 +#define mmSCL3_SCL_F_SHARP_CONTROL 0x4153 +#define mmSCL4_SCL_F_SHARP_CONTROL 0x4353 +#define mmSCL5_SCL_F_SHARP_CONTROL 0x4553 +#define mmSCL_ALU_CONTROL 0x1b54 +#define mmSCL0_SCL_ALU_CONTROL 0x1b54 +#define mmSCL1_SCL_ALU_CONTROL 0x1d54 +#define mmSCL2_SCL_ALU_CONTROL 0x1f54 +#define mmSCL3_SCL_ALU_CONTROL 0x4154 +#define mmSCL4_SCL_ALU_CONTROL 0x4354 +#define mmSCL5_SCL_ALU_CONTROL 0x4554 +#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 +#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55 +#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55 +#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 +#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355 +#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555 +#define mmVIEWPORT_START_SECONDARY 0x1b5b +#define mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b +#define mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b +#define mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b +#define mmSCL3_VIEWPORT_START_SECONDARY 0x415b +#define mmSCL4_VIEWPORT_START_SECONDARY 0x435b +#define mmSCL5_VIEWPORT_START_SECONDARY 0x455b +#define mmVIEWPORT_START 0x1b5c +#define mmSCL0_VIEWPORT_START 0x1b5c +#define mmSCL1_VIEWPORT_START 0x1d5c +#define mmSCL2_VIEWPORT_START 0x1f5c +#define mmSCL3_VIEWPORT_START 0x415c +#define mmSCL4_VIEWPORT_START 0x435c +#define mmSCL5_VIEWPORT_START 0x455c +#define mmVIEWPORT_SIZE 0x1b5d +#define mmSCL0_VIEWPORT_SIZE 0x1b5d +#define mmSCL1_VIEWPORT_SIZE 0x1d5d +#define mmSCL2_VIEWPORT_SIZE 0x1f5d +#define mmSCL3_VIEWPORT_SIZE 0x415d +#define mmSCL4_VIEWPORT_SIZE 0x435d +#define mmSCL5_VIEWPORT_SIZE 0x455d +#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e +#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e +#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e +#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e +#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e +#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e +#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f +#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f +#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f +#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f +#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f +#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f +#define mmSCL_MODE_CHANGE_DET1 0x1b60 +#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 +#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60 +#define mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60 +#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4160 +#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4360 +#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4560 +#define mmSCL_MODE_CHANGE_DET2 0x1b61 +#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 +#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61 +#define mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61 +#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4161 +#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4361 +#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4561 +#define mmSCL_MODE_CHANGE_DET3 0x1b62 +#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 +#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62 +#define mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62 +#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4162 +#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4362 +#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4562 +#define mmSCL_MODE_CHANGE_MASK 0x1b63 +#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 +#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63 +#define mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63 +#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4163 +#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4363 +#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4563 +#define mmSCL_DEBUG2 0x1b69 +#define mmSCL0_SCL_DEBUG2 0x1b69 +#define mmSCL1_SCL_DEBUG2 0x1d69 +#define mmSCL2_SCL_DEBUG2 0x1f69 +#define mmSCL3_SCL_DEBUG2 0x4169 +#define mmSCL4_SCL_DEBUG2 0x4369 +#define mmSCL5_SCL_DEBUG2 0x4569 +#define mmSCL_DEBUG 0x1b6a +#define mmSCL0_SCL_DEBUG 0x1b6a +#define mmSCL1_SCL_DEBUG 0x1d6a +#define mmSCL2_SCL_DEBUG 0x1f6a +#define mmSCL3_SCL_DEBUG 0x416a +#define mmSCL4_SCL_DEBUG 0x436a +#define mmSCL5_SCL_DEBUG 0x456a +#define mmSCL_TEST_DEBUG_INDEX 0x1b6b +#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b +#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b +#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b +#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b +#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b +#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b +#define mmSCL_TEST_DEBUG_DATA 0x1b6c +#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c +#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c +#define mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c +#define mmSCL3_SCL_TEST_DEBUG_DATA 0x416c +#define mmSCL4_SCL_TEST_DEBUG_DATA 0x436c +#define mmSCL5_SCL_TEST_DEBUG_DATA 0x456c +#define mmSCLV_COEF_RAM_SELECT 0x4670 +#define mmSCLV_COEF_RAM_TAP_DATA 0x4671 +#define mmSCLV_MODE 0x4672 +#define mmSCLV_TAP_CONTROL 0x4673 +#define mmSCLV_CONTROL 0x4674 +#define mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675 +#define mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676 +#define mmSCLV_HORZ_FILTER_CONTROL 0x4677 +#define mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678 +#define mmSCLV_HORZ_FILTER_INIT 0x4679 +#define mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a +#define mmSCLV_HORZ_FILTER_INIT_C 0x467b +#define mmSCLV_VERT_FILTER_CONTROL 0x467c +#define mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d +#define mmSCLV_VERT_FILTER_INIT 0x467e +#define mmSCLV_VERT_FILTER_INIT_BOT 0x467f +#define mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 +#define mmSCLV_VERT_FILTER_INIT_C 0x4681 +#define mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682 +#define mmSCLV_ROUND_OFFSET 0x4683 +#define mmSCLV_UPDATE 0x4684 +#define mmSCLV_ALU_CONTROL 0x4685 +#define mmSCLV_VIEWPORT_START 0x4686 +#define mmSCLV_VIEWPORT_START_SECONDARY 0x4687 +#define mmSCLV_VIEWPORT_SIZE 0x4688 +#define mmSCLV_VIEWPORT_START_C 0x4689 +#define mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a +#define mmSCLV_VIEWPORT_SIZE_C 0x468b +#define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c +#define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d +#define mmSCLV_MODE_CHANGE_DET1 0x468e +#define mmSCLV_MODE_CHANGE_DET2 0x468f +#define mmSCLV_MODE_CHANGE_DET3 0x4690 +#define mmSCLV_MODE_CHANGE_MASK 0x4691 +#define mmSCLV_HORZ_FILTER_INIT_BOT 0x4692 +#define mmSCLV_HORZ_FILTER_INIT_BOT_C 0x4693 +#define mmSCLV_DEBUG2 0x4694 +#define mmSCLV_DEBUG 0x4695 +#define mmSCLV_TEST_DEBUG_INDEX 0x4696 +#define mmSCLV_TEST_DEBUG_DATA 0x4697 +#define mmCOL_MAN_UPDATE 0x46a4 +#define mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5 +#define mmINPUT_CSC_C11_C12_A 0x46a6 +#define mmINPUT_CSC_C13_C14_A 0x46a7 +#define mmINPUT_CSC_C21_C22_A 0x46a8 +#define mmINPUT_CSC_C23_C24_A 0x46a9 +#define mmINPUT_CSC_C31_C32_A 0x46aa +#define mmINPUT_CSC_C33_C34_A 0x46ab +#define mmINPUT_CSC_C11_C12_B 0x46ac +#define mmINPUT_CSC_C13_C14_B 0x46ad +#define mmINPUT_CSC_C21_C22_B 0x46ae +#define mmINPUT_CSC_C23_C24_B 0x46af +#define mmINPUT_CSC_C31_C32_B 0x46b0 +#define mmINPUT_CSC_C33_C34_B 0x46b1 +#define mmPRESCALE_CONTROL 0x46b2 +#define mmPRESCALE_VALUES_R 0x46b3 +#define mmPRESCALE_VALUES_G 0x46b4 +#define mmPRESCALE_VALUES_B 0x46b5 +#define mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6 +#define mmOUTPUT_CSC_C11_C12_A 0x46b7 +#define mmOUTPUT_CSC_C13_C14_A 0x46b8 +#define mmOUTPUT_CSC_C21_C22_A 0x46b9 +#define mmOUTPUT_CSC_C23_C24_A 0x46ba +#define mmOUTPUT_CSC_C31_C32_A 0x46bb +#define mmOUTPUT_CSC_C33_C34_A 0x46bc +#define mmOUTPUT_CSC_C11_C12_B 0x46bd +#define mmOUTPUT_CSC_C13_C14_B 0x46be +#define mmOUTPUT_CSC_C21_C22_B 0x46bf +#define mmOUTPUT_CSC_C23_C24_B 0x46c0 +#define mmOUTPUT_CSC_C31_C32_B 0x46c1 +#define mmOUTPUT_CSC_C33_C34_B 0x46c2 +#define mmDENORM_CLAMP_CONTROL 0x46c3 +#define mmDENORM_CLAMP_RANGE_R_CR 0x46c4 +#define mmDENORM_CLAMP_RANGE_G_Y 0x46c5 +#define mmDENORM_CLAMP_RANGE_B_CB 0x46c6 +#define mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7 +#define mmGAMMA_CORR_CONTROL 0x46c8 +#define mmGAMMA_CORR_LUT_INDEX 0x46c9 +#define mmGAMMA_CORR_LUT_DATA 0x46ca +#define mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb +#define mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc +#define mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd +#define mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce +#define mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf +#define mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0 +#define mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1 +#define mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2 +#define mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3 +#define mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4 +#define mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5 +#define mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6 +#define mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7 +#define mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8 +#define mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 +#define mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da +#define mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db +#define mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc +#define mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd +#define mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de +#define mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df +#define mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0 +#define mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1 +#define mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2 +#define mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3 +#define mmPACK_FIFO_ERROR 0x46e4 +#define mmOUTPUT_FIFO_ERROR 0x46e5 +#define mmINPUT_GAMMA_LUT_AUTOFILL 0x46e6 +#define mmINPUT_GAMMA_LUT_RW_INDEX 0x46e7 +#define mmINPUT_GAMMA_LUT_SEQ_COLOR 0x46e8 +#define mmINPUT_GAMMA_LUT_PWL_DATA 0x46e9 +#define mmINPUT_GAMMA_LUT_30_COLOR 0x46ea +#define mmCOL_MAN_INPUT_GAMMA_CONTROL1 0x46eb +#define mmCOL_MAN_INPUT_GAMMA_CONTROL2 0x46ec +#define mmINPUT_GAMMA_BW_OFFSETS_B 0x46ed +#define mmINPUT_GAMMA_BW_OFFSETS_G 0x46ee +#define mmINPUT_GAMMA_BW_OFFSETS_R 0x46ef +#define mmCOL_MAN_DEBUG_CONTROL 0x46f0 +#define mmCOL_MAN_TEST_DEBUG_INDEX 0x46f1 +#define mmCOL_MAN_TEST_DEBUG_DATA 0x46f3 +#define mmUNP_GRPH_ENABLE 0x4600 +#define mmUNP_GRPH_CONTROL 0x4601 +#define mmUNP_GRPH_CONTROL_C 0x4602 +#define mmUNP_GRPH_CONTROL_EXP 0x4603 +#define mmUNP_GRPH_SWAP_CNTL 0x4605 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 +#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c +#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 +#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 +#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 +#define mmUNP_GRPH_PITCH_L 0x4616 +#define mmUNP_GRPH_PITCH_C 0x4617 +#define mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618 +#define mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619 +#define mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a +#define mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b +#define mmUNP_GRPH_X_START_L 0x461c +#define mmUNP_GRPH_X_START_C 0x461d +#define mmUNP_GRPH_Y_START_L 0x461e +#define mmUNP_GRPH_Y_START_C 0x461f +#define mmUNP_GRPH_X_END_L 0x4620 +#define mmUNP_GRPH_X_END_C 0x4621 +#define mmUNP_GRPH_Y_END_L 0x4622 +#define mmUNP_GRPH_Y_END_C 0x4623 +#define mmUNP_GRPH_UPDATE 0x4624 +#define mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x463a +#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 +#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 +#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 +#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 +#define mmUNP_DVMM_PTE_CONTROL 0x4629 +#define mmUNP_DVMM_PTE_CONTROL_C 0x4604 +#define mmUNP_DVMM_PTE_ARB_CONTROL 0x462a +#define mmUNP_DVMM_PTE_ARB_CONTROL_C 0x462d +#define mmUNP_GRPH_INTERRUPT_STATUS 0x462b +#define mmUNP_GRPH_INTERRUPT_CONTROL 0x462c +#define mmUNP_GRPH_STEREOSYNC_FLIP 0x462e +#define mmUNP_FLIP_CONTROL 0x462f +#define mmUNP_CRC_CONTROL 0x4630 +#define mmUNP_CRC_MASK 0x4631 +#define mmUNP_CRC_CURRENT 0x4632 +#define mmUNP_CRC_LAST 0x4633 +#define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 +#define mmUNP_HW_ROTATION 0x4635 +#define mmUNP_DEBUG 0x4636 +#define mmUNP_DEBUG2 0x4637 +#define mmUNP_DVMM_DEBUG 0x463b +#define mmUNP_TEST_DEBUG_INDEX 0x4638 +#define mmUNP_TEST_DEBUG_DATA 0x4639 +#define mmGENMO_WT 0xf0 +#define mmGENMO_RD 0xf3 +#define mmGENENB 0xf0 +#define mmGENFC_WT 0xee +#define mmVGA0_GENFC_WT 0xee +#define mmVGA1_GENFC_WT 0xf6 +#define mmGENFC_RD 0xf2 +#define mmGENS0 0xf0 +#define mmGENS1 0xee +#define mmVGA0_GENS1 0xee +#define mmVGA1_GENS1 0xf6 +#define mmDAC_DATA 0xf2 +#define mmDAC_MASK 0xf1 +#define mmDAC_R_INDEX 0xf1 +#define mmDAC_W_INDEX 0xf2 +#define mmSEQ8_IDX 0xf1 +#define mmSEQ8_DATA 0xf1 +#define ixSEQ00 0x0 +#define ixSEQ01 0x1 +#define ixSEQ02 0x2 +#define ixSEQ03 0x3 +#define ixSEQ04 0x4 +#define mmCRTC8_IDX 0xed +#define mmVGA0_CRTC8_IDX 0xed +#define mmVGA1_CRTC8_IDX 0xf5 +#define mmCRTC8_DATA 0xed +#define mmVGA0_CRTC8_DATA 0xed +#define mmVGA1_CRTC8_DATA 0xf5 +#define ixCRT00 0x0 +#define ixCRT01 0x1 +#define ixCRT02 0x2 +#define ixCRT03 0x3 +#define ixCRT04 0x4 +#define ixCRT05 0x5 +#define ixCRT06 0x6 +#define ixCRT07 0x7 +#define ixCRT08 0x8 +#define ixCRT09 0x9 +#define ixCRT0A 0xa +#define ixCRT0B 0xb +#define ixCRT0C 0xc +#define ixCRT0D 0xd +#define ixCRT0E 0xe +#define ixCRT0F 0xf +#define ixCRT10 0x10 +#define ixCRT11 0x11 +#define ixCRT12 0x12 +#define ixCRT13 0x13 +#define ixCRT14 0x14 +#define ixCRT15 0x15 +#define ixCRT16 0x16 +#define ixCRT17 0x17 +#define ixCRT18 0x18 +#define ixCRT1E 0x1e +#define ixCRT1F 0x1f +#define ixCRT22 0x22 +#define mmGRPH8_IDX 0xf3 +#define mmGRPH8_DATA 0xf3 +#define ixGRA00 0x0 +#define ixGRA01 0x1 +#define ixGRA02 0x2 +#define ixGRA03 0x3 +#define ixGRA04 0x4 +#define ixGRA05 0x5 +#define ixGRA06 0x6 +#define ixGRA07 0x7 +#define ixGRA08 0x8 +#define mmATTRX 0xf0 +#define mmATTRDW 0xf0 +#define mmATTRDR 0xf0 +#define ixATTR00 0x0 +#define ixATTR01 0x1 +#define ixATTR02 0x2 +#define ixATTR03 0x3 +#define ixATTR04 0x4 +#define ixATTR05 0x5 +#define ixATTR06 0x6 +#define ixATTR07 0x7 +#define ixATTR08 0x8 +#define ixATTR09 0x9 +#define ixATTR0A 0xa +#define ixATTR0B 0xb +#define ixATTR0C 0xc +#define ixATTR0D 0xd +#define ixATTR0E 0xe +#define ixATTR0F 0xf +#define ixATTR10 0x10 +#define ixATTR11 0x11 +#define ixATTR12 0x12 +#define ixATTR13 0x13 +#define ixATTR14 0x14 +#define mmVGA_RENDER_CONTROL 0xc0 +#define mmVGA_SOURCE_SELECT 0xfc +#define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 +#define mmVGA_MODE_CONTROL 0xc2 +#define mmVGA_SURFACE_PITCH_SELECT 0xc3 +#define mmVGA_MEMORY_BASE_ADDRESS 0xc4 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 +#define mmVGA_HDP_CONTROL 0xca +#define mmVGA_CACHE_CONTROL 0xcb +#define mmD1VGA_CONTROL 0xcc +#define mmD2VGA_CONTROL 0xce +#define mmD3VGA_CONTROL 0xf8 +#define mmD4VGA_CONTROL 0xf9 +#define mmD5VGA_CONTROL 0xfa +#define mmD6VGA_CONTROL 0xfb +#define mmVGA_HW_DEBUG 0xcf +#define mmVGA_STATUS 0xd0 +#define mmVGA_INTERRUPT_CONTROL 0xd1 +#define mmVGA_STATUS_CLEAR 0xd2 +#define mmVGA_INTERRUPT_STATUS 0xd3 +#define mmVGA_MAIN_CONTROL 0xd4 +#define mmVGA_TEST_CONTROL 0xd5 +#define mmVGA_DEBUG_READBACK_INDEX 0xd6 +#define mmVGA_DEBUG_READBACK_DATA 0xd7 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x12 +#define mmVGA_MEM_READ_PAGE_ADDR 0x13 +#define mmVGA_TEST_DEBUG_INDEX 0xc5 +#define mmVGA_TEST_DEBUG_DATA 0xc7 +#define ixVGADCC_DBG_DCCIF_C 0x7e +#define mmBPHYC_DAC_MACRO_CNTL 0x48b9 +#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba +#define mmPLL_REF_DIV 0x1700 +#define mmBPHYC_PLL0_PLL_REF_DIV 0x1700 +#define mmBPHYC_PLL1_PLL_REF_DIV 0x172a +#define mmBPHYC_PLL2_PLL_REF_DIV 0x1754 +#define mmPLL_FB_DIV 0x1701 +#define mmBPHYC_PLL0_PLL_FB_DIV 0x1701 +#define mmBPHYC_PLL1_PLL_FB_DIV 0x172b +#define mmBPHYC_PLL2_PLL_FB_DIV 0x1755 +#define mmPLL_POST_DIV 0x1702 +#define mmBPHYC_PLL0_PLL_POST_DIV 0x1702 +#define mmBPHYC_PLL1_PLL_POST_DIV 0x172c +#define mmBPHYC_PLL2_PLL_POST_DIV 0x1756 +#define mmPLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 +#define mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d +#define mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757 +#define mmPLL_SS_CNTL 0x1704 +#define mmBPHYC_PLL0_PLL_SS_CNTL 0x1704 +#define mmBPHYC_PLL1_PLL_SS_CNTL 0x172e +#define mmBPHYC_PLL2_PLL_SS_CNTL 0x1758 +#define mmPLL_DS_CNTL 0x1705 +#define mmBPHYC_PLL0_PLL_DS_CNTL 0x1705 +#define mmBPHYC_PLL1_PLL_DS_CNTL 0x172f +#define mmBPHYC_PLL2_PLL_DS_CNTL 0x1759 +#define mmPLL_IDCLK_CNTL 0x1706 +#define mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706 +#define mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730 +#define mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a +#define mmPLL_CNTL 0x1707 +#define mmBPHYC_PLL0_PLL_CNTL 0x1707 +#define mmBPHYC_PLL1_PLL_CNTL 0x1731 +#define mmBPHYC_PLL2_PLL_CNTL 0x175b +#define mmPLL_ANALOG 0x1708 +#define mmBPHYC_PLL0_PLL_ANALOG 0x1708 +#define mmBPHYC_PLL1_PLL_ANALOG 0x1732 +#define mmBPHYC_PLL2_PLL_ANALOG 0x175c +#define mmPLL_VREG_CNTL 0x1709 +#define mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709 +#define mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733 +#define mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d +#define mmPLL_UNLOCK_DETECT_CNTL 0x170a +#define mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a +#define mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734 +#define mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e +#define mmPLL_DEBUG_CNTL 0x170b +#define mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b +#define mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735 +#define mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f +#define mmPLL_UPDATE_LOCK 0x170c +#define mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c +#define mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736 +#define mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760 +#define mmPLL_UPDATE_CNTL 0x170d +#define mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d +#define mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737 +#define mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761 +#define mmPLL_XOR_LOCK 0x1710 +#define mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710 +#define mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a +#define mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764 +#define mmPLL_ANALOG_CNTL 0x1711 +#define mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711 +#define mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b +#define mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765 +#define mmVGA25_PPLL_REF_DIV 0x1712 +#define mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712 +#define mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c +#define mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766 +#define mmVGA28_PPLL_REF_DIV 0x1713 +#define mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713 +#define mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d +#define mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767 +#define mmVGA41_PPLL_REF_DIV 0x1714 +#define mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714 +#define mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e +#define mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768 +#define mmVGA25_PPLL_FB_DIV 0x1715 +#define mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715 +#define mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f +#define mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769 +#define mmVGA28_PPLL_FB_DIV 0x1716 +#define mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716 +#define mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740 +#define mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a +#define mmVGA41_PPLL_FB_DIV 0x1717 +#define mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717 +#define mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741 +#define mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b +#define mmVGA25_PPLL_POST_DIV 0x1718 +#define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718 +#define mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742 +#define mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c +#define mmVGA28_PPLL_POST_DIV 0x1719 +#define mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719 +#define mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743 +#define mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d +#define mmVGA41_PPLL_POST_DIV 0x171a +#define mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a +#define mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744 +#define mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e +#define mmVGA25_PPLL_ANALOG 0x171b +#define mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b +#define mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745 +#define mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f +#define mmVGA28_PPLL_ANALOG 0x171c +#define mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c +#define mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746 +#define mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770 +#define mmVGA41_PPLL_ANALOG 0x171d +#define mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d +#define mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747 +#define mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771 +#define mmDISPPLL_BG_CNTL 0x171e +#define mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e +#define mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748 +#define mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772 +#define mmPPLL_DIV_UPDATE_DEBUG 0x171f +#define mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f +#define mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749 +#define mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773 +#define mmPPLL_STATUS_DEBUG 0x1720 +#define mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720 +#define mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a +#define mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774 +#define mmPPLL_DEBUG_MUX_CNTL 0x1721 +#define mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721 +#define mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b +#define mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775 +#define mmPPLL_SPARE0 0x1722 +#define mmBPHYC_PLL0_PPLL_SPARE0 0x1722 +#define mmBPHYC_PLL1_PPLL_SPARE0 0x174c +#define mmBPHYC_PLL2_PPLL_SPARE0 0x1776 +#define mmPPLL_SPARE1 0x1723 +#define mmBPHYC_PLL0_PPLL_SPARE1 0x1723 +#define mmBPHYC_PLL1_PPLL_SPARE1 0x174d +#define mmBPHYC_PLL2_PPLL_SPARE1 0x1777 +#define mmUNIPHY_TX_CONTROL1 0x48c0 +#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0 +#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0 +#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900 +#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920 +#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940 +#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960 +#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980 +#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL1 0x49c0 +#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL1 0x49e0 +#define mmUNIPHY_TX_CONTROL2 0x48c1 +#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1 +#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1 +#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901 +#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921 +#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941 +#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961 +#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981 +#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL2 0x49c1 +#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL2 0x49e1 +#define mmUNIPHY_TX_CONTROL3 0x48c2 +#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2 +#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2 +#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902 +#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922 +#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942 +#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962 +#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982 +#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL3 0x49c2 +#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL3 0x49e2 +#define mmUNIPHY_TX_CONTROL4 0x48c3 +#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3 +#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3 +#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903 +#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923 +#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943 +#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963 +#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983 +#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL4 0x49c3 +#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL4 0x49e3 +#define mmUNIPHY_POWER_CONTROL 0x48c4 +#define mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4 +#define mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4 +#define mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904 +#define mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924 +#define mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944 +#define mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964 +#define mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984 +#define mmBPHYC_UNIPHY7_UNIPHY_POWER_CONTROL 0x49c4 +#define mmBPHYC_UNIPHY8_UNIPHY_POWER_CONTROL 0x49e4 +#define mmUNIPHY_PLL_FBDIV 0x48c5 +#define mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5 +#define mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5 +#define mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905 +#define mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925 +#define mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945 +#define mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965 +#define mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985 +#define mmBPHYC_UNIPHY7_UNIPHY_PLL_FBDIV 0x49c5 +#define mmBPHYC_UNIPHY8_UNIPHY_PLL_FBDIV 0x49e5 +#define mmUNIPHY_PLL_CONTROL1 0x48c6 +#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6 +#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6 +#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906 +#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926 +#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946 +#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966 +#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986 +#define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL1 0x49c6 +#define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL1 0x49e6 +#define mmUNIPHY_PLL_CONTROL2 0x48c7 +#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7 +#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7 +#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907 +#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927 +#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947 +#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967 +#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987 +#define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL2 0x49c7 +#define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL2 0x49e7 +#define mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8 +#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8 +#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8 +#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908 +#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928 +#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948 +#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968 +#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988 +#define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_STEP_SIZE 0x49c8 +#define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_STEP_SIZE 0x49e8 +#define mmUNIPHY_PLL_SS_CNTL 0x48c9 +#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9 +#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9 +#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909 +#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929 +#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949 +#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969 +#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989 +#define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_CNTL 0x49c9 +#define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_CNTL 0x49e9 +#define mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca +#define mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca +#define mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea +#define mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a +#define mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a +#define mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a +#define mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a +#define mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a +#define mmBPHYC_UNIPHY7_UNIPHY_DATA_SYNCHRONIZATION 0x49ca +#define mmBPHYC_UNIPHY8_UNIPHY_DATA_SYNCHRONIZATION 0x49ea +#define mmUNIPHY_REG_TEST_OUTPUT 0x48cb +#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb +#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb +#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b +#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b +#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b +#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b +#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b +#define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT 0x49cb +#define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT 0x49eb +#define mmUNIPHY_ANG_BIST_CNTL 0x48cc +#define mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc +#define mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec +#define mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c +#define mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c +#define mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c +#define mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c +#define mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c +#define mmBPHYC_UNIPHY7_UNIPHY_ANG_BIST_CNTL 0x49cc +#define mmBPHYC_UNIPHY8_UNIPHY_ANG_BIST_CNTL 0x49ec +#define mmUNIPHY_REG_TEST_OUTPUT2 0x48cd +#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd +#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed +#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d +#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d +#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d +#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d +#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d +#define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT2 0x49cd +#define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT2 0x49ed +#define mmUNIPHY_TMDP_REG0 0x48ce +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e +#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG0 0x49ce +#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG0 0x49ee +#define mmUNIPHY_TMDP_REG1 0x48cf +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f +#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG1 0x49cf +#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG1 0x49ef +#define mmUNIPHY_TMDP_REG2 0x48d0 +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0 +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0 +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910 +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930 +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950 +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970 +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990 +#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG2 0x49d0 +#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG2 0x49f0 +#define mmUNIPHY_TMDP_REG3 0x48d1 +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1 +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1 +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911 +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931 +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951 +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971 +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991 +#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG3 0x49d1 +#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG3 0x49f1 +#define mmUNIPHY_TMDP_REG4 0x48d2 +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2 +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2 +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912 +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932 +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952 +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972 +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992 +#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG4 0x49d2 +#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG4 0x49f2 +#define mmUNIPHY_TMDP_REG5 0x48d3 +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3 +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3 +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913 +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933 +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953 +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973 +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993 +#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG5 0x49d3 +#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG5 0x49f3 +#define mmUNIPHY_TMDP_REG6 0x48d4 +#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4 +#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4 +#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914 +#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934 +#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954 +#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974 +#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994 +#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG6 0x49d4 +#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG6 0x49f4 +#define mmUNIPHY_TPG_CONTROL 0x48d5 +#define mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5 +#define mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5 +#define mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915 +#define mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935 +#define mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955 +#define mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975 +#define mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995 +#define mmBPHYC_UNIPHY7_UNIPHY_TPG_CONTROL 0x49d5 +#define mmBPHYC_UNIPHY8_UNIPHY_TPG_CONTROL 0x49f5 +#define mmUNIPHY_TPG_SEED 0x48d6 +#define mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6 +#define mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6 +#define mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916 +#define mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936 +#define mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956 +#define mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976 +#define mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996 +#define mmBPHYC_UNIPHY7_UNIPHY_TPG_SEED 0x49d6 +#define mmBPHYC_UNIPHY8_UNIPHY_TPG_SEED 0x49f6 +#define mmUNIPHY_DEBUG 0x48d7 +#define mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7 +#define mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7 +#define mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917 +#define mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937 +#define mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957 +#define mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977 +#define mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997 +#define mmBPHYC_UNIPHY7_UNIPHY_DEBUG 0x49d7 +#define mmBPHYC_UNIPHY8_UNIPHY_DEBUG 0x49f7 +#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530 +#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 +#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31 +#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31 +#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 +#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331 +#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531 +#define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 +#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 +#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32 +#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32 +#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132 +#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332 +#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532 +#define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 +#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 +#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33 +#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33 +#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133 +#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333 +#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533 +#define mmDPG_PIPE_DPM_CONTROL 0x1b34 +#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 +#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34 +#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34 +#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134 +#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334 +#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534 +#define mmDPG_PIPE_STUTTER_CONTROL 0x1b35 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535 +#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 +#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36 +#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36 +#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 +#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336 +#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536 +#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 +#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37 +#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37 +#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 +#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337 +#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537 +#define mmDPG_REPEATER_PROGRAM 0x1b3a +#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a +#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a +#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a +#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a +#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a +#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a +#define mmDPG_HW_DEBUG_A 0x1b3b +#define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b +#define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b +#define mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b +#define mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b +#define mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b +#define mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b +#define mmDPG_HW_DEBUG_B 0x1b3c +#define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c +#define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c +#define mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c +#define mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c +#define mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c +#define mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c +#define mmDPG_HW_DEBUG_11 0x1b3d +#define mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d +#define mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d +#define mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d +#define mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d +#define mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d +#define mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d +#define mmDPG_CHK_PRE_PROC_CNTL 0x1b3e +#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x1b3e +#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x1d3e +#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x1f3e +#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x413e +#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x433e +#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x453e +#define mmDPG_TEST_DEBUG_INDEX 0x1b38 +#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 +#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38 +#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38 +#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138 +#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338 +#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538 +#define mmDPG_TEST_DEBUG_DATA 0x1b39 +#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 +#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39 +#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39 +#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139 +#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339 +#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539 +#define mmDPGV0_PIPE_ARBITRATION_CONTROL1 0x4730 +#define mmDPGV1_PIPE_ARBITRATION_CONTROL1 0x473d +#define mmDPGV0_PIPE_ARBITRATION_CONTROL2 0x4731 +#define mmDPGV1_PIPE_ARBITRATION_CONTROL2 0x473e +#define mmDPGV0_WATERMARK_MASK_CONTROL 0x4732 +#define mmDPGV1_WATERMARK_MASK_CONTROL 0x473f +#define mmDPGV0_PIPE_URGENCY_CONTROL 0x4733 +#define mmDPGV1_PIPE_URGENCY_CONTROL 0x4740 +#define mmDPGV0_PIPE_DPM_CONTROL 0x4734 +#define mmDPGV1_PIPE_DPM_CONTROL 0x4741 +#define mmDPGV0_PIPE_STUTTER_CONTROL 0x4735 +#define mmDPGV1_PIPE_STUTTER_CONTROL 0x4742 +#define mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 +#define mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4743 +#define mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 +#define mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x4744 +#define mmDPGV0_REPEATER_PROGRAM 0x4738 +#define mmDPGV1_REPEATER_PROGRAM 0x4745 +#define mmDPGV0_HW_DEBUG_A 0x4739 +#define mmDPGV1_HW_DEBUG_A 0x4746 +#define mmDPGV0_HW_DEBUG_B 0x473a +#define mmDPGV1_HW_DEBUG_B 0x4747 +#define mmDPGV0_HW_DEBUG_11 0x473b +#define mmDPGV1_HW_DEBUG_11 0x4748 +#define mmDPGV0_CHK_PRE_PROC_CNTL 0x473c +#define mmDPGV1_CHK_PRE_PROC_CNTL 0x4749 +#define mmDPGV_TEST_DEBUG_INDEX 0x474e +#define mmDPGV_TEST_DEBUG_DATA 0x474f +#define ixDPGV0_DEBUG00_DMIFARB 0x1 +#define ixDPGV1_DEBUG00_DMIFARB 0x6a +#define ixDPGV0_DEBUG01_DMIFARB 0x2 +#define ixDPGV1_DEBUG01_DMIFARB 0x6b +#define ixDPGV0_DEBUG02_DMIFARB 0x3 +#define ixDPGV1_DEBUG02_DMIFARB 0x6c +#define ixDPGV0_DEBUG03_DMIFARB 0x4 +#define ixDPGV1_DEBUG03_DMIFARB 0x6d +#define ixDPGV0_DEBUG04_DMIFARB 0x5 +#define ixDPGV1_DEBUG04_DMIFARB 0x6e +#define ixDPGV0_DEBUG00 0x6 +#define ixDPGV1_DEBUG00 0x6f +#define ixDPGV0_DEBUG01 0x7 +#define ixDPGV1_DEBUG01 0x70 +#define ixDPGV0_DEBUG02 0x8 +#define ixDPGV1_DEBUG02 0x71 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835 +#define mmAZALIA_F0_CODEC_DEBUG 0x1836 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a +#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b +#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c +#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d +#define mmGLOBAL_CAPABILITIES 0x0 +#define mmMINOR_VERSION 0x0 +#define mmMAJOR_VERSION 0x0 +#define mmOUTPUT_PAYLOAD_CAPABILITY 0x1 +#define mmINPUT_PAYLOAD_CAPABILITY 0x1 +#define mmGLOBAL_CONTROL 0x2 +#define mmWAKE_ENABLE 0x3 +#define mmSTATE_CHANGE_STATUS 0x3 +#define mmGLOBAL_STATUS 0x4 +#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6 +#define mmINTERRUPT_CONTROL 0x8 +#define mmINTERRUPT_STATUS 0x9 +#define mmWALL_CLOCK_COUNTER 0xc +#define mmSTREAM_SYNCHRONIZATION 0xe +#define mmCORB_LOWER_BASE_ADDRESS 0x10 +#define mmCORB_UPPER_BASE_ADDRESS 0x11 +#define mmCORB_WRITE_POINTER 0x12 +#define mmCORB_READ_POINTER 0x12 +#define mmCORB_CONTROL 0x13 +#define mmCORB_STATUS 0x13 +#define mmCORB_SIZE 0x13 +#define mmRIRB_LOWER_BASE_ADDRESS 0x14 +#define mmRIRB_UPPER_BASE_ADDRESS 0x15 +#define mmRIRB_WRITE_POINTER 0x16 +#define mmRESPONSE_INTERRUPT_COUNT 0x16 +#define mmRIRB_CONTROL 0x17 +#define mmRIRB_STATUS 0x17 +#define mmRIRB_SIZE 0x17 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 +#define mmIMMEDIATE_COMMAND_STATUS 0x1a +#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c +#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d +#define mmWALL_CLOCK_COUNTER_ALIAS 0x80c +#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 +#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 +#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 +#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 +#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 +#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 +#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 +#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 +#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAUDIO_DESCRIPTOR0 0x1 +#define ixAUDIO_DESCRIPTOR1 0x2 +#define ixAUDIO_DESCRIPTOR2 0x3 +#define ixAUDIO_DESCRIPTOR3 0x4 +#define ixAUDIO_DESCRIPTOR4 0x5 +#define ixAUDIO_DESCRIPTOR5 0x6 +#define ixAUDIO_DESCRIPTOR6 0x7 +#define ixAUDIO_DESCRIPTOR7 0x8 +#define ixAUDIO_DESCRIPTOR8 0x9 +#define ixAUDIO_DESCRIPTOR9 0xa +#define ixAUDIO_DESCRIPTOR10 0xb +#define ixAUDIO_DESCRIPTOR11 0xc +#define ixAUDIO_DESCRIPTOR12 0xd +#define ixAUDIO_DESCRIPTOR13 0xe +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 +#define ixSINK_DESCRIPTION0 0x5 +#define ixSINK_DESCRIPTION1 0x6 +#define ixSINK_DESCRIPTION2 0x7 +#define ixSINK_DESCRIPTION3 0x8 +#define ixSINK_DESCRIPTION4 0x9 +#define ixSINK_DESCRIPTION5 0xa +#define ixSINK_DESCRIPTION6 0xb +#define ixSINK_DESCRIPTION7 0xc +#define ixSINK_DESCRIPTION8 0xd +#define ixSINK_DESCRIPTION9 0xe +#define ixSINK_DESCRIPTION10 0xf +#define ixSINK_DESCRIPTION11 0x10 +#define ixSINK_DESCRIPTION12 0x11 +#define ixSINK_DESCRIPTION13 0x12 +#define ixSINK_DESCRIPTION14 0x13 +#define ixSINK_DESCRIPTION15 0x14 +#define ixSINK_DESCRIPTION16 0x15 +#define ixSINK_DESCRIPTION17 0x16 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4 +#define mmAZALIA_AUDIO_DTO 0x17e5 +#define mmAZALIA_AUDIO_DTO_CONTROL 0x17e6 +#define mmAZALIA_SCLK_CONTROL 0x17e7 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8 +#define mmAZALIA_DATA_DMA_CONTROL 0x17e9 +#define mmAZALIA_BDL_DMA_CONTROL 0x17ea +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb +#define mmAZALIA_CORB_DMA_CONTROL 0x17ec +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4 +#define mmAZALIA_GLOBAL_CAPABILITIES 0x17f5 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8 +#define mmAZALIA_CONTROLLER_DEBUG 0x17f9 +#define mmAZALIA_MEM_PWR_CTRL 0x1810 +#define mmAZALIA_MEM_PWR_STATUS 0x1811 +#define mmDCI_PG_DEBUG_CONFIG 0x1812 +#define mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb +#define mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc +#define mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd +#define mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe +#define mmAZALIA_INPUT_CRC0_RESULT 0x17ff +#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0 +#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 +#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 +#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x3 +#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x4 +#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 +#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x6 +#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x7 +#define mmAZALIA_INPUT_CRC1_CONTROL0 0x1800 +#define mmAZALIA_INPUT_CRC1_CONTROL1 0x1801 +#define mmAZALIA_INPUT_CRC1_CONTROL2 0x1802 +#define mmAZALIA_INPUT_CRC1_CONTROL3 0x1803 +#define mmAZALIA_INPUT_CRC1_RESULT 0x1804 +#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 +#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x1 +#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 +#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x3 +#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x4 +#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 +#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x6 +#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x7 +#define mmAZALIA_CRC0_CONTROL0 0x1805 +#define mmAZALIA_CRC0_CONTROL1 0x1806 +#define mmAZALIA_CRC0_CONTROL2 0x1807 +#define mmAZALIA_CRC0_CONTROL3 0x1808 +#define mmAZALIA_CRC0_RESULT 0x1809 +#define ixAZALIA_CRC0_CHANNEL0 0x0 +#define ixAZALIA_CRC0_CHANNEL1 0x1 +#define ixAZALIA_CRC0_CHANNEL2 0x2 +#define ixAZALIA_CRC0_CHANNEL3 0x3 +#define ixAZALIA_CRC0_CHANNEL4 0x4 +#define ixAZALIA_CRC0_CHANNEL5 0x5 +#define ixAZALIA_CRC0_CHANNEL6 0x6 +#define ixAZALIA_CRC0_CHANNEL7 0x7 +#define mmAZALIA_CRC1_CONTROL0 0x180a +#define mmAZALIA_CRC1_CONTROL1 0x180b +#define mmAZALIA_CRC1_CONTROL2 0x180c +#define mmAZALIA_CRC1_CONTROL3 0x180d +#define mmAZALIA_CRC1_RESULT 0x180e +#define ixAZALIA_CRC1_CHANNEL0 0x0 +#define ixAZALIA_CRC1_CHANNEL1 0x1 +#define ixAZALIA_CRC1_CHANNEL2 0x2 +#define ixAZALIA_CRC1_CHANNEL3 0x3 +#define ixAZALIA_CRC1_CHANNEL4 0x4 +#define ixAZALIA_CRC1_CHANNEL5 0x5 +#define ixAZALIA_CRC1_CHANNEL6 0x6 +#define ixAZALIA_CRC1_CHANNEL7 0x7 +#define mmAZ_TEST_DEBUG_INDEX 0x181f +#define mmAZ_TEST_DEBUG_DATA 0x1820 +#define mmAZALIA_STREAM_INDEX 0x1780 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780 +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0 +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2 +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4 +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6 +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8 +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce +#define mmAZALIA_STREAM_DATA 0x1781 +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b +#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d +#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f +#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3 +#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5 +#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7 +#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb +#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd +#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf +#define ixAZALIA_FIFO_SIZE_CONTROL 0x0 +#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 +#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 +#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 +#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 +#define ixAZALIA_STREAM_DEBUG 0x5 +#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4 +#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5 +#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 +#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd +#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 +#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 +#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69 +#define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a +#define ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b +#define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c +#define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d +#define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e +#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0 +#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 +#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 +#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 +#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65 +#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18 +#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define mmBLND_CONTROL 0x1b6d +#define mmBLND0_BLND_CONTROL 0x1b6d +#define mmBLND1_BLND_CONTROL 0x1d6d +#define mmBLND2_BLND_CONTROL 0x1f6d +#define mmBLND3_BLND_CONTROL 0x416d +#define mmBLND4_BLND_CONTROL 0x436d +#define mmBLND5_BLND_CONTROL 0x456d +#define mmBLND_SM_CONTROL2 0x1b6e +#define mmBLND0_BLND_SM_CONTROL2 0x1b6e +#define mmBLND1_BLND_SM_CONTROL2 0x1d6e +#define mmBLND2_BLND_SM_CONTROL2 0x1f6e +#define mmBLND3_BLND_SM_CONTROL2 0x416e +#define mmBLND4_BLND_SM_CONTROL2 0x436e +#define mmBLND5_BLND_SM_CONTROL2 0x456e +#define mmBLND_CONTROL2 0x1b6f +#define mmBLND0_BLND_CONTROL2 0x1b6f +#define mmBLND1_BLND_CONTROL2 0x1d6f +#define mmBLND2_BLND_CONTROL2 0x1f6f +#define mmBLND3_BLND_CONTROL2 0x416f +#define mmBLND4_BLND_CONTROL2 0x436f +#define mmBLND5_BLND_CONTROL2 0x456f +#define mmBLND_UPDATE 0x1b70 +#define mmBLND0_BLND_UPDATE 0x1b70 +#define mmBLND1_BLND_UPDATE 0x1d70 +#define mmBLND2_BLND_UPDATE 0x1f70 +#define mmBLND3_BLND_UPDATE 0x4170 +#define mmBLND4_BLND_UPDATE 0x4370 +#define mmBLND5_BLND_UPDATE 0x4570 +#define mmBLND_UNDERFLOW_INTERRUPT 0x1b71 +#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 +#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71 +#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71 +#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171 +#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371 +#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571 +#define mmBLND_V_UPDATE_LOCK 0x1b73 +#define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 +#define mmBLND1_BLND_V_UPDATE_LOCK 0x1d73 +#define mmBLND2_BLND_V_UPDATE_LOCK 0x1f73 +#define mmBLND3_BLND_V_UPDATE_LOCK 0x4173 +#define mmBLND4_BLND_V_UPDATE_LOCK 0x4373 +#define mmBLND5_BLND_V_UPDATE_LOCK 0x4573 +#define mmBLND_REG_UPDATE_STATUS 0x1b77 +#define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 +#define mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77 +#define mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77 +#define mmBLND3_BLND_REG_UPDATE_STATUS 0x4177 +#define mmBLND4_BLND_REG_UPDATE_STATUS 0x4377 +#define mmBLND5_BLND_REG_UPDATE_STATUS 0x4577 +#define mmBLND_DEBUG 0x1b74 +#define mmBLND0_BLND_DEBUG 0x1b74 +#define mmBLND1_BLND_DEBUG 0x1d74 +#define mmBLND2_BLND_DEBUG 0x1f74 +#define mmBLND3_BLND_DEBUG 0x4174 +#define mmBLND4_BLND_DEBUG 0x4374 +#define mmBLND5_BLND_DEBUG 0x4574 +#define mmBLND_TEST_DEBUG_INDEX 0x1b75 +#define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 +#define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75 +#define mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75 +#define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175 +#define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375 +#define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575 +#define mmBLND_TEST_DEBUG_DATA 0x1b76 +#define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 +#define mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76 +#define mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76 +#define mmBLND3_BLND_TEST_DEBUG_DATA 0x4176 +#define mmBLND4_BLND_TEST_DEBUG_DATA 0x4376 +#define mmBLND5_BLND_TEST_DEBUG_DATA 0x4576 +#define mmWB_ENABLE 0x5e18 +#define mmWB_EC_CONFIG 0x5e19 +#define mmCNV_MODE 0x5e1a +#define mmCNV_WINDOW_START 0x5e1b +#define mmCNV_WINDOW_SIZE 0x5e1c +#define mmCNV_UPDATE 0x5e1d +#define mmCNV_SOURCE_SIZE 0x5e1e +#define mmCNV_CSC_CONTROL 0x5e1f +#define mmCNV_CSC_C11_C12 0x5e20 +#define mmCNV_CSC_C13_C14 0x5e21 +#define mmCNV_CSC_C21_C22 0x5e22 +#define mmCNV_CSC_C23_C24 0x5e23 +#define mmCNV_CSC_C31_C32 0x5e24 +#define mmCNV_CSC_C33_C34 0x5e25 +#define mmCNV_CSC_ROUND_OFFSET_R 0x5e26 +#define mmCNV_CSC_ROUND_OFFSET_G 0x5e27 +#define mmCNV_CSC_ROUND_OFFSET_B 0x5e28 +#define mmCNV_CSC_CLAMP_R 0x5e29 +#define mmCNV_CSC_CLAMP_G 0x5e2a +#define mmCNV_CSC_CLAMP_B 0x5e2b +#define mmCNV_TEST_CNTL 0x5e2c +#define mmCNV_TEST_CRC_RED 0x5e2d +#define mmCNV_TEST_CRC_GREEN 0x5e2e +#define mmCNV_TEST_CRC_BLUE 0x5e2f +#define mmWB_DEBUG_CTRL 0x5e30 +#define mmWB_DBG_MODE 0x5e31 +#define mmWB_HW_DEBUG 0x5e32 +#define mmCNV_INPUT_SELECT 0x5e33 +#define mmWB_SOFT_RESET 0x5e36 +#define mmCNV_TEST_DEBUG_INDEX 0x5e34 +#define mmCNV_TEST_DEBUG_DATA 0x5e35 +#define mmDCFE_CLOCK_CONTROL 0x1b00 +#define mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00 +#define mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00 +#define mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00 +#define mmDCFE3_DCFE_CLOCK_CONTROL 0x4100 +#define mmDCFE4_DCFE_CLOCK_CONTROL 0x4300 +#define mmDCFE5_DCFE_CLOCK_CONTROL 0x4500 +#define mmDCFE_SOFT_RESET 0x1b01 +#define mmDCFE0_DCFE_SOFT_RESET 0x1b01 +#define mmDCFE1_DCFE_SOFT_RESET 0x1d01 +#define mmDCFE2_DCFE_SOFT_RESET 0x1f01 +#define mmDCFE3_DCFE_SOFT_RESET 0x4101 +#define mmDCFE4_DCFE_SOFT_RESET 0x4301 +#define mmDCFE5_DCFE_SOFT_RESET 0x4501 +#define mmDCFE_DBG_CONFIG 0x1b02 +#define mmDCFE0_DCFE_DBG_CONFIG 0x1b02 +#define mmDCFE1_DCFE_DBG_CONFIG 0x1d02 +#define mmDCFE2_DCFE_DBG_CONFIG 0x1f02 +#define mmDCFE3_DCFE_DBG_CONFIG 0x4102 +#define mmDCFE4_DCFE_DBG_CONFIG 0x4302 +#define mmDCFE5_DCFE_DBG_CONFIG 0x4502 +#define mmDCFE_MEM_PWR_CTRL 0x1b03 +#define mmDCFE0_DCFE_MEM_PWR_CTRL 0x1b03 +#define mmDCFE1_DCFE_MEM_PWR_CTRL 0x1d03 +#define mmDCFE2_DCFE_MEM_PWR_CTRL 0x1f03 +#define mmDCFE3_DCFE_MEM_PWR_CTRL 0x4103 +#define mmDCFE4_DCFE_MEM_PWR_CTRL 0x4303 +#define mmDCFE5_DCFE_MEM_PWR_CTRL 0x4503 +#define mmDCFE_MEM_PWR_CTRL2 0x1b04 +#define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x1b04 +#define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x1d04 +#define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x1f04 +#define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x4104 +#define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x4304 +#define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x4504 +#define mmDCFE_MEM_PWR_STATUS 0x1b05 +#define mmDCFE0_DCFE_MEM_PWR_STATUS 0x1b05 +#define mmDCFE1_DCFE_MEM_PWR_STATUS 0x1d05 +#define mmDCFE2_DCFE_MEM_PWR_STATUS 0x1f05 +#define mmDCFE3_DCFE_MEM_PWR_STATUS 0x4105 +#define mmDCFE4_DCFE_MEM_PWR_STATUS 0x4305 +#define mmDCFE5_DCFE_MEM_PWR_STATUS 0x4505 +#define mmDCFE_MISC 0x1b06 +#define mmDCFE0_DCFE_MISC 0x1b06 +#define mmDCFE1_DCFE_MISC 0x1d06 +#define mmDCFE2_DCFE_MISC 0x1f06 +#define mmDCFE3_DCFE_MISC 0x4106 +#define mmDCFE4_DCFE_MISC 0x4306 +#define mmDCFE5_DCFE_MISC 0x4506 +#define mmDCFEV_CLOCK_CONTROL 0x46f4 +#define mmDCFEV_SOFT_RESET 0x46f5 +#define mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6 +#define mmDCFEV_DBG_CONFIG 0x46f7 +#define mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 +#define mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 +#define mmDCFEV_MEM_PWR_CTRL 0x46fa +#define mmDCFEV_MEM_PWR_CTRL2 0x46fb +#define mmDCFEV_MEM_PWR_STATUS 0x46fc +#define mmDCFEV_DMIFV_DEBUG 0x46fd +#define mmDCFEV_MISC 0x46fe +#define mmDC_HPD_INT_STATUS 0x1898 +#define mmHPD0_DC_HPD_INT_STATUS 0x1898 +#define mmHPD1_DC_HPD_INT_STATUS 0x18a0 +#define mmHPD2_DC_HPD_INT_STATUS 0x18a8 +#define mmHPD3_DC_HPD_INT_STATUS 0x18b0 +#define mmHPD4_DC_HPD_INT_STATUS 0x18b8 +#define mmHPD5_DC_HPD_INT_STATUS 0x18c0 +#define mmDC_HPD_INT_CONTROL 0x1899 +#define mmHPD0_DC_HPD_INT_CONTROL 0x1899 +#define mmHPD1_DC_HPD_INT_CONTROL 0x18a1 +#define mmHPD2_DC_HPD_INT_CONTROL 0x18a9 +#define mmHPD3_DC_HPD_INT_CONTROL 0x18b1 +#define mmHPD4_DC_HPD_INT_CONTROL 0x18b9 +#define mmHPD5_DC_HPD_INT_CONTROL 0x18c1 +#define mmDC_HPD_CONTROL 0x189a +#define mmHPD0_DC_HPD_CONTROL 0x189a +#define mmHPD1_DC_HPD_CONTROL 0x18a2 +#define mmHPD2_DC_HPD_CONTROL 0x18aa +#define mmHPD3_DC_HPD_CONTROL 0x18b2 +#define mmHPD4_DC_HPD_CONTROL 0x18ba +#define mmHPD5_DC_HPD_CONTROL 0x18c2 +#define mmDC_HPD_FAST_TRAIN_CNTL 0x189b +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3 +#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab +#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3 +#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb +#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3 +#define mmDC_HPD_TOGGLE_FILT_CNTL 0x189c +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4 +#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac +#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4 +#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc +#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4 +#define mmDCO_SCRATCH0 0x184e +#define mmDCO_SCRATCH1 0x184f +#define mmDCO_SCRATCH2 0x1850 +#define mmDCO_SCRATCH3 0x1851 +#define mmDCO_SCRATCH4 0x1852 +#define mmDCO_SCRATCH5 0x1853 +#define mmDCO_SCRATCH6 0x1854 +#define mmDCO_SCRATCH7 0x1855 +#define mmDCE_VCE_CONTROL 0x1856 +#define mmDISP_INTERRUPT_STATUS 0x1857 +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858 +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859 +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c +#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d +#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e +#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f +#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860 +#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x1875 +#define mmDCO_MEM_PWR_STATUS 0x1861 +#define mmDCO_MEM_PWR_STATUS1 0x1874 +#define mmDCO_MEM_PWR_CTRL 0x1862 +#define mmDCO_MEM_PWR_CTRL2 0x1863 +#define mmDCO_CLK_CNTL 0x1864 +#define mmDCO_CLK_CNTL2 0x1876 +#define mmDCO_CLK_CNTL3 0x1877 +#define mmDPDBG_CNTL 0x1866 +#define mmDPDBG_INTERRUPT 0x1867 +#define mmDCO_POWER_MANAGEMENT_CNTL 0x1868 +#define mmDCO_SOFT_RESET 0x1871 +#define mmDIG_SOFT_RESET 0x1872 +#define mmDIG_SOFT_RESET_2 0x186a +#define mmDCO_STEREOSYNC_SEL 0x186e +#define mmDCO_TEST_DEBUG_INDEX 0x186f +#define mmDCO_TEST_DEBUG_DATA 0x1870 +#define mmDC_I2C_CONTROL 0x16d4 +#define mmDC_I2C_ARBITRATION 0x16d5 +#define mmDC_I2C_INTERRUPT_CONTROL 0x16d6 +#define mmDC_I2C_SW_STATUS 0x16d7 +#define mmDC_I2C_DDC1_HW_STATUS 0x16d8 +#define mmDC_I2C_DDC2_HW_STATUS 0x16d9 +#define mmDC_I2C_DDC3_HW_STATUS 0x16da +#define mmDC_I2C_DDC4_HW_STATUS 0x16db +#define mmDC_I2C_DDC5_HW_STATUS 0x16dc +#define mmDC_I2C_DDC6_HW_STATUS 0x16dd +#define mmDC_I2C_DDC1_SPEED 0x16de +#define mmDC_I2C_DDC1_SETUP 0x16df +#define mmDC_I2C_DDC2_SPEED 0x16e0 +#define mmDC_I2C_DDC2_SETUP 0x16e1 +#define mmDC_I2C_DDC3_SPEED 0x16e2 +#define mmDC_I2C_DDC3_SETUP 0x16e3 +#define mmDC_I2C_DDC4_SPEED 0x16e4 +#define mmDC_I2C_DDC4_SETUP 0x16e5 +#define mmDC_I2C_DDC5_SPEED 0x16e6 +#define mmDC_I2C_DDC5_SETUP 0x16e7 +#define mmDC_I2C_DDC6_SPEED 0x16e8 +#define mmDC_I2C_DDC6_SETUP 0x16e9 +#define mmDC_I2C_TRANSACTION0 0x16ea +#define mmDC_I2C_TRANSACTION1 0x16eb +#define mmDC_I2C_TRANSACTION2 0x16ec +#define mmDC_I2C_TRANSACTION3 0x16ed +#define mmDC_I2C_DATA 0x16ee +#define mmDC_I2C_DDCVGA_HW_STATUS 0x16ef +#define mmDC_I2C_DDCVGA_SPEED 0x16f0 +#define mmDC_I2C_DDCVGA_SETUP 0x16f1 +#define mmDC_I2C_EDID_DETECT_CTRL 0x16f2 +#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3 +#define mmGENERIC_I2C_CONTROL 0x16f4 +#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5 +#define mmGENERIC_I2C_STATUS 0x16f6 +#define mmGENERIC_I2C_SPEED 0x16f7 +#define mmGENERIC_I2C_SETUP 0x16f8 +#define mmGENERIC_I2C_TRANSACTION 0x16f9 +#define mmGENERIC_I2C_DATA 0x16fa +#define mmGENERIC_I2C_PIN_SELECTION 0x16fb +#define mmGENERIC_I2C_PIN_DEBUG 0x16fc +#define mmBLNDV_CONTROL 0x476d +#define mmBLNDV_SM_CONTROL2 0x476e +#define mmBLNDV_CONTROL2 0x476f +#define mmBLNDV_UPDATE 0x4770 +#define mmBLNDV_UNDERFLOW_INTERRUPT 0x4771 +#define mmBLNDV_V_UPDATE_LOCK 0x4773 +#define mmBLNDV_REG_UPDATE_STATUS 0x4777 +#define mmBLNDV_DEBUG 0x4774 +#define mmBLNDV_TEST_DEBUG_INDEX 0x4775 +#define mmBLNDV_TEST_DEBUG_DATA 0x4776 +#define mmCRTCV_H_BLANK_EARLY_NUM 0x477d +#define mmCRTCV_H_TOTAL 0x4780 +#define mmCRTCV_H_BLANK_START_END 0x4781 +#define mmCRTCV_H_SYNC_A 0x4782 +#define mmCRTCV_H_SYNC_A_CNTL 0x4783 +#define mmCRTCV_H_SYNC_B 0x4784 +#define mmCRTCV_H_SYNC_B_CNTL 0x4785 +#define mmCRTCV_VBI_END 0x4786 +#define mmCRTCV_V_TOTAL 0x4787 +#define mmCRTCV_V_TOTAL_MIN 0x4788 +#define mmCRTCV_V_TOTAL_MAX 0x4789 +#define mmCRTCV_V_TOTAL_CONTROL 0x478a +#define mmCRTCV_V_TOTAL_INT_STATUS 0x478b +#define mmCRTCV_VSYNC_NOM_INT_STATUS 0x478c +#define mmCRTCV_V_BLANK_START_END 0x478d +#define mmCRTCV_V_SYNC_A 0x478e +#define mmCRTCV_V_SYNC_A_CNTL 0x478f +#define mmCRTCV_V_SYNC_B 0x4790 +#define mmCRTCV_V_SYNC_B_CNTL 0x4791 +#define mmCRTCV_DTMTEST_CNTL 0x4792 +#define mmCRTCV_DTMTEST_STATUS_POSITION 0x4793 +#define mmCRTCV_TRIGA_CNTL 0x4794 +#define mmCRTCV_TRIGA_MANUAL_TRIG 0x4795 +#define mmCRTCV_TRIGB_CNTL 0x4796 +#define mmCRTCV_TRIGB_MANUAL_TRIG 0x4797 +#define mmCRTCV_FORCE_COUNT_NOW_CNTL 0x4798 +#define mmCRTCV_FLOW_CONTROL 0x4799 +#define mmCRTCV_STEREO_FORCE_NEXT_EYE 0x479a +#define mmCRTCV_AVSYNC_COUNTER 0x479b +#define mmCRTCV_CONTROL 0x479c +#define mmCRTCV_BLANK_CONTROL 0x479d +#define mmCRTCV_INTERLACE_CONTROL 0x479e +#define mmCRTCV_INTERLACE_STATUS 0x479f +#define mmCRTCV_FIELD_INDICATION_CONTROL 0x47a0 +#define mmCRTCV_PIXEL_DATA_READBACK0 0x47a1 +#define mmCRTCV_PIXEL_DATA_READBACK1 0x47a2 +#define mmCRTCV_STATUS 0x47a3 +#define mmCRTCV_STATUS_POSITION 0x47a4 +#define mmCRTCV_NOM_VERT_POSITION 0x47a5 +#define mmCRTCV_STATUS_FRAME_COUNT 0x47a6 +#define mmCRTCV_STATUS_VF_COUNT 0x47a7 +#define mmCRTCV_STATUS_HV_COUNT 0x47a8 +#define mmCRTCV_COUNT_CONTROL 0x47a9 +#define mmCRTCV_COUNT_RESET 0x47aa +#define mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab +#define mmCRTCV_VERT_SYNC_CONTROL 0x47ac +#define mmCRTCV_STEREO_STATUS 0x47ad +#define mmCRTCV_STEREO_CONTROL 0x47ae +#define mmCRTCV_SNAPSHOT_STATUS 0x47af +#define mmCRTCV_SNAPSHOT_CONTROL 0x47b0 +#define mmCRTCV_SNAPSHOT_POSITION 0x47b1 +#define mmCRTCV_SNAPSHOT_FRAME 0x47b2 +#define mmCRTCV_START_LINE_CONTROL 0x47b3 +#define mmCRTCV_INTERRUPT_CONTROL 0x47b4 +#define mmCRTCV_UPDATE_LOCK 0x47b5 +#define mmCRTCV_DOUBLE_BUFFER_CONTROL 0x47b6 +#define mmCRTCV_VGA_PARAMETER_CAPTURE_MODE 0x47b7 +#define mmCRTCV_TEST_PATTERN_CONTROL 0x47ba +#define mmCRTCV_TEST_PATTERN_PARAMETERS 0x47bb +#define mmCRTCV_TEST_PATTERN_COLOR 0x47bc +#define mmCRTCV_MASTER_UPDATE_LOCK 0x47bd +#define mmCRTCV_MASTER_UPDATE_MODE 0x47be +#define mmCRTCV_MVP_INBAND_CNTL_INSERT 0x47bf +#define mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 +#define mmCRTCV_MVP_STATUS 0x47c1 +#define mmCRTCV_MASTER_EN 0x47c2 +#define mmCRTCV_ALLOW_STOP_OFF_V_CNT 0x47c3 +#define mmCRTCV_V_UPDATE_INT_STATUS 0x47c4 +#define mmCRTCV_OVERSCAN_COLOR 0x47c8 +#define mmCRTCV_OVERSCAN_COLOR_EXT 0x47c9 +#define mmCRTCV_BLANK_DATA_COLOR 0x47ca +#define mmCRTCV_BLANK_DATA_COLOR_EXT 0x47cb +#define mmCRTCV_BLACK_COLOR 0x47cc +#define mmCRTCV_BLACK_COLOR_EXT 0x47cd +#define mmCRTCV_VERTICAL_INTERRUPT0_POSITION 0x47ce +#define mmCRTCV_VERTICAL_INTERRUPT0_CONTROL 0x47cf +#define mmCRTCV_VERTICAL_INTERRUPT1_POSITION 0x47d0 +#define mmCRTCV_VERTICAL_INTERRUPT1_CONTROL 0x47d1 +#define mmCRTCV_VERTICAL_INTERRUPT2_POSITION 0x47d2 +#define mmCRTCV_VERTICAL_INTERRUPT2_CONTROL 0x47d3 +#define mmCRTCV_CRC_CNTL 0x47d4 +#define mmCRTCV_CRC0_WINDOWA_X_CONTROL 0x47d5 +#define mmCRTCV_CRC0_WINDOWA_Y_CONTROL 0x47d6 +#define mmCRTCV_CRC0_WINDOWB_X_CONTROL 0x47d7 +#define mmCRTCV_CRC0_WINDOWB_Y_CONTROL 0x47d8 +#define mmCRTCV_CRC0_DATA_RG 0x47d9 +#define mmCRTCV_CRC0_DATA_B 0x47da +#define mmCRTCV_CRC1_WINDOWA_X_CONTROL 0x47db +#define mmCRTCV_CRC1_WINDOWA_Y_CONTROL 0x47dc +#define mmCRTCV_CRC1_WINDOWB_X_CONTROL 0x47dd +#define mmCRTCV_CRC1_WINDOWB_Y_CONTROL 0x47de +#define mmCRTCV_CRC1_DATA_RG 0x47df +#define mmCRTCV_CRC1_DATA_B 0x47e0 +#define mmCRTCV_STATIC_SCREEN_CONTROL 0x47e7 +#define mmCRTCV_3D_STRUCTURE_CONTROL 0x4778 +#define mmCRTCV_GSL_VSYNC_GAP 0x4779 +#define mmCRTCV_GSL_WINDOW 0x477a +#define mmCRTCV_GSL_CONTROL 0x477b +#define mmCRTCV_TEST_DEBUG_INDEX 0x47c6 +#define mmCRTCV_TEST_DEBUG_DATA 0x47c7 +#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 +#define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 +#define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 +#define mmXDMA_INTERRUPT 0x3e3 +#define mmXDMA_CLOCK_GATING_CNTL 0x3e4 +#define mmXDMA_MEM_POWER_CNTL 0x3e6 +#define mmXDMA_IF_BIF_STATUS 0x3e7 +#define mmXDMA_PERF_MEAS_STATUS 0x3e8 +#define mmXDMA_IF_STATUS 0x3e9 +#define mmXDMA_TEST_DEBUG_INDEX 0x3ea +#define mmXDMA_TEST_DEBUG_DATA 0x3eb +#define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 +#define mmXDMA_PG_CONTROL 0x3f9 +#define mmXDMA_PG_WDATA 0x3fa +#define mmXDMA_PG_STATUS 0x3fb +#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc +#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd +#define mmXDMA_MSTR_CNTL 0x3ec +#define mmXDMA_MSTR_STATUS 0x3ed +#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 +#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 +#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 +#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 +#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 +#define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 +#define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 +#define mmXDMA_MSTR_PIPE_CNTL 0x400 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 +#define mmXDMA_MSTR_READ_COMMAND 0x401 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 +#define mmXDMA_MSTR_CHANNEL_DIM 0x402 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 +#define mmXDMA_MSTR_HEIGHT 0x403 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 +#define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 +#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 +#define mmXDMA_MSTR_CACHE 0x40a +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a +#define mmXDMA_MSTR_CHANNEL_START 0x40b +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b +#define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e +#define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f +#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f +#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f +#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f +#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f +#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f +#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f +#define mmXDMA_SLV_CNTL 0x460 +#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 +#define mmXDMA_SLV_SLS_PITCH 0x462 +#define mmXDMA_SLV_READ_URGENT_CNTL 0x463 +#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 +#define mmXDMA_SLV_WB_RATE_CNTL 0x465 +#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 +#define mmXDMA_SLV_READ_LATENCY_AVE 0x467 +#define mmXDMA_SLV_PCIE_NACK_STATUS 0x468 +#define mmXDMA_SLV_MEM_NACK_STATUS 0x469 +#define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a +#define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b +#define mmXDMA_SLV_FLIP_PENDING 0x46c +#define mmXDMA_SLV_CHANNEL_CNTL 0x470 +#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 +#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 +#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 +#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 +#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 +#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 +#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 +#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 +#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 +#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a +#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 +#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a +#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 +#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a + +#endif /* DCE_11_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h new file mode 100644 index 000000000000..d74bca76e261 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h @@ -0,0 +1,6129 @@ +/* + * DCE_11_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_11_0_ENUM_H +#define DCE_11_0_ENUM_H + +typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL { + CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0, + CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1, +} CRTC_CONTROL_CRTC_START_POINT_CNTL; +typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL { + CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0, + CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1, +} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL; +typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL { + CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0, + CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1, + CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2, + CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3, +} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL; +typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY { + CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0, + CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1, +} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY; +typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE { + CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0, + CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1, +} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE; +typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN { + CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x0, + CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x1, +} CRTC_CONTROL_CRTC_SOF_PULL_EN; +typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL { + CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x0, + CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x1, +} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL { + CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x1, +} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL { + CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x1, +} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN { + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1, +} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC { + CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1, +} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT { + CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1, +} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT; +typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK { + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe, + CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf, +} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK; +typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK { + CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0, + CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1, +} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK; +typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR { + CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0, + CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1, +} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR; +typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL { + CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x0, + CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x1, +} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL; +typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN { + CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x0, + CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x1, +} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN; +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT { + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x7, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x8, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x9, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0xa, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0xb, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0xc, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VIDEO = 0xf, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x10, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x11, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x12, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x13, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16, + CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT; +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT { + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6, + CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT; +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN { + CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0, + CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN; +typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR { + CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x0, + CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x1, +} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR; +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT { + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x7, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x8, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x9, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0xa, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0xb, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0xc, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VIDEO = 0xf, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x10, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x11, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x12, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x13, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16, + CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT; +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT { + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6, + CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT; +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN { + CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0, + CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN; +typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR { + CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x0, + CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x1, +} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR; +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE { + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE; +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK { + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK; +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL { + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL; +typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR { + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0, + CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1, +} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR; +typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT { + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GPIO= 0x10, +} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT; +typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY { + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1, +} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY; +typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY { + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0, + CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1, +} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY; +typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE { + CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0, + CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1, + CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2, + CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3, +} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE; +typedef enum CRTC_CONTROL_CRTC_MASTER_EN { + CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x0, + CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x1, +} CRTC_CONTROL_CRTC_MASTER_EN; +typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN { + CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x0, + CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x1, +} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN; +typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE { + CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x0, + CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x1, +} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE; +typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE { + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0, + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1, +} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE; +typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD { + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0, + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1, + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2, + CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3, +} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD; +typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY { + CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0, + CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1, +} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY; +typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT { + CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0, + CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1, +} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT; +typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN { + CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x0, + CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x1, +} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN; +typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE { + CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0, + CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1, +} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE; +typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR { + CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0, + CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1, +} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR; +typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE { + CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0, + CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1, + CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2, + CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3, +} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE; +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY { + CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0, + CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1, +} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY; +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY { + CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0, + CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1, +} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY; +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY { + CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0, + CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1, +} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY; +typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN { + CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x0, + CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x1, +} CRTC_STEREO_CONTROL_CRTC_STEREO_EN; +typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR { + CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x0, + CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x1, +} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR; +typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL { + CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0, + CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1, + CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2, + CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3, +} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL; +typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY { + CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0, + CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1, +} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY; +typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY { + CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0, + CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1, +} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY; +typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN { + CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0, + CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1, +} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN; +typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN { + CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x0, + CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x1, +} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK { + CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK; +typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE { + CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0, + CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1, +} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE; +typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK { + CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x0, + CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x1, +} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK; +typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY { + CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0, + CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1, +} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY; +typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN { + CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0, + CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1, +} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN; +typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE { + CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0, + CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1, +} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE; +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN { + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN; +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE { + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE; +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE { + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE; +typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT { + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2, + CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3, +} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT; +typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK { + MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x0, + MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x1, +} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; +typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK { + MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0, + MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1, +} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK; +typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK { + MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x0, + MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x1, +} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK; +typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE { + MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x0, + MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x1, + MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x2, + MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x3, +} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE; +typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE { + MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0, + MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1, + MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2, + MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3, +} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; +typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE { + CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0, + CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1, + CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2, +} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE; +typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR { + CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x0, + CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x1, +} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR; +typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR { + CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0, + CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1, +} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR; +typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR { + CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0, + CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1, +} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR; +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY { + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE { + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE; +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR { + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR; +typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE { + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE; +typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR { + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR; +typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE { + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE; +typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE { + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE; +typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR { + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR; +typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE { + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE; +typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE { + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0, + CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1, +} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE; +typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN { + CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x0, + CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x1, +} CRTC_CRC_CNTL_CRTC_CRC_EN; +typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN { + CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x0, + CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x1, +} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN; +typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE { + CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x0, + CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x1, + CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x2, + CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x3, +} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE; +typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE { + CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x0, + CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x1, + CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2, + CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3, +} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE; +typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS { + CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0, + CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1, +} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS; +typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT { + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x0, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x1, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x2, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x3, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x4, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x5, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x6, + CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x7, +} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT; +typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT { + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x0, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x1, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x2, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x3, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x4, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x5, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x6, + CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x7, +} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT; +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE { + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0, + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE; +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR { + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0, + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR; +typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE { + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0, + CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1, +} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE; +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN { + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN; +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB { + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB; +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE { + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE; +typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR { + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0, + CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1, +} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR; +typedef enum CRTC_V_SYNC_A_POL { + CRTC_V_SYNC_A_POL_HIGH = 0x0, + CRTC_V_SYNC_A_POL_LOW = 0x1, +} CRTC_V_SYNC_A_POL; +typedef enum CRTC_H_SYNC_A_POL { + CRTC_H_SYNC_A_POL_HIGH = 0x0, + CRTC_H_SYNC_A_POL_LOW = 0x1, +} CRTC_H_SYNC_A_POL; +typedef enum CRTC_HORZ_REPETITION_COUNT { + CRTC_HORZ_REPETITION_COUNT_0 = 0x0, + CRTC_HORZ_REPETITION_COUNT_1 = 0x1, + CRTC_HORZ_REPETITION_COUNT_2 = 0x2, + CRTC_HORZ_REPETITION_COUNT_3 = 0x3, + CRTC_HORZ_REPETITION_COUNT_4 = 0x4, + CRTC_HORZ_REPETITION_COUNT_5 = 0x5, + CRTC_HORZ_REPETITION_COUNT_6 = 0x6, + CRTC_HORZ_REPETITION_COUNT_7 = 0x7, + CRTC_HORZ_REPETITION_COUNT_8 = 0x8, + CRTC_HORZ_REPETITION_COUNT_9 = 0x9, + CRTC_HORZ_REPETITION_COUNT_10 = 0xa, + CRTC_HORZ_REPETITION_COUNT_11 = 0xb, + CRTC_HORZ_REPETITION_COUNT_12 = 0xc, + CRTC_HORZ_REPETITION_COUNT_13 = 0xd, + CRTC_HORZ_REPETITION_COUNT_14 = 0xe, + CRTC_HORZ_REPETITION_COUNT_15 = 0xf, +} CRTC_HORZ_REPETITION_COUNT; +typedef enum PERFCOUNTER_CVALUE_SEL { + PERFCOUNTER_CVALUE_SEL_47_0 = 0x0, + PERFCOUNTER_CVALUE_SEL_15_0 = 0x1, + PERFCOUNTER_CVALUE_SEL_31_16 = 0x2, + PERFCOUNTER_CVALUE_SEL_47_32 = 0x3, + PERFCOUNTER_CVALUE_SEL_11_0 = 0x4, + PERFCOUNTER_CVALUE_SEL_23_12 = 0x5, + PERFCOUNTER_CVALUE_SEL_35_24 = 0x6, + PERFCOUNTER_CVALUE_SEL_47_36 = 0x7, +} PERFCOUNTER_CVALUE_SEL; +typedef enum PERFCOUNTER_INC_MODE { + PERFCOUNTER_INC_MODE_MULTI_BIT = 0x0, + PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x1, + PERFCOUNTER_INC_MODE_LSB = 0x2, + PERFCOUNTER_INC_MODE_POS_EDGE = 0x3, +} PERFCOUNTER_INC_MODE; +typedef enum PERFCOUNTER_HW_CNTL_SEL { + PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x0, + PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x1, +} PERFCOUNTER_HW_CNTL_SEL; +typedef enum PERFCOUNTER_RUNEN_MODE { + PERFCOUNTER_RUNEN_MODE_LEVEL = 0x0, + PERFCOUNTER_RUNEN_MODE_EDGE = 0x1, +} PERFCOUNTER_RUNEN_MODE; +typedef enum PERFCOUNTER_CNTOFF_START_DIS { + PERFCOUNTER_CNTOFF_START_ENABLE = 0x0, + PERFCOUNTER_CNTOFF_START_DISABLE = 0x1, +} PERFCOUNTER_CNTOFF_START_DIS; +typedef enum PERFCOUNTER_RESTART_EN { + PERFCOUNTER_RESTART_DISABLE = 0x0, + PERFCOUNTER_RESTART_ENABLE = 0x1, +} PERFCOUNTER_RESTART_EN; +typedef enum PERFCOUNTER_INT_EN { + PERFCOUNTER_INT_DISABLE = 0x0, + PERFCOUNTER_INT_ENABLE = 0x1, +} PERFCOUNTER_INT_EN; +typedef enum PERFCOUNTER_OFF_MASK { + PERFCOUNTER_OFF_MASK_DISABLE = 0x0, + PERFCOUNTER_OFF_MASK_ENABLE = 0x1, +} PERFCOUNTER_OFF_MASK; +typedef enum PERFCOUNTER_ACTIVE { + PERFCOUNTER_IS_IDLE = 0x0, + PERFCOUNTER_IS_ACTIVE = 0x1, +} PERFCOUNTER_ACTIVE; +typedef enum PERFCOUNTER_INT_TYPE { + PERFCOUNTER_INT_TYPE_LEVEL = 0x0, + PERFCOUNTER_INT_TYPE_PULSE = 0x1, +} PERFCOUNTER_INT_TYPE; +typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE { + PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x0, + PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x1, +} PERFCOUNTER_COUNTED_VALUE_TYPE; +typedef enum PERFCOUNTER_CNTL_SEL { + PERFCOUNTER_CNTL_SEL_0 = 0x0, + PERFCOUNTER_CNTL_SEL_1 = 0x1, + PERFCOUNTER_CNTL_SEL_2 = 0x2, + PERFCOUNTER_CNTL_SEL_3 = 0x3, + PERFCOUNTER_CNTL_SEL_4 = 0x4, + PERFCOUNTER_CNTL_SEL_5 = 0x5, + PERFCOUNTER_CNTL_SEL_6 = 0x6, + PERFCOUNTER_CNTL_SEL_7 = 0x7, +} PERFCOUNTER_CNTL_SEL; +typedef enum PERFCOUNTER_CNT0_STATE { + PERFCOUNTER_CNT0_STATE_RESET = 0x0, + PERFCOUNTER_CNT0_STATE_START = 0x1, + PERFCOUNTER_CNT0_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT0_STATE_HW = 0x3, +} PERFCOUNTER_CNT0_STATE; +typedef enum PERFCOUNTER_STATE_SEL0 { + PERFCOUNTER_STATE_SEL0_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL0_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL0; +typedef enum PERFCOUNTER_CNT1_STATE { + PERFCOUNTER_CNT1_STATE_RESET = 0x0, + PERFCOUNTER_CNT1_STATE_START = 0x1, + PERFCOUNTER_CNT1_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT1_STATE_HW = 0x3, +} PERFCOUNTER_CNT1_STATE; +typedef enum PERFCOUNTER_STATE_SEL1 { + PERFCOUNTER_STATE_SEL1_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL1_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL1; +typedef enum PERFCOUNTER_CNT2_STATE { + PERFCOUNTER_CNT2_STATE_RESET = 0x0, + PERFCOUNTER_CNT2_STATE_START = 0x1, + PERFCOUNTER_CNT2_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT2_STATE_HW = 0x3, +} PERFCOUNTER_CNT2_STATE; +typedef enum PERFCOUNTER_STATE_SEL2 { + PERFCOUNTER_STATE_SEL2_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL2_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL2; +typedef enum PERFCOUNTER_CNT3_STATE { + PERFCOUNTER_CNT3_STATE_RESET = 0x0, + PERFCOUNTER_CNT3_STATE_START = 0x1, + PERFCOUNTER_CNT3_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT3_STATE_HW = 0x3, +} PERFCOUNTER_CNT3_STATE; +typedef enum PERFCOUNTER_STATE_SEL3 { + PERFCOUNTER_STATE_SEL3_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL3_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL3; +typedef enum PERFCOUNTER_CNT4_STATE { + PERFCOUNTER_CNT4_STATE_RESET = 0x0, + PERFCOUNTER_CNT4_STATE_START = 0x1, + PERFCOUNTER_CNT4_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT4_STATE_HW = 0x3, +} PERFCOUNTER_CNT4_STATE; +typedef enum PERFCOUNTER_STATE_SEL4 { + PERFCOUNTER_STATE_SEL4_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL4_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL4; +typedef enum PERFCOUNTER_CNT5_STATE { + PERFCOUNTER_CNT5_STATE_RESET = 0x0, + PERFCOUNTER_CNT5_STATE_START = 0x1, + PERFCOUNTER_CNT5_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT5_STATE_HW = 0x3, +} PERFCOUNTER_CNT5_STATE; +typedef enum PERFCOUNTER_STATE_SEL5 { + PERFCOUNTER_STATE_SEL5_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL5_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL5; +typedef enum PERFCOUNTER_CNT6_STATE { + PERFCOUNTER_CNT6_STATE_RESET = 0x0, + PERFCOUNTER_CNT6_STATE_START = 0x1, + PERFCOUNTER_CNT6_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT6_STATE_HW = 0x3, +} PERFCOUNTER_CNT6_STATE; +typedef enum PERFCOUNTER_STATE_SEL6 { + PERFCOUNTER_STATE_SEL6_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL6_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL6; +typedef enum PERFCOUNTER_CNT7_STATE { + PERFCOUNTER_CNT7_STATE_RESET = 0x0, + PERFCOUNTER_CNT7_STATE_START = 0x1, + PERFCOUNTER_CNT7_STATE_FREEZE = 0x2, + PERFCOUNTER_CNT7_STATE_HW = 0x3, +} PERFCOUNTER_CNT7_STATE; +typedef enum PERFCOUNTER_STATE_SEL7 { + PERFCOUNTER_STATE_SEL7_GLOBAL = 0x0, + PERFCOUNTER_STATE_SEL7_LOCAL = 0x1, +} PERFCOUNTER_STATE_SEL7; +typedef enum PERFMON_STATE { + PERFMON_STATE_RESET = 0x0, + PERFMON_STATE_START = 0x1, + PERFMON_STATE_FREEZE = 0x2, + PERFMON_STATE_HW = 0x3, +} PERFMON_STATE; +typedef enum PERFMON_CNTOFF_AND_OR { + PERFMON_CNTOFF_OR = 0x0, + PERFMON_CNTOFF_AND = 0x1, +} PERFMON_CNTOFF_AND_OR; +typedef enum PERFMON_CNTOFF_INT_EN { + PERFMON_CNTOFF_INT_DISABLE = 0x0, + PERFMON_CNTOFF_INT_ENABLE = 0x1, +} PERFMON_CNTOFF_INT_EN; +typedef enum PERFMON_CNTOFF_INT_TYPE { + PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x0, + PERFMON_CNTOFF_INT_TYPE_PULSE = 0x1, +} PERFMON_CNTOFF_INT_TYPE; +typedef enum LptNumBanks { + LPT_NUM_BANKS_2BANK = 0x0, + LPT_NUM_BANKS_4BANK = 0x1, + LPT_NUM_BANKS_8BANK = 0x2, + LPT_NUM_BANKS_16BANK = 0x3, + LPT_NUM_BANKS_32BANK = 0x4, +} LptNumBanks; +typedef enum DCIO_DC_GENERICA_SEL { + DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0, + DCIO_GENERICA_SEL_STEREOSYNC = 0x1, + DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2, + DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3, + DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4, + DCIO_GENERICA_SEL_P1_PLLCLK = 0x5, + DCIO_GENERICA_SEL_P2_PLLCLK = 0x6, + DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7, + DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8, + DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9, + DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa, + DCIO_GENERICA_SEL_SYNCEN = 0xb, + DCIO_GENERICA_SEL_GENERICA_SCG = 0xc, + DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd, + DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe, + DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf, + DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10, + DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11, +} DCIO_DC_GENERICA_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { + DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0, + DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1, + DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2, + DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3, + DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4, + DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5, + DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x6, + DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x7, + DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x8, +} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { + DCIO_UNIPHYA_FBDIV_CLK = 0x0, + DCIO_UNIPHYB_FBDIV_CLK = 0x1, + DCIO_UNIPHYC_FBDIV_CLK = 0x2, + DCIO_UNIPHYD_FBDIV_CLK = 0x3, + DCIO_UNIPHYE_FBDIV_CLK = 0x4, + DCIO_UNIPHYF_FBDIV_CLK = 0x5, + DCIO_UNIPHYG_FBDIV_CLK = 0x6, + DCIO_UNIPHYLPA_FBDIV_CLK = 0x7, + DCIO_UNIPHYLPB_FBDIV_CLK = 0x8, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { + DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0, + DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1, + DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2, + DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3, + DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4, + DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5, + DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x6, + DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x7, + DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x8, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; +typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { + DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0, + DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1, + DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2, + DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3, + DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4, + DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5, + DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x6, + DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x7, + DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x8, +} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; +typedef enum DCIO_DC_GENERICB_SEL { + DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0, + DCIO_GENERICB_SEL_STEREOSYNC = 0x1, + DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2, + DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3, + DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4, + DCIO_GENERICB_SEL_P1_PLLCLK = 0x5, + DCIO_GENERICB_SEL_P2_PLLCLK = 0x6, + DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7, + DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8, + DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9, + DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa, + DCIO_GENERICB_SEL_SYNCEN = 0xb, + DCIO_GENERICB_SEL_GENERICA_SCG = 0xc, + DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd, + DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe, + DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf, +} DCIO_DC_GENERICB_SEL; +typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL { + DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0, + DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5, + DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6, + DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7, + DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb, + DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc, + DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd, + DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe, + DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf, +} DCIO_DC_PAD_EXTERN_SIG_SEL; +typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS { + DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0, + DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1, + DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2, + DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3, +} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS; +typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL { + DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0, + DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1, + DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2, + DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3, +} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; +typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { + DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0, + DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1, + DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2, + DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3, +} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; +typedef enum DCIO_DC_GPIO_VIP_DEBUG { + DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0, + DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1, +} DCIO_DC_GPIO_VIP_DEBUG; +typedef enum DCIO_DC_GPIO_MACRO_DEBUG { + DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0, + DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1, + DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2, + DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3, +} DCIO_DC_GPIO_MACRO_DEBUG; +typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL { + DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0, + DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1, +} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL; +typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN { + DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0, + DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1, +} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN; +typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE { + DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0, + DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1, +} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; +typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION { + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6, + DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7, +} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION; +typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { + DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0, + DCIO_UNIPHY_CHANNEL_INVERTED = 0x1, +} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; +typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0, + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1, + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2, + DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3, +} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; +typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0, + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1, + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2, + DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3, +} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; +typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN { + DCIO_VIP_MUX_EN_DVO = 0x0, + DCIO_VIP_MUX_EN_VIP = 0x1, +} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN; +typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN { + DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0, + DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, +} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN; +typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN { + DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0, + DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, +} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN { + DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0, + DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE { + DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0, + DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL { + DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0, + DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON { + DCIO_LVTMA_DIGON_OFF = 0x0, + DCIO_LVTMA_DIGON_ON = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL { + DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0, + DCIO_LVTMA_DIGON_POL_INVERT = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON { + DCIO_LVTMA_BLON_OFF = 0x0, + DCIO_LVTMA_BLON_ON = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON; +typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL { + DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0, + DCIO_LVTMA_BLON_POL_INVERT = 0x1, +} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL; +typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN { + DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0, + DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1, +} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN; +typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { + DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0, + DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1, +} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; +typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN { + DCIO_BL_PWM_DISABLE = 0x0, + DCIO_BL_PWM_ENABLE = 0x1, +} DCIO_BL_PWM_CNTL_BL_PWM_EN; +typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT { + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0, + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1, + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2, + DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3, +} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; +typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { + DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0, + DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1, +} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; +typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN { + DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0, + DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1, +} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN; +typedef enum DCIO_BL_PWM_GRP1_REG_LOCK { + DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0, + DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1, +} DCIO_BL_PWM_GRP1_REG_LOCK; +typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START { + DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0, + DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1, +} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START; +typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4, + DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5, +} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; +typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { + DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0, + DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1, +} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; +typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { + DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0, + DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1, +} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; +typedef enum DCIO_GSL_SEL { + DCIO_GSL_SEL_GROUP_0 = 0x0, + DCIO_GSL_SEL_GROUP_1 = 0x1, + DCIO_GSL_SEL_GROUP_2 = 0x2, +} DCIO_GSL_SEL; +typedef enum DCIO_GENLK_CLK_GSL_MASK { + DCIO_GENLK_CLK_GSL_MASK_NO = 0x0, + DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1, + DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2, +} DCIO_GENLK_CLK_GSL_MASK; +typedef enum DCIO_GENLK_VSYNC_GSL_MASK { + DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0, + DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1, + DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2, +} DCIO_GENLK_VSYNC_GSL_MASK; +typedef enum DCIO_SWAPLOCK_A_GSL_MASK { + DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0, + DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1, + DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2, +} DCIO_SWAPLOCK_A_GSL_MASK; +typedef enum DCIO_SWAPLOCK_B_GSL_MASK { + DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0, + DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1, + DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2, +} DCIO_SWAPLOCK_B_GSL_MASK; +typedef enum DCIO_GSL_VSYNC_SEL { + DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0, + DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1, + DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2, + DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3, + DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4, + DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5, +} DCIO_GSL_VSYNC_SEL; +typedef enum DCIO_GSL0_TIMING_SYNC_SEL { + DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0, + DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, + DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL0_TIMING_SYNC_SEL; +typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL { + DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL0_GLOBAL_UNLOCK_SEL; +typedef enum DCIO_GSL1_TIMING_SYNC_SEL { + DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0, + DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, + DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL1_TIMING_SYNC_SEL; +typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL { + DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL1_GLOBAL_UNLOCK_SEL; +typedef enum DCIO_GSL2_TIMING_SYNC_SEL { + DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0, + DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, + DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL2_TIMING_SYNC_SEL; +typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL { + DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, + DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, +} DCIO_GSL2_GLOBAL_UNLOCK_SEL; +typedef enum DCIO_DC_GPU_TIMER_START_POSITION { + DCIO_GPU_TIMER_START_0_END_27 = 0x0, + DCIO_GPU_TIMER_START_1_END_28 = 0x1, + DCIO_GPU_TIMER_START_2_END_29 = 0x2, + DCIO_GPU_TIMER_START_3_END_30 = 0x3, + DCIO_GPU_TIMER_START_4_END_31 = 0x4, + DCIO_GPU_TIMER_START_6_END_33 = 0x5, + DCIO_GPU_TIMER_START_8_END_35 = 0x6, + DCIO_GPU_TIMER_START_10_END_37 = 0x7, +} DCIO_DC_GPU_TIMER_START_POSITION; +typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { + DCIO_TEST_CLK_SEL_DISPCLK = 0x0, + DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1, + DCIO_TEST_CLK_SEL_SCLK = 0x2, +} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; +typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { + DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0, + DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1, +} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; +typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX { + DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0, + DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1, + DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2, + DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3, + DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4, + DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5, + DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6, + DCIO_EXT_VSYNC_MUX_GENERICB = 0x7, +} DCIO_DCO_DCFE_EXT_VSYNC_MUX; +typedef enum DCIO_DCO_EXT_VSYNC_MASK { + DCIO_EXT_VSYNC_MASK_NONE = 0x0, + DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1, + DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2, + DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3, + DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4, + DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5, + DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6, + DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7, +} DCIO_DCO_EXT_VSYNC_MASK; +typedef enum DCIO_DBG_OUT_PIN_SEL { + DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0, + DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1, +} DCIO_DBG_OUT_PIN_SEL; +typedef enum DCIO_DBG_OUT_12BIT_SEL { + DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0, + DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1, + DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2, + DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3, +} DCIO_DBG_OUT_12BIT_SEL; +typedef enum DCIO_DSYNC_SOFT_RESET { + DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0, + DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1, +} DCIO_DSYNC_SOFT_RESET; +typedef enum DCIO_DACA_SOFT_RESET { + DCIO_DACA_SOFT_RESET_DEASSERT = 0x0, + DCIO_DACA_SOFT_RESET_ASSERT = 0x1, +} DCIO_DACA_SOFT_RESET; +typedef enum DCIO_DCRXPHY_SOFT_RESET { + DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0, + DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1, +} DCIO_DCRXPHY_SOFT_RESET; +typedef enum DCIO_DPHY_LANE_SEL { + DCIO_DPHY_LANE_SEL_LANE0 = 0x0, + DCIO_DPHY_LANE_SEL_LANE1 = 0x1, + DCIO_DPHY_LANE_SEL_LANE2 = 0x2, + DCIO_DPHY_LANE_SEL_LANE3 = 0x3, +} DCIO_DPHY_LANE_SEL; +typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { + DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b, + DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c, + DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d, + DCIO_GPU_TIMER_READ_SELECT_LOWER_DCFEV_P_FLIP = 0x24, + DCIO_GPU_TIMER_READ_SELECT_UPPER_DCFEV_P_FLIP = 0x25, +} DCIO_DC_GPU_TIMER_READ_SELECT; +typedef enum DCIO_IMPCAL_STEP_DELAY { + DCIO_IMPCAL_STEP_DELAY_1us = 0x0, + DCIO_IMPCAL_STEP_DELAY_2us = 0x1, + DCIO_IMPCAL_STEP_DELAY_3us = 0x2, + DCIO_IMPCAL_STEP_DELAY_4us = 0x3, + DCIO_IMPCAL_STEP_DELAY_5us = 0x4, + DCIO_IMPCAL_STEP_DELAY_6us = 0x5, + DCIO_IMPCAL_STEP_DELAY_7us = 0x6, + DCIO_IMPCAL_STEP_DELAY_8us = 0x7, + DCIO_IMPCAL_STEP_DELAY_9us = 0x8, + DCIO_IMPCAL_STEP_DELAY_10us = 0x9, + DCIO_IMPCAL_STEP_DELAY_11us = 0xa, + DCIO_IMPCAL_STEP_DELAY_12us = 0xb, + DCIO_IMPCAL_STEP_DELAY_13us = 0xc, + DCIO_IMPCAL_STEP_DELAY_14us = 0xd, + DCIO_IMPCAL_STEP_DELAY_15us = 0xe, + DCIO_IMPCAL_STEP_DELAY_16us = 0xf, +} DCIO_IMPCAL_STEP_DELAY; +typedef enum DCIO_UNIPHY_IMPCAL_SEL { + DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0, + DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1, +} DCIO_UNIPHY_IMPCAL_SEL; +typedef enum DCIOCHIP_HPD_SEL { + DCIOCHIP_HPD_SEL_ASYNC = 0x0, + DCIOCHIP_HPD_SEL_CLOCKED = 0x1, +} DCIOCHIP_HPD_SEL; +typedef enum DCIOCHIP_PAD_MODE { + DCIOCHIP_PAD_MODE_DDC = 0x0, + DCIOCHIP_PAD_MODE_DP = 0x1, +} DCIOCHIP_PAD_MODE; +typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE { + DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0, + DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1, +} DCIOCHIP_AUXSLAVE_PAD_MODE; +typedef enum DCIOCHIP_INVERT { + DCIOCHIP_POL_NON_INVERT = 0x0, + DCIOCHIP_POL_INVERT = 0x1, +} DCIOCHIP_INVERT; +typedef enum DCIOCHIP_PD_EN { + DCIOCHIP_PD_EN_NOTALLOW = 0x0, + DCIOCHIP_PD_EN_ALLOW = 0x1, +} DCIOCHIP_PD_EN; +typedef enum DCIOCHIP_GPIO_MASK_EN { + DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0, + DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1, +} DCIOCHIP_GPIO_MASK_EN; +typedef enum DCIOCHIP_MASK { + DCIOCHIP_MASK_DISABLE = 0x0, + DCIOCHIP_MASK_ENABLE = 0x1, +} DCIOCHIP_MASK; +typedef enum DCIOCHIP_GPIO_I2C_MASK { + DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0, + DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1, +} DCIOCHIP_GPIO_I2C_MASK; +typedef enum DCIOCHIP_GPIO_I2C_DRIVE { + DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0, + DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1, +} DCIOCHIP_GPIO_I2C_DRIVE; +typedef enum DCIOCHIP_GPIO_I2C_EN { + DCIOCHIP_GPIO_I2C_DISABLE = 0x0, + DCIOCHIP_GPIO_I2C_ENABLE = 0x1, +} DCIOCHIP_GPIO_I2C_EN; +typedef enum DCIOCHIP_MASK_4BIT { + DCIOCHIP_MASK_4BIT_DISABLE = 0x0, + DCIOCHIP_MASK_4BIT_ENABLE = 0xf, +} DCIOCHIP_MASK_4BIT; +typedef enum DCIOCHIP_ENABLE_4BIT { + DCIOCHIP_4BIT_DISABLE = 0x0, + DCIOCHIP_4BIT_ENABLE = 0xf, +} DCIOCHIP_ENABLE_4BIT; +typedef enum DCIOCHIP_MASK_5BIT { + DCIOCHIP_MASIK_5BIT_DISABLE = 0x0, + DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f, +} DCIOCHIP_MASK_5BIT; +typedef enum DCIOCHIP_ENABLE_5BIT { + DCIOCHIP_5BIT_DISABLE = 0x0, + DCIOCHIP_5BIT_ENABLE = 0x1f, +} DCIOCHIP_ENABLE_5BIT; +typedef enum DCIOCHIP_MASK_2BIT { + DCIOCHIP_MASK_2BIT_DISABLE = 0x0, + DCIOCHIP_MASK_2BIT_ENABLE = 0x3, +} DCIOCHIP_MASK_2BIT; +typedef enum DCIOCHIP_ENABLE_2BIT { + DCIOCHIP_2BIT_DISABLE = 0x0, + DCIOCHIP_2BIT_ENABLE = 0x3, +} DCIOCHIP_ENABLE_2BIT; +typedef enum DCIOCHIP_REF_27_SRC_SEL { + DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0, + DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1, + DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2, + DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3, +} DCIOCHIP_REF_27_SRC_SEL; +typedef enum DCIOCHIP_DVO_VREFPON { + DCIOCHIP_DVO_VREFPON_DISABLE = 0x0, + DCIOCHIP_DVO_VREFPON_ENABLE = 0x1, +} DCIOCHIP_DVO_VREFPON; +typedef enum DCIOCHIP_DVO_VREFSEL { + DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0, + DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1, +} DCIOCHIP_DVO_VREFSEL; +typedef enum DCP_GRPH_ENABLE { + DCP_GRPH_ENABLE_FALSE = 0x0, + DCP_GRPH_ENABLE_TRUE = 0x1, +} DCP_GRPH_ENABLE; +typedef enum DCP_GRPH_KEYER_ALPHA_SEL { + DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x0, + DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x1, +} DCP_GRPH_KEYER_ALPHA_SEL; +typedef enum DCP_GRPH_DEPTH { + DCP_GRPH_DEPTH_8BPP = 0x0, + DCP_GRPH_DEPTH_16BPP = 0x1, + DCP_GRPH_DEPTH_32BPP = 0x2, + DCP_GRPH_DEPTH_64BPP = 0x3, +} DCP_GRPH_DEPTH; +typedef enum DCP_GRPH_NUM_BANKS { + DCP_GRPH_NUM_BANKS_2BANK = 0x0, + DCP_GRPH_NUM_BANKS_4BANK = 0x1, + DCP_GRPH_NUM_BANKS_8BANK = 0x2, + DCP_GRPH_NUM_BANKS_16BANK = 0x3, +} DCP_GRPH_NUM_BANKS; +typedef enum DCP_GRPH_BANK_WIDTH { + DCP_GRPH_BANK_WIDTH_1 = 0x0, + DCP_GRPH_BANK_WIDTH_2 = 0x1, + DCP_GRPH_BANK_WIDTH_4 = 0x2, + DCP_GRPH_BANK_WIDTH_8 = 0x3, +} DCP_GRPH_BANK_WIDTH; +typedef enum DCP_GRPH_FORMAT { + DCP_GRPH_FORMAT_8BPP = 0x0, + DCP_GRPH_FORMAT_16BPP = 0x1, + DCP_GRPH_FORMAT_32BPP = 0x2, + DCP_GRPH_FORMAT_64BPP = 0x3, +} DCP_GRPH_FORMAT; +typedef enum DCP_GRPH_BANK_HEIGHT { + DCP_GRPH_BANK_HEIGHT_1 = 0x0, + DCP_GRPH_BANK_HEIGHT_2 = 0x1, + DCP_GRPH_BANK_HEIGHT_4 = 0x2, + DCP_GRPH_BANK_HEIGHT_8 = 0x3, +} DCP_GRPH_BANK_HEIGHT; +typedef enum DCP_GRPH_TILE_SPLIT { + DCP_GRPH_TILE_SPLIT_64B = 0x0, + DCP_GRPH_TILE_SPLIT_128B = 0x1, + DCP_GRPH_TILE_SPLIT_256B = 0x2, + DCP_GRPH_TILE_SPLIT_512B = 0x3, + DCP_GRPH_TILE_SPLIT_1B = 0x4, + DCP_GRPH_TILE_SPLIT_2B = 0x5, + DCP_GRPH_TILE_SPLIT_4B = 0x6, +} DCP_GRPH_TILE_SPLIT; +typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE { + DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x0, + DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x1, +} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE; +typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE { + DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE = 0x0, + DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE = 0x1, +} DCP_GRPH_PRIVILEGED_ACCESS_ENABLE; +typedef enum DCP_GRPH_MACRO_TILE_ASPECT { + DCP_GRPH_MACRO_TILE_ASPECT_1 = 0x0, + DCP_GRPH_MACRO_TILE_ASPECT_2 = 0x1, + DCP_GRPH_MACRO_TILE_ASPECT_4 = 0x2, + DCP_GRPH_MACRO_TILE_ASPECT_8 = 0x3, +} DCP_GRPH_MACRO_TILE_ASPECT; +typedef enum DCP_GRPH_ARRAY_MODE { + DCP_GRPH_ARRAY_MODE_0 = 0x0, + DCP_GRPH_ARRAY_MODE_1 = 0x1, + DCP_GRPH_ARRAY_MODE_2 = 0x2, + DCP_GRPH_ARRAY_MODE_3 = 0x3, + DCP_GRPH_ARRAY_MODE_4 = 0x4, + DCP_GRPH_ARRAY_MODE_7 = 0x7, + DCP_GRPH_ARRAY_MODE_12 = 0xc, + DCP_GRPH_ARRAY_MODE_13 = 0xd, +} DCP_GRPH_ARRAY_MODE; +typedef enum DCP_GRPH_MICRO_TILE_MODE { + DCP_GRPH_MICRO_TILE_MODE_0 = 0x0, + DCP_GRPH_MICRO_TILE_MODE_1 = 0x1, + DCP_GRPH_MICRO_TILE_MODE_2 = 0x2, + DCP_GRPH_MICRO_TILE_MODE_3 = 0x3, +} DCP_GRPH_MICRO_TILE_MODE; +typedef enum DCP_GRPH_COLOR_EXPANSION_MODE { + DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x0, + DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x1, +} DCP_GRPH_COLOR_EXPANSION_MODE; +typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN { + DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x0, + DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x1, +} DCP_GRPH_LUT_10BIT_BYPASS_EN; +typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN { + DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x0, + DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x1, +} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN; +typedef enum DCP_GRPH_ENDIAN_SWAP { + DCP_GRPH_ENDIAN_SWAP_NONE = 0x0, + DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x1, + DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x2, + DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x3, +} DCP_GRPH_ENDIAN_SWAP; +typedef enum DCP_GRPH_RED_CROSSBAR { + DCP_GRPH_RED_CROSSBAR_FROM_R = 0x0, + DCP_GRPH_RED_CROSSBAR_FROM_G = 0x1, + DCP_GRPH_RED_CROSSBAR_FROM_B = 0x2, + DCP_GRPH_RED_CROSSBAR_FROM_A = 0x3, +} DCP_GRPH_RED_CROSSBAR; +typedef enum DCP_GRPH_GREEN_CROSSBAR { + DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x0, + DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x1, + DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x2, + DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x3, +} DCP_GRPH_GREEN_CROSSBAR; +typedef enum DCP_GRPH_BLUE_CROSSBAR { + DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x0, + DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x1, + DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x2, + DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x3, +} DCP_GRPH_BLUE_CROSSBAR; +typedef enum DCP_GRPH_ALPHA_CROSSBAR { + DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x0, + DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x1, + DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x2, + DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x3, +} DCP_GRPH_ALPHA_CROSSBAR; +typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE { + DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x0, + DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x1, +} DCP_GRPH_PRIMARY_DFQ_ENABLE; +typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE { + DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x0, + DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x1, +} DCP_GRPH_SECONDARY_DFQ_ENABLE; +typedef enum DCP_GRPH_INPUT_GAMMA_MODE { + DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x0, + DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x1, +} DCP_GRPH_INPUT_GAMMA_MODE; +typedef enum DCP_GRPH_MODE_UPDATE_PENDING { + DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x0, + DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x1, +} DCP_GRPH_MODE_UPDATE_PENDING; +typedef enum DCP_GRPH_MODE_UPDATE_TAKEN { + DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x0, + DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x1, +} DCP_GRPH_MODE_UPDATE_TAKEN; +typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING { + DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x0, + DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x1, +} DCP_GRPH_SURFACE_UPDATE_PENDING; +typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN { + DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x0, + DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x1, +} DCP_GRPH_SURFACE_UPDATE_TAKEN; +typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE { + DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x0, + DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x1, +} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE; +typedef enum DCP_GRPH_UPDATE_LOCK { + DCP_GRPH_UPDATE_LOCK_FALSE = 0x0, + DCP_GRPH_UPDATE_LOCK_TRUE = 0x1, +} DCP_GRPH_UPDATE_LOCK; +typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK { + DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x0, + DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x1, +} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; +typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE { + DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, + DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, +} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; +typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE { + DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, + DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, +} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; +typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN { + DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x0, + DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x1, +} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN; +typedef enum DCP_GRPH_XDMA_SUPER_AA_EN { + DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x0, + DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x1, +} DCP_GRPH_XDMA_SUPER_AA_EN; +typedef enum DCP_GRPH_DFQ_RESET { + DCP_GRPH_DFQ_RESET_FALSE = 0x0, + DCP_GRPH_DFQ_RESET_TRUE = 0x1, +} DCP_GRPH_DFQ_RESET; +typedef enum DCP_GRPH_DFQ_SIZE { + DCP_GRPH_DFQ_SIZE_DEEP1 = 0x0, + DCP_GRPH_DFQ_SIZE_DEEP2 = 0x1, + DCP_GRPH_DFQ_SIZE_DEEP3 = 0x2, + DCP_GRPH_DFQ_SIZE_DEEP4 = 0x3, + DCP_GRPH_DFQ_SIZE_DEEP5 = 0x4, + DCP_GRPH_DFQ_SIZE_DEEP6 = 0x5, + DCP_GRPH_DFQ_SIZE_DEEP7 = 0x6, + DCP_GRPH_DFQ_SIZE_DEEP8 = 0x7, +} DCP_GRPH_DFQ_SIZE; +typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES { + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x0, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x1, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x2, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x3, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x4, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x5, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x6, + DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x7, +} DCP_GRPH_DFQ_MIN_FREE_ENTRIES; +typedef enum DCP_GRPH_DFQ_RESET_ACK { + DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x0, + DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x1, +} DCP_GRPH_DFQ_RESET_ACK; +typedef enum DCP_GRPH_PFLIP_INT_CLEAR { + DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x0, + DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x1, +} DCP_GRPH_PFLIP_INT_CLEAR; +typedef enum DCP_GRPH_PFLIP_INT_MASK { + DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x0, + DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x1, +} DCP_GRPH_PFLIP_INT_MASK; +typedef enum DCP_GRPH_PFLIP_INT_TYPE { + DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x0, + DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x1, +} DCP_GRPH_PFLIP_INT_TYPE; +typedef enum DCP_GRPH_PRESCALE_SELECT { + DCP_GRPH_PRESCALE_SELECT_FIXED = 0x0, + DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x1, +} DCP_GRPH_PRESCALE_SELECT; +typedef enum DCP_GRPH_PRESCALE_R_SIGN { + DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x0, + DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x1, +} DCP_GRPH_PRESCALE_R_SIGN; +typedef enum DCP_GRPH_PRESCALE_G_SIGN { + DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x0, + DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x1, +} DCP_GRPH_PRESCALE_G_SIGN; +typedef enum DCP_GRPH_PRESCALE_B_SIGN { + DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x0, + DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x1, +} DCP_GRPH_PRESCALE_B_SIGN; +typedef enum DCP_GRPH_PRESCALE_BYPASS { + DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x0, + DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x1, +} DCP_GRPH_PRESCALE_BYPASS; +typedef enum DCP_INPUT_CSC_GRPH_MODE { + DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x0, + DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x1, + DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x2, + DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x3, +} DCP_INPUT_CSC_GRPH_MODE; +typedef enum DCP_OUTPUT_CSC_GRPH_MODE { + DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x0, + DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x1, + DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x2, + DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x3, + DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x4, + DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x5, + DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x6, + DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x7, +} DCP_OUTPUT_CSC_GRPH_MODE; +typedef enum DCP_DENORM_MODE { + DCP_DENORM_MODE_UNITY = 0x0, + DCP_DENORM_MODE_6BIT = 0x1, + DCP_DENORM_MODE_8BIT = 0x2, + DCP_DENORM_MODE_10BIT = 0x3, + DCP_DENORM_MODE_11BIT = 0x4, + DCP_DENORM_MODE_12BIT = 0x5, + DCP_DENORM_MODE_RESERVED0 = 0x6, + DCP_DENORM_MODE_RESERVED1 = 0x7, +} DCP_DENORM_MODE; +typedef enum DCP_DENORM_14BIT_OUT { + DCP_DENORM_14BIT_OUT_FALSE = 0x0, + DCP_DENORM_14BIT_OUT_TRUE = 0x1, +} DCP_DENORM_14BIT_OUT; +typedef enum DCP_OUT_ROUND_TRUNC_MODE { + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x0, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x1, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x2, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x3, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x4, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x5, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x6, + DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x7, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x8, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x9, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0xa, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0xb, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0xc, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0xd, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0xe, + DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0xf, +} DCP_OUT_ROUND_TRUNC_MODE; +typedef enum DCP_KEY_MODE { + DCP_KEY_MODE_ALPHA0 = 0x0, + DCP_KEY_MODE_ALPHA1 = 0x1, + DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x2, + DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x3, +} DCP_KEY_MODE; +typedef enum DCP_GRPH_DEGAMMA_MODE { + DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x0, + DCP_GRPH_DEGAMMA_MODE_ROMA = 0x1, + DCP_GRPH_DEGAMMA_MODE_ROMB = 0x2, + DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x3, +} DCP_GRPH_DEGAMMA_MODE; +typedef enum DCP_CURSOR2_DEGAMMA_MODE { + DCP_CURSOR2_DEGAMMA_MODE_BYPASS = 0x0, + DCP_CURSOR2_DEGAMMA_MODE_ROMA = 0x1, + DCP_CURSOR2_DEGAMMA_MODE_ROMB = 0x2, + DCP_CURSOR2_DEGAMMA_MODE_RESERVED = 0x3, +} DCP_CURSOR2_DEGAMMA_MODE; +typedef enum DCP_CURSOR_DEGAMMA_MODE { + DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x0, + DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x1, + DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x2, + DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x3, +} DCP_CURSOR_DEGAMMA_MODE; +typedef enum DCP_GRPH_GAMUT_REMAP_MODE { + DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x0, + DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x1, + DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x2, + DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x3, +} DCP_GRPH_GAMUT_REMAP_MODE; +typedef enum DCP_SPATIAL_DITHER_EN { + DCP_SPATIAL_DITHER_EN_FALSE = 0x0, + DCP_SPATIAL_DITHER_EN_TRUE = 0x1, +} DCP_SPATIAL_DITHER_EN; +typedef enum DCP_SPATIAL_DITHER_MODE { + DCP_SPATIAL_DITHER_MODE_BYPASS = 0x0, + DCP_SPATIAL_DITHER_MODE_ROMA = 0x1, + DCP_SPATIAL_DITHER_MODE_ROMB = 0x2, + DCP_SPATIAL_DITHER_MODE_RESERVED = 0x3, +} DCP_SPATIAL_DITHER_MODE; +typedef enum DCP_SPATIAL_DITHER_DEPTH { + DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x0, + DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x1, + DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x2, + DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x3, +} DCP_SPATIAL_DITHER_DEPTH; +typedef enum DCP_FRAME_RANDOM_ENABLE { + DCP_FRAME_RANDOM_ENABLE_FALSE = 0x0, + DCP_FRAME_RANDOM_ENABLE_TRUE = 0x1, +} DCP_FRAME_RANDOM_ENABLE; +typedef enum DCP_RGB_RANDOM_ENABLE { + DCP_RGB_RANDOM_ENABLE_FALSE = 0x0, + DCP_RGB_RANDOM_ENABLE_TRUE = 0x1, +} DCP_RGB_RANDOM_ENABLE; +typedef enum DCP_HIGHPASS_RANDOM_ENABLE { + DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x0, + DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x1, +} DCP_HIGHPASS_RANDOM_ENABLE; +typedef enum DCP_CURSOR_EN { + DCP_CURSOR_EN_FALSE = 0x0, + DCP_CURSOR_EN_TRUE = 0x1, +} DCP_CURSOR_EN; +typedef enum DCP_CUR_INV_TRANS_CLAMP { + DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x0, + DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x1, +} DCP_CUR_INV_TRANS_CLAMP; +typedef enum DCP_CURSOR_MODE { + DCP_CURSOR_MODE_MONO_2BPP = 0x0, + DCP_CURSOR_MODE_24BPP_1BIT = 0x1, + DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x2, + DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x3, +} DCP_CURSOR_MODE; +typedef enum DCP_CURSOR_2X_MAGNIFY { + DCP_CURSOR_2X_MAGNIFY_FALSE = 0x0, + DCP_CURSOR_2X_MAGNIFY_TRUE = 0x1, +} DCP_CURSOR_2X_MAGNIFY; +typedef enum DCP_CURSOR_FORCE_MC_ON { + DCP_CURSOR_FORCE_MC_ON_FALSE = 0x0, + DCP_CURSOR_FORCE_MC_ON_TRUE = 0x1, +} DCP_CURSOR_FORCE_MC_ON; +typedef enum DCP_CURSOR_URGENT_CONTROL { + DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x0, + DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x1, + DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x2, + DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x3, + DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x4, +} DCP_CURSOR_URGENT_CONTROL; +typedef enum DCP_CURSOR_UPDATE_PENDING { + DCP_CURSOR_UPDATE_PENDING_FALSE = 0x0, + DCP_CURSOR_UPDATE_PENDING_TRUE = 0x1, +} DCP_CURSOR_UPDATE_PENDING; +typedef enum DCP_CURSOR_UPDATE_TAKEN { + DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x0, + DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x1, +} DCP_CURSOR_UPDATE_TAKEN; +typedef enum DCP_CURSOR_UPDATE_LOCK { + DCP_CURSOR_UPDATE_LOCK_FALSE = 0x0, + DCP_CURSOR_UPDATE_LOCK_TRUE = 0x1, +} DCP_CURSOR_UPDATE_LOCK; +typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE { + DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, + DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, +} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE; +typedef enum DCP_CURSOR_UPDATE_STEREO_MODE { + DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x0, + DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1, + DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x2, + DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3, +} DCP_CURSOR_UPDATE_STEREO_MODE; +typedef enum DCP_CURSOR2_EN { + DCP_CURSOR2_EN_FALSE = 0x0, + DCP_CURSOR2_EN_TRUE = 0x1, +} DCP_CURSOR2_EN; +typedef enum DCP_CUR2_INV_TRANS_CLAMP { + DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x0, + DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x1, +} DCP_CUR2_INV_TRANS_CLAMP; +typedef enum DCP_CURSOR2_MODE { + DCP_CURSOR2_MODE_MONO_2BPP = 0x0, + DCP_CURSOR2_MODE_24BPP_1BIT = 0x1, + DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI = 0x2, + DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI = 0x3, +} DCP_CURSOR2_MODE; +typedef enum DCP_CURSOR2_2X_MAGNIFY { + DCP_CURSOR2_2X_MAGNIFY_FALSE = 0x0, + DCP_CURSOR2_2X_MAGNIFY_TRUE = 0x1, +} DCP_CURSOR2_2X_MAGNIFY; +typedef enum DCP_CURSOR2_FORCE_MC_ON { + DCP_CURSOR2_FORCE_MC_ON_FALSE = 0x0, + DCP_CURSOR2_FORCE_MC_ON_TRUE = 0x1, +} DCP_CURSOR2_FORCE_MC_ON; +typedef enum DCP_CURSOR2_URGENT_CONTROL { + DCP_CURSOR2_URGENT_CONTROL_MODE_0 = 0x0, + DCP_CURSOR2_URGENT_CONTROL_MODE_1 = 0x1, + DCP_CURSOR2_URGENT_CONTROL_MODE_2 = 0x2, + DCP_CURSOR2_URGENT_CONTROL_MODE_3 = 0x3, + DCP_CURSOR2_URGENT_CONTROL_MODE_4 = 0x4, +} DCP_CURSOR2_URGENT_CONTROL; +typedef enum DCP_CURSOR2_UPDATE_PENDING { + DCP_CURSOR2_UPDATE_PENDING_FALSE = 0x0, + DCP_CURSOR2_UPDATE_PENDING_TRUE = 0x1, +} DCP_CURSOR2_UPDATE_PENDING; +typedef enum DCP_CURSOR2_UPDATE_TAKEN { + DCP_CURSOR2_UPDATE_TAKEN_FALSE = 0x0, + DCP_CURSOR2_UPDATE_TAKEN_TRUE = 0x1, +} DCP_CURSOR2_UPDATE_TAKEN; +typedef enum DCP_CURSOR2_UPDATE_LOCK { + DCP_CURSOR2_UPDATE_LOCK_FALSE = 0x0, + DCP_CURSOR2_UPDATE_LOCK_TRUE = 0x1, +} DCP_CURSOR2_UPDATE_LOCK; +typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE { + DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, + DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, +} DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE; +typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE { + DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH = 0x0, + DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1, + DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED = 0x2, + DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3, +} DCP_CURSOR2_UPDATE_STEREO_MODE; +typedef enum DCP_CUR_REQUEST_FILTER_DIS { + DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x0, + DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x1, +} DCP_CUR_REQUEST_FILTER_DIS; +typedef enum DCP_CURSOR_STEREO_EN { + DCP_CURSOR_STEREO_EN_FALSE = 0x0, + DCP_CURSOR_STEREO_EN_TRUE = 0x1, +} DCP_CURSOR_STEREO_EN; +typedef enum DCP_CURSOR_STEREO_OFFSET_YNX { + DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x0, + DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x1, +} DCP_CURSOR_STEREO_OFFSET_YNX; +typedef enum DCP_CURSOR2_STEREO_EN { + DCP_CURSOR2_STEREO_EN_FALSE = 0x0, + DCP_CURSOR2_STEREO_EN_TRUE = 0x1, +} DCP_CURSOR2_STEREO_EN; +typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX { + DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION = 0x0, + DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION = 0x1, +} DCP_CURSOR2_STEREO_OFFSET_YNX; +typedef enum DCP_DC_LUT_RW_MODE { + DCP_DC_LUT_RW_MODE_256_ENTRY = 0x0, + DCP_DC_LUT_RW_MODE_PWL = 0x1, +} DCP_DC_LUT_RW_MODE; +typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE { + DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x0, + DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x1, +} DCP_DC_LUT_VGA_ACCESS_ENABLE; +typedef enum DCP_DC_LUT_AUTOFILL { + DCP_DC_LUT_AUTOFILL_FALSE = 0x0, + DCP_DC_LUT_AUTOFILL_TRUE = 0x1, +} DCP_DC_LUT_AUTOFILL; +typedef enum DCP_DC_LUT_AUTOFILL_DONE { + DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x0, + DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x1, +} DCP_DC_LUT_AUTOFILL_DONE; +typedef enum DCP_DC_LUT_INC_B { + DCP_DC_LUT_INC_B_NA = 0x0, + DCP_DC_LUT_INC_B_2 = 0x1, + DCP_DC_LUT_INC_B_4 = 0x2, + DCP_DC_LUT_INC_B_8 = 0x3, + DCP_DC_LUT_INC_B_16 = 0x4, + DCP_DC_LUT_INC_B_32 = 0x5, + DCP_DC_LUT_INC_B_64 = 0x6, + DCP_DC_LUT_INC_B_128 = 0x7, + DCP_DC_LUT_INC_B_256 = 0x8, + DCP_DC_LUT_INC_B_512 = 0x9, +} DCP_DC_LUT_INC_B; +typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN { + DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_B_SIGNED_EN; +typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN { + DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN; +typedef enum DCP_DC_LUT_DATA_B_FORMAT { + DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x0, + DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x1, + DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x2, + DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x3, +} DCP_DC_LUT_DATA_B_FORMAT; +typedef enum DCP_DC_LUT_INC_G { + DCP_DC_LUT_INC_G_NA = 0x0, + DCP_DC_LUT_INC_G_2 = 0x1, + DCP_DC_LUT_INC_G_4 = 0x2, + DCP_DC_LUT_INC_G_8 = 0x3, + DCP_DC_LUT_INC_G_16 = 0x4, + DCP_DC_LUT_INC_G_32 = 0x5, + DCP_DC_LUT_INC_G_64 = 0x6, + DCP_DC_LUT_INC_G_128 = 0x7, + DCP_DC_LUT_INC_G_256 = 0x8, + DCP_DC_LUT_INC_G_512 = 0x9, +} DCP_DC_LUT_INC_G; +typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN { + DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_G_SIGNED_EN; +typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN { + DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN; +typedef enum DCP_DC_LUT_DATA_G_FORMAT { + DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x0, + DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x1, + DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x2, + DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x3, +} DCP_DC_LUT_DATA_G_FORMAT; +typedef enum DCP_DC_LUT_INC_R { + DCP_DC_LUT_INC_R_NA = 0x0, + DCP_DC_LUT_INC_R_2 = 0x1, + DCP_DC_LUT_INC_R_4 = 0x2, + DCP_DC_LUT_INC_R_8 = 0x3, + DCP_DC_LUT_INC_R_16 = 0x4, + DCP_DC_LUT_INC_R_32 = 0x5, + DCP_DC_LUT_INC_R_64 = 0x6, + DCP_DC_LUT_INC_R_128 = 0x7, + DCP_DC_LUT_INC_R_256 = 0x8, + DCP_DC_LUT_INC_R_512 = 0x9, +} DCP_DC_LUT_INC_R; +typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN { + DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_R_SIGNED_EN; +typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN { + DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x0, + DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x1, +} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN; +typedef enum DCP_DC_LUT_DATA_R_FORMAT { + DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x0, + DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x1, + DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x2, + DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x3, +} DCP_DC_LUT_DATA_R_FORMAT; +typedef enum DCP_CRC_ENABLE { + DCP_CRC_ENABLE_FALSE = 0x0, + DCP_CRC_ENABLE_TRUE = 0x1, +} DCP_CRC_ENABLE; +typedef enum DCP_CRC_SOURCE_SEL { + DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x0, + DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x1, + DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x2, + DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x4, +} DCP_CRC_SOURCE_SEL; +typedef enum DCP_CRC_LINE_SEL { + DCP_CRC_LINE_SEL_RESERVED = 0x0, + DCP_CRC_LINE_SEL_EVEN = 0x1, + DCP_CRC_LINE_SEL_ODD = 0x2, + DCP_CRC_LINE_SEL_BOTH = 0x3, +} DCP_CRC_LINE_SEL; +typedef enum DCP_GRPH_FLIP_RATE { + DCP_GRPH_FLIP_RATE_1FRAME = 0x0, + DCP_GRPH_FLIP_RATE_2FRAME = 0x1, + DCP_GRPH_FLIP_RATE_3FRAME = 0x2, + DCP_GRPH_FLIP_RATE_4FRAME = 0x3, + DCP_GRPH_FLIP_RATE_5FRAME = 0x4, + DCP_GRPH_FLIP_RATE_6FRAME = 0x5, + DCP_GRPH_FLIP_RATE_7FRAME = 0x6, + DCP_GRPH_FLIP_RATE_8FRAME = 0x7, +} DCP_GRPH_FLIP_RATE; +typedef enum DCP_GRPH_FLIP_RATE_ENABLE { + DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x0, + DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x1, +} DCP_GRPH_FLIP_RATE_ENABLE; +typedef enum DCP_GSL0_EN { + DCP_GSL0_EN_FALSE = 0x0, + DCP_GSL0_EN_TRUE = 0x1, +} DCP_GSL0_EN; +typedef enum DCP_GSL1_EN { + DCP_GSL1_EN_FALSE = 0x0, + DCP_GSL1_EN_TRUE = 0x1, +} DCP_GSL1_EN; +typedef enum DCP_GSL2_EN { + DCP_GSL2_EN_FALSE = 0x0, + DCP_GSL2_EN_TRUE = 0x1, +} DCP_GSL2_EN; +typedef enum DCP_GSL_MASTER_EN { + DCP_GSL_MASTER_EN_FALSE = 0x0, + DCP_GSL_MASTER_EN_TRUE = 0x1, +} DCP_GSL_MASTER_EN; +typedef enum DCP_GSL_XDMA_GROUP { + DCP_GSL_XDMA_GROUP_VSYNC = 0x0, + DCP_GSL_XDMA_GROUP_HSYNC0 = 0x1, + DCP_GSL_XDMA_GROUP_HSYNC1 = 0x2, + DCP_GSL_XDMA_GROUP_HSYNC2 = 0x3, +} DCP_GSL_XDMA_GROUP; +typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN { + DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x0, + DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x1, +} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN; +typedef enum DCP_GSL_SYNC_SOURCE { + DCP_GSL_SYNC_SOURCE_FLIP = 0x0, + DCP_GSL_SYNC_SOURCE_PHASE0 = 0x1, + DCP_GSL_SYNC_SOURCE_RESET = 0x2, + DCP_GSL_SYNC_SOURCE_PHASE1 = 0x3, +} DCP_GSL_SYNC_SOURCE; +typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING { + DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x0, + DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x1, +} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING; +typedef enum DCP_TEST_DEBUG_WRITE_EN { + DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x0, + DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x1, +} DCP_TEST_DEBUG_WRITE_EN; +typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN { + DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x0, + DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x1, +} DCP_GRPH_STEREOSYNC_FLIP_EN; +typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE { + DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x0, + DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x1, + DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x2, + DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x3, +} DCP_GRPH_STEREOSYNC_FLIP_MODE; +typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE { + DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x0, + DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x1, +} DCP_GRPH_STEREOSYNC_SELECT_DISABLE; +typedef enum DCP_GRPH_ROTATION_ANGLE { + DCP_GRPH_ROTATION_ANGLE_0 = 0x0, + DCP_GRPH_ROTATION_ANGLE_90 = 0x1, + DCP_GRPH_ROTATION_ANGLE_180 = 0x2, + DCP_GRPH_ROTATION_ANGLE_270 = 0x3, +} DCP_GRPH_ROTATION_ANGLE; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE; +typedef enum DCP_GRPH_REGAMMA_MODE { + DCP_GRPH_REGAMMA_MODE_BYPASS = 0x0, + DCP_GRPH_REGAMMA_MODE_SRGB = 0x1, + DCP_GRPH_REGAMMA_MODE_XVYCC = 0x2, + DCP_GRPH_REGAMMA_MODE_PROGA = 0x3, + DCP_GRPH_REGAMMA_MODE_PROGB = 0x4, +} DCP_GRPH_REGAMMA_MODE; +typedef enum DCP_ALPHA_ROUND_TRUNC_MODE { + DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x0, + DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x1, +} DCP_ALPHA_ROUND_TRUNC_MODE; +typedef enum DCP_CURSOR_ALPHA_BLND_ENA { + DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x0, + DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x1, +} DCP_CURSOR_ALPHA_BLND_ENA; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK; +typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK { + DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x0, + DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x1, +} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK; +typedef enum DCP_GRPH_SURFACE_COUNTER_EN { + DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x0, + DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x1, +} DCP_GRPH_SURFACE_COUNTER_EN; +typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT { + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x0, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x1, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x2, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x3, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x4, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x5, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x6, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x7, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x8, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x9, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0xa, + DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0xb, +} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT; +typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED { + DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x0, + DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x1, +} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED; +typedef enum HDMI_KEEPOUT_MODE { + HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x0, + HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x1, +} HDMI_KEEPOUT_MODE; +typedef enum HDMI_CLOCK_CHANNEL_RATE { + HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x0, + HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x1, +} HDMI_CLOCK_CHANNEL_RATE; +typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED { + HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x0, + HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x1, +} HDMI_NO_EXTRA_NULL_PACKET_FILLED; +typedef enum HDMI_PACKET_GEN_VERSION { + HDMI_PACKET_GEN_VERSION_OLD = 0x0, + HDMI_PACKET_GEN_VERSION_NEW = 0x1, +} HDMI_PACKET_GEN_VERSION; +typedef enum HDMI_ERROR_ACK { + HDMI_ERROR_ACK_INT = 0x0, + HDMI_ERROR_NOT_ACK = 0x1, +} HDMI_ERROR_ACK; +typedef enum HDMI_ERROR_MASK { + HDMI_ERROR_MASK_INT = 0x0, + HDMI_ERROR_NOT_MASK = 0x1, +} HDMI_ERROR_MASK; +typedef enum HDMI_DEEP_COLOR_DEPTH { + HDMI_DEEP_COLOR_DEPTH_24BPP = 0x0, + HDMI_DEEP_COLOR_DEPTH_30BPP = 0x1, + HDMI_DEEP_COLOR_DEPTH_36BPP = 0x2, + HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x3, +} HDMI_DEEP_COLOR_DEPTH; +typedef enum HDMI_AUDIO_DELAY_EN { + HDMI_AUDIO_DELAY_DISABLE = 0x0, + HDMI_AUDIO_DELAY_58CLK = 0x1, + HDMI_AUDIO_DELAY_56CLK = 0x2, + HDMI_AUDIO_DELAY_RESERVED = 0x3, +} HDMI_AUDIO_DELAY_EN; +typedef enum HDMI_AUDIO_SEND_MAX_PACKETS { + HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x0, + HDMI_SEND_MAX_AUDIO_PACKETS = 0x1, +} HDMI_AUDIO_SEND_MAX_PACKETS; +typedef enum HDMI_ACR_SEND { + HDMI_ACR_NOT_SEND = 0x0, + HDMI_ACR_PKT_SEND = 0x1, +} HDMI_ACR_SEND; +typedef enum HDMI_ACR_CONT { + HDMI_ACR_CONT_DISABLE = 0x0, + HDMI_ACR_CONT_ENABLE = 0x1, +} HDMI_ACR_CONT; +typedef enum HDMI_ACR_SELECT { + HDMI_ACR_SELECT_HW = 0x0, + HDMI_ACR_SELECT_32K = 0x1, + HDMI_ACR_SELECT_44K = 0x2, + HDMI_ACR_SELECT_48K = 0x3, +} HDMI_ACR_SELECT; +typedef enum HDMI_ACR_SOURCE { + HDMI_ACR_SOURCE_HW = 0x0, + HDMI_ACR_SOURCE_SW = 0x1, +} HDMI_ACR_SOURCE; +typedef enum HDMI_ACR_N_MULTIPLE { + HDMI_ACR_0_MULTIPLE_RESERVED = 0x0, + HDMI_ACR_1_MULTIPLE = 0x1, + HDMI_ACR_2_MULTIPLE = 0x2, + HDMI_ACR_3_MULTIPLE_RESERVED = 0x3, + HDMI_ACR_4_MULTIPLE = 0x4, + HDMI_ACR_5_MULTIPLE_RESERVED = 0x5, + HDMI_ACR_6_MULTIPLE_RESERVED = 0x6, + HDMI_ACR_7_MULTIPLE_RESERVED = 0x7, +} HDMI_ACR_N_MULTIPLE; +typedef enum HDMI_ACR_AUDIO_PRIORITY { + HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x0, + HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x1, +} HDMI_ACR_AUDIO_PRIORITY; +typedef enum HDMI_NULL_SEND { + HDMI_NULL_NOT_SEND = 0x0, + HDMI_NULL_PKT_SEND = 0x1, +} HDMI_NULL_SEND; +typedef enum HDMI_GC_SEND { + HDMI_GC_NOT_SEND = 0x0, + HDMI_GC_PKT_SEND = 0x1, +} HDMI_GC_SEND; +typedef enum HDMI_GC_CONT { + HDMI_GC_CONT_DISABLE = 0x0, + HDMI_GC_CONT_ENABLE = 0x1, +} HDMI_GC_CONT; +typedef enum HDMI_ISRC_SEND { + HDMI_ISRC_NOT_SEND = 0x0, + HDMI_ISRC_PKT_SEND = 0x1, +} HDMI_ISRC_SEND; +typedef enum HDMI_ISRC_CONT { + HDMI_ISRC_CONT_DISABLE = 0x0, + HDMI_ISRC_CONT_ENABLE = 0x1, +} HDMI_ISRC_CONT; +typedef enum HDMI_AVI_INFO_SEND { + HDMI_AVI_INFO_NOT_SEND = 0x0, + HDMI_AVI_INFO_PKT_SEND = 0x1, +} HDMI_AVI_INFO_SEND; +typedef enum HDMI_AVI_INFO_CONT { + HDMI_AVI_INFO_CONT_DISABLE = 0x0, + HDMI_AVI_INFO_CONT_ENABLE = 0x1, +} HDMI_AVI_INFO_CONT; +typedef enum HDMI_AUDIO_INFO_SEND { + HDMI_AUDIO_INFO_NOT_SEND = 0x0, + HDMI_AUDIO_INFO_PKT_SEND = 0x1, +} HDMI_AUDIO_INFO_SEND; +typedef enum HDMI_AUDIO_INFO_CONT { + HDMI_AUDIO_INFO_CONT_DISABLE = 0x0, + HDMI_AUDIO_INFO_CONT_ENABLE = 0x1, +} HDMI_AUDIO_INFO_CONT; +typedef enum HDMI_MPEG_INFO_SEND { + HDMI_MPEG_INFO_NOT_SEND = 0x0, + HDMI_MPEG_INFO_PKT_SEND = 0x1, +} HDMI_MPEG_INFO_SEND; +typedef enum HDMI_MPEG_INFO_CONT { + HDMI_MPEG_INFO_CONT_DISABLE = 0x0, + HDMI_MPEG_INFO_CONT_ENABLE = 0x1, +} HDMI_MPEG_INFO_CONT; +typedef enum HDMI_GENERIC0_SEND { + HDMI_GENERIC0_NOT_SEND = 0x0, + HDMI_GENERIC0_PKT_SEND = 0x1, +} HDMI_GENERIC0_SEND; +typedef enum HDMI_GENERIC0_CONT { + HDMI_GENERIC0_CONT_DISABLE = 0x0, + HDMI_GENERIC0_CONT_ENABLE = 0x1, +} HDMI_GENERIC0_CONT; +typedef enum HDMI_GENERIC1_SEND { + HDMI_GENERIC1_NOT_SEND = 0x0, + HDMI_GENERIC1_PKT_SEND = 0x1, +} HDMI_GENERIC1_SEND; +typedef enum HDMI_GENERIC1_CONT { + HDMI_GENERIC1_CONT_DISABLE = 0x0, + HDMI_GENERIC1_CONT_ENABLE = 0x1, +} HDMI_GENERIC1_CONT; +typedef enum HDMI_GC_AVMUTE_CONT { + HDMI_GC_AVMUTE_CONT_DISABLE = 0x0, + HDMI_GC_AVMUTE_CONT_ENABLE = 0x1, +} HDMI_GC_AVMUTE_CONT; +typedef enum HDMI_PACKING_PHASE_OVERRIDE { + HDMI_PACKING_PHASE_SET_BY_HW = 0x0, + HDMI_PACKING_PHASE_SET_BY_SW = 0x1, +} HDMI_PACKING_PHASE_OVERRIDE; +typedef enum HDMI_GENERIC2_SEND { + HDMI_GENERIC2_NOT_SEND = 0x0, + HDMI_GENERIC2_PKT_SEND = 0x1, +} HDMI_GENERIC2_SEND; +typedef enum HDMI_GENERIC2_CONT { + HDMI_GENERIC2_CONT_DISABLE = 0x0, + HDMI_GENERIC2_CONT_ENABLE = 0x1, +} HDMI_GENERIC2_CONT; +typedef enum HDMI_GENERIC3_SEND { + HDMI_GENERIC3_NOT_SEND = 0x0, + HDMI_GENERIC3_PKT_SEND = 0x1, +} HDMI_GENERIC3_SEND; +typedef enum HDMI_GENERIC3_CONT { + HDMI_GENERIC3_CONT_DISABLE = 0x0, + HDMI_GENERIC3_CONT_ENABLE = 0x1, +} HDMI_GENERIC3_CONT; +typedef enum TMDS_PIXEL_ENCODING { + TMDS_PIXEL_ENCODING_444 = 0x0, + TMDS_PIXEL_ENCODING_422 = 0x1, +} TMDS_PIXEL_ENCODING; +typedef enum TMDS_COLOR_FORMAT { + TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0, + TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x1, + TMDS_COLOR_FORMAT_DUAL30BPP = 0x2, + TMDS_COLOR_FORMAT_RESERVED = 0x3, +} TMDS_COLOR_FORMAT; +typedef enum TMDS_STEREOSYNC_CTL_SEL_REG { + TMDS_STEREOSYNC_CTL0 = 0x0, + TMDS_STEREOSYNC_CTL1 = 0x1, + TMDS_STEREOSYNC_CTL2 = 0x2, + TMDS_STEREOSYNC_CTL3 = 0x3, +} TMDS_STEREOSYNC_CTL_SEL_REG; +typedef enum TMDS_CTL0_DATA_SEL { + TMDS_CTL0_DATA_SEL0_RESERVED = 0x0, + TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x1, + TMDS_CTL0_DATA_SEL2_VSYNC = 0x2, + TMDS_CTL0_DATA_SEL3_RESERVED = 0x3, + TMDS_CTL0_DATA_SEL4_HSYNC = 0x4, + TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x5, + TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x6, + TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x7, +} TMDS_CTL0_DATA_SEL; +typedef enum TMDS_CTL0_DATA_DELAY { + TMDS_CTL0_DATA_DELAY_0PIX = 0x0, + TMDS_CTL0_DATA_DELAY_1PIX = 0x1, + TMDS_CTL0_DATA_DELAY_2PIX = 0x2, + TMDS_CTL0_DATA_DELAY_3PIX = 0x3, + TMDS_CTL0_DATA_DELAY_4PIX = 0x4, + TMDS_CTL0_DATA_DELAY_5PIX = 0x5, + TMDS_CTL0_DATA_DELAY_6PIX = 0x6, + TMDS_CTL0_DATA_DELAY_7PIX = 0x7, +} TMDS_CTL0_DATA_DELAY; +typedef enum TMDS_CTL0_DATA_INVERT { + TMDS_CTL0_DATA_NORMAL = 0x0, + TMDS_CTL0_DATA_INVERT_EN = 0x1, +} TMDS_CTL0_DATA_INVERT; +typedef enum TMDS_CTL0_DATA_MODULATION { + TMDS_CTL0_DATA_MODULATION_DISABLE = 0x0, + TMDS_CTL0_DATA_MODULATION_BIT0 = 0x1, + TMDS_CTL0_DATA_MODULATION_BIT1 = 0x2, + TMDS_CTL0_DATA_MODULATION_BIT2 = 0x3, +} TMDS_CTL0_DATA_MODULATION; +typedef enum TMDS_CTL0_PATTERN_OUT_EN { + TMDS_CTL0_PATTERN_OUT_DISABLE = 0x0, + TMDS_CTL0_PATTERN_OUT_ENABLE = 0x1, +} TMDS_CTL0_PATTERN_OUT_EN; +typedef enum TMDS_CTL1_DATA_SEL { + TMDS_CTL1_DATA_SEL0_RESERVED = 0x0, + TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x1, + TMDS_CTL1_DATA_SEL2_VSYNC = 0x2, + TMDS_CTL1_DATA_SEL3_RESERVED = 0x3, + TMDS_CTL1_DATA_SEL4_HSYNC = 0x4, + TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x5, + TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x6, + TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x7, +} TMDS_CTL1_DATA_SEL; +typedef enum TMDS_CTL1_DATA_DELAY { + TMDS_CTL1_DATA_DELAY_0PIX = 0x0, + TMDS_CTL1_DATA_DELAY_1PIX = 0x1, + TMDS_CTL1_DATA_DELAY_2PIX = 0x2, + TMDS_CTL1_DATA_DELAY_3PIX = 0x3, + TMDS_CTL1_DATA_DELAY_4PIX = 0x4, + TMDS_CTL1_DATA_DELAY_5PIX = 0x5, + TMDS_CTL1_DATA_DELAY_6PIX = 0x6, + TMDS_CTL1_DATA_DELAY_7PIX = 0x7, +} TMDS_CTL1_DATA_DELAY; +typedef enum TMDS_CTL1_DATA_INVERT { + TMDS_CTL1_DATA_NORMAL = 0x0, + TMDS_CTL1_DATA_INVERT_EN = 0x1, +} TMDS_CTL1_DATA_INVERT; +typedef enum TMDS_CTL1_DATA_MODULATION { + TMDS_CTL1_DATA_MODULATION_DISABLE = 0x0, + TMDS_CTL1_DATA_MODULATION_BIT0 = 0x1, + TMDS_CTL1_DATA_MODULATION_BIT1 = 0x2, + TMDS_CTL1_DATA_MODULATION_BIT2 = 0x3, +} TMDS_CTL1_DATA_MODULATION; +typedef enum TMDS_CTL1_PATTERN_OUT_EN { + TMDS_CTL1_PATTERN_OUT_DISABLE = 0x0, + TMDS_CTL1_PATTERN_OUT_ENABLE = 0x1, +} TMDS_CTL1_PATTERN_OUT_EN; +typedef enum TMDS_CTL2_DATA_SEL { + TMDS_CTL2_DATA_SEL0_RESERVED = 0x0, + TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x1, + TMDS_CTL2_DATA_SEL2_VSYNC = 0x2, + TMDS_CTL2_DATA_SEL3_RESERVED = 0x3, + TMDS_CTL2_DATA_SEL4_HSYNC = 0x4, + TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x5, + TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x6, + TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x7, +} TMDS_CTL2_DATA_SEL; +typedef enum TMDS_CTL2_DATA_DELAY { + TMDS_CTL2_DATA_DELAY_0PIX = 0x0, + TMDS_CTL2_DATA_DELAY_1PIX = 0x1, + TMDS_CTL2_DATA_DELAY_2PIX = 0x2, + TMDS_CTL2_DATA_DELAY_3PIX = 0x3, + TMDS_CTL2_DATA_DELAY_4PIX = 0x4, + TMDS_CTL2_DATA_DELAY_5PIX = 0x5, + TMDS_CTL2_DATA_DELAY_6PIX = 0x6, + TMDS_CTL2_DATA_DELAY_7PIX = 0x7, +} TMDS_CTL2_DATA_DELAY; +typedef enum TMDS_CTL2_DATA_INVERT { + TMDS_CTL2_DATA_NORMAL = 0x0, + TMDS_CTL2_DATA_INVERT_EN = 0x1, +} TMDS_CTL2_DATA_INVERT; +typedef enum TMDS_CTL2_DATA_MODULATION { + TMDS_CTL2_DATA_MODULATION_DISABLE = 0x0, + TMDS_CTL2_DATA_MODULATION_BIT0 = 0x1, + TMDS_CTL2_DATA_MODULATION_BIT1 = 0x2, + TMDS_CTL2_DATA_MODULATION_BIT2 = 0x3, +} TMDS_CTL2_DATA_MODULATION; +typedef enum TMDS_CTL2_PATTERN_OUT_EN { + TMDS_CTL2_PATTERN_OUT_DISABLE = 0x0, + TMDS_CTL2_PATTERN_OUT_ENABLE = 0x1, +} TMDS_CTL2_PATTERN_OUT_EN; +typedef enum TMDS_CTL3_DATA_DELAY { + TMDS_CTL3_DATA_DELAY_0PIX = 0x0, + TMDS_CTL3_DATA_DELAY_1PIX = 0x1, + TMDS_CTL3_DATA_DELAY_2PIX = 0x2, + TMDS_CTL3_DATA_DELAY_3PIX = 0x3, + TMDS_CTL3_DATA_DELAY_4PIX = 0x4, + TMDS_CTL3_DATA_DELAY_5PIX = 0x5, + TMDS_CTL3_DATA_DELAY_6PIX = 0x6, + TMDS_CTL3_DATA_DELAY_7PIX = 0x7, +} TMDS_CTL3_DATA_DELAY; +typedef enum TMDS_CTL3_DATA_INVERT { + TMDS_CTL3_DATA_NORMAL = 0x0, + TMDS_CTL3_DATA_INVERT_EN = 0x1, +} TMDS_CTL3_DATA_INVERT; +typedef enum TMDS_CTL3_DATA_MODULATION { + TMDS_CTL3_DATA_MODULATION_DISABLE = 0x0, + TMDS_CTL3_DATA_MODULATION_BIT0 = 0x1, + TMDS_CTL3_DATA_MODULATION_BIT1 = 0x2, + TMDS_CTL3_DATA_MODULATION_BIT2 = 0x3, +} TMDS_CTL3_DATA_MODULATION; +typedef enum TMDS_CTL3_PATTERN_OUT_EN { + TMDS_CTL3_PATTERN_OUT_DISABLE = 0x0, + TMDS_CTL3_PATTERN_OUT_ENABLE = 0x1, +} TMDS_CTL3_PATTERN_OUT_EN; +typedef enum TMDS_CTL3_DATA_SEL { + TMDS_CTL3_DATA_SEL0_RESERVED = 0x0, + TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x1, + TMDS_CTL3_DATA_SEL2_VSYNC = 0x2, + TMDS_CTL3_DATA_SEL3_RESERVED = 0x3, + TMDS_CTL3_DATA_SEL4_HSYNC = 0x4, + TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x5, + TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x6, + TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x7, +} TMDS_CTL3_DATA_SEL; +typedef enum DIG_FE_CNTL_SOURCE_SELECT { + DIG_FE_SOURCE_FROM_FMT0 = 0x0, + DIG_FE_SOURCE_FROM_FMT1 = 0x1, + DIG_FE_SOURCE_FROM_FMT2 = 0x2, + DIG_FE_SOURCE_FROM_FMT3 = 0x3, +} DIG_FE_CNTL_SOURCE_SELECT; +typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT { + DIG_FE_STEREOSYNC_FROM_FMT0 = 0x0, + DIG_FE_STEREOSYNC_FROM_FMT1 = 0x1, + DIG_FE_STEREOSYNC_FROM_FMT2 = 0x2, + DIG_FE_STEREOSYNC_FROM_FMT3 = 0x3, +} DIG_FE_CNTL_STEREOSYNC_SELECT; +typedef enum DIG_FIFO_READ_CLOCK_SRC { + DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x0, + DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x1, +} DIG_FIFO_READ_CLOCK_SRC; +typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL { + DIG_OUTPUT_CRC_ON_LINK0 = 0x0, + DIG_OUTPUT_CRC_ON_LINK1 = 0x1, +} DIG_OUTPUT_CRC_CNTL_LINK_SEL; +typedef enum DIG_OUTPUT_CRC_DATA_SEL { + DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x0, + DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x1, + DIG_OUTPUT_CRC_FOR_VBI = 0x2, + DIG_OUTPUT_CRC_FOR_AUDIO = 0x3, +} DIG_OUTPUT_CRC_DATA_SEL; +typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN { + DIG_IN_NORMAL_OPERATION = 0x0, + DIG_IN_DEBUG_MODE = 0x1, +} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN; +typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL { + DIG_10BIT_TEST_PATTERN = 0x0, + DIG_ALTERNATING_TEST_PATTERN = 0x1, +} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL; +typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN { + DIG_TEST_PATTERN_NORMAL = 0x0, + DIG_TEST_PATTERN_RANDOM = 0x1, +} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN; +typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET { + DIG_RANDOM_PATTERN_ENABLED = 0x0, + DIG_RANDOM_PATTERN_RESETED = 0x1, +} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET; +typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN { + DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x0, + DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x1, +} DIG_TEST_PATTERN_EXTERNAL_RESET_EN; +typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT { + DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x0, + DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x1, +} DIG_RANDOM_PATTERN_SEED_RAN_PAT; +typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL { + DIG_FIFO_USE_OVERWRITE_LEVEL = 0x0, + DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x1, +} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL; +typedef enum DIG_FIFO_ERROR_ACK { + DIG_FIFO_ERROR_ACK_INT = 0x0, + DIG_FIFO_ERROR_NOT_ACK = 0x1, +} DIG_FIFO_ERROR_ACK; +typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE { + DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x0, + DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x1, +} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE; +typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX { + DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x0, + DIG_FIFO_FORCE_RECOMP_MINMAX = 0x1, +} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX; +typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT { + DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK = 0x0, + DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC = 0x1, +} DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT; +typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK { + DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT = 0x0, + DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK = 0x1, +} DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK; +typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK { + DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT = 0x0, + DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK = 0x1, +} DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK; +typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK { + AFMT_INTERRUPT_DISABLE = 0x0, + AFMT_INTERRUPT_ENABLE = 0x1, +} AFMT_INTERRUPT_STATUS_CHG_MASK; +typedef enum HDMI_GC_AVMUTE { + HDMI_GC_AVMUTE_SET = 0x0, + HDMI_GC_AVMUTE_UNSET = 0x1, +} HDMI_GC_AVMUTE; +typedef enum HDMI_DEFAULT_PAHSE { + HDMI_DEFAULT_PHASE_IS_0 = 0x0, + HDMI_DEFAULT_PHASE_IS_1 = 0x1, +} HDMI_DEFAULT_PAHSE; +typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD { + AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0, + AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x1, +} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD; +typedef enum AUDIO_LAYOUT_SELECT { + AUDIO_LAYOUT_0 = 0x0, + AUDIO_LAYOUT_1 = 0x1, +} AUDIO_LAYOUT_SELECT; +typedef enum AFMT_AUDIO_CRC_CONTROL_CONT { + AFMT_AUDIO_CRC_ONESHOT = 0x0, + AFMT_AUDIO_CRC_AUTO_RESTART = 0x1, +} AFMT_AUDIO_CRC_CONTROL_CONT; +typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE { + AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x0, + AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x1, +} AFMT_AUDIO_CRC_CONTROL_SOURCE; +typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL { + AFMT_AUDIO_CRC_CH0_SIG = 0x0, + AFMT_AUDIO_CRC_CH1_SIG = 0x1, + AFMT_AUDIO_CRC_CH2_SIG = 0x2, + AFMT_AUDIO_CRC_CH3_SIG = 0x3, + AFMT_AUDIO_CRC_CH4_SIG = 0x4, + AFMT_AUDIO_CRC_CH5_SIG = 0x5, + AFMT_AUDIO_CRC_CH6_SIG = 0x6, + AFMT_AUDIO_CRC_CH7_SIG = 0x7, + AFMT_AUDIO_CRC_RESERVED = 0x8, + AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x9, +} AFMT_AUDIO_CRC_CONTROL_CH_SEL; +typedef enum AFMT_RAMP_CONTROL0_SIGN { + AFMT_RAMP_SIGNED = 0x0, + AFMT_RAMP_UNSIGNED = 0x1, +} AFMT_RAMP_CONTROL0_SIGN; +typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND { + AFMT_AUDIO_PACKET_SENT_DISABLED = 0x0, + AFMT_AUDIO_PACKET_SENT_ENABLED = 0x1, +} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND; +typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS { + AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0, + AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x1, +} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS; +typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE { + AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x0, + AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x1, +} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE; +typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT { + AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x0, + AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x1, + AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x2, + AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x3, + AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x4, + AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x5, + AFMT_AUDIO_SRC_RESERVED = 0x6, +} AFMT_AUDIO_SRC_CONTROL_SELECT; +typedef enum DIG_BE_CNTL_MODE { + DIG_BE_DP_SST_MODE = 0x0, + DIG_BE_RESERVED1 = 0x1, + DIG_BE_TMDS_DVI_MODE = 0x2, + DIG_BE_TMDS_HDMI_MODE = 0x3, + DIG_BE_SDVO_RESERVED = 0x4, + DIG_BE_DP_MST_MODE = 0x5, + DIG_BE_RESERVED2 = 0x6, + DIG_BE_RESERVED3 = 0x7, +} DIG_BE_CNTL_MODE; +typedef enum DIG_BE_CNTL_HPD_SELECT { + DIG_BE_CNTL_HPD1 = 0x0, + DIG_BE_CNTL_HPD2 = 0x1, + DIG_BE_CNTL_HPD3 = 0x2, + DIG_BE_CNTL_HPD4 = 0x3, + DIG_BE_CNTL_HPD5 = 0x4, + DIG_BE_CNTL_HPD6 = 0x5, +} DIG_BE_CNTL_HPD_SELECT; +typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT { + LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x0, + LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x1, +} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT; +typedef enum TMDS_SYNC_PHASE { + TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x0, + TMDS_SYNC_PHASE_ON_FRAME_START = 0x1, +} TMDS_SYNC_PHASE; +typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL { + TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x0, + TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x1, +} TMDS_DATA_SYNCHRONIZATION_DSINTSEL; +typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK { + TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x0, + TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x1, +} TMDS_TRANSMITTER_ENABLE_HPD_MASK; +typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK { + TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x0, + TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x1, +} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK; +typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK { + TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x0, + TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x1, +} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK; +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK { + TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x0, + TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1, + TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x2, + TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x3, +} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK; +typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA { + TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x0, + TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x1, +} TMDS_TRANSMITTER_CONTROL_IDSCKSELA; +typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB { + TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x0, + TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x1, +} TMDS_TRANSMITTER_CONTROL_IDSCKSELB; +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN { + TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x0, + TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x1, +} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN; +typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK { + TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x0, + TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x1, +} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK; +typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS { + TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x0, + TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x1, +} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS; +typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS { + TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x0, + TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x1, +} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS; +typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN { + TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x0, + TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x1, +} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN; +typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA { + TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x0, + TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x1, +} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA; +typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB { + TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x0, + TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x1, +} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB; +typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA { + TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x0, + TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x1, + TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x2, + TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x3, +} TMDS_REG_TEST_OUTPUTA_CNTLA; +typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB { + TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x0, + TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x1, + TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x2, + TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x3, +} TMDS_REG_TEST_OUTPUTB_CNTLB; +typedef enum DP_LINK_TRAINING_COMPLETE { + DP_LINK_TRAINING_NOT_COMPLETE = 0x0, + DP_LINK_TRAINING_ALREADY_COMPLETE = 0x1, +} DP_LINK_TRAINING_COMPLETE; +typedef enum DP_EMBEDDED_PANEL_MODE { + DP_EXTERNAL_PANEL = 0x0, + DP_EMBEDDED_PANEL = 0x1, +} DP_EMBEDDED_PANEL_MODE; +typedef enum DP_PIXEL_ENCODING { + DP_PIXEL_ENCODING_RGB444 = 0x0, + DP_PIXEL_ENCODING_YCBCR422 = 0x1, + DP_PIXEL_ENCODING_YCBCR444 = 0x2, + DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x3, + DP_PIXEL_ENCODING_Y_ONLY = 0x4, + DP_PIXEL_ENCODING_RESERVED = 0x5, +} DP_PIXEL_ENCODING; +typedef enum DP_DYN_RANGE { + DP_DYN_VESA_RANGE = 0x0, + DP_DYN_CEA_RANGE = 0x1, +} DP_DYN_RANGE; +typedef enum DP_YCBCR_RANGE { + DP_YCBCR_RANGE_BT601_5 = 0x0, + DP_YCBCR_RANGE_BT709_5 = 0x1, +} DP_YCBCR_RANGE; +typedef enum DP_COMPONENT_DEPTH { + DP_COMPONENT_DEPTH_6BPC = 0x0, + DP_COMPONENT_DEPTH_8BPC = 0x1, + DP_COMPONENT_DEPTH_10BPC = 0x2, + DP_COMPONENT_DEPTH_12BPC = 0x3, + DP_COMPONENT_DEPTH_16BPC = 0x4, + DP_COMPONENT_DEPTH_RESERVED = 0x5, +} DP_COMPONENT_DEPTH; +typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE { + MSA_MISC0_OVERRIDE_DISABLE = 0x0, + MSA_MISC0_OVERRIDE_ENABLE = 0x1, +} DP_MSA_MISC0_OVERRIDE_ENABLE; +typedef enum DP_UDI_LANES { + DP_UDI_1_LANE = 0x0, + DP_UDI_2_LANES = 0x1, + DP_UDI_LANES_RESERVED = 0x2, + DP_UDI_4_LANES = 0x3, +} DP_UDI_LANES; +typedef enum DP_VID_STREAM_DIS_DEFER { + DP_VID_STREAM_DIS_NO_DEFER = 0x0, + DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x1, + DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x2, +} DP_VID_STREAM_DIS_DEFER; +typedef enum DP_STEER_OVERFLOW_ACK { + DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x0, + DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x1, +} DP_STEER_OVERFLOW_ACK; +typedef enum DP_STEER_OVERFLOW_MASK { + DP_STEER_OVERFLOW_MASKED = 0x0, + DP_STEER_OVERFLOW_UNMASK = 0x1, +} DP_STEER_OVERFLOW_MASK; +typedef enum DP_TU_OVERFLOW_ACK { + DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x0, + DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x1, +} DP_TU_OVERFLOW_ACK; +typedef enum DP_VID_TIMING_MODE { + DP_VID_TIMING_MODE_ASYNC = 0x0, + DP_VID_TIMING_MODE_SYNC = 0x1, +} DP_VID_TIMING_MODE; +typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE { + DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x0, + DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x1, +} DP_VID_M_N_DOUBLE_BUFFER_MODE; +typedef enum DP_VID_M_N_GEN_EN { + DP_VID_M_N_PROGRAMMED_VIA_REG = 0x0, + DP_VID_M_N_CALC_AUTO = 0x1, +} DP_VID_M_N_GEN_EN; +typedef enum DP_VID_ENHANCED_FRAME_MODE { + VID_NORMAL_FRAME_MODE = 0x0, + VID_ENHANCED_MODE = 0x1, +} DP_VID_ENHANCED_FRAME_MODE; +typedef enum DP_VID_MSA_TOP_FIELD_MODE { + DP_TOP_FIELD_ONLY = 0x0, + DP_TOP_PLUS_BOTTOM_FIELD = 0x1, +} DP_VID_MSA_TOP_FIELD_MODE; +typedef enum DP_VID_VBID_FIELD_POL { + DP_VID_VBID_FIELD_POL_NORMAL = 0x0, + DP_VID_VBID_FIELD_POL_INV = 0x1, +} DP_VID_VBID_FIELD_POL; +typedef enum DP_VID_STREAM_DISABLE_ACK { + ID_STREAM_DISABLE_NO_ACK = 0x0, + ID_STREAM_DISABLE_ACKED = 0x1, +} DP_VID_STREAM_DISABLE_ACK; +typedef enum DP_VID_STREAM_DISABLE_MASK { + VID_STREAM_DISABLE_MASKED = 0x0, + VID_STREAM_DISABLE_UNMASK = 0x1, +} DP_VID_STREAM_DISABLE_MASK; +typedef enum DPHY_ATEST_SEL_LANE0 { + DPHY_ATEST_LANE0_PRBS_PATTERN = 0x0, + DPHY_ATEST_LANE0_REG_PATTERN = 0x1, +} DPHY_ATEST_SEL_LANE0; +typedef enum DPHY_ATEST_SEL_LANE1 { + DPHY_ATEST_LANE1_PRBS_PATTERN = 0x0, + DPHY_ATEST_LANE1_REG_PATTERN = 0x1, +} DPHY_ATEST_SEL_LANE1; +typedef enum DPHY_ATEST_SEL_LANE2 { + DPHY_ATEST_LANE2_PRBS_PATTERN = 0x0, + DPHY_ATEST_LANE2_REG_PATTERN = 0x1, +} DPHY_ATEST_SEL_LANE2; +typedef enum DPHY_ATEST_SEL_LANE3 { + DPHY_ATEST_LANE3_PRBS_PATTERN = 0x0, + DPHY_ATEST_LANE3_REG_PATTERN = 0x1, +} DPHY_ATEST_SEL_LANE3; +typedef enum DPHY_BYPASS { + DPHY_8B10B_OUTPUT = 0x0, + DPHY_DBG_OUTPUT = 0x1, +} DPHY_BYPASS; +typedef enum DPHY_SKEW_BYPASS { + DPHY_WITH_SKEW = 0x0, + DPHY_NO_SKEW = 0x1, +} DPHY_SKEW_BYPASS; +typedef enum DPHY_TRAINING_PATTERN_SEL { + DPHY_TRAINING_PATTERN_1 = 0x0, + DPHY_TRAINING_PATTERN_2 = 0x1, + DPHY_TRAINING_PATTERN_3 = 0x2, +} DPHY_TRAINING_PATTERN_SEL; +typedef enum DPHY_8B10B_RESET { + DPHY_8B10B_NOT_RESET = 0x0, + DPHY_8B10B_RESETET = 0x1, +} DPHY_8B10B_RESET; +typedef enum DP_DPHY_8B10B_EXT_DISP { + DP_DPHY_8B10B_EXT_DISP_ZERO = 0x0, + DP_DPHY_8B10B_EXT_DISP_ONE = 0x1, +} DP_DPHY_8B10B_EXT_DISP; +typedef enum DPHY_8B10B_CUR_DISP { + DPHY_8B10B_CUR_DISP_ZERO = 0x0, + DPHY_8B10B_CUR_DISP_ONE = 0x1, +} DPHY_8B10B_CUR_DISP; +typedef enum DPHY_PRBS_EN { + DPHY_PRBS_DISABLE = 0x0, + DPHY_PRBS_ENABLE = 0x1, +} DPHY_PRBS_EN; +typedef enum DPHY_PRBS_SEL { + DPHY_PRBS7_SELECTED = 0x0, + DPHY_PRBS23_SELECTED = 0x1, + DPHY_PRBS11_SELECTED = 0x2, +} DPHY_PRBS_SEL; +typedef enum DPHY_LOAD_BS_COUNT_START { + DPHY_LOAD_BS_COUNT_STARTED = 0x0, + DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x1, +} DPHY_LOAD_BS_COUNT_START; +typedef enum DPHY_CRC_EN { + DPHY_CRC_DISABLED = 0x0, + DPHY_CRC_ENABLED = 0x1, +} DPHY_CRC_EN; +typedef enum DPHY_CRC_CONT_EN { + DPHY_CRC_ONE_SHOT = 0x0, + DPHY_CRC_CONTINUOUS = 0x1, +} DPHY_CRC_CONT_EN; +typedef enum DPHY_CRC_FIELD { + DPHY_CRC_START_FROM_TOP_FIELD = 0x0, + DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x1, +} DPHY_CRC_FIELD; +typedef enum DPHY_CRC_SEL { + DPHY_CRC_LANE0_SELECTED = 0x0, + DPHY_CRC_LANE1_SELECTED = 0x1, + DPHY_CRC_LANE2_SELECTED = 0x2, + DPHY_CRC_LANE3_SELECTED = 0x3, +} DPHY_CRC_SEL; +typedef enum DPHY_RX_FAST_TRAINING_CAPABLE { + DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x0, + DPHY_FAST_TRAINING_CAPABLE = 0x1, +} DPHY_RX_FAST_TRAINING_CAPABLE; +typedef enum DP_SEC_COLLISION_ACK { + DP_SEC_COLLISION_ACK_NO_EFFECT = 0x0, + DP_SEC_COLLISION_ACK_CLR_FLAG = 0x1, +} DP_SEC_COLLISION_ACK; +typedef enum DP_SEC_AUDIO_MUTE { + DP_SEC_AUDIO_MUTE_HW_CTRL = 0x0, + DP_SEC_AUDIO_MUTE_SW_CTRL = 0x1, +} DP_SEC_AUDIO_MUTE; +typedef enum DP_SEC_TIMESTAMP_MODE { + DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x0, + DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x1, +} DP_SEC_TIMESTAMP_MODE; +typedef enum DP_SEC_ASP_PRIORITY { + DP_SEC_ASP_LOW_PRIORITY = 0x0, + DP_SEC_ASP_HIGH_PRIORITY = 0x1, +} DP_SEC_ASP_PRIORITY; +typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE { + DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x0, + DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x1, +} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE; +typedef enum DP_MSE_SAT_UPDATE_ACT { + DP_MSE_SAT_UPDATE_NO_ACTION = 0x0, + DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x1, + DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x2, +} DP_MSE_SAT_UPDATE_ACT; +typedef enum DP_MSE_LINK_LINE { + DP_MSE_LINK_LINE_32_MTP_LONG = 0x0, + DP_MSE_LINK_LINE_64_MTP_LONG = 0x1, + DP_MSE_LINK_LINE_128_MTP_LONG = 0x2, + DP_MSE_LINK_LINE_256_MTP_LONG = 0x3, +} DP_MSE_LINK_LINE; +typedef enum DP_MSE_BLANK_CODE { + DP_MSE_BLANK_CODE_SF_FILLED = 0x0, + DP_MSE_BLANK_CODE_ZERO_FILLED = 0x1, +} DP_MSE_BLANK_CODE; +typedef enum DP_MSE_TIMESTAMP_MODE { + DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x0, + DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x1, +} DP_MSE_TIMESTAMP_MODE; +typedef enum DP_MSE_ZERO_ENCODER { + DP_MSE_NOT_ZERO_FE_ENCODER = 0x0, + DP_MSE_ZERO_FE_ENCODER = 0x1, +} DP_MSE_ZERO_ENCODER; +typedef enum DP_MSE_OUTPUT_DPDBG_DATA { + DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x0, + DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x1, +} DP_MSE_OUTPUT_DPDBG_DATA; +typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE { + DP_DPHY_HBR2_PASS_THROUGH = 0x0, + DP_DPHY_HBR2_PATTERN_1 = 0x1, + DP_DPHY_HBR2_PATTERN_2_NEG = 0x2, + DP_DPHY_HBR2_PATTERN_3 = 0x3, + DP_DPHY_HBR2_PATTERN_2_POS = 0x6, +} DP_DPHY_HBR2_PATTERN_CONTROL_MODE; +typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK { + DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x0, + DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x1, +} DPHY_CRC_MST_PHASE_ERROR_ACK; +typedef enum DPHY_SW_FAST_TRAINING_START { + DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x0, + DPHY_SW_FAST_TRAINING_STARTED = 0x1, +} DPHY_SW_FAST_TRAINING_START; +typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN { + DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0, + DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1, +} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN; +typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK { + DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x0, + DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x1, +} DP_DPHY_FAST_TRAINING_COMPLETE_MASK; +typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK { + DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x0, + DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x1, +} DP_DPHY_FAST_TRAINING_COMPLETE_ACK; +typedef enum DP_MSA_V_TIMING_OVERRIDE_EN { + MSA_V_TIMING_OVERRIDE_DISABLED = 0x0, + MSA_V_TIMING_OVERRIDE_ENABLED = 0x1, +} DP_MSA_V_TIMING_OVERRIDE_EN; +typedef enum DP_SEC_GSP0_PRIORITY { + SEC_GSP0_PRIORITY_LOW = 0x0, + SEC_GSP0_PRIORITY_HIGH = 0x1, +} DP_SEC_GSP0_PRIORITY; +typedef enum DP_SEC_GSP0_SEND { + NOT_SENT = 0x0, + FORCE_SENT = 0x1, +} DP_SEC_GSP0_SEND; +typedef enum DP_AUX_CONTROL_HPD_SEL { + DP_AUX_CONTROL_HPD1_SELECTED = 0x0, + DP_AUX_CONTROL_HPD2_SELECTED = 0x1, + DP_AUX_CONTROL_HPD3_SELECTED = 0x2, + DP_AUX_CONTROL_HPD4_SELECTED = 0x3, + DP_AUX_CONTROL_HPD5_SELECTED = 0x4, + DP_AUX_CONTROL_HPD6_SELECTED = 0x5, +} DP_AUX_CONTROL_HPD_SEL; +typedef enum DP_AUX_CONTROL_TEST_MODE { + DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x0, + DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x1, +} DP_AUX_CONTROL_TEST_MODE; +typedef enum DP_AUX_SW_CONTROL_SW_GO { + DP_AUX_SW_CONTROL_SW__NOT_GO = 0x0, + DP_AUX_SW_CONTROL_SW__GO = 0x1, +} DP_AUX_SW_CONTROL_SW_GO; +typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG { + DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x0, + DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x1, +} DP_AUX_SW_CONTROL_LS_READ_TRIG; +typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY { + DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x0, + DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x1, + DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x2, + DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x3, +} DP_AUX_ARB_CONTROL_ARB_PRIORITY; +typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ { + DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x0, + DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x1, +} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ; +typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG { + DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x0, + DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x1, +} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG; +typedef enum DP_AUX_INT_ACK { + DP_AUX_INT__NOT_ACK = 0x0, + DP_AUX_INT__ACK = 0x1, +} DP_AUX_INT_ACK; +typedef enum DP_AUX_LS_UPDATE_ACK { + DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x0, + DP_AUX_INT_LS_UPDATE_ACK = 0x1, +} DP_AUX_LS_UPDATE_ACK; +typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL { + DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0, + DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1, +} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL; +typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE { + DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x0, + DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x1, + DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x2, + DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x3, +} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE; +typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN { + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x0, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x1, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x2, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x3, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x4, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x5, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x6, + DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x7, +} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN; +typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY { + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x0, + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1, + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2, + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3, + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4, + DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5, +} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY; +typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW { + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6, + DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7, +} DP_AUX_DPHY_RX_CONTROL_START_WINDOW; +typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW { + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6, + DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7, +} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW; +typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN { + DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0, + DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1, + DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2, + DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3, +} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN; +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT { + DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0, + DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START { + DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0, + DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START; +typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP { + DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0, + DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1, +} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP; +typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN { + DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0, + DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1, + DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2, + DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3, +} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN; +typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN { + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x0, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x1, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x2, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x3, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x4, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x5, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x6, + DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x7, +} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN; +typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD { + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x0, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x1, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x2, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x3, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x4, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x5, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x6, + DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x7, +} DP_AUX_DPHY_RX_DETECTION_THRESHOLD; +typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ { + DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0, + DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1, +} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ; +typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW { + DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0, + DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1, + DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2, + DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3, +} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW; +typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT { + DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0, + DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1, + DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2, + DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3, +} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT; +typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN { + DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0= 0x0, + DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64= 0x1, + DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2, + DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256= 0x3, +} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN; +typedef enum DP_AUX_ERR_OCCURRED_ACK { + DP_AUX_ERR_OCCURRED__NOT_ACK = 0x0, + DP_AUX_ERR_OCCURRED__ACK = 0x1, +} DP_AUX_ERR_OCCURRED_ACK; +typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK { + DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x0, + DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x1, +} DP_AUX_POTENTIAL_ERR_REACHED_ACK; +typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK { + ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x0, + ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x1, +} DP_AUX_DEFINITE_ERR_REACHED_ACK; +typedef enum DP_AUX_RESET { + DP_AUX_RESET_DEASSERTED = 0x0, + DP_AUX_RESET_ASSERTED = 0x1, +} DP_AUX_RESET; +typedef enum DP_AUX_RESET_DONE { + DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x0, + DP_AUX_RESET_SEQUENCE_DONE = 0x1, +} DP_AUX_RESET_DONE; +typedef enum FMT_CONTROL_PIXEL_ENCODING { + FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x0, + FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x1, +} FMT_CONTROL_PIXEL_ENCODING; +typedef enum FMT_CONTROL_SUBSAMPLING_MODE { + FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x0, + FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x1, +} FMT_CONTROL_SUBSAMPLING_MODE; +typedef enum FMT_CONTROL_SUBSAMPLING_ORDER { + FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x0, + FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x1, +} FMT_CONTROL_SUBSAMPLING_ORDER; +typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE { + FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x0, + FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x1, +} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; +typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH { + FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x0, + FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x1, + FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x2, +} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; +typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH { + FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x0, + FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x1, + FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2, +} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; +typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH { + FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP= 0x0, + FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP= 0x1, + FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2, +} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; +typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL { + FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x0, + FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x1, +} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; +typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL { + FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x0, + FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x1, + FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x2, + FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x3, +} FMT_BIT_DEPTH_CONTROL_25FRC_SEL; +typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL { + FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x0, + FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x1, + FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x2, + FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x3, +} FMT_BIT_DEPTH_CONTROL_50FRC_SEL; +typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL { + FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x0, + FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x1, + FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x2, + FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x3, +} FMT_BIT_DEPTH_CONTROL_75FRC_SEL; +typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT { + FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN= 0x0, + FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN= 0x1, +} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT; +typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 { + FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR= 0x0, + FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB= 0x1, +} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; +typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT { + FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x0, + FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x1, + FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x2, + FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED0 = 0x3, + FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x4, + FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x5, + FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x6, + FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x7, +} FMT_CLAMP_CNTL_COLOR_FORMAT; +typedef enum FMT_CRC_CNTL_CONT_EN { + FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x0, + FMT_CRC_CNTL_CONT_EN_CONT = 0x1, +} FMT_CRC_CNTL_CONT_EN; +typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN { + FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x0, + FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x1, +} FMT_CRC_CNTL_INCLUDE_OVERSCAN; +typedef enum FMT_CRC_CNTL_ONLY_BLANKB { + FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x0, + FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x1, +} FMT_CRC_CNTL_ONLY_BLANKB; +typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE { + FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x0, + FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x1, +} FMT_CRC_CNTL_PSR_MODE_ENABLE; +typedef enum FMT_CRC_CNTL_INTERLACE_MODE { + FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x0, + FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x1, + FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x2, + FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x3, +} FMT_CRC_CNTL_INTERLACE_MODE; +typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE { + FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x0, + FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x1, +} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE; +typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT { + FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x0, + FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x1, +} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT; +typedef enum FMT_DEBUG_CNTL_COLOR_SELECT { + FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x0, + FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x1, + FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x2, + FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x3, +} FMT_DEBUG_CNTL_COLOR_SELECT; +typedef enum FMT_SPATIAL_DITHER_MODE { + FMT_SPATIAL_DITHER_MODE_0 = 0x0, + FMT_SPATIAL_DITHER_MODE_1 = 0x1, + FMT_SPATIAL_DITHER_MODE_2 = 0x2, + FMT_SPATIAL_DITHER_MODE_3 = 0x3, +} FMT_SPATIAL_DITHER_MODE; +typedef enum FMT_STEREOSYNC_OVR_POL { + FMT_STEREOSYNC_OVR_POL_INVERTED = 0x0, + FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x1, +} FMT_STEREOSYNC_OVR_POL; +typedef enum FMT_DYNAMIC_EXP_MODE { + FMT_DYNAMIC_EXP_MODE_10to12 = 0x0, + FMT_DYNAMIC_EXP_MODE_8to12 = 0x1, +} FMT_DYNAMIC_EXP_MODE; +typedef enum LB_DATA_FORMAT_PIXEL_DEPTH { + LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x0, + LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x1, + LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x2, + LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x3, +} LB_DATA_FORMAT_PIXEL_DEPTH; +typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE { + LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION= 0x0, + LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION= 0x1, +} LB_DATA_FORMAT_PIXEL_EXPAN_MODE; +typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE { + LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x0, + LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x1, +} LB_DATA_FORMAT_PIXEL_REDUCE_MODE; +typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH { + LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x0, + LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x1, +} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH; +typedef enum LB_DATA_FORMAT_INTERLEAVE_EN { + LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x0, + LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x1, +} LB_DATA_FORMAT_INTERLEAVE_EN; +typedef enum LB_DATA_FORMAT_REQUEST_MODE { + LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x0, + LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x1, +} LB_DATA_FORMAT_REQUEST_MODE; +typedef enum LB_DATA_FORMAT_ALPHA_EN { + LB_DATA_FORMAT_ALPHA_DISABLE = 0x0, + LB_DATA_FORMAT_ALPHA_ENABLE = 0x1, +} LB_DATA_FORMAT_ALPHA_EN; +typedef enum LB_VLINE_START_END_VLINE_INV { + LB_VLINE_START_END_VLINE_NORMAL = 0x0, + LB_VLINE_START_END_VLINE_INVERSE = 0x1, +} LB_VLINE_START_END_VLINE_INV; +typedef enum LB_VLINE2_START_END_VLINE2_INV { + LB_VLINE2_START_END_VLINE2_NORMAL = 0x0, + LB_VLINE2_START_END_VLINE2_INVERSE = 0x1, +} LB_VLINE2_START_END_VLINE2_INV; +typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK { + LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x0, + LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x1, +} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK; +typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK { + LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x0, + LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x1, +} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK; +typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK { + LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x0, + LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x1, +} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK; +typedef enum LB_VLINE_STATUS_VLINE_ACK { + LB_VLINE_STATUS_VLINE_NORMAL = 0x0, + LB_VLINE_STATUS_VLINE_CLEAR = 0x1, +} LB_VLINE_STATUS_VLINE_ACK; +typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE { + LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x0, + LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x1, +} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE; +typedef enum LB_VLINE2_STATUS_VLINE2_ACK { + LB_VLINE2_STATUS_VLINE2_NORMAL = 0x0, + LB_VLINE2_STATUS_VLINE2_CLEAR = 0x1, +} LB_VLINE2_STATUS_VLINE2_ACK; +typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE { + LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED= 0x0, + LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED= 0x1, +} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE; +typedef enum LB_VBLANK_STATUS_VBLANK_ACK { + LB_VBLANK_STATUS_VBLANK_NORMAL = 0x0, + LB_VBLANK_STATUS_VBLANK_CLEAR = 0x1, +} LB_VBLANK_STATUS_VBLANK_ACK; +typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE { + LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED= 0x0, + LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED= 0x1, +} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE; +typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL { + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x0, + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK= 0x1, + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2, + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET= 0x3, +} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL; +typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 { + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x0, + LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x1, +} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2; +typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION { + LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x0, + LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x1, + LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x2, + LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x3, +} LB_SYNC_RESET_SEL_LB_SYNC_DURATION; +typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN { + LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x0, + LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x1, +} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN; +typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN { + LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE= 0x0, + LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE= 0x1, +} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN; +typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK { + LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x0, + LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x1, +} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK; +typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK { + LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x0, + LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x1, +} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK; +typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE { + LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2, + LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP= 0x3, +} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE; +typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET { + LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL= 0x0, + LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE= 0x1, +} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET; +typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK { + LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0= 0x0, + LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1= 0x1, +} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK; +typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE { + LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT= 0x0, + LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG= 0x1, + LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2, +} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE; +typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE { + LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE= 0x0, + LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x1, +} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE; +typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE { + ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER= 0x1, + ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2, +} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE; +typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL { + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0= 0x0, + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1= 0x1, +} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL; +typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE { + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE= 0x0, + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE= 0x1, +} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE; +typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO { + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO= 0x0, + LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO= 0x1, +} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO; +typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN { + LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0= 0x0, + LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1= 0x1, +} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN; +typedef enum LBV_PIXEL_DEPTH { + PIXEL_DEPTH_30BPP = 0x0, + PIXEL_DEPTH_24BPP = 0x1, + PIXEL_DEPTH_18BPP = 0x2, + PIXEL_DEPTH_38BPP = 0x3, +} LBV_PIXEL_DEPTH; +typedef enum LBV_PIXEL_EXPAN_MODE { + PIXEL_EXPAN_MODE_ZERO_EXP = 0x0, + PIXEL_EXPAN_MODE_DYN_EXP = 0x1, +} LBV_PIXEL_EXPAN_MODE; +typedef enum LBV_INTERLEAVE_EN { + INTERLEAVE_DIS = 0x0, + INTERLEAVE_EN = 0x1, +} LBV_INTERLEAVE_EN; +typedef enum LBV_PIXEL_REDUCE_MODE { + PIXEL_REDUCE_MODE_TRUNCATION = 0x0, + PIXEL_REDUCE_MODE_ROUNDING = 0x1, +} LBV_PIXEL_REDUCE_MODE; +typedef enum LBV_DYNAMIC_PIXEL_DEPTH { + DYNAMIC_PIXEL_DEPTH_36BPP = 0x0, + DYNAMIC_PIXEL_DEPTH_30BPP = 0x1, +} LBV_DYNAMIC_PIXEL_DEPTH; +typedef enum LBV_DITHER_EN { + DITHER_DIS = 0x0, + DITHER_EN = 0x1, +} LBV_DITHER_EN; +typedef enum LBV_DOWNSCALE_PREFETCH_EN { + DOWNSCALE_PREFETCH_DIS = 0x0, + DOWNSCALE_PREFETCH_EN = 0x1, +} LBV_DOWNSCALE_PREFETCH_EN; +typedef enum LBV_MEMORY_CONFIG { + MEMORY_CONFIG_0 = 0x0, + MEMORY_CONFIG_1 = 0x1, + MEMORY_CONFIG_2 = 0x2, + MEMORY_CONFIG_3 = 0x3, +} LBV_MEMORY_CONFIG; +typedef enum LBV_SYNC_RESET_SEL2 { + SYNC_RESET_SEL2_VBLANK = 0x0, + SYNC_RESET_SEL2_VSYNC = 0x1, +} LBV_SYNC_RESET_SEL2; +typedef enum LBV_SYNC_DURATION { + SYNC_DURATION_16 = 0x0, + SYNC_DURATION_32 = 0x1, + SYNC_DURATION_64 = 0x2, + SYNC_DURATION_128 = 0x3, +} LBV_SYNC_DURATION; +typedef enum SCL_C_RAM_TAP_PAIR_IDX { + SCL_C_RAM_TAP_PAIR_ID0 = 0x0, + SCL_C_RAM_TAP_PAIR_ID1 = 0x1, + SCL_C_RAM_TAP_PAIR_ID2 = 0x2, + SCL_C_RAM_TAP_PAIR_ID3 = 0x3, + SCL_C_RAM_TAP_PAIR_ID4 = 0x4, +} SCL_C_RAM_TAP_PAIR_IDX; +typedef enum SCL_C_RAM_PHASE { + SCL_C_RAM_PHASE_0 = 0x0, + SCL_C_RAM_PHASE_1 = 0x1, + SCL_C_RAM_PHASE_2 = 0x2, + SCL_C_RAM_PHASE_3 = 0x3, + SCL_C_RAM_PHASE_4 = 0x4, + SCL_C_RAM_PHASE_5 = 0x5, + SCL_C_RAM_PHASE_6 = 0x6, + SCL_C_RAM_PHASE_7 = 0x7, + SCL_C_RAM_PHASE_8 = 0x8, +} SCL_C_RAM_PHASE; +typedef enum SCL_C_RAM_FILTER_TYPE { + SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x0, + SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x1, + SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x2, + SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x3, + SCL_C_RAM_FILTER_TYPE_VERT_ALPHA_LUT = 0x4, + SCL_C_RAM_FILTER_TYPE_HORI_ALPHA_LUT = 0x5, +} SCL_C_RAM_FILTER_TYPE; +typedef enum SCL_MODE_SEL { + SCL_MODE_SCL_BYPASS = 0x0, + SCL_MODE_RGB_SCALING = 0x1, + SCL_MODE_YCBCR_SCALING = 0x2, +} SCL_MODE_SEL; +typedef enum SCL_PSCL_EN { + SCL_PSCL_DISABLE = 0x0, + SCL_PSCL_ENANBLE = 0x1, +} SCL_PSCL_EN; +typedef enum SCL_V_NUM_OF_TAPS { + SCL_V_NUM_OF_TAPS_1 = 0x0, + SCL_V_NUM_OF_TAPS_2 = 0x1, + SCL_V_NUM_OF_TAPS_3 = 0x2, + SCL_V_NUM_OF_TAPS_4 = 0x3, + SCL_V_NUM_OF_TAPS_5 = 0x4, + SCL_V_NUM_OF_TAPS_6 = 0x5, +} SCL_V_NUM_OF_TAPS; +typedef enum SCL_H_NUM_OF_TAPS { + SCL_H_NUM_OF_TAPS_1 = 0x0, + SCL_H_NUM_OF_TAPS_2 = 0x1, + SCL_H_NUM_OF_TAPS_4 = 0x3, + SCL_H_NUM_OF_TAPS_6 = 0x5, + SCL_H_NUM_OF_TAPS_8 = 0x7, + SCL_H_NUM_OF_TAPS_10 = 0x9, +} SCL_H_NUM_OF_TAPS; +typedef enum SCL_BOUNDARY_MODE { + SCL_BOUNDARY_MODE_BLACK = 0x0, + SCL_BOUNDARY_MODE_EDGE = 0x1, +} SCL_BOUNDARY_MODE; +typedef enum SCL_EARLY_EOL_MOD { + SCL_EARLY_EOL_MODE_CRTC = 0x0, + SCL_EARLY_EOL_MODE_INTERNAL = 0x1, +} SCL_EARLY_EOL_MOD; +typedef enum SCL_BYPASS_MODE { + SCL_BYPASS_MODE_MC_MR = 0x0, + SCL_BYPASS_MODE_AC_NR = 0x1, + SCL_BYPASS_MODE_AC_AR = 0x2, + SCL_BYPASS_MODE_RESERVED = 0x3, +} SCL_BYPASS_MODE; +typedef enum SCL_V_MANUAL_REPLICATE_FACTOR { + SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x0, + SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x1, + SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x2, + SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x3, + SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x4, + SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x5, + SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x6, + SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x7, + SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x8, + SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x9, + SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0xa, + SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0xb, + SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0xc, + SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0xd, + SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0xe, + SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0xf, +} SCL_V_MANUAL_REPLICATE_FACTOR; +typedef enum SCL_H_MANUAL_REPLICATE_FACTOR { + SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x0, + SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x1, + SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x2, + SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x3, + SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x4, + SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x5, + SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x6, + SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x7, + SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x8, + SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x9, + SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0xa, + SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0xb, + SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0xc, + SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0xd, + SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0xe, + SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0xf, +} SCL_H_MANUAL_REPLICATE_FACTOR; +typedef enum SCL_V_CALC_AUTO_RATIO_EN { + SCL_V_CALC_AUTO_RATIO_DISABLE = 0x0, + SCL_V_CALC_AUTO_RATIO_ENABLE = 0x1, +} SCL_V_CALC_AUTO_RATIO_EN; +typedef enum SCL_H_CALC_AUTO_RATIO_EN { + SCL_H_CALC_AUTO_RATIO_DISABLE = 0x0, + SCL_H_CALC_AUTO_RATIO_ENABLE = 0x1, +} SCL_H_CALC_AUTO_RATIO_EN; +typedef enum SCL_H_FILTER_PICK_NEAREST { + SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x0, + SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x1, +} SCL_H_FILTER_PICK_NEAREST; +typedef enum SCL_H_2TAP_HARDCODE_COEF_EN { + SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x0, + SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x1, +} SCL_H_2TAP_HARDCODE_COEF_EN; +typedef enum SCL_V_FILTER_PICK_NEAREST { + SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x0, + SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x1, +} SCL_V_FILTER_PICK_NEAREST; +typedef enum SCL_V_2TAP_HARDCODE_COEF_EN { + SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x0, + SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x1, +} SCL_V_2TAP_HARDCODE_COEF_EN; +typedef enum SCL_UPDATE_TAKEN { + SCL_UPDATE_TAKEN_NO = 0x0, + SCL_UPDATE_TAKEN_YES = 0x1, +} SCL_UPDATE_TAKEN; +typedef enum SCL_UPDATE_LOCK { + SCL_UPDATE_UNLOCKED = 0x0, + SCL_UPDATE_LOCKED = 0x1, +} SCL_UPDATE_LOCK; +typedef enum SCL_COEF_UPDATE_COMPLETE { + SCL_COEF_UPDATE_NOT_COMPLETED = 0x0, + SCL_COEF_UPDATE_COMPLETED = 0x1, +} SCL_COEF_UPDATE_COMPLETE; +typedef enum SCL_HF_SHARP_SCALE_FACTOR { + SCL_HF_SHARP_SCALE_FACTOR_0 = 0x0, + SCL_HF_SHARP_SCALE_FACTOR_1 = 0x1, + SCL_HF_SHARP_SCALE_FACTOR_2 = 0x2, + SCL_HF_SHARP_SCALE_FACTOR_3 = 0x3, + SCL_HF_SHARP_SCALE_FACTOR_4 = 0x4, + SCL_HF_SHARP_SCALE_FACTOR_5 = 0x5, + SCL_HF_SHARP_SCALE_FACTOR_6 = 0x6, + SCL_HF_SHARP_SCALE_FACTOR_7 = 0x7, +} SCL_HF_SHARP_SCALE_FACTOR; +typedef enum SCL_HF_SHARP_EN { + SCL_HF_SHARP_DISABLE = 0x0, + SCL_HF_SHARP_ENABLE = 0x1, +} SCL_HF_SHARP_EN; +typedef enum SCL_VF_SHARP_SCALE_FACTOR { + SCL_VF_SHARP_SCALE_FACTOR_0 = 0x0, + SCL_VF_SHARP_SCALE_FACTOR_1 = 0x1, + SCL_VF_SHARP_SCALE_FACTOR_2 = 0x2, + SCL_VF_SHARP_SCALE_FACTOR_3 = 0x3, + SCL_VF_SHARP_SCALE_FACTOR_4 = 0x4, + SCL_VF_SHARP_SCALE_FACTOR_5 = 0x5, + SCL_VF_SHARP_SCALE_FACTOR_6 = 0x6, + SCL_VF_SHARP_SCALE_FACTOR_7 = 0x7, +} SCL_VF_SHARP_SCALE_FACTOR; +typedef enum SCL_VF_SHARP_EN { + SCL_VF_SHARP_DISABLE = 0x0, + SCL_VF_SHARP_ENABLE = 0x1, +} SCL_VF_SHARP_EN; +typedef enum SCL_ALU_DISABLE { + SCL_ALU_ENABLED = 0x0, + SCL_ALU_DISABLED = 0x1, +} SCL_ALU_DISABLE; +typedef enum SCL_HOST_CONFLICT_MASK { + SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x0, + SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x1, +} SCL_HOST_CONFLICT_MASK; +typedef enum SCL_SCL_MODE_CHANGE_MASK { + SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x0, + SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x1, +} SCL_SCL_MODE_CHANGE_MASK; +typedef enum SCLV_INTERLACE_SOURCE { + INTERLACE_SOURCE_PROGRESSIVE = 0x0, + INTERLACE_SOURCE_INTERLEAVE = 0x1, + INTERLACE_SOURCE_STACK = 0x2, +} SCLV_INTERLACE_SOURCE; +typedef enum SCLV_UPDATE_LOCK { + UPDATE_UNLOCKED = 0x0, + UPDATE_LOCKED = 0x1, +} SCLV_UPDATE_LOCK; +typedef enum SCLV_COEF_UPDATE_COMPLETE { + COEF_UPDATE_NOT_COMPLETE = 0x0, + COEF_UPDATE_COMPLETE = 0x1, +} SCLV_COEF_UPDATE_COMPLETE; +typedef enum COL_MAN_UPDATE_LOCK { + COL_MAN_UPDATE_UNLOCKED = 0x0, + COL_MAN_UPDATE_LOCKED = 0x1, +} COL_MAN_UPDATE_LOCK; +typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE { + COL_MAN_MULTIPLE_UPDATE = 0x0, + COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x1, +} COL_MAN_DISABLE_MULTIPLE_UPDATE; +typedef enum COL_MAN_INPUTCSC_MODE { + INPUTCSC_MODE_BYPASS = 0x0, + INPUTCSC_MODE_A = 0x1, + INPUTCSC_MODE_B = 0x2, + INPUTCSC_MODE_UNITY = 0x3, +} COL_MAN_INPUTCSC_MODE; +typedef enum COL_MAN_INPUTCSC_TYPE { + INPUTCSC_TYPE_12_0 = 0x0, + INPUTCSC_TYPE_10_2 = 0x1, + INPUTCSC_TYPE_8_4 = 0x2, +} COL_MAN_INPUTCSC_TYPE; +typedef enum COL_MAN_INPUTCSC_CONVERT { + INPUTCSC_ROUND = 0x0, + INPUTCSC_TRUNCATE = 0x1, +} COL_MAN_INPUTCSC_CONVERT; +typedef enum COL_MAN_PRESCALE_MODE { + PRESCALE_MODE_BYPASS = 0x0, + PRESCALE_MODE_PROGRAM = 0x1, + PRESCALE_MODE_UNITY = 0x2, +} COL_MAN_PRESCALE_MODE; +typedef enum COL_MAN_INPUT_GAMMA_MODE { + INGAMMA_MODE_BYPASS = 0x0, + INGAMMA_MODE_FIX = 0x1, + INGAMMA_MODE_FLOAT = 0x2, +} COL_MAN_INPUT_GAMMA_MODE; +typedef enum COL_MAN_OUTPUT_CSC_MODE { + COL_MAN_OUTPUT_CSC_BYPASS = 0x0, + COL_MAN_OUTPUT_CSC_RGB = 0x1, + COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2, + COL_MAN_OUTPUT_CSC_YCrCb709 = 0x3, + COL_MAN_OUTPUT_CSC_A = 0x4, + COL_MAN_OUTPUT_CSC_B = 0x5, + COL_MAN_OUTPUT_CSC_UNITY = 0x6, +} COL_MAN_OUTPUT_CSC_MODE; +typedef enum COL_MAN_DENORM_CLAMP_CONTROL { + DENORM_CLAMP_MODE_UNITY = 0x0, + DENORM_CLAMP_MODE_8 = 0x1, + DENORM_CLAMP_MODE_10 = 0x2, + DENORM_CLAMP_MODE_12 = 0x3, +} COL_MAN_DENORM_CLAMP_CONTROL; +typedef enum COL_MAN_GAMMA_CORR_CONTROL { + GAMMA_CORR_MODE_BYPASS = 0x0, + GAMMA_CORR_MODE_A = 0x1, + GAMMA_CORR_MODE_B = 0x2, +} COL_MAN_GAMMA_CORR_CONTROL; +typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE { + CM_GLOBAL_PASSTHROUGH_DISBALE = 0x0, + CM_GLOBAL_PASSTHROUGH_ENABLE = 0x1, +} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE; +typedef enum UNP_GRPH_EN { + UNP_GRPH_DISABLED = 0x0, + UNP_GRPH_ENABLED = 0x1, +} UNP_GRPH_EN; +typedef enum UNP_GRPH_DEPTH { + UNP_GRPH_8BPP = 0x0, + UNP_GRPH_16BPP = 0x1, + UNP_GRPH_32BPP = 0x2, +} UNP_GRPH_DEPTH; +typedef enum UNP_GRPH_NUM_BANKS { + UNP_GRPH_ADDR_SURF_2_BANK = 0x0, + UNP_GRPH_ADDR_SURF_4_BANK = 0x1, + UNP_GRPH_ADDR_SURF_8_BANK = 0x2, + UNP_GRPH_ADDR_SURF_16_BANK = 0x3, +} UNP_GRPH_NUM_BANKS; +typedef enum UNP_GRPH_BANK_WIDTH { + UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x0, + UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x1, + UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x2, + UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x3, +} UNP_GRPH_BANK_WIDTH; +typedef enum UNP_GRPH_BANK_HEIGHT { + UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x0, + UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x1, + UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x2, + UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} UNP_GRPH_BANK_HEIGHT; +typedef enum UNP_GRPH_TILE_SPLIT { + UNP_ADDR_SURF_TILE_SPLIT_64B = 0x0, + UNP_ADDR_SURF_TILE_SPLIT_128B = 0x1, + UNP_ADDR_SURF_TILE_SPLIT_256B = 0x2, + UNP_ADDR_SURF_TILE_SPLIT_512B = 0x3, + UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x4, + UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x5, + UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} UNP_GRPH_TILE_SPLIT; +typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE { + UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x0, + UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x1, +} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE; +typedef enum UNP_GRPH_PRIVILEGED_ACCESS_ENABLE { + UNP_GRPH_PRIVILEGED_ACCESS_DIS = 0x0, + UNP_GRPH_PRIVILEGED_ACCESS_EN = 0x1, +} UNP_GRPH_PRIVILEGED_ACCESS_ENABLE; +typedef enum UNP_GRPH_MACRO_TILE_ASPECT { + UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x0, + UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x1, + UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x2, + UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} UNP_GRPH_MACRO_TILE_ASPECT; +typedef enum UNP_GRPH_COLOR_EXPANSION_MODE { + UNP_GRPH_DYNAMIC_EXPANSION = 0x0, + UNP_GRPH_ZERO_EXPANSION = 0x1, +} UNP_GRPH_COLOR_EXPANSION_MODE; +typedef enum UNP_VIDEO_FORMAT { + UNP_VIDEO_FORMAT0 = 0x0, + UNP_VIDEO_FORMAT1 = 0x1, + UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x2, + UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x3, + UNP_VIDEO_FORMAT_YUV422_YCb = 0x4, + UNP_VIDEO_FORMAT_YUV422_YCr = 0x5, + UNP_VIDEO_FORMAT_YUV422_CbY = 0x6, + UNP_VIDEO_FORMAT_YUV422_CrY = 0x7, +} UNP_VIDEO_FORMAT; +typedef enum UNP_GRPH_ENDIAN_SWAP { + UNP_GRPH_ENDIAN_SWAP_NONE = 0x0, + UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x1, + UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x2, + UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x3, +} UNP_GRPH_ENDIAN_SWAP; +typedef enum UNP_GRPH_RED_CROSSBAR { + UNP_GRPH_RED_CROSSBAR_R_Cr = 0x0, + UNP_GRPH_RED_CROSSBAR_G_Y = 0x1, + UNP_GRPH_RED_CROSSBAR_B_Cb = 0x2, + UNP_GRPH_RED_CROSSBAR_A = 0x3, +} UNP_GRPH_RED_CROSSBAR; +typedef enum UNP_GRPH_GREEN_CROSSBAR { + UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x0, + UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x1, + UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x2, + UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x3, +} UNP_GRPH_GREEN_CROSSBAR; +typedef enum UNP_GRPH_BLUE_CROSSBAR { + UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x0, + UNP_GRPH_BLUE_CROSSBAR_A = 0x1, + UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x2, + UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x3, +} UNP_GRPH_BLUE_CROSSBAR; +typedef enum UNP_GRPH_MODE_UPDATE_LOCKG { + UNP_GRPH_UPDATE_LOCK_0 = 0x0, + UNP_GRPH_UPDATE_LOCK_1 = 0x1, +} UNP_GRPH_MODE_UPDATE_LOCKG; +typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK { + UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x0, + UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x1, +} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; +typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE { + UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x0, + UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x1, +} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; +typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE { + UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x0, + UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x1, +} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; +typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN { + UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x0, + UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x1, +} UNP_GRPH_STEREOSYNC_FLIP_EN; +typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE { + UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x0, + UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x1, + UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x2, + UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x3, +} UNP_GRPH_STEREOSYNC_FLIP_MODE; +typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN { + UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x0, + UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x1, +} UNP_GRPH_STACK_INTERLACE_FLIP_EN; +typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE { + UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x0, + UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x1, + UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x2, + UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x3, +} UNP_GRPH_STACK_INTERLACE_FLIP_MODE; +typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE { + UNP_GRPH_STEREOSYNC_SELECT_EN = 0x0, + UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x1, +} UNP_GRPH_STEREOSYNC_SELECT_DISABLE; +typedef enum UNP_CRC_SOURCE_SEL { + UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x0, + UNP_CRC_SOURCE_SEL_LOWER32 = 0x1, + UNP_CRC_SOURCE_SEL_RESERVED = 0x2, + UNP_CRC_SOURCE_SEL_LOWER16 = 0x3, + UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x4, +} UNP_CRC_SOURCE_SEL; +typedef enum UNP_CRC_LINE_SEL { + UNP_CRC_LINE_SEL_RESERVED = 0x0, + UNP_CRC_LINE_SEL_EVEN_ONLY = 0x1, + UNP_CRC_LINE_SEL_ODD_ONLY = 0x2, + UNP_CRC_LINE_SEL_ODD_EVEN = 0x3, +} UNP_CRC_LINE_SEL; +typedef enum UNP_ROTATION_ANGLE { + UNP_ROTATION_ANGLE_0 = 0x0, + UNP_ROTATION_ANGLE_90 = 0x1, + UNP_ROTATION_ANGLE_180 = 0x2, + UNP_ROTATION_ANGLE_270 = 0x3, + UNP_ROTATION_ANGLE_0m = 0x4, + UNP_ROTATION_ANGLE_90m = 0x5, + UNP_ROTATION_ANGLE_180m = 0x6, + UNP_ROTATION_ANGLE_270m = 0x7, +} UNP_ROTATION_ANGLE; +typedef enum UNP_PIXEL_DROP { + UNP_PIXEL_NO_DROP = 0x0, + UNP_PIXEL_DROPPING = 0x1, +} UNP_PIXEL_DROP; +typedef enum UNP_BUFFER_MODE { + UNP_BUFFER_MODE_LUMA = 0x0, + UNP_BUFFER_MODE_LUMA_CHROMA = 0x1, +} UNP_BUFFER_MODE; +typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET { + AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET= 0x0, + AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET= 0x1, +} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET; +typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY { + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL= 0x0, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6= 0x1, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4= 0x3, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3= 0x4, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2= 0x5, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1= 0x6, + CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0= 0x7, +} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY; +typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY { + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL= 0x0, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6= 0x1, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4= 0x3, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3= 0x4, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2= 0x5, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1= 0x6, + CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0= 0x7, +} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY; +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL { + GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x0, + GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x1, +} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL; +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED { + GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x0, + GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x1, +} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED; +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS { + GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x0, + GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x1, +} GENERIC_AZ_CONTROLLER_REGISTER_STATUS; +typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED { + GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED= 0x0, + GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED= 0x1, +} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED; +typedef enum AZ_GLOBAL_CAPABILITIES { + AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED= 0x0, + AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED= 0x1, +} AZ_GLOBAL_CAPABILITIES; +typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE { + ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x0, + ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x1, +} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE; +typedef enum GLOBAL_CONTROL_FLUSH_CONTROL { + FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x0, + FLUSH_CONTROL_FLUSH_STARTED = 0x1, +} GLOBAL_CONTROL_FLUSH_CONTROL; +typedef enum GLOBAL_CONTROL_CONTROLLER_RESET { + CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x0, + CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x1, +} GLOBAL_CONTROL_CONTROLLER_RESET; +typedef enum AZ_STATE_CHANGE_STATUS { + AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x0, + AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x1, +} AZ_STATE_CHANGE_STATUS; +typedef enum GLOBAL_STATUS_FLUSH_STATUS { + GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x0, + GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x1, +} GLOBAL_STATUS_FLUSH_STATUS; +typedef enum STREAM_0_SYNCHRONIZATION { + STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, + STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x1, +} STREAM_0_SYNCHRONIZATION; +typedef enum STREAM_1_SYNCHRONIZATION { + STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, + STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x1, +} STREAM_1_SYNCHRONIZATION; +typedef enum STREAM_2_SYNCHRONIZATION { + STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, + STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x1, +} STREAM_2_SYNCHRONIZATION; +typedef enum STREAM_3_SYNCHRONIZATION { + STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_3_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_3_SYNCHRONIZATION; +typedef enum STREAM_4_SYNCHRONIZATION { + STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_4_SYNCHRONIZATION; +typedef enum STREAM_5_SYNCHRONIZATION { + STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_5_SYNCHRONIZATION; +typedef enum STREAM_6_SYNCHRONIZATION { + STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_6_SYNCHRONIZATION; +typedef enum STREAM_7_SYNCHRONIZATION { + STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_7_SYNCHRONIZATION; +typedef enum STREAM_8_SYNCHRONIZATION { + STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_8_SYNCHRONIZATION; +typedef enum STREAM_9_SYNCHRONIZATION { + STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_9_SYNCHRONIZATION; +typedef enum STREAM_10_SYNCHRONIZATION { + STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_10_SYNCHRONIZATION; +typedef enum STREAM_11_SYNCHRONIZATION { + STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_11_SYNCHRONIZATION; +typedef enum STREAM_12_SYNCHRONIZATION { + STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_12_SYNCHRONIZATION; +typedef enum STREAM_13_SYNCHRONIZATION { + STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_13_SYNCHRONIZATION; +typedef enum STREAM_14_SYNCHRONIZATION { + STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_14_SYNCHRONIZATION; +typedef enum STREAM_15_SYNCHRONIZATION { + STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, + STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, +} STREAM_15_SYNCHRONIZATION; +typedef enum CORB_READ_POINTER_RESET { + CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x0, + CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x1, +} CORB_READ_POINTER_RESET; +typedef enum AZ_CORB_SIZE { + AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x0, + AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x1, + AZ_CORB_SIZE_256ENTRIES = 0x2, + AZ_CORB_SIZE_RESERVED = 0x3, +} AZ_CORB_SIZE; +typedef enum AZ_RIRB_WRITE_POINTER_RESET { + AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x0, + AZ_RIRB_WRITE_POINTER_DO_RESET = 0x1, +} AZ_RIRB_WRITE_POINTER_RESET; +typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL { + RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0, + RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1, +} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL; +typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL { + RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0, + RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1, +} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL; +typedef enum AZ_RIRB_SIZE { + AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x0, + AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x1, + AZ_RIRB_SIZE_256ENTRIES = 0x2, + AZ_RIRB_SIZE_UNDEFINED = 0x3, +} AZ_RIRB_SIZE; +typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID { + IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID= 0x0, + IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID= 0x1, +} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID; +typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY { + IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY= 0x0, + IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY= 0x1, +} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY; +typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE { + DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE= 0x0, + DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE= 0x1, +} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN; +typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET { + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET= 0x0, + OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET; +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE { + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE { + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR { + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR; +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE { + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16= 0x1, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24= 0x3, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE; +typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS { + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED= 0x8, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED= 0x9, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED= 0xa, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED= 0xb, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED= 0xc, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED= 0xd, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED= 0xe, + OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED= 0xf, +} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, + AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; +typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE { + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE= 0x0, + AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE= 0x1, +} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE { + AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { + AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT { + AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; +typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0, + AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1, +} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; +typedef enum AZ_LATENCY_COUNTER_CONTROL { + AZ_LATENCY_COUNTER_NO_RESET = 0x0, + AZ_LATENCY_COUNTER_RESET_DONE = 0x1, +} AZ_LATENCY_COUNTER_CONTROL; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0, + AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1, +} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; +typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; +typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { + AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0, + AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1, +} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; +typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY= 0x0, + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY= 0x1, +} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0, + AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1, +} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; +typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { + AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY= 0x0, + AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY= 0x1, +} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; +typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0, + AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1, +} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE; +typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0, + AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1, +} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; +typedef enum BLND_CONTROL_BLND_MODE { + BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0, + BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1, + BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2, + BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3, +} BLND_CONTROL_BLND_MODE; +typedef enum BLND_CONTROL_BLND_STEREO_TYPE { + BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0, + BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1, + BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2, + BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3, +} BLND_CONTROL_BLND_STEREO_TYPE; +typedef enum BLND_CONTROL_BLND_STEREO_POLARITY { + BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0, + BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1, +} BLND_CONTROL_BLND_STEREO_POLARITY; +typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN { + BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0, + BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1, +} BLND_CONTROL_BLND_FEEDTHROUGH_EN; +typedef enum BLND_CONTROL_BLND_ALPHA_MODE { + BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x0, + BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1, + BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2, + BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3, +} BLND_CONTROL_BLND_ALPHA_MODE; +typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE { + BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0, + BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1, +} BLND_CONTROL_BLND_MULTIPLIED_MODE; +typedef enum BLND_SM_CONTROL2_SM_MODE { + BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0, + BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2, + BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4, + BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6, +} BLND_SM_CONTROL2_SM_MODE; +typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE { + BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0, + BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1, +} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE; +typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE { + BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0, + BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1, +} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE; +typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL { + BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0, + BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1, + BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2, + BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3, +} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; +typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL { + BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0, + BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1, + BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2, + BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3, +} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; +typedef enum BLND_CONTROL2_PTI_ENABLE { + BLND_CONTROL2_PTI_ENABLE_FALSE = 0x0, + BLND_CONTROL2_PTI_ENABLE_TRUE = 0x1, +} BLND_CONTROL2_PTI_ENABLE; +typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN { + BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0, + BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1, +} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; +typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN { + BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0, + BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1, +} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN; +typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK { + BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0, + BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1, +} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; +typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK { + BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0, + BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1, +} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0, + BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1, +} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0, + BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1, +} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0, + BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1, +} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0, + BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1, +} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0, + BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1, +} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK { + BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x0, + BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1, +} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; +typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE { + BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x0, + BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1, +} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; +typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT { + BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0, + BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1, +} BLND_DEBUG_BLND_CNV_MUX_SELECT; +typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN { + BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0, + BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1, +} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; +typedef enum DebugBlockId { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_UVDU = 0xd, + DBG_BLOCK_ID_SQA = 0xe, + DBG_BLOCK_ID_SDMA0 = 0xf, + DBG_BLOCK_ID_SDMA1 = 0x10, + DBG_BLOCK_ID_SPIM = 0x11, + DBG_BLOCK_ID_GDS = 0x12, + DBG_BLOCK_ID_VC0 = 0x13, + DBG_BLOCK_ID_VC1 = 0x14, + DBG_BLOCK_ID_PA0 = 0x15, + DBG_BLOCK_ID_PA1 = 0x16, + DBG_BLOCK_ID_CP0 = 0x17, + DBG_BLOCK_ID_CP1 = 0x18, + DBG_BLOCK_ID_CP2 = 0x19, + DBG_BLOCK_ID_XBR = 0x1a, + DBG_BLOCK_ID_UVDM = 0x1b, + DBG_BLOCK_ID_VGT0 = 0x1c, + DBG_BLOCK_ID_VGT1 = 0x1d, + DBG_BLOCK_ID_IA = 0x1e, + DBG_BLOCK_ID_SXM0 = 0x1f, + DBG_BLOCK_ID_SXM1 = 0x20, + DBG_BLOCK_ID_SCT0 = 0x21, + DBG_BLOCK_ID_SCT1 = 0x22, + DBG_BLOCK_ID_SPM0 = 0x23, + DBG_BLOCK_ID_SPM1 = 0x24, + DBG_BLOCK_ID_UNUSED0 = 0x25, + DBG_BLOCK_ID_UNUSED1 = 0x26, + DBG_BLOCK_ID_TCAA = 0x27, + DBG_BLOCK_ID_TCAB = 0x28, + DBG_BLOCK_ID_TCCA = 0x29, + DBG_BLOCK_ID_TCCB = 0x2a, + DBG_BLOCK_ID_MCC0 = 0x2b, + DBG_BLOCK_ID_MCC1 = 0x2c, + DBG_BLOCK_ID_MCC2 = 0x2d, + DBG_BLOCK_ID_MCC3 = 0x2e, + DBG_BLOCK_ID_SXS0 = 0x2f, + DBG_BLOCK_ID_SXS1 = 0x30, + DBG_BLOCK_ID_SXS2 = 0x31, + DBG_BLOCK_ID_SXS3 = 0x32, + DBG_BLOCK_ID_SXS4 = 0x33, + DBG_BLOCK_ID_SXS5 = 0x34, + DBG_BLOCK_ID_SXS6 = 0x35, + DBG_BLOCK_ID_SXS7 = 0x36, + DBG_BLOCK_ID_SXS8 = 0x37, + DBG_BLOCK_ID_SXS9 = 0x38, + DBG_BLOCK_ID_BCI0 = 0x39, + DBG_BLOCK_ID_BCI1 = 0x3a, + DBG_BLOCK_ID_BCI2 = 0x3b, + DBG_BLOCK_ID_BCI3 = 0x3c, + DBG_BLOCK_ID_MCB = 0x3d, + DBG_BLOCK_ID_UNUSED6 = 0x3e, + DBG_BLOCK_ID_SQA00 = 0x3f, + DBG_BLOCK_ID_SQA01 = 0x40, + DBG_BLOCK_ID_SQA02 = 0x41, + DBG_BLOCK_ID_SQA10 = 0x42, + DBG_BLOCK_ID_SQA11 = 0x43, + DBG_BLOCK_ID_SQA12 = 0x44, + DBG_BLOCK_ID_UNUSED7 = 0x45, + DBG_BLOCK_ID_UNUSED8 = 0x46, + DBG_BLOCK_ID_SQB00 = 0x47, + DBG_BLOCK_ID_SQB01 = 0x48, + DBG_BLOCK_ID_SQB10 = 0x49, + DBG_BLOCK_ID_SQB11 = 0x4a, + DBG_BLOCK_ID_SQ00 = 0x4b, + DBG_BLOCK_ID_SQ01 = 0x4c, + DBG_BLOCK_ID_SQ10 = 0x4d, + DBG_BLOCK_ID_SQ11 = 0x4e, + DBG_BLOCK_ID_CB00 = 0x4f, + DBG_BLOCK_ID_CB01 = 0x50, + DBG_BLOCK_ID_CB02 = 0x51, + DBG_BLOCK_ID_CB03 = 0x52, + DBG_BLOCK_ID_CB04 = 0x53, + DBG_BLOCK_ID_UNUSED9 = 0x54, + DBG_BLOCK_ID_UNUSED10 = 0x55, + DBG_BLOCK_ID_UNUSED11 = 0x56, + DBG_BLOCK_ID_CB10 = 0x57, + DBG_BLOCK_ID_CB11 = 0x58, + DBG_BLOCK_ID_CB12 = 0x59, + DBG_BLOCK_ID_CB13 = 0x5a, + DBG_BLOCK_ID_CB14 = 0x5b, + DBG_BLOCK_ID_UNUSED12 = 0x5c, + DBG_BLOCK_ID_UNUSED13 = 0x5d, + DBG_BLOCK_ID_UNUSED14 = 0x5e, + DBG_BLOCK_ID_TCP0 = 0x5f, + DBG_BLOCK_ID_TCP1 = 0x60, + DBG_BLOCK_ID_TCP2 = 0x61, + DBG_BLOCK_ID_TCP3 = 0x62, + DBG_BLOCK_ID_TCP4 = 0x63, + DBG_BLOCK_ID_TCP5 = 0x64, + DBG_BLOCK_ID_TCP6 = 0x65, + DBG_BLOCK_ID_TCP7 = 0x66, + DBG_BLOCK_ID_TCP8 = 0x67, + DBG_BLOCK_ID_TCP9 = 0x68, + DBG_BLOCK_ID_TCP10 = 0x69, + DBG_BLOCK_ID_TCP11 = 0x6a, + DBG_BLOCK_ID_TCP12 = 0x6b, + DBG_BLOCK_ID_TCP13 = 0x6c, + DBG_BLOCK_ID_TCP14 = 0x6d, + DBG_BLOCK_ID_TCP15 = 0x6e, + DBG_BLOCK_ID_TCP16 = 0x6f, + DBG_BLOCK_ID_TCP17 = 0x70, + DBG_BLOCK_ID_TCP18 = 0x71, + DBG_BLOCK_ID_TCP19 = 0x72, + DBG_BLOCK_ID_TCP20 = 0x73, + DBG_BLOCK_ID_TCP21 = 0x74, + DBG_BLOCK_ID_TCP22 = 0x75, + DBG_BLOCK_ID_TCP23 = 0x76, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, + DBG_BLOCK_ID_DB00 = 0x7f, + DBG_BLOCK_ID_DB01 = 0x80, + DBG_BLOCK_ID_DB02 = 0x81, + DBG_BLOCK_ID_DB03 = 0x82, + DBG_BLOCK_ID_DB04 = 0x83, + DBG_BLOCK_ID_UNUSED15 = 0x84, + DBG_BLOCK_ID_UNUSED16 = 0x85, + DBG_BLOCK_ID_UNUSED17 = 0x86, + DBG_BLOCK_ID_DB10 = 0x87, + DBG_BLOCK_ID_DB11 = 0x88, + DBG_BLOCK_ID_DB12 = 0x89, + DBG_BLOCK_ID_DB13 = 0x8a, + DBG_BLOCK_ID_DB14 = 0x8b, + DBG_BLOCK_ID_UNUSED18 = 0x8c, + DBG_BLOCK_ID_UNUSED19 = 0x8d, + DBG_BLOCK_ID_UNUSED20 = 0x8e, + DBG_BLOCK_ID_TCC0 = 0x8f, + DBG_BLOCK_ID_TCC1 = 0x90, + DBG_BLOCK_ID_TCC2 = 0x91, + DBG_BLOCK_ID_TCC3 = 0x92, + DBG_BLOCK_ID_TCC4 = 0x93, + DBG_BLOCK_ID_TCC5 = 0x94, + DBG_BLOCK_ID_TCC6 = 0x95, + DBG_BLOCK_ID_TCC7 = 0x96, + DBG_BLOCK_ID_SPS00 = 0x97, + DBG_BLOCK_ID_SPS01 = 0x98, + DBG_BLOCK_ID_SPS02 = 0x99, + DBG_BLOCK_ID_SPS10 = 0x9a, + DBG_BLOCK_ID_SPS11 = 0x9b, + DBG_BLOCK_ID_SPS12 = 0x9c, + DBG_BLOCK_ID_UNUSED21 = 0x9d, + DBG_BLOCK_ID_UNUSED22 = 0x9e, + DBG_BLOCK_ID_TA00 = 0x9f, + DBG_BLOCK_ID_TA01 = 0xa0, + DBG_BLOCK_ID_TA02 = 0xa1, + DBG_BLOCK_ID_TA03 = 0xa2, + DBG_BLOCK_ID_TA04 = 0xa3, + DBG_BLOCK_ID_TA05 = 0xa4, + DBG_BLOCK_ID_TA06 = 0xa5, + DBG_BLOCK_ID_TA07 = 0xa6, + DBG_BLOCK_ID_TA08 = 0xa7, + DBG_BLOCK_ID_TA09 = 0xa8, + DBG_BLOCK_ID_TA0A = 0xa9, + DBG_BLOCK_ID_TA0B = 0xaa, + DBG_BLOCK_ID_UNUSED23 = 0xab, + DBG_BLOCK_ID_UNUSED24 = 0xac, + DBG_BLOCK_ID_UNUSED25 = 0xad, + DBG_BLOCK_ID_UNUSED26 = 0xae, + DBG_BLOCK_ID_TA10 = 0xaf, + DBG_BLOCK_ID_TA11 = 0xb0, + DBG_BLOCK_ID_TA12 = 0xb1, + DBG_BLOCK_ID_TA13 = 0xb2, + DBG_BLOCK_ID_TA14 = 0xb3, + DBG_BLOCK_ID_TA15 = 0xb4, + DBG_BLOCK_ID_TA16 = 0xb5, + DBG_BLOCK_ID_TA17 = 0xb6, + DBG_BLOCK_ID_TA18 = 0xb7, + DBG_BLOCK_ID_TA19 = 0xb8, + DBG_BLOCK_ID_TA1A = 0xb9, + DBG_BLOCK_ID_TA1B = 0xba, + DBG_BLOCK_ID_UNUSED27 = 0xbb, + DBG_BLOCK_ID_UNUSED28 = 0xbc, + DBG_BLOCK_ID_UNUSED29 = 0xbd, + DBG_BLOCK_ID_UNUSED30 = 0xbe, + DBG_BLOCK_ID_TD00 = 0xbf, + DBG_BLOCK_ID_TD01 = 0xc0, + DBG_BLOCK_ID_TD02 = 0xc1, + DBG_BLOCK_ID_TD03 = 0xc2, + DBG_BLOCK_ID_TD04 = 0xc3, + DBG_BLOCK_ID_TD05 = 0xc4, + DBG_BLOCK_ID_TD06 = 0xc5, + DBG_BLOCK_ID_TD07 = 0xc6, + DBG_BLOCK_ID_TD08 = 0xc7, + DBG_BLOCK_ID_TD09 = 0xc8, + DBG_BLOCK_ID_TD0A = 0xc9, + DBG_BLOCK_ID_TD0B = 0xca, + DBG_BLOCK_ID_UNUSED31 = 0xcb, + DBG_BLOCK_ID_UNUSED32 = 0xcc, + DBG_BLOCK_ID_UNUSED33 = 0xcd, + DBG_BLOCK_ID_UNUSED34 = 0xce, + DBG_BLOCK_ID_TD10 = 0xcf, + DBG_BLOCK_ID_TD11 = 0xd0, + DBG_BLOCK_ID_TD12 = 0xd1, + DBG_BLOCK_ID_TD13 = 0xd2, + DBG_BLOCK_ID_TD14 = 0xd3, + DBG_BLOCK_ID_TD15 = 0xd4, + DBG_BLOCK_ID_TD16 = 0xd5, + DBG_BLOCK_ID_TD17 = 0xd6, + DBG_BLOCK_ID_TD18 = 0xd7, + DBG_BLOCK_ID_TD19 = 0xd8, + DBG_BLOCK_ID_TD1A = 0xd9, + DBG_BLOCK_ID_TD1B = 0xda, + DBG_BLOCK_ID_UNUSED35 = 0xdb, + DBG_BLOCK_ID_UNUSED36 = 0xdc, + DBG_BLOCK_ID_UNUSED37 = 0xdd, + DBG_BLOCK_ID_UNUSED38 = 0xde, + DBG_BLOCK_ID_LDS00 = 0xdf, + DBG_BLOCK_ID_LDS01 = 0xe0, + DBG_BLOCK_ID_LDS02 = 0xe1, + DBG_BLOCK_ID_LDS03 = 0xe2, + DBG_BLOCK_ID_LDS04 = 0xe3, + DBG_BLOCK_ID_LDS05 = 0xe4, + DBG_BLOCK_ID_LDS06 = 0xe5, + DBG_BLOCK_ID_LDS07 = 0xe6, + DBG_BLOCK_ID_LDS08 = 0xe7, + DBG_BLOCK_ID_LDS09 = 0xe8, + DBG_BLOCK_ID_LDS0A = 0xe9, + DBG_BLOCK_ID_LDS0B = 0xea, + DBG_BLOCK_ID_UNUSED39 = 0xeb, + DBG_BLOCK_ID_UNUSED40 = 0xec, + DBG_BLOCK_ID_UNUSED41 = 0xed, + DBG_BLOCK_ID_UNUSED42 = 0xee, + DBG_BLOCK_ID_LDS10 = 0xef, + DBG_BLOCK_ID_LDS11 = 0xf0, + DBG_BLOCK_ID_LDS12 = 0xf1, + DBG_BLOCK_ID_LDS13 = 0xf2, + DBG_BLOCK_ID_LDS14 = 0xf3, + DBG_BLOCK_ID_LDS15 = 0xf4, + DBG_BLOCK_ID_LDS16 = 0xf5, + DBG_BLOCK_ID_LDS17 = 0xf6, + DBG_BLOCK_ID_LDS18 = 0xf7, + DBG_BLOCK_ID_LDS19 = 0xf8, + DBG_BLOCK_ID_LDS1A = 0xf9, + DBG_BLOCK_ID_LDS1B = 0xfa, + DBG_BLOCK_ID_UNUSED43 = 0xfb, + DBG_BLOCK_ID_UNUSED44 = 0xfc, + DBG_BLOCK_ID_UNUSED45 = 0xfd, + DBG_BLOCK_ID_UNUSED46 = 0xfe, +} DebugBlockId; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_UVD_BY2 = 0x7, + DBG_BLOCK_ID_SDMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_VC0_BY2 = 0xa, + DBG_BLOCK_ID_PA_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_PC0_BY2 = 0xe, + DBG_BLOCK_ID_BCI0_BY2 = 0xf, + DBG_BLOCK_ID_SXM0_BY2 = 0x10, + DBG_BLOCK_ID_SCT0_BY2 = 0x11, + DBG_BLOCK_ID_SPM0_BY2 = 0x12, + DBG_BLOCK_ID_BCI2_BY2 = 0x13, + DBG_BLOCK_ID_TCA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_MCD_BY2 = 0x18, + DBG_BLOCK_ID_MCD2_BY2 = 0x19, + DBG_BLOCK_ID_MCD4_BY2 = 0x1a, + DBG_BLOCK_ID_MCB_BY2 = 0x1b, + DBG_BLOCK_ID_SQA_BY2 = 0x1c, + DBG_BLOCK_ID_SQA02_BY2 = 0x1d, + DBG_BLOCK_ID_SQA11_BY2 = 0x1e, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, + DBG_BLOCK_ID_SQB_BY2 = 0x20, + DBG_BLOCK_ID_SQB10_BY2 = 0x21, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, + DBG_BLOCK_ID_CB_BY2 = 0x24, + DBG_BLOCK_ID_CB02_BY2 = 0x25, + DBG_BLOCK_ID_CB10_BY2 = 0x26, + DBG_BLOCK_ID_CB12_BY2 = 0x27, + DBG_BLOCK_ID_SXS_BY2 = 0x28, + DBG_BLOCK_ID_SXS2_BY2 = 0x29, + DBG_BLOCK_ID_SXS4_BY2 = 0x2a, + DBG_BLOCK_ID_SXS6_BY2 = 0x2b, + DBG_BLOCK_ID_DB_BY2 = 0x2c, + DBG_BLOCK_ID_DB02_BY2 = 0x2d, + DBG_BLOCK_ID_DB10_BY2 = 0x2e, + DBG_BLOCK_ID_DB12_BY2 = 0x2f, + DBG_BLOCK_ID_TCP_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_TCC_BY2 = 0x40, + DBG_BLOCK_ID_TCC2_BY2 = 0x41, + DBG_BLOCK_ID_TCC4_BY2 = 0x42, + DBG_BLOCK_ID_TCC6_BY2 = 0x43, + DBG_BLOCK_ID_SPS_BY2 = 0x44, + DBG_BLOCK_ID_SPS02_BY2 = 0x45, + DBG_BLOCK_ID_SPS11_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, + DBG_BLOCK_ID_TA_BY2 = 0x48, + DBG_BLOCK_ID_TA02_BY2 = 0x49, + DBG_BLOCK_ID_TA04_BY2 = 0x4a, + DBG_BLOCK_ID_TA06_BY2 = 0x4b, + DBG_BLOCK_ID_TA08_BY2 = 0x4c, + DBG_BLOCK_ID_TA0A_BY2 = 0x4d, + DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, + DBG_BLOCK_ID_TA10_BY2 = 0x50, + DBG_BLOCK_ID_TA12_BY2 = 0x51, + DBG_BLOCK_ID_TA14_BY2 = 0x52, + DBG_BLOCK_ID_TA16_BY2 = 0x53, + DBG_BLOCK_ID_TA18_BY2 = 0x54, + DBG_BLOCK_ID_TA1A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, + DBG_BLOCK_ID_TD_BY2 = 0x58, + DBG_BLOCK_ID_TD02_BY2 = 0x59, + DBG_BLOCK_ID_TD04_BY2 = 0x5a, + DBG_BLOCK_ID_TD06_BY2 = 0x5b, + DBG_BLOCK_ID_TD08_BY2 = 0x5c, + DBG_BLOCK_ID_TD0A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, + DBG_BLOCK_ID_TD10_BY2 = 0x60, + DBG_BLOCK_ID_TD12_BY2 = 0x61, + DBG_BLOCK_ID_TD14_BY2 = 0x62, + DBG_BLOCK_ID_TD16_BY2 = 0x63, + DBG_BLOCK_ID_TD18_BY2 = 0x64, + DBG_BLOCK_ID_TD1A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, + DBG_BLOCK_ID_LDS_BY2 = 0x68, + DBG_BLOCK_ID_LDS02_BY2 = 0x69, + DBG_BLOCK_ID_LDS04_BY2 = 0x6a, + DBG_BLOCK_ID_LDS06_BY2 = 0x6b, + DBG_BLOCK_ID_LDS08_BY2 = 0x6c, + DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, + DBG_BLOCK_ID_LDS10_BY2 = 0x70, + DBG_BLOCK_ID_LDS12_BY2 = 0x71, + DBG_BLOCK_ID_LDS14_BY2 = 0x72, + DBG_BLOCK_ID_LDS16_BY2 = 0x73, + DBG_BLOCK_ID_LDS18_BY2 = 0x74, + DBG_BLOCK_ID_LDS1A_BY2 = 0x75, + DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, + DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_SDMA0_BY4 = 0x4, + DBG_BLOCK_ID_VC0_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, + DBG_BLOCK_ID_SXM0_BY4 = 0x8, + DBG_BLOCK_ID_SPM0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC_BY4 = 0xb, + DBG_BLOCK_ID_MCD_BY4 = 0xc, + DBG_BLOCK_ID_MCD4_BY4 = 0xd, + DBG_BLOCK_ID_SQA_BY4 = 0xe, + DBG_BLOCK_ID_SQA11_BY4 = 0xf, + DBG_BLOCK_ID_SQB_BY4 = 0x10, + DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, + DBG_BLOCK_ID_CB_BY4 = 0x12, + DBG_BLOCK_ID_CB10_BY4 = 0x13, + DBG_BLOCK_ID_SXS_BY4 = 0x14, + DBG_BLOCK_ID_SXS4_BY4 = 0x15, + DBG_BLOCK_ID_DB_BY4 = 0x16, + DBG_BLOCK_ID_DB10_BY4 = 0x17, + DBG_BLOCK_ID_TCP_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_TCC_BY4 = 0x20, + DBG_BLOCK_ID_TCC4_BY4 = 0x21, + DBG_BLOCK_ID_SPS_BY4 = 0x22, + DBG_BLOCK_ID_SPS11_BY4 = 0x23, + DBG_BLOCK_ID_TA_BY4 = 0x24, + DBG_BLOCK_ID_TA04_BY4 = 0x25, + DBG_BLOCK_ID_TA08_BY4 = 0x26, + DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, + DBG_BLOCK_ID_TA10_BY4 = 0x28, + DBG_BLOCK_ID_TA14_BY4 = 0x29, + DBG_BLOCK_ID_TA18_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, + DBG_BLOCK_ID_TD_BY4 = 0x2c, + DBG_BLOCK_ID_TD04_BY4 = 0x2d, + DBG_BLOCK_ID_TD08_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, + DBG_BLOCK_ID_TD10_BY4 = 0x30, + DBG_BLOCK_ID_TD14_BY4 = 0x31, + DBG_BLOCK_ID_TD18_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, + DBG_BLOCK_ID_LDS_BY4 = 0x34, + DBG_BLOCK_ID_LDS04_BY4 = 0x35, + DBG_BLOCK_ID_LDS08_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, + DBG_BLOCK_ID_LDS10_BY4 = 0x38, + DBG_BLOCK_ID_LDS14_BY4 = 0x39, + DBG_BLOCK_ID_LDS18_BY4 = 0x3a, + DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_SDMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_SXM0_BY8 = 0x4, + DBG_BLOCK_ID_TCA_BY8 = 0x5, + DBG_BLOCK_ID_MCD_BY8 = 0x6, + DBG_BLOCK_ID_SQA_BY8 = 0x7, + DBG_BLOCK_ID_SQB_BY8 = 0x8, + DBG_BLOCK_ID_CB_BY8 = 0x9, + DBG_BLOCK_ID_SXS_BY8 = 0xa, + DBG_BLOCK_ID_DB_BY8 = 0xb, + DBG_BLOCK_ID_TCP_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_TCC_BY8 = 0x10, + DBG_BLOCK_ID_SPS_BY8 = 0x11, + DBG_BLOCK_ID_TA_BY8 = 0x12, + DBG_BLOCK_ID_TA08_BY8 = 0x13, + DBG_BLOCK_ID_TA10_BY8 = 0x14, + DBG_BLOCK_ID_TA18_BY8 = 0x15, + DBG_BLOCK_ID_TD_BY8 = 0x16, + DBG_BLOCK_ID_TD08_BY8 = 0x17, + DBG_BLOCK_ID_TD10_BY8 = 0x18, + DBG_BLOCK_ID_TD18_BY8 = 0x19, + DBG_BLOCK_ID_LDS_BY8 = 0x1a, + DBG_BLOCK_ID_LDS08_BY8 = 0x1b, + DBG_BLOCK_ID_LDS10_BY8 = 0x1c, + DBG_BLOCK_ID_LDS18_BY8 = 0x1d, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_SDMA0_BY16 = 0x1, + DBG_BLOCK_ID_SXM_BY16 = 0x2, + DBG_BLOCK_ID_MCD_BY16 = 0x3, + DBG_BLOCK_ID_SQB_BY16 = 0x4, + DBG_BLOCK_ID_SXS_BY16 = 0x5, + DBG_BLOCK_ID_TCP_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_TCC_BY16 = 0x8, + DBG_BLOCK_ID_TA_BY16 = 0x9, + DBG_BLOCK_ID_TA10_BY16 = 0xa, + DBG_BLOCK_ID_TD_BY16 = 0xb, + DBG_BLOCK_ID_TD10_BY16 = 0xc, + DBG_BLOCK_ID_LDS_BY16 = 0xd, + DBG_BLOCK_ID_LDS10_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; +typedef enum HPD_INT_CONTROL_ACK { + HPD_INT_CONTROL_ACK_0 = 0x0, + HPD_INT_CONTROL_ACK_1 = 0x1, +} HPD_INT_CONTROL_ACK; +typedef enum HPD_INT_CONTROL_POLARITY { + HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x0, + HPD_INT_CONTROL_GEN_INT_ON_CON = 0x1, +} HPD_INT_CONTROL_POLARITY; +typedef enum HPD_INT_CONTROL_RX_INT_ACK { + HPD_INT_CONTROL_RX_INT_ACK_0 = 0x0, + HPD_INT_CONTROL_RX_INT_ACK_1 = 0x1, +} HPD_INT_CONTROL_RX_INT_ACK; +typedef enum DPDBG_EN { + DPDBG_DISABLE = 0x0, + DPDBG_ENABLE = 0x1, +} DPDBG_EN; +typedef enum DPDBG_INPUT_EN { + DPDBG_INPUT_DISABLE = 0x0, + DPDBG_INPUT_ENABLE = 0x1, +} DPDBG_INPUT_EN; +typedef enum DPDBG_ERROR_DETECTION_MODE { + DPDBG_ERROR_DETECTION_MODE_CSC = 0x0, + DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 0x1, +} DPDBG_ERROR_DETECTION_MODE; +typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK { + DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0x0, + DPDBG_FIFO_OVERFLOW_INT_ENABLE = 0x1, +} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK; +typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE { + DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0x0, + DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 0x1, +} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE; +typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK { + DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0x0, + DPDBG_FIFO_OVERFLOW_INT_CLEAR = 0x1, +} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK; +typedef enum PM_ASSERT_RESET { + PM_ASSERT_RESET_0 = 0x0, + PM_ASSERT_RESET_1 = 0x1, +} PM_ASSERT_RESET; +typedef enum DAC_MUX_SELECT { + DAC_MUX_SELECT_DACA = 0x0, + DAC_MUX_SELECT_DACB = 0x1, +} DAC_MUX_SELECT; +typedef enum TMDS_DVO_MUX_SELECT { + TMDS_DVO_MUX_SELECT_B = 0x0, + TMDS_DVO_MUX_SELECT_G = 0x1, + TMDS_DVO_MUX_SELECT_R = 0x2, + TMDS_DVO_MUX_SELECT_RESERVED = 0x3, +} TMDS_DVO_MUX_SELECT; +typedef enum DACA_SOFT_RESET { + DACA_SOFT_RESET_0 = 0x0, + DACA_SOFT_RESET_1 = 0x1, +} DACA_SOFT_RESET; +typedef enum I2S0_SPDIF0_SOFT_RESET { + I2S0_SPDIF0_SOFT_RESET_0 = 0x0, + I2S0_SPDIF0_SOFT_RESET_1 = 0x1, +} I2S0_SPDIF0_SOFT_RESET; +typedef enum I2S1_SOFT_RESET { + I2S1_SOFT_RESET_0 = 0x0, + I2S1_SOFT_RESET_1 = 0x1, +} I2S1_SOFT_RESET; +typedef enum SPDIF1_SOFT_RESET { + SPDIF1_SOFT_RESET_0 = 0x0, + SPDIF1_SOFT_RESET_1 = 0x1, +} SPDIF1_SOFT_RESET; +typedef enum DB_CLK_SOFT_RESET { + DB_CLK_SOFT_RESET_0 = 0x0, + DB_CLK_SOFT_RESET_1 = 0x1, +} DB_CLK_SOFT_RESET; +typedef enum FMT0_SOFT_RESET { + FMT0_SOFT_RESET_0 = 0x0, + FMT0_SOFT_RESET_1 = 0x1, +} FMT0_SOFT_RESET; +typedef enum FMT1_SOFT_RESET { + FMT1_SOFT_RESET_0 = 0x0, + FMT1_SOFT_RESET_1 = 0x1, +} FMT1_SOFT_RESET; +typedef enum FMT2_SOFT_RESET { + FMT2_SOFT_RESET_0 = 0x0, + FMT2_SOFT_RESET_1 = 0x1, +} FMT2_SOFT_RESET; +typedef enum FMT3_SOFT_RESET { + FMT3_SOFT_RESET_0 = 0x0, + FMT3_SOFT_RESET_1 = 0x1, +} FMT3_SOFT_RESET; +typedef enum FMT4_SOFT_RESET { + FMT4_SOFT_RESET_0 = 0x0, + FMT4_SOFT_RESET_1 = 0x1, +} FMT4_SOFT_RESET; +typedef enum FMT5_SOFT_RESET { + FMT5_SOFT_RESET_0 = 0x0, + FMT5_SOFT_RESET_1 = 0x1, +} FMT5_SOFT_RESET; +typedef enum MVP_SOFT_RESET { + MVP_SOFT_RESET_0 = 0x0, + MVP_SOFT_RESET_1 = 0x1, +} MVP_SOFT_RESET; +typedef enum ABM_SOFT_RESET { + ABM_SOFT_RESET_0 = 0x0, + ABM_SOFT_RESET_1 = 0x1, +} ABM_SOFT_RESET; +typedef enum DVO_SOFT_RESET { + DVO_SOFT_RESET_0 = 0x0, + DVO_SOFT_RESET_1 = 0x1, +} DVO_SOFT_RESET; +typedef enum DIGA_FE_SOFT_RESET { + DIGA_FE_SOFT_RESET_0 = 0x0, + DIGA_FE_SOFT_RESET_1 = 0x1, +} DIGA_FE_SOFT_RESET; +typedef enum DIGA_BE_SOFT_RESET { + DIGA_BE_SOFT_RESET_0 = 0x0, + DIGA_BE_SOFT_RESET_1 = 0x1, +} DIGA_BE_SOFT_RESET; +typedef enum DIGB_FE_SOFT_RESET { + DIGB_FE_SOFT_RESET_0 = 0x0, + DIGB_FE_SOFT_RESET_1 = 0x1, +} DIGB_FE_SOFT_RESET; +typedef enum DIGB_BE_SOFT_RESET { + DIGB_BE_SOFT_RESET_0 = 0x0, + DIGB_BE_SOFT_RESET_1 = 0x1, +} DIGB_BE_SOFT_RESET; +typedef enum DIGC_FE_SOFT_RESET { + DIGC_FE_SOFT_RESET_0 = 0x0, + DIGC_FE_SOFT_RESET_1 = 0x1, +} DIGC_FE_SOFT_RESET; +typedef enum DIGC_BE_SOFT_RESET { + DIGC_BE_SOFT_RESET_0 = 0x0, + DIGC_BE_SOFT_RESET_1 = 0x1, +} DIGC_BE_SOFT_RESET; +typedef enum DIGD_FE_SOFT_RESET { + DIGD_FE_SOFT_RESET_0 = 0x0, + DIGD_FE_SOFT_RESET_1 = 0x1, +} DIGD_FE_SOFT_RESET; +typedef enum DIGD_BE_SOFT_RESET { + DIGD_BE_SOFT_RESET_0 = 0x0, + DIGD_BE_SOFT_RESET_1 = 0x1, +} DIGD_BE_SOFT_RESET; +typedef enum DIGE_FE_SOFT_RESET { + DIGE_FE_SOFT_RESET_0 = 0x0, + DIGE_FE_SOFT_RESET_1 = 0x1, +} DIGE_FE_SOFT_RESET; +typedef enum DIGE_BE_SOFT_RESET { + DIGE_BE_SOFT_RESET_0 = 0x0, + DIGE_BE_SOFT_RESET_1 = 0x1, +} DIGE_BE_SOFT_RESET; +typedef enum DIGF_FE_SOFT_RESET { + DIGF_FE_SOFT_RESET_0 = 0x0, + DIGF_FE_SOFT_RESET_1 = 0x1, +} DIGF_FE_SOFT_RESET; +typedef enum DIGF_BE_SOFT_RESET { + DIGF_BE_SOFT_RESET_0 = 0x0, + DIGF_BE_SOFT_RESET_1 = 0x1, +} DIGF_BE_SOFT_RESET; +typedef enum DIGG_FE_SOFT_RESET { + DIGG_FE_SOFT_RESET_0 = 0x0, + DIGG_FE_SOFT_RESET_1 = 0x1, +} DIGG_FE_SOFT_RESET; +typedef enum DIGG_BE_SOFT_RESET { + DIGG_BE_SOFT_RESET_0 = 0x0, + DIGG_BE_SOFT_RESET_1 = 0x1, +} DIGG_BE_SOFT_RESET; +typedef enum DPDBG_SOFT_RESET { + DPDBG_SOFT_RESET_0 = 0x0, + DPDBG_SOFT_RESET_1 = 0x1, +} DPDBG_SOFT_RESET; +typedef enum DIGLPA_FE_SOFT_RESET { + DIGLPA_FE_SOFT_RESET_0 = 0x0, + DIGLPA_FE_SOFT_RESET_1 = 0x1, +} DIGLPA_FE_SOFT_RESET; +typedef enum DIGLPA_BE_SOFT_RESET { + DIGLPA_BE_SOFT_RESET_0 = 0x0, + DIGLPA_BE_SOFT_RESET_1 = 0x1, +} DIGLPA_BE_SOFT_RESET; +typedef enum DIGLPB_FE_SOFT_RESET { + DIGLPB_FE_SOFT_RESET_0 = 0x0, + DIGLPB_FE_SOFT_RESET_1 = 0x1, +} DIGLPB_FE_SOFT_RESET; +typedef enum DIGLPB_BE_SOFT_RESET { + DIGLPB_BE_SOFT_RESET_0 = 0x0, + DIGLPB_BE_SOFT_RESET_1 = 0x1, +} DIGLPB_BE_SOFT_RESET; +typedef enum GENERICA_STEREOSYNC_SEL { + GENERICA_STEREOSYNC_SEL_D1 = 0x0, + GENERICA_STEREOSYNC_SEL_D2 = 0x1, + GENERICA_STEREOSYNC_SEL_D3 = 0x2, + GENERICA_STEREOSYNC_SEL_D4 = 0x3, + GENERICA_STEREOSYNC_SEL_D5 = 0x4, + GENERICA_STEREOSYNC_SEL_D6 = 0x5, + GENERICA_STEREOSYNC_SEL_RESERVED = 0x6, +} GENERICA_STEREOSYNC_SEL; +typedef enum GENERICB_STEREOSYNC_SEL { + GENERICB_STEREOSYNC_SEL_D1 = 0x0, + GENERICB_STEREOSYNC_SEL_D2 = 0x1, + GENERICB_STEREOSYNC_SEL_D3 = 0x2, + GENERICB_STEREOSYNC_SEL_D4 = 0x3, + GENERICB_STEREOSYNC_SEL_D5 = 0x4, + GENERICB_STEREOSYNC_SEL_D6 = 0x5, + GENERICB_STEREOSYNC_SEL_RESERVED = 0x6, +} GENERICB_STEREOSYNC_SEL; +typedef enum DCO_DBG_BLOCK_SEL { + DCO_DBG_BLOCK_SEL_DCO = 0x0, + DCO_DBG_BLOCK_SEL_ABM = 0x1, + DCO_DBG_BLOCK_SEL_DVO = 0x2, + DCO_DBG_BLOCK_SEL_DAC = 0x3, + DCO_DBG_BLOCK_SEL_MVP = 0x4, + DCO_DBG_BLOCK_SEL_FMT0 = 0x5, + DCO_DBG_BLOCK_SEL_FMT1 = 0x6, + DCO_DBG_BLOCK_SEL_FMT2 = 0x7, + DCO_DBG_BLOCK_SEL_FMT3 = 0x8, + DCO_DBG_BLOCK_SEL_FMT4 = 0x9, + DCO_DBG_BLOCK_SEL_FMT5 = 0xa, + DCO_DBG_BLOCK_SEL_DIGFE_A = 0xb, + DCO_DBG_BLOCK_SEL_DIGFE_B = 0xc, + DCO_DBG_BLOCK_SEL_DIGFE_C = 0xd, + DCO_DBG_BLOCK_SEL_DIGFE_D = 0xe, + DCO_DBG_BLOCK_SEL_DIGFE_E = 0xf, + DCO_DBG_BLOCK_SEL_DIGFE_F = 0x10, + DCO_DBG_BLOCK_SEL_DIGFE_G = 0x11, + DCO_DBG_BLOCK_SEL_DIGA = 0x12, + DCO_DBG_BLOCK_SEL_DIGB = 0x13, + DCO_DBG_BLOCK_SEL_DIGC = 0x14, + DCO_DBG_BLOCK_SEL_DIGD = 0x15, + DCO_DBG_BLOCK_SEL_DIGE = 0x16, + DCO_DBG_BLOCK_SEL_DIGF = 0x17, + DCO_DBG_BLOCK_SEL_DIGG = 0x18, + DCO_DBG_BLOCK_SEL_DPFE_A = 0x19, + DCO_DBG_BLOCK_SEL_DPFE_B = 0x1a, + DCO_DBG_BLOCK_SEL_DPFE_C = 0x1b, + DCO_DBG_BLOCK_SEL_DPFE_D = 0x1c, + DCO_DBG_BLOCK_SEL_DPFE_E = 0x1d, + DCO_DBG_BLOCK_SEL_DPFE_F = 0x1e, + DCO_DBG_BLOCK_SEL_DPFE_G = 0x1f, + DCO_DBG_BLOCK_SEL_DPA = 0x20, + DCO_DBG_BLOCK_SEL_DPB = 0x21, + DCO_DBG_BLOCK_SEL_DPC = 0x22, + DCO_DBG_BLOCK_SEL_DPD = 0x23, + DCO_DBG_BLOCK_SEL_DPE = 0x24, + DCO_DBG_BLOCK_SEL_DPF = 0x25, + DCO_DBG_BLOCK_SEL_DPG = 0x26, + DCO_DBG_BLOCK_SEL_AUX0 = 0x27, + DCO_DBG_BLOCK_SEL_AUX1 = 0x28, + DCO_DBG_BLOCK_SEL_AUX2 = 0x29, + DCO_DBG_BLOCK_SEL_AUX3 = 0x2a, + DCO_DBG_BLOCK_SEL_AUX4 = 0x2b, + DCO_DBG_BLOCK_SEL_AUX5 = 0x2c, + DCO_DBG_BLOCK_SEL_PERFMON_DCO = 0x2d, + DCO_DBG_BLOCK_SEL_AUDIO_OUT = 0x2e, + DCO_DBG_BLOCK_SEL_DIGLPFEA = 0x2f, + DCO_DBG_BLOCK_SEL_DIGLPFEB = 0x30, + DCO_DBG_BLOCK_SEL_DIGLPA = 0x31, + DCO_DBG_BLOCK_SEL_DIGLPB = 0x32, + DCO_DBG_BLOCK_SEL_DPLPFEA = 0x33, + DCO_DBG_BLOCK_SEL_DPLPFEB = 0x34, + DCO_DBG_BLOCK_SEL_DPLPA = 0x35, + DCO_DBG_BLOCK_SEL_DPLPB = 0x36, +} DCO_DBG_BLOCK_SEL; +typedef enum DCO_DBG_CLOCK_SEL { + DCO_DBG_CLOCK_SEL_DISPCLK = 0x0, + DCO_DBG_CLOCK_SEL_SCLK = 0x1, + DCO_DBG_CLOCK_SEL_MVPCLK = 0x2, + DCO_DBG_CLOCK_SEL_DVOCLK = 0x3, + DCO_DBG_CLOCK_SEL_DACCLK = 0x4, + DCO_DBG_CLOCK_SEL_REFCLK = 0x5, + DCO_DBG_CLOCK_SEL_SYMCLKA = 0x6, + DCO_DBG_CLOCK_SEL_SYMCLKB = 0x7, + DCO_DBG_CLOCK_SEL_SYMCLKC = 0x8, + DCO_DBG_CLOCK_SEL_SYMCLKD = 0x9, + DCO_DBG_CLOCK_SEL_SYMCLKE = 0xa, + DCO_DBG_CLOCK_SEL_SYMCLKF = 0xb, + DCO_DBG_CLOCK_SEL_SYMCLKG = 0xc, + DCO_DBG_CLOCK_SEL_RESERVED = 0xd, + DCO_DBG_CLOCK_SEL_AM0CLK = 0xe, + DCO_DBG_CLOCK_SEL_AM1CLK = 0xf, + DCO_DBG_CLOCK_SEL_AM2CLK = 0x10, + DCO_DBG_CLOCK_SEL_SYMCLKLPA = 0x11, + DCO_DBG_CLOCK_SEL_SYMCLKLPB = 0x12, +} DCO_DBG_CLOCK_SEL; +typedef enum DOUT_I2C_CONTROL_GO { + DOUT_I2C_CONTROL_STOP_TRANSFER = 0x0, + DOUT_I2C_CONTROL_START_TRANSFER = 0x1, +} DOUT_I2C_CONTROL_GO; +typedef enum DOUT_I2C_CONTROL_SOFT_RESET { + DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x0, + DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x1, +} DOUT_I2C_CONTROL_SOFT_RESET; +typedef enum DOUT_I2C_CONTROL_SEND_RESET { + DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x0, + DOUT_I2C_CONTROL__SEND_RESET = 0x1, +} DOUT_I2C_CONTROL_SEND_RESET; +typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET { + DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x0, + DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x1, +} DOUT_I2C_CONTROL_SW_STATUS_RESET; +typedef enum DOUT_I2C_CONTROL_DDC_SELECT { + DOUT_I2C_CONTROL_SELECT_DDC1 = 0x0, + DOUT_I2C_CONTROL_SELECT_DDC2 = 0x1, + DOUT_I2C_CONTROL_SELECT_DDC3 = 0x2, + DOUT_I2C_CONTROL_SELECT_DDC4 = 0x3, + DOUT_I2C_CONTROL_SELECT_DDC5 = 0x4, + DOUT_I2C_CONTROL_SELECT_DDC6 = 0x5, + DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x6, +} DOUT_I2C_CONTROL_DDC_SELECT; +typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT { + DOUT_I2C_CONTROL_TRANS0 = 0x0, + DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x1, + DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x2, + DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x3, +} DOUT_I2C_CONTROL_TRANSACTION_COUNT; +typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL { + DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x0, + DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x1, +} DOUT_I2C_CONTROL_DBG_REF_SEL; +typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY { + DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x0, + DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x1, + DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x2, + DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x3, +} DOUT_I2C_ARBITRATION_SW_PRIORITY; +typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO { + DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x0, + DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x1, +} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO; +typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER { + DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x0, + DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x1, +} DOUT_I2C_ARBITRATION_ABORT_XFER; +typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ { + DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x0, + DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x1, +} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ; +typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG { + DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x0, + DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x1, +} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG; +typedef enum DOUT_I2C_ACK { + DOUT_I2C_NO_ACK = 0x0, + DOUT_I2C_ACK_TO_CLEAN = 0x1, +} DOUT_I2C_ACK; +typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD { + DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x0, + DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE= 0x1, + DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2, + DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE= 0x3, +} DOUT_I2C_DDC_SPEED_THRESHOLD; +typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN { + DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR= 0x0, + DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x1, +} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN; +typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL { + DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x0, + DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x1, +} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL; +typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE { + DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x0, + DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x1, +} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE; +typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN { + DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR= 0x0, + DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x1, +} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN; +typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK { + DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x0, + DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x1, +} DOUT_I2C_TRANSACTION_STOP_ON_NACK; +typedef enum DOUT_I2C_DATA_INDEX_WRITE { + DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x0, + DOUT_I2C_DATA__INDEX_WRITE = 0x1, +} DOUT_I2C_DATA_INDEX_WRITE; +typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET { + DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x0, + DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x1, +} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET; +typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE { + DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x0, + DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x1, +} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE; +typedef enum BLNDV_CONTROL_BLND_MODE { + BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0, + BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1, + BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2, + BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3, +} BLNDV_CONTROL_BLND_MODE; +typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE { + BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0, + BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1, + BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2, + BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3, +} BLNDV_CONTROL_BLND_STEREO_TYPE; +typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY { + BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0, + BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1, +} BLNDV_CONTROL_BLND_STEREO_POLARITY; +typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN { + BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0, + BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1, +} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN; +typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE { + BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA= 0x0, + BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1, + BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2, + BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3, +} BLNDV_CONTROL_BLND_ALPHA_MODE; +typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE { + BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0, + BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1, +} BLNDV_CONTROL_BLND_MULTIPLIED_MODE; +typedef enum BLNDV_SM_CONTROL2_SM_MODE { + BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0, + BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2, + BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4, + BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6, +} BLNDV_SM_CONTROL2_SM_MODE; +typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE { + BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0, + BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1, +} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE; +typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE { + BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0, + BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1, +} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE; +typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL { + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3, +} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; +typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL { + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2, + BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3, +} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; +typedef enum BLNDV_CONTROL2_PTI_ENABLE { + BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x0, + BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x1, +} BLNDV_CONTROL2_PTI_ENABLE; +typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN { + BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0, + BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1, +} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; +typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN { + BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0, + BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1, +} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN; +typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK { + BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0, + BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1, +} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; +typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK { + BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0, + BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1, +} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0, + BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK { + BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; +typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE { + BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE= 0x0, + BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1, +} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; +typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT { + BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0, + BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1, +} BLNDV_DEBUG_BLND_CNV_MUX_SELECT; +typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN { + BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0, + BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1, +} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; + +#endif /* DCE_11_0_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h new file mode 100644 index 000000000000..a438c2b6e280 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h @@ -0,0 +1,17557 @@ +/* + * DCE_11_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DCE_11_0_SH_MASK_H +#define DCE_11_0_SH_MASK_H + +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1 +#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0 +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1 +#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0 +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1 +#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0 +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 +#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0 +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1 +#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0 +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1 +#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0 +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff +#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0 +#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000 +#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18 +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000 +#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000 +#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON_MASK 0x1 +#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON__SHIFT 0x0 +#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE_MASK 0x1 +#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE__SHIFT 0x0 +#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_READ_DATA_MASK 0xffffff +#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_READ_DATA__SHIFT 0x0 +#define DCFEV0_PG_STATUS__DCFEV0_DEBUG_PWR_STATUS_MASK 0x3000000 +#define DCFEV0_PG_STATUS__DCFEV0_DEBUG_PWR_STATUS__SHIFT 0x18 +#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK 0x10000000 +#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE__SHIFT 0x1c +#define DCFEV0_PG_STATUS__DCFEV0_REQUESTED_PWR_STATE_MASK 0x20000000 +#define DCFEV0_PG_STATUS__DCFEV0_REQUESTED_PWR_STATE__SHIFT 0x1d +#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS_MASK 0xc0000000 +#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1 +#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x2 +#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED_MASK 0x4 +#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x8 +#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x10 +#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x20 +#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED_MASK 0x40 +#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x80 +#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK 0x100 +#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x8 +#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x200 +#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 +#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED_MASK 0x400 +#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0xa +#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800 +#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb +#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x1000 +#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0xc +#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x2000 +#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0xd +#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED_MASK 0x4000 +#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED__SHIFT 0xe +#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED_MASK 0x8000 +#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK_MASK 0x1 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR_MASK 0x2 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK_MASK 0x4 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x8 +#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x10 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR_MASK 0x20 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK_MASK 0x40 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80 +#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK 0x100 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x200 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK_MASK 0x400 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x800 +#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK_MASK 0x1000 +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR_MASK 0x2000 +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK_MASK 0x4000 +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x8000 +#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK_MASK 0x10000 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR_MASK 0x20000 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK_MASK 0x40000 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x12 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x80000 +#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK_MASK 0x100000 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK__SHIFT 0x14 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR_MASK 0x200000 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x15 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK_MASK 0x400000 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x16 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000 +#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK_MASK 0x1000000 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK__SHIFT 0x18 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR_MASK 0x2000000 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x19 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK_MASK 0x4000000 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK__SHIFT 0x1a +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x8000000 +#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x1b +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK_MASK 0x10000000 +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK__SHIFT 0x1c +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR_MASK 0x20000000 +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR__SHIFT 0x1d +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK_MASK 0x40000000 +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK__SHIFT 0x1e +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR_MASK 0x80000000 +#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x1f +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1 +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff +#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0 +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff +#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2 +#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1 +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4 +#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2 +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000 +#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0 +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1 +#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000 +#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1 +#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0 +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100 +#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8 +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000 +#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff +#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000 +#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14 +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000 +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff +#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000 +#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10 +#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff +#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000 +#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000 +#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0 +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000 +#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000 +#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000 +#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0 +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000 +#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000 +#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11 +#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x3fff +#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0 +#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000 +#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10 +#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff +#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff +#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0 +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff +#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0 +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000 +#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10 +#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000 +#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000 +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000 +#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000 +#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10 +#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000 +#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000 +#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1 +#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000 +#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10 +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1 +#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0 +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e +#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000 +#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000 +#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1 +#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000 +#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1 +#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000 +#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000 +#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000 +#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff +#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0 +#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1 +#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 +#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 +#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 +#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 +#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 +#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 +#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 +#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 +#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 +#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d +#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000 +#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e +#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000 +#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1 +#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000 +#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000 +#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2 +#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2 +#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000 +#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff +#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1 +#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0 +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2 +#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1 +#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4 +#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2 +#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8 +#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3 +#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10 +#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4 +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20 +#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000 +#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10 +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000 +#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11 +#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000 +#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12 +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff +#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0 +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000 +#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10 +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff +#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0 +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff +#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0 +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff +#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0 +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff +#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e +#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1 +#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0 +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1 +#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100 +#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000 +#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1 +#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10 +#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14 +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000 +#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000 +#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000 +#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4 +#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3 +#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000 +#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff +#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 +#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2 +#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1 +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4 +#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2 +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100 +#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8 +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000 +#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2 +#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20 +#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000 +#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000 +#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1 +#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000 +#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1 +#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000 +#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000 +#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000 +#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10 +#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1 +#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0 +#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100 +#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8 +#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x10000 +#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10 +#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7 +#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0 +#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000 +#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00 +#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8 +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff +#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000 +#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000 +#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14 +#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1 +#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000 +#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100 +#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 +#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 +#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000 +#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000 +#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 +#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 +#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000 +#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff +#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff +#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000 +#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 +#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 +#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 +#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 +#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 +#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 +#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 +#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc +#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 +#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 +#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 +#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 +#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 +#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000 +#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff +#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 +#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff +#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000 +#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff +#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 +#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff +#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000 +#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000 +#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000 +#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000 +#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0 +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000 +#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000 +#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff +#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 +#define DAC_ENABLE__DAC_ENABLE_MASK 0x1 +#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1 +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc +#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20 +#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100 +#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7 +#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8 +#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3 +#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1 +#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0 +#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000 +#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1 +#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x100 +#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000 +#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14 +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f +#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000 +#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14 +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f +#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000 +#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7 +#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000 +#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100 +#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00 +#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000 +#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000 +#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x1000000 +#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18 +#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff +#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0 +#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1 +#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100 +#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000 +#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10 +#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000 +#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18 +#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1 +#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0 +#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100 +#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000 +#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100 +#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000 +#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000 +#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000 +#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8 +#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3 +#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3 +#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0 +#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000 +#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10 +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff +#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0 +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 +#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000 +#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK 0xff +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK 0xffffffff +#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT 0x0 +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0xe00 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17 +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18 +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x4000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1a +#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x8000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x1b +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3 +#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xfc +#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x2 +#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00 +#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000 +#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x1 +#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x2 +#define PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000 +#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000 +#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff +#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define PERFMON_HI__PERFMON_HI_MASK 0xffff +#define PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000 +#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff +#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff +#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0 +#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x1 +#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0 +#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x2 +#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1 +#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0xf +#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x100 +#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8 +#define DCE_VERSION__MAJOR_VERSION_MASK 0xff +#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define DCE_VERSION__MINOR_VERSION_MASK 0xff00 +#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 +#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xffffffff +#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0 +#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x1 +#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0 +#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xffffffff +#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000 +#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 +#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1 +#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0 +#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2 +#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1 +#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4 +#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2 +#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8 +#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3 +#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10 +#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4 +#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20 +#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5 +#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x40 +#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6 +#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000 +#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1 +#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0 +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10 +#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1 +#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4 +#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20 +#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK 0x80 +#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT 0x7 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x100 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000 +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x800000 +#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x4000000 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x8000000 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000 +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000 +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000 +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x8 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x20 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x40 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE_MASK 0x100 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x200 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x10000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x20000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x40000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x80000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x100000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x200000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x400000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE_MASK 0x1000000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE_MASK 0x2000000 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE__SHIFT 0x19 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0 +#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000 +#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0xf +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0xff0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0xf +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0xff0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0xf +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0xff0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1 +#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30 +#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4 +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1 +#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30 +#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1 +#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0 +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30 +#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4 +#define PHYPLL_PIXCLK_CNTL__PHYPLL_PIXCLK_RESYNC_ENABLE_MASK 0x1 +#define PHYPLL_PIXCLK_CNTL__PHYPLL_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLL_PIXCLK_CNTL__DCCG_DEEP_COLOR_CNTL_PHYPLL_PIXCLK_MASK 0x30 +#define PHYPLL_PIXCLK_CNTL__DCCG_DEEP_COLOR_CNTL_PHYPLL_PIXCLK__SHIFT 0x4 +#define PHYPLL_PIXCLK_CNTL__PIXEL_RATE_PHYPLL_SEL_MASK 0x100 +#define PHYPLL_PIXCLK_CNTL__PIXEL_RATE_PHYPLL_SEL__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x1 +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700 +#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x1 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20 +#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20 +#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20 +#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20 +#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20 +#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff +#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0 +#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff +#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20 +#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000 +#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10 +#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff +#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0 +#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff +#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0 +#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE_MASK 0x3 +#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x2 +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000 +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x4000 +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x8000 +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x10000 +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x20000 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x40000 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x80000 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x100000 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x200000 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x1 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x10 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x700 +#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK 0x10 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT 0x4 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK 0x700 +#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT 0x8 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c +#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18 +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0 +#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK 0xffffffff +#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x1f +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x3e0 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x5 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf8000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0xf +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000 +#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f +#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x800000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x17 +#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK 0x1f000000 +#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT 0x18 +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff +#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0 +#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3 +#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0 +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4 +#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2 +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10 +#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4 +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700 +#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8 +#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800 +#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000 +#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000 +#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10 +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000 +#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18 +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000 +#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0xff +#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0 +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0xff00 +#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0xf00000 +#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14 +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0xf000000 +#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18 +#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000 +#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c +#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT_MASK 0x60000000 +#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT__SHIFT 0x1d +#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE_MASK 0x80000000 +#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE__SHIFT 0x1f +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff +#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0 +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff +#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0 +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000 +#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10 +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff +#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 +#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0xf +#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0 +#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0xf0 +#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4 +#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0xf00 +#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8 +#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0xf000 +#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc +#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0xf0000 +#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10 +#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0xf00000 +#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14 +#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0xf000000 +#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18 +#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xf0000000 +#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x1 +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0 +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0xf0 +#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff +#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff +#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000 +#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11 +#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff +#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000 +#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11 +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000 +#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1 +#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0 +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2 +#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1 +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4 +#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2 +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8 +#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3 +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10 +#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4 +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20 +#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5 +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100 +#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8 +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200 +#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9 +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff +#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 +#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS_MASK 0x1 +#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS__SHIFT 0x0 +#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA_MASK 0xffffffff +#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA__SHIFT 0x0 +#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE_MASK 0xff +#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE__SHIFT 0x0 +#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT_MASK 0xff00 +#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT__SHIFT 0x8 +#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER_MASK 0x3f0000 +#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER__SHIFT 0x10 +#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL_MASK 0x3 +#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL__SHIFT 0x0 +#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE_MASK 0x30 +#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE__SHIFT 0x4 +#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE_MASK 0x80 +#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE__SHIFT 0x7 +#define DVMM_CNTL__DBG_DCE_VMID_MASK 0xf00 +#define DVMM_CNTL__DBG_DCE_VMID__SHIFT 0x8 +#define DVMM_CNTL__FORCE_DBG_DCE_VMID_MASK 0x8000 +#define DVMM_CNTL__FORCE_DBG_DCE_VMID__SHIFT 0xf +#define DVMM_CNTL__OVERRIDE_SNOOP_MASK 0x20000 +#define DVMM_CNTL__OVERRIDE_SNOOP__SHIFT 0x11 +#define DVMM_CNTL__ENABLE_PDE_INVALIDATE_MASK 0x40000 +#define DVMM_CNTL__ENABLE_PDE_INVALIDATE__SHIFT 0x12 +#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS_MASK 0xffffffff +#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS__SHIFT 0x0 +#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR_MASK 0xffffffff +#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR__SHIFT 0x0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000 +#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10 +#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3 +#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0 +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10 +#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4 +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100 +#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8 +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000 +#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc +#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000 +#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10 +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000 +#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000 +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00 +#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff +#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0 +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff +#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff +#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0 +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff +#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0 +#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf +#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0 +#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0 +#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000 +#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1 +#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS_MASK 0x3f0000 +#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS__SHIFT 0x10 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10 +#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000 +#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000 +#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0xfffff +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xfff00000 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x7fff +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x10 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x20 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x40 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x80 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x100 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x200 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x400 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800 +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x1000 +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x2000 +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x4000 +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x3 +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x10 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x20 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x40 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x3 +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0 +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK 0xc +#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT 0x2 +#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK 0x10 +#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT 0x4 +#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK 0x40 +#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT 0x6 +#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x100 +#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8 +#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x600 +#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9 +#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800 +#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb +#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x3000 +#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc +#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK 0xc000 +#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT 0xe +#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE_MASK 0x30000 +#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE__SHIFT 0x10 +#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE_MASK 0xc0000 +#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE__SHIFT 0x12 +#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 0x300000 +#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE__SHIFT 0x14 +#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x400000 +#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16 +#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000000 +#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18 +#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0xc000000 +#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a +#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000 +#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c +#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x3 +#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0 +#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0xc +#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2 +#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x10 +#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4 +#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x60 +#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5 +#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x180 +#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7 +#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x200 +#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9 +#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc00 +#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa +#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x3000 +#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc +#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x4000 +#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe +#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x18000 +#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf +#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000 +#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11 +#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x80000 +#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13 +#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x300000 +#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14 +#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0xc00000 +#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16 +#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x1000000 +#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18 +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f +#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0 +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20 +#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5 +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40 +#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6 +#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80 +#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7 +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100 +#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200 +#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9 +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800 +#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000 +#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd +#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x4000 +#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000 +#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15 +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000 +#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16 +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000 +#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17 +#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000 +#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS_MASK 0x2000000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS__SHIFT 0x19 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS_MASK 0x4000000 +#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS__SHIFT 0x1a +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000 +#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS_MASK 0x1 +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x0 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS_MASK 0x2 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x1 +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x4 +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x2 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x8 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x3 +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x10 +#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x4 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x80000000 +#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x1f +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x3 +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0 +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x4 +#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK 0x8 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x3 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK 0x10 +#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT 0x4 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK 0x20 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT 0x5 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK 0x40 +#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT 0x6 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x80 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x100 +#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x600 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800 +#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x1000 +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x2000 +#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0xc000 +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x10000 +#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK 0x60000 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT 0x11 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK 0x80000 +#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT 0x13 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x300000 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x400000 +#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x1800000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x2000000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19 +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0xc000000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000 +#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000 +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000 +#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x3 +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x4 +#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x18 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x20 +#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x40 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x80 +#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x300 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x400 +#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x1800 +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x2000 +#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x4000 +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x8000 +#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x30000 +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10 +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x40000 +#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x180000 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x200000 +#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x400000 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x800000 +#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x3000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x4000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000 +#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x3 +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x4 +#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x18 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x20 +#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x40 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x80 +#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x300 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x400 +#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x1800 +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x2000 +#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x4000 +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x8000 +#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf +#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x30000 +#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10 +#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0xc0000 +#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12 +#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x300000 +#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14 +#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x400000 +#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16 +#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x1800000 +#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x6000000 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000 +#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b +#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000 +#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE_MASK 0x3 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE__SHIFT 0x0 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS_MASK 0x4 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS__SHIFT 0x2 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE_MASK 0x18 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE__SHIFT 0x3 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS_MASK 0x20 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS__SHIFT 0x5 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE_MASK 0xc0 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE__SHIFT 0x6 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS_MASK 0x100 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS__SHIFT 0x8 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE_MASK 0x600 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE__SHIFT 0x9 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS_MASK 0x800 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS__SHIFT 0xb +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE_MASK 0x3000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE__SHIFT 0xc +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS_MASK 0x4000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS__SHIFT 0xe +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE_MASK 0x18000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE__SHIFT 0xf +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS_MASK 0x20000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS__SHIFT 0x11 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE_MASK 0xc0000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE__SHIFT 0x12 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS_MASK 0x100000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS__SHIFT 0x14 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE_MASK 0x600000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE__SHIFT 0x15 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS_MASK 0x800000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS__SHIFT 0x17 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL_MASK 0x3000000 +#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL__SHIFT 0x18 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE_MASK 0x3 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE__SHIFT 0x0 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE_MASK 0xc +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE__SHIFT 0x2 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE_MASK 0x30 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE__SHIFT 0x4 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE_MASK 0xc0 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE__SHIFT 0x6 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE_MASK 0x300 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE__SHIFT 0x8 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE_MASK 0xc00 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE__SHIFT 0xa +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE_MASK 0x3000 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE__SHIFT 0xc +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE_MASK 0xc000 +#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE__SHIFT 0xe +#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1 +#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 +#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2 +#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1 +#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4 +#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2 +#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8 +#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3 +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10 +#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4 +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20 +#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5 +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40 +#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6 +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80 +#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7 +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100 +#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8 +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200 +#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9 +#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x400 +#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa +#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x800 +#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000 +#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc +#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x10000 +#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10 +#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x20000 +#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11 +#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x40000 +#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12 +#define DCI_MISC__MCIF_WB_URG_OVRD_MASK 0x1 +#define DCI_MISC__MCIF_WB_URG_OVRD__SHIFT 0x0 +#define DCI_MISC__MCIF_WB_URG_LVL_MASK 0x1e +#define DCI_MISC__MCIF_WB_URG_LVL__SHIFT 0x1 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK 0x1 +#define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT 0x0 +#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK 0xf0 +#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT 0x4 +#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK 0xf00 +#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT 0x8 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 +#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 +#define DC_GENERICA__GENERICA_EN_MASK 0x1 +#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 +#define DC_GENERICA__GENERICA_SEL_MASK 0xf80 +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICB__GENERICB_EN_MASK 0x1 +#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 +#define DC_GENERICB__GENERICB_SEL_MASK 0xf00 +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf +#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0 +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30 +#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1 +#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300 +#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000 +#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10 +#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000 +#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11 +#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000 +#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 +#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 +#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000 +#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000 +#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000 +#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff +#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0 +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1 +#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100 +#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400 +#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000 +#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000 +#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 +#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1 +#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100 +#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400 +#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000 +#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000 +#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 +#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c +#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x78000 +#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10 +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10 +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf +#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000 +#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000 +#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xf +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0 +#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0xf0 +#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4 +#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0xf00 +#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8 +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0xf000 +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400 +#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000 +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000 +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0xe0000 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 +#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000 +#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000 +#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000 +#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000 +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000 +#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7 +#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0 +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700 +#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8 +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000 +#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV_P_FLIP_MASK 0x3800000 +#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV_P_FLIP__SHIFT 0x17 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x1f +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x20 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000 +#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f +#define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK 0x1 +#define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT 0x0 +#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK 0x10 +#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT 0x4 +#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK 0x300 +#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT 0x8 +#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK 0xfff000 +#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT 0xc +#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x1 +#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x1 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x2 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x4 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x8 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x10 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x20 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x40 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x80 +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x100 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x200 +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x400 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x800 +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x1000 +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x2000 +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd +#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x10000 +#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10 +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x100000 +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14 +#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x1000000 +#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18 +#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET_MASK 0x10000000 +#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET__SHIFT 0x1c +#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET_MASK 0x20000000 +#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET__SHIFT 0x1d +#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET_MASK 0x40000000 +#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET__SHIFT 0x1e +#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET_MASK 0x80000000 +#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET__SHIFT 0x1f +#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x3 +#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 +#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0xc +#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2 +#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x30 +#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4 +#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0xc0 +#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK 0xc0 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK 0xc00 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK 0x1000 +#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT 0xc +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK 0x2000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK 0x8000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT 0xf +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK 0x10000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10 +#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11 +#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK 0x40000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK 0x100000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT 0x14 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK 0x200000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT 0x15 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16 +#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK 0x800000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT 0x17 +#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18 +#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK 0x2000000 +#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT 0x19 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK 0x8000000 +#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b +#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff +#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0 +#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff +#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0 +#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff +#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0 +#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff +#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0 +#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff +#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0 +#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff +#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0 +#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff +#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0 +#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff +#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0 +#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff +#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0 +#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff +#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0 +#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff +#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0 +#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff +#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0 +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff +#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0 +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff +#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff +#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0 +#define DCIO_DEBUG16__DCIO_DEBUG16_MASK 0xffffffff +#define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT 0x0 +#define DCIO_DEBUG17__DCIO_DEBUG17_MASK 0xffffffff +#define DCIO_DEBUG17__DCIO_DEBUG17__SHIFT 0x0 +#define DCIO_DEBUG18__DCIO_DEBUG18_MASK 0xffffffff +#define DCIO_DEBUG18__DCIO_DEBUG18__SHIFT 0x0 +#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG_MASK 0xffffffff +#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG1B__DCIO_DEBUGHPD_MASK 0xffffffff +#define DCIO_DEBUG1B__DCIO_DEBUGHPD__SHIFT 0x0 +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff +#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000 +#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff +#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000 +#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000 +#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000 +#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000 +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000 +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000 +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000 +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000 +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000 +#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10 +#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000 +#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000 +#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100 +#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100 +#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100 +#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000 +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000 +#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1 +#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100 +#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1 +#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100 +#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8 +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1 +#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100 +#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x2 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1 +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000 +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x2 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x4 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x8 +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3 +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x10 +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4 +#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x20 +#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 +#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x40 +#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 +#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x80 +#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x200 +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 +#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x400 +#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x20000 +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 +#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x40000 +#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x100000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x200000 +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 +#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x400000 +#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x1000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x2000000 +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 +#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x4000000 +#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000 +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d +#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000 +#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0xf00 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0xf000 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0xf0000 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0xf00000 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x1 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x2 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x4 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x8 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x10 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x20 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x40 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x80 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7 +#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000 +#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x2000 +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000 +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe +#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000 +#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x1 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x2 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x4 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x10 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x20 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x40 +#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2 +#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2 +#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2 +#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0 +#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4 +#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1 +#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0 +#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2 +#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1 +#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0 +#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4 +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff +#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff +#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 +#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 +#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x2 +#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1 +#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 +#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 +#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc +#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 +#define GRPH_CONTROL__GRPH_Z_MASK 0x30 +#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4 +#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0 +#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6 +#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 +#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 +#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800 +#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb +#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000 +#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 +#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 +#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000 +#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12 +#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 +#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 +#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 +#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 +#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000 +#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 +#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000 +#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10 +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 +#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 +#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 +#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 +#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00 +#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff +#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0 +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff +#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0 +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff +#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0 +#define GRPH_X_START__GRPH_X_START_MASK 0x3fff +#define GRPH_X_START__GRPH_X_START__SHIFT 0x0 +#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff +#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0 +#define GRPH_X_END__GRPH_X_END_MASK 0x7fff +#define GRPH_X_END__GRPH_X_END__SHIFT 0x0 +#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff +#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0 +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x1 +#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 +#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 +#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100 +#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8 +#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 +#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 +#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 +#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 +#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0 +#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x2 +#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x10 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x20 +#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5 +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 +#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700 +#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf +#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0 +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 +#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200 +#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 +#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 +#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff +#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0 +#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6 +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0xff +#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10 +#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000 +#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10 +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3 +#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0 +#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff +#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0 +#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000 +#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10 +#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff +#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0 +#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000 +#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10 +#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff +#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0 +#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000 +#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10 +#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff +#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0 +#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000 +#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10 +#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff +#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0 +#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000 +#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10 +#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff +#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0 +#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000 +#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7 +#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000 +#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000 +#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000 +#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000 +#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000 +#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000 +#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000 +#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000 +#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10 +#define DENORM_CONTROL__DENORM_MODE_MASK 0x7 +#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0 +#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10 +#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4 +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf +#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000 +#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10 +#define KEY_CONTROL__KEY_MODE_MASK 0x6 +#define KEY_CONTROL__KEY_MODE__SHIFT 0x1 +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff +#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0 +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000 +#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10 +#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff +#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0 +#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000 +#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10 +#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff +#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0 +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000 +#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10 +#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff +#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0 +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000 +#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10 +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3 +#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0 +#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300 +#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8 +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000 +#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3 +#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000 +#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000 +#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000 +#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000 +#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000 +#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000 +#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0 +#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6 +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100 +#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8 +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200 +#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9 +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400 +#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000 +#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 +#define CUR_CONTROL__CURSOR_EN_MASK 0x1 +#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0 +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10 +#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4 +#define CUR_CONTROL__CURSOR_MODE_MASK 0x300 +#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000 +#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10 +#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000 +#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14 +#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000 +#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18 +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff +#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f +#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000 +#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff +#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff +#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000 +#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000 +#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff +#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0 +#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00 +#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8 +#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000 +#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10 +#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff +#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0 +#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00 +#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8 +#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000 +#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10 +#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1 +#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0 +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2 +#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1 +#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000 +#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10 +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000 +#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19 +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1 +#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2 +#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1 +#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0 +#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000 +#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10 +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1 +#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0 +#define DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x10000 +#define DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10 +#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x20000 +#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11 +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff +#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0 +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff +#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0 +#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff +#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0 +#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000 +#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000 +#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14 +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1 +#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0 +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7 +#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2 +#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1 +#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf +#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0 +#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6 +#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00 +#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000 +#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe +#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000 +#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000 +#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16 +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff +#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0 +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff +#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0 +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1 +#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0 +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c +#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2 +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300 +#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8 +#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff +#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0 +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff +#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0 +#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1 +#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0 +#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e +#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1 +#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0 +#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5 +#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00 +#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9 +#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000 +#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14 +#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000 +#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15 +#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff +#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0 +#define DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x3f +#define DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0 +#define DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0xff00 +#define DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8 +#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff +#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8 +#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3 +#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1 +#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0 +#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2 +#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1 +#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4 +#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000 +#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x60000 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x11 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x80000 +#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x13 +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000 +#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18 +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000 +#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000 +#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0 +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x1f0 +#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4 +#define DCP_DEBUG_SG__DCP_DEBUG_SG_MASK 0xffffffff +#define DCP_DEBUG_SG__DCP_DEBUG_SG__SHIFT 0x0 +#define DCP_DEBUG_SG2__DCP_DEBUG_SG2_MASK 0xffffffff +#define DCP_DEBUG_SG2__DCP_DEBUG_SG2__SHIFT 0x0 +#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG_MASK 0xffffffff +#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG__SHIFT 0x0 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8 +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 +#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 +#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 +#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c +#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff +#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0 +#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7 +#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4 +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7 +#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0 +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff +#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0 +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff +#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0 +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7 +#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff +#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 +#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff +#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 +#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 +#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1 +#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0 +#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2 +#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8 +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff +#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000 +#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x1 +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0 +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x1e +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1 +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x200 +#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9 +#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0xffff +#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0 +#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xffff0000 +#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10 +#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7 +#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70 +#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100 +#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG_FE_CNTL__DIG_START_MASK 0x400 +#define DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000 +#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000 +#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xc0000000 +#define DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300 +#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff +#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff +#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2 +#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20 +#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40 +#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000 +#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff +#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000 +#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1 +#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100 +#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000 +#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x4000000 +#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000 +#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1 +#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000 +#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1 +#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4 +#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8 +#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10 +#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100 +#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200 +#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000 +#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1 +#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000 +#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000 +#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000 +#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000 +#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000 +#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1 +#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20 +#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 +#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20 +#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200 +#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f +#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00 +#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000 +#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000 +#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 +#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1 +#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4 +#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10 +#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00 +#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000 +#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000 +#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7 +#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40 +#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80 +#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000 +#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000 +#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000 +#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000 +#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000 +#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000 +#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000 +#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000 +#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000 +#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000 +#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000 +#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000 +#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000 +#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000 +#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000 +#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000 +#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000 +#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000 +#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000 +#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000 +#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000 +#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000 +#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000 +#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000 +#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000 +#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff +#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000 +#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff +#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000 +#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff +#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000 +#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff +#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000 +#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000 +#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1 +#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2 +#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4 +#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38 +#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0 +#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00 +#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000 +#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000 +#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000 +#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000 +#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf +#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0 +#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000 +#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000 +#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000 +#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000 +#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000 +#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000 +#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff +#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000 +#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00 +#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10 +#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100 +#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000 +#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000 +#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000 +#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000 +#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80 +#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400 +#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7 +#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000 +#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 +#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x1 +#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x100 +#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x1 +#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG_BE_CNTL__DIG_SWAP_MASK 0x2 +#define DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x4 +#define DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00 +#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000 +#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000 +#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1 +#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100 +#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1 +#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8 +#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300 +#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3 +#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000 +#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000 +#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1 +#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200 +#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000 +#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11 +#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000 +#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18 +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000 +#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19 +#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1 +#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100 +#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000 +#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000 +#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70 +#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000 +#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000 +#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000 +#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG_VERSION__DIG_TYPE_MASK 0x1 +#define DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1 +#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2 +#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4 +#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8 +#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100 +#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK 0xff +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT 0x0 +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK 0xff +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK 0xffffffff +#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT 0x0 +#define DMCU_CTRL__RESET_UC_MASK 0x1 +#define DMCU_CTRL__RESET_UC__SHIFT 0x0 +#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2 +#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 +#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10 +#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x100 +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffff0000 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10 +#define DMCU_STATUS__UC_IN_RESET_MASK 0x1 +#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 +#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2 +#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 +#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4 +#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x20 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x20 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x40 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR_MASK 0x40 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x80 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x80 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800 +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800 +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000 +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000 +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000 +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000 +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000 +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_OCCURRED_MASK 0x40000000 +#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_OCCURRED__SHIFT 0x1e +#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_CLEAR_MASK 0x40000000 +#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_CLEAR__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x20 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x40 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x80 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x200 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x400 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x800 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCFEV0_VBLANK_INT_TO_UC_EN_MASK 0x80000000 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCFEV0_VBLANK_INT_TO_UC_EN__SHIFT 0x1f +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x80000000 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x1f +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff +#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff +#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x20 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x40 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x80 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x100 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x200 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x400 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x800 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x1000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x2000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x4000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x8000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x10000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x20000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x40000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x80000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x100000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x200000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x400000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x800000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x1000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x2000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x4000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x8000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10 +#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100 +#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000 +#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7 +#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100 +#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8 +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000 +#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10 +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000 +#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100 +#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8 +#define DP_CONFIG__DP_UDI_LANES_MASK 0x3 +#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000 +#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1 +#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80 +#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000 +#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78 +#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3 +#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00 +#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000 +#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000 +#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1 +#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0 +#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x10 +#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100 +#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000 +#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP_VID_N__DP_VID_N_MASK 0xffffff +#define DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP_VID_M__DP_VID_M_MASK 0xffffff +#define DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff +#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000 +#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000 +#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1 +#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff +#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000 +#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10 +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000 +#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4 +#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8 +#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000 +#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000 +#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3 +#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff +#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00 +#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000 +#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff +#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00 +#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000 +#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff +#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00 +#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000 +#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 +#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x3ff +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x8000 +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x10000 +#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1 +#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10 +#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100 +#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000 +#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000 +#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00 +#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000 +#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1 +#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2 +#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000 +#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000 +#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x7 +#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x3fff0 +#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x3fff +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3fff0000 +#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10 +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1 +#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10 +#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100 +#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000 +#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000 +#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000 +#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000 +#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000 +#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000 +#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000 +#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18 +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000 +#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1 +#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x10 +#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x20 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x40 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x80 +#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xffff0000 +#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff +#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff +#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff +#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000 +#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000 +#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000 +#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff +#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff +#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff +#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff +#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00 +#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000 +#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000 +#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1 +#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000 +#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000 +#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000 +#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000 +#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000 +#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000 +#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3 +#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100 +#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000 +#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1 +#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10 +#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100 +#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK 0x10000 +#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT 0x10 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff +#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0 +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK 0xff +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK 0xffffffff +#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT 0x0 +#define AUX_CONTROL__AUX_EN_MASK 0x1 +#define AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define AUX_CONTROL__AUX_RESET_MASK 0x10 +#define AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define AUX_CONTROL__AUX_RESET_DONE_MASK 0x20 +#define AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100 +#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000 +#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000 +#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000 +#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000 +#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000 +#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000 +#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000 +#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define AUX_CONTROL__SPARE_0_MASK 0x40000000 +#define AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define AUX_CONTROL__SPARE_1_MASK 0x80000000 +#define AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1 +#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4 +#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0 +#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000 +#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3 +#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc +#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400 +#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000 +#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000 +#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000 +#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000 +#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000 +#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000 +#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4 +#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40 +#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000 +#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1 +#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2 +#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80 +#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100 +#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200 +#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800 +#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000 +#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000 +#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e +#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1 +#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2 +#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80 +#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100 +#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200 +#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800 +#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000 +#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000 +#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000 +#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000 +#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1 +#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00 +#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000 +#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000 +#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00 +#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000 +#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000 +#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00 +#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000 +#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000 +#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff +#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1 +#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70 +#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000 +#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7 +#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00 +#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000 +#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000 +#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000 +#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000 +#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000 +#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1 +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0 +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00 +#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000 +#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1 +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0 +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0 +#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4 +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK 0xff +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT 0x0 +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK 0xffffffff +#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT 0x0 +#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xffffffff +#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xffffffff +#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xffffffff +#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xffffffff +#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xffffffff +#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xffffffff +#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xffffffff +#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xffffffff +#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xffffffff +#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xffffffff +#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK 0xffffffff +#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT 0x0 +#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK 0xffffffff +#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT 0x0 +#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK 0xffffffff +#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT 0x0 +#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK 0xffffffff +#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT 0x0 +#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK 0xffffffff +#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT 0x0 +#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK 0xffffffff +#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT 0x0 +#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK 0xffffffff +#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT 0x0 +#define DVO_ENABLE__DVO_ENABLE_MASK 0x1 +#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0 +#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30 +#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4 +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7 +#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0 +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000 +#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10 +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3 +#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0 +#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100 +#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8 +#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1 +#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0 +#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2 +#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1 +#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30 +#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4 +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100 +#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8 +#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000 +#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10 +#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000 +#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11 +#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000 +#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12 +#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000 +#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14 +#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000 +#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15 +#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000 +#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16 +#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000 +#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18 +#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000 +#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f +#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000 +#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10 +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff +#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0 +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff +#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 +#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK 0xff +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK 0xffffffff +#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT 0x0 +#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1 +#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0 +#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe +#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1 +#define FBC_CNTL__FBC_COMP_CLK_GATE_EN_MASK 0x100 +#define FBC_CNTL__FBC_COMP_CLK_GATE_EN__SHIFT 0x8 +#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000 +#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10 +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000 +#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19 +#define FBC_CNTL__FBC_EN_MASK 0x80000000 +#define FBC_CNTL__FBC_EN__SHIFT 0x1f +#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff +#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0 +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff +#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0 +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f +#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0 +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80 +#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7 +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00 +#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8 +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf +#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000 +#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000 +#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14 +#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1 +#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0 +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100 +#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8 +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200 +#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9 +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400 +#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800 +#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb +#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000 +#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10 +#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff +#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0 +#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 +#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8 +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000 +#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10 +#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000 +#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11 +#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000 +#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18 +#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff +#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0 +#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff +#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0 +#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff +#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0 +#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff +#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0 +#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff +#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0 +#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff +#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0 +#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff +#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0 +#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff +#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0 +#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff +#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0 +#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff +#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0 +#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff +#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0 +#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff +#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0 +#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff +#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0 +#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff +#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0 +#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff +#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0 +#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff +#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0 +#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff +#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0 +#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff +#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0xfff +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0xfff0000 +#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0xfff +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0xfff0000 +#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10 +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000 +#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10 +#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3 +#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0 +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8 +#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3 +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0 +#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4 +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300 +#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8 +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400 +#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800 +#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0xfff +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000 +#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff +#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0 +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff +#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0 +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff +#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0 +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff +#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3 +#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0 +#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4 +#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2 +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8 +#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3 +#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0 +#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4 +#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300 +#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8 +#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400 +#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa +#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800 +#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000 +#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc +#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT_MASK 0x2000 +#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT__SHIFT 0xd +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000 +#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10 +#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000 +#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14 +#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000 +#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15 +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1f000000 +#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18 +#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN_MASK 0x80000000 +#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN__SHIFT 0x1f +#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1 +#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff +#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000 +#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10 +#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1 +#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10 +#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0xf00 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x3000 +#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000 +#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000 +#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11 +#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000 +#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12 +#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000 +#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30 +#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800 +#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000 +#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000 +#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000 +#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000 +#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff +#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000 +#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff +#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000 +#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff +#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000 +#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10 +#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0 +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff +#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0 +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1 +#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000 +#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1 +#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0 +#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2 +#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1 +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10 +#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4 +#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x20 +#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5 +#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x40 +#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6 +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x100 +#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8 +#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x200 +#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9 +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000 +#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 +#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000 +#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000 +#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000 +#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000 +#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000 +#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10 +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3 +#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff +#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0 +#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff +#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0 +#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff +#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0 +#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff +#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0 +#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff +#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0 +#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 +#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 +#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 +#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 +#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 +#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 +#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10 +#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4 +#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20 +#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5 +#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000 +#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc +#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 +#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 +#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 +#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f +#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff +#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 +#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 +#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 +#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 +#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff +#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 +#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff +#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 +#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff +#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0 +#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000 +#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10 +#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000 +#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f +#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff +#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0 +#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 +#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10 +#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 +#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f +#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff +#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff +#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 +#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 +#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 +#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 +#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 +#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 +#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 +#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 +#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 +#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10 +#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 +#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000 +#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc +#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 +#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 +#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 +#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 +#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 +#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 +#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 +#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 +#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 +#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 +#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 +#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 +#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 +#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 +#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 +#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 +#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 +#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 +#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 +#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 +#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 +#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 +#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 +#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 +#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 +#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 +#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 +#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 +#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 +#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 +#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 +#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 +#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa +#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 +#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 +#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 +#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 +#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 +#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 +#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 +#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 +#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3 +#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000 +#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000 +#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3 +#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000 +#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000 +#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f +#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff +#define LB_DEBUG__LB_DEBUG__SHIFT 0x0 +#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff +#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0 +#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff +#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff +#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 +#define LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 +#define LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 +#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 +#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 +#define LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 +#define LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 +#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10 +#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4 +#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20 +#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5 +#define LBV_DATA_FORMAT__DITHER_EN_MASK 0x40 +#define LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6 +#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x80 +#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7 +#define LBV_DATA_FORMAT__PREFETCH_MASK 0x1000 +#define LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc +#define LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 +#define LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 +#define LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 +#define LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f +#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff +#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 +#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 +#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 +#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 +#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff +#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 +#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff +#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 +#define LBV_VLINE_START_END__VLINE_START_MASK 0x3fff +#define LBV_VLINE_START_END__VLINE_START__SHIFT 0x0 +#define LBV_VLINE_START_END__VLINE_END_MASK 0x7fff0000 +#define LBV_VLINE_START_END__VLINE_END__SHIFT 0x10 +#define LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000 +#define LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f +#define LBV_VLINE2_START_END__VLINE2_START_MASK 0x3fff +#define LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0 +#define LBV_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 +#define LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10 +#define LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 +#define LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f +#define LBV_V_COUNTER__V_COUNTER_MASK 0x7fff +#define LBV_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff +#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 +#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x7fff +#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0 +#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x7fff +#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0 +#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 +#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 +#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 +#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 +#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 +#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 +#define LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 +#define LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 +#define LBV_VLINE_STATUS__VLINE_ACK_MASK 0x10 +#define LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 +#define LBV_VLINE_STATUS__VLINE_STAT_MASK 0x1000 +#define LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc +#define LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 +#define LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 +#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 +#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 +#define LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 +#define LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 +#define LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 +#define LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 +#define LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 +#define LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 +#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 +#define LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 +#define LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 +#define LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 +#define LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 +#define LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 +#define LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 +#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 +#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 +#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 +#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 +#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 +#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 +#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 +#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 +#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 +#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 +#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 +#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 +#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 +#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 +#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 +#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 +#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 +#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 +#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 +#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 +#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 +#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 +#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 +#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa +#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 +#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 +#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 +#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 +#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 +#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 +#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 +#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 +#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 +#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 +#define LBV_DEBUG__LB_DEBUG_MASK 0xffffffff +#define LBV_DEBUG__LB_DEBUG__SHIFT 0x0 +#define LBV_DEBUG2__LB_DEBUG2_MASK 0xffffffff +#define LBV_DEBUG2__LB_DEBUG2__SHIFT 0x0 +#define LBV_DEBUG3__LB_DEBUG3_MASK 0xffffffff +#define LBV_DEBUG3__LB_DEBUG3__SHIFT 0x0 +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff +#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MVP_CONTROL1__MVP_EN_MASK 0x1 +#define MVP_CONTROL1__MVP_EN__SHIFT 0x0 +#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70 +#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200 +#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9 +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400 +#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa +#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000 +#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000 +#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10 +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000 +#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14 +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000 +#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18 +#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000 +#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000 +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000 +#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10 +#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4 +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100 +#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8 +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000 +#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc +#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000 +#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10 +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000 +#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14 +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000 +#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18 +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000 +#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff +#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000 +#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10 +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff +#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000 +#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000 +#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000 +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000 +#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff +#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0 +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000 +#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10 +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1 +#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0 +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10 +#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4 +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00 +#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000 +#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14 +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff +#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0 +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00 +#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8 +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000 +#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10 +#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000 +#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000 +#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000 +#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0 +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000 +#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10 +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff +#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0 +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1 +#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0 +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 +#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100 +#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14 +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000 +#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000 +#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000 +#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0 +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000 +#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4 +#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8 +#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20 +#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5 +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40 +#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6 +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80 +#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7 +#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00 +#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff +#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0 +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6 +#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6 +#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0 +#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe +#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0 +#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe +#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1 +#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000 +#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19 +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000 +#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a +#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000 +#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b +#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7 +#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0 +#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6 +#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200 +#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9 +#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400 +#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800 +#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000 +#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc +#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000 +#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000 +#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12 +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000 +#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13 +#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000 +#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0 +#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2 +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8 +#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000 +#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc +#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000 +#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 +#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define SCL_MODE__SCL_MODE_MASK 0x3 +#define SCL_MODE__SCL_MODE__SHIFT 0x0 +#define SCL_MODE__SCL_PSCL_EN_MASK 0x10 +#define SCL_MODE__SCL_PSCL_EN__SHIFT 0x4 +#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 +#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 +#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00 +#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8 +#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 +#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10 +#define SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4 +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3 +#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 +#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 +#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff +#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 +#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1 +#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0 +#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff +#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 +#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 +#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 +#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 +#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 +#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 +#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 +#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 +#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 +#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 +#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10 +#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000 +#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 +#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000 +#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 +#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff +#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0 +#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000 +#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10 +#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff +#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 +#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 +#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff +#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 +#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000 +#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 +#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 +#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 +#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 +#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff +#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 +#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 +#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 +#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 +#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 +#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 +#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 +#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 +#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3 +#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff +#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff +#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x3 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x7f00 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x30000 +#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 +#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define SCLV_MODE__SCL_MODE_MASK 0x1 +#define SCLV_MODE__SCL_MODE__SHIFT 0x0 +#define SCLV_MODE__SCL_MODE_C_MASK 0x2 +#define SCLV_MODE__SCL_MODE_C__SHIFT 0x1 +#define SCLV_MODE__SCL_PSCL_EN_MASK 0x10 +#define SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4 +#define SCLV_MODE__SCL_PSCL_EN_C_MASK 0x20 +#define SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5 +#define SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x300 +#define SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x70 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x700 +#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x7000 +#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc +#define SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 +#define SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10 +#define SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4 +#define SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x100 +#define SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8 +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 +#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 +#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 +#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff +#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 +#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x3ffffff +#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0xffffff +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0xf000000 +#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 +#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 +#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff +#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x3ffffff +#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0xffffff +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x7000000 +#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 +#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 +#define SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 +#define SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 +#define SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 +#define SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 +#define SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 +#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 +#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 +#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 +#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 +#define SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff +#define SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 +#define SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0 +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10 +#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x1fff +#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 +#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1fff0000 +#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 +#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x3fff +#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0 +#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10 +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x3fff +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0 +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3fff0000 +#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10 +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x1fff +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0 +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1fff0000 +#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10 +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 +#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 +#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 +#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 +#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 +#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 +#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff +#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 +#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 +#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 +#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0xffffff +#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0xf000000 +#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18 +#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0xffffff +#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0 +#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0xf000000 +#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18 +#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 +#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 +#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 +#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 +#define SCLV_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 +#define SCLV_DEBUG2__SCL_DEBUG2__SHIFT 0x3 +#define SCLV_DEBUG__SCL_DEBUG_MASK 0xffffffff +#define SCLV_DEBUG__SCL_DEBUG__SHIFT 0x0 +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff +#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x1 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x2 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x10000 +#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10 +#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x3 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x300 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x10000 +#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10 +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0xffff +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0 +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xffff0000 +#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10 +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0xffff +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0 +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xffff0000 +#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10 +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0xffff +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0 +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xffff0000 +#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10 +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0xffff +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0 +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xffff0000 +#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10 +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0xffff +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0 +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xffff0000 +#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10 +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0xffff +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0 +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xffff0000 +#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10 +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0xffff +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0 +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xffff0000 +#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10 +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0xffff +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0 +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xffff0000 +#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10 +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0xffff +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0 +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xffff0000 +#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10 +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0xffff +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0 +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xffff0000 +#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10 +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0xffff +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0 +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xffff0000 +#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10 +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0xffff +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0 +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xffff0000 +#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10 +#define PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x3 +#define PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0 +#define PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0xffff +#define PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0 +#define PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xffff0000 +#define PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10 +#define PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0xffff +#define PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0 +#define PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xffff0000 +#define PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10 +#define PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0xffff +#define PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0 +#define PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xffff0000 +#define PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10 +#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x7 +#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0xffff +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xffff0000 +#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10 +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0xffff +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0 +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xffff0000 +#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10 +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0xffff +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0 +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xffff0000 +#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10 +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0xffff +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0 +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xffff0000 +#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10 +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0xffff +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0 +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xffff0000 +#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10 +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0xffff +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0 +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xffff0000 +#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10 +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0xffff +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0 +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xffff0000 +#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10 +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0xffff +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0 +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xffff0000 +#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10 +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0xffff +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0 +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xffff0000 +#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10 +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0xffff +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0 +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xffff0000 +#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10 +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0xffff +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0 +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xffff0000 +#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10 +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0xffff +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0 +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xffff0000 +#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10 +#define DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x3 +#define DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0 +#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x100 +#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8 +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0xfff +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0 +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0xfff000 +#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0xfff +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0 +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0xfff000 +#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0xfff +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0 +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0xfff000 +#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x3f00000 +#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 +#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK 0x3 +#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT 0x0 +#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK 0xff +#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT 0x0 +#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK 0x7ffff +#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT 0x0 +#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK 0x7 +#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK 0x3ffff +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK 0xffff +#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 +#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK 0x3ffff +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 +#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 +#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff +#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK 0xffff +#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 +#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0xff +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000 +#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b +#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x1 +#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0 +#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x2 +#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1 +#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x100 +#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8 +#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x200 +#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9 +#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x10000 +#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10 +#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x20000 +#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11 +#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x1000000 +#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18 +#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x2000000 +#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x1 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x2 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x100 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x200 +#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9 +#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x1 +#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0 +#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x2 +#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1 +#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0xff +#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0 +#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0xffff +#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0 +#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0xffff +#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0 +#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xffff0000 +#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10 +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x3ff +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0 +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0xffc00 +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3ff00000 +#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14 +#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x3 +#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0 +#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x4000000 +#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x1e +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x20 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0xc0 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0xf00 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x1000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x6000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x78000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x80000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x300000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x400000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x3800000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x4000000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x8000000 +#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b +#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0xffff +#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0 +#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xffff0000 +#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10 +#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0xffff +#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0 +#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xffff0000 +#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10 +#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0xffff +#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0 +#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xffff0000 +#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10 +#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE_MASK 0x1 +#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__SHIFT 0x0 +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX_MASK 0xff +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX__SHIFT 0x0 +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA_MASK 0xffffffff +#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA__SHIFT 0x0 +#define UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 +#define UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 +#define UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 +#define UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 +#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc +#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 +#define UNP_GRPH_CONTROL__GRPH_Z_MASK 0x30 +#define UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4 +#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0xc0 +#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6 +#define UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 +#define UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 +#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x1800 +#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb +#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0xe000 +#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd +#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 +#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 +#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 +#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 +#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0xc0000 +#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12 +#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 +#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 +#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 +#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 +#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000 +#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d +#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 +#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f +#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0xc0 +#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6 +#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x1800 +#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb +#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0xe000 +#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd +#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0xc0000 +#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12 +#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000 +#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d +#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x7 +#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0 +#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 +#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 +#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 +#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 +#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 +#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 +#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 +#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff +#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x7fff +#define UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0 +#define UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x7fff +#define UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0 +#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x3fff +#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0 +#define UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x3fff +#define UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0 +#define UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x3fff +#define UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0 +#define UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x3fff +#define UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0 +#define UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x3fff +#define UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0 +#define UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x7fff +#define UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0 +#define UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x7fff +#define UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0 +#define UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x7fff +#define UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0 +#define UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x7fff +#define UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 +#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 +#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 +#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 +#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 +#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 +#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c +#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0xff +#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0 +#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0xff00 +#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8 +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xffffff00 +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8 +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xffffff00 +#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8 +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0xff +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0 +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0xff +#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0 +#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1 +#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0 +#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e +#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1 +#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0 +#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5 +#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00 +#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9 +#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000 +#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14 +#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000 +#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15 +#define UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK 0x1 +#define UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT 0x0 +#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK 0x1e +#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT 0x1 +#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK 0x1e0 +#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT 0x5 +#define UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK 0x7fe00 +#define UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT 0x9 +#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK 0x100000 +#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT 0x14 +#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK 0x200000 +#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT 0x15 +#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x3f +#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0 +#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0xff00 +#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8 +#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK 0x3f +#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT 0x0 +#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK 0xff00 +#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT 0x8 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 +#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 +#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x30 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x100 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x3000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x40000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x80000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 +#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c +#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x1 +#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0 +#define UNP_FLIP_CONTROL__UNP_DEBUG_SG_MASK 0xfffffffc +#define UNP_FLIP_CONTROL__UNP_DEBUG_SG__SHIFT 0x2 +#define UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x1 +#define UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0 +#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x1c +#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2 +#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x300 +#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8 +#define UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xffffffff +#define UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0 +#define UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xffffffff +#define UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0 +#define UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xffffffff +#define UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0 +#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x1f0 +#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4 +#define UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x7 +#define UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0 +#define UNP_HW_ROTATION__PIXEL_DROP_MASK 0x10 +#define UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4 +#define UNP_HW_ROTATION__BUFFER_MODE_MASK 0x100 +#define UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8 +#define UNP_DEBUG__UNP_DEBUG_MASK 0xffffffff +#define UNP_DEBUG__UNP_DEBUG__SHIFT 0x0 +#define UNP_DEBUG2__UNP_DEBUG2_MASK 0xffffffff +#define UNP_DEBUG2__UNP_DEBUG2__SHIFT 0x0 +#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG_MASK 0xffff +#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG__SHIFT 0x0 +#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG_MASK 0xffff0000 +#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG__SHIFT 0x10 +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK 0xff +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK 0xffffffff +#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT 0x0 +#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1 +#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_WT__VGA_RAM_EN_MASK 0x2 +#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_WT__VGA_CKSEL_MASK 0xc +#define GENMO_WT__VGA_CKSEL__SHIFT 0x2 +#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20 +#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 +#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 +#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 +#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1 +#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 +#define GENMO_RD__VGA_RAM_EN_MASK 0x2 +#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 +#define GENMO_RD__VGA_CKSEL_MASK 0xc +#define GENMO_RD__VGA_CKSEL__SHIFT 0x2 +#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20 +#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 +#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 +#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 +#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 +#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 +#define GENENB__BLK_IO_BASE_MASK 0xff +#define GENENB__BLK_IO_BASE__SHIFT 0x0 +#define GENFC_WT__VSYNC_SEL_W_MASK 0x8 +#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 +#define GENFC_RD__VSYNC_SEL_R_MASK 0x8 +#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 +#define GENS0__SENSE_SWITCH_MASK 0x10 +#define GENS0__SENSE_SWITCH__SHIFT 0x4 +#define GENS0__CRT_INTR_MASK 0x80 +#define GENS0__CRT_INTR__SHIFT 0x7 +#define GENS1__NO_DISPLAY_MASK 0x1 +#define GENS1__NO_DISPLAY__SHIFT 0x0 +#define GENS1__VGA_VSTATUS_MASK 0x8 +#define GENS1__VGA_VSTATUS__SHIFT 0x3 +#define GENS1__PIXEL_READ_BACK_MASK 0x30 +#define GENS1__PIXEL_READ_BACK__SHIFT 0x4 +#define DAC_DATA__DAC_DATA_MASK 0x3f +#define DAC_DATA__DAC_DATA__SHIFT 0x0 +#define DAC_MASK__DAC_MASK_MASK 0xff +#define DAC_MASK__DAC_MASK__SHIFT 0x0 +#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff +#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 +#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff +#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 +#define SEQ8_IDX__SEQ_IDX_MASK 0x7 +#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 +#define SEQ8_DATA__SEQ_DATA_MASK 0xff +#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 +#define SEQ00__SEQ_RST0B_MASK 0x1 +#define SEQ00__SEQ_RST0B__SHIFT 0x0 +#define SEQ00__SEQ_RST1B_MASK 0x2 +#define SEQ00__SEQ_RST1B__SHIFT 0x1 +#define SEQ01__SEQ_DOT8_MASK 0x1 +#define SEQ01__SEQ_DOT8__SHIFT 0x0 +#define SEQ01__SEQ_SHIFT2_MASK 0x4 +#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 +#define SEQ01__SEQ_PCLKBY2_MASK 0x8 +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 +#define SEQ01__SEQ_SHIFT4_MASK 0x10 +#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 +#define SEQ01__SEQ_MAXBW_MASK 0x20 +#define SEQ01__SEQ_MAXBW__SHIFT 0x5 +#define SEQ02__SEQ_MAP0_EN_MASK 0x1 +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 +#define SEQ02__SEQ_MAP1_EN_MASK 0x2 +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 +#define SEQ02__SEQ_MAP2_EN_MASK 0x4 +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 +#define SEQ02__SEQ_MAP3_EN_MASK 0x8 +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B1_MASK 0x1 +#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 +#define SEQ03__SEQ_FONT_B2_MASK 0x2 +#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 +#define SEQ03__SEQ_FONT_A1_MASK 0x4 +#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 +#define SEQ03__SEQ_FONT_A2_MASK 0x8 +#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B0_MASK 0x10 +#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 +#define SEQ03__SEQ_FONT_A0_MASK 0x20 +#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 +#define SEQ04__SEQ_256K_MASK 0x2 +#define SEQ04__SEQ_256K__SHIFT 0x1 +#define SEQ04__SEQ_ODDEVEN_MASK 0x4 +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 +#define SEQ04__SEQ_CHAIN_MASK 0x8 +#define SEQ04__SEQ_CHAIN__SHIFT 0x3 +#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f +#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 +#define CRTC8_DATA__VCRTC_DATA_MASK 0xff +#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 +#define CRT00__H_TOTAL_MASK 0xff +#define CRT00__H_TOTAL__SHIFT 0x0 +#define CRT01__H_DISP_END_MASK 0xff +#define CRT01__H_DISP_END__SHIFT 0x0 +#define CRT02__H_BLANK_START_MASK 0xff +#define CRT02__H_BLANK_START__SHIFT 0x0 +#define CRT03__H_BLANK_END_MASK 0x1f +#define CRT03__H_BLANK_END__SHIFT 0x0 +#define CRT03__H_DE_SKEW_MASK 0x60 +#define CRT03__H_DE_SKEW__SHIFT 0x5 +#define CRT03__CR10CR11_R_DIS_B_MASK 0x80 +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 +#define CRT04__H_SYNC_START_MASK 0xff +#define CRT04__H_SYNC_START__SHIFT 0x0 +#define CRT05__H_SYNC_END_MASK 0x1f +#define CRT05__H_SYNC_END__SHIFT 0x0 +#define CRT05__H_SYNC_SKEW_MASK 0x60 +#define CRT05__H_SYNC_SKEW__SHIFT 0x5 +#define CRT05__H_BLANK_END_B5_MASK 0x80 +#define CRT05__H_BLANK_END_B5__SHIFT 0x7 +#define CRT06__V_TOTAL_MASK 0xff +#define CRT06__V_TOTAL__SHIFT 0x0 +#define CRT07__V_TOTAL_B8_MASK 0x1 +#define CRT07__V_TOTAL_B8__SHIFT 0x0 +#define CRT07__V_DISP_END_B8_MASK 0x2 +#define CRT07__V_DISP_END_B8__SHIFT 0x1 +#define CRT07__V_SYNC_START_B8_MASK 0x4 +#define CRT07__V_SYNC_START_B8__SHIFT 0x2 +#define CRT07__V_BLANK_START_B8_MASK 0x8 +#define CRT07__V_BLANK_START_B8__SHIFT 0x3 +#define CRT07__LINE_CMP_B8_MASK 0x10 +#define CRT07__LINE_CMP_B8__SHIFT 0x4 +#define CRT07__V_TOTAL_B9_MASK 0x20 +#define CRT07__V_TOTAL_B9__SHIFT 0x5 +#define CRT07__V_DISP_END_B9_MASK 0x40 +#define CRT07__V_DISP_END_B9__SHIFT 0x6 +#define CRT07__V_SYNC_START_B9_MASK 0x80 +#define CRT07__V_SYNC_START_B9__SHIFT 0x7 +#define CRT08__ROW_SCAN_START_MASK 0x1f +#define CRT08__ROW_SCAN_START__SHIFT 0x0 +#define CRT08__BYTE_PAN_MASK 0x60 +#define CRT08__BYTE_PAN__SHIFT 0x5 +#define CRT09__MAX_ROW_SCAN_MASK 0x1f +#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 +#define CRT09__V_BLANK_START_B9_MASK 0x20 +#define CRT09__V_BLANK_START_B9__SHIFT 0x5 +#define CRT09__LINE_CMP_B9_MASK 0x40 +#define CRT09__LINE_CMP_B9__SHIFT 0x6 +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80 +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 +#define CRT0A__CURSOR_START_MASK 0x1f +#define CRT0A__CURSOR_START__SHIFT 0x0 +#define CRT0A__CURSOR_DISABLE_MASK 0x20 +#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 +#define CRT0B__CURSOR_END_MASK 0x1f +#define CRT0B__CURSOR_END__SHIFT 0x0 +#define CRT0B__CURSOR_SKEW_MASK 0x60 +#define CRT0B__CURSOR_SKEW__SHIFT 0x5 +#define CRT0C__DISP_START_MASK 0xff +#define CRT0C__DISP_START__SHIFT 0x0 +#define CRT0D__DISP_START_MASK 0xff +#define CRT0D__DISP_START__SHIFT 0x0 +#define CRT0E__CURSOR_LOC_HI_MASK 0xff +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 +#define CRT0F__CURSOR_LOC_LO_MASK 0xff +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 +#define CRT10__V_SYNC_START_MASK 0xff +#define CRT10__V_SYNC_START__SHIFT 0x0 +#define CRT11__V_SYNC_END_MASK 0xf +#define CRT11__V_SYNC_END__SHIFT 0x0 +#define CRT11__V_INTR_CLR_MASK 0x10 +#define CRT11__V_INTR_CLR__SHIFT 0x4 +#define CRT11__V_INTR_EN_MASK 0x20 +#define CRT11__V_INTR_EN__SHIFT 0x5 +#define CRT11__SEL5_REFRESH_CYC_MASK 0x40 +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 +#define CRT11__C0T7_WR_ONLY_MASK 0x80 +#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 +#define CRT12__V_DISP_END_MASK 0xff +#define CRT12__V_DISP_END__SHIFT 0x0 +#define CRT13__DISP_PITCH_MASK 0xff +#define CRT13__DISP_PITCH__SHIFT 0x0 +#define CRT14__UNDRLN_LOC_MASK 0x1f +#define CRT14__UNDRLN_LOC__SHIFT 0x0 +#define CRT14__ADDR_CNT_BY4_MASK 0x20 +#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 +#define CRT14__DOUBLE_WORD_MASK 0x40 +#define CRT14__DOUBLE_WORD__SHIFT 0x6 +#define CRT15__V_BLANK_START_MASK 0xff +#define CRT15__V_BLANK_START__SHIFT 0x0 +#define CRT16__V_BLANK_END_MASK 0xff +#define CRT16__V_BLANK_END__SHIFT 0x0 +#define CRT17__RA0_AS_A13B_MASK 0x1 +#define CRT17__RA0_AS_A13B__SHIFT 0x0 +#define CRT17__RA1_AS_A14B_MASK 0x2 +#define CRT17__RA1_AS_A14B__SHIFT 0x1 +#define CRT17__VCOUNT_BY2_MASK 0x4 +#define CRT17__VCOUNT_BY2__SHIFT 0x2 +#define CRT17__ADDR_CNT_BY2_MASK 0x8 +#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 +#define CRT17__WRAP_A15TOA0_MASK 0x20 +#define CRT17__WRAP_A15TOA0__SHIFT 0x5 +#define CRT17__BYTE_MODE_MASK 0x40 +#define CRT17__BYTE_MODE__SHIFT 0x6 +#define CRT17__CRTC_SYNC_EN_MASK 0x80 +#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 +#define CRT18__LINE_CMP_MASK 0xff +#define CRT18__LINE_CMP__SHIFT 0x0 +#define CRT1E__GRPH_DEC_RD1_MASK 0x2 +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 +#define CRT1F__GRPH_DEC_RD0_MASK 0xff +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 +#define CRT22__GRPH_LATCH_DATA_MASK 0xff +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 +#define GRPH8_IDX__GRPH_IDX_MASK 0xf +#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 +#define GRPH8_DATA__GRPH_DATA_MASK 0xff +#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET0_MASK 0x1 +#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET1_MASK 0x2 +#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 +#define GRA00__GRPH_SET_RESET2_MASK 0x4 +#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 +#define GRA00__GRPH_SET_RESET3_MASK 0x8 +#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1 +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2 +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4 +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8 +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 +#define GRA02__GRPH_CCOMP_MASK 0xf +#define GRA02__GRPH_CCOMP__SHIFT 0x0 +#define GRA03__GRPH_ROTATE_MASK 0x7 +#define GRA03__GRPH_ROTATE__SHIFT 0x0 +#define GRA03__GRPH_FN_SEL_MASK 0x18 +#define GRA03__GRPH_FN_SEL__SHIFT 0x3 +#define GRA04__GRPH_RMAP_MASK 0x3 +#define GRA04__GRPH_RMAP__SHIFT 0x0 +#define GRA05__GRPH_WRITE_MODE_MASK 0x3 +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 +#define GRA05__GRPH_READ1_MASK 0x8 +#define GRA05__GRPH_READ1__SHIFT 0x3 +#define GRA05__CGA_ODDEVEN_MASK 0x10 +#define GRA05__CGA_ODDEVEN__SHIFT 0x4 +#define GRA05__GRPH_OES_MASK 0x20 +#define GRA05__GRPH_OES__SHIFT 0x5 +#define GRA05__GRPH_PACK_MASK 0x40 +#define GRA05__GRPH_PACK__SHIFT 0x6 +#define GRA06__GRPH_GRAPHICS_MASK 0x1 +#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 +#define GRA06__GRPH_ODDEVEN_MASK 0x2 +#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 +#define GRA06__GRPH_ADRSEL_MASK 0xc +#define GRA06__GRPH_ADRSEL__SHIFT 0x2 +#define GRA07__GRPH_XCARE0_MASK 0x1 +#define GRA07__GRPH_XCARE0__SHIFT 0x0 +#define GRA07__GRPH_XCARE1_MASK 0x2 +#define GRA07__GRPH_XCARE1__SHIFT 0x1 +#define GRA07__GRPH_XCARE2_MASK 0x4 +#define GRA07__GRPH_XCARE2__SHIFT 0x2 +#define GRA07__GRPH_XCARE3_MASK 0x8 +#define GRA07__GRPH_XCARE3__SHIFT 0x3 +#define GRA08__GRPH_BMSK_MASK 0xff +#define GRA08__GRPH_BMSK__SHIFT 0x0 +#define ATTRX__ATTR_IDX_MASK 0x1f +#define ATTRX__ATTR_IDX__SHIFT 0x0 +#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20 +#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 +#define ATTRDW__ATTR_DATA_MASK 0xff +#define ATTRDW__ATTR_DATA__SHIFT 0x0 +#define ATTRDR__ATTR_DATA_MASK 0xff +#define ATTRDR__ATTR_DATA__SHIFT 0x0 +#define ATTR00__ATTR_PAL_MASK 0x3f +#define ATTR00__ATTR_PAL__SHIFT 0x0 +#define ATTR01__ATTR_PAL_MASK 0x3f +#define ATTR01__ATTR_PAL__SHIFT 0x0 +#define ATTR02__ATTR_PAL_MASK 0x3f +#define ATTR02__ATTR_PAL__SHIFT 0x0 +#define ATTR03__ATTR_PAL_MASK 0x3f +#define ATTR03__ATTR_PAL__SHIFT 0x0 +#define ATTR04__ATTR_PAL_MASK 0x3f +#define ATTR04__ATTR_PAL__SHIFT 0x0 +#define ATTR05__ATTR_PAL_MASK 0x3f +#define ATTR05__ATTR_PAL__SHIFT 0x0 +#define ATTR06__ATTR_PAL_MASK 0x3f +#define ATTR06__ATTR_PAL__SHIFT 0x0 +#define ATTR07__ATTR_PAL_MASK 0x3f +#define ATTR07__ATTR_PAL__SHIFT 0x0 +#define ATTR08__ATTR_PAL_MASK 0x3f +#define ATTR08__ATTR_PAL__SHIFT 0x0 +#define ATTR09__ATTR_PAL_MASK 0x3f +#define ATTR09__ATTR_PAL__SHIFT 0x0 +#define ATTR0A__ATTR_PAL_MASK 0x3f +#define ATTR0A__ATTR_PAL__SHIFT 0x0 +#define ATTR0B__ATTR_PAL_MASK 0x3f +#define ATTR0B__ATTR_PAL__SHIFT 0x0 +#define ATTR0C__ATTR_PAL_MASK 0x3f +#define ATTR0C__ATTR_PAL__SHIFT 0x0 +#define ATTR0D__ATTR_PAL_MASK 0x3f +#define ATTR0D__ATTR_PAL__SHIFT 0x0 +#define ATTR0E__ATTR_PAL_MASK 0x3f +#define ATTR0E__ATTR_PAL__SHIFT 0x0 +#define ATTR0F__ATTR_PAL_MASK 0x3f +#define ATTR0F__ATTR_PAL__SHIFT 0x0 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x1 +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 +#define ATTR10__ATTR_MONO_EN_MASK 0x2 +#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 +#define ATTR10__ATTR_LGRPH_EN_MASK 0x4 +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 +#define ATTR10__ATTR_BLINK_EN_MASK 0x8 +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 +#define ATTR10__ATTR_PANTOPONLY_MASK 0x20 +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 +#define ATTR10__ATTR_PCLKBY2_MASK 0x40 +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 +#define ATTR10__ATTR_CSEL_EN_MASK 0x80 +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 +#define ATTR11__ATTR_OVSC_MASK 0xff +#define ATTR11__ATTR_OVSC__SHIFT 0x0 +#define ATTR12__ATTR_MAP_EN_MASK 0xf +#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 +#define ATTR12__ATTR_VSMUX_MASK 0x30 +#define ATTR12__ATTR_VSMUX__SHIFT 0x4 +#define ATTR13__ATTR_PPAN_MASK 0xf +#define ATTR13__ATTR_PPAN__SHIFT 0x0 +#define ATTR14__ATTR_CSEL1_MASK 0x3 +#define ATTR14__ATTR_CSEL1__SHIFT 0x0 +#define ATTR14__ATTR_CSEL2_MASK 0xc +#define ATTR14__ATTR_CSEL2__SHIFT 0x2 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800 +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000 +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000 +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000 +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000 +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000 +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000 +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000 +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000 +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 +#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff +#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3 +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0xf000 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000 +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000 +#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000 +#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000 +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000 +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff +#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0 +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff +#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff +#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0 +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff +#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000 +#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000 +#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c +#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff +#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0 +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000 +#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000 +#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10 +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f +#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7 +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000 +#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10 +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff +#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff +#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00 +#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8 +#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000 +#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc +#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000 +#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000 +#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10 +#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff +#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0 +#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000 +#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10 +#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000 +#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12 +#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000 +#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2 +#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8 +#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3 +#define PLL_IDCLK_CNTL__PLL_IDCLK_EN_MASK 0x10 +#define PLL_IDCLK_CNTL__PLL_IDCLK_EN__SHIFT 0x4 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000 +#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10 +#define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000 +#define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14 +#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000 +#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16 +#define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000 +#define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18 +#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR_MASK 0xc000000 +#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR__SHIFT 0x1a +#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR_MASK 0x30000000 +#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR__SHIFT 0x1c +#define PLL_CNTL__PLL_RESET_MASK 0x1 +#define PLL_CNTL__PLL_RESET__SHIFT 0x0 +#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2 +#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1 +#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4 +#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2 +#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8 +#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3 +#define PLL_CNTL__PLL_VCOREF_MASK 0x30 +#define PLL_CNTL__PLL_VCOREF__SHIFT 0x4 +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40 +#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6 +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80 +#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7 +#define PLL_CNTL__PLL_CALREF_MASK 0x300 +#define PLL_CNTL__PLL_CALREF__SHIFT 0x8 +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400 +#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa +#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800 +#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000 +#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd +#define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000 +#define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe +#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000 +#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10 +#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000 +#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13 +#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000 +#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14 +#define PLL_CNTL__PLL_LOCKED_MASK 0x200000 +#define PLL_CNTL__PLL_LOCKED__SHIFT 0x15 +#define PLL_CNTL__PLL_REFCLK_RECV_EN_MASK 0x400000 +#define PLL_CNTL__PLL_REFCLK_RECV_EN__SHIFT 0x16 +#define PLL_CNTL__PLL_REFCLK_RECV_SEL_MASK 0x800000 +#define PLL_CNTL__PLL_REFCLK_RECV_SEL__SHIFT 0x17 +#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000 +#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18 +#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000 +#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a +#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f +#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0 +#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60 +#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5 +#define PLL_ANALOG__PLL_CP_MASK 0xf00 +#define PLL_ANALOG__PLL_CP__SHIFT 0x8 +#define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000 +#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc +#define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000 +#define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15 +#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000 +#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18 +#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff +#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0 +#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000 +#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14 +#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000 +#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a +#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000 +#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100 +#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8 +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1 +#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0 +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0 +#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4 +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00 +#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000 +#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1 +#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0 +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1 +#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0 +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100 +#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8 +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000 +#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10 +#define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1 +#define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0 +#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2 +#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1 +#define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00 +#define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8 +#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL_MASK 0xf0000 +#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL__SHIFT 0x10 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF_MASK 0x700000 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF__SHIFT 0x14 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB_MASK 0x3800000 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB__SHIFT 0x17 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS_MASK 0xc000000 +#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS__SHIFT 0x1a +#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN_MASK 0x10000000 +#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN__SHIFT 0x1c +#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1 +#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0 +#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e +#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1 +#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0 +#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5 +#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM_MASK 0x3e00 +#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM__SHIFT 0x9 +#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV_MASK 0x1c000 +#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV__SHIFT 0xe +#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL_MASK 0x20000 +#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL__SHIFT 0x11 +#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN_MASK 0x40000 +#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN__SHIFT 0x12 +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff +#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0 +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff +#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0 +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff +#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000 +#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000 +#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000 +#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 +#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10 +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f +#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000 +#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18 +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f +#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000 +#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18 +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f +#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000 +#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18 +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1 +#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0 +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0 +#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4 +#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED_MASK 0x1 +#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED__SHIFT 0x0 +#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED_MASK 0x2 +#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED__SHIFT 0x1 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING_MASK 0x4 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING__SHIFT 0x2 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE_MASK 0x18 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE__SHIFT 0x3 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE_MASK 0x20 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE__SHIFT 0x5 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ_MASK 0x40 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ__SHIFT 0x6 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK_MASK 0x80 +#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK__SHIFT 0x7 +#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS_MASK 0xffff +#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS__SHIFT 0x0 +#define PPLL_STATUS_DEBUG__PLL_UNLOCK_MASK 0x10000 +#define PPLL_STATUS_DEBUG__PLL_UNLOCK__SHIFT 0x10 +#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT_MASK 0x1e0000 +#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT__SHIFT 0x11 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB_MASK 0x1000000 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB__SHIFT 0x18 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S_MASK 0x2000000 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S__SHIFT 0x19 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V_MASK 0x4000000 +#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V__SHIFT 0x1a +#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK 0x1f +#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT 0x0 +#define PPLL_SPARE0__PLL_SPARE0_MASK 0xffffffff +#define PPLL_SPARE0__PLL_SPARE0__SHIFT 0x0 +#define PPLL_SPARE1__PLL_SPARE1_MASK 0xffffffff +#define PPLL_SPARE1__PLL_SPARE1__SHIFT 0x0 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000 +#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000 +#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000 +#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000 +#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0xf000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0xf0000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000 +#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17 +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000 +#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18 +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000 +#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000 +#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0 +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2 +#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1 +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0xc +#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000 +#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000 +#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000 +#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0 +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc +#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000 +#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff +#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000 +#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000 +#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19 +#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW_MASK 0x10000000 +#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW__SHIFT 0x1c +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000 +#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000 +#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a +#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff +#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0 +#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN_MASK 0x1 +#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN__SHIFT 0x0 +#define UNIPHY_TMDP_REG0__ICALRA_MODE_MASK 0x2 +#define UNIPHY_TMDP_REG0__ICALRA_MODE__SHIFT 0x1 +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG_MASK 0x7fc +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG__SHIFT 0x2 +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG_MASK 0xff800 +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG__SHIFT 0xb +#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL_MASK 0x100000 +#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL__SHIFT 0x14 +#define UNIPHY_TMDP_REG0__ITXA_PCALEN_MASK 0x200000 +#define UNIPHY_TMDP_REG0__ITXA_PCALEN__SHIFT 0x15 +#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN_MASK 0x400000 +#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN__SHIFT 0x16 +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN_MASK 0x800000 +#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN__SHIFT 0x17 +#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL_MASK 0x3000000 +#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL__SHIFT 0x18 +#define UNIPHY_TMDP_REG0__ITXA_VSCALEN_MASK 0x4000000 +#define UNIPHY_TMDP_REG0__ITXA_VSCALEN__SHIFT 0x1a +#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL_MASK 0x78000000 +#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL__SHIFT 0x1b +#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN_MASK 0x80000000 +#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN__SHIFT 0x1f +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST_MASK 0x1f +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST__SHIFT 0x0 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ_MASK 0x1e0 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ__SHIFT 0x5 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ_MASK 0x1e00 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ__SHIFT 0x9 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ_MASK 0x1e000 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ__SHIFT 0xd +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN_MASK 0x20000 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN__SHIFT 0x11 +#define UNIPHY_TMDP_REG1__ITXA_IOCNTL_MASK 0xffc0000 +#define UNIPHY_TMDP_REG1__ITXA_IOCNTL__SHIFT 0x12 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL_MASK 0x10000000 +#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL__SHIFT 0x1c +#define UNIPHY_TMDP_REG1__ITX_EDPSEL_MASK 0xe0000000 +#define UNIPHY_TMDP_REG1__ITX_EDPSEL__SHIFT 0x1d +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN_MASK 0x1 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN__SHIFT 0x0 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN_MASK 0x2 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN__SHIFT 0x1 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_MASK 0x3c +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET__SHIFT 0x2 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN_MASK 0x40 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN__SHIFT 0x6 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_MASK 0x3f80 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE__SHIFT 0x7 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET_MASK 0x4000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET__SHIFT 0xe +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN_MASK 0x10000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN__SHIFT 0x10 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN_MASK 0x20000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN__SHIFT 0x11 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_MASK 0x3c0000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET__SHIFT 0x12 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN_MASK 0x400000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN__SHIFT 0x16 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_MASK 0x3f800000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE__SHIFT 0x17 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET_MASK 0x40000000 +#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET__SHIFT 0x1e +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN_MASK 0x1 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN__SHIFT 0x0 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN_MASK 0x2 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN__SHIFT 0x1 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_MASK 0x3c +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET__SHIFT 0x2 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN_MASK 0x40 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN__SHIFT 0x6 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_MASK 0x3f80 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE__SHIFT 0x7 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET_MASK 0x4000 +#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET__SHIFT 0xe +#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ_MASK 0xf8000 +#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ__SHIFT 0xf +#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL_MASK 0x1f00000 +#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL__SHIFT 0x14 +#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL_MASK 0x3e000000 +#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL__SHIFT 0x19 +#define UNIPHY_TMDP_REG4__RESERVED_MASK 0x3fffff +#define UNIPHY_TMDP_REG4__RESERVED__SHIFT 0x0 +#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF_MASK 0x7fc00000 +#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF__SHIFT 0x16 +#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT_MASK 0x1 +#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT__SHIFT 0x0 +#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE_MASK 0x2 +#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE__SHIFT 0x1 +#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT_MASK 0x4 +#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT__SHIFT 0x2 +#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE_MASK 0x8 +#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE__SHIFT 0x3 +#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT_MASK 0x10 +#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT__SHIFT 0x4 +#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE_MASK 0x20 +#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE__SHIFT 0x5 +#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT_MASK 0x40 +#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT__SHIFT 0x6 +#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE_MASK 0x80 +#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE__SHIFT 0x7 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_MASK 0x1ff00 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN__SHIFT 0x8 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE_MASK 0x20000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE__SHIFT 0x11 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR_MASK 0x40000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR__SHIFT 0x12 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_MASK 0x780000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP__SHIFT 0x13 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE_MASK 0x800000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE__SHIFT 0x17 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR_MASK 0x1000000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR__SHIFT 0x18 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_MASK 0x3e000000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS__SHIFT 0x19 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE_MASK 0x40000000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE__SHIFT 0x1e +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR_MASK 0x80000000 +#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR__SHIFT 0x1f +#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ_MASK 0x1 +#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ__SHIFT 0x0 +#define UNIPHY_TMDP_REG6__IRXA_OS_POLB_MASK 0x2 +#define UNIPHY_TMDP_REG6__IRXA_OS_POLB__SHIFT 0x1 +#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL_MASK 0x4 +#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL__SHIFT 0x2 +#define UNIPHY_TMDP_REG6__IRXA_SENADJ_MASK 0x78 +#define UNIPHY_TMDP_REG6__IRXA_SENADJ__SHIFT 0x3 +#define UNIPHY_TMDP_REG6__IRXA_CPSEL_MASK 0x780 +#define UNIPHY_TMDP_REG6__IRXA_CPSEL__SHIFT 0x7 +#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x800 +#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0xb +#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN_MASK 0x3ff +#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN__SHIFT 0x0 +#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN_MASK 0x10000 +#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN__SHIFT 0x10 +#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL_MASK 0xe0000 +#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL__SHIFT 0x11 +#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED_MASK 0x7fffff +#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED__SHIFT 0x0 +#define UNIPHY_DEBUG__DEBUG0_MASK 0x3ff000 +#define UNIPHY_DEBUG__DEBUG0__SHIFT 0xc +#define UNIPHY_DEBUG__DEBUG1_MASK 0x1c00000 +#define UNIPHY_DEBUG__DEBUG1__SHIFT 0x16 +#define UNIPHY_DEBUG__DBG_SEL_MASK 0x6000000 +#define UNIPHY_DEBUG__DBG_SEL__SHIFT 0x19 +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff +#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 +#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff +#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 +#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 +#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 +#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 +#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 +#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 +#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 +#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 +#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000 +#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 +#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 +#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb +#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 +#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 +#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 +#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 +#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff +#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 +#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff +#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 +#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1 +#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0 +#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1 +#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0 +#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff +#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 +#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 +#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 +#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff +#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 +#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 +#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 +#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff +#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 +#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 +#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 +#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff +#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 +#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 +#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 +#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 +#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 +#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 +#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 +#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 +#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 +#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000 +#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18 +#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 +#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 +#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 +#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 +#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 +#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 +#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000 +#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18 +#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff +#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 +#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 +#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 +#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff +#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 +#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 +#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 +#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 +#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 +#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 +#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 +#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 +#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 +#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 +#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 +#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb +#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 +#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 +#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 +#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 +#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 +#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 +#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 +#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 +#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff +#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 +#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff +#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 +#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff +#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 +#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff +#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 +#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1 +#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0 +#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1 +#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0 +#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1 +#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0 +#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1 +#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0 +#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff +#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff +#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x7 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK 0x3f +#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT 0x0 +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffc0 +#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x6 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1 +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8 +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00 +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000 +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc +#define MINOR_VERSION__MINOR_VERSION_MASK 0xff +#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 +#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff +#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1 +#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 +#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2 +#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100 +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1 +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1 +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 +#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2 +#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 +#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff +#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0 +#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1 +#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 +#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x2 +#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 +#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x4 +#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 +#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x8 +#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 +#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x10 +#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 +#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x20 +#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 +#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x40 +#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6 +#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x80 +#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7 +#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x100 +#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8 +#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x200 +#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9 +#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x400 +#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa +#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x800 +#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb +#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x1000 +#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc +#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x2000 +#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd +#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x4000 +#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe +#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x8000 +#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000 +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f +#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x1 +#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 +#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x2 +#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 +#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x4 +#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 +#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x8 +#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 +#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x10 +#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 +#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x20 +#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 +#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x40 +#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6 +#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x80 +#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7 +#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x100 +#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8 +#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x200 +#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9 +#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x400 +#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa +#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x800 +#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb +#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x1000 +#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc +#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x2000 +#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd +#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x4000 +#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe +#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x8000 +#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000 +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000 +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1 +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2 +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4 +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8 +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10 +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20 +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 +#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x40 +#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6 +#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x80 +#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7 +#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x100 +#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8 +#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x200 +#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9 +#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x400 +#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa +#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x800 +#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb +#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x1000 +#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc +#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x2000 +#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd +#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x4000 +#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe +#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x8000 +#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff +#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff +#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000 +#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 +#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2 +#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1 +#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_MASK 0x3 +#define CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0 +#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000 +#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff +#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 +#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 +#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4 +#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1 +#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4 +#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define RIRB_SIZE__RIRB_SIZE_MASK 0x3 +#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 +#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff +#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2 +#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff +#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000 +#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff +#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff +#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff +#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30 +#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0xc +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0xc0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0xc +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0xc0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x1e0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0xff0000 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff0000 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff +#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x4 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x18 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x20 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0xc0 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x100 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x600 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x800 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x3000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x4000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x18000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x20000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0xc0000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x100000 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x3 +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0xc +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x30 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0xc0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x300 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0xc00 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x3000 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc +#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK 0x1 +#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x1 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x1 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff +#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100 +#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff +#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f +#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000 +#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1 +#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff +#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff +#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff +#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff +#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff +#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff +#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 +#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff +#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x3000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 +#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff +#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000 +#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3 +#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10 +#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x1 +#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x1 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x10 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x100 +#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x1 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x10 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x100 +#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x1 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x10 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x100 +#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x3fff +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x2 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x100 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x200 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x10000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x20000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff +#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff +#define BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0 +#define BLND_CONTROL__BLND_MODE_MASK 0x300 +#define BLND_CONTROL__BLND_MODE__SHIFT 0x8 +#define BLND_CONTROL__BLND_STEREO_TYPE_MASK 0xc00 +#define BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa +#define BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000 +#define BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc +#define BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000 +#define BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd +#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000 +#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10 +#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000 +#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14 +#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000 +#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18 +#define BLND_SM_CONTROL2__SM_MODE_MASK 0x7 +#define BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0 +#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10 +#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4 +#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20 +#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5 +#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300 +#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000 +#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000 +#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define BLND_CONTROL2__PTI_ENABLE_MASK 0x1 +#define BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0 +#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30 +#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4 +#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40 +#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6 +#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80 +#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7 +#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100 +#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8 +#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1 +#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0 +#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100 +#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8 +#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000 +#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000 +#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2 +#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000 +#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18 +#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000 +#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c +#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000 +#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d +#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000 +#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80 +#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200 +#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9 +#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400 +#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa +#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800 +#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb +#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1 +#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0 +#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe +#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff +#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0 +#define WB_ENABLE__WB_ENABLE_MASK 0x1 +#define WB_ENABLE__WB_ENABLE__SHIFT 0x0 +#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x1 +#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0 +#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x2 +#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1 +#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x4 +#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2 +#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x40 +#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x6 +#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x80 +#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x7 +#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x100 +#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x8 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x600 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0x9 +#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0xf000 +#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0xc +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x10000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0x10 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x60000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0x11 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x180000 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x13 +#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x800000 +#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17 +#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000 +#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c +#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000 +#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e +#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x300 +#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8 +#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x1000 +#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc +#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x6000 +#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd +#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x8000 +#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf +#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000 +#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 +#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x40000 +#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12 +#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x80000 +#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13 +#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x100000 +#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14 +#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000 +#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 +#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000 +#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f +#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff +#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 +#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000 +#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 +#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff +#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 +#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000 +#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 +#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1 +#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 +#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100 +#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 +#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000 +#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 +#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff +#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 +#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000 +#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 +#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x1 +#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0 +#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff +#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 +#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000 +#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 +#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff +#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 +#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000 +#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 +#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff +#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 +#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000 +#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 +#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff +#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 +#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000 +#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 +#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff +#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 +#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000 +#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 +#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff +#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 +#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000 +#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 +#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 +#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 +#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff +#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000 +#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000 +#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000 +#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 +#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10 +#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 +#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100 +#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 +#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000 +#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xfff0 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xfff0 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xfff0 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 +#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x1 +#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0 +#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0xc0 +#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6 +#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x1 +#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0 +#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x2 +#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1 +#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x4 +#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2 +#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x8 +#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3 +#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x100 +#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8 +#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7fff0000 +#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10 +#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xffffffff +#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0 +#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x3 +#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0 +#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x1c +#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 +#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x1 +#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff +#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10 +#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc +#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x8000 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf +#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_LOW_POWER_GATE_DISABLE_MASK 0x20000 +#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_LOW_POWER_GATE_DISABLE__SHIFT 0x11 +#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1f000000 +#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18 +#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000 +#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f +#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x2 +#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x4 +#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x8 +#define DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3 +#define DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10 +#define DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4 +#define DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x20 +#define DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5 +#define DCFE_SOFT_RESET__DCP_LOW_POWER_SOFT_RESET_MASK 0x40 +#define DCFE_SOFT_RESET__DCP_LOW_POWER_SOFT_RESET__SHIFT 0x6 +#define DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK 0x1 +#define DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT 0x0 +#define DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK 0xf0 +#define DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT 0x4 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x3 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x4 +#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x18 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x20 +#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0xc0 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100 +#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x600 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800 +#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x3000 +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x4000 +#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x18000 +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000 +#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0xc0000 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x100000 +#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x600000 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x800000 +#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x3000000 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x4000000 +#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000 +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000 +#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d +#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x3 +#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0xc +#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2 +#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x30 +#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0xc0 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6 +#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x300 +#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8 +#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0xc00 +#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x3000 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0xc000 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x30000 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x40000 +#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x600000 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x800000 +#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17 +#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3 +#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0xc +#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2 +#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x30 +#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0xc0 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x300 +#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8 +#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0xc00 +#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa +#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x3000 +#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc +#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0xc000 +#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe +#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x30000 +#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10 +#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000 +#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12 +#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x300000 +#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14 +#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0xc00000 +#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16 +#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x1 +#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0 +#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x8 +#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x80 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x200 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x800 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x2000 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x8000 +#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf +#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1f000000 +#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18 +#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000 +#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f +#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x1 +#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0 +#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x2 +#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1 +#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x4 +#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2 +#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x8 +#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3 +#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10 +#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4 +#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x20 +#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5 +#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x40 +#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x8 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x10 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x20 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x40 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1f000000 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000 +#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f +#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK 0x1 +#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT 0x0 +#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK 0xf0 +#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT 0x4 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x3 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x4 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x8 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x10 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x20 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x40 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x80 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x100 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x200 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x400 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x800 +#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x3 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0xc +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x30 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0xc0 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x300 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0xc00 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x3000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0xc000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x30000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0xc0000 +#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE_MASK 0x3 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE__SHIFT 0x0 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS_MASK 0x4 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS__SHIFT 0x2 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x18 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x20 +#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5 +#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0xc0 +#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6 +#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x100 +#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8 +#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x600 +#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9 +#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x800 +#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb +#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x3000 +#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc +#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x4000 +#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe +#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x18000 +#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf +#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x20000 +#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11 +#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL_MASK 0x3 +#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0xc +#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2 +#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x30 +#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4 +#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0xc0 +#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6 +#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE_MASK 0x3 +#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE__SHIFT 0x0 +#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0xc +#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2 +#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x30 +#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4 +#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0xc0 +#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6 +#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x300 +#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8 +#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0xc00 +#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa +#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x3000 +#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL_MASK 0xf +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL__SHIFT 0x0 +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA_MASK 0x10 +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA__SHIFT 0x4 +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER_MASK 0x20 +#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER__SHIFT 0x5 +#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x1 +#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0 +#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x1 +#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x2 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x10 +#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x100 +#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 +#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x1 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x100 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x10000 +#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x100000 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x1000000 +#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x1fff +#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x3ff0000 +#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000 +#define DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0xff +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x1000000 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 +#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0xff +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0xff00000 +#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xffffffff +#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0 +#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xffffffff +#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0 +#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xffffffff +#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0 +#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xffffffff +#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0 +#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xffffffff +#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0 +#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xffffffff +#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0 +#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xffffffff +#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0 +#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xffffffff +#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0 +#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7 +#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0 +#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70 +#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x400 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x800 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0xb +#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x1 +#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 +#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x4 +#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2 +#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x8 +#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 +#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x10 +#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 +#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x20 +#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 +#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x40 +#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 +#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x80 +#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 +#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x100 +#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 +#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x200 +#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 +#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0xc00 +#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa +#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x3000 +#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc +#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0xc000 +#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe +#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x30000 +#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10 +#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0xc0000 +#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12 +#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x300000 +#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14 +#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0xc00000 +#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16 +#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE_MASK 0x1 +#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE__SHIFT 0x0 +#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE_MASK 0x2 +#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE__SHIFT 0x1 +#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE_MASK 0xc00 +#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE__SHIFT 0xa +#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE_MASK 0x3000 +#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 0xc +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x1 +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x2 +#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x8 +#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3 +#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x10 +#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x20 +#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x40 +#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x80 +#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 +#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x100 +#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x200 +#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x400 +#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x1800 +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x2000 +#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0xc000 +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x10000 +#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x60000 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x80000 +#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x300000 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x400000 +#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x1800000 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x2000000 +#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19 +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0xc000000 +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000 +#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000 +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000 +#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f +#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x3 +#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS_MASK 0x4 +#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS__SHIFT 0x2 +#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS_MASK 0x8 +#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS__SHIFT 0x3 +#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE_MASK 0x30000 +#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE__SHIFT 0x10 +#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS_MASK 0x40000 +#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS__SHIFT 0x12 +#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE_MASK 0x180000 +#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE__SHIFT 0x13 +#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS_MASK 0x200000 +#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS__SHIFT 0x15 +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20 +#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5 +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40 +#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6 +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80 +#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7 +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100 +#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8 +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200 +#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9 +#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x400 +#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10 +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11 +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12 +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13 +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14 +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000 +#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15 +#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS_MASK 0x400000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS__SHIFT 0x16 +#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS_MASK 0x800000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS__SHIFT 0x17 +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d +#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000 +#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e +#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL_MASK 0x7f +#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL__SHIFT 0x0 +#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS_MASK 0x80 +#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS__SHIFT 0x7 +#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS_MASK 0x100 +#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS__SHIFT 0x8 +#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS_MASK 0x200 +#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS__SHIFT 0x9 +#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS_MASK 0x400 +#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS__SHIFT 0xa +#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS_MASK 0x800 +#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS__SHIFT 0xb +#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS_MASK 0x1000 +#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS__SHIFT 0xc +#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS_MASK 0x2000 +#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS__SHIFT 0xd +#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS_MASK 0x8000 +#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS__SHIFT 0xf +#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS_MASK 0x10000 +#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS__SHIFT 0x10 +#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x20000 +#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11 +#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x40000 +#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12 +#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x80000 +#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13 +#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x100000 +#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14 +#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x200000 +#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15 +#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x400000 +#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16 +#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x800000 +#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17 +#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS_MASK 0x2000000 +#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS__SHIFT 0x19 +#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS_MASK 0x4000000 +#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS__SHIFT 0x1a +#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x1 +#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0 +#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x2 +#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1 +#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x4 +#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2 +#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x8 +#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3 +#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x10 +#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4 +#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x20 +#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5 +#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x40 +#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6 +#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS_MASK 0x100 +#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS__SHIFT 0x8 +#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS_MASK 0x200 +#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS__SHIFT 0x9 +#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x400 +#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa +#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x800 +#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb +#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x1000 +#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc +#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x2000 +#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd +#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x4000 +#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe +#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x8000 +#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf +#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x10000 +#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10 +#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS_MASK 0x40000 +#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS__SHIFT 0x12 +#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS_MASK 0x80000 +#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS__SHIFT 0x13 +#define DPDBG_CNTL__DPDBG_ENABLE_MASK 0x1 +#define DPDBG_CNTL__DPDBG_ENABLE__SHIFT 0x0 +#define DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK 0x2 +#define DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT 0x1 +#define DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK 0x10 +#define DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT 0x4 +#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK 0x100 +#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT 0x8 +#define DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK 0xffff0000 +#define DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT 0x10 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK 0x1 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT 0x0 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK 0x2 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT 0x1 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK 0x100 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT 0x8 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK 0x10000 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT 0x10 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK 0x1000000 +#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT 0x18 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100 +#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 +#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1 +#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0 +#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10 +#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4 +#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20 +#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5 +#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40 +#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6 +#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x1000 +#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc +#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000 +#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10 +#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000 +#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11 +#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000 +#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12 +#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000 +#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13 +#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000 +#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14 +#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000 +#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15 +#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000 +#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18 +#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000 +#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19 +#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000 +#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000 +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000 +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 +#define DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK 0x80000000 +#define DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT 0x1f +#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET_MASK 0x1 +#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET_MASK 0x2 +#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET_MASK 0x10 +#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET_MASK 0x20 +#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET__SHIFT 0x5 +#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7 +#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0 +#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000 +#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10 +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK 0xff +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK 0xffffffff +#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1 +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000 +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000 +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000 +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000 +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000 +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000 +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1 +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000 +#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x300 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000 +#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000 +#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x20 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x40 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x80 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x100 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x200 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x400 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x800 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x1000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x2000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x4000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x8000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x10000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x20000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x40000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x80000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x100000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x200000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x400000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x800000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x1000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x2000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x4000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x8000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000 +#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK 0x100 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK 0x200 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT 0x9 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK 0x400 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT 0xa +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK 0x800 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT 0xb +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x1000 +#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0xc +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf +#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10 +#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20 +#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40 +#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200 +#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400 +#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3 +#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10 +#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x300 +#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000 +#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2 +#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80 +#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00 +#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000 +#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000 +#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00 +#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000 +#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00 +#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40 +#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6 +#define BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff +#define BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0 +#define BLNDV_CONTROL__BLND_MODE_MASK 0x300 +#define BLNDV_CONTROL__BLND_MODE__SHIFT 0x8 +#define BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0xc00 +#define BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa +#define BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000 +#define BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc +#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000 +#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd +#define BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x30000 +#define BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10 +#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000 +#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14 +#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000 +#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18 +#define BLNDV_SM_CONTROL2__SM_MODE_MASK 0x7 +#define BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0 +#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10 +#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4 +#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20 +#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5 +#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300 +#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000 +#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000 +#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define BLNDV_CONTROL2__PTI_ENABLE_MASK 0x1 +#define BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0 +#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30 +#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4 +#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40 +#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6 +#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80 +#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7 +#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100 +#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8 +#define BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x1 +#define BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0 +#define BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100 +#define BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8 +#define BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000 +#define BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000 +#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000 +#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18 +#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000 +#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c +#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000 +#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d +#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000 +#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80 +#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7 +#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100 +#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8 +#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200 +#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9 +#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400 +#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa +#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800 +#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb +#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1 +#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0 +#define BLNDV_DEBUG__BLND_DEBUG_MASK 0xfffffffe +#define BLNDV_DEBUG__BLND_DEBUG__SHIFT 0x1 +#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff +#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0 +#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff +#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0 +#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff +#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0 +#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000 +#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10 +#define CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff +#define CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 +#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff +#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 +#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000 +#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 +#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff +#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 +#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000 +#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 +#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1 +#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0 +#define CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000 +#define CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10 +#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000 +#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff +#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0 +#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000 +#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10 +#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1 +#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0 +#define CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000 +#define CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10 +#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000 +#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11 +#define CRTCV_VBI_END__CRTC_VBI_V_END_MASK 0x3fff +#define CRTCV_VBI_END__CRTC_VBI_V_END__SHIFT 0x0 +#define CRTCV_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000 +#define CRTCV_VBI_END__CRTC_VBI_H_END__SHIFT 0x10 +#define CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff +#define CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 +#define CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff +#define CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0 +#define CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff +#define CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0 +#define CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000 +#define CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10 +#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1 +#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10 +#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4 +#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100 +#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8 +#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000 +#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc +#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000 +#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf +#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000 +#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1 +#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 +#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10 +#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 +#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100 +#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 +#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000 +#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc +#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1 +#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0 +#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10 +#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff +#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 +#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000 +#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 +#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff +#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 +#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000 +#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 +#define CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1 +#define CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0 +#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff +#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0 +#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000 +#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10 +#define CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1 +#define CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0 +#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1 +#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0 +#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e +#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1 +#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff +#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0 +#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000 +#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000 +#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f +#define CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1 +#define CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000 +#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f +#define CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1 +#define CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3 +#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10 +#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100 +#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000 +#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000 +#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f +#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100 +#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000 +#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000 +#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3 +#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00 +#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000 +#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff +#define CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0 +#define CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x1 +#define CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 +#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 +#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 +#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 +#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 +#define CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 +#define CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc +#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 +#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd +#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 +#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 +#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 +#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 +#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 +#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 +#define CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d +#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000 +#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e +#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000 +#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f +#define CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1 +#define CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0 +#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100 +#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8 +#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000 +#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10 +#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1 +#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0 +#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000 +#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1 +#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2 +#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1 +#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 +#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2 +#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1 +#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff +#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000 +#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff +#define CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define CRTCV_STATUS__CRTC_V_BLANK_MASK 0x1 +#define CRTCV_STATUS__CRTC_V_BLANK__SHIFT 0x0 +#define CRTCV_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2 +#define CRTCV_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1 +#define CRTCV_STATUS__CRTC_V_SYNC_A_MASK 0x4 +#define CRTCV_STATUS__CRTC_V_SYNC_A__SHIFT 0x2 +#define CRTCV_STATUS__CRTC_V_UPDATE_MASK 0x8 +#define CRTCV_STATUS__CRTC_V_UPDATE__SHIFT 0x3 +#define CRTCV_STATUS__CRTC_V_START_LINE_MASK 0x10 +#define CRTCV_STATUS__CRTC_V_START_LINE__SHIFT 0x4 +#define CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20 +#define CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define CRTCV_STATUS__CRTC_H_BLANK_MASK 0x10000 +#define CRTCV_STATUS__CRTC_H_BLANK__SHIFT 0x10 +#define CRTCV_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000 +#define CRTCV_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11 +#define CRTCV_STATUS__CRTC_H_SYNC_A_MASK 0x40000 +#define CRTCV_STATUS__CRTC_H_SYNC_A__SHIFT 0x12 +#define CRTCV_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff +#define CRTCV_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0 +#define CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000 +#define CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10 +#define CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff +#define CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0 +#define CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff +#define CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0 +#define CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff +#define CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0 +#define CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff +#define CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0 +#define CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1 +#define CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e +#define CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1 +#define CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0 +#define CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1 +#define CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1 +#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100 +#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000 +#define CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1 +#define CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0 +#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100 +#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000 +#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10 +#define CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000 +#define CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14 +#define CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000 +#define CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff +#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000 +#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000 +#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10 +#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000 +#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000 +#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000 +#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13 +#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000 +#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000 +#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18 +#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1 +#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2 +#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1 +#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4 +#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3 +#define CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff +#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000 +#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff +#define CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 +#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 +#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2 +#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1 +#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4 +#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2 +#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100 +#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8 +#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000 +#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc +#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1 +#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2 +#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10 +#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4 +#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20 +#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5 +#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100 +#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 +#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000 +#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000 +#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000 +#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18 +#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000 +#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19 +#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000 +#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a +#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000 +#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b +#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000 +#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000 +#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000 +#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000 +#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1 +#define CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0 +#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1 +#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0 +#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100 +#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8 +#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000 +#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1 +#define CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0 +#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1 +#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0 +#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700 +#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8 +#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000 +#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 +#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000 +#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 +#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf +#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0 +#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0 +#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4 +#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00 +#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8 +#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000 +#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc +#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000 +#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 +#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff +#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0 +#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000 +#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10 +#define CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1 +#define CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0 +#define CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100 +#define CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8 +#define CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x10000 +#define CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10 +#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7 +#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0 +#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000 +#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10 +#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3 +#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0 +#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00 +#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8 +#define CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff +#define CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0 +#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1 +#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0 +#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10 +#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4 +#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000 +#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10 +#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000 +#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14 +#define CRTCV_MASTER_EN__CRTC_MASTER_EN_MASK 0x1 +#define CRTCV_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0 +#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff +#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0 +#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000 +#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10 +#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1 +#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0 +#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100 +#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8 +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 +#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 +#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 +#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff +#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00 +#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000 +#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3 +#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300 +#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000 +#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 +#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 +#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff +#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000 +#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10 +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100 +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000 +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000 +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000 +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000 +#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff +#define CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100 +#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000 +#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000 +#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000 +#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000 +#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff +#define CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100 +#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000 +#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000 +#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000 +#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000 +#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 +#define CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 +#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 +#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 +#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 +#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 +#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 +#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc +#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 +#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 +#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 +#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 +#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 +#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 +#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff +#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000 +#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff +#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000 +#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff +#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000 +#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff +#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000 +#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff +#define CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 +#define CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff +#define CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff +#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000 +#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff +#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000 +#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff +#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000 +#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff +#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000 +#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff +#define CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 +#define CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff +#define CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000 +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000 +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000 +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19 +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000 +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000 +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000 +#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000 +#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000 +#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18 +#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff +#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0 +#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000 +#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10 +#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff +#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0 +#define CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000 +#define CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10 +#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000 +#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff +#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff +#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000 +#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000 +#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000 +#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400 +#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000 +#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000 +#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000 +#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE_MASK 0x3 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE__SHIFT 0x0 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE_MASK 0xc +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE__SHIFT 0x2 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE_MASK 0x180000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE__SHIFT 0x13 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS_MASK 0x200000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS__SHIFT 0x15 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE_MASK 0xc00000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE__SHIFT 0x16 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS_MASK 0x2000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS__SHIFT 0x19 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE_MASK 0xc000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE__SHIFT 0x1a +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS_MASK 0x10000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS__SHIFT 0x1c +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE_MASK 0x60000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE__SHIFT 0x1d +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS_MASK 0x80000000 +#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS__SHIFT 0x1f +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100 +#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8 +#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff +#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0 +#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1 +#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff +#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000 +#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf +#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff +#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0 +#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff +#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0 +#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff +#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0 +#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000 +#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18 +#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000 +#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19 +#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000 +#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN_MASK 0x400 +#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN__SHIFT 0xa +#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff +#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10 +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12 +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14 +#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15 +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0 +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10 +#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0 +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE_MASK 0x10000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE__SHIFT 0x1c +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP_MASK 0x60000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP__SHIFT 0x1d +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER_MASK 0x80000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER__SHIFT 0x1f +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10 +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 +#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff +#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0 +#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff +#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE_MASK 0x60000000 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE__SHIFT 0x1d +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS_MASK 0x80000000 +#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS__SHIFT 0x1f +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0 +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000 +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0 +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200 +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9 +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400 +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa +#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000 +#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000 +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13 +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000 +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14 +#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000 +#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18 +#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET_MASK 0x2000000 +#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET__SHIFT 0x19 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE_MASK 0xc00000 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE__SHIFT 0x16 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS_MASK 0x1000000 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS__SHIFT 0x18 +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0 +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1 +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18 +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0 +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 + +#endif /* DCE_11_0_SH_MASK_H */ -- cgit v1.2.3 From 9f24d8ce2522808cdb719775dbb32cb296e20f47 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:19:28 -0400 Subject: drm/amdgpu: add GCA 7.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h | 2532 ++++++++++++++++++++ 1 file changed, 2532 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h new file mode 100644 index 000000000000..b1d7cefb4bd1 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h @@ -0,0 +1,2532 @@ +/* + * GFX_7_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_7_0_D_H +#define GFX_7_0_D_H + +#define mmCB_BLEND_RED 0xa105 +#define mmCB_BLEND_GREEN 0xa106 +#define mmCB_BLEND_BLUE 0xa107 +#define mmCB_BLEND_ALPHA 0xa108 +#define mmCB_COLOR_CONTROL 0xa202 +#define mmCB_BLEND0_CONTROL 0xa1e0 +#define mmCB_BLEND1_CONTROL 0xa1e1 +#define mmCB_BLEND2_CONTROL 0xa1e2 +#define mmCB_BLEND3_CONTROL 0xa1e3 +#define mmCB_BLEND4_CONTROL 0xa1e4 +#define mmCB_BLEND5_CONTROL 0xa1e5 +#define mmCB_BLEND6_CONTROL 0xa1e6 +#define mmCB_BLEND7_CONTROL 0xa1e7 +#define mmCB_COLOR0_BASE 0xa318 +#define mmCB_COLOR1_BASE 0xa327 +#define mmCB_COLOR2_BASE 0xa336 +#define mmCB_COLOR3_BASE 0xa345 +#define mmCB_COLOR4_BASE 0xa354 +#define mmCB_COLOR5_BASE 0xa363 +#define mmCB_COLOR6_BASE 0xa372 +#define mmCB_COLOR7_BASE 0xa381 +#define mmCB_COLOR0_PITCH 0xa319 +#define mmCB_COLOR1_PITCH 0xa328 +#define mmCB_COLOR2_PITCH 0xa337 +#define mmCB_COLOR3_PITCH 0xa346 +#define mmCB_COLOR4_PITCH 0xa355 +#define mmCB_COLOR5_PITCH 0xa364 +#define mmCB_COLOR6_PITCH 0xa373 +#define mmCB_COLOR7_PITCH 0xa382 +#define mmCB_COLOR0_SLICE 0xa31a +#define mmCB_COLOR1_SLICE 0xa329 +#define mmCB_COLOR2_SLICE 0xa338 +#define mmCB_COLOR3_SLICE 0xa347 +#define mmCB_COLOR4_SLICE 0xa356 +#define mmCB_COLOR5_SLICE 0xa365 +#define mmCB_COLOR6_SLICE 0xa374 +#define mmCB_COLOR7_SLICE 0xa383 +#define mmCB_COLOR0_VIEW 0xa31b +#define mmCB_COLOR1_VIEW 0xa32a +#define mmCB_COLOR2_VIEW 0xa339 +#define mmCB_COLOR3_VIEW 0xa348 +#define mmCB_COLOR4_VIEW 0xa357 +#define mmCB_COLOR5_VIEW 0xa366 +#define mmCB_COLOR6_VIEW 0xa375 +#define mmCB_COLOR7_VIEW 0xa384 +#define mmCB_COLOR0_INFO 0xa31c +#define mmCB_COLOR1_INFO 0xa32b +#define mmCB_COLOR2_INFO 0xa33a +#define mmCB_COLOR3_INFO 0xa349 +#define mmCB_COLOR4_INFO 0xa358 +#define mmCB_COLOR5_INFO 0xa367 +#define mmCB_COLOR6_INFO 0xa376 +#define mmCB_COLOR7_INFO 0xa385 +#define mmCB_COLOR0_ATTRIB 0xa31d +#define mmCB_COLOR1_ATTRIB 0xa32c +#define mmCB_COLOR2_ATTRIB 0xa33b +#define mmCB_COLOR3_ATTRIB 0xa34a +#define mmCB_COLOR4_ATTRIB 0xa359 +#define mmCB_COLOR5_ATTRIB 0xa368 +#define mmCB_COLOR6_ATTRIB 0xa377 +#define mmCB_COLOR7_ATTRIB 0xa386 +#define mmCB_COLOR0_CMASK 0xa31f +#define mmCB_COLOR1_CMASK 0xa32e +#define mmCB_COLOR2_CMASK 0xa33d +#define mmCB_COLOR3_CMASK 0xa34c +#define mmCB_COLOR4_CMASK 0xa35b +#define mmCB_COLOR5_CMASK 0xa36a +#define mmCB_COLOR6_CMASK 0xa379 +#define mmCB_COLOR7_CMASK 0xa388 +#define mmCB_COLOR0_CMASK_SLICE 0xa320 +#define mmCB_COLOR1_CMASK_SLICE 0xa32f +#define mmCB_COLOR2_CMASK_SLICE 0xa33e +#define mmCB_COLOR3_CMASK_SLICE 0xa34d +#define mmCB_COLOR4_CMASK_SLICE 0xa35c +#define mmCB_COLOR5_CMASK_SLICE 0xa36b +#define mmCB_COLOR6_CMASK_SLICE 0xa37a +#define mmCB_COLOR7_CMASK_SLICE 0xa389 +#define mmCB_COLOR0_FMASK 0xa321 +#define mmCB_COLOR1_FMASK 0xa330 +#define mmCB_COLOR2_FMASK 0xa33f +#define mmCB_COLOR3_FMASK 0xa34e +#define mmCB_COLOR4_FMASK 0xa35d +#define mmCB_COLOR5_FMASK 0xa36c +#define mmCB_COLOR6_FMASK 0xa37b +#define mmCB_COLOR7_FMASK 0xa38a +#define mmCB_COLOR0_FMASK_SLICE 0xa322 +#define mmCB_COLOR1_FMASK_SLICE 0xa331 +#define mmCB_COLOR2_FMASK_SLICE 0xa340 +#define mmCB_COLOR3_FMASK_SLICE 0xa34f +#define mmCB_COLOR4_FMASK_SLICE 0xa35e +#define mmCB_COLOR5_FMASK_SLICE 0xa36d +#define mmCB_COLOR6_FMASK_SLICE 0xa37c +#define mmCB_COLOR7_FMASK_SLICE 0xa38b +#define mmCB_COLOR0_CLEAR_WORD0 0xa323 +#define mmCB_COLOR1_CLEAR_WORD0 0xa332 +#define mmCB_COLOR2_CLEAR_WORD0 0xa341 +#define mmCB_COLOR3_CLEAR_WORD0 0xa350 +#define mmCB_COLOR4_CLEAR_WORD0 0xa35f +#define mmCB_COLOR5_CLEAR_WORD0 0xa36e +#define mmCB_COLOR6_CLEAR_WORD0 0xa37d +#define mmCB_COLOR7_CLEAR_WORD0 0xa38c +#define mmCB_COLOR0_CLEAR_WORD1 0xa324 +#define mmCB_COLOR1_CLEAR_WORD1 0xa333 +#define mmCB_COLOR2_CLEAR_WORD1 0xa342 +#define mmCB_COLOR3_CLEAR_WORD1 0xa351 +#define mmCB_COLOR4_CLEAR_WORD1 0xa360 +#define mmCB_COLOR5_CLEAR_WORD1 0xa36f +#define mmCB_COLOR6_CLEAR_WORD1 0xa37e +#define mmCB_COLOR7_CLEAR_WORD1 0xa38d +#define mmCB_TARGET_MASK 0xa08e +#define mmCB_SHADER_MASK 0xa08f +#define mmCB_HW_CONTROL 0x2684 +#define mmCB_HW_CONTROL_1 0x2685 +#define mmCB_HW_CONTROL_2 0x2686 +#define mmCB_HW_CONTROL_3 0x2683 +#define mmCB_PERFCOUNTER_FILTER 0xdc00 +#define mmCB_PERFCOUNTER0_SELECT 0xdc01 +#define mmCB_PERFCOUNTER0_SELECT1 0xdc02 +#define mmCB_PERFCOUNTER1_SELECT 0xdc03 +#define mmCB_PERFCOUNTER2_SELECT 0xdc04 +#define mmCB_PERFCOUNTER3_SELECT 0xdc05 +#define mmCB_PERFCOUNTER0_LO 0xd406 +#define mmCB_PERFCOUNTER1_LO 0xd408 +#define mmCB_PERFCOUNTER2_LO 0xd40a +#define mmCB_PERFCOUNTER3_LO 0xd40c +#define mmCB_PERFCOUNTER0_HI 0xd407 +#define mmCB_PERFCOUNTER1_HI 0xd409 +#define mmCB_PERFCOUNTER2_HI 0xd40b +#define mmCB_PERFCOUNTER3_HI 0xd40d +#define mmCB_CGTT_SCLK_CTRL 0xf0a8 +#define mmCB_DEBUG_BUS_1 0x2699 +#define mmCB_DEBUG_BUS_2 0x269a +#define mmCB_DEBUG_BUS_3 0x269b +#define mmCB_DEBUG_BUS_4 0x269c +#define mmCB_DEBUG_BUS_5 0x269d +#define mmCB_DEBUG_BUS_6 0x269e +#define mmCB_DEBUG_BUS_7 0x269f +#define mmCB_DEBUG_BUS_8 0x26a0 +#define mmCB_DEBUG_BUS_9 0x26a1 +#define mmCB_DEBUG_BUS_10 0x26a2 +#define mmCB_DEBUG_BUS_11 0x26a3 +#define mmCB_DEBUG_BUS_12 0x26a4 +#define mmCB_DEBUG_BUS_13 0x26a5 +#define mmCB_DEBUG_BUS_14 0x26a6 +#define mmCB_DEBUG_BUS_15 0x26a7 +#define mmCB_DEBUG_BUS_16 0x26a8 +#define mmCB_DEBUG_BUS_17 0x26a9 +#define mmCB_DEBUG_BUS_18 0x26aa +#define mmCP_DFY_CNTL 0x3020 +#define mmCP_DFY_STAT 0x3021 +#define mmCP_DFY_ADDR_HI 0x3022 +#define mmCP_DFY_ADDR_LO 0x3023 +#define mmCP_DFY_DATA_0 0x3024 +#define mmCP_DFY_DATA_1 0x3025 +#define mmCP_DFY_DATA_2 0x3026 +#define mmCP_DFY_DATA_3 0x3027 +#define mmCP_DFY_DATA_4 0x3028 +#define mmCP_DFY_DATA_5 0x3029 +#define mmCP_DFY_DATA_6 0x302a +#define mmCP_DFY_DATA_7 0x302b +#define mmCP_DFY_DATA_8 0x302c +#define mmCP_DFY_DATA_9 0x302d +#define mmCP_DFY_DATA_10 0x302e +#define mmCP_DFY_DATA_11 0x302f +#define mmCP_DFY_DATA_12 0x3030 +#define mmCP_DFY_DATA_13 0x3031 +#define mmCP_DFY_DATA_14 0x3032 +#define mmCP_DFY_DATA_15 0x3033 +#define mmCP_RB0_BASE 0x3040 +#define mmCP_RB0_BASE_HI 0x30b1 +#define mmCP_RB_BASE 0x3040 +#define mmCP_RB1_BASE 0x3060 +#define mmCP_RB1_BASE_HI 0x30b2 +#define mmCP_RB2_BASE 0x3065 +#define mmCP_RB0_CNTL 0x3041 +#define mmCP_RB_CNTL 0x3041 +#define mmCP_RB1_CNTL 0x3061 +#define mmCP_RB2_CNTL 0x3066 +#define mmCP_RB_RPTR_WR 0x3042 +#define mmCP_RB0_RPTR_ADDR 0x3043 +#define mmCP_RB_RPTR_ADDR 0x3043 +#define mmCP_RB1_RPTR_ADDR 0x3062 +#define mmCP_RB2_RPTR_ADDR 0x3067 +#define mmCP_RB0_RPTR_ADDR_HI 0x3044 +#define mmCP_RB_RPTR_ADDR_HI 0x3044 +#define mmCP_RB1_RPTR_ADDR_HI 0x3063 +#define mmCP_RB2_RPTR_ADDR_HI 0x3068 +#define mmCP_RB0_WPTR 0x3045 +#define mmCP_RB_WPTR 0x3045 +#define mmCP_RB1_WPTR 0x3064 +#define mmCP_RB2_WPTR 0x3069 +#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 +#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 +#define mmGC_PRIV_MODE 0x3048 +#define mmCP_INT_CNTL 0x3049 +#define mmCP_INT_CNTL_RING0 0x306a +#define mmCP_INT_CNTL_RING1 0x306b +#define mmCP_INT_CNTL_RING2 0x306c +#define mmCP_INT_STATUS 0x304a +#define mmCP_INT_STATUS_RING0 0x306d +#define mmCP_INT_STATUS_RING1 0x306e +#define mmCP_INT_STATUS_RING2 0x306f +#define mmCP_DEVICE_ID 0x304b +#define mmCP_RING_PRIORITY_CNTS 0x304c +#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c +#define mmCP_RING0_PRIORITY 0x304d +#define mmCP_ME0_PIPE0_PRIORITY 0x304d +#define mmCP_RING1_PRIORITY 0x304e +#define mmCP_ME0_PIPE1_PRIORITY 0x304e +#define mmCP_RING2_PRIORITY 0x304f +#define mmCP_ME0_PIPE2_PRIORITY 0x304f +#define mmCP_ENDIAN_SWAP 0x3050 +#define mmCP_RB_VMID 0x3051 +#define mmCP_PFP_UCODE_ADDR 0x3054 +#define mmCP_PFP_UCODE_DATA 0x3055 +#define mmCP_ME_RAM_RADDR 0x3056 +#define mmCP_ME_RAM_WADDR 0x3057 +#define mmCP_ME_RAM_DATA 0x3058 +#define mmCGTT_CPC_CLK_CTRL 0xf0b2 +#define mmCGTT_CPF_CLK_CTRL 0xf0b1 +#define mmCGTT_CP_CLK_CTRL 0xf0b0 +#define mmCP_CE_UCODE_ADDR 0x305a +#define mmCP_CE_UCODE_DATA 0x305b +#define mmCP_MEC_ME1_UCODE_ADDR 0x305c +#define mmCP_MEC_ME1_UCODE_DATA 0x305d +#define mmCP_MEC_ME2_UCODE_ADDR 0x305e +#define mmCP_MEC_ME2_UCODE_DATA 0x305f +#define mmCP_PWR_CNTL 0x3078 +#define mmCP_MEM_SLP_CNTL 0x3079 +#define mmCP_ECC_FIRSTOCCURRENCE 0x307a +#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b +#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c +#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d +#define mmCP_CPF_DEBUG 0x3080 +#define mmCP_FETCHER_SOURCE 0x3082 +#define mmCP_PQ_WPTR_POLL_CNTL 0x3083 +#define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 +#define mmCPC_INT_CNTL 0x30b4 +#define mmCP_ME1_PIPE0_INT_CNTL 0x3085 +#define mmCP_ME1_PIPE1_INT_CNTL 0x3086 +#define mmCP_ME1_PIPE2_INT_CNTL 0x3087 +#define mmCP_ME1_PIPE3_INT_CNTL 0x3088 +#define mmCP_ME2_PIPE0_INT_CNTL 0x3089 +#define mmCP_ME2_PIPE1_INT_CNTL 0x308a +#define mmCP_ME2_PIPE2_INT_CNTL 0x308b +#define mmCP_ME2_PIPE3_INT_CNTL 0x308c +#define mmCPC_INT_STATUS 0x30b5 +#define mmCP_ME1_PIPE0_INT_STATUS 0x308d +#define mmCP_ME1_PIPE1_INT_STATUS 0x308e +#define mmCP_ME1_PIPE2_INT_STATUS 0x308f +#define mmCP_ME1_PIPE3_INT_STATUS 0x3090 +#define mmCP_ME2_PIPE0_INT_STATUS 0x3091 +#define mmCP_ME2_PIPE1_INT_STATUS 0x3092 +#define mmCP_ME2_PIPE2_INT_STATUS 0x3093 +#define mmCP_ME2_PIPE3_INT_STATUS 0x3094 +#define mmCP_ME1_INT_STAT_DEBUG 0x3095 +#define mmCP_ME2_INT_STAT_DEBUG 0x3096 +#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099 +#define mmCP_ME1_PIPE0_PRIORITY 0x309a +#define mmCP_ME1_PIPE1_PRIORITY 0x309b +#define mmCP_ME1_PIPE2_PRIORITY 0x309c +#define mmCP_ME1_PIPE3_PRIORITY 0x309d +#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e +#define mmCP_ME2_PIPE0_PRIORITY 0x309f +#define mmCP_ME2_PIPE1_PRIORITY 0x30a0 +#define mmCP_ME2_PIPE2_PRIORITY 0x30a1 +#define mmCP_ME2_PIPE3_PRIORITY 0x30a2 +#define mmCP_CE_PRGRM_CNTR_START 0x30a3 +#define mmCP_PFP_PRGRM_CNTR_START 0x30a4 +#define mmCP_ME_PRGRM_CNTR_START 0x30a5 +#define mmCP_MEC1_PRGRM_CNTR_START 0x30a6 +#define mmCP_MEC2_PRGRM_CNTR_START 0x30a7 +#define mmCP_CE_INTR_ROUTINE_START 0x30a8 +#define mmCP_PFP_INTR_ROUTINE_START 0x30a9 +#define mmCP_ME_INTR_ROUTINE_START 0x30aa +#define mmCP_MEC1_INTR_ROUTINE_START 0x30ab +#define mmCP_MEC2_INTR_ROUTINE_START 0x30ac +#define mmCP_CONTEXT_CNTL 0x30ad +#define mmCP_MAX_CONTEXT 0x30ae +#define mmCP_IQ_WAIT_TIME1 0x30af +#define mmCP_IQ_WAIT_TIME2 0x30b0 +#define mmCP_VMID_RESET 0x30b3 +#define mmCP_VMID_PREEMPT 0x30b6 +#define mmCP_PQ_STATUS 0x30b8 +#define mmCP_CPC_STATUS 0x2084 +#define mmCP_CPC_BUSY_STAT 0x2085 +#define mmCP_CPC_STALLED_STAT1 0x2086 +#define mmCP_CPF_STATUS 0x2087 +#define mmCP_CPF_BUSY_STAT 0x2088 +#define mmCP_CPF_STALLED_STAT1 0x2089 +#define mmCP_CPC_MC_CNTL 0x208a +#define mmCP_CPC_GRBM_FREE_COUNT 0x208b +#define mmCP_MEC_CNTL 0x208d +#define mmCP_MEC_ME1_HEADER_DUMP 0x208e +#define mmCP_MEC_ME2_HEADER_DUMP 0x208f +#define mmCP_CPC_SCRATCH_INDEX 0x2090 +#define mmCP_CPC_SCRATCH_DATA 0x2091 +#define mmCPG_PERFCOUNTER1_SELECT 0xd800 +#define mmCPG_PERFCOUNTER1_LO 0xd000 +#define mmCPG_PERFCOUNTER1_HI 0xd001 +#define mmCPG_PERFCOUNTER0_SELECT1 0xd801 +#define mmCPG_PERFCOUNTER0_SELECT 0xd802 +#define mmCPG_PERFCOUNTER0_LO 0xd002 +#define mmCPG_PERFCOUNTER0_HI 0xd003 +#define mmCPC_PERFCOUNTER1_SELECT 0xd803 +#define mmCPC_PERFCOUNTER1_LO 0xd004 +#define mmCPC_PERFCOUNTER1_HI 0xd005 +#define mmCPC_PERFCOUNTER0_SELECT1 0xd804 +#define mmCPC_PERFCOUNTER0_SELECT 0xd809 +#define mmCPC_PERFCOUNTER0_LO 0xd006 +#define mmCPC_PERFCOUNTER0_HI 0xd007 +#define mmCPF_PERFCOUNTER1_SELECT 0xd805 +#define mmCPF_PERFCOUNTER1_LO 0xd008 +#define mmCPF_PERFCOUNTER1_HI 0xd009 +#define mmCPF_PERFCOUNTER0_SELECT1 0xd806 +#define mmCPF_PERFCOUNTER0_SELECT 0xd807 +#define mmCPF_PERFCOUNTER0_LO 0xd00a +#define mmCPF_PERFCOUNTER0_HI 0xd00b +#define mmCP_CPC_HALT_HYST_COUNT 0x20a7 +#define mmCP_CE_COMPARE_COUNT 0x20c0 +#define mmCP_CE_DE_COUNT 0x20c1 +#define mmCP_DE_CE_COUNT 0x20c2 +#define mmCP_DE_LAST_INVAL_COUNT 0x20c3 +#define mmCP_DE_DE_COUNT 0x20c4 +#define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5 +#define mmCP_EOP_DONE_DATA_CNTL 0xc0d6 +#define mmCP_EOP_DONE_ADDR_LO 0xc000 +#define mmCP_EOP_DONE_ADDR_HI 0xc001 +#define mmCP_EOP_DONE_DATA_LO 0xc002 +#define mmCP_EOP_DONE_DATA_HI 0xc003 +#define mmCP_EOP_LAST_FENCE_LO 0xc004 +#define mmCP_EOP_LAST_FENCE_HI 0xc005 +#define mmCP_STREAM_OUT_ADDR_LO 0xc006 +#define mmCP_STREAM_OUT_ADDR_HI 0xc007 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009 +#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a +#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d +#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e +#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017 +#define mmCP_PIPE_STATS_ADDR_LO 0xc018 +#define mmCP_PIPE_STATS_ADDR_HI 0xc019 +#define mmCP_VGT_IAVERT_COUNT_LO 0xc01a +#define mmCP_VGT_IAVERT_COUNT_HI 0xc01b +#define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c +#define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d +#define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e +#define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f +#define mmCP_VGT_VSINVOC_COUNT_LO 0xc020 +#define mmCP_VGT_VSINVOC_COUNT_HI 0xc021 +#define mmCP_VGT_GSINVOC_COUNT_LO 0xc022 +#define mmCP_VGT_GSINVOC_COUNT_HI 0xc023 +#define mmCP_VGT_HSINVOC_COUNT_LO 0xc024 +#define mmCP_VGT_HSINVOC_COUNT_HI 0xc025 +#define mmCP_VGT_DSINVOC_COUNT_LO 0xc026 +#define mmCP_VGT_DSINVOC_COUNT_HI 0xc027 +#define mmCP_PA_CINVOC_COUNT_LO 0xc028 +#define mmCP_PA_CINVOC_COUNT_HI 0xc029 +#define mmCP_PA_CPRIM_COUNT_LO 0xc02a +#define mmCP_PA_CPRIM_COUNT_HI 0xc02b +#define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c +#define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d +#define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e +#define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f +#define mmCP_VGT_CSINVOC_COUNT_LO 0xc030 +#define mmCP_VGT_CSINVOC_COUNT_HI 0xc031 +#define mmCP_STRMOUT_CNTL 0xc03f +#define mmSCRATCH_REG0 0xc040 +#define mmSCRATCH_REG1 0xc041 +#define mmSCRATCH_REG2 0xc042 +#define mmSCRATCH_REG3 0xc043 +#define mmSCRATCH_REG4 0xc044 +#define mmSCRATCH_REG5 0xc045 +#define mmSCRATCH_REG6 0xc046 +#define mmSCRATCH_REG7 0xc047 +#define mmSCRATCH_UMSK 0xc050 +#define mmSCRATCH_ADDR 0xc051 +#define mmCP_PFP_ATOMIC_PREOP_LO 0xc052 +#define mmCP_PFP_ATOMIC_PREOP_HI 0xc053 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057 +#define mmCP_APPEND_ADDR_LO 0xc058 +#define mmCP_APPEND_ADDR_HI 0xc059 +#define mmCP_APPEND_DATA 0xc05a +#define mmCP_APPEND_LAST_CS_FENCE 0xc05b +#define mmCP_APPEND_LAST_PS_FENCE 0xc05c +#define mmCP_ATOMIC_PREOP_LO 0xc05d +#define mmCP_ME_ATOMIC_PREOP_LO 0xc05d +#define mmCP_ATOMIC_PREOP_HI 0xc05e +#define mmCP_ME_ATOMIC_PREOP_HI 0xc05e +#define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f +#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f +#define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060 +#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060 +#define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061 +#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061 +#define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062 +#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062 +#define mmCP_ME_MC_WADDR_LO 0xc069 +#define mmCP_ME_MC_WADDR_HI 0xc06a +#define mmCP_ME_MC_WDATA_LO 0xc06b +#define mmCP_ME_MC_WDATA_HI 0xc06c +#define mmCP_ME_MC_RADDR_LO 0xc06d +#define mmCP_ME_MC_RADDR_HI 0xc06e +#define mmCP_SEM_WAIT_TIMER 0xc06f +#define mmCP_SIG_SEM_ADDR_LO 0xc070 +#define mmCP_SIG_SEM_ADDR_HI 0xc071 +#define mmCP_SEM_INCOMPLETE_TIMER_CNTL 0xc072 +#define mmCP_WAIT_SEM_STATUS 0xc073 +#define mmCP_WAIT_SEM_ADDR_LO 0xc075 +#define mmCP_WAIT_SEM_ADDR_HI 0xc076 +#define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074 +#define mmCP_COHER_START_DELAY 0xc07b +#define mmCP_COHER_CNTL 0xc07c +#define mmCP_COHER_SIZE 0xc07d +#define mmCP_COHER_SIZE_HI 0xc08c +#define mmCP_COHER_BASE 0xc07e +#define mmCP_COHER_BASE_HI 0xc079 +#define mmCP_COHER_STATUS 0xc07f +#define mmCOHER_DEST_BASE_0 0xa092 +#define mmCOHER_DEST_BASE_1 0xa093 +#define mmCOHER_DEST_BASE_2 0xa07e +#define mmCOHER_DEST_BASE_3 0xa07f +#define mmCOHER_DEST_BASE_HI_0 0xa07a +#define mmCOHER_DEST_BASE_HI_1 0xa07b +#define mmCOHER_DEST_BASE_HI_2 0xa07c +#define mmCOHER_DEST_BASE_HI_3 0xa07d +#define mmCP_DMA_ME_SRC_ADDR 0xc080 +#define mmCP_DMA_ME_SRC_ADDR_HI 0xc081 +#define mmCP_DMA_ME_DST_ADDR 0xc082 +#define mmCP_DMA_ME_DST_ADDR_HI 0xc083 +#define mmCP_DMA_ME_CONTROL 0xc078 +#define mmCP_DMA_ME_COMMAND 0xc084 +#define mmCP_DMA_PFP_SRC_ADDR 0xc085 +#define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086 +#define mmCP_DMA_PFP_DST_ADDR 0xc087 +#define mmCP_DMA_PFP_DST_ADDR_HI 0xc088 +#define mmCP_DMA_PFP_CONTROL 0xc077 +#define mmCP_DMA_PFP_COMMAND 0xc089 +#define mmCP_DMA_CNTL 0xc08a +#define mmCP_DMA_READ_TAGS 0xc08b +#define mmCP_PFP_IB_CONTROL 0xc08d +#define mmCP_PFP_LOAD_CONTROL 0xc08e +#define mmCP_SCRATCH_INDEX 0xc08f +#define mmCP_SCRATCH_DATA 0xc090 +#define mmCP_RB_OFFSET 0xc091 +#define mmCP_IB1_OFFSET 0xc092 +#define mmCP_IB2_OFFSET 0xc093 +#define mmCP_IB1_PREAMBLE_BEGIN 0xc094 +#define mmCP_IB1_PREAMBLE_END 0xc095 +#define mmCP_IB2_PREAMBLE_BEGIN 0xc096 +#define mmCP_IB2_PREAMBLE_END 0xc097 +#define mmCP_STALLED_STAT1 0x219d +#define mmCP_STALLED_STAT2 0x219e +#define mmCP_STALLED_STAT3 0x219c +#define mmCP_BUSY_STAT 0x219f +#define mmCP_STAT 0x21a0 +#define mmCP_ME_HEADER_DUMP 0x21a1 +#define mmCP_PFP_HEADER_DUMP 0x21a2 +#define mmCP_GRBM_FREE_COUNT 0x21a3 +#define mmCP_CE_HEADER_DUMP 0x21a4 +#define mmCP_MC_PACK_DELAY_CNT 0x21a7 +#define mmCP_MC_TAG_CNTL 0x21a8 +#define mmCP_MC_TAG_DATA 0x21a9 +#define mmCP_CSF_STAT 0x21b4 +#define mmCP_CSF_CNTL 0x21b5 +#define mmCP_ME_CNTL 0x21b6 +#define mmCP_CNTX_STAT 0x21b8 +#define mmCP_ME_PREEMPTION 0x21b9 +#define mmCP_RB0_RPTR 0x21c0 +#define mmCP_RB_RPTR 0x21c0 +#define mmCP_RB1_RPTR 0x21bf +#define mmCP_RB2_RPTR 0x21be +#define mmCP_RB_WPTR_DELAY 0x21c1 +#define mmCP_RB_WPTR_POLL_CNTL 0x21c2 +#define mmCP_CE_INIT_BASE_LO 0xc0c3 +#define mmCP_CE_INIT_BASE_HI 0xc0c4 +#define mmCP_CE_INIT_BUFSZ 0xc0c5 +#define mmCP_CE_IB1_BASE_LO 0xc0c6 +#define mmCP_CE_IB1_BASE_HI 0xc0c7 +#define mmCP_CE_IB1_BUFSZ 0xc0c8 +#define mmCP_CE_IB2_BASE_LO 0xc0c9 +#define mmCP_CE_IB2_BASE_HI 0xc0ca +#define mmCP_CE_IB2_BUFSZ 0xc0cb +#define mmCP_IB1_BASE_LO 0xc0cc +#define mmCP_IB1_BASE_HI 0xc0cd +#define mmCP_IB1_BUFSZ 0xc0ce +#define mmCP_IB2_BASE_LO 0xc0cf +#define mmCP_IB2_BASE_HI 0xc0d0 +#define mmCP_IB2_BUFSZ 0xc0d1 +#define mmCP_ST_BASE_LO 0xc0d2 +#define mmCP_ST_BASE_HI 0xc0d3 +#define mmCP_ST_BUFSZ 0xc0d4 +#define mmCP_ROQ_THRESHOLDS 0x21bc +#define mmCP_MEQ_STQ_THRESHOLD 0x21bd +#define mmCP_ROQ1_THRESHOLDS 0x21d5 +#define mmCP_ROQ2_THRESHOLDS 0x21d6 +#define mmCP_STQ_THRESHOLDS 0x21d7 +#define mmCP_QUEUE_THRESHOLDS 0x21d8 +#define mmCP_MEQ_THRESHOLDS 0x21d9 +#define mmCP_ROQ_AVAIL 0x21da +#define mmCP_STQ_AVAIL 0x21db +#define mmCP_ROQ2_AVAIL 0x21dc +#define mmCP_MEQ_AVAIL 0x21dd +#define mmCP_CMD_INDEX 0x21de +#define mmCP_CMD_DATA 0x21df +#define mmCP_ROQ_RB_STAT 0x21e0 +#define mmCP_ROQ_IB1_STAT 0x21e1 +#define mmCP_ROQ_IB2_STAT 0x21e2 +#define mmCP_STQ_STAT 0x21e3 +#define mmCP_STQ_WR_STAT 0x21e4 +#define mmCP_MEQ_STAT 0x21e5 +#define mmCP_CEQ1_AVAIL 0x21e6 +#define mmCP_CEQ2_AVAIL 0x21e7 +#define mmCP_CE_ROQ_RB_STAT 0x21e8 +#define mmCP_CE_ROQ_IB1_STAT 0x21e9 +#define mmCP_CE_ROQ_IB2_STAT 0x21ea +#define mmCP_INT_STAT_DEBUG 0x21f7 +#define mmCP_PERFMON_CNTL 0xd808 +#define mmCP_PERFMON_CNTX_CNTL 0xa0d8 +#define mmCP_RINGID 0xa0d9 +#define mmCP_PIPEID 0xa0d9 +#define mmCP_VMID 0xa0da +#define mmCP_HPD_ROQ_OFFSETS 0x3240 +#define mmCP_HPD_EOP_BASE_ADDR 0x3241 +#define mmCP_HPD_EOP_BASE_ADDR_HI 0x3242 +#define mmCP_HPD_EOP_VMID 0x3243 +#define mmCP_HPD_EOP_CONTROL 0x3244 +#define mmCP_MQD_BASE_ADDR 0x3245 +#define mmCP_MQD_BASE_ADDR_HI 0x3246 +#define mmCP_HQD_ACTIVE 0x3247 +#define mmCP_HQD_VMID 0x3248 +#define mmCP_HQD_PERSISTENT_STATE 0x3249 +#define mmCP_HQD_PIPE_PRIORITY 0x324a +#define mmCP_HQD_QUEUE_PRIORITY 0x324b +#define mmCP_HQD_QUANTUM 0x324c +#define mmCP_HQD_PQ_BASE 0x324d +#define mmCP_HQD_PQ_BASE_HI 0x324e +#define mmCP_HQD_PQ_RPTR 0x324f +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 +#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 +#define mmCP_HQD_PQ_WPTR 0x3255 +#define mmCP_HQD_PQ_CONTROL 0x3256 +#define mmCP_HQD_IB_BASE_ADDR 0x3257 +#define mmCP_HQD_IB_BASE_ADDR_HI 0x3258 +#define mmCP_HQD_IB_RPTR 0x3259 +#define mmCP_HQD_IB_CONTROL 0x325a +#define mmCP_HQD_IQ_TIMER 0x325b +#define mmCP_HQD_IQ_RPTR 0x325c +#define mmCP_HQD_DEQUEUE_REQUEST 0x325d +#define mmCP_HQD_DMA_OFFLOAD 0x325e +#define mmCP_HQD_SEMA_CMD 0x325f +#define mmCP_HQD_MSG_TYPE 0x3260 +#define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261 +#define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262 +#define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263 +#define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264 +#define mmCP_HQD_HQ_SCHEDULER0 0x3265 +#define mmCP_HQD_HQ_SCHEDULER1 0x3266 +#define mmCP_MQD_CONTROL 0x3267 +#define mmDB_Z_READ_BASE 0xa012 +#define mmDB_STENCIL_READ_BASE 0xa013 +#define mmDB_Z_WRITE_BASE 0xa014 +#define mmDB_STENCIL_WRITE_BASE 0xa015 +#define mmDB_DEPTH_INFO 0xa00f +#define mmDB_Z_INFO 0xa010 +#define mmDB_STENCIL_INFO 0xa011 +#define mmDB_DEPTH_SIZE 0xa016 +#define mmDB_DEPTH_SLICE 0xa017 +#define mmDB_DEPTH_VIEW 0xa002 +#define mmDB_RENDER_CONTROL 0xa000 +#define mmDB_COUNT_CONTROL 0xa001 +#define mmDB_RENDER_OVERRIDE 0xa003 +#define mmDB_RENDER_OVERRIDE2 0xa004 +#define mmDB_EQAA 0xa201 +#define mmDB_SHADER_CONTROL 0xa203 +#define mmDB_DEPTH_BOUNDS_MIN 0xa008 +#define mmDB_DEPTH_BOUNDS_MAX 0xa009 +#define mmDB_STENCIL_CLEAR 0xa00a +#define mmDB_DEPTH_CLEAR 0xa00b +#define mmDB_HTILE_DATA_BASE 0xa005 +#define mmDB_HTILE_SURFACE 0xa2af +#define mmDB_PRELOAD_CONTROL 0xa2b2 +#define mmDB_STENCILREFMASK 0xa10c +#define mmDB_STENCILREFMASK_BF 0xa10d +#define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0 +#define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1 +#define mmDB_DEPTH_CONTROL 0xa200 +#define mmDB_STENCIL_CONTROL 0xa10b +#define mmDB_ALPHA_TO_MASK 0xa2dc +#define mmDB_PERFCOUNTER0_SELECT 0xdc40 +#define mmDB_PERFCOUNTER1_SELECT 0xdc42 +#define mmDB_PERFCOUNTER2_SELECT 0xdc44 +#define mmDB_PERFCOUNTER3_SELECT 0xdc46 +#define mmDB_PERFCOUNTER0_SELECT1 0xdc41 +#define mmDB_PERFCOUNTER1_SELECT1 0xdc43 +#define mmDB_PERFCOUNTER0_LO 0xd440 +#define mmDB_PERFCOUNTER1_LO 0xd442 +#define mmDB_PERFCOUNTER2_LO 0xd444 +#define mmDB_PERFCOUNTER3_LO 0xd446 +#define mmDB_PERFCOUNTER0_HI 0xd441 +#define mmDB_PERFCOUNTER1_HI 0xd443 +#define mmDB_PERFCOUNTER2_HI 0xd445 +#define mmDB_PERFCOUNTER3_HI 0xd447 +#define mmDB_DEBUG 0x260c +#define mmDB_DEBUG2 0x260d +#define mmDB_DEBUG3 0x260e +#define mmDB_DEBUG4 0x260f +#define mmDB_CREDIT_LIMIT 0x2614 +#define mmDB_WATERMARKS 0x2615 +#define mmDB_SUBTILE_CONTROL 0x2616 +#define mmDB_FREE_CACHELINES 0x2617 +#define mmDB_FIFO_DEPTH1 0x2618 +#define mmDB_FIFO_DEPTH2 0x2619 +#define mmDB_CGTT_CLK_CTRL_0 0xf0a4 +#define mmDB_ZPASS_COUNT_LOW 0xc3fe +#define mmDB_ZPASS_COUNT_HI 0xc3ff +#define mmDB_RING_CONTROL 0x261b +#define mmDB_READ_DEBUG_0 0x2620 +#define mmDB_READ_DEBUG_1 0x2621 +#define mmDB_READ_DEBUG_2 0x2622 +#define mmDB_READ_DEBUG_3 0x2623 +#define mmDB_READ_DEBUG_4 0x2624 +#define mmDB_READ_DEBUG_5 0x2625 +#define mmDB_READ_DEBUG_6 0x2626 +#define mmDB_READ_DEBUG_7 0x2627 +#define mmDB_READ_DEBUG_8 0x2628 +#define mmDB_READ_DEBUG_9 0x2629 +#define mmDB_READ_DEBUG_A 0x262a +#define mmDB_READ_DEBUG_B 0x262b +#define mmDB_READ_DEBUG_C 0x262c +#define mmDB_READ_DEBUG_D 0x262d +#define mmDB_READ_DEBUG_E 0x262e +#define mmDB_READ_DEBUG_F 0x262f +#define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0 +#define mmDB_OCCLUSION_COUNT0_HI 0xc3c1 +#define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2 +#define mmDB_OCCLUSION_COUNT1_HI 0xc3c3 +#define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4 +#define mmDB_OCCLUSION_COUNT2_HI 0xc3c5 +#define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6 +#define mmDB_OCCLUSION_COUNT3_HI 0xc3c7 +#define mmCC_RB_REDUNDANCY 0x263c +#define mmCC_RB_BACKEND_DISABLE 0x263d +#define mmGC_USER_RB_REDUNDANCY 0x26de +#define mmGC_USER_RB_BACKEND_DISABLE 0x26df +#define mmGB_ADDR_CONFIG 0x263e +#define mmGB_BACKEND_MAP 0x263f +#define mmGB_GPU_ID 0x2640 +#define mmCC_RB_DAISY_CHAIN 0x2641 +#define mmGB_TILE_MODE0 0x2644 +#define mmGB_TILE_MODE1 0x2645 +#define mmGB_TILE_MODE2 0x2646 +#define mmGB_TILE_MODE3 0x2647 +#define mmGB_TILE_MODE4 0x2648 +#define mmGB_TILE_MODE5 0x2649 +#define mmGB_TILE_MODE6 0x264a +#define mmGB_TILE_MODE7 0x264b +#define mmGB_TILE_MODE8 0x264c +#define mmGB_TILE_MODE9 0x264d +#define mmGB_TILE_MODE10 0x264e +#define mmGB_TILE_MODE11 0x264f +#define mmGB_TILE_MODE12 0x2650 +#define mmGB_TILE_MODE13 0x2651 +#define mmGB_TILE_MODE14 0x2652 +#define mmGB_TILE_MODE15 0x2653 +#define mmGB_TILE_MODE16 0x2654 +#define mmGB_TILE_MODE17 0x2655 +#define mmGB_TILE_MODE18 0x2656 +#define mmGB_TILE_MODE19 0x2657 +#define mmGB_TILE_MODE20 0x2658 +#define mmGB_TILE_MODE21 0x2659 +#define mmGB_TILE_MODE22 0x265a +#define mmGB_TILE_MODE23 0x265b +#define mmGB_TILE_MODE24 0x265c +#define mmGB_TILE_MODE25 0x265d +#define mmGB_TILE_MODE26 0x265e +#define mmGB_TILE_MODE27 0x265f +#define mmGB_TILE_MODE28 0x2660 +#define mmGB_TILE_MODE29 0x2661 +#define mmGB_TILE_MODE30 0x2662 +#define mmGB_TILE_MODE31 0x2663 +#define mmGB_MACROTILE_MODE0 0x2664 +#define mmGB_MACROTILE_MODE1 0x2665 +#define mmGB_MACROTILE_MODE2 0x2666 +#define mmGB_MACROTILE_MODE3 0x2667 +#define mmGB_MACROTILE_MODE4 0x2668 +#define mmGB_MACROTILE_MODE5 0x2669 +#define mmGB_MACROTILE_MODE6 0x266a +#define mmGB_MACROTILE_MODE7 0x266b +#define mmGB_MACROTILE_MODE8 0x266c +#define mmGB_MACROTILE_MODE9 0x266d +#define mmGB_MACROTILE_MODE10 0x266e +#define mmGB_MACROTILE_MODE11 0x266f +#define mmGB_MACROTILE_MODE12 0x2670 +#define mmGB_MACROTILE_MODE13 0x2671 +#define mmGB_MACROTILE_MODE14 0x2672 +#define mmGB_MACROTILE_MODE15 0x2673 +#define mmGB_EDC_MODE 0x307e +#define mmCC_GC_EDC_CONFIG 0x3098 +#define mmRAS_SIGNATURE_CONTROL 0x3380 +#define mmRAS_SIGNATURE_MASK 0x3381 +#define mmRAS_SX_SIGNATURE0 0x3382 +#define mmRAS_SX_SIGNATURE1 0x3383 +#define mmRAS_SX_SIGNATURE2 0x3384 +#define mmRAS_SX_SIGNATURE3 0x3385 +#define mmRAS_DB_SIGNATURE0 0x338b +#define mmRAS_PA_SIGNATURE0 0x338c +#define mmRAS_VGT_SIGNATURE0 0x338d +#define mmRAS_SQ_SIGNATURE0 0x338e +#define mmRAS_SC_SIGNATURE0 0x338f +#define mmRAS_SC_SIGNATURE1 0x3390 +#define mmRAS_SC_SIGNATURE2 0x3391 +#define mmRAS_SC_SIGNATURE3 0x3392 +#define mmRAS_SC_SIGNATURE4 0x3393 +#define mmRAS_SC_SIGNATURE5 0x3394 +#define mmRAS_SC_SIGNATURE6 0x3395 +#define mmRAS_SC_SIGNATURE7 0x3396 +#define mmRAS_IA_SIGNATURE0 0x3397 +#define mmRAS_IA_SIGNATURE1 0x3398 +#define mmRAS_SPI_SIGNATURE0 0x3399 +#define mmRAS_SPI_SIGNATURE1 0x339a +#define mmRAS_TA_SIGNATURE0 0x339b +#define mmRAS_TD_SIGNATURE0 0x339c +#define mmRAS_CB_SIGNATURE0 0x339d +#define mmRAS_BCI_SIGNATURE0 0x339e +#define mmRAS_BCI_SIGNATURE1 0x339f +#define mmGRBM_CAM_INDEX 0x3000 +#define mmGRBM_CAM_DATA 0x3001 +#define mmGRBM_CNTL 0x2000 +#define mmGRBM_SKEW_CNTL 0x2001 +#define mmGRBM_PWR_CNTL 0x2003 +#define mmGRBM_STATUS 0x2004 +#define mmGRBM_STATUS2 0x2002 +#define mmGRBM_STATUS_SE0 0x2005 +#define mmGRBM_STATUS_SE1 0x2006 +#define mmGRBM_STATUS_SE2 0x200e +#define mmGRBM_STATUS_SE3 0x200f +#define mmGRBM_SOFT_RESET 0x2008 +#define mmGRBM_DEBUG_CNTL 0x2009 +#define mmGRBM_DEBUG_DATA 0x200a +#define mmGRBM_GFX_INDEX 0xc200 +#define mmGRBM_GFX_CLKEN_CNTL 0x200c +#define mmGRBM_WAIT_IDLE_CLOCKS 0x200d +#define mmGRBM_DEBUG 0x2014 +#define mmGRBM_DEBUG_SNAPSHOT 0x2015 +#define mmGRBM_READ_ERROR 0x2016 +#define mmGRBM_READ_ERROR2 0x2017 +#define mmGRBM_INT_CNTL 0x2018 +#define mmGRBM_PERFCOUNTER0_SELECT 0xd840 +#define mmGRBM_PERFCOUNTER1_SELECT 0xd841 +#define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842 +#define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843 +#define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844 +#define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845 +#define mmGRBM_PERFCOUNTER0_LO 0xd040 +#define mmGRBM_PERFCOUNTER0_HI 0xd041 +#define mmGRBM_PERFCOUNTER1_LO 0xd043 +#define mmGRBM_PERFCOUNTER1_HI 0xd044 +#define mmGRBM_SE0_PERFCOUNTER_LO 0xd045 +#define mmGRBM_SE0_PERFCOUNTER_HI 0xd046 +#define mmGRBM_SE1_PERFCOUNTER_LO 0xd047 +#define mmGRBM_SE1_PERFCOUNTER_HI 0xd048 +#define mmGRBM_SE2_PERFCOUNTER_LO 0xd049 +#define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a +#define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b +#define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c +#define mmGRBM_SCRATCH_REG0 0x2040 +#define mmGRBM_SCRATCH_REG1 0x2041 +#define mmGRBM_SCRATCH_REG2 0x2042 +#define mmGRBM_SCRATCH_REG3 0x2043 +#define mmGRBM_SCRATCH_REG4 0x2044 +#define mmGRBM_SCRATCH_REG5 0x2045 +#define mmGRBM_SCRATCH_REG6 0x2046 +#define mmGRBM_SCRATCH_REG7 0x2047 +#define mmDEBUG_INDEX 0x203c +#define mmDEBUG_DATA 0x203d +#define mmGRBM_NOWHERE 0x203f +#define mmPA_CL_VPORT_XSCALE 0xa10f +#define mmPA_CL_VPORT_XOFFSET 0xa110 +#define mmPA_CL_VPORT_YSCALE 0xa111 +#define mmPA_CL_VPORT_YOFFSET 0xa112 +#define mmPA_CL_VPORT_ZSCALE 0xa113 +#define mmPA_CL_VPORT_ZOFFSET 0xa114 +#define mmPA_CL_VPORT_XSCALE_1 0xa115 +#define mmPA_CL_VPORT_XSCALE_2 0xa11b +#define mmPA_CL_VPORT_XSCALE_3 0xa121 +#define mmPA_CL_VPORT_XSCALE_4 0xa127 +#define mmPA_CL_VPORT_XSCALE_5 0xa12d +#define mmPA_CL_VPORT_XSCALE_6 0xa133 +#define mmPA_CL_VPORT_XSCALE_7 0xa139 +#define mmPA_CL_VPORT_XSCALE_8 0xa13f +#define mmPA_CL_VPORT_XSCALE_9 0xa145 +#define mmPA_CL_VPORT_XSCALE_10 0xa14b +#define mmPA_CL_VPORT_XSCALE_11 0xa151 +#define mmPA_CL_VPORT_XSCALE_12 0xa157 +#define mmPA_CL_VPORT_XSCALE_13 0xa15d +#define mmPA_CL_VPORT_XSCALE_14 0xa163 +#define mmPA_CL_VPORT_XSCALE_15 0xa169 +#define mmPA_CL_VPORT_XOFFSET_1 0xa116 +#define mmPA_CL_VPORT_XOFFSET_2 0xa11c +#define mmPA_CL_VPORT_XOFFSET_3 0xa122 +#define mmPA_CL_VPORT_XOFFSET_4 0xa128 +#define mmPA_CL_VPORT_XOFFSET_5 0xa12e +#define mmPA_CL_VPORT_XOFFSET_6 0xa134 +#define mmPA_CL_VPORT_XOFFSET_7 0xa13a +#define mmPA_CL_VPORT_XOFFSET_8 0xa140 +#define mmPA_CL_VPORT_XOFFSET_9 0xa146 +#define mmPA_CL_VPORT_XOFFSET_10 0xa14c +#define mmPA_CL_VPORT_XOFFSET_11 0xa152 +#define mmPA_CL_VPORT_XOFFSET_12 0xa158 +#define mmPA_CL_VPORT_XOFFSET_13 0xa15e +#define mmPA_CL_VPORT_XOFFSET_14 0xa164 +#define mmPA_CL_VPORT_XOFFSET_15 0xa16a +#define mmPA_CL_VPORT_YSCALE_1 0xa117 +#define mmPA_CL_VPORT_YSCALE_2 0xa11d +#define mmPA_CL_VPORT_YSCALE_3 0xa123 +#define mmPA_CL_VPORT_YSCALE_4 0xa129 +#define mmPA_CL_VPORT_YSCALE_5 0xa12f +#define mmPA_CL_VPORT_YSCALE_6 0xa135 +#define mmPA_CL_VPORT_YSCALE_7 0xa13b +#define mmPA_CL_VPORT_YSCALE_8 0xa141 +#define mmPA_CL_VPORT_YSCALE_9 0xa147 +#define mmPA_CL_VPORT_YSCALE_10 0xa14d +#define mmPA_CL_VPORT_YSCALE_11 0xa153 +#define mmPA_CL_VPORT_YSCALE_12 0xa159 +#define mmPA_CL_VPORT_YSCALE_13 0xa15f +#define mmPA_CL_VPORT_YSCALE_14 0xa165 +#define mmPA_CL_VPORT_YSCALE_15 0xa16b +#define mmPA_CL_VPORT_YOFFSET_1 0xa118 +#define mmPA_CL_VPORT_YOFFSET_2 0xa11e +#define mmPA_CL_VPORT_YOFFSET_3 0xa124 +#define mmPA_CL_VPORT_YOFFSET_4 0xa12a +#define mmPA_CL_VPORT_YOFFSET_5 0xa130 +#define mmPA_CL_VPORT_YOFFSET_6 0xa136 +#define mmPA_CL_VPORT_YOFFSET_7 0xa13c +#define mmPA_CL_VPORT_YOFFSET_8 0xa142 +#define mmPA_CL_VPORT_YOFFSET_9 0xa148 +#define mmPA_CL_VPORT_YOFFSET_10 0xa14e +#define mmPA_CL_VPORT_YOFFSET_11 0xa154 +#define mmPA_CL_VPORT_YOFFSET_12 0xa15a +#define mmPA_CL_VPORT_YOFFSET_13 0xa160 +#define mmPA_CL_VPORT_YOFFSET_14 0xa166 +#define mmPA_CL_VPORT_YOFFSET_15 0xa16c +#define mmPA_CL_VPORT_ZSCALE_1 0xa119 +#define mmPA_CL_VPORT_ZSCALE_2 0xa11f +#define mmPA_CL_VPORT_ZSCALE_3 0xa125 +#define mmPA_CL_VPORT_ZSCALE_4 0xa12b +#define mmPA_CL_VPORT_ZSCALE_5 0xa131 +#define mmPA_CL_VPORT_ZSCALE_6 0xa137 +#define mmPA_CL_VPORT_ZSCALE_7 0xa13d +#define mmPA_CL_VPORT_ZSCALE_8 0xa143 +#define mmPA_CL_VPORT_ZSCALE_9 0xa149 +#define mmPA_CL_VPORT_ZSCALE_10 0xa14f +#define mmPA_CL_VPORT_ZSCALE_11 0xa155 +#define mmPA_CL_VPORT_ZSCALE_12 0xa15b +#define mmPA_CL_VPORT_ZSCALE_13 0xa161 +#define mmPA_CL_VPORT_ZSCALE_14 0xa167 +#define mmPA_CL_VPORT_ZSCALE_15 0xa16d +#define mmPA_CL_VPORT_ZOFFSET_1 0xa11a +#define mmPA_CL_VPORT_ZOFFSET_2 0xa120 +#define mmPA_CL_VPORT_ZOFFSET_3 0xa126 +#define mmPA_CL_VPORT_ZOFFSET_4 0xa12c +#define mmPA_CL_VPORT_ZOFFSET_5 0xa132 +#define mmPA_CL_VPORT_ZOFFSET_6 0xa138 +#define mmPA_CL_VPORT_ZOFFSET_7 0xa13e +#define mmPA_CL_VPORT_ZOFFSET_8 0xa144 +#define mmPA_CL_VPORT_ZOFFSET_9 0xa14a +#define mmPA_CL_VPORT_ZOFFSET_10 0xa150 +#define mmPA_CL_VPORT_ZOFFSET_11 0xa156 +#define mmPA_CL_VPORT_ZOFFSET_12 0xa15c +#define mmPA_CL_VPORT_ZOFFSET_13 0xa162 +#define mmPA_CL_VPORT_ZOFFSET_14 0xa168 +#define mmPA_CL_VPORT_ZOFFSET_15 0xa16e +#define mmPA_CL_VTE_CNTL 0xa206 +#define mmPA_CL_VS_OUT_CNTL 0xa207 +#define mmPA_CL_NANINF_CNTL 0xa208 +#define mmPA_CL_CLIP_CNTL 0xa204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa +#define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc +#define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd +#define mmPA_CL_UCP_0_X 0xa16f +#define mmPA_CL_UCP_0_Y 0xa170 +#define mmPA_CL_UCP_0_Z 0xa171 +#define mmPA_CL_UCP_0_W 0xa172 +#define mmPA_CL_UCP_1_X 0xa173 +#define mmPA_CL_UCP_1_Y 0xa174 +#define mmPA_CL_UCP_1_Z 0xa175 +#define mmPA_CL_UCP_1_W 0xa176 +#define mmPA_CL_UCP_2_X 0xa177 +#define mmPA_CL_UCP_2_Y 0xa178 +#define mmPA_CL_UCP_2_Z 0xa179 +#define mmPA_CL_UCP_2_W 0xa17a +#define mmPA_CL_UCP_3_X 0xa17b +#define mmPA_CL_UCP_3_Y 0xa17c +#define mmPA_CL_UCP_3_Z 0xa17d +#define mmPA_CL_UCP_3_W 0xa17e +#define mmPA_CL_UCP_4_X 0xa17f +#define mmPA_CL_UCP_4_Y 0xa180 +#define mmPA_CL_UCP_4_Z 0xa181 +#define mmPA_CL_UCP_4_W 0xa182 +#define mmPA_CL_UCP_5_X 0xa183 +#define mmPA_CL_UCP_5_Y 0xa184 +#define mmPA_CL_UCP_5_Z 0xa185 +#define mmPA_CL_UCP_5_W 0xa186 +#define mmPA_CL_POINT_X_RAD 0xa1f5 +#define mmPA_CL_POINT_Y_RAD 0xa1f6 +#define mmPA_CL_POINT_SIZE 0xa1f7 +#define mmPA_CL_POINT_CULL_RAD 0xa1f8 +#define mmPA_CL_ENHANCE 0x2285 +#define mmPA_CL_RESET_DEBUG 0x2286 +#define mmPA_SU_VTX_CNTL 0xa2f9 +#define mmPA_SU_POINT_SIZE 0xa280 +#define mmPA_SU_POINT_MINMAX 0xa281 +#define mmPA_SU_LINE_CNTL 0xa282 +#define mmPA_SU_LINE_STIPPLE_CNTL 0xa209 +#define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a +#define mmPA_SU_PRIM_FILTER_CNTL 0xa20b +#define mmPA_SU_SC_MODE_CNTL 0xa205 +#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de +#define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3 +#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d +#define mmPA_SU_LINE_STIPPLE_VALUE 0xc280 +#define mmPA_SU_PERFCOUNTER0_SELECT 0xd900 +#define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901 +#define mmPA_SU_PERFCOUNTER1_SELECT 0xd902 +#define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903 +#define mmPA_SU_PERFCOUNTER2_SELECT 0xd904 +#define mmPA_SU_PERFCOUNTER3_SELECT 0xd905 +#define mmPA_SU_PERFCOUNTER0_LO 0xd100 +#define mmPA_SU_PERFCOUNTER0_HI 0xd101 +#define mmPA_SU_PERFCOUNTER1_LO 0xd102 +#define mmPA_SU_PERFCOUNTER1_HI 0xd103 +#define mmPA_SU_PERFCOUNTER2_LO 0xd104 +#define mmPA_SU_PERFCOUNTER2_HI 0xd105 +#define mmPA_SU_PERFCOUNTER3_LO 0xd106 +#define mmPA_SU_PERFCOUNTER3_HI 0xd107 +#define mmPA_SC_AA_CONFIG 0xa2f8 +#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e +#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d +#define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5 +#define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6 +#define mmPA_SC_CLIPRECT_0_TL 0xa084 +#define mmPA_SC_CLIPRECT_0_BR 0xa085 +#define mmPA_SC_CLIPRECT_1_TL 0xa086 +#define mmPA_SC_CLIPRECT_1_BR 0xa087 +#define mmPA_SC_CLIPRECT_2_TL 0xa088 +#define mmPA_SC_CLIPRECT_2_BR 0xa089 +#define mmPA_SC_CLIPRECT_3_TL 0xa08a +#define mmPA_SC_CLIPRECT_3_BR 0xa08b +#define mmPA_SC_CLIPRECT_RULE 0xa083 +#define mmPA_SC_EDGERULE 0xa08c +#define mmPA_SC_LINE_CNTL 0xa2f7 +#define mmPA_SC_LINE_STIPPLE 0xa283 +#define mmPA_SC_MODE_CNTL_0 0xa292 +#define mmPA_SC_MODE_CNTL_1 0xa293 +#define mmPA_SC_RASTER_CONFIG 0xa0d4 +#define mmPA_SC_RASTER_CONFIG_1 0xa0d5 +#define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6 +#define mmPA_SC_GENERIC_SCISSOR_TL 0xa090 +#define mmPA_SC_GENERIC_SCISSOR_BR 0xa091 +#define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c +#define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d +#define mmPA_SC_WINDOW_OFFSET 0xa080 +#define mmPA_SC_WINDOW_SCISSOR_TL 0xa081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0xa082 +#define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094 +#define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096 +#define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098 +#define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a +#define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c +#define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e +#define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0 +#define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2 +#define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4 +#define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6 +#define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8 +#define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa +#define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac +#define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae +#define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0 +#define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2 +#define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095 +#define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097 +#define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099 +#define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b +#define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d +#define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f +#define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1 +#define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3 +#define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5 +#define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7 +#define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9 +#define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab +#define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad +#define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af +#define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1 +#define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3 +#define mmPA_SC_VPORT_ZMIN_0 0xa0b4 +#define mmPA_SC_VPORT_ZMIN_1 0xa0b6 +#define mmPA_SC_VPORT_ZMIN_2 0xa0b8 +#define mmPA_SC_VPORT_ZMIN_3 0xa0ba +#define mmPA_SC_VPORT_ZMIN_4 0xa0bc +#define mmPA_SC_VPORT_ZMIN_5 0xa0be +#define mmPA_SC_VPORT_ZMIN_6 0xa0c0 +#define mmPA_SC_VPORT_ZMIN_7 0xa0c2 +#define mmPA_SC_VPORT_ZMIN_8 0xa0c4 +#define mmPA_SC_VPORT_ZMIN_9 0xa0c6 +#define mmPA_SC_VPORT_ZMIN_10 0xa0c8 +#define mmPA_SC_VPORT_ZMIN_11 0xa0ca +#define mmPA_SC_VPORT_ZMIN_12 0xa0cc +#define mmPA_SC_VPORT_ZMIN_13 0xa0ce +#define mmPA_SC_VPORT_ZMIN_14 0xa0d0 +#define mmPA_SC_VPORT_ZMIN_15 0xa0d2 +#define mmPA_SC_VPORT_ZMAX_0 0xa0b5 +#define mmPA_SC_VPORT_ZMAX_1 0xa0b7 +#define mmPA_SC_VPORT_ZMAX_2 0xa0b9 +#define mmPA_SC_VPORT_ZMAX_3 0xa0bb +#define mmPA_SC_VPORT_ZMAX_4 0xa0bd +#define mmPA_SC_VPORT_ZMAX_5 0xa0bf +#define mmPA_SC_VPORT_ZMAX_6 0xa0c1 +#define mmPA_SC_VPORT_ZMAX_7 0xa0c3 +#define mmPA_SC_VPORT_ZMAX_8 0xa0c5 +#define mmPA_SC_VPORT_ZMAX_9 0xa0c7 +#define mmPA_SC_VPORT_ZMAX_10 0xa0c9 +#define mmPA_SC_VPORT_ZMAX_11 0xa0cb +#define mmPA_SC_VPORT_ZMAX_12 0xa0cd +#define mmPA_SC_VPORT_ZMAX_13 0xa0cf +#define mmPA_SC_VPORT_ZMAX_14 0xa0d1 +#define mmPA_SC_VPORT_ZMAX_15 0xa0d3 +#define mmPA_SC_ENHANCE 0x22fc +#define mmPA_SC_FIFO_SIZE 0x22f3 +#define mmPA_SC_IF_FIFO_SIZE 0x22f5 +#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9 +#define mmPA_SC_LINE_STIPPLE_STATE 0xc281 +#define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284 +#define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285 +#define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286 +#define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b +#define mmPA_SC_PERFCOUNTER0_SELECT 0xd940 +#define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941 +#define mmPA_SC_PERFCOUNTER1_SELECT 0xd942 +#define mmPA_SC_PERFCOUNTER2_SELECT 0xd943 +#define mmPA_SC_PERFCOUNTER3_SELECT 0xd944 +#define mmPA_SC_PERFCOUNTER4_SELECT 0xd945 +#define mmPA_SC_PERFCOUNTER5_SELECT 0xd946 +#define mmPA_SC_PERFCOUNTER6_SELECT 0xd947 +#define mmPA_SC_PERFCOUNTER7_SELECT 0xd948 +#define mmPA_SC_PERFCOUNTER0_LO 0xd140 +#define mmPA_SC_PERFCOUNTER0_HI 0xd141 +#define mmPA_SC_PERFCOUNTER1_LO 0xd142 +#define mmPA_SC_PERFCOUNTER1_HI 0xd143 +#define mmPA_SC_PERFCOUNTER2_LO 0xd144 +#define mmPA_SC_PERFCOUNTER2_HI 0xd145 +#define mmPA_SC_PERFCOUNTER3_LO 0xd146 +#define mmPA_SC_PERFCOUNTER3_HI 0xd147 +#define mmPA_SC_PERFCOUNTER4_LO 0xd148 +#define mmPA_SC_PERFCOUNTER4_HI 0xd149 +#define mmPA_SC_PERFCOUNTER5_LO 0xd14a +#define mmPA_SC_PERFCOUNTER5_HI 0xd14b +#define mmPA_SC_PERFCOUNTER6_LO 0xd14c +#define mmPA_SC_PERFCOUNTER6_HI 0xd14d +#define mmPA_SC_PERFCOUNTER7_LO 0xd14e +#define mmPA_SC_PERFCOUNTER7_HI 0xd14f +#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0 +#define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1 +#define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2 +#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3 +#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8 +#define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9 +#define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa +#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab +#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac +#define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0 +#define mmPA_SC_TRAP_SCREEN_H 0xc2b1 +#define mmPA_SC_TRAP_SCREEN_V 0xc2b2 +#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3 +#define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4 +#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1 +#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2 +#define mmPA_CL_CNTL_STATUS 0x2284 +#define mmPA_SU_CNTL_STATUS 0x2294 +#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 +#define mmCGTT_PA_CLK_CTRL 0xf088 +#define mmCGTT_SC_CLK_CTRL 0xf089 +#define mmPA_SU_DEBUG_CNTL 0x2280 +#define mmPA_SU_DEBUG_DATA 0x2281 +#define mmPA_SC_DEBUG_CNTL 0x22f6 +#define mmPA_SC_DEBUG_DATA 0x22f7 +#define ixCLIPPER_DEBUG_REG00 0x0 +#define ixCLIPPER_DEBUG_REG01 0x1 +#define ixCLIPPER_DEBUG_REG02 0x2 +#define ixCLIPPER_DEBUG_REG03 0x3 +#define ixCLIPPER_DEBUG_REG04 0x4 +#define ixCLIPPER_DEBUG_REG05 0x5 +#define ixCLIPPER_DEBUG_REG06 0x6 +#define ixCLIPPER_DEBUG_REG07 0x7 +#define ixCLIPPER_DEBUG_REG08 0x8 +#define ixCLIPPER_DEBUG_REG09 0x9 +#define ixCLIPPER_DEBUG_REG10 0xa +#define ixCLIPPER_DEBUG_REG11 0xb +#define ixCLIPPER_DEBUG_REG12 0xc +#define ixCLIPPER_DEBUG_REG13 0xd +#define ixCLIPPER_DEBUG_REG14 0xe +#define ixCLIPPER_DEBUG_REG15 0xf +#define ixCLIPPER_DEBUG_REG16 0x10 +#define ixCLIPPER_DEBUG_REG17 0x11 +#define ixCLIPPER_DEBUG_REG18 0x12 +#define ixCLIPPER_DEBUG_REG19 0x13 +#define ixSXIFCCG_DEBUG_REG0 0x14 +#define ixSXIFCCG_DEBUG_REG1 0x15 +#define ixSXIFCCG_DEBUG_REG2 0x16 +#define ixSXIFCCG_DEBUG_REG3 0x17 +#define ixSETUP_DEBUG_REG0 0x18 +#define ixSETUP_DEBUG_REG1 0x19 +#define ixSETUP_DEBUG_REG2 0x1a +#define ixSETUP_DEBUG_REG3 0x1b +#define ixSETUP_DEBUG_REG4 0x1c +#define ixSETUP_DEBUG_REG5 0x1d +#define ixPA_SC_DEBUG_REG0 0x0 +#define ixPA_SC_DEBUG_REG1 0x1 +#define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00 +#define mmCOMPUTE_DIM_X 0x2e01 +#define mmCOMPUTE_DIM_Y 0x2e02 +#define mmCOMPUTE_DIM_Z 0x2e03 +#define mmCOMPUTE_START_X 0x2e04 +#define mmCOMPUTE_START_Y 0x2e05 +#define mmCOMPUTE_START_Z 0x2e06 +#define mmCOMPUTE_NUM_THREAD_X 0x2e07 +#define mmCOMPUTE_NUM_THREAD_Y 0x2e08 +#define mmCOMPUTE_NUM_THREAD_Z 0x2e09 +#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a +#define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b +#define mmCOMPUTE_PGM_LO 0x2e0c +#define mmCOMPUTE_PGM_HI 0x2e0d +#define mmCOMPUTE_TBA_LO 0x2e0e +#define mmCOMPUTE_TBA_HI 0x2e0f +#define mmCOMPUTE_TMA_LO 0x2e10 +#define mmCOMPUTE_TMA_HI 0x2e11 +#define mmCOMPUTE_PGM_RSRC1 0x2e12 +#define mmCOMPUTE_PGM_RSRC2 0x2e13 +#define mmCOMPUTE_VMID 0x2e14 +#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17 +#define mmCOMPUTE_TMPRING_SIZE 0x2e18 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a +#define mmCOMPUTE_RESTART_X 0x2e1b +#define mmCOMPUTE_RESTART_Y 0x2e1c +#define mmCOMPUTE_RESTART_Z 0x2e1d +#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e +#define mmCOMPUTE_MISC_RESERVED 0x2e1f +#define mmCOMPUTE_USER_DATA_0 0x2e40 +#define mmCOMPUTE_USER_DATA_1 0x2e41 +#define mmCOMPUTE_USER_DATA_2 0x2e42 +#define mmCOMPUTE_USER_DATA_3 0x2e43 +#define mmCOMPUTE_USER_DATA_4 0x2e44 +#define mmCOMPUTE_USER_DATA_5 0x2e45 +#define mmCOMPUTE_USER_DATA_6 0x2e46 +#define mmCOMPUTE_USER_DATA_7 0x2e47 +#define mmCOMPUTE_USER_DATA_8 0x2e48 +#define mmCOMPUTE_USER_DATA_9 0x2e49 +#define mmCOMPUTE_USER_DATA_10 0x2e4a +#define mmCOMPUTE_USER_DATA_11 0x2e4b +#define mmCOMPUTE_USER_DATA_12 0x2e4c +#define mmCOMPUTE_USER_DATA_13 0x2e4d +#define mmCOMPUTE_USER_DATA_14 0x2e4e +#define mmCOMPUTE_USER_DATA_15 0x2e4f +#define mmCSPRIV_CONNECT 0x0 +#define mmCSPRIV_THREAD_TRACE_TG0 0x1e +#define mmCSPRIV_THREAD_TRACE_TG1 0x1e +#define mmCSPRIV_THREAD_TRACE_TG2 0x1e +#define mmCSPRIV_THREAD_TRACE_TG3 0x1e +#define mmCSPRIV_THREAD_TRACE_EVENT 0x1f +#define mmRLC_CNTL 0x30c0 +#define mmRLC_DEBUG_SELECT 0x30c1 +#define mmRLC_DEBUG 0x30c2 +#define mmRLC_MC_CNTL 0x30c3 +#define mmRLC_STAT 0x30c4 +#define mmRLC_SAFE_MODE 0x313a +#define mmRLC_SOFT_RESET_GPU 0x30c5 +#define mmRLC_MEM_SLP_CNTL 0x30c6 +#define mmRLC_PERFMON_CNTL 0xdcc0 +#define mmRLC_PERFCOUNTER0_SELECT 0xdcc1 +#define mmRLC_PERFCOUNTER1_SELECT 0xdcc2 +#define mmRLC_PERFCOUNTER0_LO 0xd480 +#define mmRLC_PERFCOUNTER1_LO 0xd482 +#define mmRLC_PERFCOUNTER0_HI 0xd481 +#define mmRLC_PERFCOUNTER1_HI 0xd483 +#define mmCGTT_RLC_CLK_CTRL 0xf0b8 +#define mmRLC_LB_CNTL 0x30d9 +#define mmRLC_LB_CNTR_MAX 0x30d2 +#define mmRLC_LB_CNTR_INIT 0x30db +#define mmRLC_LOAD_BALANCE_CNTR 0x30dc +#define mmRLC_SAVE_AND_RESTORE_BASE 0x30dd +#define mmRLC_JUMP_TABLE_RESTORE 0x30de +#define mmRLC_DRIVER_CPDMA_STATUS 0x30de +#define mmRLC_PG_DELAY_2 0x30df +#define mmRLC_GPM_DEBUG_SELECT 0x30e0 +#define mmRLC_GPM_DEBUG 0x30e1 +#define mmRLC_GPM_UCODE_ADDR 0x30e2 +#define mmRLC_GPM_UCODE_DATA 0x30e3 +#define mmRLC_GPU_CLOCK_COUNT_LSB 0x30e4 +#define mmRLC_GPU_CLOCK_COUNT_MSB 0x30e5 +#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30e6 +#define mmRLC_UCODE_CNTL 0x30e7 +#define mmRLC_GPM_STAT 0x3100 +#define mmRLC_GPU_CLOCK_32_RES_SEL 0x3101 +#define mmRLC_GPU_CLOCK_32 0x3102 +#define mmRLC_PG_CNTL 0x3103 +#define mmRLC_GPM_THREAD_PRIORITY 0x3104 +#define mmRLC_GPM_THREAD_ENABLE 0x3105 +#define mmRLC_GPM_VMID_THREAD0 0x3106 +#define mmRLC_GPM_VMID_THREAD1 0x3107 +#define mmRLC_CGTT_MGCG_OVERRIDE 0x3108 +#define mmRLC_CGCG_CGLS_CTRL 0x3109 +#define mmRLC_CGCG_RAMP_CTRL 0x310a +#define mmRLC_DYN_PG_STATUS 0x310b +#define mmRLC_DYN_PG_REQUEST 0x310c +#define mmRLC_PG_DELAY 0x310d +#define mmRLC_CU_STATUS 0x310e +#define mmRLC_LB_INIT_CU_MASK 0x310f +#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3110 +#define mmRLC_LB_PARAMS 0x3111 +#define mmRLC_THREAD1_DELAY 0x3112 +#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x3113 +#define mmRLC_MAX_PG_CU 0x3114 +#define mmRLC_AUTO_PG_CTRL 0x3115 +#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x3116 +#define mmRLC_SMU_PG_CTRL 0x3117 +#define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3118 +#define mmRLC_SERDES_RD_MASTER_INDEX 0x3119 +#define mmRLC_SERDES_RD_DATA_0 0x311a +#define mmRLC_SERDES_RD_DATA_1 0x311b +#define mmRLC_SERDES_RD_DATA_2 0x311c +#define mmRLC_SERDES_WR_CU_MASTER_MASK 0x311d +#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x311e +#define mmRLC_SERDES_WR_CTRL 0x311f +#define mmRLC_SERDES_WR_DATA 0x3120 +#define mmRLC_SERDES_CU_MASTER_BUSY 0x3121 +#define mmRLC_SERDES_NONCU_MASTER_BUSY 0x3122 +#define mmRLC_GPM_GENERAL_0 0x3123 +#define mmRLC_GPM_GENERAL_1 0x3124 +#define mmRLC_GPM_GENERAL_2 0x3125 +#define mmRLC_GPM_GENERAL_3 0x3126 +#define mmRLC_GPM_GENERAL_4 0x3127 +#define mmRLC_GPM_GENERAL_5 0x3128 +#define mmRLC_GPM_GENERAL_6 0x3129 +#define mmRLC_GPM_GENERAL_7 0x312a +#define mmRLC_GPM_CU_PD_TIMEOUT 0x312b +#define mmRLC_GPM_SCRATCH_ADDR 0x312c +#define mmRLC_GPM_SCRATCH_DATA 0x312d +#define mmRLC_STATIC_PG_STATUS 0x312e +#define mmRLC_GPM_PERF_COUNT_0 0x312f +#define mmRLC_GPM_PERF_COUNT_1 0x3130 +#define mmRLC_GPR_REG1 0x3139 +#define mmRLC_GPR_REG2 0x313a +#define mmRLC_SPM_VMID 0x3131 +#define mmRLC_SPM_INT_CNTL 0x3132 +#define mmRLC_SPM_INT_STATUS 0x3133 +#define mmRLC_SPM_DEBUG_SELECT 0x3134 +#define mmRLC_SPM_DEBUG 0x3135 +#define mmRLC_GPM_LOG_ADDR 0x3136 +#define mmRLC_GPM_LOG_SIZE 0x3137 +#define mmRLC_GPM_LOG_CONT 0x3138 +#define mmRLC_SPM_PERFMON_CNTL 0xdc80 +#define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81 +#define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82 +#define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83 +#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84 +#define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85 +#define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86 +#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87 +#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88 +#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89 +#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a +#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b +#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c +#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d +#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e +#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90 +#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91 +#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92 +#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93 +#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94 +#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95 +#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96 +#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97 +#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98 +#define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY 0xdc99 +#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a +#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b +#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c +#define mmRLC_SPM_RING_RDPTR 0xdc9d +#define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e +#define mmSPI_PS_INPUT_CNTL_0 0xa191 +#define mmSPI_PS_INPUT_CNTL_1 0xa192 +#define mmSPI_PS_INPUT_CNTL_2 0xa193 +#define mmSPI_PS_INPUT_CNTL_3 0xa194 +#define mmSPI_PS_INPUT_CNTL_4 0xa195 +#define mmSPI_PS_INPUT_CNTL_5 0xa196 +#define mmSPI_PS_INPUT_CNTL_6 0xa197 +#define mmSPI_PS_INPUT_CNTL_7 0xa198 +#define mmSPI_PS_INPUT_CNTL_8 0xa199 +#define mmSPI_PS_INPUT_CNTL_9 0xa19a +#define mmSPI_PS_INPUT_CNTL_10 0xa19b +#define mmSPI_PS_INPUT_CNTL_11 0xa19c +#define mmSPI_PS_INPUT_CNTL_12 0xa19d +#define mmSPI_PS_INPUT_CNTL_13 0xa19e +#define mmSPI_PS_INPUT_CNTL_14 0xa19f +#define mmSPI_PS_INPUT_CNTL_15 0xa1a0 +#define mmSPI_PS_INPUT_CNTL_16 0xa1a1 +#define mmSPI_PS_INPUT_CNTL_17 0xa1a2 +#define mmSPI_PS_INPUT_CNTL_18 0xa1a3 +#define mmSPI_PS_INPUT_CNTL_19 0xa1a4 +#define mmSPI_PS_INPUT_CNTL_20 0xa1a5 +#define mmSPI_PS_INPUT_CNTL_21 0xa1a6 +#define mmSPI_PS_INPUT_CNTL_22 0xa1a7 +#define mmSPI_PS_INPUT_CNTL_23 0xa1a8 +#define mmSPI_PS_INPUT_CNTL_24 0xa1a9 +#define mmSPI_PS_INPUT_CNTL_25 0xa1aa +#define mmSPI_PS_INPUT_CNTL_26 0xa1ab +#define mmSPI_PS_INPUT_CNTL_27 0xa1ac +#define mmSPI_PS_INPUT_CNTL_28 0xa1ad +#define mmSPI_PS_INPUT_CNTL_29 0xa1ae +#define mmSPI_PS_INPUT_CNTL_30 0xa1af +#define mmSPI_PS_INPUT_CNTL_31 0xa1b0 +#define mmSPI_VS_OUT_CONFIG 0xa1b1 +#define mmSPI_PS_INPUT_ENA 0xa1b3 +#define mmSPI_PS_INPUT_ADDR 0xa1b4 +#define mmSPI_INTERP_CONTROL_0 0xa1b5 +#define mmSPI_PS_IN_CONTROL 0xa1b6 +#define mmSPI_BARYC_CNTL 0xa1b8 +#define mmSPI_TMPRING_SIZE 0xa1ba +#define mmSPI_SHADER_POS_FORMAT 0xa1c3 +#define mmSPI_SHADER_Z_FORMAT 0xa1c4 +#define mmSPI_SHADER_COL_FORMAT 0xa1c5 +#define mmSPI_ARB_PRIORITY 0x31c0 +#define mmSPI_ARB_CYCLES_0 0x31c1 +#define mmSPI_ARB_CYCLES_1 0x31c2 +#define mmSPI_CDBG_SYS_GFX 0x31c3 +#define mmSPI_CDBG_SYS_HP3D 0x31c4 +#define mmSPI_CDBG_SYS_CS0 0x31c5 +#define mmSPI_CDBG_SYS_CS1 0x31c6 +#define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 +#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8 +#define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9 +#define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca +#define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb +#define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc +#define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd +#define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce +#define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf +#define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0 +#define mmSPI_GDBG_WAVE_CNTL 0x31d1 +#define mmSPI_GDBG_TRAP_CONFIG 0x31d2 +#define mmSPI_GDBG_TRAP_MASK 0x31d3 +#define mmSPI_GDBG_TBA_LO 0x31d4 +#define mmSPI_GDBG_TBA_HI 0x31d5 +#define mmSPI_GDBG_TMA_LO 0x31d6 +#define mmSPI_GDBG_TMA_HI 0x31d7 +#define mmSPI_GDBG_TRAP_DATA0 0x31d8 +#define mmSPI_GDBG_TRAP_DATA1 0x31d9 +#define mmSPI_RESET_DEBUG 0x31da +#define mmSPI_COMPUTE_QUEUE_RESET 0x31db +#define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc +#define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd +#define mmSPI_RESOURCE_RESERVE_CU_2 0x31de +#define mmSPI_RESOURCE_RESERVE_CU_3 0x31df +#define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0 +#define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1 +#define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2 +#define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3 +#define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4 +#define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5 +#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6 +#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7 +#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8 +#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9 +#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea +#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb +#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec +#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed +#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee +#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef +#define mmSPI_PS_MAX_WAVE_ID 0x243a +#define mmSPI_CONFIG_CNTL 0x2440 +#define mmSPI_DEBUG_CNTL 0x2441 +#define mmSPI_DEBUG_READ 0x2442 +#define mmSPI_PERFCOUNTER0_SELECT 0xd980 +#define mmSPI_PERFCOUNTER1_SELECT 0xd981 +#define mmSPI_PERFCOUNTER2_SELECT 0xd982 +#define mmSPI_PERFCOUNTER3_SELECT 0xd983 +#define mmSPI_PERFCOUNTER0_SELECT1 0xd984 +#define mmSPI_PERFCOUNTER1_SELECT1 0xd985 +#define mmSPI_PERFCOUNTER2_SELECT1 0xd986 +#define mmSPI_PERFCOUNTER3_SELECT1 0xd987 +#define mmSPI_PERFCOUNTER4_SELECT 0xd988 +#define mmSPI_PERFCOUNTER5_SELECT 0xd989 +#define mmSPI_PERFCOUNTER_BINS 0xd98a +#define mmSPI_PERFCOUNTER0_HI 0xd180 +#define mmSPI_PERFCOUNTER0_LO 0xd181 +#define mmSPI_PERFCOUNTER1_HI 0xd182 +#define mmSPI_PERFCOUNTER1_LO 0xd183 +#define mmSPI_PERFCOUNTER2_HI 0xd184 +#define mmSPI_PERFCOUNTER2_LO 0xd185 +#define mmSPI_PERFCOUNTER3_HI 0xd186 +#define mmSPI_PERFCOUNTER3_LO 0xd187 +#define mmSPI_PERFCOUNTER4_HI 0xd188 +#define mmSPI_PERFCOUNTER4_LO 0xd189 +#define mmSPI_PERFCOUNTER5_HI 0xd18a +#define mmSPI_PERFCOUNTER5_LO 0xd18b +#define mmSPI_CONFIG_CNTL_1 0x244f +#define mmSPI_DEBUG_BUSY 0x2450 +#define mmCGTS_SM_CTRL_REG 0xf000 +#define mmCGTS_RD_CTRL_REG 0xf001 +#define mmCGTS_RD_REG 0xf002 +#define mmCGTS_TCC_DISABLE 0xf003 +#define mmCGTS_USER_TCC_DISABLE 0xf004 +#define mmCGTS_CU0_SP0_CTRL_REG 0xf008 +#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009 +#define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a +#define mmCGTS_CU0_SP1_CTRL_REG 0xf00b +#define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c +#define mmCGTS_CU1_SP0_CTRL_REG 0xf00d +#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e +#define mmCGTS_CU1_TA_CTRL_REG 0xf00f +#define mmCGTS_CU1_SP1_CTRL_REG 0xf010 +#define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011 +#define mmCGTS_CU2_SP0_CTRL_REG 0xf012 +#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013 +#define mmCGTS_CU2_TA_CTRL_REG 0xf014 +#define mmCGTS_CU2_SP1_CTRL_REG 0xf015 +#define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016 +#define mmCGTS_CU3_SP0_CTRL_REG 0xf017 +#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018 +#define mmCGTS_CU3_TA_CTRL_REG 0xf019 +#define mmCGTS_CU3_SP1_CTRL_REG 0xf01a +#define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b +#define mmCGTS_CU4_SP0_CTRL_REG 0xf01c +#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d +#define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e +#define mmCGTS_CU4_SP1_CTRL_REG 0xf01f +#define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020 +#define mmCGTS_CU5_SP0_CTRL_REG 0xf021 +#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022 +#define mmCGTS_CU5_TA_CTRL_REG 0xf023 +#define mmCGTS_CU5_SP1_CTRL_REG 0xf024 +#define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025 +#define mmCGTS_CU6_SP0_CTRL_REG 0xf026 +#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027 +#define mmCGTS_CU6_TA_CTRL_REG 0xf028 +#define mmCGTS_CU6_SP1_CTRL_REG 0xf029 +#define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a +#define mmCGTS_CU7_SP0_CTRL_REG 0xf02b +#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c +#define mmCGTS_CU7_TA_CTRL_REG 0xf02d +#define mmCGTS_CU7_SP1_CTRL_REG 0xf02e +#define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f +#define mmCGTS_CU8_SP0_CTRL_REG 0xf030 +#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031 +#define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032 +#define mmCGTS_CU8_SP1_CTRL_REG 0xf033 +#define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034 +#define mmCGTS_CU9_SP0_CTRL_REG 0xf035 +#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036 +#define mmCGTS_CU9_TA_CTRL_REG 0xf037 +#define mmCGTS_CU9_SP1_CTRL_REG 0xf038 +#define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039 +#define mmCGTS_CU10_SP0_CTRL_REG 0xf03a +#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b +#define mmCGTS_CU10_TA_CTRL_REG 0xf03c +#define mmCGTS_CU10_SP1_CTRL_REG 0xf03d +#define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e +#define mmCGTS_CU11_SP0_CTRL_REG 0xf03f +#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040 +#define mmCGTS_CU11_TA_CTRL_REG 0xf041 +#define mmCGTS_CU11_SP1_CTRL_REG 0xf042 +#define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043 +#define mmCGTS_CU12_SP0_CTRL_REG 0xf044 +#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045 +#define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046 +#define mmCGTS_CU12_SP1_CTRL_REG 0xf047 +#define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048 +#define mmCGTS_CU13_SP0_CTRL_REG 0xf049 +#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a +#define mmCGTS_CU13_TA_CTRL_REG 0xf04b +#define mmCGTS_CU13_SP1_CTRL_REG 0xf04c +#define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d +#define mmCGTS_CU14_SP0_CTRL_REG 0xf04e +#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f +#define mmCGTS_CU14_TA_CTRL_REG 0xf050 +#define mmCGTS_CU14_SP1_CTRL_REG 0xf051 +#define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052 +#define mmCGTS_CU15_SP0_CTRL_REG 0xf053 +#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 +#define mmCGTS_CU15_TA_CTRL_REG 0xf055 +#define mmCGTS_CU15_SP1_CTRL_REG 0xf056 +#define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057 +#define mmCGTT_SPI_CLK_CTRL 0xf080 +#define mmCGTT_PC_CLK_CTRL 0xf081 +#define mmCGTT_BCI_CLK_CTRL 0xf082 +#define mmSPI_WF_LIFETIME_CNTL 0x24aa +#define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab +#define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac +#define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad +#define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae +#define mmSPI_WF_LIFETIME_LIMIT_4 0x24af +#define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0 +#define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1 +#define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2 +#define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3 +#define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4 +#define mmSPI_WF_LIFETIME_STATUS_0 0x24b5 +#define mmSPI_WF_LIFETIME_STATUS_1 0x24b6 +#define mmSPI_WF_LIFETIME_STATUS_2 0x24b7 +#define mmSPI_WF_LIFETIME_STATUS_3 0x24b8 +#define mmSPI_WF_LIFETIME_STATUS_4 0x24b9 +#define mmSPI_WF_LIFETIME_STATUS_5 0x24ba +#define mmSPI_WF_LIFETIME_STATUS_6 0x24bb +#define mmSPI_WF_LIFETIME_STATUS_7 0x24bc +#define mmSPI_WF_LIFETIME_STATUS_8 0x24bd +#define mmSPI_WF_LIFETIME_STATUS_9 0x24be +#define mmSPI_WF_LIFETIME_STATUS_10 0x24bf +#define mmSPI_WF_LIFETIME_STATUS_11 0x24c0 +#define mmSPI_WF_LIFETIME_STATUS_12 0x24c1 +#define mmSPI_WF_LIFETIME_STATUS_13 0x24c2 +#define mmSPI_WF_LIFETIME_STATUS_14 0x24c3 +#define mmSPI_WF_LIFETIME_STATUS_15 0x24c4 +#define mmSPI_WF_LIFETIME_STATUS_16 0x24c5 +#define mmSPI_WF_LIFETIME_STATUS_17 0x24c6 +#define mmSPI_WF_LIFETIME_STATUS_18 0x24c7 +#define mmSPI_WF_LIFETIME_STATUS_19 0x24c8 +#define mmSPI_WF_LIFETIME_STATUS_20 0x24c9 +#define mmSPI_WF_LIFETIME_DEBUG 0x24ca +#define mmSPI_SLAVE_DEBUG_BUSY 0x24d3 +#define mmSPI_LB_CTR_CTRL 0x24d4 +#define mmSPI_LB_CU_MASK 0x24d5 +#define mmSPI_LB_DATA_REG 0x24d6 +#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7 +#define mmSPI_GDS_CREDITS 0x24d8 +#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9 +#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da +#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db +#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc +#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd +#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de +#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df +#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3 +#define mmBCI_DEBUG_READ 0x24eb +#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec +#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed +#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee +#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef +#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0 +#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1 +#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2 +#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3 +#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4 +#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5 +#define mmSPI_SHADER_TBA_LO_PS 0x2c00 +#define mmSPI_SHADER_TBA_HI_PS 0x2c01 +#define mmSPI_SHADER_TMA_LO_PS 0x2c02 +#define mmSPI_SHADER_TMA_HI_PS 0x2c03 +#define mmSPI_SHADER_PGM_LO_PS 0x2c08 +#define mmSPI_SHADER_PGM_HI_PS 0x2c09 +#define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a +#define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b +#define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07 +#define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c +#define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d +#define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e +#define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f +#define mmSPI_SHADER_USER_DATA_PS_4 0x2c10 +#define mmSPI_SHADER_USER_DATA_PS_5 0x2c11 +#define mmSPI_SHADER_USER_DATA_PS_6 0x2c12 +#define mmSPI_SHADER_USER_DATA_PS_7 0x2c13 +#define mmSPI_SHADER_USER_DATA_PS_8 0x2c14 +#define mmSPI_SHADER_USER_DATA_PS_9 0x2c15 +#define mmSPI_SHADER_USER_DATA_PS_10 0x2c16 +#define mmSPI_SHADER_USER_DATA_PS_11 0x2c17 +#define mmSPI_SHADER_USER_DATA_PS_12 0x2c18 +#define mmSPI_SHADER_USER_DATA_PS_13 0x2c19 +#define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a +#define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b +#define mmSPI_SHADER_TBA_LO_VS 0x2c40 +#define mmSPI_SHADER_TBA_HI_VS 0x2c41 +#define mmSPI_SHADER_TMA_LO_VS 0x2c42 +#define mmSPI_SHADER_TMA_HI_VS 0x2c43 +#define mmSPI_SHADER_PGM_LO_VS 0x2c48 +#define mmSPI_SHADER_PGM_HI_VS 0x2c49 +#define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a +#define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b +#define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46 +#define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47 +#define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c +#define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d +#define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e +#define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f +#define mmSPI_SHADER_USER_DATA_VS_4 0x2c50 +#define mmSPI_SHADER_USER_DATA_VS_5 0x2c51 +#define mmSPI_SHADER_USER_DATA_VS_6 0x2c52 +#define mmSPI_SHADER_USER_DATA_VS_7 0x2c53 +#define mmSPI_SHADER_USER_DATA_VS_8 0x2c54 +#define mmSPI_SHADER_USER_DATA_VS_9 0x2c55 +#define mmSPI_SHADER_USER_DATA_VS_10 0x2c56 +#define mmSPI_SHADER_USER_DATA_VS_11 0x2c57 +#define mmSPI_SHADER_USER_DATA_VS_12 0x2c58 +#define mmSPI_SHADER_USER_DATA_VS_13 0x2c59 +#define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a +#define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b +#define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c +#define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d +#define mmSPI_SHADER_TBA_LO_GS 0x2c80 +#define mmSPI_SHADER_TBA_HI_GS 0x2c81 +#define mmSPI_SHADER_TMA_LO_GS 0x2c82 +#define mmSPI_SHADER_TMA_HI_GS 0x2c83 +#define mmSPI_SHADER_PGM_LO_GS 0x2c88 +#define mmSPI_SHADER_PGM_HI_GS 0x2c89 +#define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a +#define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b +#define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87 +#define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c +#define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d +#define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e +#define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f +#define mmSPI_SHADER_USER_DATA_GS_4 0x2c90 +#define mmSPI_SHADER_USER_DATA_GS_5 0x2c91 +#define mmSPI_SHADER_USER_DATA_GS_6 0x2c92 +#define mmSPI_SHADER_USER_DATA_GS_7 0x2c93 +#define mmSPI_SHADER_USER_DATA_GS_8 0x2c94 +#define mmSPI_SHADER_USER_DATA_GS_9 0x2c95 +#define mmSPI_SHADER_USER_DATA_GS_10 0x2c96 +#define mmSPI_SHADER_USER_DATA_GS_11 0x2c97 +#define mmSPI_SHADER_USER_DATA_GS_12 0x2c98 +#define mmSPI_SHADER_USER_DATA_GS_13 0x2c99 +#define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a +#define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b +#define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc +#define mmSPI_SHADER_TBA_LO_ES 0x2cc0 +#define mmSPI_SHADER_TBA_HI_ES 0x2cc1 +#define mmSPI_SHADER_TMA_LO_ES 0x2cc2 +#define mmSPI_SHADER_TMA_HI_ES 0x2cc3 +#define mmSPI_SHADER_PGM_LO_ES 0x2cc8 +#define mmSPI_SHADER_PGM_HI_ES 0x2cc9 +#define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca +#define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb +#define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7 +#define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc +#define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd +#define mmSPI_SHADER_USER_DATA_ES_2 0x2cce +#define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf +#define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0 +#define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1 +#define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2 +#define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3 +#define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4 +#define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5 +#define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6 +#define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7 +#define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8 +#define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9 +#define mmSPI_SHADER_USER_DATA_ES_14 0x2cda +#define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb +#define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd +#define mmSPI_SHADER_TBA_LO_HS 0x2d00 +#define mmSPI_SHADER_TBA_HI_HS 0x2d01 +#define mmSPI_SHADER_TMA_LO_HS 0x2d02 +#define mmSPI_SHADER_TMA_HI_HS 0x2d03 +#define mmSPI_SHADER_PGM_LO_HS 0x2d08 +#define mmSPI_SHADER_PGM_HI_HS 0x2d09 +#define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a +#define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b +#define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07 +#define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c +#define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d +#define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e +#define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f +#define mmSPI_SHADER_USER_DATA_HS_4 0x2d10 +#define mmSPI_SHADER_USER_DATA_HS_5 0x2d11 +#define mmSPI_SHADER_USER_DATA_HS_6 0x2d12 +#define mmSPI_SHADER_USER_DATA_HS_7 0x2d13 +#define mmSPI_SHADER_USER_DATA_HS_8 0x2d14 +#define mmSPI_SHADER_USER_DATA_HS_9 0x2d15 +#define mmSPI_SHADER_USER_DATA_HS_10 0x2d16 +#define mmSPI_SHADER_USER_DATA_HS_11 0x2d17 +#define mmSPI_SHADER_USER_DATA_HS_12 0x2d18 +#define mmSPI_SHADER_USER_DATA_HS_13 0x2d19 +#define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a +#define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b +#define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d +#define mmSPI_SHADER_TBA_LO_LS 0x2d40 +#define mmSPI_SHADER_TBA_HI_LS 0x2d41 +#define mmSPI_SHADER_TMA_LO_LS 0x2d42 +#define mmSPI_SHADER_TMA_HI_LS 0x2d43 +#define mmSPI_SHADER_PGM_LO_LS 0x2d48 +#define mmSPI_SHADER_PGM_HI_LS 0x2d49 +#define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a +#define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b +#define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47 +#define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c +#define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d +#define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e +#define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f +#define mmSPI_SHADER_USER_DATA_LS_4 0x2d50 +#define mmSPI_SHADER_USER_DATA_LS_5 0x2d51 +#define mmSPI_SHADER_USER_DATA_LS_6 0x2d52 +#define mmSPI_SHADER_USER_DATA_LS_7 0x2d53 +#define mmSPI_SHADER_USER_DATA_LS_8 0x2d54 +#define mmSPI_SHADER_USER_DATA_LS_9 0x2d55 +#define mmSPI_SHADER_USER_DATA_LS_10 0x2d56 +#define mmSPI_SHADER_USER_DATA_LS_11 0x2d57 +#define mmSPI_SHADER_USER_DATA_LS_12 0x2d58 +#define mmSPI_SHADER_USER_DATA_LS_13 0x2d59 +#define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a +#define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b +#define mmSQ_CONFIG 0x2300 +#define mmSQC_CONFIG 0x2301 +#define mmSQC_CACHES 0xc348 +#define mmSQ_RANDOM_WAVE_PRI 0x2303 +#define mmSQ_REG_CREDITS 0x2304 +#define mmSQ_FIFO_SIZES 0x2305 +#define mmSQ_INTERRUPT_AUTO_MASK 0x2314 +#define mmSQ_INTERRUPT_MSG_CTRL 0x2315 +#define mmSQ_PERFCOUNTER_CTRL 0xd9e0 +#define mmSQ_PERFCOUNTER_MASK 0xd9e1 +#define mmSQ_PERFCOUNTER_CTRL2 0xd9e2 +#define mmCC_SQC_BANK_DISABLE 0x2307 +#define mmUSER_SQC_BANK_DISABLE 0x2308 +#define mmSQ_PERFCOUNTER0_LO 0xd1c0 +#define mmSQ_PERFCOUNTER1_LO 0xd1c2 +#define mmSQ_PERFCOUNTER2_LO 0xd1c4 +#define mmSQ_PERFCOUNTER3_LO 0xd1c6 +#define mmSQ_PERFCOUNTER4_LO 0xd1c8 +#define mmSQ_PERFCOUNTER5_LO 0xd1ca +#define mmSQ_PERFCOUNTER6_LO 0xd1cc +#define mmSQ_PERFCOUNTER7_LO 0xd1ce +#define mmSQ_PERFCOUNTER8_LO 0xd1d0 +#define mmSQ_PERFCOUNTER9_LO 0xd1d2 +#define mmSQ_PERFCOUNTER10_LO 0xd1d4 +#define mmSQ_PERFCOUNTER11_LO 0xd1d6 +#define mmSQ_PERFCOUNTER12_LO 0xd1d8 +#define mmSQ_PERFCOUNTER13_LO 0xd1da +#define mmSQ_PERFCOUNTER14_LO 0xd1dc +#define mmSQ_PERFCOUNTER15_LO 0xd1de +#define mmSQ_PERFCOUNTER0_HI 0xd1c1 +#define mmSQ_PERFCOUNTER1_HI 0xd1c3 +#define mmSQ_PERFCOUNTER2_HI 0xd1c5 +#define mmSQ_PERFCOUNTER3_HI 0xd1c7 +#define mmSQ_PERFCOUNTER4_HI 0xd1c9 +#define mmSQ_PERFCOUNTER5_HI 0xd1cb +#define mmSQ_PERFCOUNTER6_HI 0xd1cd +#define mmSQ_PERFCOUNTER7_HI 0xd1cf +#define mmSQ_PERFCOUNTER8_HI 0xd1d1 +#define mmSQ_PERFCOUNTER9_HI 0xd1d3 +#define mmSQ_PERFCOUNTER10_HI 0xd1d5 +#define mmSQ_PERFCOUNTER11_HI 0xd1d7 +#define mmSQ_PERFCOUNTER12_HI 0xd1d9 +#define mmSQ_PERFCOUNTER13_HI 0xd1db +#define mmSQ_PERFCOUNTER14_HI 0xd1dd +#define mmSQ_PERFCOUNTER15_HI 0xd1df +#define mmSQ_PERFCOUNTER0_SELECT 0xd9c0 +#define mmSQ_PERFCOUNTER1_SELECT 0xd9c1 +#define mmSQ_PERFCOUNTER2_SELECT 0xd9c2 +#define mmSQ_PERFCOUNTER3_SELECT 0xd9c3 +#define mmSQ_PERFCOUNTER4_SELECT 0xd9c4 +#define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 +#define mmSQ_PERFCOUNTER6_SELECT 0xd9c6 +#define mmSQ_PERFCOUNTER7_SELECT 0xd9c7 +#define mmSQ_PERFCOUNTER8_SELECT 0xd9c8 +#define mmSQ_PERFCOUNTER9_SELECT 0xd9c9 +#define mmSQ_PERFCOUNTER10_SELECT 0xd9ca +#define mmSQ_PERFCOUNTER11_SELECT 0xd9cb +#define mmSQ_PERFCOUNTER12_SELECT 0xd9cc +#define mmSQ_PERFCOUNTER13_SELECT 0xd9cd +#define mmSQ_PERFCOUNTER14_SELECT 0xd9ce +#define mmSQ_PERFCOUNTER15_SELECT 0xd9cf +#define mmCGTT_SQ_CLK_CTRL 0xf08c +#define mmCGTT_SQG_CLK_CTRL 0xf08d +#define mmSQ_ALU_CLK_CTRL 0xf08e +#define mmSQ_TEX_CLK_CTRL 0xf08f +#define mmSQ_LDS_CLK_CTRL 0xf090 +#define mmSQ_POWER_THROTTLE 0xf091 +#define mmSQ_POWER_THROTTLE2 0xf092 +#define mmSQ_TIME_HI 0x237c +#define mmSQ_TIME_LO 0x237d +#define mmSQ_THREAD_TRACE_BASE 0x2380 +#define mmSQ_THREAD_TRACE_BASE2 0x2385 +#define mmSQ_THREAD_TRACE_SIZE 0x2381 +#define mmSQ_THREAD_TRACE_MASK 0x2382 +#define mmSQ_THREAD_TRACE_USERDATA_0 0xc340 +#define mmSQ_THREAD_TRACE_USERDATA_1 0xc341 +#define mmSQ_THREAD_TRACE_USERDATA_2 0xc342 +#define mmSQ_THREAD_TRACE_USERDATA_3 0xc343 +#define mmSQ_THREAD_TRACE_MODE 0x238e +#define mmSQ_THREAD_TRACE_CTRL 0x238f +#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383 +#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2386 +#define mmSQ_THREAD_TRACE_PERF_MASK 0x2384 +#define mmSQ_THREAD_TRACE_WPTR 0x238c +#define mmSQ_THREAD_TRACE_STATUS 0x238d +#define mmSQ_THREAD_TRACE_CNTR 0x2390 +#define mmSQ_THREAD_TRACE_HIWATER 0x2392 +#define mmSQ_LB_CTR_CTRL 0x2398 +#define mmSQ_LB_DATA_ALU_CYCLES 0x2399 +#define mmSQ_LB_DATA_TEX_CYCLES 0x239a +#define mmSQ_LB_DATA_ALU_STALLS 0x239b +#define mmSQ_LB_DATA_TEX_STALLS 0x239c +#define mmSQC_SECDED_CNT 0x23a0 +#define mmSQ_SEC_CNT 0x23a1 +#define mmSQ_DED_CNT 0x23a2 +#define mmSQ_DED_INFO 0x23a3 +#define mmSQ_BUF_RSRC_WORD0 0x23c0 +#define mmSQ_BUF_RSRC_WORD1 0x23c1 +#define mmSQ_BUF_RSRC_WORD2 0x23c2 +#define mmSQ_BUF_RSRC_WORD3 0x23c3 +#define mmSQ_IMG_RSRC_WORD0 0x23c4 +#define mmSQ_IMG_RSRC_WORD1 0x23c5 +#define mmSQ_IMG_RSRC_WORD2 0x23c6 +#define mmSQ_IMG_RSRC_WORD3 0x23c7 +#define mmSQ_IMG_RSRC_WORD4 0x23c8 +#define mmSQ_IMG_RSRC_WORD5 0x23c9 +#define mmSQ_IMG_RSRC_WORD6 0x23ca +#define mmSQ_IMG_RSRC_WORD7 0x23cb +#define mmSQ_IMG_SAMP_WORD0 0x23cc +#define mmSQ_IMG_SAMP_WORD1 0x23cd +#define mmSQ_IMG_SAMP_WORD2 0x23ce +#define mmSQ_IMG_SAMP_WORD3 0x23cf +#define mmSQ_FLAT_SCRATCH_WORD0 0x23d0 +#define mmSQ_FLAT_SCRATCH_WORD1 0x23d1 +#define mmSQ_IND_INDEX 0x2378 +#define mmSQ_IND_CMD 0x237a +#define mmSQ_CMD 0x237b +#define mmSQ_IND_DATA 0x2379 +#define mmSQ_REG_TIMESTAMP 0x2374 +#define mmSQ_CMD_TIMESTAMP 0x2375 +#define mmSQ_HV_VMID_CTRL 0xf840 +#define ixSQ_WAVE_INST_DW0 0x1a +#define ixSQ_WAVE_INST_DW1 0x1b +#define ixSQ_WAVE_PC_LO 0x18 +#define ixSQ_WAVE_PC_HI 0x19 +#define ixSQ_WAVE_IB_DBG0 0x1c +#define ixSQ_WAVE_EXEC_LO 0x27e +#define ixSQ_WAVE_EXEC_HI 0x27f +#define ixSQ_WAVE_STATUS 0x12 +#define ixSQ_WAVE_MODE 0x11 +#define ixSQ_WAVE_TRAPSTS 0x13 +#define ixSQ_WAVE_HW_ID 0x14 +#define ixSQ_WAVE_GPR_ALLOC 0x15 +#define ixSQ_WAVE_LDS_ALLOC 0x16 +#define ixSQ_WAVE_IB_STS 0x17 +#define ixSQ_WAVE_M0 0x27c +#define ixSQ_WAVE_TBA_LO 0x26c +#define ixSQ_WAVE_TBA_HI 0x26d +#define ixSQ_WAVE_TMA_LO 0x26e +#define ixSQ_WAVE_TMA_HI 0x26f +#define ixSQ_WAVE_TTMP0 0x270 +#define ixSQ_WAVE_TTMP1 0x271 +#define ixSQ_WAVE_TTMP2 0x272 +#define ixSQ_WAVE_TTMP3 0x273 +#define ixSQ_WAVE_TTMP4 0x274 +#define ixSQ_WAVE_TTMP5 0x275 +#define ixSQ_WAVE_TTMP6 0x276 +#define ixSQ_WAVE_TTMP7 0x277 +#define ixSQ_WAVE_TTMP8 0x278 +#define ixSQ_WAVE_TTMP9 0x279 +#define ixSQ_WAVE_TTMP10 0x27a +#define ixSQ_WAVE_TTMP11 0x27b +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 +#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 +#define mmSQ_DEBUG_STS_GLOBAL3 0x2311 +#define ixSQ_DEBUG_STS_LOCAL 0x8 +#define ixSQ_DEBUG_CTRL_LOCAL 0x9 +#define mmSH_MEM_BASES 0x230a +#define mmSH_MEM_APE1_BASE 0x230b +#define mmSH_MEM_APE1_LIMIT 0x230c +#define mmSH_MEM_CONFIG 0x230d +#define mmSQC_POLICY 0x230e +#define mmSQC_VOLATILE 0x230f +#define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1 +#define ixSQ_INTERRUPT_WORD_CMN 0x20c0 +#define ixSQ_INTERRUPT_WORD_AUTO 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE 0x20c0 +#define mmSQ_SOP2 0x237f +#define mmSQ_VOP1 0x237f +#define mmSQ_MTBUF_1 0x237f +#define mmSQ_EXP_1 0x237f +#define mmSQ_MUBUF_1 0x237f +#define mmSQ_INST 0x237f +#define mmSQ_EXP_0 0x237f +#define mmSQ_MUBUF_0 0x237f +#define mmSQ_VOP3_0 0x237f +#define mmSQ_VOP2 0x237f +#define mmSQ_MTBUF_0 0x237f +#define mmSQ_SOPP 0x237f +#define mmSQ_FLAT_0 0x237f +#define mmSQ_VOP3_0_SDST_ENC 0x237f +#define mmSQ_MIMG_1 0x237f +#define mmSQ_SMRD 0x237f +#define mmSQ_SOP1 0x237f +#define mmSQ_SOPC 0x237f +#define mmSQ_FLAT_1 0x237f +#define mmSQ_DS_1 0x237f +#define mmSQ_VOP3_1 0x237f +#define mmSQ_MIMG_0 0x237f +#define mmSQ_SOPK 0x237f +#define mmSQ_DS_0 0x237f +#define mmSQ_VOPC 0x237f +#define mmSQ_VINTRP 0x237f +#define mmCGTT_SX_CLK_CTRL0 0xf094 +#define mmCGTT_SX_CLK_CTRL1 0xf095 +#define mmCGTT_SX_CLK_CTRL2 0xf096 +#define mmCGTT_SX_CLK_CTRL3 0xf097 +#define mmCGTT_SX_CLK_CTRL4 0xf098 +#define mmSX_DEBUG_BUSY 0x2414 +#define mmSX_DEBUG_BUSY_2 0x2415 +#define mmSX_DEBUG_BUSY_3 0x2416 +#define mmSX_DEBUG_BUSY_4 0x2417 +#define mmSX_DEBUG_1 0x2418 +#define mmSX_PERFCOUNTER0_SELECT 0xda40 +#define mmSX_PERFCOUNTER1_SELECT 0xda41 +#define mmSX_PERFCOUNTER2_SELECT 0xda42 +#define mmSX_PERFCOUNTER3_SELECT 0xda43 +#define mmSX_PERFCOUNTER0_SELECT1 0xda44 +#define mmSX_PERFCOUNTER1_SELECT1 0xda45 +#define mmSX_PERFCOUNTER0_LO 0xd240 +#define mmSX_PERFCOUNTER0_HI 0xd241 +#define mmSX_PERFCOUNTER1_LO 0xd242 +#define mmSX_PERFCOUNTER1_HI 0xd243 +#define mmSX_PERFCOUNTER2_LO 0xd244 +#define mmSX_PERFCOUNTER2_HI 0xd245 +#define mmSX_PERFCOUNTER3_LO 0xd246 +#define mmSX_PERFCOUNTER3_HI 0xd247 +#define mmTCC_CTRL 0x2b80 +#define mmTCC_EDC_COUNTER 0x2b82 +#define mmTCC_REDUNDANCY 0x2b83 +#define mmTCC_CGTT_SCLK_CTRL 0xf0ac +#define mmTCA_CGTT_SCLK_CTRL 0xf0ad +#define mmTCS_CGTT_SCLK_CTRL 0xf0ae +#define mmTCC_PERFCOUNTER0_SELECT 0xdb80 +#define mmTCC_PERFCOUNTER1_SELECT 0xdb82 +#define mmTCC_PERFCOUNTER0_SELECT1 0xdb81 +#define mmTCC_PERFCOUNTER1_SELECT1 0xdb83 +#define mmTCC_PERFCOUNTER2_SELECT 0xdb84 +#define mmTCC_PERFCOUNTER3_SELECT 0xdb85 +#define mmTCC_PERFCOUNTER0_LO 0xd380 +#define mmTCC_PERFCOUNTER1_LO 0xd382 +#define mmTCC_PERFCOUNTER2_LO 0xd384 +#define mmTCC_PERFCOUNTER3_LO 0xd386 +#define mmTCC_PERFCOUNTER0_HI 0xd381 +#define mmTCC_PERFCOUNTER1_HI 0xd383 +#define mmTCC_PERFCOUNTER2_HI 0xd385 +#define mmTCC_PERFCOUNTER3_HI 0xd387 +#define mmTCA_CTRL 0x2bc0 +#define mmTCA_PERFCOUNTER0_SELECT 0xdb90 +#define mmTCA_PERFCOUNTER1_SELECT 0xdb92 +#define mmTCA_PERFCOUNTER0_SELECT1 0xdb91 +#define mmTCA_PERFCOUNTER1_SELECT1 0xdb93 +#define mmTCA_PERFCOUNTER2_SELECT 0xdb94 +#define mmTCA_PERFCOUNTER3_SELECT 0xdb95 +#define mmTCA_PERFCOUNTER0_LO 0xd390 +#define mmTCA_PERFCOUNTER1_LO 0xd392 +#define mmTCA_PERFCOUNTER2_LO 0xd394 +#define mmTCA_PERFCOUNTER3_LO 0xd396 +#define mmTCA_PERFCOUNTER0_HI 0xd391 +#define mmTCA_PERFCOUNTER1_HI 0xd393 +#define mmTCA_PERFCOUNTER2_HI 0xd395 +#define mmTCA_PERFCOUNTER3_HI 0xd397 +#define mmTCS_CTRL 0x2be0 +#define mmTCS_PERFCOUNTER0_SELECT 0xdba0 +#define mmTCS_PERFCOUNTER0_SELECT1 0xdba1 +#define mmTCS_PERFCOUNTER1_SELECT 0xdba2 +#define mmTCS_PERFCOUNTER2_SELECT 0xdba3 +#define mmTCS_PERFCOUNTER3_SELECT 0xdba4 +#define mmTCS_PERFCOUNTER0_LO 0xd3a0 +#define mmTCS_PERFCOUNTER1_LO 0xd3a2 +#define mmTCS_PERFCOUNTER2_LO 0xd3a4 +#define mmTCS_PERFCOUNTER3_LO 0xd3a6 +#define mmTCS_PERFCOUNTER0_HI 0xd3a1 +#define mmTCS_PERFCOUNTER1_HI 0xd3a3 +#define mmTCS_PERFCOUNTER2_HI 0xd3a5 +#define mmTCS_PERFCOUNTER3_HI 0xd3a7 +#define mmTA_BC_BASE_ADDR 0xa020 +#define mmTA_BC_BASE_ADDR_HI 0xa021 +#define mmTD_CNTL 0x2525 +#define mmTD_STATUS 0x2526 +#define mmTD_DEBUG_INDEX 0x2528 +#define mmTD_DEBUG_DATA 0x2529 +#define mmTD_PERFCOUNTER0_SELECT 0xdb00 +#define mmTD_PERFCOUNTER1_SELECT 0xdb02 +#define mmTD_PERFCOUNTER0_SELECT1 0xdb01 +#define mmTD_PERFCOUNTER0_LO 0xd300 +#define mmTD_PERFCOUNTER1_LO 0xd302 +#define mmTD_PERFCOUNTER0_HI 0xd301 +#define mmTD_PERFCOUNTER1_HI 0xd303 +#define mmTD_SCRATCH 0x2533 +#define mmTA_CNTL 0x2541 +#define mmTA_CNTL_AUX 0x2542 +#define mmTA_RESERVED_010C 0x2543 +#define mmTA_CS_BC_BASE_ADDR 0xc380 +#define mmTA_CS_BC_BASE_ADDR_HI 0xc381 +#define mmTA_STATUS 0x2548 +#define mmTA_DEBUG_INDEX 0x254c +#define mmTA_DEBUG_DATA 0x254d +#define mmTA_PERFCOUNTER0_SELECT 0xdac0 +#define mmTA_PERFCOUNTER1_SELECT 0xdac2 +#define mmTA_PERFCOUNTER0_SELECT1 0xdac1 +#define mmTA_PERFCOUNTER0_LO 0xd2c0 +#define mmTA_PERFCOUNTER1_LO 0xd2c2 +#define mmTA_PERFCOUNTER0_HI 0xd2c1 +#define mmTA_PERFCOUNTER1_HI 0xd2c3 +#define mmTA_SCRATCH 0x2564 +#define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580 +#define mmSH_STATIC_MEM_CONFIG 0x2581 +#define mmTCP_INVALIDATE 0x2b00 +#define mmTCP_STATUS 0x2b01 +#define mmTCP_CNTL 0x2b02 +#define mmTCP_CHAN_STEER_LO 0x2b03 +#define mmTCP_CHAN_STEER_HI 0x2b04 +#define mmTCP_ADDR_CONFIG 0x2b05 +#define mmTCP_CREDIT 0x2b06 +#define mmTCP_PERFCOUNTER0_SELECT 0xdb40 +#define mmTCP_PERFCOUNTER1_SELECT 0xdb42 +#define mmTCP_PERFCOUNTER0_SELECT1 0xdb41 +#define mmTCP_PERFCOUNTER1_SELECT1 0xdb43 +#define mmTCP_PERFCOUNTER2_SELECT 0xdb44 +#define mmTCP_PERFCOUNTER3_SELECT 0xdb45 +#define mmTCP_PERFCOUNTER0_LO 0xd340 +#define mmTCP_PERFCOUNTER1_LO 0xd342 +#define mmTCP_PERFCOUNTER2_LO 0xd344 +#define mmTCP_PERFCOUNTER3_LO 0xd346 +#define mmTCP_PERFCOUNTER0_HI 0xd341 +#define mmTCP_PERFCOUNTER1_HI 0xd343 +#define mmTCP_PERFCOUNTER2_HI 0xd345 +#define mmTCP_PERFCOUNTER3_HI 0xd347 +#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16 +#define mmTCP_EDC_COUNTER 0x2b17 +#define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a +#define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b +#define mmTC_CFG_L1_STORE_POLICY 0x2b1c +#define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d +#define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e +#define mmTC_CFG_L2_STORE_POLICY0 0x2b1f +#define mmTC_CFG_L2_STORE_POLICY1 0x2b20 +#define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21 +#define mmTC_CFG_L1_VOLATILE 0x2b22 +#define mmTC_CFG_L2_VOLATILE 0x2b23 +#define mmTCP_WATCH0_ADDR_H 0x32a0 +#define mmTCP_WATCH1_ADDR_H 0x32a3 +#define mmTCP_WATCH2_ADDR_H 0x32a6 +#define mmTCP_WATCH3_ADDR_H 0x32a9 +#define mmTCP_WATCH0_ADDR_L 0x32a1 +#define mmTCP_WATCH1_ADDR_L 0x32a4 +#define mmTCP_WATCH2_ADDR_L 0x32a7 +#define mmTCP_WATCH3_ADDR_L 0x32aa +#define mmTCP_WATCH0_CNTL 0x32a2 +#define mmTCP_WATCH1_CNTL 0x32a5 +#define mmTCP_WATCH2_CNTL 0x32a8 +#define mmTCP_WATCH3_CNTL 0x32ab +#define mmTD_CGTT_CTRL 0xf09c +#define mmTA_CGTT_CTRL 0xf09d +#define mmCGTT_TCP_CLK_CTRL 0xf09e +#define mmCGTT_TCI_CLK_CTRL 0xf09f +#define mmTCI_STATUS 0x2b61 +#define mmTCI_CNTL_1 0x2b62 +#define mmTCI_CNTL_2 0x2b63 +#define mmGDS_CONFIG 0x25c0 +#define mmGDS_CNTL_STATUS 0x25c1 +#define mmGDS_ENHANCE 0x25c2 +#define mmGDS_PROTECTION_FAULT 0x25c3 +#define mmGDS_VM_PROTECTION_FAULT 0x25c4 +#define mmGDS_SECDED_CNT 0x25c5 +#define mmGDS_GRBM_SECDED_CNT 0x25c6 +#define mmGDS_OA_DED 0x25c7 +#define mmGDS_DEBUG_CNTL 0x25c8 +#define mmGDS_DEBUG_DATA 0x25c9 +#define mmCGTT_GDS_CLK_CTRL 0xf0a0 +#define mmGDS_RD_ADDR 0xc400 +#define mmGDS_RD_DATA 0xc401 +#define mmGDS_RD_BURST_ADDR 0xc402 +#define mmGDS_RD_BURST_COUNT 0xc403 +#define mmGDS_RD_BURST_DATA 0xc404 +#define mmGDS_WR_ADDR 0xc405 +#define mmGDS_WR_DATA 0xc406 +#define mmGDS_WR_BURST_ADDR 0xc407 +#define mmGDS_WR_BURST_DATA 0xc408 +#define mmGDS_WRITE_COMPLETE 0xc409 +#define mmGDS_ATOM_CNTL 0xc40a +#define mmGDS_ATOM_COMPLETE 0xc40b +#define mmGDS_ATOM_BASE 0xc40c +#define mmGDS_ATOM_SIZE 0xc40d +#define mmGDS_ATOM_OFFSET0 0xc40e +#define mmGDS_ATOM_OFFSET1 0xc40f +#define mmGDS_ATOM_DST 0xc410 +#define mmGDS_ATOM_OP 0xc411 +#define mmGDS_ATOM_SRC0 0xc412 +#define mmGDS_ATOM_SRC0_U 0xc413 +#define mmGDS_ATOM_SRC1 0xc414 +#define mmGDS_ATOM_SRC1_U 0xc415 +#define mmGDS_ATOM_READ0 0xc416 +#define mmGDS_ATOM_READ0_U 0xc417 +#define mmGDS_ATOM_READ1 0xc418 +#define mmGDS_ATOM_READ1_U 0xc419 +#define mmGDS_GWS_RESOURCE_CNTL 0xc41a +#define mmGDS_GWS_RESOURCE 0xc41b +#define mmGDS_GWS_RESOURCE_CNT 0xc41c +#define mmGDS_OA_CNTL 0xc41d +#define mmGDS_OA_COUNTER 0xc41e +#define mmGDS_OA_ADDRESS 0xc41f +#define mmGDS_OA_INCDEC 0xc420 +#define ixGDS_DEBUG_REG0 0x0 +#define ixGDS_DEBUG_REG1 0x1 +#define ixGDS_DEBUG_REG2 0x2 +#define ixGDS_DEBUG_REG3 0x3 +#define ixGDS_DEBUG_REG4 0x4 +#define ixGDS_DEBUG_REG5 0x5 +#define ixGDS_DEBUG_REG6 0x6 +#define mmGDS_PERFCOUNTER0_SELECT 0xda80 +#define mmGDS_PERFCOUNTER1_SELECT 0xda81 +#define mmGDS_PERFCOUNTER2_SELECT 0xda82 +#define mmGDS_PERFCOUNTER3_SELECT 0xda83 +#define mmGDS_PERFCOUNTER0_LO 0xd280 +#define mmGDS_PERFCOUNTER1_LO 0xd282 +#define mmGDS_PERFCOUNTER2_LO 0xd284 +#define mmGDS_PERFCOUNTER3_LO 0xd286 +#define mmGDS_PERFCOUNTER0_HI 0xd281 +#define mmGDS_PERFCOUNTER1_HI 0xd283 +#define mmGDS_PERFCOUNTER2_HI 0xd285 +#define mmGDS_PERFCOUNTER3_HI 0xd287 +#define mmGDS_PERFCOUNTER0_SELECT1 0xda84 +#define mmGDS_VMID0_BASE 0x3300 +#define mmGDS_VMID1_BASE 0x3302 +#define mmGDS_VMID2_BASE 0x3304 +#define mmGDS_VMID3_BASE 0x3306 +#define mmGDS_VMID4_BASE 0x3308 +#define mmGDS_VMID5_BASE 0x330a +#define mmGDS_VMID6_BASE 0x330c +#define mmGDS_VMID7_BASE 0x330e +#define mmGDS_VMID8_BASE 0x3310 +#define mmGDS_VMID9_BASE 0x3312 +#define mmGDS_VMID10_BASE 0x3314 +#define mmGDS_VMID11_BASE 0x3316 +#define mmGDS_VMID12_BASE 0x3318 +#define mmGDS_VMID13_BASE 0x331a +#define mmGDS_VMID14_BASE 0x331c +#define mmGDS_VMID15_BASE 0x331e +#define mmGDS_VMID0_SIZE 0x3301 +#define mmGDS_VMID1_SIZE 0x3303 +#define mmGDS_VMID2_SIZE 0x3305 +#define mmGDS_VMID3_SIZE 0x3307 +#define mmGDS_VMID4_SIZE 0x3309 +#define mmGDS_VMID5_SIZE 0x330b +#define mmGDS_VMID6_SIZE 0x330d +#define mmGDS_VMID7_SIZE 0x330f +#define mmGDS_VMID8_SIZE 0x3311 +#define mmGDS_VMID9_SIZE 0x3313 +#define mmGDS_VMID10_SIZE 0x3315 +#define mmGDS_VMID11_SIZE 0x3317 +#define mmGDS_VMID12_SIZE 0x3319 +#define mmGDS_VMID13_SIZE 0x331b +#define mmGDS_VMID14_SIZE 0x331d +#define mmGDS_VMID15_SIZE 0x331f +#define mmGDS_GWS_VMID0 0x3320 +#define mmGDS_GWS_VMID1 0x3321 +#define mmGDS_GWS_VMID2 0x3322 +#define mmGDS_GWS_VMID3 0x3323 +#define mmGDS_GWS_VMID4 0x3324 +#define mmGDS_GWS_VMID5 0x3325 +#define mmGDS_GWS_VMID6 0x3326 +#define mmGDS_GWS_VMID7 0x3327 +#define mmGDS_GWS_VMID8 0x3328 +#define mmGDS_GWS_VMID9 0x3329 +#define mmGDS_GWS_VMID10 0x332a +#define mmGDS_GWS_VMID11 0x332b +#define mmGDS_GWS_VMID12 0x332c +#define mmGDS_GWS_VMID13 0x332d +#define mmGDS_GWS_VMID14 0x332e +#define mmGDS_GWS_VMID15 0x332f +#define mmGDS_OA_VMID0 0x3330 +#define mmGDS_OA_VMID1 0x3331 +#define mmGDS_OA_VMID2 0x3332 +#define mmGDS_OA_VMID3 0x3333 +#define mmGDS_OA_VMID4 0x3334 +#define mmGDS_OA_VMID5 0x3335 +#define mmGDS_OA_VMID6 0x3336 +#define mmGDS_OA_VMID7 0x3337 +#define mmGDS_OA_VMID8 0x3338 +#define mmGDS_OA_VMID9 0x3339 +#define mmGDS_OA_VMID10 0x333a +#define mmGDS_OA_VMID11 0x333b +#define mmGDS_OA_VMID12 0x333c +#define mmGDS_OA_VMID13 0x333d +#define mmGDS_OA_VMID14 0x333e +#define mmGDS_OA_VMID15 0x333f +#define mmGDS_GWS_RESET0 0x3344 +#define mmGDS_GWS_RESET1 0x3345 +#define mmGDS_GWS_RESOURCE_RESET 0x3346 +#define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348 +#define mmGDS_OA_RESET_MASK 0x3349 +#define mmGDS_OA_RESET 0x334a +#define mmCS_COPY_STATE 0xa1f3 +#define mmGFX_COPY_STATE 0xa1f4 +#define mmVGT_DRAW_INITIATOR 0xa1fc +#define mmVGT_EVENT_INITIATOR 0xa2a4 +#define mmVGT_EVENT_ADDRESS_REG 0xa1fe +#define mmVGT_DMA_BASE_HI 0xa1f9 +#define mmVGT_DMA_BASE 0xa1fa +#define mmVGT_DMA_INDEX_TYPE 0xa29f +#define mmVGT_DMA_NUM_INSTANCES 0xa2a2 +#define mmIA_ENHANCE 0xa29c +#define mmVGT_DMA_SIZE 0xa29d +#define mmVGT_DMA_MAX_SIZE 0xa29e +#define mmVGT_DMA_PRIMITIVE_TYPE 0x2271 +#define mmVGT_DMA_CONTROL 0x2272 +#define mmVGT_IMMED_DATA 0xa1fd +#define mmVGT_INDEX_TYPE 0xc243 +#define mmVGT_NUM_INDICES 0xc24c +#define mmVGT_NUM_INSTANCES 0xc24d +#define mmVGT_PRIMITIVE_TYPE 0xc242 +#define mmVGT_PRIMITIVEID_EN 0xa2a1 +#define mmVGT_PRIMITIVEID_RESET 0xa2a3 +#define mmVGT_VTX_CNT_EN 0xa2ae +#define mmVGT_REUSE_OFF 0xa2ad +#define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8 +#define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9 +#define mmVGT_MAX_VTX_INDX 0xa100 +#define mmVGT_MIN_VTX_INDX 0xa101 +#define mmVGT_INDX_OFFSET 0xa102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316 +#define mmVGT_OUT_DEALLOC_CNTL 0xa317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103 +#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5 +#define mmVGT_ENHANCE 0xa294 +#define mmVGT_OUTPUT_PATH_CNTL 0xa284 +#define mmVGT_HOS_CNTL 0xa285 +#define mmVGT_HOS_MAX_TESS_LEVEL 0xa286 +#define mmVGT_HOS_MIN_TESS_LEVEL 0xa287 +#define mmVGT_HOS_REUSE_DEPTH 0xa288 +#define mmVGT_GROUP_PRIM_TYPE 0xa289 +#define mmVGT_GROUP_FIRST_DECR 0xa28a +#define mmVGT_GROUP_DECR 0xa28b +#define mmVGT_GROUP_VECT_0_CNTL 0xa28c +#define mmVGT_GROUP_VECT_1_CNTL 0xa28d +#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e +#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f +#define mmVGT_VTX_VECT_EJECT_REG 0x222c +#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d +#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e +#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f +#define mmVGT_LAST_COPY_STATE 0x2230 +#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f +#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 +#define mmVGT_GS_MODE 0xa290 +#define mmVGT_GS_ONCHIP_CNTL 0xa291 +#define mmVGT_GS_OUT_PRIM_TYPE 0xa29b +#define mmVGT_CACHE_INVALIDATION 0x2231 +#define mmVGT_RESET_DEBUG 0x2232 +#define mmVGT_STRMOUT_DELAY 0x2233 +#define mmVGT_FIFO_DEPTHS 0x2234 +#define mmVGT_GS_PER_ES 0xa295 +#define mmVGT_ES_PER_GS 0xa296 +#define mmVGT_GS_PER_VS 0xa297 +#define mmVGT_GS_VERTEX_REUSE 0x2235 +#define mmVGT_MC_LAT_CNTL 0x2236 +#define mmIA_CNTL_STATUS 0x2237 +#define mmVGT_STRMOUT_CONFIG 0xa2e5 +#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4 +#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8 +#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc +#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0 +#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7 +#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb +#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf +#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3 +#define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5 +#define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9 +#define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd +#define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1 +#define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247 +#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca +#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb +#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc +#define mmVGT_GS_MAX_VERT_OUT 0xa2ce +#define mmIA_VMID_OVERRIDE 0x2260 +#define mmVGT_SHADER_STAGES_EN 0xa2d5 +#define mmVGT_LS_HS_CONFIG 0xa2d6 +#define mmVGT_DMA_LS_HS_CONFIG 0x2273 +#define mmVGT_TF_PARAM 0xa2db +#define mmVGT_TF_RING_SIZE 0xc24e +#define mmVGT_SYS_CONFIG 0x2263 +#define mmVGT_HS_OFFCHIP_PARAM 0xc24f +#define mmVGT_TF_MEMORY_BASE 0xc250 +#define mmVGT_GS_INSTANCE_CNT 0xa2e4 +#define mmIA_MULTI_VGT_PARAM 0xa2aa +#define mmVGT_VS_MAX_WAVE_ID 0x2268 +#define mmVGT_ESGS_RING_SIZE 0xc240 +#define mmVGT_GSVS_RING_SIZE 0xc241 +#define mmVGT_GSVS_RING_OFFSET_1 0xa298 +#define mmVGT_GSVS_RING_OFFSET_2 0xa299 +#define mmVGT_GSVS_RING_OFFSET_3 0xa29a +#define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab +#define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac +#define mmVGT_GS_VERT_ITEMSIZE 0xa2d7 +#define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8 +#define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9 +#define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da +#define mmWD_CNTL_STATUS 0x223f +#define mmWD_ENHANCE 0xa2a0 +#define mmGFX_PIPE_CONTROL 0x226d +#define mmGFX_PIPE_PRIORITY 0xf87f +#define mmCGTT_VGT_CLK_CTRL 0xf084 +#define mmCGTT_IA_CLK_CTRL 0xf085 +#define mmCGTT_WD_CLK_CTRL 0xf086 +#define mmVGT_DEBUG_CNTL 0x2238 +#define mmVGT_DEBUG_DATA 0x2239 +#define mmIA_DEBUG_CNTL 0x223a +#define mmIA_DEBUG_DATA 0x223b +#define mmVGT_CNTL_STATUS 0x223c +#define mmWD_DEBUG_CNTL 0x223d +#define mmWD_DEBUG_DATA 0x223e +#define mmCC_GC_PRIM_CONFIG 0x2240 +#define mmGC_USER_PRIM_CONFIG 0x2241 +#define ixWD_DEBUG_REG0 0x0 +#define ixWD_DEBUG_REG1 0x1 +#define ixWD_DEBUG_REG2 0x2 +#define ixWD_DEBUG_REG3 0x3 +#define ixWD_DEBUG_REG4 0x4 +#define ixWD_DEBUG_REG5 0x5 +#define ixIA_DEBUG_REG0 0x0 +#define ixIA_DEBUG_REG1 0x1 +#define ixIA_DEBUG_REG2 0x2 +#define ixIA_DEBUG_REG3 0x3 +#define ixIA_DEBUG_REG4 0x4 +#define ixIA_DEBUG_REG5 0x5 +#define ixIA_DEBUG_REG6 0x6 +#define ixIA_DEBUG_REG7 0x7 +#define ixIA_DEBUG_REG8 0x8 +#define ixIA_DEBUG_REG9 0x9 +#define ixVGT_DEBUG_REG0 0x0 +#define ixVGT_DEBUG_REG1 0x1 +#define ixVGT_DEBUG_REG2 0x1e +#define ixVGT_DEBUG_REG3 0x1f +#define ixVGT_DEBUG_REG4 0x20 +#define ixVGT_DEBUG_REG5 0x21 +#define ixVGT_DEBUG_REG6 0x22 +#define ixVGT_DEBUG_REG7 0x23 +#define ixVGT_DEBUG_REG8 0x8 +#define ixVGT_DEBUG_REG9 0x9 +#define ixVGT_DEBUG_REG10 0xa +#define ixVGT_DEBUG_REG11 0xb +#define ixVGT_DEBUG_REG12 0xc +#define ixVGT_DEBUG_REG13 0xd +#define ixVGT_DEBUG_REG14 0xe +#define ixVGT_DEBUG_REG15 0xf +#define ixVGT_DEBUG_REG16 0x10 +#define ixVGT_DEBUG_REG17 0x11 +#define ixVGT_DEBUG_REG18 0x7 +#define ixVGT_DEBUG_REG19 0x13 +#define ixVGT_DEBUG_REG20 0x14 +#define ixVGT_DEBUG_REG21 0x15 +#define ixVGT_DEBUG_REG22 0x16 +#define ixVGT_DEBUG_REG23 0x17 +#define ixVGT_DEBUG_REG24 0x18 +#define ixVGT_DEBUG_REG25 0x19 +#define ixVGT_DEBUG_REG26 0x24 +#define ixVGT_DEBUG_REG27 0x1b +#define ixVGT_DEBUG_REG28 0x1c +#define ixVGT_DEBUG_REG29 0x1d +#define ixVGT_DEBUG_REG30 0x25 +#define ixVGT_DEBUG_REG31 0x26 +#define ixVGT_DEBUG_REG32 0x27 +#define ixVGT_DEBUG_REG33 0x28 +#define ixVGT_DEBUG_REG34 0x29 +#define ixVGT_DEBUG_REG35 0x2a +#define mmVGT_PERFCOUNTER_SEID_MASK 0xd894 +#define mmVGT_PERFCOUNTER0_SELECT 0xd88c +#define mmVGT_PERFCOUNTER1_SELECT 0xd88d +#define mmVGT_PERFCOUNTER2_SELECT 0xd88e +#define mmVGT_PERFCOUNTER3_SELECT 0xd88f +#define mmVGT_PERFCOUNTER0_SELECT1 0xd890 +#define mmVGT_PERFCOUNTER1_SELECT1 0xd891 +#define mmVGT_PERFCOUNTER0_LO 0xd090 +#define mmVGT_PERFCOUNTER1_LO 0xd092 +#define mmVGT_PERFCOUNTER2_LO 0xd094 +#define mmVGT_PERFCOUNTER3_LO 0xd096 +#define mmVGT_PERFCOUNTER0_HI 0xd091 +#define mmVGT_PERFCOUNTER1_HI 0xd093 +#define mmVGT_PERFCOUNTER2_HI 0xd095 +#define mmVGT_PERFCOUNTER3_HI 0xd097 +#define mmIA_PERFCOUNTER0_SELECT 0xd884 +#define mmIA_PERFCOUNTER1_SELECT 0xd885 +#define mmIA_PERFCOUNTER2_SELECT 0xd886 +#define mmIA_PERFCOUNTER3_SELECT 0xd887 +#define mmIA_PERFCOUNTER0_SELECT1 0xd888 +#define mmIA_PERFCOUNTER0_LO 0xd088 +#define mmIA_PERFCOUNTER1_LO 0xd08a +#define mmIA_PERFCOUNTER2_LO 0xd08c +#define mmIA_PERFCOUNTER3_LO 0xd08e +#define mmIA_PERFCOUNTER0_HI 0xd089 +#define mmIA_PERFCOUNTER1_HI 0xd08b +#define mmIA_PERFCOUNTER2_HI 0xd08d +#define mmIA_PERFCOUNTER3_HI 0xd08f +#define mmWD_PERFCOUNTER0_SELECT 0xd880 +#define mmWD_PERFCOUNTER1_SELECT 0xd881 +#define mmWD_PERFCOUNTER2_SELECT 0xd882 +#define mmWD_PERFCOUNTER3_SELECT 0xd883 +#define mmWD_PERFCOUNTER0_LO 0xd080 +#define mmWD_PERFCOUNTER1_LO 0xd082 +#define mmWD_PERFCOUNTER2_LO 0xd084 +#define mmWD_PERFCOUNTER3_LO 0xd086 +#define mmWD_PERFCOUNTER0_HI 0xd081 +#define mmWD_PERFCOUNTER1_HI 0xd083 +#define mmWD_PERFCOUNTER2_HI 0xd085 +#define mmWD_PERFCOUNTER3_HI 0xd087 +#define mmDIDT_IND_INDEX 0x3280 +#define mmDIDT_IND_DATA 0x3281 +#define ixDIDT_SQ_CTRL0 0x0 +#define ixDIDT_SQ_CTRL1 0x1 +#define ixDIDT_SQ_CTRL2 0x2 +#define ixDIDT_SQ_WEIGHT0_3 0x10 +#define ixDIDT_SQ_WEIGHT4_7 0x11 +#define ixDIDT_SQ_WEIGHT8_11 0x12 +#define ixDIDT_DB_CTRL0 0x20 +#define ixDIDT_DB_CTRL1 0x21 +#define ixDIDT_DB_CTRL2 0x22 +#define ixDIDT_DB_WEIGHT0_3 0x30 +#define ixDIDT_DB_WEIGHT4_7 0x31 +#define ixDIDT_DB_WEIGHT8_11 0x32 +#define ixDIDT_TD_CTRL0 0x40 +#define ixDIDT_TD_CTRL1 0x41 +#define ixDIDT_TD_CTRL2 0x42 +#define ixDIDT_TD_WEIGHT0_3 0x50 +#define ixDIDT_TD_WEIGHT4_7 0x51 +#define ixDIDT_TD_WEIGHT8_11 0x52 +#define ixDIDT_TCP_CTRL0 0x60 +#define ixDIDT_TCP_CTRL1 0x61 +#define ixDIDT_TCP_CTRL2 0x62 +#define ixDIDT_TCP_WEIGHT0_3 0x70 +#define ixDIDT_TCP_WEIGHT4_7 0x71 +#define ixDIDT_TCP_WEIGHT8_11 0x72 + +#endif /* GFX_7_0_D_H */ -- cgit v1.2.3 From 46d5a27269af9420b925cbbfdd66d3979abd8092 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:20:39 -0400 Subject: drm/amdgpu: add GCA 7.2 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h | 2557 +++ .../drm/amd/include/asic_reg/gca/gfx_7_2_enum.h | 6274 +++++++ .../drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h | 18444 +++++++++++++++++++ 3 files changed, 27275 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h new file mode 100644 index 000000000000..290ce6aa4b71 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h @@ -0,0 +1,2557 @@ +/* + * GFX_7_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_7_2_D_H +#define GFX_7_2_D_H + +#define mmCB_BLEND_RED 0xa105 +#define mmCB_BLEND_GREEN 0xa106 +#define mmCB_BLEND_BLUE 0xa107 +#define mmCB_BLEND_ALPHA 0xa108 +#define mmCB_COLOR_CONTROL 0xa202 +#define mmCB_BLEND0_CONTROL 0xa1e0 +#define mmCB_BLEND1_CONTROL 0xa1e1 +#define mmCB_BLEND2_CONTROL 0xa1e2 +#define mmCB_BLEND3_CONTROL 0xa1e3 +#define mmCB_BLEND4_CONTROL 0xa1e4 +#define mmCB_BLEND5_CONTROL 0xa1e5 +#define mmCB_BLEND6_CONTROL 0xa1e6 +#define mmCB_BLEND7_CONTROL 0xa1e7 +#define mmCB_COLOR0_BASE 0xa318 +#define mmCB_COLOR1_BASE 0xa327 +#define mmCB_COLOR2_BASE 0xa336 +#define mmCB_COLOR3_BASE 0xa345 +#define mmCB_COLOR4_BASE 0xa354 +#define mmCB_COLOR5_BASE 0xa363 +#define mmCB_COLOR6_BASE 0xa372 +#define mmCB_COLOR7_BASE 0xa381 +#define mmCB_COLOR0_PITCH 0xa319 +#define mmCB_COLOR1_PITCH 0xa328 +#define mmCB_COLOR2_PITCH 0xa337 +#define mmCB_COLOR3_PITCH 0xa346 +#define mmCB_COLOR4_PITCH 0xa355 +#define mmCB_COLOR5_PITCH 0xa364 +#define mmCB_COLOR6_PITCH 0xa373 +#define mmCB_COLOR7_PITCH 0xa382 +#define mmCB_COLOR0_SLICE 0xa31a +#define mmCB_COLOR1_SLICE 0xa329 +#define mmCB_COLOR2_SLICE 0xa338 +#define mmCB_COLOR3_SLICE 0xa347 +#define mmCB_COLOR4_SLICE 0xa356 +#define mmCB_COLOR5_SLICE 0xa365 +#define mmCB_COLOR6_SLICE 0xa374 +#define mmCB_COLOR7_SLICE 0xa383 +#define mmCB_COLOR0_VIEW 0xa31b +#define mmCB_COLOR1_VIEW 0xa32a +#define mmCB_COLOR2_VIEW 0xa339 +#define mmCB_COLOR3_VIEW 0xa348 +#define mmCB_COLOR4_VIEW 0xa357 +#define mmCB_COLOR5_VIEW 0xa366 +#define mmCB_COLOR6_VIEW 0xa375 +#define mmCB_COLOR7_VIEW 0xa384 +#define mmCB_COLOR0_INFO 0xa31c +#define mmCB_COLOR1_INFO 0xa32b +#define mmCB_COLOR2_INFO 0xa33a +#define mmCB_COLOR3_INFO 0xa349 +#define mmCB_COLOR4_INFO 0xa358 +#define mmCB_COLOR5_INFO 0xa367 +#define mmCB_COLOR6_INFO 0xa376 +#define mmCB_COLOR7_INFO 0xa385 +#define mmCB_COLOR0_ATTRIB 0xa31d +#define mmCB_COLOR1_ATTRIB 0xa32c +#define mmCB_COLOR2_ATTRIB 0xa33b +#define mmCB_COLOR3_ATTRIB 0xa34a +#define mmCB_COLOR4_ATTRIB 0xa359 +#define mmCB_COLOR5_ATTRIB 0xa368 +#define mmCB_COLOR6_ATTRIB 0xa377 +#define mmCB_COLOR7_ATTRIB 0xa386 +#define mmCB_COLOR0_CMASK 0xa31f +#define mmCB_COLOR1_CMASK 0xa32e +#define mmCB_COLOR2_CMASK 0xa33d +#define mmCB_COLOR3_CMASK 0xa34c +#define mmCB_COLOR4_CMASK 0xa35b +#define mmCB_COLOR5_CMASK 0xa36a +#define mmCB_COLOR6_CMASK 0xa379 +#define mmCB_COLOR7_CMASK 0xa388 +#define mmCB_COLOR0_CMASK_SLICE 0xa320 +#define mmCB_COLOR1_CMASK_SLICE 0xa32f +#define mmCB_COLOR2_CMASK_SLICE 0xa33e +#define mmCB_COLOR3_CMASK_SLICE 0xa34d +#define mmCB_COLOR4_CMASK_SLICE 0xa35c +#define mmCB_COLOR5_CMASK_SLICE 0xa36b +#define mmCB_COLOR6_CMASK_SLICE 0xa37a +#define mmCB_COLOR7_CMASK_SLICE 0xa389 +#define mmCB_COLOR0_FMASK 0xa321 +#define mmCB_COLOR1_FMASK 0xa330 +#define mmCB_COLOR2_FMASK 0xa33f +#define mmCB_COLOR3_FMASK 0xa34e +#define mmCB_COLOR4_FMASK 0xa35d +#define mmCB_COLOR5_FMASK 0xa36c +#define mmCB_COLOR6_FMASK 0xa37b +#define mmCB_COLOR7_FMASK 0xa38a +#define mmCB_COLOR0_FMASK_SLICE 0xa322 +#define mmCB_COLOR1_FMASK_SLICE 0xa331 +#define mmCB_COLOR2_FMASK_SLICE 0xa340 +#define mmCB_COLOR3_FMASK_SLICE 0xa34f +#define mmCB_COLOR4_FMASK_SLICE 0xa35e +#define mmCB_COLOR5_FMASK_SLICE 0xa36d +#define mmCB_COLOR6_FMASK_SLICE 0xa37c +#define mmCB_COLOR7_FMASK_SLICE 0xa38b +#define mmCB_COLOR0_CLEAR_WORD0 0xa323 +#define mmCB_COLOR1_CLEAR_WORD0 0xa332 +#define mmCB_COLOR2_CLEAR_WORD0 0xa341 +#define mmCB_COLOR3_CLEAR_WORD0 0xa350 +#define mmCB_COLOR4_CLEAR_WORD0 0xa35f +#define mmCB_COLOR5_CLEAR_WORD0 0xa36e +#define mmCB_COLOR6_CLEAR_WORD0 0xa37d +#define mmCB_COLOR7_CLEAR_WORD0 0xa38c +#define mmCB_COLOR0_CLEAR_WORD1 0xa324 +#define mmCB_COLOR1_CLEAR_WORD1 0xa333 +#define mmCB_COLOR2_CLEAR_WORD1 0xa342 +#define mmCB_COLOR3_CLEAR_WORD1 0xa351 +#define mmCB_COLOR4_CLEAR_WORD1 0xa360 +#define mmCB_COLOR5_CLEAR_WORD1 0xa36f +#define mmCB_COLOR6_CLEAR_WORD1 0xa37e +#define mmCB_COLOR7_CLEAR_WORD1 0xa38d +#define mmCB_TARGET_MASK 0xa08e +#define mmCB_SHADER_MASK 0xa08f +#define mmCB_HW_CONTROL 0x2684 +#define mmCB_HW_CONTROL_1 0x2685 +#define mmCB_HW_CONTROL_2 0x2686 +#define mmCB_HW_CONTROL_3 0x2683 +#define mmCB_PERFCOUNTER_FILTER 0xdc00 +#define mmCB_PERFCOUNTER0_SELECT 0xdc01 +#define mmCB_PERFCOUNTER0_SELECT1 0xdc02 +#define mmCB_PERFCOUNTER1_SELECT 0xdc03 +#define mmCB_PERFCOUNTER2_SELECT 0xdc04 +#define mmCB_PERFCOUNTER3_SELECT 0xdc05 +#define mmCB_PERFCOUNTER0_LO 0xd406 +#define mmCB_PERFCOUNTER1_LO 0xd408 +#define mmCB_PERFCOUNTER2_LO 0xd40a +#define mmCB_PERFCOUNTER3_LO 0xd40c +#define mmCB_PERFCOUNTER0_HI 0xd407 +#define mmCB_PERFCOUNTER1_HI 0xd409 +#define mmCB_PERFCOUNTER2_HI 0xd40b +#define mmCB_PERFCOUNTER3_HI 0xd40d +#define mmCB_CGTT_SCLK_CTRL 0xf0a8 +#define mmCB_DEBUG_BUS_1 0x2699 +#define mmCB_DEBUG_BUS_2 0x269a +#define mmCB_DEBUG_BUS_3 0x269b +#define mmCB_DEBUG_BUS_4 0x269c +#define mmCB_DEBUG_BUS_5 0x269d +#define mmCB_DEBUG_BUS_6 0x269e +#define mmCB_DEBUG_BUS_7 0x269f +#define mmCB_DEBUG_BUS_8 0x26a0 +#define mmCB_DEBUG_BUS_9 0x26a1 +#define mmCB_DEBUG_BUS_10 0x26a2 +#define mmCB_DEBUG_BUS_11 0x26a3 +#define mmCB_DEBUG_BUS_12 0x26a4 +#define mmCB_DEBUG_BUS_13 0x26a5 +#define mmCB_DEBUG_BUS_14 0x26a6 +#define mmCB_DEBUG_BUS_15 0x26a7 +#define mmCB_DEBUG_BUS_16 0x26a8 +#define mmCB_DEBUG_BUS_17 0x26a9 +#define mmCB_DEBUG_BUS_18 0x26aa +#define mmCP_DFY_CNTL 0x3020 +#define mmCP_DFY_STAT 0x3021 +#define mmCP_DFY_ADDR_HI 0x3022 +#define mmCP_DFY_ADDR_LO 0x3023 +#define mmCP_DFY_DATA_0 0x3024 +#define mmCP_DFY_DATA_1 0x3025 +#define mmCP_DFY_DATA_2 0x3026 +#define mmCP_DFY_DATA_3 0x3027 +#define mmCP_DFY_DATA_4 0x3028 +#define mmCP_DFY_DATA_5 0x3029 +#define mmCP_DFY_DATA_6 0x302a +#define mmCP_DFY_DATA_7 0x302b +#define mmCP_DFY_DATA_8 0x302c +#define mmCP_DFY_DATA_9 0x302d +#define mmCP_DFY_DATA_10 0x302e +#define mmCP_DFY_DATA_11 0x302f +#define mmCP_DFY_DATA_12 0x3030 +#define mmCP_DFY_DATA_13 0x3031 +#define mmCP_DFY_DATA_14 0x3032 +#define mmCP_DFY_DATA_15 0x3033 +#define mmCP_RB0_BASE 0x3040 +#define mmCP_RB0_BASE_HI 0x30b1 +#define mmCP_RB_BASE 0x3040 +#define mmCP_RB1_BASE 0x3060 +#define mmCP_RB1_BASE_HI 0x30b2 +#define mmCP_RB2_BASE 0x3065 +#define mmCP_RB0_CNTL 0x3041 +#define mmCP_RB_CNTL 0x3041 +#define mmCP_RB1_CNTL 0x3061 +#define mmCP_RB2_CNTL 0x3066 +#define mmCP_RB_RPTR_WR 0x3042 +#define mmCP_RB0_RPTR_ADDR 0x3043 +#define mmCP_RB_RPTR_ADDR 0x3043 +#define mmCP_RB1_RPTR_ADDR 0x3062 +#define mmCP_RB2_RPTR_ADDR 0x3067 +#define mmCP_RB0_RPTR_ADDR_HI 0x3044 +#define mmCP_RB_RPTR_ADDR_HI 0x3044 +#define mmCP_RB1_RPTR_ADDR_HI 0x3063 +#define mmCP_RB2_RPTR_ADDR_HI 0x3068 +#define mmCP_RB0_WPTR 0x3045 +#define mmCP_RB_WPTR 0x3045 +#define mmCP_RB1_WPTR 0x3064 +#define mmCP_RB2_WPTR 0x3069 +#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 +#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 +#define mmGC_PRIV_MODE 0x3048 +#define mmCP_INT_CNTL 0x3049 +#define mmCP_INT_CNTL_RING0 0x306a +#define mmCP_INT_CNTL_RING1 0x306b +#define mmCP_INT_CNTL_RING2 0x306c +#define mmCP_INT_STATUS 0x304a +#define mmCP_INT_STATUS_RING0 0x306d +#define mmCP_INT_STATUS_RING1 0x306e +#define mmCP_INT_STATUS_RING2 0x306f +#define mmCP_DEVICE_ID 0x304b +#define mmCP_RING_PRIORITY_CNTS 0x304c +#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c +#define mmCP_RING0_PRIORITY 0x304d +#define mmCP_ME0_PIPE0_PRIORITY 0x304d +#define mmCP_RING1_PRIORITY 0x304e +#define mmCP_ME0_PIPE1_PRIORITY 0x304e +#define mmCP_RING2_PRIORITY 0x304f +#define mmCP_ME0_PIPE2_PRIORITY 0x304f +#define mmCP_ENDIAN_SWAP 0x3050 +#define mmCP_RB_VMID 0x3051 +#define mmCP_ME0_PIPE0_VMID 0x3052 +#define mmCP_ME0_PIPE1_VMID 0x3053 +#define mmCP_PFP_UCODE_ADDR 0x3054 +#define mmCP_PFP_UCODE_DATA 0x3055 +#define mmCP_ME_RAM_RADDR 0x3056 +#define mmCP_ME_RAM_WADDR 0x3057 +#define mmCP_ME_RAM_DATA 0x3058 +#define mmCGTT_CPC_CLK_CTRL 0xf0b2 +#define mmCGTT_CPF_CLK_CTRL 0xf0b1 +#define mmCGTT_CP_CLK_CTRL 0xf0b0 +#define mmCP_CE_UCODE_ADDR 0x305a +#define mmCP_CE_UCODE_DATA 0x305b +#define mmCP_MEC_ME1_UCODE_ADDR 0x305c +#define mmCP_MEC_ME1_UCODE_DATA 0x305d +#define mmCP_MEC_ME2_UCODE_ADDR 0x305e +#define mmCP_MEC_ME2_UCODE_DATA 0x305f +#define mmCP_PWR_CNTL 0x3078 +#define mmCP_MEM_SLP_CNTL 0x3079 +#define mmCP_ECC_FIRSTOCCURRENCE 0x307a +#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b +#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c +#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d +#define mmCP_CPF_DEBUG 0x3080 +#define mmCP_FETCHER_SOURCE 0x3082 +#define mmCP_PQ_WPTR_POLL_CNTL 0x3083 +#define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 +#define mmCPC_INT_CNTL 0x30b4 +#define mmCP_ME1_PIPE0_INT_CNTL 0x3085 +#define mmCP_ME1_PIPE1_INT_CNTL 0x3086 +#define mmCP_ME1_PIPE2_INT_CNTL 0x3087 +#define mmCP_ME1_PIPE3_INT_CNTL 0x3088 +#define mmCP_ME2_PIPE0_INT_CNTL 0x3089 +#define mmCP_ME2_PIPE1_INT_CNTL 0x308a +#define mmCP_ME2_PIPE2_INT_CNTL 0x308b +#define mmCP_ME2_PIPE3_INT_CNTL 0x308c +#define mmCPC_INT_STATUS 0x30b5 +#define mmCP_ME1_PIPE0_INT_STATUS 0x308d +#define mmCP_ME1_PIPE1_INT_STATUS 0x308e +#define mmCP_ME1_PIPE2_INT_STATUS 0x308f +#define mmCP_ME1_PIPE3_INT_STATUS 0x3090 +#define mmCP_ME2_PIPE0_INT_STATUS 0x3091 +#define mmCP_ME2_PIPE1_INT_STATUS 0x3092 +#define mmCP_ME2_PIPE2_INT_STATUS 0x3093 +#define mmCP_ME2_PIPE3_INT_STATUS 0x3094 +#define mmCP_ME1_INT_STAT_DEBUG 0x3095 +#define mmCP_ME2_INT_STAT_DEBUG 0x3096 +#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099 +#define mmCP_ME1_PIPE0_PRIORITY 0x309a +#define mmCP_ME1_PIPE1_PRIORITY 0x309b +#define mmCP_ME1_PIPE2_PRIORITY 0x309c +#define mmCP_ME1_PIPE3_PRIORITY 0x309d +#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e +#define mmCP_ME2_PIPE0_PRIORITY 0x309f +#define mmCP_ME2_PIPE1_PRIORITY 0x30a0 +#define mmCP_ME2_PIPE2_PRIORITY 0x30a1 +#define mmCP_ME2_PIPE3_PRIORITY 0x30a2 +#define mmCP_CE_PRGRM_CNTR_START 0x30a3 +#define mmCP_PFP_PRGRM_CNTR_START 0x30a4 +#define mmCP_ME_PRGRM_CNTR_START 0x30a5 +#define mmCP_MEC1_PRGRM_CNTR_START 0x30a6 +#define mmCP_MEC2_PRGRM_CNTR_START 0x30a7 +#define mmCP_CE_INTR_ROUTINE_START 0x30a8 +#define mmCP_PFP_INTR_ROUTINE_START 0x30a9 +#define mmCP_ME_INTR_ROUTINE_START 0x30aa +#define mmCP_MEC1_INTR_ROUTINE_START 0x30ab +#define mmCP_MEC2_INTR_ROUTINE_START 0x30ac +#define mmCP_CONTEXT_CNTL 0x30ad +#define mmCP_MAX_CONTEXT 0x30ae +#define mmCP_IQ_WAIT_TIME1 0x30af +#define mmCP_IQ_WAIT_TIME2 0x30b0 +#define mmCP_VMID_RESET 0x30b3 +#define mmCP_VMID_PREEMPT 0x30b6 +#define mmCPC_INT_CNTX_ID 0x30b7 +#define mmCP_PQ_STATUS 0x30b8 +#define mmCP_CPC_STATUS 0x2084 +#define mmCP_CPC_BUSY_STAT 0x2085 +#define mmCP_CPC_STALLED_STAT1 0x2086 +#define mmCP_CPF_STATUS 0x2087 +#define mmCP_CPF_BUSY_STAT 0x2088 +#define mmCP_CPF_STALLED_STAT1 0x2089 +#define mmCP_CPC_MC_CNTL 0x208a +#define mmCP_CPC_GRBM_FREE_COUNT 0x208b +#define mmCP_MEC_CNTL 0x208d +#define mmCP_MEC_ME1_HEADER_DUMP 0x208e +#define mmCP_MEC_ME2_HEADER_DUMP 0x208f +#define mmCP_CPC_SCRATCH_INDEX 0x2090 +#define mmCP_CPC_SCRATCH_DATA 0x2091 +#define mmCPG_PERFCOUNTER1_SELECT 0xd800 +#define mmCPG_PERFCOUNTER1_LO 0xd000 +#define mmCPG_PERFCOUNTER1_HI 0xd001 +#define mmCPG_PERFCOUNTER0_SELECT1 0xd801 +#define mmCPG_PERFCOUNTER0_SELECT 0xd802 +#define mmCPG_PERFCOUNTER0_LO 0xd002 +#define mmCPG_PERFCOUNTER0_HI 0xd003 +#define mmCPC_PERFCOUNTER1_SELECT 0xd803 +#define mmCPC_PERFCOUNTER1_LO 0xd004 +#define mmCPC_PERFCOUNTER1_HI 0xd005 +#define mmCPC_PERFCOUNTER0_SELECT1 0xd804 +#define mmCPC_PERFCOUNTER0_SELECT 0xd809 +#define mmCPC_PERFCOUNTER0_LO 0xd006 +#define mmCPC_PERFCOUNTER0_HI 0xd007 +#define mmCPF_PERFCOUNTER1_SELECT 0xd805 +#define mmCPF_PERFCOUNTER1_LO 0xd008 +#define mmCPF_PERFCOUNTER1_HI 0xd009 +#define mmCPF_PERFCOUNTER0_SELECT1 0xd806 +#define mmCPF_PERFCOUNTER0_SELECT 0xd807 +#define mmCPF_PERFCOUNTER0_LO 0xd00a +#define mmCPF_PERFCOUNTER0_HI 0xd00b +#define mmCP_CPC_HALT_HYST_COUNT 0x20a7 +#define mmCP_DRAW_OBJECT 0xd810 +#define mmCP_DRAW_OBJECT_COUNTER 0xd811 +#define mmCP_DRAW_WINDOW_MASK_HI 0xd812 +#define mmCP_DRAW_WINDOW_HI 0xd813 +#define mmCP_DRAW_WINDOW_LO 0xd814 +#define mmCP_DRAW_WINDOW_CNTL 0xd815 +#define mmCP_PRT_LOD_STATS_CNTL0 0x20ad +#define mmCP_PRT_LOD_STATS_CNTL1 0x20ae +#define mmCP_PRT_LOD_STATS_CNTL2 0x20af +#define mmCP_CE_COMPARE_COUNT 0x20c0 +#define mmCP_CE_DE_COUNT 0x20c1 +#define mmCP_DE_CE_COUNT 0x20c2 +#define mmCP_DE_LAST_INVAL_COUNT 0x20c3 +#define mmCP_DE_DE_COUNT 0x20c4 +#define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5 +#define mmCP_EOP_DONE_DATA_CNTL 0xc0d6 +#define mmCP_EOP_DONE_ADDR_LO 0xc000 +#define mmCP_EOP_DONE_ADDR_HI 0xc001 +#define mmCP_EOP_DONE_DATA_LO 0xc002 +#define mmCP_EOP_DONE_DATA_HI 0xc003 +#define mmCP_EOP_LAST_FENCE_LO 0xc004 +#define mmCP_EOP_LAST_FENCE_HI 0xc005 +#define mmCP_STREAM_OUT_ADDR_LO 0xc006 +#define mmCP_STREAM_OUT_ADDR_HI 0xc007 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009 +#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a +#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d +#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e +#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017 +#define mmCP_PIPE_STATS_ADDR_LO 0xc018 +#define mmCP_PIPE_STATS_ADDR_HI 0xc019 +#define mmCP_VGT_IAVERT_COUNT_LO 0xc01a +#define mmCP_VGT_IAVERT_COUNT_HI 0xc01b +#define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c +#define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d +#define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e +#define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f +#define mmCP_VGT_VSINVOC_COUNT_LO 0xc020 +#define mmCP_VGT_VSINVOC_COUNT_HI 0xc021 +#define mmCP_VGT_GSINVOC_COUNT_LO 0xc022 +#define mmCP_VGT_GSINVOC_COUNT_HI 0xc023 +#define mmCP_VGT_HSINVOC_COUNT_LO 0xc024 +#define mmCP_VGT_HSINVOC_COUNT_HI 0xc025 +#define mmCP_VGT_DSINVOC_COUNT_LO 0xc026 +#define mmCP_VGT_DSINVOC_COUNT_HI 0xc027 +#define mmCP_PA_CINVOC_COUNT_LO 0xc028 +#define mmCP_PA_CINVOC_COUNT_HI 0xc029 +#define mmCP_PA_CPRIM_COUNT_LO 0xc02a +#define mmCP_PA_CPRIM_COUNT_HI 0xc02b +#define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c +#define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d +#define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e +#define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f +#define mmCP_VGT_CSINVOC_COUNT_LO 0xc030 +#define mmCP_VGT_CSINVOC_COUNT_HI 0xc031 +#define mmCP_STRMOUT_CNTL 0xc03f +#define mmSCRATCH_REG0 0xc040 +#define mmSCRATCH_REG1 0xc041 +#define mmSCRATCH_REG2 0xc042 +#define mmSCRATCH_REG3 0xc043 +#define mmSCRATCH_REG4 0xc044 +#define mmSCRATCH_REG5 0xc045 +#define mmSCRATCH_REG6 0xc046 +#define mmSCRATCH_REG7 0xc047 +#define mmSCRATCH_UMSK 0xc050 +#define mmSCRATCH_ADDR 0xc051 +#define mmCP_PFP_ATOMIC_PREOP_LO 0xc052 +#define mmCP_PFP_ATOMIC_PREOP_HI 0xc053 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057 +#define mmCP_APPEND_ADDR_LO 0xc058 +#define mmCP_APPEND_ADDR_HI 0xc059 +#define mmCP_APPEND_DATA 0xc05a +#define mmCP_APPEND_LAST_CS_FENCE 0xc05b +#define mmCP_APPEND_LAST_PS_FENCE 0xc05c +#define mmCP_ATOMIC_PREOP_LO 0xc05d +#define mmCP_ME_ATOMIC_PREOP_LO 0xc05d +#define mmCP_ATOMIC_PREOP_HI 0xc05e +#define mmCP_ME_ATOMIC_PREOP_HI 0xc05e +#define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f +#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f +#define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060 +#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060 +#define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061 +#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061 +#define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062 +#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062 +#define mmCP_ME_MC_WADDR_LO 0xc069 +#define mmCP_ME_MC_WADDR_HI 0xc06a +#define mmCP_ME_MC_WDATA_LO 0xc06b +#define mmCP_ME_MC_WDATA_HI 0xc06c +#define mmCP_ME_MC_RADDR_LO 0xc06d +#define mmCP_ME_MC_RADDR_HI 0xc06e +#define mmCP_SEM_WAIT_TIMER 0xc06f +#define mmCP_SIG_SEM_ADDR_LO 0xc070 +#define mmCP_SIG_SEM_ADDR_HI 0xc071 +#define mmCP_WAIT_SEM_ADDR_LO 0xc075 +#define mmCP_WAIT_SEM_ADDR_HI 0xc076 +#define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074 +#define mmCP_COHER_START_DELAY 0xc07b +#define mmCP_COHER_CNTL 0xc07c +#define mmCP_COHER_SIZE 0xc07d +#define mmCP_COHER_SIZE_HI 0xc08c +#define mmCP_COHER_BASE 0xc07e +#define mmCP_COHER_BASE_HI 0xc079 +#define mmCP_COHER_STATUS 0xc07f +#define mmCOHER_DEST_BASE_0 0xa092 +#define mmCOHER_DEST_BASE_1 0xa093 +#define mmCOHER_DEST_BASE_2 0xa07e +#define mmCOHER_DEST_BASE_3 0xa07f +#define mmCOHER_DEST_BASE_HI_0 0xa07a +#define mmCOHER_DEST_BASE_HI_1 0xa07b +#define mmCOHER_DEST_BASE_HI_2 0xa07c +#define mmCOHER_DEST_BASE_HI_3 0xa07d +#define mmCP_DMA_ME_SRC_ADDR 0xc080 +#define mmCP_DMA_ME_SRC_ADDR_HI 0xc081 +#define mmCP_DMA_ME_DST_ADDR 0xc082 +#define mmCP_DMA_ME_DST_ADDR_HI 0xc083 +#define mmCP_DMA_ME_CONTROL 0xc078 +#define mmCP_DMA_ME_COMMAND 0xc084 +#define mmCP_DMA_PFP_SRC_ADDR 0xc085 +#define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086 +#define mmCP_DMA_PFP_DST_ADDR 0xc087 +#define mmCP_DMA_PFP_DST_ADDR_HI 0xc088 +#define mmCP_DMA_PFP_CONTROL 0xc077 +#define mmCP_DMA_PFP_COMMAND 0xc089 +#define mmCP_DMA_CNTL 0xc08a +#define mmCP_DMA_READ_TAGS 0xc08b +#define mmCP_PFP_IB_CONTROL 0xc08d +#define mmCP_PFP_LOAD_CONTROL 0xc08e +#define mmCP_SCRATCH_INDEX 0xc08f +#define mmCP_SCRATCH_DATA 0xc090 +#define mmCP_RB_OFFSET 0xc091 +#define mmCP_IB1_OFFSET 0xc092 +#define mmCP_IB2_OFFSET 0xc093 +#define mmCP_IB1_PREAMBLE_BEGIN 0xc094 +#define mmCP_IB1_PREAMBLE_END 0xc095 +#define mmCP_IB2_PREAMBLE_BEGIN 0xc096 +#define mmCP_IB2_PREAMBLE_END 0xc097 +#define mmCP_CE_IB1_OFFSET 0xc098 +#define mmCP_CE_IB2_OFFSET 0xc099 +#define mmCP_CE_COUNTER 0xc09a +#define mmCP_STALLED_STAT1 0x219d +#define mmCP_STALLED_STAT2 0x219e +#define mmCP_STALLED_STAT3 0x219c +#define mmCP_BUSY_STAT 0x219f +#define mmCP_STAT 0x21a0 +#define mmCP_ME_HEADER_DUMP 0x21a1 +#define mmCP_PFP_HEADER_DUMP 0x21a2 +#define mmCP_GRBM_FREE_COUNT 0x21a3 +#define mmCP_CE_HEADER_DUMP 0x21a4 +#define mmCP_MC_PACK_DELAY_CNT 0x21a7 +#define mmCP_MC_TAG_CNTL 0x21a8 +#define mmCP_MC_TAG_DATA 0x21a9 +#define mmCP_CSF_STAT 0x21b4 +#define mmCP_CSF_CNTL 0x21b5 +#define mmCP_ME_CNTL 0x21b6 +#define mmCP_CNTX_STAT 0x21b8 +#define mmCP_ME_PREEMPTION 0x21b9 +#define mmCP_RB0_RPTR 0x21c0 +#define mmCP_RB_RPTR 0x21c0 +#define mmCP_RB1_RPTR 0x21bf +#define mmCP_RB2_RPTR 0x21be +#define mmCP_RB_WPTR_DELAY 0x21c1 +#define mmCP_RB_WPTR_POLL_CNTL 0x21c2 +#define mmCP_CE_INIT_BASE_LO 0xc0c3 +#define mmCP_CE_INIT_BASE_HI 0xc0c4 +#define mmCP_CE_INIT_BUFSZ 0xc0c5 +#define mmCP_CE_IB1_BASE_LO 0xc0c6 +#define mmCP_CE_IB1_BASE_HI 0xc0c7 +#define mmCP_CE_IB1_BUFSZ 0xc0c8 +#define mmCP_CE_IB2_BASE_LO 0xc0c9 +#define mmCP_CE_IB2_BASE_HI 0xc0ca +#define mmCP_CE_IB2_BUFSZ 0xc0cb +#define mmCP_IB1_BASE_LO 0xc0cc +#define mmCP_IB1_BASE_HI 0xc0cd +#define mmCP_IB1_BUFSZ 0xc0ce +#define mmCP_IB2_BASE_LO 0xc0cf +#define mmCP_IB2_BASE_HI 0xc0d0 +#define mmCP_IB2_BUFSZ 0xc0d1 +#define mmCP_ST_BASE_LO 0xc0d2 +#define mmCP_ST_BASE_HI 0xc0d3 +#define mmCP_ST_BUFSZ 0xc0d4 +#define mmCP_ROQ_THRESHOLDS 0x21bc +#define mmCP_MEQ_STQ_THRESHOLD 0x21bd +#define mmCP_ROQ1_THRESHOLDS 0x21d5 +#define mmCP_ROQ2_THRESHOLDS 0x21d6 +#define mmCP_STQ_THRESHOLDS 0x21d7 +#define mmCP_QUEUE_THRESHOLDS 0x21d8 +#define mmCP_MEQ_THRESHOLDS 0x21d9 +#define mmCP_ROQ_AVAIL 0x21da +#define mmCP_STQ_AVAIL 0x21db +#define mmCP_ROQ2_AVAIL 0x21dc +#define mmCP_MEQ_AVAIL 0x21dd +#define mmCP_CMD_INDEX 0x21de +#define mmCP_CMD_DATA 0x21df +#define mmCP_ROQ_RB_STAT 0x21e0 +#define mmCP_ROQ_IB1_STAT 0x21e1 +#define mmCP_ROQ_IB2_STAT 0x21e2 +#define mmCP_STQ_STAT 0x21e3 +#define mmCP_STQ_WR_STAT 0x21e4 +#define mmCP_MEQ_STAT 0x21e5 +#define mmCP_CEQ1_AVAIL 0x21e6 +#define mmCP_CEQ2_AVAIL 0x21e7 +#define mmCP_CE_ROQ_RB_STAT 0x21e8 +#define mmCP_CE_ROQ_IB1_STAT 0x21e9 +#define mmCP_CE_ROQ_IB2_STAT 0x21ea +#define mmCP_INT_STAT_DEBUG 0x21f7 +#define mmCP_PERFMON_CNTL 0xd808 +#define mmCP_PERFMON_CNTX_CNTL 0xa0d8 +#define mmCP_RINGID 0xa0d9 +#define mmCP_PIPEID 0xa0d9 +#define mmCP_VMID 0xa0da +#define mmCP_HPD_ROQ_OFFSETS 0x3240 +#define mmCP_HPD_EOP_BASE_ADDR 0x3241 +#define mmCP_HPD_EOP_BASE_ADDR_HI 0x3242 +#define mmCP_HPD_EOP_VMID 0x3243 +#define mmCP_HPD_EOP_CONTROL 0x3244 +#define mmCP_MQD_BASE_ADDR 0x3245 +#define mmCP_MQD_BASE_ADDR_HI 0x3246 +#define mmCP_HQD_ACTIVE 0x3247 +#define mmCP_HQD_VMID 0x3248 +#define mmCP_HQD_PERSISTENT_STATE 0x3249 +#define mmCP_HQD_PIPE_PRIORITY 0x324a +#define mmCP_HQD_QUEUE_PRIORITY 0x324b +#define mmCP_HQD_QUANTUM 0x324c +#define mmCP_HQD_PQ_BASE 0x324d +#define mmCP_HQD_PQ_BASE_HI 0x324e +#define mmCP_HQD_PQ_RPTR 0x324f +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 +#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 +#define mmCP_HQD_PQ_WPTR 0x3255 +#define mmCP_HQD_PQ_CONTROL 0x3256 +#define mmCP_HQD_IB_BASE_ADDR 0x3257 +#define mmCP_HQD_IB_BASE_ADDR_HI 0x3258 +#define mmCP_HQD_IB_RPTR 0x3259 +#define mmCP_HQD_IB_CONTROL 0x325a +#define mmCP_HQD_IQ_TIMER 0x325b +#define mmCP_HQD_IQ_RPTR 0x325c +#define mmCP_HQD_DEQUEUE_REQUEST 0x325d +#define mmCP_HQD_DMA_OFFLOAD 0x325e +#define mmCP_HQD_SEMA_CMD 0x325f +#define mmCP_HQD_MSG_TYPE 0x3260 +#define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261 +#define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262 +#define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263 +#define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264 +#define mmCP_HQD_HQ_SCHEDULER0 0x3265 +#define mmCP_HQD_HQ_SCHEDULER1 0x3266 +#define mmCP_MQD_CONTROL 0x3267 +#define mmDB_Z_READ_BASE 0xa012 +#define mmDB_STENCIL_READ_BASE 0xa013 +#define mmDB_Z_WRITE_BASE 0xa014 +#define mmDB_STENCIL_WRITE_BASE 0xa015 +#define mmDB_DEPTH_INFO 0xa00f +#define mmDB_Z_INFO 0xa010 +#define mmDB_STENCIL_INFO 0xa011 +#define mmDB_DEPTH_SIZE 0xa016 +#define mmDB_DEPTH_SLICE 0xa017 +#define mmDB_DEPTH_VIEW 0xa002 +#define mmDB_RENDER_CONTROL 0xa000 +#define mmDB_COUNT_CONTROL 0xa001 +#define mmDB_RENDER_OVERRIDE 0xa003 +#define mmDB_RENDER_OVERRIDE2 0xa004 +#define mmDB_EQAA 0xa201 +#define mmDB_SHADER_CONTROL 0xa203 +#define mmDB_DEPTH_BOUNDS_MIN 0xa008 +#define mmDB_DEPTH_BOUNDS_MAX 0xa009 +#define mmDB_STENCIL_CLEAR 0xa00a +#define mmDB_DEPTH_CLEAR 0xa00b +#define mmDB_HTILE_DATA_BASE 0xa005 +#define mmDB_HTILE_SURFACE 0xa2af +#define mmDB_PRELOAD_CONTROL 0xa2b2 +#define mmDB_STENCILREFMASK 0xa10c +#define mmDB_STENCILREFMASK_BF 0xa10d +#define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0 +#define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1 +#define mmDB_DEPTH_CONTROL 0xa200 +#define mmDB_STENCIL_CONTROL 0xa10b +#define mmDB_ALPHA_TO_MASK 0xa2dc +#define mmDB_PERFCOUNTER0_SELECT 0xdc40 +#define mmDB_PERFCOUNTER1_SELECT 0xdc42 +#define mmDB_PERFCOUNTER2_SELECT 0xdc44 +#define mmDB_PERFCOUNTER3_SELECT 0xdc46 +#define mmDB_PERFCOUNTER0_SELECT1 0xdc41 +#define mmDB_PERFCOUNTER1_SELECT1 0xdc43 +#define mmDB_PERFCOUNTER0_LO 0xd440 +#define mmDB_PERFCOUNTER1_LO 0xd442 +#define mmDB_PERFCOUNTER2_LO 0xd444 +#define mmDB_PERFCOUNTER3_LO 0xd446 +#define mmDB_PERFCOUNTER0_HI 0xd441 +#define mmDB_PERFCOUNTER1_HI 0xd443 +#define mmDB_PERFCOUNTER2_HI 0xd445 +#define mmDB_PERFCOUNTER3_HI 0xd447 +#define mmDB_DEBUG 0x260c +#define mmDB_DEBUG2 0x260d +#define mmDB_DEBUG3 0x260e +#define mmDB_DEBUG4 0x260f +#define mmDB_CREDIT_LIMIT 0x2614 +#define mmDB_WATERMARKS 0x2615 +#define mmDB_SUBTILE_CONTROL 0x2616 +#define mmDB_FREE_CACHELINES 0x2617 +#define mmDB_FIFO_DEPTH1 0x2618 +#define mmDB_FIFO_DEPTH2 0x2619 +#define mmDB_CGTT_CLK_CTRL_0 0xf0a4 +#define mmDB_ZPASS_COUNT_LOW 0xc3fe +#define mmDB_ZPASS_COUNT_HI 0xc3ff +#define mmDB_RING_CONTROL 0x261b +#define mmDB_READ_DEBUG_0 0x2620 +#define mmDB_READ_DEBUG_1 0x2621 +#define mmDB_READ_DEBUG_2 0x2622 +#define mmDB_READ_DEBUG_3 0x2623 +#define mmDB_READ_DEBUG_4 0x2624 +#define mmDB_READ_DEBUG_5 0x2625 +#define mmDB_READ_DEBUG_6 0x2626 +#define mmDB_READ_DEBUG_7 0x2627 +#define mmDB_READ_DEBUG_8 0x2628 +#define mmDB_READ_DEBUG_9 0x2629 +#define mmDB_READ_DEBUG_A 0x262a +#define mmDB_READ_DEBUG_B 0x262b +#define mmDB_READ_DEBUG_C 0x262c +#define mmDB_READ_DEBUG_D 0x262d +#define mmDB_READ_DEBUG_E 0x262e +#define mmDB_READ_DEBUG_F 0x262f +#define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0 +#define mmDB_OCCLUSION_COUNT0_HI 0xc3c1 +#define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2 +#define mmDB_OCCLUSION_COUNT1_HI 0xc3c3 +#define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4 +#define mmDB_OCCLUSION_COUNT2_HI 0xc3c5 +#define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6 +#define mmDB_OCCLUSION_COUNT3_HI 0xc3c7 +#define mmCC_RB_REDUNDANCY 0x263c +#define mmCC_RB_BACKEND_DISABLE 0x263d +#define mmGC_USER_RB_REDUNDANCY 0x26de +#define mmGC_USER_RB_BACKEND_DISABLE 0x26df +#define mmGB_ADDR_CONFIG 0x263e +#define mmGB_BACKEND_MAP 0x263f +#define mmGB_GPU_ID 0x2640 +#define mmCC_RB_DAISY_CHAIN 0x2641 +#define mmGB_TILE_MODE0 0x2644 +#define mmGB_TILE_MODE1 0x2645 +#define mmGB_TILE_MODE2 0x2646 +#define mmGB_TILE_MODE3 0x2647 +#define mmGB_TILE_MODE4 0x2648 +#define mmGB_TILE_MODE5 0x2649 +#define mmGB_TILE_MODE6 0x264a +#define mmGB_TILE_MODE7 0x264b +#define mmGB_TILE_MODE8 0x264c +#define mmGB_TILE_MODE9 0x264d +#define mmGB_TILE_MODE10 0x264e +#define mmGB_TILE_MODE11 0x264f +#define mmGB_TILE_MODE12 0x2650 +#define mmGB_TILE_MODE13 0x2651 +#define mmGB_TILE_MODE14 0x2652 +#define mmGB_TILE_MODE15 0x2653 +#define mmGB_TILE_MODE16 0x2654 +#define mmGB_TILE_MODE17 0x2655 +#define mmGB_TILE_MODE18 0x2656 +#define mmGB_TILE_MODE19 0x2657 +#define mmGB_TILE_MODE20 0x2658 +#define mmGB_TILE_MODE21 0x2659 +#define mmGB_TILE_MODE22 0x265a +#define mmGB_TILE_MODE23 0x265b +#define mmGB_TILE_MODE24 0x265c +#define mmGB_TILE_MODE25 0x265d +#define mmGB_TILE_MODE26 0x265e +#define mmGB_TILE_MODE27 0x265f +#define mmGB_TILE_MODE28 0x2660 +#define mmGB_TILE_MODE29 0x2661 +#define mmGB_TILE_MODE30 0x2662 +#define mmGB_TILE_MODE31 0x2663 +#define mmGB_MACROTILE_MODE0 0x2664 +#define mmGB_MACROTILE_MODE1 0x2665 +#define mmGB_MACROTILE_MODE2 0x2666 +#define mmGB_MACROTILE_MODE3 0x2667 +#define mmGB_MACROTILE_MODE4 0x2668 +#define mmGB_MACROTILE_MODE5 0x2669 +#define mmGB_MACROTILE_MODE6 0x266a +#define mmGB_MACROTILE_MODE7 0x266b +#define mmGB_MACROTILE_MODE8 0x266c +#define mmGB_MACROTILE_MODE9 0x266d +#define mmGB_MACROTILE_MODE10 0x266e +#define mmGB_MACROTILE_MODE11 0x266f +#define mmGB_MACROTILE_MODE12 0x2670 +#define mmGB_MACROTILE_MODE13 0x2671 +#define mmGB_MACROTILE_MODE14 0x2672 +#define mmGB_MACROTILE_MODE15 0x2673 +#define mmGB_EDC_MODE 0x307e +#define mmCC_GC_EDC_CONFIG 0x3098 +#define mmRAS_SIGNATURE_CONTROL 0x3380 +#define mmRAS_SIGNATURE_MASK 0x3381 +#define mmRAS_SX_SIGNATURE0 0x3382 +#define mmRAS_SX_SIGNATURE1 0x3383 +#define mmRAS_SX_SIGNATURE2 0x3384 +#define mmRAS_SX_SIGNATURE3 0x3385 +#define mmRAS_DB_SIGNATURE0 0x338b +#define mmRAS_PA_SIGNATURE0 0x338c +#define mmRAS_VGT_SIGNATURE0 0x338d +#define mmRAS_SQ_SIGNATURE0 0x338e +#define mmRAS_SC_SIGNATURE0 0x338f +#define mmRAS_SC_SIGNATURE1 0x3390 +#define mmRAS_SC_SIGNATURE2 0x3391 +#define mmRAS_SC_SIGNATURE3 0x3392 +#define mmRAS_SC_SIGNATURE4 0x3393 +#define mmRAS_SC_SIGNATURE5 0x3394 +#define mmRAS_SC_SIGNATURE6 0x3395 +#define mmRAS_SC_SIGNATURE7 0x3396 +#define mmRAS_IA_SIGNATURE0 0x3397 +#define mmRAS_IA_SIGNATURE1 0x3398 +#define mmRAS_SPI_SIGNATURE0 0x3399 +#define mmRAS_SPI_SIGNATURE1 0x339a +#define mmRAS_TA_SIGNATURE0 0x339b +#define mmRAS_TD_SIGNATURE0 0x339c +#define mmRAS_CB_SIGNATURE0 0x339d +#define mmRAS_BCI_SIGNATURE0 0x339e +#define mmRAS_BCI_SIGNATURE1 0x339f +#define mmGRBM_CAM_INDEX 0x3000 +#define mmGRBM_CAM_DATA 0x3001 +#define mmGRBM_CNTL 0x2000 +#define mmGRBM_SKEW_CNTL 0x2001 +#define mmGRBM_PWR_CNTL 0x2003 +#define mmGRBM_STATUS 0x2004 +#define mmGRBM_STATUS2 0x2002 +#define mmGRBM_STATUS_SE0 0x2005 +#define mmGRBM_STATUS_SE1 0x2006 +#define mmGRBM_STATUS_SE2 0x200e +#define mmGRBM_STATUS_SE3 0x200f +#define mmGRBM_SOFT_RESET 0x2008 +#define mmGRBM_DEBUG_CNTL 0x2009 +#define mmGRBM_DEBUG_DATA 0x200a +#define mmGRBM_GFX_INDEX 0xc200 +#define mmGRBM_GFX_CLKEN_CNTL 0x200c +#define mmGRBM_WAIT_IDLE_CLOCKS 0x200d +#define mmGRBM_DEBUG 0x2014 +#define mmGRBM_DEBUG_SNAPSHOT 0x2015 +#define mmGRBM_READ_ERROR 0x2016 +#define mmGRBM_READ_ERROR2 0x2017 +#define mmGRBM_INT_CNTL 0x2018 +#define mmGRBM_PERFCOUNTER0_SELECT 0xd840 +#define mmGRBM_PERFCOUNTER1_SELECT 0xd841 +#define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842 +#define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843 +#define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844 +#define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845 +#define mmGRBM_PERFCOUNTER0_LO 0xd040 +#define mmGRBM_PERFCOUNTER0_HI 0xd041 +#define mmGRBM_PERFCOUNTER1_LO 0xd043 +#define mmGRBM_PERFCOUNTER1_HI 0xd044 +#define mmGRBM_SE0_PERFCOUNTER_LO 0xd045 +#define mmGRBM_SE0_PERFCOUNTER_HI 0xd046 +#define mmGRBM_SE1_PERFCOUNTER_LO 0xd047 +#define mmGRBM_SE1_PERFCOUNTER_HI 0xd048 +#define mmGRBM_SE2_PERFCOUNTER_LO 0xd049 +#define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a +#define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b +#define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c +#define mmGRBM_SCRATCH_REG0 0x2040 +#define mmGRBM_SCRATCH_REG1 0x2041 +#define mmGRBM_SCRATCH_REG2 0x2042 +#define mmGRBM_SCRATCH_REG3 0x2043 +#define mmGRBM_SCRATCH_REG4 0x2044 +#define mmGRBM_SCRATCH_REG5 0x2045 +#define mmGRBM_SCRATCH_REG6 0x2046 +#define mmGRBM_SCRATCH_REG7 0x2047 +#define mmDEBUG_INDEX 0x203c +#define mmDEBUG_DATA 0x203d +#define mmGRBM_NOWHERE 0x203f +#define mmPA_CL_VPORT_XSCALE 0xa10f +#define mmPA_CL_VPORT_XOFFSET 0xa110 +#define mmPA_CL_VPORT_YSCALE 0xa111 +#define mmPA_CL_VPORT_YOFFSET 0xa112 +#define mmPA_CL_VPORT_ZSCALE 0xa113 +#define mmPA_CL_VPORT_ZOFFSET 0xa114 +#define mmPA_CL_VPORT_XSCALE_1 0xa115 +#define mmPA_CL_VPORT_XSCALE_2 0xa11b +#define mmPA_CL_VPORT_XSCALE_3 0xa121 +#define mmPA_CL_VPORT_XSCALE_4 0xa127 +#define mmPA_CL_VPORT_XSCALE_5 0xa12d +#define mmPA_CL_VPORT_XSCALE_6 0xa133 +#define mmPA_CL_VPORT_XSCALE_7 0xa139 +#define mmPA_CL_VPORT_XSCALE_8 0xa13f +#define mmPA_CL_VPORT_XSCALE_9 0xa145 +#define mmPA_CL_VPORT_XSCALE_10 0xa14b +#define mmPA_CL_VPORT_XSCALE_11 0xa151 +#define mmPA_CL_VPORT_XSCALE_12 0xa157 +#define mmPA_CL_VPORT_XSCALE_13 0xa15d +#define mmPA_CL_VPORT_XSCALE_14 0xa163 +#define mmPA_CL_VPORT_XSCALE_15 0xa169 +#define mmPA_CL_VPORT_XOFFSET_1 0xa116 +#define mmPA_CL_VPORT_XOFFSET_2 0xa11c +#define mmPA_CL_VPORT_XOFFSET_3 0xa122 +#define mmPA_CL_VPORT_XOFFSET_4 0xa128 +#define mmPA_CL_VPORT_XOFFSET_5 0xa12e +#define mmPA_CL_VPORT_XOFFSET_6 0xa134 +#define mmPA_CL_VPORT_XOFFSET_7 0xa13a +#define mmPA_CL_VPORT_XOFFSET_8 0xa140 +#define mmPA_CL_VPORT_XOFFSET_9 0xa146 +#define mmPA_CL_VPORT_XOFFSET_10 0xa14c +#define mmPA_CL_VPORT_XOFFSET_11 0xa152 +#define mmPA_CL_VPORT_XOFFSET_12 0xa158 +#define mmPA_CL_VPORT_XOFFSET_13 0xa15e +#define mmPA_CL_VPORT_XOFFSET_14 0xa164 +#define mmPA_CL_VPORT_XOFFSET_15 0xa16a +#define mmPA_CL_VPORT_YSCALE_1 0xa117 +#define mmPA_CL_VPORT_YSCALE_2 0xa11d +#define mmPA_CL_VPORT_YSCALE_3 0xa123 +#define mmPA_CL_VPORT_YSCALE_4 0xa129 +#define mmPA_CL_VPORT_YSCALE_5 0xa12f +#define mmPA_CL_VPORT_YSCALE_6 0xa135 +#define mmPA_CL_VPORT_YSCALE_7 0xa13b +#define mmPA_CL_VPORT_YSCALE_8 0xa141 +#define mmPA_CL_VPORT_YSCALE_9 0xa147 +#define mmPA_CL_VPORT_YSCALE_10 0xa14d +#define mmPA_CL_VPORT_YSCALE_11 0xa153 +#define mmPA_CL_VPORT_YSCALE_12 0xa159 +#define mmPA_CL_VPORT_YSCALE_13 0xa15f +#define mmPA_CL_VPORT_YSCALE_14 0xa165 +#define mmPA_CL_VPORT_YSCALE_15 0xa16b +#define mmPA_CL_VPORT_YOFFSET_1 0xa118 +#define mmPA_CL_VPORT_YOFFSET_2 0xa11e +#define mmPA_CL_VPORT_YOFFSET_3 0xa124 +#define mmPA_CL_VPORT_YOFFSET_4 0xa12a +#define mmPA_CL_VPORT_YOFFSET_5 0xa130 +#define mmPA_CL_VPORT_YOFFSET_6 0xa136 +#define mmPA_CL_VPORT_YOFFSET_7 0xa13c +#define mmPA_CL_VPORT_YOFFSET_8 0xa142 +#define mmPA_CL_VPORT_YOFFSET_9 0xa148 +#define mmPA_CL_VPORT_YOFFSET_10 0xa14e +#define mmPA_CL_VPORT_YOFFSET_11 0xa154 +#define mmPA_CL_VPORT_YOFFSET_12 0xa15a +#define mmPA_CL_VPORT_YOFFSET_13 0xa160 +#define mmPA_CL_VPORT_YOFFSET_14 0xa166 +#define mmPA_CL_VPORT_YOFFSET_15 0xa16c +#define mmPA_CL_VPORT_ZSCALE_1 0xa119 +#define mmPA_CL_VPORT_ZSCALE_2 0xa11f +#define mmPA_CL_VPORT_ZSCALE_3 0xa125 +#define mmPA_CL_VPORT_ZSCALE_4 0xa12b +#define mmPA_CL_VPORT_ZSCALE_5 0xa131 +#define mmPA_CL_VPORT_ZSCALE_6 0xa137 +#define mmPA_CL_VPORT_ZSCALE_7 0xa13d +#define mmPA_CL_VPORT_ZSCALE_8 0xa143 +#define mmPA_CL_VPORT_ZSCALE_9 0xa149 +#define mmPA_CL_VPORT_ZSCALE_10 0xa14f +#define mmPA_CL_VPORT_ZSCALE_11 0xa155 +#define mmPA_CL_VPORT_ZSCALE_12 0xa15b +#define mmPA_CL_VPORT_ZSCALE_13 0xa161 +#define mmPA_CL_VPORT_ZSCALE_14 0xa167 +#define mmPA_CL_VPORT_ZSCALE_15 0xa16d +#define mmPA_CL_VPORT_ZOFFSET_1 0xa11a +#define mmPA_CL_VPORT_ZOFFSET_2 0xa120 +#define mmPA_CL_VPORT_ZOFFSET_3 0xa126 +#define mmPA_CL_VPORT_ZOFFSET_4 0xa12c +#define mmPA_CL_VPORT_ZOFFSET_5 0xa132 +#define mmPA_CL_VPORT_ZOFFSET_6 0xa138 +#define mmPA_CL_VPORT_ZOFFSET_7 0xa13e +#define mmPA_CL_VPORT_ZOFFSET_8 0xa144 +#define mmPA_CL_VPORT_ZOFFSET_9 0xa14a +#define mmPA_CL_VPORT_ZOFFSET_10 0xa150 +#define mmPA_CL_VPORT_ZOFFSET_11 0xa156 +#define mmPA_CL_VPORT_ZOFFSET_12 0xa15c +#define mmPA_CL_VPORT_ZOFFSET_13 0xa162 +#define mmPA_CL_VPORT_ZOFFSET_14 0xa168 +#define mmPA_CL_VPORT_ZOFFSET_15 0xa16e +#define mmPA_CL_VTE_CNTL 0xa206 +#define mmPA_CL_VS_OUT_CNTL 0xa207 +#define mmPA_CL_NANINF_CNTL 0xa208 +#define mmPA_CL_CLIP_CNTL 0xa204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa +#define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc +#define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd +#define mmPA_CL_UCP_0_X 0xa16f +#define mmPA_CL_UCP_0_Y 0xa170 +#define mmPA_CL_UCP_0_Z 0xa171 +#define mmPA_CL_UCP_0_W 0xa172 +#define mmPA_CL_UCP_1_X 0xa173 +#define mmPA_CL_UCP_1_Y 0xa174 +#define mmPA_CL_UCP_1_Z 0xa175 +#define mmPA_CL_UCP_1_W 0xa176 +#define mmPA_CL_UCP_2_X 0xa177 +#define mmPA_CL_UCP_2_Y 0xa178 +#define mmPA_CL_UCP_2_Z 0xa179 +#define mmPA_CL_UCP_2_W 0xa17a +#define mmPA_CL_UCP_3_X 0xa17b +#define mmPA_CL_UCP_3_Y 0xa17c +#define mmPA_CL_UCP_3_Z 0xa17d +#define mmPA_CL_UCP_3_W 0xa17e +#define mmPA_CL_UCP_4_X 0xa17f +#define mmPA_CL_UCP_4_Y 0xa180 +#define mmPA_CL_UCP_4_Z 0xa181 +#define mmPA_CL_UCP_4_W 0xa182 +#define mmPA_CL_UCP_5_X 0xa183 +#define mmPA_CL_UCP_5_Y 0xa184 +#define mmPA_CL_UCP_5_Z 0xa185 +#define mmPA_CL_UCP_5_W 0xa186 +#define mmPA_CL_POINT_X_RAD 0xa1f5 +#define mmPA_CL_POINT_Y_RAD 0xa1f6 +#define mmPA_CL_POINT_SIZE 0xa1f7 +#define mmPA_CL_POINT_CULL_RAD 0xa1f8 +#define mmPA_CL_ENHANCE 0x2285 +#define mmPA_CL_RESET_DEBUG 0x2286 +#define mmPA_SU_VTX_CNTL 0xa2f9 +#define mmPA_SU_POINT_SIZE 0xa280 +#define mmPA_SU_POINT_MINMAX 0xa281 +#define mmPA_SU_LINE_CNTL 0xa282 +#define mmPA_SU_LINE_STIPPLE_CNTL 0xa209 +#define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a +#define mmPA_SU_PRIM_FILTER_CNTL 0xa20b +#define mmPA_SU_SC_MODE_CNTL 0xa205 +#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de +#define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3 +#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d +#define mmPA_SU_LINE_STIPPLE_VALUE 0xc280 +#define mmPA_SU_PERFCOUNTER0_SELECT 0xd900 +#define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901 +#define mmPA_SU_PERFCOUNTER1_SELECT 0xd902 +#define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903 +#define mmPA_SU_PERFCOUNTER2_SELECT 0xd904 +#define mmPA_SU_PERFCOUNTER3_SELECT 0xd905 +#define mmPA_SU_PERFCOUNTER0_LO 0xd100 +#define mmPA_SU_PERFCOUNTER0_HI 0xd101 +#define mmPA_SU_PERFCOUNTER1_LO 0xd102 +#define mmPA_SU_PERFCOUNTER1_HI 0xd103 +#define mmPA_SU_PERFCOUNTER2_LO 0xd104 +#define mmPA_SU_PERFCOUNTER2_HI 0xd105 +#define mmPA_SU_PERFCOUNTER3_LO 0xd106 +#define mmPA_SU_PERFCOUNTER3_HI 0xd107 +#define mmPA_SC_AA_CONFIG 0xa2f8 +#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e +#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d +#define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5 +#define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6 +#define mmPA_SC_CLIPRECT_0_TL 0xa084 +#define mmPA_SC_CLIPRECT_0_BR 0xa085 +#define mmPA_SC_CLIPRECT_1_TL 0xa086 +#define mmPA_SC_CLIPRECT_1_BR 0xa087 +#define mmPA_SC_CLIPRECT_2_TL 0xa088 +#define mmPA_SC_CLIPRECT_2_BR 0xa089 +#define mmPA_SC_CLIPRECT_3_TL 0xa08a +#define mmPA_SC_CLIPRECT_3_BR 0xa08b +#define mmPA_SC_CLIPRECT_RULE 0xa083 +#define mmPA_SC_EDGERULE 0xa08c +#define mmPA_SC_LINE_CNTL 0xa2f7 +#define mmPA_SC_LINE_STIPPLE 0xa283 +#define mmPA_SC_MODE_CNTL_0 0xa292 +#define mmPA_SC_MODE_CNTL_1 0xa293 +#define mmPA_SC_RASTER_CONFIG 0xa0d4 +#define mmPA_SC_RASTER_CONFIG_1 0xa0d5 +#define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6 +#define mmPA_SC_GENERIC_SCISSOR_TL 0xa090 +#define mmPA_SC_GENERIC_SCISSOR_BR 0xa091 +#define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c +#define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d +#define mmPA_SC_WINDOW_OFFSET 0xa080 +#define mmPA_SC_WINDOW_SCISSOR_TL 0xa081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0xa082 +#define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094 +#define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096 +#define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098 +#define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a +#define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c +#define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e +#define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0 +#define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2 +#define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4 +#define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6 +#define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8 +#define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa +#define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac +#define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae +#define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0 +#define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2 +#define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095 +#define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097 +#define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099 +#define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b +#define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d +#define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f +#define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1 +#define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3 +#define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5 +#define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7 +#define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9 +#define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab +#define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad +#define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af +#define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1 +#define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3 +#define mmPA_SC_VPORT_ZMIN_0 0xa0b4 +#define mmPA_SC_VPORT_ZMIN_1 0xa0b6 +#define mmPA_SC_VPORT_ZMIN_2 0xa0b8 +#define mmPA_SC_VPORT_ZMIN_3 0xa0ba +#define mmPA_SC_VPORT_ZMIN_4 0xa0bc +#define mmPA_SC_VPORT_ZMIN_5 0xa0be +#define mmPA_SC_VPORT_ZMIN_6 0xa0c0 +#define mmPA_SC_VPORT_ZMIN_7 0xa0c2 +#define mmPA_SC_VPORT_ZMIN_8 0xa0c4 +#define mmPA_SC_VPORT_ZMIN_9 0xa0c6 +#define mmPA_SC_VPORT_ZMIN_10 0xa0c8 +#define mmPA_SC_VPORT_ZMIN_11 0xa0ca +#define mmPA_SC_VPORT_ZMIN_12 0xa0cc +#define mmPA_SC_VPORT_ZMIN_13 0xa0ce +#define mmPA_SC_VPORT_ZMIN_14 0xa0d0 +#define mmPA_SC_VPORT_ZMIN_15 0xa0d2 +#define mmPA_SC_VPORT_ZMAX_0 0xa0b5 +#define mmPA_SC_VPORT_ZMAX_1 0xa0b7 +#define mmPA_SC_VPORT_ZMAX_2 0xa0b9 +#define mmPA_SC_VPORT_ZMAX_3 0xa0bb +#define mmPA_SC_VPORT_ZMAX_4 0xa0bd +#define mmPA_SC_VPORT_ZMAX_5 0xa0bf +#define mmPA_SC_VPORT_ZMAX_6 0xa0c1 +#define mmPA_SC_VPORT_ZMAX_7 0xa0c3 +#define mmPA_SC_VPORT_ZMAX_8 0xa0c5 +#define mmPA_SC_VPORT_ZMAX_9 0xa0c7 +#define mmPA_SC_VPORT_ZMAX_10 0xa0c9 +#define mmPA_SC_VPORT_ZMAX_11 0xa0cb +#define mmPA_SC_VPORT_ZMAX_12 0xa0cd +#define mmPA_SC_VPORT_ZMAX_13 0xa0cf +#define mmPA_SC_VPORT_ZMAX_14 0xa0d1 +#define mmPA_SC_VPORT_ZMAX_15 0xa0d3 +#define mmPA_SC_ENHANCE 0x22fc +#define mmPA_SC_FIFO_SIZE 0x22f3 +#define mmPA_SC_IF_FIFO_SIZE 0x22f5 +#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9 +#define mmPA_SC_LINE_STIPPLE_STATE 0xc281 +#define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284 +#define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285 +#define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286 +#define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b +#define mmPA_SC_PERFCOUNTER0_SELECT 0xd940 +#define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941 +#define mmPA_SC_PERFCOUNTER1_SELECT 0xd942 +#define mmPA_SC_PERFCOUNTER2_SELECT 0xd943 +#define mmPA_SC_PERFCOUNTER3_SELECT 0xd944 +#define mmPA_SC_PERFCOUNTER4_SELECT 0xd945 +#define mmPA_SC_PERFCOUNTER5_SELECT 0xd946 +#define mmPA_SC_PERFCOUNTER6_SELECT 0xd947 +#define mmPA_SC_PERFCOUNTER7_SELECT 0xd948 +#define mmPA_SC_PERFCOUNTER0_LO 0xd140 +#define mmPA_SC_PERFCOUNTER0_HI 0xd141 +#define mmPA_SC_PERFCOUNTER1_LO 0xd142 +#define mmPA_SC_PERFCOUNTER1_HI 0xd143 +#define mmPA_SC_PERFCOUNTER2_LO 0xd144 +#define mmPA_SC_PERFCOUNTER2_HI 0xd145 +#define mmPA_SC_PERFCOUNTER3_LO 0xd146 +#define mmPA_SC_PERFCOUNTER3_HI 0xd147 +#define mmPA_SC_PERFCOUNTER4_LO 0xd148 +#define mmPA_SC_PERFCOUNTER4_HI 0xd149 +#define mmPA_SC_PERFCOUNTER5_LO 0xd14a +#define mmPA_SC_PERFCOUNTER5_HI 0xd14b +#define mmPA_SC_PERFCOUNTER6_LO 0xd14c +#define mmPA_SC_PERFCOUNTER6_HI 0xd14d +#define mmPA_SC_PERFCOUNTER7_LO 0xd14e +#define mmPA_SC_PERFCOUNTER7_HI 0xd14f +#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0 +#define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1 +#define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2 +#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3 +#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8 +#define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9 +#define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa +#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab +#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac +#define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0 +#define mmPA_SC_TRAP_SCREEN_H 0xc2b1 +#define mmPA_SC_TRAP_SCREEN_V 0xc2b2 +#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3 +#define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4 +#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1 +#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2 +#define mmPA_CL_CNTL_STATUS 0x2284 +#define mmPA_SU_CNTL_STATUS 0x2294 +#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 +#define mmCGTT_PA_CLK_CTRL 0xf088 +#define mmCGTT_SC_CLK_CTRL 0xf089 +#define mmPA_SU_DEBUG_CNTL 0x2280 +#define mmPA_SU_DEBUG_DATA 0x2281 +#define mmPA_SC_DEBUG_CNTL 0x22f6 +#define mmPA_SC_DEBUG_DATA 0x22f7 +#define ixCLIPPER_DEBUG_REG00 0x0 +#define ixCLIPPER_DEBUG_REG01 0x1 +#define ixCLIPPER_DEBUG_REG02 0x2 +#define ixCLIPPER_DEBUG_REG03 0x3 +#define ixCLIPPER_DEBUG_REG04 0x4 +#define ixCLIPPER_DEBUG_REG05 0x5 +#define ixCLIPPER_DEBUG_REG06 0x6 +#define ixCLIPPER_DEBUG_REG07 0x7 +#define ixCLIPPER_DEBUG_REG08 0x8 +#define ixCLIPPER_DEBUG_REG09 0x9 +#define ixCLIPPER_DEBUG_REG10 0xa +#define ixCLIPPER_DEBUG_REG11 0xb +#define ixCLIPPER_DEBUG_REG12 0xc +#define ixCLIPPER_DEBUG_REG13 0xd +#define ixCLIPPER_DEBUG_REG14 0xe +#define ixCLIPPER_DEBUG_REG15 0xf +#define ixCLIPPER_DEBUG_REG16 0x10 +#define ixCLIPPER_DEBUG_REG17 0x11 +#define ixCLIPPER_DEBUG_REG18 0x12 +#define ixCLIPPER_DEBUG_REG19 0x13 +#define ixSXIFCCG_DEBUG_REG0 0x14 +#define ixSXIFCCG_DEBUG_REG1 0x15 +#define ixSXIFCCG_DEBUG_REG2 0x16 +#define ixSXIFCCG_DEBUG_REG3 0x17 +#define ixSETUP_DEBUG_REG0 0x18 +#define ixSETUP_DEBUG_REG1 0x19 +#define ixSETUP_DEBUG_REG2 0x1a +#define ixSETUP_DEBUG_REG3 0x1b +#define ixSETUP_DEBUG_REG4 0x1c +#define ixSETUP_DEBUG_REG5 0x1d +#define ixPA_SC_DEBUG_REG0 0x0 +#define ixPA_SC_DEBUG_REG1 0x1 +#define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00 +#define mmCOMPUTE_DIM_X 0x2e01 +#define mmCOMPUTE_DIM_Y 0x2e02 +#define mmCOMPUTE_DIM_Z 0x2e03 +#define mmCOMPUTE_START_X 0x2e04 +#define mmCOMPUTE_START_Y 0x2e05 +#define mmCOMPUTE_START_Z 0x2e06 +#define mmCOMPUTE_NUM_THREAD_X 0x2e07 +#define mmCOMPUTE_NUM_THREAD_Y 0x2e08 +#define mmCOMPUTE_NUM_THREAD_Z 0x2e09 +#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a +#define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b +#define mmCOMPUTE_PGM_LO 0x2e0c +#define mmCOMPUTE_PGM_HI 0x2e0d +#define mmCOMPUTE_TBA_LO 0x2e0e +#define mmCOMPUTE_TBA_HI 0x2e0f +#define mmCOMPUTE_TMA_LO 0x2e10 +#define mmCOMPUTE_TMA_HI 0x2e11 +#define mmCOMPUTE_PGM_RSRC1 0x2e12 +#define mmCOMPUTE_PGM_RSRC2 0x2e13 +#define mmCOMPUTE_VMID 0x2e14 +#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17 +#define mmCOMPUTE_TMPRING_SIZE 0x2e18 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a +#define mmCOMPUTE_RESTART_X 0x2e1b +#define mmCOMPUTE_RESTART_Y 0x2e1c +#define mmCOMPUTE_RESTART_Z 0x2e1d +#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e +#define mmCOMPUTE_MISC_RESERVED 0x2e1f +#define mmCOMPUTE_USER_DATA_0 0x2e40 +#define mmCOMPUTE_USER_DATA_1 0x2e41 +#define mmCOMPUTE_USER_DATA_2 0x2e42 +#define mmCOMPUTE_USER_DATA_3 0x2e43 +#define mmCOMPUTE_USER_DATA_4 0x2e44 +#define mmCOMPUTE_USER_DATA_5 0x2e45 +#define mmCOMPUTE_USER_DATA_6 0x2e46 +#define mmCOMPUTE_USER_DATA_7 0x2e47 +#define mmCOMPUTE_USER_DATA_8 0x2e48 +#define mmCOMPUTE_USER_DATA_9 0x2e49 +#define mmCOMPUTE_USER_DATA_10 0x2e4a +#define mmCOMPUTE_USER_DATA_11 0x2e4b +#define mmCOMPUTE_USER_DATA_12 0x2e4c +#define mmCOMPUTE_USER_DATA_13 0x2e4d +#define mmCOMPUTE_USER_DATA_14 0x2e4e +#define mmCOMPUTE_USER_DATA_15 0x2e4f +#define mmCSPRIV_CONNECT 0x0 +#define mmCSPRIV_THREAD_TRACE_TG0 0x1e +#define mmCSPRIV_THREAD_TRACE_TG1 0x1e +#define mmCSPRIV_THREAD_TRACE_TG2 0x1e +#define mmCSPRIV_THREAD_TRACE_TG3 0x1e +#define mmCSPRIV_THREAD_TRACE_EVENT 0x1f +#define mmRLC_CNTL 0x30c0 +#define mmRLC_DEBUG_SELECT 0x30c1 +#define mmRLC_DEBUG 0x30c2 +#define mmRLC_MC_CNTL 0x30c3 +#define mmRLC_STAT 0x30c4 +#define mmRLC_SAFE_MODE 0x313a +#define mmRLC_SOFT_RESET_GPU 0x30c5 +#define mmRLC_MEM_SLP_CNTL 0x30c6 +#define mmRLC_PERFMON_CNTL 0xdcc0 +#define mmRLC_PERFCOUNTER0_SELECT 0xdcc1 +#define mmRLC_PERFCOUNTER1_SELECT 0xdcc2 +#define mmRLC_PERFCOUNTER0_LO 0xd480 +#define mmRLC_PERFCOUNTER1_LO 0xd482 +#define mmRLC_PERFCOUNTER0_HI 0xd481 +#define mmRLC_PERFCOUNTER1_HI 0xd483 +#define mmCGTT_RLC_CLK_CTRL 0xf0b8 +#define mmRLC_LB_CNTL 0x30d9 +#define mmRLC_LB_CNTR_MAX 0x30d2 +#define mmRLC_LB_CNTR_INIT 0x30db +#define mmRLC_LOAD_BALANCE_CNTR 0x30dc +#define mmRLC_SAVE_AND_RESTORE_BASE 0x30dd +#define mmRLC_JUMP_TABLE_RESTORE 0x30de +#define mmRLC_DRIVER_CPDMA_STATUS 0x30de +#define mmRLC_PG_DELAY_2 0x30df +#define mmRLC_GPM_DEBUG_SELECT 0x30e0 +#define mmRLC_GPM_DEBUG 0x30e1 +#define mmRLC_GPM_UCODE_ADDR 0x30e2 +#define mmRLC_GPM_UCODE_DATA 0x30e3 +#define mmRLC_GPU_CLOCK_COUNT_LSB 0x30e4 +#define mmRLC_GPU_CLOCK_COUNT_MSB 0x30e5 +#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30e6 +#define mmRLC_UCODE_CNTL 0x30e7 +#define mmRLC_GPM_STAT 0x3100 +#define mmRLC_GPU_CLOCK_32_RES_SEL 0x3101 +#define mmRLC_GPU_CLOCK_32 0x3102 +#define mmRLC_PG_CNTL 0x3103 +#define mmRLC_GPM_THREAD_PRIORITY 0x3104 +#define mmRLC_GPM_THREAD_ENABLE 0x3105 +#define mmRLC_GPM_VMID_THREAD0 0x3106 +#define mmRLC_GPM_VMID_THREAD1 0x3107 +#define mmRLC_CGTT_MGCG_OVERRIDE 0x3108 +#define mmRLC_CGCG_CGLS_CTRL 0x3109 +#define mmRLC_CGCG_RAMP_CTRL 0x310a +#define mmRLC_DYN_PG_STATUS 0x310b +#define mmRLC_DYN_PG_REQUEST 0x310c +#define mmRLC_PG_DELAY 0x310d +#define mmRLC_CU_STATUS 0x310e +#define mmRLC_LB_INIT_CU_MASK 0x310f +#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3110 +#define mmRLC_LB_PARAMS 0x3111 +#define mmRLC_THREAD1_DELAY 0x3112 +#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x3113 +#define mmRLC_MAX_PG_CU 0x3114 +#define mmRLC_AUTO_PG_CTRL 0x3115 +#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x3116 +#define mmRLC_SMU_PG_CTRL 0x3117 +#define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3118 +#define mmRLC_SERDES_RD_MASTER_INDEX 0x3119 +#define mmRLC_SERDES_RD_DATA_0 0x311a +#define mmRLC_SERDES_RD_DATA_1 0x311b +#define mmRLC_SERDES_RD_DATA_2 0x311c +#define mmRLC_SERDES_WR_CU_MASTER_MASK 0x311d +#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x311e +#define mmRLC_SERDES_WR_CTRL 0x311f +#define mmRLC_SERDES_WR_DATA 0x3120 +#define mmRLC_SERDES_CU_MASTER_BUSY 0x3121 +#define mmRLC_SERDES_NONCU_MASTER_BUSY 0x3122 +#define mmRLC_GPM_GENERAL_0 0x3123 +#define mmRLC_GPM_GENERAL_1 0x3124 +#define mmRLC_GPM_GENERAL_2 0x3125 +#define mmRLC_GPM_GENERAL_3 0x3126 +#define mmRLC_GPM_GENERAL_4 0x3127 +#define mmRLC_GPM_GENERAL_5 0x3128 +#define mmRLC_GPM_GENERAL_6 0x3129 +#define mmRLC_GPM_GENERAL_7 0x312a +#define mmRLC_GPM_CU_PD_TIMEOUT 0x312b +#define mmRLC_GPM_SCRATCH_ADDR 0x312c +#define mmRLC_GPM_SCRATCH_DATA 0x312d +#define mmRLC_STATIC_PG_STATUS 0x312e +#define mmRLC_GPM_PERF_COUNT_0 0x312f +#define mmRLC_GPM_PERF_COUNT_1 0x3130 +#define mmRLC_GPR_REG1 0x3139 +#define mmRLC_GPR_REG2 0x313a +#define mmRLC_SPM_VMID 0x3131 +#define mmRLC_SPM_INT_CNTL 0x3132 +#define mmRLC_SPM_INT_STATUS 0x3133 +#define mmRLC_SPM_DEBUG_SELECT 0x3134 +#define mmRLC_SPM_DEBUG 0x3135 +#define mmRLC_GPM_LOG_ADDR 0x3136 +#define mmRLC_GPM_LOG_SIZE 0x3137 +#define mmRLC_GPM_LOG_CONT 0x3138 +#define mmRLC_SPM_PERFMON_CNTL 0xdc80 +#define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81 +#define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82 +#define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83 +#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84 +#define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85 +#define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86 +#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87 +#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88 +#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89 +#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a +#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b +#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c +#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d +#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e +#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90 +#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91 +#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92 +#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93 +#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94 +#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95 +#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96 +#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97 +#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98 +#define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY 0xdc99 +#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a +#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b +#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c +#define mmRLC_SPM_RING_RDPTR 0xdc9d +#define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e +#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY 0xdc9f +#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY 0xdca0 +#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY 0xdca1 +#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY 0xdca2 +#define mmSPI_PS_INPUT_CNTL_0 0xa191 +#define mmSPI_PS_INPUT_CNTL_1 0xa192 +#define mmSPI_PS_INPUT_CNTL_2 0xa193 +#define mmSPI_PS_INPUT_CNTL_3 0xa194 +#define mmSPI_PS_INPUT_CNTL_4 0xa195 +#define mmSPI_PS_INPUT_CNTL_5 0xa196 +#define mmSPI_PS_INPUT_CNTL_6 0xa197 +#define mmSPI_PS_INPUT_CNTL_7 0xa198 +#define mmSPI_PS_INPUT_CNTL_8 0xa199 +#define mmSPI_PS_INPUT_CNTL_9 0xa19a +#define mmSPI_PS_INPUT_CNTL_10 0xa19b +#define mmSPI_PS_INPUT_CNTL_11 0xa19c +#define mmSPI_PS_INPUT_CNTL_12 0xa19d +#define mmSPI_PS_INPUT_CNTL_13 0xa19e +#define mmSPI_PS_INPUT_CNTL_14 0xa19f +#define mmSPI_PS_INPUT_CNTL_15 0xa1a0 +#define mmSPI_PS_INPUT_CNTL_16 0xa1a1 +#define mmSPI_PS_INPUT_CNTL_17 0xa1a2 +#define mmSPI_PS_INPUT_CNTL_18 0xa1a3 +#define mmSPI_PS_INPUT_CNTL_19 0xa1a4 +#define mmSPI_PS_INPUT_CNTL_20 0xa1a5 +#define mmSPI_PS_INPUT_CNTL_21 0xa1a6 +#define mmSPI_PS_INPUT_CNTL_22 0xa1a7 +#define mmSPI_PS_INPUT_CNTL_23 0xa1a8 +#define mmSPI_PS_INPUT_CNTL_24 0xa1a9 +#define mmSPI_PS_INPUT_CNTL_25 0xa1aa +#define mmSPI_PS_INPUT_CNTL_26 0xa1ab +#define mmSPI_PS_INPUT_CNTL_27 0xa1ac +#define mmSPI_PS_INPUT_CNTL_28 0xa1ad +#define mmSPI_PS_INPUT_CNTL_29 0xa1ae +#define mmSPI_PS_INPUT_CNTL_30 0xa1af +#define mmSPI_PS_INPUT_CNTL_31 0xa1b0 +#define mmSPI_VS_OUT_CONFIG 0xa1b1 +#define mmSPI_PS_INPUT_ENA 0xa1b3 +#define mmSPI_PS_INPUT_ADDR 0xa1b4 +#define mmSPI_INTERP_CONTROL_0 0xa1b5 +#define mmSPI_PS_IN_CONTROL 0xa1b6 +#define mmSPI_BARYC_CNTL 0xa1b8 +#define mmSPI_TMPRING_SIZE 0xa1ba +#define mmSPI_SHADER_POS_FORMAT 0xa1c3 +#define mmSPI_SHADER_Z_FORMAT 0xa1c4 +#define mmSPI_SHADER_COL_FORMAT 0xa1c5 +#define mmSPI_ARB_PRIORITY 0x31c0 +#define mmSPI_ARB_CYCLES_0 0x31c1 +#define mmSPI_ARB_CYCLES_1 0x31c2 +#define mmSPI_CDBG_SYS_GFX 0x31c3 +#define mmSPI_CDBG_SYS_HP3D 0x31c4 +#define mmSPI_CDBG_SYS_CS0 0x31c5 +#define mmSPI_CDBG_SYS_CS1 0x31c6 +#define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 +#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8 +#define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9 +#define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca +#define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb +#define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc +#define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd +#define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce +#define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf +#define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0 +#define mmSPI_GDBG_WAVE_CNTL 0x31d1 +#define mmSPI_GDBG_TRAP_CONFIG 0x31d2 +#define mmSPI_GDBG_TRAP_MASK 0x31d3 +#define mmSPI_GDBG_TBA_LO 0x31d4 +#define mmSPI_GDBG_TBA_HI 0x31d5 +#define mmSPI_GDBG_TMA_LO 0x31d6 +#define mmSPI_GDBG_TMA_HI 0x31d7 +#define mmSPI_GDBG_TRAP_DATA0 0x31d8 +#define mmSPI_GDBG_TRAP_DATA1 0x31d9 +#define mmSPI_RESET_DEBUG 0x31da +#define mmSPI_COMPUTE_QUEUE_RESET 0x31db +#define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc +#define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd +#define mmSPI_RESOURCE_RESERVE_CU_2 0x31de +#define mmSPI_RESOURCE_RESERVE_CU_3 0x31df +#define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0 +#define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1 +#define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2 +#define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3 +#define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4 +#define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5 +#define mmSPI_RESOURCE_RESERVE_CU_10 0x31f0 +#define mmSPI_RESOURCE_RESERVE_CU_11 0x31f1 +#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6 +#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7 +#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8 +#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9 +#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea +#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb +#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec +#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed +#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee +#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef +#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x31f2 +#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x31f3 +#define mmSPI_PS_MAX_WAVE_ID 0x243a +#define mmSPI_CONFIG_CNTL 0x2440 +#define mmSPI_DEBUG_CNTL 0x2441 +#define mmSPI_DEBUG_READ 0x2442 +#define mmSPI_PERFCOUNTER0_SELECT 0xd980 +#define mmSPI_PERFCOUNTER1_SELECT 0xd981 +#define mmSPI_PERFCOUNTER2_SELECT 0xd982 +#define mmSPI_PERFCOUNTER3_SELECT 0xd983 +#define mmSPI_PERFCOUNTER0_SELECT1 0xd984 +#define mmSPI_PERFCOUNTER1_SELECT1 0xd985 +#define mmSPI_PERFCOUNTER2_SELECT1 0xd986 +#define mmSPI_PERFCOUNTER3_SELECT1 0xd987 +#define mmSPI_PERFCOUNTER4_SELECT 0xd988 +#define mmSPI_PERFCOUNTER5_SELECT 0xd989 +#define mmSPI_PERFCOUNTER_BINS 0xd98a +#define mmSPI_PERFCOUNTER0_HI 0xd180 +#define mmSPI_PERFCOUNTER0_LO 0xd181 +#define mmSPI_PERFCOUNTER1_HI 0xd182 +#define mmSPI_PERFCOUNTER1_LO 0xd183 +#define mmSPI_PERFCOUNTER2_HI 0xd184 +#define mmSPI_PERFCOUNTER2_LO 0xd185 +#define mmSPI_PERFCOUNTER3_HI 0xd186 +#define mmSPI_PERFCOUNTER3_LO 0xd187 +#define mmSPI_PERFCOUNTER4_HI 0xd188 +#define mmSPI_PERFCOUNTER4_LO 0xd189 +#define mmSPI_PERFCOUNTER5_HI 0xd18a +#define mmSPI_PERFCOUNTER5_LO 0xd18b +#define mmSPI_CONFIG_CNTL_1 0x244f +#define mmSPI_DEBUG_BUSY 0x2450 +#define mmCGTS_SM_CTRL_REG 0xf000 +#define mmCGTS_RD_CTRL_REG 0xf001 +#define mmCGTS_RD_REG 0xf002 +#define mmCGTS_TCC_DISABLE 0xf003 +#define mmCGTS_USER_TCC_DISABLE 0xf004 +#define mmCGTS_CU0_SP0_CTRL_REG 0xf008 +#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009 +#define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a +#define mmCGTS_CU0_SP1_CTRL_REG 0xf00b +#define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c +#define mmCGTS_CU1_SP0_CTRL_REG 0xf00d +#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e +#define mmCGTS_CU1_TA_CTRL_REG 0xf00f +#define mmCGTS_CU1_SP1_CTRL_REG 0xf010 +#define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011 +#define mmCGTS_CU2_SP0_CTRL_REG 0xf012 +#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013 +#define mmCGTS_CU2_TA_CTRL_REG 0xf014 +#define mmCGTS_CU2_SP1_CTRL_REG 0xf015 +#define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016 +#define mmCGTS_CU3_SP0_CTRL_REG 0xf017 +#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018 +#define mmCGTS_CU3_TA_CTRL_REG 0xf019 +#define mmCGTS_CU3_SP1_CTRL_REG 0xf01a +#define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b +#define mmCGTS_CU4_SP0_CTRL_REG 0xf01c +#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d +#define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e +#define mmCGTS_CU4_SP1_CTRL_REG 0xf01f +#define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020 +#define mmCGTS_CU5_SP0_CTRL_REG 0xf021 +#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022 +#define mmCGTS_CU5_TA_CTRL_REG 0xf023 +#define mmCGTS_CU5_SP1_CTRL_REG 0xf024 +#define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025 +#define mmCGTS_CU6_SP0_CTRL_REG 0xf026 +#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027 +#define mmCGTS_CU6_TA_CTRL_REG 0xf028 +#define mmCGTS_CU6_SP1_CTRL_REG 0xf029 +#define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a +#define mmCGTS_CU7_SP0_CTRL_REG 0xf02b +#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c +#define mmCGTS_CU7_TA_CTRL_REG 0xf02d +#define mmCGTS_CU7_SP1_CTRL_REG 0xf02e +#define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f +#define mmCGTS_CU8_SP0_CTRL_REG 0xf030 +#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031 +#define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032 +#define mmCGTS_CU8_SP1_CTRL_REG 0xf033 +#define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034 +#define mmCGTS_CU9_SP0_CTRL_REG 0xf035 +#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036 +#define mmCGTS_CU9_TA_CTRL_REG 0xf037 +#define mmCGTS_CU9_SP1_CTRL_REG 0xf038 +#define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039 +#define mmCGTS_CU10_SP0_CTRL_REG 0xf03a +#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b +#define mmCGTS_CU10_TA_CTRL_REG 0xf03c +#define mmCGTS_CU10_SP1_CTRL_REG 0xf03d +#define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e +#define mmCGTS_CU11_SP0_CTRL_REG 0xf03f +#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040 +#define mmCGTS_CU11_TA_CTRL_REG 0xf041 +#define mmCGTS_CU11_SP1_CTRL_REG 0xf042 +#define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043 +#define mmCGTS_CU12_SP0_CTRL_REG 0xf044 +#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045 +#define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046 +#define mmCGTS_CU12_SP1_CTRL_REG 0xf047 +#define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048 +#define mmCGTS_CU13_SP0_CTRL_REG 0xf049 +#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a +#define mmCGTS_CU13_TA_CTRL_REG 0xf04b +#define mmCGTS_CU13_SP1_CTRL_REG 0xf04c +#define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d +#define mmCGTS_CU14_SP0_CTRL_REG 0xf04e +#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f +#define mmCGTS_CU14_TA_CTRL_REG 0xf050 +#define mmCGTS_CU14_SP1_CTRL_REG 0xf051 +#define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052 +#define mmCGTS_CU15_SP0_CTRL_REG 0xf053 +#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 +#define mmCGTS_CU15_TA_CTRL_REG 0xf055 +#define mmCGTS_CU15_SP1_CTRL_REG 0xf056 +#define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057 +#define mmCGTT_SPI_CLK_CTRL 0xf080 +#define mmCGTT_PC_CLK_CTRL 0xf081 +#define mmCGTT_BCI_CLK_CTRL 0xf082 +#define mmSPI_WF_LIFETIME_CNTL 0x24aa +#define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab +#define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac +#define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad +#define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae +#define mmSPI_WF_LIFETIME_LIMIT_4 0x24af +#define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0 +#define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1 +#define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2 +#define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3 +#define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4 +#define mmSPI_WF_LIFETIME_STATUS_0 0x24b5 +#define mmSPI_WF_LIFETIME_STATUS_1 0x24b6 +#define mmSPI_WF_LIFETIME_STATUS_2 0x24b7 +#define mmSPI_WF_LIFETIME_STATUS_3 0x24b8 +#define mmSPI_WF_LIFETIME_STATUS_4 0x24b9 +#define mmSPI_WF_LIFETIME_STATUS_5 0x24ba +#define mmSPI_WF_LIFETIME_STATUS_6 0x24bb +#define mmSPI_WF_LIFETIME_STATUS_7 0x24bc +#define mmSPI_WF_LIFETIME_STATUS_8 0x24bd +#define mmSPI_WF_LIFETIME_STATUS_9 0x24be +#define mmSPI_WF_LIFETIME_STATUS_10 0x24bf +#define mmSPI_WF_LIFETIME_STATUS_11 0x24c0 +#define mmSPI_WF_LIFETIME_STATUS_12 0x24c1 +#define mmSPI_WF_LIFETIME_STATUS_13 0x24c2 +#define mmSPI_WF_LIFETIME_STATUS_14 0x24c3 +#define mmSPI_WF_LIFETIME_STATUS_15 0x24c4 +#define mmSPI_WF_LIFETIME_STATUS_16 0x24c5 +#define mmSPI_WF_LIFETIME_STATUS_17 0x24c6 +#define mmSPI_WF_LIFETIME_STATUS_18 0x24c7 +#define mmSPI_WF_LIFETIME_STATUS_19 0x24c8 +#define mmSPI_WF_LIFETIME_STATUS_20 0x24c9 +#define mmSPI_WF_LIFETIME_DEBUG 0x24ca +#define mmSPI_SLAVE_DEBUG_BUSY 0x24d3 +#define mmSPI_LB_CTR_CTRL 0x24d4 +#define mmSPI_LB_CU_MASK 0x24d5 +#define mmSPI_LB_DATA_REG 0x24d6 +#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7 +#define mmSPI_GDS_CREDITS 0x24d8 +#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9 +#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da +#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db +#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc +#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd +#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de +#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df +#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3 +#define mmBCI_DEBUG_READ 0x24eb +#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec +#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed +#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee +#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef +#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0 +#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1 +#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2 +#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3 +#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4 +#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5 +#define mmSPI_SHADER_TBA_LO_PS 0x2c00 +#define mmSPI_SHADER_TBA_HI_PS 0x2c01 +#define mmSPI_SHADER_TMA_LO_PS 0x2c02 +#define mmSPI_SHADER_TMA_HI_PS 0x2c03 +#define mmSPI_SHADER_PGM_LO_PS 0x2c08 +#define mmSPI_SHADER_PGM_HI_PS 0x2c09 +#define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a +#define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b +#define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07 +#define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c +#define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d +#define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e +#define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f +#define mmSPI_SHADER_USER_DATA_PS_4 0x2c10 +#define mmSPI_SHADER_USER_DATA_PS_5 0x2c11 +#define mmSPI_SHADER_USER_DATA_PS_6 0x2c12 +#define mmSPI_SHADER_USER_DATA_PS_7 0x2c13 +#define mmSPI_SHADER_USER_DATA_PS_8 0x2c14 +#define mmSPI_SHADER_USER_DATA_PS_9 0x2c15 +#define mmSPI_SHADER_USER_DATA_PS_10 0x2c16 +#define mmSPI_SHADER_USER_DATA_PS_11 0x2c17 +#define mmSPI_SHADER_USER_DATA_PS_12 0x2c18 +#define mmSPI_SHADER_USER_DATA_PS_13 0x2c19 +#define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a +#define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b +#define mmSPI_SHADER_TBA_LO_VS 0x2c40 +#define mmSPI_SHADER_TBA_HI_VS 0x2c41 +#define mmSPI_SHADER_TMA_LO_VS 0x2c42 +#define mmSPI_SHADER_TMA_HI_VS 0x2c43 +#define mmSPI_SHADER_PGM_LO_VS 0x2c48 +#define mmSPI_SHADER_PGM_HI_VS 0x2c49 +#define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a +#define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b +#define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46 +#define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47 +#define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c +#define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d +#define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e +#define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f +#define mmSPI_SHADER_USER_DATA_VS_4 0x2c50 +#define mmSPI_SHADER_USER_DATA_VS_5 0x2c51 +#define mmSPI_SHADER_USER_DATA_VS_6 0x2c52 +#define mmSPI_SHADER_USER_DATA_VS_7 0x2c53 +#define mmSPI_SHADER_USER_DATA_VS_8 0x2c54 +#define mmSPI_SHADER_USER_DATA_VS_9 0x2c55 +#define mmSPI_SHADER_USER_DATA_VS_10 0x2c56 +#define mmSPI_SHADER_USER_DATA_VS_11 0x2c57 +#define mmSPI_SHADER_USER_DATA_VS_12 0x2c58 +#define mmSPI_SHADER_USER_DATA_VS_13 0x2c59 +#define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a +#define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b +#define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c +#define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d +#define mmSPI_SHADER_TBA_LO_GS 0x2c80 +#define mmSPI_SHADER_TBA_HI_GS 0x2c81 +#define mmSPI_SHADER_TMA_LO_GS 0x2c82 +#define mmSPI_SHADER_TMA_HI_GS 0x2c83 +#define mmSPI_SHADER_PGM_LO_GS 0x2c88 +#define mmSPI_SHADER_PGM_HI_GS 0x2c89 +#define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a +#define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b +#define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87 +#define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c +#define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d +#define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e +#define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f +#define mmSPI_SHADER_USER_DATA_GS_4 0x2c90 +#define mmSPI_SHADER_USER_DATA_GS_5 0x2c91 +#define mmSPI_SHADER_USER_DATA_GS_6 0x2c92 +#define mmSPI_SHADER_USER_DATA_GS_7 0x2c93 +#define mmSPI_SHADER_USER_DATA_GS_8 0x2c94 +#define mmSPI_SHADER_USER_DATA_GS_9 0x2c95 +#define mmSPI_SHADER_USER_DATA_GS_10 0x2c96 +#define mmSPI_SHADER_USER_DATA_GS_11 0x2c97 +#define mmSPI_SHADER_USER_DATA_GS_12 0x2c98 +#define mmSPI_SHADER_USER_DATA_GS_13 0x2c99 +#define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a +#define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b +#define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc +#define mmSPI_SHADER_TBA_LO_ES 0x2cc0 +#define mmSPI_SHADER_TBA_HI_ES 0x2cc1 +#define mmSPI_SHADER_TMA_LO_ES 0x2cc2 +#define mmSPI_SHADER_TMA_HI_ES 0x2cc3 +#define mmSPI_SHADER_PGM_LO_ES 0x2cc8 +#define mmSPI_SHADER_PGM_HI_ES 0x2cc9 +#define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca +#define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb +#define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7 +#define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc +#define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd +#define mmSPI_SHADER_USER_DATA_ES_2 0x2cce +#define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf +#define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0 +#define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1 +#define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2 +#define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3 +#define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4 +#define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5 +#define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6 +#define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7 +#define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8 +#define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9 +#define mmSPI_SHADER_USER_DATA_ES_14 0x2cda +#define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb +#define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd +#define mmSPI_SHADER_TBA_LO_HS 0x2d00 +#define mmSPI_SHADER_TBA_HI_HS 0x2d01 +#define mmSPI_SHADER_TMA_LO_HS 0x2d02 +#define mmSPI_SHADER_TMA_HI_HS 0x2d03 +#define mmSPI_SHADER_PGM_LO_HS 0x2d08 +#define mmSPI_SHADER_PGM_HI_HS 0x2d09 +#define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a +#define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b +#define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07 +#define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c +#define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d +#define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e +#define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f +#define mmSPI_SHADER_USER_DATA_HS_4 0x2d10 +#define mmSPI_SHADER_USER_DATA_HS_5 0x2d11 +#define mmSPI_SHADER_USER_DATA_HS_6 0x2d12 +#define mmSPI_SHADER_USER_DATA_HS_7 0x2d13 +#define mmSPI_SHADER_USER_DATA_HS_8 0x2d14 +#define mmSPI_SHADER_USER_DATA_HS_9 0x2d15 +#define mmSPI_SHADER_USER_DATA_HS_10 0x2d16 +#define mmSPI_SHADER_USER_DATA_HS_11 0x2d17 +#define mmSPI_SHADER_USER_DATA_HS_12 0x2d18 +#define mmSPI_SHADER_USER_DATA_HS_13 0x2d19 +#define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a +#define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b +#define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d +#define mmSPI_SHADER_TBA_LO_LS 0x2d40 +#define mmSPI_SHADER_TBA_HI_LS 0x2d41 +#define mmSPI_SHADER_TMA_LO_LS 0x2d42 +#define mmSPI_SHADER_TMA_HI_LS 0x2d43 +#define mmSPI_SHADER_PGM_LO_LS 0x2d48 +#define mmSPI_SHADER_PGM_HI_LS 0x2d49 +#define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a +#define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b +#define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47 +#define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c +#define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d +#define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e +#define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f +#define mmSPI_SHADER_USER_DATA_LS_4 0x2d50 +#define mmSPI_SHADER_USER_DATA_LS_5 0x2d51 +#define mmSPI_SHADER_USER_DATA_LS_6 0x2d52 +#define mmSPI_SHADER_USER_DATA_LS_7 0x2d53 +#define mmSPI_SHADER_USER_DATA_LS_8 0x2d54 +#define mmSPI_SHADER_USER_DATA_LS_9 0x2d55 +#define mmSPI_SHADER_USER_DATA_LS_10 0x2d56 +#define mmSPI_SHADER_USER_DATA_LS_11 0x2d57 +#define mmSPI_SHADER_USER_DATA_LS_12 0x2d58 +#define mmSPI_SHADER_USER_DATA_LS_13 0x2d59 +#define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a +#define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b +#define mmSQ_CONFIG 0x2300 +#define mmSQC_CONFIG 0x2301 +#define mmSQC_CACHES 0xc348 +#define mmSQ_RANDOM_WAVE_PRI 0x2303 +#define mmSQ_REG_CREDITS 0x2304 +#define mmSQ_FIFO_SIZES 0x2305 +#define mmSQ_INTERRUPT_AUTO_MASK 0x2314 +#define mmSQ_INTERRUPT_MSG_CTRL 0x2315 +#define mmSQ_PERFCOUNTER_CTRL 0xd9e0 +#define mmSQ_PERFCOUNTER_MASK 0xd9e1 +#define mmSQ_PERFCOUNTER_CTRL2 0xd9e2 +#define mmCC_SQC_BANK_DISABLE 0x2307 +#define mmUSER_SQC_BANK_DISABLE 0x2308 +#define mmSQ_PERFCOUNTER0_LO 0xd1c0 +#define mmSQ_PERFCOUNTER1_LO 0xd1c2 +#define mmSQ_PERFCOUNTER2_LO 0xd1c4 +#define mmSQ_PERFCOUNTER3_LO 0xd1c6 +#define mmSQ_PERFCOUNTER4_LO 0xd1c8 +#define mmSQ_PERFCOUNTER5_LO 0xd1ca +#define mmSQ_PERFCOUNTER6_LO 0xd1cc +#define mmSQ_PERFCOUNTER7_LO 0xd1ce +#define mmSQ_PERFCOUNTER8_LO 0xd1d0 +#define mmSQ_PERFCOUNTER9_LO 0xd1d2 +#define mmSQ_PERFCOUNTER10_LO 0xd1d4 +#define mmSQ_PERFCOUNTER11_LO 0xd1d6 +#define mmSQ_PERFCOUNTER12_LO 0xd1d8 +#define mmSQ_PERFCOUNTER13_LO 0xd1da +#define mmSQ_PERFCOUNTER14_LO 0xd1dc +#define mmSQ_PERFCOUNTER15_LO 0xd1de +#define mmSQ_PERFCOUNTER0_HI 0xd1c1 +#define mmSQ_PERFCOUNTER1_HI 0xd1c3 +#define mmSQ_PERFCOUNTER2_HI 0xd1c5 +#define mmSQ_PERFCOUNTER3_HI 0xd1c7 +#define mmSQ_PERFCOUNTER4_HI 0xd1c9 +#define mmSQ_PERFCOUNTER5_HI 0xd1cb +#define mmSQ_PERFCOUNTER6_HI 0xd1cd +#define mmSQ_PERFCOUNTER7_HI 0xd1cf +#define mmSQ_PERFCOUNTER8_HI 0xd1d1 +#define mmSQ_PERFCOUNTER9_HI 0xd1d3 +#define mmSQ_PERFCOUNTER10_HI 0xd1d5 +#define mmSQ_PERFCOUNTER11_HI 0xd1d7 +#define mmSQ_PERFCOUNTER12_HI 0xd1d9 +#define mmSQ_PERFCOUNTER13_HI 0xd1db +#define mmSQ_PERFCOUNTER14_HI 0xd1dd +#define mmSQ_PERFCOUNTER15_HI 0xd1df +#define mmSQ_PERFCOUNTER0_SELECT 0xd9c0 +#define mmSQ_PERFCOUNTER1_SELECT 0xd9c1 +#define mmSQ_PERFCOUNTER2_SELECT 0xd9c2 +#define mmSQ_PERFCOUNTER3_SELECT 0xd9c3 +#define mmSQ_PERFCOUNTER4_SELECT 0xd9c4 +#define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 +#define mmSQ_PERFCOUNTER6_SELECT 0xd9c6 +#define mmSQ_PERFCOUNTER7_SELECT 0xd9c7 +#define mmSQ_PERFCOUNTER8_SELECT 0xd9c8 +#define mmSQ_PERFCOUNTER9_SELECT 0xd9c9 +#define mmSQ_PERFCOUNTER10_SELECT 0xd9ca +#define mmSQ_PERFCOUNTER11_SELECT 0xd9cb +#define mmSQ_PERFCOUNTER12_SELECT 0xd9cc +#define mmSQ_PERFCOUNTER13_SELECT 0xd9cd +#define mmSQ_PERFCOUNTER14_SELECT 0xd9ce +#define mmSQ_PERFCOUNTER15_SELECT 0xd9cf +#define mmCGTT_SQ_CLK_CTRL 0xf08c +#define mmCGTT_SQG_CLK_CTRL 0xf08d +#define mmSQ_ALU_CLK_CTRL 0xf08e +#define mmSQ_TEX_CLK_CTRL 0xf08f +#define mmSQ_LDS_CLK_CTRL 0xf090 +#define mmSQ_POWER_THROTTLE 0xf091 +#define mmSQ_POWER_THROTTLE2 0xf092 +#define mmSQ_TIME_HI 0x237c +#define mmSQ_TIME_LO 0x237d +#define mmSQ_THREAD_TRACE_BASE 0x2380 +#define mmSQ_THREAD_TRACE_BASE2 0x2385 +#define mmSQ_THREAD_TRACE_SIZE 0x2381 +#define mmSQ_THREAD_TRACE_MASK 0x2382 +#define mmSQ_THREAD_TRACE_USERDATA_0 0xc340 +#define mmSQ_THREAD_TRACE_USERDATA_1 0xc341 +#define mmSQ_THREAD_TRACE_USERDATA_2 0xc342 +#define mmSQ_THREAD_TRACE_USERDATA_3 0xc343 +#define mmSQ_THREAD_TRACE_MODE 0x238e +#define mmSQ_THREAD_TRACE_CTRL 0x238f +#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383 +#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2386 +#define mmSQ_THREAD_TRACE_PERF_MASK 0x2384 +#define mmSQ_THREAD_TRACE_WPTR 0x238c +#define mmSQ_THREAD_TRACE_STATUS 0x238d +#define mmSQ_THREAD_TRACE_CNTR 0x2390 +#define mmSQ_THREAD_TRACE_HIWATER 0x2392 +#define mmSQ_LB_CTR_CTRL 0x2398 +#define mmSQ_LB_DATA_ALU_CYCLES 0x2399 +#define mmSQ_LB_DATA_TEX_CYCLES 0x239a +#define mmSQ_LB_DATA_ALU_STALLS 0x239b +#define mmSQ_LB_DATA_TEX_STALLS 0x239c +#define mmSQC_SECDED_CNT 0x23a0 +#define mmSQ_SEC_CNT 0x23a1 +#define mmSQ_DED_CNT 0x23a2 +#define mmSQ_DED_INFO 0x23a3 +#define mmSQ_BUF_RSRC_WORD0 0x23c0 +#define mmSQ_BUF_RSRC_WORD1 0x23c1 +#define mmSQ_BUF_RSRC_WORD2 0x23c2 +#define mmSQ_BUF_RSRC_WORD3 0x23c3 +#define mmSQ_IMG_RSRC_WORD0 0x23c4 +#define mmSQ_IMG_RSRC_WORD1 0x23c5 +#define mmSQ_IMG_RSRC_WORD2 0x23c6 +#define mmSQ_IMG_RSRC_WORD3 0x23c7 +#define mmSQ_IMG_RSRC_WORD4 0x23c8 +#define mmSQ_IMG_RSRC_WORD5 0x23c9 +#define mmSQ_IMG_RSRC_WORD6 0x23ca +#define mmSQ_IMG_RSRC_WORD7 0x23cb +#define mmSQ_IMG_SAMP_WORD0 0x23cc +#define mmSQ_IMG_SAMP_WORD1 0x23cd +#define mmSQ_IMG_SAMP_WORD2 0x23ce +#define mmSQ_IMG_SAMP_WORD3 0x23cf +#define mmSQ_FLAT_SCRATCH_WORD0 0x23d0 +#define mmSQ_FLAT_SCRATCH_WORD1 0x23d1 +#define mmSQ_IND_INDEX 0x2378 +#define mmSQ_IND_CMD 0x237a +#define mmSQ_CMD 0x237b +#define mmSQ_IND_DATA 0x2379 +#define mmSQ_REG_TIMESTAMP 0x2374 +#define mmSQ_CMD_TIMESTAMP 0x2375 +#define mmSQ_HV_VMID_CTRL 0xf840 +#define ixSQ_WAVE_INST_DW0 0x1a +#define ixSQ_WAVE_INST_DW1 0x1b +#define ixSQ_WAVE_PC_LO 0x18 +#define ixSQ_WAVE_PC_HI 0x19 +#define ixSQ_WAVE_IB_DBG0 0x1c +#define ixSQ_WAVE_EXEC_LO 0x27e +#define ixSQ_WAVE_EXEC_HI 0x27f +#define ixSQ_WAVE_STATUS 0x12 +#define ixSQ_WAVE_MODE 0x11 +#define ixSQ_WAVE_TRAPSTS 0x13 +#define ixSQ_WAVE_HW_ID 0x14 +#define ixSQ_WAVE_GPR_ALLOC 0x15 +#define ixSQ_WAVE_LDS_ALLOC 0x16 +#define ixSQ_WAVE_IB_STS 0x17 +#define ixSQ_WAVE_M0 0x27c +#define ixSQ_WAVE_TBA_LO 0x26c +#define ixSQ_WAVE_TBA_HI 0x26d +#define ixSQ_WAVE_TMA_LO 0x26e +#define ixSQ_WAVE_TMA_HI 0x26f +#define ixSQ_WAVE_TTMP0 0x270 +#define ixSQ_WAVE_TTMP1 0x271 +#define ixSQ_WAVE_TTMP2 0x272 +#define ixSQ_WAVE_TTMP3 0x273 +#define ixSQ_WAVE_TTMP4 0x274 +#define ixSQ_WAVE_TTMP5 0x275 +#define ixSQ_WAVE_TTMP6 0x276 +#define ixSQ_WAVE_TTMP7 0x277 +#define ixSQ_WAVE_TTMP8 0x278 +#define ixSQ_WAVE_TTMP9 0x279 +#define ixSQ_WAVE_TTMP10 0x27a +#define ixSQ_WAVE_TTMP11 0x27b +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 +#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 +#define mmSQ_DEBUG_STS_GLOBAL3 0x2311 +#define ixSQ_DEBUG_STS_LOCAL 0x8 +#define ixSQ_DEBUG_CTRL_LOCAL 0x9 +#define mmSH_MEM_BASES 0x230a +#define mmSH_MEM_APE1_BASE 0x230b +#define mmSH_MEM_APE1_LIMIT 0x230c +#define mmSH_MEM_CONFIG 0x230d +#define mmSQC_POLICY 0x230e +#define mmSQC_VOLATILE 0x230f +#define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1 +#define ixSQ_INTERRUPT_WORD_CMN 0x20c0 +#define ixSQ_INTERRUPT_WORD_AUTO 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE 0x20c0 +#define mmSQ_SOP2 0x237f +#define mmSQ_VOP1 0x237f +#define mmSQ_MTBUF_1 0x237f +#define mmSQ_EXP_1 0x237f +#define mmSQ_MUBUF_1 0x237f +#define mmSQ_INST 0x237f +#define mmSQ_EXP_0 0x237f +#define mmSQ_MUBUF_0 0x237f +#define mmSQ_VOP3_0 0x237f +#define mmSQ_VOP2 0x237f +#define mmSQ_MTBUF_0 0x237f +#define mmSQ_SOPP 0x237f +#define mmSQ_FLAT_0 0x237f +#define mmSQ_VOP3_0_SDST_ENC 0x237f +#define mmSQ_MIMG_1 0x237f +#define mmSQ_SMRD 0x237f +#define mmSQ_SOP1 0x237f +#define mmSQ_SOPC 0x237f +#define mmSQ_FLAT_1 0x237f +#define mmSQ_DS_1 0x237f +#define mmSQ_VOP3_1 0x237f +#define mmSQ_MIMG_0 0x237f +#define mmSQ_SOPK 0x237f +#define mmSQ_DS_0 0x237f +#define mmSQ_VOPC 0x237f +#define mmSQ_VINTRP 0x237f +#define mmCGTT_SX_CLK_CTRL0 0xf094 +#define mmCGTT_SX_CLK_CTRL1 0xf095 +#define mmCGTT_SX_CLK_CTRL2 0xf096 +#define mmCGTT_SX_CLK_CTRL3 0xf097 +#define mmCGTT_SX_CLK_CTRL4 0xf098 +#define mmSX_DEBUG_BUSY 0x2414 +#define mmSX_DEBUG_BUSY_2 0x2415 +#define mmSX_DEBUG_BUSY_3 0x2416 +#define mmSX_DEBUG_BUSY_4 0x2417 +#define mmSX_DEBUG_1 0x2418 +#define mmSX_PERFCOUNTER0_SELECT 0xda40 +#define mmSX_PERFCOUNTER1_SELECT 0xda41 +#define mmSX_PERFCOUNTER2_SELECT 0xda42 +#define mmSX_PERFCOUNTER3_SELECT 0xda43 +#define mmSX_PERFCOUNTER0_SELECT1 0xda44 +#define mmSX_PERFCOUNTER1_SELECT1 0xda45 +#define mmSX_PERFCOUNTER0_LO 0xd240 +#define mmSX_PERFCOUNTER0_HI 0xd241 +#define mmSX_PERFCOUNTER1_LO 0xd242 +#define mmSX_PERFCOUNTER1_HI 0xd243 +#define mmSX_PERFCOUNTER2_LO 0xd244 +#define mmSX_PERFCOUNTER2_HI 0xd245 +#define mmSX_PERFCOUNTER3_LO 0xd246 +#define mmSX_PERFCOUNTER3_HI 0xd247 +#define mmTCC_CTRL 0x2b80 +#define mmTCC_EDC_COUNTER 0x2b82 +#define mmTCC_REDUNDANCY 0x2b83 +#define mmTCC_CGTT_SCLK_CTRL 0xf0ac +#define mmTCA_CGTT_SCLK_CTRL 0xf0ad +#define mmTCS_CGTT_SCLK_CTRL 0xf0ae +#define mmTCC_PERFCOUNTER0_SELECT 0xdb80 +#define mmTCC_PERFCOUNTER1_SELECT 0xdb82 +#define mmTCC_PERFCOUNTER0_SELECT1 0xdb81 +#define mmTCC_PERFCOUNTER1_SELECT1 0xdb83 +#define mmTCC_PERFCOUNTER2_SELECT 0xdb84 +#define mmTCC_PERFCOUNTER3_SELECT 0xdb85 +#define mmTCC_PERFCOUNTER0_LO 0xd380 +#define mmTCC_PERFCOUNTER1_LO 0xd382 +#define mmTCC_PERFCOUNTER2_LO 0xd384 +#define mmTCC_PERFCOUNTER3_LO 0xd386 +#define mmTCC_PERFCOUNTER0_HI 0xd381 +#define mmTCC_PERFCOUNTER1_HI 0xd383 +#define mmTCC_PERFCOUNTER2_HI 0xd385 +#define mmTCC_PERFCOUNTER3_HI 0xd387 +#define mmTCA_CTRL 0x2bc0 +#define mmTCA_PERFCOUNTER0_SELECT 0xdb90 +#define mmTCA_PERFCOUNTER1_SELECT 0xdb92 +#define mmTCA_PERFCOUNTER0_SELECT1 0xdb91 +#define mmTCA_PERFCOUNTER1_SELECT1 0xdb93 +#define mmTCA_PERFCOUNTER2_SELECT 0xdb94 +#define mmTCA_PERFCOUNTER3_SELECT 0xdb95 +#define mmTCA_PERFCOUNTER0_LO 0xd390 +#define mmTCA_PERFCOUNTER1_LO 0xd392 +#define mmTCA_PERFCOUNTER2_LO 0xd394 +#define mmTCA_PERFCOUNTER3_LO 0xd396 +#define mmTCA_PERFCOUNTER0_HI 0xd391 +#define mmTCA_PERFCOUNTER1_HI 0xd393 +#define mmTCA_PERFCOUNTER2_HI 0xd395 +#define mmTCA_PERFCOUNTER3_HI 0xd397 +#define mmTCS_CTRL 0x2be0 +#define mmTCS_PERFCOUNTER0_SELECT 0xdba0 +#define mmTCS_PERFCOUNTER0_SELECT1 0xdba1 +#define mmTCS_PERFCOUNTER1_SELECT 0xdba2 +#define mmTCS_PERFCOUNTER2_SELECT 0xdba3 +#define mmTCS_PERFCOUNTER3_SELECT 0xdba4 +#define mmTCS_PERFCOUNTER0_LO 0xd3a0 +#define mmTCS_PERFCOUNTER1_LO 0xd3a2 +#define mmTCS_PERFCOUNTER2_LO 0xd3a4 +#define mmTCS_PERFCOUNTER3_LO 0xd3a6 +#define mmTCS_PERFCOUNTER0_HI 0xd3a1 +#define mmTCS_PERFCOUNTER1_HI 0xd3a3 +#define mmTCS_PERFCOUNTER2_HI 0xd3a5 +#define mmTCS_PERFCOUNTER3_HI 0xd3a7 +#define mmTA_BC_BASE_ADDR 0xa020 +#define mmTA_BC_BASE_ADDR_HI 0xa021 +#define mmTD_CNTL 0x2525 +#define mmTD_STATUS 0x2526 +#define mmTD_DEBUG_INDEX 0x2528 +#define mmTD_DEBUG_DATA 0x2529 +#define mmTD_PERFCOUNTER0_SELECT 0xdb00 +#define mmTD_PERFCOUNTER1_SELECT 0xdb02 +#define mmTD_PERFCOUNTER0_SELECT1 0xdb01 +#define mmTD_PERFCOUNTER0_LO 0xd300 +#define mmTD_PERFCOUNTER1_LO 0xd302 +#define mmTD_PERFCOUNTER0_HI 0xd301 +#define mmTD_PERFCOUNTER1_HI 0xd303 +#define mmTD_SCRATCH 0x2533 +#define mmTA_CNTL 0x2541 +#define mmTA_CNTL_AUX 0x2542 +#define mmTA_RESERVED_010C 0x2543 +#define mmTA_CS_BC_BASE_ADDR 0xc380 +#define mmTA_CS_BC_BASE_ADDR_HI 0xc381 +#define mmTA_STATUS 0x2548 +#define mmTA_DEBUG_INDEX 0x254c +#define mmTA_DEBUG_DATA 0x254d +#define mmTA_PERFCOUNTER0_SELECT 0xdac0 +#define mmTA_PERFCOUNTER1_SELECT 0xdac2 +#define mmTA_PERFCOUNTER0_SELECT1 0xdac1 +#define mmTA_PERFCOUNTER0_LO 0xd2c0 +#define mmTA_PERFCOUNTER1_LO 0xd2c2 +#define mmTA_PERFCOUNTER0_HI 0xd2c1 +#define mmTA_PERFCOUNTER1_HI 0xd2c3 +#define mmTA_SCRATCH 0x2564 +#define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580 +#define mmSH_STATIC_MEM_CONFIG 0x2581 +#define mmTCP_INVALIDATE 0x2b00 +#define mmTCP_STATUS 0x2b01 +#define mmTCP_CNTL 0x2b02 +#define mmTCP_CHAN_STEER_LO 0x2b03 +#define mmTCP_CHAN_STEER_HI 0x2b04 +#define mmTCP_ADDR_CONFIG 0x2b05 +#define mmTCP_CREDIT 0x2b06 +#define mmTCP_PERFCOUNTER0_SELECT 0xdb40 +#define mmTCP_PERFCOUNTER1_SELECT 0xdb42 +#define mmTCP_PERFCOUNTER0_SELECT1 0xdb41 +#define mmTCP_PERFCOUNTER1_SELECT1 0xdb43 +#define mmTCP_PERFCOUNTER2_SELECT 0xdb44 +#define mmTCP_PERFCOUNTER3_SELECT 0xdb45 +#define mmTCP_PERFCOUNTER0_LO 0xd340 +#define mmTCP_PERFCOUNTER1_LO 0xd342 +#define mmTCP_PERFCOUNTER2_LO 0xd344 +#define mmTCP_PERFCOUNTER3_LO 0xd346 +#define mmTCP_PERFCOUNTER0_HI 0xd341 +#define mmTCP_PERFCOUNTER1_HI 0xd343 +#define mmTCP_PERFCOUNTER2_HI 0xd345 +#define mmTCP_PERFCOUNTER3_HI 0xd347 +#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16 +#define mmTCP_EDC_COUNTER 0x2b17 +#define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a +#define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b +#define mmTC_CFG_L1_STORE_POLICY 0x2b1c +#define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d +#define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e +#define mmTC_CFG_L2_STORE_POLICY0 0x2b1f +#define mmTC_CFG_L2_STORE_POLICY1 0x2b20 +#define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21 +#define mmTC_CFG_L1_VOLATILE 0x2b22 +#define mmTC_CFG_L2_VOLATILE 0x2b23 +#define mmTCP_WATCH0_ADDR_H 0x32a0 +#define mmTCP_WATCH1_ADDR_H 0x32a3 +#define mmTCP_WATCH2_ADDR_H 0x32a6 +#define mmTCP_WATCH3_ADDR_H 0x32a9 +#define mmTCP_WATCH0_ADDR_L 0x32a1 +#define mmTCP_WATCH1_ADDR_L 0x32a4 +#define mmTCP_WATCH2_ADDR_L 0x32a7 +#define mmTCP_WATCH3_ADDR_L 0x32aa +#define mmTCP_WATCH0_CNTL 0x32a2 +#define mmTCP_WATCH1_CNTL 0x32a5 +#define mmTCP_WATCH2_CNTL 0x32a8 +#define mmTCP_WATCH3_CNTL 0x32ab +#define mmTD_CGTT_CTRL 0xf09c +#define mmTA_CGTT_CTRL 0xf09d +#define mmCGTT_TCP_CLK_CTRL 0xf09e +#define mmCGTT_TCI_CLK_CTRL 0xf09f +#define mmTCI_STATUS 0x2b61 +#define mmTCI_CNTL_1 0x2b62 +#define mmTCI_CNTL_2 0x2b63 +#define mmGDS_CONFIG 0x25c0 +#define mmGDS_CNTL_STATUS 0x25c1 +#define mmGDS_ENHANCE2 0x25c2 +#define mmGDS_PROTECTION_FAULT 0x25c3 +#define mmGDS_VM_PROTECTION_FAULT 0x25c4 +#define mmGDS_SECDED_CNT 0x25c5 +#define mmGDS_GRBM_SECDED_CNT 0x25c6 +#define mmGDS_OA_DED 0x25c7 +#define mmGDS_DEBUG_CNTL 0x25c8 +#define mmGDS_DEBUG_DATA 0x25c9 +#define mmCGTT_GDS_CLK_CTRL 0xf0a0 +#define mmGDS_RD_ADDR 0xc400 +#define mmGDS_RD_DATA 0xc401 +#define mmGDS_RD_BURST_ADDR 0xc402 +#define mmGDS_RD_BURST_COUNT 0xc403 +#define mmGDS_RD_BURST_DATA 0xc404 +#define mmGDS_WR_ADDR 0xc405 +#define mmGDS_WR_DATA 0xc406 +#define mmGDS_WR_BURST_ADDR 0xc407 +#define mmGDS_WR_BURST_DATA 0xc408 +#define mmGDS_WRITE_COMPLETE 0xc409 +#define mmGDS_ATOM_CNTL 0xc40a +#define mmGDS_ATOM_COMPLETE 0xc40b +#define mmGDS_ATOM_BASE 0xc40c +#define mmGDS_ATOM_SIZE 0xc40d +#define mmGDS_ATOM_OFFSET0 0xc40e +#define mmGDS_ATOM_OFFSET1 0xc40f +#define mmGDS_ATOM_DST 0xc410 +#define mmGDS_ATOM_OP 0xc411 +#define mmGDS_ATOM_SRC0 0xc412 +#define mmGDS_ATOM_SRC0_U 0xc413 +#define mmGDS_ATOM_SRC1 0xc414 +#define mmGDS_ATOM_SRC1_U 0xc415 +#define mmGDS_ATOM_READ0 0xc416 +#define mmGDS_ATOM_READ0_U 0xc417 +#define mmGDS_ATOM_READ1 0xc418 +#define mmGDS_ATOM_READ1_U 0xc419 +#define mmGDS_GWS_RESOURCE_CNTL 0xc41a +#define mmGDS_GWS_RESOURCE 0xc41b +#define mmGDS_GWS_RESOURCE_CNT 0xc41c +#define mmGDS_OA_CNTL 0xc41d +#define mmGDS_OA_COUNTER 0xc41e +#define mmGDS_OA_ADDRESS 0xc41f +#define mmGDS_OA_INCDEC 0xc420 +#define mmGDS_OA_RING_SIZE 0xc421 +#define ixGDS_DEBUG_REG0 0x0 +#define ixGDS_DEBUG_REG1 0x1 +#define ixGDS_DEBUG_REG2 0x2 +#define ixGDS_DEBUG_REG3 0x3 +#define ixGDS_DEBUG_REG4 0x4 +#define ixGDS_DEBUG_REG5 0x5 +#define ixGDS_DEBUG_REG6 0x6 +#define mmGDS_PERFCOUNTER0_SELECT 0xda80 +#define mmGDS_PERFCOUNTER1_SELECT 0xda81 +#define mmGDS_PERFCOUNTER2_SELECT 0xda82 +#define mmGDS_PERFCOUNTER3_SELECT 0xda83 +#define mmGDS_PERFCOUNTER0_LO 0xd280 +#define mmGDS_PERFCOUNTER1_LO 0xd282 +#define mmGDS_PERFCOUNTER2_LO 0xd284 +#define mmGDS_PERFCOUNTER3_LO 0xd286 +#define mmGDS_PERFCOUNTER0_HI 0xd281 +#define mmGDS_PERFCOUNTER1_HI 0xd283 +#define mmGDS_PERFCOUNTER2_HI 0xd285 +#define mmGDS_PERFCOUNTER3_HI 0xd287 +#define mmGDS_PERFCOUNTER0_SELECT1 0xda84 +#define mmGDS_VMID0_BASE 0x3300 +#define mmGDS_VMID1_BASE 0x3302 +#define mmGDS_VMID2_BASE 0x3304 +#define mmGDS_VMID3_BASE 0x3306 +#define mmGDS_VMID4_BASE 0x3308 +#define mmGDS_VMID5_BASE 0x330a +#define mmGDS_VMID6_BASE 0x330c +#define mmGDS_VMID7_BASE 0x330e +#define mmGDS_VMID8_BASE 0x3310 +#define mmGDS_VMID9_BASE 0x3312 +#define mmGDS_VMID10_BASE 0x3314 +#define mmGDS_VMID11_BASE 0x3316 +#define mmGDS_VMID12_BASE 0x3318 +#define mmGDS_VMID13_BASE 0x331a +#define mmGDS_VMID14_BASE 0x331c +#define mmGDS_VMID15_BASE 0x331e +#define mmGDS_VMID0_SIZE 0x3301 +#define mmGDS_VMID1_SIZE 0x3303 +#define mmGDS_VMID2_SIZE 0x3305 +#define mmGDS_VMID3_SIZE 0x3307 +#define mmGDS_VMID4_SIZE 0x3309 +#define mmGDS_VMID5_SIZE 0x330b +#define mmGDS_VMID6_SIZE 0x330d +#define mmGDS_VMID7_SIZE 0x330f +#define mmGDS_VMID8_SIZE 0x3311 +#define mmGDS_VMID9_SIZE 0x3313 +#define mmGDS_VMID10_SIZE 0x3315 +#define mmGDS_VMID11_SIZE 0x3317 +#define mmGDS_VMID12_SIZE 0x3319 +#define mmGDS_VMID13_SIZE 0x331b +#define mmGDS_VMID14_SIZE 0x331d +#define mmGDS_VMID15_SIZE 0x331f +#define mmGDS_GWS_VMID0 0x3320 +#define mmGDS_GWS_VMID1 0x3321 +#define mmGDS_GWS_VMID2 0x3322 +#define mmGDS_GWS_VMID3 0x3323 +#define mmGDS_GWS_VMID4 0x3324 +#define mmGDS_GWS_VMID5 0x3325 +#define mmGDS_GWS_VMID6 0x3326 +#define mmGDS_GWS_VMID7 0x3327 +#define mmGDS_GWS_VMID8 0x3328 +#define mmGDS_GWS_VMID9 0x3329 +#define mmGDS_GWS_VMID10 0x332a +#define mmGDS_GWS_VMID11 0x332b +#define mmGDS_GWS_VMID12 0x332c +#define mmGDS_GWS_VMID13 0x332d +#define mmGDS_GWS_VMID14 0x332e +#define mmGDS_GWS_VMID15 0x332f +#define mmGDS_OA_VMID0 0x3330 +#define mmGDS_OA_VMID1 0x3331 +#define mmGDS_OA_VMID2 0x3332 +#define mmGDS_OA_VMID3 0x3333 +#define mmGDS_OA_VMID4 0x3334 +#define mmGDS_OA_VMID5 0x3335 +#define mmGDS_OA_VMID6 0x3336 +#define mmGDS_OA_VMID7 0x3337 +#define mmGDS_OA_VMID8 0x3338 +#define mmGDS_OA_VMID9 0x3339 +#define mmGDS_OA_VMID10 0x333a +#define mmGDS_OA_VMID11 0x333b +#define mmGDS_OA_VMID12 0x333c +#define mmGDS_OA_VMID13 0x333d +#define mmGDS_OA_VMID14 0x333e +#define mmGDS_OA_VMID15 0x333f +#define mmGDS_GWS_RESET0 0x3344 +#define mmGDS_GWS_RESET1 0x3345 +#define mmGDS_GWS_RESOURCE_RESET 0x3346 +#define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348 +#define mmGDS_OA_RESET_MASK 0x3349 +#define mmGDS_OA_RESET 0x334a +#define mmGDS_ENHANCE 0x334b +#define mmGDS_OA_CGPG_RESTORE 0x334c +#define mmCS_COPY_STATE 0xa1f3 +#define mmGFX_COPY_STATE 0xa1f4 +#define mmVGT_DRAW_INITIATOR 0xa1fc +#define mmVGT_EVENT_INITIATOR 0xa2a4 +#define mmVGT_EVENT_ADDRESS_REG 0xa1fe +#define mmVGT_DMA_BASE_HI 0xa1f9 +#define mmVGT_DMA_BASE 0xa1fa +#define mmVGT_DMA_INDEX_TYPE 0xa29f +#define mmVGT_DMA_NUM_INSTANCES 0xa2a2 +#define mmIA_ENHANCE 0xa29c +#define mmVGT_DMA_SIZE 0xa29d +#define mmVGT_DMA_MAX_SIZE 0xa29e +#define mmVGT_DMA_PRIMITIVE_TYPE 0x2271 +#define mmVGT_DMA_CONTROL 0x2272 +#define mmVGT_IMMED_DATA 0xa1fd +#define mmVGT_INDEX_TYPE 0xc243 +#define mmVGT_NUM_INDICES 0xc24c +#define mmVGT_NUM_INSTANCES 0xc24d +#define mmVGT_PRIMITIVE_TYPE 0xc242 +#define mmVGT_PRIMITIVEID_EN 0xa2a1 +#define mmVGT_PRIMITIVEID_RESET 0xa2a3 +#define mmVGT_VTX_CNT_EN 0xa2ae +#define mmVGT_REUSE_OFF 0xa2ad +#define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8 +#define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9 +#define mmVGT_MAX_VTX_INDX 0xa100 +#define mmVGT_MIN_VTX_INDX 0xa101 +#define mmVGT_INDX_OFFSET 0xa102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316 +#define mmVGT_OUT_DEALLOC_CNTL 0xa317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103 +#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5 +#define mmVGT_ENHANCE 0xa294 +#define mmVGT_OUTPUT_PATH_CNTL 0xa284 +#define mmVGT_HOS_CNTL 0xa285 +#define mmVGT_HOS_MAX_TESS_LEVEL 0xa286 +#define mmVGT_HOS_MIN_TESS_LEVEL 0xa287 +#define mmVGT_HOS_REUSE_DEPTH 0xa288 +#define mmVGT_GROUP_PRIM_TYPE 0xa289 +#define mmVGT_GROUP_FIRST_DECR 0xa28a +#define mmVGT_GROUP_DECR 0xa28b +#define mmVGT_GROUP_VECT_0_CNTL 0xa28c +#define mmVGT_GROUP_VECT_1_CNTL 0xa28d +#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e +#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f +#define mmVGT_VTX_VECT_EJECT_REG 0x222c +#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d +#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e +#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f +#define mmVGT_LAST_COPY_STATE 0x2230 +#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f +#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 +#define mmVGT_GS_MODE 0xa290 +#define mmVGT_GS_ONCHIP_CNTL 0xa291 +#define mmVGT_GS_OUT_PRIM_TYPE 0xa29b +#define mmVGT_CACHE_INVALIDATION 0x2231 +#define mmVGT_RESET_DEBUG 0x2232 +#define mmVGT_STRMOUT_DELAY 0x2233 +#define mmVGT_FIFO_DEPTHS 0x2234 +#define mmVGT_GS_PER_ES 0xa295 +#define mmVGT_ES_PER_GS 0xa296 +#define mmVGT_GS_PER_VS 0xa297 +#define mmVGT_GS_VERTEX_REUSE 0x2235 +#define mmVGT_MC_LAT_CNTL 0x2236 +#define mmIA_CNTL_STATUS 0x2237 +#define mmVGT_STRMOUT_CONFIG 0xa2e5 +#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4 +#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8 +#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc +#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0 +#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7 +#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb +#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf +#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3 +#define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5 +#define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9 +#define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd +#define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1 +#define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247 +#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca +#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb +#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc +#define mmVGT_GS_MAX_VERT_OUT 0xa2ce +#define mmIA_VMID_OVERRIDE 0x2260 +#define mmVGT_SHADER_STAGES_EN 0xa2d5 +#define mmVGT_DISPATCH_DRAW_INDEX 0xa2dd +#define mmVGT_LS_HS_CONFIG 0xa2d6 +#define mmVGT_DMA_LS_HS_CONFIG 0x2273 +#define mmVGT_TF_PARAM 0xa2db +#define mmVGT_TF_RING_SIZE 0xc24e +#define mmVGT_SYS_CONFIG 0x2263 +#define mmVGT_HS_OFFCHIP_PARAM 0xc24f +#define mmVGT_TF_MEMORY_BASE 0xc250 +#define mmVGT_GS_INSTANCE_CNT 0xa2e4 +#define mmIA_MULTI_VGT_PARAM 0xa2aa +#define mmVGT_VS_MAX_WAVE_ID 0x2268 +#define mmVGT_ESGS_RING_SIZE 0xc240 +#define mmVGT_GSVS_RING_SIZE 0xc241 +#define mmVGT_GSVS_RING_OFFSET_1 0xa298 +#define mmVGT_GSVS_RING_OFFSET_2 0xa299 +#define mmVGT_GSVS_RING_OFFSET_3 0xa29a +#define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab +#define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac +#define mmVGT_GS_VERT_ITEMSIZE 0xa2d7 +#define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8 +#define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9 +#define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da +#define mmWD_CNTL_STATUS 0x223f +#define mmWD_ENHANCE 0xa2a0 +#define mmGFX_PIPE_CONTROL 0x226d +#define mmGFX_PIPE_PRIORITY 0xf87f +#define mmCGTT_VGT_CLK_CTRL 0xf084 +#define mmCGTT_IA_CLK_CTRL 0xf085 +#define mmCGTT_WD_CLK_CTRL 0xf086 +#define mmVGT_DEBUG_CNTL 0x2238 +#define mmVGT_DEBUG_DATA 0x2239 +#define mmIA_DEBUG_CNTL 0x223a +#define mmIA_DEBUG_DATA 0x223b +#define mmVGT_CNTL_STATUS 0x223c +#define mmWD_DEBUG_CNTL 0x223d +#define mmWD_DEBUG_DATA 0x223e +#define mmCC_GC_PRIM_CONFIG 0x2240 +#define mmGC_USER_PRIM_CONFIG 0x2241 +#define ixWD_DEBUG_REG0 0x0 +#define ixWD_DEBUG_REG1 0x1 +#define ixWD_DEBUG_REG2 0x2 +#define ixWD_DEBUG_REG3 0x3 +#define ixWD_DEBUG_REG4 0x4 +#define ixWD_DEBUG_REG5 0x5 +#define ixIA_DEBUG_REG0 0x0 +#define ixIA_DEBUG_REG1 0x1 +#define ixIA_DEBUG_REG2 0x2 +#define ixIA_DEBUG_REG3 0x3 +#define ixIA_DEBUG_REG4 0x4 +#define ixIA_DEBUG_REG5 0x5 +#define ixIA_DEBUG_REG6 0x6 +#define ixIA_DEBUG_REG7 0x7 +#define ixIA_DEBUG_REG8 0x8 +#define ixIA_DEBUG_REG9 0x9 +#define ixVGT_DEBUG_REG0 0x0 +#define ixVGT_DEBUG_REG1 0x1 +#define ixVGT_DEBUG_REG2 0x1e +#define ixVGT_DEBUG_REG3 0x1f +#define ixVGT_DEBUG_REG4 0x20 +#define ixVGT_DEBUG_REG5 0x21 +#define ixVGT_DEBUG_REG6 0x22 +#define ixVGT_DEBUG_REG7 0x23 +#define ixVGT_DEBUG_REG8 0x8 +#define ixVGT_DEBUG_REG9 0x9 +#define ixVGT_DEBUG_REG10 0xa +#define ixVGT_DEBUG_REG11 0xb +#define ixVGT_DEBUG_REG12 0xc +#define ixVGT_DEBUG_REG13 0xd +#define ixVGT_DEBUG_REG14 0xe +#define ixVGT_DEBUG_REG15 0xf +#define ixVGT_DEBUG_REG16 0x10 +#define ixVGT_DEBUG_REG17 0x11 +#define ixVGT_DEBUG_REG18 0x7 +#define ixVGT_DEBUG_REG19 0x13 +#define ixVGT_DEBUG_REG20 0x14 +#define ixVGT_DEBUG_REG21 0x15 +#define ixVGT_DEBUG_REG22 0x16 +#define ixVGT_DEBUG_REG23 0x17 +#define ixVGT_DEBUG_REG24 0x18 +#define ixVGT_DEBUG_REG25 0x19 +#define ixVGT_DEBUG_REG26 0x24 +#define ixVGT_DEBUG_REG27 0x1b +#define ixVGT_DEBUG_REG28 0x1c +#define ixVGT_DEBUG_REG29 0x1d +#define ixVGT_DEBUG_REG30 0x25 +#define ixVGT_DEBUG_REG31 0x26 +#define ixVGT_DEBUG_REG32 0x27 +#define ixVGT_DEBUG_REG33 0x28 +#define ixVGT_DEBUG_REG34 0x29 +#define ixVGT_DEBUG_REG35 0x2a +#define mmVGT_PERFCOUNTER_SEID_MASK 0xd894 +#define mmVGT_PERFCOUNTER0_SELECT 0xd88c +#define mmVGT_PERFCOUNTER1_SELECT 0xd88d +#define mmVGT_PERFCOUNTER2_SELECT 0xd88e +#define mmVGT_PERFCOUNTER3_SELECT 0xd88f +#define mmVGT_PERFCOUNTER0_SELECT1 0xd890 +#define mmVGT_PERFCOUNTER1_SELECT1 0xd891 +#define mmVGT_PERFCOUNTER0_LO 0xd090 +#define mmVGT_PERFCOUNTER1_LO 0xd092 +#define mmVGT_PERFCOUNTER2_LO 0xd094 +#define mmVGT_PERFCOUNTER3_LO 0xd096 +#define mmVGT_PERFCOUNTER0_HI 0xd091 +#define mmVGT_PERFCOUNTER1_HI 0xd093 +#define mmVGT_PERFCOUNTER2_HI 0xd095 +#define mmVGT_PERFCOUNTER3_HI 0xd097 +#define mmIA_PERFCOUNTER0_SELECT 0xd884 +#define mmIA_PERFCOUNTER1_SELECT 0xd885 +#define mmIA_PERFCOUNTER2_SELECT 0xd886 +#define mmIA_PERFCOUNTER3_SELECT 0xd887 +#define mmIA_PERFCOUNTER0_SELECT1 0xd888 +#define mmIA_PERFCOUNTER0_LO 0xd088 +#define mmIA_PERFCOUNTER1_LO 0xd08a +#define mmIA_PERFCOUNTER2_LO 0xd08c +#define mmIA_PERFCOUNTER3_LO 0xd08e +#define mmIA_PERFCOUNTER0_HI 0xd089 +#define mmIA_PERFCOUNTER1_HI 0xd08b +#define mmIA_PERFCOUNTER2_HI 0xd08d +#define mmIA_PERFCOUNTER3_HI 0xd08f +#define mmWD_PERFCOUNTER0_SELECT 0xd880 +#define mmWD_PERFCOUNTER1_SELECT 0xd881 +#define mmWD_PERFCOUNTER2_SELECT 0xd882 +#define mmWD_PERFCOUNTER3_SELECT 0xd883 +#define mmWD_PERFCOUNTER0_LO 0xd080 +#define mmWD_PERFCOUNTER1_LO 0xd082 +#define mmWD_PERFCOUNTER2_LO 0xd084 +#define mmWD_PERFCOUNTER3_LO 0xd086 +#define mmWD_PERFCOUNTER0_HI 0xd081 +#define mmWD_PERFCOUNTER1_HI 0xd083 +#define mmWD_PERFCOUNTER2_HI 0xd085 +#define mmWD_PERFCOUNTER3_HI 0xd087 +#define mmDIDT_IND_INDEX 0x3280 +#define mmDIDT_IND_DATA 0x3281 +#define ixDIDT_SQ_CTRL0 0x0 +#define ixDIDT_SQ_CTRL1 0x1 +#define ixDIDT_SQ_CTRL2 0x2 +#define ixDIDT_SQ_WEIGHT0_3 0x10 +#define ixDIDT_SQ_WEIGHT4_7 0x11 +#define ixDIDT_SQ_WEIGHT8_11 0x12 +#define ixDIDT_DB_CTRL0 0x20 +#define ixDIDT_DB_CTRL1 0x21 +#define ixDIDT_DB_CTRL2 0x22 +#define ixDIDT_DB_WEIGHT0_3 0x30 +#define ixDIDT_DB_WEIGHT4_7 0x31 +#define ixDIDT_DB_WEIGHT8_11 0x32 +#define ixDIDT_TD_CTRL0 0x40 +#define ixDIDT_TD_CTRL1 0x41 +#define ixDIDT_TD_CTRL2 0x42 +#define ixDIDT_TD_WEIGHT0_3 0x50 +#define ixDIDT_TD_WEIGHT4_7 0x51 +#define ixDIDT_TD_WEIGHT8_11 0x52 +#define ixDIDT_TCP_CTRL0 0x60 +#define ixDIDT_TCP_CTRL1 0x61 +#define ixDIDT_TCP_CTRL2 0x62 +#define ixDIDT_TCP_WEIGHT0_3 0x70 +#define ixDIDT_TCP_WEIGHT4_7 0x71 +#define ixDIDT_TCP_WEIGHT8_11 0x72 + +#endif /* GFX_7_2_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h new file mode 100644 index 000000000000..9d4347dd6125 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h @@ -0,0 +1,6274 @@ +/* + * GFX_7_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_7_2_ENUM_H +#define GFX_7_2_ENUM_H + +typedef enum SurfaceNumber { + NUMBER_UNORM = 0x0, + NUMBER_SNORM = 0x1, + NUMBER_USCALED = 0x2, + NUMBER_SSCALED = 0x3, + NUMBER_UINT = 0x4, + NUMBER_SINT = 0x5, + NUMBER_SRGB = 0x6, + NUMBER_FLOAT = 0x7, +} SurfaceNumber; +typedef enum SurfaceSwap { + SWAP_STD = 0x0, + SWAP_ALT = 0x1, + SWAP_STD_REV = 0x2, + SWAP_ALT_REV = 0x3, +} SurfaceSwap; +typedef enum CBMode { + CB_DISABLE = 0x0, + CB_NORMAL = 0x1, + CB_ELIMINATE_FAST_CLEAR = 0x2, + CB_RESOLVE = 0x3, + CB_DECOMPRESS = 0x4, + CB_FMASK_DECOMPRESS = 0x5, +} CBMode; +typedef enum RoundMode { + ROUND_BY_HALF = 0x0, + ROUND_TRUNCATE = 0x1, +} RoundMode; +typedef enum SourceFormat { + EXPORT_4C_32BPC = 0x0, + EXPORT_4C_16BPC = 0x1, + EXPORT_2C_32BPC_GR = 0x2, + EXPORT_2C_32BPC_AR = 0x3, +} SourceFormat; +typedef enum BlendOp { + BLEND_ZERO = 0x0, + BLEND_ONE = 0x1, + BLEND_SRC_COLOR = 0x2, + BLEND_ONE_MINUS_SRC_COLOR = 0x3, + BLEND_SRC_ALPHA = 0x4, + BLEND_ONE_MINUS_SRC_ALPHA = 0x5, + BLEND_DST_ALPHA = 0x6, + BLEND_ONE_MINUS_DST_ALPHA = 0x7, + BLEND_DST_COLOR = 0x8, + BLEND_ONE_MINUS_DST_COLOR = 0x9, + BLEND_SRC_ALPHA_SATURATE = 0xa, + BLEND_BOTH_SRC_ALPHA = 0xb, + BLEND_BOTH_INV_SRC_ALPHA = 0xc, + BLEND_CONSTANT_COLOR = 0xd, + BLEND_ONE_MINUS_CONSTANT_COLOR = 0xe, + BLEND_SRC1_COLOR = 0xf, + BLEND_INV_SRC1_COLOR = 0x10, + BLEND_SRC1_ALPHA = 0x11, + BLEND_INV_SRC1_ALPHA = 0x12, + BLEND_CONSTANT_ALPHA = 0x13, + BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, +} BlendOp; +typedef enum CombFunc { + COMB_DST_PLUS_SRC = 0x0, + COMB_SRC_MINUS_DST = 0x1, + COMB_MIN_DST_SRC = 0x2, + COMB_MAX_DST_SRC = 0x3, + COMB_DST_MINUS_SRC = 0x4, +} CombFunc; +typedef enum BlendOpt { + FORCE_OPT_AUTO = 0x0, + FORCE_OPT_DISABLE = 0x1, + FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2, + FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x3, + FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x4, + FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5, + FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x6, + FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x7, +} BlendOpt; +typedef enum CmaskCode { + CMASK_CLR00_F0 = 0x0, + CMASK_CLR00_F1 = 0x1, + CMASK_CLR00_F2 = 0x2, + CMASK_CLR00_FX = 0x3, + CMASK_CLR01_F0 = 0x4, + CMASK_CLR01_F1 = 0x5, + CMASK_CLR01_F2 = 0x6, + CMASK_CLR01_FX = 0x7, + CMASK_CLR10_F0 = 0x8, + CMASK_CLR10_F1 = 0x9, + CMASK_CLR10_F2 = 0xa, + CMASK_CLR10_FX = 0xb, + CMASK_CLR11_F0 = 0xc, + CMASK_CLR11_F1 = 0xd, + CMASK_CLR11_F2 = 0xe, + CMASK_CLR11_FX = 0xf, +} CmaskCode; +typedef enum CBPerfSel { + CB_PERF_SEL_NONE = 0x0, + CB_PERF_SEL_BUSY = 0x1, + CB_PERF_SEL_CORE_SCLK_VLD = 0x2, + CB_PERF_SEL_REG_SCLK0_VLD = 0x3, + CB_PERF_SEL_REG_SCLK1_VLD = 0x4, + CB_PERF_SEL_DRAWN_QUAD = 0x5, + CB_PERF_SEL_DRAWN_PIXEL = 0x6, + CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x7, + CB_PERF_SEL_DRAWN_TILE = 0x8, + CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x9, + CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa, + CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0xb, + CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0xc, + CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0xd, + CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0xe, + CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0xf, + CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x10, + CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x11, + CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x12, + CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x13, + CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x14, + CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x15, + CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x16, + CB_PERF_SEL_LQUAD_NO_TILE = 0x17, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x18, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x19, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x1a, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x1b, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x1c, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e, + CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x1f, + CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x20, + CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21, + CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x22, + CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x23, + CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x24, + CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x25, + CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x26, + CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x27, + CB_PERF_SEL_FOP_IN_VALID_READY = 0x28, + CB_PERF_SEL_FOP_IN_VALID_READYB = 0x29, + CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x2a, + CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x2b, + CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x2c, + CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x2d, + CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x2e, + CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x2f, + CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x30, + CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x31, + CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x32, + CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x33, + CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x34, + CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x35, + CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x36, + CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x37, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x38, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x39, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x3a, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x3b, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x3c, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x3d, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x3e, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x3f, + CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x40, + CB_PERF_SEL_CM_CACHE_HIT = 0x41, + CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x42, + CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x43, + CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x44, + CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45, + CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46, + CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47, + CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x48, + CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x49, + CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x4a, + CB_PERF_SEL_CM_CACHE_STALL = 0x4b, + CB_PERF_SEL_CM_CACHE_FLUSH = 0x4c, + CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x4d, + CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x4e, + CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x4f, + CB_PERF_SEL_FC_CACHE_HIT = 0x50, + CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x51, + CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x52, + CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x53, + CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54, + CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55, + CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56, + CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x57, + CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x58, + CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x59, + CB_PERF_SEL_FC_CACHE_STALL = 0x5a, + CB_PERF_SEL_FC_CACHE_FLUSH = 0x5b, + CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x5c, + CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x5d, + CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x5e, + CB_PERF_SEL_CC_CACHE_HIT = 0x5f, + CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x60, + CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x61, + CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x62, + CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63, + CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64, + CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65, + CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x66, + CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x67, + CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x68, + CB_PERF_SEL_CC_CACHE_STALL = 0x69, + CB_PERF_SEL_CC_CACHE_FLUSH = 0x6a, + CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x6b, + CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x6c, + CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x6d, + CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x6e, + CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x6f, + CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x70, + CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x71, + CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x72, + CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x73, + CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x74, + CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x75, + CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x76, + CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x77, + CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x78, + CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x79, + CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x7a, + CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x7b, + CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x7c, + CB_PERF_SEL_CM_MC_READ_REQUEST = 0x7d, + CB_PERF_SEL_FC_MC_READ_REQUEST = 0x7e, + CB_PERF_SEL_CC_MC_READ_REQUEST = 0x7f, + CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x80, + CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x81, + CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x82, + CB_PERF_SEL_CM_TQ_FULL = 0x83, + CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x84, + CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x85, + CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x86, + CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x87, + CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x88, + CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x89, + CB_PERF_SEL_CC_SF_FULL = 0x8a, + CB_PERF_SEL_CC_RB_FULL = 0x8b, + CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x8c, + CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x8d, + CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x8e, + CB_PERF_SEL_EVENT = 0x8f, + CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x90, + CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x91, + CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x92, + CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x93, + CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x94, + CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x95, + CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x96, + CB_PERF_SEL_CC_SURFACE_SYNC = 0x97, + CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x98, + CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x99, + CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x9a, + CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x9b, + CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x9c, + CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x9d, + CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x9e, + CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x9f, + CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0xa0, + CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0xa1, + CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0xa2, + CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0xa3, + CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0xa4, + CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0xa5, + CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0xa6, + CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0xa7, + CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0xa8, + CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0xa9, + CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0xaa, + CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0xab, + CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0xac, + CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0xad, + CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0xae, + CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0xaf, + CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0xb0, + CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0xb1, + CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0xb2, + CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0xb3, + CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0xb4, + CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0xb5, + CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0xb6, + CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0xb7, + CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0xb8, + CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0xb9, + CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0xba, + CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0xbb, + CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0xbc, + CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0xbd, + CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0xbe, + CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0xbf, + CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0xc0, + CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0xc1, + CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0xc2, + CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0xc3, + CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0xc4, + CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0xc5, + CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0xc6, + CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0xc7, + CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0xc8, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0xc9, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0xca, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0xcb, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0xcc, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0xcd, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0xce, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0xcf, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0xd0, + CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0xd1, + CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0xd2, + CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0xd3, + CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd4, + CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd5, + CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0xd6, + CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0xd7, + CB_PERF_SEL_DRAWN_BUSY = 0xd8, + CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0xd9, + CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0xda, + CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0xdb, + CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0xdc, + CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xdd, + CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0xde, + CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0xdf, + CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0xe0, + CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe1, +} CBPerfSel; +typedef enum CBPerfOpFilterSel { + CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x0, + CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x1, + CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2, + CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x3, + CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x4, + CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5, +} CBPerfOpFilterSel; +typedef enum CBPerfClearFilterSel { + CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x0, + CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x1, +} CBPerfClearFilterSel; +typedef enum CP_RING_ID { + RINGID0 = 0x0, + RINGID1 = 0x1, + RINGID2 = 0x2, + RINGID3 = 0x3, +} CP_RING_ID; +typedef enum CP_PIPE_ID { + PIPE_ID0 = 0x0, + PIPE_ID1 = 0x1, + PIPE_ID2 = 0x2, + PIPE_ID3 = 0x3, +} CP_PIPE_ID; +typedef enum CP_ME_ID { + ME_ID0 = 0x0, + ME_ID1 = 0x1, + ME_ID2 = 0x2, + ME_ID3 = 0x3, +} CP_ME_ID; +typedef enum SPM_PERFMON_STATE { + STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x0, + STRM_PERFMON_STATE_START_COUNTING = 0x1, + STRM_PERFMON_STATE_STOP_COUNTING = 0x2, + STRM_PERFMON_STATE_RESERVED_3 = 0x3, + STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, + STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, +} SPM_PERFMON_STATE; +typedef enum CP_PERFMON_STATE { + CP_PERFMON_STATE_DISABLE_AND_RESET = 0x0, + CP_PERFMON_STATE_START_COUNTING = 0x1, + CP_PERFMON_STATE_STOP_COUNTING = 0x2, + CP_PERFMON_STATE_RESERVED_3 = 0x3, + CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, + CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, +} CP_PERFMON_STATE; +typedef enum CP_PERFMON_ENABLE_MODE { + CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x0, + CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x1, + CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2, + CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x3, +} CP_PERFMON_ENABLE_MODE; +typedef enum CPG_PERFCOUNT_SEL { + CPG_PERF_SEL_ALWAYS_COUNT = 0x0, + CPG_PERF_SEL_RBIU_FIFO_FULL = 0x1, + CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2, + CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x3, + CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x4, + CPG_PERF_SEL_ME_PARSER_BUSY = 0x5, + CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x6, + CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x7, + CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x8, + CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x9, + CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa, + CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0xb, + CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0xc, + CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0xd, + CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0xe, + CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0xf, + CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x10, + CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x11, + CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x12, + CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x13, + CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x14, + CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x15, + CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x16, + CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x17, + CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x18, + CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x19, + CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x1a, + CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x1b, + CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x1c, + CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d, + CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x1e, + CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x1f, + CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x20, + CPG_PERF_SEL_REGISTER_CLK_VALID = 0x21, + CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x22, + CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x23, + CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x24, + CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x25, + CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x26, + CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x27, + CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x28, + CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x29, + CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x2a, + CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x2b, + CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x2c, + CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x2d, +} CPG_PERFCOUNT_SEL; +typedef enum CPF_PERFCOUNT_SEL { + CPF_PERF_SEL_ALWAYS_COUNT = 0x0, + CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x1, + CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2, + CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x3, + CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x4, + CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x5, + CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x6, + CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x7, + CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x8, + CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x9, + CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa, + CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0xb, + CPF_PERF_SEL_GRBM_DWORDS_SENT = 0xc, + CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0xd, + CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0xe, + CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0xf, + CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x10, +} CPF_PERFCOUNT_SEL; +typedef enum CPC_PERFCOUNT_SEL { + CPC_PERF_SEL_ALWAYS_COUNT = 0x0, + CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x1, + CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2, + CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x3, + CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x4, + CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x5, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x6, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x7, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x8, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x9, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa, + CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0xb, + CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0xc, + CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0xd, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0xe, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0xf, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x10, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x11, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x12, + CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x13, + CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x14, + CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x15, +} CPC_PERFCOUNT_SEL; +typedef enum CP_ALPHA_TAG_RAM_SEL { + CPG_TAG_RAM = 0x0, + CPC_TAG_RAM = 0x1, + CPF_TAG_RAM = 0x2, + RSV_TAG_RAM = 0x3, +} CP_ALPHA_TAG_RAM_SEL; +#define SEM_ECC_ERROR 0x0 +#define SEM_RESERVED 0x1 +#define SEM_FAILED 0x2 +#define SEM_PASSED 0x3 +#define IQ_QUEUE_SLEEP 0x0 +#define IQ_OFFLOAD_RETRY 0x1 +#define IQ_SCH_WAVE_MSG 0x2 +#define IQ_SEM_REARM 0x3 +#define IQ_DEQUEUE_RETRY 0x4 +#define IQ_INTR_TYPE_PQ 0x0 +#define IQ_INTR_TYPE_IB 0x1 +#define IQ_INTR_TYPE_MQD 0x2 +#define VMID_SZ 0x4 +#define CONFIG_SPACE_START 0x2000 +#define CONFIG_SPACE_END 0x9fff +#define CONFIG_SPACE1_START 0x2000 +#define CONFIG_SPACE1_END 0x2bff +#define CONFIG_SPACE2_START 0x3000 +#define CONFIG_SPACE2_END 0x9fff +#define UCONFIG_SPACE_START 0xc000 +#define UCONFIG_SPACE_END 0xffff +#define PERSISTENT_SPACE_START 0x2c00 +#define PERSISTENT_SPACE_END 0x2fff +#define CONTEXT_SPACE_START 0xa000 +#define CONTEXT_SPACE_END 0xbfff +typedef enum ForceControl { + FORCE_OFF = 0x0, + FORCE_ENABLE = 0x1, + FORCE_DISABLE = 0x2, + FORCE_RESERVED = 0x3, +} ForceControl; +typedef enum ZSamplePosition { + Z_SAMPLE_CENTER = 0x0, + Z_SAMPLE_CENTROID = 0x1, +} ZSamplePosition; +typedef enum ZOrder { + LATE_Z = 0x0, + EARLY_Z_THEN_LATE_Z = 0x1, + RE_Z = 0x2, + EARLY_Z_THEN_RE_Z = 0x3, +} ZOrder; +typedef enum ZpassControl { + ZPASS_DISABLE = 0x0, + ZPASS_SAMPLES = 0x1, + ZPASS_PIXELS = 0x2, +} ZpassControl; +typedef enum ZModeForce { + NO_FORCE = 0x0, + FORCE_EARLY_Z = 0x1, + FORCE_LATE_Z = 0x2, + FORCE_RE_Z = 0x3, +} ZModeForce; +typedef enum ZLimitSumm { + FORCE_SUMM_OFF = 0x0, + FORCE_SUMM_MINZ = 0x1, + FORCE_SUMM_MAXZ = 0x2, + FORCE_SUMM_BOTH = 0x3, +} ZLimitSumm; +typedef enum CompareFrag { + FRAG_NEVER = 0x0, + FRAG_LESS = 0x1, + FRAG_EQUAL = 0x2, + FRAG_LEQUAL = 0x3, + FRAG_GREATER = 0x4, + FRAG_NOTEQUAL = 0x5, + FRAG_GEQUAL = 0x6, + FRAG_ALWAYS = 0x7, +} CompareFrag; +typedef enum StencilOp { + STENCIL_KEEP = 0x0, + STENCIL_ZERO = 0x1, + STENCIL_ONES = 0x2, + STENCIL_REPLACE_TEST = 0x3, + STENCIL_REPLACE_OP = 0x4, + STENCIL_ADD_CLAMP = 0x5, + STENCIL_SUB_CLAMP = 0x6, + STENCIL_INVERT = 0x7, + STENCIL_ADD_WRAP = 0x8, + STENCIL_SUB_WRAP = 0x9, + STENCIL_AND = 0xa, + STENCIL_OR = 0xb, + STENCIL_XOR = 0xc, + STENCIL_NAND = 0xd, + STENCIL_NOR = 0xe, + STENCIL_XNOR = 0xf, +} StencilOp; +typedef enum ConservativeZExport { + EXPORT_ANY_Z = 0x0, + EXPORT_LESS_THAN_Z = 0x1, + EXPORT_GREATER_THAN_Z = 0x2, + EXPORT_RESERVED = 0x3, +} ConservativeZExport; +typedef enum DbPSLControl { + PSLC_AUTO = 0x0, + PSLC_ON_HANG_ONLY = 0x1, + PSLC_ASAP = 0x2, + PSLC_COUNTDOWN = 0x3, +} DbPSLControl; +typedef enum PerfCounter_Vals { + DB_PERF_SEL_SC_DB_tile_sends = 0x0, + DB_PERF_SEL_SC_DB_tile_busy = 0x1, + DB_PERF_SEL_SC_DB_tile_stalls = 0x2, + DB_PERF_SEL_SC_DB_tile_events = 0x3, + DB_PERF_SEL_SC_DB_tile_tiles = 0x4, + DB_PERF_SEL_SC_DB_tile_covered = 0x5, + DB_PERF_SEL_hiz_tc_read_starved = 0x6, + DB_PERF_SEL_hiz_tc_write_stall = 0x7, + DB_PERF_SEL_hiz_qtiles_culled = 0x8, + DB_PERF_SEL_his_qtiles_culled = 0x9, + DB_PERF_SEL_DB_SC_tile_sends = 0xa, + DB_PERF_SEL_DB_SC_tile_busy = 0xb, + DB_PERF_SEL_DB_SC_tile_stalls = 0xc, + DB_PERF_SEL_DB_SC_tile_df_stalls = 0xd, + DB_PERF_SEL_DB_SC_tile_tiles = 0xe, + DB_PERF_SEL_DB_SC_tile_culled = 0xf, + DB_PERF_SEL_DB_SC_tile_hier_kill = 0x10, + DB_PERF_SEL_DB_SC_tile_fast_ops = 0x11, + DB_PERF_SEL_DB_SC_tile_no_ops = 0x12, + DB_PERF_SEL_DB_SC_tile_tile_rate = 0x13, + DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x14, + DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x15, + DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x16, + DB_PERF_SEL_SC_DB_quad_sends = 0x17, + DB_PERF_SEL_SC_DB_quad_busy = 0x18, + DB_PERF_SEL_SC_DB_quad_squads = 0x19, + DB_PERF_SEL_SC_DB_quad_tiles = 0x1a, + DB_PERF_SEL_SC_DB_quad_pixels = 0x1b, + DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x1c, + DB_PERF_SEL_DB_SC_quad_sends = 0x1d, + DB_PERF_SEL_DB_SC_quad_busy = 0x1e, + DB_PERF_SEL_DB_SC_quad_stalls = 0x1f, + DB_PERF_SEL_DB_SC_quad_tiles = 0x20, + DB_PERF_SEL_DB_SC_quad_lit_quad = 0x21, + DB_PERF_SEL_DB_CB_tile_sends = 0x22, + DB_PERF_SEL_DB_CB_tile_busy = 0x23, + DB_PERF_SEL_DB_CB_tile_stalls = 0x24, + DB_PERF_SEL_SX_DB_quad_sends = 0x25, + DB_PERF_SEL_SX_DB_quad_busy = 0x26, + DB_PERF_SEL_SX_DB_quad_stalls = 0x27, + DB_PERF_SEL_SX_DB_quad_quads = 0x28, + DB_PERF_SEL_SX_DB_quad_pixels = 0x29, + DB_PERF_SEL_SX_DB_quad_exports = 0x2a, + DB_PERF_SEL_SH_quads_outstanding_sum = 0x2b, + DB_PERF_SEL_DB_CB_lquad_sends = 0x2c, + DB_PERF_SEL_DB_CB_lquad_busy = 0x2d, + DB_PERF_SEL_DB_CB_lquad_stalls = 0x2e, + DB_PERF_SEL_DB_CB_lquad_quads = 0x2f, + DB_PERF_SEL_tile_rd_sends = 0x30, + DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x31, + DB_PERF_SEL_quad_rd_sends = 0x32, + DB_PERF_SEL_quad_rd_busy = 0x33, + DB_PERF_SEL_quad_rd_mi_stall = 0x34, + DB_PERF_SEL_quad_rd_rw_collision = 0x35, + DB_PERF_SEL_quad_rd_tag_stall = 0x36, + DB_PERF_SEL_quad_rd_32byte_reqs = 0x37, + DB_PERF_SEL_quad_rd_panic = 0x38, + DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x39, + DB_PERF_SEL_quad_rdret_sends = 0x3a, + DB_PERF_SEL_quad_rdret_busy = 0x3b, + DB_PERF_SEL_tile_wr_sends = 0x3c, + DB_PERF_SEL_tile_wr_acks = 0x3d, + DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x3e, + DB_PERF_SEL_quad_wr_sends = 0x3f, + DB_PERF_SEL_quad_wr_busy = 0x40, + DB_PERF_SEL_quad_wr_mi_stall = 0x41, + DB_PERF_SEL_quad_wr_coherency_stall = 0x42, + DB_PERF_SEL_quad_wr_acks = 0x43, + DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x44, + DB_PERF_SEL_Tile_Cache_misses = 0x45, + DB_PERF_SEL_Tile_Cache_hits = 0x46, + DB_PERF_SEL_Tile_Cache_flushes = 0x47, + DB_PERF_SEL_Tile_Cache_surface_stall = 0x48, + DB_PERF_SEL_Tile_Cache_starves = 0x49, + DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x4a, + DB_PERF_SEL_tcp_dispatcher_reads = 0x4b, + DB_PERF_SEL_tcp_prefetcher_reads = 0x4c, + DB_PERF_SEL_tcp_preloader_reads = 0x4d, + DB_PERF_SEL_tcp_dispatcher_flushes = 0x4e, + DB_PERF_SEL_tcp_prefetcher_flushes = 0x4f, + DB_PERF_SEL_tcp_preloader_flushes = 0x50, + DB_PERF_SEL_Depth_Tile_Cache_sends = 0x51, + DB_PERF_SEL_Depth_Tile_Cache_busy = 0x52, + DB_PERF_SEL_Depth_Tile_Cache_starves = 0x53, + DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x54, + DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x55, + DB_PERF_SEL_Depth_Tile_Cache_misses = 0x56, + DB_PERF_SEL_Depth_Tile_Cache_hits = 0x57, + DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x58, + DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x59, + DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x5a, + DB_PERF_SEL_Depth_Tile_Cache_event = 0x5b, + DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x5c, + DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x5d, + DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x5e, + DB_PERF_SEL_Stencil_Cache_misses = 0x5f, + DB_PERF_SEL_Stencil_Cache_hits = 0x60, + DB_PERF_SEL_Stencil_Cache_flushes = 0x61, + DB_PERF_SEL_Stencil_Cache_starves = 0x62, + DB_PERF_SEL_Stencil_Cache_frees = 0x63, + DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x64, + DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x65, + DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x66, + DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x67, + DB_PERF_SEL_Z_Cache_pmask_misses = 0x68, + DB_PERF_SEL_Z_Cache_pmask_hits = 0x69, + DB_PERF_SEL_Z_Cache_pmask_flushes = 0x6a, + DB_PERF_SEL_Z_Cache_pmask_starves = 0x6b, + DB_PERF_SEL_Z_Cache_frees = 0x6c, + DB_PERF_SEL_Plane_Cache_misses = 0x6d, + DB_PERF_SEL_Plane_Cache_hits = 0x6e, + DB_PERF_SEL_Plane_Cache_flushes = 0x6f, + DB_PERF_SEL_Plane_Cache_starves = 0x70, + DB_PERF_SEL_Plane_Cache_frees = 0x71, + DB_PERF_SEL_flush_expanded_stencil = 0x72, + DB_PERF_SEL_flush_compressed_stencil = 0x73, + DB_PERF_SEL_flush_single_stencil = 0x74, + DB_PERF_SEL_planes_flushed = 0x75, + DB_PERF_SEL_flush_1plane = 0x76, + DB_PERF_SEL_flush_2plane = 0x77, + DB_PERF_SEL_flush_3plane = 0x78, + DB_PERF_SEL_flush_4plane = 0x79, + DB_PERF_SEL_flush_5plane = 0x7a, + DB_PERF_SEL_flush_6plane = 0x7b, + DB_PERF_SEL_flush_7plane = 0x7c, + DB_PERF_SEL_flush_8plane = 0x7d, + DB_PERF_SEL_flush_9plane = 0x7e, + DB_PERF_SEL_flush_10plane = 0x7f, + DB_PERF_SEL_flush_11plane = 0x80, + DB_PERF_SEL_flush_12plane = 0x81, + DB_PERF_SEL_flush_13plane = 0x82, + DB_PERF_SEL_flush_14plane = 0x83, + DB_PERF_SEL_flush_15plane = 0x84, + DB_PERF_SEL_flush_16plane = 0x85, + DB_PERF_SEL_flush_expanded_z = 0x86, + DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x87, + DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x88, + DB_PERF_SEL_dk_tile_sends = 0x89, + DB_PERF_SEL_dk_tile_busy = 0x8a, + DB_PERF_SEL_dk_tile_quad_starves = 0x8b, + DB_PERF_SEL_dk_tile_stalls = 0x8c, + DB_PERF_SEL_dk_squad_sends = 0x8d, + DB_PERF_SEL_dk_squad_busy = 0x8e, + DB_PERF_SEL_dk_squad_stalls = 0x8f, + DB_PERF_SEL_Op_Pipe_Busy = 0x90, + DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x91, + DB_PERF_SEL_qc_busy = 0x92, + DB_PERF_SEL_qc_xfc = 0x93, + DB_PERF_SEL_qc_conflicts = 0x94, + DB_PERF_SEL_qc_full_stall = 0x95, + DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x96, + DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x97, + DB_PERF_SEL_tsc_insert_summarize_stall = 0x98, + DB_PERF_SEL_tl_busy = 0x99, + DB_PERF_SEL_tl_dtc_read_starved = 0x9a, + DB_PERF_SEL_tl_z_fetch_stall = 0x9b, + DB_PERF_SEL_tl_stencil_stall = 0x9c, + DB_PERF_SEL_tl_z_decompress_stall = 0x9d, + DB_PERF_SEL_tl_stencil_locked_stall = 0x9e, + DB_PERF_SEL_tl_events = 0x9f, + DB_PERF_SEL_tl_summarize_squads = 0xa0, + DB_PERF_SEL_tl_flush_expand_squads = 0xa1, + DB_PERF_SEL_tl_expand_squads = 0xa2, + DB_PERF_SEL_tl_preZ_squads = 0xa3, + DB_PERF_SEL_tl_postZ_squads = 0xa4, + DB_PERF_SEL_tl_preZ_noop_squads = 0xa5, + DB_PERF_SEL_tl_postZ_noop_squads = 0xa6, + DB_PERF_SEL_tl_tile_ops = 0xa7, + DB_PERF_SEL_tl_in_xfc = 0xa8, + DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0xa9, + DB_PERF_SEL_tl_in_fast_z_stall = 0xaa, + DB_PERF_SEL_tl_out_xfc = 0xab, + DB_PERF_SEL_tl_out_squads = 0xac, + DB_PERF_SEL_zf_plane_multicycle = 0xad, + DB_PERF_SEL_PostZ_Samples_passing_Z = 0xae, + DB_PERF_SEL_PostZ_Samples_failing_Z = 0xaf, + DB_PERF_SEL_PostZ_Samples_failing_S = 0xb0, + DB_PERF_SEL_PreZ_Samples_passing_Z = 0xb1, + DB_PERF_SEL_PreZ_Samples_failing_Z = 0xb2, + DB_PERF_SEL_PreZ_Samples_failing_S = 0xb3, + DB_PERF_SEL_ts_tc_update_stall = 0xb4, + DB_PERF_SEL_sc_kick_start = 0xb5, + DB_PERF_SEL_sc_kick_end = 0xb6, + DB_PERF_SEL_clock_reg_active = 0xb7, + DB_PERF_SEL_clock_main_active = 0xb8, + DB_PERF_SEL_clock_mem_export_active = 0xb9, + DB_PERF_SEL_esr_ps_out_busy = 0xba, + DB_PERF_SEL_esr_ps_lqf_busy = 0xbb, + DB_PERF_SEL_esr_ps_lqf_stall = 0xbc, + DB_PERF_SEL_etr_out_send = 0xbd, + DB_PERF_SEL_etr_out_busy = 0xbe, + DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0xbf, + DB_PERF_SEL_etr_out_cb_tile_stall = 0xc0, + DB_PERF_SEL_etr_out_esr_stall = 0xc1, + DB_PERF_SEL_esr_ps_sqq_busy = 0xc2, + DB_PERF_SEL_esr_ps_sqq_stall = 0xc3, + DB_PERF_SEL_esr_eot_fwd_busy = 0xc4, + DB_PERF_SEL_esr_eot_fwd_holding_squad = 0xc5, + DB_PERF_SEL_esr_eot_fwd_forward = 0xc6, + DB_PERF_SEL_esr_sqq_zi_busy = 0xc7, + DB_PERF_SEL_esr_sqq_zi_stall = 0xc8, + DB_PERF_SEL_postzl_sq_pt_busy = 0xc9, + DB_PERF_SEL_postzl_sq_pt_stall = 0xca, + DB_PERF_SEL_postzl_se_busy = 0xcb, + DB_PERF_SEL_postzl_se_stall = 0xcc, + DB_PERF_SEL_postzl_partial_launch = 0xcd, + DB_PERF_SEL_postzl_full_launch = 0xce, + DB_PERF_SEL_postzl_partial_waiting = 0xcf, + DB_PERF_SEL_postzl_tile_mem_stall = 0xd0, + DB_PERF_SEL_postzl_tile_init_stall = 0xd1, + DB_PEFF_SEL_prezl_tile_mem_stall = 0xd2, + DB_PERF_SEL_prezl_tile_init_stall = 0xd3, + DB_PERF_SEL_dtt_sm_clash_stall = 0xd4, + DB_PERF_SEL_dtt_sm_slot_stall = 0xd5, + DB_PERF_SEL_dtt_sm_miss_stall = 0xd6, + DB_PERF_SEL_mi_rdreq_busy = 0xd7, + DB_PERF_SEL_mi_rdreq_stall = 0xd8, + DB_PERF_SEL_mi_wrreq_busy = 0xd9, + DB_PERF_SEL_mi_wrreq_stall = 0xda, + DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0xdb, + DB_PERF_SEL_dkg_tile_rate_tile = 0xdc, + DB_PERF_SEL_prezl_src_in_sends = 0xdd, + DB_PERF_SEL_prezl_src_in_stall = 0xde, + DB_PERF_SEL_prezl_src_in_squads = 0xdf, + DB_PERF_SEL_prezl_src_in_squads_unrolled = 0xe0, + DB_PERF_SEL_prezl_src_in_tile_rate = 0xe1, + DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0xe2, + DB_PERF_SEL_prezl_src_out_stall = 0xe3, + DB_PERF_SEL_postzl_src_in_sends = 0xe4, + DB_PERF_SEL_postzl_src_in_stall = 0xe5, + DB_PERF_SEL_postzl_src_in_squads = 0xe6, + DB_PERF_SEL_postzl_src_in_squads_unrolled = 0xe7, + DB_PERF_SEL_postzl_src_in_tile_rate = 0xe8, + DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0xe9, + DB_PERF_SEL_postzl_src_out_stall = 0xea, + DB_PERF_SEL_esr_ps_src_in_sends = 0xeb, + DB_PERF_SEL_esr_ps_src_in_stall = 0xec, + DB_PERF_SEL_esr_ps_src_in_squads = 0xed, + DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0xee, + DB_PERF_SEL_esr_ps_src_in_tile_rate = 0xef, + DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0xf0, + DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1, + DB_PERF_SEL_esr_ps_src_out_stall = 0xf2, + DB_PERF_SEL_depth_bounds_qtiles_culled = 0xf3, + DB_PERF_SEL_PreZ_Samples_failing_DB = 0xf4, + DB_PERF_SEL_PostZ_Samples_failing_DB = 0xf5, + DB_PERF_SEL_flush_compressed = 0xf6, + DB_PERF_SEL_flush_plane_le4 = 0xf7, + DB_PERF_SEL_tiles_z_fully_summarized = 0xf8, + DB_PERF_SEL_tiles_stencil_fully_summarized = 0xf9, + DB_PERF_SEL_tiles_z_clear_on_expclear = 0xfa, + DB_PERF_SEL_tiles_s_clear_on_expclear = 0xfb, + DB_PERF_SEL_tiles_decomp_on_expclear = 0xfc, + DB_PERF_SEL_tiles_compressed_to_decompressed = 0xfd, + DB_PERF_SEL_Op_Pipe_Prez_Busy = 0xfe, + DB_PERF_SEL_Op_Pipe_Postz_Busy = 0xff, + DB_PERF_SEL_di_dt_stall = 0x100, +} PerfCounter_Vals; +typedef enum RingCounterControl { + COUNTER_RING_SPLIT = 0x0, + COUNTER_RING_0 = 0x1, + COUNTER_RING_1 = 0x2, +} RingCounterControl; +typedef enum PixelPipeCounterId { + PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x0, + PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x1, + PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2, + PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x3, + PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x4, + PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x5, + PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x6, + PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x7, +} PixelPipeCounterId; +typedef enum PixelPipeStride { + PIXEL_PIPE_STRIDE_32_BITS = 0x0, + PIXEL_PIPE_STRIDE_64_BITS = 0x1, + PIXEL_PIPE_STRIDE_128_BITS = 0x2, + PIXEL_PIPE_STRIDE_256_BITS = 0x3, +} PixelPipeStride; +typedef enum GB_EDC_DED_MODE { + GB_EDC_DED_MODE_LOG = 0x0, + GB_EDC_DED_MODE_HALT = 0x1, + GB_EDC_DED_MODE_INT_HALT = 0x2, +} GB_EDC_DED_MODE; +#define GB_TILING_CONFIG_TABLE_SIZE 0x20 +#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x10 +typedef enum GRBM_PERF_SEL { + GRBM_PERF_SEL_COUNT = 0x0, + GRBM_PERF_SEL_USER_DEFINED = 0x1, + GRBM_PERF_SEL_GUI_ACTIVE = 0x2, + GRBM_PERF_SEL_CP_BUSY = 0x3, + GRBM_PERF_SEL_CP_COHER_BUSY = 0x4, + GRBM_PERF_SEL_CP_DMA_BUSY = 0x5, + GRBM_PERF_SEL_CB_BUSY = 0x6, + GRBM_PERF_SEL_DB_BUSY = 0x7, + GRBM_PERF_SEL_PA_BUSY = 0x8, + GRBM_PERF_SEL_SC_BUSY = 0x9, + GRBM_PERF_SEL_RESERVED_6 = 0xa, + GRBM_PERF_SEL_SPI_BUSY = 0xb, + GRBM_PERF_SEL_SX_BUSY = 0xc, + GRBM_PERF_SEL_TA_BUSY = 0xd, + GRBM_PERF_SEL_CB_CLEAN = 0xe, + GRBM_PERF_SEL_DB_CLEAN = 0xf, + GRBM_PERF_SEL_RESERVED_5 = 0x10, + GRBM_PERF_SEL_VGT_BUSY = 0x11, + GRBM_PERF_SEL_RESERVED_4 = 0x12, + GRBM_PERF_SEL_RESERVED_3 = 0x13, + GRBM_PERF_SEL_RESERVED_2 = 0x14, + GRBM_PERF_SEL_RESERVED_1 = 0x15, + GRBM_PERF_SEL_RESERVED_0 = 0x16, + GRBM_PERF_SEL_IA_BUSY = 0x17, + GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x18, + GRBM_PERF_SEL_GDS_BUSY = 0x19, + GRBM_PERF_SEL_BCI_BUSY = 0x1a, + GRBM_PERF_SEL_RLC_BUSY = 0x1b, + GRBM_PERF_SEL_TC_BUSY = 0x1c, + GRBM_PERF_SEL_CPG_BUSY = 0x1d, + GRBM_PERF_SEL_CPC_BUSY = 0x1e, + GRBM_PERF_SEL_CPF_BUSY = 0x1f, + GRBM_PERF_SEL_WD_BUSY = 0x20, + GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x21, +} GRBM_PERF_SEL; +typedef enum GRBM_SE0_PERF_SEL { + GRBM_SE0_PERF_SEL_COUNT = 0x0, + GRBM_SE0_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE0_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE0_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE0_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE0_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE0_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE0_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE0_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE0_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE0_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE0_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE0_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE0_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE0_PERF_SEL; +typedef enum GRBM_SE1_PERF_SEL { + GRBM_SE1_PERF_SEL_COUNT = 0x0, + GRBM_SE1_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE1_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE1_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE1_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE1_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE1_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE1_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE1_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE1_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE1_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE1_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE1_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE1_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE1_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE1_PERF_SEL; +typedef enum GRBM_SE2_PERF_SEL { + GRBM_SE2_PERF_SEL_COUNT = 0x0, + GRBM_SE2_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE2_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE2_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE2_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE2_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE2_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE2_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE2_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE2_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE2_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE2_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE2_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE2_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE2_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE2_PERF_SEL; +typedef enum GRBM_SE3_PERF_SEL { + GRBM_SE3_PERF_SEL_COUNT = 0x0, + GRBM_SE3_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE3_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE3_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE3_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE3_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE3_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE3_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE3_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE3_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE3_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE3_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE3_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE3_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE3_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE3_PERF_SEL; +typedef enum SU_PERFCNT_SEL { + PERF_PAPC_PASX_REQ = 0x0, + PERF_PAPC_PASX_DISABLE_PIPE = 0x1, + PERF_PAPC_PASX_FIRST_VECTOR = 0x2, + PERF_PAPC_PASX_SECOND_VECTOR = 0x3, + PERF_PAPC_PASX_FIRST_DEAD = 0x4, + PERF_PAPC_PASX_SECOND_DEAD = 0x5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x7, + PERF_PAPC_PA_INPUT_PRIM = 0x8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 0x9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 0xa, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0xb, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 0xc, + PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0xd, + PERF_PAPC_CLPR_CULL_PRIM = 0xe, + PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0xf, + PERF_PAPC_CLPR_VV_CULL_PRIM = 0x10, + PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x11, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x12, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x13, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x14, + PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x15, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x16, + PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x17, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x18, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x19, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x1a, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x1b, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x1c, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x1e, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x1f, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x20, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x21, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x22, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x23, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x24, + PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x25, + PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x26, + PERF_PAPC_CLSM_NULL_PRIM = 0x27, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x28, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x29, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x2a, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x2b, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x2c, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x2d, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x2e, + PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x2f, + PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x30, + PERF_PAPC_SU_INPUT_PRIM = 0x31, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x32, + PERF_PAPC_SU_INPUT_NULL_PRIM = 0x33, + PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x34, + PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x35, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x36, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x37, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x38, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x39, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x3a, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x3b, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x3c, + PERF_PAPC_SU_OUTPUT_PRIM = 0x3d, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x3e, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x3f, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x40, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x41, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x42, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x43, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x44, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x45, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x46, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x47, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x48, + PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x49, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x4a, + PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x4b, + PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x4c, + PERF_PAPC_PASX_REQ_IDLE = 0x4d, + PERF_PAPC_PASX_REQ_BUSY = 0x4e, + PERF_PAPC_PASX_REQ_STALLED = 0x4f, + PERF_PAPC_PASX_REC_IDLE = 0x50, + PERF_PAPC_PASX_REC_BUSY = 0x51, + PERF_PAPC_PASX_REC_STARVED_SX = 0x52, + PERF_PAPC_PASX_REC_STALLED = 0x53, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x54, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x55, + PERF_PAPC_CCGSM_IDLE = 0x56, + PERF_PAPC_CCGSM_BUSY = 0x57, + PERF_PAPC_CCGSM_STALLED = 0x58, + PERF_PAPC_CLPRIM_IDLE = 0x59, + PERF_PAPC_CLPRIM_BUSY = 0x5a, + PERF_PAPC_CLPRIM_STALLED = 0x5b, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x5c, + PERF_PAPC_CLIPSM_IDLE = 0x5d, + PERF_PAPC_CLIPSM_BUSY = 0x5e, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x5f, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x60, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x61, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x62, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x63, + PERF_PAPC_CLIPGA_IDLE = 0x64, + PERF_PAPC_CLIPGA_BUSY = 0x65, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x66, + PERF_PAPC_CLIPGA_STALLED = 0x67, + PERF_PAPC_CLIP_IDLE = 0x68, + PERF_PAPC_CLIP_BUSY = 0x69, + PERF_PAPC_SU_IDLE = 0x6a, + PERF_PAPC_SU_BUSY = 0x6b, + PERF_PAPC_SU_STARVED_CLIP = 0x6c, + PERF_PAPC_SU_STALLED_SC = 0x6d, + PERF_PAPC_CL_DYN_SCLK_VLD = 0x6e, + PERF_PAPC_SU_DYN_SCLK_VLD = 0x6f, + PERF_PAPC_PA_REG_SCLK_VLD = 0x70, + PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x71, + PERF_PAPC_PASX_SE0_REQ = 0x72, + PERF_PAPC_PASX_SE1_REQ = 0x73, + PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x74, + PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x75, + PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x76, + PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x77, + PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x78, + PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x79, + PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x7a, + PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x7b, + PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x7c, + PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x7d, + PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x7e, + PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x7f, + PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x80, + PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x81, + PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x82, + PERF_PAPC_SU_SE0_STALLED_SC = 0x83, + PERF_PAPC_SU_SE1_STALLED_SC = 0x84, + PERF_PAPC_SU_SE01_STALLED_SC = 0x85, + PERF_PAPC_CLSM_CLIPPING_PRIM = 0x86, + PERF_PAPC_SU_CULLED_PRIM = 0x87, + PERF_PAPC_SU_OUTPUT_EOPG = 0x88, + PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x89, + PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x8a, + PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x8b, + PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x8c, + PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x8d, + PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x8e, + PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x8f, + PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x90, + PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x91, + PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x92, + PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x93, + PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x94, + PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x95, + PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x96, + PERF_PAPC_SU_SE2_STALLED_SC = 0x97, + PERF_PAPC_SU_SE3_STALLED_SC = 0x98, +} SU_PERFCNT_SEL; +typedef enum SC_PERFCNT_SEL { + SC_SRPS_WINDOW_VALID = 0x0, + SC_PSSW_WINDOW_VALID = 0x1, + SC_TPQZ_WINDOW_VALID = 0x2, + SC_QZQP_WINDOW_VALID = 0x3, + SC_TRPK_WINDOW_VALID = 0x4, + SC_SRPS_WINDOW_VALID_BUSY = 0x5, + SC_PSSW_WINDOW_VALID_BUSY = 0x6, + SC_TPQZ_WINDOW_VALID_BUSY = 0x7, + SC_QZQP_WINDOW_VALID_BUSY = 0x8, + SC_TRPK_WINDOW_VALID_BUSY = 0x9, + SC_STARVED_BY_PA = 0xa, + SC_STALLED_BY_PRIMFIFO = 0xb, + SC_STALLED_BY_DB_TILE = 0xc, + SC_STARVED_BY_DB_TILE = 0xd, + SC_STALLED_BY_TILEORDERFIFO = 0xe, + SC_STALLED_BY_TILEFIFO = 0xf, + SC_STALLED_BY_DB_QUAD = 0x10, + SC_STARVED_BY_DB_QUAD = 0x11, + SC_STALLED_BY_QUADFIFO = 0x12, + SC_STALLED_BY_BCI = 0x13, + SC_STALLED_BY_SPI = 0x14, + SC_SCISSOR_DISCARD = 0x15, + SC_BB_DISCARD = 0x16, + SC_SUPERTILE_COUNT = 0x17, + SC_SUPERTILE_PER_PRIM_H0 = 0x18, + SC_SUPERTILE_PER_PRIM_H1 = 0x19, + SC_SUPERTILE_PER_PRIM_H2 = 0x1a, + SC_SUPERTILE_PER_PRIM_H3 = 0x1b, + SC_SUPERTILE_PER_PRIM_H4 = 0x1c, + SC_SUPERTILE_PER_PRIM_H5 = 0x1d, + SC_SUPERTILE_PER_PRIM_H6 = 0x1e, + SC_SUPERTILE_PER_PRIM_H7 = 0x1f, + SC_SUPERTILE_PER_PRIM_H8 = 0x20, + SC_SUPERTILE_PER_PRIM_H9 = 0x21, + SC_SUPERTILE_PER_PRIM_H10 = 0x22, + SC_SUPERTILE_PER_PRIM_H11 = 0x23, + SC_SUPERTILE_PER_PRIM_H12 = 0x24, + SC_SUPERTILE_PER_PRIM_H13 = 0x25, + SC_SUPERTILE_PER_PRIM_H14 = 0x26, + SC_SUPERTILE_PER_PRIM_H15 = 0x27, + SC_SUPERTILE_PER_PRIM_H16 = 0x28, + SC_TILE_PER_PRIM_H0 = 0x29, + SC_TILE_PER_PRIM_H1 = 0x2a, + SC_TILE_PER_PRIM_H2 = 0x2b, + SC_TILE_PER_PRIM_H3 = 0x2c, + SC_TILE_PER_PRIM_H4 = 0x2d, + SC_TILE_PER_PRIM_H5 = 0x2e, + SC_TILE_PER_PRIM_H6 = 0x2f, + SC_TILE_PER_PRIM_H7 = 0x30, + SC_TILE_PER_PRIM_H8 = 0x31, + SC_TILE_PER_PRIM_H9 = 0x32, + SC_TILE_PER_PRIM_H10 = 0x33, + SC_TILE_PER_PRIM_H11 = 0x34, + SC_TILE_PER_PRIM_H12 = 0x35, + SC_TILE_PER_PRIM_H13 = 0x36, + SC_TILE_PER_PRIM_H14 = 0x37, + SC_TILE_PER_PRIM_H15 = 0x38, + SC_TILE_PER_PRIM_H16 = 0x39, + SC_TILE_PER_SUPERTILE_H0 = 0x3a, + SC_TILE_PER_SUPERTILE_H1 = 0x3b, + SC_TILE_PER_SUPERTILE_H2 = 0x3c, + SC_TILE_PER_SUPERTILE_H3 = 0x3d, + SC_TILE_PER_SUPERTILE_H4 = 0x3e, + SC_TILE_PER_SUPERTILE_H5 = 0x3f, + SC_TILE_PER_SUPERTILE_H6 = 0x40, + SC_TILE_PER_SUPERTILE_H7 = 0x41, + SC_TILE_PER_SUPERTILE_H8 = 0x42, + SC_TILE_PER_SUPERTILE_H9 = 0x43, + SC_TILE_PER_SUPERTILE_H10 = 0x44, + SC_TILE_PER_SUPERTILE_H11 = 0x45, + SC_TILE_PER_SUPERTILE_H12 = 0x46, + SC_TILE_PER_SUPERTILE_H13 = 0x47, + SC_TILE_PER_SUPERTILE_H14 = 0x48, + SC_TILE_PER_SUPERTILE_H15 = 0x49, + SC_TILE_PER_SUPERTILE_H16 = 0x4a, + SC_TILE_PICKED_H1 = 0x4b, + SC_TILE_PICKED_H2 = 0x4c, + SC_TILE_PICKED_H3 = 0x4d, + SC_TILE_PICKED_H4 = 0x4e, + SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x4f, + SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x50, + SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x51, + SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x52, + SC_QZ0_TILE_COUNT = 0x53, + SC_QZ1_TILE_COUNT = 0x54, + SC_QZ2_TILE_COUNT = 0x55, + SC_QZ3_TILE_COUNT = 0x56, + SC_QZ0_TILE_COVERED_COUNT = 0x57, + SC_QZ1_TILE_COVERED_COUNT = 0x58, + SC_QZ2_TILE_COVERED_COUNT = 0x59, + SC_QZ3_TILE_COVERED_COUNT = 0x5a, + SC_QZ0_TILE_NOT_COVERED_COUNT = 0x5b, + SC_QZ1_TILE_NOT_COVERED_COUNT = 0x5c, + SC_QZ2_TILE_NOT_COVERED_COUNT = 0x5d, + SC_QZ3_TILE_NOT_COVERED_COUNT = 0x5e, + SC_QZ0_QUAD_PER_TILE_H0 = 0x5f, + SC_QZ0_QUAD_PER_TILE_H1 = 0x60, + SC_QZ0_QUAD_PER_TILE_H2 = 0x61, + SC_QZ0_QUAD_PER_TILE_H3 = 0x62, + SC_QZ0_QUAD_PER_TILE_H4 = 0x63, + SC_QZ0_QUAD_PER_TILE_H5 = 0x64, + SC_QZ0_QUAD_PER_TILE_H6 = 0x65, + SC_QZ0_QUAD_PER_TILE_H7 = 0x66, + SC_QZ0_QUAD_PER_TILE_H8 = 0x67, + SC_QZ0_QUAD_PER_TILE_H9 = 0x68, + SC_QZ0_QUAD_PER_TILE_H10 = 0x69, + SC_QZ0_QUAD_PER_TILE_H11 = 0x6a, + SC_QZ0_QUAD_PER_TILE_H12 = 0x6b, + SC_QZ0_QUAD_PER_TILE_H13 = 0x6c, + SC_QZ0_QUAD_PER_TILE_H14 = 0x6d, + SC_QZ0_QUAD_PER_TILE_H15 = 0x6e, + SC_QZ0_QUAD_PER_TILE_H16 = 0x6f, + SC_QZ1_QUAD_PER_TILE_H0 = 0x70, + SC_QZ1_QUAD_PER_TILE_H1 = 0x71, + SC_QZ1_QUAD_PER_TILE_H2 = 0x72, + SC_QZ1_QUAD_PER_TILE_H3 = 0x73, + SC_QZ1_QUAD_PER_TILE_H4 = 0x74, + SC_QZ1_QUAD_PER_TILE_H5 = 0x75, + SC_QZ1_QUAD_PER_TILE_H6 = 0x76, + SC_QZ1_QUAD_PER_TILE_H7 = 0x77, + SC_QZ1_QUAD_PER_TILE_H8 = 0x78, + SC_QZ1_QUAD_PER_TILE_H9 = 0x79, + SC_QZ1_QUAD_PER_TILE_H10 = 0x7a, + SC_QZ1_QUAD_PER_TILE_H11 = 0x7b, + SC_QZ1_QUAD_PER_TILE_H12 = 0x7c, + SC_QZ1_QUAD_PER_TILE_H13 = 0x7d, + SC_QZ1_QUAD_PER_TILE_H14 = 0x7e, + SC_QZ1_QUAD_PER_TILE_H15 = 0x7f, + SC_QZ1_QUAD_PER_TILE_H16 = 0x80, + SC_QZ2_QUAD_PER_TILE_H0 = 0x81, + SC_QZ2_QUAD_PER_TILE_H1 = 0x82, + SC_QZ2_QUAD_PER_TILE_H2 = 0x83, + SC_QZ2_QUAD_PER_TILE_H3 = 0x84, + SC_QZ2_QUAD_PER_TILE_H4 = 0x85, + SC_QZ2_QUAD_PER_TILE_H5 = 0x86, + SC_QZ2_QUAD_PER_TILE_H6 = 0x87, + SC_QZ2_QUAD_PER_TILE_H7 = 0x88, + SC_QZ2_QUAD_PER_TILE_H8 = 0x89, + SC_QZ2_QUAD_PER_TILE_H9 = 0x8a, + SC_QZ2_QUAD_PER_TILE_H10 = 0x8b, + SC_QZ2_QUAD_PER_TILE_H11 = 0x8c, + SC_QZ2_QUAD_PER_TILE_H12 = 0x8d, + SC_QZ2_QUAD_PER_TILE_H13 = 0x8e, + SC_QZ2_QUAD_PER_TILE_H14 = 0x8f, + SC_QZ2_QUAD_PER_TILE_H15 = 0x90, + SC_QZ2_QUAD_PER_TILE_H16 = 0x91, + SC_QZ3_QUAD_PER_TILE_H0 = 0x92, + SC_QZ3_QUAD_PER_TILE_H1 = 0x93, + SC_QZ3_QUAD_PER_TILE_H2 = 0x94, + SC_QZ3_QUAD_PER_TILE_H3 = 0x95, + SC_QZ3_QUAD_PER_TILE_H4 = 0x96, + SC_QZ3_QUAD_PER_TILE_H5 = 0x97, + SC_QZ3_QUAD_PER_TILE_H6 = 0x98, + SC_QZ3_QUAD_PER_TILE_H7 = 0x99, + SC_QZ3_QUAD_PER_TILE_H8 = 0x9a, + SC_QZ3_QUAD_PER_TILE_H9 = 0x9b, + SC_QZ3_QUAD_PER_TILE_H10 = 0x9c, + SC_QZ3_QUAD_PER_TILE_H11 = 0x9d, + SC_QZ3_QUAD_PER_TILE_H12 = 0x9e, + SC_QZ3_QUAD_PER_TILE_H13 = 0x9f, + SC_QZ3_QUAD_PER_TILE_H14 = 0xa0, + SC_QZ3_QUAD_PER_TILE_H15 = 0xa1, + SC_QZ3_QUAD_PER_TILE_H16 = 0xa2, + SC_QZ0_QUAD_COUNT = 0xa3, + SC_QZ1_QUAD_COUNT = 0xa4, + SC_QZ2_QUAD_COUNT = 0xa5, + SC_QZ3_QUAD_COUNT = 0xa6, + SC_P0_HIZ_TILE_COUNT = 0xa7, + SC_P1_HIZ_TILE_COUNT = 0xa8, + SC_P2_HIZ_TILE_COUNT = 0xa9, + SC_P3_HIZ_TILE_COUNT = 0xaa, + SC_P0_HIZ_QUAD_PER_TILE_H0 = 0xab, + SC_P0_HIZ_QUAD_PER_TILE_H1 = 0xac, + SC_P0_HIZ_QUAD_PER_TILE_H2 = 0xad, + SC_P0_HIZ_QUAD_PER_TILE_H3 = 0xae, + SC_P0_HIZ_QUAD_PER_TILE_H4 = 0xaf, + SC_P0_HIZ_QUAD_PER_TILE_H5 = 0xb0, + SC_P0_HIZ_QUAD_PER_TILE_H6 = 0xb1, + SC_P0_HIZ_QUAD_PER_TILE_H7 = 0xb2, + SC_P0_HIZ_QUAD_PER_TILE_H8 = 0xb3, + SC_P0_HIZ_QUAD_PER_TILE_H9 = 0xb4, + SC_P0_HIZ_QUAD_PER_TILE_H10 = 0xb5, + SC_P0_HIZ_QUAD_PER_TILE_H11 = 0xb6, + SC_P0_HIZ_QUAD_PER_TILE_H12 = 0xb7, + SC_P0_HIZ_QUAD_PER_TILE_H13 = 0xb8, + SC_P0_HIZ_QUAD_PER_TILE_H14 = 0xb9, + SC_P0_HIZ_QUAD_PER_TILE_H15 = 0xba, + SC_P0_HIZ_QUAD_PER_TILE_H16 = 0xbb, + SC_P1_HIZ_QUAD_PER_TILE_H0 = 0xbc, + SC_P1_HIZ_QUAD_PER_TILE_H1 = 0xbd, + SC_P1_HIZ_QUAD_PER_TILE_H2 = 0xbe, + SC_P1_HIZ_QUAD_PER_TILE_H3 = 0xbf, + SC_P1_HIZ_QUAD_PER_TILE_H4 = 0xc0, + SC_P1_HIZ_QUAD_PER_TILE_H5 = 0xc1, + SC_P1_HIZ_QUAD_PER_TILE_H6 = 0xc2, + SC_P1_HIZ_QUAD_PER_TILE_H7 = 0xc3, + SC_P1_HIZ_QUAD_PER_TILE_H8 = 0xc4, + SC_P1_HIZ_QUAD_PER_TILE_H9 = 0xc5, + SC_P1_HIZ_QUAD_PER_TILE_H10 = 0xc6, + SC_P1_HIZ_QUAD_PER_TILE_H11 = 0xc7, + SC_P1_HIZ_QUAD_PER_TILE_H12 = 0xc8, + SC_P1_HIZ_QUAD_PER_TILE_H13 = 0xc9, + SC_P1_HIZ_QUAD_PER_TILE_H14 = 0xca, + SC_P1_HIZ_QUAD_PER_TILE_H15 = 0xcb, + SC_P1_HIZ_QUAD_PER_TILE_H16 = 0xcc, + SC_P2_HIZ_QUAD_PER_TILE_H0 = 0xcd, + SC_P2_HIZ_QUAD_PER_TILE_H1 = 0xce, + SC_P2_HIZ_QUAD_PER_TILE_H2 = 0xcf, + SC_P2_HIZ_QUAD_PER_TILE_H3 = 0xd0, + SC_P2_HIZ_QUAD_PER_TILE_H4 = 0xd1, + SC_P2_HIZ_QUAD_PER_TILE_H5 = 0xd2, + SC_P2_HIZ_QUAD_PER_TILE_H6 = 0xd3, + SC_P2_HIZ_QUAD_PER_TILE_H7 = 0xd4, + SC_P2_HIZ_QUAD_PER_TILE_H8 = 0xd5, + SC_P2_HIZ_QUAD_PER_TILE_H9 = 0xd6, + SC_P2_HIZ_QUAD_PER_TILE_H10 = 0xd7, + SC_P2_HIZ_QUAD_PER_TILE_H11 = 0xd8, + SC_P2_HIZ_QUAD_PER_TILE_H12 = 0xd9, + SC_P2_HIZ_QUAD_PER_TILE_H13 = 0xda, + SC_P2_HIZ_QUAD_PER_TILE_H14 = 0xdb, + SC_P2_HIZ_QUAD_PER_TILE_H15 = 0xdc, + SC_P2_HIZ_QUAD_PER_TILE_H16 = 0xdd, + SC_P3_HIZ_QUAD_PER_TILE_H0 = 0xde, + SC_P3_HIZ_QUAD_PER_TILE_H1 = 0xdf, + SC_P3_HIZ_QUAD_PER_TILE_H2 = 0xe0, + SC_P3_HIZ_QUAD_PER_TILE_H3 = 0xe1, + SC_P3_HIZ_QUAD_PER_TILE_H4 = 0xe2, + SC_P3_HIZ_QUAD_PER_TILE_H5 = 0xe3, + SC_P3_HIZ_QUAD_PER_TILE_H6 = 0xe4, + SC_P3_HIZ_QUAD_PER_TILE_H7 = 0xe5, + SC_P3_HIZ_QUAD_PER_TILE_H8 = 0xe6, + SC_P3_HIZ_QUAD_PER_TILE_H9 = 0xe7, + SC_P3_HIZ_QUAD_PER_TILE_H10 = 0xe8, + SC_P3_HIZ_QUAD_PER_TILE_H11 = 0xe9, + SC_P3_HIZ_QUAD_PER_TILE_H12 = 0xea, + SC_P3_HIZ_QUAD_PER_TILE_H13 = 0xeb, + SC_P3_HIZ_QUAD_PER_TILE_H14 = 0xec, + SC_P3_HIZ_QUAD_PER_TILE_H15 = 0xed, + SC_P3_HIZ_QUAD_PER_TILE_H16 = 0xee, + SC_P0_HIZ_QUAD_COUNT = 0xef, + SC_P1_HIZ_QUAD_COUNT = 0xf0, + SC_P2_HIZ_QUAD_COUNT = 0xf1, + SC_P3_HIZ_QUAD_COUNT = 0xf2, + SC_P0_DETAIL_QUAD_COUNT = 0xf3, + SC_P1_DETAIL_QUAD_COUNT = 0xf4, + SC_P2_DETAIL_QUAD_COUNT = 0xf5, + SC_P3_DETAIL_QUAD_COUNT = 0xf6, + SC_P0_DETAIL_QUAD_WITH_1_PIX = 0xf7, + SC_P0_DETAIL_QUAD_WITH_2_PIX = 0xf8, + SC_P0_DETAIL_QUAD_WITH_3_PIX = 0xf9, + SC_P0_DETAIL_QUAD_WITH_4_PIX = 0xfa, + SC_P1_DETAIL_QUAD_WITH_1_PIX = 0xfb, + SC_P1_DETAIL_QUAD_WITH_2_PIX = 0xfc, + SC_P1_DETAIL_QUAD_WITH_3_PIX = 0xfd, + SC_P1_DETAIL_QUAD_WITH_4_PIX = 0xfe, + SC_P2_DETAIL_QUAD_WITH_1_PIX = 0xff, + SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x100, + SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x101, + SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x102, + SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x103, + SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x104, + SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105, + SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x106, + SC_EARLYZ_QUAD_COUNT = 0x107, + SC_EARLYZ_QUAD_WITH_1_PIX = 0x108, + SC_EARLYZ_QUAD_WITH_2_PIX = 0x109, + SC_EARLYZ_QUAD_WITH_3_PIX = 0x10a, + SC_EARLYZ_QUAD_WITH_4_PIX = 0x10b, + SC_PKR_QUAD_PER_ROW_H1 = 0x10c, + SC_PKR_QUAD_PER_ROW_H2 = 0x10d, + SC_PKR_QUAD_PER_ROW_H3 = 0x10e, + SC_PKR_QUAD_PER_ROW_H4 = 0x10f, + SC_PKR_END_OF_VECTOR = 0x110, + SC_PKR_CONTROL_XFER = 0x111, + SC_PKR_DBHANG_FORCE_EOV = 0x112, + SC_REG_SCLK_BUSY = 0x113, + SC_GRP0_DYN_SCLK_BUSY = 0x114, + SC_GRP1_DYN_SCLK_BUSY = 0x115, + SC_GRP2_DYN_SCLK_BUSY = 0x116, + SC_GRP3_DYN_SCLK_BUSY = 0x117, + SC_GRP4_DYN_SCLK_BUSY = 0x118, + SC_PA0_SC_DATA_FIFO_RD = 0x119, + SC_PA0_SC_DATA_FIFO_WE = 0x11a, + SC_PA1_SC_DATA_FIFO_RD = 0x11b, + SC_PA1_SC_DATA_FIFO_WE = 0x11c, + SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x11d, + SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x11e, + SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x11f, + SC_PS_ARB_STALLED_FROM_BELOW = 0x120, + SC_PS_ARB_STARVED_FROM_ABOVE = 0x121, + SC_PS_ARB_SC_BUSY = 0x122, + SC_PS_ARB_PA_SC_BUSY = 0x123, + SC_PA2_SC_DATA_FIFO_RD = 0x124, + SC_PA2_SC_DATA_FIFO_WE = 0x125, + SC_PA3_SC_DATA_FIFO_RD = 0x126, + SC_PA3_SC_DATA_FIFO_WE = 0x127, + SC_PA_SC_DEALLOC_0_0_WE = 0x128, + SC_PA_SC_DEALLOC_0_1_WE = 0x129, + SC_PA_SC_DEALLOC_1_0_WE = 0x12a, + SC_PA_SC_DEALLOC_1_1_WE = 0x12b, + SC_PA_SC_DEALLOC_2_0_WE = 0x12c, + SC_PA_SC_DEALLOC_2_1_WE = 0x12d, + SC_PA_SC_DEALLOC_3_0_WE = 0x12e, + SC_PA_SC_DEALLOC_3_1_WE = 0x12f, + SC_PA0_SC_EOP_WE = 0x130, + SC_PA0_SC_EOPG_WE = 0x131, + SC_PA0_SC_EVENT_WE = 0x132, + SC_PA1_SC_EOP_WE = 0x133, + SC_PA1_SC_EOPG_WE = 0x134, + SC_PA1_SC_EVENT_WE = 0x135, + SC_PA2_SC_EOP_WE = 0x136, + SC_PA2_SC_EOPG_WE = 0x137, + SC_PA2_SC_EVENT_WE = 0x138, + SC_PA3_SC_EOP_WE = 0x139, + SC_PA3_SC_EOPG_WE = 0x13a, + SC_PA3_SC_EVENT_WE = 0x13b, + SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x13c, + SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x13d, + SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x13e, + SC_PS_ARB_EOP_POP_SYNC_POP = 0x13f, + SC_PS_ARB_EVENT_SYNC_POP = 0x140, + SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141, + SC_PA0_SC_FPOV_WE = 0x142, + SC_PA1_SC_FPOV_WE = 0x143, + SC_PA2_SC_FPOV_WE = 0x144, + SC_PA3_SC_FPOV_WE = 0x145, + SC_PA0_SC_LPOV_WE = 0x146, + SC_PA1_SC_LPOV_WE = 0x147, + SC_PA2_SC_LPOV_WE = 0x148, + SC_PA3_SC_LPOV_WE = 0x149, + SC_SC_SPI_DEALLOC_0_0 = 0x14a, + SC_SC_SPI_DEALLOC_0_1 = 0x14b, + SC_SC_SPI_DEALLOC_0_2 = 0x14c, + SC_SC_SPI_DEALLOC_1_0 = 0x14d, + SC_SC_SPI_DEALLOC_1_1 = 0x14e, + SC_SC_SPI_DEALLOC_1_2 = 0x14f, + SC_SC_SPI_DEALLOC_2_0 = 0x150, + SC_SC_SPI_DEALLOC_2_1 = 0x151, + SC_SC_SPI_DEALLOC_2_2 = 0x152, + SC_SC_SPI_DEALLOC_3_0 = 0x153, + SC_SC_SPI_DEALLOC_3_1 = 0x154, + SC_SC_SPI_DEALLOC_3_2 = 0x155, + SC_SC_SPI_FPOV_0 = 0x156, + SC_SC_SPI_FPOV_1 = 0x157, + SC_SC_SPI_FPOV_2 = 0x158, + SC_SC_SPI_FPOV_3 = 0x159, + SC_SC_SPI_EVENT = 0x15a, + SC_PS_TS_EVENT_FIFO_PUSH = 0x15b, + SC_PS_TS_EVENT_FIFO_POP = 0x15c, + SC_PS_CTX_DONE_FIFO_PUSH = 0x15d, + SC_PS_CTX_DONE_FIFO_POP = 0x15e, + SC_MULTICYCLE_BUBBLE_FREEZE = 0x15f, + SC_EOP_SYNC_WINDOW = 0x160, + SC_PA0_SC_NULL_WE = 0x161, + SC_PA0_SC_NULL_DEALLOC_WE = 0x162, + SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x163, + SC_PA0_SC_DATA_FIFO_EOP_RD = 0x164, + SC_PA0_SC_DEALLOC_0_RD = 0x165, + SC_PA0_SC_DEALLOC_1_RD = 0x166, + SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x167, + SC_PA1_SC_DATA_FIFO_EOP_RD = 0x168, + SC_PA1_SC_DEALLOC_0_RD = 0x169, + SC_PA1_SC_DEALLOC_1_RD = 0x16a, + SC_PA1_SC_NULL_WE = 0x16b, + SC_PA1_SC_NULL_DEALLOC_WE = 0x16c, + SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x16d, + SC_PA2_SC_DATA_FIFO_EOP_RD = 0x16e, + SC_PA2_SC_DEALLOC_0_RD = 0x16f, + SC_PA2_SC_DEALLOC_1_RD = 0x170, + SC_PA2_SC_NULL_WE = 0x171, + SC_PA2_SC_NULL_DEALLOC_WE = 0x172, + SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x173, + SC_PA3_SC_DATA_FIFO_EOP_RD = 0x174, + SC_PA3_SC_DEALLOC_0_RD = 0x175, + SC_PA3_SC_DEALLOC_1_RD = 0x176, + SC_PA3_SC_NULL_WE = 0x177, + SC_PA3_SC_NULL_DEALLOC_WE = 0x178, + SC_PS_PA0_SC_FIFO_EMPTY = 0x179, + SC_PS_PA0_SC_FIFO_FULL = 0x17a, + SC_PA0_PS_DATA_SEND = 0x17b, + SC_PS_PA1_SC_FIFO_EMPTY = 0x17c, + SC_PS_PA1_SC_FIFO_FULL = 0x17d, + SC_PA1_PS_DATA_SEND = 0x17e, + SC_PS_PA2_SC_FIFO_EMPTY = 0x17f, + SC_PS_PA2_SC_FIFO_FULL = 0x180, + SC_PA2_PS_DATA_SEND = 0x181, + SC_PS_PA3_SC_FIFO_EMPTY = 0x182, + SC_PS_PA3_SC_FIFO_FULL = 0x183, + SC_PA3_PS_DATA_SEND = 0x184, + SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x185, + SC_BUSY_CNT_NOT_ZERO = 0x186, + SC_BM_BUSY = 0x187, + SC_BACKEND_BUSY = 0x188, + SC_SCF_SCB_INTERFACE_BUSY = 0x189, + SC_SCB_BUSY = 0x18a, +} SC_PERFCNT_SEL; +typedef enum SePairXsel { + RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x3, +} SePairXsel; +typedef enum SePairYsel { + RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x3, +} SePairYsel; +typedef enum SePairMap { + RASTER_CONFIG_SE_PAIR_MAP_0 = 0x0, + RASTER_CONFIG_SE_PAIR_MAP_1 = 0x1, + RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2, + RASTER_CONFIG_SE_PAIR_MAP_3 = 0x3, +} SePairMap; +typedef enum SeXsel { + RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x3, +} SeXsel; +typedef enum SeYsel { + RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x3, +} SeYsel; +typedef enum SeMap { + RASTER_CONFIG_SE_MAP_0 = 0x0, + RASTER_CONFIG_SE_MAP_1 = 0x1, + RASTER_CONFIG_SE_MAP_2 = 0x2, + RASTER_CONFIG_SE_MAP_3 = 0x3, +} SeMap; +typedef enum ScXsel { + RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x3, +} ScXsel; +typedef enum ScYsel { + RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x3, +} ScYsel; +typedef enum ScMap { + RASTER_CONFIG_SC_MAP_0 = 0x0, + RASTER_CONFIG_SC_MAP_1 = 0x1, + RASTER_CONFIG_SC_MAP_2 = 0x2, + RASTER_CONFIG_SC_MAP_3 = 0x3, +} ScMap; +typedef enum PkrXsel2 { + RASTER_CONFIG_PKR_XSEL2_0 = 0x0, + RASTER_CONFIG_PKR_XSEL2_1 = 0x1, + RASTER_CONFIG_PKR_XSEL2_2 = 0x2, + RASTER_CONFIG_PKR_XSEL2_3 = 0x3, +} PkrXsel2; +typedef enum PkrXsel { + RASTER_CONFIG_PKR_XSEL_0 = 0x0, + RASTER_CONFIG_PKR_XSEL_1 = 0x1, + RASTER_CONFIG_PKR_XSEL_2 = 0x2, + RASTER_CONFIG_PKR_XSEL_3 = 0x3, +} PkrXsel; +typedef enum PkrYsel { + RASTER_CONFIG_PKR_YSEL_0 = 0x0, + RASTER_CONFIG_PKR_YSEL_1 = 0x1, + RASTER_CONFIG_PKR_YSEL_2 = 0x2, + RASTER_CONFIG_PKR_YSEL_3 = 0x3, +} PkrYsel; +typedef enum PkrMap { + RASTER_CONFIG_PKR_MAP_0 = 0x0, + RASTER_CONFIG_PKR_MAP_1 = 0x1, + RASTER_CONFIG_PKR_MAP_2 = 0x2, + RASTER_CONFIG_PKR_MAP_3 = 0x3, +} PkrMap; +typedef enum RbXsel { + RASTER_CONFIG_RB_XSEL_0 = 0x0, + RASTER_CONFIG_RB_XSEL_1 = 0x1, +} RbXsel; +typedef enum RbYsel { + RASTER_CONFIG_RB_YSEL_0 = 0x0, + RASTER_CONFIG_RB_YSEL_1 = 0x1, +} RbYsel; +typedef enum RbXsel2 { + RASTER_CONFIG_RB_XSEL2_0 = 0x0, + RASTER_CONFIG_RB_XSEL2_1 = 0x1, + RASTER_CONFIG_RB_XSEL2_2 = 0x2, + RASTER_CONFIG_RB_XSEL2_3 = 0x3, +} RbXsel2; +typedef enum RbMap { + RASTER_CONFIG_RB_MAP_0 = 0x0, + RASTER_CONFIG_RB_MAP_1 = 0x1, + RASTER_CONFIG_RB_MAP_2 = 0x2, + RASTER_CONFIG_RB_MAP_3 = 0x3, +} RbMap; +typedef enum CSDATA_TYPE { + CSDATA_TYPE_TG = 0x0, + CSDATA_TYPE_STATE = 0x1, + CSDATA_TYPE_EVENT = 0x2, + CSDATA_TYPE_PRIVATE = 0x3, +} CSDATA_TYPE; +#define CSDATA_TYPE_WIDTH 0x2 +#define CSDATA_ADDR_WIDTH 0x7 +#define CSDATA_DATA_WIDTH 0x20 +typedef enum SPI_SAMPLE_CNTL { + CENTROIDS_ONLY = 0x0, + CENTERS_ONLY = 0x1, + CENTROIDS_AND_CENTERS = 0x2, + UNDEF = 0x3, +} SPI_SAMPLE_CNTL; +typedef enum SPI_FOG_MODE { + SPI_FOG_NONE = 0x0, + SPI_FOG_EXP = 0x1, + SPI_FOG_EXP2 = 0x2, + SPI_FOG_LINEAR = 0x3, +} SPI_FOG_MODE; +typedef enum SPI_PNT_SPRITE_OVERRIDE { + SPI_PNT_SPRITE_SEL_0 = 0x0, + SPI_PNT_SPRITE_SEL_1 = 0x1, + SPI_PNT_SPRITE_SEL_S = 0x2, + SPI_PNT_SPRITE_SEL_T = 0x3, + SPI_PNT_SPRITE_SEL_NONE = 0x4, +} SPI_PNT_SPRITE_OVERRIDE; +typedef enum SPI_PERFCNT_SEL { + SPI_PERF_VS_WINDOW_VALID = 0x0, + SPI_PERF_VS_BUSY = 0x1, + SPI_PERF_VS_FIRST_WAVE = 0x2, + SPI_PERF_VS_LAST_WAVE = 0x3, + SPI_PERF_VS_LSHS_DEALLOC = 0x4, + SPI_PERF_VS_PC_STALL = 0x5, + SPI_PERF_VS_POS0_STALL = 0x6, + SPI_PERF_VS_POS1_STALL = 0x7, + SPI_PERF_VS_CRAWLER_STALL = 0x8, + SPI_PERF_VS_EVENT_WAVE = 0x9, + SPI_PERF_VS_WAVE = 0xa, + SPI_PERF_VS_PERS_UPD_FULL0 = 0xb, + SPI_PERF_VS_PERS_UPD_FULL1 = 0xc, + SPI_PERF_VS_LATE_ALLOC_FULL = 0xd, + SPI_PERF_VS_FIRST_SUBGRP = 0xe, + SPI_PERF_VS_LAST_SUBGRP = 0xf, + SPI_PERF_GS_WINDOW_VALID = 0x10, + SPI_PERF_GS_BUSY = 0x11, + SPI_PERF_GS_CRAWLER_STALL = 0x12, + SPI_PERF_GS_EVENT_WAVE = 0x13, + SPI_PERF_GS_WAVE = 0x14, + SPI_PERF_GS_PERS_UPD_FULL0 = 0x15, + SPI_PERF_GS_PERS_UPD_FULL1 = 0x16, + SPI_PERF_GS_FIRST_SUBGRP = 0x17, + SPI_PERF_GS_LAST_SUBGRP = 0x18, + SPI_PERF_ES_WINDOW_VALID = 0x19, + SPI_PERF_ES_BUSY = 0x1a, + SPI_PERF_ES_CRAWLER_STALL = 0x1b, + SPI_PERF_ES_FIRST_WAVE = 0x1c, + SPI_PERF_ES_LAST_WAVE = 0x1d, + SPI_PERF_ES_LSHS_DEALLOC = 0x1e, + SPI_PERF_ES_EVENT_WAVE = 0x1f, + SPI_PERF_ES_WAVE = 0x20, + SPI_PERF_ES_PERS_UPD_FULL0 = 0x21, + SPI_PERF_ES_PERS_UPD_FULL1 = 0x22, + SPI_PERF_ES_FIRST_SUBGRP = 0x23, + SPI_PERF_ES_LAST_SUBGRP = 0x24, + SPI_PERF_HS_WINDOW_VALID = 0x25, + SPI_PERF_HS_BUSY = 0x26, + SPI_PERF_HS_CRAWLER_STALL = 0x27, + SPI_PERF_HS_FIRST_WAVE = 0x28, + SPI_PERF_HS_LAST_WAVE = 0x29, + SPI_PERF_HS_LSHS_DEALLOC = 0x2a, + SPI_PERF_HS_EVENT_WAVE = 0x2b, + SPI_PERF_HS_WAVE = 0x2c, + SPI_PERF_HS_PERS_UPD_FULL0 = 0x2d, + SPI_PERF_HS_PERS_UPD_FULL1 = 0x2e, + SPI_PERF_LS_WINDOW_VALID = 0x2f, + SPI_PERF_LS_BUSY = 0x30, + SPI_PERF_LS_CRAWLER_STALL = 0x31, + SPI_PERF_LS_FIRST_WAVE = 0x32, + SPI_PERF_LS_LAST_WAVE = 0x33, + SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x34, + SPI_PERF_LS_EVENT_WAVE = 0x35, + SPI_PERF_LS_WAVE = 0x36, + SPI_PERF_LS_PERS_UPD_FULL0 = 0x37, + SPI_PERF_LS_PERS_UPD_FULL1 = 0x38, + SPI_PERF_CSG_WINDOW_VALID = 0x39, + SPI_PERF_CSG_BUSY = 0x3a, + SPI_PERF_CSG_NUM_THREADGROUPS = 0x3b, + SPI_PERF_CSG_CRAWLER_STALL = 0x3c, + SPI_PERF_CSG_EVENT_WAVE = 0x3d, + SPI_PERF_CSG_WAVE = 0x3e, + SPI_PERF_CSN_WINDOW_VALID = 0x3f, + SPI_PERF_CSN_BUSY = 0x40, + SPI_PERF_CSN_NUM_THREADGROUPS = 0x41, + SPI_PERF_CSN_CRAWLER_STALL = 0x42, + SPI_PERF_CSN_EVENT_WAVE = 0x43, + SPI_PERF_CSN_WAVE = 0x44, + SPI_PERF_PS_CTL_WINDOW_VALID = 0x45, + SPI_PERF_PS_CTL_BUSY = 0x46, + SPI_PERF_PS_CTL_ACTIVE = 0x47, + SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x48, + SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x49, + SPI_PERF_PS_CTL_EVENT_WAVE = 0x4a, + SPI_PERF_PS_CTL_WAVE = 0x4b, + SPI_PERF_PS_CTL_OPT_WAVE = 0x4c, + SPI_PERF_PS_CTL_PASS_BIN0 = 0x4d, + SPI_PERF_PS_CTL_PASS_BIN1 = 0x4e, + SPI_PERF_PS_CTL_FPOS_BIN2 = 0x4f, + SPI_PERF_PS_CTL_PRIM_BIN0 = 0x50, + SPI_PERF_PS_CTL_PRIM_BIN1 = 0x51, + SPI_PERF_PS_CTL_CNF_BIN2 = 0x52, + SPI_PERF_PS_CTL_CNF_BIN3 = 0x53, + SPI_PERF_PS_CTL_CRAWLER_STALL = 0x54, + SPI_PERF_PS_CTL_LDS_RES_FULL = 0x55, + SPI_PERF_PS_PERS_UPD_FULL0 = 0x56, + SPI_PERF_PS_PERS_UPD_FULL1 = 0x57, + SPI_PERF_PIX_ALLOC_PEND_CNT = 0x58, + SPI_PERF_PIX_ALLOC_SCB_STALL = 0x59, + SPI_PERF_PIX_ALLOC_DB0_STALL = 0x5a, + SPI_PERF_PIX_ALLOC_DB1_STALL = 0x5b, + SPI_PERF_PIX_ALLOC_DB2_STALL = 0x5c, + SPI_PERF_PIX_ALLOC_DB3_STALL = 0x5d, + SPI_PERF_LDS0_PC_VALID = 0x5e, + SPI_PERF_LDS1_PC_VALID = 0x5f, + SPI_PERF_RA_PIPE_REQ_BIN2 = 0x60, + SPI_PERF_RA_TASK_REQ_BIN3 = 0x61, + SPI_PERF_RA_WR_CTL_FULL = 0x62, + SPI_PERF_RA_REQ_NO_ALLOC = 0x63, + SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x64, + SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x65, + SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x66, + SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x67, + SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x68, + SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x69, + SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x6a, + SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x6b, + SPI_PERF_RA_RES_STALL_PS = 0x6c, + SPI_PERF_RA_RES_STALL_VS = 0x6d, + SPI_PERF_RA_RES_STALL_GS = 0x6e, + SPI_PERF_RA_RES_STALL_ES = 0x6f, + SPI_PERF_RA_RES_STALL_HS = 0x70, + SPI_PERF_RA_RES_STALL_LS = 0x71, + SPI_PERF_RA_RES_STALL_CSG = 0x72, + SPI_PERF_RA_RES_STALL_CSN = 0x73, + SPI_PERF_RA_TMP_STALL_PS = 0x74, + SPI_PERF_RA_TMP_STALL_VS = 0x75, + SPI_PERF_RA_TMP_STALL_GS = 0x76, + SPI_PERF_RA_TMP_STALL_ES = 0x77, + SPI_PERF_RA_TMP_STALL_HS = 0x78, + SPI_PERF_RA_TMP_STALL_LS = 0x79, + SPI_PERF_RA_TMP_STALL_CSG = 0x7a, + SPI_PERF_RA_TMP_STALL_CSN = 0x7b, + SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x7c, + SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x7d, + SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x7e, + SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x7f, + SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x80, + SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x81, + SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x82, + SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x83, + SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x84, + SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x85, + SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x86, + SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x87, + SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x88, + SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x89, + SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x8a, + SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x8b, + SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x8c, + SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x8d, + SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x8e, + SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x8f, + SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x90, + SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x91, + SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x92, + SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x93, + SPI_PERF_RA_LDS_CU_FULL_PS = 0x94, + SPI_PERF_RA_LDS_CU_FULL_LS = 0x95, + SPI_PERF_RA_LDS_CU_FULL_ES = 0x96, + SPI_PERF_RA_LDS_CU_FULL_CSG = 0x97, + SPI_PERF_RA_LDS_CU_FULL_CSN = 0x98, + SPI_PERF_RA_BAR_CU_FULL_HS = 0x99, + SPI_PERF_RA_BAR_CU_FULL_CSG = 0x9a, + SPI_PERF_RA_BAR_CU_FULL_CSN = 0x9b, + SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x9c, + SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x9d, + SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x9e, + SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x9f, + SPI_PERF_RA_WVLIM_STALL_PS = 0xa0, + SPI_PERF_RA_WVLIM_STALL_VS = 0xa1, + SPI_PERF_RA_WVLIM_STALL_GS = 0xa2, + SPI_PERF_RA_WVLIM_STALL_ES = 0xa3, + SPI_PERF_RA_WVLIM_STALL_HS = 0xa4, + SPI_PERF_RA_WVLIM_STALL_LS = 0xa5, + SPI_PERF_RA_WVLIM_STALL_CSG = 0xa6, + SPI_PERF_RA_WVLIM_STALL_CSN = 0xa7, + SPI_PERF_RA_PS_LOCK = 0xa8, + SPI_PERF_RA_VS_LOCK = 0xa9, + SPI_PERF_RA_GS_LOCK = 0xaa, + SPI_PERF_RA_ES_LOCK = 0xab, + SPI_PERF_RA_HS_LOCK = 0xac, + SPI_PERF_RA_LS_LOCK = 0xad, + SPI_PERF_RA_CSG_LOCK = 0xae, + SPI_PERF_RA_CSN_LOCK = 0xaf, + SPI_PERF_RA_RSV_UPD = 0xb0, + SPI_PERF_EXP_ARB_COL_CNT = 0xb1, + SPI_PERF_EXP_ARB_PAR_CNT = 0xb2, + SPI_PERF_EXP_ARB_POS_CNT = 0xb3, + SPI_PERF_EXP_ARB_GDS_CNT = 0xb4, + SPI_PERF_CLKGATE_BUSY_STALL = 0xb5, + SPI_PERF_CLKGATE_ACTIVE_STALL = 0xb6, + SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0xb7, + SPI_PERF_CLKGATE_CGTT_DYN_ON = 0xb8, + SPI_PERF_CLKGATE_CGTT_REG_ON = 0xb9, +} SPI_PERFCNT_SEL; +typedef enum SPI_SHADER_FORMAT { + SPI_SHADER_NONE = 0x0, + SPI_SHADER_1COMP = 0x1, + SPI_SHADER_2COMP = 0x2, + SPI_SHADER_4COMPRESS = 0x3, + SPI_SHADER_4COMP = 0x4, +} SPI_SHADER_FORMAT; +typedef enum SPI_SHADER_EX_FORMAT { + SPI_SHADER_ZERO = 0x0, + SPI_SHADER_32_R = 0x1, + SPI_SHADER_32_GR = 0x2, + SPI_SHADER_32_AR = 0x3, + SPI_SHADER_FP16_ABGR = 0x4, + SPI_SHADER_UNORM16_ABGR = 0x5, + SPI_SHADER_SNORM16_ABGR = 0x6, + SPI_SHADER_UINT16_ABGR = 0x7, + SPI_SHADER_SINT16_ABGR = 0x8, + SPI_SHADER_32_ABGR = 0x9, +} SPI_SHADER_EX_FORMAT; +typedef enum CLKGATE_SM_MODE { + ON_SEQ = 0x0, + OFF_SEQ = 0x1, + PROG_SEQ = 0x2, + READ_SEQ = 0x3, + SM_MODE_RESERVED = 0x4, +} CLKGATE_SM_MODE; +typedef enum CLKGATE_BASE_MODE { + MULT_8 = 0x0, + MULT_16 = 0x1, +} CLKGATE_BASE_MODE; +typedef enum SQ_TEX_CLAMP { + SQ_TEX_WRAP = 0x0, + SQ_TEX_MIRROR = 0x1, + SQ_TEX_CLAMP_LAST_TEXEL = 0x2, + SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x3, + SQ_TEX_CLAMP_HALF_BORDER = 0x4, + SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x5, + SQ_TEX_CLAMP_BORDER = 0x6, + SQ_TEX_MIRROR_ONCE_BORDER = 0x7, +} SQ_TEX_CLAMP; +typedef enum SQ_TEX_XY_FILTER { + SQ_TEX_XY_FILTER_POINT = 0x0, + SQ_TEX_XY_FILTER_BILINEAR = 0x1, + SQ_TEX_XY_FILTER_ANISO_POINT = 0x2, + SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x3, +} SQ_TEX_XY_FILTER; +typedef enum SQ_TEX_Z_FILTER { + SQ_TEX_Z_FILTER_NONE = 0x0, + SQ_TEX_Z_FILTER_POINT = 0x1, + SQ_TEX_Z_FILTER_LINEAR = 0x2, +} SQ_TEX_Z_FILTER; +typedef enum SQ_TEX_MIP_FILTER { + SQ_TEX_MIP_FILTER_NONE = 0x0, + SQ_TEX_MIP_FILTER_POINT = 0x1, + SQ_TEX_MIP_FILTER_LINEAR = 0x2, +} SQ_TEX_MIP_FILTER; +typedef enum SQ_TEX_ANISO_RATIO { + SQ_TEX_ANISO_RATIO_1 = 0x0, + SQ_TEX_ANISO_RATIO_2 = 0x1, + SQ_TEX_ANISO_RATIO_4 = 0x2, + SQ_TEX_ANISO_RATIO_8 = 0x3, + SQ_TEX_ANISO_RATIO_16 = 0x4, +} SQ_TEX_ANISO_RATIO; +typedef enum SQ_TEX_DEPTH_COMPARE { + SQ_TEX_DEPTH_COMPARE_NEVER = 0x0, + SQ_TEX_DEPTH_COMPARE_LESS = 0x1, + SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2, + SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x3, + SQ_TEX_DEPTH_COMPARE_GREATER = 0x4, + SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x5, + SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x6, + SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x7, +} SQ_TEX_DEPTH_COMPARE; +typedef enum SQ_TEX_BORDER_COLOR { + SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x0, + SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x1, + SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2, + SQ_TEX_BORDER_COLOR_REGISTER = 0x3, +} SQ_TEX_BORDER_COLOR; +typedef enum SQ_RSRC_BUF_TYPE { + SQ_RSRC_BUF = 0x0, + SQ_RSRC_BUF_RSVD_1 = 0x1, + SQ_RSRC_BUF_RSVD_2 = 0x2, + SQ_RSRC_BUF_RSVD_3 = 0x3, +} SQ_RSRC_BUF_TYPE; +typedef enum SQ_RSRC_IMG_TYPE { + SQ_RSRC_IMG_RSVD_0 = 0x0, + SQ_RSRC_IMG_RSVD_1 = 0x1, + SQ_RSRC_IMG_RSVD_2 = 0x2, + SQ_RSRC_IMG_RSVD_3 = 0x3, + SQ_RSRC_IMG_RSVD_4 = 0x4, + SQ_RSRC_IMG_RSVD_5 = 0x5, + SQ_RSRC_IMG_RSVD_6 = 0x6, + SQ_RSRC_IMG_RSVD_7 = 0x7, + SQ_RSRC_IMG_1D = 0x8, + SQ_RSRC_IMG_2D = 0x9, + SQ_RSRC_IMG_3D = 0xa, + SQ_RSRC_IMG_CUBE = 0xb, + SQ_RSRC_IMG_1D_ARRAY = 0xc, + SQ_RSRC_IMG_2D_ARRAY = 0xd, + SQ_RSRC_IMG_2D_MSAA = 0xe, + SQ_RSRC_IMG_2D_MSAA_ARRAY = 0xf, +} SQ_RSRC_IMG_TYPE; +typedef enum SQ_RSRC_FLAT_TYPE { + SQ_RSRC_FLAT_RSVD_0 = 0x0, + SQ_RSRC_FLAT = 0x1, + SQ_RSRC_FLAT_RSVD_2 = 0x2, + SQ_RSRC_FLAT_RSVD_3 = 0x3, +} SQ_RSRC_FLAT_TYPE; +typedef enum SQ_IMG_FILTER_TYPE { + SQ_IMG_FILTER_MODE_BLEND = 0x0, + SQ_IMG_FILTER_MODE_MIN = 0x1, + SQ_IMG_FILTER_MODE_MAX = 0x2, +} SQ_IMG_FILTER_TYPE; +typedef enum SQ_SEL_XYZW01 { + SQ_SEL_0 = 0x0, + SQ_SEL_1 = 0x1, + SQ_SEL_RESERVED_0 = 0x2, + SQ_SEL_RESERVED_1 = 0x3, + SQ_SEL_X = 0x4, + SQ_SEL_Y = 0x5, + SQ_SEL_Z = 0x6, + SQ_SEL_W = 0x7, +} SQ_SEL_XYZW01; +typedef enum SQ_WAVE_TYPE { + SQ_WAVE_TYPE_PS = 0x0, + SQ_WAVE_TYPE_VS = 0x1, + SQ_WAVE_TYPE_GS = 0x2, + SQ_WAVE_TYPE_ES = 0x3, + SQ_WAVE_TYPE_HS = 0x4, + SQ_WAVE_TYPE_LS = 0x5, + SQ_WAVE_TYPE_CS = 0x6, + SQ_WAVE_TYPE_PS1 = 0x7, +} SQ_WAVE_TYPE; +typedef enum SQ_THREAD_TRACE_TOKEN_TYPE { + SQ_THREAD_TRACE_TOKEN_MISC = 0x0, + SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x1, + SQ_THREAD_TRACE_TOKEN_REG = 0x2, + SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x3, + SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x4, + SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x5, + SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x6, + SQ_THREAD_TRACE_TOKEN_EVENT = 0x7, + SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x8, + SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x9, + SQ_THREAD_TRACE_TOKEN_INST = 0xa, + SQ_THREAD_TRACE_TOKEN_INST_PC = 0xb, + SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0xc, + SQ_THREAD_TRACE_TOKEN_ISSUE = 0xd, + SQ_THREAD_TRACE_TOKEN_PERF = 0xe, + SQ_THREAD_TRACE_TOKEN_REG_CS = 0xf, +} SQ_THREAD_TRACE_TOKEN_TYPE; +typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE { + SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x0, + SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x1, + SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2, + SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x3, + SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x4, + SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x5, +} SQ_THREAD_TRACE_MISC_TOKEN_TYPE; +typedef enum SQ_THREAD_TRACE_INST_TYPE { + SQ_THREAD_TRACE_INST_TYPE_SMEM = 0x0, + SQ_THREAD_TRACE_INST_TYPE_SALU = 0x1, + SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2, + SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x3, + SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x4, + SQ_THREAD_TRACE_INST_TYPE_VALU = 0x5, + SQ_THREAD_TRACE_INST_TYPE_LDS = 0x6, + SQ_THREAD_TRACE_INST_TYPE_PC = 0x7, + SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x8, + SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x9, + SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0xa, + SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0xb, + SQ_THREAD_TRACE_INST_TYPE_JUMP = 0xc, + SQ_THREAD_TRACE_INST_TYPE_NEXT = 0xd, + SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0xe, + SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0xf, +} SQ_THREAD_TRACE_INST_TYPE; +typedef enum SQ_THREAD_TRACE_REG_TYPE { + SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x0, + SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x1, + SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2, + SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x3, + SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x4, + SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x5, + SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x6, + SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x7, +} SQ_THREAD_TRACE_REG_TYPE; +typedef enum SQ_THREAD_TRACE_REG_OP { + SQ_THREAD_TRACE_REG_OP_READ = 0x0, + SQ_THREAD_TRACE_REG_OP_WRITE = 0x1, +} SQ_THREAD_TRACE_REG_OP; +typedef enum SQ_THREAD_TRACE_MODE_SEL { + SQ_THREAD_TRACE_MODE_OFF = 0x0, + SQ_THREAD_TRACE_MODE_ON = 0x1, + SQ_THREAD_TRACE_MODE_RANDOM = 0x2, +} SQ_THREAD_TRACE_MODE_SEL; +typedef enum SQ_THREAD_TRACE_CAPTURE_MODE { + SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x0, + SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x1, + SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2, +} SQ_THREAD_TRACE_CAPTURE_MODE; +typedef enum SQ_THREAD_TRACE_VM_ID_MASK { + SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x0, + SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x1, + SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2, +} SQ_THREAD_TRACE_VM_ID_MASK; +typedef enum SQ_THREAD_TRACE_WAVE_MASK { + SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x0, + SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x1, + SQ_THREAD_TRACE_WAVE_MASK_1_2 = 0x2, + SQ_THREAD_TRACE_WAVE_MASK_1_4 = 0x3, + SQ_THREAD_TRACE_WAVE_MASK_1_8 = 0x4, + SQ_THREAD_TRACE_WAVE_MASK_1_16 = 0x5, + SQ_THREAD_TRACE_WAVE_MASK_1_32 = 0x6, + SQ_THREAD_TRACE_WAVE_MASK_1_64 = 0x7, +} SQ_THREAD_TRACE_WAVE_MASK; +typedef enum SQ_THREAD_TRACE_ISSUE { + SQ_THREAD_TRACE_ISSUE_NULL = 0x0, + SQ_THREAD_TRACE_ISSUE_STALL = 0x1, + SQ_THREAD_TRACE_ISSUE_INST = 0x2, + SQ_THREAD_TRACE_ISSUE_IMMED = 0x3, +} SQ_THREAD_TRACE_ISSUE; +typedef enum SQ_THREAD_TRACE_ISSUE_MASK { + SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x0, + SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x1, + SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2, + SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x3, +} SQ_THREAD_TRACE_ISSUE_MASK; +typedef enum SQ_PERF_SEL { + SQ_PERF_SEL_NONE = 0x0, + SQ_PERF_SEL_ACCUM_PREV = 0x1, + SQ_PERF_SEL_CYCLES = 0x2, + SQ_PERF_SEL_BUSY_CYCLES = 0x3, + SQ_PERF_SEL_WAVES = 0x4, + SQ_PERF_SEL_LEVEL_WAVES = 0x5, + SQ_PERF_SEL_WAVES_EQ_64 = 0x6, + SQ_PERF_SEL_WAVES_LT_64 = 0x7, + SQ_PERF_SEL_WAVES_LT_48 = 0x8, + SQ_PERF_SEL_WAVES_LT_32 = 0x9, + SQ_PERF_SEL_WAVES_LT_16 = 0xa, + SQ_PERF_SEL_WAVES_CU = 0xb, + SQ_PERF_SEL_LEVEL_WAVES_CU = 0xc, + SQ_PERF_SEL_BUSY_CU_CYCLES = 0xd, + SQ_PERF_SEL_ITEMS = 0xe, + SQ_PERF_SEL_QUADS = 0xf, + SQ_PERF_SEL_EVENTS = 0x10, + SQ_PERF_SEL_SURF_SYNCS = 0x11, + SQ_PERF_SEL_TTRACE_REQS = 0x12, + SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x13, + SQ_PERF_SEL_TTRACE_STALL = 0x14, + SQ_PERF_SEL_MSG_CNTR = 0x15, + SQ_PERF_SEL_MSG_PERF = 0x16, + SQ_PERF_SEL_MSG_GSCNT = 0x17, + SQ_PERF_SEL_MSG_INTERRUPT = 0x18, + SQ_PERF_SEL_INSTS = 0x19, + SQ_PERF_SEL_INSTS_VALU = 0x1a, + SQ_PERF_SEL_INSTS_VMEM_WR = 0x1b, + SQ_PERF_SEL_INSTS_VMEM_RD = 0x1c, + SQ_PERF_SEL_INSTS_VMEM = 0x1d, + SQ_PERF_SEL_INSTS_SALU = 0x1e, + SQ_PERF_SEL_INSTS_SMEM = 0x1f, + SQ_PERF_SEL_INSTS_FLAT = 0x20, + SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x21, + SQ_PERF_SEL_INSTS_LDS = 0x22, + SQ_PERF_SEL_INSTS_GDS = 0x23, + SQ_PERF_SEL_INSTS_EXP = 0x24, + SQ_PERF_SEL_INSTS_EXP_GDS = 0x25, + SQ_PERF_SEL_INSTS_BRANCH = 0x26, + SQ_PERF_SEL_INSTS_SENDMSG = 0x27, + SQ_PERF_SEL_INSTS_VSKIPPED = 0x28, + SQ_PERF_SEL_INST_LEVEL_VMEM = 0x29, + SQ_PERF_SEL_INST_LEVEL_SMEM = 0x2a, + SQ_PERF_SEL_INST_LEVEL_LDS = 0x2b, + SQ_PERF_SEL_INST_LEVEL_GDS = 0x2c, + SQ_PERF_SEL_INST_LEVEL_EXP = 0x2d, + SQ_PERF_SEL_WAVE_CYCLES = 0x2e, + SQ_PERF_SEL_WAVE_READY = 0x2f, + SQ_PERF_SEL_WAIT_CNT_VM = 0x30, + SQ_PERF_SEL_WAIT_CNT_LGKM = 0x31, + SQ_PERF_SEL_WAIT_CNT_EXP = 0x32, + SQ_PERF_SEL_WAIT_CNT_ANY = 0x33, + SQ_PERF_SEL_WAIT_BARRIER = 0x34, + SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x35, + SQ_PERF_SEL_WAIT_SLEEP = 0x36, + SQ_PERF_SEL_WAIT_OTHER = 0x37, + SQ_PERF_SEL_WAIT_ANY = 0x38, + SQ_PERF_SEL_WAIT_TTRACE = 0x39, + SQ_PERF_SEL_WAIT_IFETCH = 0x3a, + SQ_PERF_SEL_WAIT_INST_VMEM = 0x3b, + SQ_PERF_SEL_WAIT_INST_SCA = 0x3c, + SQ_PERF_SEL_WAIT_INST_LDS = 0x3d, + SQ_PERF_SEL_WAIT_INST_VALU = 0x3e, + SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x3f, + SQ_PERF_SEL_WAIT_INST_MISC = 0x40, + SQ_PERF_SEL_WAIT_INST_FLAT = 0x41, + SQ_PERF_SEL_ACTIVE_INST_ANY = 0x42, + SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x43, + SQ_PERF_SEL_ACTIVE_INST_LDS = 0x44, + SQ_PERF_SEL_ACTIVE_INST_VALU = 0x45, + SQ_PERF_SEL_ACTIVE_INST_SCA = 0x46, + SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x47, + SQ_PERF_SEL_ACTIVE_INST_MISC = 0x48, + SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x49, + SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x4a, + SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x4b, + SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x4c, + SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x4d, + SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x4e, + SQ_PERF_SEL_INST_CYCLES_VMEM = 0x4f, + SQ_PERF_SEL_INST_CYCLES_LDS = 0x50, + SQ_PERF_SEL_INST_CYCLES_VALU = 0x51, + SQ_PERF_SEL_INST_CYCLES_EXP = 0x52, + SQ_PERF_SEL_INST_CYCLES_GDS = 0x53, + SQ_PERF_SEL_INST_CYCLES_SCA = 0x54, + SQ_PERF_SEL_INST_CYCLES_SMEM = 0x55, + SQ_PERF_SEL_INST_CYCLES_SALU = 0x56, + SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x57, + SQ_PERF_SEL_INST_CYCLES_MISC = 0x58, + SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x59, + SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x5a, + SQ_PERF_SEL_IFETCH = 0x5b, + SQ_PERF_SEL_IFETCH_LEVEL = 0x5c, + SQ_PERF_SEL_CBRANCH_FORK = 0x5d, + SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x5e, + SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x5f, + SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x60, + SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x61, + SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x62, + SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x63, + SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x64, + SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x65, + SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x66, + SQ_PERF_SEL_VALU_DEP_STALL = 0x67, + SQ_PERF_SEL_VALU_STARVE = 0x68, + SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x69, + SQ_PERF_SEL_LDS_BACK2BACK_STALL = 0x6a, + SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x6b, + SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x6c, + SQ_PERF_SEL_VMEM_BACK2BACK_STALL = 0x6d, + SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x6e, + SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x6f, + SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x70, + SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL = 0x71, + SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x72, + SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x73, + SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x74, + SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x75, + SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x76, + SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x77, + SQ_PERF_SEL_SRC_CD_BUSY = 0x78, + SQ_PERF_SEL_PT_POWER_STALL = 0x79, + SQ_PERF_SEL_USER0 = 0x7a, + SQ_PERF_SEL_USER1 = 0x7b, + SQ_PERF_SEL_USER2 = 0x7c, + SQ_PERF_SEL_USER3 = 0x7d, + SQ_PERF_SEL_USER4 = 0x7e, + SQ_PERF_SEL_USER5 = 0x7f, + SQ_PERF_SEL_USER6 = 0x80, + SQ_PERF_SEL_USER7 = 0x81, + SQ_PERF_SEL_USER8 = 0x82, + SQ_PERF_SEL_USER9 = 0x83, + SQ_PERF_SEL_USER10 = 0x84, + SQ_PERF_SEL_USER11 = 0x85, + SQ_PERF_SEL_USER12 = 0x86, + SQ_PERF_SEL_USER13 = 0x87, + SQ_PERF_SEL_USER14 = 0x88, + SQ_PERF_SEL_USER15 = 0x89, + SQ_PERF_SEL_USER_LEVEL0 = 0x8a, + SQ_PERF_SEL_USER_LEVEL1 = 0x8b, + SQ_PERF_SEL_USER_LEVEL2 = 0x8c, + SQ_PERF_SEL_USER_LEVEL3 = 0x8d, + SQ_PERF_SEL_USER_LEVEL4 = 0x8e, + SQ_PERF_SEL_USER_LEVEL5 = 0x8f, + SQ_PERF_SEL_USER_LEVEL6 = 0x90, + SQ_PERF_SEL_USER_LEVEL7 = 0x91, + SQ_PERF_SEL_USER_LEVEL8 = 0x92, + SQ_PERF_SEL_USER_LEVEL9 = 0x93, + SQ_PERF_SEL_USER_LEVEL10 = 0x94, + SQ_PERF_SEL_USER_LEVEL11 = 0x95, + SQ_PERF_SEL_USER_LEVEL12 = 0x96, + SQ_PERF_SEL_USER_LEVEL13 = 0x97, + SQ_PERF_SEL_USER_LEVEL14 = 0x98, + SQ_PERF_SEL_USER_LEVEL15 = 0x99, + SQ_PERF_SEL_POWER_VALU = 0x9a, + SQ_PERF_SEL_POWER_VALU0 = 0x9b, + SQ_PERF_SEL_POWER_VALU1 = 0x9c, + SQ_PERF_SEL_POWER_VALU2 = 0x9d, + SQ_PERF_SEL_POWER_GPR_RD = 0x9e, + SQ_PERF_SEL_POWER_GPR_WR = 0x9f, + SQ_PERF_SEL_POWER_LDS_BUSY = 0xa0, + SQ_PERF_SEL_POWER_ALU_BUSY = 0xa1, + SQ_PERF_SEL_POWER_TEX_BUSY = 0xa2, + SQ_PERF_SEL_ACCUM_PREV_HIRES = 0xa3, + SQ_PERF_SEL_DUMMY_LAST = 0xa7, + SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0xa8, + SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0xa9, + SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0xaa, + SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0xab, + SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0xac, + SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0xad, + SQC_PERF_SEL_TC_REQ = 0xae, + SQC_PERF_SEL_TC_INST_REQ = 0xaf, + SQC_PERF_SEL_TC_DATA_REQ = 0xb0, + SQC_PERF_SEL_TC_STALL = 0xb1, + SQC_PERF_SEL_TC_STARVE = 0xb2, + SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0xb3, + SQC_PERF_SEL_ICACHE_REQ = 0xb4, + SQC_PERF_SEL_ICACHE_HITS = 0xb5, + SQC_PERF_SEL_ICACHE_MISSES = 0xb6, + SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0xb7, + SQC_PERF_SEL_ICACHE_UNCACHED = 0xb8, + SQC_PERF_SEL_ICACHE_VOLATILE = 0xb9, + SQC_PERF_SEL_ICACHE_INVAL_INST = 0xba, + SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0xbb, + SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_INST = 0xbc, + SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_ASYNC = 0xbd, + SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0xbe, + SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0xbf, + SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0xc0, + SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xc1, + SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0xc2, + SQC_PERF_SEL_ICACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xc3, + SQC_PERF_SEL_ICACHE_CACHE_STALL_UNCACHED_HIT = 0xc4, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0xc5, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc6, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xc7, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0xc8, + SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xc9, + SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0xca, + SQC_PERF_SEL_DCACHE_REQ = 0xcb, + SQC_PERF_SEL_DCACHE_HITS = 0xcc, + SQC_PERF_SEL_DCACHE_MISSES = 0xcd, + SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0xce, + SQC_PERF_SEL_DCACHE_UNCACHED = 0xcf, + SQC_PERF_SEL_DCACHE_VOLATILE = 0xd0, + SQC_PERF_SEL_DCACHE_INVAL_INST = 0xd1, + SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0xd2, + SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0xd3, + SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0xd4, + SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0xd5, + SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0xd6, + SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0xd7, + SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xd8, + SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0xd9, + SQC_PERF_SEL_DCACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xda, + SQC_PERF_SEL_DCACHE_CACHE_STALL_UNCACHED_HIT = 0xdb, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0xdc, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xdd, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xde, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0xdf, + SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xe0, + SQC_PERF_SEL_DCACHE_REQ_1 = 0xe1, + SQC_PERF_SEL_DCACHE_REQ_2 = 0xe2, + SQC_PERF_SEL_DCACHE_REQ_4 = 0xe3, + SQC_PERF_SEL_DCACHE_REQ_8 = 0xe4, + SQC_PERF_SEL_DCACHE_REQ_16 = 0xe5, + SQC_PERF_SEL_DCACHE_REQ_TIME = 0xe6, + SQC_PERF_SEL_SQ_DCACHE_REQS = 0xe7, + SQC_PERF_SEL_DCACHE_FLAT_REQ = 0xe8, + SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0xe9, + SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0xea, + SQC_PERF_SEL_ICACHE_PRE_CC_LEVEL = 0xeb, + SQC_PERF_SEL_ICACHE_POST_CC_LEVEL = 0xec, + SQC_PERF_SEL_ICACHE_POST_CC_HIT_LEVEL = 0xed, + SQC_PERF_SEL_ICACHE_POST_CC_MISS_LEVEL = 0xee, + SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0xef, + SQC_PERF_SEL_DCACHE_PRE_CC_LEVEL = 0xf0, + SQC_PERF_SEL_DCACHE_POST_CC_LEVEL = 0xf1, + SQC_PERF_SEL_DCACHE_POST_CC_HIT_LEVEL = 0xf2, + SQC_PERF_SEL_DCACHE_POST_CC_MISS_LEVEL = 0xf3, + SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0xf4, + SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0xf5, + SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0xf6, + SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED = 0xf7, + SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED = 0xf8, + SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED = 0xf9, + SQC_PERF_SEL_ERR_DCACHE_REQ_16_GPR_ADDR_UNALIGNED= 0xfa, + SQC_PERF_SEL_DUMMY_LAST = 0xfb, +} SQ_PERF_SEL; +typedef enum SQC_DATA_CACHE_POLICIES { + SQC_DATA_CACHE_POLICY_HIT_LRU = 0x0, + SQC_DATA_CACHE_POLICY_MISS_EVICT = 0x1, +} SQC_DATA_CACHE_POLICIES; +typedef enum SQ_CAC_POWER_SEL { + SQ_CAC_POWER_VALU = 0x0, + SQ_CAC_POWER_VALU0 = 0x1, + SQ_CAC_POWER_VALU1 = 0x2, + SQ_CAC_POWER_VALU2 = 0x3, + SQ_CAC_POWER_GPR_RD = 0x4, + SQ_CAC_POWER_GPR_WR = 0x5, + SQ_CAC_POWER_LDS_BUSY = 0x6, + SQ_CAC_POWER_ALU_BUSY = 0x7, + SQ_CAC_POWER_TEX_BUSY = 0x8, +} SQ_CAC_POWER_SEL; +typedef enum SQ_IND_CMD_CMD { + SQ_IND_CMD_CMD_NULL = 0x0, + SQ_IND_CMD_CMD_HALT = 0x1, + SQ_IND_CMD_CMD_RESUME = 0x2, + SQ_IND_CMD_CMD_KILL = 0x3, + SQ_IND_CMD_CMD_DEBUG = 0x4, + SQ_IND_CMD_CMD_TRAP = 0x5, +} SQ_IND_CMD_CMD; +typedef enum SQ_IND_CMD_MODE { + SQ_IND_CMD_MODE_SINGLE = 0x0, + SQ_IND_CMD_MODE_BROADCAST = 0x1, + SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2, + SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x3, + SQ_IND_CMD_MODE_BROADCAST_ME = 0x4, +} SQ_IND_CMD_MODE; +typedef enum SQ_DED_INFO_SOURCE { + SQ_DED_INFO_SOURCE_INVALID = 0x0, + SQ_DED_INFO_SOURCE_INST = 0x1, + SQ_DED_INFO_SOURCE_SGPR = 0x2, + SQ_DED_INFO_SOURCE_VGPR = 0x3, + SQ_DED_INFO_SOURCE_LDS = 0x4, + SQ_DED_INFO_SOURCE_GDS = 0x5, + SQ_DED_INFO_SOURCE_TA = 0x6, +} SQ_DED_INFO_SOURCE; +typedef enum SQ_ROUND_MODE { + SQ_ROUND_NEAREST_EVEN = 0x0, + SQ_ROUND_PLUS_INFINITY = 0x1, + SQ_ROUND_MINUS_INFINITY = 0x2, + SQ_ROUND_TO_ZERO = 0x3, +} SQ_ROUND_MODE; +typedef enum SQ_INTERRUPT_WORD_ENCODING { + SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, + SQ_INTERRUPT_WORD_ENCODING_INST = 0x1, + SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2, +} SQ_INTERRUPT_WORD_ENCODING; +typedef enum ENUM_SQ_EXPORT_RAT_INST { + SQ_EXPORT_RAT_INST_NOP = 0x0, + SQ_EXPORT_RAT_INST_STORE_TYPED = 0x1, + SQ_EXPORT_RAT_INST_STORE_RAW = 0x2, + SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x3, + SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x4, + SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x5, + SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x6, + SQ_EXPORT_RAT_INST_ADD = 0x7, + SQ_EXPORT_RAT_INST_SUB = 0x8, + SQ_EXPORT_RAT_INST_RSUB = 0x9, + SQ_EXPORT_RAT_INST_MIN_INT = 0xa, + SQ_EXPORT_RAT_INST_MIN_UINT = 0xb, + SQ_EXPORT_RAT_INST_MAX_INT = 0xc, + SQ_EXPORT_RAT_INST_MAX_UINT = 0xd, + SQ_EXPORT_RAT_INST_AND = 0xe, + SQ_EXPORT_RAT_INST_OR = 0xf, + SQ_EXPORT_RAT_INST_XOR = 0x10, + SQ_EXPORT_RAT_INST_MSKOR = 0x11, + SQ_EXPORT_RAT_INST_INC_UINT = 0x12, + SQ_EXPORT_RAT_INST_DEC_UINT = 0x13, + SQ_EXPORT_RAT_INST_STORE_DWORD = 0x14, + SQ_EXPORT_RAT_INST_STORE_SHORT = 0x15, + SQ_EXPORT_RAT_INST_STORE_BYTE = 0x16, + SQ_EXPORT_RAT_INST_NOP_RTN = 0x20, + SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22, + SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23, + SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24, + SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25, + SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26, + SQ_EXPORT_RAT_INST_ADD_RTN = 0x27, + SQ_EXPORT_RAT_INST_SUB_RTN = 0x28, + SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29, + SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a, + SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b, + SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c, + SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d, + SQ_EXPORT_RAT_INST_AND_RTN = 0x2e, + SQ_EXPORT_RAT_INST_OR_RTN = 0x2f, + SQ_EXPORT_RAT_INST_XOR_RTN = 0x30, + SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31, + SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32, + SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33, +} ENUM_SQ_EXPORT_RAT_INST; +typedef enum SQ_IBUF_ST { + SQ_IBUF_IB_IDLE = 0x0, + SQ_IBUF_IB_INI_WAIT_GNT = 0x1, + SQ_IBUF_IB_INI_WAIT_DRET = 0x2, + SQ_IBUF_IB_LE_4DW = 0x3, + SQ_IBUF_IB_WAIT_DRET = 0x4, + SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x5, + SQ_IBUF_IB_DRET = 0x6, + SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x7, +} SQ_IBUF_ST; +typedef enum SQ_INST_STR_ST { + SQ_INST_STR_IB_WAVE_NORML = 0x0, + SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x1, + SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2, + SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x3, + SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x4, + SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x5, + SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x6, + SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x7, +} SQ_INST_STR_ST; +typedef enum SQ_WAVE_IB_ECC_ST { + SQ_WAVE_IB_ECC_CLEAN = 0x0, + SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x1, + SQ_WAVE_IB_ECC_ERR_HALT = 0x2, + SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x3, +} SQ_WAVE_IB_ECC_ST; +typedef enum SH_MEM_ALIGNMENT_MODE { + SH_MEM_ALIGNMENT_MODE_DWORD = 0x0, + SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x1, + SH_MEM_ALIGNMENT_MODE_STRICT = 0x2, + SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x3, +} SH_MEM_ALIGNMENT_MODE; +#define SQ_WAVE_TYPE_PS0 0x0 +#define SQ_THREAD_TRACE_LFSR_PS 0x8016 +#define SQ_THREAD_TRACE_LFSR_VS 0x801c +#define SQ_THREAD_TRACE_LFSR_GS 0x801f +#define SQ_THREAD_TRACE_LFSR_ES 0x8029 +#define SQ_THREAD_TRACE_LFSR_HS 0x805e +#define SQ_THREAD_TRACE_LFSR_LS 0x806b +#define SQ_THREAD_TRACE_LFSR_CS 0x8097 +#define SQIND_GLOBAL_REGS_OFFSET 0x0 +#define SQIND_GLOBAL_REGS_SIZE 0x8 +#define SQIND_LOCAL_REGS_OFFSET 0x8 +#define SQIND_LOCAL_REGS_SIZE 0x8 +#define SQIND_WAVE_HWREGS_OFFSET 0x10 +#define SQIND_WAVE_HWREGS_SIZE 0x1f0 +#define SQIND_WAVE_SGPRS_OFFSET 0x200 +#define SQIND_WAVE_SGPRS_SIZE 0x200 +#define SQ_GFXDEC_BEGIN 0xa000 +#define SQ_GFXDEC_END 0xc000 +#define SQ_GFXDEC_STATE_ID_SHIFT 0xa +#define SQDEC_BEGIN 0x2300 +#define SQDEC_END 0x23ff +#define SQPERFSDEC_BEGIN 0xd9c0 +#define SQPERFSDEC_END 0xda40 +#define SQPERFDDEC_BEGIN 0xd1c0 +#define SQPERFDDEC_END 0xd240 +#define SQGFXUDEC_BEGIN 0xc340 +#define SQGFXUDEC_END 0xc380 +#define SQPWRDEC_BEGIN 0xf08c +#define SQPWRDEC_END 0xf094 +#define SQ_DISPATCHER_GFX_MIN 0x10 +#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x8 +#define SQ_MAX_PGM_SGPRS 0x68 +#define SQ_MAX_PGM_VGPRS 0x100 +#define SQ_THREAD_TRACE_TIME_UNIT 0x4 +#define SQ_INTERRUPT_ID 0xef +#define SQ_EX_MODE_EXCP_VALU_BASE 0x0 +#define SQ_EX_MODE_EXCP_VALU_SIZE 0x7 +#define SQ_EX_MODE_EXCP_INVALID 0x0 +#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x1 +#define SQ_EX_MODE_EXCP_DIV0 0x2 +#define SQ_EX_MODE_EXCP_OVERFLOW 0x3 +#define SQ_EX_MODE_EXCP_UNDERFLOW 0x4 +#define SQ_EX_MODE_EXCP_INEXACT 0x5 +#define SQ_EX_MODE_EXCP_INT_DIV0 0x6 +#define SQ_EX_MODE_EXCP_ADDR_WATCH 0x7 +#define SQ_EX_MODE_EXCP_MEM_VIOL 0x8 +#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 +#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 +#define INST_ID_HW_TRAP 0xfffffff2 +#define INST_ID_KILL_SEQ 0xfffffff3 +#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe +#define SQ_ENC_SOP1_BITS 0xbe800000 +#define SQ_ENC_SOP1_MASK 0xff800000 +#define SQ_ENC_SOP1_FIELD 0x17d +#define SQ_ENC_SOPC_BITS 0xbf000000 +#define SQ_ENC_SOPC_MASK 0xff800000 +#define SQ_ENC_SOPC_FIELD 0x17e +#define SQ_ENC_SOPP_BITS 0xbf800000 +#define SQ_ENC_SOPP_MASK 0xff800000 +#define SQ_ENC_SOPP_FIELD 0x17f +#define SQ_ENC_SOPK_BITS 0xb0000000 +#define SQ_ENC_SOPK_MASK 0xf0000000 +#define SQ_ENC_SOPK_FIELD 0xb +#define SQ_ENC_SOP2_BITS 0x80000000 +#define SQ_ENC_SOP2_MASK 0xc0000000 +#define SQ_ENC_SOP2_FIELD 0x2 +#define SQ_ENC_SMRD_BITS 0xc0000000 +#define SQ_ENC_SMRD_MASK 0xf8000000 +#define SQ_ENC_SMRD_FIELD 0x18 +#define SQ_ENC_VOP1_BITS 0x7e000000 +#define SQ_ENC_VOP1_MASK 0xfe000000 +#define SQ_ENC_VOP1_FIELD 0x3f +#define SQ_ENC_VOPC_BITS 0x7c000000 +#define SQ_ENC_VOPC_MASK 0xfe000000 +#define SQ_ENC_VOPC_FIELD 0x3e +#define SQ_ENC_VOP2_BITS 0x0 +#define SQ_ENC_VOP2_MASK 0x80000000 +#define SQ_ENC_VOP2_FIELD 0x0 +#define SQ_ENC_VINTRP_BITS 0xc8000000 +#define SQ_ENC_VINTRP_MASK 0xfc000000 +#define SQ_ENC_VINTRP_FIELD 0x32 +#define SQ_ENC_VOP3_BITS 0xd0000000 +#define SQ_ENC_VOP3_MASK 0xfc000000 +#define SQ_ENC_VOP3_FIELD 0x34 +#define SQ_ENC_DS_BITS 0xd8000000 +#define SQ_ENC_DS_MASK 0xfc000000 +#define SQ_ENC_DS_FIELD 0x36 +#define SQ_ENC_MUBUF_BITS 0xe0000000 +#define SQ_ENC_MUBUF_MASK 0xfc000000 +#define SQ_ENC_MUBUF_FIELD 0x38 +#define SQ_ENC_MTBUF_BITS 0xe8000000 +#define SQ_ENC_MTBUF_MASK 0xfc000000 +#define SQ_ENC_MTBUF_FIELD 0x3a +#define SQ_ENC_MIMG_BITS 0xf0000000 +#define SQ_ENC_MIMG_MASK 0xfc000000 +#define SQ_ENC_MIMG_FIELD 0x3c +#define SQ_ENC_EXP_BITS 0xf8000000 +#define SQ_ENC_EXP_MASK 0xfc000000 +#define SQ_ENC_EXP_FIELD 0x3e +#define SQ_ENC_FLAT_BITS 0xdc000000 +#define SQ_ENC_FLAT_MASK 0xfc000000 +#define SQ_ENC_FLAT_FIELD 0x37 +#define SQ_WAITCNT_VM_SHIFT 0x0 +#define SQ_SENDMSG_STREAMID_SIZE 0x2 +#define SQ_V_OPC_COUNT 0x100 +#define SQ_HWREG_OFFSET_SIZE 0x5 +#define SQ_HWREG_OFFSET_SHIFT 0x6 +#define SQ_NUM_ATTR 0x21 +#define SQ_NUM_VGPR 0x100 +#define SQ_SENDMSG_MSG_SIZE 0x4 +#define SQ_NUM_TTMP 0xc +#define SQ_HWREG_ID_SIZE 0x6 +#define SQ_SENDMSG_GSOP_SIZE 0x2 +#define SQ_NUM_SGPR 0x68 +#define SQ_EXP_NUM_MRT 0x8 +#define SQ_SENDMSG_SYSTEM_SIZE 0x3 +#define SQ_WAITCNT_LGKM_SHIFT 0x8 +#define SQ_WAITCNT_EXP_SIZE 0x3 +#define SQ_SENDMSG_SYSTEM_SHIFT 0x4 +#define SQ_HWREG_SIZE_SHIFT 0xb +#define SQ_EXP_NUM_GDS 0x5 +#define SQ_SENDMSG_MSG_SHIFT 0x0 +#define SQ_WAITCNT_EXP_SHIFT 0x4 +#define SQ_WAITCNT_VM_SIZE 0x4 +#define SQ_SENDMSG_GSOP_SHIFT 0x4 +#define SQ_SRC_VGPR_BIT 0x100 +#define SQ_V_OP2_COUNT 0x40 +#define SQ_EXP_NUM_PARAM 0x20 +#define SQ_SENDMSG_STREAMID_SHIFT 0x8 +#define SQ_V_OP1_COUNT 0x80 +#define SQ_WAITCNT_LGKM_SIZE 0x5 +#define SQ_EXP_NUM_POS 0x4 +#define SQ_HWREG_SIZE_SIZE 0x5 +#define SQ_HWREG_ID_SHIFT 0x0 +#define SQ_S_MOV_B32 0x3 +#define SQ_S_MOV_B64 0x4 +#define SQ_S_CMOV_B32 0x5 +#define SQ_S_CMOV_B64 0x6 +#define SQ_S_NOT_B32 0x7 +#define SQ_S_NOT_B64 0x8 +#define SQ_S_WQM_B32 0x9 +#define SQ_S_WQM_B64 0xa +#define SQ_S_BREV_B32 0xb +#define SQ_S_BREV_B64 0xc +#define SQ_S_BCNT0_I32_B32 0xd +#define SQ_S_BCNT0_I32_B64 0xe +#define SQ_S_BCNT1_I32_B32 0xf +#define SQ_S_BCNT1_I32_B64 0x10 +#define SQ_S_FF0_I32_B32 0x11 +#define SQ_S_FF0_I32_B64 0x12 +#define SQ_S_FF1_I32_B32 0x13 +#define SQ_S_FF1_I32_B64 0x14 +#define SQ_S_FLBIT_I32_B32 0x15 +#define SQ_S_FLBIT_I32_B64 0x16 +#define SQ_S_FLBIT_I32 0x17 +#define SQ_S_FLBIT_I32_I64 0x18 +#define SQ_S_SEXT_I32_I8 0x19 +#define SQ_S_SEXT_I32_I16 0x1a +#define SQ_S_BITSET0_B32 0x1b +#define SQ_S_BITSET0_B64 0x1c +#define SQ_S_BITSET1_B32 0x1d +#define SQ_S_BITSET1_B64 0x1e +#define SQ_S_GETPC_B64 0x1f +#define SQ_S_SETPC_B64 0x20 +#define SQ_S_SWAPPC_B64 0x21 +#define SQ_S_RFE_B64 0x22 +#define SQ_S_AND_SAVEEXEC_B64 0x24 +#define SQ_S_OR_SAVEEXEC_B64 0x25 +#define SQ_S_XOR_SAVEEXEC_B64 0x26 +#define SQ_S_ANDN2_SAVEEXEC_B64 0x27 +#define SQ_S_ORN2_SAVEEXEC_B64 0x28 +#define SQ_S_NAND_SAVEEXEC_B64 0x29 +#define SQ_S_NOR_SAVEEXEC_B64 0x2a +#define SQ_S_XNOR_SAVEEXEC_B64 0x2b +#define SQ_S_QUADMASK_B32 0x2c +#define SQ_S_QUADMASK_B64 0x2d +#define SQ_S_MOVRELS_B32 0x2e +#define SQ_S_MOVRELS_B64 0x2f +#define SQ_S_MOVRELD_B32 0x30 +#define SQ_S_MOVRELD_B64 0x31 +#define SQ_S_CBRANCH_JOIN 0x32 +#define SQ_S_MOV_REGRD_B32 0x33 +#define SQ_S_ABS_I32 0x34 +#define SQ_S_MOV_FED_B32 0x35 +#define SQ_ATTR0 0x0 +#define SQ_S_MOVK_I32 0x0 +#define SQ_S_CMOVK_I32 0x2 +#define SQ_S_CMPK_EQ_I32 0x3 +#define SQ_S_CMPK_LG_I32 0x4 +#define SQ_S_CMPK_GT_I32 0x5 +#define SQ_S_CMPK_GE_I32 0x6 +#define SQ_S_CMPK_LT_I32 0x7 +#define SQ_S_CMPK_LE_I32 0x8 +#define SQ_S_CMPK_EQ_U32 0x9 +#define SQ_S_CMPK_LG_U32 0xa +#define SQ_S_CMPK_GT_U32 0xb +#define SQ_S_CMPK_GE_U32 0xc +#define SQ_S_CMPK_LT_U32 0xd +#define SQ_S_CMPK_LE_U32 0xe +#define SQ_S_ADDK_I32 0xf +#define SQ_S_MULK_I32 0x10 +#define SQ_S_CBRANCH_I_FORK 0x11 +#define SQ_S_GETREG_B32 0x12 +#define SQ_S_SETREG_B32 0x13 +#define SQ_S_GETREG_REGRD_B32 0x14 +#define SQ_S_SETREG_IMM32_B32 0x15 +#define SQ_TBA_LO 0x6c +#define SQ_TBA_HI 0x6d +#define SQ_TMA_LO 0x6e +#define SQ_TMA_HI 0x6f +#define SQ_TTMP0 0x70 +#define SQ_TTMP1 0x71 +#define SQ_TTMP2 0x72 +#define SQ_TTMP3 0x73 +#define SQ_TTMP4 0x74 +#define SQ_TTMP5 0x75 +#define SQ_TTMP6 0x76 +#define SQ_TTMP7 0x77 +#define SQ_TTMP8 0x78 +#define SQ_TTMP9 0x79 +#define SQ_TTMP10 0x7a +#define SQ_TTMP11 0x7b +#define SQ_VGPR0 0x0 +#define SQ_EXP 0x0 +#define SQ_EXP_MRT0 0x0 +#define SQ_EXP_MRTZ 0x8 +#define SQ_EXP_NULL 0x9 +#define SQ_EXP_POS0 0xc +#define SQ_EXP_PARAM0 0x20 +#define SQ_CNT1 0x0 +#define SQ_CNT2 0x1 +#define SQ_CNT3 0x2 +#define SQ_CNT4 0x3 +#define SQ_F 0x0 +#define SQ_LT 0x1 +#define SQ_EQ 0x2 +#define SQ_LE 0x3 +#define SQ_GT 0x4 +#define SQ_LG 0x5 +#define SQ_GE 0x6 +#define SQ_O 0x7 +#define SQ_U 0x8 +#define SQ_NGE 0x9 +#define SQ_NLG 0xa +#define SQ_NGT 0xb +#define SQ_NLE 0xc +#define SQ_NEQ 0xd +#define SQ_NLT 0xe +#define SQ_TRU 0xf +#define SQ_V_CMP_F_F32 0x0 +#define SQ_V_CMP_LT_F32 0x1 +#define SQ_V_CMP_EQ_F32 0x2 +#define SQ_V_CMP_LE_F32 0x3 +#define SQ_V_CMP_GT_F32 0x4 +#define SQ_V_CMP_LG_F32 0x5 +#define SQ_V_CMP_GE_F32 0x6 +#define SQ_V_CMP_O_F32 0x7 +#define SQ_V_CMP_U_F32 0x8 +#define SQ_V_CMP_NGE_F32 0x9 +#define SQ_V_CMP_NLG_F32 0xa +#define SQ_V_CMP_NGT_F32 0xb +#define SQ_V_CMP_NLE_F32 0xc +#define SQ_V_CMP_NEQ_F32 0xd +#define SQ_V_CMP_NLT_F32 0xe +#define SQ_V_CMP_TRU_F32 0xf +#define SQ_V_CMPX_F_F32 0x10 +#define SQ_V_CMPX_LT_F32 0x11 +#define SQ_V_CMPX_EQ_F32 0x12 +#define SQ_V_CMPX_LE_F32 0x13 +#define SQ_V_CMPX_GT_F32 0x14 +#define SQ_V_CMPX_LG_F32 0x15 +#define SQ_V_CMPX_GE_F32 0x16 +#define SQ_V_CMPX_O_F32 0x17 +#define SQ_V_CMPX_U_F32 0x18 +#define SQ_V_CMPX_NGE_F32 0x19 +#define SQ_V_CMPX_NLG_F32 0x1a +#define SQ_V_CMPX_NGT_F32 0x1b +#define SQ_V_CMPX_NLE_F32 0x1c +#define SQ_V_CMPX_NEQ_F32 0x1d +#define SQ_V_CMPX_NLT_F32 0x1e +#define SQ_V_CMPX_TRU_F32 0x1f +#define SQ_V_CMP_F_F64 0x20 +#define SQ_V_CMP_LT_F64 0x21 +#define SQ_V_CMP_EQ_F64 0x22 +#define SQ_V_CMP_LE_F64 0x23 +#define SQ_V_CMP_GT_F64 0x24 +#define SQ_V_CMP_LG_F64 0x25 +#define SQ_V_CMP_GE_F64 0x26 +#define SQ_V_CMP_O_F64 0x27 +#define SQ_V_CMP_U_F64 0x28 +#define SQ_V_CMP_NGE_F64 0x29 +#define SQ_V_CMP_NLG_F64 0x2a +#define SQ_V_CMP_NGT_F64 0x2b +#define SQ_V_CMP_NLE_F64 0x2c +#define SQ_V_CMP_NEQ_F64 0x2d +#define SQ_V_CMP_NLT_F64 0x2e +#define SQ_V_CMP_TRU_F64 0x2f +#define SQ_V_CMPX_F_F64 0x30 +#define SQ_V_CMPX_LT_F64 0x31 +#define SQ_V_CMPX_EQ_F64 0x32 +#define SQ_V_CMPX_LE_F64 0x33 +#define SQ_V_CMPX_GT_F64 0x34 +#define SQ_V_CMPX_LG_F64 0x35 +#define SQ_V_CMPX_GE_F64 0x36 +#define SQ_V_CMPX_O_F64 0x37 +#define SQ_V_CMPX_U_F64 0x38 +#define SQ_V_CMPX_NGE_F64 0x39 +#define SQ_V_CMPX_NLG_F64 0x3a +#define SQ_V_CMPX_NGT_F64 0x3b +#define SQ_V_CMPX_NLE_F64 0x3c +#define SQ_V_CMPX_NEQ_F64 0x3d +#define SQ_V_CMPX_NLT_F64 0x3e +#define SQ_V_CMPX_TRU_F64 0x3f +#define SQ_V_CMPS_F_F32 0x40 +#define SQ_V_CMPS_LT_F32 0x41 +#define SQ_V_CMPS_EQ_F32 0x42 +#define SQ_V_CMPS_LE_F32 0x43 +#define SQ_V_CMPS_GT_F32 0x44 +#define SQ_V_CMPS_LG_F32 0x45 +#define SQ_V_CMPS_GE_F32 0x46 +#define SQ_V_CMPS_O_F32 0x47 +#define SQ_V_CMPS_U_F32 0x48 +#define SQ_V_CMPS_NGE_F32 0x49 +#define SQ_V_CMPS_NLG_F32 0x4a +#define SQ_V_CMPS_NGT_F32 0x4b +#define SQ_V_CMPS_NLE_F32 0x4c +#define SQ_V_CMPS_NEQ_F32 0x4d +#define SQ_V_CMPS_NLT_F32 0x4e +#define SQ_V_CMPS_TRU_F32 0x4f +#define SQ_V_CMPSX_F_F32 0x50 +#define SQ_V_CMPSX_LT_F32 0x51 +#define SQ_V_CMPSX_EQ_F32 0x52 +#define SQ_V_CMPSX_LE_F32 0x53 +#define SQ_V_CMPSX_GT_F32 0x54 +#define SQ_V_CMPSX_LG_F32 0x55 +#define SQ_V_CMPSX_GE_F32 0x56 +#define SQ_V_CMPSX_O_F32 0x57 +#define SQ_V_CMPSX_U_F32 0x58 +#define SQ_V_CMPSX_NGE_F32 0x59 +#define SQ_V_CMPSX_NLG_F32 0x5a +#define SQ_V_CMPSX_NGT_F32 0x5b +#define SQ_V_CMPSX_NLE_F32 0x5c +#define SQ_V_CMPSX_NEQ_F32 0x5d +#define SQ_V_CMPSX_NLT_F32 0x5e +#define SQ_V_CMPSX_TRU_F32 0x5f +#define SQ_V_CMPS_F_F64 0x60 +#define SQ_V_CMPS_LT_F64 0x61 +#define SQ_V_CMPS_EQ_F64 0x62 +#define SQ_V_CMPS_LE_F64 0x63 +#define SQ_V_CMPS_GT_F64 0x64 +#define SQ_V_CMPS_LG_F64 0x65 +#define SQ_V_CMPS_GE_F64 0x66 +#define SQ_V_CMPS_O_F64 0x67 +#define SQ_V_CMPS_U_F64 0x68 +#define SQ_V_CMPS_NGE_F64 0x69 +#define SQ_V_CMPS_NLG_F64 0x6a +#define SQ_V_CMPS_NGT_F64 0x6b +#define SQ_V_CMPS_NLE_F64 0x6c +#define SQ_V_CMPS_NEQ_F64 0x6d +#define SQ_V_CMPS_NLT_F64 0x6e +#define SQ_V_CMPS_TRU_F64 0x6f +#define SQ_V_CMPSX_F_F64 0x70 +#define SQ_V_CMPSX_LT_F64 0x71 +#define SQ_V_CMPSX_EQ_F64 0x72 +#define SQ_V_CMPSX_LE_F64 0x73 +#define SQ_V_CMPSX_GT_F64 0x74 +#define SQ_V_CMPSX_LG_F64 0x75 +#define SQ_V_CMPSX_GE_F64 0x76 +#define SQ_V_CMPSX_O_F64 0x77 +#define SQ_V_CMPSX_U_F64 0x78 +#define SQ_V_CMPSX_NGE_F64 0x79 +#define SQ_V_CMPSX_NLG_F64 0x7a +#define SQ_V_CMPSX_NGT_F64 0x7b +#define SQ_V_CMPSX_NLE_F64 0x7c +#define SQ_V_CMPSX_NEQ_F64 0x7d +#define SQ_V_CMPSX_NLT_F64 0x7e +#define SQ_V_CMPSX_TRU_F64 0x7f +#define SQ_V_CMP_F_I32 0x80 +#define SQ_V_CMP_LT_I32 0x81 +#define SQ_V_CMP_EQ_I32 0x82 +#define SQ_V_CMP_LE_I32 0x83 +#define SQ_V_CMP_GT_I32 0x84 +#define SQ_V_CMP_NE_I32 0x85 +#define SQ_V_CMP_GE_I32 0x86 +#define SQ_V_CMP_T_I32 0x87 +#define SQ_V_CMPX_F_I32 0x90 +#define SQ_V_CMPX_LT_I32 0x91 +#define SQ_V_CMPX_EQ_I32 0x92 +#define SQ_V_CMPX_LE_I32 0x93 +#define SQ_V_CMPX_GT_I32 0x94 +#define SQ_V_CMPX_NE_I32 0x95 +#define SQ_V_CMPX_GE_I32 0x96 +#define SQ_V_CMPX_T_I32 0x97 +#define SQ_V_CMP_F_I64 0xa0 +#define SQ_V_CMP_LT_I64 0xa1 +#define SQ_V_CMP_EQ_I64 0xa2 +#define SQ_V_CMP_LE_I64 0xa3 +#define SQ_V_CMP_GT_I64 0xa4 +#define SQ_V_CMP_NE_I64 0xa5 +#define SQ_V_CMP_GE_I64 0xa6 +#define SQ_V_CMP_T_I64 0xa7 +#define SQ_V_CMPX_F_I64 0xb0 +#define SQ_V_CMPX_LT_I64 0xb1 +#define SQ_V_CMPX_EQ_I64 0xb2 +#define SQ_V_CMPX_LE_I64 0xb3 +#define SQ_V_CMPX_GT_I64 0xb4 +#define SQ_V_CMPX_NE_I64 0xb5 +#define SQ_V_CMPX_GE_I64 0xb6 +#define SQ_V_CMPX_T_I64 0xb7 +#define SQ_V_CMP_F_U32 0xc0 +#define SQ_V_CMP_LT_U32 0xc1 +#define SQ_V_CMP_EQ_U32 0xc2 +#define SQ_V_CMP_LE_U32 0xc3 +#define SQ_V_CMP_GT_U32 0xc4 +#define SQ_V_CMP_NE_U32 0xc5 +#define SQ_V_CMP_GE_U32 0xc6 +#define SQ_V_CMP_T_U32 0xc7 +#define SQ_V_CMPX_F_U32 0xd0 +#define SQ_V_CMPX_LT_U32 0xd1 +#define SQ_V_CMPX_EQ_U32 0xd2 +#define SQ_V_CMPX_LE_U32 0xd3 +#define SQ_V_CMPX_GT_U32 0xd4 +#define SQ_V_CMPX_NE_U32 0xd5 +#define SQ_V_CMPX_GE_U32 0xd6 +#define SQ_V_CMPX_T_U32 0xd7 +#define SQ_V_CMP_F_U64 0xe0 +#define SQ_V_CMP_LT_U64 0xe1 +#define SQ_V_CMP_EQ_U64 0xe2 +#define SQ_V_CMP_LE_U64 0xe3 +#define SQ_V_CMP_GT_U64 0xe4 +#define SQ_V_CMP_NE_U64 0xe5 +#define SQ_V_CMP_GE_U64 0xe6 +#define SQ_V_CMP_T_U64 0xe7 +#define SQ_V_CMPX_F_U64 0xf0 +#define SQ_V_CMPX_LT_U64 0xf1 +#define SQ_V_CMPX_EQ_U64 0xf2 +#define SQ_V_CMPX_LE_U64 0xf3 +#define SQ_V_CMPX_GT_U64 0xf4 +#define SQ_V_CMPX_NE_U64 0xf5 +#define SQ_V_CMPX_GE_U64 0xf6 +#define SQ_V_CMPX_T_U64 0xf7 +#define SQ_V_CMP_CLASS_F32 0x88 +#define SQ_V_CMPX_CLASS_F32 0x98 +#define SQ_V_CMP_CLASS_F64 0xa8 +#define SQ_V_CMPX_CLASS_F64 0xb8 +#define SQ_SGPR0 0x0 +#define SQ_F 0x0 +#define SQ_LT 0x1 +#define SQ_EQ 0x2 +#define SQ_LE 0x3 +#define SQ_GT 0x4 +#define SQ_NE 0x5 +#define SQ_GE 0x6 +#define SQ_T 0x7 +#define SQ_SRC_64_INT 0xc0 +#define SQ_SRC_M_1_INT 0xc1 +#define SQ_SRC_M_2_INT 0xc2 +#define SQ_SRC_M_3_INT 0xc3 +#define SQ_SRC_M_4_INT 0xc4 +#define SQ_SRC_M_5_INT 0xc5 +#define SQ_SRC_M_6_INT 0xc6 +#define SQ_SRC_M_7_INT 0xc7 +#define SQ_SRC_M_8_INT 0xc8 +#define SQ_SRC_M_9_INT 0xc9 +#define SQ_SRC_M_10_INT 0xca +#define SQ_SRC_M_11_INT 0xcb +#define SQ_SRC_M_12_INT 0xcc +#define SQ_SRC_M_13_INT 0xcd +#define SQ_SRC_M_14_INT 0xce +#define SQ_SRC_M_15_INT 0xcf +#define SQ_SRC_M_16_INT 0xd0 +#define SQ_SRC_0_5 0xf0 +#define SQ_SRC_M_0_5 0xf1 +#define SQ_SRC_1 0xf2 +#define SQ_SRC_M_1 0xf3 +#define SQ_SRC_2 0xf4 +#define SQ_SRC_M_2 0xf5 +#define SQ_SRC_4 0xf6 +#define SQ_SRC_M_4 0xf7 +#define SQ_SRC_0 0x80 +#define SQ_SRC_1_INT 0x81 +#define SQ_SRC_2_INT 0x82 +#define SQ_SRC_3_INT 0x83 +#define SQ_SRC_4_INT 0x84 +#define SQ_SRC_5_INT 0x85 +#define SQ_SRC_6_INT 0x86 +#define SQ_SRC_7_INT 0x87 +#define SQ_SRC_8_INT 0x88 +#define SQ_SRC_9_INT 0x89 +#define SQ_SRC_10_INT 0x8a +#define SQ_SRC_11_INT 0x8b +#define SQ_SRC_12_INT 0x8c +#define SQ_SRC_13_INT 0x8d +#define SQ_SRC_14_INT 0x8e +#define SQ_SRC_15_INT 0x8f +#define SQ_SRC_16_INT 0x90 +#define SQ_SRC_17_INT 0x91 +#define SQ_SRC_18_INT 0x92 +#define SQ_SRC_19_INT 0x93 +#define SQ_SRC_20_INT 0x94 +#define SQ_SRC_21_INT 0x95 +#define SQ_SRC_22_INT 0x96 +#define SQ_SRC_23_INT 0x97 +#define SQ_SRC_24_INT 0x98 +#define SQ_SRC_25_INT 0x99 +#define SQ_SRC_26_INT 0x9a +#define SQ_SRC_27_INT 0x9b +#define SQ_SRC_28_INT 0x9c +#define SQ_SRC_29_INT 0x9d +#define SQ_SRC_30_INT 0x9e +#define SQ_SRC_31_INT 0x9f +#define SQ_SRC_32_INT 0xa0 +#define SQ_SRC_33_INT 0xa1 +#define SQ_SRC_34_INT 0xa2 +#define SQ_SRC_35_INT 0xa3 +#define SQ_SRC_36_INT 0xa4 +#define SQ_SRC_37_INT 0xa5 +#define SQ_SRC_38_INT 0xa6 +#define SQ_SRC_39_INT 0xa7 +#define SQ_SRC_40_INT 0xa8 +#define SQ_SRC_41_INT 0xa9 +#define SQ_SRC_42_INT 0xaa +#define SQ_SRC_43_INT 0xab +#define SQ_SRC_44_INT 0xac +#define SQ_SRC_45_INT 0xad +#define SQ_SRC_46_INT 0xae +#define SQ_SRC_47_INT 0xaf +#define SQ_SRC_48_INT 0xb0 +#define SQ_SRC_49_INT 0xb1 +#define SQ_SRC_50_INT 0xb2 +#define SQ_SRC_51_INT 0xb3 +#define SQ_SRC_52_INT 0xb4 +#define SQ_SRC_53_INT 0xb5 +#define SQ_SRC_54_INT 0xb6 +#define SQ_SRC_55_INT 0xb7 +#define SQ_SRC_56_INT 0xb8 +#define SQ_SRC_57_INT 0xb9 +#define SQ_SRC_58_INT 0xba +#define SQ_SRC_59_INT 0xbb +#define SQ_SRC_60_INT 0xbc +#define SQ_SRC_61_INT 0xbd +#define SQ_SRC_62_INT 0xbe +#define SQ_SRC_63_INT 0xbf +#define SQ_BUFFER_LOAD_FORMAT_X 0x0 +#define SQ_BUFFER_LOAD_FORMAT_XY 0x1 +#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2 +#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x3 +#define SQ_BUFFER_STORE_FORMAT_X 0x4 +#define SQ_BUFFER_STORE_FORMAT_XY 0x5 +#define SQ_BUFFER_STORE_FORMAT_XYZ 0x6 +#define SQ_BUFFER_STORE_FORMAT_XYZW 0x7 +#define SQ_BUFFER_LOAD_UBYTE 0x8 +#define SQ_BUFFER_LOAD_SBYTE 0x9 +#define SQ_BUFFER_LOAD_USHORT 0xa +#define SQ_BUFFER_LOAD_SSHORT 0xb +#define SQ_BUFFER_LOAD_DWORD 0xc +#define SQ_BUFFER_LOAD_DWORDX2 0xd +#define SQ_BUFFER_LOAD_DWORDX4 0xe +#define SQ_BUFFER_LOAD_DWORDX3 0xf +#define SQ_BUFFER_STORE_BYTE 0x18 +#define SQ_BUFFER_STORE_SHORT 0x1a +#define SQ_BUFFER_STORE_DWORD 0x1c +#define SQ_BUFFER_STORE_DWORDX2 0x1d +#define SQ_BUFFER_STORE_DWORDX4 0x1e +#define SQ_BUFFER_STORE_DWORDX3 0x1f +#define SQ_BUFFER_ATOMIC_SWAP 0x30 +#define SQ_BUFFER_ATOMIC_CMPSWAP 0x31 +#define SQ_BUFFER_ATOMIC_ADD 0x32 +#define SQ_BUFFER_ATOMIC_SUB 0x33 +#define SQ_BUFFER_ATOMIC_SMIN 0x35 +#define SQ_BUFFER_ATOMIC_UMIN 0x36 +#define SQ_BUFFER_ATOMIC_SMAX 0x37 +#define SQ_BUFFER_ATOMIC_UMAX 0x38 +#define SQ_BUFFER_ATOMIC_AND 0x39 +#define SQ_BUFFER_ATOMIC_OR 0x3a +#define SQ_BUFFER_ATOMIC_XOR 0x3b +#define SQ_BUFFER_ATOMIC_INC 0x3c +#define SQ_BUFFER_ATOMIC_DEC 0x3d +#define SQ_BUFFER_ATOMIC_FCMPSWAP 0x3e +#define SQ_BUFFER_ATOMIC_FMIN 0x3f +#define SQ_BUFFER_ATOMIC_FMAX 0x40 +#define SQ_BUFFER_ATOMIC_SWAP_X2 0x50 +#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x51 +#define SQ_BUFFER_ATOMIC_ADD_X2 0x52 +#define SQ_BUFFER_ATOMIC_SUB_X2 0x53 +#define SQ_BUFFER_ATOMIC_SMIN_X2 0x55 +#define SQ_BUFFER_ATOMIC_UMIN_X2 0x56 +#define SQ_BUFFER_ATOMIC_SMAX_X2 0x57 +#define SQ_BUFFER_ATOMIC_UMAX_X2 0x58 +#define SQ_BUFFER_ATOMIC_AND_X2 0x59 +#define SQ_BUFFER_ATOMIC_OR_X2 0x5a +#define SQ_BUFFER_ATOMIC_XOR_X2 0x5b +#define SQ_BUFFER_ATOMIC_INC_X2 0x5c +#define SQ_BUFFER_ATOMIC_DEC_X2 0x5d +#define SQ_BUFFER_ATOMIC_FCMPSWAP_X2 0x5e +#define SQ_BUFFER_ATOMIC_FMIN_X2 0x5f +#define SQ_BUFFER_ATOMIC_FMAX_X2 0x60 +#define SQ_BUFFER_WBINVL1_VOL 0x70 +#define SQ_BUFFER_WBINVL1 0x71 +#define SQ_DS_ADD_U32 0x0 +#define SQ_DS_SUB_U32 0x1 +#define SQ_DS_RSUB_U32 0x2 +#define SQ_DS_INC_U32 0x3 +#define SQ_DS_DEC_U32 0x4 +#define SQ_DS_MIN_I32 0x5 +#define SQ_DS_MAX_I32 0x6 +#define SQ_DS_MIN_U32 0x7 +#define SQ_DS_MAX_U32 0x8 +#define SQ_DS_AND_B32 0x9 +#define SQ_DS_OR_B32 0xa +#define SQ_DS_XOR_B32 0xb +#define SQ_DS_MSKOR_B32 0xc +#define SQ_DS_WRITE_B32 0xd +#define SQ_DS_WRITE2_B32 0xe +#define SQ_DS_WRITE2ST64_B32 0xf +#define SQ_DS_CMPST_B32 0x10 +#define SQ_DS_CMPST_F32 0x11 +#define SQ_DS_MIN_F32 0x12 +#define SQ_DS_MAX_F32 0x13 +#define SQ_DS_NOP 0x14 +#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x18 +#define SQ_DS_GWS_INIT 0x19 +#define SQ_DS_GWS_SEMA_V 0x1a +#define SQ_DS_GWS_SEMA_BR 0x1b +#define SQ_DS_GWS_SEMA_P 0x1c +#define SQ_DS_GWS_BARRIER 0x1d +#define SQ_DS_WRITE_B8 0x1e +#define SQ_DS_WRITE_B16 0x1f +#define SQ_DS_ADD_RTN_U32 0x20 +#define SQ_DS_SUB_RTN_U32 0x21 +#define SQ_DS_RSUB_RTN_U32 0x22 +#define SQ_DS_INC_RTN_U32 0x23 +#define SQ_DS_DEC_RTN_U32 0x24 +#define SQ_DS_MIN_RTN_I32 0x25 +#define SQ_DS_MAX_RTN_I32 0x26 +#define SQ_DS_MIN_RTN_U32 0x27 +#define SQ_DS_MAX_RTN_U32 0x28 +#define SQ_DS_AND_RTN_B32 0x29 +#define SQ_DS_OR_RTN_B32 0x2a +#define SQ_DS_XOR_RTN_B32 0x2b +#define SQ_DS_MSKOR_RTN_B32 0x2c +#define SQ_DS_WRXCHG_RTN_B32 0x2d +#define SQ_DS_WRXCHG2_RTN_B32 0x2e +#define SQ_DS_WRXCHG2ST64_RTN_B32 0x2f +#define SQ_DS_CMPST_RTN_B32 0x30 +#define SQ_DS_CMPST_RTN_F32 0x31 +#define SQ_DS_MIN_RTN_F32 0x32 +#define SQ_DS_MAX_RTN_F32 0x33 +#define SQ_DS_WRAP_RTN_B32 0x34 +#define SQ_DS_SWIZZLE_B32 0x35 +#define SQ_DS_READ_B32 0x36 +#define SQ_DS_READ2_B32 0x37 +#define SQ_DS_READ2ST64_B32 0x38 +#define SQ_DS_READ_I8 0x39 +#define SQ_DS_READ_U8 0x3a +#define SQ_DS_READ_I16 0x3b +#define SQ_DS_READ_U16 0x3c +#define SQ_DS_CONSUME 0x3d +#define SQ_DS_APPEND 0x3e +#define SQ_DS_ORDERED_COUNT 0x3f +#define SQ_DS_ADD_U64 0x40 +#define SQ_DS_SUB_U64 0x41 +#define SQ_DS_RSUB_U64 0x42 +#define SQ_DS_INC_U64 0x43 +#define SQ_DS_DEC_U64 0x44 +#define SQ_DS_MIN_I64 0x45 +#define SQ_DS_MAX_I64 0x46 +#define SQ_DS_MIN_U64 0x47 +#define SQ_DS_MAX_U64 0x48 +#define SQ_DS_AND_B64 0x49 +#define SQ_DS_OR_B64 0x4a +#define SQ_DS_XOR_B64 0x4b +#define SQ_DS_MSKOR_B64 0x4c +#define SQ_DS_WRITE_B64 0x4d +#define SQ_DS_WRITE2_B64 0x4e +#define SQ_DS_WRITE2ST64_B64 0x4f +#define SQ_DS_CMPST_B64 0x50 +#define SQ_DS_CMPST_F64 0x51 +#define SQ_DS_MIN_F64 0x52 +#define SQ_DS_MAX_F64 0x53 +#define SQ_DS_ADD_RTN_U64 0x60 +#define SQ_DS_SUB_RTN_U64 0x61 +#define SQ_DS_RSUB_RTN_U64 0x62 +#define SQ_DS_INC_RTN_U64 0x63 +#define SQ_DS_DEC_RTN_U64 0x64 +#define SQ_DS_MIN_RTN_I64 0x65 +#define SQ_DS_MAX_RTN_I64 0x66 +#define SQ_DS_MIN_RTN_U64 0x67 +#define SQ_DS_MAX_RTN_U64 0x68 +#define SQ_DS_AND_RTN_B64 0x69 +#define SQ_DS_OR_RTN_B64 0x6a +#define SQ_DS_XOR_RTN_B64 0x6b +#define SQ_DS_MSKOR_RTN_B64 0x6c +#define SQ_DS_WRXCHG_RTN_B64 0x6d +#define SQ_DS_WRXCHG2_RTN_B64 0x6e +#define SQ_DS_WRXCHG2ST64_RTN_B64 0x6f +#define SQ_DS_CMPST_RTN_B64 0x70 +#define SQ_DS_CMPST_RTN_F64 0x71 +#define SQ_DS_MIN_RTN_F64 0x72 +#define SQ_DS_MAX_RTN_F64 0x73 +#define SQ_DS_READ_B64 0x76 +#define SQ_DS_READ2_B64 0x77 +#define SQ_DS_READ2ST64_B64 0x78 +#define SQ_DS_CONDXCHG32_RTN_B64 0x7e +#define SQ_DS_ADD_SRC2_U32 0x80 +#define SQ_DS_SUB_SRC2_U32 0x81 +#define SQ_DS_RSUB_SRC2_U32 0x82 +#define SQ_DS_INC_SRC2_U32 0x83 +#define SQ_DS_DEC_SRC2_U32 0x84 +#define SQ_DS_MIN_SRC2_I32 0x85 +#define SQ_DS_MAX_SRC2_I32 0x86 +#define SQ_DS_MIN_SRC2_U32 0x87 +#define SQ_DS_MAX_SRC2_U32 0x88 +#define SQ_DS_AND_SRC2_B32 0x89 +#define SQ_DS_OR_SRC2_B32 0x8a +#define SQ_DS_XOR_SRC2_B32 0x8b +#define SQ_DS_WRITE_SRC2_B32 0x8d +#define SQ_DS_MIN_SRC2_F32 0x92 +#define SQ_DS_MAX_SRC2_F32 0x93 +#define SQ_DS_ADD_SRC2_U64 0xc0 +#define SQ_DS_SUB_SRC2_U64 0xc1 +#define SQ_DS_RSUB_SRC2_U64 0xc2 +#define SQ_DS_INC_SRC2_U64 0xc3 +#define SQ_DS_DEC_SRC2_U64 0xc4 +#define SQ_DS_MIN_SRC2_I64 0xc5 +#define SQ_DS_MAX_SRC2_I64 0xc6 +#define SQ_DS_MIN_SRC2_U64 0xc7 +#define SQ_DS_MAX_SRC2_U64 0xc8 +#define SQ_DS_AND_SRC2_B64 0xc9 +#define SQ_DS_OR_SRC2_B64 0xca +#define SQ_DS_XOR_SRC2_B64 0xcb +#define SQ_DS_WRITE_SRC2_B64 0xcd +#define SQ_DS_MIN_SRC2_F64 0xd2 +#define SQ_DS_MAX_SRC2_F64 0xd3 +#define SQ_DS_WRITE_B96 0xde +#define SQ_DS_WRITE_B128 0xdf +#define SQ_DS_CONDXCHG32_RTN_B128 0xfd +#define SQ_DS_READ_B96 0xfe +#define SQ_DS_READ_B128 0xff +#define SQ_SRC_SCC 0xfd +#define SQ_OMOD_OFF 0x0 +#define SQ_OMOD_M2 0x1 +#define SQ_OMOD_M4 0x2 +#define SQ_OMOD_D2 0x3 +#define SQ_EXP_GDS0 0x18 +#define SQ_GS_OP_NOP 0x0 +#define SQ_GS_OP_CUT 0x1 +#define SQ_GS_OP_EMIT 0x2 +#define SQ_GS_OP_EMIT_CUT 0x3 +#define SQ_IMAGE_LOAD 0x0 +#define SQ_IMAGE_LOAD_MIP 0x1 +#define SQ_IMAGE_LOAD_PCK 0x2 +#define SQ_IMAGE_LOAD_PCK_SGN 0x3 +#define SQ_IMAGE_LOAD_MIP_PCK 0x4 +#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x5 +#define SQ_IMAGE_STORE 0x8 +#define SQ_IMAGE_STORE_MIP 0x9 +#define SQ_IMAGE_STORE_PCK 0xa +#define SQ_IMAGE_STORE_MIP_PCK 0xb +#define SQ_IMAGE_GET_RESINFO 0xe +#define SQ_IMAGE_ATOMIC_SWAP 0xf +#define SQ_IMAGE_ATOMIC_CMPSWAP 0x10 +#define SQ_IMAGE_ATOMIC_ADD 0x11 +#define SQ_IMAGE_ATOMIC_SUB 0x12 +#define SQ_IMAGE_ATOMIC_SMIN 0x14 +#define SQ_IMAGE_ATOMIC_UMIN 0x15 +#define SQ_IMAGE_ATOMIC_SMAX 0x16 +#define SQ_IMAGE_ATOMIC_UMAX 0x17 +#define SQ_IMAGE_ATOMIC_AND 0x18 +#define SQ_IMAGE_ATOMIC_OR 0x19 +#define SQ_IMAGE_ATOMIC_XOR 0x1a +#define SQ_IMAGE_ATOMIC_INC 0x1b +#define SQ_IMAGE_ATOMIC_DEC 0x1c +#define SQ_IMAGE_ATOMIC_FCMPSWAP 0x1d +#define SQ_IMAGE_ATOMIC_FMIN 0x1e +#define SQ_IMAGE_ATOMIC_FMAX 0x1f +#define SQ_IMAGE_SAMPLE 0x20 +#define SQ_IMAGE_SAMPLE_CL 0x21 +#define SQ_IMAGE_SAMPLE_D 0x22 +#define SQ_IMAGE_SAMPLE_D_CL 0x23 +#define SQ_IMAGE_SAMPLE_L 0x24 +#define SQ_IMAGE_SAMPLE_B 0x25 +#define SQ_IMAGE_SAMPLE_B_CL 0x26 +#define SQ_IMAGE_SAMPLE_LZ 0x27 +#define SQ_IMAGE_SAMPLE_C 0x28 +#define SQ_IMAGE_SAMPLE_C_CL 0x29 +#define SQ_IMAGE_SAMPLE_C_D 0x2a +#define SQ_IMAGE_SAMPLE_C_D_CL 0x2b +#define SQ_IMAGE_SAMPLE_C_L 0x2c +#define SQ_IMAGE_SAMPLE_C_B 0x2d +#define SQ_IMAGE_SAMPLE_C_B_CL 0x2e +#define SQ_IMAGE_SAMPLE_C_LZ 0x2f +#define SQ_IMAGE_SAMPLE_O 0x30 +#define SQ_IMAGE_SAMPLE_CL_O 0x31 +#define SQ_IMAGE_SAMPLE_D_O 0x32 +#define SQ_IMAGE_SAMPLE_D_CL_O 0x33 +#define SQ_IMAGE_SAMPLE_L_O 0x34 +#define SQ_IMAGE_SAMPLE_B_O 0x35 +#define SQ_IMAGE_SAMPLE_B_CL_O 0x36 +#define SQ_IMAGE_SAMPLE_LZ_O 0x37 +#define SQ_IMAGE_SAMPLE_C_O 0x38 +#define SQ_IMAGE_SAMPLE_C_CL_O 0x39 +#define SQ_IMAGE_SAMPLE_C_D_O 0x3a +#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x3b +#define SQ_IMAGE_SAMPLE_C_L_O 0x3c +#define SQ_IMAGE_SAMPLE_C_B_O 0x3d +#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x3e +#define SQ_IMAGE_SAMPLE_C_LZ_O 0x3f +#define SQ_IMAGE_GATHER4 0x40 +#define SQ_IMAGE_GATHER4_CL 0x41 +#define SQ_IMAGE_GATHER4_L 0x44 +#define SQ_IMAGE_GATHER4_B 0x45 +#define SQ_IMAGE_GATHER4_B_CL 0x46 +#define SQ_IMAGE_GATHER4_LZ 0x47 +#define SQ_IMAGE_GATHER4_C 0x48 +#define SQ_IMAGE_GATHER4_C_CL 0x49 +#define SQ_IMAGE_GATHER4_C_L 0x4c +#define SQ_IMAGE_GATHER4_C_B 0x4d +#define SQ_IMAGE_GATHER4_C_B_CL 0x4e +#define SQ_IMAGE_GATHER4_C_LZ 0x4f +#define SQ_IMAGE_GATHER4_O 0x50 +#define SQ_IMAGE_GATHER4_CL_O 0x51 +#define SQ_IMAGE_GATHER4_L_O 0x54 +#define SQ_IMAGE_GATHER4_B_O 0x55 +#define SQ_IMAGE_GATHER4_B_CL_O 0x56 +#define SQ_IMAGE_GATHER4_LZ_O 0x57 +#define SQ_IMAGE_GATHER4_C_O 0x58 +#define SQ_IMAGE_GATHER4_C_CL_O 0x59 +#define SQ_IMAGE_GATHER4_C_L_O 0x5c +#define SQ_IMAGE_GATHER4_C_B_O 0x5d +#define SQ_IMAGE_GATHER4_C_B_CL_O 0x5e +#define SQ_IMAGE_GATHER4_C_LZ_O 0x5f +#define SQ_IMAGE_GET_LOD 0x60 +#define SQ_IMAGE_SAMPLE_CD 0x68 +#define SQ_IMAGE_SAMPLE_CD_CL 0x69 +#define SQ_IMAGE_SAMPLE_C_CD 0x6a +#define SQ_IMAGE_SAMPLE_C_CD_CL 0x6b +#define SQ_IMAGE_SAMPLE_CD_O 0x6c +#define SQ_IMAGE_SAMPLE_CD_CL_O 0x6d +#define SQ_IMAGE_SAMPLE_C_CD_O 0x6e +#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6f +#define SQ_IMAGE_RSRC256 0x7e +#define SQ_IMAGE_SAMPLER 0x7f +#define SQ_SRC_VCCZ 0xfb +#define SQ_SRC_VGPR0 0x100 +#define SQ_DFMT_INVALID 0x0 +#define SQ_DFMT_8 0x1 +#define SQ_DFMT_16 0x2 +#define SQ_DFMT_8_8 0x3 +#define SQ_DFMT_32 0x4 +#define SQ_DFMT_16_16 0x5 +#define SQ_DFMT_10_11_11 0x6 +#define SQ_DFMT_11_11_10 0x7 +#define SQ_DFMT_10_10_10_2 0x8 +#define SQ_DFMT_2_10_10_10 0x9 +#define SQ_DFMT_8_8_8_8 0xa +#define SQ_DFMT_32_32 0xb +#define SQ_DFMT_16_16_16_16 0xc +#define SQ_DFMT_32_32_32 0xd +#define SQ_DFMT_32_32_32_32 0xe +#define SQ_TBUFFER_LOAD_FORMAT_X 0x0 +#define SQ_TBUFFER_LOAD_FORMAT_XY 0x1 +#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2 +#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x3 +#define SQ_TBUFFER_STORE_FORMAT_X 0x4 +#define SQ_TBUFFER_STORE_FORMAT_XY 0x5 +#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x6 +#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x7 +#define SQ_CHAN_X 0x0 +#define SQ_CHAN_Y 0x1 +#define SQ_CHAN_Z 0x2 +#define SQ_CHAN_W 0x3 +#define SQ_EXEC_LO 0x7e +#define SQ_EXEC_HI 0x7f +#define SQ_S_LOAD_DWORD 0x0 +#define SQ_S_LOAD_DWORDX2 0x1 +#define SQ_S_LOAD_DWORDX4 0x2 +#define SQ_S_LOAD_DWORDX8 0x3 +#define SQ_S_LOAD_DWORDX16 0x4 +#define SQ_S_BUFFER_LOAD_DWORD 0x8 +#define SQ_S_BUFFER_LOAD_DWORDX2 0x9 +#define SQ_S_BUFFER_LOAD_DWORDX4 0xa +#define SQ_S_BUFFER_LOAD_DWORDX8 0xb +#define SQ_S_BUFFER_LOAD_DWORDX16 0xc +#define SQ_S_DCACHE_INV_VOL 0x1d +#define SQ_S_MEMTIME 0x1e +#define SQ_S_DCACHE_INV 0x1f +#define SQ_V_NOP 0x0 +#define SQ_V_MOV_B32 0x1 +#define SQ_V_READFIRSTLANE_B32 0x2 +#define SQ_V_CVT_I32_F64 0x3 +#define SQ_V_CVT_F64_I32 0x4 +#define SQ_V_CVT_F32_I32 0x5 +#define SQ_V_CVT_F32_U32 0x6 +#define SQ_V_CVT_U32_F32 0x7 +#define SQ_V_CVT_I32_F32 0x8 +#define SQ_V_MOV_FED_B32 0x9 +#define SQ_V_CVT_F16_F32 0xa +#define SQ_V_CVT_F32_F16 0xb +#define SQ_V_CVT_RPI_I32_F32 0xc +#define SQ_V_CVT_FLR_I32_F32 0xd +#define SQ_V_CVT_OFF_F32_I4 0xe +#define SQ_V_CVT_F32_F64 0xf +#define SQ_V_CVT_F64_F32 0x10 +#define SQ_V_CVT_F32_UBYTE0 0x11 +#define SQ_V_CVT_F32_UBYTE1 0x12 +#define SQ_V_CVT_F32_UBYTE2 0x13 +#define SQ_V_CVT_F32_UBYTE3 0x14 +#define SQ_V_CVT_U32_F64 0x15 +#define SQ_V_CVT_F64_U32 0x16 +#define SQ_V_TRUNC_F64 0x17 +#define SQ_V_CEIL_F64 0x18 +#define SQ_V_RNDNE_F64 0x19 +#define SQ_V_FLOOR_F64 0x1a +#define SQ_V_FRACT_F32 0x20 +#define SQ_V_TRUNC_F32 0x21 +#define SQ_V_CEIL_F32 0x22 +#define SQ_V_RNDNE_F32 0x23 +#define SQ_V_FLOOR_F32 0x24 +#define SQ_V_EXP_F32 0x25 +#define SQ_V_LOG_CLAMP_F32 0x26 +#define SQ_V_LOG_F32 0x27 +#define SQ_V_RCP_CLAMP_F32 0x28 +#define SQ_V_RCP_LEGACY_F32 0x29 +#define SQ_V_RCP_F32 0x2a +#define SQ_V_RCP_IFLAG_F32 0x2b +#define SQ_V_RSQ_CLAMP_F32 0x2c +#define SQ_V_RSQ_LEGACY_F32 0x2d +#define SQ_V_RSQ_F32 0x2e +#define SQ_V_RCP_F64 0x2f +#define SQ_V_RCP_CLAMP_F64 0x30 +#define SQ_V_RSQ_F64 0x31 +#define SQ_V_RSQ_CLAMP_F64 0x32 +#define SQ_V_SQRT_F32 0x33 +#define SQ_V_SQRT_F64 0x34 +#define SQ_V_SIN_F32 0x35 +#define SQ_V_COS_F32 0x36 +#define SQ_V_NOT_B32 0x37 +#define SQ_V_BFREV_B32 0x38 +#define SQ_V_FFBH_U32 0x39 +#define SQ_V_FFBL_B32 0x3a +#define SQ_V_FFBH_I32 0x3b +#define SQ_V_FREXP_EXP_I32_F64 0x3c +#define SQ_V_FREXP_MANT_F64 0x3d +#define SQ_V_FRACT_F64 0x3e +#define SQ_V_FREXP_EXP_I32_F32 0x3f +#define SQ_V_FREXP_MANT_F32 0x40 +#define SQ_V_CLREXCP 0x41 +#define SQ_V_MOVRELD_B32 0x42 +#define SQ_V_MOVRELS_B32 0x43 +#define SQ_V_MOVRELSD_B32 0x44 +#define SQ_V_LOG_LEGACY_F32 0x45 +#define SQ_V_EXP_LEGACY_F32 0x46 +#define SQ_NFMT_UNORM 0x0 +#define SQ_NFMT_SNORM 0x1 +#define SQ_NFMT_USCALED 0x2 +#define SQ_NFMT_SSCALED 0x3 +#define SQ_NFMT_UINT 0x4 +#define SQ_NFMT_SINT 0x5 +#define SQ_NFMT_SNORM_OGL 0x6 +#define SQ_NFMT_FLOAT 0x7 +#define SQ_V_OP1_OFFSET 0x180 +#define SQ_V_OP2_OFFSET 0x100 +#define SQ_V_OPC_OFFSET 0x0 +#define SQ_V_INTERP_P1_F32 0x0 +#define SQ_V_INTERP_P2_F32 0x1 +#define SQ_V_INTERP_MOV_F32 0x2 +#define SQ_S_NOP 0x0 +#define SQ_S_ENDPGM 0x1 +#define SQ_S_BRANCH 0x2 +#define SQ_S_CBRANCH_SCC0 0x4 +#define SQ_S_CBRANCH_SCC1 0x5 +#define SQ_S_CBRANCH_VCCZ 0x6 +#define SQ_S_CBRANCH_VCCNZ 0x7 +#define SQ_S_CBRANCH_EXECZ 0x8 +#define SQ_S_CBRANCH_EXECNZ 0x9 +#define SQ_S_BARRIER 0xa +#define SQ_S_SETKILL 0xb +#define SQ_S_WAITCNT 0xc +#define SQ_S_SETHALT 0xd +#define SQ_S_SLEEP 0xe +#define SQ_S_SETPRIO 0xf +#define SQ_S_SENDMSG 0x10 +#define SQ_S_SENDMSGHALT 0x11 +#define SQ_S_TRAP 0x12 +#define SQ_S_ICACHE_INV 0x13 +#define SQ_S_INCPERFLEVEL 0x14 +#define SQ_S_DECPERFLEVEL 0x15 +#define SQ_S_TTRACEDATA 0x16 +#define SQ_S_CBRANCH_CDBGSYS 0x17 +#define SQ_S_CBRANCH_CDBGUSER 0x18 +#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19 +#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1a +#define SQ_SRC_LITERAL 0xff +#define SQ_VCC_LO 0x6a +#define SQ_VCC_HI 0x6b +#define SQ_PARAM_P10 0x0 +#define SQ_PARAM_P20 0x1 +#define SQ_PARAM_P0 0x2 +#define SQ_SRC_LDS_DIRECT 0xfe +#define SQ_FLAT_SCRATCH_LO 0x68 +#define SQ_FLAT_SCRATCH_HI 0x69 +#define SQ_V_CNDMASK_B32 0x0 +#define SQ_V_READLANE_B32 0x1 +#define SQ_V_WRITELANE_B32 0x2 +#define SQ_V_ADD_F32 0x3 +#define SQ_V_SUB_F32 0x4 +#define SQ_V_SUBREV_F32 0x5 +#define SQ_V_MAC_LEGACY_F32 0x6 +#define SQ_V_MUL_LEGACY_F32 0x7 +#define SQ_V_MUL_F32 0x8 +#define SQ_V_MUL_I32_I24 0x9 +#define SQ_V_MUL_HI_I32_I24 0xa +#define SQ_V_MUL_U32_U24 0xb +#define SQ_V_MUL_HI_U32_U24 0xc +#define SQ_V_MIN_LEGACY_F32 0xd +#define SQ_V_MAX_LEGACY_F32 0xe +#define SQ_V_MIN_F32 0xf +#define SQ_V_MAX_F32 0x10 +#define SQ_V_MIN_I32 0x11 +#define SQ_V_MAX_I32 0x12 +#define SQ_V_MIN_U32 0x13 +#define SQ_V_MAX_U32 0x14 +#define SQ_V_LSHR_B32 0x15 +#define SQ_V_LSHRREV_B32 0x16 +#define SQ_V_ASHR_I32 0x17 +#define SQ_V_ASHRREV_I32 0x18 +#define SQ_V_LSHL_B32 0x19 +#define SQ_V_LSHLREV_B32 0x1a +#define SQ_V_AND_B32 0x1b +#define SQ_V_OR_B32 0x1c +#define SQ_V_XOR_B32 0x1d +#define SQ_V_BFM_B32 0x1e +#define SQ_V_MAC_F32 0x1f +#define SQ_V_MADMK_F32 0x20 +#define SQ_V_MADAK_F32 0x21 +#define SQ_V_BCNT_U32_B32 0x22 +#define SQ_V_MBCNT_LO_U32_B32 0x23 +#define SQ_V_MBCNT_HI_U32_B32 0x24 +#define SQ_V_ADD_I32 0x25 +#define SQ_V_SUB_I32 0x26 +#define SQ_V_SUBREV_I32 0x27 +#define SQ_V_ADDC_U32 0x28 +#define SQ_V_SUBB_U32 0x29 +#define SQ_V_SUBBREV_U32 0x2a +#define SQ_V_LDEXP_F32 0x2b +#define SQ_V_CVT_PKACCUM_U8_F32 0x2c +#define SQ_V_CVT_PKNORM_I16_F32 0x2d +#define SQ_V_CVT_PKNORM_U16_F32 0x2e +#define SQ_V_CVT_PKRTZ_F16_F32 0x2f +#define SQ_V_CVT_PK_U16_U32 0x30 +#define SQ_V_CVT_PK_I16_I32 0x31 +#define SQ_FLAT_LOAD_UBYTE 0x8 +#define SQ_FLAT_LOAD_SBYTE 0x9 +#define SQ_FLAT_LOAD_USHORT 0xa +#define SQ_FLAT_LOAD_SSHORT 0xb +#define SQ_FLAT_LOAD_DWORD 0xc +#define SQ_FLAT_LOAD_DWORDX2 0xd +#define SQ_FLAT_LOAD_DWORDX4 0xe +#define SQ_FLAT_LOAD_DWORDX3 0xf +#define SQ_FLAT_STORE_BYTE 0x18 +#define SQ_FLAT_STORE_SHORT 0x1a +#define SQ_FLAT_STORE_DWORD 0x1c +#define SQ_FLAT_STORE_DWORDX2 0x1d +#define SQ_FLAT_STORE_DWORDX4 0x1e +#define SQ_FLAT_STORE_DWORDX3 0x1f +#define SQ_FLAT_ATOMIC_SWAP 0x30 +#define SQ_FLAT_ATOMIC_CMPSWAP 0x31 +#define SQ_FLAT_ATOMIC_ADD 0x32 +#define SQ_FLAT_ATOMIC_SUB 0x33 +#define SQ_FLAT_ATOMIC_SMIN 0x35 +#define SQ_FLAT_ATOMIC_UMIN 0x36 +#define SQ_FLAT_ATOMIC_SMAX 0x37 +#define SQ_FLAT_ATOMIC_UMAX 0x38 +#define SQ_FLAT_ATOMIC_AND 0x39 +#define SQ_FLAT_ATOMIC_OR 0x3a +#define SQ_FLAT_ATOMIC_XOR 0x3b +#define SQ_FLAT_ATOMIC_INC 0x3c +#define SQ_FLAT_ATOMIC_DEC 0x3d +#define SQ_FLAT_ATOMIC_FCMPSWAP 0x3e +#define SQ_FLAT_ATOMIC_FMIN 0x3f +#define SQ_FLAT_ATOMIC_FMAX 0x40 +#define SQ_FLAT_ATOMIC_SWAP_X2 0x50 +#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x51 +#define SQ_FLAT_ATOMIC_ADD_X2 0x52 +#define SQ_FLAT_ATOMIC_SUB_X2 0x53 +#define SQ_FLAT_ATOMIC_SMIN_X2 0x55 +#define SQ_FLAT_ATOMIC_UMIN_X2 0x56 +#define SQ_FLAT_ATOMIC_SMAX_X2 0x57 +#define SQ_FLAT_ATOMIC_UMAX_X2 0x58 +#define SQ_FLAT_ATOMIC_AND_X2 0x59 +#define SQ_FLAT_ATOMIC_OR_X2 0x5a +#define SQ_FLAT_ATOMIC_XOR_X2 0x5b +#define SQ_FLAT_ATOMIC_INC_X2 0x5c +#define SQ_FLAT_ATOMIC_DEC_X2 0x5d +#define SQ_FLAT_ATOMIC_FCMPSWAP_X2 0x5e +#define SQ_FLAT_ATOMIC_FMIN_X2 0x5f +#define SQ_FLAT_ATOMIC_FMAX_X2 0x60 +#define SQ_S_CMP_EQ_I32 0x0 +#define SQ_S_CMP_LG_I32 0x1 +#define SQ_S_CMP_GT_I32 0x2 +#define SQ_S_CMP_GE_I32 0x3 +#define SQ_S_CMP_LT_I32 0x4 +#define SQ_S_CMP_LE_I32 0x5 +#define SQ_S_CMP_EQ_U32 0x6 +#define SQ_S_CMP_LG_U32 0x7 +#define SQ_S_CMP_GT_U32 0x8 +#define SQ_S_CMP_GE_U32 0x9 +#define SQ_S_CMP_LT_U32 0xa +#define SQ_S_CMP_LE_U32 0xb +#define SQ_S_BITCMP0_B32 0xc +#define SQ_S_BITCMP1_B32 0xd +#define SQ_S_BITCMP0_B64 0xe +#define SQ_S_BITCMP1_B64 0xf +#define SQ_S_SETVSKIP 0x10 +#define SQ_M0 0x7c +#define SQ_V_MAD_LEGACY_F32 0x140 +#define SQ_V_MAD_F32 0x141 +#define SQ_V_MAD_I32_I24 0x142 +#define SQ_V_MAD_U32_U24 0x143 +#define SQ_V_CUBEID_F32 0x144 +#define SQ_V_CUBESC_F32 0x145 +#define SQ_V_CUBETC_F32 0x146 +#define SQ_V_CUBEMA_F32 0x147 +#define SQ_V_BFE_U32 0x148 +#define SQ_V_BFE_I32 0x149 +#define SQ_V_BFI_B32 0x14a +#define SQ_V_FMA_F32 0x14b +#define SQ_V_FMA_F64 0x14c +#define SQ_V_LERP_U8 0x14d +#define SQ_V_ALIGNBIT_B32 0x14e +#define SQ_V_ALIGNBYTE_B32 0x14f +#define SQ_V_MULLIT_F32 0x150 +#define SQ_V_MIN3_F32 0x151 +#define SQ_V_MIN3_I32 0x152 +#define SQ_V_MIN3_U32 0x153 +#define SQ_V_MAX3_F32 0x154 +#define SQ_V_MAX3_I32 0x155 +#define SQ_V_MAX3_U32 0x156 +#define SQ_V_MED3_F32 0x157 +#define SQ_V_MED3_I32 0x158 +#define SQ_V_MED3_U32 0x159 +#define SQ_V_SAD_U8 0x15a +#define SQ_V_SAD_HI_U8 0x15b +#define SQ_V_SAD_U16 0x15c +#define SQ_V_SAD_U32 0x15d +#define SQ_V_CVT_PK_U8_F32 0x15e +#define SQ_V_DIV_FIXUP_F32 0x15f +#define SQ_V_DIV_FIXUP_F64 0x160 +#define SQ_V_LSHL_B64 0x161 +#define SQ_V_LSHR_B64 0x162 +#define SQ_V_ASHR_I64 0x163 +#define SQ_V_ADD_F64 0x164 +#define SQ_V_MUL_F64 0x165 +#define SQ_V_MIN_F64 0x166 +#define SQ_V_MAX_F64 0x167 +#define SQ_V_LDEXP_F64 0x168 +#define SQ_V_MUL_LO_U32 0x169 +#define SQ_V_MUL_HI_U32 0x16a +#define SQ_V_MUL_LO_I32 0x16b +#define SQ_V_MUL_HI_I32 0x16c +#define SQ_V_DIV_SCALE_F32 0x16d +#define SQ_V_DIV_SCALE_F64 0x16e +#define SQ_V_DIV_FMAS_F32 0x16f +#define SQ_V_DIV_FMAS_F64 0x170 +#define SQ_V_MSAD_U8 0x171 +#define SQ_V_QSAD_PK_U16_U8 0x172 +#define SQ_V_MQSAD_PK_U16_U8 0x173 +#define SQ_V_TRIG_PREOP_F64 0x174 +#define SQ_V_MQSAD_U32_U8 0x175 +#define SQ_V_MAD_U64_U32 0x176 +#define SQ_V_MAD_I64_I32 0x177 +#define SQ_VCC_ALL 0x0 +#define SQ_SRC_EXECZ 0xfc +#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x1 +#define SQ_SYSMSG_OP_REG_RD 0x2 +#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x3 +#define SQ_SYSMSG_OP_TTRACE_PC 0x4 +#define SQ_HW_REG_MODE 0x1 +#define SQ_HW_REG_STATUS 0x2 +#define SQ_HW_REG_TRAPSTS 0x3 +#define SQ_HW_REG_HW_ID 0x4 +#define SQ_HW_REG_GPR_ALLOC 0x5 +#define SQ_HW_REG_LDS_ALLOC 0x6 +#define SQ_HW_REG_IB_STS 0x7 +#define SQ_HW_REG_PC_LO 0x8 +#define SQ_HW_REG_PC_HI 0x9 +#define SQ_HW_REG_INST_DW0 0xa +#define SQ_HW_REG_INST_DW1 0xb +#define SQ_HW_REG_IB_DBG0 0xc +#define SQ_S_ADD_U32 0x0 +#define SQ_S_SUB_U32 0x1 +#define SQ_S_ADD_I32 0x2 +#define SQ_S_SUB_I32 0x3 +#define SQ_S_ADDC_U32 0x4 +#define SQ_S_SUBB_U32 0x5 +#define SQ_S_MIN_I32 0x6 +#define SQ_S_MIN_U32 0x7 +#define SQ_S_MAX_I32 0x8 +#define SQ_S_MAX_U32 0x9 +#define SQ_S_CSELECT_B32 0xa +#define SQ_S_CSELECT_B64 0xb +#define SQ_S_AND_B32 0xe +#define SQ_S_AND_B64 0xf +#define SQ_S_OR_B32 0x10 +#define SQ_S_OR_B64 0x11 +#define SQ_S_XOR_B32 0x12 +#define SQ_S_XOR_B64 0x13 +#define SQ_S_ANDN2_B32 0x14 +#define SQ_S_ANDN2_B64 0x15 +#define SQ_S_ORN2_B32 0x16 +#define SQ_S_ORN2_B64 0x17 +#define SQ_S_NAND_B32 0x18 +#define SQ_S_NAND_B64 0x19 +#define SQ_S_NOR_B32 0x1a +#define SQ_S_NOR_B64 0x1b +#define SQ_S_XNOR_B32 0x1c +#define SQ_S_XNOR_B64 0x1d +#define SQ_S_LSHL_B32 0x1e +#define SQ_S_LSHL_B64 0x1f +#define SQ_S_LSHR_B32 0x20 +#define SQ_S_LSHR_B64 0x21 +#define SQ_S_ASHR_I32 0x22 +#define SQ_S_ASHR_I64 0x23 +#define SQ_S_BFM_B32 0x24 +#define SQ_S_BFM_B64 0x25 +#define SQ_S_MUL_I32 0x26 +#define SQ_S_BFE_U32 0x27 +#define SQ_S_BFE_I32 0x28 +#define SQ_S_BFE_U64 0x29 +#define SQ_S_BFE_I64 0x2a +#define SQ_S_CBRANCH_G_FORK 0x2b +#define SQ_S_ABSDIFF_I32 0x2c +#define SQ_MSG_INTERRUPT 0x1 +#define SQ_MSG_GS 0x2 +#define SQ_MSG_GS_DONE 0x3 +#define SQ_MSG_SYSMSG 0xf +typedef enum TEX_BORDER_COLOR_TYPE { + TEX_BorderColor_TransparentBlack = 0x0, + TEX_BorderColor_OpaqueBlack = 0x1, + TEX_BorderColor_OpaqueWhite = 0x2, + TEX_BorderColor_Register = 0x3, +} TEX_BORDER_COLOR_TYPE; +typedef enum TEX_CHROMA_KEY { + TEX_ChromaKey_Disabled = 0x0, + TEX_ChromaKey_Kill = 0x1, + TEX_ChromaKey_Blend = 0x2, + TEX_ChromaKey_RESERVED_3 = 0x3, +} TEX_CHROMA_KEY; +typedef enum TEX_CLAMP { + TEX_Clamp_Repeat = 0x0, + TEX_Clamp_Mirror = 0x1, + TEX_Clamp_ClampToLast = 0x2, + TEX_Clamp_MirrorOnceToLast = 0x3, + TEX_Clamp_ClampHalfToBorder = 0x4, + TEX_Clamp_MirrorOnceHalfToBorder = 0x5, + TEX_Clamp_ClampToBorder = 0x6, + TEX_Clamp_MirrorOnceToBorder = 0x7, +} TEX_CLAMP; +typedef enum TEX_COORD_TYPE { + TEX_CoordType_Unnormalized = 0x0, + TEX_CoordType_Normalized = 0x1, +} TEX_COORD_TYPE; +typedef enum TEX_DEPTH_COMPARE_FUNCTION { + TEX_DepthCompareFunction_Never = 0x0, + TEX_DepthCompareFunction_Less = 0x1, + TEX_DepthCompareFunction_Equal = 0x2, + TEX_DepthCompareFunction_LessEqual = 0x3, + TEX_DepthCompareFunction_Greater = 0x4, + TEX_DepthCompareFunction_NotEqual = 0x5, + TEX_DepthCompareFunction_GreaterEqual = 0x6, + TEX_DepthCompareFunction_Always = 0x7, +} TEX_DEPTH_COMPARE_FUNCTION; +typedef enum TEX_DIM { + TEX_Dim_1D = 0x0, + TEX_Dim_2D = 0x1, + TEX_Dim_3D = 0x2, + TEX_Dim_CubeMap = 0x3, + TEX_Dim_1DArray = 0x4, + TEX_Dim_2DArray = 0x5, + TEX_Dim_2D_MSAA = 0x6, + TEX_Dim_2DArray_MSAA = 0x7, +} TEX_DIM; +typedef enum TEX_FORMAT_COMP { + TEX_FormatComp_Unsigned = 0x0, + TEX_FormatComp_Signed = 0x1, + TEX_FormatComp_UnsignedBiased = 0x2, + TEX_FormatComp_RESERVED_3 = 0x3, +} TEX_FORMAT_COMP; +typedef enum TEX_MAX_ANISO_RATIO { + TEX_MaxAnisoRatio_1to1 = 0x0, + TEX_MaxAnisoRatio_2to1 = 0x1, + TEX_MaxAnisoRatio_4to1 = 0x2, + TEX_MaxAnisoRatio_8to1 = 0x3, + TEX_MaxAnisoRatio_16to1 = 0x4, + TEX_MaxAnisoRatio_RESERVED_5 = 0x5, + TEX_MaxAnisoRatio_RESERVED_6 = 0x6, + TEX_MaxAnisoRatio_RESERVED_7 = 0x7, +} TEX_MAX_ANISO_RATIO; +typedef enum TEX_MIP_FILTER { + TEX_MipFilter_None = 0x0, + TEX_MipFilter_Point = 0x1, + TEX_MipFilter_Linear = 0x2, + TEX_MipFilter_RESERVED_3 = 0x3, +} TEX_MIP_FILTER; +typedef enum TEX_REQUEST_SIZE { + TEX_RequestSize_32B = 0x0, + TEX_RequestSize_64B = 0x1, + TEX_RequestSize_128B = 0x2, + TEX_RequestSize_2X64B = 0x3, +} TEX_REQUEST_SIZE; +typedef enum TEX_SAMPLER_TYPE { + TEX_SamplerType_Invalid = 0x0, + TEX_SamplerType_Valid = 0x1, +} TEX_SAMPLER_TYPE; +typedef enum TEX_XY_FILTER { + TEX_XYFilter_Point = 0x0, + TEX_XYFilter_Linear = 0x1, + TEX_XYFilter_AnisoPoint = 0x2, + TEX_XYFilter_AnisoLinear = 0x3, +} TEX_XY_FILTER; +typedef enum TEX_Z_FILTER { + TEX_ZFilter_None = 0x0, + TEX_ZFilter_Point = 0x1, + TEX_ZFilter_Linear = 0x2, + TEX_ZFilter_RESERVED_3 = 0x3, +} TEX_Z_FILTER; +typedef enum VTX_CLAMP { + VTX_Clamp_ClampToZero = 0x0, + VTX_Clamp_ClampToNAN = 0x1, +} VTX_CLAMP; +typedef enum VTX_FETCH_TYPE { + VTX_FetchType_VertexData = 0x0, + VTX_FetchType_InstanceData = 0x1, + VTX_FetchType_NoIndexOffset = 0x2, + VTX_FetchType_RESERVED_3 = 0x3, +} VTX_FETCH_TYPE; +typedef enum VTX_FORMAT_COMP_ALL { + VTX_FormatCompAll_Unsigned = 0x0, + VTX_FormatCompAll_Signed = 0x1, +} VTX_FORMAT_COMP_ALL; +typedef enum VTX_MEM_REQUEST_SIZE { + VTX_MemRequestSize_32B = 0x0, + VTX_MemRequestSize_64B = 0x1, +} VTX_MEM_REQUEST_SIZE; +typedef enum TVX_DATA_FORMAT { + TVX_FMT_INVALID = 0x0, + TVX_FMT_8 = 0x1, + TVX_FMT_4_4 = 0x2, + TVX_FMT_3_3_2 = 0x3, + TVX_FMT_RESERVED_4 = 0x4, + TVX_FMT_16 = 0x5, + TVX_FMT_16_FLOAT = 0x6, + TVX_FMT_8_8 = 0x7, + TVX_FMT_5_6_5 = 0x8, + TVX_FMT_6_5_5 = 0x9, + TVX_FMT_1_5_5_5 = 0xa, + TVX_FMT_4_4_4_4 = 0xb, + TVX_FMT_5_5_5_1 = 0xc, + TVX_FMT_32 = 0xd, + TVX_FMT_32_FLOAT = 0xe, + TVX_FMT_16_16 = 0xf, + TVX_FMT_16_16_FLOAT = 0x10, + TVX_FMT_8_24 = 0x11, + TVX_FMT_8_24_FLOAT = 0x12, + TVX_FMT_24_8 = 0x13, + TVX_FMT_24_8_FLOAT = 0x14, + TVX_FMT_10_11_11 = 0x15, + TVX_FMT_10_11_11_FLOAT = 0x16, + TVX_FMT_11_11_10 = 0x17, + TVX_FMT_11_11_10_FLOAT = 0x18, + TVX_FMT_2_10_10_10 = 0x19, + TVX_FMT_8_8_8_8 = 0x1a, + TVX_FMT_10_10_10_2 = 0x1b, + TVX_FMT_X24_8_32_FLOAT = 0x1c, + TVX_FMT_32_32 = 0x1d, + TVX_FMT_32_32_FLOAT = 0x1e, + TVX_FMT_16_16_16_16 = 0x1f, + TVX_FMT_16_16_16_16_FLOAT = 0x20, + TVX_FMT_RESERVED_33 = 0x21, + TVX_FMT_32_32_32_32 = 0x22, + TVX_FMT_32_32_32_32_FLOAT = 0x23, + TVX_FMT_RESERVED_36 = 0x24, + TVX_FMT_1 = 0x25, + TVX_FMT_1_REVERSED = 0x26, + TVX_FMT_GB_GR = 0x27, + TVX_FMT_BG_RG = 0x28, + TVX_FMT_32_AS_8 = 0x29, + TVX_FMT_32_AS_8_8 = 0x2a, + TVX_FMT_5_9_9_9_SHAREDEXP = 0x2b, + TVX_FMT_8_8_8 = 0x2c, + TVX_FMT_16_16_16 = 0x2d, + TVX_FMT_16_16_16_FLOAT = 0x2e, + TVX_FMT_32_32_32 = 0x2f, + TVX_FMT_32_32_32_FLOAT = 0x30, + TVX_FMT_BC1 = 0x31, + TVX_FMT_BC2 = 0x32, + TVX_FMT_BC3 = 0x33, + TVX_FMT_BC4 = 0x34, + TVX_FMT_BC5 = 0x35, + TVX_FMT_APC0 = 0x36, + TVX_FMT_APC1 = 0x37, + TVX_FMT_APC2 = 0x38, + TVX_FMT_APC3 = 0x39, + TVX_FMT_APC4 = 0x3a, + TVX_FMT_APC5 = 0x3b, + TVX_FMT_APC6 = 0x3c, + TVX_FMT_APC7 = 0x3d, + TVX_FMT_CTX1 = 0x3e, + TVX_FMT_RESERVED_63 = 0x3f, +} TVX_DATA_FORMAT; +typedef enum TVX_DST_SEL { + TVX_DstSel_X = 0x0, + TVX_DstSel_Y = 0x1, + TVX_DstSel_Z = 0x2, + TVX_DstSel_W = 0x3, + TVX_DstSel_0f = 0x4, + TVX_DstSel_1f = 0x5, + TVX_DstSel_RESERVED_6 = 0x6, + TVX_DstSel_Mask = 0x7, +} TVX_DST_SEL; +typedef enum TVX_ENDIAN_SWAP { + TVX_EndianSwap_None = 0x0, + TVX_EndianSwap_8in16 = 0x1, + TVX_EndianSwap_8in32 = 0x2, + TVX_EndianSwap_8in64 = 0x3, +} TVX_ENDIAN_SWAP; +typedef enum TVX_INST { + TVX_Inst_NormalVertexFetch = 0x0, + TVX_Inst_SemanticVertexFetch = 0x1, + TVX_Inst_RESERVED_2 = 0x2, + TVX_Inst_LD = 0x3, + TVX_Inst_GetTextureResInfo = 0x4, + TVX_Inst_GetNumberOfSamples = 0x5, + TVX_Inst_GetLOD = 0x6, + TVX_Inst_GetGradientsH = 0x7, + TVX_Inst_GetGradientsV = 0x8, + TVX_Inst_SetTextureOffsets = 0x9, + TVX_Inst_KeepGradients = 0xa, + TVX_Inst_SetGradientsH = 0xb, + TVX_Inst_SetGradientsV = 0xc, + TVX_Inst_Pass = 0xd, + TVX_Inst_GetBufferResInfo = 0xe, + TVX_Inst_RESERVED_15 = 0xf, + TVX_Inst_Sample = 0x10, + TVX_Inst_Sample_L = 0x11, + TVX_Inst_Sample_LB = 0x12, + TVX_Inst_Sample_LZ = 0x13, + TVX_Inst_Sample_G = 0x14, + TVX_Inst_Gather4 = 0x15, + TVX_Inst_Sample_G_LB = 0x16, + TVX_Inst_Gather4_O = 0x17, + TVX_Inst_Sample_C = 0x18, + TVX_Inst_Sample_C_L = 0x19, + TVX_Inst_Sample_C_LB = 0x1a, + TVX_Inst_Sample_C_LZ = 0x1b, + TVX_Inst_Sample_C_G = 0x1c, + TVX_Inst_Gather4_C = 0x1d, + TVX_Inst_Sample_C_G_LB = 0x1e, + TVX_Inst_Gather4_C_O = 0x1f, +} TVX_INST; +typedef enum TVX_NUM_FORMAT_ALL { + TVX_NumFormatAll_Norm = 0x0, + TVX_NumFormatAll_Int = 0x1, + TVX_NumFormatAll_Scaled = 0x2, + TVX_NumFormatAll_RESERVED_3 = 0x3, +} TVX_NUM_FORMAT_ALL; +typedef enum TVX_SRC_SEL { + TVX_SrcSel_X = 0x0, + TVX_SrcSel_Y = 0x1, + TVX_SrcSel_Z = 0x2, + TVX_SrcSel_W = 0x3, + TVX_SrcSel_0f = 0x4, + TVX_SrcSel_1f = 0x5, +} TVX_SRC_SEL; +typedef enum TVX_SRF_MODE_ALL { + TVX_SRFModeAll_ZCMO = 0x0, + TVX_SRFModeAll_NZ = 0x1, +} TVX_SRF_MODE_ALL; +typedef enum TVX_TYPE { + TVX_Type_InvalidTextureResource = 0x0, + TVX_Type_InvalidVertexBuffer = 0x1, + TVX_Type_ValidTextureResource = 0x2, + TVX_Type_ValidVertexBuffer = 0x3, +} TVX_TYPE; +typedef enum TC_OP_MASKS { + TC_OP_MASK_FLUSH_DENROM = 0x8, + TC_OP_MASK_64 = 0x20, + TC_OP_MASK_NO_RTN = 0x40, +} TC_OP_MASKS; +typedef enum TC_OP { + TC_OP_READ = 0x0, + TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x1, + TC_OP_ATOMIC_FMIN_RTN_32 = 0x2, + TC_OP_ATOMIC_FMAX_RTN_32 = 0x3, + TC_OP_RESERVED_FOP_RTN_32_0 = 0x4, + TC_OP_RESERVED_FOP_RTN_32_1 = 0x5, + TC_OP_RESERVED_FOP_RTN_32_2 = 0x6, + TC_OP_ATOMIC_SWAP_RTN_32 = 0x7, + TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x8, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x9, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0xa, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0xb, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0xc, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0xd, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0xe, + TC_OP_ATOMIC_ADD_RTN_32 = 0xf, + TC_OP_ATOMIC_SUB_RTN_32 = 0x10, + TC_OP_ATOMIC_SMIN_RTN_32 = 0x11, + TC_OP_ATOMIC_UMIN_RTN_32 = 0x12, + TC_OP_ATOMIC_SMAX_RTN_32 = 0x13, + TC_OP_ATOMIC_UMAX_RTN_32 = 0x14, + TC_OP_ATOMIC_AND_RTN_32 = 0x15, + TC_OP_ATOMIC_OR_RTN_32 = 0x16, + TC_OP_ATOMIC_XOR_RTN_32 = 0x17, + TC_OP_ATOMIC_INC_RTN_32 = 0x18, + TC_OP_ATOMIC_DEC_RTN_32 = 0x19, + TC_OP_WBINVL1_VOL = 0x1a, + TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x1b, + TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1c, + TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x1d, + TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x1e, + TC_OP_RESERVED_NON_FLOAT_RTN_32_4 = 0x1f, + TC_OP_WRITE = 0x20, + TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x21, + TC_OP_ATOMIC_FMIN_RTN_64 = 0x22, + TC_OP_ATOMIC_FMAX_RTN_64 = 0x23, + TC_OP_RESERVED_FOP_RTN_64_0 = 0x24, + TC_OP_RESERVED_FOP_RTN_64_1 = 0x25, + TC_OP_RESERVED_FOP_RTN_64_2 = 0x26, + TC_OP_ATOMIC_SWAP_RTN_64 = 0x27, + TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x28, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x29, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x2a, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x2b, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x2c, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x2d, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_2 = 0x2e, + TC_OP_ATOMIC_ADD_RTN_64 = 0x2f, + TC_OP_ATOMIC_SUB_RTN_64 = 0x30, + TC_OP_ATOMIC_SMIN_RTN_64 = 0x31, + TC_OP_ATOMIC_UMIN_RTN_64 = 0x32, + TC_OP_ATOMIC_SMAX_RTN_64 = 0x33, + TC_OP_ATOMIC_UMAX_RTN_64 = 0x34, + TC_OP_ATOMIC_AND_RTN_64 = 0x35, + TC_OP_ATOMIC_OR_RTN_64 = 0x36, + TC_OP_ATOMIC_XOR_RTN_64 = 0x37, + TC_OP_ATOMIC_INC_RTN_64 = 0x38, + TC_OP_ATOMIC_DEC_RTN_64 = 0x39, + TC_OP_WBL2_VOL = 0x3a, + TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x3b, + TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x3c, + TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x3d, + TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x3e, + TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x3f, + TC_OP_WBINVL1 = 0x40, + TC_OP_ATOMIC_FCMPSWAP_32 = 0x41, + TC_OP_ATOMIC_FMIN_32 = 0x42, + TC_OP_ATOMIC_FMAX_32 = 0x43, + TC_OP_RESERVED_FOP_32_0 = 0x44, + TC_OP_RESERVED_FOP_32_1 = 0x45, + TC_OP_RESERVED_FOP_32_2 = 0x46, + TC_OP_ATOMIC_SWAP_32 = 0x47, + TC_OP_ATOMIC_CMPSWAP_32 = 0x48, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x49, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x4a, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x4b, + TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x4c, + TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x4d, + TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x4e, + TC_OP_ATOMIC_ADD_32 = 0x4f, + TC_OP_ATOMIC_SUB_32 = 0x50, + TC_OP_ATOMIC_SMIN_32 = 0x51, + TC_OP_ATOMIC_UMIN_32 = 0x52, + TC_OP_ATOMIC_SMAX_32 = 0x53, + TC_OP_ATOMIC_UMAX_32 = 0x54, + TC_OP_ATOMIC_AND_32 = 0x55, + TC_OP_ATOMIC_OR_32 = 0x56, + TC_OP_ATOMIC_XOR_32 = 0x57, + TC_OP_ATOMIC_INC_32 = 0x58, + TC_OP_ATOMIC_DEC_32 = 0x59, + TC_OP_INVL2_VOL = 0x5a, + TC_OP_RESERVED_NON_FLOAT_32_0 = 0x5b, + TC_OP_RESERVED_NON_FLOAT_32_1 = 0x5c, + TC_OP_RESERVED_NON_FLOAT_32_2 = 0x5d, + TC_OP_RESERVED_NON_FLOAT_32_3 = 0x5e, + TC_OP_RESERVED_NON_FLOAT_32_4 = 0x5f, + TC_OP_WBINVL2 = 0x60, + TC_OP_ATOMIC_FCMPSWAP_64 = 0x61, + TC_OP_ATOMIC_FMIN_64 = 0x62, + TC_OP_ATOMIC_FMAX_64 = 0x63, + TC_OP_RESERVED_FOP_64_0 = 0x64, + TC_OP_RESERVED_FOP_64_1 = 0x65, + TC_OP_RESERVED_FOP_64_2 = 0x66, + TC_OP_ATOMIC_SWAP_64 = 0x67, + TC_OP_ATOMIC_CMPSWAP_64 = 0x68, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x69, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x6a, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x6b, + TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x6c, + TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x6d, + TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x6e, + TC_OP_ATOMIC_ADD_64 = 0x6f, + TC_OP_ATOMIC_SUB_64 = 0x70, + TC_OP_ATOMIC_SMIN_64 = 0x71, + TC_OP_ATOMIC_UMIN_64 = 0x72, + TC_OP_ATOMIC_SMAX_64 = 0x73, + TC_OP_ATOMIC_UMAX_64 = 0x74, + TC_OP_ATOMIC_AND_64 = 0x75, + TC_OP_ATOMIC_OR_64 = 0x76, + TC_OP_ATOMIC_XOR_64 = 0x77, + TC_OP_ATOMIC_INC_64 = 0x78, + TC_OP_ATOMIC_DEC_64 = 0x79, + TC_OP_INVL1L2_VOL = 0x7a, + TC_OP_RESERVED_NON_FLOAT_64_0 = 0x7b, + TC_OP_RESERVED_NON_FLOAT_64_1 = 0x7c, + TC_OP_RESERVED_NON_FLOAT_64_2 = 0x7d, + TC_OP_RESERVED_NON_FLOAT_64_3 = 0x7e, + TC_OP_RESERVED_NON_FLOAT_64_4 = 0x7f, +} TC_OP; +typedef enum TC_CHUB_REQ_CREDITS_ENUM { + TC_CHUB_REQ_CREDITS = 0x10, +} TC_CHUB_REQ_CREDITS_ENUM; +typedef enum CHUB_TC_RET_CREDITS_ENUM { + CHUB_TC_RET_CREDITS = 0x20, +} CHUB_TC_RET_CREDITS_ENUM; +typedef enum TC_NACKS { + TC_NACK_NO_FAULT = 0x0, + TC_NACK_PAGE_FAULT = 0x1, + TC_NACK_PROTECTION_FAULT = 0x2, + TC_NACK_DATA_ERROR = 0x3, +} TC_NACKS; +typedef enum TCC_PERF_SEL { + TCC_PERF_SEL_NONE = 0x0, + TCC_PERF_SEL_CYCLE = 0x1, + TCC_PERF_SEL_BUSY = 0x2, + TCC_PERF_SEL_REQ = 0x3, + TCC_PERF_SEL_STREAMING_REQ = 0x4, + TCC_PERF_SEL_READ = 0x5, + TCC_PERF_SEL_WRITE = 0x6, + TCC_PERF_SEL_ATOMIC = 0x7, + TCC_PERF_SEL_WBINVL2 = 0x8, + TCC_PERF_SEL_WBINVL2_CYCLE = 0x9, + TCC_PERF_SEL_HIT = 0xa, + TCC_PERF_SEL_MISS = 0xb, + TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0xc, + TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0xd, + TCC_PERF_SEL_WRITEBACK = 0xe, + TCC_PERF_SEL_LATENCY_FIFO_FULL = 0xf, + TCC_PERF_SEL_SRC_FIFO_FULL = 0x10, + TCC_PERF_SEL_HOLE_FIFO_FULL = 0x11, + TCC_PERF_SEL_MC_WRREQ = 0x12, + TCC_PERF_SEL_MC_WRREQ_STALL = 0x13, + TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x14, + TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL = 0x15, + TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL = 0x16, + TCC_PERF_SEL_MC_WRREQ_LEVEL = 0x17, + TCC_PERF_SEL_MC_RDREQ = 0x18, + TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL = 0x19, + TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL = 0x1a, + TCC_PERF_SEL_MC_RDREQ_LEVEL = 0x1b, + TCC_PERF_SEL_TAG_STALL = 0x1c, + TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL = 0x1d, + TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x1e, + TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x1f, + TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x20, + TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x21, + TCC_PERF_SEL_BUBBLE = 0x22, + TCC_PERF_SEL_RETURN_ACK = 0x23, + TCC_PERF_SEL_RETURN_DATA = 0x24, + TCC_PERF_SEL_RETURN_HOLE = 0x25, + TCC_PERF_SEL_RETURN_ACK_HOLE = 0x26, + TCC_PERF_SEL_IB_STALL = 0x27, + TCC_PERF_SEL_TCA_LEVEL = 0x28, + TCC_PERF_SEL_HOLE_LEVEL = 0x29, + TCC_PERF_SEL_MC_RDRET_NACK = 0x2a, + TCC_PERF_SEL_MC_WRRET_NACK = 0x2b, + TCC_PERF_SEL_EXE_REQ = 0x2c, + TCC_PERF_SEL_CLIENT0_REQ = 0x40, + TCC_PERF_SEL_CLIENT1_REQ = 0x41, + TCC_PERF_SEL_CLIENT2_REQ = 0x42, + TCC_PERF_SEL_CLIENT3_REQ = 0x43, + TCC_PERF_SEL_CLIENT4_REQ = 0x44, + TCC_PERF_SEL_CLIENT5_REQ = 0x45, + TCC_PERF_SEL_CLIENT6_REQ = 0x46, + TCC_PERF_SEL_CLIENT7_REQ = 0x47, + TCC_PERF_SEL_CLIENT8_REQ = 0x48, + TCC_PERF_SEL_CLIENT9_REQ = 0x49, + TCC_PERF_SEL_CLIENT10_REQ = 0x4a, + TCC_PERF_SEL_CLIENT11_REQ = 0x4b, + TCC_PERF_SEL_CLIENT12_REQ = 0x4c, + TCC_PERF_SEL_CLIENT13_REQ = 0x4d, + TCC_PERF_SEL_CLIENT14_REQ = 0x4e, + TCC_PERF_SEL_CLIENT15_REQ = 0x4f, + TCC_PERF_SEL_CLIENT16_REQ = 0x50, + TCC_PERF_SEL_CLIENT17_REQ = 0x51, + TCC_PERF_SEL_CLIENT18_REQ = 0x52, + TCC_PERF_SEL_CLIENT19_REQ = 0x53, + TCC_PERF_SEL_CLIENT20_REQ = 0x54, + TCC_PERF_SEL_CLIENT21_REQ = 0x55, + TCC_PERF_SEL_CLIENT22_REQ = 0x56, + TCC_PERF_SEL_CLIENT23_REQ = 0x57, + TCC_PERF_SEL_CLIENT24_REQ = 0x58, + TCC_PERF_SEL_CLIENT25_REQ = 0x59, + TCC_PERF_SEL_CLIENT26_REQ = 0x5a, + TCC_PERF_SEL_CLIENT27_REQ = 0x5b, + TCC_PERF_SEL_CLIENT28_REQ = 0x5c, + TCC_PERF_SEL_CLIENT29_REQ = 0x5d, + TCC_PERF_SEL_CLIENT30_REQ = 0x5e, + TCC_PERF_SEL_CLIENT31_REQ = 0x5f, + TCC_PERF_SEL_CLIENT32_REQ = 0x60, + TCC_PERF_SEL_CLIENT33_REQ = 0x61, + TCC_PERF_SEL_CLIENT34_REQ = 0x62, + TCC_PERF_SEL_CLIENT35_REQ = 0x63, + TCC_PERF_SEL_CLIENT36_REQ = 0x64, + TCC_PERF_SEL_CLIENT37_REQ = 0x65, + TCC_PERF_SEL_CLIENT38_REQ = 0x66, + TCC_PERF_SEL_CLIENT39_REQ = 0x67, + TCC_PERF_SEL_CLIENT40_REQ = 0x68, + TCC_PERF_SEL_CLIENT41_REQ = 0x69, + TCC_PERF_SEL_CLIENT42_REQ = 0x6a, + TCC_PERF_SEL_CLIENT43_REQ = 0x6b, + TCC_PERF_SEL_CLIENT44_REQ = 0x6c, + TCC_PERF_SEL_CLIENT45_REQ = 0x6d, + TCC_PERF_SEL_CLIENT46_REQ = 0x6e, + TCC_PERF_SEL_CLIENT47_REQ = 0x6f, + TCC_PERF_SEL_CLIENT48_REQ = 0x70, + TCC_PERF_SEL_CLIENT49_REQ = 0x71, + TCC_PERF_SEL_CLIENT50_REQ = 0x72, + TCC_PERF_SEL_CLIENT51_REQ = 0x73, + TCC_PERF_SEL_CLIENT52_REQ = 0x74, + TCC_PERF_SEL_CLIENT53_REQ = 0x75, + TCC_PERF_SEL_CLIENT54_REQ = 0x76, + TCC_PERF_SEL_CLIENT55_REQ = 0x77, + TCC_PERF_SEL_CLIENT56_REQ = 0x78, + TCC_PERF_SEL_CLIENT57_REQ = 0x79, + TCC_PERF_SEL_CLIENT58_REQ = 0x7a, + TCC_PERF_SEL_CLIENT59_REQ = 0x7b, + TCC_PERF_SEL_CLIENT60_REQ = 0x7c, + TCC_PERF_SEL_CLIENT61_REQ = 0x7d, + TCC_PERF_SEL_CLIENT62_REQ = 0x7e, + TCC_PERF_SEL_CLIENT63_REQ = 0x7f, + TCC_PERF_SEL_NORMAL_WRITEBACK = 0x80, + TCC_PERF_SEL_TC_OP_WBL2_VOL_WRITEBACK = 0x81, + TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x82, + TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x83, + TCC_PERF_SEL_NORMAL_EVICT = 0x84, + TCC_PERF_SEL_TC_OP_INVL2_VOL_EVICT = 0x85, + TCC_PERF_SEL_TC_OP_INVL1L2_VOL_EVICT = 0x86, + TCC_PERF_SEL_TC_OP_WBL2_VOL_EVICT = 0x87, + TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x88, + TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x89, + TCC_PERF_SEL_ALL_TC_OP_INV_VOL_EVICT = 0x8a, + TCC_PERF_SEL_TC_OP_WBL2_VOL_CYCLE = 0x8b, + TCC_PERF_SEL_TC_OP_INVL2_VOL_CYCLE = 0x8c, + TCC_PERF_SEL_TC_OP_INVL1L2_VOL_CYCLE = 0x8d, + TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x8e, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x8f, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_CYCLE = 0x90, + TCC_PERF_SEL_TC_OP_WBL2_VOL_START = 0x91, + TCC_PERF_SEL_TC_OP_INVL2_VOL_START = 0x92, + TCC_PERF_SEL_TC_OP_INVL1L2_VOL_START = 0x93, + TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x94, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x95, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x96, + TCC_PERF_SEL_TC_OP_WBL2_VOL_FINISH = 0x97, + TCC_PERF_SEL_TC_OP_INVL2_VOL_FINISH = 0x98, + TCC_PERF_SEL_TC_OP_INVL1L2_VOL_FINISH = 0x99, + TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x9a, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x9b, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_FINISH = 0x9c, + TCC_PERF_SEL_VOL_MC_WRREQ = 0x9d, + TCC_PERF_SEL_VOL_MC_RDREQ = 0x9e, + TCC_PERF_SEL_VOL_REQ = 0x9f, +} TCC_PERF_SEL; +typedef enum TCA_PERF_SEL { + TCA_PERF_SEL_NONE = 0x0, + TCA_PERF_SEL_CYCLE = 0x1, + TCA_PERF_SEL_BUSY = 0x2, + TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x3, + TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x4, + TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x5, + TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x6, + TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x7, + TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x8, + TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x9, + TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0xa, + TCA_PERF_SEL_REQ_TCC0 = 0xb, + TCA_PERF_SEL_REQ_TCC1 = 0xc, + TCA_PERF_SEL_REQ_TCC2 = 0xd, + TCA_PERF_SEL_REQ_TCC3 = 0xe, + TCA_PERF_SEL_REQ_TCC4 = 0xf, + TCA_PERF_SEL_REQ_TCC5 = 0x10, + TCA_PERF_SEL_REQ_TCC6 = 0x11, + TCA_PERF_SEL_REQ_TCC7 = 0x12, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x13, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x14, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x15, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x16, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x17, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x18, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x19, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x1a, + TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x1b, + TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x1c, + TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d, + TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x1e, + TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x1f, + TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x20, + TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x21, + TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x22, + TCA_PERF_SEL_FORCED_HOLE_TCS = 0x23, + TCA_PERF_SEL_REQ_TCS = 0x24, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCS = 0x25, + TCA_PERF_SEL_CROSSBAR_STALL_TCS = 0x26, +} TCA_PERF_SEL; +typedef enum TCS_PERF_SEL { + TCS_PERF_SEL_NONE = 0x0, + TCS_PERF_SEL_CYCLE = 0x1, + TCS_PERF_SEL_BUSY = 0x2, + TCS_PERF_SEL_REQ = 0x3, + TCS_PERF_SEL_READ = 0x4, + TCS_PERF_SEL_WRITE = 0x5, + TCS_PERF_SEL_ATOMIC = 0x6, + TCS_PERF_SEL_HOLE_FIFO_FULL = 0x7, + TCS_PERF_SEL_REQ_FIFO_FULL = 0x8, + TCS_PERF_SEL_REQ_CREDIT_STALL = 0x9, + TCS_PERF_SEL_REQ_NO_SRC_DATA_STALL = 0xa, + TCS_PERF_SEL_REQ_STALL = 0xb, + TCS_PERF_SEL_TCS_CHUB_REQ_SEND = 0xc, + TCS_PERF_SEL_CHUB_TCS_RET_SEND = 0xd, + TCS_PERF_SEL_RETURN_ACK = 0xe, + TCS_PERF_SEL_RETURN_DATA = 0xf, + TCS_PERF_SEL_IB_TOTAL_REQUESTS_STALL = 0x10, + TCS_PERF_SEL_IB_STALL = 0x11, + TCS_PERF_SEL_TCA_LEVEL = 0x12, + TCS_PERF_SEL_HOLE_LEVEL = 0x13, + TCS_PERF_SEL_CHUB_LEVEL = 0x14, + TCS_PERF_SEL_CLIENT0_REQ = 0x40, + TCS_PERF_SEL_CLIENT1_REQ = 0x41, + TCS_PERF_SEL_CLIENT2_REQ = 0x42, + TCS_PERF_SEL_CLIENT3_REQ = 0x43, + TCS_PERF_SEL_CLIENT4_REQ = 0x44, + TCS_PERF_SEL_CLIENT5_REQ = 0x45, + TCS_PERF_SEL_CLIENT6_REQ = 0x46, + TCS_PERF_SEL_CLIENT7_REQ = 0x47, + TCS_PERF_SEL_CLIENT8_REQ = 0x48, + TCS_PERF_SEL_CLIENT9_REQ = 0x49, + TCS_PERF_SEL_CLIENT10_REQ = 0x4a, + TCS_PERF_SEL_CLIENT11_REQ = 0x4b, + TCS_PERF_SEL_CLIENT12_REQ = 0x4c, + TCS_PERF_SEL_CLIENT13_REQ = 0x4d, + TCS_PERF_SEL_CLIENT14_REQ = 0x4e, + TCS_PERF_SEL_CLIENT15_REQ = 0x4f, + TCS_PERF_SEL_CLIENT16_REQ = 0x50, + TCS_PERF_SEL_CLIENT17_REQ = 0x51, + TCS_PERF_SEL_CLIENT18_REQ = 0x52, + TCS_PERF_SEL_CLIENT19_REQ = 0x53, + TCS_PERF_SEL_CLIENT20_REQ = 0x54, + TCS_PERF_SEL_CLIENT21_REQ = 0x55, + TCS_PERF_SEL_CLIENT22_REQ = 0x56, + TCS_PERF_SEL_CLIENT23_REQ = 0x57, + TCS_PERF_SEL_CLIENT24_REQ = 0x58, + TCS_PERF_SEL_CLIENT25_REQ = 0x59, + TCS_PERF_SEL_CLIENT26_REQ = 0x5a, + TCS_PERF_SEL_CLIENT27_REQ = 0x5b, + TCS_PERF_SEL_CLIENT28_REQ = 0x5c, + TCS_PERF_SEL_CLIENT29_REQ = 0x5d, + TCS_PERF_SEL_CLIENT30_REQ = 0x5e, + TCS_PERF_SEL_CLIENT31_REQ = 0x5f, + TCS_PERF_SEL_CLIENT32_REQ = 0x60, + TCS_PERF_SEL_CLIENT33_REQ = 0x61, + TCS_PERF_SEL_CLIENT34_REQ = 0x62, + TCS_PERF_SEL_CLIENT35_REQ = 0x63, + TCS_PERF_SEL_CLIENT36_REQ = 0x64, + TCS_PERF_SEL_CLIENT37_REQ = 0x65, + TCS_PERF_SEL_CLIENT38_REQ = 0x66, + TCS_PERF_SEL_CLIENT39_REQ = 0x67, + TCS_PERF_SEL_CLIENT40_REQ = 0x68, + TCS_PERF_SEL_CLIENT41_REQ = 0x69, + TCS_PERF_SEL_CLIENT42_REQ = 0x6a, + TCS_PERF_SEL_CLIENT43_REQ = 0x6b, + TCS_PERF_SEL_CLIENT44_REQ = 0x6c, + TCS_PERF_SEL_CLIENT45_REQ = 0x6d, + TCS_PERF_SEL_CLIENT46_REQ = 0x6e, + TCS_PERF_SEL_CLIENT47_REQ = 0x6f, + TCS_PERF_SEL_CLIENT48_REQ = 0x70, + TCS_PERF_SEL_CLIENT49_REQ = 0x71, + TCS_PERF_SEL_CLIENT50_REQ = 0x72, + TCS_PERF_SEL_CLIENT51_REQ = 0x73, + TCS_PERF_SEL_CLIENT52_REQ = 0x74, + TCS_PERF_SEL_CLIENT53_REQ = 0x75, + TCS_PERF_SEL_CLIENT54_REQ = 0x76, + TCS_PERF_SEL_CLIENT55_REQ = 0x77, + TCS_PERF_SEL_CLIENT56_REQ = 0x78, + TCS_PERF_SEL_CLIENT57_REQ = 0x79, + TCS_PERF_SEL_CLIENT58_REQ = 0x7a, + TCS_PERF_SEL_CLIENT59_REQ = 0x7b, + TCS_PERF_SEL_CLIENT60_REQ = 0x7c, + TCS_PERF_SEL_CLIENT61_REQ = 0x7d, + TCS_PERF_SEL_CLIENT62_REQ = 0x7e, + TCS_PERF_SEL_CLIENT63_REQ = 0x7f, +} TCS_PERF_SEL; +typedef enum TA_TC_ADDR_MODES { + TA_TC_ADDR_MODE_DEFAULT = 0x0, + TA_TC_ADDR_MODE_COMP0 = 0x1, + TA_TC_ADDR_MODE_COMP1 = 0x2, + TA_TC_ADDR_MODE_COMP2 = 0x3, + TA_TC_ADDR_MODE_COMP3 = 0x4, + TA_TC_ADDR_MODE_UNALIGNED = 0x5, + TA_TC_ADDR_MODE_BORDER_COLOR = 0x6, +} TA_TC_ADDR_MODES; +typedef enum TA_PERFCOUNT_SEL { + TA_PERF_SEL_ta_busy = 0x0, + TA_PERF_SEL_sh_fifo_busy = 0x1, + TA_PERF_SEL_sh_fifo_cmd_busy = 0x2, + TA_PERF_SEL_sh_fifo_addr_busy = 0x3, + TA_PERF_SEL_sh_fifo_data_busy = 0x4, + TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x5, + TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x6, + TA_PERF_SEL_gradient_busy = 0x7, + TA_PERF_SEL_gradient_fifo_busy = 0x8, + TA_PERF_SEL_lod_busy = 0x9, + TA_PERF_SEL_lod_fifo_busy = 0xa, + TA_PERF_SEL_addresser_busy = 0xb, + TA_PERF_SEL_addresser_fifo_busy = 0xc, + TA_PERF_SEL_aligner_busy = 0xd, + TA_PERF_SEL_write_path_busy = 0xe, + TA_PERF_SEL_RESERVED_15 = 0xf, + TA_PERF_SEL_sq_ta_cmd_cycles = 0x10, + TA_PERF_SEL_sp_ta_addr_cycles = 0x11, + TA_PERF_SEL_sp_ta_data_cycles = 0x12, + TA_PERF_SEL_ta_fa_data_state_cycles = 0x13, + TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x14, + TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x15, + TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16, + TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17, + TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18, + TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19, + TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a, + TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b, + TA_PERF_SEL_RESERVED_28 = 0x1c, + TA_PERF_SEL_RESERVED_29 = 0x1d, + TA_PERF_SEL_sh_fifo_addr_cycles = 0x1e, + TA_PERF_SEL_sh_fifo_data_cycles = 0x1f, + TA_PERF_SEL_total_wavefronts = 0x20, + TA_PERF_SEL_gradient_cycles = 0x21, + TA_PERF_SEL_walker_cycles = 0x22, + TA_PERF_SEL_aligner_cycles = 0x23, + TA_PERF_SEL_image_wavefronts = 0x24, + TA_PERF_SEL_image_read_wavefronts = 0x25, + TA_PERF_SEL_image_write_wavefronts = 0x26, + TA_PERF_SEL_image_atomic_wavefronts = 0x27, + TA_PERF_SEL_image_total_cycles = 0x28, + TA_PERF_SEL_RESERVED_41 = 0x29, + TA_PERF_SEL_RESERVED_42 = 0x2a, + TA_PERF_SEL_RESERVED_43 = 0x2b, + TA_PERF_SEL_buffer_wavefronts = 0x2c, + TA_PERF_SEL_buffer_read_wavefronts = 0x2d, + TA_PERF_SEL_buffer_write_wavefronts = 0x2e, + TA_PERF_SEL_buffer_atomic_wavefronts = 0x2f, + TA_PERF_SEL_buffer_coalescable_wavefronts = 0x30, + TA_PERF_SEL_buffer_total_cycles = 0x31, + TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32, + TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33, + TA_PERF_SEL_buffer_coalesced_read_cycles = 0x34, + TA_PERF_SEL_buffer_coalesced_write_cycles = 0x35, + TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x36, + TA_PERF_SEL_addr_stalled_by_td_cycles = 0x37, + TA_PERF_SEL_data_stalled_by_tc_cycles = 0x38, + TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39, + TA_PERF_SEL_addresser_stalled_cycles = 0x3a, + TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b, + TA_PERF_SEL_aniso_stalled_cycles = 0x3c, + TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x3d, + TA_PERF_SEL_deriv_stalled_cycles = 0x3e, + TA_PERF_SEL_aniso_gt1_cycle_quads = 0x3f, + TA_PERF_SEL_color_1_cycle_pixels = 0x40, + TA_PERF_SEL_color_2_cycle_pixels = 0x41, + TA_PERF_SEL_color_3_cycle_pixels = 0x42, + TA_PERF_SEL_color_4_cycle_pixels = 0x43, + TA_PERF_SEL_mip_1_cycle_pixels = 0x44, + TA_PERF_SEL_mip_2_cycle_pixels = 0x45, + TA_PERF_SEL_vol_1_cycle_pixels = 0x46, + TA_PERF_SEL_vol_2_cycle_pixels = 0x47, + TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x48, + TA_PERF_SEL_mipmap_lod_0_samples = 0x49, + TA_PERF_SEL_mipmap_lod_1_samples = 0x4a, + TA_PERF_SEL_mipmap_lod_2_samples = 0x4b, + TA_PERF_SEL_mipmap_lod_3_samples = 0x4c, + TA_PERF_SEL_mipmap_lod_4_samples = 0x4d, + TA_PERF_SEL_mipmap_lod_5_samples = 0x4e, + TA_PERF_SEL_mipmap_lod_6_samples = 0x4f, + TA_PERF_SEL_mipmap_lod_7_samples = 0x50, + TA_PERF_SEL_mipmap_lod_8_samples = 0x51, + TA_PERF_SEL_mipmap_lod_9_samples = 0x52, + TA_PERF_SEL_mipmap_lod_10_samples = 0x53, + TA_PERF_SEL_mipmap_lod_11_samples = 0x54, + TA_PERF_SEL_mipmap_lod_12_samples = 0x55, + TA_PERF_SEL_mipmap_lod_13_samples = 0x56, + TA_PERF_SEL_mipmap_lod_14_samples = 0x57, + TA_PERF_SEL_mipmap_invalid_samples = 0x58, + TA_PERF_SEL_aniso_1_cycle_quads = 0x59, + TA_PERF_SEL_aniso_2_cycle_quads = 0x5a, + TA_PERF_SEL_aniso_4_cycle_quads = 0x5b, + TA_PERF_SEL_aniso_6_cycle_quads = 0x5c, + TA_PERF_SEL_aniso_8_cycle_quads = 0x5d, + TA_PERF_SEL_aniso_10_cycle_quads = 0x5e, + TA_PERF_SEL_aniso_12_cycle_quads = 0x5f, + TA_PERF_SEL_aniso_14_cycle_quads = 0x60, + TA_PERF_SEL_aniso_16_cycle_quads = 0x61, + TA_PERF_SEL_write_path_input_cycles = 0x62, + TA_PERF_SEL_write_path_output_cycles = 0x63, + TA_PERF_SEL_flat_wavefronts = 0x64, + TA_PERF_SEL_flat_read_wavefronts = 0x65, + TA_PERF_SEL_flat_write_wavefronts = 0x66, + TA_PERF_SEL_flat_atomic_wavefronts = 0x67, + TA_PERF_SEL_flat_coalesceable_wavefronts = 0x68, + TA_PERF_SEL_reg_sclk_vld = 0x69, + TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6a, + TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x6b, + TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x6c, + TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x6d, + TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x6e, +} TA_PERFCOUNT_SEL; +typedef enum TD_PERFCOUNT_SEL { + TD_PERF_SEL_td_busy = 0x0, + TD_PERF_SEL_input_busy = 0x1, + TD_PERF_SEL_output_busy = 0x2, + TD_PERF_SEL_lerp_busy = 0x3, + TD_PERF_SEL_RESERVED_4 = 0x4, + TD_PERF_SEL_reg_sclk_vld = 0x5, + TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6, + TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x7, + TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x8, + TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x9, + TD_PERF_SEL_tc_td_fifo_full = 0xa, + TD_PERF_SEL_constant_state_full = 0xb, + TD_PERF_SEL_sample_state_full = 0xc, + TD_PERF_SEL_output_fifo_full = 0xd, + TD_PERF_SEL_RESERVED_14 = 0xe, + TD_PERF_SEL_tc_stall = 0xf, + TD_PERF_SEL_pc_stall = 0x10, + TD_PERF_SEL_gds_stall = 0x11, + TD_PERF_SEL_RESERVED_18 = 0x12, + TD_PERF_SEL_RESERVED_19 = 0x13, + TD_PERF_SEL_gather4_wavefront = 0x14, + TD_PERF_SEL_sample_c_wavefront = 0x15, + TD_PERF_SEL_load_wavefront = 0x16, + TD_PERF_SEL_atomic_wavefront = 0x17, + TD_PERF_SEL_store_wavefront = 0x18, + TD_PERF_SEL_ldfptr_wavefront = 0x19, + TD_PERF_SEL_RESERVED_26 = 0x1a, + TD_PERF_SEL_RESERVED_27 = 0x1b, + TD_PERF_SEL_RESERVED_28 = 0x1c, + TD_PERF_SEL_RESERVED_29 = 0x1d, + TD_PERF_SEL_bypass_filter_wavefront = 0x1e, + TD_PERF_SEL_min_max_filter_wavefront = 0x1f, + TD_PERF_SEL_coalescable_wavefront = 0x20, + TD_PERF_SEL_coalesced_phase = 0x21, + TD_PERF_SEL_four_phase_wavefront = 0x22, + TD_PERF_SEL_eight_phase_wavefront = 0x23, + TD_PERF_SEL_sixteen_phase_wavefront = 0x24, + TD_PERF_SEL_four_phase_forward_wavefront = 0x25, + TD_PERF_SEL_write_ack_wavefront = 0x26, + TD_PERF_SEL_RESERVED_39 = 0x27, + TD_PERF_SEL_user_defined_border = 0x28, + TD_PERF_SEL_white_border = 0x29, + TD_PERF_SEL_opaque_black_border = 0x2a, + TD_PERF_SEL_RESERVED_43 = 0x2b, + TD_PERF_SEL_RESERVED_44 = 0x2c, + TD_PERF_SEL_nack = 0x2d, + TD_PERF_SEL_td_sp_traffic = 0x2e, + TD_PERF_SEL_consume_gds_traffic = 0x2f, + TD_PERF_SEL_addresscmd_poison = 0x30, + TD_PERF_SEL_data_poison = 0x31, + TD_PERF_SEL_start_cycle_0 = 0x32, + TD_PERF_SEL_start_cycle_1 = 0x33, + TD_PERF_SEL_start_cycle_2 = 0x34, + TD_PERF_SEL_start_cycle_3 = 0x35, + TD_PERF_SEL_null_cycle_output = 0x36, +} TD_PERFCOUNT_SEL; +typedef enum TCP_PERFCOUNT_SELECT { + TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x0, + TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x1, + TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2, + TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x3, + TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x4, + TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x5, + TCP_PERF_SEL_LOD_STALL_CYCLES = 0x6, + TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x7, + TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x8, + TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x9, + TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0xa, + TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0xb, + TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0xc, + TCP_PERF_SEL_TCR_RDRET_STALL = 0xd, + TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0xe, + TCP_PERF_SEL_HOLE_READ_STALL = 0xf, + TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x10, + TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x11, + TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x12, + TCP_PERF_SEL_TCP_LATENCY = 0x13, + TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x14, + TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x15, + TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x16, + TCP_PERF_SEL_TCC_READ_REQ = 0x17, + TCP_PERF_SEL_TCC_WRITE_REQ = 0x18, + TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x19, + TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x1a, + TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x1b, + TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x1c, + TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d, + TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x1e, + TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x1f, + TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x20, + TCP_PERF_SEL_TOTAL_WBINVL1 = 0x21, + TCP_PERF_SEL_IMG_READ_FMT_1 = 0x22, + TCP_PERF_SEL_IMG_READ_FMT_8 = 0x23, + TCP_PERF_SEL_IMG_READ_FMT_16 = 0x24, + TCP_PERF_SEL_IMG_READ_FMT_32 = 0x25, + TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x26, + TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x27, + TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x28, + TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x29, + TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x2a, + TCP_PERF_SEL_IMG_READ_FMT_96 = 0x2b, + TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x2c, + TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x2d, + TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x2e, + TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x2f, + TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x30, + TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x31, + TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x32, + TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x33, + TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x34, + TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x35, + TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x36, + TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x37, + TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x38, + TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x39, + TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x3a, + TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x3b, + TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x3c, + TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x3d, + TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x3e, + TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x3f, + TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x40, + TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x41, + TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x42, + TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x43, + TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x44, + TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x45, + TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x46, + TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x47, + TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x48, + TCP_PERF_SEL_BUF_READ_FMT_8 = 0x49, + TCP_PERF_SEL_BUF_READ_FMT_16 = 0x4a, + TCP_PERF_SEL_BUF_READ_FMT_32 = 0x4b, + TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x4c, + TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x4d, + TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x4e, + TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x4f, + TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x50, + TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x51, + TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x52, + TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x53, + TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x54, + TCP_PERF_SEL_ARR_1D_THIN1 = 0x55, + TCP_PERF_SEL_ARR_1D_THICK = 0x56, + TCP_PERF_SEL_ARR_2D_THIN1 = 0x57, + TCP_PERF_SEL_ARR_2D_THICK = 0x58, + TCP_PERF_SEL_ARR_2D_XTHICK = 0x59, + TCP_PERF_SEL_ARR_3D_THIN1 = 0x5a, + TCP_PERF_SEL_ARR_3D_THICK = 0x5b, + TCP_PERF_SEL_ARR_3D_XTHICK = 0x5c, + TCP_PERF_SEL_DIM_1D = 0x5d, + TCP_PERF_SEL_DIM_2D = 0x5e, + TCP_PERF_SEL_DIM_3D = 0x5f, + TCP_PERF_SEL_DIM_1D_ARRAY = 0x60, + TCP_PERF_SEL_DIM_2D_ARRAY = 0x61, + TCP_PERF_SEL_DIM_2D_MSAA = 0x62, + TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x63, + TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x64, + TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x65, + TCP_PERF_SEL_TA_TCP_STATE_READ = 0x66, + TCP_PERF_SEL_TAGRAM0_REQ = 0x67, + TCP_PERF_SEL_TAGRAM1_REQ = 0x68, + TCP_PERF_SEL_TAGRAM2_REQ = 0x69, + TCP_PERF_SEL_TAGRAM3_REQ = 0x6a, + TCP_PERF_SEL_GATE_EN1 = 0x6b, + TCP_PERF_SEL_GATE_EN2 = 0x6c, + TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x6d, + TCP_PERF_SEL_TCC_REQ = 0x6e, + TCP_PERF_SEL_TCC_NON_READ_REQ = 0x6f, + TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x70, + TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x71, + TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x72, + TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x73, + TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x74, + TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x75, + TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x76, + TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x77, + TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x78, + TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x79, + TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x7a, + TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x7b, + TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x7c, + TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x7d, + TCP_PERF_SEL_TOTAL_ACCESSES = 0x7e, + TCP_PERF_SEL_TOTAL_READ = 0x7f, + TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x80, + TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x81, + TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x82, + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x83, + TCP_PERF_SEL_TOTAL_NON_READ = 0x84, + TCP_PERF_SEL_TOTAL_WRITE = 0x85, + TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x86, + TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x87, + TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x88, + TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x89, + TCP_PERF_SEL_DISPLAY_MICROTILING = 0x8a, + TCP_PERF_SEL_THIN_MICROTILING = 0x8b, + TCP_PERF_SEL_DEPTH_MICROTILING = 0x8c, + TCP_PERF_SEL_ARR_PRT_THIN1 = 0x8d, + TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x8e, + TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x8f, + TCP_PERF_SEL_ARR_PRT_THICK = 0x90, + TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x91, + TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x92, + TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x93, + TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x94, + TCP_PERF_SEL_UNALIGNED = 0x95, + TCP_PERF_SEL_ROTATED_MICROTILING = 0x96, + TCP_PERF_SEL_THICK_MICROTILING = 0x97, + TCP_PERF_SEL_ATC = 0x98, + TCP_PERF_SEL_POWER_STALL = 0x99, +} TCP_PERFCOUNT_SELECT; +typedef enum TCP_CACHE_POLICIES { + TCP_CACHE_POLICY_MISS_LRU = 0x0, + TCP_CACHE_POLICY_MISS_EVICT = 0x1, + TCP_CACHE_POLICY_HIT_LRU = 0x2, + TCP_CACHE_POLICY_HIT_EVICT = 0x3, +} TCP_CACHE_POLICIES; +typedef enum TCP_CACHE_STORE_POLICIES { + TCP_CACHE_STORE_POLICY_MISS_LRU = 0x0, + TCP_CACHE_STORE_POLICY_MISS_EVICT = 0x1, +} TCP_CACHE_STORE_POLICIES; +typedef enum TCP_WATCH_MODES { + TCP_WATCH_MODE_READ = 0x0, + TCP_WATCH_MODE_NONREAD = 0x1, + TCP_WATCH_MODE_ATOMIC = 0x2, + TCP_WATCH_MODE_ALL = 0x3, +} TCP_WATCH_MODES; +typedef enum VGT_OUT_PRIM_TYPE { + VGT_OUT_POINT = 0x0, + VGT_OUT_LINE = 0x1, + VGT_OUT_TRI = 0x2, + VGT_OUT_RECT_V0 = 0x3, + VGT_OUT_RECT_V1 = 0x4, + VGT_OUT_RECT_V2 = 0x5, + VGT_OUT_RECT_V3 = 0x6, + VGT_OUT_RESERVED = 0x7, + VGT_TE_QUAD = 0x8, + VGT_TE_PRIM_INDEX_LINE = 0x9, + VGT_TE_PRIM_INDEX_TRI = 0xa, + VGT_TE_PRIM_INDEX_QUAD = 0xb, + VGT_OUT_LINE_ADJ = 0xc, + VGT_OUT_TRI_ADJ = 0xd, + VGT_OUT_PATCH = 0xe, +} VGT_OUT_PRIM_TYPE; +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0x0, + DI_PT_POINTLIST = 0x1, + DI_PT_LINELIST = 0x2, + DI_PT_LINESTRIP = 0x3, + DI_PT_TRILIST = 0x4, + DI_PT_TRIFAN = 0x5, + DI_PT_TRISTRIP = 0x6, + DI_PT_UNUSED_0 = 0x7, + DI_PT_UNUSED_1 = 0x8, + DI_PT_PATCH = 0x9, + DI_PT_LINELIST_ADJ = 0xa, + DI_PT_LINESTRIP_ADJ = 0xb, + DI_PT_TRILIST_ADJ = 0xc, + DI_PT_TRISTRIP_ADJ = 0xd, + DI_PT_UNUSED_3 = 0xe, + DI_PT_UNUSED_4 = 0xf, + DI_PT_TRI_WITH_WFLAGS = 0x10, + DI_PT_RECTLIST = 0x11, + DI_PT_LINELOOP = 0x12, + DI_PT_QUADLIST = 0x13, + DI_PT_QUADSTRIP = 0x14, + DI_PT_POLYGON = 0x15, + DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, + DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, + DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, + DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, + DI_PT_2D_FILL_RECT_LIST = 0x1a, + DI_PT_2D_LINE_STRIP = 0x1b, + DI_PT_2D_TRI_STRIP = 0x1c, +} VGT_DI_PRIM_TYPE; +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0x0, + DI_SRC_SEL_IMMEDIATE = 0x1, + DI_SRC_SEL_AUTO_INDEX = 0x2, + DI_SRC_SEL_RESERVED = 0x3, +} VGT_DI_SOURCE_SELECT; +typedef enum VGT_DI_MAJOR_MODE_SELECT { + DI_MAJOR_MODE_0 = 0x0, + DI_MAJOR_MODE_1 = 0x1, +} VGT_DI_MAJOR_MODE_SELECT; +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0x0, + DI_INDEX_SIZE_32_BIT = 0x1, +} VGT_DI_INDEX_SIZE; +typedef enum VGT_EVENT_TYPE { + Reserved_0x00 = 0x0, + SAMPLE_STREAMOUTSTATS1 = 0x1, + SAMPLE_STREAMOUTSTATS2 = 0x2, + SAMPLE_STREAMOUTSTATS3 = 0x3, + CACHE_FLUSH_TS = 0x4, + CONTEXT_DONE = 0x5, + CACHE_FLUSH = 0x6, + CS_PARTIAL_FLUSH = 0x7, + VGT_STREAMOUT_SYNC = 0x8, + Reserved_0x09 = 0x9, + VGT_STREAMOUT_RESET = 0xa, + END_OF_PIPE_INCR_DE = 0xb, + END_OF_PIPE_IB_END = 0xc, + RST_PIX_CNT = 0xd, + Reserved_0x0E = 0xe, + VS_PARTIAL_FLUSH = 0xf, + PS_PARTIAL_FLUSH = 0x10, + FLUSH_HS_OUTPUT = 0x11, + FLUSH_LS_OUTPUT = 0x12, + Reserved_0x13 = 0x13, + CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, + ZPASS_DONE = 0x15, + CACHE_FLUSH_AND_INV_EVENT = 0x16, + PERFCOUNTER_START = 0x17, + PERFCOUNTER_STOP = 0x18, + PIPELINESTAT_START = 0x19, + PIPELINESTAT_STOP = 0x1a, + PERFCOUNTER_SAMPLE = 0x1b, + FLUSH_ES_OUTPUT = 0x1c, + FLUSH_GS_OUTPUT = 0x1d, + SAMPLE_PIPELINESTAT = 0x1e, + SO_VGTSTREAMOUT_FLUSH = 0x1f, + SAMPLE_STREAMOUTSTATS = 0x20, + RESET_VTX_CNT = 0x21, + BLOCK_CONTEXT_DONE = 0x22, + CS_CONTEXT_DONE = 0x23, + VGT_FLUSH = 0x24, + Reserved_0x25 = 0x25, + SQ_NON_EVENT = 0x26, + SC_SEND_DB_VPZ = 0x27, + BOTTOM_OF_PIPE_TS = 0x28, + FLUSH_SX_TS = 0x29, + DB_CACHE_FLUSH_AND_INV = 0x2a, + FLUSH_AND_INV_DB_DATA_TS = 0x2b, + FLUSH_AND_INV_DB_META = 0x2c, + FLUSH_AND_INV_CB_DATA_TS = 0x2d, + FLUSH_AND_INV_CB_META = 0x2e, + CS_DONE = 0x2f, + PS_DONE = 0x30, + FLUSH_AND_INV_CB_PIXEL_DATA = 0x31, + SX_CB_RAT_ACK_REQUEST = 0x32, + THREAD_TRACE_START = 0x33, + THREAD_TRACE_STOP = 0x34, + THREAD_TRACE_MARKER = 0x35, + THREAD_TRACE_FLUSH = 0x36, + THREAD_TRACE_FINISH = 0x37, + PIXEL_PIPE_STAT_CONTROL = 0x38, + PIXEL_PIPE_STAT_DUMP = 0x39, + PIXEL_PIPE_STAT_RESET = 0x3a, + CONTEXT_SUSPEND = 0x3b, +} VGT_EVENT_TYPE; +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0x0, + VGT_DMA_SWAP_16_BIT = 0x1, + VGT_DMA_SWAP_32_BIT = 0x2, + VGT_DMA_SWAP_WORD = 0x3, +} VGT_DMA_SWAP_MODE; +typedef enum VGT_INDEX_TYPE_MODE { + VGT_INDEX_16 = 0x0, + VGT_INDEX_32 = 0x1, +} VGT_INDEX_TYPE_MODE; +typedef enum VGT_DMA_BUF_TYPE { + VGT_DMA_BUF_MEM = 0x0, + VGT_DMA_BUF_RING = 0x1, + VGT_DMA_BUF_SETUP = 0x2, +} VGT_DMA_BUF_TYPE; +typedef enum VGT_OUTPATH_SELECT { + VGT_OUTPATH_VTX_REUSE = 0x0, + VGT_OUTPATH_TESS_EN = 0x1, + VGT_OUTPATH_PASSTHRU = 0x2, + VGT_OUTPATH_GS_BLOCK = 0x3, + VGT_OUTPATH_HS_BLOCK = 0x4, +} VGT_OUTPATH_SELECT; +typedef enum VGT_GRP_PRIM_TYPE { + VGT_GRP_3D_POINT = 0x0, + VGT_GRP_3D_LINE = 0x1, + VGT_GRP_3D_TRI = 0x2, + VGT_GRP_3D_RECT = 0x3, + VGT_GRP_3D_QUAD = 0x4, + VGT_GRP_2D_COPY_RECT_V0 = 0x5, + VGT_GRP_2D_COPY_RECT_V1 = 0x6, + VGT_GRP_2D_COPY_RECT_V2 = 0x7, + VGT_GRP_2D_COPY_RECT_V3 = 0x8, + VGT_GRP_2D_FILL_RECT = 0x9, + VGT_GRP_2D_LINE = 0xa, + VGT_GRP_2D_TRI = 0xb, + VGT_GRP_PRIM_INDEX_LINE = 0xc, + VGT_GRP_PRIM_INDEX_TRI = 0xd, + VGT_GRP_PRIM_INDEX_QUAD = 0xe, + VGT_GRP_3D_LINE_ADJ = 0xf, + VGT_GRP_3D_TRI_ADJ = 0x10, + VGT_GRP_3D_PATCH = 0x11, +} VGT_GRP_PRIM_TYPE; +typedef enum VGT_GRP_PRIM_ORDER { + VGT_GRP_LIST = 0x0, + VGT_GRP_STRIP = 0x1, + VGT_GRP_FAN = 0x2, + VGT_GRP_LOOP = 0x3, + VGT_GRP_POLYGON = 0x4, +} VGT_GRP_PRIM_ORDER; +typedef enum VGT_GROUP_CONV_SEL { + VGT_GRP_INDEX_16 = 0x0, + VGT_GRP_INDEX_32 = 0x1, + VGT_GRP_UINT_16 = 0x2, + VGT_GRP_UINT_32 = 0x3, + VGT_GRP_SINT_16 = 0x4, + VGT_GRP_SINT_32 = 0x5, + VGT_GRP_FLOAT_32 = 0x6, + VGT_GRP_AUTO_PRIM = 0x7, + VGT_GRP_FIX_1_23_TO_FLOAT = 0x8, +} VGT_GROUP_CONV_SEL; +typedef enum VGT_GS_MODE_TYPE { + GS_OFF = 0x0, + GS_SCENARIO_A = 0x1, + GS_SCENARIO_B = 0x2, + GS_SCENARIO_G = 0x3, + GS_SCENARIO_C = 0x4, + SPRITE_EN = 0x5, +} VGT_GS_MODE_TYPE; +typedef enum VGT_GS_CUT_MODE { + GS_CUT_1024 = 0x0, + GS_CUT_512 = 0x1, + GS_CUT_256 = 0x2, + GS_CUT_128 = 0x3, +} VGT_GS_CUT_MODE; +typedef enum VGT_GS_OUTPRIM_TYPE { + POINTLIST = 0x0, + LINESTRIP = 0x1, + TRISTRIP = 0x2, +} VGT_GS_OUTPRIM_TYPE; +typedef enum VGT_CACHE_INVALID_MODE { + VC_ONLY = 0x0, + TC_ONLY = 0x1, + VC_AND_TC = 0x2, +} VGT_CACHE_INVALID_MODE; +typedef enum VGT_TESS_TYPE { + TESS_ISOLINE = 0x0, + TESS_TRIANGLE = 0x1, + TESS_QUAD = 0x2, +} VGT_TESS_TYPE; +typedef enum VGT_TESS_PARTITION { + PART_INTEGER = 0x0, + PART_POW2 = 0x1, + PART_FRAC_ODD = 0x2, + PART_FRAC_EVEN = 0x3, +} VGT_TESS_PARTITION; +typedef enum VGT_TESS_TOPOLOGY { + OUTPUT_POINT = 0x0, + OUTPUT_LINE = 0x1, + OUTPUT_TRIANGLE_CW = 0x2, + OUTPUT_TRIANGLE_CCW = 0x3, +} VGT_TESS_TOPOLOGY; +typedef enum VGT_RDREQ_POLICY { + VGT_POLICY_LRU = 0x0, + VGT_POLICY_STREAM = 0x1, + VGT_POLICY_BYPASS = 0x2, + VGT_POLICY_RESERVED = 0x3, +} VGT_RDREQ_POLICY; +typedef enum VGT_STAGES_LS_EN { + LS_STAGE_OFF = 0x0, + LS_STAGE_ON = 0x1, + CS_STAGE_ON = 0x2, + RESERVED_LS = 0x3, +} VGT_STAGES_LS_EN; +typedef enum VGT_STAGES_HS_EN { + HS_STAGE_OFF = 0x0, + HS_STAGE_ON = 0x1, +} VGT_STAGES_HS_EN; +typedef enum VGT_STAGES_ES_EN { + ES_STAGE_OFF = 0x0, + ES_STAGE_DS = 0x1, + ES_STAGE_REAL = 0x2, + RESERVED_ES = 0x3, +} VGT_STAGES_ES_EN; +typedef enum VGT_STAGES_GS_EN { + GS_STAGE_OFF = 0x0, + GS_STAGE_ON = 0x1, +} VGT_STAGES_GS_EN; +typedef enum VGT_STAGES_VS_EN { + VS_STAGE_REAL = 0x0, + VS_STAGE_DS = 0x1, + VS_STAGE_COPY_SHADER = 0x2, + RESERVED_VS = 0x3, +} VGT_STAGES_VS_EN; +typedef enum VGT_PERFCOUNT_SELECT { + vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x0, + vgt_perf_VGT_SPI_ESVERT_VALID = 0x1, + vgt_perf_VGT_SPI_ESVERT_EOV = 0x2, + vgt_perf_VGT_SPI_ESVERT_STALLED = 0x3, + vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x4, + vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x5, + vgt_perf_VGT_SPI_ESVERT_STATIC = 0x6, + vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x7, + vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x8, + vgt_perf_VGT_SPI_GSPRIM_VALID = 0x9, + vgt_perf_VGT_SPI_GSPRIM_EOV = 0xa, + vgt_perf_VGT_SPI_GSPRIM_CONT = 0xb, + vgt_perf_VGT_SPI_GSPRIM_STALLED = 0xc, + vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0xd, + vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0xe, + vgt_perf_VGT_SPI_GSPRIM_STATIC = 0xf, + vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x10, + vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x11, + vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x12, + vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x13, + vgt_perf_VGT_SPI_VSVERT_SEND = 0x14, + vgt_perf_VGT_SPI_VSVERT_EOV = 0x15, + vgt_perf_VGT_SPI_VSVERT_STALLED = 0x16, + vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x17, + vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x18, + vgt_perf_VGT_SPI_VSVERT_STATIC = 0x19, + vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x1a, + vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x1b, + vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x1c, + vgt_perf_VGT_PA_CLIPV_SEND = 0x1d, + vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x1e, + vgt_perf_VGT_PA_CLIPV_STALLED = 0x1f, + vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x20, + vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x21, + vgt_perf_VGT_PA_CLIPV_STATIC = 0x22, + vgt_perf_VGT_PA_CLIPP_SEND = 0x23, + vgt_perf_VGT_PA_CLIPP_EOP = 0x24, + vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x25, + vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x26, + vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x27, + vgt_perf_VGT_PA_CLIPP_STALLED = 0x28, + vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x29, + vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x2a, + vgt_perf_VGT_PA_CLIPP_STATIC = 0x2b, + vgt_perf_VGT_PA_CLIPS_SEND = 0x2c, + vgt_perf_VGT_PA_CLIPS_STALLED = 0x2d, + vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x2e, + vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x2f, + vgt_perf_VGT_PA_CLIPS_STATIC = 0x30, + vgt_perf_vsvert_ds_send = 0x31, + vgt_perf_vsvert_api_send = 0x32, + vgt_perf_hs_tif_stall = 0x33, + vgt_perf_hs_input_stall = 0x34, + vgt_perf_hs_interface_stall = 0x35, + vgt_perf_hs_tfm_stall = 0x36, + vgt_perf_te11_starved = 0x37, + vgt_perf_gs_event_stall = 0x38, + vgt_perf_vgt_pa_clipp_send_not_event = 0x39, + vgt_perf_vgt_pa_clipp_valid_prim = 0x3a, + vgt_perf_reused_es_indices = 0x3b, + vgt_perf_vs_cache_hits = 0x3c, + vgt_perf_gs_cache_hits = 0x3d, + vgt_perf_ds_cache_hits = 0x3e, + vgt_perf_total_cache_hits = 0x3f, + vgt_perf_vgt_busy = 0x40, + vgt_perf_vgt_gs_busy = 0x41, + vgt_perf_esvert_stalled_es_tbl = 0x42, + vgt_perf_esvert_stalled_gs_tbl = 0x43, + vgt_perf_esvert_stalled_gs_event = 0x44, + vgt_perf_esvert_stalled_gsprim = 0x45, + vgt_perf_gsprim_stalled_es_tbl = 0x46, + vgt_perf_gsprim_stalled_gs_tbl = 0x47, + vgt_perf_gsprim_stalled_gs_event = 0x48, + vgt_perf_gsprim_stalled_esvert = 0x49, + vgt_perf_esthread_stalled_es_rb_full = 0x4a, + vgt_perf_esthread_stalled_spi_bp = 0x4b, + vgt_perf_counters_avail_stalled = 0x4c, + vgt_perf_gs_rb_space_avail_stalled = 0x4d, + vgt_perf_gs_issue_rtr_stalled = 0x4e, + vgt_perf_gsthread_stalled = 0x4f, + vgt_perf_strmout_stalled = 0x50, + vgt_perf_wait_for_es_done_stalled = 0x51, + vgt_perf_cm_stalled_by_gog = 0x52, + vgt_perf_cm_reading_stalled = 0x53, + vgt_perf_cm_stalled_by_gsfetch_done = 0x54, + vgt_perf_gog_vs_tbl_stalled = 0x55, + vgt_perf_gog_out_indx_stalled = 0x56, + vgt_perf_gog_out_prim_stalled = 0x57, + vgt_perf_waveid_stalled = 0x58, + vgt_perf_gog_busy = 0x59, + vgt_perf_reused_vs_indices = 0x5a, + vgt_perf_sclk_reg_vld_event = 0x5b, + vgt_perf_RESERVED0 = 0x5c, + vgt_perf_sclk_core_vld_event = 0x5d, + vgt_perf_RESERVED1 = 0x5e, + vgt_perf_sclk_gs_vld_event = 0x5f, + vgt_perf_VGT_SPI_LSVERT_VALID = 0x60, + vgt_perf_VGT_SPI_LSVERT_EOV = 0x61, + vgt_perf_VGT_SPI_LSVERT_STALLED = 0x62, + vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x63, + vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x64, + vgt_perf_VGT_SPI_LSVERT_STATIC = 0x65, + vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x66, + vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x67, + vgt_perf_VGT_SPI_LSWAVE_SEND = 0x68, + vgt_perf_VGT_SPI_HSVERT_VALID = 0x69, + vgt_perf_VGT_SPI_HSVERT_EOV = 0x6a, + vgt_perf_VGT_SPI_HSVERT_STALLED = 0x6b, + vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x6c, + vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x6d, + vgt_perf_VGT_SPI_HSVERT_STATIC = 0x6e, + vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x6f, + vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x70, + vgt_perf_VGT_SPI_HSWAVE_SEND = 0x71, + vgt_perf_ds_prims = 0x72, + vgt_perf_null_tess_patches = 0x73, + vgt_perf_ls_thread_groups = 0x74, + vgt_perf_hs_thread_groups = 0x75, + vgt_perf_es_thread_groups = 0x76, + vgt_perf_vs_thread_groups = 0x77, + vgt_perf_ls_done_latency = 0x78, + vgt_perf_hs_done_latency = 0x79, + vgt_perf_es_done_latency = 0x7a, + vgt_perf_gs_done_latency = 0x7b, + vgt_perf_vgt_hs_busy = 0x7c, + vgt_perf_vgt_te11_busy = 0x7d, + vgt_perf_ls_flush = 0x7e, + vgt_perf_hs_flush = 0x7f, + vgt_perf_es_flush = 0x80, + vgt_perf_gs_flush = 0x81, + vgt_perf_ls_done = 0x82, + vgt_perf_hs_done = 0x83, + vgt_perf_es_done = 0x84, + vgt_perf_gs_done = 0x85, + vgt_perf_vsfetch_done = 0x86, + vgt_perf_RESERVED2 = 0x87, + vgt_perf_es_ring_high_water_mark = 0x88, + vgt_perf_gs_ring_high_water_mark = 0x89, + vgt_perf_vs_table_high_water_mark = 0x8a, + vgt_perf_hs_tgs_active_high_water_mark = 0x8b, +} VGT_PERFCOUNT_SELECT; +typedef enum IA_PERFCOUNT_SELECT { + ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x0, + ia_perf_MC_LAT_BIN_0 = 0x1, + ia_perf_MC_LAT_BIN_1 = 0x2, + ia_perf_MC_LAT_BIN_2 = 0x3, + ia_perf_MC_LAT_BIN_3 = 0x4, + ia_perf_MC_LAT_BIN_4 = 0x5, + ia_perf_MC_LAT_BIN_5 = 0x6, + ia_perf_MC_LAT_BIN_6 = 0x7, + ia_perf_MC_LAT_BIN_7 = 0x8, + ia_perf_ia_busy = 0x9, + ia_perf_ia_sclk_reg_vld_event = 0xa, + ia_perf_RESERVED0 = 0xb, + ia_perf_ia_sclk_core_vld_event = 0xc, + ia_perf_RESERVED1 = 0xd, + ia_perf_ia_dma_return = 0xe, + ia_perf_shift_starved_pipe1_event = 0xf, + ia_perf_shift_starved_pipe0_event = 0x10, + ia_perf_ia_stalled = 0x11, +} IA_PERFCOUNT_SELECT; +typedef enum WD_PERFCOUNT_SELECT { + wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x0, + wd_perf_RBIU_DR_FIFO_STARVED = 0x1, + wd_perf_RBIU_DR_FIFO_STALLED = 0x2, + wd_perf_RBIU_DI_FIFO_STARVED = 0x3, + wd_perf_RBIU_DI_FIFO_STALLED = 0x4, + wd_perf_wd_busy = 0x5, + wd_perf_wd_sclk_reg_vld_event = 0x6, + wd_perf_wd_sclk_input_vld_event = 0x7, + wd_perf_wd_sclk_core_vld_event = 0x8, + wd_perf_wd_stalled = 0x9, +} WD_PERFCOUNT_SELECT; +typedef enum WD_IA_DRAW_TYPE { + WD_IA_DRAW_TYPE_DI_MM0 = 0x0, + WD_IA_DRAW_TYPE_DI_MM1 = 0x1, + WD_IA_DRAW_TYPE_EVENT_INIT = 0x2, + WD_IA_DRAW_TYPE_EVENT_ADDR = 0x3, + WD_IA_DRAW_TYPE_MIN_INDX = 0x4, + WD_IA_DRAW_TYPE_MAX_INDX = 0x5, + WD_IA_DRAW_TYPE_INDX_OFF = 0x6, + WD_IA_DRAW_TYPE_IMM_DATA = 0x7, +} WD_IA_DRAW_TYPE; +#define GSTHREADID_SIZE 0x2 +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, + ADDR_CONFIG_16_PIPE = 0x4, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_dco0 = 0x2, + DBG_CLIENT_BLKID_wd = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_scf2 = 0x5, + DBG_CLIENT_BLKID_spim3 = 0x6, + DBG_CLIENT_BLKID_cb3 = 0x7, + DBG_CLIENT_BLKID_sx0 = 0x8, + DBG_CLIENT_BLKID_cb2 = 0x9, + DBG_CLIENT_BLKID_bci1 = 0xa, + DBG_CLIENT_BLKID_xdma = 0xb, + DBG_CLIENT_BLKID_bci0 = 0xc, + DBG_CLIENT_BLKID_spim0 = 0xd, + DBG_CLIENT_BLKID_mcd0 = 0xe, + DBG_CLIENT_BLKID_mcc0 = 0xf, + DBG_CLIENT_BLKID_cb0 = 0x10, + DBG_CLIENT_BLKID_cb1 = 0x11, + DBG_CLIENT_BLKID_cpc_0 = 0x12, + DBG_CLIENT_BLKID_cpc_1 = 0x13, + DBG_CLIENT_BLKID_cpf = 0x14, + DBG_CLIENT_BLKID_rlc = 0x15, + DBG_CLIENT_BLKID_grbm = 0x16, + DBG_CLIENT_BLKID_bif = 0x17, + DBG_CLIENT_BLKID_scf1 = 0x18, + DBG_CLIENT_BLKID_sam = 0x19, + DBG_CLIENT_BLKID_mcd4 = 0x1a, + DBG_CLIENT_BLKID_mcc4 = 0x1b, + DBG_CLIENT_BLKID_gmcon = 0x1c, + DBG_CLIENT_BLKID_mcb = 0x1d, + DBG_CLIENT_BLKID_vgt0 = 0x1e, + DBG_CLIENT_BLKID_pc0 = 0x1f, + DBG_CLIENT_BLKID_spim1 = 0x20, + DBG_CLIENT_BLKID_bci2 = 0x21, + DBG_CLIENT_BLKID_mcd6 = 0x22, + DBG_CLIENT_BLKID_mcc6 = 0x23, + DBG_CLIENT_BLKID_mcd3 = 0x24, + DBG_CLIENT_BLKID_mcc3 = 0x25, + DBG_CLIENT_BLKID_uvdm_0 = 0x26, + DBG_CLIENT_BLKID_uvdm_1 = 0x27, + DBG_CLIENT_BLKID_uvdm_2 = 0x28, + DBG_CLIENT_BLKID_uvdm_3 = 0x29, + DBG_CLIENT_BLKID_spim2 = 0x2a, + DBG_CLIENT_BLKID_ds = 0x2b, + DBG_CLIENT_BLKID_srbm = 0x2c, + DBG_CLIENT_BLKID_ih = 0x2d, + DBG_CLIENT_BLKID_sem = 0x2e, + DBG_CLIENT_BLKID_sdma_0 = 0x2f, + DBG_CLIENT_BLKID_sdma_1 = 0x30, + DBG_CLIENT_BLKID_hdp = 0x31, + DBG_CLIENT_BLKID_acp_0 = 0x32, + DBG_CLIENT_BLKID_acp_1 = 0x33, + DBG_CLIENT_BLKID_vceb_0 = 0x34, + DBG_CLIENT_BLKID_vceb_1 = 0x35, + DBG_CLIENT_BLKID_vceb_2 = 0x36, + DBG_CLIENT_BLKID_mcd2 = 0x37, + DBG_CLIENT_BLKID_mcc2 = 0x38, + DBG_CLIENT_BLKID_scf3 = 0x39, + DBG_CLIENT_BLKID_bci3 = 0x3a, + DBG_CLIENT_BLKID_mcd5 = 0x3b, + DBG_CLIENT_BLKID_mcc5 = 0x3c, + DBG_CLIENT_BLKID_vgt2 = 0x3d, + DBG_CLIENT_BLKID_pc2 = 0x3e, + DBG_CLIENT_BLKID_smu_0 = 0x3f, + DBG_CLIENT_BLKID_smu_1 = 0x40, + DBG_CLIENT_BLKID_smu_2 = 0x41, + DBG_CLIENT_BLKID_vcea_0 = 0x42, + DBG_CLIENT_BLKID_vcea_1 = 0x43, + DBG_CLIENT_BLKID_vcea_2 = 0x44, + DBG_CLIENT_BLKID_vcea_3 = 0x45, + DBG_CLIENT_BLKID_vcea_4 = 0x46, + DBG_CLIENT_BLKID_vcea_5 = 0x47, + DBG_CLIENT_BLKID_vcea_6 = 0x48, + DBG_CLIENT_BLKID_scf0 = 0x49, + DBG_CLIENT_BLKID_vgt1 = 0x4a, + DBG_CLIENT_BLKID_pc1 = 0x4b, + DBG_CLIENT_BLKID_gdc_0 = 0x4c, + DBG_CLIENT_BLKID_gdc_1 = 0x4d, + DBG_CLIENT_BLKID_gdc_2 = 0x4e, + DBG_CLIENT_BLKID_gdc_3 = 0x4f, + DBG_CLIENT_BLKID_gdc_4 = 0x50, + DBG_CLIENT_BLKID_gdc_5 = 0x51, + DBG_CLIENT_BLKID_gdc_6 = 0x52, + DBG_CLIENT_BLKID_gdc_7 = 0x53, + DBG_CLIENT_BLKID_gdc_8 = 0x54, + DBG_CLIENT_BLKID_gdc_9 = 0x55, + DBG_CLIENT_BLKID_gdc_10 = 0x56, + DBG_CLIENT_BLKID_gdc_11 = 0x57, + DBG_CLIENT_BLKID_gdc_12 = 0x58, + DBG_CLIENT_BLKID_gdc_13 = 0x59, + DBG_CLIENT_BLKID_gdc_14 = 0x5a, + DBG_CLIENT_BLKID_gdc_15 = 0x5b, + DBG_CLIENT_BLKID_gdc_16 = 0x5c, + DBG_CLIENT_BLKID_gdc_17 = 0x5d, + DBG_CLIENT_BLKID_gdc_18 = 0x5e, + DBG_CLIENT_BLKID_gdc_19 = 0x5f, + DBG_CLIENT_BLKID_gdc_20 = 0x60, + DBG_CLIENT_BLKID_gdc_21 = 0x61, + DBG_CLIENT_BLKID_gdc_22 = 0x62, + DBG_CLIENT_BLKID_vgt3 = 0x63, + DBG_CLIENT_BLKID_pc3 = 0x64, + DBG_CLIENT_BLKID_uvdu_0 = 0x65, + DBG_CLIENT_BLKID_uvdu_1 = 0x66, + DBG_CLIENT_BLKID_uvdu_2 = 0x67, + DBG_CLIENT_BLKID_uvdu_3 = 0x68, + DBG_CLIENT_BLKID_uvdu_4 = 0x69, + DBG_CLIENT_BLKID_uvdu_5 = 0x6a, + DBG_CLIENT_BLKID_uvdu_6 = 0x6b, + DBG_CLIENT_BLKID_mcd7 = 0x6c, + DBG_CLIENT_BLKID_mcc7 = 0x6d, + DBG_CLIENT_BLKID_cpg_0 = 0x6e, + DBG_CLIENT_BLKID_cpg_1 = 0x6f, + DBG_CLIENT_BLKID_gck = 0x70, + DBG_CLIENT_BLKID_mcd1 = 0x71, + DBG_CLIENT_BLKID_mcc1 = 0x72, + DBG_CLIENT_BLKID_cb101 = 0x73, + DBG_CLIENT_BLKID_cb103 = 0x74, + DBG_CLIENT_BLKID_sx10 = 0x75, + DBG_CLIENT_BLKID_cb102 = 0x76, + DBG_CLIENT_BLKID_cb002 = 0x77, + DBG_CLIENT_BLKID_cb100 = 0x78, + DBG_CLIENT_BLKID_cb000 = 0x79, + DBG_CLIENT_BLKID_pa00 = 0x7a, + DBG_CLIENT_BLKID_pa10 = 0x7b, + DBG_CLIENT_BLKID_ia0 = 0x7c, + DBG_CLIENT_BLKID_ia1 = 0x7d, + DBG_CLIENT_BLKID_tmonw00 = 0x7e, + DBG_CLIENT_BLKID_cb001 = 0x7f, + DBG_CLIENT_BLKID_cb003 = 0x80, + DBG_CLIENT_BLKID_sx00 = 0x81, + DBG_CLIENT_BLKID_sx20 = 0x82, + DBG_CLIENT_BLKID_cb203 = 0x83, + DBG_CLIENT_BLKID_cb201 = 0x84, + DBG_CLIENT_BLKID_cb302 = 0x85, + DBG_CLIENT_BLKID_cb202 = 0x86, + DBG_CLIENT_BLKID_cb300 = 0x87, + DBG_CLIENT_BLKID_cb200 = 0x88, + DBG_CLIENT_BLKID_pa01 = 0x89, + DBG_CLIENT_BLKID_pa11 = 0x8a, + DBG_CLIENT_BLKID_sx30 = 0x8b, + DBG_CLIENT_BLKID_cb303 = 0x8c, + DBG_CLIENT_BLKID_cb301 = 0x8d, + DBG_CLIENT_BLKID_dco = 0x8e, + DBG_CLIENT_BLKID_scb0 = 0x8f, + DBG_CLIENT_BLKID_scb1 = 0x90, + DBG_CLIENT_BLKID_scb2 = 0x91, + DBG_CLIENT_BLKID_scb3 = 0x92, + DBG_CLIENT_BLKID_tmonw01 = 0x93, + DBG_CLIENT_BLKID_RESERVED_LAST = 0x94, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_SNORM_OGL = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_SNORM_OGL = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_UBNORM = 0xa, + IMG_NUM_FORMAT_UBNORM_OGL = 0xb, + IMG_NUM_FORMAT_UBINT = 0xc, + IMG_NUM_FORMAT_UBSCALED = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, + TCC_CACHE_POLICY_BYPASS = 0x2, +} TCC_CACHE_POLICIES; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; + +#endif /* GFX_7_2_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h new file mode 100644 index 000000000000..4509c8237db5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h @@ -0,0 +1,18444 @@ +/* + * GFX_7_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_7_2_SH_MASK_H +#define GFX_7_2_SH_MASK_H + +#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff +#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 +#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff +#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 +#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff +#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 +#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff +#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 +#define CB_COLOR_CONTROL__MODE_MASK 0x70 +#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 +#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000 +#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR0_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR0_INFO__FORMAT_MASK 0x7c +#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR1_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR1_INFO__FORMAT_MASK 0x7c +#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR2_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR2_INFO__FORMAT_MASK 0x7c +#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR3_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR3_INFO__FORMAT_MASK 0x7c +#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR4_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR4_INFO__FORMAT_MASK 0x7c +#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR5_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR5_INFO__FORMAT_MASK 0x7c +#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR6_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR6_INFO__FORMAT_MASK 0x7c +#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR7_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR7_INFO__FORMAT_MASK 0x7c +#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf +#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0 +#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 +#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00 +#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 +#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000 +#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc +#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000 +#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 +#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000 +#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 +#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000 +#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 +#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000 +#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c +#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf +#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 +#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00 +#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 +#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000 +#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc +#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000 +#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 +#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000 +#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 +#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000 +#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 +#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000 +#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0 +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000 +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000 +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000 +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 +#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000 +#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000 +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000 +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000 +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000 +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000 +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000 +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000 +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0 +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000 +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 +#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000 +#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00 +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000 +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf +#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff000000 +#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x18 +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1 +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000 +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000 +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf +#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x1 +#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x0 +#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x2 +#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x1 +#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x4 +#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x2 +#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x20 +#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x5 +#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x40 +#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x6 +#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x80 +#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x7 +#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x100 +#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x8 +#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x200 +#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x9 +#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x400 +#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0xa +#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x7f800 +#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0xb +#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x1 +#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x0 +#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x2 +#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x1 +#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x4 +#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x2 +#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x20 +#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x5 +#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x40 +#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x6 +#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x80 +#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x7 +#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x100 +#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x8 +#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x3 +#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x0 +#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x4 +#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x2 +#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x20 +#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x5 +#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x40 +#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x6 +#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x80 +#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x7 +#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x100 +#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x8 +#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x3f +#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x0 +#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x3c0 +#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x6 +#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0xfc00 +#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0xa +#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0xf0000 +#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x10 +#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x100000 +#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14 +#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x200000 +#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15 +#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x400000 +#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16 +#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x1 +#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x0 +#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x2 +#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x1 +#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x4 +#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x2 +#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x20 +#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x5 +#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x40 +#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x6 +#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x80 +#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x7 +#define CB_DEBUG_BUS_18__NOT_USED_MASK 0xffffff +#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x0 +#define CP_DFY_CNTL__POLICY_MASK 0x300 +#define CP_DFY_CNTL__POLICY__SHIFT 0x8 +#define CP_DFY_CNTL__VOL_MASK 0x400 +#define CP_DFY_CNTL__VOL__SHIFT 0xa +#define CP_DFY_CNTL__ATC_MASK 0x800 +#define CP_DFY_CNTL__ATC__SHIFT 0xb +#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff +#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 +#define CP_DFY_STAT__TAGS_PENDING_MASK 0xff0000 +#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 +#define CP_DFY_STAT__BUSY_MASK 0x80000000 +#define CP_DFY_STAT__BUSY__SHIFT 0x1f +#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff +#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0 +#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CP_DFY_DATA_0__DATA_MASK 0xffffffff +#define CP_DFY_DATA_0__DATA__SHIFT 0x0 +#define CP_DFY_DATA_1__DATA_MASK 0xffffffff +#define CP_DFY_DATA_1__DATA__SHIFT 0x0 +#define CP_DFY_DATA_2__DATA_MASK 0xffffffff +#define CP_DFY_DATA_2__DATA__SHIFT 0x0 +#define CP_DFY_DATA_3__DATA_MASK 0xffffffff +#define CP_DFY_DATA_3__DATA__SHIFT 0x0 +#define CP_DFY_DATA_4__DATA_MASK 0xffffffff +#define CP_DFY_DATA_4__DATA__SHIFT 0x0 +#define CP_DFY_DATA_5__DATA_MASK 0xffffffff +#define CP_DFY_DATA_5__DATA__SHIFT 0x0 +#define CP_DFY_DATA_6__DATA_MASK 0xffffffff +#define CP_DFY_DATA_6__DATA__SHIFT 0x0 +#define CP_DFY_DATA_7__DATA_MASK 0xffffffff +#define CP_DFY_DATA_7__DATA__SHIFT 0x0 +#define CP_DFY_DATA_8__DATA_MASK 0xffffffff +#define CP_DFY_DATA_8__DATA__SHIFT 0x0 +#define CP_DFY_DATA_9__DATA_MASK 0xffffffff +#define CP_DFY_DATA_9__DATA__SHIFT 0x0 +#define CP_DFY_DATA_10__DATA_MASK 0xffffffff +#define CP_DFY_DATA_10__DATA__SHIFT 0x0 +#define CP_DFY_DATA_11__DATA_MASK 0xffffffff +#define CP_DFY_DATA_11__DATA__SHIFT 0x0 +#define CP_DFY_DATA_12__DATA_MASK 0xffffffff +#define CP_DFY_DATA_12__DATA__SHIFT 0x0 +#define CP_DFY_DATA_13__DATA_MASK 0xffffffff +#define CP_DFY_DATA_13__DATA__SHIFT 0x0 +#define CP_DFY_DATA_14__DATA_MASK 0xffffffff +#define CP_DFY_DATA_14__DATA__SHIFT 0x0 +#define CP_DFY_DATA_15__DATA_MASK 0xffffffff +#define CP_DFY_DATA_15__DATA__SHIFT 0x0 +#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff +#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff +#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB2_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB0_CNTL__BUF_SWAP_MASK 0x30000 +#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x10 +#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x3000000 +#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x4000000 +#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a +#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB_CNTL__BUF_SWAP_MASK 0x30000 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x10 +#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB_CNTL__CACHE_POLICY_MASK 0x3000000 +#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB_CNTL__RB_VOLATILE_MASK 0x4000000 +#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x3000000 +#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x4000000 +#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a +#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x3000000 +#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x4000000 +#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x1a +#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffc +#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x2 +#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0xff +#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x0 +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff +#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3 +#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0 +#define CP_RB_VMID__RB0_VMID_MASK 0xf +#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 +#define CP_RB_VMID__RB1_VMID_MASK 0xf00 +#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 +#define CP_RB_VMID__RB2_VMID_MASK 0xf0000 +#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 +#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf +#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf +#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0xfff +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0xfff +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0xfff +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 +#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff +#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x1 +#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x0 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2 +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 +#define CP_MEM_SLP_CNTL__RESERVED_MASK 0xfc +#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 +#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0xf0 +#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x3c00 +#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000 +#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 +#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x3 +#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0xf0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x3c00 +#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0xf0000 +#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x10 +#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x3 +#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0xf0 +#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x3c00 +#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0xf0000 +#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x10 +#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x3 +#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0xf0 +#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x3c00 +#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0xf0000 +#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x10 +#define CP_FETCHER_SOURCE__ME_SRC_MASK 0x1 +#define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff +#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000 +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e +#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000 +#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff +#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x7ff +#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x7ff +#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xfff +#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xfff +#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff +#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x7ff +#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x7ff +#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xfff +#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xfff +#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 +#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7 +#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 +#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000 +#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff +#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 +#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00 +#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 +#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000 +#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 +#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff +#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 +#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000 +#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10 +#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff +#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 +#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000 +#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x10 +#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xffff +#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1 +#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2 +#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1 +#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 +#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2 +#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 +#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4 +#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 +#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8 +#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 +#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10 +#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 +#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20 +#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 +#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40 +#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 +#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80 +#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 +#define CP_CPC_STATUS__MIU_RDREQ_BUSY_MASK 0x100 +#define CP_CPC_STATUS__MIU_RDREQ_BUSY__SHIFT 0x8 +#define CP_CPC_STATUS__MIU_WRREQ_BUSY_MASK 0x200 +#define CP_CPC_STATUS__MIU_WRREQ_BUSY__SHIFT 0x9 +#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400 +#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800 +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb +#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000 +#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc +#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000 +#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d +#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000 +#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e +#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000 +#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1 +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2 +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800 +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000 +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000 +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000 +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000 +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d +#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL_MASK 0x1 +#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL__SHIFT 0x0 +#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL_MASK 0x2 +#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL__SHIFT 0x1 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ_MASK 0x800 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ__SHIFT 0xb +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK_MASK 0x1000 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK__SHIFT 0xc +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000 +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ_MASK 0x80000 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ__SHIFT 0x13 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK_MASK 0x100000 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK__SHIFT 0x14 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1 +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 +#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2 +#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 +#define CP_CPF_STATUS__MIU_RDREQ_BUSY_MASK 0x4 +#define CP_CPF_STATUS__MIU_RDREQ_BUSY__SHIFT 0x2 +#define CP_CPF_STATUS__MIU_WRREQ_BUSY_MASK 0x8 +#define CP_CPF_STATUS__MIU_WRREQ_BUSY__SHIFT 0x3 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 +#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20 +#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 +#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100 +#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb +#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000 +#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc +#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000 +#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd +#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000 +#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe +#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000 +#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf +#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000 +#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e +#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000 +#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200 +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800 +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000 +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000 +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000 +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000 +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000 +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000 +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000 +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000 +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000 +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1 +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 +#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10 +#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x4 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 +#define CP_CPC_MC_CNTL__PACK_DELAY_CNT_MASK 0x1f +#define CP_CPC_MC_CNTL__PACK_DELAY_CNT__SHIFT 0x0 +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10 +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 +#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c +#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000 +#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d +#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 +#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e +#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000 +#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf +#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 +#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff +#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 +#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff +#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff +#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff +#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000 +#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 +#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100 +#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 +#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff +#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff +#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3 +#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc +#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2 +#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00 +#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa +#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000 +#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12 +#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000 +#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13 +#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP_MASK 0x300000 +#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP__SHIFT 0x14 +#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000 +#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17 +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc +#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x6000000 +#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19 +#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x8000000 +#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b +#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff +#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0 +#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000 +#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d +#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x3 +#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x0 +#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc +#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff +#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff +#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x3 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x0 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x3 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x0 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1 +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff +#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 +#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000 +#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 +#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff +#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000 +#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 +#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000 +#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d +#define CP_APPEND_DATA__DATA_MASK 0xffffffff +#define CP_APPEND_DATA__DATA__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 +#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f +#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 +#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1 +#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 +#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2 +#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 +#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40 +#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 +#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80 +#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 +#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100 +#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 +#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200 +#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 +#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400 +#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa +#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800 +#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb +#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000 +#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc +#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000 +#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd +#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000 +#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000 +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf +#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x10000 +#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x10 +#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000 +#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 +#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000 +#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 +#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000 +#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 +#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000 +#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 +#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000 +#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 +#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000 +#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 +#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000 +#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000 +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000 +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000 +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d +#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff +#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff +#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff +#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 +#define CP_COHER_STATUS__MEID_MASK 0x3000000 +#define CP_COHER_STATUS__MEID__SHIFT 0x18 +#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000 +#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e +#define CP_COHER_STATUS__STATUS_MASK 0x80000000 +#define CP_COHER_STATUS__STATUS__SHIFT 0x1f +#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff +#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000 +#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x6000 +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_ME_CONTROL__SRC_VOLATILE_MASK 0x8000 +#define CP_DMA_ME_CONTROL__SRC_VOLATILE__SHIFT 0xf +#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000 +#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000 +#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x6000000 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_ME_CONTROL__DST_VOLATILE_MASK 0x8000000 +#define CP_DMA_ME_CONTROL__DST_VOLATILE__SHIFT 0x1b +#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000 +#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff +#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000 +#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15 +#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000 +#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16 +#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000 +#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18 +#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000 +#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000 +#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000 +#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000 +#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000 +#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff +#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000 +#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x6000 +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_PFP_CONTROL__SRC_VOLATILE_MASK 0x8000 +#define CP_DMA_PFP_CONTROL__SRC_VOLATILE__SHIFT 0xf +#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000 +#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000 +#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x6000000 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_PFP_CONTROL__DST_VOLATILE_MASK 0x8000000 +#define CP_DMA_PFP_CONTROL__DST_VOLATILE__SHIFT 0x1b +#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000 +#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff +#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000 +#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15 +#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000 +#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16 +#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000 +#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18 +#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000 +#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000 +#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000 +#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000 +#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000 +#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30 +#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 +#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000 +#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c +#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000 +#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d +#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000 +#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e +#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff +#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c +#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff +#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1 +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x8000 +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000 +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff +#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff +#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff +#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff +#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff +#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 +#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff +#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff +#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff +#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000 +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000 +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd +#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x4000 +#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0xe +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000 +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf +#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10000 +#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x10 +#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x20000 +#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x11 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000 +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 +#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x40 +#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x6 +#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x80 +#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x7 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800 +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000 +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000 +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000 +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000 +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000 +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000 +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000 +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000 +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000 +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 +#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x100 +#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x8 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800 +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000 +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000 +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000 +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000 +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 +#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100 +#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 +#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200 +#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 +#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400 +#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000 +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000 +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000 +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000 +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf +#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000 +#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 +#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000 +#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 +#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000 +#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 +#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000 +#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 +#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000 +#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 +#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000 +#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 +#define CP_STAT__MIU_RDREQ_BUSY_MASK 0x80 +#define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x7 +#define CP_STAT__MIU_WRREQ_BUSY_MASK 0x100 +#define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x8 +#define CP_STAT__ROQ_RING_BUSY_MASK 0x200 +#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 +#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400 +#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa +#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800 +#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb +#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000 +#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc +#define CP_STAT__DC_BUSY_MASK 0x2000 +#define CP_STAT__DC_BUSY__SHIFT 0xd +#define CP_STAT__PFP_BUSY_MASK 0x8000 +#define CP_STAT__PFP_BUSY__SHIFT 0xf +#define CP_STAT__MEQ_BUSY_MASK 0x10000 +#define CP_STAT__MEQ_BUSY__SHIFT 0x10 +#define CP_STAT__ME_BUSY_MASK 0x20000 +#define CP_STAT__ME_BUSY__SHIFT 0x11 +#define CP_STAT__QUERY_BUSY_MASK 0x40000 +#define CP_STAT__QUERY_BUSY__SHIFT 0x12 +#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000 +#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 +#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000 +#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 +#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000 +#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 +#define CP_STAT__DMA_BUSY_MASK 0x400000 +#define CP_STAT__DMA_BUSY__SHIFT 0x16 +#define CP_STAT__RCIU_BUSY_MASK 0x800000 +#define CP_STAT__RCIU_BUSY__SHIFT 0x17 +#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000 +#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 +#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000 +#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19 +#define CP_STAT__CE_BUSY_MASK 0x4000000 +#define CP_STAT__CE_BUSY__SHIFT 0x1a +#define CP_STAT__TCIU_BUSY_MASK 0x8000000 +#define CP_STAT__TCIU_BUSY__SHIFT 0x1b +#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000 +#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000 +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000 +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e +#define CP_STAT__CP_BUSY_MASK 0x80000000 +#define CP_STAT__CP_BUSY__SHIFT 0x1f +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f +#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 +#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x1f +#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x0 +#define CP_MC_TAG_CNTL__TAG_RAM_INDEX_MASK 0x3f +#define CP_MC_TAG_CNTL__TAG_RAM_INDEX__SHIFT 0x0 +#define CP_MC_TAG_CNTL__TAG_RAM_SEL_MASK 0x30000 +#define CP_MC_TAG_CNTL__TAG_RAM_SEL__SHIFT 0x10 +#define CP_MC_TAG_DATA__TAG_RAM_DATA_MASK 0xffffffff +#define CP_MC_TAG_DATA__TAG_RAM_DATA__SHIFT 0x0 +#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf +#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x3f00 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 +#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf +#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0 +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10 +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 +#define CP_ME_CNTL__CE_HALT_MASK 0x1000000 +#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 +#define CP_ME_CNTL__CE_STEP_MASK 0x2000000 +#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 +#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000 +#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a +#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000 +#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c +#define CP_ME_CNTL__ME_STEP_MASK 0x20000000 +#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c +#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x1 +#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x0 +#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0 +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc +#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff +#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc +#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff +#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc +#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 +#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff +#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 +#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff +#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 +#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00 +#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 +#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff +#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff +#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00 +#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 +#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000 +#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 +#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff +#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 +#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00 +#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 +#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000 +#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 +#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff +#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 +#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00 +#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 +#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000 +#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00 +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 +#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff +#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 +#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00 +#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 +#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff +#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 +#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff +#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000 +#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x30000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff +#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 +#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff +#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 +#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff +#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000 +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000 +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000 +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000 +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000 +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000 +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f +#define CP_RINGID__RINGID_MASK 0x3 +#define CP_RINGID__RINGID__SHIFT 0x0 +#define CP_PIPEID__PIPE_ID_MASK 0x3 +#define CP_PIPEID__PIPE_ID__SHIFT 0x0 +#define CP_VMID__VMID_MASK 0xf +#define CP_VMID__VMID__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff +#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff +#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HPD_EOP_VMID__VMID_MASK 0xf +#define CP_HPD_EOP_VMID__VMID__SHIFT 0x0 +#define CP_HPD_EOP_CONTROL__EOP_SIZE_MASK 0x3f +#define CP_HPD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 +#define CP_HPD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100 +#define CP_HPD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 +#define CP_HPD_EOP_CONTROL__PROCESSING_QID_MASK 0xe00 +#define CP_HPD_EOP_CONTROL__PROCESSING_QID__SHIFT 0x9 +#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000 +#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc +#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000 +#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd +#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000 +#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe +#define CP_HPD_EOP_CONTROL__EOP_ATC_MASK 0x800000 +#define CP_HPD_EOP_CONTROL__EOP_ATC__SHIFT 0x17 +#define CP_HPD_EOP_CONTROL__CACHE_POLICY_MASK 0x3000000 +#define CP_HPD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HPD_EOP_CONTROL__EOP_VOLATILE_MASK 0x4000000 +#define CP_HPD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a +#define CP_HPD_EOP_CONTROL__PEND_Q_SEM_MASK 0x70000000 +#define CP_HPD_EOP_CONTROL__PEND_Q_SEM__SHIFT 0x1c +#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000 +#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f +#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc +#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1 +#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_HQD_VMID__VMID_MASK 0xf +#define CP_HQD_VMID__VMID__SHIFT 0x0 +#define CP_HQD_VMID__IB_VMID_MASK 0xf00 +#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 +#define CP_HQD_VMID__VQID_MASK 0x3ff0000 +#define CP_HQD_VMID__VQID__SHIFT 0x10 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000 +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3 +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1 +#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10 +#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 +#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00 +#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff +#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 +#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff +#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff +#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x30000 +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x10 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000 +#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x3000000 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x4000000 +#define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000 +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000 +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d +#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000 +#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e +#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000 +#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff +#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000 +#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x3000000 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x4000000 +#define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a +#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000 +#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f +#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff +#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700 +#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000 +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000 +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 +#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000 +#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17 +#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x3000000 +#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x4000000 +#define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000 +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d +#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000 +#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e +#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000 +#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f +#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x3 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1 +#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 +#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6 +#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 +#define CP_HQD_MSG_TYPE__ACTION_MASK 0x3 +#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS_MASK 0x3 +#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT_MASK 0xc +#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT__SHIFT 0x2 +#define CP_HQD_HQ_SCHEDULER0__RSV_5_4_MASK 0x30 +#define CP_HQD_HQ_SCHEDULER0__RSV_5_4__SHIFT 0x4 +#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK 0x40 +#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT 0x6 +#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK 0x80 +#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK 0x100 +#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED_MASK 0x200 +#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED__SHIFT 0x9 +#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED_MASK 0x400 +#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED__SHIFT 0xa +#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11_MASK 0xfffff800 +#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11__SHIFT 0xb +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 +#define CP_MQD_CONTROL__VMID_MASK 0xf +#define CP_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000 +#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17 +#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x3000000 +#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x4000000 +#define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a +#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff +#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff +#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff +#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff +#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf +#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0 +#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0 +#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4 +#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00 +#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8 +#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000 +#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd +#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000 +#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf +#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000 +#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11 +#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000 +#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13 +#define DB_Z_INFO__FORMAT_MASK 0x3 +#define DB_Z_INFO__FORMAT__SHIFT 0x0 +#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc +#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 +#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000 +#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd +#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000 +#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14 +#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 +#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_Z_INFO__READ_SIZE_MASK 0x10000000 +#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c +#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000 +#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d +#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000 +#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f +#define DB_STENCIL_INFO__FORMAT_MASK 0x1 +#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 +#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000 +#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd +#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000 +#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14 +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000 +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d +#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff +#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0 +#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800 +#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb +#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff +#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff +#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000 +#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd +#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000 +#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1 +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 +#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4 +#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 +#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8 +#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 +#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80 +#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 +#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00 +#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1 +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2 +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 +#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70 +#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 +#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00 +#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc +#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000 +#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3 +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa +#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800 +#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000 +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000 +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000 +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000 +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000 +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000 +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000 +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000 +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000 +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000 +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000 +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000 +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800 +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000 +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000 +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000 +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 +#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7 +#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 +#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70 +#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000 +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 +#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000 +#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 +#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000 +#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 +#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000 +#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1 +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 +#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30 +#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 +#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40 +#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800 +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000 +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000 +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd +#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff +#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff +#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 +#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff +#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 +#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff +#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 +#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff +#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 +#define DB_HTILE_SURFACE__LINEAR_MASK 0x1 +#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0 +#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2 +#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4 +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 +#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8 +#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 +#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0 +#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00 +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000 +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 +#define DB_PRELOAD_CONTROL__START_X_MASK 0xff +#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 +#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00 +#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 +#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000 +#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 +#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000 +#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 +#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff +#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 +#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00 +#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 +#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000 +#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 +#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000 +#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000 +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000 +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 +#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1 +#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 +#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2 +#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 +#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70 +#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 +#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700 +#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000 +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000 +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f +#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf +#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 +#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0 +#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 +#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00 +#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc +#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000 +#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe +#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000 +#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1 +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 +#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4 +#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 +#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30 +#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000 +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000 +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000 +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 +#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000 +#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 +#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000 +#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000 +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000 +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000 +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1 +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4 +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5 +#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40 +#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7 +#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100 +#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8 +#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00 +#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000 +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000 +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000 +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000 +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000 +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000 +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000 +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f +#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4 +#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80 +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200 +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800 +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000 +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000 +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000 +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000 +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000 +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000 +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 +#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000 +#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000 +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000 +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000 +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d +#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xc0000000 +#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x1e +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 +#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0 +#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4 +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000 +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 +#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f +#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 +#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0 +#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 +#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800 +#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb +#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000 +#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000 +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 +#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000 +#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b +#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000 +#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c +#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000 +#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d +#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000 +#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e +#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000 +#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f +#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3 +#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 +#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc +#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 +#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30 +#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 +#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0 +#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 +#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300 +#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 +#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00 +#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa +#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000 +#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc +#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000 +#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe +#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000 +#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 +#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000 +#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000 +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15 +#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000 +#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19 +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0 +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5 +#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00 +#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa +#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000 +#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000 +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000 +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 +#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf +#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0 +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 +#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000 +#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f +#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff +#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 +#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3 +#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 +#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff +#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0 +#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff +#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0 +#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff +#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0 +#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 +#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 +#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 +#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 +#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 +#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff +#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 +#define GB_GPU_ID__GPU_ID_MASK 0xf +#define GB_GPU_ID__GPU_ID__SHIFT 0x0 +#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf +#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 +#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0 +#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 +#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00 +#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 +#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000 +#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc +#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000 +#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 +#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000 +#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 +#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000 +#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 +#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000 +#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c +#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 +#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000 +#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10 +#define GB_EDC_MODE__DED_MODE_MASK 0x300000 +#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 +#define GB_EDC_MODE__PROP_FED_MASK 0x20000000 +#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d +#define GB_EDC_MODE__BYPASS_MASK 0x80000000 +#define GB_EDC_MODE__BYPASS__SHIFT 0x1f +#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1 +#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 +#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 +#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 +#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7 +#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff +#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 +#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff +#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 +#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0 +#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 +#define GRBM_PWR_CNTL__REQ_TYPE_MASK 0xf +#define GRBM_PWR_CNTL__REQ_TYPE__SHIFT 0x0 +#define GRBM_PWR_CNTL__RSP_TYPE_MASK 0xf0 +#define GRBM_PWR_CNTL__RSP_TYPE__SHIFT 0x4 +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20 +#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200 +#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS__DB_CLEAN_MASK 0x1000 +#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc +#define GRBM_STATUS__CB_CLEAN_MASK 0x2000 +#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd +#define GRBM_STATUS__TA_BUSY_MASK 0x4000 +#define GRBM_STATUS__TA_BUSY__SHIFT 0xe +#define GRBM_STATUS__GDS_BUSY_MASK 0x8000 +#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf +#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000 +#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 +#define GRBM_STATUS__VGT_BUSY_MASK 0x20000 +#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 +#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000 +#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 +#define GRBM_STATUS__IA_BUSY_MASK 0x80000 +#define GRBM_STATUS__IA_BUSY__SHIFT 0x13 +#define GRBM_STATUS__SX_BUSY_MASK 0x100000 +#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 +#define GRBM_STATUS__WD_BUSY_MASK 0x200000 +#define GRBM_STATUS__WD_BUSY__SHIFT 0x15 +#define GRBM_STATUS__SPI_BUSY_MASK 0x400000 +#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 +#define GRBM_STATUS__BCI_BUSY_MASK 0x800000 +#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 +#define GRBM_STATUS__SC_BUSY_MASK 0x1000000 +#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 +#define GRBM_STATUS__PA_BUSY_MASK 0x2000000 +#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 +#define GRBM_STATUS__DB_BUSY_MASK 0x4000000 +#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a +#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000 +#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c +#define GRBM_STATUS__CP_BUSY_MASK 0x20000000 +#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d +#define GRBM_STATUS__CB_BUSY_MASK 0x40000000 +#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e +#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000 +#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400 +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800 +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000 +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000 +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd +#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000 +#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe +#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000 +#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 +#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000 +#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 +#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000 +#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c +#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000 +#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d +#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000 +#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f +#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1 +#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 +#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000 +#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 +#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f +#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0 +#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff +#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0 +#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff +#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00 +#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000 +#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000 +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000 +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 +#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2 +#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1 +#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20 +#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5 +#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40 +#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6 +#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80 +#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7 +#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00 +#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8 +#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000 +#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc +#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1 +#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0 +#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2 +#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1 +#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4 +#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4 +#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20 +#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15 +#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc +#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000 +#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 +#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000 +#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 +#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 +#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000 +#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11 +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000 +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f +#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1 +#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff +#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff +#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff +#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff +#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff +#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff +#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff +#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff +#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff +#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0 +#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff +#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 +#define GRBM_NOWHERE__DATA_MASK 0xffffffff +#define GRBM_NOWHERE__DATA__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1 +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800 +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800 +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000 +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000 +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000 +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000 +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 +#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8 +#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 +#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10 +#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 +#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd +#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000 +#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000 +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000 +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1 +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20 +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000 +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1 +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1 +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 +#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10 +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000 +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000 +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7 +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000 +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c +#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff +#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_TRI_MASK 0xf +#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0 +#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 +#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00 +#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 +#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000 +#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc +#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000 +#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 +#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000 +#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 +#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000 +#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800 +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000 +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000 +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1 +#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800 +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000 +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000 +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000 +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000 +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000 +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000 +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000 +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30 +#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40 +#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 +#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80 +#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 +#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300 +#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 +#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00 +#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa +#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000 +#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc +#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000 +#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe +#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000 +#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 +#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000 +#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 +#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000 +#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 +#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000 +#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 +#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000 +#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a +#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000 +#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 +#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff +#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff +#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1 +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 +#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0 +#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000 +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000 +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000 +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000 +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000 +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000 +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000 +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000 +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17 +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000 +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 +#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff +#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff +#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff +#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000 +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000 +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 +#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000 +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000 +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000 +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0 +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0 +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8 +#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600 +#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0 +#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700 +#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8 +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800 +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a +#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000 +#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c +#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000 +#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f +#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7 +#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0 +#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38 +#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19 +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000 +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000 +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000 +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000 +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b +#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000 +#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c +#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000 +#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d +#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000 +#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e +#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000 +#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19 +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000 +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000 +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000 +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000 +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7 +#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0 +#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8 +#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3 +#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10 +#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4 +#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20 +#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5 +#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40 +#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6 +#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80 +#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7 +#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00 +#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8 +#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000 +#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc +#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000 +#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe +#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000 +#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf +#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000 +#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10 +#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000 +#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc +#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000 +#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12 +#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13 +#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14 +#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e +#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff +#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a +#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380 +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7 +#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00 +#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa +#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000 +#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf +#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000 +#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10 +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c +#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f +#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7 +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8 +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000 +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000 +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000 +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000 +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f +#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3 +#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2 +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8 +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000 +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf +#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000 +#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10 +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000 +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12 +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000 +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13 +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000 +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14 +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15 +#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000 +#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16 +#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c +#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000 +#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d +#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000 +#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e +#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000 +#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f +#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff +#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0 +#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000 +#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10 +#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff +#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0 +#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000 +#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10 +#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff +#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0 +#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000 +#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0 +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000 +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000 +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10 +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000 +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13 +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14 +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17 +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18 +#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000 +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000 +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c +#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000 +#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e +#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000 +#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f +#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3 +#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0 +#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc +#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2 +#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3 +#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0 +#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc +#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1 +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 +#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380 +#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800 +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb +#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000 +#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc +#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000 +#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe +#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff +#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff +#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff +#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 +#define COMPUTE_START_X__START_MASK 0xffffffff +#define COMPUTE_START_X__START__SHIFT 0x0 +#define COMPUTE_START_Y__START_MASK 0xffffffff +#define COMPUTE_START_Y__START__SHIFT 0x0 +#define COMPUTE_START_Z__START_MASK 0xffffffff +#define COMPUTE_START_Z__START__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 +#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff +#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__DATA_MASK 0xff +#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100 +#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8 +#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff +#define COMPUTE_TBA_LO__DATA__SHIFT 0x0 +#define COMPUTE_TBA_HI__DATA_MASK 0xff +#define COMPUTE_TBA_HI__DATA__SHIFT 0x0 +#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff +#define COMPUTE_TMA_LO__DATA__SHIFT 0x0 +#define COMPUTE_TMA_HI__DATA_MASK 0xff +#define COMPUTE_TMA_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f +#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0 +#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 +#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00 +#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa +#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000 +#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc +#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000 +#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 +#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000 +#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 +#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000 +#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 +#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000 +#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 +#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000 +#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 +#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e +#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40 +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 +#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80 +#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800 +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000 +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd +#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000 +#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf +#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000 +#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 +#define COMPUTE_VMID__DATA_MASK 0xf +#define COMPUTE_VMID__DATA__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000 +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff +#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 +#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff +#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff +#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff +#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3 +#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4 +#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 +#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8 +#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 +#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10 +#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 +#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 +#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff +#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0 +#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000 +#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15 +#define CSPRIV_CONNECT__VMID_MASK 0x3c000000 +#define CSPRIV_CONNECT__VMID__SHIFT 0x1a +#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000 +#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f +#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff +#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff +#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff +#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff +#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000 +#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a +#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000 +#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b +#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000 +#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c +#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f +#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0 +#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 +#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 +#define RLC_CNTL__FORCE_RETRY_MASK 0x2 +#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 +#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4 +#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 +#define RLC_CNTL__RLC_STEP_F32_MASK 0x8 +#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 +#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10 +#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4 +#define RLC_CNTL__RESERVED_MASK 0xffffff00 +#define RLC_CNTL__RESERVED__SHIFT 0x8 +#define RLC_DEBUG_SELECT__SELECT_MASK 0xff +#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0 +#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00 +#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8 +#define RLC_DEBUG__DATA_MASK 0xffffffff +#define RLC_DEBUG__DATA__SHIFT 0x0 +#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3 +#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0 +#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4 +#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2 +#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8 +#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3 +#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10 +#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4 +#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0 +#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5 +#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00 +#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9 +#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000 +#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd +#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000 +#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14 +#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000 +#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18 +#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000 +#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a +#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000 +#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b +#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000 +#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c +#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000 +#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d +#define RLC_STAT__RLC_BUSY_MASK 0x1 +#define RLC_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2 +#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1 +#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4 +#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2 +#define RLC_STAT__RESERVED_MASK 0xfffffff8 +#define RLC_STAT__RESERVED__SHIFT 0x3 +#define RLC_SAFE_MODE__REQ_MASK 0x1 +#define RLC_SAFE_MODE__REQ__SHIFT 0x0 +#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e +#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SAFE_MODE__RESERVED_MASK 0xffffffe0 +#define RLC_SAFE_MODE__RESERVED__SHIFT 0x5 +#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1 +#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0 +#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe +#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 +#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0xfc +#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 +#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7 +#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1 +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 +#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2 +#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4 +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 +#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8 +#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0 +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 +#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000 +#define RLC_LB_CNTL__RESERVED__SHIFT 0xc +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 +#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff +#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0 +#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff +#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0 +#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe +#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4 +#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0 +#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000 +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 +#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff +#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0 +#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xffffff00 +#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0x8 +#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff +#define RLC_GPM_DEBUG__DATA__SHIFT 0x0 +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000 +#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc +#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 +#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1 +#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2 +#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8 +#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_GPM_STAT__RESERVED_MASK 0xfffffff0 +#define RLC_GPM_STAT__RESERVED__SHIFT 0x4 +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4 +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8 +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 +#define RLC_PG_CNTL__RESERVED_MASK 0xfff0 +#define RLC_PG_CNTL__RESERVED__SHIFT 0x4 +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000 +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 +#define RLC_PG_CNTL__RESERVED1_MASK 0xf80000 +#define RLC_PG_CNTL__RESERVED1__SHIFT 0x13 +#define RLC_PG_CNTL__PG_ERROR_STATUS_MASK 0xff000000 +#define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 +#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0 +#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 +#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf +#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0 +#define RLC_GPM_VMID_THREAD0__RESERVED_MASK 0xfffffff0 +#define RLC_GPM_VMID_THREAD0__RESERVED__SHIFT 0x4 +#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf +#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0 +#define RLC_GPM_VMID_THREAD1__RESERVED_MASK 0xfffffff0 +#define RLC_GPM_VMID_THREAD1__RESERVED__SHIFT 0x4 +#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff +#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 +#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000 +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000 +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d +#define RLC_CGCG_CGLS_CTRL__SPARE_MASK 0x80000000 +#define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT 0x1f +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff +#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00 +#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 +#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff +#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 +#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1 +#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 +#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe +#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00 +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000 +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 +#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000 +#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 +#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00 +#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 +#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1 +#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0 +#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe +#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1 +#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1 +#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0 +#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe +#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1 +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30 +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0 +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x3800 +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0xc000 +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xe +#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xffff0000 +#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x10 +#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff +#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff +#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff +#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x20000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x11 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x40000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x12 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x80000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x13 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x100000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x14 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x200000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x15 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x400000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x16 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff800000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x17 +#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff +#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 +#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100 +#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 +#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200 +#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 +#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400 +#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa +#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800 +#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000 +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc +#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000 +#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd +#define RLC_SERDES_WR_CTRL__RESERVED_1_MASK 0xc000 +#define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT 0xe +#define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK 0x10000 +#define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT 0x10 +#define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK 0x20000 +#define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT 0x11 +#define RLC_SERDES_WR_CTRL__CGLS_ON_MASK 0x40000 +#define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT 0x12 +#define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK 0x80000 +#define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT 0x13 +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK 0x100000 +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT 0x14 +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK 0x200000 +#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT 0x15 +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK 0x400000 +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT 0x16 +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK 0x800000 +#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT 0x17 +#define RLC_SERDES_WR_CTRL__RESERVED_2_MASK 0xf000000 +#define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT 0x18 +#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000 +#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c +#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff +#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x20000 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x11 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x40000 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x12 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x80000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x13 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x100000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x14 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x200000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x15 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x400000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x16 +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff800000 +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x17 +#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff +#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff +#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00 +#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 +#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff +#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00 +#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000 +#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000 +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000 +#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000 +#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000 +#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00 +#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000 +#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000 +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000 +#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000 +#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000 +#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 +#define RLC_GPR_REG1__DATA_MASK 0xffffffff +#define RLC_GPR_REG1__DATA__SHIFT 0x0 +#define RLC_GPR_REG2__DATA_MASK 0xffffffff +#define RLC_GPR_REG2__DATA__SHIFT 0x0 +#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf +#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0 +#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0 +#define RLC_SPM_VMID__RESERVED__SHIFT 0x4 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 +#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe +#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 +#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe +#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 +#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff +#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0 +#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00 +#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8 +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000 +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000 +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10 +#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff +#define RLC_SPM_DEBUG__DATA__SHIFT 0x0 +#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff +#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff +#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 +#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff +#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 +#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff +#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc +#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000 +#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000 +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 +#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40 +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1 +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800 +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000 +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000 +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000 +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000 +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800 +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000 +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000 +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000 +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000 +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe +#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f +#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 +#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40 +#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1 +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000 +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 +#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff +#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 +#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000 +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc +#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000 +#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe +#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000 +#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 +#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff +#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000 +#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff +#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000 +#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 +#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1 +#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2 +#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1 +#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4 +#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8 +#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3 +#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10 +#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20 +#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5 +#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40 +#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 +#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1 +#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2 +#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1 +#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4 +#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8 +#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3 +#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10 +#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20 +#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5 +#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff +#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 +#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00 +#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 +#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000 +#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 +#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000 +#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 +#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff +#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0 +#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00 +#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8 +#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000 +#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10 +#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000 +#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18 +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x1f +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x1f +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x1f +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x1f +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x1f +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x1f +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x1f +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x1f +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x1f +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x1f +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 +#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3 +#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80 +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100 +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000 +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000 +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 +#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff +#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 +#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200 +#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 +#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff +#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff +#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff +#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff +#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4 +#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1 +#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000 +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000 +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b +#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1 +#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0 +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1 +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0 +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4 +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00 +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000 +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18 +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000 +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19 +#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000 +#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f +#define SPI_DEBUG_READ__DATA_MASK 0xffffff +#define SPI_DEBUG_READ__DATA__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf +#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc +#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000 +#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100 +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 +#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1 +#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0 +#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2 +#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1 +#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4 +#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2 +#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8 +#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3 +#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10 +#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4 +#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20 +#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5 +#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40 +#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6 +#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80 +#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7 +#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100 +#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8 +#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200 +#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9 +#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400 +#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa +#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800 +#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb +#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000 +#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc +#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000 +#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd +#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000 +#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe +#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000 +#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000 +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10 +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000 +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11 +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000 +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12 +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000 +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13 +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000 +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14 +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000 +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15 +#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000 +#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16 +#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000 +#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17 +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0 +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 +#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000 +#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc +#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000 +#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 +#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000 +#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000 +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 +#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000 +#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 +#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000 +#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 +#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00 +#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 +#define CGTS_RD_REG__READ_DATA_MASK 0x3fff +#define CGTS_RD_REG__READ_DATA__SHIFT 0x0 +#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 +#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000 +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000 +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000 +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000 +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000 +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 +#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000 +#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19 +#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000 +#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000 +#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000 +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000 +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000 +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 +#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10 +#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff +#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0 +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000 +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1 +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0 +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2 +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1 +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4 +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2 +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8 +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3 +#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10 +#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14 +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000 +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15 +#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1 +#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 +#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff +#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff +#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff +#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 +#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000 +#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 +#define BCI_DEBUG_READ__DATA_MASK 0xffffff +#define BCI_DEBUG_READ__DATA__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000 +#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000 +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000 +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000 +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000 +#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000 +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000 +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000 +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00 +#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000 +#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000 +#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000 +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00 +#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000 +#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14 +#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000 +#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000 +#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000 +#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000 +#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00 +#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000 +#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000 +#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000 +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100 +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 +#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000 +#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000 +#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000 +#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 +#define SQ_CONFIG__UNUSED_MASK 0xff +#define SQ_CONFIG__UNUSED__SHIFT 0x0 +#define SQ_CONFIG__DEBUG_EN_MASK 0x100 +#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8 +#define SQ_CONFIG__DISABLE_SCA_BYPASS_MASK 0x200 +#define SQ_CONFIG__DISABLE_SCA_BYPASS__SHIFT 0x9 +#define SQ_CONFIG__DISABLE_IB_DEP_CHECK_MASK 0x400 +#define SQ_CONFIG__DISABLE_IB_DEP_CHECK__SHIFT 0xa +#define SQ_CONFIG__ENABLE_SOFT_CLAUSE_MASK 0x800 +#define SQ_CONFIG__ENABLE_SOFT_CLAUSE__SHIFT 0xb +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000 +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000 +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000 +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000 +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf +#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3 +#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 +#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc +#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 +#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30 +#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 +#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40 +#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 +#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80 +#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 +#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100 +#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 +#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200 +#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 +#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400 +#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa +#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800 +#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb +#define SQC_CACHES__INST_INVALIDATE_MASK 0x1 +#define SQC_CACHES__INST_INVALIDATE__SHIFT 0x0 +#define SQC_CACHES__DATA_INVALIDATE_MASK 0x2 +#define SQC_CACHES__DATA_INVALIDATE__SHIFT 0x1 +#define SQC_CACHES__INVALIDATE_VOLATILE_MASK 0x4 +#define SQC_CACHES__INVALIDATE_VOLATILE__SHIFT 0x2 +#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f +#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 +#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380 +#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 +#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00 +#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa +#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f +#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 +#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00 +#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 +#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000 +#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c +#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000 +#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d +#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000 +#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e +#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000 +#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000 +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 +#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff +#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 +#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1 +#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1 +#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2 +#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 +#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4 +#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8 +#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 +#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10 +#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20 +#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 +#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40 +#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00 +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000 +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd +#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff +#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000 +#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 +#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 +#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 +#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 +#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 +#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 +#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 +#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c +#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 +#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 +#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 +#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 +#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 +#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 +#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 +#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0xff +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c +#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff +#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 +#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000 +#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 +#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000 +#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000 +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f +#define SQ_TIME_HI__TIME_MASK 0xffffffff +#define SQ_TIME_HI__TIME__SHIFT 0x0 +#define SQ_TIME_LO__TIME_MASK 0xffffffff +#define SQ_TIME_LO__TIME__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff +#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf +#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE2__ATC_MASK 0x10 +#define SQ_THREAD_TRACE_BASE2__ATC__SHIFT 0x4 +#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff +#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f +#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20 +#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80 +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 +#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00 +#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000 +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000 +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000 +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf +#define SQ_THREAD_TRACE_MASK__RANDOM_SEED_MASK 0xffff0000 +#define SQ_THREAD_TRACE_MASK__RANDOM_SEED__SHIFT 0x10 +#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7 +#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 +#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38 +#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 +#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0 +#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 +#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00 +#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 +#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000 +#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc +#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000 +#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf +#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000 +#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 +#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000 +#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000 +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000 +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 +#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000 +#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000 +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b +#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000 +#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000 +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e +#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000 +#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000 +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffff +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000 +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff +#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000 +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 +#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000 +#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d +#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000 +#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e +#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000 +#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f +#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff +#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7 +#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 +#define SQ_LB_CTR_CTRL__START_MASK 0x1 +#define SQ_LB_CTR_CTRL__START__SHIFT 0x0 +#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2 +#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 +#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4 +#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 +#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff +#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0 +#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff +#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0 +#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff +#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0 +#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff +#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0 +#define SQC_SECDED_CNT__INST_SEC_MASK 0xff +#define SQC_SECDED_CNT__INST_SEC__SHIFT 0x0 +#define SQC_SECDED_CNT__INST_DED_MASK 0xff00 +#define SQC_SECDED_CNT__INST_DED__SHIFT 0x8 +#define SQC_SECDED_CNT__DATA_SEC_MASK 0xff0000 +#define SQC_SECDED_CNT__DATA_SEC__SHIFT 0x10 +#define SQC_SECDED_CNT__DATA_DED_MASK 0xff000000 +#define SQC_SECDED_CNT__DATA_DED__SHIFT 0x18 +#define SQ_SEC_CNT__LDS_SEC_MASK 0x3f +#define SQ_SEC_CNT__LDS_SEC__SHIFT 0x0 +#define SQ_SEC_CNT__SGPR_SEC_MASK 0x1f00 +#define SQ_SEC_CNT__SGPR_SEC__SHIFT 0x8 +#define SQ_SEC_CNT__VGPR_SEC_MASK 0x1ff0000 +#define SQ_SEC_CNT__VGPR_SEC__SHIFT 0x10 +#define SQ_DED_CNT__LDS_DED_MASK 0x3f +#define SQ_DED_CNT__LDS_DED__SHIFT 0x0 +#define SQ_DED_CNT__SGPR_DED_MASK 0x1f00 +#define SQ_DED_CNT__SGPR_DED__SHIFT 0x8 +#define SQ_DED_CNT__VGPR_DED_MASK 0x1ff0000 +#define SQ_DED_CNT__VGPR_DED__SHIFT 0x10 +#define SQ_DED_INFO__WAVE_ID_MASK 0xf +#define SQ_DED_INFO__WAVE_ID__SHIFT 0x0 +#define SQ_DED_INFO__SIMD_ID_MASK 0x30 +#define SQ_DED_INFO__SIMD_ID__SHIFT 0x4 +#define SQ_DED_INFO__SOURCE_MASK 0x1c0 +#define SQ_DED_INFO__SOURCE__SHIFT 0x6 +#define SQ_DED_INFO__VM_ID_MASK 0x1e00 +#define SQ_DED_INFO__VM_ID__SHIFT 0x9 +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000 +#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000 +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000 +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7 +#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00 +#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000 +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000 +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf +#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000 +#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13 +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000 +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000 +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 +#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000 +#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18 +#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000 +#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19 +#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000 +#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a +#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000 +#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b +#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000 +#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00 +#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000 +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000 +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000 +#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e +#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff +#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000 +#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe +#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000 +#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000 +#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f +#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7 +#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00 +#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000 +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000 +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 +#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000 +#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000 +#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19 +#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000 +#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000 +#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b +#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000 +#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff +#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000 +#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000 +#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000 +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000 +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD6__UNUNSED_MASK 0xffe00000 +#define SQ_IMG_RSRC_WORD6__UNUNSED__SHIFT 0x15 +#define SQ_IMG_RSRC_WORD7__UNUNSED_MASK 0xffffffff +#define SQ_IMG_RSRC_WORD7__UNUNSED__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7 +#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38 +#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 +#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0 +#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00 +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000 +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000 +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000 +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000 +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000 +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000 +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000 +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000 +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000 +#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff +#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000 +#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc +#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000 +#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000 +#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff +#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000 +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000 +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 +#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000 +#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000 +#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000 +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000 +#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000 +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e +#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff +#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 +#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff +#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 +#define SQ_IND_INDEX__WAVE_ID_MASK 0xf +#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 +#define SQ_IND_INDEX__SIMD_ID_MASK 0x30 +#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 +#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0 +#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 +#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000 +#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc +#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000 +#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd +#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000 +#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe +#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000 +#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf +#define SQ_IND_INDEX__INDEX_MASK 0xffff0000 +#define SQ_IND_INDEX__INDEX__SHIFT 0x10 +#define SQ_CMD__CMD_MASK 0x7 +#define SQ_CMD__CMD__SHIFT 0x0 +#define SQ_CMD__MODE_MASK 0x70 +#define SQ_CMD__MODE__SHIFT 0x4 +#define SQ_CMD__CHECK_VMID_MASK 0x80 +#define SQ_CMD__CHECK_VMID__SHIFT 0x7 +#define SQ_CMD__TRAP_ID_MASK 0x700 +#define SQ_CMD__TRAP_ID__SHIFT 0x8 +#define SQ_CMD__WAVE_ID_MASK 0xf0000 +#define SQ_CMD__WAVE_ID__SHIFT 0x10 +#define SQ_CMD__SIMD_ID_MASK 0x300000 +#define SQ_CMD__SIMD_ID__SHIFT 0x14 +#define SQ_CMD__QUEUE_ID_MASK 0x7000000 +#define SQ_CMD__QUEUE_ID__SHIFT 0x18 +#define SQ_CMD__VM_ID_MASK 0xf0000000 +#define SQ_CMD__VM_ID__SHIFT 0x1c +#define SQ_IND_DATA__DATA_MASK 0xffffffff +#define SQ_IND_DATA__DATA__SHIFT 0x0 +#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff +#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff +#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf +#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0 +#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0 +#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4 +#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff +#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 +#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff +#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 +#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff +#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 +#define SQ_WAVE_PC_HI__PC_HI_MASK 0xff +#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 +#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7 +#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 +#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8 +#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10 +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0 +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 +#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300 +#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 +#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00 +#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa +#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x70000 +#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 +#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0x380000 +#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x13 +#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0xc00000 +#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x16 +#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x1000000 +#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x18 +#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x6000000 +#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x19 +#define SQ_WAVE_IB_DBG0__KILL_MASK 0x8000000 +#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1b +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x10000000 +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1c +#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff +#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 +#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff +#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 +#define SQ_WAVE_STATUS__SCC_MASK 0x1 +#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 +#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6 +#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 +#define SQ_WAVE_STATUS__WAVE_PRIO_MASK 0x18 +#define SQ_WAVE_STATUS__WAVE_PRIO__SHIFT 0x3 +#define SQ_WAVE_STATUS__PRIV_MASK 0x20 +#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 +#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40 +#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 +#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80 +#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 +#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100 +#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 +#define SQ_WAVE_STATUS__EXECZ_MASK 0x200 +#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 +#define SQ_WAVE_STATUS__VCCZ_MASK 0x400 +#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa +#define SQ_WAVE_STATUS__IN_TG_MASK 0x800 +#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb +#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000 +#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc +#define SQ_WAVE_STATUS__HALT_MASK 0x2000 +#define SQ_WAVE_STATUS__HALT__SHIFT 0xd +#define SQ_WAVE_STATUS__TRAP_MASK 0x4000 +#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe +#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000 +#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf +#define SQ_WAVE_STATUS__VALID_MASK 0x10000 +#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 +#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000 +#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 +#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000 +#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 +#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000 +#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 +#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000 +#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14 +#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000 +#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15 +#define SQ_WAVE_STATUS__DATA_ATC_MASK 0x400000 +#define SQ_WAVE_STATUS__DATA_ATC__SHIFT 0x16 +#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000 +#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17 +#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL_MASK 0x7000000 +#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL__SHIFT 0x18 +#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000 +#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b +#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf +#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 +#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0 +#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 +#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100 +#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 +#define SQ_WAVE_MODE__IEEE_MASK 0x200 +#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 +#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400 +#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa +#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800 +#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb +#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000 +#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc +#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000 +#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c +#define SQ_WAVE_MODE__CSP_MASK 0xe0000000 +#define SQ_WAVE_MODE__CSP__SHIFT 0x1d +#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff +#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000 +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 +#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000 +#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d +#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf +#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30 +#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 +#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0 +#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 +#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00 +#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000 +#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc +#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000 +#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd +#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000 +#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000 +#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 +#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000 +#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 +#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000 +#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b +#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000 +#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000 +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000 +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 +#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff +#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc +#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf +#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 +#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70 +#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 +#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00 +#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 +#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000 +#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc +#define SQ_WAVE_M0__M0_MASK 0xffffffff +#define SQ_WAVE_M0__M0__SHIFT 0x0 +#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff +#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff +#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff +#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff +#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1 +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0xf0 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4 +#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1 +#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 +#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff +#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 +#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff +#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 +#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000 +#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 +#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff +#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0 +#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff +#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0 +#define SH_MEM_CONFIG__PTR32_MASK 0x1 +#define SH_MEM_CONFIG__PTR32__SHIFT 0x0 +#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x2 +#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x1 +#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0xc +#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2 +#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0x70 +#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x4 +#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x380 +#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x7 +#define SQC_POLICY__DATA_L1_POLICY_0_MASK 0x1 +#define SQC_POLICY__DATA_L1_POLICY_0__SHIFT 0x0 +#define SQC_POLICY__DATA_L1_POLICY_1_MASK 0x2 +#define SQC_POLICY__DATA_L1_POLICY_1__SHIFT 0x1 +#define SQC_POLICY__DATA_L1_POLICY_2_MASK 0x4 +#define SQC_POLICY__DATA_L1_POLICY_2__SHIFT 0x2 +#define SQC_POLICY__DATA_L1_POLICY_3_MASK 0x8 +#define SQC_POLICY__DATA_L1_POLICY_3__SHIFT 0x3 +#define SQC_POLICY__DATA_L1_POLICY_4_MASK 0x10 +#define SQC_POLICY__DATA_L1_POLICY_4__SHIFT 0x4 +#define SQC_POLICY__DATA_L1_POLICY_5_MASK 0x20 +#define SQC_POLICY__DATA_L1_POLICY_5__SHIFT 0x5 +#define SQC_POLICY__DATA_L1_POLICY_6_MASK 0x40 +#define SQC_POLICY__DATA_L1_POLICY_6__SHIFT 0x6 +#define SQC_POLICY__DATA_L1_POLICY_7_MASK 0x80 +#define SQC_POLICY__DATA_L1_POLICY_7__SHIFT 0x7 +#define SQC_POLICY__DATA_L2_POLICY_0_MASK 0x300 +#define SQC_POLICY__DATA_L2_POLICY_0__SHIFT 0x8 +#define SQC_POLICY__DATA_L2_POLICY_1_MASK 0xc00 +#define SQC_POLICY__DATA_L2_POLICY_1__SHIFT 0xa +#define SQC_POLICY__DATA_L2_POLICY_2_MASK 0x3000 +#define SQC_POLICY__DATA_L2_POLICY_2__SHIFT 0xc +#define SQC_POLICY__DATA_L2_POLICY_3_MASK 0xc000 +#define SQC_POLICY__DATA_L2_POLICY_3__SHIFT 0xe +#define SQC_POLICY__DATA_L2_POLICY_4_MASK 0x30000 +#define SQC_POLICY__DATA_L2_POLICY_4__SHIFT 0x10 +#define SQC_POLICY__DATA_L2_POLICY_5_MASK 0xc0000 +#define SQC_POLICY__DATA_L2_POLICY_5__SHIFT 0x12 +#define SQC_POLICY__DATA_L2_POLICY_6_MASK 0x300000 +#define SQC_POLICY__DATA_L2_POLICY_6__SHIFT 0x14 +#define SQC_POLICY__DATA_L2_POLICY_7_MASK 0xc00000 +#define SQC_POLICY__DATA_L2_POLICY_7__SHIFT 0x16 +#define SQC_POLICY__INST_L2_POLICY_MASK 0x3000000 +#define SQC_POLICY__INST_L2_POLICY__SHIFT 0x18 +#define SQC_VOLATILE__DATA_L1_MASK 0xf +#define SQC_VOLATILE__DATA_L1__SHIFT 0x0 +#define SQC_VOLATILE__DATA_L2_MASK 0xf0 +#define SQC_VOLATILE__DATA_L2__SHIFT 0x4 +#define SQC_VOLATILE__INST_L2_MASK 0x100 +#define SQC_VOLATILE__INST_L2__SHIFT 0x8 +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0 +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600 +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST__SIZE_MASK 0x800 +#define SQ_THREAD_TRACE_WORD_INST__SIZE__SHIFT 0xb +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf000 +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00 +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0 +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000 +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000 +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00 +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0 +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00 +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60 +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 +#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000 +#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000 +#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2 +#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 +#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8 +#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3 +#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10 +#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20 +#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5 +#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40 +#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6 +#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80 +#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7 +#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000 +#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000 +#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff +#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100 +#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200 +#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9 +#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00 +#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa +#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000 +#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe +#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000 +#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12 +#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000 +#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14 +#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000 +#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000 +#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a +#define SQ_SOP2__SSRC0_MASK 0xff +#define SQ_SOP2__SSRC0__SHIFT 0x0 +#define SQ_SOP2__SSRC1_MASK 0xff00 +#define SQ_SOP2__SSRC1__SHIFT 0x8 +#define SQ_SOP2__SDST_MASK 0x7f0000 +#define SQ_SOP2__SDST__SHIFT 0x10 +#define SQ_SOP2__OP_MASK 0x3f800000 +#define SQ_SOP2__OP__SHIFT 0x17 +#define SQ_SOP2__ENCODING_MASK 0xc0000000 +#define SQ_SOP2__ENCODING__SHIFT 0x1e +#define SQ_VOP1__SRC0_MASK 0x1ff +#define SQ_VOP1__SRC0__SHIFT 0x0 +#define SQ_VOP1__OP_MASK 0x1fe00 +#define SQ_VOP1__OP__SHIFT 0x9 +#define SQ_VOP1__VDST_MASK 0x1fe0000 +#define SQ_VOP1__VDST__SHIFT 0x11 +#define SQ_VOP1__ENCODING_MASK 0xfe000000 +#define SQ_VOP1__ENCODING__SHIFT 0x19 +#define SQ_MTBUF_1__VADDR_MASK 0xff +#define SQ_MTBUF_1__VADDR__SHIFT 0x0 +#define SQ_MTBUF_1__VDATA_MASK 0xff00 +#define SQ_MTBUF_1__VDATA__SHIFT 0x8 +#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000 +#define SQ_MTBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MTBUF_1__SLC_MASK 0x400000 +#define SQ_MTBUF_1__SLC__SHIFT 0x16 +#define SQ_MTBUF_1__TFE_MASK 0x800000 +#define SQ_MTBUF_1__TFE__SHIFT 0x17 +#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000 +#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_EXP_1__VSRC0_MASK 0xff +#define SQ_EXP_1__VSRC0__SHIFT 0x0 +#define SQ_EXP_1__VSRC1_MASK 0xff00 +#define SQ_EXP_1__VSRC1__SHIFT 0x8 +#define SQ_EXP_1__VSRC2_MASK 0xff0000 +#define SQ_EXP_1__VSRC2__SHIFT 0x10 +#define SQ_EXP_1__VSRC3_MASK 0xff000000 +#define SQ_EXP_1__VSRC3__SHIFT 0x18 +#define SQ_MUBUF_1__VADDR_MASK 0xff +#define SQ_MUBUF_1__VADDR__SHIFT 0x0 +#define SQ_MUBUF_1__VDATA_MASK 0xff00 +#define SQ_MUBUF_1__VDATA__SHIFT 0x8 +#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000 +#define SQ_MUBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MUBUF_1__SLC_MASK 0x400000 +#define SQ_MUBUF_1__SLC__SHIFT 0x16 +#define SQ_MUBUF_1__TFE_MASK 0x800000 +#define SQ_MUBUF_1__TFE__SHIFT 0x17 +#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000 +#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_INST__ENCODING_MASK 0xffffffff +#define SQ_INST__ENCODING__SHIFT 0x0 +#define SQ_EXP_0__EN_MASK 0xf +#define SQ_EXP_0__EN__SHIFT 0x0 +#define SQ_EXP_0__TGT_MASK 0x3f0 +#define SQ_EXP_0__TGT__SHIFT 0x4 +#define SQ_EXP_0__COMPR_MASK 0x400 +#define SQ_EXP_0__COMPR__SHIFT 0xa +#define SQ_EXP_0__DONE_MASK 0x800 +#define SQ_EXP_0__DONE__SHIFT 0xb +#define SQ_EXP_0__VM_MASK 0x1000 +#define SQ_EXP_0__VM__SHIFT 0xc +#define SQ_EXP_0__ENCODING_MASK 0xfc000000 +#define SQ_EXP_0__ENCODING__SHIFT 0x1a +#define SQ_MUBUF_0__OFFSET_MASK 0xfff +#define SQ_MUBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MUBUF_0__OFFEN_MASK 0x1000 +#define SQ_MUBUF_0__OFFEN__SHIFT 0xc +#define SQ_MUBUF_0__IDXEN_MASK 0x2000 +#define SQ_MUBUF_0__IDXEN__SHIFT 0xd +#define SQ_MUBUF_0__GLC_MASK 0x4000 +#define SQ_MUBUF_0__GLC__SHIFT 0xe +#define SQ_MUBUF_0__ADDR64_MASK 0x8000 +#define SQ_MUBUF_0__ADDR64__SHIFT 0xf +#define SQ_MUBUF_0__LDS_MASK 0x10000 +#define SQ_MUBUF_0__LDS__SHIFT 0x10 +#define SQ_MUBUF_0__OP_MASK 0x1fc0000 +#define SQ_MUBUF_0__OP__SHIFT 0x12 +#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000 +#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a +#define SQ_VOP3_0__VDST_MASK 0xff +#define SQ_VOP3_0__VDST__SHIFT 0x0 +#define SQ_VOP3_0__ABS_MASK 0x700 +#define SQ_VOP3_0__ABS__SHIFT 0x8 +#define SQ_VOP3_0__CLAMP_MASK 0x800 +#define SQ_VOP3_0__CLAMP__SHIFT 0xb +#define SQ_VOP3_0__OP_MASK 0x3fe0000 +#define SQ_VOP3_0__OP__SHIFT 0x11 +#define SQ_VOP3_0__ENCODING_MASK 0xfc000000 +#define SQ_VOP3_0__ENCODING__SHIFT 0x1a +#define SQ_VOP2__SRC0_MASK 0x1ff +#define SQ_VOP2__SRC0__SHIFT 0x0 +#define SQ_VOP2__VSRC1_MASK 0x1fe00 +#define SQ_VOP2__VSRC1__SHIFT 0x9 +#define SQ_VOP2__VDST_MASK 0x1fe0000 +#define SQ_VOP2__VDST__SHIFT 0x11 +#define SQ_VOP2__OP_MASK 0x7e000000 +#define SQ_VOP2__OP__SHIFT 0x19 +#define SQ_VOP2__ENCODING_MASK 0x80000000 +#define SQ_VOP2__ENCODING__SHIFT 0x1f +#define SQ_MTBUF_0__OFFSET_MASK 0xfff +#define SQ_MTBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MTBUF_0__OFFEN_MASK 0x1000 +#define SQ_MTBUF_0__OFFEN__SHIFT 0xc +#define SQ_MTBUF_0__IDXEN_MASK 0x2000 +#define SQ_MTBUF_0__IDXEN__SHIFT 0xd +#define SQ_MTBUF_0__GLC_MASK 0x4000 +#define SQ_MTBUF_0__GLC__SHIFT 0xe +#define SQ_MTBUF_0__ADDR64_MASK 0x8000 +#define SQ_MTBUF_0__ADDR64__SHIFT 0xf +#define SQ_MTBUF_0__OP_MASK 0x70000 +#define SQ_MTBUF_0__OP__SHIFT 0x10 +#define SQ_MTBUF_0__DFMT_MASK 0x780000 +#define SQ_MTBUF_0__DFMT__SHIFT 0x13 +#define SQ_MTBUF_0__NFMT_MASK 0x3800000 +#define SQ_MTBUF_0__NFMT__SHIFT 0x17 +#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000 +#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a +#define SQ_SOPP__SIMM16_MASK 0xffff +#define SQ_SOPP__SIMM16__SHIFT 0x0 +#define SQ_SOPP__OP_MASK 0x7f0000 +#define SQ_SOPP__OP__SHIFT 0x10 +#define SQ_SOPP__ENCODING_MASK 0xff800000 +#define SQ_SOPP__ENCODING__SHIFT 0x17 +#define SQ_FLAT_0__GLC_MASK 0x10000 +#define SQ_FLAT_0__GLC__SHIFT 0x10 +#define SQ_FLAT_0__SLC_MASK 0x20000 +#define SQ_FLAT_0__SLC__SHIFT 0x11 +#define SQ_FLAT_0__OP_MASK 0x1fc0000 +#define SQ_FLAT_0__OP__SHIFT 0x12 +#define SQ_FLAT_0__ENCODING_MASK 0xfc000000 +#define SQ_FLAT_0__ENCODING__SHIFT 0x1a +#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff +#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 +#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00 +#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 +#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3fe0000 +#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x11 +#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000 +#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a +#define SQ_MIMG_1__VADDR_MASK 0xff +#define SQ_MIMG_1__VADDR__SHIFT 0x0 +#define SQ_MIMG_1__VDATA_MASK 0xff00 +#define SQ_MIMG_1__VDATA__SHIFT 0x8 +#define SQ_MIMG_1__SRSRC_MASK 0x1f0000 +#define SQ_MIMG_1__SRSRC__SHIFT 0x10 +#define SQ_MIMG_1__SSAMP_MASK 0x3e00000 +#define SQ_MIMG_1__SSAMP__SHIFT 0x15 +#define SQ_SMRD__OFFSET_MASK 0xff +#define SQ_SMRD__OFFSET__SHIFT 0x0 +#define SQ_SMRD__IMM_MASK 0x100 +#define SQ_SMRD__IMM__SHIFT 0x8 +#define SQ_SMRD__SBASE_MASK 0x7e00 +#define SQ_SMRD__SBASE__SHIFT 0x9 +#define SQ_SMRD__SDST_MASK 0x3f8000 +#define SQ_SMRD__SDST__SHIFT 0xf +#define SQ_SMRD__OP_MASK 0x7c00000 +#define SQ_SMRD__OP__SHIFT 0x16 +#define SQ_SMRD__ENCODING_MASK 0xf8000000 +#define SQ_SMRD__ENCODING__SHIFT 0x1b +#define SQ_SOP1__SSRC0_MASK 0xff +#define SQ_SOP1__SSRC0__SHIFT 0x0 +#define SQ_SOP1__OP_MASK 0xff00 +#define SQ_SOP1__OP__SHIFT 0x8 +#define SQ_SOP1__SDST_MASK 0x7f0000 +#define SQ_SOP1__SDST__SHIFT 0x10 +#define SQ_SOP1__ENCODING_MASK 0xff800000 +#define SQ_SOP1__ENCODING__SHIFT 0x17 +#define SQ_SOPC__SSRC0_MASK 0xff +#define SQ_SOPC__SSRC0__SHIFT 0x0 +#define SQ_SOPC__SSRC1_MASK 0xff00 +#define SQ_SOPC__SSRC1__SHIFT 0x8 +#define SQ_SOPC__OP_MASK 0x7f0000 +#define SQ_SOPC__OP__SHIFT 0x10 +#define SQ_SOPC__ENCODING_MASK 0xff800000 +#define SQ_SOPC__ENCODING__SHIFT 0x17 +#define SQ_FLAT_1__ADDR_MASK 0xff +#define SQ_FLAT_1__ADDR__SHIFT 0x0 +#define SQ_FLAT_1__DATA_MASK 0xff00 +#define SQ_FLAT_1__DATA__SHIFT 0x8 +#define SQ_FLAT_1__TFE_MASK 0x800000 +#define SQ_FLAT_1__TFE__SHIFT 0x17 +#define SQ_FLAT_1__VDST_MASK 0xff000000 +#define SQ_FLAT_1__VDST__SHIFT 0x18 +#define SQ_DS_1__ADDR_MASK 0xff +#define SQ_DS_1__ADDR__SHIFT 0x0 +#define SQ_DS_1__DATA0_MASK 0xff00 +#define SQ_DS_1__DATA0__SHIFT 0x8 +#define SQ_DS_1__DATA1_MASK 0xff0000 +#define SQ_DS_1__DATA1__SHIFT 0x10 +#define SQ_DS_1__VDST_MASK 0xff000000 +#define SQ_DS_1__VDST__SHIFT 0x18 +#define SQ_VOP3_1__SRC0_MASK 0x1ff +#define SQ_VOP3_1__SRC0__SHIFT 0x0 +#define SQ_VOP3_1__SRC1_MASK 0x3fe00 +#define SQ_VOP3_1__SRC1__SHIFT 0x9 +#define SQ_VOP3_1__SRC2_MASK 0x7fc0000 +#define SQ_VOP3_1__SRC2__SHIFT 0x12 +#define SQ_VOP3_1__OMOD_MASK 0x18000000 +#define SQ_VOP3_1__OMOD__SHIFT 0x1b +#define SQ_VOP3_1__NEG_MASK 0xe0000000 +#define SQ_VOP3_1__NEG__SHIFT 0x1d +#define SQ_MIMG_0__DMASK_MASK 0xf00 +#define SQ_MIMG_0__DMASK__SHIFT 0x8 +#define SQ_MIMG_0__UNORM_MASK 0x1000 +#define SQ_MIMG_0__UNORM__SHIFT 0xc +#define SQ_MIMG_0__GLC_MASK 0x2000 +#define SQ_MIMG_0__GLC__SHIFT 0xd +#define SQ_MIMG_0__DA_MASK 0x4000 +#define SQ_MIMG_0__DA__SHIFT 0xe +#define SQ_MIMG_0__R128_MASK 0x8000 +#define SQ_MIMG_0__R128__SHIFT 0xf +#define SQ_MIMG_0__TFE_MASK 0x10000 +#define SQ_MIMG_0__TFE__SHIFT 0x10 +#define SQ_MIMG_0__LWE_MASK 0x20000 +#define SQ_MIMG_0__LWE__SHIFT 0x11 +#define SQ_MIMG_0__OP_MASK 0x1fc0000 +#define SQ_MIMG_0__OP__SHIFT 0x12 +#define SQ_MIMG_0__SLC_MASK 0x2000000 +#define SQ_MIMG_0__SLC__SHIFT 0x19 +#define SQ_MIMG_0__ENCODING_MASK 0xfc000000 +#define SQ_MIMG_0__ENCODING__SHIFT 0x1a +#define SQ_SOPK__SIMM16_MASK 0xffff +#define SQ_SOPK__SIMM16__SHIFT 0x0 +#define SQ_SOPK__SDST_MASK 0x7f0000 +#define SQ_SOPK__SDST__SHIFT 0x10 +#define SQ_SOPK__OP_MASK 0xf800000 +#define SQ_SOPK__OP__SHIFT 0x17 +#define SQ_SOPK__ENCODING_MASK 0xf0000000 +#define SQ_SOPK__ENCODING__SHIFT 0x1c +#define SQ_DS_0__OFFSET0_MASK 0xff +#define SQ_DS_0__OFFSET0__SHIFT 0x0 +#define SQ_DS_0__OFFSET1_MASK 0xff00 +#define SQ_DS_0__OFFSET1__SHIFT 0x8 +#define SQ_DS_0__GDS_MASK 0x20000 +#define SQ_DS_0__GDS__SHIFT 0x11 +#define SQ_DS_0__OP_MASK 0x3fc0000 +#define SQ_DS_0__OP__SHIFT 0x12 +#define SQ_DS_0__ENCODING_MASK 0xfc000000 +#define SQ_DS_0__ENCODING__SHIFT 0x1a +#define SQ_VOPC__SRC0_MASK 0x1ff +#define SQ_VOPC__SRC0__SHIFT 0x0 +#define SQ_VOPC__VSRC1_MASK 0x1fe00 +#define SQ_VOPC__VSRC1__SHIFT 0x9 +#define SQ_VOPC__OP_MASK 0x1fe0000 +#define SQ_VOPC__OP__SHIFT 0x11 +#define SQ_VOPC__ENCODING_MASK 0xfe000000 +#define SQ_VOPC__ENCODING__SHIFT 0x19 +#define SQ_VINTRP__VSRC_MASK 0xff +#define SQ_VINTRP__VSRC__SHIFT 0x0 +#define SQ_VINTRP__ATTRCHAN_MASK 0x300 +#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 +#define SQ_VINTRP__ATTR_MASK 0xfc00 +#define SQ_VINTRP__ATTR__SHIFT 0xa +#define SQ_VINTRP__OP_MASK 0x30000 +#define SQ_VINTRP__OP__SHIFT 0x10 +#define SQ_VINTRP__VDST_MASK 0x3fc0000 +#define SQ_VINTRP__VDST__SHIFT 0x12 +#define SQ_VINTRP__ENCODING_MASK 0xfc000000 +#define SQ_VINTRP__ENCODING__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f +#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1 +#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0 +#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2 +#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4 +#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10 +#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20 +#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80 +#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100 +#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400 +#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800 +#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000 +#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000 +#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000 +#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a +#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000 +#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b +#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000 +#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c +#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000 +#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d +#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000 +#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000 +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f +#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1 +#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2 +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1 +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4 +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2 +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10 +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4 +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20 +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5 +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80 +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7 +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100 +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8 +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400 +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800 +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000 +#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000 +#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12 +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000 +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000 +#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15 +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000 +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000 +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000 +#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000 +#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 +#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80 +#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_CTRL__CACHE_SIZE_MASK 0x3 +#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 +#define TCC_CTRL__RATE_MASK 0xc +#define TCC_CTRL__RATE__SHIFT 0x2 +#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0 +#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 +#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000 +#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc +#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000 +#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 +#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000 +#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14 +#define TCC_EDC_COUNTER__SEC_COUNT_MASK 0xf +#define TCC_EDC_COUNTER__SEC_COUNT__SHIFT 0x0 +#define TCC_EDC_COUNTER__DED_COUNT_MASK 0xf0000 +#define TCC_EDC_COUNTER__DED_COUNT__SHIFT 0x10 +#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1 +#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 +#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2 +#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 +#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf +#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf +#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCS_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf +#define TCS_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf +#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCS_CTRL__RATE_MASK 0x3 +#define TCS_CTRL__RATE__SHIFT 0x0 +#define TCS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define TCS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define TCS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define TCS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define TCS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff +#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff +#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3 +#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 +#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30 +#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 +#define TD_CNTL__PAD_STALL_EN_MASK 0x100 +#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 +#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600 +#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 +#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800 +#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb +#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000 +#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf +#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000 +#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 +#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000 +#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 +#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000 +#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 +#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000 +#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 +#define TD_STATUS__BUSY_MASK 0x80000000 +#define TD_STATUS__BUSY__SHIFT 0x1f +#define TD_DEBUG_INDEX__INDEX_MASK 0x1f +#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0 +#define TD_DEBUG_DATA__DATA_MASK 0xffffffff +#define TD_DEBUG_DATA__DATA__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff +#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_SCRATCH__SCRATCH_MASK 0xffffffff +#define TD_SCRATCH__SCRATCH__SHIFT 0x0 +#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000 +#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd +#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000 +#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 +#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000 +#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1 +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 +#define TA_CNTL_AUX__RESERVED_MASK 0xe +#define TA_CNTL_AUX__RESERVED__SHIFT 0x1 +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000 +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 +#define TA_RESERVED_010C__Unused_MASK 0xffffffff +#define TA_RESERVED_010C__Unused__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff +#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000 +#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc +#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000 +#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd +#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000 +#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe +#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000 +#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 +#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000 +#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 +#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000 +#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 +#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000 +#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 +#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000 +#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 +#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000 +#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 +#define TA_STATUS__IN_BUSY_MASK 0x1000000 +#define TA_STATUS__IN_BUSY__SHIFT 0x18 +#define TA_STATUS__FG_BUSY_MASK 0x2000000 +#define TA_STATUS__FG_BUSY__SHIFT 0x19 +#define TA_STATUS__LA_BUSY_MASK 0x4000000 +#define TA_STATUS__LA_BUSY__SHIFT 0x1a +#define TA_STATUS__FL_BUSY_MASK 0x8000000 +#define TA_STATUS__FL_BUSY__SHIFT 0x1b +#define TA_STATUS__TA_BUSY_MASK 0x10000000 +#define TA_STATUS__TA_BUSY__SHIFT 0x1c +#define TA_STATUS__FA_BUSY_MASK 0x20000000 +#define TA_STATUS__FA_BUSY__SHIFT 0x1d +#define TA_STATUS__AL_BUSY_MASK 0x40000000 +#define TA_STATUS__AL_BUSY__SHIFT 0x1e +#define TA_STATUS__BUSY_MASK 0x80000000 +#define TA_STATUS__BUSY__SHIFT 0x1f +#define TA_DEBUG_INDEX__INDEX_MASK 0x1f +#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0 +#define TA_DEBUG_DATA__DATA_MASK 0xffffffff +#define TA_DEBUG_DATA__DATA__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff +#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_SCRATCH__SCRATCH_MASK 0xffffffff +#define TA_SCRATCH__SCRATCH__SHIFT 0x0 +#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff +#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0 +#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1 +#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0 +#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6 +#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1 +#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18 +#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3 +#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0 +#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5 +#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00 +#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8 +#define TCP_INVALIDATE__START_MASK 0x1 +#define TCP_INVALIDATE__START__SHIFT 0x0 +#define TCP_STATUS__TCP_BUSY_MASK 0x1 +#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 +#define TCP_CNTL__FORCE_HIT_MASK 0x1 +#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 +#define TCP_CNTL__FORCE_MISS_MASK 0x2 +#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 +#define TCP_CNTL__L1_SIZE_MASK 0xc +#define TCP_CNTL__L1_SIZE__SHIFT 0x2 +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10 +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20 +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000 +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000 +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 +#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000 +#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c +#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000 +#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d +#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf +#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 +#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0 +#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 +#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00 +#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 +#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000 +#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc +#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000 +#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 +#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000 +#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 +#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000 +#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 +#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000 +#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c +#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf +#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 +#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0 +#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 +#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00 +#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 +#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000 +#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc +#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000 +#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 +#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000 +#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 +#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000 +#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 +#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000 +#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 +#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30 +#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 +#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0 +#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200 +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 +#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff +#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 +#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000 +#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 +#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000 +#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 +#define TCP_EDC_COUNTER__SEC_COUNT_MASK 0xf +#define TCP_EDC_COUNTER__SEC_COUNT__SHIFT 0x0 +#define TCP_EDC_COUNTER__DED_COUNT_MASK 0xf0000 +#define TCP_EDC_COUNTER__DED_COUNT__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1 +#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2 +#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 +#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4 +#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 +#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8 +#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 +#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10 +#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 +#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20 +#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 +#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40 +#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 +#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80 +#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 +#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100 +#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 +#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200 +#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 +#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400 +#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa +#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800 +#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb +#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000 +#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc +#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000 +#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd +#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000 +#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe +#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000 +#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf +#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000 +#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 +#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000 +#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 +#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000 +#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 +#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000 +#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 +#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000 +#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 +#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000 +#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 +#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000 +#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 +#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000 +#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 +#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 +#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 +#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a +#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b +#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c +#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d +#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e +#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3 +#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc +#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30 +#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300 +#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00 +#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3 +#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc +#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30 +#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0 +#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300 +#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00 +#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e +#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf +#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 +#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf +#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 +#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f +#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf +#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf +#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCI_STATUS__TCI_BUSY_MASK 0x1 +#define TCI_STATUS__TCI_BUSY__SHIFT 0x0 +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 +#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000 +#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 +#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000 +#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 +#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe +#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 +#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6 +#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 +#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18 +#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 +#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60 +#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 +#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180 +#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 +#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1 +#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 +#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4 +#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8 +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10 +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 +#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20 +#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 +#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40 +#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 +#define GDS_ENHANCE2__MISC_MASK 0xffff +#define GDS_ENHANCE2__MISC__SHIFT 0x0 +#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000 +#define GDS_ENHANCE2__UNUSED__SHIFT 0x10 +#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 +#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 +#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4 +#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 +#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38 +#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 +#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0 +#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 +#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00 +#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa +#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000 +#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc +#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 +#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4 +#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 +#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8 +#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 +#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10 +#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 +#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00 +#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 +#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 +#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_SECDED_CNT__DED_MASK 0xffff +#define GDS_SECDED_CNT__DED__SHIFT 0x0 +#define GDS_SECDED_CNT__SEC_MASK 0xffff0000 +#define GDS_SECDED_CNT__SEC__SHIFT 0x10 +#define GDS_GRBM_SECDED_CNT__DED_MASK 0xffff +#define GDS_GRBM_SECDED_CNT__DED__SHIFT 0x0 +#define GDS_GRBM_SECDED_CNT__SEC_MASK 0xffff0000 +#define GDS_GRBM_SECDED_CNT__SEC__SHIFT 0x10 +#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1 +#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 +#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2 +#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 +#define GDS_OA_DED__ME0_CS_DED_MASK 0x4 +#define GDS_OA_DED__ME0_CS_DED__SHIFT 0x2 +#define GDS_OA_DED__UNUSED0_MASK 0x8 +#define GDS_OA_DED__UNUSED0__SHIFT 0x3 +#define GDS_OA_DED__ME1_PIPE0_DED_MASK 0x10 +#define GDS_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 +#define GDS_OA_DED__ME1_PIPE1_DED_MASK 0x20 +#define GDS_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 +#define GDS_OA_DED__ME1_PIPE2_DED_MASK 0x40 +#define GDS_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 +#define GDS_OA_DED__ME1_PIPE3_DED_MASK 0x80 +#define GDS_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 +#define GDS_OA_DED__ME2_PIPE0_DED_MASK 0x100 +#define GDS_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 +#define GDS_OA_DED__ME2_PIPE1_DED_MASK 0x200 +#define GDS_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 +#define GDS_OA_DED__ME2_PIPE2_DED_MASK 0x400 +#define GDS_OA_DED__ME2_PIPE2_DED__SHIFT 0xa +#define GDS_OA_DED__ME2_PIPE3_DED_MASK 0x800 +#define GDS_OA_DED__ME2_PIPE3_DED__SHIFT 0xb +#define GDS_OA_DED__UNUSED1_MASK 0xfffff000 +#define GDS_OA_DED__UNUSED1__SHIFT 0xc +#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f +#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0 +#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0 +#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5 +#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff +#define GDS_DEBUG_DATA__DATA__SHIFT 0x0 +#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff +#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 +#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff +#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 +#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff +#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 +#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff +#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 +#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff +#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 +#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff +#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff +#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff +#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff +#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 +#define GDS_ATOM_CNTL__AINC_MASK 0x3f +#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 +#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0 +#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 +#define GDS_ATOM_CNTL__DMODE_MASK 0x100 +#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 +#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffe00 +#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0x9 +#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1 +#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 +#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe +#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 +#define GDS_ATOM_BASE__BASE_MASK 0xffff +#define GDS_ATOM_BASE__BASE__SHIFT 0x0 +#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000 +#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_SIZE__SIZE_MASK 0xffff +#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 +#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000 +#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff +#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 +#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00 +#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff +#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 +#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00 +#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 +#define GDS_ATOM_DST__DST_MASK 0xffffffff +#define GDS_ATOM_DST__DST__SHIFT 0x0 +#define GDS_ATOM_OP__OP_MASK 0xff +#define GDS_ATOM_OP__OP__SHIFT 0x0 +#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00 +#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 +#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0__DATA_MASK 0xffffffff +#define GDS_ATOM_READ0__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff +#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1__DATA_MASK 0xffffffff +#define GDS_ATOM_READ1__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff +#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f +#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0 +#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 +#define GDS_GWS_RESOURCE__FLAG_MASK 0x1 +#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 +#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe +#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 +#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000 +#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd +#define GDS_GWS_RESOURCE__DED_MASK 0x4000 +#define GDS_GWS_RESOURCE__DED__SHIFT 0xe +#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000 +#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf +#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000 +#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 +#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000 +#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b +#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000 +#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c +#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000 +#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000 +#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 +#define GDS_OA_CNTL__INDEX_MASK 0xf +#define GDS_OA_CNTL__INDEX__SHIFT 0x0 +#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0 +#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 +#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff +#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 +#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff +#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 +#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0xf0000 +#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x10 +#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf00000 +#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x14 +#define GDS_OA_ADDRESS__UNUSED_MASK 0x3f000000 +#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x18 +#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000 +#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e +#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000 +#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f +#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff +#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 +#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000 +#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f +#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff +#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 +#define GDS_DEBUG_REG0__spare1_MASK 0x3f +#define GDS_DEBUG_REG0__spare1__SHIFT 0x0 +#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40 +#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6 +#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80 +#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7 +#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000 +#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc +#define GDS_DEBUG_REG0__cstate_MASK 0x1e000 +#define GDS_DEBUG_REG0__cstate__SHIFT 0xd +#define GDS_DEBUG_REG0__buff_write_MASK 0x20000 +#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11 +#define GDS_DEBUG_REG0__flush_request_MASK 0x40000 +#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12 +#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000 +#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13 +#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000 +#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14 +#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000 +#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15 +#define GDS_DEBUG_REG0__spare_MASK 0xffc00000 +#define GDS_DEBUG_REG0__spare__SHIFT 0x16 +#define GDS_DEBUG_REG1__tag_hit_MASK 0x1 +#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0 +#define GDS_DEBUG_REG1__tag_miss_MASK 0x2 +#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1 +#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc +#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2 +#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000 +#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11 +#define GDS_DEBUG_REG1__data_ready_MASK 0x40000 +#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12 +#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000 +#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13 +#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000 +#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14 +#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000 +#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15 +#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000 +#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16 +#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000 +#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17 +#define GDS_DEBUG_REG1__spare_MASK 0xff000000 +#define GDS_DEBUG_REG1__spare__SHIFT 0x18 +#define GDS_DEBUG_REG2__ds_full_MASK 0x1 +#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0 +#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2 +#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1 +#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4 +#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2 +#define GDS_DEBUG_REG2__cmd_write_MASK 0x8 +#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3 +#define GDS_DEBUG_REG2__app_sel_MASK 0xf0 +#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4 +#define GDS_DEBUG_REG2__req_MASK 0x7fff00 +#define GDS_DEBUG_REG2__req__SHIFT 0x8 +#define GDS_DEBUG_REG2__spare_MASK 0xff800000 +#define GDS_DEBUG_REG2__spare__SHIFT 0x17 +#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff +#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0 +#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800 +#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb +#define GDS_DEBUG_REG3__spare_MASK 0xffff8000 +#define GDS_DEBUG_REG3__spare__SHIFT 0xf +#define GDS_DEBUG_REG4__gws_busy_MASK 0x1 +#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0 +#define GDS_DEBUG_REG4__gws_req_MASK 0x2 +#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1 +#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4 +#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2 +#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8 +#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3 +#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200 +#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9 +#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400 +#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa +#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800 +#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb +#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000 +#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc +#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000 +#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd +#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000 +#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe +#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000 +#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf +#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000 +#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10 +#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000 +#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11 +#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000 +#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12 +#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000 +#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13 +#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000 +#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14 +#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000 +#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15 +#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000 +#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16 +#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000 +#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17 +#define GDS_DEBUG_REG4__spare_MASK 0xff000000 +#define GDS_DEBUG_REG4__spare__SHIFT 0x18 +#define GDS_DEBUG_REG5__write_dis_MASK 0x1 +#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0 +#define GDS_DEBUG_REG5__dec_error_MASK 0x2 +#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1 +#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4 +#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2 +#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8 +#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3 +#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10 +#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4 +#define GDS_DEBUG_REG5__spare_MASK 0xe0 +#define GDS_DEBUG_REG5__spare__SHIFT 0x5 +#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00 +#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8 +#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000 +#define GDS_DEBUG_REG5__spare1__SHIFT 0x16 +#define GDS_DEBUG_REG6__oa_busy_MASK 0x1 +#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0 +#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e +#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1 +#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0 +#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5 +#define GDS_DEBUG_REG6__spare_MASK 0xffe00000 +#define GDS_DEBUG_REG6__spare__SHIFT 0x15 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define GDS_VMID0_BASE__BASE_MASK 0xffff +#define GDS_VMID0_BASE__BASE__SHIFT 0x0 +#define GDS_VMID1_BASE__BASE_MASK 0xffff +#define GDS_VMID1_BASE__BASE__SHIFT 0x0 +#define GDS_VMID2_BASE__BASE_MASK 0xffff +#define GDS_VMID2_BASE__BASE__SHIFT 0x0 +#define GDS_VMID3_BASE__BASE_MASK 0xffff +#define GDS_VMID3_BASE__BASE__SHIFT 0x0 +#define GDS_VMID4_BASE__BASE_MASK 0xffff +#define GDS_VMID4_BASE__BASE__SHIFT 0x0 +#define GDS_VMID5_BASE__BASE_MASK 0xffff +#define GDS_VMID5_BASE__BASE__SHIFT 0x0 +#define GDS_VMID6_BASE__BASE_MASK 0xffff +#define GDS_VMID6_BASE__BASE__SHIFT 0x0 +#define GDS_VMID7_BASE__BASE_MASK 0xffff +#define GDS_VMID7_BASE__BASE__SHIFT 0x0 +#define GDS_VMID8_BASE__BASE_MASK 0xffff +#define GDS_VMID8_BASE__BASE__SHIFT 0x0 +#define GDS_VMID9_BASE__BASE_MASK 0xffff +#define GDS_VMID9_BASE__BASE__SHIFT 0x0 +#define GDS_VMID10_BASE__BASE_MASK 0xffff +#define GDS_VMID10_BASE__BASE__SHIFT 0x0 +#define GDS_VMID11_BASE__BASE_MASK 0xffff +#define GDS_VMID11_BASE__BASE__SHIFT 0x0 +#define GDS_VMID12_BASE__BASE_MASK 0xffff +#define GDS_VMID12_BASE__BASE__SHIFT 0x0 +#define GDS_VMID13_BASE__BASE_MASK 0xffff +#define GDS_VMID13_BASE__BASE__SHIFT 0x0 +#define GDS_VMID14_BASE__BASE_MASK 0xffff +#define GDS_VMID14_BASE__BASE__SHIFT 0x0 +#define GDS_VMID15_BASE__BASE_MASK 0xffff +#define GDS_VMID15_BASE__BASE__SHIFT 0x0 +#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 +#define GDS_GWS_VMID0__BASE_MASK 0x3f +#define GDS_GWS_VMID0__BASE__SHIFT 0x0 +#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID1__BASE_MASK 0x3f +#define GDS_GWS_VMID1__BASE__SHIFT 0x0 +#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID2__BASE_MASK 0x3f +#define GDS_GWS_VMID2__BASE__SHIFT 0x0 +#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID3__BASE_MASK 0x3f +#define GDS_GWS_VMID3__BASE__SHIFT 0x0 +#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID4__BASE_MASK 0x3f +#define GDS_GWS_VMID4__BASE__SHIFT 0x0 +#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID5__BASE_MASK 0x3f +#define GDS_GWS_VMID5__BASE__SHIFT 0x0 +#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID6__BASE_MASK 0x3f +#define GDS_GWS_VMID6__BASE__SHIFT 0x0 +#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID7__BASE_MASK 0x3f +#define GDS_GWS_VMID7__BASE__SHIFT 0x0 +#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID8__BASE_MASK 0x3f +#define GDS_GWS_VMID8__BASE__SHIFT 0x0 +#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID9__BASE_MASK 0x3f +#define GDS_GWS_VMID9__BASE__SHIFT 0x0 +#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID10__BASE_MASK 0x3f +#define GDS_GWS_VMID10__BASE__SHIFT 0x0 +#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID11__BASE_MASK 0x3f +#define GDS_GWS_VMID11__BASE__SHIFT 0x0 +#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID12__BASE_MASK 0x3f +#define GDS_GWS_VMID12__BASE__SHIFT 0x0 +#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID13__BASE_MASK 0x3f +#define GDS_GWS_VMID13__BASE__SHIFT 0x0 +#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID14__BASE_MASK 0x3f +#define GDS_GWS_VMID14__BASE__SHIFT 0x0 +#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID15__BASE_MASK 0x3f +#define GDS_GWS_VMID15__BASE__SHIFT 0x0 +#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 +#define GDS_OA_VMID0__MASK_MASK 0xffff +#define GDS_OA_VMID0__MASK__SHIFT 0x0 +#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID1__MASK_MASK 0xffff +#define GDS_OA_VMID1__MASK__SHIFT 0x0 +#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID2__MASK_MASK 0xffff +#define GDS_OA_VMID2__MASK__SHIFT 0x0 +#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID3__MASK_MASK 0xffff +#define GDS_OA_VMID3__MASK__SHIFT 0x0 +#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID4__MASK_MASK 0xffff +#define GDS_OA_VMID4__MASK__SHIFT 0x0 +#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID5__MASK_MASK 0xffff +#define GDS_OA_VMID5__MASK__SHIFT 0x0 +#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID6__MASK_MASK 0xffff +#define GDS_OA_VMID6__MASK__SHIFT 0x0 +#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID7__MASK_MASK 0xffff +#define GDS_OA_VMID7__MASK__SHIFT 0x0 +#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID8__MASK_MASK 0xffff +#define GDS_OA_VMID8__MASK__SHIFT 0x0 +#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID9__MASK_MASK 0xffff +#define GDS_OA_VMID9__MASK__SHIFT 0x0 +#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID10__MASK_MASK 0xffff +#define GDS_OA_VMID10__MASK__SHIFT 0x0 +#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID11__MASK_MASK 0xffff +#define GDS_OA_VMID11__MASK__SHIFT 0x0 +#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID12__MASK_MASK 0xffff +#define GDS_OA_VMID12__MASK__SHIFT 0x0 +#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID13__MASK_MASK 0xffff +#define GDS_OA_VMID13__MASK__SHIFT 0x0 +#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID14__MASK_MASK 0xffff +#define GDS_OA_VMID14__MASK__SHIFT 0x0 +#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID15__MASK_MASK 0xffff +#define GDS_OA_VMID15__MASK__SHIFT 0x0 +#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 +#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1 +#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 +#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2 +#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 +#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4 +#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 +#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8 +#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 +#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10 +#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 +#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20 +#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 +#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40 +#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 +#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80 +#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 +#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100 +#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 +#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200 +#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 +#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400 +#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa +#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800 +#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb +#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000 +#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc +#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000 +#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd +#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000 +#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe +#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000 +#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf +#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000 +#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 +#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000 +#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 +#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000 +#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 +#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000 +#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 +#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000 +#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 +#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000 +#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 +#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000 +#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 +#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000 +#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 +#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000 +#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 +#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000 +#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 +#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000 +#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a +#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000 +#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b +#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000 +#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c +#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000 +#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d +#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000 +#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e +#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000 +#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f +#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1 +#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 +#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2 +#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 +#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4 +#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 +#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8 +#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 +#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10 +#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 +#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20 +#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 +#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40 +#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 +#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80 +#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 +#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100 +#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 +#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200 +#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 +#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400 +#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa +#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800 +#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb +#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000 +#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc +#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000 +#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd +#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000 +#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe +#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000 +#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf +#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000 +#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 +#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000 +#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 +#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000 +#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 +#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000 +#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 +#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000 +#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 +#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000 +#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 +#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000 +#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 +#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000 +#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 +#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000 +#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 +#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000 +#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 +#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000 +#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a +#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000 +#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b +#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000 +#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c +#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000 +#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d +#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000 +#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e +#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000 +#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f +#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1 +#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 +#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4 +#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 +#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8 +#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3 +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10 +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20 +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40 +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80 +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100 +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200 +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400 +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800 +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb +#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000 +#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc +#define GDS_OA_RESET__RESET_MASK 0x1 +#define GDS_OA_RESET__RESET__SHIFT 0x0 +#define GDS_OA_RESET__PIPE_ID_MASK 0xff00 +#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 +#define GDS_ENHANCE__MISC_MASK 0xffff +#define GDS_ENHANCE__MISC__SHIFT 0x0 +#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000 +#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 +#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000 +#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 +#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000 +#define GDS_ENHANCE__UNUSED__SHIFT 0x12 +#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff +#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 +#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00 +#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 +#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000 +#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc +#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xffff0000 +#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x10 +#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7 +#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7 +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc +#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20 +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 +#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40 +#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000 +#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12 +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000 +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 +#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff +#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3 +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc +#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0xc0 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 +#define VGT_DMA_INDEX_TYPE__ATC_MASK 0x100 +#define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x8 +#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200 +#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 +#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400 +#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define IA_ENHANCE__MISC_MASK 0xffffffff +#define IA_ENHANCE__MISC__SHIFT 0x0 +#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff +#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 +#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff +#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000 +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000 +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define VGT_IMMED_DATA__DATA_MASK 0xffffffff +#define VGT_IMMED_DATA__DATA__SHIFT 0x0 +#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3 +#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff +#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 +#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff +#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 +#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff +#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 +#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1 +#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 +#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1 +#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 +#define VGT_ENHANCE__MISC_MASK 0xffffffff +#define VGT_ENHANCE__MISC__SHIFT 0x0 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 +#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3 +#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000 +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000 +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 +#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf +#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 +#define VGT_GROUP_DECR__DECR_MASK 0xf +#define VGT_GROUP_DECR__DECR__SHIFT 0x0 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2 +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4 +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8 +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00 +#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000 +#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2 +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4 +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8 +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00 +#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000 +#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 +#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x6 +#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x1 +#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 +#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x10 +#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x4 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x6 +#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x1 +#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 +#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x10 +#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x4 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define VGT_GS_MODE__MODE_MASK 0x7 +#define VGT_GS_MODE__MODE__SHIFT 0x0 +#define VGT_GS_MODE__RESERVED_0_MASK 0x8 +#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 +#define VGT_GS_MODE__CUT_MODE_MASK 0x30 +#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 +#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0 +#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 +#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800 +#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb +#define VGT_GS_MODE__RESERVED_2_MASK 0x1000 +#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc +#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000 +#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd +#define VGT_GS_MODE__COMPUTE_MODE_MASK 0x4000 +#define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0xe +#define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x8000 +#define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0xf +#define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x10000 +#define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x10 +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000 +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 +#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000 +#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000 +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000 +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 +#define VGT_GS_MODE__ONCHIP_MASK 0x600000 +#define VGT_GS_MODE__ONCHIP__SHIFT 0x15 +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800 +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000 +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3 +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0 +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 +#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200 +#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800 +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000 +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000 +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd +#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000 +#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 +#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1 +#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 +#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2 +#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 +#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4 +#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 +#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff +#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700 +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800 +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000 +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000 +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 +#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80 +#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00 +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 +#define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0x400000 +#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x16 +#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff +#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 +#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff +#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 +#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf +#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 +#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f +#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 +#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1 +#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 +#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2 +#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4 +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 +#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8 +#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 +#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10 +#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1 +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2 +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4 +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8 +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70 +#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000 +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 +#define IA_VMID_OVERRIDE__ENABLE_MASK 0x1 +#define IA_VMID_OVERRIDE__ENABLE__SHIFT 0x0 +#define IA_VMID_OVERRIDE__VMID_MASK 0x1e +#define IA_VMID_OVERRIDE__VMID__SHIFT 0x1 +#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3 +#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 +#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4 +#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 +#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18 +#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 +#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20 +#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 +#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0 +#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100 +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8 +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff +#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_TF_PARAM__TYPE_MASK 0x3 +#define VGT_TF_PARAM__TYPE__SHIFT 0x0 +#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c +#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 +#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0 +#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100 +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 +#define VGT_TF_PARAM__DEPRECATED_MASK 0x200 +#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00 +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa +#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000 +#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe +#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x18000 +#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf +#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff +#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 +#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1 +#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 +#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff +#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1 +#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc +#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000 +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000 +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000 +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff +#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff +#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff +#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff +#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff +#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 +#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1 +#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2 +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4 +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 +#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8 +#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 +#define WD_ENHANCE__MISC_MASK 0xffffffff +#define WD_ENHANCE__MISC__SHIFT 0x0 +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 +#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000 +#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000 +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 +#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1 +#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0 +#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000 +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 +#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 +#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 +#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 +#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 +#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000 +#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000 +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000 +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0 +#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40 +#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6 +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff +#define VGT_DEBUG_DATA__DATA__SHIFT 0x0 +#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f +#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0 +#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40 +#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6 +#define IA_DEBUG_DATA__DATA_MASK 0xffffffff +#define IA_DEBUG_DATA__DATA__SHIFT 0x0 +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1 +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 +#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10 +#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 +#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40 +#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 +#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80 +#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 +#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100 +#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 +#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200 +#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 +#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f +#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0 +#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40 +#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6 +#define WD_DEBUG_DATA__DATA_MASK 0xffffffff +#define WD_DEBUG_DATA__DATA__SHIFT 0x0 +#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 +#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 +#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1 +#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0 +#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2 +#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1 +#define WD_DEBUG_REG0__wd_busy_MASK 0x4 +#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2 +#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8 +#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3 +#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10 +#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4 +#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20 +#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5 +#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40 +#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6 +#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80 +#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7 +#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100 +#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8 +#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200 +#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9 +#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400 +#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa +#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800 +#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb +#define WD_DEBUG_REG0__SPARE2_MASK 0x1000 +#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc +#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000 +#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd +#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000 +#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe +#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000 +#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf +#define WD_DEBUG_REG0__SPARE3_MASK 0x10000 +#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10 +#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000 +#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11 +#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000 +#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12 +#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000 +#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13 +#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000 +#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14 +#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000 +#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15 +#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000 +#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16 +#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000 +#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17 +#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 +#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 +#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000 +#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19 +#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000 +#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a +#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000 +#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b +#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 +#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c +#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000 +#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d +#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000 +#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e +#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000 +#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f +#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1 +#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0 +#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2 +#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1 +#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4 +#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2 +#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8 +#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3 +#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10 +#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4 +#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20 +#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5 +#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40 +#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6 +#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80 +#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7 +#define WD_DEBUG_REG1__SPARE0_MASK 0x100 +#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8 +#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200 +#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9 +#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400 +#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa +#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800 +#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb +#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000 +#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc +#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000 +#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11 +#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000 +#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14 +#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000 +#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a +#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000 +#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b +#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000 +#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c +#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000 +#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d +#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f +#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1 +#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0 +#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2 +#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1 +#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4 +#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2 +#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8 +#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3 +#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10 +#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4 +#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20 +#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5 +#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40 +#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6 +#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80 +#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7 +#define WD_DEBUG_REG2__SPARE0_MASK 0x100 +#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8 +#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200 +#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9 +#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400 +#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa +#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800 +#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000 +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000 +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11 +#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000 +#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000 +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f +#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1 +#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0 +#define WD_DEBUG_REG3__SPARE0_MASK 0x2 +#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1 +#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4 +#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2 +#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8 +#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3 +#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10 +#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4 +#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20 +#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5 +#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40 +#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6 +#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80 +#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7 +#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300 +#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8 +#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400 +#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa +#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800 +#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb +#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000 +#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc +#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000 +#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd +#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000 +#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe +#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000 +#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf +#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000 +#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10 +#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000 +#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11 +#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000 +#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12 +#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000 +#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13 +#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000 +#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14 +#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000 +#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15 +#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000 +#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16 +#define WD_DEBUG_REG3__SPARE1_MASK 0x800000 +#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17 +#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000 +#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18 +#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000 +#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19 +#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000 +#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a +#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000 +#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b +#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000 +#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c +#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000 +#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d +#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f +#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1 +#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0 +#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2 +#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1 +#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4 +#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2 +#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8 +#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3 +#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10 +#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4 +#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20 +#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5 +#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40 +#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6 +#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80 +#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7 +#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100 +#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8 +#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200 +#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9 +#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400 +#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa +#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800 +#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb +#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000 +#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc +#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000 +#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd +#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000 +#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe +#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000 +#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10 +#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000 +#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13 +#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000 +#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14 +#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000 +#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15 +#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000 +#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16 +#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000 +#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17 +#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000 +#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18 +#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000 +#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19 +#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000 +#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a +#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000 +#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b +#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000 +#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c +#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000 +#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d +#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000 +#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e +#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000 +#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f +#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1 +#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0 +#define WD_DEBUG_REG5__SPARE0_MASK 0x2 +#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1 +#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4 +#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2 +#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8 +#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3 +#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10 +#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4 +#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20 +#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7 +#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300 +#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8 +#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400 +#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa +#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800 +#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb +#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000 +#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc +#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000 +#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd +#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000 +#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe +#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000 +#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf +#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000 +#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10 +#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000 +#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13 +#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000 +#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14 +#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000 +#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15 +#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000 +#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16 +#define WD_DEBUG_REG5__SPARE1_MASK 0x800000 +#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17 +#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000 +#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19 +#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000 +#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a +#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000 +#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b +#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000 +#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c +#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000 +#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f +#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1 +#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0 +#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2 +#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1 +#define IA_DEBUG_REG0__ia_busy_MASK 0x4 +#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2 +#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8 +#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3 +#define IA_DEBUG_REG0__SPARE0_MASK 0x10 +#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4 +#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20 +#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5 +#define IA_DEBUG_REG0__dma_busy_MASK 0x40 +#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6 +#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80 +#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7 +#define IA_DEBUG_REG0__grp_busy_MASK 0x100 +#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8 +#define IA_DEBUG_REG0__SPARE1_MASK 0x200 +#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9 +#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400 +#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa +#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800 +#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb +#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000 +#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc +#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000 +#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd +#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000 +#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe +#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 +#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 +#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000 +#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19 +#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000 +#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a +#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000 +#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b +#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 +#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c +#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 +#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d +#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000 +#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e +#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000 +#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f +#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1 +#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0 +#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2 +#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1 +#define IA_DEBUG_REG1__start_new_packet_MASK 0x4 +#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2 +#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8 +#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3 +#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10 +#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4 +#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60 +#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5 +#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80 +#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7 +#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100 +#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8 +#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200 +#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9 +#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400 +#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa +#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800 +#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb +#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000 +#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc +#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000 +#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd +#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000 +#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe +#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000 +#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf +#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000 +#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10 +#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000 +#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11 +#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000 +#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12 +#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000 +#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13 +#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000 +#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14 +#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000 +#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15 +#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000 +#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16 +#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000 +#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17 +#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000 +#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18 +#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000 +#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19 +#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000 +#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a +#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000 +#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b +#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000 +#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c +#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000 +#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d +#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000 +#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e +#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000 +#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f +#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1 +#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0 +#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2 +#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1 +#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4 +#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2 +#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8 +#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3 +#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10 +#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4 +#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60 +#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5 +#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80 +#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7 +#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100 +#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8 +#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200 +#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9 +#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400 +#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa +#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800 +#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb +#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000 +#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc +#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000 +#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd +#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000 +#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe +#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000 +#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf +#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000 +#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10 +#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000 +#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11 +#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000 +#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12 +#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000 +#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13 +#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000 +#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14 +#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000 +#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15 +#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000 +#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16 +#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000 +#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19 +#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000 +#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a +#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000 +#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b +#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000 +#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c +#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000 +#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d +#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000 +#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e +#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000 +#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f +#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4 +#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20 +#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5 +#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40 +#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6 +#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80 +#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa +#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb +#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc +#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000 +#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd +#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000 +#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe +#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000 +#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf +#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000 +#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10 +#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000 +#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11 +#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000 +#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12 +#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000 +#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13 +#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000 +#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14 +#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000 +#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15 +#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000 +#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16 +#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000 +#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17 +#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000 +#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18 +#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000 +#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a +#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000 +#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b +#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000 +#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c +#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000 +#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d +#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000 +#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e +#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000 +#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f +#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1 +#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0 +#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2 +#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1 +#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4 +#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2 +#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8 +#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3 +#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10 +#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4 +#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20 +#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5 +#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40 +#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6 +#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80 +#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7 +#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100 +#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8 +#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200 +#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9 +#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400 +#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa +#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800 +#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb +#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000 +#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc +#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000 +#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd +#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000 +#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe +#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000 +#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf +#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000 +#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10 +#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000 +#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11 +#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000 +#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14 +#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000 +#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15 +#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000 +#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18 +#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000 +#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19 +#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000 +#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a +#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000 +#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c +#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000 +#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d +#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000 +#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e +#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000 +#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f +#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff +#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0 +#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000 +#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10 +#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000 +#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e +#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000 +#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f +#define IA_DEBUG_REG6__current_shift_q_MASK 0xf +#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0 +#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0 +#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4 +#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00 +#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8 +#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000 +#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd +#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000 +#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe +#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000 +#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf +#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000 +#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10 +#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000 +#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15 +#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000 +#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16 +#define IA_DEBUG_REG6__extract_group_MASK 0x800000 +#define IA_DEBUG_REG6__extract_group__SHIFT 0x17 +#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000 +#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18 +#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf +#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0 +#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0 +#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4 +#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00 +#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8 +#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000 +#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc +#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000 +#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10 +#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000 +#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14 +#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000 +#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17 +#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000 +#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18 +#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000 +#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19 +#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000 +#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a +#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000 +#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b +#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000 +#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c +#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000 +#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d +#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000 +#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e +#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000 +#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f +#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f +#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0 +#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20 +#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5 +#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40 +#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6 +#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80 +#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7 +#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100 +#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8 +#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200 +#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9 +#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400 +#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa +#define IA_DEBUG_REG8__grp_continued_MASK 0x800 +#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb +#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000 +#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc +#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000 +#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf +#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000 +#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15 +#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000 +#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18 +#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000 +#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19 +#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000 +#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a +#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000 +#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b +#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000 +#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c +#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1 +#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0 +#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2 +#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1 +#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4 +#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2 +#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8 +#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3 +#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10 +#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4 +#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20 +#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5 +#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40 +#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6 +#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80 +#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7 +#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100 +#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8 +#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200 +#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9 +#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400 +#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa +#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800 +#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb +#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000 +#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc +#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000 +#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd +#define IA_DEBUG_REG9__SPARE0_MASK 0x4000 +#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe +#define IA_DEBUG_REG9__SPARE1_MASK 0x8000 +#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf +#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000 +#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10 +#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000 +#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11 +#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000 +#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12 +#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000 +#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13 +#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000 +#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14 +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1 +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0 +#define VGT_DEBUG_REG0__SPARE9_MASK 0x2 +#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1 +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4 +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2 +#define VGT_DEBUG_REG0__SPARE8_MASK 0x8 +#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3 +#define VGT_DEBUG_REG0__SPARE7_MASK 0x10 +#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4 +#define VGT_DEBUG_REG0__SPARE6_MASK 0x20 +#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5 +#define VGT_DEBUG_REG0__SPARE5_MASK 0x40 +#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6 +#define VGT_DEBUG_REG0__SPARE4_MASK 0x80 +#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7 +#define VGT_DEBUG_REG0__pi_busy_MASK 0x100 +#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8 +#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200 +#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9 +#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400 +#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa +#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800 +#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb +#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000 +#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc +#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000 +#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd +#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000 +#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe +#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000 +#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf +#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000 +#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10 +#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000 +#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11 +#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000 +#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12 +#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000 +#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13 +#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000 +#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14 +#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000 +#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15 +#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000 +#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16 +#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000 +#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17 +#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 +#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 +#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000 +#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19 +#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000 +#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a +#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000 +#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b +#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000 +#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c +#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 +#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d +#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000 +#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e +#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000 +#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f +#define VGT_DEBUG_REG1__SPARE9_MASK 0x1 +#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0 +#define VGT_DEBUG_REG1__SPARE8_MASK 0x2 +#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1 +#define VGT_DEBUG_REG1__SPARE7_MASK 0x4 +#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2 +#define VGT_DEBUG_REG1__SPARE6_MASK 0x8 +#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3 +#define VGT_DEBUG_REG1__SPARE5_MASK 0x10 +#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4 +#define VGT_DEBUG_REG1__SPARE4_MASK 0x20 +#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5 +#define VGT_DEBUG_REG1__SPARE3_MASK 0x40 +#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6 +#define VGT_DEBUG_REG1__SPARE2_MASK 0x80 +#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7 +#define VGT_DEBUG_REG1__SPARE1_MASK 0x100 +#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8 +#define VGT_DEBUG_REG1__SPARE0_MASK 0x200 +#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9 +#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400 +#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa +#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800 +#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb +#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000 +#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc +#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000 +#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd +#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000 +#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10 +#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000 +#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11 +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12 +#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000 +#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13 +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14 +#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000 +#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15 +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16 +#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000 +#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17 +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18 +#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000 +#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19 +#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000 +#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a +#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000 +#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b +#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000 +#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c +#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000 +#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d +#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000 +#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e +#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000 +#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f +#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1 +#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0 +#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2 +#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1 +#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4 +#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2 +#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8 +#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3 +#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10 +#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20 +#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5 +#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40 +#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6 +#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80 +#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7 +#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100 +#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8 +#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200 +#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9 +#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400 +#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa +#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800 +#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb +#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000 +#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc +#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000 +#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd +#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000 +#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe +#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000 +#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf +#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000 +#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10 +#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000 +#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11 +#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000 +#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12 +#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000 +#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13 +#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000 +#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14 +#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000 +#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15 +#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000 +#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16 +#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000 +#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17 +#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000 +#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18 +#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000 +#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19 +#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000 +#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a +#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000 +#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b +#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000 +#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c +#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000 +#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d +#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff +#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0 +#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000 +#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc +#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000 +#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12 +#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000 +#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a +#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff +#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0 +#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00 +#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8 +#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000 +#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18 +#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000 +#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d +#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000 +#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e +#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000 +#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f +#define VGT_DEBUG_REG5__SPARE4_MASK 0x7 +#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0 +#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8 +#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3 +#define VGT_DEBUG_REG5__SPARE3_MASK 0x700 +#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8 +#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800 +#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb +#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000 +#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10 +#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000 +#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13 +#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000 +#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18 +#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000 +#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b +#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff +#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0 +#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000 +#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10 +#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1 +#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0 +#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2 +#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1 +#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4 +#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2 +#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8 +#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3 +#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10 +#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0 +#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5 +#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000 +#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10 +#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1 +#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2 +#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4 +#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2 +#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8 +#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3 +#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10 +#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4 +#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20 +#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5 +#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40 +#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6 +#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80 +#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7 +#define VGT_DEBUG_REG8__valid_r2_MASK 0x100 +#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8 +#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200 +#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9 +#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400 +#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa +#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800 +#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb +#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000 +#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc +#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000 +#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd +#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000 +#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe +#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000 +#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf +#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000 +#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10 +#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000 +#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11 +#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000 +#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12 +#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000 +#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13 +#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000 +#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14 +#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000 +#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15 +#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000 +#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16 +#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000 +#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17 +#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000 +#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18 +#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000 +#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19 +#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000 +#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a +#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000 +#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b +#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000 +#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c +#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000 +#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d +#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000 +#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e +#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000 +#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f +#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3 +#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0 +#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4 +#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2 +#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8 +#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3 +#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10 +#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4 +#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20 +#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5 +#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40 +#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6 +#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80 +#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7 +#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100 +#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8 +#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200 +#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9 +#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400 +#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa +#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800 +#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb +#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000 +#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12 +#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000 +#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13 +#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000 +#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16 +#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000 +#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17 +#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000 +#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18 +#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000 +#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19 +#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000 +#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a +#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000 +#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c +#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000 +#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d +#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000 +#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e +#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000 +#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f +#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f +#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0 +#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20 +#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5 +#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40 +#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6 +#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180 +#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7 +#define VGT_DEBUG_REG10__SPARE2_MASK 0x600 +#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9 +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800 +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000 +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc +#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000 +#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd +#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000 +#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17 +#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1 +#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2 +#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4 +#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3 +#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10 +#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4 +#define VGT_DEBUG_REG11__SPARE1_MASK 0x20 +#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5 +#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40 +#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6 +#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80 +#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7 +#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100 +#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8 +#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200 +#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9 +#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400 +#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa +#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800 +#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb +#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000 +#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc +#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000 +#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd +#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000 +#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe +#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000 +#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf +#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000 +#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10 +#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000 +#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11 +#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000 +#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12 +#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000 +#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13 +#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000 +#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14 +#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000 +#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15 +#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000 +#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16 +#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000 +#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17 +#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000 +#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18 +#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000 +#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19 +#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000 +#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b +#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000 +#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c +#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000 +#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d +#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000 +#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e +#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000 +#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f +#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7 +#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0 +#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38 +#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3 +#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0 +#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6 +#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00 +#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9 +#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000 +#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc +#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000 +#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf +#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000 +#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12 +#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000 +#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15 +#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000 +#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18 +#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000 +#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b +#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000 +#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e +#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000 +#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f +#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7 +#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0 +#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38 +#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3 +#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0 +#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6 +#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00 +#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9 +#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000 +#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc +#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000 +#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf +#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000 +#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12 +#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000 +#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16 +#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000 +#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17 +#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000 +#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18 +#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000 +#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19 +#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000 +#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a +#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000 +#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b +#define VGT_DEBUG_REG14__SPARE3_MASK 0xf +#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0 +#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10 +#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4 +#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20 +#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5 +#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40 +#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6 +#define VGT_DEBUG_REG14__SPARE8_MASK 0x180 +#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7 +#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200 +#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9 +#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400 +#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa +#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800 +#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb +#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000 +#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc +#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000 +#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15 +#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000 +#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16 +#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000 +#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19 +#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000 +#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a +#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000 +#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b +#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000 +#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c +#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000 +#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d +#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000 +#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e +#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000 +#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f +#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1 +#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2 +#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4 +#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2 +#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8 +#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3 +#define VGT_DEBUG_REG15__counters_full_MASK 0x10 +#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4 +#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0 +#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5 +#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00 +#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa +#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000 +#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf +#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000 +#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14 +#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000 +#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a +#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000 +#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c +#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000 +#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d +#define VGT_DEBUG_REG16__gog_busy_MASK 0x1 +#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0 +#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe +#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1 +#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10 +#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20 +#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40 +#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6 +#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80 +#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7 +#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100 +#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8 +#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200 +#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9 +#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400 +#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa +#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800 +#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb +#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000 +#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc +#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000 +#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd +#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000 +#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe +#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000 +#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf +#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000 +#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10 +#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000 +#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11 +#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000 +#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12 +#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000 +#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13 +#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000 +#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14 +#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000 +#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15 +#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000 +#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16 +#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000 +#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17 +#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000 +#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18 +#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000 +#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19 +#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000 +#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c +#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000 +#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d +#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000 +#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e +#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000 +#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc +#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000 +#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12 +#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1 +#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0 +#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2 +#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1 +#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4 +#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2 +#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8 +#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3 +#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10 +#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20 +#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40 +#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6 +#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80 +#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7 +#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700 +#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8 +#define VGT_DEBUG_REG18__valid_indices_MASK 0x800 +#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb +#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000 +#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc +#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000 +#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd +#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000 +#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe +#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000 +#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf +#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000 +#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10 +#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000 +#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11 +#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000 +#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12 +#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000 +#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13 +#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000 +#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14 +#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000 +#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15 +#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000 +#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16 +#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000 +#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17 +#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000 +#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18 +#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000 +#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b +#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000 +#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c +#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000 +#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d +#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1 +#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2 +#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4 +#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2 +#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8 +#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3 +#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10 +#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4 +#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20 +#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5 +#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40 +#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6 +#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80 +#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7 +#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100 +#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8 +#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200 +#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9 +#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400 +#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa +#define VGT_DEBUG_REG19__hold_prim_MASK 0x800 +#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb +#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000 +#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc +#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000 +#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd +#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000 +#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe +#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000 +#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf +#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000 +#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10 +#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000 +#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11 +#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000 +#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12 +#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000 +#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13 +#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000 +#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14 +#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000 +#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a +#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000 +#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b +#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000 +#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c +#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000 +#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e +#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000 +#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0 +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000 +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10 +#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000 +#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11 +#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000 +#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12 +#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000 +#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16 +#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000 +#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d +#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000 +#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e +#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000 +#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f +#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1 +#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0 +#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2 +#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1 +#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4 +#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2 +#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8 +#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3 +#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10 +#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4 +#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20 +#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5 +#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40 +#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6 +#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80 +#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7 +#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100 +#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8 +#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200 +#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9 +#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400 +#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa +#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800 +#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb +#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000 +#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc +#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000 +#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd +#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000 +#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe +#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000 +#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf +#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000 +#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10 +#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000 +#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000 +#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14 +#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000 +#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15 +#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000 +#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16 +#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000 +#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17 +#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000 +#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18 +#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000 +#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19 +#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000 +#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a +#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000 +#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b +#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000 +#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c +#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000 +#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e +#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000 +#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f +#define VGT_DEBUG_REG22__cm_state16_MASK 0x3 +#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0 +#define VGT_DEBUG_REG22__cm_state17_MASK 0xc +#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2 +#define VGT_DEBUG_REG22__cm_state18_MASK 0x30 +#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4 +#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0 +#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6 +#define VGT_DEBUG_REG22__cm_state20_MASK 0x300 +#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8 +#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00 +#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa +#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000 +#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc +#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000 +#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe +#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000 +#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10 +#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000 +#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12 +#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000 +#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14 +#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000 +#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16 +#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000 +#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18 +#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000 +#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a +#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000 +#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c +#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000 +#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e +#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1 +#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0 +#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2 +#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1 +#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4 +#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2 +#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8 +#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3 +#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10 +#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20 +#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40 +#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6 +#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80 +#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7 +#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100 +#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8 +#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200 +#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9 +#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400 +#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa +#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800 +#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb +#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000 +#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc +#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000 +#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd +#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000 +#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe +#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000 +#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf +#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000 +#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11 +#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000 +#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15 +#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000 +#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18 +#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff +#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0 +#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000 +#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18 +#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000 +#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a +#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff +#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0 +#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000 +#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a +#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000 +#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e +#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000 +#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f +#define VGT_DEBUG_REG26__cm_state0_MASK 0x3 +#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0 +#define VGT_DEBUG_REG26__cm_state1_MASK 0xc +#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2 +#define VGT_DEBUG_REG26__cm_state2_MASK 0x30 +#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4 +#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0 +#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6 +#define VGT_DEBUG_REG26__cm_state4_MASK 0x300 +#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8 +#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00 +#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa +#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000 +#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc +#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000 +#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe +#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000 +#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10 +#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000 +#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12 +#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000 +#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14 +#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000 +#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16 +#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000 +#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18 +#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000 +#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a +#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000 +#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c +#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000 +#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e +#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1 +#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0 +#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2 +#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1 +#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4 +#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2 +#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8 +#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3 +#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10 +#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20 +#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40 +#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6 +#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80 +#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7 +#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300 +#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8 +#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400 +#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa +#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800 +#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb +#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000 +#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc +#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000 +#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10 +#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000 +#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12 +#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000 +#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13 +#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000 +#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14 +#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000 +#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f +#define VGT_DEBUG_REG28__con_state_q_MASK 0xf +#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0 +#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10 +#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4 +#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20 +#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5 +#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40 +#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80 +#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100 +#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8 +#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200 +#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9 +#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400 +#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa +#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800 +#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb +#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000 +#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc +#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000 +#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd +#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000 +#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10 +#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000 +#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12 +#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000 +#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13 +#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000 +#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14 +#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000 +#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 +#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000 +#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16 +#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000 +#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17 +#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000 +#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c +#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000 +#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e +#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000 +#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f +#define VGT_DEBUG_REG29__con_state_q_MASK 0xf +#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0 +#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10 +#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4 +#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20 +#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5 +#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40 +#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80 +#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100 +#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8 +#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200 +#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9 +#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400 +#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa +#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800 +#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb +#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000 +#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc +#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000 +#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd +#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000 +#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10 +#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000 +#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12 +#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000 +#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13 +#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000 +#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14 +#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000 +#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 +#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000 +#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16 +#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000 +#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17 +#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000 +#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c +#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000 +#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e +#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000 +#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f +#define VGT_DEBUG_REG30__pipe0_dr_MASK 0x1 +#define VGT_DEBUG_REG30__pipe0_dr__SHIFT 0x0 +#define VGT_DEBUG_REG30__pipe0_tf_dr_MASK 0x2 +#define VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT 0x1 +#define VGT_DEBUG_REG30__pipe2_dr_MASK 0x4 +#define VGT_DEBUG_REG30__pipe2_dr__SHIFT 0x2 +#define VGT_DEBUG_REG30__event_or_null_p0_q_MASK 0x8 +#define VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT 0x3 +#define VGT_DEBUG_REG30__pipe0_rtr_MASK 0x10 +#define VGT_DEBUG_REG30__pipe0_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG30__pipe1_rtr_MASK 0x20 +#define VGT_DEBUG_REG30__pipe1_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG30__pipe1_tf_rtr_MASK 0x40 +#define VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT 0x6 +#define VGT_DEBUG_REG30__pipe2_rtr_MASK 0x80 +#define VGT_DEBUG_REG30__pipe2_rtr__SHIFT 0x7 +#define VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK 0x100 +#define VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT 0x8 +#define VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK 0x200 +#define VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT 0x9 +#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK 0x400 +#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT 0xa +#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK 0x800 +#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT 0xb +#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK 0x1000 +#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT 0xc +#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK 0x2000 +#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT 0xd +#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK 0x4000 +#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT 0xe +#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK 0x8000 +#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT 0xf +#define VGT_DEBUG_REG30__tf_fetch_state_q_MASK 0x70000 +#define VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT 0x10 +#define VGT_DEBUG_REG30__last_tf_of_tg_MASK 0x80000 +#define VGT_DEBUG_REG30__last_tf_of_tg__SHIFT 0x13 +#define VGT_DEBUG_REG30__tf_pointer_p0_q_MASK 0xf00000 +#define VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT 0x14 +#define VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK 0x1000000 +#define VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK 0x2000000 +#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT 0x19 +#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK 0x4000000 +#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT 0x1a +#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK 0x8000000 +#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT 0x1b +#define VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK 0x30000000 +#define VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT 0x1c +#define VGT_DEBUG_REG30__pipe4_dr_MASK 0x40000000 +#define VGT_DEBUG_REG30__pipe4_dr__SHIFT 0x1e +#define VGT_DEBUG_REG30__pipe4_rtr_MASK 0x80000000 +#define VGT_DEBUG_REG30__pipe4_rtr__SHIFT 0x1f +#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1 +#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0 +#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2 +#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1 +#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4 +#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2 +#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8 +#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3 +#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10 +#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4 +#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20 +#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5 +#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40 +#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6 +#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80 +#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7 +#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100 +#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8 +#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200 +#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9 +#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400 +#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa +#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800 +#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb +#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000 +#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc +#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000 +#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd +#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000 +#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe +#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000 +#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf +#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000 +#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10 +#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000 +#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11 +#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000 +#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12 +#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000 +#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13 +#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000 +#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14 +#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000 +#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15 +#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000 +#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16 +#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000 +#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17 +#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000 +#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18 +#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000 +#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19 +#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000 +#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a +#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000 +#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b +#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000 +#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c +#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000 +#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d +#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000 +#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e +#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000 +#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f +#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1 +#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0 +#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2 +#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1 +#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4 +#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2 +#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8 +#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3 +#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10 +#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4 +#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20 +#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5 +#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40 +#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80 +#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100 +#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8 +#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200 +#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9 +#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400 +#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa +#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800 +#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb +#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000 +#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc +#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000 +#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe +#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000 +#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf +#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000 +#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10 +#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000 +#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11 +#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000 +#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12 +#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000 +#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13 +#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000 +#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14 +#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000 +#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15 +#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000 +#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16 +#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000 +#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17 +#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000 +#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18 +#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000 +#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c +#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1 +#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0 +#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2 +#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1 +#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4 +#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2 +#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8 +#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3 +#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10 +#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20 +#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5 +#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40 +#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6 +#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80 +#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7 +#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100 +#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8 +#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200 +#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9 +#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400 +#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa +#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800 +#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb +#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000 +#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc +#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000 +#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd +#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000 +#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe +#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000 +#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf +#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000 +#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10 +#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000 +#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11 +#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000 +#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12 +#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000 +#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13 +#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000 +#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14 +#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000 +#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15 +#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000 +#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16 +#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000 +#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17 +#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000 +#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000 +#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a +#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000 +#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c +#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000 +#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d +#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000 +#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e +#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000 +#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f +#define VGT_DEBUG_REG34__con_state_q_MASK 0xf +#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0 +#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10 +#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4 +#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20 +#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5 +#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40 +#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80 +#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100 +#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8 +#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200 +#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9 +#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400 +#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa +#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800 +#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb +#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000 +#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc +#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000 +#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd +#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000 +#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10 +#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000 +#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12 +#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000 +#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13 +#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000 +#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14 +#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000 +#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 +#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000 +#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16 +#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000 +#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17 +#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000 +#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c +#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000 +#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e +#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000 +#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f +#define VGT_DEBUG_REG35__pipe0_dr_MASK 0x1 +#define VGT_DEBUG_REG35__pipe0_dr__SHIFT 0x0 +#define VGT_DEBUG_REG35__pipe1_dr_MASK 0x2 +#define VGT_DEBUG_REG35__pipe1_dr__SHIFT 0x1 +#define VGT_DEBUG_REG35__pipe0_rtr_MASK 0x4 +#define VGT_DEBUG_REG35__pipe0_rtr__SHIFT 0x2 +#define VGT_DEBUG_REG35__pipe1_rtr_MASK 0x8 +#define VGT_DEBUG_REG35__pipe1_rtr__SHIFT 0x3 +#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK 0x10 +#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT 0x4 +#define VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK 0x20 +#define VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT 0x5 +#define VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK 0x40 +#define VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT 0x6 +#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK 0x80 +#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT 0x7 +#define VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK 0x100 +#define VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT 0x8 +#define VGT_DEBUG_REG35__tf_skid_fifo_full_MASK 0x200 +#define VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT 0x9 +#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK 0x400 +#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT 0xa +#define VGT_DEBUG_REG35__last_req_of_tg_p2_MASK 0x800 +#define VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT 0xb +#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK 0x3f000 +#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT 0xc +#define VGT_DEBUG_REG35__event_flag_p1_q_MASK 0x40000 +#define VGT_DEBUG_REG35__event_flag_p1_q__SHIFT 0x12 +#define VGT_DEBUG_REG35__null_flag_p1_q_MASK 0x80000 +#define VGT_DEBUG_REG35__null_flag_p1_q__SHIFT 0x13 +#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK 0x7f00000 +#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT 0x14 +#define VGT_DEBUG_REG35__second_tf_ret_data_q_MASK 0x8000000 +#define VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT 0x1b +#define VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK 0x10000000 +#define VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT 0x1c +#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK 0x20000000 +#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT 0x1d +#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK 0x40000000 +#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT 0x1e +#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK 0x80000000 +#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT 0x1f +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff +#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff +#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff +#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 +#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff +#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 +#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 + +#endif /* GFX_7_2_SH_MASK_H */ -- cgit v1.2.3 From 675892a184ee337471077e762a26f878f21535ae Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:21:21 -0400 Subject: drm/amdgpu: add GCA 8.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the GCA (Graphics and Compute Array) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h | 2811 +++ .../drm/amd/include/asic_reg/gca/gfx_8_0_enum.h | 6858 ++++++ .../drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h | 20776 +++++++++++++++++++ 3 files changed, 30445 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h new file mode 100644 index 000000000000..daf763ba1a8f --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h @@ -0,0 +1,2811 @@ +/* + * GFX_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_8_0_D_H +#define GFX_8_0_D_H + +#define mmCB_BLEND_RED 0xa105 +#define mmCB_BLEND_GREEN 0xa106 +#define mmCB_BLEND_BLUE 0xa107 +#define mmCB_BLEND_ALPHA 0xa108 +#define mmCB_DCC_CONTROL 0xa109 +#define mmCB_COLOR_CONTROL 0xa202 +#define mmCB_BLEND0_CONTROL 0xa1e0 +#define mmCB_BLEND1_CONTROL 0xa1e1 +#define mmCB_BLEND2_CONTROL 0xa1e2 +#define mmCB_BLEND3_CONTROL 0xa1e3 +#define mmCB_BLEND4_CONTROL 0xa1e4 +#define mmCB_BLEND5_CONTROL 0xa1e5 +#define mmCB_BLEND6_CONTROL 0xa1e6 +#define mmCB_BLEND7_CONTROL 0xa1e7 +#define mmCB_COLOR0_BASE 0xa318 +#define mmCB_COLOR1_BASE 0xa327 +#define mmCB_COLOR2_BASE 0xa336 +#define mmCB_COLOR3_BASE 0xa345 +#define mmCB_COLOR4_BASE 0xa354 +#define mmCB_COLOR5_BASE 0xa363 +#define mmCB_COLOR6_BASE 0xa372 +#define mmCB_COLOR7_BASE 0xa381 +#define mmCB_COLOR0_PITCH 0xa319 +#define mmCB_COLOR1_PITCH 0xa328 +#define mmCB_COLOR2_PITCH 0xa337 +#define mmCB_COLOR3_PITCH 0xa346 +#define mmCB_COLOR4_PITCH 0xa355 +#define mmCB_COLOR5_PITCH 0xa364 +#define mmCB_COLOR6_PITCH 0xa373 +#define mmCB_COLOR7_PITCH 0xa382 +#define mmCB_COLOR0_SLICE 0xa31a +#define mmCB_COLOR1_SLICE 0xa329 +#define mmCB_COLOR2_SLICE 0xa338 +#define mmCB_COLOR3_SLICE 0xa347 +#define mmCB_COLOR4_SLICE 0xa356 +#define mmCB_COLOR5_SLICE 0xa365 +#define mmCB_COLOR6_SLICE 0xa374 +#define mmCB_COLOR7_SLICE 0xa383 +#define mmCB_COLOR0_VIEW 0xa31b +#define mmCB_COLOR1_VIEW 0xa32a +#define mmCB_COLOR2_VIEW 0xa339 +#define mmCB_COLOR3_VIEW 0xa348 +#define mmCB_COLOR4_VIEW 0xa357 +#define mmCB_COLOR5_VIEW 0xa366 +#define mmCB_COLOR6_VIEW 0xa375 +#define mmCB_COLOR7_VIEW 0xa384 +#define mmCB_COLOR0_INFO 0xa31c +#define mmCB_COLOR1_INFO 0xa32b +#define mmCB_COLOR2_INFO 0xa33a +#define mmCB_COLOR3_INFO 0xa349 +#define mmCB_COLOR4_INFO 0xa358 +#define mmCB_COLOR5_INFO 0xa367 +#define mmCB_COLOR6_INFO 0xa376 +#define mmCB_COLOR7_INFO 0xa385 +#define mmCB_COLOR0_ATTRIB 0xa31d +#define mmCB_COLOR1_ATTRIB 0xa32c +#define mmCB_COLOR2_ATTRIB 0xa33b +#define mmCB_COLOR3_ATTRIB 0xa34a +#define mmCB_COLOR4_ATTRIB 0xa359 +#define mmCB_COLOR5_ATTRIB 0xa368 +#define mmCB_COLOR6_ATTRIB 0xa377 +#define mmCB_COLOR7_ATTRIB 0xa386 +#define mmCB_COLOR0_DCC_CONTROL 0xa31e +#define mmCB_COLOR1_DCC_CONTROL 0xa32d +#define mmCB_COLOR2_DCC_CONTROL 0xa33c +#define mmCB_COLOR3_DCC_CONTROL 0xa34b +#define mmCB_COLOR4_DCC_CONTROL 0xa35a +#define mmCB_COLOR5_DCC_CONTROL 0xa369 +#define mmCB_COLOR6_DCC_CONTROL 0xa378 +#define mmCB_COLOR7_DCC_CONTROL 0xa387 +#define mmCB_COLOR0_CMASK 0xa31f +#define mmCB_COLOR1_CMASK 0xa32e +#define mmCB_COLOR2_CMASK 0xa33d +#define mmCB_COLOR3_CMASK 0xa34c +#define mmCB_COLOR4_CMASK 0xa35b +#define mmCB_COLOR5_CMASK 0xa36a +#define mmCB_COLOR6_CMASK 0xa379 +#define mmCB_COLOR7_CMASK 0xa388 +#define mmCB_COLOR0_CMASK_SLICE 0xa320 +#define mmCB_COLOR1_CMASK_SLICE 0xa32f +#define mmCB_COLOR2_CMASK_SLICE 0xa33e +#define mmCB_COLOR3_CMASK_SLICE 0xa34d +#define mmCB_COLOR4_CMASK_SLICE 0xa35c +#define mmCB_COLOR5_CMASK_SLICE 0xa36b +#define mmCB_COLOR6_CMASK_SLICE 0xa37a +#define mmCB_COLOR7_CMASK_SLICE 0xa389 +#define mmCB_COLOR0_FMASK 0xa321 +#define mmCB_COLOR1_FMASK 0xa330 +#define mmCB_COLOR2_FMASK 0xa33f +#define mmCB_COLOR3_FMASK 0xa34e +#define mmCB_COLOR4_FMASK 0xa35d +#define mmCB_COLOR5_FMASK 0xa36c +#define mmCB_COLOR6_FMASK 0xa37b +#define mmCB_COLOR7_FMASK 0xa38a +#define mmCB_COLOR0_FMASK_SLICE 0xa322 +#define mmCB_COLOR1_FMASK_SLICE 0xa331 +#define mmCB_COLOR2_FMASK_SLICE 0xa340 +#define mmCB_COLOR3_FMASK_SLICE 0xa34f +#define mmCB_COLOR4_FMASK_SLICE 0xa35e +#define mmCB_COLOR5_FMASK_SLICE 0xa36d +#define mmCB_COLOR6_FMASK_SLICE 0xa37c +#define mmCB_COLOR7_FMASK_SLICE 0xa38b +#define mmCB_COLOR0_CLEAR_WORD0 0xa323 +#define mmCB_COLOR1_CLEAR_WORD0 0xa332 +#define mmCB_COLOR2_CLEAR_WORD0 0xa341 +#define mmCB_COLOR3_CLEAR_WORD0 0xa350 +#define mmCB_COLOR4_CLEAR_WORD0 0xa35f +#define mmCB_COLOR5_CLEAR_WORD0 0xa36e +#define mmCB_COLOR6_CLEAR_WORD0 0xa37d +#define mmCB_COLOR7_CLEAR_WORD0 0xa38c +#define mmCB_COLOR0_CLEAR_WORD1 0xa324 +#define mmCB_COLOR1_CLEAR_WORD1 0xa333 +#define mmCB_COLOR2_CLEAR_WORD1 0xa342 +#define mmCB_COLOR3_CLEAR_WORD1 0xa351 +#define mmCB_COLOR4_CLEAR_WORD1 0xa360 +#define mmCB_COLOR5_CLEAR_WORD1 0xa36f +#define mmCB_COLOR6_CLEAR_WORD1 0xa37e +#define mmCB_COLOR7_CLEAR_WORD1 0xa38d +#define mmCB_COLOR0_DCC_BASE 0xa325 +#define mmCB_COLOR1_DCC_BASE 0xa334 +#define mmCB_COLOR2_DCC_BASE 0xa343 +#define mmCB_COLOR3_DCC_BASE 0xa352 +#define mmCB_COLOR4_DCC_BASE 0xa361 +#define mmCB_COLOR5_DCC_BASE 0xa370 +#define mmCB_COLOR6_DCC_BASE 0xa37f +#define mmCB_COLOR7_DCC_BASE 0xa38e +#define mmCB_TARGET_MASK 0xa08e +#define mmCB_SHADER_MASK 0xa08f +#define mmCB_HW_CONTROL 0x2684 +#define mmCB_HW_CONTROL_1 0x2685 +#define mmCB_HW_CONTROL_2 0x2686 +#define mmCB_HW_CONTROL_3 0x2683 +#define mmCB_DCC_CONFIG 0x2687 +#define mmCB_PERFCOUNTER_FILTER 0xdc00 +#define mmCB_PERFCOUNTER0_SELECT 0xdc01 +#define mmCB_PERFCOUNTER0_SELECT1 0xdc02 +#define mmCB_PERFCOUNTER1_SELECT 0xdc03 +#define mmCB_PERFCOUNTER2_SELECT 0xdc04 +#define mmCB_PERFCOUNTER3_SELECT 0xdc05 +#define mmCB_PERFCOUNTER0_LO 0xd406 +#define mmCB_PERFCOUNTER1_LO 0xd408 +#define mmCB_PERFCOUNTER2_LO 0xd40a +#define mmCB_PERFCOUNTER3_LO 0xd40c +#define mmCB_PERFCOUNTER0_HI 0xd407 +#define mmCB_PERFCOUNTER1_HI 0xd409 +#define mmCB_PERFCOUNTER2_HI 0xd40b +#define mmCB_PERFCOUNTER3_HI 0xd40d +#define mmCB_CGTT_SCLK_CTRL 0xf0a8 +#define mmCB_DEBUG_BUS_1 0x2699 +#define mmCB_DEBUG_BUS_2 0x269a +#define mmCB_DEBUG_BUS_3 0x269b +#define mmCB_DEBUG_BUS_4 0x269c +#define mmCB_DEBUG_BUS_5 0x269d +#define mmCB_DEBUG_BUS_6 0x269e +#define mmCB_DEBUG_BUS_7 0x269f +#define mmCB_DEBUG_BUS_8 0x26a0 +#define mmCB_DEBUG_BUS_9 0x26a1 +#define mmCB_DEBUG_BUS_10 0x26a2 +#define mmCB_DEBUG_BUS_11 0x26a3 +#define mmCB_DEBUG_BUS_12 0x26a4 +#define mmCB_DEBUG_BUS_13 0x26a5 +#define mmCB_DEBUG_BUS_14 0x26a6 +#define mmCB_DEBUG_BUS_15 0x26a7 +#define mmCB_DEBUG_BUS_16 0x26a8 +#define mmCB_DEBUG_BUS_17 0x26a9 +#define mmCB_DEBUG_BUS_18 0x26aa +#define mmCB_DEBUG_BUS_19 0x26ab +#define mmCB_DEBUG_BUS_20 0x26ac +#define mmCB_DEBUG_BUS_21 0x26ad +#define mmCB_DEBUG_BUS_22 0x26ae +#define mmCP_DFY_CNTL 0x3020 +#define mmCP_DFY_STAT 0x3021 +#define mmCP_DFY_ADDR_HI 0x3022 +#define mmCP_DFY_ADDR_LO 0x3023 +#define mmCP_DFY_DATA_0 0x3024 +#define mmCP_DFY_DATA_1 0x3025 +#define mmCP_DFY_DATA_2 0x3026 +#define mmCP_DFY_DATA_3 0x3027 +#define mmCP_DFY_DATA_4 0x3028 +#define mmCP_DFY_DATA_5 0x3029 +#define mmCP_DFY_DATA_6 0x302a +#define mmCP_DFY_DATA_7 0x302b +#define mmCP_DFY_DATA_8 0x302c +#define mmCP_DFY_DATA_9 0x302d +#define mmCP_DFY_DATA_10 0x302e +#define mmCP_DFY_DATA_11 0x302f +#define mmCP_DFY_DATA_12 0x3030 +#define mmCP_DFY_DATA_13 0x3031 +#define mmCP_DFY_DATA_14 0x3032 +#define mmCP_DFY_DATA_15 0x3033 +#define mmCP_DFY_CMD 0x3034 +#define mmCP_CPC_MGCG_SYNC_CNTL 0x3036 +#define mmCP_RB0_BASE 0x3040 +#define mmCP_RB0_BASE_HI 0x30b1 +#define mmCP_RB_BASE 0x3040 +#define mmCP_RB1_BASE 0x3060 +#define mmCP_RB1_BASE_HI 0x30b2 +#define mmCP_RB2_BASE 0x3065 +#define mmCP_RB0_CNTL 0x3041 +#define mmCP_RB_CNTL 0x3041 +#define mmCP_RB1_CNTL 0x3061 +#define mmCP_RB2_CNTL 0x3066 +#define mmCP_RB_RPTR_WR 0x3042 +#define mmCP_RB0_RPTR_ADDR 0x3043 +#define mmCP_RB_RPTR_ADDR 0x3043 +#define mmCP_RB1_RPTR_ADDR 0x3062 +#define mmCP_RB2_RPTR_ADDR 0x3067 +#define mmCP_RB0_RPTR_ADDR_HI 0x3044 +#define mmCP_RB_RPTR_ADDR_HI 0x3044 +#define mmCP_RB1_RPTR_ADDR_HI 0x3063 +#define mmCP_RB2_RPTR_ADDR_HI 0x3068 +#define mmCP_RB0_WPTR 0x3045 +#define mmCP_RB_WPTR 0x3045 +#define mmCP_RB1_WPTR 0x3064 +#define mmCP_RB2_WPTR 0x3069 +#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 +#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 +#define mmGC_PRIV_MODE 0x3048 +#define mmCP_INT_CNTL 0x3049 +#define mmCP_INT_CNTL_RING0 0x306a +#define mmCP_INT_CNTL_RING1 0x306b +#define mmCP_INT_CNTL_RING2 0x306c +#define mmCP_INT_STATUS 0x304a +#define mmCP_INT_STATUS_RING0 0x306d +#define mmCP_INT_STATUS_RING1 0x306e +#define mmCP_INT_STATUS_RING2 0x306f +#define mmCP_DEVICE_ID 0x304b +#define mmCP_RING_PRIORITY_CNTS 0x304c +#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c +#define mmCP_RING0_PRIORITY 0x304d +#define mmCP_ME0_PIPE0_PRIORITY 0x304d +#define mmCP_RING1_PRIORITY 0x304e +#define mmCP_ME0_PIPE1_PRIORITY 0x304e +#define mmCP_RING2_PRIORITY 0x304f +#define mmCP_ME0_PIPE2_PRIORITY 0x304f +#define mmCP_ENDIAN_SWAP 0x3050 +#define mmCP_RB_VMID 0x3051 +#define mmCP_ME0_PIPE0_VMID 0x3052 +#define mmCP_ME0_PIPE1_VMID 0x3053 +#define mmCP_RB_DOORBELL_CONTROL 0x3059 +#define mmCP_RB_DOORBELL_RANGE_LOWER 0x305a +#define mmCP_RB_DOORBELL_RANGE_UPPER 0x305b +#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x305c +#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x305d +#define mmCP_PFP_UCODE_ADDR 0xf814 +#define mmCP_PFP_UCODE_DATA 0xf815 +#define mmCP_ME_RAM_RADDR 0xf816 +#define mmCP_ME_RAM_WADDR 0xf816 +#define mmCP_ME_RAM_DATA 0xf817 +#define mmCGTT_CPC_CLK_CTRL 0xf0b2 +#define mmCGTT_CPF_CLK_CTRL 0xf0b1 +#define mmCGTT_CP_CLK_CTRL 0xf0b0 +#define mmCP_CE_UCODE_ADDR 0xf818 +#define mmCP_CE_UCODE_DATA 0xf819 +#define mmCP_MEC_ME1_UCODE_ADDR 0xf81a +#define mmCP_MEC_ME1_UCODE_DATA 0xf81b +#define mmCP_MEC_ME2_UCODE_ADDR 0xf81c +#define mmCP_MEC_ME2_UCODE_DATA 0xf81d +#define mmCP_MEC1_F32_INT_DIS 0x30bd +#define mmCP_MEC2_F32_INT_DIS 0x30be +#define mmCP_VIRT_STATUS 0x3038 +#define mmCP_PWR_CNTL 0x3078 +#define mmCP_MEM_SLP_CNTL 0x3079 +#define mmCP_ECC_FIRSTOCCURRENCE 0x307a +#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b +#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c +#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d +#define mmCP_CPF_DEBUG 0x3080 +#define mmCP_PQ_WPTR_POLL_CNTL 0x3083 +#define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 +#define mmCPC_INT_CNTL 0x30b4 +#define mmCP_ME1_PIPE0_INT_CNTL 0x3085 +#define mmCP_ME1_PIPE1_INT_CNTL 0x3086 +#define mmCP_ME1_PIPE2_INT_CNTL 0x3087 +#define mmCP_ME1_PIPE3_INT_CNTL 0x3088 +#define mmCP_ME2_PIPE0_INT_CNTL 0x3089 +#define mmCP_ME2_PIPE1_INT_CNTL 0x308a +#define mmCP_ME2_PIPE2_INT_CNTL 0x308b +#define mmCP_ME2_PIPE3_INT_CNTL 0x308c +#define mmCPC_INT_STATUS 0x30b5 +#define mmCP_ME1_PIPE0_INT_STATUS 0x308d +#define mmCP_ME1_PIPE1_INT_STATUS 0x308e +#define mmCP_ME1_PIPE2_INT_STATUS 0x308f +#define mmCP_ME1_PIPE3_INT_STATUS 0x3090 +#define mmCP_ME2_PIPE0_INT_STATUS 0x3091 +#define mmCP_ME2_PIPE1_INT_STATUS 0x3092 +#define mmCP_ME2_PIPE2_INT_STATUS 0x3093 +#define mmCP_ME2_PIPE3_INT_STATUS 0x3094 +#define mmCP_ME1_INT_STAT_DEBUG 0x3095 +#define mmCP_ME2_INT_STAT_DEBUG 0x3096 +#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099 +#define mmCP_ME1_PIPE0_PRIORITY 0x309a +#define mmCP_ME1_PIPE1_PRIORITY 0x309b +#define mmCP_ME1_PIPE2_PRIORITY 0x309c +#define mmCP_ME1_PIPE3_PRIORITY 0x309d +#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e +#define mmCP_ME2_PIPE0_PRIORITY 0x309f +#define mmCP_ME2_PIPE1_PRIORITY 0x30a0 +#define mmCP_ME2_PIPE2_PRIORITY 0x30a1 +#define mmCP_ME2_PIPE3_PRIORITY 0x30a2 +#define mmCP_CE_PRGRM_CNTR_START 0x30a3 +#define mmCP_PFP_PRGRM_CNTR_START 0x30a4 +#define mmCP_ME_PRGRM_CNTR_START 0x30a5 +#define mmCP_MEC1_PRGRM_CNTR_START 0x30a6 +#define mmCP_MEC2_PRGRM_CNTR_START 0x30a7 +#define mmCP_CE_INTR_ROUTINE_START 0x30a8 +#define mmCP_PFP_INTR_ROUTINE_START 0x30a9 +#define mmCP_ME_INTR_ROUTINE_START 0x30aa +#define mmCP_MEC1_INTR_ROUTINE_START 0x30ab +#define mmCP_MEC2_INTR_ROUTINE_START 0x30ac +#define mmCP_CONTEXT_CNTL 0x30ad +#define mmCP_MAX_CONTEXT 0x30ae +#define mmCP_IQ_WAIT_TIME1 0x30af +#define mmCP_IQ_WAIT_TIME2 0x30b0 +#define mmCP_VMID_RESET 0x30b3 +#define mmCP_VMID_PREEMPT 0x30b6 +#define mmCP_VMID_STATUS 0x30bf +#define mmCPC_INT_CNTX_ID 0x30b7 +#define mmCP_PQ_STATUS 0x30b8 +#define mmCP_CPC_IC_BASE_LO 0x30b9 +#define mmCP_CPC_IC_BASE_HI 0x30ba +#define mmCP_CPC_IC_BASE_CNTL 0x30bb +#define mmCP_CPC_IC_OP_CNTL 0x30bc +#define mmCP_CPC_STATUS 0x2084 +#define mmCP_CPC_BUSY_STAT 0x2085 +#define mmCP_CPC_STALLED_STAT1 0x2086 +#define mmCP_CPF_STATUS 0x2087 +#define mmCP_CPF_BUSY_STAT 0x2088 +#define mmCP_CPF_STALLED_STAT1 0x2089 +#define mmCP_CPC_GRBM_FREE_COUNT 0x208b +#define mmCP_MEC_CNTL 0x208d +#define mmCP_MEC_ME1_HEADER_DUMP 0x208e +#define mmCP_MEC_ME2_HEADER_DUMP 0x208f +#define mmCP_CPC_SCRATCH_INDEX 0x2090 +#define mmCP_CPC_SCRATCH_DATA 0x2091 +#define mmCPG_PERFCOUNTER1_SELECT 0xd800 +#define mmCPG_PERFCOUNTER1_LO 0xd000 +#define mmCPG_PERFCOUNTER1_HI 0xd001 +#define mmCPG_PERFCOUNTER0_SELECT1 0xd801 +#define mmCPG_PERFCOUNTER0_SELECT 0xd802 +#define mmCPG_PERFCOUNTER0_LO 0xd002 +#define mmCPG_PERFCOUNTER0_HI 0xd003 +#define mmCPC_PERFCOUNTER1_SELECT 0xd803 +#define mmCPC_PERFCOUNTER1_LO 0xd004 +#define mmCPC_PERFCOUNTER1_HI 0xd005 +#define mmCPC_PERFCOUNTER0_SELECT1 0xd804 +#define mmCPC_PERFCOUNTER0_SELECT 0xd809 +#define mmCPC_PERFCOUNTER0_LO 0xd006 +#define mmCPC_PERFCOUNTER0_HI 0xd007 +#define mmCPF_PERFCOUNTER1_SELECT 0xd805 +#define mmCPF_PERFCOUNTER1_LO 0xd008 +#define mmCPF_PERFCOUNTER1_HI 0xd009 +#define mmCPF_PERFCOUNTER0_SELECT1 0xd806 +#define mmCPF_PERFCOUNTER0_SELECT 0xd807 +#define mmCPF_PERFCOUNTER0_LO 0xd00a +#define mmCPF_PERFCOUNTER0_HI 0xd00b +#define mmCP_CPC_HALT_HYST_COUNT 0x20a7 +#define mmCP_DRAW_OBJECT 0xd810 +#define mmCP_DRAW_OBJECT_COUNTER 0xd811 +#define mmCP_DRAW_WINDOW_MASK_HI 0xd812 +#define mmCP_DRAW_WINDOW_HI 0xd813 +#define mmCP_DRAW_WINDOW_LO 0xd814 +#define mmCP_DRAW_WINDOW_CNTL 0xd815 +#define mmCP_PRT_LOD_STATS_CNTL0 0x20ad +#define mmCP_PRT_LOD_STATS_CNTL1 0x20ae +#define mmCP_PRT_LOD_STATS_CNTL2 0x20af +#define mmCP_CE_COMPARE_COUNT 0x20c0 +#define mmCP_CE_DE_COUNT 0x20c1 +#define mmCP_DE_CE_COUNT 0x20c2 +#define mmCP_DE_LAST_INVAL_COUNT 0x20c3 +#define mmCP_DE_DE_COUNT 0x20c4 +#define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5 +#define mmCP_EOP_DONE_DATA_CNTL 0xc0d6 +#define mmCP_EOP_DONE_CNTX_ID 0xc0d7 +#define mmCP_EOP_DONE_ADDR_LO 0xc000 +#define mmCP_EOP_DONE_ADDR_HI 0xc001 +#define mmCP_EOP_DONE_DATA_LO 0xc002 +#define mmCP_EOP_DONE_DATA_HI 0xc003 +#define mmCP_EOP_LAST_FENCE_LO 0xc004 +#define mmCP_EOP_LAST_FENCE_HI 0xc005 +#define mmCP_STREAM_OUT_ADDR_LO 0xc006 +#define mmCP_STREAM_OUT_ADDR_HI 0xc007 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009 +#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a +#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d +#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e +#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017 +#define mmCP_PIPE_STATS_ADDR_LO 0xc018 +#define mmCP_PIPE_STATS_ADDR_HI 0xc019 +#define mmCP_VGT_IAVERT_COUNT_LO 0xc01a +#define mmCP_VGT_IAVERT_COUNT_HI 0xc01b +#define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c +#define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d +#define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e +#define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f +#define mmCP_VGT_VSINVOC_COUNT_LO 0xc020 +#define mmCP_VGT_VSINVOC_COUNT_HI 0xc021 +#define mmCP_VGT_GSINVOC_COUNT_LO 0xc022 +#define mmCP_VGT_GSINVOC_COUNT_HI 0xc023 +#define mmCP_VGT_HSINVOC_COUNT_LO 0xc024 +#define mmCP_VGT_HSINVOC_COUNT_HI 0xc025 +#define mmCP_VGT_DSINVOC_COUNT_LO 0xc026 +#define mmCP_VGT_DSINVOC_COUNT_HI 0xc027 +#define mmCP_PA_CINVOC_COUNT_LO 0xc028 +#define mmCP_PA_CINVOC_COUNT_HI 0xc029 +#define mmCP_PA_CPRIM_COUNT_LO 0xc02a +#define mmCP_PA_CPRIM_COUNT_HI 0xc02b +#define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c +#define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d +#define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e +#define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f +#define mmCP_VGT_CSINVOC_COUNT_LO 0xc030 +#define mmCP_VGT_CSINVOC_COUNT_HI 0xc031 +#define mmCP_PIPE_STATS_CONTROL 0xc03d +#define mmCP_STREAM_OUT_CONTROL 0xc03e +#define mmCP_STRMOUT_CNTL 0xc03f +#define mmSCRATCH_REG0 0xc040 +#define mmSCRATCH_REG1 0xc041 +#define mmSCRATCH_REG2 0xc042 +#define mmSCRATCH_REG3 0xc043 +#define mmSCRATCH_REG4 0xc044 +#define mmSCRATCH_REG5 0xc045 +#define mmSCRATCH_REG6 0xc046 +#define mmSCRATCH_REG7 0xc047 +#define mmSCRATCH_UMSK 0xc050 +#define mmSCRATCH_ADDR 0xc051 +#define mmCP_PFP_ATOMIC_PREOP_LO 0xc052 +#define mmCP_PFP_ATOMIC_PREOP_HI 0xc053 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057 +#define mmCP_APPEND_ADDR_LO 0xc058 +#define mmCP_APPEND_ADDR_HI 0xc059 +#define mmCP_APPEND_DATA 0xc05a +#define mmCP_APPEND_LAST_CS_FENCE 0xc05b +#define mmCP_APPEND_LAST_PS_FENCE 0xc05c +#define mmCP_ATOMIC_PREOP_LO 0xc05d +#define mmCP_ME_ATOMIC_PREOP_LO 0xc05d +#define mmCP_ATOMIC_PREOP_HI 0xc05e +#define mmCP_ME_ATOMIC_PREOP_HI 0xc05e +#define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f +#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f +#define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060 +#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060 +#define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061 +#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061 +#define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062 +#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062 +#define mmCP_ME_MC_WADDR_LO 0xc069 +#define mmCP_ME_MC_WADDR_HI 0xc06a +#define mmCP_ME_MC_WDATA_LO 0xc06b +#define mmCP_ME_MC_WDATA_HI 0xc06c +#define mmCP_ME_MC_RADDR_LO 0xc06d +#define mmCP_ME_MC_RADDR_HI 0xc06e +#define mmCP_SEM_WAIT_TIMER 0xc06f +#define mmCP_SIG_SEM_ADDR_LO 0xc070 +#define mmCP_SIG_SEM_ADDR_HI 0xc071 +#define mmCP_WAIT_SEM_ADDR_LO 0xc075 +#define mmCP_WAIT_SEM_ADDR_HI 0xc076 +#define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074 +#define mmCP_COHER_START_DELAY 0xc07b +#define mmCP_COHER_CNTL 0xc07c +#define mmCP_COHER_SIZE 0xc07d +#define mmCP_COHER_SIZE_HI 0xc08c +#define mmCP_COHER_BASE 0xc07e +#define mmCP_COHER_BASE_HI 0xc079 +#define mmCP_COHER_STATUS 0xc07f +#define mmCOHER_DEST_BASE_0 0xa092 +#define mmCOHER_DEST_BASE_1 0xa093 +#define mmCOHER_DEST_BASE_2 0xa07e +#define mmCOHER_DEST_BASE_3 0xa07f +#define mmCOHER_DEST_BASE_HI_0 0xa07a +#define mmCOHER_DEST_BASE_HI_1 0xa07b +#define mmCOHER_DEST_BASE_HI_2 0xa07c +#define mmCOHER_DEST_BASE_HI_3 0xa07d +#define mmCP_DMA_ME_SRC_ADDR 0xc080 +#define mmCP_DMA_ME_SRC_ADDR_HI 0xc081 +#define mmCP_DMA_ME_DST_ADDR 0xc082 +#define mmCP_DMA_ME_DST_ADDR_HI 0xc083 +#define mmCP_DMA_ME_CONTROL 0xc078 +#define mmCP_DMA_ME_COMMAND 0xc084 +#define mmCP_DMA_PFP_SRC_ADDR 0xc085 +#define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086 +#define mmCP_DMA_PFP_DST_ADDR 0xc087 +#define mmCP_DMA_PFP_DST_ADDR_HI 0xc088 +#define mmCP_DMA_PFP_CONTROL 0xc077 +#define mmCP_DMA_PFP_COMMAND 0xc089 +#define mmCP_DMA_CNTL 0xc08a +#define mmCP_DMA_READ_TAGS 0xc08b +#define mmCP_PFP_IB_CONTROL 0xc08d +#define mmCP_PFP_LOAD_CONTROL 0xc08e +#define mmCP_SCRATCH_INDEX 0xc08f +#define mmCP_SCRATCH_DATA 0xc090 +#define mmCP_RB_OFFSET 0xc091 +#define mmCP_IB1_OFFSET 0xc092 +#define mmCP_IB2_OFFSET 0xc093 +#define mmCP_IB1_PREAMBLE_BEGIN 0xc094 +#define mmCP_IB1_PREAMBLE_END 0xc095 +#define mmCP_IB2_PREAMBLE_BEGIN 0xc096 +#define mmCP_IB2_PREAMBLE_END 0xc097 +#define mmCP_CE_IB1_OFFSET 0xc098 +#define mmCP_CE_IB2_OFFSET 0xc099 +#define mmCP_CE_COUNTER 0xc09a +#define mmCP_CE_RB_OFFSET 0xc09b +#define mmCP_PFP_COMPLETION_STATUS 0xc0ec +#define mmCP_CE_COMPLETION_STATUS 0xc0ed +#define mmCP_PRED_NOT_VISIBLE 0xc0ee +#define mmCP_PFP_METADATA_BASE_ADDR 0xc0f0 +#define mmCP_PFP_METADATA_BASE_ADDR_HI 0xc0f1 +#define mmCP_CE_METADATA_BASE_ADDR 0xc0f2 +#define mmCP_CE_METADATA_BASE_ADDR_HI 0xc0f3 +#define mmCP_DRAW_INDX_INDR_ADDR 0xc0f4 +#define mmCP_DRAW_INDX_INDR_ADDR_HI 0xc0f5 +#define mmCP_DISPATCH_INDR_ADDR 0xc0f6 +#define mmCP_DISPATCH_INDR_ADDR_HI 0xc0f7 +#define mmCP_INDEX_BASE_ADDR 0xc0f8 +#define mmCP_INDEX_BASE_ADDR_HI 0xc0f9 +#define mmCP_INDEX_TYPE 0xc0fa +#define mmCP_GDS_BKUP_ADDR 0xc0fb +#define mmCP_GDS_BKUP_ADDR_HI 0xc0fc +#define mmCP_SAMPLE_STATUS 0xc0fd +#define mmCP_STALLED_STAT1 0x219d +#define mmCP_STALLED_STAT2 0x219e +#define mmCP_STALLED_STAT3 0x219c +#define mmCP_BUSY_STAT 0x219f +#define mmCP_STAT 0x21a0 +#define mmCP_ME_HEADER_DUMP 0x21a1 +#define mmCP_PFP_HEADER_DUMP 0x21a2 +#define mmCP_GRBM_FREE_COUNT 0x21a3 +#define mmCP_CE_HEADER_DUMP 0x21a4 +#define mmCP_CSF_STAT 0x21b4 +#define mmCP_CSF_CNTL 0x21b5 +#define mmCP_ME_CNTL 0x21b6 +#define mmCP_CNTX_STAT 0x21b8 +#define mmCP_ME_PREEMPTION 0x21b9 +#define mmCP_RB0_RPTR 0x21c0 +#define mmCP_RB_RPTR 0x21c0 +#define mmCP_RB1_RPTR 0x21bf +#define mmCP_RB2_RPTR 0x21be +#define mmCP_RB_WPTR_DELAY 0x21c1 +#define mmCP_RB_WPTR_POLL_CNTL 0x21c2 +#define mmCP_CE_INIT_BASE_LO 0xc0c3 +#define mmCP_CE_INIT_BASE_HI 0xc0c4 +#define mmCP_CE_INIT_BUFSZ 0xc0c5 +#define mmCP_CE_IB1_BASE_LO 0xc0c6 +#define mmCP_CE_IB1_BASE_HI 0xc0c7 +#define mmCP_CE_IB1_BUFSZ 0xc0c8 +#define mmCP_CE_IB2_BASE_LO 0xc0c9 +#define mmCP_CE_IB2_BASE_HI 0xc0ca +#define mmCP_CE_IB2_BUFSZ 0xc0cb +#define mmCP_IB1_BASE_LO 0xc0cc +#define mmCP_IB1_BASE_HI 0xc0cd +#define mmCP_IB1_BUFSZ 0xc0ce +#define mmCP_IB2_BASE_LO 0xc0cf +#define mmCP_IB2_BASE_HI 0xc0d0 +#define mmCP_IB2_BUFSZ 0xc0d1 +#define mmCP_ST_BASE_LO 0xc0d2 +#define mmCP_ST_BASE_HI 0xc0d3 +#define mmCP_ST_BUFSZ 0xc0d4 +#define mmCP_ROQ_THRESHOLDS 0x21bc +#define mmCP_MEQ_STQ_THRESHOLD 0x21bd +#define mmCP_ROQ1_THRESHOLDS 0x21d5 +#define mmCP_ROQ2_THRESHOLDS 0x21d6 +#define mmCP_STQ_THRESHOLDS 0x21d7 +#define mmCP_QUEUE_THRESHOLDS 0x21d8 +#define mmCP_MEQ_THRESHOLDS 0x21d9 +#define mmCP_ROQ_AVAIL 0x21da +#define mmCP_STQ_AVAIL 0x21db +#define mmCP_ROQ2_AVAIL 0x21dc +#define mmCP_MEQ_AVAIL 0x21dd +#define mmCP_CMD_INDEX 0x21de +#define mmCP_CMD_DATA 0x21df +#define mmCP_ROQ_RB_STAT 0x21e0 +#define mmCP_ROQ_IB1_STAT 0x21e1 +#define mmCP_ROQ_IB2_STAT 0x21e2 +#define mmCP_STQ_STAT 0x21e3 +#define mmCP_STQ_WR_STAT 0x21e4 +#define mmCP_MEQ_STAT 0x21e5 +#define mmCP_CEQ1_AVAIL 0x21e6 +#define mmCP_CEQ2_AVAIL 0x21e7 +#define mmCP_CE_ROQ_RB_STAT 0x21e8 +#define mmCP_CE_ROQ_IB1_STAT 0x21e9 +#define mmCP_CE_ROQ_IB2_STAT 0x21ea +#define mmCP_INT_STAT_DEBUG 0x21f7 +#define mmCP_PERFMON_CNTL 0xd808 +#define mmCP_PERFMON_CNTX_CNTL 0xa0d8 +#define mmCP_RINGID 0xa0d9 +#define mmCP_PIPEID 0xa0d9 +#define mmCP_VMID 0xa0da +#define mmCP_HPD_ROQ_OFFSETS 0x3240 +#define mmCP_HPD_STATUS0 0x3241 +#define mmCP_MQD_BASE_ADDR 0x3245 +#define mmCP_MQD_BASE_ADDR_HI 0x3246 +#define mmCP_HQD_ACTIVE 0x3247 +#define mmCP_HQD_VMID 0x3248 +#define mmCP_HQD_PERSISTENT_STATE 0x3249 +#define mmCP_HQD_PIPE_PRIORITY 0x324a +#define mmCP_HQD_QUEUE_PRIORITY 0x324b +#define mmCP_HQD_QUANTUM 0x324c +#define mmCP_HQD_PQ_BASE 0x324d +#define mmCP_HQD_PQ_BASE_HI 0x324e +#define mmCP_HQD_PQ_RPTR 0x324f +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 +#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 +#define mmCP_HQD_PQ_WPTR 0x3255 +#define mmCP_HQD_PQ_CONTROL 0x3256 +#define mmCP_HQD_IB_BASE_ADDR 0x3257 +#define mmCP_HQD_IB_BASE_ADDR_HI 0x3258 +#define mmCP_HQD_IB_RPTR 0x3259 +#define mmCP_HQD_IB_CONTROL 0x325a +#define mmCP_HQD_IQ_TIMER 0x325b +#define mmCP_HQD_IQ_RPTR 0x325c +#define mmCP_HQD_DEQUEUE_REQUEST 0x325d +#define mmCP_HQD_DMA_OFFLOAD 0x325e +#define mmCP_HQD_OFFLOAD 0x325e +#define mmCP_HQD_SEMA_CMD 0x325f +#define mmCP_HQD_MSG_TYPE 0x3260 +#define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261 +#define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262 +#define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263 +#define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264 +#define mmCP_HQD_HQ_SCHEDULER0 0x3265 +#define mmCP_HQD_HQ_STATUS0 0x3265 +#define mmCP_HQD_HQ_SCHEDULER1 0x3266 +#define mmCP_HQD_HQ_CONTROL0 0x3266 +#define mmCP_MQD_CONTROL 0x3267 +#define mmCP_HQD_HQ_STATUS1 0x3268 +#define mmCP_HQD_HQ_CONTROL1 0x3269 +#define mmCP_HQD_EOP_BASE_ADDR 0x326a +#define mmCP_HQD_EOP_BASE_ADDR_HI 0x326b +#define mmCP_HQD_EOP_CONTROL 0x326c +#define mmCP_HQD_EOP_RPTR 0x326d +#define mmCP_HQD_EOP_WPTR 0x326e +#define mmCP_HQD_EOP_EVENTS 0x326f +#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x3270 +#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x3271 +#define mmCP_HQD_CTX_SAVE_CONTROL 0x3272 +#define mmCP_HQD_CNTL_STACK_OFFSET 0x3273 +#define mmCP_HQD_CNTL_STACK_SIZE 0x3274 +#define mmCP_HQD_WG_STATE_OFFSET 0x3275 +#define mmCP_HQD_CTX_SAVE_SIZE 0x3276 +#define mmCP_HQD_GDS_RESOURCE_STATE 0x3277 +#define mmCP_HQD_ERROR 0x3278 +#define mmCP_HQD_EOP_WPTR_MEM 0x3279 +#define mmCP_HQD_EOP_DONES 0x327a +#define mmDB_Z_READ_BASE 0xa012 +#define mmDB_STENCIL_READ_BASE 0xa013 +#define mmDB_Z_WRITE_BASE 0xa014 +#define mmDB_STENCIL_WRITE_BASE 0xa015 +#define mmDB_DEPTH_INFO 0xa00f +#define mmDB_Z_INFO 0xa010 +#define mmDB_STENCIL_INFO 0xa011 +#define mmDB_DEPTH_SIZE 0xa016 +#define mmDB_DEPTH_SLICE 0xa017 +#define mmDB_DEPTH_VIEW 0xa002 +#define mmDB_RENDER_CONTROL 0xa000 +#define mmDB_COUNT_CONTROL 0xa001 +#define mmDB_RENDER_OVERRIDE 0xa003 +#define mmDB_RENDER_OVERRIDE2 0xa004 +#define mmDB_EQAA 0xa201 +#define mmDB_SHADER_CONTROL 0xa203 +#define mmDB_DEPTH_BOUNDS_MIN 0xa008 +#define mmDB_DEPTH_BOUNDS_MAX 0xa009 +#define mmDB_STENCIL_CLEAR 0xa00a +#define mmDB_DEPTH_CLEAR 0xa00b +#define mmDB_HTILE_DATA_BASE 0xa005 +#define mmDB_HTILE_SURFACE 0xa2af +#define mmDB_PRELOAD_CONTROL 0xa2b2 +#define mmDB_STENCILREFMASK 0xa10c +#define mmDB_STENCILREFMASK_BF 0xa10d +#define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0 +#define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1 +#define mmDB_DEPTH_CONTROL 0xa200 +#define mmDB_STENCIL_CONTROL 0xa10b +#define mmDB_ALPHA_TO_MASK 0xa2dc +#define mmDB_PERFCOUNTER0_SELECT 0xdc40 +#define mmDB_PERFCOUNTER1_SELECT 0xdc42 +#define mmDB_PERFCOUNTER2_SELECT 0xdc44 +#define mmDB_PERFCOUNTER3_SELECT 0xdc46 +#define mmDB_PERFCOUNTER0_SELECT1 0xdc41 +#define mmDB_PERFCOUNTER1_SELECT1 0xdc43 +#define mmDB_PERFCOUNTER0_LO 0xd440 +#define mmDB_PERFCOUNTER1_LO 0xd442 +#define mmDB_PERFCOUNTER2_LO 0xd444 +#define mmDB_PERFCOUNTER3_LO 0xd446 +#define mmDB_PERFCOUNTER0_HI 0xd441 +#define mmDB_PERFCOUNTER1_HI 0xd443 +#define mmDB_PERFCOUNTER2_HI 0xd445 +#define mmDB_PERFCOUNTER3_HI 0xd447 +#define mmDB_DEBUG 0x260c +#define mmDB_DEBUG2 0x260d +#define mmDB_DEBUG3 0x260e +#define mmDB_DEBUG4 0x260f +#define mmDB_CREDIT_LIMIT 0x2614 +#define mmDB_WATERMARKS 0x2615 +#define mmDB_SUBTILE_CONTROL 0x2616 +#define mmDB_FREE_CACHELINES 0x2617 +#define mmDB_FIFO_DEPTH1 0x2618 +#define mmDB_FIFO_DEPTH2 0x2619 +#define mmDB_CGTT_CLK_CTRL_0 0xf0a4 +#define mmDB_ZPASS_COUNT_LOW 0xc3fe +#define mmDB_ZPASS_COUNT_HI 0xc3ff +#define mmDB_RING_CONTROL 0x261b +#define mmDB_READ_DEBUG_0 0x2620 +#define mmDB_READ_DEBUG_1 0x2621 +#define mmDB_READ_DEBUG_2 0x2622 +#define mmDB_READ_DEBUG_3 0x2623 +#define mmDB_READ_DEBUG_4 0x2624 +#define mmDB_READ_DEBUG_5 0x2625 +#define mmDB_READ_DEBUG_6 0x2626 +#define mmDB_READ_DEBUG_7 0x2627 +#define mmDB_READ_DEBUG_8 0x2628 +#define mmDB_READ_DEBUG_9 0x2629 +#define mmDB_READ_DEBUG_A 0x262a +#define mmDB_READ_DEBUG_B 0x262b +#define mmDB_READ_DEBUG_C 0x262c +#define mmDB_READ_DEBUG_D 0x262d +#define mmDB_READ_DEBUG_E 0x262e +#define mmDB_READ_DEBUG_F 0x262f +#define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0 +#define mmDB_OCCLUSION_COUNT0_HI 0xc3c1 +#define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2 +#define mmDB_OCCLUSION_COUNT1_HI 0xc3c3 +#define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4 +#define mmDB_OCCLUSION_COUNT2_HI 0xc3c5 +#define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6 +#define mmDB_OCCLUSION_COUNT3_HI 0xc3c7 +#define mmCC_RB_REDUNDANCY 0x263c +#define mmCC_RB_BACKEND_DISABLE 0x263d +#define mmGC_USER_RB_REDUNDANCY 0x26de +#define mmGC_USER_RB_BACKEND_DISABLE 0x26df +#define mmGB_ADDR_CONFIG 0x263e +#define mmGB_BACKEND_MAP 0x263f +#define mmGB_GPU_ID 0x2640 +#define mmCC_RB_DAISY_CHAIN 0x2641 +#define mmGB_TILE_MODE0 0x2644 +#define mmGB_TILE_MODE1 0x2645 +#define mmGB_TILE_MODE2 0x2646 +#define mmGB_TILE_MODE3 0x2647 +#define mmGB_TILE_MODE4 0x2648 +#define mmGB_TILE_MODE5 0x2649 +#define mmGB_TILE_MODE6 0x264a +#define mmGB_TILE_MODE7 0x264b +#define mmGB_TILE_MODE8 0x264c +#define mmGB_TILE_MODE9 0x264d +#define mmGB_TILE_MODE10 0x264e +#define mmGB_TILE_MODE11 0x264f +#define mmGB_TILE_MODE12 0x2650 +#define mmGB_TILE_MODE13 0x2651 +#define mmGB_TILE_MODE14 0x2652 +#define mmGB_TILE_MODE15 0x2653 +#define mmGB_TILE_MODE16 0x2654 +#define mmGB_TILE_MODE17 0x2655 +#define mmGB_TILE_MODE18 0x2656 +#define mmGB_TILE_MODE19 0x2657 +#define mmGB_TILE_MODE20 0x2658 +#define mmGB_TILE_MODE21 0x2659 +#define mmGB_TILE_MODE22 0x265a +#define mmGB_TILE_MODE23 0x265b +#define mmGB_TILE_MODE24 0x265c +#define mmGB_TILE_MODE25 0x265d +#define mmGB_TILE_MODE26 0x265e +#define mmGB_TILE_MODE27 0x265f +#define mmGB_TILE_MODE28 0x2660 +#define mmGB_TILE_MODE29 0x2661 +#define mmGB_TILE_MODE30 0x2662 +#define mmGB_TILE_MODE31 0x2663 +#define mmGB_MACROTILE_MODE0 0x2664 +#define mmGB_MACROTILE_MODE1 0x2665 +#define mmGB_MACROTILE_MODE2 0x2666 +#define mmGB_MACROTILE_MODE3 0x2667 +#define mmGB_MACROTILE_MODE4 0x2668 +#define mmGB_MACROTILE_MODE5 0x2669 +#define mmGB_MACROTILE_MODE6 0x266a +#define mmGB_MACROTILE_MODE7 0x266b +#define mmGB_MACROTILE_MODE8 0x266c +#define mmGB_MACROTILE_MODE9 0x266d +#define mmGB_MACROTILE_MODE10 0x266e +#define mmGB_MACROTILE_MODE11 0x266f +#define mmGB_MACROTILE_MODE12 0x2670 +#define mmGB_MACROTILE_MODE13 0x2671 +#define mmGB_MACROTILE_MODE14 0x2672 +#define mmGB_MACROTILE_MODE15 0x2673 +#define mmGB_EDC_MODE 0x307e +#define mmCC_GC_EDC_CONFIG 0x3098 +#define mmRAS_SIGNATURE_CONTROL 0x3380 +#define mmRAS_SIGNATURE_MASK 0x3381 +#define mmRAS_SX_SIGNATURE0 0x3382 +#define mmRAS_SX_SIGNATURE1 0x3383 +#define mmRAS_SX_SIGNATURE2 0x3384 +#define mmRAS_SX_SIGNATURE3 0x3385 +#define mmRAS_DB_SIGNATURE0 0x338b +#define mmRAS_PA_SIGNATURE0 0x338c +#define mmRAS_VGT_SIGNATURE0 0x338d +#define mmRAS_SQ_SIGNATURE0 0x338e +#define mmRAS_SC_SIGNATURE0 0x338f +#define mmRAS_SC_SIGNATURE1 0x3390 +#define mmRAS_SC_SIGNATURE2 0x3391 +#define mmRAS_SC_SIGNATURE3 0x3392 +#define mmRAS_SC_SIGNATURE4 0x3393 +#define mmRAS_SC_SIGNATURE5 0x3394 +#define mmRAS_SC_SIGNATURE6 0x3395 +#define mmRAS_SC_SIGNATURE7 0x3396 +#define mmRAS_IA_SIGNATURE0 0x3397 +#define mmRAS_IA_SIGNATURE1 0x3398 +#define mmRAS_SPI_SIGNATURE0 0x3399 +#define mmRAS_SPI_SIGNATURE1 0x339a +#define mmRAS_TA_SIGNATURE0 0x339b +#define mmRAS_TD_SIGNATURE0 0x339c +#define mmRAS_CB_SIGNATURE0 0x339d +#define mmRAS_BCI_SIGNATURE0 0x339e +#define mmRAS_BCI_SIGNATURE1 0x339f +#define mmRAS_TA_SIGNATURE1 0x33a0 +#define mmGRBM_HYP_CAM_INDEX 0xf83e +#define mmGRBM_CAM_INDEX 0xf83e +#define mmGRBM_HYP_CAM_DATA 0xf83f +#define mmGRBM_CAM_DATA 0xf83f +#define mmGRBM_CNTL 0x2000 +#define mmGRBM_SKEW_CNTL 0x2001 +#define mmGRBM_PWR_CNTL 0x2003 +#define mmGRBM_STATUS 0x2004 +#define mmGRBM_STATUS2 0x2002 +#define mmGRBM_STATUS_SE0 0x2005 +#define mmGRBM_STATUS_SE1 0x2006 +#define mmGRBM_STATUS_SE2 0x200e +#define mmGRBM_STATUS_SE3 0x200f +#define mmGRBM_SOFT_RESET 0x2008 +#define mmGRBM_DEBUG_CNTL 0x2009 +#define mmGRBM_DEBUG_DATA 0x200a +#define mmGRBM_GFX_INDEX 0xc200 +#define mmGRBM_GFX_CLKEN_CNTL 0x200c +#define mmGRBM_WAIT_IDLE_CLOCKS 0x200d +#define mmGRBM_DEBUG 0x2014 +#define mmGRBM_DEBUG_SNAPSHOT 0x2015 +#define mmGRBM_READ_ERROR 0x2016 +#define mmGRBM_READ_ERROR2 0x2017 +#define mmGRBM_INT_CNTL 0x2018 +#define mmGRBM_TRAP_OP 0x2019 +#define mmGRBM_TRAP_ADDR 0x201a +#define mmGRBM_TRAP_ADDR_MSK 0x201b +#define mmGRBM_TRAP_WD 0x201c +#define mmGRBM_TRAP_WD_MSK 0x201d +#define mmGRBM_DSM_BYPASS 0x201e +#define mmGRBM_WRITE_ERROR 0x201f +#define mmGRBM_PERFCOUNTER0_SELECT 0xd840 +#define mmGRBM_PERFCOUNTER1_SELECT 0xd841 +#define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842 +#define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843 +#define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844 +#define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845 +#define mmGRBM_PERFCOUNTER0_LO 0xd040 +#define mmGRBM_PERFCOUNTER0_HI 0xd041 +#define mmGRBM_PERFCOUNTER1_LO 0xd043 +#define mmGRBM_PERFCOUNTER1_HI 0xd044 +#define mmGRBM_SE0_PERFCOUNTER_LO 0xd045 +#define mmGRBM_SE0_PERFCOUNTER_HI 0xd046 +#define mmGRBM_SE1_PERFCOUNTER_LO 0xd047 +#define mmGRBM_SE1_PERFCOUNTER_HI 0xd048 +#define mmGRBM_SE2_PERFCOUNTER_LO 0xd049 +#define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a +#define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b +#define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c +#define mmGRBM_SCRATCH_REG0 0x2040 +#define mmGRBM_SCRATCH_REG1 0x2041 +#define mmGRBM_SCRATCH_REG2 0x2042 +#define mmGRBM_SCRATCH_REG3 0x2043 +#define mmGRBM_SCRATCH_REG4 0x2044 +#define mmGRBM_SCRATCH_REG5 0x2045 +#define mmGRBM_SCRATCH_REG6 0x2046 +#define mmGRBM_SCRATCH_REG7 0x2047 +#define mmDEBUG_INDEX 0x203c +#define mmDEBUG_DATA 0x203d +#define mmGRBM_NOWHERE 0x203f +#define mmPA_CL_VPORT_XSCALE 0xa10f +#define mmPA_CL_VPORT_XOFFSET 0xa110 +#define mmPA_CL_VPORT_YSCALE 0xa111 +#define mmPA_CL_VPORT_YOFFSET 0xa112 +#define mmPA_CL_VPORT_ZSCALE 0xa113 +#define mmPA_CL_VPORT_ZOFFSET 0xa114 +#define mmPA_CL_VPORT_XSCALE_1 0xa115 +#define mmPA_CL_VPORT_XSCALE_2 0xa11b +#define mmPA_CL_VPORT_XSCALE_3 0xa121 +#define mmPA_CL_VPORT_XSCALE_4 0xa127 +#define mmPA_CL_VPORT_XSCALE_5 0xa12d +#define mmPA_CL_VPORT_XSCALE_6 0xa133 +#define mmPA_CL_VPORT_XSCALE_7 0xa139 +#define mmPA_CL_VPORT_XSCALE_8 0xa13f +#define mmPA_CL_VPORT_XSCALE_9 0xa145 +#define mmPA_CL_VPORT_XSCALE_10 0xa14b +#define mmPA_CL_VPORT_XSCALE_11 0xa151 +#define mmPA_CL_VPORT_XSCALE_12 0xa157 +#define mmPA_CL_VPORT_XSCALE_13 0xa15d +#define mmPA_CL_VPORT_XSCALE_14 0xa163 +#define mmPA_CL_VPORT_XSCALE_15 0xa169 +#define mmPA_CL_VPORT_XOFFSET_1 0xa116 +#define mmPA_CL_VPORT_XOFFSET_2 0xa11c +#define mmPA_CL_VPORT_XOFFSET_3 0xa122 +#define mmPA_CL_VPORT_XOFFSET_4 0xa128 +#define mmPA_CL_VPORT_XOFFSET_5 0xa12e +#define mmPA_CL_VPORT_XOFFSET_6 0xa134 +#define mmPA_CL_VPORT_XOFFSET_7 0xa13a +#define mmPA_CL_VPORT_XOFFSET_8 0xa140 +#define mmPA_CL_VPORT_XOFFSET_9 0xa146 +#define mmPA_CL_VPORT_XOFFSET_10 0xa14c +#define mmPA_CL_VPORT_XOFFSET_11 0xa152 +#define mmPA_CL_VPORT_XOFFSET_12 0xa158 +#define mmPA_CL_VPORT_XOFFSET_13 0xa15e +#define mmPA_CL_VPORT_XOFFSET_14 0xa164 +#define mmPA_CL_VPORT_XOFFSET_15 0xa16a +#define mmPA_CL_VPORT_YSCALE_1 0xa117 +#define mmPA_CL_VPORT_YSCALE_2 0xa11d +#define mmPA_CL_VPORT_YSCALE_3 0xa123 +#define mmPA_CL_VPORT_YSCALE_4 0xa129 +#define mmPA_CL_VPORT_YSCALE_5 0xa12f +#define mmPA_CL_VPORT_YSCALE_6 0xa135 +#define mmPA_CL_VPORT_YSCALE_7 0xa13b +#define mmPA_CL_VPORT_YSCALE_8 0xa141 +#define mmPA_CL_VPORT_YSCALE_9 0xa147 +#define mmPA_CL_VPORT_YSCALE_10 0xa14d +#define mmPA_CL_VPORT_YSCALE_11 0xa153 +#define mmPA_CL_VPORT_YSCALE_12 0xa159 +#define mmPA_CL_VPORT_YSCALE_13 0xa15f +#define mmPA_CL_VPORT_YSCALE_14 0xa165 +#define mmPA_CL_VPORT_YSCALE_15 0xa16b +#define mmPA_CL_VPORT_YOFFSET_1 0xa118 +#define mmPA_CL_VPORT_YOFFSET_2 0xa11e +#define mmPA_CL_VPORT_YOFFSET_3 0xa124 +#define mmPA_CL_VPORT_YOFFSET_4 0xa12a +#define mmPA_CL_VPORT_YOFFSET_5 0xa130 +#define mmPA_CL_VPORT_YOFFSET_6 0xa136 +#define mmPA_CL_VPORT_YOFFSET_7 0xa13c +#define mmPA_CL_VPORT_YOFFSET_8 0xa142 +#define mmPA_CL_VPORT_YOFFSET_9 0xa148 +#define mmPA_CL_VPORT_YOFFSET_10 0xa14e +#define mmPA_CL_VPORT_YOFFSET_11 0xa154 +#define mmPA_CL_VPORT_YOFFSET_12 0xa15a +#define mmPA_CL_VPORT_YOFFSET_13 0xa160 +#define mmPA_CL_VPORT_YOFFSET_14 0xa166 +#define mmPA_CL_VPORT_YOFFSET_15 0xa16c +#define mmPA_CL_VPORT_ZSCALE_1 0xa119 +#define mmPA_CL_VPORT_ZSCALE_2 0xa11f +#define mmPA_CL_VPORT_ZSCALE_3 0xa125 +#define mmPA_CL_VPORT_ZSCALE_4 0xa12b +#define mmPA_CL_VPORT_ZSCALE_5 0xa131 +#define mmPA_CL_VPORT_ZSCALE_6 0xa137 +#define mmPA_CL_VPORT_ZSCALE_7 0xa13d +#define mmPA_CL_VPORT_ZSCALE_8 0xa143 +#define mmPA_CL_VPORT_ZSCALE_9 0xa149 +#define mmPA_CL_VPORT_ZSCALE_10 0xa14f +#define mmPA_CL_VPORT_ZSCALE_11 0xa155 +#define mmPA_CL_VPORT_ZSCALE_12 0xa15b +#define mmPA_CL_VPORT_ZSCALE_13 0xa161 +#define mmPA_CL_VPORT_ZSCALE_14 0xa167 +#define mmPA_CL_VPORT_ZSCALE_15 0xa16d +#define mmPA_CL_VPORT_ZOFFSET_1 0xa11a +#define mmPA_CL_VPORT_ZOFFSET_2 0xa120 +#define mmPA_CL_VPORT_ZOFFSET_3 0xa126 +#define mmPA_CL_VPORT_ZOFFSET_4 0xa12c +#define mmPA_CL_VPORT_ZOFFSET_5 0xa132 +#define mmPA_CL_VPORT_ZOFFSET_6 0xa138 +#define mmPA_CL_VPORT_ZOFFSET_7 0xa13e +#define mmPA_CL_VPORT_ZOFFSET_8 0xa144 +#define mmPA_CL_VPORT_ZOFFSET_9 0xa14a +#define mmPA_CL_VPORT_ZOFFSET_10 0xa150 +#define mmPA_CL_VPORT_ZOFFSET_11 0xa156 +#define mmPA_CL_VPORT_ZOFFSET_12 0xa15c +#define mmPA_CL_VPORT_ZOFFSET_13 0xa162 +#define mmPA_CL_VPORT_ZOFFSET_14 0xa168 +#define mmPA_CL_VPORT_ZOFFSET_15 0xa16e +#define mmPA_CL_VTE_CNTL 0xa206 +#define mmPA_CL_VS_OUT_CNTL 0xa207 +#define mmPA_CL_NANINF_CNTL 0xa208 +#define mmPA_CL_CLIP_CNTL 0xa204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa +#define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc +#define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd +#define mmPA_CL_UCP_0_X 0xa16f +#define mmPA_CL_UCP_0_Y 0xa170 +#define mmPA_CL_UCP_0_Z 0xa171 +#define mmPA_CL_UCP_0_W 0xa172 +#define mmPA_CL_UCP_1_X 0xa173 +#define mmPA_CL_UCP_1_Y 0xa174 +#define mmPA_CL_UCP_1_Z 0xa175 +#define mmPA_CL_UCP_1_W 0xa176 +#define mmPA_CL_UCP_2_X 0xa177 +#define mmPA_CL_UCP_2_Y 0xa178 +#define mmPA_CL_UCP_2_Z 0xa179 +#define mmPA_CL_UCP_2_W 0xa17a +#define mmPA_CL_UCP_3_X 0xa17b +#define mmPA_CL_UCP_3_Y 0xa17c +#define mmPA_CL_UCP_3_Z 0xa17d +#define mmPA_CL_UCP_3_W 0xa17e +#define mmPA_CL_UCP_4_X 0xa17f +#define mmPA_CL_UCP_4_Y 0xa180 +#define mmPA_CL_UCP_4_Z 0xa181 +#define mmPA_CL_UCP_4_W 0xa182 +#define mmPA_CL_UCP_5_X 0xa183 +#define mmPA_CL_UCP_5_Y 0xa184 +#define mmPA_CL_UCP_5_Z 0xa185 +#define mmPA_CL_UCP_5_W 0xa186 +#define mmPA_CL_POINT_X_RAD 0xa1f5 +#define mmPA_CL_POINT_Y_RAD 0xa1f6 +#define mmPA_CL_POINT_SIZE 0xa1f7 +#define mmPA_CL_POINT_CULL_RAD 0xa1f8 +#define mmPA_CL_ENHANCE 0x2285 +#define mmPA_CL_RESET_DEBUG 0x2286 +#define mmPA_SU_VTX_CNTL 0xa2f9 +#define mmPA_SU_POINT_SIZE 0xa280 +#define mmPA_SU_POINT_MINMAX 0xa281 +#define mmPA_SU_LINE_CNTL 0xa282 +#define mmPA_SU_LINE_STIPPLE_CNTL 0xa209 +#define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a +#define mmPA_SU_PRIM_FILTER_CNTL 0xa20b +#define mmPA_SU_SC_MODE_CNTL 0xa205 +#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de +#define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3 +#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d +#define mmPA_SU_LINE_STIPPLE_VALUE 0xc280 +#define mmPA_SU_PERFCOUNTER0_SELECT 0xd900 +#define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901 +#define mmPA_SU_PERFCOUNTER1_SELECT 0xd902 +#define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903 +#define mmPA_SU_PERFCOUNTER2_SELECT 0xd904 +#define mmPA_SU_PERFCOUNTER3_SELECT 0xd905 +#define mmPA_SU_PERFCOUNTER0_LO 0xd100 +#define mmPA_SU_PERFCOUNTER0_HI 0xd101 +#define mmPA_SU_PERFCOUNTER1_LO 0xd102 +#define mmPA_SU_PERFCOUNTER1_HI 0xd103 +#define mmPA_SU_PERFCOUNTER2_LO 0xd104 +#define mmPA_SU_PERFCOUNTER2_HI 0xd105 +#define mmPA_SU_PERFCOUNTER3_LO 0xd106 +#define mmPA_SU_PERFCOUNTER3_HI 0xd107 +#define mmPA_SC_AA_CONFIG 0xa2f8 +#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e +#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d +#define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5 +#define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6 +#define mmPA_SC_CLIPRECT_0_TL 0xa084 +#define mmPA_SC_CLIPRECT_0_BR 0xa085 +#define mmPA_SC_CLIPRECT_1_TL 0xa086 +#define mmPA_SC_CLIPRECT_1_BR 0xa087 +#define mmPA_SC_CLIPRECT_2_TL 0xa088 +#define mmPA_SC_CLIPRECT_2_BR 0xa089 +#define mmPA_SC_CLIPRECT_3_TL 0xa08a +#define mmPA_SC_CLIPRECT_3_BR 0xa08b +#define mmPA_SC_CLIPRECT_RULE 0xa083 +#define mmPA_SC_EDGERULE 0xa08c +#define mmPA_SC_LINE_CNTL 0xa2f7 +#define mmPA_SC_LINE_STIPPLE 0xa283 +#define mmPA_SC_MODE_CNTL_0 0xa292 +#define mmPA_SC_MODE_CNTL_1 0xa293 +#define mmPA_SC_RASTER_CONFIG 0xa0d4 +#define mmPA_SC_RASTER_CONFIG_1 0xa0d5 +#define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6 +#define mmPA_SC_GENERIC_SCISSOR_TL 0xa090 +#define mmPA_SC_GENERIC_SCISSOR_BR 0xa091 +#define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c +#define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d +#define mmPA_SC_WINDOW_OFFSET 0xa080 +#define mmPA_SC_WINDOW_SCISSOR_TL 0xa081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0xa082 +#define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094 +#define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096 +#define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098 +#define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a +#define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c +#define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e +#define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0 +#define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2 +#define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4 +#define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6 +#define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8 +#define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa +#define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac +#define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae +#define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0 +#define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2 +#define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095 +#define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097 +#define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099 +#define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b +#define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d +#define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f +#define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1 +#define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3 +#define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5 +#define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7 +#define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9 +#define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab +#define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad +#define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af +#define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1 +#define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3 +#define mmPA_SC_VPORT_ZMIN_0 0xa0b4 +#define mmPA_SC_VPORT_ZMIN_1 0xa0b6 +#define mmPA_SC_VPORT_ZMIN_2 0xa0b8 +#define mmPA_SC_VPORT_ZMIN_3 0xa0ba +#define mmPA_SC_VPORT_ZMIN_4 0xa0bc +#define mmPA_SC_VPORT_ZMIN_5 0xa0be +#define mmPA_SC_VPORT_ZMIN_6 0xa0c0 +#define mmPA_SC_VPORT_ZMIN_7 0xa0c2 +#define mmPA_SC_VPORT_ZMIN_8 0xa0c4 +#define mmPA_SC_VPORT_ZMIN_9 0xa0c6 +#define mmPA_SC_VPORT_ZMIN_10 0xa0c8 +#define mmPA_SC_VPORT_ZMIN_11 0xa0ca +#define mmPA_SC_VPORT_ZMIN_12 0xa0cc +#define mmPA_SC_VPORT_ZMIN_13 0xa0ce +#define mmPA_SC_VPORT_ZMIN_14 0xa0d0 +#define mmPA_SC_VPORT_ZMIN_15 0xa0d2 +#define mmPA_SC_VPORT_ZMAX_0 0xa0b5 +#define mmPA_SC_VPORT_ZMAX_1 0xa0b7 +#define mmPA_SC_VPORT_ZMAX_2 0xa0b9 +#define mmPA_SC_VPORT_ZMAX_3 0xa0bb +#define mmPA_SC_VPORT_ZMAX_4 0xa0bd +#define mmPA_SC_VPORT_ZMAX_5 0xa0bf +#define mmPA_SC_VPORT_ZMAX_6 0xa0c1 +#define mmPA_SC_VPORT_ZMAX_7 0xa0c3 +#define mmPA_SC_VPORT_ZMAX_8 0xa0c5 +#define mmPA_SC_VPORT_ZMAX_9 0xa0c7 +#define mmPA_SC_VPORT_ZMAX_10 0xa0c9 +#define mmPA_SC_VPORT_ZMAX_11 0xa0cb +#define mmPA_SC_VPORT_ZMAX_12 0xa0cd +#define mmPA_SC_VPORT_ZMAX_13 0xa0cf +#define mmPA_SC_VPORT_ZMAX_14 0xa0d1 +#define mmPA_SC_VPORT_ZMAX_15 0xa0d3 +#define mmPA_SC_ENHANCE 0x22fc +#define mmPA_SC_FIFO_SIZE 0x22f3 +#define mmPA_SC_IF_FIFO_SIZE 0x22f5 +#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9 +#define mmPA_SC_LINE_STIPPLE_STATE 0xc281 +#define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284 +#define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285 +#define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286 +#define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b +#define mmPA_SC_PERFCOUNTER0_SELECT 0xd940 +#define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941 +#define mmPA_SC_PERFCOUNTER1_SELECT 0xd942 +#define mmPA_SC_PERFCOUNTER2_SELECT 0xd943 +#define mmPA_SC_PERFCOUNTER3_SELECT 0xd944 +#define mmPA_SC_PERFCOUNTER4_SELECT 0xd945 +#define mmPA_SC_PERFCOUNTER5_SELECT 0xd946 +#define mmPA_SC_PERFCOUNTER6_SELECT 0xd947 +#define mmPA_SC_PERFCOUNTER7_SELECT 0xd948 +#define mmPA_SC_PERFCOUNTER0_LO 0xd140 +#define mmPA_SC_PERFCOUNTER0_HI 0xd141 +#define mmPA_SC_PERFCOUNTER1_LO 0xd142 +#define mmPA_SC_PERFCOUNTER1_HI 0xd143 +#define mmPA_SC_PERFCOUNTER2_LO 0xd144 +#define mmPA_SC_PERFCOUNTER2_HI 0xd145 +#define mmPA_SC_PERFCOUNTER3_LO 0xd146 +#define mmPA_SC_PERFCOUNTER3_HI 0xd147 +#define mmPA_SC_PERFCOUNTER4_LO 0xd148 +#define mmPA_SC_PERFCOUNTER4_HI 0xd149 +#define mmPA_SC_PERFCOUNTER5_LO 0xd14a +#define mmPA_SC_PERFCOUNTER5_HI 0xd14b +#define mmPA_SC_PERFCOUNTER6_LO 0xd14c +#define mmPA_SC_PERFCOUNTER6_HI 0xd14d +#define mmPA_SC_PERFCOUNTER7_LO 0xd14e +#define mmPA_SC_PERFCOUNTER7_HI 0xd14f +#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0 +#define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1 +#define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2 +#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3 +#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8 +#define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9 +#define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa +#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab +#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac +#define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0 +#define mmPA_SC_TRAP_SCREEN_H 0xc2b1 +#define mmPA_SC_TRAP_SCREEN_V 0xc2b2 +#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3 +#define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4 +#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1 +#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2 +#define mmPA_CL_CNTL_STATUS 0x2284 +#define mmPA_SU_CNTL_STATUS 0x2294 +#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 +#define mmCGTT_PA_CLK_CTRL 0xf088 +#define mmCGTT_SC_CLK_CTRL 0xf089 +#define mmPA_SU_DEBUG_CNTL 0x2280 +#define mmPA_SU_DEBUG_DATA 0x2281 +#define mmPA_SC_DEBUG_CNTL 0x22f6 +#define mmPA_SC_DEBUG_DATA 0x22f7 +#define ixCLIPPER_DEBUG_REG00 0x0 +#define ixCLIPPER_DEBUG_REG01 0x1 +#define ixCLIPPER_DEBUG_REG02 0x2 +#define ixCLIPPER_DEBUG_REG03 0x3 +#define ixCLIPPER_DEBUG_REG04 0x4 +#define ixCLIPPER_DEBUG_REG05 0x5 +#define ixCLIPPER_DEBUG_REG06 0x6 +#define ixCLIPPER_DEBUG_REG07 0x7 +#define ixCLIPPER_DEBUG_REG08 0x8 +#define ixCLIPPER_DEBUG_REG09 0x9 +#define ixCLIPPER_DEBUG_REG10 0xa +#define ixCLIPPER_DEBUG_REG11 0xb +#define ixCLIPPER_DEBUG_REG12 0xc +#define ixCLIPPER_DEBUG_REG13 0xd +#define ixCLIPPER_DEBUG_REG14 0xe +#define ixCLIPPER_DEBUG_REG15 0xf +#define ixCLIPPER_DEBUG_REG16 0x10 +#define ixCLIPPER_DEBUG_REG17 0x11 +#define ixCLIPPER_DEBUG_REG18 0x12 +#define ixCLIPPER_DEBUG_REG19 0x13 +#define ixSXIFCCG_DEBUG_REG0 0x14 +#define ixSXIFCCG_DEBUG_REG1 0x15 +#define ixSXIFCCG_DEBUG_REG2 0x16 +#define ixSXIFCCG_DEBUG_REG3 0x17 +#define ixSETUP_DEBUG_REG0 0x18 +#define ixSETUP_DEBUG_REG1 0x19 +#define ixSETUP_DEBUG_REG2 0x1a +#define ixSETUP_DEBUG_REG3 0x1b +#define ixSETUP_DEBUG_REG4 0x1c +#define ixSETUP_DEBUG_REG5 0x1d +#define ixPA_SC_DEBUG_REG0 0x0 +#define ixPA_SC_DEBUG_REG1 0x1 +#define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00 +#define mmCOMPUTE_DIM_X 0x2e01 +#define mmCOMPUTE_DIM_Y 0x2e02 +#define mmCOMPUTE_DIM_Z 0x2e03 +#define mmCOMPUTE_START_X 0x2e04 +#define mmCOMPUTE_START_Y 0x2e05 +#define mmCOMPUTE_START_Z 0x2e06 +#define mmCOMPUTE_NUM_THREAD_X 0x2e07 +#define mmCOMPUTE_NUM_THREAD_Y 0x2e08 +#define mmCOMPUTE_NUM_THREAD_Z 0x2e09 +#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a +#define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b +#define mmCOMPUTE_PGM_LO 0x2e0c +#define mmCOMPUTE_PGM_HI 0x2e0d +#define mmCOMPUTE_TBA_LO 0x2e0e +#define mmCOMPUTE_TBA_HI 0x2e0f +#define mmCOMPUTE_TMA_LO 0x2e10 +#define mmCOMPUTE_TMA_HI 0x2e11 +#define mmCOMPUTE_PGM_RSRC1 0x2e12 +#define mmCOMPUTE_PGM_RSRC2 0x2e13 +#define mmCOMPUTE_VMID 0x2e14 +#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17 +#define mmCOMPUTE_TMPRING_SIZE 0x2e18 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a +#define mmCOMPUTE_RESTART_X 0x2e1b +#define mmCOMPUTE_RESTART_Y 0x2e1c +#define mmCOMPUTE_RESTART_Z 0x2e1d +#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e +#define mmCOMPUTE_MISC_RESERVED 0x2e1f +#define mmCOMPUTE_DISPATCH_ID 0x2e20 +#define mmCOMPUTE_THREADGROUP_ID 0x2e21 +#define mmCOMPUTE_RELAUNCH 0x2e22 +#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x2e23 +#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x2e24 +#define mmCOMPUTE_WAVE_RESTORE_CONTROL 0x2e25 +#define mmCOMPUTE_USER_DATA_0 0x2e40 +#define mmCOMPUTE_USER_DATA_1 0x2e41 +#define mmCOMPUTE_USER_DATA_2 0x2e42 +#define mmCOMPUTE_USER_DATA_3 0x2e43 +#define mmCOMPUTE_USER_DATA_4 0x2e44 +#define mmCOMPUTE_USER_DATA_5 0x2e45 +#define mmCOMPUTE_USER_DATA_6 0x2e46 +#define mmCOMPUTE_USER_DATA_7 0x2e47 +#define mmCOMPUTE_USER_DATA_8 0x2e48 +#define mmCOMPUTE_USER_DATA_9 0x2e49 +#define mmCOMPUTE_USER_DATA_10 0x2e4a +#define mmCOMPUTE_USER_DATA_11 0x2e4b +#define mmCOMPUTE_USER_DATA_12 0x2e4c +#define mmCOMPUTE_USER_DATA_13 0x2e4d +#define mmCOMPUTE_USER_DATA_14 0x2e4e +#define mmCOMPUTE_USER_DATA_15 0x2e4f +#define mmCOMPUTE_NOWHERE 0x2e7f +#define mmCSPRIV_CONNECT 0x0 +#define mmCSPRIV_THREAD_TRACE_TG0 0x1e +#define mmCSPRIV_THREAD_TRACE_TG1 0x1e +#define mmCSPRIV_THREAD_TRACE_TG2 0x1e +#define mmCSPRIV_THREAD_TRACE_TG3 0x1e +#define mmCSPRIV_THREAD_TRACE_EVENT 0x1f +#define mmRLC_CNTL 0xec00 +#define mmRLC_DEBUG_SELECT 0xec01 +#define mmRLC_DEBUG 0xec02 +#define mmRLC_MC_CNTL 0xec03 +#define mmRLC_STAT 0xec04 +#define mmRLC_SAFE_MODE 0xec05 +#define mmRLC_SOFT_RESET_GPU 0xec05 +#define mmRLC_MEM_SLP_CNTL 0xec06 +#define mmSMU_RLC_RESPONSE 0xec07 +#define mmRLC_RLCV_SAFE_MODE 0xec08 +#define mmRLC_SMU_SAFE_MODE 0xec09 +#define mmRLC_RLCV_COMMAND 0xec0a +#define mmRLC_PERFMON_CLK_CNTL 0xdcbf +#define mmRLC_PERFMON_CNTL 0xdcc0 +#define mmRLC_PERFCOUNTER0_SELECT 0xdcc1 +#define mmRLC_PERFCOUNTER1_SELECT 0xdcc2 +#define mmRLC_PERFCOUNTER0_LO 0xd480 +#define mmRLC_PERFCOUNTER1_LO 0xd482 +#define mmRLC_PERFCOUNTER0_HI 0xd481 +#define mmRLC_PERFCOUNTER1_HI 0xd483 +#define mmCGTT_RLC_CLK_CTRL 0xf0b8 +#define mmRLC_LB_CNTL 0xec19 +#define mmRLC_LB_CNTR_MAX 0xec12 +#define mmRLC_LB_CNTR_INIT 0xec1b +#define mmRLC_LOAD_BALANCE_CNTR 0xec1c +#define mmRLC_SAVE_AND_RESTORE_BASE 0xec1d +#define mmRLC_JUMP_TABLE_RESTORE 0xec1e +#define mmRLC_DRIVER_CPDMA_STATUS 0xec1e +#define mmRLC_PG_DELAY_2 0xec1f +#define mmRLC_GPM_DEBUG_SELECT 0xec20 +#define mmRLC_GPM_DEBUG 0xec21 +#define mmRLC_HYP_GPM_UCODE_ADDR 0xf83c +#define mmRLC_GPM_UCODE_ADDR 0xf83c +#define mmRLC_HYP_GPM_UCODE_DATA 0xf83d +#define mmRLC_GPM_UCODE_DATA 0xf83d +#define mmGPU_BIST_CONTROL 0xf835 +#define mmRLC_ROM_CNTL 0xf836 +#define mmRLC_GPU_CLOCK_COUNT_LSB 0xec24 +#define mmRLC_GPU_CLOCK_COUNT_MSB 0xec25 +#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0xec26 +#define mmRLC_UCODE_CNTL 0xec27 +#define mmRLC_GPM_STAT 0xec40 +#define mmRLC_GPU_CLOCK_32_RES_SEL 0xec41 +#define mmRLC_GPU_CLOCK_32 0xec42 +#define mmRLC_PG_CNTL 0xec43 +#define mmRLC_GPM_THREAD_PRIORITY 0xec44 +#define mmRLC_GPM_THREAD_ENABLE 0xec45 +#define mmRLC_GPM_VMID_THREAD0 0xec46 +#define mmRLC_GPM_VMID_THREAD1 0xec47 +#define mmRLC_CGTT_MGCG_OVERRIDE 0xec48 +#define mmRLC_CGCG_CGLS_CTRL 0xec49 +#define mmRLC_CGCG_RAMP_CTRL 0xec4a +#define mmRLC_DYN_PG_STATUS 0xec4b +#define mmRLC_DYN_PG_REQUEST 0xec4c +#define mmRLC_PG_DELAY 0xec4d +#define mmRLC_CU_STATUS 0xec4e +#define mmRLC_LB_INIT_CU_MASK 0xec4f +#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0xec50 +#define mmRLC_LB_PARAMS 0xec51 +#define mmRLC_THREAD1_DELAY 0xec52 +#define mmRLC_PG_ALWAYS_ON_CU_MASK 0xec53 +#define mmRLC_MAX_PG_CU 0xec54 +#define mmRLC_AUTO_PG_CTRL 0xec55 +#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0xec56 +#define mmRLC_SMU_PG_CTRL 0xec57 +#define mmRLC_SMU_PG_WAKE_UP_CTRL 0xec58 +#define mmRLC_SERDES_RD_MASTER_INDEX 0xec59 +#define mmRLC_SERDES_RD_DATA_0 0xec5a +#define mmRLC_SERDES_RD_DATA_1 0xec5b +#define mmRLC_SERDES_RD_DATA_2 0xec5c +#define mmRLC_SERDES_WR_CU_MASTER_MASK 0xec5d +#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0xec5e +#define mmRLC_SERDES_WR_CTRL 0xec5f +#define mmRLC_SERDES_WR_DATA 0xec60 +#define mmRLC_SERDES_CU_MASTER_BUSY 0xec61 +#define mmRLC_SERDES_NONCU_MASTER_BUSY 0xec62 +#define mmRLC_GPM_GENERAL_0 0xec63 +#define mmRLC_GPM_GENERAL_1 0xec64 +#define mmRLC_GPM_GENERAL_2 0xec65 +#define mmRLC_GPM_GENERAL_3 0xec66 +#define mmRLC_GPM_GENERAL_4 0xec67 +#define mmRLC_GPM_GENERAL_5 0xec68 +#define mmRLC_GPM_GENERAL_6 0xec69 +#define mmRLC_GPM_GENERAL_7 0xec6a +#define mmRLC_GPM_CU_PD_TIMEOUT 0xec6b +#define mmRLC_GPM_SCRATCH_ADDR 0xec6c +#define mmRLC_GPM_SCRATCH_DATA 0xec6d +#define mmRLC_STATIC_PG_STATUS 0xec6e +#define mmRLC_GPM_PERF_COUNT_0 0xec6f +#define mmRLC_GPM_PERF_COUNT_1 0xec70 +#define mmRLC_GPR_REG1 0xec79 +#define mmRLC_GPR_REG2 0xec7a +#define mmRLC_MGCG_CTRL 0xec1a +#define mmRLC_GPM_THREAD_RESET 0xec28 +#define mmRLC_SPM_VMID 0xec71 +#define mmRLC_SPM_INT_CNTL 0xec72 +#define mmRLC_SPM_INT_STATUS 0xec73 +#define mmRLC_SPM_DEBUG_SELECT 0xec74 +#define mmRLC_SPM_DEBUG 0xec75 +#define mmRLC_GPM_LOG_ADDR 0xec76 +#define mmRLC_SMU_MESSAGE 0xec76 +#define mmRLC_GPM_LOG_SIZE 0xec77 +#define mmRLC_GPM_LOG_CONT 0xec7b +#define mmRLC_PG_DELAY_3 0xec78 +#define mmRLC_GPM_INT_DISABLE_TH0 0xec7c +#define mmRLC_GPM_INT_DISABLE_TH1 0xec7d +#define mmRLC_GPM_INT_FORCE_TH0 0xec7e +#define mmRLC_GPM_INT_FORCE_TH1 0xec7f +#define mmRLC_SRM_CNTL 0xec80 +#define mmRLC_SRM_DEBUG_SELECT 0xec81 +#define mmRLC_SRM_DEBUG 0xec82 +#define mmRLC_SRM_ARAM_ADDR 0xec83 +#define mmRLC_SRM_ARAM_DATA 0xec84 +#define mmRLC_SRM_DRAM_ADDR 0xec85 +#define mmRLC_SRM_DRAM_DATA 0xec86 +#define mmRLC_SRM_GPM_COMMAND 0xec87 +#define mmRLC_SRM_GPM_COMMAND_STATUS 0xec88 +#define mmRLC_SRM_RLCV_COMMAND 0xec89 +#define mmRLC_SRM_RLCV_COMMAND_STATUS 0xec8a +#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b +#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0xec8c +#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0xec8d +#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0xec8e +#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0xec8f +#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0xec90 +#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0xec91 +#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0xec92 +#define mmRLC_SRM_INDEX_CNTL_DATA_0 0xec93 +#define mmRLC_SRM_INDEX_CNTL_DATA_1 0xec94 +#define mmRLC_SRM_INDEX_CNTL_DATA_2 0xec95 +#define mmRLC_SRM_INDEX_CNTL_DATA_3 0xec96 +#define mmRLC_SRM_INDEX_CNTL_DATA_4 0xec97 +#define mmRLC_SRM_INDEX_CNTL_DATA_5 0xec98 +#define mmRLC_SRM_INDEX_CNTL_DATA_6 0xec99 +#define mmRLC_SRM_INDEX_CNTL_DATA_7 0xec9a +#define mmRLC_SRM_STAT 0xec9b +#define mmRLC_SRM_GPM_ABORT 0xec9c +#define mmRLC_CSIB_ADDR_LO 0xeca2 +#define mmRLC_CSIB_ADDR_HI 0xeca3 +#define mmRLC_CSIB_LENGTH 0xeca4 +#define mmRLC_CP_RESPONSE0 0xeca5 +#define mmRLC_CP_RESPONSE1 0xeca6 +#define mmRLC_CP_RESPONSE2 0xeca7 +#define mmRLC_CP_RESPONSE3 0xeca8 +#define mmRLC_SMU_COMMAND 0xeca9 +#define mmRLC_CP_SCHEDULERS 0xecaa +#define mmRLC_SPM_PERFMON_CNTL 0xdc80 +#define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81 +#define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82 +#define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83 +#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84 +#define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85 +#define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86 +#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87 +#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88 +#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89 +#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a +#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b +#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c +#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d +#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e +#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90 +#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91 +#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92 +#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93 +#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94 +#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95 +#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96 +#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97 +#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98 +#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a +#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b +#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c +#define mmRLC_SPM_RING_RDPTR 0xdc9d +#define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e +#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY 0xdc9f +#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY 0xdca0 +#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY 0xdca1 +#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY 0xdca2 +#define mmRLC_GPU_IOV_VF_ENABLE 0xfb00 +#define mmRLC_GPU_IOV_CFG_REG1 0xfb01 +#define mmRLC_GPU_IOV_CFG_REG2 0xfb02 +#define mmRLC_GPU_IOV_CFG_REG6 0xfb06 +#define mmRLC_GPU_IOV_CFG_REG8 0xfb08 +#define mmRLC_GPU_IOV_CFG_REG9 0xfb21 +#define mmRLC_GPU_IOV_CFG_REG10 0xfb22 +#define mmRLC_GPU_IOV_CFG_REG11 0xfb23 +#define mmRLC_GPU_IOV_CFG_REG12 0xfb24 +#define mmRLC_GPU_IOV_CFG_REG13 0xfb25 +#define mmRLC_GPU_IOV_CFG_REG14 0xfb26 +#define mmRLC_GPU_IOV_CFG_REG15 0xfb27 +#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0xfb40 +#define mmRLC_GPM_VMID_THREAD2 0xfb41 +#define mmRLC_GPU_IOV_UCODE_ADDR 0xfb42 +#define mmRLC_GPU_IOV_UCODE_DATA 0xfb43 +#define mmRLC_GPU_IOV_SCRATCH_ADDR 0xfb44 +#define mmRLC_GPU_IOV_SCRATCH_DATA 0xfb45 +#define mmRLC_GPU_IOV_F32_CNTL 0xfb46 +#define mmRLC_GPU_IOV_F32_RESET 0xfb47 +#define mmRLC_GPU_IOV_SDMA0_STATUS 0xfb48 +#define mmRLC_GPU_IOV_SDMA1_STATUS 0xfb49 +#define mmRLC_GPU_IOV_SMU_RESPONSE 0xfb4a +#define mmRLC_GPU_IOV_VIRT_RESET_REQ 0xfb4c +#define mmRLC_GPU_IOV_RLC_RESPONSE 0xfb4d +#define mmRLC_GPU_IOV_INT_DISABLE 0xfb4e +#define mmRLC_GPU_IOV_INT_FORCE 0xfb4f +#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0xfb50 +#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0xfb51 +#define mmRLC_GPU_IOV_SCH_0 0xfb52 +#define mmRLC_GPU_IOV_SCH_1 0xfb53 +#define mmRLC_GPU_IOV_SCH_2 0xfb54 +#define mmRLC_GPU_IOV_SCH_3 0xfb55 +#define mmRLC_GPU_IOV_SCH_INT 0xfb56 +#define mmSPI_PS_INPUT_CNTL_0 0xa191 +#define mmSPI_PS_INPUT_CNTL_1 0xa192 +#define mmSPI_PS_INPUT_CNTL_2 0xa193 +#define mmSPI_PS_INPUT_CNTL_3 0xa194 +#define mmSPI_PS_INPUT_CNTL_4 0xa195 +#define mmSPI_PS_INPUT_CNTL_5 0xa196 +#define mmSPI_PS_INPUT_CNTL_6 0xa197 +#define mmSPI_PS_INPUT_CNTL_7 0xa198 +#define mmSPI_PS_INPUT_CNTL_8 0xa199 +#define mmSPI_PS_INPUT_CNTL_9 0xa19a +#define mmSPI_PS_INPUT_CNTL_10 0xa19b +#define mmSPI_PS_INPUT_CNTL_11 0xa19c +#define mmSPI_PS_INPUT_CNTL_12 0xa19d +#define mmSPI_PS_INPUT_CNTL_13 0xa19e +#define mmSPI_PS_INPUT_CNTL_14 0xa19f +#define mmSPI_PS_INPUT_CNTL_15 0xa1a0 +#define mmSPI_PS_INPUT_CNTL_16 0xa1a1 +#define mmSPI_PS_INPUT_CNTL_17 0xa1a2 +#define mmSPI_PS_INPUT_CNTL_18 0xa1a3 +#define mmSPI_PS_INPUT_CNTL_19 0xa1a4 +#define mmSPI_PS_INPUT_CNTL_20 0xa1a5 +#define mmSPI_PS_INPUT_CNTL_21 0xa1a6 +#define mmSPI_PS_INPUT_CNTL_22 0xa1a7 +#define mmSPI_PS_INPUT_CNTL_23 0xa1a8 +#define mmSPI_PS_INPUT_CNTL_24 0xa1a9 +#define mmSPI_PS_INPUT_CNTL_25 0xa1aa +#define mmSPI_PS_INPUT_CNTL_26 0xa1ab +#define mmSPI_PS_INPUT_CNTL_27 0xa1ac +#define mmSPI_PS_INPUT_CNTL_28 0xa1ad +#define mmSPI_PS_INPUT_CNTL_29 0xa1ae +#define mmSPI_PS_INPUT_CNTL_30 0xa1af +#define mmSPI_PS_INPUT_CNTL_31 0xa1b0 +#define mmSPI_VS_OUT_CONFIG 0xa1b1 +#define mmSPI_PS_INPUT_ENA 0xa1b3 +#define mmSPI_PS_INPUT_ADDR 0xa1b4 +#define mmSPI_INTERP_CONTROL_0 0xa1b5 +#define mmSPI_PS_IN_CONTROL 0xa1b6 +#define mmSPI_BARYC_CNTL 0xa1b8 +#define mmSPI_TMPRING_SIZE 0xa1ba +#define mmSPI_SHADER_POS_FORMAT 0xa1c3 +#define mmSPI_SHADER_Z_FORMAT 0xa1c4 +#define mmSPI_SHADER_COL_FORMAT 0xa1c5 +#define mmSPI_ARB_PRIORITY 0x31c0 +#define mmSPI_ARB_CYCLES_0 0x31c1 +#define mmSPI_ARB_CYCLES_1 0x31c2 +#define mmSPI_CDBG_SYS_GFX 0x31c3 +#define mmSPI_CDBG_SYS_HP3D 0x31c4 +#define mmSPI_CDBG_SYS_CS0 0x31c5 +#define mmSPI_CDBG_SYS_CS1 0x31c6 +#define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 +#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8 +#define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9 +#define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca +#define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb +#define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc +#define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd +#define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce +#define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf +#define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0 +#define mmSPI_GDBG_WAVE_CNTL 0x31d1 +#define mmSPI_GDBG_TRAP_CONFIG 0x31d2 +#define mmSPI_GDBG_TRAP_MASK 0x31d3 +#define mmSPI_GDBG_TBA_LO 0x31d4 +#define mmSPI_GDBG_TBA_HI 0x31d5 +#define mmSPI_GDBG_TMA_LO 0x31d6 +#define mmSPI_GDBG_TMA_HI 0x31d7 +#define mmSPI_GDBG_TRAP_DATA0 0x31d8 +#define mmSPI_GDBG_TRAP_DATA1 0x31d9 +#define mmSPI_RESET_DEBUG 0x31da +#define mmSPI_COMPUTE_QUEUE_RESET 0x31db +#define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc +#define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd +#define mmSPI_RESOURCE_RESERVE_CU_2 0x31de +#define mmSPI_RESOURCE_RESERVE_CU_3 0x31df +#define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0 +#define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1 +#define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2 +#define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3 +#define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4 +#define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5 +#define mmSPI_RESOURCE_RESERVE_CU_10 0x31f0 +#define mmSPI_RESOURCE_RESERVE_CU_11 0x31f1 +#define mmSPI_RESOURCE_RESERVE_CU_12 0x31f4 +#define mmSPI_RESOURCE_RESERVE_CU_13 0x31f5 +#define mmSPI_RESOURCE_RESERVE_CU_14 0x31f6 +#define mmSPI_RESOURCE_RESERVE_CU_15 0x31f7 +#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6 +#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7 +#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8 +#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9 +#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea +#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb +#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec +#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed +#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee +#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef +#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x31f2 +#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x31f3 +#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x31f8 +#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x31f9 +#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x31fa +#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x31fb +#define mmSPI_COMPUTE_WF_CTX_SAVE 0x31fc +#define mmSPI_PS_MAX_WAVE_ID 0x243a +#define mmSPI_START_PHASE 0x243b +#define mmSPI_GFX_CNTL 0x243c +#define mmSPI_CONFIG_CNTL 0x2440 +#define mmSPI_DEBUG_CNTL 0x2441 +#define mmSPI_DEBUG_READ 0x2442 +#define mmSPI_DSM_CNTL 0x2443 +#define mmSPI_EDC_CNT 0x2444 +#define mmSPI_PERFCOUNTER0_SELECT 0xd980 +#define mmSPI_PERFCOUNTER1_SELECT 0xd981 +#define mmSPI_PERFCOUNTER2_SELECT 0xd982 +#define mmSPI_PERFCOUNTER3_SELECT 0xd983 +#define mmSPI_PERFCOUNTER0_SELECT1 0xd984 +#define mmSPI_PERFCOUNTER1_SELECT1 0xd985 +#define mmSPI_PERFCOUNTER2_SELECT1 0xd986 +#define mmSPI_PERFCOUNTER3_SELECT1 0xd987 +#define mmSPI_PERFCOUNTER4_SELECT 0xd988 +#define mmSPI_PERFCOUNTER5_SELECT 0xd989 +#define mmSPI_PERFCOUNTER_BINS 0xd98a +#define mmSPI_PERFCOUNTER0_HI 0xd180 +#define mmSPI_PERFCOUNTER0_LO 0xd181 +#define mmSPI_PERFCOUNTER1_HI 0xd182 +#define mmSPI_PERFCOUNTER1_LO 0xd183 +#define mmSPI_PERFCOUNTER2_HI 0xd184 +#define mmSPI_PERFCOUNTER2_LO 0xd185 +#define mmSPI_PERFCOUNTER3_HI 0xd186 +#define mmSPI_PERFCOUNTER3_LO 0xd187 +#define mmSPI_PERFCOUNTER4_HI 0xd188 +#define mmSPI_PERFCOUNTER4_LO 0xd189 +#define mmSPI_PERFCOUNTER5_HI 0xd18a +#define mmSPI_PERFCOUNTER5_LO 0xd18b +#define mmSPI_CONFIG_CNTL_1 0x244f +#define mmSPI_DEBUG_BUSY 0x2450 +#define mmSPI_CONFIG_CNTL_2 0x2451 +#define mmCGTS_SM_CTRL_REG 0xf000 +#define mmCGTS_RD_CTRL_REG 0xf001 +#define mmCGTS_RD_REG 0xf002 +#define mmCGTS_TCC_DISABLE 0xf003 +#define mmCGTS_USER_TCC_DISABLE 0xf004 +#define mmCGTS_CU0_SP0_CTRL_REG 0xf008 +#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009 +#define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a +#define mmCGTS_CU0_SP1_CTRL_REG 0xf00b +#define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c +#define mmCGTS_CU1_SP0_CTRL_REG 0xf00d +#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e +#define mmCGTS_CU1_TA_CTRL_REG 0xf00f +#define mmCGTS_CU1_SP1_CTRL_REG 0xf010 +#define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011 +#define mmCGTS_CU2_SP0_CTRL_REG 0xf012 +#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013 +#define mmCGTS_CU2_TA_CTRL_REG 0xf014 +#define mmCGTS_CU2_SP1_CTRL_REG 0xf015 +#define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016 +#define mmCGTS_CU3_SP0_CTRL_REG 0xf017 +#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018 +#define mmCGTS_CU3_TA_CTRL_REG 0xf019 +#define mmCGTS_CU3_SP1_CTRL_REG 0xf01a +#define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b +#define mmCGTS_CU4_SP0_CTRL_REG 0xf01c +#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d +#define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e +#define mmCGTS_CU4_SP1_CTRL_REG 0xf01f +#define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020 +#define mmCGTS_CU5_SP0_CTRL_REG 0xf021 +#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022 +#define mmCGTS_CU5_TA_CTRL_REG 0xf023 +#define mmCGTS_CU5_SP1_CTRL_REG 0xf024 +#define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025 +#define mmCGTS_CU6_SP0_CTRL_REG 0xf026 +#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027 +#define mmCGTS_CU6_TA_CTRL_REG 0xf028 +#define mmCGTS_CU6_SP1_CTRL_REG 0xf029 +#define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a +#define mmCGTS_CU7_SP0_CTRL_REG 0xf02b +#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c +#define mmCGTS_CU7_TA_CTRL_REG 0xf02d +#define mmCGTS_CU7_SP1_CTRL_REG 0xf02e +#define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f +#define mmCGTS_CU8_SP0_CTRL_REG 0xf030 +#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031 +#define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032 +#define mmCGTS_CU8_SP1_CTRL_REG 0xf033 +#define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034 +#define mmCGTS_CU9_SP0_CTRL_REG 0xf035 +#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036 +#define mmCGTS_CU9_TA_CTRL_REG 0xf037 +#define mmCGTS_CU9_SP1_CTRL_REG 0xf038 +#define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039 +#define mmCGTS_CU10_SP0_CTRL_REG 0xf03a +#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b +#define mmCGTS_CU10_TA_CTRL_REG 0xf03c +#define mmCGTS_CU10_SP1_CTRL_REG 0xf03d +#define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e +#define mmCGTS_CU11_SP0_CTRL_REG 0xf03f +#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040 +#define mmCGTS_CU11_TA_CTRL_REG 0xf041 +#define mmCGTS_CU11_SP1_CTRL_REG 0xf042 +#define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043 +#define mmCGTS_CU12_SP0_CTRL_REG 0xf044 +#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045 +#define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046 +#define mmCGTS_CU12_SP1_CTRL_REG 0xf047 +#define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048 +#define mmCGTS_CU13_SP0_CTRL_REG 0xf049 +#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a +#define mmCGTS_CU13_TA_CTRL_REG 0xf04b +#define mmCGTS_CU13_SP1_CTRL_REG 0xf04c +#define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d +#define mmCGTS_CU14_SP0_CTRL_REG 0xf04e +#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f +#define mmCGTS_CU14_TA_CTRL_REG 0xf050 +#define mmCGTS_CU14_SP1_CTRL_REG 0xf051 +#define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052 +#define mmCGTS_CU15_SP0_CTRL_REG 0xf053 +#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 +#define mmCGTS_CU15_TA_CTRL_REG 0xf055 +#define mmCGTS_CU15_SP1_CTRL_REG 0xf056 +#define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057 +#define mmCGTT_SPI_CLK_CTRL 0xf080 +#define mmCGTT_PC_CLK_CTRL 0xf081 +#define mmCGTT_BCI_CLK_CTRL 0xf082 +#define mmSPI_WF_LIFETIME_CNTL 0x24aa +#define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab +#define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac +#define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad +#define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae +#define mmSPI_WF_LIFETIME_LIMIT_4 0x24af +#define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0 +#define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1 +#define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2 +#define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3 +#define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4 +#define mmSPI_WF_LIFETIME_STATUS_0 0x24b5 +#define mmSPI_WF_LIFETIME_STATUS_1 0x24b6 +#define mmSPI_WF_LIFETIME_STATUS_2 0x24b7 +#define mmSPI_WF_LIFETIME_STATUS_3 0x24b8 +#define mmSPI_WF_LIFETIME_STATUS_4 0x24b9 +#define mmSPI_WF_LIFETIME_STATUS_5 0x24ba +#define mmSPI_WF_LIFETIME_STATUS_6 0x24bb +#define mmSPI_WF_LIFETIME_STATUS_7 0x24bc +#define mmSPI_WF_LIFETIME_STATUS_8 0x24bd +#define mmSPI_WF_LIFETIME_STATUS_9 0x24be +#define mmSPI_WF_LIFETIME_STATUS_10 0x24bf +#define mmSPI_WF_LIFETIME_STATUS_11 0x24c0 +#define mmSPI_WF_LIFETIME_STATUS_12 0x24c1 +#define mmSPI_WF_LIFETIME_STATUS_13 0x24c2 +#define mmSPI_WF_LIFETIME_STATUS_14 0x24c3 +#define mmSPI_WF_LIFETIME_STATUS_15 0x24c4 +#define mmSPI_WF_LIFETIME_STATUS_16 0x24c5 +#define mmSPI_WF_LIFETIME_STATUS_17 0x24c6 +#define mmSPI_WF_LIFETIME_STATUS_18 0x24c7 +#define mmSPI_WF_LIFETIME_STATUS_19 0x24c8 +#define mmSPI_WF_LIFETIME_STATUS_20 0x24c9 +#define mmSPI_WF_LIFETIME_DEBUG 0x24ca +#define mmSPI_SLAVE_DEBUG_BUSY 0x24d3 +#define mmSPI_LB_CTR_CTRL 0x24d4 +#define mmSPI_LB_CU_MASK 0x24d5 +#define mmSPI_LB_DATA_REG 0x24d6 +#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7 +#define mmSPI_GDS_CREDITS 0x24d8 +#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9 +#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da +#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db +#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc +#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd +#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de +#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df +#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3 +#define mmBCI_DEBUG_READ 0x24eb +#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec +#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed +#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee +#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef +#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0 +#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1 +#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2 +#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3 +#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4 +#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5 +#define mmSPI_SHADER_TBA_LO_PS 0x2c00 +#define mmSPI_SHADER_TBA_HI_PS 0x2c01 +#define mmSPI_SHADER_TMA_LO_PS 0x2c02 +#define mmSPI_SHADER_TMA_HI_PS 0x2c03 +#define mmSPI_SHADER_PGM_LO_PS 0x2c08 +#define mmSPI_SHADER_PGM_HI_PS 0x2c09 +#define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a +#define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b +#define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07 +#define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c +#define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d +#define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e +#define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f +#define mmSPI_SHADER_USER_DATA_PS_4 0x2c10 +#define mmSPI_SHADER_USER_DATA_PS_5 0x2c11 +#define mmSPI_SHADER_USER_DATA_PS_6 0x2c12 +#define mmSPI_SHADER_USER_DATA_PS_7 0x2c13 +#define mmSPI_SHADER_USER_DATA_PS_8 0x2c14 +#define mmSPI_SHADER_USER_DATA_PS_9 0x2c15 +#define mmSPI_SHADER_USER_DATA_PS_10 0x2c16 +#define mmSPI_SHADER_USER_DATA_PS_11 0x2c17 +#define mmSPI_SHADER_USER_DATA_PS_12 0x2c18 +#define mmSPI_SHADER_USER_DATA_PS_13 0x2c19 +#define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a +#define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b +#define mmSPI_SHADER_TBA_LO_VS 0x2c40 +#define mmSPI_SHADER_TBA_HI_VS 0x2c41 +#define mmSPI_SHADER_TMA_LO_VS 0x2c42 +#define mmSPI_SHADER_TMA_HI_VS 0x2c43 +#define mmSPI_SHADER_PGM_LO_VS 0x2c48 +#define mmSPI_SHADER_PGM_HI_VS 0x2c49 +#define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a +#define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b +#define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46 +#define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47 +#define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c +#define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d +#define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e +#define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f +#define mmSPI_SHADER_USER_DATA_VS_4 0x2c50 +#define mmSPI_SHADER_USER_DATA_VS_5 0x2c51 +#define mmSPI_SHADER_USER_DATA_VS_6 0x2c52 +#define mmSPI_SHADER_USER_DATA_VS_7 0x2c53 +#define mmSPI_SHADER_USER_DATA_VS_8 0x2c54 +#define mmSPI_SHADER_USER_DATA_VS_9 0x2c55 +#define mmSPI_SHADER_USER_DATA_VS_10 0x2c56 +#define mmSPI_SHADER_USER_DATA_VS_11 0x2c57 +#define mmSPI_SHADER_USER_DATA_VS_12 0x2c58 +#define mmSPI_SHADER_USER_DATA_VS_13 0x2c59 +#define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a +#define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b +#define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c +#define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d +#define mmSPI_SHADER_TBA_LO_GS 0x2c80 +#define mmSPI_SHADER_TBA_HI_GS 0x2c81 +#define mmSPI_SHADER_TMA_LO_GS 0x2c82 +#define mmSPI_SHADER_TMA_HI_GS 0x2c83 +#define mmSPI_SHADER_PGM_LO_GS 0x2c88 +#define mmSPI_SHADER_PGM_HI_GS 0x2c89 +#define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a +#define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b +#define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87 +#define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c +#define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d +#define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e +#define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f +#define mmSPI_SHADER_USER_DATA_GS_4 0x2c90 +#define mmSPI_SHADER_USER_DATA_GS_5 0x2c91 +#define mmSPI_SHADER_USER_DATA_GS_6 0x2c92 +#define mmSPI_SHADER_USER_DATA_GS_7 0x2c93 +#define mmSPI_SHADER_USER_DATA_GS_8 0x2c94 +#define mmSPI_SHADER_USER_DATA_GS_9 0x2c95 +#define mmSPI_SHADER_USER_DATA_GS_10 0x2c96 +#define mmSPI_SHADER_USER_DATA_GS_11 0x2c97 +#define mmSPI_SHADER_USER_DATA_GS_12 0x2c98 +#define mmSPI_SHADER_USER_DATA_GS_13 0x2c99 +#define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a +#define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b +#define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc +#define mmSPI_SHADER_TBA_LO_ES 0x2cc0 +#define mmSPI_SHADER_TBA_HI_ES 0x2cc1 +#define mmSPI_SHADER_TMA_LO_ES 0x2cc2 +#define mmSPI_SHADER_TMA_HI_ES 0x2cc3 +#define mmSPI_SHADER_PGM_LO_ES 0x2cc8 +#define mmSPI_SHADER_PGM_HI_ES 0x2cc9 +#define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca +#define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb +#define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7 +#define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc +#define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd +#define mmSPI_SHADER_USER_DATA_ES_2 0x2cce +#define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf +#define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0 +#define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1 +#define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2 +#define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3 +#define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4 +#define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5 +#define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6 +#define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7 +#define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8 +#define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9 +#define mmSPI_SHADER_USER_DATA_ES_14 0x2cda +#define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb +#define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd +#define mmSPI_SHADER_TBA_LO_HS 0x2d00 +#define mmSPI_SHADER_TBA_HI_HS 0x2d01 +#define mmSPI_SHADER_TMA_LO_HS 0x2d02 +#define mmSPI_SHADER_TMA_HI_HS 0x2d03 +#define mmSPI_SHADER_PGM_LO_HS 0x2d08 +#define mmSPI_SHADER_PGM_HI_HS 0x2d09 +#define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a +#define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b +#define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07 +#define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c +#define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d +#define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e +#define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f +#define mmSPI_SHADER_USER_DATA_HS_4 0x2d10 +#define mmSPI_SHADER_USER_DATA_HS_5 0x2d11 +#define mmSPI_SHADER_USER_DATA_HS_6 0x2d12 +#define mmSPI_SHADER_USER_DATA_HS_7 0x2d13 +#define mmSPI_SHADER_USER_DATA_HS_8 0x2d14 +#define mmSPI_SHADER_USER_DATA_HS_9 0x2d15 +#define mmSPI_SHADER_USER_DATA_HS_10 0x2d16 +#define mmSPI_SHADER_USER_DATA_HS_11 0x2d17 +#define mmSPI_SHADER_USER_DATA_HS_12 0x2d18 +#define mmSPI_SHADER_USER_DATA_HS_13 0x2d19 +#define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a +#define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b +#define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d +#define mmSPI_SHADER_TBA_LO_LS 0x2d40 +#define mmSPI_SHADER_TBA_HI_LS 0x2d41 +#define mmSPI_SHADER_TMA_LO_LS 0x2d42 +#define mmSPI_SHADER_TMA_HI_LS 0x2d43 +#define mmSPI_SHADER_PGM_LO_LS 0x2d48 +#define mmSPI_SHADER_PGM_HI_LS 0x2d49 +#define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a +#define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b +#define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47 +#define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c +#define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d +#define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e +#define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f +#define mmSPI_SHADER_USER_DATA_LS_4 0x2d50 +#define mmSPI_SHADER_USER_DATA_LS_5 0x2d51 +#define mmSPI_SHADER_USER_DATA_LS_6 0x2d52 +#define mmSPI_SHADER_USER_DATA_LS_7 0x2d53 +#define mmSPI_SHADER_USER_DATA_LS_8 0x2d54 +#define mmSPI_SHADER_USER_DATA_LS_9 0x2d55 +#define mmSPI_SHADER_USER_DATA_LS_10 0x2d56 +#define mmSPI_SHADER_USER_DATA_LS_11 0x2d57 +#define mmSPI_SHADER_USER_DATA_LS_12 0x2d58 +#define mmSPI_SHADER_USER_DATA_LS_13 0x2d59 +#define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a +#define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b +#define mmSQ_CONFIG 0x2300 +#define mmSQC_CONFIG 0x2301 +#define mmSQC_CACHES 0xc348 +#define mmSQC_WRITEBACK 0xc349 +#define mmSQC_DSM_CNTL 0x230f +#define mmSQ_RANDOM_WAVE_PRI 0x2303 +#define mmSQ_REG_CREDITS 0x2304 +#define mmSQ_FIFO_SIZES 0x2305 +#define mmSQ_DSM_CNTL 0x2306 +#define mmCC_GC_SHADER_RATE_CONFIG 0x2312 +#define mmGC_USER_SHADER_RATE_CONFIG 0x2313 +#define mmSQ_INTERRUPT_AUTO_MASK 0x2314 +#define mmSQ_INTERRUPT_MSG_CTRL 0x2315 +#define mmSQ_PERFCOUNTER_CTRL 0xd9e0 +#define mmSQ_PERFCOUNTER_MASK 0xd9e1 +#define mmSQ_PERFCOUNTER_CTRL2 0xd9e2 +#define mmCC_SQC_BANK_DISABLE 0x2307 +#define mmUSER_SQC_BANK_DISABLE 0x2308 +#define mmSQ_PERFCOUNTER0_LO 0xd1c0 +#define mmSQ_PERFCOUNTER1_LO 0xd1c2 +#define mmSQ_PERFCOUNTER2_LO 0xd1c4 +#define mmSQ_PERFCOUNTER3_LO 0xd1c6 +#define mmSQ_PERFCOUNTER4_LO 0xd1c8 +#define mmSQ_PERFCOUNTER5_LO 0xd1ca +#define mmSQ_PERFCOUNTER6_LO 0xd1cc +#define mmSQ_PERFCOUNTER7_LO 0xd1ce +#define mmSQ_PERFCOUNTER8_LO 0xd1d0 +#define mmSQ_PERFCOUNTER9_LO 0xd1d2 +#define mmSQ_PERFCOUNTER10_LO 0xd1d4 +#define mmSQ_PERFCOUNTER11_LO 0xd1d6 +#define mmSQ_PERFCOUNTER12_LO 0xd1d8 +#define mmSQ_PERFCOUNTER13_LO 0xd1da +#define mmSQ_PERFCOUNTER14_LO 0xd1dc +#define mmSQ_PERFCOUNTER15_LO 0xd1de +#define mmSQ_PERFCOUNTER0_HI 0xd1c1 +#define mmSQ_PERFCOUNTER1_HI 0xd1c3 +#define mmSQ_PERFCOUNTER2_HI 0xd1c5 +#define mmSQ_PERFCOUNTER3_HI 0xd1c7 +#define mmSQ_PERFCOUNTER4_HI 0xd1c9 +#define mmSQ_PERFCOUNTER5_HI 0xd1cb +#define mmSQ_PERFCOUNTER6_HI 0xd1cd +#define mmSQ_PERFCOUNTER7_HI 0xd1cf +#define mmSQ_PERFCOUNTER8_HI 0xd1d1 +#define mmSQ_PERFCOUNTER9_HI 0xd1d3 +#define mmSQ_PERFCOUNTER10_HI 0xd1d5 +#define mmSQ_PERFCOUNTER11_HI 0xd1d7 +#define mmSQ_PERFCOUNTER12_HI 0xd1d9 +#define mmSQ_PERFCOUNTER13_HI 0xd1db +#define mmSQ_PERFCOUNTER14_HI 0xd1dd +#define mmSQ_PERFCOUNTER15_HI 0xd1df +#define mmSQ_PERFCOUNTER0_SELECT 0xd9c0 +#define mmSQ_PERFCOUNTER1_SELECT 0xd9c1 +#define mmSQ_PERFCOUNTER2_SELECT 0xd9c2 +#define mmSQ_PERFCOUNTER3_SELECT 0xd9c3 +#define mmSQ_PERFCOUNTER4_SELECT 0xd9c4 +#define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 +#define mmSQ_PERFCOUNTER6_SELECT 0xd9c6 +#define mmSQ_PERFCOUNTER7_SELECT 0xd9c7 +#define mmSQ_PERFCOUNTER8_SELECT 0xd9c8 +#define mmSQ_PERFCOUNTER9_SELECT 0xd9c9 +#define mmSQ_PERFCOUNTER10_SELECT 0xd9ca +#define mmSQ_PERFCOUNTER11_SELECT 0xd9cb +#define mmSQ_PERFCOUNTER12_SELECT 0xd9cc +#define mmSQ_PERFCOUNTER13_SELECT 0xd9cd +#define mmSQ_PERFCOUNTER14_SELECT 0xd9ce +#define mmSQ_PERFCOUNTER15_SELECT 0xd9cf +#define mmCGTT_SQ_CLK_CTRL 0xf08c +#define mmCGTT_SQG_CLK_CTRL 0xf08d +#define mmSQ_ALU_CLK_CTRL 0xf08e +#define mmSQ_TEX_CLK_CTRL 0xf08f +#define mmSQ_LDS_CLK_CTRL 0xf090 +#define mmSQ_POWER_THROTTLE 0xf091 +#define mmSQ_POWER_THROTTLE2 0xf092 +#define mmSQ_TIME_HI 0x237c +#define mmSQ_TIME_LO 0x237d +#define mmSQ_THREAD_TRACE_BASE 0xc330 +#define mmSQ_THREAD_TRACE_BASE2 0xc337 +#define mmSQ_THREAD_TRACE_SIZE 0xc331 +#define mmSQ_THREAD_TRACE_MASK 0xc332 +#define mmSQ_THREAD_TRACE_USERDATA_0 0xc340 +#define mmSQ_THREAD_TRACE_USERDATA_1 0xc341 +#define mmSQ_THREAD_TRACE_USERDATA_2 0xc342 +#define mmSQ_THREAD_TRACE_USERDATA_3 0xc343 +#define mmSQ_THREAD_TRACE_MODE 0xc336 +#define mmSQ_THREAD_TRACE_CTRL 0xc335 +#define mmSQ_THREAD_TRACE_TOKEN_MASK 0xc333 +#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0xc338 +#define mmSQ_THREAD_TRACE_PERF_MASK 0xc334 +#define mmSQ_THREAD_TRACE_WPTR 0xc339 +#define mmSQ_THREAD_TRACE_STATUS 0xc33a +#define mmSQ_THREAD_TRACE_CNTR 0x2390 +#define mmSQ_THREAD_TRACE_HIWATER 0xc33b +#define mmSQ_LB_CTR_CTRL 0x2398 +#define mmSQ_LB_DATA_ALU_CYCLES 0x2399 +#define mmSQ_LB_DATA_TEX_CYCLES 0x239a +#define mmSQ_LB_DATA_ALU_STALLS 0x239b +#define mmSQ_LB_DATA_TEX_STALLS 0x239c +#define mmSQC_EDC_CNT 0x23a0 +#define mmSQ_EDC_SEC_CNT 0x23a1 +#define mmSQ_EDC_DED_CNT 0x23a2 +#define mmSQ_EDC_INFO 0x23a3 +#define mmSQ_BUF_RSRC_WORD0 0x23c0 +#define mmSQ_BUF_RSRC_WORD1 0x23c1 +#define mmSQ_BUF_RSRC_WORD2 0x23c2 +#define mmSQ_BUF_RSRC_WORD3 0x23c3 +#define mmSQ_IMG_RSRC_WORD0 0x23c4 +#define mmSQ_IMG_RSRC_WORD1 0x23c5 +#define mmSQ_IMG_RSRC_WORD2 0x23c6 +#define mmSQ_IMG_RSRC_WORD3 0x23c7 +#define mmSQ_IMG_RSRC_WORD4 0x23c8 +#define mmSQ_IMG_RSRC_WORD5 0x23c9 +#define mmSQ_IMG_RSRC_WORD6 0x23ca +#define mmSQ_IMG_RSRC_WORD7 0x23cb +#define mmSQ_IMG_SAMP_WORD0 0x23cc +#define mmSQ_IMG_SAMP_WORD1 0x23cd +#define mmSQ_IMG_SAMP_WORD2 0x23ce +#define mmSQ_IMG_SAMP_WORD3 0x23cf +#define mmSQ_FLAT_SCRATCH_WORD0 0x23d0 +#define mmSQ_FLAT_SCRATCH_WORD1 0x23d1 +#define mmSQ_M0_GPR_IDX_WORD 0x23d2 +#define mmSQ_IND_INDEX 0x2378 +#define mmSQ_CMD 0x237b +#define mmSQ_IND_DATA 0x2379 +#define mmSQ_REG_TIMESTAMP 0x2374 +#define mmSQ_CMD_TIMESTAMP 0x2375 +#define mmSQ_HV_VMID_CTRL 0xf840 +#define ixSQ_WAVE_INST_DW0 0x1a +#define ixSQ_WAVE_INST_DW1 0x1b +#define ixSQ_WAVE_PC_LO 0x18 +#define ixSQ_WAVE_PC_HI 0x19 +#define ixSQ_WAVE_IB_DBG0 0x1c +#define ixSQ_WAVE_IB_DBG1 0x1d +#define ixSQ_WAVE_EXEC_LO 0x27e +#define ixSQ_WAVE_EXEC_HI 0x27f +#define ixSQ_WAVE_STATUS 0x12 +#define ixSQ_WAVE_MODE 0x11 +#define ixSQ_WAVE_TRAPSTS 0x13 +#define ixSQ_WAVE_HW_ID 0x14 +#define ixSQ_WAVE_GPR_ALLOC 0x15 +#define ixSQ_WAVE_LDS_ALLOC 0x16 +#define ixSQ_WAVE_IB_STS 0x17 +#define ixSQ_WAVE_M0 0x27c +#define ixSQ_WAVE_TBA_LO 0x26c +#define ixSQ_WAVE_TBA_HI 0x26d +#define ixSQ_WAVE_TMA_LO 0x26e +#define ixSQ_WAVE_TMA_HI 0x26f +#define ixSQ_WAVE_TTMP0 0x270 +#define ixSQ_WAVE_TTMP1 0x271 +#define ixSQ_WAVE_TTMP2 0x272 +#define ixSQ_WAVE_TTMP3 0x273 +#define ixSQ_WAVE_TTMP4 0x274 +#define ixSQ_WAVE_TTMP5 0x275 +#define ixSQ_WAVE_TTMP6 0x276 +#define ixSQ_WAVE_TTMP7 0x277 +#define ixSQ_WAVE_TTMP8 0x278 +#define ixSQ_WAVE_TTMP9 0x279 +#define ixSQ_WAVE_TTMP10 0x27a +#define ixSQ_WAVE_TTMP11 0x27b +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 +#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 +#define mmSQ_DEBUG_STS_GLOBAL3 0x2311 +#define ixSQ_DEBUG_STS_LOCAL 0x8 +#define ixSQ_DEBUG_CTRL_LOCAL 0x9 +#define mmSH_MEM_BASES 0x230a +#define mmSH_MEM_APE1_BASE 0x230b +#define mmSH_MEM_APE1_LIMIT 0x230c +#define mmSH_MEM_CONFIG 0x230d +#define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1 +#define mmSQ_WREXEC_EXEC_LO 0x23b1 +#define mmSQ_WREXEC_EXEC_HI 0x23b1 +#define mmSQC_GATCL1_CNTL 0x23b2 +#define mmSQC_ATC_EDC_GATCL1_CNT 0x23b3 +#define ixSQ_INTERRUPT_WORD_CMN 0x20c0 +#define ixSQ_INTERRUPT_WORD_AUTO 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE 0x20c0 +#define mmSQ_SOP2 0x237f +#define mmSQ_VOP1 0x237f +#define mmSQ_MTBUF_1 0x237f +#define mmSQ_EXP_1 0x237f +#define mmSQ_MUBUF_1 0x237f +#define mmSQ_SMEM_1 0x237f +#define mmSQ_INST 0x237f +#define mmSQ_EXP_0 0x237f +#define mmSQ_MUBUF_0 0x237f +#define mmSQ_VOP_SDWA 0x237f +#define mmSQ_VOP3_0 0x237f +#define mmSQ_VOP2 0x237f +#define mmSQ_MTBUF_0 0x237f +#define mmSQ_SOPP 0x237f +#define mmSQ_FLAT_0 0x237f +#define mmSQ_VOP3_0_SDST_ENC 0x237f +#define mmSQ_MIMG_1 0x237f +#define mmSQ_SOP1 0x237f +#define mmSQ_SOPC 0x237f +#define mmSQ_FLAT_1 0x237f +#define mmSQ_DS_1 0x237f +#define mmSQ_VOP3_1 0x237f +#define mmSQ_SMEM_0 0x237f +#define mmSQ_MIMG_0 0x237f +#define mmSQ_SOPK 0x237f +#define mmSQ_DS_0 0x237f +#define mmSQ_VOP_DPP 0x237f +#define mmSQ_VOPC 0x237f +#define mmSQ_VINTRP 0x237f +#define mmCGTT_SX_CLK_CTRL0 0xf094 +#define mmCGTT_SX_CLK_CTRL1 0xf095 +#define mmCGTT_SX_CLK_CTRL2 0xf096 +#define mmCGTT_SX_CLK_CTRL3 0xf097 +#define mmCGTT_SX_CLK_CTRL4 0xf098 +#define mmSX_DEBUG_BUSY 0x2414 +#define mmSX_DEBUG_BUSY_2 0x2415 +#define mmSX_DEBUG_BUSY_3 0x2416 +#define mmSX_DEBUG_BUSY_4 0x2417 +#define mmSX_DEBUG_1 0x2418 +#define mmSX_PERFCOUNTER0_SELECT 0xda40 +#define mmSX_PERFCOUNTER1_SELECT 0xda41 +#define mmSX_PERFCOUNTER2_SELECT 0xda42 +#define mmSX_PERFCOUNTER3_SELECT 0xda43 +#define mmSX_PERFCOUNTER0_SELECT1 0xda44 +#define mmSX_PERFCOUNTER1_SELECT1 0xda45 +#define mmSX_PERFCOUNTER0_LO 0xd240 +#define mmSX_PERFCOUNTER0_HI 0xd241 +#define mmSX_PERFCOUNTER1_LO 0xd242 +#define mmSX_PERFCOUNTER1_HI 0xd243 +#define mmSX_PERFCOUNTER2_LO 0xd244 +#define mmSX_PERFCOUNTER2_HI 0xd245 +#define mmSX_PERFCOUNTER3_LO 0xd246 +#define mmSX_PERFCOUNTER3_HI 0xd247 +#define mmTCC_CTRL 0x2b80 +#define mmTCC_EDC_CNT 0x2b82 +#define mmTCC_REDUNDANCY 0x2b83 +#define mmTCC_EXE_DISABLE 0x2b84 +#define mmTCC_DSM_CNTL 0x2b85 +#define mmTCC_CGTT_SCLK_CTRL 0xf0ac +#define mmTCA_CGTT_SCLK_CTRL 0xf0ad +#define mmTCC_PERFCOUNTER0_SELECT 0xdb80 +#define mmTCC_PERFCOUNTER1_SELECT 0xdb82 +#define mmTCC_PERFCOUNTER0_SELECT1 0xdb81 +#define mmTCC_PERFCOUNTER1_SELECT1 0xdb83 +#define mmTCC_PERFCOUNTER2_SELECT 0xdb84 +#define mmTCC_PERFCOUNTER3_SELECT 0xdb85 +#define mmTCC_PERFCOUNTER0_LO 0xd380 +#define mmTCC_PERFCOUNTER1_LO 0xd382 +#define mmTCC_PERFCOUNTER2_LO 0xd384 +#define mmTCC_PERFCOUNTER3_LO 0xd386 +#define mmTCC_PERFCOUNTER0_HI 0xd381 +#define mmTCC_PERFCOUNTER1_HI 0xd383 +#define mmTCC_PERFCOUNTER2_HI 0xd385 +#define mmTCC_PERFCOUNTER3_HI 0xd387 +#define mmTCA_CTRL 0x2bc0 +#define mmTCA_PERFCOUNTER0_SELECT 0xdb90 +#define mmTCA_PERFCOUNTER1_SELECT 0xdb92 +#define mmTCA_PERFCOUNTER0_SELECT1 0xdb91 +#define mmTCA_PERFCOUNTER1_SELECT1 0xdb93 +#define mmTCA_PERFCOUNTER2_SELECT 0xdb94 +#define mmTCA_PERFCOUNTER3_SELECT 0xdb95 +#define mmTCA_PERFCOUNTER0_LO 0xd390 +#define mmTCA_PERFCOUNTER1_LO 0xd392 +#define mmTCA_PERFCOUNTER2_LO 0xd394 +#define mmTCA_PERFCOUNTER3_LO 0xd396 +#define mmTCA_PERFCOUNTER0_HI 0xd391 +#define mmTCA_PERFCOUNTER1_HI 0xd393 +#define mmTCA_PERFCOUNTER2_HI 0xd395 +#define mmTCA_PERFCOUNTER3_HI 0xd397 +#define mmTA_BC_BASE_ADDR 0xa020 +#define mmTA_BC_BASE_ADDR_HI 0xa021 +#define mmTD_CNTL 0x2525 +#define mmTD_STATUS 0x2526 +#define mmTD_DEBUG_INDEX 0x2528 +#define mmTD_DEBUG_DATA 0x2529 +#define mmTD_DSM_CNTL 0x252f +#define mmTD_PERFCOUNTER0_SELECT 0xdb00 +#define mmTD_PERFCOUNTER1_SELECT 0xdb02 +#define mmTD_PERFCOUNTER0_SELECT1 0xdb01 +#define mmTD_PERFCOUNTER0_LO 0xd300 +#define mmTD_PERFCOUNTER1_LO 0xd302 +#define mmTD_PERFCOUNTER0_HI 0xd301 +#define mmTD_PERFCOUNTER1_HI 0xd303 +#define mmTD_SCRATCH 0x2533 +#define mmTA_CNTL 0x2541 +#define mmTA_CNTL_AUX 0x2542 +#define mmTA_RESERVED_010C 0x2543 +#define mmTA_CS_BC_BASE_ADDR 0xc380 +#define mmTA_CS_BC_BASE_ADDR_HI 0xc381 +#define mmTA_STATUS 0x2548 +#define mmTA_DEBUG_INDEX 0x254c +#define mmTA_DEBUG_DATA 0x254d +#define mmTA_PERFCOUNTER0_SELECT 0xdac0 +#define mmTA_PERFCOUNTER1_SELECT 0xdac2 +#define mmTA_PERFCOUNTER0_SELECT1 0xdac1 +#define mmTA_PERFCOUNTER0_LO 0xd2c0 +#define mmTA_PERFCOUNTER1_LO 0xd2c2 +#define mmTA_PERFCOUNTER0_HI 0xd2c1 +#define mmTA_PERFCOUNTER1_HI 0xd2c3 +#define mmTA_SCRATCH 0x2564 +#define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580 +#define mmSH_STATIC_MEM_CONFIG 0x2581 +#define mmTCP_INVALIDATE 0x2b00 +#define mmTCP_STATUS 0x2b01 +#define mmTCP_CNTL 0x2b02 +#define mmTCP_CHAN_STEER_LO 0x2b03 +#define mmTCP_CHAN_STEER_HI 0x2b04 +#define mmTCP_ADDR_CONFIG 0x2b05 +#define mmTCP_CREDIT 0x2b06 +#define mmTCP_PERFCOUNTER0_SELECT 0xdb40 +#define mmTCP_PERFCOUNTER1_SELECT 0xdb42 +#define mmTCP_PERFCOUNTER0_SELECT1 0xdb41 +#define mmTCP_PERFCOUNTER1_SELECT1 0xdb43 +#define mmTCP_PERFCOUNTER2_SELECT 0xdb44 +#define mmTCP_PERFCOUNTER3_SELECT 0xdb45 +#define mmTCP_PERFCOUNTER0_LO 0xd340 +#define mmTCP_PERFCOUNTER1_LO 0xd342 +#define mmTCP_PERFCOUNTER2_LO 0xd344 +#define mmTCP_PERFCOUNTER3_LO 0xd346 +#define mmTCP_PERFCOUNTER0_HI 0xd341 +#define mmTCP_PERFCOUNTER1_HI 0xd343 +#define mmTCP_PERFCOUNTER2_HI 0xd345 +#define mmTCP_PERFCOUNTER3_HI 0xd347 +#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16 +#define mmTCP_EDC_CNT 0x2b17 +#define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a +#define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b +#define mmTC_CFG_L1_STORE_POLICY 0x2b1c +#define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d +#define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e +#define mmTC_CFG_L2_STORE_POLICY0 0x2b1f +#define mmTC_CFG_L2_STORE_POLICY1 0x2b20 +#define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21 +#define mmTC_CFG_L1_VOLATILE 0x2b22 +#define mmTC_CFG_L2_VOLATILE 0x2b23 +#define mmTCP_WATCH0_ADDR_H 0x32a0 +#define mmTCP_WATCH1_ADDR_H 0x32a3 +#define mmTCP_WATCH2_ADDR_H 0x32a6 +#define mmTCP_WATCH3_ADDR_H 0x32a9 +#define mmTCP_WATCH0_ADDR_L 0x32a1 +#define mmTCP_WATCH1_ADDR_L 0x32a4 +#define mmTCP_WATCH2_ADDR_L 0x32a7 +#define mmTCP_WATCH3_ADDR_L 0x32aa +#define mmTCP_WATCH0_CNTL 0x32a2 +#define mmTCP_WATCH1_CNTL 0x32a5 +#define mmTCP_WATCH2_CNTL 0x32a8 +#define mmTCP_WATCH3_CNTL 0x32ab +#define mmTCP_GATCL1_CNTL 0x32b0 +#define mmTCP_ATC_EDC_GATCL1_CNT 0x32b1 +#define mmTCP_GATCL1_DSM_CNTL 0x32b2 +#define mmTCP_DSM_CNTL 0x32b3 +#define mmTCP_CNTL2 0x32b4 +#define mmTD_CGTT_CTRL 0xf09c +#define mmTA_CGTT_CTRL 0xf09d +#define mmCGTT_TCP_CLK_CTRL 0xf09e +#define mmCGTT_TCI_CLK_CTRL 0xf09f +#define mmTCI_STATUS 0x2b61 +#define mmTCI_CNTL_1 0x2b62 +#define mmTCI_CNTL_2 0x2b63 +#define mmGDS_CONFIG 0x25c0 +#define mmGDS_CNTL_STATUS 0x25c1 +#define mmGDS_ENHANCE2 0x25c2 +#define mmGDS_PROTECTION_FAULT 0x25c3 +#define mmGDS_VM_PROTECTION_FAULT 0x25c4 +#define mmGDS_EDC_CNT 0x25c5 +#define mmGDS_EDC_GRBM_CNT 0x25c6 +#define mmGDS_EDC_OA_DED 0x25c7 +#define mmGDS_DEBUG_CNTL 0x25c8 +#define mmGDS_DEBUG_DATA 0x25c9 +#define mmGDS_DSM_CNTL 0x25ca +#define mmCGTT_GDS_CLK_CTRL 0xf0a0 +#define mmGDS_RD_ADDR 0xc400 +#define mmGDS_RD_DATA 0xc401 +#define mmGDS_RD_BURST_ADDR 0xc402 +#define mmGDS_RD_BURST_COUNT 0xc403 +#define mmGDS_RD_BURST_DATA 0xc404 +#define mmGDS_WR_ADDR 0xc405 +#define mmGDS_WR_DATA 0xc406 +#define mmGDS_WR_BURST_ADDR 0xc407 +#define mmGDS_WR_BURST_DATA 0xc408 +#define mmGDS_WRITE_COMPLETE 0xc409 +#define mmGDS_ATOM_CNTL 0xc40a +#define mmGDS_ATOM_COMPLETE 0xc40b +#define mmGDS_ATOM_BASE 0xc40c +#define mmGDS_ATOM_SIZE 0xc40d +#define mmGDS_ATOM_OFFSET0 0xc40e +#define mmGDS_ATOM_OFFSET1 0xc40f +#define mmGDS_ATOM_DST 0xc410 +#define mmGDS_ATOM_OP 0xc411 +#define mmGDS_ATOM_SRC0 0xc412 +#define mmGDS_ATOM_SRC0_U 0xc413 +#define mmGDS_ATOM_SRC1 0xc414 +#define mmGDS_ATOM_SRC1_U 0xc415 +#define mmGDS_ATOM_READ0 0xc416 +#define mmGDS_ATOM_READ0_U 0xc417 +#define mmGDS_ATOM_READ1 0xc418 +#define mmGDS_ATOM_READ1_U 0xc419 +#define mmGDS_GWS_RESOURCE_CNTL 0xc41a +#define mmGDS_GWS_RESOURCE 0xc41b +#define mmGDS_GWS_RESOURCE_CNT 0xc41c +#define mmGDS_OA_CNTL 0xc41d +#define mmGDS_OA_COUNTER 0xc41e +#define mmGDS_OA_ADDRESS 0xc41f +#define mmGDS_OA_INCDEC 0xc420 +#define mmGDS_OA_RING_SIZE 0xc421 +#define ixGDS_DEBUG_REG0 0x0 +#define ixGDS_DEBUG_REG1 0x1 +#define ixGDS_DEBUG_REG2 0x2 +#define ixGDS_DEBUG_REG3 0x3 +#define ixGDS_DEBUG_REG4 0x4 +#define ixGDS_DEBUG_REG5 0x5 +#define ixGDS_DEBUG_REG6 0x6 +#define mmGDS_PERFCOUNTER0_SELECT 0xda80 +#define mmGDS_PERFCOUNTER1_SELECT 0xda81 +#define mmGDS_PERFCOUNTER2_SELECT 0xda82 +#define mmGDS_PERFCOUNTER3_SELECT 0xda83 +#define mmGDS_PERFCOUNTER0_LO 0xd280 +#define mmGDS_PERFCOUNTER1_LO 0xd282 +#define mmGDS_PERFCOUNTER2_LO 0xd284 +#define mmGDS_PERFCOUNTER3_LO 0xd286 +#define mmGDS_PERFCOUNTER0_HI 0xd281 +#define mmGDS_PERFCOUNTER1_HI 0xd283 +#define mmGDS_PERFCOUNTER2_HI 0xd285 +#define mmGDS_PERFCOUNTER3_HI 0xd287 +#define mmGDS_PERFCOUNTER0_SELECT1 0xda84 +#define mmGDS_VMID0_BASE 0x3300 +#define mmGDS_VMID1_BASE 0x3302 +#define mmGDS_VMID2_BASE 0x3304 +#define mmGDS_VMID3_BASE 0x3306 +#define mmGDS_VMID4_BASE 0x3308 +#define mmGDS_VMID5_BASE 0x330a +#define mmGDS_VMID6_BASE 0x330c +#define mmGDS_VMID7_BASE 0x330e +#define mmGDS_VMID8_BASE 0x3310 +#define mmGDS_VMID9_BASE 0x3312 +#define mmGDS_VMID10_BASE 0x3314 +#define mmGDS_VMID11_BASE 0x3316 +#define mmGDS_VMID12_BASE 0x3318 +#define mmGDS_VMID13_BASE 0x331a +#define mmGDS_VMID14_BASE 0x331c +#define mmGDS_VMID15_BASE 0x331e +#define mmGDS_VMID0_SIZE 0x3301 +#define mmGDS_VMID1_SIZE 0x3303 +#define mmGDS_VMID2_SIZE 0x3305 +#define mmGDS_VMID3_SIZE 0x3307 +#define mmGDS_VMID4_SIZE 0x3309 +#define mmGDS_VMID5_SIZE 0x330b +#define mmGDS_VMID6_SIZE 0x330d +#define mmGDS_VMID7_SIZE 0x330f +#define mmGDS_VMID8_SIZE 0x3311 +#define mmGDS_VMID9_SIZE 0x3313 +#define mmGDS_VMID10_SIZE 0x3315 +#define mmGDS_VMID11_SIZE 0x3317 +#define mmGDS_VMID12_SIZE 0x3319 +#define mmGDS_VMID13_SIZE 0x331b +#define mmGDS_VMID14_SIZE 0x331d +#define mmGDS_VMID15_SIZE 0x331f +#define mmGDS_GWS_VMID0 0x3320 +#define mmGDS_GWS_VMID1 0x3321 +#define mmGDS_GWS_VMID2 0x3322 +#define mmGDS_GWS_VMID3 0x3323 +#define mmGDS_GWS_VMID4 0x3324 +#define mmGDS_GWS_VMID5 0x3325 +#define mmGDS_GWS_VMID6 0x3326 +#define mmGDS_GWS_VMID7 0x3327 +#define mmGDS_GWS_VMID8 0x3328 +#define mmGDS_GWS_VMID9 0x3329 +#define mmGDS_GWS_VMID10 0x332a +#define mmGDS_GWS_VMID11 0x332b +#define mmGDS_GWS_VMID12 0x332c +#define mmGDS_GWS_VMID13 0x332d +#define mmGDS_GWS_VMID14 0x332e +#define mmGDS_GWS_VMID15 0x332f +#define mmGDS_OA_VMID0 0x3330 +#define mmGDS_OA_VMID1 0x3331 +#define mmGDS_OA_VMID2 0x3332 +#define mmGDS_OA_VMID3 0x3333 +#define mmGDS_OA_VMID4 0x3334 +#define mmGDS_OA_VMID5 0x3335 +#define mmGDS_OA_VMID6 0x3336 +#define mmGDS_OA_VMID7 0x3337 +#define mmGDS_OA_VMID8 0x3338 +#define mmGDS_OA_VMID9 0x3339 +#define mmGDS_OA_VMID10 0x333a +#define mmGDS_OA_VMID11 0x333b +#define mmGDS_OA_VMID12 0x333c +#define mmGDS_OA_VMID13 0x333d +#define mmGDS_OA_VMID14 0x333e +#define mmGDS_OA_VMID15 0x333f +#define mmGDS_GWS_RESET0 0x3344 +#define mmGDS_GWS_RESET1 0x3345 +#define mmGDS_GWS_RESOURCE_RESET 0x3346 +#define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348 +#define mmGDS_OA_RESET_MASK 0x3349 +#define mmGDS_OA_RESET 0x334a +#define mmGDS_ENHANCE 0x334b +#define mmGDS_OA_CGPG_RESTORE 0x334c +#define mmGDS_CS_CTXSW_STATUS 0x334d +#define mmGDS_CS_CTXSW_CNT0 0x334e +#define mmGDS_CS_CTXSW_CNT1 0x334f +#define mmGDS_CS_CTXSW_CNT2 0x3350 +#define mmGDS_CS_CTXSW_CNT3 0x3351 +#define mmGDS_GFX_CTXSW_STATUS 0x3352 +#define mmGDS_VS_CTXSW_CNT0 0x3353 +#define mmGDS_VS_CTXSW_CNT1 0x3354 +#define mmGDS_VS_CTXSW_CNT2 0x3355 +#define mmGDS_VS_CTXSW_CNT3 0x3356 +#define mmGDS_PS0_CTXSW_CNT0 0x3357 +#define mmGDS_PS1_CTXSW_CNT0 0x335b +#define mmGDS_PS2_CTXSW_CNT0 0x335f +#define mmGDS_PS3_CTXSW_CNT0 0x3363 +#define mmGDS_PS4_CTXSW_CNT0 0x3367 +#define mmGDS_PS5_CTXSW_CNT0 0x336b +#define mmGDS_PS6_CTXSW_CNT0 0x336f +#define mmGDS_PS7_CTXSW_CNT0 0x3373 +#define mmGDS_PS0_CTXSW_CNT1 0x3358 +#define mmGDS_PS1_CTXSW_CNT1 0x335c +#define mmGDS_PS2_CTXSW_CNT1 0x3360 +#define mmGDS_PS3_CTXSW_CNT1 0x3364 +#define mmGDS_PS4_CTXSW_CNT1 0x3368 +#define mmGDS_PS5_CTXSW_CNT1 0x336c +#define mmGDS_PS6_CTXSW_CNT1 0x3370 +#define mmGDS_PS7_CTXSW_CNT1 0x3374 +#define mmGDS_PS0_CTXSW_CNT2 0x3359 +#define mmGDS_PS1_CTXSW_CNT2 0x335d +#define mmGDS_PS2_CTXSW_CNT2 0x3361 +#define mmGDS_PS3_CTXSW_CNT2 0x3365 +#define mmGDS_PS4_CTXSW_CNT2 0x3369 +#define mmGDS_PS5_CTXSW_CNT2 0x336d +#define mmGDS_PS6_CTXSW_CNT2 0x3371 +#define mmGDS_PS7_CTXSW_CNT2 0x3375 +#define mmGDS_PS0_CTXSW_CNT3 0x335a +#define mmGDS_PS1_CTXSW_CNT3 0x335e +#define mmGDS_PS2_CTXSW_CNT3 0x3362 +#define mmGDS_PS3_CTXSW_CNT3 0x3366 +#define mmGDS_PS4_CTXSW_CNT3 0x336a +#define mmGDS_PS5_CTXSW_CNT3 0x336e +#define mmGDS_PS6_CTXSW_CNT3 0x3372 +#define mmGDS_PS7_CTXSW_CNT3 0x3376 +#define mmCS_COPY_STATE 0xa1f3 +#define mmGFX_COPY_STATE 0xa1f4 +#define mmVGT_DRAW_INITIATOR 0xa1fc +#define mmVGT_EVENT_INITIATOR 0xa2a4 +#define mmVGT_EVENT_ADDRESS_REG 0xa1fe +#define mmVGT_DMA_BASE_HI 0xa1f9 +#define mmVGT_DMA_BASE 0xa1fa +#define mmVGT_DMA_INDEX_TYPE 0xa29f +#define mmVGT_DMA_NUM_INSTANCES 0xa2a2 +#define mmIA_ENHANCE 0xa29c +#define mmVGT_DMA_SIZE 0xa29d +#define mmVGT_DMA_MAX_SIZE 0xa29e +#define mmVGT_DMA_PRIMITIVE_TYPE 0x2271 +#define mmVGT_DMA_CONTROL 0x2272 +#define mmVGT_IMMED_DATA 0xa1fd +#define mmVGT_INDEX_TYPE 0xc243 +#define mmVGT_NUM_INDICES 0xc24c +#define mmVGT_NUM_INSTANCES 0xc24d +#define mmVGT_PRIMITIVE_TYPE 0xc242 +#define mmVGT_PRIMITIVEID_EN 0xa2a1 +#define mmVGT_PRIMITIVEID_RESET 0xa2a3 +#define mmVGT_VTX_CNT_EN 0xa2ae +#define mmVGT_REUSE_OFF 0xa2ad +#define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8 +#define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9 +#define mmVGT_MAX_VTX_INDX 0xa100 +#define mmVGT_MIN_VTX_INDX 0xa101 +#define mmVGT_INDX_OFFSET 0xa102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316 +#define mmVGT_OUT_DEALLOC_CNTL 0xa317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103 +#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5 +#define mmVGT_ENHANCE 0xa294 +#define mmVGT_OUTPUT_PATH_CNTL 0xa284 +#define mmVGT_HOS_CNTL 0xa285 +#define mmVGT_HOS_MAX_TESS_LEVEL 0xa286 +#define mmVGT_HOS_MIN_TESS_LEVEL 0xa287 +#define mmVGT_HOS_REUSE_DEPTH 0xa288 +#define mmVGT_GROUP_PRIM_TYPE 0xa289 +#define mmVGT_GROUP_FIRST_DECR 0xa28a +#define mmVGT_GROUP_DECR 0xa28b +#define mmVGT_GROUP_VECT_0_CNTL 0xa28c +#define mmVGT_GROUP_VECT_1_CNTL 0xa28d +#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e +#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f +#define mmVGT_VTX_VECT_EJECT_REG 0x222c +#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d +#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e +#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f +#define mmVGT_LAST_COPY_STATE 0x2230 +#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f +#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 +#define mmVGT_GS_MODE 0xa290 +#define mmVGT_GS_ONCHIP_CNTL 0xa291 +#define mmVGT_GS_OUT_PRIM_TYPE 0xa29b +#define mmVGT_CACHE_INVALIDATION 0x2231 +#define mmVGT_RESET_DEBUG 0x2232 +#define mmVGT_STRMOUT_DELAY 0x2233 +#define mmVGT_FIFO_DEPTHS 0x2234 +#define mmVGT_GS_PER_ES 0xa295 +#define mmVGT_ES_PER_GS 0xa296 +#define mmVGT_GS_PER_VS 0xa297 +#define mmVGT_GS_VERTEX_REUSE 0x2235 +#define mmVGT_MC_LAT_CNTL 0x2236 +#define mmIA_CNTL_STATUS 0x2237 +#define mmVGT_STRMOUT_CONFIG 0xa2e5 +#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4 +#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8 +#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc +#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0 +#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7 +#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb +#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf +#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3 +#define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5 +#define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9 +#define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd +#define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1 +#define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247 +#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca +#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb +#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc +#define mmVGT_GS_MAX_VERT_OUT 0xa2ce +#define mmVGT_SHADER_STAGES_EN 0xa2d5 +#define mmVGT_DISPATCH_DRAW_INDEX 0xa2dd +#define mmVGT_LS_HS_CONFIG 0xa2d6 +#define mmVGT_DMA_LS_HS_CONFIG 0x2273 +#define mmVGT_TF_PARAM 0xa2db +#define mmVGT_TESS_DISTRIBUTION 0xa2d4 +#define mmVGT_TF_RING_SIZE 0xc24e +#define mmVGT_SYS_CONFIG 0x2263 +#define mmVGT_HS_OFFCHIP_PARAM 0xc24f +#define mmVGT_TF_MEMORY_BASE 0xc250 +#define mmVGT_GS_INSTANCE_CNT 0xa2e4 +#define mmIA_MULTI_VGT_PARAM 0xa2aa +#define mmVGT_VS_MAX_WAVE_ID 0x2268 +#define mmVGT_ESGS_RING_SIZE 0xc240 +#define mmVGT_GSVS_RING_SIZE 0xc241 +#define mmVGT_GSVS_RING_OFFSET_1 0xa298 +#define mmVGT_GSVS_RING_OFFSET_2 0xa299 +#define mmVGT_GSVS_RING_OFFSET_3 0xa29a +#define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab +#define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac +#define mmVGT_GS_VERT_ITEMSIZE 0xa2d7 +#define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8 +#define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9 +#define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da +#define mmWD_CNTL_STATUS 0x223f +#define mmWD_ENHANCE 0xa2a0 +#define mmGFX_PIPE_CONTROL 0x226d +#define mmGFX_PIPE_PRIORITY 0xf87f +#define mmCGTT_VGT_CLK_CTRL 0xf084 +#define mmCGTT_IA_CLK_CTRL 0xf085 +#define mmCGTT_WD_CLK_CTRL 0xf086 +#define mmVGT_DEBUG_CNTL 0x2238 +#define mmVGT_DEBUG_DATA 0x2239 +#define mmIA_DEBUG_CNTL 0x223a +#define mmIA_DEBUG_DATA 0x223b +#define mmVGT_CNTL_STATUS 0x223c +#define mmWD_DEBUG_CNTL 0x223d +#define mmWD_DEBUG_DATA 0x223e +#define mmWD_QOS 0x2242 +#define mmCC_GC_PRIM_CONFIG 0x2240 +#define mmGC_USER_PRIM_CONFIG 0x2241 +#define ixWD_DEBUG_REG0 0x0 +#define ixWD_DEBUG_REG1 0x1 +#define ixWD_DEBUG_REG2 0x2 +#define ixWD_DEBUG_REG3 0x3 +#define ixWD_DEBUG_REG4 0x4 +#define ixWD_DEBUG_REG5 0x5 +#define ixWD_DEBUG_REG6 0x6 +#define ixWD_DEBUG_REG7 0x7 +#define ixWD_DEBUG_REG8 0x8 +#define ixWD_DEBUG_REG9 0x9 +#define ixWD_DEBUG_REG10 0xa +#define ixIA_DEBUG_REG0 0x0 +#define ixIA_DEBUG_REG1 0x1 +#define ixIA_DEBUG_REG2 0x2 +#define ixIA_DEBUG_REG3 0x3 +#define ixIA_DEBUG_REG4 0x4 +#define ixIA_DEBUG_REG5 0x5 +#define ixIA_DEBUG_REG6 0x6 +#define ixIA_DEBUG_REG7 0x7 +#define ixIA_DEBUG_REG8 0x8 +#define ixIA_DEBUG_REG9 0x9 +#define ixVGT_DEBUG_REG0 0x0 +#define ixVGT_DEBUG_REG1 0x1 +#define ixVGT_DEBUG_REG2 0x1e +#define ixVGT_DEBUG_REG3 0x1f +#define ixVGT_DEBUG_REG4 0x20 +#define ixVGT_DEBUG_REG5 0x21 +#define ixVGT_DEBUG_REG6 0x22 +#define ixVGT_DEBUG_REG7 0x23 +#define ixVGT_DEBUG_REG8 0x8 +#define ixVGT_DEBUG_REG9 0x9 +#define ixVGT_DEBUG_REG10 0xa +#define ixVGT_DEBUG_REG11 0xb +#define ixVGT_DEBUG_REG12 0xc +#define ixVGT_DEBUG_REG13 0xd +#define ixVGT_DEBUG_REG14 0xe +#define ixVGT_DEBUG_REG15 0xf +#define ixVGT_DEBUG_REG16 0x10 +#define ixVGT_DEBUG_REG17 0x11 +#define ixVGT_DEBUG_REG18 0x7 +#define ixVGT_DEBUG_REG19 0x13 +#define ixVGT_DEBUG_REG20 0x14 +#define ixVGT_DEBUG_REG21 0x15 +#define ixVGT_DEBUG_REG22 0x16 +#define ixVGT_DEBUG_REG23 0x17 +#define ixVGT_DEBUG_REG24 0x18 +#define ixVGT_DEBUG_REG25 0x19 +#define ixVGT_DEBUG_REG26 0x24 +#define ixVGT_DEBUG_REG27 0x1b +#define ixVGT_DEBUG_REG28 0x1c +#define ixVGT_DEBUG_REG29 0x1d +#define ixVGT_DEBUG_REG31 0x26 +#define ixVGT_DEBUG_REG32 0x27 +#define ixVGT_DEBUG_REG33 0x28 +#define ixVGT_DEBUG_REG34 0x29 +#define ixVGT_DEBUG_REG36 0x2b +#define mmVGT_PERFCOUNTER_SEID_MASK 0xd894 +#define mmVGT_PERFCOUNTER0_SELECT 0xd88c +#define mmVGT_PERFCOUNTER1_SELECT 0xd88d +#define mmVGT_PERFCOUNTER2_SELECT 0xd88e +#define mmVGT_PERFCOUNTER3_SELECT 0xd88f +#define mmVGT_PERFCOUNTER0_SELECT1 0xd890 +#define mmVGT_PERFCOUNTER1_SELECT1 0xd891 +#define mmVGT_PERFCOUNTER0_LO 0xd090 +#define mmVGT_PERFCOUNTER1_LO 0xd092 +#define mmVGT_PERFCOUNTER2_LO 0xd094 +#define mmVGT_PERFCOUNTER3_LO 0xd096 +#define mmVGT_PERFCOUNTER0_HI 0xd091 +#define mmVGT_PERFCOUNTER1_HI 0xd093 +#define mmVGT_PERFCOUNTER2_HI 0xd095 +#define mmVGT_PERFCOUNTER3_HI 0xd097 +#define mmIA_PERFCOUNTER0_SELECT 0xd884 +#define mmIA_PERFCOUNTER1_SELECT 0xd885 +#define mmIA_PERFCOUNTER2_SELECT 0xd886 +#define mmIA_PERFCOUNTER3_SELECT 0xd887 +#define mmIA_PERFCOUNTER0_SELECT1 0xd888 +#define mmIA_PERFCOUNTER0_LO 0xd088 +#define mmIA_PERFCOUNTER1_LO 0xd08a +#define mmIA_PERFCOUNTER2_LO 0xd08c +#define mmIA_PERFCOUNTER3_LO 0xd08e +#define mmIA_PERFCOUNTER0_HI 0xd089 +#define mmIA_PERFCOUNTER1_HI 0xd08b +#define mmIA_PERFCOUNTER2_HI 0xd08d +#define mmIA_PERFCOUNTER3_HI 0xd08f +#define mmWD_PERFCOUNTER0_SELECT 0xd880 +#define mmWD_PERFCOUNTER1_SELECT 0xd881 +#define mmWD_PERFCOUNTER2_SELECT 0xd882 +#define mmWD_PERFCOUNTER3_SELECT 0xd883 +#define mmWD_PERFCOUNTER0_LO 0xd080 +#define mmWD_PERFCOUNTER1_LO 0xd082 +#define mmWD_PERFCOUNTER2_LO 0xd084 +#define mmWD_PERFCOUNTER3_LO 0xd086 +#define mmWD_PERFCOUNTER0_HI 0xd081 +#define mmWD_PERFCOUNTER1_HI 0xd083 +#define mmWD_PERFCOUNTER2_HI 0xd085 +#define mmWD_PERFCOUNTER3_HI 0xd087 +#define mmDIDT_IND_INDEX 0x3280 +#define mmDIDT_IND_DATA 0x3281 +#define ixDIDT_SQ_CTRL0 0x0 +#define ixDIDT_SQ_CTRL1 0x1 +#define ixDIDT_SQ_CTRL2 0x2 +#define ixDIDT_SQ_CTRL_OCP 0x3 +#define ixDIDT_SQ_WEIGHT0_3 0x10 +#define ixDIDT_SQ_WEIGHT4_7 0x11 +#define ixDIDT_SQ_WEIGHT8_11 0x12 +#define ixDIDT_DB_CTRL0 0x20 +#define ixDIDT_DB_CTRL1 0x21 +#define ixDIDT_DB_CTRL2 0x22 +#define ixDIDT_DB_CTRL_OCP 0x23 +#define ixDIDT_DB_WEIGHT0_3 0x30 +#define ixDIDT_DB_WEIGHT4_7 0x31 +#define ixDIDT_DB_WEIGHT8_11 0x32 +#define ixDIDT_TD_CTRL0 0x40 +#define ixDIDT_TD_CTRL1 0x41 +#define ixDIDT_TD_CTRL2 0x42 +#define ixDIDT_TD_CTRL_OCP 0x43 +#define ixDIDT_TD_WEIGHT0_3 0x50 +#define ixDIDT_TD_WEIGHT4_7 0x51 +#define ixDIDT_TD_WEIGHT8_11 0x52 +#define ixDIDT_TCP_CTRL0 0x60 +#define ixDIDT_TCP_CTRL1 0x61 +#define ixDIDT_TCP_CTRL2 0x62 +#define ixDIDT_TCP_CTRL_OCP 0x63 +#define ixDIDT_TCP_WEIGHT0_3 0x70 +#define ixDIDT_TCP_WEIGHT4_7 0x71 +#define ixDIDT_TCP_WEIGHT8_11 0x72 +#define ixDIDT_DBR_CTRL0 0x80 +#define ixDIDT_DBR_CTRL1 0x81 +#define ixDIDT_DBR_CTRL2 0x82 +#define ixDIDT_DBR_CTRL_OCP 0x83 +#define ixDIDT_DBR_WEIGHT0_3 0x90 +#define ixDIDT_DBR_WEIGHT4_7 0x91 +#define ixDIDT_DBR_WEIGHT8_11 0x92 + +#endif /* GFX_8_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h new file mode 100644 index 000000000000..43386c24c17c --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h @@ -0,0 +1,6858 @@ +/* + * GFX_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_8_0_ENUM_H +#define GFX_8_0_ENUM_H + +typedef enum SurfaceNumber { + NUMBER_UNORM = 0x0, + NUMBER_SNORM = 0x1, + NUMBER_USCALED = 0x2, + NUMBER_SSCALED = 0x3, + NUMBER_UINT = 0x4, + NUMBER_SINT = 0x5, + NUMBER_SRGB = 0x6, + NUMBER_FLOAT = 0x7, +} SurfaceNumber; +typedef enum SurfaceSwap { + SWAP_STD = 0x0, + SWAP_ALT = 0x1, + SWAP_STD_REV = 0x2, + SWAP_ALT_REV = 0x3, +} SurfaceSwap; +typedef enum CBMode { + CB_DISABLE = 0x0, + CB_NORMAL = 0x1, + CB_ELIMINATE_FAST_CLEAR = 0x2, + CB_RESOLVE = 0x3, + CB_DECOMPRESS = 0x4, + CB_FMASK_DECOMPRESS = 0x5, + CB_DCC_DECOMPRESS = 0x6, +} CBMode; +typedef enum RoundMode { + ROUND_BY_HALF = 0x0, + ROUND_TRUNCATE = 0x1, +} RoundMode; +typedef enum SourceFormat { + EXPORT_4C_32BPC = 0x0, + EXPORT_4C_16BPC = 0x1, + EXPORT_2C_32BPC_GR = 0x2, + EXPORT_2C_32BPC_AR = 0x3, +} SourceFormat; +typedef enum BlendOp { + BLEND_ZERO = 0x0, + BLEND_ONE = 0x1, + BLEND_SRC_COLOR = 0x2, + BLEND_ONE_MINUS_SRC_COLOR = 0x3, + BLEND_SRC_ALPHA = 0x4, + BLEND_ONE_MINUS_SRC_ALPHA = 0x5, + BLEND_DST_ALPHA = 0x6, + BLEND_ONE_MINUS_DST_ALPHA = 0x7, + BLEND_DST_COLOR = 0x8, + BLEND_ONE_MINUS_DST_COLOR = 0x9, + BLEND_SRC_ALPHA_SATURATE = 0xa, + BLEND_BOTH_SRC_ALPHA = 0xb, + BLEND_BOTH_INV_SRC_ALPHA = 0xc, + BLEND_CONSTANT_COLOR = 0xd, + BLEND_ONE_MINUS_CONSTANT_COLOR = 0xe, + BLEND_SRC1_COLOR = 0xf, + BLEND_INV_SRC1_COLOR = 0x10, + BLEND_SRC1_ALPHA = 0x11, + BLEND_INV_SRC1_ALPHA = 0x12, + BLEND_CONSTANT_ALPHA = 0x13, + BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, +} BlendOp; +typedef enum CombFunc { + COMB_DST_PLUS_SRC = 0x0, + COMB_SRC_MINUS_DST = 0x1, + COMB_MIN_DST_SRC = 0x2, + COMB_MAX_DST_SRC = 0x3, + COMB_DST_MINUS_SRC = 0x4, +} CombFunc; +typedef enum BlendOpt { + FORCE_OPT_AUTO = 0x0, + FORCE_OPT_DISABLE = 0x1, + FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2, + FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x3, + FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x4, + FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5, + FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x6, + FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x7, +} BlendOpt; +typedef enum CmaskCode { + CMASK_CLR00_F0 = 0x0, + CMASK_CLR00_F1 = 0x1, + CMASK_CLR00_F2 = 0x2, + CMASK_CLR00_FX = 0x3, + CMASK_CLR01_F0 = 0x4, + CMASK_CLR01_F1 = 0x5, + CMASK_CLR01_F2 = 0x6, + CMASK_CLR01_FX = 0x7, + CMASK_CLR10_F0 = 0x8, + CMASK_CLR10_F1 = 0x9, + CMASK_CLR10_F2 = 0xa, + CMASK_CLR10_FX = 0xb, + CMASK_CLR11_F0 = 0xc, + CMASK_CLR11_F1 = 0xd, + CMASK_CLR11_F2 = 0xe, + CMASK_CLR11_FX = 0xf, +} CmaskCode; +typedef enum CmaskAddr { + CMASK_ADDR_TILED = 0x0, + CMASK_ADDR_LINEAR = 0x1, + CMASK_ADDR_COMPATIBLE = 0x2, +} CmaskAddr; +typedef enum CBPerfSel { + CB_PERF_SEL_NONE = 0x0, + CB_PERF_SEL_BUSY = 0x1, + CB_PERF_SEL_CORE_SCLK_VLD = 0x2, + CB_PERF_SEL_REG_SCLK0_VLD = 0x3, + CB_PERF_SEL_REG_SCLK1_VLD = 0x4, + CB_PERF_SEL_DRAWN_QUAD = 0x5, + CB_PERF_SEL_DRAWN_PIXEL = 0x6, + CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x7, + CB_PERF_SEL_DRAWN_TILE = 0x8, + CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x9, + CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa, + CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0xb, + CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0xc, + CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0xd, + CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0xe, + CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0xf, + CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x10, + CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x11, + CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x12, + CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x13, + CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x14, + CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x15, + CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x16, + CB_PERF_SEL_LQUAD_NO_TILE = 0x17, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x18, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x19, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x1a, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x1b, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x1c, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e, + CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x1f, + CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x20, + CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21, + CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x22, + CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x23, + CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x24, + CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x25, + CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x26, + CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x27, + CB_PERF_SEL_FOP_IN_VALID_READY = 0x28, + CB_PERF_SEL_FOP_IN_VALID_READYB = 0x29, + CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x2a, + CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x2b, + CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x2c, + CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x2d, + CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x2e, + CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x2f, + CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x30, + CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x31, + CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x32, + CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x33, + CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x34, + CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x35, + CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x36, + CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x37, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x38, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x39, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x3a, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x3b, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x3c, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x3d, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x3e, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x3f, + CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x40, + CB_PERF_SEL_CM_CACHE_HIT = 0x41, + CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x42, + CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x43, + CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x44, + CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45, + CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46, + CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47, + CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x48, + CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x49, + CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x4a, + CB_PERF_SEL_CM_CACHE_STALL = 0x4b, + CB_PERF_SEL_CM_CACHE_FLUSH = 0x4c, + CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x4d, + CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x4e, + CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x4f, + CB_PERF_SEL_FC_CACHE_HIT = 0x50, + CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x51, + CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x52, + CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x53, + CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54, + CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55, + CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56, + CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x57, + CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x58, + CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x59, + CB_PERF_SEL_FC_CACHE_STALL = 0x5a, + CB_PERF_SEL_FC_CACHE_FLUSH = 0x5b, + CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x5c, + CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x5d, + CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x5e, + CB_PERF_SEL_CC_CACHE_HIT = 0x5f, + CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x60, + CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x61, + CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x62, + CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63, + CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64, + CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65, + CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x66, + CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x67, + CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x68, + CB_PERF_SEL_CC_CACHE_STALL = 0x69, + CB_PERF_SEL_CC_CACHE_FLUSH = 0x6a, + CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x6b, + CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x6c, + CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x6d, + CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x6e, + CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x6f, + CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x70, + CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x71, + CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x72, + CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x73, + CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x74, + CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x75, + CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x76, + CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x77, + CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x78, + CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x79, + CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x7a, + CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x7b, + CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x7c, + CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x7d, + CB_PERF_SEL_CM_MC_READ_REQUEST = 0x7e, + CB_PERF_SEL_FC_MC_READ_REQUEST = 0x7f, + CB_PERF_SEL_CC_MC_READ_REQUEST = 0x80, + CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x81, + CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x82, + CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x83, + CB_PERF_SEL_CM_TQ_FULL = 0x84, + CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x85, + CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x86, + CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x87, + CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x88, + CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x89, + CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x8a, + CB_PERF_SEL_CC_SF_FULL = 0x8b, + CB_PERF_SEL_CC_RB_FULL = 0x8c, + CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x8d, + CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x8e, + CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x8f, + CB_PERF_SEL_EVENT = 0x90, + CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x91, + CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x92, + CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x93, + CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x94, + CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x95, + CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x96, + CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x97, + CB_PERF_SEL_CC_SURFACE_SYNC = 0x98, + CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x99, + CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x9a, + CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x9b, + CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x9c, + CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x9d, + CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x9e, + CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x9f, + CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0xa0, + CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0xa1, + CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0xa2, + CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0xa3, + CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0xa4, + CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0xa5, + CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0xa6, + CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0xa7, + CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0xa8, + CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0xa9, + CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0xaa, + CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0xab, + CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0xac, + CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0xad, + CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0xae, + CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0xaf, + CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0xb0, + CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0xb1, + CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0xb2, + CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0xb3, + CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0xb4, + CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0xb5, + CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0xb6, + CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0xb7, + CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0xb8, + CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0xb9, + CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0xba, + CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0xbb, + CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0xbc, + CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0xbd, + CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0xbe, + CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0xbf, + CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0xc0, + CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0xc1, + CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0xc2, + CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0xc3, + CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0xc4, + CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0xc5, + CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0xc6, + CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0xc7, + CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0xc8, + CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0xc9, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0xca, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0xcb, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0xcc, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0xcd, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0xce, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0xcf, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0xd0, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0xd1, + CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0xd2, + CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0xd3, + CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0xd4, + CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd5, + CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd6, + CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0xd7, + CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0xd8, + CB_PERF_SEL_DRAWN_BUSY = 0xd9, + CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0xda, + CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0xdb, + CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0xdc, + CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0xdd, + CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xde, + CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0xdf, + CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0xe0, + CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0xe1, + CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe2, + CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0xe3, + CB_PERF_SEL_FC_DOC_IS_STALLED = 0xe4, + CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0xe5, + CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0xe6, + CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0xe7, + CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0xe8, + CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0xe9, + CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0xea, + CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0xeb, + CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0xec, + CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0xed, + CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0xee, + CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0xef, + CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0xf0, + CB_PERF_SEL_FC_DCC_CACHE_HIT = 0xf1, + CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0xf2, + CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0xf3, + CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0xf4, + CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0xf5, + CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL= 0xf6, + CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0xf7, + CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0xf8, + CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0xf9, + CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0xfa, + CB_PERF_SEL_FC_DCC_CACHE_STALL = 0xfb, + CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0xfc, + CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0xfd, + CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0xfe, + CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0xff, + CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x100, + CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x101, + CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x102, + CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x103, + CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x104, + CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x105, + CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x106, + CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x107, + CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x108, + CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x109, + CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x10a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x10b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2= 0x10c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x10d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1= 0x10e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1= 0x10f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2= 0x110, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x113, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1= 0x114, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2= 0x116, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x118, + CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1= 0x119, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x11a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2= 0x11b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3= 0x11c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4= 0x11d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1= 0x11e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x11f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3= 0x120, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4= 0x121, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2= 0x123, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x124, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2= 0x127, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3= 0x128, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1= 0x129, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2= 0x12a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3= 0x12b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4= 0x12c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1= 0x12d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2= 0x12e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3= 0x12f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4= 0x130, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4= 0x134, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3= 0x137, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1= 0x138, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1= 0x139, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1= 0x13a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1= 0x13b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1= 0x13c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1= 0x13d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1= 0x13e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1= 0x13f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2= 0x140, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2= 0x142, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2= 0x143, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2= 0x144, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2= 0x146, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1= 0x147, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1= 0x148, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1= 0x149, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1= 0x14a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2= 0x14b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2= 0x14c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2= 0x14d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2= 0x14e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x14f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2= 0x150, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2= 0x151, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x152, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1= 0x153, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1= 0x154, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1= 0x155, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1= 0x156, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2= 0x157, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3= 0x158, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4= 0x159, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5= 0x15a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6= 0x15b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x15c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x15d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1= 0x15e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2= 0x15f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3= 0x160, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4= 0x161, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5= 0x162, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x163, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x164, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1= 0x165, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1= 0x166, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1= 0x167, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1= 0x168, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1= 0x169, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1= 0x16a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x16b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x16c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2= 0x16d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2= 0x16e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2= 0x16f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2= 0x170, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2= 0x171, + CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x172, + CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x173, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x174, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x175, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x176, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x177, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x178, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x179, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x17a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x17b, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x17c, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x17d, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x17e, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x17f, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x180, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x181, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x182, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x183, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x184, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x185, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x186, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x187, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x188, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x189, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x18a, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x18b, +} CBPerfSel; +typedef enum CBPerfOpFilterSel { + CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x0, + CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x1, + CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2, + CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x3, + CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x4, + CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5, +} CBPerfOpFilterSel; +typedef enum CBPerfClearFilterSel { + CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x0, + CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x1, +} CBPerfClearFilterSel; +typedef enum CP_RING_ID { + RINGID0 = 0x0, + RINGID1 = 0x1, + RINGID2 = 0x2, + RINGID3 = 0x3, +} CP_RING_ID; +typedef enum CP_PIPE_ID { + PIPE_ID0 = 0x0, + PIPE_ID1 = 0x1, + PIPE_ID2 = 0x2, + PIPE_ID3 = 0x3, +} CP_PIPE_ID; +typedef enum CP_ME_ID { + ME_ID0 = 0x0, + ME_ID1 = 0x1, + ME_ID2 = 0x2, + ME_ID3 = 0x3, +} CP_ME_ID; +typedef enum SPM_PERFMON_STATE { + STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x0, + STRM_PERFMON_STATE_START_COUNTING = 0x1, + STRM_PERFMON_STATE_STOP_COUNTING = 0x2, + STRM_PERFMON_STATE_RESERVED_3 = 0x3, + STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, + STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, +} SPM_PERFMON_STATE; +typedef enum CP_PERFMON_STATE { + CP_PERFMON_STATE_DISABLE_AND_RESET = 0x0, + CP_PERFMON_STATE_START_COUNTING = 0x1, + CP_PERFMON_STATE_STOP_COUNTING = 0x2, + CP_PERFMON_STATE_RESERVED_3 = 0x3, + CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, + CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, +} CP_PERFMON_STATE; +typedef enum CP_PERFMON_ENABLE_MODE { + CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x0, + CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x1, + CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2, + CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x3, +} CP_PERFMON_ENABLE_MODE; +typedef enum CPG_PERFCOUNT_SEL { + CPG_PERF_SEL_ALWAYS_COUNT = 0x0, + CPG_PERF_SEL_RBIU_FIFO_FULL = 0x1, + CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2, + CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x3, + CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x4, + CPG_PERF_SEL_ME_PARSER_BUSY = 0x5, + CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x6, + CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x7, + CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x8, + CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x9, + CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa, + CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0xb, + CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0xc, + CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0xd, + CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0xe, + CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0xf, + CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x10, + CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x11, + CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x12, + CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x13, + CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x14, + CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x15, + CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x16, + CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x17, + CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x18, + CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x19, + CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x1a, + CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x1b, + CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x1c, + CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d, + CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x1e, + CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x1f, + CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x20, + CPG_PERF_SEL_REGISTER_CLK_VALID = 0x21, + CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x22, + CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x23, + CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x24, + CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x25, + CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x26, + CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x27, + CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x28, + CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x29, + CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x2a, + CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x2b, + CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x2c, + CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x2d, + CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x2e, + CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x2f, + CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x30, +} CPG_PERFCOUNT_SEL; +typedef enum CPF_PERFCOUNT_SEL { + CPF_PERF_SEL_ALWAYS_COUNT = 0x0, + CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x1, + CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2, + CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x3, + CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x4, + CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x5, + CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x6, + CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x7, + CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x8, + CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x9, + CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa, + CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0xb, + CPF_PERF_SEL_GRBM_DWORDS_SENT = 0xc, + CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0xd, + CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0xe, + CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0xf, + CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x10, + CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x11, + CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x12, + CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x13, +} CPF_PERFCOUNT_SEL; +typedef enum CPC_PERFCOUNT_SEL { + CPC_PERF_SEL_ALWAYS_COUNT = 0x0, + CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x1, + CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2, + CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x3, + CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x4, + CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x5, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x6, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x7, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x8, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x9, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa, + CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0xb, + CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0xc, + CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0xd, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0xe, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0xf, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x10, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x11, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x12, + CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x13, + CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x14, + CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x15, + CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x16, + CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x17, + CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x18, +} CPC_PERFCOUNT_SEL; +typedef enum CP_ALPHA_TAG_RAM_SEL { + CPG_TAG_RAM = 0x0, + CPC_TAG_RAM = 0x1, + CPF_TAG_RAM = 0x2, + RSV_TAG_RAM = 0x3, +} CP_ALPHA_TAG_RAM_SEL; +#define SEM_ECC_ERROR 0x0 +#define SEM_RESERVED 0x1 +#define SEM_FAILED 0x2 +#define SEM_PASSED 0x3 +#define IQ_QUEUE_SLEEP 0x0 +#define IQ_OFFLOAD_RETRY 0x1 +#define IQ_SCH_WAVE_MSG 0x2 +#define IQ_SEM_REARM 0x3 +#define IQ_DEQUEUE_RETRY 0x4 +#define IQ_INTR_TYPE_PQ 0x0 +#define IQ_INTR_TYPE_IB 0x1 +#define IQ_INTR_TYPE_MQD 0x2 +#define VMID_SZ 0x4 +#define CONFIG_SPACE_START 0x2000 +#define CONFIG_SPACE_END 0x9fff +#define CONFIG_SPACE1_START 0x2000 +#define CONFIG_SPACE1_END 0x2bff +#define CONFIG_SPACE2_START 0x3000 +#define CONFIG_SPACE2_END 0x9fff +#define UCONFIG_SPACE_START 0xc000 +#define UCONFIG_SPACE_END 0xffff +#define PERSISTENT_SPACE_START 0x2c00 +#define PERSISTENT_SPACE_END 0x2fff +#define CONTEXT_SPACE_START 0xa000 +#define CONTEXT_SPACE_END 0xbfff +typedef enum ForceControl { + FORCE_OFF = 0x0, + FORCE_ENABLE = 0x1, + FORCE_DISABLE = 0x2, + FORCE_RESERVED = 0x3, +} ForceControl; +typedef enum ZSamplePosition { + Z_SAMPLE_CENTER = 0x0, + Z_SAMPLE_CENTROID = 0x1, +} ZSamplePosition; +typedef enum ZOrder { + LATE_Z = 0x0, + EARLY_Z_THEN_LATE_Z = 0x1, + RE_Z = 0x2, + EARLY_Z_THEN_RE_Z = 0x3, +} ZOrder; +typedef enum ZpassControl { + ZPASS_DISABLE = 0x0, + ZPASS_SAMPLES = 0x1, + ZPASS_PIXELS = 0x2, +} ZpassControl; +typedef enum ZModeForce { + NO_FORCE = 0x0, + FORCE_EARLY_Z = 0x1, + FORCE_LATE_Z = 0x2, + FORCE_RE_Z = 0x3, +} ZModeForce; +typedef enum ZLimitSumm { + FORCE_SUMM_OFF = 0x0, + FORCE_SUMM_MINZ = 0x1, + FORCE_SUMM_MAXZ = 0x2, + FORCE_SUMM_BOTH = 0x3, +} ZLimitSumm; +typedef enum CompareFrag { + FRAG_NEVER = 0x0, + FRAG_LESS = 0x1, + FRAG_EQUAL = 0x2, + FRAG_LEQUAL = 0x3, + FRAG_GREATER = 0x4, + FRAG_NOTEQUAL = 0x5, + FRAG_GEQUAL = 0x6, + FRAG_ALWAYS = 0x7, +} CompareFrag; +typedef enum StencilOp { + STENCIL_KEEP = 0x0, + STENCIL_ZERO = 0x1, + STENCIL_ONES = 0x2, + STENCIL_REPLACE_TEST = 0x3, + STENCIL_REPLACE_OP = 0x4, + STENCIL_ADD_CLAMP = 0x5, + STENCIL_SUB_CLAMP = 0x6, + STENCIL_INVERT = 0x7, + STENCIL_ADD_WRAP = 0x8, + STENCIL_SUB_WRAP = 0x9, + STENCIL_AND = 0xa, + STENCIL_OR = 0xb, + STENCIL_XOR = 0xc, + STENCIL_NAND = 0xd, + STENCIL_NOR = 0xe, + STENCIL_XNOR = 0xf, +} StencilOp; +typedef enum ConservativeZExport { + EXPORT_ANY_Z = 0x0, + EXPORT_LESS_THAN_Z = 0x1, + EXPORT_GREATER_THAN_Z = 0x2, + EXPORT_RESERVED = 0x3, +} ConservativeZExport; +typedef enum DbPSLControl { + PSLC_AUTO = 0x0, + PSLC_ON_HANG_ONLY = 0x1, + PSLC_ASAP = 0x2, + PSLC_COUNTDOWN = 0x3, +} DbPSLControl; +typedef enum PerfCounter_Vals { + DB_PERF_SEL_SC_DB_tile_sends = 0x0, + DB_PERF_SEL_SC_DB_tile_busy = 0x1, + DB_PERF_SEL_SC_DB_tile_stalls = 0x2, + DB_PERF_SEL_SC_DB_tile_events = 0x3, + DB_PERF_SEL_SC_DB_tile_tiles = 0x4, + DB_PERF_SEL_SC_DB_tile_covered = 0x5, + DB_PERF_SEL_hiz_tc_read_starved = 0x6, + DB_PERF_SEL_hiz_tc_write_stall = 0x7, + DB_PERF_SEL_hiz_qtiles_culled = 0x8, + DB_PERF_SEL_his_qtiles_culled = 0x9, + DB_PERF_SEL_DB_SC_tile_sends = 0xa, + DB_PERF_SEL_DB_SC_tile_busy = 0xb, + DB_PERF_SEL_DB_SC_tile_stalls = 0xc, + DB_PERF_SEL_DB_SC_tile_df_stalls = 0xd, + DB_PERF_SEL_DB_SC_tile_tiles = 0xe, + DB_PERF_SEL_DB_SC_tile_culled = 0xf, + DB_PERF_SEL_DB_SC_tile_hier_kill = 0x10, + DB_PERF_SEL_DB_SC_tile_fast_ops = 0x11, + DB_PERF_SEL_DB_SC_tile_no_ops = 0x12, + DB_PERF_SEL_DB_SC_tile_tile_rate = 0x13, + DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x14, + DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x15, + DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x16, + DB_PERF_SEL_SC_DB_quad_sends = 0x17, + DB_PERF_SEL_SC_DB_quad_busy = 0x18, + DB_PERF_SEL_SC_DB_quad_squads = 0x19, + DB_PERF_SEL_SC_DB_quad_tiles = 0x1a, + DB_PERF_SEL_SC_DB_quad_pixels = 0x1b, + DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x1c, + DB_PERF_SEL_DB_SC_quad_sends = 0x1d, + DB_PERF_SEL_DB_SC_quad_busy = 0x1e, + DB_PERF_SEL_DB_SC_quad_stalls = 0x1f, + DB_PERF_SEL_DB_SC_quad_tiles = 0x20, + DB_PERF_SEL_DB_SC_quad_lit_quad = 0x21, + DB_PERF_SEL_DB_CB_tile_sends = 0x22, + DB_PERF_SEL_DB_CB_tile_busy = 0x23, + DB_PERF_SEL_DB_CB_tile_stalls = 0x24, + DB_PERF_SEL_SX_DB_quad_sends = 0x25, + DB_PERF_SEL_SX_DB_quad_busy = 0x26, + DB_PERF_SEL_SX_DB_quad_stalls = 0x27, + DB_PERF_SEL_SX_DB_quad_quads = 0x28, + DB_PERF_SEL_SX_DB_quad_pixels = 0x29, + DB_PERF_SEL_SX_DB_quad_exports = 0x2a, + DB_PERF_SEL_SH_quads_outstanding_sum = 0x2b, + DB_PERF_SEL_DB_CB_lquad_sends = 0x2c, + DB_PERF_SEL_DB_CB_lquad_busy = 0x2d, + DB_PERF_SEL_DB_CB_lquad_stalls = 0x2e, + DB_PERF_SEL_DB_CB_lquad_quads = 0x2f, + DB_PERF_SEL_tile_rd_sends = 0x30, + DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x31, + DB_PERF_SEL_quad_rd_sends = 0x32, + DB_PERF_SEL_quad_rd_busy = 0x33, + DB_PERF_SEL_quad_rd_mi_stall = 0x34, + DB_PERF_SEL_quad_rd_rw_collision = 0x35, + DB_PERF_SEL_quad_rd_tag_stall = 0x36, + DB_PERF_SEL_quad_rd_32byte_reqs = 0x37, + DB_PERF_SEL_quad_rd_panic = 0x38, + DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x39, + DB_PERF_SEL_quad_rdret_sends = 0x3a, + DB_PERF_SEL_quad_rdret_busy = 0x3b, + DB_PERF_SEL_tile_wr_sends = 0x3c, + DB_PERF_SEL_tile_wr_acks = 0x3d, + DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x3e, + DB_PERF_SEL_quad_wr_sends = 0x3f, + DB_PERF_SEL_quad_wr_busy = 0x40, + DB_PERF_SEL_quad_wr_mi_stall = 0x41, + DB_PERF_SEL_quad_wr_coherency_stall = 0x42, + DB_PERF_SEL_quad_wr_acks = 0x43, + DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x44, + DB_PERF_SEL_Tile_Cache_misses = 0x45, + DB_PERF_SEL_Tile_Cache_hits = 0x46, + DB_PERF_SEL_Tile_Cache_flushes = 0x47, + DB_PERF_SEL_Tile_Cache_surface_stall = 0x48, + DB_PERF_SEL_Tile_Cache_starves = 0x49, + DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x4a, + DB_PERF_SEL_tcp_dispatcher_reads = 0x4b, + DB_PERF_SEL_tcp_prefetcher_reads = 0x4c, + DB_PERF_SEL_tcp_preloader_reads = 0x4d, + DB_PERF_SEL_tcp_dispatcher_flushes = 0x4e, + DB_PERF_SEL_tcp_prefetcher_flushes = 0x4f, + DB_PERF_SEL_tcp_preloader_flushes = 0x50, + DB_PERF_SEL_Depth_Tile_Cache_sends = 0x51, + DB_PERF_SEL_Depth_Tile_Cache_busy = 0x52, + DB_PERF_SEL_Depth_Tile_Cache_starves = 0x53, + DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x54, + DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x55, + DB_PERF_SEL_Depth_Tile_Cache_misses = 0x56, + DB_PERF_SEL_Depth_Tile_Cache_hits = 0x57, + DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x58, + DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x59, + DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x5a, + DB_PERF_SEL_Depth_Tile_Cache_event = 0x5b, + DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x5c, + DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x5d, + DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x5e, + DB_PERF_SEL_Stencil_Cache_misses = 0x5f, + DB_PERF_SEL_Stencil_Cache_hits = 0x60, + DB_PERF_SEL_Stencil_Cache_flushes = 0x61, + DB_PERF_SEL_Stencil_Cache_starves = 0x62, + DB_PERF_SEL_Stencil_Cache_frees = 0x63, + DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x64, + DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x65, + DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x66, + DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x67, + DB_PERF_SEL_Z_Cache_pmask_misses = 0x68, + DB_PERF_SEL_Z_Cache_pmask_hits = 0x69, + DB_PERF_SEL_Z_Cache_pmask_flushes = 0x6a, + DB_PERF_SEL_Z_Cache_pmask_starves = 0x6b, + DB_PERF_SEL_Z_Cache_frees = 0x6c, + DB_PERF_SEL_Plane_Cache_misses = 0x6d, + DB_PERF_SEL_Plane_Cache_hits = 0x6e, + DB_PERF_SEL_Plane_Cache_flushes = 0x6f, + DB_PERF_SEL_Plane_Cache_starves = 0x70, + DB_PERF_SEL_Plane_Cache_frees = 0x71, + DB_PERF_SEL_flush_expanded_stencil = 0x72, + DB_PERF_SEL_flush_compressed_stencil = 0x73, + DB_PERF_SEL_flush_single_stencil = 0x74, + DB_PERF_SEL_planes_flushed = 0x75, + DB_PERF_SEL_flush_1plane = 0x76, + DB_PERF_SEL_flush_2plane = 0x77, + DB_PERF_SEL_flush_3plane = 0x78, + DB_PERF_SEL_flush_4plane = 0x79, + DB_PERF_SEL_flush_5plane = 0x7a, + DB_PERF_SEL_flush_6plane = 0x7b, + DB_PERF_SEL_flush_7plane = 0x7c, + DB_PERF_SEL_flush_8plane = 0x7d, + DB_PERF_SEL_flush_9plane = 0x7e, + DB_PERF_SEL_flush_10plane = 0x7f, + DB_PERF_SEL_flush_11plane = 0x80, + DB_PERF_SEL_flush_12plane = 0x81, + DB_PERF_SEL_flush_13plane = 0x82, + DB_PERF_SEL_flush_14plane = 0x83, + DB_PERF_SEL_flush_15plane = 0x84, + DB_PERF_SEL_flush_16plane = 0x85, + DB_PERF_SEL_flush_expanded_z = 0x86, + DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x87, + DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x88, + DB_PERF_SEL_dk_tile_sends = 0x89, + DB_PERF_SEL_dk_tile_busy = 0x8a, + DB_PERF_SEL_dk_tile_quad_starves = 0x8b, + DB_PERF_SEL_dk_tile_stalls = 0x8c, + DB_PERF_SEL_dk_squad_sends = 0x8d, + DB_PERF_SEL_dk_squad_busy = 0x8e, + DB_PERF_SEL_dk_squad_stalls = 0x8f, + DB_PERF_SEL_Op_Pipe_Busy = 0x90, + DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x91, + DB_PERF_SEL_qc_busy = 0x92, + DB_PERF_SEL_qc_xfc = 0x93, + DB_PERF_SEL_qc_conflicts = 0x94, + DB_PERF_SEL_qc_full_stall = 0x95, + DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x96, + DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x97, + DB_PERF_SEL_tsc_insert_summarize_stall = 0x98, + DB_PERF_SEL_tl_busy = 0x99, + DB_PERF_SEL_tl_dtc_read_starved = 0x9a, + DB_PERF_SEL_tl_z_fetch_stall = 0x9b, + DB_PERF_SEL_tl_stencil_stall = 0x9c, + DB_PERF_SEL_tl_z_decompress_stall = 0x9d, + DB_PERF_SEL_tl_stencil_locked_stall = 0x9e, + DB_PERF_SEL_tl_events = 0x9f, + DB_PERF_SEL_tl_summarize_squads = 0xa0, + DB_PERF_SEL_tl_flush_expand_squads = 0xa1, + DB_PERF_SEL_tl_expand_squads = 0xa2, + DB_PERF_SEL_tl_preZ_squads = 0xa3, + DB_PERF_SEL_tl_postZ_squads = 0xa4, + DB_PERF_SEL_tl_preZ_noop_squads = 0xa5, + DB_PERF_SEL_tl_postZ_noop_squads = 0xa6, + DB_PERF_SEL_tl_tile_ops = 0xa7, + DB_PERF_SEL_tl_in_xfc = 0xa8, + DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0xa9, + DB_PERF_SEL_tl_in_fast_z_stall = 0xaa, + DB_PERF_SEL_tl_out_xfc = 0xab, + DB_PERF_SEL_tl_out_squads = 0xac, + DB_PERF_SEL_zf_plane_multicycle = 0xad, + DB_PERF_SEL_PostZ_Samples_passing_Z = 0xae, + DB_PERF_SEL_PostZ_Samples_failing_Z = 0xaf, + DB_PERF_SEL_PostZ_Samples_failing_S = 0xb0, + DB_PERF_SEL_PreZ_Samples_passing_Z = 0xb1, + DB_PERF_SEL_PreZ_Samples_failing_Z = 0xb2, + DB_PERF_SEL_PreZ_Samples_failing_S = 0xb3, + DB_PERF_SEL_ts_tc_update_stall = 0xb4, + DB_PERF_SEL_sc_kick_start = 0xb5, + DB_PERF_SEL_sc_kick_end = 0xb6, + DB_PERF_SEL_clock_reg_active = 0xb7, + DB_PERF_SEL_clock_main_active = 0xb8, + DB_PERF_SEL_clock_mem_export_active = 0xb9, + DB_PERF_SEL_esr_ps_out_busy = 0xba, + DB_PERF_SEL_esr_ps_lqf_busy = 0xbb, + DB_PERF_SEL_esr_ps_lqf_stall = 0xbc, + DB_PERF_SEL_etr_out_send = 0xbd, + DB_PERF_SEL_etr_out_busy = 0xbe, + DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0xbf, + DB_PERF_SEL_etr_out_cb_tile_stall = 0xc0, + DB_PERF_SEL_etr_out_esr_stall = 0xc1, + DB_PERF_SEL_esr_ps_sqq_busy = 0xc2, + DB_PERF_SEL_esr_ps_sqq_stall = 0xc3, + DB_PERF_SEL_esr_eot_fwd_busy = 0xc4, + DB_PERF_SEL_esr_eot_fwd_holding_squad = 0xc5, + DB_PERF_SEL_esr_eot_fwd_forward = 0xc6, + DB_PERF_SEL_esr_sqq_zi_busy = 0xc7, + DB_PERF_SEL_esr_sqq_zi_stall = 0xc8, + DB_PERF_SEL_postzl_sq_pt_busy = 0xc9, + DB_PERF_SEL_postzl_sq_pt_stall = 0xca, + DB_PERF_SEL_postzl_se_busy = 0xcb, + DB_PERF_SEL_postzl_se_stall = 0xcc, + DB_PERF_SEL_postzl_partial_launch = 0xcd, + DB_PERF_SEL_postzl_full_launch = 0xce, + DB_PERF_SEL_postzl_partial_waiting = 0xcf, + DB_PERF_SEL_postzl_tile_mem_stall = 0xd0, + DB_PERF_SEL_postzl_tile_init_stall = 0xd1, + DB_PEFF_SEL_prezl_tile_mem_stall = 0xd2, + DB_PERF_SEL_prezl_tile_init_stall = 0xd3, + DB_PERF_SEL_dtt_sm_clash_stall = 0xd4, + DB_PERF_SEL_dtt_sm_slot_stall = 0xd5, + DB_PERF_SEL_dtt_sm_miss_stall = 0xd6, + DB_PERF_SEL_mi_rdreq_busy = 0xd7, + DB_PERF_SEL_mi_rdreq_stall = 0xd8, + DB_PERF_SEL_mi_wrreq_busy = 0xd9, + DB_PERF_SEL_mi_wrreq_stall = 0xda, + DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0xdb, + DB_PERF_SEL_dkg_tile_rate_tile = 0xdc, + DB_PERF_SEL_prezl_src_in_sends = 0xdd, + DB_PERF_SEL_prezl_src_in_stall = 0xde, + DB_PERF_SEL_prezl_src_in_squads = 0xdf, + DB_PERF_SEL_prezl_src_in_squads_unrolled = 0xe0, + DB_PERF_SEL_prezl_src_in_tile_rate = 0xe1, + DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0xe2, + DB_PERF_SEL_prezl_src_out_stall = 0xe3, + DB_PERF_SEL_postzl_src_in_sends = 0xe4, + DB_PERF_SEL_postzl_src_in_stall = 0xe5, + DB_PERF_SEL_postzl_src_in_squads = 0xe6, + DB_PERF_SEL_postzl_src_in_squads_unrolled = 0xe7, + DB_PERF_SEL_postzl_src_in_tile_rate = 0xe8, + DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0xe9, + DB_PERF_SEL_postzl_src_out_stall = 0xea, + DB_PERF_SEL_esr_ps_src_in_sends = 0xeb, + DB_PERF_SEL_esr_ps_src_in_stall = 0xec, + DB_PERF_SEL_esr_ps_src_in_squads = 0xed, + DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0xee, + DB_PERF_SEL_esr_ps_src_in_tile_rate = 0xef, + DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0xf0, + DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1, + DB_PERF_SEL_esr_ps_src_out_stall = 0xf2, + DB_PERF_SEL_depth_bounds_qtiles_culled = 0xf3, + DB_PERF_SEL_PreZ_Samples_failing_DB = 0xf4, + DB_PERF_SEL_PostZ_Samples_failing_DB = 0xf5, + DB_PERF_SEL_flush_compressed = 0xf6, + DB_PERF_SEL_flush_plane_le4 = 0xf7, + DB_PERF_SEL_tiles_z_fully_summarized = 0xf8, + DB_PERF_SEL_tiles_stencil_fully_summarized = 0xf9, + DB_PERF_SEL_tiles_z_clear_on_expclear = 0xfa, + DB_PERF_SEL_tiles_s_clear_on_expclear = 0xfb, + DB_PERF_SEL_tiles_decomp_on_expclear = 0xfc, + DB_PERF_SEL_tiles_compressed_to_decompressed = 0xfd, + DB_PERF_SEL_Op_Pipe_Prez_Busy = 0xfe, + DB_PERF_SEL_Op_Pipe_Postz_Busy = 0xff, + DB_PERF_SEL_di_dt_stall = 0x100, +} PerfCounter_Vals; +typedef enum RingCounterControl { + COUNTER_RING_SPLIT = 0x0, + COUNTER_RING_0 = 0x1, + COUNTER_RING_1 = 0x2, +} RingCounterControl; +typedef enum PixelPipeCounterId { + PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x0, + PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x1, + PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2, + PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x3, + PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x4, + PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x5, + PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x6, + PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x7, +} PixelPipeCounterId; +typedef enum PixelPipeStride { + PIXEL_PIPE_STRIDE_32_BITS = 0x0, + PIXEL_PIPE_STRIDE_64_BITS = 0x1, + PIXEL_PIPE_STRIDE_128_BITS = 0x2, + PIXEL_PIPE_STRIDE_256_BITS = 0x3, +} PixelPipeStride; +typedef enum GB_EDC_DED_MODE { + GB_EDC_DED_MODE_LOG = 0x0, + GB_EDC_DED_MODE_HALT = 0x1, + GB_EDC_DED_MODE_INT_HALT = 0x2, +} GB_EDC_DED_MODE; +#define GB_TILING_CONFIG_TABLE_SIZE 0x20 +#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x10 +typedef enum GRBM_PERF_SEL { + GRBM_PERF_SEL_COUNT = 0x0, + GRBM_PERF_SEL_USER_DEFINED = 0x1, + GRBM_PERF_SEL_GUI_ACTIVE = 0x2, + GRBM_PERF_SEL_CP_BUSY = 0x3, + GRBM_PERF_SEL_CP_COHER_BUSY = 0x4, + GRBM_PERF_SEL_CP_DMA_BUSY = 0x5, + GRBM_PERF_SEL_CB_BUSY = 0x6, + GRBM_PERF_SEL_DB_BUSY = 0x7, + GRBM_PERF_SEL_PA_BUSY = 0x8, + GRBM_PERF_SEL_SC_BUSY = 0x9, + GRBM_PERF_SEL_RESERVED_6 = 0xa, + GRBM_PERF_SEL_SPI_BUSY = 0xb, + GRBM_PERF_SEL_SX_BUSY = 0xc, + GRBM_PERF_SEL_TA_BUSY = 0xd, + GRBM_PERF_SEL_CB_CLEAN = 0xe, + GRBM_PERF_SEL_DB_CLEAN = 0xf, + GRBM_PERF_SEL_RESERVED_5 = 0x10, + GRBM_PERF_SEL_VGT_BUSY = 0x11, + GRBM_PERF_SEL_RESERVED_4 = 0x12, + GRBM_PERF_SEL_RESERVED_3 = 0x13, + GRBM_PERF_SEL_RESERVED_2 = 0x14, + GRBM_PERF_SEL_RESERVED_1 = 0x15, + GRBM_PERF_SEL_RESERVED_0 = 0x16, + GRBM_PERF_SEL_IA_BUSY = 0x17, + GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x18, + GRBM_PERF_SEL_GDS_BUSY = 0x19, + GRBM_PERF_SEL_BCI_BUSY = 0x1a, + GRBM_PERF_SEL_RLC_BUSY = 0x1b, + GRBM_PERF_SEL_TC_BUSY = 0x1c, + GRBM_PERF_SEL_CPG_BUSY = 0x1d, + GRBM_PERF_SEL_CPC_BUSY = 0x1e, + GRBM_PERF_SEL_CPF_BUSY = 0x1f, + GRBM_PERF_SEL_WD_BUSY = 0x20, + GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x21, +} GRBM_PERF_SEL; +typedef enum GRBM_SE0_PERF_SEL { + GRBM_SE0_PERF_SEL_COUNT = 0x0, + GRBM_SE0_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE0_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE0_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE0_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE0_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE0_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE0_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE0_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE0_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE0_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE0_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE0_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE0_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE0_PERF_SEL; +typedef enum GRBM_SE1_PERF_SEL { + GRBM_SE1_PERF_SEL_COUNT = 0x0, + GRBM_SE1_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE1_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE1_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE1_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE1_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE1_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE1_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE1_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE1_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE1_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE1_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE1_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE1_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE1_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE1_PERF_SEL; +typedef enum GRBM_SE2_PERF_SEL { + GRBM_SE2_PERF_SEL_COUNT = 0x0, + GRBM_SE2_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE2_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE2_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE2_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE2_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE2_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE2_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE2_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE2_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE2_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE2_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE2_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE2_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE2_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE2_PERF_SEL; +typedef enum GRBM_SE3_PERF_SEL { + GRBM_SE3_PERF_SEL_COUNT = 0x0, + GRBM_SE3_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE3_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE3_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE3_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE3_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE3_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE3_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE3_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE3_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE3_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE3_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE3_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE3_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE3_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE3_PERF_SEL; +typedef enum SU_PERFCNT_SEL { + PERF_PAPC_PASX_REQ = 0x0, + PERF_PAPC_PASX_DISABLE_PIPE = 0x1, + PERF_PAPC_PASX_FIRST_VECTOR = 0x2, + PERF_PAPC_PASX_SECOND_VECTOR = 0x3, + PERF_PAPC_PASX_FIRST_DEAD = 0x4, + PERF_PAPC_PASX_SECOND_DEAD = 0x5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x7, + PERF_PAPC_PA_INPUT_PRIM = 0x8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 0x9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 0xa, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0xb, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 0xc, + PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0xd, + PERF_PAPC_CLPR_CULL_PRIM = 0xe, + PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0xf, + PERF_PAPC_CLPR_VV_CULL_PRIM = 0x10, + PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x11, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x12, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x13, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x14, + PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x15, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x16, + PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x17, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x18, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x19, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x1a, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x1b, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x1c, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x1e, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x1f, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x20, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x21, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x22, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x23, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x24, + PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x25, + PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x26, + PERF_PAPC_CLSM_NULL_PRIM = 0x27, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x28, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x29, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x2a, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x2b, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x2c, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x2d, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x2e, + PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x2f, + PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x30, + PERF_PAPC_SU_INPUT_PRIM = 0x31, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x32, + PERF_PAPC_SU_INPUT_NULL_PRIM = 0x33, + PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x34, + PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x35, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x36, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x37, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x38, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x39, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x3a, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x3b, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x3c, + PERF_PAPC_SU_OUTPUT_PRIM = 0x3d, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x3e, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x3f, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x40, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x41, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x42, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x43, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x44, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x45, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x46, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x47, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x48, + PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x49, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x4a, + PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x4b, + PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x4c, + PERF_PAPC_PASX_REQ_IDLE = 0x4d, + PERF_PAPC_PASX_REQ_BUSY = 0x4e, + PERF_PAPC_PASX_REQ_STALLED = 0x4f, + PERF_PAPC_PASX_REC_IDLE = 0x50, + PERF_PAPC_PASX_REC_BUSY = 0x51, + PERF_PAPC_PASX_REC_STARVED_SX = 0x52, + PERF_PAPC_PASX_REC_STALLED = 0x53, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x54, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x55, + PERF_PAPC_CCGSM_IDLE = 0x56, + PERF_PAPC_CCGSM_BUSY = 0x57, + PERF_PAPC_CCGSM_STALLED = 0x58, + PERF_PAPC_CLPRIM_IDLE = 0x59, + PERF_PAPC_CLPRIM_BUSY = 0x5a, + PERF_PAPC_CLPRIM_STALLED = 0x5b, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x5c, + PERF_PAPC_CLIPSM_IDLE = 0x5d, + PERF_PAPC_CLIPSM_BUSY = 0x5e, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x5f, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x60, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x61, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x62, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x63, + PERF_PAPC_CLIPGA_IDLE = 0x64, + PERF_PAPC_CLIPGA_BUSY = 0x65, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x66, + PERF_PAPC_CLIPGA_STALLED = 0x67, + PERF_PAPC_CLIP_IDLE = 0x68, + PERF_PAPC_CLIP_BUSY = 0x69, + PERF_PAPC_SU_IDLE = 0x6a, + PERF_PAPC_SU_BUSY = 0x6b, + PERF_PAPC_SU_STARVED_CLIP = 0x6c, + PERF_PAPC_SU_STALLED_SC = 0x6d, + PERF_PAPC_CL_DYN_SCLK_VLD = 0x6e, + PERF_PAPC_SU_DYN_SCLK_VLD = 0x6f, + PERF_PAPC_PA_REG_SCLK_VLD = 0x70, + PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x71, + PERF_PAPC_PASX_SE0_REQ = 0x72, + PERF_PAPC_PASX_SE1_REQ = 0x73, + PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x74, + PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x75, + PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x76, + PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x77, + PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x78, + PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x79, + PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x7a, + PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x7b, + PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x7c, + PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x7d, + PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x7e, + PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x7f, + PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x80, + PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x81, + PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x82, + PERF_PAPC_SU_SE0_STALLED_SC = 0x83, + PERF_PAPC_SU_SE1_STALLED_SC = 0x84, + PERF_PAPC_SU_SE01_STALLED_SC = 0x85, + PERF_PAPC_CLSM_CLIPPING_PRIM = 0x86, + PERF_PAPC_SU_CULLED_PRIM = 0x87, + PERF_PAPC_SU_OUTPUT_EOPG = 0x88, + PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x89, + PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x8a, + PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x8b, + PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x8c, + PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x8d, + PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x8e, + PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x8f, + PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x90, + PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x91, + PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x92, + PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x93, + PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x94, + PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x95, + PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x96, + PERF_PAPC_SU_SE2_STALLED_SC = 0x97, + PERF_PAPC_SU_SE3_STALLED_SC = 0x98, +} SU_PERFCNT_SEL; +typedef enum SC_PERFCNT_SEL { + SC_SRPS_WINDOW_VALID = 0x0, + SC_PSSW_WINDOW_VALID = 0x1, + SC_TPQZ_WINDOW_VALID = 0x2, + SC_QZQP_WINDOW_VALID = 0x3, + SC_TRPK_WINDOW_VALID = 0x4, + SC_SRPS_WINDOW_VALID_BUSY = 0x5, + SC_PSSW_WINDOW_VALID_BUSY = 0x6, + SC_TPQZ_WINDOW_VALID_BUSY = 0x7, + SC_QZQP_WINDOW_VALID_BUSY = 0x8, + SC_TRPK_WINDOW_VALID_BUSY = 0x9, + SC_STARVED_BY_PA = 0xa, + SC_STALLED_BY_PRIMFIFO = 0xb, + SC_STALLED_BY_DB_TILE = 0xc, + SC_STARVED_BY_DB_TILE = 0xd, + SC_STALLED_BY_TILEORDERFIFO = 0xe, + SC_STALLED_BY_TILEFIFO = 0xf, + SC_STALLED_BY_DB_QUAD = 0x10, + SC_STARVED_BY_DB_QUAD = 0x11, + SC_STALLED_BY_QUADFIFO = 0x12, + SC_STALLED_BY_BCI = 0x13, + SC_STALLED_BY_SPI = 0x14, + SC_SCISSOR_DISCARD = 0x15, + SC_BB_DISCARD = 0x16, + SC_SUPERTILE_COUNT = 0x17, + SC_SUPERTILE_PER_PRIM_H0 = 0x18, + SC_SUPERTILE_PER_PRIM_H1 = 0x19, + SC_SUPERTILE_PER_PRIM_H2 = 0x1a, + SC_SUPERTILE_PER_PRIM_H3 = 0x1b, + SC_SUPERTILE_PER_PRIM_H4 = 0x1c, + SC_SUPERTILE_PER_PRIM_H5 = 0x1d, + SC_SUPERTILE_PER_PRIM_H6 = 0x1e, + SC_SUPERTILE_PER_PRIM_H7 = 0x1f, + SC_SUPERTILE_PER_PRIM_H8 = 0x20, + SC_SUPERTILE_PER_PRIM_H9 = 0x21, + SC_SUPERTILE_PER_PRIM_H10 = 0x22, + SC_SUPERTILE_PER_PRIM_H11 = 0x23, + SC_SUPERTILE_PER_PRIM_H12 = 0x24, + SC_SUPERTILE_PER_PRIM_H13 = 0x25, + SC_SUPERTILE_PER_PRIM_H14 = 0x26, + SC_SUPERTILE_PER_PRIM_H15 = 0x27, + SC_SUPERTILE_PER_PRIM_H16 = 0x28, + SC_TILE_PER_PRIM_H0 = 0x29, + SC_TILE_PER_PRIM_H1 = 0x2a, + SC_TILE_PER_PRIM_H2 = 0x2b, + SC_TILE_PER_PRIM_H3 = 0x2c, + SC_TILE_PER_PRIM_H4 = 0x2d, + SC_TILE_PER_PRIM_H5 = 0x2e, + SC_TILE_PER_PRIM_H6 = 0x2f, + SC_TILE_PER_PRIM_H7 = 0x30, + SC_TILE_PER_PRIM_H8 = 0x31, + SC_TILE_PER_PRIM_H9 = 0x32, + SC_TILE_PER_PRIM_H10 = 0x33, + SC_TILE_PER_PRIM_H11 = 0x34, + SC_TILE_PER_PRIM_H12 = 0x35, + SC_TILE_PER_PRIM_H13 = 0x36, + SC_TILE_PER_PRIM_H14 = 0x37, + SC_TILE_PER_PRIM_H15 = 0x38, + SC_TILE_PER_PRIM_H16 = 0x39, + SC_TILE_PER_SUPERTILE_H0 = 0x3a, + SC_TILE_PER_SUPERTILE_H1 = 0x3b, + SC_TILE_PER_SUPERTILE_H2 = 0x3c, + SC_TILE_PER_SUPERTILE_H3 = 0x3d, + SC_TILE_PER_SUPERTILE_H4 = 0x3e, + SC_TILE_PER_SUPERTILE_H5 = 0x3f, + SC_TILE_PER_SUPERTILE_H6 = 0x40, + SC_TILE_PER_SUPERTILE_H7 = 0x41, + SC_TILE_PER_SUPERTILE_H8 = 0x42, + SC_TILE_PER_SUPERTILE_H9 = 0x43, + SC_TILE_PER_SUPERTILE_H10 = 0x44, + SC_TILE_PER_SUPERTILE_H11 = 0x45, + SC_TILE_PER_SUPERTILE_H12 = 0x46, + SC_TILE_PER_SUPERTILE_H13 = 0x47, + SC_TILE_PER_SUPERTILE_H14 = 0x48, + SC_TILE_PER_SUPERTILE_H15 = 0x49, + SC_TILE_PER_SUPERTILE_H16 = 0x4a, + SC_TILE_PICKED_H1 = 0x4b, + SC_TILE_PICKED_H2 = 0x4c, + SC_TILE_PICKED_H3 = 0x4d, + SC_TILE_PICKED_H4 = 0x4e, + SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x4f, + SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x50, + SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x51, + SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x52, + SC_QZ0_TILE_COUNT = 0x53, + SC_QZ1_TILE_COUNT = 0x54, + SC_QZ2_TILE_COUNT = 0x55, + SC_QZ3_TILE_COUNT = 0x56, + SC_QZ0_TILE_COVERED_COUNT = 0x57, + SC_QZ1_TILE_COVERED_COUNT = 0x58, + SC_QZ2_TILE_COVERED_COUNT = 0x59, + SC_QZ3_TILE_COVERED_COUNT = 0x5a, + SC_QZ0_TILE_NOT_COVERED_COUNT = 0x5b, + SC_QZ1_TILE_NOT_COVERED_COUNT = 0x5c, + SC_QZ2_TILE_NOT_COVERED_COUNT = 0x5d, + SC_QZ3_TILE_NOT_COVERED_COUNT = 0x5e, + SC_QZ0_QUAD_PER_TILE_H0 = 0x5f, + SC_QZ0_QUAD_PER_TILE_H1 = 0x60, + SC_QZ0_QUAD_PER_TILE_H2 = 0x61, + SC_QZ0_QUAD_PER_TILE_H3 = 0x62, + SC_QZ0_QUAD_PER_TILE_H4 = 0x63, + SC_QZ0_QUAD_PER_TILE_H5 = 0x64, + SC_QZ0_QUAD_PER_TILE_H6 = 0x65, + SC_QZ0_QUAD_PER_TILE_H7 = 0x66, + SC_QZ0_QUAD_PER_TILE_H8 = 0x67, + SC_QZ0_QUAD_PER_TILE_H9 = 0x68, + SC_QZ0_QUAD_PER_TILE_H10 = 0x69, + SC_QZ0_QUAD_PER_TILE_H11 = 0x6a, + SC_QZ0_QUAD_PER_TILE_H12 = 0x6b, + SC_QZ0_QUAD_PER_TILE_H13 = 0x6c, + SC_QZ0_QUAD_PER_TILE_H14 = 0x6d, + SC_QZ0_QUAD_PER_TILE_H15 = 0x6e, + SC_QZ0_QUAD_PER_TILE_H16 = 0x6f, + SC_QZ1_QUAD_PER_TILE_H0 = 0x70, + SC_QZ1_QUAD_PER_TILE_H1 = 0x71, + SC_QZ1_QUAD_PER_TILE_H2 = 0x72, + SC_QZ1_QUAD_PER_TILE_H3 = 0x73, + SC_QZ1_QUAD_PER_TILE_H4 = 0x74, + SC_QZ1_QUAD_PER_TILE_H5 = 0x75, + SC_QZ1_QUAD_PER_TILE_H6 = 0x76, + SC_QZ1_QUAD_PER_TILE_H7 = 0x77, + SC_QZ1_QUAD_PER_TILE_H8 = 0x78, + SC_QZ1_QUAD_PER_TILE_H9 = 0x79, + SC_QZ1_QUAD_PER_TILE_H10 = 0x7a, + SC_QZ1_QUAD_PER_TILE_H11 = 0x7b, + SC_QZ1_QUAD_PER_TILE_H12 = 0x7c, + SC_QZ1_QUAD_PER_TILE_H13 = 0x7d, + SC_QZ1_QUAD_PER_TILE_H14 = 0x7e, + SC_QZ1_QUAD_PER_TILE_H15 = 0x7f, + SC_QZ1_QUAD_PER_TILE_H16 = 0x80, + SC_QZ2_QUAD_PER_TILE_H0 = 0x81, + SC_QZ2_QUAD_PER_TILE_H1 = 0x82, + SC_QZ2_QUAD_PER_TILE_H2 = 0x83, + SC_QZ2_QUAD_PER_TILE_H3 = 0x84, + SC_QZ2_QUAD_PER_TILE_H4 = 0x85, + SC_QZ2_QUAD_PER_TILE_H5 = 0x86, + SC_QZ2_QUAD_PER_TILE_H6 = 0x87, + SC_QZ2_QUAD_PER_TILE_H7 = 0x88, + SC_QZ2_QUAD_PER_TILE_H8 = 0x89, + SC_QZ2_QUAD_PER_TILE_H9 = 0x8a, + SC_QZ2_QUAD_PER_TILE_H10 = 0x8b, + SC_QZ2_QUAD_PER_TILE_H11 = 0x8c, + SC_QZ2_QUAD_PER_TILE_H12 = 0x8d, + SC_QZ2_QUAD_PER_TILE_H13 = 0x8e, + SC_QZ2_QUAD_PER_TILE_H14 = 0x8f, + SC_QZ2_QUAD_PER_TILE_H15 = 0x90, + SC_QZ2_QUAD_PER_TILE_H16 = 0x91, + SC_QZ3_QUAD_PER_TILE_H0 = 0x92, + SC_QZ3_QUAD_PER_TILE_H1 = 0x93, + SC_QZ3_QUAD_PER_TILE_H2 = 0x94, + SC_QZ3_QUAD_PER_TILE_H3 = 0x95, + SC_QZ3_QUAD_PER_TILE_H4 = 0x96, + SC_QZ3_QUAD_PER_TILE_H5 = 0x97, + SC_QZ3_QUAD_PER_TILE_H6 = 0x98, + SC_QZ3_QUAD_PER_TILE_H7 = 0x99, + SC_QZ3_QUAD_PER_TILE_H8 = 0x9a, + SC_QZ3_QUAD_PER_TILE_H9 = 0x9b, + SC_QZ3_QUAD_PER_TILE_H10 = 0x9c, + SC_QZ3_QUAD_PER_TILE_H11 = 0x9d, + SC_QZ3_QUAD_PER_TILE_H12 = 0x9e, + SC_QZ3_QUAD_PER_TILE_H13 = 0x9f, + SC_QZ3_QUAD_PER_TILE_H14 = 0xa0, + SC_QZ3_QUAD_PER_TILE_H15 = 0xa1, + SC_QZ3_QUAD_PER_TILE_H16 = 0xa2, + SC_QZ0_QUAD_COUNT = 0xa3, + SC_QZ1_QUAD_COUNT = 0xa4, + SC_QZ2_QUAD_COUNT = 0xa5, + SC_QZ3_QUAD_COUNT = 0xa6, + SC_P0_HIZ_TILE_COUNT = 0xa7, + SC_P1_HIZ_TILE_COUNT = 0xa8, + SC_P2_HIZ_TILE_COUNT = 0xa9, + SC_P3_HIZ_TILE_COUNT = 0xaa, + SC_P0_HIZ_QUAD_PER_TILE_H0 = 0xab, + SC_P0_HIZ_QUAD_PER_TILE_H1 = 0xac, + SC_P0_HIZ_QUAD_PER_TILE_H2 = 0xad, + SC_P0_HIZ_QUAD_PER_TILE_H3 = 0xae, + SC_P0_HIZ_QUAD_PER_TILE_H4 = 0xaf, + SC_P0_HIZ_QUAD_PER_TILE_H5 = 0xb0, + SC_P0_HIZ_QUAD_PER_TILE_H6 = 0xb1, + SC_P0_HIZ_QUAD_PER_TILE_H7 = 0xb2, + SC_P0_HIZ_QUAD_PER_TILE_H8 = 0xb3, + SC_P0_HIZ_QUAD_PER_TILE_H9 = 0xb4, + SC_P0_HIZ_QUAD_PER_TILE_H10 = 0xb5, + SC_P0_HIZ_QUAD_PER_TILE_H11 = 0xb6, + SC_P0_HIZ_QUAD_PER_TILE_H12 = 0xb7, + SC_P0_HIZ_QUAD_PER_TILE_H13 = 0xb8, + SC_P0_HIZ_QUAD_PER_TILE_H14 = 0xb9, + SC_P0_HIZ_QUAD_PER_TILE_H15 = 0xba, + SC_P0_HIZ_QUAD_PER_TILE_H16 = 0xbb, + SC_P1_HIZ_QUAD_PER_TILE_H0 = 0xbc, + SC_P1_HIZ_QUAD_PER_TILE_H1 = 0xbd, + SC_P1_HIZ_QUAD_PER_TILE_H2 = 0xbe, + SC_P1_HIZ_QUAD_PER_TILE_H3 = 0xbf, + SC_P1_HIZ_QUAD_PER_TILE_H4 = 0xc0, + SC_P1_HIZ_QUAD_PER_TILE_H5 = 0xc1, + SC_P1_HIZ_QUAD_PER_TILE_H6 = 0xc2, + SC_P1_HIZ_QUAD_PER_TILE_H7 = 0xc3, + SC_P1_HIZ_QUAD_PER_TILE_H8 = 0xc4, + SC_P1_HIZ_QUAD_PER_TILE_H9 = 0xc5, + SC_P1_HIZ_QUAD_PER_TILE_H10 = 0xc6, + SC_P1_HIZ_QUAD_PER_TILE_H11 = 0xc7, + SC_P1_HIZ_QUAD_PER_TILE_H12 = 0xc8, + SC_P1_HIZ_QUAD_PER_TILE_H13 = 0xc9, + SC_P1_HIZ_QUAD_PER_TILE_H14 = 0xca, + SC_P1_HIZ_QUAD_PER_TILE_H15 = 0xcb, + SC_P1_HIZ_QUAD_PER_TILE_H16 = 0xcc, + SC_P2_HIZ_QUAD_PER_TILE_H0 = 0xcd, + SC_P2_HIZ_QUAD_PER_TILE_H1 = 0xce, + SC_P2_HIZ_QUAD_PER_TILE_H2 = 0xcf, + SC_P2_HIZ_QUAD_PER_TILE_H3 = 0xd0, + SC_P2_HIZ_QUAD_PER_TILE_H4 = 0xd1, + SC_P2_HIZ_QUAD_PER_TILE_H5 = 0xd2, + SC_P2_HIZ_QUAD_PER_TILE_H6 = 0xd3, + SC_P2_HIZ_QUAD_PER_TILE_H7 = 0xd4, + SC_P2_HIZ_QUAD_PER_TILE_H8 = 0xd5, + SC_P2_HIZ_QUAD_PER_TILE_H9 = 0xd6, + SC_P2_HIZ_QUAD_PER_TILE_H10 = 0xd7, + SC_P2_HIZ_QUAD_PER_TILE_H11 = 0xd8, + SC_P2_HIZ_QUAD_PER_TILE_H12 = 0xd9, + SC_P2_HIZ_QUAD_PER_TILE_H13 = 0xda, + SC_P2_HIZ_QUAD_PER_TILE_H14 = 0xdb, + SC_P2_HIZ_QUAD_PER_TILE_H15 = 0xdc, + SC_P2_HIZ_QUAD_PER_TILE_H16 = 0xdd, + SC_P3_HIZ_QUAD_PER_TILE_H0 = 0xde, + SC_P3_HIZ_QUAD_PER_TILE_H1 = 0xdf, + SC_P3_HIZ_QUAD_PER_TILE_H2 = 0xe0, + SC_P3_HIZ_QUAD_PER_TILE_H3 = 0xe1, + SC_P3_HIZ_QUAD_PER_TILE_H4 = 0xe2, + SC_P3_HIZ_QUAD_PER_TILE_H5 = 0xe3, + SC_P3_HIZ_QUAD_PER_TILE_H6 = 0xe4, + SC_P3_HIZ_QUAD_PER_TILE_H7 = 0xe5, + SC_P3_HIZ_QUAD_PER_TILE_H8 = 0xe6, + SC_P3_HIZ_QUAD_PER_TILE_H9 = 0xe7, + SC_P3_HIZ_QUAD_PER_TILE_H10 = 0xe8, + SC_P3_HIZ_QUAD_PER_TILE_H11 = 0xe9, + SC_P3_HIZ_QUAD_PER_TILE_H12 = 0xea, + SC_P3_HIZ_QUAD_PER_TILE_H13 = 0xeb, + SC_P3_HIZ_QUAD_PER_TILE_H14 = 0xec, + SC_P3_HIZ_QUAD_PER_TILE_H15 = 0xed, + SC_P3_HIZ_QUAD_PER_TILE_H16 = 0xee, + SC_P0_HIZ_QUAD_COUNT = 0xef, + SC_P1_HIZ_QUAD_COUNT = 0xf0, + SC_P2_HIZ_QUAD_COUNT = 0xf1, + SC_P3_HIZ_QUAD_COUNT = 0xf2, + SC_P0_DETAIL_QUAD_COUNT = 0xf3, + SC_P1_DETAIL_QUAD_COUNT = 0xf4, + SC_P2_DETAIL_QUAD_COUNT = 0xf5, + SC_P3_DETAIL_QUAD_COUNT = 0xf6, + SC_P0_DETAIL_QUAD_WITH_1_PIX = 0xf7, + SC_P0_DETAIL_QUAD_WITH_2_PIX = 0xf8, + SC_P0_DETAIL_QUAD_WITH_3_PIX = 0xf9, + SC_P0_DETAIL_QUAD_WITH_4_PIX = 0xfa, + SC_P1_DETAIL_QUAD_WITH_1_PIX = 0xfb, + SC_P1_DETAIL_QUAD_WITH_2_PIX = 0xfc, + SC_P1_DETAIL_QUAD_WITH_3_PIX = 0xfd, + SC_P1_DETAIL_QUAD_WITH_4_PIX = 0xfe, + SC_P2_DETAIL_QUAD_WITH_1_PIX = 0xff, + SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x100, + SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x101, + SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x102, + SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x103, + SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x104, + SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105, + SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x106, + SC_EARLYZ_QUAD_COUNT = 0x107, + SC_EARLYZ_QUAD_WITH_1_PIX = 0x108, + SC_EARLYZ_QUAD_WITH_2_PIX = 0x109, + SC_EARLYZ_QUAD_WITH_3_PIX = 0x10a, + SC_EARLYZ_QUAD_WITH_4_PIX = 0x10b, + SC_PKR_QUAD_PER_ROW_H1 = 0x10c, + SC_PKR_QUAD_PER_ROW_H2 = 0x10d, + SC_PKR_QUAD_PER_ROW_H3 = 0x10e, + SC_PKR_QUAD_PER_ROW_H4 = 0x10f, + SC_PKR_END_OF_VECTOR = 0x110, + SC_PKR_CONTROL_XFER = 0x111, + SC_PKR_DBHANG_FORCE_EOV = 0x112, + SC_REG_SCLK_BUSY = 0x113, + SC_GRP0_DYN_SCLK_BUSY = 0x114, + SC_GRP1_DYN_SCLK_BUSY = 0x115, + SC_GRP2_DYN_SCLK_BUSY = 0x116, + SC_GRP3_DYN_SCLK_BUSY = 0x117, + SC_GRP4_DYN_SCLK_BUSY = 0x118, + SC_PA0_SC_DATA_FIFO_RD = 0x119, + SC_PA0_SC_DATA_FIFO_WE = 0x11a, + SC_PA1_SC_DATA_FIFO_RD = 0x11b, + SC_PA1_SC_DATA_FIFO_WE = 0x11c, + SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x11d, + SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x11e, + SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x11f, + SC_PS_ARB_STALLED_FROM_BELOW = 0x120, + SC_PS_ARB_STARVED_FROM_ABOVE = 0x121, + SC_PS_ARB_SC_BUSY = 0x122, + SC_PS_ARB_PA_SC_BUSY = 0x123, + SC_PA2_SC_DATA_FIFO_RD = 0x124, + SC_PA2_SC_DATA_FIFO_WE = 0x125, + SC_PA3_SC_DATA_FIFO_RD = 0x126, + SC_PA3_SC_DATA_FIFO_WE = 0x127, + SC_PA_SC_DEALLOC_0_0_WE = 0x128, + SC_PA_SC_DEALLOC_0_1_WE = 0x129, + SC_PA_SC_DEALLOC_1_0_WE = 0x12a, + SC_PA_SC_DEALLOC_1_1_WE = 0x12b, + SC_PA_SC_DEALLOC_2_0_WE = 0x12c, + SC_PA_SC_DEALLOC_2_1_WE = 0x12d, + SC_PA_SC_DEALLOC_3_0_WE = 0x12e, + SC_PA_SC_DEALLOC_3_1_WE = 0x12f, + SC_PA0_SC_EOP_WE = 0x130, + SC_PA0_SC_EOPG_WE = 0x131, + SC_PA0_SC_EVENT_WE = 0x132, + SC_PA1_SC_EOP_WE = 0x133, + SC_PA1_SC_EOPG_WE = 0x134, + SC_PA1_SC_EVENT_WE = 0x135, + SC_PA2_SC_EOP_WE = 0x136, + SC_PA2_SC_EOPG_WE = 0x137, + SC_PA2_SC_EVENT_WE = 0x138, + SC_PA3_SC_EOP_WE = 0x139, + SC_PA3_SC_EOPG_WE = 0x13a, + SC_PA3_SC_EVENT_WE = 0x13b, + SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x13c, + SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x13d, + SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x13e, + SC_PS_ARB_EOP_POP_SYNC_POP = 0x13f, + SC_PS_ARB_EVENT_SYNC_POP = 0x140, + SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141, + SC_PA0_SC_FPOV_WE = 0x142, + SC_PA1_SC_FPOV_WE = 0x143, + SC_PA2_SC_FPOV_WE = 0x144, + SC_PA3_SC_FPOV_WE = 0x145, + SC_PA0_SC_LPOV_WE = 0x146, + SC_PA1_SC_LPOV_WE = 0x147, + SC_PA2_SC_LPOV_WE = 0x148, + SC_PA3_SC_LPOV_WE = 0x149, + SC_SC_SPI_DEALLOC_0_0 = 0x14a, + SC_SC_SPI_DEALLOC_0_1 = 0x14b, + SC_SC_SPI_DEALLOC_0_2 = 0x14c, + SC_SC_SPI_DEALLOC_1_0 = 0x14d, + SC_SC_SPI_DEALLOC_1_1 = 0x14e, + SC_SC_SPI_DEALLOC_1_2 = 0x14f, + SC_SC_SPI_DEALLOC_2_0 = 0x150, + SC_SC_SPI_DEALLOC_2_1 = 0x151, + SC_SC_SPI_DEALLOC_2_2 = 0x152, + SC_SC_SPI_DEALLOC_3_0 = 0x153, + SC_SC_SPI_DEALLOC_3_1 = 0x154, + SC_SC_SPI_DEALLOC_3_2 = 0x155, + SC_SC_SPI_FPOV_0 = 0x156, + SC_SC_SPI_FPOV_1 = 0x157, + SC_SC_SPI_FPOV_2 = 0x158, + SC_SC_SPI_FPOV_3 = 0x159, + SC_SC_SPI_EVENT = 0x15a, + SC_PS_TS_EVENT_FIFO_PUSH = 0x15b, + SC_PS_TS_EVENT_FIFO_POP = 0x15c, + SC_PS_CTX_DONE_FIFO_PUSH = 0x15d, + SC_PS_CTX_DONE_FIFO_POP = 0x15e, + SC_MULTICYCLE_BUBBLE_FREEZE = 0x15f, + SC_EOP_SYNC_WINDOW = 0x160, + SC_PA0_SC_NULL_WE = 0x161, + SC_PA0_SC_NULL_DEALLOC_WE = 0x162, + SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x163, + SC_PA0_SC_DATA_FIFO_EOP_RD = 0x164, + SC_PA0_SC_DEALLOC_0_RD = 0x165, + SC_PA0_SC_DEALLOC_1_RD = 0x166, + SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x167, + SC_PA1_SC_DATA_FIFO_EOP_RD = 0x168, + SC_PA1_SC_DEALLOC_0_RD = 0x169, + SC_PA1_SC_DEALLOC_1_RD = 0x16a, + SC_PA1_SC_NULL_WE = 0x16b, + SC_PA1_SC_NULL_DEALLOC_WE = 0x16c, + SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x16d, + SC_PA2_SC_DATA_FIFO_EOP_RD = 0x16e, + SC_PA2_SC_DEALLOC_0_RD = 0x16f, + SC_PA2_SC_DEALLOC_1_RD = 0x170, + SC_PA2_SC_NULL_WE = 0x171, + SC_PA2_SC_NULL_DEALLOC_WE = 0x172, + SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x173, + SC_PA3_SC_DATA_FIFO_EOP_RD = 0x174, + SC_PA3_SC_DEALLOC_0_RD = 0x175, + SC_PA3_SC_DEALLOC_1_RD = 0x176, + SC_PA3_SC_NULL_WE = 0x177, + SC_PA3_SC_NULL_DEALLOC_WE = 0x178, + SC_PS_PA0_SC_FIFO_EMPTY = 0x179, + SC_PS_PA0_SC_FIFO_FULL = 0x17a, + SC_PA0_PS_DATA_SEND = 0x17b, + SC_PS_PA1_SC_FIFO_EMPTY = 0x17c, + SC_PS_PA1_SC_FIFO_FULL = 0x17d, + SC_PA1_PS_DATA_SEND = 0x17e, + SC_PS_PA2_SC_FIFO_EMPTY = 0x17f, + SC_PS_PA2_SC_FIFO_FULL = 0x180, + SC_PA2_PS_DATA_SEND = 0x181, + SC_PS_PA3_SC_FIFO_EMPTY = 0x182, + SC_PS_PA3_SC_FIFO_FULL = 0x183, + SC_PA3_PS_DATA_SEND = 0x184, + SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x185, + SC_BUSY_CNT_NOT_ZERO = 0x186, + SC_BM_BUSY = 0x187, + SC_BACKEND_BUSY = 0x188, + SC_SCF_SCB_INTERFACE_BUSY = 0x189, + SC_SCB_BUSY = 0x18a, + SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x18b, + SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x18c, +} SC_PERFCNT_SEL; +typedef enum SePairXsel { + RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x3, +} SePairXsel; +typedef enum SePairYsel { + RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x3, +} SePairYsel; +typedef enum SePairMap { + RASTER_CONFIG_SE_PAIR_MAP_0 = 0x0, + RASTER_CONFIG_SE_PAIR_MAP_1 = 0x1, + RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2, + RASTER_CONFIG_SE_PAIR_MAP_3 = 0x3, +} SePairMap; +typedef enum SeXsel { + RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x3, +} SeXsel; +typedef enum SeYsel { + RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x3, +} SeYsel; +typedef enum SeMap { + RASTER_CONFIG_SE_MAP_0 = 0x0, + RASTER_CONFIG_SE_MAP_1 = 0x1, + RASTER_CONFIG_SE_MAP_2 = 0x2, + RASTER_CONFIG_SE_MAP_3 = 0x3, +} SeMap; +typedef enum ScXsel { + RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x3, +} ScXsel; +typedef enum ScYsel { + RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x3, +} ScYsel; +typedef enum ScMap { + RASTER_CONFIG_SC_MAP_0 = 0x0, + RASTER_CONFIG_SC_MAP_1 = 0x1, + RASTER_CONFIG_SC_MAP_2 = 0x2, + RASTER_CONFIG_SC_MAP_3 = 0x3, +} ScMap; +typedef enum PkrXsel2 { + RASTER_CONFIG_PKR_XSEL2_0 = 0x0, + RASTER_CONFIG_PKR_XSEL2_1 = 0x1, + RASTER_CONFIG_PKR_XSEL2_2 = 0x2, + RASTER_CONFIG_PKR_XSEL2_3 = 0x3, +} PkrXsel2; +typedef enum PkrXsel { + RASTER_CONFIG_PKR_XSEL_0 = 0x0, + RASTER_CONFIG_PKR_XSEL_1 = 0x1, + RASTER_CONFIG_PKR_XSEL_2 = 0x2, + RASTER_CONFIG_PKR_XSEL_3 = 0x3, +} PkrXsel; +typedef enum PkrYsel { + RASTER_CONFIG_PKR_YSEL_0 = 0x0, + RASTER_CONFIG_PKR_YSEL_1 = 0x1, + RASTER_CONFIG_PKR_YSEL_2 = 0x2, + RASTER_CONFIG_PKR_YSEL_3 = 0x3, +} PkrYsel; +typedef enum PkrMap { + RASTER_CONFIG_PKR_MAP_0 = 0x0, + RASTER_CONFIG_PKR_MAP_1 = 0x1, + RASTER_CONFIG_PKR_MAP_2 = 0x2, + RASTER_CONFIG_PKR_MAP_3 = 0x3, +} PkrMap; +typedef enum RbXsel { + RASTER_CONFIG_RB_XSEL_0 = 0x0, + RASTER_CONFIG_RB_XSEL_1 = 0x1, +} RbXsel; +typedef enum RbYsel { + RASTER_CONFIG_RB_YSEL_0 = 0x0, + RASTER_CONFIG_RB_YSEL_1 = 0x1, +} RbYsel; +typedef enum RbXsel2 { + RASTER_CONFIG_RB_XSEL2_0 = 0x0, + RASTER_CONFIG_RB_XSEL2_1 = 0x1, + RASTER_CONFIG_RB_XSEL2_2 = 0x2, + RASTER_CONFIG_RB_XSEL2_3 = 0x3, +} RbXsel2; +typedef enum RbMap { + RASTER_CONFIG_RB_MAP_0 = 0x0, + RASTER_CONFIG_RB_MAP_1 = 0x1, + RASTER_CONFIG_RB_MAP_2 = 0x2, + RASTER_CONFIG_RB_MAP_3 = 0x3, +} RbMap; +typedef enum CSDATA_TYPE { + CSDATA_TYPE_TG = 0x0, + CSDATA_TYPE_STATE = 0x1, + CSDATA_TYPE_EVENT = 0x2, + CSDATA_TYPE_PRIVATE = 0x3, +} CSDATA_TYPE; +#define CSDATA_TYPE_WIDTH 0x2 +#define CSDATA_ADDR_WIDTH 0x7 +#define CSDATA_DATA_WIDTH 0x20 +typedef enum SPI_SAMPLE_CNTL { + CENTROIDS_ONLY = 0x0, + CENTERS_ONLY = 0x1, + CENTROIDS_AND_CENTERS = 0x2, + UNDEF = 0x3, +} SPI_SAMPLE_CNTL; +typedef enum SPI_FOG_MODE { + SPI_FOG_NONE = 0x0, + SPI_FOG_EXP = 0x1, + SPI_FOG_EXP2 = 0x2, + SPI_FOG_LINEAR = 0x3, +} SPI_FOG_MODE; +typedef enum SPI_PNT_SPRITE_OVERRIDE { + SPI_PNT_SPRITE_SEL_0 = 0x0, + SPI_PNT_SPRITE_SEL_1 = 0x1, + SPI_PNT_SPRITE_SEL_S = 0x2, + SPI_PNT_SPRITE_SEL_T = 0x3, + SPI_PNT_SPRITE_SEL_NONE = 0x4, +} SPI_PNT_SPRITE_OVERRIDE; +typedef enum SPI_PERFCNT_SEL { + SPI_PERF_VS_WINDOW_VALID = 0x0, + SPI_PERF_VS_BUSY = 0x1, + SPI_PERF_VS_FIRST_WAVE = 0x2, + SPI_PERF_VS_LAST_WAVE = 0x3, + SPI_PERF_VS_LSHS_DEALLOC = 0x4, + SPI_PERF_VS_PC_STALL = 0x5, + SPI_PERF_VS_POS0_STALL = 0x6, + SPI_PERF_VS_POS1_STALL = 0x7, + SPI_PERF_VS_CRAWLER_STALL = 0x8, + SPI_PERF_VS_EVENT_WAVE = 0x9, + SPI_PERF_VS_WAVE = 0xa, + SPI_PERF_VS_PERS_UPD_FULL0 = 0xb, + SPI_PERF_VS_PERS_UPD_FULL1 = 0xc, + SPI_PERF_VS_LATE_ALLOC_FULL = 0xd, + SPI_PERF_VS_FIRST_SUBGRP = 0xe, + SPI_PERF_VS_LAST_SUBGRP = 0xf, + SPI_PERF_GS_WINDOW_VALID = 0x10, + SPI_PERF_GS_BUSY = 0x11, + SPI_PERF_GS_CRAWLER_STALL = 0x12, + SPI_PERF_GS_EVENT_WAVE = 0x13, + SPI_PERF_GS_WAVE = 0x14, + SPI_PERF_GS_PERS_UPD_FULL0 = 0x15, + SPI_PERF_GS_PERS_UPD_FULL1 = 0x16, + SPI_PERF_GS_FIRST_SUBGRP = 0x17, + SPI_PERF_GS_LAST_SUBGRP = 0x18, + SPI_PERF_ES_WINDOW_VALID = 0x19, + SPI_PERF_ES_BUSY = 0x1a, + SPI_PERF_ES_CRAWLER_STALL = 0x1b, + SPI_PERF_ES_FIRST_WAVE = 0x1c, + SPI_PERF_ES_LAST_WAVE = 0x1d, + SPI_PERF_ES_LSHS_DEALLOC = 0x1e, + SPI_PERF_ES_EVENT_WAVE = 0x1f, + SPI_PERF_ES_WAVE = 0x20, + SPI_PERF_ES_PERS_UPD_FULL0 = 0x21, + SPI_PERF_ES_PERS_UPD_FULL1 = 0x22, + SPI_PERF_ES_FIRST_SUBGRP = 0x23, + SPI_PERF_ES_LAST_SUBGRP = 0x24, + SPI_PERF_HS_WINDOW_VALID = 0x25, + SPI_PERF_HS_BUSY = 0x26, + SPI_PERF_HS_CRAWLER_STALL = 0x27, + SPI_PERF_HS_FIRST_WAVE = 0x28, + SPI_PERF_HS_LAST_WAVE = 0x29, + SPI_PERF_HS_LSHS_DEALLOC = 0x2a, + SPI_PERF_HS_EVENT_WAVE = 0x2b, + SPI_PERF_HS_WAVE = 0x2c, + SPI_PERF_HS_PERS_UPD_FULL0 = 0x2d, + SPI_PERF_HS_PERS_UPD_FULL1 = 0x2e, + SPI_PERF_LS_WINDOW_VALID = 0x2f, + SPI_PERF_LS_BUSY = 0x30, + SPI_PERF_LS_CRAWLER_STALL = 0x31, + SPI_PERF_LS_FIRST_WAVE = 0x32, + SPI_PERF_LS_LAST_WAVE = 0x33, + SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x34, + SPI_PERF_LS_EVENT_WAVE = 0x35, + SPI_PERF_LS_WAVE = 0x36, + SPI_PERF_LS_PERS_UPD_FULL0 = 0x37, + SPI_PERF_LS_PERS_UPD_FULL1 = 0x38, + SPI_PERF_CSG_WINDOW_VALID = 0x39, + SPI_PERF_CSG_BUSY = 0x3a, + SPI_PERF_CSG_NUM_THREADGROUPS = 0x3b, + SPI_PERF_CSG_CRAWLER_STALL = 0x3c, + SPI_PERF_CSG_EVENT_WAVE = 0x3d, + SPI_PERF_CSG_WAVE = 0x3e, + SPI_PERF_CSN_WINDOW_VALID = 0x3f, + SPI_PERF_CSN_BUSY = 0x40, + SPI_PERF_CSN_NUM_THREADGROUPS = 0x41, + SPI_PERF_CSN_CRAWLER_STALL = 0x42, + SPI_PERF_CSN_EVENT_WAVE = 0x43, + SPI_PERF_CSN_WAVE = 0x44, + SPI_PERF_PS_CTL_WINDOW_VALID = 0x45, + SPI_PERF_PS_CTL_BUSY = 0x46, + SPI_PERF_PS_CTL_ACTIVE = 0x47, + SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x48, + SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x49, + SPI_PERF_PS_CTL_EVENT_WAVE = 0x4a, + SPI_PERF_PS_CTL_WAVE = 0x4b, + SPI_PERF_PS_CTL_OPT_WAVE = 0x4c, + SPI_PERF_PS_CTL_PASS_BIN0 = 0x4d, + SPI_PERF_PS_CTL_PASS_BIN1 = 0x4e, + SPI_PERF_PS_CTL_FPOS_BIN2 = 0x4f, + SPI_PERF_PS_CTL_PRIM_BIN0 = 0x50, + SPI_PERF_PS_CTL_PRIM_BIN1 = 0x51, + SPI_PERF_PS_CTL_CNF_BIN2 = 0x52, + SPI_PERF_PS_CTL_CNF_BIN3 = 0x53, + SPI_PERF_PS_CTL_CRAWLER_STALL = 0x54, + SPI_PERF_PS_CTL_LDS_RES_FULL = 0x55, + SPI_PERF_PS_PERS_UPD_FULL0 = 0x56, + SPI_PERF_PS_PERS_UPD_FULL1 = 0x57, + SPI_PERF_PIX_ALLOC_PEND_CNT = 0x58, + SPI_PERF_PIX_ALLOC_SCB_STALL = 0x59, + SPI_PERF_PIX_ALLOC_DB0_STALL = 0x5a, + SPI_PERF_PIX_ALLOC_DB1_STALL = 0x5b, + SPI_PERF_PIX_ALLOC_DB2_STALL = 0x5c, + SPI_PERF_PIX_ALLOC_DB3_STALL = 0x5d, + SPI_PERF_LDS0_PC_VALID = 0x5e, + SPI_PERF_LDS1_PC_VALID = 0x5f, + SPI_PERF_RA_PIPE_REQ_BIN2 = 0x60, + SPI_PERF_RA_TASK_REQ_BIN3 = 0x61, + SPI_PERF_RA_WR_CTL_FULL = 0x62, + SPI_PERF_RA_REQ_NO_ALLOC = 0x63, + SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x64, + SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x65, + SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x66, + SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x67, + SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x68, + SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x69, + SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x6a, + SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x6b, + SPI_PERF_RA_RES_STALL_PS = 0x6c, + SPI_PERF_RA_RES_STALL_VS = 0x6d, + SPI_PERF_RA_RES_STALL_GS = 0x6e, + SPI_PERF_RA_RES_STALL_ES = 0x6f, + SPI_PERF_RA_RES_STALL_HS = 0x70, + SPI_PERF_RA_RES_STALL_LS = 0x71, + SPI_PERF_RA_RES_STALL_CSG = 0x72, + SPI_PERF_RA_RES_STALL_CSN = 0x73, + SPI_PERF_RA_TMP_STALL_PS = 0x74, + SPI_PERF_RA_TMP_STALL_VS = 0x75, + SPI_PERF_RA_TMP_STALL_GS = 0x76, + SPI_PERF_RA_TMP_STALL_ES = 0x77, + SPI_PERF_RA_TMP_STALL_HS = 0x78, + SPI_PERF_RA_TMP_STALL_LS = 0x79, + SPI_PERF_RA_TMP_STALL_CSG = 0x7a, + SPI_PERF_RA_TMP_STALL_CSN = 0x7b, + SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x7c, + SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x7d, + SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x7e, + SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x7f, + SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x80, + SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x81, + SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x82, + SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x83, + SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x84, + SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x85, + SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x86, + SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x87, + SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x88, + SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x89, + SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x8a, + SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x8b, + SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x8c, + SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x8d, + SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x8e, + SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x8f, + SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x90, + SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x91, + SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x92, + SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x93, + SPI_PERF_RA_LDS_CU_FULL_PS = 0x94, + SPI_PERF_RA_LDS_CU_FULL_LS = 0x95, + SPI_PERF_RA_LDS_CU_FULL_ES = 0x96, + SPI_PERF_RA_LDS_CU_FULL_CSG = 0x97, + SPI_PERF_RA_LDS_CU_FULL_CSN = 0x98, + SPI_PERF_RA_BAR_CU_FULL_HS = 0x99, + SPI_PERF_RA_BAR_CU_FULL_CSG = 0x9a, + SPI_PERF_RA_BAR_CU_FULL_CSN = 0x9b, + SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x9c, + SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x9d, + SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x9e, + SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x9f, + SPI_PERF_RA_WVLIM_STALL_PS = 0xa0, + SPI_PERF_RA_WVLIM_STALL_VS = 0xa1, + SPI_PERF_RA_WVLIM_STALL_GS = 0xa2, + SPI_PERF_RA_WVLIM_STALL_ES = 0xa3, + SPI_PERF_RA_WVLIM_STALL_HS = 0xa4, + SPI_PERF_RA_WVLIM_STALL_LS = 0xa5, + SPI_PERF_RA_WVLIM_STALL_CSG = 0xa6, + SPI_PERF_RA_WVLIM_STALL_CSN = 0xa7, + SPI_PERF_RA_PS_LOCK_NA = 0xa8, + SPI_PERF_RA_VS_LOCK = 0xa9, + SPI_PERF_RA_GS_LOCK = 0xaa, + SPI_PERF_RA_ES_LOCK = 0xab, + SPI_PERF_RA_HS_LOCK = 0xac, + SPI_PERF_RA_LS_LOCK = 0xad, + SPI_PERF_RA_CSG_LOCK = 0xae, + SPI_PERF_RA_CSN_LOCK = 0xaf, + SPI_PERF_RA_RSV_UPD = 0xb0, + SPI_PERF_EXP_ARB_COL_CNT = 0xb1, + SPI_PERF_EXP_ARB_PAR_CNT = 0xb2, + SPI_PERF_EXP_ARB_POS_CNT = 0xb3, + SPI_PERF_EXP_ARB_GDS_CNT = 0xb4, + SPI_PERF_CLKGATE_BUSY_STALL = 0xb5, + SPI_PERF_CLKGATE_ACTIVE_STALL = 0xb6, + SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0xb7, + SPI_PERF_CLKGATE_CGTT_DYN_ON = 0xb8, + SPI_PERF_CLKGATE_CGTT_REG_ON = 0xb9, + SPI_PERF_NUM_VS_POS_EXPORTS = 0xba, + SPI_PERF_NUM_VS_PARAM_EXPORTS = 0xbb, + SPI_PERF_NUM_PS_COL_EXPORTS = 0xbc, + SPI_PERF_ES_GRP_FIFO_FULL = 0xbd, + SPI_PERF_GS_GRP_FIFO_FULL = 0xbe, + SPI_PERF_HS_GRP_FIFO_FULL = 0xbf, + SPI_PERF_LS_GRP_FIFO_FULL = 0xc0, + SPI_PERF_VS_ALLOC_CNT = 0xc1, + SPI_PERF_VS_LATE_ALLOC_ACCUM = 0xc2, + SPI_PERF_PC_ALLOC_CNT = 0xc3, + SPI_PERF_PC_ALLOC_ACCUM = 0xc4, +} SPI_PERFCNT_SEL; +typedef enum SPI_SHADER_FORMAT { + SPI_SHADER_NONE = 0x0, + SPI_SHADER_1COMP = 0x1, + SPI_SHADER_2COMP = 0x2, + SPI_SHADER_4COMPRESS = 0x3, + SPI_SHADER_4COMP = 0x4, +} SPI_SHADER_FORMAT; +typedef enum SPI_SHADER_EX_FORMAT { + SPI_SHADER_ZERO = 0x0, + SPI_SHADER_32_R = 0x1, + SPI_SHADER_32_GR = 0x2, + SPI_SHADER_32_AR = 0x3, + SPI_SHADER_FP16_ABGR = 0x4, + SPI_SHADER_UNORM16_ABGR = 0x5, + SPI_SHADER_SNORM16_ABGR = 0x6, + SPI_SHADER_UINT16_ABGR = 0x7, + SPI_SHADER_SINT16_ABGR = 0x8, + SPI_SHADER_32_ABGR = 0x9, +} SPI_SHADER_EX_FORMAT; +typedef enum CLKGATE_SM_MODE { + ON_SEQ = 0x0, + OFF_SEQ = 0x1, + PROG_SEQ = 0x2, + READ_SEQ = 0x3, + SM_MODE_RESERVED = 0x4, +} CLKGATE_SM_MODE; +typedef enum CLKGATE_BASE_MODE { + MULT_8 = 0x0, + MULT_16 = 0x1, +} CLKGATE_BASE_MODE; +typedef enum SQ_TEX_CLAMP { + SQ_TEX_WRAP = 0x0, + SQ_TEX_MIRROR = 0x1, + SQ_TEX_CLAMP_LAST_TEXEL = 0x2, + SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x3, + SQ_TEX_CLAMP_HALF_BORDER = 0x4, + SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x5, + SQ_TEX_CLAMP_BORDER = 0x6, + SQ_TEX_MIRROR_ONCE_BORDER = 0x7, +} SQ_TEX_CLAMP; +typedef enum SQ_TEX_XY_FILTER { + SQ_TEX_XY_FILTER_POINT = 0x0, + SQ_TEX_XY_FILTER_BILINEAR = 0x1, + SQ_TEX_XY_FILTER_ANISO_POINT = 0x2, + SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x3, +} SQ_TEX_XY_FILTER; +typedef enum SQ_TEX_Z_FILTER { + SQ_TEX_Z_FILTER_NONE = 0x0, + SQ_TEX_Z_FILTER_POINT = 0x1, + SQ_TEX_Z_FILTER_LINEAR = 0x2, +} SQ_TEX_Z_FILTER; +typedef enum SQ_TEX_MIP_FILTER { + SQ_TEX_MIP_FILTER_NONE = 0x0, + SQ_TEX_MIP_FILTER_POINT = 0x1, + SQ_TEX_MIP_FILTER_LINEAR = 0x2, + SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x3, +} SQ_TEX_MIP_FILTER; +typedef enum SQ_TEX_ANISO_RATIO { + SQ_TEX_ANISO_RATIO_1 = 0x0, + SQ_TEX_ANISO_RATIO_2 = 0x1, + SQ_TEX_ANISO_RATIO_4 = 0x2, + SQ_TEX_ANISO_RATIO_8 = 0x3, + SQ_TEX_ANISO_RATIO_16 = 0x4, +} SQ_TEX_ANISO_RATIO; +typedef enum SQ_TEX_DEPTH_COMPARE { + SQ_TEX_DEPTH_COMPARE_NEVER = 0x0, + SQ_TEX_DEPTH_COMPARE_LESS = 0x1, + SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2, + SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x3, + SQ_TEX_DEPTH_COMPARE_GREATER = 0x4, + SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x5, + SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x6, + SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x7, +} SQ_TEX_DEPTH_COMPARE; +typedef enum SQ_TEX_BORDER_COLOR { + SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x0, + SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x1, + SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2, + SQ_TEX_BORDER_COLOR_REGISTER = 0x3, +} SQ_TEX_BORDER_COLOR; +typedef enum SQ_RSRC_BUF_TYPE { + SQ_RSRC_BUF = 0x0, + SQ_RSRC_BUF_RSVD_1 = 0x1, + SQ_RSRC_BUF_RSVD_2 = 0x2, + SQ_RSRC_BUF_RSVD_3 = 0x3, +} SQ_RSRC_BUF_TYPE; +typedef enum SQ_RSRC_IMG_TYPE { + SQ_RSRC_IMG_RSVD_0 = 0x0, + SQ_RSRC_IMG_RSVD_1 = 0x1, + SQ_RSRC_IMG_RSVD_2 = 0x2, + SQ_RSRC_IMG_RSVD_3 = 0x3, + SQ_RSRC_IMG_RSVD_4 = 0x4, + SQ_RSRC_IMG_RSVD_5 = 0x5, + SQ_RSRC_IMG_RSVD_6 = 0x6, + SQ_RSRC_IMG_RSVD_7 = 0x7, + SQ_RSRC_IMG_1D = 0x8, + SQ_RSRC_IMG_2D = 0x9, + SQ_RSRC_IMG_3D = 0xa, + SQ_RSRC_IMG_CUBE = 0xb, + SQ_RSRC_IMG_1D_ARRAY = 0xc, + SQ_RSRC_IMG_2D_ARRAY = 0xd, + SQ_RSRC_IMG_2D_MSAA = 0xe, + SQ_RSRC_IMG_2D_MSAA_ARRAY = 0xf, +} SQ_RSRC_IMG_TYPE; +typedef enum SQ_RSRC_FLAT_TYPE { + SQ_RSRC_FLAT_RSVD_0 = 0x0, + SQ_RSRC_FLAT = 0x1, + SQ_RSRC_FLAT_RSVD_2 = 0x2, + SQ_RSRC_FLAT_RSVD_3 = 0x3, +} SQ_RSRC_FLAT_TYPE; +typedef enum SQ_IMG_FILTER_TYPE { + SQ_IMG_FILTER_MODE_BLEND = 0x0, + SQ_IMG_FILTER_MODE_MIN = 0x1, + SQ_IMG_FILTER_MODE_MAX = 0x2, +} SQ_IMG_FILTER_TYPE; +typedef enum SQ_SEL_XYZW01 { + SQ_SEL_0 = 0x0, + SQ_SEL_1 = 0x1, + SQ_SEL_RESERVED_0 = 0x2, + SQ_SEL_RESERVED_1 = 0x3, + SQ_SEL_X = 0x4, + SQ_SEL_Y = 0x5, + SQ_SEL_Z = 0x6, + SQ_SEL_W = 0x7, +} SQ_SEL_XYZW01; +typedef enum SQ_WAVE_TYPE { + SQ_WAVE_TYPE_PS = 0x0, + SQ_WAVE_TYPE_VS = 0x1, + SQ_WAVE_TYPE_GS = 0x2, + SQ_WAVE_TYPE_ES = 0x3, + SQ_WAVE_TYPE_HS = 0x4, + SQ_WAVE_TYPE_LS = 0x5, + SQ_WAVE_TYPE_CS = 0x6, + SQ_WAVE_TYPE_PS1 = 0x7, +} SQ_WAVE_TYPE; +typedef enum SQ_THREAD_TRACE_TOKEN_TYPE { + SQ_THREAD_TRACE_TOKEN_MISC = 0x0, + SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x1, + SQ_THREAD_TRACE_TOKEN_REG = 0x2, + SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x3, + SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x4, + SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x5, + SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x6, + SQ_THREAD_TRACE_TOKEN_EVENT = 0x7, + SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x8, + SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x9, + SQ_THREAD_TRACE_TOKEN_INST = 0xa, + SQ_THREAD_TRACE_TOKEN_INST_PC = 0xb, + SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0xc, + SQ_THREAD_TRACE_TOKEN_ISSUE = 0xd, + SQ_THREAD_TRACE_TOKEN_PERF = 0xe, + SQ_THREAD_TRACE_TOKEN_REG_CS = 0xf, +} SQ_THREAD_TRACE_TOKEN_TYPE; +typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE { + SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x0, + SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x1, + SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2, + SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x3, + SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x4, + SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x5, + SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x6, + SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x7, +} SQ_THREAD_TRACE_MISC_TOKEN_TYPE; +typedef enum SQ_THREAD_TRACE_INST_TYPE { + SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x0, + SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x1, + SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2, + SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x3, + SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x4, + SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x5, + SQ_THREAD_TRACE_INST_TYPE_LDS = 0x6, + SQ_THREAD_TRACE_INST_TYPE_PC = 0x7, + SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x8, + SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x9, + SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0xa, + SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0xb, + SQ_THREAD_TRACE_INST_TYPE_JUMP = 0xc, + SQ_THREAD_TRACE_INST_TYPE_NEXT = 0xd, + SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0xe, + SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0xf, + SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x10, + SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x11, + SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x12, + SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x13, + SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x14, + SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x15, + SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x16, + SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x17, + SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x18, +} SQ_THREAD_TRACE_INST_TYPE; +typedef enum SQ_THREAD_TRACE_REG_TYPE { + SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x0, + SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x1, + SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2, + SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x3, + SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x4, + SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x5, + SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x6, + SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x7, +} SQ_THREAD_TRACE_REG_TYPE; +typedef enum SQ_THREAD_TRACE_REG_OP { + SQ_THREAD_TRACE_REG_OP_READ = 0x0, + SQ_THREAD_TRACE_REG_OP_WRITE = 0x1, +} SQ_THREAD_TRACE_REG_OP; +typedef enum SQ_THREAD_TRACE_MODE_SEL { + SQ_THREAD_TRACE_MODE_OFF = 0x0, + SQ_THREAD_TRACE_MODE_ON = 0x1, +} SQ_THREAD_TRACE_MODE_SEL; +typedef enum SQ_THREAD_TRACE_CAPTURE_MODE { + SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x0, + SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x1, + SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2, +} SQ_THREAD_TRACE_CAPTURE_MODE; +typedef enum SQ_THREAD_TRACE_VM_ID_MASK { + SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x0, + SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x1, + SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2, +} SQ_THREAD_TRACE_VM_ID_MASK; +typedef enum SQ_THREAD_TRACE_WAVE_MASK { + SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x0, + SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x1, +} SQ_THREAD_TRACE_WAVE_MASK; +typedef enum SQ_THREAD_TRACE_ISSUE { + SQ_THREAD_TRACE_ISSUE_NULL = 0x0, + SQ_THREAD_TRACE_ISSUE_STALL = 0x1, + SQ_THREAD_TRACE_ISSUE_INST = 0x2, + SQ_THREAD_TRACE_ISSUE_IMMED = 0x3, +} SQ_THREAD_TRACE_ISSUE; +typedef enum SQ_THREAD_TRACE_ISSUE_MASK { + SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x0, + SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x1, + SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2, + SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x3, +} SQ_THREAD_TRACE_ISSUE_MASK; +typedef enum SQ_PERF_SEL { + SQ_PERF_SEL_NONE = 0x0, + SQ_PERF_SEL_ACCUM_PREV = 0x1, + SQ_PERF_SEL_CYCLES = 0x2, + SQ_PERF_SEL_BUSY_CYCLES = 0x3, + SQ_PERF_SEL_WAVES = 0x4, + SQ_PERF_SEL_LEVEL_WAVES = 0x5, + SQ_PERF_SEL_WAVES_EQ_64 = 0x6, + SQ_PERF_SEL_WAVES_LT_64 = 0x7, + SQ_PERF_SEL_WAVES_LT_48 = 0x8, + SQ_PERF_SEL_WAVES_LT_32 = 0x9, + SQ_PERF_SEL_WAVES_LT_16 = 0xa, + SQ_PERF_SEL_WAVES_CU = 0xb, + SQ_PERF_SEL_LEVEL_WAVES_CU = 0xc, + SQ_PERF_SEL_BUSY_CU_CYCLES = 0xd, + SQ_PERF_SEL_ITEMS = 0xe, + SQ_PERF_SEL_QUADS = 0xf, + SQ_PERF_SEL_EVENTS = 0x10, + SQ_PERF_SEL_SURF_SYNCS = 0x11, + SQ_PERF_SEL_TTRACE_REQS = 0x12, + SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x13, + SQ_PERF_SEL_TTRACE_STALL = 0x14, + SQ_PERF_SEL_MSG_CNTR = 0x15, + SQ_PERF_SEL_MSG_PERF = 0x16, + SQ_PERF_SEL_MSG_GSCNT = 0x17, + SQ_PERF_SEL_MSG_INTERRUPT = 0x18, + SQ_PERF_SEL_INSTS = 0x19, + SQ_PERF_SEL_INSTS_VALU = 0x1a, + SQ_PERF_SEL_INSTS_VMEM_WR = 0x1b, + SQ_PERF_SEL_INSTS_VMEM_RD = 0x1c, + SQ_PERF_SEL_INSTS_VMEM = 0x1d, + SQ_PERF_SEL_INSTS_SALU = 0x1e, + SQ_PERF_SEL_INSTS_SMEM = 0x1f, + SQ_PERF_SEL_INSTS_FLAT = 0x20, + SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x21, + SQ_PERF_SEL_INSTS_LDS = 0x22, + SQ_PERF_SEL_INSTS_GDS = 0x23, + SQ_PERF_SEL_INSTS_EXP = 0x24, + SQ_PERF_SEL_INSTS_EXP_GDS = 0x25, + SQ_PERF_SEL_INSTS_BRANCH = 0x26, + SQ_PERF_SEL_INSTS_SENDMSG = 0x27, + SQ_PERF_SEL_INSTS_VSKIPPED = 0x28, + SQ_PERF_SEL_INST_LEVEL_VMEM = 0x29, + SQ_PERF_SEL_INST_LEVEL_SMEM = 0x2a, + SQ_PERF_SEL_INST_LEVEL_LDS = 0x2b, + SQ_PERF_SEL_INST_LEVEL_GDS = 0x2c, + SQ_PERF_SEL_INST_LEVEL_EXP = 0x2d, + SQ_PERF_SEL_WAVE_CYCLES = 0x2e, + SQ_PERF_SEL_WAVE_READY = 0x2f, + SQ_PERF_SEL_WAIT_CNT_VM = 0x30, + SQ_PERF_SEL_WAIT_CNT_LGKM = 0x31, + SQ_PERF_SEL_WAIT_CNT_EXP = 0x32, + SQ_PERF_SEL_WAIT_CNT_ANY = 0x33, + SQ_PERF_SEL_WAIT_BARRIER = 0x34, + SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x35, + SQ_PERF_SEL_WAIT_SLEEP = 0x36, + SQ_PERF_SEL_WAIT_OTHER = 0x37, + SQ_PERF_SEL_WAIT_ANY = 0x38, + SQ_PERF_SEL_WAIT_TTRACE = 0x39, + SQ_PERF_SEL_WAIT_IFETCH = 0x3a, + SQ_PERF_SEL_WAIT_INST_VMEM = 0x3b, + SQ_PERF_SEL_WAIT_INST_SCA = 0x3c, + SQ_PERF_SEL_WAIT_INST_LDS = 0x3d, + SQ_PERF_SEL_WAIT_INST_VALU = 0x3e, + SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x3f, + SQ_PERF_SEL_WAIT_INST_MISC = 0x40, + SQ_PERF_SEL_WAIT_INST_FLAT = 0x41, + SQ_PERF_SEL_ACTIVE_INST_ANY = 0x42, + SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x43, + SQ_PERF_SEL_ACTIVE_INST_LDS = 0x44, + SQ_PERF_SEL_ACTIVE_INST_VALU = 0x45, + SQ_PERF_SEL_ACTIVE_INST_SCA = 0x46, + SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x47, + SQ_PERF_SEL_ACTIVE_INST_MISC = 0x48, + SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x49, + SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x4a, + SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x4b, + SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x4c, + SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x4d, + SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x4e, + SQ_PERF_SEL_INST_CYCLES_VMEM = 0x4f, + SQ_PERF_SEL_INST_CYCLES_LDS = 0x50, + SQ_PERF_SEL_INST_CYCLES_VALU = 0x51, + SQ_PERF_SEL_INST_CYCLES_EXP = 0x52, + SQ_PERF_SEL_INST_CYCLES_GDS = 0x53, + SQ_PERF_SEL_INST_CYCLES_SCA = 0x54, + SQ_PERF_SEL_INST_CYCLES_SMEM = 0x55, + SQ_PERF_SEL_INST_CYCLES_SALU = 0x56, + SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x57, + SQ_PERF_SEL_INST_CYCLES_MISC = 0x58, + SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x59, + SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x5a, + SQ_PERF_SEL_IFETCH = 0x5b, + SQ_PERF_SEL_IFETCH_LEVEL = 0x5c, + SQ_PERF_SEL_CBRANCH_FORK = 0x5d, + SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x5e, + SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x5f, + SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x60, + SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x61, + SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x62, + SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x63, + SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x64, + SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x65, + SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x66, + SQ_PERF_SEL_VALU_DEP_STALL = 0x67, + SQ_PERF_SEL_VALU_STARVE = 0x68, + SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x69, + SQ_PERF_SEL_LDS_BACK2BACK_STALL = 0x6a, + SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x6b, + SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x6c, + SQ_PERF_SEL_VMEM_BACK2BACK_STALL = 0x6d, + SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x6e, + SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x6f, + SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x70, + SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL = 0x71, + SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x72, + SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x73, + SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x74, + SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x75, + SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x76, + SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x77, + SQ_PERF_SEL_SRC_CD_BUSY = 0x78, + SQ_PERF_SEL_PT_POWER_STALL = 0x79, + SQ_PERF_SEL_USER0 = 0x7a, + SQ_PERF_SEL_USER1 = 0x7b, + SQ_PERF_SEL_USER2 = 0x7c, + SQ_PERF_SEL_USER3 = 0x7d, + SQ_PERF_SEL_USER4 = 0x7e, + SQ_PERF_SEL_USER5 = 0x7f, + SQ_PERF_SEL_USER6 = 0x80, + SQ_PERF_SEL_USER7 = 0x81, + SQ_PERF_SEL_USER8 = 0x82, + SQ_PERF_SEL_USER9 = 0x83, + SQ_PERF_SEL_USER10 = 0x84, + SQ_PERF_SEL_USER11 = 0x85, + SQ_PERF_SEL_USER12 = 0x86, + SQ_PERF_SEL_USER13 = 0x87, + SQ_PERF_SEL_USER14 = 0x88, + SQ_PERF_SEL_USER15 = 0x89, + SQ_PERF_SEL_USER_LEVEL0 = 0x8a, + SQ_PERF_SEL_USER_LEVEL1 = 0x8b, + SQ_PERF_SEL_USER_LEVEL2 = 0x8c, + SQ_PERF_SEL_USER_LEVEL3 = 0x8d, + SQ_PERF_SEL_USER_LEVEL4 = 0x8e, + SQ_PERF_SEL_USER_LEVEL5 = 0x8f, + SQ_PERF_SEL_USER_LEVEL6 = 0x90, + SQ_PERF_SEL_USER_LEVEL7 = 0x91, + SQ_PERF_SEL_USER_LEVEL8 = 0x92, + SQ_PERF_SEL_USER_LEVEL9 = 0x93, + SQ_PERF_SEL_USER_LEVEL10 = 0x94, + SQ_PERF_SEL_USER_LEVEL11 = 0x95, + SQ_PERF_SEL_USER_LEVEL12 = 0x96, + SQ_PERF_SEL_USER_LEVEL13 = 0x97, + SQ_PERF_SEL_USER_LEVEL14 = 0x98, + SQ_PERF_SEL_USER_LEVEL15 = 0x99, + SQ_PERF_SEL_POWER_VALU = 0x9a, + SQ_PERF_SEL_POWER_VALU0 = 0x9b, + SQ_PERF_SEL_POWER_VALU1 = 0x9c, + SQ_PERF_SEL_POWER_VALU2 = 0x9d, + SQ_PERF_SEL_POWER_GPR_RD = 0x9e, + SQ_PERF_SEL_POWER_GPR_WR = 0x9f, + SQ_PERF_SEL_POWER_LDS_BUSY = 0xa0, + SQ_PERF_SEL_POWER_ALU_BUSY = 0xa1, + SQ_PERF_SEL_POWER_TEX_BUSY = 0xa2, + SQ_PERF_SEL_ACCUM_PREV_HIRES = 0xa3, + SQ_PERF_SEL_WAVES_RESTORED = 0xa4, + SQ_PERF_SEL_WAVES_SAVED = 0xa5, + SQ_PERF_SEL_DUMMY_LAST = 0xa7, + SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0xa8, + SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0xa9, + SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0xaa, + SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0xab, + SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0xac, + SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0xad, + SQC_PERF_SEL_TC_REQ = 0xae, + SQC_PERF_SEL_TC_INST_REQ = 0xaf, + SQC_PERF_SEL_TC_DATA_READ_REQ = 0xb0, + SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0xb1, + SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0xb2, + SQC_PERF_SEL_TC_STALL = 0xb3, + SQC_PERF_SEL_TC_STARVE = 0xb4, + SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0xb5, + SQC_PERF_SEL_ICACHE_REQ = 0xb6, + SQC_PERF_SEL_ICACHE_HITS = 0xb7, + SQC_PERF_SEL_ICACHE_MISSES = 0xb8, + SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0xb9, + SQC_PERF_SEL_ICACHE_INVAL_INST = 0xba, + SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0xbb, + SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0xbc, + SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0xbd, + SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0xbe, + SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xbf, + SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0xc0, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0xc1, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc2, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xc3, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0xc4, + SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xc5, + SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0xc6, + SQC_PERF_SEL_DCACHE_REQ = 0xc7, + SQC_PERF_SEL_DCACHE_HITS = 0xc8, + SQC_PERF_SEL_DCACHE_MISSES = 0xc9, + SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0xca, + SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0xcb, + SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0xcc, + SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0xcd, + SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0xce, + SQC_PERF_SEL_DCACHE_ATOMIC = 0xcf, + SQC_PERF_SEL_DCACHE_VOLATILE = 0xd0, + SQC_PERF_SEL_DCACHE_INVAL_INST = 0xd1, + SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0xd2, + SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0xd3, + SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0xd4, + SQC_PERF_SEL_DCACHE_WB_INST = 0xd5, + SQC_PERF_SEL_DCACHE_WB_ASYNC = 0xd6, + SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0xd7, + SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0xd8, + SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0xd9, + SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0xda, + SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0xdb, + SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0xdc, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0xdd, + SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0xde, + SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0xdf, + SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE= 0xe0, + SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0xe1, + SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0xe2, + SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0xe3, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xe4, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xe5, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0xe6, + SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xe7, + SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0xe8, + SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0xe9, + SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0xea, + SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0xeb, + SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0xec, + SQC_PERF_SEL_DCACHE_REQ_TIME = 0xed, + SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0xee, + SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0xef, + SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0xf0, + SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0xf1, + SQC_PERF_SEL_SQ_DCACHE_REQS = 0xf2, + SQC_PERF_SEL_DCACHE_FLAT_REQ = 0xf3, + SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0xf4, + SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0xf5, + SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0xf6, + SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0xf7, + SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0xf8, + SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0xf9, + SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0xfa, + SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0xfb, + SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0xfc, + SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0xfd, + SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0xfe, + SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0xff, + SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x100, + SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x101, + SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x102, + SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x103, + SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x104, + SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x105, + SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x106, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x107, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x108, + SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x109, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x10a, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x10b, + SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x10c, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x10d, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x10e, + SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x10f, + SQC_PERF_SEL_DUMMY_LAST = 0x110, + SQ_PERF_SEL_INSTS_SMEM_NORM = 0x111, + SQ_PERF_SEL_ATC_INSTS_VMEM = 0x112, + SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 0x113, + SQ_PERF_SEL_ATC_XNACK_FIRST = 0x114, + SQ_PERF_SEL_ATC_XNACK_ALL = 0x115, + SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 0x116, + SQ_PERF_SEL_ATC_INSTS_SMEM = 0x117, + SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 0x118, + SQ_PERF_SEL_IFETCH_XNACK = 0x119, + SQ_PERF_SEL_TLB_SHOOTDOWN = 0x11a, + SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x11b, + SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x11c, + SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x11d, + SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x11e, + SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x11f, + SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x120, + SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x121, + SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x122, + SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 0x123, + SQ_PERF_SEL_DUMMY_LAST1 = 0x12a, +} SQ_PERF_SEL; +typedef enum SQ_CAC_POWER_SEL { + SQ_CAC_POWER_VALU = 0x0, + SQ_CAC_POWER_VALU0 = 0x1, + SQ_CAC_POWER_VALU1 = 0x2, + SQ_CAC_POWER_VALU2 = 0x3, + SQ_CAC_POWER_GPR_RD = 0x4, + SQ_CAC_POWER_GPR_WR = 0x5, + SQ_CAC_POWER_LDS_BUSY = 0x6, + SQ_CAC_POWER_ALU_BUSY = 0x7, + SQ_CAC_POWER_TEX_BUSY = 0x8, +} SQ_CAC_POWER_SEL; +typedef enum SQ_IND_CMD_CMD { + SQ_IND_CMD_CMD_NULL = 0x0, + SQ_IND_CMD_CMD_SETHALT = 0x1, + SQ_IND_CMD_CMD_SAVECTX = 0x2, + SQ_IND_CMD_CMD_KILL = 0x3, + SQ_IND_CMD_CMD_DEBUG = 0x4, + SQ_IND_CMD_CMD_TRAP = 0x5, + SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x6, +} SQ_IND_CMD_CMD; +typedef enum SQ_IND_CMD_MODE { + SQ_IND_CMD_MODE_SINGLE = 0x0, + SQ_IND_CMD_MODE_BROADCAST = 0x1, + SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2, + SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x3, + SQ_IND_CMD_MODE_BROADCAST_ME = 0x4, +} SQ_IND_CMD_MODE; +typedef enum SQ_EDC_INFO_SOURCE { + SQ_EDC_INFO_SOURCE_INVALID = 0x0, + SQ_EDC_INFO_SOURCE_INST = 0x1, + SQ_EDC_INFO_SOURCE_SGPR = 0x2, + SQ_EDC_INFO_SOURCE_VGPR = 0x3, + SQ_EDC_INFO_SOURCE_LDS = 0x4, + SQ_EDC_INFO_SOURCE_GDS = 0x5, + SQ_EDC_INFO_SOURCE_TA = 0x6, +} SQ_EDC_INFO_SOURCE; +typedef enum SQ_ROUND_MODE { + SQ_ROUND_NEAREST_EVEN = 0x0, + SQ_ROUND_PLUS_INFINITY = 0x1, + SQ_ROUND_MINUS_INFINITY = 0x2, + SQ_ROUND_TO_ZERO = 0x3, +} SQ_ROUND_MODE; +typedef enum SQ_INTERRUPT_WORD_ENCODING { + SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, + SQ_INTERRUPT_WORD_ENCODING_INST = 0x1, + SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2, +} SQ_INTERRUPT_WORD_ENCODING; +typedef enum ENUM_SQ_EXPORT_RAT_INST { + SQ_EXPORT_RAT_INST_NOP = 0x0, + SQ_EXPORT_RAT_INST_STORE_TYPED = 0x1, + SQ_EXPORT_RAT_INST_STORE_RAW = 0x2, + SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x3, + SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x4, + SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x5, + SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x6, + SQ_EXPORT_RAT_INST_ADD = 0x7, + SQ_EXPORT_RAT_INST_SUB = 0x8, + SQ_EXPORT_RAT_INST_RSUB = 0x9, + SQ_EXPORT_RAT_INST_MIN_INT = 0xa, + SQ_EXPORT_RAT_INST_MIN_UINT = 0xb, + SQ_EXPORT_RAT_INST_MAX_INT = 0xc, + SQ_EXPORT_RAT_INST_MAX_UINT = 0xd, + SQ_EXPORT_RAT_INST_AND = 0xe, + SQ_EXPORT_RAT_INST_OR = 0xf, + SQ_EXPORT_RAT_INST_XOR = 0x10, + SQ_EXPORT_RAT_INST_MSKOR = 0x11, + SQ_EXPORT_RAT_INST_INC_UINT = 0x12, + SQ_EXPORT_RAT_INST_DEC_UINT = 0x13, + SQ_EXPORT_RAT_INST_STORE_DWORD = 0x14, + SQ_EXPORT_RAT_INST_STORE_SHORT = 0x15, + SQ_EXPORT_RAT_INST_STORE_BYTE = 0x16, + SQ_EXPORT_RAT_INST_NOP_RTN = 0x20, + SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22, + SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23, + SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24, + SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25, + SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26, + SQ_EXPORT_RAT_INST_ADD_RTN = 0x27, + SQ_EXPORT_RAT_INST_SUB_RTN = 0x28, + SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29, + SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a, + SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b, + SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c, + SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d, + SQ_EXPORT_RAT_INST_AND_RTN = 0x2e, + SQ_EXPORT_RAT_INST_OR_RTN = 0x2f, + SQ_EXPORT_RAT_INST_XOR_RTN = 0x30, + SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31, + SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32, + SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33, +} ENUM_SQ_EXPORT_RAT_INST; +typedef enum SQ_IBUF_ST { + SQ_IBUF_IB_IDLE = 0x0, + SQ_IBUF_IB_INI_WAIT_GNT = 0x1, + SQ_IBUF_IB_INI_WAIT_DRET = 0x2, + SQ_IBUF_IB_LE_4DW = 0x3, + SQ_IBUF_IB_WAIT_DRET = 0x4, + SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x5, + SQ_IBUF_IB_DRET = 0x6, + SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x7, +} SQ_IBUF_ST; +typedef enum SQ_INST_STR_ST { + SQ_INST_STR_IB_WAVE_NORML = 0x0, + SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x1, + SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2, + SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x3, + SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x4, + SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x5, + SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x6, + SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x7, +} SQ_INST_STR_ST; +typedef enum SQ_WAVE_IB_ECC_ST { + SQ_WAVE_IB_ECC_CLEAN = 0x0, + SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x1, + SQ_WAVE_IB_ECC_ERR_HALT = 0x2, + SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x3, +} SQ_WAVE_IB_ECC_ST; +typedef enum SH_MEM_ADDRESS_MODE { + SH_MEM_ADDRESS_MODE_GPUVM64 = 0x0, + SH_MEM_ADDRESS_MODE_GPUVM32 = 0x1, + SH_MEM_ADDRESS_MODE_HSA64 = 0x2, + SH_MEM_ADDRESS_MODE_HSA32 = 0x3, +} SH_MEM_ADDRESS_MODE; +typedef enum SH_MEM_ALIGNMENT_MODE { + SH_MEM_ALIGNMENT_MODE_DWORD = 0x0, + SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x1, + SH_MEM_ALIGNMENT_MODE_STRICT = 0x2, + SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x3, +} SH_MEM_ALIGNMENT_MODE; +typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX { + SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x18, + SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x19, +} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX; +#define SQ_WAVE_TYPE_PS0 0x0 +#define SQIND_GLOBAL_REGS_OFFSET 0x0 +#define SQIND_GLOBAL_REGS_SIZE 0x8 +#define SQIND_LOCAL_REGS_OFFSET 0x8 +#define SQIND_LOCAL_REGS_SIZE 0x8 +#define SQIND_WAVE_HWREGS_OFFSET 0x10 +#define SQIND_WAVE_HWREGS_SIZE 0x1f0 +#define SQIND_WAVE_SGPRS_OFFSET 0x200 +#define SQIND_WAVE_SGPRS_SIZE 0x200 +#define SQ_GFXDEC_BEGIN 0xa000 +#define SQ_GFXDEC_END 0xc000 +#define SQ_GFXDEC_STATE_ID_SHIFT 0xa +#define SQDEC_BEGIN 0x2300 +#define SQDEC_END 0x23ff +#define SQPERFSDEC_BEGIN 0xd9c0 +#define SQPERFSDEC_END 0xda40 +#define SQPERFDDEC_BEGIN 0xd1c0 +#define SQPERFDDEC_END 0xd240 +#define SQGFXUDEC_BEGIN 0xc330 +#define SQGFXUDEC_END 0xc380 +#define SQPWRDEC_BEGIN 0xf08c +#define SQPWRDEC_END 0xf094 +#define SQ_DISPATCHER_GFX_MIN 0x10 +#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x8 +#define SQ_MAX_PGM_SGPRS 0x68 +#define SQ_MAX_PGM_VGPRS 0x100 +#define SQ_THREAD_TRACE_TIME_UNIT 0x4 +#define SQ_EX_MODE_EXCP_VALU_BASE 0x0 +#define SQ_EX_MODE_EXCP_VALU_SIZE 0x7 +#define SQ_EX_MODE_EXCP_INVALID 0x0 +#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x1 +#define SQ_EX_MODE_EXCP_DIV0 0x2 +#define SQ_EX_MODE_EXCP_OVERFLOW 0x3 +#define SQ_EX_MODE_EXCP_UNDERFLOW 0x4 +#define SQ_EX_MODE_EXCP_INEXACT 0x5 +#define SQ_EX_MODE_EXCP_INT_DIV0 0x6 +#define SQ_EX_MODE_EXCP_ADDR_WATCH 0x7 +#define SQ_EX_MODE_EXCP_MEM_VIOL 0x8 +#define INST_ID_PRIV_START 0x80000000 +#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 +#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 +#define INST_ID_HW_TRAP 0xfffffff2 +#define INST_ID_KILL_SEQ 0xfffffff3 +#define INST_ID_SPI_WREXEC 0xfffffff4 +#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe +#define SQ_ENC_SOP1_BITS 0xbe800000 +#define SQ_ENC_SOP1_MASK 0xff800000 +#define SQ_ENC_SOP1_FIELD 0x17d +#define SQ_ENC_SOPC_BITS 0xbf000000 +#define SQ_ENC_SOPC_MASK 0xff800000 +#define SQ_ENC_SOPC_FIELD 0x17e +#define SQ_ENC_SOPP_BITS 0xbf800000 +#define SQ_ENC_SOPP_MASK 0xff800000 +#define SQ_ENC_SOPP_FIELD 0x17f +#define SQ_ENC_SOPK_BITS 0xb0000000 +#define SQ_ENC_SOPK_MASK 0xf0000000 +#define SQ_ENC_SOPK_FIELD 0xb +#define SQ_ENC_SOP2_BITS 0x80000000 +#define SQ_ENC_SOP2_MASK 0xc0000000 +#define SQ_ENC_SOP2_FIELD 0x2 +#define SQ_ENC_SMEM_BITS 0xc0000000 +#define SQ_ENC_SMEM_MASK 0xfc000000 +#define SQ_ENC_SMEM_FIELD 0x30 +#define SQ_ENC_VOP1_BITS 0x7e000000 +#define SQ_ENC_VOP1_MASK 0xfe000000 +#define SQ_ENC_VOP1_FIELD 0x3f +#define SQ_ENC_VOPC_BITS 0x7c000000 +#define SQ_ENC_VOPC_MASK 0xfe000000 +#define SQ_ENC_VOPC_FIELD 0x3e +#define SQ_ENC_VOP2_BITS 0x0 +#define SQ_ENC_VOP2_MASK 0x80000000 +#define SQ_ENC_VOP2_FIELD 0x0 +#define SQ_ENC_VINTRP_BITS 0xd4000000 +#define SQ_ENC_VINTRP_MASK 0xfc000000 +#define SQ_ENC_VINTRP_FIELD 0x35 +#define SQ_ENC_VOP3_BITS 0xd0000000 +#define SQ_ENC_VOP3_MASK 0xfc000000 +#define SQ_ENC_VOP3_FIELD 0x34 +#define SQ_ENC_DS_BITS 0xd8000000 +#define SQ_ENC_DS_MASK 0xfc000000 +#define SQ_ENC_DS_FIELD 0x36 +#define SQ_ENC_MUBUF_BITS 0xe0000000 +#define SQ_ENC_MUBUF_MASK 0xfc000000 +#define SQ_ENC_MUBUF_FIELD 0x38 +#define SQ_ENC_MTBUF_BITS 0xe8000000 +#define SQ_ENC_MTBUF_MASK 0xfc000000 +#define SQ_ENC_MTBUF_FIELD 0x3a +#define SQ_ENC_MIMG_BITS 0xf0000000 +#define SQ_ENC_MIMG_MASK 0xfc000000 +#define SQ_ENC_MIMG_FIELD 0x3c +#define SQ_ENC_EXP_BITS 0xc4000000 +#define SQ_ENC_EXP_MASK 0xfc000000 +#define SQ_ENC_EXP_FIELD 0x31 +#define SQ_ENC_FLAT_BITS 0xdc000000 +#define SQ_ENC_FLAT_MASK 0xfc000000 +#define SQ_ENC_FLAT_FIELD 0x37 +#define SQ_V_OP3_INTRP_OFFSET 0x274 +#define SQ_WAITCNT_VM_SHIFT 0x0 +#define SQ_SENDMSG_STREAMID_SIZE 0x2 +#define SQ_V_OPC_COUNT 0x100 +#define SQ_V_OP3_INTRP_COUNT 0xc +#define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x100 +#define SQ_HWREG_OFFSET_SIZE 0x5 +#define SQ_HWREG_OFFSET_SHIFT 0x6 +#define SQ_V_OP3_3IN_OFFSET 0x1c0 +#define SQ_NUM_ATTR 0x21 +#define SQ_NUM_VGPR 0x100 +#define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x4 +#define SQ_SENDMSG_MSG_SIZE 0x4 +#define SQ_NUM_TTMP 0xc +#define SQ_HWREG_ID_SIZE 0x6 +#define SQ_SENDMSG_GSOP_SIZE 0x2 +#define SQ_NUM_SGPR 0x66 +#define SQ_EXP_NUM_MRT 0x8 +#define SQ_SENDMSG_SYSTEM_SIZE 0x3 +#define SQ_WAITCNT_LGKM_SHIFT 0x8 +#define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x40 +#define SQ_V_OP3_3IN_COUNT 0xb0 +#define SQ_V_INTRP_COUNT 0x4 +#define SQ_WAITCNT_EXP_SIZE 0x3 +#define SQ_SENDMSG_SYSTEM_SHIFT 0x4 +#define SQ_EXP_NUM_GDS 0x5 +#define SQ_HWREG_SIZE_SHIFT 0xb +#define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x0 +#define SQ_V_OP3_2IN_COUNT 0x80 +#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x270 +#define SQ_SENDMSG_MSG_SHIFT 0x0 +#define SQ_WAITCNT_EXP_SHIFT 0x4 +#define SQ_WAITCNT_VM_SIZE 0x4 +#define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x140 +#define SQ_SENDMSG_GSOP_SHIFT 0x4 +#define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x80 +#define SQ_SRC_VGPR_BIT 0x100 +#define SQ_V_OP2_COUNT 0x40 +#define SQ_EXP_NUM_PARAM 0x20 +#define SQ_V_OP1_COUNT 0x80 +#define SQ_SENDMSG_STREAMID_SHIFT 0x8 +#define SQ_V_OP3_2IN_OFFSET 0x280 +#define SQ_WAITCNT_LGKM_SIZE 0x4 +#define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x100 +#define SQ_EXP_NUM_POS 0x4 +#define SQ_HWREG_SIZE_SIZE 0x5 +#define SQ_HWREG_ID_SHIFT 0x0 +#define SQ_S_MOV_B32 0x0 +#define SQ_S_MOV_B64 0x1 +#define SQ_S_CMOV_B32 0x2 +#define SQ_S_CMOV_B64 0x3 +#define SQ_S_NOT_B32 0x4 +#define SQ_S_NOT_B64 0x5 +#define SQ_S_WQM_B32 0x6 +#define SQ_S_WQM_B64 0x7 +#define SQ_S_BREV_B32 0x8 +#define SQ_S_BREV_B64 0x9 +#define SQ_S_BCNT0_I32_B32 0xa +#define SQ_S_BCNT0_I32_B64 0xb +#define SQ_S_BCNT1_I32_B32 0xc +#define SQ_S_BCNT1_I32_B64 0xd +#define SQ_S_FF0_I32_B32 0xe +#define SQ_S_FF0_I32_B64 0xf +#define SQ_S_FF1_I32_B32 0x10 +#define SQ_S_FF1_I32_B64 0x11 +#define SQ_S_FLBIT_I32_B32 0x12 +#define SQ_S_FLBIT_I32_B64 0x13 +#define SQ_S_FLBIT_I32 0x14 +#define SQ_S_FLBIT_I32_I64 0x15 +#define SQ_S_SEXT_I32_I8 0x16 +#define SQ_S_SEXT_I32_I16 0x17 +#define SQ_S_BITSET0_B32 0x18 +#define SQ_S_BITSET0_B64 0x19 +#define SQ_S_BITSET1_B32 0x1a +#define SQ_S_BITSET1_B64 0x1b +#define SQ_S_GETPC_B64 0x1c +#define SQ_S_SETPC_B64 0x1d +#define SQ_S_SWAPPC_B64 0x1e +#define SQ_S_RFE_B64 0x1f +#define SQ_S_AND_SAVEEXEC_B64 0x20 +#define SQ_S_OR_SAVEEXEC_B64 0x21 +#define SQ_S_XOR_SAVEEXEC_B64 0x22 +#define SQ_S_ANDN2_SAVEEXEC_B64 0x23 +#define SQ_S_ORN2_SAVEEXEC_B64 0x24 +#define SQ_S_NAND_SAVEEXEC_B64 0x25 +#define SQ_S_NOR_SAVEEXEC_B64 0x26 +#define SQ_S_XNOR_SAVEEXEC_B64 0x27 +#define SQ_S_QUADMASK_B32 0x28 +#define SQ_S_QUADMASK_B64 0x29 +#define SQ_S_MOVRELS_B32 0x2a +#define SQ_S_MOVRELS_B64 0x2b +#define SQ_S_MOVRELD_B32 0x2c +#define SQ_S_MOVRELD_B64 0x2d +#define SQ_S_CBRANCH_JOIN 0x2e +#define SQ_S_MOV_REGRD_B32 0x2f +#define SQ_S_ABS_I32 0x30 +#define SQ_S_MOV_FED_B32 0x31 +#define SQ_S_SET_GPR_IDX_IDX 0x32 +#define SQ_ATTR0 0x0 +#define SQ_S_MOVK_I32 0x0 +#define SQ_S_CMOVK_I32 0x1 +#define SQ_S_CMPK_EQ_I32 0x2 +#define SQ_S_CMPK_LG_I32 0x3 +#define SQ_S_CMPK_GT_I32 0x4 +#define SQ_S_CMPK_GE_I32 0x5 +#define SQ_S_CMPK_LT_I32 0x6 +#define SQ_S_CMPK_LE_I32 0x7 +#define SQ_S_CMPK_EQ_U32 0x8 +#define SQ_S_CMPK_LG_U32 0x9 +#define SQ_S_CMPK_GT_U32 0xa +#define SQ_S_CMPK_GE_U32 0xb +#define SQ_S_CMPK_LT_U32 0xc +#define SQ_S_CMPK_LE_U32 0xd +#define SQ_S_ADDK_I32 0xe +#define SQ_S_MULK_I32 0xf +#define SQ_S_CBRANCH_I_FORK 0x10 +#define SQ_S_GETREG_B32 0x11 +#define SQ_S_SETREG_B32 0x12 +#define SQ_S_GETREG_REGRD_B32 0x13 +#define SQ_S_SETREG_IMM32_B32 0x14 +#define SQ_TBA_LO 0x6c +#define SQ_TBA_HI 0x6d +#define SQ_TMA_LO 0x6e +#define SQ_TMA_HI 0x6f +#define SQ_TTMP0 0x70 +#define SQ_TTMP1 0x71 +#define SQ_TTMP2 0x72 +#define SQ_TTMP3 0x73 +#define SQ_TTMP4 0x74 +#define SQ_TTMP5 0x75 +#define SQ_TTMP6 0x76 +#define SQ_TTMP7 0x77 +#define SQ_TTMP8 0x78 +#define SQ_TTMP9 0x79 +#define SQ_TTMP10 0x7a +#define SQ_TTMP11 0x7b +#define SQ_VGPR0 0x0 +#define SQ_EXP 0x0 +#define SQ_EXP_MRT0 0x0 +#define SQ_EXP_MRTZ 0x8 +#define SQ_EXP_NULL 0x9 +#define SQ_EXP_POS0 0xc +#define SQ_EXP_PARAM0 0x20 +#define SQ_CNT1 0x0 +#define SQ_CNT2 0x1 +#define SQ_CNT3 0x2 +#define SQ_CNT4 0x3 +#define SQ_S_LOAD_DWORD 0x0 +#define SQ_S_LOAD_DWORDX2 0x1 +#define SQ_S_LOAD_DWORDX4 0x2 +#define SQ_S_LOAD_DWORDX8 0x3 +#define SQ_S_LOAD_DWORDX16 0x4 +#define SQ_S_BUFFER_LOAD_DWORD 0x8 +#define SQ_S_BUFFER_LOAD_DWORDX2 0x9 +#define SQ_S_BUFFER_LOAD_DWORDX4 0xa +#define SQ_S_BUFFER_LOAD_DWORDX8 0xb +#define SQ_S_BUFFER_LOAD_DWORDX16 0xc +#define SQ_S_STORE_DWORD 0x10 +#define SQ_S_STORE_DWORDX2 0x11 +#define SQ_S_STORE_DWORDX4 0x12 +#define SQ_S_BUFFER_STORE_DWORD 0x18 +#define SQ_S_BUFFER_STORE_DWORDX2 0x19 +#define SQ_S_BUFFER_STORE_DWORDX4 0x1a +#define SQ_S_DCACHE_INV 0x20 +#define SQ_S_DCACHE_WB 0x21 +#define SQ_S_DCACHE_INV_VOL 0x22 +#define SQ_S_DCACHE_WB_VOL 0x23 +#define SQ_S_MEMTIME 0x24 +#define SQ_S_MEMREALTIME 0x25 +#define SQ_S_ATC_PROBE 0x26 +#define SQ_S_ATC_PROBE_BUFFER 0x27 +#define SQ_S_BUFFER_ATOMIC_SWAP 0x40 +#define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x41 +#define SQ_S_BUFFER_ATOMIC_ADD 0x42 +#define SQ_S_BUFFER_ATOMIC_SUB 0x43 +#define SQ_S_BUFFER_ATOMIC_SMIN 0x44 +#define SQ_S_BUFFER_ATOMIC_UMIN 0x45 +#define SQ_S_BUFFER_ATOMIC_SMAX 0x46 +#define SQ_S_BUFFER_ATOMIC_UMAX 0x47 +#define SQ_S_BUFFER_ATOMIC_AND 0x48 +#define SQ_S_BUFFER_ATOMIC_OR 0x49 +#define SQ_S_BUFFER_ATOMIC_XOR 0x4a +#define SQ_S_BUFFER_ATOMIC_INC 0x4b +#define SQ_S_BUFFER_ATOMIC_DEC 0x4c +#define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x60 +#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x61 +#define SQ_S_BUFFER_ATOMIC_ADD_X2 0x62 +#define SQ_S_BUFFER_ATOMIC_SUB_X2 0x63 +#define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x64 +#define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x65 +#define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x66 +#define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x67 +#define SQ_S_BUFFER_ATOMIC_AND_X2 0x68 +#define SQ_S_BUFFER_ATOMIC_OR_X2 0x69 +#define SQ_S_BUFFER_ATOMIC_XOR_X2 0x6a +#define SQ_S_BUFFER_ATOMIC_INC_X2 0x6b +#define SQ_S_BUFFER_ATOMIC_DEC_X2 0x6c +#define SQ_F 0x0 +#define SQ_LT 0x1 +#define SQ_EQ 0x2 +#define SQ_LE 0x3 +#define SQ_GT 0x4 +#define SQ_LG 0x5 +#define SQ_GE 0x6 +#define SQ_O 0x7 +#define SQ_U 0x8 +#define SQ_NGE 0x9 +#define SQ_NLG 0xa +#define SQ_NGT 0xb +#define SQ_NLE 0xc +#define SQ_NEQ 0xd +#define SQ_NLT 0xe +#define SQ_TRU 0xf +#define SQ_V_CMP_CLASS_F32 0x10 +#define SQ_V_CMPX_CLASS_F32 0x11 +#define SQ_V_CMP_CLASS_F64 0x12 +#define SQ_V_CMPX_CLASS_F64 0x13 +#define SQ_V_CMP_CLASS_F16 0x14 +#define SQ_V_CMPX_CLASS_F16 0x15 +#define SQ_V_CMP_F_F16 0x20 +#define SQ_V_CMP_LT_F16 0x21 +#define SQ_V_CMP_EQ_F16 0x22 +#define SQ_V_CMP_LE_F16 0x23 +#define SQ_V_CMP_GT_F16 0x24 +#define SQ_V_CMP_LG_F16 0x25 +#define SQ_V_CMP_GE_F16 0x26 +#define SQ_V_CMP_O_F16 0x27 +#define SQ_V_CMP_U_F16 0x28 +#define SQ_V_CMP_NGE_F16 0x29 +#define SQ_V_CMP_NLG_F16 0x2a +#define SQ_V_CMP_NGT_F16 0x2b +#define SQ_V_CMP_NLE_F16 0x2c +#define SQ_V_CMP_NEQ_F16 0x2d +#define SQ_V_CMP_NLT_F16 0x2e +#define SQ_V_CMP_TRU_F16 0x2f +#define SQ_V_CMPX_F_F16 0x30 +#define SQ_V_CMPX_LT_F16 0x31 +#define SQ_V_CMPX_EQ_F16 0x32 +#define SQ_V_CMPX_LE_F16 0x33 +#define SQ_V_CMPX_GT_F16 0x34 +#define SQ_V_CMPX_LG_F16 0x35 +#define SQ_V_CMPX_GE_F16 0x36 +#define SQ_V_CMPX_O_F16 0x37 +#define SQ_V_CMPX_U_F16 0x38 +#define SQ_V_CMPX_NGE_F16 0x39 +#define SQ_V_CMPX_NLG_F16 0x3a +#define SQ_V_CMPX_NGT_F16 0x3b +#define SQ_V_CMPX_NLE_F16 0x3c +#define SQ_V_CMPX_NEQ_F16 0x3d +#define SQ_V_CMPX_NLT_F16 0x3e +#define SQ_V_CMPX_TRU_F16 0x3f +#define SQ_V_CMP_F_F32 0x40 +#define SQ_V_CMP_LT_F32 0x41 +#define SQ_V_CMP_EQ_F32 0x42 +#define SQ_V_CMP_LE_F32 0x43 +#define SQ_V_CMP_GT_F32 0x44 +#define SQ_V_CMP_LG_F32 0x45 +#define SQ_V_CMP_GE_F32 0x46 +#define SQ_V_CMP_O_F32 0x47 +#define SQ_V_CMP_U_F32 0x48 +#define SQ_V_CMP_NGE_F32 0x49 +#define SQ_V_CMP_NLG_F32 0x4a +#define SQ_V_CMP_NGT_F32 0x4b +#define SQ_V_CMP_NLE_F32 0x4c +#define SQ_V_CMP_NEQ_F32 0x4d +#define SQ_V_CMP_NLT_F32 0x4e +#define SQ_V_CMP_TRU_F32 0x4f +#define SQ_V_CMPX_F_F32 0x50 +#define SQ_V_CMPX_LT_F32 0x51 +#define SQ_V_CMPX_EQ_F32 0x52 +#define SQ_V_CMPX_LE_F32 0x53 +#define SQ_V_CMPX_GT_F32 0x54 +#define SQ_V_CMPX_LG_F32 0x55 +#define SQ_V_CMPX_GE_F32 0x56 +#define SQ_V_CMPX_O_F32 0x57 +#define SQ_V_CMPX_U_F32 0x58 +#define SQ_V_CMPX_NGE_F32 0x59 +#define SQ_V_CMPX_NLG_F32 0x5a +#define SQ_V_CMPX_NGT_F32 0x5b +#define SQ_V_CMPX_NLE_F32 0x5c +#define SQ_V_CMPX_NEQ_F32 0x5d +#define SQ_V_CMPX_NLT_F32 0x5e +#define SQ_V_CMPX_TRU_F32 0x5f +#define SQ_V_CMP_F_F64 0x60 +#define SQ_V_CMP_LT_F64 0x61 +#define SQ_V_CMP_EQ_F64 0x62 +#define SQ_V_CMP_LE_F64 0x63 +#define SQ_V_CMP_GT_F64 0x64 +#define SQ_V_CMP_LG_F64 0x65 +#define SQ_V_CMP_GE_F64 0x66 +#define SQ_V_CMP_O_F64 0x67 +#define SQ_V_CMP_U_F64 0x68 +#define SQ_V_CMP_NGE_F64 0x69 +#define SQ_V_CMP_NLG_F64 0x6a +#define SQ_V_CMP_NGT_F64 0x6b +#define SQ_V_CMP_NLE_F64 0x6c +#define SQ_V_CMP_NEQ_F64 0x6d +#define SQ_V_CMP_NLT_F64 0x6e +#define SQ_V_CMP_TRU_F64 0x6f +#define SQ_V_CMPX_F_F64 0x70 +#define SQ_V_CMPX_LT_F64 0x71 +#define SQ_V_CMPX_EQ_F64 0x72 +#define SQ_V_CMPX_LE_F64 0x73 +#define SQ_V_CMPX_GT_F64 0x74 +#define SQ_V_CMPX_LG_F64 0x75 +#define SQ_V_CMPX_GE_F64 0x76 +#define SQ_V_CMPX_O_F64 0x77 +#define SQ_V_CMPX_U_F64 0x78 +#define SQ_V_CMPX_NGE_F64 0x79 +#define SQ_V_CMPX_NLG_F64 0x7a +#define SQ_V_CMPX_NGT_F64 0x7b +#define SQ_V_CMPX_NLE_F64 0x7c +#define SQ_V_CMPX_NEQ_F64 0x7d +#define SQ_V_CMPX_NLT_F64 0x7e +#define SQ_V_CMPX_TRU_F64 0x7f +#define SQ_V_CMP_F_I16 0xa0 +#define SQ_V_CMP_LT_I16 0xa1 +#define SQ_V_CMP_EQ_I16 0xa2 +#define SQ_V_CMP_LE_I16 0xa3 +#define SQ_V_CMP_GT_I16 0xa4 +#define SQ_V_CMP_NE_I16 0xa5 +#define SQ_V_CMP_GE_I16 0xa6 +#define SQ_V_CMP_T_I16 0xa7 +#define SQ_V_CMP_F_U16 0xa8 +#define SQ_V_CMP_LT_U16 0xa9 +#define SQ_V_CMP_EQ_U16 0xaa +#define SQ_V_CMP_LE_U16 0xab +#define SQ_V_CMP_GT_U16 0xac +#define SQ_V_CMP_NE_U16 0xad +#define SQ_V_CMP_GE_U16 0xae +#define SQ_V_CMP_T_U16 0xaf +#define SQ_V_CMPX_F_I16 0xb0 +#define SQ_V_CMPX_LT_I16 0xb1 +#define SQ_V_CMPX_EQ_I16 0xb2 +#define SQ_V_CMPX_LE_I16 0xb3 +#define SQ_V_CMPX_GT_I16 0xb4 +#define SQ_V_CMPX_NE_I16 0xb5 +#define SQ_V_CMPX_GE_I16 0xb6 +#define SQ_V_CMPX_T_I16 0xb7 +#define SQ_V_CMPX_F_U16 0xb8 +#define SQ_V_CMPX_LT_U16 0xb9 +#define SQ_V_CMPX_EQ_U16 0xba +#define SQ_V_CMPX_LE_U16 0xbb +#define SQ_V_CMPX_GT_U16 0xbc +#define SQ_V_CMPX_NE_U16 0xbd +#define SQ_V_CMPX_GE_U16 0xbe +#define SQ_V_CMPX_T_U16 0xbf +#define SQ_V_CMP_F_I32 0xc0 +#define SQ_V_CMP_LT_I32 0xc1 +#define SQ_V_CMP_EQ_I32 0xc2 +#define SQ_V_CMP_LE_I32 0xc3 +#define SQ_V_CMP_GT_I32 0xc4 +#define SQ_V_CMP_NE_I32 0xc5 +#define SQ_V_CMP_GE_I32 0xc6 +#define SQ_V_CMP_T_I32 0xc7 +#define SQ_V_CMP_F_U32 0xc8 +#define SQ_V_CMP_LT_U32 0xc9 +#define SQ_V_CMP_EQ_U32 0xca +#define SQ_V_CMP_LE_U32 0xcb +#define SQ_V_CMP_GT_U32 0xcc +#define SQ_V_CMP_NE_U32 0xcd +#define SQ_V_CMP_GE_U32 0xce +#define SQ_V_CMP_T_U32 0xcf +#define SQ_V_CMPX_F_I32 0xd0 +#define SQ_V_CMPX_LT_I32 0xd1 +#define SQ_V_CMPX_EQ_I32 0xd2 +#define SQ_V_CMPX_LE_I32 0xd3 +#define SQ_V_CMPX_GT_I32 0xd4 +#define SQ_V_CMPX_NE_I32 0xd5 +#define SQ_V_CMPX_GE_I32 0xd6 +#define SQ_V_CMPX_T_I32 0xd7 +#define SQ_V_CMPX_F_U32 0xd8 +#define SQ_V_CMPX_LT_U32 0xd9 +#define SQ_V_CMPX_EQ_U32 0xda +#define SQ_V_CMPX_LE_U32 0xdb +#define SQ_V_CMPX_GT_U32 0xdc +#define SQ_V_CMPX_NE_U32 0xdd +#define SQ_V_CMPX_GE_U32 0xde +#define SQ_V_CMPX_T_U32 0xdf +#define SQ_V_CMP_F_I64 0xe0 +#define SQ_V_CMP_LT_I64 0xe1 +#define SQ_V_CMP_EQ_I64 0xe2 +#define SQ_V_CMP_LE_I64 0xe3 +#define SQ_V_CMP_GT_I64 0xe4 +#define SQ_V_CMP_NE_I64 0xe5 +#define SQ_V_CMP_GE_I64 0xe6 +#define SQ_V_CMP_T_I64 0xe7 +#define SQ_V_CMP_F_U64 0xe8 +#define SQ_V_CMP_LT_U64 0xe9 +#define SQ_V_CMP_EQ_U64 0xea +#define SQ_V_CMP_LE_U64 0xeb +#define SQ_V_CMP_GT_U64 0xec +#define SQ_V_CMP_NE_U64 0xed +#define SQ_V_CMP_GE_U64 0xee +#define SQ_V_CMP_T_U64 0xef +#define SQ_V_CMPX_F_I64 0xf0 +#define SQ_V_CMPX_LT_I64 0xf1 +#define SQ_V_CMPX_EQ_I64 0xf2 +#define SQ_V_CMPX_LE_I64 0xf3 +#define SQ_V_CMPX_GT_I64 0xf4 +#define SQ_V_CMPX_NE_I64 0xf5 +#define SQ_V_CMPX_GE_I64 0xf6 +#define SQ_V_CMPX_T_I64 0xf7 +#define SQ_V_CMPX_F_U64 0xf8 +#define SQ_V_CMPX_LT_U64 0xf9 +#define SQ_V_CMPX_EQ_U64 0xfa +#define SQ_V_CMPX_LE_U64 0xfb +#define SQ_V_CMPX_GT_U64 0xfc +#define SQ_V_CMPX_NE_U64 0xfd +#define SQ_V_CMPX_GE_U64 0xfe +#define SQ_V_CMPX_T_U64 0xff +#define SQ_L1 0x1 +#define SQ_L2 0x2 +#define SQ_L3 0x3 +#define SQ_L4 0x4 +#define SQ_L5 0x5 +#define SQ_L6 0x6 +#define SQ_L7 0x7 +#define SQ_L8 0x8 +#define SQ_L9 0x9 +#define SQ_L10 0xa +#define SQ_L11 0xb +#define SQ_L12 0xc +#define SQ_L13 0xd +#define SQ_L14 0xe +#define SQ_L15 0xf +#define SQ_SGPR0 0x0 +#define SQ_SDWA_UNUSED_PAD 0x0 +#define SQ_SDWA_UNUSED_SEXT 0x1 +#define SQ_SDWA_UNUSED_PRESERVE 0x2 +#define SQ_F 0x0 +#define SQ_LT 0x1 +#define SQ_EQ 0x2 +#define SQ_LE 0x3 +#define SQ_GT 0x4 +#define SQ_NE 0x5 +#define SQ_GE 0x6 +#define SQ_T 0x7 +#define SQ_SRC_64_INT 0xc0 +#define SQ_SRC_M_1_INT 0xc1 +#define SQ_SRC_M_2_INT 0xc2 +#define SQ_SRC_M_3_INT 0xc3 +#define SQ_SRC_M_4_INT 0xc4 +#define SQ_SRC_M_5_INT 0xc5 +#define SQ_SRC_M_6_INT 0xc6 +#define SQ_SRC_M_7_INT 0xc7 +#define SQ_SRC_M_8_INT 0xc8 +#define SQ_SRC_M_9_INT 0xc9 +#define SQ_SRC_M_10_INT 0xca +#define SQ_SRC_M_11_INT 0xcb +#define SQ_SRC_M_12_INT 0xcc +#define SQ_SRC_M_13_INT 0xcd +#define SQ_SRC_M_14_INT 0xce +#define SQ_SRC_M_15_INT 0xcf +#define SQ_SRC_M_16_INT 0xd0 +#define SQ_SRC_0_5 0xf0 +#define SQ_SRC_M_0_5 0xf1 +#define SQ_SRC_1 0xf2 +#define SQ_SRC_M_1 0xf3 +#define SQ_SRC_2 0xf4 +#define SQ_SRC_M_2 0xf5 +#define SQ_SRC_4 0xf6 +#define SQ_SRC_M_4 0xf7 +#define SQ_SRC_INV_2PI 0xf8 +#define SQ_SRC_0 0x80 +#define SQ_SRC_1_INT 0x81 +#define SQ_SRC_2_INT 0x82 +#define SQ_SRC_3_INT 0x83 +#define SQ_SRC_4_INT 0x84 +#define SQ_SRC_5_INT 0x85 +#define SQ_SRC_6_INT 0x86 +#define SQ_SRC_7_INT 0x87 +#define SQ_SRC_8_INT 0x88 +#define SQ_SRC_9_INT 0x89 +#define SQ_SRC_10_INT 0x8a +#define SQ_SRC_11_INT 0x8b +#define SQ_SRC_12_INT 0x8c +#define SQ_SRC_13_INT 0x8d +#define SQ_SRC_14_INT 0x8e +#define SQ_SRC_15_INT 0x8f +#define SQ_SRC_16_INT 0x90 +#define SQ_SRC_17_INT 0x91 +#define SQ_SRC_18_INT 0x92 +#define SQ_SRC_19_INT 0x93 +#define SQ_SRC_20_INT 0x94 +#define SQ_SRC_21_INT 0x95 +#define SQ_SRC_22_INT 0x96 +#define SQ_SRC_23_INT 0x97 +#define SQ_SRC_24_INT 0x98 +#define SQ_SRC_25_INT 0x99 +#define SQ_SRC_26_INT 0x9a +#define SQ_SRC_27_INT 0x9b +#define SQ_SRC_28_INT 0x9c +#define SQ_SRC_29_INT 0x9d +#define SQ_SRC_30_INT 0x9e +#define SQ_SRC_31_INT 0x9f +#define SQ_SRC_32_INT 0xa0 +#define SQ_SRC_33_INT 0xa1 +#define SQ_SRC_34_INT 0xa2 +#define SQ_SRC_35_INT 0xa3 +#define SQ_SRC_36_INT 0xa4 +#define SQ_SRC_37_INT 0xa5 +#define SQ_SRC_38_INT 0xa6 +#define SQ_SRC_39_INT 0xa7 +#define SQ_SRC_40_INT 0xa8 +#define SQ_SRC_41_INT 0xa9 +#define SQ_SRC_42_INT 0xaa +#define SQ_SRC_43_INT 0xab +#define SQ_SRC_44_INT 0xac +#define SQ_SRC_45_INT 0xad +#define SQ_SRC_46_INT 0xae +#define SQ_SRC_47_INT 0xaf +#define SQ_SRC_48_INT 0xb0 +#define SQ_SRC_49_INT 0xb1 +#define SQ_SRC_50_INT 0xb2 +#define SQ_SRC_51_INT 0xb3 +#define SQ_SRC_52_INT 0xb4 +#define SQ_SRC_53_INT 0xb5 +#define SQ_SRC_54_INT 0xb6 +#define SQ_SRC_55_INT 0xb7 +#define SQ_SRC_56_INT 0xb8 +#define SQ_SRC_57_INT 0xb9 +#define SQ_SRC_58_INT 0xba +#define SQ_SRC_59_INT 0xbb +#define SQ_SRC_60_INT 0xbc +#define SQ_SRC_61_INT 0xbd +#define SQ_SRC_62_INT 0xbe +#define SQ_SRC_63_INT 0xbf +#define SQ_DS_ADD_U32 0x0 +#define SQ_DS_SUB_U32 0x1 +#define SQ_DS_RSUB_U32 0x2 +#define SQ_DS_INC_U32 0x3 +#define SQ_DS_DEC_U32 0x4 +#define SQ_DS_MIN_I32 0x5 +#define SQ_DS_MAX_I32 0x6 +#define SQ_DS_MIN_U32 0x7 +#define SQ_DS_MAX_U32 0x8 +#define SQ_DS_AND_B32 0x9 +#define SQ_DS_OR_B32 0xa +#define SQ_DS_XOR_B32 0xb +#define SQ_DS_MSKOR_B32 0xc +#define SQ_DS_WRITE_B32 0xd +#define SQ_DS_WRITE2_B32 0xe +#define SQ_DS_WRITE2ST64_B32 0xf +#define SQ_DS_CMPST_B32 0x10 +#define SQ_DS_CMPST_F32 0x11 +#define SQ_DS_MIN_F32 0x12 +#define SQ_DS_MAX_F32 0x13 +#define SQ_DS_NOP 0x14 +#define SQ_DS_ADD_F32 0x15 +#define SQ_DS_WRITE_B8 0x1e +#define SQ_DS_WRITE_B16 0x1f +#define SQ_DS_ADD_RTN_U32 0x20 +#define SQ_DS_SUB_RTN_U32 0x21 +#define SQ_DS_RSUB_RTN_U32 0x22 +#define SQ_DS_INC_RTN_U32 0x23 +#define SQ_DS_DEC_RTN_U32 0x24 +#define SQ_DS_MIN_RTN_I32 0x25 +#define SQ_DS_MAX_RTN_I32 0x26 +#define SQ_DS_MIN_RTN_U32 0x27 +#define SQ_DS_MAX_RTN_U32 0x28 +#define SQ_DS_AND_RTN_B32 0x29 +#define SQ_DS_OR_RTN_B32 0x2a +#define SQ_DS_XOR_RTN_B32 0x2b +#define SQ_DS_MSKOR_RTN_B32 0x2c +#define SQ_DS_WRXCHG_RTN_B32 0x2d +#define SQ_DS_WRXCHG2_RTN_B32 0x2e +#define SQ_DS_WRXCHG2ST64_RTN_B32 0x2f +#define SQ_DS_CMPST_RTN_B32 0x30 +#define SQ_DS_CMPST_RTN_F32 0x31 +#define SQ_DS_MIN_RTN_F32 0x32 +#define SQ_DS_MAX_RTN_F32 0x33 +#define SQ_DS_WRAP_RTN_B32 0x34 +#define SQ_DS_ADD_RTN_F32 0x35 +#define SQ_DS_READ_B32 0x36 +#define SQ_DS_READ2_B32 0x37 +#define SQ_DS_READ2ST64_B32 0x38 +#define SQ_DS_READ_I8 0x39 +#define SQ_DS_READ_U8 0x3a +#define SQ_DS_READ_I16 0x3b +#define SQ_DS_READ_U16 0x3c +#define SQ_DS_SWIZZLE_B32 0x3d +#define SQ_DS_PERMUTE_B32 0x3e +#define SQ_DS_BPERMUTE_B32 0x3f +#define SQ_DS_ADD_U64 0x40 +#define SQ_DS_SUB_U64 0x41 +#define SQ_DS_RSUB_U64 0x42 +#define SQ_DS_INC_U64 0x43 +#define SQ_DS_DEC_U64 0x44 +#define SQ_DS_MIN_I64 0x45 +#define SQ_DS_MAX_I64 0x46 +#define SQ_DS_MIN_U64 0x47 +#define SQ_DS_MAX_U64 0x48 +#define SQ_DS_AND_B64 0x49 +#define SQ_DS_OR_B64 0x4a +#define SQ_DS_XOR_B64 0x4b +#define SQ_DS_MSKOR_B64 0x4c +#define SQ_DS_WRITE_B64 0x4d +#define SQ_DS_WRITE2_B64 0x4e +#define SQ_DS_WRITE2ST64_B64 0x4f +#define SQ_DS_CMPST_B64 0x50 +#define SQ_DS_CMPST_F64 0x51 +#define SQ_DS_MIN_F64 0x52 +#define SQ_DS_MAX_F64 0x53 +#define SQ_DS_ADD_RTN_U64 0x60 +#define SQ_DS_SUB_RTN_U64 0x61 +#define SQ_DS_RSUB_RTN_U64 0x62 +#define SQ_DS_INC_RTN_U64 0x63 +#define SQ_DS_DEC_RTN_U64 0x64 +#define SQ_DS_MIN_RTN_I64 0x65 +#define SQ_DS_MAX_RTN_I64 0x66 +#define SQ_DS_MIN_RTN_U64 0x67 +#define SQ_DS_MAX_RTN_U64 0x68 +#define SQ_DS_AND_RTN_B64 0x69 +#define SQ_DS_OR_RTN_B64 0x6a +#define SQ_DS_XOR_RTN_B64 0x6b +#define SQ_DS_MSKOR_RTN_B64 0x6c +#define SQ_DS_WRXCHG_RTN_B64 0x6d +#define SQ_DS_WRXCHG2_RTN_B64 0x6e +#define SQ_DS_WRXCHG2ST64_RTN_B64 0x6f +#define SQ_DS_CMPST_RTN_B64 0x70 +#define SQ_DS_CMPST_RTN_F64 0x71 +#define SQ_DS_MIN_RTN_F64 0x72 +#define SQ_DS_MAX_RTN_F64 0x73 +#define SQ_DS_READ_B64 0x76 +#define SQ_DS_READ2_B64 0x77 +#define SQ_DS_READ2ST64_B64 0x78 +#define SQ_DS_CONDXCHG32_RTN_B64 0x7e +#define SQ_DS_ADD_SRC2_U32 0x80 +#define SQ_DS_SUB_SRC2_U32 0x81 +#define SQ_DS_RSUB_SRC2_U32 0x82 +#define SQ_DS_INC_SRC2_U32 0x83 +#define SQ_DS_DEC_SRC2_U32 0x84 +#define SQ_DS_MIN_SRC2_I32 0x85 +#define SQ_DS_MAX_SRC2_I32 0x86 +#define SQ_DS_MIN_SRC2_U32 0x87 +#define SQ_DS_MAX_SRC2_U32 0x88 +#define SQ_DS_AND_SRC2_B32 0x89 +#define SQ_DS_OR_SRC2_B32 0x8a +#define SQ_DS_XOR_SRC2_B32 0x8b +#define SQ_DS_WRITE_SRC2_B32 0x8d +#define SQ_DS_MIN_SRC2_F32 0x92 +#define SQ_DS_MAX_SRC2_F32 0x93 +#define SQ_DS_ADD_SRC2_F32 0x95 +#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x98 +#define SQ_DS_GWS_INIT 0x99 +#define SQ_DS_GWS_SEMA_V 0x9a +#define SQ_DS_GWS_SEMA_BR 0x9b +#define SQ_DS_GWS_SEMA_P 0x9c +#define SQ_DS_GWS_BARRIER 0x9d +#define SQ_DS_CONSUME 0xbd +#define SQ_DS_APPEND 0xbe +#define SQ_DS_ORDERED_COUNT 0xbf +#define SQ_DS_ADD_SRC2_U64 0xc0 +#define SQ_DS_SUB_SRC2_U64 0xc1 +#define SQ_DS_RSUB_SRC2_U64 0xc2 +#define SQ_DS_INC_SRC2_U64 0xc3 +#define SQ_DS_DEC_SRC2_U64 0xc4 +#define SQ_DS_MIN_SRC2_I64 0xc5 +#define SQ_DS_MAX_SRC2_I64 0xc6 +#define SQ_DS_MIN_SRC2_U64 0xc7 +#define SQ_DS_MAX_SRC2_U64 0xc8 +#define SQ_DS_AND_SRC2_B64 0xc9 +#define SQ_DS_OR_SRC2_B64 0xca +#define SQ_DS_XOR_SRC2_B64 0xcb +#define SQ_DS_WRITE_SRC2_B64 0xcd +#define SQ_DS_MIN_SRC2_F64 0xd2 +#define SQ_DS_MAX_SRC2_F64 0xd3 +#define SQ_DS_WRITE_B96 0xde +#define SQ_DS_WRITE_B128 0xdf +#define SQ_DS_CONDXCHG32_RTN_B128 0xfd +#define SQ_DS_READ_B96 0xfe +#define SQ_DS_READ_B128 0xff +#define SQ_BUFFER_LOAD_FORMAT_X 0x0 +#define SQ_BUFFER_LOAD_FORMAT_XY 0x1 +#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2 +#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x3 +#define SQ_BUFFER_STORE_FORMAT_X 0x4 +#define SQ_BUFFER_STORE_FORMAT_XY 0x5 +#define SQ_BUFFER_STORE_FORMAT_XYZ 0x6 +#define SQ_BUFFER_STORE_FORMAT_XYZW 0x7 +#define SQ_BUFFER_LOAD_FORMAT_D16_X 0x8 +#define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x9 +#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0xa +#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0xb +#define SQ_BUFFER_STORE_FORMAT_D16_X 0xc +#define SQ_BUFFER_STORE_FORMAT_D16_XY 0xd +#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0xe +#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0xf +#define SQ_BUFFER_LOAD_UBYTE 0x10 +#define SQ_BUFFER_LOAD_SBYTE 0x11 +#define SQ_BUFFER_LOAD_USHORT 0x12 +#define SQ_BUFFER_LOAD_SSHORT 0x13 +#define SQ_BUFFER_LOAD_DWORD 0x14 +#define SQ_BUFFER_LOAD_DWORDX2 0x15 +#define SQ_BUFFER_LOAD_DWORDX3 0x16 +#define SQ_BUFFER_LOAD_DWORDX4 0x17 +#define SQ_BUFFER_STORE_BYTE 0x18 +#define SQ_BUFFER_STORE_SHORT 0x1a +#define SQ_BUFFER_STORE_DWORD 0x1c +#define SQ_BUFFER_STORE_DWORDX2 0x1d +#define SQ_BUFFER_STORE_DWORDX3 0x1e +#define SQ_BUFFER_STORE_DWORDX4 0x1f +#define SQ_BUFFER_STORE_LDS_DWORD 0x3d +#define SQ_BUFFER_WBINVL1 0x3e +#define SQ_BUFFER_WBINVL1_VOL 0x3f +#define SQ_BUFFER_ATOMIC_SWAP 0x40 +#define SQ_BUFFER_ATOMIC_CMPSWAP 0x41 +#define SQ_BUFFER_ATOMIC_ADD 0x42 +#define SQ_BUFFER_ATOMIC_SUB 0x43 +#define SQ_BUFFER_ATOMIC_SMIN 0x44 +#define SQ_BUFFER_ATOMIC_UMIN 0x45 +#define SQ_BUFFER_ATOMIC_SMAX 0x46 +#define SQ_BUFFER_ATOMIC_UMAX 0x47 +#define SQ_BUFFER_ATOMIC_AND 0x48 +#define SQ_BUFFER_ATOMIC_OR 0x49 +#define SQ_BUFFER_ATOMIC_XOR 0x4a +#define SQ_BUFFER_ATOMIC_INC 0x4b +#define SQ_BUFFER_ATOMIC_DEC 0x4c +#define SQ_BUFFER_ATOMIC_SWAP_X2 0x60 +#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x61 +#define SQ_BUFFER_ATOMIC_ADD_X2 0x62 +#define SQ_BUFFER_ATOMIC_SUB_X2 0x63 +#define SQ_BUFFER_ATOMIC_SMIN_X2 0x64 +#define SQ_BUFFER_ATOMIC_UMIN_X2 0x65 +#define SQ_BUFFER_ATOMIC_SMAX_X2 0x66 +#define SQ_BUFFER_ATOMIC_UMAX_X2 0x67 +#define SQ_BUFFER_ATOMIC_AND_X2 0x68 +#define SQ_BUFFER_ATOMIC_OR_X2 0x69 +#define SQ_BUFFER_ATOMIC_XOR_X2 0x6a +#define SQ_BUFFER_ATOMIC_INC_X2 0x6b +#define SQ_BUFFER_ATOMIC_DEC_X2 0x6c +#define SQ_EXEC_LO 0x7e +#define SQ_EXEC_HI 0x7f +#define SQ_SRC_SCC 0xfd +#define SQ_OMOD_OFF 0x0 +#define SQ_OMOD_M2 0x1 +#define SQ_OMOD_M4 0x2 +#define SQ_OMOD_D2 0x3 +#define SQ_DPP_QUAD_PERM 0x0 +#define SQ_DPP_ROW_SL1 0x101 +#define SQ_DPP_ROW_SL2 0x102 +#define SQ_DPP_ROW_SL3 0x103 +#define SQ_DPP_ROW_SL4 0x104 +#define SQ_DPP_ROW_SL5 0x105 +#define SQ_DPP_ROW_SL6 0x106 +#define SQ_DPP_ROW_SL7 0x107 +#define SQ_DPP_ROW_SL8 0x108 +#define SQ_DPP_ROW_SL9 0x109 +#define SQ_DPP_ROW_SL10 0x10a +#define SQ_DPP_ROW_SL11 0x10b +#define SQ_DPP_ROW_SL12 0x10c +#define SQ_DPP_ROW_SL13 0x10d +#define SQ_DPP_ROW_SL14 0x10e +#define SQ_DPP_ROW_SL15 0x10f +#define SQ_DPP_ROW_SR1 0x111 +#define SQ_DPP_ROW_SR2 0x112 +#define SQ_DPP_ROW_SR3 0x113 +#define SQ_DPP_ROW_SR4 0x114 +#define SQ_DPP_ROW_SR5 0x115 +#define SQ_DPP_ROW_SR6 0x116 +#define SQ_DPP_ROW_SR7 0x117 +#define SQ_DPP_ROW_SR8 0x118 +#define SQ_DPP_ROW_SR9 0x119 +#define SQ_DPP_ROW_SR10 0x11a +#define SQ_DPP_ROW_SR11 0x11b +#define SQ_DPP_ROW_SR12 0x11c +#define SQ_DPP_ROW_SR13 0x11d +#define SQ_DPP_ROW_SR14 0x11e +#define SQ_DPP_ROW_SR15 0x11f +#define SQ_DPP_ROW_RR1 0x121 +#define SQ_DPP_ROW_RR2 0x122 +#define SQ_DPP_ROW_RR3 0x123 +#define SQ_DPP_ROW_RR4 0x124 +#define SQ_DPP_ROW_RR5 0x125 +#define SQ_DPP_ROW_RR6 0x126 +#define SQ_DPP_ROW_RR7 0x127 +#define SQ_DPP_ROW_RR8 0x128 +#define SQ_DPP_ROW_RR9 0x129 +#define SQ_DPP_ROW_RR10 0x12a +#define SQ_DPP_ROW_RR11 0x12b +#define SQ_DPP_ROW_RR12 0x12c +#define SQ_DPP_ROW_RR13 0x12d +#define SQ_DPP_ROW_RR14 0x12e +#define SQ_DPP_ROW_RR15 0x12f +#define SQ_DPP_WF_SL1 0x130 +#define SQ_DPP_WF_RL1 0x134 +#define SQ_DPP_WF_SR1 0x138 +#define SQ_DPP_WF_RR1 0x13c +#define SQ_DPP_ROW_MIRROR 0x140 +#define SQ_DPP_ROW_HALF_MIRROR 0x141 +#define SQ_DPP_ROW_BCAST15 0x142 +#define SQ_DPP_ROW_BCAST31 0x143 +#define SQ_EXP_GDS0 0x18 +#define SQ_GS_OP_NOP 0x0 +#define SQ_GS_OP_CUT 0x1 +#define SQ_GS_OP_EMIT 0x2 +#define SQ_GS_OP_EMIT_CUT 0x3 +#define SQ_IMAGE_LOAD 0x0 +#define SQ_IMAGE_LOAD_MIP 0x1 +#define SQ_IMAGE_LOAD_PCK 0x2 +#define SQ_IMAGE_LOAD_PCK_SGN 0x3 +#define SQ_IMAGE_LOAD_MIP_PCK 0x4 +#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x5 +#define SQ_IMAGE_STORE 0x8 +#define SQ_IMAGE_STORE_MIP 0x9 +#define SQ_IMAGE_STORE_PCK 0xa +#define SQ_IMAGE_STORE_MIP_PCK 0xb +#define SQ_IMAGE_GET_RESINFO 0xe +#define SQ_IMAGE_ATOMIC_SWAP 0x10 +#define SQ_IMAGE_ATOMIC_CMPSWAP 0x11 +#define SQ_IMAGE_ATOMIC_ADD 0x12 +#define SQ_IMAGE_ATOMIC_SUB 0x13 +#define SQ_IMAGE_ATOMIC_SMIN 0x14 +#define SQ_IMAGE_ATOMIC_UMIN 0x15 +#define SQ_IMAGE_ATOMIC_SMAX 0x16 +#define SQ_IMAGE_ATOMIC_UMAX 0x17 +#define SQ_IMAGE_ATOMIC_AND 0x18 +#define SQ_IMAGE_ATOMIC_OR 0x19 +#define SQ_IMAGE_ATOMIC_XOR 0x1a +#define SQ_IMAGE_ATOMIC_INC 0x1b +#define SQ_IMAGE_ATOMIC_DEC 0x1c +#define SQ_IMAGE_SAMPLE 0x20 +#define SQ_IMAGE_SAMPLE_CL 0x21 +#define SQ_IMAGE_SAMPLE_D 0x22 +#define SQ_IMAGE_SAMPLE_D_CL 0x23 +#define SQ_IMAGE_SAMPLE_L 0x24 +#define SQ_IMAGE_SAMPLE_B 0x25 +#define SQ_IMAGE_SAMPLE_B_CL 0x26 +#define SQ_IMAGE_SAMPLE_LZ 0x27 +#define SQ_IMAGE_SAMPLE_C 0x28 +#define SQ_IMAGE_SAMPLE_C_CL 0x29 +#define SQ_IMAGE_SAMPLE_C_D 0x2a +#define SQ_IMAGE_SAMPLE_C_D_CL 0x2b +#define SQ_IMAGE_SAMPLE_C_L 0x2c +#define SQ_IMAGE_SAMPLE_C_B 0x2d +#define SQ_IMAGE_SAMPLE_C_B_CL 0x2e +#define SQ_IMAGE_SAMPLE_C_LZ 0x2f +#define SQ_IMAGE_SAMPLE_O 0x30 +#define SQ_IMAGE_SAMPLE_CL_O 0x31 +#define SQ_IMAGE_SAMPLE_D_O 0x32 +#define SQ_IMAGE_SAMPLE_D_CL_O 0x33 +#define SQ_IMAGE_SAMPLE_L_O 0x34 +#define SQ_IMAGE_SAMPLE_B_O 0x35 +#define SQ_IMAGE_SAMPLE_B_CL_O 0x36 +#define SQ_IMAGE_SAMPLE_LZ_O 0x37 +#define SQ_IMAGE_SAMPLE_C_O 0x38 +#define SQ_IMAGE_SAMPLE_C_CL_O 0x39 +#define SQ_IMAGE_SAMPLE_C_D_O 0x3a +#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x3b +#define SQ_IMAGE_SAMPLE_C_L_O 0x3c +#define SQ_IMAGE_SAMPLE_C_B_O 0x3d +#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x3e +#define SQ_IMAGE_SAMPLE_C_LZ_O 0x3f +#define SQ_IMAGE_GATHER4 0x40 +#define SQ_IMAGE_GATHER4_CL 0x41 +#define SQ_IMAGE_GATHER4_L 0x44 +#define SQ_IMAGE_GATHER4_B 0x45 +#define SQ_IMAGE_GATHER4_B_CL 0x46 +#define SQ_IMAGE_GATHER4_LZ 0x47 +#define SQ_IMAGE_GATHER4_C 0x48 +#define SQ_IMAGE_GATHER4_C_CL 0x49 +#define SQ_IMAGE_GATHER4_C_L 0x4c +#define SQ_IMAGE_GATHER4_C_B 0x4d +#define SQ_IMAGE_GATHER4_C_B_CL 0x4e +#define SQ_IMAGE_GATHER4_C_LZ 0x4f +#define SQ_IMAGE_GATHER4_O 0x50 +#define SQ_IMAGE_GATHER4_CL_O 0x51 +#define SQ_IMAGE_GATHER4_L_O 0x54 +#define SQ_IMAGE_GATHER4_B_O 0x55 +#define SQ_IMAGE_GATHER4_B_CL_O 0x56 +#define SQ_IMAGE_GATHER4_LZ_O 0x57 +#define SQ_IMAGE_GATHER4_C_O 0x58 +#define SQ_IMAGE_GATHER4_C_CL_O 0x59 +#define SQ_IMAGE_GATHER4_C_L_O 0x5c +#define SQ_IMAGE_GATHER4_C_B_O 0x5d +#define SQ_IMAGE_GATHER4_C_B_CL_O 0x5e +#define SQ_IMAGE_GATHER4_C_LZ_O 0x5f +#define SQ_IMAGE_GET_LOD 0x60 +#define SQ_IMAGE_SAMPLE_CD 0x68 +#define SQ_IMAGE_SAMPLE_CD_CL 0x69 +#define SQ_IMAGE_SAMPLE_C_CD 0x6a +#define SQ_IMAGE_SAMPLE_C_CD_CL 0x6b +#define SQ_IMAGE_SAMPLE_CD_O 0x6c +#define SQ_IMAGE_SAMPLE_CD_CL_O 0x6d +#define SQ_IMAGE_SAMPLE_C_CD_O 0x6e +#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6f +#define SQ_IMAGE_RSRC256 0x7e +#define SQ_IMAGE_SAMPLER 0x7f +#define SQ_SRC_VCCZ 0xfb +#define SQ_SRC_VGPR0 0x100 +#define SQ_SDWA_BYTE_0 0x0 +#define SQ_SDWA_BYTE_1 0x1 +#define SQ_SDWA_BYTE_2 0x2 +#define SQ_SDWA_BYTE_3 0x3 +#define SQ_SDWA_WORD_0 0x4 +#define SQ_SDWA_WORD_1 0x5 +#define SQ_SDWA_DWORD 0x6 +#define SQ_XNACK_MASK_LO 0x68 +#define SQ_XNACK_MASK_HI 0x69 +#define SQ_TBUFFER_LOAD_FORMAT_X 0x0 +#define SQ_TBUFFER_LOAD_FORMAT_XY 0x1 +#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2 +#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x3 +#define SQ_TBUFFER_STORE_FORMAT_X 0x4 +#define SQ_TBUFFER_STORE_FORMAT_XY 0x5 +#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x6 +#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x7 +#define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x8 +#define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x9 +#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0xa +#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0xb +#define SQ_TBUFFER_STORE_FORMAT_D16_X 0xc +#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0xd +#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0xe +#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0xf +#define SQ_CHAN_X 0x0 +#define SQ_CHAN_Y 0x1 +#define SQ_CHAN_Z 0x2 +#define SQ_CHAN_W 0x3 +#define SQ_V_NOP 0x0 +#define SQ_V_MOV_B32 0x1 +#define SQ_V_READFIRSTLANE_B32 0x2 +#define SQ_V_CVT_I32_F64 0x3 +#define SQ_V_CVT_F64_I32 0x4 +#define SQ_V_CVT_F32_I32 0x5 +#define SQ_V_CVT_F32_U32 0x6 +#define SQ_V_CVT_U32_F32 0x7 +#define SQ_V_CVT_I32_F32 0x8 +#define SQ_V_MOV_FED_B32 0x9 +#define SQ_V_CVT_F16_F32 0xa +#define SQ_V_CVT_F32_F16 0xb +#define SQ_V_CVT_RPI_I32_F32 0xc +#define SQ_V_CVT_FLR_I32_F32 0xd +#define SQ_V_CVT_OFF_F32_I4 0xe +#define SQ_V_CVT_F32_F64 0xf +#define SQ_V_CVT_F64_F32 0x10 +#define SQ_V_CVT_F32_UBYTE0 0x11 +#define SQ_V_CVT_F32_UBYTE1 0x12 +#define SQ_V_CVT_F32_UBYTE2 0x13 +#define SQ_V_CVT_F32_UBYTE3 0x14 +#define SQ_V_CVT_U32_F64 0x15 +#define SQ_V_CVT_F64_U32 0x16 +#define SQ_V_TRUNC_F64 0x17 +#define SQ_V_CEIL_F64 0x18 +#define SQ_V_RNDNE_F64 0x19 +#define SQ_V_FLOOR_F64 0x1a +#define SQ_V_FRACT_F32 0x1b +#define SQ_V_TRUNC_F32 0x1c +#define SQ_V_CEIL_F32 0x1d +#define SQ_V_RNDNE_F32 0x1e +#define SQ_V_FLOOR_F32 0x1f +#define SQ_V_EXP_F32 0x20 +#define SQ_V_LOG_F32 0x21 +#define SQ_V_RCP_F32 0x22 +#define SQ_V_RCP_IFLAG_F32 0x23 +#define SQ_V_RSQ_F32 0x24 +#define SQ_V_RCP_F64 0x25 +#define SQ_V_RSQ_F64 0x26 +#define SQ_V_SQRT_F32 0x27 +#define SQ_V_SQRT_F64 0x28 +#define SQ_V_SIN_F32 0x29 +#define SQ_V_COS_F32 0x2a +#define SQ_V_NOT_B32 0x2b +#define SQ_V_BFREV_B32 0x2c +#define SQ_V_FFBH_U32 0x2d +#define SQ_V_FFBL_B32 0x2e +#define SQ_V_FFBH_I32 0x2f +#define SQ_V_FREXP_EXP_I32_F64 0x30 +#define SQ_V_FREXP_MANT_F64 0x31 +#define SQ_V_FRACT_F64 0x32 +#define SQ_V_FREXP_EXP_I32_F32 0x33 +#define SQ_V_FREXP_MANT_F32 0x34 +#define SQ_V_CLREXCP 0x35 +#define SQ_V_MOVRELD_B32 0x36 +#define SQ_V_MOVRELS_B32 0x37 +#define SQ_V_MOVRELSD_B32 0x38 +#define SQ_V_CVT_F16_U16 0x39 +#define SQ_V_CVT_F16_I16 0x3a +#define SQ_V_CVT_U16_F16 0x3b +#define SQ_V_CVT_I16_F16 0x3c +#define SQ_V_RCP_F16 0x3d +#define SQ_V_SQRT_F16 0x3e +#define SQ_V_RSQ_F16 0x3f +#define SQ_V_LOG_F16 0x40 +#define SQ_V_EXP_F16 0x41 +#define SQ_V_FREXP_MANT_F16 0x42 +#define SQ_V_FREXP_EXP_I16_F16 0x43 +#define SQ_V_FLOOR_F16 0x44 +#define SQ_V_CEIL_F16 0x45 +#define SQ_V_TRUNC_F16 0x46 +#define SQ_V_RNDNE_F16 0x47 +#define SQ_V_FRACT_F16 0x48 +#define SQ_V_SIN_F16 0x49 +#define SQ_V_COS_F16 0x4a +#define SQ_V_EXP_LEGACY_F32 0x4b +#define SQ_V_LOG_LEGACY_F32 0x4c +#define SQ_SRC_SDWA 0xf9 +#define SQ_V_OPC_OFFSET 0x0 +#define SQ_V_OP2_OFFSET 0x100 +#define SQ_V_OP1_OFFSET 0x140 +#define SQ_V_INTRP_OFFSET 0x270 +#define SQ_V_INTERP_P1_F32 0x0 +#define SQ_V_INTERP_P2_F32 0x1 +#define SQ_V_INTERP_MOV_F32 0x2 +#define SQ_S_NOP 0x0 +#define SQ_S_ENDPGM 0x1 +#define SQ_S_BRANCH 0x2 +#define SQ_S_WAKEUP 0x3 +#define SQ_S_CBRANCH_SCC0 0x4 +#define SQ_S_CBRANCH_SCC1 0x5 +#define SQ_S_CBRANCH_VCCZ 0x6 +#define SQ_S_CBRANCH_VCCNZ 0x7 +#define SQ_S_CBRANCH_EXECZ 0x8 +#define SQ_S_CBRANCH_EXECNZ 0x9 +#define SQ_S_BARRIER 0xa +#define SQ_S_SETKILL 0xb +#define SQ_S_WAITCNT 0xc +#define SQ_S_SETHALT 0xd +#define SQ_S_SLEEP 0xe +#define SQ_S_SETPRIO 0xf +#define SQ_S_SENDMSG 0x10 +#define SQ_S_SENDMSGHALT 0x11 +#define SQ_S_TRAP 0x12 +#define SQ_S_ICACHE_INV 0x13 +#define SQ_S_INCPERFLEVEL 0x14 +#define SQ_S_DECPERFLEVEL 0x15 +#define SQ_S_TTRACEDATA 0x16 +#define SQ_S_CBRANCH_CDBGSYS 0x17 +#define SQ_S_CBRANCH_CDBGUSER 0x18 +#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19 +#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1a +#define SQ_S_ENDPGM_SAVED 0x1b +#define SQ_S_SET_GPR_IDX_OFF 0x1c +#define SQ_S_SET_GPR_IDX_MODE 0x1d +#define SQ_SRC_DPP 0xfa +#define SQ_SRC_LITERAL 0xff +#define SQ_VCC_LO 0x6a +#define SQ_VCC_HI 0x6b +#define SQ_PARAM_P10 0x0 +#define SQ_PARAM_P20 0x1 +#define SQ_PARAM_P0 0x2 +#define SQ_SRC_LDS_DIRECT 0xfe +#define SQ_V_CNDMASK_B32 0x0 +#define SQ_V_ADD_F32 0x1 +#define SQ_V_SUB_F32 0x2 +#define SQ_V_SUBREV_F32 0x3 +#define SQ_V_MUL_LEGACY_F32 0x4 +#define SQ_V_MUL_F32 0x5 +#define SQ_V_MUL_I32_I24 0x6 +#define SQ_V_MUL_HI_I32_I24 0x7 +#define SQ_V_MUL_U32_U24 0x8 +#define SQ_V_MUL_HI_U32_U24 0x9 +#define SQ_V_MIN_F32 0xa +#define SQ_V_MAX_F32 0xb +#define SQ_V_MIN_I32 0xc +#define SQ_V_MAX_I32 0xd +#define SQ_V_MIN_U32 0xe +#define SQ_V_MAX_U32 0xf +#define SQ_V_LSHRREV_B32 0x10 +#define SQ_V_ASHRREV_I32 0x11 +#define SQ_V_LSHLREV_B32 0x12 +#define SQ_V_AND_B32 0x13 +#define SQ_V_OR_B32 0x14 +#define SQ_V_XOR_B32 0x15 +#define SQ_V_MAC_F32 0x16 +#define SQ_V_MADMK_F32 0x17 +#define SQ_V_MADAK_F32 0x18 +#define SQ_V_ADD_U32 0x19 +#define SQ_V_SUB_U32 0x1a +#define SQ_V_SUBREV_U32 0x1b +#define SQ_V_ADDC_U32 0x1c +#define SQ_V_SUBB_U32 0x1d +#define SQ_V_SUBBREV_U32 0x1e +#define SQ_V_ADD_F16 0x1f +#define SQ_V_SUB_F16 0x20 +#define SQ_V_SUBREV_F16 0x21 +#define SQ_V_MUL_F16 0x22 +#define SQ_V_MAC_F16 0x23 +#define SQ_V_MADMK_F16 0x24 +#define SQ_V_MADAK_F16 0x25 +#define SQ_V_ADD_U16 0x26 +#define SQ_V_SUB_U16 0x27 +#define SQ_V_SUBREV_U16 0x28 +#define SQ_V_MUL_LO_U16 0x29 +#define SQ_V_LSHLREV_B16 0x2a +#define SQ_V_LSHRREV_B16 0x2b +#define SQ_V_ASHRREV_I16 0x2c +#define SQ_V_MAX_F16 0x2d +#define SQ_V_MIN_F16 0x2e +#define SQ_V_MAX_U16 0x2f +#define SQ_V_MAX_I16 0x30 +#define SQ_V_MIN_U16 0x31 +#define SQ_V_MIN_I16 0x32 +#define SQ_V_LDEXP_F16 0x33 +#define SQ_FLAT_LOAD_UBYTE 0x10 +#define SQ_FLAT_LOAD_SBYTE 0x11 +#define SQ_FLAT_LOAD_USHORT 0x12 +#define SQ_FLAT_LOAD_SSHORT 0x13 +#define SQ_FLAT_LOAD_DWORD 0x14 +#define SQ_FLAT_LOAD_DWORDX2 0x15 +#define SQ_FLAT_LOAD_DWORDX3 0x16 +#define SQ_FLAT_LOAD_DWORDX4 0x17 +#define SQ_FLAT_STORE_BYTE 0x18 +#define SQ_FLAT_STORE_SHORT 0x1a +#define SQ_FLAT_STORE_DWORD 0x1c +#define SQ_FLAT_STORE_DWORDX2 0x1d +#define SQ_FLAT_STORE_DWORDX3 0x1e +#define SQ_FLAT_STORE_DWORDX4 0x1f +#define SQ_FLAT_ATOMIC_SWAP 0x40 +#define SQ_FLAT_ATOMIC_CMPSWAP 0x41 +#define SQ_FLAT_ATOMIC_ADD 0x42 +#define SQ_FLAT_ATOMIC_SUB 0x43 +#define SQ_FLAT_ATOMIC_SMIN 0x44 +#define SQ_FLAT_ATOMIC_UMIN 0x45 +#define SQ_FLAT_ATOMIC_SMAX 0x46 +#define SQ_FLAT_ATOMIC_UMAX 0x47 +#define SQ_FLAT_ATOMIC_AND 0x48 +#define SQ_FLAT_ATOMIC_OR 0x49 +#define SQ_FLAT_ATOMIC_XOR 0x4a +#define SQ_FLAT_ATOMIC_INC 0x4b +#define SQ_FLAT_ATOMIC_DEC 0x4c +#define SQ_FLAT_ATOMIC_SWAP_X2 0x60 +#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x61 +#define SQ_FLAT_ATOMIC_ADD_X2 0x62 +#define SQ_FLAT_ATOMIC_SUB_X2 0x63 +#define SQ_FLAT_ATOMIC_SMIN_X2 0x64 +#define SQ_FLAT_ATOMIC_UMIN_X2 0x65 +#define SQ_FLAT_ATOMIC_SMAX_X2 0x66 +#define SQ_FLAT_ATOMIC_UMAX_X2 0x67 +#define SQ_FLAT_ATOMIC_AND_X2 0x68 +#define SQ_FLAT_ATOMIC_OR_X2 0x69 +#define SQ_FLAT_ATOMIC_XOR_X2 0x6a +#define SQ_FLAT_ATOMIC_INC_X2 0x6b +#define SQ_FLAT_ATOMIC_DEC_X2 0x6c +#define SQ_S_CMP_EQ_I32 0x0 +#define SQ_S_CMP_LG_I32 0x1 +#define SQ_S_CMP_GT_I32 0x2 +#define SQ_S_CMP_GE_I32 0x3 +#define SQ_S_CMP_LT_I32 0x4 +#define SQ_S_CMP_LE_I32 0x5 +#define SQ_S_CMP_EQ_U32 0x6 +#define SQ_S_CMP_LG_U32 0x7 +#define SQ_S_CMP_GT_U32 0x8 +#define SQ_S_CMP_GE_U32 0x9 +#define SQ_S_CMP_LT_U32 0xa +#define SQ_S_CMP_LE_U32 0xb +#define SQ_S_BITCMP0_B32 0xc +#define SQ_S_BITCMP1_B32 0xd +#define SQ_S_BITCMP0_B64 0xe +#define SQ_S_BITCMP1_B64 0xf +#define SQ_S_SETVSKIP 0x10 +#define SQ_S_SET_GPR_IDX_ON 0x11 +#define SQ_S_CMP_EQ_U64 0x12 +#define SQ_S_CMP_LG_U64 0x13 +#define SQ_M0 0x7c +#define SQ_V_MAD_LEGACY_F32 0x1c0 +#define SQ_V_MAD_F32 0x1c1 +#define SQ_V_MAD_I32_I24 0x1c2 +#define SQ_V_MAD_U32_U24 0x1c3 +#define SQ_V_CUBEID_F32 0x1c4 +#define SQ_V_CUBESC_F32 0x1c5 +#define SQ_V_CUBETC_F32 0x1c6 +#define SQ_V_CUBEMA_F32 0x1c7 +#define SQ_V_BFE_U32 0x1c8 +#define SQ_V_BFE_I32 0x1c9 +#define SQ_V_BFI_B32 0x1ca +#define SQ_V_FMA_F32 0x1cb +#define SQ_V_FMA_F64 0x1cc +#define SQ_V_LERP_U8 0x1cd +#define SQ_V_ALIGNBIT_B32 0x1ce +#define SQ_V_ALIGNBYTE_B32 0x1cf +#define SQ_V_MIN3_F32 0x1d0 +#define SQ_V_MIN3_I32 0x1d1 +#define SQ_V_MIN3_U32 0x1d2 +#define SQ_V_MAX3_F32 0x1d3 +#define SQ_V_MAX3_I32 0x1d4 +#define SQ_V_MAX3_U32 0x1d5 +#define SQ_V_MED3_F32 0x1d6 +#define SQ_V_MED3_I32 0x1d7 +#define SQ_V_MED3_U32 0x1d8 +#define SQ_V_SAD_U8 0x1d9 +#define SQ_V_SAD_HI_U8 0x1da +#define SQ_V_SAD_U16 0x1db +#define SQ_V_SAD_U32 0x1dc +#define SQ_V_CVT_PK_U8_F32 0x1dd +#define SQ_V_DIV_FIXUP_F32 0x1de +#define SQ_V_DIV_FIXUP_F64 0x1df +#define SQ_V_DIV_SCALE_F32 0x1e0 +#define SQ_V_DIV_SCALE_F64 0x1e1 +#define SQ_V_DIV_FMAS_F32 0x1e2 +#define SQ_V_DIV_FMAS_F64 0x1e3 +#define SQ_V_MSAD_U8 0x1e4 +#define SQ_V_QSAD_PK_U16_U8 0x1e5 +#define SQ_V_MQSAD_PK_U16_U8 0x1e6 +#define SQ_V_MQSAD_U32_U8 0x1e7 +#define SQ_V_MAD_U64_U32 0x1e8 +#define SQ_V_MAD_I64_I32 0x1e9 +#define SQ_V_MAD_F16 0x1ea +#define SQ_V_MAD_U16 0x1eb +#define SQ_V_MAD_I16 0x1ec +#define SQ_V_PERM_B32 0x1ed +#define SQ_V_FMA_F16 0x1ee +#define SQ_V_DIV_FIXUP_F16 0x1ef +#define SQ_V_CVT_PKACCUM_U8_F32 0x1f0 +#define SQ_V_INTERP_P1LL_F16 0x274 +#define SQ_V_INTERP_P1LV_F16 0x275 +#define SQ_V_INTERP_P2_F16 0x276 +#define SQ_V_ADD_F64 0x280 +#define SQ_V_MUL_F64 0x281 +#define SQ_V_MIN_F64 0x282 +#define SQ_V_MAX_F64 0x283 +#define SQ_V_LDEXP_F64 0x284 +#define SQ_V_MUL_LO_U32 0x285 +#define SQ_V_MUL_HI_U32 0x286 +#define SQ_V_MUL_HI_I32 0x287 +#define SQ_V_LDEXP_F32 0x288 +#define SQ_V_READLANE_B32 0x289 +#define SQ_V_WRITELANE_B32 0x28a +#define SQ_V_BCNT_U32_B32 0x28b +#define SQ_V_MBCNT_LO_U32_B32 0x28c +#define SQ_V_MBCNT_HI_U32_B32 0x28d +#define SQ_V_MAC_LEGACY_F32 0x28e +#define SQ_V_LSHLREV_B64 0x28f +#define SQ_V_LSHRREV_B64 0x290 +#define SQ_V_ASHRREV_I64 0x291 +#define SQ_V_TRIG_PREOP_F64 0x292 +#define SQ_V_BFM_B32 0x293 +#define SQ_V_CVT_PKNORM_I16_F32 0x294 +#define SQ_V_CVT_PKNORM_U16_F32 0x295 +#define SQ_V_CVT_PKRTZ_F16_F32 0x296 +#define SQ_V_CVT_PK_U16_U32 0x297 +#define SQ_V_CVT_PK_I16_I32 0x298 +#define SQ_VCC_ALL 0x0 +#define SQ_SRC_EXECZ 0xfc +#define SQ_FLAT_SCRATCH_LO 0x66 +#define SQ_FLAT_SCRATCH_HI 0x67 +#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x1 +#define SQ_SYSMSG_OP_REG_RD 0x2 +#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x3 +#define SQ_SYSMSG_OP_TTRACE_PC 0x4 +#define SQ_HW_REG_MODE 0x1 +#define SQ_HW_REG_STATUS 0x2 +#define SQ_HW_REG_TRAPSTS 0x3 +#define SQ_HW_REG_HW_ID 0x4 +#define SQ_HW_REG_GPR_ALLOC 0x5 +#define SQ_HW_REG_LDS_ALLOC 0x6 +#define SQ_HW_REG_IB_STS 0x7 +#define SQ_HW_REG_PC_LO 0x8 +#define SQ_HW_REG_PC_HI 0x9 +#define SQ_HW_REG_INST_DW0 0xa +#define SQ_HW_REG_INST_DW1 0xb +#define SQ_HW_REG_IB_DBG0 0xc +#define SQ_HW_REG_IB_DBG1 0xd +#define SQ_DPP_BOUND_OFF 0x0 +#define SQ_DPP_BOUND_ZERO 0x1 +#define SQ_R1 0x1 +#define SQ_R2 0x2 +#define SQ_R3 0x3 +#define SQ_R4 0x4 +#define SQ_R5 0x5 +#define SQ_R6 0x6 +#define SQ_R7 0x7 +#define SQ_R8 0x8 +#define SQ_R9 0x9 +#define SQ_R10 0xa +#define SQ_R11 0xb +#define SQ_R12 0xc +#define SQ_R13 0xd +#define SQ_R14 0xe +#define SQ_R15 0xf +#define SQ_S_ADD_U32 0x0 +#define SQ_S_SUB_U32 0x1 +#define SQ_S_ADD_I32 0x2 +#define SQ_S_SUB_I32 0x3 +#define SQ_S_ADDC_U32 0x4 +#define SQ_S_SUBB_U32 0x5 +#define SQ_S_MIN_I32 0x6 +#define SQ_S_MIN_U32 0x7 +#define SQ_S_MAX_I32 0x8 +#define SQ_S_MAX_U32 0x9 +#define SQ_S_CSELECT_B32 0xa +#define SQ_S_CSELECT_B64 0xb +#define SQ_S_AND_B32 0xc +#define SQ_S_AND_B64 0xd +#define SQ_S_OR_B32 0xe +#define SQ_S_OR_B64 0xf +#define SQ_S_XOR_B32 0x10 +#define SQ_S_XOR_B64 0x11 +#define SQ_S_ANDN2_B32 0x12 +#define SQ_S_ANDN2_B64 0x13 +#define SQ_S_ORN2_B32 0x14 +#define SQ_S_ORN2_B64 0x15 +#define SQ_S_NAND_B32 0x16 +#define SQ_S_NAND_B64 0x17 +#define SQ_S_NOR_B32 0x18 +#define SQ_S_NOR_B64 0x19 +#define SQ_S_XNOR_B32 0x1a +#define SQ_S_XNOR_B64 0x1b +#define SQ_S_LSHL_B32 0x1c +#define SQ_S_LSHL_B64 0x1d +#define SQ_S_LSHR_B32 0x1e +#define SQ_S_LSHR_B64 0x1f +#define SQ_S_ASHR_I32 0x20 +#define SQ_S_ASHR_I64 0x21 +#define SQ_S_BFM_B32 0x22 +#define SQ_S_BFM_B64 0x23 +#define SQ_S_MUL_I32 0x24 +#define SQ_S_BFE_U32 0x25 +#define SQ_S_BFE_I32 0x26 +#define SQ_S_BFE_U64 0x27 +#define SQ_S_BFE_I64 0x28 +#define SQ_S_CBRANCH_G_FORK 0x29 +#define SQ_S_ABSDIFF_I32 0x2a +#define SQ_S_RFE_RESTORE_B64 0x2b +#define SQ_MSG_INTERRUPT 0x1 +#define SQ_MSG_GS 0x2 +#define SQ_MSG_GS_DONE 0x3 +#define SQ_MSG_SAVEWAVE 0x4 +#define SQ_MSG_SYSMSG 0xf +typedef enum TEX_BORDER_COLOR_TYPE { + TEX_BorderColor_TransparentBlack = 0x0, + TEX_BorderColor_OpaqueBlack = 0x1, + TEX_BorderColor_OpaqueWhite = 0x2, + TEX_BorderColor_Register = 0x3, +} TEX_BORDER_COLOR_TYPE; +typedef enum TEX_CHROMA_KEY { + TEX_ChromaKey_Disabled = 0x0, + TEX_ChromaKey_Kill = 0x1, + TEX_ChromaKey_Blend = 0x2, + TEX_ChromaKey_RESERVED_3 = 0x3, +} TEX_CHROMA_KEY; +typedef enum TEX_CLAMP { + TEX_Clamp_Repeat = 0x0, + TEX_Clamp_Mirror = 0x1, + TEX_Clamp_ClampToLast = 0x2, + TEX_Clamp_MirrorOnceToLast = 0x3, + TEX_Clamp_ClampHalfToBorder = 0x4, + TEX_Clamp_MirrorOnceHalfToBorder = 0x5, + TEX_Clamp_ClampToBorder = 0x6, + TEX_Clamp_MirrorOnceToBorder = 0x7, +} TEX_CLAMP; +typedef enum TEX_COORD_TYPE { + TEX_CoordType_Unnormalized = 0x0, + TEX_CoordType_Normalized = 0x1, +} TEX_COORD_TYPE; +typedef enum TEX_DEPTH_COMPARE_FUNCTION { + TEX_DepthCompareFunction_Never = 0x0, + TEX_DepthCompareFunction_Less = 0x1, + TEX_DepthCompareFunction_Equal = 0x2, + TEX_DepthCompareFunction_LessEqual = 0x3, + TEX_DepthCompareFunction_Greater = 0x4, + TEX_DepthCompareFunction_NotEqual = 0x5, + TEX_DepthCompareFunction_GreaterEqual = 0x6, + TEX_DepthCompareFunction_Always = 0x7, +} TEX_DEPTH_COMPARE_FUNCTION; +typedef enum TEX_DIM { + TEX_Dim_1D = 0x0, + TEX_Dim_2D = 0x1, + TEX_Dim_3D = 0x2, + TEX_Dim_CubeMap = 0x3, + TEX_Dim_1DArray = 0x4, + TEX_Dim_2DArray = 0x5, + TEX_Dim_2D_MSAA = 0x6, + TEX_Dim_2DArray_MSAA = 0x7, +} TEX_DIM; +typedef enum TEX_FORMAT_COMP { + TEX_FormatComp_Unsigned = 0x0, + TEX_FormatComp_Signed = 0x1, + TEX_FormatComp_UnsignedBiased = 0x2, + TEX_FormatComp_RESERVED_3 = 0x3, +} TEX_FORMAT_COMP; +typedef enum TEX_MAX_ANISO_RATIO { + TEX_MaxAnisoRatio_1to1 = 0x0, + TEX_MaxAnisoRatio_2to1 = 0x1, + TEX_MaxAnisoRatio_4to1 = 0x2, + TEX_MaxAnisoRatio_8to1 = 0x3, + TEX_MaxAnisoRatio_16to1 = 0x4, + TEX_MaxAnisoRatio_RESERVED_5 = 0x5, + TEX_MaxAnisoRatio_RESERVED_6 = 0x6, + TEX_MaxAnisoRatio_RESERVED_7 = 0x7, +} TEX_MAX_ANISO_RATIO; +typedef enum TEX_MIP_FILTER { + TEX_MipFilter_None = 0x0, + TEX_MipFilter_Point = 0x1, + TEX_MipFilter_Linear = 0x2, + TEX_MipFilter_Point_Aniso_Adj = 0x3, +} TEX_MIP_FILTER; +typedef enum TEX_REQUEST_SIZE { + TEX_RequestSize_32B = 0x0, + TEX_RequestSize_64B = 0x1, + TEX_RequestSize_128B = 0x2, + TEX_RequestSize_2X64B = 0x3, +} TEX_REQUEST_SIZE; +typedef enum TEX_SAMPLER_TYPE { + TEX_SamplerType_Invalid = 0x0, + TEX_SamplerType_Valid = 0x1, +} TEX_SAMPLER_TYPE; +typedef enum TEX_XY_FILTER { + TEX_XYFilter_Point = 0x0, + TEX_XYFilter_Linear = 0x1, + TEX_XYFilter_AnisoPoint = 0x2, + TEX_XYFilter_AnisoLinear = 0x3, +} TEX_XY_FILTER; +typedef enum TEX_Z_FILTER { + TEX_ZFilter_None = 0x0, + TEX_ZFilter_Point = 0x1, + TEX_ZFilter_Linear = 0x2, + TEX_ZFilter_RESERVED_3 = 0x3, +} TEX_Z_FILTER; +typedef enum VTX_CLAMP { + VTX_Clamp_ClampToZero = 0x0, + VTX_Clamp_ClampToNAN = 0x1, +} VTX_CLAMP; +typedef enum VTX_FETCH_TYPE { + VTX_FetchType_VertexData = 0x0, + VTX_FetchType_InstanceData = 0x1, + VTX_FetchType_NoIndexOffset = 0x2, + VTX_FetchType_RESERVED_3 = 0x3, +} VTX_FETCH_TYPE; +typedef enum VTX_FORMAT_COMP_ALL { + VTX_FormatCompAll_Unsigned = 0x0, + VTX_FormatCompAll_Signed = 0x1, +} VTX_FORMAT_COMP_ALL; +typedef enum VTX_MEM_REQUEST_SIZE { + VTX_MemRequestSize_32B = 0x0, + VTX_MemRequestSize_64B = 0x1, +} VTX_MEM_REQUEST_SIZE; +typedef enum TVX_DATA_FORMAT { + TVX_FMT_INVALID = 0x0, + TVX_FMT_8 = 0x1, + TVX_FMT_4_4 = 0x2, + TVX_FMT_3_3_2 = 0x3, + TVX_FMT_RESERVED_4 = 0x4, + TVX_FMT_16 = 0x5, + TVX_FMT_16_FLOAT = 0x6, + TVX_FMT_8_8 = 0x7, + TVX_FMT_5_6_5 = 0x8, + TVX_FMT_6_5_5 = 0x9, + TVX_FMT_1_5_5_5 = 0xa, + TVX_FMT_4_4_4_4 = 0xb, + TVX_FMT_5_5_5_1 = 0xc, + TVX_FMT_32 = 0xd, + TVX_FMT_32_FLOAT = 0xe, + TVX_FMT_16_16 = 0xf, + TVX_FMT_16_16_FLOAT = 0x10, + TVX_FMT_8_24 = 0x11, + TVX_FMT_8_24_FLOAT = 0x12, + TVX_FMT_24_8 = 0x13, + TVX_FMT_24_8_FLOAT = 0x14, + TVX_FMT_10_11_11 = 0x15, + TVX_FMT_10_11_11_FLOAT = 0x16, + TVX_FMT_11_11_10 = 0x17, + TVX_FMT_11_11_10_FLOAT = 0x18, + TVX_FMT_2_10_10_10 = 0x19, + TVX_FMT_8_8_8_8 = 0x1a, + TVX_FMT_10_10_10_2 = 0x1b, + TVX_FMT_X24_8_32_FLOAT = 0x1c, + TVX_FMT_32_32 = 0x1d, + TVX_FMT_32_32_FLOAT = 0x1e, + TVX_FMT_16_16_16_16 = 0x1f, + TVX_FMT_16_16_16_16_FLOAT = 0x20, + TVX_FMT_RESERVED_33 = 0x21, + TVX_FMT_32_32_32_32 = 0x22, + TVX_FMT_32_32_32_32_FLOAT = 0x23, + TVX_FMT_RESERVED_36 = 0x24, + TVX_FMT_1 = 0x25, + TVX_FMT_1_REVERSED = 0x26, + TVX_FMT_GB_GR = 0x27, + TVX_FMT_BG_RG = 0x28, + TVX_FMT_32_AS_8 = 0x29, + TVX_FMT_32_AS_8_8 = 0x2a, + TVX_FMT_5_9_9_9_SHAREDEXP = 0x2b, + TVX_FMT_8_8_8 = 0x2c, + TVX_FMT_16_16_16 = 0x2d, + TVX_FMT_16_16_16_FLOAT = 0x2e, + TVX_FMT_32_32_32 = 0x2f, + TVX_FMT_32_32_32_FLOAT = 0x30, + TVX_FMT_BC1 = 0x31, + TVX_FMT_BC2 = 0x32, + TVX_FMT_BC3 = 0x33, + TVX_FMT_BC4 = 0x34, + TVX_FMT_BC5 = 0x35, + TVX_FMT_APC0 = 0x36, + TVX_FMT_APC1 = 0x37, + TVX_FMT_APC2 = 0x38, + TVX_FMT_APC3 = 0x39, + TVX_FMT_APC4 = 0x3a, + TVX_FMT_APC5 = 0x3b, + TVX_FMT_APC6 = 0x3c, + TVX_FMT_APC7 = 0x3d, + TVX_FMT_CTX1 = 0x3e, + TVX_FMT_RESERVED_63 = 0x3f, +} TVX_DATA_FORMAT; +typedef enum TVX_DST_SEL { + TVX_DstSel_X = 0x0, + TVX_DstSel_Y = 0x1, + TVX_DstSel_Z = 0x2, + TVX_DstSel_W = 0x3, + TVX_DstSel_0f = 0x4, + TVX_DstSel_1f = 0x5, + TVX_DstSel_RESERVED_6 = 0x6, + TVX_DstSel_Mask = 0x7, +} TVX_DST_SEL; +typedef enum TVX_ENDIAN_SWAP { + TVX_EndianSwap_None = 0x0, + TVX_EndianSwap_8in16 = 0x1, + TVX_EndianSwap_8in32 = 0x2, + TVX_EndianSwap_8in64 = 0x3, +} TVX_ENDIAN_SWAP; +typedef enum TVX_INST { + TVX_Inst_NormalVertexFetch = 0x0, + TVX_Inst_SemanticVertexFetch = 0x1, + TVX_Inst_RESERVED_2 = 0x2, + TVX_Inst_LD = 0x3, + TVX_Inst_GetTextureResInfo = 0x4, + TVX_Inst_GetNumberOfSamples = 0x5, + TVX_Inst_GetLOD = 0x6, + TVX_Inst_GetGradientsH = 0x7, + TVX_Inst_GetGradientsV = 0x8, + TVX_Inst_SetTextureOffsets = 0x9, + TVX_Inst_KeepGradients = 0xa, + TVX_Inst_SetGradientsH = 0xb, + TVX_Inst_SetGradientsV = 0xc, + TVX_Inst_Pass = 0xd, + TVX_Inst_GetBufferResInfo = 0xe, + TVX_Inst_RESERVED_15 = 0xf, + TVX_Inst_Sample = 0x10, + TVX_Inst_Sample_L = 0x11, + TVX_Inst_Sample_LB = 0x12, + TVX_Inst_Sample_LZ = 0x13, + TVX_Inst_Sample_G = 0x14, + TVX_Inst_Gather4 = 0x15, + TVX_Inst_Sample_G_LB = 0x16, + TVX_Inst_Gather4_O = 0x17, + TVX_Inst_Sample_C = 0x18, + TVX_Inst_Sample_C_L = 0x19, + TVX_Inst_Sample_C_LB = 0x1a, + TVX_Inst_Sample_C_LZ = 0x1b, + TVX_Inst_Sample_C_G = 0x1c, + TVX_Inst_Gather4_C = 0x1d, + TVX_Inst_Sample_C_G_LB = 0x1e, + TVX_Inst_Gather4_C_O = 0x1f, +} TVX_INST; +typedef enum TVX_NUM_FORMAT_ALL { + TVX_NumFormatAll_Norm = 0x0, + TVX_NumFormatAll_Int = 0x1, + TVX_NumFormatAll_Scaled = 0x2, + TVX_NumFormatAll_RESERVED_3 = 0x3, +} TVX_NUM_FORMAT_ALL; +typedef enum TVX_SRC_SEL { + TVX_SrcSel_X = 0x0, + TVX_SrcSel_Y = 0x1, + TVX_SrcSel_Z = 0x2, + TVX_SrcSel_W = 0x3, + TVX_SrcSel_0f = 0x4, + TVX_SrcSel_1f = 0x5, +} TVX_SRC_SEL; +typedef enum TVX_SRF_MODE_ALL { + TVX_SRFModeAll_ZCMO = 0x0, + TVX_SRFModeAll_NZ = 0x1, +} TVX_SRF_MODE_ALL; +typedef enum TVX_TYPE { + TVX_Type_InvalidTextureResource = 0x0, + TVX_Type_InvalidVertexBuffer = 0x1, + TVX_Type_ValidTextureResource = 0x2, + TVX_Type_ValidVertexBuffer = 0x3, +} TVX_TYPE; +typedef enum TC_OP_MASKS { + TC_OP_MASK_FLUSH_DENROM = 0x8, + TC_OP_MASK_64 = 0x20, + TC_OP_MASK_NO_RTN = 0x40, +} TC_OP_MASKS; +typedef enum TC_OP { + TC_OP_READ = 0x0, + TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x1, + TC_OP_ATOMIC_FMIN_RTN_32 = 0x2, + TC_OP_ATOMIC_FMAX_RTN_32 = 0x3, + TC_OP_RESERVED_FOP_RTN_32_0 = 0x4, + TC_OP_RESERVED_FOP_RTN_32_1 = 0x5, + TC_OP_RESERVED_FOP_RTN_32_2 = 0x6, + TC_OP_ATOMIC_SWAP_RTN_32 = 0x7, + TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x8, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x9, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0xa, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0xb, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0xc, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0xd, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0xe, + TC_OP_ATOMIC_ADD_RTN_32 = 0xf, + TC_OP_ATOMIC_SUB_RTN_32 = 0x10, + TC_OP_ATOMIC_SMIN_RTN_32 = 0x11, + TC_OP_ATOMIC_UMIN_RTN_32 = 0x12, + TC_OP_ATOMIC_SMAX_RTN_32 = 0x13, + TC_OP_ATOMIC_UMAX_RTN_32 = 0x14, + TC_OP_ATOMIC_AND_RTN_32 = 0x15, + TC_OP_ATOMIC_OR_RTN_32 = 0x16, + TC_OP_ATOMIC_XOR_RTN_32 = 0x17, + TC_OP_ATOMIC_INC_RTN_32 = 0x18, + TC_OP_ATOMIC_DEC_RTN_32 = 0x19, + TC_OP_WBINVL1_VOL = 0x1a, + TC_OP_WBINVL1_SD = 0x1b, + TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x1c, + TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1d, + TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x1e, + TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x1f, + TC_OP_WRITE = 0x20, + TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x21, + TC_OP_ATOMIC_FMIN_RTN_64 = 0x22, + TC_OP_ATOMIC_FMAX_RTN_64 = 0x23, + TC_OP_RESERVED_FOP_RTN_64_0 = 0x24, + TC_OP_RESERVED_FOP_RTN_64_1 = 0x25, + TC_OP_RESERVED_FOP_RTN_64_2 = 0x26, + TC_OP_ATOMIC_SWAP_RTN_64 = 0x27, + TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x28, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x29, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x2a, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x2b, + TC_OP_WBINVL2_SD = 0x2c, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x2d, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x2e, + TC_OP_ATOMIC_ADD_RTN_64 = 0x2f, + TC_OP_ATOMIC_SUB_RTN_64 = 0x30, + TC_OP_ATOMIC_SMIN_RTN_64 = 0x31, + TC_OP_ATOMIC_UMIN_RTN_64 = 0x32, + TC_OP_ATOMIC_SMAX_RTN_64 = 0x33, + TC_OP_ATOMIC_UMAX_RTN_64 = 0x34, + TC_OP_ATOMIC_AND_RTN_64 = 0x35, + TC_OP_ATOMIC_OR_RTN_64 = 0x36, + TC_OP_ATOMIC_XOR_RTN_64 = 0x37, + TC_OP_ATOMIC_INC_RTN_64 = 0x38, + TC_OP_ATOMIC_DEC_RTN_64 = 0x39, + TC_OP_WBL2_NC = 0x3a, + TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x3b, + TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x3c, + TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x3d, + TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x3e, + TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x3f, + TC_OP_WBINVL1 = 0x40, + TC_OP_ATOMIC_FCMPSWAP_32 = 0x41, + TC_OP_ATOMIC_FMIN_32 = 0x42, + TC_OP_ATOMIC_FMAX_32 = 0x43, + TC_OP_RESERVED_FOP_32_0 = 0x44, + TC_OP_RESERVED_FOP_32_1 = 0x45, + TC_OP_RESERVED_FOP_32_2 = 0x46, + TC_OP_ATOMIC_SWAP_32 = 0x47, + TC_OP_ATOMIC_CMPSWAP_32 = 0x48, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x49, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x4a, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x4b, + TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x4c, + TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x4d, + TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x4e, + TC_OP_ATOMIC_ADD_32 = 0x4f, + TC_OP_ATOMIC_SUB_32 = 0x50, + TC_OP_ATOMIC_SMIN_32 = 0x51, + TC_OP_ATOMIC_UMIN_32 = 0x52, + TC_OP_ATOMIC_SMAX_32 = 0x53, + TC_OP_ATOMIC_UMAX_32 = 0x54, + TC_OP_ATOMIC_AND_32 = 0x55, + TC_OP_ATOMIC_OR_32 = 0x56, + TC_OP_ATOMIC_XOR_32 = 0x57, + TC_OP_ATOMIC_INC_32 = 0x58, + TC_OP_ATOMIC_DEC_32 = 0x59, + TC_OP_INVL2_NC = 0x5a, + TC_OP_RESERVED_NON_FLOAT_32_0 = 0x5b, + TC_OP_RESERVED_NON_FLOAT_32_1 = 0x5c, + TC_OP_RESERVED_NON_FLOAT_32_2 = 0x5d, + TC_OP_RESERVED_NON_FLOAT_32_3 = 0x5e, + TC_OP_RESERVED_NON_FLOAT_32_4 = 0x5f, + TC_OP_WBINVL2 = 0x60, + TC_OP_ATOMIC_FCMPSWAP_64 = 0x61, + TC_OP_ATOMIC_FMIN_64 = 0x62, + TC_OP_ATOMIC_FMAX_64 = 0x63, + TC_OP_RESERVED_FOP_64_0 = 0x64, + TC_OP_RESERVED_FOP_64_1 = 0x65, + TC_OP_RESERVED_FOP_64_2 = 0x66, + TC_OP_ATOMIC_SWAP_64 = 0x67, + TC_OP_ATOMIC_CMPSWAP_64 = 0x68, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x69, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x6a, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x6b, + TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x6c, + TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x6d, + TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x6e, + TC_OP_ATOMIC_ADD_64 = 0x6f, + TC_OP_ATOMIC_SUB_64 = 0x70, + TC_OP_ATOMIC_SMIN_64 = 0x71, + TC_OP_ATOMIC_UMIN_64 = 0x72, + TC_OP_ATOMIC_SMAX_64 = 0x73, + TC_OP_ATOMIC_UMAX_64 = 0x74, + TC_OP_ATOMIC_AND_64 = 0x75, + TC_OP_ATOMIC_OR_64 = 0x76, + TC_OP_ATOMIC_XOR_64 = 0x77, + TC_OP_ATOMIC_INC_64 = 0x78, + TC_OP_ATOMIC_DEC_64 = 0x79, + TC_OP_WBINVL2_NC = 0x7a, + TC_OP_RESERVED_NON_FLOAT_64_0 = 0x7b, + TC_OP_RESERVED_NON_FLOAT_64_1 = 0x7c, + TC_OP_RESERVED_NON_FLOAT_64_2 = 0x7d, + TC_OP_RESERVED_NON_FLOAT_64_3 = 0x7e, + TC_OP_RESERVED_NON_FLOAT_64_4 = 0x7f, +} TC_OP; +typedef enum TC_CHUB_REQ_CREDITS_ENUM { + TC_CHUB_REQ_CREDITS = 0x10, +} TC_CHUB_REQ_CREDITS_ENUM; +typedef enum CHUB_TC_RET_CREDITS_ENUM { + CHUB_TC_RET_CREDITS = 0x20, +} CHUB_TC_RET_CREDITS_ENUM; +typedef enum TC_NACKS { + TC_NACK_NO_FAULT = 0x0, + TC_NACK_PAGE_FAULT = 0x1, + TC_NACK_PROTECTION_FAULT = 0x2, + TC_NACK_DATA_ERROR = 0x3, +} TC_NACKS; +typedef enum TCC_PERF_SEL { + TCC_PERF_SEL_NONE = 0x0, + TCC_PERF_SEL_CYCLE = 0x1, + TCC_PERF_SEL_BUSY = 0x2, + TCC_PERF_SEL_REQ = 0x3, + TCC_PERF_SEL_STREAMING_REQ = 0x4, + TCC_PERF_SEL_EXE_REQ = 0x5, + TCC_PERF_SEL_COMPRESSED_REQ = 0x6, + TCC_PERF_SEL_COMPRESSED_0_REQ = 0x7, + TCC_PERF_SEL_METADATA_REQ = 0x8, + TCC_PERF_SEL_NC_VIRTUAL_REQ = 0x9, + TCC_PERF_SEL_NC_PHYSICAL_REQ = 0xa, + TCC_PERF_SEL_UC_VIRTUAL_REQ = 0xb, + TCC_PERF_SEL_UC_PHYSICAL_REQ = 0xc, + TCC_PERF_SEL_CC_PHYSICAL_REQ = 0xd, + TCC_PERF_SEL_PROBE = 0xe, + TCC_PERF_SEL_READ = 0xf, + TCC_PERF_SEL_WRITE = 0x10, + TCC_PERF_SEL_ATOMIC = 0x11, + TCC_PERF_SEL_HIT = 0x12, + TCC_PERF_SEL_MISS = 0x13, + TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x14, + TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x15, + TCC_PERF_SEL_WRITEBACK = 0x16, + TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x17, + TCC_PERF_SEL_SRC_FIFO_FULL = 0x18, + TCC_PERF_SEL_HOLE_FIFO_FULL = 0x19, + TCC_PERF_SEL_MC_WRREQ = 0x1a, + TCC_PERF_SEL_MC_WRREQ_UNCACHED = 0x1b, + TCC_PERF_SEL_MC_WRREQ_STALL = 0x1c, + TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x1d, + TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL = 0x1e, + TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL = 0x1f, + TCC_PERF_SEL_MC_WRREQ_LEVEL = 0x20, + TCC_PERF_SEL_MC_ATOMIC = 0x21, + TCC_PERF_SEL_MC_ATOMIC_LEVEL = 0x22, + TCC_PERF_SEL_MC_RDREQ = 0x23, + TCC_PERF_SEL_MC_RDREQ_UNCACHED = 0x24, + TCC_PERF_SEL_MC_RDREQ_MDC = 0x25, + TCC_PERF_SEL_MC_RDREQ_COMPRESSED = 0x26, + TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL = 0x27, + TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL = 0x28, + TCC_PERF_SEL_MC_RDREQ_LEVEL = 0x29, + TCC_PERF_SEL_TAG_STALL = 0x2a, + TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x2b, + TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x2c, + TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL= 0x2d, + TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL= 0x2e, + TCC_PERF_SEL_TAG_PROBE_STALL = 0x2f, + TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x30, + TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x31, + TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x32, + TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x33, + TCC_PERF_SEL_BUBBLE = 0x34, + TCC_PERF_SEL_RETURN_ACK = 0x35, + TCC_PERF_SEL_RETURN_DATA = 0x36, + TCC_PERF_SEL_RETURN_HOLE = 0x37, + TCC_PERF_SEL_RETURN_ACK_HOLE = 0x38, + TCC_PERF_SEL_IB_REQ = 0x39, + TCC_PERF_SEL_IB_STALL = 0x3a, + TCC_PERF_SEL_IB_TAG_STALL = 0x3b, + TCC_PERF_SEL_IB_MDC_STALL = 0x3c, + TCC_PERF_SEL_TCA_LEVEL = 0x3d, + TCC_PERF_SEL_HOLE_LEVEL = 0x3e, + TCC_PERF_SEL_MC_RDRET_NACK = 0x3f, + TCC_PERF_SEL_MC_WRRET_NACK = 0x40, + TCC_PERF_SEL_NORMAL_WRITEBACK = 0x41, + TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x42, + TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x43, + TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x44, + TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x45, + TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x46, + TCC_PERF_SEL_NORMAL_EVICT = 0x47, + TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x48, + TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x49, + TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x4a, + TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x4b, + TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x4c, + TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x4d, + TCC_PERF_SEL_PROBE_EVICT = 0x4e, + TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x4f, + TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x50, + TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x51, + TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x52, + TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x53, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x54, + TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x55, + TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x56, + TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x57, + TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x58, + TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x59, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x5a, + TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x5b, + TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x5c, + TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x5d, + TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x5e, + TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x5f, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x60, + TCC_PERF_SEL_MDC_REQ = 0x61, + TCC_PERF_SEL_MDC_LEVEL = 0x62, + TCC_PERF_SEL_MDC_TAG_HIT = 0x63, + TCC_PERF_SEL_MDC_SECTOR_HIT = 0x64, + TCC_PERF_SEL_MDC_SECTOR_MISS = 0x65, + TCC_PERF_SEL_MDC_TAG_STALL = 0x66, + TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL= 0x67, + TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL= 0x68, + TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL= 0x69, + TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x6a, + TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x6b, + TCC_PERF_SEL_CLIENT0_REQ = 0x80, + TCC_PERF_SEL_CLIENT1_REQ = 0x81, + TCC_PERF_SEL_CLIENT2_REQ = 0x82, + TCC_PERF_SEL_CLIENT3_REQ = 0x83, + TCC_PERF_SEL_CLIENT4_REQ = 0x84, + TCC_PERF_SEL_CLIENT5_REQ = 0x85, + TCC_PERF_SEL_CLIENT6_REQ = 0x86, + TCC_PERF_SEL_CLIENT7_REQ = 0x87, + TCC_PERF_SEL_CLIENT8_REQ = 0x88, + TCC_PERF_SEL_CLIENT9_REQ = 0x89, + TCC_PERF_SEL_CLIENT10_REQ = 0x8a, + TCC_PERF_SEL_CLIENT11_REQ = 0x8b, + TCC_PERF_SEL_CLIENT12_REQ = 0x8c, + TCC_PERF_SEL_CLIENT13_REQ = 0x8d, + TCC_PERF_SEL_CLIENT14_REQ = 0x8e, + TCC_PERF_SEL_CLIENT15_REQ = 0x8f, + TCC_PERF_SEL_CLIENT16_REQ = 0x90, + TCC_PERF_SEL_CLIENT17_REQ = 0x91, + TCC_PERF_SEL_CLIENT18_REQ = 0x92, + TCC_PERF_SEL_CLIENT19_REQ = 0x93, + TCC_PERF_SEL_CLIENT20_REQ = 0x94, + TCC_PERF_SEL_CLIENT21_REQ = 0x95, + TCC_PERF_SEL_CLIENT22_REQ = 0x96, + TCC_PERF_SEL_CLIENT23_REQ = 0x97, + TCC_PERF_SEL_CLIENT24_REQ = 0x98, + TCC_PERF_SEL_CLIENT25_REQ = 0x99, + TCC_PERF_SEL_CLIENT26_REQ = 0x9a, + TCC_PERF_SEL_CLIENT27_REQ = 0x9b, + TCC_PERF_SEL_CLIENT28_REQ = 0x9c, + TCC_PERF_SEL_CLIENT29_REQ = 0x9d, + TCC_PERF_SEL_CLIENT30_REQ = 0x9e, + TCC_PERF_SEL_CLIENT31_REQ = 0x9f, + TCC_PERF_SEL_CLIENT32_REQ = 0xa0, + TCC_PERF_SEL_CLIENT33_REQ = 0xa1, + TCC_PERF_SEL_CLIENT34_REQ = 0xa2, + TCC_PERF_SEL_CLIENT35_REQ = 0xa3, + TCC_PERF_SEL_CLIENT36_REQ = 0xa4, + TCC_PERF_SEL_CLIENT37_REQ = 0xa5, + TCC_PERF_SEL_CLIENT38_REQ = 0xa6, + TCC_PERF_SEL_CLIENT39_REQ = 0xa7, + TCC_PERF_SEL_CLIENT40_REQ = 0xa8, + TCC_PERF_SEL_CLIENT41_REQ = 0xa9, + TCC_PERF_SEL_CLIENT42_REQ = 0xaa, + TCC_PERF_SEL_CLIENT43_REQ = 0xab, + TCC_PERF_SEL_CLIENT44_REQ = 0xac, + TCC_PERF_SEL_CLIENT45_REQ = 0xad, + TCC_PERF_SEL_CLIENT46_REQ = 0xae, + TCC_PERF_SEL_CLIENT47_REQ = 0xaf, + TCC_PERF_SEL_CLIENT48_REQ = 0xb0, + TCC_PERF_SEL_CLIENT49_REQ = 0xb1, + TCC_PERF_SEL_CLIENT50_REQ = 0xb2, + TCC_PERF_SEL_CLIENT51_REQ = 0xb3, + TCC_PERF_SEL_CLIENT52_REQ = 0xb4, + TCC_PERF_SEL_CLIENT53_REQ = 0xb5, + TCC_PERF_SEL_CLIENT54_REQ = 0xb6, + TCC_PERF_SEL_CLIENT55_REQ = 0xb7, + TCC_PERF_SEL_CLIENT56_REQ = 0xb8, + TCC_PERF_SEL_CLIENT57_REQ = 0xb9, + TCC_PERF_SEL_CLIENT58_REQ = 0xba, + TCC_PERF_SEL_CLIENT59_REQ = 0xbb, + TCC_PERF_SEL_CLIENT60_REQ = 0xbc, + TCC_PERF_SEL_CLIENT61_REQ = 0xbd, + TCC_PERF_SEL_CLIENT62_REQ = 0xbe, + TCC_PERF_SEL_CLIENT63_REQ = 0xbf, + TCC_PERF_SEL_CLIENT64_REQ = 0xc0, + TCC_PERF_SEL_CLIENT65_REQ = 0xc1, + TCC_PERF_SEL_CLIENT66_REQ = 0xc2, + TCC_PERF_SEL_CLIENT67_REQ = 0xc3, + TCC_PERF_SEL_CLIENT68_REQ = 0xc4, + TCC_PERF_SEL_CLIENT69_REQ = 0xc5, + TCC_PERF_SEL_CLIENT70_REQ = 0xc6, + TCC_PERF_SEL_CLIENT71_REQ = 0xc7, + TCC_PERF_SEL_CLIENT72_REQ = 0xc8, + TCC_PERF_SEL_CLIENT73_REQ = 0xc9, + TCC_PERF_SEL_CLIENT74_REQ = 0xca, + TCC_PERF_SEL_CLIENT75_REQ = 0xcb, + TCC_PERF_SEL_CLIENT76_REQ = 0xcc, + TCC_PERF_SEL_CLIENT77_REQ = 0xcd, + TCC_PERF_SEL_CLIENT78_REQ = 0xce, + TCC_PERF_SEL_CLIENT79_REQ = 0xcf, + TCC_PERF_SEL_CLIENT80_REQ = 0xd0, + TCC_PERF_SEL_CLIENT81_REQ = 0xd1, + TCC_PERF_SEL_CLIENT82_REQ = 0xd2, + TCC_PERF_SEL_CLIENT83_REQ = 0xd3, + TCC_PERF_SEL_CLIENT84_REQ = 0xd4, + TCC_PERF_SEL_CLIENT85_REQ = 0xd5, + TCC_PERF_SEL_CLIENT86_REQ = 0xd6, + TCC_PERF_SEL_CLIENT87_REQ = 0xd7, + TCC_PERF_SEL_CLIENT88_REQ = 0xd8, + TCC_PERF_SEL_CLIENT89_REQ = 0xd9, + TCC_PERF_SEL_CLIENT90_REQ = 0xda, + TCC_PERF_SEL_CLIENT91_REQ = 0xdb, + TCC_PERF_SEL_CLIENT92_REQ = 0xdc, + TCC_PERF_SEL_CLIENT93_REQ = 0xdd, + TCC_PERF_SEL_CLIENT94_REQ = 0xde, + TCC_PERF_SEL_CLIENT95_REQ = 0xdf, + TCC_PERF_SEL_CLIENT96_REQ = 0xe0, + TCC_PERF_SEL_CLIENT97_REQ = 0xe1, + TCC_PERF_SEL_CLIENT98_REQ = 0xe2, + TCC_PERF_SEL_CLIENT99_REQ = 0xe3, + TCC_PERF_SEL_CLIENT100_REQ = 0xe4, + TCC_PERF_SEL_CLIENT101_REQ = 0xe5, + TCC_PERF_SEL_CLIENT102_REQ = 0xe6, + TCC_PERF_SEL_CLIENT103_REQ = 0xe7, + TCC_PERF_SEL_CLIENT104_REQ = 0xe8, + TCC_PERF_SEL_CLIENT105_REQ = 0xe9, + TCC_PERF_SEL_CLIENT106_REQ = 0xea, + TCC_PERF_SEL_CLIENT107_REQ = 0xeb, + TCC_PERF_SEL_CLIENT108_REQ = 0xec, + TCC_PERF_SEL_CLIENT109_REQ = 0xed, + TCC_PERF_SEL_CLIENT110_REQ = 0xee, + TCC_PERF_SEL_CLIENT111_REQ = 0xef, + TCC_PERF_SEL_CLIENT112_REQ = 0xf0, + TCC_PERF_SEL_CLIENT113_REQ = 0xf1, + TCC_PERF_SEL_CLIENT114_REQ = 0xf2, + TCC_PERF_SEL_CLIENT115_REQ = 0xf3, + TCC_PERF_SEL_CLIENT116_REQ = 0xf4, + TCC_PERF_SEL_CLIENT117_REQ = 0xf5, + TCC_PERF_SEL_CLIENT118_REQ = 0xf6, + TCC_PERF_SEL_CLIENT119_REQ = 0xf7, + TCC_PERF_SEL_CLIENT120_REQ = 0xf8, + TCC_PERF_SEL_CLIENT121_REQ = 0xf9, + TCC_PERF_SEL_CLIENT122_REQ = 0xfa, + TCC_PERF_SEL_CLIENT123_REQ = 0xfb, + TCC_PERF_SEL_CLIENT124_REQ = 0xfc, + TCC_PERF_SEL_CLIENT125_REQ = 0xfd, + TCC_PERF_SEL_CLIENT126_REQ = 0xfe, + TCC_PERF_SEL_CLIENT127_REQ = 0xff, +} TCC_PERF_SEL; +typedef enum TCA_PERF_SEL { + TCA_PERF_SEL_NONE = 0x0, + TCA_PERF_SEL_CYCLE = 0x1, + TCA_PERF_SEL_BUSY = 0x2, + TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x3, + TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x4, + TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x5, + TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x6, + TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x7, + TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x8, + TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x9, + TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0xa, + TCA_PERF_SEL_REQ_TCC0 = 0xb, + TCA_PERF_SEL_REQ_TCC1 = 0xc, + TCA_PERF_SEL_REQ_TCC2 = 0xd, + TCA_PERF_SEL_REQ_TCC3 = 0xe, + TCA_PERF_SEL_REQ_TCC4 = 0xf, + TCA_PERF_SEL_REQ_TCC5 = 0x10, + TCA_PERF_SEL_REQ_TCC6 = 0x11, + TCA_PERF_SEL_REQ_TCC7 = 0x12, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x13, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x14, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x15, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x16, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x17, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x18, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x19, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x1a, + TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x1b, + TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x1c, + TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d, + TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x1e, + TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x1f, + TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x20, + TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x21, + TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x22, +} TCA_PERF_SEL; +typedef enum TA_TC_ADDR_MODES { + TA_TC_ADDR_MODE_DEFAULT = 0x0, + TA_TC_ADDR_MODE_COMP0 = 0x1, + TA_TC_ADDR_MODE_COMP1 = 0x2, + TA_TC_ADDR_MODE_COMP2 = 0x3, + TA_TC_ADDR_MODE_COMP3 = 0x4, + TA_TC_ADDR_MODE_UNALIGNED = 0x5, + TA_TC_ADDR_MODE_BORDER_COLOR = 0x6, +} TA_TC_ADDR_MODES; +typedef enum TA_PERFCOUNT_SEL { + TA_PERF_SEL_NULL = 0x0, + TA_PERF_SEL_sh_fifo_busy = 0x1, + TA_PERF_SEL_sh_fifo_cmd_busy = 0x2, + TA_PERF_SEL_sh_fifo_addr_busy = 0x3, + TA_PERF_SEL_sh_fifo_data_busy = 0x4, + TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x5, + TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x6, + TA_PERF_SEL_gradient_busy = 0x7, + TA_PERF_SEL_gradient_fifo_busy = 0x8, + TA_PERF_SEL_lod_busy = 0x9, + TA_PERF_SEL_lod_fifo_busy = 0xa, + TA_PERF_SEL_addresser_busy = 0xb, + TA_PERF_SEL_addresser_fifo_busy = 0xc, + TA_PERF_SEL_aligner_busy = 0xd, + TA_PERF_SEL_write_path_busy = 0xe, + TA_PERF_SEL_ta_busy = 0xf, + TA_PERF_SEL_sq_ta_cmd_cycles = 0x10, + TA_PERF_SEL_sp_ta_addr_cycles = 0x11, + TA_PERF_SEL_sp_ta_data_cycles = 0x12, + TA_PERF_SEL_ta_fa_data_state_cycles = 0x13, + TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x14, + TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x15, + TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16, + TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17, + TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18, + TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19, + TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a, + TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b, + TA_PERF_SEL_RESERVED_28 = 0x1c, + TA_PERF_SEL_RESERVED_29 = 0x1d, + TA_PERF_SEL_sh_fifo_addr_cycles = 0x1e, + TA_PERF_SEL_sh_fifo_data_cycles = 0x1f, + TA_PERF_SEL_total_wavefronts = 0x20, + TA_PERF_SEL_gradient_cycles = 0x21, + TA_PERF_SEL_walker_cycles = 0x22, + TA_PERF_SEL_aligner_cycles = 0x23, + TA_PERF_SEL_image_wavefronts = 0x24, + TA_PERF_SEL_image_read_wavefronts = 0x25, + TA_PERF_SEL_image_write_wavefronts = 0x26, + TA_PERF_SEL_image_atomic_wavefronts = 0x27, + TA_PERF_SEL_image_total_cycles = 0x28, + TA_PERF_SEL_RESERVED_41 = 0x29, + TA_PERF_SEL_RESERVED_42 = 0x2a, + TA_PERF_SEL_RESERVED_43 = 0x2b, + TA_PERF_SEL_buffer_wavefronts = 0x2c, + TA_PERF_SEL_buffer_read_wavefronts = 0x2d, + TA_PERF_SEL_buffer_write_wavefronts = 0x2e, + TA_PERF_SEL_buffer_atomic_wavefronts = 0x2f, + TA_PERF_SEL_buffer_coalescable_wavefronts = 0x30, + TA_PERF_SEL_buffer_total_cycles = 0x31, + TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32, + TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33, + TA_PERF_SEL_buffer_coalesced_read_cycles = 0x34, + TA_PERF_SEL_buffer_coalesced_write_cycles = 0x35, + TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x36, + TA_PERF_SEL_addr_stalled_by_td_cycles = 0x37, + TA_PERF_SEL_data_stalled_by_tc_cycles = 0x38, + TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39, + TA_PERF_SEL_addresser_stalled_cycles = 0x3a, + TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b, + TA_PERF_SEL_aniso_stalled_cycles = 0x3c, + TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x3d, + TA_PERF_SEL_deriv_stalled_cycles = 0x3e, + TA_PERF_SEL_aniso_gt1_cycle_quads = 0x3f, + TA_PERF_SEL_color_1_cycle_pixels = 0x40, + TA_PERF_SEL_color_2_cycle_pixels = 0x41, + TA_PERF_SEL_color_3_cycle_pixels = 0x42, + TA_PERF_SEL_color_4_cycle_pixels = 0x43, + TA_PERF_SEL_mip_1_cycle_pixels = 0x44, + TA_PERF_SEL_mip_2_cycle_pixels = 0x45, + TA_PERF_SEL_vol_1_cycle_pixels = 0x46, + TA_PERF_SEL_vol_2_cycle_pixels = 0x47, + TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x48, + TA_PERF_SEL_mipmap_lod_0_samples = 0x49, + TA_PERF_SEL_mipmap_lod_1_samples = 0x4a, + TA_PERF_SEL_mipmap_lod_2_samples = 0x4b, + TA_PERF_SEL_mipmap_lod_3_samples = 0x4c, + TA_PERF_SEL_mipmap_lod_4_samples = 0x4d, + TA_PERF_SEL_mipmap_lod_5_samples = 0x4e, + TA_PERF_SEL_mipmap_lod_6_samples = 0x4f, + TA_PERF_SEL_mipmap_lod_7_samples = 0x50, + TA_PERF_SEL_mipmap_lod_8_samples = 0x51, + TA_PERF_SEL_mipmap_lod_9_samples = 0x52, + TA_PERF_SEL_mipmap_lod_10_samples = 0x53, + TA_PERF_SEL_mipmap_lod_11_samples = 0x54, + TA_PERF_SEL_mipmap_lod_12_samples = 0x55, + TA_PERF_SEL_mipmap_lod_13_samples = 0x56, + TA_PERF_SEL_mipmap_lod_14_samples = 0x57, + TA_PERF_SEL_mipmap_invalid_samples = 0x58, + TA_PERF_SEL_aniso_1_cycle_quads = 0x59, + TA_PERF_SEL_aniso_2_cycle_quads = 0x5a, + TA_PERF_SEL_aniso_4_cycle_quads = 0x5b, + TA_PERF_SEL_aniso_6_cycle_quads = 0x5c, + TA_PERF_SEL_aniso_8_cycle_quads = 0x5d, + TA_PERF_SEL_aniso_10_cycle_quads = 0x5e, + TA_PERF_SEL_aniso_12_cycle_quads = 0x5f, + TA_PERF_SEL_aniso_14_cycle_quads = 0x60, + TA_PERF_SEL_aniso_16_cycle_quads = 0x61, + TA_PERF_SEL_write_path_input_cycles = 0x62, + TA_PERF_SEL_write_path_output_cycles = 0x63, + TA_PERF_SEL_flat_wavefronts = 0x64, + TA_PERF_SEL_flat_read_wavefronts = 0x65, + TA_PERF_SEL_flat_write_wavefronts = 0x66, + TA_PERF_SEL_flat_atomic_wavefronts = 0x67, + TA_PERF_SEL_flat_coalesceable_wavefronts = 0x68, + TA_PERF_SEL_reg_sclk_vld = 0x69, + TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6a, + TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x6b, + TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x6c, + TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x6d, + TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x6e, + TA_PERF_SEL_xnack_on_phase0 = 0x6f, + TA_PERF_SEL_xnack_on_phase1 = 0x70, + TA_PERF_SEL_xnack_on_phase2 = 0x71, + TA_PERF_SEL_xnack_on_phase3 = 0x72, + TA_PERF_SEL_first_xnack_on_phase0 = 0x73, + TA_PERF_SEL_first_xnack_on_phase1 = 0x74, + TA_PERF_SEL_first_xnack_on_phase2 = 0x75, + TA_PERF_SEL_first_xnack_on_phase3 = 0x76, +} TA_PERFCOUNT_SEL; +typedef enum TD_PERFCOUNT_SEL { + TD_PERF_SEL_none = 0x0, + TD_PERF_SEL_td_busy = 0x1, + TD_PERF_SEL_input_busy = 0x2, + TD_PERF_SEL_output_busy = 0x3, + TD_PERF_SEL_lerp_busy = 0x4, + TD_PERF_SEL_reg_sclk_vld = 0x5, + TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6, + TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x7, + TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x8, + TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x9, + TD_PERF_SEL_tc_td_fifo_full = 0xa, + TD_PERF_SEL_constant_state_full = 0xb, + TD_PERF_SEL_sample_state_full = 0xc, + TD_PERF_SEL_output_fifo_full = 0xd, + TD_PERF_SEL_RESERVED_14 = 0xe, + TD_PERF_SEL_tc_stall = 0xf, + TD_PERF_SEL_pc_stall = 0x10, + TD_PERF_SEL_gds_stall = 0x11, + TD_PERF_SEL_RESERVED_18 = 0x12, + TD_PERF_SEL_RESERVED_19 = 0x13, + TD_PERF_SEL_gather4_wavefront = 0x14, + TD_PERF_SEL_sample_c_wavefront = 0x15, + TD_PERF_SEL_load_wavefront = 0x16, + TD_PERF_SEL_atomic_wavefront = 0x17, + TD_PERF_SEL_store_wavefront = 0x18, + TD_PERF_SEL_ldfptr_wavefront = 0x19, + TD_PERF_SEL_RESERVED_26 = 0x1a, + TD_PERF_SEL_RESERVED_27 = 0x1b, + TD_PERF_SEL_d16_en_wavefront = 0x1c, + TD_PERF_SEL_bicubic_filter_wavefront = 0x1d, + TD_PERF_SEL_bypass_filter_wavefront = 0x1e, + TD_PERF_SEL_min_max_filter_wavefront = 0x1f, + TD_PERF_SEL_coalescable_wavefront = 0x20, + TD_PERF_SEL_coalesced_phase = 0x21, + TD_PERF_SEL_four_phase_wavefront = 0x22, + TD_PERF_SEL_eight_phase_wavefront = 0x23, + TD_PERF_SEL_sixteen_phase_wavefront = 0x24, + TD_PERF_SEL_four_phase_forward_wavefront = 0x25, + TD_PERF_SEL_write_ack_wavefront = 0x26, + TD_PERF_SEL_RESERVED_39 = 0x27, + TD_PERF_SEL_user_defined_border = 0x28, + TD_PERF_SEL_white_border = 0x29, + TD_PERF_SEL_opaque_black_border = 0x2a, + TD_PERF_SEL_RESERVED_43 = 0x2b, + TD_PERF_SEL_RESERVED_44 = 0x2c, + TD_PERF_SEL_nack = 0x2d, + TD_PERF_SEL_td_sp_traffic = 0x2e, + TD_PERF_SEL_consume_gds_traffic = 0x2f, + TD_PERF_SEL_addresscmd_poison = 0x30, + TD_PERF_SEL_data_poison = 0x31, + TD_PERF_SEL_start_cycle_0 = 0x32, + TD_PERF_SEL_start_cycle_1 = 0x33, + TD_PERF_SEL_start_cycle_2 = 0x34, + TD_PERF_SEL_start_cycle_3 = 0x35, + TD_PERF_SEL_null_cycle_output = 0x36, +} TD_PERFCOUNT_SEL; +typedef enum TCP_PERFCOUNT_SELECT { + TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x0, + TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x1, + TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2, + TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x3, + TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x4, + TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x5, + TCP_PERF_SEL_LOD_STALL_CYCLES = 0x6, + TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x7, + TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x8, + TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x9, + TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0xa, + TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0xb, + TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0xc, + TCP_PERF_SEL_TCR_RDRET_STALL = 0xd, + TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0xe, + TCP_PERF_SEL_HOLE_READ_STALL = 0xf, + TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x10, + TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x11, + TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x12, + TCP_PERF_SEL_TCP_LATENCY = 0x13, + TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x14, + TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x15, + TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x16, + TCP_PERF_SEL_TCC_READ_REQ = 0x17, + TCP_PERF_SEL_TCC_WRITE_REQ = 0x18, + TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x19, + TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x1a, + TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x1b, + TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x1c, + TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d, + TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x1e, + TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x1f, + TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x20, + TCP_PERF_SEL_TOTAL_WBINVL1 = 0x21, + TCP_PERF_SEL_IMG_READ_FMT_1 = 0x22, + TCP_PERF_SEL_IMG_READ_FMT_8 = 0x23, + TCP_PERF_SEL_IMG_READ_FMT_16 = 0x24, + TCP_PERF_SEL_IMG_READ_FMT_32 = 0x25, + TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x26, + TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x27, + TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x28, + TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x29, + TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x2a, + TCP_PERF_SEL_IMG_READ_FMT_96 = 0x2b, + TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x2c, + TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x2d, + TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x2e, + TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x2f, + TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x30, + TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x31, + TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x32, + TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x33, + TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x34, + TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x35, + TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x36, + TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x37, + TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x38, + TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x39, + TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x3a, + TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x3b, + TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x3c, + TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x3d, + TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x3e, + TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x3f, + TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x40, + TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x41, + TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x42, + TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x43, + TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x44, + TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x45, + TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x46, + TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x47, + TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x48, + TCP_PERF_SEL_BUF_READ_FMT_8 = 0x49, + TCP_PERF_SEL_BUF_READ_FMT_16 = 0x4a, + TCP_PERF_SEL_BUF_READ_FMT_32 = 0x4b, + TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x4c, + TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x4d, + TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x4e, + TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x4f, + TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x50, + TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x51, + TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x52, + TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x53, + TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x54, + TCP_PERF_SEL_ARR_1D_THIN1 = 0x55, + TCP_PERF_SEL_ARR_1D_THICK = 0x56, + TCP_PERF_SEL_ARR_2D_THIN1 = 0x57, + TCP_PERF_SEL_ARR_2D_THICK = 0x58, + TCP_PERF_SEL_ARR_2D_XTHICK = 0x59, + TCP_PERF_SEL_ARR_3D_THIN1 = 0x5a, + TCP_PERF_SEL_ARR_3D_THICK = 0x5b, + TCP_PERF_SEL_ARR_3D_XTHICK = 0x5c, + TCP_PERF_SEL_DIM_1D = 0x5d, + TCP_PERF_SEL_DIM_2D = 0x5e, + TCP_PERF_SEL_DIM_3D = 0x5f, + TCP_PERF_SEL_DIM_1D_ARRAY = 0x60, + TCP_PERF_SEL_DIM_2D_ARRAY = 0x61, + TCP_PERF_SEL_DIM_2D_MSAA = 0x62, + TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x63, + TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x64, + TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x65, + TCP_PERF_SEL_TA_TCP_STATE_READ = 0x66, + TCP_PERF_SEL_TAGRAM0_REQ = 0x67, + TCP_PERF_SEL_TAGRAM1_REQ = 0x68, + TCP_PERF_SEL_TAGRAM2_REQ = 0x69, + TCP_PERF_SEL_TAGRAM3_REQ = 0x6a, + TCP_PERF_SEL_GATE_EN1 = 0x6b, + TCP_PERF_SEL_GATE_EN2 = 0x6c, + TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x6d, + TCP_PERF_SEL_TCC_REQ = 0x6e, + TCP_PERF_SEL_TCC_NON_READ_REQ = 0x6f, + TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x70, + TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x71, + TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x72, + TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x73, + TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x74, + TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x75, + TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x76, + TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x77, + TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x78, + TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x79, + TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x7a, + TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x7b, + TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x7c, + TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x7d, + TCP_PERF_SEL_TOTAL_ACCESSES = 0x7e, + TCP_PERF_SEL_TOTAL_READ = 0x7f, + TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x80, + TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x81, + TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x82, + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x83, + TCP_PERF_SEL_TOTAL_NON_READ = 0x84, + TCP_PERF_SEL_TOTAL_WRITE = 0x85, + TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x86, + TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x87, + TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x88, + TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x89, + TCP_PERF_SEL_DISPLAY_MICROTILING = 0x8a, + TCP_PERF_SEL_THIN_MICROTILING = 0x8b, + TCP_PERF_SEL_DEPTH_MICROTILING = 0x8c, + TCP_PERF_SEL_ARR_PRT_THIN1 = 0x8d, + TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x8e, + TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x8f, + TCP_PERF_SEL_ARR_PRT_THICK = 0x90, + TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x91, + TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x92, + TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x93, + TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x94, + TCP_PERF_SEL_UNALIGNED = 0x95, + TCP_PERF_SEL_ROTATED_MICROTILING = 0x96, + TCP_PERF_SEL_THICK_MICROTILING = 0x97, + TCP_PERF_SEL_ATC = 0x98, + TCP_PERF_SEL_POWER_STALL = 0x99, + TCP_PERF_SEL_RESERVED_154 = 0x9a, + TCP_PERF_SEL_TCC_LRU_REQ = 0x9b, + TCP_PERF_SEL_TCC_STREAM_REQ = 0x9c, + TCP_PERF_SEL_TCC_NC_READ_REQ = 0x9d, + TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x9e, + TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x9f, + TCP_PERF_SEL_TCC_UC_READ_REQ = 0xa0, + TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0xa1, + TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0xa2, + TCP_PERF_SEL_TCC_CC_READ_REQ = 0xa3, + TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0xa4, + TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0xa5, + TCP_PERF_SEL_TCC_DCC_REQ = 0xa6, + TCP_PERF_SEL_TCC_PHYSICAL_REQ = 0xa7, + TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0xa8, + TCP_PERF_SEL_VOLATILE = 0xa9, + TCP_PERF_SEL_TC_TA_XNACK_STALL = 0xaa, + TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL = 0xab, + TCP_PERF_SEL_SHOOTDOWN = 0xac, + TCP_PERF_SEL_GATCL1_TRANSLATION_MISS = 0xad, + TCP_PERF_SEL_GATCL1_PERMISSION_MISS = 0xae, + TCP_PERF_SEL_GATCL1_REQUEST = 0xaf, + TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX = 0xb0, + TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT = 0xb1, + TCP_PERF_SEL_GATCL1_LFIFO_FULL = 0xb2, + TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES = 0xb3, + TCP_PERF_SEL_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0xb4, + TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT = 0xb5, + TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL = 0xb6, +} TCP_PERFCOUNT_SELECT; +typedef enum TCP_CACHE_POLICIES { + TCP_CACHE_POLICY_MISS_LRU = 0x0, + TCP_CACHE_POLICY_MISS_EVICT = 0x1, + TCP_CACHE_POLICY_HIT_LRU = 0x2, + TCP_CACHE_POLICY_HIT_EVICT = 0x3, +} TCP_CACHE_POLICIES; +typedef enum TCP_CACHE_STORE_POLICIES { + TCP_CACHE_STORE_POLICY_WT_LRU = 0x0, + TCP_CACHE_STORE_POLICY_WT_EVICT = 0x1, +} TCP_CACHE_STORE_POLICIES; +typedef enum TCP_WATCH_MODES { + TCP_WATCH_MODE_READ = 0x0, + TCP_WATCH_MODE_NONREAD = 0x1, + TCP_WATCH_MODE_ATOMIC = 0x2, + TCP_WATCH_MODE_ALL = 0x3, +} TCP_WATCH_MODES; +typedef enum TCP_DSM_DATA_SEL { + TCP_DSM_DISABLE = 0x0, + TCP_DSM_SEL0 = 0x1, + TCP_DSM_SEL1 = 0x2, + TCP_DSM_SEL_BOTH = 0x3, +} TCP_DSM_DATA_SEL; +typedef enum TCP_DSM_SINGLE_WRITE { + TCP_DSM_SINGLE_WRITE_EN = 0x1, +} TCP_DSM_SINGLE_WRITE; +typedef enum VGT_OUT_PRIM_TYPE { + VGT_OUT_POINT = 0x0, + VGT_OUT_LINE = 0x1, + VGT_OUT_TRI = 0x2, + VGT_OUT_RECT_V0 = 0x3, + VGT_OUT_RECT_V1 = 0x4, + VGT_OUT_RECT_V2 = 0x5, + VGT_OUT_RECT_V3 = 0x6, + VGT_OUT_RESERVED = 0x7, + VGT_TE_QUAD = 0x8, + VGT_TE_PRIM_INDEX_LINE = 0x9, + VGT_TE_PRIM_INDEX_TRI = 0xa, + VGT_TE_PRIM_INDEX_QUAD = 0xb, + VGT_OUT_LINE_ADJ = 0xc, + VGT_OUT_TRI_ADJ = 0xd, + VGT_OUT_PATCH = 0xe, +} VGT_OUT_PRIM_TYPE; +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0x0, + DI_PT_POINTLIST = 0x1, + DI_PT_LINELIST = 0x2, + DI_PT_LINESTRIP = 0x3, + DI_PT_TRILIST = 0x4, + DI_PT_TRIFAN = 0x5, + DI_PT_TRISTRIP = 0x6, + DI_PT_UNUSED_0 = 0x7, + DI_PT_UNUSED_1 = 0x8, + DI_PT_PATCH = 0x9, + DI_PT_LINELIST_ADJ = 0xa, + DI_PT_LINESTRIP_ADJ = 0xb, + DI_PT_TRILIST_ADJ = 0xc, + DI_PT_TRISTRIP_ADJ = 0xd, + DI_PT_UNUSED_3 = 0xe, + DI_PT_UNUSED_4 = 0xf, + DI_PT_TRI_WITH_WFLAGS = 0x10, + DI_PT_RECTLIST = 0x11, + DI_PT_LINELOOP = 0x12, + DI_PT_QUADLIST = 0x13, + DI_PT_QUADSTRIP = 0x14, + DI_PT_POLYGON = 0x15, + DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, + DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, + DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, + DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, + DI_PT_2D_FILL_RECT_LIST = 0x1a, + DI_PT_2D_LINE_STRIP = 0x1b, + DI_PT_2D_TRI_STRIP = 0x1c, +} VGT_DI_PRIM_TYPE; +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0x0, + DI_SRC_SEL_IMMEDIATE = 0x1, + DI_SRC_SEL_AUTO_INDEX = 0x2, + DI_SRC_SEL_RESERVED = 0x3, +} VGT_DI_SOURCE_SELECT; +typedef enum VGT_DI_MAJOR_MODE_SELECT { + DI_MAJOR_MODE_0 = 0x0, + DI_MAJOR_MODE_1 = 0x1, +} VGT_DI_MAJOR_MODE_SELECT; +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0x0, + DI_INDEX_SIZE_32_BIT = 0x1, + DI_INDEX_SIZE_8_BIT = 0x2, +} VGT_DI_INDEX_SIZE; +typedef enum VGT_EVENT_TYPE { + Reserved_0x00 = 0x0, + SAMPLE_STREAMOUTSTATS1 = 0x1, + SAMPLE_STREAMOUTSTATS2 = 0x2, + SAMPLE_STREAMOUTSTATS3 = 0x3, + CACHE_FLUSH_TS = 0x4, + CONTEXT_DONE = 0x5, + CACHE_FLUSH = 0x6, + CS_PARTIAL_FLUSH = 0x7, + VGT_STREAMOUT_SYNC = 0x8, + Reserved_0x09 = 0x9, + VGT_STREAMOUT_RESET = 0xa, + END_OF_PIPE_INCR_DE = 0xb, + END_OF_PIPE_IB_END = 0xc, + RST_PIX_CNT = 0xd, + Reserved_0x0E = 0xe, + VS_PARTIAL_FLUSH = 0xf, + PS_PARTIAL_FLUSH = 0x10, + FLUSH_HS_OUTPUT = 0x11, + FLUSH_LS_OUTPUT = 0x12, + Reserved_0x13 = 0x13, + CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, + ZPASS_DONE = 0x15, + CACHE_FLUSH_AND_INV_EVENT = 0x16, + PERFCOUNTER_START = 0x17, + PERFCOUNTER_STOP = 0x18, + PIPELINESTAT_START = 0x19, + PIPELINESTAT_STOP = 0x1a, + PERFCOUNTER_SAMPLE = 0x1b, + FLUSH_ES_OUTPUT = 0x1c, + FLUSH_GS_OUTPUT = 0x1d, + SAMPLE_PIPELINESTAT = 0x1e, + SO_VGTSTREAMOUT_FLUSH = 0x1f, + SAMPLE_STREAMOUTSTATS = 0x20, + RESET_VTX_CNT = 0x21, + BLOCK_CONTEXT_DONE = 0x22, + CS_CONTEXT_DONE = 0x23, + VGT_FLUSH = 0x24, + TGID_ROLLOVER = 0x25, + SQ_NON_EVENT = 0x26, + SC_SEND_DB_VPZ = 0x27, + BOTTOM_OF_PIPE_TS = 0x28, + FLUSH_SX_TS = 0x29, + DB_CACHE_FLUSH_AND_INV = 0x2a, + FLUSH_AND_INV_DB_DATA_TS = 0x2b, + FLUSH_AND_INV_DB_META = 0x2c, + FLUSH_AND_INV_CB_DATA_TS = 0x2d, + FLUSH_AND_INV_CB_META = 0x2e, + CS_DONE = 0x2f, + PS_DONE = 0x30, + FLUSH_AND_INV_CB_PIXEL_DATA = 0x31, + SX_CB_RAT_ACK_REQUEST = 0x32, + THREAD_TRACE_START = 0x33, + THREAD_TRACE_STOP = 0x34, + THREAD_TRACE_MARKER = 0x35, + THREAD_TRACE_FLUSH = 0x36, + THREAD_TRACE_FINISH = 0x37, + PIXEL_PIPE_STAT_CONTROL = 0x38, + PIXEL_PIPE_STAT_DUMP = 0x39, + PIXEL_PIPE_STAT_RESET = 0x3a, + CONTEXT_SUSPEND = 0x3b, + OFFCHIP_HS_DEALLOC = 0x3c, +} VGT_EVENT_TYPE; +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0x0, + VGT_DMA_SWAP_16_BIT = 0x1, + VGT_DMA_SWAP_32_BIT = 0x2, + VGT_DMA_SWAP_WORD = 0x3, +} VGT_DMA_SWAP_MODE; +typedef enum VGT_INDEX_TYPE_MODE { + VGT_INDEX_16 = 0x0, + VGT_INDEX_32 = 0x1, + VGT_INDEX_8 = 0x2, +} VGT_INDEX_TYPE_MODE; +typedef enum VGT_DMA_BUF_TYPE { + VGT_DMA_BUF_MEM = 0x0, + VGT_DMA_BUF_RING = 0x1, + VGT_DMA_BUF_SETUP = 0x2, + VGT_DMA_PTR_UPDATE = 0x3, +} VGT_DMA_BUF_TYPE; +typedef enum VGT_OUTPATH_SELECT { + VGT_OUTPATH_VTX_REUSE = 0x0, + VGT_OUTPATH_TESS_EN = 0x1, + VGT_OUTPATH_PASSTHRU = 0x2, + VGT_OUTPATH_GS_BLOCK = 0x3, + VGT_OUTPATH_HS_BLOCK = 0x4, +} VGT_OUTPATH_SELECT; +typedef enum VGT_GRP_PRIM_TYPE { + VGT_GRP_3D_POINT = 0x0, + VGT_GRP_3D_LINE = 0x1, + VGT_GRP_3D_TRI = 0x2, + VGT_GRP_3D_RECT = 0x3, + VGT_GRP_3D_QUAD = 0x4, + VGT_GRP_2D_COPY_RECT_V0 = 0x5, + VGT_GRP_2D_COPY_RECT_V1 = 0x6, + VGT_GRP_2D_COPY_RECT_V2 = 0x7, + VGT_GRP_2D_COPY_RECT_V3 = 0x8, + VGT_GRP_2D_FILL_RECT = 0x9, + VGT_GRP_2D_LINE = 0xa, + VGT_GRP_2D_TRI = 0xb, + VGT_GRP_PRIM_INDEX_LINE = 0xc, + VGT_GRP_PRIM_INDEX_TRI = 0xd, + VGT_GRP_PRIM_INDEX_QUAD = 0xe, + VGT_GRP_3D_LINE_ADJ = 0xf, + VGT_GRP_3D_TRI_ADJ = 0x10, + VGT_GRP_3D_PATCH = 0x11, +} VGT_GRP_PRIM_TYPE; +typedef enum VGT_GRP_PRIM_ORDER { + VGT_GRP_LIST = 0x0, + VGT_GRP_STRIP = 0x1, + VGT_GRP_FAN = 0x2, + VGT_GRP_LOOP = 0x3, + VGT_GRP_POLYGON = 0x4, +} VGT_GRP_PRIM_ORDER; +typedef enum VGT_GROUP_CONV_SEL { + VGT_GRP_INDEX_16 = 0x0, + VGT_GRP_INDEX_32 = 0x1, + VGT_GRP_UINT_16 = 0x2, + VGT_GRP_UINT_32 = 0x3, + VGT_GRP_SINT_16 = 0x4, + VGT_GRP_SINT_32 = 0x5, + VGT_GRP_FLOAT_32 = 0x6, + VGT_GRP_AUTO_PRIM = 0x7, + VGT_GRP_FIX_1_23_TO_FLOAT = 0x8, +} VGT_GROUP_CONV_SEL; +typedef enum VGT_GS_MODE_TYPE { + GS_OFF = 0x0, + GS_SCENARIO_A = 0x1, + GS_SCENARIO_B = 0x2, + GS_SCENARIO_G = 0x3, + GS_SCENARIO_C = 0x4, + SPRITE_EN = 0x5, +} VGT_GS_MODE_TYPE; +typedef enum VGT_GS_CUT_MODE { + GS_CUT_1024 = 0x0, + GS_CUT_512 = 0x1, + GS_CUT_256 = 0x2, + GS_CUT_128 = 0x3, +} VGT_GS_CUT_MODE; +typedef enum VGT_GS_OUTPRIM_TYPE { + POINTLIST = 0x0, + LINESTRIP = 0x1, + TRISTRIP = 0x2, +} VGT_GS_OUTPRIM_TYPE; +typedef enum VGT_CACHE_INVALID_MODE { + VC_ONLY = 0x0, + TC_ONLY = 0x1, + VC_AND_TC = 0x2, +} VGT_CACHE_INVALID_MODE; +typedef enum VGT_TESS_TYPE { + TESS_ISOLINE = 0x0, + TESS_TRIANGLE = 0x1, + TESS_QUAD = 0x2, +} VGT_TESS_TYPE; +typedef enum VGT_TESS_PARTITION { + PART_INTEGER = 0x0, + PART_POW2 = 0x1, + PART_FRAC_ODD = 0x2, + PART_FRAC_EVEN = 0x3, +} VGT_TESS_PARTITION; +typedef enum VGT_TESS_TOPOLOGY { + OUTPUT_POINT = 0x0, + OUTPUT_LINE = 0x1, + OUTPUT_TRIANGLE_CW = 0x2, + OUTPUT_TRIANGLE_CCW = 0x3, +} VGT_TESS_TOPOLOGY; +typedef enum VGT_RDREQ_POLICY { + VGT_POLICY_LRU = 0x0, + VGT_POLICY_STREAM = 0x1, +} VGT_RDREQ_POLICY; +typedef enum VGT_DIST_MODE { + NO_DIST = 0x0, + PATCHES = 0x1, + DONUTS = 0x2, +} VGT_DIST_MODE; +typedef enum VGT_STAGES_LS_EN { + LS_STAGE_OFF = 0x0, + LS_STAGE_ON = 0x1, + CS_STAGE_ON = 0x2, + RESERVED_LS = 0x3, +} VGT_STAGES_LS_EN; +typedef enum VGT_STAGES_HS_EN { + HS_STAGE_OFF = 0x0, + HS_STAGE_ON = 0x1, +} VGT_STAGES_HS_EN; +typedef enum VGT_STAGES_ES_EN { + ES_STAGE_OFF = 0x0, + ES_STAGE_DS = 0x1, + ES_STAGE_REAL = 0x2, + RESERVED_ES = 0x3, +} VGT_STAGES_ES_EN; +typedef enum VGT_STAGES_GS_EN { + GS_STAGE_OFF = 0x0, + GS_STAGE_ON = 0x1, +} VGT_STAGES_GS_EN; +typedef enum VGT_STAGES_VS_EN { + VS_STAGE_REAL = 0x0, + VS_STAGE_DS = 0x1, + VS_STAGE_COPY_SHADER = 0x2, + RESERVED_VS = 0x3, +} VGT_STAGES_VS_EN; +typedef enum VGT_PERFCOUNT_SELECT { + vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x0, + vgt_perf_VGT_SPI_ESVERT_VALID = 0x1, + vgt_perf_VGT_SPI_ESVERT_EOV = 0x2, + vgt_perf_VGT_SPI_ESVERT_STALLED = 0x3, + vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x4, + vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x5, + vgt_perf_VGT_SPI_ESVERT_STATIC = 0x6, + vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x7, + vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x8, + vgt_perf_VGT_SPI_GSPRIM_VALID = 0x9, + vgt_perf_VGT_SPI_GSPRIM_EOV = 0xa, + vgt_perf_VGT_SPI_GSPRIM_CONT = 0xb, + vgt_perf_VGT_SPI_GSPRIM_STALLED = 0xc, + vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0xd, + vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0xe, + vgt_perf_VGT_SPI_GSPRIM_STATIC = 0xf, + vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x10, + vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x11, + vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x12, + vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x13, + vgt_perf_VGT_SPI_VSVERT_SEND = 0x14, + vgt_perf_VGT_SPI_VSVERT_EOV = 0x15, + vgt_perf_VGT_SPI_VSVERT_STALLED = 0x16, + vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x17, + vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x18, + vgt_perf_VGT_SPI_VSVERT_STATIC = 0x19, + vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x1a, + vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x1b, + vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x1c, + vgt_perf_VGT_PA_CLIPV_SEND = 0x1d, + vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x1e, + vgt_perf_VGT_PA_CLIPV_STALLED = 0x1f, + vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x20, + vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x21, + vgt_perf_VGT_PA_CLIPV_STATIC = 0x22, + vgt_perf_VGT_PA_CLIPP_SEND = 0x23, + vgt_perf_VGT_PA_CLIPP_EOP = 0x24, + vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x25, + vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x26, + vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x27, + vgt_perf_VGT_PA_CLIPP_STALLED = 0x28, + vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x29, + vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x2a, + vgt_perf_VGT_PA_CLIPP_STATIC = 0x2b, + vgt_perf_VGT_PA_CLIPS_SEND = 0x2c, + vgt_perf_VGT_PA_CLIPS_STALLED = 0x2d, + vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x2e, + vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x2f, + vgt_perf_VGT_PA_CLIPS_STATIC = 0x30, + vgt_perf_vsvert_ds_send = 0x31, + vgt_perf_vsvert_api_send = 0x32, + vgt_perf_hs_tif_stall = 0x33, + vgt_perf_hs_input_stall = 0x34, + vgt_perf_hs_interface_stall = 0x35, + vgt_perf_hs_tfm_stall = 0x36, + vgt_perf_te11_starved = 0x37, + vgt_perf_gs_event_stall = 0x38, + vgt_perf_vgt_pa_clipp_send_not_event = 0x39, + vgt_perf_vgt_pa_clipp_valid_prim = 0x3a, + vgt_perf_reused_es_indices = 0x3b, + vgt_perf_vs_cache_hits = 0x3c, + vgt_perf_gs_cache_hits = 0x3d, + vgt_perf_ds_cache_hits = 0x3e, + vgt_perf_total_cache_hits = 0x3f, + vgt_perf_vgt_busy = 0x40, + vgt_perf_vgt_gs_busy = 0x41, + vgt_perf_esvert_stalled_es_tbl = 0x42, + vgt_perf_esvert_stalled_gs_tbl = 0x43, + vgt_perf_esvert_stalled_gs_event = 0x44, + vgt_perf_esvert_stalled_gsprim = 0x45, + vgt_perf_gsprim_stalled_es_tbl = 0x46, + vgt_perf_gsprim_stalled_gs_tbl = 0x47, + vgt_perf_gsprim_stalled_gs_event = 0x48, + vgt_perf_gsprim_stalled_esvert = 0x49, + vgt_perf_esthread_stalled_es_rb_full = 0x4a, + vgt_perf_esthread_stalled_spi_bp = 0x4b, + vgt_perf_counters_avail_stalled = 0x4c, + vgt_perf_gs_rb_space_avail_stalled = 0x4d, + vgt_perf_gs_issue_rtr_stalled = 0x4e, + vgt_perf_gsthread_stalled = 0x4f, + vgt_perf_strmout_stalled = 0x50, + vgt_perf_wait_for_es_done_stalled = 0x51, + vgt_perf_cm_stalled_by_gog = 0x52, + vgt_perf_cm_reading_stalled = 0x53, + vgt_perf_cm_stalled_by_gsfetch_done = 0x54, + vgt_perf_gog_vs_tbl_stalled = 0x55, + vgt_perf_gog_out_indx_stalled = 0x56, + vgt_perf_gog_out_prim_stalled = 0x57, + vgt_perf_waveid_stalled = 0x58, + vgt_perf_gog_busy = 0x59, + vgt_perf_reused_vs_indices = 0x5a, + vgt_perf_sclk_reg_vld_event = 0x5b, + vgt_perf_vs_conflicting_indices = 0x5c, + vgt_perf_sclk_core_vld_event = 0x5d, + vgt_perf_hswave_stalled = 0x5e, + vgt_perf_sclk_gs_vld_event = 0x5f, + vgt_perf_VGT_SPI_LSVERT_VALID = 0x60, + vgt_perf_VGT_SPI_LSVERT_EOV = 0x61, + vgt_perf_VGT_SPI_LSVERT_STALLED = 0x62, + vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x63, + vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x64, + vgt_perf_VGT_SPI_LSVERT_STATIC = 0x65, + vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x66, + vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x67, + vgt_perf_VGT_SPI_LSWAVE_SEND = 0x68, + vgt_perf_VGT_SPI_HSVERT_VALID = 0x69, + vgt_perf_VGT_SPI_HSVERT_EOV = 0x6a, + vgt_perf_VGT_SPI_HSVERT_STALLED = 0x6b, + vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x6c, + vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x6d, + vgt_perf_VGT_SPI_HSVERT_STATIC = 0x6e, + vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x6f, + vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x70, + vgt_perf_VGT_SPI_HSWAVE_SEND = 0x71, + vgt_perf_ds_prims = 0x72, + vgt_perf_ls_thread_groups = 0x73, + vgt_perf_hs_thread_groups = 0x74, + vgt_perf_es_thread_groups = 0x75, + vgt_perf_vs_thread_groups = 0x76, + vgt_perf_ls_done_latency = 0x77, + vgt_perf_hs_done_latency = 0x78, + vgt_perf_es_done_latency = 0x79, + vgt_perf_gs_done_latency = 0x7a, + vgt_perf_vgt_hs_busy = 0x7b, + vgt_perf_vgt_te11_busy = 0x7c, + vgt_perf_ls_flush = 0x7d, + vgt_perf_hs_flush = 0x7e, + vgt_perf_es_flush = 0x7f, + vgt_perf_vgt_pa_clipp_eopg = 0x80, + vgt_perf_ls_done = 0x81, + vgt_perf_hs_done = 0x82, + vgt_perf_es_done = 0x83, + vgt_perf_gs_done = 0x84, + vgt_perf_vsfetch_done = 0x85, + vgt_perf_gs_done_received = 0x86, + vgt_perf_es_ring_high_water_mark = 0x87, + vgt_perf_gs_ring_high_water_mark = 0x88, + vgt_perf_vs_table_high_water_mark = 0x89, + vgt_perf_hs_tgs_active_high_water_mark = 0x8a, + vgt_perf_pa_clipp_dealloc = 0x8b, + vgt_perf_cut_mem_flush_stalled = 0x8c, + vgt_perf_vsvert_work_received = 0x8d, + vgt_perf_vgt_pa_clipp_starved_after_work = 0x8e, + vgt_perf_te11_con_starved_after_work = 0x8f, + vgt_perf_hs_waiting_on_ls_done_stall = 0x90, + vgt_spi_vsvert_valid = 0x91, +} VGT_PERFCOUNT_SELECT; +typedef enum IA_PERFCOUNT_SELECT { + ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x0, + ia_perf_dma_data_fifo_full = 0x1, + ia_perf_RESERVED1 = 0x2, + ia_perf_RESERVED2 = 0x3, + ia_perf_RESERVED3 = 0x4, + ia_perf_RESERVED4 = 0x5, + ia_perf_RESERVED5 = 0x6, + ia_perf_MC_LAT_BIN_0 = 0x7, + ia_perf_MC_LAT_BIN_1 = 0x8, + ia_perf_MC_LAT_BIN_2 = 0x9, + ia_perf_MC_LAT_BIN_3 = 0xa, + ia_perf_MC_LAT_BIN_4 = 0xb, + ia_perf_MC_LAT_BIN_5 = 0xc, + ia_perf_MC_LAT_BIN_6 = 0xd, + ia_perf_MC_LAT_BIN_7 = 0xe, + ia_perf_ia_busy = 0xf, + ia_perf_ia_sclk_reg_vld_event = 0x10, + ia_perf_RESERVED6 = 0x11, + ia_perf_ia_sclk_core_vld_event = 0x12, + ia_perf_RESERVED7 = 0x13, + ia_perf_ia_dma_return = 0x14, + ia_perf_ia_stalled = 0x15, + ia_perf_shift_starved_pipe0_event = 0x16, + ia_perf_shift_starved_pipe1_event = 0x17, +} IA_PERFCOUNT_SELECT; +typedef enum WD_PERFCOUNT_SELECT { + wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x0, + wd_perf_RBIU_DR_FIFO_STARVED = 0x1, + wd_perf_RBIU_DR_FIFO_STALLED = 0x2, + wd_perf_RBIU_DI_FIFO_STARVED = 0x3, + wd_perf_RBIU_DI_FIFO_STALLED = 0x4, + wd_perf_wd_busy = 0x5, + wd_perf_wd_sclk_reg_vld_event = 0x6, + wd_perf_wd_sclk_input_vld_event = 0x7, + wd_perf_wd_sclk_core_vld_event = 0x8, + wd_perf_wd_stalled = 0x9, + wd_perf_inside_tf_bin_0 = 0xa, + wd_perf_inside_tf_bin_1 = 0xb, + wd_perf_inside_tf_bin_2 = 0xc, + wd_perf_inside_tf_bin_3 = 0xd, + wd_perf_inside_tf_bin_4 = 0xe, + wd_perf_inside_tf_bin_5 = 0xf, + wd_perf_inside_tf_bin_6 = 0x10, + wd_perf_inside_tf_bin_7 = 0x11, + wd_perf_inside_tf_bin_8 = 0x12, + wd_perf_tfreq_lat_bin_0 = 0x13, + wd_perf_tfreq_lat_bin_1 = 0x14, + wd_perf_tfreq_lat_bin_2 = 0x15, + wd_perf_tfreq_lat_bin_3 = 0x16, + wd_perf_tfreq_lat_bin_4 = 0x17, + wd_perf_tfreq_lat_bin_5 = 0x18, + wd_perf_tfreq_lat_bin_6 = 0x19, + wd_perf_tfreq_lat_bin_7 = 0x1a, + wd_starved_on_hs_done = 0x1b, + wd_perf_se0_hs_done_latency = 0x1c, + wd_perf_se1_hs_done_latency = 0x1d, + wd_perf_se2_hs_done_latency = 0x1e, + wd_perf_se3_hs_done_latency = 0x1f, + wd_perf_hs_done_se0 = 0x20, + wd_perf_hs_done_se1 = 0x21, + wd_perf_hs_done_se2 = 0x22, + wd_perf_hs_done_se3 = 0x23, + wd_perf_null_patches = 0x24, +} WD_PERFCOUNT_SELECT; +typedef enum WD_IA_DRAW_TYPE { + WD_IA_DRAW_TYPE_DI_MM0 = 0x0, + WD_IA_DRAW_TYPE_DI_MM1 = 0x1, + WD_IA_DRAW_TYPE_EVENT_INIT = 0x2, + WD_IA_DRAW_TYPE_EVENT_ADDR = 0x3, + WD_IA_DRAW_TYPE_MIN_INDX = 0x4, + WD_IA_DRAW_TYPE_MAX_INDX = 0x5, + WD_IA_DRAW_TYPE_INDX_OFF = 0x6, + WD_IA_DRAW_TYPE_IMM_DATA = 0x7, +} WD_IA_DRAW_TYPE; +typedef enum WD_IA_DRAW_SOURCE { + WD_IA_DRAW_SOURCE_DMA = 0x0, + WD_IA_DRAW_SOURCE_IMMD = 0x1, + WD_IA_DRAW_SOURCE_AUTO = 0x2, + WD_IA_DRAW_SOURCE_OPAQ = 0x3, +} WD_IA_DRAW_SOURCE; +#define GSTHREADID_SIZE 0x2 +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_scf2 = 0x2, + DBG_CLIENT_BLKID_mcd5 = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_sx30 = 0x5, + DBG_CLIENT_BLKID_mcd2 = 0x6, + DBG_CLIENT_BLKID_bci1 = 0x7, + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, + DBG_CLIENT_BLKID_mcc0 = 0x9, + DBG_CLIENT_BLKID_uvdf_0 = 0xa, + DBG_CLIENT_BLKID_uvdf_1 = 0xb, + DBG_CLIENT_BLKID_uvdf_2 = 0xc, + DBG_CLIENT_BLKID_uvdi_0 = 0xd, + DBG_CLIENT_BLKID_bci0 = 0xe, + DBG_CLIENT_BLKID_vcec0_0 = 0xf, + DBG_CLIENT_BLKID_cb100 = 0x10, + DBG_CLIENT_BLKID_cb001 = 0x11, + DBG_CLIENT_BLKID_mcd4 = 0x12, + DBG_CLIENT_BLKID_tmonw00 = 0x13, + DBG_CLIENT_BLKID_cb101 = 0x14, + DBG_CLIENT_BLKID_sx10 = 0x15, + DBG_CLIENT_BLKID_cb301 = 0x16, + DBG_CLIENT_BLKID_tmonw01 = 0x17, + DBG_CLIENT_BLKID_vcea0_0 = 0x18, + DBG_CLIENT_BLKID_vcea0_1 = 0x19, + DBG_CLIENT_BLKID_vcea0_2 = 0x1a, + DBG_CLIENT_BLKID_vcea0_3 = 0x1b, + DBG_CLIENT_BLKID_scf1 = 0x1c, + DBG_CLIENT_BLKID_sx20 = 0x1d, + DBG_CLIENT_BLKID_spim1 = 0x1e, + DBG_CLIENT_BLKID_pa10 = 0x1f, + DBG_CLIENT_BLKID_pa00 = 0x20, + DBG_CLIENT_BLKID_gmcon = 0x21, + DBG_CLIENT_BLKID_mcb = 0x22, + DBG_CLIENT_BLKID_vgt0 = 0x23, + DBG_CLIENT_BLKID_pc0 = 0x24, + DBG_CLIENT_BLKID_bci2 = 0x25, + DBG_CLIENT_BLKID_uvdb_0 = 0x26, + DBG_CLIENT_BLKID_spim3 = 0x27, + DBG_CLIENT_BLKID_cpc_0 = 0x28, + DBG_CLIENT_BLKID_cpc_1 = 0x29, + DBG_CLIENT_BLKID_uvdm_0 = 0x2a, + DBG_CLIENT_BLKID_uvdm_1 = 0x2b, + DBG_CLIENT_BLKID_uvdm_2 = 0x2c, + DBG_CLIENT_BLKID_uvdm_3 = 0x2d, + DBG_CLIENT_BLKID_cb000 = 0x2e, + DBG_CLIENT_BLKID_spim0 = 0x2f, + DBG_CLIENT_BLKID_mcc2 = 0x30, + DBG_CLIENT_BLKID_ds0 = 0x31, + DBG_CLIENT_BLKID_srbm = 0x32, + DBG_CLIENT_BLKID_ih = 0x33, + DBG_CLIENT_BLKID_sem = 0x34, + DBG_CLIENT_BLKID_sdma_0 = 0x35, + DBG_CLIENT_BLKID_sdma_1 = 0x36, + DBG_CLIENT_BLKID_hdp = 0x37, + DBG_CLIENT_BLKID_acp_0 = 0x38, + DBG_CLIENT_BLKID_acp_1 = 0x39, + DBG_CLIENT_BLKID_cb200 = 0x3a, + DBG_CLIENT_BLKID_scf3 = 0x3b, + DBG_CLIENT_BLKID_vceb1_0 = 0x3c, + DBG_CLIENT_BLKID_vcea1_0 = 0x3d, + DBG_CLIENT_BLKID_vcea1_1 = 0x3e, + DBG_CLIENT_BLKID_vcea1_2 = 0x3f, + DBG_CLIENT_BLKID_vcea1_3 = 0x40, + DBG_CLIENT_BLKID_bci3 = 0x41, + DBG_CLIENT_BLKID_mcd0 = 0x42, + DBG_CLIENT_BLKID_pa11 = 0x43, + DBG_CLIENT_BLKID_pa01 = 0x44, + DBG_CLIENT_BLKID_cb201 = 0x45, + DBG_CLIENT_BLKID_spim2 = 0x46, + DBG_CLIENT_BLKID_vgt2 = 0x47, + DBG_CLIENT_BLKID_pc2 = 0x48, + DBG_CLIENT_BLKID_smu_0 = 0x49, + DBG_CLIENT_BLKID_smu_1 = 0x4a, + DBG_CLIENT_BLKID_smu_2 = 0x4b, + DBG_CLIENT_BLKID_cb1 = 0x4c, + DBG_CLIENT_BLKID_ia0 = 0x4d, + DBG_CLIENT_BLKID_wd = 0x4e, + DBG_CLIENT_BLKID_ia1 = 0x4f, + DBG_CLIENT_BLKID_vcec1_0 = 0x50, + DBG_CLIENT_BLKID_scf0 = 0x51, + DBG_CLIENT_BLKID_vgt1 = 0x52, + DBG_CLIENT_BLKID_pc1 = 0x53, + DBG_CLIENT_BLKID_cb0 = 0x54, + DBG_CLIENT_BLKID_gdc_one_0 = 0x55, + DBG_CLIENT_BLKID_gdc_one_1 = 0x56, + DBG_CLIENT_BLKID_gdc_one_2 = 0x57, + DBG_CLIENT_BLKID_gdc_one_3 = 0x58, + DBG_CLIENT_BLKID_gdc_one_4 = 0x59, + DBG_CLIENT_BLKID_gdc_one_5 = 0x5a, + DBG_CLIENT_BLKID_gdc_one_6 = 0x5b, + DBG_CLIENT_BLKID_gdc_one_7 = 0x5c, + DBG_CLIENT_BLKID_gdc_one_8 = 0x5d, + DBG_CLIENT_BLKID_gdc_one_9 = 0x5e, + DBG_CLIENT_BLKID_gdc_one_10 = 0x5f, + DBG_CLIENT_BLKID_gdc_one_11 = 0x60, + DBG_CLIENT_BLKID_gdc_one_12 = 0x61, + DBG_CLIENT_BLKID_gdc_one_13 = 0x62, + DBG_CLIENT_BLKID_gdc_one_14 = 0x63, + DBG_CLIENT_BLKID_gdc_one_15 = 0x64, + DBG_CLIENT_BLKID_gdc_one_16 = 0x65, + DBG_CLIENT_BLKID_gdc_one_17 = 0x66, + DBG_CLIENT_BLKID_gdc_one_18 = 0x67, + DBG_CLIENT_BLKID_gdc_one_19 = 0x68, + DBG_CLIENT_BLKID_gdc_one_20 = 0x69, + DBG_CLIENT_BLKID_gdc_one_21 = 0x6a, + DBG_CLIENT_BLKID_gdc_one_22 = 0x6b, + DBG_CLIENT_BLKID_gdc_one_23 = 0x6c, + DBG_CLIENT_BLKID_gdc_one_24 = 0x6d, + DBG_CLIENT_BLKID_gdc_one_25 = 0x6e, + DBG_CLIENT_BLKID_gdc_one_26 = 0x6f, + DBG_CLIENT_BLKID_gdc_one_27 = 0x70, + DBG_CLIENT_BLKID_gdc_one_28 = 0x71, + DBG_CLIENT_BLKID_gdc_one_29 = 0x72, + DBG_CLIENT_BLKID_gdc_one_30 = 0x73, + DBG_CLIENT_BLKID_gdc_one_31 = 0x74, + DBG_CLIENT_BLKID_gdc_one_32 = 0x75, + DBG_CLIENT_BLKID_gdc_one_33 = 0x76, + DBG_CLIENT_BLKID_gdc_one_34 = 0x77, + DBG_CLIENT_BLKID_gdc_one_35 = 0x78, + DBG_CLIENT_BLKID_vceb0_0 = 0x79, + DBG_CLIENT_BLKID_vgt3 = 0x7a, + DBG_CLIENT_BLKID_pc3 = 0x7b, + DBG_CLIENT_BLKID_mcd3 = 0x7c, + DBG_CLIENT_BLKID_uvdu_0 = 0x7d, + DBG_CLIENT_BLKID_uvdu_1 = 0x7e, + DBG_CLIENT_BLKID_uvdu_2 = 0x7f, + DBG_CLIENT_BLKID_uvdu_3 = 0x80, + DBG_CLIENT_BLKID_uvdu_4 = 0x81, + DBG_CLIENT_BLKID_uvdu_5 = 0x82, + DBG_CLIENT_BLKID_uvdu_6 = 0x83, + DBG_CLIENT_BLKID_cb300 = 0x84, + DBG_CLIENT_BLKID_mcd1 = 0x85, + DBG_CLIENT_BLKID_sx00 = 0x86, + DBG_CLIENT_BLKID_uvdc_0 = 0x87, + DBG_CLIENT_BLKID_uvdc_1 = 0x88, + DBG_CLIENT_BLKID_mcc3 = 0x89, + DBG_CLIENT_BLKID_cpg_0 = 0x8a, + DBG_CLIENT_BLKID_cpg_1 = 0x8b, + DBG_CLIENT_BLKID_gck = 0x8c, + DBG_CLIENT_BLKID_mcc1 = 0x8d, + DBG_CLIENT_BLKID_cpf_0 = 0x8e, + DBG_CLIENT_BLKID_cpf_1 = 0x8f, + DBG_CLIENT_BLKID_rlc = 0x90, + DBG_CLIENT_BLKID_grbm = 0x91, + DBG_CLIENT_BLKID_sammsp = 0x92, + DBG_CLIENT_BLKID_dci_pg = 0x93, + DBG_CLIENT_BLKID_dci_0 = 0x94, + DBG_CLIENT_BLKID_dccg0_0 = 0x95, + DBG_CLIENT_BLKID_dccg0_1 = 0x96, + DBG_CLIENT_BLKID_dcfe01_0 = 0x97, + DBG_CLIENT_BLKID_dcfe02_0 = 0x98, + DBG_CLIENT_BLKID_dcfe03_0 = 0x99, + DBG_CLIENT_BLKID_dcfe04_0 = 0x9a, + DBG_CLIENT_BLKID_dcfe05_0 = 0x9b, + DBG_CLIENT_BLKID_dcfe06_0 = 0x9c, + DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* GFX_8_0_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h new file mode 100644 index 000000000000..7d722458d9f5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h @@ -0,0 +1,20776 @@ +/* + * GFX_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_8_0_SH_MASK_H +#define GFX_8_0_SH_MASK_H + +#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff +#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 +#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff +#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 +#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff +#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 +#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff +#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 +#define CB_COLOR_CONTROL__MODE_MASK 0x70 +#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 +#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000 +#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR0_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR0_INFO__FORMAT_MASK 0x7c +#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR1_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR1_INFO__FORMAT_MASK 0x7c +#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR2_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR2_INFO__FORMAT_MASK 0x7c +#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR3_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR3_INFO__FORMAT_MASK 0x7c +#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR4_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR4_INFO__FORMAT_MASK 0x7c +#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR5_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR5_INFO__FORMAT_MASK 0x7c +#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR6_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR6_INFO__FORMAT_MASK 0x7c +#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR7_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR7_INFO__FORMAT_MASK 0x7c +#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf +#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0 +#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 +#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00 +#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 +#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000 +#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc +#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000 +#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 +#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000 +#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 +#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000 +#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 +#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000 +#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c +#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf +#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 +#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00 +#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 +#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000 +#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc +#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000 +#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 +#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000 +#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 +#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000 +#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 +#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000 +#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0 +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000 +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000 +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000 +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 +#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000 +#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000 +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000 +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000 +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000 +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000 +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000 +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000 +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0 +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000 +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 +#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000 +#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00 +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000 +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000 +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 +#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000 +#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1 +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2 +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 +#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4 +#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 +#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8 +#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x40 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 +#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00 +#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000 +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 +#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000 +#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000 +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000 +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000 +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf +#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1 +#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0 +#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2 +#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1 +#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4 +#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2 +#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20 +#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5 +#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40 +#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6 +#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80 +#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7 +#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100 +#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8 +#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200 +#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9 +#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400 +#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa +#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800 +#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb +#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1 +#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0 +#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2 +#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1 +#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4 +#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2 +#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20 +#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5 +#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40 +#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6 +#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80 +#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7 +#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100 +#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8 +#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200 +#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9 +#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400 +#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa +#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800 +#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb +#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000 +#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc +#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000 +#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd +#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000 +#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe +#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000 +#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf +#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000 +#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10 +#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000 +#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11 +#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000 +#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12 +#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000 +#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13 +#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000 +#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14 +#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000 +#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15 +#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3 +#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0 +#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4 +#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2 +#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20 +#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5 +#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40 +#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6 +#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80 +#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7 +#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100 +#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8 +#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200 +#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9 +#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400 +#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa +#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800 +#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb +#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000 +#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc +#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000 +#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd +#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000 +#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe +#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000 +#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf +#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000 +#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10 +#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000 +#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11 +#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000 +#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12 +#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f +#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0 +#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0 +#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6 +#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000 +#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc +#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000 +#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd +#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000 +#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe +#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000 +#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10 +#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000 +#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11 +#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000 +#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12 +#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000 +#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14 +#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000 +#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15 +#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000 +#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16 +#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000 +#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17 +#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1 +#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0 +#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2 +#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1 +#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4 +#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2 +#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20 +#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5 +#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40 +#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6 +#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80 +#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7 +#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff +#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0 +#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000 +#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc +#define CP_DFY_CNTL__POLICY_MASK 0x1 +#define CP_DFY_CNTL__POLICY__SHIFT 0x0 +#define CP_DFY_CNTL__MTYPE_MASK 0xc +#define CP_DFY_CNTL__MTYPE__SHIFT 0x2 +#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000 +#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c +#define CP_DFY_CNTL__MODE_MASK 0x60000000 +#define CP_DFY_CNTL__MODE__SHIFT 0x1d +#define CP_DFY_CNTL__ENABLE_MASK 0x80000000 +#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f +#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff +#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 +#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000 +#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 +#define CP_DFY_STAT__BUSY_MASK 0x80000000 +#define CP_DFY_STAT__BUSY__SHIFT 0x1f +#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff +#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0 +#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CP_DFY_DATA_0__DATA_MASK 0xffffffff +#define CP_DFY_DATA_0__DATA__SHIFT 0x0 +#define CP_DFY_DATA_1__DATA_MASK 0xffffffff +#define CP_DFY_DATA_1__DATA__SHIFT 0x0 +#define CP_DFY_DATA_2__DATA_MASK 0xffffffff +#define CP_DFY_DATA_2__DATA__SHIFT 0x0 +#define CP_DFY_DATA_3__DATA_MASK 0xffffffff +#define CP_DFY_DATA_3__DATA__SHIFT 0x0 +#define CP_DFY_DATA_4__DATA_MASK 0xffffffff +#define CP_DFY_DATA_4__DATA__SHIFT 0x0 +#define CP_DFY_DATA_5__DATA_MASK 0xffffffff +#define CP_DFY_DATA_5__DATA__SHIFT 0x0 +#define CP_DFY_DATA_6__DATA_MASK 0xffffffff +#define CP_DFY_DATA_6__DATA__SHIFT 0x0 +#define CP_DFY_DATA_7__DATA_MASK 0xffffffff +#define CP_DFY_DATA_7__DATA__SHIFT 0x0 +#define CP_DFY_DATA_8__DATA_MASK 0xffffffff +#define CP_DFY_DATA_8__DATA__SHIFT 0x0 +#define CP_DFY_DATA_9__DATA_MASK 0xffffffff +#define CP_DFY_DATA_9__DATA__SHIFT 0x0 +#define CP_DFY_DATA_10__DATA_MASK 0xffffffff +#define CP_DFY_DATA_10__DATA__SHIFT 0x0 +#define CP_DFY_DATA_11__DATA_MASK 0xffffffff +#define CP_DFY_DATA_11__DATA__SHIFT 0x0 +#define CP_DFY_DATA_12__DATA_MASK 0xffffffff +#define CP_DFY_DATA_12__DATA__SHIFT 0x0 +#define CP_DFY_DATA_13__DATA_MASK 0xffffffff +#define CP_DFY_DATA_13__DATA__SHIFT 0x0 +#define CP_DFY_DATA_14__DATA_MASK 0xffffffff +#define CP_DFY_DATA_14__DATA__SHIFT 0x0 +#define CP_DFY_DATA_15__DATA_MASK 0xffffffff +#define CP_DFY_DATA_15__DATA__SHIFT 0x0 +#define CP_DFY_CMD__OFFSET_MASK 0x1ff +#define CP_DFY_CMD__OFFSET__SHIFT 0x0 +#define CP_DFY_CMD__SIZE_MASK 0xffff0000 +#define CP_DFY_CMD__SIZE__SHIFT 0x10 +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00 +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 +#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff +#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff +#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB2_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB0_CNTL__MTYPE_MASK 0x18000 +#define CP_RB0_CNTL__MTYPE__SHIFT 0xf +#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000 +#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 +#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000 +#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB_CNTL__MTYPE_MASK 0x18000 +#define CP_RB_CNTL__MTYPE__SHIFT 0xf +#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11 +#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000 +#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB1_CNTL__MTYPE_MASK 0x18000 +#define CP_RB1_CNTL__MTYPE__SHIFT 0xf +#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000 +#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB2_CNTL__MTYPE_MASK 0x18000 +#define CP_RB2_CNTL__MTYPE__SHIFT 0xf +#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000 +#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000 +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000 +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000 +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000 +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 +#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000 +#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000 +#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 +#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000 +#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000 +#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000 +#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000 +#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000 +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000 +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 +#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000 +#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000 +#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 +#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000 +#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000 +#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff +#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3 +#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0 +#define CP_RB_VMID__RB0_VMID_MASK 0xf +#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 +#define CP_RB_VMID__RB1_VMID_MASK 0xf00 +#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 +#define CP_RB_VMID__RB2_VMID_MASK 0xf0000 +#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 +#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf +#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf +#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 +#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff +#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1 +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2 +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4 +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8 +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10 +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20 +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40 +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80 +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100 +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200 +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1 +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2 +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4 +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8 +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10 +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20 +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40 +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80 +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100 +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200 +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xffffffff +#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2 +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 +#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c +#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80 +#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 +#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0 +#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300 +#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 +#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00 +#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000 +#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc +#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000 +#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff +#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff +#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000 +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e +#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000 +#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000 +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000 +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff +#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff +#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff +#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff +#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff +#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff +#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff +#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff +#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff +#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff +#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 +#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7 +#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 +#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000 +#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff +#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 +#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00 +#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 +#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000 +#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 +#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff +#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 +#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000 +#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10 +#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff +#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 +#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000 +#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 +#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff +#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 +#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000 +#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 +#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff +#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000 +#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c +#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1 +#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2 +#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000 +#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff +#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf +#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000 +#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17 +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000 +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000 +#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1 +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10 +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20 +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1 +#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 +#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2 +#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 +#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4 +#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 +#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8 +#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 +#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10 +#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 +#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20 +#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 +#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40 +#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 +#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80 +#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 +#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400 +#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800 +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb +#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000 +#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc +#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000 +#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd +#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000 +#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d +#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000 +#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e +#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000 +#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1 +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2 +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800 +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000 +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000 +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000 +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000 +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000 +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 +#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000 +#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16 +#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000 +#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17 +#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000 +#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18 +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1 +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 +#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2 +#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 +#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20 +#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 +#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100 +#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb +#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000 +#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc +#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000 +#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd +#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000 +#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe +#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000 +#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf +#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000 +#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 +#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000 +#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11 +#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000 +#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a +#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000 +#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000 +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c +#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000 +#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e +#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000 +#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200 +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800 +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000 +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000 +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000 +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000 +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000 +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000 +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000 +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000 +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000 +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1 +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 +#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80 +#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7 +#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100 +#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8 +#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200 +#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9 +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10 +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000 +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000 +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000 +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000 +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000 +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000 +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 +#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 +#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c +#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000 +#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d +#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 +#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e +#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000 +#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf +#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 +#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff +#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 +#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff +#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff +#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff +#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000 +#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 +#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100 +#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 +#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff +#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff +#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3 +#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc +#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2 +#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00 +#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa +#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000 +#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12 +#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000 +#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13 +#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000 +#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17 +#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000 +#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c +#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000 +#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc +#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000 +#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19 +#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000 +#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b +#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff +#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0 +#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000 +#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d +#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff +#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc +#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff +#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff +#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000 +#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19 +#define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000 +#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b +#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000 +#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19 +#define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000 +#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1 +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff +#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 +#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000 +#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 +#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff +#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000 +#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 +#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000 +#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 +#define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000 +#define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b +#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000 +#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d +#define CP_APPEND_DATA__DATA_MASK 0xffffffff +#define CP_APPEND_DATA__DATA__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 +#define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000 +#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14 +#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000 +#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 +#define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000 +#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14 +#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000 +#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 +#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f +#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 +#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1 +#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 +#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2 +#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 +#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4 +#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2 +#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8 +#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 +#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40 +#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 +#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80 +#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 +#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100 +#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 +#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200 +#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 +#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400 +#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa +#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800 +#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb +#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000 +#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc +#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000 +#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd +#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000 +#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000 +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf +#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000 +#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 +#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000 +#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 +#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000 +#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 +#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000 +#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 +#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000 +#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 +#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000 +#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 +#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000 +#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000 +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000 +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000 +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d +#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000 +#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e +#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000 +#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f +#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff +#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff +#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff +#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 +#define CP_COHER_STATUS__MEID_MASK 0x3000000 +#define CP_COHER_STATUS__MEID__SHIFT 0x18 +#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000 +#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e +#define CP_COHER_STATUS__STATUS_MASK 0x80000000 +#define CP_COHER_STATUS__STATUS__SHIFT 0x1f +#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff +#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00 +#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa +#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000 +#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000 +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000 +#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000 +#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16 +#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000 +#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000 +#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff +#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000 +#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15 +#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000 +#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16 +#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000 +#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18 +#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000 +#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000 +#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000 +#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000 +#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000 +#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff +#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00 +#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa +#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000 +#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000 +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000 +#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000 +#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16 +#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000 +#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000 +#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff +#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000 +#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15 +#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000 +#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16 +#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000 +#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18 +#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000 +#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000 +#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000 +#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000 +#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000 +#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30 +#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 +#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000 +#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c +#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000 +#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d +#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000 +#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e +#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff +#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c +#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff +#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1 +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000 +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff +#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff +#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff +#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff +#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff +#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 +#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff +#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff +#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff +#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff +#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3 +#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3 +#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1 +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3 +#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1 +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2 +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4 +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8 +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10 +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20 +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40 +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80 +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000 +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000 +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000 +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000 +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000 +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800 +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000 +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000 +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000 +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000 +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000 +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000 +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000 +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000 +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000 +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800 +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000 +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000 +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000 +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000 +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000 +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000 +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 +#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000 +#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12 +#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000 +#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13 +#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000 +#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14 +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 +#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100 +#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 +#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200 +#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 +#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400 +#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000 +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000 +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000 +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000 +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf +#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000 +#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 +#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000 +#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 +#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000 +#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 +#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000 +#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 +#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000 +#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 +#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000 +#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 +#define CP_STAT__ROQ_RING_BUSY_MASK 0x200 +#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 +#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400 +#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa +#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800 +#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb +#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000 +#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc +#define CP_STAT__DC_BUSY_MASK 0x2000 +#define CP_STAT__DC_BUSY__SHIFT 0xd +#define CP_STAT__ATCL2IU_BUSY_MASK 0x4000 +#define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe +#define CP_STAT__PFP_BUSY_MASK 0x8000 +#define CP_STAT__PFP_BUSY__SHIFT 0xf +#define CP_STAT__MEQ_BUSY_MASK 0x10000 +#define CP_STAT__MEQ_BUSY__SHIFT 0x10 +#define CP_STAT__ME_BUSY_MASK 0x20000 +#define CP_STAT__ME_BUSY__SHIFT 0x11 +#define CP_STAT__QUERY_BUSY_MASK 0x40000 +#define CP_STAT__QUERY_BUSY__SHIFT 0x12 +#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000 +#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 +#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000 +#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 +#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000 +#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 +#define CP_STAT__DMA_BUSY_MASK 0x400000 +#define CP_STAT__DMA_BUSY__SHIFT 0x16 +#define CP_STAT__RCIU_BUSY_MASK 0x800000 +#define CP_STAT__RCIU_BUSY__SHIFT 0x17 +#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000 +#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 +#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000 +#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19 +#define CP_STAT__CE_BUSY_MASK 0x4000000 +#define CP_STAT__CE_BUSY__SHIFT 0x1a +#define CP_STAT__TCIU_BUSY_MASK 0x8000000 +#define CP_STAT__TCIU_BUSY__SHIFT 0x1b +#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000 +#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000 +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000 +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e +#define CP_STAT__CP_BUSY_MASK 0x80000000 +#define CP_STAT__CP_BUSY__SHIFT 0x1f +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f +#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 +#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf +#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 +#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf +#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0 +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10 +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 +#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000 +#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 +#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000 +#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 +#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000 +#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 +#define CP_ME_CNTL__CE_HALT_MASK 0x1000000 +#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 +#define CP_ME_CNTL__CE_STEP_MASK 0x2000000 +#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 +#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000 +#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a +#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000 +#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c +#define CP_ME_CNTL__ME_STEP_MASK 0x20000000 +#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c +#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1 +#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 +#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0 +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc +#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff +#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc +#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff +#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc +#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 +#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff +#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 +#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff +#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 +#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00 +#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 +#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff +#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff +#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00 +#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 +#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000 +#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 +#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff +#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 +#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00 +#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 +#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000 +#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 +#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff +#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 +#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00 +#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 +#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000 +#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00 +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 +#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff +#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 +#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00 +#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 +#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff +#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 +#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff +#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000 +#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff +#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 +#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff +#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 +#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff +#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000 +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000 +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000 +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800 +#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000 +#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12 +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000 +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000 +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 +#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000 +#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000 +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f +#define CP_RINGID__RINGID_MASK 0x3 +#define CP_RINGID__RINGID__SHIFT 0x0 +#define CP_PIPEID__PIPE_ID_MASK 0x3 +#define CP_PIPEID__PIPE_ID__SHIFT 0x0 +#define CP_VMID__VMID_MASK 0xf +#define CP_VMID__VMID__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f +#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 +#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0 +#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 +#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00 +#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 +#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc +#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1 +#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2 +#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 +#define CP_HQD_VMID__VMID_MASK 0xf +#define CP_HQD_VMID__VMID__SHIFT 0x0 +#define CP_HQD_VMID__IB_VMID_MASK 0xf00 +#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 +#define CP_HQD_VMID__VQID_MASK 0x3ff0000 +#define CP_HQD_VMID__VQID__SHIFT 0x10 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000 +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000 +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000 +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000 +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3 +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1 +#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10 +#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 +#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00 +#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000 +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f +#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff +#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 +#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff +#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff +#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 +#define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000 +#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000 +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000 +#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000 +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000 +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000 +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d +#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000 +#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e +#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000 +#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff +#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000 +#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000 +#define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b +#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000 +#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f +#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff +#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700 +#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800 +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000 +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000 +#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000 +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000 +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000 +#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17 +#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000 +#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000 +#define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000 +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d +#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000 +#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e +#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000 +#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f +#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 +#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1 +#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 +#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6 +#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 +#define CP_HQD_MSG_TYPE__ACTION_MASK 0x7 +#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 +#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70 +#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff +#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3 +#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 +#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc +#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 +#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70 +#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80 +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100 +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200 +#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 +#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00 +#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff +#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 +#define CP_MQD_CONTROL__VMID_MASK 0xf +#define CP_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000 +#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc +#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000 +#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd +#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000 +#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17 +#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000 +#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_MQD_CONTROL__MTYPE_MASK 0x18000000 +#define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b +#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff +#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff +#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f +#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000 +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000 +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe +#define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000 +#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf +#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000 +#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17 +#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000 +#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000 +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000 +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f +#define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff +#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000 +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e +#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000 +#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f +#define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff +#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000 +#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 +#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff +#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000 +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000 +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1 +#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0 +#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6 +#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1 +#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8 +#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000 +#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc +#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000 +#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1 +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2 +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc +#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf +#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 +#define CP_HQD_ERROR__SUA_ERROR_MASK 0x10 +#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff +#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff +#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0 +#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff +#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff +#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff +#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff +#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf +#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0 +#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0 +#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4 +#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00 +#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8 +#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000 +#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd +#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000 +#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf +#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000 +#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11 +#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000 +#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13 +#define DB_Z_INFO__FORMAT_MASK 0x3 +#define DB_Z_INFO__FORMAT__SHIFT 0x0 +#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc +#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 +#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000 +#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd +#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000 +#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14 +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000 +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 +#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 +#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_Z_INFO__READ_SIZE_MASK 0x10000000 +#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c +#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000 +#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d +#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000 +#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e +#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000 +#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f +#define DB_STENCIL_INFO__FORMAT_MASK 0x1 +#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 +#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000 +#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd +#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000 +#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14 +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000 +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d +#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000 +#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e +#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff +#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0 +#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800 +#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb +#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff +#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff +#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000 +#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd +#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000 +#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1 +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 +#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4 +#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 +#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8 +#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 +#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80 +#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 +#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00 +#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000 +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1 +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2 +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 +#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70 +#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 +#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00 +#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc +#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000 +#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3 +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa +#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800 +#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000 +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000 +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000 +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000 +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000 +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000 +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000 +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000 +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000 +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000 +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000 +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000 +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800 +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000 +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000 +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000 +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 +#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7 +#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 +#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70 +#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000 +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 +#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000 +#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 +#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000 +#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 +#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000 +#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1 +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 +#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30 +#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 +#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40 +#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800 +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000 +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000 +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd +#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff +#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff +#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 +#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff +#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 +#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff +#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 +#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff +#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 +#define DB_HTILE_SURFACE__LINEAR_MASK 0x1 +#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0 +#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2 +#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4 +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 +#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8 +#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 +#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0 +#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00 +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000 +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 +#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000 +#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11 +#define DB_PRELOAD_CONTROL__START_X_MASK 0xff +#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 +#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00 +#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 +#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000 +#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 +#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000 +#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 +#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff +#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 +#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00 +#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 +#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000 +#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 +#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000 +#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000 +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000 +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 +#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1 +#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 +#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2 +#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 +#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70 +#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 +#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700 +#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000 +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000 +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f +#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf +#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 +#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0 +#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 +#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00 +#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc +#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000 +#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe +#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000 +#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1 +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 +#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4 +#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 +#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30 +#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000 +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000 +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000 +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 +#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000 +#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 +#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000 +#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000 +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000 +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000 +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1 +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4 +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5 +#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40 +#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7 +#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100 +#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8 +#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00 +#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000 +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000 +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000 +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000 +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000 +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000 +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000 +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f +#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4 +#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80 +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200 +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800 +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000 +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000 +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000 +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000 +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000 +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000 +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 +#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000 +#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000 +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000 +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000 +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d +#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000 +#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e +#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000 +#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 +#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0 +#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4 +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000 +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 +#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f +#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 +#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0 +#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 +#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800 +#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb +#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000 +#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000 +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 +#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000 +#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b +#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000 +#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c +#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000 +#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d +#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000 +#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e +#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000 +#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f +#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3 +#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 +#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc +#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 +#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30 +#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 +#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0 +#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 +#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300 +#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 +#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00 +#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa +#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000 +#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc +#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000 +#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe +#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000 +#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 +#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000 +#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000 +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15 +#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000 +#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19 +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0 +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5 +#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00 +#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa +#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000 +#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000 +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000 +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 +#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf +#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0 +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 +#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000 +#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f +#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff +#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 +#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3 +#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 +#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff +#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0 +#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff +#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0 +#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff +#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0 +#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 +#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 +#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 +#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 +#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 +#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff +#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 +#define GB_GPU_ID__GPU_ID_MASK 0xf +#define GB_GPU_ID__GPU_ID__SHIFT 0x0 +#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf +#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 +#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0 +#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 +#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00 +#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 +#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000 +#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc +#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000 +#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 +#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000 +#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 +#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000 +#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 +#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000 +#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c +#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 +#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000 +#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10 +#define GB_EDC_MODE__DED_MODE_MASK 0x300000 +#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 +#define GB_EDC_MODE__PROP_FED_MASK 0x20000000 +#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d +#define GB_EDC_MODE__BYPASS_MASK 0x80000000 +#define GB_EDC_MODE__BYPASS__SHIFT 0x1f +#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1 +#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 +#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 +#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 +#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7 +#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7 +#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff +#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff +#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 +#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff +#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000 +#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 +#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0 +#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 +#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3 +#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 +#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc +#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 +#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30 +#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 +#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0 +#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 +#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000 +#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe +#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000 +#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20 +#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200 +#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS__DB_CLEAN_MASK 0x1000 +#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc +#define GRBM_STATUS__CB_CLEAN_MASK 0x2000 +#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd +#define GRBM_STATUS__TA_BUSY_MASK 0x4000 +#define GRBM_STATUS__TA_BUSY__SHIFT 0xe +#define GRBM_STATUS__GDS_BUSY_MASK 0x8000 +#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf +#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000 +#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 +#define GRBM_STATUS__VGT_BUSY_MASK 0x20000 +#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 +#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000 +#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 +#define GRBM_STATUS__IA_BUSY_MASK 0x80000 +#define GRBM_STATUS__IA_BUSY__SHIFT 0x13 +#define GRBM_STATUS__SX_BUSY_MASK 0x100000 +#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 +#define GRBM_STATUS__WD_BUSY_MASK 0x200000 +#define GRBM_STATUS__WD_BUSY__SHIFT 0x15 +#define GRBM_STATUS__SPI_BUSY_MASK 0x400000 +#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 +#define GRBM_STATUS__BCI_BUSY_MASK 0x800000 +#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 +#define GRBM_STATUS__SC_BUSY_MASK 0x1000000 +#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 +#define GRBM_STATUS__PA_BUSY_MASK 0x2000000 +#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 +#define GRBM_STATUS__DB_BUSY_MASK 0x4000000 +#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a +#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000 +#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c +#define GRBM_STATUS__CP_BUSY_MASK 0x20000000 +#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d +#define GRBM_STATUS__CB_BUSY_MASK 0x40000000 +#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e +#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000 +#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400 +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800 +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000 +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000 +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd +#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000 +#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe +#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000 +#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 +#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000 +#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 +#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000 +#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a +#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000 +#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c +#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000 +#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d +#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000 +#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f +#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1 +#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 +#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000 +#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 +#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000 +#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 +#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f +#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0 +#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff +#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0 +#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff +#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00 +#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000 +#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000 +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000 +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 +#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2 +#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1 +#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20 +#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5 +#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40 +#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6 +#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80 +#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7 +#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00 +#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8 +#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000 +#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc +#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000 +#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd +#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000 +#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f +#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1 +#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0 +#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2 +#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1 +#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4 +#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4 +#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20 +#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15 +#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc +#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000 +#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 +#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000 +#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 +#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 +#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000 +#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11 +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000 +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f +#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1 +#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 +#define GRBM_TRAP_OP__RW_MASK 0x1 +#define GRBM_TRAP_OP__RW__SHIFT 0x0 +#define GRBM_TRAP_ADDR__DATA_MASK 0xffff +#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff +#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD__DATA_MASK 0xffffffff +#define GRBM_TRAP_WD__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff +#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 +#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3 +#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 +#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4 +#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1 +#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c +#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 +#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0 +#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 +#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000 +#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc +#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000 +#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd +#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000 +#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 +#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000 +#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 +#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000 +#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff +#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff +#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff +#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff +#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff +#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff +#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff +#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff +#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff +#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0 +#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff +#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 +#define GRBM_NOWHERE__DATA_MASK 0xffffffff +#define GRBM_NOWHERE__DATA__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1 +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800 +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800 +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000 +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000 +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000 +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000 +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 +#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8 +#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 +#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10 +#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 +#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd +#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000 +#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000 +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000 +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1 +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20 +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000 +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1 +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1 +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 +#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10 +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000 +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000 +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7 +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000 +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c +#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff +#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_TRI_MASK 0xf +#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0 +#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 +#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00 +#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 +#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000 +#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc +#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000 +#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 +#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000 +#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 +#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000 +#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800 +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000 +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000 +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1 +#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800 +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000 +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000 +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000 +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000 +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000 +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000 +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000 +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30 +#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40 +#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 +#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80 +#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 +#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300 +#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 +#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00 +#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa +#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000 +#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc +#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000 +#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe +#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000 +#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 +#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000 +#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 +#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000 +#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 +#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000 +#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 +#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000 +#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a +#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000 +#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 +#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff +#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff +#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1 +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 +#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0 +#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000 +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000 +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000 +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000 +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000 +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000 +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000 +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000 +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17 +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000 +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 +#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff +#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff +#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff +#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000 +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000 +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 +#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000 +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000 +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000 +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0 +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0 +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8 +#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600 +#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0 +#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700 +#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8 +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800 +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a +#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000 +#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c +#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000 +#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f +#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7 +#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0 +#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38 +#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19 +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000 +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000 +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000 +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000 +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b +#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000 +#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c +#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000 +#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d +#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000 +#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e +#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000 +#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19 +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000 +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000 +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000 +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000 +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7 +#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0 +#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8 +#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3 +#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10 +#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4 +#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20 +#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5 +#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40 +#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6 +#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80 +#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7 +#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00 +#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8 +#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000 +#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc +#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000 +#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe +#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000 +#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf +#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000 +#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10 +#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000 +#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc +#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000 +#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12 +#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13 +#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14 +#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e +#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff +#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a +#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380 +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7 +#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00 +#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa +#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000 +#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf +#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000 +#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10 +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c +#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f +#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7 +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8 +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000 +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000 +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000 +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000 +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f +#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3 +#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2 +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8 +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000 +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf +#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000 +#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10 +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000 +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12 +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000 +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13 +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000 +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14 +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15 +#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000 +#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16 +#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c +#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000 +#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d +#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000 +#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e +#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000 +#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f +#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff +#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0 +#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000 +#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10 +#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff +#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0 +#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000 +#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10 +#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff +#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0 +#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000 +#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0 +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000 +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000 +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10 +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000 +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13 +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14 +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17 +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18 +#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000 +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000 +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c +#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000 +#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e +#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000 +#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f +#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3 +#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0 +#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc +#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2 +#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3 +#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0 +#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc +#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1 +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 +#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380 +#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800 +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb +#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000 +#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc +#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000 +#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe +#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff +#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff +#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff +#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 +#define COMPUTE_START_X__START_MASK 0xffffffff +#define COMPUTE_START_X__START__SHIFT 0x0 +#define COMPUTE_START_Y__START_MASK 0xffffffff +#define COMPUTE_START_Y__START__SHIFT 0x0 +#define COMPUTE_START_Z__START_MASK 0xffffffff +#define COMPUTE_START_Z__START__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 +#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff +#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__DATA_MASK 0xff +#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100 +#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8 +#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff +#define COMPUTE_TBA_LO__DATA__SHIFT 0x0 +#define COMPUTE_TBA_HI__DATA_MASK 0xff +#define COMPUTE_TBA_HI__DATA__SHIFT 0x0 +#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff +#define COMPUTE_TMA_LO__DATA__SHIFT 0x0 +#define COMPUTE_TMA_HI__DATA_MASK 0xff +#define COMPUTE_TMA_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f +#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0 +#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 +#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00 +#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa +#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000 +#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc +#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000 +#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 +#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000 +#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 +#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000 +#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 +#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000 +#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 +#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000 +#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 +#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e +#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40 +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 +#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80 +#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800 +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000 +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd +#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000 +#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf +#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000 +#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 +#define COMPUTE_VMID__DATA_MASK 0xf +#define COMPUTE_VMID__DATA__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000 +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff +#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 +#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff +#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff +#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff +#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3 +#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4 +#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 +#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8 +#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 +#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10 +#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0 +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 +#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff +#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 +#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff +#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 +#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000 +#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000 +#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1 +#define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6 +#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1 +#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 +#define COMPUTE_NOWHERE__DATA_MASK 0xffffffff +#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 +#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff +#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0 +#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000 +#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15 +#define CSPRIV_CONNECT__VMID_MASK 0x3c000000 +#define CSPRIV_CONNECT__VMID__SHIFT 0x1a +#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000 +#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f +#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff +#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff +#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff +#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff +#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000 +#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a +#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000 +#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b +#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000 +#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c +#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f +#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0 +#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 +#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 +#define RLC_CNTL__FORCE_RETRY_MASK 0x2 +#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 +#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4 +#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 +#define RLC_CNTL__RLC_STEP_F32_MASK 0x8 +#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 +#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10 +#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4 +#define RLC_CNTL__RESERVED_MASK 0xffffff00 +#define RLC_CNTL__RESERVED__SHIFT 0x8 +#define RLC_DEBUG_SELECT__SELECT_MASK 0xff +#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0 +#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00 +#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8 +#define RLC_DEBUG__DATA_MASK 0xffffffff +#define RLC_DEBUG__DATA__SHIFT 0x0 +#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3 +#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0 +#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4 +#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2 +#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8 +#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3 +#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10 +#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4 +#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0 +#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5 +#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00 +#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9 +#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000 +#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd +#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000 +#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14 +#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000 +#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18 +#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000 +#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a +#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000 +#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b +#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000 +#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c +#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000 +#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d +#define RLC_STAT__RLC_BUSY_MASK 0x1 +#define RLC_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2 +#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1 +#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4 +#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2 +#define RLC_STAT__RESERVED_MASK 0xfffffff8 +#define RLC_STAT__RESERVED__SHIFT 0x3 +#define RLC_SAFE_MODE__CMD_MASK 0x1 +#define RLC_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e +#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SAFE_MODE__RESERVED1_MASK 0xe0 +#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SAFE_MODE__RESPONSE_MASK 0xf00 +#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000 +#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1 +#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0 +#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe +#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 +#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c +#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80 +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 +#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff +#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 +#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1 +#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e +#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0 +#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00 +#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000 +#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SMU_SAFE_MODE__CMD_MASK 0x1 +#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e +#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0 +#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00 +#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000 +#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_RLCV_COMMAND__CMD_MASK 0xf +#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 +#define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0 +#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 +#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1 +#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 +#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7 +#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1 +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 +#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2 +#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4 +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 +#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8 +#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0 +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 +#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000 +#define RLC_LB_CNTL__RESERVED__SHIFT 0xc +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 +#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff +#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0 +#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff +#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0 +#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe +#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10 +#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4 +#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0 +#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000 +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 +#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff +#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0 +#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300 +#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8 +#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00 +#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa +#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff +#define RLC_GPM_DEBUG__DATA__SHIFT 0x0 +#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff +#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_HYP_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000 +#define RLC_HYP_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000 +#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc +#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1 +#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0 +#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2 +#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1 +#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c +#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2 +#define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80 +#define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7 +#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000 +#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18 +#define RLC_ROM_CNTL__USE_ROM_MASK 0x1 +#define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0 +#define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2 +#define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1 +#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4 +#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2 +#define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8 +#define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3 +#define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10 +#define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4 +#define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0 +#define RLC_ROM_CNTL__RESERVED__SHIFT 0x5 +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 +#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1 +#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2 +#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8 +#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10 +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20 +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40 +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80 +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100 +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 +#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200 +#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 +#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400 +#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800 +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000 +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc +#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000 +#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd +#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000 +#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe +#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000 +#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf +#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000 +#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000 +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 +#define RLC_GPM_STAT__RESERVED_MASK 0xfc0000 +#define RLC_GPM_STAT__RESERVED__SHIFT 0x12 +#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000 +#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4 +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8 +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10 +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 +#define RLC_PG_CNTL__RESERVED_MASK 0x3fe0 +#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 +#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000 +#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe +#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000 +#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000 +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 +#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000 +#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13 +#define RLC_PG_CNTL__RESERVED1_MASK 0xf00000 +#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 +#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0 +#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 +#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf +#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0 +#define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0 +#define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4 +#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700 +#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8 +#define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800 +#define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb +#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf +#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0 +#define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0 +#define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4 +#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700 +#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8 +#define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800 +#define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb +#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff +#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 +#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000 +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000 +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000 +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff +#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00 +#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 +#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff +#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 +#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1 +#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 +#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe +#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00 +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000 +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 +#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000 +#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 +#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00 +#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 +#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1 +#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0 +#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe +#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1 +#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1 +#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0 +#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe +#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1 +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30 +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0 +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800 +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000 +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf +#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000 +#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11 +#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff +#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff +#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff +#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18 +#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff +#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 +#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100 +#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 +#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200 +#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 +#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400 +#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa +#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800 +#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000 +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc +#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000 +#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd +#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000 +#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe +#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000 +#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf +#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000 +#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 +#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000 +#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a +#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000 +#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b +#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000 +#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c +#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff +#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000 +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18 +#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff +#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff +#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00 +#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 +#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff +#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00 +#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000 +#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000 +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000 +#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000 +#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000 +#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00 +#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000 +#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000 +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000 +#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000 +#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000 +#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 +#define RLC_GPR_REG1__DATA_MASK 0xffffffff +#define RLC_GPR_REG1__DATA__SHIFT 0x0 +#define RLC_GPR_REG2__DATA_MASK 0xffffffff +#define RLC_GPR_REG2__DATA__SHIFT 0x0 +#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1 +#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 +#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2 +#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 +#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4 +#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 +#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78 +#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 +#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80 +#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 +#define RLC_MGCG_CTRL__SPARE_MASK 0xffff8000 +#define RLC_MGCG_CTRL__SPARE__SHIFT 0xf +#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1 +#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 +#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2 +#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 +#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4 +#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 +#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8 +#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 +#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0 +#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 +#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf +#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0 +#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0 +#define RLC_SPM_VMID__RESERVED__SHIFT 0x4 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 +#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe +#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 +#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe +#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 +#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff +#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0 +#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00 +#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8 +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000 +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000 +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10 +#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff +#define RLC_SPM_DEBUG__DATA__SHIFT 0x0 +#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff +#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0 +#define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff +#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 +#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff +#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 +#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff +#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 +#define RLC_PG_DELAY_3__RESERVED_MASK 0xffffff00 +#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff +#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 +#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff +#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff +#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff +#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 +#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1 +#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 +#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2 +#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 +#define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc +#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 +#define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff +#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0 +#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00 +#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8 +#define RLC_SRM_DEBUG__DATA_MASK 0xffffffff +#define RLC_SRM_DEBUG__DATA__SHIFT 0x0 +#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x3ff +#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xfffffc00 +#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xa +#define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff +#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x3ff +#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00 +#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa +#define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff +#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND__OP_MASK 0x1 +#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0 +#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 +#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000 +#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 +#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000 +#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000 +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 +#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1 +#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe +#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 +#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0 +#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 +#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000 +#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 +#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000 +#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c +#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000 +#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc +#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 +#define RLC_SRM_STAT__SRM_STATUS_MASK 0x1 +#define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0 +#define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe +#define RLC_SRM_STAT__RESERVED__SHIFT 0x1 +#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1 +#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 +#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe +#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 +#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff +#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff +#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff +#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 +#define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff +#define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0 +#define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff +#define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0 +#define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff +#define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0 +#define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff +#define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0 +#define RLC_SMU_COMMAND__CMD_MASK 0xffffffff +#define RLC_SMU_COMMAND__CMD__SHIFT 0x0 +#define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff +#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 +#define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00 +#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 +#define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000 +#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 +#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000 +#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 +#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff +#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc +#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000 +#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000 +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 +#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1 +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe +#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000 +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0xf +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x10 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x20 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0xc0 +#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0xff00 +#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0xff0000 +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xff000000 +#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0xf +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xfffffff0 +#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x7f +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x80 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 +#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x300 +#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xfffffc00 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xffffffff +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_MASK 0xff +#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS_MASK 0xf00 +#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG9__RESERVED_MASK 0xfffff000 +#define RLC_GPU_IOV_CFG_REG9__RESERVED__SHIFT 0xc +#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF_MASK 0xffff +#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG10__RESERVED_MASK 0xffff0000 +#define RLC_GPU_IOV_CFG_REG10__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG11__YIELD_MASK 0xffffffff +#define RLC_GPU_IOV_CFG_REG11__YIELD__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0_MASK 0xff +#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1_MASK 0xff00 +#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2_MASK 0xff0000 +#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3_MASK 0xff000000 +#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3__SHIFT 0x18 +#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4_MASK 0xff +#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5_MASK 0xff00 +#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6_MASK 0xff0000 +#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7_MASK 0xff000000 +#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7__SHIFT 0x18 +#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8_MASK 0xff +#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9_MASK 0xff00 +#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10_MASK 0xff0000 +#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11_MASK 0xff000000 +#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11__SHIFT 0x18 +#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12_MASK 0xff +#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13_MASK 0xff00 +#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14_MASK 0xff0000 +#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15_MASK 0xff000000 +#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15__SHIFT 0x18 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f +#define RLC_GPM_VMID_THREAD2__RLC_VMID_MASK 0xf +#define RLC_GPM_VMID_THREAD2__RLC_VMID__SHIFT 0x0 +#define RLC_GPM_VMID_THREAD2__RESERVED0_MASK 0xf0 +#define RLC_GPM_VMID_THREAD2__RESERVED0__SHIFT 0x4 +#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID_MASK 0x700 +#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID__SHIFT 0x8 +#define RLC_GPM_VMID_THREAD2__RESERVED1_MASK 0xfffff800 +#define RLC_GPM_VMID_THREAD2__RESERVED1__SHIFT 0xb +#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0xfff +#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xfffff000 +#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc +#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x1ff +#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00 +#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9 +#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xffffffff +#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x1 +#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xfffffffe +#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x1 +#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 +#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xfffffffe +#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x1 +#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0xfe +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x100 +#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0xe00 +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x1000 +#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xffffe000 +#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x1 +#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0xfe +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x100 +#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8 +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0xe00 +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9 +#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x1000 +#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xffffe000 +#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd +#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xffffffff +#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0xffff +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 +#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7fff0000 +#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000 +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f +#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff +#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xffffffff +#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0 +#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xffffffff +#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_0__DATA_MASK 0xffffffff +#define RLC_GPU_IOV_SCH_0__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xffffffff +#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xffffffff +#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_3__DATA_MASK 0xffffffff +#define RLC_GPU_IOV_SCH_3__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_INT__interrupt_MASK 0xffffffff +#define RLC_GPU_IOV_SCH_INT__interrupt__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40 +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1 +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800 +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000 +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000 +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000 +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000 +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800 +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000 +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000 +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000 +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000 +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe +#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f +#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 +#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40 +#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1 +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000 +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 +#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff +#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 +#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000 +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc +#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000 +#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe +#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000 +#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 +#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff +#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000 +#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff +#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000 +#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 +#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1 +#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2 +#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1 +#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4 +#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8 +#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3 +#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10 +#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20 +#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5 +#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40 +#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 +#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1 +#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2 +#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1 +#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4 +#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8 +#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3 +#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10 +#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20 +#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5 +#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff +#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 +#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00 +#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 +#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000 +#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 +#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000 +#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 +#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff +#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0 +#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00 +#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8 +#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000 +#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10 +#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000 +#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18 +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0xf80 +#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x1f000 +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x3e0000 +#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x7c00000 +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK 0xf80 +#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT 0x7 +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x1f000 +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK 0x3e0000 +#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT 0x11 +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x7c00000 +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 +#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x1fffe +#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1 +#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3 +#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80 +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100 +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000 +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000 +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 +#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff +#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 +#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200 +#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 +#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff +#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff +#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff +#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff +#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4 +#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1 +#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x1 +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x4 +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000 +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x3 +#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 +#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0xc +#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 +#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x30 +#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 +#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1 +#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000 +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000 +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b +#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1 +#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0 +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1 +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0 +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4 +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00 +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000 +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18 +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000 +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19 +#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000 +#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f +#define SPI_DEBUG_READ__DATA_MASK 0xffffff +#define SPI_DEBUG_READ__DATA__SHIFT 0x0 +#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0_MASK 0x1 +#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0__SHIFT 0x0 +#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1_MASK 0x2 +#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1__SHIFT 0x1 +#define SPI_DSM_CNTL__SPI_Enable_Single_Write_MASK 0x4 +#define SPI_DSM_CNTL__SPI_Enable_Single_Write__SHIFT 0x2 +#define SPI_DSM_CNTL__UNUSED_MASK 0xfffffff8 +#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3 +#define SPI_EDC_CNT__SED_MASK 0xff +#define SPI_EDC_CNT__SED__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf +#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc +#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000 +#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100 +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 +#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1 +#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0 +#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2 +#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1 +#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4 +#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2 +#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8 +#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3 +#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10 +#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4 +#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20 +#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5 +#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40 +#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6 +#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80 +#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7 +#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100 +#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8 +#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200 +#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9 +#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400 +#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa +#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800 +#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb +#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000 +#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc +#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000 +#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd +#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000 +#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe +#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000 +#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000 +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10 +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000 +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11 +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000 +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12 +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000 +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13 +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000 +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14 +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000 +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15 +#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000 +#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16 +#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000 +#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0xf +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0xf0 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0 +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 +#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000 +#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc +#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000 +#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 +#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000 +#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000 +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 +#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000 +#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 +#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000 +#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 +#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00 +#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 +#define CGTS_RD_REG__READ_DATA_MASK 0x3fff +#define CGTS_RD_REG__READ_DATA__SHIFT 0x0 +#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 +#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000 +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000 +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000 +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000 +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000 +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 +#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000 +#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19 +#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000 +#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000 +#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000 +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000 +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000 +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 +#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10 +#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff +#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0 +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000 +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1 +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0 +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2 +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1 +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4 +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2 +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8 +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3 +#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10 +#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14 +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000 +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15 +#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x400000 +#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0x16 +#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1 +#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 +#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff +#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff +#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff +#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 +#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000 +#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 +#define BCI_DEBUG_READ__DATA_MASK 0xffffff +#define BCI_DEBUG_READ__DATA__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000 +#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000 +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000 +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000 +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000 +#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000 +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000 +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000 +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd +#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x1000000 +#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00 +#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000 +#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000 +#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000 +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xfc000000 +#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a +#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00 +#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000 +#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14 +#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000 +#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000 +#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000 +#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000 +#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00 +#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000 +#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xfc000000 +#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a +#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000 +#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000 +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100 +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0xfc00 +#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa +#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000 +#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000 +#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000 +#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xfc000000 +#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a +#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 +#define SQ_CONFIG__UNUSED_MASK 0xff +#define SQ_CONFIG__UNUSED__SHIFT 0x0 +#define SQ_CONFIG__DEBUG_EN_MASK 0x100 +#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8 +#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x200 +#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9 +#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x400 +#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000 +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000 +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000 +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000 +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf +#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x10000 +#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 +#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x20000 +#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x40000 +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x180000 +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 +#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x1e00000 +#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 +#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3 +#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 +#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc +#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 +#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30 +#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 +#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40 +#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 +#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80 +#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 +#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100 +#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 +#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200 +#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 +#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400 +#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa +#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800 +#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb +#define SQC_CONFIG__EVICT_LRU_MASK 0x3000 +#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc +#define SQC_CONFIG__FORCE_2_BANK_MASK 0x4000 +#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe +#define SQC_CONFIG__FORCE_1_BANK_MASK 0x8000 +#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf +#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0xff0000 +#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 +#define SQC_CACHES__TARGET_INST_MASK 0x1 +#define SQC_CACHES__TARGET_INST__SHIFT 0x0 +#define SQC_CACHES__TARGET_DATA_MASK 0x2 +#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 +#define SQC_CACHES__INVALIDATE_MASK 0x4 +#define SQC_CACHES__INVALIDATE__SHIFT 0x2 +#define SQC_CACHES__WRITEBACK_MASK 0x8 +#define SQC_CACHES__WRITEBACK__SHIFT 0x3 +#define SQC_CACHES__VOL_MASK 0x10 +#define SQC_CACHES__VOL__SHIFT 0x4 +#define SQC_CACHES__COMPLETE_MASK 0x10000 +#define SQC_CACHES__COMPLETE__SHIFT 0x10 +#define SQC_WRITEBACK__DWB_MASK 0x1 +#define SQC_WRITEBACK__DWB__SHIFT 0x0 +#define SQC_WRITEBACK__DIRTY_MASK 0x2 +#define SQC_WRITEBACK__DIRTY__SHIFT 0x1 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA_MASK 0x3 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA__SHIFT 0x0 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA_MASK 0x4 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA__SHIFT 0x2 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB_MASK 0x18 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB__SHIFT 0x3 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB_MASK 0x20 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB__SHIFT 0x5 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC_MASK 0xc0 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC__SHIFT 0x6 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC_MASK 0x100 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC__SHIFT 0x8 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD_MASK 0x600 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD__SHIFT 0x9 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD_MASK 0x800 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD__SHIFT 0xb +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1_MASK 0x3000 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1__SHIFT 0xc +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1_MASK 0x4000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1__SHIFT 0xe +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA_MASK 0x18000 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA__SHIFT 0xf +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA_MASK 0x20000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA__SHIFT 0x11 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB_MASK 0xc0000 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB__SHIFT 0x12 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB_MASK 0x100000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT 0x14 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC_MASK 0x600000 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC__SHIFT 0x15 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC_MASK 0x800000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC__SHIFT 0x17 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD_MASK 0x3000000 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD__SHIFT 0x18 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD_MASK 0x4000000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD__SHIFT 0x1a +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1_MASK 0x18000000 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1__SHIFT 0x1b +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1_MASK 0x20000000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d +#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f +#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 +#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380 +#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 +#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00 +#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa +#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f +#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 +#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00 +#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 +#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000 +#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c +#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000 +#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d +#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000 +#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e +#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000 +#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000 +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x2 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x4 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x8 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x100 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x200 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x400 +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x10000 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x20000 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x40000 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x80000 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x100000 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x200000 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x1000000 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x2000000 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x4000000 +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6 +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 +#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10 +#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6 +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 +#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10 +#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 +#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff +#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 +#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1 +#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1 +#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2 +#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 +#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4 +#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8 +#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 +#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10 +#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20 +#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 +#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40 +#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00 +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000 +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd +#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff +#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000 +#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 +#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 +#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 +#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 +#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 +#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 +#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 +#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c +#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 +#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 +#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 +#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 +#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 +#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 +#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 +#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c +#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000 +#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000 +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000 +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff +#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 +#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000 +#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 +#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000 +#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000 +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f +#define SQ_TIME_HI__TIME_MASK 0xffffffff +#define SQ_TIME_HI__TIME__SHIFT 0x0 +#define SQ_TIME_LO__TIME_MASK 0xffffffff +#define SQ_TIME_LO__TIME__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff +#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf +#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff +#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f +#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20 +#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80 +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 +#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00 +#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000 +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000 +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000 +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf +#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7 +#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 +#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38 +#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 +#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0 +#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 +#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00 +#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 +#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000 +#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc +#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000 +#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf +#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000 +#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 +#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000 +#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000 +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000 +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 +#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000 +#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000 +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b +#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000 +#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000 +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e +#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000 +#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000 +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffffffff +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000 +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff +#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000 +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 +#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000 +#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d +#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000 +#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e +#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000 +#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f +#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff +#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7 +#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 +#define SQ_LB_CTR_CTRL__START_MASK 0x1 +#define SQ_LB_CTR_CTRL__START__SHIFT 0x0 +#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2 +#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 +#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4 +#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 +#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff +#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0 +#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff +#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0 +#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff +#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0 +#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff +#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0 +#define SQC_EDC_CNT__INST_SEC_MASK 0xff +#define SQC_EDC_CNT__INST_SEC__SHIFT 0x0 +#define SQC_EDC_CNT__INST_DED_MASK 0xff00 +#define SQC_EDC_CNT__INST_DED__SHIFT 0x8 +#define SQC_EDC_CNT__DATA_SEC_MASK 0xff0000 +#define SQC_EDC_CNT__DATA_SEC__SHIFT 0x10 +#define SQC_EDC_CNT__DATA_DED_MASK 0xff000000 +#define SQC_EDC_CNT__DATA_DED__SHIFT 0x18 +#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0xff +#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 +#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0xff00 +#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 +#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000 +#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 +#define SQ_EDC_DED_CNT__LDS_DED_MASK 0xff +#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 +#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0xff00 +#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 +#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0xff0000 +#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 +#define SQ_EDC_INFO__WAVE_ID_MASK 0xf +#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 +#define SQ_EDC_INFO__SIMD_ID_MASK 0x30 +#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 +#define SQ_EDC_INFO__SOURCE_MASK 0x1c0 +#define SQ_EDC_INFO__SOURCE__SHIFT 0x6 +#define SQ_EDC_INFO__VM_ID_MASK 0x1e00 +#define SQ_EDC_INFO__VM_ID__SHIFT 0x9 +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000 +#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000 +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000 +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7 +#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00 +#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000 +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000 +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf +#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000 +#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13 +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000 +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000 +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 +#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000 +#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18 +#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000 +#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19 +#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000 +#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a +#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000 +#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b +#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000 +#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00 +#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000 +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000 +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000 +#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e +#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff +#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000 +#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe +#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000 +#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000 +#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f +#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7 +#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00 +#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000 +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000 +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 +#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000 +#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000 +#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19 +#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000 +#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000 +#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b +#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000 +#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff +#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000 +#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000 +#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000 +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000 +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x200000 +#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 +#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x400000 +#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 +#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x800000 +#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 +#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0xf000000 +#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 +#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xf0000000 +#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xffffffff +#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7 +#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38 +#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 +#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0 +#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00 +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000 +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000 +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000 +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000 +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000 +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000 +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000 +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000 +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000 +#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000 +#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f +#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff +#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000 +#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc +#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000 +#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000 +#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff +#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000 +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000 +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 +#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000 +#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000 +#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000 +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000 +#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000 +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e +#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000 +#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e +#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff +#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 +#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff +#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 +#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0xff +#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 +#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x1000 +#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc +#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x2000 +#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd +#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x4000 +#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe +#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x8000 +#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf +#define SQ_IND_INDEX__WAVE_ID_MASK 0xf +#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 +#define SQ_IND_INDEX__SIMD_ID_MASK 0x30 +#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 +#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0 +#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 +#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000 +#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc +#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000 +#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd +#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000 +#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe +#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000 +#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf +#define SQ_IND_INDEX__INDEX_MASK 0xffff0000 +#define SQ_IND_INDEX__INDEX__SHIFT 0x10 +#define SQ_CMD__CMD_MASK 0x7 +#define SQ_CMD__CMD__SHIFT 0x0 +#define SQ_CMD__MODE_MASK 0x70 +#define SQ_CMD__MODE__SHIFT 0x4 +#define SQ_CMD__CHECK_VMID_MASK 0x80 +#define SQ_CMD__CHECK_VMID__SHIFT 0x7 +#define SQ_CMD__DATA_MASK 0x700 +#define SQ_CMD__DATA__SHIFT 0x8 +#define SQ_CMD__WAVE_ID_MASK 0xf0000 +#define SQ_CMD__WAVE_ID__SHIFT 0x10 +#define SQ_CMD__SIMD_ID_MASK 0x300000 +#define SQ_CMD__SIMD_ID__SHIFT 0x14 +#define SQ_CMD__QUEUE_ID_MASK 0x7000000 +#define SQ_CMD__QUEUE_ID__SHIFT 0x18 +#define SQ_CMD__VM_ID_MASK 0xf0000000 +#define SQ_CMD__VM_ID__SHIFT 0x1c +#define SQ_IND_DATA__DATA_MASK 0xffffffff +#define SQ_IND_DATA__DATA__SHIFT 0x0 +#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff +#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff +#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf +#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0 +#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0 +#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4 +#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff +#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 +#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff +#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 +#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff +#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 +#define SQ_WAVE_PC_HI__PC_HI_MASK 0xff +#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 +#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7 +#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 +#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8 +#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10 +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0 +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 +#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300 +#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 +#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00 +#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa +#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0xf0000 +#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 +#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0xf00000 +#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x14 +#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x3000000 +#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 +#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x4000000 +#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a +#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000 +#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b +#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000 +#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000 +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e +#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x1 +#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 +#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x2 +#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 +#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x4 +#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 +#define SQ_WAVE_IB_DBG1__XCNT_MASK 0xf0 +#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 +#define SQ_WAVE_IB_DBG1__QCNT_MASK 0xf00 +#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0x8 +#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff +#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 +#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff +#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 +#define SQ_WAVE_STATUS__SCC_MASK 0x1 +#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 +#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6 +#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 +#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x18 +#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 +#define SQ_WAVE_STATUS__PRIV_MASK 0x20 +#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 +#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40 +#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 +#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80 +#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 +#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100 +#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 +#define SQ_WAVE_STATUS__EXECZ_MASK 0x200 +#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 +#define SQ_WAVE_STATUS__VCCZ_MASK 0x400 +#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa +#define SQ_WAVE_STATUS__IN_TG_MASK 0x800 +#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb +#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000 +#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc +#define SQ_WAVE_STATUS__HALT_MASK 0x2000 +#define SQ_WAVE_STATUS__HALT__SHIFT 0xd +#define SQ_WAVE_STATUS__TRAP_MASK 0x4000 +#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe +#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000 +#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf +#define SQ_WAVE_STATUS__VALID_MASK 0x10000 +#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 +#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000 +#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 +#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000 +#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 +#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000 +#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 +#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000 +#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14 +#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000 +#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15 +#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x400000 +#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 +#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000 +#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17 +#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000 +#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b +#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf +#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 +#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0 +#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 +#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100 +#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 +#define SQ_WAVE_MODE__IEEE_MASK 0x200 +#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 +#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400 +#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa +#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800 +#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb +#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000 +#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc +#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x8000000 +#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b +#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000 +#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c +#define SQ_WAVE_MODE__CSP_MASK 0xe0000000 +#define SQ_WAVE_MODE__CSP__SHIFT 0x1d +#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff +#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 +#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x400 +#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000 +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 +#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000 +#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d +#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf +#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30 +#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 +#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0 +#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 +#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00 +#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000 +#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc +#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000 +#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd +#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000 +#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000 +#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 +#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000 +#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 +#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000 +#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b +#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000 +#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000 +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000 +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 +#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff +#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc +#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf +#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 +#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70 +#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 +#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00 +#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 +#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000 +#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc +#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x8000 +#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf +#define SQ_WAVE_IB_STS__RCNT_MASK 0xf0000 +#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 +#define SQ_WAVE_M0__M0_MASK 0xffffffff +#define SQ_WAVE_M0__M0__SHIFT 0x0 +#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff +#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff +#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff +#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff +#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1 +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x3f0 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4 +#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1 +#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 +#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff +#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 +#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff +#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 +#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000 +#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 +#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff +#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0 +#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff +#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0 +#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x3 +#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 +#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x4 +#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x2 +#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x18 +#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 +#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0xe0 +#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x5 +#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x700 +#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x8 +#define SH_MEM_CONFIG__APE1_ATC_MASK 0x800 +#define SH_MEM_CONFIG__APE1_ATC__SHIFT 0xb +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0 +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600 +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf800 +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00 +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0 +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000 +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000 +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00 +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0 +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00 +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60 +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 +#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xffffffff +#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 +#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0xffff +#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 +#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x4000000 +#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a +#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x8000000 +#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b +#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000 +#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c +#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000 +#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f +#define SQC_GATCL1_CNTL__RESERVED_MASK 0x3ffff +#define SQC_GATCL1_CNTL__RESERVED__SHIFT 0x0 +#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID_MASK 0x40000 +#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID__SHIFT 0x12 +#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS_MASK 0x80000 +#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS__SHIFT 0x13 +#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER_MASK 0x100000 +#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT 0x14 +#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x600000 +#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x15 +#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0x1800000 +#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x17 +#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID_MASK 0x2000000 +#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS_MASK 0x4000000 +#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS__SHIFT 0x1a +#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER_MASK 0x8000000 +#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER__SHIFT 0x1b +#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000 +#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000 +#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC_MASK 0xff +#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC__SHIFT 0x0 +#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC_MASK 0xff0000 +#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC__SHIFT 0x10 +#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000 +#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000 +#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2 +#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 +#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8 +#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3 +#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10 +#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20 +#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5 +#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40 +#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6 +#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80 +#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7 +#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000 +#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000 +#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff +#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100 +#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200 +#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9 +#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00 +#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa +#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000 +#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe +#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000 +#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12 +#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000 +#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14 +#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000 +#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000 +#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a +#define SQ_SOP2__SSRC0_MASK 0xff +#define SQ_SOP2__SSRC0__SHIFT 0x0 +#define SQ_SOP2__SSRC1_MASK 0xff00 +#define SQ_SOP2__SSRC1__SHIFT 0x8 +#define SQ_SOP2__SDST_MASK 0x7f0000 +#define SQ_SOP2__SDST__SHIFT 0x10 +#define SQ_SOP2__OP_MASK 0x3f800000 +#define SQ_SOP2__OP__SHIFT 0x17 +#define SQ_SOP2__ENCODING_MASK 0xc0000000 +#define SQ_SOP2__ENCODING__SHIFT 0x1e +#define SQ_VOP1__SRC0_MASK 0x1ff +#define SQ_VOP1__SRC0__SHIFT 0x0 +#define SQ_VOP1__OP_MASK 0x1fe00 +#define SQ_VOP1__OP__SHIFT 0x9 +#define SQ_VOP1__VDST_MASK 0x1fe0000 +#define SQ_VOP1__VDST__SHIFT 0x11 +#define SQ_VOP1__ENCODING_MASK 0xfe000000 +#define SQ_VOP1__ENCODING__SHIFT 0x19 +#define SQ_MTBUF_1__VADDR_MASK 0xff +#define SQ_MTBUF_1__VADDR__SHIFT 0x0 +#define SQ_MTBUF_1__VDATA_MASK 0xff00 +#define SQ_MTBUF_1__VDATA__SHIFT 0x8 +#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000 +#define SQ_MTBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MTBUF_1__SLC_MASK 0x400000 +#define SQ_MTBUF_1__SLC__SHIFT 0x16 +#define SQ_MTBUF_1__TFE_MASK 0x800000 +#define SQ_MTBUF_1__TFE__SHIFT 0x17 +#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000 +#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_EXP_1__VSRC0_MASK 0xff +#define SQ_EXP_1__VSRC0__SHIFT 0x0 +#define SQ_EXP_1__VSRC1_MASK 0xff00 +#define SQ_EXP_1__VSRC1__SHIFT 0x8 +#define SQ_EXP_1__VSRC2_MASK 0xff0000 +#define SQ_EXP_1__VSRC2__SHIFT 0x10 +#define SQ_EXP_1__VSRC3_MASK 0xff000000 +#define SQ_EXP_1__VSRC3__SHIFT 0x18 +#define SQ_MUBUF_1__VADDR_MASK 0xff +#define SQ_MUBUF_1__VADDR__SHIFT 0x0 +#define SQ_MUBUF_1__VDATA_MASK 0xff00 +#define SQ_MUBUF_1__VDATA__SHIFT 0x8 +#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000 +#define SQ_MUBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MUBUF_1__TFE_MASK 0x800000 +#define SQ_MUBUF_1__TFE__SHIFT 0x17 +#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000 +#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_SMEM_1__OFFSET_MASK 0xfffff +#define SQ_SMEM_1__OFFSET__SHIFT 0x0 +#define SQ_INST__ENCODING_MASK 0xffffffff +#define SQ_INST__ENCODING__SHIFT 0x0 +#define SQ_EXP_0__EN_MASK 0xf +#define SQ_EXP_0__EN__SHIFT 0x0 +#define SQ_EXP_0__TGT_MASK 0x3f0 +#define SQ_EXP_0__TGT__SHIFT 0x4 +#define SQ_EXP_0__COMPR_MASK 0x400 +#define SQ_EXP_0__COMPR__SHIFT 0xa +#define SQ_EXP_0__DONE_MASK 0x800 +#define SQ_EXP_0__DONE__SHIFT 0xb +#define SQ_EXP_0__VM_MASK 0x1000 +#define SQ_EXP_0__VM__SHIFT 0xc +#define SQ_EXP_0__ENCODING_MASK 0xfc000000 +#define SQ_EXP_0__ENCODING__SHIFT 0x1a +#define SQ_MUBUF_0__OFFSET_MASK 0xfff +#define SQ_MUBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MUBUF_0__OFFEN_MASK 0x1000 +#define SQ_MUBUF_0__OFFEN__SHIFT 0xc +#define SQ_MUBUF_0__IDXEN_MASK 0x2000 +#define SQ_MUBUF_0__IDXEN__SHIFT 0xd +#define SQ_MUBUF_0__GLC_MASK 0x4000 +#define SQ_MUBUF_0__GLC__SHIFT 0xe +#define SQ_MUBUF_0__LDS_MASK 0x10000 +#define SQ_MUBUF_0__LDS__SHIFT 0x10 +#define SQ_MUBUF_0__SLC_MASK 0x20000 +#define SQ_MUBUF_0__SLC__SHIFT 0x11 +#define SQ_MUBUF_0__OP_MASK 0x1fc0000 +#define SQ_MUBUF_0__OP__SHIFT 0x12 +#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000 +#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a +#define SQ_VOP_SDWA__SRC0_MASK 0xff +#define SQ_VOP_SDWA__SRC0__SHIFT 0x0 +#define SQ_VOP_SDWA__DST_SEL_MASK 0x700 +#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 +#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x1800 +#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb +#define SQ_VOP_SDWA__CLAMP_MASK 0x2000 +#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd +#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x70000 +#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 +#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x80000 +#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 +#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x100000 +#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x200000 +#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x7000000 +#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 +#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x8000000 +#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b +#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000 +#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c +#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000 +#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d +#define SQ_VOP3_0__VDST_MASK 0xff +#define SQ_VOP3_0__VDST__SHIFT 0x0 +#define SQ_VOP3_0__ABS_MASK 0x700 +#define SQ_VOP3_0__ABS__SHIFT 0x8 +#define SQ_VOP3_0__CLAMP_MASK 0x8000 +#define SQ_VOP3_0__CLAMP__SHIFT 0xf +#define SQ_VOP3_0__OP_MASK 0x3ff0000 +#define SQ_VOP3_0__OP__SHIFT 0x10 +#define SQ_VOP3_0__ENCODING_MASK 0xfc000000 +#define SQ_VOP3_0__ENCODING__SHIFT 0x1a +#define SQ_VOP2__SRC0_MASK 0x1ff +#define SQ_VOP2__SRC0__SHIFT 0x0 +#define SQ_VOP2__VSRC1_MASK 0x1fe00 +#define SQ_VOP2__VSRC1__SHIFT 0x9 +#define SQ_VOP2__VDST_MASK 0x1fe0000 +#define SQ_VOP2__VDST__SHIFT 0x11 +#define SQ_VOP2__OP_MASK 0x7e000000 +#define SQ_VOP2__OP__SHIFT 0x19 +#define SQ_VOP2__ENCODING_MASK 0x80000000 +#define SQ_VOP2__ENCODING__SHIFT 0x1f +#define SQ_MTBUF_0__OFFSET_MASK 0xfff +#define SQ_MTBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MTBUF_0__OFFEN_MASK 0x1000 +#define SQ_MTBUF_0__OFFEN__SHIFT 0xc +#define SQ_MTBUF_0__IDXEN_MASK 0x2000 +#define SQ_MTBUF_0__IDXEN__SHIFT 0xd +#define SQ_MTBUF_0__GLC_MASK 0x4000 +#define SQ_MTBUF_0__GLC__SHIFT 0xe +#define SQ_MTBUF_0__OP_MASK 0x78000 +#define SQ_MTBUF_0__OP__SHIFT 0xf +#define SQ_MTBUF_0__DFMT_MASK 0x780000 +#define SQ_MTBUF_0__DFMT__SHIFT 0x13 +#define SQ_MTBUF_0__NFMT_MASK 0x3800000 +#define SQ_MTBUF_0__NFMT__SHIFT 0x17 +#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000 +#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a +#define SQ_SOPP__SIMM16_MASK 0xffff +#define SQ_SOPP__SIMM16__SHIFT 0x0 +#define SQ_SOPP__OP_MASK 0x7f0000 +#define SQ_SOPP__OP__SHIFT 0x10 +#define SQ_SOPP__ENCODING_MASK 0xff800000 +#define SQ_SOPP__ENCODING__SHIFT 0x17 +#define SQ_FLAT_0__GLC_MASK 0x10000 +#define SQ_FLAT_0__GLC__SHIFT 0x10 +#define SQ_FLAT_0__SLC_MASK 0x20000 +#define SQ_FLAT_0__SLC__SHIFT 0x11 +#define SQ_FLAT_0__OP_MASK 0x1fc0000 +#define SQ_FLAT_0__OP__SHIFT 0x12 +#define SQ_FLAT_0__ENCODING_MASK 0xfc000000 +#define SQ_FLAT_0__ENCODING__SHIFT 0x1a +#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff +#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 +#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00 +#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 +#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x8000 +#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf +#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3ff0000 +#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 +#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000 +#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a +#define SQ_MIMG_1__VADDR_MASK 0xff +#define SQ_MIMG_1__VADDR__SHIFT 0x0 +#define SQ_MIMG_1__VDATA_MASK 0xff00 +#define SQ_MIMG_1__VDATA__SHIFT 0x8 +#define SQ_MIMG_1__SRSRC_MASK 0x1f0000 +#define SQ_MIMG_1__SRSRC__SHIFT 0x10 +#define SQ_MIMG_1__SSAMP_MASK 0x3e00000 +#define SQ_MIMG_1__SSAMP__SHIFT 0x15 +#define SQ_MIMG_1__D16_MASK 0x80000000 +#define SQ_MIMG_1__D16__SHIFT 0x1f +#define SQ_SOP1__SSRC0_MASK 0xff +#define SQ_SOP1__SSRC0__SHIFT 0x0 +#define SQ_SOP1__OP_MASK 0xff00 +#define SQ_SOP1__OP__SHIFT 0x8 +#define SQ_SOP1__SDST_MASK 0x7f0000 +#define SQ_SOP1__SDST__SHIFT 0x10 +#define SQ_SOP1__ENCODING_MASK 0xff800000 +#define SQ_SOP1__ENCODING__SHIFT 0x17 +#define SQ_SOPC__SSRC0_MASK 0xff +#define SQ_SOPC__SSRC0__SHIFT 0x0 +#define SQ_SOPC__SSRC1_MASK 0xff00 +#define SQ_SOPC__SSRC1__SHIFT 0x8 +#define SQ_SOPC__OP_MASK 0x7f0000 +#define SQ_SOPC__OP__SHIFT 0x10 +#define SQ_SOPC__ENCODING_MASK 0xff800000 +#define SQ_SOPC__ENCODING__SHIFT 0x17 +#define SQ_FLAT_1__ADDR_MASK 0xff +#define SQ_FLAT_1__ADDR__SHIFT 0x0 +#define SQ_FLAT_1__DATA_MASK 0xff00 +#define SQ_FLAT_1__DATA__SHIFT 0x8 +#define SQ_FLAT_1__TFE_MASK 0x800000 +#define SQ_FLAT_1__TFE__SHIFT 0x17 +#define SQ_FLAT_1__VDST_MASK 0xff000000 +#define SQ_FLAT_1__VDST__SHIFT 0x18 +#define SQ_DS_1__ADDR_MASK 0xff +#define SQ_DS_1__ADDR__SHIFT 0x0 +#define SQ_DS_1__DATA0_MASK 0xff00 +#define SQ_DS_1__DATA0__SHIFT 0x8 +#define SQ_DS_1__DATA1_MASK 0xff0000 +#define SQ_DS_1__DATA1__SHIFT 0x10 +#define SQ_DS_1__VDST_MASK 0xff000000 +#define SQ_DS_1__VDST__SHIFT 0x18 +#define SQ_VOP3_1__SRC0_MASK 0x1ff +#define SQ_VOP3_1__SRC0__SHIFT 0x0 +#define SQ_VOP3_1__SRC1_MASK 0x3fe00 +#define SQ_VOP3_1__SRC1__SHIFT 0x9 +#define SQ_VOP3_1__SRC2_MASK 0x7fc0000 +#define SQ_VOP3_1__SRC2__SHIFT 0x12 +#define SQ_VOP3_1__OMOD_MASK 0x18000000 +#define SQ_VOP3_1__OMOD__SHIFT 0x1b +#define SQ_VOP3_1__NEG_MASK 0xe0000000 +#define SQ_VOP3_1__NEG__SHIFT 0x1d +#define SQ_SMEM_0__SBASE_MASK 0x3f +#define SQ_SMEM_0__SBASE__SHIFT 0x0 +#define SQ_SMEM_0__SDATA_MASK 0x1fc0 +#define SQ_SMEM_0__SDATA__SHIFT 0x6 +#define SQ_SMEM_0__GLC_MASK 0x10000 +#define SQ_SMEM_0__GLC__SHIFT 0x10 +#define SQ_SMEM_0__IMM_MASK 0x20000 +#define SQ_SMEM_0__IMM__SHIFT 0x11 +#define SQ_SMEM_0__OP_MASK 0x3fc0000 +#define SQ_SMEM_0__OP__SHIFT 0x12 +#define SQ_SMEM_0__ENCODING_MASK 0xfc000000 +#define SQ_SMEM_0__ENCODING__SHIFT 0x1a +#define SQ_MIMG_0__DMASK_MASK 0xf00 +#define SQ_MIMG_0__DMASK__SHIFT 0x8 +#define SQ_MIMG_0__UNORM_MASK 0x1000 +#define SQ_MIMG_0__UNORM__SHIFT 0xc +#define SQ_MIMG_0__GLC_MASK 0x2000 +#define SQ_MIMG_0__GLC__SHIFT 0xd +#define SQ_MIMG_0__DA_MASK 0x4000 +#define SQ_MIMG_0__DA__SHIFT 0xe +#define SQ_MIMG_0__R128_MASK 0x8000 +#define SQ_MIMG_0__R128__SHIFT 0xf +#define SQ_MIMG_0__TFE_MASK 0x10000 +#define SQ_MIMG_0__TFE__SHIFT 0x10 +#define SQ_MIMG_0__LWE_MASK 0x20000 +#define SQ_MIMG_0__LWE__SHIFT 0x11 +#define SQ_MIMG_0__OP_MASK 0x1fc0000 +#define SQ_MIMG_0__OP__SHIFT 0x12 +#define SQ_MIMG_0__SLC_MASK 0x2000000 +#define SQ_MIMG_0__SLC__SHIFT 0x19 +#define SQ_MIMG_0__ENCODING_MASK 0xfc000000 +#define SQ_MIMG_0__ENCODING__SHIFT 0x1a +#define SQ_SOPK__SIMM16_MASK 0xffff +#define SQ_SOPK__SIMM16__SHIFT 0x0 +#define SQ_SOPK__SDST_MASK 0x7f0000 +#define SQ_SOPK__SDST__SHIFT 0x10 +#define SQ_SOPK__OP_MASK 0xf800000 +#define SQ_SOPK__OP__SHIFT 0x17 +#define SQ_SOPK__ENCODING_MASK 0xf0000000 +#define SQ_SOPK__ENCODING__SHIFT 0x1c +#define SQ_DS_0__OFFSET0_MASK 0xff +#define SQ_DS_0__OFFSET0__SHIFT 0x0 +#define SQ_DS_0__OFFSET1_MASK 0xff00 +#define SQ_DS_0__OFFSET1__SHIFT 0x8 +#define SQ_DS_0__GDS_MASK 0x10000 +#define SQ_DS_0__GDS__SHIFT 0x10 +#define SQ_DS_0__OP_MASK 0x1fe0000 +#define SQ_DS_0__OP__SHIFT 0x11 +#define SQ_DS_0__ENCODING_MASK 0xfc000000 +#define SQ_DS_0__ENCODING__SHIFT 0x1a +#define SQ_VOP_DPP__SRC0_MASK 0xff +#define SQ_VOP_DPP__SRC0__SHIFT 0x0 +#define SQ_VOP_DPP__DPP_CTRL_MASK 0x1ff00 +#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 +#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x80000 +#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 +#define SQ_VOP_DPP__SRC0_NEG_MASK 0x100000 +#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_DPP__SRC0_ABS_MASK 0x200000 +#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_DPP__SRC1_NEG_MASK 0x400000 +#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 +#define SQ_VOP_DPP__SRC1_ABS_MASK 0x800000 +#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 +#define SQ_VOP_DPP__BANK_MASK_MASK 0xf000000 +#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 +#define SQ_VOP_DPP__ROW_MASK_MASK 0xf0000000 +#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c +#define SQ_VOPC__SRC0_MASK 0x1ff +#define SQ_VOPC__SRC0__SHIFT 0x0 +#define SQ_VOPC__VSRC1_MASK 0x1fe00 +#define SQ_VOPC__VSRC1__SHIFT 0x9 +#define SQ_VOPC__OP_MASK 0x1fe0000 +#define SQ_VOPC__OP__SHIFT 0x11 +#define SQ_VOPC__ENCODING_MASK 0xfe000000 +#define SQ_VOPC__ENCODING__SHIFT 0x19 +#define SQ_VINTRP__VSRC_MASK 0xff +#define SQ_VINTRP__VSRC__SHIFT 0x0 +#define SQ_VINTRP__ATTRCHAN_MASK 0x300 +#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 +#define SQ_VINTRP__ATTR_MASK 0xfc00 +#define SQ_VINTRP__ATTR__SHIFT 0xa +#define SQ_VINTRP__OP_MASK 0x30000 +#define SQ_VINTRP__OP__SHIFT 0x10 +#define SQ_VINTRP__VDST_MASK 0x3fc0000 +#define SQ_VINTRP__VDST__SHIFT 0x12 +#define SQ_VINTRP__ENCODING_MASK 0xfc000000 +#define SQ_VINTRP__ENCODING__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f +#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1 +#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0 +#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2 +#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4 +#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10 +#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20 +#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80 +#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100 +#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400 +#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800 +#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000 +#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000 +#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000 +#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a +#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000 +#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b +#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000 +#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c +#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000 +#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d +#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000 +#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000 +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f +#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1 +#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2 +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1 +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4 +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2 +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10 +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4 +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20 +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5 +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80 +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7 +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100 +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8 +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400 +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800 +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000 +#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000 +#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12 +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000 +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000 +#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15 +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000 +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000 +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000 +#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000 +#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 +#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80 +#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_CTRL__CACHE_SIZE_MASK 0x3 +#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 +#define TCC_CTRL__RATE_MASK 0xc +#define TCC_CTRL__RATE__SHIFT 0x2 +#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0 +#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 +#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00 +#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 +#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000 +#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc +#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000 +#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 +#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000 +#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14 +#define TCC_CTRL__MDC_SIZE_MASK 0x3000000 +#define TCC_CTRL__MDC_SIZE__SHIFT 0x18 +#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0xc000000 +#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a +#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xf0000000 +#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c +#define TCC_EDC_CNT__SEC_COUNT_MASK 0xff +#define TCC_EDC_CNT__SEC_COUNT__SHIFT 0x0 +#define TCC_EDC_CNT__DED_COUNT_MASK 0xff0000 +#define TCC_EDC_CNT__DED_COUNT__SHIFT 0x10 +#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1 +#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 +#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2 +#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 +#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x2 +#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1 +#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3 +#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4 +#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf +#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf +#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf +#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff +#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff +#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3 +#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 +#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30 +#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 +#define TD_CNTL__PAD_STALL_EN_MASK 0x100 +#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 +#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600 +#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 +#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800 +#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb +#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000 +#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf +#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000 +#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 +#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000 +#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 +#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000 +#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 +#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000 +#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 +#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x200000 +#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 +#define TD_STATUS__BUSY_MASK 0x80000000 +#define TD_STATUS__BUSY__SHIFT 0x1f +#define TD_DEBUG_INDEX__INDEX_MASK 0x1f +#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0 +#define TD_DEBUG_DATA__DATA_MASK 0xffffffff +#define TD_DEBUG_DATA__DATA__SHIFT 0x0 +#define TD_DSM_CNTL__FORCE_SEDB_0_MASK 0x1 +#define TD_DSM_CNTL__FORCE_SEDB_0__SHIFT 0x0 +#define TD_DSM_CNTL__FORCE_SEDB_1_MASK 0x2 +#define TD_DSM_CNTL__FORCE_SEDB_1__SHIFT 0x1 +#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK 0x4 +#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT 0x2 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff +#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_SCRATCH__SCRATCH_MASK 0xffffffff +#define TD_SCRATCH__SCRATCH__SHIFT 0x0 +#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000 +#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd +#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000 +#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 +#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000 +#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1 +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 +#define TA_CNTL_AUX__RESERVED_MASK 0xe +#define TA_CNTL_AUX__RESERVED__SHIFT 0x1 +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000 +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 +#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x20000 +#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 +#define TA_CNTL_AUX__ANISO_TAP_MASK 0x40000 +#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 +#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x80000 +#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13 +#define TA_RESERVED_010C__Unused_MASK 0xffffffff +#define TA_RESERVED_010C__Unused__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff +#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000 +#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc +#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000 +#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd +#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000 +#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe +#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000 +#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 +#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000 +#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 +#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000 +#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 +#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000 +#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 +#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000 +#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 +#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000 +#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 +#define TA_STATUS__IN_BUSY_MASK 0x1000000 +#define TA_STATUS__IN_BUSY__SHIFT 0x18 +#define TA_STATUS__FG_BUSY_MASK 0x2000000 +#define TA_STATUS__FG_BUSY__SHIFT 0x19 +#define TA_STATUS__LA_BUSY_MASK 0x4000000 +#define TA_STATUS__LA_BUSY__SHIFT 0x1a +#define TA_STATUS__FL_BUSY_MASK 0x8000000 +#define TA_STATUS__FL_BUSY__SHIFT 0x1b +#define TA_STATUS__TA_BUSY_MASK 0x10000000 +#define TA_STATUS__TA_BUSY__SHIFT 0x1c +#define TA_STATUS__FA_BUSY_MASK 0x20000000 +#define TA_STATUS__FA_BUSY__SHIFT 0x1d +#define TA_STATUS__AL_BUSY_MASK 0x40000000 +#define TA_STATUS__AL_BUSY__SHIFT 0x1e +#define TA_STATUS__BUSY_MASK 0x80000000 +#define TA_STATUS__BUSY__SHIFT 0x1f +#define TA_DEBUG_INDEX__INDEX_MASK 0x1f +#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0 +#define TA_DEBUG_DATA__DATA_MASK 0xffffffff +#define TA_DEBUG_DATA__DATA__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff +#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_SCRATCH__SCRATCH_MASK 0xffffffff +#define TA_SCRATCH__SCRATCH__SHIFT 0x0 +#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff +#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0 +#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1 +#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0 +#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6 +#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1 +#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18 +#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3 +#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0 +#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5 +#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00 +#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8 +#define TCP_INVALIDATE__START_MASK 0x1 +#define TCP_INVALIDATE__START__SHIFT 0x0 +#define TCP_STATUS__TCP_BUSY_MASK 0x1 +#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 +#define TCP_STATUS__INPUT_BUSY_MASK 0x2 +#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 +#define TCP_STATUS__ADRS_BUSY_MASK 0x4 +#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 +#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x8 +#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 +#define TCP_STATUS__CNTRL_BUSY_MASK 0x10 +#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 +#define TCP_STATUS__LFIFO_BUSY_MASK 0x20 +#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 +#define TCP_STATUS__READ_BUSY_MASK 0x40 +#define TCP_STATUS__READ_BUSY__SHIFT 0x6 +#define TCP_STATUS__FORMAT_BUSY_MASK 0x80 +#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 +#define TCP_CNTL__FORCE_HIT_MASK 0x1 +#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 +#define TCP_CNTL__FORCE_MISS_MASK 0x2 +#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 +#define TCP_CNTL__L1_SIZE_MASK 0xc +#define TCP_CNTL__L1_SIZE__SHIFT 0x2 +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10 +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20 +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000 +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000 +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 +#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000 +#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c +#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000 +#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d +#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf +#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 +#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0 +#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 +#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00 +#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 +#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000 +#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc +#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000 +#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 +#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000 +#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 +#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000 +#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 +#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000 +#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c +#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf +#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 +#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0 +#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 +#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00 +#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 +#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000 +#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc +#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000 +#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 +#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000 +#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 +#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000 +#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 +#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000 +#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 +#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30 +#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 +#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0 +#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200 +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 +#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff +#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 +#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000 +#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 +#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000 +#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 +#define TCP_EDC_CNT__SEC_COUNT_MASK 0xff +#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 +#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0xff00 +#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 +#define TCP_EDC_CNT__DED_COUNT_MASK 0xff0000 +#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 +#define TCP_EDC_CNT__UNUSED_MASK 0xff000000 +#define TCP_EDC_CNT__UNUSED__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1 +#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2 +#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 +#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4 +#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 +#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8 +#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 +#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10 +#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 +#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20 +#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 +#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40 +#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 +#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80 +#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 +#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100 +#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 +#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200 +#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 +#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400 +#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa +#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800 +#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb +#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000 +#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc +#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000 +#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd +#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000 +#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe +#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000 +#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf +#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000 +#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 +#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000 +#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 +#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000 +#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 +#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000 +#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 +#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000 +#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 +#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000 +#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 +#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000 +#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 +#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000 +#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 +#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 +#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 +#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a +#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b +#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c +#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d +#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e +#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3 +#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc +#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30 +#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300 +#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00 +#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3 +#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc +#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30 +#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0 +#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300 +#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00 +#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e +#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf +#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 +#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf +#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 +#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f +#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x2000000 +#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 +#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x4000000 +#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a +#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x8000000 +#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b +#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000 +#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000 +#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0xff +#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x1 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x2 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 +#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x4 +#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x18 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x20 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0xff +#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 +#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf +#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf +#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCI_STATUS__TCI_BUSY_MASK 0x1 +#define TCI_STATUS__TCI_BUSY__SHIFT 0x0 +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 +#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000 +#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 +#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000 +#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 +#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe +#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 +#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6 +#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 +#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18 +#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 +#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60 +#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 +#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180 +#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 +#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1 +#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 +#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4 +#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8 +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10 +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 +#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20 +#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 +#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40 +#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x80 +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 +#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x100 +#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 +#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x200 +#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x400 +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa +#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x800 +#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb +#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x1000 +#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc +#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x2000 +#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd +#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x4000 +#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe +#define GDS_ENHANCE2__MISC_MASK 0xffff +#define GDS_ENHANCE2__MISC__SHIFT 0x0 +#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000 +#define GDS_ENHANCE2__UNUSED__SHIFT 0x10 +#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 +#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 +#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4 +#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 +#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38 +#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 +#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0 +#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 +#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00 +#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa +#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000 +#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc +#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 +#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4 +#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 +#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8 +#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 +#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10 +#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 +#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00 +#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 +#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 +#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_EDC_CNT__DED_MASK 0xff +#define GDS_EDC_CNT__DED__SHIFT 0x0 +#define GDS_EDC_CNT__SED_MASK 0xff00 +#define GDS_EDC_CNT__SED__SHIFT 0x8 +#define GDS_EDC_CNT__SEC_MASK 0xff0000 +#define GDS_EDC_CNT__SEC__SHIFT 0x10 +#define GDS_EDC_GRBM_CNT__DED_MASK 0xff +#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 +#define GDS_EDC_GRBM_CNT__SEC_MASK 0xff0000 +#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x10 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 +#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x4 +#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 +#define GDS_EDC_OA_DED__UNUSED0_MASK 0x8 +#define GDS_EDC_OA_DED__UNUSED0__SHIFT 0x3 +#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x10 +#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 +#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x20 +#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 +#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x40 +#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 +#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x80 +#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 +#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x100 +#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 +#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x200 +#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 +#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x400 +#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa +#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x800 +#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb +#define GDS_EDC_OA_DED__UNUSED1_MASK 0xfffff000 +#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc +#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f +#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0 +#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0 +#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5 +#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff +#define GDS_DEBUG_DATA__DATA__SHIFT 0x0 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK 0x1 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT 0x0 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK 0x2 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT 0x1 +#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK 0x4 +#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK 0x8 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT 0x3 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK 0x10 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT 0x4 +#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK 0x20 +#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT 0x5 +#define GDS_DSM_CNTL__UNUSED_MASK 0xffffffc0 +#define GDS_DSM_CNTL__UNUSED__SHIFT 0x6 +#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff +#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 +#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff +#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 +#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff +#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 +#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff +#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 +#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff +#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 +#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff +#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff +#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff +#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff +#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 +#define GDS_ATOM_CNTL__AINC_MASK 0x3f +#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 +#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0 +#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 +#define GDS_ATOM_CNTL__DMODE_MASK 0x300 +#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 +#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffc00 +#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa +#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1 +#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 +#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe +#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 +#define GDS_ATOM_BASE__BASE_MASK 0xffff +#define GDS_ATOM_BASE__BASE__SHIFT 0x0 +#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000 +#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_SIZE__SIZE_MASK 0xffff +#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 +#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000 +#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff +#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 +#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00 +#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff +#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 +#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00 +#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 +#define GDS_ATOM_DST__DST_MASK 0xffffffff +#define GDS_ATOM_DST__DST__SHIFT 0x0 +#define GDS_ATOM_OP__OP_MASK 0xff +#define GDS_ATOM_OP__OP__SHIFT 0x0 +#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00 +#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 +#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0__DATA_MASK 0xffffffff +#define GDS_ATOM_READ0__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff +#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1__DATA_MASK 0xffffffff +#define GDS_ATOM_READ1__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff +#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f +#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0 +#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 +#define GDS_GWS_RESOURCE__FLAG_MASK 0x1 +#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 +#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe +#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 +#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000 +#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd +#define GDS_GWS_RESOURCE__DED_MASK 0x4000 +#define GDS_GWS_RESOURCE__DED__SHIFT 0xe +#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000 +#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf +#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000 +#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 +#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000 +#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b +#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000 +#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c +#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000 +#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000 +#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 +#define GDS_OA_CNTL__INDEX_MASK 0xf +#define GDS_OA_CNTL__INDEX__SHIFT 0x0 +#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0 +#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 +#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff +#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 +#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff +#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 +#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf0000 +#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 +#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x300000 +#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 +#define GDS_OA_ADDRESS__UNUSED_MASK 0x3fc00000 +#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 +#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000 +#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e +#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000 +#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f +#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff +#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 +#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000 +#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f +#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff +#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 +#define GDS_DEBUG_REG0__spare1_MASK 0x3f +#define GDS_DEBUG_REG0__spare1__SHIFT 0x0 +#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40 +#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6 +#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80 +#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7 +#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000 +#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc +#define GDS_DEBUG_REG0__cstate_MASK 0x1e000 +#define GDS_DEBUG_REG0__cstate__SHIFT 0xd +#define GDS_DEBUG_REG0__buff_write_MASK 0x20000 +#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11 +#define GDS_DEBUG_REG0__flush_request_MASK 0x40000 +#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12 +#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000 +#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13 +#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000 +#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14 +#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000 +#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15 +#define GDS_DEBUG_REG0__spare_MASK 0xffc00000 +#define GDS_DEBUG_REG0__spare__SHIFT 0x16 +#define GDS_DEBUG_REG1__tag_hit_MASK 0x1 +#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0 +#define GDS_DEBUG_REG1__tag_miss_MASK 0x2 +#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1 +#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc +#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2 +#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000 +#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11 +#define GDS_DEBUG_REG1__data_ready_MASK 0x40000 +#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12 +#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000 +#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13 +#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000 +#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14 +#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000 +#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15 +#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000 +#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16 +#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000 +#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17 +#define GDS_DEBUG_REG1__spare_MASK 0xff000000 +#define GDS_DEBUG_REG1__spare__SHIFT 0x18 +#define GDS_DEBUG_REG2__ds_full_MASK 0x1 +#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0 +#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2 +#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1 +#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4 +#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2 +#define GDS_DEBUG_REG2__cmd_write_MASK 0x8 +#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3 +#define GDS_DEBUG_REG2__app_sel_MASK 0xf0 +#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4 +#define GDS_DEBUG_REG2__req_MASK 0x7fff00 +#define GDS_DEBUG_REG2__req__SHIFT 0x8 +#define GDS_DEBUG_REG2__spare_MASK 0xff800000 +#define GDS_DEBUG_REG2__spare__SHIFT 0x17 +#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff +#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0 +#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800 +#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb +#define GDS_DEBUG_REG3__spare_MASK 0xffff8000 +#define GDS_DEBUG_REG3__spare__SHIFT 0xf +#define GDS_DEBUG_REG4__gws_busy_MASK 0x1 +#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0 +#define GDS_DEBUG_REG4__gws_req_MASK 0x2 +#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1 +#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4 +#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2 +#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8 +#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3 +#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200 +#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9 +#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400 +#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa +#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800 +#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb +#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000 +#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc +#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000 +#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd +#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000 +#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe +#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000 +#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf +#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000 +#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10 +#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000 +#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11 +#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000 +#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12 +#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000 +#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13 +#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000 +#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14 +#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000 +#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15 +#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000 +#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16 +#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000 +#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17 +#define GDS_DEBUG_REG4__spare_MASK 0xff000000 +#define GDS_DEBUG_REG4__spare__SHIFT 0x18 +#define GDS_DEBUG_REG5__write_dis_MASK 0x1 +#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0 +#define GDS_DEBUG_REG5__dec_error_MASK 0x2 +#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1 +#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4 +#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2 +#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8 +#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3 +#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10 +#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4 +#define GDS_DEBUG_REG5__spare_MASK 0xe0 +#define GDS_DEBUG_REG5__spare__SHIFT 0x5 +#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00 +#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8 +#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000 +#define GDS_DEBUG_REG5__spare1__SHIFT 0x16 +#define GDS_DEBUG_REG6__oa_busy_MASK 0x1 +#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0 +#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e +#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1 +#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0 +#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5 +#define GDS_DEBUG_REG6__spare_MASK 0xffe00000 +#define GDS_DEBUG_REG6__spare__SHIFT 0x15 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define GDS_VMID0_BASE__BASE_MASK 0xffff +#define GDS_VMID0_BASE__BASE__SHIFT 0x0 +#define GDS_VMID1_BASE__BASE_MASK 0xffff +#define GDS_VMID1_BASE__BASE__SHIFT 0x0 +#define GDS_VMID2_BASE__BASE_MASK 0xffff +#define GDS_VMID2_BASE__BASE__SHIFT 0x0 +#define GDS_VMID3_BASE__BASE_MASK 0xffff +#define GDS_VMID3_BASE__BASE__SHIFT 0x0 +#define GDS_VMID4_BASE__BASE_MASK 0xffff +#define GDS_VMID4_BASE__BASE__SHIFT 0x0 +#define GDS_VMID5_BASE__BASE_MASK 0xffff +#define GDS_VMID5_BASE__BASE__SHIFT 0x0 +#define GDS_VMID6_BASE__BASE_MASK 0xffff +#define GDS_VMID6_BASE__BASE__SHIFT 0x0 +#define GDS_VMID7_BASE__BASE_MASK 0xffff +#define GDS_VMID7_BASE__BASE__SHIFT 0x0 +#define GDS_VMID8_BASE__BASE_MASK 0xffff +#define GDS_VMID8_BASE__BASE__SHIFT 0x0 +#define GDS_VMID9_BASE__BASE_MASK 0xffff +#define GDS_VMID9_BASE__BASE__SHIFT 0x0 +#define GDS_VMID10_BASE__BASE_MASK 0xffff +#define GDS_VMID10_BASE__BASE__SHIFT 0x0 +#define GDS_VMID11_BASE__BASE_MASK 0xffff +#define GDS_VMID11_BASE__BASE__SHIFT 0x0 +#define GDS_VMID12_BASE__BASE_MASK 0xffff +#define GDS_VMID12_BASE__BASE__SHIFT 0x0 +#define GDS_VMID13_BASE__BASE_MASK 0xffff +#define GDS_VMID13_BASE__BASE__SHIFT 0x0 +#define GDS_VMID14_BASE__BASE_MASK 0xffff +#define GDS_VMID14_BASE__BASE__SHIFT 0x0 +#define GDS_VMID15_BASE__BASE_MASK 0xffff +#define GDS_VMID15_BASE__BASE__SHIFT 0x0 +#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 +#define GDS_GWS_VMID0__BASE_MASK 0x3f +#define GDS_GWS_VMID0__BASE__SHIFT 0x0 +#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID1__BASE_MASK 0x3f +#define GDS_GWS_VMID1__BASE__SHIFT 0x0 +#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID2__BASE_MASK 0x3f +#define GDS_GWS_VMID2__BASE__SHIFT 0x0 +#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID3__BASE_MASK 0x3f +#define GDS_GWS_VMID3__BASE__SHIFT 0x0 +#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID4__BASE_MASK 0x3f +#define GDS_GWS_VMID4__BASE__SHIFT 0x0 +#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID5__BASE_MASK 0x3f +#define GDS_GWS_VMID5__BASE__SHIFT 0x0 +#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID6__BASE_MASK 0x3f +#define GDS_GWS_VMID6__BASE__SHIFT 0x0 +#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID7__BASE_MASK 0x3f +#define GDS_GWS_VMID7__BASE__SHIFT 0x0 +#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID8__BASE_MASK 0x3f +#define GDS_GWS_VMID8__BASE__SHIFT 0x0 +#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID9__BASE_MASK 0x3f +#define GDS_GWS_VMID9__BASE__SHIFT 0x0 +#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID10__BASE_MASK 0x3f +#define GDS_GWS_VMID10__BASE__SHIFT 0x0 +#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID11__BASE_MASK 0x3f +#define GDS_GWS_VMID11__BASE__SHIFT 0x0 +#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID12__BASE_MASK 0x3f +#define GDS_GWS_VMID12__BASE__SHIFT 0x0 +#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID13__BASE_MASK 0x3f +#define GDS_GWS_VMID13__BASE__SHIFT 0x0 +#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID14__BASE_MASK 0x3f +#define GDS_GWS_VMID14__BASE__SHIFT 0x0 +#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID15__BASE_MASK 0x3f +#define GDS_GWS_VMID15__BASE__SHIFT 0x0 +#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 +#define GDS_OA_VMID0__MASK_MASK 0xffff +#define GDS_OA_VMID0__MASK__SHIFT 0x0 +#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID1__MASK_MASK 0xffff +#define GDS_OA_VMID1__MASK__SHIFT 0x0 +#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID2__MASK_MASK 0xffff +#define GDS_OA_VMID2__MASK__SHIFT 0x0 +#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID3__MASK_MASK 0xffff +#define GDS_OA_VMID3__MASK__SHIFT 0x0 +#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID4__MASK_MASK 0xffff +#define GDS_OA_VMID4__MASK__SHIFT 0x0 +#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID5__MASK_MASK 0xffff +#define GDS_OA_VMID5__MASK__SHIFT 0x0 +#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID6__MASK_MASK 0xffff +#define GDS_OA_VMID6__MASK__SHIFT 0x0 +#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID7__MASK_MASK 0xffff +#define GDS_OA_VMID7__MASK__SHIFT 0x0 +#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID8__MASK_MASK 0xffff +#define GDS_OA_VMID8__MASK__SHIFT 0x0 +#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID9__MASK_MASK 0xffff +#define GDS_OA_VMID9__MASK__SHIFT 0x0 +#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID10__MASK_MASK 0xffff +#define GDS_OA_VMID10__MASK__SHIFT 0x0 +#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID11__MASK_MASK 0xffff +#define GDS_OA_VMID11__MASK__SHIFT 0x0 +#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID12__MASK_MASK 0xffff +#define GDS_OA_VMID12__MASK__SHIFT 0x0 +#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID13__MASK_MASK 0xffff +#define GDS_OA_VMID13__MASK__SHIFT 0x0 +#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID14__MASK_MASK 0xffff +#define GDS_OA_VMID14__MASK__SHIFT 0x0 +#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID15__MASK_MASK 0xffff +#define GDS_OA_VMID15__MASK__SHIFT 0x0 +#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 +#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1 +#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 +#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2 +#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 +#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4 +#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 +#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8 +#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 +#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10 +#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 +#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20 +#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 +#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40 +#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 +#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80 +#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 +#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100 +#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 +#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200 +#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 +#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400 +#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa +#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800 +#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb +#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000 +#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc +#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000 +#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd +#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000 +#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe +#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000 +#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf +#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000 +#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 +#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000 +#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 +#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000 +#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 +#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000 +#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 +#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000 +#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 +#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000 +#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 +#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000 +#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 +#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000 +#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 +#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000 +#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 +#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000 +#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 +#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000 +#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a +#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000 +#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b +#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000 +#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c +#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000 +#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d +#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000 +#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e +#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000 +#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f +#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1 +#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 +#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2 +#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 +#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4 +#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 +#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8 +#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 +#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10 +#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 +#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20 +#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 +#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40 +#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 +#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80 +#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 +#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100 +#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 +#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200 +#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 +#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400 +#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa +#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800 +#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb +#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000 +#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc +#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000 +#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd +#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000 +#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe +#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000 +#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf +#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000 +#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 +#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000 +#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 +#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000 +#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 +#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000 +#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 +#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000 +#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 +#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000 +#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 +#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000 +#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 +#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000 +#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 +#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000 +#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 +#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000 +#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 +#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000 +#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a +#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000 +#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b +#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000 +#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c +#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000 +#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d +#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000 +#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e +#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000 +#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f +#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1 +#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 +#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4 +#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 +#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8 +#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3 +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10 +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20 +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40 +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80 +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100 +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200 +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400 +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800 +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb +#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000 +#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc +#define GDS_OA_RESET__RESET_MASK 0x1 +#define GDS_OA_RESET__RESET__SHIFT 0x0 +#define GDS_OA_RESET__PIPE_ID_MASK 0xff00 +#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 +#define GDS_ENHANCE__MISC_MASK 0xffff +#define GDS_ENHANCE__MISC__SHIFT 0x0 +#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000 +#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 +#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000 +#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 +#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000 +#define GDS_ENHANCE__UNUSED__SHIFT 0x12 +#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff +#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 +#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00 +#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 +#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000 +#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc +#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0xf0000 +#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 +#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xfff00000 +#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 +#define GDS_CS_CTXSW_STATUS__R_MASK 0x1 +#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_CS_CTXSW_STATUS__W_MASK 0x2 +#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xfffffffc +#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_GFX_CTXSW_STATUS__R_MASK 0x1 +#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_GFX_CTXSW_STATUS__W_MASK 0x2 +#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xfffffffc +#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 +#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7 +#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7 +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc +#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20 +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 +#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40 +#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000 +#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12 +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000 +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 +#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff +#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3 +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc +#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x40 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 +#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200 +#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 +#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400 +#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa +#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x1800 +#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define IA_ENHANCE__MISC_MASK 0xffffffff +#define IA_ENHANCE__MISC__SHIFT 0x0 +#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff +#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 +#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff +#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000 +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000 +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define VGT_IMMED_DATA__DATA_MASK 0xffffffff +#define VGT_IMMED_DATA__DATA__SHIFT 0x0 +#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3 +#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff +#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 +#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff +#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 +#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff +#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 +#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1 +#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 +#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1 +#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 +#define VGT_ENHANCE__MISC_MASK 0xffffffff +#define VGT_ENHANCE__MISC__SHIFT 0x0 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 +#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3 +#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000 +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000 +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 +#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf +#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 +#define VGT_GROUP_DECR__DECR_MASK 0xf +#define VGT_GROUP_DECR__DECR__SHIFT 0x0 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2 +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4 +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8 +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00 +#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000 +#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2 +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4 +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8 +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00 +#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000 +#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define VGT_GS_MODE__MODE_MASK 0x7 +#define VGT_GS_MODE__MODE__SHIFT 0x0 +#define VGT_GS_MODE__RESERVED_0_MASK 0x8 +#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 +#define VGT_GS_MODE__CUT_MODE_MASK 0x30 +#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 +#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0 +#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 +#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800 +#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb +#define VGT_GS_MODE__RESERVED_2_MASK 0x1000 +#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc +#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000 +#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd +#define VGT_GS_MODE__RESERVED_3_MASK 0x4000 +#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe +#define VGT_GS_MODE__RESERVED_4_MASK 0x8000 +#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf +#define VGT_GS_MODE__RESERVED_5_MASK 0x10000 +#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000 +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 +#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000 +#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000 +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000 +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 +#define VGT_GS_MODE__ONCHIP_MASK 0x600000 +#define VGT_GS_MODE__ONCHIP__SHIFT 0x15 +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800 +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000 +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3 +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 +#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x10 +#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0 +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 +#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200 +#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800 +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000 +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000 +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd +#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000 +#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 +#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1 +#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 +#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2 +#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 +#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4 +#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 +#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff +#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700 +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800 +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000 +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000 +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 +#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80 +#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00 +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 +#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0xfc00000 +#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 +#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff +#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 +#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff +#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 +#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf +#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 +#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f +#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 +#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1 +#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 +#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2 +#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4 +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 +#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8 +#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 +#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10 +#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1 +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2 +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4 +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8 +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70 +#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000 +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 +#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3 +#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 +#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4 +#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 +#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18 +#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 +#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20 +#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 +#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0 +#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100 +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8 +#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x200 +#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x400 +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x800 +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x1000 +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff +#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_TF_PARAM__TYPE_MASK 0x3 +#define VGT_TF_PARAM__TYPE__SHIFT 0x0 +#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c +#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 +#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0 +#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100 +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 +#define VGT_TF_PARAM__DEPRECATED_MASK 0x200 +#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00 +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa +#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000 +#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe +#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x8000 +#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf +#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x60000 +#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 +#define VGT_TF_PARAM__MTYPE_MASK 0x180000 +#define VGT_TF_PARAM__MTYPE__SHIFT 0x13 +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0xff +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0xff00 +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000 +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0xff000000 +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 +#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff +#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 +#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1 +#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 +#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff +#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1 +#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc +#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000 +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000 +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000 +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK 0xf0000000 +#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT 0x1c +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff +#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff +#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff +#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff +#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff +#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 +#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1 +#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2 +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4 +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 +#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8 +#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 +#define WD_ENHANCE__MISC_MASK 0xffffffff +#define WD_ENHANCE__MISC__SHIFT 0x0 +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 +#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000 +#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000 +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 +#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1 +#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0 +#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000 +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 +#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 +#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 +#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 +#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 +#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000 +#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000 +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000 +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0 +#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40 +#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6 +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff +#define VGT_DEBUG_DATA__DATA__SHIFT 0x0 +#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f +#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0 +#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40 +#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6 +#define IA_DEBUG_DATA__DATA_MASK 0xffffffff +#define IA_DEBUG_DATA__DATA__SHIFT 0x0 +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1 +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 +#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10 +#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 +#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40 +#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 +#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80 +#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 +#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100 +#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 +#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200 +#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 +#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f +#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0 +#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40 +#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6 +#define WD_DEBUG_DATA__DATA_MASK 0xffffffff +#define WD_DEBUG_DATA__DATA__SHIFT 0x0 +#define WD_QOS__DRAW_STALL_MASK 0x1 +#define WD_QOS__DRAW_STALL__SHIFT 0x0 +#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 +#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 +#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1 +#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0 +#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2 +#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1 +#define WD_DEBUG_REG0__wd_busy_MASK 0x4 +#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2 +#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8 +#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3 +#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10 +#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4 +#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20 +#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5 +#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40 +#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6 +#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80 +#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7 +#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100 +#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8 +#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200 +#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9 +#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400 +#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa +#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800 +#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb +#define WD_DEBUG_REG0__SPARE2_MASK 0x1000 +#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc +#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000 +#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd +#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000 +#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe +#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000 +#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf +#define WD_DEBUG_REG0__SPARE3_MASK 0x10000 +#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10 +#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000 +#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11 +#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000 +#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12 +#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000 +#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13 +#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000 +#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14 +#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000 +#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15 +#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000 +#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16 +#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000 +#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17 +#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 +#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 +#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000 +#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19 +#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000 +#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a +#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000 +#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b +#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 +#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c +#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000 +#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d +#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000 +#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e +#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000 +#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f +#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1 +#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0 +#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2 +#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1 +#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4 +#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2 +#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8 +#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3 +#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10 +#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4 +#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20 +#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5 +#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40 +#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6 +#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80 +#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7 +#define WD_DEBUG_REG1__SPARE0_MASK 0x100 +#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8 +#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200 +#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9 +#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400 +#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa +#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800 +#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb +#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000 +#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc +#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000 +#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11 +#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000 +#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14 +#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000 +#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a +#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000 +#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b +#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000 +#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c +#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000 +#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d +#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f +#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1 +#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0 +#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2 +#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1 +#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4 +#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2 +#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8 +#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3 +#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10 +#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4 +#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20 +#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5 +#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40 +#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6 +#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80 +#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7 +#define WD_DEBUG_REG2__SPARE0_MASK 0x100 +#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8 +#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200 +#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9 +#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400 +#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa +#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800 +#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000 +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000 +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11 +#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000 +#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000 +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f +#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1 +#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0 +#define WD_DEBUG_REG3__SPARE0_MASK 0x2 +#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1 +#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4 +#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2 +#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8 +#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3 +#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10 +#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4 +#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20 +#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5 +#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40 +#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6 +#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80 +#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7 +#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300 +#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8 +#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400 +#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa +#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800 +#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb +#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000 +#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc +#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000 +#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd +#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000 +#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe +#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000 +#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf +#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000 +#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10 +#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000 +#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11 +#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000 +#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12 +#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000 +#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13 +#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000 +#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14 +#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000 +#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15 +#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000 +#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16 +#define WD_DEBUG_REG3__SPARE1_MASK 0x800000 +#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17 +#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000 +#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18 +#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000 +#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19 +#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000 +#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a +#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000 +#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b +#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000 +#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c +#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000 +#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d +#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f +#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1 +#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0 +#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2 +#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1 +#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4 +#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2 +#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8 +#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3 +#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10 +#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4 +#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20 +#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5 +#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40 +#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6 +#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80 +#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7 +#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100 +#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8 +#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200 +#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9 +#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400 +#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa +#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800 +#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb +#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000 +#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc +#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000 +#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd +#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000 +#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe +#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000 +#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10 +#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000 +#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13 +#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000 +#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14 +#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000 +#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15 +#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000 +#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16 +#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000 +#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17 +#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000 +#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18 +#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000 +#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19 +#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000 +#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a +#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000 +#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b +#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000 +#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c +#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000 +#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d +#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000 +#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e +#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000 +#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f +#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1 +#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0 +#define WD_DEBUG_REG5__SPARE0_MASK 0x2 +#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1 +#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4 +#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2 +#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8 +#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3 +#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10 +#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4 +#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20 +#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7 +#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300 +#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8 +#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400 +#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa +#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800 +#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb +#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000 +#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc +#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000 +#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd +#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000 +#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe +#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000 +#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf +#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000 +#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10 +#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000 +#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13 +#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000 +#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14 +#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000 +#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15 +#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000 +#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16 +#define WD_DEBUG_REG5__SPARE1_MASK 0x800000 +#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17 +#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000 +#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19 +#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000 +#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a +#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000 +#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b +#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000 +#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c +#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000 +#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f +#define WD_DEBUG_REG6__WD_IA_draw_eop_MASK 0xffffffff +#define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT 0x0 +#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK 0x1 +#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT 0x0 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK 0x2 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT 0x1 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK 0x4 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT 0x2 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK 0x8 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT 0x3 +#define WD_DEBUG_REG7__SPARE0_MASK 0xf0 +#define WD_DEBUG_REG7__SPARE0__SHIFT 0x4 +#define WD_DEBUG_REG7__SPARE1_MASK 0xf00 +#define WD_DEBUG_REG7__SPARE1__SHIFT 0x8 +#define WD_DEBUG_REG7__SPARE2_MASK 0xf000 +#define WD_DEBUG_REG7__SPARE2__SHIFT 0xc +#define WD_DEBUG_REG7__SPARE3_MASK 0xf0000 +#define WD_DEBUG_REG7__SPARE3__SHIFT 0x10 +#define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK 0x100000 +#define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x14 +#define WD_DEBUG_REG7__se0_thdgrp_eop_MASK 0x200000 +#define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT 0x15 +#define WD_DEBUG_REG7__SPARE4_MASK 0xfc00000 +#define WD_DEBUG_REG7__SPARE4__SHIFT 0x16 +#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK 0x10000000 +#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT 0x1c +#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK 0x20000000 +#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d +#define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK 0x40000000 +#define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT 0x1e +#define WD_DEBUG_REG7__te11_arb_busy_MASK 0x80000000 +#define WD_DEBUG_REG7__te11_arb_busy__SHIFT 0x1f +#define WD_DEBUG_REG8__pipe0_dr_MASK 0x1 +#define WD_DEBUG_REG8__pipe0_dr__SHIFT 0x0 +#define WD_DEBUG_REG8__pipe1_dr_MASK 0x2 +#define WD_DEBUG_REG8__pipe1_dr__SHIFT 0x1 +#define WD_DEBUG_REG8__pipe0_rtr_MASK 0x4 +#define WD_DEBUG_REG8__pipe0_rtr__SHIFT 0x2 +#define WD_DEBUG_REG8__pipe1_rtr_MASK 0x8 +#define WD_DEBUG_REG8__pipe1_rtr__SHIFT 0x3 +#define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK 0x10 +#define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT 0x4 +#define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK 0x20 +#define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT 0x5 +#define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK 0x40 +#define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT 0x6 +#define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK 0x80 +#define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT 0x7 +#define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK 0x100 +#define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT 0x8 +#define WD_DEBUG_REG8__tf_skid_fifo_full_MASK 0x200 +#define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT 0x9 +#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK 0x400 +#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT 0xa +#define WD_DEBUG_REG8__last_req_of_tg_p2_MASK 0x800 +#define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT 0xb +#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK 0x3f000 +#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT 0xc +#define WD_DEBUG_REG8__event_flag_p1_q_MASK 0x40000 +#define WD_DEBUG_REG8__event_flag_p1_q__SHIFT 0x12 +#define WD_DEBUG_REG8__null_flag_p1_q_MASK 0x80000 +#define WD_DEBUG_REG8__null_flag_p1_q__SHIFT 0x13 +#define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK 0x7f00000 +#define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x14 +#define WD_DEBUG_REG8__second_tf_ret_data_q_MASK 0x8000000 +#define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT 0x1b +#define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK 0x10000000 +#define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT 0x1c +#define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK 0x20000000 +#define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d +#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK 0x40000000 +#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT 0x1e +#define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK 0x80000000 +#define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT 0x1f +#define WD_DEBUG_REG9__pipe0_dr_MASK 0x1 +#define WD_DEBUG_REG9__pipe0_dr__SHIFT 0x0 +#define WD_DEBUG_REG9__pipec_tf_dr_MASK 0x2 +#define WD_DEBUG_REG9__pipec_tf_dr__SHIFT 0x1 +#define WD_DEBUG_REG9__pipe2_dr_MASK 0x4 +#define WD_DEBUG_REG9__pipe2_dr__SHIFT 0x2 +#define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK 0x8 +#define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT 0x3 +#define WD_DEBUG_REG9__pipe0_rtr_MASK 0x10 +#define WD_DEBUG_REG9__pipe0_rtr__SHIFT 0x4 +#define WD_DEBUG_REG9__pipe1_rtr_MASK 0x20 +#define WD_DEBUG_REG9__pipe1_rtr__SHIFT 0x5 +#define WD_DEBUG_REG9__pipec_tf_rtr_MASK 0x40 +#define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT 0x6 +#define WD_DEBUG_REG9__pipe2_rtr_MASK 0x80 +#define WD_DEBUG_REG9__pipe2_rtr__SHIFT 0x7 +#define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK 0x100 +#define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT 0x8 +#define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK 0x200 +#define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT 0x9 +#define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK 0x400 +#define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT 0xa +#define WD_DEBUG_REG9__SPARE0_MASK 0xf800 +#define WD_DEBUG_REG9__SPARE0__SHIFT 0xb +#define WD_DEBUG_REG9__tf_fetch_state_q_MASK 0x70000 +#define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT 0x10 +#define WD_DEBUG_REG9__last_patch_of_tg_MASK 0x80000 +#define WD_DEBUG_REG9__last_patch_of_tg__SHIFT 0x13 +#define WD_DEBUG_REG9__tf_pointer_p0_q_MASK 0xf00000 +#define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x14 +#define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK 0x1000000 +#define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT 0x18 +#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK 0x2000000 +#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT 0x19 +#define WD_DEBUG_REG9__mem_is_even_MASK 0x4000000 +#define WD_DEBUG_REG9__mem_is_even__SHIFT 0x1a +#define WD_DEBUG_REG9__SPARE1_MASK 0x8000000 +#define WD_DEBUG_REG9__SPARE1__SHIFT 0x1b +#define WD_DEBUG_REG9__SPARE2_MASK 0x30000000 +#define WD_DEBUG_REG9__SPARE2__SHIFT 0x1c +#define WD_DEBUG_REG9__pipe4_dr_MASK 0x40000000 +#define WD_DEBUG_REG9__pipe4_dr__SHIFT 0x1e +#define WD_DEBUG_REG9__pipe4_rtr_MASK 0x80000000 +#define WD_DEBUG_REG9__pipe4_rtr__SHIFT 0x1f +#define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK 0x1 +#define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT 0x0 +#define WD_DEBUG_REG10__ttp_pd_is_event_MASK 0x2 +#define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT 0x1 +#define WD_DEBUG_REG10__ttp_pd_eopg_MASK 0x4 +#define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT 0x2 +#define WD_DEBUG_REG10__ttp_pd_eop_MASK 0x8 +#define WD_DEBUG_REG10__ttp_pd_eop__SHIFT 0x3 +#define WD_DEBUG_REG10__pipe0_dr_MASK 0x10 +#define WD_DEBUG_REG10__pipe0_dr__SHIFT 0x4 +#define WD_DEBUG_REG10__pipe1_dr_MASK 0x20 +#define WD_DEBUG_REG10__pipe1_dr__SHIFT 0x5 +#define WD_DEBUG_REG10__pipe0_rtr_MASK 0x40 +#define WD_DEBUG_REG10__pipe0_rtr__SHIFT 0x6 +#define WD_DEBUG_REG10__pipe1_rtr_MASK 0x80 +#define WD_DEBUG_REG10__pipe1_rtr__SHIFT 0x7 +#define WD_DEBUG_REG10__donut_en_p1_q_MASK 0x100 +#define WD_DEBUG_REG10__donut_en_p1_q__SHIFT 0x8 +#define WD_DEBUG_REG10__donut_se_switch_p2_MASK 0x200 +#define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT 0x9 +#define WD_DEBUG_REG10__patch_se_switch_p2_MASK 0x400 +#define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT 0xa +#define WD_DEBUG_REG10__last_donut_switch_p2_MASK 0x800 +#define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT 0xb +#define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK 0x1000 +#define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT 0xc +#define WD_DEBUG_REG10__is_event_p1_q_MASK 0x2000 +#define WD_DEBUG_REG10__is_event_p1_q__SHIFT 0xd +#define WD_DEBUG_REG10__eopg_p1_q_MASK 0x4000 +#define WD_DEBUG_REG10__eopg_p1_q__SHIFT 0xe +#define WD_DEBUG_REG10__eop_p1_q_MASK 0x8000 +#define WD_DEBUG_REG10__eop_p1_q__SHIFT 0xf +#define WD_DEBUG_REG10__patch_accum_q_MASK 0xff0000 +#define WD_DEBUG_REG10__patch_accum_q__SHIFT 0x10 +#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK 0x1000000 +#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT 0x18 +#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK 0x2000000 +#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT 0x19 +#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK 0x4000000 +#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT 0x1a +#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK 0x8000000 +#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT 0x1b +#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK 0x10000000 +#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT 0x1c +#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK 0x20000000 +#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d +#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK 0x40000000 +#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT 0x1e +#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK 0x80000000 +#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT 0x1f +#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1 +#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0 +#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2 +#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1 +#define IA_DEBUG_REG0__ia_busy_MASK 0x4 +#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2 +#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8 +#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3 +#define IA_DEBUG_REG0__SPARE0_MASK 0x10 +#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4 +#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20 +#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5 +#define IA_DEBUG_REG0__dma_busy_MASK 0x40 +#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6 +#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80 +#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7 +#define IA_DEBUG_REG0__grp_busy_MASK 0x100 +#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8 +#define IA_DEBUG_REG0__SPARE1_MASK 0x200 +#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9 +#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400 +#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa +#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800 +#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb +#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000 +#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc +#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000 +#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd +#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000 +#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe +#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 +#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 +#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000 +#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19 +#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000 +#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a +#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000 +#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b +#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 +#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c +#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 +#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d +#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000 +#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e +#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000 +#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f +#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1 +#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0 +#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2 +#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1 +#define IA_DEBUG_REG1__start_new_packet_MASK 0x4 +#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2 +#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8 +#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3 +#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10 +#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4 +#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60 +#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5 +#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80 +#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7 +#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100 +#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8 +#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200 +#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9 +#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400 +#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa +#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800 +#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb +#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000 +#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc +#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000 +#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd +#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000 +#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe +#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000 +#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf +#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000 +#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10 +#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000 +#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11 +#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000 +#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12 +#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000 +#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13 +#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000 +#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14 +#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000 +#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15 +#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000 +#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16 +#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000 +#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17 +#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000 +#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18 +#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000 +#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19 +#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000 +#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a +#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000 +#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b +#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000 +#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c +#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000 +#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d +#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000 +#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e +#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000 +#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f +#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1 +#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0 +#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2 +#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1 +#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4 +#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2 +#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8 +#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3 +#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10 +#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4 +#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60 +#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5 +#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80 +#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7 +#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100 +#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8 +#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200 +#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9 +#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400 +#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa +#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800 +#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb +#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000 +#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc +#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000 +#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd +#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000 +#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe +#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000 +#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf +#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000 +#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10 +#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000 +#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11 +#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000 +#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12 +#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000 +#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13 +#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000 +#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14 +#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000 +#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15 +#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000 +#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16 +#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000 +#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19 +#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000 +#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a +#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000 +#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b +#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000 +#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c +#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000 +#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d +#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000 +#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e +#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000 +#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f +#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4 +#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20 +#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5 +#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40 +#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6 +#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80 +#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa +#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb +#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc +#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000 +#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd +#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000 +#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe +#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000 +#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf +#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000 +#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10 +#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000 +#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11 +#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000 +#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12 +#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000 +#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13 +#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000 +#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14 +#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000 +#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15 +#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000 +#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16 +#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000 +#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17 +#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000 +#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18 +#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000 +#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a +#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000 +#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b +#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000 +#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c +#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000 +#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d +#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000 +#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e +#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000 +#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f +#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1 +#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0 +#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2 +#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1 +#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4 +#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2 +#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8 +#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3 +#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10 +#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4 +#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20 +#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5 +#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40 +#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6 +#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80 +#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7 +#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100 +#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8 +#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200 +#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9 +#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400 +#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa +#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800 +#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb +#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000 +#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc +#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000 +#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd +#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000 +#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe +#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000 +#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf +#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000 +#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10 +#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000 +#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11 +#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000 +#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14 +#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000 +#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15 +#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000 +#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18 +#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000 +#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19 +#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000 +#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a +#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000 +#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c +#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000 +#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d +#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000 +#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e +#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000 +#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f +#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff +#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0 +#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000 +#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10 +#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000 +#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e +#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000 +#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f +#define IA_DEBUG_REG6__current_shift_q_MASK 0xf +#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0 +#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0 +#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4 +#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00 +#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8 +#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000 +#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd +#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000 +#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe +#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000 +#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf +#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000 +#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10 +#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000 +#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15 +#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000 +#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16 +#define IA_DEBUG_REG6__extract_group_MASK 0x800000 +#define IA_DEBUG_REG6__extract_group__SHIFT 0x17 +#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000 +#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18 +#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf +#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0 +#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0 +#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4 +#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00 +#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8 +#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000 +#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc +#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000 +#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10 +#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000 +#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14 +#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000 +#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17 +#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000 +#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18 +#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000 +#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19 +#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000 +#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a +#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000 +#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b +#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000 +#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c +#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000 +#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d +#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000 +#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e +#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000 +#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f +#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f +#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0 +#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20 +#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5 +#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40 +#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6 +#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80 +#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7 +#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100 +#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8 +#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200 +#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9 +#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400 +#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa +#define IA_DEBUG_REG8__grp_continued_MASK 0x800 +#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb +#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000 +#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc +#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000 +#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf +#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000 +#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15 +#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000 +#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18 +#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000 +#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19 +#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000 +#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a +#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000 +#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b +#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000 +#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c +#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1 +#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0 +#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2 +#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1 +#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4 +#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2 +#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8 +#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3 +#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10 +#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4 +#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20 +#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5 +#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40 +#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6 +#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80 +#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7 +#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100 +#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8 +#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200 +#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9 +#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400 +#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa +#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800 +#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb +#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000 +#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc +#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000 +#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd +#define IA_DEBUG_REG9__SPARE0_MASK 0x4000 +#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe +#define IA_DEBUG_REG9__SPARE1_MASK 0x8000 +#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf +#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000 +#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10 +#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000 +#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11 +#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000 +#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12 +#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000 +#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13 +#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000 +#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14 +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1 +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0 +#define VGT_DEBUG_REG0__SPARE9_MASK 0x2 +#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1 +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4 +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2 +#define VGT_DEBUG_REG0__SPARE8_MASK 0x8 +#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3 +#define VGT_DEBUG_REG0__SPARE7_MASK 0x10 +#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4 +#define VGT_DEBUG_REG0__SPARE6_MASK 0x20 +#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5 +#define VGT_DEBUG_REG0__SPARE5_MASK 0x40 +#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6 +#define VGT_DEBUG_REG0__SPARE4_MASK 0x80 +#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7 +#define VGT_DEBUG_REG0__pi_busy_MASK 0x100 +#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8 +#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200 +#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9 +#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400 +#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa +#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800 +#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb +#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000 +#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc +#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000 +#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd +#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000 +#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe +#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000 +#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf +#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000 +#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10 +#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000 +#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11 +#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000 +#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12 +#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000 +#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13 +#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000 +#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14 +#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000 +#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15 +#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000 +#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16 +#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000 +#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17 +#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 +#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 +#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000 +#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19 +#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000 +#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a +#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000 +#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b +#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000 +#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c +#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 +#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d +#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000 +#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e +#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000 +#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f +#define VGT_DEBUG_REG1__SPARE9_MASK 0x1 +#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0 +#define VGT_DEBUG_REG1__SPARE8_MASK 0x2 +#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1 +#define VGT_DEBUG_REG1__SPARE7_MASK 0x4 +#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2 +#define VGT_DEBUG_REG1__SPARE6_MASK 0x8 +#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3 +#define VGT_DEBUG_REG1__SPARE5_MASK 0x10 +#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4 +#define VGT_DEBUG_REG1__SPARE4_MASK 0x20 +#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5 +#define VGT_DEBUG_REG1__SPARE3_MASK 0x40 +#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6 +#define VGT_DEBUG_REG1__SPARE2_MASK 0x80 +#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7 +#define VGT_DEBUG_REG1__SPARE1_MASK 0x100 +#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8 +#define VGT_DEBUG_REG1__SPARE0_MASK 0x200 +#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9 +#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400 +#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa +#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800 +#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb +#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000 +#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc +#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000 +#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd +#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000 +#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10 +#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000 +#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11 +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12 +#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000 +#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13 +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14 +#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000 +#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15 +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16 +#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000 +#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17 +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18 +#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000 +#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19 +#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000 +#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a +#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000 +#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b +#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000 +#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c +#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000 +#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d +#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000 +#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e +#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000 +#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f +#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1 +#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0 +#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2 +#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1 +#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4 +#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2 +#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8 +#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3 +#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10 +#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20 +#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5 +#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40 +#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6 +#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80 +#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7 +#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100 +#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8 +#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200 +#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9 +#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400 +#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa +#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800 +#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb +#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000 +#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc +#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000 +#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd +#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000 +#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe +#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000 +#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf +#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000 +#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10 +#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000 +#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11 +#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000 +#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12 +#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000 +#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13 +#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000 +#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14 +#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000 +#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15 +#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000 +#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16 +#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000 +#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17 +#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000 +#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18 +#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000 +#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19 +#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000 +#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a +#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000 +#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b +#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000 +#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c +#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000 +#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d +#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff +#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0 +#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000 +#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc +#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000 +#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12 +#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000 +#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a +#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff +#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0 +#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00 +#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8 +#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000 +#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18 +#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000 +#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d +#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000 +#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e +#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000 +#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f +#define VGT_DEBUG_REG5__SPARE4_MASK 0x7 +#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0 +#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8 +#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3 +#define VGT_DEBUG_REG5__SPARE3_MASK 0x700 +#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8 +#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800 +#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb +#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000 +#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10 +#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000 +#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13 +#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000 +#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18 +#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000 +#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b +#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff +#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0 +#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000 +#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10 +#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1 +#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0 +#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2 +#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1 +#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4 +#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2 +#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8 +#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3 +#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10 +#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0 +#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5 +#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000 +#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10 +#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1 +#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2 +#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4 +#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2 +#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8 +#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3 +#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10 +#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4 +#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20 +#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5 +#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40 +#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6 +#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80 +#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7 +#define VGT_DEBUG_REG8__valid_r2_MASK 0x100 +#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8 +#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200 +#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9 +#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400 +#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa +#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800 +#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb +#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000 +#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc +#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000 +#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd +#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000 +#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe +#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000 +#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf +#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000 +#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10 +#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000 +#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11 +#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000 +#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12 +#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000 +#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13 +#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000 +#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14 +#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000 +#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15 +#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000 +#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16 +#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000 +#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17 +#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000 +#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18 +#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000 +#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19 +#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000 +#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a +#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000 +#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b +#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000 +#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c +#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000 +#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d +#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000 +#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e +#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000 +#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f +#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3 +#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0 +#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4 +#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2 +#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8 +#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3 +#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10 +#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4 +#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20 +#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5 +#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40 +#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6 +#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80 +#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7 +#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100 +#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8 +#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200 +#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9 +#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400 +#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa +#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800 +#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb +#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000 +#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12 +#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000 +#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13 +#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000 +#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16 +#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000 +#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17 +#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000 +#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18 +#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000 +#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19 +#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000 +#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a +#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000 +#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c +#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000 +#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d +#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000 +#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e +#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000 +#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f +#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f +#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0 +#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20 +#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5 +#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40 +#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6 +#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180 +#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7 +#define VGT_DEBUG_REG10__SPARE2_MASK 0x600 +#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9 +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800 +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000 +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc +#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000 +#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd +#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000 +#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17 +#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1 +#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2 +#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4 +#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3 +#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10 +#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4 +#define VGT_DEBUG_REG11__SPARE1_MASK 0x20 +#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5 +#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40 +#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6 +#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80 +#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7 +#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100 +#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8 +#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200 +#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9 +#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400 +#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa +#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800 +#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb +#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000 +#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc +#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000 +#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd +#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000 +#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe +#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000 +#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf +#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000 +#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10 +#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000 +#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11 +#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000 +#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12 +#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000 +#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13 +#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000 +#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14 +#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000 +#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15 +#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000 +#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16 +#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000 +#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17 +#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000 +#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18 +#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000 +#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19 +#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000 +#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b +#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000 +#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c +#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000 +#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d +#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000 +#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e +#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000 +#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f +#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7 +#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0 +#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38 +#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3 +#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0 +#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6 +#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00 +#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9 +#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000 +#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc +#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000 +#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf +#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000 +#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12 +#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000 +#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15 +#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000 +#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18 +#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000 +#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b +#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000 +#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e +#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000 +#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f +#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7 +#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0 +#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38 +#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3 +#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0 +#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6 +#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00 +#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9 +#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000 +#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc +#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000 +#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf +#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000 +#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12 +#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000 +#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16 +#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000 +#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17 +#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000 +#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18 +#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000 +#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19 +#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000 +#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a +#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000 +#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b +#define VGT_DEBUG_REG14__SPARE3_MASK 0xf +#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0 +#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10 +#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4 +#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20 +#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5 +#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40 +#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6 +#define VGT_DEBUG_REG14__SPARE8_MASK 0x180 +#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7 +#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200 +#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9 +#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400 +#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa +#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800 +#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb +#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000 +#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc +#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000 +#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15 +#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000 +#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16 +#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000 +#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19 +#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000 +#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a +#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000 +#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b +#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000 +#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c +#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000 +#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d +#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000 +#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e +#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000 +#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f +#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1 +#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2 +#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4 +#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2 +#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8 +#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3 +#define VGT_DEBUG_REG15__counters_full_MASK 0x10 +#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4 +#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0 +#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5 +#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00 +#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa +#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000 +#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf +#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000 +#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14 +#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000 +#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a +#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000 +#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c +#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000 +#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d +#define VGT_DEBUG_REG16__gog_busy_MASK 0x1 +#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0 +#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe +#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1 +#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10 +#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20 +#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40 +#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6 +#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80 +#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7 +#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100 +#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8 +#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200 +#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9 +#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400 +#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa +#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800 +#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb +#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000 +#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc +#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000 +#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd +#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000 +#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe +#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000 +#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf +#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000 +#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10 +#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000 +#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11 +#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000 +#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12 +#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000 +#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13 +#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000 +#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14 +#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000 +#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15 +#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000 +#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16 +#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000 +#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17 +#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000 +#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18 +#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000 +#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19 +#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000 +#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c +#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000 +#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d +#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000 +#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e +#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000 +#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc +#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000 +#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12 +#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1 +#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0 +#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2 +#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1 +#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4 +#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2 +#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8 +#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3 +#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10 +#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20 +#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40 +#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6 +#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80 +#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7 +#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700 +#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8 +#define VGT_DEBUG_REG18__valid_indices_MASK 0x800 +#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb +#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000 +#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc +#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000 +#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd +#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000 +#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe +#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000 +#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf +#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000 +#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10 +#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000 +#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11 +#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000 +#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12 +#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000 +#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13 +#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000 +#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14 +#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000 +#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15 +#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000 +#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16 +#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000 +#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17 +#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000 +#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18 +#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000 +#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b +#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000 +#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c +#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000 +#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d +#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1 +#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2 +#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4 +#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2 +#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8 +#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3 +#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10 +#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4 +#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20 +#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5 +#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40 +#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6 +#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80 +#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7 +#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100 +#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8 +#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200 +#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9 +#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400 +#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa +#define VGT_DEBUG_REG19__hold_prim_MASK 0x800 +#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb +#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000 +#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc +#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000 +#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd +#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000 +#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe +#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000 +#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf +#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000 +#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10 +#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000 +#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11 +#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000 +#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12 +#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000 +#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13 +#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000 +#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14 +#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000 +#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a +#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000 +#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b +#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000 +#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c +#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000 +#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e +#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000 +#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0 +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000 +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10 +#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000 +#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11 +#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000 +#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12 +#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000 +#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16 +#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000 +#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d +#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000 +#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e +#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000 +#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f +#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1 +#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0 +#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2 +#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1 +#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4 +#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2 +#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8 +#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3 +#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10 +#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4 +#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20 +#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5 +#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40 +#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6 +#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80 +#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7 +#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100 +#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8 +#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200 +#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9 +#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400 +#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa +#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800 +#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb +#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000 +#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc +#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000 +#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd +#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000 +#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe +#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000 +#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf +#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000 +#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10 +#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000 +#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000 +#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14 +#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000 +#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15 +#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000 +#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16 +#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000 +#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17 +#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000 +#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18 +#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000 +#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19 +#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000 +#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a +#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000 +#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b +#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000 +#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c +#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000 +#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e +#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000 +#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f +#define VGT_DEBUG_REG22__cm_state16_MASK 0x3 +#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0 +#define VGT_DEBUG_REG22__cm_state17_MASK 0xc +#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2 +#define VGT_DEBUG_REG22__cm_state18_MASK 0x30 +#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4 +#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0 +#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6 +#define VGT_DEBUG_REG22__cm_state20_MASK 0x300 +#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8 +#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00 +#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa +#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000 +#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc +#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000 +#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe +#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000 +#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10 +#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000 +#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12 +#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000 +#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14 +#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000 +#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16 +#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000 +#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18 +#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000 +#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a +#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000 +#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c +#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000 +#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e +#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1 +#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0 +#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2 +#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1 +#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4 +#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2 +#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8 +#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3 +#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10 +#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20 +#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40 +#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6 +#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80 +#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7 +#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100 +#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8 +#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200 +#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9 +#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400 +#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa +#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800 +#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb +#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000 +#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc +#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000 +#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd +#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000 +#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe +#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000 +#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf +#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000 +#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11 +#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000 +#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15 +#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000 +#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18 +#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff +#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0 +#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000 +#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18 +#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000 +#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a +#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff +#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0 +#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000 +#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a +#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000 +#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e +#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000 +#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f +#define VGT_DEBUG_REG26__cm_state0_MASK 0x3 +#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0 +#define VGT_DEBUG_REG26__cm_state1_MASK 0xc +#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2 +#define VGT_DEBUG_REG26__cm_state2_MASK 0x30 +#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4 +#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0 +#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6 +#define VGT_DEBUG_REG26__cm_state4_MASK 0x300 +#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8 +#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00 +#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa +#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000 +#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc +#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000 +#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe +#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000 +#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10 +#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000 +#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12 +#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000 +#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14 +#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000 +#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16 +#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000 +#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18 +#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000 +#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a +#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000 +#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c +#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000 +#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e +#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1 +#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0 +#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2 +#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1 +#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4 +#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2 +#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8 +#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3 +#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10 +#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20 +#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40 +#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6 +#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80 +#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7 +#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300 +#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8 +#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400 +#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa +#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800 +#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb +#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000 +#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc +#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000 +#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10 +#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000 +#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12 +#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000 +#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13 +#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000 +#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14 +#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000 +#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f +#define VGT_DEBUG_REG28__con_state_q_MASK 0xf +#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0 +#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10 +#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4 +#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20 +#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5 +#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40 +#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80 +#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100 +#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8 +#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200 +#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9 +#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400 +#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa +#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800 +#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb +#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000 +#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc +#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000 +#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd +#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000 +#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10 +#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000 +#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12 +#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000 +#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13 +#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000 +#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14 +#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000 +#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 +#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000 +#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16 +#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000 +#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17 +#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000 +#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c +#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000 +#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e +#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000 +#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f +#define VGT_DEBUG_REG29__con_state_q_MASK 0xf +#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0 +#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10 +#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4 +#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20 +#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5 +#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40 +#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80 +#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100 +#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8 +#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200 +#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9 +#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400 +#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa +#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800 +#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb +#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000 +#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc +#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000 +#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd +#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000 +#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10 +#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000 +#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12 +#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000 +#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13 +#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000 +#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14 +#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000 +#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 +#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000 +#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16 +#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000 +#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17 +#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000 +#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c +#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000 +#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e +#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000 +#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f +#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1 +#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0 +#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2 +#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1 +#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4 +#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2 +#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8 +#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3 +#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10 +#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4 +#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20 +#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5 +#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40 +#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6 +#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80 +#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7 +#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100 +#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8 +#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200 +#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9 +#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400 +#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa +#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800 +#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb +#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000 +#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc +#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000 +#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd +#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000 +#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe +#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000 +#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf +#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000 +#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10 +#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000 +#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11 +#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000 +#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12 +#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000 +#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13 +#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000 +#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14 +#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000 +#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15 +#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000 +#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16 +#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000 +#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17 +#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000 +#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18 +#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000 +#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19 +#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000 +#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a +#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000 +#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b +#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000 +#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c +#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000 +#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d +#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000 +#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e +#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000 +#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f +#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1 +#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0 +#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2 +#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1 +#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4 +#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2 +#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8 +#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3 +#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10 +#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4 +#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20 +#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5 +#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40 +#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80 +#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100 +#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8 +#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200 +#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9 +#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400 +#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa +#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800 +#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb +#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000 +#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc +#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000 +#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe +#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000 +#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf +#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000 +#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10 +#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000 +#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11 +#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000 +#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12 +#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000 +#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13 +#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000 +#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14 +#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000 +#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15 +#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000 +#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16 +#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000 +#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17 +#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000 +#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18 +#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000 +#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c +#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1 +#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0 +#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2 +#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1 +#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4 +#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2 +#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8 +#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3 +#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10 +#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20 +#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5 +#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40 +#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6 +#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80 +#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7 +#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100 +#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8 +#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200 +#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9 +#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400 +#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa +#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800 +#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb +#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000 +#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc +#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000 +#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd +#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000 +#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe +#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000 +#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf +#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000 +#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10 +#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000 +#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11 +#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000 +#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12 +#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000 +#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13 +#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000 +#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14 +#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000 +#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15 +#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000 +#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16 +#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000 +#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17 +#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000 +#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000 +#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a +#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000 +#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c +#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000 +#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d +#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000 +#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e +#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000 +#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f +#define VGT_DEBUG_REG34__con_state_q_MASK 0xf +#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0 +#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10 +#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4 +#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20 +#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5 +#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40 +#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80 +#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100 +#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8 +#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200 +#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9 +#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400 +#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa +#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800 +#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb +#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000 +#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc +#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000 +#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd +#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000 +#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10 +#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000 +#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12 +#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000 +#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13 +#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000 +#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14 +#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000 +#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 +#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000 +#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16 +#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000 +#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17 +#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000 +#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c +#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000 +#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e +#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000 +#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f +#define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK 0xffffffff +#define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT 0x0 +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff +#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff +#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff +#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 +#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff +#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 +#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xffffffc0 +#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x6 +#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0xc000 +#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x4000000 +#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000 +#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_SQ_CTRL_OCP__UNUSED_0_MASK 0xffff +#define DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT 0x0 +#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 +#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 +#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xffffffc0 +#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x6 +#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_DB_CTRL2__UNUSED_0_MASK 0xc000 +#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x4000000 +#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000 +#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_DB_CTRL_OCP__UNUSED_0_MASK 0xffff +#define DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT 0x0 +#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 +#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 +#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xffffffc0 +#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x6 +#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_TD_CTRL2__UNUSED_0_MASK 0xc000 +#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x4000000 +#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000 +#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_TD_CTRL_OCP__UNUSED_0_MASK 0xffff +#define DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT 0x0 +#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 +#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 +#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xffffffc0 +#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x6 +#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0xc000 +#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x4000000 +#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000 +#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_TCP_CTRL_OCP__UNUSED_0_MASK 0xffff +#define DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT 0x0 +#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 +#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 +#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xffffffc0 +#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x6 +#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0xc000 +#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x4000000 +#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000 +#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_DBR_CTRL_OCP__UNUSED_0_MASK 0xffff +#define DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT 0x0 +#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 +#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 +#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18 + +#endif /* GFX_8_0_SH_MASK_H */ -- cgit v1.2.3 From 52fb57e7ee35eb6ff19589391255f7188ebdc434 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:22:19 -0400 Subject: drm/amdgpu: add GMC 7.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h | 657 +++ .../drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h | 6116 ++++++++++++++++++++ 2 files changed, 6773 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h new file mode 100644 index 000000000000..1940e7a7c979 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h @@ -0,0 +1,657 @@ +/* + * GMC_7_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_7_0_D_H +#define GMC_7_0_D_H + +#define mmMC_CONFIG 0x800 +#define mmMC_ARB_AGE_CNTL 0x9bf +#define mmMC_ARB_RET_CREDITS2 0x9c0 +#define mmMC_ARB_FED_CNTL 0x9c1 +#define mmMC_ARB_GECC2_STATUS 0x9c2 +#define mmMC_ARB_GECC2_MISC 0x9c3 +#define mmMC_ARB_GECC2_DEBUG 0x9c4 +#define mmMC_ARB_GECC2_DEBUG2 0x9c5 +#define mmMC_ARB_GECC2 0x9c9 +#define mmMC_ARB_GECC2_CLI 0x9ca +#define mmMC_ARB_ADDR_SWIZ0 0x9cb +#define mmMC_ARB_ADDR_SWIZ1 0x9cc +#define mmMC_ARB_MISC3 0x9cd +#define mmMC_ARB_WCDR_2 0x9ce +#define mmMC_ARB_RTT_DATA 0x9cf +#define mmMC_ARB_RTT_CNTL0 0x9d0 +#define mmMC_ARB_RTT_CNTL1 0x9d1 +#define mmMC_ARB_RTT_CNTL2 0x9d2 +#define mmMC_ARB_RTT_DEBUG 0x9d3 +#define mmMC_ARB_CAC_CNTL 0x9d4 +#define mmMC_ARB_MISC2 0x9d5 +#define mmMC_ARB_MISC 0x9d6 +#define mmMC_ARB_BANKMAP 0x9d7 +#define mmMC_ARB_RAMCFG 0x9d8 +#define mmMC_ARB_POP 0x9d9 +#define mmMC_ARB_MINCLKS 0x9da +#define mmMC_ARB_SQM_CNTL 0x9db +#define mmMC_ARB_ADDR_HASH 0x9dc +#define mmMC_ARB_DRAM_TIMING 0x9dd +#define mmMC_ARB_DRAM_TIMING2 0x9de +#define mmMC_ARB_WTM_CNTL_RD 0x9df +#define mmMC_ARB_WTM_CNTL_WR 0x9e0 +#define mmMC_ARB_WTM_GRPWT_RD 0x9e1 +#define mmMC_ARB_WTM_GRPWT_WR 0x9e2 +#define mmMC_ARB_TM_CNTL_RD 0x9e3 +#define mmMC_ARB_TM_CNTL_WR 0x9e4 +#define mmMC_ARB_LAZY0_RD 0x9e5 +#define mmMC_ARB_LAZY0_WR 0x9e6 +#define mmMC_ARB_LAZY1_RD 0x9e7 +#define mmMC_ARB_LAZY1_WR 0x9e8 +#define mmMC_ARB_AGE_RD 0x9e9 +#define mmMC_ARB_AGE_WR 0x9ea +#define mmMC_ARB_RFSH_CNTL 0x9eb +#define mmMC_ARB_RFSH_RATE 0x9ec +#define mmMC_ARB_PM_CNTL 0x9ed +#define mmMC_ARB_GDEC_RD_CNTL 0x9ee +#define mmMC_ARB_GDEC_WR_CNTL 0x9ef +#define mmMC_ARB_LM_RD 0x9f0 +#define mmMC_ARB_LM_WR 0x9f1 +#define mmMC_ARB_REMREQ 0x9f2 +#define mmMC_ARB_REPLAY 0x9f3 +#define mmMC_ARB_RET_CREDITS_RD 0x9f4 +#define mmMC_ARB_RET_CREDITS_WR 0x9f5 +#define mmMC_ARB_MAX_LAT_CID 0x9f6 +#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7 +#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8 +#define mmMC_ARB_SSM 0x9f9 +#define mmMC_ARB_CG 0x9fa +#define mmMC_ARB_WCDR 0x9fb +#define mmMC_ARB_DRAM_TIMING_1 0x9fc +#define mmMC_ARB_BUSY_STATUS 0x9fd +#define mmMC_ARB_DRAM_TIMING2_1 0x9ff +#define mmMC_ARB_BURST_TIME 0xa02 +#define mmMC_CITF_XTRA_ENABLE 0x96d +#define mmCC_MC_MAX_CHANNEL 0x96e +#define mmMC_CG_CONFIG 0x96f +#define mmMC_CITF_CNTL 0x970 +#define mmMC_CITF_CREDITS_VM 0x971 +#define mmMC_CITF_CREDITS_ARB_RD 0x972 +#define mmMC_CITF_CREDITS_ARB_WR 0x973 +#define mmMC_CITF_DAGB_CNTL 0x974 +#define mmMC_CITF_INT_CREDITS 0x975 +#define mmMC_CITF_RET_MODE 0x976 +#define mmMC_CITF_DAGB_DLY 0x977 +#define mmMC_RD_GRP_EXT 0x978 +#define mmMC_WR_GRP_EXT 0x979 +#define mmMC_CITF_REMREQ 0x97a +#define mmMC_WR_TC0 0x97b +#define mmMC_WR_TC1 0x97c +#define mmMC_CITF_INT_CREDITS_WR 0x97d +#define mmMC_CITF_WTM_RD_CNTL 0x97f +#define mmMC_CITF_WTM_WR_CNTL 0x980 +#define mmMC_RD_CB 0x981 +#define mmMC_RD_DB 0x982 +#define mmMC_RD_TC0 0x983 +#define mmMC_RD_TC1 0x984 +#define mmMC_RD_HUB 0x985 +#define mmMC_WR_CB 0x986 +#define mmMC_WR_DB 0x987 +#define mmMC_WR_HUB 0x988 +#define mmMC_CITF_CREDITS_XBAR 0x989 +#define mmMC_RD_GRP_LCL 0x98a +#define mmMC_WR_GRP_LCL 0x98b +#define mmMC_CITF_PERF_MON_CNTL2 0x98e +#define mmMC_CITF_PERF_MON_RSLT2 0x991 +#define mmMC_CITF_MISC_RD_CG 0x992 +#define mmMC_CITF_MISC_WR_CG 0x993 +#define mmMC_CITF_MISC_VM_CG 0x994 +#define mmMC_HUB_MISC_POWER 0x82d +#define mmMC_HUB_MISC_HUB_CG 0x82e +#define mmMC_HUB_MISC_VM_CG 0x82f +#define mmMC_HUB_MISC_SIP_CG 0x830 +#define mmMC_HUB_MISC_DBG 0x831 +#define mmMC_HUB_MISC_STATUS 0x832 +#define mmMC_HUB_MISC_OVERRIDE 0x833 +#define mmMC_HUB_MISC_FRAMING 0x834 +#define mmMC_HUB_WDP_CNTL 0x835 +#define mmMC_HUB_WDP_ERR 0x836 +#define mmMC_HUB_WDP_BP 0x837 +#define mmMC_HUB_WDP_STATUS 0x838 +#define mmMC_HUB_RDREQ_STATUS 0x839 +#define mmMC_HUB_WRRET_STATUS 0x83a +#define mmMC_HUB_RDREQ_CNTL 0x83b +#define mmMC_HUB_WRRET_CNTL 0x83c +#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d +#define mmMC_HUB_WDP_WTM_CNTL 0x83e +#define mmMC_HUB_WDP_CREDITS 0x83f +#define mmMC_HUB_WDP_MGPU2 0x840 +#define mmMC_HUB_WDP_GBL0 0x841 +#define mmMC_HUB_WDP_GBL1 0x842 +#define mmMC_HUB_WDP_MGPU 0x843 +#define mmMC_HUB_RDREQ_CREDITS 0x844 +#define mmMC_HUB_RDREQ_CREDITS2 0x845 +#define mmMC_HUB_SHARED_DAGB_DLY 0x846 +#define mmMC_HUB_MISC_IDLE_STATUS 0x847 +#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848 +#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849 +#define mmMC_HUB_WDP_SH2 0x84d +#define mmMC_HUB_WDP_SH3 0x84e +#define mmMC_HUB_RDREQ_IA0 0x84f +#define mmMC_HUB_RDREQ_IA1 0x850 +#define mmMC_HUB_RDREQ_MCDW 0x851 +#define mmMC_HUB_RDREQ_MCDX 0x852 +#define mmMC_HUB_RDREQ_MCDY 0x853 +#define mmMC_HUB_RDREQ_MCDZ 0x854 +#define mmMC_HUB_RDREQ_SIP 0x855 +#define mmMC_HUB_RDREQ_GBL0 0x856 +#define mmMC_HUB_RDREQ_GBL1 0x857 +#define mmMC_HUB_RDREQ_SMU 0x858 +#define mmMC_HUB_RDREQ_CPG 0x859 +#define mmMC_HUB_RDREQ_SDMA0 0x85a +#define mmMC_HUB_RDREQ_HDP 0x85b +#define mmMC_HUB_RDREQ_SDMA1 0x85c +#define mmMC_HUB_RDREQ_RLC 0x85d +#define mmMC_HUB_RDREQ_SEM 0x85e +#define mmMC_HUB_RDREQ_VCE 0x85f +#define mmMC_HUB_RDREQ_UMC 0x860 +#define mmMC_HUB_RDREQ_UVD 0x861 +#define mmMC_HUB_RDREQ_IA 0x862 +#define mmMC_HUB_RDREQ_DMIF 0x863 +#define mmMC_HUB_RDREQ_MCIF 0x864 +#define mmMC_HUB_RDREQ_VMC 0x865 +#define mmMC_HUB_RDREQ_VCEU 0x866 +#define mmMC_HUB_WDP_MCDW 0x867 +#define mmMC_HUB_WDP_MCDX 0x868 +#define mmMC_HUB_WDP_MCDY 0x869 +#define mmMC_HUB_WDP_MCDZ 0x86a +#define mmMC_HUB_WDP_SIP 0x86b +#define mmMC_HUB_WDP_CPG 0x86c +#define mmMC_HUB_WDP_SDMA1 0x86d +#define mmMC_HUB_WDP_SH0 0x86e +#define mmMC_HUB_WDP_MCIF 0x86f +#define mmMC_HUB_WDP_VCE 0x870 +#define mmMC_HUB_WDP_XDP 0x871 +#define mmMC_HUB_WDP_IH 0x872 +#define mmMC_HUB_WDP_RLC 0x873 +#define mmMC_HUB_WDP_SEM 0x874 +#define mmMC_HUB_WDP_SMU 0x875 +#define mmMC_HUB_WDP_SH1 0x876 +#define mmMC_HUB_WDP_UMC 0x877 +#define mmMC_HUB_WDP_UVD 0x878 +#define mmMC_HUB_WDP_HDP 0x879 +#define mmMC_HUB_WDP_SDMA0 0x87a +#define mmMC_HUB_WRRET_MCDW 0x87b +#define mmMC_HUB_WRRET_MCDX 0x87c +#define mmMC_HUB_WRRET_MCDY 0x87d +#define mmMC_HUB_WRRET_MCDZ 0x87e +#define mmMC_HUB_WDP_VCEU 0x87f +#define mmMC_HUB_WDP_XDMAM 0x880 +#define mmMC_HUB_WDP_XDMA 0x881 +#define mmMC_HUB_RDREQ_XDMAM 0x882 +#define mmMC_HUB_RDREQ_ACPG 0x883 +#define mmMC_HUB_RDREQ_ACPO 0x884 +#define mmMC_HUB_RDREQ_SAM 0x885 +#define mmMC_HUB_WDP_ACPG 0x886 +#define mmMC_HUB_WDP_ACPO 0x887 +#define mmMC_HUB_WDP_SAM 0x888 +#define mmMC_HUB_RDREQ_CPC 0x889 +#define mmMC_HUB_RDREQ_CPF 0x88a +#define mmMC_HUB_WDP_CPC 0x88b +#define mmMC_HUB_WDP_CPF 0x88c +#define mmMC_RPB_CONF 0x94d +#define mmMC_RPB_IF_CONF 0x94e +#define mmMC_RPB_DBG1 0x94f +#define mmMC_RPB_EFF_CNTL 0x950 +#define mmMC_RPB_ARB_CNTL 0x951 +#define mmMC_RPB_BIF_CNTL 0x952 +#define mmMC_RPB_WR_SWITCH_CNTL 0x953 +#define mmMC_RPB_WR_COMBINE_CNTL 0x954 +#define mmMC_RPB_RD_SWITCH_CNTL 0x955 +#define mmMC_RPB_CID_QUEUE_WR 0x956 +#define mmMC_RPB_CID_QUEUE_RD 0x957 +#define mmMC_RPB_PERF_COUNTER_CNTL 0x958 +#define mmMC_RPB_PERF_COUNTER_STATUS 0x959 +#define mmMC_RPB_CID_QUEUE_EX 0x95a +#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b +#define mmMC_SHARED_CHMAP 0x801 +#define mmMC_SHARED_CHREMAP 0x802 +#define mmMC_RD_GRP_GFX 0x803 +#define mmMC_WR_GRP_GFX 0x804 +#define mmMC_RD_GRP_SYS 0x805 +#define mmMC_WR_GRP_SYS 0x806 +#define mmMC_RD_GRP_OTH 0x807 +#define mmMC_WR_GRP_OTH 0x808 +#define mmMC_VM_FB_LOCATION 0x809 +#define mmMC_VM_AGP_TOP 0x80a +#define mmMC_VM_AGP_BOT 0x80b +#define mmMC_VM_AGP_BASE 0x80c +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f +#define mmMC_VM_DC_WRITE_CNTL 0x810 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818 +#define mmMC_VM_MX_L1_TLB_CNTL 0x819 +#define mmMC_VM_FB_OFFSET 0x81a +#define mmMC_VM_STEERING 0x81b +#define mmMC_CONFIG_MCD 0x828 +#define mmMC_CG_CONFIG_MCD 0x829 +#define mmMC_MEM_POWER_LS 0x82a +#define mmMC_SHARED_BLACKOUT_CNTL 0x82b +#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891 +#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893 +#define mmMC_VM_MB_L1_TLB0_STATUS 0x895 +#define mmMC_VM_MB_L1_TLB1_STATUS 0x896 +#define mmMC_VM_MB_L1_TLB2_STATUS 0x897 +#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1 +#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5 +#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6 +#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998 +#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999 +#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a +#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b +#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c +#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d +#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4 +#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7 +#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8 +#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd +#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce +#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf +#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0 +#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1 +#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2 +#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3 +#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4 +#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5 +#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da +#define mmMC_XPB_RTR_DEST_MAP0 0x8db +#define mmMC_XPB_RTR_DEST_MAP1 0x8dc +#define mmMC_XPB_RTR_DEST_MAP2 0x8dd +#define mmMC_XPB_RTR_DEST_MAP3 0x8de +#define mmMC_XPB_RTR_DEST_MAP4 0x8df +#define mmMC_XPB_RTR_DEST_MAP5 0x8e0 +#define mmMC_XPB_RTR_DEST_MAP6 0x8e1 +#define mmMC_XPB_RTR_DEST_MAP7 0x8e2 +#define mmMC_XPB_RTR_DEST_MAP8 0x8e3 +#define mmMC_XPB_RTR_DEST_MAP9 0x8e4 +#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5 +#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6 +#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7 +#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8 +#define mmMC_XPB_CLG_CFG0 0x8e9 +#define mmMC_XPB_CLG_CFG1 0x8ea +#define mmMC_XPB_CLG_CFG2 0x8eb +#define mmMC_XPB_CLG_CFG3 0x8ec +#define mmMC_XPB_CLG_CFG4 0x8ed +#define mmMC_XPB_CLG_CFG5 0x8ee +#define mmMC_XPB_CLG_CFG6 0x8ef +#define mmMC_XPB_CLG_CFG7 0x8f0 +#define mmMC_XPB_CLG_CFG8 0x8f1 +#define mmMC_XPB_CLG_CFG9 0x8f2 +#define mmMC_XPB_CLG_CFG10 0x8f3 +#define mmMC_XPB_CLG_CFG11 0x8f4 +#define mmMC_XPB_CLG_CFG12 0x8f5 +#define mmMC_XPB_CLG_CFG13 0x8f6 +#define mmMC_XPB_CLG_CFG14 0x8f7 +#define mmMC_XPB_CLG_CFG15 0x8f8 +#define mmMC_XPB_CLG_CFG16 0x8f9 +#define mmMC_XPB_CLG_CFG17 0x8fa +#define mmMC_XPB_CLG_CFG18 0x8fb +#define mmMC_XPB_CLG_CFG19 0x8fc +#define mmMC_XPB_CLG_EXTRA 0x8fd +#define mmMC_XPB_LB_ADDR 0x8fe +#define mmMC_XPB_UNC_THRESH_HST 0x8ff +#define mmMC_XPB_UNC_THRESH_SID 0x900 +#define mmMC_XPB_WCB_STS 0x901 +#define mmMC_XPB_WCB_CFG 0x902 +#define mmMC_XPB_P2P_BAR_CFG 0x903 +#define mmMC_XPB_P2P_BAR0 0x904 +#define mmMC_XPB_P2P_BAR1 0x905 +#define mmMC_XPB_P2P_BAR2 0x906 +#define mmMC_XPB_P2P_BAR3 0x907 +#define mmMC_XPB_P2P_BAR4 0x908 +#define mmMC_XPB_P2P_BAR5 0x909 +#define mmMC_XPB_P2P_BAR6 0x90a +#define mmMC_XPB_P2P_BAR7 0x90b +#define mmMC_XPB_P2P_BAR_SETUP 0x90c +#define mmMC_XPB_P2P_BAR_DEBUG 0x90d +#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e +#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f +#define mmMC_XPB_PEER_SYS_BAR0 0x910 +#define mmMC_XPB_PEER_SYS_BAR1 0x911 +#define mmMC_XPB_PEER_SYS_BAR2 0x912 +#define mmMC_XPB_PEER_SYS_BAR3 0x913 +#define mmMC_XPB_PEER_SYS_BAR4 0x914 +#define mmMC_XPB_PEER_SYS_BAR5 0x915 +#define mmMC_XPB_PEER_SYS_BAR6 0x916 +#define mmMC_XPB_PEER_SYS_BAR7 0x917 +#define mmMC_XPB_PEER_SYS_BAR8 0x918 +#define mmMC_XPB_PEER_SYS_BAR9 0x919 +#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a +#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b +#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c +#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d +#define mmMC_XPB_CLK_GAT 0x91e +#define mmMC_XPB_INTF_CFG 0x91f +#define mmMC_XPB_INTF_STS 0x920 +#define mmMC_XPB_PIPE_STS 0x921 +#define mmMC_XPB_SUB_CTRL 0x922 +#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923 +#define mmMC_XPB_PERF_KNOBS 0x924 +#define mmMC_XPB_STICKY 0x925 +#define mmMC_XPB_STICKY_W1C 0x926 +#define mmMC_XPB_MISC_CFG 0x927 +#define mmMC_XPB_CLG_CFG20 0x928 +#define mmMC_XPB_CLG_CFG21 0x929 +#define mmMC_XPB_CLG_CFG22 0x92a +#define mmMC_XPB_CLG_CFG23 0x92b +#define mmMC_XPB_CLG_CFG24 0x92c +#define mmMC_XPB_CLG_CFG25 0x92d +#define mmMC_XPB_CLG_CFG26 0x92e +#define mmMC_XPB_CLG_CFG27 0x92f +#define mmMC_XPB_CLG_CFG28 0x930 +#define mmMC_XPB_CLG_CFG29 0x931 +#define mmMC_XPB_CLG_CFG30 0x932 +#define mmMC_XPB_CLG_CFG31 0x933 +#define mmMC_XPB_INTF_CFG2 0x934 +#define mmMC_XPB_CLG_EXTRA_RD 0x935 +#define mmMC_XPB_CLG_CFG32 0x936 +#define mmMC_XPB_CLG_CFG33 0x937 +#define mmMC_XPB_CLG_CFG34 0x938 +#define mmMC_XPB_CLG_CFG35 0x939 +#define mmMC_XPB_CLG_CFG36 0x93a +#define mmMC_XBAR_ADDR_DEC 0xc80 +#define mmMC_XBAR_REMOTE 0xc81 +#define mmMC_XBAR_WRREQ_CREDIT 0xc82 +#define mmMC_XBAR_RDREQ_CREDIT 0xc83 +#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84 +#define mmMC_XBAR_WRRET_CREDIT1 0xc85 +#define mmMC_XBAR_WRRET_CREDIT2 0xc86 +#define mmMC_XBAR_RDRET_CREDIT1 0xc87 +#define mmMC_XBAR_RDRET_CREDIT2 0xc88 +#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89 +#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a +#define mmMC_XBAR_CHTRIREMAP 0xc8b +#define mmMC_XBAR_TWOCHAN 0xc8c +#define mmMC_XBAR_ARB 0xc8d +#define mmMC_XBAR_ARB_MAX_BURST 0xc8e +#define mmMC_XBAR_PERF_MON_CNTL0 0xc8f +#define mmMC_XBAR_PERF_MON_CNTL1 0xc90 +#define mmMC_XBAR_PERF_MON_CNTL2 0xc91 +#define mmMC_XBAR_PERF_MON_RSLT0 0xc92 +#define mmMC_XBAR_PERF_MON_RSLT1 0xc93 +#define mmMC_XBAR_PERF_MON_RSLT2 0xc94 +#define mmMC_XBAR_PERF_MON_RSLT3 0xc95 +#define mmMC_XBAR_PERF_MON_MAX_THSH 0xc96 +#define mmMC_XBAR_SPARE0 0xc97 +#define mmMC_XBAR_SPARE1 0xc98 +#define mmMC_CITF_PERFCOUNTER_LO 0x7a0 +#define mmMC_HUB_PERFCOUNTER_LO 0x7a1 +#define mmMC_RPB_PERFCOUNTER_LO 0x7a2 +#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3 +#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4 +#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5 +#define mmMC_ARB_PERFCOUNTER_LO 0x7a6 +#define mmATC_PERFCOUNTER_LO 0x7a7 +#define mmMC_CITF_PERFCOUNTER_HI 0x7a8 +#define mmMC_HUB_PERFCOUNTER_HI 0x7a9 +#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa +#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab +#define mmMC_RPB_PERFCOUNTER_HI 0x7ac +#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad +#define mmMC_ARB_PERFCOUNTER_HI 0x7ae +#define mmATC_PERFCOUNTER_HI 0x7af +#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0 +#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1 +#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2 +#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3 +#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4 +#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5 +#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6 +#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7 +#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8 +#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9 +#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba +#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb +#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc +#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd +#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be +#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf +#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0 +#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1 +#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2 +#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3 +#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4 +#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5 +#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6 +#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7 +#define mmATC_PERFCOUNTER0_CFG 0x7c8 +#define mmATC_PERFCOUNTER1_CFG 0x7c9 +#define mmATC_PERFCOUNTER2_CFG 0x7ca +#define mmATC_PERFCOUNTER3_CFG 0x7cb +#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc +#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd +#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce +#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf +#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0 +#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1 +#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2 +#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3 +#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4 +#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5 +#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6 +#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7 +#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8 +#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9 +#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da +#define mmMC_ARB_PERF_MON_CNTL0_ECC 0x7db +#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0 +#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1 +#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2 +#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3 +#define mmATC_VM_APERTURE0_CNTL 0xcc4 +#define mmATC_VM_APERTURE1_CNTL 0xcc5 +#define mmATC_VM_APERTURE0_CNTL2 0xcc6 +#define mmATC_VM_APERTURE1_CNTL2 0xcc7 +#define mmATC_ATS_CNTL 0xcc9 +#define mmATC_ATS_DEBUG 0xcca +#define mmATC_ATS_FAULT_DEBUG 0xccb +#define mmATC_ATS_STATUS 0xccc +#define mmATC_ATS_FAULT_CNTL 0xccd +#define mmATC_ATS_FAULT_STATUS_INFO 0xcce +#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf +#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0 +#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1 +#define mmATC_MISC_CG 0xcd4 +#define mmATC_L2_CNTL 0xcd5 +#define mmATC_L2_CNTL2 0xcd6 +#define mmATC_L2_DEBUG 0xcd7 +#define mmATC_L2_DEBUG2 0xcd8 +#define mmATC_L1_CNTL 0xcdc +#define mmATC_L1_ADDRESS_OFFSET 0xcdd +#define mmATC_L1RD_DEBUG_TLB 0xcde +#define mmATC_L1WR_DEBUG_TLB 0xcdf +#define mmATC_L1RD_STATUS 0xce0 +#define mmATC_L1WR_STATUS 0xce1 +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6 +#define mmATC_VMID0_PASID_MAPPING 0xce7 +#define mmATC_VMID1_PASID_MAPPING 0xce8 +#define mmATC_VMID2_PASID_MAPPING 0xce9 +#define mmATC_VMID3_PASID_MAPPING 0xcea +#define mmATC_VMID4_PASID_MAPPING 0xceb +#define mmATC_VMID5_PASID_MAPPING 0xcec +#define mmATC_VMID6_PASID_MAPPING 0xced +#define mmATC_VMID7_PASID_MAPPING 0xcee +#define mmATC_VMID8_PASID_MAPPING 0xcef +#define mmATC_VMID9_PASID_MAPPING 0xcf0 +#define mmATC_VMID10_PASID_MAPPING 0xcf1 +#define mmATC_VMID11_PASID_MAPPING 0xcf2 +#define mmATC_VMID12_PASID_MAPPING 0xcf3 +#define mmATC_VMID13_PASID_MAPPING 0xcf4 +#define mmATC_VMID14_PASID_MAPPING 0xcf5 +#define mmATC_VMID15_PASID_MAPPING 0xcf6 +#define mmGMCON_RENG_RAM_INDEX 0xd40 +#define mmGMCON_RENG_RAM_DATA 0xd41 +#define mmGMCON_RENG_EXECUTE 0xd42 +#define mmGMCON_MISC 0xd43 +#define mmGMCON_MISC2 0xd44 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49 +#define mmGMCON_PERF_MON_CNTL0 0xd4a +#define mmGMCON_PERF_MON_CNTL1 0xd4b +#define mmGMCON_PERF_MON_RSLT0 0xd4c +#define mmGMCON_PERF_MON_RSLT1 0xd4d +#define mmGMCON_PGFSM_CONFIG 0xd4e +#define mmGMCON_PGFSM_WRITE 0xd4f +#define mmGMCON_PGFSM_READ 0xd50 +#define mmGMCON_MISC3 0xd51 +#define mmGMCON_MASK 0xd52 +#define mmGMCON_DEBUG 0xd5f +#define mmVM_L2_CNTL 0x500 +#define mmVM_L2_CNTL2 0x501 +#define mmVM_L2_CNTL3 0x502 +#define mmVM_L2_STATUS 0x503 +#define mmVM_CONTEXT0_CNTL 0x504 +#define mmVM_CONTEXT1_CNTL 0x505 +#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506 +#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507 +#define mmVM_CONTEXT0_CNTL2 0x50c +#define mmVM_CONTEXT1_CNTL2 0x50d +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 +#define mmVM_INVALIDATE_REQUEST 0x51e +#define mmVM_INVALIDATE_RESPONSE 0x51f +#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c +#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d +#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e +#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f +#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530 +#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531 +#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532 +#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533 +#define mmVM_PRT_CNTL 0x534 +#define mmVM_CONTEXTS_DISABLE 0x535 +#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536 +#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 +#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538 +#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539 +#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e +#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f +#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 +#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 +#define mmVM_FAULT_CLIENT_ID 0x54e +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 +#define mmVM_DEBUG 0x56f +#define mmVM_L2_CG 0x570 +#define mmVM_L2_BANK_SELECT_MASKA 0x572 +#define mmVM_L2_BANK_SELECT_MASKB 0x573 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577 +#define mmMC_ARB_HARSH_EN_RD 0xdc0 +#define mmMC_ARB_HARSH_EN_WR 0xdc1 +#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2 +#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3 +#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4 +#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5 +#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6 +#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7 +#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8 +#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9 +#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca +#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb +#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc +#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd +#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce +#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf +#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0 +#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1 +#define mmMC_ARB_HARSH_SAT0_RD 0xdd2 +#define mmMC_ARB_HARSH_SAT0_WR 0xdd3 +#define mmMC_ARB_HARSH_SAT1_RD 0xdd4 +#define mmMC_ARB_HARSH_SAT1_WR 0xdd5 +#define mmMC_ARB_HARSH_CTL_RD 0xdd6 +#define mmMC_ARB_HARSH_CTL_WR 0xdd7 +#define mmMC_FUS_DRAM0_CS0_BASE 0xa05 +#define mmMC_FUS_DRAM1_CS0_BASE 0xa06 +#define mmMC_FUS_DRAM0_CS1_BASE 0xa07 +#define mmMC_FUS_DRAM1_CS1_BASE 0xa08 +#define mmMC_FUS_DRAM0_CS2_BASE 0xa09 +#define mmMC_FUS_DRAM1_CS2_BASE 0xa0a +#define mmMC_FUS_DRAM0_CS3_BASE 0xa0b +#define mmMC_FUS_DRAM1_CS3_BASE 0xa0c +#define mmMC_FUS_DRAM0_CS01_MASK 0xa0d +#define mmMC_FUS_DRAM1_CS01_MASK 0xa0e +#define mmMC_FUS_DRAM0_CS23_MASK 0xa0f +#define mmMC_FUS_DRAM1_CS23_MASK 0xa10 +#define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING 0xa11 +#define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING 0xa12 +#define mmMC_FUS_DRAM0_CTL_BASE 0xa13 +#define mmMC_FUS_DRAM1_CTL_BASE 0xa14 +#define mmMC_FUS_DRAM0_CTL_LIMIT 0xa15 +#define mmMC_FUS_DRAM1_CTL_LIMIT 0xa16 +#define mmMC_FUS_DRAM_CTL_HIGH_01 0xa17 +#define mmMC_FUS_DRAM_CTL_HIGH_23 0xa18 +#define mmMC_FUS_DRAM_MODE 0xa19 +#define mmMC_FUS_DRAM_APER_BASE 0xa1a +#define mmMC_FUS_DRAM_APER_TOP 0xa1b +#define mmMC_FUS_DRAM_C6SAVE_APER_BASE 0xa1c +#define mmMC_FUS_DRAM_C6SAVE_APER_TOP 0xa1d +#define mmMC_FUS_DRAM_APER_DEF 0xa1e +#define mmMC_FUS_ARB_GARLIC_ISOC_PRI 0xa1f +#define mmMC_FUS_ARB_GARLIC_CNTL 0xa20 +#define mmMC_FUS_ARB_GARLIC_WR_PRI 0xa21 +#define mmMC_FUS_ARB_GARLIC_WR_PRI2 0xa22 +#define mmMC_CG_DATAPORT 0xa32 +#define mmCHUB_ATC_L1_DEBUG_TLB 0x8c00 +#define mmCHUB_ATC_L1_STATUS 0x8c01 + +#endif /* GMC_7_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h new file mode 100644 index 000000000000..64d3c2356e09 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h @@ -0,0 +1,6116 @@ +/* + * GMC_7_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_7_0_SH_MASK_H +#define GMC_7_0_SH_MASK_H + +#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 +#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 +#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 +#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 +#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 +#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 +#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 +#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 +#define MC_CONFIG__MC_RD_ENABLE_MASK 0x30 +#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4 +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000 +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13 +#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff +#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0 +#define MC_ARB_FED_CNTL__MODE_MASK 0x3 +#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0 +#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc +#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2 +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10 +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4 +#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20 +#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5 +#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40 +#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6 +#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80 +#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7 +#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1 +#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0 +#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2 +#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1 +#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4 +#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2 +#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8 +#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3 +#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10 +#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4 +#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20 +#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5 +#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40 +#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6 +#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80 +#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9 +#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400 +#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa +#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800 +#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd +#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000 +#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe +#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000 +#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11 +#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000 +#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15 +#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000 +#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19 +#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000 +#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d +#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf +#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0 +#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10 +#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4 +#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20 +#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5 +#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40 +#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6 +#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffff80 +#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0x7 +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3 +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0 +#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4 +#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2 +#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18 +#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3 +#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20 +#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5 +#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff +#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0 +#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00 +#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8 +#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000 +#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10 +#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000 +#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18 +#define MC_ARB_GECC2__ENABLE_MASK 0x1 +#define MC_ARB_GECC2__ENABLE__SHIFT 0x0 +#define MC_ARB_GECC2__ECC_MODE_MASK 0x6 +#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1 +#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18 +#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3 +#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60 +#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5 +#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780 +#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7 +#define MC_ARB_GECC2__READ_ERR_MASK 0x3800 +#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb +#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000 +#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe +#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000 +#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf +#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000 +#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15 +#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000 +#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18 +#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf +#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0 +#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0 +#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4 +#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00 +#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8 +#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000 +#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc +#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000 +#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10 +#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000 +#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14 +#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000 +#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18 +#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000 +#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c +#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf +#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0 +#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0 +#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4 +#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00 +#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8 +#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000 +#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc +#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1 +#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0 +#define MC_ARB_MISC3__TBD_FIELD_MASK 0xfffffffe +#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x1 +#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0xf +#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x0 +#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x1f0 +#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x4 +#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x200 +#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x9 +#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x400 +#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa +#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800 +#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0xb +#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x1000 +#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0xc +#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x2000 +#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0xd +#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x4000 +#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0xe +#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff +#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0 +#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1 +#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0 +#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2 +#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1 +#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc +#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2 +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10 +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4 +#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20 +#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5 +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40 +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6 +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80 +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7 +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100 +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800 +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000 +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17 +#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000 +#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18 +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000 +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5 +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0 +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6 +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000 +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc +#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000 +#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19 +#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1 +#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0 +#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e +#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1 +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80 +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7 +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000 +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa +#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800 +#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb +#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000 +#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc +#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000 +#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd +#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000 +#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe +#define MC_ARB_MISC2__GECC_MASK 0x40000 +#define MC_ARB_MISC2__GECC__SHIFT 0x12 +#define MC_ARB_MISC2__GECC_RST_MASK 0x80000 +#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13 +#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000 +#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14 +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000 +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15 +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000 +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19 +#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000 +#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c +#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000 +#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000 +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000 +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f +#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1 +#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0 +#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2 +#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1 +#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4 +#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2 +#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8 +#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3 +#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800 +#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb +#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000 +#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13 +#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000 +#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14 +#define MC_ARB_MISC__CALI_RATES_MASK 0x600000 +#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15 +#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000 +#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17 +#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000 +#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18 +#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000 +#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19 +#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000 +#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a +#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000 +#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e +#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000 +#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f +#define MC_ARB_BANKMAP__BANK0_MASK 0xf +#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0 +#define MC_ARB_BANKMAP__BANK1_MASK 0xf0 +#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4 +#define MC_ARB_BANKMAP__BANK2_MASK 0xf00 +#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8 +#define MC_ARB_BANKMAP__BANK3_MASK 0xf000 +#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc +#define MC_ARB_BANKMAP__RANK_MASK 0xf0000 +#define MC_ARB_BANKMAP__RANK__SHIFT 0x10 +#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3 +#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0 +#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4 +#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2 +#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38 +#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3 +#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0 +#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6 +#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100 +#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8 +#define MC_ARB_RAMCFG__RSV_1_MASK 0x200 +#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9 +#define MC_ARB_RAMCFG__RSV_2_MASK 0x400 +#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa +#define MC_ARB_RAMCFG__RSV_3_MASK 0x800 +#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb +#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000 +#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc +#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000 +#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd +#define MC_ARB_POP__ENABLE_ARB_MASK 0x1 +#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0 +#define MC_ARB_POP__SPEC_OPEN_MASK 0x2 +#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1 +#define MC_ARB_POP__POP_DEPTH_MASK 0x3c +#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2 +#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0 +#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6 +#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000 +#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc +#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000 +#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf +#define MC_ARB_POP__QUICK_STOP_MASK 0x20000 +#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11 +#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000 +#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12 +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000 +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13 +#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff +#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0 +#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00 +#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8 +#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000 +#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10 +#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000 +#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11 +#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff +#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0 +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100 +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8 +#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200 +#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9 +#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00 +#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa +#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000 +#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10 +#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000 +#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18 +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0 +#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0 +#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4 +#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000 +#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc +#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff +#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00 +#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000 +#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18 +#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff +#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00 +#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000 +#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18 +#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3 +#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0 +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4 +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa +#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800 +#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb +#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000 +#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc +#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000 +#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd +#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3 +#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0 +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4 +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa +#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800 +#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb +#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000 +#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc +#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000 +#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd +#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3 +#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0 +#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc +#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2 +#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30 +#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4 +#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0 +#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6 +#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300 +#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8 +#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00 +#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa +#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000 +#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc +#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000 +#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000 +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10 +#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3 +#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0 +#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc +#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2 +#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30 +#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4 +#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0 +#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6 +#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300 +#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8 +#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00 +#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa +#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000 +#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc +#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000 +#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000 +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10 +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1 +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0 +#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6 +#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1 +#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8 +#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3 +#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10 +#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4 +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1 +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0 +#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6 +#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1 +#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8 +#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3 +#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10 +#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4 +#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff +#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff +#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff +#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff +#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3 +#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc +#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2 +#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30 +#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4 +#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0 +#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6 +#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300 +#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8 +#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00 +#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa +#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000 +#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc +#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000 +#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe +#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000 +#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10 +#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000 +#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11 +#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000 +#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12 +#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000 +#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13 +#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000 +#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14 +#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000 +#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15 +#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000 +#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16 +#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000 +#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17 +#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18 +#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19 +#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a +#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b +#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c +#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d +#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e +#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f +#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3 +#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc +#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2 +#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30 +#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4 +#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0 +#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6 +#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300 +#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8 +#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00 +#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa +#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000 +#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc +#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000 +#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe +#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000 +#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10 +#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000 +#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11 +#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000 +#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12 +#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000 +#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13 +#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000 +#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14 +#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000 +#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15 +#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000 +#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16 +#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000 +#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17 +#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18 +#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19 +#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a +#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b +#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c +#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d +#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e +#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f +#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1 +#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0 +#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e +#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1 +#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0 +#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6 +#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800 +#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb +#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff +#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0 +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3 +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0 +#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4 +#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2 +#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8 +#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3 +#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10 +#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4 +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20 +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5 +#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40 +#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6 +#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80 +#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7 +#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300 +#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8 +#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400 +#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa +#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800 +#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb +#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000 +#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc +#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000 +#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd +#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000 +#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000 +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf +#define MC_ARB_PM_CNTL__RSV_0_MASK 0x30000 +#define MC_ARB_PM_CNTL__RSV_0__SHIFT 0x10 +#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000 +#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12 +#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000 +#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13 +#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000 +#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14 +#define MC_ARB_PM_CNTL__RSV_1_MASK 0x1000000 +#define MC_ARB_PM_CNTL__RSV_1__SHIFT 0x18 +#define MC_ARB_PM_CNTL__RSV_2_MASK 0x2000000 +#define MC_ARB_PM_CNTL__RSV_2__SHIFT 0x19 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4 +#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100 +#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8 +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200 +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9 +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4 +#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100 +#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8 +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200 +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9 +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa +#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff +#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0 +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00 +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8 +#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000 +#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10 +#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000 +#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11 +#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000 +#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12 +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000 +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13 +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000 +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14 +#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000 +#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15 +#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff +#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0 +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00 +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8 +#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000 +#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10 +#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000 +#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11 +#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000 +#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12 +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000 +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13 +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000 +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14 +#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000 +#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15 +#define MC_ARB_REMREQ__RD_WATER_MASK 0xff +#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0 +#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00 +#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8 +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000 +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10 +#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000 +#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14 +#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000 +#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18 +#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1 +#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0 +#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2 +#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1 +#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4 +#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2 +#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8 +#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3 +#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10 +#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4 +#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20 +#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5 +#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40 +#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6 +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80 +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7 +#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00 +#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8 +#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000 +#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf +#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff +#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0 +#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00 +#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8 +#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000 +#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10 +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000 +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18 +#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff +#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0 +#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00 +#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8 +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000 +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10 +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000 +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18 +#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff +#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0 +#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00 +#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8 +#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000 +#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10 +#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000 +#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13 +#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff +#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0 +#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff +#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0 +#define MC_ARB_SSM__FORMAT_MASK 0x1f +#define MC_ARB_SSM__FORMAT__SHIFT 0x0 +#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff +#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0 +#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00 +#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8 +#define MC_ARB_CG__RSV_0_MASK 0xff0000 +#define MC_ARB_CG__RSV_0__SHIFT 0x10 +#define MC_ARB_CG__RSV_1_MASK 0xff000000 +#define MC_ARB_CG__RSV_1__SHIFT 0x18 +#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x1 +#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x0 +#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x2 +#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x1 +#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x7c +#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x2 +#define MC_ARB_WCDR__IDLE_BURST_MASK 0x1f80 +#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x7 +#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x2000 +#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0xd +#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0xc000 +#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0xe +#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x10000 +#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x10 +#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x20000 +#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x11 +#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x3c0000 +#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x12 +#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x1c00000 +#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x16 +#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x2000000 +#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x19 +#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x4000000 +#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x1a +#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x8000000 +#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x1b +#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000 +#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x1c +#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff +#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00 +#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000 +#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18 +#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1 +#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0 +#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2 +#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1 +#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4 +#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2 +#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8 +#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3 +#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10 +#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4 +#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20 +#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5 +#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40 +#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6 +#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80 +#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7 +#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100 +#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8 +#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200 +#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9 +#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400 +#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa +#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800 +#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb +#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000 +#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc +#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000 +#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd +#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000 +#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe +#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000 +#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf +#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000 +#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10 +#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000 +#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11 +#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000 +#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12 +#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000 +#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13 +#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000 +#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14 +#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000 +#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15 +#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000 +#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16 +#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000 +#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17 +#define MC_ARB_BUSY_STATUS__WCDR0_MASK 0x1000000 +#define MC_ARB_BUSY_STATUS__WCDR0__SHIFT 0x18 +#define MC_ARB_BUSY_STATUS__WCDR1_MASK 0x2000000 +#define MC_ARB_BUSY_STATUS__WCDR1__SHIFT 0x19 +#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000 +#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a +#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000 +#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b +#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000 +#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c +#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000 +#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d +#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000 +#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e +#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000 +#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00 +#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000 +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18 +#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f +#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0 +#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0 +#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5 +#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00 +#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa +#define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000 +#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf +#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1 +#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0 +#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2 +#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1 +#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4 +#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2 +#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8 +#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3 +#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10 +#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4 +#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00 +#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8 +#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000 +#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc +#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000 +#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd +#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000 +#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf +#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000 +#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11 +#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000 +#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13 +#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000 +#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15 +#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000 +#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17 +#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000 +#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19 +#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000 +#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a +#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000 +#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b +#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000 +#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c +#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000 +#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d +#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e +#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1 +#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1 +#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 +#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2 +#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 +#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4 +#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 +#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 +#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 +#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30 +#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4 +#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0 +#define MC_CG_CONFIG__INDEX__SHIFT 0x6 +#define MC_CITF_CNTL__IGNOREPM_MASK 0x4 +#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2 +#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8 +#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3 +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30 +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4 +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40 +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6 +#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x80 +#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7 +#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x100 +#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x8 +#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f +#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0 +#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0 +#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6 +#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff +#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00 +#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8 +#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000 +#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10 +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000 +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18 +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000 +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19 +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00 +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8 +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x10000 +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x10 +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x20000 +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x11 +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1 +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0 +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1 +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20 +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5 +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0 +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6 +#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f +#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12 +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000 +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18 +#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1 +#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0 +#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2 +#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1 +#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4 +#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2 +#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8 +#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3 +#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10 +#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4 +#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20 +#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5 +#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f +#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0 +#define MC_CITF_DAGB_DLY__CLI_MASK 0x1f0000 +#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10 +#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000 +#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18 +#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf +#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0 +#define MC_RD_GRP_EXT__TC0_MASK 0xf0 +#define MC_RD_GRP_EXT__TC0__SHIFT 0x4 +#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf +#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0 +#define MC_WR_GRP_EXT__TC0_MASK 0xf0 +#define MC_WR_GRP_EXT__TC0__SHIFT 0x4 +#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f +#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0 +#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80 +#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7 +#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000 +#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe +#define MC_WR_TC0__ENABLE_MASK 0x1 +#define MC_WR_TC0__ENABLE__SHIFT 0x0 +#define MC_WR_TC0__PRESCALE_MASK 0x6 +#define MC_WR_TC0__PRESCALE__SHIFT 0x1 +#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_TC0__STALL_MODE_MASK 0x30 +#define MC_WR_TC0__STALL_MODE__SHIFT 0x4 +#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_TC0__MAX_BURST_MASK 0x780 +#define MC_WR_TC0__MAX_BURST__SHIFT 0x7 +#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800 +#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb +#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_TC1__ENABLE_MASK 0x1 +#define MC_WR_TC1__ENABLE__SHIFT 0x0 +#define MC_WR_TC1__PRESCALE_MASK 0x6 +#define MC_WR_TC1__PRESCALE__SHIFT 0x1 +#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_TC1__STALL_MODE_MASK 0x30 +#define MC_WR_TC1__STALL_MODE__SHIFT 0x4 +#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_TC1__MAX_BURST_MASK 0x780 +#define MC_WR_TC1__MAX_BURST__SHIFT 0x7 +#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800 +#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb +#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6 +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000 +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18 +#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000 +#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19 +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000 +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18 +#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000 +#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19 +#define MC_RD_CB__ENABLE_MASK 0x1 +#define MC_RD_CB__ENABLE__SHIFT 0x0 +#define MC_RD_CB__PRESCALE_MASK 0x6 +#define MC_RD_CB__PRESCALE__SHIFT 0x1 +#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_CB__STALL_MODE_MASK 0x30 +#define MC_RD_CB__STALL_MODE__SHIFT 0x4 +#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_CB__MAX_BURST_MASK 0x780 +#define MC_RD_CB__MAX_BURST__SHIFT 0x7 +#define MC_RD_CB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_DB__ENABLE_MASK 0x1 +#define MC_RD_DB__ENABLE__SHIFT 0x0 +#define MC_RD_DB__PRESCALE_MASK 0x6 +#define MC_RD_DB__PRESCALE__SHIFT 0x1 +#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_DB__STALL_MODE_MASK 0x30 +#define MC_RD_DB__STALL_MODE__SHIFT 0x4 +#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_DB__MAX_BURST_MASK 0x780 +#define MC_RD_DB__MAX_BURST__SHIFT 0x7 +#define MC_RD_DB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_TC0__ENABLE_MASK 0x1 +#define MC_RD_TC0__ENABLE__SHIFT 0x0 +#define MC_RD_TC0__PRESCALE_MASK 0x6 +#define MC_RD_TC0__PRESCALE__SHIFT 0x1 +#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_TC0__STALL_MODE_MASK 0x30 +#define MC_RD_TC0__STALL_MODE__SHIFT 0x4 +#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_TC0__MAX_BURST_MASK 0x780 +#define MC_RD_TC0__MAX_BURST__SHIFT 0x7 +#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800 +#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb +#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_TC1__ENABLE_MASK 0x1 +#define MC_RD_TC1__ENABLE__SHIFT 0x0 +#define MC_RD_TC1__PRESCALE_MASK 0x6 +#define MC_RD_TC1__PRESCALE__SHIFT 0x1 +#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_TC1__STALL_MODE_MASK 0x30 +#define MC_RD_TC1__STALL_MODE__SHIFT 0x4 +#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_TC1__MAX_BURST_MASK 0x780 +#define MC_RD_TC1__MAX_BURST__SHIFT 0x7 +#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800 +#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb +#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_HUB__ENABLE_MASK 0x1 +#define MC_RD_HUB__ENABLE__SHIFT 0x0 +#define MC_RD_HUB__PRESCALE_MASK 0x6 +#define MC_RD_HUB__PRESCALE__SHIFT 0x1 +#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_HUB__STALL_MODE_MASK 0x30 +#define MC_RD_HUB__STALL_MODE__SHIFT 0x4 +#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_HUB__MAX_BURST_MASK 0x780 +#define MC_RD_HUB__MAX_BURST__SHIFT 0x7 +#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_CB__ENABLE_MASK 0x1 +#define MC_WR_CB__ENABLE__SHIFT 0x0 +#define MC_WR_CB__PRESCALE_MASK 0x6 +#define MC_WR_CB__PRESCALE__SHIFT 0x1 +#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_CB__STALL_MODE_MASK 0x30 +#define MC_WR_CB__STALL_MODE__SHIFT 0x4 +#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_CB__MAX_BURST_MASK 0x780 +#define MC_WR_CB__MAX_BURST__SHIFT 0x7 +#define MC_WR_CB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_DB__ENABLE_MASK 0x1 +#define MC_WR_DB__ENABLE__SHIFT 0x0 +#define MC_WR_DB__PRESCALE_MASK 0x6 +#define MC_WR_DB__PRESCALE__SHIFT 0x1 +#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_DB__STALL_MODE_MASK 0x30 +#define MC_WR_DB__STALL_MODE__SHIFT 0x4 +#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_DB__MAX_BURST_MASK 0x780 +#define MC_WR_DB__MAX_BURST__SHIFT 0x7 +#define MC_WR_DB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_HUB__ENABLE_MASK 0x1 +#define MC_WR_HUB__ENABLE__SHIFT 0x0 +#define MC_WR_HUB__PRESCALE_MASK 0x6 +#define MC_WR_HUB__PRESCALE__SHIFT 0x1 +#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_HUB__STALL_MODE_MASK 0x30 +#define MC_WR_HUB__STALL_MODE__SHIFT 0x4 +#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_HUB__MAX_BURST_MASK 0x780 +#define MC_WR_HUB__MAX_BURST__SHIFT 0x7 +#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff +#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00 +#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8 +#define MC_RD_GRP_LCL__CB0_MASK 0xf000 +#define MC_RD_GRP_LCL__CB0__SHIFT 0xc +#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000 +#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10 +#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000 +#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14 +#define MC_RD_GRP_LCL__DB0_MASK 0xf000000 +#define MC_RD_GRP_LCL__DB0__SHIFT 0x18 +#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000 +#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c +#define MC_WR_GRP_LCL__CB0_MASK 0xf +#define MC_WR_GRP_LCL__CB0__SHIFT 0x0 +#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0 +#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4 +#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00 +#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8 +#define MC_WR_GRP_LCL__DB0_MASK 0xf000 +#define MC_WR_GRP_LCL__DB0__SHIFT 0xc +#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000 +#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10 +#define MC_WR_GRP_LCL__SX0_MASK 0xf00000 +#define MC_WR_GRP_LCL__SX0__SHIFT 0x14 +#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000 +#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c +#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff +#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0 +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x40 +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x6 +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x80 +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x7 +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x100 +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x8 +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x200 +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x9 +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x400 +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0xa +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x800 +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0xb +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x1000 +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0xc +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x2000 +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0xd +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x4000 +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0xe +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x8000 +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xf +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x10000 +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x10 +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x20000 +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x11 +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x40000 +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x12 +#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4 +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2 +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18 +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3 +#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_DBG__SELECT0_MASK 0xf +#define MC_HUB_MISC_DBG__SELECT0__SHIFT 0x0 +#define MC_HUB_MISC_DBG__SELECT1_MASK 0xf0 +#define MC_HUB_MISC_DBG__SELECT1__SHIFT 0x4 +#define MC_HUB_MISC_DBG__CTRL0_MASK 0x1f00 +#define MC_HUB_MISC_DBG__CTRL0__SHIFT 0x8 +#define MC_HUB_MISC_DBG__CTRL1_MASK 0x3e000 +#define MC_HUB_MISC_DBG__CTRL1__SHIFT 0xd +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1 +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0 +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2 +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x4 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x2 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x8 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x3 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x10 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x4 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x20 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x5 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x40 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x6 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x80 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x7 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x100 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x8 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x200 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x9 +#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x400 +#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xa +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x800 +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0xb +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x1000 +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0xc +#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x2000 +#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0xd +#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3 +#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0 +#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff +#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3 +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 +#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0 +#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf +#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000 +#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10 +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000 +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11 +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000 +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12 +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000 +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13 +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000 +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14 +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1 +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0 +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2 +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1 +#define MC_HUB_WDP_BP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe +#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1 +#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000 +#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12 +#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1 +#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0 +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2 +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4 +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8 +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10 +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20 +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x5 +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40 +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x6 +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80 +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x7 +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100 +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x8 +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200 +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x9 +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400 +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xa +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1 +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0 +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2 +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4 +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8 +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10 +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x20 +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x5 +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x40 +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0x6 +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80 +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x7 +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x100 +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0x8 +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x200 +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0x9 +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400 +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xa +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x800 +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xb +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1 +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0 +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2 +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1 +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4 +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2 +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8 +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3 +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1 +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3 +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20 +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5 +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40 +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6 +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80 +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7 +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100 +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8 +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x200 +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0x9 +#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc00 +#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xa +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x20000 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x11 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x40000 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x12 +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x80000 +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x13 +#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x100000 +#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x14 +#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1 +#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0 +#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe +#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1 +#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000 +#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15 +#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000 +#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16 +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000 +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000 +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff +#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00 +#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8 +#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000 +#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10 +#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000 +#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18 +#define MC_HUB_WDP_MGPU2__CID2_MASK 0xff +#define MC_HUB_WDP_MGPU2__CID2__SHIFT 0x0 +#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf +#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0 +#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0 +#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8 +#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000 +#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10 +#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf +#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0 +#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0 +#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8 +#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000 +#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10 +#define MC_HUB_WDP_MGPU__STOR_MASK 0xff +#define MC_HUB_WDP_MGPU__STOR__SHIFT 0x0 +#define MC_HUB_WDP_MGPU__CID_MASK 0xff00 +#define MC_HUB_WDP_MGPU__CID__SHIFT 0x8 +#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME_MASK 0x7f0000 +#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME__SHIFT 0x10 +#define MC_HUB_WDP_MGPU__ENABLE_MASK 0x800000 +#define MC_HUB_WDP_MGPU__ENABLE__SHIFT 0x17 +#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME_MASK 0x7f000000 +#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME__SHIFT 0x18 +#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff +#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0 +#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00 +#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8 +#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000 +#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10 +#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000 +#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18 +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x0 +#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f +#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0 +#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x1f0000 +#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10 +#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000 +#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ_MASK 0x100000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ__SHIFT 0x14 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE_MASK 0x200000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE__SHIFT 0x15 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x400000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x16 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x800000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x17 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x1000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x18 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x2000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x19 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x4000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x1a +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x8000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x1b +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x10000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1c +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x20000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1d +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3 +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2 +#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3 +#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c +#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2 +#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_IA0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_IA0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_IA0__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_IA0__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_IA0__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_IA0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_IA0__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_IA0__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_IA0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_IA0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_IA1__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_IA1__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_IA1__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_IA1__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_IA1__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_IA1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_IA1__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_IA1__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_IA1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_IA1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f +#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0 +#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x80 +#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x7 +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00 +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8 +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0 +#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_CPG__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_CPG__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_CPG__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_CPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_CPG__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_CPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_CPG__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_CPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_CPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_CPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_IA__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_IA__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_IA__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_IA__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_IA__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_IA__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_IA__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_IA__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_IA__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_IA__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_IA__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3 +#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc +#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2 +#define MC_HUB_WDP_CPG__ENABLE_MASK 0x1 +#define MC_HUB_WDP_CPG__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_CPG__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_CPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_CPG__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_CPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_CPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_CPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_CPG__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_CPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_CPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_CPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VCE__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_IH__ENABLE_MASK 0x1 +#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1 +#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1 +#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1 +#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000 +#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_SAM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SAM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SAM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SAM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SAM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_SAM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SAM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SAM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SAM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SAM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_CPC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_CPC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_CPC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_CPC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_CPC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_CPC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_CPC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_CPC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_CPC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_CPC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_CPF__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_CPF__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_CPF__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_CPF__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_CPF__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_CPF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_CPF__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_CPF__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_CPF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_CPF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_CPC__ENABLE_MASK 0x1 +#define MC_HUB_WDP_CPC__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_CPC__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_CPC__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_CPC__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_CPC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_CPC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_CPC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_CPC__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_CPC__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_CPC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_CPC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_CPF__ENABLE_MASK 0x1 +#define MC_HUB_WDP_CPF__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_CPF__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_CPF__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_CPF__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_CPF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_CPF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_CPF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_CPF__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_CPF__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_CPF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_CPF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000 +#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000 +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10 +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000 +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11 +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0 +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00 +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8 +#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000 +#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14 +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00 +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1 +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0 +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6 +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1 +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78 +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3 +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80 +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100 +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8 +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600 +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9 +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800 +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb +#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000 +#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300 +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8 +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00 +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10 +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0 +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1 +#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e +#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000 +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 +#define MC_SHARED_CHMAP__CHAN0_MASK 0xf +#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0 +#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0 +#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4 +#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00 +#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8 +#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000 +#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc +#define MC_SHARED_CHREMAP__CHAN0_MASK 0x7 +#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0 +#define MC_SHARED_CHREMAP__CHAN1_MASK 0x38 +#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x3 +#define MC_SHARED_CHREMAP__CHAN2_MASK 0x1c0 +#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x6 +#define MC_SHARED_CHREMAP__CHAN3_MASK 0xe00 +#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0x9 +#define MC_SHARED_CHREMAP__CHAN4_MASK 0x7000 +#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0xc +#define MC_SHARED_CHREMAP__CHAN5_MASK 0x38000 +#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0xf +#define MC_SHARED_CHREMAP__CHAN6_MASK 0x1c0000 +#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x12 +#define MC_SHARED_CHREMAP__CHAN7_MASK 0xe00000 +#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x15 +#define MC_RD_GRP_GFX__CP_MASK 0xf +#define MC_RD_GRP_GFX__CP__SHIFT 0x0 +#define MC_RD_GRP_GFX__SH_MASK 0xf0 +#define MC_RD_GRP_GFX__SH__SHIFT 0x4 +#define MC_RD_GRP_GFX__IA_MASK 0xf00 +#define MC_RD_GRP_GFX__IA__SHIFT 0x8 +#define MC_RD_GRP_GFX__ACPG_MASK 0xf000 +#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc +#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000 +#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10 +#define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000 +#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14 +#define MC_WR_GRP_GFX__CP_MASK 0xf +#define MC_WR_GRP_GFX__CP__SHIFT 0x0 +#define MC_WR_GRP_GFX__SH_MASK 0xf0 +#define MC_WR_GRP_GFX__SH__SHIFT 0x4 +#define MC_WR_GRP_GFX__ACPG_MASK 0xf00 +#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8 +#define MC_WR_GRP_GFX__ACPO_MASK 0xf000 +#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc +#define MC_WR_GRP_GFX__XDMA_MASK 0xf0000 +#define MC_WR_GRP_GFX__XDMA__SHIFT 0x10 +#define MC_WR_GRP_GFX__XDMAM_MASK 0xf00000 +#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x14 +#define MC_RD_GRP_SYS__RLC_MASK 0xf +#define MC_RD_GRP_SYS__RLC__SHIFT 0x0 +#define MC_RD_GRP_SYS__VMC_MASK 0xf0 +#define MC_RD_GRP_SYS__VMC__SHIFT 0x4 +#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00 +#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8 +#define MC_RD_GRP_SYS__DMIF_MASK 0xf000 +#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc +#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000 +#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10 +#define MC_RD_GRP_SYS__SMU_MASK 0xf00000 +#define MC_RD_GRP_SYS__SMU__SHIFT 0x14 +#define MC_RD_GRP_SYS__VCE_MASK 0xf000000 +#define MC_RD_GRP_SYS__VCE__SHIFT 0x18 +#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000 +#define MC_RD_GRP_SYS__VCEU__SHIFT 0x1c +#define MC_WR_GRP_SYS__IH_MASK 0xf +#define MC_WR_GRP_SYS__IH__SHIFT 0x0 +#define MC_WR_GRP_SYS__MCIF_MASK 0xf0 +#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4 +#define MC_WR_GRP_SYS__RLC_MASK 0xf00 +#define MC_WR_GRP_SYS__RLC__SHIFT 0x8 +#define MC_WR_GRP_SYS__SAM_MASK 0xf000 +#define MC_WR_GRP_SYS__SAM__SHIFT 0xc +#define MC_WR_GRP_SYS__SMU_MASK 0xf0000 +#define MC_WR_GRP_SYS__SMU__SHIFT 0x10 +#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000 +#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14 +#define MC_WR_GRP_SYS__VCE_MASK 0xf000000 +#define MC_WR_GRP_SYS__VCE__SHIFT 0x18 +#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000 +#define MC_WR_GRP_SYS__VCEU__SHIFT 0x1c +#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf +#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0 +#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0 +#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4 +#define MC_RD_GRP_OTH__HDP_MASK 0xf00 +#define MC_RD_GRP_OTH__HDP__SHIFT 0x8 +#define MC_RD_GRP_OTH__SEM_MASK 0xf000 +#define MC_RD_GRP_OTH__SEM__SHIFT 0xc +#define MC_RD_GRP_OTH__UMC_MASK 0xf0000 +#define MC_RD_GRP_OTH__UMC__SHIFT 0x10 +#define MC_RD_GRP_OTH__UVD_MASK 0xf00000 +#define MC_RD_GRP_OTH__UVD__SHIFT 0x14 +#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000 +#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18 +#define MC_RD_GRP_OTH__SAM_MASK 0xf0000000 +#define MC_RD_GRP_OTH__SAM__SHIFT 0x1c +#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf +#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0 +#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0 +#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4 +#define MC_WR_GRP_OTH__HDP_MASK 0xf00 +#define MC_WR_GRP_OTH__HDP__SHIFT 0x8 +#define MC_WR_GRP_OTH__SEM_MASK 0xf000 +#define MC_WR_GRP_OTH__SEM__SHIFT 0xc +#define MC_WR_GRP_OTH__UMC_MASK 0xf0000 +#define MC_WR_GRP_OTH__UMC__SHIFT 0x10 +#define MC_WR_GRP_OTH__UVD_MASK 0xf00000 +#define MC_WR_GRP_OTH__UVD__SHIFT 0x14 +#define MC_WR_GRP_OTH__XDP_MASK 0xf000000 +#define MC_WR_GRP_OTH__XDP__SHIFT 0x18 +#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000 +#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c +#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff +#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0 +#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000 +#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10 +#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff +#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff +#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff +#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9 +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff +#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3 +#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 +#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 +#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 +#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 +#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 +#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 +#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 +#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 +#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 +#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 +#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 +#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 +#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 +#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000 +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 +#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000 +#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd +#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f +#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0 +#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0 +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff +#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00 +#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8 +#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000 +#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10 +#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000 +#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11 +#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000 +#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19 +#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff +#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0 +#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00 +#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa +#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000 +#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14 +#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000 +#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0 +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0 +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6 +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000 +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0 +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0 +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6 +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000 +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc +#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff +#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000 +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000 +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 +#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff +#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0 +#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000 +#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10 +#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000 +#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12 +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 +#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30 +#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40 +#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 +#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80 +#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100 +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200 +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400 +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa +#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800 +#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000 +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc +#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff +#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff +#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00 +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8 +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000 +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00 +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 +#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2 +#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f +#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0 +#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0 +#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6 +#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000 +#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc +#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000 +#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12 +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000 +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 +#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00 +#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 +#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000 +#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000 +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000 +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000 +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000 +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 +#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00 +#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000 +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000 +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 +#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000 +#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 +#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000 +#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000 +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1 +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000 +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000 +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 +#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000 +#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000 +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1 +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2 +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4 +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8 +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10 +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20 +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40 +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80 +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100 +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200 +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 +#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400 +#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa +#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800 +#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb +#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000 +#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc +#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000 +#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd +#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000 +#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe +#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000 +#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf +#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000 +#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 +#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000 +#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 +#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000 +#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 +#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000 +#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0 +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000 +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc +#define MC_XPB_STICKY__BITS_MASK 0xffffffff +#define MC_XPB_STICKY__BITS__SHIFT 0x0 +#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff +#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0 +#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff +#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 +#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00 +#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 +#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000 +#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 +#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000 +#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 +#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000 +#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f +#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff +#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00 +#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8 +#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000 +#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10 +#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000 +#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11 +#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000 +#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19 +#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1 +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0 +#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2 +#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4 +#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3 +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1 +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0 +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2 +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1 +#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000 +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3 +#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0 +#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc +#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2 +#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30 +#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4 +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1 +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0 +#define MC_XBAR_TWOCHAN__CH0_MASK 0x6 +#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1 +#define MC_XBAR_TWOCHAN__CH1_MASK 0x18 +#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3 +#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1 +#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0 +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2 +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1 +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4 +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c +#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0xfff +#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0 +#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000 +#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc +#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x3000000 +#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x18 +#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000 +#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a +#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 +#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c +#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff +#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 +#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xff00 +#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x8 +#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000 +#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10 +#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0xff +#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x0 +#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0xff00 +#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x8 +#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0xff0000 +#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x10 +#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000 +#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x18 +#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffff +#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x0 +#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffff +#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x0 +#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffff +#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x0 +#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffff +#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x0 +#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0xff +#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x0 +#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0xff00 +#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x8 +#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0xff0000 +#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x10 +#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000 +#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x18 +#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff +#define MC_XBAR_SPARE0__BIT__SHIFT 0x0 +#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff +#define MC_XBAR_SPARE1__BIT__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP_MASK 0x1 +#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP__SHIFT 0x0 +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3 +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3 +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 +#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1 +#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 +#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2 +#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 +#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4 +#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 +#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00 +#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 +#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000 +#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10 +#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1 +#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0 +#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2 +#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1 +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4 +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2 +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20 +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5 +#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40 +#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6 +#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80 +#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7 +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100 +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8 +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200 +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9 +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00 +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000 +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe +#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000 +#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000 +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10 +#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000 +#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11 +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0 +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100 +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8 +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000 +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10 +#define ATC_ATS_STATUS__BUSY_MASK 0x1 +#define ATC_ATS_STATUS__BUSY__SHIFT 0x0 +#define ATC_ATS_STATUS__CRASHED_MASK 0x2 +#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x3f +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0xfc00 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x3f00000 +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x3f +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00 +#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffff +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1 +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x3c +#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x2 +#define ATC_MISC_CG__OFFDLY_MASK 0xfc0 +#define ATC_MISC_CG__OFFDLY__SHIFT 0x6 +#define ATC_MISC_CG__ENABLE_MASK 0x40000 +#define ATC_MISC_CG__ENABLE__SHIFT 0x12 +#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000 +#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9 +#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f +#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00 +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000 +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf +#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f +#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0 +#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f +#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0 +#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0 +#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5 +#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100 +#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8 +#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200 +#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9 +#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x400 +#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0xa +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS_MASK 0x800 +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS__SHIFT 0xb +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS_MASK 0x1000 +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS__SHIFT 0xc +#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000 +#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe +#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000 +#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf +#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000 +#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11 +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3 +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0 +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4 +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2 +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10 +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4 +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0 +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 +#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 +#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e +#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 +#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 +#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 +#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e +#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 +#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f +#define ATC_L1RD_STATUS__BUSY_MASK 0x1 +#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0 +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2 +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 +#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100 +#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8 +#define ATC_L1WR_STATUS__BUSY_MASK 0x1 +#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0 +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2 +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 +#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100 +#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf +#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16 +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400 +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800 +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000 +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc +#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000 +#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10 +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000 +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11 +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000 +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13 +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000 +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15 +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000 +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16 +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000 +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17 +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000 +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18 +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000 +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19 +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000 +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a +#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000 +#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000 +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000 +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK 0x7 +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT 0x0 +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK 0x38 +#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT 0x3 +#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0 +#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6 +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800 +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb +#define GMCON_MISC2__STCTRL_LPT_TARGET_MASK 0x1ffe0000 +#define GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT 0x11 +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000 +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000 +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e +#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000 +#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff +#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0 +#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000 +#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc +#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000 +#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18 +#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000 +#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0 +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6 +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000 +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc +#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0xfc0000 +#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12 +#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0x3f000000 +#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x18 +#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff +#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0 +#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff +#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0 +#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff +#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 +#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200 +#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400 +#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800 +#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000 +#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000 +#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd +#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000 +#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 +#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff +#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0 +#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff +#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0 +#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000 +#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18 +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000 +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c +#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0x3f +#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0 +#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xfc0 +#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x6 +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff000 +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xc +#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x1000000 +#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x18 +#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x2000000 +#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x19 +#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x4000000 +#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1a +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3 +#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0x3f0 +#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4 +#define GMCON_DEBUG__GFX_STALL_MASK 0x1 +#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0 +#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2 +#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1 +#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffc +#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x2 +#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1 +#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800 +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000 +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000 +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000 +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000 +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000 +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1 +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000 +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000 +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f +#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000 +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VM_L2_STATUS__L2_BUSY_MASK 0x1 +#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2 +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1 +#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0 +#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2 +#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1 +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4 +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2 +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8 +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3 +#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10 +#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4 +#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20 +#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5 +#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40 +#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0xff000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0xff000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 +#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff +#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff +#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_DEBUG__FLAGS_MASK 0xffffffff +#define VM_DEBUG__FLAGS__SHIFT 0x0 +#define VM_L2_CG__OFFDLY_MASK 0xfc0 +#define VM_L2_CG__OFFDLY__SHIFT 0x6 +#define VM_L2_CG__ENABLE_MASK 0x40000 +#define VM_L2_CG__ENABLE__SHIFT 0x12 +#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000 +#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0 +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0xff +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0 +#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff +#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0 +#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00 +#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8 +#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000 +#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10 +#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000 +#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18 +#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff +#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0 +#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00 +#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8 +#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000 +#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10 +#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000 +#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff +#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0 +#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100 +#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8 +#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200 +#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9 +#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400 +#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa +#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800 +#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb +#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000 +#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc +#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000 +#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe +#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000 +#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16 +#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff +#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0 +#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100 +#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8 +#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200 +#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9 +#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400 +#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa +#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800 +#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb +#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000 +#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc +#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000 +#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe +#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000 +#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16 +#define MC_FUS_DRAM0_CS0_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM0_CS0_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM1_CS0_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM1_CS0_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM0_CS1_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM0_CS1_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM1_CS1_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM1_CS1_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM0_CS2_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM0_CS2_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM1_CS2_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM1_CS2_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM0_CS3_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM0_CS3_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM1_CS3_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM1_CS3_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9 +#define MC_FUS_DRAM0_CTL_BASE__DCTSEL_MASK 0x7 +#define MC_FUS_DRAM0_CTL_BASE__DCTSEL__SHIFT 0x0 +#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN_MASK 0x78 +#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN__SHIFT 0x3 +#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR_MASK 0xfffff80 +#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR__SHIFT 0x7 +#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN_MASK 0x10000000 +#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c +#define MC_FUS_DRAM1_CTL_BASE__DCTSEL_MASK 0x7 +#define MC_FUS_DRAM1_CTL_BASE__DCTSEL__SHIFT 0x0 +#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN_MASK 0x78 +#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN__SHIFT 0x3 +#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR_MASK 0xfffff80 +#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR__SHIFT 0x7 +#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN_MASK 0x10000000 +#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c +#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff +#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0 +#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000 +#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15 +#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff +#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0 +#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000 +#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15 +#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0_MASK 0xfff +#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0__SHIFT 0x0 +#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1_MASK 0xfff000 +#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1__SHIFT 0xc +#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2_MASK 0xfff +#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2__SHIFT 0x0 +#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3_MASK 0xfff000 +#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3__SHIFT 0xc +#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR_MASK 0x7 +#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR__SHIFT 0x0 +#define MC_FUS_DRAM_MODE__GDDR5EN_MASK 0x8 +#define MC_FUS_DRAM_MODE__GDDR5EN__SHIFT 0x3 +#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET_MASK 0x1ff0 +#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET__SHIFT 0x4 +#define MC_FUS_DRAM_APER_BASE__BASE_MASK 0xfffff +#define MC_FUS_DRAM_APER_BASE__BASE__SHIFT 0x0 +#define MC_FUS_DRAM_APER_TOP__TOP_MASK 0xfffff +#define MC_FUS_DRAM_APER_TOP__TOP__SHIFT 0x0 +#define MC_FUS_DRAM_C6SAVE_APER_BASE__BASE_MASK 0xfffff +#define MC_FUS_DRAM_C6SAVE_APER_BASE__BASE__SHIFT 0x0 +#define MC_FUS_DRAM_C6SAVE_APER_TOP__TOP_MASK 0xfffff +#define MC_FUS_DRAM_C6SAVE_APER_TOP__TOP__SHIFT 0x0 +#define MC_FUS_DRAM_APER_DEF__DEF_MASK 0xfffffff +#define MC_FUS_DRAM_APER_DEF__DEF__SHIFT 0x0 +#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS_MASK 0x10000000 +#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS__SHIFT 0x1c +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN_MASK 0x1 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN__SHIFT 0x0 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN_MASK 0x2 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN__SHIFT 0x1 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN_MASK 0x4 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN__SHIFT 0x2 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN_MASK 0x8 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN__SHIFT 0x3 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN_MASK 0x10 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN__SHIFT 0x4 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN_MASK 0x20 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN__SHIFT 0x5 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN_MASK 0x40 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN__SHIFT 0x6 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN_MASK 0x80 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN__SHIFT 0x7 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN_MASK 0x100 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN__SHIFT 0x8 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN_MASK 0x200 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN__SHIFT 0x9 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN_MASK 0x400 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN__SHIFT 0xa +#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN_MASK 0x800 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN__SHIFT 0xb +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN_MASK 0x1000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN__SHIFT 0xc +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN_MASK 0x2000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN__SHIFT 0xd +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN_MASK 0x4000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN__SHIFT 0xe +#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN_MASK 0x8000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN__SHIFT 0xf +#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL_MASK 0x30000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL__SHIFT 0x10 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN_MASK 0x40000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN__SHIFT 0x12 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN_MASK 0x80000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN__SHIFT 0x13 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN_MASK 0x100000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN__SHIFT 0x14 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL_MASK 0x200000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL__SHIFT 0x15 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL_MASK 0x400000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL__SHIFT 0x16 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL_MASK 0x800000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL__SHIFT 0x17 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS_MASK 0x1f000000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS__SHIFT 0x18 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE_MASK 0x20000000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT 0x1d +#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE_MASK 0xff +#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x0 +#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE_MASK 0x7f00 +#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x8 +#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE_MASK 0x8000 +#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE__SHIFT 0xf +#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE_MASK 0x10000 +#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE__SHIFT 0x10 +#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT_MASK 0x3fe0000 +#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT__SHIFT 0x11 +#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT_MASK 0xfc000000 +#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT__SHIFT 0x1a +#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI_MASK 0x3 +#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI__SHIFT 0x0 +#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI_MASK 0xc +#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI__SHIFT 0x2 +#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI_MASK 0x30 +#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI__SHIFT 0x4 +#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI_MASK 0xc0 +#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI__SHIFT 0x6 +#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI_MASK 0x300 +#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI__SHIFT 0x8 +#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI_MASK 0xc00 +#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI__SHIFT 0xa +#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI_MASK 0x3000 +#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI__SHIFT 0xc +#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI_MASK 0xc000 +#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI__SHIFT 0xe +#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI_MASK 0x30000 +#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI__SHIFT 0x10 +#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI_MASK 0xc0000 +#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI__SHIFT 0x12 +#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI_MASK 0x300000 +#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI__SHIFT 0x14 +#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI_MASK 0xc00000 +#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI__SHIFT 0x16 +#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI_MASK 0x3000000 +#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI__SHIFT 0x18 +#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI_MASK 0xc000000 +#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI__SHIFT 0x1a +#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI_MASK 0x30000000 +#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI__SHIFT 0x1c +#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI_MASK 0xc0000000 +#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI__SHIFT 0x1e +#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI_MASK 0x3 +#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI__SHIFT 0x0 +#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI_MASK 0xc +#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI__SHIFT 0x2 +#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI_MASK 0x30 +#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI__SHIFT 0x4 +#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff +#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0 +#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 +#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 +#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 +#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 +#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 +#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 +#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 +#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 +#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 +#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc +#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 +#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 +#define CHUB_ATC_L1_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 +#define CHUB_ATC_L1_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c +#define CHUB_ATC_L1_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 +#define CHUB_ATC_L1_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e +#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_CACHING_UNTRANSLATED_RETURNS_MASK 0x80000000 +#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_CACHING_UNTRANSLATED_RETURNS__SHIFT 0x1f +#define CHUB_ATC_L1_STATUS__BUSY_MASK 0x1 +#define CHUB_ATC_L1_STATUS__BUSY__SHIFT 0x0 +#define CHUB_ATC_L1_STATUS__DEADLOCK_DETECTION_MASK 0x2 +#define CHUB_ATC_L1_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 +#define CHUB_ATC_L1_STATUS__BAD_NEED_ATS_MASK 0x100 +#define CHUB_ATC_L1_STATUS__BAD_NEED_ATS__SHIFT 0x8 + +#endif /* GMC_7_0_SH_MASK_H */ -- cgit v1.2.3 From 973305270b6690feed82ae9ed0694e50a7eeae34 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:23:29 -0400 Subject: drm/amdgpu: add GMC 7.1 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h | 1464 ++ .../drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h | 14416 +++++++++++++++++++ 2 files changed, 15880 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h new file mode 100644 index 000000000000..9da033dc1a34 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h @@ -0,0 +1,1464 @@ +/* + * GMC_7_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_7_1_D_H +#define GMC_7_1_D_H + +#define mmMC_CONFIG 0x800 +#define mmMC_ARB_AGE_CNTL 0x9bf +#define mmMC_ARB_RET_CREDITS2 0x9c0 +#define mmMC_ARB_FED_CNTL 0x9c1 +#define mmMC_ARB_GECC2_STATUS 0x9c2 +#define mmMC_ARB_GECC2_MISC 0x9c3 +#define mmMC_ARB_GECC2_DEBUG 0x9c4 +#define mmMC_ARB_GECC2_DEBUG2 0x9c5 +#define mmMC_ARB_PERF_CID 0x9c6 +#define mmMC_ARB_GECC2 0x9c9 +#define mmMC_ARB_GECC2_CLI 0x9ca +#define mmMC_ARB_ADDR_SWIZ0 0x9cb +#define mmMC_ARB_ADDR_SWIZ1 0x9cc +#define mmMC_ARB_MISC3 0x9cd +#define mmMC_ARB_WCDR_2 0x9ce +#define mmMC_ARB_RTT_DATA 0x9cf +#define mmMC_ARB_RTT_CNTL0 0x9d0 +#define mmMC_ARB_RTT_CNTL1 0x9d1 +#define mmMC_ARB_RTT_CNTL2 0x9d2 +#define mmMC_ARB_RTT_DEBUG 0x9d3 +#define mmMC_ARB_CAC_CNTL 0x9d4 +#define mmMC_ARB_MISC2 0x9d5 +#define mmMC_ARB_MISC 0x9d6 +#define mmMC_ARB_BANKMAP 0x9d7 +#define mmMC_ARB_RAMCFG 0x9d8 +#define mmMC_ARB_POP 0x9d9 +#define mmMC_ARB_MINCLKS 0x9da +#define mmMC_ARB_SQM_CNTL 0x9db +#define mmMC_ARB_ADDR_HASH 0x9dc +#define mmMC_ARB_DRAM_TIMING 0x9dd +#define mmMC_ARB_DRAM_TIMING2 0x9de +#define mmMC_ARB_WTM_CNTL_RD 0x9df +#define mmMC_ARB_WTM_CNTL_WR 0x9e0 +#define mmMC_ARB_WTM_GRPWT_RD 0x9e1 +#define mmMC_ARB_WTM_GRPWT_WR 0x9e2 +#define mmMC_ARB_TM_CNTL_RD 0x9e3 +#define mmMC_ARB_TM_CNTL_WR 0x9e4 +#define mmMC_ARB_LAZY0_RD 0x9e5 +#define mmMC_ARB_LAZY0_WR 0x9e6 +#define mmMC_ARB_LAZY1_RD 0x9e7 +#define mmMC_ARB_LAZY1_WR 0x9e8 +#define mmMC_ARB_AGE_RD 0x9e9 +#define mmMC_ARB_AGE_WR 0x9ea +#define mmMC_ARB_RFSH_CNTL 0x9eb +#define mmMC_ARB_RFSH_RATE 0x9ec +#define mmMC_ARB_PM_CNTL 0x9ed +#define mmMC_ARB_GDEC_RD_CNTL 0x9ee +#define mmMC_ARB_GDEC_WR_CNTL 0x9ef +#define mmMC_ARB_LM_RD 0x9f0 +#define mmMC_ARB_LM_WR 0x9f1 +#define mmMC_ARB_REMREQ 0x9f2 +#define mmMC_ARB_REPLAY 0x9f3 +#define mmMC_ARB_RET_CREDITS_RD 0x9f4 +#define mmMC_ARB_RET_CREDITS_WR 0x9f5 +#define mmMC_ARB_MAX_LAT_CID 0x9f6 +#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7 +#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8 +#define mmMC_ARB_SSM 0x9f9 +#define mmMC_ARB_CG 0x9fa +#define mmMC_ARB_WCDR 0x9fb +#define mmMC_ARB_DRAM_TIMING_1 0x9fc +#define mmMC_ARB_BUSY_STATUS 0x9fd +#define mmMC_ARB_DRAM_TIMING2_1 0x9ff +#define mmMC_ARB_BURST_TIME 0xa02 +#define mmMC_CITF_XTRA_ENABLE 0x96d +#define mmCC_MC_MAX_CHANNEL 0x96e +#define mmMC_CG_CONFIG 0x96f +#define mmMC_CITF_CNTL 0x970 +#define mmMC_CITF_CREDITS_VM 0x971 +#define mmMC_CITF_CREDITS_ARB_RD 0x972 +#define mmMC_CITF_CREDITS_ARB_WR 0x973 +#define mmMC_CITF_DAGB_CNTL 0x974 +#define mmMC_CITF_INT_CREDITS 0x975 +#define mmMC_CITF_RET_MODE 0x976 +#define mmMC_CITF_DAGB_DLY 0x977 +#define mmMC_RD_GRP_EXT 0x978 +#define mmMC_WR_GRP_EXT 0x979 +#define mmMC_CITF_REMREQ 0x97a +#define mmMC_WR_TC0 0x97b +#define mmMC_WR_TC1 0x97c +#define mmMC_CITF_INT_CREDITS_WR 0x97d +#define mmMC_CITF_WTM_RD_CNTL 0x97f +#define mmMC_CITF_WTM_WR_CNTL 0x980 +#define mmMC_RD_CB 0x981 +#define mmMC_RD_DB 0x982 +#define mmMC_RD_TC0 0x983 +#define mmMC_RD_TC1 0x984 +#define mmMC_RD_HUB 0x985 +#define mmMC_WR_CB 0x986 +#define mmMC_WR_DB 0x987 +#define mmMC_WR_HUB 0x988 +#define mmMC_CITF_CREDITS_XBAR 0x989 +#define mmMC_RD_GRP_LCL 0x98a +#define mmMC_WR_GRP_LCL 0x98b +#define mmMC_CITF_PERF_MON_CNTL2 0x98e +#define mmMC_CITF_PERF_MON_RSLT2 0x991 +#define mmMC_CITF_MISC_RD_CG 0x992 +#define mmMC_CITF_MISC_WR_CG 0x993 +#define mmMC_CITF_MISC_VM_CG 0x994 +#define mmMC_HUB_MISC_POWER 0x82d +#define mmMC_HUB_MISC_HUB_CG 0x82e +#define mmMC_HUB_MISC_VM_CG 0x82f +#define mmMC_HUB_MISC_SIP_CG 0x830 +#define mmMC_HUB_MISC_STATUS 0x832 +#define mmMC_HUB_MISC_OVERRIDE 0x833 +#define mmMC_HUB_MISC_FRAMING 0x834 +#define mmMC_HUB_WDP_CNTL 0x835 +#define mmMC_HUB_WDP_ERR 0x836 +#define mmMC_HUB_WDP_BP 0x837 +#define mmMC_HUB_WDP_STATUS 0x838 +#define mmMC_HUB_RDREQ_STATUS 0x839 +#define mmMC_HUB_WRRET_STATUS 0x83a +#define mmMC_HUB_RDREQ_CNTL 0x83b +#define mmMC_HUB_WRRET_CNTL 0x83c +#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d +#define mmMC_HUB_WDP_WTM_CNTL 0x83e +#define mmMC_HUB_WDP_CREDITS 0x83f +#define mmMC_HUB_WDP_CREDITS2 0x840 +#define mmMC_HUB_WDP_GBL0 0x841 +#define mmMC_HUB_WDP_GBL1 0x842 +#define mmMC_HUB_RDREQ_CREDITS 0x844 +#define mmMC_HUB_RDREQ_CREDITS2 0x845 +#define mmMC_HUB_SHARED_DAGB_DLY 0x846 +#define mmMC_HUB_MISC_IDLE_STATUS 0x847 +#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848 +#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849 +#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a +#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b +#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c +#define mmMC_HUB_WDP_SH2 0x84d +#define mmMC_HUB_WDP_SH3 0x84e +#define mmMC_HUB_RDREQ_IA0 0x84f +#define mmMC_HUB_RDREQ_IA1 0x850 +#define mmMC_HUB_RDREQ_MCDW 0x851 +#define mmMC_HUB_RDREQ_MCDX 0x852 +#define mmMC_HUB_RDREQ_MCDY 0x853 +#define mmMC_HUB_RDREQ_MCDZ 0x854 +#define mmMC_HUB_RDREQ_SIP 0x855 +#define mmMC_HUB_RDREQ_GBL0 0x856 +#define mmMC_HUB_RDREQ_GBL1 0x857 +#define mmMC_HUB_RDREQ_SMU 0x858 +#define mmMC_HUB_RDREQ_CPG 0x859 +#define mmMC_HUB_RDREQ_SDMA0 0x85a +#define mmMC_HUB_RDREQ_HDP 0x85b +#define mmMC_HUB_RDREQ_SDMA1 0x85c +#define mmMC_HUB_RDREQ_RLC 0x85d +#define mmMC_HUB_RDREQ_SEM 0x85e +#define mmMC_HUB_RDREQ_VCE 0x85f +#define mmMC_HUB_RDREQ_UMC 0x860 +#define mmMC_HUB_RDREQ_UVD 0x861 +#define mmMC_HUB_RDREQ_IA 0x862 +#define mmMC_HUB_RDREQ_DMIF 0x863 +#define mmMC_HUB_RDREQ_MCIF 0x864 +#define mmMC_HUB_RDREQ_VMC 0x865 +#define mmMC_HUB_RDREQ_VCEU 0x866 +#define mmMC_HUB_WDP_MCDW 0x867 +#define mmMC_HUB_WDP_MCDX 0x868 +#define mmMC_HUB_WDP_MCDY 0x869 +#define mmMC_HUB_WDP_MCDZ 0x86a +#define mmMC_HUB_WDP_SIP 0x86b +#define mmMC_HUB_WDP_CPG 0x86c +#define mmMC_HUB_WDP_SDMA1 0x86d +#define mmMC_HUB_WDP_SH0 0x86e +#define mmMC_HUB_WDP_MCIF 0x86f +#define mmMC_HUB_WDP_VCE 0x870 +#define mmMC_HUB_WDP_XDP 0x871 +#define mmMC_HUB_WDP_IH 0x872 +#define mmMC_HUB_WDP_RLC 0x873 +#define mmMC_HUB_WDP_SEM 0x874 +#define mmMC_HUB_WDP_SMU 0x875 +#define mmMC_HUB_WDP_SH1 0x876 +#define mmMC_HUB_WDP_UMC 0x877 +#define mmMC_HUB_WDP_UVD 0x878 +#define mmMC_HUB_WDP_HDP 0x879 +#define mmMC_HUB_WDP_SDMA0 0x87a +#define mmMC_HUB_WRRET_MCDW 0x87b +#define mmMC_HUB_WRRET_MCDX 0x87c +#define mmMC_HUB_WRRET_MCDY 0x87d +#define mmMC_HUB_WRRET_MCDZ 0x87e +#define mmMC_HUB_WDP_VCEU 0x87f +#define mmMC_HUB_WDP_XDMAM 0x880 +#define mmMC_HUB_WDP_XDMA 0x881 +#define mmMC_HUB_RDREQ_XDMAM 0x882 +#define mmMC_HUB_RDREQ_ACPG 0x883 +#define mmMC_HUB_RDREQ_ACPO 0x884 +#define mmMC_HUB_RDREQ_SAM 0x885 +#define mmMC_HUB_WDP_ACPG 0x886 +#define mmMC_HUB_WDP_ACPO 0x887 +#define mmMC_HUB_WDP_SAM 0x888 +#define mmMC_HUB_RDREQ_CPC 0x889 +#define mmMC_HUB_RDREQ_CPF 0x88a +#define mmMC_HUB_WDP_CPC 0x88b +#define mmMC_HUB_WDP_CPF 0x88c +#define mmMC_HUB_RDREQ_ISP_SPM 0xde0 +#define mmMC_HUB_RDREQ_ISP_MPM 0xde1 +#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2 +#define mmMC_HUB_WDP_ISP_SPM 0xde3 +#define mmMC_HUB_WDP_ISP_MPS 0xde4 +#define mmMC_HUB_WDP_ISP_MPM 0xde5 +#define mmMC_HUB_WDP_ISP_CCPU 0xde6 +#define mmMC_HUB_RDREQ_MCDS 0xde7 +#define mmMC_HUB_RDREQ_MCDT 0xde8 +#define mmMC_HUB_RDREQ_MCDU 0xde9 +#define mmMC_HUB_RDREQ_MCDV 0xdea +#define mmMC_HUB_WDP_MCDS 0xdeb +#define mmMC_HUB_WDP_MCDT 0xdec +#define mmMC_HUB_WDP_MCDU 0xded +#define mmMC_HUB_WDP_MCDV 0xdee +#define mmMC_HUB_WRRET_MCDS 0xdef +#define mmMC_HUB_WRRET_MCDT 0xdf0 +#define mmMC_HUB_WRRET_MCDU 0xdf1 +#define mmMC_HUB_WRRET_MCDV 0xdf2 +#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3 +#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4 +#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5 +#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6 +#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7 +#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8 +#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9 +#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa +#define mmMC_HUB_WDP_BP2 0xdfb +#define mmMC_RPB_CONF 0x94d +#define mmMC_RPB_IF_CONF 0x94e +#define mmMC_RPB_DBG1 0x94f +#define mmMC_RPB_EFF_CNTL 0x950 +#define mmMC_RPB_ARB_CNTL 0x951 +#define mmMC_RPB_BIF_CNTL 0x952 +#define mmMC_RPB_WR_SWITCH_CNTL 0x953 +#define mmMC_RPB_WR_COMBINE_CNTL 0x954 +#define mmMC_RPB_RD_SWITCH_CNTL 0x955 +#define mmMC_RPB_CID_QUEUE_WR 0x956 +#define mmMC_RPB_CID_QUEUE_RD 0x957 +#define mmMC_RPB_PERF_COUNTER_CNTL 0x958 +#define mmMC_RPB_PERF_COUNTER_STATUS 0x959 +#define mmMC_RPB_CID_QUEUE_EX 0x95a +#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b +#define mmMC_RPB_TCI_CNTL 0x95c +#define mmMC_SHARED_CHMAP 0x801 +#define mmMC_SHARED_CHREMAP 0x802 +#define mmMC_RD_GRP_GFX 0x803 +#define mmMC_WR_GRP_GFX 0x804 +#define mmMC_RD_GRP_SYS 0x805 +#define mmMC_WR_GRP_SYS 0x806 +#define mmMC_RD_GRP_OTH 0x807 +#define mmMC_WR_GRP_OTH 0x808 +#define mmMC_VM_FB_LOCATION 0x809 +#define mmMC_VM_AGP_TOP 0x80a +#define mmMC_VM_AGP_BOT 0x80b +#define mmMC_VM_AGP_BASE 0x80c +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f +#define mmMC_VM_DC_WRITE_CNTL 0x810 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818 +#define mmMC_VM_MX_L1_TLB_CNTL 0x819 +#define mmMC_VM_FB_OFFSET 0x81a +#define mmMC_VM_STEERING 0x81b +#define mmMC_SHARED_CHREMAP2 0x81c +#define mmMC_CONFIG_MCD 0x828 +#define mmMC_CG_CONFIG_MCD 0x829 +#define mmMC_MEM_POWER_LS 0x82a +#define mmMC_SHARED_BLACKOUT_CNTL 0x82b +#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891 +#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893 +#define mmMC_VM_MB_L1_TLB0_STATUS 0x895 +#define mmMC_VM_MB_L1_TLB1_STATUS 0x896 +#define mmMC_VM_MB_L1_TLB2_STATUS 0x897 +#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1 +#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5 +#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6 +#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998 +#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999 +#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a +#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b +#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c +#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d +#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4 +#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7 +#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8 +#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd +#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce +#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf +#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0 +#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1 +#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2 +#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3 +#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4 +#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5 +#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da +#define mmMC_XPB_RTR_DEST_MAP0 0x8db +#define mmMC_XPB_RTR_DEST_MAP1 0x8dc +#define mmMC_XPB_RTR_DEST_MAP2 0x8dd +#define mmMC_XPB_RTR_DEST_MAP3 0x8de +#define mmMC_XPB_RTR_DEST_MAP4 0x8df +#define mmMC_XPB_RTR_DEST_MAP5 0x8e0 +#define mmMC_XPB_RTR_DEST_MAP6 0x8e1 +#define mmMC_XPB_RTR_DEST_MAP7 0x8e2 +#define mmMC_XPB_RTR_DEST_MAP8 0x8e3 +#define mmMC_XPB_RTR_DEST_MAP9 0x8e4 +#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5 +#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6 +#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7 +#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8 +#define mmMC_XPB_CLG_CFG0 0x8e9 +#define mmMC_XPB_CLG_CFG1 0x8ea +#define mmMC_XPB_CLG_CFG2 0x8eb +#define mmMC_XPB_CLG_CFG3 0x8ec +#define mmMC_XPB_CLG_CFG4 0x8ed +#define mmMC_XPB_CLG_CFG5 0x8ee +#define mmMC_XPB_CLG_CFG6 0x8ef +#define mmMC_XPB_CLG_CFG7 0x8f0 +#define mmMC_XPB_CLG_CFG8 0x8f1 +#define mmMC_XPB_CLG_CFG9 0x8f2 +#define mmMC_XPB_CLG_CFG10 0x8f3 +#define mmMC_XPB_CLG_CFG11 0x8f4 +#define mmMC_XPB_CLG_CFG12 0x8f5 +#define mmMC_XPB_CLG_CFG13 0x8f6 +#define mmMC_XPB_CLG_CFG14 0x8f7 +#define mmMC_XPB_CLG_CFG15 0x8f8 +#define mmMC_XPB_CLG_CFG16 0x8f9 +#define mmMC_XPB_CLG_CFG17 0x8fa +#define mmMC_XPB_CLG_CFG18 0x8fb +#define mmMC_XPB_CLG_CFG19 0x8fc +#define mmMC_XPB_CLG_EXTRA 0x8fd +#define mmMC_XPB_LB_ADDR 0x8fe +#define mmMC_XPB_UNC_THRESH_HST 0x8ff +#define mmMC_XPB_UNC_THRESH_SID 0x900 +#define mmMC_XPB_WCB_STS 0x901 +#define mmMC_XPB_WCB_CFG 0x902 +#define mmMC_XPB_P2P_BAR_CFG 0x903 +#define mmMC_XPB_P2P_BAR0 0x904 +#define mmMC_XPB_P2P_BAR1 0x905 +#define mmMC_XPB_P2P_BAR2 0x906 +#define mmMC_XPB_P2P_BAR3 0x907 +#define mmMC_XPB_P2P_BAR4 0x908 +#define mmMC_XPB_P2P_BAR5 0x909 +#define mmMC_XPB_P2P_BAR6 0x90a +#define mmMC_XPB_P2P_BAR7 0x90b +#define mmMC_XPB_P2P_BAR_SETUP 0x90c +#define mmMC_XPB_P2P_BAR_DEBUG 0x90d +#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e +#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f +#define mmMC_XPB_PEER_SYS_BAR0 0x910 +#define mmMC_XPB_PEER_SYS_BAR1 0x911 +#define mmMC_XPB_PEER_SYS_BAR2 0x912 +#define mmMC_XPB_PEER_SYS_BAR3 0x913 +#define mmMC_XPB_PEER_SYS_BAR4 0x914 +#define mmMC_XPB_PEER_SYS_BAR5 0x915 +#define mmMC_XPB_PEER_SYS_BAR6 0x916 +#define mmMC_XPB_PEER_SYS_BAR7 0x917 +#define mmMC_XPB_PEER_SYS_BAR8 0x918 +#define mmMC_XPB_PEER_SYS_BAR9 0x919 +#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a +#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b +#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c +#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d +#define mmMC_XPB_CLK_GAT 0x91e +#define mmMC_XPB_INTF_CFG 0x91f +#define mmMC_XPB_INTF_STS 0x920 +#define mmMC_XPB_PIPE_STS 0x921 +#define mmMC_XPB_SUB_CTRL 0x922 +#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923 +#define mmMC_XPB_PERF_KNOBS 0x924 +#define mmMC_XPB_STICKY 0x925 +#define mmMC_XPB_STICKY_W1C 0x926 +#define mmMC_XPB_MISC_CFG 0x927 +#define mmMC_XPB_CLG_CFG20 0x928 +#define mmMC_XPB_CLG_CFG21 0x929 +#define mmMC_XPB_CLG_CFG22 0x92a +#define mmMC_XPB_CLG_CFG23 0x92b +#define mmMC_XPB_CLG_CFG24 0x92c +#define mmMC_XPB_CLG_CFG25 0x92d +#define mmMC_XPB_CLG_CFG26 0x92e +#define mmMC_XPB_CLG_CFG27 0x92f +#define mmMC_XPB_CLG_CFG28 0x930 +#define mmMC_XPB_CLG_CFG29 0x931 +#define mmMC_XPB_CLG_CFG30 0x932 +#define mmMC_XPB_CLG_CFG31 0x933 +#define mmMC_XPB_INTF_CFG2 0x934 +#define mmMC_XPB_CLG_EXTRA_RD 0x935 +#define mmMC_XPB_CLG_CFG32 0x936 +#define mmMC_XPB_CLG_CFG33 0x937 +#define mmMC_XPB_CLG_CFG34 0x938 +#define mmMC_XPB_CLG_CFG35 0x939 +#define mmMC_XPB_CLG_CFG36 0x93a +#define mmMC_XBAR_ADDR_DEC 0xc80 +#define mmMC_XBAR_REMOTE 0xc81 +#define mmMC_XBAR_WRREQ_CREDIT 0xc82 +#define mmMC_XBAR_RDREQ_CREDIT 0xc83 +#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84 +#define mmMC_XBAR_WRRET_CREDIT1 0xc85 +#define mmMC_XBAR_WRRET_CREDIT2 0xc86 +#define mmMC_XBAR_RDRET_CREDIT1 0xc87 +#define mmMC_XBAR_RDRET_CREDIT2 0xc88 +#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89 +#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a +#define mmMC_XBAR_CHTRIREMAP 0xc8b +#define mmMC_XBAR_TWOCHAN 0xc8c +#define mmMC_XBAR_ARB 0xc8d +#define mmMC_XBAR_ARB_MAX_BURST 0xc8e +#define mmMC_XBAR_PERF_MON_CNTL0 0xc8f +#define mmMC_XBAR_PERF_MON_CNTL1 0xc90 +#define mmMC_XBAR_PERF_MON_CNTL2 0xc91 +#define mmMC_XBAR_PERF_MON_RSLT0 0xc92 +#define mmMC_XBAR_PERF_MON_RSLT1 0xc93 +#define mmMC_XBAR_PERF_MON_RSLT2 0xc94 +#define mmMC_XBAR_PERF_MON_RSLT3 0xc95 +#define mmMC_XBAR_PERF_MON_MAX_THSH 0xc96 +#define mmMC_XBAR_SPARE0 0xc97 +#define mmMC_XBAR_SPARE1 0xc98 +#define mmMC_CITF_PERFCOUNTER_LO 0x7a0 +#define mmMC_HUB_PERFCOUNTER_LO 0x7a1 +#define mmMC_RPB_PERFCOUNTER_LO 0x7a2 +#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3 +#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4 +#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5 +#define mmMC_ARB_PERFCOUNTER_LO 0x7a6 +#define mmATC_PERFCOUNTER_LO 0x7a7 +#define mmMC_CITF_PERFCOUNTER_HI 0x7a8 +#define mmMC_HUB_PERFCOUNTER_HI 0x7a9 +#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa +#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab +#define mmMC_RPB_PERFCOUNTER_HI 0x7ac +#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad +#define mmMC_ARB_PERFCOUNTER_HI 0x7ae +#define mmATC_PERFCOUNTER_HI 0x7af +#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0 +#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1 +#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2 +#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3 +#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4 +#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5 +#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6 +#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7 +#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8 +#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9 +#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba +#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb +#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc +#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd +#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be +#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf +#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0 +#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1 +#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2 +#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3 +#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4 +#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5 +#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6 +#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7 +#define mmATC_PERFCOUNTER0_CFG 0x7c8 +#define mmATC_PERFCOUNTER1_CFG 0x7c9 +#define mmATC_PERFCOUNTER2_CFG 0x7ca +#define mmATC_PERFCOUNTER3_CFG 0x7cb +#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc +#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd +#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce +#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf +#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0 +#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1 +#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2 +#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3 +#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4 +#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5 +#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6 +#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7 +#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8 +#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9 +#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da +#define mmMC_ARB_PERF_MON_CNTL0_ECC 0x7db +#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0 +#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1 +#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2 +#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3 +#define mmATC_VM_APERTURE0_CNTL 0xcc4 +#define mmATC_VM_APERTURE1_CNTL 0xcc5 +#define mmATC_VM_APERTURE0_CNTL2 0xcc6 +#define mmATC_VM_APERTURE1_CNTL2 0xcc7 +#define mmATC_ATS_CNTL 0xcc9 +#define mmATC_ATS_DEBUG 0xcca +#define mmATC_ATS_FAULT_DEBUG 0xccb +#define mmATC_ATS_STATUS 0xccc +#define mmATC_ATS_FAULT_CNTL 0xccd +#define mmATC_ATS_FAULT_STATUS_INFO 0xcce +#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf +#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0 +#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1 +#define mmATC_MISC_CG 0xcd4 +#define mmATC_L2_CNTL 0xcd5 +#define mmATC_L2_CNTL2 0xcd6 +#define mmATC_L2_DEBUG 0xcd7 +#define mmATC_L2_DEBUG2 0xcd8 +#define mmATC_L1_CNTL 0xcdc +#define mmATC_L1_ADDRESS_OFFSET 0xcdd +#define mmATC_L1RD_DEBUG_TLB 0xcde +#define mmATC_L1WR_DEBUG_TLB 0xcdf +#define mmATC_L1RD_STATUS 0xce0 +#define mmATC_L1WR_STATUS 0xce1 +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6 +#define mmATC_VMID0_PASID_MAPPING 0xce7 +#define mmATC_VMID1_PASID_MAPPING 0xce8 +#define mmATC_VMID2_PASID_MAPPING 0xce9 +#define mmATC_VMID3_PASID_MAPPING 0xcea +#define mmATC_VMID4_PASID_MAPPING 0xceb +#define mmATC_VMID5_PASID_MAPPING 0xcec +#define mmATC_VMID6_PASID_MAPPING 0xced +#define mmATC_VMID7_PASID_MAPPING 0xcee +#define mmATC_VMID8_PASID_MAPPING 0xcef +#define mmATC_VMID9_PASID_MAPPING 0xcf0 +#define mmATC_VMID10_PASID_MAPPING 0xcf1 +#define mmATC_VMID11_PASID_MAPPING 0xcf2 +#define mmATC_VMID12_PASID_MAPPING 0xcf3 +#define mmATC_VMID13_PASID_MAPPING 0xcf4 +#define mmATC_VMID14_PASID_MAPPING 0xcf5 +#define mmATC_VMID15_PASID_MAPPING 0xcf6 +#define mmGMCON_RENG_RAM_INDEX 0xd40 +#define mmGMCON_RENG_RAM_DATA 0xd41 +#define mmGMCON_RENG_EXECUTE 0xd42 +#define mmGMCON_MISC 0xd43 +#define mmGMCON_MISC2 0xd44 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49 +#define mmGMCON_PERF_MON_CNTL0 0xd4a +#define mmGMCON_PERF_MON_CNTL1 0xd4b +#define mmGMCON_PERF_MON_RSLT0 0xd4c +#define mmGMCON_PERF_MON_RSLT1 0xd4d +#define mmGMCON_PGFSM_CONFIG 0xd4e +#define mmGMCON_PGFSM_WRITE 0xd4f +#define mmGMCON_PGFSM_READ 0xd50 +#define mmGMCON_MISC3 0xd51 +#define mmGMCON_MASK 0xd52 +#define mmGMCON_LPT_TARGET 0xd53 +#define mmGMCON_DEBUG 0xd5f +#define mmVM_L2_CNTL 0x500 +#define mmVM_L2_CNTL2 0x501 +#define mmVM_L2_CNTL3 0x502 +#define mmVM_L2_STATUS 0x503 +#define mmVM_CONTEXT0_CNTL 0x504 +#define mmVM_CONTEXT1_CNTL 0x505 +#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506 +#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507 +#define mmVM_CONTEXT0_CNTL2 0x50c +#define mmVM_CONTEXT1_CNTL2 0x50d +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 +#define mmVM_INVALIDATE_REQUEST 0x51e +#define mmVM_INVALIDATE_RESPONSE 0x51f +#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c +#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d +#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e +#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f +#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530 +#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531 +#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532 +#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533 +#define mmVM_PRT_CNTL 0x534 +#define mmVM_CONTEXTS_DISABLE 0x535 +#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536 +#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 +#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538 +#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539 +#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e +#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f +#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 +#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 +#define mmVM_FAULT_CLIENT_ID 0x54e +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 +#define mmVM_DEBUG 0x56f +#define mmVM_L2_CG 0x570 +#define mmVM_L2_BANK_SELECT_MASKA 0x572 +#define mmVM_L2_BANK_SELECT_MASKB 0x573 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577 +#define mmMC_SEQ_CNTL 0xa25 +#define mmMC_SEQ_CNTL_2 0xad4 +#define mmMC_SEQ_DRAM 0xa26 +#define mmMC_SEQ_DRAM_2 0xa27 +#define mmMC_SEQ_RAS_TIMING 0xa28 +#define mmMC_SEQ_CAS_TIMING 0xa29 +#define mmMC_SEQ_MISC_TIMING 0xa2a +#define mmMC_SEQ_MISC_TIMING2 0xa2b +#define mmMC_SEQ_PMG_TIMING 0xa2c +#define mmMC_SEQ_RD_CTL_D0 0xa2d +#define mmMC_SEQ_RD_CTL_D1 0xa2e +#define mmMC_SEQ_WR_CTL_D0 0xa2f +#define mmMC_SEQ_WR_CTL_D1 0xa30 +#define mmMC_SEQ_WR_CTL_2 0xad5 +#define mmMC_SEQ_CMD 0xa31 +#define mmMC_PMG_CMD_EMRS 0xa83 +#define mmMC_PMG_CMD_MRS 0xaab +#define mmMC_PMG_CMD_MRS1 0xad1 +#define mmMC_PMG_CMD_MRS2 0xad7 +#define mmMC_PMG_CFG 0xa84 +#define mmMC_PMG_AUTO_CMD 0xa34 +#define mmMC_PMG_AUTO_CFG 0xa35 +#define mmMC_IMP_CNTL 0xa36 +#define mmMC_IMP_DEBUG 0xa37 +#define mmMC_IMP_STATUS 0xa38 +#define mmMC_IMP_DQ_STATUS 0xabc +#define mmMC_SEQ_WCDR_CTRL 0xa39 +#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0xa3a +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0xa3b +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0xafe +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0xaff +#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0xa3c +#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0xa3d +#define mmMC_SEQ_TRAIN_CAPTURE 0xa3e +#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0xa3f +#define mmMC_SEQ_TRAIN_TIMING 0xa40 +#define mmMC_TRAIN_EDCCDR_R_D0 0xa41 +#define mmMC_TRAIN_EDCCDR_R_D1 0xa42 +#define mmMC_TRAIN_PRBSERR_0_D0 0xa43 +#define mmMC_TRAIN_PRBSERR_1_D0 0xa44 +#define mmMC_TRAIN_PRBSERR_2_D0 0xafb +#define mmMC_TRAIN_EDC_STATUS_D0 0xa45 +#define mmMC_TRAIN_PRBSERR_0_D1 0xa46 +#define mmMC_TRAIN_PRBSERR_1_D1 0xa47 +#define mmMC_TRAIN_PRBSERR_2_D1 0xafc +#define mmMC_TRAIN_EDC_STATUS_D1 0xa48 +#define mmMC_IO_TXCNTL_DPHY0_D0 0xa49 +#define mmMC_IO_TXCNTL_DPHY1_D0 0xa4a +#define mmMC_IO_TXCNTL_APHY_D0 0xa4b +#define mmMC_IO_RXCNTL_DPHY0_D0 0xa4c +#define mmMC_IO_RXCNTL1_DPHY0_D0 0xadf +#define mmMC_IO_RXCNTL_DPHY1_D0 0xa4d +#define mmMC_IO_RXCNTL1_DPHY1_D0 0xae0 +#define mmMC_IO_DPHY_STR_CNTL_D0 0xa4e +#define mmMC_IO_APHY_STR_CNTL_D0 0xa97 +#define mmMC_IO_TXCNTL_DPHY0_D1 0xa4f +#define mmMC_IO_TXCNTL_DPHY1_D1 0xa50 +#define mmMC_IO_TXCNTL_APHY_D1 0xa51 +#define mmMC_IO_RXCNTL_DPHY0_D1 0xa52 +#define mmMC_IO_RXCNTL1_DPHY0_D1 0xae1 +#define mmMC_IO_RXCNTL_DPHY1_D1 0xa53 +#define mmMC_IO_RXCNTL1_DPHY1_D1 0xae2 +#define mmMC_IO_DPHY_STR_CNTL_D1 0xa54 +#define mmMC_IO_APHY_STR_CNTL_D1 0xa98 +#define mmMC_IO_CDRCNTL_D0 0xa55 +#define mmMC_IO_CDRCNTL1_D0 0xadd +#define mmMC_IO_CDRCNTL2_D0 0xae4 +#define mmMC_IO_CDRCNTL_D1 0xa56 +#define mmMC_IO_CDRCNTL1_D1 0xade +#define mmMC_IO_CDRCNTL2_D1 0xae5 +#define mmMC_SEQ_FIFO_CTL 0xa57 +#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0xa58 +#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0xa59 +#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0xa5a +#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0xa5b +#define mmMC_SEQ_TXFRAMING_DBI_D0 0xa5c +#define mmMC_SEQ_TXFRAMING_EDC_D0 0xa5d +#define mmMC_SEQ_TXFRAMING_FCK_D0 0xa5e +#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0xa60 +#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0xa61 +#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0xa62 +#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0xa63 +#define mmMC_SEQ_TXFRAMING_DBI_D1 0xa64 +#define mmMC_SEQ_TXFRAMING_EDC_D1 0xa65 +#define mmMC_SEQ_TXFRAMING_FCK_D1 0xa66 +#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0xa67 +#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0xa68 +#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0xa69 +#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0xa6a +#define mmMC_SEQ_RXFRAMING_DBI_D0 0xa6b +#define mmMC_SEQ_RXFRAMING_EDC_D0 0xa6c +#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0xa6d +#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0xa6e +#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0xa6f +#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0xa70 +#define mmMC_SEQ_RXFRAMING_DBI_D1 0xa71 +#define mmMC_SEQ_RXFRAMING_EDC_D1 0xa72 +#define mmMC_IO_PAD_CNTL 0xa73 +#define mmMC_IO_PAD_CNTL_D0 0xa74 +#define mmMC_IO_PAD_CNTL_D1 0xa75 +#define mmMC_NPL_STATUS 0xa76 +#define mmMC_BIST_CMD_CNTL 0xa8e +#define mmMC_BIST_CNTL 0xa05 +#define mmMC_BIST_AUTO_CNTL 0xa06 +#define mmMC_BIST_DIR_CNTL 0xa07 +#define mmMC_BIST_SADDR 0xa08 +#define mmMC_BIST_EADDR 0xa09 +#define mmMC_BIST_CMP_CNTL 0xa8d +#define mmMC_BIST_CMP_CNTL_2 0xab6 +#define mmMC_BIST_DATA_WORD0 0xa0a +#define mmMC_BIST_DATA_WORD1 0xa0b +#define mmMC_BIST_DATA_WORD2 0xa0c +#define mmMC_BIST_DATA_WORD3 0xa0d +#define mmMC_BIST_DATA_WORD4 0xa0e +#define mmMC_BIST_DATA_WORD5 0xa0f +#define mmMC_BIST_DATA_WORD6 0xa10 +#define mmMC_BIST_DATA_WORD7 0xa11 +#define mmMC_BIST_DATA_MASK 0xa12 +#define mmMC_BIST_MISMATCH_ADDR 0xa13 +#define mmMC_BIST_RDATA_WORD0 0xa14 +#define mmMC_BIST_RDATA_WORD1 0xa15 +#define mmMC_BIST_RDATA_WORD2 0xa16 +#define mmMC_BIST_RDATA_WORD3 0xa17 +#define mmMC_BIST_RDATA_WORD4 0xa18 +#define mmMC_BIST_RDATA_WORD5 0xa19 +#define mmMC_BIST_RDATA_WORD6 0xa1a +#define mmMC_BIST_RDATA_WORD7 0xa1b +#define mmMC_BIST_RDATA_MASK 0xa1c +#define mmMC_BIST_RDATA_EDC 0xa1d +#define mmMC_SEQ_PERF_CNTL 0xa77 +#define mmMC_SEQ_PERF_CNTL_1 0xafd +#define mmMC_SEQ_PERF_SEQ_CTL 0xa78 +#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0xa79 +#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0xa7a +#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0xa7b +#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0xa7c +#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0xad9 +#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0xada +#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0xadb +#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0xadc +#define mmMC_SEQ_STATUS_M 0xa7d +#define mmMC_SEQ_STATUS_S 0xa20 +#define mmMC_CG_DATAPORT 0xa21 +#define mmMC_SEQ_VENDOR_ID_I0 0xa7e +#define mmMC_SEQ_VENDOR_ID_I1 0xa7f +#define mmMC_SEQ_MISC0 0xa80 +#define mmMC_SEQ_MISC1 0xa81 +#define mmMC_SEQ_RESERVE_0_S 0xa1e +#define mmMC_SEQ_RESERVE_1_S 0xa1f +#define mmMC_SEQ_RESERVE_M 0xa82 +#define mmMC_SEQ_IO_RESERVE_D0 0xab7 +#define mmMC_SEQ_IO_RESERVE_D1 0xab8 +#define mmMC_SEQ_SUP_CNTL 0xa32 +#define mmMC_SEQ_SUP_PGM 0xa33 +#define mmMC_SEQ_SUP_GP0_STAT 0xa8f +#define mmMC_SEQ_SUP_GP1_STAT 0xa90 +#define mmMC_SEQ_SUP_GP2_STAT 0xa85 +#define mmMC_SEQ_SUP_GP3_STAT 0xa86 +#define mmMC_SEQ_SUP_IR_STAT 0xa87 +#define mmMC_SEQ_SUP_DEC_STAT 0xa88 +#define mmMC_SEQ_SUP_PGM_STAT 0xa89 +#define mmMC_SEQ_SUP_R_PGM 0xa8a +#define mmMC_SEQ_MISC3 0xa8b +#define mmMC_SEQ_MISC4 0xa8c +#define mmMC_SEQ_MISC5 0xa95 +#define mmMC_SEQ_MISC6 0xa96 +#define mmMC_SEQ_MISC7 0xa99 +#define mmMC_SEQ_MISC8 0xa5f +#define mmMC_SEQ_MISC9 0xae7 +#define mmMC_SEQ_CG 0xa9a +#define mmMC_SEQ_BYTE_REMAP_D0 0xa93 +#define mmMC_SEQ_BYTE_REMAP_D1 0xa94 +#define mmMC_SEQ_BIT_REMAP_B0_D0 0xaa3 +#define mmMC_SEQ_BIT_REMAP_B1_D0 0xaa4 +#define mmMC_SEQ_BIT_REMAP_B2_D0 0xaa5 +#define mmMC_SEQ_BIT_REMAP_B3_D0 0xaa6 +#define mmMC_SEQ_BIT_REMAP_B0_D1 0xaa7 +#define mmMC_SEQ_BIT_REMAP_B1_D1 0xaa8 +#define mmMC_SEQ_BIT_REMAP_B2_D1 0xaa9 +#define mmMC_SEQ_BIT_REMAP_B3_D1 0xaaa +#define mmMC_SEQ_RAS_TIMING_LP 0xa9b +#define mmMC_SEQ_CAS_TIMING_LP 0xa9c +#define mmMC_SEQ_MISC_TIMING_LP 0xa9d +#define mmMC_SEQ_MISC_TIMING2_LP 0xa9e +#define mmMC_SEQ_RD_CTL_D0_LP 0xac7 +#define mmMC_SEQ_RD_CTL_D1_LP 0xac8 +#define mmMC_SEQ_WR_CTL_D0_LP 0xa9f +#define mmMC_SEQ_WR_CTL_D1_LP 0xaa0 +#define mmMC_SEQ_WR_CTL_2_LP 0xad6 +#define mmMC_SEQ_PMG_CMD_EMRS_LP 0xaa1 +#define mmMC_SEQ_PMG_CMD_MRS_LP 0xaa2 +#define mmMC_SEQ_PMG_CMD_MRS1_LP 0xad2 +#define mmMC_SEQ_PMG_CMD_MRS2_LP 0xad8 +#define mmMC_SEQ_PMG_TIMING_LP 0xad3 +#define mmMC_SEQ_IO_RWORD0 0xaac +#define mmMC_SEQ_IO_RWORD1 0xaad +#define mmMC_SEQ_IO_RWORD2 0xaae +#define mmMC_SEQ_IO_RWORD3 0xaaf +#define mmMC_SEQ_IO_RWORD4 0xab0 +#define mmMC_SEQ_IO_RWORD5 0xab1 +#define mmMC_SEQ_IO_RWORD6 0xab2 +#define mmMC_SEQ_IO_RWORD7 0xab3 +#define mmMC_SEQ_IO_RDBI 0xab4 +#define mmMC_SEQ_IO_REDC 0xab5 +#define mmMC_SEQ_TCG_CNTL 0xabd +#define mmMC_SEQ_TSM_CTRL 0xabe +#define mmMC_SEQ_TSM_GCNT 0xabf +#define mmMC_SEQ_TSM_OCNT 0xac0 +#define mmMC_SEQ_TSM_NCNT 0xac1 +#define mmMC_SEQ_TSM_BCNT 0xac2 +#define mmMC_SEQ_TSM_FLAG 0xac3 +#define mmMC_SEQ_TSM_UPDATE 0xac4 +#define mmMC_SEQ_TSM_EDC 0xac5 +#define mmMC_SEQ_TSM_DBI 0xac6 +#define mmMC_SEQ_TSM_WCDR 0xae3 +#define mmMC_SEQ_TSM_MISC 0xae6 +#define mmMC_SEQ_TIMER_WR 0xac9 +#define mmMC_SEQ_TIMER_RD 0xaca +#define mmMC_SEQ_DRAM_ERROR_INSERTION 0xacb +#define mmMC_PHY_TIMING_D0 0xacc +#define mmMC_PHY_TIMING_D1 0xacd +#define mmMC_PHY_TIMING_2 0xace +#define mmMC_SEQ_MPLL_OVERRIDE 0xa22 +#define mmMCLK_PWRMGT_CNTL 0xae8 +#define mmDLL_CNTL 0xae9 +#define mmMPLL_SEQ_UCODE_1 0xaea +#define mmMPLL_SEQ_UCODE_2 0xaeb +#define mmMPLL_CNTL_MODE 0xaec +#define mmMPLL_FUNC_CNTL 0xaed +#define mmMPLL_FUNC_CNTL_1 0xaee +#define mmMPLL_FUNC_CNTL_2 0xaef +#define mmMPLL_AD_FUNC_CNTL 0xaf0 +#define mmMPLL_DQ_FUNC_CNTL 0xaf1 +#define mmMPLL_TIME 0xaf2 +#define mmMPLL_SS1 0xaf3 +#define mmMPLL_SS2 0xaf4 +#define mmMPLL_CONTROL 0xaf5 +#define mmMPLL_AD_STATUS 0xaf6 +#define mmMPLL_DQ_0_0_STATUS 0xaf7 +#define mmMPLL_DQ_0_1_STATUS 0xaf8 +#define mmMPLL_DQ_1_0_STATUS 0xaf9 +#define mmMPLL_DQ_1_1_STATUS 0xafa +#define mmMC_SEQ_PMG_PG_HWCNTL 0xab9 +#define mmMC_SEQ_PMG_PG_SWCNTL_0 0xaba +#define mmMC_SEQ_PMG_PG_SWCNTL_1 0xabb +#define mmMC_SEQ_TSM_DEBUG_INDEX 0xacf +#define mmMC_SEQ_TSM_DEBUG_DATA 0xad0 +#define ixMC_TSM_DEBUG_GCNT 0x0 +#define ixMC_TSM_DEBUG_FLAG 0x1 +#define ixMC_TSM_DEBUG_MISC 0x2 +#define ixMC_TSM_DEBUG_BCNT0 0x3 +#define ixMC_TSM_DEBUG_BCNT1 0x4 +#define ixMC_TSM_DEBUG_BCNT2 0x5 +#define ixMC_TSM_DEBUG_BCNT3 0x6 +#define ixMC_TSM_DEBUG_BCNT4 0x7 +#define ixMC_TSM_DEBUG_BCNT5 0x8 +#define ixMC_TSM_DEBUG_BCNT6 0x9 +#define ixMC_TSM_DEBUG_BCNT7 0xa +#define ixMC_TSM_DEBUG_BCNT8 0xb +#define ixMC_TSM_DEBUG_BCNT9 0xc +#define ixMC_TSM_DEBUG_BCNT10 0xd +#define ixMC_TSM_DEBUG_ST01 0x10 +#define ixMC_TSM_DEBUG_ST23 0x11 +#define ixMC_TSM_DEBUG_ST45 0x12 +#define ixMC_TSM_DEBUG_BKPT 0x13 +#define mmMC_SEQ_IO_DEBUG_INDEX 0xa91 +#define mmMC_SEQ_IO_DEBUG_DATA 0xa92 +#define ixMC_IO_DEBUG_UP_0 0x0 +#define ixMC_IO_DEBUG_UP_1 0x1 +#define ixMC_IO_DEBUG_UP_2 0x2 +#define ixMC_IO_DEBUG_UP_3 0x3 +#define ixMC_IO_DEBUG_UP_4 0x4 +#define ixMC_IO_DEBUG_UP_5 0x5 +#define ixMC_IO_DEBUG_UP_6 0x6 +#define ixMC_IO_DEBUG_UP_7 0x7 +#define ixMC_IO_DEBUG_UP_8 0x8 +#define ixMC_IO_DEBUG_UP_9 0x9 +#define ixMC_IO_DEBUG_UP_10 0xa +#define ixMC_IO_DEBUG_UP_11 0xb +#define ixMC_IO_DEBUG_UP_12 0xc +#define ixMC_IO_DEBUG_UP_13 0xd +#define ixMC_IO_DEBUG_UP_14 0xe +#define ixMC_IO_DEBUG_UP_15 0xf +#define ixMC_IO_DEBUG_UP_16 0x10 +#define ixMC_IO_DEBUG_UP_17 0x11 +#define ixMC_IO_DEBUG_UP_18 0x12 +#define ixMC_IO_DEBUG_UP_19 0x13 +#define ixMC_IO_DEBUG_UP_20 0x14 +#define ixMC_IO_DEBUG_UP_21 0x15 +#define ixMC_IO_DEBUG_UP_22 0x16 +#define ixMC_IO_DEBUG_UP_23 0x17 +#define ixMC_IO_DEBUG_UP_24 0x18 +#define ixMC_IO_DEBUG_UP_25 0x19 +#define ixMC_IO_DEBUG_UP_26 0x1a +#define ixMC_IO_DEBUG_UP_27 0x1b +#define ixMC_IO_DEBUG_UP_28 0x1c +#define ixMC_IO_DEBUG_UP_29 0x1d +#define ixMC_IO_DEBUG_UP_30 0x1e +#define ixMC_IO_DEBUG_UP_31 0x1f +#define ixMC_IO_DEBUG_UP_32 0x20 +#define ixMC_IO_DEBUG_UP_33 0x21 +#define ixMC_IO_DEBUG_UP_34 0x22 +#define ixMC_IO_DEBUG_UP_35 0x23 +#define ixMC_IO_DEBUG_UP_36 0x24 +#define ixMC_IO_DEBUG_UP_37 0x25 +#define ixMC_IO_DEBUG_UP_38 0x26 +#define ixMC_IO_DEBUG_UP_39 0x27 +#define ixMC_IO_DEBUG_UP_40 0x28 +#define ixMC_IO_DEBUG_UP_41 0x29 +#define ixMC_IO_DEBUG_UP_42 0x2a +#define ixMC_IO_DEBUG_UP_43 0x2b +#define ixMC_IO_DEBUG_UP_44 0x2c +#define ixMC_IO_DEBUG_UP_45 0x2d +#define ixMC_IO_DEBUG_UP_46 0x2e +#define ixMC_IO_DEBUG_UP_47 0x2f +#define ixMC_IO_DEBUG_UP_48 0x30 +#define ixMC_IO_DEBUG_UP_49 0x31 +#define ixMC_IO_DEBUG_UP_50 0x32 +#define ixMC_IO_DEBUG_UP_51 0x33 +#define ixMC_IO_DEBUG_UP_52 0x34 +#define ixMC_IO_DEBUG_UP_53 0x35 +#define ixMC_IO_DEBUG_UP_54 0x36 +#define ixMC_IO_DEBUG_UP_55 0x37 +#define ixMC_IO_DEBUG_UP_56 0x38 +#define ixMC_IO_DEBUG_UP_57 0x39 +#define ixMC_IO_DEBUG_UP_58 0x3a +#define ixMC_IO_DEBUG_UP_59 0x3b +#define ixMC_IO_DEBUG_UP_60 0x3c +#define ixMC_IO_DEBUG_UP_61 0x3d +#define ixMC_IO_DEBUG_UP_62 0x3e +#define ixMC_IO_DEBUG_UP_63 0x3f +#define ixMC_IO_DEBUG_UP_64 0x40 +#define ixMC_IO_DEBUG_UP_65 0x41 +#define ixMC_IO_DEBUG_UP_66 0x42 +#define ixMC_IO_DEBUG_UP_67 0x43 +#define ixMC_IO_DEBUG_UP_68 0x44 +#define ixMC_IO_DEBUG_UP_69 0x45 +#define ixMC_IO_DEBUG_UP_70 0x46 +#define ixMC_IO_DEBUG_UP_71 0x47 +#define ixMC_IO_DEBUG_UP_72 0x48 +#define ixMC_IO_DEBUG_UP_73 0x49 +#define ixMC_IO_DEBUG_UP_74 0x4a +#define ixMC_IO_DEBUG_UP_75 0x4b +#define ixMC_IO_DEBUG_UP_76 0x4c +#define ixMC_IO_DEBUG_UP_77 0x4d +#define ixMC_IO_DEBUG_UP_78 0x4e +#define ixMC_IO_DEBUG_UP_79 0x4f +#define ixMC_IO_DEBUG_UP_80 0x50 +#define ixMC_IO_DEBUG_UP_81 0x51 +#define ixMC_IO_DEBUG_UP_82 0x52 +#define ixMC_IO_DEBUG_UP_83 0x53 +#define ixMC_IO_DEBUG_UP_84 0x54 +#define ixMC_IO_DEBUG_UP_85 0x55 +#define ixMC_IO_DEBUG_UP_86 0x56 +#define ixMC_IO_DEBUG_UP_87 0x57 +#define ixMC_IO_DEBUG_UP_88 0x58 +#define ixMC_IO_DEBUG_UP_89 0x59 +#define ixMC_IO_DEBUG_UP_90 0x5a +#define ixMC_IO_DEBUG_UP_91 0x5b +#define ixMC_IO_DEBUG_UP_92 0x5c +#define ixMC_IO_DEBUG_UP_93 0x5d +#define ixMC_IO_DEBUG_UP_94 0x5e +#define ixMC_IO_DEBUG_UP_95 0x5f +#define ixMC_IO_DEBUG_UP_96 0x60 +#define ixMC_IO_DEBUG_UP_97 0x61 +#define ixMC_IO_DEBUG_UP_98 0x62 +#define ixMC_IO_DEBUG_UP_99 0x63 +#define ixMC_IO_DEBUG_UP_100 0x64 +#define ixMC_IO_DEBUG_UP_101 0x65 +#define ixMC_IO_DEBUG_UP_102 0x66 +#define ixMC_IO_DEBUG_UP_103 0x67 +#define ixMC_IO_DEBUG_UP_104 0x68 +#define ixMC_IO_DEBUG_UP_105 0x69 +#define ixMC_IO_DEBUG_UP_106 0x6a +#define ixMC_IO_DEBUG_UP_107 0x6b +#define ixMC_IO_DEBUG_UP_108 0x6c +#define ixMC_IO_DEBUG_UP_109 0x6d +#define ixMC_IO_DEBUG_UP_110 0x6e +#define ixMC_IO_DEBUG_UP_111 0x6f +#define ixMC_IO_DEBUG_UP_112 0x70 +#define ixMC_IO_DEBUG_UP_113 0x71 +#define ixMC_IO_DEBUG_UP_114 0x72 +#define ixMC_IO_DEBUG_UP_115 0x73 +#define ixMC_IO_DEBUG_UP_116 0x74 +#define ixMC_IO_DEBUG_UP_117 0x75 +#define ixMC_IO_DEBUG_UP_118 0x76 +#define ixMC_IO_DEBUG_UP_119 0x77 +#define ixMC_IO_DEBUG_UP_120 0x78 +#define ixMC_IO_DEBUG_UP_121 0x79 +#define ixMC_IO_DEBUG_UP_122 0x7a +#define ixMC_IO_DEBUG_UP_123 0x7b +#define ixMC_IO_DEBUG_UP_124 0x7c +#define ixMC_IO_DEBUG_UP_125 0x7d +#define ixMC_IO_DEBUG_UP_126 0x7e +#define ixMC_IO_DEBUG_UP_127 0x7f +#define ixMC_IO_DEBUG_UP_128 0x80 +#define ixMC_IO_DEBUG_UP_129 0x81 +#define ixMC_IO_DEBUG_UP_130 0x82 +#define ixMC_IO_DEBUG_UP_131 0x83 +#define ixMC_IO_DEBUG_UP_132 0x84 +#define ixMC_IO_DEBUG_UP_133 0x85 +#define ixMC_IO_DEBUG_UP_134 0x86 +#define ixMC_IO_DEBUG_UP_135 0x87 +#define ixMC_IO_DEBUG_UP_136 0x88 +#define ixMC_IO_DEBUG_UP_137 0x89 +#define ixMC_IO_DEBUG_UP_138 0x8a +#define ixMC_IO_DEBUG_UP_139 0x8b +#define ixMC_IO_DEBUG_UP_140 0x8c +#define ixMC_IO_DEBUG_UP_141 0x8d +#define ixMC_IO_DEBUG_UP_142 0x8e +#define ixMC_IO_DEBUG_UP_143 0x8f +#define ixMC_IO_DEBUG_UP_144 0x90 +#define ixMC_IO_DEBUG_UP_145 0x91 +#define ixMC_IO_DEBUG_UP_146 0x92 +#define ixMC_IO_DEBUG_UP_147 0x93 +#define ixMC_IO_DEBUG_UP_148 0x94 +#define ixMC_IO_DEBUG_UP_149 0x95 +#define ixMC_IO_DEBUG_UP_150 0x96 +#define ixMC_IO_DEBUG_UP_151 0x97 +#define ixMC_IO_DEBUG_UP_152 0x98 +#define ixMC_IO_DEBUG_UP_153 0x99 +#define ixMC_IO_DEBUG_UP_154 0x9a +#define ixMC_IO_DEBUG_UP_155 0x9b +#define ixMC_IO_DEBUG_UP_156 0x9c +#define ixMC_IO_DEBUG_UP_157 0x9d +#define ixMC_IO_DEBUG_UP_158 0x9e +#define ixMC_IO_DEBUG_UP_159 0x9f +#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0xa0 +#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0xa1 +#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0xa2 +#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0xa3 +#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0xa4 +#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0xa5 +#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0xa6 +#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0xa7 +#define ixMC_IO_DEBUG_DBI_MISC_D0 0xa8 +#define ixMC_IO_DEBUG_EDC_MISC_D0 0xa9 +#define ixMC_IO_DEBUG_WCK_MISC_D0 0xaa +#define ixMC_IO_DEBUG_CK_MISC_D0 0xab +#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0xac +#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0xad +#define ixMC_IO_DEBUG_ACMD_MISC_D0 0xae +#define ixMC_IO_DEBUG_CMD_MISC_D0 0xaf +#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0xb0 +#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0xb1 +#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0xb2 +#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0xb3 +#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0xb4 +#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0xb5 +#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0xb6 +#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0xb7 +#define ixMC_IO_DEBUG_DBI_MISC_D1 0xb8 +#define ixMC_IO_DEBUG_EDC_MISC_D1 0xb9 +#define ixMC_IO_DEBUG_WCK_MISC_D1 0xba +#define ixMC_IO_DEBUG_CK_MISC_D1 0xbb +#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0xbc +#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0xbd +#define ixMC_IO_DEBUG_ACMD_MISC_D1 0xbe +#define ixMC_IO_DEBUG_CMD_MISC_D1 0xbf +#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0xc0 +#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0xc1 +#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0xc2 +#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0xc3 +#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0xc4 +#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0xc5 +#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0xc6 +#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0xc7 +#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0xc8 +#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0xc9 +#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0xca +#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0xcb +#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0xcc +#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0xcd +#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0xce +#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0xcf +#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0xd0 +#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0xd1 +#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0xd2 +#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0xd3 +#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0xd4 +#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0xd5 +#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0xd6 +#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0xd7 +#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0xd8 +#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0xd9 +#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0xda +#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0xdb +#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0xdc +#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0xdd +#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0xde +#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0xdf +#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0xe0 +#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0xe1 +#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0xe2 +#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0xe3 +#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0xe4 +#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0xe5 +#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0xe6 +#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0xe7 +#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0xe8 +#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0xe9 +#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0xea +#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0xeb +#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0xec +#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0xed +#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0xee +#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0xef +#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0xf0 +#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0xf1 +#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0xf2 +#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0xf3 +#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0xf4 +#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0xf5 +#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0xf6 +#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0xf7 +#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0xf8 +#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0xf9 +#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0xfa +#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0xfb +#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0xfc +#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0xfd +#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0xfe +#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0xff +#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x100 +#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x101 +#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x102 +#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x103 +#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x104 +#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x105 +#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x106 +#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x107 +#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x108 +#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x109 +#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x10a +#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x10b +#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x10c +#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x10d +#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x10e +#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x10f +#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x110 +#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x111 +#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x112 +#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x113 +#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x114 +#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x115 +#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x116 +#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x117 +#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x118 +#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x119 +#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x11a +#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x11b +#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x11c +#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x11d +#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x11e +#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x11f +#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x120 +#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x121 +#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x122 +#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x123 +#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x124 +#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125 +#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x126 +#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x127 +#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x128 +#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x129 +#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x12a +#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x12b +#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x12c +#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x12d +#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x12e +#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x12f +#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x130 +#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x131 +#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x132 +#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x133 +#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x134 +#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x135 +#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x136 +#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x137 +#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x138 +#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x139 +#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x13a +#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x13b +#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x13c +#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x13d +#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x13e +#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x13f +#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x140 +#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x141 +#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x142 +#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x143 +#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x144 +#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x145 +#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x146 +#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x147 +#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x148 +#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x149 +#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x14a +#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x14b +#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x14c +#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x14d +#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x14e +#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x14f +#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x150 +#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x151 +#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x152 +#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x153 +#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x154 +#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x155 +#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x156 +#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x157 +#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x158 +#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x159 +#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x15a +#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x15b +#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x15c +#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x15d +#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x15e +#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x15f +#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x160 +#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x161 +#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x162 +#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x163 +#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x164 +#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x165 +#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x166 +#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x167 +#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x168 +#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x169 +#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x16a +#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x16b +#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x16c +#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x16d +#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x16e +#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x16f +#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x170 +#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x171 +#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x172 +#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x173 +#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x174 +#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x175 +#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x176 +#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x177 +#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x178 +#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x179 +#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x17a +#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x17b +#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x17c +#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x17d +#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x17e +#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x17f +#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x180 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x181 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x182 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x183 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x184 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x185 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x186 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x187 +#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x188 +#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x189 +#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x18a +#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x18b +#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x18c +#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x18d +#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x18e +#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x18f +#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x190 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x191 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x192 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x193 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x194 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x195 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x196 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x197 +#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x198 +#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x199 +#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x19a +#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x19b +#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x19c +#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x19d +#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x19e +#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x19f +#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x1a0 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x1a1 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x1a2 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x1a3 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x1a4 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x1a5 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x1a6 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x1a7 +#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x1a8 +#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x1a9 +#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x1aa +#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x1ab +#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x1ac +#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x1ad +#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x1ae +#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x1af +#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x1b0 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x1b1 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x1b2 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x1b3 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x1b4 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x1b5 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x1b6 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x1b7 +#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x1b8 +#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x1b9 +#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x1ba +#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x1bb +#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x1bc +#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x1bd +#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x1be +#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x1bf +#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x1c0 +#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x1c1 +#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x1c2 +#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x1c3 +#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x1c4 +#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x1c5 +#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x1c6 +#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x1c7 +#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x1c8 +#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x1c9 +#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x1ca +#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x1cb +#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x1cc +#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x1cd +#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x1ce +#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x1cf +#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x1d0 +#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x1d1 +#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x1d2 +#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x1d3 +#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x1d4 +#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x1d5 +#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x1d6 +#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x1d7 +#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x1d8 +#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x1d9 +#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x1da +#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x1db +#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x1dc +#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x1dd +#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x1de +#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x1df +#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x1e0 +#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x1e1 +#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x1e2 +#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x1e3 +#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x1e4 +#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x1e5 +#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x1e6 +#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x1e7 +#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x1e8 +#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x1e9 +#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x1ea +#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x1eb +#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x1ec +#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x1f0 +#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x1f1 +#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x1f2 +#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x1f3 +#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x1f4 +#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x1f5 +#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x1f6 +#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x1f7 +#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x1f8 +#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x1f9 +#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x1fa +#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x1fb +#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x1fc +#define mmMC_SEQ_CNTL_3 0xd80 +#define mmMC_SEQ_G5PDX_CTRL 0xd81 +#define mmMC_SEQ_G5PDX_CTRL_LP 0xd82 +#define mmMC_SEQ_G5PDX_CMD0 0xd83 +#define mmMC_SEQ_G5PDX_CMD0_LP 0xd84 +#define mmMC_SEQ_G5PDX_CMD1 0xd85 +#define mmMC_SEQ_G5PDX_CMD1_LP 0xd86 +#define mmMC_SEQ_SREG_READ 0xd87 +#define mmMC_SEQ_SREG_STATUS 0xd88 +#define mmMC_SEQ_PHYREG_BCAST 0xd89 +#define mmMC_SEQ_PMG_DVS_CTL 0xd8a +#define mmMC_SEQ_PMG_DVS_CTL_LP 0xd8b +#define mmMC_SEQ_PMG_DVS_CMD 0xd8c +#define mmMC_SEQ_PMG_DVS_CMD_LP 0xd8d +#define mmMC_SEQ_DLL_STBY 0xd8e +#define mmMC_SEQ_DLL_STBY_LP 0xd8f +#define mmMC_DLB_MISCCTRL0 0xd90 +#define mmMC_DLB_MISCCTRL1 0xd91 +#define mmMC_DLB_MISCCTRL2 0xd92 +#define mmMC_DLB_CONFIG0 0xd93 +#define mmMC_DLB_CONFIG1 0xd94 +#define mmMC_DLB_SETUP 0xd95 +#define mmMC_DLB_SETUPSWEEP 0xd96 +#define mmMC_DLB_SETUPFIFO 0xd97 +#define mmMC_DLB_WRITE_MASK 0xd98 +#define mmMC_DLB_STATUS 0xd99 +#define mmMC_DLB_STATUS_MISC0 0xd9a +#define mmMC_DLB_STATUS_MISC1 0xd9b +#define mmMC_DLB_STATUS_MISC2 0xd9c +#define mmMC_DLB_STATUS_MISC3 0xd9d +#define mmMC_DLB_STATUS_MISC4 0xd9e +#define mmMC_DLB_STATUS_MISC5 0xd9f +#define mmMC_DLB_STATUS_MISC6 0xda0 +#define mmMC_DLB_STATUS_MISC7 0xda1 +#define mmMC_ARB_HARSH_EN_RD 0xdc0 +#define mmMC_ARB_HARSH_EN_WR 0xdc1 +#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2 +#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3 +#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4 +#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5 +#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6 +#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7 +#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8 +#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9 +#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca +#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb +#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc +#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd +#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce +#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf +#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0 +#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1 +#define mmMC_ARB_HARSH_SAT0_RD 0xdd2 +#define mmMC_ARB_HARSH_SAT0_WR 0xdd3 +#define mmMC_ARB_HARSH_SAT1_RD 0xdd4 +#define mmMC_ARB_HARSH_SAT1_WR 0xdd5 +#define mmMC_ARB_HARSH_CTL_RD 0xdd6 +#define mmMC_ARB_HARSH_CTL_WR 0xdd7 + +#endif /* GMC_7_1_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h new file mode 100644 index 000000000000..3a202b69d5aa --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h @@ -0,0 +1,14416 @@ +/* + * GMC_7_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_7_1_SH_MASK_H +#define GMC_7_1_SH_MASK_H + +#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 +#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 +#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 +#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 +#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 +#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 +#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 +#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 +#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 +#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 +#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20 +#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5 +#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40 +#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6 +#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80 +#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7 +#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700 +#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8 +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000 +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13 +#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000 +#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16 +#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000 +#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19 +#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff +#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9 +#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400 +#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa +#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800 +#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd +#define MC_ARB_FED_CNTL__MODE_MASK 0x3 +#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0 +#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc +#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2 +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10 +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4 +#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20 +#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5 +#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40 +#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6 +#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80 +#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7 +#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1 +#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0 +#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2 +#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1 +#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4 +#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2 +#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8 +#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3 +#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10 +#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4 +#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20 +#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5 +#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40 +#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6 +#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80 +#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9 +#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400 +#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa +#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800 +#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd +#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000 +#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe +#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000 +#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11 +#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000 +#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15 +#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000 +#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19 +#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000 +#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d +#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf +#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0 +#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10 +#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4 +#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20 +#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5 +#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40 +#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6 +#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80 +#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7 +#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100 +#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8 +#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200 +#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9 +#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400 +#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa +#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800 +#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb +#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000 +#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc +#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000 +#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3 +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0 +#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4 +#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2 +#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18 +#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3 +#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20 +#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5 +#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff +#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0 +#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00 +#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8 +#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000 +#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10 +#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000 +#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18 +#define MC_ARB_PERF_CID__CH0_MASK 0xff +#define MC_ARB_PERF_CID__CH0__SHIFT 0x0 +#define MC_ARB_PERF_CID__CH1_MASK 0xff00 +#define MC_ARB_PERF_CID__CH1__SHIFT 0x8 +#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000 +#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10 +#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000 +#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11 +#define MC_ARB_GECC2__ENABLE_MASK 0x1 +#define MC_ARB_GECC2__ENABLE__SHIFT 0x0 +#define MC_ARB_GECC2__ECC_MODE_MASK 0x6 +#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1 +#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18 +#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3 +#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60 +#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5 +#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780 +#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7 +#define MC_ARB_GECC2__READ_ERR_MASK 0x3800 +#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb +#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000 +#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe +#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000 +#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf +#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000 +#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15 +#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000 +#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18 +#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf +#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0 +#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0 +#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4 +#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00 +#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8 +#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000 +#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc +#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000 +#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10 +#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000 +#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14 +#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000 +#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18 +#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000 +#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c +#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf +#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0 +#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0 +#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4 +#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00 +#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8 +#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000 +#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc +#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1 +#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0 +#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2 +#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1 +#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4 +#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2 +#define MC_ARB_MISC3__TBD_FIELD_MASK 0xfffffff8 +#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x3 +#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0xf +#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x0 +#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x1f0 +#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x4 +#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x200 +#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x9 +#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x400 +#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa +#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800 +#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0xb +#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x1000 +#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0xc +#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x2000 +#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0xd +#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x4000 +#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0xe +#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff +#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0 +#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1 +#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0 +#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2 +#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1 +#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc +#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2 +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10 +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4 +#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20 +#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5 +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40 +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6 +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80 +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7 +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100 +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800 +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000 +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17 +#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000 +#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18 +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000 +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5 +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0 +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6 +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000 +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc +#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000 +#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19 +#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1 +#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0 +#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e +#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1 +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80 +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7 +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000 +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa +#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800 +#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb +#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000 +#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc +#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000 +#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd +#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000 +#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe +#define MC_ARB_MISC2__GECC_MASK 0x40000 +#define MC_ARB_MISC2__GECC__SHIFT 0x12 +#define MC_ARB_MISC2__GECC_RST_MASK 0x80000 +#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13 +#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000 +#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14 +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000 +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15 +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000 +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19 +#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000 +#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c +#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000 +#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000 +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000 +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f +#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1 +#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0 +#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2 +#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1 +#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4 +#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2 +#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8 +#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3 +#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800 +#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb +#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000 +#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13 +#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000 +#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14 +#define MC_ARB_MISC__CALI_RATES_MASK 0x600000 +#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15 +#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000 +#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17 +#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000 +#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18 +#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000 +#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19 +#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000 +#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a +#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000 +#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e +#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000 +#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f +#define MC_ARB_BANKMAP__BANK0_MASK 0xf +#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0 +#define MC_ARB_BANKMAP__BANK1_MASK 0xf0 +#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4 +#define MC_ARB_BANKMAP__BANK2_MASK 0xf00 +#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8 +#define MC_ARB_BANKMAP__BANK3_MASK 0xf000 +#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc +#define MC_ARB_BANKMAP__RANK_MASK 0xf0000 +#define MC_ARB_BANKMAP__RANK__SHIFT 0x10 +#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3 +#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0 +#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4 +#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2 +#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38 +#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3 +#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0 +#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6 +#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100 +#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8 +#define MC_ARB_RAMCFG__RSV_1_MASK 0x200 +#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9 +#define MC_ARB_RAMCFG__RSV_2_MASK 0x400 +#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa +#define MC_ARB_RAMCFG__RSV_3_MASK 0x800 +#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb +#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000 +#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc +#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000 +#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd +#define MC_ARB_POP__ENABLE_ARB_MASK 0x1 +#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0 +#define MC_ARB_POP__SPEC_OPEN_MASK 0x2 +#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1 +#define MC_ARB_POP__POP_DEPTH_MASK 0x3c +#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2 +#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0 +#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6 +#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000 +#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc +#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000 +#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf +#define MC_ARB_POP__QUICK_STOP_MASK 0x20000 +#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11 +#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000 +#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12 +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000 +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13 +#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff +#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0 +#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00 +#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8 +#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000 +#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10 +#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000 +#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11 +#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff +#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0 +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100 +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8 +#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200 +#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9 +#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00 +#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa +#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000 +#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10 +#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000 +#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18 +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0 +#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0 +#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4 +#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000 +#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc +#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff +#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00 +#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000 +#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18 +#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff +#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00 +#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000 +#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18 +#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3 +#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0 +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4 +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa +#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800 +#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb +#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000 +#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc +#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000 +#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd +#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3 +#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0 +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4 +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa +#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800 +#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb +#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000 +#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc +#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000 +#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd +#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3 +#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0 +#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc +#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2 +#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30 +#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4 +#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0 +#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6 +#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300 +#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8 +#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00 +#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa +#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000 +#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc +#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000 +#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000 +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10 +#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3 +#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0 +#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc +#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2 +#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30 +#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4 +#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0 +#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6 +#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300 +#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8 +#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00 +#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa +#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000 +#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc +#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000 +#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000 +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10 +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1 +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0 +#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6 +#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1 +#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8 +#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3 +#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10 +#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4 +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1 +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0 +#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6 +#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1 +#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8 +#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3 +#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10 +#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4 +#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff +#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff +#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff +#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff +#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3 +#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc +#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2 +#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30 +#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4 +#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0 +#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6 +#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300 +#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8 +#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00 +#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa +#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000 +#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc +#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000 +#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe +#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000 +#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10 +#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000 +#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11 +#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000 +#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12 +#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000 +#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13 +#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000 +#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14 +#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000 +#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15 +#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000 +#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16 +#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000 +#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17 +#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18 +#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19 +#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a +#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b +#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c +#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d +#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e +#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f +#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3 +#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc +#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2 +#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30 +#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4 +#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0 +#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6 +#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300 +#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8 +#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00 +#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa +#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000 +#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc +#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000 +#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe +#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000 +#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10 +#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000 +#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11 +#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000 +#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12 +#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000 +#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13 +#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000 +#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14 +#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000 +#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15 +#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000 +#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16 +#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000 +#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17 +#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18 +#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19 +#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a +#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b +#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c +#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d +#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e +#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f +#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1 +#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0 +#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e +#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1 +#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0 +#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6 +#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800 +#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb +#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000 +#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc +#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000 +#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd +#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000 +#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe +#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff +#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0 +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3 +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0 +#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4 +#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2 +#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8 +#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3 +#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10 +#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4 +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20 +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5 +#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40 +#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6 +#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80 +#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7 +#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300 +#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8 +#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400 +#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa +#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800 +#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb +#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000 +#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc +#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000 +#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd +#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000 +#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000 +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf +#define MC_ARB_PM_CNTL__RSV_0_MASK 0x30000 +#define MC_ARB_PM_CNTL__RSV_0__SHIFT 0x10 +#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000 +#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12 +#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000 +#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13 +#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000 +#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14 +#define MC_ARB_PM_CNTL__RSV_1_MASK 0x1000000 +#define MC_ARB_PM_CNTL__RSV_1__SHIFT 0x18 +#define MC_ARB_PM_CNTL__RSV_2_MASK 0x2000000 +#define MC_ARB_PM_CNTL__RSV_2__SHIFT 0x19 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4 +#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100 +#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8 +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200 +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9 +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4 +#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100 +#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8 +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200 +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9 +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa +#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff +#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0 +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00 +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8 +#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000 +#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10 +#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000 +#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11 +#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000 +#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12 +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000 +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13 +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000 +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14 +#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000 +#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15 +#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff +#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0 +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00 +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8 +#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000 +#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10 +#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000 +#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11 +#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000 +#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12 +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000 +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13 +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000 +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14 +#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000 +#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15 +#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000 +#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18 +#define MC_ARB_REMREQ__RD_WATER_MASK 0xff +#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0 +#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00 +#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8 +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000 +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10 +#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000 +#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14 +#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000 +#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18 +#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1 +#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0 +#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2 +#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1 +#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4 +#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2 +#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8 +#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3 +#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10 +#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4 +#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20 +#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5 +#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40 +#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6 +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80 +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7 +#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00 +#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8 +#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000 +#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf +#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff +#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0 +#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00 +#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8 +#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000 +#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10 +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000 +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18 +#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff +#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0 +#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00 +#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8 +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000 +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10 +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000 +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18 +#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000 +#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c +#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff +#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0 +#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00 +#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8 +#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000 +#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10 +#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000 +#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13 +#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff +#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0 +#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff +#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0 +#define MC_ARB_SSM__FORMAT_MASK 0x1f +#define MC_ARB_SSM__FORMAT__SHIFT 0x0 +#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff +#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0 +#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00 +#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8 +#define MC_ARB_CG__RSV_0_MASK 0xff0000 +#define MC_ARB_CG__RSV_0__SHIFT 0x10 +#define MC_ARB_CG__RSV_1_MASK 0xff000000 +#define MC_ARB_CG__RSV_1__SHIFT 0x18 +#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x1 +#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x0 +#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x2 +#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x1 +#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x7c +#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x2 +#define MC_ARB_WCDR__IDLE_BURST_MASK 0x1f80 +#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x7 +#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x2000 +#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0xd +#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0xc000 +#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0xe +#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x10000 +#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x10 +#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x20000 +#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x11 +#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x3c0000 +#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x12 +#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x1c00000 +#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x16 +#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x2000000 +#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x19 +#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x4000000 +#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x1a +#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x8000000 +#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x1b +#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000 +#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x1c +#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff +#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00 +#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000 +#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18 +#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1 +#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0 +#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2 +#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1 +#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4 +#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2 +#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8 +#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3 +#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10 +#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4 +#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20 +#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5 +#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40 +#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6 +#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80 +#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7 +#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100 +#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8 +#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200 +#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9 +#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400 +#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa +#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800 +#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb +#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000 +#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc +#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000 +#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd +#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000 +#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe +#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000 +#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf +#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000 +#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10 +#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000 +#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11 +#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000 +#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12 +#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000 +#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13 +#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000 +#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14 +#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000 +#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15 +#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000 +#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16 +#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000 +#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17 +#define MC_ARB_BUSY_STATUS__WCDR0_MASK 0x1000000 +#define MC_ARB_BUSY_STATUS__WCDR0__SHIFT 0x18 +#define MC_ARB_BUSY_STATUS__WCDR1_MASK 0x2000000 +#define MC_ARB_BUSY_STATUS__WCDR1__SHIFT 0x19 +#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000 +#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a +#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000 +#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b +#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000 +#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c +#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000 +#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d +#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000 +#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e +#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000 +#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00 +#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000 +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18 +#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f +#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0 +#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0 +#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5 +#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00 +#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa +#define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000 +#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf +#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1 +#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0 +#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2 +#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1 +#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4 +#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2 +#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8 +#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3 +#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10 +#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4 +#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00 +#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8 +#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000 +#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc +#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000 +#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd +#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000 +#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf +#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000 +#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11 +#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000 +#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13 +#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000 +#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15 +#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000 +#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17 +#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000 +#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19 +#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000 +#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a +#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000 +#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b +#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000 +#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c +#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000 +#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d +#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e +#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1 +#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1 +#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 +#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2 +#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 +#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4 +#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 +#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 +#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 +#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30 +#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4 +#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0 +#define MC_CG_CONFIG__INDEX__SHIFT 0x6 +#define MC_CITF_CNTL__IGNOREPM_MASK 0x4 +#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2 +#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8 +#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3 +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30 +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4 +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40 +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6 +#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180 +#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7 +#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200 +#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9 +#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f +#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0 +#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0 +#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6 +#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff +#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00 +#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8 +#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000 +#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10 +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000 +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18 +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000 +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19 +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00 +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8 +#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000 +#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10 +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000 +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18 +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000 +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19 +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1 +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0 +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1 +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20 +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5 +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0 +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6 +#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f +#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12 +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000 +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18 +#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1 +#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0 +#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2 +#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1 +#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4 +#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2 +#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8 +#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3 +#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10 +#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4 +#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20 +#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5 +#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40 +#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6 +#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80 +#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7 +#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f +#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0 +#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000 +#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10 +#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000 +#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18 +#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf +#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0 +#define MC_RD_GRP_EXT__TC0_MASK 0xf0 +#define MC_RD_GRP_EXT__TC0__SHIFT 0x4 +#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf +#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0 +#define MC_WR_GRP_EXT__TC0_MASK 0xf0 +#define MC_WR_GRP_EXT__TC0__SHIFT 0x4 +#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f +#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0 +#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80 +#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7 +#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000 +#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe +#define MC_WR_TC0__ENABLE_MASK 0x1 +#define MC_WR_TC0__ENABLE__SHIFT 0x0 +#define MC_WR_TC0__PRESCALE_MASK 0x6 +#define MC_WR_TC0__PRESCALE__SHIFT 0x1 +#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_TC0__STALL_MODE_MASK 0x30 +#define MC_WR_TC0__STALL_MODE__SHIFT 0x4 +#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_TC0__MAX_BURST_MASK 0x780 +#define MC_WR_TC0__MAX_BURST__SHIFT 0x7 +#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800 +#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb +#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_TC1__ENABLE_MASK 0x1 +#define MC_WR_TC1__ENABLE__SHIFT 0x0 +#define MC_WR_TC1__PRESCALE_MASK 0x6 +#define MC_WR_TC1__PRESCALE__SHIFT 0x1 +#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_TC1__STALL_MODE_MASK 0x30 +#define MC_WR_TC1__STALL_MODE__SHIFT 0x4 +#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_TC1__MAX_BURST_MASK 0x780 +#define MC_WR_TC1__MAX_BURST__SHIFT 0x7 +#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800 +#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb +#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6 +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000 +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18 +#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000 +#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19 +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000 +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18 +#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000 +#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19 +#define MC_RD_CB__ENABLE_MASK 0x1 +#define MC_RD_CB__ENABLE__SHIFT 0x0 +#define MC_RD_CB__PRESCALE_MASK 0x6 +#define MC_RD_CB__PRESCALE__SHIFT 0x1 +#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_CB__STALL_MODE_MASK 0x30 +#define MC_RD_CB__STALL_MODE__SHIFT 0x4 +#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_CB__MAX_BURST_MASK 0x780 +#define MC_RD_CB__MAX_BURST__SHIFT 0x7 +#define MC_RD_CB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_DB__ENABLE_MASK 0x1 +#define MC_RD_DB__ENABLE__SHIFT 0x0 +#define MC_RD_DB__PRESCALE_MASK 0x6 +#define MC_RD_DB__PRESCALE__SHIFT 0x1 +#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_DB__STALL_MODE_MASK 0x30 +#define MC_RD_DB__STALL_MODE__SHIFT 0x4 +#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_DB__MAX_BURST_MASK 0x780 +#define MC_RD_DB__MAX_BURST__SHIFT 0x7 +#define MC_RD_DB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_TC0__ENABLE_MASK 0x1 +#define MC_RD_TC0__ENABLE__SHIFT 0x0 +#define MC_RD_TC0__PRESCALE_MASK 0x6 +#define MC_RD_TC0__PRESCALE__SHIFT 0x1 +#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_TC0__STALL_MODE_MASK 0x30 +#define MC_RD_TC0__STALL_MODE__SHIFT 0x4 +#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_TC0__MAX_BURST_MASK 0x780 +#define MC_RD_TC0__MAX_BURST__SHIFT 0x7 +#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800 +#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb +#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_TC1__ENABLE_MASK 0x1 +#define MC_RD_TC1__ENABLE__SHIFT 0x0 +#define MC_RD_TC1__PRESCALE_MASK 0x6 +#define MC_RD_TC1__PRESCALE__SHIFT 0x1 +#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_TC1__STALL_MODE_MASK 0x30 +#define MC_RD_TC1__STALL_MODE__SHIFT 0x4 +#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_TC1__MAX_BURST_MASK 0x780 +#define MC_RD_TC1__MAX_BURST__SHIFT 0x7 +#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800 +#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb +#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_HUB__ENABLE_MASK 0x1 +#define MC_RD_HUB__ENABLE__SHIFT 0x0 +#define MC_RD_HUB__PRESCALE_MASK 0x6 +#define MC_RD_HUB__PRESCALE__SHIFT 0x1 +#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_HUB__STALL_MODE_MASK 0x30 +#define MC_RD_HUB__STALL_MODE__SHIFT 0x4 +#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_HUB__MAX_BURST_MASK 0x780 +#define MC_RD_HUB__MAX_BURST__SHIFT 0x7 +#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_CB__ENABLE_MASK 0x1 +#define MC_WR_CB__ENABLE__SHIFT 0x0 +#define MC_WR_CB__PRESCALE_MASK 0x6 +#define MC_WR_CB__PRESCALE__SHIFT 0x1 +#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_CB__STALL_MODE_MASK 0x30 +#define MC_WR_CB__STALL_MODE__SHIFT 0x4 +#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_CB__MAX_BURST_MASK 0x780 +#define MC_WR_CB__MAX_BURST__SHIFT 0x7 +#define MC_WR_CB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_DB__ENABLE_MASK 0x1 +#define MC_WR_DB__ENABLE__SHIFT 0x0 +#define MC_WR_DB__PRESCALE_MASK 0x6 +#define MC_WR_DB__PRESCALE__SHIFT 0x1 +#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_DB__STALL_MODE_MASK 0x30 +#define MC_WR_DB__STALL_MODE__SHIFT 0x4 +#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_DB__MAX_BURST_MASK 0x780 +#define MC_WR_DB__MAX_BURST__SHIFT 0x7 +#define MC_WR_DB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_HUB__ENABLE_MASK 0x1 +#define MC_WR_HUB__ENABLE__SHIFT 0x0 +#define MC_WR_HUB__PRESCALE_MASK 0x6 +#define MC_WR_HUB__PRESCALE__SHIFT 0x1 +#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_HUB__STALL_MODE_MASK 0x30 +#define MC_WR_HUB__STALL_MODE__SHIFT 0x4 +#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_HUB__MAX_BURST_MASK 0x780 +#define MC_WR_HUB__MAX_BURST__SHIFT 0x7 +#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff +#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00 +#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8 +#define MC_RD_GRP_LCL__CB0_MASK 0xf000 +#define MC_RD_GRP_LCL__CB0__SHIFT 0xc +#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000 +#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10 +#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000 +#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14 +#define MC_RD_GRP_LCL__DB0_MASK 0xf000000 +#define MC_RD_GRP_LCL__DB0__SHIFT 0x18 +#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000 +#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c +#define MC_WR_GRP_LCL__CB0_MASK 0xf +#define MC_WR_GRP_LCL__CB0__SHIFT 0x0 +#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0 +#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4 +#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00 +#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8 +#define MC_WR_GRP_LCL__DB0_MASK 0xf000 +#define MC_WR_GRP_LCL__DB0__SHIFT 0xc +#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000 +#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10 +#define MC_WR_GRP_LCL__SX0_MASK 0xf00000 +#define MC_WR_GRP_LCL__SX0__SHIFT 0x14 +#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000 +#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c +#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff +#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0 +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x40 +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x6 +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x80 +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x7 +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x100 +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x8 +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x200 +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x9 +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x400 +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0xa +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x800 +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0xb +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x1000 +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0xc +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x2000 +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0xd +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x4000 +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0xe +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x8000 +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xf +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x10000 +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x10 +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x20000 +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x11 +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x40000 +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x12 +#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4 +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2 +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18 +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3 +#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1 +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0 +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2 +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x4 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x2 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x8 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x3 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x10 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x4 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x20 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x5 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x40 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x6 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x80 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x7 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x100 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x8 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x200 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x9 +#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x400 +#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xa +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x800 +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0xb +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x1000 +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0xc +#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x2000 +#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0xd +#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3 +#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0 +#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff +#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3 +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 +#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0 +#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf +#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000 +#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10 +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000 +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11 +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000 +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12 +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000 +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13 +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000 +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14 +#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000 +#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15 +#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000 +#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16 +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1 +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0 +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2 +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1 +#define MC_HUB_WDP_BP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe +#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1 +#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000 +#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12 +#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1 +#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0 +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2 +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4 +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8 +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10 +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 +#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20 +#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 +#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40 +#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 +#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80 +#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 +#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100 +#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 +#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200 +#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9 +#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400 +#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa +#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800 +#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb +#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000 +#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc +#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000 +#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd +#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000 +#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe +#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000 +#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf +#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000 +#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10 +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000 +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11 +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000 +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12 +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000 +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13 +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000 +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14 +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000 +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15 +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000 +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16 +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1 +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0 +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2 +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4 +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8 +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10 +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 +#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20 +#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 +#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40 +#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 +#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80 +#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 +#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100 +#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200 +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9 +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400 +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800 +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000 +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000 +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000 +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000 +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1 +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0 +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2 +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1 +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4 +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2 +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8 +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3 +#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10 +#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4 +#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20 +#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5 +#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40 +#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6 +#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80 +#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7 +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1 +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3 +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20 +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5 +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40 +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6 +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80 +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7 +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100 +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8 +#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200 +#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9 +#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400 +#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa +#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800 +#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb +#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000 +#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000 +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd +#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000 +#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16 +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000 +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17 +#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000 +#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18 +#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000 +#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19 +#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1 +#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0 +#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe +#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1 +#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000 +#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15 +#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000 +#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16 +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000 +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000 +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff +#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00 +#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8 +#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000 +#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10 +#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000 +#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18 +#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff +#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00 +#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8 +#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf +#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0 +#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0 +#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8 +#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000 +#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11 +#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf +#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0 +#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0 +#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8 +#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000 +#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11 +#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff +#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0 +#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00 +#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8 +#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000 +#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10 +#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000 +#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18 +#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff +#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0 +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00 +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8 +#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f +#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0 +#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000 +#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10 +#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000 +#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ_MASK 0x100000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ__SHIFT 0x14 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE_MASK 0x200000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE__SHIFT 0x15 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x400000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x16 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x800000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x17 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x1000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x18 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x2000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x19 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x4000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x1a +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x8000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x1b +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x10000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1c +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x20000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1d +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x40000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1e +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x80000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1f +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3 +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2 +#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3 +#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c +#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2 +#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe +#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1 +#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00 +#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9 +#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000 +#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11 +#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000 +#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18 +#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe +#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1 +#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00 +#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9 +#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000 +#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11 +#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000 +#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18 +#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe +#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1 +#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00 +#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9 +#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_IA0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_IA0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_IA0__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_IA0__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_IA0__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_IA0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_IA0__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_IA0__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_IA0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_IA0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_IA1__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_IA1__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_IA1__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_IA1__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_IA1__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_IA1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_IA1__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_IA1__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_IA1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_IA1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f +#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0 +#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x80 +#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x7 +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00 +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8 +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0 +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00 +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8 +#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_CPG__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_CPG__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_CPG__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_CPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_CPG__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_CPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_CPG__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_CPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_CPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_CPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCE__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_VCE__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_IA__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_IA__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_IA__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_IA__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_IA__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_IA__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_IA__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_IA__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_IA__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_IA__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_IA__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3 +#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc +#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2 +#define MC_HUB_WDP_CPG__ENABLE_MASK 0x1 +#define MC_HUB_WDP_CPG__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_CPG__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_CPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_CPG__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_CPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_CPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_CPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_CPG__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_CPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_CPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_CPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_VCE__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VCE__VM_BYPASS_MASK 0x10000 +#define MC_HUB_WDP_VCE__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_IH__ENABLE_MASK 0x1 +#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1 +#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1 +#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1 +#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000 +#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_SAM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SAM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SAM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SAM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SAM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_SAM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SAM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SAM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SAM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SAM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_CPC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_CPC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_CPC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_CPC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_CPC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_CPC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_CPC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_CPC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_CPC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_CPC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_CPF__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_CPF__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_CPF__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_CPF__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_CPF__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_CPF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_CPF__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_CPF__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_CPF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_CPF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_CPC__ENABLE_MASK 0x1 +#define MC_HUB_WDP_CPC__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_CPC__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_CPC__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_CPC__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_CPC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_CPC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_CPC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_CPC__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_CPC__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_CPC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_CPC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_CPF__ENABLE_MASK 0x1 +#define MC_HUB_WDP_CPF__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_CPF__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_CPF__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_CPF__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_CPF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_CPF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_CPF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_CPF__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_CPF__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_CPF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_CPF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff +#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0 +#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000 +#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000 +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10 +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000 +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11 +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0 +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00 +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8 +#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000 +#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14 +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00 +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1 +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0 +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6 +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1 +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78 +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3 +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80 +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100 +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8 +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600 +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9 +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800 +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb +#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000 +#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300 +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8 +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00 +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10 +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0 +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1 +#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e +#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000 +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 +#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1 +#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0 +#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6 +#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1 +#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8 +#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3 +#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0 +#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4 +#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00 +#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8 +#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000 +#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10 +#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000 +#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18 +#define MC_SHARED_CHMAP__CHAN0_MASK 0xf +#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0 +#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0 +#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4 +#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00 +#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8 +#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000 +#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc +#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000 +#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10 +#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000 +#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14 +#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf +#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0 +#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0 +#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4 +#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00 +#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8 +#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000 +#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc +#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000 +#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10 +#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000 +#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14 +#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000 +#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18 +#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000 +#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c +#define MC_RD_GRP_GFX__CP_MASK 0xf +#define MC_RD_GRP_GFX__CP__SHIFT 0x0 +#define MC_RD_GRP_GFX__SH_MASK 0xf0 +#define MC_RD_GRP_GFX__SH__SHIFT 0x4 +#define MC_RD_GRP_GFX__IA_MASK 0xf00 +#define MC_RD_GRP_GFX__IA__SHIFT 0x8 +#define MC_RD_GRP_GFX__ACPG_MASK 0xf000 +#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc +#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000 +#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10 +#define MC_RD_GRP_GFX__ISP_MASK 0xf00000 +#define MC_RD_GRP_GFX__ISP__SHIFT 0x14 +#define MC_RD_GRP_GFX__XDMAM_MASK 0xf000000 +#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x18 +#define MC_WR_GRP_GFX__CP_MASK 0xf +#define MC_WR_GRP_GFX__CP__SHIFT 0x0 +#define MC_WR_GRP_GFX__SH_MASK 0xf0 +#define MC_WR_GRP_GFX__SH__SHIFT 0x4 +#define MC_WR_GRP_GFX__ACPG_MASK 0xf00 +#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8 +#define MC_WR_GRP_GFX__ACPO_MASK 0xf000 +#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc +#define MC_WR_GRP_GFX__ISP_MASK 0xf0000 +#define MC_WR_GRP_GFX__ISP__SHIFT 0x10 +#define MC_WR_GRP_GFX__XDMA_MASK 0xf00000 +#define MC_WR_GRP_GFX__XDMA__SHIFT 0x14 +#define MC_WR_GRP_GFX__XDMAM_MASK 0xf000000 +#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x18 +#define MC_RD_GRP_SYS__RLC_MASK 0xf +#define MC_RD_GRP_SYS__RLC__SHIFT 0x0 +#define MC_RD_GRP_SYS__VMC_MASK 0xf0 +#define MC_RD_GRP_SYS__VMC__SHIFT 0x4 +#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00 +#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8 +#define MC_RD_GRP_SYS__DMIF_MASK 0xf000 +#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc +#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000 +#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10 +#define MC_RD_GRP_SYS__SMU_MASK 0xf00000 +#define MC_RD_GRP_SYS__SMU__SHIFT 0x14 +#define MC_RD_GRP_SYS__VCE_MASK 0xf000000 +#define MC_RD_GRP_SYS__VCE__SHIFT 0x18 +#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000 +#define MC_RD_GRP_SYS__VCEU__SHIFT 0x1c +#define MC_WR_GRP_SYS__IH_MASK 0xf +#define MC_WR_GRP_SYS__IH__SHIFT 0x0 +#define MC_WR_GRP_SYS__MCIF_MASK 0xf0 +#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4 +#define MC_WR_GRP_SYS__RLC_MASK 0xf00 +#define MC_WR_GRP_SYS__RLC__SHIFT 0x8 +#define MC_WR_GRP_SYS__SAM_MASK 0xf000 +#define MC_WR_GRP_SYS__SAM__SHIFT 0xc +#define MC_WR_GRP_SYS__SMU_MASK 0xf0000 +#define MC_WR_GRP_SYS__SMU__SHIFT 0x10 +#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000 +#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14 +#define MC_WR_GRP_SYS__VCE_MASK 0xf000000 +#define MC_WR_GRP_SYS__VCE__SHIFT 0x18 +#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000 +#define MC_WR_GRP_SYS__VCEU__SHIFT 0x1c +#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf +#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0 +#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0 +#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4 +#define MC_RD_GRP_OTH__HDP_MASK 0xf00 +#define MC_RD_GRP_OTH__HDP__SHIFT 0x8 +#define MC_RD_GRP_OTH__SEM_MASK 0xf000 +#define MC_RD_GRP_OTH__SEM__SHIFT 0xc +#define MC_RD_GRP_OTH__UMC_MASK 0xf0000 +#define MC_RD_GRP_OTH__UMC__SHIFT 0x10 +#define MC_RD_GRP_OTH__UVD_MASK 0xf00000 +#define MC_RD_GRP_OTH__UVD__SHIFT 0x14 +#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000 +#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18 +#define MC_RD_GRP_OTH__SAM_MASK 0xf0000000 +#define MC_RD_GRP_OTH__SAM__SHIFT 0x1c +#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf +#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0 +#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0 +#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4 +#define MC_WR_GRP_OTH__HDP_MASK 0xf00 +#define MC_WR_GRP_OTH__HDP__SHIFT 0x8 +#define MC_WR_GRP_OTH__SEM_MASK 0xf000 +#define MC_WR_GRP_OTH__SEM__SHIFT 0xc +#define MC_WR_GRP_OTH__UMC_MASK 0xf0000 +#define MC_WR_GRP_OTH__UMC__SHIFT 0x10 +#define MC_WR_GRP_OTH__UVD_MASK 0xf00000 +#define MC_WR_GRP_OTH__UVD__SHIFT 0x14 +#define MC_WR_GRP_OTH__XDP_MASK 0xf000000 +#define MC_WR_GRP_OTH__XDP__SHIFT 0x18 +#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000 +#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c +#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff +#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0 +#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000 +#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10 +#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff +#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff +#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff +#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9 +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff +#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3 +#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf +#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0 +#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0 +#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4 +#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00 +#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8 +#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000 +#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc +#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000 +#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10 +#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000 +#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14 +#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000 +#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18 +#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000 +#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c +#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 +#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 +#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 +#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 +#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 +#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 +#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 +#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 +#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 +#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 +#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 +#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 +#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40 +#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6 +#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80 +#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7 +#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 +#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 +#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800 +#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb +#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000 +#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc +#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000 +#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000 +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 +#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40 +#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6 +#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80 +#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb +#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000 +#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd +#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f +#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0 +#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0 +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff +#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00 +#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8 +#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000 +#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10 +#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000 +#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11 +#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000 +#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19 +#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff +#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0 +#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00 +#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa +#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000 +#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14 +#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000 +#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0 +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0 +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6 +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000 +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0 +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0 +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6 +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000 +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc +#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff +#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000 +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000 +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 +#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff +#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0 +#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000 +#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10 +#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000 +#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12 +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 +#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30 +#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40 +#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 +#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80 +#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100 +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200 +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400 +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa +#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800 +#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000 +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc +#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff +#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff +#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00 +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8 +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000 +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00 +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 +#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2 +#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f +#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0 +#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0 +#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6 +#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000 +#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc +#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000 +#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12 +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000 +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 +#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00 +#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 +#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000 +#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000 +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000 +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000 +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000 +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 +#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00 +#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000 +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000 +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 +#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000 +#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 +#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000 +#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000 +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1 +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000 +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000 +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 +#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000 +#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000 +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1 +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2 +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4 +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8 +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10 +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20 +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40 +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80 +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100 +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200 +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 +#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400 +#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa +#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800 +#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb +#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000 +#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc +#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000 +#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd +#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000 +#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe +#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000 +#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf +#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000 +#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 +#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000 +#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 +#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000 +#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 +#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000 +#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0 +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000 +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc +#define MC_XPB_STICKY__BITS_MASK 0xffffffff +#define MC_XPB_STICKY__BITS__SHIFT 0x0 +#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff +#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0 +#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff +#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 +#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00 +#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 +#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000 +#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 +#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000 +#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 +#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000 +#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f +#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff +#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00 +#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8 +#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000 +#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10 +#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000 +#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11 +#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000 +#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19 +#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1 +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0 +#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2 +#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4 +#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3 +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1 +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0 +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2 +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1 +#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000 +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3 +#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0 +#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc +#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2 +#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30 +#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4 +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1 +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0 +#define MC_XBAR_TWOCHAN__CH0_MASK 0x6 +#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1 +#define MC_XBAR_TWOCHAN__CH1_MASK 0x18 +#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3 +#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1 +#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0 +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2 +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1 +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4 +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c +#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0xfff +#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0 +#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000 +#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc +#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x3000000 +#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x18 +#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000 +#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a +#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 +#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c +#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff +#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 +#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xff00 +#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x8 +#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000 +#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10 +#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0xff +#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x0 +#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0xff00 +#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x8 +#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0xff0000 +#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x10 +#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000 +#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x18 +#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffff +#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x0 +#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffff +#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x0 +#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffff +#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x0 +#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffff +#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x0 +#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0xff +#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x0 +#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0xff00 +#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x8 +#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0xff0000 +#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x10 +#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000 +#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x18 +#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff +#define MC_XBAR_SPARE0__BIT__SHIFT 0x0 +#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff +#define MC_XBAR_SPARE1__BIT__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP_MASK 0x1 +#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP__SHIFT 0x0 +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3 +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3 +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 +#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1 +#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 +#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2 +#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 +#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4 +#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 +#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00 +#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 +#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000 +#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10 +#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1 +#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0 +#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2 +#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1 +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4 +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2 +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20 +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5 +#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40 +#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6 +#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80 +#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7 +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100 +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8 +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200 +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9 +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00 +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000 +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe +#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000 +#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000 +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10 +#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000 +#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11 +#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000 +#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12 +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0 +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100 +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8 +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000 +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10 +#define ATC_ATS_STATUS__BUSY_MASK 0x1 +#define ATC_ATS_STATUS__BUSY__SHIFT 0x0 +#define ATC_ATS_STATUS__CRASHED_MASK 0x2 +#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x3f +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0xfc00 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x3f00000 +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x3f +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00 +#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffff +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1 +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x3c +#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x2 +#define ATC_MISC_CG__OFFDLY_MASK 0xfc0 +#define ATC_MISC_CG__OFFDLY__SHIFT 0x6 +#define ATC_MISC_CG__ENABLE_MASK 0x40000 +#define ATC_MISC_CG__ENABLE__SHIFT 0x12 +#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000 +#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9 +#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f +#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00 +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000 +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf +#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f +#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0 +#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f +#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0 +#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0 +#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5 +#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100 +#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8 +#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200 +#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9 +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS_MASK 0x800 +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS__SHIFT 0xb +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS_MASK 0x1000 +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS__SHIFT 0xc +#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000 +#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe +#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000 +#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf +#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000 +#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11 +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3 +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0 +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4 +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2 +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10 +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4 +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0 +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 +#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 +#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e +#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 +#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 +#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 +#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e +#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 +#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f +#define ATC_L1RD_STATUS__BUSY_MASK 0x1 +#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0 +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2 +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 +#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100 +#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8 +#define ATC_L1WR_STATUS__BUSY_MASK 0x1 +#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0 +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2 +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 +#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100 +#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf +#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16 +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400 +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800 +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000 +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc +#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000 +#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10 +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000 +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11 +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000 +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13 +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000 +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15 +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000 +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16 +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000 +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17 +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000 +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18 +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000 +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19 +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000 +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a +#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000 +#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000 +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000 +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f +#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f +#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0 +#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0 +#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6 +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800 +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb +#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000 +#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11 +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000 +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000 +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e +#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000 +#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff +#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0 +#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000 +#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc +#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000 +#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18 +#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000 +#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c +#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000 +#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d +#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000 +#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e +#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000 +#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0 +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6 +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000 +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc +#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000 +#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12 +#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000 +#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19 +#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff +#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0 +#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff +#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0 +#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff +#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 +#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200 +#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400 +#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800 +#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000 +#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000 +#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd +#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000 +#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 +#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff +#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0 +#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff +#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0 +#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000 +#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18 +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000 +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c +#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff +#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0 +#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00 +#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8 +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000 +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 +#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000 +#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c +#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000 +#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d +#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000 +#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3 +#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0 +#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4 +#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff +#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0 +#define GMCON_DEBUG__GFX_STALL_MASK 0x1 +#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0 +#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2 +#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1 +#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffc +#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x2 +#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1 +#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800 +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000 +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000 +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000 +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000 +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000 +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1 +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000 +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000 +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f +#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000 +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VM_L2_STATUS__L2_BUSY_MASK 0x1 +#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 +#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 +#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2 +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1 +#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0 +#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2 +#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1 +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4 +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2 +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8 +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3 +#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10 +#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4 +#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20 +#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5 +#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40 +#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 +#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff +#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff +#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_DEBUG__FLAGS_MASK 0xffffffff +#define VM_DEBUG__FLAGS__SHIFT 0x0 +#define VM_L2_CG__OFFDLY_MASK 0xfc0 +#define VM_L2_CG__OFFDLY__SHIFT 0x6 +#define VM_L2_CG__ENABLE_MASK 0x40000 +#define VM_L2_CG__ENABLE__SHIFT 0x12 +#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000 +#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0 +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x1ff +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0 +#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x3 +#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x0 +#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0xc +#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x2 +#define MC_SEQ_CNTL__SAFE_MODE_MASK 0x30 +#define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x4 +#define MC_SEQ_CNTL__DAT_INV_MASK 0x40 +#define MC_SEQ_CNTL__DAT_INV__SHIFT 0x6 +#define MC_SEQ_CNTL__MSK_DF1_MASK 0x80 +#define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x7 +#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x300 +#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x8 +#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x4000 +#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0xe +#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x8000 +#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0xf +#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x10000 +#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x10 +#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x20000 +#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x11 +#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x40000 +#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x12 +#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x80000 +#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x13 +#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0xf00000 +#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x14 +#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0xf000000 +#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x18 +#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000 +#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x1c +#define MC_SEQ_CNTL_2__DRST_PDRV_MASK 0xf +#define MC_SEQ_CNTL_2__DRST_PDRV__SHIFT 0x0 +#define MC_SEQ_CNTL_2__DRST_PU_MASK 0x10 +#define MC_SEQ_CNTL_2__DRST_PU__SHIFT 0x4 +#define MC_SEQ_CNTL_2__DRST_PD_MASK 0x20 +#define MC_SEQ_CNTL_2__DRST_PD__SHIFT 0x5 +#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x300 +#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x8 +#define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0xfc00 +#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0xa +#define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x3f0000 +#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x10 +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x400000 +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x16 +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x800000 +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x17 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0xf000000 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x18 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x1c +#define MC_SEQ_DRAM__ADR_2CK_MASK 0x1 +#define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x0 +#define MC_SEQ_DRAM__ADR_MUX_MASK 0x2 +#define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x1 +#define MC_SEQ_DRAM__ADR_DF1_MASK 0x4 +#define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x2 +#define MC_SEQ_DRAM__AP8_MASK 0x8 +#define MC_SEQ_DRAM__AP8__SHIFT 0x3 +#define MC_SEQ_DRAM__DAT_DF1_MASK 0x10 +#define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x4 +#define MC_SEQ_DRAM__DQS_DF1_MASK 0x20 +#define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x5 +#define MC_SEQ_DRAM__DQM_DF1_MASK 0x40 +#define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x6 +#define MC_SEQ_DRAM__DQM_ACT_MASK 0x80 +#define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x7 +#define MC_SEQ_DRAM__STB_CNT_MASK 0xf00 +#define MC_SEQ_DRAM__STB_CNT__SHIFT 0x8 +#define MC_SEQ_DRAM__CKE_DYN_MASK 0x1000 +#define MC_SEQ_DRAM__CKE_DYN__SHIFT 0xc +#define MC_SEQ_DRAM__CKE_ACT_MASK 0x2000 +#define MC_SEQ_DRAM__CKE_ACT__SHIFT 0xd +#define MC_SEQ_DRAM__BO4_MASK 0x4000 +#define MC_SEQ_DRAM__BO4__SHIFT 0xe +#define MC_SEQ_DRAM__DLL_CLR_MASK 0x8000 +#define MC_SEQ_DRAM__DLL_CLR__SHIFT 0xf +#define MC_SEQ_DRAM__DLL_CNT_MASK 0xff0000 +#define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x10 +#define MC_SEQ_DRAM__DAT_INV_MASK 0x1000000 +#define MC_SEQ_DRAM__DAT_INV__SHIFT 0x18 +#define MC_SEQ_DRAM__INV_ACM_MASK 0x2000000 +#define MC_SEQ_DRAM__INV_ACM__SHIFT 0x19 +#define MC_SEQ_DRAM__ODT_ENB_MASK 0x4000000 +#define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x1a +#define MC_SEQ_DRAM__ODT_ACT_MASK 0x8000000 +#define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x1b +#define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000 +#define MC_SEQ_DRAM__RST_CTL__SHIFT 0x1c +#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000 +#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x1d +#define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000 +#define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x1e +#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS_MASK 0x80000000 +#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS__SHIFT 0x1f +#define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x1 +#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x0 +#define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x2 +#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x1 +#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x4 +#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x2 +#define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x8 +#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x3 +#define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x10 +#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x4 +#define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x20 +#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x5 +#define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x40 +#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x6 +#define MC_SEQ_DRAM_2__DQM_EST_MASK 0x80 +#define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x7 +#define MC_SEQ_DRAM_2__RD_DQS_MASK 0x100 +#define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x8 +#define MC_SEQ_DRAM_2__WR_DQS_MASK 0x200 +#define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x9 +#define MC_SEQ_DRAM_2__PLL_EST_MASK 0x400 +#define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0xa +#define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x800 +#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0xb +#define MC_SEQ_DRAM_2__DLL_EST_MASK 0x1000 +#define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0xc +#define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x2000 +#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0xd +#define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x4000 +#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0xe +#define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x8000 +#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0xf +#define MC_SEQ_DRAM_2__PLL_CNT_MASK 0xff0000 +#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x10 +#define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x1000000 +#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x18 +#define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x2000000 +#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x19 +#define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x4000000 +#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x1a +#define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x8000000 +#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x1b +#define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000 +#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x1c +#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000 +#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x1d +#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000 +#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x1e +#define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000 +#define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x1f +#define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x1f +#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x0 +#define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x3e0 +#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x5 +#define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x7c00 +#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0xa +#define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0xf8000 +#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0xf +#define MC_SEQ_RAS_TIMING__TRRD_MASK 0xf00000 +#define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x14 +#define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000 +#define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x18 +#define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x3 +#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x0 +#define MC_SEQ_CAS_TIMING__TNOPR_MASK 0xc +#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x2 +#define MC_SEQ_CAS_TIMING__TR2W_MASK 0x1f0 +#define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x4 +#define MC_SEQ_CAS_TIMING__TCCDL_MASK 0xe00 +#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x9 +#define MC_SEQ_CAS_TIMING__TR2R_MASK 0xf000 +#define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0xc +#define MC_SEQ_CAS_TIMING__TW2R_MASK 0x1f0000 +#define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x10 +#define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000 +#define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x18 +#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x3f +#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x0 +#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x3f00 +#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x8 +#define MC_SEQ_MISC_TIMING__TRP_MASK 0xf8000 +#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0xf +#define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000 +#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x14 +#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x7 +#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x0 +#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x70 +#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x4 +#define MC_SEQ_MISC_TIMING2__FAW_MASK 0x1f00 +#define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x8 +#define MC_SEQ_MISC_TIMING2__TREDC_MASK 0xe000 +#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0xd +#define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x1f0000 +#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x10 +#define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x1e00000 +#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x15 +#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000 +#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x1c +#define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x7 +#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x0 +#define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x70 +#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x4 +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0xf00 +#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x8 +#define MC_SEQ_PMG_TIMING__TCKE_MASK 0x3f000 +#define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0xc +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x1c0000 +#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x12 +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x800000 +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x17 +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000 +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x18 +#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x7 +#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x0 +#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0xf8 +#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x3 +#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x300 +#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x8 +#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0xc00 +#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0xa +#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0xf000 +#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0xc +#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x10000 +#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x10 +#define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x20000 +#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x11 +#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x1f00000 +#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x14 +#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000 +#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x19 +#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x7 +#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x0 +#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0xf8 +#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x3 +#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x300 +#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x8 +#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0xc00 +#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0xa +#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0xf000 +#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0xc +#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x10000 +#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x10 +#define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x20000 +#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x11 +#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x1f00000 +#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x14 +#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000 +#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x19 +#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0xf +#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x0 +#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0xf0 +#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x4 +#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x100 +#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x8 +#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x200 +#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x9 +#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x400 +#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0xa +#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x800 +#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0xb +#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0xf000 +#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0xc +#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0xf0000 +#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x10 +#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x300000 +#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x14 +#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0xf000000 +#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18 +#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000 +#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x1c +#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000 +#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x1d +#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000 +#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x1e +#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0xf +#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x0 +#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0xf0 +#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x4 +#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x100 +#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x8 +#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x200 +#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x9 +#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x400 +#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0xa +#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x800 +#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0xb +#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0xf000 +#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0xc +#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0xf0000 +#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x10 +#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x300000 +#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x14 +#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0xf000000 +#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x18 +#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000 +#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x1c +#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000 +#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x1d +#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000 +#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x1e +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x1 +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x0 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x2 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x1 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x4 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x2 +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x8 +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x3 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x10 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x4 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x20 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x5 +#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x40 +#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x6 +#define MC_SEQ_CMD__ADR_MASK 0xffff +#define MC_SEQ_CMD__ADR__SHIFT 0x0 +#define MC_SEQ_CMD__MOP_MASK 0xf0000 +#define MC_SEQ_CMD__MOP__SHIFT 0x10 +#define MC_SEQ_CMD__END_MASK 0x100000 +#define MC_SEQ_CMD__END__SHIFT 0x14 +#define MC_SEQ_CMD__CSB_MASK 0x600000 +#define MC_SEQ_CMD__CSB__SHIFT 0x15 +#define MC_SEQ_CMD__CHAN0_MASK 0x1000000 +#define MC_SEQ_CMD__CHAN0__SHIFT 0x18 +#define MC_SEQ_CMD__CHAN1_MASK 0x2000000 +#define MC_SEQ_CMD__CHAN1__SHIFT 0x19 +#define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000 +#define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x1c +#define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000 +#define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_CMD_EMRS__ADR_MASK 0xffff +#define MC_PMG_CMD_EMRS__ADR__SHIFT 0x0 +#define MC_PMG_CMD_EMRS__MOP_MASK 0x70000 +#define MC_PMG_CMD_EMRS__MOP__SHIFT 0x10 +#define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x80000 +#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x13 +#define MC_PMG_CMD_EMRS__END_MASK 0x100000 +#define MC_PMG_CMD_EMRS__END__SHIFT 0x14 +#define MC_PMG_CMD_EMRS__CSB_MASK 0x600000 +#define MC_PMG_CMD_EMRS__CSB__SHIFT 0x15 +#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000 +#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x1c +#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000 +#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_CMD_MRS__ADR_MASK 0xffff +#define MC_PMG_CMD_MRS__ADR__SHIFT 0x0 +#define MC_PMG_CMD_MRS__MOP_MASK 0x70000 +#define MC_PMG_CMD_MRS__MOP__SHIFT 0x10 +#define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x80000 +#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x13 +#define MC_PMG_CMD_MRS__END_MASK 0x100000 +#define MC_PMG_CMD_MRS__END__SHIFT 0x14 +#define MC_PMG_CMD_MRS__CSB_MASK 0x600000 +#define MC_PMG_CMD_MRS__CSB__SHIFT 0x15 +#define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000 +#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x1c +#define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000 +#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_CMD_MRS1__ADR_MASK 0xffff +#define MC_PMG_CMD_MRS1__ADR__SHIFT 0x0 +#define MC_PMG_CMD_MRS1__MOP_MASK 0x70000 +#define MC_PMG_CMD_MRS1__MOP__SHIFT 0x10 +#define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x80000 +#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x13 +#define MC_PMG_CMD_MRS1__END_MASK 0x100000 +#define MC_PMG_CMD_MRS1__END__SHIFT 0x14 +#define MC_PMG_CMD_MRS1__CSB_MASK 0x600000 +#define MC_PMG_CMD_MRS1__CSB__SHIFT 0x15 +#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000 +#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x1c +#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000 +#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_CMD_MRS2__ADR_MASK 0xffff +#define MC_PMG_CMD_MRS2__ADR__SHIFT 0x0 +#define MC_PMG_CMD_MRS2__MOP_MASK 0x70000 +#define MC_PMG_CMD_MRS2__MOP__SHIFT 0x10 +#define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x80000 +#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x13 +#define MC_PMG_CMD_MRS2__END_MASK 0x100000 +#define MC_PMG_CMD_MRS2__END__SHIFT 0x14 +#define MC_PMG_CMD_MRS2__CSB_MASK 0x600000 +#define MC_PMG_CMD_MRS2__CSB__SHIFT 0x15 +#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000 +#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x1c +#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000 +#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_CFG__SYC_CLK_MASK 0x1 +#define MC_PMG_CFG__SYC_CLK__SHIFT 0x0 +#define MC_PMG_CFG__RST_MRS_MASK 0x2 +#define MC_PMG_CFG__RST_MRS__SHIFT 0x1 +#define MC_PMG_CFG__RST_EMRS_MASK 0x4 +#define MC_PMG_CFG__RST_EMRS__SHIFT 0x2 +#define MC_PMG_CFG__TRI_MIO_MASK 0x8 +#define MC_PMG_CFG__TRI_MIO__SHIFT 0x3 +#define MC_PMG_CFG__XSR_TMR_MASK 0xf0 +#define MC_PMG_CFG__XSR_TMR__SHIFT 0x4 +#define MC_PMG_CFG__RST_MRS1_MASK 0x100 +#define MC_PMG_CFG__RST_MRS1__SHIFT 0x8 +#define MC_PMG_CFG__RST_MRS2_MASK 0x200 +#define MC_PMG_CFG__RST_MRS2__SHIFT 0x9 +#define MC_PMG_CFG__DPM_WAKE_MASK 0x400 +#define MC_PMG_CFG__DPM_WAKE__SHIFT 0xa +#define MC_PMG_CFG__RFS_SRX_MASK 0x1000 +#define MC_PMG_CFG__RFS_SRX__SHIFT 0xc +#define MC_PMG_CFG__PREA_SRX_MASK 0x2000 +#define MC_PMG_CFG__PREA_SRX__SHIFT 0xd +#define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0xf0000 +#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x10 +#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x100000 +#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x14 +#define MC_PMG_CFG__YCLK_ON_MASK 0x200000 +#define MC_PMG_CFG__YCLK_ON__SHIFT 0x15 +#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x400000 +#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x16 +#define MC_PMG_CFG__RXPDNB_MASK 0x2000000 +#define MC_PMG_CFG__RXPDNB__SHIFT 0x19 +#define MC_PMG_CFG__ZQCL_SEND_MASK 0xc000000 +#define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x1a +#define MC_PMG_AUTO_CMD__ADR_MASK 0x1ffff +#define MC_PMG_AUTO_CMD__ADR__SHIFT 0x0 +#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000 +#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x1c +#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000 +#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x1 +#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x0 +#define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x2 +#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x1 +#define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x4 +#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x2 +#define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0xf0 +#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x4 +#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x100 +#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x8 +#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x200 +#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x9 +#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x400 +#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0xa +#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x800 +#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0xb +#define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x1000 +#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0xc +#define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x2000 +#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0xd +#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x4000 +#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0xe +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x8000 +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0xf +#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0xf0000 +#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x10 +#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x100000 +#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x14 +#define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x200000 +#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x15 +#define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x400000 +#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x16 +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x800000 +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x17 +#define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000 +#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x18 +#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x1f +#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x0 +#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x20 +#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x5 +#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x40 +#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x6 +#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x100 +#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x8 +#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x200 +#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x9 +#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0xe000 +#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0xd +#define MC_IMP_CNTL__CAL_VREF_MASK 0x7f0000 +#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x10 +#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000 +#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x1d +#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000 +#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x1e +#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000 +#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x1f +#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0xff +#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x0 +#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0xff00 +#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x8 +#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0xfff0000 +#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x10 +#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000 +#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x1c +#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000 +#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x1d +#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000 +#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x1e +#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000 +#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x1f +#define MC_IMP_STATUS__PSTR_CAL_MASK 0xff +#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x0 +#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0xff00 +#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x8 +#define MC_IMP_STATUS__NSTR_CAL_MASK 0xff0000 +#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x10 +#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000 +#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x18 +#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0xff +#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x0 +#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0xff00 +#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x8 +#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0xff0000 +#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x10 +#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000 +#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x18 +#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0xff +#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x0 +#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0xf00 +#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x8 +#define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x1000 +#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0xc +#define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x2000 +#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0xd +#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x4000 +#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0xe +#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x8000 +#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0xf +#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0xf0000 +#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x10 +#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x100000 +#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x14 +#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x200000 +#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x15 +#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0xf000000 +#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x18 +#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000 +#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x1c +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x1 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x0 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x2 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x1 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x4 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x2 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x8 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x3 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x10 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x4 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x20 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x5 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x40 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x6 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x80 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x7 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x100 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x8 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x200 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x9 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x400 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0xa +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x800 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0xb +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x1000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0xc +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x2000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0xd +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x4000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0xe +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x8000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0xf +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x10000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x10 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x20000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x11 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x40000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x12 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x80000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x13 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x100000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x14 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x200000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x15 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x400000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x16 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x1000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x18 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x2000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x19 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x4000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x1a +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x8000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x1b +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x1c +#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x1d +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x1e +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x1f +#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0xffff +#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x0 +#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000 +#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x10 +#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffff +#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x0 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x1 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x0 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x2 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x1 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x4 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x2 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x8 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x3 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x30 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x4 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x100 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x8 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x200 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x9 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x1 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x0 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x2 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x1 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x4 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x2 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x8 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x3 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x10 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x4 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x20 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x5 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x80 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc +#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x2000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0xd +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x4000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0xe +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x8000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0xf +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x20000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x11 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x40000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x12 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x80000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x13 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x100000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x14 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x200000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x400000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x800000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x17 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x1000000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x18 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x2000000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x19 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x4000000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x1a +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP_MASK 0x8000000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP__SHIFT 0x1b +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x1 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x0 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x2 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x1 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x4 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x2 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x8 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x3 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x10 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x4 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x20 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x5 +#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40 +#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6 +#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x80 +#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb +#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc +#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x2000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0xd +#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x4000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0xe +#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x8000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0xf +#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x20000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x11 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x40000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x12 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x80000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x13 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x100000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x14 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x200000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x15 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x400000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x16 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x800000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x17 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x1000000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x18 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x2000000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x19 +#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x4000000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x1a +#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP_MASK 0x8000000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP__SHIFT 0x1b +#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x1 +#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x0 +#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x2 +#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x1 +#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x4 +#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x2 +#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x8 +#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x3 +#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x10 +#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x4 +#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x20 +#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x5 +#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40 +#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6 +#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x80 +#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7 +#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100 +#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8 +#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200 +#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9 +#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400 +#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa +#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800 +#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb +#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000 +#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc +#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x2000 +#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0xd +#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x4000 +#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0xe +#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x8000 +#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0xf +#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x20000 +#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x11 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x40000 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x12 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x80000 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x13 +#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x100000 +#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x14 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x200000 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x400000 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16 +#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x800000 +#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x17 +#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x1000000 +#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x18 +#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x2000000 +#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x19 +#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x4000000 +#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x1a +#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP_MASK 0x8000000 +#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP__SHIFT 0x1b +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x1 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x0 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x2 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x1 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x4 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x2 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x8 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x3 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x10 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x4 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x20 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x5 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x80 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x2000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0xd +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x4000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0xe +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x8000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0xf +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x10000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x10 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x20000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x11 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x40000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x12 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x80000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x13 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x100000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x14 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x200000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x15 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x400000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x16 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x800000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x17 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x1000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x18 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x2000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x19 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x4000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x1a +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP_MASK 0x8000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP__SHIFT 0x1b +#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x1f +#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x0 +#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x3e0 +#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x5 +#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x7c00 +#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0xa +#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0xf8000 +#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0xf +#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0xff +#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x0 +#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0xff00 +#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x8 +#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0xff0000 +#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x10 +#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000 +#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x18 +#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0xff +#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x0 +#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0xff00 +#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x8 +#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0xff0000 +#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x10 +#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000 +#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x18 +#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffff +#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0xf +#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0xf0 +#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x4 +#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0xf00 +#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x8 +#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0xf000 +#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0xc +#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000 +#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x1c +#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000 +#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x1d +#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000 +#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x1e +#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x1 +#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x2 +#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x1 +#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x30 +#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x4 +#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x100 +#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x8 +#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x200 +#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x9 +#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x400 +#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0xa +#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x800 +#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0xb +#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x3ff0000 +#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x10 +#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000 +#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x1c +#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0xffff +#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x0 +#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000 +#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x10 +#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffff +#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0xf +#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0xf0 +#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x4 +#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0xf00 +#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x8 +#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0xf000 +#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0xc +#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000 +#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x1c +#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000 +#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x1d +#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000 +#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x1e +#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x1 +#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x2 +#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x1 +#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x30 +#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x4 +#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x100 +#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x8 +#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x200 +#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x9 +#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x400 +#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0xa +#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x800 +#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0xb +#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x3ff0000 +#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x10 +#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000 +#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x1c +#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0xffff +#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x0 +#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000 +#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x10 +#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x20 +#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0xf000 +#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0xc +#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0xf00000 +#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x2000000 +#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x19 +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x8000000 +#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x1b +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000 +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x1c +#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x20 +#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0xf000 +#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0xc +#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0xf00000 +#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x2000000 +#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x19 +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x8000000 +#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x1b +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000 +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x1c +#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x20 +#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x1000 +#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0xc +#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0xe000 +#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0xd +#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x700000 +#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x800000 +#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x17 +#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x2000000 +#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x19 +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000 +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x1b +#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000 +#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x1e +#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000 +#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x1f +#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x3 +#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x0 +#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x4 +#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x2 +#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x8 +#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x3 +#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x30 +#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x4 +#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x40 +#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x6 +#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x80 +#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x7 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0xf00 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x8 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0xf000 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0xc +#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x10000 +#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x10 +#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0xc0000 +#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x12 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x700000 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x14 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x7000000 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x18 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000 +#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x1d +#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x1e +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0xf +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x0 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0xf0 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x4 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0xff00 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x8 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x10000 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x10 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x20000 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x11 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x40000 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x12 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR_MASK 0x80000 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR__SHIFT 0x13 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN_MASK 0x100000 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN__SHIFT 0x14 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY_MASK 0x200000 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY__SHIFT 0x15 +#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN_MASK 0x400000 +#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN__SHIFT 0x16 +#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT_MASK 0x800000 +#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT__SHIFT 0x17 +#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0xe000000 +#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x19 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x3 +#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x0 +#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x4 +#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x2 +#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x8 +#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x3 +#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x30 +#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x4 +#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x40 +#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x6 +#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x80 +#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x7 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0xf00 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x8 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0xf000 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0xc +#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x10000 +#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x10 +#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0xc0000 +#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x12 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x700000 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x14 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x7000000 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x18 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000 +#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x1d +#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x1e +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0xf +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x0 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0xf0 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x4 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0xff00 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x8 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x10000 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x10 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x20000 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x11 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x40000 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x12 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR_MASK 0x80000 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR__SHIFT 0x13 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN_MASK 0x100000 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN__SHIFT 0x14 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY_MASK 0x200000 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY__SHIFT 0x15 +#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN_MASK 0x400000 +#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN__SHIFT 0x16 +#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT_MASK 0x800000 +#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT__SHIFT 0x17 +#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0xe000000 +#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x19 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x1c +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x3f +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x0 +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0xfc0 +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x6 +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x3f000 +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0xc +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0xfc0000 +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x12 +#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x1000000 +#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x18 +#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x2000000 +#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x19 +#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000 +#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000 +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x1c +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000 +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x1d +#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR_MASK 0x40000000 +#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR__SHIFT 0x1e +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x3f +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x0 +#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0xfc0 +#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x6 +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x3f000 +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0xc +#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x1000000 +#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x18 +#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x2000000 +#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x19 +#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000 +#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a +#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000 +#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x1c +#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000 +#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x1d +#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x20 +#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0xf000 +#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0xc +#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0xf00000 +#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x2000000 +#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x19 +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x8000000 +#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x1b +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000 +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x1c +#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x20 +#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0xf000 +#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0xc +#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0xf00000 +#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x2000000 +#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x19 +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x8000000 +#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x1b +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000 +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x1c +#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x20 +#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x1000 +#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0xc +#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0xe000 +#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0xd +#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x700000 +#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x800000 +#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x17 +#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x2000000 +#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x19 +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000 +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x1b +#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000 +#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x1e +#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000 +#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x1f +#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x3 +#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x0 +#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x4 +#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x2 +#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x8 +#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x3 +#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x30 +#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x4 +#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x40 +#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x6 +#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x80 +#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x7 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0xf00 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x8 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0xf000 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0xc +#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x10000 +#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x10 +#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0xc0000 +#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x12 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x700000 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x14 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x7000000 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x18 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000 +#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x1d +#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x1e +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0xf +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x0 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0xf0 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x4 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0xff00 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x8 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x10000 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x10 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x20000 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x11 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x40000 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x12 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR_MASK 0x80000 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR__SHIFT 0x13 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN_MASK 0x100000 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN__SHIFT 0x14 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY_MASK 0x200000 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY__SHIFT 0x15 +#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN_MASK 0x400000 +#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN__SHIFT 0x16 +#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT_MASK 0x800000 +#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT__SHIFT 0x17 +#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0xe000000 +#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x19 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x3 +#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x0 +#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x4 +#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x2 +#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x8 +#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x3 +#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x30 +#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x4 +#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x40 +#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x6 +#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x80 +#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x7 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0xf00 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x8 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0xf000 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0xc +#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x10000 +#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x10 +#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0xc0000 +#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x12 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x700000 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x14 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x7000000 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x18 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000 +#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x1d +#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x1e +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0xf +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x0 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0xf0 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x4 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0xff00 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x8 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x10000 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x10 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x20000 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x11 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x40000 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x12 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR_MASK 0x80000 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR__SHIFT 0x13 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN_MASK 0x100000 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN__SHIFT 0x14 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY_MASK 0x200000 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY__SHIFT 0x15 +#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN_MASK 0x400000 +#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN__SHIFT 0x16 +#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT_MASK 0x800000 +#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT__SHIFT 0x17 +#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0xe000000 +#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x19 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x1c +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x3f +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x0 +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0xfc0 +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x6 +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x3f000 +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0xc +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0xfc0000 +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x12 +#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x1000000 +#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x18 +#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x2000000 +#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x19 +#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000 +#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000 +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x1c +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000 +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x1d +#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR_MASK 0x40000000 +#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR__SHIFT 0x1e +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x3f +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x0 +#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0xfc0 +#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x6 +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x3f000 +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0xc +#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x1000000 +#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x18 +#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x2000000 +#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x19 +#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000 +#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a +#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000 +#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x1c +#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000 +#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x1d +#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0xf +#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x0 +#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0xf0 +#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x4 +#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x100 +#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x8 +#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x200 +#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x9 +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x400 +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0xa +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x800 +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0xb +#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0xf000 +#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0xc +#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0xf0000 +#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x10 +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x100000 +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x14 +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x200000 +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x15 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x400000 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x16 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x800000 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x17 +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x1000000 +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x18 +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x2000000 +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x19 +#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x4000000 +#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x1a +#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x8000000 +#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x1b +#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000 +#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x1c +#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000 +#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x1d +#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000 +#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x1e +#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000 +#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x1f +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0xff +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x0 +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0xff00 +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x8 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0xff0000 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x10 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x18 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x1 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x0 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x2 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x1 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x4 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x2 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x8 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x3 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x10 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x4 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x20 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x5 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x40 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x6 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x80 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x7 +#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON_MASK 0xf00 +#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON__SHIFT 0x8 +#define MC_IO_CDRCNTL2_D0__WCDRTXSEL_MASK 0xf000 +#define MC_IO_CDRCNTL2_D0__WCDRTXSEL__SHIFT 0xc +#define MC_IO_CDRCNTL2_D0__WCDRTRACK01_MASK 0xf0000 +#define MC_IO_CDRCNTL2_D0__WCDRTRACK01__SHIFT 0x10 +#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0xf +#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x0 +#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0xf0 +#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x4 +#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x100 +#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x8 +#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x200 +#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x9 +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x400 +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0xa +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x800 +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0xb +#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0xf000 +#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0xc +#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0xf0000 +#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x10 +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x100000 +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x14 +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x200000 +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x15 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x400000 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x16 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x800000 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x17 +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x1000000 +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x18 +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x2000000 +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x19 +#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x4000000 +#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x1a +#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x8000000 +#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x1b +#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000 +#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x1c +#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000 +#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x1d +#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000 +#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x1e +#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000 +#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x1f +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0xff +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x0 +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0xff00 +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x8 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0xff0000 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x10 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x18 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x1 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x0 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x2 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x1 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x4 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x2 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x8 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x3 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x10 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x4 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x20 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x5 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x40 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x6 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x80 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x7 +#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON_MASK 0xf00 +#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON__SHIFT 0x8 +#define MC_IO_CDRCNTL2_D1__WCDRTXSEL_MASK 0xf000 +#define MC_IO_CDRCNTL2_D1__WCDRTXSEL__SHIFT 0xc +#define MC_IO_CDRCNTL2_D1__WCDRTRACK01_MASK 0xf0000 +#define MC_IO_CDRCNTL2_D1__WCDRTRACK01__SHIFT 0x10 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x3 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x0 +#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0xc +#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x2 +#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x30 +#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x4 +#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0xc0 +#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x6 +#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x100 +#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x8 +#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x200 +#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x9 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0xc00 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0xa +#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x7000 +#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0xc +#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x30000 +#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x10 +#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0xc0000 +#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x12 +#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT_MASK 0xf00000 +#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT__SHIFT 0x14 +#define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 0xf000000 +#define MC_SEQ_FIFO_CTL__R_DQS_STEP__SHIFT 0x18 +#define MC_SEQ_FIFO_CTL__R_DQS_FRC_MASK 0x10000000 +#define MC_SEQ_FIFO_CTL__R_DQS_FRC__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0xf +#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0xf +#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0xf +#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0xf +#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0xf +#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0xf +#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0xf +#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0xf +#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0xf +#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0xf +#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0xff +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x0 +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0xff00 +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x8 +#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x10000 +#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x10 +#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x20000 +#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x11 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x40000 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x12 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x80000 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x13 +#define MC_IO_PAD_CNTL__ATBSEL_MASK 0xf00000 +#define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x14 +#define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000 +#define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x18 +#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000 +#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x1e +#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000 +#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x1f +#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x4 +#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x2 +#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x8 +#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x3 +#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x10 +#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x4 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x80 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x7 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x100 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x8 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x200 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x9 +#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x400 +#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0xa +#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x800 +#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0xb +#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x1000 +#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0xc +#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x2000 +#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0xd +#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x4000 +#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0xe +#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0xf8000 +#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0xf +#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x100000 +#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x14 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x200000 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x15 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0xc00000 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x16 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x3000000 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x18 +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x8000000 +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x1b +#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000 +#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x1c +#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000 +#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x1d +#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000 +#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x1e +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000 +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x1f +#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x1 +#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x0 +#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x2 +#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x1 +#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x4 +#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x2 +#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x8 +#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x3 +#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x10 +#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x4 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x20 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x5 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x40 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x6 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x80 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x7 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x100 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x8 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x200 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x9 +#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x400 +#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0xa +#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x800 +#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0xb +#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x1000 +#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0xc +#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x2000 +#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0xd +#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x4000 +#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0xe +#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0xf8000 +#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0xf +#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x100000 +#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x14 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x200000 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x15 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0xc00000 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x16 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x3000000 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x18 +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x8000000 +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x1b +#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000 +#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x1c +#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000 +#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x1d +#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000 +#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x1e +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000 +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x1f +#define MC_NPL_STATUS__D0_PDELAY_MASK 0x3 +#define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x0 +#define MC_NPL_STATUS__D0_NDELAY_MASK 0xc +#define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x2 +#define MC_NPL_STATUS__D0_PEARLY_MASK 0x10 +#define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x4 +#define MC_NPL_STATUS__D0_NEARLY_MASK 0x20 +#define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x5 +#define MC_NPL_STATUS__D1_PDELAY_MASK 0xc0 +#define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x6 +#define MC_NPL_STATUS__D1_NDELAY_MASK 0x300 +#define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x8 +#define MC_NPL_STATUS__D1_PEARLY_MASK 0x400 +#define MC_NPL_STATUS__D1_PEARLY__SHIFT 0xa +#define MC_NPL_STATUS__D1_NEARLY_MASK 0x800 +#define MC_NPL_STATUS__D1_NEARLY__SHIFT 0xb +#define MC_BIST_CMD_CNTL__RESET_MASK 0x1 +#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x0 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x2 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x1 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x4 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x2 +#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x8 +#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x3 +#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0xfff0 +#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x4 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x10000 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x10 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x20000 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x11 +#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0xffc0000 +#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x12 +#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000 +#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x1c +#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000 +#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x1d +#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000 +#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x1e +#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000 +#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x1f +#define MC_BIST_CNTL__RESET_MASK 0x1 +#define MC_BIST_CNTL__RESET__SHIFT 0x0 +#define MC_BIST_CNTL__RUN_MASK 0x2 +#define MC_BIST_CNTL__RUN__SHIFT 0x1 +#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x4 +#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x2 +#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x8 +#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x3 +#define MC_BIST_CNTL__MOP_MODE_MASK 0x10 +#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x4 +#define MC_BIST_CNTL__ADR_MODE_MASK 0x20 +#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x5 +#define MC_BIST_CNTL__DAT_MODE_MASK 0x40 +#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x6 +#define MC_BIST_CNTL__LOOP_MASK 0xc00 +#define MC_BIST_CNTL__LOOP__SHIFT 0xa +#define MC_BIST_CNTL__ENABLE_D0_MASK 0x1000 +#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0xc +#define MC_BIST_CNTL__ENABLE_D1_MASK 0x2000 +#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0xd +#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x4000 +#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0xe +#define MC_BIST_CNTL__LOOP_CNT_MASK 0xfff0000 +#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x10 +#define MC_BIST_CNTL__DONE_MASK 0x40000000 +#define MC_BIST_CNTL__DONE__SHIFT 0x1e +#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000 +#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x1f +#define MC_BIST_AUTO_CNTL__MOP_MASK 0x3 +#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x0 +#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0xf0 +#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x4 +#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0xffff00 +#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x8 +#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x1000000 +#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x18 +#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x2000000 +#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x19 +#define MC_BIST_DIR_CNTL__MOP_MASK 0x7 +#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x0 +#define MC_BIST_DIR_CNTL__EOB_MASK 0x8 +#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x3 +#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x10 +#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x4 +#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x20 +#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x5 +#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x40 +#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x6 +#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x80 +#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x7 +#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x100 +#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x8 +#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x200 +#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x9 +#define MC_BIST_DIR_CNTL__MOP3_MASK 0x400 +#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0xa +#define MC_BIST_SADDR__COL_MASK 0x3ff +#define MC_BIST_SADDR__COL__SHIFT 0x0 +#define MC_BIST_SADDR__ROW_MASK 0xfffc00 +#define MC_BIST_SADDR__ROW__SHIFT 0xa +#define MC_BIST_SADDR__BANK_MASK 0xf000000 +#define MC_BIST_SADDR__BANK__SHIFT 0x18 +#define MC_BIST_SADDR__RANK_MASK 0x10000000 +#define MC_BIST_SADDR__RANK__SHIFT 0x1c +#define MC_BIST_SADDR__COLH_MASK 0x20000000 +#define MC_BIST_SADDR__COLH__SHIFT 0x1d +#define MC_BIST_SADDR__ROWH_MASK 0xc0000000 +#define MC_BIST_SADDR__ROWH__SHIFT 0x1e +#define MC_BIST_EADDR__COL_MASK 0x3ff +#define MC_BIST_EADDR__COL__SHIFT 0x0 +#define MC_BIST_EADDR__ROW_MASK 0xfffc00 +#define MC_BIST_EADDR__ROW__SHIFT 0xa +#define MC_BIST_EADDR__BANK_MASK 0xf000000 +#define MC_BIST_EADDR__BANK__SHIFT 0x18 +#define MC_BIST_EADDR__RANK_MASK 0x10000000 +#define MC_BIST_EADDR__RANK__SHIFT 0x1c +#define MC_BIST_EADDR__COLH_MASK 0x20000000 +#define MC_BIST_EADDR__COLH__SHIFT 0x1d +#define MC_BIST_EADDR__ROWH_MASK 0xc0000000 +#define MC_BIST_EADDR__ROWH__SHIFT 0x1e +#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0xf +#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x0 +#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0xff0 +#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x4 +#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x1000 +#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0xc +#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x2000 +#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0xd +#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x4000 +#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0xe +#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x8000 +#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0xf +#define MC_BIST_CMP_CNTL__CMP_MASK 0x30000 +#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x10 +#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x40000 +#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x12 +#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x80000 +#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x13 +#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x300000 +#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x14 +#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000 +#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x16 +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x1f +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x0 +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x100 +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x8 +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x1f000 +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0xc +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x100000 +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x14 +#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x0 +#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffff +#define MC_BIST_DATA_MASK__MASK__SHIFT 0x0 +#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x3ff +#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x0 +#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0xfffc00 +#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0xa +#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0xf000000 +#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x18 +#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000 +#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x1c +#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000 +#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x1d +#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000 +#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x1e +#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffff +#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x0 +#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffff +#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x0 +#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffff +#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x0 +#define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000 +#define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x1e +#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x1 +#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x0 +#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x100 +#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x8 +#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x200 +#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x9 +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x400 +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0xa +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x800 +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0xb +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x1000 +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0xc +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x2000 +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0xd +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x4000 +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0xe +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x8000 +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0xf +#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0xf +#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0xf0 +#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x4 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0xf00 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x8 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0xf000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0xc +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0xf0000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x10 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0xf00000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x14 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0xf000000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x18 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x1c +#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x0 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x1 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x0 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x2 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x1 +#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x4 +#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x2 +#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x8 +#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x3 +#define MC_SEQ_STATUS_M__SLF_D0_MASK 0x10 +#define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x4 +#define MC_SEQ_STATUS_M__SLF_D1_MASK 0x20 +#define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x5 +#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x40 +#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x6 +#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x80 +#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x7 +#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x100 +#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x8 +#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x200 +#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x9 +#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x1000 +#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0xc +#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x2000 +#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0xd +#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x4000 +#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0xe +#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x8000 +#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0xf +#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x10000 +#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x10 +#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x1f00000 +#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x14 +#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x2000000 +#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x19 +#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x4000000 +#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x1a +#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP_MASK 0x8000000 +#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP__SHIFT 0x1b +#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP_MASK 0x10000000 +#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP__SHIFT 0x1c +#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x1 +#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x0 +#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x2 +#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x1 +#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x10 +#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x4 +#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x20 +#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x5 +#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x100 +#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x8 +#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x200 +#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x9 +#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff +#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0 +#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffff +#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x0 +#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffff +#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC0__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC0__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC1__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC1__VALUE__SHIFT 0x0 +#define MC_SEQ_RESERVE_0_S__MCLK_GCK_SEL_MASK 0x1 +#define MC_SEQ_RESERVE_0_S__MCLK_GCK_SEL__SHIFT 0x0 +#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xfffffffe +#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x1 +#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffff +#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x0 +#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffff +#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x0 +#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0xfff +#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x0 +#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0xfff000 +#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0xc +#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000 +#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x18 +#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0xfff +#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x0 +#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0xfff000 +#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0xc +#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000 +#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x18 +#define MC_SEQ_SUP_CNTL__RUN_MASK 0x1 +#define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x0 +#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x2 +#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x1 +#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x4 +#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x2 +#define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x8 +#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x3 +#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x10 +#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x4 +#define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x20 +#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x5 +#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x40 +#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x6 +#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x80 +#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x7 +#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000 +#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x17 +#define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffff +#define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x0 +#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffff +#define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x0 +#define MC_SEQ_MISC3__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC3__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC4__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC4__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC5__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC5__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC6__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC6__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC7__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC7__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC8__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC8__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC9__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC9__VALUE__SHIFT 0x0 +#define MC_SEQ_CG__CG_SEQ_REQ_MASK 0xff +#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x0 +#define MC_SEQ_CG__CG_SEQ_RESP_MASK 0xff00 +#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x8 +#define MC_SEQ_CG__SEQ_CG_REQ_MASK 0xff0000 +#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x10 +#define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000 +#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x18 +#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x3 +#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x0 +#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0xc +#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x2 +#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x30 +#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x4 +#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0xc0 +#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x6 +#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x3 +#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x0 +#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0xc +#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x2 +#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x30 +#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x4 +#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0xc0 +#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x15 +#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f +#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0 +#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0 +#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5 +#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00 +#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa +#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000 +#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf +#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000 +#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14 +#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000 +#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18 +#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3 +#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0 +#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc +#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2 +#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0 +#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4 +#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00 +#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9 +#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000 +#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc +#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000 +#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10 +#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000 +#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18 +#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f +#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0 +#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00 +#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8 +#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000 +#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf +#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000 +#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14 +#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x7 +#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x0 +#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x70 +#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x4 +#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x1f00 +#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x8 +#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0xe000 +#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0xd +#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x1f0000 +#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x10 +#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0xe00000 +#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x15 +#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0xf000000 +#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x18 +#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000 +#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x1c +#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x7 +#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x0 +#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0xf8 +#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x3 +#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x300 +#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x8 +#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0xc00 +#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0xa +#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0xf000 +#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0xc +#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x10000 +#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x10 +#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x20000 +#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x11 +#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x1f00000 +#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x14 +#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000 +#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x19 +#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x7 +#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x0 +#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0xf8 +#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x3 +#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x300 +#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x8 +#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0xc00 +#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0xa +#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0xf000 +#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0xc +#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x10000 +#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x10 +#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x20000 +#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x11 +#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x1f00000 +#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x14 +#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000 +#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x19 +#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0xf +#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x0 +#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0xf0 +#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x4 +#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x100 +#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x8 +#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x200 +#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x9 +#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x400 +#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0xa +#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x800 +#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0xb +#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0xf000 +#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0xc +#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0xf0000 +#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x10 +#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x300000 +#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x14 +#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0xf000000 +#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x18 +#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000 +#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x1c +#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000 +#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x1d +#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000 +#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x1e +#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0xf +#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x0 +#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0xf0 +#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x4 +#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x100 +#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x8 +#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x200 +#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x9 +#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x400 +#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0xa +#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x800 +#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0xb +#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0xf000 +#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0xc +#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0xf0000 +#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x10 +#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x300000 +#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x14 +#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0xf000000 +#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x18 +#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000 +#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x1c +#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000 +#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x1d +#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000 +#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x1e +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x1 +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x0 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x2 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x1 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x4 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x2 +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x8 +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x3 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x10 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x4 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x20 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x5 +#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x40 +#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x6 +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0xffff +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x70000 +#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x100000 +#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x14 +#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x600000 +#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000 +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x1c +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000 +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x1d +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0xffff +#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x70000 +#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x100000 +#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x14 +#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x600000 +#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000 +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x1c +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000 +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x1d +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0xffff +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x70000 +#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x100000 +#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x14 +#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x600000 +#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000 +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x1c +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000 +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x1d +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0xffff +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x70000 +#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x100000 +#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x14 +#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x600000 +#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000 +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x1c +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000 +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x1d +#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x7 +#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x0 +#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x70 +#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x4 +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0xf00 +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x8 +#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x3f000 +#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0xc +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x1c0000 +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x12 +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x800000 +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x17 +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000 +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x18 +#define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffff +#define MC_SEQ_IO_RDBI__MASK__SHIFT 0x0 +#define MC_SEQ_IO_REDC__EDC_MASK 0xffffffff +#define MC_SEQ_IO_REDC__EDC__SHIFT 0x0 +#define MC_SEQ_TCG_CNTL__RESET_MASK 0x1 +#define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x0 +#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x2 +#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x1 +#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x4 +#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x2 +#define MC_SEQ_TCG_CNTL__START_MASK 0x8 +#define MC_SEQ_TCG_CNTL__START__SHIFT 0x3 +#define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x70 +#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x4 +#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x80 +#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x7 +#define MC_SEQ_TCG_CNTL__MOP_MASK 0xf00 +#define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x8 +#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0xf000 +#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0xc +#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x10000 +#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x10 +#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x20000 +#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x11 +#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x40000 +#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x12 +#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x380000 +#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x13 +#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x400000 +#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x16 +#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x800000 +#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x17 +#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x1000000 +#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x18 +#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x2000000 +#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x19 +#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x4000000 +#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x1a +#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR_MASK 0x10000000 +#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR__SHIFT 0x1c +#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH_MASK 0x20000000 +#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH__SHIFT 0x1d +#define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000 +#define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x1f +#define MC_SEQ_TSM_CTRL__START_MASK 0x1 +#define MC_SEQ_TSM_CTRL__START__SHIFT 0x0 +#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x2 +#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x1 +#define MC_SEQ_TSM_CTRL__DONE_MASK 0x4 +#define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x2 +#define MC_SEQ_TSM_CTRL__ERR_MASK 0x8 +#define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x3 +#define MC_SEQ_TSM_CTRL__STEP_MASK 0x10 +#define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x4 +#define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x20 +#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x5 +#define MC_SEQ_TSM_CTRL__INVERT_MASK 0x40 +#define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x6 +#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x80 +#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x7 +#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x300 +#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x8 +#define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x400 +#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0xa +#define MC_SEQ_TSM_CTRL__DUAL_CH_EN_MASK 0x800 +#define MC_SEQ_TSM_CTRL__DUAL_CH_EN__SHIFT 0xb +#define MC_SEQ_TSM_CTRL__DONE0_MASK 0x1000 +#define MC_SEQ_TSM_CTRL__DONE0__SHIFT 0xc +#define MC_SEQ_TSM_CTRL__DONE1_MASK 0x2000 +#define MC_SEQ_TSM_CTRL__DONE1__SHIFT 0xd +#define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000 +#define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x10 +#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_GCNT__TESTS_MASK 0xff00 +#define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000 +#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x10 +#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_OCNT__TESTS_MASK 0xff00 +#define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000 +#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x10 +#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_NCNT__TESTS_MASK 0xff00 +#define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0xf0000 +#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x10 +#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0xf00000 +#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x14 +#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0xf000000 +#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x18 +#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0xff00 +#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0xff0000 +#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x10 +#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000 +#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x18 +#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0xff00 +#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0xf0000 +#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x10 +#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000 +#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x18 +#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0xff00 +#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0xff0000 +#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x10 +#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000 +#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x18 +#define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffff +#define MC_SEQ_TSM_EDC__EDC__SHIFT 0x0 +#define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffff +#define MC_SEQ_TSM_DBI__DBI__SHIFT 0x0 +#define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffff +#define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x0 +#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0xffff +#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x0 +#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0xf0000 +#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x10 +#define MC_SEQ_TSM_MISC__CH1_OFFSET_MASK 0x3f00000 +#define MC_SEQ_TSM_MISC__CH1_OFFSET__SHIFT 0x14 +#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET_MASK 0xfc000000 +#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET__SHIFT 0x1a +#define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffff +#define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x0 +#define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffff +#define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x0 +#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0xffff +#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x0 +#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000 +#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x10 +#define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0xf +#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x0 +#define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0xf0 +#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x4 +#define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0xf00 +#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x8 +#define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0xf000 +#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0xc +#define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x70000 +#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x10 +#define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0xf00000 +#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x14 +#define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x7000000 +#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x18 +#define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000 +#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x1c +#define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0xf +#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x0 +#define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0xf0 +#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x4 +#define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0xf00 +#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x8 +#define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0xf000 +#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0xc +#define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x70000 +#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x10 +#define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0xf00000 +#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x14 +#define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x7000000 +#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x18 +#define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000 +#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x1c +#define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x7f +#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x0 +#define MC_PHY_TIMING_2__RXC0_INV_MASK 0x100 +#define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x8 +#define MC_PHY_TIMING_2__RXC1_INV_MASK 0x200 +#define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x9 +#define MC_PHY_TIMING_2__TXC0_INV_MASK 0x400 +#define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0xa +#define MC_PHY_TIMING_2__TXC1_INV_MASK 0x800 +#define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0xb +#define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x1000 +#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0xc +#define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x2000 +#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0xd +#define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x4000 +#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0xe +#define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x8000 +#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0xf +#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x10000 +#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x10 +#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x20000 +#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x11 +#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x40000 +#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x12 +#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x80000 +#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x13 +#define MC_PHY_TIMING_2__WR_DLY_MASK 0xf00000 +#define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x14 +#define MC_PHY_TIMING_2__RXDPWRONC0_FRC_MASK 0x1000000 +#define MC_PHY_TIMING_2__RXDPWRONC0_FRC__SHIFT 0x18 +#define MC_PHY_TIMING_2__RXDPWRONC1_FRC_MASK 0x2000000 +#define MC_PHY_TIMING_2__RXDPWRONC1_FRC__SHIFT 0x19 +#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x1 +#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x0 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x2 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x1 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x4 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x2 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x8 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x3 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x10 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x4 +#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x20 +#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x5 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x40 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x6 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x80 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x7 +#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x1f +#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x0 +#define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x40 +#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x6 +#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x80 +#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x7 +#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x100 +#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x8 +#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x200 +#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x9 +#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x10000 +#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x10 +#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x20000 +#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x11 +#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x1000000 +#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x18 +#define DLL_CNTL__DLL_RESET_TIME_MASK 0x3ff +#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x0 +#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x3ff000 +#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0xc +#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x1000000 +#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x18 +#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x2000000 +#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x19 +#define DLL_CNTL__PWR2_MODE_MASK 0x4000000 +#define DLL_CNTL__PWR2_MODE__SHIFT 0x1a +#define MPLL_SEQ_UCODE_1__INSTR0_MASK 0xf +#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x0 +#define MPLL_SEQ_UCODE_1__INSTR1_MASK 0xf0 +#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x4 +#define MPLL_SEQ_UCODE_1__INSTR2_MASK 0xf00 +#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x8 +#define MPLL_SEQ_UCODE_1__INSTR3_MASK 0xf000 +#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0xc +#define MPLL_SEQ_UCODE_1__INSTR4_MASK 0xf0000 +#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x10 +#define MPLL_SEQ_UCODE_1__INSTR5_MASK 0xf00000 +#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x14 +#define MPLL_SEQ_UCODE_1__INSTR6_MASK 0xf000000 +#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x18 +#define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000 +#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x1c +#define MPLL_SEQ_UCODE_2__INSTR8_MASK 0xf +#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x0 +#define MPLL_SEQ_UCODE_2__INSTR9_MASK 0xf0 +#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x4 +#define MPLL_SEQ_UCODE_2__INSTR10_MASK 0xf00 +#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x8 +#define MPLL_SEQ_UCODE_2__INSTR11_MASK 0xf000 +#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0xc +#define MPLL_SEQ_UCODE_2__INSTR12_MASK 0xf0000 +#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x10 +#define MPLL_SEQ_UCODE_2__INSTR13_MASK 0xf00000 +#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x14 +#define MPLL_SEQ_UCODE_2__INSTR14_MASK 0xf000000 +#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x18 +#define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000 +#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x1c +#define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0xff +#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x0 +#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x100 +#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x8 +#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x800 +#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0xb +#define MPLL_CNTL_MODE__SPARE_1_MASK 0x1000 +#define MPLL_CNTL_MODE__SPARE_1__SHIFT 0xc +#define MPLL_CNTL_MODE__QDR_MASK 0x2000 +#define MPLL_CNTL_MODE__QDR__SHIFT 0xd +#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x4000 +#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0xe +#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x10000 +#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x10 +#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x20000 +#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x11 +#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x100000 +#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x14 +#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x600000 +#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x15 +#define MPLL_CNTL_MODE__SPARE_2_MASK 0x800000 +#define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x17 +#define MPLL_CNTL_MODE__SS_SSEN_MASK 0x3000000 +#define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x18 +#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x4000000 +#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x1a +#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x8000000 +#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x1b +#define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000 +#define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x1c +#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000 +#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x1f +#define MPLL_FUNC_CNTL__SPARE_0_MASK 0x20 +#define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x5 +#define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0xf00 +#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x8 +#define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0xf0000 +#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x10 +#define MPLL_FUNC_CNTL__BWCTRL_MASK 0xff00000 +#define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x14 +#define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000 +#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x1e +#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x3 +#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x0 +#define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0xc +#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x2 +#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0xfff0 +#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x4 +#define MPLL_FUNC_CNTL_1__CLKF_MASK 0xfff0000 +#define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x10 +#define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000 +#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x1c +#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x1 +#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x0 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x2 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x1 +#define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x4 +#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x2 +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x8 +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x3 +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x10 +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x4 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x20 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x5 +#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x40 +#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x6 +#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x80 +#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x7 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x100 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x8 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x200 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x9 +#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0xc00 +#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0xa +#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x3000 +#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0xc +#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN_MASK 0x4000 +#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN__SHIFT 0xe +#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR_MASK 0x8000 +#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR__SHIFT 0xf +#define MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK 0x10000 +#define MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT 0x10 +#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0xe0000 +#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x11 +#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x7f00000 +#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x14 +#define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000 +#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x1b +#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7 +#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0 +#define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8 +#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x3 +#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7 +#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0 +#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x8 +#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x3 +#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x10 +#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x4 +#define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0 +#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x5 +#define MPLL_TIME__MPLL_LOCK_TIME_MASK 0xffff +#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x0 +#define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000 +#define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x10 +#define MPLL_SS1__CLKV_MASK 0x3ffffff +#define MPLL_SS1__CLKV__SHIFT 0x0 +#define MPLL_SS1__SPARE_MASK 0xfc000000 +#define MPLL_SS1__SPARE__SHIFT 0x1a +#define MPLL_SS2__CLKS_MASK 0xfff +#define MPLL_SS2__CLKS__SHIFT 0x0 +#define MPLL_SS2__SPARE_MASK 0xfffff000 +#define MPLL_SS2__SPARE__SHIFT 0xc +#define MPLL_CONTROL__GDDR_PWRON_MASK 0x1 +#define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x0 +#define MPLL_CONTROL__REFCLK_PWRON_MASK 0x2 +#define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x1 +#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x4 +#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x2 +#define MPLL_CONTROL__AD_BG_PWRON_MASK 0x1000 +#define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0xc +#define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x2000 +#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0xd +#define MPLL_CONTROL__AD_PLL_RESET_MASK 0x4000 +#define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0xe +#define MPLL_CONTROL__SPARE_AD_0_MASK 0x8000 +#define MPLL_CONTROL__SPARE_AD_0__SHIFT 0xf +#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x10000 +#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x10 +#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x20000 +#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x11 +#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x40000 +#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x12 +#define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x80000 +#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x13 +#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x100000 +#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x14 +#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x200000 +#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x15 +#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x400000 +#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x16 +#define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x800000 +#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x17 +#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x1000000 +#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x18 +#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x2000000 +#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x19 +#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x4000000 +#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x1a +#define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x8000000 +#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x1b +#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000 +#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x1c +#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000 +#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x1d +#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000 +#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x1e +#define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000 +#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x1f +#define MPLL_AD_STATUS__VCTRLADC_MASK 0x7 +#define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x0 +#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x70 +#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4 +#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x1ff80 +#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x7 +#define MPLL_AD_STATUS__OINT_RESET_MASK 0x20000 +#define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x11 +#define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x40000 +#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x12 +#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000 +#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13 +#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x7 +#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x0 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7 +#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x20000 +#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x11 +#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x40000 +#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x12 +#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000 +#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13 +#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x7 +#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x0 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7 +#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x20000 +#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x11 +#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x40000 +#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x12 +#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000 +#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13 +#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x7 +#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x0 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7 +#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x20000 +#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x11 +#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x40000 +#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x12 +#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000 +#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13 +#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x7 +#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x0 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7 +#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x20000 +#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x11 +#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x40000 +#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x12 +#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000 +#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13 +#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x1 +#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x0 +#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x2 +#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x1 +#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x3c +#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x2 +#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0xc0 +#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x6 +#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x300 +#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x8 +#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x3c00 +#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0xa +#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x10000 +#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x10 +#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x20000 +#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x11 +#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x40000 +#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x12 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x1 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x0 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x2 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x1 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x4 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x2 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x8 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x3 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x10 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x4 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x20 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x5 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x40 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x6 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x80 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x7 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x100 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x8 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x200 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x9 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x400 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0xa +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x800 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0xb +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x1000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0xc +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x2000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0xd +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x4000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0xe +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x8000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0xf +#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x10000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x10 +#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000 +#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x1f +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x1 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x0 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x2 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x1 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x4 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x2 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x8 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x3 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x10 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x4 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x20 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x5 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x40 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x6 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x80 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x7 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x100 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x8 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x200 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x9 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x400 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0xa +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x800 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0xb +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x1000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0xc +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x2000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0xd +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x4000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0xe +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x8000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0xf +#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x10000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x10 +#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000 +#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x1f +#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x1f +#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x0 +#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffff +#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_MISC__FLAG_MASK 0xff +#define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x0 +#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0xf00 +#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x8 +#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0xf000 +#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0xc +#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x0 +#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x1ff +#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x0 +#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffff +#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x0 +#define MC_IO_DEBUG_UP_0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_2__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_2__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_2__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_3__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_3__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_3__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_4__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_4__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_4__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_5__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_5__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_5__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_6__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_6__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_6__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_7__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_7__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_7__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_8__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_8__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_8__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_9__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_9__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_9__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_10__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_10__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_10__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_11__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_11__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_11__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_12__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_12__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_12__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_13__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_13__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_13__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_14__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_14__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_14__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_15__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_15__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_15__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_16__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_16__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_16__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_17__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_17__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_17__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_18__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_18__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_18__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_19__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_19__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_19__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_20__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_20__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_20__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_21__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_21__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_21__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_22__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_22__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_22__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_23__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_23__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_23__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_24__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_24__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_24__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_25__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_25__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_25__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_26__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_26__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_26__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_27__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_27__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_27__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_28__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_28__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_28__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_29__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_29__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_29__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_30__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_30__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_30__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_31__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_31__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_31__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_32__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_32__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_32__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_33__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_33__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_33__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_34__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_34__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_34__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_35__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_35__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_35__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_36__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_36__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_36__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_37__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_37__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_37__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_38__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_38__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_38__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_39__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_39__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_39__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_40__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_40__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_40__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_41__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_41__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_41__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_42__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_42__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_42__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_43__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_43__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_43__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_44__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_44__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_44__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_45__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_45__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_45__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_46__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_46__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_46__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_47__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_47__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_47__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_48__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_48__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_48__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_49__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_49__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_49__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_50__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_50__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_50__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_51__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_51__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_51__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_52__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_52__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_52__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_53__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_53__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_53__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_54__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_54__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_54__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_55__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_55__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_55__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_56__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_56__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_56__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_57__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_57__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_57__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_58__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_58__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_58__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_59__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_59__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_59__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_60__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_60__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_60__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_61__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_61__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_61__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_62__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_62__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_62__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_63__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_63__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_63__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_64__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_64__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_64__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_65__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_65__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_65__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_66__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_66__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_66__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_67__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_67__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_67__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_68__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_68__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_68__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_69__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_69__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_69__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_70__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_70__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_70__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_71__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_71__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_71__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_72__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_72__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_72__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_73__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_73__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_73__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_74__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_74__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_74__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_75__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_75__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_75__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_76__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_76__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_76__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_77__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_77__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_77__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_78__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_78__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_78__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_79__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_79__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_79__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_80__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_80__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_80__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_81__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_81__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_81__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_82__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_82__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_82__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_83__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_83__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_83__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_84__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_84__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_84__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_85__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_85__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_85__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_86__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_86__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_86__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_87__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_87__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_87__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_88__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_88__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_88__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_89__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_89__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_89__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_90__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_90__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_90__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_91__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_91__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_91__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_92__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_92__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_92__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_93__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_93__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_93__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_94__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_94__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_94__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_95__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_95__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_95__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_96__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_96__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_96__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_97__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_97__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_97__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_98__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_98__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_98__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_99__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_99__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_99__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_100__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_100__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_100__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_101__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_101__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_101__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_102__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_102__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_102__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_103__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_103__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_103__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_104__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_104__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_104__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_105__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_105__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_105__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_106__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_106__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_106__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_107__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_107__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_107__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_108__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_108__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_108__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_109__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_109__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_109__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_110__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_110__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_110__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_111__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_111__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_111__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_112__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_112__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_112__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_113__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_113__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_113__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_114__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_114__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_114__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_115__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_115__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_115__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_116__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_116__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_116__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_117__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_117__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_117__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_118__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_118__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_118__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_119__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_119__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_119__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_120__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_120__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_120__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_121__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_121__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_121__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_122__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_122__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_122__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_123__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_123__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_123__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_124__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_124__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_124__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_125__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_125__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_125__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_126__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_126__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_126__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_127__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_127__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_127__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_128__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_128__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_128__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_129__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_129__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_129__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_130__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_130__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_130__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_131__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_131__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_131__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_132__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_132__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_132__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_133__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_133__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_133__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_134__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_134__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_134__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_135__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_135__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_135__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_136__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_136__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_136__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_137__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_137__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_137__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_138__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_138__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_138__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_139__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_139__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_139__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_140__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_140__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_140__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_141__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_141__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_141__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_142__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_142__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_142__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_143__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_143__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_143__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_144__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_144__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_144__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_145__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_145__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_145__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_146__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_146__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_146__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_147__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_147__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_147__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_148__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_148__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_148__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_149__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_149__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_149__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_150__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_150__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_150__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_151__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_151__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_151__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_152__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_152__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_152__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_153__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_153__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_153__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_154__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_154__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_154__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_155__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_155__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_155__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_156__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_156__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_156__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_157__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_157__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_157__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_158__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_158__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_158__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_159__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_159__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_159__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x18 +#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0_MASK 0x7 +#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0__SHIFT 0x0 +#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0_MASK 0x38 +#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0__SHIFT 0x3 +#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1_MASK 0x1c0 +#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1__SHIFT 0x6 +#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1_MASK 0xe00 +#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1__SHIFT 0x9 +#define MC_SEQ_CNTL_3__REPCG_EN_D0_MASK 0x1000 +#define MC_SEQ_CNTL_3__REPCG_EN_D0__SHIFT 0xc +#define MC_SEQ_CNTL_3__REPCG_EN_D1_MASK 0x2000 +#define MC_SEQ_CNTL_3__REPCG_EN_D1__SHIFT 0xd +#define MC_SEQ_CNTL_3__REPCG_OFF_DLY_MASK 0xf0000 +#define MC_SEQ_CNTL_3__REPCG_OFF_DLY__SHIFT 0x10 +#define MC_SEQ_CNTL_3__FCK_FRC_MASK 0x100000 +#define MC_SEQ_CNTL_3__FCK_FRC__SHIFT 0x14 +#define MC_SEQ_CNTL_3__DBI_FRC_MASK 0x200000 +#define MC_SEQ_CNTL_3__DBI_FRC__SHIFT 0x15 +#define MC_SEQ_CNTL_3__PRGRM_CDC_MASK 0x400000 +#define MC_SEQ_CNTL_3__PRGRM_CDC__SHIFT 0x16 +#define MC_SEQ_CNTL_3__DQS_FRC_MASK 0x800000 +#define MC_SEQ_CNTL_3__DQS_FRC__SHIFT 0x17 +#define MC_SEQ_CNTL_3__DQS_FRC_PAT_MASK 0xf000000 +#define MC_SEQ_CNTL_3__DQS_FRC_PAT__SHIFT 0x18 +#define MC_SEQ_CNTL_3__IDSC_EN_MASK 0x40000000 +#define MC_SEQ_CNTL_3__IDSC_EN__SHIFT 0x1e +#define MC_SEQ_CNTL_3__CAC_EN_MASK 0x80000000 +#define MC_SEQ_CNTL_3__CAC_EN__SHIFT 0x1f +#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 0x1 +#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE__SHIFT 0x0 +#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE_MASK 0x2 +#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE__SHIFT 0x1 +#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY_MASK 0x4 +#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY__SHIFT 0x2 +#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE_MASK 0x8 +#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE__SHIFT 0x3 +#define MC_SEQ_G5PDX_CTRL__TPD2MRS_MASK 0x3f0 +#define MC_SEQ_G5PDX_CTRL__TPD2MRS__SHIFT 0x4 +#define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 0xf000 +#define MC_SEQ_G5PDX_CTRL__TMRS2WCK__SHIFT 0xc +#define MC_SEQ_G5PDX_CTRL__TWCK2MRS_MASK 0xf0000 +#define MC_SEQ_G5PDX_CTRL__TWCK2MRS__SHIFT 0x10 +#define MC_SEQ_G5PDX_CTRL__TMRD_MASK 0xf00000 +#define MC_SEQ_G5PDX_CTRL__TMRD__SHIFT 0x14 +#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE_MASK 0x1 +#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE__SHIFT 0x0 +#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE_MASK 0x2 +#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE__SHIFT 0x1 +#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY_MASK 0x4 +#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY__SHIFT 0x2 +#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE_MASK 0x8 +#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE__SHIFT 0x3 +#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS_MASK 0x3f0 +#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS__SHIFT 0x4 +#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK_MASK 0xf000 +#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK__SHIFT 0xc +#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS_MASK 0xf0000 +#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS__SHIFT 0x10 +#define MC_SEQ_G5PDX_CTRL_LP__TMRD_MASK 0xf00000 +#define MC_SEQ_G5PDX_CTRL_LP__TMRD__SHIFT 0x14 +#define MC_SEQ_G5PDX_CMD0__CMD_MASK 0xffffffff +#define MC_SEQ_G5PDX_CMD0__CMD__SHIFT 0x0 +#define MC_SEQ_G5PDX_CMD0_LP__CMD_MASK 0xffffffff +#define MC_SEQ_G5PDX_CMD0_LP__CMD__SHIFT 0x0 +#define MC_SEQ_G5PDX_CMD1__CMD_MASK 0xffffffff +#define MC_SEQ_G5PDX_CMD1__CMD__SHIFT 0x0 +#define MC_SEQ_G5PDX_CMD1_LP__CMD_MASK 0xffffffff +#define MC_SEQ_G5PDX_CMD1_LP__CMD__SHIFT 0x0 +#define MC_SEQ_SREG_READ__DATA_MASK 0xffffffff +#define MC_SEQ_SREG_READ__DATA__SHIFT 0x0 +#define MC_SEQ_SREG_STATUS__AVAIL_RTN_MASK 0xf +#define MC_SEQ_SREG_STATUS__AVAIL_RTN__SHIFT 0x0 +#define MC_SEQ_SREG_STATUS__PND_RD_MASK 0xf00 +#define MC_SEQ_SREG_STATUS__PND_RD__SHIFT 0x8 +#define MC_SEQ_SREG_STATUS__PND_WR_MASK 0xf000 +#define MC_SEQ_SREG_STATUS__PND_WR__SHIFT 0xc +#define MC_SEQ_PHYREG_BCAST__CH0_EN_MASK 0x1 +#define MC_SEQ_PHYREG_BCAST__CH0_EN__SHIFT 0x0 +#define MC_SEQ_PHYREG_BCAST__CH1_EN_MASK 0x2 +#define MC_SEQ_PHYREG_BCAST__CH1_EN__SHIFT 0x1 +#define MC_SEQ_PHYREG_BCAST__CKE_MASK_MASK 0x80 +#define MC_SEQ_PHYREG_BCAST__CKE_MASK__SHIFT 0x7 +#define MC_SEQ_PHYREG_BCAST__DQ_MASK_MASK 0x100 +#define MC_SEQ_PHYREG_BCAST__DQ_MASK__SHIFT 0x8 +#define MC_SEQ_PHYREG_BCAST__DBI_MASK_MASK 0x200 +#define MC_SEQ_PHYREG_BCAST__DBI_MASK__SHIFT 0x9 +#define MC_SEQ_PHYREG_BCAST__EDC_MASK_MASK 0x400 +#define MC_SEQ_PHYREG_BCAST__EDC_MASK__SHIFT 0xa +#define MC_SEQ_PHYREG_BCAST__WCK_MASK_MASK 0x800 +#define MC_SEQ_PHYREG_BCAST__WCK_MASK__SHIFT 0xb +#define MC_SEQ_PHYREG_BCAST__WCDR_MASK_MASK 0x1000 +#define MC_SEQ_PHYREG_BCAST__WCDR_MASK__SHIFT 0xc +#define MC_SEQ_PHYREG_BCAST__CLK_MASK_MASK 0x2000 +#define MC_SEQ_PHYREG_BCAST__CLK_MASK__SHIFT 0xd +#define MC_SEQ_PHYREG_BCAST__CMD_MASK_MASK 0x4000 +#define MC_SEQ_PHYREG_BCAST__CMD_MASK__SHIFT 0xe +#define MC_SEQ_PHYREG_BCAST__ADR_MASK_MASK 0x8000 +#define MC_SEQ_PHYREG_BCAST__ADR_MASK__SHIFT 0xf +#define MC_SEQ_PMG_DVS_CTL__ENABLE_MASK 0x1 +#define MC_SEQ_PMG_DVS_CTL__ENABLE__SHIFT 0x0 +#define MC_SEQ_PMG_DVS_CTL__TDVS_MASK 0x3e +#define MC_SEQ_PMG_DVS_CTL__TDVS__SHIFT 0x1 +#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE_MASK 0x1 +#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE__SHIFT 0x0 +#define MC_SEQ_PMG_DVS_CTL_LP__TDVS_MASK 0x3e +#define MC_SEQ_PMG_DVS_CTL_LP__TDVS__SHIFT 0x1 +#define MC_SEQ_PMG_DVS_CMD__ADR_MASK 0xffff +#define MC_SEQ_PMG_DVS_CMD__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_DVS_CMD__MOP_MASK 0x70000 +#define MC_SEQ_PMG_DVS_CMD__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_DVS_CMD__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_DVS_CMD__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_DVS_CMD__END_MASK 0x100000 +#define MC_SEQ_PMG_DVS_CMD__END__SHIFT 0x14 +#define MC_SEQ_PMG_DVS_CMD__CSB_MASK 0x600000 +#define MC_SEQ_PMG_DVS_CMD__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1_MASK 0x800000 +#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1__SHIFT 0x17 +#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0_MASK 0x1000000 +#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0__SHIFT 0x18 +#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MASK 0xffff +#define MC_SEQ_PMG_DVS_CMD_LP__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_DVS_CMD_LP__MOP_MASK 0x70000 +#define MC_SEQ_PMG_DVS_CMD_LP__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_DVS_CMD_LP__END_MASK 0x100000 +#define MC_SEQ_PMG_DVS_CMD_LP__END__SHIFT 0x14 +#define MC_SEQ_PMG_DVS_CMD_LP__CSB_MASK 0x600000 +#define MC_SEQ_PMG_DVS_CMD_LP__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1_MASK 0x800000 +#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1__SHIFT 0x17 +#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0_MASK 0x1000000 +#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0__SHIFT 0x18 +#define MC_SEQ_DLL_STBY__EN_MASK 0x1 +#define MC_SEQ_DLL_STBY__EN__SHIFT 0x0 +#define MC_SEQ_DLL_STBY__VCTRLADC_FRC_MASK 0x2 +#define MC_SEQ_DLL_STBY__VCTRLADC_FRC__SHIFT 0x1 +#define MC_SEQ_DLL_STBY__VCTRLADC_VAL_MASK 0x4 +#define MC_SEQ_DLL_STBY__VCTRLADC_VAL__SHIFT 0x2 +#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC_MASK 0x8 +#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC__SHIFT 0x3 +#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL_MASK 0x10 +#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL__SHIFT 0x4 +#define MC_SEQ_DLL_STBY__ENTR_DLY_MASK 0xe0 +#define MC_SEQ_DLL_STBY__ENTR_DLY__SHIFT 0x5 +#define MC_SEQ_DLL_STBY__STBY_DLY_MASK 0xf00 +#define MC_SEQ_DLL_STBY__STBY_DLY__SHIFT 0x8 +#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN_MASK 0xf000 +#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN__SHIFT 0xc +#define MC_SEQ_DLL_STBY__TCKE_EXTN_MASK 0xff0000 +#define MC_SEQ_DLL_STBY__TCKE_EXTN__SHIFT 0x10 +#define MC_SEQ_DLL_STBY__EXIT_DLY_MASK 0x3f000000 +#define MC_SEQ_DLL_STBY__EXIT_DLY__SHIFT 0x18 +#define MC_SEQ_DLL_STBY_LP__EN_MASK 0x1 +#define MC_SEQ_DLL_STBY_LP__EN__SHIFT 0x0 +#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC_MASK 0x2 +#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC__SHIFT 0x1 +#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL_MASK 0x4 +#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL__SHIFT 0x2 +#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC_MASK 0x8 +#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC__SHIFT 0x3 +#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL_MASK 0x10 +#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL__SHIFT 0x4 +#define MC_SEQ_DLL_STBY_LP__ENTR_DLY_MASK 0xe0 +#define MC_SEQ_DLL_STBY_LP__ENTR_DLY__SHIFT 0x5 +#define MC_SEQ_DLL_STBY_LP__STBY_DLY_MASK 0xf00 +#define MC_SEQ_DLL_STBY_LP__STBY_DLY__SHIFT 0x8 +#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN_MASK 0xf000 +#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN__SHIFT 0xc +#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN_MASK 0xff0000 +#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN__SHIFT 0x10 +#define MC_SEQ_DLL_STBY_LP__EXIT_DLY_MASK 0x3f000000 +#define MC_SEQ_DLL_STBY_LP__EXIT_DLY__SHIFT 0x18 +#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS_MASK 0x1 +#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS__SHIFT 0x0 +#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL_MASK 0x2 +#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL__SHIFT 0x1 +#define MC_DLB_MISCCTRL0__LOAD_UDD_MASK 0x4 +#define MC_DLB_MISCCTRL0__LOAD_UDD__SHIFT 0x2 +#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL_MASK 0x8 +#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL__SHIFT 0x3 +#define MC_DLB_MISCCTRL0__DATA_SEL_MASK 0xf0 +#define MC_DLB_MISCCTRL0__DATA_SEL__SHIFT 0x4 +#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT_MASK 0x7f00 +#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT__SHIFT 0x8 +#define MC_DLB_MISCCTRL0__UDD_MASK 0xffff0000 +#define MC_DLB_MISCCTRL0__UDD__SHIFT 0x10 +#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT_MASK 0xffffffff +#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT__SHIFT 0x0 +#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH_MASK 0x1ffff +#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH__SHIFT 0x0 +#define MC_DLB_MISCCTRL2__PRBS_FREERUN_MASK 0x20000 +#define MC_DLB_MISCCTRL2__PRBS_FREERUN__SHIFT 0x11 +#define MC_DLB_MISCCTRL2__PRBS15_MODE_MASK 0x40000 +#define MC_DLB_MISCCTRL2__PRBS15_MODE__SHIFT 0x12 +#define MC_DLB_MISCCTRL2__PRBS23_MODE_MASK 0x80000 +#define MC_DLB_MISCCTRL2__PRBS23_MODE__SHIFT 0x13 +#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR_MASK 0x100000 +#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR__SHIFT 0x14 +#define MC_DLB_MISCCTRL2__STOP_CLK_MASK 0x200000 +#define MC_DLB_MISCCTRL2__STOP_CLK__SHIFT 0x15 +#define MC_DLB_MISCCTRL2__SWEEP_DLY_MASK 0x3000000 +#define MC_DLB_MISCCTRL2__SWEEP_DLY__SHIFT 0x18 +#define MC_DLB_MISCCTRL2__GRAY_CODE_EN_MASK 0x4000000 +#define MC_DLB_MISCCTRL2__GRAY_CODE_EN__SHIFT 0x1a +#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK_MASK 0x10000000 +#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK__SHIFT 0x1c +#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK_MASK 0x20000000 +#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK__SHIFT 0x1d +#define MC_DLB_MISCCTRL2__STATUS_SEL_MASK 0x40000000 +#define MC_DLB_MISCCTRL2__STATUS_SEL__SHIFT 0x1e +#define MC_DLB_CONFIG0__CONF_EN_CH0_MASK 0x1 +#define MC_DLB_CONFIG0__CONF_EN_CH0__SHIFT 0x0 +#define MC_DLB_CONFIG0__CONF_EN_CH1_MASK 0x2 +#define MC_DLB_CONFIG0__CONF_EN_CH1__SHIFT 0x1 +#define MC_DLB_CONFIG0__CONF_AUTO_EN_MASK 0x4 +#define MC_DLB_CONFIG0__CONF_AUTO_EN__SHIFT 0x2 +#define MC_DLB_CONFIG0__MASK_MASK 0xf0 +#define MC_DLB_CONFIG0__MASK__SHIFT 0x4 +#define MC_DLB_CONFIG0__PTR_MASK 0x3ff00 +#define MC_DLB_CONFIG0__PTR__SHIFT 0x8 +#define MC_DLB_CONFIG1__DATA_MASK 0xffffffff +#define MC_DLB_CONFIG1__DATA__SHIFT 0x0 +#define MC_DLB_SETUP__DLB_EN_MASK 0x1 +#define MC_DLB_SETUP__DLB_EN__SHIFT 0x0 +#define MC_DLB_SETUP__DLB_FIFO_EN_MASK 0x2 +#define MC_DLB_SETUP__DLB_FIFO_EN__SHIFT 0x1 +#define MC_DLB_SETUP__DLB_STATUS_EN_MASK 0x4 +#define MC_DLB_SETUP__DLB_STATUS_EN__SHIFT 0x2 +#define MC_DLB_SETUP__DLB_CONFIG_EN_MASK 0x8 +#define MC_DLB_SETUP__DLB_CONFIG_EN__SHIFT 0x3 +#define MC_DLB_SETUP__DLB_PRBS_EN_MASK 0x10 +#define MC_DLB_SETUP__DLB_PRBS_EN__SHIFT 0x4 +#define MC_DLB_SETUP__PRBS_GEN_RST_MASK 0x20 +#define MC_DLB_SETUP__PRBS_GEN_RST__SHIFT 0x5 +#define MC_DLB_SETUP__PRBS_CHK_RST_MASK 0x40 +#define MC_DLB_SETUP__PRBS_CHK_RST__SHIFT 0x6 +#define MC_DLB_SETUP__PRBS_PHY_RST_MASK 0x80 +#define MC_DLB_SETUP__PRBS_PHY_RST__SHIFT 0x7 +#define MC_DLB_SETUP__QDR_MODE_MASK 0x100 +#define MC_DLB_SETUP__QDR_MODE__SHIFT 0x8 +#define MC_DLB_SETUP__CHK_DATA_BITS_MASK 0xff0000 +#define MC_DLB_SETUP__CHK_DATA_BITS__SHIFT 0x10 +#define MC_DLB_SETUP__MEM_BIT_SEL_MASK 0x1f000000 +#define MC_DLB_SETUP__MEM_BIT_SEL__SHIFT 0x18 +#define MC_DLB_SETUP__RXTXLP_EN_MASK 0x80000000 +#define MC_DLB_SETUP__RXTXLP_EN__SHIFT 0x1f +#define MC_DLB_SETUPSWEEP__DLL_RST_MASK 0x1 +#define MC_DLB_SETUPSWEEP__DLL_RST__SHIFT 0x0 +#define MC_DLB_SETUPSWEEP__CONFIG_MASK 0x2 +#define MC_DLB_SETUPSWEEP__CONFIG__SHIFT 0x1 +#define MC_DLB_SETUPSWEEP__MASTER_MASK 0x4 +#define MC_DLB_SETUPSWEEP__MASTER__SHIFT 0x2 +#define MC_DLB_SETUPSWEEP__DLLDLY_MASK 0xf0 +#define MC_DLB_SETUPSWEEP__DLLDLY__SHIFT 0x4 +#define MC_DLB_SETUPSWEEP__DLLSTEPS_MASK 0x1f00 +#define MC_DLB_SETUPSWEEP__DLLSTEPS__SHIFT 0x8 +#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST_MASK 0x1 +#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST__SHIFT 0x0 +#define MC_DLB_SETUPFIFO__READ_FIFO_RST_MASK 0x2 +#define MC_DLB_SETUPFIFO__READ_FIFO_RST__SHIFT 0x1 +#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST_MASK 0x4 +#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST__SHIFT 0x2 +#define MC_DLB_SETUPFIFO__SYNC_RST_MASK 0x8 +#define MC_DLB_SETUPFIFO__SYNC_RST__SHIFT 0x3 +#define MC_DLB_SETUPFIFO__SYNC_RST_MASK_MASK 0x30 +#define MC_DLB_SETUPFIFO__SYNC_RST_MASK__SHIFT 0x4 +#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST_MASK 0x40 +#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST__SHIFT 0x6 +#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR_MASK 0x300 +#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR__SHIFT 0x8 +#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR_MASK 0x1c00 +#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR__SHIFT 0xa +#define MC_DLB_SETUPFIFO__STROBE_MASK 0xf0000 +#define MC_DLB_SETUPFIFO__STROBE__SHIFT 0x10 +#define MC_DLB_WRITE_MASK__BIT_MASK_MASK 0x3fffff +#define MC_DLB_WRITE_MASK__BIT_MASK__SHIFT 0x0 +#define MC_DLB_WRITE_MASK__CH_MASK_MASK 0xf000000 +#define MC_DLB_WRITE_MASK__CH_MASK__SHIFT 0x18 +#define MC_DLB_STATUS__STICK_ERROR_MASK 0xf +#define MC_DLB_STATUS__STICK_ERROR__SHIFT 0x0 +#define MC_DLB_STATUS__LOCK_MASK 0xf0 +#define MC_DLB_STATUS__LOCK__SHIFT 0x4 +#define MC_DLB_STATUS__SWEEP_DONE_MASK 0xf00 +#define MC_DLB_STATUS__SWEEP_DONE__SHIFT 0x8 +#define MC_DLB_STATUS_MISC0__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC0__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC1__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC1__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC2__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC2__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC3__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC3__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC4__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC4__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC5__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC5__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC6__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC6__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC7__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC7__DATA__SHIFT 0x0 +#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff +#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0 +#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00 +#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8 +#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000 +#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10 +#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000 +#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18 +#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff +#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0 +#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00 +#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8 +#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000 +#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10 +#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000 +#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff +#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0 +#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100 +#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8 +#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200 +#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9 +#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400 +#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa +#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800 +#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb +#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000 +#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc +#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000 +#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe +#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000 +#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16 +#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff +#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0 +#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100 +#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8 +#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200 +#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9 +#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400 +#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa +#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800 +#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb +#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000 +#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc +#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000 +#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe +#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000 +#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16 + +#endif /* GMC_7_1_SH_MASK_H */ -- cgit v1.2.3 From bd6a6b43fdfe1755c16ffa787df3b22883617b70 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:24:04 -0400 Subject: drm/amdgpu: add GMC 8.1 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h | 1708 ++ .../drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h | 1198 ++ .../drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h | 15682 +++++++++++++++++++ 3 files changed, 18588 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h new file mode 100644 index 000000000000..8c2412e6681e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h @@ -0,0 +1,1708 @@ +/* + * GMC_8_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_8_1_D_H +#define GMC_8_1_D_H + +#define mmMC_CONFIG 0x800 +#define mmMC_ARB_ATOMIC 0x9be +#define mmMC_ARB_AGE_CNTL 0x9bf +#define mmMC_ARB_RET_CREDITS2 0x9c0 +#define mmMC_ARB_FED_CNTL 0x9c1 +#define mmMC_ARB_GECC2_STATUS 0x9c2 +#define mmMC_ARB_GECC2_MISC 0x9c3 +#define mmMC_ARB_GECC2_DEBUG 0x9c4 +#define mmMC_ARB_GECC2_DEBUG2 0x9c5 +#define mmMC_ARB_PERF_CID 0x9c6 +#define mmMC_ARB_SNOOP 0x9c7 +#define mmMC_ARB_GRUB 0x9c8 +#define mmMC_ARB_GECC2 0x9c9 +#define mmMC_ARB_GECC2_CLI 0x9ca +#define mmMC_ARB_ADDR_SWIZ0 0x9cb +#define mmMC_ARB_ADDR_SWIZ1 0x9cc +#define mmMC_ARB_MISC3 0x9cd +#define mmMC_ARB_GRUB_PROMOTE 0x9ce +#define mmMC_ARB_RTT_DATA 0x9cf +#define mmMC_ARB_RTT_CNTL0 0x9d0 +#define mmMC_ARB_RTT_CNTL1 0x9d1 +#define mmMC_ARB_RTT_CNTL2 0x9d2 +#define mmMC_ARB_RTT_DEBUG 0x9d3 +#define mmMC_ARB_CAC_CNTL 0x9d4 +#define mmMC_ARB_MISC2 0x9d5 +#define mmMC_ARB_MISC 0x9d6 +#define mmMC_ARB_BANKMAP 0x9d7 +#define mmMC_ARB_RAMCFG 0x9d8 +#define mmMC_ARB_POP 0x9d9 +#define mmMC_ARB_MINCLKS 0x9da +#define mmMC_ARB_SQM_CNTL 0x9db +#define mmMC_ARB_ADDR_HASH 0x9dc +#define mmMC_ARB_DRAM_TIMING 0x9dd +#define mmMC_ARB_DRAM_TIMING2 0x9de +#define mmMC_ARB_WTM_CNTL_RD 0x9df +#define mmMC_ARB_WTM_CNTL_WR 0x9e0 +#define mmMC_ARB_WTM_GRPWT_RD 0x9e1 +#define mmMC_ARB_WTM_GRPWT_WR 0x9e2 +#define mmMC_ARB_TM_CNTL_RD 0x9e3 +#define mmMC_ARB_TM_CNTL_WR 0x9e4 +#define mmMC_ARB_LAZY0_RD 0x9e5 +#define mmMC_ARB_LAZY0_WR 0x9e6 +#define mmMC_ARB_LAZY1_RD 0x9e7 +#define mmMC_ARB_LAZY1_WR 0x9e8 +#define mmMC_ARB_AGE_RD 0x9e9 +#define mmMC_ARB_AGE_WR 0x9ea +#define mmMC_ARB_RFSH_CNTL 0x9eb +#define mmMC_ARB_RFSH_RATE 0x9ec +#define mmMC_ARB_PM_CNTL 0x9ed +#define mmMC_ARB_GDEC_RD_CNTL 0x9ee +#define mmMC_ARB_GDEC_WR_CNTL 0x9ef +#define mmMC_ARB_LM_RD 0x9f0 +#define mmMC_ARB_LM_WR 0x9f1 +#define mmMC_ARB_REMREQ 0x9f2 +#define mmMC_ARB_REPLAY 0x9f3 +#define mmMC_ARB_RET_CREDITS_RD 0x9f4 +#define mmMC_ARB_RET_CREDITS_WR 0x9f5 +#define mmMC_ARB_MAX_LAT_CID 0x9f6 +#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7 +#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8 +#define mmMC_ARB_GRUB_REALTIME_RD 0x9f9 +#define mmMC_ARB_CG 0x9fa +#define mmMC_ARB_GRUB_REALTIME_WR 0x9fb +#define mmMC_ARB_DRAM_TIMING_1 0x9fc +#define mmMC_ARB_BUSY_STATUS 0x9fd +#define mmMC_ARB_DRAM_TIMING2_1 0x9ff +#define mmMC_ARB_GRUB2 0xa01 +#define mmMC_ARB_BURST_TIME 0xa02 +#define mmMC_CITF_XTRA_ENABLE 0x96d +#define mmCC_MC_MAX_CHANNEL 0x96e +#define mmMC_CG_CONFIG 0x96f +#define mmMC_CITF_CNTL 0x970 +#define mmMC_CITF_CREDITS_VM 0x971 +#define mmMC_CITF_CREDITS_ARB_RD 0x972 +#define mmMC_CITF_CREDITS_ARB_WR 0x973 +#define mmMC_CITF_DAGB_CNTL 0x974 +#define mmMC_CITF_INT_CREDITS 0x975 +#define mmMC_CITF_RET_MODE 0x976 +#define mmMC_CITF_DAGB_DLY 0x977 +#define mmMC_RD_GRP_EXT 0x978 +#define mmMC_WR_GRP_EXT 0x979 +#define mmMC_CITF_REMREQ 0x97a +#define mmMC_WR_TC0 0x97b +#define mmMC_WR_TC1 0x97c +#define mmMC_CITF_INT_CREDITS_WR 0x97d +#define mmMC_CITF_CREDITS_ARB_RD2 0x97e +#define mmMC_CITF_WTM_RD_CNTL 0x97f +#define mmMC_CITF_WTM_WR_CNTL 0x980 +#define mmMC_RD_CB 0x981 +#define mmMC_RD_DB 0x982 +#define mmMC_RD_TC0 0x983 +#define mmMC_RD_TC1 0x984 +#define mmMC_RD_HUB 0x985 +#define mmMC_WR_CB 0x986 +#define mmMC_WR_DB 0x987 +#define mmMC_WR_HUB 0x988 +#define mmMC_CITF_CREDITS_XBAR 0x989 +#define mmMC_RD_GRP_LCL 0x98a +#define mmMC_WR_GRP_LCL 0x98b +#define mmMC_CITF_PERF_MON_CNTL2 0x98e +#define mmMC_CITF_PERF_MON_RSLT2 0x991 +#define mmMC_CITF_MISC_RD_CG 0x992 +#define mmMC_CITF_MISC_WR_CG 0x993 +#define mmMC_CITF_MISC_VM_CG 0x994 +#define mmMC_HUB_MISC_POWER 0x82d +#define mmMC_HUB_MISC_HUB_CG 0x82e +#define mmMC_HUB_MISC_VM_CG 0x82f +#define mmMC_HUB_MISC_SIP_CG 0x830 +#define mmMC_HUB_MISC_STATUS 0x832 +#define mmMC_HUB_MISC_OVERRIDE 0x833 +#define mmMC_HUB_MISC_FRAMING 0x834 +#define mmMC_HUB_WDP_CNTL 0x835 +#define mmMC_HUB_WDP_ERR 0x836 +#define mmMC_HUB_WDP_BP 0x837 +#define mmMC_HUB_WDP_STATUS 0x838 +#define mmMC_HUB_RDREQ_STATUS 0x839 +#define mmMC_HUB_WRRET_STATUS 0x83a +#define mmMC_HUB_RDREQ_CNTL 0x83b +#define mmMC_HUB_WRRET_CNTL 0x83c +#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d +#define mmMC_HUB_WDP_WTM_CNTL 0x83e +#define mmMC_HUB_WDP_CREDITS 0x83f +#define mmMC_HUB_WDP_CREDITS2 0x840 +#define mmMC_HUB_WDP_GBL0 0x841 +#define mmMC_HUB_WDP_GBL1 0x842 +#define mmMC_HUB_WDP_CREDITS3 0x843 +#define mmMC_HUB_RDREQ_CREDITS 0x844 +#define mmMC_HUB_RDREQ_CREDITS2 0x845 +#define mmMC_HUB_SHARED_DAGB_DLY 0x846 +#define mmMC_HUB_MISC_IDLE_STATUS 0x847 +#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848 +#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849 +#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a +#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b +#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c +#define mmMC_HUB_WDP_SH2 0x84d +#define mmMC_HUB_WDP_SH3 0x84e +#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS 0x84f +#define mmMC_HUB_WDP_VIN0 0x850 +#define mmMC_HUB_RDREQ_MCDW 0x851 +#define mmMC_HUB_RDREQ_MCDX 0x852 +#define mmMC_HUB_RDREQ_MCDY 0x853 +#define mmMC_HUB_RDREQ_MCDZ 0x854 +#define mmMC_HUB_RDREQ_SIP 0x855 +#define mmMC_HUB_RDREQ_GBL0 0x856 +#define mmMC_HUB_RDREQ_GBL1 0x857 +#define mmMC_HUB_RDREQ_SMU 0x858 +#define mmMC_HUB_RDREQ_SDMA0 0x859 +#define mmMC_HUB_RDREQ_HDP 0x85a +#define mmMC_HUB_RDREQ_SDMA1 0x85b +#define mmMC_HUB_RDREQ_RLC 0x85c +#define mmMC_HUB_RDREQ_SEM 0x85d +#define mmMC_HUB_RDREQ_VCE0 0x85e +#define mmMC_HUB_RDREQ_UMC 0x85f +#define mmMC_HUB_RDREQ_UVD 0x860 +#define mmMC_HUB_RDREQ_TLS 0x861 +#define mmMC_HUB_RDREQ_DMIF 0x862 +#define mmMC_HUB_RDREQ_MCIF 0x863 +#define mmMC_HUB_RDREQ_VMC 0x864 +#define mmMC_HUB_RDREQ_VCEU0 0x865 +#define mmMC_HUB_WDP_MCDW 0x866 +#define mmMC_HUB_WDP_MCDX 0x867 +#define mmMC_HUB_WDP_MCDY 0x868 +#define mmMC_HUB_WDP_MCDZ 0x869 +#define mmMC_HUB_WDP_SIP 0x86a +#define mmMC_HUB_WDP_SDMA1 0x86b +#define mmMC_HUB_WDP_SH0 0x86c +#define mmMC_HUB_WDP_MCIF 0x86d +#define mmMC_HUB_WDP_VCE0 0x86e +#define mmMC_HUB_WDP_XDP 0x86f +#define mmMC_HUB_WDP_IH 0x870 +#define mmMC_HUB_WDP_RLC 0x871 +#define mmMC_HUB_WDP_SEM 0x872 +#define mmMC_HUB_WDP_SMU 0x873 +#define mmMC_HUB_WDP_SH1 0x874 +#define mmMC_HUB_WDP_UMC 0x875 +#define mmMC_HUB_WDP_UVD 0x876 +#define mmMC_HUB_WDP_HDP 0x877 +#define mmMC_HUB_WDP_SDMA0 0x878 +#define mmMC_HUB_WRRET_MCDW 0x879 +#define mmMC_HUB_WRRET_MCDX 0x87a +#define mmMC_HUB_WRRET_MCDY 0x87b +#define mmMC_HUB_WRRET_MCDZ 0x87c +#define mmMC_HUB_WDP_VCEU0 0x87d +#define mmMC_HUB_WDP_XDMAM 0x87e +#define mmMC_HUB_WDP_XDMA 0x87f +#define mmMC_HUB_RDREQ_XDMAM 0x880 +#define mmMC_HUB_RDREQ_ACPG 0x881 +#define mmMC_HUB_RDREQ_ACPO 0x882 +#define mmMC_HUB_RDREQ_SAMMSP 0x883 +#define mmMC_HUB_RDREQ_VP8 0x884 +#define mmMC_HUB_RDREQ_VP8U 0x885 +#define mmMC_HUB_WDP_ACPG 0x886 +#define mmMC_HUB_WDP_ACPO 0x887 +#define mmMC_HUB_WDP_SAMMSP 0x888 +#define mmMC_HUB_WDP_VP8 0x889 +#define mmMC_HUB_WDP_VP8U 0x88a +#define mmMC_HUB_RDREQ_ISP_SPM 0xde0 +#define mmMC_HUB_RDREQ_ISP_MPM 0xde1 +#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2 +#define mmMC_HUB_WDP_ISP_SPM 0xde3 +#define mmMC_HUB_WDP_ISP_MPS 0xde4 +#define mmMC_HUB_WDP_ISP_MPM 0xde5 +#define mmMC_HUB_WDP_ISP_CCPU 0xde6 +#define mmMC_HUB_RDREQ_MCDS 0xde7 +#define mmMC_HUB_RDREQ_MCDT 0xde8 +#define mmMC_HUB_RDREQ_MCDU 0xde9 +#define mmMC_HUB_RDREQ_MCDV 0xdea +#define mmMC_HUB_WDP_MCDS 0xdeb +#define mmMC_HUB_WDP_MCDT 0xdec +#define mmMC_HUB_WDP_MCDU 0xded +#define mmMC_HUB_WDP_MCDV 0xdee +#define mmMC_HUB_WRRET_MCDS 0xdef +#define mmMC_HUB_WRRET_MCDT 0xdf0 +#define mmMC_HUB_WRRET_MCDU 0xdf1 +#define mmMC_HUB_WRRET_MCDV 0xdf2 +#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3 +#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4 +#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5 +#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6 +#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7 +#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8 +#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9 +#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa +#define mmMC_HUB_WDP_BP2 0xdfb +#define mmMC_HUB_RDREQ_VCE1 0xdfc +#define mmMC_HUB_RDREQ_VCEU1 0xdfd +#define mmMC_HUB_WDP_VCE1 0xdfe +#define mmMC_HUB_WDP_VCEU1 0xdff +#define mmMC_RPB_CONF 0x94d +#define mmMC_RPB_IF_CONF 0x94e +#define mmMC_RPB_DBG1 0x94f +#define mmMC_RPB_EFF_CNTL 0x950 +#define mmMC_RPB_ARB_CNTL 0x951 +#define mmMC_RPB_BIF_CNTL 0x952 +#define mmMC_RPB_WR_SWITCH_CNTL 0x953 +#define mmMC_RPB_WR_COMBINE_CNTL 0x954 +#define mmMC_RPB_RD_SWITCH_CNTL 0x955 +#define mmMC_RPB_CID_QUEUE_WR 0x956 +#define mmMC_RPB_CID_QUEUE_RD 0x957 +#define mmMC_RPB_PERF_COUNTER_CNTL 0x958 +#define mmMC_RPB_PERF_COUNTER_STATUS 0x959 +#define mmMC_RPB_CID_QUEUE_EX 0x95a +#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b +#define mmMC_RPB_TCI_CNTL 0x95c +#define mmMC_RPB_TCI_CNTL2 0x95d +#define mmMC_SHARED_CHMAP 0x801 +#define mmMC_SHARED_CHREMAP 0x802 +#define mmMC_RD_GRP_GFX 0x803 +#define mmMC_WR_GRP_GFX 0x804 +#define mmMC_RD_GRP_SYS 0x805 +#define mmMC_WR_GRP_SYS 0x806 +#define mmMC_RD_GRP_OTH 0x807 +#define mmMC_WR_GRP_OTH 0x808 +#define mmMC_VM_FB_LOCATION 0x809 +#define mmMC_VM_AGP_TOP 0x80a +#define mmMC_VM_AGP_BOT 0x80b +#define mmMC_VM_AGP_BASE 0x80c +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f +#define mmMC_VM_DC_WRITE_CNTL 0x810 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818 +#define mmMC_VM_MX_L1_TLB_CNTL 0x819 +#define mmMC_VM_FB_OFFSET 0x81a +#define mmMC_VM_STEERING 0x81b +#define mmMC_SHARED_CHREMAP2 0x81c +#define mmMC_SHARED_VF_ENABLE 0x81d +#define mmMC_SHARED_VIRT_RESET_REQ 0x81e +#define mmMC_SHARED_ACTIVE_FCN_ID 0x81f +#define mmMC_CONFIG_MCD 0x828 +#define mmMC_CG_CONFIG_MCD 0x829 +#define mmMC_MEM_POWER_LS 0x82a +#define mmMC_SHARED_BLACKOUT_CNTL 0x82b +#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891 +#define mmMC_VM_MB_L1_TLB1_DEBUG 0x892 +#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893 +#define mmMC_VM_MB_L1_TLB0_STATUS 0x895 +#define mmMC_VM_MB_L1_TLB1_STATUS 0x896 +#define mmMC_VM_MB_L1_TLB2_STATUS 0x897 +#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1 +#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5 +#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6 +#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998 +#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999 +#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a +#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b +#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c +#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d +#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4 +#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7 +#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8 +#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd +#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce +#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf +#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0 +#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1 +#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2 +#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3 +#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4 +#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5 +#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da +#define mmMC_XPB_RTR_DEST_MAP0 0x8db +#define mmMC_XPB_RTR_DEST_MAP1 0x8dc +#define mmMC_XPB_RTR_DEST_MAP2 0x8dd +#define mmMC_XPB_RTR_DEST_MAP3 0x8de +#define mmMC_XPB_RTR_DEST_MAP4 0x8df +#define mmMC_XPB_RTR_DEST_MAP5 0x8e0 +#define mmMC_XPB_RTR_DEST_MAP6 0x8e1 +#define mmMC_XPB_RTR_DEST_MAP7 0x8e2 +#define mmMC_XPB_RTR_DEST_MAP8 0x8e3 +#define mmMC_XPB_RTR_DEST_MAP9 0x8e4 +#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5 +#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6 +#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7 +#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8 +#define mmMC_XPB_CLG_CFG0 0x8e9 +#define mmMC_XPB_CLG_CFG1 0x8ea +#define mmMC_XPB_CLG_CFG2 0x8eb +#define mmMC_XPB_CLG_CFG3 0x8ec +#define mmMC_XPB_CLG_CFG4 0x8ed +#define mmMC_XPB_CLG_CFG5 0x8ee +#define mmMC_XPB_CLG_CFG6 0x8ef +#define mmMC_XPB_CLG_CFG7 0x8f0 +#define mmMC_XPB_CLG_CFG8 0x8f1 +#define mmMC_XPB_CLG_CFG9 0x8f2 +#define mmMC_XPB_CLG_CFG10 0x8f3 +#define mmMC_XPB_CLG_CFG11 0x8f4 +#define mmMC_XPB_CLG_CFG12 0x8f5 +#define mmMC_XPB_CLG_CFG13 0x8f6 +#define mmMC_XPB_CLG_CFG14 0x8f7 +#define mmMC_XPB_CLG_CFG15 0x8f8 +#define mmMC_XPB_CLG_CFG16 0x8f9 +#define mmMC_XPB_CLG_CFG17 0x8fa +#define mmMC_XPB_CLG_CFG18 0x8fb +#define mmMC_XPB_CLG_CFG19 0x8fc +#define mmMC_XPB_CLG_EXTRA 0x8fd +#define mmMC_XPB_LB_ADDR 0x8fe +#define mmMC_XPB_UNC_THRESH_HST 0x8ff +#define mmMC_XPB_UNC_THRESH_SID 0x900 +#define mmMC_XPB_WCB_STS 0x901 +#define mmMC_XPB_WCB_CFG 0x902 +#define mmMC_XPB_P2P_BAR_CFG 0x903 +#define mmMC_XPB_P2P_BAR0 0x904 +#define mmMC_XPB_P2P_BAR1 0x905 +#define mmMC_XPB_P2P_BAR2 0x906 +#define mmMC_XPB_P2P_BAR3 0x907 +#define mmMC_XPB_P2P_BAR4 0x908 +#define mmMC_XPB_P2P_BAR5 0x909 +#define mmMC_XPB_P2P_BAR6 0x90a +#define mmMC_XPB_P2P_BAR7 0x90b +#define mmMC_XPB_P2P_BAR_SETUP 0x90c +#define mmMC_XPB_P2P_BAR_DEBUG 0x90d +#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e +#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f +#define mmMC_XPB_PEER_SYS_BAR0 0x910 +#define mmMC_XPB_PEER_SYS_BAR1 0x911 +#define mmMC_XPB_PEER_SYS_BAR2 0x912 +#define mmMC_XPB_PEER_SYS_BAR3 0x913 +#define mmMC_XPB_PEER_SYS_BAR4 0x914 +#define mmMC_XPB_PEER_SYS_BAR5 0x915 +#define mmMC_XPB_PEER_SYS_BAR6 0x916 +#define mmMC_XPB_PEER_SYS_BAR7 0x917 +#define mmMC_XPB_PEER_SYS_BAR8 0x918 +#define mmMC_XPB_PEER_SYS_BAR9 0x919 +#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a +#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b +#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c +#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d +#define mmMC_XPB_CLK_GAT 0x91e +#define mmMC_XPB_INTF_CFG 0x91f +#define mmMC_XPB_INTF_STS 0x920 +#define mmMC_XPB_PIPE_STS 0x921 +#define mmMC_XPB_SUB_CTRL 0x922 +#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923 +#define mmMC_XPB_PERF_KNOBS 0x924 +#define mmMC_XPB_STICKY 0x925 +#define mmMC_XPB_STICKY_W1C 0x926 +#define mmMC_XPB_MISC_CFG 0x927 +#define mmMC_XPB_CLG_CFG20 0x928 +#define mmMC_XPB_CLG_CFG21 0x929 +#define mmMC_XPB_CLG_CFG22 0x92a +#define mmMC_XPB_CLG_CFG23 0x92b +#define mmMC_XPB_CLG_CFG24 0x92c +#define mmMC_XPB_CLG_CFG25 0x92d +#define mmMC_XPB_CLG_CFG26 0x92e +#define mmMC_XPB_CLG_CFG27 0x92f +#define mmMC_XPB_CLG_CFG28 0x930 +#define mmMC_XPB_CLG_CFG29 0x931 +#define mmMC_XPB_CLG_CFG30 0x932 +#define mmMC_XPB_CLG_CFG31 0x933 +#define mmMC_XPB_INTF_CFG2 0x934 +#define mmMC_XPB_CLG_EXTRA_RD 0x935 +#define mmMC_XPB_CLG_CFG32 0x936 +#define mmMC_XPB_CLG_CFG33 0x937 +#define mmMC_XPB_CLG_CFG34 0x938 +#define mmMC_XPB_CLG_CFG35 0x939 +#define mmMC_XPB_CLG_CFG36 0x93a +#define mmMC_XBAR_ADDR_DEC 0xc80 +#define mmMC_XBAR_REMOTE 0xc81 +#define mmMC_XBAR_WRREQ_CREDIT 0xc82 +#define mmMC_XBAR_RDREQ_CREDIT 0xc83 +#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84 +#define mmMC_XBAR_WRRET_CREDIT1 0xc85 +#define mmMC_XBAR_WRRET_CREDIT2 0xc86 +#define mmMC_XBAR_RDRET_CREDIT1 0xc87 +#define mmMC_XBAR_RDRET_CREDIT2 0xc88 +#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89 +#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a +#define mmMC_XBAR_CHTRIREMAP 0xc8b +#define mmMC_XBAR_TWOCHAN 0xc8c +#define mmMC_XBAR_ARB 0xc8d +#define mmMC_XBAR_ARB_MAX_BURST 0xc8e +#define mmMC_XBAR_FIFO_MON_CNTL0 0xc8f +#define mmMC_XBAR_FIFO_MON_CNTL1 0xc90 +#define mmMC_XBAR_FIFO_MON_CNTL2 0xc91 +#define mmMC_XBAR_FIFO_MON_RSLT0 0xc92 +#define mmMC_XBAR_FIFO_MON_RSLT1 0xc93 +#define mmMC_XBAR_FIFO_MON_RSLT2 0xc94 +#define mmMC_XBAR_FIFO_MON_RSLT3 0xc95 +#define mmMC_XBAR_FIFO_MON_MAX_THSH 0xc96 +#define mmMC_XBAR_SPARE0 0xc97 +#define mmMC_XBAR_SPARE1 0xc98 +#define mmMC_CITF_PERFCOUNTER_LO 0x7a0 +#define mmMC_HUB_PERFCOUNTER_LO 0x7a1 +#define mmMC_RPB_PERFCOUNTER_LO 0x7a2 +#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3 +#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4 +#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5 +#define mmMC_ARB_PERFCOUNTER_LO 0x7a6 +#define mmATC_PERFCOUNTER_LO 0x7a7 +#define mmMC_CITF_PERFCOUNTER_HI 0x7a8 +#define mmMC_HUB_PERFCOUNTER_HI 0x7a9 +#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa +#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab +#define mmMC_RPB_PERFCOUNTER_HI 0x7ac +#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad +#define mmMC_ARB_PERFCOUNTER_HI 0x7ae +#define mmATC_PERFCOUNTER_HI 0x7af +#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0 +#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1 +#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2 +#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3 +#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4 +#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5 +#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6 +#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7 +#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8 +#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9 +#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba +#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb +#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc +#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd +#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be +#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf +#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0 +#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1 +#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2 +#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3 +#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4 +#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5 +#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6 +#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7 +#define mmATC_PERFCOUNTER0_CFG 0x7c8 +#define mmATC_PERFCOUNTER1_CFG 0x7c9 +#define mmATC_PERFCOUNTER2_CFG 0x7ca +#define mmATC_PERFCOUNTER3_CFG 0x7cb +#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc +#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd +#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce +#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf +#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0 +#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1 +#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2 +#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3 +#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4 +#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5 +#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6 +#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7 +#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8 +#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9 +#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da +#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0 +#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1 +#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2 +#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3 +#define mmATC_VM_APERTURE0_CNTL 0xcc4 +#define mmATC_VM_APERTURE1_CNTL 0xcc5 +#define mmATC_VM_APERTURE0_CNTL2 0xcc6 +#define mmATC_VM_APERTURE1_CNTL2 0xcc7 +#define mmATC_ATS_CNTL 0xcc9 +#define mmATC_ATS_DEBUG 0xcca +#define mmATC_ATS_FAULT_DEBUG 0xccb +#define mmATC_ATS_STATUS 0xccc +#define mmATC_ATS_FAULT_CNTL 0xccd +#define mmATC_ATS_FAULT_STATUS_INFO 0xcce +#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf +#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0 +#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1 +#define mmATC_ATS_FAULT_STATUS_INFO2 0xcd2 +#define mmATC_MISC_CG 0xcd4 +#define mmATC_L2_CNTL 0xcd5 +#define mmATC_L2_CNTL2 0xcd6 +#define mmATC_L2_DEBUG 0xcd7 +#define mmATC_L2_DEBUG2 0xcd8 +#define mmATC_L2_CACHE_DATA0 0xcd9 +#define mmATC_L2_CACHE_DATA1 0xcda +#define mmATC_L2_CACHE_DATA2 0xcdb +#define mmATC_L1_CNTL 0xcdc +#define mmATC_L1_ADDRESS_OFFSET 0xcdd +#define mmATC_L1RD_DEBUG_TLB 0xcde +#define mmATC_L1WR_DEBUG_TLB 0xcdf +#define mmATC_L1RD_STATUS 0xce0 +#define mmATC_L1WR_STATUS 0xce1 +#define mmATC_L1RD_DEBUG2_TLB 0xce2 +#define mmATC_L1WR_DEBUG2_TLB 0xce3 +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6 +#define mmATC_VMID0_PASID_MAPPING 0xce7 +#define mmATC_VMID1_PASID_MAPPING 0xce8 +#define mmATC_VMID2_PASID_MAPPING 0xce9 +#define mmATC_VMID3_PASID_MAPPING 0xcea +#define mmATC_VMID4_PASID_MAPPING 0xceb +#define mmATC_VMID5_PASID_MAPPING 0xcec +#define mmATC_VMID6_PASID_MAPPING 0xced +#define mmATC_VMID7_PASID_MAPPING 0xcee +#define mmATC_VMID8_PASID_MAPPING 0xcef +#define mmATC_VMID9_PASID_MAPPING 0xcf0 +#define mmATC_VMID10_PASID_MAPPING 0xcf1 +#define mmATC_VMID11_PASID_MAPPING 0xcf2 +#define mmATC_VMID12_PASID_MAPPING 0xcf3 +#define mmATC_VMID13_PASID_MAPPING 0xcf4 +#define mmATC_VMID14_PASID_MAPPING 0xcf5 +#define mmATC_VMID15_PASID_MAPPING 0xcf6 +#define mmATC_ATS_VMID_STATUS 0xd07 +#define mmATC_ATS_SMU_STATUS 0xd08 +#define mmATC_L2_CNTL3 0xd09 +#define mmATC_L2_STATUS 0xd0a +#define mmATC_L2_STATUS2 0xd0b +#define mmGMCON_RENG_RAM_INDEX 0xd40 +#define mmGMCON_RENG_RAM_DATA 0xd41 +#define mmGMCON_RENG_EXECUTE 0xd42 +#define mmGMCON_MISC 0xd43 +#define mmGMCON_MISC2 0xd44 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49 +#define mmGMCON_PERF_MON_CNTL0 0xd4a +#define mmGMCON_PERF_MON_CNTL1 0xd4b +#define mmGMCON_PERF_MON_RSLT0 0xd4c +#define mmGMCON_PERF_MON_RSLT1 0xd4d +#define mmGMCON_PGFSM_CONFIG 0xd4e +#define mmGMCON_PGFSM_WRITE 0xd4f +#define mmGMCON_PGFSM_READ 0xd50 +#define mmGMCON_MISC3 0xd51 +#define mmGMCON_MASK 0xd52 +#define mmGMCON_LPT_TARGET 0xd53 +#define mmGMCON_DEBUG 0xd5f +#define mmVM_L2_CNTL 0x500 +#define mmVM_L2_CNTL2 0x501 +#define mmVM_L2_CNTL3 0x502 +#define mmVM_L2_STATUS 0x503 +#define mmVM_CONTEXT0_CNTL 0x504 +#define mmVM_CONTEXT1_CNTL 0x505 +#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506 +#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507 +#define mmVM_CONTEXT0_CNTL2 0x50c +#define mmVM_CONTEXT1_CNTL2 0x50d +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 +#define mmVM_INVALIDATE_REQUEST 0x51e +#define mmVM_INVALIDATE_RESPONSE 0x51f +#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c +#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d +#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e +#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f +#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530 +#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531 +#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532 +#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533 +#define mmVM_PRT_CNTL 0x534 +#define mmVM_CONTEXTS_DISABLE 0x535 +#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536 +#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 +#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538 +#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539 +#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e +#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f +#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 +#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 +#define mmVM_FAULT_CLIENT_ID 0x54e +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 +#define mmVM_DEBUG 0x56f +#define mmVM_L2_CG 0x570 +#define mmVM_L2_BANK_SELECT_MASKA 0x572 +#define mmVM_L2_BANK_SELECT_MASKB 0x573 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577 +#define mmVM_L2_CNTL4 0x578 +#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x579 +#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x57a +#define mmMC_VM_FB_SIZE_OFFSET_VF0 0xf980 +#define mmMC_VM_FB_SIZE_OFFSET_VF1 0xf981 +#define mmMC_VM_FB_SIZE_OFFSET_VF2 0xf982 +#define mmMC_VM_FB_SIZE_OFFSET_VF3 0xf983 +#define mmMC_VM_FB_SIZE_OFFSET_VF4 0xf984 +#define mmMC_VM_FB_SIZE_OFFSET_VF5 0xf985 +#define mmMC_VM_FB_SIZE_OFFSET_VF6 0xf986 +#define mmMC_VM_FB_SIZE_OFFSET_VF7 0xf987 +#define mmMC_VM_FB_SIZE_OFFSET_VF8 0xf988 +#define mmMC_VM_FB_SIZE_OFFSET_VF9 0xf989 +#define mmMC_VM_FB_SIZE_OFFSET_VF10 0xf98a +#define mmMC_VM_FB_SIZE_OFFSET_VF11 0xf98b +#define mmMC_VM_FB_SIZE_OFFSET_VF12 0xf98c +#define mmMC_VM_FB_SIZE_OFFSET_VF13 0xf98d +#define mmMC_VM_FB_SIZE_OFFSET_VF14 0xf98e +#define mmMC_VM_FB_SIZE_OFFSET_VF15 0xf98f +#define mmMC_VM_NB_MMIOBASE 0xf990 +#define mmMC_VM_NB_MMIOLIMIT 0xf991 +#define mmMC_VM_NB_PCI_CTRL 0xf992 +#define mmMC_VM_NB_PCI_ARB 0xf993 +#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0xf994 +#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0xf995 +#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0xf996 +#define mmMC_VM_NB_TOP_OF_DRAM3 0xf997 +#define mmMC_VM_MARC_BASE_LO_0 0xf998 +#define mmMC_VM_MARC_BASE_LO_1 0xf99e +#define mmMC_VM_MARC_BASE_LO_2 0xf9a4 +#define mmMC_VM_MARC_BASE_LO_3 0xf9aa +#define mmMC_VM_MARC_BASE_HI_0 0xf999 +#define mmMC_VM_MARC_BASE_HI_1 0xf99f +#define mmMC_VM_MARC_BASE_HI_2 0xf9a5 +#define mmMC_VM_MARC_BASE_HI_3 0xf9ab +#define mmMC_VM_MARC_RELOC_LO_0 0xf99a +#define mmMC_VM_MARC_RELOC_LO_1 0xf9a0 +#define mmMC_VM_MARC_RELOC_LO_2 0xf9a6 +#define mmMC_VM_MARC_RELOC_LO_3 0xf9ac +#define mmMC_VM_MARC_RELOC_HI_0 0xf99b +#define mmMC_VM_MARC_RELOC_HI_1 0xf9a1 +#define mmMC_VM_MARC_RELOC_HI_2 0xf9a7 +#define mmMC_VM_MARC_RELOC_HI_3 0xf9ad +#define mmMC_VM_MARC_LEN_LO_0 0xf99c +#define mmMC_VM_MARC_LEN_LO_1 0xf9a2 +#define mmMC_VM_MARC_LEN_LO_2 0xf9a8 +#define mmMC_VM_MARC_LEN_LO_3 0xf9ae +#define mmMC_VM_MARC_LEN_HI_0 0xf99d +#define mmMC_VM_MARC_LEN_HI_1 0xf9a3 +#define mmMC_VM_MARC_LEN_HI_2 0xf9a9 +#define mmMC_VM_MARC_LEN_HI_3 0xf9af +#define mmMC_VM_MARC_CNTL 0xf9b0 +#define mmMC_VM_MB_L1_TLS0_CNTL0 0xf9b1 +#define mmMC_VM_MB_L1_TLS0_CNTL1 0xf9b4 +#define mmMC_VM_MB_L1_TLS0_CNTL2 0xf9b7 +#define mmMC_VM_MB_L1_TLS0_CNTL3 0xf9ba +#define mmMC_VM_MB_L1_TLS0_CNTL4 0xf9bd +#define mmMC_VM_MB_L1_TLS0_CNTL5 0xf9c0 +#define mmMC_VM_MB_L1_TLS0_CNTL6 0xf9c3 +#define mmMC_VM_MB_L1_TLS0_CNTL7 0xf9c6 +#define mmMC_VM_MB_L1_TLS0_CNTL8 0xf9c9 +#define mmMC_VM_MB_L1_TLS0_START_ADDR0 0xf9b2 +#define mmMC_VM_MB_L1_TLS0_START_ADDR1 0xf9b5 +#define mmMC_VM_MB_L1_TLS0_START_ADDR2 0xf9b8 +#define mmMC_VM_MB_L1_TLS0_START_ADDR3 0xf9bb +#define mmMC_VM_MB_L1_TLS0_START_ADDR4 0xf9be +#define mmMC_VM_MB_L1_TLS0_START_ADDR5 0xf9c1 +#define mmMC_VM_MB_L1_TLS0_START_ADDR6 0xf9c4 +#define mmMC_VM_MB_L1_TLS0_START_ADDR7 0xf9c7 +#define mmMC_VM_MB_L1_TLS0_START_ADDR8 0xf9ca +#define mmMC_VM_MB_L1_TLS0_END_ADDR0 0xf9b3 +#define mmMC_VM_MB_L1_TLS0_END_ADDR1 0xf9b6 +#define mmMC_VM_MB_L1_TLS0_END_ADDR2 0xf9b9 +#define mmMC_VM_MB_L1_TLS0_END_ADDR3 0xf9bc +#define mmMC_VM_MB_L1_TLS0_END_ADDR4 0xf9bf +#define mmMC_VM_MB_L1_TLS0_END_ADDR5 0xf9c2 +#define mmMC_VM_MB_L1_TLS0_END_ADDR6 0xf9c5 +#define mmMC_VM_MB_L1_TLS0_END_ADDR7 0xf9c8 +#define mmMC_VM_MB_L1_TLS0_END_ADDR8 0xf9cb +#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS 0xf9cc +#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR 0xf9cd +#define mmMC_SEQ_CNTL 0xa25 +#define mmMC_SEQ_CNTL_2 0xad4 +#define mmMC_SEQ_DRAM 0xa26 +#define mmMC_SEQ_DRAM_2 0xa27 +#define mmMC_SEQ_RAS_TIMING 0xa28 +#define mmMC_SEQ_CAS_TIMING 0xa29 +#define mmMC_SEQ_MISC_TIMING 0xa2a +#define mmMC_SEQ_MISC_TIMING2 0xa2b +#define mmMC_SEQ_PMG_TIMING 0xa2c +#define mmMC_SEQ_RD_CTL_D0 0xa2d +#define mmMC_SEQ_RD_CTL_D1 0xa2e +#define mmMC_SEQ_WR_CTL_D0 0xa2f +#define mmMC_SEQ_WR_CTL_D1 0xa30 +#define mmMC_SEQ_WR_CTL_2 0xad5 +#define mmMC_SEQ_CMD 0xa31 +#define mmMC_PMG_CMD_EMRS 0xa83 +#define mmMC_PMG_CMD_MRS 0xaab +#define mmMC_PMG_CMD_MRS1 0xad1 +#define mmMC_PMG_CMD_MRS2 0xad7 +#define mmMC_PMG_CFG 0xa84 +#define mmMC_PMG_AUTO_CMD 0xa34 +#define mmMC_PMG_AUTO_CFG 0xa35 +#define mmMC_IMP_CNTL 0xa36 +#define mmMC_IMP_DEBUG 0xa37 +#define mmMC_IMP_STATUS 0xa38 +#define mmMC_IMP_DQ_STATUS 0xabc +#define mmMC_SEQ_WCDR_CTRL 0xa39 +#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0xa3a +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0xa3b +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0xafe +#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0xaff +#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0xa3c +#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0xa3d +#define mmMC_SEQ_TRAIN_CAPTURE 0xa3e +#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0xa3f +#define mmMC_SEQ_TRAIN_TIMING 0xa40 +#define mmMC_TRAIN_EDCCDR_R_D0 0xa41 +#define mmMC_TRAIN_EDCCDR_R_D1 0xa42 +#define mmMC_TRAIN_PRBSERR_0_D0 0xa43 +#define mmMC_TRAIN_PRBSERR_1_D0 0xa44 +#define mmMC_TRAIN_PRBSERR_2_D0 0xafb +#define mmMC_TRAIN_EDC_STATUS_D0 0xa45 +#define mmMC_TRAIN_PRBSERR_0_D1 0xa46 +#define mmMC_TRAIN_PRBSERR_1_D1 0xa47 +#define mmMC_TRAIN_PRBSERR_2_D1 0xafc +#define mmMC_TRAIN_EDC_STATUS_D1 0xa48 +#define mmMC_IO_TXCNTL_DPHY0_D0 0xa49 +#define mmMC_IO_TXCNTL_DPHY1_D0 0xa4a +#define mmMC_IO_TXCNTL_APHY_D0 0xa4b +#define mmMC_IO_RXCNTL_DPHY0_D0 0xa4c +#define mmMC_IO_RXCNTL1_DPHY0_D0 0xadf +#define mmMC_IO_RXCNTL_DPHY1_D0 0xa4d +#define mmMC_IO_RXCNTL1_DPHY1_D0 0xae0 +#define mmMC_IO_DPHY_STR_CNTL_D0 0xa4e +#define mmMC_IO_APHY_STR_CNTL_D0 0xa97 +#define mmMC_IO_TXCNTL_DPHY0_D1 0xa4f +#define mmMC_IO_TXCNTL_DPHY1_D1 0xa50 +#define mmMC_IO_TXCNTL_APHY_D1 0xa51 +#define mmMC_IO_RXCNTL_DPHY0_D1 0xa52 +#define mmMC_IO_RXCNTL1_DPHY0_D1 0xae1 +#define mmMC_IO_RXCNTL_DPHY1_D1 0xa53 +#define mmMC_IO_RXCNTL1_DPHY1_D1 0xae2 +#define mmMC_IO_DPHY_STR_CNTL_D1 0xa54 +#define mmMC_IO_APHY_STR_CNTL_D1 0xa98 +#define mmMC_IO_CDRCNTL_D0 0xa55 +#define mmMC_IO_CDRCNTL1_D0 0xadd +#define mmMC_IO_CDRCNTL2_D0 0xae4 +#define mmMC_IO_CDRCNTL_D1 0xa56 +#define mmMC_IO_CDRCNTL1_D1 0xade +#define mmMC_IO_CDRCNTL2_D1 0xae5 +#define mmMC_SEQ_FIFO_CTL 0xa57 +#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0xa58 +#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0xa59 +#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0xa5a +#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0xa5b +#define mmMC_SEQ_TXFRAMING_DBI_D0 0xa5c +#define mmMC_SEQ_TXFRAMING_EDC_D0 0xa5d +#define mmMC_SEQ_TXFRAMING_FCK_D0 0xa5e +#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0xa60 +#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0xa61 +#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0xa62 +#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0xa63 +#define mmMC_SEQ_TXFRAMING_DBI_D1 0xa64 +#define mmMC_SEQ_TXFRAMING_EDC_D1 0xa65 +#define mmMC_SEQ_TXFRAMING_FCK_D1 0xa66 +#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0xa67 +#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0xa68 +#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0xa69 +#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0xa6a +#define mmMC_SEQ_RXFRAMING_DBI_D0 0xa6b +#define mmMC_SEQ_RXFRAMING_EDC_D0 0xa6c +#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0xa6d +#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0xa6e +#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0xa6f +#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0xa70 +#define mmMC_SEQ_RXFRAMING_DBI_D1 0xa71 +#define mmMC_SEQ_RXFRAMING_EDC_D1 0xa72 +#define mmMC_IO_PAD_CNTL 0xa73 +#define mmMC_IO_PAD_CNTL_D0 0xa74 +#define mmMC_IO_PAD_CNTL_D1 0xa75 +#define mmMC_NPL_STATUS 0xa76 +#define mmMC_BIST_CMD_CNTL 0xa8e +#define mmMC_BIST_CNTL 0xa05 +#define mmMC_BIST_AUTO_CNTL 0xa06 +#define mmMC_BIST_DIR_CNTL 0xa07 +#define mmMC_BIST_SADDR 0xa08 +#define mmMC_BIST_EADDR 0xa09 +#define mmMC_BIST_CMP_CNTL 0xa8d +#define mmMC_BIST_CMP_CNTL_2 0xab6 +#define mmMC_BIST_DATA_WORD0 0xa0a +#define mmMC_BIST_DATA_WORD1 0xa0b +#define mmMC_BIST_DATA_WORD2 0xa0c +#define mmMC_BIST_DATA_WORD3 0xa0d +#define mmMC_BIST_DATA_WORD4 0xa0e +#define mmMC_BIST_DATA_WORD5 0xa0f +#define mmMC_BIST_DATA_WORD6 0xa10 +#define mmMC_BIST_DATA_WORD7 0xa11 +#define mmMC_BIST_DATA_MASK 0xa12 +#define mmMC_BIST_MISMATCH_ADDR 0xa13 +#define mmMC_BIST_RDATA_WORD0 0xa14 +#define mmMC_BIST_RDATA_WORD1 0xa15 +#define mmMC_BIST_RDATA_WORD2 0xa16 +#define mmMC_BIST_RDATA_WORD3 0xa17 +#define mmMC_BIST_RDATA_WORD4 0xa18 +#define mmMC_BIST_RDATA_WORD5 0xa19 +#define mmMC_BIST_RDATA_WORD6 0xa1a +#define mmMC_BIST_RDATA_WORD7 0xa1b +#define mmMC_BIST_RDATA_MASK 0xa1c +#define mmMC_BIST_RDATA_EDC 0xa1d +#define mmMC_SEQ_PERF_CNTL 0xa77 +#define mmMC_SEQ_PERF_CNTL_1 0xafd +#define mmMC_SEQ_PERF_SEQ_CTL 0xa78 +#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0xa79 +#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0xa7a +#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0xa7b +#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0xa7c +#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0xad9 +#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0xada +#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0xadb +#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0xadc +#define mmMC_SEQ_STATUS_M 0xa7d +#define mmMC_SEQ_STATUS_S 0xa20 +#define mmMC_CG_DATAPORT 0xa21 +#define mmMC_SEQ_VENDOR_ID_I0 0xa7e +#define mmMC_SEQ_VENDOR_ID_I1 0xa7f +#define mmMC_SEQ_MISC0 0xa80 +#define mmMC_SEQ_MISC1 0xa81 +#define mmMC_SEQ_RESERVE_0_S 0xa1e +#define mmMC_SEQ_RESERVE_1_S 0xa1f +#define mmMC_SEQ_RESERVE_M 0xa82 +#define mmMC_SEQ_IO_RESERVE_D0 0xab7 +#define mmMC_SEQ_IO_RESERVE_D1 0xab8 +#define mmMC_SEQ_SUP_CNTL 0xa32 +#define mmMC_SEQ_SUP_PGM 0xa33 +#define mmMC_SEQ_SUP_GP0_STAT 0xa8f +#define mmMC_SEQ_SUP_GP1_STAT 0xa90 +#define mmMC_SEQ_SUP_GP2_STAT 0xa85 +#define mmMC_SEQ_SUP_GP3_STAT 0xa86 +#define mmMC_SEQ_SUP_IR_STAT 0xa87 +#define mmMC_SEQ_SUP_DEC_STAT 0xa88 +#define mmMC_SEQ_SUP_PGM_STAT 0xa89 +#define mmMC_SEQ_SUP_R_PGM 0xa8a +#define mmMC_SEQ_MISC3 0xa8b +#define mmMC_SEQ_MISC4 0xa8c +#define mmMC_SEQ_MISC5 0xa95 +#define mmMC_SEQ_MISC6 0xa96 +#define mmMC_SEQ_MISC7 0xa99 +#define mmMC_SEQ_MISC8 0xa5f +#define mmMC_SEQ_MISC9 0xae7 +#define mmMC_SEQ_CG 0xa9a +#define mmMC_SEQ_BYTE_REMAP_D0 0xa93 +#define mmMC_SEQ_BYTE_REMAP_D1 0xa94 +#define mmMC_SEQ_BIT_REMAP_B0_D0 0xaa3 +#define mmMC_SEQ_BIT_REMAP_B1_D0 0xaa4 +#define mmMC_SEQ_BIT_REMAP_B2_D0 0xaa5 +#define mmMC_SEQ_BIT_REMAP_B3_D0 0xaa6 +#define mmMC_SEQ_BIT_REMAP_B0_D1 0xaa7 +#define mmMC_SEQ_BIT_REMAP_B1_D1 0xaa8 +#define mmMC_SEQ_BIT_REMAP_B2_D1 0xaa9 +#define mmMC_SEQ_BIT_REMAP_B3_D1 0xaaa +#define mmMC_SEQ_RAS_TIMING_LP 0xa9b +#define mmMC_SEQ_CAS_TIMING_LP 0xa9c +#define mmMC_SEQ_MISC_TIMING_LP 0xa9d +#define mmMC_SEQ_MISC_TIMING2_LP 0xa9e +#define mmMC_SEQ_RD_CTL_D0_LP 0xac7 +#define mmMC_SEQ_RD_CTL_D1_LP 0xac8 +#define mmMC_SEQ_WR_CTL_D0_LP 0xa9f +#define mmMC_SEQ_WR_CTL_D1_LP 0xaa0 +#define mmMC_SEQ_WR_CTL_2_LP 0xad6 +#define mmMC_SEQ_PMG_CMD_EMRS_LP 0xaa1 +#define mmMC_SEQ_PMG_CMD_MRS_LP 0xaa2 +#define mmMC_SEQ_PMG_CMD_MRS1_LP 0xad2 +#define mmMC_SEQ_PMG_CMD_MRS2_LP 0xad8 +#define mmMC_SEQ_PMG_TIMING_LP 0xad3 +#define mmMC_SEQ_IO_RWORD0 0xaac +#define mmMC_SEQ_IO_RWORD1 0xaad +#define mmMC_SEQ_IO_RWORD2 0xaae +#define mmMC_SEQ_IO_RWORD3 0xaaf +#define mmMC_SEQ_IO_RWORD4 0xab0 +#define mmMC_SEQ_IO_RWORD5 0xab1 +#define mmMC_SEQ_IO_RWORD6 0xab2 +#define mmMC_SEQ_IO_RWORD7 0xab3 +#define mmMC_SEQ_IO_RDBI 0xab4 +#define mmMC_SEQ_IO_REDC 0xab5 +#define mmMC_SEQ_TCG_CNTL 0xabd +#define mmMC_SEQ_TSM_CTRL 0xabe +#define mmMC_SEQ_TSM_GCNT 0xabf +#define mmMC_SEQ_TSM_OCNT 0xac0 +#define mmMC_SEQ_TSM_NCNT 0xac1 +#define mmMC_SEQ_TSM_BCNT 0xac2 +#define mmMC_SEQ_TSM_FLAG 0xac3 +#define mmMC_SEQ_TSM_UPDATE 0xac4 +#define mmMC_SEQ_TSM_EDC 0xac5 +#define mmMC_SEQ_TSM_DBI 0xac6 +#define mmMC_SEQ_TSM_WCDR 0xae3 +#define mmMC_SEQ_TSM_MISC 0xae6 +#define mmMC_SEQ_TIMER_WR 0xac9 +#define mmMC_SEQ_TIMER_RD 0xaca +#define mmMC_SEQ_DRAM_ERROR_INSERTION 0xacb +#define mmMC_PHY_TIMING_D0 0xacc +#define mmMC_PHY_TIMING_D1 0xacd +#define mmMC_PHY_TIMING_2 0xace +#define mmMC_SEQ_MPLL_OVERRIDE 0xa22 +#define mmMCLK_PWRMGT_CNTL 0xae8 +#define mmDLL_CNTL 0xae9 +#define mmMPLL_SEQ_UCODE_1 0xaea +#define mmMPLL_SEQ_UCODE_2 0xaeb +#define mmMPLL_CNTL_MODE 0xaec +#define mmMPLL_FUNC_CNTL 0xaed +#define mmMPLL_FUNC_CNTL_1 0xaee +#define mmMPLL_FUNC_CNTL_2 0xaef +#define mmMPLL_AD_FUNC_CNTL 0xaf0 +#define mmMPLL_DQ_FUNC_CNTL 0xaf1 +#define mmMPLL_TIME 0xaf2 +#define mmMPLL_SS1 0xaf3 +#define mmMPLL_SS2 0xaf4 +#define mmMPLL_CONTROL 0xaf5 +#define mmMPLL_AD_STATUS 0xaf6 +#define mmMPLL_DQ_0_0_STATUS 0xaf7 +#define mmMPLL_DQ_0_1_STATUS 0xaf8 +#define mmMPLL_DQ_1_0_STATUS 0xaf9 +#define mmMPLL_DQ_1_1_STATUS 0xafa +#define mmMC_SEQ_PMG_PG_HWCNTL 0xab9 +#define mmMC_SEQ_PMG_PG_SWCNTL_0 0xaba +#define mmMC_SEQ_PMG_PG_SWCNTL_1 0xabb +#define mmMC_SEQ_TSM_DEBUG_INDEX 0xacf +#define mmMC_SEQ_TSM_DEBUG_DATA 0xad0 +#define ixMC_TSM_DEBUG_GCNT 0x0 +#define ixMC_TSM_DEBUG_FLAG 0x1 +#define ixMC_TSM_DEBUG_MISC 0x2 +#define ixMC_TSM_DEBUG_BCNT0 0x3 +#define ixMC_TSM_DEBUG_BCNT1 0x4 +#define ixMC_TSM_DEBUG_BCNT2 0x5 +#define ixMC_TSM_DEBUG_BCNT3 0x6 +#define ixMC_TSM_DEBUG_BCNT4 0x7 +#define ixMC_TSM_DEBUG_BCNT5 0x8 +#define ixMC_TSM_DEBUG_BCNT6 0x9 +#define ixMC_TSM_DEBUG_BCNT7 0xa +#define ixMC_TSM_DEBUG_BCNT8 0xb +#define ixMC_TSM_DEBUG_BCNT9 0xc +#define ixMC_TSM_DEBUG_BCNT10 0xd +#define ixMC_TSM_DEBUG_ST01 0x10 +#define ixMC_TSM_DEBUG_ST23 0x11 +#define ixMC_TSM_DEBUG_ST45 0x12 +#define ixMC_TSM_DEBUG_BKPT 0x13 +#define mmMC_SEQ_IO_DEBUG_INDEX 0xa91 +#define mmMC_SEQ_IO_DEBUG_DATA 0xa92 +#define ixMC_IO_DEBUG_UP_0 0x0 +#define ixMC_IO_DEBUG_UP_1 0x1 +#define ixMC_IO_DEBUG_UP_2 0x2 +#define ixMC_IO_DEBUG_UP_3 0x3 +#define ixMC_IO_DEBUG_UP_4 0x4 +#define ixMC_IO_DEBUG_UP_5 0x5 +#define ixMC_IO_DEBUG_UP_6 0x6 +#define ixMC_IO_DEBUG_UP_7 0x7 +#define ixMC_IO_DEBUG_UP_8 0x8 +#define ixMC_IO_DEBUG_UP_9 0x9 +#define ixMC_IO_DEBUG_UP_10 0xa +#define ixMC_IO_DEBUG_UP_11 0xb +#define ixMC_IO_DEBUG_UP_12 0xc +#define ixMC_IO_DEBUG_UP_13 0xd +#define ixMC_IO_DEBUG_UP_14 0xe +#define ixMC_IO_DEBUG_UP_15 0xf +#define ixMC_IO_DEBUG_UP_16 0x10 +#define ixMC_IO_DEBUG_UP_17 0x11 +#define ixMC_IO_DEBUG_UP_18 0x12 +#define ixMC_IO_DEBUG_UP_19 0x13 +#define ixMC_IO_DEBUG_UP_20 0x14 +#define ixMC_IO_DEBUG_UP_21 0x15 +#define ixMC_IO_DEBUG_UP_22 0x16 +#define ixMC_IO_DEBUG_UP_23 0x17 +#define ixMC_IO_DEBUG_UP_24 0x18 +#define ixMC_IO_DEBUG_UP_25 0x19 +#define ixMC_IO_DEBUG_UP_26 0x1a +#define ixMC_IO_DEBUG_UP_27 0x1b +#define ixMC_IO_DEBUG_UP_28 0x1c +#define ixMC_IO_DEBUG_UP_29 0x1d +#define ixMC_IO_DEBUG_UP_30 0x1e +#define ixMC_IO_DEBUG_UP_31 0x1f +#define ixMC_IO_DEBUG_UP_32 0x20 +#define ixMC_IO_DEBUG_UP_33 0x21 +#define ixMC_IO_DEBUG_UP_34 0x22 +#define ixMC_IO_DEBUG_UP_35 0x23 +#define ixMC_IO_DEBUG_UP_36 0x24 +#define ixMC_IO_DEBUG_UP_37 0x25 +#define ixMC_IO_DEBUG_UP_38 0x26 +#define ixMC_IO_DEBUG_UP_39 0x27 +#define ixMC_IO_DEBUG_UP_40 0x28 +#define ixMC_IO_DEBUG_UP_41 0x29 +#define ixMC_IO_DEBUG_UP_42 0x2a +#define ixMC_IO_DEBUG_UP_43 0x2b +#define ixMC_IO_DEBUG_UP_44 0x2c +#define ixMC_IO_DEBUG_UP_45 0x2d +#define ixMC_IO_DEBUG_UP_46 0x2e +#define ixMC_IO_DEBUG_UP_47 0x2f +#define ixMC_IO_DEBUG_UP_48 0x30 +#define ixMC_IO_DEBUG_UP_49 0x31 +#define ixMC_IO_DEBUG_UP_50 0x32 +#define ixMC_IO_DEBUG_UP_51 0x33 +#define ixMC_IO_DEBUG_UP_52 0x34 +#define ixMC_IO_DEBUG_UP_53 0x35 +#define ixMC_IO_DEBUG_UP_54 0x36 +#define ixMC_IO_DEBUG_UP_55 0x37 +#define ixMC_IO_DEBUG_UP_56 0x38 +#define ixMC_IO_DEBUG_UP_57 0x39 +#define ixMC_IO_DEBUG_UP_58 0x3a +#define ixMC_IO_DEBUG_UP_59 0x3b +#define ixMC_IO_DEBUG_UP_60 0x3c +#define ixMC_IO_DEBUG_UP_61 0x3d +#define ixMC_IO_DEBUG_UP_62 0x3e +#define ixMC_IO_DEBUG_UP_63 0x3f +#define ixMC_IO_DEBUG_UP_64 0x40 +#define ixMC_IO_DEBUG_UP_65 0x41 +#define ixMC_IO_DEBUG_UP_66 0x42 +#define ixMC_IO_DEBUG_UP_67 0x43 +#define ixMC_IO_DEBUG_UP_68 0x44 +#define ixMC_IO_DEBUG_UP_69 0x45 +#define ixMC_IO_DEBUG_UP_70 0x46 +#define ixMC_IO_DEBUG_UP_71 0x47 +#define ixMC_IO_DEBUG_UP_72 0x48 +#define ixMC_IO_DEBUG_UP_73 0x49 +#define ixMC_IO_DEBUG_UP_74 0x4a +#define ixMC_IO_DEBUG_UP_75 0x4b +#define ixMC_IO_DEBUG_UP_76 0x4c +#define ixMC_IO_DEBUG_UP_77 0x4d +#define ixMC_IO_DEBUG_UP_78 0x4e +#define ixMC_IO_DEBUG_UP_79 0x4f +#define ixMC_IO_DEBUG_UP_80 0x50 +#define ixMC_IO_DEBUG_UP_81 0x51 +#define ixMC_IO_DEBUG_UP_82 0x52 +#define ixMC_IO_DEBUG_UP_83 0x53 +#define ixMC_IO_DEBUG_UP_84 0x54 +#define ixMC_IO_DEBUG_UP_85 0x55 +#define ixMC_IO_DEBUG_UP_86 0x56 +#define ixMC_IO_DEBUG_UP_87 0x57 +#define ixMC_IO_DEBUG_UP_88 0x58 +#define ixMC_IO_DEBUG_UP_89 0x59 +#define ixMC_IO_DEBUG_UP_90 0x5a +#define ixMC_IO_DEBUG_UP_91 0x5b +#define ixMC_IO_DEBUG_UP_92 0x5c +#define ixMC_IO_DEBUG_UP_93 0x5d +#define ixMC_IO_DEBUG_UP_94 0x5e +#define ixMC_IO_DEBUG_UP_95 0x5f +#define ixMC_IO_DEBUG_UP_96 0x60 +#define ixMC_IO_DEBUG_UP_97 0x61 +#define ixMC_IO_DEBUG_UP_98 0x62 +#define ixMC_IO_DEBUG_UP_99 0x63 +#define ixMC_IO_DEBUG_UP_100 0x64 +#define ixMC_IO_DEBUG_UP_101 0x65 +#define ixMC_IO_DEBUG_UP_102 0x66 +#define ixMC_IO_DEBUG_UP_103 0x67 +#define ixMC_IO_DEBUG_UP_104 0x68 +#define ixMC_IO_DEBUG_UP_105 0x69 +#define ixMC_IO_DEBUG_UP_106 0x6a +#define ixMC_IO_DEBUG_UP_107 0x6b +#define ixMC_IO_DEBUG_UP_108 0x6c +#define ixMC_IO_DEBUG_UP_109 0x6d +#define ixMC_IO_DEBUG_UP_110 0x6e +#define ixMC_IO_DEBUG_UP_111 0x6f +#define ixMC_IO_DEBUG_UP_112 0x70 +#define ixMC_IO_DEBUG_UP_113 0x71 +#define ixMC_IO_DEBUG_UP_114 0x72 +#define ixMC_IO_DEBUG_UP_115 0x73 +#define ixMC_IO_DEBUG_UP_116 0x74 +#define ixMC_IO_DEBUG_UP_117 0x75 +#define ixMC_IO_DEBUG_UP_118 0x76 +#define ixMC_IO_DEBUG_UP_119 0x77 +#define ixMC_IO_DEBUG_UP_120 0x78 +#define ixMC_IO_DEBUG_UP_121 0x79 +#define ixMC_IO_DEBUG_UP_122 0x7a +#define ixMC_IO_DEBUG_UP_123 0x7b +#define ixMC_IO_DEBUG_UP_124 0x7c +#define ixMC_IO_DEBUG_UP_125 0x7d +#define ixMC_IO_DEBUG_UP_126 0x7e +#define ixMC_IO_DEBUG_UP_127 0x7f +#define ixMC_IO_DEBUG_UP_128 0x80 +#define ixMC_IO_DEBUG_UP_129 0x81 +#define ixMC_IO_DEBUG_UP_130 0x82 +#define ixMC_IO_DEBUG_UP_131 0x83 +#define ixMC_IO_DEBUG_UP_132 0x84 +#define ixMC_IO_DEBUG_UP_133 0x85 +#define ixMC_IO_DEBUG_UP_134 0x86 +#define ixMC_IO_DEBUG_UP_135 0x87 +#define ixMC_IO_DEBUG_UP_136 0x88 +#define ixMC_IO_DEBUG_UP_137 0x89 +#define ixMC_IO_DEBUG_UP_138 0x8a +#define ixMC_IO_DEBUG_UP_139 0x8b +#define ixMC_IO_DEBUG_UP_140 0x8c +#define ixMC_IO_DEBUG_UP_141 0x8d +#define ixMC_IO_DEBUG_UP_142 0x8e +#define ixMC_IO_DEBUG_UP_143 0x8f +#define ixMC_IO_DEBUG_UP_144 0x90 +#define ixMC_IO_DEBUG_UP_145 0x91 +#define ixMC_IO_DEBUG_UP_146 0x92 +#define ixMC_IO_DEBUG_UP_147 0x93 +#define ixMC_IO_DEBUG_UP_148 0x94 +#define ixMC_IO_DEBUG_UP_149 0x95 +#define ixMC_IO_DEBUG_UP_150 0x96 +#define ixMC_IO_DEBUG_UP_151 0x97 +#define ixMC_IO_DEBUG_UP_152 0x98 +#define ixMC_IO_DEBUG_UP_153 0x99 +#define ixMC_IO_DEBUG_UP_154 0x9a +#define ixMC_IO_DEBUG_UP_155 0x9b +#define ixMC_IO_DEBUG_UP_156 0x9c +#define ixMC_IO_DEBUG_UP_157 0x9d +#define ixMC_IO_DEBUG_UP_158 0x9e +#define ixMC_IO_DEBUG_UP_159 0x9f +#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0xa0 +#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0xa1 +#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0xa2 +#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0xa3 +#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0xa4 +#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0xa5 +#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0xa6 +#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0xa7 +#define ixMC_IO_DEBUG_DBI_MISC_D0 0xa8 +#define ixMC_IO_DEBUG_EDC_MISC_D0 0xa9 +#define ixMC_IO_DEBUG_WCK_MISC_D0 0xaa +#define ixMC_IO_DEBUG_CK_MISC_D0 0xab +#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0xac +#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0xad +#define ixMC_IO_DEBUG_ACMD_MISC_D0 0xae +#define ixMC_IO_DEBUG_CMD_MISC_D0 0xaf +#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0xb0 +#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0xb1 +#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0xb2 +#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0xb3 +#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0xb4 +#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0xb5 +#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0xb6 +#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0xb7 +#define ixMC_IO_DEBUG_DBI_MISC_D1 0xb8 +#define ixMC_IO_DEBUG_EDC_MISC_D1 0xb9 +#define ixMC_IO_DEBUG_WCK_MISC_D1 0xba +#define ixMC_IO_DEBUG_CK_MISC_D1 0xbb +#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0xbc +#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0xbd +#define ixMC_IO_DEBUG_ACMD_MISC_D1 0xbe +#define ixMC_IO_DEBUG_CMD_MISC_D1 0xbf +#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0xc0 +#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0xc1 +#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0xc2 +#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0xc3 +#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0xc4 +#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0xc5 +#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0xc6 +#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0xc7 +#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0xc8 +#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0xc9 +#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0xca +#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0xcb +#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0xcc +#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0xcd +#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0xce +#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0xcf +#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0xd0 +#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0xd1 +#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0xd2 +#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0xd3 +#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0xd4 +#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0xd5 +#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0xd6 +#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0xd7 +#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0xd8 +#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0xd9 +#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0xda +#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0xdb +#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0xdc +#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0xdd +#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0xde +#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0xdf +#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0xe0 +#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0xe1 +#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0xe2 +#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0xe3 +#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0xe4 +#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0xe5 +#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0xe6 +#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0xe7 +#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0xe8 +#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0xe9 +#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0xea +#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0xeb +#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0xec +#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0xed +#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0xee +#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0xef +#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0xf0 +#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0xf1 +#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0xf2 +#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0xf3 +#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0xf4 +#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0xf5 +#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0xf6 +#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0xf7 +#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0xf8 +#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0xf9 +#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0xfa +#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0xfb +#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0xfc +#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0xfd +#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0xfe +#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0xff +#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x100 +#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x101 +#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x102 +#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x103 +#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x104 +#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x105 +#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x106 +#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x107 +#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x108 +#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x109 +#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x10a +#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x10b +#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x10c +#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x10d +#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x10e +#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x10f +#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x110 +#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x111 +#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x112 +#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x113 +#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x114 +#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x115 +#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x116 +#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x117 +#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x118 +#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x119 +#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x11a +#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x11b +#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x11c +#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x11d +#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x11e +#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x11f +#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x120 +#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x121 +#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x122 +#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x123 +#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x124 +#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125 +#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x126 +#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x127 +#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x128 +#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x129 +#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x12a +#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x12b +#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x12c +#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x12d +#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x12e +#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x12f +#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x130 +#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x131 +#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x132 +#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x133 +#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x134 +#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x135 +#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x136 +#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x137 +#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x138 +#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x139 +#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x13a +#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x13b +#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x13c +#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x13d +#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x13e +#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x13f +#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x140 +#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x141 +#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x142 +#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x143 +#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x144 +#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x145 +#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x146 +#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x147 +#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x148 +#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x149 +#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x14a +#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x14b +#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x14c +#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x14d +#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x14e +#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x14f +#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x150 +#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x151 +#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x152 +#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x153 +#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x154 +#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x155 +#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x156 +#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x157 +#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x158 +#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x159 +#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x15a +#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x15b +#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x15c +#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x15d +#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x15e +#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x15f +#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x160 +#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x161 +#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x162 +#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x163 +#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x164 +#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x165 +#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x166 +#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x167 +#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x168 +#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x169 +#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x16a +#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x16b +#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x16c +#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x16d +#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x16e +#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x16f +#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x170 +#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x171 +#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x172 +#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x173 +#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x174 +#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x175 +#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x176 +#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x177 +#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x178 +#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x179 +#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x17a +#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x17b +#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x17c +#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x17d +#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x17e +#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x17f +#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x180 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x181 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x182 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x183 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x184 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x185 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x186 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x187 +#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x188 +#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x189 +#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x18a +#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x18b +#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x18c +#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x18d +#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x18e +#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x18f +#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x190 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x191 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x192 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x193 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x194 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x195 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x196 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x197 +#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x198 +#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x199 +#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x19a +#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x19b +#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x19c +#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x19d +#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x19e +#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x19f +#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x1a0 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x1a1 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x1a2 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x1a3 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x1a4 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x1a5 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x1a6 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x1a7 +#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x1a8 +#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x1a9 +#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x1aa +#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x1ab +#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x1ac +#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x1ad +#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x1ae +#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x1af +#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x1b0 +#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x1b1 +#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x1b2 +#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x1b3 +#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x1b4 +#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x1b5 +#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x1b6 +#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x1b7 +#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x1b8 +#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x1b9 +#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x1ba +#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x1bb +#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x1bc +#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x1bd +#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x1be +#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x1bf +#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x1c0 +#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x1c1 +#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x1c2 +#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x1c3 +#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x1c4 +#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x1c5 +#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x1c6 +#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x1c7 +#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x1c8 +#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x1c9 +#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x1ca +#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x1cb +#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x1cc +#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x1cd +#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x1ce +#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x1cf +#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x1d0 +#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x1d1 +#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x1d2 +#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x1d3 +#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x1d4 +#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x1d5 +#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x1d6 +#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x1d7 +#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x1d8 +#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x1d9 +#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x1da +#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x1db +#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x1dc +#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x1dd +#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x1de +#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x1df +#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x1e0 +#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x1e1 +#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x1e2 +#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x1e3 +#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x1e4 +#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x1e5 +#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x1e6 +#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x1e7 +#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x1e8 +#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x1e9 +#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x1ea +#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x1eb +#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x1ec +#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x1f0 +#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x1f1 +#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x1f2 +#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x1f3 +#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x1f4 +#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x1f5 +#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x1f6 +#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x1f7 +#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x1f8 +#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x1f9 +#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x1fa +#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x1fb +#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x1fc +#define mmMC_SEQ_CNTL_3 0xd80 +#define mmMC_SEQ_G5PDX_CTRL 0xd81 +#define mmMC_SEQ_G5PDX_CTRL_LP 0xd82 +#define mmMC_SEQ_G5PDX_CMD0 0xd83 +#define mmMC_SEQ_G5PDX_CMD0_LP 0xd84 +#define mmMC_SEQ_G5PDX_CMD1 0xd85 +#define mmMC_SEQ_G5PDX_CMD1_LP 0xd86 +#define mmMC_SEQ_SREG_READ 0xd87 +#define mmMC_SEQ_SREG_STATUS 0xd88 +#define mmMC_SEQ_PHYREG_BCAST 0xd89 +#define mmMC_SEQ_PMG_DVS_CTL 0xd8a +#define mmMC_SEQ_PMG_DVS_CTL_LP 0xd8b +#define mmMC_SEQ_PMG_DVS_CMD 0xd8c +#define mmMC_SEQ_PMG_DVS_CMD_LP 0xd8d +#define mmMC_SEQ_DLL_STBY 0xd8e +#define mmMC_SEQ_DLL_STBY_LP 0xd8f +#define mmMC_DLB_MISCCTRL0 0xd90 +#define mmMC_DLB_MISCCTRL1 0xd91 +#define mmMC_DLB_MISCCTRL2 0xd92 +#define mmMC_DLB_CONFIG0 0xd93 +#define mmMC_DLB_CONFIG1 0xd94 +#define mmMC_DLB_SETUP 0xd95 +#define mmMC_DLB_SETUPSWEEP 0xd96 +#define mmMC_DLB_SETUPFIFO 0xd97 +#define mmMC_DLB_WRITE_MASK 0xd98 +#define mmMC_DLB_STATUS 0xd99 +#define mmMC_DLB_STATUS_MISC0 0xd9a +#define mmMC_DLB_STATUS_MISC1 0xd9b +#define mmMC_DLB_STATUS_MISC2 0xd9c +#define mmMC_DLB_STATUS_MISC3 0xd9d +#define mmMC_DLB_STATUS_MISC4 0xd9e +#define mmMC_DLB_STATUS_MISC5 0xd9f +#define mmMC_DLB_STATUS_MISC6 0xda0 +#define mmMC_DLB_STATUS_MISC7 0xda1 +#define mmMC_ARB_HARSH_EN_RD 0xdc0 +#define mmMC_ARB_HARSH_EN_WR 0xdc1 +#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2 +#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3 +#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4 +#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5 +#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6 +#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7 +#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8 +#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9 +#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca +#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb +#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc +#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd +#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce +#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf +#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0 +#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1 +#define mmMC_ARB_HARSH_SAT0_RD 0xdd2 +#define mmMC_ARB_HARSH_SAT0_WR 0xdd3 +#define mmMC_ARB_HARSH_SAT1_RD 0xdd4 +#define mmMC_ARB_HARSH_SAT1_WR 0xdd5 +#define mmMC_ARB_HARSH_CTL_RD 0xdd6 +#define mmMC_ARB_HARSH_CTL_WR 0xdd7 +#define mmMC_ARB_GRUB_PRIORITY1_RD 0xdd8 +#define mmMC_ARB_GRUB_PRIORITY1_WR 0xdd9 +#define mmMC_ARB_GRUB_PRIORITY2_RD 0xdda +#define mmMC_ARB_GRUB_PRIORITY2_WR 0xddb +#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x5e78 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x5e78 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x5eb8 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x5ef8 +#define mmMCIF_WB_BUFMGR_CUR_LINE_R 0x5e79 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x5e79 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x5eb9 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x5ef9 +#define mmMCIF_WB_BUFMGR_STATUS 0x5e7a +#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x5e7a +#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x5eba +#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x5efa +#define mmMCIF_WB_BUF_PITCH 0x5e7b +#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x5e7b +#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x5ebb +#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x5efb +#define mmMCIF_WB_BUF_1_STATUS 0x5e7c +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x5e7c +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x5ebc +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x5efc +#define mmMCIF_WB_BUF_1_STATUS2 0x5e7d +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x5e7d +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x5ebd +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x5efd +#define mmMCIF_WB_BUF_2_STATUS 0x5e7e +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x5e7e +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x5ebe +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x5efe +#define mmMCIF_WB_BUF_2_STATUS2 0x5e7f +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x5e7f +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x5ebf +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x5eff +#define mmMCIF_WB_BUF_3_STATUS 0x5e80 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x5e80 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x5ec0 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x5f00 +#define mmMCIF_WB_BUF_3_STATUS2 0x5e81 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x5e81 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x5ec1 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x5f01 +#define mmMCIF_WB_BUF_4_STATUS 0x5e82 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x5e82 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x5ec2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x5f02 +#define mmMCIF_WB_BUF_4_STATUS2 0x5e83 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x5e83 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x5ec3 +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x5f03 +#define mmMCIF_WB_ARBITRATION_CONTROL 0x5e84 +#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x5e84 +#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x5ec4 +#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x5f04 +#define mmMCIF_WB_URGENCY_WATERMARK 0x5e85 +#define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK 0x5e85 +#define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK 0x5ec5 +#define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK 0x5f05 +#define mmMCIF_WB_TEST_DEBUG_INDEX 0x5e86 +#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x5e86 +#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x5ec6 +#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x5f06 +#define mmMCIF_WB_TEST_DEBUG_DATA 0x5e87 +#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x5e87 +#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x5ec7 +#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x5f07 +#define mmMCIF_WB_BUF_1_ADDR_Y 0x5e88 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x5e88 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x5ec8 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x5f08 +#define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5ec9 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5f09 +#define mmMCIF_WB_BUF_1_ADDR_C 0x5e8a +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x5e8a +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x5eca +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x5f0a +#define mmMCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5ecb +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5f0b +#define mmMCIF_WB_BUF_2_ADDR_Y 0x5e8c +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x5e8c +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x5ecc +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x5f0c +#define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5ecd +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5f0d +#define mmMCIF_WB_BUF_2_ADDR_C 0x5e8e +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x5e8e +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x5ece +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x5f0e +#define mmMCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5ecf +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5f0f +#define mmMCIF_WB_BUF_3_ADDR_Y 0x5e90 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x5e90 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x5ed0 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x5f10 +#define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5ed1 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5f11 +#define mmMCIF_WB_BUF_3_ADDR_C 0x5e92 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x5e92 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x5ed2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x5f12 +#define mmMCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5ed3 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5f13 +#define mmMCIF_WB_BUF_4_ADDR_Y 0x5e94 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x5e94 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x5ed4 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x5f14 +#define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5ed5 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5f15 +#define mmMCIF_WB_BUF_4_ADDR_C 0x5e96 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x5e96 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x5ed6 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x5f16 +#define mmMCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5ed7 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5f17 +#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x5e98 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x5e98 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x5ed8 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x5f18 +#define mmMCIF_WB_HVVMID_CONTROL 0x5e99 +#define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL 0x5e99 +#define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL 0x5ed9 +#define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL 0x5f19 + +#endif /* GMC_8_1_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h new file mode 100644 index 000000000000..05b80f2bb147 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h @@ -0,0 +1,1198 @@ +/* + * GMC_8_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_8_1_ENUM_H +#define GMC_8_1_ENUM_H + +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_scf2 = 0x2, + DBG_CLIENT_BLKID_mcd5 = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_sx30 = 0x5, + DBG_CLIENT_BLKID_mcd2 = 0x6, + DBG_CLIENT_BLKID_bci1 = 0x7, + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, + DBG_CLIENT_BLKID_mcc0 = 0x9, + DBG_CLIENT_BLKID_uvdf_0 = 0xa, + DBG_CLIENT_BLKID_uvdf_1 = 0xb, + DBG_CLIENT_BLKID_uvdf_2 = 0xc, + DBG_CLIENT_BLKID_uvdi_0 = 0xd, + DBG_CLIENT_BLKID_bci0 = 0xe, + DBG_CLIENT_BLKID_vcec0_0 = 0xf, + DBG_CLIENT_BLKID_cb100 = 0x10, + DBG_CLIENT_BLKID_cb001 = 0x11, + DBG_CLIENT_BLKID_mcd4 = 0x12, + DBG_CLIENT_BLKID_tmonw00 = 0x13, + DBG_CLIENT_BLKID_cb101 = 0x14, + DBG_CLIENT_BLKID_sx10 = 0x15, + DBG_CLIENT_BLKID_cb301 = 0x16, + DBG_CLIENT_BLKID_tmonw01 = 0x17, + DBG_CLIENT_BLKID_vcea0_0 = 0x18, + DBG_CLIENT_BLKID_vcea0_1 = 0x19, + DBG_CLIENT_BLKID_vcea0_2 = 0x1a, + DBG_CLIENT_BLKID_vcea0_3 = 0x1b, + DBG_CLIENT_BLKID_scf1 = 0x1c, + DBG_CLIENT_BLKID_sx20 = 0x1d, + DBG_CLIENT_BLKID_spim1 = 0x1e, + DBG_CLIENT_BLKID_pa10 = 0x1f, + DBG_CLIENT_BLKID_pa00 = 0x20, + DBG_CLIENT_BLKID_gmcon = 0x21, + DBG_CLIENT_BLKID_mcb = 0x22, + DBG_CLIENT_BLKID_vgt0 = 0x23, + DBG_CLIENT_BLKID_pc0 = 0x24, + DBG_CLIENT_BLKID_bci2 = 0x25, + DBG_CLIENT_BLKID_uvdb_0 = 0x26, + DBG_CLIENT_BLKID_spim3 = 0x27, + DBG_CLIENT_BLKID_cpc_0 = 0x28, + DBG_CLIENT_BLKID_cpc_1 = 0x29, + DBG_CLIENT_BLKID_uvdm_0 = 0x2a, + DBG_CLIENT_BLKID_uvdm_1 = 0x2b, + DBG_CLIENT_BLKID_uvdm_2 = 0x2c, + DBG_CLIENT_BLKID_uvdm_3 = 0x2d, + DBG_CLIENT_BLKID_cb000 = 0x2e, + DBG_CLIENT_BLKID_spim0 = 0x2f, + DBG_CLIENT_BLKID_mcc2 = 0x30, + DBG_CLIENT_BLKID_ds0 = 0x31, + DBG_CLIENT_BLKID_srbm = 0x32, + DBG_CLIENT_BLKID_ih = 0x33, + DBG_CLIENT_BLKID_sem = 0x34, + DBG_CLIENT_BLKID_sdma_0 = 0x35, + DBG_CLIENT_BLKID_sdma_1 = 0x36, + DBG_CLIENT_BLKID_hdp = 0x37, + DBG_CLIENT_BLKID_acp_0 = 0x38, + DBG_CLIENT_BLKID_acp_1 = 0x39, + DBG_CLIENT_BLKID_cb200 = 0x3a, + DBG_CLIENT_BLKID_scf3 = 0x3b, + DBG_CLIENT_BLKID_vceb1_0 = 0x3c, + DBG_CLIENT_BLKID_vcea1_0 = 0x3d, + DBG_CLIENT_BLKID_vcea1_1 = 0x3e, + DBG_CLIENT_BLKID_vcea1_2 = 0x3f, + DBG_CLIENT_BLKID_vcea1_3 = 0x40, + DBG_CLIENT_BLKID_bci3 = 0x41, + DBG_CLIENT_BLKID_mcd0 = 0x42, + DBG_CLIENT_BLKID_pa11 = 0x43, + DBG_CLIENT_BLKID_pa01 = 0x44, + DBG_CLIENT_BLKID_cb201 = 0x45, + DBG_CLIENT_BLKID_spim2 = 0x46, + DBG_CLIENT_BLKID_vgt2 = 0x47, + DBG_CLIENT_BLKID_pc2 = 0x48, + DBG_CLIENT_BLKID_smu_0 = 0x49, + DBG_CLIENT_BLKID_smu_1 = 0x4a, + DBG_CLIENT_BLKID_smu_2 = 0x4b, + DBG_CLIENT_BLKID_cb1 = 0x4c, + DBG_CLIENT_BLKID_ia0 = 0x4d, + DBG_CLIENT_BLKID_wd = 0x4e, + DBG_CLIENT_BLKID_ia1 = 0x4f, + DBG_CLIENT_BLKID_vcec1_0 = 0x50, + DBG_CLIENT_BLKID_scf0 = 0x51, + DBG_CLIENT_BLKID_vgt1 = 0x52, + DBG_CLIENT_BLKID_pc1 = 0x53, + DBG_CLIENT_BLKID_cb0 = 0x54, + DBG_CLIENT_BLKID_gdc_one_0 = 0x55, + DBG_CLIENT_BLKID_gdc_one_1 = 0x56, + DBG_CLIENT_BLKID_gdc_one_2 = 0x57, + DBG_CLIENT_BLKID_gdc_one_3 = 0x58, + DBG_CLIENT_BLKID_gdc_one_4 = 0x59, + DBG_CLIENT_BLKID_gdc_one_5 = 0x5a, + DBG_CLIENT_BLKID_gdc_one_6 = 0x5b, + DBG_CLIENT_BLKID_gdc_one_7 = 0x5c, + DBG_CLIENT_BLKID_gdc_one_8 = 0x5d, + DBG_CLIENT_BLKID_gdc_one_9 = 0x5e, + DBG_CLIENT_BLKID_gdc_one_10 = 0x5f, + DBG_CLIENT_BLKID_gdc_one_11 = 0x60, + DBG_CLIENT_BLKID_gdc_one_12 = 0x61, + DBG_CLIENT_BLKID_gdc_one_13 = 0x62, + DBG_CLIENT_BLKID_gdc_one_14 = 0x63, + DBG_CLIENT_BLKID_gdc_one_15 = 0x64, + DBG_CLIENT_BLKID_gdc_one_16 = 0x65, + DBG_CLIENT_BLKID_gdc_one_17 = 0x66, + DBG_CLIENT_BLKID_gdc_one_18 = 0x67, + DBG_CLIENT_BLKID_gdc_one_19 = 0x68, + DBG_CLIENT_BLKID_gdc_one_20 = 0x69, + DBG_CLIENT_BLKID_gdc_one_21 = 0x6a, + DBG_CLIENT_BLKID_gdc_one_22 = 0x6b, + DBG_CLIENT_BLKID_gdc_one_23 = 0x6c, + DBG_CLIENT_BLKID_gdc_one_24 = 0x6d, + DBG_CLIENT_BLKID_gdc_one_25 = 0x6e, + DBG_CLIENT_BLKID_gdc_one_26 = 0x6f, + DBG_CLIENT_BLKID_gdc_one_27 = 0x70, + DBG_CLIENT_BLKID_gdc_one_28 = 0x71, + DBG_CLIENT_BLKID_gdc_one_29 = 0x72, + DBG_CLIENT_BLKID_gdc_one_30 = 0x73, + DBG_CLIENT_BLKID_gdc_one_31 = 0x74, + DBG_CLIENT_BLKID_gdc_one_32 = 0x75, + DBG_CLIENT_BLKID_gdc_one_33 = 0x76, + DBG_CLIENT_BLKID_gdc_one_34 = 0x77, + DBG_CLIENT_BLKID_gdc_one_35 = 0x78, + DBG_CLIENT_BLKID_vceb0_0 = 0x79, + DBG_CLIENT_BLKID_vgt3 = 0x7a, + DBG_CLIENT_BLKID_pc3 = 0x7b, + DBG_CLIENT_BLKID_mcd3 = 0x7c, + DBG_CLIENT_BLKID_uvdu_0 = 0x7d, + DBG_CLIENT_BLKID_uvdu_1 = 0x7e, + DBG_CLIENT_BLKID_uvdu_2 = 0x7f, + DBG_CLIENT_BLKID_uvdu_3 = 0x80, + DBG_CLIENT_BLKID_uvdu_4 = 0x81, + DBG_CLIENT_BLKID_uvdu_5 = 0x82, + DBG_CLIENT_BLKID_uvdu_6 = 0x83, + DBG_CLIENT_BLKID_cb300 = 0x84, + DBG_CLIENT_BLKID_mcd1 = 0x85, + DBG_CLIENT_BLKID_sx00 = 0x86, + DBG_CLIENT_BLKID_uvdc_0 = 0x87, + DBG_CLIENT_BLKID_uvdc_1 = 0x88, + DBG_CLIENT_BLKID_mcc3 = 0x89, + DBG_CLIENT_BLKID_cpg_0 = 0x8a, + DBG_CLIENT_BLKID_cpg_1 = 0x8b, + DBG_CLIENT_BLKID_gck = 0x8c, + DBG_CLIENT_BLKID_mcc1 = 0x8d, + DBG_CLIENT_BLKID_cpf_0 = 0x8e, + DBG_CLIENT_BLKID_cpf_1 = 0x8f, + DBG_CLIENT_BLKID_rlc = 0x90, + DBG_CLIENT_BLKID_grbm = 0x91, + DBG_CLIENT_BLKID_sammsp = 0x92, + DBG_CLIENT_BLKID_dci_pg = 0x93, + DBG_CLIENT_BLKID_dci_0 = 0x94, + DBG_CLIENT_BLKID_dccg0_0 = 0x95, + DBG_CLIENT_BLKID_dccg0_1 = 0x96, + DBG_CLIENT_BLKID_dcfe01_0 = 0x97, + DBG_CLIENT_BLKID_dcfe02_0 = 0x98, + DBG_CLIENT_BLKID_dcfe03_0 = 0x99, + DBG_CLIENT_BLKID_dcfe04_0 = 0x9a, + DBG_CLIENT_BLKID_dcfe05_0 = 0x9b, + DBG_CLIENT_BLKID_dcfe06_0 = 0x9c, + DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* GMC_8_1_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h new file mode 100644 index 000000000000..7d3963f36a6b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h @@ -0,0 +1,15682 @@ +/* + * GMC_8_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_8_1_SH_MASK_H +#define GMC_8_1_SH_MASK_H + +#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 +#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 +#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 +#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 +#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 +#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 +#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 +#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 +#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 +#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 +#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20 +#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5 +#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40 +#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6 +#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80 +#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7 +#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700 +#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8 +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000 +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f +#define MC_ARB_ATOMIC__TC_GRP_MASK 0x7 +#define MC_ARB_ATOMIC__TC_GRP__SHIFT 0x0 +#define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8 +#define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT 0x3 +#define MC_ARB_ATOMIC__SDMA_GRP_MASK 0x70 +#define MC_ARB_ATOMIC__SDMA_GRP__SHIFT 0x4 +#define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK 0x80 +#define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT 0x7 +#define MC_ARB_ATOMIC__OUTSTANDING_MASK 0xff00 +#define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8 +#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP_MASK 0xff0000 +#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13 +#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000 +#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16 +#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000 +#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19 +#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff +#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9 +#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400 +#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa +#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800 +#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd +#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK 0x4000 +#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe +#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK 0x8000 +#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT 0xf +#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK 0xff0000 +#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10 +#define MC_ARB_FED_CNTL__MODE_MASK 0x3 +#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0 +#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc +#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2 +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10 +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4 +#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20 +#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5 +#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40 +#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6 +#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80 +#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7 +#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1 +#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0 +#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2 +#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1 +#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4 +#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2 +#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8 +#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3 +#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10 +#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4 +#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20 +#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5 +#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40 +#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6 +#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80 +#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9 +#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400 +#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa +#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800 +#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd +#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000 +#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe +#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000 +#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11 +#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000 +#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15 +#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000 +#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19 +#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000 +#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d +#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf +#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0 +#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10 +#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4 +#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20 +#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5 +#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40 +#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6 +#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80 +#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7 +#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100 +#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8 +#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200 +#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9 +#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400 +#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa +#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800 +#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb +#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000 +#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc +#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000 +#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3 +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0 +#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4 +#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2 +#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18 +#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3 +#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20 +#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5 +#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff +#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0 +#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00 +#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8 +#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000 +#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10 +#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000 +#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18 +#define MC_ARB_PERF_CID__CH0_MASK 0xff +#define MC_ARB_PERF_CID__CH0__SHIFT 0x0 +#define MC_ARB_PERF_CID__CH1_MASK 0xff00 +#define MC_ARB_PERF_CID__CH1__SHIFT 0x8 +#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000 +#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10 +#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000 +#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11 +#define MC_ARB_SNOOP__TC_GRP_RD_MASK 0x7 +#define MC_ARB_SNOOP__TC_GRP_RD__SHIFT 0x0 +#define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK 0x8 +#define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT 0x3 +#define MC_ARB_SNOOP__TC_GRP_WR_MASK 0x70 +#define MC_ARB_SNOOP__TC_GRP_WR__SHIFT 0x4 +#define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK 0x80 +#define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT 0x7 +#define MC_ARB_SNOOP__SDMA_GRP_RD_MASK 0x700 +#define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT 0x8 +#define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK 0x800 +#define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT 0xb +#define MC_ARB_SNOOP__SDMA_GRP_WR_MASK 0x7000 +#define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT 0xc +#define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK 0x8000 +#define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT 0xf +#define MC_ARB_SNOOP__OUTSTANDING_RD_MASK 0xff0000 +#define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT 0x10 +#define MC_ARB_SNOOP__OUTSTANDING_WR_MASK 0xff000000 +#define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT 0x18 +#define MC_ARB_GRUB__GRUB_WATERMARK_MASK 0xff +#define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT 0x0 +#define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK 0xff00 +#define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT 0x8 +#define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK 0xff0000 +#define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT 0x10 +#define MC_ARB_GRUB__REG_WR_EN_MASK 0x3000000 +#define MC_ARB_GRUB__REG_WR_EN__SHIFT 0x18 +#define MC_ARB_GRUB__REG_RD_SEL_MASK 0x4000000 +#define MC_ARB_GRUB__REG_RD_SEL__SHIFT 0x1a +#define MC_ARB_GECC2__ENABLE_MASK 0x1 +#define MC_ARB_GECC2__ENABLE__SHIFT 0x0 +#define MC_ARB_GECC2__ECC_MODE_MASK 0x6 +#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1 +#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18 +#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3 +#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60 +#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5 +#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780 +#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7 +#define MC_ARB_GECC2__READ_ERR_MASK 0x3800 +#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb +#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000 +#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe +#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000 +#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf +#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000 +#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15 +#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000 +#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18 +#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf +#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0 +#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0 +#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4 +#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00 +#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8 +#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000 +#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc +#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000 +#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10 +#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000 +#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14 +#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000 +#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18 +#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000 +#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c +#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf +#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0 +#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0 +#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4 +#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00 +#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8 +#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000 +#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc +#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1 +#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0 +#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2 +#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1 +#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4 +#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2 +#define MC_ARB_MISC3__UVD_URG_MODE_MASK 0x8 +#define MC_ARB_MISC3__UVD_URG_MODE__SHIFT 0x3 +#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK 0x10 +#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT 0x4 +#define MC_ARB_MISC3__TBD_FIELD_MASK 0xffffffe0 +#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x5 +#define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK 0xff +#define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT 0x0 +#define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK 0xff00 +#define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT 0x8 +#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK 0xff0000 +#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT 0x10 +#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK 0xff000000 +#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT 0x18 +#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff +#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0 +#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1 +#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0 +#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2 +#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1 +#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc +#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2 +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10 +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4 +#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20 +#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5 +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40 +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6 +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80 +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7 +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100 +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800 +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000 +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17 +#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000 +#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18 +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000 +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5 +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0 +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6 +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000 +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc +#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000 +#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19 +#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1 +#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0 +#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e +#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1 +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80 +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7 +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000 +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa +#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800 +#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb +#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000 +#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc +#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000 +#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd +#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000 +#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe +#define MC_ARB_MISC2__GECC_MASK 0x40000 +#define MC_ARB_MISC2__GECC__SHIFT 0x12 +#define MC_ARB_MISC2__GECC_RST_MASK 0x80000 +#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13 +#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000 +#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14 +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000 +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15 +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000 +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19 +#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000 +#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c +#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000 +#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000 +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000 +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f +#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1 +#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0 +#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2 +#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1 +#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4 +#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2 +#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8 +#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3 +#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800 +#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb +#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000 +#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13 +#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000 +#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14 +#define MC_ARB_MISC__CALI_RATES_MASK 0x600000 +#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15 +#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000 +#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17 +#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000 +#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18 +#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000 +#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19 +#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000 +#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a +#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000 +#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e +#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000 +#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f +#define MC_ARB_BANKMAP__BANK0_MASK 0xf +#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0 +#define MC_ARB_BANKMAP__BANK1_MASK 0xf0 +#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4 +#define MC_ARB_BANKMAP__BANK2_MASK 0xf00 +#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8 +#define MC_ARB_BANKMAP__BANK3_MASK 0xf000 +#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc +#define MC_ARB_BANKMAP__RANK_MASK 0xf0000 +#define MC_ARB_BANKMAP__RANK__SHIFT 0x10 +#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3 +#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0 +#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4 +#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2 +#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38 +#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3 +#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0 +#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6 +#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100 +#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8 +#define MC_ARB_RAMCFG__RSV_1_MASK 0x200 +#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9 +#define MC_ARB_RAMCFG__RSV_2_MASK 0x400 +#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa +#define MC_ARB_RAMCFG__RSV_3_MASK 0x800 +#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb +#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000 +#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc +#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000 +#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd +#define MC_ARB_POP__ENABLE_ARB_MASK 0x1 +#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0 +#define MC_ARB_POP__SPEC_OPEN_MASK 0x2 +#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1 +#define MC_ARB_POP__POP_DEPTH_MASK 0x3c +#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2 +#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0 +#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6 +#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000 +#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc +#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000 +#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf +#define MC_ARB_POP__QUICK_STOP_MASK 0x20000 +#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11 +#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000 +#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12 +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000 +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13 +#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff +#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0 +#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00 +#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8 +#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000 +#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10 +#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000 +#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11 +#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff +#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0 +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100 +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8 +#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200 +#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9 +#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00 +#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa +#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000 +#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10 +#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000 +#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18 +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0 +#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0 +#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4 +#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000 +#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc +#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff +#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00 +#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000 +#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18 +#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff +#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00 +#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000 +#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18 +#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3 +#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0 +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4 +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa +#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800 +#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb +#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000 +#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc +#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000 +#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd +#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3 +#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0 +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4 +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa +#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800 +#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb +#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000 +#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc +#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000 +#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd +#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3 +#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0 +#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc +#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2 +#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30 +#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4 +#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0 +#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6 +#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300 +#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8 +#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00 +#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa +#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000 +#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc +#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000 +#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000 +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10 +#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3 +#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0 +#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc +#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2 +#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30 +#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4 +#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0 +#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6 +#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300 +#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8 +#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00 +#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa +#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000 +#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc +#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000 +#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000 +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10 +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1 +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0 +#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6 +#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1 +#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8 +#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3 +#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10 +#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4 +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1 +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0 +#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6 +#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1 +#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8 +#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3 +#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10 +#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4 +#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff +#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff +#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff +#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff +#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3 +#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc +#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2 +#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30 +#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4 +#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0 +#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6 +#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300 +#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8 +#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00 +#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa +#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000 +#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc +#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000 +#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe +#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000 +#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10 +#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000 +#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11 +#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000 +#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12 +#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000 +#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13 +#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000 +#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14 +#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000 +#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15 +#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000 +#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16 +#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000 +#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17 +#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18 +#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19 +#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a +#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b +#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c +#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d +#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e +#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f +#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3 +#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc +#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2 +#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30 +#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4 +#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0 +#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6 +#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300 +#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8 +#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00 +#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa +#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000 +#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc +#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000 +#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe +#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000 +#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10 +#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000 +#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11 +#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000 +#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12 +#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000 +#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13 +#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000 +#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14 +#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000 +#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15 +#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000 +#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16 +#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000 +#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17 +#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18 +#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19 +#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a +#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b +#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c +#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d +#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e +#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f +#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1 +#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0 +#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e +#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1 +#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0 +#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6 +#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800 +#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb +#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000 +#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc +#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000 +#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd +#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000 +#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe +#define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE_MASK 0x20000 +#define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE__SHIFT 0x11 +#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff +#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0 +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3 +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0 +#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4 +#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2 +#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8 +#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3 +#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10 +#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4 +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20 +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5 +#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40 +#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6 +#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80 +#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7 +#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300 +#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8 +#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400 +#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa +#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800 +#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb +#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000 +#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc +#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000 +#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd +#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000 +#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000 +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf +#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK 0x10000 +#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT 0x10 +#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK 0x20000 +#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT 0x11 +#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000 +#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12 +#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000 +#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13 +#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000 +#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14 +#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK 0x1000000 +#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT 0x18 +#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK 0x2000000 +#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT 0x19 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4 +#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100 +#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8 +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200 +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9 +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4 +#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100 +#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8 +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200 +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9 +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa +#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff +#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0 +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00 +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8 +#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000 +#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10 +#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000 +#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11 +#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000 +#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12 +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000 +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13 +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000 +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14 +#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000 +#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15 +#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff +#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0 +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00 +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8 +#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000 +#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10 +#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000 +#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11 +#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000 +#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12 +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000 +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13 +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000 +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14 +#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000 +#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15 +#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000 +#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18 +#define MC_ARB_LM_WR__ATOMIC_LM_EOB_MASK 0x2000000 +#define MC_ARB_LM_WR__ATOMIC_LM_EOB__SHIFT 0x19 +#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB_MASK 0x4000000 +#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB__SHIFT 0x1a +#define MC_ARB_REMREQ__RD_WATER_MASK 0xff +#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0 +#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00 +#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8 +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000 +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10 +#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000 +#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14 +#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000 +#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18 +#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1 +#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0 +#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2 +#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1 +#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4 +#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2 +#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8 +#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3 +#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10 +#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4 +#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20 +#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5 +#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40 +#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6 +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80 +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7 +#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00 +#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8 +#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000 +#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf +#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff +#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0 +#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00 +#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8 +#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000 +#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10 +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000 +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18 +#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff +#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0 +#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00 +#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8 +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000 +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10 +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000 +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18 +#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000 +#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c +#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff +#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0 +#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00 +#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8 +#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000 +#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10 +#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000 +#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13 +#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff +#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0 +#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff +#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0 +#define MC_ARB_GRUB_REALTIME_RD__CB0_MASK 0x1 +#define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT 0x0 +#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK 0x2 +#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT 0x1 +#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK 0x4 +#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT 0x2 +#define MC_ARB_GRUB_REALTIME_RD__DB0_MASK 0x8 +#define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT 0x3 +#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK 0x10 +#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT 0x4 +#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK 0x20 +#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT 0x5 +#define MC_ARB_GRUB_REALTIME_RD__TC0_MASK 0x40 +#define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT 0x6 +#define MC_ARB_GRUB_REALTIME_RD__IA_MASK 0x80 +#define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT 0x7 +#define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK 0x100 +#define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT 0x8 +#define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK 0x200 +#define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT 0x9 +#define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK 0x400 +#define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT 0xa +#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK 0x800 +#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT 0xb +#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK 0x1000 +#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT 0xc +#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK 0x2000 +#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT 0xd +#define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK 0x4000 +#define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT 0xe +#define MC_ARB_GRUB_REALTIME_RD__RLC_MASK 0x8000 +#define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT 0xf +#define MC_ARB_GRUB_REALTIME_RD__VMC_MASK 0x10000 +#define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT 0x10 +#define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK 0x20000 +#define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT 0x11 +#define MC_ARB_GRUB_REALTIME_RD__SMU_MASK 0x40000 +#define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT 0x12 +#define MC_ARB_GRUB_REALTIME_RD__VCE0_MASK 0x80000 +#define MC_ARB_GRUB_REALTIME_RD__VCE0__SHIFT 0x13 +#define MC_ARB_GRUB_REALTIME_RD__VCE1_MASK 0x100000 +#define MC_ARB_GRUB_REALTIME_RD__VCE1__SHIFT 0x14 +#define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK 0x200000 +#define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT 0x15 +#define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK 0x400000 +#define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT 0x16 +#define MC_ARB_GRUB_REALTIME_RD__HDP_MASK 0x800000 +#define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT 0x17 +#define MC_ARB_GRUB_REALTIME_RD__UMC_MASK 0x1000000 +#define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT 0x18 +#define MC_ARB_GRUB_REALTIME_RD__UVD_MASK 0x2000000 +#define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT 0x19 +#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK 0x4000000 +#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT 0x1a +#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK 0x8000000 +#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT 0x1b +#define MC_ARB_GRUB_REALTIME_RD__SEM_MASK 0x10000000 +#define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT 0x1c +#define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK 0x20000000 +#define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d +#define MC_ARB_GRUB_REALTIME_RD__VP8_MASK 0x40000000 +#define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT 0x1e +#define MC_ARB_GRUB_REALTIME_RD__ISP_MASK 0x80000000 +#define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT 0x1f +#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff +#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0 +#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00 +#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8 +#define MC_ARB_CG__RSV_0_MASK 0xff0000 +#define MC_ARB_CG__RSV_0__SHIFT 0x10 +#define MC_ARB_CG__RSV_1_MASK 0xff000000 +#define MC_ARB_CG__RSV_1__SHIFT 0x18 +#define MC_ARB_GRUB_REALTIME_WR__CB0_MASK 0x1 +#define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT 0x0 +#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK 0x2 +#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT 0x1 +#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK 0x4 +#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT 0x2 +#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK 0x8 +#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT 0x3 +#define MC_ARB_GRUB_REALTIME_WR__DB0_MASK 0x10 +#define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT 0x4 +#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK 0x20 +#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT 0x5 +#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK 0x40 +#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT 0x6 +#define MC_ARB_GRUB_REALTIME_WR__TC0_MASK 0x80 +#define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT 0x7 +#define MC_ARB_GRUB_REALTIME_WR__SH_MASK 0x100 +#define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT 0x8 +#define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK 0x200 +#define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT 0x9 +#define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK 0x400 +#define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT 0xa +#define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK 0x800 +#define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT 0xb +#define MC_ARB_GRUB_REALTIME_WR__RLC_MASK 0x1000 +#define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT 0xc +#define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK 0x2000 +#define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT 0xd +#define MC_ARB_GRUB_REALTIME_WR__SMU_MASK 0x4000 +#define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT 0xe +#define MC_ARB_GRUB_REALTIME_WR__VCE0_MASK 0x8000 +#define MC_ARB_GRUB_REALTIME_WR__VCE0__SHIFT 0xf +#define MC_ARB_GRUB_REALTIME_WR__VCE1_MASK 0x10000 +#define MC_ARB_GRUB_REALTIME_WR__VCE1__SHIFT 0x10 +#define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK 0x20000 +#define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT 0x11 +#define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK 0x40000 +#define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT 0x12 +#define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK 0x80000 +#define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT 0x13 +#define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK 0x100000 +#define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT 0x14 +#define MC_ARB_GRUB_REALTIME_WR__HDP_MASK 0x200000 +#define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT 0x15 +#define MC_ARB_GRUB_REALTIME_WR__UMC_MASK 0x400000 +#define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT 0x16 +#define MC_ARB_GRUB_REALTIME_WR__UVD_MASK 0x800000 +#define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT 0x17 +#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK 0x1000000 +#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT 0x18 +#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK 0x2000000 +#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT 0x19 +#define MC_ARB_GRUB_REALTIME_WR__XDP_MASK 0x4000000 +#define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT 0x1a +#define MC_ARB_GRUB_REALTIME_WR__SEM_MASK 0x8000000 +#define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT 0x1b +#define MC_ARB_GRUB_REALTIME_WR__IH_MASK 0x10000000 +#define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT 0x1c +#define MC_ARB_GRUB_REALTIME_WR__VP8_MASK 0x20000000 +#define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d +#define MC_ARB_GRUB_REALTIME_WR__ISP_MASK 0x40000000 +#define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT 0x1e +#define MC_ARB_GRUB_REALTIME_WR__VIN0_MASK 0x80000000 +#define MC_ARB_GRUB_REALTIME_WR__VIN0__SHIFT 0x1f +#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff +#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00 +#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000 +#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18 +#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1 +#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0 +#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2 +#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1 +#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4 +#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2 +#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8 +#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3 +#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10 +#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4 +#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20 +#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5 +#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40 +#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6 +#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80 +#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7 +#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100 +#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8 +#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200 +#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9 +#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400 +#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa +#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800 +#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb +#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000 +#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc +#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000 +#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd +#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000 +#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe +#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000 +#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf +#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000 +#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10 +#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000 +#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11 +#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000 +#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12 +#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000 +#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13 +#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000 +#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14 +#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000 +#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15 +#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000 +#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16 +#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000 +#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17 +#define MC_ARB_BUSY_STATUS__WRRET0_MASK 0x1000000 +#define MC_ARB_BUSY_STATUS__WRRET0__SHIFT 0x18 +#define MC_ARB_BUSY_STATUS__WRRET1_MASK 0x2000000 +#define MC_ARB_BUSY_STATUS__WRRET1__SHIFT 0x19 +#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000 +#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a +#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000 +#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b +#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000 +#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c +#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000 +#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d +#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000 +#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e +#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000 +#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00 +#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000 +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18 +#define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK 0xff +#define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT 0x0 +#define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK 0xff00 +#define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT 0x8 +#define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK 0x10000 +#define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT 0x10 +#define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK 0x20000 +#define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT 0x11 +#define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK 0x40000 +#define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT 0x12 +#define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK 0x80000 +#define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT 0x13 +#define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK 0x100000 +#define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT 0x14 +#define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK 0x200000 +#define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT 0x15 +#define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK 0x400000 +#define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT 0x16 +#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK 0x800000 +#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT 0x17 +#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK 0x1000000 +#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT 0x18 +#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD_MASK 0x2000000 +#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD__SHIFT 0x19 +#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD_MASK 0x4000000 +#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD__SHIFT 0x1a +#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR_MASK 0x8000000 +#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR__SHIFT 0x1b +#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR_MASK 0x10000000 +#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR__SHIFT 0x1c +#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f +#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0 +#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0 +#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5 +#define MC_ARB_BURST_TIME__TRRDS0_MASK 0x7c00 +#define MC_ARB_BURST_TIME__TRRDS0__SHIFT 0xa +#define MC_ARB_BURST_TIME__TRRDS1_MASK 0xf8000 +#define MC_ARB_BURST_TIME__TRRDS1__SHIFT 0xf +#define MC_ARB_BURST_TIME__TRRDL0_MASK 0x1f00000 +#define MC_ARB_BURST_TIME__TRRDL0__SHIFT 0x14 +#define MC_ARB_BURST_TIME__TRRDL1_MASK 0x3e000000 +#define MC_ARB_BURST_TIME__TRRDL1__SHIFT 0x19 +#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1 +#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0 +#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2 +#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1 +#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4 +#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2 +#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8 +#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3 +#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10 +#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4 +#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00 +#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8 +#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000 +#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc +#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000 +#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd +#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000 +#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf +#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000 +#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11 +#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000 +#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13 +#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000 +#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15 +#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000 +#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17 +#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000 +#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19 +#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000 +#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a +#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000 +#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b +#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000 +#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c +#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000 +#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d +#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e +#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1 +#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1 +#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 +#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2 +#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 +#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4 +#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 +#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 +#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 +#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30 +#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4 +#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0 +#define MC_CG_CONFIG__INDEX__SHIFT 0x6 +#define MC_CITF_CNTL__IGNOREPM_MASK 0x4 +#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2 +#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8 +#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3 +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30 +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4 +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40 +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6 +#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180 +#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7 +#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200 +#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9 +#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f +#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0 +#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0 +#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6 +#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff +#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00 +#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8 +#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000 +#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10 +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000 +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18 +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000 +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19 +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00 +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8 +#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000 +#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10 +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000 +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18 +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000 +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19 +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1 +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0 +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1 +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20 +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5 +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0 +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6 +#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f +#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12 +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000 +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18 +#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1 +#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0 +#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2 +#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1 +#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4 +#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2 +#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8 +#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3 +#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10 +#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4 +#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20 +#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5 +#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40 +#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6 +#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80 +#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7 +#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f +#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0 +#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000 +#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10 +#define MC_CITF_DAGB_DLY__POS_MASK 0x3f000000 +#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18 +#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf +#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0 +#define MC_RD_GRP_EXT__TC0_MASK 0xf0 +#define MC_RD_GRP_EXT__TC0__SHIFT 0x4 +#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf +#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0 +#define MC_WR_GRP_EXT__TC0_MASK 0xf0 +#define MC_WR_GRP_EXT__TC0__SHIFT 0x4 +#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f +#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0 +#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80 +#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7 +#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000 +#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe +#define MC_WR_TC0__ENABLE_MASK 0x1 +#define MC_WR_TC0__ENABLE__SHIFT 0x0 +#define MC_WR_TC0__PRESCALE_MASK 0x6 +#define MC_WR_TC0__PRESCALE__SHIFT 0x1 +#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_TC0__STALL_MODE_MASK 0x30 +#define MC_WR_TC0__STALL_MODE__SHIFT 0x4 +#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_TC0__MAX_BURST_MASK 0x780 +#define MC_WR_TC0__MAX_BURST__SHIFT 0x7 +#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800 +#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb +#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_TC1__ENABLE_MASK 0x1 +#define MC_WR_TC1__ENABLE__SHIFT 0x0 +#define MC_WR_TC1__PRESCALE_MASK 0x6 +#define MC_WR_TC1__PRESCALE__SHIFT 0x1 +#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_TC1__STALL_MODE_MASK 0x30 +#define MC_WR_TC1__STALL_MODE__SHIFT 0x4 +#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_TC1__MAX_BURST_MASK 0x780 +#define MC_WR_TC1__MAX_BURST__SHIFT 0x7 +#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800 +#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb +#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6 +#define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK 0xff +#define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT 0x0 +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000 +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18 +#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000 +#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19 +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000 +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18 +#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000 +#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19 +#define MC_RD_CB__ENABLE_MASK 0x1 +#define MC_RD_CB__ENABLE__SHIFT 0x0 +#define MC_RD_CB__PRESCALE_MASK 0x6 +#define MC_RD_CB__PRESCALE__SHIFT 0x1 +#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_CB__STALL_MODE_MASK 0x30 +#define MC_RD_CB__STALL_MODE__SHIFT 0x4 +#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_CB__MAX_BURST_MASK 0x780 +#define MC_RD_CB__MAX_BURST__SHIFT 0x7 +#define MC_RD_CB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_DB__ENABLE_MASK 0x1 +#define MC_RD_DB__ENABLE__SHIFT 0x0 +#define MC_RD_DB__PRESCALE_MASK 0x6 +#define MC_RD_DB__PRESCALE__SHIFT 0x1 +#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_DB__STALL_MODE_MASK 0x30 +#define MC_RD_DB__STALL_MODE__SHIFT 0x4 +#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_DB__MAX_BURST_MASK 0x780 +#define MC_RD_DB__MAX_BURST__SHIFT 0x7 +#define MC_RD_DB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_TC0__ENABLE_MASK 0x1 +#define MC_RD_TC0__ENABLE__SHIFT 0x0 +#define MC_RD_TC0__PRESCALE_MASK 0x6 +#define MC_RD_TC0__PRESCALE__SHIFT 0x1 +#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_TC0__STALL_MODE_MASK 0x30 +#define MC_RD_TC0__STALL_MODE__SHIFT 0x4 +#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_TC0__MAX_BURST_MASK 0x780 +#define MC_RD_TC0__MAX_BURST__SHIFT 0x7 +#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800 +#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb +#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_TC1__ENABLE_MASK 0x1 +#define MC_RD_TC1__ENABLE__SHIFT 0x0 +#define MC_RD_TC1__PRESCALE_MASK 0x6 +#define MC_RD_TC1__PRESCALE__SHIFT 0x1 +#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_TC1__STALL_MODE_MASK 0x30 +#define MC_RD_TC1__STALL_MODE__SHIFT 0x4 +#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_TC1__MAX_BURST_MASK 0x780 +#define MC_RD_TC1__MAX_BURST__SHIFT 0x7 +#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800 +#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb +#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_HUB__ENABLE_MASK 0x1 +#define MC_RD_HUB__ENABLE__SHIFT 0x0 +#define MC_RD_HUB__PRESCALE_MASK 0x6 +#define MC_RD_HUB__PRESCALE__SHIFT 0x1 +#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_HUB__STALL_MODE_MASK 0x30 +#define MC_RD_HUB__STALL_MODE__SHIFT 0x4 +#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_HUB__MAX_BURST_MASK 0x780 +#define MC_RD_HUB__MAX_BURST__SHIFT 0x7 +#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_CB__ENABLE_MASK 0x1 +#define MC_WR_CB__ENABLE__SHIFT 0x0 +#define MC_WR_CB__PRESCALE_MASK 0x6 +#define MC_WR_CB__PRESCALE__SHIFT 0x1 +#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_CB__STALL_MODE_MASK 0x30 +#define MC_WR_CB__STALL_MODE__SHIFT 0x4 +#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_CB__MAX_BURST_MASK 0x780 +#define MC_WR_CB__MAX_BURST__SHIFT 0x7 +#define MC_WR_CB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_DB__ENABLE_MASK 0x1 +#define MC_WR_DB__ENABLE__SHIFT 0x0 +#define MC_WR_DB__PRESCALE_MASK 0x6 +#define MC_WR_DB__PRESCALE__SHIFT 0x1 +#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_DB__STALL_MODE_MASK 0x30 +#define MC_WR_DB__STALL_MODE__SHIFT 0x4 +#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_DB__MAX_BURST_MASK 0x780 +#define MC_WR_DB__MAX_BURST__SHIFT 0x7 +#define MC_WR_DB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_HUB__ENABLE_MASK 0x1 +#define MC_WR_HUB__ENABLE__SHIFT 0x0 +#define MC_WR_HUB__PRESCALE_MASK 0x6 +#define MC_WR_HUB__PRESCALE__SHIFT 0x1 +#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_HUB__STALL_MODE_MASK 0x30 +#define MC_WR_HUB__STALL_MODE__SHIFT 0x4 +#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_HUB__MAX_BURST_MASK 0x780 +#define MC_WR_HUB__MAX_BURST__SHIFT 0x7 +#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff +#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00 +#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8 +#define MC_RD_GRP_LCL__CB0_MASK 0xf000 +#define MC_RD_GRP_LCL__CB0__SHIFT 0xc +#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000 +#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10 +#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000 +#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14 +#define MC_RD_GRP_LCL__DB0_MASK 0xf000000 +#define MC_RD_GRP_LCL__DB0__SHIFT 0x18 +#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000 +#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c +#define MC_WR_GRP_LCL__CB0_MASK 0xf +#define MC_WR_GRP_LCL__CB0__SHIFT 0x0 +#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0 +#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4 +#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00 +#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8 +#define MC_WR_GRP_LCL__DB0_MASK 0xf000 +#define MC_WR_GRP_LCL__DB0__SHIFT 0xc +#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000 +#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10 +#define MC_WR_GRP_LCL__SX0_MASK 0xf00000 +#define MC_WR_GRP_LCL__SX0__SHIFT 0x14 +#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000 +#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c +#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff +#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0 +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x2 +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x1 +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x4 +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x2 +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x8 +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x3 +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x10 +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x4 +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x20 +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x5 +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x40 +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x6 +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x80 +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x7 +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x100 +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x8 +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x200 +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x9 +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x400 +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xa +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x800 +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0xb +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x1000 +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0xc +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x2000 +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0xd +#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK 0x4000 +#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT 0xe +#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK 0x8000 +#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT 0xf +#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK 0x10000 +#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT 0x10 +#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK 0x20000 +#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT 0x11 +#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK 0x40000 +#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT 0x12 +#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4 +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2 +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18 +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3 +#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1 +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0 +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2 +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1 +#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK 0x4 +#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT 0x2 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x8 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x3 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x10 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x4 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x20 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x5 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x40 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x6 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK 0x80 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT 0x7 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK 0x100 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT 0x8 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x200 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x9 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x400 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0xa +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK 0x800 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT 0xb +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1000 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0xc +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2000 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0xd +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK 0x4000 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT 0xe +#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x8000 +#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xf +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x10000 +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x10 +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x20000 +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x11 +#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK 0x40000 +#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT 0x12 +#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x80000 +#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x13 +#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3 +#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0 +#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff +#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3 +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 +#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0 +#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf +#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000 +#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10 +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000 +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11 +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000 +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12 +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000 +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13 +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000 +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14 +#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000 +#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15 +#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000 +#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16 +#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK 0x800000 +#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT 0x17 +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1 +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0 +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2 +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1 +#define MC_HUB_WDP_BP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe +#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1 +#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000 +#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12 +#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1 +#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0 +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2 +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4 +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8 +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10 +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 +#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20 +#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 +#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40 +#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 +#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80 +#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 +#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100 +#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 +#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200 +#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9 +#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400 +#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa +#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800 +#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb +#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000 +#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc +#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000 +#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd +#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000 +#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe +#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000 +#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf +#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000 +#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10 +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000 +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11 +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000 +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12 +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000 +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13 +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000 +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14 +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000 +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15 +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000 +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16 +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1 +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0 +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2 +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4 +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8 +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10 +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 +#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20 +#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 +#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40 +#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 +#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80 +#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 +#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100 +#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200 +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9 +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400 +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800 +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000 +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000 +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000 +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000 +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1 +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0 +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2 +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1 +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4 +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2 +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8 +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3 +#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10 +#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4 +#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20 +#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5 +#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40 +#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6 +#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80 +#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7 +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1 +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3 +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20 +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5 +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40 +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6 +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80 +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7 +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100 +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8 +#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200 +#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9 +#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400 +#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa +#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800 +#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb +#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000 +#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000 +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd +#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000 +#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16 +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000 +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17 +#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000 +#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18 +#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000 +#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19 +#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK 0x4000000 +#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT 0x1a +#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK 0x78000000 +#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT 0x1b +#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1 +#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0 +#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe +#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1 +#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000 +#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15 +#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000 +#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16 +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000 +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000 +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff +#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00 +#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8 +#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000 +#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10 +#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000 +#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18 +#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff +#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00 +#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8 +#define MC_HUB_WDP_CREDITS2__VM2_MASK 0xff0000 +#define MC_HUB_WDP_CREDITS2__VM2__SHIFT 0x10 +#define MC_HUB_WDP_CREDITS2__VM3_MASK 0xff000000 +#define MC_HUB_WDP_CREDITS2__VM3__SHIFT 0x18 +#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf +#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0 +#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0 +#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8 +#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000 +#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG_MASK 0xfe000000 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG__SHIFT 0x19 +#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf +#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0 +#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0 +#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8 +#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000 +#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG_MASK 0xfe000000 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG__SHIFT 0x19 +#define MC_HUB_WDP_CREDITS3__STOR0_URG_MASK 0xff +#define MC_HUB_WDP_CREDITS3__STOR0_URG__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS3__STOR1_URG_MASK 0xff00 +#define MC_HUB_WDP_CREDITS3__STOR1_URG__SHIFT 0x8 +#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff +#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0 +#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00 +#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8 +#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000 +#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10 +#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000 +#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18 +#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff +#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0 +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00 +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8 +#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f +#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0 +#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000 +#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10 +#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000 +#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x100000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x14 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x200000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x15 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x400000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x16 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x800000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x17 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK 0x1000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT 0x18 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK 0x2000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT 0x19 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x4000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1a +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x8000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1b +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x10000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1c +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x20000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK 0x40000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT 0x1e +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK 0x80000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT 0x1f +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3 +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2 +#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3 +#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c +#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2 +#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe +#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1 +#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00 +#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9 +#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000 +#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11 +#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000 +#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18 +#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe +#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1 +#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00 +#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9 +#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000 +#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11 +#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000 +#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18 +#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe +#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1 +#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00 +#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9 +#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK 0x1 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT 0x0 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK 0x2 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT 0x1 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK 0x4 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT 0x2 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK 0x8 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT 0x3 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK 0x10 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT 0x4 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK 0x20 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT 0x5 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK 0x40 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT 0x6 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK 0x80 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT 0x7 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK 0x100 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT 0x8 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK 0x200 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT 0x9 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK 0x400 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT 0xa +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK 0x800 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT 0xb +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK 0x1000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT 0xc +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK 0x2000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT 0xd +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK 0x4000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT 0xe +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK 0x8000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT 0xf +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ_MASK 0x10000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ__SHIFT 0x10 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE_MASK 0x20000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE__SHIFT 0x11 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC_MASK 0x40000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC__SHIFT 0x12 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ_MASK 0x80000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ__SHIFT 0x13 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE_MASK 0x100000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE__SHIFT 0x14 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC_MASK 0x200000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC__SHIFT 0x15 +#define MC_HUB_WDP_VIN0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VIN0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VIN0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VIN0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VIN0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VIN0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VIN0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VIN0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VIN0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VIN0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VIN0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f +#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0 +#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK 0x80 +#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT 0x7 +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00 +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8 +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0 +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00 +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8 +#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VCE0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCE0__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCE0__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_TLS__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_TLS__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_TLS__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_TLS__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_TLS__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_TLS__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_TLS__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_TLS__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_TLS__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_TLS__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VCEU0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3 +#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc +#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2 +#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_VCE0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCE0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCE0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCE0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCE0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCE0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCE0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VCE0__VM_BYPASS_MASK 0x10000 +#define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000 +#define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12 +#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_IH__ENABLE_MASK 0x1 +#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1 +#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1 +#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1 +#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000 +#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000 +#define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12 +#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WDP_VCEU0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCEU0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCEU0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCEU0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCEU0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VP8__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VP8__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VP8__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VP8__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VP8__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VP8U__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VP8U__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VP8U__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VP8U__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VP8U__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VP8U__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VP8U__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VP8U__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VP8U__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VP8U__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x40000 +#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x12 +#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x80000 +#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x13 +#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x3f00000 +#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x14 +#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x40000 +#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x12 +#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x80000 +#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x13 +#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x3f00000 +#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x14 +#define MC_HUB_WDP_SAMMSP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SAMMSP__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SAMMSP__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_VP8__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VP8__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VP8__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VP8__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VP8__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VP8__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VP8__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VP8__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VP8__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_VP8U__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VP8U__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VP8U__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VP8U__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VP8U__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VP8U__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VP8U__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VP8U__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VP8U__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VP8U__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VP8U__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_SPM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_ISP_SPM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x80000 +#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x13 +#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x3f00000 +#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x14 +#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_MPS__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_ISP_MPS__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x80000 +#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x13 +#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x3f00000 +#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x14 +#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_MPM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_ISP_MPM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x80000 +#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x13 +#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x3f00000 +#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x14 +#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_CCPU__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_ISP_CCPU__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x80000 +#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x13 +#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x3f00000 +#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x14 +#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDS__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDS__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDT__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDT__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDU__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDU__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDV__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDV__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_MASK 0x1fc000 +#define MC_HUB_WDP_CREDITS_MCDW__WR_URG__SHIFT 0xe +#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_STALL_THRESHOLD_MASK 0xfe00000 +#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_STALL_THRESHOLD__SHIFT 0x15 +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_MASK 0x1fc000 +#define MC_HUB_WDP_CREDITS_MCDX__WR_URG__SHIFT 0xe +#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_STALL_THRESHOLD_MASK 0xfe00000 +#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_STALL_THRESHOLD__SHIFT 0x15 +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_MASK 0x1fc000 +#define MC_HUB_WDP_CREDITS_MCDY__WR_URG__SHIFT 0xe +#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_STALL_THRESHOLD_MASK 0xfe00000 +#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_STALL_THRESHOLD__SHIFT 0x15 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_MASK 0x1fc000 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG__SHIFT 0xe +#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_STALL_THRESHOLD_MASK 0xfe00000 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_STALL_THRESHOLD__SHIFT 0x15 +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_MASK 0x1fc000 +#define MC_HUB_WDP_CREDITS_MCDS__WR_URG__SHIFT 0xe +#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_STALL_THRESHOLD_MASK 0xfe00000 +#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_STALL_THRESHOLD__SHIFT 0x15 +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_MASK 0x1fc000 +#define MC_HUB_WDP_CREDITS_MCDT__WR_URG__SHIFT 0xe +#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_STALL_THRESHOLD_MASK 0xfe00000 +#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_STALL_THRESHOLD__SHIFT 0x15 +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_MASK 0x1fc000 +#define MC_HUB_WDP_CREDITS_MCDU__WR_URG__SHIFT 0xe +#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_STALL_THRESHOLD_MASK 0xfe00000 +#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_STALL_THRESHOLD__SHIFT 0x15 +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_MASK 0x1fc000 +#define MC_HUB_WDP_CREDITS_MCDV__WR_URG__SHIFT 0xe +#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_STALL_THRESHOLD_MASK 0xfe00000 +#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_STALL_THRESHOLD__SHIFT 0x15 +#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff +#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0 +#define MC_HUB_RDREQ_VCE1__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCE1__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCE1__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCE1__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCE1__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCE1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCE1__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCE1__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCE1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCE1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCE1__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_VCE1__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_VCEU1__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCEU1__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCEU1__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCEU1__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCEU1__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCEU1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCEU1__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCEU1__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_VCE1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCE1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCE1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCE1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCE1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCE1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCE1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCE1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCE1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCE1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCE1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VCE1__VM_BYPASS_MASK 0x10000 +#define MC_HUB_WDP_VCE1__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_VCE1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000 +#define MC_HUB_WDP_VCE1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12 +#define MC_HUB_WDP_VCEU1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCEU1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCEU1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCEU1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCEU1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCEU1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCEU1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCEU1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCEU1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCEU1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_VCEU1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_VCEU1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000 +#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000 +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10 +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000 +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11 +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0 +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00 +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8 +#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000 +#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14 +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00 +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1 +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0 +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6 +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1 +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78 +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3 +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80 +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100 +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8 +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600 +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9 +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800 +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb +#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000 +#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300 +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8 +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00 +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10 +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0 +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1 +#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e +#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000 +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 +#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1 +#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0 +#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6 +#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1 +#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8 +#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3 +#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0 +#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4 +#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00 +#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8 +#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000 +#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10 +#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000 +#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18 +#define MC_RPB_TCI_CNTL2__TCI_POLICY_MASK 0x1 +#define MC_RPB_TCI_CNTL2__TCI_POLICY__SHIFT 0x0 +#define MC_RPB_TCI_CNTL2__TCI_MTYPE_MASK 0x6 +#define MC_RPB_TCI_CNTL2__TCI_MTYPE__SHIFT 0x1 +#define MC_RPB_TCI_CNTL2__TCI_SNOOP_MASK 0x8 +#define MC_RPB_TCI_CNTL2__TCI_SNOOP__SHIFT 0x3 +#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL_MASK 0x10 +#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL__SHIFT 0x4 +#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN_MASK 0x20 +#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN__SHIFT 0x5 +#define MC_RPB_TCI_CNTL2__TCI_EXE_MASK 0x40 +#define MC_RPB_TCI_CNTL2__TCI_EXE__SHIFT 0x6 +#define MC_SHARED_CHMAP__CHAN0_MASK 0xf +#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0 +#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0 +#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4 +#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00 +#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8 +#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000 +#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc +#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000 +#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10 +#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000 +#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14 +#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf +#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0 +#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0 +#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4 +#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00 +#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8 +#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000 +#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc +#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000 +#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10 +#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000 +#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14 +#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000 +#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18 +#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000 +#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c +#define MC_RD_GRP_GFX__CP_MASK 0xf +#define MC_RD_GRP_GFX__CP__SHIFT 0x0 +#define MC_RD_GRP_GFX__SH_MASK 0xf0 +#define MC_RD_GRP_GFX__SH__SHIFT 0x4 +#define MC_RD_GRP_GFX__TLS_MASK 0xf00 +#define MC_RD_GRP_GFX__TLS__SHIFT 0x8 +#define MC_RD_GRP_GFX__ACPG_MASK 0xf000 +#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc +#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000 +#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10 +#define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000 +#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14 +#define MC_RD_GRP_GFX__ISP_MASK 0xf000000 +#define MC_RD_GRP_GFX__ISP__SHIFT 0x18 +#define MC_RD_GRP_GFX__VP8_MASK 0xf0000000 +#define MC_RD_GRP_GFX__VP8__SHIFT 0x1c +#define MC_WR_GRP_GFX__VIN0_MASK 0xf +#define MC_WR_GRP_GFX__VIN0__SHIFT 0x0 +#define MC_WR_GRP_GFX__SH_MASK 0xf0 +#define MC_WR_GRP_GFX__SH__SHIFT 0x4 +#define MC_WR_GRP_GFX__ACPG_MASK 0xf00 +#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8 +#define MC_WR_GRP_GFX__ACPO_MASK 0xf000 +#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc +#define MC_WR_GRP_GFX__ISP_MASK 0xf0000 +#define MC_WR_GRP_GFX__ISP__SHIFT 0x10 +#define MC_WR_GRP_GFX__VP8_MASK 0xf00000 +#define MC_WR_GRP_GFX__VP8__SHIFT 0x14 +#define MC_WR_GRP_GFX__XDMA_MASK 0xf000000 +#define MC_WR_GRP_GFX__XDMA__SHIFT 0x18 +#define MC_WR_GRP_GFX__XDMAM_MASK 0xf0000000 +#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x1c +#define MC_RD_GRP_SYS__RLC_MASK 0xf +#define MC_RD_GRP_SYS__RLC__SHIFT 0x0 +#define MC_RD_GRP_SYS__VMC_MASK 0xf0 +#define MC_RD_GRP_SYS__VMC__SHIFT 0x4 +#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00 +#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8 +#define MC_RD_GRP_SYS__DMIF_MASK 0xf000 +#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc +#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000 +#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10 +#define MC_RD_GRP_SYS__SMU_MASK 0xf00000 +#define MC_RD_GRP_SYS__SMU__SHIFT 0x14 +#define MC_RD_GRP_SYS__VCE0_MASK 0xf000000 +#define MC_RD_GRP_SYS__VCE0__SHIFT 0x18 +#define MC_RD_GRP_SYS__VCE1_MASK 0xf0000000 +#define MC_RD_GRP_SYS__VCE1__SHIFT 0x1c +#define MC_WR_GRP_SYS__IH_MASK 0xf +#define MC_WR_GRP_SYS__IH__SHIFT 0x0 +#define MC_WR_GRP_SYS__MCIF_MASK 0xf0 +#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4 +#define MC_WR_GRP_SYS__RLC_MASK 0xf00 +#define MC_WR_GRP_SYS__RLC__SHIFT 0x8 +#define MC_WR_GRP_SYS__SAMMSP_MASK 0xf000 +#define MC_WR_GRP_SYS__SAMMSP__SHIFT 0xc +#define MC_WR_GRP_SYS__SMU_MASK 0xf0000 +#define MC_WR_GRP_SYS__SMU__SHIFT 0x10 +#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000 +#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14 +#define MC_WR_GRP_SYS__VCE0_MASK 0xf000000 +#define MC_WR_GRP_SYS__VCE0__SHIFT 0x18 +#define MC_WR_GRP_SYS__VCE1_MASK 0xf0000000 +#define MC_WR_GRP_SYS__VCE1__SHIFT 0x1c +#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf +#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0 +#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0 +#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4 +#define MC_RD_GRP_OTH__HDP_MASK 0xf00 +#define MC_RD_GRP_OTH__HDP__SHIFT 0x8 +#define MC_RD_GRP_OTH__SEM_MASK 0xf000 +#define MC_RD_GRP_OTH__SEM__SHIFT 0xc +#define MC_RD_GRP_OTH__UMC_MASK 0xf0000 +#define MC_RD_GRP_OTH__UMC__SHIFT 0x10 +#define MC_RD_GRP_OTH__UVD_MASK 0xf00000 +#define MC_RD_GRP_OTH__UVD__SHIFT 0x14 +#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000 +#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18 +#define MC_RD_GRP_OTH__SAMMSP_MASK 0xf0000000 +#define MC_RD_GRP_OTH__SAMMSP__SHIFT 0x1c +#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf +#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0 +#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0 +#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4 +#define MC_WR_GRP_OTH__HDP_MASK 0xf00 +#define MC_WR_GRP_OTH__HDP__SHIFT 0x8 +#define MC_WR_GRP_OTH__SEM_MASK 0xf000 +#define MC_WR_GRP_OTH__SEM__SHIFT 0xc +#define MC_WR_GRP_OTH__UMC_MASK 0xf0000 +#define MC_WR_GRP_OTH__UMC__SHIFT 0x10 +#define MC_WR_GRP_OTH__UVD_MASK 0xf00000 +#define MC_WR_GRP_OTH__UVD__SHIFT 0x14 +#define MC_WR_GRP_OTH__XDP_MASK 0xf000000 +#define MC_WR_GRP_OTH__XDP__SHIFT 0x18 +#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000 +#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c +#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff +#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0 +#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000 +#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10 +#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff +#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff +#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff +#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9 +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff +#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3 +#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf +#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0 +#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0 +#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4 +#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00 +#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8 +#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000 +#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc +#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000 +#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10 +#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000 +#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14 +#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000 +#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18 +#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000 +#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c +#define MC_SHARED_VF_ENABLE__VF_ENABLE_MASK 0x1 +#define MC_SHARED_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0xffff +#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0xf +#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000 +#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 +#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 +#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 +#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 +#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 +#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 +#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 +#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 +#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 +#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 +#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 +#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 +#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40 +#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6 +#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80 +#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7 +#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 +#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 +#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800 +#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb +#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000 +#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc +#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000 +#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000 +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 +#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40 +#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6 +#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80 +#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb +#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000 +#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd +#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f +#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0 +#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE_MASK 0x8 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE__SHIFT 0x3 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM_MASK 0xff0 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM__SHIFT 0x4 +#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH_MASK 0x1000 +#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH__SHIFT 0xc +#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN_MASK 0x2000 +#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN__SHIFT 0xd +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff +#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00 +#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8 +#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000 +#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10 +#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000 +#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11 +#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000 +#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19 +#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff +#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0 +#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00 +#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa +#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000 +#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14 +#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000 +#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0 +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0 +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6 +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000 +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0 +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0 +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6 +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000 +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc +#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff +#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000 +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000 +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 +#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff +#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0 +#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000 +#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10 +#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000 +#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12 +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 +#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30 +#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40 +#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 +#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80 +#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100 +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200 +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400 +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa +#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800 +#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000 +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc +#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff +#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff +#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00 +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8 +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000 +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00 +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 +#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2 +#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f +#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0 +#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0 +#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6 +#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000 +#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc +#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000 +#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12 +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000 +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 +#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00 +#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 +#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000 +#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000 +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000 +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000 +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000 +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 +#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00 +#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000 +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000 +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 +#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000 +#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 +#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000 +#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000 +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1 +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000 +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000 +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 +#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000 +#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000 +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1 +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2 +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4 +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8 +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10 +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20 +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40 +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80 +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100 +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200 +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 +#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400 +#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa +#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800 +#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb +#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000 +#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc +#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000 +#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd +#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000 +#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe +#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000 +#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf +#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000 +#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 +#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000 +#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 +#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000 +#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 +#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000 +#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0 +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000 +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc +#define MC_XPB_STICKY__BITS_MASK 0xffffffff +#define MC_XPB_STICKY__BITS__SHIFT 0x0 +#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff +#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0 +#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff +#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 +#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00 +#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 +#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000 +#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 +#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000 +#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 +#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000 +#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f +#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff +#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00 +#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8 +#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000 +#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10 +#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000 +#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11 +#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000 +#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19 +#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1 +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0 +#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2 +#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4 +#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3 +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1 +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0 +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2 +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1 +#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000 +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3 +#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0 +#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc +#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2 +#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30 +#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4 +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1 +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0 +#define MC_XBAR_TWOCHAN__CH0_MASK 0x6 +#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1 +#define MC_XBAR_TWOCHAN__CH1_MASK 0x18 +#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3 +#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1 +#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0 +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2 +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1 +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4 +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2 +#define MC_XBAR_ARB__ACP_RDRET_URG_MASK 0x8 +#define MC_XBAR_ARB__ACP_RDRET_URG__SHIFT 0x3 +#define MC_XBAR_ARB__HDP_RDRET_URG_MASK 0x10 +#define MC_XBAR_ARB__HDP_RDRET_URG__SHIFT 0x4 +#define MC_XBAR_ARB__BREAK_BURST_BY_URG_MASK 0x20 +#define MC_XBAR_ARB__BREAK_BURST_BY_URG__SHIFT 0x5 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c +#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH_MASK 0xfff +#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH_MASK 0xfff000 +#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH__SHIFT 0xc +#define MC_XBAR_FIFO_MON_CNTL0__START_MODE_MASK 0x3000000 +#define MC_XBAR_FIFO_MON_CNTL0__START_MODE__SHIFT 0x18 +#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE_MASK 0xc000000 +#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE__SHIFT 0x1a +#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 +#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c +#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff +#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID_MASK 0xff00 +#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID__SHIFT 0x8 +#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000 +#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10 +#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID_MASK 0xff +#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID_MASK 0xff00 +#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID__SHIFT 0x8 +#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID_MASK 0xff0000 +#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID__SHIFT 0x10 +#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID_MASK 0xff000000 +#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID__SHIFT 0x18 +#define MC_XBAR_FIFO_MON_RSLT0__COUNT_MASK 0xffffffff +#define MC_XBAR_FIFO_MON_RSLT0__COUNT__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_RSLT1__COUNT_MASK 0xffffffff +#define MC_XBAR_FIFO_MON_RSLT1__COUNT__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_RSLT2__COUNT_MASK 0xffffffff +#define MC_XBAR_FIFO_MON_RSLT2__COUNT__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_RSLT3__COUNT_MASK 0xffffffff +#define MC_XBAR_FIFO_MON_RSLT3__COUNT__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON0_MASK 0xff +#define MC_XBAR_FIFO_MON_MAX_THSH__MON0__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON1_MASK 0xff00 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON1__SHIFT 0x8 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON2_MASK 0xff0000 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON2__SHIFT 0x10 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON3_MASK 0xff000000 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON3__SHIFT 0x18 +#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff +#define MC_XBAR_SPARE0__BIT__SHIFT 0x0 +#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff +#define MC_XBAR_SPARE1__BIT__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3 +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3 +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 +#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1 +#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 +#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2 +#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 +#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4 +#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 +#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00 +#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 +#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000 +#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10 +#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1 +#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0 +#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2 +#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1 +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4 +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2 +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20 +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5 +#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40 +#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6 +#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80 +#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7 +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100 +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8 +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200 +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9 +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00 +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000 +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe +#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000 +#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000 +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10 +#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000 +#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11 +#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000 +#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12 +#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING_MASK 0x80000 +#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING__SHIFT 0x13 +#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH_MASK 0x100000 +#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH__SHIFT 0x14 +#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT_MASK 0x200000 +#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__SHIFT 0x15 +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0 +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100 +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8 +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000 +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10 +#define ATC_ATS_STATUS__BUSY_MASK 0x1 +#define ATC_ATS_STATUS__BUSY__SHIFT 0x0 +#define ATC_ATS_STATUS__CRASHED_MASK 0x2 +#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x1ff +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x7fc00 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1ff00000 +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x1ff +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00 +#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xfffffff +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1 +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x1 +#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x3e +#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 +#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID_MASK 0x1fe00 +#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID__SHIFT 0x9 +#define ATC_MISC_CG__OFFDLY_MASK 0xfc0 +#define ATC_MISC_CG__OFFDLY__SHIFT 0x6 +#define ATC_MISC_CG__ENABLE_MASK 0x40000 +#define ATC_MISC_CG__ENABLE__SHIFT 0x12 +#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000 +#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9 +#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f +#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00 +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000 +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf +#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f +#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0 +#define ATC_L2_DEBUG__L2_MEM_SELECT_MASK 0x80 +#define ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT 0x7 +#define ATC_L2_DEBUG__CACHE_INDEX_MASK 0xfff00 +#define ATC_L2_DEBUG__CACHE_INDEX__SHIFT 0x8 +#define ATC_L2_DEBUG__CACHE_SELECT_MASK 0x1000000 +#define ATC_L2_DEBUG__CACHE_SELECT__SHIFT 0x18 +#define ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK 0x2000000 +#define ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT 0x19 +#define ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK 0x8000000 +#define ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT 0x1b +#define ATC_L2_DEBUG__CACHE_READ_MASK 0x20000000 +#define ATC_L2_DEBUG__CACHE_READ__SHIFT 0x1d +#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK 0x40000000 +#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT 0x1e +#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK 0x80000000 +#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT 0x1f +#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f +#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0 +#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0 +#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5 +#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100 +#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8 +#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200 +#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9 +#define ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK 0x400 +#define ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT 0xa +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK 0x800 +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT 0xb +#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000 +#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe +#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000 +#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf +#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000 +#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11 +#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK 0x780000 +#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT 0x13 +#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD_MASK 0x7f800000 +#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD__SHIFT 0x17 +#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK 0x80000000 +#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT 0x1f +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x1 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x2 +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x1fffffc +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x1e000000 +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x19 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xffffffff +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW_MASK 0xfffffff +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3 +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0 +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4 +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2 +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10 +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4 +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0 +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 +#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 +#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e +#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 +#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 +#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 +#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e +#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 +#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f +#define ATC_L1RD_STATUS__BUSY_MASK 0x1 +#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0 +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2 +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 +#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100 +#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8 +#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000 +#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc +#define ATC_L1RD_STATUS__CAM_INDEX_MASK 0x3e0000 +#define ATC_L1RD_STATUS__CAM_INDEX__SHIFT 0x11 +#define ATC_L1WR_STATUS__BUSY_MASK 0x1 +#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0 +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2 +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 +#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100 +#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8 +#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000 +#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc +#define ATC_L1WR_STATUS__CAM_INDEX_MASK 0x3e0000 +#define ATC_L1WR_STATUS__CAM_INDEX__SHIFT 0x11 +#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff +#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0 +#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000 +#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe +#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000 +#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10 +#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000 +#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11 +#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000 +#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12 +#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000 +#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13 +#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff +#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0 +#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000 +#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe +#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000 +#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10 +#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000 +#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11 +#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000 +#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12 +#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000 +#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf +#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x1 +#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 +#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x2 +#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 +#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x4 +#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 +#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x8 +#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 +#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x10 +#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 +#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x20 +#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 +#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x40 +#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 +#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x80 +#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 +#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x100 +#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 +#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x200 +#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 +#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x400 +#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa +#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x800 +#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb +#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x1000 +#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc +#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x2000 +#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd +#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x4000 +#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe +#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x8000 +#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf +#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN_MASK 0x1 +#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN__SHIFT 0x0 +#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING_MASK 0x7f +#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING__SHIFT 0x0 +#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER_MASK 0x80 +#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER__SHIFT 0x7 +#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD_MASK 0x1f00 +#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD__SHIFT 0x8 +#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION_MASK 0x2000 +#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION__SHIFT 0xd +#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST_MASK 0x1c000 +#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0xe +#define ATC_L2_STATUS__BUSY_MASK 0x1 +#define ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3ffffffe +#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 +#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE_MASK 0x7 +#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE__SHIFT 0x0 +#define ATC_L2_STATUS2__PARITY_ERROR_INFO_MASK 0x7f8 +#define ATC_L2_STATUS2__PARITY_ERROR_INFO__SHIFT 0x3 +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16 +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400 +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800 +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000 +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc +#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000 +#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10 +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000 +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11 +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000 +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13 +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000 +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15 +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000 +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16 +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000 +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17 +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000 +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18 +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000 +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19 +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000 +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a +#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000 +#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000 +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000 +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f +#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f +#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0 +#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0 +#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6 +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800 +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb +#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000 +#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11 +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000 +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000 +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e +#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000 +#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff +#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0 +#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000 +#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc +#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000 +#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18 +#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000 +#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c +#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000 +#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d +#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000 +#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e +#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000 +#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0 +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6 +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000 +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc +#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000 +#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12 +#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000 +#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19 +#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff +#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0 +#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff +#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0 +#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff +#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 +#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200 +#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400 +#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800 +#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000 +#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000 +#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd +#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000 +#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 +#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff +#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0 +#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff +#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0 +#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000 +#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18 +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000 +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c +#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff +#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0 +#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00 +#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8 +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000 +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 +#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000 +#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c +#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000 +#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d +#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000 +#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3 +#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0 +#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4 +#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff +#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0 +#define GMCON_DEBUG__GFX_STALL_MASK 0x1 +#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0 +#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2 +#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1 +#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0_MASK 0x4 +#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0__SHIFT 0x2 +#define GMCON_DEBUG__SR_COMMIT_STATE_MASK 0x8 +#define GMCON_DEBUG__SR_COMMIT_STATE__SHIFT 0x3 +#define GMCON_DEBUG__STCTRL_ST_MASK 0xf0 +#define GMCON_DEBUG__STCTRL_ST__SHIFT 0x4 +#define GMCON_DEBUG__MISC_FLAGS_MASK 0xffffff00 +#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x8 +#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1 +#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800 +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000 +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000 +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000 +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000 +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000 +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1 +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000 +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000 +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f +#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000 +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000 +#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define VM_L2_STATUS__L2_BUSY_MASK 0x1 +#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2 +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1 +#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0 +#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2 +#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1 +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4 +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2 +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8 +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3 +#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10 +#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4 +#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20 +#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5 +#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40 +#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d +#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff +#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff +#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB_MASK 0x40000 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB__SHIFT 0x12 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB_MASK 0x80000 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB__SHIFT 0x13 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_DEBUG__FLAGS_MASK 0xffffffff +#define VM_DEBUG__FLAGS__SHIFT 0x0 +#define VM_L2_CG__OFFDLY_MASK 0xfc0 +#define VM_L2_CG__OFFDLY__SHIFT 0x6 +#define VM_L2_CG__ENABLE_MASK 0x40000 +#define VM_L2_CG__ENABLE__SHIFT 0x12 +#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000 +#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define VM_L2_CG__OVERRIDE_MASK 0x100000 +#define VM_L2_CG__OVERRIDE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0 +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0xff +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0 +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x3f +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x40 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x80 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x100 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x200 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x400 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x800 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x1000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x2000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x4000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x8000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x10000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x20000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 +#define VM_L2_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x40000 +#define VM_L2_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x1ff +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x100000 +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x1ff +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x100000 +#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000 +#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xffffffff +#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xffffffff +#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x800000 +#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x8 +#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xff800000 +#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x1 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xff800000 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0xff +#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3fffffff +#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0 +#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000 +#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xfffff000 +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xfffff000 +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xfffff000 +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xfffff000 +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0xfffff +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0xfffff +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0xfffff +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0xfffff +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x1 +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x2 +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xfffff000 +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x1 +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x2 +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xfffff000 +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x1 +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x2 +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xfffff000 +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x1 +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x2 +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xfffff000 +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0xfffff +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0xfffff +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0xfffff +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0xfffff +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xfffff000 +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xfffff000 +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xfffff000 +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xfffff000 +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0xfffff +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0xfffff +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0xfffff +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0xfffff +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 +#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS_MASK 0x1 +#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK 0x1ff +#define MC_VM_MB_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_CNTL0__EN_MASK 0x1000 +#define MC_VM_MB_L1_TLS0_CNTL0__EN__SHIFT 0xc +#define MC_VM_MB_L1_TLS0_CNTL0__PREFETCH_DONE_MASK 0x2000 +#define MC_VM_MB_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT 0xd +#define MC_VM_MB_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK 0x1ff +#define MC_VM_MB_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_CNTL1__EN_MASK 0x1000 +#define MC_VM_MB_L1_TLS0_CNTL1__EN__SHIFT 0xc +#define MC_VM_MB_L1_TLS0_CNTL1__PREFETCH_DONE_MASK 0x2000 +#define MC_VM_MB_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT 0xd +#define MC_VM_MB_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK 0x1ff +#define MC_VM_MB_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_CNTL2__EN_MASK 0x1000 +#define MC_VM_MB_L1_TLS0_CNTL2__EN__SHIFT 0xc +#define MC_VM_MB_L1_TLS0_CNTL2__PREFETCH_DONE_MASK 0x2000 +#define MC_VM_MB_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT 0xd +#define MC_VM_MB_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK 0x1ff +#define MC_VM_MB_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_CNTL3__EN_MASK 0x1000 +#define MC_VM_MB_L1_TLS0_CNTL3__EN__SHIFT 0xc +#define MC_VM_MB_L1_TLS0_CNTL3__PREFETCH_DONE_MASK 0x2000 +#define MC_VM_MB_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT 0xd +#define MC_VM_MB_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK 0x1ff +#define MC_VM_MB_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_CNTL4__EN_MASK 0x1000 +#define MC_VM_MB_L1_TLS0_CNTL4__EN__SHIFT 0xc +#define MC_VM_MB_L1_TLS0_CNTL4__PREFETCH_DONE_MASK 0x2000 +#define MC_VM_MB_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT 0xd +#define MC_VM_MB_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK 0x1ff +#define MC_VM_MB_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_CNTL5__EN_MASK 0x1000 +#define MC_VM_MB_L1_TLS0_CNTL5__EN__SHIFT 0xc +#define MC_VM_MB_L1_TLS0_CNTL5__PREFETCH_DONE_MASK 0x2000 +#define MC_VM_MB_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT 0xd +#define MC_VM_MB_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK 0x1ff +#define MC_VM_MB_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_CNTL6__EN_MASK 0x1000 +#define MC_VM_MB_L1_TLS0_CNTL6__EN__SHIFT 0xc +#define MC_VM_MB_L1_TLS0_CNTL6__PREFETCH_DONE_MASK 0x2000 +#define MC_VM_MB_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT 0xd +#define MC_VM_MB_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK 0x1ff +#define MC_VM_MB_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_CNTL7__EN_MASK 0x1000 +#define MC_VM_MB_L1_TLS0_CNTL7__EN__SHIFT 0xc +#define MC_VM_MB_L1_TLS0_CNTL7__PREFETCH_DONE_MASK 0x2000 +#define MC_VM_MB_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT 0xd +#define MC_VM_MB_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK 0x1ff +#define MC_VM_MB_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_CNTL8__EN_MASK 0x1000 +#define MC_VM_MB_L1_TLS0_CNTL8__EN__SHIFT 0xc +#define MC_VM_MB_L1_TLS0_CNTL8__PREFETCH_DONE_MASK 0x2000 +#define MC_VM_MB_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT 0xd +#define MC_VM_MB_L1_TLS0_START_ADDR0__START_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_START_ADDR0__START_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_START_ADDR1__START_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_START_ADDR1__START_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_START_ADDR2__START_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_START_ADDR2__START_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_START_ADDR3__START_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_START_ADDR3__START_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_START_ADDR4__START_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_START_ADDR4__START_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_START_ADDR5__START_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_START_ADDR5__START_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_START_ADDR6__START_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_START_ADDR6__START_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_START_ADDR7__START_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_START_ADDR7__START_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_START_ADDR8__START_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_START_ADDR8__START_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_END_ADDR0__END_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_END_ADDR0__END_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_END_ADDR1__END_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_END_ADDR1__END_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_END_ADDR2__END_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_END_ADDR2__END_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_END_ADDR3__END_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_END_ADDR3__END_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_END_ADDR4__END_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_END_ADDR4__END_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_END_ADDR5__END_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_END_ADDR5__END_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_END_ADDR6__END_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_END_ADDR6__END_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_END_ADDR7__END_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_END_ADDR7__END_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_END_ADDR8__END_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_END_ADDR8__END_ADDR__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000 +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000 +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff +#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x3 +#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x0 +#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0xc +#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x2 +#define MC_SEQ_CNTL__SAFE_MODE_MASK 0x30 +#define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x4 +#define MC_SEQ_CNTL__DAT_INV_MASK 0x40 +#define MC_SEQ_CNTL__DAT_INV__SHIFT 0x6 +#define MC_SEQ_CNTL__MSK_DF1_MASK 0x80 +#define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x7 +#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x300 +#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x8 +#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x4000 +#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0xe +#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x8000 +#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0xf +#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x10000 +#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x10 +#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x20000 +#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x11 +#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x40000 +#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x12 +#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x80000 +#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x13 +#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0xf00000 +#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x14 +#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0xf000000 +#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x18 +#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000 +#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x1c +#define MC_SEQ_CNTL_2__DRST_PDRV_MASK 0xf +#define MC_SEQ_CNTL_2__DRST_PDRV__SHIFT 0x0 +#define MC_SEQ_CNTL_2__DRST_PU_MASK 0x10 +#define MC_SEQ_CNTL_2__DRST_PU__SHIFT 0x4 +#define MC_SEQ_CNTL_2__DRST_PD_MASK 0x20 +#define MC_SEQ_CNTL_2__DRST_PD__SHIFT 0x5 +#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x300 +#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x8 +#define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0xfc00 +#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0xa +#define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x3f0000 +#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x10 +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x400000 +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x16 +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x800000 +#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x17 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0xf000000 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x18 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000 +#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x1c +#define MC_SEQ_DRAM__ADR_2CK_MASK 0x1 +#define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x0 +#define MC_SEQ_DRAM__ADR_MUX_MASK 0x2 +#define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x1 +#define MC_SEQ_DRAM__ADR_DF1_MASK 0x4 +#define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x2 +#define MC_SEQ_DRAM__AP8_MASK 0x8 +#define MC_SEQ_DRAM__AP8__SHIFT 0x3 +#define MC_SEQ_DRAM__DAT_DF1_MASK 0x10 +#define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x4 +#define MC_SEQ_DRAM__DQS_DF1_MASK 0x20 +#define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x5 +#define MC_SEQ_DRAM__DQM_DF1_MASK 0x40 +#define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x6 +#define MC_SEQ_DRAM__DQM_ACT_MASK 0x80 +#define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x7 +#define MC_SEQ_DRAM__STB_CNT_MASK 0xf00 +#define MC_SEQ_DRAM__STB_CNT__SHIFT 0x8 +#define MC_SEQ_DRAM__CKE_DYN_MASK 0x1000 +#define MC_SEQ_DRAM__CKE_DYN__SHIFT 0xc +#define MC_SEQ_DRAM__CKE_ACT_MASK 0x2000 +#define MC_SEQ_DRAM__CKE_ACT__SHIFT 0xd +#define MC_SEQ_DRAM__BO4_MASK 0x4000 +#define MC_SEQ_DRAM__BO4__SHIFT 0xe +#define MC_SEQ_DRAM__DLL_CLR_MASK 0x8000 +#define MC_SEQ_DRAM__DLL_CLR__SHIFT 0xf +#define MC_SEQ_DRAM__DLL_CNT_MASK 0xff0000 +#define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x10 +#define MC_SEQ_DRAM__DAT_INV_MASK 0x1000000 +#define MC_SEQ_DRAM__DAT_INV__SHIFT 0x18 +#define MC_SEQ_DRAM__INV_ACM_MASK 0x2000000 +#define MC_SEQ_DRAM__INV_ACM__SHIFT 0x19 +#define MC_SEQ_DRAM__ODT_ENB_MASK 0x4000000 +#define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x1a +#define MC_SEQ_DRAM__ODT_ACT_MASK 0x8000000 +#define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x1b +#define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000 +#define MC_SEQ_DRAM__RST_CTL__SHIFT 0x1c +#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000 +#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x1d +#define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000 +#define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x1e +#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS_MASK 0x80000000 +#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS__SHIFT 0x1f +#define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x1 +#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x0 +#define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x2 +#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x1 +#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x4 +#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x2 +#define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x8 +#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x3 +#define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x10 +#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x4 +#define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x20 +#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x5 +#define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x40 +#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x6 +#define MC_SEQ_DRAM_2__DQM_EST_MASK 0x80 +#define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x7 +#define MC_SEQ_DRAM_2__RD_DQS_MASK 0x100 +#define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x8 +#define MC_SEQ_DRAM_2__WR_DQS_MASK 0x200 +#define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x9 +#define MC_SEQ_DRAM_2__PLL_EST_MASK 0x400 +#define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0xa +#define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x800 +#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0xb +#define MC_SEQ_DRAM_2__DLL_EST_MASK 0x1000 +#define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0xc +#define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x2000 +#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0xd +#define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x4000 +#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0xe +#define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x8000 +#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0xf +#define MC_SEQ_DRAM_2__PLL_CNT_MASK 0xff0000 +#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x10 +#define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x1000000 +#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x18 +#define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x2000000 +#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x19 +#define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x4000000 +#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x1a +#define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x8000000 +#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x1b +#define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000 +#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x1c +#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000 +#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x1d +#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000 +#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x1e +#define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000 +#define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x1f +#define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x1f +#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x0 +#define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x3e0 +#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x5 +#define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x7c00 +#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0xa +#define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0xf8000 +#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0xf +#define MC_SEQ_RAS_TIMING__TRRD_MASK 0xf00000 +#define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x14 +#define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000 +#define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x18 +#define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x3 +#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x0 +#define MC_SEQ_CAS_TIMING__TNOPR_MASK 0xc +#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x2 +#define MC_SEQ_CAS_TIMING__TR2W_MASK 0x1f0 +#define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x4 +#define MC_SEQ_CAS_TIMING__TCCDL_MASK 0xe00 +#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x9 +#define MC_SEQ_CAS_TIMING__TR2R_MASK 0xf000 +#define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0xc +#define MC_SEQ_CAS_TIMING__TW2R_MASK 0x1f0000 +#define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x10 +#define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000 +#define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x18 +#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x3f +#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x0 +#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x3f00 +#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x8 +#define MC_SEQ_MISC_TIMING__TRP_MASK 0xf8000 +#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0xf +#define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000 +#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x14 +#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x7 +#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x0 +#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x70 +#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x4 +#define MC_SEQ_MISC_TIMING2__FAW_MASK 0x1f00 +#define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x8 +#define MC_SEQ_MISC_TIMING2__TREDC_MASK 0xe000 +#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0xd +#define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x1f0000 +#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x10 +#define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x1e00000 +#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x15 +#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000 +#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x1c +#define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x7 +#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x0 +#define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x70 +#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x4 +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0xf00 +#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x8 +#define MC_SEQ_PMG_TIMING__TCKE_MASK 0x3f000 +#define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0xc +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x1c0000 +#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x12 +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x800000 +#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x17 +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000 +#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x18 +#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x7 +#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x0 +#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0xf8 +#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x3 +#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x300 +#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x8 +#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0xc00 +#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0xa +#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0xf000 +#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0xc +#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x10000 +#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x10 +#define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x20000 +#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x11 +#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x1f00000 +#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x14 +#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000 +#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x19 +#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x7 +#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x0 +#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0xf8 +#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x3 +#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x300 +#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x8 +#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0xc00 +#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0xa +#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0xf000 +#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0xc +#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x10000 +#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x10 +#define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x20000 +#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x11 +#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x1f00000 +#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x14 +#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000 +#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x19 +#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0xf +#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x0 +#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0xf0 +#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x4 +#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x100 +#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x8 +#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x200 +#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x9 +#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x400 +#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0xa +#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x800 +#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0xb +#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0xf000 +#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0xc +#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0xf0000 +#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x10 +#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x300000 +#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x14 +#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0xf000000 +#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18 +#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000 +#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x1c +#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000 +#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x1d +#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000 +#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x1e +#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0xf +#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x0 +#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0xf0 +#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x4 +#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x100 +#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x8 +#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x200 +#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x9 +#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x400 +#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0xa +#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x800 +#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0xb +#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0xf000 +#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0xc +#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0xf0000 +#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x10 +#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x300000 +#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x14 +#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0xf000000 +#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x18 +#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000 +#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x1c +#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000 +#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x1d +#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000 +#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x1e +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x1 +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x0 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x2 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x1 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x4 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x2 +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x8 +#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x3 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x10 +#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x4 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x20 +#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x5 +#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x40 +#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x6 +#define MC_SEQ_CMD__ADR_MASK 0xffff +#define MC_SEQ_CMD__ADR__SHIFT 0x0 +#define MC_SEQ_CMD__MOP_MASK 0xf0000 +#define MC_SEQ_CMD__MOP__SHIFT 0x10 +#define MC_SEQ_CMD__END_MASK 0x100000 +#define MC_SEQ_CMD__END__SHIFT 0x14 +#define MC_SEQ_CMD__CSB_MASK 0x600000 +#define MC_SEQ_CMD__CSB__SHIFT 0x15 +#define MC_SEQ_CMD__CHAN0_MASK 0x1000000 +#define MC_SEQ_CMD__CHAN0__SHIFT 0x18 +#define MC_SEQ_CMD__CHAN1_MASK 0x2000000 +#define MC_SEQ_CMD__CHAN1__SHIFT 0x19 +#define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000 +#define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x1c +#define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000 +#define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_CMD_EMRS__ADR_MASK 0xffff +#define MC_PMG_CMD_EMRS__ADR__SHIFT 0x0 +#define MC_PMG_CMD_EMRS__MOP_MASK 0x70000 +#define MC_PMG_CMD_EMRS__MOP__SHIFT 0x10 +#define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x80000 +#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x13 +#define MC_PMG_CMD_EMRS__END_MASK 0x100000 +#define MC_PMG_CMD_EMRS__END__SHIFT 0x14 +#define MC_PMG_CMD_EMRS__CSB_MASK 0x600000 +#define MC_PMG_CMD_EMRS__CSB__SHIFT 0x15 +#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000 +#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x1c +#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000 +#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_CMD_MRS__ADR_MASK 0xffff +#define MC_PMG_CMD_MRS__ADR__SHIFT 0x0 +#define MC_PMG_CMD_MRS__MOP_MASK 0x70000 +#define MC_PMG_CMD_MRS__MOP__SHIFT 0x10 +#define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x80000 +#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x13 +#define MC_PMG_CMD_MRS__END_MASK 0x100000 +#define MC_PMG_CMD_MRS__END__SHIFT 0x14 +#define MC_PMG_CMD_MRS__CSB_MASK 0x600000 +#define MC_PMG_CMD_MRS__CSB__SHIFT 0x15 +#define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000 +#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x1c +#define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000 +#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_CMD_MRS1__ADR_MASK 0xffff +#define MC_PMG_CMD_MRS1__ADR__SHIFT 0x0 +#define MC_PMG_CMD_MRS1__MOP_MASK 0x70000 +#define MC_PMG_CMD_MRS1__MOP__SHIFT 0x10 +#define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x80000 +#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x13 +#define MC_PMG_CMD_MRS1__END_MASK 0x100000 +#define MC_PMG_CMD_MRS1__END__SHIFT 0x14 +#define MC_PMG_CMD_MRS1__CSB_MASK 0x600000 +#define MC_PMG_CMD_MRS1__CSB__SHIFT 0x15 +#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000 +#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x1c +#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000 +#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_CMD_MRS2__ADR_MASK 0xffff +#define MC_PMG_CMD_MRS2__ADR__SHIFT 0x0 +#define MC_PMG_CMD_MRS2__MOP_MASK 0x70000 +#define MC_PMG_CMD_MRS2__MOP__SHIFT 0x10 +#define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x80000 +#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x13 +#define MC_PMG_CMD_MRS2__END_MASK 0x100000 +#define MC_PMG_CMD_MRS2__END__SHIFT 0x14 +#define MC_PMG_CMD_MRS2__CSB_MASK 0x600000 +#define MC_PMG_CMD_MRS2__CSB__SHIFT 0x15 +#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000 +#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x1c +#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000 +#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_CFG__SYC_CLK_MASK 0x1 +#define MC_PMG_CFG__SYC_CLK__SHIFT 0x0 +#define MC_PMG_CFG__RST_MRS_MASK 0x2 +#define MC_PMG_CFG__RST_MRS__SHIFT 0x1 +#define MC_PMG_CFG__RST_EMRS_MASK 0x4 +#define MC_PMG_CFG__RST_EMRS__SHIFT 0x2 +#define MC_PMG_CFG__TRI_MIO_MASK 0x8 +#define MC_PMG_CFG__TRI_MIO__SHIFT 0x3 +#define MC_PMG_CFG__XSR_TMR_MASK 0xf0 +#define MC_PMG_CFG__XSR_TMR__SHIFT 0x4 +#define MC_PMG_CFG__RST_MRS1_MASK 0x100 +#define MC_PMG_CFG__RST_MRS1__SHIFT 0x8 +#define MC_PMG_CFG__RST_MRS2_MASK 0x200 +#define MC_PMG_CFG__RST_MRS2__SHIFT 0x9 +#define MC_PMG_CFG__DPM_WAKE_MASK 0x400 +#define MC_PMG_CFG__DPM_WAKE__SHIFT 0xa +#define MC_PMG_CFG__RFS_SRX_MASK 0x1000 +#define MC_PMG_CFG__RFS_SRX__SHIFT 0xc +#define MC_PMG_CFG__PREA_SRX_MASK 0x2000 +#define MC_PMG_CFG__PREA_SRX__SHIFT 0xd +#define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0xf0000 +#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x10 +#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x100000 +#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x14 +#define MC_PMG_CFG__YCLK_ON_MASK 0x200000 +#define MC_PMG_CFG__YCLK_ON__SHIFT 0x15 +#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x400000 +#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x16 +#define MC_PMG_CFG__RXPDNB_MASK 0x2000000 +#define MC_PMG_CFG__RXPDNB__SHIFT 0x19 +#define MC_PMG_CFG__ZQCL_SEND_MASK 0xc000000 +#define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x1a +#define MC_PMG_AUTO_CMD__ADR_MASK 0x1ffff +#define MC_PMG_AUTO_CMD__ADR__SHIFT 0x0 +#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000 +#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x1c +#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000 +#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x1d +#define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x1 +#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x0 +#define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x2 +#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x1 +#define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x4 +#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x2 +#define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0xf0 +#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x4 +#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x100 +#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x8 +#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x200 +#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x9 +#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x400 +#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0xa +#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x800 +#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0xb +#define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x1000 +#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0xc +#define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x2000 +#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0xd +#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x4000 +#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0xe +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x8000 +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0xf +#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0xf0000 +#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x10 +#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x100000 +#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x14 +#define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x200000 +#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x15 +#define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x400000 +#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x16 +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x800000 +#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x17 +#define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000 +#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x18 +#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x1f +#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x0 +#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x20 +#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x5 +#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x40 +#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x6 +#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x100 +#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x8 +#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x200 +#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x9 +#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0xe000 +#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0xd +#define MC_IMP_CNTL__CAL_VREF_MASK 0x7f0000 +#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x10 +#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000 +#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x1d +#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000 +#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x1e +#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000 +#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x1f +#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0xff +#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x0 +#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0xff00 +#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x8 +#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0xfff0000 +#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x10 +#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000 +#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x1c +#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000 +#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x1d +#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000 +#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x1e +#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000 +#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x1f +#define MC_IMP_STATUS__PSTR_CAL_MASK 0xff +#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x0 +#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0xff00 +#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x8 +#define MC_IMP_STATUS__NSTR_CAL_MASK 0xff0000 +#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x10 +#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000 +#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x18 +#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0xff +#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x0 +#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0xff00 +#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x8 +#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0xff0000 +#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x10 +#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000 +#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x18 +#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0xff +#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x0 +#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0xf00 +#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x8 +#define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x1000 +#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0xc +#define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x2000 +#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0xd +#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x4000 +#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0xe +#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x8000 +#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0xf +#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0xf0000 +#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x10 +#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x100000 +#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x14 +#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x200000 +#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x15 +#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0xf000000 +#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x18 +#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000 +#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x1c +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x1 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x0 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x2 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x1 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x4 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x2 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x8 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x3 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x10 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x4 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x20 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x5 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x40 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x6 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x80 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x7 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x100 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x8 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x200 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x9 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x400 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0xa +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x800 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0xb +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x1000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0xc +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x2000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0xd +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x4000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0xe +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x8000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0xf +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x10000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x10 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x20000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x11 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x40000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x12 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x80000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x13 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x100000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x14 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x200000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x15 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x400000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x16 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x1000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x18 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x2000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x19 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x4000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x1a +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x8000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x1b +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x1c +#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x1d +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x1e +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000 +#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x1f +#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0xffff +#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x0 +#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000 +#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x10 +#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffff +#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x0 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x1 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x0 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x2 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x1 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x4 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x2 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x8 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x3 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x30 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x4 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x100 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x8 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x200 +#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x9 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x1 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x0 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x2 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x1 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x4 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x2 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x8 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x3 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x10 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x4 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x20 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x5 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x80 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc +#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x2000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0xd +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x4000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0xe +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x8000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0xf +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x20000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x11 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x40000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x12 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x80000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x13 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x100000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x14 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x200000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x400000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x800000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x17 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x1000000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x18 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x2000000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x19 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x4000000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x1a +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP_MASK 0x8000000 +#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP__SHIFT 0x1b +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x1 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x0 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x2 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x1 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x4 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x2 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x8 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x3 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x10 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x4 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x20 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x5 +#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40 +#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6 +#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x80 +#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb +#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc +#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x2000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0xd +#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x4000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0xe +#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x8000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0xf +#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x20000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x11 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x40000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x12 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x80000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x13 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x100000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x14 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x200000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x15 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x400000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x16 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x800000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x17 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x1000000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x18 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x2000000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x19 +#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x4000000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x1a +#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP_MASK 0x8000000 +#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP__SHIFT 0x1b +#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x1 +#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x0 +#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x2 +#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x1 +#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x4 +#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x2 +#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x8 +#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x3 +#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x10 +#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x4 +#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x20 +#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x5 +#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40 +#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6 +#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x80 +#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7 +#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100 +#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8 +#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200 +#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9 +#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400 +#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa +#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800 +#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb +#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000 +#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc +#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x2000 +#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0xd +#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x4000 +#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0xe +#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x8000 +#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0xf +#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x20000 +#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x11 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x40000 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x12 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x80000 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x13 +#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x100000 +#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x14 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x200000 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x400000 +#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16 +#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x800000 +#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x17 +#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x1000000 +#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x18 +#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x2000000 +#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x19 +#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x4000000 +#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x1a +#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP_MASK 0x8000000 +#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP__SHIFT 0x1b +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x1 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x0 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x2 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x1 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x4 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x2 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x8 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x3 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x10 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x4 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x20 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x5 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x80 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x2000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0xd +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x4000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0xe +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x8000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0xf +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x10000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x10 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x20000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x11 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x40000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x12 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x80000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x13 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x100000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x14 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x200000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x15 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x400000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x16 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x800000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x17 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x1000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x18 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x2000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x19 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x4000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x1a +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP_MASK 0x8000000 +#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP__SHIFT 0x1b +#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x1f +#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x0 +#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x3e0 +#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x5 +#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x7c00 +#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0xa +#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0xf8000 +#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0xf +#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0xff +#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x0 +#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0xff00 +#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x8 +#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0xff0000 +#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x10 +#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000 +#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x18 +#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0xff +#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x0 +#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0xff00 +#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x8 +#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0xff0000 +#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x10 +#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000 +#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x18 +#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffff +#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0xf +#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0xf0 +#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x4 +#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0xf00 +#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x8 +#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0xf000 +#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0xc +#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000 +#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x1c +#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000 +#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x1d +#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000 +#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x1e +#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x1 +#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x2 +#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x1 +#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x30 +#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x4 +#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x100 +#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x8 +#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x200 +#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x9 +#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x400 +#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0xa +#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x800 +#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0xb +#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x3ff0000 +#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x10 +#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000 +#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x1c +#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0xffff +#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x0 +#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000 +#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x10 +#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffff +#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0xf +#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0xf0 +#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x4 +#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0xf00 +#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x8 +#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0xf000 +#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0xc +#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000 +#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x1c +#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000 +#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x1d +#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000 +#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x1e +#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x1 +#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x0 +#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x2 +#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x1 +#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x30 +#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x4 +#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x100 +#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x8 +#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x200 +#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x9 +#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x400 +#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0xa +#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x800 +#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0xb +#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x3ff0000 +#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x10 +#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000 +#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x1c +#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0xffff +#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x0 +#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000 +#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x10 +#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x20 +#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0xf000 +#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0xc +#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0xf00000 +#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x2000000 +#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x19 +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x8000000 +#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x1b +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000 +#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x1c +#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x20 +#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0xf000 +#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0xc +#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0xf00000 +#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x2000000 +#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x19 +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x8000000 +#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x1b +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000 +#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x1c +#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x20 +#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x1000 +#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0xc +#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0xe000 +#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0xd +#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x700000 +#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x800000 +#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x17 +#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x2000000 +#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x19 +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000 +#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x1b +#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000 +#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x1e +#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000 +#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x1f +#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x3 +#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x0 +#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x4 +#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x2 +#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x8 +#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x3 +#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x30 +#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x4 +#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x40 +#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x6 +#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x80 +#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x7 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0xf00 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x8 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0xf000 +#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0xc +#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x10000 +#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x10 +#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0xc0000 +#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x12 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x700000 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x14 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x7000000 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x18 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000 +#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x1d +#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000 +#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x1e +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0xf +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x0 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0xf0 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x4 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0xff00 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x8 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x10000 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x10 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x20000 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x11 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x40000 +#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x12 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR_MASK 0x80000 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR__SHIFT 0x13 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN_MASK 0x100000 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN__SHIFT 0x14 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY_MASK 0x200000 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY__SHIFT 0x15 +#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN_MASK 0x400000 +#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN__SHIFT 0x16 +#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT_MASK 0x800000 +#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT__SHIFT 0x17 +#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0xe000000 +#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x19 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000 +#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x3 +#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x0 +#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x4 +#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x2 +#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x8 +#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x3 +#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x30 +#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x4 +#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x40 +#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x6 +#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x80 +#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x7 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0xf00 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x8 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0xf000 +#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0xc +#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x10000 +#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x10 +#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0xc0000 +#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x12 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x700000 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x14 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x7000000 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x18 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000 +#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x1d +#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000 +#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x1e +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0xf +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x0 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0xf0 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x4 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0xff00 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x8 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x10000 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x10 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x20000 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x11 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x40000 +#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x12 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR_MASK 0x80000 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR__SHIFT 0x13 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN_MASK 0x100000 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN__SHIFT 0x14 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY_MASK 0x200000 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY__SHIFT 0x15 +#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN_MASK 0x400000 +#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN__SHIFT 0x16 +#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT_MASK 0x800000 +#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT__SHIFT 0x17 +#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0xe000000 +#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x19 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000 +#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x1c +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x3f +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x0 +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0xfc0 +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x6 +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x3f000 +#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0xc +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0xfc0000 +#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x12 +#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x1000000 +#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x18 +#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x2000000 +#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x19 +#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000 +#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000 +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x1c +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000 +#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x1d +#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR_MASK 0x40000000 +#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR__SHIFT 0x1e +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x3f +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x0 +#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0xfc0 +#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x6 +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x3f000 +#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0xc +#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x1000000 +#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x18 +#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x2000000 +#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x19 +#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000 +#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a +#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000 +#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x1c +#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000 +#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x1d +#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x20 +#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0xf000 +#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0xc +#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0xf00000 +#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x2000000 +#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x19 +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x8000000 +#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x1b +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000 +#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x1c +#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x20 +#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0xf000 +#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0xc +#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0xf00000 +#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x2000000 +#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x19 +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x8000000 +#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x1b +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000 +#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x1c +#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x3 +#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x0 +#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0xc +#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x2 +#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x10 +#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x4 +#define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x20 +#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x5 +#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x40 +#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x6 +#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x80 +#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x7 +#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0xf00 +#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x8 +#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x1000 +#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0xc +#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0xe000 +#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0xd +#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0xf0000 +#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x10 +#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x700000 +#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x14 +#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x800000 +#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x17 +#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x1000000 +#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x18 +#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x2000000 +#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x19 +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x4000000 +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x1a +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000 +#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x1b +#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000 +#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x1e +#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000 +#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x1f +#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x3 +#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x0 +#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x4 +#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x2 +#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x8 +#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x3 +#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x30 +#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x4 +#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x40 +#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x6 +#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x80 +#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x7 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0xf00 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x8 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0xf000 +#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0xc +#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x10000 +#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x10 +#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0xc0000 +#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x12 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x700000 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x14 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x7000000 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x18 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000 +#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x1d +#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000 +#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x1e +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0xf +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x0 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0xf0 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x4 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0xff00 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x8 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x10000 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x10 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x20000 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x11 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x40000 +#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x12 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR_MASK 0x80000 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR__SHIFT 0x13 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN_MASK 0x100000 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN__SHIFT 0x14 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY_MASK 0x200000 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY__SHIFT 0x15 +#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN_MASK 0x400000 +#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN__SHIFT 0x16 +#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT_MASK 0x800000 +#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT__SHIFT 0x17 +#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0xe000000 +#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x19 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000 +#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x3 +#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x0 +#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x4 +#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x2 +#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x8 +#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x3 +#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x30 +#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x4 +#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x40 +#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x6 +#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x80 +#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x7 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0xf00 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x8 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0xf000 +#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0xc +#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x10000 +#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x10 +#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0xc0000 +#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x12 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x700000 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x14 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x7000000 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x18 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x1c +#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000 +#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x1d +#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000 +#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x1e +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0xf +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x0 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0xf0 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x4 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0xff00 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x8 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x10000 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x10 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x20000 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x11 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x40000 +#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x12 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR_MASK 0x80000 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR__SHIFT 0x13 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN_MASK 0x100000 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN__SHIFT 0x14 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY_MASK 0x200000 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY__SHIFT 0x15 +#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN_MASK 0x400000 +#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN__SHIFT 0x16 +#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT_MASK 0x800000 +#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT__SHIFT 0x17 +#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0xe000000 +#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x19 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000 +#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x1c +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x3f +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x0 +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0xfc0 +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x6 +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x3f000 +#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0xc +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0xfc0000 +#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x12 +#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x1000000 +#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x18 +#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x2000000 +#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x19 +#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000 +#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000 +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x1c +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000 +#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x1d +#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR_MASK 0x40000000 +#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR__SHIFT 0x1e +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x3f +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x0 +#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0xfc0 +#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x6 +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x3f000 +#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0xc +#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x1000000 +#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x18 +#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x2000000 +#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x19 +#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000 +#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a +#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000 +#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x1c +#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000 +#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x1d +#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0xf +#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x0 +#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0xf0 +#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x4 +#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x100 +#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x8 +#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x200 +#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x9 +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x400 +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0xa +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x800 +#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0xb +#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0xf000 +#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0xc +#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0xf0000 +#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x10 +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x100000 +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x14 +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x200000 +#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x15 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x400000 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x16 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x800000 +#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x17 +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x1000000 +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x18 +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x2000000 +#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x19 +#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x4000000 +#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x1a +#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x8000000 +#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x1b +#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000 +#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x1c +#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000 +#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x1d +#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000 +#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x1e +#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000 +#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x1f +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0xff +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x0 +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0xff00 +#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x8 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0xff0000 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x10 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000 +#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x18 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x1 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x0 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x2 +#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x1 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x4 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x2 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x8 +#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x3 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x10 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x4 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x20 +#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x5 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x40 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x6 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x80 +#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x7 +#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON_MASK 0xf00 +#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON__SHIFT 0x8 +#define MC_IO_CDRCNTL2_D0__WCDRTXSEL_MASK 0xf000 +#define MC_IO_CDRCNTL2_D0__WCDRTXSEL__SHIFT 0xc +#define MC_IO_CDRCNTL2_D0__WCDRTRACK01_MASK 0xf0000 +#define MC_IO_CDRCNTL2_D0__WCDRTRACK01__SHIFT 0x10 +#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0xf +#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x0 +#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0xf0 +#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x4 +#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x100 +#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x8 +#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x200 +#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x9 +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x400 +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0xa +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x800 +#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0xb +#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0xf000 +#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0xc +#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0xf0000 +#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x10 +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x100000 +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x14 +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x200000 +#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x15 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x400000 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x16 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x800000 +#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x17 +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x1000000 +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x18 +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x2000000 +#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x19 +#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x4000000 +#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x1a +#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x8000000 +#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x1b +#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000 +#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x1c +#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000 +#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x1d +#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000 +#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x1e +#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000 +#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x1f +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0xff +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x0 +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0xff00 +#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x8 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0xff0000 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x10 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000 +#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x18 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x1 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x0 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x2 +#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x1 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x4 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x2 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x8 +#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x3 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x10 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x4 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x20 +#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x5 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x40 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x6 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x80 +#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x7 +#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON_MASK 0xf00 +#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON__SHIFT 0x8 +#define MC_IO_CDRCNTL2_D1__WCDRTXSEL_MASK 0xf000 +#define MC_IO_CDRCNTL2_D1__WCDRTXSEL__SHIFT 0xc +#define MC_IO_CDRCNTL2_D1__WCDRTRACK01_MASK 0xf0000 +#define MC_IO_CDRCNTL2_D1__WCDRTRACK01__SHIFT 0x10 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x3 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x0 +#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0xc +#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x2 +#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x30 +#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x4 +#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0xc0 +#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x6 +#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x100 +#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x8 +#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x200 +#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x9 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0xc00 +#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0xa +#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x7000 +#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0xc +#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x30000 +#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x10 +#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0xc0000 +#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x12 +#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT_MASK 0xf00000 +#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT__SHIFT 0x14 +#define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 0xf000000 +#define MC_SEQ_FIFO_CTL__R_DQS_STEP__SHIFT 0x18 +#define MC_SEQ_FIFO_CTL__R_DQS_FRC_MASK 0x10000000 +#define MC_SEQ_FIFO_CTL__R_DQS_FRC__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0xf +#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0xf +#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0xf +#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0xf +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0xf +#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0xf +#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0xc +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0xf0000 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x10 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0xf00000 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x14 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0xf000000 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x18 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000 +#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c +#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0xf +#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x0 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0xf0 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x4 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0xf00 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x8 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0xf000 +#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0xf +#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0xf +#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0xf +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c +#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0xf +#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0xf +#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x0 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0xf0 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x4 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0xf00 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x8 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0xf000 +#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0xc +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0xf0000 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x10 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0xf00000 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x14 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0xf000000 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x18 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000 +#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0xff +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x0 +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0xff00 +#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x8 +#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x10000 +#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x10 +#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x20000 +#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x11 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x40000 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x12 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x80000 +#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x13 +#define MC_IO_PAD_CNTL__ATBSEL_MASK 0xf00000 +#define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x14 +#define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000 +#define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x18 +#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000 +#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x1e +#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000 +#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x1f +#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x4 +#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x2 +#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x8 +#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x3 +#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x10 +#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x4 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x80 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x7 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x100 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x8 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x200 +#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x9 +#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x400 +#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0xa +#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x800 +#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0xb +#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x1000 +#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0xc +#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x2000 +#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0xd +#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x4000 +#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0xe +#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0xf8000 +#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0xf +#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x100000 +#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x14 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x200000 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x15 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0xc00000 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x16 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x3000000 +#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x18 +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x8000000 +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x1b +#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000 +#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x1c +#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000 +#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x1d +#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000 +#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x1e +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000 +#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x1f +#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x1 +#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x0 +#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x2 +#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x1 +#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x4 +#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x2 +#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x8 +#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x3 +#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x10 +#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x4 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x20 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x5 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x40 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x6 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x80 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x7 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x100 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x8 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x200 +#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x9 +#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x400 +#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0xa +#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x800 +#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0xb +#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x1000 +#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0xc +#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x2000 +#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0xd +#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x4000 +#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0xe +#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0xf8000 +#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0xf +#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x100000 +#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x14 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x200000 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x15 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0xc00000 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x16 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x3000000 +#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x18 +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x8000000 +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x1b +#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000 +#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x1c +#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000 +#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x1d +#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000 +#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x1e +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000 +#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x1f +#define MC_NPL_STATUS__D0_PDELAY_MASK 0x3 +#define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x0 +#define MC_NPL_STATUS__D0_NDELAY_MASK 0xc +#define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x2 +#define MC_NPL_STATUS__D0_PEARLY_MASK 0x10 +#define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x4 +#define MC_NPL_STATUS__D0_NEARLY_MASK 0x20 +#define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x5 +#define MC_NPL_STATUS__D1_PDELAY_MASK 0xc0 +#define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x6 +#define MC_NPL_STATUS__D1_NDELAY_MASK 0x300 +#define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x8 +#define MC_NPL_STATUS__D1_PEARLY_MASK 0x400 +#define MC_NPL_STATUS__D1_PEARLY__SHIFT 0xa +#define MC_NPL_STATUS__D1_NEARLY_MASK 0x800 +#define MC_NPL_STATUS__D1_NEARLY__SHIFT 0xb +#define MC_BIST_CMD_CNTL__RESET_MASK 0x1 +#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x0 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x2 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x1 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x4 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x2 +#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x8 +#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x3 +#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0xfff0 +#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x4 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x10000 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x10 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x20000 +#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x11 +#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0xffc0000 +#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x12 +#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000 +#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x1c +#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000 +#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x1d +#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000 +#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x1e +#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000 +#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x1f +#define MC_BIST_CNTL__RESET_MASK 0x1 +#define MC_BIST_CNTL__RESET__SHIFT 0x0 +#define MC_BIST_CNTL__RUN_MASK 0x2 +#define MC_BIST_CNTL__RUN__SHIFT 0x1 +#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x4 +#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x2 +#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x8 +#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x3 +#define MC_BIST_CNTL__MOP_MODE_MASK 0x10 +#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x4 +#define MC_BIST_CNTL__ADR_MODE_MASK 0x20 +#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x5 +#define MC_BIST_CNTL__DAT_MODE_MASK 0x40 +#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x6 +#define MC_BIST_CNTL__LOOP_MASK 0xc00 +#define MC_BIST_CNTL__LOOP__SHIFT 0xa +#define MC_BIST_CNTL__ENABLE_D0_MASK 0x1000 +#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0xc +#define MC_BIST_CNTL__ENABLE_D1_MASK 0x2000 +#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0xd +#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x4000 +#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0xe +#define MC_BIST_CNTL__LOOP_CNT_MASK 0xfff0000 +#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x10 +#define MC_BIST_CNTL__DONE_MASK 0x40000000 +#define MC_BIST_CNTL__DONE__SHIFT 0x1e +#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000 +#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x1f +#define MC_BIST_AUTO_CNTL__MOP_MASK 0x3 +#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x0 +#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0xf0 +#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x4 +#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0xffff00 +#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x8 +#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x1000000 +#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x18 +#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x2000000 +#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x19 +#define MC_BIST_DIR_CNTL__MOP_MASK 0x7 +#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x0 +#define MC_BIST_DIR_CNTL__EOB_MASK 0x8 +#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x3 +#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x10 +#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x4 +#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x20 +#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x5 +#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x40 +#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x6 +#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x80 +#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x7 +#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x100 +#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x8 +#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x200 +#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x9 +#define MC_BIST_DIR_CNTL__MOP3_MASK 0x400 +#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0xa +#define MC_BIST_SADDR__COL_MASK 0x3ff +#define MC_BIST_SADDR__COL__SHIFT 0x0 +#define MC_BIST_SADDR__ROW_MASK 0xfffc00 +#define MC_BIST_SADDR__ROW__SHIFT 0xa +#define MC_BIST_SADDR__BANK_MASK 0xf000000 +#define MC_BIST_SADDR__BANK__SHIFT 0x18 +#define MC_BIST_SADDR__RANK_MASK 0x10000000 +#define MC_BIST_SADDR__RANK__SHIFT 0x1c +#define MC_BIST_SADDR__COLH_MASK 0x20000000 +#define MC_BIST_SADDR__COLH__SHIFT 0x1d +#define MC_BIST_SADDR__ROWH_MASK 0xc0000000 +#define MC_BIST_SADDR__ROWH__SHIFT 0x1e +#define MC_BIST_EADDR__COL_MASK 0x3ff +#define MC_BIST_EADDR__COL__SHIFT 0x0 +#define MC_BIST_EADDR__ROW_MASK 0xfffc00 +#define MC_BIST_EADDR__ROW__SHIFT 0xa +#define MC_BIST_EADDR__BANK_MASK 0xf000000 +#define MC_BIST_EADDR__BANK__SHIFT 0x18 +#define MC_BIST_EADDR__RANK_MASK 0x10000000 +#define MC_BIST_EADDR__RANK__SHIFT 0x1c +#define MC_BIST_EADDR__COLH_MASK 0x20000000 +#define MC_BIST_EADDR__COLH__SHIFT 0x1d +#define MC_BIST_EADDR__ROWH_MASK 0xc0000000 +#define MC_BIST_EADDR__ROWH__SHIFT 0x1e +#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0xf +#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x0 +#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0xff0 +#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x4 +#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x1000 +#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0xc +#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x2000 +#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0xd +#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x4000 +#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0xe +#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x8000 +#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0xf +#define MC_BIST_CMP_CNTL__CMP_MASK 0x30000 +#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x10 +#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x40000 +#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x12 +#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x80000 +#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x13 +#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x300000 +#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x14 +#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000 +#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x16 +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x1f +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x0 +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x100 +#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x8 +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x1f000 +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0xc +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x100000 +#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x14 +#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x0 +#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffff +#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x0 +#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffff +#define MC_BIST_DATA_MASK__MASK__SHIFT 0x0 +#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x3ff +#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x0 +#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0xfffc00 +#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0xa +#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0xf000000 +#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x18 +#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000 +#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x1c +#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000 +#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x1d +#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000 +#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x1e +#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffff +#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x0 +#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffff +#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x0 +#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffff +#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x0 +#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffff +#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x0 +#define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000 +#define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x1e +#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x1 +#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x0 +#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x100 +#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x8 +#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x200 +#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x9 +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x400 +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0xa +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x800 +#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0xb +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x1000 +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0xc +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x2000 +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0xd +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x4000 +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0xe +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x8000 +#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0xf +#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0xf +#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0xf0 +#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x4 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0xf00 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x8 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0xf000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0xc +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0xf0000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x10 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0xf00000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x14 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0xf000000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x18 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000 +#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x1c +#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x0 +#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffff +#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x0 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x1 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x0 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x2 +#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x1 +#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x4 +#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x2 +#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x8 +#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x3 +#define MC_SEQ_STATUS_M__SLF_D0_MASK 0x10 +#define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x4 +#define MC_SEQ_STATUS_M__SLF_D1_MASK 0x20 +#define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x5 +#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x40 +#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x6 +#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x80 +#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x7 +#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x100 +#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x8 +#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x200 +#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x9 +#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x1000 +#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0xc +#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x2000 +#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0xd +#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x4000 +#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0xe +#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x8000 +#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0xf +#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x10000 +#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x10 +#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x1f00000 +#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x14 +#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x2000000 +#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x19 +#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x4000000 +#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x1a +#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP_MASK 0x8000000 +#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP__SHIFT 0x1b +#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP_MASK 0x10000000 +#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP__SHIFT 0x1c +#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x1 +#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x0 +#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x2 +#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x1 +#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x10 +#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x4 +#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x20 +#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x5 +#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x100 +#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x8 +#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x200 +#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x9 +#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff +#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0 +#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffff +#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x0 +#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffff +#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC0__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC0__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC1__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC1__VALUE__SHIFT 0x0 +#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xffffffff +#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x0 +#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffff +#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x0 +#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffff +#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x0 +#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0xfff +#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x0 +#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0xfff000 +#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0xc +#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000 +#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x18 +#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0xfff +#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x0 +#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0xfff000 +#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0xc +#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000 +#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x18 +#define MC_SEQ_SUP_CNTL__RUN_MASK 0x1 +#define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x0 +#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x2 +#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x1 +#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x4 +#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x2 +#define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x8 +#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x3 +#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x10 +#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x4 +#define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x20 +#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x5 +#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x40 +#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x6 +#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x80 +#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x7 +#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000 +#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x17 +#define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffff +#define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x0 +#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffff +#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x0 +#define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffff +#define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x0 +#define MC_SEQ_MISC3__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC3__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC4__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC4__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC5__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC5__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC6__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC6__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC7__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC7__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC8__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC8__VALUE__SHIFT 0x0 +#define MC_SEQ_MISC9__VALUE_MASK 0xffffffff +#define MC_SEQ_MISC9__VALUE__SHIFT 0x0 +#define MC_SEQ_CG__CG_SEQ_REQ_MASK 0xff +#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x0 +#define MC_SEQ_CG__CG_SEQ_RESP_MASK 0xff00 +#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x8 +#define MC_SEQ_CG__SEQ_CG_REQ_MASK 0xff0000 +#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x10 +#define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000 +#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x18 +#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x3 +#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x0 +#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0xc +#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x2 +#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x30 +#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x4 +#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0xc0 +#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x6 +#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x3 +#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x0 +#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0xc +#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x2 +#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x30 +#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x4 +#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0xc0 +#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x15 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x7 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x0 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x38 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x3 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x1c0 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x6 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0xe00 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x9 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x7000 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0xc +#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x38000 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0xf +#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x1c0000 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x12 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0xe00000 +#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x15 +#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f +#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0 +#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0 +#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5 +#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00 +#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa +#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000 +#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf +#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000 +#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14 +#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000 +#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18 +#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3 +#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0 +#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc +#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2 +#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0 +#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4 +#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00 +#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9 +#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000 +#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc +#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000 +#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10 +#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000 +#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18 +#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f +#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0 +#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00 +#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8 +#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000 +#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf +#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000 +#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14 +#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x7 +#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x0 +#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x70 +#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x4 +#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x1f00 +#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x8 +#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0xe000 +#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0xd +#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x1f0000 +#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x10 +#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0xe00000 +#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x15 +#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0xf000000 +#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x18 +#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000 +#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x1c +#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x7 +#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x0 +#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0xf8 +#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x3 +#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x300 +#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x8 +#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0xc00 +#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0xa +#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0xf000 +#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0xc +#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x10000 +#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x10 +#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x20000 +#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x11 +#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x1f00000 +#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x14 +#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000 +#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x19 +#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x7 +#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x0 +#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0xf8 +#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x3 +#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x300 +#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x8 +#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0xc00 +#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0xa +#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0xf000 +#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0xc +#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x10000 +#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x10 +#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x20000 +#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x11 +#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x1f00000 +#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x14 +#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000 +#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x19 +#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0xf +#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x0 +#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0xf0 +#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x4 +#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x100 +#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x8 +#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x200 +#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x9 +#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x400 +#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0xa +#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x800 +#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0xb +#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0xf000 +#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0xc +#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0xf0000 +#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x10 +#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x300000 +#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x14 +#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0xf000000 +#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x18 +#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000 +#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x1c +#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000 +#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x1d +#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000 +#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x1e +#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0xf +#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x0 +#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0xf0 +#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x4 +#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x100 +#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x8 +#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x200 +#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x9 +#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x400 +#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0xa +#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x800 +#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0xb +#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0xf000 +#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0xc +#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0xf0000 +#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x10 +#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x300000 +#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x14 +#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0xf000000 +#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x18 +#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000 +#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x1c +#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000 +#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x1d +#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000 +#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x1e +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x1 +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x0 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x2 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x1 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x4 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x2 +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x8 +#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x3 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x10 +#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x4 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x20 +#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x5 +#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x40 +#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x6 +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0xffff +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x70000 +#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x100000 +#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x14 +#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x600000 +#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000 +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x1c +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000 +#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x1d +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0xffff +#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x70000 +#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x100000 +#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x14 +#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x600000 +#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000 +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x1c +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000 +#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x1d +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0xffff +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x70000 +#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x100000 +#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x14 +#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x600000 +#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000 +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x1c +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000 +#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x1d +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0xffff +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x70000 +#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x100000 +#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x14 +#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x600000 +#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000 +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x1c +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000 +#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x1d +#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x7 +#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x0 +#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x70 +#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x4 +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0xf00 +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x8 +#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x3f000 +#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0xc +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x1c0000 +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x12 +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x800000 +#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x17 +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000 +#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x18 +#define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffff +#define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x0 +#define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffff +#define MC_SEQ_IO_RDBI__MASK__SHIFT 0x0 +#define MC_SEQ_IO_REDC__EDC_MASK 0xffffffff +#define MC_SEQ_IO_REDC__EDC__SHIFT 0x0 +#define MC_SEQ_TCG_CNTL__RESET_MASK 0x1 +#define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x0 +#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x2 +#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x1 +#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x4 +#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x2 +#define MC_SEQ_TCG_CNTL__START_MASK 0x8 +#define MC_SEQ_TCG_CNTL__START__SHIFT 0x3 +#define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x70 +#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x4 +#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x80 +#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x7 +#define MC_SEQ_TCG_CNTL__MOP_MASK 0xf00 +#define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x8 +#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0xf000 +#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0xc +#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x10000 +#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x10 +#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x20000 +#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x11 +#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x40000 +#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x12 +#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x380000 +#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x13 +#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x400000 +#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x16 +#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x800000 +#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x17 +#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x1000000 +#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x18 +#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x2000000 +#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x19 +#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x4000000 +#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x1a +#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR_MASK 0x10000000 +#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR__SHIFT 0x1c +#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH_MASK 0x20000000 +#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH__SHIFT 0x1d +#define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000 +#define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x1f +#define MC_SEQ_TSM_CTRL__START_MASK 0x1 +#define MC_SEQ_TSM_CTRL__START__SHIFT 0x0 +#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x2 +#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x1 +#define MC_SEQ_TSM_CTRL__DONE_MASK 0x4 +#define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x2 +#define MC_SEQ_TSM_CTRL__ERR_MASK 0x8 +#define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x3 +#define MC_SEQ_TSM_CTRL__STEP_MASK 0x10 +#define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x4 +#define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x20 +#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x5 +#define MC_SEQ_TSM_CTRL__INVERT_MASK 0x40 +#define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x6 +#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x80 +#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x7 +#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x300 +#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x8 +#define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x400 +#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0xa +#define MC_SEQ_TSM_CTRL__DUAL_CH_EN_MASK 0x800 +#define MC_SEQ_TSM_CTRL__DUAL_CH_EN__SHIFT 0xb +#define MC_SEQ_TSM_CTRL__DONE0_MASK 0x1000 +#define MC_SEQ_TSM_CTRL__DONE0__SHIFT 0xc +#define MC_SEQ_TSM_CTRL__DONE1_MASK 0x2000 +#define MC_SEQ_TSM_CTRL__DONE1__SHIFT 0xd +#define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000 +#define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x10 +#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_GCNT__TESTS_MASK 0xff00 +#define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000 +#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x10 +#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_OCNT__TESTS_MASK 0xff00 +#define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000 +#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x10 +#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_NCNT__TESTS_MASK 0xff00 +#define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0xf0000 +#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x10 +#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0xf00000 +#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x14 +#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0xf000000 +#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x18 +#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0xff00 +#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0xff0000 +#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x10 +#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000 +#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x18 +#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0xff00 +#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0xf0000 +#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x10 +#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000 +#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x18 +#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0xf +#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x0 +#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0xf0 +#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x4 +#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0xff00 +#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x8 +#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0xff0000 +#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x10 +#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000 +#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x18 +#define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffff +#define MC_SEQ_TSM_EDC__EDC__SHIFT 0x0 +#define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffff +#define MC_SEQ_TSM_DBI__DBI__SHIFT 0x0 +#define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffff +#define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x0 +#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0xffff +#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x0 +#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0xf0000 +#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x10 +#define MC_SEQ_TSM_MISC__CH1_OFFSET_MASK 0x3f00000 +#define MC_SEQ_TSM_MISC__CH1_OFFSET__SHIFT 0x14 +#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET_MASK 0xfc000000 +#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET__SHIFT 0x1a +#define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffff +#define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x0 +#define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffff +#define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x0 +#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0xffff +#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x0 +#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000 +#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x10 +#define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0xf +#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x0 +#define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0xf0 +#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x4 +#define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0xf00 +#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x8 +#define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0xf000 +#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0xc +#define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x70000 +#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x10 +#define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0xf00000 +#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x14 +#define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x7000000 +#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x18 +#define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000 +#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x1c +#define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0xf +#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x0 +#define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0xf0 +#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x4 +#define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0xf00 +#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x8 +#define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0xf000 +#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0xc +#define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x70000 +#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x10 +#define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0xf00000 +#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x14 +#define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x7000000 +#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x18 +#define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000 +#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x1c +#define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x7f +#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x0 +#define MC_PHY_TIMING_2__RXC0_INV_MASK 0x100 +#define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x8 +#define MC_PHY_TIMING_2__RXC1_INV_MASK 0x200 +#define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x9 +#define MC_PHY_TIMING_2__TXC0_INV_MASK 0x400 +#define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0xa +#define MC_PHY_TIMING_2__TXC1_INV_MASK 0x800 +#define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0xb +#define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x1000 +#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0xc +#define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x2000 +#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0xd +#define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x4000 +#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0xe +#define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x8000 +#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0xf +#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x10000 +#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x10 +#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x20000 +#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x11 +#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x40000 +#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x12 +#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x80000 +#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x13 +#define MC_PHY_TIMING_2__WR_DLY_MASK 0xf00000 +#define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x14 +#define MC_PHY_TIMING_2__RXDPWRONC0_FRC_MASK 0x1000000 +#define MC_PHY_TIMING_2__RXDPWRONC0_FRC__SHIFT 0x18 +#define MC_PHY_TIMING_2__RXDPWRONC1_FRC_MASK 0x2000000 +#define MC_PHY_TIMING_2__RXDPWRONC1_FRC__SHIFT 0x19 +#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x1 +#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x0 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x2 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x1 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x4 +#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x2 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x8 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x3 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x10 +#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x4 +#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x20 +#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x5 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x40 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x6 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x80 +#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x7 +#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x1f +#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x0 +#define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x40 +#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x6 +#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x80 +#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x7 +#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x100 +#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x8 +#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x200 +#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x9 +#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x10000 +#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x10 +#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x20000 +#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x11 +#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x1000000 +#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x18 +#define DLL_CNTL__DLL_RESET_TIME_MASK 0x3ff +#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x0 +#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x3ff000 +#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0xc +#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x1000000 +#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x18 +#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x2000000 +#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x19 +#define DLL_CNTL__PWR2_MODE_MASK 0x4000000 +#define DLL_CNTL__PWR2_MODE__SHIFT 0x1a +#define MPLL_SEQ_UCODE_1__INSTR0_MASK 0xf +#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x0 +#define MPLL_SEQ_UCODE_1__INSTR1_MASK 0xf0 +#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x4 +#define MPLL_SEQ_UCODE_1__INSTR2_MASK 0xf00 +#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x8 +#define MPLL_SEQ_UCODE_1__INSTR3_MASK 0xf000 +#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0xc +#define MPLL_SEQ_UCODE_1__INSTR4_MASK 0xf0000 +#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x10 +#define MPLL_SEQ_UCODE_1__INSTR5_MASK 0xf00000 +#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x14 +#define MPLL_SEQ_UCODE_1__INSTR6_MASK 0xf000000 +#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x18 +#define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000 +#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x1c +#define MPLL_SEQ_UCODE_2__INSTR8_MASK 0xf +#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x0 +#define MPLL_SEQ_UCODE_2__INSTR9_MASK 0xf0 +#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x4 +#define MPLL_SEQ_UCODE_2__INSTR10_MASK 0xf00 +#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x8 +#define MPLL_SEQ_UCODE_2__INSTR11_MASK 0xf000 +#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0xc +#define MPLL_SEQ_UCODE_2__INSTR12_MASK 0xf0000 +#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x10 +#define MPLL_SEQ_UCODE_2__INSTR13_MASK 0xf00000 +#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x14 +#define MPLL_SEQ_UCODE_2__INSTR14_MASK 0xf000000 +#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x18 +#define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000 +#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x1c +#define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0xff +#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x0 +#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x100 +#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x8 +#define MPLL_CNTL_MODE__GDDR_PWRON_OVR_MASK 0x200 +#define MPLL_CNTL_MODE__GDDR_PWRON_OVR__SHIFT 0x9 +#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x800 +#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0xb +#define MPLL_CNTL_MODE__SPARE_1_MASK 0x1000 +#define MPLL_CNTL_MODE__SPARE_1__SHIFT 0xc +#define MPLL_CNTL_MODE__QDR_MASK 0x2000 +#define MPLL_CNTL_MODE__QDR__SHIFT 0xd +#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x4000 +#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0xe +#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x10000 +#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x10 +#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x20000 +#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x11 +#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x100000 +#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x14 +#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x600000 +#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x15 +#define MPLL_CNTL_MODE__SPARE_2_MASK 0x800000 +#define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x17 +#define MPLL_CNTL_MODE__SS_SSEN_MASK 0x3000000 +#define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x18 +#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x4000000 +#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x1a +#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x8000000 +#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x1b +#define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000 +#define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x1c +#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000 +#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x1f +#define MPLL_FUNC_CNTL__SPARE_0_MASK 0x20 +#define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x5 +#define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0xf00 +#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x8 +#define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0xf0000 +#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x10 +#define MPLL_FUNC_CNTL__BWCTRL_MASK 0xff00000 +#define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x14 +#define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000 +#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x1e +#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x3 +#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x0 +#define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0xc +#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x2 +#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0xfff0 +#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x4 +#define MPLL_FUNC_CNTL_1__CLKF_MASK 0xfff0000 +#define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x10 +#define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000 +#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x1c +#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x1 +#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x0 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x2 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x1 +#define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x4 +#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x2 +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x8 +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x3 +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x10 +#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x4 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x20 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x5 +#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x40 +#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x6 +#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x80 +#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x7 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x100 +#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x8 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x200 +#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x9 +#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0xc00 +#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0xa +#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x3000 +#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0xc +#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN_MASK 0x4000 +#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN__SHIFT 0xe +#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR_MASK 0x8000 +#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR__SHIFT 0xf +#define MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK 0x10000 +#define MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT 0x10 +#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0xe0000 +#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x11 +#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x7f00000 +#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x14 +#define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000 +#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x1b +#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7 +#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0 +#define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8 +#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x3 +#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7 +#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0 +#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x8 +#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x3 +#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x10 +#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x4 +#define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0 +#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x5 +#define MPLL_TIME__MPLL_LOCK_TIME_MASK 0xffff +#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x0 +#define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000 +#define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x10 +#define MPLL_SS1__CLKV_MASK 0x3ffffff +#define MPLL_SS1__CLKV__SHIFT 0x0 +#define MPLL_SS1__SPARE_MASK 0xfc000000 +#define MPLL_SS1__SPARE__SHIFT 0x1a +#define MPLL_SS2__CLKS_MASK 0xfff +#define MPLL_SS2__CLKS__SHIFT 0x0 +#define MPLL_SS2__SPARE_MASK 0xfffff000 +#define MPLL_SS2__SPARE__SHIFT 0xc +#define MPLL_CONTROL__GDDR_PWRON_MASK 0x1 +#define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x0 +#define MPLL_CONTROL__REFCLK_PWRON_MASK 0x2 +#define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x1 +#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x4 +#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x2 +#define MPLL_CONTROL__AD_BG_PWRON_MASK 0x1000 +#define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0xc +#define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x2000 +#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0xd +#define MPLL_CONTROL__AD_PLL_RESET_MASK 0x4000 +#define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0xe +#define MPLL_CONTROL__SPARE_AD_0_MASK 0x8000 +#define MPLL_CONTROL__SPARE_AD_0__SHIFT 0xf +#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x10000 +#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x10 +#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x20000 +#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x11 +#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x40000 +#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x12 +#define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x80000 +#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x13 +#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x100000 +#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x14 +#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x200000 +#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x15 +#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x400000 +#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x16 +#define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x800000 +#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x17 +#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x1000000 +#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x18 +#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x2000000 +#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x19 +#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x4000000 +#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x1a +#define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x8000000 +#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x1b +#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000 +#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x1c +#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000 +#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x1d +#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000 +#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x1e +#define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000 +#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x1f +#define MPLL_AD_STATUS__VCTRLADC_MASK 0x7 +#define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x0 +#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x70 +#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4 +#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x1ff80 +#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x7 +#define MPLL_AD_STATUS__OINT_RESET_MASK 0x20000 +#define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x11 +#define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x40000 +#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x12 +#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000 +#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13 +#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x7 +#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x0 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80 +#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7 +#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x20000 +#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x11 +#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x40000 +#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x12 +#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000 +#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13 +#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x7 +#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x0 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80 +#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7 +#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x20000 +#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x11 +#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x40000 +#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x12 +#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000 +#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13 +#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x7 +#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x0 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80 +#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7 +#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x20000 +#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x11 +#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x40000 +#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x12 +#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000 +#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13 +#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x7 +#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x0 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80 +#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7 +#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x20000 +#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x11 +#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x40000 +#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x12 +#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000 +#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13 +#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x1 +#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x0 +#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x2 +#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x1 +#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x3c +#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x2 +#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0xc0 +#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x6 +#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x300 +#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x8 +#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x3c00 +#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0xa +#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x10000 +#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x10 +#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x20000 +#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x11 +#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x40000 +#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x12 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x1 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x0 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x2 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x1 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x4 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x2 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x8 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x3 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x10 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x4 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x20 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x5 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x40 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x6 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x80 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x7 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x100 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x8 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x200 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x9 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x400 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0xa +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x800 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0xb +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x1000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0xc +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x2000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0xd +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x4000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0xe +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x8000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0xf +#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x10000 +#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x10 +#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000 +#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x1f +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x1 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x0 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x2 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x1 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x4 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x2 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x8 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x3 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x10 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x4 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x20 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x5 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x40 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x6 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x80 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x7 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x100 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x8 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x200 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x9 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x400 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0xa +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x800 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0xb +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x1000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0xc +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x2000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0xd +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x4000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0xe +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x8000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0xf +#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x10000 +#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x10 +#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000 +#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x1f +#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x1f +#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x0 +#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffff +#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_MISC__FLAG_MASK 0xff +#define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x0 +#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0xf00 +#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x8 +#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0xf000 +#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0xc +#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0xff +#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x0 +#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0xff00 +#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x8 +#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0xff0000 +#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x10 +#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000 +#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x18 +#define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x0 +#define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffff +#define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x0 +#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x1ff +#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x0 +#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffff +#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x0 +#define MC_IO_DEBUG_UP_0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_2__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_2__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_2__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_3__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_3__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_3__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_4__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_4__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_4__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_5__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_5__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_5__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_6__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_6__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_6__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_7__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_7__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_7__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_8__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_8__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_8__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_9__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_9__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_9__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_10__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_10__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_10__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_11__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_11__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_11__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_12__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_12__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_12__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_13__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_13__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_13__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_14__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_14__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_14__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_15__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_15__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_15__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_16__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_16__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_16__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_17__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_17__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_17__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_18__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_18__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_18__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_19__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_19__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_19__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_20__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_20__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_20__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_21__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_21__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_21__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_22__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_22__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_22__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_23__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_23__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_23__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_24__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_24__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_24__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_25__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_25__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_25__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_26__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_26__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_26__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_27__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_27__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_27__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_28__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_28__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_28__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_29__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_29__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_29__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_30__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_30__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_30__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_31__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_31__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_31__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_32__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_32__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_32__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_33__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_33__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_33__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_34__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_34__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_34__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_35__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_35__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_35__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_36__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_36__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_36__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_37__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_37__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_37__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_38__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_38__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_38__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_39__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_39__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_39__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_40__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_40__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_40__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_41__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_41__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_41__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_42__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_42__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_42__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_43__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_43__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_43__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_44__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_44__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_44__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_45__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_45__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_45__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_46__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_46__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_46__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_47__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_47__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_47__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_48__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_48__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_48__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_49__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_49__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_49__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_50__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_50__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_50__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_51__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_51__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_51__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_52__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_52__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_52__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_53__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_53__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_53__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_54__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_54__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_54__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_55__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_55__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_55__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_56__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_56__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_56__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_57__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_57__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_57__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_58__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_58__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_58__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_59__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_59__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_59__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_60__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_60__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_60__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_61__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_61__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_61__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_62__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_62__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_62__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_63__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_63__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_63__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_64__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_64__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_64__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_65__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_65__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_65__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_66__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_66__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_66__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_67__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_67__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_67__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_68__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_68__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_68__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_69__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_69__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_69__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_70__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_70__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_70__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_71__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_71__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_71__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_72__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_72__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_72__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_73__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_73__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_73__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_74__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_74__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_74__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_75__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_75__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_75__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_76__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_76__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_76__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_77__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_77__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_77__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_78__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_78__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_78__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_79__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_79__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_79__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_80__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_80__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_80__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_81__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_81__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_81__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_82__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_82__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_82__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_83__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_83__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_83__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_84__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_84__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_84__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_85__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_85__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_85__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_86__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_86__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_86__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_87__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_87__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_87__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_88__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_88__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_88__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_89__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_89__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_89__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_90__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_90__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_90__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_91__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_91__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_91__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_92__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_92__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_92__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_93__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_93__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_93__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_94__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_94__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_94__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_95__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_95__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_95__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_96__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_96__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_96__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_97__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_97__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_97__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_98__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_98__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_98__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_99__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_99__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_99__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_100__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_100__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_100__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_101__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_101__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_101__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_102__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_102__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_102__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_103__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_103__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_103__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_104__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_104__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_104__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_105__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_105__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_105__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_106__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_106__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_106__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_107__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_107__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_107__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_108__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_108__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_108__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_109__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_109__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_109__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_110__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_110__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_110__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_111__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_111__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_111__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_112__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_112__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_112__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_113__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_113__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_113__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_114__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_114__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_114__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_115__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_115__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_115__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_116__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_116__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_116__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_117__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_117__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_117__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_118__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_118__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_118__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_119__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_119__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_119__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_120__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_120__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_120__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_121__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_121__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_121__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_122__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_122__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_122__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_123__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_123__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_123__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_124__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_124__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_124__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_125__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_125__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_125__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_126__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_126__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_126__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_127__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_127__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_127__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_128__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_128__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_128__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_129__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_129__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_129__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_130__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_130__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_130__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_131__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_131__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_131__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_132__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_132__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_132__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_133__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_133__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_133__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_134__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_134__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_134__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_135__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_135__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_135__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_136__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_136__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_136__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_137__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_137__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_137__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_138__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_138__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_138__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_139__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_139__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_139__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_140__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_140__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_140__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_141__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_141__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_141__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_142__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_142__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_142__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_143__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_143__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_143__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_144__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_144__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_144__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_145__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_145__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_145__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_146__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_146__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_146__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_147__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_147__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_147__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_148__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_148__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_148__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_149__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_149__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_149__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_150__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_150__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_150__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_151__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_151__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_151__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_152__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_152__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_152__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_153__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_153__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_153__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_154__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_154__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_154__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_155__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_155__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_155__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_156__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_156__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_156__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_157__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_157__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_157__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_158__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_158__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_158__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_UP_159__VALUE0_MASK 0xff +#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_UP_159__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_UP_159__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x18 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0xff +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x0 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0xff00 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x8 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0xff0000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x10 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000 +#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x18 +#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0_MASK 0x7 +#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0__SHIFT 0x0 +#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0_MASK 0x38 +#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0__SHIFT 0x3 +#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1_MASK 0x1c0 +#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1__SHIFT 0x6 +#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1_MASK 0xe00 +#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1__SHIFT 0x9 +#define MC_SEQ_CNTL_3__REPCG_EN_D0_MASK 0x1000 +#define MC_SEQ_CNTL_3__REPCG_EN_D0__SHIFT 0xc +#define MC_SEQ_CNTL_3__REPCG_EN_D1_MASK 0x2000 +#define MC_SEQ_CNTL_3__REPCG_EN_D1__SHIFT 0xd +#define MC_SEQ_CNTL_3__REPCG_OFF_DLY_MASK 0xf0000 +#define MC_SEQ_CNTL_3__REPCG_OFF_DLY__SHIFT 0x10 +#define MC_SEQ_CNTL_3__FCK_FRC_MASK 0x100000 +#define MC_SEQ_CNTL_3__FCK_FRC__SHIFT 0x14 +#define MC_SEQ_CNTL_3__DBI_FRC_MASK 0x200000 +#define MC_SEQ_CNTL_3__DBI_FRC__SHIFT 0x15 +#define MC_SEQ_CNTL_3__PRGRM_CDC_MASK 0x400000 +#define MC_SEQ_CNTL_3__PRGRM_CDC__SHIFT 0x16 +#define MC_SEQ_CNTL_3__DQS_FRC_MASK 0x800000 +#define MC_SEQ_CNTL_3__DQS_FRC__SHIFT 0x17 +#define MC_SEQ_CNTL_3__DQS_FRC_PAT_MASK 0xf000000 +#define MC_SEQ_CNTL_3__DQS_FRC_PAT__SHIFT 0x18 +#define MC_SEQ_CNTL_3__IDSC_EN_MASK 0x40000000 +#define MC_SEQ_CNTL_3__IDSC_EN__SHIFT 0x1e +#define MC_SEQ_CNTL_3__CAC_EN_MASK 0x80000000 +#define MC_SEQ_CNTL_3__CAC_EN__SHIFT 0x1f +#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 0x1 +#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE__SHIFT 0x0 +#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE_MASK 0x2 +#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE__SHIFT 0x1 +#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY_MASK 0x4 +#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY__SHIFT 0x2 +#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE_MASK 0x8 +#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE__SHIFT 0x3 +#define MC_SEQ_G5PDX_CTRL__TPD2MRS_MASK 0x3f0 +#define MC_SEQ_G5PDX_CTRL__TPD2MRS__SHIFT 0x4 +#define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 0xf000 +#define MC_SEQ_G5PDX_CTRL__TMRS2WCK__SHIFT 0xc +#define MC_SEQ_G5PDX_CTRL__TWCK2MRS_MASK 0xf0000 +#define MC_SEQ_G5PDX_CTRL__TWCK2MRS__SHIFT 0x10 +#define MC_SEQ_G5PDX_CTRL__TMRD_MASK 0xf00000 +#define MC_SEQ_G5PDX_CTRL__TMRD__SHIFT 0x14 +#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE_MASK 0x1 +#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE__SHIFT 0x0 +#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE_MASK 0x2 +#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE__SHIFT 0x1 +#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY_MASK 0x4 +#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY__SHIFT 0x2 +#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE_MASK 0x8 +#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE__SHIFT 0x3 +#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS_MASK 0x3f0 +#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS__SHIFT 0x4 +#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK_MASK 0xf000 +#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK__SHIFT 0xc +#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS_MASK 0xf0000 +#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS__SHIFT 0x10 +#define MC_SEQ_G5PDX_CTRL_LP__TMRD_MASK 0xf00000 +#define MC_SEQ_G5PDX_CTRL_LP__TMRD__SHIFT 0x14 +#define MC_SEQ_G5PDX_CMD0__CMD_MASK 0xffffffff +#define MC_SEQ_G5PDX_CMD0__CMD__SHIFT 0x0 +#define MC_SEQ_G5PDX_CMD0_LP__CMD_MASK 0xffffffff +#define MC_SEQ_G5PDX_CMD0_LP__CMD__SHIFT 0x0 +#define MC_SEQ_G5PDX_CMD1__CMD_MASK 0xffffffff +#define MC_SEQ_G5PDX_CMD1__CMD__SHIFT 0x0 +#define MC_SEQ_G5PDX_CMD1_LP__CMD_MASK 0xffffffff +#define MC_SEQ_G5PDX_CMD1_LP__CMD__SHIFT 0x0 +#define MC_SEQ_SREG_READ__DATA_MASK 0xffffffff +#define MC_SEQ_SREG_READ__DATA__SHIFT 0x0 +#define MC_SEQ_SREG_STATUS__AVAIL_RTN_MASK 0xf +#define MC_SEQ_SREG_STATUS__AVAIL_RTN__SHIFT 0x0 +#define MC_SEQ_SREG_STATUS__PND_RD_MASK 0xf00 +#define MC_SEQ_SREG_STATUS__PND_RD__SHIFT 0x8 +#define MC_SEQ_SREG_STATUS__PND_WR_MASK 0xf000 +#define MC_SEQ_SREG_STATUS__PND_WR__SHIFT 0xc +#define MC_SEQ_PHYREG_BCAST__CH0_EN_MASK 0x1 +#define MC_SEQ_PHYREG_BCAST__CH0_EN__SHIFT 0x0 +#define MC_SEQ_PHYREG_BCAST__CH1_EN_MASK 0x2 +#define MC_SEQ_PHYREG_BCAST__CH1_EN__SHIFT 0x1 +#define MC_SEQ_PHYREG_BCAST__CKE_MASK_MASK 0x80 +#define MC_SEQ_PHYREG_BCAST__CKE_MASK__SHIFT 0x7 +#define MC_SEQ_PHYREG_BCAST__DQ_MASK_MASK 0x100 +#define MC_SEQ_PHYREG_BCAST__DQ_MASK__SHIFT 0x8 +#define MC_SEQ_PHYREG_BCAST__DBI_MASK_MASK 0x200 +#define MC_SEQ_PHYREG_BCAST__DBI_MASK__SHIFT 0x9 +#define MC_SEQ_PHYREG_BCAST__EDC_MASK_MASK 0x400 +#define MC_SEQ_PHYREG_BCAST__EDC_MASK__SHIFT 0xa +#define MC_SEQ_PHYREG_BCAST__WCK_MASK_MASK 0x800 +#define MC_SEQ_PHYREG_BCAST__WCK_MASK__SHIFT 0xb +#define MC_SEQ_PHYREG_BCAST__WCDR_MASK_MASK 0x1000 +#define MC_SEQ_PHYREG_BCAST__WCDR_MASK__SHIFT 0xc +#define MC_SEQ_PHYREG_BCAST__CLK_MASK_MASK 0x2000 +#define MC_SEQ_PHYREG_BCAST__CLK_MASK__SHIFT 0xd +#define MC_SEQ_PHYREG_BCAST__CMD_MASK_MASK 0x4000 +#define MC_SEQ_PHYREG_BCAST__CMD_MASK__SHIFT 0xe +#define MC_SEQ_PHYREG_BCAST__ADR_MASK_MASK 0x8000 +#define MC_SEQ_PHYREG_BCAST__ADR_MASK__SHIFT 0xf +#define MC_SEQ_PMG_DVS_CTL__ENABLE_MASK 0x1 +#define MC_SEQ_PMG_DVS_CTL__ENABLE__SHIFT 0x0 +#define MC_SEQ_PMG_DVS_CTL__TDVS_MASK 0x3e +#define MC_SEQ_PMG_DVS_CTL__TDVS__SHIFT 0x1 +#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE_MASK 0x1 +#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE__SHIFT 0x0 +#define MC_SEQ_PMG_DVS_CTL_LP__TDVS_MASK 0x3e +#define MC_SEQ_PMG_DVS_CTL_LP__TDVS__SHIFT 0x1 +#define MC_SEQ_PMG_DVS_CMD__ADR_MASK 0xffff +#define MC_SEQ_PMG_DVS_CMD__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_DVS_CMD__MOP_MASK 0x70000 +#define MC_SEQ_PMG_DVS_CMD__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_DVS_CMD__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_DVS_CMD__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_DVS_CMD__END_MASK 0x100000 +#define MC_SEQ_PMG_DVS_CMD__END__SHIFT 0x14 +#define MC_SEQ_PMG_DVS_CMD__CSB_MASK 0x600000 +#define MC_SEQ_PMG_DVS_CMD__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1_MASK 0x800000 +#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1__SHIFT 0x17 +#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0_MASK 0x1000000 +#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0__SHIFT 0x18 +#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MASK 0xffff +#define MC_SEQ_PMG_DVS_CMD_LP__ADR__SHIFT 0x0 +#define MC_SEQ_PMG_DVS_CMD_LP__MOP_MASK 0x70000 +#define MC_SEQ_PMG_DVS_CMD_LP__MOP__SHIFT 0x10 +#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB_MASK 0x80000 +#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB__SHIFT 0x13 +#define MC_SEQ_PMG_DVS_CMD_LP__END_MASK 0x100000 +#define MC_SEQ_PMG_DVS_CMD_LP__END__SHIFT 0x14 +#define MC_SEQ_PMG_DVS_CMD_LP__CSB_MASK 0x600000 +#define MC_SEQ_PMG_DVS_CMD_LP__CSB__SHIFT 0x15 +#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1_MASK 0x800000 +#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1__SHIFT 0x17 +#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0_MASK 0x1000000 +#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0__SHIFT 0x18 +#define MC_SEQ_DLL_STBY__EN_MASK 0x1 +#define MC_SEQ_DLL_STBY__EN__SHIFT 0x0 +#define MC_SEQ_DLL_STBY__VCTRLADC_FRC_MASK 0x2 +#define MC_SEQ_DLL_STBY__VCTRLADC_FRC__SHIFT 0x1 +#define MC_SEQ_DLL_STBY__VCTRLADC_VAL_MASK 0x4 +#define MC_SEQ_DLL_STBY__VCTRLADC_VAL__SHIFT 0x2 +#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC_MASK 0x8 +#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC__SHIFT 0x3 +#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL_MASK 0x10 +#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL__SHIFT 0x4 +#define MC_SEQ_DLL_STBY__ENTR_DLY_MASK 0xe0 +#define MC_SEQ_DLL_STBY__ENTR_DLY__SHIFT 0x5 +#define MC_SEQ_DLL_STBY__STBY_DLY_MASK 0xf00 +#define MC_SEQ_DLL_STBY__STBY_DLY__SHIFT 0x8 +#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN_MASK 0xf000 +#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN__SHIFT 0xc +#define MC_SEQ_DLL_STBY__TCKE_EXTN_MASK 0xff0000 +#define MC_SEQ_DLL_STBY__TCKE_EXTN__SHIFT 0x10 +#define MC_SEQ_DLL_STBY__EXIT_DLY_MASK 0x3f000000 +#define MC_SEQ_DLL_STBY__EXIT_DLY__SHIFT 0x18 +#define MC_SEQ_DLL_STBY_LP__EN_MASK 0x1 +#define MC_SEQ_DLL_STBY_LP__EN__SHIFT 0x0 +#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC_MASK 0x2 +#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC__SHIFT 0x1 +#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL_MASK 0x4 +#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL__SHIFT 0x2 +#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC_MASK 0x8 +#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC__SHIFT 0x3 +#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL_MASK 0x10 +#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL__SHIFT 0x4 +#define MC_SEQ_DLL_STBY_LP__ENTR_DLY_MASK 0xe0 +#define MC_SEQ_DLL_STBY_LP__ENTR_DLY__SHIFT 0x5 +#define MC_SEQ_DLL_STBY_LP__STBY_DLY_MASK 0xf00 +#define MC_SEQ_DLL_STBY_LP__STBY_DLY__SHIFT 0x8 +#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN_MASK 0xf000 +#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN__SHIFT 0xc +#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN_MASK 0xff0000 +#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN__SHIFT 0x10 +#define MC_SEQ_DLL_STBY_LP__EXIT_DLY_MASK 0x3f000000 +#define MC_SEQ_DLL_STBY_LP__EXIT_DLY__SHIFT 0x18 +#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS_MASK 0x1 +#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS__SHIFT 0x0 +#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL_MASK 0x2 +#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL__SHIFT 0x1 +#define MC_DLB_MISCCTRL0__LOAD_UDD_MASK 0x4 +#define MC_DLB_MISCCTRL0__LOAD_UDD__SHIFT 0x2 +#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL_MASK 0x8 +#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL__SHIFT 0x3 +#define MC_DLB_MISCCTRL0__DATA_SEL_MASK 0xf0 +#define MC_DLB_MISCCTRL0__DATA_SEL__SHIFT 0x4 +#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT_MASK 0x7f00 +#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT__SHIFT 0x8 +#define MC_DLB_MISCCTRL0__UDD_MASK 0xffff0000 +#define MC_DLB_MISCCTRL0__UDD__SHIFT 0x10 +#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT_MASK 0xffffffff +#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT__SHIFT 0x0 +#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH_MASK 0x1ffff +#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH__SHIFT 0x0 +#define MC_DLB_MISCCTRL2__PRBS_FREERUN_MASK 0x20000 +#define MC_DLB_MISCCTRL2__PRBS_FREERUN__SHIFT 0x11 +#define MC_DLB_MISCCTRL2__PRBS15_MODE_MASK 0x40000 +#define MC_DLB_MISCCTRL2__PRBS15_MODE__SHIFT 0x12 +#define MC_DLB_MISCCTRL2__PRBS23_MODE_MASK 0x80000 +#define MC_DLB_MISCCTRL2__PRBS23_MODE__SHIFT 0x13 +#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR_MASK 0x100000 +#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR__SHIFT 0x14 +#define MC_DLB_MISCCTRL2__STOP_CLK_MASK 0x200000 +#define MC_DLB_MISCCTRL2__STOP_CLK__SHIFT 0x15 +#define MC_DLB_MISCCTRL2__SWEEP_DLY_MASK 0x3000000 +#define MC_DLB_MISCCTRL2__SWEEP_DLY__SHIFT 0x18 +#define MC_DLB_MISCCTRL2__GRAY_CODE_EN_MASK 0x4000000 +#define MC_DLB_MISCCTRL2__GRAY_CODE_EN__SHIFT 0x1a +#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK_MASK 0x10000000 +#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK__SHIFT 0x1c +#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK_MASK 0x20000000 +#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK__SHIFT 0x1d +#define MC_DLB_MISCCTRL2__STATUS_SEL_MASK 0x40000000 +#define MC_DLB_MISCCTRL2__STATUS_SEL__SHIFT 0x1e +#define MC_DLB_CONFIG0__CONF_EN_CH0_MASK 0x1 +#define MC_DLB_CONFIG0__CONF_EN_CH0__SHIFT 0x0 +#define MC_DLB_CONFIG0__CONF_EN_CH1_MASK 0x2 +#define MC_DLB_CONFIG0__CONF_EN_CH1__SHIFT 0x1 +#define MC_DLB_CONFIG0__CONF_AUTO_EN_MASK 0x4 +#define MC_DLB_CONFIG0__CONF_AUTO_EN__SHIFT 0x2 +#define MC_DLB_CONFIG0__MASK_MASK 0xf0 +#define MC_DLB_CONFIG0__MASK__SHIFT 0x4 +#define MC_DLB_CONFIG0__PTR_MASK 0x3ff00 +#define MC_DLB_CONFIG0__PTR__SHIFT 0x8 +#define MC_DLB_CONFIG1__DATA_MASK 0xffffffff +#define MC_DLB_CONFIG1__DATA__SHIFT 0x0 +#define MC_DLB_SETUP__DLB_EN_MASK 0x1 +#define MC_DLB_SETUP__DLB_EN__SHIFT 0x0 +#define MC_DLB_SETUP__DLB_FIFO_EN_MASK 0x2 +#define MC_DLB_SETUP__DLB_FIFO_EN__SHIFT 0x1 +#define MC_DLB_SETUP__DLB_STATUS_EN_MASK 0x4 +#define MC_DLB_SETUP__DLB_STATUS_EN__SHIFT 0x2 +#define MC_DLB_SETUP__DLB_CONFIG_EN_MASK 0x8 +#define MC_DLB_SETUP__DLB_CONFIG_EN__SHIFT 0x3 +#define MC_DLB_SETUP__DLB_PRBS_EN_MASK 0x10 +#define MC_DLB_SETUP__DLB_PRBS_EN__SHIFT 0x4 +#define MC_DLB_SETUP__PRBS_GEN_RST_MASK 0x20 +#define MC_DLB_SETUP__PRBS_GEN_RST__SHIFT 0x5 +#define MC_DLB_SETUP__PRBS_CHK_RST_MASK 0x40 +#define MC_DLB_SETUP__PRBS_CHK_RST__SHIFT 0x6 +#define MC_DLB_SETUP__PRBS_PHY_RST_MASK 0x80 +#define MC_DLB_SETUP__PRBS_PHY_RST__SHIFT 0x7 +#define MC_DLB_SETUP__QDR_MODE_MASK 0x100 +#define MC_DLB_SETUP__QDR_MODE__SHIFT 0x8 +#define MC_DLB_SETUP__CHK_DATA_BITS_MASK 0xff0000 +#define MC_DLB_SETUP__CHK_DATA_BITS__SHIFT 0x10 +#define MC_DLB_SETUP__MEM_BIT_SEL_MASK 0x1f000000 +#define MC_DLB_SETUP__MEM_BIT_SEL__SHIFT 0x18 +#define MC_DLB_SETUP__RXTXLP_EN_MASK 0x80000000 +#define MC_DLB_SETUP__RXTXLP_EN__SHIFT 0x1f +#define MC_DLB_SETUPSWEEP__DLL_RST_MASK 0x1 +#define MC_DLB_SETUPSWEEP__DLL_RST__SHIFT 0x0 +#define MC_DLB_SETUPSWEEP__CONFIG_MASK 0x2 +#define MC_DLB_SETUPSWEEP__CONFIG__SHIFT 0x1 +#define MC_DLB_SETUPSWEEP__MASTER_MASK 0x4 +#define MC_DLB_SETUPSWEEP__MASTER__SHIFT 0x2 +#define MC_DLB_SETUPSWEEP__DLLDLY_MASK 0xf0 +#define MC_DLB_SETUPSWEEP__DLLDLY__SHIFT 0x4 +#define MC_DLB_SETUPSWEEP__DLLSTEPS_MASK 0x1f00 +#define MC_DLB_SETUPSWEEP__DLLSTEPS__SHIFT 0x8 +#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST_MASK 0x1 +#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST__SHIFT 0x0 +#define MC_DLB_SETUPFIFO__READ_FIFO_RST_MASK 0x2 +#define MC_DLB_SETUPFIFO__READ_FIFO_RST__SHIFT 0x1 +#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST_MASK 0x4 +#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST__SHIFT 0x2 +#define MC_DLB_SETUPFIFO__SYNC_RST_MASK 0x8 +#define MC_DLB_SETUPFIFO__SYNC_RST__SHIFT 0x3 +#define MC_DLB_SETUPFIFO__SYNC_RST_MASK_MASK 0x30 +#define MC_DLB_SETUPFIFO__SYNC_RST_MASK__SHIFT 0x4 +#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST_MASK 0x40 +#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST__SHIFT 0x6 +#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR_MASK 0x300 +#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR__SHIFT 0x8 +#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR_MASK 0x1c00 +#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR__SHIFT 0xa +#define MC_DLB_SETUPFIFO__STROBE_MASK 0xf0000 +#define MC_DLB_SETUPFIFO__STROBE__SHIFT 0x10 +#define MC_DLB_WRITE_MASK__BIT_MASK_MASK 0x3fffff +#define MC_DLB_WRITE_MASK__BIT_MASK__SHIFT 0x0 +#define MC_DLB_WRITE_MASK__CH_MASK_MASK 0xf000000 +#define MC_DLB_WRITE_MASK__CH_MASK__SHIFT 0x18 +#define MC_DLB_STATUS__STICK_ERROR_MASK 0xf +#define MC_DLB_STATUS__STICK_ERROR__SHIFT 0x0 +#define MC_DLB_STATUS__LOCK_MASK 0xf0 +#define MC_DLB_STATUS__LOCK__SHIFT 0x4 +#define MC_DLB_STATUS__SWEEP_DONE_MASK 0xf00 +#define MC_DLB_STATUS__SWEEP_DONE__SHIFT 0x8 +#define MC_DLB_STATUS_MISC0__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC0__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC1__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC1__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC2__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC2__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC3__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC3__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC4__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC4__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC5__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC5__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC6__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC6__DATA__SHIFT 0x0 +#define MC_DLB_STATUS_MISC7__DATA_MASK 0xffffffff +#define MC_DLB_STATUS_MISC7__DATA__SHIFT 0x0 +#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff +#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0 +#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00 +#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8 +#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000 +#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10 +#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000 +#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18 +#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff +#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0 +#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00 +#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8 +#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000 +#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10 +#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000 +#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff +#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0 +#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100 +#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8 +#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200 +#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9 +#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400 +#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa +#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800 +#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb +#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000 +#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc +#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000 +#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe +#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000 +#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16 +#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff +#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0 +#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100 +#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8 +#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200 +#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9 +#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400 +#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa +#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800 +#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb +#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000 +#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc +#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000 +#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe +#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000 +#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16 +#define MC_ARB_GRUB_PRIORITY1_RD__CB0_MASK 0x3 +#define MC_ARB_GRUB_PRIORITY1_RD__CB0__SHIFT 0x0 +#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0_MASK 0xc +#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0__SHIFT 0x2 +#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0_MASK 0x30 +#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0__SHIFT 0x4 +#define MC_ARB_GRUB_PRIORITY1_RD__DB0_MASK 0xc0 +#define MC_ARB_GRUB_PRIORITY1_RD__DB0__SHIFT 0x6 +#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0_MASK 0x300 +#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0__SHIFT 0x8 +#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0_MASK 0xc00 +#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0__SHIFT 0xa +#define MC_ARB_GRUB_PRIORITY1_RD__TC0_MASK 0x3000 +#define MC_ARB_GRUB_PRIORITY1_RD__TC0__SHIFT 0xc +#define MC_ARB_GRUB_PRIORITY1_RD__ACPG_MASK 0xc000 +#define MC_ARB_GRUB_PRIORITY1_RD__ACPG__SHIFT 0xe +#define MC_ARB_GRUB_PRIORITY1_RD__ACPO_MASK 0x30000 +#define MC_ARB_GRUB_PRIORITY1_RD__ACPO__SHIFT 0x10 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_MASK 0xc0000 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF__SHIFT 0x12 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0_MASK 0x300000 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0__SHIFT 0x14 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1_MASK 0xc00000 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1__SHIFT 0x16 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW_MASK 0x3000000 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW__SHIFT 0x18 +#define MC_ARB_GRUB_PRIORITY1_RD__MCIF_MASK 0xc000000 +#define MC_ARB_GRUB_PRIORITY1_RD__MCIF__SHIFT 0x1a +#define MC_ARB_GRUB_PRIORITY1_RD__RLC_MASK 0x30000000 +#define MC_ARB_GRUB_PRIORITY1_RD__RLC__SHIFT 0x1c +#define MC_ARB_GRUB_PRIORITY1_RD__VMC_MASK 0xc0000000 +#define MC_ARB_GRUB_PRIORITY1_RD__VMC__SHIFT 0x1e +#define MC_ARB_GRUB_PRIORITY1_WR__CB0_MASK 0x3 +#define MC_ARB_GRUB_PRIORITY1_WR__CB0__SHIFT 0x0 +#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0_MASK 0xc +#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0__SHIFT 0x2 +#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0_MASK 0x30 +#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0__SHIFT 0x4 +#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0_MASK 0xc0 +#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0__SHIFT 0x6 +#define MC_ARB_GRUB_PRIORITY1_WR__DB0_MASK 0x300 +#define MC_ARB_GRUB_PRIORITY1_WR__DB0__SHIFT 0x8 +#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0_MASK 0xc00 +#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0__SHIFT 0xa +#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0_MASK 0x3000 +#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0__SHIFT 0xc +#define MC_ARB_GRUB_PRIORITY1_WR__TC0_MASK 0xc000 +#define MC_ARB_GRUB_PRIORITY1_WR__TC0__SHIFT 0xe +#define MC_ARB_GRUB_PRIORITY1_WR__SH_MASK 0x30000 +#define MC_ARB_GRUB_PRIORITY1_WR__SH__SHIFT 0x10 +#define MC_ARB_GRUB_PRIORITY1_WR__ACPG_MASK 0xc0000 +#define MC_ARB_GRUB_PRIORITY1_WR__ACPG__SHIFT 0x12 +#define MC_ARB_GRUB_PRIORITY1_WR__ACPO_MASK 0x300000 +#define MC_ARB_GRUB_PRIORITY1_WR__ACPO__SHIFT 0x14 +#define MC_ARB_GRUB_PRIORITY1_WR__MCIF_MASK 0xc00000 +#define MC_ARB_GRUB_PRIORITY1_WR__MCIF__SHIFT 0x16 +#define MC_ARB_GRUB_PRIORITY1_WR__RLC_MASK 0x3000000 +#define MC_ARB_GRUB_PRIORITY1_WR__RLC__SHIFT 0x18 +#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1_MASK 0xc000000 +#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1__SHIFT 0x1a +#define MC_ARB_GRUB_PRIORITY1_WR__SMU_MASK 0x30000000 +#define MC_ARB_GRUB_PRIORITY1_WR__SMU__SHIFT 0x1c +#define MC_ARB_GRUB_PRIORITY1_WR__VCE0_MASK 0xc0000000 +#define MC_ARB_GRUB_PRIORITY1_WR__VCE0__SHIFT 0x1e +#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1_MASK 0x3 +#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1__SHIFT 0x0 +#define MC_ARB_GRUB_PRIORITY2_RD__SMU_MASK 0xc +#define MC_ARB_GRUB_PRIORITY2_RD__SMU__SHIFT 0x2 +#define MC_ARB_GRUB_PRIORITY2_RD__VCE0_MASK 0x30 +#define MC_ARB_GRUB_PRIORITY2_RD__VCE0__SHIFT 0x4 +#define MC_ARB_GRUB_PRIORITY2_RD__VCE1_MASK 0xc0 +#define MC_ARB_GRUB_PRIORITY2_RD__VCE1__SHIFT 0x6 +#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM_MASK 0x300 +#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM__SHIFT 0x8 +#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0_MASK 0xc00 +#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0__SHIFT 0xa +#define MC_ARB_GRUB_PRIORITY2_RD__HDP_MASK 0x3000 +#define MC_ARB_GRUB_PRIORITY2_RD__HDP__SHIFT 0xc +#define MC_ARB_GRUB_PRIORITY2_RD__UMC_MASK 0xc000 +#define MC_ARB_GRUB_PRIORITY2_RD__UMC__SHIFT 0xe +#define MC_ARB_GRUB_PRIORITY2_RD__UVD_MASK 0x30000 +#define MC_ARB_GRUB_PRIORITY2_RD__UVD__SHIFT 0x10 +#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0_MASK 0xc0000 +#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0__SHIFT 0x12 +#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1_MASK 0x300000 +#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1__SHIFT 0x14 +#define MC_ARB_GRUB_PRIORITY2_RD__SEM_MASK 0xc00000 +#define MC_ARB_GRUB_PRIORITY2_RD__SEM__SHIFT 0x16 +#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP_MASK 0x3000000 +#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP__SHIFT 0x18 +#define MC_ARB_GRUB_PRIORITY2_RD__VP8_MASK 0xc000000 +#define MC_ARB_GRUB_PRIORITY2_RD__VP8__SHIFT 0x1a +#define MC_ARB_GRUB_PRIORITY2_RD__ISP_MASK 0x30000000 +#define MC_ARB_GRUB_PRIORITY2_RD__ISP__SHIFT 0x1c +#define MC_ARB_GRUB_PRIORITY2_RD__RSV2_MASK 0xc0000000 +#define MC_ARB_GRUB_PRIORITY2_RD__RSV2__SHIFT 0x1e +#define MC_ARB_GRUB_PRIORITY2_WR__VCE1_MASK 0x3 +#define MC_ARB_GRUB_PRIORITY2_WR__VCE1__SHIFT 0x0 +#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP_MASK 0xc +#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP__SHIFT 0x2 +#define MC_ARB_GRUB_PRIORITY2_WR__XDMA_MASK 0x30 +#define MC_ARB_GRUB_PRIORITY2_WR__XDMA__SHIFT 0x4 +#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM_MASK 0xc0 +#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM__SHIFT 0x6 +#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0_MASK 0x300 +#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0__SHIFT 0x8 +#define MC_ARB_GRUB_PRIORITY2_WR__HDP_MASK 0xc00 +#define MC_ARB_GRUB_PRIORITY2_WR__HDP__SHIFT 0xa +#define MC_ARB_GRUB_PRIORITY2_WR__UMC_MASK 0x3000 +#define MC_ARB_GRUB_PRIORITY2_WR__UMC__SHIFT 0xc +#define MC_ARB_GRUB_PRIORITY2_WR__UVD_MASK 0xc000 +#define MC_ARB_GRUB_PRIORITY2_WR__UVD__SHIFT 0xe +#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0_MASK 0x30000 +#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0__SHIFT 0x10 +#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1_MASK 0xc0000 +#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1__SHIFT 0x12 +#define MC_ARB_GRUB_PRIORITY2_WR__XDP_MASK 0x300000 +#define MC_ARB_GRUB_PRIORITY2_WR__XDP__SHIFT 0x14 +#define MC_ARB_GRUB_PRIORITY2_WR__SEM_MASK 0xc00000 +#define MC_ARB_GRUB_PRIORITY2_WR__SEM__SHIFT 0x16 +#define MC_ARB_GRUB_PRIORITY2_WR__IH_MASK 0x3000000 +#define MC_ARB_GRUB_PRIORITY2_WR__IH__SHIFT 0x18 +#define MC_ARB_GRUB_PRIORITY2_WR__VP8_MASK 0xc000000 +#define MC_ARB_GRUB_PRIORITY2_WR__VP8__SHIFT 0x1a +#define MC_ARB_GRUB_PRIORITY2_WR__ISP_MASK 0x30000000 +#define MC_ARB_GRUB_PRIORITY2_WR__ISP__SHIFT 0x1c +#define MC_ARB_GRUB_PRIORITY2_WR__VIN0_MASK 0xc0000000 +#define MC_ARB_GRUB_PRIORITY2_WR__VIN0__SHIFT 0x1e +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x1 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x2 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x10 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x20 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x40 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0xf00 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0xf0000 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 +#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x1fff +#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x1 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x2 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x70 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x80 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0xf00 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x1fff000 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0xff00 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xff000000 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x1 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x2 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x4 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x8 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x10 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0xe0 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0xf00 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x7000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x8000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1fff0000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x1fff +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x2000 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x4000 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x1 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x2 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x4 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x8 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x10 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0xe0 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0xf00 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x7000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x8000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1fff0000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x1fff +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x2000 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x4000 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x1 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x2 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x4 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x8 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x10 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0xe0 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0xf00 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x7000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x8000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1fff0000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x1fff +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x2000 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x4000 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x1 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x2 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x4 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x8 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x10 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0xe0 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0xf00 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x7000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x8000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1fff0000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x1fff +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x2000 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x4000 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x3 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xfc000000 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x1a +#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK_MASK 0xffff +#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0 +#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000 +#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0xff +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xffffffff +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xffffffff +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xffffffff +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xffffffff +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xffffffff +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xffffffff +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xffffffff +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xffffffff +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xffffffff +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x1 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x10 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x20 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x40 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0xf00 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1fff0000 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID_MASK 0xf00 +#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID__SHIFT 0x8 +#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK_MASK 0xffff0000 +#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK__SHIFT 0x10 + +#endif /* GMC_8_1_SH_MASK_H */ -- cgit v1.2.3 From 8f54b7c9eb87f4b11649ec997005af83c53315bb Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:24:40 -0400 Subject: drm/amdgpu: add GMC 8.2 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the GMC (Graphics Memory Controller) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h | 910 +++ .../drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h | 1068 +++ .../drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h | 7850 ++++++++++++++++++++ 3 files changed, 9828 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h new file mode 100644 index 000000000000..06ef7d9b0cb3 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h @@ -0,0 +1,910 @@ +/* + * GMC_8_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_8_2_D_H +#define GMC_8_2_D_H + +#define mmMC_CONFIG 0x800 +#define mmMC_ARB_ATOMIC 0x9be +#define mmMC_ARB_AGE_CNTL 0x9bf +#define mmMC_ARB_RET_CREDITS2 0x9c0 +#define mmMC_ARB_FED_CNTL 0x9c1 +#define mmMC_ARB_GECC2_STATUS 0x9c2 +#define mmMC_ARB_GECC2_MISC 0x9c3 +#define mmMC_ARB_GECC2_DEBUG 0x9c4 +#define mmMC_ARB_GECC2_DEBUG2 0x9c5 +#define mmMC_ARB_PERF_CID 0x9c6 +#define mmMC_ARB_SNOOP 0x9c7 +#define mmMC_ARB_GRUB 0x9c8 +#define mmMC_ARB_GECC2 0x9c9 +#define mmMC_ARB_GECC2_CLI 0x9ca +#define mmMC_ARB_ADDR_SWIZ0 0x9cb +#define mmMC_ARB_ADDR_SWIZ1 0x9cc +#define mmMC_ARB_MISC3 0x9cd +#define mmMC_ARB_GRUB_PROMOTE 0x9ce +#define mmMC_ARB_RTT_DATA 0x9cf +#define mmMC_ARB_RTT_CNTL0 0x9d0 +#define mmMC_ARB_RTT_CNTL1 0x9d1 +#define mmMC_ARB_RTT_CNTL2 0x9d2 +#define mmMC_ARB_RTT_DEBUG 0x9d3 +#define mmMC_ARB_CAC_CNTL 0x9d4 +#define mmMC_ARB_MISC2 0x9d5 +#define mmMC_ARB_MISC 0x9d6 +#define mmMC_ARB_BANKMAP 0x9d7 +#define mmMC_ARB_RAMCFG 0x9d8 +#define mmMC_ARB_POP 0x9d9 +#define mmMC_ARB_MINCLKS 0x9da +#define mmMC_ARB_SQM_CNTL 0x9db +#define mmMC_ARB_ADDR_HASH 0x9dc +#define mmMC_ARB_DRAM_TIMING 0x9dd +#define mmMC_ARB_DRAM_TIMING2 0x9de +#define mmMC_ARB_WTM_CNTL_RD 0x9df +#define mmMC_ARB_WTM_CNTL_WR 0x9e0 +#define mmMC_ARB_WTM_GRPWT_RD 0x9e1 +#define mmMC_ARB_WTM_GRPWT_WR 0x9e2 +#define mmMC_ARB_TM_CNTL_RD 0x9e3 +#define mmMC_ARB_TM_CNTL_WR 0x9e4 +#define mmMC_ARB_LAZY0_RD 0x9e5 +#define mmMC_ARB_LAZY0_WR 0x9e6 +#define mmMC_ARB_LAZY1_RD 0x9e7 +#define mmMC_ARB_LAZY1_WR 0x9e8 +#define mmMC_ARB_AGE_RD 0x9e9 +#define mmMC_ARB_AGE_WR 0x9ea +#define mmMC_ARB_RFSH_CNTL 0x9eb +#define mmMC_ARB_RFSH_RATE 0x9ec +#define mmMC_ARB_PM_CNTL 0x9ed +#define mmMC_ARB_GDEC_RD_CNTL 0x9ee +#define mmMC_ARB_GDEC_WR_CNTL 0x9ef +#define mmMC_ARB_LM_RD 0x9f0 +#define mmMC_ARB_LM_WR 0x9f1 +#define mmMC_ARB_REMREQ 0x9f2 +#define mmMC_ARB_REPLAY 0x9f3 +#define mmMC_ARB_RET_CREDITS_RD 0x9f4 +#define mmMC_ARB_RET_CREDITS_WR 0x9f5 +#define mmMC_ARB_MAX_LAT_CID 0x9f6 +#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7 +#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8 +#define mmMC_ARB_GRUB_REALTIME_RD 0x9f9 +#define mmMC_ARB_CG 0x9fa +#define mmMC_ARB_GRUB_REALTIME_WR 0x9fb +#define mmMC_ARB_DRAM_TIMING_1 0x9fc +#define mmMC_ARB_BUSY_STATUS 0x9fd +#define mmMC_ARB_DRAM_TIMING2_1 0x9ff +#define mmMC_ARB_GRUB2 0xa01 +#define mmMC_ARB_BURST_TIME 0xa02 +#define mmMC_CITF_XTRA_ENABLE 0x96d +#define mmCC_MC_MAX_CHANNEL 0x96e +#define mmMC_CG_CONFIG 0x96f +#define mmMC_CITF_CNTL 0x970 +#define mmMC_CITF_CREDITS_VM 0x971 +#define mmMC_CITF_CREDITS_ARB_RD 0x972 +#define mmMC_CITF_CREDITS_ARB_WR 0x973 +#define mmMC_CITF_DAGB_CNTL 0x974 +#define mmMC_CITF_INT_CREDITS 0x975 +#define mmMC_CITF_RET_MODE 0x976 +#define mmMC_CITF_DAGB_DLY 0x977 +#define mmMC_RD_GRP_EXT 0x978 +#define mmMC_WR_GRP_EXT 0x979 +#define mmMC_CITF_REMREQ 0x97a +#define mmMC_WR_TC0 0x97b +#define mmMC_WR_TC1 0x97c +#define mmMC_CITF_INT_CREDITS_WR 0x97d +#define mmMC_CITF_CREDITS_ARB_RD2 0x97e +#define mmMC_CITF_WTM_RD_CNTL 0x97f +#define mmMC_CITF_WTM_WR_CNTL 0x980 +#define mmMC_RD_CB 0x981 +#define mmMC_RD_DB 0x982 +#define mmMC_RD_TC0 0x983 +#define mmMC_RD_TC1 0x984 +#define mmMC_RD_HUB 0x985 +#define mmMC_WR_CB 0x986 +#define mmMC_WR_DB 0x987 +#define mmMC_WR_HUB 0x988 +#define mmMC_CITF_CREDITS_XBAR 0x989 +#define mmMC_RD_GRP_LCL 0x98a +#define mmMC_WR_GRP_LCL 0x98b +#define mmMC_CITF_PERF_MON_CNTL2 0x98e +#define mmMC_CITF_PERF_MON_RSLT2 0x991 +#define mmMC_CITF_MISC_RD_CG 0x992 +#define mmMC_CITF_MISC_WR_CG 0x993 +#define mmMC_CITF_MISC_VM_CG 0x994 +#define mmMC_HUB_MISC_POWER 0x82d +#define mmMC_HUB_MISC_HUB_CG 0x82e +#define mmMC_HUB_MISC_VM_CG 0x82f +#define mmMC_HUB_MISC_SIP_CG 0x830 +#define mmMC_HUB_MISC_STATUS 0x832 +#define mmMC_HUB_MISC_OVERRIDE 0x833 +#define mmMC_HUB_MISC_FRAMING 0x834 +#define mmMC_HUB_WDP_CNTL 0x835 +#define mmMC_HUB_WDP_ERR 0x836 +#define mmMC_HUB_WDP_BP 0x837 +#define mmMC_HUB_WDP_STATUS 0x838 +#define mmMC_HUB_RDREQ_STATUS 0x839 +#define mmMC_HUB_WRRET_STATUS 0x83a +#define mmMC_HUB_RDREQ_CNTL 0x83b +#define mmMC_HUB_WRRET_CNTL 0x83c +#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d +#define mmMC_HUB_WDP_WTM_CNTL 0x83e +#define mmMC_HUB_WDP_CREDITS 0x83f +#define mmMC_HUB_WDP_CREDITS2 0x840 +#define mmMC_HUB_WDP_GBL0 0x841 +#define mmMC_HUB_WDP_GBL1 0x842 +#define mmMC_HUB_RDREQ_CREDITS 0x844 +#define mmMC_HUB_RDREQ_CREDITS2 0x845 +#define mmMC_HUB_SHARED_DAGB_DLY 0x846 +#define mmMC_HUB_MISC_IDLE_STATUS 0x847 +#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848 +#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849 +#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a +#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b +#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c +#define mmMC_HUB_WDP_SH2 0x84d +#define mmMC_HUB_WDP_SH3 0x84e +#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS 0x84f +#define mmMC_HUB_RDREQ_MCDW 0x851 +#define mmMC_HUB_RDREQ_MCDX 0x852 +#define mmMC_HUB_RDREQ_MCDY 0x853 +#define mmMC_HUB_RDREQ_MCDZ 0x854 +#define mmMC_HUB_RDREQ_SIP 0x855 +#define mmMC_HUB_RDREQ_GBL0 0x856 +#define mmMC_HUB_RDREQ_GBL1 0x857 +#define mmMC_HUB_RDREQ_SMU 0x858 +#define mmMC_HUB_RDREQ_SDMA0 0x859 +#define mmMC_HUB_RDREQ_HDP 0x85a +#define mmMC_HUB_RDREQ_SDMA1 0x85b +#define mmMC_HUB_RDREQ_RLC 0x85c +#define mmMC_HUB_RDREQ_SEM 0x85d +#define mmMC_HUB_RDREQ_VCE0 0x85e +#define mmMC_HUB_RDREQ_UMC 0x85f +#define mmMC_HUB_RDREQ_UVD 0x860 +#define mmMC_HUB_RDREQ_DMIF 0x862 +#define mmMC_HUB_RDREQ_MCIF 0x863 +#define mmMC_HUB_RDREQ_VMC 0x864 +#define mmMC_HUB_RDREQ_VCEU0 0x865 +#define mmMC_HUB_WDP_MCDW 0x866 +#define mmMC_HUB_WDP_MCDX 0x867 +#define mmMC_HUB_WDP_MCDY 0x868 +#define mmMC_HUB_WDP_MCDZ 0x869 +#define mmMC_HUB_WDP_SIP 0x86a +#define mmMC_HUB_WDP_SDMA1 0x86b +#define mmMC_HUB_WDP_SH0 0x86c +#define mmMC_HUB_WDP_MCIF 0x86d +#define mmMC_HUB_WDP_VCE0 0x86e +#define mmMC_HUB_WDP_XDP 0x86f +#define mmMC_HUB_WDP_IH 0x870 +#define mmMC_HUB_WDP_RLC 0x871 +#define mmMC_HUB_WDP_SEM 0x872 +#define mmMC_HUB_WDP_SMU 0x873 +#define mmMC_HUB_WDP_SH1 0x874 +#define mmMC_HUB_WDP_UMC 0x875 +#define mmMC_HUB_WDP_UVD 0x876 +#define mmMC_HUB_WDP_HDP 0x877 +#define mmMC_HUB_WDP_SDMA0 0x878 +#define mmMC_HUB_WRRET_MCDW 0x879 +#define mmMC_HUB_WRRET_MCDX 0x87a +#define mmMC_HUB_WRRET_MCDY 0x87b +#define mmMC_HUB_WRRET_MCDZ 0x87c +#define mmMC_HUB_WDP_VCEU0 0x87d +#define mmMC_HUB_WDP_XDMAM 0x87e +#define mmMC_HUB_WDP_XDMA 0x87f +#define mmMC_HUB_RDREQ_XDMAM 0x880 +#define mmMC_HUB_RDREQ_ACPG 0x881 +#define mmMC_HUB_RDREQ_ACPO 0x882 +#define mmMC_HUB_RDREQ_SAMMSP 0x883 +#define mmMC_HUB_RDREQ_VP8 0x884 +#define mmMC_HUB_RDREQ_VP8U 0x885 +#define mmMC_HUB_WDP_ACPG 0x886 +#define mmMC_HUB_WDP_ACPO 0x887 +#define mmMC_HUB_WDP_SAMMSP 0x888 +#define mmMC_HUB_WDP_VP8 0x889 +#define mmMC_HUB_WDP_VP8U 0x88a +#define mmMC_HUB_RDREQ_ISP_SPM 0xde0 +#define mmMC_HUB_RDREQ_ISP_MPM 0xde1 +#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2 +#define mmMC_HUB_WDP_ISP_SPM 0xde3 +#define mmMC_HUB_WDP_ISP_MPS 0xde4 +#define mmMC_HUB_WDP_ISP_MPM 0xde5 +#define mmMC_HUB_WDP_ISP_CCPU 0xde6 +#define mmMC_HUB_RDREQ_MCDS 0xde7 +#define mmMC_HUB_RDREQ_MCDT 0xde8 +#define mmMC_HUB_RDREQ_MCDU 0xde9 +#define mmMC_HUB_RDREQ_MCDV 0xdea +#define mmMC_HUB_WDP_MCDS 0xdeb +#define mmMC_HUB_WDP_MCDT 0xdec +#define mmMC_HUB_WDP_MCDU 0xded +#define mmMC_HUB_WDP_MCDV 0xdee +#define mmMC_HUB_WRRET_MCDS 0xdef +#define mmMC_HUB_WRRET_MCDT 0xdf0 +#define mmMC_HUB_WRRET_MCDU 0xdf1 +#define mmMC_HUB_WRRET_MCDV 0xdf2 +#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3 +#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4 +#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5 +#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6 +#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7 +#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8 +#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9 +#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa +#define mmMC_HUB_WDP_BP2 0xdfb +#define mmMC_HUB_RDREQ_VCE1 0xdfc +#define mmMC_HUB_RDREQ_VCEU1 0xdfd +#define mmMC_HUB_WDP_VCE1 0xdfe +#define mmMC_HUB_WDP_VCEU1 0xdff +#define mmMC_RPB_CONF 0x94d +#define mmMC_RPB_IF_CONF 0x94e +#define mmMC_RPB_DBG1 0x94f +#define mmMC_RPB_EFF_CNTL 0x950 +#define mmMC_RPB_ARB_CNTL 0x951 +#define mmMC_RPB_BIF_CNTL 0x952 +#define mmMC_RPB_WR_SWITCH_CNTL 0x953 +#define mmMC_RPB_WR_COMBINE_CNTL 0x954 +#define mmMC_RPB_RD_SWITCH_CNTL 0x955 +#define mmMC_RPB_CID_QUEUE_WR 0x956 +#define mmMC_RPB_CID_QUEUE_RD 0x957 +#define mmMC_RPB_PERF_COUNTER_CNTL 0x958 +#define mmMC_RPB_PERF_COUNTER_STATUS 0x959 +#define mmMC_RPB_CID_QUEUE_EX 0x95a +#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b +#define mmMC_RPB_TCI_CNTL 0x95c +#define mmMC_RPB_TCI_CNTL2 0x95d +#define mmMC_SHARED_CHMAP 0x801 +#define mmMC_SHARED_CHREMAP 0x802 +#define mmMC_RD_GRP_GFX 0x803 +#define mmMC_WR_GRP_GFX 0x804 +#define mmMC_RD_GRP_SYS 0x805 +#define mmMC_WR_GRP_SYS 0x806 +#define mmMC_RD_GRP_OTH 0x807 +#define mmMC_WR_GRP_OTH 0x808 +#define mmMC_VM_FB_LOCATION 0x809 +#define mmMC_VM_AGP_TOP 0x80a +#define mmMC_VM_AGP_BOT 0x80b +#define mmMC_VM_AGP_BASE 0x80c +#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d +#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e +#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f +#define mmMC_VM_DC_WRITE_CNTL 0x810 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814 +#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815 +#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816 +#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817 +#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818 +#define mmMC_VM_MX_L1_TLB_CNTL 0x819 +#define mmMC_VM_FB_OFFSET 0x81a +#define mmMC_VM_STEERING 0x81b +#define mmMC_SHARED_CHREMAP2 0x81c +#define mmMC_SHARED_VF_ENABLE 0x81d +#define mmMC_SHARED_VIRT_RESET_REQ 0x81e +#define mmMC_SHARED_ACTIVE_FCN_ID 0x81f +#define mmMC_CONFIG_MCD 0x828 +#define mmMC_CG_CONFIG_MCD 0x829 +#define mmMC_MEM_POWER_LS 0x82a +#define mmMC_SHARED_BLACKOUT_CNTL 0x82b +#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891 +#define mmMC_VM_MB_L1_TLB1_DEBUG 0x892 +#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893 +#define mmMC_VM_MB_L1_TLB0_STATUS 0x895 +#define mmMC_VM_MB_L1_TLB1_STATUS 0x896 +#define mmMC_VM_MB_L1_TLB2_STATUS 0x897 +#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1 +#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5 +#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6 +#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998 +#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999 +#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a +#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b +#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c +#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d +#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4 +#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7 +#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8 +#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd +#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce +#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf +#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0 +#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1 +#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2 +#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3 +#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4 +#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5 +#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9 +#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da +#define mmMC_XPB_RTR_DEST_MAP0 0x8db +#define mmMC_XPB_RTR_DEST_MAP1 0x8dc +#define mmMC_XPB_RTR_DEST_MAP2 0x8dd +#define mmMC_XPB_RTR_DEST_MAP3 0x8de +#define mmMC_XPB_RTR_DEST_MAP4 0x8df +#define mmMC_XPB_RTR_DEST_MAP5 0x8e0 +#define mmMC_XPB_RTR_DEST_MAP6 0x8e1 +#define mmMC_XPB_RTR_DEST_MAP7 0x8e2 +#define mmMC_XPB_RTR_DEST_MAP8 0x8e3 +#define mmMC_XPB_RTR_DEST_MAP9 0x8e4 +#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5 +#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6 +#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7 +#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8 +#define mmMC_XPB_CLG_CFG0 0x8e9 +#define mmMC_XPB_CLG_CFG1 0x8ea +#define mmMC_XPB_CLG_CFG2 0x8eb +#define mmMC_XPB_CLG_CFG3 0x8ec +#define mmMC_XPB_CLG_CFG4 0x8ed +#define mmMC_XPB_CLG_CFG5 0x8ee +#define mmMC_XPB_CLG_CFG6 0x8ef +#define mmMC_XPB_CLG_CFG7 0x8f0 +#define mmMC_XPB_CLG_CFG8 0x8f1 +#define mmMC_XPB_CLG_CFG9 0x8f2 +#define mmMC_XPB_CLG_CFG10 0x8f3 +#define mmMC_XPB_CLG_CFG11 0x8f4 +#define mmMC_XPB_CLG_CFG12 0x8f5 +#define mmMC_XPB_CLG_CFG13 0x8f6 +#define mmMC_XPB_CLG_CFG14 0x8f7 +#define mmMC_XPB_CLG_CFG15 0x8f8 +#define mmMC_XPB_CLG_CFG16 0x8f9 +#define mmMC_XPB_CLG_CFG17 0x8fa +#define mmMC_XPB_CLG_CFG18 0x8fb +#define mmMC_XPB_CLG_CFG19 0x8fc +#define mmMC_XPB_CLG_EXTRA 0x8fd +#define mmMC_XPB_LB_ADDR 0x8fe +#define mmMC_XPB_UNC_THRESH_HST 0x8ff +#define mmMC_XPB_UNC_THRESH_SID 0x900 +#define mmMC_XPB_WCB_STS 0x901 +#define mmMC_XPB_WCB_CFG 0x902 +#define mmMC_XPB_P2P_BAR_CFG 0x903 +#define mmMC_XPB_P2P_BAR0 0x904 +#define mmMC_XPB_P2P_BAR1 0x905 +#define mmMC_XPB_P2P_BAR2 0x906 +#define mmMC_XPB_P2P_BAR3 0x907 +#define mmMC_XPB_P2P_BAR4 0x908 +#define mmMC_XPB_P2P_BAR5 0x909 +#define mmMC_XPB_P2P_BAR6 0x90a +#define mmMC_XPB_P2P_BAR7 0x90b +#define mmMC_XPB_P2P_BAR_SETUP 0x90c +#define mmMC_XPB_P2P_BAR_DEBUG 0x90d +#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e +#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f +#define mmMC_XPB_PEER_SYS_BAR0 0x910 +#define mmMC_XPB_PEER_SYS_BAR1 0x911 +#define mmMC_XPB_PEER_SYS_BAR2 0x912 +#define mmMC_XPB_PEER_SYS_BAR3 0x913 +#define mmMC_XPB_PEER_SYS_BAR4 0x914 +#define mmMC_XPB_PEER_SYS_BAR5 0x915 +#define mmMC_XPB_PEER_SYS_BAR6 0x916 +#define mmMC_XPB_PEER_SYS_BAR7 0x917 +#define mmMC_XPB_PEER_SYS_BAR8 0x918 +#define mmMC_XPB_PEER_SYS_BAR9 0x919 +#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a +#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b +#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c +#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d +#define mmMC_XPB_CLK_GAT 0x91e +#define mmMC_XPB_INTF_CFG 0x91f +#define mmMC_XPB_INTF_STS 0x920 +#define mmMC_XPB_PIPE_STS 0x921 +#define mmMC_XPB_SUB_CTRL 0x922 +#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923 +#define mmMC_XPB_PERF_KNOBS 0x924 +#define mmMC_XPB_STICKY 0x925 +#define mmMC_XPB_STICKY_W1C 0x926 +#define mmMC_XPB_MISC_CFG 0x927 +#define mmMC_XPB_CLG_CFG20 0x928 +#define mmMC_XPB_CLG_CFG21 0x929 +#define mmMC_XPB_CLG_CFG22 0x92a +#define mmMC_XPB_CLG_CFG23 0x92b +#define mmMC_XPB_CLG_CFG24 0x92c +#define mmMC_XPB_CLG_CFG25 0x92d +#define mmMC_XPB_CLG_CFG26 0x92e +#define mmMC_XPB_CLG_CFG27 0x92f +#define mmMC_XPB_CLG_CFG28 0x930 +#define mmMC_XPB_CLG_CFG29 0x931 +#define mmMC_XPB_CLG_CFG30 0x932 +#define mmMC_XPB_CLG_CFG31 0x933 +#define mmMC_XPB_INTF_CFG2 0x934 +#define mmMC_XPB_CLG_EXTRA_RD 0x935 +#define mmMC_XPB_CLG_CFG32 0x936 +#define mmMC_XPB_CLG_CFG33 0x937 +#define mmMC_XPB_CLG_CFG34 0x938 +#define mmMC_XPB_CLG_CFG35 0x939 +#define mmMC_XPB_CLG_CFG36 0x93a +#define mmMC_XBAR_ADDR_DEC 0xc80 +#define mmMC_XBAR_REMOTE 0xc81 +#define mmMC_XBAR_WRREQ_CREDIT 0xc82 +#define mmMC_XBAR_RDREQ_CREDIT 0xc83 +#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84 +#define mmMC_XBAR_WRRET_CREDIT1 0xc85 +#define mmMC_XBAR_WRRET_CREDIT2 0xc86 +#define mmMC_XBAR_RDRET_CREDIT1 0xc87 +#define mmMC_XBAR_RDRET_CREDIT2 0xc88 +#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89 +#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a +#define mmMC_XBAR_CHTRIREMAP 0xc8b +#define mmMC_XBAR_TWOCHAN 0xc8c +#define mmMC_XBAR_ARB 0xc8d +#define mmMC_XBAR_ARB_MAX_BURST 0xc8e +#define mmMC_XBAR_FIFO_MON_CNTL0 0xc8f +#define mmMC_XBAR_FIFO_MON_CNTL1 0xc90 +#define mmMC_XBAR_FIFO_MON_CNTL2 0xc91 +#define mmMC_XBAR_FIFO_MON_RSLT0 0xc92 +#define mmMC_XBAR_FIFO_MON_RSLT1 0xc93 +#define mmMC_XBAR_FIFO_MON_RSLT2 0xc94 +#define mmMC_XBAR_FIFO_MON_RSLT3 0xc95 +#define mmMC_XBAR_FIFO_MON_MAX_THSH 0xc96 +#define mmMC_XBAR_SPARE0 0xc97 +#define mmMC_XBAR_SPARE1 0xc98 +#define mmMC_CITF_PERFCOUNTER_LO 0x7a0 +#define mmMC_HUB_PERFCOUNTER_LO 0x7a1 +#define mmMC_RPB_PERFCOUNTER_LO 0x7a2 +#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3 +#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4 +#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5 +#define mmMC_ARB_PERFCOUNTER_LO 0x7a6 +#define mmATC_PERFCOUNTER_LO 0x7a7 +#define mmMC_CITF_PERFCOUNTER_HI 0x7a8 +#define mmMC_HUB_PERFCOUNTER_HI 0x7a9 +#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa +#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab +#define mmMC_RPB_PERFCOUNTER_HI 0x7ac +#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad +#define mmMC_ARB_PERFCOUNTER_HI 0x7ae +#define mmATC_PERFCOUNTER_HI 0x7af +#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0 +#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1 +#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2 +#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3 +#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4 +#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5 +#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6 +#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7 +#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8 +#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9 +#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba +#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb +#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc +#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd +#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be +#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf +#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0 +#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1 +#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2 +#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3 +#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4 +#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5 +#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6 +#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7 +#define mmATC_PERFCOUNTER0_CFG 0x7c8 +#define mmATC_PERFCOUNTER1_CFG 0x7c9 +#define mmATC_PERFCOUNTER2_CFG 0x7ca +#define mmATC_PERFCOUNTER3_CFG 0x7cb +#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc +#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd +#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce +#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf +#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0 +#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1 +#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2 +#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3 +#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4 +#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5 +#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6 +#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7 +#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8 +#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9 +#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da +#define mmMC_GRUB_PERFCOUNTER_LO 0x7e4 +#define mmMC_GRUB_PERFCOUNTER_HI 0x7e5 +#define mmMC_GRUB_PERFCOUNTER0_CFG 0x7e6 +#define mmMC_GRUB_PERFCOUNTER1_CFG 0x7e7 +#define mmMC_GRUB_PERFCOUNTER_RSLT_CNTL 0x7e8 +#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0 +#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1 +#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2 +#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3 +#define mmATC_VM_APERTURE0_CNTL 0xcc4 +#define mmATC_VM_APERTURE1_CNTL 0xcc5 +#define mmATC_VM_APERTURE0_CNTL2 0xcc6 +#define mmATC_VM_APERTURE1_CNTL2 0xcc7 +#define mmATC_ATS_CNTL 0xcc9 +#define mmATC_ATS_DEBUG 0xcca +#define mmATC_ATS_FAULT_DEBUG 0xccb +#define mmATC_ATS_STATUS 0xccc +#define mmATC_ATS_FAULT_CNTL 0xccd +#define mmATC_ATS_FAULT_STATUS_INFO 0xcce +#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf +#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0 +#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1 +#define mmATC_ATS_FAULT_STATUS_INFO2 0xcd2 +#define mmATC_MISC_CG 0xcd4 +#define mmATC_L2_CNTL 0xcd5 +#define mmATC_L2_CNTL2 0xcd6 +#define mmATC_L2_DEBUG 0xcd7 +#define mmATC_L2_DEBUG2 0xcd8 +#define mmATC_L2_CACHE_DATA0 0xcd9 +#define mmATC_L2_CACHE_DATA1 0xcda +#define mmATC_L2_CACHE_DATA2 0xcdb +#define mmATC_L1_CNTL 0xcdc +#define mmATC_L1_ADDRESS_OFFSET 0xcdd +#define mmATC_L1RD_DEBUG_TLB 0xcde +#define mmATC_L1WR_DEBUG_TLB 0xcdf +#define mmATC_L1RD_STATUS 0xce0 +#define mmATC_L1WR_STATUS 0xce1 +#define mmATC_L1RD_DEBUG2_TLB 0xce2 +#define mmATC_L1WR_DEBUG2_TLB 0xce3 +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6 +#define mmATC_VMID0_PASID_MAPPING 0xce7 +#define mmATC_VMID1_PASID_MAPPING 0xce8 +#define mmATC_VMID2_PASID_MAPPING 0xce9 +#define mmATC_VMID3_PASID_MAPPING 0xcea +#define mmATC_VMID4_PASID_MAPPING 0xceb +#define mmATC_VMID5_PASID_MAPPING 0xcec +#define mmATC_VMID6_PASID_MAPPING 0xced +#define mmATC_VMID7_PASID_MAPPING 0xcee +#define mmATC_VMID8_PASID_MAPPING 0xcef +#define mmATC_VMID9_PASID_MAPPING 0xcf0 +#define mmATC_VMID10_PASID_MAPPING 0xcf1 +#define mmATC_VMID11_PASID_MAPPING 0xcf2 +#define mmATC_VMID12_PASID_MAPPING 0xcf3 +#define mmATC_VMID13_PASID_MAPPING 0xcf4 +#define mmATC_VMID14_PASID_MAPPING 0xcf5 +#define mmATC_VMID15_PASID_MAPPING 0xcf6 +#define mmATC_ATS_VMID_STATUS 0xd07 +#define mmATC_ATS_SMU_STATUS 0xd08 +#define mmATC_L2_CNTL3 0xd09 +#define mmATC_L2_STATUS 0xd0a +#define mmATC_L2_STATUS2 0xd0b +#define mmGMCON_RENG_RAM_INDEX 0xd40 +#define mmGMCON_RENG_RAM_DATA 0xd41 +#define mmGMCON_RENG_EXECUTE 0xd42 +#define mmGMCON_MISC 0xd43 +#define mmGMCON_MISC2 0xd44 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46 +#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48 +#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49 +#define mmGMCON_PERF_MON_CNTL0 0xd4a +#define mmGMCON_PERF_MON_CNTL1 0xd4b +#define mmGMCON_PERF_MON_RSLT0 0xd4c +#define mmGMCON_PERF_MON_RSLT1 0xd4d +#define mmGMCON_PGFSM_CONFIG 0xd4e +#define mmGMCON_PGFSM_WRITE 0xd4f +#define mmGMCON_PGFSM_READ 0xd50 +#define mmGMCON_MISC3 0xd51 +#define mmGMCON_MASK 0xd52 +#define mmGMCON_LPT_TARGET 0xd53 +#define mmGMCON_DEBUG 0xd5f +#define mmVM_L2_CNTL 0x500 +#define mmVM_L2_CNTL2 0x501 +#define mmVM_L2_CNTL3 0x502 +#define mmVM_L2_STATUS 0x503 +#define mmVM_CONTEXT0_CNTL 0x504 +#define mmVM_CONTEXT1_CNTL 0x505 +#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506 +#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507 +#define mmVM_CONTEXT0_CNTL2 0x50c +#define mmVM_CONTEXT1_CNTL2 0x50d +#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e +#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f +#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 +#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 +#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 +#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 +#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 +#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 +#define mmVM_INVALIDATE_REQUEST 0x51e +#define mmVM_INVALIDATE_RESPONSE 0x51f +#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c +#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d +#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e +#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f +#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530 +#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531 +#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532 +#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533 +#define mmVM_PRT_CNTL 0x534 +#define mmVM_CONTEXTS_DISABLE 0x535 +#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536 +#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 +#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538 +#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539 +#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e +#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f +#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 +#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 +#define mmVM_FAULT_CLIENT_ID 0x54e +#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f +#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 +#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 +#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 +#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 +#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 +#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 +#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 +#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 +#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 +#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f +#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 +#define mmVM_DEBUG 0x56f +#define mmVM_L2_CG 0x570 +#define mmVM_L2_BANK_SELECT_MASKA 0x572 +#define mmVM_L2_BANK_SELECT_MASKB 0x573 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575 +#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576 +#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577 +#define mmVM_L2_CNTL4 0x578 +#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x579 +#define mmMC_VM_FB_SIZE_OFFSET_VF0 0xf980 +#define mmMC_VM_FB_SIZE_OFFSET_VF1 0xf981 +#define mmMC_VM_FB_SIZE_OFFSET_VF2 0xf982 +#define mmMC_VM_FB_SIZE_OFFSET_VF3 0xf983 +#define mmMC_VM_FB_SIZE_OFFSET_VF4 0xf984 +#define mmMC_VM_FB_SIZE_OFFSET_VF5 0xf985 +#define mmMC_VM_FB_SIZE_OFFSET_VF6 0xf986 +#define mmMC_VM_FB_SIZE_OFFSET_VF7 0xf987 +#define mmMC_VM_FB_SIZE_OFFSET_VF8 0xf988 +#define mmMC_VM_FB_SIZE_OFFSET_VF9 0xf989 +#define mmMC_VM_FB_SIZE_OFFSET_VF10 0xf98a +#define mmMC_VM_FB_SIZE_OFFSET_VF11 0xf98b +#define mmMC_VM_FB_SIZE_OFFSET_VF12 0xf98c +#define mmMC_VM_FB_SIZE_OFFSET_VF13 0xf98d +#define mmMC_VM_FB_SIZE_OFFSET_VF14 0xf98e +#define mmMC_VM_FB_SIZE_OFFSET_VF15 0xf98f +#define mmMC_VM_NB_MMIOBASE 0xf990 +#define mmMC_VM_NB_MMIOLIMIT 0xf991 +#define mmMC_VM_NB_PCI_CTRL 0xf992 +#define mmMC_VM_NB_PCI_ARB 0xf993 +#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0xf994 +#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0xf995 +#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0xf996 +#define mmMC_VM_NB_TOP_OF_DRAM3 0xf997 +#define mmMC_VM_MARC_BASE_LO_0 0xf998 +#define mmMC_VM_MARC_BASE_LO_1 0xf99e +#define mmMC_VM_MARC_BASE_LO_2 0xf9a4 +#define mmMC_VM_MARC_BASE_LO_3 0xf9aa +#define mmMC_VM_MARC_BASE_HI_0 0xf999 +#define mmMC_VM_MARC_BASE_HI_1 0xf99f +#define mmMC_VM_MARC_BASE_HI_2 0xf9a5 +#define mmMC_VM_MARC_BASE_HI_3 0xf9ab +#define mmMC_VM_MARC_RELOC_LO_0 0xf99a +#define mmMC_VM_MARC_RELOC_LO_1 0xf9a0 +#define mmMC_VM_MARC_RELOC_LO_2 0xf9a6 +#define mmMC_VM_MARC_RELOC_LO_3 0xf9ac +#define mmMC_VM_MARC_RELOC_HI_0 0xf99b +#define mmMC_VM_MARC_RELOC_HI_1 0xf9a1 +#define mmMC_VM_MARC_RELOC_HI_2 0xf9a7 +#define mmMC_VM_MARC_RELOC_HI_3 0xf9ad +#define mmMC_VM_MARC_LEN_LO_0 0xf99c +#define mmMC_VM_MARC_LEN_LO_1 0xf9a2 +#define mmMC_VM_MARC_LEN_LO_2 0xf9a8 +#define mmMC_VM_MARC_LEN_LO_3 0xf9ae +#define mmMC_VM_MARC_LEN_HI_0 0xf99d +#define mmMC_VM_MARC_LEN_HI_1 0xf9a3 +#define mmMC_VM_MARC_LEN_HI_2 0xf9a9 +#define mmMC_VM_MARC_LEN_HI_3 0xf9af +#define mmMC_VM_MARC_CNTL 0xf9b0 +#define mmMC_ARB_HARSH_EN_RD 0xdc0 +#define mmMC_ARB_HARSH_EN_WR 0xdc1 +#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2 +#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3 +#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4 +#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5 +#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6 +#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7 +#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8 +#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9 +#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca +#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb +#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc +#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd +#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce +#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf +#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0 +#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1 +#define mmMC_ARB_HARSH_SAT0_RD 0xdd2 +#define mmMC_ARB_HARSH_SAT0_WR 0xdd3 +#define mmMC_ARB_HARSH_SAT1_RD 0xdd4 +#define mmMC_ARB_HARSH_SAT1_WR 0xdd5 +#define mmMC_ARB_HARSH_CTL_RD 0xdd6 +#define mmMC_ARB_HARSH_CTL_WR 0xdd7 +#define mmMC_ARB_GRUB_PRIORITY1_RD 0xdd8 +#define mmMC_ARB_GRUB_PRIORITY1_WR 0xdd9 +#define mmMC_ARB_GRUB_PRIORITY2_RD 0xdda +#define mmMC_ARB_GRUB_PRIORITY2_WR 0xddb +#define mmMC_FUS_DRAM0_CS0_BASE 0xa05 +#define mmMC_FUS_DRAM1_CS0_BASE 0xa06 +#define mmMC_FUS_DRAM0_CS1_BASE 0xa07 +#define mmMC_FUS_DRAM1_CS1_BASE 0xa08 +#define mmMC_FUS_DRAM0_CS2_BASE 0xa09 +#define mmMC_FUS_DRAM1_CS2_BASE 0xa0a +#define mmMC_FUS_DRAM0_CS3_BASE 0xa0b +#define mmMC_FUS_DRAM1_CS3_BASE 0xa0c +#define mmMC_FUS_DRAM0_CS01_MASK 0xa0d +#define mmMC_FUS_DRAM1_CS01_MASK 0xa0e +#define mmMC_FUS_DRAM0_CS23_MASK 0xa0f +#define mmMC_FUS_DRAM1_CS23_MASK 0xa10 +#define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING 0xa11 +#define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING 0xa12 +#define mmMC_FUS_DRAM0_CTL_BASE 0xa13 +#define mmMC_FUS_DRAM1_CTL_BASE 0xa14 +#define mmMC_FUS_DRAM0_CTL_LIMIT 0xa15 +#define mmMC_FUS_DRAM1_CTL_LIMIT 0xa16 +#define mmMC_FUS_DRAM_CTL_HIGH_01 0xa17 +#define mmMC_FUS_DRAM_CTL_HIGH_23 0xa18 +#define mmMC_FUS_DRAM_MODE 0xa19 +#define mmMC_FUS_DRAM_APER_BASE 0xa1a +#define mmMC_FUS_DRAM_APER_TOP 0xa1b +#define mmMC_FUS_DRAM_APER_DEF 0xa1e +#define mmMC_FUS_ARB_GARLIC_ISOC_PRI 0xa1f +#define mmMC_FUS_ARB_GARLIC_CNTL 0xa20 +#define mmMC_FUS_ARB_GARLIC_WR_PRI 0xa21 +#define mmMC_FUS_ARB_GARLIC_WR_PRI2 0xa22 +#define mmMC_CG_DATAPORT 0xa32 +#define mmMC_GRUB_PROBE_MAP 0xa33 +#define mmMC_GRUB_POST_PROBE_DELAY 0xa34 +#define mmMC_GRUB_PROBE_CREDITS 0xa35 +#define mmMC_GRUB_FEATURES 0xa36 +#define mmMC_GRUB_TX_CREDITS 0xa37 +#define mmMC_GRUB_TCB_INDEX 0xa38 +#define mmMC_GRUB_TCB_DATA_LO 0xa39 +#define mmMC_GRUB_TCB_DATA_HI 0xa3a +#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x5e78 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x5e78 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x5eb8 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x5ef8 +#define mmMCIF_WB_BUFMGR_CUR_LINE_R 0x5e79 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x5e79 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x5eb9 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x5ef9 +#define mmMCIF_WB_BUFMGR_STATUS 0x5e7a +#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x5e7a +#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x5eba +#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x5efa +#define mmMCIF_WB_BUF_PITCH 0x5e7b +#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x5e7b +#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x5ebb +#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x5efb +#define mmMCIF_WB_BUF_1_STATUS 0x5e7c +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x5e7c +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x5ebc +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x5efc +#define mmMCIF_WB_BUF_1_STATUS2 0x5e7d +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x5e7d +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x5ebd +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x5efd +#define mmMCIF_WB_BUF_2_STATUS 0x5e7e +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x5e7e +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x5ebe +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x5efe +#define mmMCIF_WB_BUF_2_STATUS2 0x5e7f +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x5e7f +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x5ebf +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x5eff +#define mmMCIF_WB_BUF_3_STATUS 0x5e80 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x5e80 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x5ec0 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x5f00 +#define mmMCIF_WB_BUF_3_STATUS2 0x5e81 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x5e81 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x5ec1 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x5f01 +#define mmMCIF_WB_BUF_4_STATUS 0x5e82 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x5e82 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x5ec2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x5f02 +#define mmMCIF_WB_BUF_4_STATUS2 0x5e83 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x5e83 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x5ec3 +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x5f03 +#define mmMCIF_WB_ARBITRATION_CONTROL 0x5e84 +#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x5e84 +#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x5ec4 +#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x5f04 +#define mmMCIF_WB_URGENCY_WATERMARK 0x5e85 +#define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK 0x5e85 +#define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK 0x5ec5 +#define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK 0x5f05 +#define mmMCIF_WB_TEST_DEBUG_INDEX 0x5e86 +#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x5e86 +#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x5ec6 +#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x5f06 +#define mmMCIF_WB_TEST_DEBUG_DATA 0x5e87 +#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x5e87 +#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x5ec7 +#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x5f07 +#define mmMCIF_WB_BUF_1_ADDR_Y 0x5e88 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x5e88 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x5ec8 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x5f08 +#define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5ec9 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5f09 +#define mmMCIF_WB_BUF_1_ADDR_C 0x5e8a +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x5e8a +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x5eca +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x5f0a +#define mmMCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5ecb +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5f0b +#define mmMCIF_WB_BUF_2_ADDR_Y 0x5e8c +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x5e8c +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x5ecc +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x5f0c +#define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5ecd +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5f0d +#define mmMCIF_WB_BUF_2_ADDR_C 0x5e8e +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x5e8e +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x5ece +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x5f0e +#define mmMCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5ecf +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5f0f +#define mmMCIF_WB_BUF_3_ADDR_Y 0x5e90 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x5e90 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x5ed0 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x5f10 +#define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5ed1 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5f11 +#define mmMCIF_WB_BUF_3_ADDR_C 0x5e92 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x5e92 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x5ed2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x5f12 +#define mmMCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5ed3 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5f13 +#define mmMCIF_WB_BUF_4_ADDR_Y 0x5e94 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x5e94 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x5ed4 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x5f14 +#define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5ed5 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5f15 +#define mmMCIF_WB_BUF_4_ADDR_C 0x5e96 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x5e96 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x5ed6 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x5f16 +#define mmMCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5ed7 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5f17 +#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x5e98 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x5e98 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x5ed8 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x5f18 +#define mmMCIF_WB_HVVMID_CONTROL 0x5e99 +#define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL 0x5e99 +#define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL 0x5ed9 +#define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL 0x5f19 + +#endif /* GMC_8_2_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h new file mode 100644 index 000000000000..bc18e4d1f20e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h @@ -0,0 +1,1068 @@ +/* + * GMC_8_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_8_2_ENUM_H +#define GMC_8_2_ENUM_H + +typedef enum DebugBlockId { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_UVDU = 0xd, + DBG_BLOCK_ID_SQA = 0xe, + DBG_BLOCK_ID_SDMA0 = 0xf, + DBG_BLOCK_ID_SDMA1 = 0x10, + DBG_BLOCK_ID_SPIM = 0x11, + DBG_BLOCK_ID_GDS = 0x12, + DBG_BLOCK_ID_VC0 = 0x13, + DBG_BLOCK_ID_VC1 = 0x14, + DBG_BLOCK_ID_PA0 = 0x15, + DBG_BLOCK_ID_PA1 = 0x16, + DBG_BLOCK_ID_CP0 = 0x17, + DBG_BLOCK_ID_CP1 = 0x18, + DBG_BLOCK_ID_CP2 = 0x19, + DBG_BLOCK_ID_XBR = 0x1a, + DBG_BLOCK_ID_UVDM = 0x1b, + DBG_BLOCK_ID_VGT0 = 0x1c, + DBG_BLOCK_ID_VGT1 = 0x1d, + DBG_BLOCK_ID_IA = 0x1e, + DBG_BLOCK_ID_SXM0 = 0x1f, + DBG_BLOCK_ID_SXM1 = 0x20, + DBG_BLOCK_ID_SCT0 = 0x21, + DBG_BLOCK_ID_SCT1 = 0x22, + DBG_BLOCK_ID_SPM0 = 0x23, + DBG_BLOCK_ID_SPM1 = 0x24, + DBG_BLOCK_ID_UNUSED0 = 0x25, + DBG_BLOCK_ID_UNUSED1 = 0x26, + DBG_BLOCK_ID_TCAA = 0x27, + DBG_BLOCK_ID_TCAB = 0x28, + DBG_BLOCK_ID_TCCA = 0x29, + DBG_BLOCK_ID_TCCB = 0x2a, + DBG_BLOCK_ID_MCC0 = 0x2b, + DBG_BLOCK_ID_MCC1 = 0x2c, + DBG_BLOCK_ID_MCC2 = 0x2d, + DBG_BLOCK_ID_MCC3 = 0x2e, + DBG_BLOCK_ID_SXS0 = 0x2f, + DBG_BLOCK_ID_SXS1 = 0x30, + DBG_BLOCK_ID_SXS2 = 0x31, + DBG_BLOCK_ID_SXS3 = 0x32, + DBG_BLOCK_ID_SXS4 = 0x33, + DBG_BLOCK_ID_SXS5 = 0x34, + DBG_BLOCK_ID_SXS6 = 0x35, + DBG_BLOCK_ID_SXS7 = 0x36, + DBG_BLOCK_ID_SXS8 = 0x37, + DBG_BLOCK_ID_SXS9 = 0x38, + DBG_BLOCK_ID_BCI0 = 0x39, + DBG_BLOCK_ID_BCI1 = 0x3a, + DBG_BLOCK_ID_BCI2 = 0x3b, + DBG_BLOCK_ID_BCI3 = 0x3c, + DBG_BLOCK_ID_MCB = 0x3d, + DBG_BLOCK_ID_UNUSED6 = 0x3e, + DBG_BLOCK_ID_SQA00 = 0x3f, + DBG_BLOCK_ID_SQA01 = 0x40, + DBG_BLOCK_ID_SQA02 = 0x41, + DBG_BLOCK_ID_SQA10 = 0x42, + DBG_BLOCK_ID_SQA11 = 0x43, + DBG_BLOCK_ID_SQA12 = 0x44, + DBG_BLOCK_ID_UNUSED7 = 0x45, + DBG_BLOCK_ID_UNUSED8 = 0x46, + DBG_BLOCK_ID_SQB00 = 0x47, + DBG_BLOCK_ID_SQB01 = 0x48, + DBG_BLOCK_ID_SQB10 = 0x49, + DBG_BLOCK_ID_SQB11 = 0x4a, + DBG_BLOCK_ID_SQ00 = 0x4b, + DBG_BLOCK_ID_SQ01 = 0x4c, + DBG_BLOCK_ID_SQ10 = 0x4d, + DBG_BLOCK_ID_SQ11 = 0x4e, + DBG_BLOCK_ID_CB00 = 0x4f, + DBG_BLOCK_ID_CB01 = 0x50, + DBG_BLOCK_ID_CB02 = 0x51, + DBG_BLOCK_ID_CB03 = 0x52, + DBG_BLOCK_ID_CB04 = 0x53, + DBG_BLOCK_ID_UNUSED9 = 0x54, + DBG_BLOCK_ID_UNUSED10 = 0x55, + DBG_BLOCK_ID_UNUSED11 = 0x56, + DBG_BLOCK_ID_CB10 = 0x57, + DBG_BLOCK_ID_CB11 = 0x58, + DBG_BLOCK_ID_CB12 = 0x59, + DBG_BLOCK_ID_CB13 = 0x5a, + DBG_BLOCK_ID_CB14 = 0x5b, + DBG_BLOCK_ID_UNUSED12 = 0x5c, + DBG_BLOCK_ID_UNUSED13 = 0x5d, + DBG_BLOCK_ID_UNUSED14 = 0x5e, + DBG_BLOCK_ID_TCP0 = 0x5f, + DBG_BLOCK_ID_TCP1 = 0x60, + DBG_BLOCK_ID_TCP2 = 0x61, + DBG_BLOCK_ID_TCP3 = 0x62, + DBG_BLOCK_ID_TCP4 = 0x63, + DBG_BLOCK_ID_TCP5 = 0x64, + DBG_BLOCK_ID_TCP6 = 0x65, + DBG_BLOCK_ID_TCP7 = 0x66, + DBG_BLOCK_ID_TCP8 = 0x67, + DBG_BLOCK_ID_TCP9 = 0x68, + DBG_BLOCK_ID_TCP10 = 0x69, + DBG_BLOCK_ID_TCP11 = 0x6a, + DBG_BLOCK_ID_TCP12 = 0x6b, + DBG_BLOCK_ID_TCP13 = 0x6c, + DBG_BLOCK_ID_TCP14 = 0x6d, + DBG_BLOCK_ID_TCP15 = 0x6e, + DBG_BLOCK_ID_TCP16 = 0x6f, + DBG_BLOCK_ID_TCP17 = 0x70, + DBG_BLOCK_ID_TCP18 = 0x71, + DBG_BLOCK_ID_TCP19 = 0x72, + DBG_BLOCK_ID_TCP20 = 0x73, + DBG_BLOCK_ID_TCP21 = 0x74, + DBG_BLOCK_ID_TCP22 = 0x75, + DBG_BLOCK_ID_TCP23 = 0x76, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, + DBG_BLOCK_ID_DB00 = 0x7f, + DBG_BLOCK_ID_DB01 = 0x80, + DBG_BLOCK_ID_DB02 = 0x81, + DBG_BLOCK_ID_DB03 = 0x82, + DBG_BLOCK_ID_DB04 = 0x83, + DBG_BLOCK_ID_UNUSED15 = 0x84, + DBG_BLOCK_ID_UNUSED16 = 0x85, + DBG_BLOCK_ID_UNUSED17 = 0x86, + DBG_BLOCK_ID_DB10 = 0x87, + DBG_BLOCK_ID_DB11 = 0x88, + DBG_BLOCK_ID_DB12 = 0x89, + DBG_BLOCK_ID_DB13 = 0x8a, + DBG_BLOCK_ID_DB14 = 0x8b, + DBG_BLOCK_ID_UNUSED18 = 0x8c, + DBG_BLOCK_ID_UNUSED19 = 0x8d, + DBG_BLOCK_ID_UNUSED20 = 0x8e, + DBG_BLOCK_ID_TCC0 = 0x8f, + DBG_BLOCK_ID_TCC1 = 0x90, + DBG_BLOCK_ID_TCC2 = 0x91, + DBG_BLOCK_ID_TCC3 = 0x92, + DBG_BLOCK_ID_TCC4 = 0x93, + DBG_BLOCK_ID_TCC5 = 0x94, + DBG_BLOCK_ID_TCC6 = 0x95, + DBG_BLOCK_ID_TCC7 = 0x96, + DBG_BLOCK_ID_SPS00 = 0x97, + DBG_BLOCK_ID_SPS01 = 0x98, + DBG_BLOCK_ID_SPS02 = 0x99, + DBG_BLOCK_ID_SPS10 = 0x9a, + DBG_BLOCK_ID_SPS11 = 0x9b, + DBG_BLOCK_ID_SPS12 = 0x9c, + DBG_BLOCK_ID_UNUSED21 = 0x9d, + DBG_BLOCK_ID_UNUSED22 = 0x9e, + DBG_BLOCK_ID_TA00 = 0x9f, + DBG_BLOCK_ID_TA01 = 0xa0, + DBG_BLOCK_ID_TA02 = 0xa1, + DBG_BLOCK_ID_TA03 = 0xa2, + DBG_BLOCK_ID_TA04 = 0xa3, + DBG_BLOCK_ID_TA05 = 0xa4, + DBG_BLOCK_ID_TA06 = 0xa5, + DBG_BLOCK_ID_TA07 = 0xa6, + DBG_BLOCK_ID_TA08 = 0xa7, + DBG_BLOCK_ID_TA09 = 0xa8, + DBG_BLOCK_ID_TA0A = 0xa9, + DBG_BLOCK_ID_TA0B = 0xaa, + DBG_BLOCK_ID_UNUSED23 = 0xab, + DBG_BLOCK_ID_UNUSED24 = 0xac, + DBG_BLOCK_ID_UNUSED25 = 0xad, + DBG_BLOCK_ID_UNUSED26 = 0xae, + DBG_BLOCK_ID_TA10 = 0xaf, + DBG_BLOCK_ID_TA11 = 0xb0, + DBG_BLOCK_ID_TA12 = 0xb1, + DBG_BLOCK_ID_TA13 = 0xb2, + DBG_BLOCK_ID_TA14 = 0xb3, + DBG_BLOCK_ID_TA15 = 0xb4, + DBG_BLOCK_ID_TA16 = 0xb5, + DBG_BLOCK_ID_TA17 = 0xb6, + DBG_BLOCK_ID_TA18 = 0xb7, + DBG_BLOCK_ID_TA19 = 0xb8, + DBG_BLOCK_ID_TA1A = 0xb9, + DBG_BLOCK_ID_TA1B = 0xba, + DBG_BLOCK_ID_UNUSED27 = 0xbb, + DBG_BLOCK_ID_UNUSED28 = 0xbc, + DBG_BLOCK_ID_UNUSED29 = 0xbd, + DBG_BLOCK_ID_UNUSED30 = 0xbe, + DBG_BLOCK_ID_TD00 = 0xbf, + DBG_BLOCK_ID_TD01 = 0xc0, + DBG_BLOCK_ID_TD02 = 0xc1, + DBG_BLOCK_ID_TD03 = 0xc2, + DBG_BLOCK_ID_TD04 = 0xc3, + DBG_BLOCK_ID_TD05 = 0xc4, + DBG_BLOCK_ID_TD06 = 0xc5, + DBG_BLOCK_ID_TD07 = 0xc6, + DBG_BLOCK_ID_TD08 = 0xc7, + DBG_BLOCK_ID_TD09 = 0xc8, + DBG_BLOCK_ID_TD0A = 0xc9, + DBG_BLOCK_ID_TD0B = 0xca, + DBG_BLOCK_ID_UNUSED31 = 0xcb, + DBG_BLOCK_ID_UNUSED32 = 0xcc, + DBG_BLOCK_ID_UNUSED33 = 0xcd, + DBG_BLOCK_ID_UNUSED34 = 0xce, + DBG_BLOCK_ID_TD10 = 0xcf, + DBG_BLOCK_ID_TD11 = 0xd0, + DBG_BLOCK_ID_TD12 = 0xd1, + DBG_BLOCK_ID_TD13 = 0xd2, + DBG_BLOCK_ID_TD14 = 0xd3, + DBG_BLOCK_ID_TD15 = 0xd4, + DBG_BLOCK_ID_TD16 = 0xd5, + DBG_BLOCK_ID_TD17 = 0xd6, + DBG_BLOCK_ID_TD18 = 0xd7, + DBG_BLOCK_ID_TD19 = 0xd8, + DBG_BLOCK_ID_TD1A = 0xd9, + DBG_BLOCK_ID_TD1B = 0xda, + DBG_BLOCK_ID_UNUSED35 = 0xdb, + DBG_BLOCK_ID_UNUSED36 = 0xdc, + DBG_BLOCK_ID_UNUSED37 = 0xdd, + DBG_BLOCK_ID_UNUSED38 = 0xde, + DBG_BLOCK_ID_LDS00 = 0xdf, + DBG_BLOCK_ID_LDS01 = 0xe0, + DBG_BLOCK_ID_LDS02 = 0xe1, + DBG_BLOCK_ID_LDS03 = 0xe2, + DBG_BLOCK_ID_LDS04 = 0xe3, + DBG_BLOCK_ID_LDS05 = 0xe4, + DBG_BLOCK_ID_LDS06 = 0xe5, + DBG_BLOCK_ID_LDS07 = 0xe6, + DBG_BLOCK_ID_LDS08 = 0xe7, + DBG_BLOCK_ID_LDS09 = 0xe8, + DBG_BLOCK_ID_LDS0A = 0xe9, + DBG_BLOCK_ID_LDS0B = 0xea, + DBG_BLOCK_ID_UNUSED39 = 0xeb, + DBG_BLOCK_ID_UNUSED40 = 0xec, + DBG_BLOCK_ID_UNUSED41 = 0xed, + DBG_BLOCK_ID_UNUSED42 = 0xee, + DBG_BLOCK_ID_LDS10 = 0xef, + DBG_BLOCK_ID_LDS11 = 0xf0, + DBG_BLOCK_ID_LDS12 = 0xf1, + DBG_BLOCK_ID_LDS13 = 0xf2, + DBG_BLOCK_ID_LDS14 = 0xf3, + DBG_BLOCK_ID_LDS15 = 0xf4, + DBG_BLOCK_ID_LDS16 = 0xf5, + DBG_BLOCK_ID_LDS17 = 0xf6, + DBG_BLOCK_ID_LDS18 = 0xf7, + DBG_BLOCK_ID_LDS19 = 0xf8, + DBG_BLOCK_ID_LDS1A = 0xf9, + DBG_BLOCK_ID_LDS1B = 0xfa, + DBG_BLOCK_ID_UNUSED43 = 0xfb, + DBG_BLOCK_ID_UNUSED44 = 0xfc, + DBG_BLOCK_ID_UNUSED45 = 0xfd, + DBG_BLOCK_ID_UNUSED46 = 0xfe, +} DebugBlockId; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_UVD_BY2 = 0x7, + DBG_BLOCK_ID_SDMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_VC0_BY2 = 0xa, + DBG_BLOCK_ID_PA_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_PC0_BY2 = 0xe, + DBG_BLOCK_ID_BCI0_BY2 = 0xf, + DBG_BLOCK_ID_SXM0_BY2 = 0x10, + DBG_BLOCK_ID_SCT0_BY2 = 0x11, + DBG_BLOCK_ID_SPM0_BY2 = 0x12, + DBG_BLOCK_ID_BCI2_BY2 = 0x13, + DBG_BLOCK_ID_TCA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_MCD_BY2 = 0x18, + DBG_BLOCK_ID_MCD2_BY2 = 0x19, + DBG_BLOCK_ID_MCD4_BY2 = 0x1a, + DBG_BLOCK_ID_MCB_BY2 = 0x1b, + DBG_BLOCK_ID_SQA_BY2 = 0x1c, + DBG_BLOCK_ID_SQA02_BY2 = 0x1d, + DBG_BLOCK_ID_SQA11_BY2 = 0x1e, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, + DBG_BLOCK_ID_SQB_BY2 = 0x20, + DBG_BLOCK_ID_SQB10_BY2 = 0x21, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, + DBG_BLOCK_ID_CB_BY2 = 0x24, + DBG_BLOCK_ID_CB02_BY2 = 0x25, + DBG_BLOCK_ID_CB10_BY2 = 0x26, + DBG_BLOCK_ID_CB12_BY2 = 0x27, + DBG_BLOCK_ID_SXS_BY2 = 0x28, + DBG_BLOCK_ID_SXS2_BY2 = 0x29, + DBG_BLOCK_ID_SXS4_BY2 = 0x2a, + DBG_BLOCK_ID_SXS6_BY2 = 0x2b, + DBG_BLOCK_ID_DB_BY2 = 0x2c, + DBG_BLOCK_ID_DB02_BY2 = 0x2d, + DBG_BLOCK_ID_DB10_BY2 = 0x2e, + DBG_BLOCK_ID_DB12_BY2 = 0x2f, + DBG_BLOCK_ID_TCP_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_TCC_BY2 = 0x40, + DBG_BLOCK_ID_TCC2_BY2 = 0x41, + DBG_BLOCK_ID_TCC4_BY2 = 0x42, + DBG_BLOCK_ID_TCC6_BY2 = 0x43, + DBG_BLOCK_ID_SPS_BY2 = 0x44, + DBG_BLOCK_ID_SPS02_BY2 = 0x45, + DBG_BLOCK_ID_SPS11_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, + DBG_BLOCK_ID_TA_BY2 = 0x48, + DBG_BLOCK_ID_TA02_BY2 = 0x49, + DBG_BLOCK_ID_TA04_BY2 = 0x4a, + DBG_BLOCK_ID_TA06_BY2 = 0x4b, + DBG_BLOCK_ID_TA08_BY2 = 0x4c, + DBG_BLOCK_ID_TA0A_BY2 = 0x4d, + DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, + DBG_BLOCK_ID_TA10_BY2 = 0x50, + DBG_BLOCK_ID_TA12_BY2 = 0x51, + DBG_BLOCK_ID_TA14_BY2 = 0x52, + DBG_BLOCK_ID_TA16_BY2 = 0x53, + DBG_BLOCK_ID_TA18_BY2 = 0x54, + DBG_BLOCK_ID_TA1A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, + DBG_BLOCK_ID_TD_BY2 = 0x58, + DBG_BLOCK_ID_TD02_BY2 = 0x59, + DBG_BLOCK_ID_TD04_BY2 = 0x5a, + DBG_BLOCK_ID_TD06_BY2 = 0x5b, + DBG_BLOCK_ID_TD08_BY2 = 0x5c, + DBG_BLOCK_ID_TD0A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, + DBG_BLOCK_ID_TD10_BY2 = 0x60, + DBG_BLOCK_ID_TD12_BY2 = 0x61, + DBG_BLOCK_ID_TD14_BY2 = 0x62, + DBG_BLOCK_ID_TD16_BY2 = 0x63, + DBG_BLOCK_ID_TD18_BY2 = 0x64, + DBG_BLOCK_ID_TD1A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, + DBG_BLOCK_ID_LDS_BY2 = 0x68, + DBG_BLOCK_ID_LDS02_BY2 = 0x69, + DBG_BLOCK_ID_LDS04_BY2 = 0x6a, + DBG_BLOCK_ID_LDS06_BY2 = 0x6b, + DBG_BLOCK_ID_LDS08_BY2 = 0x6c, + DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, + DBG_BLOCK_ID_LDS10_BY2 = 0x70, + DBG_BLOCK_ID_LDS12_BY2 = 0x71, + DBG_BLOCK_ID_LDS14_BY2 = 0x72, + DBG_BLOCK_ID_LDS16_BY2 = 0x73, + DBG_BLOCK_ID_LDS18_BY2 = 0x74, + DBG_BLOCK_ID_LDS1A_BY2 = 0x75, + DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, + DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_SDMA0_BY4 = 0x4, + DBG_BLOCK_ID_VC0_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, + DBG_BLOCK_ID_SXM0_BY4 = 0x8, + DBG_BLOCK_ID_SPM0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC_BY4 = 0xb, + DBG_BLOCK_ID_MCD_BY4 = 0xc, + DBG_BLOCK_ID_MCD4_BY4 = 0xd, + DBG_BLOCK_ID_SQA_BY4 = 0xe, + DBG_BLOCK_ID_SQA11_BY4 = 0xf, + DBG_BLOCK_ID_SQB_BY4 = 0x10, + DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, + DBG_BLOCK_ID_CB_BY4 = 0x12, + DBG_BLOCK_ID_CB10_BY4 = 0x13, + DBG_BLOCK_ID_SXS_BY4 = 0x14, + DBG_BLOCK_ID_SXS4_BY4 = 0x15, + DBG_BLOCK_ID_DB_BY4 = 0x16, + DBG_BLOCK_ID_DB10_BY4 = 0x17, + DBG_BLOCK_ID_TCP_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_TCC_BY4 = 0x20, + DBG_BLOCK_ID_TCC4_BY4 = 0x21, + DBG_BLOCK_ID_SPS_BY4 = 0x22, + DBG_BLOCK_ID_SPS11_BY4 = 0x23, + DBG_BLOCK_ID_TA_BY4 = 0x24, + DBG_BLOCK_ID_TA04_BY4 = 0x25, + DBG_BLOCK_ID_TA08_BY4 = 0x26, + DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, + DBG_BLOCK_ID_TA10_BY4 = 0x28, + DBG_BLOCK_ID_TA14_BY4 = 0x29, + DBG_BLOCK_ID_TA18_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, + DBG_BLOCK_ID_TD_BY4 = 0x2c, + DBG_BLOCK_ID_TD04_BY4 = 0x2d, + DBG_BLOCK_ID_TD08_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, + DBG_BLOCK_ID_TD10_BY4 = 0x30, + DBG_BLOCK_ID_TD14_BY4 = 0x31, + DBG_BLOCK_ID_TD18_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, + DBG_BLOCK_ID_LDS_BY4 = 0x34, + DBG_BLOCK_ID_LDS04_BY4 = 0x35, + DBG_BLOCK_ID_LDS08_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, + DBG_BLOCK_ID_LDS10_BY4 = 0x38, + DBG_BLOCK_ID_LDS14_BY4 = 0x39, + DBG_BLOCK_ID_LDS18_BY4 = 0x3a, + DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_SDMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_SXM0_BY8 = 0x4, + DBG_BLOCK_ID_TCA_BY8 = 0x5, + DBG_BLOCK_ID_MCD_BY8 = 0x6, + DBG_BLOCK_ID_SQA_BY8 = 0x7, + DBG_BLOCK_ID_SQB_BY8 = 0x8, + DBG_BLOCK_ID_CB_BY8 = 0x9, + DBG_BLOCK_ID_SXS_BY8 = 0xa, + DBG_BLOCK_ID_DB_BY8 = 0xb, + DBG_BLOCK_ID_TCP_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_TCC_BY8 = 0x10, + DBG_BLOCK_ID_SPS_BY8 = 0x11, + DBG_BLOCK_ID_TA_BY8 = 0x12, + DBG_BLOCK_ID_TA08_BY8 = 0x13, + DBG_BLOCK_ID_TA10_BY8 = 0x14, + DBG_BLOCK_ID_TA18_BY8 = 0x15, + DBG_BLOCK_ID_TD_BY8 = 0x16, + DBG_BLOCK_ID_TD08_BY8 = 0x17, + DBG_BLOCK_ID_TD10_BY8 = 0x18, + DBG_BLOCK_ID_TD18_BY8 = 0x19, + DBG_BLOCK_ID_LDS_BY8 = 0x1a, + DBG_BLOCK_ID_LDS08_BY8 = 0x1b, + DBG_BLOCK_ID_LDS10_BY8 = 0x1c, + DBG_BLOCK_ID_LDS18_BY8 = 0x1d, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_SDMA0_BY16 = 0x1, + DBG_BLOCK_ID_SXM_BY16 = 0x2, + DBG_BLOCK_ID_MCD_BY16 = 0x3, + DBG_BLOCK_ID_SQB_BY16 = 0x4, + DBG_BLOCK_ID_SXS_BY16 = 0x5, + DBG_BLOCK_ID_TCP_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_TCC_BY16 = 0x8, + DBG_BLOCK_ID_TA_BY16 = 0x9, + DBG_BLOCK_ID_TA10_BY16 = 0xa, + DBG_BLOCK_ID_TD_BY16 = 0xb, + DBG_BLOCK_ID_TD10_BY16 = 0xc, + DBG_BLOCK_ID_LDS_BY16 = 0xd, + DBG_BLOCK_ID_LDS10_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* GMC_8_2_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h new file mode 100644 index 000000000000..c5dd8ecdd3e1 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h @@ -0,0 +1,7850 @@ +/* + * GMC_8_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GMC_8_2_SH_MASK_H +#define GMC_8_2_SH_MASK_H + +#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 +#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 +#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 +#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 +#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 +#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 +#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 +#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 +#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 +#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 +#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20 +#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5 +#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40 +#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6 +#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80 +#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7 +#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700 +#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8 +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000 +#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f +#define MC_ARB_ATOMIC__TC_GRP_MASK 0x7 +#define MC_ARB_ATOMIC__TC_GRP__SHIFT 0x0 +#define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8 +#define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT 0x3 +#define MC_ARB_ATOMIC__SDMA_GRP_MASK 0x70 +#define MC_ARB_ATOMIC__SDMA_GRP__SHIFT 0x4 +#define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK 0x80 +#define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT 0x7 +#define MC_ARB_ATOMIC__OUTSTANDING_MASK 0xff00 +#define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8 +#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP_MASK 0xff0000 +#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80 +#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000 +#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000 +#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13 +#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000 +#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16 +#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000 +#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000 +#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19 +#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff +#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9 +#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400 +#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa +#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800 +#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000 +#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd +#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK 0x4000 +#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe +#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK 0x8000 +#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT 0xf +#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK 0xff0000 +#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10 +#define MC_ARB_FED_CNTL__MODE_MASK 0x3 +#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0 +#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc +#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2 +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10 +#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4 +#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20 +#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5 +#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40 +#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6 +#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80 +#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7 +#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1 +#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0 +#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2 +#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1 +#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4 +#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2 +#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8 +#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3 +#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10 +#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4 +#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20 +#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5 +#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40 +#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6 +#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80 +#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9 +#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400 +#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa +#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800 +#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000 +#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000 +#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd +#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000 +#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe +#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000 +#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11 +#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000 +#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15 +#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000 +#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19 +#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000 +#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000 +#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000 +#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d +#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf +#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0 +#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10 +#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4 +#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20 +#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5 +#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40 +#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6 +#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80 +#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7 +#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100 +#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8 +#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200 +#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9 +#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400 +#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa +#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800 +#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb +#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000 +#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc +#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000 +#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3 +#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0 +#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4 +#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2 +#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18 +#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3 +#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20 +#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5 +#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff +#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0 +#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00 +#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8 +#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000 +#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10 +#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000 +#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18 +#define MC_ARB_PERF_CID__CH0_MASK 0xff +#define MC_ARB_PERF_CID__CH0__SHIFT 0x0 +#define MC_ARB_PERF_CID__CH1_MASK 0xff00 +#define MC_ARB_PERF_CID__CH1__SHIFT 0x8 +#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000 +#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10 +#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000 +#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11 +#define MC_ARB_SNOOP__TC_GRP_RD_MASK 0x7 +#define MC_ARB_SNOOP__TC_GRP_RD__SHIFT 0x0 +#define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK 0x8 +#define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT 0x3 +#define MC_ARB_SNOOP__TC_GRP_WR_MASK 0x70 +#define MC_ARB_SNOOP__TC_GRP_WR__SHIFT 0x4 +#define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK 0x80 +#define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT 0x7 +#define MC_ARB_SNOOP__SDMA_GRP_RD_MASK 0x700 +#define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT 0x8 +#define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK 0x800 +#define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT 0xb +#define MC_ARB_SNOOP__SDMA_GRP_WR_MASK 0x7000 +#define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT 0xc +#define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK 0x8000 +#define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT 0xf +#define MC_ARB_SNOOP__OUTSTANDING_RD_MASK 0xff0000 +#define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT 0x10 +#define MC_ARB_SNOOP__OUTSTANDING_WR_MASK 0xff000000 +#define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT 0x18 +#define MC_ARB_GRUB__GRUB_WATERMARK_MASK 0xff +#define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT 0x0 +#define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK 0xff00 +#define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT 0x8 +#define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK 0xff0000 +#define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT 0x10 +#define MC_ARB_GRUB__REG_WR_EN_MASK 0x3000000 +#define MC_ARB_GRUB__REG_WR_EN__SHIFT 0x18 +#define MC_ARB_GRUB__REG_RD_SEL_MASK 0x4000000 +#define MC_ARB_GRUB__REG_RD_SEL__SHIFT 0x1a +#define MC_ARB_GECC2__ENABLE_MASK 0x1 +#define MC_ARB_GECC2__ENABLE__SHIFT 0x0 +#define MC_ARB_GECC2__ECC_MODE_MASK 0x6 +#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1 +#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18 +#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3 +#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60 +#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5 +#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780 +#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7 +#define MC_ARB_GECC2__READ_ERR_MASK 0x3800 +#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb +#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000 +#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe +#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000 +#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf +#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000 +#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15 +#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000 +#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff +#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000 +#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18 +#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf +#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0 +#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0 +#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4 +#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00 +#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8 +#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000 +#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc +#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000 +#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10 +#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000 +#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14 +#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000 +#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18 +#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000 +#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c +#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf +#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0 +#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0 +#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4 +#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00 +#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8 +#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000 +#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc +#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1 +#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0 +#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2 +#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1 +#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4 +#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2 +#define MC_ARB_MISC3__UVD_URG_MODE_MASK 0x8 +#define MC_ARB_MISC3__UVD_URG_MODE__SHIFT 0x3 +#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK 0x10 +#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT 0x4 +#define MC_ARB_MISC3__TBD_FIELD_MASK 0xffffffe0 +#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x5 +#define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK 0xff +#define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT 0x0 +#define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK 0xff00 +#define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT 0x8 +#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK 0xff0000 +#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT 0x10 +#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK 0xff000000 +#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT 0x18 +#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff +#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0 +#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1 +#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0 +#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2 +#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1 +#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc +#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2 +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10 +#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4 +#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20 +#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5 +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40 +#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6 +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80 +#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7 +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100 +#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400 +#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800 +#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000 +#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000 +#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17 +#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000 +#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18 +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000 +#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5 +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0 +#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6 +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000 +#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000 +#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000 +#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f +#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000 +#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc +#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000 +#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0 +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc +#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000 +#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000 +#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19 +#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1 +#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0 +#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e +#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1 +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80 +#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7 +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000 +#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400 +#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa +#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800 +#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb +#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000 +#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc +#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000 +#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd +#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000 +#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe +#define MC_ARB_MISC2__GECC_MASK 0x40000 +#define MC_ARB_MISC2__GECC__SHIFT 0x12 +#define MC_ARB_MISC2__GECC_RST_MASK 0x80000 +#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13 +#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000 +#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14 +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000 +#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15 +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000 +#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19 +#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000 +#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c +#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000 +#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000 +#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000 +#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f +#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1 +#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0 +#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2 +#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1 +#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4 +#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2 +#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8 +#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3 +#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800 +#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb +#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000 +#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13 +#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000 +#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14 +#define MC_ARB_MISC__CALI_RATES_MASK 0x600000 +#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15 +#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000 +#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17 +#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000 +#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18 +#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000 +#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19 +#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000 +#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a +#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000 +#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e +#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000 +#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f +#define MC_ARB_BANKMAP__BANK0_MASK 0xf +#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0 +#define MC_ARB_BANKMAP__BANK1_MASK 0xf0 +#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4 +#define MC_ARB_BANKMAP__BANK2_MASK 0xf00 +#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8 +#define MC_ARB_BANKMAP__BANK3_MASK 0xf000 +#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc +#define MC_ARB_BANKMAP__RANK_MASK 0xf0000 +#define MC_ARB_BANKMAP__RANK__SHIFT 0x10 +#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3 +#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0 +#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4 +#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2 +#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38 +#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3 +#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0 +#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6 +#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100 +#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8 +#define MC_ARB_RAMCFG__RSV_1_MASK 0x200 +#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9 +#define MC_ARB_RAMCFG__RSV_2_MASK 0x400 +#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa +#define MC_ARB_RAMCFG__RSV_3_MASK 0x800 +#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb +#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000 +#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc +#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000 +#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd +#define MC_ARB_POP__ENABLE_ARB_MASK 0x1 +#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0 +#define MC_ARB_POP__SPEC_OPEN_MASK 0x2 +#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1 +#define MC_ARB_POP__POP_DEPTH_MASK 0x3c +#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2 +#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0 +#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6 +#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000 +#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc +#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000 +#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf +#define MC_ARB_POP__QUICK_STOP_MASK 0x20000 +#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11 +#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000 +#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12 +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000 +#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13 +#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff +#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0 +#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00 +#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8 +#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000 +#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10 +#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000 +#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11 +#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff +#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0 +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100 +#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8 +#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200 +#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9 +#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00 +#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa +#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000 +#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10 +#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000 +#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18 +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf +#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0 +#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0 +#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4 +#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000 +#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc +#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff +#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00 +#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000 +#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18 +#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff +#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00 +#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000 +#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18 +#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3 +#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0 +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4 +#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400 +#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa +#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800 +#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb +#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000 +#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc +#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000 +#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd +#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3 +#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0 +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4 +#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400 +#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa +#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800 +#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb +#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000 +#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc +#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000 +#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd +#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3 +#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0 +#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc +#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2 +#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30 +#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4 +#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0 +#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6 +#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300 +#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8 +#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00 +#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa +#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000 +#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc +#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000 +#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000 +#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10 +#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3 +#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0 +#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc +#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2 +#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30 +#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4 +#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0 +#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6 +#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300 +#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8 +#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00 +#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa +#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000 +#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc +#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000 +#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000 +#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10 +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1 +#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0 +#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6 +#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1 +#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8 +#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3 +#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10 +#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4 +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1 +#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0 +#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6 +#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1 +#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8 +#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3 +#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10 +#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4 +#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff +#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff +#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff +#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff +#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3 +#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc +#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2 +#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30 +#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4 +#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0 +#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6 +#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300 +#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8 +#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00 +#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa +#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000 +#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc +#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000 +#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe +#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000 +#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10 +#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000 +#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11 +#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000 +#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12 +#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000 +#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13 +#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000 +#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14 +#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000 +#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15 +#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000 +#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16 +#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000 +#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17 +#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18 +#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19 +#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a +#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b +#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c +#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d +#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e +#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000 +#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f +#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3 +#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0 +#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc +#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2 +#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30 +#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4 +#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0 +#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6 +#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300 +#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8 +#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00 +#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa +#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000 +#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc +#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000 +#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe +#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000 +#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10 +#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000 +#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11 +#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000 +#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12 +#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000 +#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13 +#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000 +#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14 +#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000 +#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15 +#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000 +#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16 +#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000 +#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17 +#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18 +#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19 +#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a +#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b +#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c +#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d +#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e +#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000 +#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f +#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1 +#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0 +#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e +#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1 +#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0 +#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6 +#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800 +#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb +#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000 +#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc +#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000 +#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd +#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000 +#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe +#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff +#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0 +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3 +#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0 +#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4 +#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2 +#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8 +#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3 +#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10 +#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4 +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20 +#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5 +#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40 +#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6 +#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80 +#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7 +#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300 +#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8 +#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400 +#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa +#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800 +#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb +#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000 +#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc +#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000 +#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd +#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000 +#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000 +#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf +#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK 0x10000 +#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT 0x10 +#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK 0x20000 +#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT 0x11 +#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000 +#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12 +#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000 +#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13 +#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000 +#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14 +#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK 0x1000000 +#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT 0x18 +#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK 0x2000000 +#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT 0x19 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0 +#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4 +#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100 +#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8 +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200 +#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9 +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 +#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0 +#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4 +#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100 +#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8 +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200 +#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9 +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 +#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa +#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff +#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0 +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00 +#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8 +#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000 +#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10 +#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000 +#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11 +#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000 +#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12 +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000 +#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13 +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000 +#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14 +#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000 +#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15 +#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff +#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0 +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00 +#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8 +#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000 +#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10 +#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000 +#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11 +#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000 +#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12 +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000 +#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13 +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000 +#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14 +#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000 +#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15 +#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000 +#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18 +#define MC_ARB_LM_WR__ATOMIC_LM_EOB_MASK 0x2000000 +#define MC_ARB_LM_WR__ATOMIC_LM_EOB__SHIFT 0x19 +#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB_MASK 0x4000000 +#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB__SHIFT 0x1a +#define MC_ARB_REMREQ__RD_WATER_MASK 0xff +#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0 +#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00 +#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8 +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000 +#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10 +#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000 +#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14 +#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000 +#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18 +#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1 +#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0 +#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2 +#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1 +#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4 +#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2 +#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8 +#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3 +#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10 +#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4 +#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20 +#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5 +#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40 +#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6 +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80 +#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7 +#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00 +#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8 +#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000 +#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf +#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff +#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0 +#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00 +#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8 +#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000 +#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10 +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000 +#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18 +#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff +#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0 +#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00 +#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8 +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000 +#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10 +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000 +#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18 +#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000 +#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c +#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff +#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0 +#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00 +#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8 +#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000 +#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10 +#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000 +#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000 +#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13 +#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff +#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0 +#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff +#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0 +#define MC_ARB_GRUB_REALTIME_RD__CB0_MASK 0x1 +#define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT 0x0 +#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK 0x2 +#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT 0x1 +#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK 0x4 +#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT 0x2 +#define MC_ARB_GRUB_REALTIME_RD__DB0_MASK 0x8 +#define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT 0x3 +#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK 0x10 +#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT 0x4 +#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK 0x20 +#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT 0x5 +#define MC_ARB_GRUB_REALTIME_RD__TC0_MASK 0x40 +#define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT 0x6 +#define MC_ARB_GRUB_REALTIME_RD__IA_MASK 0x80 +#define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT 0x7 +#define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK 0x100 +#define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT 0x8 +#define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK 0x200 +#define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT 0x9 +#define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK 0x400 +#define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT 0xa +#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK 0x800 +#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT 0xb +#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK 0x1000 +#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT 0xc +#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK 0x2000 +#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT 0xd +#define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK 0x4000 +#define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT 0xe +#define MC_ARB_GRUB_REALTIME_RD__RLC_MASK 0x8000 +#define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT 0xf +#define MC_ARB_GRUB_REALTIME_RD__VMC_MASK 0x10000 +#define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT 0x10 +#define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK 0x20000 +#define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT 0x11 +#define MC_ARB_GRUB_REALTIME_RD__SMU_MASK 0x40000 +#define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT 0x12 +#define MC_ARB_GRUB_REALTIME_RD__VCE0_MASK 0x80000 +#define MC_ARB_GRUB_REALTIME_RD__VCE0__SHIFT 0x13 +#define MC_ARB_GRUB_REALTIME_RD__VCE1_MASK 0x100000 +#define MC_ARB_GRUB_REALTIME_RD__VCE1__SHIFT 0x14 +#define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK 0x200000 +#define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT 0x15 +#define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK 0x400000 +#define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT 0x16 +#define MC_ARB_GRUB_REALTIME_RD__HDP_MASK 0x800000 +#define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT 0x17 +#define MC_ARB_GRUB_REALTIME_RD__UMC_MASK 0x1000000 +#define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT 0x18 +#define MC_ARB_GRUB_REALTIME_RD__UVD_MASK 0x2000000 +#define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT 0x19 +#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK 0x4000000 +#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT 0x1a +#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK 0x8000000 +#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT 0x1b +#define MC_ARB_GRUB_REALTIME_RD__SEM_MASK 0x10000000 +#define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT 0x1c +#define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK 0x20000000 +#define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d +#define MC_ARB_GRUB_REALTIME_RD__VP8_MASK 0x40000000 +#define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT 0x1e +#define MC_ARB_GRUB_REALTIME_RD__ISP_MASK 0x80000000 +#define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT 0x1f +#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff +#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0 +#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00 +#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8 +#define MC_ARB_CG__RSV_0_MASK 0xff0000 +#define MC_ARB_CG__RSV_0__SHIFT 0x10 +#define MC_ARB_CG__RSV_1_MASK 0xff000000 +#define MC_ARB_CG__RSV_1__SHIFT 0x18 +#define MC_ARB_GRUB_REALTIME_WR__CB0_MASK 0x1 +#define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT 0x0 +#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK 0x2 +#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT 0x1 +#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK 0x4 +#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT 0x2 +#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK 0x8 +#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT 0x3 +#define MC_ARB_GRUB_REALTIME_WR__DB0_MASK 0x10 +#define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT 0x4 +#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK 0x20 +#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT 0x5 +#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK 0x40 +#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT 0x6 +#define MC_ARB_GRUB_REALTIME_WR__TC0_MASK 0x80 +#define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT 0x7 +#define MC_ARB_GRUB_REALTIME_WR__SH_MASK 0x100 +#define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT 0x8 +#define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK 0x200 +#define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT 0x9 +#define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK 0x400 +#define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT 0xa +#define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK 0x800 +#define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT 0xb +#define MC_ARB_GRUB_REALTIME_WR__RLC_MASK 0x1000 +#define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT 0xc +#define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK 0x2000 +#define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT 0xd +#define MC_ARB_GRUB_REALTIME_WR__SMU_MASK 0x4000 +#define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT 0xe +#define MC_ARB_GRUB_REALTIME_WR__VCE0_MASK 0x8000 +#define MC_ARB_GRUB_REALTIME_WR__VCE0__SHIFT 0xf +#define MC_ARB_GRUB_REALTIME_WR__VCE1_MASK 0x10000 +#define MC_ARB_GRUB_REALTIME_WR__VCE1__SHIFT 0x10 +#define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK 0x20000 +#define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT 0x11 +#define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK 0x40000 +#define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT 0x12 +#define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK 0x80000 +#define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT 0x13 +#define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK 0x100000 +#define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT 0x14 +#define MC_ARB_GRUB_REALTIME_WR__HDP_MASK 0x200000 +#define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT 0x15 +#define MC_ARB_GRUB_REALTIME_WR__UMC_MASK 0x400000 +#define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT 0x16 +#define MC_ARB_GRUB_REALTIME_WR__UVD_MASK 0x800000 +#define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT 0x17 +#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK 0x1000000 +#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT 0x18 +#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK 0x2000000 +#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT 0x19 +#define MC_ARB_GRUB_REALTIME_WR__XDP_MASK 0x4000000 +#define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT 0x1a +#define MC_ARB_GRUB_REALTIME_WR__SEM_MASK 0x8000000 +#define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT 0x1b +#define MC_ARB_GRUB_REALTIME_WR__IH_MASK 0x10000000 +#define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT 0x1c +#define MC_ARB_GRUB_REALTIME_WR__VP8_MASK 0x20000000 +#define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d +#define MC_ARB_GRUB_REALTIME_WR__ISP_MASK 0x40000000 +#define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT 0x1e +#define MC_ARB_GRUB_REALTIME_WR__VIN0_MASK 0x80000000 +#define MC_ARB_GRUB_REALTIME_WR__VIN0__SHIFT 0x1f +#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff +#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00 +#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000 +#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18 +#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1 +#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0 +#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2 +#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1 +#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4 +#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2 +#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8 +#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3 +#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10 +#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4 +#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20 +#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5 +#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40 +#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6 +#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80 +#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7 +#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100 +#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8 +#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200 +#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9 +#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400 +#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa +#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800 +#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb +#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000 +#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc +#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000 +#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd +#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000 +#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe +#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000 +#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf +#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000 +#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10 +#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000 +#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11 +#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000 +#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12 +#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000 +#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13 +#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000 +#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14 +#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000 +#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15 +#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000 +#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16 +#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000 +#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17 +#define MC_ARB_BUSY_STATUS__WRRET0_MASK 0x1000000 +#define MC_ARB_BUSY_STATUS__WRRET0__SHIFT 0x18 +#define MC_ARB_BUSY_STATUS__WRRET1_MASK 0x2000000 +#define MC_ARB_BUSY_STATUS__WRRET1__SHIFT 0x19 +#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000 +#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a +#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000 +#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b +#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000 +#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c +#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000 +#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d +#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000 +#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e +#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000 +#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff +#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0 +#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00 +#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8 +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000 +#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10 +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000 +#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18 +#define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK 0xff +#define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT 0x0 +#define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK 0xff00 +#define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT 0x8 +#define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK 0x10000 +#define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT 0x10 +#define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK 0x20000 +#define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT 0x11 +#define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK 0x40000 +#define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT 0x12 +#define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK 0x80000 +#define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT 0x13 +#define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK 0x100000 +#define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT 0x14 +#define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK 0x200000 +#define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT 0x15 +#define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK 0x400000 +#define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT 0x16 +#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK 0x800000 +#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT 0x17 +#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK 0x1000000 +#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT 0x18 +#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD_MASK 0x2000000 +#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD__SHIFT 0x19 +#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD_MASK 0x4000000 +#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD__SHIFT 0x1a +#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR_MASK 0x8000000 +#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR__SHIFT 0x1b +#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR_MASK 0x10000000 +#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR__SHIFT 0x1c +#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f +#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0 +#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0 +#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5 +#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00 +#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa +#define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000 +#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf +#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1 +#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0 +#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2 +#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1 +#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4 +#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2 +#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8 +#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3 +#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10 +#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4 +#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00 +#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8 +#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000 +#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc +#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000 +#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd +#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000 +#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf +#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000 +#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11 +#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000 +#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13 +#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000 +#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15 +#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000 +#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17 +#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000 +#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19 +#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000 +#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a +#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000 +#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b +#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000 +#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c +#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000 +#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d +#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e +#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1 +#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1 +#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 +#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2 +#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 +#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4 +#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 +#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 +#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 +#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30 +#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4 +#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0 +#define MC_CG_CONFIG__INDEX__SHIFT 0x6 +#define MC_CITF_CNTL__IGNOREPM_MASK 0x4 +#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2 +#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8 +#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3 +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30 +#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4 +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40 +#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6 +#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180 +#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7 +#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200 +#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9 +#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f +#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0 +#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0 +#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6 +#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff +#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00 +#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8 +#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000 +#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10 +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000 +#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18 +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000 +#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19 +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff +#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00 +#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8 +#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000 +#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10 +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000 +#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18 +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000 +#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19 +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1 +#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0 +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e +#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1 +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20 +#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5 +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0 +#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6 +#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f +#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000 +#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12 +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000 +#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18 +#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1 +#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0 +#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2 +#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1 +#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4 +#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2 +#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8 +#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3 +#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10 +#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4 +#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20 +#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5 +#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40 +#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6 +#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80 +#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7 +#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f +#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0 +#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000 +#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10 +#define MC_CITF_DAGB_DLY__POS_MASK 0x3f000000 +#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18 +#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf +#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0 +#define MC_RD_GRP_EXT__TC0_MASK 0xf0 +#define MC_RD_GRP_EXT__TC0__SHIFT 0x4 +#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf +#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0 +#define MC_WR_GRP_EXT__TC0_MASK 0xf0 +#define MC_WR_GRP_EXT__TC0__SHIFT 0x4 +#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f +#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0 +#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80 +#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7 +#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000 +#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe +#define MC_WR_TC0__ENABLE_MASK 0x1 +#define MC_WR_TC0__ENABLE__SHIFT 0x0 +#define MC_WR_TC0__PRESCALE_MASK 0x6 +#define MC_WR_TC0__PRESCALE__SHIFT 0x1 +#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_TC0__STALL_MODE_MASK 0x30 +#define MC_WR_TC0__STALL_MODE__SHIFT 0x4 +#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_TC0__MAX_BURST_MASK 0x780 +#define MC_WR_TC0__MAX_BURST__SHIFT 0x7 +#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800 +#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb +#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_TC1__ENABLE_MASK 0x1 +#define MC_WR_TC1__ENABLE__SHIFT 0x0 +#define MC_WR_TC1__PRESCALE_MASK 0x6 +#define MC_WR_TC1__PRESCALE__SHIFT 0x1 +#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_TC1__STALL_MODE_MASK 0x30 +#define MC_WR_TC1__STALL_MODE__SHIFT 0x4 +#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_TC1__MAX_BURST_MASK 0x780 +#define MC_WR_TC1__MAX_BURST__SHIFT 0x7 +#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800 +#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb +#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0 +#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6 +#define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK 0xff +#define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT 0x0 +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000 +#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18 +#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000 +#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19 +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000 +#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18 +#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000 +#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19 +#define MC_RD_CB__ENABLE_MASK 0x1 +#define MC_RD_CB__ENABLE__SHIFT 0x0 +#define MC_RD_CB__PRESCALE_MASK 0x6 +#define MC_RD_CB__PRESCALE__SHIFT 0x1 +#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_CB__STALL_MODE_MASK 0x30 +#define MC_RD_CB__STALL_MODE__SHIFT 0x4 +#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_CB__MAX_BURST_MASK 0x780 +#define MC_RD_CB__MAX_BURST__SHIFT 0x7 +#define MC_RD_CB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_DB__ENABLE_MASK 0x1 +#define MC_RD_DB__ENABLE__SHIFT 0x0 +#define MC_RD_DB__PRESCALE_MASK 0x6 +#define MC_RD_DB__PRESCALE__SHIFT 0x1 +#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_DB__STALL_MODE_MASK 0x30 +#define MC_RD_DB__STALL_MODE__SHIFT 0x4 +#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_DB__MAX_BURST_MASK 0x780 +#define MC_RD_DB__MAX_BURST__SHIFT 0x7 +#define MC_RD_DB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_TC0__ENABLE_MASK 0x1 +#define MC_RD_TC0__ENABLE__SHIFT 0x0 +#define MC_RD_TC0__PRESCALE_MASK 0x6 +#define MC_RD_TC0__PRESCALE__SHIFT 0x1 +#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_TC0__STALL_MODE_MASK 0x30 +#define MC_RD_TC0__STALL_MODE__SHIFT 0x4 +#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_TC0__MAX_BURST_MASK 0x780 +#define MC_RD_TC0__MAX_BURST__SHIFT 0x7 +#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800 +#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb +#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_TC1__ENABLE_MASK 0x1 +#define MC_RD_TC1__ENABLE__SHIFT 0x0 +#define MC_RD_TC1__PRESCALE_MASK 0x6 +#define MC_RD_TC1__PRESCALE__SHIFT 0x1 +#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_TC1__STALL_MODE_MASK 0x30 +#define MC_RD_TC1__STALL_MODE__SHIFT 0x4 +#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_TC1__MAX_BURST_MASK 0x780 +#define MC_RD_TC1__MAX_BURST__SHIFT 0x7 +#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800 +#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb +#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_RD_HUB__ENABLE_MASK 0x1 +#define MC_RD_HUB__ENABLE__SHIFT 0x0 +#define MC_RD_HUB__PRESCALE_MASK 0x6 +#define MC_RD_HUB__PRESCALE__SHIFT 0x1 +#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_RD_HUB__STALL_MODE_MASK 0x30 +#define MC_RD_HUB__STALL_MODE__SHIFT 0x4 +#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40 +#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_RD_HUB__MAX_BURST_MASK 0x780 +#define MC_RD_HUB__MAX_BURST__SHIFT 0x7 +#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800 +#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb +#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_CB__ENABLE_MASK 0x1 +#define MC_WR_CB__ENABLE__SHIFT 0x0 +#define MC_WR_CB__PRESCALE_MASK 0x6 +#define MC_WR_CB__PRESCALE__SHIFT 0x1 +#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_CB__STALL_MODE_MASK 0x30 +#define MC_WR_CB__STALL_MODE__SHIFT 0x4 +#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_CB__MAX_BURST_MASK 0x780 +#define MC_WR_CB__MAX_BURST__SHIFT 0x7 +#define MC_WR_CB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_DB__ENABLE_MASK 0x1 +#define MC_WR_DB__ENABLE__SHIFT 0x0 +#define MC_WR_DB__PRESCALE_MASK 0x6 +#define MC_WR_DB__PRESCALE__SHIFT 0x1 +#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_DB__STALL_MODE_MASK 0x30 +#define MC_WR_DB__STALL_MODE__SHIFT 0x4 +#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_DB__MAX_BURST_MASK 0x780 +#define MC_WR_DB__MAX_BURST__SHIFT 0x7 +#define MC_WR_DB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_WR_HUB__ENABLE_MASK 0x1 +#define MC_WR_HUB__ENABLE__SHIFT 0x0 +#define MC_WR_HUB__PRESCALE_MASK 0x6 +#define MC_WR_HUB__PRESCALE__SHIFT 0x1 +#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_WR_HUB__STALL_MODE_MASK 0x30 +#define MC_WR_HUB__STALL_MODE__SHIFT 0x4 +#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40 +#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6 +#define MC_WR_HUB__MAX_BURST_MASK 0x780 +#define MC_WR_HUB__MAX_BURST__SHIFT 0x7 +#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800 +#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb +#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff +#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0 +#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00 +#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8 +#define MC_RD_GRP_LCL__CB0_MASK 0xf000 +#define MC_RD_GRP_LCL__CB0__SHIFT 0xc +#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000 +#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10 +#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000 +#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14 +#define MC_RD_GRP_LCL__DB0_MASK 0xf000000 +#define MC_RD_GRP_LCL__DB0__SHIFT 0x18 +#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000 +#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c +#define MC_WR_GRP_LCL__CB0_MASK 0xf +#define MC_WR_GRP_LCL__CB0__SHIFT 0x0 +#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0 +#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4 +#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00 +#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8 +#define MC_WR_GRP_LCL__DB0_MASK 0xf000 +#define MC_WR_GRP_LCL__DB0__SHIFT 0xc +#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000 +#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10 +#define MC_WR_GRP_LCL__SX0_MASK 0xf00000 +#define MC_WR_GRP_LCL__SX0__SHIFT 0x14 +#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000 +#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c +#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff +#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0 +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x2 +#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x1 +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x4 +#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x2 +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x8 +#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x3 +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x10 +#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x4 +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x20 +#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x5 +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x40 +#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x6 +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x80 +#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x7 +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x100 +#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x8 +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x200 +#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x9 +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x400 +#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xa +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x800 +#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0xb +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x1000 +#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0xc +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x2000 +#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0xd +#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK 0x4000 +#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT 0xe +#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK 0x8000 +#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT 0xf +#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK 0x10000 +#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT 0x10 +#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK 0x20000 +#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT 0x11 +#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK 0x40000 +#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT 0x12 +#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f +#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0 +#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0 +#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6 +#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000 +#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc +#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000 +#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12 +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4 +#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2 +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18 +#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3 +#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f +#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0 +#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0 +#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6 +#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000 +#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc +#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000 +#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12 +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000 +#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1 +#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0 +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2 +#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1 +#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK 0x4 +#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT 0x2 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x8 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x3 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x10 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x4 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x20 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x5 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x40 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x6 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK 0x80 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT 0x7 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK 0x100 +#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT 0x8 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x200 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x9 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x400 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0xa +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK 0x800 +#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT 0xb +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1000 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0xc +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2000 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0xd +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK 0x4000 +#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT 0xe +#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x8000 +#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xf +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x10000 +#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x10 +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x20000 +#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x11 +#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK 0x40000 +#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT 0x12 +#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x80000 +#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x13 +#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3 +#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0 +#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff +#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8 +#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3 +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 +#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 +#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0 +#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000 +#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf +#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000 +#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10 +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000 +#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11 +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000 +#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12 +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000 +#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13 +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000 +#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14 +#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000 +#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15 +#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000 +#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16 +#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK 0x800000 +#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT 0x17 +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1 +#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0 +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2 +#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1 +#define MC_HUB_WDP_BP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe +#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1 +#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000 +#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12 +#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1 +#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0 +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2 +#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4 +#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8 +#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10 +#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 +#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20 +#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 +#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40 +#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 +#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80 +#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 +#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100 +#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 +#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200 +#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9 +#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400 +#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa +#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800 +#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb +#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000 +#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc +#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000 +#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd +#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000 +#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe +#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000 +#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf +#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000 +#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10 +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000 +#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11 +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000 +#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12 +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000 +#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13 +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000 +#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14 +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000 +#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15 +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000 +#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16 +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1 +#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0 +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2 +#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4 +#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8 +#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10 +#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 +#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20 +#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 +#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40 +#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 +#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80 +#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 +#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100 +#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200 +#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9 +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400 +#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800 +#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000 +#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000 +#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000 +#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000 +#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1 +#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0 +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2 +#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1 +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4 +#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2 +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8 +#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3 +#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10 +#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4 +#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20 +#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5 +#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40 +#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6 +#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80 +#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7 +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1 +#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8 +#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3 +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 +#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20 +#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5 +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40 +#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6 +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80 +#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7 +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100 +#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8 +#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200 +#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9 +#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400 +#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa +#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800 +#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb +#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000 +#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000 +#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd +#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000 +#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000 +#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16 +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000 +#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17 +#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000 +#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18 +#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000 +#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19 +#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK 0x4000000 +#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT 0x1a +#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK 0x78000000 +#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT 0x1b +#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1 +#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0 +#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe +#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1 +#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000 +#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15 +#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000 +#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16 +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000 +#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000 +#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 +#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 +#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 +#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 +#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 +#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 +#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 +#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 +#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 +#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff +#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00 +#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8 +#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000 +#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10 +#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000 +#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18 +#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff +#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00 +#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8 +#define MC_HUB_WDP_CREDITS2__VM2_MASK 0xff0000 +#define MC_HUB_WDP_CREDITS2__VM2__SHIFT 0x10 +#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf +#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0 +#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0 +#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8 +#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000 +#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000 +#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11 +#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf +#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0 +#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0 +#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8 +#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000 +#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000 +#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11 +#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff +#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0 +#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00 +#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8 +#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000 +#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10 +#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000 +#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18 +#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff +#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0 +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00 +#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8 +#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f +#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0 +#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000 +#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10 +#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000 +#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x100000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x14 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x200000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x15 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x400000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x16 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x800000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x17 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK 0x1000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT 0x18 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK 0x2000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT 0x19 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x4000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1a +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x8000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1b +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x10000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1c +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x20000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK 0x40000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT 0x1e +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK 0x80000000 +#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT 0x1f +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3 +#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c +#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2 +#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3 +#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c +#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2 +#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe +#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1 +#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00 +#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9 +#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000 +#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11 +#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000 +#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18 +#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe +#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1 +#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00 +#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9 +#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000 +#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11 +#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000 +#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18 +#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe +#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1 +#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00 +#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9 +#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK 0x1 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT 0x0 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK 0x2 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT 0x1 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK 0x4 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT 0x2 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK 0x8 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT 0x3 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK 0x10 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT 0x4 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK 0x20 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT 0x5 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK 0x40 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT 0x6 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK 0x80 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT 0x7 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK 0x100 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT 0x8 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK 0x200 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT 0x9 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK 0x400 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT 0xa +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK 0x800 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT 0xb +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK 0x1000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT 0xc +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK 0x2000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT 0xd +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK 0x4000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT 0xe +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK 0x8000 +#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT 0xf +#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT 0x19 +#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f +#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0 +#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK 0x80 +#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT 0x7 +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00 +#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8 +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0 +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00 +#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00 +#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8 +#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VCE0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCE0__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCE0__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VCEU0__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3 +#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc +#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2 +#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_VCE0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCE0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCE0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCE0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCE0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCE0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCE0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VCE0__VM_BYPASS_MASK 0x10000 +#define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_IH__ENABLE_MASK 0x1 +#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1 +#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1 +#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1 +#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000 +#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WDP_VCEU0__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCEU0__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCEU0__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCEU0__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCEU0__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1 +#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VP8__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VP8__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VP8__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VP8__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VP8__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_VP8U__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VP8U__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VP8U__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VP8U__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VP8U__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VP8U__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VP8U__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VP8U__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VP8U__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VP8U__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_SAMMSP__ENABLE_MASK 0x1 +#define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_SAMMSP__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_SAMMSP__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_VP8__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VP8__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VP8__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VP8__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VP8__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VP8__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VP8__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VP8__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VP8__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_VP8U__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VP8U__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VP8U__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VP8U__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VP8U__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VP8U__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VP8U__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VP8U__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VP8U__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VP8U__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VP8U__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000 +#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11 +#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000 +#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12 +#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000 +#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13 +#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4 +#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2 +#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78 +#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3 +#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780 +#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7 +#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800 +#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb +#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000 +#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12 +#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK 0xfe000000 +#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT 0x19 +#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1 +#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2 +#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1 +#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4 +#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2 +#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78 +#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3 +#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80 +#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7 +#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000 +#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd +#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000 +#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11 +#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000 +#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18 +#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1 +#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0 +#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe +#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1 +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0 +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 +#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 +#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff +#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0 +#define MC_HUB_RDREQ_VCE1__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCE1__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCE1__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCE1__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCE1__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCE1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCE1__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCE1__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCE1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCE1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCE1__VM_BYPASS_MASK 0x10000 +#define MC_HUB_RDREQ_VCE1__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_RDREQ_VCEU1__ENABLE_MASK 0x1 +#define MC_HUB_RDREQ_VCEU1__ENABLE__SHIFT 0x0 +#define MC_HUB_RDREQ_VCEU1__PRESCALE_MASK 0x6 +#define MC_HUB_RDREQ_VCEU1__PRESCALE__SHIFT 0x1 +#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_RDREQ_VCEU1__STALL_MODE_MASK 0x30 +#define MC_HUB_RDREQ_VCEU1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_RDREQ_VCEU1__MAXBURST_MASK 0x780 +#define MC_HUB_RDREQ_VCEU1__MAXBURST__SHIFT 0x7 +#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_HUB_WDP_VCE1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCE1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCE1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCE1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCE1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCE1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCE1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCE1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCE1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCE1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCE1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VCE1__VM_BYPASS_MASK 0x10000 +#define MC_HUB_WDP_VCE1__VM_BYPASS__SHIFT 0x10 +#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 +#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 +#define MC_HUB_WDP_VCEU1__ENABLE_MASK 0x1 +#define MC_HUB_WDP_VCEU1__ENABLE__SHIFT 0x0 +#define MC_HUB_WDP_VCEU1__PRESCALE_MASK 0x6 +#define MC_HUB_WDP_VCEU1__PRESCALE__SHIFT 0x1 +#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT_MASK 0x8 +#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3 +#define MC_HUB_WDP_VCEU1__STALL_MODE_MASK 0x30 +#define MC_HUB_WDP_VCEU1__STALL_MODE__SHIFT 0x4 +#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_MASK 0x40 +#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE__SHIFT 0x6 +#define MC_HUB_WDP_VCEU1__MAXBURST_MASK 0x780 +#define MC_HUB_WDP_VCEU1__MAXBURST__SHIFT 0x7 +#define MC_HUB_WDP_VCEU1__LAZY_TIMER_MASK 0x7800 +#define MC_HUB_WDP_VCEU1__LAZY_TIMER__SHIFT 0xb +#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000 +#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf +#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 +#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 +#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000 +#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000 +#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10 +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000 +#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11 +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff +#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0 +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00 +#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00 +#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8 +#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000 +#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14 +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff +#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00 +#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff +#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff +#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff +#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 +#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1 +#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0 +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6 +#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1 +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78 +#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3 +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80 +#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff +#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 +#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff +#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100 +#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8 +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600 +#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9 +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800 +#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb +#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000 +#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff +#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300 +#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8 +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00 +#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8 +#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10 +#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0 +#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000 +#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff +#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1 +#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e +#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff +#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000 +#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 +#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1 +#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0 +#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6 +#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1 +#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8 +#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3 +#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0 +#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4 +#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00 +#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8 +#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000 +#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10 +#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000 +#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18 +#define MC_RPB_TCI_CNTL2__TCI_POLICY_MASK 0x1 +#define MC_RPB_TCI_CNTL2__TCI_POLICY__SHIFT 0x0 +#define MC_RPB_TCI_CNTL2__TCI_MTYPE_MASK 0x6 +#define MC_RPB_TCI_CNTL2__TCI_MTYPE__SHIFT 0x1 +#define MC_RPB_TCI_CNTL2__TCI_SNOOP_MASK 0x8 +#define MC_RPB_TCI_CNTL2__TCI_SNOOP__SHIFT 0x3 +#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL_MASK 0x10 +#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL__SHIFT 0x4 +#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN_MASK 0x20 +#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN__SHIFT 0x5 +#define MC_RPB_TCI_CNTL2__TCI_EXE_MASK 0x40 +#define MC_RPB_TCI_CNTL2__TCI_EXE__SHIFT 0x6 +#define MC_SHARED_CHMAP__CHAN0_MASK 0xf +#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0 +#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0 +#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4 +#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00 +#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8 +#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000 +#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc +#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000 +#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10 +#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000 +#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14 +#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf +#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0 +#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0 +#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4 +#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00 +#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8 +#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000 +#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc +#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000 +#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10 +#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000 +#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14 +#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000 +#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18 +#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000 +#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c +#define MC_RD_GRP_GFX__CP_MASK 0xf +#define MC_RD_GRP_GFX__CP__SHIFT 0x0 +#define MC_RD_GRP_GFX__SH_MASK 0xf0 +#define MC_RD_GRP_GFX__SH__SHIFT 0x4 +#define MC_RD_GRP_GFX__IA_MASK 0xf00 +#define MC_RD_GRP_GFX__IA__SHIFT 0x8 +#define MC_RD_GRP_GFX__ACPG_MASK 0xf000 +#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc +#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000 +#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10 +#define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000 +#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14 +#define MC_RD_GRP_GFX__ISP_MASK 0xf000000 +#define MC_RD_GRP_GFX__ISP__SHIFT 0x18 +#define MC_RD_GRP_GFX__VP8_MASK 0xf0000000 +#define MC_RD_GRP_GFX__VP8__SHIFT 0x1c +#define MC_WR_GRP_GFX__CP_MASK 0xf +#define MC_WR_GRP_GFX__CP__SHIFT 0x0 +#define MC_WR_GRP_GFX__SH_MASK 0xf0 +#define MC_WR_GRP_GFX__SH__SHIFT 0x4 +#define MC_WR_GRP_GFX__ACPG_MASK 0xf00 +#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8 +#define MC_WR_GRP_GFX__ACPO_MASK 0xf000 +#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc +#define MC_WR_GRP_GFX__ISP_MASK 0xf0000 +#define MC_WR_GRP_GFX__ISP__SHIFT 0x10 +#define MC_WR_GRP_GFX__VP8_MASK 0xf00000 +#define MC_WR_GRP_GFX__VP8__SHIFT 0x14 +#define MC_WR_GRP_GFX__XDMA_MASK 0xf000000 +#define MC_WR_GRP_GFX__XDMA__SHIFT 0x18 +#define MC_WR_GRP_GFX__XDMAM_MASK 0xf0000000 +#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x1c +#define MC_RD_GRP_SYS__RLC_MASK 0xf +#define MC_RD_GRP_SYS__RLC__SHIFT 0x0 +#define MC_RD_GRP_SYS__VMC_MASK 0xf0 +#define MC_RD_GRP_SYS__VMC__SHIFT 0x4 +#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00 +#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8 +#define MC_RD_GRP_SYS__DMIF_MASK 0xf000 +#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc +#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000 +#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10 +#define MC_RD_GRP_SYS__SMU_MASK 0xf00000 +#define MC_RD_GRP_SYS__SMU__SHIFT 0x14 +#define MC_RD_GRP_SYS__VCE0_MASK 0xf000000 +#define MC_RD_GRP_SYS__VCE0__SHIFT 0x18 +#define MC_RD_GRP_SYS__VCE1_MASK 0xf0000000 +#define MC_RD_GRP_SYS__VCE1__SHIFT 0x1c +#define MC_WR_GRP_SYS__IH_MASK 0xf +#define MC_WR_GRP_SYS__IH__SHIFT 0x0 +#define MC_WR_GRP_SYS__MCIF_MASK 0xf0 +#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4 +#define MC_WR_GRP_SYS__RLC_MASK 0xf00 +#define MC_WR_GRP_SYS__RLC__SHIFT 0x8 +#define MC_WR_GRP_SYS__SAMMSP_MASK 0xf000 +#define MC_WR_GRP_SYS__SAMMSP__SHIFT 0xc +#define MC_WR_GRP_SYS__SMU_MASK 0xf0000 +#define MC_WR_GRP_SYS__SMU__SHIFT 0x10 +#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000 +#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14 +#define MC_WR_GRP_SYS__VCE0_MASK 0xf000000 +#define MC_WR_GRP_SYS__VCE0__SHIFT 0x18 +#define MC_WR_GRP_SYS__VCE1_MASK 0xf0000000 +#define MC_WR_GRP_SYS__VCE1__SHIFT 0x1c +#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf +#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0 +#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0 +#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4 +#define MC_RD_GRP_OTH__HDP_MASK 0xf00 +#define MC_RD_GRP_OTH__HDP__SHIFT 0x8 +#define MC_RD_GRP_OTH__SEM_MASK 0xf000 +#define MC_RD_GRP_OTH__SEM__SHIFT 0xc +#define MC_RD_GRP_OTH__UMC_MASK 0xf0000 +#define MC_RD_GRP_OTH__UMC__SHIFT 0x10 +#define MC_RD_GRP_OTH__UVD_MASK 0xf00000 +#define MC_RD_GRP_OTH__UVD__SHIFT 0x14 +#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000 +#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18 +#define MC_RD_GRP_OTH__SAMMSP_MASK 0xf0000000 +#define MC_RD_GRP_OTH__SAMMSP__SHIFT 0x1c +#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf +#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0 +#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0 +#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4 +#define MC_WR_GRP_OTH__HDP_MASK 0xf00 +#define MC_WR_GRP_OTH__HDP__SHIFT 0x8 +#define MC_WR_GRP_OTH__SEM_MASK 0xf000 +#define MC_WR_GRP_OTH__SEM__SHIFT 0xc +#define MC_WR_GRP_OTH__UMC_MASK 0xf0000 +#define MC_WR_GRP_OTH__UMC__SHIFT 0x10 +#define MC_WR_GRP_OTH__UVD_MASK 0xf00000 +#define MC_WR_GRP_OTH__UVD__SHIFT 0x14 +#define MC_WR_GRP_OTH__XDP_MASK 0xf000000 +#define MC_WR_GRP_OTH__XDP__SHIFT 0x18 +#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000 +#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c +#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff +#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0 +#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000 +#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10 +#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff +#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff +#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff +#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0 +#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200 +#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9 +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff +#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20 +#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40 +#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780 +#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff +#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3 +#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf +#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0 +#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0 +#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4 +#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00 +#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8 +#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000 +#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc +#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000 +#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10 +#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000 +#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14 +#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000 +#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18 +#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000 +#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c +#define MC_SHARED_VF_ENABLE__VF_ENABLE_MASK 0x1 +#define MC_SHARED_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0xffff +#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0xf +#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000 +#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 +#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 +#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 +#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 +#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 +#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 +#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 +#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 +#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 +#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 +#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 +#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 +#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40 +#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6 +#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80 +#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7 +#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 +#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 +#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800 +#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb +#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000 +#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc +#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000 +#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000 +#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 +#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 +#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 +#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 +#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 +#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 +#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 +#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40 +#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6 +#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80 +#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800 +#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb +#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000 +#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd +#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f +#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0 +#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE_MASK 0x8 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE__SHIFT 0x3 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM_MASK 0xff0 +#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM__SHIFT 0x4 +#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH_MASK 0x1000 +#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH__SHIFT 0xc +#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN_MASK 0x2000 +#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN__SHIFT 0xd +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f +#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1 +#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f +#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 +#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 +#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 +#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 +#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 +#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1 +#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff +#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1 +#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000 +#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 +#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff +#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00 +#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8 +#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000 +#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10 +#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000 +#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11 +#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000 +#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19 +#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff +#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0 +#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00 +#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa +#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000 +#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14 +#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000 +#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f +#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0 +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0 +#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6 +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000 +#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f +#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0 +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0 +#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6 +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000 +#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc +#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff +#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000 +#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000 +#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 +#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff +#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0 +#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000 +#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10 +#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000 +#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12 +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf +#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 +#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30 +#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40 +#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 +#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80 +#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100 +#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200 +#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400 +#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa +#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800 +#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000 +#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc +#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf +#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 +#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0 +#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff +#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00 +#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 +#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000 +#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000 +#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000 +#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe +#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000 +#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf +#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000 +#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 +#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff +#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00 +#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8 +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000 +#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff +#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00 +#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff +#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00 +#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 +#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2 +#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1 +#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2 +#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1 +#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc +#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 +#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc +#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2 +#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f +#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0 +#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0 +#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6 +#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000 +#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc +#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000 +#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12 +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000 +#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff +#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 +#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00 +#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 +#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000 +#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000 +#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000 +#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000 +#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000 +#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000 +#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000 +#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff +#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 +#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00 +#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000 +#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000 +#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 +#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000 +#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 +#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000 +#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000 +#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1 +#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe +#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000 +#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000 +#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000 +#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000 +#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000 +#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000 +#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 +#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000 +#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000 +#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1 +#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2 +#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4 +#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8 +#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10 +#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20 +#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40 +#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80 +#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100 +#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200 +#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 +#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400 +#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa +#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800 +#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb +#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000 +#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc +#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000 +#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd +#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000 +#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe +#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000 +#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf +#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000 +#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 +#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000 +#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 +#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000 +#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 +#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000 +#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff +#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f +#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0 +#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000 +#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc +#define MC_XPB_STICKY__BITS_MASK 0xffffffff +#define MC_XPB_STICKY__BITS__SHIFT 0x0 +#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff +#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0 +#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff +#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 +#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00 +#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 +#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000 +#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 +#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000 +#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 +#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000 +#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f +#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff +#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff +#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0 +#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00 +#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8 +#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000 +#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10 +#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000 +#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11 +#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000 +#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19 +#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe +#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf +#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0 +#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70 +#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4 +#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380 +#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7 +#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00 +#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa +#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000 +#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1 +#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0 +#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2 +#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4 +#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8 +#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3 +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1 +#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0 +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2 +#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1 +#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000 +#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18 +#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000 +#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000 +#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00 +#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8 +#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3 +#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0 +#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc +#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2 +#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30 +#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4 +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1 +#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0 +#define MC_XBAR_TWOCHAN__CH0_MASK 0x6 +#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1 +#define MC_XBAR_TWOCHAN__CH1_MASK 0x18 +#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3 +#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1 +#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0 +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2 +#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1 +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4 +#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2 +#define MC_XBAR_ARB__ACP_RDRET_URG_MASK 0x8 +#define MC_XBAR_ARB__ACP_RDRET_URG__SHIFT 0x3 +#define MC_XBAR_ARB__HDP_RDRET_URG_MASK 0x10 +#define MC_XBAR_ARB__HDP_RDRET_URG__SHIFT 0x4 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf +#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000 +#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000 +#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c +#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH_MASK 0xfff +#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH_MASK 0xfff000 +#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH__SHIFT 0xc +#define MC_XBAR_FIFO_MON_CNTL0__START_MODE_MASK 0x3000000 +#define MC_XBAR_FIFO_MON_CNTL0__START_MODE__SHIFT 0x18 +#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE_MASK 0xc000000 +#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE__SHIFT 0x1a +#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 +#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c +#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff +#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID_MASK 0xff00 +#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID__SHIFT 0x8 +#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000 +#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10 +#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID_MASK 0xff +#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID_MASK 0xff00 +#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID__SHIFT 0x8 +#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID_MASK 0xff0000 +#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID__SHIFT 0x10 +#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID_MASK 0xff000000 +#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID__SHIFT 0x18 +#define MC_XBAR_FIFO_MON_RSLT0__COUNT_MASK 0xffffffff +#define MC_XBAR_FIFO_MON_RSLT0__COUNT__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_RSLT1__COUNT_MASK 0xffffffff +#define MC_XBAR_FIFO_MON_RSLT1__COUNT__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_RSLT2__COUNT_MASK 0xffffffff +#define MC_XBAR_FIFO_MON_RSLT2__COUNT__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_RSLT3__COUNT_MASK 0xffffffff +#define MC_XBAR_FIFO_MON_RSLT3__COUNT__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON0_MASK 0xff +#define MC_XBAR_FIFO_MON_MAX_THSH__MON0__SHIFT 0x0 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON1_MASK 0xff00 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON1__SHIFT 0x8 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON2_MASK 0xff0000 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON2__SHIFT 0x10 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON3_MASK 0xff000000 +#define MC_XBAR_FIFO_MON_MAX_THSH__MON3__SHIFT 0x18 +#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff +#define MC_XBAR_SPARE0__BIT__SHIFT 0x0 +#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff +#define MC_XBAR_SPARE1__BIT__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff +#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 +#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 +#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 +#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff +#define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff +#define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 +#define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff +#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 +#define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MC_GRUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 +#define MC_GRUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MC_GRUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 +#define MC_GRUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff +#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 +#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 +#define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MC_GRUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 +#define MC_GRUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MC_GRUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 +#define MC_GRUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 +#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff +#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3 +#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3 +#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff +#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff +#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 +#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1 +#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 +#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2 +#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 +#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4 +#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 +#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00 +#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 +#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000 +#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10 +#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1 +#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0 +#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2 +#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1 +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4 +#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2 +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20 +#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5 +#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40 +#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6 +#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80 +#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7 +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100 +#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8 +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200 +#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9 +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00 +#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000 +#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe +#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000 +#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000 +#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10 +#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000 +#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11 +#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000 +#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12 +#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING_MASK 0x80000 +#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING__SHIFT 0x13 +#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH_MASK 0x100000 +#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH__SHIFT 0x14 +#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT_MASK 0x200000 +#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__SHIFT 0x15 +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f +#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0 +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100 +#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8 +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000 +#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10 +#define ATC_ATS_STATUS__BUSY_MASK 0x1 +#define ATC_ATS_STATUS__BUSY__SHIFT 0x0 +#define ATC_ATS_STATUS__CRASHED_MASK 0x2 +#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x1ff +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x7fc00 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1ff00000 +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x1ff +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00 +#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000 +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xfffffff +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1 +#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x1 +#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x3e +#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 +#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID_MASK 0x1fe00 +#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID__SHIFT 0x9 +#define ATC_MISC_CG__OFFDLY_MASK 0xfc0 +#define ATC_MISC_CG__OFFDLY__SHIFT 0x6 +#define ATC_MISC_CG__ENABLE_MASK 0x40000 +#define ATC_MISC_CG__ENABLE__SHIFT 0x12 +#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000 +#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200 +#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9 +#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f +#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100 +#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00 +#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000 +#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000 +#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf +#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f +#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0 +#define ATC_L2_DEBUG__L2_MEM_SELECT_MASK 0x80 +#define ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT 0x7 +#define ATC_L2_DEBUG__CACHE_INDEX_MASK 0xfff00 +#define ATC_L2_DEBUG__CACHE_INDEX__SHIFT 0x8 +#define ATC_L2_DEBUG__CACHE_SELECT_MASK 0x1000000 +#define ATC_L2_DEBUG__CACHE_SELECT__SHIFT 0x18 +#define ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK 0x2000000 +#define ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT 0x19 +#define ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK 0x8000000 +#define ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT 0x1b +#define ATC_L2_DEBUG__CACHE_READ_MASK 0x20000000 +#define ATC_L2_DEBUG__CACHE_READ__SHIFT 0x1d +#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK 0x40000000 +#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT 0x1e +#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK 0x80000000 +#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT 0x1f +#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f +#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0 +#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0 +#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5 +#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100 +#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8 +#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200 +#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9 +#define ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK 0x400 +#define ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT 0xa +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK 0x800 +#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT 0xb +#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000 +#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe +#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000 +#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf +#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000 +#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11 +#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK 0x780000 +#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT 0x13 +#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD_MASK 0x7f800000 +#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD__SHIFT 0x17 +#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK 0x80000000 +#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT 0x1f +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x1 +#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x2 +#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x1fffffc +#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x1e000000 +#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x19 +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xffffffff +#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW_MASK 0xfffffff +#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3 +#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0 +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4 +#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2 +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10 +#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4 +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff +#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0 +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 +#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 +#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 +#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 +#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 +#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 +#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 +#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e +#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 +#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 +#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 +#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 +#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 +#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 +#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 +#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 +#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e +#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 +#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f +#define ATC_L1RD_STATUS__BUSY_MASK 0x1 +#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0 +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2 +#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 +#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100 +#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8 +#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000 +#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc +#define ATC_L1RD_STATUS__CAM_INDEX_MASK 0x3e0000 +#define ATC_L1RD_STATUS__CAM_INDEX__SHIFT 0x11 +#define ATC_L1WR_STATUS__BUSY_MASK 0x1 +#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0 +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2 +#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 +#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100 +#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8 +#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000 +#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc +#define ATC_L1WR_STATUS__CAM_INDEX_MASK 0x3e0000 +#define ATC_L1WR_STATUS__CAM_INDEX__SHIFT 0x11 +#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff +#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0 +#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000 +#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe +#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000 +#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10 +#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000 +#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11 +#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000 +#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12 +#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000 +#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13 +#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff +#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0 +#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000 +#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe +#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000 +#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10 +#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000 +#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11 +#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000 +#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12 +#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000 +#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf +#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff +#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 +#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000 +#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x1 +#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 +#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x2 +#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 +#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x4 +#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 +#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x8 +#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 +#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x10 +#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 +#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x20 +#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 +#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x40 +#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 +#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x80 +#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 +#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x100 +#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 +#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x200 +#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 +#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x400 +#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa +#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x800 +#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb +#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x1000 +#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc +#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x2000 +#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd +#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x4000 +#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe +#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x8000 +#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf +#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN_MASK 0x1 +#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN__SHIFT 0x0 +#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING_MASK 0x7f +#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING__SHIFT 0x0 +#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER_MASK 0x80 +#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER__SHIFT 0x7 +#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD_MASK 0x1f00 +#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD__SHIFT 0x8 +#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION_MASK 0x2000 +#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION__SHIFT 0xd +#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST_MASK 0x1c000 +#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0xe +#define ATC_L2_STATUS__BUSY_MASK 0x1 +#define ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3ffffffe +#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 +#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE_MASK 0x7 +#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE__SHIFT 0x0 +#define ATC_L2_STATUS2__PARITY_ERROR_INFO_MASK 0x7f8 +#define ATC_L2_STATUS2__PARITY_ERROR_INFO__SHIFT 0x3 +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff +#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff +#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000 +#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16 +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400 +#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800 +#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000 +#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc +#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000 +#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10 +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000 +#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11 +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000 +#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13 +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000 +#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15 +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000 +#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16 +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000 +#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17 +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000 +#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18 +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000 +#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19 +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000 +#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a +#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000 +#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000 +#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000 +#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f +#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f +#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0 +#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0 +#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6 +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800 +#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb +#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000 +#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11 +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000 +#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000 +#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e +#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000 +#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000 +#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 +#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff +#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0 +#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000 +#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc +#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000 +#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18 +#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000 +#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 +#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c +#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000 +#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d +#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000 +#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e +#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000 +#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f +#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0 +#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6 +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000 +#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc +#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000 +#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12 +#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000 +#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19 +#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff +#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0 +#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff +#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0 +#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff +#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 +#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200 +#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400 +#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800 +#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000 +#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000 +#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd +#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000 +#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 +#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 +#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff +#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0 +#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff +#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0 +#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000 +#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18 +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000 +#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c +#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff +#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0 +#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00 +#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8 +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000 +#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 +#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000 +#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c +#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000 +#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d +#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000 +#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2 +#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8 +#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3 +#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0 +#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4 +#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff +#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0 +#define GMCON_DEBUG__GFX_STALL_MASK 0x1 +#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0 +#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2 +#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1 +#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0_MASK 0x4 +#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0__SHIFT 0x2 +#define GMCON_DEBUG__SR_COMMIT_STATE_MASK 0x8 +#define GMCON_DEBUG__SR_COMMIT_STATE__SHIFT 0x3 +#define GMCON_DEBUG__STCTRL_ST_MASK 0xf0 +#define GMCON_DEBUG__STCTRL_ST__SHIFT 0x4 +#define GMCON_DEBUG__MISC_FLAGS_MASK 0xffffff00 +#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x8 +#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1 +#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2 +#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc +#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30 +#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100 +#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200 +#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 +#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800 +#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000 +#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000 +#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000 +#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000 +#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000 +#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000 +#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000 +#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1 +#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2 +#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000 +#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000 +#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000 +#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000 +#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000 +#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f +#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00 +#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000 +#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000 +#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000 +#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000 +#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VM_L2_STATUS__L2_BUSY_MASK 0x1 +#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe +#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1 +#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 +#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 +#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 +#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 +#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 +#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 +#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 +#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 +#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1 +#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 +#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 +#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 +#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 +#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 +#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 +#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 +#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 +#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc +#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2 +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff +#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 +#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 +#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 +#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 +#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 +#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 +#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 +#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 +#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 +#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 +#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000 +#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000 +#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1 +#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0 +#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2 +#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1 +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4 +#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2 +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8 +#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3 +#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10 +#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4 +#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20 +#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5 +#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40 +#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000 +#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000 +#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000 +#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d +#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff +#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff +#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff +#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB_MASK 0x40000 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB__SHIFT 0x12 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB_MASK 0x80000 +#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB__SHIFT 0x13 +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_DEBUG__FLAGS_MASK 0xffffffff +#define VM_DEBUG__FLAGS__SHIFT 0x0 +#define VM_L2_CG__OFFDLY_MASK 0xfc0 +#define VM_L2_CG__OFFDLY__SHIFT 0x6 +#define VM_L2_CG__ENABLE_MASK 0x40000 +#define VM_L2_CG__ENABLE__SHIFT 0x12 +#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000 +#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define VM_L2_CG__OVERRIDE_MASK 0x100000 +#define VM_L2_CG__OVERRIDE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff +#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0 +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x7f +#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff +#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff +#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0 +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x3f +#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x40 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x80 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x100 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x200 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x400 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x800 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x1000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x2000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x4000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x8000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x10000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x20000 +#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x1ff +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x100000 +#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000 +#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0xffff +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xffff0000 +#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xffffffff +#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xffffffff +#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x800000 +#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x8 +#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xff800000 +#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x1 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xff800000 +#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0xff +#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3fffffff +#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0 +#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000 +#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xfffff000 +#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xfffff000 +#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xfffff000 +#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xfffff000 +#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0xfffff +#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0xfffff +#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0xfffff +#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0xfffff +#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x1 +#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x2 +#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xfffff000 +#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x1 +#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x2 +#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xfffff000 +#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x1 +#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x2 +#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xfffff000 +#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x1 +#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x2 +#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xfffff000 +#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0xfffff +#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0xfffff +#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0xfffff +#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0xfffff +#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xfffff000 +#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xfffff000 +#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xfffff000 +#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xfffff000 +#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0xfffff +#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0xfffff +#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0xfffff +#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0xfffff +#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 +#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS_MASK 0x1 +#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS__SHIFT 0x0 +#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff +#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0 +#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00 +#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8 +#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000 +#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10 +#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000 +#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18 +#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff +#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0 +#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00 +#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8 +#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000 +#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10 +#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000 +#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff +#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff +#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0 +#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00 +#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8 +#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000 +#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10 +#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000 +#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18 +#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff +#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff +#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0 +#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00 +#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8 +#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000 +#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10 +#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000 +#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18 +#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff +#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0 +#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100 +#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8 +#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200 +#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9 +#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400 +#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa +#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800 +#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb +#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000 +#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc +#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000 +#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe +#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000 +#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16 +#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff +#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0 +#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100 +#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8 +#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200 +#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9 +#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400 +#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa +#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800 +#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb +#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000 +#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc +#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000 +#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe +#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000 +#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16 +#define MC_ARB_GRUB_PRIORITY1_RD__CB0_MASK 0x3 +#define MC_ARB_GRUB_PRIORITY1_RD__CB0__SHIFT 0x0 +#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0_MASK 0xc +#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0__SHIFT 0x2 +#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0_MASK 0x30 +#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0__SHIFT 0x4 +#define MC_ARB_GRUB_PRIORITY1_RD__DB0_MASK 0xc0 +#define MC_ARB_GRUB_PRIORITY1_RD__DB0__SHIFT 0x6 +#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0_MASK 0x300 +#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0__SHIFT 0x8 +#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0_MASK 0xc00 +#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0__SHIFT 0xa +#define MC_ARB_GRUB_PRIORITY1_RD__TC0_MASK 0x3000 +#define MC_ARB_GRUB_PRIORITY1_RD__TC0__SHIFT 0xc +#define MC_ARB_GRUB_PRIORITY1_RD__ACPG_MASK 0xc000 +#define MC_ARB_GRUB_PRIORITY1_RD__ACPG__SHIFT 0xe +#define MC_ARB_GRUB_PRIORITY1_RD__ACPO_MASK 0x30000 +#define MC_ARB_GRUB_PRIORITY1_RD__ACPO__SHIFT 0x10 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_MASK 0xc0000 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF__SHIFT 0x12 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0_MASK 0x300000 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0__SHIFT 0x14 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1_MASK 0xc00000 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1__SHIFT 0x16 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW_MASK 0x3000000 +#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW__SHIFT 0x18 +#define MC_ARB_GRUB_PRIORITY1_RD__MCIF_MASK 0xc000000 +#define MC_ARB_GRUB_PRIORITY1_RD__MCIF__SHIFT 0x1a +#define MC_ARB_GRUB_PRIORITY1_RD__RLC_MASK 0x30000000 +#define MC_ARB_GRUB_PRIORITY1_RD__RLC__SHIFT 0x1c +#define MC_ARB_GRUB_PRIORITY1_RD__VMC_MASK 0xc0000000 +#define MC_ARB_GRUB_PRIORITY1_RD__VMC__SHIFT 0x1e +#define MC_ARB_GRUB_PRIORITY1_WR__CB0_MASK 0x3 +#define MC_ARB_GRUB_PRIORITY1_WR__CB0__SHIFT 0x0 +#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0_MASK 0xc +#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0__SHIFT 0x2 +#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0_MASK 0x30 +#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0__SHIFT 0x4 +#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0_MASK 0xc0 +#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0__SHIFT 0x6 +#define MC_ARB_GRUB_PRIORITY1_WR__DB0_MASK 0x300 +#define MC_ARB_GRUB_PRIORITY1_WR__DB0__SHIFT 0x8 +#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0_MASK 0xc00 +#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0__SHIFT 0xa +#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0_MASK 0x3000 +#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0__SHIFT 0xc +#define MC_ARB_GRUB_PRIORITY1_WR__TC0_MASK 0xc000 +#define MC_ARB_GRUB_PRIORITY1_WR__TC0__SHIFT 0xe +#define MC_ARB_GRUB_PRIORITY1_WR__SH_MASK 0x30000 +#define MC_ARB_GRUB_PRIORITY1_WR__SH__SHIFT 0x10 +#define MC_ARB_GRUB_PRIORITY1_WR__ACPG_MASK 0xc0000 +#define MC_ARB_GRUB_PRIORITY1_WR__ACPG__SHIFT 0x12 +#define MC_ARB_GRUB_PRIORITY1_WR__ACPO_MASK 0x300000 +#define MC_ARB_GRUB_PRIORITY1_WR__ACPO__SHIFT 0x14 +#define MC_ARB_GRUB_PRIORITY1_WR__MCIF_MASK 0xc00000 +#define MC_ARB_GRUB_PRIORITY1_WR__MCIF__SHIFT 0x16 +#define MC_ARB_GRUB_PRIORITY1_WR__RLC_MASK 0x3000000 +#define MC_ARB_GRUB_PRIORITY1_WR__RLC__SHIFT 0x18 +#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1_MASK 0xc000000 +#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1__SHIFT 0x1a +#define MC_ARB_GRUB_PRIORITY1_WR__SMU_MASK 0x30000000 +#define MC_ARB_GRUB_PRIORITY1_WR__SMU__SHIFT 0x1c +#define MC_ARB_GRUB_PRIORITY1_WR__VCE0_MASK 0xc0000000 +#define MC_ARB_GRUB_PRIORITY1_WR__VCE0__SHIFT 0x1e +#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1_MASK 0x3 +#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1__SHIFT 0x0 +#define MC_ARB_GRUB_PRIORITY2_RD__SMU_MASK 0xc +#define MC_ARB_GRUB_PRIORITY2_RD__SMU__SHIFT 0x2 +#define MC_ARB_GRUB_PRIORITY2_RD__VCE0_MASK 0x30 +#define MC_ARB_GRUB_PRIORITY2_RD__VCE0__SHIFT 0x4 +#define MC_ARB_GRUB_PRIORITY2_RD__VCE1_MASK 0xc0 +#define MC_ARB_GRUB_PRIORITY2_RD__VCE1__SHIFT 0x6 +#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM_MASK 0x300 +#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM__SHIFT 0x8 +#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0_MASK 0xc00 +#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0__SHIFT 0xa +#define MC_ARB_GRUB_PRIORITY2_RD__HDP_MASK 0x3000 +#define MC_ARB_GRUB_PRIORITY2_RD__HDP__SHIFT 0xc +#define MC_ARB_GRUB_PRIORITY2_RD__UMC_MASK 0xc000 +#define MC_ARB_GRUB_PRIORITY2_RD__UMC__SHIFT 0xe +#define MC_ARB_GRUB_PRIORITY2_RD__UVD_MASK 0x30000 +#define MC_ARB_GRUB_PRIORITY2_RD__UVD__SHIFT 0x10 +#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0_MASK 0xc0000 +#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0__SHIFT 0x12 +#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1_MASK 0x300000 +#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1__SHIFT 0x14 +#define MC_ARB_GRUB_PRIORITY2_RD__SEM_MASK 0xc00000 +#define MC_ARB_GRUB_PRIORITY2_RD__SEM__SHIFT 0x16 +#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP_MASK 0x3000000 +#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP__SHIFT 0x18 +#define MC_ARB_GRUB_PRIORITY2_RD__VP8_MASK 0xc000000 +#define MC_ARB_GRUB_PRIORITY2_RD__VP8__SHIFT 0x1a +#define MC_ARB_GRUB_PRIORITY2_RD__ISP_MASK 0x30000000 +#define MC_ARB_GRUB_PRIORITY2_RD__ISP__SHIFT 0x1c +#define MC_ARB_GRUB_PRIORITY2_RD__RSV2_MASK 0xc0000000 +#define MC_ARB_GRUB_PRIORITY2_RD__RSV2__SHIFT 0x1e +#define MC_ARB_GRUB_PRIORITY2_WR__VCE1_MASK 0x3 +#define MC_ARB_GRUB_PRIORITY2_WR__VCE1__SHIFT 0x0 +#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP_MASK 0xc +#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP__SHIFT 0x2 +#define MC_ARB_GRUB_PRIORITY2_WR__XDMA_MASK 0x30 +#define MC_ARB_GRUB_PRIORITY2_WR__XDMA__SHIFT 0x4 +#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM_MASK 0xc0 +#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM__SHIFT 0x6 +#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0_MASK 0x300 +#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0__SHIFT 0x8 +#define MC_ARB_GRUB_PRIORITY2_WR__HDP_MASK 0xc00 +#define MC_ARB_GRUB_PRIORITY2_WR__HDP__SHIFT 0xa +#define MC_ARB_GRUB_PRIORITY2_WR__UMC_MASK 0x3000 +#define MC_ARB_GRUB_PRIORITY2_WR__UMC__SHIFT 0xc +#define MC_ARB_GRUB_PRIORITY2_WR__UVD_MASK 0xc000 +#define MC_ARB_GRUB_PRIORITY2_WR__UVD__SHIFT 0xe +#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0_MASK 0x30000 +#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0__SHIFT 0x10 +#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1_MASK 0xc0000 +#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1__SHIFT 0x12 +#define MC_ARB_GRUB_PRIORITY2_WR__XDP_MASK 0x300000 +#define MC_ARB_GRUB_PRIORITY2_WR__XDP__SHIFT 0x14 +#define MC_ARB_GRUB_PRIORITY2_WR__SEM_MASK 0xc00000 +#define MC_ARB_GRUB_PRIORITY2_WR__SEM__SHIFT 0x16 +#define MC_ARB_GRUB_PRIORITY2_WR__IH_MASK 0x3000000 +#define MC_ARB_GRUB_PRIORITY2_WR__IH__SHIFT 0x18 +#define MC_ARB_GRUB_PRIORITY2_WR__VP8_MASK 0xc000000 +#define MC_ARB_GRUB_PRIORITY2_WR__VP8__SHIFT 0x1a +#define MC_ARB_GRUB_PRIORITY2_WR__ISP_MASK 0x30000000 +#define MC_ARB_GRUB_PRIORITY2_WR__ISP__SHIFT 0x1c +#define MC_ARB_GRUB_PRIORITY2_WR__VIN0_MASK 0xc0000000 +#define MC_ARB_GRUB_PRIORITY2_WR__VIN0__SHIFT 0x1e +#define MC_FUS_DRAM0_CS0_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM0_CS0_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM1_CS0_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM1_CS0_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM0_CS1_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM0_CS1_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM1_CS1_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM1_CS1_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM0_CS2_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM0_CS2_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM1_CS2_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM1_CS2_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM0_CS3_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM0_CS3_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM1_CS3_BASE__CSENABLE_MASK 0x1 +#define MC_FUS_DRAM1_CS3_BASE__CSENABLE__SHIFT 0x0 +#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11_MASK 0xffe0 +#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11__SHIFT 0x5 +#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000 +#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27__SHIFT 0x13 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200 +#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200 +#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9 +#define MC_FUS_DRAM0_CTL_BASE__DCTSEL_MASK 0x7 +#define MC_FUS_DRAM0_CTL_BASE__DCTSEL__SHIFT 0x0 +#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN_MASK 0x78 +#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN__SHIFT 0x3 +#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR_MASK 0xfffff80 +#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR__SHIFT 0x7 +#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN_MASK 0x10000000 +#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c +#define MC_FUS_DRAM1_CTL_BASE__DCTSEL_MASK 0x7 +#define MC_FUS_DRAM1_CTL_BASE__DCTSEL__SHIFT 0x0 +#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN_MASK 0x78 +#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN__SHIFT 0x3 +#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR_MASK 0xfffff80 +#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR__SHIFT 0x7 +#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN_MASK 0x10000000 +#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c +#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff +#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0 +#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000 +#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15 +#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff +#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0 +#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000 +#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15 +#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0_MASK 0xfff +#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0__SHIFT 0x0 +#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1_MASK 0xfff000 +#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1__SHIFT 0xc +#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2_MASK 0xfff +#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2__SHIFT 0x0 +#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3_MASK 0xfff000 +#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3__SHIFT 0xc +#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR_MASK 0x7 +#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR__SHIFT 0x0 +#define MC_FUS_DRAM_MODE__DRAMTYPE_MASK 0x38 +#define MC_FUS_DRAM_MODE__DRAMTYPE__SHIFT 0x3 +#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET_MASK 0x7fc0 +#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET__SHIFT 0x6 +#define MC_FUS_DRAM_MODE__DDR3LPX32_MASK 0x8000 +#define MC_FUS_DRAM_MODE__DDR3LPX32__SHIFT 0xf +#define MC_FUS_DRAM_MODE__BANKGROUPSWAP_MASK 0x10000 +#define MC_FUS_DRAM_MODE__BANKGROUPSWAP__SHIFT 0x10 +#define MC_FUS_DRAM_APER_BASE__BASE_MASK 0xfffff +#define MC_FUS_DRAM_APER_BASE__BASE__SHIFT 0x0 +#define MC_FUS_DRAM_APER_TOP__TOP_MASK 0xfffff +#define MC_FUS_DRAM_APER_TOP__TOP__SHIFT 0x0 +#define MC_FUS_DRAM_APER_DEF__DEF_MASK 0xfffffff +#define MC_FUS_DRAM_APER_DEF__DEF__SHIFT 0x0 +#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS_MASK 0x10000000 +#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS__SHIFT 0x1c +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN_MASK 0x1 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN__SHIFT 0x0 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN_MASK 0x2 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN__SHIFT 0x1 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN_MASK 0x4 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN__SHIFT 0x2 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN_MASK 0x8 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN__SHIFT 0x3 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN_MASK 0x10 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN__SHIFT 0x4 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN_MASK 0x20 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN__SHIFT 0x5 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN_MASK 0x40 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN__SHIFT 0x6 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN_MASK 0x80 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN__SHIFT 0x7 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN_MASK 0x100 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN__SHIFT 0x8 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN_MASK 0x200 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN__SHIFT 0x9 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN_MASK 0x400 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN__SHIFT 0xa +#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN_MASK 0x800 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN__SHIFT 0xb +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN_MASK 0x1000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN__SHIFT 0xc +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN_MASK 0x2000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN__SHIFT 0xd +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN_MASK 0x4000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN__SHIFT 0xe +#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN_MASK 0x8000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN__SHIFT 0xf +#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL_MASK 0x30000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL__SHIFT 0x10 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN_MASK 0x40000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN__SHIFT 0x12 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN_MASK 0x80000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN__SHIFT 0x13 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN_MASK 0x100000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN__SHIFT 0x14 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL_MASK 0x200000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL__SHIFT 0x15 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL_MASK 0x400000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL__SHIFT 0x16 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL_MASK 0x800000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL__SHIFT 0x17 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS_MASK 0x1f000000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS__SHIFT 0x18 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE_MASK 0x20000000 +#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT 0x1d +#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE_MASK 0xff +#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x0 +#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE_MASK 0x7f00 +#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x8 +#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE_MASK 0x8000 +#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE__SHIFT 0xf +#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE_MASK 0x10000 +#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE__SHIFT 0x10 +#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT_MASK 0x3fe0000 +#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT__SHIFT 0x11 +#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT_MASK 0xfc000000 +#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT__SHIFT 0x1a +#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI_MASK 0x3 +#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI__SHIFT 0x0 +#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI_MASK 0xc +#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI__SHIFT 0x2 +#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI_MASK 0x30 +#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI__SHIFT 0x4 +#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI_MASK 0xc0 +#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI__SHIFT 0x6 +#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI_MASK 0x300 +#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI__SHIFT 0x8 +#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI_MASK 0xc00 +#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI__SHIFT 0xa +#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI_MASK 0x3000 +#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI__SHIFT 0xc +#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI_MASK 0xc000 +#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI__SHIFT 0xe +#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI_MASK 0x30000 +#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI__SHIFT 0x10 +#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI_MASK 0xc0000 +#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI__SHIFT 0x12 +#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI_MASK 0x300000 +#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI__SHIFT 0x14 +#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI_MASK 0xc00000 +#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI__SHIFT 0x16 +#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI_MASK 0x3000000 +#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI__SHIFT 0x18 +#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI_MASK 0xc000000 +#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI__SHIFT 0x1a +#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI_MASK 0x30000000 +#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI__SHIFT 0x1c +#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI_MASK 0xc0000000 +#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI__SHIFT 0x1e +#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI_MASK 0x3 +#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI__SHIFT 0x0 +#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI_MASK 0xc +#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI__SHIFT 0x2 +#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI_MASK 0x30 +#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI__SHIFT 0x4 +#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff +#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0 +#define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP_MASK 0x3 +#define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP__SHIFT 0x0 +#define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP_MASK 0xc +#define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP__SHIFT 0x2 +#define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP_MASK 0x30 +#define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP__SHIFT 0x4 +#define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP_MASK 0xc0 +#define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP__SHIFT 0x6 +#define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP_MASK 0x100 +#define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP__SHIFT 0x8 +#define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP_MASK 0x200 +#define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP__SHIFT 0x9 +#define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP_MASK 0x400 +#define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP__SHIFT 0xa +#define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP_MASK 0x800 +#define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP__SHIFT 0xb +#define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY_MASK 0x1f +#define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY__SHIFT 0x0 +#define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY_MASK 0x1f00 +#define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY__SHIFT 0x8 +#define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY_MASK 0x1f0000 +#define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY__SHIFT 0x10 +#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO_MASK 0x3f +#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO__SHIFT 0x0 +#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI_MASK 0x3f00 +#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI__SHIFT 0x8 +#define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL_MASK 0x8000 +#define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL__SHIFT 0xf +#define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH_MASK 0x70000 +#define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH__SHIFT 0x10 +#define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH_MASK 0x700000 +#define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH__SHIFT 0x14 +#define MC_GRUB_FEATURES__WR_COMBINE_OFF_MASK 0x1 +#define MC_GRUB_FEATURES__WR_COMBINE_OFF__SHIFT 0x0 +#define MC_GRUB_FEATURES__SCLK_CG_DISABLE_MASK 0x2 +#define MC_GRUB_FEATURES__SCLK_CG_DISABLE__SHIFT 0x1 +#define MC_GRUB_FEATURES__PRB_FILTER_DISABLE_MASK 0x4 +#define MC_GRUB_FEATURES__PRB_FILTER_DISABLE__SHIFT 0x2 +#define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE_MASK 0x8 +#define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE__SHIFT 0x3 +#define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY_MASK 0x10 +#define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY__SHIFT 0x4 +#define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE_MASK 0x20 +#define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE__SHIFT 0x5 +#define MC_GRUB_FEATURES__RT_BYPASS_OFF_MASK 0x40 +#define MC_GRUB_FEATURES__RT_BYPASS_OFF__SHIFT 0x6 +#define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE_MASK 0x80 +#define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE__SHIFT 0x7 +#define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE_MASK 0x100 +#define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE__SHIFT 0x8 +#define MC_GRUB_FEATURES__ARB_STALL_EN_MASK 0x400 +#define MC_GRUB_FEATURES__ARB_STALL_EN__SHIFT 0xa +#define MC_GRUB_FEATURES__CREDIT_STALL_EN_MASK 0x800 +#define MC_GRUB_FEATURES__CREDIT_STALL_EN__SHIFT 0xb +#define MC_GRUB_FEATURES__ARB_STALL_SET_SEL_MASK 0x3000 +#define MC_GRUB_FEATURES__ARB_STALL_SET_SEL__SHIFT 0xc +#define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL_MASK 0xc000 +#define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL__SHIFT 0xe +#define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL_MASK 0x30000 +#define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL__SHIFT 0x10 +#define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL_MASK 0xc0000 +#define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL__SHIFT 0x12 +#define MC_GRUB_FEATURES__WR_REORDER_OFF_MASK 0x100000 +#define MC_GRUB_FEATURES__WR_REORDER_OFF__SHIFT 0x14 +#define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT_MASK 0x3f +#define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT__SHIFT 0x0 +#define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE_MASK 0xf00 +#define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE__SHIFT 0x8 +#define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE_MASK 0xf000 +#define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE__SHIFT 0xc +#define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE_MASK 0xf0000 +#define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE__SHIFT 0x10 +#define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH_MASK 0x1f00000 +#define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH__SHIFT 0x14 +#define MC_GRUB_TCB_INDEX__INDEX_MASK 0x7f +#define MC_GRUB_TCB_INDEX__INDEX__SHIFT 0x0 +#define MC_GRUB_TCB_INDEX__TCB0_WR_EN_MASK 0x100 +#define MC_GRUB_TCB_INDEX__TCB0_WR_EN__SHIFT 0x8 +#define MC_GRUB_TCB_INDEX__TCB1_WR_EN_MASK 0x200 +#define MC_GRUB_TCB_INDEX__TCB1_WR_EN__SHIFT 0x9 +#define MC_GRUB_TCB_INDEX__RD_EN_MASK 0x400 +#define MC_GRUB_TCB_INDEX__RD_EN__SHIFT 0xa +#define MC_GRUB_TCB_INDEX__TCB_SEL_MASK 0x800 +#define MC_GRUB_TCB_INDEX__TCB_SEL__SHIFT 0xb +#define MC_GRUB_TCB_DATA_LO__DATA_MASK 0xffffffff +#define MC_GRUB_TCB_DATA_LO__DATA__SHIFT 0x0 +#define MC_GRUB_TCB_DATA_HI__DATA_MASK 0xffffffff +#define MC_GRUB_TCB_DATA_HI__DATA__SHIFT 0x0 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x1 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x2 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x10 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x20 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x40 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0xf00 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0xf0000 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 +#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x1fff +#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x1 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x2 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x70 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x80 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0xf00 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x1fff000 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0xff00 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xff000000 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x1 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x2 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x4 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x8 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x10 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0xe0 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0xf00 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x7000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x8000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1fff0000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x1fff +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x2000 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x4000 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x1 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x2 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x4 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x8 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x10 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0xe0 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0xf00 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x7000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x8000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1fff0000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x1fff +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x2000 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x4000 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x1 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x2 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x4 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x8 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x10 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0xe0 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0xf00 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x7000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x8000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1fff0000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x1fff +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x2000 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x4000 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x1 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x2 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x4 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x8 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x10 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0xe0 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0xf00 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x7000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x8000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1fff0000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x1fff +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x2000 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x4000 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x3 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xfc000000 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x1a +#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK_MASK 0xffff +#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0 +#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000 +#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0xff +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xffffffff +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xffffffff +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xffffffff +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xffffffff +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xffffffff +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xffffffff +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xffffffff +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xffffffff +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xffffffff +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x3ffff +#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x1 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x10 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x20 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x40 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0xf00 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1fff0000 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID_MASK 0xf00 +#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID__SHIFT 0x8 +#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK_MASK 0xffff0000 +#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK__SHIFT 0x10 + +#endif /* GMC_8_2_SH_MASK_H */ -- cgit v1.2.3 From 599bd21552e191913f26f581b549ec41d66984be Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:25:48 -0400 Subject: drm/amdgpu: add OSS 2.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the OSS (OS Services) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h | 642 +++++ .../drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h | 2476 ++++++++++++++++++++ 2 files changed, 3118 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h new file mode 100644 index 000000000000..34ab258fd35e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h @@ -0,0 +1,642 @@ +/* + * OSS_2_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_2_0_D_H +#define OSS_2_0_D_H + +#define mmIH_VMID_0_LUT 0xf50 +#define mmIH_VMID_1_LUT 0xf51 +#define mmIH_VMID_2_LUT 0xf52 +#define mmIH_VMID_3_LUT 0xf53 +#define mmIH_VMID_4_LUT 0xf54 +#define mmIH_VMID_5_LUT 0xf55 +#define mmIH_VMID_6_LUT 0xf56 +#define mmIH_VMID_7_LUT 0xf57 +#define mmIH_VMID_8_LUT 0xf58 +#define mmIH_VMID_9_LUT 0xf59 +#define mmIH_VMID_10_LUT 0xf5a +#define mmIH_VMID_11_LUT 0xf5b +#define mmIH_VMID_12_LUT 0xf5c +#define mmIH_VMID_13_LUT 0xf5d +#define mmIH_VMID_14_LUT 0xf5e +#define mmIH_VMID_15_LUT 0xf5f +#define mmIH_RB_CNTL 0xf80 +#define mmIH_RB_BASE 0xf81 +#define mmIH_RB_RPTR 0xf82 +#define mmIH_RB_WPTR 0xf83 +#define mmIH_RB_WPTR_ADDR_HI 0xf84 +#define mmIH_RB_WPTR_ADDR_LO 0xf85 +#define mmIH_CNTL 0xf86 +#define mmIH_LEVEL_STATUS 0xf87 +#define mmIH_STATUS 0xf88 +#define mmIH_PERFMON_CNTL 0xf89 +#define mmIH_PERFCOUNTER0_RESULT 0xf8a +#define mmIH_PERFCOUNTER1_RESULT 0xf8b +#define mmIH_ADVFAULT_CNTL 0xf8c +#define mmSEM_MCIF_CONFIG 0xf90 +#define mmSDMA_CONFIG 0xf91 +#define mmSDMA1_CONFIG 0xf92 +#define mmUVD_CONFIG 0xf93 +#define mmVCE_CONFIG 0xf94 +#define mmACP_CONFIG 0xf95 +#define mmCPG_CONFIG 0xf96 +#define mmCPC1_CONFIG 0xf97 +#define mmCPC2_CONFIG 0xf98 +#define mmSEM_STATUS 0xf99 +#define mmSEM_EDC_CONFIG 0xf9a +#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b +#define mmSEM_MAILBOX 0xf9c +#define mmSEM_MAILBOX_CONTROL 0xf9d +#define mmSEM_CHICKEN_BITS 0xf9e +#define mmSRBM_CNTL 0x390 +#define mmSRBM_GFX_CNTL 0x391 +#define mmSRBM_STATUS2 0x393 +#define mmSRBM_STATUS 0x394 +#define mmSRBM_CAM_INDEX 0x396 +#define mmSRBM_CAM_DATA 0x397 +#define mmSRBM_SOFT_RESET 0x398 +#define mmSRBM_DEBUG_CNTL 0x399 +#define mmSRBM_DEBUG_DATA 0x39a +#define mmSRBM_CHIP_REVISION 0x39b +#define mmCC_SYS_RB_REDUNDANCY 0x39f +#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0 +#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1 +#define mmSRBM_MC_CLKEN_CNTL 0x3b3 +#define mmSRBM_SYS_CLKEN_CNTL 0x3b4 +#define mmSRBM_VCE_CLKEN_CNTL 0x3b5 +#define mmSRBM_UVD_CLKEN_CNTL 0x3b6 +#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7 +#define mmSRBM_SAM_CLKEN_CNTL 0x3b8 +#define mmSRBM_DEBUG 0x3a4 +#define mmSRBM_DEBUG_SNAPSHOT 0x3a5 +#define mmSRBM_READ_ERROR 0x3a6 +#define mmSRBM_INT_CNTL 0x3a8 +#define mmSRBM_INT_STATUS 0x3a9 +#define mmSRBM_INT_ACK 0x3aa +#define mmSRBM_PERFMON_CNTL 0x700 +#define mmSRBM_PERFCOUNTER0_SELECT 0x701 +#define mmSRBM_PERFCOUNTER1_SELECT 0x702 +#define mmSRBM_PERFCOUNTER0_LO 0x703 +#define mmSRBM_PERFCOUNTER0_HI 0x704 +#define mmSRBM_PERFCOUNTER1_LO 0x705 +#define mmSRBM_PERFCOUNTER1_HI 0x706 +#define mmCC_DRM_ID_STRAPS 0x1559 +#define mmCGTT_DRM_CLK_CTRL0 0x1579 +#define ixDH_TEST 0x0 +#define ixKHFS0 0x4 +#define ixKHFS1 0x8 +#define ixKHFS2 0xc +#define ixKHFS3 0x10 +#define ixKSESSION0 0x14 +#define ixKSESSION1 0x18 +#define ixKSESSION2 0x1c +#define ixKSESSION3 0x20 +#define ixKSIG0 0x24 +#define ixKSIG1 0x28 +#define ixKSIG2 0x2c +#define ixKSIG3 0x30 +#define ixEXP0 0x34 +#define ixEXP1 0x38 +#define ixEXP2 0x3c +#define ixEXP3 0x40 +#define ixEXP4 0x44 +#define ixEXP5 0x48 +#define ixEXP6 0x4c +#define ixEXP7 0x50 +#define ixLX0 0x54 +#define ixLX1 0x58 +#define ixLX2 0x5c +#define ixLX3 0x60 +#define ixCLIENT2_K0 0x1b4 +#define ixCLIENT2_K1 0x1b8 +#define ixCLIENT2_K2 0x1bc +#define ixCLIENT2_K3 0x1c0 +#define ixCLIENT2_CK0 0x1c4 +#define ixCLIENT2_CK1 0x1c8 +#define ixCLIENT2_CK2 0x1cc +#define ixCLIENT2_CK3 0x1d0 +#define ixCLIENT2_CD0 0x1d4 +#define ixCLIENT2_CD1 0x1d8 +#define ixCLIENT2_CD2 0x1dc +#define ixCLIENT2_CD3 0x1e0 +#define ixCLIENT2_BM 0x1e4 +#define ixCLIENT2_OFFSET 0x1e8 +#define ixCLIENT2_STATUS 0x1ec +#define ixCLIENT0_K0 0x1f0 +#define ixCLIENT0_K1 0x1f4 +#define ixCLIENT0_K2 0x1f8 +#define ixCLIENT0_K3 0x1fc +#define ixCLIENT0_CK0 0x200 +#define ixCLIENT0_CK1 0x204 +#define ixCLIENT0_CK2 0x208 +#define ixCLIENT0_CK3 0x20c +#define ixCLIENT0_CD0 0x210 +#define ixCLIENT0_CD1 0x214 +#define ixCLIENT0_CD2 0x218 +#define ixCLIENT0_CD3 0x21c +#define ixCLIENT0_BM 0x220 +#define ixCLIENT0_OFFSET 0x224 +#define ixCLIENT0_STATUS 0x228 +#define ixCLIENT1_K0 0x22c +#define ixCLIENT1_K1 0x230 +#define ixCLIENT1_K2 0x234 +#define ixCLIENT1_K3 0x238 +#define ixCLIENT1_CK0 0x23c +#define ixCLIENT1_CK1 0x240 +#define ixCLIENT1_CK2 0x244 +#define ixCLIENT1_CK3 0x248 +#define ixCLIENT1_CD0 0x24c +#define ixCLIENT1_CD1 0x250 +#define ixCLIENT1_CD2 0x254 +#define ixCLIENT1_CD3 0x258 +#define ixCLIENT1_BM 0x25c +#define ixCLIENT1_OFFSET 0x260 +#define ixCLIENT1_PORT_STATUS 0x264 +#define ixKEFUSE0 0x268 +#define ixKEFUSE1 0x26c +#define ixKEFUSE2 0x270 +#define ixKEFUSE3 0x274 +#define ixHFS_SEED0 0x278 +#define ixHFS_SEED1 0x27c +#define ixHFS_SEED2 0x280 +#define ixHFS_SEED3 0x284 +#define ixRINGOSC_MASK 0x288 +#define ixCLIENT0_OFFSET_HI 0x290 +#define ixCLIENT1_OFFSET_HI 0x294 +#define ixCLIENT2_OFFSET_HI 0x298 +#define ixSPU_PORT_STATUS 0x29c +#define ixCLIENT3_OFFSET_HI 0x2a0 +#define ixCLIENT3_K0 0x2a4 +#define ixCLIENT3_K1 0x2a8 +#define ixCLIENT3_K2 0x2ac +#define ixCLIENT3_K3 0x2b0 +#define ixCLIENT3_CK0 0x2b4 +#define ixCLIENT3_CK1 0x2b8 +#define ixCLIENT3_CK2 0x2bc +#define ixCLIENT3_CK3 0x2c0 +#define ixCLIENT3_CD0 0x2c4 +#define ixCLIENT3_CD1 0x2c8 +#define ixCLIENT3_CD2 0x2cc +#define ixCLIENT3_CD3 0x2d0 +#define ixCLIENT3_BM 0x2d4 +#define ixCLIENT3_OFFSET 0x2d8 +#define ixCLIENT3_STATUS 0x2dc +#define mmDC_TEST_DEBUG_INDEX 0x157c +#define mmDC_TEST_DEBUG_DATA 0x157d +#define mmXDMA_SLV_CNTL 0x460 +#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 +#define mmXDMA_SLV_SLS_PITCH 0x462 +#define mmXDMA_SLV_READ_URGENT_CNTL 0x463 +#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 +#define mmXDMA_SLV_WB_RATE_CNTL 0x465 +#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 +#define mmXDMA_SLV_READ_LATENCY_AVE 0x467 +#define mmXDMA_SLV_PCIE_NACK_STATUS 0x468 +#define mmXDMA_SLV_MEM_NACK_STATUS 0x469 +#define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a +#define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b +#define mmXDMA_SLV_FLIP_PENDING 0x46c +#define mmSDMA0_UCODE_ADDR 0x3400 +#define mmSDMA0_UCODE_DATA 0x3401 +#define mmSDMA0_POWER_CNTL 0x3402 +#define mmSDMA0_CLK_CTRL 0x3403 +#define mmSDMA0_CNTL 0x3404 +#define mmSDMA0_CHICKEN_BITS 0x3405 +#define mmSDMA0_TILING_CONFIG 0x3406 +#define mmSDMA0_HASH 0x3407 +#define mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL 0x3408 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 +#define mmSDMA0_RB_RPTR_FETCH 0x340a +#define mmSDMA0_IB_OFFSET_FETCH 0x340b +#define mmSDMA0_PROGRAM 0x340c +#define mmSDMA0_STATUS_REG 0x340d +#define mmSDMA0_STATUS1_REG 0x340e +#define mmSDMA0_PERFMON_CNTL 0x340f +#define mmSDMA0_PERFCOUNTER0_RESULT 0x3410 +#define mmSDMA0_PERFCOUNTER1_RESULT 0x3411 +#define mmSDMA0_F32_CNTL 0x3412 +#define mmSDMA0_FREEZE 0x3413 +#define mmSDMA0_PHASE0_QUANTUM 0x3414 +#define mmSDMA0_PHASE1_QUANTUM 0x3415 +#define mmSDMA_POWER_GATING 0x3416 +#define mmSDMA_PGFSM_CONFIG 0x3417 +#define mmSDMA_PGFSM_WRITE 0x3418 +#define mmSDMA_PGFSM_READ 0x3419 +#define mmSDMA0_EDC_CONFIG 0x341a +#define mmSDMA0_GFX_RB_CNTL 0x3480 +#define mmSDMA0_GFX_RB_BASE 0x3481 +#define mmSDMA0_GFX_RB_BASE_HI 0x3482 +#define mmSDMA0_GFX_RB_RPTR 0x3483 +#define mmSDMA0_GFX_RB_WPTR 0x3484 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489 +#define mmSDMA0_GFX_IB_CNTL 0x348a +#define mmSDMA0_GFX_IB_RPTR 0x348b +#define mmSDMA0_GFX_IB_OFFSET 0x348c +#define mmSDMA0_GFX_IB_BASE_LO 0x348d +#define mmSDMA0_GFX_IB_BASE_HI 0x348e +#define mmSDMA0_GFX_IB_SIZE 0x348f +#define mmSDMA0_GFX_SKIP_CNTL 0x3490 +#define mmSDMA0_GFX_CONTEXT_STATUS 0x3491 +#define mmSDMA0_GFX_CONTEXT_CNTL 0x3493 +#define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7 +#define mmSDMA0_GFX_APE1_CNTL 0x34a8 +#define mmSDMA0_GFX_WATERMARK 0x34aa +#define mmSDMA0_RLC0_RB_CNTL 0x3500 +#define mmSDMA0_RLC0_RB_BASE 0x3501 +#define mmSDMA0_RLC0_RB_BASE_HI 0x3502 +#define mmSDMA0_RLC0_RB_RPTR 0x3503 +#define mmSDMA0_RLC0_RB_WPTR 0x3504 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509 +#define mmSDMA0_RLC0_IB_CNTL 0x350a +#define mmSDMA0_RLC0_IB_RPTR 0x350b +#define mmSDMA0_RLC0_IB_OFFSET 0x350c +#define mmSDMA0_RLC0_IB_BASE_LO 0x350d +#define mmSDMA0_RLC0_IB_BASE_HI 0x350e +#define mmSDMA0_RLC0_IB_SIZE 0x350f +#define mmSDMA0_RLC0_SKIP_CNTL 0x3510 +#define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511 +#define mmSDMA0_RLC0_DOORBELL 0x3512 +#define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527 +#define mmSDMA0_RLC0_APE1_CNTL 0x3528 +#define mmSDMA0_RLC0_DOORBELL_LOG 0x3529 +#define mmSDMA0_RLC0_WATERMARK 0x352a +#define mmSDMA0_RLC1_RB_CNTL 0x3580 +#define mmSDMA0_RLC1_RB_BASE 0x3581 +#define mmSDMA0_RLC1_RB_BASE_HI 0x3582 +#define mmSDMA0_RLC1_RB_RPTR 0x3583 +#define mmSDMA0_RLC1_RB_WPTR 0x3584 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589 +#define mmSDMA0_RLC1_IB_CNTL 0x358a +#define mmSDMA0_RLC1_IB_RPTR 0x358b +#define mmSDMA0_RLC1_IB_OFFSET 0x358c +#define mmSDMA0_RLC1_IB_BASE_LO 0x358d +#define mmSDMA0_RLC1_IB_BASE_HI 0x358e +#define mmSDMA0_RLC1_IB_SIZE 0x358f +#define mmSDMA0_RLC1_SKIP_CNTL 0x3590 +#define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591 +#define mmSDMA0_RLC1_DOORBELL 0x3592 +#define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7 +#define mmSDMA0_RLC1_APE1_CNTL 0x35a8 +#define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9 +#define mmSDMA0_RLC1_WATERMARK 0x35aa +#define mmSDMA1_UCODE_ADDR 0x3600 +#define mmSDMA1_UCODE_DATA 0x3601 +#define mmSDMA1_POWER_CNTL 0x3602 +#define mmSDMA1_CLK_CTRL 0x3603 +#define mmSDMA1_CNTL 0x3604 +#define mmSDMA1_CHICKEN_BITS 0x3605 +#define mmSDMA1_TILING_CONFIG 0x3606 +#define mmSDMA1_HASH 0x3607 +#define mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL 0x3608 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609 +#define mmSDMA1_RB_RPTR_FETCH 0x360a +#define mmSDMA1_IB_OFFSET_FETCH 0x360b +#define mmSDMA1_PROGRAM 0x360c +#define mmSDMA1_STATUS_REG 0x360d +#define mmSDMA1_STATUS1_REG 0x360e +#define mmSDMA1_PERFMON_CNTL 0x360f +#define mmSDMA1_PERFCOUNTER0_RESULT 0x3610 +#define mmSDMA1_PERFCOUNTER1_RESULT 0x3611 +#define mmSDMA1_F32_CNTL 0x3612 +#define mmSDMA1_FREEZE 0x3613 +#define mmSDMA1_PHASE0_QUANTUM 0x3614 +#define mmSDMA1_PHASE1_QUANTUM 0x3615 +#define mmSDMA1_EDC_CONFIG 0x361a +#define mmSDMA1_GFX_RB_CNTL 0x3680 +#define mmSDMA1_GFX_RB_BASE 0x3681 +#define mmSDMA1_GFX_RB_BASE_HI 0x3682 +#define mmSDMA1_GFX_RB_RPTR 0x3683 +#define mmSDMA1_GFX_RB_WPTR 0x3684 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689 +#define mmSDMA1_GFX_IB_CNTL 0x368a +#define mmSDMA1_GFX_IB_RPTR 0x368b +#define mmSDMA1_GFX_IB_OFFSET 0x368c +#define mmSDMA1_GFX_IB_BASE_LO 0x368d +#define mmSDMA1_GFX_IB_BASE_HI 0x368e +#define mmSDMA1_GFX_IB_SIZE 0x368f +#define mmSDMA1_GFX_SKIP_CNTL 0x3690 +#define mmSDMA1_GFX_CONTEXT_STATUS 0x3691 +#define mmSDMA1_GFX_CONTEXT_CNTL 0x3693 +#define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7 +#define mmSDMA1_GFX_APE1_CNTL 0x36a8 +#define mmSDMA1_GFX_WATERMARK 0x36aa +#define mmSDMA1_RLC0_RB_CNTL 0x3700 +#define mmSDMA1_RLC0_RB_BASE 0x3701 +#define mmSDMA1_RLC0_RB_BASE_HI 0x3702 +#define mmSDMA1_RLC0_RB_RPTR 0x3703 +#define mmSDMA1_RLC0_RB_WPTR 0x3704 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709 +#define mmSDMA1_RLC0_IB_CNTL 0x370a +#define mmSDMA1_RLC0_IB_RPTR 0x370b +#define mmSDMA1_RLC0_IB_OFFSET 0x370c +#define mmSDMA1_RLC0_IB_BASE_LO 0x370d +#define mmSDMA1_RLC0_IB_BASE_HI 0x370e +#define mmSDMA1_RLC0_IB_SIZE 0x370f +#define mmSDMA1_RLC0_SKIP_CNTL 0x3710 +#define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711 +#define mmSDMA1_RLC0_DOORBELL 0x3712 +#define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727 +#define mmSDMA1_RLC0_APE1_CNTL 0x3728 +#define mmSDMA1_RLC0_DOORBELL_LOG 0x3729 +#define mmSDMA1_RLC0_WATERMARK 0x372a +#define mmSDMA1_RLC1_RB_CNTL 0x3780 +#define mmSDMA1_RLC1_RB_BASE 0x3781 +#define mmSDMA1_RLC1_RB_BASE_HI 0x3782 +#define mmSDMA1_RLC1_RB_RPTR 0x3783 +#define mmSDMA1_RLC1_RB_WPTR 0x3784 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789 +#define mmSDMA1_RLC1_IB_CNTL 0x378a +#define mmSDMA1_RLC1_IB_RPTR 0x378b +#define mmSDMA1_RLC1_IB_OFFSET 0x378c +#define mmSDMA1_RLC1_IB_BASE_LO 0x378d +#define mmSDMA1_RLC1_IB_BASE_HI 0x378e +#define mmSDMA1_RLC1_IB_SIZE 0x378f +#define mmSDMA1_RLC1_SKIP_CNTL 0x3790 +#define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791 +#define mmSDMA1_RLC1_DOORBELL 0x3792 +#define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7 +#define mmSDMA1_RLC1_APE1_CNTL 0x37a8 +#define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9 +#define mmSDMA1_RLC1_WATERMARK 0x37aa +#define mmXDMA_SLV_CHANNEL_CNTL 0x470 +#define mmSDMA_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 +#define mmSDMA_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 +#define mmSDMA_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 +#define mmSDMA_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 +#define mmSDMA_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 +#define mmSDMA_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 +#define mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 +#define mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 +#define mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 +#define mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 +#define mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 +#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 +#define mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a +#define mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 +#define mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a +#define mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 +#define mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a +#define mmXDMA_MSTR_PIPE_CNTL 0x400 +#define mmMDMA_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 +#define mmMDMA_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 +#define mmMDMA_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 +#define mmMDMA_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 +#define mmMDMA_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 +#define mmMDMA_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 +#define mmXDMA_MSTR_READ_COMMAND 0x401 +#define mmMDMA_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 +#define mmMDMA_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 +#define mmMDMA_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 +#define mmMDMA_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 +#define mmMDMA_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 +#define mmMDMA_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 +#define mmXDMA_MSTR_CHANNEL_DIM 0x402 +#define mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 +#define mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 +#define mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 +#define mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 +#define mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 +#define mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 +#define mmXDMA_MSTR_HEIGHT 0x403 +#define mmMDMA_PIPE0_XDMA_MSTR_HEIGHT 0x403 +#define mmMDMA_PIPE1_XDMA_MSTR_HEIGHT 0x413 +#define mmMDMA_PIPE2_XDMA_MSTR_HEIGHT 0x423 +#define mmMDMA_PIPE3_XDMA_MSTR_HEIGHT 0x433 +#define mmMDMA_PIPE4_XDMA_MSTR_HEIGHT 0x443 +#define mmMDMA_PIPE5_XDMA_MSTR_HEIGHT 0x453 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 +#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 +#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 +#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 +#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 +#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 +#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 +#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 +#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 +#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 +#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 +#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 +#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 +#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 +#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 +#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 +#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 +#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 +#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 +#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 +#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 +#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 +#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 +#define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 +#define mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 +#define mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 +#define mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 +#define mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 +#define mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 +#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 +#define mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 +#define mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 +#define mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 +#define mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 +#define mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 +#define mmXDMA_MSTR_CACHE_PITCH 0x40a +#define mmMDMA_PIPE0_XDMA_MSTR_CACHE_PITCH 0x40a +#define mmMDMA_PIPE1_XDMA_MSTR_CACHE_PITCH 0x41a +#define mmMDMA_PIPE2_XDMA_MSTR_CACHE_PITCH 0x42a +#define mmMDMA_PIPE3_XDMA_MSTR_CACHE_PITCH 0x43a +#define mmMDMA_PIPE4_XDMA_MSTR_CACHE_PITCH 0x44a +#define mmMDMA_PIPE5_XDMA_MSTR_CACHE_PITCH 0x45a +#define mmXDMA_MSTR_CHANNEL_START 0x40b +#define mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b +#define mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b +#define mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b +#define mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b +#define mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b +#define mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b +#define mmXDMA_MSTR_MEM_OVERFLOW_CNTL 0x40c +#define mmMDMA_PIPE0_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x40c +#define mmMDMA_PIPE1_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x41c +#define mmMDMA_PIPE2_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x42c +#define mmMDMA_PIPE3_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x43c +#define mmMDMA_PIPE4_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x44c +#define mmMDMA_PIPE5_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x45c +#define mmXDMA_MSTR_MEM_UNDERFLOW_CNTL 0x40d +#define mmMDMA_PIPE0_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x40d +#define mmMDMA_PIPE1_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x41d +#define mmMDMA_PIPE2_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x42d +#define mmMDMA_PIPE3_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x43d +#define mmMDMA_PIPE4_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x44d +#define mmMDMA_PIPE5_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x45d +#define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e +#define mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e +#define mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e +#define mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e +#define mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e +#define mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e +#define mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e +#define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f +#define mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f +#define mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f +#define mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f +#define mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f +#define mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f +#define mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f +#define mmXDMA_MSTR_CNTL 0x3ec +#define mmXDMA_MSTR_STATUS 0x3ed +#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef +#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 +#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 +#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 +#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 +#define mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG 0x3f4 +#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 +#define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 +#define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 +#define mmHDP_HOST_PATH_CNTL 0xb00 +#define mmHDP_NONSURFACE_BASE 0xb01 +#define mmHDP_NONSURFACE_INFO 0xb02 +#define mmHDP_NONSURFACE_SIZE 0xb03 +#define mmHDP_NONSURF_FLAGS 0xbc9 +#define mmHDP_NONSURF_FLAGS_CLR 0xbca +#define mmHDP_SW_SEMAPHORE 0xbcb +#define mmHDP_DEBUG0 0xbcc +#define mmHDP_DEBUG1 0xbcd +#define mmHDP_LAST_SURFACE_HIT 0xbce +#define mmHDP_TILING_CONFIG 0xbcf +#define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0 +#define mmHDP_OUTSTANDING_REQ 0xbd1 +#define mmHDP_ADDR_CONFIG 0xbd2 +#define mmHDP_MISC_CNTL 0xbd3 +#define mmHDP_MEM_POWER_LS 0xbd4 +#define mmHDP_NONSURFACE_PREFETCH 0xbd5 +#define mmHDP_MEMIO_CNTL 0xbf6 +#define mmHDP_MEMIO_ADDR 0xbf7 +#define mmHDP_MEMIO_STATUS 0xbf8 +#define mmHDP_MEMIO_WR_DATA 0xbf9 +#define mmHDP_MEMIO_RD_DATA 0xbfa +#define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00 +#define mmHDP_XDP_D2H_FLUSH 0xc01 +#define mmHDP_XDP_D2H_BAR_UPDATE 0xc02 +#define mmHDP_XDP_D2H_RSVD_3 0xc03 +#define mmHDP_XDP_D2H_RSVD_4 0xc04 +#define mmHDP_XDP_D2H_RSVD_5 0xc05 +#define mmHDP_XDP_D2H_RSVD_6 0xc06 +#define mmHDP_XDP_D2H_RSVD_7 0xc07 +#define mmHDP_XDP_D2H_RSVD_8 0xc08 +#define mmHDP_XDP_D2H_RSVD_9 0xc09 +#define mmHDP_XDP_D2H_RSVD_10 0xc0a +#define mmHDP_XDP_D2H_RSVD_11 0xc0b +#define mmHDP_XDP_D2H_RSVD_12 0xc0c +#define mmHDP_XDP_D2H_RSVD_13 0xc0d +#define mmHDP_XDP_D2H_RSVD_14 0xc0e +#define mmHDP_XDP_D2H_RSVD_15 0xc0f +#define mmHDP_XDP_D2H_RSVD_16 0xc10 +#define mmHDP_XDP_D2H_RSVD_17 0xc11 +#define mmHDP_XDP_D2H_RSVD_18 0xc12 +#define mmHDP_XDP_D2H_RSVD_19 0xc13 +#define mmHDP_XDP_D2H_RSVD_20 0xc14 +#define mmHDP_XDP_D2H_RSVD_21 0xc15 +#define mmHDP_XDP_D2H_RSVD_22 0xc16 +#define mmHDP_XDP_D2H_RSVD_23 0xc17 +#define mmHDP_XDP_D2H_RSVD_24 0xc18 +#define mmHDP_XDP_D2H_RSVD_25 0xc19 +#define mmHDP_XDP_D2H_RSVD_26 0xc1a +#define mmHDP_XDP_D2H_RSVD_27 0xc1b +#define mmHDP_XDP_D2H_RSVD_28 0xc1c +#define mmHDP_XDP_D2H_RSVD_29 0xc1d +#define mmHDP_XDP_D2H_RSVD_30 0xc1e +#define mmHDP_XDP_D2H_RSVD_31 0xc1f +#define mmHDP_XDP_D2H_RSVD_32 0xc20 +#define mmHDP_XDP_D2H_RSVD_33 0xc21 +#define mmHDP_XDP_D2H_RSVD_34 0xc22 +#define mmHDP_XDP_DIRECT2HDP_LAST 0xc23 +#define mmHDP_XDP_P2P_BAR_CFG 0xc24 +#define mmHDP_XDP_P2P_MBX_OFFSET 0xc25 +#define mmHDP_XDP_P2P_MBX_ADDR0 0xc26 +#define mmHDP_XDP_P2P_MBX_ADDR1 0xc27 +#define mmHDP_XDP_P2P_MBX_ADDR2 0xc28 +#define mmHDP_XDP_P2P_MBX_ADDR3 0xc29 +#define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a +#define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b +#define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c +#define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d +#define mmHDP_XDP_HDP_MC_CFG 0xc2e +#define mmHDP_XDP_HST_CFG 0xc2f +#define mmHDP_XDP_SID_CFG 0xc30 +#define mmHDP_XDP_HDP_IPH_CFG 0xc31 +#define mmHDP_XDP_SRBM_CFG 0xc32 +#define mmHDP_XDP_CGTT_BLK_CTRL 0xc33 +#define mmHDP_XDP_P2P_BAR0 0xc34 +#define mmHDP_XDP_P2P_BAR1 0xc35 +#define mmHDP_XDP_P2P_BAR2 0xc36 +#define mmHDP_XDP_P2P_BAR3 0xc37 +#define mmHDP_XDP_P2P_BAR4 0xc38 +#define mmHDP_XDP_P2P_BAR5 0xc39 +#define mmHDP_XDP_P2P_BAR6 0xc3a +#define mmHDP_XDP_P2P_BAR7 0xc3b +#define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c +#define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d +#define mmHDP_XDP_BUSY_STS 0xc3e +#define mmHDP_XDP_STICKY 0xc3f +#define mmHDP_XDP_CHKN 0xc40 +#define mmHDP_XDP_DBG_ADDR 0xc41 +#define mmHDP_XDP_DBG_DATA 0xc42 +#define mmHDP_XDP_DBG_MASK 0xc43 +#define mmHDP_XDP_BARS_ADDR_39_36 0xc44 + +#endif /* OSS_2_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h new file mode 100644 index 000000000000..99e0b2dced04 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h @@ -0,0 +1,2476 @@ +/* + * OSS_2_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_2_0_SH_MASK_H +#define OSS_2_0_SH_MASK_H + +#define IH_VMID_0_LUT__PASID_MASK 0xffff +#define IH_VMID_0_LUT__PASID__SHIFT 0x0 +#define IH_VMID_1_LUT__PASID_MASK 0xffff +#define IH_VMID_1_LUT__PASID__SHIFT 0x0 +#define IH_VMID_2_LUT__PASID_MASK 0xffff +#define IH_VMID_2_LUT__PASID__SHIFT 0x0 +#define IH_VMID_3_LUT__PASID_MASK 0xffff +#define IH_VMID_3_LUT__PASID__SHIFT 0x0 +#define IH_VMID_4_LUT__PASID_MASK 0xffff +#define IH_VMID_4_LUT__PASID__SHIFT 0x0 +#define IH_VMID_5_LUT__PASID_MASK 0xffff +#define IH_VMID_5_LUT__PASID__SHIFT 0x0 +#define IH_VMID_6_LUT__PASID_MASK 0xffff +#define IH_VMID_6_LUT__PASID__SHIFT 0x0 +#define IH_VMID_7_LUT__PASID_MASK 0xffff +#define IH_VMID_7_LUT__PASID__SHIFT 0x0 +#define IH_VMID_8_LUT__PASID_MASK 0xffff +#define IH_VMID_8_LUT__PASID__SHIFT 0x0 +#define IH_VMID_9_LUT__PASID_MASK 0xffff +#define IH_VMID_9_LUT__PASID__SHIFT 0x0 +#define IH_VMID_10_LUT__PASID_MASK 0xffff +#define IH_VMID_10_LUT__PASID__SHIFT 0x0 +#define IH_VMID_11_LUT__PASID_MASK 0xffff +#define IH_VMID_11_LUT__PASID__SHIFT 0x0 +#define IH_VMID_12_LUT__PASID_MASK 0xffff +#define IH_VMID_12_LUT__PASID__SHIFT 0x0 +#define IH_VMID_13_LUT__PASID_MASK 0xffff +#define IH_VMID_13_LUT__PASID__SHIFT 0x0 +#define IH_VMID_14_LUT__PASID_MASK 0xffff +#define IH_VMID_14_LUT__PASID__SHIFT 0x0 +#define IH_VMID_15_LUT__PASID_MASK 0xffff +#define IH_VMID_15_LUT__PASID__SHIFT 0x0 +#define IH_RB_CNTL__RB_ENABLE_MASK 0x1 +#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define IH_RB_CNTL__RB_SIZE_MASK 0x3e +#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40 +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6 +#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80 +#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00 +#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000 +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define IH_RB_BASE__ADDR_MASK 0xffffffff +#define IH_RB_BASE__ADDR__SHIFT 0x0 +#define IH_RB_RPTR__OFFSET_MASK 0x3fffc +#define IH_RB_RPTR__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1 +#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 +#define IH_RB_WPTR__OFFSET_MASK 0x3fffc +#define IH_RB_WPTR__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff +#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define IH_CNTL__ENABLE_INTR_MASK 0x1 +#define IH_CNTL__ENABLE_INTR__SHIFT 0x0 +#define IH_CNTL__MC_SWAP_MASK 0x6 +#define IH_CNTL__MC_SWAP__SHIFT 0x1 +#define IH_CNTL__MC_TRAN_MASK 0x8 +#define IH_CNTL__MC_TRAN__SHIFT 0x3 +#define IH_CNTL__RPTR_REARM_MASK 0x10 +#define IH_CNTL__RPTR_REARM__SHIFT 0x4 +#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300 +#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8 +#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00 +#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa +#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000 +#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf +#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000 +#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 +#define IH_CNTL__MC_VMID_MASK 0x1e000000 +#define IH_CNTL__MC_VMID__SHIFT 0x19 +#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1 +#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0 +#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4 +#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2 +#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8 +#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3 +#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10 +#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4 +#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20 +#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5 +#define IH_STATUS__IDLE_MASK 0x1 +#define IH_STATUS__IDLE__SHIFT 0x0 +#define IH_STATUS__INPUT_IDLE_MASK 0x2 +#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 +#define IH_STATUS__RB_IDLE_MASK 0x4 +#define IH_STATUS__RB_IDLE__SHIFT 0x2 +#define IH_STATUS__RB_FULL_MASK 0x8 +#define IH_STATUS__RB_FULL__SHIFT 0x3 +#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10 +#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 +#define IH_STATUS__RB_OVERFLOW_MASK 0x20 +#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 +#define IH_STATUS__MC_WR_IDLE_MASK 0x40 +#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 +#define IH_STATUS__MC_WR_STALL_MASK 0x80 +#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 +#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100 +#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 +#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200 +#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 +#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400 +#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa +#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1 +#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 +#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2 +#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 +#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc +#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100 +#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8 +#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200 +#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9 +#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 +#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_ADVFAULT_CNTL__WATERMARK_MASK 0x7 +#define IH_ADVFAULT_CNTL__WATERMARK__SHIFT 0x0 +#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK 0x8 +#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT 0x3 +#define IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK 0x10 +#define IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT 0x4 +#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK 0xff00 +#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT 0x8 +#define IH_ADVFAULT_CNTL__WAIT_TIMER_MASK 0x3fff0000 +#define IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT 0x10 +#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3 +#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 +#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc +#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 +#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00 +#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 +#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 +#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 +#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 +#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 +#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 +#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 +#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 +#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 +#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00 +#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8 +#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000 +#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10 +#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00 +#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8 +#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000 +#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10 +#define ACP_CONFIG__ACP_RDREQ_URG_MASK 0xf00 +#define ACP_CONFIG__ACP_RDREQ_URG__SHIFT 0x8 +#define ACP_CONFIG__ACP_REQ_TRAN_MASK 0x10000 +#define ACP_CONFIG__ACP_REQ_TRAN__SHIFT 0x10 +#define CPG_CONFIG__CPG_RDREQ_URG_MASK 0xf00 +#define CPG_CONFIG__CPG_RDREQ_URG__SHIFT 0x8 +#define CPG_CONFIG__CPG_REQ_TRAN_MASK 0x10000 +#define CPG_CONFIG__CPG_REQ_TRAN__SHIFT 0x10 +#define CPC1_CONFIG__CPC1_RDREQ_URG_MASK 0xf00 +#define CPC1_CONFIG__CPC1_RDREQ_URG__SHIFT 0x8 +#define CPC1_CONFIG__CPC1_REQ_TRAN_MASK 0x10000 +#define CPC1_CONFIG__CPC1_REQ_TRAN__SHIFT 0x10 +#define CPC2_CONFIG__CPC2_RDREQ_URG_MASK 0xf00 +#define CPC2_CONFIG__CPC2_RDREQ_URG__SHIFT 0x8 +#define CPC2_CONFIG__CPC2_REQ_TRAN_MASK 0x10000 +#define CPC2_CONFIG__CPC2_REQ_TRAN__SHIFT 0x10 +#define SEM_STATUS__SEM_IDLE_MASK 0x1 +#define SEM_STATUS__SEM_IDLE__SHIFT 0x0 +#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2 +#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 +#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4 +#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 +#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8 +#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 +#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10 +#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 +#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20 +#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 +#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40 +#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 +#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80 +#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 +#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100 +#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 +#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200 +#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 +#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400 +#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa +#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800 +#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb +#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000 +#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc +#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000 +#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd +#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000 +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf +#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000 +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 +#define SEM_MAILBOX__SIDEPORT_MASK 0xff +#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0 +#define SEM_MAILBOX__HOSTPORT_MASK 0xff00 +#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8 +#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1 +#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 +#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2 +#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 +#define SRBM_CNTL__READ_TIMEOUT_MASK 0x1fff +#define SRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000 +#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10 +#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000 +#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11 +#define SRBM_GFX_CNTL__PIPEID_MASK 0x3 +#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0 +#define SRBM_GFX_CNTL__MEID_MASK 0xc +#define SRBM_GFX_CNTL__MEID__SHIFT 0x2 +#define SRBM_GFX_CNTL__VMID_MASK 0xf0 +#define SRBM_GFX_CNTL__VMID__SHIFT 0x4 +#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700 +#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 +#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1 +#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0 +#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2 +#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1 +#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4 +#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2 +#define SRBM_STATUS2__VCE_RQ_PENDING_MASK 0x8 +#define SRBM_STATUS2__VCE_RQ_PENDING__SHIFT 0x3 +#define SRBM_STATUS2__XSP_BUSY_MASK 0x10 +#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x4 +#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20 +#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5 +#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40 +#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6 +#define SRBM_STATUS2__VCE_BUSY_MASK 0x80 +#define SRBM_STATUS2__VCE_BUSY__SHIFT 0x7 +#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100 +#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8 +#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200 +#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9 +#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2 +#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1 +#define SRBM_STATUS__SAM_RQ_PENDING_MASK 0x4 +#define SRBM_STATUS__SAM_RQ_PENDING__SHIFT 0x2 +#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8 +#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3 +#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10 +#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4 +#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20 +#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5 +#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40 +#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6 +#define SRBM_STATUS__IO_EXTERN_SIGNAL_MASK 0x80 +#define SRBM_STATUS__IO_EXTERN_SIGNAL__SHIFT 0x7 +#define SRBM_STATUS__VMC_BUSY_MASK 0x100 +#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8 +#define SRBM_STATUS__MCB_BUSY_MASK 0x200 +#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9 +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400 +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa +#define SRBM_STATUS__MCC_BUSY_MASK 0x800 +#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb +#define SRBM_STATUS__MCD_BUSY_MASK 0x1000 +#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc +#define SRBM_STATUS__SEM_BUSY_MASK 0x4000 +#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe +#define SRBM_STATUS__ACP_BUSY_MASK 0x10000 +#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10 +#define SRBM_STATUS__IH_BUSY_MASK 0x20000 +#define SRBM_STATUS__IH_BUSY__SHIFT 0x11 +#define SRBM_STATUS__UVD_BUSY_MASK 0x80000 +#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13 +#define SRBM_STATUS__SAM_BUSY_MASK 0x100000 +#define SRBM_STATUS__SAM_BUSY__SHIFT 0x14 +#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000 +#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d +#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x7 +#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff +#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 +#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2 +#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1 +#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL_MASK 0x10 +#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL__SHIFT 0x4 +#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20 +#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6 +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100 +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8 +#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200 +#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9 +#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400 +#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa +#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800 +#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb +#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000 +#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc +#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000 +#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe +#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000 +#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf +#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000 +#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10 +#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000 +#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11 +#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000 +#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12 +#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x80000 +#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x13 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14 +#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000 +#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15 +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000 +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16 +#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x800000 +#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x17 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK 0x1000000 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE__SHIFT 0x18 +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000 +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19 +#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000 +#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a +#define SRBM_SOFT_RESET__SOFT_RESET_SAM_MASK 0x8000000 +#define SRBM_SOFT_RESET__SOFT_RESET_SAM__SHIFT 0x1b +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0 +#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff +#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0 +#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff +#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 +#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 +#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 +#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1 +#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0 +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2 +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1 +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4 +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2 +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10 +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4 +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20 +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5 +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40 +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6 +#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80 +#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7 +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100 +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8 +#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200 +#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9 +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1 +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0 +#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK 0x2 +#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY__SHIFT 0x1 +#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4 +#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2 +#define SRBM_DEBUG_SNAPSHOT__SAM_RDY_MASK 0x8 +#define SRBM_DEBUG_SNAPSHOT__SAM_RDY__SHIFT 0x3 +#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10 +#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4 +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20 +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5 +#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40 +#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6 +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80 +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7 +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100 +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8 +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200 +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9 +#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x400 +#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0xa +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800 +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb +#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x1000 +#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0xc +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000 +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000 +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000 +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000 +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10 +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000 +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11 +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000 +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12 +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000 +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13 +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000 +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14 +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000 +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15 +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000 +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16 +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000 +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17 +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000 +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18 +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000 +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19 +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000 +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000 +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000 +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c +#define SRBM_DEBUG_SNAPSHOT__VCE_RDY_MASK 0x20000000 +#define SRBM_DEBUG_SNAPSHOT__VCE_RDY__SHIFT 0x1d +#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc +#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define SRBM_READ_ERROR__READ_REQUESTER_VCE_MASK 0x100000 +#define SRBM_READ_ERROR__READ_REQUESTER_VCE__SHIFT 0x14 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15 +#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000 +#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16 +#define SRBM_READ_ERROR__READ_REQUESTER_SAM_MASK 0x800000 +#define SRBM_READ_ERROR__READ_REQUESTER_SAM__SHIFT 0x17 +#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000 +#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18 +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000 +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19 +#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000 +#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a +#define SRBM_READ_ERROR__READ_REQUESTER_ACP_MASK 0x8000000 +#define SRBM_READ_ERROR__READ_REQUESTER_ACP__SHIFT 0x1b +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c +#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000 +#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d +#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 +#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1 +#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0 +#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1 +#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0 +#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1 +#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0 +#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf +#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0 +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0 +#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 +#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c +#define DH_TEST__DH_TEST_MASK 0x1 +#define DH_TEST__DH_TEST__SHIFT 0x0 +#define KHFS0__RESERVED_MASK 0xffffffff +#define KHFS0__RESERVED__SHIFT 0x0 +#define KHFS1__RESERVED_MASK 0xffffffff +#define KHFS1__RESERVED__SHIFT 0x0 +#define KHFS2__RESERVED_MASK 0xffffffff +#define KHFS2__RESERVED__SHIFT 0x0 +#define KHFS3__RESERVED_MASK 0xffffffff +#define KHFS3__RESERVED__SHIFT 0x0 +#define KSESSION0__RESERVED_MASK 0xffffffff +#define KSESSION0__RESERVED__SHIFT 0x0 +#define KSESSION1__RESERVED_MASK 0xffffffff +#define KSESSION1__RESERVED__SHIFT 0x0 +#define KSESSION2__RESERVED_MASK 0xffffffff +#define KSESSION2__RESERVED__SHIFT 0x0 +#define KSESSION3__RESERVED_MASK 0xffffffff +#define KSESSION3__RESERVED__SHIFT 0x0 +#define KSIG0__RESERVED_MASK 0xffffffff +#define KSIG0__RESERVED__SHIFT 0x0 +#define KSIG1__RESERVED_MASK 0xffffffff +#define KSIG1__RESERVED__SHIFT 0x0 +#define KSIG2__RESERVED_MASK 0xffffffff +#define KSIG2__RESERVED__SHIFT 0x0 +#define KSIG3__RESERVED_MASK 0xffffffff +#define KSIG3__RESERVED__SHIFT 0x0 +#define EXP0__RESERVED_MASK 0xffffffff +#define EXP0__RESERVED__SHIFT 0x0 +#define EXP1__RESERVED_MASK 0xffffffff +#define EXP1__RESERVED__SHIFT 0x0 +#define EXP2__RESERVED_MASK 0xffffffff +#define EXP2__RESERVED__SHIFT 0x0 +#define EXP3__RESERVED_MASK 0xffffffff +#define EXP3__RESERVED__SHIFT 0x0 +#define EXP4__RESERVED_MASK 0xffffffff +#define EXP4__RESERVED__SHIFT 0x0 +#define EXP5__RESERVED_MASK 0xffffffff +#define EXP5__RESERVED__SHIFT 0x0 +#define EXP6__RESERVED_MASK 0xffffffff +#define EXP6__RESERVED__SHIFT 0x0 +#define EXP7__RESERVED_MASK 0xffffffff +#define EXP7__RESERVED__SHIFT 0x0 +#define LX0__RESERVED_MASK 0xffffffff +#define LX0__RESERVED__SHIFT 0x0 +#define LX1__RESERVED_MASK 0xffffffff +#define LX1__RESERVED__SHIFT 0x0 +#define LX2__RESERVED_MASK 0xffffffff +#define LX2__RESERVED__SHIFT 0x0 +#define LX3__RESERVED_MASK 0xffffffff +#define LX3__RESERVED__SHIFT 0x0 +#define CLIENT2_K0__RESERVED_MASK 0xffffffff +#define CLIENT2_K0__RESERVED__SHIFT 0x0 +#define CLIENT2_K1__RESERVED_MASK 0xffffffff +#define CLIENT2_K1__RESERVED__SHIFT 0x0 +#define CLIENT2_K2__RESERVED_MASK 0xffffffff +#define CLIENT2_K2__RESERVED__SHIFT 0x0 +#define CLIENT2_K3__RESERVED_MASK 0xffffffff +#define CLIENT2_K3__RESERVED__SHIFT 0x0 +#define CLIENT2_CK0__RESERVED_MASK 0xffffffff +#define CLIENT2_CK0__RESERVED__SHIFT 0x0 +#define CLIENT2_CK1__RESERVED_MASK 0xffffffff +#define CLIENT2_CK1__RESERVED__SHIFT 0x0 +#define CLIENT2_CK2__RESERVED_MASK 0xffffffff +#define CLIENT2_CK2__RESERVED__SHIFT 0x0 +#define CLIENT2_CK3__RESERVED_MASK 0xffffffff +#define CLIENT2_CK3__RESERVED__SHIFT 0x0 +#define CLIENT2_CD0__RESERVED_MASK 0xffffffff +#define CLIENT2_CD0__RESERVED__SHIFT 0x0 +#define CLIENT2_CD1__RESERVED_MASK 0xffffffff +#define CLIENT2_CD1__RESERVED__SHIFT 0x0 +#define CLIENT2_CD2__RESERVED_MASK 0xffffffff +#define CLIENT2_CD2__RESERVED__SHIFT 0x0 +#define CLIENT2_CD3__RESERVED_MASK 0xffffffff +#define CLIENT2_CD3__RESERVED__SHIFT 0x0 +#define CLIENT2_BM__RESERVED_MASK 0xffffffff +#define CLIENT2_BM__RESERVED__SHIFT 0x0 +#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffff +#define CLIENT2_OFFSET__RESERVED__SHIFT 0x0 +#define CLIENT2_STATUS__RESERVED_MASK 0xffffffff +#define CLIENT2_STATUS__RESERVED__SHIFT 0x0 +#define CLIENT0_K0__RESERVED_MASK 0xffffffff +#define CLIENT0_K0__RESERVED__SHIFT 0x0 +#define CLIENT0_K1__RESERVED_MASK 0xffffffff +#define CLIENT0_K1__RESERVED__SHIFT 0x0 +#define CLIENT0_K2__RESERVED_MASK 0xffffffff +#define CLIENT0_K2__RESERVED__SHIFT 0x0 +#define CLIENT0_K3__RESERVED_MASK 0xffffffff +#define CLIENT0_K3__RESERVED__SHIFT 0x0 +#define CLIENT0_CK0__RESERVED_MASK 0xffffffff +#define CLIENT0_CK0__RESERVED__SHIFT 0x0 +#define CLIENT0_CK1__RESERVED_MASK 0xffffffff +#define CLIENT0_CK1__RESERVED__SHIFT 0x0 +#define CLIENT0_CK2__RESERVED_MASK 0xffffffff +#define CLIENT0_CK2__RESERVED__SHIFT 0x0 +#define CLIENT0_CK3__RESERVED_MASK 0xffffffff +#define CLIENT0_CK3__RESERVED__SHIFT 0x0 +#define CLIENT0_CD0__RESERVED_MASK 0xffffffff +#define CLIENT0_CD0__RESERVED__SHIFT 0x0 +#define CLIENT0_CD1__RESERVED_MASK 0xffffffff +#define CLIENT0_CD1__RESERVED__SHIFT 0x0 +#define CLIENT0_CD2__RESERVED_MASK 0xffffffff +#define CLIENT0_CD2__RESERVED__SHIFT 0x0 +#define CLIENT0_CD3__RESERVED_MASK 0xffffffff +#define CLIENT0_CD3__RESERVED__SHIFT 0x0 +#define CLIENT0_BM__RESERVED_MASK 0xffffffff +#define CLIENT0_BM__RESERVED__SHIFT 0x0 +#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffff +#define CLIENT0_OFFSET__RESERVED__SHIFT 0x0 +#define CLIENT0_STATUS__RESERVED_MASK 0xffffffff +#define CLIENT0_STATUS__RESERVED__SHIFT 0x0 +#define CLIENT1_K0__RESERVED_MASK 0xffffffff +#define CLIENT1_K0__RESERVED__SHIFT 0x0 +#define CLIENT1_K1__RESERVED_MASK 0xffffffff +#define CLIENT1_K1__RESERVED__SHIFT 0x0 +#define CLIENT1_K2__RESERVED_MASK 0xffffffff +#define CLIENT1_K2__RESERVED__SHIFT 0x0 +#define CLIENT1_K3__RESERVED_MASK 0xffffffff +#define CLIENT1_K3__RESERVED__SHIFT 0x0 +#define CLIENT1_CK0__RESERVED_MASK 0xffffffff +#define CLIENT1_CK0__RESERVED__SHIFT 0x0 +#define CLIENT1_CK1__RESERVED_MASK 0xffffffff +#define CLIENT1_CK1__RESERVED__SHIFT 0x0 +#define CLIENT1_CK2__RESERVED_MASK 0xffffffff +#define CLIENT1_CK2__RESERVED__SHIFT 0x0 +#define CLIENT1_CK3__RESERVED_MASK 0xffffffff +#define CLIENT1_CK3__RESERVED__SHIFT 0x0 +#define CLIENT1_CD0__RESERVED_MASK 0xffffffff +#define CLIENT1_CD0__RESERVED__SHIFT 0x0 +#define CLIENT1_CD1__RESERVED_MASK 0xffffffff +#define CLIENT1_CD1__RESERVED__SHIFT 0x0 +#define CLIENT1_CD2__RESERVED_MASK 0xffffffff +#define CLIENT1_CD2__RESERVED__SHIFT 0x0 +#define CLIENT1_CD3__RESERVED_MASK 0xffffffff +#define CLIENT1_CD3__RESERVED__SHIFT 0x0 +#define CLIENT1_BM__RESERVED_MASK 0xffffffff +#define CLIENT1_BM__RESERVED__SHIFT 0x0 +#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffff +#define CLIENT1_OFFSET__RESERVED__SHIFT 0x0 +#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffff +#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x0 +#define KEFUSE0__RESERVED_MASK 0xffffffff +#define KEFUSE0__RESERVED__SHIFT 0x0 +#define KEFUSE1__RESERVED_MASK 0xffffffff +#define KEFUSE1__RESERVED__SHIFT 0x0 +#define KEFUSE2__RESERVED_MASK 0xffffffff +#define KEFUSE2__RESERVED__SHIFT 0x0 +#define KEFUSE3__RESERVED_MASK 0xffffffff +#define KEFUSE3__RESERVED__SHIFT 0x0 +#define HFS_SEED0__RESERVED_MASK 0xffffffff +#define HFS_SEED0__RESERVED__SHIFT 0x0 +#define HFS_SEED1__RESERVED_MASK 0xffffffff +#define HFS_SEED1__RESERVED__SHIFT 0x0 +#define HFS_SEED2__RESERVED_MASK 0xffffffff +#define HFS_SEED2__RESERVED__SHIFT 0x0 +#define HFS_SEED3__RESERVED_MASK 0xffffffff +#define HFS_SEED3__RESERVED__SHIFT 0x0 +#define RINGOSC_MASK__MASK_MASK 0xffff +#define RINGOSC_MASK__MASK__SHIFT 0x0 +#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffff +#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x0 +#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffff +#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x0 +#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffff +#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x0 +#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffff +#define SPU_PORT_STATUS__RESERVED__SHIFT 0x0 +#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffff +#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x0 +#define CLIENT3_K0__RESERVED_MASK 0xffffffff +#define CLIENT3_K0__RESERVED__SHIFT 0x0 +#define CLIENT3_K1__RESERVED_MASK 0xffffffff +#define CLIENT3_K1__RESERVED__SHIFT 0x0 +#define CLIENT3_K2__RESERVED_MASK 0xffffffff +#define CLIENT3_K2__RESERVED__SHIFT 0x0 +#define CLIENT3_K3__RESERVED_MASK 0xffffffff +#define CLIENT3_K3__RESERVED__SHIFT 0x0 +#define CLIENT3_CK0__RESERVED_MASK 0xffffffff +#define CLIENT3_CK0__RESERVED__SHIFT 0x0 +#define CLIENT3_CK1__RESERVED_MASK 0xffffffff +#define CLIENT3_CK1__RESERVED__SHIFT 0x0 +#define CLIENT3_CK2__RESERVED_MASK 0xffffffff +#define CLIENT3_CK2__RESERVED__SHIFT 0x0 +#define CLIENT3_CK3__RESERVED_MASK 0xffffffff +#define CLIENT3_CK3__RESERVED__SHIFT 0x0 +#define CLIENT3_CD0__RESERVED_MASK 0xffffffff +#define CLIENT3_CD0__RESERVED__SHIFT 0x0 +#define CLIENT3_CD1__RESERVED_MASK 0xffffffff +#define CLIENT3_CD1__RESERVED__SHIFT 0x0 +#define CLIENT3_CD2__RESERVED_MASK 0xffffffff +#define CLIENT3_CD2__RESERVED__SHIFT 0x0 +#define CLIENT3_CD3__RESERVED_MASK 0xffffffff +#define CLIENT3_CD3__RESERVED__SHIFT 0x0 +#define CLIENT3_BM__RESERVED_MASK 0xffffffff +#define CLIENT3_BM__RESERVED__SHIFT 0x0 +#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffff +#define CLIENT3_OFFSET__RESERVED__SHIFT 0x0 +#define CLIENT3_STATUS__RESERVED_MASK 0xffffffff +#define CLIENT3_STATUS__RESERVED__SHIFT 0x0 +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0xff +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffff +#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x0 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0 +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200 +#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9 +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400 +#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa +#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000 +#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000 +#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000 +#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13 +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000 +#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14 +#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000 +#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000 +#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000 +#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000 +#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000 +#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000 +#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000 +#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000 +#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000 +#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000 +#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000 +#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff +#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0 +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1 +#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0 +#define SDMA0_UCODE_ADDR__VALUE_MASK 0x7ff +#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff +#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf +#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1 +#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK 0x2 +#define SDMA0_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT 0x1 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8 +#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 +#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 +#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 +#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7 +#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0 +#define SDMA0_HASH__BANK_BITS_MASK 0x70 +#define SDMA0_HASH__BANK_BITS__SHIFT 0x4 +#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700 +#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 +#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000 +#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc +#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK 0xffff +#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc +#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc +#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff +#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_STATUS_REG__IDLE_MASK 0x1 +#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2 +#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4 +#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8 +#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10 +#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20 +#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40 +#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80 +#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100 +#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200 +#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400 +#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000 +#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000 +#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000 +#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 +#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000 +#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000 +#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 +#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 +#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000 +#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 +#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2 +#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20 +#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40 +#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 +#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 +#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000 +#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000 +#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc +#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 +#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 +#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_F32_CNTL__HALT_MASK 0x1 +#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA0_F32_CNTL__STEP_MASK 0x2 +#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA0_FREEZE__FREEZE_MASK 0x10 +#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA0_FREEZE__FROZEN_MASK 0x20 +#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf +#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf +#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1 +#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2 +#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1 +#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4 +#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2 +#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30 +#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 +#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40 +#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6 +#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80 +#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7 +#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00 +#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8 +#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000 +#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14 +#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff +#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 +#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200 +#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400 +#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800 +#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000 +#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000 +#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 +#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff +#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff +#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 +#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 +#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_UCODE_ADDR__VALUE_MASK 0x7ff +#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff +#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf +#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1 +#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK 0x2 +#define SDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT 0x1 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8 +#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 +#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 +#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 +#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7 +#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0 +#define SDMA1_HASH__BANK_BITS_MASK 0x70 +#define SDMA1_HASH__BANK_BITS__SHIFT 0x4 +#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700 +#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 +#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000 +#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc +#define SDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK 0xffff +#define SDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc +#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc +#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff +#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_STATUS_REG__IDLE_MASK 0x1 +#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2 +#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4 +#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8 +#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10 +#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20 +#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40 +#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80 +#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100 +#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200 +#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400 +#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000 +#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000 +#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000 +#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 +#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000 +#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000 +#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 +#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 +#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000 +#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 +#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 +#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20 +#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40 +#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 +#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 +#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000 +#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000 +#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc +#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 +#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 +#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_F32_CNTL__HALT_MASK 0x1 +#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA1_F32_CNTL__STEP_MASK 0x2 +#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA1_FREEZE__FREEZE_MASK 0x10 +#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA1_FREEZE__FROZEN_MASK 0x20 +#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf +#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf +#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 +#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000 +#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18 +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff +#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0 +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff +#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000 +#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000 +#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000 +#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000 +#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10 +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff +#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff +#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff +#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0 +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff +#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 +#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff +#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0 +#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff +#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0 +#define XDMA_MSTR_CACHE_PITCH__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff +#define XDMA_MSTR_CACHE_PITCH__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0 +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0 +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000 +#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10 +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_MASK 0xffff +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT__SHIFT 0x0 +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD_MASK 0x3fff0000 +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD__SHIFT 0x10 +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_BP_ENABLE_MASK 0x40000000 +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_BP_ENABLE__SHIFT 0x1e +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE_MASK 0x80000000 +#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE__SHIFT 0x1f +#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_COUNT_MASK 0xffff +#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_COUNT__SHIFT 0x0 +#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_THRESHOLD_MASK 0x3fff0000 +#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_THRESHOLD__SHIFT 0x10 +#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_DETECT_ENABLE_MASK 0x80000000 +#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_DETECT_ENABLE__SHIFT 0x1f +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000 +#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000 +#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f +#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10 +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12 +#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN_MASK 0x80000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN__SHIFT 0x13 +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14 +#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000 +#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15 +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff +#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0 +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10 +#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000 +#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000 +#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0 +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff +#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0 +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff +#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000 +#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000 +#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10 +#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_LIMIT_MASK 0xffff +#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_LIMIT__SHIFT 0x0 +#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_TIMER_MASK 0xffff0000 +#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_TIMER__SHIFT 0x10 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000 +#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000 +#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00 +#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8 +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7 +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0 +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8 +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3 +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600 +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000 +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16 +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000 +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17 +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000 +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000 +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000 +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f +#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff +#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0 +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1 +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0 +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1 +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60 +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5 +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380 +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd +#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000 +#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11 +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000 +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18 +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000 +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000 +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000 +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0 +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800 +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1 +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 +#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 +#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0 +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 +#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe +#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1 +#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30 +#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4 +#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0 +#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6 +#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700 +#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8 +#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800 +#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb +#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000 +#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7 +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0 +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18 +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3 +#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff +#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 +#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00 +#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 +#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1 +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 +#define HDP_MISC_CNTL__VM_ID_MASK 0x1e +#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1 +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20 +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 +#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40 +#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780 +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000 +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000 +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000 +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13 +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000 +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14 +#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000 +#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 +#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1 +#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 +#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e +#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1 +#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80 +#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b +#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1 +#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 +#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2 +#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 +#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c +#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000 +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000 +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 +#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18 +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f +#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 +#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff +#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 +#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff +#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 +#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000 +#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 +#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff +#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 +#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00 +#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 +#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000 +#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 +#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000 +#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 +#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff +#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0 +#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10 +#define HDP_XDP_DBG_DATA__STS_MASK 0xffff +#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0 +#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10 +#define HDP_XDP_DBG_MASK__STS_MASK 0xffff +#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0 +#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10 +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000 +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c + +#endif /* OSS_2_0_SH_MASK_H */ -- cgit v1.2.3 From 3f2ec6f51dfa089179ddf37115f9e25aadd31a56 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:26:30 -0400 Subject: drm/amdgpu: add OSS 2.4 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the OSS (OS Services) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h | 471 ++++ .../drm/amd/include/asic_reg/oss/oss_2_4_enum.h | 1340 +++++++++++ .../drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h | 2544 ++++++++++++++++++++ 3 files changed, 4355 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h new file mode 100644 index 000000000000..ca833d3cc128 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h @@ -0,0 +1,471 @@ +/* + * OSS_2_4 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_2_4_D_H +#define OSS_2_4_D_H + +#define mmIH_VMID_0_LUT 0xe00 +#define mmIH_VMID_1_LUT 0xe01 +#define mmIH_VMID_2_LUT 0xe02 +#define mmIH_VMID_3_LUT 0xe03 +#define mmIH_VMID_4_LUT 0xe04 +#define mmIH_VMID_5_LUT 0xe05 +#define mmIH_VMID_6_LUT 0xe06 +#define mmIH_VMID_7_LUT 0xe07 +#define mmIH_VMID_8_LUT 0xe08 +#define mmIH_VMID_9_LUT 0xe09 +#define mmIH_VMID_10_LUT 0xe0a +#define mmIH_VMID_11_LUT 0xe0b +#define mmIH_VMID_12_LUT 0xe0c +#define mmIH_VMID_13_LUT 0xe0d +#define mmIH_VMID_14_LUT 0xe0e +#define mmIH_VMID_15_LUT 0xe0f +#define mmIH_RB_CNTL 0xe30 +#define mmIH_RB_BASE 0xe31 +#define mmIH_RB_RPTR 0xe32 +#define mmIH_RB_WPTR 0xe33 +#define mmIH_RB_WPTR_ADDR_HI 0xe34 +#define mmIH_RB_WPTR_ADDR_LO 0xe35 +#define mmIH_CNTL 0xe36 +#define mmIH_LEVEL_STATUS 0xe37 +#define mmIH_STATUS 0xe38 +#define mmIH_PERFMON_CNTL 0xe39 +#define mmIH_PERFCOUNTER0_RESULT 0xe3a +#define mmIH_PERFCOUNTER1_RESULT 0xe3b +#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d +#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e +#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f +#define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40 +#define mmIH_DSM_MATCH_DATA_CONTROL 0xe41 +#define mmIH_VERSION 0xe42 +#define mmSEM_MCIF_CONFIG 0xf90 +#define mmSDMA_CONFIG 0xf91 +#define mmSDMA1_CONFIG 0xf92 +#define mmUVD_CONFIG 0xf93 +#define mmVCE_CONFIG 0xf94 +#define mmACP_CONFIG 0xf95 +#define mmCPG_CONFIG 0xf96 +#define mmCPC1_CONFIG 0xf97 +#define mmCPC2_CONFIG 0xf98 +#define mmSEM_STATUS 0xf99 +#define mmSEM_EDC_CONFIG 0xf9a +#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b +#define mmSEM_MAILBOX 0xf9c +#define mmSEM_MAILBOX_CONTROL 0xf9d +#define mmSEM_CHICKEN_BITS 0xf9e +#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f +#define mmSRBM_CNTL 0x390 +#define mmSRBM_GFX_CNTL 0x391 +#define mmSRBM_READ_CNTL 0x392 +#define mmSRBM_STATUS2 0x393 +#define mmSRBM_STATUS 0x394 +#define mmSRBM_STATUS3 0x395 +#define mmSRBM_SOFT_RESET 0x398 +#define mmSRBM_DEBUG_CNTL 0x399 +#define mmSRBM_DEBUG_DATA 0x39a +#define mmSRBM_CHIP_REVISION 0x39b +#define mmCC_SYS_RB_REDUNDANCY 0x39f +#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0 +#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1 +#define mmSRBM_MC_CLKEN_CNTL 0x3b3 +#define mmSRBM_SYS_CLKEN_CNTL 0x3b4 +#define mmSRBM_VCE_CLKEN_CNTL 0x3b5 +#define mmSRBM_UVD_CLKEN_CNTL 0x3b6 +#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7 +#define mmSRBM_SAM_CLKEN_CNTL 0x3b8 +#define mmSRBM_ISP_CLKEN_CNTL 0x3b9 +#define mmSRBM_DEBUG 0x3a4 +#define mmSRBM_DEBUG_SNAPSHOT 0x3a5 +#define mmSRBM_DEBUG_SNAPSHOT2 0x3ad +#define mmSRBM_READ_ERROR 0x3a6 +#define mmSRBM_READ_ERROR2 0x3ae +#define mmSRBM_INT_CNTL 0x3a8 +#define mmSRBM_INT_STATUS 0x3a9 +#define mmSRBM_INT_ACK 0x3aa +#define mmSRBM_FIREWALL_ERROR_SRC 0x3ab +#define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac +#define mmSRBM_DSM_TRIG_CNTL0 0x3af +#define mmSRBM_DSM_TRIG_CNTL1 0x3b0 +#define mmSRBM_DSM_TRIG_MASK0 0x3b1 +#define mmSRBM_DSM_TRIG_MASK1 0x3b2 +#define mmSRBM_PERFMON_CNTL 0x7c00 +#define mmSRBM_PERFCOUNTER0_SELECT 0x7c01 +#define mmSRBM_PERFCOUNTER1_SELECT 0x7c02 +#define mmSRBM_PERFCOUNTER0_LO 0x7c03 +#define mmSRBM_PERFCOUNTER0_HI 0x7c04 +#define mmSRBM_PERFCOUNTER1_LO 0x7c05 +#define mmSRBM_PERFCOUNTER1_HI 0x7c06 +#define mmSRBM_CAM_INDEX 0xfe34 +#define mmSRBM_CAM_DATA 0xfe35 +#define mmSRBM_MC_DOMAIN_ADDR0 0xfa00 +#define mmSRBM_MC_DOMAIN_ADDR1 0xfa01 +#define mmSRBM_MC_DOMAIN_ADDR2 0xfa02 +#define mmSRBM_MC_DOMAIN_ADDR3 0xfa03 +#define mmSRBM_MC_DOMAIN_ADDR4 0xfa04 +#define mmSRBM_MC_DOMAIN_ADDR5 0xfa05 +#define mmSRBM_MC_DOMAIN_ADDR6 0xfa06 +#define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08 +#define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09 +#define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a +#define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b +#define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c +#define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d +#define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e +#define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10 +#define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11 +#define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12 +#define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13 +#define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14 +#define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15 +#define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16 +#define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18 +#define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19 +#define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a +#define mmSRBM_SAM_DOMAIN_ADDR0 0xfa1c +#define mmSRBM_SAM_DOMAIN_ADDR1 0xfa1d +#define mmSRBM_SAM_DOMAIN_ADDR2 0xfa1e +#define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20 +#define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21 +#define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22 +#define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c +#define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d +#define mmSRBM_GFX_CNTL_SELECT 0xfa2e +#define mmSRBM_GFX_CNTL_DATA 0xfa2f +#define mmSRBM_VF_ENABLE 0xfa30 +#define mmSRBM_VIRT_CNTL 0xfa31 +#define mmSRBM_VIRT_RESET_REQ 0xfa32 +#define mmSDMA0_UCODE_ADDR 0x3400 +#define mmSDMA0_UCODE_DATA 0x3401 +#define mmSDMA0_POWER_CNTL 0x3402 +#define mmSDMA0_CLK_CTRL 0x3403 +#define mmSDMA0_CNTL 0x3404 +#define mmSDMA0_CHICKEN_BITS 0x3405 +#define mmSDMA0_TILING_CONFIG 0x3406 +#define mmSDMA0_HASH 0x3407 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 +#define mmSDMA0_RB_RPTR_FETCH 0x340a +#define mmSDMA0_IB_OFFSET_FETCH 0x340b +#define mmSDMA0_PROGRAM 0x340c +#define mmSDMA0_STATUS_REG 0x340d +#define mmSDMA0_STATUS1_REG 0x340e +#define mmSDMA0_PERFMON_CNTL 0x9000 +#define mmSDMA0_PERFCOUNTER0_RESULT 0x9001 +#define mmSDMA0_PERFCOUNTER1_RESULT 0x9002 +#define mmSDMA0_F32_CNTL 0x3412 +#define mmSDMA0_FREEZE 0x3413 +#define mmSDMA0_PHASE0_QUANTUM 0x3414 +#define mmSDMA0_PHASE1_QUANTUM 0x3415 +#define mmSDMA_POWER_GATING 0x3416 +#define mmSDMA_PGFSM_CONFIG 0x3417 +#define mmSDMA_PGFSM_WRITE 0x3418 +#define mmSDMA_PGFSM_READ 0x3419 +#define mmSDMA0_EDC_CONFIG 0x341a +#define mmSDMA0_BA_THRESHOLD 0x341b +#define mmSDMA0_ID 0x341c +#define mmSDMA0_VERSION 0x341d +#define mmSDMA0_STATUS2_REG 0x341e +#define mmSDMA0_GFX_RB_CNTL 0x3480 +#define mmSDMA0_GFX_RB_BASE 0x3481 +#define mmSDMA0_GFX_RB_BASE_HI 0x3482 +#define mmSDMA0_GFX_RB_RPTR 0x3483 +#define mmSDMA0_GFX_RB_WPTR 0x3484 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489 +#define mmSDMA0_GFX_IB_CNTL 0x348a +#define mmSDMA0_GFX_IB_RPTR 0x348b +#define mmSDMA0_GFX_IB_OFFSET 0x348c +#define mmSDMA0_GFX_IB_BASE_LO 0x348d +#define mmSDMA0_GFX_IB_BASE_HI 0x348e +#define mmSDMA0_GFX_IB_SIZE 0x348f +#define mmSDMA0_GFX_SKIP_CNTL 0x3490 +#define mmSDMA0_GFX_CONTEXT_STATUS 0x3491 +#define mmSDMA0_GFX_CONTEXT_CNTL 0x3493 +#define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7 +#define mmSDMA0_GFX_APE1_CNTL 0x34a8 +#define mmSDMA0_GFX_WATERMARK 0x34aa +#define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac +#define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad +#define mmSDMA0_GFX_DUMMY_REG 0x34ae +#define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af +#define mmSDMA0_GFX_PREEMPT 0x34b0 +#define mmSDMA0_RLC0_RB_CNTL 0x3500 +#define mmSDMA0_RLC0_RB_BASE 0x3501 +#define mmSDMA0_RLC0_RB_BASE_HI 0x3502 +#define mmSDMA0_RLC0_RB_RPTR 0x3503 +#define mmSDMA0_RLC0_RB_WPTR 0x3504 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509 +#define mmSDMA0_RLC0_IB_CNTL 0x350a +#define mmSDMA0_RLC0_IB_RPTR 0x350b +#define mmSDMA0_RLC0_IB_OFFSET 0x350c +#define mmSDMA0_RLC0_IB_BASE_LO 0x350d +#define mmSDMA0_RLC0_IB_BASE_HI 0x350e +#define mmSDMA0_RLC0_IB_SIZE 0x350f +#define mmSDMA0_RLC0_SKIP_CNTL 0x3510 +#define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511 +#define mmSDMA0_RLC0_DOORBELL 0x3512 +#define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527 +#define mmSDMA0_RLC0_APE1_CNTL 0x3528 +#define mmSDMA0_RLC0_DOORBELL_LOG 0x3529 +#define mmSDMA0_RLC0_WATERMARK 0x352a +#define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c +#define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d +#define mmSDMA0_RLC0_DUMMY_REG 0x352e +#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f +#define mmSDMA0_RLC0_PREEMPT 0x3530 +#define mmSDMA0_RLC1_RB_CNTL 0x3580 +#define mmSDMA0_RLC1_RB_BASE 0x3581 +#define mmSDMA0_RLC1_RB_BASE_HI 0x3582 +#define mmSDMA0_RLC1_RB_RPTR 0x3583 +#define mmSDMA0_RLC1_RB_WPTR 0x3584 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589 +#define mmSDMA0_RLC1_IB_CNTL 0x358a +#define mmSDMA0_RLC1_IB_RPTR 0x358b +#define mmSDMA0_RLC1_IB_OFFSET 0x358c +#define mmSDMA0_RLC1_IB_BASE_LO 0x358d +#define mmSDMA0_RLC1_IB_BASE_HI 0x358e +#define mmSDMA0_RLC1_IB_SIZE 0x358f +#define mmSDMA0_RLC1_SKIP_CNTL 0x3590 +#define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591 +#define mmSDMA0_RLC1_DOORBELL 0x3592 +#define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7 +#define mmSDMA0_RLC1_APE1_CNTL 0x35a8 +#define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9 +#define mmSDMA0_RLC1_WATERMARK 0x35aa +#define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac +#define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad +#define mmSDMA0_RLC1_DUMMY_REG 0x35ae +#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af +#define mmSDMA0_RLC1_PREEMPT 0x35b0 +#define mmSDMA1_UCODE_ADDR 0x3600 +#define mmSDMA1_UCODE_DATA 0x3601 +#define mmSDMA1_POWER_CNTL 0x3602 +#define mmSDMA1_CLK_CTRL 0x3603 +#define mmSDMA1_CNTL 0x3604 +#define mmSDMA1_CHICKEN_BITS 0x3605 +#define mmSDMA1_TILING_CONFIG 0x3606 +#define mmSDMA1_HASH 0x3607 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609 +#define mmSDMA1_RB_RPTR_FETCH 0x360a +#define mmSDMA1_IB_OFFSET_FETCH 0x360b +#define mmSDMA1_PROGRAM 0x360c +#define mmSDMA1_STATUS_REG 0x360d +#define mmSDMA1_STATUS1_REG 0x360e +#define mmSDMA1_PERFMON_CNTL 0x9010 +#define mmSDMA1_PERFCOUNTER0_RESULT 0x9011 +#define mmSDMA1_PERFCOUNTER1_RESULT 0x9012 +#define mmSDMA1_F32_CNTL 0x3612 +#define mmSDMA1_FREEZE 0x3613 +#define mmSDMA1_PHASE0_QUANTUM 0x3614 +#define mmSDMA1_PHASE1_QUANTUM 0x3615 +#define mmSDMA1_EDC_CONFIG 0x361a +#define mmSDMA1_BA_THRESHOLD 0x361b +#define mmSDMA1_ID 0x361c +#define mmSDMA1_VERSION 0x361d +#define mmSDMA1_STATUS2_REG 0x361e +#define mmSDMA1_GFX_RB_CNTL 0x3680 +#define mmSDMA1_GFX_RB_BASE 0x3681 +#define mmSDMA1_GFX_RB_BASE_HI 0x3682 +#define mmSDMA1_GFX_RB_RPTR 0x3683 +#define mmSDMA1_GFX_RB_WPTR 0x3684 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689 +#define mmSDMA1_GFX_IB_CNTL 0x368a +#define mmSDMA1_GFX_IB_RPTR 0x368b +#define mmSDMA1_GFX_IB_OFFSET 0x368c +#define mmSDMA1_GFX_IB_BASE_LO 0x368d +#define mmSDMA1_GFX_IB_BASE_HI 0x368e +#define mmSDMA1_GFX_IB_SIZE 0x368f +#define mmSDMA1_GFX_SKIP_CNTL 0x3690 +#define mmSDMA1_GFX_CONTEXT_STATUS 0x3691 +#define mmSDMA1_GFX_CONTEXT_CNTL 0x3693 +#define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7 +#define mmSDMA1_GFX_APE1_CNTL 0x36a8 +#define mmSDMA1_GFX_WATERMARK 0x36aa +#define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac +#define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad +#define mmSDMA1_GFX_DUMMY_REG 0x36ae +#define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af +#define mmSDMA1_GFX_PREEMPT 0x36b0 +#define mmSDMA1_RLC0_RB_CNTL 0x3700 +#define mmSDMA1_RLC0_RB_BASE 0x3701 +#define mmSDMA1_RLC0_RB_BASE_HI 0x3702 +#define mmSDMA1_RLC0_RB_RPTR 0x3703 +#define mmSDMA1_RLC0_RB_WPTR 0x3704 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709 +#define mmSDMA1_RLC0_IB_CNTL 0x370a +#define mmSDMA1_RLC0_IB_RPTR 0x370b +#define mmSDMA1_RLC0_IB_OFFSET 0x370c +#define mmSDMA1_RLC0_IB_BASE_LO 0x370d +#define mmSDMA1_RLC0_IB_BASE_HI 0x370e +#define mmSDMA1_RLC0_IB_SIZE 0x370f +#define mmSDMA1_RLC0_SKIP_CNTL 0x3710 +#define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711 +#define mmSDMA1_RLC0_DOORBELL 0x3712 +#define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727 +#define mmSDMA1_RLC0_APE1_CNTL 0x3728 +#define mmSDMA1_RLC0_DOORBELL_LOG 0x3729 +#define mmSDMA1_RLC0_WATERMARK 0x372a +#define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c +#define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d +#define mmSDMA1_RLC0_DUMMY_REG 0x372e +#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f +#define mmSDMA1_RLC0_PREEMPT 0x3730 +#define mmSDMA1_RLC1_RB_CNTL 0x3780 +#define mmSDMA1_RLC1_RB_BASE 0x3781 +#define mmSDMA1_RLC1_RB_BASE_HI 0x3782 +#define mmSDMA1_RLC1_RB_RPTR 0x3783 +#define mmSDMA1_RLC1_RB_WPTR 0x3784 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789 +#define mmSDMA1_RLC1_IB_CNTL 0x378a +#define mmSDMA1_RLC1_IB_RPTR 0x378b +#define mmSDMA1_RLC1_IB_OFFSET 0x378c +#define mmSDMA1_RLC1_IB_BASE_LO 0x378d +#define mmSDMA1_RLC1_IB_BASE_HI 0x378e +#define mmSDMA1_RLC1_IB_SIZE 0x378f +#define mmSDMA1_RLC1_SKIP_CNTL 0x3790 +#define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791 +#define mmSDMA1_RLC1_DOORBELL 0x3792 +#define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7 +#define mmSDMA1_RLC1_APE1_CNTL 0x37a8 +#define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9 +#define mmSDMA1_RLC1_WATERMARK 0x37aa +#define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac +#define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad +#define mmSDMA1_RLC1_DUMMY_REG 0x37ae +#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af +#define mmSDMA1_RLC1_PREEMPT 0x37b0 +#define mmHDP_HOST_PATH_CNTL 0xb00 +#define mmHDP_NONSURFACE_BASE 0xb01 +#define mmHDP_NONSURFACE_INFO 0xb02 +#define mmHDP_NONSURFACE_SIZE 0xb03 +#define mmHDP_NONSURF_FLAGS 0xbc9 +#define mmHDP_NONSURF_FLAGS_CLR 0xbca +#define mmHDP_SW_SEMAPHORE 0xbcb +#define mmHDP_DEBUG0 0xbcc +#define mmHDP_DEBUG1 0xbcd +#define mmHDP_LAST_SURFACE_HIT 0xbce +#define mmHDP_TILING_CONFIG 0xbcf +#define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0 +#define mmHDP_OUTSTANDING_REQ 0xbd1 +#define mmHDP_ADDR_CONFIG 0xbd2 +#define mmHDP_MISC_CNTL 0xbd3 +#define mmHDP_MEM_POWER_LS 0xbd4 +#define mmHDP_NONSURFACE_PREFETCH 0xbd5 +#define mmHDP_MEMIO_CNTL 0xbf6 +#define mmHDP_MEMIO_ADDR 0xbf7 +#define mmHDP_MEMIO_STATUS 0xbf8 +#define mmHDP_MEMIO_WR_DATA 0xbf9 +#define mmHDP_MEMIO_RD_DATA 0xbfa +#define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00 +#define mmHDP_XDP_D2H_FLUSH 0xc01 +#define mmHDP_XDP_D2H_BAR_UPDATE 0xc02 +#define mmHDP_XDP_D2H_RSVD_3 0xc03 +#define mmHDP_XDP_D2H_RSVD_4 0xc04 +#define mmHDP_XDP_D2H_RSVD_5 0xc05 +#define mmHDP_XDP_D2H_RSVD_6 0xc06 +#define mmHDP_XDP_D2H_RSVD_7 0xc07 +#define mmHDP_XDP_D2H_RSVD_8 0xc08 +#define mmHDP_XDP_D2H_RSVD_9 0xc09 +#define mmHDP_XDP_D2H_RSVD_10 0xc0a +#define mmHDP_XDP_D2H_RSVD_11 0xc0b +#define mmHDP_XDP_D2H_RSVD_12 0xc0c +#define mmHDP_XDP_D2H_RSVD_13 0xc0d +#define mmHDP_XDP_D2H_RSVD_14 0xc0e +#define mmHDP_XDP_D2H_RSVD_15 0xc0f +#define mmHDP_XDP_D2H_RSVD_16 0xc10 +#define mmHDP_XDP_D2H_RSVD_17 0xc11 +#define mmHDP_XDP_D2H_RSVD_18 0xc12 +#define mmHDP_XDP_D2H_RSVD_19 0xc13 +#define mmHDP_XDP_D2H_RSVD_20 0xc14 +#define mmHDP_XDP_D2H_RSVD_21 0xc15 +#define mmHDP_XDP_D2H_RSVD_22 0xc16 +#define mmHDP_XDP_D2H_RSVD_23 0xc17 +#define mmHDP_XDP_D2H_RSVD_24 0xc18 +#define mmHDP_XDP_D2H_RSVD_25 0xc19 +#define mmHDP_XDP_D2H_RSVD_26 0xc1a +#define mmHDP_XDP_D2H_RSVD_27 0xc1b +#define mmHDP_XDP_D2H_RSVD_28 0xc1c +#define mmHDP_XDP_D2H_RSVD_29 0xc1d +#define mmHDP_XDP_D2H_RSVD_30 0xc1e +#define mmHDP_XDP_D2H_RSVD_31 0xc1f +#define mmHDP_XDP_D2H_RSVD_32 0xc20 +#define mmHDP_XDP_D2H_RSVD_33 0xc21 +#define mmHDP_XDP_D2H_RSVD_34 0xc22 +#define mmHDP_XDP_DIRECT2HDP_LAST 0xc23 +#define mmHDP_XDP_P2P_BAR_CFG 0xc24 +#define mmHDP_XDP_P2P_MBX_OFFSET 0xc25 +#define mmHDP_XDP_P2P_MBX_ADDR0 0xc26 +#define mmHDP_XDP_P2P_MBX_ADDR1 0xc27 +#define mmHDP_XDP_P2P_MBX_ADDR2 0xc28 +#define mmHDP_XDP_P2P_MBX_ADDR3 0xc29 +#define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a +#define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b +#define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c +#define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d +#define mmHDP_XDP_HDP_MC_CFG 0xc2e +#define mmHDP_XDP_HST_CFG 0xc2f +#define mmHDP_XDP_SID_CFG 0xc30 +#define mmHDP_XDP_HDP_IPH_CFG 0xc31 +#define mmHDP_XDP_SRBM_CFG 0xc32 +#define mmHDP_XDP_CGTT_BLK_CTRL 0xc33 +#define mmHDP_XDP_P2P_BAR0 0xc34 +#define mmHDP_XDP_P2P_BAR1 0xc35 +#define mmHDP_XDP_P2P_BAR2 0xc36 +#define mmHDP_XDP_P2P_BAR3 0xc37 +#define mmHDP_XDP_P2P_BAR4 0xc38 +#define mmHDP_XDP_P2P_BAR5 0xc39 +#define mmHDP_XDP_P2P_BAR6 0xc3a +#define mmHDP_XDP_P2P_BAR7 0xc3b +#define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c +#define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d +#define mmHDP_XDP_BUSY_STS 0xc3e +#define mmHDP_XDP_STICKY 0xc3f +#define mmHDP_XDP_CHKN 0xc40 +#define mmHDP_XDP_DBG_ADDR 0xc41 +#define mmHDP_XDP_DBG_DATA 0xc42 +#define mmHDP_XDP_DBG_MASK 0xc43 +#define mmHDP_XDP_BARS_ADDR_39_36 0xc44 + +#endif /* OSS_2_4_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h new file mode 100644 index 000000000000..37adf0df0fd3 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h @@ -0,0 +1,1340 @@ +/* + * OSS_2_4 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_2_4_ENUM_H +#define OSS_2_4_ENUM_H + +typedef enum IH_CLIENT_ID { + DC_IH_SRC_ID_START = 0x1, + DC_IH_SRC_ID_END = 0x1f, + VGA_IH_SRC_ID_START = 0x20, + VGA_IH_SRC_ID_END = 0x27, + CAP_IH_SRC_ID_START = 0x28, + CAP_IH_SRC_ID_END = 0x2f, + VIP_IH_SRC_ID_START = 0x30, + VIP_IH_SRC_ID_END = 0x3f, + ROM_IH_SRC_ID_START = 0x40, + ROM_IH_SRC_ID_END = 0x5d, + BIF_IH_SRC_ID_START = 0x5e, + SAM_IH_SRC_ID_START = 0x5f, + SRBM_IH_SRC_ID_START = 0x60, + SRBM_IH_SRC_ID_END = 0x67, + UVD_IH_SRC_ID_START = 0x72, + UVD_IH_SRC_ID_END = 0x85, + VMC_IH_SRC_ID_START = 0x86, + VMC_IH_SRC_ID_END = 0x8f, + RLC_IH_SRC_ID_START = 0x90, + RLC_IH_SRC_ID_END = 0xf3, + PDMA_IH_SRC_ID_START = 0xf4, + PDMA_IH_SRC_ID_END = 0xf7, + CG_IH_SRC_ID_START = 0xf8, + CG_IH_SRC_ID_END = 0xff, +} IH_CLIENT_ID; +typedef enum IH_PERF_SEL { + IH_PERF_SEL_CYCLE = 0x0, + IH_PERF_SEL_IDLE = 0x1, + IH_PERF_SEL_INPUT_IDLE = 0x2, + IH_PERF_SEL_CLIENT0_IH_STALL = 0x3, + IH_PERF_SEL_CLIENT1_IH_STALL = 0x4, + IH_PERF_SEL_CLIENT2_IH_STALL = 0x5, + IH_PERF_SEL_CLIENT3_IH_STALL = 0x6, + IH_PERF_SEL_CLIENT4_IH_STALL = 0x7, + IH_PERF_SEL_CLIENT5_IH_STALL = 0x8, + IH_PERF_SEL_CLIENT6_IH_STALL = 0x9, + IH_PERF_SEL_CLIENT7_IH_STALL = 0xa, + IH_PERF_SEL_RB_IDLE = 0xb, + IH_PERF_SEL_RB_FULL = 0xc, + IH_PERF_SEL_RB_OVERFLOW = 0xd, + IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe, + IH_PERF_SEL_RB_WPTR_WRAP = 0xf, + IH_PERF_SEL_RB_RPTR_WRAP = 0x10, + IH_PERF_SEL_MC_WR_IDLE = 0x11, + IH_PERF_SEL_MC_WR_COUNT = 0x12, + IH_PERF_SEL_MC_WR_STALL = 0x13, + IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14, + IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15, + IH_PERF_SEL_BIF_RISING = 0x16, + IH_PERF_SEL_BIF_FALLING = 0x17, + IH_PERF_SEL_CLIENT8_IH_STALL = 0x18, + IH_PERF_SEL_CLIENT9_IH_STALL = 0x19, + IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a, + IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b, + IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c, + IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d, + IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e, + IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f, + IH_PERF_SEL_CLIENT16_IH_STALL = 0x20, + IH_PERF_SEL_CLIENT17_IH_STALL = 0x21, + IH_PERF_SEL_CLIENT18_IH_STALL = 0x22, + IH_PERF_SEL_CLIENT19_IH_STALL = 0x23, + IH_PERF_SEL_CLIENT20_IH_STALL = 0x24, + IH_PERF_SEL_CLIENT21_IH_STALL = 0x25, +} IH_PERF_SEL; +typedef enum SRBM_PERFCOUNT1_SEL { + SRBM_PERF_SEL_COUNT = 0x0, + SRBM_PERF_SEL_BIF_BUSY = 0x1, + SRBM_PERF_SEL_SDMA0_BUSY = 0x3, + SRBM_PERF_SEL_IH_BUSY = 0x4, + SRBM_PERF_SEL_MCB_BUSY = 0x5, + SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6, + SRBM_PERF_SEL_MCC_BUSY = 0x7, + SRBM_PERF_SEL_MCD_BUSY = 0x8, + SRBM_PERF_SEL_CHUB_BUSY = 0x9, + SRBM_PERF_SEL_SEM_BUSY = 0xa, + SRBM_PERF_SEL_UVD_BUSY = 0xb, + SRBM_PERF_SEL_VMC_BUSY = 0xc, + SRBM_PERF_SEL_XSP_BUSY = 0xd, + SRBM_PERF_SEL_SDMA1_BUSY = 0xe, + SRBM_PERF_SEL_SAMMSP_BUSY = 0xf, + SRBM_PERF_SEL_VCE0_BUSY = 0x10, + SRBM_PERF_SEL_XDMA_BUSY = 0x11, + SRBM_PERF_SEL_ACP_BUSY = 0x12, + SRBM_PERF_SEL_SDMA2_BUSY = 0x13, + SRBM_PERF_SEL_SDMA3_BUSY = 0x14, + SRBM_PERF_SEL_SAMSCP_BUSY = 0x15, + SRBM_PERF_SEL_VMC1_BUSY = 0x16, + SRBM_PERF_SEL_ISP_BUSY = 0x17, + SRBM_PERF_SEL_VCE1_BUSY = 0x18, + SRBM_PERF_SEL_GCATCL2_BUSY = 0x19, + SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a, +} SRBM_PERFCOUNT1_SEL; +typedef enum SYS_GRBM_GFX_INDEX_SEL { + GRBM_GFX_INDEX_BIF = 0x0, + GRBM_GFX_INDEX_SDMA0 = 0x1, + GRBM_GFX_INDEX_SDMA1 = 0x2, + RESEVERED0 = 0x3, + GRBM_GFX_INDEX_UVD = 0x4, + GRBM_GFX_INDEX_VCE0 = 0x5, + GRBM_GFX_INDEX_VCE1 = 0x6, + GRBM_GFX_INDEX_ACP = 0x7, + GRBM_GFX_INDEX_SMU = 0x8, + GRBM_GFX_INDEX_SAMMSP = 0x9, + GRBM_GFX_INDEX_SAMSCP = 0xa, + GRBM_GFX_INDEX_ISP = 0xb, + GRBM_GFX_INDEX_TST = 0xc, + GRBM_GFX_INDEX_SDMA2 = 0xd, + GRBM_GFX_INDEX_SDMA3 = 0xe, +} SYS_GRBM_GFX_INDEX_SEL; +typedef enum SRBM_GFX_CNTL_SEL { + SRBM_GFX_CNTL_BIF = 0x0, + SRBM_GFX_CNTL_SDMA0 = 0x1, + SRBM_GFX_CNTL_SDMA1 = 0x2, + SRBM_GFX_CNTL_GRBM = 0x3, + SRBM_GFX_CNTL_UVD = 0x4, + SRBM_GFX_CNTL_VCE0 = 0x5, + SRBM_GFX_CNTL_VCE1 = 0x6, + SRBM_GFX_CNTL_ACP = 0x7, + SRBM_GFX_CNTL_SMU = 0x8, + SRBM_GFX_CNTL_SAMMSP = 0x9, + SRBM_GFX_CNTL_SAMSCP = 0xa, + SRBM_GFX_CNTL_ISP = 0xb, + SRBM_GFX_CNTL_TST = 0xc, + SRBM_GFX_CNTL_SDMA2 = 0xd, + SRBM_GFX_CNTL_SDMA3 = 0xe, +} SRBM_GFX_CNTL_SEL; +typedef enum SDMA_PERF_SEL { + SDMA_PERF_SEL_CYCLE = 0x0, + SDMA_PERF_SEL_IDLE = 0x1, + SDMA_PERF_SEL_REG_IDLE = 0x2, + SDMA_PERF_SEL_RB_EMPTY = 0x3, + SDMA_PERF_SEL_RB_FULL = 0x4, + SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5, + SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6, + SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7, + SDMA_PERF_SEL_RB_RPTR_WB = 0x8, + SDMA_PERF_SEL_RB_CMD_IDLE = 0x9, + SDMA_PERF_SEL_RB_CMD_FULL = 0xa, + SDMA_PERF_SEL_IB_CMD_IDLE = 0xb, + SDMA_PERF_SEL_IB_CMD_FULL = 0xc, + SDMA_PERF_SEL_EX_IDLE = 0xd, + SDMA_PERF_SEL_SRBM_REG_SEND = 0xe, + SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf, + SDMA_PERF_SEL_MC_WR_IDLE = 0x10, + SDMA_PERF_SEL_MC_WR_COUNT = 0x11, + SDMA_PERF_SEL_MC_RD_IDLE = 0x12, + SDMA_PERF_SEL_MC_RD_COUNT = 0x13, + SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14, + SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15, + SDMA_PERF_SEL_SEM_IDLE = 0x18, + SDMA_PERF_SEL_SEM_REQ_STALL = 0x19, + SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a, + SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b, + SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c, + SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d, + SDMA_PERF_SEL_INT_IDLE = 0x1e, + SDMA_PERF_SEL_INT_REQ_STALL = 0x1f, + SDMA_PERF_SEL_INT_REQ_COUNT = 0x20, + SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21, + SDMA_PERF_SEL_INT_RESP_RETRY = 0x22, + SDMA_PERF_SEL_NUM_PACKET = 0x23, + SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25, + SDMA_PERF_SEL_CE_WR_IDLE = 0x26, + SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27, + SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28, + SDMA_PERF_SEL_CE_OUT_IDLE = 0x29, + SDMA_PERF_SEL_CE_IN_IDLE = 0x2a, + SDMA_PERF_SEL_CE_DST_IDLE = 0x2b, + SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e, + SDMA_PERF_SEL_CE_INFO_FULL = 0x31, + SDMA_PERF_SEL_CE_INFO1_FULL = 0x32, + SDMA_PERF_SEL_CE_RD_STALL = 0x33, + SDMA_PERF_SEL_CE_WR_STALL = 0x34, + SDMA_PERF_SEL_GFX_SELECT = 0x35, + SDMA_PERF_SEL_RLC0_SELECT = 0x36, + SDMA_PERF_SEL_RLC1_SELECT = 0x37, + SDMA_PERF_SEL_CTX_CHANGE = 0x38, + SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39, + SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a, + SDMA_PERF_SEL_DOORBELL = 0x3b, + SDMA_PERF_SEL_RD_BA_RTR = 0x3c, + SDMA_PERF_SEL_WR_BA_RTR = 0x3d, +} SDMA_PERF_SEL; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_uvdu_0 = 0x2, + DBG_CLIENT_BLKID_uvdu_1 = 0x3, + DBG_CLIENT_BLKID_uvdu_2 = 0x4, + DBG_CLIENT_BLKID_uvdu_3 = 0x5, + DBG_CLIENT_BLKID_uvdu_4 = 0x6, + DBG_CLIENT_BLKID_uvdu_5 = 0x7, + DBG_CLIENT_BLKID_uvdu_6 = 0x8, + DBG_CLIENT_BLKID_uvdb_0 = 0x9, + DBG_CLIENT_BLKID_uvdc_0 = 0xa, + DBG_CLIENT_BLKID_uvdc_1 = 0xb, + DBG_CLIENT_BLKID_uvdf_0 = 0xc, + DBG_CLIENT_BLKID_uvdf_1 = 0xd, + DBG_CLIENT_BLKID_uvdm_0 = 0xe, + DBG_CLIENT_BLKID_uvdm_1 = 0xf, + DBG_CLIENT_BLKID_uvdm_2 = 0x10, + DBG_CLIENT_BLKID_uvdm_3 = 0x11, + DBG_CLIENT_BLKID_vcea_0 = 0x12, + DBG_CLIENT_BLKID_vcea_1 = 0x13, + DBG_CLIENT_BLKID_vcea_2 = 0x14, + DBG_CLIENT_BLKID_vcea_3 = 0x15, + DBG_CLIENT_BLKID_vceb_0 = 0x16, + DBG_CLIENT_BLKID_vcec_0 = 0x17, + DBG_CLIENT_BLKID_dco = 0x18, + DBG_CLIENT_BLKID_xdma = 0x19, + DBG_CLIENT_BLKID_dci_pg = 0x1a, + DBG_CLIENT_BLKID_smu_0 = 0x1b, + DBG_CLIENT_BLKID_smu_1 = 0x1c, + DBG_CLIENT_BLKID_smu_2 = 0x1d, + DBG_CLIENT_BLKID_gck = 0x1e, + DBG_CLIENT_BLKID_tmonw0 = 0x1f, + DBG_CLIENT_BLKID_tmonw1 = 0x20, + DBG_CLIENT_BLKID_grbm = 0x21, + DBG_CLIENT_BLKID_rlc = 0x22, + DBG_CLIENT_BLKID_ds0 = 0x23, + DBG_CLIENT_BLKID_cpg_0 = 0x24, + DBG_CLIENT_BLKID_cpg_1 = 0x25, + DBG_CLIENT_BLKID_cpc_0 = 0x26, + DBG_CLIENT_BLKID_cpc_1 = 0x27, + DBG_CLIENT_BLKID_cpf_0 = 0x28, + DBG_CLIENT_BLKID_cpf_1 = 0x29, + DBG_CLIENT_BLKID_scf0 = 0x2a, + DBG_CLIENT_BLKID_scf1 = 0x2b, + DBG_CLIENT_BLKID_scf2 = 0x2c, + DBG_CLIENT_BLKID_scf3 = 0x2d, + DBG_CLIENT_BLKID_pc0 = 0x2e, + DBG_CLIENT_BLKID_pc1 = 0x2f, + DBG_CLIENT_BLKID_pc2 = 0x30, + DBG_CLIENT_BLKID_pc3 = 0x31, + DBG_CLIENT_BLKID_vgt0 = 0x32, + DBG_CLIENT_BLKID_vgt1 = 0x33, + DBG_CLIENT_BLKID_vgt2 = 0x34, + DBG_CLIENT_BLKID_vgt3 = 0x35, + DBG_CLIENT_BLKID_sx00 = 0x36, + DBG_CLIENT_BLKID_sx10 = 0x37, + DBG_CLIENT_BLKID_sx20 = 0x38, + DBG_CLIENT_BLKID_sx30 = 0x39, + DBG_CLIENT_BLKID_cb001 = 0x3a, + DBG_CLIENT_BLKID_cb200 = 0x3b, + DBG_CLIENT_BLKID_cb201 = 0x3c, + DBG_CLIENT_BLKID_cbr0 = 0x3d, + DBG_CLIENT_BLKID_cb000 = 0x3e, + DBG_CLIENT_BLKID_cb101 = 0x3f, + DBG_CLIENT_BLKID_cb300 = 0x40, + DBG_CLIENT_BLKID_cb301 = 0x41, + DBG_CLIENT_BLKID_cbr1 = 0x42, + DBG_CLIENT_BLKID_cb100 = 0x43, + DBG_CLIENT_BLKID_ia0 = 0x44, + DBG_CLIENT_BLKID_ia1 = 0x45, + DBG_CLIENT_BLKID_bci0 = 0x46, + DBG_CLIENT_BLKID_bci1 = 0x47, + DBG_CLIENT_BLKID_bci2 = 0x48, + DBG_CLIENT_BLKID_bci3 = 0x49, + DBG_CLIENT_BLKID_pa0 = 0x4a, + DBG_CLIENT_BLKID_pa1 = 0x4b, + DBG_CLIENT_BLKID_spim0 = 0x4c, + DBG_CLIENT_BLKID_spim1 = 0x4d, + DBG_CLIENT_BLKID_spim2 = 0x4e, + DBG_CLIENT_BLKID_spim3 = 0x4f, + DBG_CLIENT_BLKID_sdma = 0x50, + DBG_CLIENT_BLKID_ih = 0x51, + DBG_CLIENT_BLKID_sem = 0x52, + DBG_CLIENT_BLKID_srbm = 0x53, + DBG_CLIENT_BLKID_hdp = 0x54, + DBG_CLIENT_BLKID_acp_0 = 0x55, + DBG_CLIENT_BLKID_acp_1 = 0x56, + DBG_CLIENT_BLKID_sam = 0x57, + DBG_CLIENT_BLKID_mcc0 = 0x58, + DBG_CLIENT_BLKID_mcc1 = 0x59, + DBG_CLIENT_BLKID_mcc2 = 0x5a, + DBG_CLIENT_BLKID_mcc3 = 0x5b, + DBG_CLIENT_BLKID_mcd0 = 0x5c, + DBG_CLIENT_BLKID_mcd1 = 0x5d, + DBG_CLIENT_BLKID_mcd2 = 0x5e, + DBG_CLIENT_BLKID_mcd3 = 0x5f, + DBG_CLIENT_BLKID_mcb = 0x60, + DBG_CLIENT_BLKID_vmc = 0x61, + DBG_CLIENT_BLKID_gmcon = 0x62, + DBG_CLIENT_BLKID_gdc_0 = 0x63, + DBG_CLIENT_BLKID_gdc_1 = 0x64, + DBG_CLIENT_BLKID_gdc_2 = 0x65, + DBG_CLIENT_BLKID_gdc_3 = 0x66, + DBG_CLIENT_BLKID_gdc_4 = 0x67, + DBG_CLIENT_BLKID_gdc_5 = 0x68, + DBG_CLIENT_BLKID_gdc_6 = 0x69, + DBG_CLIENT_BLKID_gdc_7 = 0x6a, + DBG_CLIENT_BLKID_gdc_8 = 0x6b, + DBG_CLIENT_BLKID_gdc_9 = 0x6c, + DBG_CLIENT_BLKID_gdc_10 = 0x6d, + DBG_CLIENT_BLKID_gdc_11 = 0x6e, + DBG_CLIENT_BLKID_gdc_12 = 0x6f, + DBG_CLIENT_BLKID_gdc_13 = 0x70, + DBG_CLIENT_BLKID_gdc_14 = 0x71, + DBG_CLIENT_BLKID_gdc_15 = 0x72, + DBG_CLIENT_BLKID_gdc_16 = 0x73, + DBG_CLIENT_BLKID_gdc_17 = 0x74, + DBG_CLIENT_BLKID_gdc_18 = 0x75, + DBG_CLIENT_BLKID_gdc_19 = 0x76, + DBG_CLIENT_BLKID_gdc_20 = 0x77, + DBG_CLIENT_BLKID_gdc_21 = 0x78, + DBG_CLIENT_BLKID_gdc_22 = 0x79, + DBG_CLIENT_BLKID_gdc_23 = 0x7a, + DBG_CLIENT_BLKID_gdc_24 = 0x7b, + DBG_CLIENT_BLKID_gdc_25 = 0x7c, + DBG_CLIENT_BLKID_gdc_26 = 0x7d, + DBG_CLIENT_BLKID_gdc_27 = 0x7e, + DBG_CLIENT_BLKID_gdc_28 = 0x7f, + DBG_CLIENT_BLKID_wd = 0x80, + DBG_CLIENT_BLKID_sdma_0 = 0x81, + DBG_CLIENT_BLKID_sdma_1 = 0x82, + DBG_CLIENT_BLKID_sammsp = 0x83, + DBG_CLIENT_BLKID_dci_0 = 0x84, + DBG_CLIENT_BLKID_dccg0_0 = 0x85, + DBG_CLIENT_BLKID_dcfe01_0 = 0x86, + DBG_CLIENT_BLKID_dcfe02_0 = 0x87, + DBG_CLIENT_BLKID_dcfe03_0 = 0x88, + DBG_CLIENT_BLKID_dccg0_1 = 0x89, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; + +#endif /* OSS_2_4_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h new file mode 100644 index 000000000000..413af7d9a21a --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h @@ -0,0 +1,2544 @@ +/* + * OSS_2_4 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_2_4_SH_MASK_H +#define OSS_2_4_SH_MASK_H + +#define IH_VMID_0_LUT__PASID_MASK 0xffff +#define IH_VMID_0_LUT__PASID__SHIFT 0x0 +#define IH_VMID_1_LUT__PASID_MASK 0xffff +#define IH_VMID_1_LUT__PASID__SHIFT 0x0 +#define IH_VMID_2_LUT__PASID_MASK 0xffff +#define IH_VMID_2_LUT__PASID__SHIFT 0x0 +#define IH_VMID_3_LUT__PASID_MASK 0xffff +#define IH_VMID_3_LUT__PASID__SHIFT 0x0 +#define IH_VMID_4_LUT__PASID_MASK 0xffff +#define IH_VMID_4_LUT__PASID__SHIFT 0x0 +#define IH_VMID_5_LUT__PASID_MASK 0xffff +#define IH_VMID_5_LUT__PASID__SHIFT 0x0 +#define IH_VMID_6_LUT__PASID_MASK 0xffff +#define IH_VMID_6_LUT__PASID__SHIFT 0x0 +#define IH_VMID_7_LUT__PASID_MASK 0xffff +#define IH_VMID_7_LUT__PASID__SHIFT 0x0 +#define IH_VMID_8_LUT__PASID_MASK 0xffff +#define IH_VMID_8_LUT__PASID__SHIFT 0x0 +#define IH_VMID_9_LUT__PASID_MASK 0xffff +#define IH_VMID_9_LUT__PASID__SHIFT 0x0 +#define IH_VMID_10_LUT__PASID_MASK 0xffff +#define IH_VMID_10_LUT__PASID__SHIFT 0x0 +#define IH_VMID_11_LUT__PASID_MASK 0xffff +#define IH_VMID_11_LUT__PASID__SHIFT 0x0 +#define IH_VMID_12_LUT__PASID_MASK 0xffff +#define IH_VMID_12_LUT__PASID__SHIFT 0x0 +#define IH_VMID_13_LUT__PASID_MASK 0xffff +#define IH_VMID_13_LUT__PASID__SHIFT 0x0 +#define IH_VMID_14_LUT__PASID_MASK 0xffff +#define IH_VMID_14_LUT__PASID__SHIFT 0x0 +#define IH_VMID_15_LUT__PASID_MASK 0xffff +#define IH_VMID_15_LUT__PASID__SHIFT 0x0 +#define IH_RB_CNTL__RB_ENABLE_MASK 0x1 +#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define IH_RB_CNTL__RB_SIZE_MASK 0x3e +#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40 +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6 +#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80 +#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00 +#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000 +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define IH_RB_BASE__ADDR_MASK 0xffffffff +#define IH_RB_BASE__ADDR__SHIFT 0x0 +#define IH_RB_RPTR__OFFSET_MASK 0x3fffc +#define IH_RB_RPTR__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1 +#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 +#define IH_RB_WPTR__OFFSET_MASK 0x3fffc +#define IH_RB_WPTR__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000 +#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 +#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000 +#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 +#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff +#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define IH_CNTL__ENABLE_INTR_MASK 0x1 +#define IH_CNTL__ENABLE_INTR__SHIFT 0x0 +#define IH_CNTL__MC_SWAP_MASK 0x6 +#define IH_CNTL__MC_SWAP__SHIFT 0x1 +#define IH_CNTL__RPTR_REARM_MASK 0x10 +#define IH_CNTL__RPTR_REARM__SHIFT 0x4 +#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300 +#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8 +#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00 +#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa +#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000 +#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf +#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000 +#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 +#define IH_CNTL__MC_VMID_MASK 0x1e000000 +#define IH_CNTL__MC_VMID__SHIFT 0x19 +#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1 +#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0 +#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4 +#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2 +#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8 +#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3 +#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10 +#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4 +#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20 +#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5 +#define IH_STATUS__IDLE_MASK 0x1 +#define IH_STATUS__IDLE__SHIFT 0x0 +#define IH_STATUS__INPUT_IDLE_MASK 0x2 +#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 +#define IH_STATUS__RB_IDLE_MASK 0x4 +#define IH_STATUS__RB_IDLE__SHIFT 0x2 +#define IH_STATUS__RB_FULL_MASK 0x8 +#define IH_STATUS__RB_FULL__SHIFT 0x3 +#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10 +#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 +#define IH_STATUS__RB_OVERFLOW_MASK 0x20 +#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 +#define IH_STATUS__MC_WR_IDLE_MASK 0x40 +#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 +#define IH_STATUS__MC_WR_STALL_MASK 0x80 +#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 +#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100 +#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 +#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200 +#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 +#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400 +#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa +#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1 +#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 +#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2 +#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 +#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc +#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100 +#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8 +#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200 +#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9 +#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 +#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff +#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff +#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff +#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1 +#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 +#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4 +#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 +#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8 +#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 +#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10 +#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 +#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20 +#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 +#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff +#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 +#define IH_VERSION__VALUE_MASK 0xfff +#define IH_VERSION__VALUE__SHIFT 0x0 +#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3 +#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 +#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc +#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 +#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00 +#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 +#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 +#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 +#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 +#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 +#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 +#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 +#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 +#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 +#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00 +#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8 +#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000 +#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10 +#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00 +#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8 +#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000 +#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10 +#define ACP_CONFIG__ACP_RDREQ_URG_MASK 0xf00 +#define ACP_CONFIG__ACP_RDREQ_URG__SHIFT 0x8 +#define ACP_CONFIG__ACP_REQ_TRAN_MASK 0x10000 +#define ACP_CONFIG__ACP_REQ_TRAN__SHIFT 0x10 +#define CPG_CONFIG__CPG_RDREQ_URG_MASK 0xf00 +#define CPG_CONFIG__CPG_RDREQ_URG__SHIFT 0x8 +#define CPG_CONFIG__CPG_REQ_TRAN_MASK 0x10000 +#define CPG_CONFIG__CPG_REQ_TRAN__SHIFT 0x10 +#define CPC1_CONFIG__CPC1_RDREQ_URG_MASK 0xf00 +#define CPC1_CONFIG__CPC1_RDREQ_URG__SHIFT 0x8 +#define CPC1_CONFIG__CPC1_REQ_TRAN_MASK 0x10000 +#define CPC1_CONFIG__CPC1_REQ_TRAN__SHIFT 0x10 +#define CPC2_CONFIG__CPC2_RDREQ_URG_MASK 0xf00 +#define CPC2_CONFIG__CPC2_RDREQ_URG__SHIFT 0x8 +#define CPC2_CONFIG__CPC2_REQ_TRAN_MASK 0x10000 +#define CPC2_CONFIG__CPC2_REQ_TRAN__SHIFT 0x10 +#define SEM_STATUS__SEM_IDLE_MASK 0x1 +#define SEM_STATUS__SEM_IDLE__SHIFT 0x0 +#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2 +#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 +#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4 +#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 +#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8 +#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 +#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10 +#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 +#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20 +#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 +#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40 +#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 +#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80 +#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 +#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100 +#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 +#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200 +#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 +#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400 +#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa +#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800 +#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb +#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000 +#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc +#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000 +#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd +#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000 +#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe +#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000 +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf +#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000 +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 +#define SEM_MAILBOX__SIDEPORT_MASK 0xff +#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0 +#define SEM_MAILBOX__HOSTPORT_MASK 0xff00 +#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8 +#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000 +#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10 +#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000 +#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18 +#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1 +#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 +#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2 +#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 +#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4 +#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 +#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18 +#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 +#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00 +#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 +#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f +#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 +#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000 +#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10 +#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000 +#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11 +#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000 +#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12 +#define SRBM_GFX_CNTL__PIPEID_MASK 0x3 +#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0 +#define SRBM_GFX_CNTL__MEID_MASK 0xc +#define SRBM_GFX_CNTL__MEID__SHIFT 0x2 +#define SRBM_GFX_CNTL__VMID_MASK 0xf0 +#define SRBM_GFX_CNTL__VMID__SHIFT 0x4 +#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700 +#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 +#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff +#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1 +#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0 +#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2 +#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1 +#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4 +#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2 +#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8 +#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3 +#define SRBM_STATUS2__XSP_BUSY_MASK 0x10 +#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x4 +#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20 +#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5 +#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40 +#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6 +#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80 +#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7 +#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100 +#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8 +#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200 +#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9 +#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400 +#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa +#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800 +#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb +#define SRBM_STATUS2__SAMSCP_BUSY_MASK 0x1000 +#define SRBM_STATUS2__SAMSCP_BUSY__SHIFT 0xc +#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000 +#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd +#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000 +#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe +#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000 +#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10 +#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000 +#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11 +#define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK 0x40000 +#define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT 0x12 +#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000 +#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13 +#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000 +#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14 +#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2 +#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1 +#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4 +#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2 +#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8 +#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3 +#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10 +#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4 +#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20 +#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5 +#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40 +#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6 +#define SRBM_STATUS__VMC_BUSY_MASK 0x100 +#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8 +#define SRBM_STATUS__MCB_BUSY_MASK 0x200 +#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9 +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400 +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa +#define SRBM_STATUS__MCC_BUSY_MASK 0x800 +#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb +#define SRBM_STATUS__MCD_BUSY_MASK 0x1000 +#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc +#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000 +#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd +#define SRBM_STATUS__SEM_BUSY_MASK 0x4000 +#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe +#define SRBM_STATUS__ACP_BUSY_MASK 0x10000 +#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10 +#define SRBM_STATUS__IH_BUSY_MASK 0x20000 +#define SRBM_STATUS__IH_BUSY__SHIFT 0x11 +#define SRBM_STATUS__UVD_BUSY_MASK 0x80000 +#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13 +#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000 +#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14 +#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000 +#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15 +#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000 +#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16 +#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000 +#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d +#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1 +#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0 +#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2 +#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1 +#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4 +#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2 +#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8 +#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3 +#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10 +#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4 +#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20 +#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5 +#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40 +#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6 +#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80 +#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7 +#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100 +#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8 +#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200 +#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9 +#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400 +#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa +#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800 +#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb +#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000 +#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc +#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000 +#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd +#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000 +#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe +#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000 +#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf +#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1 +#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0 +#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2 +#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3 +#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL_MASK 0x10 +#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL__SHIFT 0x4 +#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20 +#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6 +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100 +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8 +#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200 +#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9 +#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400 +#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa +#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800 +#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb +#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000 +#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc +#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000 +#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd +#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000 +#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe +#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000 +#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf +#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000 +#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10 +#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000 +#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11 +#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000 +#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12 +#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x80000 +#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x13 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14 +#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000 +#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15 +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000 +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16 +#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x800000 +#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x17 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18 +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000 +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19 +#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000 +#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a +#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000 +#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b +#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK 0x10000000 +#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT 0x1c +#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000 +#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d +#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000 +#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e +#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0 +#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff +#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0 +#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff +#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 +#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 +#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 +#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1 +#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0 +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2 +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1 +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4 +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2 +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10 +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4 +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20 +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5 +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40 +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6 +#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80 +#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7 +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100 +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8 +#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200 +#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9 +#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400 +#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1 +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0 +#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK 0x2 +#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY__SHIFT 0x1 +#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4 +#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2 +#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8 +#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3 +#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10 +#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4 +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20 +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5 +#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40 +#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6 +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80 +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7 +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100 +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8 +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200 +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9 +#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x400 +#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0xa +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800 +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb +#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x1000 +#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0xc +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000 +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000 +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000 +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000 +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10 +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000 +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11 +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000 +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12 +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000 +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13 +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000 +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14 +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000 +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15 +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000 +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16 +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000 +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17 +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000 +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18 +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000 +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19 +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000 +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000 +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000 +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c +#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000 +#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d +#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK 0x40000000 +#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT 0x1e +#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000 +#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f +#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1 +#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0 +#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc +#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13 +#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000 +#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15 +#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000 +#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16 +#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000 +#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17 +#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000 +#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18 +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000 +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19 +#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000 +#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a +#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK 0x8000000 +#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT 0x1b +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c +#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000 +#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d +#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 +#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1 +#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0 +#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2 +#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1 +#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4 +#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2 +#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000 +#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17 +#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000 +#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18 +#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1 +#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0 +#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2 +#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1 +#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1 +#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0 +#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2 +#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1 +#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1 +#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0 +#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2 +#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK 0x4 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14 +#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000 +#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0 +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000 +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10 +#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff +#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0 +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0 +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000 +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10 +#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff +#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0 +#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf +#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0 +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0 +#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3 +#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff +#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 +#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf +#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0 +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0 +#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00 +#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8 +#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000 +#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10 +#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000 +#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000 +#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f +#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf +#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0 +#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3 +#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0 +#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc +#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2 +#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0 +#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4 +#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700 +#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8 +#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1 +#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1 +#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0 +#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff +#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA0_UCODE_ADDR__VALUE_MASK 0xfff +#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff +#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf +#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1 +#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8 +#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 +#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 +#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 +#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7 +#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0 +#define SDMA0_HASH__BANK_BITS_MASK 0x70 +#define SDMA0_HASH__BANK_BITS__SHIFT 0x4 +#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700 +#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 +#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000 +#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc +#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc +#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff +#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_STATUS_REG__IDLE_MASK 0x1 +#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2 +#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4 +#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8 +#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10 +#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20 +#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40 +#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80 +#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100 +#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200 +#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400 +#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000 +#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000 +#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000 +#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 +#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000 +#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000 +#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 +#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 +#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000 +#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 +#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2 +#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20 +#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40 +#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 +#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 +#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000 +#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000 +#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc +#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 +#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 +#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_F32_CNTL__HALT_MASK 0x1 +#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA0_F32_CNTL__STEP_MASK 0x2 +#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc +#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define SDMA0_FREEZE__FREEZE_MASK 0x10 +#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA0_FREEZE__FROZEN_MASK 0x20 +#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40 +#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf +#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf +#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1 +#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2 +#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1 +#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4 +#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2 +#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30 +#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 +#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40 +#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6 +#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80 +#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7 +#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00 +#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8 +#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000 +#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14 +#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff +#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 +#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200 +#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400 +#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800 +#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000 +#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000 +#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 +#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff +#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff +#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 +#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff +#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 +#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA0_ID__DEVICE_ID_MASK 0xff +#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_VERSION__VALUE_MASK 0xffff +#define SDMA0_VERSION__VALUE__SHIFT 0x0 +#define SDMA0_STATUS2_REG__ID_MASK 0x3 +#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc +#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 +#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000 +#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 +#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_UCODE_ADDR__VALUE_MASK 0xfff +#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff +#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf +#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1 +#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8 +#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 +#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 +#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 +#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7 +#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0 +#define SDMA1_HASH__BANK_BITS_MASK 0x70 +#define SDMA1_HASH__BANK_BITS__SHIFT 0x4 +#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700 +#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 +#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000 +#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc +#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc +#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff +#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_STATUS_REG__IDLE_MASK 0x1 +#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2 +#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4 +#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8 +#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10 +#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20 +#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40 +#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80 +#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100 +#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200 +#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400 +#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000 +#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000 +#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000 +#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 +#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000 +#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000 +#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 +#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 +#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000 +#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 +#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 +#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20 +#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40 +#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 +#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 +#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000 +#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000 +#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc +#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 +#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 +#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_F32_CNTL__HALT_MASK 0x1 +#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA1_F32_CNTL__STEP_MASK 0x2 +#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc +#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define SDMA1_FREEZE__FREEZE_MASK 0x10 +#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA1_FREEZE__FROZEN_MASK 0x20 +#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40 +#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf +#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf +#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff +#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 +#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA1_ID__DEVICE_ID_MASK 0xff +#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA1_VERSION__VALUE_MASK 0xffff +#define SDMA1_VERSION__VALUE__SHIFT 0x0 +#define SDMA1_STATUS2_REG__ID_MASK 0x3 +#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc +#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 +#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000 +#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 +#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7 +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0 +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8 +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3 +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600 +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000 +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16 +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000 +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17 +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000 +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000 +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000 +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f +#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff +#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0 +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1 +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0 +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1 +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60 +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5 +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380 +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd +#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000 +#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11 +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000 +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18 +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000 +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000 +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000 +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0 +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800 +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1 +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 +#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 +#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0 +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 +#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe +#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1 +#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30 +#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4 +#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0 +#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6 +#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700 +#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8 +#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800 +#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb +#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000 +#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7 +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0 +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18 +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3 +#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff +#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 +#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00 +#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 +#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1 +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 +#define HDP_MISC_CNTL__VM_ID_MASK 0x1e +#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1 +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20 +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 +#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40 +#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780 +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000 +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000 +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000 +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13 +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000 +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14 +#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000 +#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 +#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1 +#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 +#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e +#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1 +#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80 +#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b +#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1 +#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 +#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2 +#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 +#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c +#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000 +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000 +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 +#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18 +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f +#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 +#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff +#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 +#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff +#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 +#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000 +#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 +#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff +#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 +#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00 +#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 +#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000 +#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 +#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000 +#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 +#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff +#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0 +#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10 +#define HDP_XDP_DBG_DATA__STS_MASK 0xffff +#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0 +#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10 +#define HDP_XDP_DBG_MASK__STS_MASK 0xffff +#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0 +#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10 +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000 +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c + +#endif /* OSS_2_4_SH_MASK_H */ -- cgit v1.2.3 From 6d5506b6174247e69273a68115bf9711531dacdb Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:27:33 -0400 Subject: drm/amdgpu: add OSS 3.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the OSS (OS Services) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h | 688 ++++ .../drm/amd/include/asic_reg/oss/oss_3_0_enum.h | 1497 ++++++++ .../drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h | 3660 ++++++++++++++++++++ 3 files changed, 5845 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h new file mode 100644 index 000000000000..f56c68bb0b91 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h @@ -0,0 +1,688 @@ +/* + * OSS_3_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_3_0_D_H +#define OSS_3_0_D_H + +#define mmIH_VMID_0_LUT 0xe00 +#define mmIH_VMID_1_LUT 0xe01 +#define mmIH_VMID_2_LUT 0xe02 +#define mmIH_VMID_3_LUT 0xe03 +#define mmIH_VMID_4_LUT 0xe04 +#define mmIH_VMID_5_LUT 0xe05 +#define mmIH_VMID_6_LUT 0xe06 +#define mmIH_VMID_7_LUT 0xe07 +#define mmIH_VMID_8_LUT 0xe08 +#define mmIH_VMID_9_LUT 0xe09 +#define mmIH_VMID_10_LUT 0xe0a +#define mmIH_VMID_11_LUT 0xe0b +#define mmIH_VMID_12_LUT 0xe0c +#define mmIH_VMID_13_LUT 0xe0d +#define mmIH_VMID_14_LUT 0xe0e +#define mmIH_VMID_15_LUT 0xe0f +#define mmIH_RB_CNTL 0xe30 +#define mmIH_RB_BASE 0xe31 +#define mmIH_RB_RPTR 0xe32 +#define mmIH_RB_WPTR 0xe33 +#define mmIH_RB_WPTR_ADDR_HI 0xe34 +#define mmIH_RB_WPTR_ADDR_LO 0xe35 +#define mmIH_CNTL 0xe36 +#define mmIH_LEVEL_STATUS 0xe37 +#define mmIH_STATUS 0xe38 +#define mmIH_PERFMON_CNTL 0xe39 +#define mmIH_PERFCOUNTER0_RESULT 0xe3a +#define mmIH_PERFCOUNTER1_RESULT 0xe3b +#define mmIH_DEBUG 0xe3c +#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d +#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e +#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f +#define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40 +#define mmIH_DSM_MATCH_DATA_CONTROL 0xe41 +#define mmIH_DOORBELL_RPTR 0xe42 +#define mmIH_ACTIVE_FCN_ID 0xe43 +#define mmIH_VF_RB_STATUS 0xe44 +#define mmIH_VF_ENABLE 0xe45 +#define mmIH_VIRT_RESET_REQ 0xe46 +#define mmIH_VF_RB_BIF_STATUS 0xe47 +#define mmIH_VERSION 0xe48 +#define mmIH_LEVEL_INTR_MASK 0xe49 +#define mmIH_RESET_INCOMPLETE_INT_CNTL 0xe4a +#define mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT 0xe4b +#define mmSEM_MCIF_CONFIG 0xf90 +#define mmSDMA_CONFIG 0xf91 +#define mmSDMA1_CONFIG 0xf92 +#define mmUVD_CONFIG 0xf93 +#define mmVCE_CONFIG 0xf94 +#define mmSEM_VF_ENABLE 0xf95 +#define mmCP_CONFIG 0xf96 +#define mmSEM_ACTIVE_FCN_ID 0xf97 +#define mmSEM_VIRT_RESET_REQ 0xf98 +#define mmSEM_STATUS 0xf99 +#define mmSEM_EDC_CONFIG 0xf9a +#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b +#define mmSEM_MAILBOX 0xf9c +#define mmSEM_MAILBOX_CONTROL 0xf9d +#define mmSEM_CHICKEN_BITS 0xf9e +#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f +#define mmSRBM_CNTL 0x390 +#define mmSRBM_GFX_CNTL 0x391 +#define mmSRBM_READ_CNTL 0x392 +#define mmSRBM_STATUS2 0x393 +#define mmSRBM_STATUS 0x394 +#define mmSRBM_STATUS3 0x395 +#define mmSRBM_SOFT_RESET 0x398 +#define mmSRBM_DEBUG_CNTL 0x399 +#define mmSRBM_DEBUG_DATA 0x39a +#define mmSRBM_CHIP_REVISION 0x39b +#define mmSRBM_CREDIT_RECOVER_CNTL 0x39c +#define mmSRBM_CREDIT_RECOVER 0x39d +#define mmSRBM_CREDIT_RESET 0x39e +#define mmCC_SYS_RB_REDUNDANCY 0x39f +#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0 +#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1 +#define mmSRBM_MC_CLKEN_CNTL 0x3b3 +#define mmSRBM_SYS_CLKEN_CNTL 0x3b4 +#define mmSRBM_VCE_CLKEN_CNTL 0x3b5 +#define mmSRBM_UVD_CLKEN_CNTL 0x3b6 +#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7 +#define mmSRBM_SAM_CLKEN_CNTL 0x3b8 +#define mmSRBM_ISP_CLKEN_CNTL 0x3b9 +#define mmSRBM_VP8_CLKEN_CNTL 0x3ba +#define mmSRBM_DEBUG 0x3a4 +#define mmSRBM_DEBUG_SNAPSHOT 0x3a5 +#define mmSRBM_DEBUG_SNAPSHOT2 0x3ad +#define mmSRBM_READ_ERROR 0x3a6 +#define mmSRBM_READ_ERROR2 0x3ae +#define mmSRBM_INT_CNTL 0x3a8 +#define mmSRBM_INT_STATUS 0x3a9 +#define mmSRBM_INT_ACK 0x3aa +#define mmSRBM_FIREWALL_ERROR_SRC 0x3ab +#define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac +#define mmSRBM_DSM_TRIG_CNTL0 0x3af +#define mmSRBM_DSM_TRIG_CNTL1 0x3b0 +#define mmSRBM_DSM_TRIG_MASK0 0x3b1 +#define mmSRBM_DSM_TRIG_MASK1 0x3b2 +#define mmSRBM_PERFMON_CNTL 0x7c00 +#define mmSRBM_PERFCOUNTER0_SELECT 0x7c01 +#define mmSRBM_PERFCOUNTER1_SELECT 0x7c02 +#define mmSRBM_PERFCOUNTER0_LO 0x7c03 +#define mmSRBM_PERFCOUNTER0_HI 0x7c04 +#define mmSRBM_PERFCOUNTER1_LO 0x7c05 +#define mmSRBM_PERFCOUNTER1_HI 0x7c06 +#define mmSRBM_CAM_INDEX 0xfe34 +#define mmSRBM_CAM_DATA 0xfe35 +#define mmSRBM_MC_DOMAIN_ADDR0 0xfa00 +#define mmSRBM_MC_DOMAIN_ADDR1 0xfa01 +#define mmSRBM_MC_DOMAIN_ADDR2 0xfa02 +#define mmSRBM_MC_DOMAIN_ADDR3 0xfa03 +#define mmSRBM_MC_DOMAIN_ADDR4 0xfa04 +#define mmSRBM_MC_DOMAIN_ADDR5 0xfa05 +#define mmSRBM_MC_DOMAIN_ADDR6 0xfa06 +#define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08 +#define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09 +#define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a +#define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b +#define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c +#define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d +#define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e +#define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10 +#define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11 +#define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12 +#define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13 +#define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14 +#define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15 +#define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16 +#define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18 +#define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19 +#define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a +#define mmSRBM_SAM_DOMAIN_ADDR0 0xfa1c +#define mmSRBM_SAM_DOMAIN_ADDR1 0xfa1d +#define mmSRBM_SAM_DOMAIN_ADDR2 0xfa1e +#define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20 +#define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21 +#define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22 +#define mmSRBM_VP8_DOMAIN_ADDR0 0xfa24 +#define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c +#define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d +#define mmSRBM_GFX_CNTL_SELECT 0xfa2e +#define mmSRBM_GFX_CNTL_DATA 0xfa2f +#define mmSRBM_VF_ENABLE 0xfa30 +#define mmSRBM_VIRT_CNTL 0xfa31 +#define mmSRBM_VIRT_RESET_REQ 0xfa32 +#define mmCC_DRM_ID_STRAPS 0x1559 +#define mmCGTT_DRM_CLK_CTRL0 0x1579 +#define ixDH_TEST 0x0 +#define ixKHFS0 0x4 +#define ixKHFS1 0x8 +#define ixKHFS2 0xc +#define ixKHFS3 0x10 +#define ixKSESSION0 0x14 +#define ixKSESSION1 0x18 +#define ixKSESSION2 0x1c +#define ixKSESSION3 0x20 +#define ixKSIG0 0x24 +#define ixKSIG1 0x28 +#define ixKSIG2 0x2c +#define ixKSIG3 0x30 +#define ixEXP0 0x34 +#define ixEXP1 0x38 +#define ixEXP2 0x3c +#define ixEXP3 0x40 +#define ixEXP4 0x44 +#define ixEXP5 0x48 +#define ixEXP6 0x4c +#define ixEXP7 0x50 +#define ixLX0 0x54 +#define ixLX1 0x58 +#define ixLX2 0x5c +#define ixLX3 0x60 +#define ixCLIENT2_K0 0x1b4 +#define ixCLIENT2_K1 0x1b8 +#define ixCLIENT2_K2 0x1bc +#define ixCLIENT2_K3 0x1c0 +#define ixCLIENT2_CK0 0x1c4 +#define ixCLIENT2_CK1 0x1c8 +#define ixCLIENT2_CK2 0x1cc +#define ixCLIENT2_CK3 0x1d0 +#define ixCLIENT2_CD0 0x1d4 +#define ixCLIENT2_CD1 0x1d8 +#define ixCLIENT2_CD2 0x1dc +#define ixCLIENT2_CD3 0x1e0 +#define ixCLIENT2_BM 0x1e4 +#define ixCLIENT2_OFFSET 0x1e8 +#define ixCLIENT2_STATUS 0x1ec +#define ixCLIENT0_K0 0x1f0 +#define ixCLIENT0_K1 0x1f4 +#define ixCLIENT0_K2 0x1f8 +#define ixCLIENT0_K3 0x1fc +#define ixCLIENT0_CK0 0x200 +#define ixCLIENT0_CK1 0x204 +#define ixCLIENT0_CK2 0x208 +#define ixCLIENT0_CK3 0x20c +#define ixCLIENT0_CD0 0x210 +#define ixCLIENT0_CD1 0x214 +#define ixCLIENT0_CD2 0x218 +#define ixCLIENT0_CD3 0x21c +#define ixCLIENT0_BM 0x220 +#define ixCLIENT0_OFFSET 0x224 +#define ixCLIENT0_STATUS 0x228 +#define ixCLIENT1_K0 0x22c +#define ixCLIENT1_K1 0x230 +#define ixCLIENT1_K2 0x234 +#define ixCLIENT1_K3 0x238 +#define ixCLIENT1_CK0 0x23c +#define ixCLIENT1_CK1 0x240 +#define ixCLIENT1_CK2 0x244 +#define ixCLIENT1_CK3 0x248 +#define ixCLIENT1_CD0 0x24c +#define ixCLIENT1_CD1 0x250 +#define ixCLIENT1_CD2 0x254 +#define ixCLIENT1_CD3 0x258 +#define ixCLIENT1_BM 0x25c +#define ixCLIENT1_OFFSET 0x260 +#define ixCLIENT1_PORT_STATUS 0x264 +#define ixKEFUSE0 0x268 +#define ixKEFUSE1 0x26c +#define ixKEFUSE2 0x270 +#define ixKEFUSE3 0x274 +#define ixHFS_SEED0 0x278 +#define ixHFS_SEED1 0x27c +#define ixHFS_SEED2 0x280 +#define ixHFS_SEED3 0x284 +#define ixRINGOSC_MASK 0x288 +#define ixCLIENT0_OFFSET_HI 0x290 +#define ixCLIENT1_OFFSET_HI 0x294 +#define ixCLIENT2_OFFSET_HI 0x298 +#define ixSPU_PORT_STATUS 0x29c +#define ixCLIENT3_OFFSET_HI 0x2a0 +#define ixCLIENT3_K0 0x2a4 +#define ixCLIENT3_K1 0x2a8 +#define ixCLIENT3_K2 0x2ac +#define ixCLIENT3_K3 0x2b0 +#define ixCLIENT3_CK0 0x2b4 +#define ixCLIENT3_CK1 0x2b8 +#define ixCLIENT3_CK2 0x2bc +#define ixCLIENT3_CK3 0x2c0 +#define ixCLIENT3_CD0 0x2c4 +#define ixCLIENT3_CD1 0x2c8 +#define ixCLIENT3_CD2 0x2cc +#define ixCLIENT3_CD3 0x2d0 +#define ixCLIENT3_BM 0x2d4 +#define ixCLIENT3_OFFSET 0x2d8 +#define ixCLIENT3_STATUS 0x2dc +#define ixCLIENT4_OFFSET_HI 0x2e0 +#define ixCLIENT4_K0 0x2e4 +#define ixCLIENT4_K1 0x2e8 +#define ixCLIENT4_K2 0x2ec +#define ixCLIENT4_K3 0x2f0 +#define ixCLIENT4_CK0 0x2f4 +#define ixCLIENT4_CK1 0x2f8 +#define ixCLIENT4_CK2 0x2fc +#define ixCLIENT4_CK3 0x300 +#define ixCLIENT4_CD0 0x304 +#define ixCLIENT4_CD1 0x308 +#define ixCLIENT4_CD2 0x30c +#define ixCLIENT4_CD3 0x310 +#define ixCLIENT4_BM 0x314 +#define ixCLIENT4_OFFSET 0x318 +#define ixCLIENT4_STATUS 0x31c +#define mmDC_TEST_DEBUG_INDEX 0x157c +#define mmDC_TEST_DEBUG_DATA 0x157d +#define mmSDMA0_UCODE_ADDR 0x3400 +#define mmSDMA0_UCODE_DATA 0x3401 +#define mmSDMA0_POWER_CNTL 0x3402 +#define mmSDMA0_CLK_CTRL 0x3403 +#define mmSDMA0_CNTL 0x3404 +#define mmSDMA0_CHICKEN_BITS 0x3405 +#define mmSDMA0_TILING_CONFIG 0x3406 +#define mmSDMA0_HASH 0x3407 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 +#define mmSDMA0_RB_RPTR_FETCH 0x340a +#define mmSDMA0_IB_OFFSET_FETCH 0x340b +#define mmSDMA0_PROGRAM 0x340c +#define mmSDMA0_STATUS_REG 0x340d +#define mmSDMA0_STATUS1_REG 0x340e +#define mmSDMA0_RD_BURST_CNTL 0x340f +#define mmSDMA0_PERFMON_CNTL 0x9000 +#define mmSDMA0_PERFCOUNTER0_RESULT 0x9001 +#define mmSDMA0_PERFCOUNTER1_RESULT 0x9002 +#define mmSDMA0_F32_CNTL 0x3412 +#define mmSDMA0_FREEZE 0x3413 +#define mmSDMA0_PHASE0_QUANTUM 0x3414 +#define mmSDMA0_PHASE1_QUANTUM 0x3415 +#define mmSDMA_POWER_GATING 0x3416 +#define mmSDMA_PGFSM_CONFIG 0x3417 +#define mmSDMA_PGFSM_WRITE 0x3418 +#define mmSDMA_PGFSM_READ 0x3419 +#define mmSDMA0_EDC_CONFIG 0x341a +#define mmSDMA0_VM_CNTL 0x3420 +#define mmSDMA0_VM_CTX_LO 0x3421 +#define mmSDMA0_VM_CTX_HI 0x3422 +#define mmSDMA0_STATUS2_REG 0x3423 +#define mmSDMA0_ACTIVE_FCN_ID 0x3424 +#define mmSDMA0_VM_CTX_CNTL 0x3425 +#define mmSDMA0_VIRT_RESET_REQ 0x3426 +#define mmSDMA0_VF_ENABLE 0x3427 +#define mmSDMA0_BA_THRESHOLD 0x341b +#define mmSDMA0_ID 0x341c +#define mmSDMA0_VERSION 0x341d +#define mmSDMA0_ATOMIC_CNTL 0x3428 +#define mmSDMA0_ATOMIC_PREOP_LO 0x3429 +#define mmSDMA0_ATOMIC_PREOP_HI 0x342a +#define mmSDMA0_POWER_CNTL_IDLE 0x342c +#define mmSDMA0_PERF_REG_TYPE0 0x3477 +#define mmSDMA0_CONTEXT_REG_TYPE0 0x3478 +#define mmSDMA0_CONTEXT_REG_TYPE1 0x3479 +#define mmSDMA0_CONTEXT_REG_TYPE2 0x347a +#define mmSDMA0_PUB_REG_TYPE0 0x347c +#define mmSDMA0_PUB_REG_TYPE1 0x347d +#define mmSDMA0_GFX_RB_CNTL 0x3480 +#define mmSDMA0_GFX_RB_BASE 0x3481 +#define mmSDMA0_GFX_RB_BASE_HI 0x3482 +#define mmSDMA0_GFX_RB_RPTR 0x3483 +#define mmSDMA0_GFX_RB_WPTR 0x3484 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489 +#define mmSDMA0_GFX_IB_CNTL 0x348a +#define mmSDMA0_GFX_IB_RPTR 0x348b +#define mmSDMA0_GFX_IB_OFFSET 0x348c +#define mmSDMA0_GFX_IB_BASE_LO 0x348d +#define mmSDMA0_GFX_IB_BASE_HI 0x348e +#define mmSDMA0_GFX_IB_SIZE 0x348f +#define mmSDMA0_GFX_SKIP_CNTL 0x3490 +#define mmSDMA0_GFX_CONTEXT_STATUS 0x3491 +#define mmSDMA0_GFX_DOORBELL 0x3492 +#define mmSDMA0_GFX_CONTEXT_CNTL 0x3493 +#define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7 +#define mmSDMA0_GFX_APE1_CNTL 0x34a8 +#define mmSDMA0_GFX_DOORBELL_LOG 0x34a9 +#define mmSDMA0_GFX_WATERMARK 0x34aa +#define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac +#define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad +#define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af +#define mmSDMA0_GFX_PREEMPT 0x34b0 +#define mmSDMA0_GFX_DUMMY_REG 0x34b1 +#define mmSDMA0_GFX_MIDCMD_DATA0 0x34c1 +#define mmSDMA0_GFX_MIDCMD_DATA1 0x34c2 +#define mmSDMA0_GFX_MIDCMD_DATA2 0x34c3 +#define mmSDMA0_GFX_MIDCMD_DATA3 0x34c4 +#define mmSDMA0_GFX_MIDCMD_DATA4 0x34c5 +#define mmSDMA0_GFX_MIDCMD_DATA5 0x34c6 +#define mmSDMA0_GFX_MIDCMD_CNTL 0x34c7 +#define mmSDMA0_RLC0_RB_CNTL 0x3500 +#define mmSDMA0_RLC0_RB_BASE 0x3501 +#define mmSDMA0_RLC0_RB_BASE_HI 0x3502 +#define mmSDMA0_RLC0_RB_RPTR 0x3503 +#define mmSDMA0_RLC0_RB_WPTR 0x3504 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509 +#define mmSDMA0_RLC0_IB_CNTL 0x350a +#define mmSDMA0_RLC0_IB_RPTR 0x350b +#define mmSDMA0_RLC0_IB_OFFSET 0x350c +#define mmSDMA0_RLC0_IB_BASE_LO 0x350d +#define mmSDMA0_RLC0_IB_BASE_HI 0x350e +#define mmSDMA0_RLC0_IB_SIZE 0x350f +#define mmSDMA0_RLC0_SKIP_CNTL 0x3510 +#define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511 +#define mmSDMA0_RLC0_DOORBELL 0x3512 +#define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527 +#define mmSDMA0_RLC0_APE1_CNTL 0x3528 +#define mmSDMA0_RLC0_DOORBELL_LOG 0x3529 +#define mmSDMA0_RLC0_WATERMARK 0x352a +#define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c +#define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d +#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f +#define mmSDMA0_RLC0_PREEMPT 0x3530 +#define mmSDMA0_RLC0_DUMMY_REG 0x3531 +#define mmSDMA0_RLC0_MIDCMD_DATA0 0x3541 +#define mmSDMA0_RLC0_MIDCMD_DATA1 0x3542 +#define mmSDMA0_RLC0_MIDCMD_DATA2 0x3543 +#define mmSDMA0_RLC0_MIDCMD_DATA3 0x3544 +#define mmSDMA0_RLC0_MIDCMD_DATA4 0x3545 +#define mmSDMA0_RLC0_MIDCMD_DATA5 0x3546 +#define mmSDMA0_RLC0_MIDCMD_CNTL 0x3547 +#define mmSDMA0_RLC1_RB_CNTL 0x3580 +#define mmSDMA0_RLC1_RB_BASE 0x3581 +#define mmSDMA0_RLC1_RB_BASE_HI 0x3582 +#define mmSDMA0_RLC1_RB_RPTR 0x3583 +#define mmSDMA0_RLC1_RB_WPTR 0x3584 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589 +#define mmSDMA0_RLC1_IB_CNTL 0x358a +#define mmSDMA0_RLC1_IB_RPTR 0x358b +#define mmSDMA0_RLC1_IB_OFFSET 0x358c +#define mmSDMA0_RLC1_IB_BASE_LO 0x358d +#define mmSDMA0_RLC1_IB_BASE_HI 0x358e +#define mmSDMA0_RLC1_IB_SIZE 0x358f +#define mmSDMA0_RLC1_SKIP_CNTL 0x3590 +#define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591 +#define mmSDMA0_RLC1_DOORBELL 0x3592 +#define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7 +#define mmSDMA0_RLC1_APE1_CNTL 0x35a8 +#define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9 +#define mmSDMA0_RLC1_WATERMARK 0x35aa +#define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac +#define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad +#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af +#define mmSDMA0_RLC1_PREEMPT 0x35b0 +#define mmSDMA0_RLC1_DUMMY_REG 0x35b1 +#define mmSDMA0_RLC1_MIDCMD_DATA0 0x35c1 +#define mmSDMA0_RLC1_MIDCMD_DATA1 0x35c2 +#define mmSDMA0_RLC1_MIDCMD_DATA2 0x35c3 +#define mmSDMA0_RLC1_MIDCMD_DATA3 0x35c4 +#define mmSDMA0_RLC1_MIDCMD_DATA4 0x35c5 +#define mmSDMA0_RLC1_MIDCMD_DATA5 0x35c6 +#define mmSDMA0_RLC1_MIDCMD_CNTL 0x35c7 +#define mmSDMA1_UCODE_ADDR 0x3600 +#define mmSDMA1_UCODE_DATA 0x3601 +#define mmSDMA1_POWER_CNTL 0x3602 +#define mmSDMA1_CLK_CTRL 0x3603 +#define mmSDMA1_CNTL 0x3604 +#define mmSDMA1_CHICKEN_BITS 0x3605 +#define mmSDMA1_TILING_CONFIG 0x3606 +#define mmSDMA1_HASH 0x3607 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609 +#define mmSDMA1_RB_RPTR_FETCH 0x360a +#define mmSDMA1_IB_OFFSET_FETCH 0x360b +#define mmSDMA1_PROGRAM 0x360c +#define mmSDMA1_STATUS_REG 0x360d +#define mmSDMA1_STATUS1_REG 0x360e +#define mmSDMA1_RD_BURST_CNTL 0x360f +#define mmSDMA1_PERFMON_CNTL 0x9010 +#define mmSDMA1_PERFCOUNTER0_RESULT 0x9011 +#define mmSDMA1_PERFCOUNTER1_RESULT 0x9012 +#define mmSDMA1_F32_CNTL 0x3612 +#define mmSDMA1_FREEZE 0x3613 +#define mmSDMA1_PHASE0_QUANTUM 0x3614 +#define mmSDMA1_PHASE1_QUANTUM 0x3615 +#define mmSDMA1_EDC_CONFIG 0x361a +#define mmSDMA1_VM_CNTL 0x3620 +#define mmSDMA1_VM_CTX_LO 0x3621 +#define mmSDMA1_VM_CTX_HI 0x3622 +#define mmSDMA1_STATUS2_REG 0x3623 +#define mmSDMA1_ACTIVE_FCN_ID 0x3624 +#define mmSDMA1_VM_CTX_CNTL 0x3625 +#define mmSDMA1_VIRT_RESET_REQ 0x3626 +#define mmSDMA1_VF_ENABLE 0x3627 +#define mmSDMA1_BA_THRESHOLD 0x361b +#define mmSDMA1_ID 0x361c +#define mmSDMA1_VERSION 0x361d +#define mmSDMA1_ATOMIC_CNTL 0x3628 +#define mmSDMA1_ATOMIC_PREOP_LO 0x3629 +#define mmSDMA1_ATOMIC_PREOP_HI 0x362a +#define mmSDMA1_POWER_CNTL_IDLE 0x362c +#define mmSDMA1_PERF_REG_TYPE0 0x3677 +#define mmSDMA1_CONTEXT_REG_TYPE0 0x3678 +#define mmSDMA1_CONTEXT_REG_TYPE1 0x3679 +#define mmSDMA1_CONTEXT_REG_TYPE2 0x367a +#define mmSDMA1_PUB_REG_TYPE0 0x367c +#define mmSDMA1_PUB_REG_TYPE1 0x367d +#define mmSDMA1_GFX_RB_CNTL 0x3680 +#define mmSDMA1_GFX_RB_BASE 0x3681 +#define mmSDMA1_GFX_RB_BASE_HI 0x3682 +#define mmSDMA1_GFX_RB_RPTR 0x3683 +#define mmSDMA1_GFX_RB_WPTR 0x3684 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689 +#define mmSDMA1_GFX_IB_CNTL 0x368a +#define mmSDMA1_GFX_IB_RPTR 0x368b +#define mmSDMA1_GFX_IB_OFFSET 0x368c +#define mmSDMA1_GFX_IB_BASE_LO 0x368d +#define mmSDMA1_GFX_IB_BASE_HI 0x368e +#define mmSDMA1_GFX_IB_SIZE 0x368f +#define mmSDMA1_GFX_SKIP_CNTL 0x3690 +#define mmSDMA1_GFX_CONTEXT_STATUS 0x3691 +#define mmSDMA1_GFX_DOORBELL 0x3692 +#define mmSDMA1_GFX_CONTEXT_CNTL 0x3693 +#define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7 +#define mmSDMA1_GFX_APE1_CNTL 0x36a8 +#define mmSDMA1_GFX_DOORBELL_LOG 0x36a9 +#define mmSDMA1_GFX_WATERMARK 0x36aa +#define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac +#define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad +#define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af +#define mmSDMA1_GFX_PREEMPT 0x36b0 +#define mmSDMA1_GFX_DUMMY_REG 0x36b1 +#define mmSDMA1_GFX_MIDCMD_DATA0 0x36c1 +#define mmSDMA1_GFX_MIDCMD_DATA1 0x36c2 +#define mmSDMA1_GFX_MIDCMD_DATA2 0x36c3 +#define mmSDMA1_GFX_MIDCMD_DATA3 0x36c4 +#define mmSDMA1_GFX_MIDCMD_DATA4 0x36c5 +#define mmSDMA1_GFX_MIDCMD_DATA5 0x36c6 +#define mmSDMA1_GFX_MIDCMD_CNTL 0x36c7 +#define mmSDMA1_RLC0_RB_CNTL 0x3700 +#define mmSDMA1_RLC0_RB_BASE 0x3701 +#define mmSDMA1_RLC0_RB_BASE_HI 0x3702 +#define mmSDMA1_RLC0_RB_RPTR 0x3703 +#define mmSDMA1_RLC0_RB_WPTR 0x3704 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709 +#define mmSDMA1_RLC0_IB_CNTL 0x370a +#define mmSDMA1_RLC0_IB_RPTR 0x370b +#define mmSDMA1_RLC0_IB_OFFSET 0x370c +#define mmSDMA1_RLC0_IB_BASE_LO 0x370d +#define mmSDMA1_RLC0_IB_BASE_HI 0x370e +#define mmSDMA1_RLC0_IB_SIZE 0x370f +#define mmSDMA1_RLC0_SKIP_CNTL 0x3710 +#define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711 +#define mmSDMA1_RLC0_DOORBELL 0x3712 +#define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727 +#define mmSDMA1_RLC0_APE1_CNTL 0x3728 +#define mmSDMA1_RLC0_DOORBELL_LOG 0x3729 +#define mmSDMA1_RLC0_WATERMARK 0x372a +#define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c +#define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d +#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f +#define mmSDMA1_RLC0_PREEMPT 0x3730 +#define mmSDMA1_RLC0_DUMMY_REG 0x3731 +#define mmSDMA1_RLC0_MIDCMD_DATA0 0x3741 +#define mmSDMA1_RLC0_MIDCMD_DATA1 0x3742 +#define mmSDMA1_RLC0_MIDCMD_DATA2 0x3743 +#define mmSDMA1_RLC0_MIDCMD_DATA3 0x3744 +#define mmSDMA1_RLC0_MIDCMD_DATA4 0x3745 +#define mmSDMA1_RLC0_MIDCMD_DATA5 0x3746 +#define mmSDMA1_RLC0_MIDCMD_CNTL 0x3747 +#define mmSDMA1_RLC1_RB_CNTL 0x3780 +#define mmSDMA1_RLC1_RB_BASE 0x3781 +#define mmSDMA1_RLC1_RB_BASE_HI 0x3782 +#define mmSDMA1_RLC1_RB_RPTR 0x3783 +#define mmSDMA1_RLC1_RB_WPTR 0x3784 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789 +#define mmSDMA1_RLC1_IB_CNTL 0x378a +#define mmSDMA1_RLC1_IB_RPTR 0x378b +#define mmSDMA1_RLC1_IB_OFFSET 0x378c +#define mmSDMA1_RLC1_IB_BASE_LO 0x378d +#define mmSDMA1_RLC1_IB_BASE_HI 0x378e +#define mmSDMA1_RLC1_IB_SIZE 0x378f +#define mmSDMA1_RLC1_SKIP_CNTL 0x3790 +#define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791 +#define mmSDMA1_RLC1_DOORBELL 0x3792 +#define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7 +#define mmSDMA1_RLC1_APE1_CNTL 0x37a8 +#define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9 +#define mmSDMA1_RLC1_WATERMARK 0x37aa +#define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac +#define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad +#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af +#define mmSDMA1_RLC1_PREEMPT 0x37b0 +#define mmSDMA1_RLC1_DUMMY_REG 0x37b1 +#define mmSDMA1_RLC1_MIDCMD_DATA0 0x37c1 +#define mmSDMA1_RLC1_MIDCMD_DATA1 0x37c2 +#define mmSDMA1_RLC1_MIDCMD_DATA2 0x37c3 +#define mmSDMA1_RLC1_MIDCMD_DATA3 0x37c4 +#define mmSDMA1_RLC1_MIDCMD_DATA4 0x37c5 +#define mmSDMA1_RLC1_MIDCMD_DATA5 0x37c6 +#define mmSDMA1_RLC1_MIDCMD_CNTL 0x37c7 +#define mmHDP_HOST_PATH_CNTL 0xb00 +#define mmHDP_NONSURFACE_BASE 0xb01 +#define mmHDP_NONSURFACE_INFO 0xb02 +#define mmHDP_NONSURFACE_SIZE 0xb03 +#define mmHDP_NONSURF_FLAGS 0xbc9 +#define mmHDP_NONSURF_FLAGS_CLR 0xbca +#define mmHDP_SW_SEMAPHORE 0xbcb +#define mmHDP_DEBUG0 0xbcc +#define mmHDP_DEBUG1 0xbcd +#define mmHDP_LAST_SURFACE_HIT 0xbce +#define mmHDP_TILING_CONFIG 0xbcf +#define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0 +#define mmHDP_OUTSTANDING_REQ 0xbd1 +#define mmHDP_ADDR_CONFIG 0xbd2 +#define mmHDP_MISC_CNTL 0xbd3 +#define mmHDP_MEM_POWER_LS 0xbd4 +#define mmHDP_NONSURFACE_PREFETCH 0xbd5 +#define mmHDP_MEMIO_CNTL 0xbf6 +#define mmHDP_MEMIO_ADDR 0xbf7 +#define mmHDP_MEMIO_STATUS 0xbf8 +#define mmHDP_MEMIO_WR_DATA 0xbf9 +#define mmHDP_MEMIO_RD_DATA 0xbfa +#define mmHDP_VF_ENABLE 0xbfb +#define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00 +#define mmHDP_XDP_D2H_FLUSH 0xc01 +#define mmHDP_XDP_D2H_BAR_UPDATE 0xc02 +#define mmHDP_XDP_D2H_RSVD_3 0xc03 +#define mmHDP_XDP_D2H_RSVD_4 0xc04 +#define mmHDP_XDP_D2H_RSVD_5 0xc05 +#define mmHDP_XDP_D2H_RSVD_6 0xc06 +#define mmHDP_XDP_D2H_RSVD_7 0xc07 +#define mmHDP_XDP_D2H_RSVD_8 0xc08 +#define mmHDP_XDP_D2H_RSVD_9 0xc09 +#define mmHDP_XDP_D2H_RSVD_10 0xc0a +#define mmHDP_XDP_D2H_RSVD_11 0xc0b +#define mmHDP_XDP_D2H_RSVD_12 0xc0c +#define mmHDP_XDP_D2H_RSVD_13 0xc0d +#define mmHDP_XDP_D2H_RSVD_14 0xc0e +#define mmHDP_XDP_D2H_RSVD_15 0xc0f +#define mmHDP_XDP_D2H_RSVD_16 0xc10 +#define mmHDP_XDP_D2H_RSVD_17 0xc11 +#define mmHDP_XDP_D2H_RSVD_18 0xc12 +#define mmHDP_XDP_D2H_RSVD_19 0xc13 +#define mmHDP_XDP_D2H_RSVD_20 0xc14 +#define mmHDP_XDP_D2H_RSVD_21 0xc15 +#define mmHDP_XDP_D2H_RSVD_22 0xc16 +#define mmHDP_XDP_D2H_RSVD_23 0xc17 +#define mmHDP_XDP_D2H_RSVD_24 0xc18 +#define mmHDP_XDP_D2H_RSVD_25 0xc19 +#define mmHDP_XDP_D2H_RSVD_26 0xc1a +#define mmHDP_XDP_D2H_RSVD_27 0xc1b +#define mmHDP_XDP_D2H_RSVD_28 0xc1c +#define mmHDP_XDP_D2H_RSVD_29 0xc1d +#define mmHDP_XDP_D2H_RSVD_30 0xc1e +#define mmHDP_XDP_D2H_RSVD_31 0xc1f +#define mmHDP_XDP_D2H_RSVD_32 0xc20 +#define mmHDP_XDP_D2H_RSVD_33 0xc21 +#define mmHDP_XDP_D2H_RSVD_34 0xc22 +#define mmHDP_XDP_DIRECT2HDP_LAST 0xc23 +#define mmHDP_XDP_P2P_BAR_CFG 0xc24 +#define mmHDP_XDP_P2P_MBX_OFFSET 0xc25 +#define mmHDP_XDP_P2P_MBX_ADDR0 0xc26 +#define mmHDP_XDP_P2P_MBX_ADDR1 0xc27 +#define mmHDP_XDP_P2P_MBX_ADDR2 0xc28 +#define mmHDP_XDP_P2P_MBX_ADDR3 0xc29 +#define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a +#define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b +#define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c +#define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d +#define mmHDP_XDP_HDP_MC_CFG 0xc2e +#define mmHDP_XDP_HST_CFG 0xc2f +#define mmHDP_XDP_SID_CFG 0xc30 +#define mmHDP_XDP_HDP_IPH_CFG 0xc31 +#define mmHDP_XDP_SRBM_CFG 0xc32 +#define mmHDP_XDP_CGTT_BLK_CTRL 0xc33 +#define mmHDP_XDP_P2P_BAR0 0xc34 +#define mmHDP_XDP_P2P_BAR1 0xc35 +#define mmHDP_XDP_P2P_BAR2 0xc36 +#define mmHDP_XDP_P2P_BAR3 0xc37 +#define mmHDP_XDP_P2P_BAR4 0xc38 +#define mmHDP_XDP_P2P_BAR5 0xc39 +#define mmHDP_XDP_P2P_BAR6 0xc3a +#define mmHDP_XDP_P2P_BAR7 0xc3b +#define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c +#define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d +#define mmHDP_XDP_BUSY_STS 0xc3e +#define mmHDP_XDP_STICKY 0xc3f +#define mmHDP_XDP_CHKN 0xc40 +#define mmHDP_XDP_DBG_ADDR 0xc41 +#define mmHDP_XDP_DBG_DATA 0xc42 +#define mmHDP_XDP_DBG_MASK 0xc43 +#define mmHDP_XDP_BARS_ADDR_39_36 0xc44 + +#endif /* OSS_3_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h new file mode 100644 index 000000000000..09338d82afba --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h @@ -0,0 +1,1497 @@ +/* + * OSS_3_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_3_0_ENUM_H +#define OSS_3_0_ENUM_H + +typedef enum IH_CLIENT_ID { + DC_IH_SRC_ID_START = 0x1, + DC_IH_SRC_ID_END = 0x1f, + VGA_IH_SRC_ID_START = 0x20, + VGA_IH_SRC_ID_END = 0x27, + CAP_IH_SRC_ID_START = 0x28, + CAP_IH_SRC_ID_END = 0x2f, + VIP_IH_SRC_ID_START = 0x30, + VIP_IH_SRC_ID_END = 0x3f, + ROM_IH_SRC_ID_START = 0x40, + ROM_IH_SRC_ID_END = 0x5d, + BIF_IH_SRC_ID_START = 0x5e, + SAM_IH_SRC_ID_START = 0x5f, + SRBM_IH_SRC_ID_START = 0x60, + SRBM_IH_SRC_ID_END = 0x67, + UVD_IH_SRC_ID_START = 0x72, + UVD_IH_SRC_ID_END = 0x85, + VMC_IH_SRC_ID_START = 0x86, + VMC_IH_SRC_ID_END = 0x8f, + RLC_IH_SRC_ID_START = 0x90, + RLC_IH_SRC_ID_END = 0xf3, + PDMA_IH_SRC_ID_START = 0xf4, + PDMA_IH_SRC_ID_END = 0xf7, + CG_IH_SRC_ID_START = 0xf8, + CG_IH_SRC_ID_END = 0xff, +} IH_CLIENT_ID; +typedef enum IH_PERF_SEL { + IH_PERF_SEL_CYCLE = 0x0, + IH_PERF_SEL_IDLE = 0x1, + IH_PERF_SEL_INPUT_IDLE = 0x2, + IH_PERF_SEL_CLIENT0_IH_STALL = 0x3, + IH_PERF_SEL_CLIENT1_IH_STALL = 0x4, + IH_PERF_SEL_CLIENT2_IH_STALL = 0x5, + IH_PERF_SEL_CLIENT3_IH_STALL = 0x6, + IH_PERF_SEL_CLIENT4_IH_STALL = 0x7, + IH_PERF_SEL_CLIENT5_IH_STALL = 0x8, + IH_PERF_SEL_CLIENT6_IH_STALL = 0x9, + IH_PERF_SEL_CLIENT7_IH_STALL = 0xa, + IH_PERF_SEL_RB_IDLE = 0xb, + IH_PERF_SEL_RB_FULL = 0xc, + IH_PERF_SEL_RB_OVERFLOW = 0xd, + IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe, + IH_PERF_SEL_RB_WPTR_WRAP = 0xf, + IH_PERF_SEL_RB_RPTR_WRAP = 0x10, + IH_PERF_SEL_MC_WR_IDLE = 0x11, + IH_PERF_SEL_MC_WR_COUNT = 0x12, + IH_PERF_SEL_MC_WR_STALL = 0x13, + IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14, + IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15, + IH_PERF_SEL_BIF_RISING = 0x16, + IH_PERF_SEL_BIF_FALLING = 0x17, + IH_PERF_SEL_CLIENT8_IH_STALL = 0x18, + IH_PERF_SEL_CLIENT9_IH_STALL = 0x19, + IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a, + IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b, + IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c, + IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d, + IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e, + IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f, + IH_PERF_SEL_CLIENT16_IH_STALL = 0x20, + IH_PERF_SEL_CLIENT17_IH_STALL = 0x21, + IH_PERF_SEL_CLIENT18_IH_STALL = 0x22, + IH_PERF_SEL_CLIENT19_IH_STALL = 0x23, + IH_PERF_SEL_CLIENT20_IH_STALL = 0x24, + IH_PERF_SEL_CLIENT21_IH_STALL = 0x25, + IH_PERF_SEL_CLIENT22_IH_STALL = 0x26, + IH_PERF_SEL_RB_FULL_VF0 = 0x27, + IH_PERF_SEL_RB_FULL_VF1 = 0x28, + IH_PERF_SEL_RB_FULL_VF2 = 0x29, + IH_PERF_SEL_RB_FULL_VF3 = 0x2a, + IH_PERF_SEL_RB_FULL_VF4 = 0x2b, + IH_PERF_SEL_RB_FULL_VF5 = 0x2c, + IH_PERF_SEL_RB_FULL_VF6 = 0x2d, + IH_PERF_SEL_RB_FULL_VF7 = 0x2e, + IH_PERF_SEL_RB_FULL_VF8 = 0x2f, + IH_PERF_SEL_RB_FULL_VF9 = 0x30, + IH_PERF_SEL_RB_FULL_VF10 = 0x31, + IH_PERF_SEL_RB_FULL_VF11 = 0x32, + IH_PERF_SEL_RB_FULL_VF12 = 0x33, + IH_PERF_SEL_RB_FULL_VF13 = 0x34, + IH_PERF_SEL_RB_FULL_VF14 = 0x35, + IH_PERF_SEL_RB_FULL_VF15 = 0x36, + IH_PERF_SEL_RB_OVERFLOW_VF0 = 0x37, + IH_PERF_SEL_RB_OVERFLOW_VF1 = 0x38, + IH_PERF_SEL_RB_OVERFLOW_VF2 = 0x39, + IH_PERF_SEL_RB_OVERFLOW_VF3 = 0x3a, + IH_PERF_SEL_RB_OVERFLOW_VF4 = 0x3b, + IH_PERF_SEL_RB_OVERFLOW_VF5 = 0x3c, + IH_PERF_SEL_RB_OVERFLOW_VF6 = 0x3d, + IH_PERF_SEL_RB_OVERFLOW_VF7 = 0x3e, + IH_PERF_SEL_RB_OVERFLOW_VF8 = 0x3f, + IH_PERF_SEL_RB_OVERFLOW_VF9 = 0x40, + IH_PERF_SEL_RB_OVERFLOW_VF10 = 0x41, + IH_PERF_SEL_RB_OVERFLOW_VF11 = 0x42, + IH_PERF_SEL_RB_OVERFLOW_VF12 = 0x43, + IH_PERF_SEL_RB_OVERFLOW_VF13 = 0x44, + IH_PERF_SEL_RB_OVERFLOW_VF14 = 0x45, + IH_PERF_SEL_RB_OVERFLOW_VF15 = 0x46, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF0 = 0x47, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF1 = 0x48, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF2 = 0x49, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF3 = 0x4a, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF4 = 0x4b, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF5 = 0x4c, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF6 = 0x4d, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF7 = 0x4e, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF8 = 0x4f, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF9 = 0x50, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF10 = 0x51, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF11 = 0x52, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF12 = 0x53, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF13 = 0x54, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF14 = 0x55, + IH_PERF_SEL_RB_WPTR_WRITEBACK_VF15 = 0x56, + IH_PERF_SEL_RB_WPTR_WRAP_VF0 = 0x57, + IH_PERF_SEL_RB_WPTR_WRAP_VF1 = 0x58, + IH_PERF_SEL_RB_WPTR_WRAP_VF2 = 0x59, + IH_PERF_SEL_RB_WPTR_WRAP_VF3 = 0x5a, + IH_PERF_SEL_RB_WPTR_WRAP_VF4 = 0x5b, + IH_PERF_SEL_RB_WPTR_WRAP_VF5 = 0x5c, + IH_PERF_SEL_RB_WPTR_WRAP_VF6 = 0x5d, + IH_PERF_SEL_RB_WPTR_WRAP_VF7 = 0x5e, + IH_PERF_SEL_RB_WPTR_WRAP_VF8 = 0x5f, + IH_PERF_SEL_RB_WPTR_WRAP_VF9 = 0x60, + IH_PERF_SEL_RB_WPTR_WRAP_VF10 = 0x61, + IH_PERF_SEL_RB_WPTR_WRAP_VF11 = 0x62, + IH_PERF_SEL_RB_WPTR_WRAP_VF12 = 0x63, + IH_PERF_SEL_RB_WPTR_WRAP_VF13 = 0x64, + IH_PERF_SEL_RB_WPTR_WRAP_VF14 = 0x65, + IH_PERF_SEL_RB_WPTR_WRAP_VF15 = 0x66, + IH_PERF_SEL_RB_RPTR_WRAP_VF0 = 0x67, + IH_PERF_SEL_RB_RPTR_WRAP_VF1 = 0x68, + IH_PERF_SEL_RB_RPTR_WRAP_VF2 = 0x69, + IH_PERF_SEL_RB_RPTR_WRAP_VF3 = 0x6a, + IH_PERF_SEL_RB_RPTR_WRAP_VF4 = 0x6b, + IH_PERF_SEL_RB_RPTR_WRAP_VF5 = 0x6c, + IH_PERF_SEL_RB_RPTR_WRAP_VF6 = 0x6d, + IH_PERF_SEL_RB_RPTR_WRAP_VF7 = 0x6e, + IH_PERF_SEL_RB_RPTR_WRAP_VF8 = 0x6f, + IH_PERF_SEL_RB_RPTR_WRAP_VF9 = 0x70, + IH_PERF_SEL_RB_RPTR_WRAP_VF10 = 0x71, + IH_PERF_SEL_RB_RPTR_WRAP_VF11 = 0x72, + IH_PERF_SEL_RB_RPTR_WRAP_VF12 = 0x73, + IH_PERF_SEL_RB_RPTR_WRAP_VF13 = 0x74, + IH_PERF_SEL_RB_RPTR_WRAP_VF14 = 0x75, + IH_PERF_SEL_RB_RPTR_WRAP_VF15 = 0x76, + IH_PERF_SEL_BIF_RISING_VF0 = 0x77, + IH_PERF_SEL_BIF_RISING_VF1 = 0x78, + IH_PERF_SEL_BIF_RISING_VF2 = 0x79, + IH_PERF_SEL_BIF_RISING_VF3 = 0x7a, + IH_PERF_SEL_BIF_RISING_VF4 = 0x7b, + IH_PERF_SEL_BIF_RISING_VF5 = 0x7c, + IH_PERF_SEL_BIF_RISING_VF6 = 0x7d, + IH_PERF_SEL_BIF_RISING_VF7 = 0x7e, + IH_PERF_SEL_BIF_RISING_VF8 = 0x7f, + IH_PERF_SEL_BIF_RISING_VF9 = 0x80, + IH_PERF_SEL_BIF_RISING_VF10 = 0x81, + IH_PERF_SEL_BIF_RISING_VF11 = 0x82, + IH_PERF_SEL_BIF_RISING_VF12 = 0x83, + IH_PERF_SEL_BIF_RISING_VF13 = 0x84, + IH_PERF_SEL_BIF_RISING_VF14 = 0x85, + IH_PERF_SEL_BIF_RISING_VF15 = 0x86, + IH_PERF_SEL_BIF_FALLING_VF0 = 0x87, + IH_PERF_SEL_BIF_FALLING_VF1 = 0x88, + IH_PERF_SEL_BIF_FALLING_VF2 = 0x89, + IH_PERF_SEL_BIF_FALLING_VF3 = 0x8a, + IH_PERF_SEL_BIF_FALLING_VF4 = 0x8b, + IH_PERF_SEL_BIF_FALLING_VF5 = 0x8c, + IH_PERF_SEL_BIF_FALLING_VF6 = 0x8d, + IH_PERF_SEL_BIF_FALLING_VF7 = 0x8e, + IH_PERF_SEL_BIF_FALLING_VF8 = 0x8f, + IH_PERF_SEL_BIF_FALLING_VF9 = 0x90, + IH_PERF_SEL_BIF_FALLING_VF10 = 0x91, + IH_PERF_SEL_BIF_FALLING_VF11 = 0x92, + IH_PERF_SEL_BIF_FALLING_VF12 = 0x93, + IH_PERF_SEL_BIF_FALLING_VF13 = 0x94, + IH_PERF_SEL_BIF_FALLING_VF14 = 0x95, + IH_PERF_SEL_BIF_FALLING_VF15 = 0x96, +} IH_PERF_SEL; +typedef enum SRBM_PERFCOUNT1_SEL { + SRBM_PERF_SEL_COUNT = 0x0, + SRBM_PERF_SEL_BIF_BUSY = 0x1, + SRBM_PERF_SEL_SDMA0_BUSY = 0x3, + SRBM_PERF_SEL_IH_BUSY = 0x4, + SRBM_PERF_SEL_MCB_BUSY = 0x5, + SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6, + SRBM_PERF_SEL_MCC_BUSY = 0x7, + SRBM_PERF_SEL_MCD_BUSY = 0x8, + SRBM_PERF_SEL_CHUB_BUSY = 0x9, + SRBM_PERF_SEL_SEM_BUSY = 0xa, + SRBM_PERF_SEL_UVD_BUSY = 0xb, + SRBM_PERF_SEL_VMC_BUSY = 0xc, + SRBM_PERF_SEL_ODE_BUSY = 0xd, + SRBM_PERF_SEL_SDMA1_BUSY = 0xe, + SRBM_PERF_SEL_SAMMSP_BUSY = 0xf, + SRBM_PERF_SEL_VCE0_BUSY = 0x10, + SRBM_PERF_SEL_XDMA_BUSY = 0x11, + SRBM_PERF_SEL_ACP_BUSY = 0x12, + SRBM_PERF_SEL_SDMA2_BUSY = 0x13, + SRBM_PERF_SEL_SDMA3_BUSY = 0x14, + SRBM_PERF_SEL_SAMSCP_BUSY = 0x15, + SRBM_PERF_SEL_VMC1_BUSY = 0x16, + SRBM_PERF_SEL_ISP_BUSY = 0x17, + SRBM_PERF_SEL_VCE1_BUSY = 0x18, + SRBM_PERF_SEL_GCATCL2_BUSY = 0x19, + SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a, + SRBM_PERF_SEL_VP8_BUSY = 0x1b, +} SRBM_PERFCOUNT1_SEL; +typedef enum SYS_GRBM_GFX_INDEX_SEL { + GRBM_GFX_INDEX_BIF = 0x0, + GRBM_GFX_INDEX_SDMA0 = 0x1, + GRBM_GFX_INDEX_SDMA1 = 0x2, + RESEVERED0 = 0x3, + GRBM_GFX_INDEX_UVD = 0x4, + GRBM_GFX_INDEX_VCE0 = 0x5, + GRBM_GFX_INDEX_VCE1 = 0x6, + GRBM_GFX_INDEX_ACP = 0x7, + GRBM_GFX_INDEX_SMU = 0x8, + GRBM_GFX_INDEX_SAMMSP = 0x9, + GRBM_GFX_INDEX_SAMSCP = 0xa, + GRBM_GFX_INDEX_ISP = 0xb, + GRBM_GFX_INDEX_TST = 0xc, + GRBM_GFX_INDEX_SDMA2 = 0xd, + GRBM_GFX_INDEX_SDMA3 = 0xe, +} SYS_GRBM_GFX_INDEX_SEL; +typedef enum SRBM_GFX_CNTL_SEL { + SRBM_GFX_CNTL_BIF = 0x0, + SRBM_GFX_CNTL_SDMA0 = 0x1, + SRBM_GFX_CNTL_SDMA1 = 0x2, + SRBM_GFX_CNTL_GRBM = 0x3, + SRBM_GFX_CNTL_UVD = 0x4, + SRBM_GFX_CNTL_VCE0 = 0x5, + SRBM_GFX_CNTL_VCE1 = 0x6, + SRBM_GFX_CNTL_ACP = 0x7, + SRBM_GFX_CNTL_SMU = 0x8, + SRBM_GFX_CNTL_SAMMSP = 0x9, + SRBM_GFX_CNTL_SAMSCP = 0xa, + SRBM_GFX_CNTL_ISP = 0xb, + SRBM_GFX_CNTL_TST = 0xc, + SRBM_GFX_CNTL_SDMA2 = 0xd, + SRBM_GFX_CNTL_SDMA3 = 0xe, +} SRBM_GFX_CNTL_SEL; +typedef enum SDMA_PERF_SEL { + SDMA_PERF_SEL_CYCLE = 0x0, + SDMA_PERF_SEL_IDLE = 0x1, + SDMA_PERF_SEL_REG_IDLE = 0x2, + SDMA_PERF_SEL_RB_EMPTY = 0x3, + SDMA_PERF_SEL_RB_FULL = 0x4, + SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5, + SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6, + SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7, + SDMA_PERF_SEL_RB_RPTR_WB = 0x8, + SDMA_PERF_SEL_RB_CMD_IDLE = 0x9, + SDMA_PERF_SEL_RB_CMD_FULL = 0xa, + SDMA_PERF_SEL_IB_CMD_IDLE = 0xb, + SDMA_PERF_SEL_IB_CMD_FULL = 0xc, + SDMA_PERF_SEL_EX_IDLE = 0xd, + SDMA_PERF_SEL_SRBM_REG_SEND = 0xe, + SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf, + SDMA_PERF_SEL_MC_WR_IDLE = 0x10, + SDMA_PERF_SEL_MC_WR_COUNT = 0x11, + SDMA_PERF_SEL_MC_RD_IDLE = 0x12, + SDMA_PERF_SEL_MC_RD_COUNT = 0x13, + SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14, + SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15, + SDMA_PERF_SEL_SEM_IDLE = 0x18, + SDMA_PERF_SEL_SEM_REQ_STALL = 0x19, + SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a, + SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b, + SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c, + SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d, + SDMA_PERF_SEL_INT_IDLE = 0x1e, + SDMA_PERF_SEL_INT_REQ_STALL = 0x1f, + SDMA_PERF_SEL_INT_REQ_COUNT = 0x20, + SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21, + SDMA_PERF_SEL_INT_RESP_RETRY = 0x22, + SDMA_PERF_SEL_NUM_PACKET = 0x23, + SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25, + SDMA_PERF_SEL_CE_WR_IDLE = 0x26, + SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27, + SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28, + SDMA_PERF_SEL_CE_OUT_IDLE = 0x29, + SDMA_PERF_SEL_CE_IN_IDLE = 0x2a, + SDMA_PERF_SEL_CE_DST_IDLE = 0x2b, + SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e, + SDMA_PERF_SEL_CE_INFO_FULL = 0x31, + SDMA_PERF_SEL_CE_INFO1_FULL = 0x32, + SDMA_PERF_SEL_CE_RD_STALL = 0x33, + SDMA_PERF_SEL_CE_WR_STALL = 0x34, + SDMA_PERF_SEL_GFX_SELECT = 0x35, + SDMA_PERF_SEL_RLC0_SELECT = 0x36, + SDMA_PERF_SEL_RLC1_SELECT = 0x37, + SDMA_PERF_SEL_CTX_CHANGE = 0x38, + SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39, + SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a, + SDMA_PERF_SEL_DOORBELL = 0x3b, + SDMA_PERF_SEL_RD_BA_RTR = 0x3c, + SDMA_PERF_SEL_WR_BA_RTR = 0x3d, +} SDMA_PERF_SEL; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_scf2 = 0x2, + DBG_CLIENT_BLKID_mcd5 = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_sx30 = 0x5, + DBG_CLIENT_BLKID_mcd2 = 0x6, + DBG_CLIENT_BLKID_bci1 = 0x7, + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, + DBG_CLIENT_BLKID_mcc0 = 0x9, + DBG_CLIENT_BLKID_uvdf_0 = 0xa, + DBG_CLIENT_BLKID_uvdf_1 = 0xb, + DBG_CLIENT_BLKID_uvdf_2 = 0xc, + DBG_CLIENT_BLKID_uvdi_0 = 0xd, + DBG_CLIENT_BLKID_bci0 = 0xe, + DBG_CLIENT_BLKID_vcec0_0 = 0xf, + DBG_CLIENT_BLKID_cb100 = 0x10, + DBG_CLIENT_BLKID_cb001 = 0x11, + DBG_CLIENT_BLKID_mcd4 = 0x12, + DBG_CLIENT_BLKID_tmonw00 = 0x13, + DBG_CLIENT_BLKID_cb101 = 0x14, + DBG_CLIENT_BLKID_sx10 = 0x15, + DBG_CLIENT_BLKID_cb301 = 0x16, + DBG_CLIENT_BLKID_tmonw01 = 0x17, + DBG_CLIENT_BLKID_vcea0_0 = 0x18, + DBG_CLIENT_BLKID_vcea0_1 = 0x19, + DBG_CLIENT_BLKID_vcea0_2 = 0x1a, + DBG_CLIENT_BLKID_vcea0_3 = 0x1b, + DBG_CLIENT_BLKID_scf1 = 0x1c, + DBG_CLIENT_BLKID_sx20 = 0x1d, + DBG_CLIENT_BLKID_spim1 = 0x1e, + DBG_CLIENT_BLKID_pa10 = 0x1f, + DBG_CLIENT_BLKID_pa00 = 0x20, + DBG_CLIENT_BLKID_gmcon = 0x21, + DBG_CLIENT_BLKID_mcb = 0x22, + DBG_CLIENT_BLKID_vgt0 = 0x23, + DBG_CLIENT_BLKID_pc0 = 0x24, + DBG_CLIENT_BLKID_bci2 = 0x25, + DBG_CLIENT_BLKID_uvdb_0 = 0x26, + DBG_CLIENT_BLKID_spim3 = 0x27, + DBG_CLIENT_BLKID_cpc_0 = 0x28, + DBG_CLIENT_BLKID_cpc_1 = 0x29, + DBG_CLIENT_BLKID_uvdm_0 = 0x2a, + DBG_CLIENT_BLKID_uvdm_1 = 0x2b, + DBG_CLIENT_BLKID_uvdm_2 = 0x2c, + DBG_CLIENT_BLKID_uvdm_3 = 0x2d, + DBG_CLIENT_BLKID_cb000 = 0x2e, + DBG_CLIENT_BLKID_spim0 = 0x2f, + DBG_CLIENT_BLKID_mcc2 = 0x30, + DBG_CLIENT_BLKID_ds0 = 0x31, + DBG_CLIENT_BLKID_srbm = 0x32, + DBG_CLIENT_BLKID_ih = 0x33, + DBG_CLIENT_BLKID_sem = 0x34, + DBG_CLIENT_BLKID_sdma_0 = 0x35, + DBG_CLIENT_BLKID_sdma_1 = 0x36, + DBG_CLIENT_BLKID_hdp = 0x37, + DBG_CLIENT_BLKID_acp_0 = 0x38, + DBG_CLIENT_BLKID_acp_1 = 0x39, + DBG_CLIENT_BLKID_cb200 = 0x3a, + DBG_CLIENT_BLKID_scf3 = 0x3b, + DBG_CLIENT_BLKID_vceb1_0 = 0x3c, + DBG_CLIENT_BLKID_vcea1_0 = 0x3d, + DBG_CLIENT_BLKID_vcea1_1 = 0x3e, + DBG_CLIENT_BLKID_vcea1_2 = 0x3f, + DBG_CLIENT_BLKID_vcea1_3 = 0x40, + DBG_CLIENT_BLKID_bci3 = 0x41, + DBG_CLIENT_BLKID_mcd0 = 0x42, + DBG_CLIENT_BLKID_pa11 = 0x43, + DBG_CLIENT_BLKID_pa01 = 0x44, + DBG_CLIENT_BLKID_cb201 = 0x45, + DBG_CLIENT_BLKID_spim2 = 0x46, + DBG_CLIENT_BLKID_vgt2 = 0x47, + DBG_CLIENT_BLKID_pc2 = 0x48, + DBG_CLIENT_BLKID_smu_0 = 0x49, + DBG_CLIENT_BLKID_smu_1 = 0x4a, + DBG_CLIENT_BLKID_smu_2 = 0x4b, + DBG_CLIENT_BLKID_cb1 = 0x4c, + DBG_CLIENT_BLKID_ia0 = 0x4d, + DBG_CLIENT_BLKID_wd = 0x4e, + DBG_CLIENT_BLKID_ia1 = 0x4f, + DBG_CLIENT_BLKID_vcec1_0 = 0x50, + DBG_CLIENT_BLKID_scf0 = 0x51, + DBG_CLIENT_BLKID_vgt1 = 0x52, + DBG_CLIENT_BLKID_pc1 = 0x53, + DBG_CLIENT_BLKID_cb0 = 0x54, + DBG_CLIENT_BLKID_gdc_one_0 = 0x55, + DBG_CLIENT_BLKID_gdc_one_1 = 0x56, + DBG_CLIENT_BLKID_gdc_one_2 = 0x57, + DBG_CLIENT_BLKID_gdc_one_3 = 0x58, + DBG_CLIENT_BLKID_gdc_one_4 = 0x59, + DBG_CLIENT_BLKID_gdc_one_5 = 0x5a, + DBG_CLIENT_BLKID_gdc_one_6 = 0x5b, + DBG_CLIENT_BLKID_gdc_one_7 = 0x5c, + DBG_CLIENT_BLKID_gdc_one_8 = 0x5d, + DBG_CLIENT_BLKID_gdc_one_9 = 0x5e, + DBG_CLIENT_BLKID_gdc_one_10 = 0x5f, + DBG_CLIENT_BLKID_gdc_one_11 = 0x60, + DBG_CLIENT_BLKID_gdc_one_12 = 0x61, + DBG_CLIENT_BLKID_gdc_one_13 = 0x62, + DBG_CLIENT_BLKID_gdc_one_14 = 0x63, + DBG_CLIENT_BLKID_gdc_one_15 = 0x64, + DBG_CLIENT_BLKID_gdc_one_16 = 0x65, + DBG_CLIENT_BLKID_gdc_one_17 = 0x66, + DBG_CLIENT_BLKID_gdc_one_18 = 0x67, + DBG_CLIENT_BLKID_gdc_one_19 = 0x68, + DBG_CLIENT_BLKID_gdc_one_20 = 0x69, + DBG_CLIENT_BLKID_gdc_one_21 = 0x6a, + DBG_CLIENT_BLKID_gdc_one_22 = 0x6b, + DBG_CLIENT_BLKID_gdc_one_23 = 0x6c, + DBG_CLIENT_BLKID_gdc_one_24 = 0x6d, + DBG_CLIENT_BLKID_gdc_one_25 = 0x6e, + DBG_CLIENT_BLKID_gdc_one_26 = 0x6f, + DBG_CLIENT_BLKID_gdc_one_27 = 0x70, + DBG_CLIENT_BLKID_gdc_one_28 = 0x71, + DBG_CLIENT_BLKID_gdc_one_29 = 0x72, + DBG_CLIENT_BLKID_gdc_one_30 = 0x73, + DBG_CLIENT_BLKID_gdc_one_31 = 0x74, + DBG_CLIENT_BLKID_gdc_one_32 = 0x75, + DBG_CLIENT_BLKID_gdc_one_33 = 0x76, + DBG_CLIENT_BLKID_gdc_one_34 = 0x77, + DBG_CLIENT_BLKID_gdc_one_35 = 0x78, + DBG_CLIENT_BLKID_vceb0_0 = 0x79, + DBG_CLIENT_BLKID_vgt3 = 0x7a, + DBG_CLIENT_BLKID_pc3 = 0x7b, + DBG_CLIENT_BLKID_mcd3 = 0x7c, + DBG_CLIENT_BLKID_uvdu_0 = 0x7d, + DBG_CLIENT_BLKID_uvdu_1 = 0x7e, + DBG_CLIENT_BLKID_uvdu_2 = 0x7f, + DBG_CLIENT_BLKID_uvdu_3 = 0x80, + DBG_CLIENT_BLKID_uvdu_4 = 0x81, + DBG_CLIENT_BLKID_uvdu_5 = 0x82, + DBG_CLIENT_BLKID_uvdu_6 = 0x83, + DBG_CLIENT_BLKID_cb300 = 0x84, + DBG_CLIENT_BLKID_mcd1 = 0x85, + DBG_CLIENT_BLKID_sx00 = 0x86, + DBG_CLIENT_BLKID_uvdc_0 = 0x87, + DBG_CLIENT_BLKID_uvdc_1 = 0x88, + DBG_CLIENT_BLKID_mcc3 = 0x89, + DBG_CLIENT_BLKID_cpg_0 = 0x8a, + DBG_CLIENT_BLKID_cpg_1 = 0x8b, + DBG_CLIENT_BLKID_gck = 0x8c, + DBG_CLIENT_BLKID_mcc1 = 0x8d, + DBG_CLIENT_BLKID_cpf_0 = 0x8e, + DBG_CLIENT_BLKID_cpf_1 = 0x8f, + DBG_CLIENT_BLKID_rlc = 0x90, + DBG_CLIENT_BLKID_grbm = 0x91, + DBG_CLIENT_BLKID_sammsp = 0x92, + DBG_CLIENT_BLKID_dci_pg = 0x93, + DBG_CLIENT_BLKID_dci_0 = 0x94, + DBG_CLIENT_BLKID_dccg0_0 = 0x95, + DBG_CLIENT_BLKID_dccg0_1 = 0x96, + DBG_CLIENT_BLKID_dcfe01_0 = 0x97, + DBG_CLIENT_BLKID_dcfe02_0 = 0x98, + DBG_CLIENT_BLKID_dcfe03_0 = 0x99, + DBG_CLIENT_BLKID_dcfe04_0 = 0x9a, + DBG_CLIENT_BLKID_dcfe05_0 = 0x9b, + DBG_CLIENT_BLKID_dcfe06_0 = 0x9c, + DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* OSS_3_0_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h new file mode 100644 index 000000000000..7e2cca5fed87 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h @@ -0,0 +1,3660 @@ +/* + * OSS_3_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_3_0_SH_MASK_H +#define OSS_3_0_SH_MASK_H + +#define IH_VMID_0_LUT__PASID_MASK 0xffff +#define IH_VMID_0_LUT__PASID__SHIFT 0x0 +#define IH_VMID_1_LUT__PASID_MASK 0xffff +#define IH_VMID_1_LUT__PASID__SHIFT 0x0 +#define IH_VMID_2_LUT__PASID_MASK 0xffff +#define IH_VMID_2_LUT__PASID__SHIFT 0x0 +#define IH_VMID_3_LUT__PASID_MASK 0xffff +#define IH_VMID_3_LUT__PASID__SHIFT 0x0 +#define IH_VMID_4_LUT__PASID_MASK 0xffff +#define IH_VMID_4_LUT__PASID__SHIFT 0x0 +#define IH_VMID_5_LUT__PASID_MASK 0xffff +#define IH_VMID_5_LUT__PASID__SHIFT 0x0 +#define IH_VMID_6_LUT__PASID_MASK 0xffff +#define IH_VMID_6_LUT__PASID__SHIFT 0x0 +#define IH_VMID_7_LUT__PASID_MASK 0xffff +#define IH_VMID_7_LUT__PASID__SHIFT 0x0 +#define IH_VMID_8_LUT__PASID_MASK 0xffff +#define IH_VMID_8_LUT__PASID__SHIFT 0x0 +#define IH_VMID_9_LUT__PASID_MASK 0xffff +#define IH_VMID_9_LUT__PASID__SHIFT 0x0 +#define IH_VMID_10_LUT__PASID_MASK 0xffff +#define IH_VMID_10_LUT__PASID__SHIFT 0x0 +#define IH_VMID_11_LUT__PASID_MASK 0xffff +#define IH_VMID_11_LUT__PASID__SHIFT 0x0 +#define IH_VMID_12_LUT__PASID_MASK 0xffff +#define IH_VMID_12_LUT__PASID__SHIFT 0x0 +#define IH_VMID_13_LUT__PASID_MASK 0xffff +#define IH_VMID_13_LUT__PASID__SHIFT 0x0 +#define IH_VMID_14_LUT__PASID_MASK 0xffff +#define IH_VMID_14_LUT__PASID__SHIFT 0x0 +#define IH_VMID_15_LUT__PASID_MASK 0xffff +#define IH_VMID_15_LUT__PASID__SHIFT 0x0 +#define IH_RB_CNTL__RB_ENABLE_MASK 0x1 +#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define IH_RB_CNTL__RB_SIZE_MASK 0x3e +#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80 +#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define IH_RB_CNTL__ENABLE_INTR_MASK 0x20000 +#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 +#define IH_RB_CNTL__MC_SWAP_MASK 0xc0000 +#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 +#define IH_RB_CNTL__RPTR_REARM_MASK 0x200000 +#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 +#define IH_RB_CNTL__MC_VMID_MASK 0xf000000 +#define IH_RB_CNTL__MC_VMID__SHIFT 0x18 +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define IH_RB_BASE__ADDR_MASK 0xffffffff +#define IH_RB_BASE__ADDR__SHIFT 0x0 +#define IH_RB_RPTR__OFFSET_MASK 0x3fffc +#define IH_RB_RPTR__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1 +#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 +#define IH_RB_WPTR__OFFSET_MASK 0x3fffc +#define IH_RB_WPTR__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000 +#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 +#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000 +#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 +#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff +#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x1f +#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 +#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300 +#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8 +#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00 +#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa +#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000 +#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf +#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000 +#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 +#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1 +#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0 +#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4 +#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2 +#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8 +#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3 +#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10 +#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4 +#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20 +#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5 +#define IH_STATUS__IDLE_MASK 0x1 +#define IH_STATUS__IDLE__SHIFT 0x0 +#define IH_STATUS__INPUT_IDLE_MASK 0x2 +#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 +#define IH_STATUS__RB_IDLE_MASK 0x4 +#define IH_STATUS__RB_IDLE__SHIFT 0x2 +#define IH_STATUS__RB_FULL_MASK 0x8 +#define IH_STATUS__RB_FULL__SHIFT 0x3 +#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10 +#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 +#define IH_STATUS__RB_OVERFLOW_MASK 0x20 +#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 +#define IH_STATUS__MC_WR_IDLE_MASK 0x40 +#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 +#define IH_STATUS__MC_WR_STALL_MASK 0x80 +#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 +#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100 +#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 +#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200 +#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 +#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400 +#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa +#define IH_STATUS__SWITCH_READY_MASK 0x800 +#define IH_STATUS__SWITCH_READY__SHIFT 0xb +#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1 +#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 +#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2 +#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 +#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc +#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define IH_PERFMON_CNTL__ENABLE1_MASK 0x400 +#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0xa +#define IH_PERFMON_CNTL__CLEAR1_MASK 0x800 +#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0xb +#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xff000 +#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_DEBUG__RB_FULL_DRAIN_ENABLE_MASK 0x1 +#define IH_DEBUG__RB_FULL_DRAIN_ENABLE__SHIFT 0x0 +#define IH_DEBUG__WPTR_OVERFLOW_ENABLE_MASK 0x2 +#define IH_DEBUG__WPTR_OVERFLOW_ENABLE__SHIFT 0x1 +#define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE_MASK 0x4 +#define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE__SHIFT 0x2 +#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff +#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff +#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff +#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1 +#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 +#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x2 +#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 +#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4 +#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 +#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8 +#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 +#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10 +#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 +#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20 +#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 +#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff +#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 +#define IH_DOORBELL_RPTR__OFFSET_MASK 0x1fffff +#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 +#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000 +#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c +#define IH_DOORBELL_RPTR__CAPTURED_MASK 0x40000000 +#define IH_DOORBELL_RPTR__CAPTURED__SHIFT 0x1e +#define IH_ACTIVE_FCN_ID__VF_ID_MASK 0xf +#define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 +#define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0 +#define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000 +#define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f +#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0xffff +#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 +#define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xffff0000 +#define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 +#define IH_VF_ENABLE__VALUE_MASK 0x1 +#define IH_VF_ENABLE__VALUE__SHIFT 0x0 +#define IH_VIRT_RESET_REQ__VF_MASK 0xffff +#define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define IH_VF_RB_BIF_STATUS__RB_FULL_VF_MASK 0xffff +#define IH_VF_RB_BIF_STATUS__RB_FULL_VF__SHIFT 0x0 +#define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF_MASK 0xffff0000 +#define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF__SHIFT 0x10 +#define IH_VERSION__VALUE_MASK 0xfff +#define IH_VERSION__VALUE__SHIFT 0x0 +#define IH_LEVEL_INTR_MASK__MASK_MASK 0x1 +#define IH_LEVEL_INTR_MASK__MASK__SHIFT 0x0 +#define IH_RESET_INCOMPLETE_INT_CNTL__CG_MASK 0x1 +#define IH_RESET_INCOMPLETE_INT_CNTL__CG__SHIFT 0x0 +#define IH_RESET_INCOMPLETE_INT_CNTL__DC_MASK 0x2 +#define IH_RESET_INCOMPLETE_INT_CNTL__DC__SHIFT 0x1 +#define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP_MASK 0x8 +#define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP__SHIFT 0x3 +#define IH_RESET_INCOMPLETE_INT_CNTL__RLC_MASK 0x10 +#define IH_RESET_INCOMPLETE_INT_CNTL__RLC__SHIFT 0x4 +#define IH_RESET_INCOMPLETE_INT_CNTL__ROM_MASK 0x20 +#define IH_RESET_INCOMPLETE_INT_CNTL__ROM__SHIFT 0x5 +#define IH_RESET_INCOMPLETE_INT_CNTL__SRBM_MASK 0x40 +#define IH_RESET_INCOMPLETE_INT_CNTL__SRBM__SHIFT 0x6 +#define IH_RESET_INCOMPLETE_INT_CNTL__VMC_MASK 0x80 +#define IH_RESET_INCOMPLETE_INT_CNTL__VMC__SHIFT 0x7 +#define IH_RESET_INCOMPLETE_INT_CNTL__UVD_MASK 0x100 +#define IH_RESET_INCOMPLETE_INT_CNTL__UVD__SHIFT 0x8 +#define IH_RESET_INCOMPLETE_INT_CNTL__BIF_MASK 0x200 +#define IH_RESET_INCOMPLETE_INT_CNTL__BIF__SHIFT 0x9 +#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0_MASK 0x400 +#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0__SHIFT 0xa +#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1_MASK 0x800 +#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1__SHIFT 0xb +#define IH_RESET_INCOMPLETE_INT_CNTL__ISP_MASK 0x1000 +#define IH_RESET_INCOMPLETE_INT_CNTL__ISP__SHIFT 0xc +#define IH_RESET_INCOMPLETE_INT_CNTL__VCE0_MASK 0x2000 +#define IH_RESET_INCOMPLETE_INT_CNTL__VCE0__SHIFT 0xd +#define IH_RESET_INCOMPLETE_INT_CNTL__VCE1_MASK 0x4000 +#define IH_RESET_INCOMPLETE_INT_CNTL__VCE1__SHIFT 0xe +#define IH_RESET_INCOMPLETE_INT_CNTL__ATC_MASK 0x8000 +#define IH_RESET_INCOMPLETE_INT_CNTL__ATC__SHIFT 0xf +#define IH_RESET_INCOMPLETE_INT_CNTL__XDMA_MASK 0x10000 +#define IH_RESET_INCOMPLETE_INT_CNTL__XDMA__SHIFT 0x10 +#define IH_RESET_INCOMPLETE_INT_CNTL__ACP_MASK 0x20000 +#define IH_RESET_INCOMPLETE_INT_CNTL__ACP__SHIFT 0x11 +#define IH_RESET_INCOMPLETE_INT_CNTL__SH_MASK 0x40000 +#define IH_RESET_INCOMPLETE_INT_CNTL__SH__SHIFT 0x12 +#define IH_RESET_INCOMPLETE_INT_CNTL__SH1_MASK 0x80000 +#define IH_RESET_INCOMPLETE_INT_CNTL__SH1__SHIFT 0x13 +#define IH_RESET_INCOMPLETE_INT_CNTL__SH2_MASK 0x100000 +#define IH_RESET_INCOMPLETE_INT_CNTL__SH2__SHIFT 0x14 +#define IH_RESET_INCOMPLETE_INT_CNTL__SH3_MASK 0x200000 +#define IH_RESET_INCOMPLETE_INT_CNTL__SH3__SHIFT 0x15 +#define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE_MASK 0x400000 +#define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE__SHIFT 0x16 +#define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT_MASK 0xf000000 +#define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT__SHIFT 0x18 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG_MASK 0x1 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG__SHIFT 0x0 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC_MASK 0x2 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC__SHIFT 0x1 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP_MASK 0x8 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP__SHIFT 0x3 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC_MASK 0x10 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC__SHIFT 0x4 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM_MASK 0x20 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM__SHIFT 0x5 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM_MASK 0x40 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM__SHIFT 0x6 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC_MASK 0x80 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC__SHIFT 0x7 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD_MASK 0x100 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD__SHIFT 0x8 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF_MASK 0x200 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF__SHIFT 0x9 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0_MASK 0x400 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0__SHIFT 0xa +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1_MASK 0x800 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1__SHIFT 0xb +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP_MASK 0x1000 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP__SHIFT 0xc +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0_MASK 0x2000 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0__SHIFT 0xd +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1_MASK 0x4000 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1__SHIFT 0xe +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC_MASK 0x8000 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC__SHIFT 0xf +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA_MASK 0x10000 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA__SHIFT 0x10 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP_MASK 0x20000 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP__SHIFT 0x11 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH_MASK 0x40000 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH__SHIFT 0x12 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1_MASK 0x80000 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1__SHIFT 0x13 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2_MASK 0x100000 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2__SHIFT 0x14 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3_MASK 0x200000 +#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3__SHIFT 0x15 +#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3 +#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 +#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc +#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 +#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00 +#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 +#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 +#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 +#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 +#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 +#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 +#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 +#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 +#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 +#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00 +#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8 +#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000 +#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10 +#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00 +#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8 +#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000 +#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10 +#define SEM_VF_ENABLE__VALUE_MASK 0x1 +#define SEM_VF_ENABLE__VALUE__SHIFT 0x0 +#define CP_CONFIG__CP_RDREQ_URG_MASK 0xf00 +#define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x8 +#define CP_CONFIG__CP_REQ_TRAN_MASK 0x10000 +#define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x10 +#define SEM_ACTIVE_FCN_ID__VFID_MASK 0xf +#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000 +#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SEM_VIRT_RESET_REQ__VF_MASK 0xffff +#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SEM_STATUS__SEM_IDLE_MASK 0x1 +#define SEM_STATUS__SEM_IDLE__SHIFT 0x0 +#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2 +#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 +#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4 +#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 +#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8 +#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 +#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10 +#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 +#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20 +#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 +#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40 +#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 +#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80 +#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 +#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100 +#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 +#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200 +#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 +#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400 +#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa +#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800 +#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb +#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000 +#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc +#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000 +#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd +#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000 +#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe +#define SEM_STATUS__SWITCH_READY_MASK 0x80000000 +#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f +#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000 +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf +#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000 +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 +#define SEM_MAILBOX__SIDEPORT_MASK 0xff +#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0 +#define SEM_MAILBOX__HOSTPORT_MASK 0xff00 +#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8 +#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000 +#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10 +#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000 +#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18 +#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1 +#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 +#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2 +#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 +#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4 +#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 +#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18 +#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 +#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00 +#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 +#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f +#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 +#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000 +#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10 +#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000 +#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11 +#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000 +#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12 +#define SRBM_GFX_CNTL__PIPEID_MASK 0x3 +#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0 +#define SRBM_GFX_CNTL__MEID_MASK 0xc +#define SRBM_GFX_CNTL__MEID__SHIFT 0x2 +#define SRBM_GFX_CNTL__VMID_MASK 0xf0 +#define SRBM_GFX_CNTL__VMID__SHIFT 0x4 +#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700 +#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 +#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff +#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1 +#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0 +#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2 +#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1 +#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4 +#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2 +#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8 +#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3 +#define SRBM_STATUS2__VP8_BUSY_MASK 0x10 +#define SRBM_STATUS2__VP8_BUSY__SHIFT 0x4 +#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20 +#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5 +#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40 +#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6 +#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80 +#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7 +#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100 +#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8 +#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200 +#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9 +#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400 +#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa +#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800 +#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb +#define SRBM_STATUS2__SAMSCP_BUSY_MASK 0x1000 +#define SRBM_STATUS2__SAMSCP_BUSY__SHIFT 0xc +#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000 +#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd +#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000 +#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe +#define SRBM_STATUS2__ODE_BUSY_MASK 0x8000 +#define SRBM_STATUS2__ODE_BUSY__SHIFT 0xf +#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000 +#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10 +#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000 +#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11 +#define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK 0x40000 +#define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT 0x12 +#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000 +#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13 +#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000 +#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14 +#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2 +#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1 +#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4 +#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2 +#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8 +#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3 +#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10 +#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4 +#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20 +#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5 +#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40 +#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6 +#define SRBM_STATUS__VMC_BUSY_MASK 0x100 +#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8 +#define SRBM_STATUS__MCB_BUSY_MASK 0x200 +#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9 +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400 +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa +#define SRBM_STATUS__MCC_BUSY_MASK 0x800 +#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb +#define SRBM_STATUS__MCD_BUSY_MASK 0x1000 +#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc +#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000 +#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd +#define SRBM_STATUS__SEM_BUSY_MASK 0x4000 +#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe +#define SRBM_STATUS__ACP_BUSY_MASK 0x10000 +#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10 +#define SRBM_STATUS__IH_BUSY_MASK 0x20000 +#define SRBM_STATUS__IH_BUSY__SHIFT 0x11 +#define SRBM_STATUS__UVD_BUSY_MASK 0x80000 +#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13 +#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000 +#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14 +#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000 +#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15 +#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000 +#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16 +#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000 +#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d +#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1 +#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0 +#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2 +#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1 +#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4 +#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2 +#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8 +#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3 +#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10 +#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4 +#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20 +#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5 +#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40 +#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6 +#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80 +#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7 +#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100 +#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8 +#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200 +#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9 +#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400 +#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa +#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800 +#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb +#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000 +#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc +#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000 +#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd +#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000 +#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe +#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000 +#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf +#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1 +#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0 +#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2 +#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3 +#define SRBM_SOFT_RESET__SOFT_RESET_GIONB_MASK 0x10 +#define SRBM_SOFT_RESET__SOFT_RESET_GIONB__SHIFT 0x4 +#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20 +#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6 +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100 +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8 +#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200 +#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9 +#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400 +#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa +#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800 +#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb +#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000 +#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc +#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000 +#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd +#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000 +#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe +#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000 +#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf +#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000 +#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10 +#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000 +#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11 +#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000 +#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12 +#define SRBM_SOFT_RESET__SOFT_RESET_VP8_MASK 0x80000 +#define SRBM_SOFT_RESET__SOFT_RESET_VP8__SHIFT 0x13 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14 +#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000 +#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15 +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000 +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16 +#define SRBM_SOFT_RESET__SOFT_RESET_ODE_MASK 0x800000 +#define SRBM_SOFT_RESET__SOFT_RESET_ODE__SHIFT 0x17 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18 +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000 +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19 +#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000 +#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a +#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000 +#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b +#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK 0x10000000 +#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT 0x1c +#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000 +#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d +#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000 +#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e +#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0 +#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff +#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0 +#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff +#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 +#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME_MASK 0xfff +#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME__SHIFT 0x0 +#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE_MASK 0x80000000 +#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE__SHIFT 0x1f +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF_MASK 0x1 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF__SHIFT 0x0 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU_MASK 0x2 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU__SHIFT 0x1 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC_MASK 0x4 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC__SHIFT 0x2 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB_MASK 0x8 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB__SHIFT 0x3 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP_MASK 0x10 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP__SHIFT 0x4 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA_MASK 0x20 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA__SHIFT 0x5 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE_MASK 0x40 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE__SHIFT 0x6 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB_MASK 0x80 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB__SHIFT 0x7 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8_MASK 0x100 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8__SHIFT 0x8 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM_MASK 0x200 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM__SHIFT 0x9 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD_MASK 0x400 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD__SHIFT 0xa +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0_MASK 0x800 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0__SHIFT 0xb +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1_MASK 0x1000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1__SHIFT 0xc +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP_MASK 0x2000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP__SHIFT 0xd +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM_MASK 0x4000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM__SHIFT 0xe +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB_MASK 0x8000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB__SHIFT 0xf +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0_MASK 0x10000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0__SHIFT 0x10 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1_MASK 0x20000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1__SHIFT 0x11 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2_MASK 0x40000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2__SHIFT 0x12 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3_MASK 0x80000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3__SHIFT 0x13 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4_MASK 0x100000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4__SHIFT 0x14 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5_MASK 0x200000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5__SHIFT 0x15 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6_MASK 0x400000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6__SHIFT 0x16 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7_MASK 0x800000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7__SHIFT 0x17 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0_MASK 0x1000000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0__SHIFT 0x18 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1_MASK 0x2000000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1__SHIFT 0x19 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2_MASK 0x4000000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2__SHIFT 0x1a +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3_MASK 0x8000000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3__SHIFT 0x1b +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4_MASK 0x10000000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4__SHIFT 0x1c +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5_MASK 0x20000000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5__SHIFT 0x1d +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6_MASK 0x40000000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6__SHIFT 0x1e +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7_MASK 0x80000000 +#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7__SHIFT 0x1f +#define SRBM_CREDIT_RESET__CREDIT_RESET_BIF_MASK 0x1 +#define SRBM_CREDIT_RESET__CREDIT_RESET_BIF__SHIFT 0x0 +#define SRBM_CREDIT_RESET__CREDIT_RESET_SMU_MASK 0x2 +#define SRBM_CREDIT_RESET__CREDIT_RESET_SMU__SHIFT 0x1 +#define SRBM_CREDIT_RESET__CREDIT_RESET_DC_MASK 0x4 +#define SRBM_CREDIT_RESET__CREDIT_RESET_DC__SHIFT 0x2 +#define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB_MASK 0x8 +#define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB__SHIFT 0x3 +#define SRBM_CREDIT_RESET__CREDIT_RESET_ACP_MASK 0x10 +#define SRBM_CREDIT_RESET__CREDIT_RESET_ACP__SHIFT 0x4 +#define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA_MASK 0x20 +#define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA__SHIFT 0x5 +#define SRBM_CREDIT_RESET__CREDIT_RESET_ODE_MASK 0x40 +#define SRBM_CREDIT_RESET__CREDIT_RESET_ODE__SHIFT 0x6 +#define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB_MASK 0x80 +#define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB__SHIFT 0x7 +#define SRBM_CREDIT_RESET__CREDIT_RESET_VP8_MASK 0x100 +#define SRBM_CREDIT_RESET__CREDIT_RESET_VP8__SHIFT 0x8 +#define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM_MASK 0x200 +#define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM__SHIFT 0x9 +#define SRBM_CREDIT_RESET__CREDIT_RESET_UVD_MASK 0x400 +#define SRBM_CREDIT_RESET__CREDIT_RESET_UVD__SHIFT 0xa +#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0_MASK 0x800 +#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0__SHIFT 0xb +#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1_MASK 0x1000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1__SHIFT 0xc +#define SRBM_CREDIT_RESET__CREDIT_RESET_ISP_MASK 0x2000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_ISP__SHIFT 0xd +#define SRBM_CREDIT_RESET__CREDIT_RESET_SAM_MASK 0x4000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_SAM__SHIFT 0xe +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCB_MASK 0x8000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCB__SHIFT 0xf +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0_MASK 0x10000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0__SHIFT 0x10 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1_MASK 0x20000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1__SHIFT 0x11 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2_MASK 0x40000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2__SHIFT 0x12 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3_MASK 0x80000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3__SHIFT 0x13 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4_MASK 0x100000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4__SHIFT 0x14 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5_MASK 0x200000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5__SHIFT 0x15 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6_MASK 0x400000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6__SHIFT 0x16 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7_MASK 0x800000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7__SHIFT 0x17 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0_MASK 0x1000000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0__SHIFT 0x18 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1_MASK 0x2000000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1__SHIFT 0x19 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2_MASK 0x4000000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2__SHIFT 0x1a +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3_MASK 0x8000000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3__SHIFT 0x1b +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4_MASK 0x10000000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4__SHIFT 0x1c +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5_MASK 0x20000000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5__SHIFT 0x1d +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6_MASK 0x40000000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6__SHIFT 0x1e +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7_MASK 0x80000000 +#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7__SHIFT 0x1f +#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 +#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 +#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1 +#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0 +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2 +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1 +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4 +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2 +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10 +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4 +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20 +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5 +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40 +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6 +#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80 +#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7 +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100 +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8 +#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200 +#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9 +#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400 +#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa +#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE_MASK 0x800 +#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xb +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1 +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0 +#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2 +#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1 +#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4 +#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2 +#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8 +#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3 +#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10 +#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4 +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20 +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5 +#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40 +#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6 +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80 +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7 +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100 +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8 +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200 +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9 +#define SRBM_DEBUG_SNAPSHOT__VP8_RDY_MASK 0x400 +#define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT 0xa +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800 +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb +#define SRBM_DEBUG_SNAPSHOT__ODE_RDY_MASK 0x1000 +#define SRBM_DEBUG_SNAPSHOT__ODE_RDY__SHIFT 0xc +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000 +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000 +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000 +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000 +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10 +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000 +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11 +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000 +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12 +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000 +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13 +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000 +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14 +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000 +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15 +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000 +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16 +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000 +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17 +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000 +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18 +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000 +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19 +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000 +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000 +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000 +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c +#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000 +#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d +#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK 0x40000000 +#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT 0x1e +#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000 +#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f +#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1 +#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0 +#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc +#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13 +#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000 +#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15 +#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000 +#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16 +#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000 +#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17 +#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000 +#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18 +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000 +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19 +#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000 +#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a +#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK 0x8000000 +#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT 0x1b +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c +#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000 +#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d +#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 +#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1 +#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0 +#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2 +#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1 +#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4 +#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2 +#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000 +#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17 +#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000 +#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18 +#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1 +#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0 +#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2 +#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1 +#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1 +#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0 +#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2 +#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1 +#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1 +#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0 +#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2 +#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK 0x4 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14 +#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000 +#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0 +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000 +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10 +#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff +#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0 +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0 +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000 +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10 +#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff +#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0 +#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf +#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0 +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0 +#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3 +#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff +#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 +#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf +#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0 +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0 +#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00 +#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8 +#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000 +#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10 +#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000 +#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000 +#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f +#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf +#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0 +#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3 +#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0 +#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc +#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2 +#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0 +#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4 +#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700 +#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8 +#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1 +#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1 +#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0 +#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff +#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 +#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c +#define DH_TEST__DH_TEST_MASK 0x1 +#define DH_TEST__DH_TEST__SHIFT 0x0 +#define KHFS0__RESERVED_MASK 0xffffffff +#define KHFS0__RESERVED__SHIFT 0x0 +#define KHFS1__RESERVED_MASK 0xffffffff +#define KHFS1__RESERVED__SHIFT 0x0 +#define KHFS2__RESERVED_MASK 0xffffffff +#define KHFS2__RESERVED__SHIFT 0x0 +#define KHFS3__RESERVED_MASK 0xffffffff +#define KHFS3__RESERVED__SHIFT 0x0 +#define KSESSION0__RESERVED_MASK 0xffffffff +#define KSESSION0__RESERVED__SHIFT 0x0 +#define KSESSION1__RESERVED_MASK 0xffffffff +#define KSESSION1__RESERVED__SHIFT 0x0 +#define KSESSION2__RESERVED_MASK 0xffffffff +#define KSESSION2__RESERVED__SHIFT 0x0 +#define KSESSION3__RESERVED_MASK 0xffffffff +#define KSESSION3__RESERVED__SHIFT 0x0 +#define KSIG0__RESERVED_MASK 0xffffffff +#define KSIG0__RESERVED__SHIFT 0x0 +#define KSIG1__RESERVED_MASK 0xffffffff +#define KSIG1__RESERVED__SHIFT 0x0 +#define KSIG2__RESERVED_MASK 0xffffffff +#define KSIG2__RESERVED__SHIFT 0x0 +#define KSIG3__RESERVED_MASK 0xffffffff +#define KSIG3__RESERVED__SHIFT 0x0 +#define EXP0__RESERVED_MASK 0xffffffff +#define EXP0__RESERVED__SHIFT 0x0 +#define EXP1__RESERVED_MASK 0xffffffff +#define EXP1__RESERVED__SHIFT 0x0 +#define EXP2__RESERVED_MASK 0xffffffff +#define EXP2__RESERVED__SHIFT 0x0 +#define EXP3__RESERVED_MASK 0xffffffff +#define EXP3__RESERVED__SHIFT 0x0 +#define EXP4__RESERVED_MASK 0xffffffff +#define EXP4__RESERVED__SHIFT 0x0 +#define EXP5__RESERVED_MASK 0xffffffff +#define EXP5__RESERVED__SHIFT 0x0 +#define EXP6__RESERVED_MASK 0xffffffff +#define EXP6__RESERVED__SHIFT 0x0 +#define EXP7__RESERVED_MASK 0xffffffff +#define EXP7__RESERVED__SHIFT 0x0 +#define LX0__RESERVED_MASK 0xffffffff +#define LX0__RESERVED__SHIFT 0x0 +#define LX1__RESERVED_MASK 0xffffffff +#define LX1__RESERVED__SHIFT 0x0 +#define LX2__RESERVED_MASK 0xffffffff +#define LX2__RESERVED__SHIFT 0x0 +#define LX3__RESERVED_MASK 0xffffffff +#define LX3__RESERVED__SHIFT 0x0 +#define CLIENT2_K0__RESERVED_MASK 0xffffffff +#define CLIENT2_K0__RESERVED__SHIFT 0x0 +#define CLIENT2_K1__RESERVED_MASK 0xffffffff +#define CLIENT2_K1__RESERVED__SHIFT 0x0 +#define CLIENT2_K2__RESERVED_MASK 0xffffffff +#define CLIENT2_K2__RESERVED__SHIFT 0x0 +#define CLIENT2_K3__RESERVED_MASK 0xffffffff +#define CLIENT2_K3__RESERVED__SHIFT 0x0 +#define CLIENT2_CK0__RESERVED_MASK 0xffffffff +#define CLIENT2_CK0__RESERVED__SHIFT 0x0 +#define CLIENT2_CK1__RESERVED_MASK 0xffffffff +#define CLIENT2_CK1__RESERVED__SHIFT 0x0 +#define CLIENT2_CK2__RESERVED_MASK 0xffffffff +#define CLIENT2_CK2__RESERVED__SHIFT 0x0 +#define CLIENT2_CK3__RESERVED_MASK 0xffffffff +#define CLIENT2_CK3__RESERVED__SHIFT 0x0 +#define CLIENT2_CD0__RESERVED_MASK 0xffffffff +#define CLIENT2_CD0__RESERVED__SHIFT 0x0 +#define CLIENT2_CD1__RESERVED_MASK 0xffffffff +#define CLIENT2_CD1__RESERVED__SHIFT 0x0 +#define CLIENT2_CD2__RESERVED_MASK 0xffffffff +#define CLIENT2_CD2__RESERVED__SHIFT 0x0 +#define CLIENT2_CD3__RESERVED_MASK 0xffffffff +#define CLIENT2_CD3__RESERVED__SHIFT 0x0 +#define CLIENT2_BM__RESERVED_MASK 0xffffffff +#define CLIENT2_BM__RESERVED__SHIFT 0x0 +#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffff +#define CLIENT2_OFFSET__RESERVED__SHIFT 0x0 +#define CLIENT2_STATUS__RESERVED_MASK 0xffffffff +#define CLIENT2_STATUS__RESERVED__SHIFT 0x0 +#define CLIENT0_K0__RESERVED_MASK 0xffffffff +#define CLIENT0_K0__RESERVED__SHIFT 0x0 +#define CLIENT0_K1__RESERVED_MASK 0xffffffff +#define CLIENT0_K1__RESERVED__SHIFT 0x0 +#define CLIENT0_K2__RESERVED_MASK 0xffffffff +#define CLIENT0_K2__RESERVED__SHIFT 0x0 +#define CLIENT0_K3__RESERVED_MASK 0xffffffff +#define CLIENT0_K3__RESERVED__SHIFT 0x0 +#define CLIENT0_CK0__RESERVED_MASK 0xffffffff +#define CLIENT0_CK0__RESERVED__SHIFT 0x0 +#define CLIENT0_CK1__RESERVED_MASK 0xffffffff +#define CLIENT0_CK1__RESERVED__SHIFT 0x0 +#define CLIENT0_CK2__RESERVED_MASK 0xffffffff +#define CLIENT0_CK2__RESERVED__SHIFT 0x0 +#define CLIENT0_CK3__RESERVED_MASK 0xffffffff +#define CLIENT0_CK3__RESERVED__SHIFT 0x0 +#define CLIENT0_CD0__RESERVED_MASK 0xffffffff +#define CLIENT0_CD0__RESERVED__SHIFT 0x0 +#define CLIENT0_CD1__RESERVED_MASK 0xffffffff +#define CLIENT0_CD1__RESERVED__SHIFT 0x0 +#define CLIENT0_CD2__RESERVED_MASK 0xffffffff +#define CLIENT0_CD2__RESERVED__SHIFT 0x0 +#define CLIENT0_CD3__RESERVED_MASK 0xffffffff +#define CLIENT0_CD3__RESERVED__SHIFT 0x0 +#define CLIENT0_BM__RESERVED_MASK 0xffffffff +#define CLIENT0_BM__RESERVED__SHIFT 0x0 +#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffff +#define CLIENT0_OFFSET__RESERVED__SHIFT 0x0 +#define CLIENT0_STATUS__RESERVED_MASK 0xffffffff +#define CLIENT0_STATUS__RESERVED__SHIFT 0x0 +#define CLIENT1_K0__RESERVED_MASK 0xffffffff +#define CLIENT1_K0__RESERVED__SHIFT 0x0 +#define CLIENT1_K1__RESERVED_MASK 0xffffffff +#define CLIENT1_K1__RESERVED__SHIFT 0x0 +#define CLIENT1_K2__RESERVED_MASK 0xffffffff +#define CLIENT1_K2__RESERVED__SHIFT 0x0 +#define CLIENT1_K3__RESERVED_MASK 0xffffffff +#define CLIENT1_K3__RESERVED__SHIFT 0x0 +#define CLIENT1_CK0__RESERVED_MASK 0xffffffff +#define CLIENT1_CK0__RESERVED__SHIFT 0x0 +#define CLIENT1_CK1__RESERVED_MASK 0xffffffff +#define CLIENT1_CK1__RESERVED__SHIFT 0x0 +#define CLIENT1_CK2__RESERVED_MASK 0xffffffff +#define CLIENT1_CK2__RESERVED__SHIFT 0x0 +#define CLIENT1_CK3__RESERVED_MASK 0xffffffff +#define CLIENT1_CK3__RESERVED__SHIFT 0x0 +#define CLIENT1_CD0__RESERVED_MASK 0xffffffff +#define CLIENT1_CD0__RESERVED__SHIFT 0x0 +#define CLIENT1_CD1__RESERVED_MASK 0xffffffff +#define CLIENT1_CD1__RESERVED__SHIFT 0x0 +#define CLIENT1_CD2__RESERVED_MASK 0xffffffff +#define CLIENT1_CD2__RESERVED__SHIFT 0x0 +#define CLIENT1_CD3__RESERVED_MASK 0xffffffff +#define CLIENT1_CD3__RESERVED__SHIFT 0x0 +#define CLIENT1_BM__RESERVED_MASK 0xffffffff +#define CLIENT1_BM__RESERVED__SHIFT 0x0 +#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffff +#define CLIENT1_OFFSET__RESERVED__SHIFT 0x0 +#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffff +#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x0 +#define KEFUSE0__RESERVED_MASK 0xffffffff +#define KEFUSE0__RESERVED__SHIFT 0x0 +#define KEFUSE1__RESERVED_MASK 0xffffffff +#define KEFUSE1__RESERVED__SHIFT 0x0 +#define KEFUSE2__RESERVED_MASK 0xffffffff +#define KEFUSE2__RESERVED__SHIFT 0x0 +#define KEFUSE3__RESERVED_MASK 0xffffffff +#define KEFUSE3__RESERVED__SHIFT 0x0 +#define HFS_SEED0__RESERVED_MASK 0xffffffff +#define HFS_SEED0__RESERVED__SHIFT 0x0 +#define HFS_SEED1__RESERVED_MASK 0xffffffff +#define HFS_SEED1__RESERVED__SHIFT 0x0 +#define HFS_SEED2__RESERVED_MASK 0xffffffff +#define HFS_SEED2__RESERVED__SHIFT 0x0 +#define HFS_SEED3__RESERVED_MASK 0xffffffff +#define HFS_SEED3__RESERVED__SHIFT 0x0 +#define RINGOSC_MASK__MASK_MASK 0xffff +#define RINGOSC_MASK__MASK__SHIFT 0x0 +#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffff +#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x0 +#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffff +#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x0 +#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffff +#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x0 +#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffff +#define SPU_PORT_STATUS__RESERVED__SHIFT 0x0 +#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffff +#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x0 +#define CLIENT3_K0__RESERVED_MASK 0xffffffff +#define CLIENT3_K0__RESERVED__SHIFT 0x0 +#define CLIENT3_K1__RESERVED_MASK 0xffffffff +#define CLIENT3_K1__RESERVED__SHIFT 0x0 +#define CLIENT3_K2__RESERVED_MASK 0xffffffff +#define CLIENT3_K2__RESERVED__SHIFT 0x0 +#define CLIENT3_K3__RESERVED_MASK 0xffffffff +#define CLIENT3_K3__RESERVED__SHIFT 0x0 +#define CLIENT3_CK0__RESERVED_MASK 0xffffffff +#define CLIENT3_CK0__RESERVED__SHIFT 0x0 +#define CLIENT3_CK1__RESERVED_MASK 0xffffffff +#define CLIENT3_CK1__RESERVED__SHIFT 0x0 +#define CLIENT3_CK2__RESERVED_MASK 0xffffffff +#define CLIENT3_CK2__RESERVED__SHIFT 0x0 +#define CLIENT3_CK3__RESERVED_MASK 0xffffffff +#define CLIENT3_CK3__RESERVED__SHIFT 0x0 +#define CLIENT3_CD0__RESERVED_MASK 0xffffffff +#define CLIENT3_CD0__RESERVED__SHIFT 0x0 +#define CLIENT3_CD1__RESERVED_MASK 0xffffffff +#define CLIENT3_CD1__RESERVED__SHIFT 0x0 +#define CLIENT3_CD2__RESERVED_MASK 0xffffffff +#define CLIENT3_CD2__RESERVED__SHIFT 0x0 +#define CLIENT3_CD3__RESERVED_MASK 0xffffffff +#define CLIENT3_CD3__RESERVED__SHIFT 0x0 +#define CLIENT3_BM__RESERVED_MASK 0xffffffff +#define CLIENT3_BM__RESERVED__SHIFT 0x0 +#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffff +#define CLIENT3_OFFSET__RESERVED__SHIFT 0x0 +#define CLIENT3_STATUS__RESERVED_MASK 0xffffffff +#define CLIENT3_STATUS__RESERVED__SHIFT 0x0 +#define CLIENT4_OFFSET_HI__RESERVED_MASK 0xffffffff +#define CLIENT4_OFFSET_HI__RESERVED__SHIFT 0x0 +#define CLIENT4_K0__RESERVED_MASK 0xffffffff +#define CLIENT4_K0__RESERVED__SHIFT 0x0 +#define CLIENT4_K1__RESERVED_MASK 0xffffffff +#define CLIENT4_K1__RESERVED__SHIFT 0x0 +#define CLIENT4_K2__RESERVED_MASK 0xffffffff +#define CLIENT4_K2__RESERVED__SHIFT 0x0 +#define CLIENT4_K3__RESERVED_MASK 0xffffffff +#define CLIENT4_K3__RESERVED__SHIFT 0x0 +#define CLIENT4_CK0__RESERVED_MASK 0xffffffff +#define CLIENT4_CK0__RESERVED__SHIFT 0x0 +#define CLIENT4_CK1__RESERVED_MASK 0xffffffff +#define CLIENT4_CK1__RESERVED__SHIFT 0x0 +#define CLIENT4_CK2__RESERVED_MASK 0xffffffff +#define CLIENT4_CK2__RESERVED__SHIFT 0x0 +#define CLIENT4_CK3__RESERVED_MASK 0xffffffff +#define CLIENT4_CK3__RESERVED__SHIFT 0x0 +#define CLIENT4_CD0__RESERVED_MASK 0xffffffff +#define CLIENT4_CD0__RESERVED__SHIFT 0x0 +#define CLIENT4_CD1__RESERVED_MASK 0xffffffff +#define CLIENT4_CD1__RESERVED__SHIFT 0x0 +#define CLIENT4_CD2__RESERVED_MASK 0xffffffff +#define CLIENT4_CD2__RESERVED__SHIFT 0x0 +#define CLIENT4_CD3__RESERVED_MASK 0xffffffff +#define CLIENT4_CD3__RESERVED__SHIFT 0x0 +#define CLIENT4_BM__RESERVED_MASK 0xffffffff +#define CLIENT4_BM__RESERVED__SHIFT 0x0 +#define CLIENT4_OFFSET__RESERVED_MASK 0xffffffff +#define CLIENT4_OFFSET__RESERVED__SHIFT 0x0 +#define CLIENT4_STATUS__RESERVED_MASK 0xffffffff +#define CLIENT4_STATUS__RESERVED__SHIFT 0x0 +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0xff +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x100 +#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffff +#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x0 +#define SDMA0_UCODE_ADDR__VALUE_MASK 0x1fff +#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff +#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf +#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1 +#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2 +#define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8 +#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 +#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 +#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 +#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7 +#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0 +#define SDMA0_HASH__BANK_BITS_MASK 0x70 +#define SDMA0_HASH__BANK_BITS__SHIFT 0x4 +#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700 +#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 +#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000 +#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc +#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc +#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff +#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_STATUS_REG__IDLE_MASK 0x1 +#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2 +#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4 +#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8 +#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10 +#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20 +#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40 +#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80 +#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100 +#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200 +#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400 +#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000 +#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000 +#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000 +#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 +#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000 +#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000 +#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 +#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 +#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000 +#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 +#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2 +#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20 +#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40 +#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 +#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 +#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000 +#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000 +#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x3 +#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc +#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 +#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 +#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_F32_CNTL__HALT_MASK 0x1 +#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA0_F32_CNTL__STEP_MASK 0x2 +#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc +#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define SDMA0_FREEZE__FREEZE_MASK 0x10 +#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA0_FREEZE__FROZEN_MASK 0x20 +#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40 +#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf +#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf +#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1 +#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2 +#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1 +#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4 +#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2 +#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30 +#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 +#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40 +#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6 +#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80 +#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7 +#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00 +#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8 +#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000 +#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14 +#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff +#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 +#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200 +#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400 +#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800 +#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000 +#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000 +#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 +#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff +#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff +#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 +#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA0_VM_CNTL__CMD_MASK 0xf +#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA0_VM_CTX_LO__ADDR_MASK 0xfffffffc +#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA0_VM_CTX_HI__ADDR_MASK 0xffffffff +#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA0_STATUS2_REG__ID_MASK 0x3 +#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc +#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 +#define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000 +#define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe +#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000 +#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0xf +#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000 +#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1 +#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA0_VM_CTX_CNTL__VMID_MASK 0xf0 +#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA0_VIRT_RESET_REQ__VF_MASK 0xffff +#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1 +#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff +#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 +#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA0_ID__DEVICE_ID_MASK 0xff +#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_VERSION__VALUE_MASK 0xffff +#define SDMA0_VERSION__VALUE__SHIFT 0x0 +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff +#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff +#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0xffff +#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0 +#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000 +#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL__SHIFT 0x0 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT_MASK 0x4 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2 +#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 +#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x4 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x8 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x10 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x100 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x200 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x400 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x800 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x1000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x2000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x4000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x8000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x10000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x20000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x40000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x80000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR_MASK 0x80 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL_MASK 0x100 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x200 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x400 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1_MASK 0x800 +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x1000 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x2000 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x4000 +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x8000 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x10000 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x20000 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x4 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x8 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x10 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x20 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x40 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80 +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x4 +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x8 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG_MASK 0x40 +#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH_MASK 0x80 +#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 +#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH_MASK 0x400 +#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH_MASK 0x800 +#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM_MASK 0x1000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG_MASK 0x2000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG_MASK 0x4000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL_MASK 0x8000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 +#define SDMA0_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 +#define SDMA0_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL_MASK 0x40000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE_MASK 0x80000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM_MASK 0x100000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM_MASK 0x200000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING_MASK 0x400000 +#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG_MASK 0x800000 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE_MASK 0x1000000 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ_MASK 0x2000000 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG_MASK 0x4000000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD_MASK 0x8000000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID_MASK 0x10000000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION_MASK 0x20000000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 +#define SDMA0_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI_MASK 0x4 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x8 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID_MASK 0x10 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL_MASK 0x20 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ_MASK 0x40 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE_MASK 0x80 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x100 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x200 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x400 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800 +#define SDMA0_PUB_REG_TYPE1__RESERVED__SHIFT 0xb +#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_GFX_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA0_GFX_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 +#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_UCODE_ADDR__VALUE_MASK 0x1fff +#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff +#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf +#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1 +#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2 +#define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8 +#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 +#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 +#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 +#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7 +#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0 +#define SDMA1_HASH__BANK_BITS_MASK 0x70 +#define SDMA1_HASH__BANK_BITS__SHIFT 0x4 +#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700 +#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 +#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000 +#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc +#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc +#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff +#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_STATUS_REG__IDLE_MASK 0x1 +#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2 +#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4 +#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8 +#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10 +#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20 +#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40 +#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80 +#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100 +#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200 +#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400 +#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000 +#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000 +#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000 +#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 +#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000 +#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000 +#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 +#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 +#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000 +#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 +#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 +#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20 +#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40 +#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 +#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 +#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000 +#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000 +#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x3 +#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc +#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 +#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 +#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_F32_CNTL__HALT_MASK 0x1 +#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA1_F32_CNTL__STEP_MASK 0x2 +#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc +#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define SDMA1_FREEZE__FREEZE_MASK 0x10 +#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA1_FREEZE__FROZEN_MASK 0x20 +#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40 +#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf +#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf +#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA1_VM_CNTL__CMD_MASK 0xf +#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA1_VM_CTX_LO__ADDR_MASK 0xfffffffc +#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA1_VM_CTX_HI__ADDR_MASK 0xffffffff +#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA1_STATUS2_REG__ID_MASK 0x3 +#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc +#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 +#define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000 +#define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe +#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000 +#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0xf +#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000 +#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1 +#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA1_VM_CTX_CNTL__VMID_MASK 0xf0 +#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA1_VIRT_RESET_REQ__VF_MASK 0xffff +#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1 +#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff +#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 +#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA1_ID__DEVICE_ID_MASK 0xff +#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA1_VERSION__VALUE_MASK 0xffff +#define SDMA1_VERSION__VALUE__SHIFT 0x0 +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff +#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff +#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0xffff +#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0 +#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000 +#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL__SHIFT 0x0 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT_MASK 0x4 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2 +#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 +#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x4 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x8 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x10 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x100 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x200 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x400 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x800 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x1000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x2000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x4000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x8000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x10000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x20000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x40000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x80000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA1_CONTEXT_REG_TYPE0__RESERVED_MASK 0xfff00000 +#define SDMA1_CONTEXT_REG_TYPE0__RESERVED__SHIFT 0x14 +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0_MASK 0x7f +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR_MASK 0x80 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL_MASK 0x100 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x200 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x400 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x800 +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x1000 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x2000 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3_MASK 0x4000 +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x8000 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x10000 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x20000 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x4 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x8 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x10 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x20 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x40 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80 +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x4 +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x8 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG_MASK 0x40 +#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH_MASK 0x80 +#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 +#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH_MASK 0x400 +#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH_MASK 0x800 +#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM_MASK 0x1000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG_MASK 0x2000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG_MASK 0x4000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL_MASK 0x8000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 +#define SDMA1_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 +#define SDMA1_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL_MASK 0x40000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE_MASK 0x80000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM_MASK 0x100000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM_MASK 0x200000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE0__VOID_REG0_MASK 0x3c00000 +#define SDMA1_PUB_REG_TYPE0__VOID_REG0__SHIFT 0x16 +#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG_MASK 0x4000000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD_MASK 0x8000000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID_MASK 0x10000000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION_MASK 0x20000000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 +#define SDMA1_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI_MASK 0x4 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x8 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID_MASK 0x10 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL_MASK 0x20 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ_MASK 0x40 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE_MASK 0x80 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x100 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x200 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x400 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800 +#define SDMA1_PUB_REG_TYPE1__RESERVED__SHIFT 0xb +#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_GFX_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA1_GFX_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 +#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7 +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0 +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8 +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3 +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600 +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000 +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16 +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000 +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17 +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000 +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000 +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000 +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f +#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff +#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0 +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1 +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0 +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1 +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60 +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5 +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380 +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd +#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000 +#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11 +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000 +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18 +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000 +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000 +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000 +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0 +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800 +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1 +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 +#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 +#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0 +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 +#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe +#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1 +#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30 +#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4 +#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0 +#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6 +#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700 +#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8 +#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800 +#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb +#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000 +#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7 +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0 +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18 +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3 +#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff +#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 +#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00 +#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 +#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1 +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 +#define HDP_MISC_CNTL__VM_ID_MASK 0x1e +#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1 +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20 +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 +#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40 +#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780 +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000 +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000 +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000 +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13 +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000 +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14 +#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000 +#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 +#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE_MASK 0x400000 +#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE__SHIFT 0x16 +#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE_MASK 0x800000 +#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE__SHIFT 0x17 +#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1 +#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 +#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e +#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1 +#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80 +#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b +#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1 +#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 +#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2 +#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 +#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c +#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000 +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000 +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf +#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x10000 +#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 +#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x1e0000 +#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 +#define HDP_VF_ENABLE__VF_EN_MASK 0x1 +#define HDP_VF_ENABLE__VF_EN__SHIFT 0x0 +#define HDP_VF_ENABLE__VF_NUM_MASK 0xffff0000 +#define HDP_VF_ENABLE__VF_NUM__SHIFT 0x10 +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 +#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18 +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f +#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 +#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff +#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 +#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff +#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 +#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000 +#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 +#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff +#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 +#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00 +#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 +#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000 +#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 +#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000 +#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 +#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff +#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0 +#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10 +#define HDP_XDP_DBG_DATA__STS_MASK 0xffff +#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0 +#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10 +#define HDP_XDP_DBG_MASK__STS_MASK 0xffff +#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0 +#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10 +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000 +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c + +#endif /* OSS_3_0_SH_MASK_H */ -- cgit v1.2.3 From a1ef4a8aa1498156da51a8b46a9a2477aac0fb01 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:27:02 -0400 Subject: drm/amdgpu: add OSS 3.0.1 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the OSS (OS Services) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h | 593 ++++ .../drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h | 1464 ++++++++ .../amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h | 3558 ++++++++++++++++++++ 3 files changed, 5615 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h new file mode 100644 index 000000000000..bdbb829c64fc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h @@ -0,0 +1,593 @@ +/* + * OSS_3_0_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_3_0_1_D_H +#define OSS_3_0_1_D_H + +#define mmIH_VMID_0_LUT 0xe00 +#define mmIH_VMID_1_LUT 0xe01 +#define mmIH_VMID_2_LUT 0xe02 +#define mmIH_VMID_3_LUT 0xe03 +#define mmIH_VMID_4_LUT 0xe04 +#define mmIH_VMID_5_LUT 0xe05 +#define mmIH_VMID_6_LUT 0xe06 +#define mmIH_VMID_7_LUT 0xe07 +#define mmIH_VMID_8_LUT 0xe08 +#define mmIH_VMID_9_LUT 0xe09 +#define mmIH_VMID_10_LUT 0xe0a +#define mmIH_VMID_11_LUT 0xe0b +#define mmIH_VMID_12_LUT 0xe0c +#define mmIH_VMID_13_LUT 0xe0d +#define mmIH_VMID_14_LUT 0xe0e +#define mmIH_VMID_15_LUT 0xe0f +#define mmIH_RB_CNTL 0xe30 +#define mmIH_RB_BASE 0xe31 +#define mmIH_RB_RPTR 0xe32 +#define mmIH_RB_WPTR 0xe33 +#define mmIH_RB_WPTR_ADDR_HI 0xe34 +#define mmIH_RB_WPTR_ADDR_LO 0xe35 +#define mmIH_CNTL 0xe36 +#define mmIH_LEVEL_STATUS 0xe37 +#define mmIH_STATUS 0xe38 +#define mmIH_PERFMON_CNTL 0xe39 +#define mmIH_PERFCOUNTER0_RESULT 0xe3a +#define mmIH_PERFCOUNTER1_RESULT 0xe3b +#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d +#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e +#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f +#define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40 +#define mmIH_DSM_MATCH_DATA_CONTROL 0xe41 +#define mmIH_VERSION 0xe48 +#define mmSEM_MCIF_CONFIG 0xf90 +#define mmSEM_PERFMON_CNTL 0xf91 +#define mmSEM_PERFCOUNTER0_RESULT 0xf92 +#define mmSEM_PERFCOUNTER1_RESULT 0xf93 +#define mmSEM_VF_ENABLE 0xf95 +#define mmSEM_ACTIVE_FCN_ID 0xf97 +#define mmSEM_VIRT_RESET_REQ 0xf98 +#define mmSEM_STATUS 0xf99 +#define mmSEM_EDC_CONFIG 0xf9a +#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b +#define mmSEM_MAILBOX 0xf9c +#define mmSEM_MAILBOX_CONTROL 0xf9d +#define mmSEM_CHICKEN_BITS 0xf9e +#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f +#define mmSRBM_CNTL 0x390 +#define mmSRBM_GFX_CNTL 0x391 +#define mmSRBM_READ_CNTL 0x392 +#define mmSRBM_STATUS2 0x393 +#define mmSRBM_STATUS 0x394 +#define mmSRBM_STATUS3 0x395 +#define mmSRBM_SOFT_RESET 0x398 +#define mmSRBM_DEBUG_CNTL 0x399 +#define mmSRBM_DEBUG_DATA 0x39a +#define mmSRBM_CHIP_REVISION 0x39b +#define mmCC_SYS_RB_REDUNDANCY 0x39f +#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0 +#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1 +#define mmSRBM_MC_CLKEN_CNTL 0x3b3 +#define mmSRBM_SYS_CLKEN_CNTL 0x3b4 +#define mmSRBM_VCE_CLKEN_CNTL 0x3b5 +#define mmSRBM_UVD_CLKEN_CNTL 0x3b6 +#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7 +#define mmSRBM_SAM_CLKEN_CNTL 0x3b8 +#define mmSRBM_ISP_CLKEN_CNTL 0x3b9 +#define mmSRBM_VP8_CLKEN_CNTL 0x3ba +#define mmSRBM_DEBUG 0x3a4 +#define mmSRBM_DEBUG_SNAPSHOT 0x3a5 +#define mmSRBM_DEBUG_SNAPSHOT2 0x3ad +#define mmSRBM_READ_ERROR 0x3a6 +#define mmSRBM_READ_ERROR2 0x3ae +#define mmSRBM_INT_CNTL 0x3a8 +#define mmSRBM_INT_STATUS 0x3a9 +#define mmSRBM_INT_ACK 0x3aa +#define mmSRBM_FIREWALL_ERROR_SRC 0x3ab +#define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac +#define mmSRBM_DSM_TRIG_CNTL0 0x3af +#define mmSRBM_DSM_TRIG_CNTL1 0x3b0 +#define mmSRBM_DSM_TRIG_MASK0 0x3b1 +#define mmSRBM_DSM_TRIG_MASK1 0x3b2 +#define mmSRBM_PERFMON_CNTL 0x7c00 +#define mmSRBM_PERFCOUNTER0_SELECT 0x7c01 +#define mmSRBM_PERFCOUNTER1_SELECT 0x7c02 +#define mmSRBM_PERFCOUNTER0_LO 0x7c03 +#define mmSRBM_PERFCOUNTER0_HI 0x7c04 +#define mmSRBM_PERFCOUNTER1_LO 0x7c05 +#define mmSRBM_PERFCOUNTER1_HI 0x7c06 +#define mmSRBM_CAM_INDEX 0xfe34 +#define mmSRBM_CAM_DATA 0xfe35 +#define mmSRBM_MC_DOMAIN_ADDR0 0xfa00 +#define mmSRBM_MC_DOMAIN_ADDR1 0xfa01 +#define mmSRBM_MC_DOMAIN_ADDR2 0xfa02 +#define mmSRBM_MC_DOMAIN_ADDR3 0xfa03 +#define mmSRBM_MC_DOMAIN_ADDR4 0xfa04 +#define mmSRBM_MC_DOMAIN_ADDR5 0xfa05 +#define mmSRBM_MC_DOMAIN_ADDR6 0xfa06 +#define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08 +#define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09 +#define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a +#define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b +#define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c +#define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d +#define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e +#define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10 +#define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11 +#define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12 +#define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13 +#define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14 +#define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15 +#define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16 +#define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18 +#define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19 +#define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a +#define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20 +#define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21 +#define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22 +#define mmSRBM_VP8_DOMAIN_ADDR0 0xfa24 +#define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c +#define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d +#define mmSRBM_GFX_CNTL_SELECT 0xfa2e +#define mmSRBM_GFX_CNTL_DATA 0xfa2f +#define mmSRBM_VF_ENABLE 0xfa30 +#define mmSRBM_VIRT_CNTL 0xfa31 +#define mmSRBM_VIRT_RESET_REQ 0xfa32 +#define mmSDMA0_UCODE_ADDR 0x3400 +#define mmSDMA0_UCODE_DATA 0x3401 +#define mmSDMA0_POWER_CNTL 0x3402 +#define mmSDMA0_CLK_CTRL 0x3403 +#define mmSDMA0_CNTL 0x3404 +#define mmSDMA0_CHICKEN_BITS 0x3405 +#define mmSDMA0_TILING_CONFIG 0x3406 +#define mmSDMA0_HASH 0x3407 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 +#define mmSDMA0_RB_RPTR_FETCH 0x340a +#define mmSDMA0_IB_OFFSET_FETCH 0x340b +#define mmSDMA0_PROGRAM 0x340c +#define mmSDMA0_STATUS_REG 0x340d +#define mmSDMA0_STATUS1_REG 0x340e +#define mmSDMA0_RD_BURST_CNTL 0x340f +#define mmSDMA0_PERFMON_CNTL 0x9000 +#define mmSDMA0_PERFCOUNTER0_RESULT 0x9001 +#define mmSDMA0_PERFCOUNTER1_RESULT 0x9002 +#define mmSDMA0_F32_CNTL 0x3412 +#define mmSDMA0_FREEZE 0x3413 +#define mmSDMA0_PHASE0_QUANTUM 0x3414 +#define mmSDMA0_PHASE1_QUANTUM 0x3415 +#define mmSDMA_POWER_GATING 0x3416 +#define mmSDMA_PGFSM_CONFIG 0x3417 +#define mmSDMA_PGFSM_WRITE 0x3418 +#define mmSDMA_PGFSM_READ 0x3419 +#define mmSDMA0_EDC_CONFIG 0x341a +#define mmSDMA0_BA_THRESHOLD 0x341b +#define mmSDMA0_ID 0x341c +#define mmSDMA0_VERSION 0x341d +#define mmSDMA0_VM_CNTL 0x3420 +#define mmSDMA0_VM_CTX_LO 0x3421 +#define mmSDMA0_VM_CTX_HI 0x3422 +#define mmSDMA0_STATUS2_REG 0x3423 +#define mmSDMA0_ACTIVE_FCN_ID 0x3424 +#define mmSDMA0_VM_CTX_CNTL 0x3425 +#define mmSDMA0_VIRT_RESET_REQ 0x3426 +#define mmSDMA0_VF_ENABLE 0x3427 +#define mmSDMA0_ATOMIC_CNTL 0x3428 +#define mmSDMA0_ATOMIC_PREOP_LO 0x3429 +#define mmSDMA0_ATOMIC_PREOP_HI 0x342a +#define mmSDMA0_ATCL1_CNTL 0x342b +#define mmSDMA0_ATCL1_WATERMK 0x342c +#define mmSDMA0_ATCL1_RD_STATUS 0x342d +#define mmSDMA0_ATCL1_WR_STATUS 0x342e +#define mmSDMA0_ATCL1_INV0 0x342f +#define mmSDMA0_ATCL1_INV1 0x3430 +#define mmSDMA0_ATCL1_INV2 0x3431 +#define mmSDMA0_ATCL1_RD_XNACK0 0x3432 +#define mmSDMA0_ATCL1_RD_XNACK1 0x3433 +#define mmSDMA0_ATCL1_WR_XNACK0 0x3434 +#define mmSDMA0_ATCL1_WR_XNACK1 0x3435 +#define mmSDMA0_ATCL1_TIMEOUT 0x3436 +#define mmSDMA0_POWER_CNTL_IDLE 0x3438 +#define mmSDMA0_PERF_REG_TYPE0 0x3477 +#define mmSDMA0_CONTEXT_REG_TYPE0 0x3478 +#define mmSDMA0_CONTEXT_REG_TYPE1 0x3479 +#define mmSDMA0_CONTEXT_REG_TYPE2 0x347a +#define mmSDMA0_PUB_REG_TYPE0 0x347c +#define mmSDMA0_PUB_REG_TYPE1 0x347d +#define mmSDMA0_GFX_RB_CNTL 0x3480 +#define mmSDMA0_GFX_RB_BASE 0x3481 +#define mmSDMA0_GFX_RB_BASE_HI 0x3482 +#define mmSDMA0_GFX_RB_RPTR 0x3483 +#define mmSDMA0_GFX_RB_WPTR 0x3484 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489 +#define mmSDMA0_GFX_IB_CNTL 0x348a +#define mmSDMA0_GFX_IB_RPTR 0x348b +#define mmSDMA0_GFX_IB_OFFSET 0x348c +#define mmSDMA0_GFX_IB_BASE_LO 0x348d +#define mmSDMA0_GFX_IB_BASE_HI 0x348e +#define mmSDMA0_GFX_IB_SIZE 0x348f +#define mmSDMA0_GFX_SKIP_CNTL 0x3490 +#define mmSDMA0_GFX_CONTEXT_STATUS 0x3491 +#define mmSDMA0_GFX_DOORBELL 0x3492 +#define mmSDMA0_GFX_CONTEXT_CNTL 0x3493 +#define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7 +#define mmSDMA0_GFX_APE1_CNTL 0x34a8 +#define mmSDMA0_GFX_DOORBELL_LOG 0x34a9 +#define mmSDMA0_GFX_WATERMARK 0x34aa +#define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac +#define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad +#define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af +#define mmSDMA0_GFX_PREEMPT 0x34b0 +#define mmSDMA0_GFX_DUMMY_REG 0x34b1 +#define mmSDMA0_GFX_MIDCMD_DATA0 0x34c1 +#define mmSDMA0_GFX_MIDCMD_DATA1 0x34c2 +#define mmSDMA0_GFX_MIDCMD_DATA2 0x34c3 +#define mmSDMA0_GFX_MIDCMD_DATA3 0x34c4 +#define mmSDMA0_GFX_MIDCMD_DATA4 0x34c5 +#define mmSDMA0_GFX_MIDCMD_DATA5 0x34c6 +#define mmSDMA0_GFX_MIDCMD_DATA6 0x34c7 +#define mmSDMA0_GFX_MIDCMD_DATA7 0x34c8 +#define mmSDMA0_GFX_MIDCMD_DATA8 0x34c9 +#define mmSDMA0_GFX_MIDCMD_CNTL 0x34ca +#define mmSDMA0_RLC0_RB_CNTL 0x3500 +#define mmSDMA0_RLC0_RB_BASE 0x3501 +#define mmSDMA0_RLC0_RB_BASE_HI 0x3502 +#define mmSDMA0_RLC0_RB_RPTR 0x3503 +#define mmSDMA0_RLC0_RB_WPTR 0x3504 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509 +#define mmSDMA0_RLC0_IB_CNTL 0x350a +#define mmSDMA0_RLC0_IB_RPTR 0x350b +#define mmSDMA0_RLC0_IB_OFFSET 0x350c +#define mmSDMA0_RLC0_IB_BASE_LO 0x350d +#define mmSDMA0_RLC0_IB_BASE_HI 0x350e +#define mmSDMA0_RLC0_IB_SIZE 0x350f +#define mmSDMA0_RLC0_SKIP_CNTL 0x3510 +#define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511 +#define mmSDMA0_RLC0_DOORBELL 0x3512 +#define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527 +#define mmSDMA0_RLC0_APE1_CNTL 0x3528 +#define mmSDMA0_RLC0_DOORBELL_LOG 0x3529 +#define mmSDMA0_RLC0_WATERMARK 0x352a +#define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c +#define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d +#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f +#define mmSDMA0_RLC0_PREEMPT 0x3530 +#define mmSDMA0_RLC0_DUMMY_REG 0x3531 +#define mmSDMA0_RLC0_MIDCMD_DATA0 0x3541 +#define mmSDMA0_RLC0_MIDCMD_DATA1 0x3542 +#define mmSDMA0_RLC0_MIDCMD_DATA2 0x3543 +#define mmSDMA0_RLC0_MIDCMD_DATA3 0x3544 +#define mmSDMA0_RLC0_MIDCMD_DATA4 0x3545 +#define mmSDMA0_RLC0_MIDCMD_DATA5 0x3546 +#define mmSDMA0_RLC0_MIDCMD_DATA6 0x3547 +#define mmSDMA0_RLC0_MIDCMD_DATA7 0x3548 +#define mmSDMA0_RLC0_MIDCMD_DATA8 0x3549 +#define mmSDMA0_RLC0_MIDCMD_CNTL 0x354a +#define mmSDMA0_RLC1_RB_CNTL 0x3580 +#define mmSDMA0_RLC1_RB_BASE 0x3581 +#define mmSDMA0_RLC1_RB_BASE_HI 0x3582 +#define mmSDMA0_RLC1_RB_RPTR 0x3583 +#define mmSDMA0_RLC1_RB_WPTR 0x3584 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589 +#define mmSDMA0_RLC1_IB_CNTL 0x358a +#define mmSDMA0_RLC1_IB_RPTR 0x358b +#define mmSDMA0_RLC1_IB_OFFSET 0x358c +#define mmSDMA0_RLC1_IB_BASE_LO 0x358d +#define mmSDMA0_RLC1_IB_BASE_HI 0x358e +#define mmSDMA0_RLC1_IB_SIZE 0x358f +#define mmSDMA0_RLC1_SKIP_CNTL 0x3590 +#define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591 +#define mmSDMA0_RLC1_DOORBELL 0x3592 +#define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7 +#define mmSDMA0_RLC1_APE1_CNTL 0x35a8 +#define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9 +#define mmSDMA0_RLC1_WATERMARK 0x35aa +#define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac +#define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad +#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af +#define mmSDMA0_RLC1_PREEMPT 0x35b0 +#define mmSDMA0_RLC1_DUMMY_REG 0x35b1 +#define mmSDMA0_RLC1_MIDCMD_DATA0 0x35c1 +#define mmSDMA0_RLC1_MIDCMD_DATA1 0x35c2 +#define mmSDMA0_RLC1_MIDCMD_DATA2 0x35c3 +#define mmSDMA0_RLC1_MIDCMD_DATA3 0x35c4 +#define mmSDMA0_RLC1_MIDCMD_DATA4 0x35c5 +#define mmSDMA0_RLC1_MIDCMD_DATA5 0x35c6 +#define mmSDMA0_RLC1_MIDCMD_DATA6 0x35c7 +#define mmSDMA0_RLC1_MIDCMD_DATA7 0x35c8 +#define mmSDMA0_RLC1_MIDCMD_DATA8 0x35c9 +#define mmSDMA0_RLC1_MIDCMD_CNTL 0x35ca +#define mmSDMA1_UCODE_ADDR 0x3600 +#define mmSDMA1_UCODE_DATA 0x3601 +#define mmSDMA1_POWER_CNTL 0x3602 +#define mmSDMA1_CLK_CTRL 0x3603 +#define mmSDMA1_CNTL 0x3604 +#define mmSDMA1_CHICKEN_BITS 0x3605 +#define mmSDMA1_TILING_CONFIG 0x3606 +#define mmSDMA1_HASH 0x3607 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609 +#define mmSDMA1_RB_RPTR_FETCH 0x360a +#define mmSDMA1_IB_OFFSET_FETCH 0x360b +#define mmSDMA1_PROGRAM 0x360c +#define mmSDMA1_STATUS_REG 0x360d +#define mmSDMA1_STATUS1_REG 0x360e +#define mmSDMA1_RD_BURST_CNTL 0x360f +#define mmSDMA1_PERFMON_CNTL 0x9010 +#define mmSDMA1_PERFCOUNTER0_RESULT 0x9011 +#define mmSDMA1_PERFCOUNTER1_RESULT 0x9012 +#define mmSDMA1_F32_CNTL 0x3612 +#define mmSDMA1_FREEZE 0x3613 +#define mmSDMA1_PHASE0_QUANTUM 0x3614 +#define mmSDMA1_PHASE1_QUANTUM 0x3615 +#define mmSDMA1_EDC_CONFIG 0x361a +#define mmSDMA1_BA_THRESHOLD 0x361b +#define mmSDMA1_ID 0x361c +#define mmSDMA1_VERSION 0x361d +#define mmSDMA1_VM_CNTL 0x3620 +#define mmSDMA1_VM_CTX_LO 0x3621 +#define mmSDMA1_VM_CTX_HI 0x3622 +#define mmSDMA1_STATUS2_REG 0x3623 +#define mmSDMA1_ACTIVE_FCN_ID 0x3624 +#define mmSDMA1_VM_CTX_CNTL 0x3625 +#define mmSDMA1_VIRT_RESET_REQ 0x3626 +#define mmSDMA1_VF_ENABLE 0x3627 +#define mmSDMA1_ATOMIC_CNTL 0x3628 +#define mmSDMA1_ATOMIC_PREOP_LO 0x3629 +#define mmSDMA1_ATOMIC_PREOP_HI 0x362a +#define mmSDMA1_ATCL1_CNTL 0x362b +#define mmSDMA1_ATCL1_WATERMK 0x362c +#define mmSDMA1_ATCL1_RD_STATUS 0x362d +#define mmSDMA1_ATCL1_WR_STATUS 0x362e +#define mmSDMA1_ATCL1_INV0 0x362f +#define mmSDMA1_ATCL1_INV1 0x3630 +#define mmSDMA1_ATCL1_INV2 0x3631 +#define mmSDMA1_ATCL1_RD_XNACK0 0x3632 +#define mmSDMA1_ATCL1_RD_XNACK1 0x3633 +#define mmSDMA1_ATCL1_WR_XNACK0 0x3634 +#define mmSDMA1_ATCL1_WR_XNACK1 0x3635 +#define mmSDMA1_ATCL1_TIMEOUT 0x3636 +#define mmSDMA1_POWER_CNTL_IDLE 0x3638 +#define mmSDMA1_PERF_REG_TYPE0 0x3677 +#define mmSDMA1_CONTEXT_REG_TYPE0 0x3678 +#define mmSDMA1_CONTEXT_REG_TYPE1 0x3679 +#define mmSDMA1_CONTEXT_REG_TYPE2 0x367a +#define mmSDMA1_PUB_REG_TYPE0 0x367c +#define mmSDMA1_PUB_REG_TYPE1 0x367d +#define mmSDMA1_GFX_RB_CNTL 0x3680 +#define mmSDMA1_GFX_RB_BASE 0x3681 +#define mmSDMA1_GFX_RB_BASE_HI 0x3682 +#define mmSDMA1_GFX_RB_RPTR 0x3683 +#define mmSDMA1_GFX_RB_WPTR 0x3684 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689 +#define mmSDMA1_GFX_IB_CNTL 0x368a +#define mmSDMA1_GFX_IB_RPTR 0x368b +#define mmSDMA1_GFX_IB_OFFSET 0x368c +#define mmSDMA1_GFX_IB_BASE_LO 0x368d +#define mmSDMA1_GFX_IB_BASE_HI 0x368e +#define mmSDMA1_GFX_IB_SIZE 0x368f +#define mmSDMA1_GFX_SKIP_CNTL 0x3690 +#define mmSDMA1_GFX_CONTEXT_STATUS 0x3691 +#define mmSDMA1_GFX_DOORBELL 0x3692 +#define mmSDMA1_GFX_CONTEXT_CNTL 0x3693 +#define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7 +#define mmSDMA1_GFX_APE1_CNTL 0x36a8 +#define mmSDMA1_GFX_DOORBELL_LOG 0x36a9 +#define mmSDMA1_GFX_WATERMARK 0x36aa +#define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac +#define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad +#define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af +#define mmSDMA1_GFX_PREEMPT 0x36b0 +#define mmSDMA1_GFX_DUMMY_REG 0x36b1 +#define mmSDMA1_GFX_MIDCMD_DATA0 0x36c1 +#define mmSDMA1_GFX_MIDCMD_DATA1 0x36c2 +#define mmSDMA1_GFX_MIDCMD_DATA2 0x36c3 +#define mmSDMA1_GFX_MIDCMD_DATA3 0x36c4 +#define mmSDMA1_GFX_MIDCMD_DATA4 0x36c5 +#define mmSDMA1_GFX_MIDCMD_DATA5 0x36c6 +#define mmSDMA1_GFX_MIDCMD_DATA6 0x36c7 +#define mmSDMA1_GFX_MIDCMD_DATA7 0x36c8 +#define mmSDMA1_GFX_MIDCMD_DATA8 0x36c9 +#define mmSDMA1_GFX_MIDCMD_CNTL 0x36ca +#define mmSDMA1_RLC0_RB_CNTL 0x3700 +#define mmSDMA1_RLC0_RB_BASE 0x3701 +#define mmSDMA1_RLC0_RB_BASE_HI 0x3702 +#define mmSDMA1_RLC0_RB_RPTR 0x3703 +#define mmSDMA1_RLC0_RB_WPTR 0x3704 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709 +#define mmSDMA1_RLC0_IB_CNTL 0x370a +#define mmSDMA1_RLC0_IB_RPTR 0x370b +#define mmSDMA1_RLC0_IB_OFFSET 0x370c +#define mmSDMA1_RLC0_IB_BASE_LO 0x370d +#define mmSDMA1_RLC0_IB_BASE_HI 0x370e +#define mmSDMA1_RLC0_IB_SIZE 0x370f +#define mmSDMA1_RLC0_SKIP_CNTL 0x3710 +#define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711 +#define mmSDMA1_RLC0_DOORBELL 0x3712 +#define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727 +#define mmSDMA1_RLC0_APE1_CNTL 0x3728 +#define mmSDMA1_RLC0_DOORBELL_LOG 0x3729 +#define mmSDMA1_RLC0_WATERMARK 0x372a +#define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c +#define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d +#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f +#define mmSDMA1_RLC0_PREEMPT 0x3730 +#define mmSDMA1_RLC0_DUMMY_REG 0x3731 +#define mmSDMA1_RLC0_MIDCMD_DATA0 0x3741 +#define mmSDMA1_RLC0_MIDCMD_DATA1 0x3742 +#define mmSDMA1_RLC0_MIDCMD_DATA2 0x3743 +#define mmSDMA1_RLC0_MIDCMD_DATA3 0x3744 +#define mmSDMA1_RLC0_MIDCMD_DATA4 0x3745 +#define mmSDMA1_RLC0_MIDCMD_DATA5 0x3746 +#define mmSDMA1_RLC0_MIDCMD_DATA6 0x3747 +#define mmSDMA1_RLC0_MIDCMD_DATA7 0x3748 +#define mmSDMA1_RLC0_MIDCMD_DATA8 0x3749 +#define mmSDMA1_RLC0_MIDCMD_CNTL 0x374a +#define mmSDMA1_RLC1_RB_CNTL 0x3780 +#define mmSDMA1_RLC1_RB_BASE 0x3781 +#define mmSDMA1_RLC1_RB_BASE_HI 0x3782 +#define mmSDMA1_RLC1_RB_RPTR 0x3783 +#define mmSDMA1_RLC1_RB_WPTR 0x3784 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789 +#define mmSDMA1_RLC1_IB_CNTL 0x378a +#define mmSDMA1_RLC1_IB_RPTR 0x378b +#define mmSDMA1_RLC1_IB_OFFSET 0x378c +#define mmSDMA1_RLC1_IB_BASE_LO 0x378d +#define mmSDMA1_RLC1_IB_BASE_HI 0x378e +#define mmSDMA1_RLC1_IB_SIZE 0x378f +#define mmSDMA1_RLC1_SKIP_CNTL 0x3790 +#define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791 +#define mmSDMA1_RLC1_DOORBELL 0x3792 +#define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7 +#define mmSDMA1_RLC1_APE1_CNTL 0x37a8 +#define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9 +#define mmSDMA1_RLC1_WATERMARK 0x37aa +#define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac +#define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad +#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af +#define mmSDMA1_RLC1_PREEMPT 0x37b0 +#define mmSDMA1_RLC1_DUMMY_REG 0x37b1 +#define mmSDMA1_RLC1_MIDCMD_DATA0 0x37c1 +#define mmSDMA1_RLC1_MIDCMD_DATA1 0x37c2 +#define mmSDMA1_RLC1_MIDCMD_DATA2 0x37c3 +#define mmSDMA1_RLC1_MIDCMD_DATA3 0x37c4 +#define mmSDMA1_RLC1_MIDCMD_DATA4 0x37c5 +#define mmSDMA1_RLC1_MIDCMD_DATA5 0x37c6 +#define mmSDMA1_RLC1_MIDCMD_DATA6 0x37c7 +#define mmSDMA1_RLC1_MIDCMD_DATA7 0x37c8 +#define mmSDMA1_RLC1_MIDCMD_DATA8 0x37c9 +#define mmSDMA1_RLC1_MIDCMD_CNTL 0x37ca +#define mmHDP_HOST_PATH_CNTL 0xb00 +#define mmHDP_NONSURFACE_BASE 0xb01 +#define mmHDP_NONSURFACE_INFO 0xb02 +#define mmHDP_NONSURFACE_SIZE 0xb03 +#define mmHDP_NONSURF_FLAGS 0xbc9 +#define mmHDP_NONSURF_FLAGS_CLR 0xbca +#define mmHDP_SW_SEMAPHORE 0xbcb +#define mmHDP_DEBUG0 0xbcc +#define mmHDP_DEBUG1 0xbcd +#define mmHDP_LAST_SURFACE_HIT 0xbce +#define mmHDP_TILING_CONFIG 0xbcf +#define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0 +#define mmHDP_OUTSTANDING_REQ 0xbd1 +#define mmHDP_ADDR_CONFIG 0xbd2 +#define mmHDP_MISC_CNTL 0xbd3 +#define mmHDP_MEM_POWER_LS 0xbd4 +#define mmHDP_NONSURFACE_PREFETCH 0xbd5 +#define mmHDP_MEMIO_CNTL 0xbf6 +#define mmHDP_MEMIO_ADDR 0xbf7 +#define mmHDP_MEMIO_STATUS 0xbf8 +#define mmHDP_MEMIO_WR_DATA 0xbf9 +#define mmHDP_MEMIO_RD_DATA 0xbfa +#define mmHDP_VF_ENABLE 0xbfb +#define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00 +#define mmHDP_XDP_D2H_FLUSH 0xc01 +#define mmHDP_XDP_D2H_BAR_UPDATE 0xc02 +#define mmHDP_XDP_D2H_RSVD_3 0xc03 +#define mmHDP_XDP_D2H_RSVD_4 0xc04 +#define mmHDP_XDP_D2H_RSVD_5 0xc05 +#define mmHDP_XDP_D2H_RSVD_6 0xc06 +#define mmHDP_XDP_D2H_RSVD_7 0xc07 +#define mmHDP_XDP_D2H_RSVD_8 0xc08 +#define mmHDP_XDP_D2H_RSVD_9 0xc09 +#define mmHDP_XDP_D2H_RSVD_10 0xc0a +#define mmHDP_XDP_D2H_RSVD_11 0xc0b +#define mmHDP_XDP_D2H_RSVD_12 0xc0c +#define mmHDP_XDP_D2H_RSVD_13 0xc0d +#define mmHDP_XDP_D2H_RSVD_14 0xc0e +#define mmHDP_XDP_D2H_RSVD_15 0xc0f +#define mmHDP_XDP_D2H_RSVD_16 0xc10 +#define mmHDP_XDP_D2H_RSVD_17 0xc11 +#define mmHDP_XDP_D2H_RSVD_18 0xc12 +#define mmHDP_XDP_D2H_RSVD_19 0xc13 +#define mmHDP_XDP_D2H_RSVD_20 0xc14 +#define mmHDP_XDP_D2H_RSVD_21 0xc15 +#define mmHDP_XDP_D2H_RSVD_22 0xc16 +#define mmHDP_XDP_D2H_RSVD_23 0xc17 +#define mmHDP_XDP_D2H_RSVD_24 0xc18 +#define mmHDP_XDP_D2H_RSVD_25 0xc19 +#define mmHDP_XDP_D2H_RSVD_26 0xc1a +#define mmHDP_XDP_D2H_RSVD_27 0xc1b +#define mmHDP_XDP_D2H_RSVD_28 0xc1c +#define mmHDP_XDP_D2H_RSVD_29 0xc1d +#define mmHDP_XDP_D2H_RSVD_30 0xc1e +#define mmHDP_XDP_D2H_RSVD_31 0xc1f +#define mmHDP_XDP_D2H_RSVD_32 0xc20 +#define mmHDP_XDP_D2H_RSVD_33 0xc21 +#define mmHDP_XDP_D2H_RSVD_34 0xc22 +#define mmHDP_XDP_DIRECT2HDP_LAST 0xc23 +#define mmHDP_XDP_P2P_BAR_CFG 0xc24 +#define mmHDP_XDP_P2P_MBX_OFFSET 0xc25 +#define mmHDP_XDP_P2P_MBX_ADDR0 0xc26 +#define mmHDP_XDP_P2P_MBX_ADDR1 0xc27 +#define mmHDP_XDP_P2P_MBX_ADDR2 0xc28 +#define mmHDP_XDP_P2P_MBX_ADDR3 0xc29 +#define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a +#define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b +#define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c +#define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d +#define mmHDP_XDP_HDP_MC_CFG 0xc2e +#define mmHDP_XDP_HST_CFG 0xc2f +#define mmHDP_XDP_SID_CFG 0xc30 +#define mmHDP_XDP_HDP_IPH_CFG 0xc31 +#define mmHDP_XDP_SRBM_CFG 0xc32 +#define mmHDP_XDP_CGTT_BLK_CTRL 0xc33 +#define mmHDP_XDP_P2P_BAR0 0xc34 +#define mmHDP_XDP_P2P_BAR1 0xc35 +#define mmHDP_XDP_P2P_BAR2 0xc36 +#define mmHDP_XDP_P2P_BAR3 0xc37 +#define mmHDP_XDP_P2P_BAR4 0xc38 +#define mmHDP_XDP_P2P_BAR5 0xc39 +#define mmHDP_XDP_P2P_BAR6 0xc3a +#define mmHDP_XDP_P2P_BAR7 0xc3b +#define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c +#define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d +#define mmHDP_XDP_BUSY_STS 0xc3e +#define mmHDP_XDP_STICKY 0xc3f +#define mmHDP_XDP_CHKN 0xc40 +#define mmHDP_XDP_DBG_ADDR 0xc41 +#define mmHDP_XDP_DBG_DATA 0xc42 +#define mmHDP_XDP_DBG_MASK 0xc43 +#define mmHDP_XDP_BARS_ADDR_39_36 0xc44 + +#endif /* OSS_3_0_1_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h new file mode 100644 index 000000000000..627cff10fcce --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h @@ -0,0 +1,1464 @@ +/* + * OSS_3_0_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_3_0_1_ENUM_H +#define OSS_3_0_1_ENUM_H + +typedef enum IH_CLIENT_ID { + DC_IH_SRC_ID_START = 0x1, + DC_IH_SRC_ID_END = 0x1f, + VGA_IH_SRC_ID_START = 0x20, + VGA_IH_SRC_ID_END = 0x27, + CAP_IH_SRC_ID_START = 0x28, + CAP_IH_SRC_ID_END = 0x2f, + VIP_IH_SRC_ID_START = 0x30, + VIP_IH_SRC_ID_END = 0x3f, + ROM_IH_SRC_ID_START = 0x40, + ROM_IH_SRC_ID_END = 0x5d, + BIF_IH_SRC_ID_START = 0x5e, + SAM_IH_SRC_ID_START = 0x5f, + SRBM_IH_SRC_ID_START = 0x60, + SRBM_IH_SRC_ID_END = 0x67, + UVD_IH_SRC_ID_START = 0x72, + UVD_IH_SRC_ID_END = 0x85, + VMC_IH_SRC_ID_START = 0x86, + VMC_IH_SRC_ID_END = 0x8f, + RLC_IH_SRC_ID_START = 0x90, + RLC_IH_SRC_ID_END = 0xf3, + PDMA_IH_SRC_ID_START = 0xf4, + PDMA_IH_SRC_ID_END = 0xf7, + CG_IH_SRC_ID_START = 0xf8, + CG_IH_SRC_ID_END = 0xff, +} IH_CLIENT_ID; +typedef enum IH_PERF_SEL { + IH_PERF_SEL_CYCLE = 0x0, + IH_PERF_SEL_IDLE = 0x1, + IH_PERF_SEL_INPUT_IDLE = 0x2, + IH_PERF_SEL_CLIENT0_IH_STALL = 0x3, + IH_PERF_SEL_CLIENT1_IH_STALL = 0x4, + IH_PERF_SEL_CLIENT2_IH_STALL = 0x5, + IH_PERF_SEL_CLIENT3_IH_STALL = 0x6, + IH_PERF_SEL_CLIENT4_IH_STALL = 0x7, + IH_PERF_SEL_CLIENT5_IH_STALL = 0x8, + IH_PERF_SEL_CLIENT6_IH_STALL = 0x9, + IH_PERF_SEL_CLIENT7_IH_STALL = 0xa, + IH_PERF_SEL_RB_IDLE = 0xb, + IH_PERF_SEL_RB_FULL = 0xc, + IH_PERF_SEL_RB_OVERFLOW = 0xd, + IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe, + IH_PERF_SEL_RB_WPTR_WRAP = 0xf, + IH_PERF_SEL_RB_RPTR_WRAP = 0x10, + IH_PERF_SEL_MC_WR_IDLE = 0x11, + IH_PERF_SEL_MC_WR_COUNT = 0x12, + IH_PERF_SEL_MC_WR_STALL = 0x13, + IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14, + IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15, + IH_PERF_SEL_BIF_RISING = 0x16, + IH_PERF_SEL_BIF_FALLING = 0x17, + IH_PERF_SEL_CLIENT8_IH_STALL = 0x18, + IH_PERF_SEL_CLIENT9_IH_STALL = 0x19, + IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a, + IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b, + IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c, + IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d, + IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e, + IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f, + IH_PERF_SEL_CLIENT16_IH_STALL = 0x20, + IH_PERF_SEL_CLIENT17_IH_STALL = 0x21, + IH_PERF_SEL_CLIENT18_IH_STALL = 0x22, + IH_PERF_SEL_CLIENT19_IH_STALL = 0x23, + IH_PERF_SEL_CLIENT20_IH_STALL = 0x24, + IH_PERF_SEL_CLIENT21_IH_STALL = 0x25, + IH_PERF_SEL_CLIENT22_IH_STALL = 0x26, + IH_PERF_SEL_CLIENT23_IH_STALL = 0x27, +} IH_PERF_SEL; +typedef enum SEM_PERF_SEL { + SEM_PERF_SEL_CYCLE = 0x0, + SEM_PERF_SEL_IDLE = 0x1, + SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x2, + SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x3, + SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x4, + SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x5, + SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x6, + SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x7, + SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x8, + SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x9, + SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0xa, + SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0xb, + SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0xc, + SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0xd, + SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0xe, + SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0xf, + SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x10, + SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x11, + SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x12, + SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x13, + SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x14, + SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x15, + SEM_PERF_SEL_UVD_REQ_WAIT = 0x16, + SEM_PERF_SEL_VCE0_REQ_WAIT = 0x17, + SEM_PERF_SEL_ACP_REQ_WAIT = 0x18, + SEM_PERF_SEL_ISP_REQ_WAIT = 0x19, + SEM_PERF_SEL_VCE1_REQ_WAIT = 0x1a, + SEM_PERF_SEL_VP8_REQ_WAIT = 0x1b, + SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x1c, + SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x1d, + SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x1e, + SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x1f, + SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x20, + SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x21, + SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x22, + SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x23, + SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x24, + SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x25, + SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x26, + SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x27, + SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x28, + SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x29, + SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x2a, + SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x2b, + SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x2c, + SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x2d, + SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x2e, + SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x2f, + SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x30, + SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x31, + SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x32, + SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x33, + SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x34, + SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x35, + SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x36, + SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x37, + SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x38, + SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x39, + SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x3a, + SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x3b, + SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x3c, + SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x3d, + SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x3e, + SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x3f, + SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x40, + SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x41, + SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x42, + SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x43, + SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x44, + SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x45, + SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x46, + SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x47, + SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x48, + SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x49, + SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x4a, + SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x4b, + SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x4c, + SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x4d, + SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x4e, + SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x4f, + SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x50, + SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x51, + SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x52, + SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x53, + SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x54, + SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x55, + SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x56, + SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x57, + SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x58, + SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x59, + SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x5a, + SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x5b, + SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x5c, + SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x5d, + SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x5e, + SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x5f, + SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x60, + SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x61, + SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x62, + SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x63, + SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x64, + SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x65, + SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x66, + SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x67, + SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x68, + SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x69, + SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x6a, + SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x6b, + SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x6c, + SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x6d, + SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x6e, + SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x6f, + SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x70, + SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x71, + SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x72, + SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x73, + SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x74, + SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x75, + SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x76, + SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x77, + SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x78, + SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x79, + SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x7a, + SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x7b, + SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x7c, + SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x7d, + SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x7e, + SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x7f, + SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x80, + SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x81, + SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x82, + SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x83, + SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x84, + SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x85, + SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x86, + SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x87, + SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x88, + SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x89, + SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x8a, + SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x8b, + SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x8c, + SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x8d, + SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x8e, + SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x8f, + SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x90, + SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x91, + SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x92, + SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x93, + SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x94, + SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x95, + SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x96, + SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x97, + SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x98, + SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x99, + SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x9a, + SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x9b, + SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x9c, + SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x9d, + SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x9e, + SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x9f, + SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0xa0, + SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0xa1, + SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0xa2, + SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0xa3, + SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0xa4, + SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0xa5, + SEM_PERF_SEL_MC_RD_REQ = 0xa6, + SEM_PERF_SEL_MC_RD_RET = 0xa7, + SEM_PERF_SEL_MC_WR_REQ = 0xa8, + SEM_PERF_SEL_MC_WR_RET = 0xa9, + SEM_PERF_SEL_ATC_REQ = 0xaa, + SEM_PERF_SEL_ATC_RET = 0xab, + SEM_PERF_SEL_ATC_XNACK = 0xac, + SEM_PERF_SEL_ATC_INVALIDATION = 0xad, +} SEM_PERF_SEL; +typedef enum SRBM_PERFCOUNT1_SEL { + SRBM_PERF_SEL_COUNT = 0x0, + SRBM_PERF_SEL_BIF_BUSY = 0x1, + SRBM_PERF_SEL_SDMA0_BUSY = 0x3, + SRBM_PERF_SEL_IH_BUSY = 0x4, + SRBM_PERF_SEL_MCB_BUSY = 0x5, + SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6, + SRBM_PERF_SEL_MCC_BUSY = 0x7, + SRBM_PERF_SEL_MCD_BUSY = 0x8, + SRBM_PERF_SEL_CHUB_BUSY = 0x9, + SRBM_PERF_SEL_SEM_BUSY = 0xa, + SRBM_PERF_SEL_UVD_BUSY = 0xb, + SRBM_PERF_SEL_VMC_BUSY = 0xc, + SRBM_PERF_SEL_ODE_BUSY = 0xd, + SRBM_PERF_SEL_SDMA1_BUSY = 0xe, + SRBM_PERF_SEL_SAMMSP_BUSY = 0xf, + SRBM_PERF_SEL_VCE0_BUSY = 0x10, + SRBM_PERF_SEL_XDMA_BUSY = 0x11, + SRBM_PERF_SEL_ACP_BUSY = 0x12, + SRBM_PERF_SEL_SDMA2_BUSY = 0x13, + SRBM_PERF_SEL_SDMA3_BUSY = 0x14, + RESERVED0 = 0x15, + SRBM_PERF_SEL_VMC1_BUSY = 0x16, + SRBM_PERF_SEL_ISP_BUSY = 0x17, + SRBM_PERF_SEL_VCE1_BUSY = 0x18, + SRBM_PERF_SEL_GCATCL2_BUSY = 0x19, + SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a, + SRBM_PERF_SEL_VP8_BUSY = 0x1b, +} SRBM_PERFCOUNT1_SEL; +typedef enum SYS_GRBM_GFX_INDEX_SEL { + GRBM_GFX_INDEX_BIF = 0x0, + GRBM_GFX_INDEX_SDMA0 = 0x1, + GRBM_GFX_INDEX_SDMA1 = 0x2, + RESEVERED0 = 0x3, + GRBM_GFX_INDEX_UVD = 0x4, + GRBM_GFX_INDEX_VCE0 = 0x5, + GRBM_GFX_INDEX_VCE1 = 0x6, + GRBM_GFX_INDEX_ACP = 0x7, + GRBM_GFX_INDEX_SMU = 0x8, + GRBM_GFX_INDEX_SAMMSP = 0x9, + GRBM_GFX_INDEX_VP8 = 0xa, + GRBM_GFX_INDEX_ISP = 0xb, + GRBM_GFX_INDEX_TST = 0xc, + GRBM_GFX_INDEX_SDMA2 = 0xd, + GRBM_GFX_INDEX_SDMA3 = 0xe, +} SYS_GRBM_GFX_INDEX_SEL; +typedef enum SRBM_GFX_CNTL_SEL { + SRBM_GFX_CNTL_BIF = 0x0, + SRBM_GFX_CNTL_SDMA0 = 0x1, + SRBM_GFX_CNTL_SDMA1 = 0x2, + SRBM_GFX_CNTL_GRBM = 0x3, + SRBM_GFX_CNTL_UVD = 0x4, + SRBM_GFX_CNTL_VCE0 = 0x5, + SRBM_GFX_CNTL_VCE1 = 0x6, + SRBM_GFX_CNTL_ACP = 0x7, + SRBM_GFX_CNTL_SMU = 0x8, + SRBM_GFX_CNTL_SAMMSP = 0x9, + SRBM_GFX_CNTL_VP8 = 0xa, + SRBM_GFX_CNTL_ISP = 0xb, + SRBM_GFX_CNTL_TST = 0xc, + SRBM_GFX_CNTL_SDMA2 = 0xd, + SRBM_GFX_CNTL_SDMA3 = 0xe, +} SRBM_GFX_CNTL_SEL; +typedef enum SDMA_PERF_SEL { + SDMA_PERF_SEL_CYCLE = 0x0, + SDMA_PERF_SEL_IDLE = 0x1, + SDMA_PERF_SEL_REG_IDLE = 0x2, + SDMA_PERF_SEL_RB_EMPTY = 0x3, + SDMA_PERF_SEL_RB_FULL = 0x4, + SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5, + SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6, + SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7, + SDMA_PERF_SEL_RB_RPTR_WB = 0x8, + SDMA_PERF_SEL_RB_CMD_IDLE = 0x9, + SDMA_PERF_SEL_RB_CMD_FULL = 0xa, + SDMA_PERF_SEL_IB_CMD_IDLE = 0xb, + SDMA_PERF_SEL_IB_CMD_FULL = 0xc, + SDMA_PERF_SEL_EX_IDLE = 0xd, + SDMA_PERF_SEL_SRBM_REG_SEND = 0xe, + SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf, + SDMA_PERF_SEL_MC_WR_IDLE = 0x10, + SDMA_PERF_SEL_MC_WR_COUNT = 0x11, + SDMA_PERF_SEL_MC_RD_IDLE = 0x12, + SDMA_PERF_SEL_MC_RD_COUNT = 0x13, + SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14, + SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15, + SDMA_PERF_SEL_SEM_IDLE = 0x18, + SDMA_PERF_SEL_SEM_REQ_STALL = 0x19, + SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a, + SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b, + SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c, + SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d, + SDMA_PERF_SEL_INT_IDLE = 0x1e, + SDMA_PERF_SEL_INT_REQ_STALL = 0x1f, + SDMA_PERF_SEL_INT_REQ_COUNT = 0x20, + SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21, + SDMA_PERF_SEL_INT_RESP_RETRY = 0x22, + SDMA_PERF_SEL_NUM_PACKET = 0x23, + SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25, + SDMA_PERF_SEL_CE_WR_IDLE = 0x26, + SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27, + SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28, + SDMA_PERF_SEL_CE_OUT_IDLE = 0x29, + SDMA_PERF_SEL_CE_IN_IDLE = 0x2a, + SDMA_PERF_SEL_CE_DST_IDLE = 0x2b, + SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e, + SDMA_PERF_SEL_CE_INFO_FULL = 0x31, + SDMA_PERF_SEL_CE_INFO1_FULL = 0x32, + SDMA_PERF_SEL_CE_RD_STALL = 0x33, + SDMA_PERF_SEL_CE_WR_STALL = 0x34, + SDMA_PERF_SEL_GFX_SELECT = 0x35, + SDMA_PERF_SEL_RLC0_SELECT = 0x36, + SDMA_PERF_SEL_RLC1_SELECT = 0x37, + SDMA_PERF_SEL_CTX_CHANGE = 0x38, + SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39, + SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a, + SDMA_PERF_SEL_DOORBELL = 0x3b, + SDMA_PERF_SEL_RD_BA_RTR = 0x3c, + SDMA_PERF_SEL_WR_BA_RTR = 0x3d, + SDMA_PERF_SEL_F32_L1_WR_VLD = 0x3e, + SDMA_PERF_SEL_CE_L1_WR_VLD = 0x3f, + SDMA_PERF_SEL_CE_L1_STALL = 0x40, + SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x41, + SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x42, + SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x43, + SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x44, + SDMA_PERF_SEL_ATCL2_RET_XNACK = 0x45, + SDMA_PERF_SEL_ATCL2_RET_ACK = 0x46, + SDMA_PERF_SEL_ATCL2_FREE = 0x47, + SDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x48, + SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x49, + SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x4a, + SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x4b, + SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x4c, + SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x4d, + SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x4e, + SDMA_PERF_SEL_L1_WRL2_IDLE = 0x4f, + SDMA_PERF_SEL_L1_RDL2_IDLE = 0x50, + SDMA_PERF_SEL_L1_WRMC_IDLE = 0x51, + SDMA_PERF_SEL_L1_RDMC_IDLE = 0x52, + SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x53, + SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x54, + SDMA_PERF_SEL_L1_WR_INV_EN = 0x55, + SDMA_PERF_SEL_L1_RD_INV_EN = 0x56, + SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x57, + SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x58, + SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x59, + SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x5a, + SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x5b, + SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x5c, + SDMA_PERF_SEL_L1_INV_MIDDLE = 0x5d, +} SDMA_PERF_SEL; +typedef enum DebugBlockId { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_UVDU = 0xd, + DBG_BLOCK_ID_SQA = 0xe, + DBG_BLOCK_ID_SDMA0 = 0xf, + DBG_BLOCK_ID_SDMA1 = 0x10, + DBG_BLOCK_ID_SPIM = 0x11, + DBG_BLOCK_ID_GDS = 0x12, + DBG_BLOCK_ID_VC0 = 0x13, + DBG_BLOCK_ID_VC1 = 0x14, + DBG_BLOCK_ID_PA0 = 0x15, + DBG_BLOCK_ID_PA1 = 0x16, + DBG_BLOCK_ID_CP0 = 0x17, + DBG_BLOCK_ID_CP1 = 0x18, + DBG_BLOCK_ID_CP2 = 0x19, + DBG_BLOCK_ID_XBR = 0x1a, + DBG_BLOCK_ID_UVDM = 0x1b, + DBG_BLOCK_ID_VGT0 = 0x1c, + DBG_BLOCK_ID_VGT1 = 0x1d, + DBG_BLOCK_ID_IA = 0x1e, + DBG_BLOCK_ID_SXM0 = 0x1f, + DBG_BLOCK_ID_SXM1 = 0x20, + DBG_BLOCK_ID_SCT0 = 0x21, + DBG_BLOCK_ID_SCT1 = 0x22, + DBG_BLOCK_ID_SPM0 = 0x23, + DBG_BLOCK_ID_SPM1 = 0x24, + DBG_BLOCK_ID_UNUSED0 = 0x25, + DBG_BLOCK_ID_UNUSED1 = 0x26, + DBG_BLOCK_ID_TCAA = 0x27, + DBG_BLOCK_ID_TCAB = 0x28, + DBG_BLOCK_ID_TCCA = 0x29, + DBG_BLOCK_ID_TCCB = 0x2a, + DBG_BLOCK_ID_MCC0 = 0x2b, + DBG_BLOCK_ID_MCC1 = 0x2c, + DBG_BLOCK_ID_MCC2 = 0x2d, + DBG_BLOCK_ID_MCC3 = 0x2e, + DBG_BLOCK_ID_SXS0 = 0x2f, + DBG_BLOCK_ID_SXS1 = 0x30, + DBG_BLOCK_ID_SXS2 = 0x31, + DBG_BLOCK_ID_SXS3 = 0x32, + DBG_BLOCK_ID_SXS4 = 0x33, + DBG_BLOCK_ID_SXS5 = 0x34, + DBG_BLOCK_ID_SXS6 = 0x35, + DBG_BLOCK_ID_SXS7 = 0x36, + DBG_BLOCK_ID_SXS8 = 0x37, + DBG_BLOCK_ID_SXS9 = 0x38, + DBG_BLOCK_ID_BCI0 = 0x39, + DBG_BLOCK_ID_BCI1 = 0x3a, + DBG_BLOCK_ID_BCI2 = 0x3b, + DBG_BLOCK_ID_BCI3 = 0x3c, + DBG_BLOCK_ID_MCB = 0x3d, + DBG_BLOCK_ID_UNUSED6 = 0x3e, + DBG_BLOCK_ID_SQA00 = 0x3f, + DBG_BLOCK_ID_SQA01 = 0x40, + DBG_BLOCK_ID_SQA02 = 0x41, + DBG_BLOCK_ID_SQA10 = 0x42, + DBG_BLOCK_ID_SQA11 = 0x43, + DBG_BLOCK_ID_SQA12 = 0x44, + DBG_BLOCK_ID_UNUSED7 = 0x45, + DBG_BLOCK_ID_UNUSED8 = 0x46, + DBG_BLOCK_ID_SQB00 = 0x47, + DBG_BLOCK_ID_SQB01 = 0x48, + DBG_BLOCK_ID_SQB10 = 0x49, + DBG_BLOCK_ID_SQB11 = 0x4a, + DBG_BLOCK_ID_SQ00 = 0x4b, + DBG_BLOCK_ID_SQ01 = 0x4c, + DBG_BLOCK_ID_SQ10 = 0x4d, + DBG_BLOCK_ID_SQ11 = 0x4e, + DBG_BLOCK_ID_CB00 = 0x4f, + DBG_BLOCK_ID_CB01 = 0x50, + DBG_BLOCK_ID_CB02 = 0x51, + DBG_BLOCK_ID_CB03 = 0x52, + DBG_BLOCK_ID_CB04 = 0x53, + DBG_BLOCK_ID_UNUSED9 = 0x54, + DBG_BLOCK_ID_UNUSED10 = 0x55, + DBG_BLOCK_ID_UNUSED11 = 0x56, + DBG_BLOCK_ID_CB10 = 0x57, + DBG_BLOCK_ID_CB11 = 0x58, + DBG_BLOCK_ID_CB12 = 0x59, + DBG_BLOCK_ID_CB13 = 0x5a, + DBG_BLOCK_ID_CB14 = 0x5b, + DBG_BLOCK_ID_UNUSED12 = 0x5c, + DBG_BLOCK_ID_UNUSED13 = 0x5d, + DBG_BLOCK_ID_UNUSED14 = 0x5e, + DBG_BLOCK_ID_TCP0 = 0x5f, + DBG_BLOCK_ID_TCP1 = 0x60, + DBG_BLOCK_ID_TCP2 = 0x61, + DBG_BLOCK_ID_TCP3 = 0x62, + DBG_BLOCK_ID_TCP4 = 0x63, + DBG_BLOCK_ID_TCP5 = 0x64, + DBG_BLOCK_ID_TCP6 = 0x65, + DBG_BLOCK_ID_TCP7 = 0x66, + DBG_BLOCK_ID_TCP8 = 0x67, + DBG_BLOCK_ID_TCP9 = 0x68, + DBG_BLOCK_ID_TCP10 = 0x69, + DBG_BLOCK_ID_TCP11 = 0x6a, + DBG_BLOCK_ID_TCP12 = 0x6b, + DBG_BLOCK_ID_TCP13 = 0x6c, + DBG_BLOCK_ID_TCP14 = 0x6d, + DBG_BLOCK_ID_TCP15 = 0x6e, + DBG_BLOCK_ID_TCP16 = 0x6f, + DBG_BLOCK_ID_TCP17 = 0x70, + DBG_BLOCK_ID_TCP18 = 0x71, + DBG_BLOCK_ID_TCP19 = 0x72, + DBG_BLOCK_ID_TCP20 = 0x73, + DBG_BLOCK_ID_TCP21 = 0x74, + DBG_BLOCK_ID_TCP22 = 0x75, + DBG_BLOCK_ID_TCP23 = 0x76, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, + DBG_BLOCK_ID_DB00 = 0x7f, + DBG_BLOCK_ID_DB01 = 0x80, + DBG_BLOCK_ID_DB02 = 0x81, + DBG_BLOCK_ID_DB03 = 0x82, + DBG_BLOCK_ID_DB04 = 0x83, + DBG_BLOCK_ID_UNUSED15 = 0x84, + DBG_BLOCK_ID_UNUSED16 = 0x85, + DBG_BLOCK_ID_UNUSED17 = 0x86, + DBG_BLOCK_ID_DB10 = 0x87, + DBG_BLOCK_ID_DB11 = 0x88, + DBG_BLOCK_ID_DB12 = 0x89, + DBG_BLOCK_ID_DB13 = 0x8a, + DBG_BLOCK_ID_DB14 = 0x8b, + DBG_BLOCK_ID_UNUSED18 = 0x8c, + DBG_BLOCK_ID_UNUSED19 = 0x8d, + DBG_BLOCK_ID_UNUSED20 = 0x8e, + DBG_BLOCK_ID_TCC0 = 0x8f, + DBG_BLOCK_ID_TCC1 = 0x90, + DBG_BLOCK_ID_TCC2 = 0x91, + DBG_BLOCK_ID_TCC3 = 0x92, + DBG_BLOCK_ID_TCC4 = 0x93, + DBG_BLOCK_ID_TCC5 = 0x94, + DBG_BLOCK_ID_TCC6 = 0x95, + DBG_BLOCK_ID_TCC7 = 0x96, + DBG_BLOCK_ID_SPS00 = 0x97, + DBG_BLOCK_ID_SPS01 = 0x98, + DBG_BLOCK_ID_SPS02 = 0x99, + DBG_BLOCK_ID_SPS10 = 0x9a, + DBG_BLOCK_ID_SPS11 = 0x9b, + DBG_BLOCK_ID_SPS12 = 0x9c, + DBG_BLOCK_ID_UNUSED21 = 0x9d, + DBG_BLOCK_ID_UNUSED22 = 0x9e, + DBG_BLOCK_ID_TA00 = 0x9f, + DBG_BLOCK_ID_TA01 = 0xa0, + DBG_BLOCK_ID_TA02 = 0xa1, + DBG_BLOCK_ID_TA03 = 0xa2, + DBG_BLOCK_ID_TA04 = 0xa3, + DBG_BLOCK_ID_TA05 = 0xa4, + DBG_BLOCK_ID_TA06 = 0xa5, + DBG_BLOCK_ID_TA07 = 0xa6, + DBG_BLOCK_ID_TA08 = 0xa7, + DBG_BLOCK_ID_TA09 = 0xa8, + DBG_BLOCK_ID_TA0A = 0xa9, + DBG_BLOCK_ID_TA0B = 0xaa, + DBG_BLOCK_ID_UNUSED23 = 0xab, + DBG_BLOCK_ID_UNUSED24 = 0xac, + DBG_BLOCK_ID_UNUSED25 = 0xad, + DBG_BLOCK_ID_UNUSED26 = 0xae, + DBG_BLOCK_ID_TA10 = 0xaf, + DBG_BLOCK_ID_TA11 = 0xb0, + DBG_BLOCK_ID_TA12 = 0xb1, + DBG_BLOCK_ID_TA13 = 0xb2, + DBG_BLOCK_ID_TA14 = 0xb3, + DBG_BLOCK_ID_TA15 = 0xb4, + DBG_BLOCK_ID_TA16 = 0xb5, + DBG_BLOCK_ID_TA17 = 0xb6, + DBG_BLOCK_ID_TA18 = 0xb7, + DBG_BLOCK_ID_TA19 = 0xb8, + DBG_BLOCK_ID_TA1A = 0xb9, + DBG_BLOCK_ID_TA1B = 0xba, + DBG_BLOCK_ID_UNUSED27 = 0xbb, + DBG_BLOCK_ID_UNUSED28 = 0xbc, + DBG_BLOCK_ID_UNUSED29 = 0xbd, + DBG_BLOCK_ID_UNUSED30 = 0xbe, + DBG_BLOCK_ID_TD00 = 0xbf, + DBG_BLOCK_ID_TD01 = 0xc0, + DBG_BLOCK_ID_TD02 = 0xc1, + DBG_BLOCK_ID_TD03 = 0xc2, + DBG_BLOCK_ID_TD04 = 0xc3, + DBG_BLOCK_ID_TD05 = 0xc4, + DBG_BLOCK_ID_TD06 = 0xc5, + DBG_BLOCK_ID_TD07 = 0xc6, + DBG_BLOCK_ID_TD08 = 0xc7, + DBG_BLOCK_ID_TD09 = 0xc8, + DBG_BLOCK_ID_TD0A = 0xc9, + DBG_BLOCK_ID_TD0B = 0xca, + DBG_BLOCK_ID_UNUSED31 = 0xcb, + DBG_BLOCK_ID_UNUSED32 = 0xcc, + DBG_BLOCK_ID_UNUSED33 = 0xcd, + DBG_BLOCK_ID_UNUSED34 = 0xce, + DBG_BLOCK_ID_TD10 = 0xcf, + DBG_BLOCK_ID_TD11 = 0xd0, + DBG_BLOCK_ID_TD12 = 0xd1, + DBG_BLOCK_ID_TD13 = 0xd2, + DBG_BLOCK_ID_TD14 = 0xd3, + DBG_BLOCK_ID_TD15 = 0xd4, + DBG_BLOCK_ID_TD16 = 0xd5, + DBG_BLOCK_ID_TD17 = 0xd6, + DBG_BLOCK_ID_TD18 = 0xd7, + DBG_BLOCK_ID_TD19 = 0xd8, + DBG_BLOCK_ID_TD1A = 0xd9, + DBG_BLOCK_ID_TD1B = 0xda, + DBG_BLOCK_ID_UNUSED35 = 0xdb, + DBG_BLOCK_ID_UNUSED36 = 0xdc, + DBG_BLOCK_ID_UNUSED37 = 0xdd, + DBG_BLOCK_ID_UNUSED38 = 0xde, + DBG_BLOCK_ID_LDS00 = 0xdf, + DBG_BLOCK_ID_LDS01 = 0xe0, + DBG_BLOCK_ID_LDS02 = 0xe1, + DBG_BLOCK_ID_LDS03 = 0xe2, + DBG_BLOCK_ID_LDS04 = 0xe3, + DBG_BLOCK_ID_LDS05 = 0xe4, + DBG_BLOCK_ID_LDS06 = 0xe5, + DBG_BLOCK_ID_LDS07 = 0xe6, + DBG_BLOCK_ID_LDS08 = 0xe7, + DBG_BLOCK_ID_LDS09 = 0xe8, + DBG_BLOCK_ID_LDS0A = 0xe9, + DBG_BLOCK_ID_LDS0B = 0xea, + DBG_BLOCK_ID_UNUSED39 = 0xeb, + DBG_BLOCK_ID_UNUSED40 = 0xec, + DBG_BLOCK_ID_UNUSED41 = 0xed, + DBG_BLOCK_ID_UNUSED42 = 0xee, + DBG_BLOCK_ID_LDS10 = 0xef, + DBG_BLOCK_ID_LDS11 = 0xf0, + DBG_BLOCK_ID_LDS12 = 0xf1, + DBG_BLOCK_ID_LDS13 = 0xf2, + DBG_BLOCK_ID_LDS14 = 0xf3, + DBG_BLOCK_ID_LDS15 = 0xf4, + DBG_BLOCK_ID_LDS16 = 0xf5, + DBG_BLOCK_ID_LDS17 = 0xf6, + DBG_BLOCK_ID_LDS18 = 0xf7, + DBG_BLOCK_ID_LDS19 = 0xf8, + DBG_BLOCK_ID_LDS1A = 0xf9, + DBG_BLOCK_ID_LDS1B = 0xfa, + DBG_BLOCK_ID_UNUSED43 = 0xfb, + DBG_BLOCK_ID_UNUSED44 = 0xfc, + DBG_BLOCK_ID_UNUSED45 = 0xfd, + DBG_BLOCK_ID_UNUSED46 = 0xfe, +} DebugBlockId; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_UVD_BY2 = 0x7, + DBG_BLOCK_ID_SDMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_VC0_BY2 = 0xa, + DBG_BLOCK_ID_PA_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_PC0_BY2 = 0xe, + DBG_BLOCK_ID_BCI0_BY2 = 0xf, + DBG_BLOCK_ID_SXM0_BY2 = 0x10, + DBG_BLOCK_ID_SCT0_BY2 = 0x11, + DBG_BLOCK_ID_SPM0_BY2 = 0x12, + DBG_BLOCK_ID_BCI2_BY2 = 0x13, + DBG_BLOCK_ID_TCA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_MCD_BY2 = 0x18, + DBG_BLOCK_ID_MCD2_BY2 = 0x19, + DBG_BLOCK_ID_MCD4_BY2 = 0x1a, + DBG_BLOCK_ID_MCB_BY2 = 0x1b, + DBG_BLOCK_ID_SQA_BY2 = 0x1c, + DBG_BLOCK_ID_SQA02_BY2 = 0x1d, + DBG_BLOCK_ID_SQA11_BY2 = 0x1e, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, + DBG_BLOCK_ID_SQB_BY2 = 0x20, + DBG_BLOCK_ID_SQB10_BY2 = 0x21, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, + DBG_BLOCK_ID_CB_BY2 = 0x24, + DBG_BLOCK_ID_CB02_BY2 = 0x25, + DBG_BLOCK_ID_CB10_BY2 = 0x26, + DBG_BLOCK_ID_CB12_BY2 = 0x27, + DBG_BLOCK_ID_SXS_BY2 = 0x28, + DBG_BLOCK_ID_SXS2_BY2 = 0x29, + DBG_BLOCK_ID_SXS4_BY2 = 0x2a, + DBG_BLOCK_ID_SXS6_BY2 = 0x2b, + DBG_BLOCK_ID_DB_BY2 = 0x2c, + DBG_BLOCK_ID_DB02_BY2 = 0x2d, + DBG_BLOCK_ID_DB10_BY2 = 0x2e, + DBG_BLOCK_ID_DB12_BY2 = 0x2f, + DBG_BLOCK_ID_TCP_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_TCC_BY2 = 0x40, + DBG_BLOCK_ID_TCC2_BY2 = 0x41, + DBG_BLOCK_ID_TCC4_BY2 = 0x42, + DBG_BLOCK_ID_TCC6_BY2 = 0x43, + DBG_BLOCK_ID_SPS_BY2 = 0x44, + DBG_BLOCK_ID_SPS02_BY2 = 0x45, + DBG_BLOCK_ID_SPS11_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, + DBG_BLOCK_ID_TA_BY2 = 0x48, + DBG_BLOCK_ID_TA02_BY2 = 0x49, + DBG_BLOCK_ID_TA04_BY2 = 0x4a, + DBG_BLOCK_ID_TA06_BY2 = 0x4b, + DBG_BLOCK_ID_TA08_BY2 = 0x4c, + DBG_BLOCK_ID_TA0A_BY2 = 0x4d, + DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, + DBG_BLOCK_ID_TA10_BY2 = 0x50, + DBG_BLOCK_ID_TA12_BY2 = 0x51, + DBG_BLOCK_ID_TA14_BY2 = 0x52, + DBG_BLOCK_ID_TA16_BY2 = 0x53, + DBG_BLOCK_ID_TA18_BY2 = 0x54, + DBG_BLOCK_ID_TA1A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, + DBG_BLOCK_ID_TD_BY2 = 0x58, + DBG_BLOCK_ID_TD02_BY2 = 0x59, + DBG_BLOCK_ID_TD04_BY2 = 0x5a, + DBG_BLOCK_ID_TD06_BY2 = 0x5b, + DBG_BLOCK_ID_TD08_BY2 = 0x5c, + DBG_BLOCK_ID_TD0A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, + DBG_BLOCK_ID_TD10_BY2 = 0x60, + DBG_BLOCK_ID_TD12_BY2 = 0x61, + DBG_BLOCK_ID_TD14_BY2 = 0x62, + DBG_BLOCK_ID_TD16_BY2 = 0x63, + DBG_BLOCK_ID_TD18_BY2 = 0x64, + DBG_BLOCK_ID_TD1A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, + DBG_BLOCK_ID_LDS_BY2 = 0x68, + DBG_BLOCK_ID_LDS02_BY2 = 0x69, + DBG_BLOCK_ID_LDS04_BY2 = 0x6a, + DBG_BLOCK_ID_LDS06_BY2 = 0x6b, + DBG_BLOCK_ID_LDS08_BY2 = 0x6c, + DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, + DBG_BLOCK_ID_LDS10_BY2 = 0x70, + DBG_BLOCK_ID_LDS12_BY2 = 0x71, + DBG_BLOCK_ID_LDS14_BY2 = 0x72, + DBG_BLOCK_ID_LDS16_BY2 = 0x73, + DBG_BLOCK_ID_LDS18_BY2 = 0x74, + DBG_BLOCK_ID_LDS1A_BY2 = 0x75, + DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, + DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_SDMA0_BY4 = 0x4, + DBG_BLOCK_ID_VC0_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, + DBG_BLOCK_ID_SXM0_BY4 = 0x8, + DBG_BLOCK_ID_SPM0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC_BY4 = 0xb, + DBG_BLOCK_ID_MCD_BY4 = 0xc, + DBG_BLOCK_ID_MCD4_BY4 = 0xd, + DBG_BLOCK_ID_SQA_BY4 = 0xe, + DBG_BLOCK_ID_SQA11_BY4 = 0xf, + DBG_BLOCK_ID_SQB_BY4 = 0x10, + DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, + DBG_BLOCK_ID_CB_BY4 = 0x12, + DBG_BLOCK_ID_CB10_BY4 = 0x13, + DBG_BLOCK_ID_SXS_BY4 = 0x14, + DBG_BLOCK_ID_SXS4_BY4 = 0x15, + DBG_BLOCK_ID_DB_BY4 = 0x16, + DBG_BLOCK_ID_DB10_BY4 = 0x17, + DBG_BLOCK_ID_TCP_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_TCC_BY4 = 0x20, + DBG_BLOCK_ID_TCC4_BY4 = 0x21, + DBG_BLOCK_ID_SPS_BY4 = 0x22, + DBG_BLOCK_ID_SPS11_BY4 = 0x23, + DBG_BLOCK_ID_TA_BY4 = 0x24, + DBG_BLOCK_ID_TA04_BY4 = 0x25, + DBG_BLOCK_ID_TA08_BY4 = 0x26, + DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, + DBG_BLOCK_ID_TA10_BY4 = 0x28, + DBG_BLOCK_ID_TA14_BY4 = 0x29, + DBG_BLOCK_ID_TA18_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, + DBG_BLOCK_ID_TD_BY4 = 0x2c, + DBG_BLOCK_ID_TD04_BY4 = 0x2d, + DBG_BLOCK_ID_TD08_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, + DBG_BLOCK_ID_TD10_BY4 = 0x30, + DBG_BLOCK_ID_TD14_BY4 = 0x31, + DBG_BLOCK_ID_TD18_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, + DBG_BLOCK_ID_LDS_BY4 = 0x34, + DBG_BLOCK_ID_LDS04_BY4 = 0x35, + DBG_BLOCK_ID_LDS08_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, + DBG_BLOCK_ID_LDS10_BY4 = 0x38, + DBG_BLOCK_ID_LDS14_BY4 = 0x39, + DBG_BLOCK_ID_LDS18_BY4 = 0x3a, + DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_SDMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_SXM0_BY8 = 0x4, + DBG_BLOCK_ID_TCA_BY8 = 0x5, + DBG_BLOCK_ID_MCD_BY8 = 0x6, + DBG_BLOCK_ID_SQA_BY8 = 0x7, + DBG_BLOCK_ID_SQB_BY8 = 0x8, + DBG_BLOCK_ID_CB_BY8 = 0x9, + DBG_BLOCK_ID_SXS_BY8 = 0xa, + DBG_BLOCK_ID_DB_BY8 = 0xb, + DBG_BLOCK_ID_TCP_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_TCC_BY8 = 0x10, + DBG_BLOCK_ID_SPS_BY8 = 0x11, + DBG_BLOCK_ID_TA_BY8 = 0x12, + DBG_BLOCK_ID_TA08_BY8 = 0x13, + DBG_BLOCK_ID_TA10_BY8 = 0x14, + DBG_BLOCK_ID_TA18_BY8 = 0x15, + DBG_BLOCK_ID_TD_BY8 = 0x16, + DBG_BLOCK_ID_TD08_BY8 = 0x17, + DBG_BLOCK_ID_TD10_BY8 = 0x18, + DBG_BLOCK_ID_TD18_BY8 = 0x19, + DBG_BLOCK_ID_LDS_BY8 = 0x1a, + DBG_BLOCK_ID_LDS08_BY8 = 0x1b, + DBG_BLOCK_ID_LDS10_BY8 = 0x1c, + DBG_BLOCK_ID_LDS18_BY8 = 0x1d, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_SDMA0_BY16 = 0x1, + DBG_BLOCK_ID_SXM_BY16 = 0x2, + DBG_BLOCK_ID_MCD_BY16 = 0x3, + DBG_BLOCK_ID_SQB_BY16 = 0x4, + DBG_BLOCK_ID_SXS_BY16 = 0x5, + DBG_BLOCK_ID_TCP_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_TCC_BY16 = 0x8, + DBG_BLOCK_ID_TA_BY16 = 0x9, + DBG_BLOCK_ID_TA10_BY16 = 0xa, + DBG_BLOCK_ID_TD_BY16 = 0xb, + DBG_BLOCK_ID_TD10_BY16 = 0xc, + DBG_BLOCK_ID_LDS_BY16 = 0xd, + DBG_BLOCK_ID_LDS10_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* OSS_3_0_1_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h new file mode 100644 index 000000000000..cfacd8509bbb --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h @@ -0,0 +1,3558 @@ +/* + * OSS_3_0_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef OSS_3_0_1_SH_MASK_H +#define OSS_3_0_1_SH_MASK_H + +#define IH_VMID_0_LUT__PASID_MASK 0xffff +#define IH_VMID_0_LUT__PASID__SHIFT 0x0 +#define IH_VMID_1_LUT__PASID_MASK 0xffff +#define IH_VMID_1_LUT__PASID__SHIFT 0x0 +#define IH_VMID_2_LUT__PASID_MASK 0xffff +#define IH_VMID_2_LUT__PASID__SHIFT 0x0 +#define IH_VMID_3_LUT__PASID_MASK 0xffff +#define IH_VMID_3_LUT__PASID__SHIFT 0x0 +#define IH_VMID_4_LUT__PASID_MASK 0xffff +#define IH_VMID_4_LUT__PASID__SHIFT 0x0 +#define IH_VMID_5_LUT__PASID_MASK 0xffff +#define IH_VMID_5_LUT__PASID__SHIFT 0x0 +#define IH_VMID_6_LUT__PASID_MASK 0xffff +#define IH_VMID_6_LUT__PASID__SHIFT 0x0 +#define IH_VMID_7_LUT__PASID_MASK 0xffff +#define IH_VMID_7_LUT__PASID__SHIFT 0x0 +#define IH_VMID_8_LUT__PASID_MASK 0xffff +#define IH_VMID_8_LUT__PASID__SHIFT 0x0 +#define IH_VMID_9_LUT__PASID_MASK 0xffff +#define IH_VMID_9_LUT__PASID__SHIFT 0x0 +#define IH_VMID_10_LUT__PASID_MASK 0xffff +#define IH_VMID_10_LUT__PASID__SHIFT 0x0 +#define IH_VMID_11_LUT__PASID_MASK 0xffff +#define IH_VMID_11_LUT__PASID__SHIFT 0x0 +#define IH_VMID_12_LUT__PASID_MASK 0xffff +#define IH_VMID_12_LUT__PASID__SHIFT 0x0 +#define IH_VMID_13_LUT__PASID_MASK 0xffff +#define IH_VMID_13_LUT__PASID__SHIFT 0x0 +#define IH_VMID_14_LUT__PASID_MASK 0xffff +#define IH_VMID_14_LUT__PASID__SHIFT 0x0 +#define IH_VMID_15_LUT__PASID_MASK 0xffff +#define IH_VMID_15_LUT__PASID__SHIFT 0x0 +#define IH_RB_CNTL__RB_ENABLE_MASK 0x1 +#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define IH_RB_CNTL__RB_SIZE_MASK 0x3e +#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40 +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6 +#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80 +#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00 +#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000 +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define IH_RB_BASE__ADDR_MASK 0xffffffff +#define IH_RB_BASE__ADDR__SHIFT 0x0 +#define IH_RB_RPTR__OFFSET_MASK 0x3fffc +#define IH_RB_RPTR__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1 +#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 +#define IH_RB_WPTR__OFFSET_MASK 0x3fffc +#define IH_RB_WPTR__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000 +#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 +#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000 +#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 +#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff +#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define IH_CNTL__ENABLE_INTR_MASK 0x1 +#define IH_CNTL__ENABLE_INTR__SHIFT 0x0 +#define IH_CNTL__MC_SWAP_MASK 0x6 +#define IH_CNTL__MC_SWAP__SHIFT 0x1 +#define IH_CNTL__RPTR_REARM_MASK 0x10 +#define IH_CNTL__RPTR_REARM__SHIFT 0x4 +#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300 +#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8 +#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00 +#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa +#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000 +#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf +#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000 +#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 +#define IH_CNTL__MC_VMID_MASK 0x1e000000 +#define IH_CNTL__MC_VMID__SHIFT 0x19 +#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1 +#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0 +#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4 +#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2 +#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8 +#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3 +#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10 +#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4 +#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20 +#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5 +#define IH_STATUS__IDLE_MASK 0x1 +#define IH_STATUS__IDLE__SHIFT 0x0 +#define IH_STATUS__INPUT_IDLE_MASK 0x2 +#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 +#define IH_STATUS__RB_IDLE_MASK 0x4 +#define IH_STATUS__RB_IDLE__SHIFT 0x2 +#define IH_STATUS__RB_FULL_MASK 0x8 +#define IH_STATUS__RB_FULL__SHIFT 0x3 +#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10 +#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 +#define IH_STATUS__RB_OVERFLOW_MASK 0x20 +#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 +#define IH_STATUS__MC_WR_IDLE_MASK 0x40 +#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 +#define IH_STATUS__MC_WR_STALL_MASK 0x80 +#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 +#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100 +#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 +#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200 +#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 +#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400 +#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa +#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1 +#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 +#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2 +#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 +#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc +#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100 +#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8 +#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200 +#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9 +#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 +#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff +#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff +#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff +#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1 +#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 +#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4 +#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 +#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8 +#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 +#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10 +#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 +#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20 +#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 +#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff +#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 +#define IH_VERSION__VALUE_MASK 0xfff +#define IH_VERSION__VALUE__SHIFT 0x0 +#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3 +#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 +#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc +#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 +#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00 +#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 +#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 +#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 +#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc +#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400 +#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800 +#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0xff000 +#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SEM_VF_ENABLE__VALUE_MASK 0x1 +#define SEM_VF_ENABLE__VALUE__SHIFT 0x0 +#define SEM_ACTIVE_FCN_ID__VFID_MASK 0xf +#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000 +#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SEM_VIRT_RESET_REQ__VF_MASK 0xffff +#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SEM_STATUS__SEM_IDLE_MASK 0x1 +#define SEM_STATUS__SEM_IDLE__SHIFT 0x0 +#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2 +#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 +#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4 +#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 +#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8 +#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 +#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10 +#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 +#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20 +#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 +#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40 +#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 +#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80 +#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 +#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100 +#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 +#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200 +#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 +#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400 +#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa +#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800 +#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb +#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000 +#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc +#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000 +#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd +#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000 +#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe +#define SEM_STATUS__ATC_REQ_PENDING_MASK 0x8000 +#define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf +#define SEM_STATUS__SWITCH_READY_MASK 0x80000000 +#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f +#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00 +#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000 +#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf +#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000 +#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000 +#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 +#define SEM_MAILBOX__SIDEPORT_MASK 0xff +#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0 +#define SEM_MAILBOX__HOSTPORT_MASK 0xff00 +#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8 +#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000 +#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10 +#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000 +#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000 +#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000 +#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18 +#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1 +#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 +#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2 +#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 +#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4 +#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 +#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18 +#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 +#define SEM_CHICKEN_BITS__SIGNAL_FAIL_MASK 0x20 +#define SEM_CHICKEN_BITS__SIGNAL_FAIL__SHIFT 0x5 +#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x40 +#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6 +#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x80 +#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7 +#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00 +#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 +#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x3000 +#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc +#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f +#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 +#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000 +#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10 +#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000 +#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11 +#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000 +#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12 +#define SRBM_CNTL__PWR_GFX3D_REQUEST_HALT_MASK 0x80000 +#define SRBM_CNTL__PWR_GFX3D_REQUEST_HALT__SHIFT 0x13 +#define SRBM_GFX_CNTL__PIPEID_MASK 0x3 +#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0 +#define SRBM_GFX_CNTL__MEID_MASK 0xc +#define SRBM_GFX_CNTL__MEID__SHIFT 0x2 +#define SRBM_GFX_CNTL__VMID_MASK 0xf0 +#define SRBM_GFX_CNTL__VMID__SHIFT 0x4 +#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700 +#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 +#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff +#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1 +#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0 +#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2 +#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1 +#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4 +#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2 +#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8 +#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3 +#define SRBM_STATUS2__VP8_BUSY_MASK 0x10 +#define SRBM_STATUS2__VP8_BUSY__SHIFT 0x4 +#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20 +#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5 +#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40 +#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6 +#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80 +#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7 +#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100 +#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8 +#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200 +#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9 +#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400 +#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa +#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800 +#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb +#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000 +#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd +#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000 +#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe +#define SRBM_STATUS2__ODE_BUSY_MASK 0x8000 +#define SRBM_STATUS2__ODE_BUSY__SHIFT 0xf +#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000 +#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10 +#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000 +#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11 +#define SRBM_STATUS2__VP8_RQ_PENDING_MASK 0x40000 +#define SRBM_STATUS2__VP8_RQ_PENDING__SHIFT 0x12 +#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000 +#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13 +#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000 +#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14 +#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2 +#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1 +#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4 +#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2 +#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8 +#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3 +#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10 +#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4 +#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20 +#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5 +#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40 +#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6 +#define SRBM_STATUS__VMC_BUSY_MASK 0x100 +#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8 +#define SRBM_STATUS__MCB_BUSY_MASK 0x200 +#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9 +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400 +#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa +#define SRBM_STATUS__MCC_BUSY_MASK 0x800 +#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb +#define SRBM_STATUS__MCD_BUSY_MASK 0x1000 +#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc +#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000 +#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd +#define SRBM_STATUS__SEM_BUSY_MASK 0x4000 +#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe +#define SRBM_STATUS__ACP_BUSY_MASK 0x10000 +#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10 +#define SRBM_STATUS__IH_BUSY_MASK 0x20000 +#define SRBM_STATUS__IH_BUSY__SHIFT 0x11 +#define SRBM_STATUS__UVD_BUSY_MASK 0x80000 +#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13 +#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000 +#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14 +#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000 +#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15 +#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000 +#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16 +#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000 +#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d +#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1 +#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0 +#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2 +#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1 +#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4 +#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2 +#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8 +#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3 +#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10 +#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4 +#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20 +#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5 +#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40 +#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6 +#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80 +#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7 +#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100 +#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8 +#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200 +#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9 +#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400 +#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa +#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800 +#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb +#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000 +#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc +#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000 +#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd +#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000 +#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe +#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000 +#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf +#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1 +#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0 +#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2 +#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3 +#define SRBM_SOFT_RESET__SOFT_RESET_GIONB_MASK 0x10 +#define SRBM_SOFT_RESET__SOFT_RESET_GIONB__SHIFT 0x4 +#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20 +#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6 +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100 +#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8 +#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200 +#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9 +#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400 +#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa +#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800 +#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb +#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000 +#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc +#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000 +#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd +#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000 +#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe +#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000 +#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf +#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000 +#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10 +#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000 +#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11 +#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000 +#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12 +#define SRBM_SOFT_RESET__SOFT_RESET_VP8_MASK 0x80000 +#define SRBM_SOFT_RESET__SOFT_RESET_VP8__SHIFT 0x13 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000 +#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14 +#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000 +#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15 +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000 +#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16 +#define SRBM_SOFT_RESET__SOFT_RESET_ODE_MASK 0x800000 +#define SRBM_SOFT_RESET__SOFT_RESET_ODE__SHIFT 0x17 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18 +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000 +#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19 +#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000 +#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a +#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000 +#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b +#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000 +#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d +#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000 +#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e +#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000 +#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f +#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0 +#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff +#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0 +#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff +#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 +#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 +#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 +#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 +#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1 +#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0 +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2 +#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1 +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4 +#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2 +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10 +#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4 +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20 +#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5 +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40 +#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6 +#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80 +#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7 +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100 +#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8 +#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200 +#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9 +#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400 +#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa +#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE_MASK 0x800 +#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xb +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1 +#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0 +#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2 +#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1 +#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4 +#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2 +#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8 +#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3 +#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10 +#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4 +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20 +#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5 +#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40 +#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6 +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80 +#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7 +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100 +#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8 +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200 +#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9 +#define SRBM_DEBUG_SNAPSHOT__VP8_RDY_MASK 0x400 +#define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT 0xa +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800 +#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb +#define SRBM_DEBUG_SNAPSHOT__ODE_RDY_MASK 0x1000 +#define SRBM_DEBUG_SNAPSHOT__ODE_RDY__SHIFT 0xc +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000 +#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000 +#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000 +#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000 +#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10 +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000 +#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11 +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000 +#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12 +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000 +#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13 +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000 +#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14 +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000 +#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15 +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000 +#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16 +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000 +#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17 +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000 +#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18 +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000 +#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19 +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000 +#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000 +#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000 +#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c +#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000 +#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d +#define SRBM_DEBUG_SNAPSHOT__RESERVED_MASK 0x40000000 +#define SRBM_DEBUG_SNAPSHOT__RESERVED__SHIFT 0x1e +#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000 +#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f +#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1 +#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0 +#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc +#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13 +#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000 +#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15 +#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000 +#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16 +#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000 +#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17 +#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000 +#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18 +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000 +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19 +#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000 +#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a +#define SRBM_READ_ERROR__READ_REQUESTER_VP8_MASK 0x8000000 +#define SRBM_READ_ERROR__READ_REQUESTER_VP8__SHIFT 0x1b +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000 +#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c +#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000 +#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d +#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 +#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1 +#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0 +#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2 +#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1 +#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4 +#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2 +#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000 +#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17 +#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000 +#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18 +#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1 +#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0 +#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2 +#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1 +#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1 +#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0 +#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2 +#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1 +#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1 +#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0 +#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2 +#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VP8_MASK 0x4 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VP8__SHIFT 0x2 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000 +#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000 +#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000 +#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14 +#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000 +#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0 +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000 +#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10 +#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff +#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0 +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0 +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000 +#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10 +#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff +#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0 +#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf +#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 +#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 +#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff +#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0 +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff +#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff +#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0 +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff +#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0 +#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3 +#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff +#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 +#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 +#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff +#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 +#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 +#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 +#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 +#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 +#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 +#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 +#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff +#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 +#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 +#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 +#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf +#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0 +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0 +#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00 +#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8 +#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000 +#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10 +#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000 +#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 +#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000 +#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f +#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf +#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0 +#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3 +#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0 +#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc +#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2 +#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0 +#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4 +#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700 +#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8 +#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1 +#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1 +#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0 +#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff +#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA0_UCODE_ADDR__VALUE_MASK 0x1fff +#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff +#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf +#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1 +#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2 +#define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8 +#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 +#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 +#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 +#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7 +#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0 +#define SDMA0_HASH__BANK_BITS_MASK 0x70 +#define SDMA0_HASH__BANK_BITS__SHIFT 0x4 +#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700 +#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 +#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000 +#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc +#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc +#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff +#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_STATUS_REG__IDLE_MASK 0x1 +#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2 +#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4 +#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8 +#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10 +#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20 +#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40 +#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80 +#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100 +#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200 +#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400 +#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000 +#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000 +#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000 +#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 +#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000 +#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000 +#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 +#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 +#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000 +#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 +#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2 +#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20 +#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40 +#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 +#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 +#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000 +#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000 +#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x3 +#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc +#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xff000 +#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_F32_CNTL__HALT_MASK 0x1 +#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA0_F32_CNTL__STEP_MASK 0x2 +#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc +#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define SDMA0_FREEZE__FREEZE_MASK 0x10 +#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA0_FREEZE__FROZEN_MASK 0x20 +#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40 +#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf +#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf +#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1 +#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2 +#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1 +#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4 +#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2 +#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30 +#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 +#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40 +#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6 +#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80 +#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7 +#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00 +#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8 +#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000 +#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14 +#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff +#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 +#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200 +#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400 +#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800 +#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000 +#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000 +#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 +#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff +#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff +#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 +#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff +#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 +#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA0_ID__DEVICE_ID_MASK 0xff +#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_VERSION__VALUE_MASK 0xffff +#define SDMA0_VERSION__VALUE__SHIFT 0x0 +#define SDMA0_VM_CNTL__CMD_MASK 0xf +#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA0_VM_CTX_LO__ADDR_MASK 0xfffffffc +#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA0_VM_CTX_HI__ADDR_MASK 0xffffffff +#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA0_STATUS2_REG__ID_MASK 0x3 +#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc +#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 +#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000 +#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0xf +#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000 +#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1 +#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA0_VM_CTX_CNTL__VMID_MASK 0xf0 +#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA0_VIRT_RESET_REQ__VF_MASK 0xffff +#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1 +#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff +#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff +#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA0_ATCL1_CNTL__REDO_ENABLE_MASK 0x1 +#define SDMA0_ATCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA0_ATCL1_CNTL__REDO_DELAY_MASK 0x7fe +#define SDMA0_ATCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA0_ATCL1_CNTL__REDO_WATERMK_MASK 0x3800 +#define SDMA0_ATCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA0_ATCL1_CNTL__INVACK_DELAY_MASK 0xffc000 +#define SDMA0_ATCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA0_ATCL1_CNTL__REQL2_CREDIT_MASK 0xf000000 +#define SDMA0_ATCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA0_ATCL1_CNTL__VADDR_WATERMK_MASK 0x70000000 +#define SDMA0_ATCL1_CNTL__VADDR_WATERMK__SHIFT 0x1c +#define SDMA0_ATCL1_WATERMK__REQMC_WATERMK_MASK 0x3ff +#define SDMA0_ATCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA0_ATCL1_WATERMK__REQPG_WATERMK_MASK 0x3fc00 +#define SDMA0_ATCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa +#define SDMA0_ATCL1_WATERMK__INVREQ_WATERMK_MASK 0xfc0000 +#define SDMA0_ATCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 +#define SDMA0_ATCL1_WATERMK__XNACK_WATERMK_MASK 0x7f000000 +#define SDMA0_ATCL1_WATERMK__XNACK_WATERMK__SHIFT 0x18 +#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1 +#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2 +#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4 +#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8 +#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10 +#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20 +#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40 +#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80 +#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100 +#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200 +#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400 +#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x800 +#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000 +#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000 +#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000 +#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000 +#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000 +#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000 +#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_ATCL1_RD_STATUS__ALL_IDLE_MASK 0x40000 +#define SDMA0_ATCL1_RD_STATUS__ALL_IDLE__SHIFT 0x12 +#define SDMA0_ATCL1_RD_STATUS__REQL2_IDLE_MASK 0x80000 +#define SDMA0_ATCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x13 +#define SDMA0_ATCL1_RD_STATUS__REQMC_IDLE_MASK 0x100000 +#define SDMA0_ATCL1_RD_STATUS__REQMC_IDLE__SHIFT 0x14 +#define SDMA0_ATCL1_RD_STATUS__CE_L1_STALL_MASK 0x200000 +#define SDMA0_ATCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA0_ATCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x3c00000 +#define SDMA0_ATCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA0_ATCL1_RD_STATUS__MERGE_STATE_MASK 0x1c000000 +#define SDMA0_ATCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA0_ATCL1_RD_STATUS__RESERVED_MASK 0xe0000000 +#define SDMA0_ATCL1_RD_STATUS__RESERVED__SHIFT 0x1d +#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1 +#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2 +#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4 +#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8 +#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10 +#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20 +#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40 +#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80 +#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100 +#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200 +#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400 +#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x800 +#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000 +#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000 +#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000 +#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000 +#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000 +#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000 +#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_ATCL1_WR_STATUS__ALL_IDLE_MASK 0x40000 +#define SDMA0_ATCL1_WR_STATUS__ALL_IDLE__SHIFT 0x12 +#define SDMA0_ATCL1_WR_STATUS__REQL2_IDLE_MASK 0x80000 +#define SDMA0_ATCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x13 +#define SDMA0_ATCL1_WR_STATUS__REQMC_IDLE_MASK 0x100000 +#define SDMA0_ATCL1_WR_STATUS__REQMC_IDLE__SHIFT 0x14 +#define SDMA0_ATCL1_WR_STATUS__F32_WR_RTR_MASK 0x200000 +#define SDMA0_ATCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA0_ATCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x3c00000 +#define SDMA0_ATCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA0_ATCL1_WR_STATUS__MERGE_STATE_MASK 0x1c000000 +#define SDMA0_ATCL1_WR_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA0_ATCL1_WR_STATUS__RESERVED_MASK 0xe0000000 +#define SDMA0_ATCL1_WR_STATUS__RESERVED__SHIFT 0x1d +#define SDMA0_ATCL1_INV0__INV_MIDDLE_MASK 0x1 +#define SDMA0_ATCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA0_ATCL1_INV0__RD_TIMEOUT_MASK 0x2 +#define SDMA0_ATCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA0_ATCL1_INV0__WR_TIMEOUT_MASK 0x4 +#define SDMA0_ATCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA0_ATCL1_INV0__RD_IN_INVADR_MASK 0x8 +#define SDMA0_ATCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA0_ATCL1_INV0__WR_IN_INVADR_MASK 0x10 +#define SDMA0_ATCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA0_ATCL1_INV0__RD_WT_INVADR_MASK 0x20 +#define SDMA0_ATCL1_INV0__RD_WT_INVADR__SHIFT 0x5 +#define SDMA0_ATCL1_INV0__WR_WT_INVADR_MASK 0x40 +#define SDMA0_ATCL1_INV0__WR_WT_INVADR__SHIFT 0x6 +#define SDMA0_ATCL1_INV0__RD_INV_EN_MASK 0x80 +#define SDMA0_ATCL1_INV0__RD_INV_EN__SHIFT 0x7 +#define SDMA0_ATCL1_INV0__WR_INV_EN_MASK 0x100 +#define SDMA0_ATCL1_INV0__WR_INV_EN__SHIFT 0x8 +#define SDMA0_ATCL1_INV0__RD_INV_IDLE_MASK 0x200 +#define SDMA0_ATCL1_INV0__RD_INV_IDLE__SHIFT 0x9 +#define SDMA0_ATCL1_INV0__WR_INV_IDLE_MASK 0x400 +#define SDMA0_ATCL1_INV0__WR_INV_IDLE__SHIFT 0xa +#define SDMA0_ATCL1_INV0__INV_FLUSHTYPE_MASK 0x800 +#define SDMA0_ATCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA0_ATCL1_INV0__INV_VMID_VEC_MASK 0xffff000 +#define SDMA0_ATCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA0_ATCL1_INV0__INV_ADDR_HI_MASK 0xf0000000 +#define SDMA0_ATCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA0_ATCL1_INV1__INV_ADDR_LO_MASK 0xffffffff +#define SDMA0_ATCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA0_ATCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xffff +#define SDMA0_ATCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA0_ATCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff +#define SDMA0_ATCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_ATCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0xf +#define SDMA0_ATCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_ATCL1_RD_XNACK1__XNACK_VMID_MASK 0xf0 +#define SDMA0_ATCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_ATCL1_RD_XNACK1__IS_XNACK_MASK 0x100 +#define SDMA0_ATCL1_RD_XNACK1__IS_XNACK__SHIFT 0x8 +#define SDMA0_ATCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff +#define SDMA0_ATCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_ATCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0xf +#define SDMA0_ATCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_ATCL1_WR_XNACK1__XNACK_VMID_MASK 0xf0 +#define SDMA0_ATCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_ATCL1_WR_XNACK1__IS_XNACK_MASK 0x100 +#define SDMA0_ATCL1_WR_XNACK1__IS_XNACK__SHIFT 0x8 +#define SDMA0_ATCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0xffff +#define SDMA0_ATCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA0_ATCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xffff0000 +#define SDMA0_ATCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0xffff +#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0xff0000 +#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xff000000 +#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL__SHIFT 0x0 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT_MASK 0x4 +#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2 +#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 +#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x4 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x8 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x10 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x100 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x200 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x400 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x800 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x1000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x2000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x4000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x8000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x10000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x20000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x40000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x80000 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR_MASK 0x80 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL_MASK 0x100 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x200 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x400 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1_MASK 0x800 +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x1000 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x2000 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x4000 +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x8000 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x10000 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x20000 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x4 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x8 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x10 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x20 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x40 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x80 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x100 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x200 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xfffffc00 +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x4 +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x8 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG_MASK 0x40 +#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH_MASK 0x80 +#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 +#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH_MASK 0x400 +#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH_MASK 0x800 +#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM_MASK 0x1000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG_MASK 0x2000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG_MASK 0x4000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL_MASK 0x8000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 +#define SDMA0_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 +#define SDMA0_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL_MASK 0x40000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE_MASK 0x80000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM_MASK 0x100000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM_MASK 0x200000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING_MASK 0x400000 +#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG_MASK 0x800000 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE_MASK 0x1000000 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ_MASK 0x2000000 +#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG_MASK 0x4000000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD_MASK 0x8000000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID_MASK 0x10000000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION_MASK 0x20000000 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 +#define SDMA0_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI_MASK 0x4 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x8 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID_MASK 0x10 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL_MASK 0x20 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ_MASK 0x40 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE_MASK 0x80 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x100 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x200 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x400 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_CNTL_MASK 0x800 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_CNTL__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_WATERMK_MASK 0x1000 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_WATERMK__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_TIMEOUT_MASK 0x2000 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_TIMEOUT__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE1__RESERVED_MASK 0xffffc000 +#define SDMA0_PUB_REG_TYPE1__RESERVED__SHIFT 0xe +#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_GFX_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA0_GFX_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 +#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xffffffff +#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xffffffff +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff +#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xffffffff +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_UCODE_ADDR__VALUE_MASK 0x1fff +#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff +#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf +#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1 +#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2 +#define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8 +#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 +#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 +#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 +#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7 +#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0 +#define SDMA1_HASH__BANK_BITS_MASK 0x70 +#define SDMA1_HASH__BANK_BITS__SHIFT 0x4 +#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700 +#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 +#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000 +#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc +#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc +#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff +#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_STATUS_REG__IDLE_MASK 0x1 +#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2 +#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4 +#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8 +#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10 +#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20 +#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40 +#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80 +#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100 +#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200 +#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400 +#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000 +#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000 +#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000 +#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 +#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000 +#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000 +#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 +#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 +#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000 +#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 +#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 +#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20 +#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40 +#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 +#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 +#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000 +#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000 +#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x3 +#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc +#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xff000 +#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_F32_CNTL__HALT_MASK 0x1 +#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA1_F32_CNTL__STEP_MASK 0x2 +#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc +#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define SDMA1_FREEZE__FREEZE_MASK 0x10 +#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA1_FREEZE__FROZEN_MASK 0x20 +#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40 +#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf +#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf +#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00 +#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000 +#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff +#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 +#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA1_ID__DEVICE_ID_MASK 0xff +#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA1_VERSION__VALUE_MASK 0xffff +#define SDMA1_VERSION__VALUE__SHIFT 0x0 +#define SDMA1_VM_CNTL__CMD_MASK 0xf +#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA1_VM_CTX_LO__ADDR_MASK 0xfffffffc +#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA1_VM_CTX_HI__ADDR_MASK 0xffffffff +#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA1_STATUS2_REG__ID_MASK 0x3 +#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc +#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 +#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000 +#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0xf +#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000 +#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1 +#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA1_VM_CTX_CNTL__VMID_MASK 0xf0 +#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA1_VIRT_RESET_REQ__VF_MASK 0xffff +#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1 +#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff +#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff +#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA1_ATCL1_CNTL__REDO_ENABLE_MASK 0x1 +#define SDMA1_ATCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA1_ATCL1_CNTL__REDO_DELAY_MASK 0x7fe +#define SDMA1_ATCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA1_ATCL1_CNTL__REDO_WATERMK_MASK 0x3800 +#define SDMA1_ATCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA1_ATCL1_CNTL__INVACK_DELAY_MASK 0xffc000 +#define SDMA1_ATCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA1_ATCL1_CNTL__REQL2_CREDIT_MASK 0xf000000 +#define SDMA1_ATCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA1_ATCL1_CNTL__VADDR_WATERMK_MASK 0x70000000 +#define SDMA1_ATCL1_CNTL__VADDR_WATERMK__SHIFT 0x1c +#define SDMA1_ATCL1_WATERMK__REQMC_WATERMK_MASK 0x3ff +#define SDMA1_ATCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA1_ATCL1_WATERMK__REQPG_WATERMK_MASK 0x3fc00 +#define SDMA1_ATCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa +#define SDMA1_ATCL1_WATERMK__INVREQ_WATERMK_MASK 0xfc0000 +#define SDMA1_ATCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 +#define SDMA1_ATCL1_WATERMK__XNACK_WATERMK_MASK 0x7f000000 +#define SDMA1_ATCL1_WATERMK__XNACK_WATERMK__SHIFT 0x18 +#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1 +#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2 +#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4 +#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8 +#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10 +#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20 +#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40 +#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80 +#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100 +#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200 +#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400 +#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x800 +#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000 +#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000 +#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000 +#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000 +#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000 +#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000 +#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_ATCL1_RD_STATUS__ALL_IDLE_MASK 0x40000 +#define SDMA1_ATCL1_RD_STATUS__ALL_IDLE__SHIFT 0x12 +#define SDMA1_ATCL1_RD_STATUS__REQL2_IDLE_MASK 0x80000 +#define SDMA1_ATCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x13 +#define SDMA1_ATCL1_RD_STATUS__REQMC_IDLE_MASK 0x100000 +#define SDMA1_ATCL1_RD_STATUS__REQMC_IDLE__SHIFT 0x14 +#define SDMA1_ATCL1_RD_STATUS__CE_L1_STALL_MASK 0x200000 +#define SDMA1_ATCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA1_ATCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x3c00000 +#define SDMA1_ATCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA1_ATCL1_RD_STATUS__MERGE_STATE_MASK 0x1c000000 +#define SDMA1_ATCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA1_ATCL1_RD_STATUS__RESERVED_MASK 0xe0000000 +#define SDMA1_ATCL1_RD_STATUS__RESERVED__SHIFT 0x1d +#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1 +#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2 +#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4 +#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8 +#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10 +#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20 +#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40 +#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80 +#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100 +#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200 +#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400 +#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x800 +#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000 +#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000 +#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000 +#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000 +#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000 +#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000 +#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_ATCL1_WR_STATUS__ALL_IDLE_MASK 0x40000 +#define SDMA1_ATCL1_WR_STATUS__ALL_IDLE__SHIFT 0x12 +#define SDMA1_ATCL1_WR_STATUS__REQL2_IDLE_MASK 0x80000 +#define SDMA1_ATCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x13 +#define SDMA1_ATCL1_WR_STATUS__REQMC_IDLE_MASK 0x100000 +#define SDMA1_ATCL1_WR_STATUS__REQMC_IDLE__SHIFT 0x14 +#define SDMA1_ATCL1_WR_STATUS__F32_WR_RTR_MASK 0x200000 +#define SDMA1_ATCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA1_ATCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x3c00000 +#define SDMA1_ATCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA1_ATCL1_WR_STATUS__MERGE_STATE_MASK 0x1c000000 +#define SDMA1_ATCL1_WR_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA1_ATCL1_WR_STATUS__RESERVED_MASK 0xe0000000 +#define SDMA1_ATCL1_WR_STATUS__RESERVED__SHIFT 0x1d +#define SDMA1_ATCL1_INV0__INV_MIDDLE_MASK 0x1 +#define SDMA1_ATCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA1_ATCL1_INV0__RD_TIMEOUT_MASK 0x2 +#define SDMA1_ATCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA1_ATCL1_INV0__WR_TIMEOUT_MASK 0x4 +#define SDMA1_ATCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA1_ATCL1_INV0__RD_IN_INVADR_MASK 0x8 +#define SDMA1_ATCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA1_ATCL1_INV0__WR_IN_INVADR_MASK 0x10 +#define SDMA1_ATCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA1_ATCL1_INV0__RD_WT_INVADR_MASK 0x20 +#define SDMA1_ATCL1_INV0__RD_WT_INVADR__SHIFT 0x5 +#define SDMA1_ATCL1_INV0__WR_WT_INVADR_MASK 0x40 +#define SDMA1_ATCL1_INV0__WR_WT_INVADR__SHIFT 0x6 +#define SDMA1_ATCL1_INV0__RD_INV_EN_MASK 0x80 +#define SDMA1_ATCL1_INV0__RD_INV_EN__SHIFT 0x7 +#define SDMA1_ATCL1_INV0__WR_INV_EN_MASK 0x100 +#define SDMA1_ATCL1_INV0__WR_INV_EN__SHIFT 0x8 +#define SDMA1_ATCL1_INV0__RD_INV_IDLE_MASK 0x200 +#define SDMA1_ATCL1_INV0__RD_INV_IDLE__SHIFT 0x9 +#define SDMA1_ATCL1_INV0__WR_INV_IDLE_MASK 0x400 +#define SDMA1_ATCL1_INV0__WR_INV_IDLE__SHIFT 0xa +#define SDMA1_ATCL1_INV0__INV_FLUSHTYPE_MASK 0x800 +#define SDMA1_ATCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA1_ATCL1_INV0__INV_VMID_VEC_MASK 0xffff000 +#define SDMA1_ATCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA1_ATCL1_INV0__INV_ADDR_HI_MASK 0xf0000000 +#define SDMA1_ATCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA1_ATCL1_INV1__INV_ADDR_LO_MASK 0xffffffff +#define SDMA1_ATCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA1_ATCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xffff +#define SDMA1_ATCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA1_ATCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff +#define SDMA1_ATCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_ATCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0xf +#define SDMA1_ATCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_ATCL1_RD_XNACK1__XNACK_VMID_MASK 0xf0 +#define SDMA1_ATCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_ATCL1_RD_XNACK1__IS_XNACK_MASK 0x100 +#define SDMA1_ATCL1_RD_XNACK1__IS_XNACK__SHIFT 0x8 +#define SDMA1_ATCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff +#define SDMA1_ATCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_ATCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0xf +#define SDMA1_ATCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_ATCL1_WR_XNACK1__XNACK_VMID_MASK 0xf0 +#define SDMA1_ATCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_ATCL1_WR_XNACK1__IS_XNACK_MASK 0x100 +#define SDMA1_ATCL1_WR_XNACK1__IS_XNACK__SHIFT 0x8 +#define SDMA1_ATCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0xffff +#define SDMA1_ATCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA1_ATCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xffff0000 +#define SDMA1_ATCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0xffff +#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0xff0000 +#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xff000000 +#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL__SHIFT 0x0 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT_MASK 0x4 +#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2 +#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 +#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x4 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x8 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x10 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x100 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x200 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x400 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x800 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x1000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x2000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x4000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x8000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x10000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x20000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x40000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x80000 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA1_CONTEXT_REG_TYPE0__RESERVED_MASK 0xfff00000 +#define SDMA1_CONTEXT_REG_TYPE0__RESERVED__SHIFT 0x14 +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0_MASK 0x7f +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR_MASK 0x80 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL_MASK 0x100 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x200 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x400 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x800 +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x1000 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x2000 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3_MASK 0x4000 +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x8000 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x10000 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x20000 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x4 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x8 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x10 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x20 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x40 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x80 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x100 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x200 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xfffffc00 +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x4 +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x8 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG_MASK 0x40 +#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH_MASK 0x80 +#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 +#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH_MASK 0x400 +#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH_MASK 0x800 +#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM_MASK 0x1000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG_MASK 0x2000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG_MASK 0x4000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL_MASK 0x8000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 +#define SDMA1_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 +#define SDMA1_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL_MASK 0x40000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE_MASK 0x80000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM_MASK 0x100000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM_MASK 0x200000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE0__VOID_REG0_MASK 0x3c00000 +#define SDMA1_PUB_REG_TYPE0__VOID_REG0__SHIFT 0x16 +#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG_MASK 0x4000000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD_MASK 0x8000000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID_MASK 0x10000000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION_MASK 0x20000000 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 +#define SDMA1_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI_MASK 0x4 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x8 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID_MASK 0x10 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL_MASK 0x20 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ_MASK 0x40 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE_MASK 0x80 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x100 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x200 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x400 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_CNTL_MASK 0x800 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_CNTL__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_WATERMK_MASK 0x1000 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_WATERMK__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_TIMEOUT_MASK 0x2000 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_TIMEOUT__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE1__RESERVED_MASK 0xffffc000 +#define SDMA1_PUB_REG_TYPE1__RESERVED__SHIFT 0xe +#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_GFX_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA1_GFX_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 +#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 +#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xffffffff +#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xffffffff +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e +#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 +#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff +#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc +#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc +#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 +#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff +#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff +#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000 +#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 +#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 +#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 +#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 +#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 +#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 +#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 +#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 +#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 +#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 +#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e +#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff +#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0 +#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 +#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc +#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff +#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xffffffff +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7 +#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0 +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8 +#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3 +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600 +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000 +#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16 +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000 +#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17 +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000 +#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000 +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000 +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f +#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff +#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0 +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1 +#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0 +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e +#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1 +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60 +#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5 +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380 +#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000 +#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd +#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000 +#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000 +#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11 +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000 +#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000 +#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18 +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000 +#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000 +#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000 +#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff +#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0 +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800 +#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1 +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 +#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 +#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0 +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 +#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe +#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1 +#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30 +#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4 +#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0 +#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6 +#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700 +#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8 +#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800 +#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb +#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000 +#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7 +#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0 +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18 +#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3 +#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff +#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 +#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00 +#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 +#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1 +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 +#define HDP_MISC_CNTL__VM_ID_MASK 0x1e +#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1 +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20 +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 +#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40 +#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780 +#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000 +#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000 +#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000 +#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13 +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000 +#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14 +#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000 +#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 +#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE_MASK 0x400000 +#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE__SHIFT 0x16 +#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE_MASK 0x800000 +#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE__SHIFT 0x17 +#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1 +#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 +#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e +#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1 +#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80 +#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000 +#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b +#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1 +#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 +#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2 +#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 +#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c +#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000 +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000 +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf +#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x10000 +#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 +#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x1e0000 +#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 +#define HDP_VF_ENABLE__VF_EN_MASK 0x1 +#define HDP_VF_ENABLE__VF_EN__SHIFT 0x0 +#define HDP_VF_ENABLE__VF_NUM_MASK 0xffff0000 +#define HDP_VF_ENABLE__VF_NUM__SHIFT 0x10 +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 +#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff +#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1 +#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe +#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6 +#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1 +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18 +#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80 +#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000 +#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f +#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff +#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000 +#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000 +#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 +#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff +#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 +#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff +#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 +#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000 +#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 +#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff +#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 +#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00 +#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 +#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000 +#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 +#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000 +#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 +#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff +#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0 +#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10 +#define HDP_XDP_DBG_DATA__STS_MASK 0xffff +#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0 +#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10 +#define HDP_XDP_DBG_MASK__STS_MASK 0xffff +#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0 +#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000 +#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10 +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000 +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c + +#endif /* OSS_3_0_1_SH_MASK_H */ -- cgit v1.2.3 From 9b289c2610c8d0e595c19d4dca318bb43b891841 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:28:58 -0400 Subject: drm/amdgpu: add SMU 7.0.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h | 741 ++++ .../amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h | 3842 ++++++++++++++++++++ 2 files changed, 4583 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h new file mode 100644 index 000000000000..f67560b82fe9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h @@ -0,0 +1,741 @@ +/* + * SMU_7_0_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_0_0_D_H +#define SMU_7_0_0_D_H + +#define mmGCK_SMC_IND_INDEX 0x80 +#define mmGCK0_GCK_SMC_IND_INDEX 0x80 +#define mmGCK1_GCK_SMC_IND_INDEX 0x82 +#define mmGCK2_GCK_SMC_IND_INDEX 0x84 +#define mmGCK3_GCK_SMC_IND_INDEX 0x86 +#define mmGCK_SMC_IND_DATA 0x81 +#define mmGCK0_GCK_SMC_IND_DATA 0x81 +#define mmGCK1_GCK_SMC_IND_DATA 0x83 +#define mmGCK2_GCK_SMC_IND_DATA 0x85 +#define mmGCK3_GCK_SMC_IND_DATA 0x87 +#define ixCG_DCLK_CNTL 0xc050009c +#define ixCG_DCLK_STATUS 0xc05000a0 +#define ixCG_VCLK_CNTL 0xc05000a4 +#define ixCG_VCLK_STATUS 0xc05000a8 +#define ixCG_ECLK_CNTL 0xc05000ac +#define ixCG_ECLK_STATUS 0xc05000b0 +#define ixCG_ACLK_CNTL 0xc05000dc +#define ixGCK_DFS_BYPASS_CNTL 0xc0500118 +#define ixCG_SPLL_FUNC_CNTL 0xc0500140 +#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 +#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 +#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c +#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 +#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 +#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 +#define ixSPLL_CNTL_MODE 0xc0500160 +#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 +#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +#define ixMPLL_BYPASSCLK_SEL 0xc050019c +#define ixCG_CLKPIN_CNTL 0xc05001a0 +#define ixCG_CLKPIN_CNTL_2 0xc05001a4 +#define ixTHM_CLK_CNTL 0xc05001a8 +#define ixMISC_CLK_CTRL 0xc05001ac +#define ixGCK_PLL_TEST_CNTL 0xc05001c0 +#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 +#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 +#define mmSMC_IND_INDEX 0x80 +#define mmSMC0_SMC_IND_INDEX 0x80 +#define mmSMC1_SMC_IND_INDEX 0x82 +#define mmSMC2_SMC_IND_INDEX 0x84 +#define mmSMC3_SMC_IND_INDEX 0x86 +#define mmSMC_IND_DATA 0x81 +#define mmSMC0_SMC_IND_DATA 0x81 +#define mmSMC1_SMC_IND_DATA 0x83 +#define mmSMC2_SMC_IND_DATA 0x85 +#define mmSMC3_SMC_IND_DATA 0x87 +#define mmSMC_IND_INDEX_0 0x80 +#define mmSMC_IND_DATA_0 0x81 +#define mmSMC_IND_INDEX_1 0x82 +#define mmSMC_IND_DATA_1 0x83 +#define mmSMC_IND_INDEX_2 0x84 +#define mmSMC_IND_DATA_2 0x85 +#define mmSMC_IND_INDEX_3 0x86 +#define mmSMC_IND_DATA_3 0x87 +#define mmSMC_IND_INDEX_4 0x88 +#define mmSMC_IND_DATA_4 0x89 +#define mmSMC_IND_INDEX_5 0x8a +#define mmSMC_IND_DATA_5 0x8b +#define mmSMC_IND_INDEX_6 0x8c +#define mmSMC_IND_DATA_6 0x8d +#define mmSMC_IND_INDEX_7 0x8e +#define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_ACCESS_CNTL 0x90 +#define mmSMC_MESSAGE_0 0x94 +#define mmSMC_RESP_0 0x95 +#define mmSMC_MESSAGE_1 0x96 +#define mmSMC_RESP_1 0x97 +#define mmSMC_MESSAGE_2 0x98 +#define mmSMC_RESP_2 0x99 +#define mmSMC_MESSAGE_3 0x9a +#define mmSMC_RESP_3 0x9b +#define mmSMC_MESSAGE_4 0x9c +#define mmSMC_RESP_4 0x9d +#define mmSMC_MESSAGE_5 0x9e +#define mmSMC_RESP_5 0x9f +#define mmSMC_MESSAGE_6 0xa0 +#define mmSMC_RESP_6 0xa1 +#define mmSMC_MESSAGE_7 0xa2 +#define mmSMC_RESP_7 0xa3 +#define mmSMC_MSG_ARG_0 0xa4 +#define mmSMC_MSG_ARG_1 0xa5 +#define mmSMC_MSG_ARG_2 0xa6 +#define mmSMC_MSG_ARG_3 0xa7 +#define mmSMC_MSG_ARG_4 0xa8 +#define mmSMC_MSG_ARG_5 0xa9 +#define mmSMC_MSG_ARG_6 0xaa +#define mmSMC_MSG_ARG_7 0xab +#define mmSMC_MESSAGE_8 0xb5 +#define mmSMC_RESP_8 0xb6 +#define mmSMC_MESSAGE_9 0xb7 +#define mmSMC_RESP_9 0xb8 +#define mmSMC_MESSAGE_10 0xb9 +#define mmSMC_RESP_10 0xba +#define mmSMC_MESSAGE_11 0xbb +#define mmSMC_RESP_11 0xbc +#define mmSMC_MSG_ARG_8 0xbd +#define mmSMC_MSG_ARG_9 0xbe +#define mmSMC_MSG_ARG_10 0xbf +#define mmSMC_MSG_ARG_11 0x91 +#define ixSMC_SYSCON_RESET_CNTL 0x80000000 +#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 +#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 +#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c +#define ixSMC_SYSCON_MISC_CNTL 0x80000010 +#define ixSMC_SYSCON_MSG_ARG_0 0x80000068 +#define ixSMC_PC_C 0x80000370 +#define ixSMC_SCRATCH9 0x80000424 +#define mmCG_FPS_CNT 0x1a4 +#define mmSMU_SMC_IND_INDEX 0x80 +#define mmSMU0_SMU_SMC_IND_INDEX 0x80 +#define mmSMU1_SMU_SMC_IND_INDEX 0x82 +#define mmSMU2_SMU_SMC_IND_INDEX 0x84 +#define mmSMU3_SMU_SMC_IND_INDEX 0x86 +#define mmSMU_SMC_IND_DATA 0x81 +#define mmSMU0_SMU_SMC_IND_DATA 0x81 +#define mmSMU1_SMU_SMC_IND_DATA 0x83 +#define mmSMU2_SMU_SMC_IND_DATA 0x85 +#define mmSMU3_SMU_SMC_IND_DATA 0x87 +#define ixRCU_UC_EVENTS 0xc0000004 +#define ixRCU_MISC_CTRL 0xc0000010 +#define ixCC_RCU_FUSES 0xc00c0000 +#define ixCC_SMU_MISC_FUSES 0xc00c0004 +#define ixCC_SCLK_VID_FUSES 0xc00c0008 +#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c +#define ixCC_GIO_IOC_FUSES 0xc00c0010 +#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c +#define ixCC_TST_ID_STRAPS 0xc00c0020 +#define ixCC_FCTRL_FUSES 0xc00c0024 +#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 +#define ixSMU_STATUS 0xe0003088 +#define ixSMU_FIRMWARE 0xe00030a4 +#define ixSMU_INPUT_DATA 0xe00030b8 +#define ixSMU_EFUSE_0 0xc0100000 +#define ixDPM_TABLE_1 0x3f000 +#define ixDPM_TABLE_2 0x3f004 +#define ixDPM_TABLE_3 0x3f008 +#define ixDPM_TABLE_4 0x3f00c +#define ixDPM_TABLE_5 0x3f010 +#define ixDPM_TABLE_6 0x3f014 +#define ixDPM_TABLE_7 0x3f018 +#define ixDPM_TABLE_8 0x3f01c +#define ixDPM_TABLE_9 0x3f020 +#define ixDPM_TABLE_10 0x3f024 +#define ixDPM_TABLE_11 0x3f028 +#define ixDPM_TABLE_12 0x3f02c +#define ixDPM_TABLE_13 0x3f030 +#define ixDPM_TABLE_14 0x3f034 +#define ixDPM_TABLE_15 0x3f038 +#define ixDPM_TABLE_16 0x3f03c +#define ixDPM_TABLE_17 0x3f040 +#define ixDPM_TABLE_18 0x3f044 +#define ixDPM_TABLE_19 0x3f048 +#define ixDPM_TABLE_20 0x3f04c +#define ixDPM_TABLE_21 0x3f050 +#define ixDPM_TABLE_22 0x3f054 +#define ixDPM_TABLE_23 0x3f058 +#define ixDPM_TABLE_24 0x3f05c +#define ixDPM_TABLE_25 0x3f060 +#define ixDPM_TABLE_26 0x3f064 +#define ixDPM_TABLE_27 0x3f068 +#define ixDPM_TABLE_28 0x3f06c +#define ixDPM_TABLE_29 0x3f070 +#define ixDPM_TABLE_30 0x3f074 +#define ixDPM_TABLE_31 0x3f078 +#define ixDPM_TABLE_32 0x3f07c +#define ixDPM_TABLE_33 0x3f080 +#define ixDPM_TABLE_34 0x3f084 +#define ixDPM_TABLE_35 0x3f088 +#define ixDPM_TABLE_36 0x3f08c +#define ixDPM_TABLE_37 0x3f090 +#define ixDPM_TABLE_38 0x3f094 +#define ixDPM_TABLE_39 0x3f098 +#define ixDPM_TABLE_40 0x3f09c +#define ixDPM_TABLE_41 0x3f0a0 +#define ixDPM_TABLE_42 0x3f0a4 +#define ixDPM_TABLE_43 0x3f0a8 +#define ixDPM_TABLE_44 0x3f0ac +#define ixDPM_TABLE_45 0x3f0b0 +#define ixDPM_TABLE_46 0x3f0b4 +#define ixDPM_TABLE_47 0x3f0b8 +#define ixDPM_TABLE_48 0x3f0bc +#define ixDPM_TABLE_49 0x3f0c0 +#define ixDPM_TABLE_50 0x3f0c4 +#define ixDPM_TABLE_51 0x3f0c8 +#define ixDPM_TABLE_52 0x3f0cc +#define ixDPM_TABLE_53 0x3f0d0 +#define ixDPM_TABLE_54 0x3f0d4 +#define ixDPM_TABLE_55 0x3f0d8 +#define ixDPM_TABLE_56 0x3f0dc +#define ixDPM_TABLE_57 0x3f0e0 +#define ixDPM_TABLE_58 0x3f0e4 +#define ixDPM_TABLE_59 0x3f0e8 +#define ixDPM_TABLE_60 0x3f0ec +#define ixDPM_TABLE_61 0x3f0f0 +#define ixDPM_TABLE_62 0x3f0f4 +#define ixDPM_TABLE_63 0x3f0f8 +#define ixDPM_TABLE_64 0x3f0fc +#define ixDPM_TABLE_65 0x3f100 +#define ixDPM_TABLE_66 0x3f104 +#define ixDPM_TABLE_67 0x3f108 +#define ixDPM_TABLE_68 0x3f10c +#define ixDPM_TABLE_69 0x3f110 +#define ixDPM_TABLE_70 0x3f114 +#define ixDPM_TABLE_71 0x3f118 +#define ixDPM_TABLE_72 0x3f11c +#define ixDPM_TABLE_73 0x3f120 +#define ixDPM_TABLE_74 0x3f124 +#define ixDPM_TABLE_75 0x3f128 +#define ixDPM_TABLE_76 0x3f12c +#define ixDPM_TABLE_77 0x3f130 +#define ixDPM_TABLE_78 0x3f134 +#define ixDPM_TABLE_79 0x3f138 +#define ixDPM_TABLE_80 0x3f13c +#define ixDPM_TABLE_81 0x3f140 +#define ixDPM_TABLE_82 0x3f144 +#define ixDPM_TABLE_83 0x3f148 +#define ixDPM_TABLE_84 0x3f14c +#define ixDPM_TABLE_85 0x3f150 +#define ixDPM_TABLE_86 0x3f154 +#define ixDPM_TABLE_87 0x3f158 +#define ixDPM_TABLE_88 0x3f15c +#define ixDPM_TABLE_89 0x3f160 +#define ixDPM_TABLE_90 0x3f164 +#define ixDPM_TABLE_91 0x3f168 +#define ixDPM_TABLE_92 0x3f16c +#define ixDPM_TABLE_93 0x3f170 +#define ixDPM_TABLE_94 0x3f174 +#define ixDPM_TABLE_95 0x3f178 +#define ixDPM_TABLE_96 0x3f17c +#define ixDPM_TABLE_97 0x3f180 +#define ixDPM_TABLE_98 0x3f184 +#define ixDPM_TABLE_99 0x3f188 +#define ixDPM_TABLE_100 0x3f18c +#define ixDPM_TABLE_101 0x3f190 +#define ixDPM_TABLE_102 0x3f194 +#define ixDPM_TABLE_103 0x3f198 +#define ixDPM_TABLE_104 0x3f19c +#define ixDPM_TABLE_105 0x3f1a0 +#define ixDPM_TABLE_106 0x3f1a4 +#define ixDPM_TABLE_107 0x3f1a8 +#define ixDPM_TABLE_108 0x3f1ac +#define ixDPM_TABLE_109 0x3f1b0 +#define ixDPM_TABLE_110 0x3f1b4 +#define ixDPM_TABLE_111 0x3f1b8 +#define ixDPM_TABLE_112 0x3f1bc +#define ixDPM_TABLE_113 0x3f1c0 +#define ixDPM_TABLE_114 0x3f1c4 +#define ixDPM_TABLE_115 0x3f1c8 +#define ixDPM_TABLE_116 0x3f1cc +#define ixDPM_TABLE_117 0x3f1d0 +#define ixDPM_TABLE_118 0x3f1d4 +#define ixDPM_TABLE_119 0x3f1d8 +#define ixDPM_TABLE_120 0x3f1dc +#define ixDPM_TABLE_121 0x3f1e0 +#define ixDPM_TABLE_122 0x3f1e4 +#define ixDPM_TABLE_123 0x3f1e8 +#define ixDPM_TABLE_124 0x3f1ec +#define ixDPM_TABLE_125 0x3f1f0 +#define ixDPM_TABLE_126 0x3f1f4 +#define ixDPM_TABLE_127 0x3f1f8 +#define ixDPM_TABLE_128 0x3f1fc +#define ixDPM_TABLE_129 0x3f200 +#define ixDPM_TABLE_130 0x3f204 +#define ixDPM_TABLE_131 0x3f208 +#define ixDPM_TABLE_132 0x3f20c +#define ixDPM_TABLE_133 0x3f210 +#define ixDPM_TABLE_134 0x3f214 +#define ixDPM_TABLE_135 0x3f218 +#define ixDPM_TABLE_136 0x3f21c +#define ixDPM_TABLE_137 0x3f220 +#define ixDPM_TABLE_138 0x3f224 +#define ixDPM_TABLE_139 0x3f228 +#define ixDPM_TABLE_140 0x3f22c +#define ixDPM_TABLE_141 0x3f230 +#define ixDPM_TABLE_142 0x3f234 +#define ixDPM_TABLE_143 0x3f238 +#define ixDPM_TABLE_144 0x3f23c +#define ixDPM_TABLE_145 0x3f240 +#define ixDPM_TABLE_146 0x3f244 +#define ixDPM_TABLE_147 0x3f248 +#define ixDPM_TABLE_148 0x3f24c +#define ixDPM_TABLE_149 0x3f250 +#define ixDPM_TABLE_150 0x3f254 +#define ixDPM_TABLE_151 0x3f258 +#define ixDPM_TABLE_152 0x3f25c +#define ixDPM_TABLE_153 0x3f260 +#define ixDPM_TABLE_154 0x3f264 +#define ixDPM_TABLE_155 0x3f268 +#define ixDPM_TABLE_156 0x3f26c +#define ixDPM_TABLE_157 0x3f270 +#define ixDPM_TABLE_158 0x3f274 +#define ixDPM_TABLE_159 0x3f278 +#define ixDPM_TABLE_160 0x3f27c +#define ixDPM_TABLE_161 0x3f280 +#define ixDPM_TABLE_162 0x3f284 +#define ixDPM_TABLE_163 0x3f288 +#define ixDPM_TABLE_164 0x3f28c +#define ixDPM_TABLE_165 0x3f290 +#define ixDPM_TABLE_166 0x3f294 +#define ixDPM_TABLE_167 0x3f298 +#define ixDPM_TABLE_168 0x3f29c +#define ixDPM_TABLE_169 0x3f2a0 +#define ixDPM_TABLE_170 0x3f2a4 +#define ixDPM_TABLE_171 0x3f2a8 +#define ixDPM_TABLE_172 0x3f2ac +#define ixDPM_TABLE_173 0x3f2b0 +#define ixDPM_TABLE_174 0x3f2b4 +#define ixDPM_TABLE_175 0x3f2b8 +#define ixDPM_TABLE_176 0x3f2bc +#define ixDPM_TABLE_177 0x3f2c0 +#define ixDPM_TABLE_178 0x3f2c4 +#define ixDPM_TABLE_179 0x3f2c8 +#define ixDPM_TABLE_180 0x3f2cc +#define ixDPM_TABLE_181 0x3f2d0 +#define ixDPM_TABLE_182 0x3f2d4 +#define ixDPM_TABLE_183 0x3f2d8 +#define ixDPM_TABLE_184 0x3f2dc +#define ixDPM_TABLE_185 0x3f2e0 +#define ixDPM_TABLE_186 0x3f2e4 +#define ixDPM_TABLE_187 0x3f2e8 +#define ixDPM_TABLE_188 0x3f2ec +#define ixDPM_TABLE_189 0x3f2f0 +#define ixDPM_TABLE_190 0x3f2f4 +#define ixDPM_TABLE_191 0x3f2f8 +#define ixSOFT_REGISTERS_TABLE_1 0x3f900 +#define ixSOFT_REGISTERS_TABLE_2 0x3f904 +#define ixSOFT_REGISTERS_TABLE_3 0x3f908 +#define ixSOFT_REGISTERS_TABLE_4 0x3f90c +#define ixSOFT_REGISTERS_TABLE_5 0x3f910 +#define ixSOFT_REGISTERS_TABLE_6 0x3f914 +#define ixSOFT_REGISTERS_TABLE_7 0x3f918 +#define ixSOFT_REGISTERS_TABLE_8 0x3f91c +#define ixSOFT_REGISTERS_TABLE_9 0x3f920 +#define ixSOFT_REGISTERS_TABLE_10 0x3f924 +#define ixSOFT_REGISTERS_TABLE_11 0x3f928 +#define ixSOFT_REGISTERS_TABLE_12 0x3f92c +#define ixSOFT_REGISTERS_TABLE_13 0x3f930 +#define ixSOFT_REGISTERS_TABLE_14 0x3f934 +#define ixSOFT_REGISTERS_TABLE_15 0x3f938 +#define ixSOFT_REGISTERS_TABLE_16 0x3f93c +#define ixSOFT_REGISTERS_TABLE_17 0x3f940 +#define ixSOFT_REGISTERS_TABLE_18 0x3f944 +#define ixSOFT_REGISTERS_TABLE_19 0x3f948 +#define ixSOFT_REGISTERS_TABLE_20 0x3f94c +#define ixSOFT_REGISTERS_TABLE_21 0x3f950 +#define ixSMU_LCLK_DPM_STATE_0_CNTL_0 0x3fd00 +#define ixSMU_LCLK_DPM_STATE_1_CNTL_0 0x3fd14 +#define ixSMU_LCLK_DPM_STATE_2_CNTL_0 0x3fd28 +#define ixSMU_LCLK_DPM_STATE_3_CNTL_0 0x3fd3c +#define ixSMU_LCLK_DPM_STATE_4_CNTL_0 0x3fd50 +#define ixSMU_LCLK_DPM_STATE_5_CNTL_0 0x3fd64 +#define ixSMU_LCLK_DPM_STATE_6_CNTL_0 0x3fd78 +#define ixSMU_LCLK_DPM_STATE_7_CNTL_0 0x3fd8c +#define ixSMU_LCLK_DPM_STATE_0_CNTL_1 0x3fd04 +#define ixSMU_LCLK_DPM_STATE_1_CNTL_1 0x3fd18 +#define ixSMU_LCLK_DPM_STATE_2_CNTL_1 0x3fd2c +#define ixSMU_LCLK_DPM_STATE_3_CNTL_1 0x3fd40 +#define ixSMU_LCLK_DPM_STATE_4_CNTL_1 0x3fd54 +#define ixSMU_LCLK_DPM_STATE_5_CNTL_1 0x3fd68 +#define ixSMU_LCLK_DPM_STATE_6_CNTL_1 0x3fd7c +#define ixSMU_LCLK_DPM_STATE_7_CNTL_1 0x3fd90 +#define ixSMU_LCLK_DPM_STATE_0_CNTL_2 0x3fd08 +#define ixSMU_LCLK_DPM_STATE_1_CNTL_2 0x3fd1c +#define ixSMU_LCLK_DPM_STATE_2_CNTL_2 0x3fd30 +#define ixSMU_LCLK_DPM_STATE_3_CNTL_2 0x3fd44 +#define ixSMU_LCLK_DPM_STATE_4_CNTL_2 0x3fd58 +#define ixSMU_LCLK_DPM_STATE_5_CNTL_2 0x3fd6c +#define ixSMU_LCLK_DPM_STATE_6_CNTL_2 0x3fd80 +#define ixSMU_LCLK_DPM_STATE_7_CNTL_2 0x3fd94 +#define ixSMU_LCLK_DPM_STATE_0_CNTL_3 0x3fd0c +#define ixSMU_LCLK_DPM_STATE_1_CNTL_3 0x3fd20 +#define ixSMU_LCLK_DPM_STATE_2_CNTL_3 0x3fd34 +#define ixSMU_LCLK_DPM_STATE_3_CNTL_3 0x3fd48 +#define ixSMU_LCLK_DPM_STATE_4_CNTL_3 0x3fd5c +#define ixSMU_LCLK_DPM_STATE_5_CNTL_3 0x3fd70 +#define ixSMU_LCLK_DPM_STATE_6_CNTL_3 0x3fd84 +#define ixSMU_LCLK_DPM_STATE_7_CNTL_3 0x3fd98 +#define ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD 0x3fd10 +#define ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD 0x3fd24 +#define ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD 0x3fd38 +#define ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD 0x3fd4c +#define ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD 0x3fd60 +#define ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD 0x3fd74 +#define ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD 0x3fd88 +#define ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD 0x3fd9c +#define ixGIO_PID_CONTROLLER_CNTL_0 0x3fda0 +#define ixGIO_PID_CONTROLLER_CNTL_1 0x3fda4 +#define ixGIO_PID_CONTROLLER_CNTL_2 0x3fda8 +#define ixGIO_PID_CONTROLLER_CNTL_3 0x3fdac +#define ixGIO_PID_CONTROLLER_CNTL_4 0x3fdb0 +#define ixGIO_PID_CONTROLLER_CNTL_5 0x3fdb4 +#define ixGIO_PID_CONTROLLER_CNTL_6 0x3fdb8 +#define ixGIO_PID_CONTROLLER_CNTL_7 0x3fdbc +#define ixGIO_PID_CONTROLLER_CNTL_8 0x3fdc0 +#define ixSMU_LCLK_DPM_LEVEL_COUNT 0x3fdc4 +#define ixSMU_LCLK_DPM_CNTL 0x3fdc8 +#define ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE 0x3fdcc +#define ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL 0x3fdd0 +#define ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS 0x3fdd4 +#define ixPM_FUSES_1 0x3fa80 +#define ixPM_FUSES_2 0x3fa84 +#define ixPM_FUSES_3 0x3fa88 +#define ixPM_FUSES_4 0x3fa8c +#define ixPM_FUSES_5 0x3fa90 +#define ixPM_FUSES_6 0x3fa94 +#define ixPM_FUSES_7 0x3fa98 +#define ixPM_FUSES_8 0x3fa9c +#define ixPM_FUSES_9 0x3faa0 +#define ixPM_FUSES_10 0x3faa4 +#define ixPM_FUSES_11 0x3faa8 +#define ixPM_FUSES_12 0x3faac +#define ixPM_FUSES_13 0x3fab0 +#define ixPM_FUSES_14 0x3fab4 +#define ixPM_FUSES_15 0x3fab8 +#define ixPM_FUSES_16 0x3fabc +#define ixPM_FUSES_17 0x3fac0 +#define ixPM_FUSES_18 0x3fac4 +#define ixPM_FUSES_19 0x3fac8 +#define ixPM_FUSES_20 0x3facc +#define ixPM_FUSES_21 0x3fad0 +#define ixPM_FUSES_22 0x3fad4 +#define ixPM_FUSES_23 0x3fad8 +#define ixPM_FUSES_24 0x3fadc +#define ixPM_FUSES_25 0x3fae0 +#define ixPM_FUSES_26 0x3fae4 +#define ixPM_FUSES_27 0x3fae8 +#define ixPM_FUSES_28 0x3faec +#define ixPM_FUSES_29 0x3faf0 +#define ixPM_FUSES_30 0x3faf4 +#define ixPM_FUSES_31 0x3faf8 +#define ixPM_FUSES_32 0x3fafc +#define ixPM_FUSES_33 0x3fb00 +#define ixPM_FUSES_34 0x3fb04 +#define ixPM_FUSES_35 0x3fb08 +#define ixPM_FUSES_36 0x3fb0c +#define ixPM_FUSES_37 0x3fb10 +#define ixPM_FUSES_38 0x3fb14 +#define ixPM_FUSES_39 0x3fb18 +#define ixPM_FUSES_40 0x3fb1c +#define ixPM_FUSES_41 0x3fb20 +#define ixPM_FUSES_42 0x3fb24 +#define ixPM_FUSES_43 0x3fb28 +#define ixPM_FUSES_44 0x3fb2c +#define ixPM_FUSES_45 0x3fb30 +#define ixPM_FUSES_46 0x3fb34 +#define ixPM_FUSES_47 0x3fb38 +#define ixPM_FUSES_48 0x3fb3c +#define ixPM_FUSES_49 0x3fb40 +#define ixPM_FUSES_50 0x3fb44 +#define ixPM_FUSES_51 0x3fb48 +#define ixPM_FUSES_52 0x3fb4c +#define ixPM_FUSES_53 0x3fb50 +#define ixPM_FUSES_54 0x3fb54 +#define ixPM_FUSES_55 0x3fb58 +#define ixPM_FUSES_56 0x3fb5c +#define ixPM_FUSES_57 0x3fb60 +#define ixPM_FUSES_58 0x3fb64 +#define ixPM_FUSES_59 0x3fb68 +#define ixPM_FUSES_60 0x3fb6c +#define ixPM_FUSES_61 0x3fb70 +#define ixPM_FUSES_62 0x3fb74 +#define ixPM_FUSES_63 0x3fb78 +#define ixPM_FUSES_64 0x3fb7c +#define ixPM_FUSES_65 0x3fb80 +#define ixFIRMWARE_FLAGS 0x3f800 +#define ixTEMPERATURE_READ_ADDR 0x3f808 +#define ixCURRENT_GNB_TEMP 0x3f810 +#define ixCURRENT_GLOBAL_TEMP 0x3f814 +#define ixFEATURE_STATUS 0x3f818 +#define ixPCIE_PLL_RECONF 0x3f81c +#define ixPM_INTERVAL_CNTL_0 0x3f820 +#define ixPM_INTERVAL_CNTL_1 0x3f824 +#define ixPM_INTERVAL_CNTL_2 0x3f82c +#define ixVPC_INTERVAL_CNTL 0x3f830 +#define ixDISP_PHY_TDP_LIMIT 0x3f834 +#define ixFCH_PWR_CREDIT 0x3f838 +#define ixPKGPWR_MV_AVG 0x3f83c +#define ixPACKAGE_POWER 0x3f840 +#define ixPKG_PWR_CNTL 0x3f844 +#define ixPKG_PWR_STATUS 0x3f848 +#define ixDISP_PHY_CONFIG 0x3f84c +#define ixGPU_TDP_LIMIT 0x3f850 +#define ixEXT_API_IN_DATA_0_0 0x3f858 +#define ixEXT_API_IN_DATA_0_1 0x3f85c +#define ixEXT_API_IN_DATA_0_2 0x3f860 +#define ixEXT_API_IN_DATA_0_3 0x3f864 +#define ixEXT_API_OUT_DATA_0_0 0x3f868 +#define ixEXT_API_OUT_DATA_0_1 0x3f86c +#define ixEXT_API_OUT_DATA_0_2 0x3f870 +#define ixEXT_API_OUT_DATA_0_3 0x3f874 +#define ixBAPM_PARAMETERS 0x3f984 +#define ixBAPM_PARAMETERS_2 0x3f988 +#define ixBAPM_PARAMETERS_3 0x3f98c +#define ixBAPM_PARAMETERS_4 0x3f990 +#define ixSMU_SVI_TELEMETRY 0x3f994 +#define ixBAPM_STATUS 0x3f998 +#define ixSMU_HTC_STATUS 0x3f99c +#define ixSMU_VPC_STATUS 0x3f9a0 +#define ixENTITY_TEMPERATURES_1 0x3f9a4 +#define ixENTITY_TEMPERATURES_2 0x3f9a8 +#define ixENTITY_TEMPERATURES_3 0x3f9ac +#define ixCU_POWER 0x3f9b0 +#define ixGPU_POWER 0x3f9b4 +#define ixNTE_POWER 0x3f9b8 +#define ixTDC_STATUS 0x3f9d0 +#define ixTDC_MV_AVERAGE 0x3f9d4 +#define ixPM_CONFIG 0x3f9d8 +#define ixTE0_TEMPERATURE_READ_ADDR 0x3f9dc +#define ixTE1_TEMPERATURE_READ_ADDR 0x3f9e0 +#define ixTE2_TEMPERATURE_READ_ADDR 0x3f9e4 +#define ixNB_DPM_CONFIG_1 0x3f9e8 +#define ixNB_DPM_CONFIG_2 0x3f9ec +#define ixNB_DPM_CONFIG_3 0x3f9f0 +#define ixSMU_IDD_OVERRIDE 0x3f9fc +#define ixAVS_CONFIG 0x3fa00 +#define ixTDC_VRM_LIMIT 0x3fa04 +#define ixCU0_PSM_CONFIG 0x3fa08 +#define ixCU1_PSM_CONFIG 0x3fa0c +#define ixSPMI_CONFIG 0x3fa10 +#define ixSPMI_SMC_CHAIN_ADDR 0x3fa14 +#define ixSPMI_STATUS 0x3fa30 +#define ixAVSNB_CONFIG 0x3fa34 +#define ixHTC_CONFIG 0x3fa38 +#define ixAVS_CU0_TEMPERATURE_SENSOR 0x3fa3c +#define ixAVS_CU1_TEMPERATURE_SENSOR 0x3fa40 +#define ixAVS_GNB_TEMPERATURE_SENSOR 0x3fa44 +#define ixAVS_UNB_TEMPERATURE_SENSOR 0x3fa48 +#define ixSMU_MONITOR_PORT80_MMIO_ADDR 0x3fa4c +#define ixSMU_MONITOR_PORT80_MEMBASE_HI 0x3fa50 +#define ixSMU_MONITOR_PORT80_MEMBASE_LO 0x3fa54 +#define ixSMU_MONITOR_PORT80_MEMSETUP 0x3fa58 +#define ixSMU_MONITOR_PORT80_CTRL 0x3fa5c +#define ixSMU_TCEN_ALIVE 0x3fa60 +#define ixPDM_STATUS 0x3fa64 +#define ixPDM_CNTL_1 0x3fa68 +#define ixPDM_CNTL_2 0x3fa6c +#define ixPDM_CNTL_3 0x3fa70 +#define ixSMU_PM_STATUS_0 0x3fe00 +#define ixSMU_PM_STATUS_1 0x3fe04 +#define ixSMU_PM_STATUS_2 0x3fe08 +#define ixSMU_PM_STATUS_3 0x3fe0c +#define ixSMU_PM_STATUS_4 0x3fe10 +#define ixSMU_PM_STATUS_5 0x3fe14 +#define ixSMU_PM_STATUS_6 0x3fe18 +#define ixSMU_PM_STATUS_7 0x3fe1c +#define ixSMU_PM_STATUS_8 0x3fe20 +#define ixSMU_PM_STATUS_9 0x3fe24 +#define ixSMU_PM_STATUS_10 0x3fe28 +#define ixSMU_PM_STATUS_11 0x3fe2c +#define ixSMU_PM_STATUS_12 0x3fe30 +#define ixSMU_PM_STATUS_13 0x3fe34 +#define ixSMU_PM_STATUS_14 0x3fe38 +#define ixSMU_PM_STATUS_15 0x3fe3c +#define ixSMU_PM_STATUS_16 0x3fe40 +#define ixSMU_PM_STATUS_17 0x3fe44 +#define ixSMU_PM_STATUS_18 0x3fe48 +#define ixSMU_PM_STATUS_19 0x3fe4c +#define ixSMU_PM_STATUS_20 0x3fe50 +#define ixSMU_PM_STATUS_21 0x3fe54 +#define ixSMU_PM_STATUS_22 0x3fe58 +#define ixSMU_PM_STATUS_23 0x3fe5c +#define ixSMU_PM_STATUS_24 0x3fe60 +#define ixSMU_PM_STATUS_25 0x3fe64 +#define ixSMU_PM_STATUS_26 0x3fe68 +#define ixSMU_PM_STATUS_27 0x3fe6c +#define ixSMU_PM_STATUS_28 0x3fe70 +#define ixSMU_PM_STATUS_29 0x3fe74 +#define ixSMU_PM_STATUS_30 0x3fe78 +#define ixSMU_PM_STATUS_31 0x3fe7c +#define ixSMU_PM_STATUS_32 0x3fe80 +#define ixSMU_PM_STATUS_33 0x3fe84 +#define ixSMU_PM_STATUS_34 0x3fe88 +#define ixSMU_PM_STATUS_35 0x3fe8c +#define ixSMU_PM_STATUS_36 0x3fe90 +#define ixSMU_PM_STATUS_37 0x3fe94 +#define ixSMU_PM_STATUS_38 0x3fe98 +#define ixSMU_PM_STATUS_39 0x3fe9c +#define ixSMU_PM_STATUS_40 0x3fea0 +#define ixSMU_PM_STATUS_41 0x3fea4 +#define ixSMU_PM_STATUS_42 0x3fea8 +#define ixSMU_PM_STATUS_43 0x3feac +#define ixSMU_PM_STATUS_44 0x3feb0 +#define ixSMU_PM_STATUS_45 0x3feb4 +#define ixSMU_PM_STATUS_46 0x3feb8 +#define ixSMU_PM_STATUS_47 0x3febc +#define ixSMU_PM_STATUS_48 0x3fec0 +#define ixSMU_PM_STATUS_49 0x3fec4 +#define ixSMU_PM_STATUS_50 0x3fec8 +#define ixSMU_PM_STATUS_51 0x3fecc +#define ixSMU_PM_STATUS_52 0x3fed0 +#define ixSMU_PM_STATUS_53 0x3fed4 +#define ixSMU_PM_STATUS_54 0x3fed8 +#define ixSMU_PM_STATUS_55 0x3fedc +#define ixSMU_PM_STATUS_56 0x3fee0 +#define ixSMU_PM_STATUS_57 0x3fee4 +#define ixSMU_PM_STATUS_58 0x3fee8 +#define ixSMU_PM_STATUS_59 0x3feec +#define ixSMU_PM_STATUS_60 0x3fef0 +#define ixSMU_PM_STATUS_61 0x3fef4 +#define ixSMU_PM_STATUS_62 0x3fef8 +#define ixSMU_PM_STATUS_63 0x3fefc +#define ixSMU_PM_STATUS_64 0x3ff00 +#define ixSMU_PM_STATUS_65 0x3ff04 +#define ixSMU_PM_STATUS_66 0x3ff08 +#define ixSMU_PM_STATUS_67 0x3ff0c +#define ixSMU_PM_STATUS_68 0x3ff10 +#define ixSMU_PM_STATUS_69 0x3ff14 +#define ixSMU_PM_STATUS_70 0x3ff18 +#define ixSMU_PM_STATUS_71 0x3ff1c +#define ixSMU_PM_STATUS_72 0x3ff20 +#define ixSMU_PM_STATUS_73 0x3ff24 +#define ixSMU_PM_STATUS_74 0x3ff28 +#define ixSMU_PM_STATUS_75 0x3ff2c +#define ixSMU_PM_STATUS_76 0x3ff30 +#define ixSMU_PM_STATUS_77 0x3ff34 +#define ixSMU_PM_STATUS_78 0x3ff38 +#define ixSMU_PM_STATUS_79 0x3ff3c +#define ixSMU_PM_STATUS_80 0x3ff40 +#define ixSMU_PM_STATUS_81 0x3ff44 +#define ixSMU_PM_STATUS_82 0x3ff48 +#define ixSMU_PM_STATUS_83 0x3ff4c +#define ixSMU_PM_STATUS_84 0x3ff50 +#define ixSMU_PM_STATUS_85 0x3ff54 +#define ixSMU_PM_STATUS_86 0x3ff58 +#define ixSMU_PM_STATUS_87 0x3ff5c +#define ixSMU_PM_STATUS_88 0x3ff60 +#define ixSMU_PM_STATUS_89 0x3ff64 +#define ixSMU_PM_STATUS_90 0x3ff68 +#define ixSMU_PM_STATUS_91 0x3ff6c +#define ixSMU_PM_STATUS_92 0x3ff70 +#define ixSMU_PM_STATUS_93 0x3ff74 +#define ixSMU_PM_STATUS_94 0x3ff78 +#define ixSMU_PM_STATUS_95 0x3ff7c +#define ixSMU_PM_STATUS_96 0x3ff80 +#define ixSMU_PM_STATUS_97 0x3ff84 +#define ixSMU_PM_STATUS_98 0x3ff88 +#define ixSMU_PM_STATUS_99 0x3ff8c +#define ixSMU_PM_STATUS_100 0x3ff90 +#define ixSMU_PM_STATUS_101 0x3ff94 +#define ixSMU_PM_STATUS_102 0x3ff98 +#define ixSMU_PM_STATUS_103 0x3ff9c +#define ixSMU_PM_STATUS_104 0x3ffa0 +#define ixSMU_PM_STATUS_105 0x3ffa4 +#define ixSMU_PM_STATUS_106 0x3ffa8 +#define ixSMU_PM_STATUS_107 0x3ffac +#define ixSMU_PM_STATUS_108 0x3ffb0 +#define ixSMU_PM_STATUS_109 0x3ffb4 +#define ixSMU_PM_STATUS_110 0x3ffb8 +#define ixSMU_PM_STATUS_111 0x3ffbc +#define ixSMU_PM_STATUS_112 0x3ffc0 +#define ixSMU_PM_STATUS_113 0x3ffc4 +#define ixSMU_PM_STATUS_114 0x3ffc8 +#define ixSMU_PM_STATUS_115 0x3ffcc +#define ixSMU_PM_STATUS_116 0x3ffd0 +#define ixSMU_PM_STATUS_117 0x3ffd4 +#define ixSMU_PM_STATUS_118 0x3ffd8 +#define ixSMU_PM_STATUS_119 0x3ffdc +#define ixSMU_PM_STATUS_120 0x3ffe0 +#define ixSMU_PM_STATUS_121 0x3ffe4 +#define ixSMU_PM_STATUS_122 0x3ffe8 +#define ixSMU_PM_STATUS_123 0x3ffec +#define ixSMU_PM_STATUS_124 0x3fff0 +#define ixSMU_PM_STATUS_125 0x3fff4 +#define ixSMU_PM_STATUS_126 0x3fff8 +#define ixSMU_PM_STATUS_127 0x3fffc +#define ixCG_THERMAL_INT_ENA 0xc2100024 +#define ixCG_THERMAL_INT_CTRL 0xc2100028 +#define ixCG_THERMAL_INT_STATUS 0xc210002c +#define ixGENERAL_PWRMGT 0xc0200000 +#define ixCNB_PWRMGT_CNTL 0xc0200004 +#define ixSCLK_PWRMGT_CNTL 0xc0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 +#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 +#define ixPLL_TEST_CNTL 0xc020003c +#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 +#define ixCG_DISPLAY_GAP_CNTL 0xc0200060 +#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 +#define ixCG_ACPI_CNTL 0xc0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 +#define ixSMU_VOLTAGE_STATUS 0xc0200094 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 +#define ixCG_ULV_PARAMETER 0xc020015c +#define ixSCLK_MIN_DIV 0xc0200308 +#define ixLCAC_SX0_CNTL 0xc0400d00 +#define ixLCAC_SX0_OVR_SEL 0xc0400d04 +#define ixLCAC_SX0_OVR_VAL 0xc0400d08 +#define ixLCAC_MC0_CNTL 0xc0400d30 +#define ixLCAC_MC0_OVR_SEL 0xc0400d34 +#define ixLCAC_MC0_OVR_VAL 0xc0400d38 +#define ixLCAC_MC1_CNTL 0xc0400d3c +#define ixLCAC_MC1_OVR_SEL 0xc0400d40 +#define ixLCAC_MC1_OVR_VAL 0xc0400d44 +#define ixLCAC_MC2_CNTL 0xc0400d48 +#define ixLCAC_MC2_OVR_SEL 0xc0400d4c +#define ixLCAC_MC2_OVR_VAL 0xc0400d50 +#define ixLCAC_MC3_CNTL 0xc0400d54 +#define ixLCAC_MC3_OVR_SEL 0xc0400d58 +#define ixLCAC_MC3_OVR_VAL 0xc0400d5c +#define ixLCAC_CPL_CNTL 0xc0400d80 +#define ixLCAC_CPL_OVR_SEL 0xc0400d84 +#define ixLCAC_CPL_OVR_VAL 0xc0400d88 + +#endif /* SMU_7_0_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h new file mode 100644 index 000000000000..54e0e4c3f1bc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h @@ -0,0 +1,3842 @@ +/* + * SMU_7_0_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_0_0_SH_MASK_H +#define SMU_7_0_0_SH_MASK_H + +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f +#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 +#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f +#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 +#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f +#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 +#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f +#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON_MASK 0x2000 +#define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON__SHIFT 0xd +#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ_MASK 0x3c000 +#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ__SHIFT 0xe +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x1fc0000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x12 +#define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS_MASK 0xe000000 +#define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fc00 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0xa +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN_MASK 0x400 +#define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN__SHIFT 0xa +#define CG_SPLL_FUNC_CNTL_5__PLLBYPASS_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_5__PLLBYPASS__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d +#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 +#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 +#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 +#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 +#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 +#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 +#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff +#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 +#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 +#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 +#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 +#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa +#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 +#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_0__SMC_RESP_MASK 0xffff +#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_1__SMC_RESP_MASK 0xffff +#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_2__SMC_RESP_MASK 0xffff +#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_3__SMC_RESP_MASK 0xffff +#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_4__SMC_RESP_MASK 0xffff +#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_5__SMC_RESP_MASK 0xffff +#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_6__SMC_RESP_MASK 0xffff +#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_7__SMC_RESP_MASK 0xffff +#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_8__SMC_RESP_MASK 0xffff +#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_9__SMC_RESP_MASK 0xffff +#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_10__SMC_RESP_MASK 0xffff +#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_11__SMC_RESP_MASK 0xffff +#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 +#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 +#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 +#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 +#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 +#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffff +#define SMC_PC_C__smc_pc_c__SHIFT 0x0 +#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff +#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 +#define CG_FPS_CNT__FPS_CNT_MASK 0xff +#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 +#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 +#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 +#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 +#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 +#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 +#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa +#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 +#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 +#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 +#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 +#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 +#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 +#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 +#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 +#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 +#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 +#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 +#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 +#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 +#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 +#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 +#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 +#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 +#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 +#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 +#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 +#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 +#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 +#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 +#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa +#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000 +#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000 +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000 +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11 +#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000 +#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14 +#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000 +#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17 +#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000 +#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18 +#define CC_RCU_FUSES__RCU_SPARE_MASK 0x7e000000 +#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19 +#define CC_RCU_FUSES__PSP_ENABLE_MASK 0x80000000 +#define CC_RCU_FUSES__PSP_ENABLE__SHIFT 0x1f +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 +#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc +#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 +#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 +#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 +#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 +#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c +#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 +#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d +#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff +#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 +#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 +#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 +#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 +#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 +#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 +#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 +#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3fffe +#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 +#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a +#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 +#define SMU_STATUS__SMU_DONE_MASK 0x1 +#define SMU_STATUS__SMU_DONE__SHIFT 0x0 +#define SMU_STATUS__SMU_PASS_MASK 0x2 +#define SMU_STATUS__SMU_PASS__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 +#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 +#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 +#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 +#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 +#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 +#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 +#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 +#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 +#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff +#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 +#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 +#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f +#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff +#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 +#define DPM_TABLE_1__SystemFlags_MASK 0xffffffff +#define DPM_TABLE_1__SystemFlags__SHIFT 0x0 +#define DPM_TABLE_2__GraphicsPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_2__GraphicsPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_5__GraphicsPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_5__GraphicsPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_6__GraphicsPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_6__GraphicsPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_7__GraphicsPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_7__GraphicsPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_8__GraphicsPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_8__GraphicsPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_9__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_9__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_10__GraphicsPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_10__GraphicsPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_11__GioPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_11__GioPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_12__GioPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_12__GioPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_13__GioPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_13__GioPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_14__GioPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_14__GioPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_15__GioPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_15__GioPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_16__GioPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_16__GioPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_17__GioPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_17__GioPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_18__GioPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_18__GioPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_19__GioPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_19__GioPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_20__VceLevelCount_MASK 0xff +#define DPM_TABLE_20__VceLevelCount__SHIFT 0x0 +#define DPM_TABLE_20__UvdLevelCount_MASK 0xff00 +#define DPM_TABLE_20__UvdLevelCount__SHIFT 0x8 +#define DPM_TABLE_20__GIOLevelCount_MASK 0xff0000 +#define DPM_TABLE_20__GIOLevelCount__SHIFT 0x10 +#define DPM_TABLE_20__GraphicsDpmLevelCount_MASK 0xff000000 +#define DPM_TABLE_20__GraphicsDpmLevelCount__SHIFT 0x18 +#define DPM_TABLE_21__FpsHighThreshold_MASK 0xffff +#define DPM_TABLE_21__FpsHighThreshold__SHIFT 0x0 +#define DPM_TABLE_21__SamuLevelCount_MASK 0xff0000 +#define DPM_TABLE_21__SamuLevelCount__SHIFT 0x10 +#define DPM_TABLE_21__AcpLevelCount_MASK 0xff000000 +#define DPM_TABLE_21__AcpLevelCount__SHIFT 0x18 +#define DPM_TABLE_22__GraphicsLevel_0_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_22__GraphicsLevel_0_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_23__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_23__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_24__GraphicsLevel_0_ActivityLevel_MASK 0xffff +#define DPM_TABLE_24__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_24__GraphicsLevel_0_VidOffset_MASK 0xff0000 +#define DPM_TABLE_24__GraphicsLevel_0_VidOffset__SHIFT 0x10 +#define DPM_TABLE_24__GraphicsLevel_0_Vid_MASK 0xff000000 +#define DPM_TABLE_24__GraphicsLevel_0_Vid__SHIFT 0x18 +#define DPM_TABLE_25__GraphicsLevel_0_SclkDid_MASK 0xff +#define DPM_TABLE_25__GraphicsLevel_0_SclkDid__SHIFT 0x0 +#define DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_25__GraphicsLevel_0_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_25__GraphicsLevel_0_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_25__GraphicsLevel_0_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_25__GraphicsLevel_0_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_26__GraphicsLevel_0_UpHyst_MASK 0xff +#define DPM_TABLE_26__GraphicsLevel_0_UpHyst__SHIFT 0x0 +#define DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_27__GraphicsLevel_0_DownHyst_MASK 0xff000000 +#define DPM_TABLE_27__GraphicsLevel_0_DownHyst__SHIFT 0x18 +#define DPM_TABLE_28__GraphicsLevel_0_reserved_MASK 0xffffffff +#define DPM_TABLE_28__GraphicsLevel_0_reserved__SHIFT 0x0 +#define DPM_TABLE_29__GraphicsLevel_1_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_29__GraphicsLevel_1_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_30__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_30__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_31__GraphicsLevel_1_ActivityLevel_MASK 0xffff +#define DPM_TABLE_31__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_31__GraphicsLevel_1_VidOffset_MASK 0xff0000 +#define DPM_TABLE_31__GraphicsLevel_1_VidOffset__SHIFT 0x10 +#define DPM_TABLE_31__GraphicsLevel_1_Vid_MASK 0xff000000 +#define DPM_TABLE_31__GraphicsLevel_1_Vid__SHIFT 0x18 +#define DPM_TABLE_32__GraphicsLevel_1_SclkDid_MASK 0xff +#define DPM_TABLE_32__GraphicsLevel_1_SclkDid__SHIFT 0x0 +#define DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_32__GraphicsLevel_1_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_32__GraphicsLevel_1_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_32__GraphicsLevel_1_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_32__GraphicsLevel_1_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_33__GraphicsLevel_1_UpHyst_MASK 0xff +#define DPM_TABLE_33__GraphicsLevel_1_UpHyst__SHIFT 0x0 +#define DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_34__GraphicsLevel_1_DownHyst_MASK 0xff000000 +#define DPM_TABLE_34__GraphicsLevel_1_DownHyst__SHIFT 0x18 +#define DPM_TABLE_35__GraphicsLevel_1_reserved_MASK 0xffffffff +#define DPM_TABLE_35__GraphicsLevel_1_reserved__SHIFT 0x0 +#define DPM_TABLE_36__GraphicsLevel_2_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_36__GraphicsLevel_2_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_37__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_37__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_38__GraphicsLevel_2_ActivityLevel_MASK 0xffff +#define DPM_TABLE_38__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_38__GraphicsLevel_2_VidOffset_MASK 0xff0000 +#define DPM_TABLE_38__GraphicsLevel_2_VidOffset__SHIFT 0x10 +#define DPM_TABLE_38__GraphicsLevel_2_Vid_MASK 0xff000000 +#define DPM_TABLE_38__GraphicsLevel_2_Vid__SHIFT 0x18 +#define DPM_TABLE_39__GraphicsLevel_2_SclkDid_MASK 0xff +#define DPM_TABLE_39__GraphicsLevel_2_SclkDid__SHIFT 0x0 +#define DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_39__GraphicsLevel_2_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_39__GraphicsLevel_2_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_39__GraphicsLevel_2_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_39__GraphicsLevel_2_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_40__GraphicsLevel_2_UpHyst_MASK 0xff +#define DPM_TABLE_40__GraphicsLevel_2_UpHyst__SHIFT 0x0 +#define DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_41__GraphicsLevel_2_DownHyst_MASK 0xff000000 +#define DPM_TABLE_41__GraphicsLevel_2_DownHyst__SHIFT 0x18 +#define DPM_TABLE_42__GraphicsLevel_2_reserved_MASK 0xffffffff +#define DPM_TABLE_42__GraphicsLevel_2_reserved__SHIFT 0x0 +#define DPM_TABLE_43__GraphicsLevel_3_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_43__GraphicsLevel_3_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_44__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_44__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_45__GraphicsLevel_3_ActivityLevel_MASK 0xffff +#define DPM_TABLE_45__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_45__GraphicsLevel_3_VidOffset_MASK 0xff0000 +#define DPM_TABLE_45__GraphicsLevel_3_VidOffset__SHIFT 0x10 +#define DPM_TABLE_45__GraphicsLevel_3_Vid_MASK 0xff000000 +#define DPM_TABLE_45__GraphicsLevel_3_Vid__SHIFT 0x18 +#define DPM_TABLE_46__GraphicsLevel_3_SclkDid_MASK 0xff +#define DPM_TABLE_46__GraphicsLevel_3_SclkDid__SHIFT 0x0 +#define DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_46__GraphicsLevel_3_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_46__GraphicsLevel_3_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_46__GraphicsLevel_3_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_46__GraphicsLevel_3_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_47__GraphicsLevel_3_UpHyst_MASK 0xff +#define DPM_TABLE_47__GraphicsLevel_3_UpHyst__SHIFT 0x0 +#define DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_48__GraphicsLevel_3_DownHyst_MASK 0xff000000 +#define DPM_TABLE_48__GraphicsLevel_3_DownHyst__SHIFT 0x18 +#define DPM_TABLE_49__GraphicsLevel_3_reserved_MASK 0xffffffff +#define DPM_TABLE_49__GraphicsLevel_3_reserved__SHIFT 0x0 +#define DPM_TABLE_50__GraphicsLevel_4_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_50__GraphicsLevel_4_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_51__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_51__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_52__GraphicsLevel_4_ActivityLevel_MASK 0xffff +#define DPM_TABLE_52__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_52__GraphicsLevel_4_VidOffset_MASK 0xff0000 +#define DPM_TABLE_52__GraphicsLevel_4_VidOffset__SHIFT 0x10 +#define DPM_TABLE_52__GraphicsLevel_4_Vid_MASK 0xff000000 +#define DPM_TABLE_52__GraphicsLevel_4_Vid__SHIFT 0x18 +#define DPM_TABLE_53__GraphicsLevel_4_SclkDid_MASK 0xff +#define DPM_TABLE_53__GraphicsLevel_4_SclkDid__SHIFT 0x0 +#define DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_53__GraphicsLevel_4_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_53__GraphicsLevel_4_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_53__GraphicsLevel_4_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_53__GraphicsLevel_4_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_54__GraphicsLevel_4_UpHyst_MASK 0xff +#define DPM_TABLE_54__GraphicsLevel_4_UpHyst__SHIFT 0x0 +#define DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_55__GraphicsLevel_4_DownHyst_MASK 0xff000000 +#define DPM_TABLE_55__GraphicsLevel_4_DownHyst__SHIFT 0x18 +#define DPM_TABLE_56__GraphicsLevel_4_reserved_MASK 0xffffffff +#define DPM_TABLE_56__GraphicsLevel_4_reserved__SHIFT 0x0 +#define DPM_TABLE_57__GraphicsLevel_5_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_57__GraphicsLevel_5_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_58__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_58__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_59__GraphicsLevel_5_ActivityLevel_MASK 0xffff +#define DPM_TABLE_59__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_59__GraphicsLevel_5_VidOffset_MASK 0xff0000 +#define DPM_TABLE_59__GraphicsLevel_5_VidOffset__SHIFT 0x10 +#define DPM_TABLE_59__GraphicsLevel_5_Vid_MASK 0xff000000 +#define DPM_TABLE_59__GraphicsLevel_5_Vid__SHIFT 0x18 +#define DPM_TABLE_60__GraphicsLevel_5_SclkDid_MASK 0xff +#define DPM_TABLE_60__GraphicsLevel_5_SclkDid__SHIFT 0x0 +#define DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_60__GraphicsLevel_5_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_60__GraphicsLevel_5_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_60__GraphicsLevel_5_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_60__GraphicsLevel_5_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_61__GraphicsLevel_5_UpHyst_MASK 0xff +#define DPM_TABLE_61__GraphicsLevel_5_UpHyst__SHIFT 0x0 +#define DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_62__GraphicsLevel_5_DownHyst_MASK 0xff000000 +#define DPM_TABLE_62__GraphicsLevel_5_DownHyst__SHIFT 0x18 +#define DPM_TABLE_63__GraphicsLevel_5_reserved_MASK 0xffffffff +#define DPM_TABLE_63__GraphicsLevel_5_reserved__SHIFT 0x0 +#define DPM_TABLE_64__GraphicsLevel_6_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_64__GraphicsLevel_6_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_65__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_65__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_66__GraphicsLevel_6_ActivityLevel_MASK 0xffff +#define DPM_TABLE_66__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_66__GraphicsLevel_6_VidOffset_MASK 0xff0000 +#define DPM_TABLE_66__GraphicsLevel_6_VidOffset__SHIFT 0x10 +#define DPM_TABLE_66__GraphicsLevel_6_Vid_MASK 0xff000000 +#define DPM_TABLE_66__GraphicsLevel_6_Vid__SHIFT 0x18 +#define DPM_TABLE_67__GraphicsLevel_6_SclkDid_MASK 0xff +#define DPM_TABLE_67__GraphicsLevel_6_SclkDid__SHIFT 0x0 +#define DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_67__GraphicsLevel_6_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_67__GraphicsLevel_6_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_67__GraphicsLevel_6_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_67__GraphicsLevel_6_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_68__GraphicsLevel_6_UpHyst_MASK 0xff +#define DPM_TABLE_68__GraphicsLevel_6_UpHyst__SHIFT 0x0 +#define DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_69__GraphicsLevel_6_DownHyst_MASK 0xff000000 +#define DPM_TABLE_69__GraphicsLevel_6_DownHyst__SHIFT 0x18 +#define DPM_TABLE_70__GraphicsLevel_6_reserved_MASK 0xffffffff +#define DPM_TABLE_70__GraphicsLevel_6_reserved__SHIFT 0x0 +#define DPM_TABLE_71__GraphicsLevel_7_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_71__GraphicsLevel_7_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_72__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_72__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_73__GraphicsLevel_7_ActivityLevel_MASK 0xffff +#define DPM_TABLE_73__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_73__GraphicsLevel_7_VidOffset_MASK 0xff0000 +#define DPM_TABLE_73__GraphicsLevel_7_VidOffset__SHIFT 0x10 +#define DPM_TABLE_73__GraphicsLevel_7_Vid_MASK 0xff000000 +#define DPM_TABLE_73__GraphicsLevel_7_Vid__SHIFT 0x18 +#define DPM_TABLE_74__GraphicsLevel_7_SclkDid_MASK 0xff +#define DPM_TABLE_74__GraphicsLevel_7_SclkDid__SHIFT 0x0 +#define DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_74__GraphicsLevel_7_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_74__GraphicsLevel_7_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_74__GraphicsLevel_7_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_74__GraphicsLevel_7_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_75__GraphicsLevel_7_UpHyst_MASK 0xff +#define DPM_TABLE_75__GraphicsLevel_7_UpHyst__SHIFT 0x0 +#define DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_76__GraphicsLevel_7_DownHyst_MASK 0xff000000 +#define DPM_TABLE_76__GraphicsLevel_7_DownHyst__SHIFT 0x18 +#define DPM_TABLE_77__GraphicsLevel_7_reserved_MASK 0xffffffff +#define DPM_TABLE_77__GraphicsLevel_7_reserved__SHIFT 0x0 +#define DPM_TABLE_78__ACPILevel_Flags_MASK 0xffffffff +#define DPM_TABLE_78__ACPILevel_Flags__SHIFT 0x0 +#define DPM_TABLE_79__ACPILevel_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_79__ACPILevel_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_80__ACPILevel_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_80__ACPILevel_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_81__ACPILevel_DisplayWatermark_MASK 0xff +#define DPM_TABLE_81__ACPILevel_DisplayWatermark__SHIFT 0x0 +#define DPM_TABLE_81__ACPILevel_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_81__ACPILevel_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_81__ACPILevel_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_81__ACPILevel_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_81__ACPILevel_SclkDid_MASK 0xff000000 +#define DPM_TABLE_81__ACPILevel_SclkDid__SHIFT 0x18 +#define DPM_TABLE_82__ACPILevel_padding_2_MASK 0xff +#define DPM_TABLE_82__ACPILevel_padding_2__SHIFT 0x0 +#define DPM_TABLE_82__ACPILevel_padding_1_MASK 0xff00 +#define DPM_TABLE_82__ACPILevel_padding_1__SHIFT 0x8 +#define DPM_TABLE_82__ACPILevel_padding_0_MASK 0xff0000 +#define DPM_TABLE_82__ACPILevel_padding_0__SHIFT 0x10 +#define DPM_TABLE_82__ACPILevel_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_82__ACPILevel_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_83__UvdLevel_0_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_83__UvdLevel_0_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_84__UvdLevel_0_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_84__UvdLevel_0_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_85__UvdLevel_0_DclkDivider_MASK 0xff +#define DPM_TABLE_85__UvdLevel_0_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_85__UvdLevel_0_VclkDivider_MASK 0xff00 +#define DPM_TABLE_85__UvdLevel_0_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_85__UvdLevel_0_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_85__UvdLevel_0_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_86__UvdLevel_0_padding_1_MASK 0xff +#define DPM_TABLE_86__UvdLevel_0_padding_1__SHIFT 0x0 +#define DPM_TABLE_86__UvdLevel_0_padding_0_MASK 0xff00 +#define DPM_TABLE_86__UvdLevel_0_padding_0__SHIFT 0x8 +#define DPM_TABLE_86__UvdLevel_0_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_86__UvdLevel_0_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_86__UvdLevel_0_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_86__UvdLevel_0_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_87__UvdLevel_1_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_87__UvdLevel_1_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_88__UvdLevel_1_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_88__UvdLevel_1_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_89__UvdLevel_1_DclkDivider_MASK 0xff +#define DPM_TABLE_89__UvdLevel_1_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_89__UvdLevel_1_VclkDivider_MASK 0xff00 +#define DPM_TABLE_89__UvdLevel_1_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_89__UvdLevel_1_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_89__UvdLevel_1_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_90__UvdLevel_1_padding_1_MASK 0xff +#define DPM_TABLE_90__UvdLevel_1_padding_1__SHIFT 0x0 +#define DPM_TABLE_90__UvdLevel_1_padding_0_MASK 0xff00 +#define DPM_TABLE_90__UvdLevel_1_padding_0__SHIFT 0x8 +#define DPM_TABLE_90__UvdLevel_1_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_90__UvdLevel_1_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_90__UvdLevel_1_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_90__UvdLevel_1_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_91__UvdLevel_2_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_91__UvdLevel_2_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_92__UvdLevel_2_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_92__UvdLevel_2_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_93__UvdLevel_2_DclkDivider_MASK 0xff +#define DPM_TABLE_93__UvdLevel_2_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_93__UvdLevel_2_VclkDivider_MASK 0xff00 +#define DPM_TABLE_93__UvdLevel_2_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_93__UvdLevel_2_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_93__UvdLevel_2_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_94__UvdLevel_2_padding_1_MASK 0xff +#define DPM_TABLE_94__UvdLevel_2_padding_1__SHIFT 0x0 +#define DPM_TABLE_94__UvdLevel_2_padding_0_MASK 0xff00 +#define DPM_TABLE_94__UvdLevel_2_padding_0__SHIFT 0x8 +#define DPM_TABLE_94__UvdLevel_2_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_94__UvdLevel_2_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_94__UvdLevel_2_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_94__UvdLevel_2_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_95__UvdLevel_3_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_95__UvdLevel_3_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_96__UvdLevel_3_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_96__UvdLevel_3_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_97__UvdLevel_3_DclkDivider_MASK 0xff +#define DPM_TABLE_97__UvdLevel_3_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_97__UvdLevel_3_VclkDivider_MASK 0xff00 +#define DPM_TABLE_97__UvdLevel_3_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_97__UvdLevel_3_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_97__UvdLevel_3_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_98__UvdLevel_3_padding_1_MASK 0xff +#define DPM_TABLE_98__UvdLevel_3_padding_1__SHIFT 0x0 +#define DPM_TABLE_98__UvdLevel_3_padding_0_MASK 0xff00 +#define DPM_TABLE_98__UvdLevel_3_padding_0__SHIFT 0x8 +#define DPM_TABLE_98__UvdLevel_3_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_98__UvdLevel_3_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_98__UvdLevel_3_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_98__UvdLevel_3_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_99__UvdLevel_4_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_99__UvdLevel_4_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_100__UvdLevel_4_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_100__UvdLevel_4_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_101__UvdLevel_4_DclkDivider_MASK 0xff +#define DPM_TABLE_101__UvdLevel_4_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_101__UvdLevel_4_VclkDivider_MASK 0xff00 +#define DPM_TABLE_101__UvdLevel_4_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_101__UvdLevel_4_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_101__UvdLevel_4_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_102__UvdLevel_4_padding_1_MASK 0xff +#define DPM_TABLE_102__UvdLevel_4_padding_1__SHIFT 0x0 +#define DPM_TABLE_102__UvdLevel_4_padding_0_MASK 0xff00 +#define DPM_TABLE_102__UvdLevel_4_padding_0__SHIFT 0x8 +#define DPM_TABLE_102__UvdLevel_4_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_102__UvdLevel_4_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_102__UvdLevel_4_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_102__UvdLevel_4_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_103__UvdLevel_5_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_103__UvdLevel_5_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_104__UvdLevel_5_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_104__UvdLevel_5_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_105__UvdLevel_5_DclkDivider_MASK 0xff +#define DPM_TABLE_105__UvdLevel_5_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_105__UvdLevel_5_VclkDivider_MASK 0xff00 +#define DPM_TABLE_105__UvdLevel_5_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_105__UvdLevel_5_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_105__UvdLevel_5_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_106__UvdLevel_5_padding_1_MASK 0xff +#define DPM_TABLE_106__UvdLevel_5_padding_1__SHIFT 0x0 +#define DPM_TABLE_106__UvdLevel_5_padding_0_MASK 0xff00 +#define DPM_TABLE_106__UvdLevel_5_padding_0__SHIFT 0x8 +#define DPM_TABLE_106__UvdLevel_5_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_106__UvdLevel_5_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_106__UvdLevel_5_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_106__UvdLevel_5_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_107__UvdLevel_6_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_107__UvdLevel_6_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_108__UvdLevel_6_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_108__UvdLevel_6_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_109__UvdLevel_6_DclkDivider_MASK 0xff +#define DPM_TABLE_109__UvdLevel_6_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_109__UvdLevel_6_VclkDivider_MASK 0xff00 +#define DPM_TABLE_109__UvdLevel_6_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_109__UvdLevel_6_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_109__UvdLevel_6_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_110__UvdLevel_6_padding_1_MASK 0xff +#define DPM_TABLE_110__UvdLevel_6_padding_1__SHIFT 0x0 +#define DPM_TABLE_110__UvdLevel_6_padding_0_MASK 0xff00 +#define DPM_TABLE_110__UvdLevel_6_padding_0__SHIFT 0x8 +#define DPM_TABLE_110__UvdLevel_6_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_110__UvdLevel_6_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_110__UvdLevel_6_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_110__UvdLevel_6_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_111__UvdLevel_7_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_111__UvdLevel_7_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_112__UvdLevel_7_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_112__UvdLevel_7_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_113__UvdLevel_7_DclkDivider_MASK 0xff +#define DPM_TABLE_113__UvdLevel_7_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_113__UvdLevel_7_VclkDivider_MASK 0xff00 +#define DPM_TABLE_113__UvdLevel_7_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_113__UvdLevel_7_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_113__UvdLevel_7_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_114__UvdLevel_7_padding_1_MASK 0xff +#define DPM_TABLE_114__UvdLevel_7_padding_1__SHIFT 0x0 +#define DPM_TABLE_114__UvdLevel_7_padding_0_MASK 0xff00 +#define DPM_TABLE_114__UvdLevel_7_padding_0__SHIFT 0x8 +#define DPM_TABLE_114__UvdLevel_7_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_114__UvdLevel_7_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_114__UvdLevel_7_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_114__UvdLevel_7_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_115__VceLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_115__VceLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_116__VceLevel_0_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_116__VceLevel_0_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_116__VceLevel_0_Divider_MASK 0xff00 +#define DPM_TABLE_116__VceLevel_0_Divider__SHIFT 0x8 +#define DPM_TABLE_116__VceLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_116__VceLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_117__VceLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_117__VceLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_118__VceLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_118__VceLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_119__VceLevel_1_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_119__VceLevel_1_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_119__VceLevel_1_Divider_MASK 0xff00 +#define DPM_TABLE_119__VceLevel_1_Divider__SHIFT 0x8 +#define DPM_TABLE_119__VceLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_119__VceLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_120__VceLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_120__VceLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_121__VceLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_121__VceLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_122__VceLevel_2_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_122__VceLevel_2_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_122__VceLevel_2_Divider_MASK 0xff00 +#define DPM_TABLE_122__VceLevel_2_Divider__SHIFT 0x8 +#define DPM_TABLE_122__VceLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_122__VceLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_123__VceLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_123__VceLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_124__VceLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_124__VceLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_125__VceLevel_3_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_125__VceLevel_3_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_125__VceLevel_3_Divider_MASK 0xff00 +#define DPM_TABLE_125__VceLevel_3_Divider__SHIFT 0x8 +#define DPM_TABLE_125__VceLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_125__VceLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_126__VceLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_126__VceLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_127__VceLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_127__VceLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_128__VceLevel_4_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_128__VceLevel_4_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_128__VceLevel_4_Divider_MASK 0xff00 +#define DPM_TABLE_128__VceLevel_4_Divider__SHIFT 0x8 +#define DPM_TABLE_128__VceLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_128__VceLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_129__VceLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_129__VceLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_130__VceLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_130__VceLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_131__VceLevel_5_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_131__VceLevel_5_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_131__VceLevel_5_Divider_MASK 0xff00 +#define DPM_TABLE_131__VceLevel_5_Divider__SHIFT 0x8 +#define DPM_TABLE_131__VceLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_131__VceLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_132__VceLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_132__VceLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_133__VceLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_133__VceLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_134__VceLevel_6_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_134__VceLevel_6_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_134__VceLevel_6_Divider_MASK 0xff00 +#define DPM_TABLE_134__VceLevel_6_Divider__SHIFT 0x8 +#define DPM_TABLE_134__VceLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_134__VceLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_135__VceLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_135__VceLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_136__VceLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_136__VceLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_137__VceLevel_7_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_137__VceLevel_7_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_137__VceLevel_7_Divider_MASK 0xff00 +#define DPM_TABLE_137__VceLevel_7_Divider__SHIFT 0x8 +#define DPM_TABLE_137__VceLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_137__VceLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_138__VceLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_138__VceLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_139__AcpLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_139__AcpLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_140__AcpLevel_0_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_140__AcpLevel_0_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_140__AcpLevel_0_Divider_MASK 0xff00 +#define DPM_TABLE_140__AcpLevel_0_Divider__SHIFT 0x8 +#define DPM_TABLE_140__AcpLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_140__AcpLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_141__AcpLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_141__AcpLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_142__AcpLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_142__AcpLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_143__AcpLevel_1_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_143__AcpLevel_1_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_143__AcpLevel_1_Divider_MASK 0xff00 +#define DPM_TABLE_143__AcpLevel_1_Divider__SHIFT 0x8 +#define DPM_TABLE_143__AcpLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_143__AcpLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_144__AcpLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_144__AcpLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_145__AcpLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_145__AcpLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_146__AcpLevel_2_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_146__AcpLevel_2_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_146__AcpLevel_2_Divider_MASK 0xff00 +#define DPM_TABLE_146__AcpLevel_2_Divider__SHIFT 0x8 +#define DPM_TABLE_146__AcpLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_146__AcpLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_147__AcpLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_147__AcpLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_148__AcpLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_148__AcpLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_149__AcpLevel_3_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_149__AcpLevel_3_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_149__AcpLevel_3_Divider_MASK 0xff00 +#define DPM_TABLE_149__AcpLevel_3_Divider__SHIFT 0x8 +#define DPM_TABLE_149__AcpLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_149__AcpLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_150__AcpLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_150__AcpLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_151__AcpLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_151__AcpLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_152__AcpLevel_4_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_152__AcpLevel_4_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_152__AcpLevel_4_Divider_MASK 0xff00 +#define DPM_TABLE_152__AcpLevel_4_Divider__SHIFT 0x8 +#define DPM_TABLE_152__AcpLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_152__AcpLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_153__AcpLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_153__AcpLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_154__AcpLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_154__AcpLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_155__AcpLevel_5_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_155__AcpLevel_5_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_155__AcpLevel_5_Divider_MASK 0xff00 +#define DPM_TABLE_155__AcpLevel_5_Divider__SHIFT 0x8 +#define DPM_TABLE_155__AcpLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_155__AcpLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_156__AcpLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_156__AcpLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_157__AcpLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_157__AcpLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_158__AcpLevel_6_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_158__AcpLevel_6_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_158__AcpLevel_6_Divider_MASK 0xff00 +#define DPM_TABLE_158__AcpLevel_6_Divider__SHIFT 0x8 +#define DPM_TABLE_158__AcpLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_158__AcpLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_159__AcpLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_159__AcpLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_160__AcpLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_160__AcpLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_161__AcpLevel_7_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_161__AcpLevel_7_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_161__AcpLevel_7_Divider_MASK 0xff00 +#define DPM_TABLE_161__AcpLevel_7_Divider__SHIFT 0x8 +#define DPM_TABLE_161__AcpLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_161__AcpLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_162__AcpLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_162__AcpLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_163__SamuLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_163__SamuLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_164__SamuLevel_0_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_164__SamuLevel_0_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_164__SamuLevel_0_Divider_MASK 0xff00 +#define DPM_TABLE_164__SamuLevel_0_Divider__SHIFT 0x8 +#define DPM_TABLE_164__SamuLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_164__SamuLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_165__SamuLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_165__SamuLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_166__SamuLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_166__SamuLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_167__SamuLevel_1_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_167__SamuLevel_1_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_167__SamuLevel_1_Divider_MASK 0xff00 +#define DPM_TABLE_167__SamuLevel_1_Divider__SHIFT 0x8 +#define DPM_TABLE_167__SamuLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_167__SamuLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_168__SamuLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_168__SamuLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_169__SamuLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_169__SamuLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_170__SamuLevel_2_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_170__SamuLevel_2_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_170__SamuLevel_2_Divider_MASK 0xff00 +#define DPM_TABLE_170__SamuLevel_2_Divider__SHIFT 0x8 +#define DPM_TABLE_170__SamuLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_170__SamuLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_171__SamuLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_171__SamuLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_172__SamuLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_172__SamuLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_173__SamuLevel_3_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_173__SamuLevel_3_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_173__SamuLevel_3_Divider_MASK 0xff00 +#define DPM_TABLE_173__SamuLevel_3_Divider__SHIFT 0x8 +#define DPM_TABLE_173__SamuLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_173__SamuLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_174__SamuLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_174__SamuLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_175__SamuLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_175__SamuLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_176__SamuLevel_4_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_176__SamuLevel_4_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_176__SamuLevel_4_Divider_MASK 0xff00 +#define DPM_TABLE_176__SamuLevel_4_Divider__SHIFT 0x8 +#define DPM_TABLE_176__SamuLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_176__SamuLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_177__SamuLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_177__SamuLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_178__SamuLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_178__SamuLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_179__SamuLevel_5_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_179__SamuLevel_5_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_179__SamuLevel_5_Divider_MASK 0xff00 +#define DPM_TABLE_179__SamuLevel_5_Divider__SHIFT 0x8 +#define DPM_TABLE_179__SamuLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_179__SamuLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_180__SamuLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_180__SamuLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_181__SamuLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_181__SamuLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_182__SamuLevel_6_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_182__SamuLevel_6_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_182__SamuLevel_6_Divider_MASK 0xff00 +#define DPM_TABLE_182__SamuLevel_6_Divider__SHIFT 0x8 +#define DPM_TABLE_182__SamuLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_182__SamuLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_183__SamuLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_183__SamuLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_184__SamuLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_184__SamuLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_185__SamuLevel_7_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_185__SamuLevel_7_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_185__SamuLevel_7_Divider_MASK 0xff00 +#define DPM_TABLE_185__SamuLevel_7_Divider__SHIFT 0x8 +#define DPM_TABLE_185__SamuLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_185__SamuLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_186__SamuLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_186__SamuLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_187__SamuBootLevel_MASK 0xff +#define DPM_TABLE_187__SamuBootLevel__SHIFT 0x0 +#define DPM_TABLE_187__AcpBootLevel_MASK 0xff00 +#define DPM_TABLE_187__AcpBootLevel__SHIFT 0x8 +#define DPM_TABLE_187__VceBootLevel_MASK 0xff0000 +#define DPM_TABLE_187__VceBootLevel__SHIFT 0x10 +#define DPM_TABLE_187__UvdBootLevel_MASK 0xff000000 +#define DPM_TABLE_187__UvdBootLevel__SHIFT 0x18 +#define DPM_TABLE_188__SAMUInterval_MASK 0xff +#define DPM_TABLE_188__SAMUInterval__SHIFT 0x0 +#define DPM_TABLE_188__ACPInterval_MASK 0xff00 +#define DPM_TABLE_188__ACPInterval__SHIFT 0x8 +#define DPM_TABLE_188__VCEInterval_MASK 0xff0000 +#define DPM_TABLE_188__VCEInterval__SHIFT 0x10 +#define DPM_TABLE_188__UVDInterval_MASK 0xff000000 +#define DPM_TABLE_188__UVDInterval__SHIFT 0x18 +#define DPM_TABLE_189__GraphicsVoltageChangeEnable_MASK 0xff +#define DPM_TABLE_189__GraphicsVoltageChangeEnable__SHIFT 0x0 +#define DPM_TABLE_189__GraphicsThermThrottleEnable_MASK 0xff00 +#define DPM_TABLE_189__GraphicsThermThrottleEnable__SHIFT 0x8 +#define DPM_TABLE_189__GraphicsInterval_MASK 0xff0000 +#define DPM_TABLE_189__GraphicsInterval__SHIFT 0x10 +#define DPM_TABLE_189__GraphicsBootLevel_MASK 0xff000000 +#define DPM_TABLE_189__GraphicsBootLevel__SHIFT 0x18 +#define DPM_TABLE_190__FpsLowThreshold_MASK 0xffff +#define DPM_TABLE_190__FpsLowThreshold__SHIFT 0x0 +#define DPM_TABLE_190__GraphicsClkSlowDivider_MASK 0xff0000 +#define DPM_TABLE_190__GraphicsClkSlowDivider__SHIFT 0x10 +#define DPM_TABLE_190__GraphicsClkSlowEnable_MASK 0xff000000 +#define DPM_TABLE_190__GraphicsClkSlowEnable__SHIFT 0x18 +#define DPM_TABLE_191__DisplayCac_MASK 0xffffffff +#define DPM_TABLE_191__DisplayCac__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_4__HandshakeDisables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_4__HandshakeDisables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy4Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_5__DisplayPhy4Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy3Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy3Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy2Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy2Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy1Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy1Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy8Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_6__DisplayPhy8Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy7Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy7Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy6Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy6Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy5Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy5Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_7__AverageGraphicsActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_7__AverageGraphicsActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_8__AverageMemoryActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_8__AverageMemoryActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_9__AverageGioActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_9__AverageGioActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__PCIeDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_10__PCIeDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__LClkDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_10__LClkDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_10__MClkDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_10__MClkDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_10__SClkDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_10__SClkDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_11__VCEDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_11__VCEDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_11__ACPDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_11__ACPDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_11__SAMUDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_11__SAMUDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_11__UVDDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_11__UVDDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_12__Reserved_0_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_12__Reserved_0__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_13__Reserved_1_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_13__Reserved_1__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__Reserved_2_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_14__Reserved_2__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_15__Reserved_3_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_15__Reserved_3__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_16__Reserved_4_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_16__Reserved_4__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_17__Reserved_5_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_17__Reserved_5__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_18__Reserved_6_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_18__Reserved_6__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__Reserved_7_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_19__Reserved_7__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_20__Reserved_8_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_20__Reserved_8__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_21__Reserved_9_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_21__Reserved_9__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_0_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_1_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_2_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_3_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_4_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_5_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_6_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_7_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_0_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_0_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_1_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_1_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_2_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_2_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_3_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_3_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_4_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_4_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_5_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_5_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_6_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_6_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_7_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_7_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_0_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_0_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_1_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_1_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_2_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_2_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_3_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_3_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_4_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_4_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_5_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_5_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_6_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_6_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_7_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_7_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_0_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_0_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_1_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_1_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_2_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_2_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_3_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_3_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_4_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_4_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_5_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_5_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_6_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_6_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_7_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_7_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define GIO_PID_CONTROLLER_CNTL_0__K_I_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_0__K_I__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_6__MAX_STATE_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_6__MAX_STATE__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT__SHIFT 0x0 +#define SMU_LCLK_DPM_LEVEL_COUNT__LCLK_DPM_LEVEL_COUNT_MASK 0xffffffff +#define SMU_LCLK_DPM_LEVEL_COUNT__LCLK_DPM_LEVEL_COUNT__SHIFT 0x0 +#define SMU_LCLK_DPM_CNTL__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_CNTL__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_CNTL__LCLK_DPM_BOOT_STATE_MASK 0xff00 +#define SMU_LCLK_DPM_CNTL__LCLK_DPM_BOOT_STATE__SHIFT 0x8 +#define SMU_LCLK_DPM_CNTL__VOLTAGE_CHG_EN_MASK 0xff0000 +#define SMU_LCLK_DPM_CNTL__VOLTAGE_CHG_EN__SHIFT 0x10 +#define SMU_LCLK_DPM_CNTL__LCLK_DPM_EN_MASK 0xff000000 +#define SMU_LCLK_DPM_CNTL__LCLK_DPM_EN__SHIFT 0x18 +#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__CURRENT_STATE_MASK 0xff +#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__CURRENT_STATE__SHIFT 0x0 +#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__TARGET_STATE_MASK 0xff00 +#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__TARGET_STATE__SHIFT 0x8 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_THERMAL_THROTTLING_EN_MASK 0xff +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_THERMAL_THROTTLING_EN__SHIFT 0x0 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TEMPERATURE_SEL_MASK 0xff00 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TEMPERATURE_SEL__SHIFT 0x8 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_TT_MODE_MASK 0xff0000 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_TT_MODE__SHIFT 0x10 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TT_HTC_ACTIVE_MASK 0xff000000 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TT_HTC_ACTIVE__SHIFT 0x18 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__LOW_THRESHOLD_MASK 0xffff +#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__LOW_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__HIGH_THRESHOLD_MASK 0xffff0000 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__HIGH_THRESHOLD__SHIFT 0x10 +#define PM_FUSES_1__BapmPstateVid_3_MASK 0xff +#define PM_FUSES_1__BapmPstateVid_3__SHIFT 0x0 +#define PM_FUSES_1__BapmPstateVid_2_MASK 0xff00 +#define PM_FUSES_1__BapmPstateVid_2__SHIFT 0x8 +#define PM_FUSES_1__BapmPstateVid_1_MASK 0xff0000 +#define PM_FUSES_1__BapmPstateVid_1__SHIFT 0x10 +#define PM_FUSES_1__BapmPstateVid_0_MASK 0xff000000 +#define PM_FUSES_1__BapmPstateVid_0__SHIFT 0x18 +#define PM_FUSES_2__BapmPstateVid_7_MASK 0xff +#define PM_FUSES_2__BapmPstateVid_7__SHIFT 0x0 +#define PM_FUSES_2__BapmPstateVid_6_MASK 0xff00 +#define PM_FUSES_2__BapmPstateVid_6__SHIFT 0x8 +#define PM_FUSES_2__BapmPstateVid_5_MASK 0xff0000 +#define PM_FUSES_2__BapmPstateVid_5__SHIFT 0x10 +#define PM_FUSES_2__BapmPstateVid_4_MASK 0xff000000 +#define PM_FUSES_2__BapmPstateVid_4__SHIFT 0x18 +#define PM_FUSES_3__BapmVddNbVidHiSidd_3_MASK 0xff +#define PM_FUSES_3__BapmVddNbVidHiSidd_3__SHIFT 0x0 +#define PM_FUSES_3__BapmVddNbVidHiSidd_2_MASK 0xff00 +#define PM_FUSES_3__BapmVddNbVidHiSidd_2__SHIFT 0x8 +#define PM_FUSES_3__BapmVddNbVidHiSidd_1_MASK 0xff0000 +#define PM_FUSES_3__BapmVddNbVidHiSidd_1__SHIFT 0x10 +#define PM_FUSES_3__BapmVddNbVidHiSidd_0_MASK 0xff000000 +#define PM_FUSES_3__BapmVddNbVidHiSidd_0__SHIFT 0x18 +#define PM_FUSES_4__BapmVddNbVidLoSidd_2_MASK 0xff +#define PM_FUSES_4__BapmVddNbVidLoSidd_2__SHIFT 0x0 +#define PM_FUSES_4__BapmVddNbVidLoSidd_1_MASK 0xff00 +#define PM_FUSES_4__BapmVddNbVidLoSidd_1__SHIFT 0x8 +#define PM_FUSES_4__BapmVddNbVidLoSidd_0_MASK 0xff0000 +#define PM_FUSES_4__BapmVddNbVidLoSidd_0__SHIFT 0x10 +#define PM_FUSES_4__BapmVddNbVidHiSidd_4_MASK 0xff000000 +#define PM_FUSES_4__BapmVddNbVidHiSidd_4__SHIFT 0x18 +#define PM_FUSES_5__CpuIdModel_MASK 0xff +#define PM_FUSES_5__CpuIdModel__SHIFT 0x0 +#define PM_FUSES_5__SviLoadLineEn_MASK 0xff00 +#define PM_FUSES_5__SviLoadLineEn__SHIFT 0x8 +#define PM_FUSES_5__BapmVddNbVidLoSidd_4_MASK 0xff0000 +#define PM_FUSES_5__BapmVddNbVidLoSidd_4__SHIFT 0x10 +#define PM_FUSES_5__BapmVddNbVidLoSidd_3_MASK 0xff000000 +#define PM_FUSES_5__BapmVddNbVidLoSidd_3__SHIFT 0x18 +#define PM_FUSES_6__SviLoadLineTrimVddNb_MASK 0xff +#define PM_FUSES_6__SviLoadLineTrimVddNb__SHIFT 0x0 +#define PM_FUSES_6__SviLoadLineTrimVdd_MASK 0xff00 +#define PM_FUSES_6__SviLoadLineTrimVdd__SHIFT 0x8 +#define PM_FUSES_6__SviLoadLineVddNb_MASK 0xff0000 +#define PM_FUSES_6__SviLoadLineVddNb__SHIFT 0x10 +#define PM_FUSES_6__SviLoadLineVdd_MASK 0xff000000 +#define PM_FUSES_6__SviLoadLineVdd__SHIFT 0x18 +#define PM_FUSES_7__BAPMTI_TjOffset_0_MASK 0xffff +#define PM_FUSES_7__BAPMTI_TjOffset_0__SHIFT 0x0 +#define PM_FUSES_7__SviLoadLineOffsetVddNb_MASK 0xff0000 +#define PM_FUSES_7__SviLoadLineOffsetVddNb__SHIFT 0x10 +#define PM_FUSES_7__SviLoadLineOffsetVdd_MASK 0xff000000 +#define PM_FUSES_7__SviLoadLineOffsetVdd__SHIFT 0x18 +#define PM_FUSES_8__BAPMTI_TjOffset_2_MASK 0xffff +#define PM_FUSES_8__BAPMTI_TjOffset_2__SHIFT 0x0 +#define PM_FUSES_8__BAPMTI_TjOffset_1_MASK 0xffff0000 +#define PM_FUSES_8__BAPMTI_TjOffset_1__SHIFT 0x10 +#define PM_FUSES_9__BAPMTI_TjHyst_1_MASK 0xffff +#define PM_FUSES_9__BAPMTI_TjHyst_1__SHIFT 0x0 +#define PM_FUSES_9__BAPMTI_TjHyst_0_MASK 0xffff0000 +#define PM_FUSES_9__BAPMTI_TjHyst_0__SHIFT 0x10 +#define PM_FUSES_10__BAPMTI_TjMax_1_MASK 0xff +#define PM_FUSES_10__BAPMTI_TjMax_1__SHIFT 0x0 +#define PM_FUSES_10__BAPMTI_TjMax_0_MASK 0xff00 +#define PM_FUSES_10__BAPMTI_TjMax_0__SHIFT 0x8 +#define PM_FUSES_10__BAPMTI_GpuTjHyst_MASK 0xffff0000 +#define PM_FUSES_10__BAPMTI_GpuTjHyst__SHIFT 0x10 +#define PM_FUSES_11__LhtcTmpLmt_MASK 0xff +#define PM_FUSES_11__LhtcTmpLmt__SHIFT 0x0 +#define PM_FUSES_11__LhtcPstateLimit_MASK 0xff00 +#define PM_FUSES_11__LhtcPstateLimit__SHIFT 0x8 +#define PM_FUSES_11__LhtcHystLmt_MASK 0xff0000 +#define PM_FUSES_11__LhtcHystLmt__SHIFT 0x10 +#define PM_FUSES_11__BAPMTI_GpuTjMax_MASK 0xff000000 +#define PM_FUSES_11__BAPMTI_GpuTjMax__SHIFT 0x18 +#define PM_FUSES_12__MaxPwrCpu_1_MASK 0xff +#define PM_FUSES_12__MaxPwrCpu_1__SHIFT 0x0 +#define PM_FUSES_12__MaxPwrCpu_0_MASK 0xff00 +#define PM_FUSES_12__MaxPwrCpu_0__SHIFT 0x8 +#define PM_FUSES_12__NomPwrCpu_1_MASK 0xff0000 +#define PM_FUSES_12__NomPwrCpu_1__SHIFT 0x10 +#define PM_FUSES_12__NomPwrCpu_0_MASK 0xff000000 +#define PM_FUSES_12__NomPwrCpu_0__SHIFT 0x18 +#define PM_FUSES_13__NomPwrGpu_MASK 0xffff +#define PM_FUSES_13__NomPwrGpu__SHIFT 0x0 +#define PM_FUSES_13__MidPwrCpu_1_MASK 0xff0000 +#define PM_FUSES_13__MidPwrCpu_1__SHIFT 0x10 +#define PM_FUSES_13__MidPwrCpu_0_MASK 0xff000000 +#define PM_FUSES_13__MidPwrCpu_0__SHIFT 0x18 +#define PM_FUSES_14__MinPwrGpu_MASK 0xffff +#define PM_FUSES_14__MinPwrGpu__SHIFT 0x0 +#define PM_FUSES_14__MaxPwrGpu_MASK 0xffff0000 +#define PM_FUSES_14__MaxPwrGpu__SHIFT 0x10 +#define PM_FUSES_15__PCIe3PhyOffset_MASK 0xff +#define PM_FUSES_15__PCIe3PhyOffset__SHIFT 0x0 +#define PM_FUSES_15__PCIe2PhyOffset_MASK 0xff00 +#define PM_FUSES_15__PCIe2PhyOffset__SHIFT 0x8 +#define PM_FUSES_15__PCIe1PhyOffset_MASK 0xff0000 +#define PM_FUSES_15__PCIe1PhyOffset__SHIFT 0x10 +#define PM_FUSES_15__MidPwrTempHyst_MASK 0xff000000 +#define PM_FUSES_15__MidPwrTempHyst__SHIFT 0x18 +#define PM_FUSES_16__TDC_VDD_PkgLimit_MASK 0xffff +#define PM_FUSES_16__TDC_VDD_PkgLimit__SHIFT 0x0 +#define PM_FUSES_16__DCE2PhyOffset_MASK 0xff0000 +#define PM_FUSES_16__DCE2PhyOffset__SHIFT 0x10 +#define PM_FUSES_16__DCE1PhyOffset_MASK 0xff000000 +#define PM_FUSES_16__DCE1PhyOffset__SHIFT 0x18 +#define PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc_MASK 0xff +#define PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc__SHIFT 0x0 +#define PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc_MASK 0xff00 +#define PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc__SHIFT 0x8 +#define PM_FUSES_17__TDC_VDDNB_PkgLimit_MASK 0xffff0000 +#define PM_FUSES_17__TDC_VDDNB_PkgLimit__SHIFT 0x10 +#define PM_FUSES_18__TdcWaterfallCtl_MASK 0xff +#define PM_FUSES_18__TdcWaterfallCtl__SHIFT 0x0 +#define PM_FUSES_18__TdpAgeRate_MASK 0xff00 +#define PM_FUSES_18__TdpAgeRate__SHIFT 0x8 +#define PM_FUSES_18__TdpAgeValue_MASK 0xff0000 +#define PM_FUSES_18__TdpAgeValue__SHIFT 0x10 +#define PM_FUSES_18__TDC_MAWt_MASK 0xff000000 +#define PM_FUSES_18__TDC_MAWt__SHIFT 0x18 +#define PM_FUSES_19__BapmLhtcCap_MASK 0xff +#define PM_FUSES_19__BapmLhtcCap__SHIFT 0x0 +#define PM_FUSES_19__BapmFuseOverride_MASK 0xff00 +#define PM_FUSES_19__BapmFuseOverride__SHIFT 0x8 +#define PM_FUSES_19__SmuCoolingIndex_MASK 0xff0000 +#define PM_FUSES_19__SmuCoolingIndex__SHIFT 0x10 +#define PM_FUSES_19__SmuSocIndex_MASK 0xff000000 +#define PM_FUSES_19__SmuSocIndex__SHIFT 0x18 +#define PM_FUSES_20__SamClkDid_3_MASK 0xff +#define PM_FUSES_20__SamClkDid_3__SHIFT 0x0 +#define PM_FUSES_20__SamClkDid_2_MASK 0xff00 +#define PM_FUSES_20__SamClkDid_2__SHIFT 0x8 +#define PM_FUSES_20__SamClkDid_1_MASK 0xff0000 +#define PM_FUSES_20__SamClkDid_1__SHIFT 0x10 +#define PM_FUSES_20__SamClkDid_0_MASK 0xff000000 +#define PM_FUSES_20__SamClkDid_0__SHIFT 0x18 +#define PM_FUSES_21__AmbientTempBase_MASK 0xff +#define PM_FUSES_21__AmbientTempBase__SHIFT 0x0 +#define PM_FUSES_21__LPMLTemperatureMax_MASK 0xff00 +#define PM_FUSES_21__LPMLTemperatureMax__SHIFT 0x8 +#define PM_FUSES_21__LPMLTemperatureMin_MASK 0xff0000 +#define PM_FUSES_21__LPMLTemperatureMin__SHIFT 0x10 +#define PM_FUSES_21__SamClkDid_4_MASK 0xff000000 +#define PM_FUSES_21__SamClkDid_4__SHIFT 0x18 +#define PM_FUSES_22__LPMLTemperatureScaler_3_MASK 0xff +#define PM_FUSES_22__LPMLTemperatureScaler_3__SHIFT 0x0 +#define PM_FUSES_22__LPMLTemperatureScaler_2_MASK 0xff00 +#define PM_FUSES_22__LPMLTemperatureScaler_2__SHIFT 0x8 +#define PM_FUSES_22__LPMLTemperatureScaler_1_MASK 0xff0000 +#define PM_FUSES_22__LPMLTemperatureScaler_1__SHIFT 0x10 +#define PM_FUSES_22__LPMLTemperatureScaler_0_MASK 0xff000000 +#define PM_FUSES_22__LPMLTemperatureScaler_0__SHIFT 0x18 +#define PM_FUSES_23__LPMLTemperatureScaler_7_MASK 0xff +#define PM_FUSES_23__LPMLTemperatureScaler_7__SHIFT 0x0 +#define PM_FUSES_23__LPMLTemperatureScaler_6_MASK 0xff00 +#define PM_FUSES_23__LPMLTemperatureScaler_6__SHIFT 0x8 +#define PM_FUSES_23__LPMLTemperatureScaler_5_MASK 0xff0000 +#define PM_FUSES_23__LPMLTemperatureScaler_5__SHIFT 0x10 +#define PM_FUSES_23__LPMLTemperatureScaler_4_MASK 0xff000000 +#define PM_FUSES_23__LPMLTemperatureScaler_4__SHIFT 0x18 +#define PM_FUSES_24__LPMLTemperatureScaler_11_MASK 0xff +#define PM_FUSES_24__LPMLTemperatureScaler_11__SHIFT 0x0 +#define PM_FUSES_24__LPMLTemperatureScaler_10_MASK 0xff00 +#define PM_FUSES_24__LPMLTemperatureScaler_10__SHIFT 0x8 +#define PM_FUSES_24__LPMLTemperatureScaler_9_MASK 0xff0000 +#define PM_FUSES_24__LPMLTemperatureScaler_9__SHIFT 0x10 +#define PM_FUSES_24__LPMLTemperatureScaler_8_MASK 0xff000000 +#define PM_FUSES_24__LPMLTemperatureScaler_8__SHIFT 0x18 +#define PM_FUSES_25__LPMLTemperatureScaler_15_MASK 0xff +#define PM_FUSES_25__LPMLTemperatureScaler_15__SHIFT 0x0 +#define PM_FUSES_25__LPMLTemperatureScaler_14_MASK 0xff00 +#define PM_FUSES_25__LPMLTemperatureScaler_14__SHIFT 0x8 +#define PM_FUSES_25__LPMLTemperatureScaler_13_MASK 0xff0000 +#define PM_FUSES_25__LPMLTemperatureScaler_13__SHIFT 0x10 +#define PM_FUSES_25__LPMLTemperatureScaler_12_MASK 0xff000000 +#define PM_FUSES_25__LPMLTemperatureScaler_12__SHIFT 0x18 +#define PM_FUSES_26__GnbLPML_3_MASK 0xff +#define PM_FUSES_26__GnbLPML_3__SHIFT 0x0 +#define PM_FUSES_26__GnbLPML_2_MASK 0xff00 +#define PM_FUSES_26__GnbLPML_2__SHIFT 0x8 +#define PM_FUSES_26__GnbLPML_1_MASK 0xff0000 +#define PM_FUSES_26__GnbLPML_1__SHIFT 0x10 +#define PM_FUSES_26__GnbLPML_0_MASK 0xff000000 +#define PM_FUSES_26__GnbLPML_0__SHIFT 0x18 +#define PM_FUSES_27__GnbLPML_7_MASK 0xff +#define PM_FUSES_27__GnbLPML_7__SHIFT 0x0 +#define PM_FUSES_27__GnbLPML_6_MASK 0xff00 +#define PM_FUSES_27__GnbLPML_6__SHIFT 0x8 +#define PM_FUSES_27__GnbLPML_5_MASK 0xff0000 +#define PM_FUSES_27__GnbLPML_5__SHIFT 0x10 +#define PM_FUSES_27__GnbLPML_4_MASK 0xff000000 +#define PM_FUSES_27__GnbLPML_4__SHIFT 0x18 +#define PM_FUSES_28__GnbLPML_11_MASK 0xff +#define PM_FUSES_28__GnbLPML_11__SHIFT 0x0 +#define PM_FUSES_28__GnbLPML_10_MASK 0xff00 +#define PM_FUSES_28__GnbLPML_10__SHIFT 0x8 +#define PM_FUSES_28__GnbLPML_9_MASK 0xff0000 +#define PM_FUSES_28__GnbLPML_9__SHIFT 0x10 +#define PM_FUSES_28__GnbLPML_8_MASK 0xff000000 +#define PM_FUSES_28__GnbLPML_8__SHIFT 0x18 +#define PM_FUSES_29__GnbLPML_15_MASK 0xff +#define PM_FUSES_29__GnbLPML_15__SHIFT 0x0 +#define PM_FUSES_29__GnbLPML_14_MASK 0xff00 +#define PM_FUSES_29__GnbLPML_14__SHIFT 0x8 +#define PM_FUSES_29__GnbLPML_13_MASK 0xff0000 +#define PM_FUSES_29__GnbLPML_13__SHIFT 0x10 +#define PM_FUSES_29__GnbLPML_12_MASK 0xff000000 +#define PM_FUSES_29__GnbLPML_12__SHIFT 0x18 +#define PM_FUSES_30__NbVid_3_MASK 0xff +#define PM_FUSES_30__NbVid_3__SHIFT 0x0 +#define PM_FUSES_30__NbVid_2_MASK 0xff00 +#define PM_FUSES_30__NbVid_2__SHIFT 0x8 +#define PM_FUSES_30__NbVid_1_MASK 0xff0000 +#define PM_FUSES_30__NbVid_1__SHIFT 0x10 +#define PM_FUSES_30__NbVid_0_MASK 0xff000000 +#define PM_FUSES_30__NbVid_0__SHIFT 0x18 +#define PM_FUSES_31__CpuVid_3_MASK 0xff +#define PM_FUSES_31__CpuVid_3__SHIFT 0x0 +#define PM_FUSES_31__CpuVid_2_MASK 0xff00 +#define PM_FUSES_31__CpuVid_2__SHIFT 0x8 +#define PM_FUSES_31__CpuVid_1_MASK 0xff0000 +#define PM_FUSES_31__CpuVid_1__SHIFT 0x10 +#define PM_FUSES_31__CpuVid_0_MASK 0xff000000 +#define PM_FUSES_31__CpuVid_0__SHIFT 0x18 +#define PM_FUSES_32__CpuVid_7_MASK 0xff +#define PM_FUSES_32__CpuVid_7__SHIFT 0x0 +#define PM_FUSES_32__CpuVid_6_MASK 0xff00 +#define PM_FUSES_32__CpuVid_6__SHIFT 0x8 +#define PM_FUSES_32__CpuVid_5_MASK 0xff0000 +#define PM_FUSES_32__CpuVid_5__SHIFT 0x10 +#define PM_FUSES_32__CpuVid_4_MASK 0xff000000 +#define PM_FUSES_32__CpuVid_4__SHIFT 0x18 +#define PM_FUSES_33__Tdp2Watt_MASK 0xffff +#define PM_FUSES_33__Tdp2Watt__SHIFT 0x0 +#define PM_FUSES_33__GnbLPMLMinVid_MASK 0xff0000 +#define PM_FUSES_33__GnbLPMLMinVid__SHIFT 0x10 +#define PM_FUSES_33__GnbLPMLMaxVid_MASK 0xff000000 +#define PM_FUSES_33__GnbLPMLMaxVid__SHIFT 0x18 +#define PM_FUSES_34__Lpml_3_MASK 0xff +#define PM_FUSES_34__Lpml_3__SHIFT 0x0 +#define PM_FUSES_34__Lpml_2_MASK 0xff00 +#define PM_FUSES_34__Lpml_2__SHIFT 0x8 +#define PM_FUSES_34__Lpml_1_MASK 0xff0000 +#define PM_FUSES_34__Lpml_1__SHIFT 0x10 +#define PM_FUSES_34__Lpml_0_MASK 0xff000000 +#define PM_FUSES_34__Lpml_0__SHIFT 0x18 +#define PM_FUSES_35__Lpml_7_MASK 0xff +#define PM_FUSES_35__Lpml_7__SHIFT 0x0 +#define PM_FUSES_35__Lpml_6_MASK 0xff00 +#define PM_FUSES_35__Lpml_6__SHIFT 0x8 +#define PM_FUSES_35__Lpml_5_MASK 0xff0000 +#define PM_FUSES_35__Lpml_5__SHIFT 0x10 +#define PM_FUSES_35__Lpml_4_MASK 0xff000000 +#define PM_FUSES_35__Lpml_4__SHIFT 0x18 +#define PM_FUSES_36__Lpmv_3_MASK 0xff +#define PM_FUSES_36__Lpmv_3__SHIFT 0x0 +#define PM_FUSES_36__Lpmv_2_MASK 0xff00 +#define PM_FUSES_36__Lpmv_2__SHIFT 0x8 +#define PM_FUSES_36__Lpmv_1_MASK 0xff0000 +#define PM_FUSES_36__Lpmv_1__SHIFT 0x10 +#define PM_FUSES_36__Lpmv_0_MASK 0xff000000 +#define PM_FUSES_36__Lpmv_0__SHIFT 0x18 +#define PM_FUSES_37__Lpmv_7_MASK 0xff +#define PM_FUSES_37__Lpmv_7__SHIFT 0x0 +#define PM_FUSES_37__Lpmv_6_MASK 0xff00 +#define PM_FUSES_37__Lpmv_6__SHIFT 0x8 +#define PM_FUSES_37__Lpmv_5_MASK 0xff0000 +#define PM_FUSES_37__Lpmv_5__SHIFT 0x10 +#define PM_FUSES_37__Lpmv_4_MASK 0xff000000 +#define PM_FUSES_37__Lpmv_4__SHIFT 0x18 +#define PM_FUSES_38__EClkDid_3_MASK 0xff +#define PM_FUSES_38__EClkDid_3__SHIFT 0x0 +#define PM_FUSES_38__EClkDid_2_MASK 0xff00 +#define PM_FUSES_38__EClkDid_2__SHIFT 0x8 +#define PM_FUSES_38__EClkDid_1_MASK 0xff0000 +#define PM_FUSES_38__EClkDid_1__SHIFT 0x10 +#define PM_FUSES_38__EClkDid_0_MASK 0xff000000 +#define PM_FUSES_38__EClkDid_0__SHIFT 0x18 +#define PM_FUSES_39__CoreDis_MASK 0xff +#define PM_FUSES_39__CoreDis__SHIFT 0x0 +#define PM_FUSES_39__C6CstatePower_MASK 0xff00 +#define PM_FUSES_39__C6CstatePower__SHIFT 0x8 +#define PM_FUSES_39__BoostLock_MASK 0xff0000 +#define PM_FUSES_39__BoostLock__SHIFT 0x10 +#define PM_FUSES_39__EClkDid_4_MASK 0xff000000 +#define PM_FUSES_39__EClkDid_4__SHIFT 0x18 +#define PM_FUSES_40__BapmVddNbBaseLeakageLoSidd_MASK 0xffff +#define PM_FUSES_40__BapmVddNbBaseLeakageLoSidd__SHIFT 0x0 +#define PM_FUSES_40__BapmVddNbBaseLeakageHiSidd_MASK 0xffff0000 +#define PM_FUSES_40__BapmVddNbBaseLeakageHiSidd__SHIFT 0x10 +#define PM_FUSES_41__VddNbVid_3_MASK 0xff +#define PM_FUSES_41__VddNbVid_3__SHIFT 0x0 +#define PM_FUSES_41__VddNbVid_2_MASK 0xff00 +#define PM_FUSES_41__VddNbVid_2__SHIFT 0x8 +#define PM_FUSES_41__VddNbVid_1_MASK 0xff0000 +#define PM_FUSES_41__VddNbVid_1__SHIFT 0x10 +#define PM_FUSES_41__VddNbVid_0_MASK 0xff000000 +#define PM_FUSES_41__VddNbVid_0__SHIFT 0x18 +#define PM_FUSES_42__VddNbVidOffset_2_MASK 0xff +#define PM_FUSES_42__VddNbVidOffset_2__SHIFT 0x0 +#define PM_FUSES_42__VddNbVidOffset_1_MASK 0xff00 +#define PM_FUSES_42__VddNbVidOffset_1__SHIFT 0x8 +#define PM_FUSES_42__VddNbVidOffset_0_MASK 0xff0000 +#define PM_FUSES_42__VddNbVidOffset_0__SHIFT 0x10 +#define PM_FUSES_42__VddNbVid_4_MASK 0xff000000 +#define PM_FUSES_42__VddNbVid_4__SHIFT 0x18 +#define PM_FUSES_43__BapmDisable_MASK 0xff +#define PM_FUSES_43__BapmDisable__SHIFT 0x0 +#define PM_FUSES_43__CoreTdpLimit0_MASK 0xff00 +#define PM_FUSES_43__CoreTdpLimit0__SHIFT 0x8 +#define PM_FUSES_43__VddNbVidOffset_4_MASK 0xff0000 +#define PM_FUSES_43__VddNbVidOffset_4__SHIFT 0x10 +#define PM_FUSES_43__VddNbVidOffset_3_MASK 0xff000000 +#define PM_FUSES_43__VddNbVidOffset_3__SHIFT 0x18 +#define PM_FUSES_44__LpmlL2_3_MASK 0xff +#define PM_FUSES_44__LpmlL2_3__SHIFT 0x0 +#define PM_FUSES_44__LpmlL2_2_MASK 0xff00 +#define PM_FUSES_44__LpmlL2_2__SHIFT 0x8 +#define PM_FUSES_44__LpmlL2_1_MASK 0xff0000 +#define PM_FUSES_44__LpmlL2_1__SHIFT 0x10 +#define PM_FUSES_44__LpmlL2_0_MASK 0xff000000 +#define PM_FUSES_44__LpmlL2_0__SHIFT 0x18 +#define PM_FUSES_45__LpmlL2_7_MASK 0xff +#define PM_FUSES_45__LpmlL2_7__SHIFT 0x0 +#define PM_FUSES_45__LpmlL2_6_MASK 0xff00 +#define PM_FUSES_45__LpmlL2_6__SHIFT 0x8 +#define PM_FUSES_45__LpmlL2_5_MASK 0xff0000 +#define PM_FUSES_45__LpmlL2_5__SHIFT 0x10 +#define PM_FUSES_45__LpmlL2_4_MASK 0xff000000 +#define PM_FUSES_45__LpmlL2_4__SHIFT 0x18 +#define PM_FUSES_46__CoolPdmTc_MASK 0xff +#define PM_FUSES_46__CoolPdmTc__SHIFT 0x0 +#define PM_FUSES_46__BaseCpcTdpLimit2_MASK 0xff00 +#define PM_FUSES_46__BaseCpcTdpLimit2__SHIFT 0x8 +#define PM_FUSES_46__BaseCpcTdpLimit1_MASK 0xff0000 +#define PM_FUSES_46__BaseCpcTdpLimit1__SHIFT 0x10 +#define PM_FUSES_46__BaseCpcTdpLimit_MASK 0xff000000 +#define PM_FUSES_46__BaseCpcTdpLimit__SHIFT 0x18 +#define PM_FUSES_47__CoolPdmThr2_MASK 0xff +#define PM_FUSES_47__CoolPdmThr2__SHIFT 0x0 +#define PM_FUSES_47__CoolPdmThr1_MASK 0xff00 +#define PM_FUSES_47__CoolPdmThr1__SHIFT 0x8 +#define PM_FUSES_47__GpuPdmTc_MASK 0xff0000 +#define PM_FUSES_47__GpuPdmTc__SHIFT 0x10 +#define PM_FUSES_47__HeatPdmTc_MASK 0xff000000 +#define PM_FUSES_47__HeatPdmTc__SHIFT 0x18 +#define PM_FUSES_48__PkgPwr_MAWt_MASK 0xff +#define PM_FUSES_48__PkgPwr_MAWt__SHIFT 0x0 +#define PM_FUSES_48__GpuActThr_MASK 0xff00 +#define PM_FUSES_48__GpuActThr__SHIFT 0x8 +#define PM_FUSES_48__HeatPdmThr2_MASK 0xff0000 +#define PM_FUSES_48__HeatPdmThr2__SHIFT 0x10 +#define PM_FUSES_48__HeatPdmThr1_MASK 0xff000000 +#define PM_FUSES_48__HeatPdmThr1__SHIFT 0x18 +#define PM_FUSES_49__SocketTdp_MASK 0xffff +#define PM_FUSES_49__SocketTdp__SHIFT 0x0 +#define PM_FUSES_49__GpuPdmMult_MASK 0xffff0000 +#define PM_FUSES_49__GpuPdmMult__SHIFT 0x10 +#define PM_FUSES_50__Reserved2_MASK 0xffff +#define PM_FUSES_50__Reserved2__SHIFT 0x0 +#define PM_FUSES_50__Reserved1_MASK 0xff0000 +#define PM_FUSES_50__Reserved1__SHIFT 0x10 +#define PM_FUSES_50__NumBoostStates_MASK 0xff000000 +#define PM_FUSES_50__NumBoostStates__SHIFT 0x18 +#define PM_FUSES_51__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_51__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_52__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_52__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_53__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_53__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_54__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_54__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_55__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_55__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_56__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_56__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_57__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_57__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_58__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_58__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_59__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_59__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_60__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_60__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_61__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_61__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_62__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_62__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_63__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_63__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_64__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_64__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_65__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_65__FUSE_DATA__SHIFT 0x0 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe +#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 +#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 +#define TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f +#define TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0 +#define TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0 +#define TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6 +#define TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00 +#define TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa +#define CURRENT_GNB_TEMP__TEMP_MASK 0x7ff +#define CURRENT_GNB_TEMP__TEMP__SHIFT 0x0 +#define CURRENT_GLOBAL_TEMP__TEMP_MASK 0x7ff +#define CURRENT_GLOBAL_TEMP__TEMP__SHIFT 0x0 +#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 +#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 +#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 +#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 +#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 +#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 +#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 +#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 +#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 +#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 +#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20 +#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5 +#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40 +#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6 +#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 +#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 +#define FEATURE_STATUS__BAPM_ON_MASK 0x100 +#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 +#define FEATURE_STATUS__LPMX_ON_MASK 0x200 +#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 +#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 +#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa +#define FEATURE_STATUS__LHTC_ON_MASK 0x800 +#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb +#define FEATURE_STATUS__VPC_ON_MASK 0x1000 +#define FEATURE_STATUS__VPC_ON__SHIFT 0xc +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd +#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 +#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe +#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 +#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf +#define FEATURE_STATUS__AVS_ON_MASK 0x10000 +#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 +#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 +#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 +#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 +#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 +#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 +#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 +#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 +#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 +#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 +#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 +#define FEATURE_STATUS__CLK_MON_ON_MASK 0x400000 +#define FEATURE_STATUS__CLK_MON_ON__SHIFT 0x16 +#define FEATURE_STATUS__RESERVED_MASK 0xff800000 +#define FEATURE_STATUS__RESERVED__SHIFT 0x17 +#define PCIE_PLL_RECONF__RECONF_WAIT_MASK 0xff +#define PCIE_PLL_RECONF__RECONF_WAIT__SHIFT 0x0 +#define PCIE_PLL_RECONF__RECONF_WRAPPER_MASK 0xff00 +#define PCIE_PLL_RECONF__RECONF_WRAPPER__SHIFT 0x8 +#define PCIE_PLL_RECONF__SB_RELOCATE_EN_MASK 0xff0000 +#define PCIE_PLL_RECONF__SB_RELOCATE_EN__SHIFT 0x10 +#define PCIE_PLL_RECONF__SB_NEW_PORT_MASK 0xff000000 +#define PCIE_PLL_RECONF__SB_NEW_PORT__SHIFT 0x18 +#define PM_INTERVAL_CNTL_0__LCLK_DPM_MASK 0xff +#define PM_INTERVAL_CNTL_0__LCLK_DPM__SHIFT 0x0 +#define PM_INTERVAL_CNTL_0__THERMAL_CNTL_MASK 0xff00 +#define PM_INTERVAL_CNTL_0__THERMAL_CNTL__SHIFT 0x8 +#define PM_INTERVAL_CNTL_0__VOLTAGE_CNTL_MASK 0xff0000 +#define PM_INTERVAL_CNTL_0__VOLTAGE_CNTL__SHIFT 0x10 +#define PM_INTERVAL_CNTL_0__LOADLINE_MASK 0xff000000 +#define PM_INTERVAL_CNTL_0__LOADLINE__SHIFT 0x18 +#define PM_INTERVAL_CNTL_1__NB_DPM_MASK 0xff +#define PM_INTERVAL_CNTL_1__NB_DPM__SHIFT 0x0 +#define PM_INTERVAL_CNTL_1__AVS_PERIOD_MASK 0xff00 +#define PM_INTERVAL_CNTL_1__AVS_PERIOD__SHIFT 0x8 +#define PM_INTERVAL_CNTL_1__PKGPWR_PERIOD_MASK 0xff0000 +#define PM_INTERVAL_CNTL_1__PKGPWR_PERIOD__SHIFT 0x10 +#define PM_INTERVAL_CNTL_1__TDP_CNTL_MASK 0xff000000 +#define PM_INTERVAL_CNTL_1__TDP_CNTL__SHIFT 0x18 +#define PM_INTERVAL_CNTL_2__BAPM_PERIOD_MASK 0xff +#define PM_INTERVAL_CNTL_2__BAPM_PERIOD__SHIFT 0x0 +#define PM_INTERVAL_CNTL_2__HTC_PERIOD_MASK 0xff00 +#define PM_INTERVAL_CNTL_2__HTC_PERIOD__SHIFT 0x8 +#define PM_INTERVAL_CNTL_2__TDC_PERIOD_MASK 0xff0000 +#define PM_INTERVAL_CNTL_2__TDC_PERIOD__SHIFT 0x10 +#define PM_INTERVAL_CNTL_2__LPMX_PERIOD_MASK 0xff000000 +#define PM_INTERVAL_CNTL_2__LPMX_PERIOD__SHIFT 0x18 +#define VPC_INTERVAL_CNTL__VPC_PERIOD_MASK 0xffffffff +#define VPC_INTERVAL_CNTL__VPC_PERIOD__SHIFT 0x0 +#define DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit_MASK 0xffffffff +#define DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit__SHIFT 0x0 +#define FCH_PWR_CREDIT__FchPwrCredit_MASK 0xffffffff +#define FCH_PWR_CREDIT__FchPwrCredit__SHIFT 0x0 +#define PKGPWR_MV_AVG__Avg_Pkg_Pwr_MASK 0xffffffff +#define PKGPWR_MV_AVG__Avg_Pkg_Pwr__SHIFT 0x0 +#define PACKAGE_POWER__Pkg_power_MASK 0xffffffff +#define PACKAGE_POWER__Pkg_power__SHIFT 0x0 +#define PKG_PWR_CNTL__CpcGpuPerfPri_MASK 0x1 +#define PKG_PWR_CNTL__CpcGpuPerfPri__SHIFT 0x0 +#define PKG_PWR_CNTL__PkgPwrLimit_MASK 0x1fffe +#define PKG_PWR_CNTL__PkgPwrLimit__SHIFT 0x1 +#define PKG_PWR_CNTL__FchPwrCreditScale_MASK 0x7e0000 +#define PKG_PWR_CNTL__FchPwrCreditScale__SHIFT 0x11 +#define PKG_PWR_CNTL__PkgHystCoeff_MASK 0x1f800000 +#define PKG_PWR_CNTL__PkgHystCoeff__SHIFT 0x17 +#define PKG_PWR_CNTL__RESERVED_MASK 0xe0000000 +#define PKG_PWR_CNTL__RESERVED__SHIFT 0x1d +#define PKG_PWR_STATUS__GnbMinLimitSetFlag_MASK 0x1 +#define PKG_PWR_STATUS__GnbMinLimitSetFlag__SHIFT 0x0 +#define PKG_PWR_STATUS__PstateLimitSetFlag_MASK 0x2 +#define PKG_PWR_STATUS__PstateLimitSetFlag__SHIFT 0x1 +#define PKG_PWR_STATUS__PkgPwrLimit_base_MASK 0x3fffc +#define PKG_PWR_STATUS__PkgPwrLimit_base__SHIFT 0x2 +#define PKG_PWR_STATUS__RESERVED_MASK 0xfc0000 +#define PKG_PWR_STATUS__RESERVED__SHIFT 0x12 +#define PKG_PWR_STATUS__PkgPwr_MAWt_MASK 0xff000000 +#define PKG_PWR_STATUS__PkgPwr_MAWt__SHIFT 0x18 +#define DISP_PHY_CONFIG__Corner_MASK 0xff +#define DISP_PHY_CONFIG__Corner__SHIFT 0x0 +#define DISP_PHY_CONFIG__DispPHYConfig_MASK 0xff00 +#define DISP_PHY_CONFIG__DispPHYConfig__SHIFT 0x8 +#define GPU_TDP_LIMIT__Gpu_Tdp_Limit_MASK 0xffff +#define GPU_TDP_LIMIT__Gpu_Tdp_Limit__SHIFT 0x0 +#define GPU_TDP_LIMIT__Reserved_MASK 0xffff0000 +#define GPU_TDP_LIMIT__Reserved__SHIFT 0x10 +#define EXT_API_IN_DATA_0_0__byte0_MASK 0xff +#define EXT_API_IN_DATA_0_0__byte0__SHIFT 0x0 +#define EXT_API_IN_DATA_0_0__byte1_MASK 0xff00 +#define EXT_API_IN_DATA_0_0__byte1__SHIFT 0x8 +#define EXT_API_IN_DATA_0_0__byte2_MASK 0xff0000 +#define EXT_API_IN_DATA_0_0__byte2__SHIFT 0x10 +#define EXT_API_IN_DATA_0_0__byte3_MASK 0xff000000 +#define EXT_API_IN_DATA_0_0__byte3__SHIFT 0x18 +#define EXT_API_IN_DATA_0_1__byte0_MASK 0xff +#define EXT_API_IN_DATA_0_1__byte0__SHIFT 0x0 +#define EXT_API_IN_DATA_0_1__byte1_MASK 0xff00 +#define EXT_API_IN_DATA_0_1__byte1__SHIFT 0x8 +#define EXT_API_IN_DATA_0_1__byte2_MASK 0xff0000 +#define EXT_API_IN_DATA_0_1__byte2__SHIFT 0x10 +#define EXT_API_IN_DATA_0_1__byte3_MASK 0xff000000 +#define EXT_API_IN_DATA_0_1__byte3__SHIFT 0x18 +#define EXT_API_IN_DATA_0_2__byte0_MASK 0xff +#define EXT_API_IN_DATA_0_2__byte0__SHIFT 0x0 +#define EXT_API_IN_DATA_0_2__byte1_MASK 0xff00 +#define EXT_API_IN_DATA_0_2__byte1__SHIFT 0x8 +#define EXT_API_IN_DATA_0_2__byte2_MASK 0xff0000 +#define EXT_API_IN_DATA_0_2__byte2__SHIFT 0x10 +#define EXT_API_IN_DATA_0_2__byte3_MASK 0xff000000 +#define EXT_API_IN_DATA_0_2__byte3__SHIFT 0x18 +#define EXT_API_IN_DATA_0_3__byte0_MASK 0xff +#define EXT_API_IN_DATA_0_3__byte0__SHIFT 0x0 +#define EXT_API_IN_DATA_0_3__byte1_MASK 0xff00 +#define EXT_API_IN_DATA_0_3__byte1__SHIFT 0x8 +#define EXT_API_IN_DATA_0_3__byte2_MASK 0xff0000 +#define EXT_API_IN_DATA_0_3__byte2__SHIFT 0x10 +#define EXT_API_IN_DATA_0_3__byte3_MASK 0xff000000 +#define EXT_API_IN_DATA_0_3__byte3__SHIFT 0x18 +#define EXT_API_OUT_DATA_0_0__byte0_MASK 0xff +#define EXT_API_OUT_DATA_0_0__byte0__SHIFT 0x0 +#define EXT_API_OUT_DATA_0_0__byte1_MASK 0xff00 +#define EXT_API_OUT_DATA_0_0__byte1__SHIFT 0x8 +#define EXT_API_OUT_DATA_0_0__byte2_MASK 0xff0000 +#define EXT_API_OUT_DATA_0_0__byte2__SHIFT 0x10 +#define EXT_API_OUT_DATA_0_0__byte3_MASK 0xff000000 +#define EXT_API_OUT_DATA_0_0__byte3__SHIFT 0x18 +#define EXT_API_OUT_DATA_0_1__byte0_MASK 0xff +#define EXT_API_OUT_DATA_0_1__byte0__SHIFT 0x0 +#define EXT_API_OUT_DATA_0_1__byte1_MASK 0xff00 +#define EXT_API_OUT_DATA_0_1__byte1__SHIFT 0x8 +#define EXT_API_OUT_DATA_0_1__byte2_MASK 0xff0000 +#define EXT_API_OUT_DATA_0_1__byte2__SHIFT 0x10 +#define EXT_API_OUT_DATA_0_1__byte3_MASK 0xff000000 +#define EXT_API_OUT_DATA_0_1__byte3__SHIFT 0x18 +#define EXT_API_OUT_DATA_0_2__byte0_MASK 0xff +#define EXT_API_OUT_DATA_0_2__byte0__SHIFT 0x0 +#define EXT_API_OUT_DATA_0_2__byte1_MASK 0xff00 +#define EXT_API_OUT_DATA_0_2__byte1__SHIFT 0x8 +#define EXT_API_OUT_DATA_0_2__byte2_MASK 0xff0000 +#define EXT_API_OUT_DATA_0_2__byte2__SHIFT 0x10 +#define EXT_API_OUT_DATA_0_2__byte3_MASK 0xff000000 +#define EXT_API_OUT_DATA_0_2__byte3__SHIFT 0x18 +#define EXT_API_OUT_DATA_0_3__byte0_MASK 0xff +#define EXT_API_OUT_DATA_0_3__byte0__SHIFT 0x0 +#define EXT_API_OUT_DATA_0_3__byte1_MASK 0xff00 +#define EXT_API_OUT_DATA_0_3__byte1__SHIFT 0x8 +#define EXT_API_OUT_DATA_0_3__byte2_MASK 0xff0000 +#define EXT_API_OUT_DATA_0_3__byte2__SHIFT 0x10 +#define EXT_API_OUT_DATA_0_3__byte3_MASK 0xff000000 +#define EXT_API_OUT_DATA_0_3__byte3__SHIFT 0x18 +#define BAPM_PARAMETERS__MaxPwrCpu_1_MASK 0xff +#define BAPM_PARAMETERS__MaxPwrCpu_1__SHIFT 0x0 +#define BAPM_PARAMETERS__NomPwrCpu_1_MASK 0xff00 +#define BAPM_PARAMETERS__NomPwrCpu_1__SHIFT 0x8 +#define BAPM_PARAMETERS__MaxPwrCpu_0_MASK 0xff0000 +#define BAPM_PARAMETERS__MaxPwrCpu_0__SHIFT 0x10 +#define BAPM_PARAMETERS__NomPwrCpu_0_MASK 0xff000000 +#define BAPM_PARAMETERS__NomPwrCpu_0__SHIFT 0x18 +#define BAPM_PARAMETERS_2__MaxPwrGpu_MASK 0xffff +#define BAPM_PARAMETERS_2__MaxPwrGpu__SHIFT 0x0 +#define BAPM_PARAMETERS_2__NomPwrGpu_MASK 0xffff0000 +#define BAPM_PARAMETERS_2__NomPwrGpu__SHIFT 0x10 +#define BAPM_PARAMETERS_3__TjOffset_MASK 0xff +#define BAPM_PARAMETERS_3__TjOffset__SHIFT 0x0 +#define BAPM_PARAMETERS_3__EnergyCntNorm_MASK 0x3ff00 +#define BAPM_PARAMETERS_3__EnergyCntNorm__SHIFT 0x8 +#define BAPM_PARAMETERS_3__Reserved_MASK 0xfffc0000 +#define BAPM_PARAMETERS_3__Reserved__SHIFT 0x12 +#define BAPM_PARAMETERS_4__MinPwrGpu_MASK 0xffff +#define BAPM_PARAMETERS_4__MinPwrGpu__SHIFT 0x0 +#define BAPM_PARAMETERS_4__MidPwrCpu_1_MASK 0xff0000 +#define BAPM_PARAMETERS_4__MidPwrCpu_1__SHIFT 0x10 +#define BAPM_PARAMETERS_4__MidPwrCpu_0_MASK 0xff000000 +#define BAPM_PARAMETERS_4__MidPwrCpu_0__SHIFT 0x18 +#define SMU_SVI_TELEMETRY__Iddspike_OCP_MASK 0xffff +#define SMU_SVI_TELEMETRY__Iddspike_OCP__SHIFT 0x0 +#define SMU_SVI_TELEMETRY__IddNbspike_OCP_MASK 0xffff0000 +#define SMU_SVI_TELEMETRY__IddNbspike_OCP__SHIFT 0x10 +#define BAPM_STATUS__THROTTLE_MASK 0xff +#define BAPM_STATUS__THROTTLE__SHIFT 0x0 +#define BAPM_STATUS__THROTTLE_LAST_MASK 0xff00 +#define BAPM_STATUS__THROTTLE_LAST__SHIFT 0x8 +#define BAPM_STATUS__COUNT_CORE1_MASK 0xff0000 +#define BAPM_STATUS__COUNT_CORE1__SHIFT 0x10 +#define BAPM_STATUS__COUNT_CORE0_MASK 0xff000000 +#define BAPM_STATUS__COUNT_CORE0__SHIFT 0x18 +#define SMU_HTC_STATUS__HTC_ACTIVE_MASK 0x1 +#define SMU_HTC_STATUS__HTC_ACTIVE__SHIFT 0x0 +#define SMU_HTC_STATUS__Reserved_MASK 0xfffffffe +#define SMU_HTC_STATUS__Reserved__SHIFT 0x1 +#define SMU_VPC_STATUS__AllCpuIdleLast_MASK 0x1 +#define SMU_VPC_STATUS__AllCpuIdleLast__SHIFT 0x0 +#define SMU_VPC_STATUS__Reserved_MASK 0xfffffffe +#define SMU_VPC_STATUS__Reserved__SHIFT 0x1 +#define ENTITY_TEMPERATURES_1__CORE0_MASK 0xffffffff +#define ENTITY_TEMPERATURES_1__CORE0__SHIFT 0x0 +#define ENTITY_TEMPERATURES_2__CORE1_MASK 0xffffffff +#define ENTITY_TEMPERATURES_2__CORE1__SHIFT 0x0 +#define ENTITY_TEMPERATURES_3__GPU_MASK 0xffffffff +#define ENTITY_TEMPERATURES_3__GPU__SHIFT 0x0 +#define CU_POWER__CU0_POWER_MASK 0xffff +#define CU_POWER__CU0_POWER__SHIFT 0x0 +#define CU_POWER__CU1_POWER_MASK 0xffff0000 +#define CU_POWER__CU1_POWER__SHIFT 0x10 +#define GPU_POWER__IGPU_POWER_MASK 0xffff +#define GPU_POWER__IGPU_POWER__SHIFT 0x0 +#define GPU_POWER__DGPU_POWER_MASK 0xffff0000 +#define GPU_POWER__DGPU_POWER__SHIFT 0x10 +#define NTE_POWER__NTE0_POWER_MASK 0xffff +#define NTE_POWER__NTE0_POWER__SHIFT 0x0 +#define NTE_POWER__NTE1_POWER_MASK 0xffff0000 +#define NTE_POWER__NTE1_POWER__SHIFT 0x10 +#define TDC_STATUS__VDD_Boost_MASK 0xff +#define TDC_STATUS__VDD_Boost__SHIFT 0x0 +#define TDC_STATUS__VDD_Throttle_MASK 0xff00 +#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 +#define TDC_STATUS__VDDNB_Boost_MASK 0xff0000 +#define TDC_STATUS__VDDNB_Boost__SHIFT 0x10 +#define TDC_STATUS__VDDNB_Throttle_MASK 0xff000000 +#define TDC_STATUS__VDDNB_Throttle__SHIFT 0x18 +#define TDC_MV_AVERAGE__IDD_MASK 0xffff +#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 +#define TDC_MV_AVERAGE__IDDNB_MASK 0xffff0000 +#define TDC_MV_AVERAGE__IDDNB__SHIFT 0x10 +#define PM_CONFIG__Enable_VPC_Accumulators_MASK 0x1 +#define PM_CONFIG__Enable_VPC_Accumulators__SHIFT 0x0 +#define PM_CONFIG__Enable_BAPM_MASK 0x2 +#define PM_CONFIG__Enable_BAPM__SHIFT 0x1 +#define PM_CONFIG__Enable_TDC_Limit_MASK 0x4 +#define PM_CONFIG__Enable_TDC_Limit__SHIFT 0x2 +#define PM_CONFIG__Enable_LPMx_MASK 0x8 +#define PM_CONFIG__Enable_LPMx__SHIFT 0x3 +#define PM_CONFIG__Enable_HTC_Limit_MASK 0x10 +#define PM_CONFIG__Enable_HTC_Limit__SHIFT 0x4 +#define PM_CONFIG__Enable_NBDPM_MASK 0x20 +#define PM_CONFIG__Enable_NBDPM__SHIFT 0x5 +#define PM_CONFIG__Enable_LoadLine_MASK 0x40 +#define PM_CONFIG__Enable_LoadLine__SHIFT 0x6 +#define PM_CONFIG__Reserved_MASK 0xff80 +#define PM_CONFIG__Reserved__SHIFT 0x7 +#define PM_CONFIG__Override_VPC_Current_MASK 0x10000 +#define PM_CONFIG__Override_VPC_Current__SHIFT 0x10 +#define PM_CONFIG__Reserved1_MASK 0x60000 +#define PM_CONFIG__Reserved1__SHIFT 0x11 +#define PM_CONFIG__Override_Calc_Temp_MASK 0x80000 +#define PM_CONFIG__Override_Calc_Temp__SHIFT 0x13 +#define PM_CONFIG__Enable_Hybrid_Boost_MASK 0x100000 +#define PM_CONFIG__Enable_Hybrid_Boost__SHIFT 0x14 +#define PM_CONFIG__Reserved2_MASK 0xe00000 +#define PM_CONFIG__Reserved2__SHIFT 0x15 +#define PM_CONFIG__PSTATE_AllCpusIdle_MASK 0x7000000 +#define PM_CONFIG__PSTATE_AllCpusIdle__SHIFT 0x18 +#define PM_CONFIG__NBPSTATE_AllCpusIdle_MASK 0x8000000 +#define PM_CONFIG__NBPSTATE_AllCpusIdle__SHIFT 0x1b +#define PM_CONFIG__Reserved3_MASK 0x10000000 +#define PM_CONFIG__Reserved3__SHIFT 0x1c +#define PM_CONFIG__SVI_Mode_MASK 0x20000000 +#define PM_CONFIG__SVI_Mode__SHIFT 0x1d +#define PM_CONFIG__Enable_PDM_MASK 0x40000000 +#define PM_CONFIG__Enable_PDM__SHIFT 0x1e +#define PM_CONFIG__Enable_PKG_PWR_LIMIT_MASK 0x80000000 +#define PM_CONFIG__Enable_PKG_PWR_LIMIT__SHIFT 0x1f +#define TE0_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f +#define TE0_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0 +#define TE0_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0 +#define TE0_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6 +#define TE0_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00 +#define TE0_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa +#define TE1_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f +#define TE1_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0 +#define TE1_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0 +#define TE1_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6 +#define TE1_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00 +#define TE1_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa +#define TE2_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f +#define TE2_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0 +#define TE2_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0 +#define TE2_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6 +#define TE2_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00 +#define TE2_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa +#define NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK 0xff +#define NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT 0x0 +#define NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK 0xff00 +#define NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT 0x8 +#define NB_DPM_CONFIG_1__DpmXNbPsLo_MASK 0xff0000 +#define NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT 0x10 +#define NB_DPM_CONFIG_1__DpmXNbPsHi_MASK 0xff000000 +#define NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT 0x18 +#define NB_DPM_CONFIG_2__Hysteresis_MASK 0xff +#define NB_DPM_CONFIG_2__Hysteresis__SHIFT 0x0 +#define NB_DPM_CONFIG_2__SkipPG_MASK 0xff00 +#define NB_DPM_CONFIG_2__SkipPG__SHIFT 0x8 +#define NB_DPM_CONFIG_2__SkipDPM0_MASK 0xff0000 +#define NB_DPM_CONFIG_2__SkipDPM0__SHIFT 0x10 +#define NB_DPM_CONFIG_2__EnablePSI1_MASK 0xff000000 +#define NB_DPM_CONFIG_2__EnablePSI1__SHIFT 0x18 +#define NB_DPM_CONFIG_3__RESERVED_MASK 0xffffff +#define NB_DPM_CONFIG_3__RESERVED__SHIFT 0x0 +#define NB_DPM_CONFIG_3__EnableDpmPstatePoll_MASK 0xff000000 +#define NB_DPM_CONFIG_3__EnableDpmPstatePoll__SHIFT 0x18 +#define SMU_IDD_OVERRIDE__IDD_MASK 0xffff +#define SMU_IDD_OVERRIDE__IDD__SHIFT 0x0 +#define SMU_IDD_OVERRIDE__IDDNB_MASK 0xffff0000 +#define SMU_IDD_OVERRIDE__IDDNB__SHIFT 0x10 +#define AVS_CONFIG__AvsEnabledForPstates_MASK 0xff +#define AVS_CONFIG__AvsEnabledForPstates__SHIFT 0x0 +#define AVS_CONFIG__AvsOverrideEnabled_MASK 0x100 +#define AVS_CONFIG__AvsOverrideEnabled__SHIFT 0x8 +#define AVS_CONFIG__AvsPsmTempCompensation_MASK 0x200 +#define AVS_CONFIG__AvsPsmTempCompensation__SHIFT 0x9 +#define AVS_CONFIG__RESERVED1_MASK 0xfc00 +#define AVS_CONFIG__RESERVED1__SHIFT 0xa +#define AVS_CONFIG__AvsOverrideOffset_MASK 0xff0000 +#define AVS_CONFIG__AvsOverrideOffset__SHIFT 0x10 +#define AVS_CONFIG__RESERVED_MASK 0xff000000 +#define AVS_CONFIG__RESERVED__SHIFT 0x18 +#define TDC_VRM_LIMIT__IDD_MASK 0xffff +#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 +#define TDC_VRM_LIMIT__IDDNB_MASK 0xffff0000 +#define TDC_VRM_LIMIT__IDDNB__SHIFT 0x10 +#define CU0_PSM_CONFIG__Psm4_MASK 0xff +#define CU0_PSM_CONFIG__Psm4__SHIFT 0x0 +#define CU0_PSM_CONFIG__Psm3_MASK 0xff00 +#define CU0_PSM_CONFIG__Psm3__SHIFT 0x8 +#define CU0_PSM_CONFIG__Psm2_MASK 0xff0000 +#define CU0_PSM_CONFIG__Psm2__SHIFT 0x10 +#define CU0_PSM_CONFIG__Psm1_MASK 0xff000000 +#define CU0_PSM_CONFIG__Psm1__SHIFT 0x18 +#define CU1_PSM_CONFIG__Psm4_MASK 0xff +#define CU1_PSM_CONFIG__Psm4__SHIFT 0x0 +#define CU1_PSM_CONFIG__Psm3_MASK 0xff00 +#define CU1_PSM_CONFIG__Psm3__SHIFT 0x8 +#define CU1_PSM_CONFIG__Psm2_MASK 0xff0000 +#define CU1_PSM_CONFIG__Psm2__SHIFT 0x10 +#define CU1_PSM_CONFIG__Psm1_MASK 0xff000000 +#define CU1_PSM_CONFIG__Psm1__SHIFT 0x18 +#define SPMI_CONFIG__SpmiTestCode_MASK 0xff +#define SPMI_CONFIG__SpmiTestCode__SHIFT 0x0 +#define SPMI_CONFIG__SpmiTestData_MASK 0xff00 +#define SPMI_CONFIG__SpmiTestData__SHIFT 0x8 +#define SPMI_CONFIG__RESERVED_MASK 0xffff0000 +#define SPMI_CONFIG__RESERVED__SHIFT 0x10 +#define SPMI_SMC_CHAIN_ADDR__Addr_MASK 0xffffffff +#define SPMI_SMC_CHAIN_ADDR__Addr__SHIFT 0x0 +#define SPMI_STATUS__OpDone_MASK 0xff +#define SPMI_STATUS__OpDone__SHIFT 0x0 +#define SPMI_STATUS__OpFailed_MASK 0xff00 +#define SPMI_STATUS__OpFailed__SHIFT 0x8 +#define AVSNB_CONFIG__AvsEnabledForPstates_MASK 0xf +#define AVSNB_CONFIG__AvsEnabledForPstates__SHIFT 0x0 +#define AVSNB_CONFIG__RESERVED0_MASK 0xf0 +#define AVSNB_CONFIG__RESERVED0__SHIFT 0x4 +#define AVSNB_CONFIG__AvsOverrideEnabled_MASK 0x100 +#define AVSNB_CONFIG__AvsOverrideEnabled__SHIFT 0x8 +#define AVSNB_CONFIG__AvsPsmTempCompensation_MASK 0x200 +#define AVSNB_CONFIG__AvsPsmTempCompensation__SHIFT 0x9 +#define AVSNB_CONFIG__RESERVED1_MASK 0xfc00 +#define AVSNB_CONFIG__RESERVED1__SHIFT 0xa +#define AVSNB_CONFIG__AvsOverrideOffset_MASK 0xff0000 +#define AVSNB_CONFIG__AvsOverrideOffset__SHIFT 0x10 +#define AVSNB_CONFIG__RESERVED_MASK 0xff000000 +#define AVSNB_CONFIG__RESERVED__SHIFT 0x18 +#define HTC_CONFIG__CSR_ADDR_MASK 0x3f +#define HTC_CONFIG__CSR_ADDR__SHIFT 0x0 +#define HTC_CONFIG__TCEN_ID_MASK 0x3c0 +#define HTC_CONFIG__TCEN_ID__SHIFT 0x6 +#define HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT_MASK 0xff0000 +#define HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT__SHIFT 0x10 +#define HTC_CONFIG__Reserved_MASK 0xff000000 +#define HTC_CONFIG__Reserved__SHIFT 0x18 +#define AVS_CU0_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f +#define AVS_CU0_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0 +#define AVS_CU0_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0 +#define AVS_CU0_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6 +#define AVS_CU0_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00 +#define AVS_CU0_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa +#define AVS_CU1_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f +#define AVS_CU1_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0 +#define AVS_CU1_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0 +#define AVS_CU1_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6 +#define AVS_CU1_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00 +#define AVS_CU1_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa +#define AVS_GNB_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f +#define AVS_GNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0 +#define AVS_GNB_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0 +#define AVS_GNB_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6 +#define AVS_GNB_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00 +#define AVS_GNB_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa +#define AVS_UNB_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f +#define AVS_UNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0 +#define AVS_UNB_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0 +#define AVS_UNB_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6 +#define AVS_UNB_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00 +#define AVS_UNB_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa +#define SMU_MONITOR_PORT80_MMIO_ADDR__MMIO_ADDRESS_MASK 0xffffffff +#define SMU_MONITOR_PORT80_MMIO_ADDR__MMIO_ADDRESS__SHIFT 0x0 +#define SMU_MONITOR_PORT80_MEMBASE_HI__MEMORY_BASE_HI_MASK 0xffffffff +#define SMU_MONITOR_PORT80_MEMBASE_HI__MEMORY_BASE_HI__SHIFT 0x0 +#define SMU_MONITOR_PORT80_MEMBASE_LO__MEMORY_BASE_LO_MASK 0xffffffff +#define SMU_MONITOR_PORT80_MEMBASE_LO__MEMORY_BASE_LO__SHIFT 0x0 +#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_POSITION_MASK 0xffff +#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_POSITION__SHIFT 0x0 +#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_BUFFER_SIZE_MASK 0xffff0000 +#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_BUFFER_SIZE__SHIFT 0x10 +#define SMU_MONITOR_PORT80_CTRL__ENABLE_DRAM_SHADOW_MASK 0x1 +#define SMU_MONITOR_PORT80_CTRL__ENABLE_DRAM_SHADOW__SHIFT 0x0 +#define SMU_MONITOR_PORT80_CTRL__ENABLE_CSR_SHADOW_MASK 0x2 +#define SMU_MONITOR_PORT80_CTRL__ENABLE_CSR_SHADOW__SHIFT 0x1 +#define SMU_MONITOR_PORT80_CTRL__RESERVED_MASK 0xfffc +#define SMU_MONITOR_PORT80_CTRL__RESERVED__SHIFT 0x2 +#define SMU_MONITOR_PORT80_CTRL__POLLING_INTERVAL_MASK 0xffff0000 +#define SMU_MONITOR_PORT80_CTRL__POLLING_INTERVAL__SHIFT 0x10 +#define SMU_TCEN_ALIVE__CORE_TCEN_ID_MASK 0xff +#define SMU_TCEN_ALIVE__CORE_TCEN_ID__SHIFT 0x0 +#define SMU_TCEN_ALIVE__GNB_TCEN_ID_MASK 0xff00 +#define SMU_TCEN_ALIVE__GNB_TCEN_ID__SHIFT 0x8 +#define SMU_TCEN_ALIVE__RESERVED_MASK 0xffff0000 +#define SMU_TCEN_ALIVE__RESERVED__SHIFT 0x10 +#define PDM_STATUS__PDM_ENABLED_MASK 0x1 +#define PDM_STATUS__PDM_ENABLED__SHIFT 0x0 +#define PDM_STATUS__NewCpcTdpLimit_MASK 0x1fffe +#define PDM_STATUS__NewCpcTdpLimit__SHIFT 0x1 +#define PDM_STATUS__NoofConnectedCores_MASK 0x1e0000 +#define PDM_STATUS__NoofConnectedCores__SHIFT 0x11 +#define PDM_STATUS__Reserved_MASK 0xffe00000 +#define PDM_STATUS__Reserved__SHIFT 0x15 +#define PDM_CNTL_1__BaseCoreTdpLimit0_MASK 0xff +#define PDM_CNTL_1__BaseCoreTdpLimit0__SHIFT 0x0 +#define PDM_CNTL_1__BaseCoreTdpLimit1_MASK 0xff00 +#define PDM_CNTL_1__BaseCoreTdpLimit1__SHIFT 0x8 +#define PDM_CNTL_1__BaseCoreTdpLimit2_MASK 0xff0000 +#define PDM_CNTL_1__BaseCoreTdpLimit2__SHIFT 0x10 +#define PDM_CNTL_1__GpuPdmMult_MASK 0xff000000 +#define PDM_CNTL_1__GpuPdmMult__SHIFT 0x18 +#define PDM_CNTL_2__HeatPdmTc_MASK 0xff +#define PDM_CNTL_2__HeatPdmTc__SHIFT 0x0 +#define PDM_CNTL_2__CoolPdmTc_MASK 0xff00 +#define PDM_CNTL_2__CoolPdmTc__SHIFT 0x8 +#define PDM_CNTL_2__GpuPdmTc_MASK 0xff0000 +#define PDM_CNTL_2__GpuPdmTc__SHIFT 0x10 +#define PDM_CNTL_2__GpuActThr_MASK 0xff000000 +#define PDM_CNTL_2__GpuActThr__SHIFT 0x18 +#define PDM_CNTL_3__HeatPdmThr1_MASK 0xff +#define PDM_CNTL_3__HeatPdmThr1__SHIFT 0x0 +#define PDM_CNTL_3__HeatPdmThr2_MASK 0xff00 +#define PDM_CNTL_3__HeatPdmThr2__SHIFT 0x8 +#define PDM_CNTL_3__CoolPdmThr1_MASK 0xff0000 +#define PDM_CNTL_3__CoolPdmThr1__SHIFT 0x10 +#define PDM_CNTL_3__CoolPdmThr2_MASK 0xff000000 +#define PDM_CNTL_3__CoolPdmThr2__SHIFT 0x18 +#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_52__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40 +#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17 +#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000 +#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf +#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 +#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 +#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 +#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 +#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 +#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf +#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 +#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS_MASK 0x1 +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS__SHIFT 0x0 +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK 0x1fe +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT 0x1 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1 +#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0 +#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe +#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0 +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 + +#endif /* SMU_7_0_0_SH_MASK_H */ -- cgit v1.2.3 From a4efaabae5aa7d3bd17b97fdd5084b31c7af84f5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:29:30 -0400 Subject: drm/amdgpu: add SMU 7.0.1 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h | 1314 +++++ .../amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h | 5456 ++++++++++++++++++++ 2 files changed, 6770 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h new file mode 100644 index 000000000000..f9fd2ea4625b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h @@ -0,0 +1,1314 @@ +/* + * SMU_7_0_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_0_1_D_H +#define SMU_7_0_1_D_H + +#define mmGCK_SMC_IND_INDEX 0x80 +#define mmGCK0_GCK_SMC_IND_INDEX 0x80 +#define mmGCK1_GCK_SMC_IND_INDEX 0x82 +#define mmGCK2_GCK_SMC_IND_INDEX 0x84 +#define mmGCK3_GCK_SMC_IND_INDEX 0x86 +#define mmGCK_SMC_IND_DATA 0x81 +#define mmGCK0_GCK_SMC_IND_DATA 0x81 +#define mmGCK1_GCK_SMC_IND_DATA 0x83 +#define mmGCK2_GCK_SMC_IND_DATA 0x85 +#define mmGCK3_GCK_SMC_IND_DATA 0x87 +#define ixCG_DCLK_CNTL 0xc050009c +#define ixCG_DCLK_STATUS 0xc05000a0 +#define ixCG_VCLK_CNTL 0xc05000a4 +#define ixCG_VCLK_STATUS 0xc05000a8 +#define ixCG_ECLK_CNTL 0xc05000ac +#define ixCG_ECLK_STATUS 0xc05000b0 +#define ixCG_ACLK_CNTL 0xc05000dc +#define ixGCK_DFS_BYPASS_CNTL 0xc0500118 +#define ixCG_SPLL_FUNC_CNTL 0xc0500140 +#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 +#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 +#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c +#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 +#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 +#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 +#define ixSPLL_CNTL_MODE 0xc0500160 +#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 +#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +#define ixMPLL_BYPASSCLK_SEL 0xc050019c +#define ixCG_CLKPIN_CNTL 0xc05001a0 +#define ixCG_CLKPIN_CNTL_2 0xc05001a4 +#define ixCG_CLKPIN_CNTL_DC 0xc0500204 +#define ixTHM_CLK_CNTL 0xc05001a8 +#define ixMISC_CLK_CTRL 0xc05001ac +#define ixGCK_PLL_TEST_CNTL 0xc05001c0 +#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 +#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 +#define mmSMC_IND_INDEX 0x80 +#define mmSMC0_SMC_IND_INDEX 0x80 +#define mmSMC1_SMC_IND_INDEX 0x82 +#define mmSMC2_SMC_IND_INDEX 0x84 +#define mmSMC3_SMC_IND_INDEX 0x86 +#define mmSMC_IND_DATA 0x81 +#define mmSMC0_SMC_IND_DATA 0x81 +#define mmSMC1_SMC_IND_DATA 0x83 +#define mmSMC2_SMC_IND_DATA 0x85 +#define mmSMC3_SMC_IND_DATA 0x87 +#define mmSMC_IND_INDEX_0 0x80 +#define mmSMC_IND_DATA_0 0x81 +#define mmSMC_IND_INDEX_1 0x82 +#define mmSMC_IND_DATA_1 0x83 +#define mmSMC_IND_INDEX_2 0x84 +#define mmSMC_IND_DATA_2 0x85 +#define mmSMC_IND_INDEX_3 0x86 +#define mmSMC_IND_DATA_3 0x87 +#define mmSMC_IND_INDEX_4 0x88 +#define mmSMC_IND_DATA_4 0x89 +#define mmSMC_IND_INDEX_5 0x8a +#define mmSMC_IND_DATA_5 0x8b +#define mmSMC_IND_INDEX_6 0x8c +#define mmSMC_IND_DATA_6 0x8d +#define mmSMC_IND_INDEX_7 0x8e +#define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_ACCESS_CNTL 0x90 +#define mmSMC_MESSAGE_0 0x94 +#define mmSMC_RESP_0 0x95 +#define mmSMC_MESSAGE_1 0x96 +#define mmSMC_RESP_1 0x97 +#define mmSMC_MESSAGE_2 0x98 +#define mmSMC_RESP_2 0x99 +#define mmSMC_MESSAGE_3 0x9a +#define mmSMC_RESP_3 0x9b +#define mmSMC_MESSAGE_4 0x9c +#define mmSMC_RESP_4 0x9d +#define mmSMC_MESSAGE_5 0x9e +#define mmSMC_RESP_5 0x9f +#define mmSMC_MESSAGE_6 0xa0 +#define mmSMC_RESP_6 0xa1 +#define mmSMC_MESSAGE_7 0xa2 +#define mmSMC_RESP_7 0xa3 +#define mmSMC_MSG_ARG_0 0xa4 +#define mmSMC_MSG_ARG_1 0xa5 +#define mmSMC_MSG_ARG_2 0xa6 +#define mmSMC_MSG_ARG_3 0xa7 +#define mmSMC_MSG_ARG_4 0xa8 +#define mmSMC_MSG_ARG_5 0xa9 +#define mmSMC_MSG_ARG_6 0xaa +#define mmSMC_MSG_ARG_7 0xab +#define mmSMC_MESSAGE_8 0xb5 +#define mmSMC_RESP_8 0xb6 +#define mmSMC_MESSAGE_9 0xb7 +#define mmSMC_RESP_9 0xb8 +#define mmSMC_MESSAGE_10 0xb9 +#define mmSMC_RESP_10 0xba +#define mmSMC_MESSAGE_11 0xbb +#define mmSMC_RESP_11 0xbc +#define mmSMC_MSG_ARG_8 0xbd +#define mmSMC_MSG_ARG_9 0xbe +#define mmSMC_MSG_ARG_10 0xbf +#define mmSMC_MSG_ARG_11 0x91 +#define ixSMC_SYSCON_RESET_CNTL 0x80000000 +#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 +#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 +#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c +#define ixSMC_SYSCON_MISC_CNTL 0x80000010 +#define ixSMC_SYSCON_MSG_ARG_0 0x80000068 +#define ixSMC_PC_C 0x80000370 +#define ixSMC_SCRATCH9 0x80000424 +#define mmGPIOPAD_SW_INT_STAT 0x180 +#define mmGPIOPAD_STRENGTH 0x181 +#define mmGPIOPAD_MASK 0x182 +#define mmGPIOPAD_A 0x183 +#define mmGPIOPAD_EN 0x184 +#define mmGPIOPAD_Y 0x185 +#define mmGPIOPAD_PINSTRAPS 0x186 +#define mmGPIOPAD_INT_STAT_EN 0x187 +#define mmGPIOPAD_INT_STAT 0x188 +#define mmGPIOPAD_INT_STAT_AK 0x189 +#define mmGPIOPAD_INT_EN 0x18a +#define mmGPIOPAD_INT_TYPE 0x18b +#define mmGPIOPAD_INT_POLARITY 0x18c +#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d +#define mmGPIOPAD_RCVR_SEL 0x191 +#define mmGPIOPAD_PU_EN 0x192 +#define mmGPIOPAD_PD_EN 0x193 +#define mmCG_FPS_CNT 0x1a4 +#define mmSMU_SMC_IND_INDEX 0x80 +#define mmSMU0_SMU_SMC_IND_INDEX 0x80 +#define mmSMU1_SMU_SMC_IND_INDEX 0x82 +#define mmSMU2_SMU_SMC_IND_INDEX 0x84 +#define mmSMU3_SMU_SMC_IND_INDEX 0x86 +#define mmSMU_SMC_IND_DATA 0x81 +#define mmSMU0_SMU_SMC_IND_DATA 0x81 +#define mmSMU1_SMU_SMC_IND_DATA 0x83 +#define mmSMU2_SMU_SMC_IND_DATA 0x85 +#define mmSMU3_SMU_SMC_IND_DATA 0x87 +#define ixRCU_UC_EVENTS 0xc0000004 +#define ixRCU_MISC_CTRL 0xc0000010 +#define ixCC_RCU_FUSES 0xc00c0000 +#define ixCC_SMU_MISC_FUSES 0xc00c0004 +#define ixCC_SCLK_VID_FUSES 0xc00c0008 +#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c +#define ixCC_GIO_IOC_FUSES 0xc00c0010 +#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c +#define ixCC_TST_ID_STRAPS 0xc00c0020 +#define ixCC_FCTRL_FUSES 0xc00c0024 +#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 +#define ixSMU_STATUS 0xe0003088 +#define ixSMU_FIRMWARE 0xe00030a4 +#define ixSMU_INPUT_DATA 0xe00030b8 +#define ixSMU_EFUSE_0 0xc0100000 +#define ixDPM_TABLE_1 0x3f000 +#define ixDPM_TABLE_2 0x3f004 +#define ixDPM_TABLE_3 0x3f008 +#define ixDPM_TABLE_4 0x3f00c +#define ixDPM_TABLE_5 0x3f010 +#define ixDPM_TABLE_6 0x3f014 +#define ixDPM_TABLE_7 0x3f018 +#define ixDPM_TABLE_8 0x3f01c +#define ixDPM_TABLE_9 0x3f020 +#define ixDPM_TABLE_10 0x3f024 +#define ixDPM_TABLE_11 0x3f028 +#define ixDPM_TABLE_12 0x3f02c +#define ixDPM_TABLE_13 0x3f030 +#define ixDPM_TABLE_14 0x3f034 +#define ixDPM_TABLE_15 0x3f038 +#define ixDPM_TABLE_16 0x3f03c +#define ixDPM_TABLE_17 0x3f040 +#define ixDPM_TABLE_18 0x3f044 +#define ixDPM_TABLE_19 0x3f048 +#define ixDPM_TABLE_20 0x3f04c +#define ixDPM_TABLE_21 0x3f050 +#define ixDPM_TABLE_22 0x3f054 +#define ixDPM_TABLE_23 0x3f058 +#define ixDPM_TABLE_24 0x3f05c +#define ixDPM_TABLE_25 0x3f060 +#define ixDPM_TABLE_26 0x3f064 +#define ixDPM_TABLE_27 0x3f068 +#define ixDPM_TABLE_28 0x3f06c +#define ixDPM_TABLE_29 0x3f070 +#define ixDPM_TABLE_30 0x3f074 +#define ixDPM_TABLE_31 0x3f078 +#define ixDPM_TABLE_32 0x3f07c +#define ixDPM_TABLE_33 0x3f080 +#define ixDPM_TABLE_34 0x3f084 +#define ixDPM_TABLE_35 0x3f088 +#define ixDPM_TABLE_36 0x3f08c +#define ixDPM_TABLE_37 0x3f090 +#define ixDPM_TABLE_38 0x3f094 +#define ixDPM_TABLE_39 0x3f098 +#define ixDPM_TABLE_40 0x3f09c +#define ixDPM_TABLE_41 0x3f0a0 +#define ixDPM_TABLE_42 0x3f0a4 +#define ixDPM_TABLE_43 0x3f0a8 +#define ixDPM_TABLE_44 0x3f0ac +#define ixDPM_TABLE_45 0x3f0b0 +#define ixDPM_TABLE_46 0x3f0b4 +#define ixDPM_TABLE_47 0x3f0b8 +#define ixDPM_TABLE_48 0x3f0bc +#define ixDPM_TABLE_49 0x3f0c0 +#define ixDPM_TABLE_50 0x3f0c4 +#define ixDPM_TABLE_51 0x3f0c8 +#define ixDPM_TABLE_52 0x3f0cc +#define ixDPM_TABLE_53 0x3f0d0 +#define ixDPM_TABLE_54 0x3f0d4 +#define ixDPM_TABLE_55 0x3f0d8 +#define ixDPM_TABLE_56 0x3f0dc +#define ixDPM_TABLE_57 0x3f0e0 +#define ixDPM_TABLE_58 0x3f0e4 +#define ixDPM_TABLE_59 0x3f0e8 +#define ixDPM_TABLE_60 0x3f0ec +#define ixDPM_TABLE_61 0x3f0f0 +#define ixDPM_TABLE_62 0x3f0f4 +#define ixDPM_TABLE_63 0x3f0f8 +#define ixDPM_TABLE_64 0x3f0fc +#define ixDPM_TABLE_65 0x3f100 +#define ixDPM_TABLE_66 0x3f104 +#define ixDPM_TABLE_67 0x3f108 +#define ixDPM_TABLE_68 0x3f10c +#define ixDPM_TABLE_69 0x3f110 +#define ixDPM_TABLE_70 0x3f114 +#define ixDPM_TABLE_71 0x3f118 +#define ixDPM_TABLE_72 0x3f11c +#define ixDPM_TABLE_73 0x3f120 +#define ixDPM_TABLE_74 0x3f124 +#define ixDPM_TABLE_75 0x3f128 +#define ixDPM_TABLE_76 0x3f12c +#define ixDPM_TABLE_77 0x3f130 +#define ixDPM_TABLE_78 0x3f134 +#define ixDPM_TABLE_79 0x3f138 +#define ixDPM_TABLE_80 0x3f13c +#define ixDPM_TABLE_81 0x3f140 +#define ixDPM_TABLE_82 0x3f144 +#define ixDPM_TABLE_83 0x3f148 +#define ixDPM_TABLE_84 0x3f14c +#define ixDPM_TABLE_85 0x3f150 +#define ixDPM_TABLE_86 0x3f154 +#define ixDPM_TABLE_87 0x3f158 +#define ixDPM_TABLE_88 0x3f15c +#define ixDPM_TABLE_89 0x3f160 +#define ixDPM_TABLE_90 0x3f164 +#define ixDPM_TABLE_91 0x3f168 +#define ixDPM_TABLE_92 0x3f16c +#define ixDPM_TABLE_93 0x3f170 +#define ixDPM_TABLE_94 0x3f174 +#define ixDPM_TABLE_95 0x3f178 +#define ixDPM_TABLE_96 0x3f17c +#define ixDPM_TABLE_97 0x3f180 +#define ixDPM_TABLE_98 0x3f184 +#define ixDPM_TABLE_99 0x3f188 +#define ixDPM_TABLE_100 0x3f18c +#define ixDPM_TABLE_101 0x3f190 +#define ixDPM_TABLE_102 0x3f194 +#define ixDPM_TABLE_103 0x3f198 +#define ixDPM_TABLE_104 0x3f19c +#define ixDPM_TABLE_105 0x3f1a0 +#define ixDPM_TABLE_106 0x3f1a4 +#define ixDPM_TABLE_107 0x3f1a8 +#define ixDPM_TABLE_108 0x3f1ac +#define ixDPM_TABLE_109 0x3f1b0 +#define ixDPM_TABLE_110 0x3f1b4 +#define ixDPM_TABLE_111 0x3f1b8 +#define ixDPM_TABLE_112 0x3f1bc +#define ixDPM_TABLE_113 0x3f1c0 +#define ixDPM_TABLE_114 0x3f1c4 +#define ixDPM_TABLE_115 0x3f1c8 +#define ixDPM_TABLE_116 0x3f1cc +#define ixDPM_TABLE_117 0x3f1d0 +#define ixDPM_TABLE_118 0x3f1d4 +#define ixDPM_TABLE_119 0x3f1d8 +#define ixDPM_TABLE_120 0x3f1dc +#define ixDPM_TABLE_121 0x3f1e0 +#define ixDPM_TABLE_122 0x3f1e4 +#define ixDPM_TABLE_123 0x3f1e8 +#define ixDPM_TABLE_124 0x3f1ec +#define ixDPM_TABLE_125 0x3f1f0 +#define ixDPM_TABLE_126 0x3f1f4 +#define ixDPM_TABLE_127 0x3f1f8 +#define ixDPM_TABLE_128 0x3f1fc +#define ixDPM_TABLE_129 0x3f200 +#define ixDPM_TABLE_130 0x3f204 +#define ixDPM_TABLE_131 0x3f208 +#define ixDPM_TABLE_132 0x3f20c +#define ixDPM_TABLE_133 0x3f210 +#define ixDPM_TABLE_134 0x3f214 +#define ixDPM_TABLE_135 0x3f218 +#define ixDPM_TABLE_136 0x3f21c +#define ixDPM_TABLE_137 0x3f220 +#define ixDPM_TABLE_138 0x3f224 +#define ixDPM_TABLE_139 0x3f228 +#define ixDPM_TABLE_140 0x3f22c +#define ixDPM_TABLE_141 0x3f230 +#define ixDPM_TABLE_142 0x3f234 +#define ixDPM_TABLE_143 0x3f238 +#define ixDPM_TABLE_144 0x3f23c +#define ixDPM_TABLE_145 0x3f240 +#define ixDPM_TABLE_146 0x3f244 +#define ixDPM_TABLE_147 0x3f248 +#define ixDPM_TABLE_148 0x3f24c +#define ixDPM_TABLE_149 0x3f250 +#define ixDPM_TABLE_150 0x3f254 +#define ixDPM_TABLE_151 0x3f258 +#define ixDPM_TABLE_152 0x3f25c +#define ixDPM_TABLE_153 0x3f260 +#define ixDPM_TABLE_154 0x3f264 +#define ixDPM_TABLE_155 0x3f268 +#define ixDPM_TABLE_156 0x3f26c +#define ixDPM_TABLE_157 0x3f270 +#define ixDPM_TABLE_158 0x3f274 +#define ixDPM_TABLE_159 0x3f278 +#define ixDPM_TABLE_160 0x3f27c +#define ixDPM_TABLE_161 0x3f280 +#define ixDPM_TABLE_162 0x3f284 +#define ixDPM_TABLE_163 0x3f288 +#define ixDPM_TABLE_164 0x3f28c +#define ixDPM_TABLE_165 0x3f290 +#define ixDPM_TABLE_166 0x3f294 +#define ixDPM_TABLE_167 0x3f298 +#define ixDPM_TABLE_168 0x3f29c +#define ixDPM_TABLE_169 0x3f2a0 +#define ixDPM_TABLE_170 0x3f2a4 +#define ixDPM_TABLE_171 0x3f2a8 +#define ixDPM_TABLE_172 0x3f2ac +#define ixDPM_TABLE_173 0x3f2b0 +#define ixDPM_TABLE_174 0x3f2b4 +#define ixDPM_TABLE_175 0x3f2b8 +#define ixDPM_TABLE_176 0x3f2bc +#define ixDPM_TABLE_177 0x3f2c0 +#define ixDPM_TABLE_178 0x3f2c4 +#define ixDPM_TABLE_179 0x3f2c8 +#define ixDPM_TABLE_180 0x3f2cc +#define ixDPM_TABLE_181 0x3f2d0 +#define ixDPM_TABLE_182 0x3f2d4 +#define ixDPM_TABLE_183 0x3f2d8 +#define ixDPM_TABLE_184 0x3f2dc +#define ixDPM_TABLE_185 0x3f2e0 +#define ixDPM_TABLE_186 0x3f2e4 +#define ixDPM_TABLE_187 0x3f2e8 +#define ixDPM_TABLE_188 0x3f2ec +#define ixDPM_TABLE_189 0x3f2f0 +#define ixDPM_TABLE_190 0x3f2f4 +#define ixDPM_TABLE_191 0x3f2f8 +#define ixDPM_TABLE_192 0x3f2fc +#define ixDPM_TABLE_193 0x3f300 +#define ixDPM_TABLE_194 0x3f304 +#define ixDPM_TABLE_195 0x3f308 +#define ixDPM_TABLE_196 0x3f30c +#define ixDPM_TABLE_197 0x3f310 +#define ixDPM_TABLE_198 0x3f314 +#define ixDPM_TABLE_199 0x3f318 +#define ixDPM_TABLE_200 0x3f31c +#define ixDPM_TABLE_201 0x3f320 +#define ixDPM_TABLE_202 0x3f324 +#define ixDPM_TABLE_203 0x3f328 +#define ixDPM_TABLE_204 0x3f32c +#define ixDPM_TABLE_205 0x3f330 +#define ixDPM_TABLE_206 0x3f334 +#define ixDPM_TABLE_207 0x3f338 +#define ixDPM_TABLE_208 0x3f33c +#define ixDPM_TABLE_209 0x3f340 +#define ixDPM_TABLE_210 0x3f344 +#define ixDPM_TABLE_211 0x3f348 +#define ixDPM_TABLE_212 0x3f34c +#define ixDPM_TABLE_213 0x3f350 +#define ixDPM_TABLE_214 0x3f354 +#define ixDPM_TABLE_215 0x3f358 +#define ixDPM_TABLE_216 0x3f35c +#define ixDPM_TABLE_217 0x3f360 +#define ixDPM_TABLE_218 0x3f364 +#define ixDPM_TABLE_219 0x3f368 +#define ixDPM_TABLE_220 0x3f36c +#define ixDPM_TABLE_221 0x3f370 +#define ixDPM_TABLE_222 0x3f374 +#define ixDPM_TABLE_223 0x3f378 +#define ixDPM_TABLE_224 0x3f37c +#define ixDPM_TABLE_225 0x3f380 +#define ixDPM_TABLE_226 0x3f384 +#define ixDPM_TABLE_227 0x3f388 +#define ixDPM_TABLE_228 0x3f38c +#define ixDPM_TABLE_229 0x3f390 +#define ixDPM_TABLE_230 0x3f394 +#define ixDPM_TABLE_231 0x3f398 +#define ixDPM_TABLE_232 0x3f39c +#define ixDPM_TABLE_233 0x3f3a0 +#define ixDPM_TABLE_234 0x3f3a4 +#define ixDPM_TABLE_235 0x3f3a8 +#define ixDPM_TABLE_236 0x3f3ac +#define ixDPM_TABLE_237 0x3f3b0 +#define ixDPM_TABLE_238 0x3f3b4 +#define ixDPM_TABLE_239 0x3f3b8 +#define ixDPM_TABLE_240 0x3f3bc +#define ixDPM_TABLE_241 0x3f3c0 +#define ixDPM_TABLE_242 0x3f3c4 +#define ixDPM_TABLE_243 0x3f3c8 +#define ixDPM_TABLE_244 0x3f3cc +#define ixDPM_TABLE_245 0x3f3d0 +#define ixDPM_TABLE_246 0x3f3d4 +#define ixDPM_TABLE_247 0x3f3d8 +#define ixDPM_TABLE_248 0x3f3dc +#define ixDPM_TABLE_249 0x3f3e0 +#define ixDPM_TABLE_250 0x3f3e4 +#define ixDPM_TABLE_251 0x3f3e8 +#define ixDPM_TABLE_252 0x3f3ec +#define ixDPM_TABLE_253 0x3f3f0 +#define ixDPM_TABLE_254 0x3f3f4 +#define ixDPM_TABLE_255 0x3f3f8 +#define ixDPM_TABLE_256 0x3f3fc +#define ixDPM_TABLE_257 0x3f400 +#define ixDPM_TABLE_258 0x3f404 +#define ixDPM_TABLE_259 0x3f408 +#define ixDPM_TABLE_260 0x3f40c +#define ixDPM_TABLE_261 0x3f410 +#define ixDPM_TABLE_262 0x3f414 +#define ixDPM_TABLE_263 0x3f418 +#define ixDPM_TABLE_264 0x3f41c +#define ixDPM_TABLE_265 0x3f420 +#define ixDPM_TABLE_266 0x3f424 +#define ixDPM_TABLE_267 0x3f428 +#define ixDPM_TABLE_268 0x3f42c +#define ixDPM_TABLE_269 0x3f430 +#define ixDPM_TABLE_270 0x3f434 +#define ixDPM_TABLE_271 0x3f438 +#define ixDPM_TABLE_272 0x3f43c +#define ixDPM_TABLE_273 0x3f440 +#define ixDPM_TABLE_274 0x3f444 +#define ixDPM_TABLE_275 0x3f448 +#define ixDPM_TABLE_276 0x3f44c +#define ixDPM_TABLE_277 0x3f450 +#define ixDPM_TABLE_278 0x3f454 +#define ixDPM_TABLE_279 0x3f458 +#define ixDPM_TABLE_280 0x3f45c +#define ixDPM_TABLE_281 0x3f460 +#define ixDPM_TABLE_282 0x3f464 +#define ixDPM_TABLE_283 0x3f468 +#define ixDPM_TABLE_284 0x3f46c +#define ixDPM_TABLE_285 0x3f470 +#define ixDPM_TABLE_286 0x3f474 +#define ixDPM_TABLE_287 0x3f478 +#define ixDPM_TABLE_288 0x3f47c +#define ixDPM_TABLE_289 0x3f480 +#define ixDPM_TABLE_290 0x3f484 +#define ixDPM_TABLE_291 0x3f488 +#define ixDPM_TABLE_292 0x3f48c +#define ixDPM_TABLE_293 0x3f490 +#define ixDPM_TABLE_294 0x3f494 +#define ixDPM_TABLE_295 0x3f498 +#define ixDPM_TABLE_296 0x3f49c +#define ixDPM_TABLE_297 0x3f4a0 +#define ixDPM_TABLE_298 0x3f4a4 +#define ixDPM_TABLE_299 0x3f4a8 +#define ixDPM_TABLE_300 0x3f4ac +#define ixDPM_TABLE_301 0x3f4b0 +#define ixDPM_TABLE_302 0x3f4b4 +#define ixDPM_TABLE_303 0x3f4b8 +#define ixDPM_TABLE_304 0x3f4bc +#define ixDPM_TABLE_305 0x3f4c0 +#define ixDPM_TABLE_306 0x3f4c4 +#define ixDPM_TABLE_307 0x3f4c8 +#define ixDPM_TABLE_308 0x3f4cc +#define ixDPM_TABLE_309 0x3f4d0 +#define ixDPM_TABLE_310 0x3f4d4 +#define ixDPM_TABLE_311 0x3f4d8 +#define ixDPM_TABLE_312 0x3f4dc +#define ixDPM_TABLE_313 0x3f4e0 +#define ixDPM_TABLE_314 0x3f4e4 +#define ixDPM_TABLE_315 0x3f4e8 +#define ixDPM_TABLE_316 0x3f4ec +#define ixDPM_TABLE_317 0x3f4f0 +#define ixDPM_TABLE_318 0x3f4f4 +#define ixDPM_TABLE_319 0x3f4f8 +#define ixDPM_TABLE_320 0x3f4fc +#define ixDPM_TABLE_321 0x3f500 +#define ixDPM_TABLE_322 0x3f504 +#define ixDPM_TABLE_323 0x3f508 +#define ixDPM_TABLE_324 0x3f50c +#define ixDPM_TABLE_325 0x3f510 +#define ixDPM_TABLE_326 0x3f514 +#define ixDPM_TABLE_327 0x3f518 +#define ixDPM_TABLE_328 0x3f51c +#define ixDPM_TABLE_329 0x3f520 +#define ixDPM_TABLE_330 0x3f524 +#define ixDPM_TABLE_331 0x3f528 +#define ixDPM_TABLE_332 0x3f52c +#define ixDPM_TABLE_333 0x3f530 +#define ixDPM_TABLE_334 0x3f534 +#define ixDPM_TABLE_335 0x3f538 +#define ixDPM_TABLE_336 0x3f53c +#define ixDPM_TABLE_337 0x3f540 +#define ixDPM_TABLE_338 0x3f544 +#define ixDPM_TABLE_339 0x3f548 +#define ixDPM_TABLE_340 0x3f54c +#define ixDPM_TABLE_341 0x3f550 +#define ixDPM_TABLE_342 0x3f554 +#define ixDPM_TABLE_343 0x3f558 +#define ixDPM_TABLE_344 0x3f55c +#define ixDPM_TABLE_345 0x3f560 +#define ixDPM_TABLE_346 0x3f564 +#define ixDPM_TABLE_347 0x3f568 +#define ixDPM_TABLE_348 0x3f56c +#define ixDPM_TABLE_349 0x3f570 +#define ixDPM_TABLE_350 0x3f574 +#define ixDPM_TABLE_351 0x3f578 +#define ixDPM_TABLE_352 0x3f57c +#define ixDPM_TABLE_353 0x3f580 +#define ixDPM_TABLE_354 0x3f584 +#define ixDPM_TABLE_355 0x3f588 +#define ixDPM_TABLE_356 0x3f58c +#define ixDPM_TABLE_357 0x3f590 +#define ixDPM_TABLE_358 0x3f594 +#define ixDPM_TABLE_359 0x3f598 +#define ixDPM_TABLE_360 0x3f59c +#define ixDPM_TABLE_361 0x3f5a0 +#define ixDPM_TABLE_362 0x3f5a4 +#define ixDPM_TABLE_363 0x3f5a8 +#define ixDPM_TABLE_364 0x3f5ac +#define ixDPM_TABLE_365 0x3f5b0 +#define ixDPM_TABLE_366 0x3f5b4 +#define ixDPM_TABLE_367 0x3f5b8 +#define ixDPM_TABLE_368 0x3f5bc +#define ixDPM_TABLE_369 0x3f5c0 +#define ixDPM_TABLE_370 0x3f5c4 +#define ixDPM_TABLE_371 0x3f5c8 +#define ixDPM_TABLE_372 0x3f5cc +#define ixDPM_TABLE_373 0x3f5d0 +#define ixDPM_TABLE_374 0x3f5d4 +#define ixDPM_TABLE_375 0x3f5d8 +#define ixDPM_TABLE_376 0x3f5dc +#define ixDPM_TABLE_377 0x3f5e0 +#define ixDPM_TABLE_378 0x3f5e4 +#define ixDPM_TABLE_379 0x3f5e8 +#define ixDPM_TABLE_380 0x3f5ec +#define ixDPM_TABLE_381 0x3f5f0 +#define ixDPM_TABLE_382 0x3f5f4 +#define ixDPM_TABLE_383 0x3f5f8 +#define ixDPM_TABLE_384 0x3f5fc +#define ixDPM_TABLE_385 0x3f600 +#define ixDPM_TABLE_386 0x3f604 +#define ixDPM_TABLE_387 0x3f608 +#define ixDPM_TABLE_388 0x3f60c +#define ixDPM_TABLE_389 0x3f610 +#define ixDPM_TABLE_390 0x3f614 +#define ixDPM_TABLE_391 0x3f618 +#define ixDPM_TABLE_392 0x3f61c +#define ixDPM_TABLE_393 0x3f620 +#define ixDPM_TABLE_394 0x3f624 +#define ixDPM_TABLE_395 0x3f628 +#define ixDPM_TABLE_396 0x3f62c +#define ixDPM_TABLE_397 0x3f630 +#define ixDPM_TABLE_398 0x3f634 +#define ixDPM_TABLE_399 0x3f638 +#define ixDPM_TABLE_400 0x3f63c +#define ixDPM_TABLE_401 0x3f640 +#define ixDPM_TABLE_402 0x3f644 +#define ixDPM_TABLE_403 0x3f648 +#define ixDPM_TABLE_404 0x3f64c +#define ixDPM_TABLE_405 0x3f650 +#define ixDPM_TABLE_406 0x3f654 +#define ixDPM_TABLE_407 0x3f658 +#define ixDPM_TABLE_408 0x3f65c +#define ixDPM_TABLE_409 0x3f660 +#define ixDPM_TABLE_410 0x3f664 +#define ixDPM_TABLE_411 0x3f668 +#define ixDPM_TABLE_412 0x3f66c +#define ixDPM_TABLE_413 0x3f670 +#define ixDPM_TABLE_414 0x3f674 +#define ixDPM_TABLE_415 0x3f678 +#define ixDPM_TABLE_416 0x3f67c +#define ixDPM_TABLE_417 0x3f680 +#define ixDPM_TABLE_418 0x3f684 +#define ixDPM_TABLE_419 0x3f688 +#define ixDPM_TABLE_420 0x3f68c +#define ixDPM_TABLE_421 0x3f690 +#define ixDPM_TABLE_422 0x3f694 +#define ixDPM_TABLE_423 0x3f698 +#define ixDPM_TABLE_424 0x3f69c +#define ixDPM_TABLE_425 0x3f6a0 +#define ixDPM_TABLE_426 0x3f6a4 +#define ixDPM_TABLE_427 0x3f6a8 +#define ixDPM_TABLE_428 0x3f6ac +#define ixDPM_TABLE_429 0x3f6b0 +#define ixDPM_TABLE_430 0x3f6b4 +#define ixDPM_TABLE_431 0x3f6b8 +#define ixDPM_TABLE_432 0x3f6bc +#define ixDPM_TABLE_433 0x3f6c0 +#define ixDPM_TABLE_434 0x3f6c4 +#define ixDPM_TABLE_435 0x3f6c8 +#define ixDPM_TABLE_436 0x3f6cc +#define ixDPM_TABLE_437 0x3f6d0 +#define ixDPM_TABLE_438 0x3f6d4 +#define ixDPM_TABLE_439 0x3f6d8 +#define ixDPM_TABLE_440 0x3f6dc +#define ixDPM_TABLE_441 0x3f6e0 +#define ixDPM_TABLE_442 0x3f6e4 +#define ixDPM_TABLE_443 0x3f6e8 +#define ixDPM_TABLE_444 0x3f6ec +#define ixDPM_TABLE_445 0x3f6f0 +#define ixDPM_TABLE_446 0x3f6f4 +#define ixDPM_TABLE_447 0x3f6f8 +#define ixDPM_TABLE_448 0x3f6fc +#define ixDPM_TABLE_449 0x3f700 +#define ixDPM_TABLE_450 0x3f704 +#define ixDPM_TABLE_451 0x3f708 +#define ixDPM_TABLE_452 0x3f70c +#define ixDPM_TABLE_453 0x3f710 +#define ixDPM_TABLE_454 0x3f714 +#define ixDPM_TABLE_455 0x3f718 +#define ixDPM_TABLE_456 0x3f71c +#define ixDPM_TABLE_457 0x3f720 +#define ixDPM_TABLE_458 0x3f724 +#define ixDPM_TABLE_459 0x3f728 +#define ixDPM_TABLE_460 0x3f72c +#define ixDPM_TABLE_461 0x3f730 +#define ixDPM_TABLE_462 0x3f734 +#define ixDPM_TABLE_463 0x3f738 +#define ixDPM_TABLE_464 0x3f73c +#define ixDPM_TABLE_465 0x3f740 +#define ixDPM_TABLE_466 0x3f744 +#define ixDPM_TABLE_467 0x3f748 +#define ixDPM_TABLE_468 0x3f74c +#define ixDPM_TABLE_469 0x3f750 +#define ixDPM_TABLE_470 0x3f754 +#define ixDPM_TABLE_471 0x3f758 +#define ixDPM_TABLE_472 0x3f75c +#define ixDPM_TABLE_473 0x3f760 +#define ixDPM_TABLE_474 0x3f764 +#define ixDPM_TABLE_475 0x3f768 +#define ixDPM_TABLE_476 0x3f76c +#define ixDPM_TABLE_477 0x3f770 +#define ixDPM_TABLE_478 0x3f774 +#define ixDPM_TABLE_479 0x3f778 +#define ixDPM_TABLE_480 0x3f77c +#define ixDPM_TABLE_481 0x3f780 +#define ixDPM_TABLE_482 0x3f784 +#define ixDPM_TABLE_483 0x3f788 +#define ixDPM_TABLE_484 0x3f78c +#define ixDPM_TABLE_485 0x3f790 +#define ixDPM_TABLE_486 0x3f794 +#define ixDPM_TABLE_487 0x3f798 +#define ixDPM_TABLE_488 0x3f79c +#define ixDPM_TABLE_489 0x3f7a0 +#define ixDPM_TABLE_490 0x3f7a4 +#define ixDPM_TABLE_491 0x3f7a8 +#define ixDPM_TABLE_492 0x3f7ac +#define ixDPM_TABLE_493 0x3f7b0 +#define ixDPM_TABLE_494 0x3f7b4 +#define ixDPM_TABLE_495 0x3f7b8 +#define ixDPM_TABLE_496 0x3f7bc +#define ixDPM_TABLE_497 0x3f7c0 +#define ixDPM_TABLE_498 0x3f7c4 +#define ixDPM_TABLE_499 0x3f7c8 +#define ixDPM_TABLE_500 0x3f7cc +#define ixDPM_TABLE_501 0x3f7d0 +#define ixDPM_TABLE_502 0x3f7d4 +#define ixDPM_TABLE_503 0x3f7d8 +#define ixDPM_TABLE_504 0x3f7dc +#define ixDPM_TABLE_505 0x3f7e0 +#define ixDPM_TABLE_506 0x3f7e4 +#define ixDPM_TABLE_507 0x3f7e8 +#define ixDPM_TABLE_508 0x3f7ec +#define ixDPM_TABLE_509 0x3f7f0 +#define ixDPM_TABLE_510 0x3f7f4 +#define ixFIRMWARE_FLAGS 0x3f800 +#define ixTDC_STATUS 0x3f808 +#define ixTDC_MV_AVERAGE 0x3f80c +#define ixTDC_VRM_LIMIT 0x3f810 +#define ixFEATURE_STATUS 0x3f818 +#define ixENTITY_TEMPERATURES_1 0x3f81c +#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f900 +#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f904 +#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f908 +#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f90c +#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f910 +#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f914 +#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f918 +#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f91c +#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f920 +#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f924 +#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f928 +#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f92c +#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f930 +#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f934 +#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f938 +#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f93c +#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f940 +#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f944 +#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f948 +#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f94c +#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f950 +#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f954 +#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f958 +#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f95c +#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f960 +#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f964 +#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f968 +#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f96c +#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f970 +#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f974 +#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f978 +#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f97c +#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f980 +#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f984 +#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f988 +#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f98c +#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f990 +#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f994 +#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f998 +#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f99c +#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f9a0 +#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f9a4 +#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f9a8 +#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f9ac +#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f9b0 +#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f9b4 +#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f9b8 +#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f9bc +#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f9c0 +#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f9c4 +#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f9c8 +#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f9cc +#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f9d0 +#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f9d4 +#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f9d8 +#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f9dc +#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f9e0 +#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f9e4 +#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f9e8 +#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f9ec +#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f9f0 +#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f9f4 +#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f9f8 +#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f9fc +#define ixMCARB_DRAM_TIMING_TABLE_65 0x3fa00 +#define ixMCARB_DRAM_TIMING_TABLE_66 0x3fa04 +#define ixMCARB_DRAM_TIMING_TABLE_67 0x3fa08 +#define ixMCARB_DRAM_TIMING_TABLE_68 0x3fa0c +#define ixMCARB_DRAM_TIMING_TABLE_69 0x3fa10 +#define ixMCARB_DRAM_TIMING_TABLE_70 0x3fa14 +#define ixMCARB_DRAM_TIMING_TABLE_71 0x3fa18 +#define ixMCARB_DRAM_TIMING_TABLE_72 0x3fa1c +#define ixMCARB_DRAM_TIMING_TABLE_73 0x3fa20 +#define ixMCARB_DRAM_TIMING_TABLE_74 0x3fa24 +#define ixMCARB_DRAM_TIMING_TABLE_75 0x3fa28 +#define ixMCARB_DRAM_TIMING_TABLE_76 0x3fa2c +#define ixMCARB_DRAM_TIMING_TABLE_77 0x3fa30 +#define ixMCARB_DRAM_TIMING_TABLE_78 0x3fa34 +#define ixMCARB_DRAM_TIMING_TABLE_79 0x3fa38 +#define ixMCARB_DRAM_TIMING_TABLE_80 0x3fa3c +#define ixMCARB_DRAM_TIMING_TABLE_81 0x3fa40 +#define ixMCARB_DRAM_TIMING_TABLE_82 0x3fa44 +#define ixMCARB_DRAM_TIMING_TABLE_83 0x3fa48 +#define ixMCARB_DRAM_TIMING_TABLE_84 0x3fa4c +#define ixMCARB_DRAM_TIMING_TABLE_85 0x3fa50 +#define ixMCARB_DRAM_TIMING_TABLE_86 0x3fa54 +#define ixMCARB_DRAM_TIMING_TABLE_87 0x3fa58 +#define ixMCARB_DRAM_TIMING_TABLE_88 0x3fa5c +#define ixMCARB_DRAM_TIMING_TABLE_89 0x3fa60 +#define ixMCARB_DRAM_TIMING_TABLE_90 0x3fa64 +#define ixMCARB_DRAM_TIMING_TABLE_91 0x3fa68 +#define ixMCARB_DRAM_TIMING_TABLE_92 0x3fa6c +#define ixMCARB_DRAM_TIMING_TABLE_93 0x3fa70 +#define ixMCARB_DRAM_TIMING_TABLE_94 0x3fa74 +#define ixMCARB_DRAM_TIMING_TABLE_95 0x3fa78 +#define ixMCARB_DRAM_TIMING_TABLE_96 0x3fa7c +#define ixMCARB_DRAM_TIMING_TABLE_97 0x3fa80 +#define ixMCARB_DRAM_TIMING_TABLE_98 0x3fa84 +#define ixMCARB_DRAM_TIMING_TABLE_99 0x3fa88 +#define ixMCARB_DRAM_TIMING_TABLE_100 0x3fa8c +#define ixMCARB_DRAM_TIMING_TABLE_101 0x3fa90 +#define ixMCARB_DRAM_TIMING_TABLE_102 0x3fa94 +#define ixMCARB_DRAM_TIMING_TABLE_103 0x3fa98 +#define ixMCARB_DRAM_TIMING_TABLE_104 0x3fa9c +#define ixMCARB_DRAM_TIMING_TABLE_105 0x3faa0 +#define ixMCARB_DRAM_TIMING_TABLE_106 0x3faa4 +#define ixMCARB_DRAM_TIMING_TABLE_107 0x3faa8 +#define ixMCARB_DRAM_TIMING_TABLE_108 0x3faac +#define ixMCARB_DRAM_TIMING_TABLE_109 0x3fab0 +#define ixMCARB_DRAM_TIMING_TABLE_110 0x3fab4 +#define ixMCARB_DRAM_TIMING_TABLE_111 0x3fab8 +#define ixMCARB_DRAM_TIMING_TABLE_112 0x3fabc +#define ixMCARB_DRAM_TIMING_TABLE_113 0x3fac0 +#define ixMCARB_DRAM_TIMING_TABLE_114 0x3fac4 +#define ixMCARB_DRAM_TIMING_TABLE_115 0x3fac8 +#define ixMCARB_DRAM_TIMING_TABLE_116 0x3facc +#define ixMCARB_DRAM_TIMING_TABLE_117 0x3fad0 +#define ixMCARB_DRAM_TIMING_TABLE_118 0x3fad4 +#define ixMCARB_DRAM_TIMING_TABLE_119 0x3fad8 +#define ixMCARB_DRAM_TIMING_TABLE_120 0x3fadc +#define ixMCARB_DRAM_TIMING_TABLE_121 0x3fae0 +#define ixMCARB_DRAM_TIMING_TABLE_122 0x3fae4 +#define ixMCARB_DRAM_TIMING_TABLE_123 0x3fae8 +#define ixMCARB_DRAM_TIMING_TABLE_124 0x3faec +#define ixMCARB_DRAM_TIMING_TABLE_125 0x3faf0 +#define ixMCARB_DRAM_TIMING_TABLE_126 0x3faf4 +#define ixMCARB_DRAM_TIMING_TABLE_127 0x3faf8 +#define ixMCARB_DRAM_TIMING_TABLE_128 0x3fafc +#define ixMCARB_DRAM_TIMING_TABLE_129 0x3fb00 +#define ixMCARB_DRAM_TIMING_TABLE_130 0x3fb04 +#define ixMCARB_DRAM_TIMING_TABLE_131 0x3fb08 +#define ixMCARB_DRAM_TIMING_TABLE_132 0x3fb0c +#define ixMCARB_DRAM_TIMING_TABLE_133 0x3fb10 +#define ixMCARB_DRAM_TIMING_TABLE_134 0x3fb14 +#define ixMCARB_DRAM_TIMING_TABLE_135 0x3fb18 +#define ixMCARB_DRAM_TIMING_TABLE_136 0x3fb1c +#define ixMCARB_DRAM_TIMING_TABLE_137 0x3fb20 +#define ixMCARB_DRAM_TIMING_TABLE_138 0x3fb24 +#define ixMCARB_DRAM_TIMING_TABLE_139 0x3fb28 +#define ixMCARB_DRAM_TIMING_TABLE_140 0x3fb2c +#define ixMCARB_DRAM_TIMING_TABLE_141 0x3fb30 +#define ixMCARB_DRAM_TIMING_TABLE_142 0x3fb34 +#define ixMCARB_DRAM_TIMING_TABLE_143 0x3fb38 +#define ixMCARB_DRAM_TIMING_TABLE_144 0x3fb3c +#define ixMC_REGISTERS_TABLE_1 0x3fb40 +#define ixMC_REGISTERS_TABLE_2 0x3fb44 +#define ixMC_REGISTERS_TABLE_3 0x3fb48 +#define ixMC_REGISTERS_TABLE_4 0x3fb4c +#define ixMC_REGISTERS_TABLE_5 0x3fb50 +#define ixMC_REGISTERS_TABLE_6 0x3fb54 +#define ixMC_REGISTERS_TABLE_7 0x3fb58 +#define ixMC_REGISTERS_TABLE_8 0x3fb5c +#define ixMC_REGISTERS_TABLE_9 0x3fb60 +#define ixMC_REGISTERS_TABLE_10 0x3fb64 +#define ixMC_REGISTERS_TABLE_11 0x3fb68 +#define ixMC_REGISTERS_TABLE_12 0x3fb6c +#define ixMC_REGISTERS_TABLE_13 0x3fb70 +#define ixMC_REGISTERS_TABLE_14 0x3fb74 +#define ixMC_REGISTERS_TABLE_15 0x3fb78 +#define ixMC_REGISTERS_TABLE_16 0x3fb7c +#define ixMC_REGISTERS_TABLE_17 0x3fb80 +#define ixMC_REGISTERS_TABLE_18 0x3fb84 +#define ixMC_REGISTERS_TABLE_19 0x3fb88 +#define ixMC_REGISTERS_TABLE_20 0x3fb8c +#define ixMC_REGISTERS_TABLE_21 0x3fb90 +#define ixMC_REGISTERS_TABLE_22 0x3fb94 +#define ixMC_REGISTERS_TABLE_23 0x3fb98 +#define ixMC_REGISTERS_TABLE_24 0x3fb9c +#define ixMC_REGISTERS_TABLE_25 0x3fba0 +#define ixMC_REGISTERS_TABLE_26 0x3fba4 +#define ixMC_REGISTERS_TABLE_27 0x3fba8 +#define ixMC_REGISTERS_TABLE_28 0x3fbac +#define ixMC_REGISTERS_TABLE_29 0x3fbb0 +#define ixMC_REGISTERS_TABLE_30 0x3fbb4 +#define ixMC_REGISTERS_TABLE_31 0x3fbb8 +#define ixMC_REGISTERS_TABLE_32 0x3fbbc +#define ixMC_REGISTERS_TABLE_33 0x3fbc0 +#define ixMC_REGISTERS_TABLE_34 0x3fbc4 +#define ixMC_REGISTERS_TABLE_35 0x3fbc8 +#define ixMC_REGISTERS_TABLE_36 0x3fbcc +#define ixMC_REGISTERS_TABLE_37 0x3fbd0 +#define ixMC_REGISTERS_TABLE_38 0x3fbd4 +#define ixMC_REGISTERS_TABLE_39 0x3fbd8 +#define ixMC_REGISTERS_TABLE_40 0x3fbdc +#define ixMC_REGISTERS_TABLE_41 0x3fbe0 +#define ixMC_REGISTERS_TABLE_42 0x3fbe4 +#define ixMC_REGISTERS_TABLE_43 0x3fbe8 +#define ixMC_REGISTERS_TABLE_44 0x3fbec +#define ixMC_REGISTERS_TABLE_45 0x3fbf0 +#define ixMC_REGISTERS_TABLE_46 0x3fbf4 +#define ixMC_REGISTERS_TABLE_47 0x3fbf8 +#define ixMC_REGISTERS_TABLE_48 0x3fbfc +#define ixMC_REGISTERS_TABLE_49 0x3fc00 +#define ixMC_REGISTERS_TABLE_50 0x3fc04 +#define ixMC_REGISTERS_TABLE_51 0x3fc08 +#define ixMC_REGISTERS_TABLE_52 0x3fc0c +#define ixMC_REGISTERS_TABLE_53 0x3fc10 +#define ixMC_REGISTERS_TABLE_54 0x3fc14 +#define ixMC_REGISTERS_TABLE_55 0x3fc18 +#define ixMC_REGISTERS_TABLE_56 0x3fc1c +#define ixMC_REGISTERS_TABLE_57 0x3fc20 +#define ixMC_REGISTERS_TABLE_58 0x3fc24 +#define ixMC_REGISTERS_TABLE_59 0x3fc28 +#define ixMC_REGISTERS_TABLE_60 0x3fc2c +#define ixMC_REGISTERS_TABLE_61 0x3fc30 +#define ixMC_REGISTERS_TABLE_62 0x3fc34 +#define ixMC_REGISTERS_TABLE_63 0x3fc38 +#define ixMC_REGISTERS_TABLE_64 0x3fc3c +#define ixMC_REGISTERS_TABLE_65 0x3fc40 +#define ixMC_REGISTERS_TABLE_66 0x3fc44 +#define ixMC_REGISTERS_TABLE_67 0x3fc48 +#define ixMC_REGISTERS_TABLE_68 0x3fc4c +#define ixMC_REGISTERS_TABLE_69 0x3fc50 +#define ixMC_REGISTERS_TABLE_70 0x3fc54 +#define ixMC_REGISTERS_TABLE_71 0x3fc58 +#define ixMC_REGISTERS_TABLE_72 0x3fc5c +#define ixMC_REGISTERS_TABLE_73 0x3fc60 +#define ixMC_REGISTERS_TABLE_74 0x3fc64 +#define ixMC_REGISTERS_TABLE_75 0x3fc68 +#define ixMC_REGISTERS_TABLE_76 0x3fc6c +#define ixMC_REGISTERS_TABLE_77 0x3fc70 +#define ixMC_REGISTERS_TABLE_78 0x3fc74 +#define ixMC_REGISTERS_TABLE_79 0x3fc78 +#define ixMC_REGISTERS_TABLE_80 0x3fc7c +#define ixMC_REGISTERS_TABLE_81 0x3fc80 +#define ixMC_REGISTERS_TABLE_82 0x3fc84 +#define ixMC_REGISTERS_TABLE_83 0x3fc88 +#define ixMC_REGISTERS_TABLE_84 0x3fc8c +#define ixMC_REGISTERS_TABLE_85 0x3fc90 +#define ixMC_REGISTERS_TABLE_86 0x3fc94 +#define ixMC_REGISTERS_TABLE_87 0x3fc98 +#define ixMC_REGISTERS_TABLE_88 0x3fc9c +#define ixMC_REGISTERS_TABLE_89 0x3fca0 +#define ixMC_REGISTERS_TABLE_90 0x3fca4 +#define ixMC_REGISTERS_TABLE_91 0x3fca8 +#define ixMC_REGISTERS_TABLE_92 0x3fcac +#define ixMC_REGISTERS_TABLE_93 0x3fcb0 +#define ixMC_REGISTERS_TABLE_94 0x3fcb4 +#define ixMC_REGISTERS_TABLE_95 0x3fcb8 +#define ixMC_REGISTERS_TABLE_96 0x3fcbc +#define ixMC_REGISTERS_TABLE_97 0x3fcc0 +#define ixMC_REGISTERS_TABLE_98 0x3fcc4 +#define ixMC_REGISTERS_TABLE_99 0x3fcc8 +#define ixMC_REGISTERS_TABLE_100 0x3fccc +#define ixMC_REGISTERS_TABLE_101 0x3fcd0 +#define ixMC_REGISTERS_TABLE_102 0x3fcd4 +#define ixMC_REGISTERS_TABLE_103 0x3fcd8 +#define ixMC_REGISTERS_TABLE_104 0x3fcdc +#define ixMC_REGISTERS_TABLE_105 0x3fce0 +#define ixMC_REGISTERS_TABLE_106 0x3fce4 +#define ixMC_REGISTERS_TABLE_107 0x3fce8 +#define ixMC_REGISTERS_TABLE_108 0x3fcec +#define ixMC_REGISTERS_TABLE_109 0x3fcf0 +#define ixMC_REGISTERS_TABLE_110 0x3fcf4 +#define ixMC_REGISTERS_TABLE_111 0x3fcf8 +#define ixMC_REGISTERS_TABLE_112 0x3fcfc +#define ixMC_REGISTERS_TABLE_113 0x3fd00 +#define ixFAN_TABLE_1 0x3fd04 +#define ixFAN_TABLE_2 0x3fd08 +#define ixFAN_TABLE_3 0x3fd0c +#define ixFAN_TABLE_4 0x3fd10 +#define ixFAN_TABLE_5 0x3fd14 +#define ixFAN_TABLE_6 0x3fd18 +#define ixFAN_TABLE_7 0x3fd1c +#define ixFAN_TABLE_8 0x3fd20 +#define ixFAN_TABLE_9 0x3fd24 +#define ixSOFT_REGISTERS_TABLE_1 0x3fd28 +#define ixSOFT_REGISTERS_TABLE_2 0x3fd2c +#define ixSOFT_REGISTERS_TABLE_3 0x3fd30 +#define ixSOFT_REGISTERS_TABLE_4 0x3fd34 +#define ixSOFT_REGISTERS_TABLE_5 0x3fd38 +#define ixSOFT_REGISTERS_TABLE_6 0x3fd3c +#define ixSOFT_REGISTERS_TABLE_7 0x3fd40 +#define ixSOFT_REGISTERS_TABLE_8 0x3fd44 +#define ixSOFT_REGISTERS_TABLE_9 0x3fd48 +#define ixSOFT_REGISTERS_TABLE_10 0x3fd4c +#define ixSOFT_REGISTERS_TABLE_11 0x3fd50 +#define ixSOFT_REGISTERS_TABLE_12 0x3fd54 +#define ixSOFT_REGISTERS_TABLE_13 0x3fd58 +#define ixSOFT_REGISTERS_TABLE_14 0x3fd5c +#define ixSOFT_REGISTERS_TABLE_15 0x3fd60 +#define ixSOFT_REGISTERS_TABLE_16 0x3fd64 +#define ixSOFT_REGISTERS_TABLE_17 0x3fd68 +#define ixSOFT_REGISTERS_TABLE_18 0x3fd6c +#define ixSOFT_REGISTERS_TABLE_19 0x3fd70 +#define ixSOFT_REGISTERS_TABLE_20 0x3fd74 +#define ixSOFT_REGISTERS_TABLE_21 0x3fd78 +#define ixSOFT_REGISTERS_TABLE_22 0x3fd7c +#define ixSOFT_REGISTERS_TABLE_23 0x3fd80 +#define ixSOFT_REGISTERS_TABLE_24 0x3fd84 +#define ixSOFT_REGISTERS_TABLE_25 0x3fd88 +#define ixSOFT_REGISTERS_TABLE_26 0x3fd8c +#define ixSOFT_REGISTERS_TABLE_27 0x3fd90 +#define ixSOFT_REGISTERS_TABLE_28 0x3fd94 +#define ixSOFT_REGISTERS_TABLE_29 0x3fd98 +#define ixSOFT_REGISTERS_TABLE_30 0x3fd9c +#define ixPM_FUSES_1 0x3fda0 +#define ixPM_FUSES_2 0x3fda4 +#define ixPM_FUSES_3 0x3fda8 +#define ixPM_FUSES_4 0x3fdac +#define ixPM_FUSES_5 0x3fdb0 +#define ixPM_FUSES_6 0x3fdb4 +#define ixPM_FUSES_7 0x3fdb8 +#define ixPM_FUSES_8 0x3fdbc +#define ixPM_FUSES_9 0x3fdc0 +#define ixPM_FUSES_10 0x3fdc4 +#define ixPM_FUSES_11 0x3fdc8 +#define ixPM_FUSES_12 0x3fdcc +#define ixPM_FUSES_13 0x3fdd0 +#define ixPM_FUSES_14 0x3fdd4 +#define ixPM_FUSES_15 0x3fdd8 +#define ixPM_FUSES_16 0x3fddc +#define ixPM_FUSES_17 0x3fde0 +#define ixPM_FUSES_18 0x3fde4 +#define ixPM_FUSES_19 0x3fde8 +#define ixSMU_PM_STATUS_0 0x3fe00 +#define ixSMU_PM_STATUS_1 0x3fe04 +#define ixSMU_PM_STATUS_2 0x3fe08 +#define ixSMU_PM_STATUS_3 0x3fe0c +#define ixSMU_PM_STATUS_4 0x3fe10 +#define ixSMU_PM_STATUS_5 0x3fe14 +#define ixSMU_PM_STATUS_6 0x3fe18 +#define ixSMU_PM_STATUS_7 0x3fe1c +#define ixSMU_PM_STATUS_8 0x3fe20 +#define ixSMU_PM_STATUS_9 0x3fe24 +#define ixSMU_PM_STATUS_10 0x3fe28 +#define ixSMU_PM_STATUS_11 0x3fe2c +#define ixSMU_PM_STATUS_12 0x3fe30 +#define ixSMU_PM_STATUS_13 0x3fe34 +#define ixSMU_PM_STATUS_14 0x3fe38 +#define ixSMU_PM_STATUS_15 0x3fe3c +#define ixSMU_PM_STATUS_16 0x3fe40 +#define ixSMU_PM_STATUS_17 0x3fe44 +#define ixSMU_PM_STATUS_18 0x3fe48 +#define ixSMU_PM_STATUS_19 0x3fe4c +#define ixSMU_PM_STATUS_20 0x3fe50 +#define ixSMU_PM_STATUS_21 0x3fe54 +#define ixSMU_PM_STATUS_22 0x3fe58 +#define ixSMU_PM_STATUS_23 0x3fe5c +#define ixSMU_PM_STATUS_24 0x3fe60 +#define ixSMU_PM_STATUS_25 0x3fe64 +#define ixSMU_PM_STATUS_26 0x3fe68 +#define ixSMU_PM_STATUS_27 0x3fe6c +#define ixSMU_PM_STATUS_28 0x3fe70 +#define ixSMU_PM_STATUS_29 0x3fe74 +#define ixSMU_PM_STATUS_30 0x3fe78 +#define ixSMU_PM_STATUS_31 0x3fe7c +#define ixSMU_PM_STATUS_32 0x3fe80 +#define ixSMU_PM_STATUS_33 0x3fe84 +#define ixSMU_PM_STATUS_34 0x3fe88 +#define ixSMU_PM_STATUS_35 0x3fe8c +#define ixSMU_PM_STATUS_36 0x3fe90 +#define ixSMU_PM_STATUS_37 0x3fe94 +#define ixSMU_PM_STATUS_38 0x3fe98 +#define ixSMU_PM_STATUS_39 0x3fe9c +#define ixSMU_PM_STATUS_40 0x3fea0 +#define ixSMU_PM_STATUS_41 0x3fea4 +#define ixSMU_PM_STATUS_42 0x3fea8 +#define ixSMU_PM_STATUS_43 0x3feac +#define ixSMU_PM_STATUS_44 0x3feb0 +#define ixSMU_PM_STATUS_45 0x3feb4 +#define ixSMU_PM_STATUS_46 0x3feb8 +#define ixSMU_PM_STATUS_47 0x3febc +#define ixSMU_PM_STATUS_48 0x3fec0 +#define ixSMU_PM_STATUS_49 0x3fec4 +#define ixSMU_PM_STATUS_50 0x3fec8 +#define ixSMU_PM_STATUS_51 0x3fecc +#define ixSMU_PM_STATUS_52 0x3fed0 +#define ixSMU_PM_STATUS_53 0x3fed4 +#define ixSMU_PM_STATUS_54 0x3fed8 +#define ixSMU_PM_STATUS_55 0x3fedc +#define ixSMU_PM_STATUS_56 0x3fee0 +#define ixSMU_PM_STATUS_57 0x3fee4 +#define ixSMU_PM_STATUS_58 0x3fee8 +#define ixSMU_PM_STATUS_59 0x3feec +#define ixSMU_PM_STATUS_60 0x3fef0 +#define ixSMU_PM_STATUS_61 0x3fef4 +#define ixSMU_PM_STATUS_62 0x3fef8 +#define ixSMU_PM_STATUS_63 0x3fefc +#define ixSMU_PM_STATUS_64 0x3ff00 +#define ixSMU_PM_STATUS_65 0x3ff04 +#define ixSMU_PM_STATUS_66 0x3ff08 +#define ixSMU_PM_STATUS_67 0x3ff0c +#define ixSMU_PM_STATUS_68 0x3ff10 +#define ixSMU_PM_STATUS_69 0x3ff14 +#define ixSMU_PM_STATUS_70 0x3ff18 +#define ixSMU_PM_STATUS_71 0x3ff1c +#define ixSMU_PM_STATUS_72 0x3ff20 +#define ixSMU_PM_STATUS_73 0x3ff24 +#define ixSMU_PM_STATUS_74 0x3ff28 +#define ixSMU_PM_STATUS_75 0x3ff2c +#define ixSMU_PM_STATUS_76 0x3ff30 +#define ixSMU_PM_STATUS_77 0x3ff34 +#define ixSMU_PM_STATUS_78 0x3ff38 +#define ixSMU_PM_STATUS_79 0x3ff3c +#define ixSMU_PM_STATUS_80 0x3ff40 +#define ixSMU_PM_STATUS_81 0x3ff44 +#define ixSMU_PM_STATUS_82 0x3ff48 +#define ixSMU_PM_STATUS_83 0x3ff4c +#define ixSMU_PM_STATUS_84 0x3ff50 +#define ixSMU_PM_STATUS_85 0x3ff54 +#define ixSMU_PM_STATUS_86 0x3ff58 +#define ixSMU_PM_STATUS_87 0x3ff5c +#define ixSMU_PM_STATUS_88 0x3ff60 +#define ixSMU_PM_STATUS_89 0x3ff64 +#define ixSMU_PM_STATUS_90 0x3ff68 +#define ixSMU_PM_STATUS_91 0x3ff6c +#define ixSMU_PM_STATUS_92 0x3ff70 +#define ixSMU_PM_STATUS_93 0x3ff74 +#define ixSMU_PM_STATUS_94 0x3ff78 +#define ixSMU_PM_STATUS_95 0x3ff7c +#define ixSMU_PM_STATUS_96 0x3ff80 +#define ixSMU_PM_STATUS_97 0x3ff84 +#define ixSMU_PM_STATUS_98 0x3ff88 +#define ixSMU_PM_STATUS_99 0x3ff8c +#define ixSMU_PM_STATUS_100 0x3ff90 +#define ixSMU_PM_STATUS_101 0x3ff94 +#define ixSMU_PM_STATUS_102 0x3ff98 +#define ixSMU_PM_STATUS_103 0x3ff9c +#define ixSMU_PM_STATUS_104 0x3ffa0 +#define ixSMU_PM_STATUS_105 0x3ffa4 +#define ixSMU_PM_STATUS_106 0x3ffa8 +#define ixSMU_PM_STATUS_107 0x3ffac +#define ixSMU_PM_STATUS_108 0x3ffb0 +#define ixSMU_PM_STATUS_109 0x3ffb4 +#define ixSMU_PM_STATUS_110 0x3ffb8 +#define ixSMU_PM_STATUS_111 0x3ffbc +#define ixSMU_PM_STATUS_112 0x3ffc0 +#define ixSMU_PM_STATUS_113 0x3ffc4 +#define ixSMU_PM_STATUS_114 0x3ffc8 +#define ixSMU_PM_STATUS_115 0x3ffcc +#define ixSMU_PM_STATUS_116 0x3ffd0 +#define ixSMU_PM_STATUS_117 0x3ffd4 +#define ixSMU_PM_STATUS_118 0x3ffd8 +#define ixSMU_PM_STATUS_119 0x3ffdc +#define ixSMU_PM_STATUS_120 0x3ffe0 +#define ixSMU_PM_STATUS_121 0x3ffe4 +#define ixSMU_PM_STATUS_122 0x3ffe8 +#define ixSMU_PM_STATUS_123 0x3ffec +#define ixSMU_PM_STATUS_124 0x3fff0 +#define ixSMU_PM_STATUS_125 0x3fff4 +#define ixSMU_PM_STATUS_126 0x3fff8 +#define ixSMU_PM_STATUS_127 0x3fffc +#define ixCG_THERMAL_INT_ENA 0xc2100024 +#define ixCG_THERMAL_INT_CTRL 0xc2100028 +#define ixCG_THERMAL_INT_STATUS 0xc210002c +#define ixCG_THERMAL_CTRL 0xc0300004 +#define ixCG_THERMAL_STATUS 0xc0300008 +#define ixCG_THERMAL_INT 0xc030000c +#define ixCG_MULT_THERMAL_CTRL 0xc0300010 +#define ixCG_MULT_THERMAL_STATUS 0xc0300014 +#define ixCG_FDO_CTRL0 0xc0300064 +#define ixCG_FDO_CTRL1 0xc0300068 +#define ixCG_FDO_CTRL2 0xc030006c +#define ixCG_TACH_CTRL 0xc0300070 +#define ixCG_TACH_STATUS 0xc0300074 +#define ixCC_THM_STRAPS0 0xc0300080 +#define ixTHM_TMON0_RDIL0_DATA 0xc0300100 +#define ixTHM_TMON0_RDIL1_DATA 0xc0300104 +#define ixTHM_TMON0_RDIL2_DATA 0xc0300108 +#define ixTHM_TMON0_RDIL3_DATA 0xc030010c +#define ixTHM_TMON0_RDIL4_DATA 0xc0300110 +#define ixTHM_TMON0_RDIL5_DATA 0xc0300114 +#define ixTHM_TMON0_RDIL6_DATA 0xc0300118 +#define ixTHM_TMON0_RDIL7_DATA 0xc030011c +#define ixTHM_TMON0_RDIL8_DATA 0xc0300120 +#define ixTHM_TMON0_RDIL9_DATA 0xc0300124 +#define ixTHM_TMON0_RDIL10_DATA 0xc0300128 +#define ixTHM_TMON0_RDIL11_DATA 0xc030012c +#define ixTHM_TMON0_RDIL12_DATA 0xc0300130 +#define ixTHM_TMON0_RDIL13_DATA 0xc0300134 +#define ixTHM_TMON0_RDIL14_DATA 0xc0300138 +#define ixTHM_TMON0_RDIL15_DATA 0xc030013c +#define ixTHM_TMON0_RDIR0_DATA 0xc0300140 +#define ixTHM_TMON0_RDIR1_DATA 0xc0300144 +#define ixTHM_TMON0_RDIR2_DATA 0xc0300148 +#define ixTHM_TMON0_RDIR3_DATA 0xc030014c +#define ixTHM_TMON0_RDIR4_DATA 0xc0300150 +#define ixTHM_TMON0_RDIR5_DATA 0xc0300154 +#define ixTHM_TMON0_RDIR6_DATA 0xc0300158 +#define ixTHM_TMON0_RDIR7_DATA 0xc030015c +#define ixTHM_TMON0_RDIR8_DATA 0xc0300160 +#define ixTHM_TMON0_RDIR9_DATA 0xc0300164 +#define ixTHM_TMON0_RDIR10_DATA 0xc0300168 +#define ixTHM_TMON0_RDIR11_DATA 0xc030016c +#define ixTHM_TMON0_RDIR12_DATA 0xc0300170 +#define ixTHM_TMON0_RDIR13_DATA 0xc0300174 +#define ixTHM_TMON0_RDIR14_DATA 0xc0300178 +#define ixTHM_TMON0_RDIR15_DATA 0xc030017c +#define ixTHM_TMON0_INT_DATA 0xc0300300 +#define ixTHM_TMON0_DEBUG 0xc0300310 +#define ixGENERAL_PWRMGT 0xc0200000 +#define ixCNB_PWRMGT_CNTL 0xc0200004 +#define ixSCLK_PWRMGT_CNTL 0xc0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 +#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 +#define ixPLL_TEST_CNTL 0xc020003c +#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 +#define ixCG_DISPLAY_GAP_CNTL 0xc0200060 +#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 +#define ixCG_ACPI_CNTL 0xc0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 +#define ixCG_ULV_PARAMETER 0xc020015c +#define ixSCLK_MIN_DIV 0xc0200308 +#define ixLCAC_SX0_CNTL 0xc0400d00 +#define ixLCAC_SX0_OVR_SEL 0xc0400d04 +#define ixLCAC_SX0_OVR_VAL 0xc0400d08 +#define ixLCAC_MC0_CNTL 0xc0400d30 +#define ixLCAC_MC0_OVR_SEL 0xc0400d34 +#define ixLCAC_MC0_OVR_VAL 0xc0400d38 +#define ixLCAC_MC1_CNTL 0xc0400d3c +#define ixLCAC_MC1_OVR_SEL 0xc0400d40 +#define ixLCAC_MC1_OVR_VAL 0xc0400d44 +#define ixLCAC_MC2_CNTL 0xc0400d48 +#define ixLCAC_MC2_OVR_SEL 0xc0400d4c +#define ixLCAC_MC2_OVR_VAL 0xc0400d50 +#define ixLCAC_MC3_CNTL 0xc0400d54 +#define ixLCAC_MC3_OVR_SEL 0xc0400d58 +#define ixLCAC_MC3_OVR_VAL 0xc0400d5c +#define ixLCAC_CPL_CNTL 0xc0400d80 +#define ixLCAC_CPL_OVR_SEL 0xc0400d84 +#define ixLCAC_CPL_OVR_VAL 0xc0400d88 +#define mmROM_SMC_IND_INDEX 0x80 +#define mmROM0_ROM_SMC_IND_INDEX 0x80 +#define mmROM1_ROM_SMC_IND_INDEX 0x82 +#define mmROM2_ROM_SMC_IND_INDEX 0x84 +#define mmROM3_ROM_SMC_IND_INDEX 0x86 +#define mmROM_SMC_IND_DATA 0x81 +#define mmROM0_ROM_SMC_IND_DATA 0x81 +#define mmROM1_ROM_SMC_IND_DATA 0x83 +#define mmROM2_ROM_SMC_IND_DATA 0x85 +#define mmROM3_ROM_SMC_IND_DATA 0x87 +#define ixROM_CNTL 0xc0600000 +#define ixPAGE_MIRROR_CNTL 0xc0600004 +#define ixROM_STATUS 0xc0600008 +#define ixCGTT_ROM_CLK_CTRL0 0xc060000c +#define ixROM_INDEX 0xc0600010 +#define ixROM_DATA 0xc0600014 +#define ixROM_START 0xc0600018 +#define ixROM_SW_CNTL 0xc060001c +#define ixROM_SW_STATUS 0xc0600020 +#define ixROM_SW_COMMAND 0xc0600024 +#define ixROM_SW_DATA_1 0xc0600028 +#define ixROM_SW_DATA_2 0xc060002c +#define ixROM_SW_DATA_3 0xc0600030 +#define ixROM_SW_DATA_4 0xc0600034 +#define ixROM_SW_DATA_5 0xc0600038 +#define ixROM_SW_DATA_6 0xc060003c +#define ixROM_SW_DATA_7 0xc0600040 +#define ixROM_SW_DATA_8 0xc0600044 +#define ixROM_SW_DATA_9 0xc0600048 +#define ixROM_SW_DATA_10 0xc060004c +#define ixROM_SW_DATA_11 0xc0600050 +#define ixROM_SW_DATA_12 0xc0600054 +#define ixROM_SW_DATA_13 0xc0600058 +#define ixROM_SW_DATA_14 0xc060005c +#define ixROM_SW_DATA_15 0xc0600060 +#define ixROM_SW_DATA_16 0xc0600064 +#define ixROM_SW_DATA_17 0xc0600068 +#define ixROM_SW_DATA_18 0xc060006c +#define ixROM_SW_DATA_19 0xc0600070 +#define ixROM_SW_DATA_20 0xc0600074 +#define ixROM_SW_DATA_21 0xc0600078 +#define ixROM_SW_DATA_22 0xc060007c +#define ixROM_SW_DATA_23 0xc0600080 +#define ixROM_SW_DATA_24 0xc0600084 +#define ixROM_SW_DATA_25 0xc0600088 +#define ixROM_SW_DATA_26 0xc060008c +#define ixROM_SW_DATA_27 0xc0600090 +#define ixROM_SW_DATA_28 0xc0600094 +#define ixROM_SW_DATA_29 0xc0600098 +#define ixROM_SW_DATA_30 0xc060009c +#define ixROM_SW_DATA_31 0xc06000a0 +#define ixROM_SW_DATA_32 0xc06000a4 +#define ixROM_SW_DATA_33 0xc06000a8 +#define ixROM_SW_DATA_34 0xc06000ac +#define ixROM_SW_DATA_35 0xc06000b0 +#define ixROM_SW_DATA_36 0xc06000b4 +#define ixROM_SW_DATA_37 0xc06000b8 +#define ixROM_SW_DATA_38 0xc06000bc +#define ixROM_SW_DATA_39 0xc06000c0 +#define ixROM_SW_DATA_40 0xc06000c4 +#define ixROM_SW_DATA_41 0xc06000c8 +#define ixROM_SW_DATA_42 0xc06000cc +#define ixROM_SW_DATA_43 0xc06000d0 +#define ixROM_SW_DATA_44 0xc06000d4 +#define ixROM_SW_DATA_45 0xc06000d8 +#define ixROM_SW_DATA_46 0xc06000dc +#define ixROM_SW_DATA_47 0xc06000e0 +#define ixROM_SW_DATA_48 0xc06000e4 +#define ixROM_SW_DATA_49 0xc06000e8 +#define ixROM_SW_DATA_50 0xc06000ec +#define ixROM_SW_DATA_51 0xc06000f0 +#define ixROM_SW_DATA_52 0xc06000f4 +#define ixROM_SW_DATA_53 0xc06000f8 +#define ixROM_SW_DATA_54 0xc06000fc +#define ixROM_SW_DATA_55 0xc0600110 +#define ixROM_SW_DATA_56 0xc0600114 +#define ixROM_SW_DATA_57 0xc0600118 +#define ixROM_SW_DATA_58 0xc060011c +#define ixROM_SW_DATA_59 0xc0600120 +#define ixROM_SW_DATA_60 0xc0600124 +#define ixROM_SW_DATA_61 0xc0600128 +#define ixROM_SW_DATA_62 0xc060012c +#define ixROM_SW_DATA_63 0xc0600130 +#define ixROM_SW_DATA_64 0xc0600134 + +#endif /* SMU_7_0_1_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h new file mode 100644 index 000000000000..25882a4dea5d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h @@ -0,0 +1,5456 @@ +/* + * SMU_7_0_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_0_1_SH_MASK_H +#define SMU_7_0_1_SH_MASK_H + +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f +#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 +#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f +#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 +#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f +#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 +#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f +#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d +#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 +#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 +#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 +#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 +#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 +#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 +#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1 +#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa +#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff +#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 +#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 +#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 +#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 +#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa +#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 +#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_0__SMC_RESP_MASK 0xffff +#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_1__SMC_RESP_MASK 0xffff +#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_2__SMC_RESP_MASK 0xffff +#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_3__SMC_RESP_MASK 0xffff +#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_4__SMC_RESP_MASK 0xffff +#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_5__SMC_RESP_MASK 0xffff +#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_6__SMC_RESP_MASK 0xffff +#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_7__SMC_RESP_MASK 0xffff +#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_8__SMC_RESP_MASK 0xffff +#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_9__SMC_RESP_MASK 0xffff +#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_10__SMC_RESP_MASK 0xffff +#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_11__SMC_RESP_MASK 0xffff +#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 +#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 +#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 +#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 +#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 +#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffff +#define SMC_PC_C__smc_pc_c__SHIFT 0x0 +#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff +#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4 +#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff +#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 +#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff +#define GPIOPAD_A__GPIO_A__SHIFT 0x0 +#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff +#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0 +#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff +#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f +#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff +#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000 +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f +#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6 +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0 +#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff +#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 +#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff +#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 +#define CG_FPS_CNT__FPS_CNT_MASK 0xff +#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 +#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 +#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3 +#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 +#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 +#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 +#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa +#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 +#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 +#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 +#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 +#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 +#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 +#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 +#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 +#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 +#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 +#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 +#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 +#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 +#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 +#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 +#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 +#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 +#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 +#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 +#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 +#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 +#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 +#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 +#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa +#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000 +#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000 +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000 +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11 +#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000 +#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14 +#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000 +#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17 +#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000 +#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18 +#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfe000000 +#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 +#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc +#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 +#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 +#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 +#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 +#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c +#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 +#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d +#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff +#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 +#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 +#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 +#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 +#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 +#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 +#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 +#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e +#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 +#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a +#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 +#define SMU_STATUS__SMU_DONE_MASK 0x1 +#define SMU_STATUS__SMU_DONE__SHIFT 0x0 +#define SMU_STATUS__SMU_PASS_MASK 0x2 +#define SMU_STATUS__SMU_PASS__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 +#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 +#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 +#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 +#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 +#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 +#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 +#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 +#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 +#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff +#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 +#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 +#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f +#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff +#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 +#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff +#define DPM_TABLE_28__SystemFlags__SHIFT 0x0 +#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff +#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0 +#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff +#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0 +#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff +#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0 +#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff +#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0 +#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff +#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0 +#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff +#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0 +#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff +#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff +#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff +#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff +#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff +#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000 +#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10 +#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff +#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0 +#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00 +#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000 +#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10 +#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff +#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0 +#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00 +#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000 +#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10 +#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff +#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0 +#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00 +#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000 +#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10 +#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff +#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0 +#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00 +#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff +#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff +#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff +#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff +#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff +#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff +#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff +#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff +#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_68__UvdLevelCount_MASK 0xff +#define DPM_TABLE_68__UvdLevelCount__SHIFT 0x0 +#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00 +#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8 +#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000 +#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10 +#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000 +#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18 +#define DPM_TABLE_69__padding2_MASK 0xff +#define DPM_TABLE_69__padding2__SHIFT 0x0 +#define DPM_TABLE_69__SamuLevelCount_MASK 0xff00 +#define DPM_TABLE_69__SamuLevelCount__SHIFT 0x8 +#define DPM_TABLE_69__AcpLevelCount_MASK 0xff0000 +#define DPM_TABLE_69__AcpLevelCount__SHIFT 0x10 +#define DPM_TABLE_69__VceLevelCount_MASK 0xff000000 +#define DPM_TABLE_69__VceLevelCount__SHIFT 0x18 +#define DPM_TABLE_70__Reserved_0_MASK 0xffffffff +#define DPM_TABLE_70__Reserved_0__SHIFT 0x0 +#define DPM_TABLE_71__Reserved_1_MASK 0xffffffff +#define DPM_TABLE_71__Reserved_1__SHIFT 0x0 +#define DPM_TABLE_72__Reserved_2_MASK 0xffffffff +#define DPM_TABLE_72__Reserved_2__SHIFT 0x0 +#define DPM_TABLE_73__Reserved_3_MASK 0xffffffff +#define DPM_TABLE_73__Reserved_3__SHIFT 0x0 +#define DPM_TABLE_74__Reserved_4_MASK 0xffffffff +#define DPM_TABLE_74__Reserved_4__SHIFT 0x0 +#define DPM_TABLE_75__GraphicsLevel_0_Flags_MASK 0xffffffff +#define DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT 0x0 +#define DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK 0xffff +#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_79__GraphicsLevel_0_padding1_1_MASK 0xff0000 +#define DPM_TABLE_79__GraphicsLevel_0_padding1_1__SHIFT 0x10 +#define DPM_TABLE_79__GraphicsLevel_0_padding1_0_MASK 0xff000000 +#define DPM_TABLE_79__GraphicsLevel_0_padding1_0__SHIFT 0x18 +#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK 0xff000000 +#define DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT 0x18 +#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK 0xff +#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_89__GraphicsLevel_1_Flags_MASK 0xffffffff +#define DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT 0x0 +#define DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK 0xffff +#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_93__GraphicsLevel_1_padding1_1_MASK 0xff0000 +#define DPM_TABLE_93__GraphicsLevel_1_padding1_1__SHIFT 0x10 +#define DPM_TABLE_93__GraphicsLevel_1_padding1_0_MASK 0xff000000 +#define DPM_TABLE_93__GraphicsLevel_1_padding1_0__SHIFT 0x18 +#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK 0xff000000 +#define DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT 0x18 +#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK 0xff +#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_103__GraphicsLevel_2_Flags_MASK 0xffffffff +#define DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT 0x0 +#define DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK 0xffff +#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_107__GraphicsLevel_2_padding1_1_MASK 0xff0000 +#define DPM_TABLE_107__GraphicsLevel_2_padding1_1__SHIFT 0x10 +#define DPM_TABLE_107__GraphicsLevel_2_padding1_0_MASK 0xff000000 +#define DPM_TABLE_107__GraphicsLevel_2_padding1_0__SHIFT 0x18 +#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK 0xff000000 +#define DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT 0x18 +#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK 0xff +#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_117__GraphicsLevel_3_Flags_MASK 0xffffffff +#define DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT 0x0 +#define DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK 0xffff +#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_3_padding1_1_MASK 0xff0000 +#define DPM_TABLE_121__GraphicsLevel_3_padding1_1__SHIFT 0x10 +#define DPM_TABLE_121__GraphicsLevel_3_padding1_0_MASK 0xff000000 +#define DPM_TABLE_121__GraphicsLevel_3_padding1_0__SHIFT 0x18 +#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK 0xff000000 +#define DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT 0x18 +#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK 0xff +#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_131__GraphicsLevel_4_Flags_MASK 0xffffffff +#define DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT 0x0 +#define DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK 0xffffffff +#define DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT 0x0 +#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK 0xffff +#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_4_padding1_1_MASK 0xff0000 +#define DPM_TABLE_135__GraphicsLevel_4_padding1_1__SHIFT 0x10 +#define DPM_TABLE_135__GraphicsLevel_4_padding1_0_MASK 0xff000000 +#define DPM_TABLE_135__GraphicsLevel_4_padding1_0__SHIFT 0x18 +#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK 0xff000000 +#define DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT 0x18 +#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK 0xff +#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_145__GraphicsLevel_5_Flags_MASK 0xffffffff +#define DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT 0x0 +#define DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK 0xffffffff +#define DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT 0x0 +#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK 0xffff +#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_5_padding1_1_MASK 0xff0000 +#define DPM_TABLE_149__GraphicsLevel_5_padding1_1__SHIFT 0x10 +#define DPM_TABLE_149__GraphicsLevel_5_padding1_0_MASK 0xff000000 +#define DPM_TABLE_149__GraphicsLevel_5_padding1_0__SHIFT 0x18 +#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK 0xff000000 +#define DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT 0x18 +#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK 0xff +#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_159__GraphicsLevel_6_Flags_MASK 0xffffffff +#define DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT 0x0 +#define DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK 0xffffffff +#define DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT 0x0 +#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_padding1_1_MASK 0xff0000 +#define DPM_TABLE_163__GraphicsLevel_6_padding1_1__SHIFT 0x10 +#define DPM_TABLE_163__GraphicsLevel_6_padding1_0_MASK 0xff000000 +#define DPM_TABLE_163__GraphicsLevel_6_padding1_0__SHIFT 0x18 +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18 +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18 +#define DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_173__GraphicsLevel_7_Flags_MASK 0xffffffff +#define DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT 0x0 +#define DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK 0xffffffff +#define DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT 0x0 +#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK 0xffff +#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_177__GraphicsLevel_7_padding1_1_MASK 0xff0000 +#define DPM_TABLE_177__GraphicsLevel_7_padding1_1__SHIFT 0x10 +#define DPM_TABLE_177__GraphicsLevel_7_padding1_0_MASK 0xff000000 +#define DPM_TABLE_177__GraphicsLevel_7_padding1_0__SHIFT 0x18 +#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK 0xff000000 +#define DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT 0x18 +#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK 0xff +#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK 0xff0000 +#define DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT 0x10 +#define DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK 0xff000000 +#define DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT 0x18 +#define DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK 0xffffffff +#define DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT 0x0 +#define DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK 0xff +#define DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK 0xff00 +#define DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT 0x8 +#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK 0xff +#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_194__MemoryACPILevel_padding_MASK 0xff +#define DPM_TABLE_194__MemoryACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK 0xff0000 +#define DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT 0x10 +#define DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK 0xff000000 +#define DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT 0x18 +#define DPM_TABLE_195__MemoryACPILevel_padding1_1_MASK 0xff +#define DPM_TABLE_195__MemoryACPILevel_padding1_1__SHIFT 0x0 +#define DPM_TABLE_195__MemoryACPILevel_padding1_0_MASK 0xff00 +#define DPM_TABLE_195__MemoryACPILevel_padding1_0__SHIFT 0x8 +#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK 0xffffffff +#define DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT 0x0 +#define DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK 0xffffffff +#define DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT 0x0 +#define DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK 0xff +#define DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK 0xff00 +#define DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT 0x8 +#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK 0xff +#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_212__MemoryLevel_0_padding_MASK 0xff +#define DPM_TABLE_212__MemoryLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_213__MemoryLevel_0_padding1_1_MASK 0xff +#define DPM_TABLE_213__MemoryLevel_0_padding1_1__SHIFT 0x0 +#define DPM_TABLE_213__MemoryLevel_0_padding1_0_MASK 0xff00 +#define DPM_TABLE_213__MemoryLevel_0_padding1_0__SHIFT 0x8 +#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK 0xffffffff +#define DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT 0x0 +#define DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK 0xffffffff +#define DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT 0x0 +#define DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK 0xff +#define DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK 0xff00 +#define DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT 0x8 +#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK 0xff +#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_230__MemoryLevel_1_padding_MASK 0xff +#define DPM_TABLE_230__MemoryLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_231__MemoryLevel_1_padding1_1_MASK 0xff +#define DPM_TABLE_231__MemoryLevel_1_padding1_1__SHIFT 0x0 +#define DPM_TABLE_231__MemoryLevel_1_padding1_0_MASK 0xff00 +#define DPM_TABLE_231__MemoryLevel_1_padding1_0__SHIFT 0x8 +#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK 0xffffffff +#define DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT 0x0 +#define DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK 0xffffffff +#define DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT 0x0 +#define DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK 0xff +#define DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK 0xff00 +#define DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT 0x8 +#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK 0xff +#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_248__MemoryLevel_2_padding_MASK 0xff +#define DPM_TABLE_248__MemoryLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_249__MemoryLevel_2_padding1_1_MASK 0xff +#define DPM_TABLE_249__MemoryLevel_2_padding1_1__SHIFT 0x0 +#define DPM_TABLE_249__MemoryLevel_2_padding1_0_MASK 0xff00 +#define DPM_TABLE_249__MemoryLevel_2_padding1_0__SHIFT 0x8 +#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK 0xffffffff +#define DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT 0x0 +#define DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK 0xffffffff +#define DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT 0x0 +#define DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK 0xff +#define DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK 0xff00 +#define DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT 0x8 +#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK 0xff +#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_266__MemoryLevel_3_padding_MASK 0xff +#define DPM_TABLE_266__MemoryLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_267__MemoryLevel_3_padding1_1_MASK 0xff +#define DPM_TABLE_267__MemoryLevel_3_padding1_1__SHIFT 0x0 +#define DPM_TABLE_267__MemoryLevel_3_padding1_0_MASK 0xff00 +#define DPM_TABLE_267__MemoryLevel_3_padding1_0__SHIFT 0x8 +#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK 0xffffffff +#define DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT 0x0 +#define DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK 0xffffffff +#define DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT 0x0 +#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK 0xffffffff +#define DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT 0x0 +#define DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK 0xff +#define DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK 0xff00 +#define DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT 0x8 +#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK 0xff +#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_284__MemoryLevel_4_padding_MASK 0xff +#define DPM_TABLE_284__MemoryLevel_4_padding__SHIFT 0x0 +#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_285__MemoryLevel_4_padding1_1_MASK 0xff +#define DPM_TABLE_285__MemoryLevel_4_padding1_1__SHIFT 0x0 +#define DPM_TABLE_285__MemoryLevel_4_padding1_0_MASK 0xff00 +#define DPM_TABLE_285__MemoryLevel_4_padding1_0__SHIFT 0x8 +#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK 0xffffffff +#define DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT 0x0 +#define DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK 0xffffffff +#define DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT 0x0 +#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK 0xffffffff +#define DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT 0x0 +#define DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK 0xff +#define DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK 0xff00 +#define DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT 0x8 +#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK 0xff +#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_302__MemoryLevel_5_padding_MASK 0xff +#define DPM_TABLE_302__MemoryLevel_5_padding__SHIFT 0x0 +#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_303__MemoryLevel_5_padding1_1_MASK 0xff +#define DPM_TABLE_303__MemoryLevel_5_padding1_1__SHIFT 0x0 +#define DPM_TABLE_303__MemoryLevel_5_padding1_0_MASK 0xff00 +#define DPM_TABLE_303__MemoryLevel_5_padding1_0__SHIFT 0x8 +#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK 0xffffffff +#define DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT 0x0 +#define DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_313__LinkLevel_0_Padding_MASK 0xff +#define DPM_TABLE_313__LinkLevel_0_Padding__SHIFT 0x0 +#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_316__LinkLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_317__LinkLevel_1_Padding_MASK 0xff +#define DPM_TABLE_317__LinkLevel_1_Padding__SHIFT 0x0 +#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_320__LinkLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_321__LinkLevel_2_Padding_MASK 0xff +#define DPM_TABLE_321__LinkLevel_2_Padding__SHIFT 0x0 +#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_324__LinkLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_325__LinkLevel_3_Padding_MASK 0xff +#define DPM_TABLE_325__LinkLevel_3_Padding__SHIFT 0x0 +#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_328__LinkLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_329__LinkLevel_4_Padding_MASK 0xff +#define DPM_TABLE_329__LinkLevel_4_Padding__SHIFT 0x0 +#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_332__LinkLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_333__LinkLevel_5_Padding_MASK 0xff +#define DPM_TABLE_333__LinkLevel_5_Padding__SHIFT 0x0 +#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_336__LinkLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_337__LinkLevel_6_Padding_MASK 0xff +#define DPM_TABLE_337__LinkLevel_6_Padding__SHIFT 0x0 +#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_340__LinkLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_341__LinkLevel_7_Padding_MASK 0xff +#define DPM_TABLE_341__LinkLevel_7_Padding__SHIFT 0x0 +#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_344__LinkLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_345__ACPILevel_Flags_MASK 0xffffffff +#define DPM_TABLE_345__ACPILevel_Flags__SHIFT 0x0 +#define DPM_TABLE_346__ACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_346__ACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_348__ACPILevel_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_349__ACPILevel_padding_MASK 0xff +#define DPM_TABLE_349__ACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_349__ACPILevel_SclkDid_MASK 0xff000000 +#define DPM_TABLE_349__ACPILevel_SclkDid__SHIFT 0x18 +#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff +#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0 +#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK 0xff +#define DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_360__UvdLevel_0_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT 0x10 +#define DPM_TABLE_361__UvdLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_361__UvdLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_361__UvdLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK 0xff +#define DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_364__UvdLevel_1_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT 0x10 +#define DPM_TABLE_365__UvdLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_365__UvdLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_365__UvdLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK 0xff +#define DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_368__UvdLevel_2_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT 0x10 +#define DPM_TABLE_369__UvdLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_369__UvdLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_369__UvdLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK 0xff +#define DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_372__UvdLevel_3_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT 0x10 +#define DPM_TABLE_373__UvdLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_373__UvdLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_373__UvdLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK 0xff +#define DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_376__UvdLevel_4_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT 0x10 +#define DPM_TABLE_377__UvdLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_377__UvdLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_377__UvdLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK 0xff +#define DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_380__UvdLevel_5_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT 0x10 +#define DPM_TABLE_381__UvdLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_381__UvdLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_381__UvdLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK 0xff +#define DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_384__UvdLevel_6_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT 0x10 +#define DPM_TABLE_385__UvdLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_385__UvdLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_385__UvdLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK 0xff +#define DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_388__UvdLevel_7_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT 0x10 +#define DPM_TABLE_389__UvdLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_389__UvdLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_389__UvdLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_390__VceLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_390__VceLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_391__VceLevel_0_Divider_MASK 0xff +#define DPM_TABLE_391__VceLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_391__VceLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_391__VceLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_392__VceLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_392__VceLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_393__VceLevel_1_Divider_MASK 0xff +#define DPM_TABLE_393__VceLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_393__VceLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_393__VceLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_394__VceLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_394__VceLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_395__VceLevel_2_Divider_MASK 0xff +#define DPM_TABLE_395__VceLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_395__VceLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_395__VceLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_396__VceLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_396__VceLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_397__VceLevel_3_Divider_MASK 0xff +#define DPM_TABLE_397__VceLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_397__VceLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_397__VceLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_398__VceLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_398__VceLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_399__VceLevel_4_Divider_MASK 0xff +#define DPM_TABLE_399__VceLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_399__VceLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_399__VceLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_400__VceLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_400__VceLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_401__VceLevel_5_Divider_MASK 0xff +#define DPM_TABLE_401__VceLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_401__VceLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_401__VceLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_402__VceLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_402__VceLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_403__VceLevel_6_Divider_MASK 0xff +#define DPM_TABLE_403__VceLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_403__VceLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_403__VceLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_404__VceLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_404__VceLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_405__VceLevel_7_Divider_MASK 0xff +#define DPM_TABLE_405__VceLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_405__VceLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_405__VceLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_406__AcpLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_407__AcpLevel_0_Divider_MASK 0xff +#define DPM_TABLE_407__AcpLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_407__AcpLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_408__AcpLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_409__AcpLevel_1_Divider_MASK 0xff +#define DPM_TABLE_409__AcpLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_409__AcpLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_410__AcpLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_411__AcpLevel_2_Divider_MASK 0xff +#define DPM_TABLE_411__AcpLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_411__AcpLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_412__AcpLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_413__AcpLevel_3_Divider_MASK 0xff +#define DPM_TABLE_413__AcpLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_413__AcpLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_414__AcpLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_415__AcpLevel_4_Divider_MASK 0xff +#define DPM_TABLE_415__AcpLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_415__AcpLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_416__AcpLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_417__AcpLevel_5_Divider_MASK 0xff +#define DPM_TABLE_417__AcpLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_417__AcpLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_418__AcpLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_419__AcpLevel_6_Divider_MASK 0xff +#define DPM_TABLE_419__AcpLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_419__AcpLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_420__AcpLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_421__AcpLevel_7_Divider_MASK 0xff +#define DPM_TABLE_421__AcpLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_421__AcpLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_422__SamuLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_423__SamuLevel_0_Divider_MASK 0xff +#define DPM_TABLE_423__SamuLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_423__SamuLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_424__SamuLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_425__SamuLevel_1_Divider_MASK 0xff +#define DPM_TABLE_425__SamuLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_425__SamuLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_426__SamuLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_427__SamuLevel_2_Divider_MASK 0xff +#define DPM_TABLE_427__SamuLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_427__SamuLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_428__SamuLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_429__SamuLevel_3_Divider_MASK 0xff +#define DPM_TABLE_429__SamuLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_429__SamuLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_430__SamuLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_431__SamuLevel_4_Divider_MASK 0xff +#define DPM_TABLE_431__SamuLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_431__SamuLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_432__SamuLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_433__SamuLevel_5_Divider_MASK 0xff +#define DPM_TABLE_433__SamuLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_433__SamuLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_434__SamuLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_435__SamuLevel_6_Divider_MASK 0xff +#define DPM_TABLE_435__SamuLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_435__SamuLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_436__SamuLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_437__SamuLevel_7_Divider_MASK 0xff +#define DPM_TABLE_437__SamuLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_437__SamuLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_438__Ulv_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_440__Ulv_VddcPhase_MASK 0xff +#define DPM_TABLE_440__Ulv_VddcPhase__SHIFT 0x0 +#define DPM_TABLE_440__Ulv_VddcOffsetVid_MASK 0xff00 +#define DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT 0x8 +#define DPM_TABLE_440__Ulv_VddcOffset_MASK 0xffff0000 +#define DPM_TABLE_440__Ulv_VddcOffset__SHIFT 0x10 +#define DPM_TABLE_441__Ulv_Reserved_MASK 0xffffffff +#define DPM_TABLE_441__Ulv_Reserved__SHIFT 0x0 +#define DPM_TABLE_442__SclkStepSize_MASK 0xffffffff +#define DPM_TABLE_442__SclkStepSize__SHIFT 0x0 +#define DPM_TABLE_443__Smio_0_MASK 0xffffffff +#define DPM_TABLE_443__Smio_0__SHIFT 0x0 +#define DPM_TABLE_444__Smio_1_MASK 0xffffffff +#define DPM_TABLE_444__Smio_1__SHIFT 0x0 +#define DPM_TABLE_445__Smio_2_MASK 0xffffffff +#define DPM_TABLE_445__Smio_2__SHIFT 0x0 +#define DPM_TABLE_446__Smio_3_MASK 0xffffffff +#define DPM_TABLE_446__Smio_3__SHIFT 0x0 +#define DPM_TABLE_447__Smio_4_MASK 0xffffffff +#define DPM_TABLE_447__Smio_4__SHIFT 0x0 +#define DPM_TABLE_448__Smio_5_MASK 0xffffffff +#define DPM_TABLE_448__Smio_5__SHIFT 0x0 +#define DPM_TABLE_449__Smio_6_MASK 0xffffffff +#define DPM_TABLE_449__Smio_6__SHIFT 0x0 +#define DPM_TABLE_450__Smio_7_MASK 0xffffffff +#define DPM_TABLE_450__Smio_7__SHIFT 0x0 +#define DPM_TABLE_451__Smio_8_MASK 0xffffffff +#define DPM_TABLE_451__Smio_8__SHIFT 0x0 +#define DPM_TABLE_452__Smio_9_MASK 0xffffffff +#define DPM_TABLE_452__Smio_9__SHIFT 0x0 +#define DPM_TABLE_453__Smio_10_MASK 0xffffffff +#define DPM_TABLE_453__Smio_10__SHIFT 0x0 +#define DPM_TABLE_454__Smio_11_MASK 0xffffffff +#define DPM_TABLE_454__Smio_11__SHIFT 0x0 +#define DPM_TABLE_455__Smio_12_MASK 0xffffffff +#define DPM_TABLE_455__Smio_12__SHIFT 0x0 +#define DPM_TABLE_456__Smio_13_MASK 0xffffffff +#define DPM_TABLE_456__Smio_13__SHIFT 0x0 +#define DPM_TABLE_457__Smio_14_MASK 0xffffffff +#define DPM_TABLE_457__Smio_14__SHIFT 0x0 +#define DPM_TABLE_458__Smio_15_MASK 0xffffffff +#define DPM_TABLE_458__Smio_15__SHIFT 0x0 +#define DPM_TABLE_459__Smio_16_MASK 0xffffffff +#define DPM_TABLE_459__Smio_16__SHIFT 0x0 +#define DPM_TABLE_460__Smio_17_MASK 0xffffffff +#define DPM_TABLE_460__Smio_17__SHIFT 0x0 +#define DPM_TABLE_461__Smio_18_MASK 0xffffffff +#define DPM_TABLE_461__Smio_18__SHIFT 0x0 +#define DPM_TABLE_462__Smio_19_MASK 0xffffffff +#define DPM_TABLE_462__Smio_19__SHIFT 0x0 +#define DPM_TABLE_463__Smio_20_MASK 0xffffffff +#define DPM_TABLE_463__Smio_20__SHIFT 0x0 +#define DPM_TABLE_464__Smio_21_MASK 0xffffffff +#define DPM_TABLE_464__Smio_21__SHIFT 0x0 +#define DPM_TABLE_465__Smio_22_MASK 0xffffffff +#define DPM_TABLE_465__Smio_22__SHIFT 0x0 +#define DPM_TABLE_466__Smio_23_MASK 0xffffffff +#define DPM_TABLE_466__Smio_23__SHIFT 0x0 +#define DPM_TABLE_467__Smio_24_MASK 0xffffffff +#define DPM_TABLE_467__Smio_24__SHIFT 0x0 +#define DPM_TABLE_468__Smio_25_MASK 0xffffffff +#define DPM_TABLE_468__Smio_25__SHIFT 0x0 +#define DPM_TABLE_469__Smio_26_MASK 0xffffffff +#define DPM_TABLE_469__Smio_26__SHIFT 0x0 +#define DPM_TABLE_470__Smio_27_MASK 0xffffffff +#define DPM_TABLE_470__Smio_27__SHIFT 0x0 +#define DPM_TABLE_471__Smio_28_MASK 0xffffffff +#define DPM_TABLE_471__Smio_28__SHIFT 0x0 +#define DPM_TABLE_472__Smio_29_MASK 0xffffffff +#define DPM_TABLE_472__Smio_29__SHIFT 0x0 +#define DPM_TABLE_473__Smio_30_MASK 0xffffffff +#define DPM_TABLE_473__Smio_30__SHIFT 0x0 +#define DPM_TABLE_474__Smio_31_MASK 0xffffffff +#define DPM_TABLE_474__Smio_31__SHIFT 0x0 +#define DPM_TABLE_475__SamuBootLevel_MASK 0xff +#define DPM_TABLE_475__SamuBootLevel__SHIFT 0x0 +#define DPM_TABLE_475__AcpBootLevel_MASK 0xff00 +#define DPM_TABLE_475__AcpBootLevel__SHIFT 0x8 +#define DPM_TABLE_475__VceBootLevel_MASK 0xff0000 +#define DPM_TABLE_475__VceBootLevel__SHIFT 0x10 +#define DPM_TABLE_475__UvdBootLevel_MASK 0xff000000 +#define DPM_TABLE_475__UvdBootLevel__SHIFT 0x18 +#define DPM_TABLE_476__SAMUInterval_MASK 0xff +#define DPM_TABLE_476__SAMUInterval__SHIFT 0x0 +#define DPM_TABLE_476__ACPInterval_MASK 0xff00 +#define DPM_TABLE_476__ACPInterval__SHIFT 0x8 +#define DPM_TABLE_476__VCEInterval_MASK 0xff0000 +#define DPM_TABLE_476__VCEInterval__SHIFT 0x10 +#define DPM_TABLE_476__UVDInterval_MASK 0xff000000 +#define DPM_TABLE_476__UVDInterval__SHIFT 0x18 +#define DPM_TABLE_477__GraphicsInterval_MASK 0xff +#define DPM_TABLE_477__GraphicsInterval__SHIFT 0x0 +#define DPM_TABLE_477__GraphicsThermThrottleEnable_MASK 0xff00 +#define DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT 0x8 +#define DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK 0xff0000 +#define DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT 0x10 +#define DPM_TABLE_477__GraphicsBootLevel_MASK 0xff000000 +#define DPM_TABLE_477__GraphicsBootLevel__SHIFT 0x18 +#define DPM_TABLE_478__TemperatureLimitHigh_MASK 0xffff +#define DPM_TABLE_478__TemperatureLimitHigh__SHIFT 0x0 +#define DPM_TABLE_478__ThermalInterval_MASK 0xff0000 +#define DPM_TABLE_478__ThermalInterval__SHIFT 0x10 +#define DPM_TABLE_478__VoltageInterval_MASK 0xff000000 +#define DPM_TABLE_478__VoltageInterval__SHIFT 0x18 +#define DPM_TABLE_479__MemoryVoltageChangeEnable_MASK 0xff +#define DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT 0x0 +#define DPM_TABLE_479__MemoryBootLevel_MASK 0xff00 +#define DPM_TABLE_479__MemoryBootLevel__SHIFT 0x8 +#define DPM_TABLE_479__TemperatureLimitLow_MASK 0xffff0000 +#define DPM_TABLE_479__TemperatureLimitLow__SHIFT 0x10 +#define DPM_TABLE_480__VddcVddciDelta_MASK 0xffff +#define DPM_TABLE_480__VddcVddciDelta__SHIFT 0x0 +#define DPM_TABLE_480__MemoryThermThrottleEnable_MASK 0xff0000 +#define DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT 0x10 +#define DPM_TABLE_480__MemoryInterval_MASK 0xff000000 +#define DPM_TABLE_480__MemoryInterval__SHIFT 0x18 +#define DPM_TABLE_481__PhaseResponseTime_MASK 0xffff +#define DPM_TABLE_481__PhaseResponseTime__SHIFT 0x0 +#define DPM_TABLE_481__VoltageResponseTime_MASK 0xffff0000 +#define DPM_TABLE_481__VoltageResponseTime__SHIFT 0x10 +#define DPM_TABLE_482__DTEMode_MASK 0xff +#define DPM_TABLE_482__DTEMode__SHIFT 0x0 +#define DPM_TABLE_482__DTEInterval_MASK 0xff00 +#define DPM_TABLE_482__DTEInterval__SHIFT 0x8 +#define DPM_TABLE_482__PCIeGenInterval_MASK 0xff0000 +#define DPM_TABLE_482__PCIeGenInterval__SHIFT 0x10 +#define DPM_TABLE_482__PCIeBootLinkLevel_MASK 0xff000000 +#define DPM_TABLE_482__PCIeBootLinkLevel__SHIFT 0x18 +#define DPM_TABLE_483__ThermGpio_MASK 0xff +#define DPM_TABLE_483__ThermGpio__SHIFT 0x0 +#define DPM_TABLE_483__AcDcGpio_MASK 0xff00 +#define DPM_TABLE_483__AcDcGpio__SHIFT 0x8 +#define DPM_TABLE_483__VRHotGpio_MASK 0xff0000 +#define DPM_TABLE_483__VRHotGpio__SHIFT 0x10 +#define DPM_TABLE_483__SVI2Enable_MASK 0xff000000 +#define DPM_TABLE_483__SVI2Enable__SHIFT 0x18 +#define DPM_TABLE_484__DisplayCac_MASK 0xffffffff +#define DPM_TABLE_484__DisplayCac__SHIFT 0x0 +#define DPM_TABLE_485__NomPwr_MASK 0xffff +#define DPM_TABLE_485__NomPwr__SHIFT 0x0 +#define DPM_TABLE_485__MaxPwr_MASK 0xffff0000 +#define DPM_TABLE_485__MaxPwr__SHIFT 0x10 +#define DPM_TABLE_486__FpsLowThreshold_MASK 0xffff +#define DPM_TABLE_486__FpsLowThreshold__SHIFT 0x0 +#define DPM_TABLE_486__FpsHighThreshold_MASK 0xffff0000 +#define DPM_TABLE_486__FpsHighThreshold__SHIFT 0x10 +#define DPM_TABLE_487__BAPMTI_R_0_1_0_MASK 0xffff +#define DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT 0x0 +#define DPM_TABLE_487__BAPMTI_R_0_0_0_MASK 0xffff0000 +#define DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT 0x10 +#define DPM_TABLE_488__BAPMTI_R_1_0_0_MASK 0xffff +#define DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT 0x0 +#define DPM_TABLE_488__BAPMTI_R_0_2_0_MASK 0xffff0000 +#define DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT 0x10 +#define DPM_TABLE_489__BAPMTI_R_1_2_0_MASK 0xffff +#define DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT 0x0 +#define DPM_TABLE_489__BAPMTI_R_1_1_0_MASK 0xffff0000 +#define DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT 0x10 +#define DPM_TABLE_490__BAPMTI_R_2_1_0_MASK 0xffff +#define DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT 0x0 +#define DPM_TABLE_490__BAPMTI_R_2_0_0_MASK 0xffff0000 +#define DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT 0x10 +#define DPM_TABLE_491__BAPMTI_R_3_0_0_MASK 0xffff +#define DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT 0x0 +#define DPM_TABLE_491__BAPMTI_R_2_2_0_MASK 0xffff0000 +#define DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT 0x10 +#define DPM_TABLE_492__BAPMTI_R_3_2_0_MASK 0xffff +#define DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT 0x0 +#define DPM_TABLE_492__BAPMTI_R_3_1_0_MASK 0xffff0000 +#define DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT 0x10 +#define DPM_TABLE_493__BAPMTI_R_4_1_0_MASK 0xffff +#define DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT 0x0 +#define DPM_TABLE_493__BAPMTI_R_4_0_0_MASK 0xffff0000 +#define DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT 0x10 +#define DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK 0xffff +#define DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT 0x0 +#define DPM_TABLE_494__BAPMTI_R_4_2_0_MASK 0xffff0000 +#define DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT 0x10 +#define DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK 0xffff +#define DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT 0x0 +#define DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK 0xffff0000 +#define DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT 0x10 +#define DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK 0xffff +#define DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT 0x0 +#define DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK 0xffff0000 +#define DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT 0x10 +#define DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK 0xffff +#define DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT 0x0 +#define DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK 0xffff0000 +#define DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT 0x10 +#define DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK 0xffff +#define DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT 0x0 +#define DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK 0xffff0000 +#define DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT 0x10 +#define DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK 0xffff +#define DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT 0x0 +#define DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK 0xffff0000 +#define DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT 0x10 +#define DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK 0xffff +#define DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT 0x0 +#define DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK 0xffff0000 +#define DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT 0x10 +#define DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK 0xffff +#define DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT 0x0 +#define DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK 0xffff0000 +#define DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT 0x10 +#define DPM_TABLE_502__GpuTjHyst_MASK 0xff +#define DPM_TABLE_502__GpuTjHyst__SHIFT 0x0 +#define DPM_TABLE_502__GpuTjMax_MASK 0xff00 +#define DPM_TABLE_502__GpuTjMax__SHIFT 0x8 +#define DPM_TABLE_502__DTETjOffset_MASK 0xff0000 +#define DPM_TABLE_502__DTETjOffset__SHIFT 0x10 +#define DPM_TABLE_502__DTEAmbientTempBase_MASK 0xff000000 +#define DPM_TABLE_502__DTEAmbientTempBase__SHIFT 0x18 +#define DPM_TABLE_503__BootVddci_MASK 0xffff +#define DPM_TABLE_503__BootVddci__SHIFT 0x0 +#define DPM_TABLE_503__BootVddc_MASK 0xffff0000 +#define DPM_TABLE_503__BootVddc__SHIFT 0x10 +#define DPM_TABLE_504__padding_MASK 0xffff +#define DPM_TABLE_504__padding__SHIFT 0x0 +#define DPM_TABLE_504__BootMVdd_MASK 0xffff0000 +#define DPM_TABLE_504__BootMVdd__SHIFT 0x10 +#define DPM_TABLE_505__DRAM_LOG_ADDR_H_MASK 0xffffffff +#define DPM_TABLE_505__DRAM_LOG_ADDR_H__SHIFT 0x0 +#define DPM_TABLE_506__DRAM_LOG_ADDR_L_MASK 0xffffffff +#define DPM_TABLE_506__DRAM_LOG_ADDR_L__SHIFT 0x0 +#define DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff +#define DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0 +#define DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff +#define DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0 +#define DPM_TABLE_509__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff +#define DPM_TABLE_509__DRAM_LOG_BUFF_SIZE__SHIFT 0x0 +#define DPM_TABLE_510__BAPM_TEMP_GRADIENT_MASK 0xffffffff +#define DPM_TABLE_510__BAPM_TEMP_GRADIENT__SHIFT 0x0 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe +#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 +#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 +#define TDC_STATUS__VDD_Boost_MASK 0xff +#define TDC_STATUS__VDD_Boost__SHIFT 0x0 +#define TDC_STATUS__VDD_Throttle_MASK 0xff00 +#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 +#define TDC_STATUS__VDDC_Boost_MASK 0xff0000 +#define TDC_STATUS__VDDC_Boost__SHIFT 0x10 +#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000 +#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18 +#define TDC_MV_AVERAGE__IDD_MASK 0xffff +#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 +#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000 +#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10 +#define TDC_VRM_LIMIT__IDD_MASK 0xffff +#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 +#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000 +#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10 +#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 +#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 +#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 +#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 +#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 +#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 +#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 +#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 +#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 +#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 +#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20 +#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5 +#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40 +#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6 +#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 +#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 +#define FEATURE_STATUS__BAPM_ON_MASK 0x100 +#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 +#define FEATURE_STATUS__LPMX_ON_MASK 0x200 +#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 +#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 +#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa +#define FEATURE_STATUS__LHTC_ON_MASK 0x800 +#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb +#define FEATURE_STATUS__VPC_ON_MASK 0x1000 +#define FEATURE_STATUS__VPC_ON__SHIFT 0xc +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd +#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 +#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe +#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 +#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf +#define FEATURE_STATUS__AVS_ON_MASK 0x10000 +#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 +#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 +#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 +#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 +#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 +#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 +#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 +#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 +#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 +#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 +#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 +#define FEATURE_STATUS__RESERVED_MASK 0xffc00000 +#define FEATURE_STATUS__RESERVED__SHIFT 0x16 +#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff +#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime__SHIFT 0x18 +#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff +#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00 +#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8 +#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000 +#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000 +#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18 +#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_82__data_4_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_82__data_4_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_83__data_4_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_83__data_4_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_84__data_4_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_84__data_4_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_85__data_4_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_85__data_4_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_86__data_4_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_86__data_4_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_87__data_4_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_87__data_4_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_88__data_4_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_88__data_4_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_89__data_4_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_89__data_4_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_90__data_4_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_90__data_4_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_91__data_4_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_91__data_4_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_92__data_4_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_93__data_4_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_93__data_4_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_94__data_4_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_94__data_4_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_95__data_4_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_95__data_4_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_96__data_4_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_96__data_4_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_97__data_4_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_97__data_4_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_98__data_5_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_98__data_5_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_99__data_5_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_99__data_5_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_100__data_5_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_100__data_5_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_101__data_5_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_102__data_5_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_103__data_5_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_103__data_5_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_104__data_5_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_104__data_5_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_105__data_5_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_105__data_5_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_106__data_5_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_106__data_5_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_107__data_5_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_107__data_5_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_108__data_5_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_109__data_5_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_109__data_5_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_110__data_5_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_111__data_5_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_111__data_5_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_112__data_5_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_112__data_5_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_113__data_5_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_113__data_5_value_15__SHIFT 0x0 +#define FAN_TABLE_1__TempMin_MASK 0xffff +#define FAN_TABLE_1__TempMin__SHIFT 0x0 +#define FAN_TABLE_1__FdoMode_MASK 0xffff0000 +#define FAN_TABLE_1__FdoMode__SHIFT 0x10 +#define FAN_TABLE_2__TempMax_MASK 0xffff +#define FAN_TABLE_2__TempMax__SHIFT 0x0 +#define FAN_TABLE_2__TempMed_MASK 0xffff0000 +#define FAN_TABLE_2__TempMed__SHIFT 0x10 +#define FAN_TABLE_3__Slope2_MASK 0xffff +#define FAN_TABLE_3__Slope2__SHIFT 0x0 +#define FAN_TABLE_3__Slope1_MASK 0xffff0000 +#define FAN_TABLE_3__Slope1__SHIFT 0x10 +#define FAN_TABLE_4__HystUp_MASK 0xffff +#define FAN_TABLE_4__HystUp__SHIFT 0x0 +#define FAN_TABLE_4__FdoMin_MASK 0xffff0000 +#define FAN_TABLE_4__FdoMin__SHIFT 0x10 +#define FAN_TABLE_5__HystSlope_MASK 0xffff +#define FAN_TABLE_5__HystSlope__SHIFT 0x0 +#define FAN_TABLE_5__HystDown_MASK 0xffff0000 +#define FAN_TABLE_5__HystDown__SHIFT 0x10 +#define FAN_TABLE_6__TempCurr_MASK 0xffff +#define FAN_TABLE_6__TempCurr__SHIFT 0x0 +#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000 +#define FAN_TABLE_6__TempRespLim__SHIFT 0x10 +#define FAN_TABLE_7__PwmCurr_MASK 0xffff +#define FAN_TABLE_7__PwmCurr__SHIFT 0x0 +#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000 +#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10 +#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff +#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0 +#define FAN_TABLE_9__Padding_MASK 0xff +#define FAN_TABLE_9__Padding__SHIFT 0x0 +#define FAN_TABLE_9__TempSrc_MASK 0xff00 +#define FAN_TABLE_9__TempSrc__SHIFT 0x8 +#define FAN_TABLE_9__FdoMax_MASK 0xffff0000 +#define FAN_TABLE_9__FdoMax__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_21__Reserved_0_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_21__Reserved_0__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_22__Reserved_1_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_22__Reserved_1__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_23__Reserved_2_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_23__Reserved_2__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_24__Reserved_3_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_24__Reserved_3__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_25__Reserved_4_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_25__Reserved_4__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_26__Reserved_5_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_26__Reserved_5__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_27__Reserved_6_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_27__Reserved_6__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_28__Reserved_7_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_28__Reserved_7__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_29__Reserved_8_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_29__Reserved_8__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_30__Reserved_9_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_30__Reserved_9__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff +#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00 +#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8 +#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000 +#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10 +#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000 +#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18 +#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff +#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0 +#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00 +#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8 +#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000 +#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10 +#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000 +#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18 +#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff +#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0 +#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00 +#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8 +#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000 +#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10 +#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000 +#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18 +#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff +#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0 +#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00 +#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8 +#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000 +#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10 +#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000 +#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18 +#define PM_FUSES_5__VddCVid_3_MASK 0xff +#define PM_FUSES_5__VddCVid_3__SHIFT 0x0 +#define PM_FUSES_5__VddCVid_2_MASK 0xff00 +#define PM_FUSES_5__VddCVid_2__SHIFT 0x8 +#define PM_FUSES_5__VddCVid_1_MASK 0xff0000 +#define PM_FUSES_5__VddCVid_1__SHIFT 0x10 +#define PM_FUSES_5__VddCVid_0_MASK 0xff000000 +#define PM_FUSES_5__VddCVid_0__SHIFT 0x18 +#define PM_FUSES_6__VddCVid_7_MASK 0xff +#define PM_FUSES_6__VddCVid_7__SHIFT 0x0 +#define PM_FUSES_6__VddCVid_6_MASK 0xff00 +#define PM_FUSES_6__VddCVid_6__SHIFT 0x8 +#define PM_FUSES_6__VddCVid_5_MASK 0xff0000 +#define PM_FUSES_6__VddCVid_5__SHIFT 0x10 +#define PM_FUSES_6__VddCVid_4_MASK 0xff000000 +#define PM_FUSES_6__VddCVid_4__SHIFT 0x18 +#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff +#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0 +#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00 +#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8 +#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000 +#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10 +#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000 +#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18 +#define PM_FUSES_8__TDC_MAWt_MASK 0xff +#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8 +#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000 +#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10 +#define PM_FUSES_9__Reserved_MASK 0xff +#define PM_FUSES_9__Reserved__SHIFT 0x0 +#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00 +#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8 +#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000 +#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10 +#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000 +#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18 +#define PM_FUSES_10__LPMLTemperatureScaler_3_MASK 0xff +#define PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT 0x0 +#define PM_FUSES_10__LPMLTemperatureScaler_2_MASK 0xff00 +#define PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT 0x8 +#define PM_FUSES_10__LPMLTemperatureScaler_1_MASK 0xff0000 +#define PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT 0x10 +#define PM_FUSES_10__LPMLTemperatureScaler_0_MASK 0xff000000 +#define PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT 0x18 +#define PM_FUSES_11__LPMLTemperatureScaler_7_MASK 0xff +#define PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT 0x0 +#define PM_FUSES_11__LPMLTemperatureScaler_6_MASK 0xff00 +#define PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT 0x8 +#define PM_FUSES_11__LPMLTemperatureScaler_5_MASK 0xff0000 +#define PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT 0x10 +#define PM_FUSES_11__LPMLTemperatureScaler_4_MASK 0xff000000 +#define PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT 0x18 +#define PM_FUSES_12__LPMLTemperatureScaler_11_MASK 0xff +#define PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT 0x0 +#define PM_FUSES_12__LPMLTemperatureScaler_10_MASK 0xff00 +#define PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT 0x8 +#define PM_FUSES_12__LPMLTemperatureScaler_9_MASK 0xff0000 +#define PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT 0x10 +#define PM_FUSES_12__LPMLTemperatureScaler_8_MASK 0xff000000 +#define PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT 0x18 +#define PM_FUSES_13__LPMLTemperatureScaler_15_MASK 0xff +#define PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT 0x0 +#define PM_FUSES_13__LPMLTemperatureScaler_14_MASK 0xff00 +#define PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT 0x8 +#define PM_FUSES_13__LPMLTemperatureScaler_13_MASK 0xff0000 +#define PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT 0x10 +#define PM_FUSES_13__LPMLTemperatureScaler_12_MASK 0xff000000 +#define PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT 0x18 +#define PM_FUSES_14__GnbLPML_3_MASK 0xff +#define PM_FUSES_14__GnbLPML_3__SHIFT 0x0 +#define PM_FUSES_14__GnbLPML_2_MASK 0xff00 +#define PM_FUSES_14__GnbLPML_2__SHIFT 0x8 +#define PM_FUSES_14__GnbLPML_1_MASK 0xff0000 +#define PM_FUSES_14__GnbLPML_1__SHIFT 0x10 +#define PM_FUSES_14__GnbLPML_0_MASK 0xff000000 +#define PM_FUSES_14__GnbLPML_0__SHIFT 0x18 +#define PM_FUSES_15__GnbLPML_7_MASK 0xff +#define PM_FUSES_15__GnbLPML_7__SHIFT 0x0 +#define PM_FUSES_15__GnbLPML_6_MASK 0xff00 +#define PM_FUSES_15__GnbLPML_6__SHIFT 0x8 +#define PM_FUSES_15__GnbLPML_5_MASK 0xff0000 +#define PM_FUSES_15__GnbLPML_5__SHIFT 0x10 +#define PM_FUSES_15__GnbLPML_4_MASK 0xff000000 +#define PM_FUSES_15__GnbLPML_4__SHIFT 0x18 +#define PM_FUSES_16__GnbLPML_11_MASK 0xff +#define PM_FUSES_16__GnbLPML_11__SHIFT 0x0 +#define PM_FUSES_16__GnbLPML_10_MASK 0xff00 +#define PM_FUSES_16__GnbLPML_10__SHIFT 0x8 +#define PM_FUSES_16__GnbLPML_9_MASK 0xff0000 +#define PM_FUSES_16__GnbLPML_9__SHIFT 0x10 +#define PM_FUSES_16__GnbLPML_8_MASK 0xff000000 +#define PM_FUSES_16__GnbLPML_8__SHIFT 0x18 +#define PM_FUSES_17__GnbLPML_15_MASK 0xff +#define PM_FUSES_17__GnbLPML_15__SHIFT 0x0 +#define PM_FUSES_17__GnbLPML_14_MASK 0xff00 +#define PM_FUSES_17__GnbLPML_14__SHIFT 0x8 +#define PM_FUSES_17__GnbLPML_13_MASK 0xff0000 +#define PM_FUSES_17__GnbLPML_13__SHIFT 0x10 +#define PM_FUSES_17__GnbLPML_12_MASK 0xff000000 +#define PM_FUSES_17__GnbLPML_12__SHIFT 0x18 +#define PM_FUSES_18__Reserved1_1_MASK 0xff +#define PM_FUSES_18__Reserved1_1__SHIFT 0x0 +#define PM_FUSES_18__Reserved1_0_MASK 0xff00 +#define PM_FUSES_18__Reserved1_0__SHIFT 0x8 +#define PM_FUSES_18__GnbLPMLMinVid_MASK 0xff0000 +#define PM_FUSES_18__GnbLPMLMinVid__SHIFT 0x10 +#define PM_FUSES_18__GnbLPMLMaxVid_MASK 0xff000000 +#define PM_FUSES_18__GnbLPMLMaxVid__SHIFT 0x18 +#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd_MASK 0xffff +#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd__SHIFT 0x0 +#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000 +#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd__SHIFT 0x10 +#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_52__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0 +#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8 +#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3 +#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0 +#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4 +#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000 +#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe +#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000 +#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19 +#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000 +#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a +#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff +#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 +#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000 +#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11 +#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000 +#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12 +#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff +#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0 +#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00 +#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8 +#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000 +#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10 +#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000 +#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18 +#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf +#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 +#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0 +#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 +#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff +#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 +#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff +#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 +#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00 +#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL1__M_MASK 0xff0000 +#define CG_FDO_CTRL1__M__SHIFT 0x10 +#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000 +#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 +#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000 +#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e +#define CG_FDO_CTRL2__TMIN_MASK 0xff +#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 +#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800 +#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb +#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000 +#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe +#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000 +#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 +#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7 +#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 +#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8 +#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 +#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff +#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 +#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe +#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1 +#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00 +#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11 +#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000 +#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12 +#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000 +#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18 +#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000 +#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19 +#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000 +#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a +#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000 +#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b +#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000 +#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c +#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000 +#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d +#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000 +#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_INT_DATA__Z_MASK 0x7ff +#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON0_INT_DATA__VALID_MASK 0x800 +#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40 +#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17 +#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000 +#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf +#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 +#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 +#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 +#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 +#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 +#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf +#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 +#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1 +#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0 +#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe +#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0 +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2 +#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1 +#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4 +#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10 +#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000 +#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a +#define ROM_STATUS__ROM_BUSY_MASK 0x1 +#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf +#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define ROM_INDEX__ROM_INDEX_MASK 0xffffff +#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 +#define ROM_DATA__ROM_DATA_MASK 0xffffffff +#define ROM_DATA__ROM_DATA__SHIFT 0x0 +#define ROM_START__ROM_START_MASK 0xffffff +#define ROM_START__ROM_START__SHIFT 0x0 +#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff +#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 +#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000 +#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 +#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1 +#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 +#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 + +#endif /* SMU_7_0_1_SH_MASK_H */ -- cgit v1.2.3 From 90593ac0dad13e0ff20426a9389836641a54fc98 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:30:14 -0400 Subject: drm/amdgpu: add SMU 7.1.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h | 1344 +++++ .../drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h | 1191 +++++ .../amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h | 5648 ++++++++++++++++++++ 3 files changed, 8183 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h new file mode 100644 index 000000000000..57588b11ff1a --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h @@ -0,0 +1,1344 @@ +/* + * SMU_7_1_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_0_D_H +#define SMU_7_1_0_D_H + +#define mmGCK_SMC_IND_INDEX 0x80 +#define mmGCK0_GCK_SMC_IND_INDEX 0x80 +#define mmGCK1_GCK_SMC_IND_INDEX 0x82 +#define mmGCK2_GCK_SMC_IND_INDEX 0x84 +#define mmGCK3_GCK_SMC_IND_INDEX 0x86 +#define mmGCK_SMC_IND_DATA 0x81 +#define mmGCK0_GCK_SMC_IND_DATA 0x81 +#define mmGCK1_GCK_SMC_IND_DATA 0x83 +#define mmGCK2_GCK_SMC_IND_DATA 0x85 +#define mmGCK3_GCK_SMC_IND_DATA 0x87 +#define ixCG_DCLK_CNTL 0xc050009c +#define ixCG_DCLK_STATUS 0xc05000a0 +#define ixCG_VCLK_CNTL 0xc05000a4 +#define ixCG_VCLK_STATUS 0xc05000a8 +#define ixCG_ECLK_CNTL 0xc05000ac +#define ixCG_ECLK_STATUS 0xc05000b0 +#define ixCG_ACLK_CNTL 0xc05000dc +#define ixGCK_DFS_BYPASS_CNTL 0xc0500118 +#define ixCG_SPLL_FUNC_CNTL 0xc0500140 +#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 +#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 +#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c +#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 +#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 +#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 +#define ixSPLL_CNTL_MODE 0xc0500160 +#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 +#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +#define ixMPLL_BYPASSCLK_SEL 0xc050019c +#define ixCG_CLKPIN_CNTL 0xc05001a0 +#define ixCG_CLKPIN_CNTL_2 0xc05001a4 +#define ixCG_CLKPIN_CNTL_DC 0xc0500204 +#define ixTHM_CLK_CNTL 0xc05001a8 +#define ixMISC_CLK_CTRL 0xc05001ac +#define ixGCK_PLL_TEST_CNTL 0xc05001c0 +#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 +#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 +#define mmSMC_IND_INDEX 0x80 +#define mmSMC0_SMC_IND_INDEX 0x80 +#define mmSMC1_SMC_IND_INDEX 0x82 +#define mmSMC2_SMC_IND_INDEX 0x84 +#define mmSMC3_SMC_IND_INDEX 0x86 +#define mmSMC_IND_DATA 0x81 +#define mmSMC0_SMC_IND_DATA 0x81 +#define mmSMC1_SMC_IND_DATA 0x83 +#define mmSMC2_SMC_IND_DATA 0x85 +#define mmSMC3_SMC_IND_DATA 0x87 +#define mmSMC_IND_INDEX_0 0x80 +#define mmSMC_IND_DATA_0 0x81 +#define mmSMC_IND_INDEX_1 0x82 +#define mmSMC_IND_DATA_1 0x83 +#define mmSMC_IND_INDEX_2 0x84 +#define mmSMC_IND_DATA_2 0x85 +#define mmSMC_IND_INDEX_3 0x86 +#define mmSMC_IND_DATA_3 0x87 +#define mmSMC_IND_INDEX_4 0x88 +#define mmSMC_IND_DATA_4 0x89 +#define mmSMC_IND_INDEX_5 0x8a +#define mmSMC_IND_DATA_5 0x8b +#define mmSMC_IND_INDEX_6 0x8c +#define mmSMC_IND_DATA_6 0x8d +#define mmSMC_IND_INDEX_7 0x8e +#define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_ACCESS_CNTL 0x90 +#define mmSMC_MESSAGE_0 0x94 +#define mmSMC_RESP_0 0x95 +#define mmSMC_MESSAGE_1 0x96 +#define mmSMC_RESP_1 0x97 +#define mmSMC_MESSAGE_2 0x98 +#define mmSMC_RESP_2 0x99 +#define mmSMC_MESSAGE_3 0x9a +#define mmSMC_RESP_3 0x9b +#define mmSMC_MESSAGE_4 0x9c +#define mmSMC_RESP_4 0x9d +#define mmSMC_MESSAGE_5 0x9e +#define mmSMC_RESP_5 0x9f +#define mmSMC_MESSAGE_6 0xa0 +#define mmSMC_RESP_6 0xa1 +#define mmSMC_MESSAGE_7 0xa2 +#define mmSMC_RESP_7 0xa3 +#define mmSMC_MSG_ARG_0 0xa4 +#define mmSMC_MSG_ARG_1 0xa5 +#define mmSMC_MSG_ARG_2 0xa6 +#define mmSMC_MSG_ARG_3 0xa7 +#define mmSMC_MSG_ARG_4 0xa8 +#define mmSMC_MSG_ARG_5 0xa9 +#define mmSMC_MSG_ARG_6 0xaa +#define mmSMC_MSG_ARG_7 0xab +#define mmSMC_MESSAGE_8 0xb5 +#define mmSMC_RESP_8 0xb6 +#define mmSMC_MESSAGE_9 0xb7 +#define mmSMC_RESP_9 0xb8 +#define mmSMC_MESSAGE_10 0xb9 +#define mmSMC_RESP_10 0xba +#define mmSMC_MESSAGE_11 0xbb +#define mmSMC_RESP_11 0xbc +#define mmSMC_MSG_ARG_8 0xbd +#define mmSMC_MSG_ARG_9 0xbe +#define mmSMC_MSG_ARG_10 0xbf +#define mmSMC_MSG_ARG_11 0x91 +#define ixSMC_SYSCON_RESET_CNTL 0x80000000 +#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 +#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 +#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c +#define ixSMC_SYSCON_MISC_CNTL 0x80000010 +#define ixSMC_SYSCON_MSG_ARG_0 0x80000068 +#define ixSMC_PC_C 0x80000370 +#define ixSMC_SCRATCH9 0x80000424 +#define mmGPIOPAD_SW_INT_STAT 0x180 +#define mmGPIOPAD_STRENGTH 0x181 +#define mmGPIOPAD_MASK 0x182 +#define mmGPIOPAD_A 0x183 +#define mmGPIOPAD_EN 0x184 +#define mmGPIOPAD_Y 0x185 +#define mmGPIOPAD_PINSTRAPS 0x186 +#define mmGPIOPAD_INT_STAT_EN 0x187 +#define mmGPIOPAD_INT_STAT 0x188 +#define mmGPIOPAD_INT_STAT_AK 0x189 +#define mmGPIOPAD_INT_EN 0x18a +#define mmGPIOPAD_INT_TYPE 0x18b +#define mmGPIOPAD_INT_POLARITY 0x18c +#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d +#define mmGPIOPAD_RCVR_SEL 0x191 +#define mmGPIOPAD_PU_EN 0x192 +#define mmGPIOPAD_PD_EN 0x193 +#define mmCG_FPS_CNT 0x1a4 +#define mmSMU_SMC_IND_INDEX 0x80 +#define mmSMU0_SMU_SMC_IND_INDEX 0x80 +#define mmSMU1_SMU_SMC_IND_INDEX 0x82 +#define mmSMU2_SMU_SMC_IND_INDEX 0x84 +#define mmSMU3_SMU_SMC_IND_INDEX 0x86 +#define mmSMU_SMC_IND_DATA 0x81 +#define mmSMU0_SMU_SMC_IND_DATA 0x81 +#define mmSMU1_SMU_SMC_IND_DATA 0x83 +#define mmSMU2_SMU_SMC_IND_DATA 0x85 +#define mmSMU3_SMU_SMC_IND_DATA 0x87 +#define ixRCU_UC_EVENTS 0xc0000004 +#define ixRCU_MISC_CTRL 0xc0000010 +#define ixCC_RCU_FUSES 0xc00c0000 +#define ixCC_SMU_MISC_FUSES 0xc00c0004 +#define ixCC_SCLK_VID_FUSES 0xc00c0008 +#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c +#define ixCC_GIO_IOC_FUSES 0xc00c0010 +#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c +#define ixCC_TST_ID_STRAPS 0xc00c0020 +#define ixCC_FCTRL_FUSES 0xc00c0024 +#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 +#define ixSMU_STATUS 0xe0003088 +#define ixSMU_FIRMWARE 0xe00030a4 +#define ixSMU_INPUT_DATA 0xe00030b8 +#define ixSMU_EFUSE_0 0xc0100000 +#define ixDPM_TABLE_1 0x3f000 +#define ixDPM_TABLE_2 0x3f004 +#define ixDPM_TABLE_3 0x3f008 +#define ixDPM_TABLE_4 0x3f00c +#define ixDPM_TABLE_5 0x3f010 +#define ixDPM_TABLE_6 0x3f014 +#define ixDPM_TABLE_7 0x3f018 +#define ixDPM_TABLE_8 0x3f01c +#define ixDPM_TABLE_9 0x3f020 +#define ixDPM_TABLE_10 0x3f024 +#define ixDPM_TABLE_11 0x3f028 +#define ixDPM_TABLE_12 0x3f02c +#define ixDPM_TABLE_13 0x3f030 +#define ixDPM_TABLE_14 0x3f034 +#define ixDPM_TABLE_15 0x3f038 +#define ixDPM_TABLE_16 0x3f03c +#define ixDPM_TABLE_17 0x3f040 +#define ixDPM_TABLE_18 0x3f044 +#define ixDPM_TABLE_19 0x3f048 +#define ixDPM_TABLE_20 0x3f04c +#define ixDPM_TABLE_21 0x3f050 +#define ixDPM_TABLE_22 0x3f054 +#define ixDPM_TABLE_23 0x3f058 +#define ixDPM_TABLE_24 0x3f05c +#define ixDPM_TABLE_25 0x3f060 +#define ixDPM_TABLE_26 0x3f064 +#define ixDPM_TABLE_27 0x3f068 +#define ixDPM_TABLE_28 0x3f06c +#define ixDPM_TABLE_29 0x3f070 +#define ixDPM_TABLE_30 0x3f074 +#define ixDPM_TABLE_31 0x3f078 +#define ixDPM_TABLE_32 0x3f07c +#define ixDPM_TABLE_33 0x3f080 +#define ixDPM_TABLE_34 0x3f084 +#define ixDPM_TABLE_35 0x3f088 +#define ixDPM_TABLE_36 0x3f08c +#define ixDPM_TABLE_37 0x3f090 +#define ixDPM_TABLE_38 0x3f094 +#define ixDPM_TABLE_39 0x3f098 +#define ixDPM_TABLE_40 0x3f09c +#define ixDPM_TABLE_41 0x3f0a0 +#define ixDPM_TABLE_42 0x3f0a4 +#define ixDPM_TABLE_43 0x3f0a8 +#define ixDPM_TABLE_44 0x3f0ac +#define ixDPM_TABLE_45 0x3f0b0 +#define ixDPM_TABLE_46 0x3f0b4 +#define ixDPM_TABLE_47 0x3f0b8 +#define ixDPM_TABLE_48 0x3f0bc +#define ixDPM_TABLE_49 0x3f0c0 +#define ixDPM_TABLE_50 0x3f0c4 +#define ixDPM_TABLE_51 0x3f0c8 +#define ixDPM_TABLE_52 0x3f0cc +#define ixDPM_TABLE_53 0x3f0d0 +#define ixDPM_TABLE_54 0x3f0d4 +#define ixDPM_TABLE_55 0x3f0d8 +#define ixDPM_TABLE_56 0x3f0dc +#define ixDPM_TABLE_57 0x3f0e0 +#define ixDPM_TABLE_58 0x3f0e4 +#define ixDPM_TABLE_59 0x3f0e8 +#define ixDPM_TABLE_60 0x3f0ec +#define ixDPM_TABLE_61 0x3f0f0 +#define ixDPM_TABLE_62 0x3f0f4 +#define ixDPM_TABLE_63 0x3f0f8 +#define ixDPM_TABLE_64 0x3f0fc +#define ixDPM_TABLE_65 0x3f100 +#define ixDPM_TABLE_66 0x3f104 +#define ixDPM_TABLE_67 0x3f108 +#define ixDPM_TABLE_68 0x3f10c +#define ixDPM_TABLE_69 0x3f110 +#define ixDPM_TABLE_70 0x3f114 +#define ixDPM_TABLE_71 0x3f118 +#define ixDPM_TABLE_72 0x3f11c +#define ixDPM_TABLE_73 0x3f120 +#define ixDPM_TABLE_74 0x3f124 +#define ixDPM_TABLE_75 0x3f128 +#define ixDPM_TABLE_76 0x3f12c +#define ixDPM_TABLE_77 0x3f130 +#define ixDPM_TABLE_78 0x3f134 +#define ixDPM_TABLE_79 0x3f138 +#define ixDPM_TABLE_80 0x3f13c +#define ixDPM_TABLE_81 0x3f140 +#define ixDPM_TABLE_82 0x3f144 +#define ixDPM_TABLE_83 0x3f148 +#define ixDPM_TABLE_84 0x3f14c +#define ixDPM_TABLE_85 0x3f150 +#define ixDPM_TABLE_86 0x3f154 +#define ixDPM_TABLE_87 0x3f158 +#define ixDPM_TABLE_88 0x3f15c +#define ixDPM_TABLE_89 0x3f160 +#define ixDPM_TABLE_90 0x3f164 +#define ixDPM_TABLE_91 0x3f168 +#define ixDPM_TABLE_92 0x3f16c +#define ixDPM_TABLE_93 0x3f170 +#define ixDPM_TABLE_94 0x3f174 +#define ixDPM_TABLE_95 0x3f178 +#define ixDPM_TABLE_96 0x3f17c +#define ixDPM_TABLE_97 0x3f180 +#define ixDPM_TABLE_98 0x3f184 +#define ixDPM_TABLE_99 0x3f188 +#define ixDPM_TABLE_100 0x3f18c +#define ixDPM_TABLE_101 0x3f190 +#define ixDPM_TABLE_102 0x3f194 +#define ixDPM_TABLE_103 0x3f198 +#define ixDPM_TABLE_104 0x3f19c +#define ixDPM_TABLE_105 0x3f1a0 +#define ixDPM_TABLE_106 0x3f1a4 +#define ixDPM_TABLE_107 0x3f1a8 +#define ixDPM_TABLE_108 0x3f1ac +#define ixDPM_TABLE_109 0x3f1b0 +#define ixDPM_TABLE_110 0x3f1b4 +#define ixDPM_TABLE_111 0x3f1b8 +#define ixDPM_TABLE_112 0x3f1bc +#define ixDPM_TABLE_113 0x3f1c0 +#define ixDPM_TABLE_114 0x3f1c4 +#define ixDPM_TABLE_115 0x3f1c8 +#define ixDPM_TABLE_116 0x3f1cc +#define ixDPM_TABLE_117 0x3f1d0 +#define ixDPM_TABLE_118 0x3f1d4 +#define ixDPM_TABLE_119 0x3f1d8 +#define ixDPM_TABLE_120 0x3f1dc +#define ixDPM_TABLE_121 0x3f1e0 +#define ixDPM_TABLE_122 0x3f1e4 +#define ixDPM_TABLE_123 0x3f1e8 +#define ixDPM_TABLE_124 0x3f1ec +#define ixDPM_TABLE_125 0x3f1f0 +#define ixDPM_TABLE_126 0x3f1f4 +#define ixDPM_TABLE_127 0x3f1f8 +#define ixDPM_TABLE_128 0x3f1fc +#define ixDPM_TABLE_129 0x3f200 +#define ixDPM_TABLE_130 0x3f204 +#define ixDPM_TABLE_131 0x3f208 +#define ixDPM_TABLE_132 0x3f20c +#define ixDPM_TABLE_133 0x3f210 +#define ixDPM_TABLE_134 0x3f214 +#define ixDPM_TABLE_135 0x3f218 +#define ixDPM_TABLE_136 0x3f21c +#define ixDPM_TABLE_137 0x3f220 +#define ixDPM_TABLE_138 0x3f224 +#define ixDPM_TABLE_139 0x3f228 +#define ixDPM_TABLE_140 0x3f22c +#define ixDPM_TABLE_141 0x3f230 +#define ixDPM_TABLE_142 0x3f234 +#define ixDPM_TABLE_143 0x3f238 +#define ixDPM_TABLE_144 0x3f23c +#define ixDPM_TABLE_145 0x3f240 +#define ixDPM_TABLE_146 0x3f244 +#define ixDPM_TABLE_147 0x3f248 +#define ixDPM_TABLE_148 0x3f24c +#define ixDPM_TABLE_149 0x3f250 +#define ixDPM_TABLE_150 0x3f254 +#define ixDPM_TABLE_151 0x3f258 +#define ixDPM_TABLE_152 0x3f25c +#define ixDPM_TABLE_153 0x3f260 +#define ixDPM_TABLE_154 0x3f264 +#define ixDPM_TABLE_155 0x3f268 +#define ixDPM_TABLE_156 0x3f26c +#define ixDPM_TABLE_157 0x3f270 +#define ixDPM_TABLE_158 0x3f274 +#define ixDPM_TABLE_159 0x3f278 +#define ixDPM_TABLE_160 0x3f27c +#define ixDPM_TABLE_161 0x3f280 +#define ixDPM_TABLE_162 0x3f284 +#define ixDPM_TABLE_163 0x3f288 +#define ixDPM_TABLE_164 0x3f28c +#define ixDPM_TABLE_165 0x3f290 +#define ixDPM_TABLE_166 0x3f294 +#define ixDPM_TABLE_167 0x3f298 +#define ixDPM_TABLE_168 0x3f29c +#define ixDPM_TABLE_169 0x3f2a0 +#define ixDPM_TABLE_170 0x3f2a4 +#define ixDPM_TABLE_171 0x3f2a8 +#define ixDPM_TABLE_172 0x3f2ac +#define ixDPM_TABLE_173 0x3f2b0 +#define ixDPM_TABLE_174 0x3f2b4 +#define ixDPM_TABLE_175 0x3f2b8 +#define ixDPM_TABLE_176 0x3f2bc +#define ixDPM_TABLE_177 0x3f2c0 +#define ixDPM_TABLE_178 0x3f2c4 +#define ixDPM_TABLE_179 0x3f2c8 +#define ixDPM_TABLE_180 0x3f2cc +#define ixDPM_TABLE_181 0x3f2d0 +#define ixDPM_TABLE_182 0x3f2d4 +#define ixDPM_TABLE_183 0x3f2d8 +#define ixDPM_TABLE_184 0x3f2dc +#define ixDPM_TABLE_185 0x3f2e0 +#define ixDPM_TABLE_186 0x3f2e4 +#define ixDPM_TABLE_187 0x3f2e8 +#define ixDPM_TABLE_188 0x3f2ec +#define ixDPM_TABLE_189 0x3f2f0 +#define ixDPM_TABLE_190 0x3f2f4 +#define ixDPM_TABLE_191 0x3f2f8 +#define ixDPM_TABLE_192 0x3f2fc +#define ixDPM_TABLE_193 0x3f300 +#define ixDPM_TABLE_194 0x3f304 +#define ixDPM_TABLE_195 0x3f308 +#define ixDPM_TABLE_196 0x3f30c +#define ixDPM_TABLE_197 0x3f310 +#define ixDPM_TABLE_198 0x3f314 +#define ixDPM_TABLE_199 0x3f318 +#define ixDPM_TABLE_200 0x3f31c +#define ixDPM_TABLE_201 0x3f320 +#define ixDPM_TABLE_202 0x3f324 +#define ixDPM_TABLE_203 0x3f328 +#define ixDPM_TABLE_204 0x3f32c +#define ixDPM_TABLE_205 0x3f330 +#define ixDPM_TABLE_206 0x3f334 +#define ixDPM_TABLE_207 0x3f338 +#define ixDPM_TABLE_208 0x3f33c +#define ixDPM_TABLE_209 0x3f340 +#define ixDPM_TABLE_210 0x3f344 +#define ixDPM_TABLE_211 0x3f348 +#define ixDPM_TABLE_212 0x3f34c +#define ixDPM_TABLE_213 0x3f350 +#define ixDPM_TABLE_214 0x3f354 +#define ixDPM_TABLE_215 0x3f358 +#define ixDPM_TABLE_216 0x3f35c +#define ixDPM_TABLE_217 0x3f360 +#define ixDPM_TABLE_218 0x3f364 +#define ixDPM_TABLE_219 0x3f368 +#define ixDPM_TABLE_220 0x3f36c +#define ixDPM_TABLE_221 0x3f370 +#define ixDPM_TABLE_222 0x3f374 +#define ixDPM_TABLE_223 0x3f378 +#define ixDPM_TABLE_224 0x3f37c +#define ixDPM_TABLE_225 0x3f380 +#define ixDPM_TABLE_226 0x3f384 +#define ixDPM_TABLE_227 0x3f388 +#define ixDPM_TABLE_228 0x3f38c +#define ixDPM_TABLE_229 0x3f390 +#define ixDPM_TABLE_230 0x3f394 +#define ixDPM_TABLE_231 0x3f398 +#define ixDPM_TABLE_232 0x3f39c +#define ixDPM_TABLE_233 0x3f3a0 +#define ixDPM_TABLE_234 0x3f3a4 +#define ixDPM_TABLE_235 0x3f3a8 +#define ixDPM_TABLE_236 0x3f3ac +#define ixDPM_TABLE_237 0x3f3b0 +#define ixDPM_TABLE_238 0x3f3b4 +#define ixDPM_TABLE_239 0x3f3b8 +#define ixDPM_TABLE_240 0x3f3bc +#define ixDPM_TABLE_241 0x3f3c0 +#define ixDPM_TABLE_242 0x3f3c4 +#define ixDPM_TABLE_243 0x3f3c8 +#define ixDPM_TABLE_244 0x3f3cc +#define ixDPM_TABLE_245 0x3f3d0 +#define ixDPM_TABLE_246 0x3f3d4 +#define ixDPM_TABLE_247 0x3f3d8 +#define ixDPM_TABLE_248 0x3f3dc +#define ixDPM_TABLE_249 0x3f3e0 +#define ixDPM_TABLE_250 0x3f3e4 +#define ixDPM_TABLE_251 0x3f3e8 +#define ixDPM_TABLE_252 0x3f3ec +#define ixDPM_TABLE_253 0x3f3f0 +#define ixDPM_TABLE_254 0x3f3f4 +#define ixDPM_TABLE_255 0x3f3f8 +#define ixDPM_TABLE_256 0x3f3fc +#define ixDPM_TABLE_257 0x3f400 +#define ixDPM_TABLE_258 0x3f404 +#define ixDPM_TABLE_259 0x3f408 +#define ixDPM_TABLE_260 0x3f40c +#define ixDPM_TABLE_261 0x3f410 +#define ixDPM_TABLE_262 0x3f414 +#define ixDPM_TABLE_263 0x3f418 +#define ixDPM_TABLE_264 0x3f41c +#define ixDPM_TABLE_265 0x3f420 +#define ixDPM_TABLE_266 0x3f424 +#define ixDPM_TABLE_267 0x3f428 +#define ixDPM_TABLE_268 0x3f42c +#define ixDPM_TABLE_269 0x3f430 +#define ixDPM_TABLE_270 0x3f434 +#define ixDPM_TABLE_271 0x3f438 +#define ixDPM_TABLE_272 0x3f43c +#define ixDPM_TABLE_273 0x3f440 +#define ixDPM_TABLE_274 0x3f444 +#define ixDPM_TABLE_275 0x3f448 +#define ixDPM_TABLE_276 0x3f44c +#define ixDPM_TABLE_277 0x3f450 +#define ixDPM_TABLE_278 0x3f454 +#define ixDPM_TABLE_279 0x3f458 +#define ixDPM_TABLE_280 0x3f45c +#define ixDPM_TABLE_281 0x3f460 +#define ixDPM_TABLE_282 0x3f464 +#define ixDPM_TABLE_283 0x3f468 +#define ixDPM_TABLE_284 0x3f46c +#define ixDPM_TABLE_285 0x3f470 +#define ixDPM_TABLE_286 0x3f474 +#define ixDPM_TABLE_287 0x3f478 +#define ixDPM_TABLE_288 0x3f47c +#define ixDPM_TABLE_289 0x3f480 +#define ixDPM_TABLE_290 0x3f484 +#define ixDPM_TABLE_291 0x3f488 +#define ixDPM_TABLE_292 0x3f48c +#define ixDPM_TABLE_293 0x3f490 +#define ixDPM_TABLE_294 0x3f494 +#define ixDPM_TABLE_295 0x3f498 +#define ixDPM_TABLE_296 0x3f49c +#define ixDPM_TABLE_297 0x3f4a0 +#define ixDPM_TABLE_298 0x3f4a4 +#define ixDPM_TABLE_299 0x3f4a8 +#define ixDPM_TABLE_300 0x3f4ac +#define ixDPM_TABLE_301 0x3f4b0 +#define ixDPM_TABLE_302 0x3f4b4 +#define ixDPM_TABLE_303 0x3f4b8 +#define ixDPM_TABLE_304 0x3f4bc +#define ixDPM_TABLE_305 0x3f4c0 +#define ixDPM_TABLE_306 0x3f4c4 +#define ixDPM_TABLE_307 0x3f4c8 +#define ixDPM_TABLE_308 0x3f4cc +#define ixDPM_TABLE_309 0x3f4d0 +#define ixDPM_TABLE_310 0x3f4d4 +#define ixDPM_TABLE_311 0x3f4d8 +#define ixDPM_TABLE_312 0x3f4dc +#define ixDPM_TABLE_313 0x3f4e0 +#define ixDPM_TABLE_314 0x3f4e4 +#define ixDPM_TABLE_315 0x3f4e8 +#define ixDPM_TABLE_316 0x3f4ec +#define ixDPM_TABLE_317 0x3f4f0 +#define ixDPM_TABLE_318 0x3f4f4 +#define ixDPM_TABLE_319 0x3f4f8 +#define ixDPM_TABLE_320 0x3f4fc +#define ixDPM_TABLE_321 0x3f500 +#define ixDPM_TABLE_322 0x3f504 +#define ixDPM_TABLE_323 0x3f508 +#define ixDPM_TABLE_324 0x3f50c +#define ixDPM_TABLE_325 0x3f510 +#define ixDPM_TABLE_326 0x3f514 +#define ixDPM_TABLE_327 0x3f518 +#define ixDPM_TABLE_328 0x3f51c +#define ixDPM_TABLE_329 0x3f520 +#define ixDPM_TABLE_330 0x3f524 +#define ixDPM_TABLE_331 0x3f528 +#define ixDPM_TABLE_332 0x3f52c +#define ixDPM_TABLE_333 0x3f530 +#define ixDPM_TABLE_334 0x3f534 +#define ixDPM_TABLE_335 0x3f538 +#define ixDPM_TABLE_336 0x3f53c +#define ixDPM_TABLE_337 0x3f540 +#define ixDPM_TABLE_338 0x3f544 +#define ixDPM_TABLE_339 0x3f548 +#define ixDPM_TABLE_340 0x3f54c +#define ixDPM_TABLE_341 0x3f550 +#define ixDPM_TABLE_342 0x3f554 +#define ixDPM_TABLE_343 0x3f558 +#define ixDPM_TABLE_344 0x3f55c +#define ixDPM_TABLE_345 0x3f560 +#define ixDPM_TABLE_346 0x3f564 +#define ixDPM_TABLE_347 0x3f568 +#define ixDPM_TABLE_348 0x3f56c +#define ixDPM_TABLE_349 0x3f570 +#define ixDPM_TABLE_350 0x3f574 +#define ixDPM_TABLE_351 0x3f578 +#define ixDPM_TABLE_352 0x3f57c +#define ixDPM_TABLE_353 0x3f580 +#define ixDPM_TABLE_354 0x3f584 +#define ixDPM_TABLE_355 0x3f588 +#define ixDPM_TABLE_356 0x3f58c +#define ixDPM_TABLE_357 0x3f590 +#define ixDPM_TABLE_358 0x3f594 +#define ixDPM_TABLE_359 0x3f598 +#define ixDPM_TABLE_360 0x3f59c +#define ixDPM_TABLE_361 0x3f5a0 +#define ixDPM_TABLE_362 0x3f5a4 +#define ixDPM_TABLE_363 0x3f5a8 +#define ixDPM_TABLE_364 0x3f5ac +#define ixDPM_TABLE_365 0x3f5b0 +#define ixDPM_TABLE_366 0x3f5b4 +#define ixDPM_TABLE_367 0x3f5b8 +#define ixDPM_TABLE_368 0x3f5bc +#define ixDPM_TABLE_369 0x3f5c0 +#define ixDPM_TABLE_370 0x3f5c4 +#define ixDPM_TABLE_371 0x3f5c8 +#define ixDPM_TABLE_372 0x3f5cc +#define ixDPM_TABLE_373 0x3f5d0 +#define ixDPM_TABLE_374 0x3f5d4 +#define ixDPM_TABLE_375 0x3f5d8 +#define ixDPM_TABLE_376 0x3f5dc +#define ixDPM_TABLE_377 0x3f5e0 +#define ixDPM_TABLE_378 0x3f5e4 +#define ixDPM_TABLE_379 0x3f5e8 +#define ixDPM_TABLE_380 0x3f5ec +#define ixDPM_TABLE_381 0x3f5f0 +#define ixDPM_TABLE_382 0x3f5f4 +#define ixDPM_TABLE_383 0x3f5f8 +#define ixDPM_TABLE_384 0x3f5fc +#define ixDPM_TABLE_385 0x3f600 +#define ixDPM_TABLE_386 0x3f604 +#define ixDPM_TABLE_387 0x3f608 +#define ixDPM_TABLE_388 0x3f60c +#define ixDPM_TABLE_389 0x3f610 +#define ixDPM_TABLE_390 0x3f614 +#define ixDPM_TABLE_391 0x3f618 +#define ixDPM_TABLE_392 0x3f61c +#define ixDPM_TABLE_393 0x3f620 +#define ixDPM_TABLE_394 0x3f624 +#define ixDPM_TABLE_395 0x3f628 +#define ixDPM_TABLE_396 0x3f62c +#define ixDPM_TABLE_397 0x3f630 +#define ixDPM_TABLE_398 0x3f634 +#define ixDPM_TABLE_399 0x3f638 +#define ixDPM_TABLE_400 0x3f63c +#define ixDPM_TABLE_401 0x3f640 +#define ixDPM_TABLE_402 0x3f644 +#define ixDPM_TABLE_403 0x3f648 +#define ixDPM_TABLE_404 0x3f64c +#define ixDPM_TABLE_405 0x3f650 +#define ixDPM_TABLE_406 0x3f654 +#define ixDPM_TABLE_407 0x3f658 +#define ixDPM_TABLE_408 0x3f65c +#define ixDPM_TABLE_409 0x3f660 +#define ixDPM_TABLE_410 0x3f664 +#define ixDPM_TABLE_411 0x3f668 +#define ixDPM_TABLE_412 0x3f66c +#define ixDPM_TABLE_413 0x3f670 +#define ixDPM_TABLE_414 0x3f674 +#define ixDPM_TABLE_415 0x3f678 +#define ixDPM_TABLE_416 0x3f67c +#define ixDPM_TABLE_417 0x3f680 +#define ixDPM_TABLE_418 0x3f684 +#define ixDPM_TABLE_419 0x3f688 +#define ixDPM_TABLE_420 0x3f68c +#define ixDPM_TABLE_421 0x3f690 +#define ixDPM_TABLE_422 0x3f694 +#define ixDPM_TABLE_423 0x3f698 +#define ixDPM_TABLE_424 0x3f69c +#define ixDPM_TABLE_425 0x3f6a0 +#define ixDPM_TABLE_426 0x3f6a4 +#define ixDPM_TABLE_427 0x3f6a8 +#define ixDPM_TABLE_428 0x3f6ac +#define ixDPM_TABLE_429 0x3f6b0 +#define ixDPM_TABLE_430 0x3f6b4 +#define ixDPM_TABLE_431 0x3f6b8 +#define ixDPM_TABLE_432 0x3f6bc +#define ixDPM_TABLE_433 0x3f6c0 +#define ixDPM_TABLE_434 0x3f6c4 +#define ixDPM_TABLE_435 0x3f6c8 +#define ixDPM_TABLE_436 0x3f6cc +#define ixDPM_TABLE_437 0x3f6d0 +#define ixDPM_TABLE_438 0x3f6d4 +#define ixDPM_TABLE_439 0x3f6d8 +#define ixDPM_TABLE_440 0x3f6dc +#define ixDPM_TABLE_441 0x3f6e0 +#define ixDPM_TABLE_442 0x3f6e4 +#define ixDPM_TABLE_443 0x3f6e8 +#define ixDPM_TABLE_444 0x3f6ec +#define ixDPM_TABLE_445 0x3f6f0 +#define ixDPM_TABLE_446 0x3f6f4 +#define ixDPM_TABLE_447 0x3f6f8 +#define ixDPM_TABLE_448 0x3f6fc +#define ixDPM_TABLE_449 0x3f700 +#define ixDPM_TABLE_450 0x3f704 +#define ixDPM_TABLE_451 0x3f708 +#define ixDPM_TABLE_452 0x3f70c +#define ixDPM_TABLE_453 0x3f710 +#define ixDPM_TABLE_454 0x3f714 +#define ixDPM_TABLE_455 0x3f718 +#define ixDPM_TABLE_456 0x3f71c +#define ixDPM_TABLE_457 0x3f720 +#define ixDPM_TABLE_458 0x3f724 +#define ixDPM_TABLE_459 0x3f728 +#define ixDPM_TABLE_460 0x3f72c +#define ixDPM_TABLE_461 0x3f730 +#define ixDPM_TABLE_462 0x3f734 +#define ixDPM_TABLE_463 0x3f738 +#define ixDPM_TABLE_464 0x3f73c +#define ixDPM_TABLE_465 0x3f740 +#define ixDPM_TABLE_466 0x3f744 +#define ixDPM_TABLE_467 0x3f748 +#define ixDPM_TABLE_468 0x3f74c +#define ixDPM_TABLE_469 0x3f750 +#define ixDPM_TABLE_470 0x3f754 +#define ixDPM_TABLE_471 0x3f758 +#define ixDPM_TABLE_472 0x3f75c +#define ixDPM_TABLE_473 0x3f760 +#define ixDPM_TABLE_474 0x3f764 +#define ixDPM_TABLE_475 0x3f768 +#define ixDPM_TABLE_476 0x3f76c +#define ixDPM_TABLE_477 0x3f770 +#define ixDPM_TABLE_478 0x3f774 +#define ixDPM_TABLE_479 0x3f778 +#define ixDPM_TABLE_480 0x3f77c +#define ixDPM_TABLE_481 0x3f780 +#define ixDPM_TABLE_482 0x3f784 +#define ixDPM_TABLE_483 0x3f788 +#define ixDPM_TABLE_484 0x3f78c +#define ixDPM_TABLE_485 0x3f790 +#define ixDPM_TABLE_486 0x3f794 +#define ixDPM_TABLE_487 0x3f798 +#define ixDPM_TABLE_488 0x3f79c +#define ixDPM_TABLE_489 0x3f7a0 +#define ixDPM_TABLE_490 0x3f7a4 +#define ixDPM_TABLE_491 0x3f7a8 +#define ixDPM_TABLE_492 0x3f7ac +#define ixDPM_TABLE_493 0x3f7b0 +#define ixDPM_TABLE_494 0x3f7b4 +#define ixDPM_TABLE_495 0x3f7b8 +#define ixDPM_TABLE_496 0x3f7bc +#define ixDPM_TABLE_497 0x3f7c0 +#define ixDPM_TABLE_498 0x3f7c4 +#define ixDPM_TABLE_499 0x3f7c8 +#define ixDPM_TABLE_500 0x3f7cc +#define ixDPM_TABLE_501 0x3f7d0 +#define ixDPM_TABLE_502 0x3f7d4 +#define ixDPM_TABLE_503 0x3f7d8 +#define ixDPM_TABLE_504 0x3f7dc +#define ixDPM_TABLE_505 0x3f7e0 +#define ixDPM_TABLE_506 0x3f7e4 +#define ixFIRMWARE_FLAGS 0x3f800 +#define ixTDC_STATUS 0x3f808 +#define ixTDC_MV_AVERAGE 0x3f80c +#define ixTDC_VRM_LIMIT 0x3f810 +#define ixFEATURE_STATUS 0x3f818 +#define ixENTITY_TEMPERATURES_1 0x3f81c +#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f900 +#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f904 +#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f908 +#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f90c +#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f910 +#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f914 +#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f918 +#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f91c +#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f920 +#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f924 +#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f928 +#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f92c +#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f930 +#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f934 +#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f938 +#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f93c +#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f940 +#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f944 +#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f948 +#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f94c +#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f950 +#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f954 +#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f958 +#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f95c +#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f960 +#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f964 +#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f968 +#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f96c +#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f970 +#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f974 +#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f978 +#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f97c +#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f980 +#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f984 +#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f988 +#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f98c +#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f990 +#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f994 +#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f998 +#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f99c +#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f9a0 +#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f9a4 +#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f9a8 +#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f9ac +#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f9b0 +#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f9b4 +#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f9b8 +#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f9bc +#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f9c0 +#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f9c4 +#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f9c8 +#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f9cc +#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f9d0 +#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f9d4 +#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f9d8 +#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f9dc +#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f9e0 +#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f9e4 +#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f9e8 +#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f9ec +#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f9f0 +#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f9f4 +#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f9f8 +#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f9fc +#define ixMCARB_DRAM_TIMING_TABLE_65 0x3fa00 +#define ixMCARB_DRAM_TIMING_TABLE_66 0x3fa04 +#define ixMCARB_DRAM_TIMING_TABLE_67 0x3fa08 +#define ixMCARB_DRAM_TIMING_TABLE_68 0x3fa0c +#define ixMCARB_DRAM_TIMING_TABLE_69 0x3fa10 +#define ixMCARB_DRAM_TIMING_TABLE_70 0x3fa14 +#define ixMCARB_DRAM_TIMING_TABLE_71 0x3fa18 +#define ixMCARB_DRAM_TIMING_TABLE_72 0x3fa1c +#define ixMCARB_DRAM_TIMING_TABLE_73 0x3fa20 +#define ixMCARB_DRAM_TIMING_TABLE_74 0x3fa24 +#define ixMCARB_DRAM_TIMING_TABLE_75 0x3fa28 +#define ixMCARB_DRAM_TIMING_TABLE_76 0x3fa2c +#define ixMCARB_DRAM_TIMING_TABLE_77 0x3fa30 +#define ixMCARB_DRAM_TIMING_TABLE_78 0x3fa34 +#define ixMCARB_DRAM_TIMING_TABLE_79 0x3fa38 +#define ixMCARB_DRAM_TIMING_TABLE_80 0x3fa3c +#define ixMCARB_DRAM_TIMING_TABLE_81 0x3fa40 +#define ixMCARB_DRAM_TIMING_TABLE_82 0x3fa44 +#define ixMCARB_DRAM_TIMING_TABLE_83 0x3fa48 +#define ixMCARB_DRAM_TIMING_TABLE_84 0x3fa4c +#define ixMCARB_DRAM_TIMING_TABLE_85 0x3fa50 +#define ixMCARB_DRAM_TIMING_TABLE_86 0x3fa54 +#define ixMCARB_DRAM_TIMING_TABLE_87 0x3fa58 +#define ixMCARB_DRAM_TIMING_TABLE_88 0x3fa5c +#define ixMCARB_DRAM_TIMING_TABLE_89 0x3fa60 +#define ixMCARB_DRAM_TIMING_TABLE_90 0x3fa64 +#define ixMCARB_DRAM_TIMING_TABLE_91 0x3fa68 +#define ixMCARB_DRAM_TIMING_TABLE_92 0x3fa6c +#define ixMCARB_DRAM_TIMING_TABLE_93 0x3fa70 +#define ixMCARB_DRAM_TIMING_TABLE_94 0x3fa74 +#define ixMCARB_DRAM_TIMING_TABLE_95 0x3fa78 +#define ixMCARB_DRAM_TIMING_TABLE_96 0x3fa7c +#define ixMCARB_DRAM_TIMING_TABLE_97 0x3fa80 +#define ixMCARB_DRAM_TIMING_TABLE_98 0x3fa84 +#define ixMCARB_DRAM_TIMING_TABLE_99 0x3fa88 +#define ixMCARB_DRAM_TIMING_TABLE_100 0x3fa8c +#define ixMCARB_DRAM_TIMING_TABLE_101 0x3fa90 +#define ixMCARB_DRAM_TIMING_TABLE_102 0x3fa94 +#define ixMCARB_DRAM_TIMING_TABLE_103 0x3fa98 +#define ixMCARB_DRAM_TIMING_TABLE_104 0x3fa9c +#define ixMCARB_DRAM_TIMING_TABLE_105 0x3faa0 +#define ixMCARB_DRAM_TIMING_TABLE_106 0x3faa4 +#define ixMCARB_DRAM_TIMING_TABLE_107 0x3faa8 +#define ixMCARB_DRAM_TIMING_TABLE_108 0x3faac +#define ixMCARB_DRAM_TIMING_TABLE_109 0x3fab0 +#define ixMCARB_DRAM_TIMING_TABLE_110 0x3fab4 +#define ixMCARB_DRAM_TIMING_TABLE_111 0x3fab8 +#define ixMCARB_DRAM_TIMING_TABLE_112 0x3fabc +#define ixMCARB_DRAM_TIMING_TABLE_113 0x3fac0 +#define ixMCARB_DRAM_TIMING_TABLE_114 0x3fac4 +#define ixMCARB_DRAM_TIMING_TABLE_115 0x3fac8 +#define ixMCARB_DRAM_TIMING_TABLE_116 0x3facc +#define ixMCARB_DRAM_TIMING_TABLE_117 0x3fad0 +#define ixMCARB_DRAM_TIMING_TABLE_118 0x3fad4 +#define ixMCARB_DRAM_TIMING_TABLE_119 0x3fad8 +#define ixMCARB_DRAM_TIMING_TABLE_120 0x3fadc +#define ixMCARB_DRAM_TIMING_TABLE_121 0x3fae0 +#define ixMCARB_DRAM_TIMING_TABLE_122 0x3fae4 +#define ixMCARB_DRAM_TIMING_TABLE_123 0x3fae8 +#define ixMCARB_DRAM_TIMING_TABLE_124 0x3faec +#define ixMCARB_DRAM_TIMING_TABLE_125 0x3faf0 +#define ixMCARB_DRAM_TIMING_TABLE_126 0x3faf4 +#define ixMCARB_DRAM_TIMING_TABLE_127 0x3faf8 +#define ixMCARB_DRAM_TIMING_TABLE_128 0x3fafc +#define ixMCARB_DRAM_TIMING_TABLE_129 0x3fb00 +#define ixMCARB_DRAM_TIMING_TABLE_130 0x3fb04 +#define ixMCARB_DRAM_TIMING_TABLE_131 0x3fb08 +#define ixMCARB_DRAM_TIMING_TABLE_132 0x3fb0c +#define ixMCARB_DRAM_TIMING_TABLE_133 0x3fb10 +#define ixMCARB_DRAM_TIMING_TABLE_134 0x3fb14 +#define ixMCARB_DRAM_TIMING_TABLE_135 0x3fb18 +#define ixMCARB_DRAM_TIMING_TABLE_136 0x3fb1c +#define ixMCARB_DRAM_TIMING_TABLE_137 0x3fb20 +#define ixMCARB_DRAM_TIMING_TABLE_138 0x3fb24 +#define ixMCARB_DRAM_TIMING_TABLE_139 0x3fb28 +#define ixMCARB_DRAM_TIMING_TABLE_140 0x3fb2c +#define ixMCARB_DRAM_TIMING_TABLE_141 0x3fb30 +#define ixMCARB_DRAM_TIMING_TABLE_142 0x3fb34 +#define ixMCARB_DRAM_TIMING_TABLE_143 0x3fb38 +#define ixMCARB_DRAM_TIMING_TABLE_144 0x3fb3c +#define ixMC_REGISTERS_TABLE_1 0x3fb40 +#define ixMC_REGISTERS_TABLE_2 0x3fb44 +#define ixMC_REGISTERS_TABLE_3 0x3fb48 +#define ixMC_REGISTERS_TABLE_4 0x3fb4c +#define ixMC_REGISTERS_TABLE_5 0x3fb50 +#define ixMC_REGISTERS_TABLE_6 0x3fb54 +#define ixMC_REGISTERS_TABLE_7 0x3fb58 +#define ixMC_REGISTERS_TABLE_8 0x3fb5c +#define ixMC_REGISTERS_TABLE_9 0x3fb60 +#define ixMC_REGISTERS_TABLE_10 0x3fb64 +#define ixMC_REGISTERS_TABLE_11 0x3fb68 +#define ixMC_REGISTERS_TABLE_12 0x3fb6c +#define ixMC_REGISTERS_TABLE_13 0x3fb70 +#define ixMC_REGISTERS_TABLE_14 0x3fb74 +#define ixMC_REGISTERS_TABLE_15 0x3fb78 +#define ixMC_REGISTERS_TABLE_16 0x3fb7c +#define ixMC_REGISTERS_TABLE_17 0x3fb80 +#define ixMC_REGISTERS_TABLE_18 0x3fb84 +#define ixMC_REGISTERS_TABLE_19 0x3fb88 +#define ixMC_REGISTERS_TABLE_20 0x3fb8c +#define ixMC_REGISTERS_TABLE_21 0x3fb90 +#define ixMC_REGISTERS_TABLE_22 0x3fb94 +#define ixMC_REGISTERS_TABLE_23 0x3fb98 +#define ixMC_REGISTERS_TABLE_24 0x3fb9c +#define ixMC_REGISTERS_TABLE_25 0x3fba0 +#define ixMC_REGISTERS_TABLE_26 0x3fba4 +#define ixMC_REGISTERS_TABLE_27 0x3fba8 +#define ixMC_REGISTERS_TABLE_28 0x3fbac +#define ixMC_REGISTERS_TABLE_29 0x3fbb0 +#define ixMC_REGISTERS_TABLE_30 0x3fbb4 +#define ixMC_REGISTERS_TABLE_31 0x3fbb8 +#define ixMC_REGISTERS_TABLE_32 0x3fbbc +#define ixMC_REGISTERS_TABLE_33 0x3fbc0 +#define ixMC_REGISTERS_TABLE_34 0x3fbc4 +#define ixMC_REGISTERS_TABLE_35 0x3fbc8 +#define ixMC_REGISTERS_TABLE_36 0x3fbcc +#define ixMC_REGISTERS_TABLE_37 0x3fbd0 +#define ixMC_REGISTERS_TABLE_38 0x3fbd4 +#define ixMC_REGISTERS_TABLE_39 0x3fbd8 +#define ixMC_REGISTERS_TABLE_40 0x3fbdc +#define ixMC_REGISTERS_TABLE_41 0x3fbe0 +#define ixMC_REGISTERS_TABLE_42 0x3fbe4 +#define ixMC_REGISTERS_TABLE_43 0x3fbe8 +#define ixMC_REGISTERS_TABLE_44 0x3fbec +#define ixMC_REGISTERS_TABLE_45 0x3fbf0 +#define ixMC_REGISTERS_TABLE_46 0x3fbf4 +#define ixMC_REGISTERS_TABLE_47 0x3fbf8 +#define ixMC_REGISTERS_TABLE_48 0x3fbfc +#define ixMC_REGISTERS_TABLE_49 0x3fc00 +#define ixMC_REGISTERS_TABLE_50 0x3fc04 +#define ixMC_REGISTERS_TABLE_51 0x3fc08 +#define ixMC_REGISTERS_TABLE_52 0x3fc0c +#define ixMC_REGISTERS_TABLE_53 0x3fc10 +#define ixMC_REGISTERS_TABLE_54 0x3fc14 +#define ixMC_REGISTERS_TABLE_55 0x3fc18 +#define ixMC_REGISTERS_TABLE_56 0x3fc1c +#define ixMC_REGISTERS_TABLE_57 0x3fc20 +#define ixMC_REGISTERS_TABLE_58 0x3fc24 +#define ixMC_REGISTERS_TABLE_59 0x3fc28 +#define ixMC_REGISTERS_TABLE_60 0x3fc2c +#define ixMC_REGISTERS_TABLE_61 0x3fc30 +#define ixMC_REGISTERS_TABLE_62 0x3fc34 +#define ixMC_REGISTERS_TABLE_63 0x3fc38 +#define ixMC_REGISTERS_TABLE_64 0x3fc3c +#define ixMC_REGISTERS_TABLE_65 0x3fc40 +#define ixMC_REGISTERS_TABLE_66 0x3fc44 +#define ixMC_REGISTERS_TABLE_67 0x3fc48 +#define ixMC_REGISTERS_TABLE_68 0x3fc4c +#define ixMC_REGISTERS_TABLE_69 0x3fc50 +#define ixMC_REGISTERS_TABLE_70 0x3fc54 +#define ixMC_REGISTERS_TABLE_71 0x3fc58 +#define ixMC_REGISTERS_TABLE_72 0x3fc5c +#define ixMC_REGISTERS_TABLE_73 0x3fc60 +#define ixMC_REGISTERS_TABLE_74 0x3fc64 +#define ixMC_REGISTERS_TABLE_75 0x3fc68 +#define ixMC_REGISTERS_TABLE_76 0x3fc6c +#define ixMC_REGISTERS_TABLE_77 0x3fc70 +#define ixMC_REGISTERS_TABLE_78 0x3fc74 +#define ixMC_REGISTERS_TABLE_79 0x3fc78 +#define ixMC_REGISTERS_TABLE_80 0x3fc7c +#define ixMC_REGISTERS_TABLE_81 0x3fc80 +#define ixMC_REGISTERS_TABLE_82 0x3fc84 +#define ixMC_REGISTERS_TABLE_83 0x3fc88 +#define ixMC_REGISTERS_TABLE_84 0x3fc8c +#define ixMC_REGISTERS_TABLE_85 0x3fc90 +#define ixMC_REGISTERS_TABLE_86 0x3fc94 +#define ixMC_REGISTERS_TABLE_87 0x3fc98 +#define ixMC_REGISTERS_TABLE_88 0x3fc9c +#define ixMC_REGISTERS_TABLE_89 0x3fca0 +#define ixMC_REGISTERS_TABLE_90 0x3fca4 +#define ixMC_REGISTERS_TABLE_91 0x3fca8 +#define ixMC_REGISTERS_TABLE_92 0x3fcac +#define ixMC_REGISTERS_TABLE_93 0x3fcb0 +#define ixMC_REGISTERS_TABLE_94 0x3fcb4 +#define ixMC_REGISTERS_TABLE_95 0x3fcb8 +#define ixMC_REGISTERS_TABLE_96 0x3fcbc +#define ixMC_REGISTERS_TABLE_97 0x3fcc0 +#define ixMC_REGISTERS_TABLE_98 0x3fcc4 +#define ixMC_REGISTERS_TABLE_99 0x3fcc8 +#define ixMC_REGISTERS_TABLE_100 0x3fccc +#define ixMC_REGISTERS_TABLE_101 0x3fcd0 +#define ixMC_REGISTERS_TABLE_102 0x3fcd4 +#define ixMC_REGISTERS_TABLE_103 0x3fcd8 +#define ixMC_REGISTERS_TABLE_104 0x3fcdc +#define ixMC_REGISTERS_TABLE_105 0x3fce0 +#define ixMC_REGISTERS_TABLE_106 0x3fce4 +#define ixMC_REGISTERS_TABLE_107 0x3fce8 +#define ixMC_REGISTERS_TABLE_108 0x3fcec +#define ixMC_REGISTERS_TABLE_109 0x3fcf0 +#define ixMC_REGISTERS_TABLE_110 0x3fcf4 +#define ixMC_REGISTERS_TABLE_111 0x3fcf8 +#define ixMC_REGISTERS_TABLE_112 0x3fcfc +#define ixMC_REGISTERS_TABLE_113 0x3fd00 +#define ixFAN_TABLE_1 0x3fd04 +#define ixFAN_TABLE_2 0x3fd08 +#define ixFAN_TABLE_3 0x3fd0c +#define ixFAN_TABLE_4 0x3fd10 +#define ixFAN_TABLE_5 0x3fd14 +#define ixFAN_TABLE_6 0x3fd18 +#define ixFAN_TABLE_7 0x3fd1c +#define ixFAN_TABLE_8 0x3fd20 +#define ixFAN_TABLE_9 0x3fd24 +#define ixSOFT_REGISTERS_TABLE_1 0x3fd28 +#define ixSOFT_REGISTERS_TABLE_2 0x3fd2c +#define ixSOFT_REGISTERS_TABLE_3 0x3fd30 +#define ixSOFT_REGISTERS_TABLE_4 0x3fd34 +#define ixSOFT_REGISTERS_TABLE_5 0x3fd38 +#define ixSOFT_REGISTERS_TABLE_6 0x3fd3c +#define ixSOFT_REGISTERS_TABLE_7 0x3fd40 +#define ixSOFT_REGISTERS_TABLE_8 0x3fd44 +#define ixSOFT_REGISTERS_TABLE_9 0x3fd48 +#define ixSOFT_REGISTERS_TABLE_10 0x3fd4c +#define ixSOFT_REGISTERS_TABLE_11 0x3fd50 +#define ixSOFT_REGISTERS_TABLE_12 0x3fd54 +#define ixSOFT_REGISTERS_TABLE_13 0x3fd58 +#define ixSOFT_REGISTERS_TABLE_14 0x3fd5c +#define ixSOFT_REGISTERS_TABLE_15 0x3fd60 +#define ixSOFT_REGISTERS_TABLE_16 0x3fd64 +#define ixSOFT_REGISTERS_TABLE_17 0x3fd68 +#define ixSOFT_REGISTERS_TABLE_18 0x3fd6c +#define ixSOFT_REGISTERS_TABLE_19 0x3fd70 +#define ixSOFT_REGISTERS_TABLE_20 0x3fd74 +#define ixSOFT_REGISTERS_TABLE_21 0x3fd78 +#define ixSOFT_REGISTERS_TABLE_22 0x3fd7c +#define ixSOFT_REGISTERS_TABLE_23 0x3fd80 +#define ixSOFT_REGISTERS_TABLE_24 0x3fd84 +#define ixSOFT_REGISTERS_TABLE_25 0x3fd88 +#define ixSOFT_REGISTERS_TABLE_26 0x3fd8c +#define ixSOFT_REGISTERS_TABLE_27 0x3fd90 +#define ixSOFT_REGISTERS_TABLE_28 0x3fd94 +#define ixSOFT_REGISTERS_TABLE_29 0x3fd98 +#define ixSOFT_REGISTERS_TABLE_30 0x3fd9c +#define ixPM_FUSES_1 0x3fda0 +#define ixPM_FUSES_2 0x3fda4 +#define ixPM_FUSES_3 0x3fda8 +#define ixPM_FUSES_4 0x3fdac +#define ixPM_FUSES_5 0x3fdb0 +#define ixPM_FUSES_6 0x3fdb4 +#define ixPM_FUSES_7 0x3fdb8 +#define ixPM_FUSES_8 0x3fdbc +#define ixPM_FUSES_9 0x3fdc0 +#define ixPM_FUSES_10 0x3fdc4 +#define ixPM_FUSES_11 0x3fdc8 +#define ixPM_FUSES_12 0x3fdcc +#define ixPM_FUSES_13 0x3fdd0 +#define ixPM_FUSES_14 0x3fdd4 +#define ixPM_FUSES_15 0x3fdd8 +#define ixPM_FUSES_16 0x3fddc +#define ixPM_FUSES_17 0x3fde0 +#define ixPM_FUSES_18 0x3fde4 +#define ixPM_FUSES_19 0x3fde8 +#define ixSMU_PM_STATUS_0 0x3fe00 +#define ixSMU_PM_STATUS_1 0x3fe04 +#define ixSMU_PM_STATUS_2 0x3fe08 +#define ixSMU_PM_STATUS_3 0x3fe0c +#define ixSMU_PM_STATUS_4 0x3fe10 +#define ixSMU_PM_STATUS_5 0x3fe14 +#define ixSMU_PM_STATUS_6 0x3fe18 +#define ixSMU_PM_STATUS_7 0x3fe1c +#define ixSMU_PM_STATUS_8 0x3fe20 +#define ixSMU_PM_STATUS_9 0x3fe24 +#define ixSMU_PM_STATUS_10 0x3fe28 +#define ixSMU_PM_STATUS_11 0x3fe2c +#define ixSMU_PM_STATUS_12 0x3fe30 +#define ixSMU_PM_STATUS_13 0x3fe34 +#define ixSMU_PM_STATUS_14 0x3fe38 +#define ixSMU_PM_STATUS_15 0x3fe3c +#define ixSMU_PM_STATUS_16 0x3fe40 +#define ixSMU_PM_STATUS_17 0x3fe44 +#define ixSMU_PM_STATUS_18 0x3fe48 +#define ixSMU_PM_STATUS_19 0x3fe4c +#define ixSMU_PM_STATUS_20 0x3fe50 +#define ixSMU_PM_STATUS_21 0x3fe54 +#define ixSMU_PM_STATUS_22 0x3fe58 +#define ixSMU_PM_STATUS_23 0x3fe5c +#define ixSMU_PM_STATUS_24 0x3fe60 +#define ixSMU_PM_STATUS_25 0x3fe64 +#define ixSMU_PM_STATUS_26 0x3fe68 +#define ixSMU_PM_STATUS_27 0x3fe6c +#define ixSMU_PM_STATUS_28 0x3fe70 +#define ixSMU_PM_STATUS_29 0x3fe74 +#define ixSMU_PM_STATUS_30 0x3fe78 +#define ixSMU_PM_STATUS_31 0x3fe7c +#define ixSMU_PM_STATUS_32 0x3fe80 +#define ixSMU_PM_STATUS_33 0x3fe84 +#define ixSMU_PM_STATUS_34 0x3fe88 +#define ixSMU_PM_STATUS_35 0x3fe8c +#define ixSMU_PM_STATUS_36 0x3fe90 +#define ixSMU_PM_STATUS_37 0x3fe94 +#define ixSMU_PM_STATUS_38 0x3fe98 +#define ixSMU_PM_STATUS_39 0x3fe9c +#define ixSMU_PM_STATUS_40 0x3fea0 +#define ixSMU_PM_STATUS_41 0x3fea4 +#define ixSMU_PM_STATUS_42 0x3fea8 +#define ixSMU_PM_STATUS_43 0x3feac +#define ixSMU_PM_STATUS_44 0x3feb0 +#define ixSMU_PM_STATUS_45 0x3feb4 +#define ixSMU_PM_STATUS_46 0x3feb8 +#define ixSMU_PM_STATUS_47 0x3febc +#define ixSMU_PM_STATUS_48 0x3fec0 +#define ixSMU_PM_STATUS_49 0x3fec4 +#define ixSMU_PM_STATUS_50 0x3fec8 +#define ixSMU_PM_STATUS_51 0x3fecc +#define ixSMU_PM_STATUS_52 0x3fed0 +#define ixSMU_PM_STATUS_53 0x3fed4 +#define ixSMU_PM_STATUS_54 0x3fed8 +#define ixSMU_PM_STATUS_55 0x3fedc +#define ixSMU_PM_STATUS_56 0x3fee0 +#define ixSMU_PM_STATUS_57 0x3fee4 +#define ixSMU_PM_STATUS_58 0x3fee8 +#define ixSMU_PM_STATUS_59 0x3feec +#define ixSMU_PM_STATUS_60 0x3fef0 +#define ixSMU_PM_STATUS_61 0x3fef4 +#define ixSMU_PM_STATUS_62 0x3fef8 +#define ixSMU_PM_STATUS_63 0x3fefc +#define ixSMU_PM_STATUS_64 0x3ff00 +#define ixSMU_PM_STATUS_65 0x3ff04 +#define ixSMU_PM_STATUS_66 0x3ff08 +#define ixSMU_PM_STATUS_67 0x3ff0c +#define ixSMU_PM_STATUS_68 0x3ff10 +#define ixSMU_PM_STATUS_69 0x3ff14 +#define ixSMU_PM_STATUS_70 0x3ff18 +#define ixSMU_PM_STATUS_71 0x3ff1c +#define ixSMU_PM_STATUS_72 0x3ff20 +#define ixSMU_PM_STATUS_73 0x3ff24 +#define ixSMU_PM_STATUS_74 0x3ff28 +#define ixSMU_PM_STATUS_75 0x3ff2c +#define ixSMU_PM_STATUS_76 0x3ff30 +#define ixSMU_PM_STATUS_77 0x3ff34 +#define ixSMU_PM_STATUS_78 0x3ff38 +#define ixSMU_PM_STATUS_79 0x3ff3c +#define ixSMU_PM_STATUS_80 0x3ff40 +#define ixSMU_PM_STATUS_81 0x3ff44 +#define ixSMU_PM_STATUS_82 0x3ff48 +#define ixSMU_PM_STATUS_83 0x3ff4c +#define ixSMU_PM_STATUS_84 0x3ff50 +#define ixSMU_PM_STATUS_85 0x3ff54 +#define ixSMU_PM_STATUS_86 0x3ff58 +#define ixSMU_PM_STATUS_87 0x3ff5c +#define ixSMU_PM_STATUS_88 0x3ff60 +#define ixSMU_PM_STATUS_89 0x3ff64 +#define ixSMU_PM_STATUS_90 0x3ff68 +#define ixSMU_PM_STATUS_91 0x3ff6c +#define ixSMU_PM_STATUS_92 0x3ff70 +#define ixSMU_PM_STATUS_93 0x3ff74 +#define ixSMU_PM_STATUS_94 0x3ff78 +#define ixSMU_PM_STATUS_95 0x3ff7c +#define ixSMU_PM_STATUS_96 0x3ff80 +#define ixSMU_PM_STATUS_97 0x3ff84 +#define ixSMU_PM_STATUS_98 0x3ff88 +#define ixSMU_PM_STATUS_99 0x3ff8c +#define ixSMU_PM_STATUS_100 0x3ff90 +#define ixSMU_PM_STATUS_101 0x3ff94 +#define ixSMU_PM_STATUS_102 0x3ff98 +#define ixSMU_PM_STATUS_103 0x3ff9c +#define ixSMU_PM_STATUS_104 0x3ffa0 +#define ixSMU_PM_STATUS_105 0x3ffa4 +#define ixSMU_PM_STATUS_106 0x3ffa8 +#define ixSMU_PM_STATUS_107 0x3ffac +#define ixSMU_PM_STATUS_108 0x3ffb0 +#define ixSMU_PM_STATUS_109 0x3ffb4 +#define ixSMU_PM_STATUS_110 0x3ffb8 +#define ixSMU_PM_STATUS_111 0x3ffbc +#define ixSMU_PM_STATUS_112 0x3ffc0 +#define ixSMU_PM_STATUS_113 0x3ffc4 +#define ixSMU_PM_STATUS_114 0x3ffc8 +#define ixSMU_PM_STATUS_115 0x3ffcc +#define ixSMU_PM_STATUS_116 0x3ffd0 +#define ixSMU_PM_STATUS_117 0x3ffd4 +#define ixSMU_PM_STATUS_118 0x3ffd8 +#define ixSMU_PM_STATUS_119 0x3ffdc +#define ixSMU_PM_STATUS_120 0x3ffe0 +#define ixSMU_PM_STATUS_121 0x3ffe4 +#define ixSMU_PM_STATUS_122 0x3ffe8 +#define ixSMU_PM_STATUS_123 0x3ffec +#define ixSMU_PM_STATUS_124 0x3fff0 +#define ixSMU_PM_STATUS_125 0x3fff4 +#define ixSMU_PM_STATUS_126 0x3fff8 +#define ixSMU_PM_STATUS_127 0x3fffc +#define ixCG_THERMAL_INT_ENA 0xc2100024 +#define ixCG_THERMAL_INT_CTRL 0xc2100028 +#define ixCG_THERMAL_INT_STATUS 0xc210002c +#define ixCG_THERMAL_CTRL 0xc0300004 +#define ixCG_THERMAL_STATUS 0xc0300008 +#define ixCG_THERMAL_INT 0xc030000c +#define ixCG_MULT_THERMAL_CTRL 0xc0300010 +#define ixCG_MULT_THERMAL_STATUS 0xc0300014 +#define ixCG_FDO_CTRL0 0xc0300064 +#define ixCG_FDO_CTRL1 0xc0300068 +#define ixCG_FDO_CTRL2 0xc030006c +#define ixCG_TACH_CTRL 0xc0300070 +#define ixCG_TACH_STATUS 0xc0300074 +#define ixCC_THM_STRAPS0 0xc0300080 +#define ixTHM_TMON0_RDIL0_DATA 0xc0300100 +#define ixTHM_TMON0_RDIL1_DATA 0xc0300104 +#define ixTHM_TMON0_RDIL2_DATA 0xc0300108 +#define ixTHM_TMON0_RDIL3_DATA 0xc030010c +#define ixTHM_TMON0_RDIL4_DATA 0xc0300110 +#define ixTHM_TMON0_RDIL5_DATA 0xc0300114 +#define ixTHM_TMON0_RDIL6_DATA 0xc0300118 +#define ixTHM_TMON0_RDIL7_DATA 0xc030011c +#define ixTHM_TMON0_RDIL8_DATA 0xc0300120 +#define ixTHM_TMON0_RDIL9_DATA 0xc0300124 +#define ixTHM_TMON0_RDIL10_DATA 0xc0300128 +#define ixTHM_TMON0_RDIL11_DATA 0xc030012c +#define ixTHM_TMON0_RDIL12_DATA 0xc0300130 +#define ixTHM_TMON0_RDIL13_DATA 0xc0300134 +#define ixTHM_TMON0_RDIL14_DATA 0xc0300138 +#define ixTHM_TMON0_RDIL15_DATA 0xc030013c +#define ixTHM_TMON0_RDIR0_DATA 0xc0300140 +#define ixTHM_TMON0_RDIR1_DATA 0xc0300144 +#define ixTHM_TMON0_RDIR2_DATA 0xc0300148 +#define ixTHM_TMON0_RDIR3_DATA 0xc030014c +#define ixTHM_TMON0_RDIR4_DATA 0xc0300150 +#define ixTHM_TMON0_RDIR5_DATA 0xc0300154 +#define ixTHM_TMON0_RDIR6_DATA 0xc0300158 +#define ixTHM_TMON0_RDIR7_DATA 0xc030015c +#define ixTHM_TMON0_RDIR8_DATA 0xc0300160 +#define ixTHM_TMON0_RDIR9_DATA 0xc0300164 +#define ixTHM_TMON0_RDIR10_DATA 0xc0300168 +#define ixTHM_TMON0_RDIR11_DATA 0xc030016c +#define ixTHM_TMON0_RDIR12_DATA 0xc0300170 +#define ixTHM_TMON0_RDIR13_DATA 0xc0300174 +#define ixTHM_TMON0_RDIR14_DATA 0xc0300178 +#define ixTHM_TMON0_RDIR15_DATA 0xc030017c +#define ixTHM_TMON1_RDIL0_DATA 0xc0300180 +#define ixTHM_TMON1_RDIL1_DATA 0xc0300184 +#define ixTHM_TMON1_RDIL2_DATA 0xc0300188 +#define ixTHM_TMON1_RDIL3_DATA 0xc030018c +#define ixTHM_TMON1_RDIL4_DATA 0xc0300190 +#define ixTHM_TMON1_RDIL5_DATA 0xc0300194 +#define ixTHM_TMON1_RDIL6_DATA 0xc0300198 +#define ixTHM_TMON1_RDIL7_DATA 0xc030019c +#define ixTHM_TMON1_RDIL8_DATA 0xc03001a0 +#define ixTHM_TMON1_RDIL9_DATA 0xc03001a4 +#define ixTHM_TMON1_RDIL10_DATA 0xc03001a8 +#define ixTHM_TMON1_RDIL11_DATA 0xc03001ac +#define ixTHM_TMON1_RDIL12_DATA 0xc03001b0 +#define ixTHM_TMON1_RDIL13_DATA 0xc03001b4 +#define ixTHM_TMON1_RDIL14_DATA 0xc03001b8 +#define ixTHM_TMON1_RDIL15_DATA 0xc03001bc +#define ixTHM_TMON1_RDIR0_DATA 0xc03001c0 +#define ixTHM_TMON1_RDIR1_DATA 0xc03001c4 +#define ixTHM_TMON1_RDIR2_DATA 0xc03001c8 +#define ixTHM_TMON1_RDIR3_DATA 0xc03001cc +#define ixTHM_TMON1_RDIR4_DATA 0xc03001d0 +#define ixTHM_TMON1_RDIR5_DATA 0xc03001d4 +#define ixTHM_TMON1_RDIR6_DATA 0xc03001d8 +#define ixTHM_TMON1_RDIR7_DATA 0xc03001dc +#define ixTHM_TMON1_RDIR8_DATA 0xc03001e0 +#define ixTHM_TMON1_RDIR9_DATA 0xc03001e4 +#define ixTHM_TMON1_RDIR10_DATA 0xc03001e8 +#define ixTHM_TMON1_RDIR11_DATA 0xc03001ec +#define ixTHM_TMON1_RDIR12_DATA 0xc03001f0 +#define ixTHM_TMON1_RDIR13_DATA 0xc03001f4 +#define ixTHM_TMON1_RDIR14_DATA 0xc03001f8 +#define ixTHM_TMON1_RDIR15_DATA 0xc03001fc +#define ixTHM_TMON0_INT_DATA 0xc0300300 +#define ixTHM_TMON1_INT_DATA 0xc0300304 +#define ixTHM_TMON0_DEBUG 0xc0300310 +#define ixTHM_TMON1_DEBUG 0xc0300314 +#define ixGENERAL_PWRMGT 0xc0200000 +#define ixCNB_PWRMGT_CNTL 0xc0200004 +#define ixSCLK_PWRMGT_CNTL 0xc0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 +#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 +#define ixPLL_TEST_CNTL 0xc020003c +#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 +#define ixCG_DISPLAY_GAP_CNTL 0xc0200060 +#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 +#define ixCG_ACPI_CNTL 0xc0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 +#define ixCG_ULV_PARAMETER 0xc020015c +#define ixSCLK_MIN_DIV 0xc0200308 +#define ixLCAC_SX0_CNTL 0xc0400d00 +#define ixLCAC_SX0_OVR_SEL 0xc0400d04 +#define ixLCAC_SX0_OVR_VAL 0xc0400d08 +#define ixLCAC_MC0_CNTL 0xc0400d30 +#define ixLCAC_MC0_OVR_SEL 0xc0400d34 +#define ixLCAC_MC0_OVR_VAL 0xc0400d38 +#define ixLCAC_MC1_CNTL 0xc0400d3c +#define ixLCAC_MC1_OVR_SEL 0xc0400d40 +#define ixLCAC_MC1_OVR_VAL 0xc0400d44 +#define ixLCAC_MC2_CNTL 0xc0400d48 +#define ixLCAC_MC2_OVR_SEL 0xc0400d4c +#define ixLCAC_MC2_OVR_VAL 0xc0400d50 +#define ixLCAC_MC3_CNTL 0xc0400d54 +#define ixLCAC_MC3_OVR_SEL 0xc0400d58 +#define ixLCAC_MC3_OVR_VAL 0xc0400d5c +#define ixLCAC_CPL_CNTL 0xc0400d80 +#define ixLCAC_CPL_OVR_SEL 0xc0400d84 +#define ixLCAC_CPL_OVR_VAL 0xc0400d88 +#define mmROM_SMC_IND_INDEX 0x80 +#define mmROM0_ROM_SMC_IND_INDEX 0x80 +#define mmROM1_ROM_SMC_IND_INDEX 0x82 +#define mmROM2_ROM_SMC_IND_INDEX 0x84 +#define mmROM3_ROM_SMC_IND_INDEX 0x86 +#define mmROM_SMC_IND_DATA 0x81 +#define mmROM0_ROM_SMC_IND_DATA 0x81 +#define mmROM1_ROM_SMC_IND_DATA 0x83 +#define mmROM2_ROM_SMC_IND_DATA 0x85 +#define mmROM3_ROM_SMC_IND_DATA 0x87 +#define ixROM_CNTL 0xc0600000 +#define ixPAGE_MIRROR_CNTL 0xc0600004 +#define ixROM_STATUS 0xc0600008 +#define ixCGTT_ROM_CLK_CTRL0 0xc060000c +#define ixROM_INDEX 0xc0600010 +#define ixROM_DATA 0xc0600014 +#define ixROM_START 0xc0600018 +#define ixROM_SW_CNTL 0xc060001c +#define ixROM_SW_STATUS 0xc0600020 +#define ixROM_SW_COMMAND 0xc0600024 +#define ixROM_SW_DATA_1 0xc0600028 +#define ixROM_SW_DATA_2 0xc060002c +#define ixROM_SW_DATA_3 0xc0600030 +#define ixROM_SW_DATA_4 0xc0600034 +#define ixROM_SW_DATA_5 0xc0600038 +#define ixROM_SW_DATA_6 0xc060003c +#define ixROM_SW_DATA_7 0xc0600040 +#define ixROM_SW_DATA_8 0xc0600044 +#define ixROM_SW_DATA_9 0xc0600048 +#define ixROM_SW_DATA_10 0xc060004c +#define ixROM_SW_DATA_11 0xc0600050 +#define ixROM_SW_DATA_12 0xc0600054 +#define ixROM_SW_DATA_13 0xc0600058 +#define ixROM_SW_DATA_14 0xc060005c +#define ixROM_SW_DATA_15 0xc0600060 +#define ixROM_SW_DATA_16 0xc0600064 +#define ixROM_SW_DATA_17 0xc0600068 +#define ixROM_SW_DATA_18 0xc060006c +#define ixROM_SW_DATA_19 0xc0600070 +#define ixROM_SW_DATA_20 0xc0600074 +#define ixROM_SW_DATA_21 0xc0600078 +#define ixROM_SW_DATA_22 0xc060007c +#define ixROM_SW_DATA_23 0xc0600080 +#define ixROM_SW_DATA_24 0xc0600084 +#define ixROM_SW_DATA_25 0xc0600088 +#define ixROM_SW_DATA_26 0xc060008c +#define ixROM_SW_DATA_27 0xc0600090 +#define ixROM_SW_DATA_28 0xc0600094 +#define ixROM_SW_DATA_29 0xc0600098 +#define ixROM_SW_DATA_30 0xc060009c +#define ixROM_SW_DATA_31 0xc06000a0 +#define ixROM_SW_DATA_32 0xc06000a4 +#define ixROM_SW_DATA_33 0xc06000a8 +#define ixROM_SW_DATA_34 0xc06000ac +#define ixROM_SW_DATA_35 0xc06000b0 +#define ixROM_SW_DATA_36 0xc06000b4 +#define ixROM_SW_DATA_37 0xc06000b8 +#define ixROM_SW_DATA_38 0xc06000bc +#define ixROM_SW_DATA_39 0xc06000c0 +#define ixROM_SW_DATA_40 0xc06000c4 +#define ixROM_SW_DATA_41 0xc06000c8 +#define ixROM_SW_DATA_42 0xc06000cc +#define ixROM_SW_DATA_43 0xc06000d0 +#define ixROM_SW_DATA_44 0xc06000d4 +#define ixROM_SW_DATA_45 0xc06000d8 +#define ixROM_SW_DATA_46 0xc06000dc +#define ixROM_SW_DATA_47 0xc06000e0 +#define ixROM_SW_DATA_48 0xc06000e4 +#define ixROM_SW_DATA_49 0xc06000e8 +#define ixROM_SW_DATA_50 0xc06000ec +#define ixROM_SW_DATA_51 0xc06000f0 +#define ixROM_SW_DATA_52 0xc06000f4 +#define ixROM_SW_DATA_53 0xc06000f8 +#define ixROM_SW_DATA_54 0xc06000fc +#define ixROM_SW_DATA_55 0xc0600100 +#define ixROM_SW_DATA_56 0xc0600104 +#define ixROM_SW_DATA_57 0xc0600108 +#define ixROM_SW_DATA_58 0xc060010c +#define ixROM_SW_DATA_59 0xc0600110 +#define ixROM_SW_DATA_60 0xc0600114 +#define ixROM_SW_DATA_61 0xc0600118 +#define ixROM_SW_DATA_62 0xc060011c +#define ixROM_SW_DATA_63 0xc0600120 +#define ixROM_SW_DATA_64 0xc0600124 + +#endif /* SMU_7_1_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h new file mode 100644 index 000000000000..61face1d0d8d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h @@ -0,0 +1,1191 @@ +/* + * SMU_7_1_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_0_ENUM_H +#define SMU_7_1_0_ENUM_H + +#define CG_SRBM_START_ADDR 0x600 +#define CG_SRBM_END_ADDR 0x8ff +#define RCU_CCF_DWORDS0 0x28 +#define RCU_CCF_BITS0 0x500 +#define RCU_CCF_DWORDS1 0x7f +#define RCU_CCF_BITS1 0x1000 +#define RCU_SAM_BYTES 0x40 +#define RCU_SAM_RTL_BYTES 0x40 +#define KEYS_CHAIN_ADR 0x0 +#define SAMU_KEY_SADR 0xa0 +#define SAMU_KEY_EADR 0xdf +#define RCU_SMU_BYTES 0x11 +#define RCU_SMU_RTL_BYTES 0x11 +#define SMC_MSG_TEST 0x1 +#define SMC_MSG_PHY_LN_OFF 0x2 +#define SMC_MSG_PHY_LN_ON 0x3 +#define SMC_MSG_DDI_PHY_OFF 0x4 +#define SMC_MSG_DDI_PHY_ON 0x5 +#define SMC_MSG_CASCADE_PLL_OFF 0x6 +#define SMC_MSG_CASCADE_PLL_ON 0x7 +#define SMC_MSG_PWR_OFF_x16 0x8 +#define SMC_MSG_CONFIG_LCLK_DPM 0x9 +#define SMC_MSG_FLUSH_DATA_CACHE 0xa +#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb +#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc +#define SMC_MSG_CONFIG_BAPM 0xd +#define SMC_MSG_CONFIG_TDC_LIMIT 0xe +#define SMC_MSG_CONFIG_LPMx 0xf +#define SMC_MSG_CONFIG_HTC_LIMIT 0x10 +#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11 +#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12 +#define SMC_MSG_CONFIG_TDP_CNTL 0x13 +#define SMC_MSG_EN_PM_CNTL 0x14 +#define SMC_MSG_DIS_PM_CNTL 0x15 +#define SMC_MSG_CONFIG_NBDPM 0x16 +#define SMC_MSG_CONFIG_LOADLINE 0x17 +#define SMC_MSG_ADJUST_LOADLINE 0x18 +#define SMC_MSG_RESET 0x20 +#define SMC_MSG_VOLTAGE 0x25 +#define SMC_VERSION_MAJOR 0x7 +#define SMC_VERSION_MINOR 0x0 +#define SMC_HEADER_SIZE 0x40 +#define ROM_SIGNATURE 0xaa55 +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, + ADDR_CONFIG_16_PIPE = 0x4, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_dco0 = 0x2, + DBG_CLIENT_BLKID_wd = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_scf2 = 0x5, + DBG_CLIENT_BLKID_spim3 = 0x6, + DBG_CLIENT_BLKID_cb3 = 0x7, + DBG_CLIENT_BLKID_sx0 = 0x8, + DBG_CLIENT_BLKID_cb2 = 0x9, + DBG_CLIENT_BLKID_bci1 = 0xa, + DBG_CLIENT_BLKID_xdma = 0xb, + DBG_CLIENT_BLKID_bci0 = 0xc, + DBG_CLIENT_BLKID_spim0 = 0xd, + DBG_CLIENT_BLKID_mcd0 = 0xe, + DBG_CLIENT_BLKID_mcc0 = 0xf, + DBG_CLIENT_BLKID_cb0 = 0x10, + DBG_CLIENT_BLKID_cb1 = 0x11, + DBG_CLIENT_BLKID_cpc_0 = 0x12, + DBG_CLIENT_BLKID_cpc_1 = 0x13, + DBG_CLIENT_BLKID_cpf = 0x14, + DBG_CLIENT_BLKID_rlc = 0x15, + DBG_CLIENT_BLKID_grbm = 0x16, + DBG_CLIENT_BLKID_bif = 0x17, + DBG_CLIENT_BLKID_scf1 = 0x18, + DBG_CLIENT_BLKID_sam = 0x19, + DBG_CLIENT_BLKID_mcd4 = 0x1a, + DBG_CLIENT_BLKID_mcc4 = 0x1b, + DBG_CLIENT_BLKID_gmcon = 0x1c, + DBG_CLIENT_BLKID_mcb = 0x1d, + DBG_CLIENT_BLKID_vgt0 = 0x1e, + DBG_CLIENT_BLKID_pc0 = 0x1f, + DBG_CLIENT_BLKID_spim1 = 0x20, + DBG_CLIENT_BLKID_bci2 = 0x21, + DBG_CLIENT_BLKID_mcd6 = 0x22, + DBG_CLIENT_BLKID_mcc6 = 0x23, + DBG_CLIENT_BLKID_mcd3 = 0x24, + DBG_CLIENT_BLKID_mcc3 = 0x25, + DBG_CLIENT_BLKID_uvdm_0 = 0x26, + DBG_CLIENT_BLKID_uvdm_1 = 0x27, + DBG_CLIENT_BLKID_uvdm_2 = 0x28, + DBG_CLIENT_BLKID_uvdm_3 = 0x29, + DBG_CLIENT_BLKID_spim2 = 0x2a, + DBG_CLIENT_BLKID_ds = 0x2b, + DBG_CLIENT_BLKID_srbm = 0x2c, + DBG_CLIENT_BLKID_ih = 0x2d, + DBG_CLIENT_BLKID_sem = 0x2e, + DBG_CLIENT_BLKID_sdma_0 = 0x2f, + DBG_CLIENT_BLKID_sdma_1 = 0x30, + DBG_CLIENT_BLKID_hdp = 0x31, + DBG_CLIENT_BLKID_acp_0 = 0x32, + DBG_CLIENT_BLKID_acp_1 = 0x33, + DBG_CLIENT_BLKID_vceb_0 = 0x34, + DBG_CLIENT_BLKID_vceb_1 = 0x35, + DBG_CLIENT_BLKID_vceb_2 = 0x36, + DBG_CLIENT_BLKID_mcd2 = 0x37, + DBG_CLIENT_BLKID_mcc2 = 0x38, + DBG_CLIENT_BLKID_scf3 = 0x39, + DBG_CLIENT_BLKID_bci3 = 0x3a, + DBG_CLIENT_BLKID_mcd5 = 0x3b, + DBG_CLIENT_BLKID_mcc5 = 0x3c, + DBG_CLIENT_BLKID_vgt2 = 0x3d, + DBG_CLIENT_BLKID_pc2 = 0x3e, + DBG_CLIENT_BLKID_smu_0 = 0x3f, + DBG_CLIENT_BLKID_smu_1 = 0x40, + DBG_CLIENT_BLKID_smu_2 = 0x41, + DBG_CLIENT_BLKID_vcea_0 = 0x42, + DBG_CLIENT_BLKID_vcea_1 = 0x43, + DBG_CLIENT_BLKID_vcea_2 = 0x44, + DBG_CLIENT_BLKID_vcea_3 = 0x45, + DBG_CLIENT_BLKID_vcea_4 = 0x46, + DBG_CLIENT_BLKID_vcea_5 = 0x47, + DBG_CLIENT_BLKID_vcea_6 = 0x48, + DBG_CLIENT_BLKID_scf0 = 0x49, + DBG_CLIENT_BLKID_vgt1 = 0x4a, + DBG_CLIENT_BLKID_pc1 = 0x4b, + DBG_CLIENT_BLKID_gdc_0 = 0x4c, + DBG_CLIENT_BLKID_gdc_1 = 0x4d, + DBG_CLIENT_BLKID_gdc_2 = 0x4e, + DBG_CLIENT_BLKID_gdc_3 = 0x4f, + DBG_CLIENT_BLKID_gdc_4 = 0x50, + DBG_CLIENT_BLKID_gdc_5 = 0x51, + DBG_CLIENT_BLKID_gdc_6 = 0x52, + DBG_CLIENT_BLKID_gdc_7 = 0x53, + DBG_CLIENT_BLKID_gdc_8 = 0x54, + DBG_CLIENT_BLKID_gdc_9 = 0x55, + DBG_CLIENT_BLKID_gdc_10 = 0x56, + DBG_CLIENT_BLKID_gdc_11 = 0x57, + DBG_CLIENT_BLKID_gdc_12 = 0x58, + DBG_CLIENT_BLKID_gdc_13 = 0x59, + DBG_CLIENT_BLKID_gdc_14 = 0x5a, + DBG_CLIENT_BLKID_gdc_15 = 0x5b, + DBG_CLIENT_BLKID_gdc_16 = 0x5c, + DBG_CLIENT_BLKID_gdc_17 = 0x5d, + DBG_CLIENT_BLKID_gdc_18 = 0x5e, + DBG_CLIENT_BLKID_gdc_19 = 0x5f, + DBG_CLIENT_BLKID_gdc_20 = 0x60, + DBG_CLIENT_BLKID_gdc_21 = 0x61, + DBG_CLIENT_BLKID_gdc_22 = 0x62, + DBG_CLIENT_BLKID_vgt3 = 0x63, + DBG_CLIENT_BLKID_pc3 = 0x64, + DBG_CLIENT_BLKID_uvdu_0 = 0x65, + DBG_CLIENT_BLKID_uvdu_1 = 0x66, + DBG_CLIENT_BLKID_uvdu_2 = 0x67, + DBG_CLIENT_BLKID_uvdu_3 = 0x68, + DBG_CLIENT_BLKID_uvdu_4 = 0x69, + DBG_CLIENT_BLKID_uvdu_5 = 0x6a, + DBG_CLIENT_BLKID_uvdu_6 = 0x6b, + DBG_CLIENT_BLKID_mcd7 = 0x6c, + DBG_CLIENT_BLKID_mcc7 = 0x6d, + DBG_CLIENT_BLKID_cpg_0 = 0x6e, + DBG_CLIENT_BLKID_cpg_1 = 0x6f, + DBG_CLIENT_BLKID_gck = 0x70, + DBG_CLIENT_BLKID_mcd1 = 0x71, + DBG_CLIENT_BLKID_mcc1 = 0x72, + DBG_CLIENT_BLKID_cb101 = 0x73, + DBG_CLIENT_BLKID_cb103 = 0x74, + DBG_CLIENT_BLKID_sx10 = 0x75, + DBG_CLIENT_BLKID_cb102 = 0x76, + DBG_CLIENT_BLKID_cb002 = 0x77, + DBG_CLIENT_BLKID_cb100 = 0x78, + DBG_CLIENT_BLKID_cb000 = 0x79, + DBG_CLIENT_BLKID_pa00 = 0x7a, + DBG_CLIENT_BLKID_pa10 = 0x7b, + DBG_CLIENT_BLKID_ia0 = 0x7c, + DBG_CLIENT_BLKID_ia1 = 0x7d, + DBG_CLIENT_BLKID_tmonw00 = 0x7e, + DBG_CLIENT_BLKID_cb001 = 0x7f, + DBG_CLIENT_BLKID_cb003 = 0x80, + DBG_CLIENT_BLKID_sx00 = 0x81, + DBG_CLIENT_BLKID_sx20 = 0x82, + DBG_CLIENT_BLKID_cb203 = 0x83, + DBG_CLIENT_BLKID_cb201 = 0x84, + DBG_CLIENT_BLKID_cb302 = 0x85, + DBG_CLIENT_BLKID_cb202 = 0x86, + DBG_CLIENT_BLKID_cb300 = 0x87, + DBG_CLIENT_BLKID_cb200 = 0x88, + DBG_CLIENT_BLKID_pa01 = 0x89, + DBG_CLIENT_BLKID_pa11 = 0x8a, + DBG_CLIENT_BLKID_sx30 = 0x8b, + DBG_CLIENT_BLKID_cb303 = 0x8c, + DBG_CLIENT_BLKID_cb301 = 0x8d, + DBG_CLIENT_BLKID_dco = 0x8e, + DBG_CLIENT_BLKID_scb0 = 0x8f, + DBG_CLIENT_BLKID_scb1 = 0x90, + DBG_CLIENT_BLKID_scb2 = 0x91, + DBG_CLIENT_BLKID_scb3 = 0x92, + DBG_CLIENT_BLKID_tmonw01 = 0x93, + DBG_CLIENT_BLKID_RESERVED_LAST = 0x94, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_SNORM_OGL = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_SNORM_OGL = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_UBNORM = 0xa, + IMG_NUM_FORMAT_UBNORM_OGL = 0xb, + IMG_NUM_FORMAT_UBINT = 0xc, + IMG_NUM_FORMAT_UBSCALED = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, + TCC_CACHE_POLICY_BYPASS = 0x2, +} TCC_CACHE_POLICIES; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; + +#endif /* SMU_7_1_0_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h new file mode 100644 index 000000000000..cd7893065a4b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h @@ -0,0 +1,5648 @@ +/* + * SMU_7_1_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_0_SH_MASK_H +#define SMU_7_1_0_SH_MASK_H + +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f +#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 +#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f +#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 +#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f +#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 +#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f +#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d +#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 +#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 +#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 +#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 +#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 +#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 +#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1 +#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa +#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff +#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 +#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 +#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 +#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 +#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa +#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 +#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_0__SMC_RESP_MASK 0xffff +#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_1__SMC_RESP_MASK 0xffff +#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_2__SMC_RESP_MASK 0xffff +#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_3__SMC_RESP_MASK 0xffff +#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_4__SMC_RESP_MASK 0xffff +#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_5__SMC_RESP_MASK 0xffff +#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_6__SMC_RESP_MASK 0xffff +#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_7__SMC_RESP_MASK 0xffff +#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_8__SMC_RESP_MASK 0xffff +#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_9__SMC_RESP_MASK 0xffff +#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_10__SMC_RESP_MASK 0xffff +#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_11__SMC_RESP_MASK 0xffff +#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 +#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 +#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 +#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 +#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 +#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffff +#define SMC_PC_C__smc_pc_c__SHIFT 0x0 +#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff +#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4 +#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff +#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 +#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff +#define GPIOPAD_A__GPIO_A__SHIFT 0x0 +#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff +#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0 +#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff +#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f +#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff +#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000 +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f +#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6 +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0 +#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff +#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 +#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff +#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 +#define CG_FPS_CNT__FPS_CNT_MASK 0xff +#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 +#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 +#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3 +#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 +#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 +#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 +#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa +#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 +#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 +#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 +#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 +#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 +#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 +#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 +#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 +#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 +#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 +#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 +#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 +#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 +#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 +#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 +#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 +#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 +#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 +#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 +#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 +#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 +#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 +#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 +#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa +#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000 +#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000 +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000 +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11 +#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000 +#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14 +#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000 +#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17 +#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000 +#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18 +#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfe000000 +#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 +#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc +#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 +#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 +#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 +#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 +#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c +#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 +#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d +#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff +#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 +#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 +#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 +#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 +#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 +#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 +#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 +#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e +#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 +#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a +#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 +#define SMU_STATUS__SMU_DONE_MASK 0x1 +#define SMU_STATUS__SMU_DONE__SHIFT 0x0 +#define SMU_STATUS__SMU_PASS_MASK 0x2 +#define SMU_STATUS__SMU_PASS__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 +#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 +#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 +#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 +#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 +#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 +#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 +#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 +#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 +#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff +#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 +#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 +#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f +#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff +#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 +#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff +#define DPM_TABLE_28__SystemFlags__SHIFT 0x0 +#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff +#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0 +#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff +#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0 +#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff +#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0 +#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff +#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0 +#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff +#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0 +#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff +#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0 +#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff +#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff +#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff +#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff +#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff +#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000 +#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10 +#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff +#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0 +#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00 +#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000 +#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10 +#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff +#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0 +#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00 +#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000 +#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10 +#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff +#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0 +#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00 +#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000 +#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10 +#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff +#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0 +#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00 +#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff +#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff +#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff +#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff +#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff +#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff +#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff +#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff +#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_68__UvdLevelCount_MASK 0xff +#define DPM_TABLE_68__UvdLevelCount__SHIFT 0x0 +#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00 +#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8 +#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000 +#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10 +#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000 +#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18 +#define DPM_TABLE_69__MasterDeepSleepControl_MASK 0xff +#define DPM_TABLE_69__MasterDeepSleepControl__SHIFT 0x0 +#define DPM_TABLE_69__SamuLevelCount_MASK 0xff00 +#define DPM_TABLE_69__SamuLevelCount__SHIFT 0x8 +#define DPM_TABLE_69__AcpLevelCount_MASK 0xff0000 +#define DPM_TABLE_69__AcpLevelCount__SHIFT 0x10 +#define DPM_TABLE_69__VceLevelCount_MASK 0xff000000 +#define DPM_TABLE_69__VceLevelCount__SHIFT 0x18 +#define DPM_TABLE_70__DefaultTdp_MASK 0xffff +#define DPM_TABLE_70__DefaultTdp__SHIFT 0x0 +#define DPM_TABLE_70__TargetTdp_MASK 0xffff0000 +#define DPM_TABLE_70__TargetTdp__SHIFT 0x10 +#define DPM_TABLE_71__Reserved_1_MASK 0xffffffff +#define DPM_TABLE_71__Reserved_1__SHIFT 0x0 +#define DPM_TABLE_72__Reserved_2_MASK 0xffffffff +#define DPM_TABLE_72__Reserved_2__SHIFT 0x0 +#define DPM_TABLE_73__Reserved_3_MASK 0xffffffff +#define DPM_TABLE_73__Reserved_3__SHIFT 0x0 +#define DPM_TABLE_74__Reserved_4_MASK 0xffffffff +#define DPM_TABLE_74__Reserved_4__SHIFT 0x0 +#define DPM_TABLE_75__GraphicsLevel_0_Flags_MASK 0xffffffff +#define DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT 0x0 +#define DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK 0xffff +#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_79__GraphicsLevel_0_padding1_MASK 0xff0000 +#define DPM_TABLE_79__GraphicsLevel_0_padding1__SHIFT 0x10 +#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK 0xff000000 +#define DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT 0x18 +#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK 0xff +#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_89__GraphicsLevel_1_Flags_MASK 0xffffffff +#define DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT 0x0 +#define DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK 0xffff +#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_93__GraphicsLevel_1_padding1_MASK 0xff0000 +#define DPM_TABLE_93__GraphicsLevel_1_padding1__SHIFT 0x10 +#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK 0xff000000 +#define DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT 0x18 +#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK 0xff +#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_103__GraphicsLevel_2_Flags_MASK 0xffffffff +#define DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT 0x0 +#define DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK 0xffff +#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_107__GraphicsLevel_2_padding1_MASK 0xff0000 +#define DPM_TABLE_107__GraphicsLevel_2_padding1__SHIFT 0x10 +#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK 0xff000000 +#define DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT 0x18 +#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK 0xff +#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_117__GraphicsLevel_3_Flags_MASK 0xffffffff +#define DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT 0x0 +#define DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK 0xffff +#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_3_padding1_MASK 0xff0000 +#define DPM_TABLE_121__GraphicsLevel_3_padding1__SHIFT 0x10 +#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK 0xff000000 +#define DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT 0x18 +#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK 0xff +#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_131__GraphicsLevel_4_Flags_MASK 0xffffffff +#define DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT 0x0 +#define DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK 0xffffffff +#define DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT 0x0 +#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK 0xffff +#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_4_padding1_MASK 0xff0000 +#define DPM_TABLE_135__GraphicsLevel_4_padding1__SHIFT 0x10 +#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK 0xff000000 +#define DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT 0x18 +#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK 0xff +#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_145__GraphicsLevel_5_Flags_MASK 0xffffffff +#define DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT 0x0 +#define DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK 0xffffffff +#define DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT 0x0 +#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK 0xffff +#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_5_padding1_MASK 0xff0000 +#define DPM_TABLE_149__GraphicsLevel_5_padding1__SHIFT 0x10 +#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK 0xff000000 +#define DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT 0x18 +#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK 0xff +#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_159__GraphicsLevel_6_Flags_MASK 0xffffffff +#define DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT 0x0 +#define DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK 0xffffffff +#define DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT 0x0 +#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_padding1_MASK 0xff0000 +#define DPM_TABLE_163__GraphicsLevel_6_padding1__SHIFT 0x10 +#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18 +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18 +#define DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_173__GraphicsLevel_7_Flags_MASK 0xffffffff +#define DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT 0x0 +#define DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK 0xffffffff +#define DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT 0x0 +#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK 0xffff +#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_177__GraphicsLevel_7_padding1_MASK 0xff0000 +#define DPM_TABLE_177__GraphicsLevel_7_padding1__SHIFT 0x10 +#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK 0xff000000 +#define DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT 0x18 +#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK 0xff +#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK 0xff0000 +#define DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT 0x10 +#define DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK 0xff000000 +#define DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT 0x18 +#define DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK 0xffffffff +#define DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT 0x0 +#define DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK 0xff +#define DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK 0xff00 +#define DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT 0x8 +#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK 0xff +#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_194__MemoryACPILevel_padding_MASK 0xff +#define DPM_TABLE_194__MemoryACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK 0xff0000 +#define DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT 0x10 +#define DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK 0xff000000 +#define DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT 0x18 +#define DPM_TABLE_195__MemoryACPILevel_padding1_MASK 0xff +#define DPM_TABLE_195__MemoryACPILevel_padding1__SHIFT 0x0 +#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK 0xffffffff +#define DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT 0x0 +#define DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK 0xffffffff +#define DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT 0x0 +#define DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK 0xff +#define DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK 0xff00 +#define DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT 0x8 +#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK 0xff +#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_212__MemoryLevel_0_padding_MASK 0xff +#define DPM_TABLE_212__MemoryLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_213__MemoryLevel_0_padding1_MASK 0xff +#define DPM_TABLE_213__MemoryLevel_0_padding1__SHIFT 0x0 +#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK 0xffffffff +#define DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT 0x0 +#define DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK 0xffffffff +#define DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT 0x0 +#define DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK 0xff +#define DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK 0xff00 +#define DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT 0x8 +#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK 0xff +#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_230__MemoryLevel_1_padding_MASK 0xff +#define DPM_TABLE_230__MemoryLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_231__MemoryLevel_1_padding1_MASK 0xff +#define DPM_TABLE_231__MemoryLevel_1_padding1__SHIFT 0x0 +#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK 0xffffffff +#define DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT 0x0 +#define DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK 0xffffffff +#define DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT 0x0 +#define DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK 0xff +#define DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK 0xff00 +#define DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT 0x8 +#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK 0xff +#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_248__MemoryLevel_2_padding_MASK 0xff +#define DPM_TABLE_248__MemoryLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_249__MemoryLevel_2_padding1_MASK 0xff +#define DPM_TABLE_249__MemoryLevel_2_padding1__SHIFT 0x0 +#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK 0xffffffff +#define DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT 0x0 +#define DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK 0xffffffff +#define DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT 0x0 +#define DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK 0xff +#define DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK 0xff00 +#define DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT 0x8 +#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK 0xff +#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_266__MemoryLevel_3_padding_MASK 0xff +#define DPM_TABLE_266__MemoryLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_267__MemoryLevel_3_padding1_MASK 0xff +#define DPM_TABLE_267__MemoryLevel_3_padding1__SHIFT 0x0 +#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK 0xffffffff +#define DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT 0x0 +#define DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK 0xffffffff +#define DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT 0x0 +#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK 0xffffffff +#define DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT 0x0 +#define DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK 0xff +#define DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK 0xff00 +#define DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT 0x8 +#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK 0xff +#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_284__MemoryLevel_4_padding_MASK 0xff +#define DPM_TABLE_284__MemoryLevel_4_padding__SHIFT 0x0 +#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_285__MemoryLevel_4_padding1_MASK 0xff +#define DPM_TABLE_285__MemoryLevel_4_padding1__SHIFT 0x0 +#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK 0xffffffff +#define DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT 0x0 +#define DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK 0xffffffff +#define DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT 0x0 +#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK 0xffffffff +#define DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT 0x0 +#define DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK 0xff +#define DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK 0xff00 +#define DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT 0x8 +#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK 0xff +#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_302__MemoryLevel_5_padding_MASK 0xff +#define DPM_TABLE_302__MemoryLevel_5_padding__SHIFT 0x0 +#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_303__MemoryLevel_5_padding1_MASK 0xff +#define DPM_TABLE_303__MemoryLevel_5_padding1__SHIFT 0x0 +#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK 0xffffffff +#define DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT 0x0 +#define DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_313__LinkLevel_0_Padding_MASK 0xff +#define DPM_TABLE_313__LinkLevel_0_Padding__SHIFT 0x0 +#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_316__LinkLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_317__LinkLevel_1_Padding_MASK 0xff +#define DPM_TABLE_317__LinkLevel_1_Padding__SHIFT 0x0 +#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_320__LinkLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_321__LinkLevel_2_Padding_MASK 0xff +#define DPM_TABLE_321__LinkLevel_2_Padding__SHIFT 0x0 +#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_324__LinkLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_325__LinkLevel_3_Padding_MASK 0xff +#define DPM_TABLE_325__LinkLevel_3_Padding__SHIFT 0x0 +#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_328__LinkLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_329__LinkLevel_4_Padding_MASK 0xff +#define DPM_TABLE_329__LinkLevel_4_Padding__SHIFT 0x0 +#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_332__LinkLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_333__LinkLevel_5_Padding_MASK 0xff +#define DPM_TABLE_333__LinkLevel_5_Padding__SHIFT 0x0 +#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_336__LinkLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_337__LinkLevel_6_Padding_MASK 0xff +#define DPM_TABLE_337__LinkLevel_6_Padding__SHIFT 0x0 +#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_340__LinkLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_341__LinkLevel_7_Padding_MASK 0xff +#define DPM_TABLE_341__LinkLevel_7_Padding__SHIFT 0x0 +#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_344__LinkLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_345__ACPILevel_Flags_MASK 0xffffffff +#define DPM_TABLE_345__ACPILevel_Flags__SHIFT 0x0 +#define DPM_TABLE_346__ACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_346__ACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_348__ACPILevel_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_349__ACPILevel_padding_MASK 0xff +#define DPM_TABLE_349__ACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_349__ACPILevel_SclkDid_MASK 0xff000000 +#define DPM_TABLE_349__ACPILevel_SclkDid__SHIFT 0x18 +#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff +#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0 +#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK 0xff +#define DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_360__UvdLevel_0_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT 0x10 +#define DPM_TABLE_361__UvdLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_361__UvdLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_361__UvdLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK 0xff +#define DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_364__UvdLevel_1_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT 0x10 +#define DPM_TABLE_365__UvdLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_365__UvdLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_365__UvdLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK 0xff +#define DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_368__UvdLevel_2_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT 0x10 +#define DPM_TABLE_369__UvdLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_369__UvdLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_369__UvdLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK 0xff +#define DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_372__UvdLevel_3_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT 0x10 +#define DPM_TABLE_373__UvdLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_373__UvdLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_373__UvdLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK 0xff +#define DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_376__UvdLevel_4_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT 0x10 +#define DPM_TABLE_377__UvdLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_377__UvdLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_377__UvdLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK 0xff +#define DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_380__UvdLevel_5_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT 0x10 +#define DPM_TABLE_381__UvdLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_381__UvdLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_381__UvdLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK 0xff +#define DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_384__UvdLevel_6_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT 0x10 +#define DPM_TABLE_385__UvdLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_385__UvdLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_385__UvdLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK 0xff +#define DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_388__UvdLevel_7_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT 0x10 +#define DPM_TABLE_389__UvdLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_389__UvdLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_389__UvdLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_390__VceLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_390__VceLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_391__VceLevel_0_Divider_MASK 0xff +#define DPM_TABLE_391__VceLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_391__VceLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_391__VceLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_392__VceLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_392__VceLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_393__VceLevel_1_Divider_MASK 0xff +#define DPM_TABLE_393__VceLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_393__VceLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_393__VceLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_394__VceLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_394__VceLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_395__VceLevel_2_Divider_MASK 0xff +#define DPM_TABLE_395__VceLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_395__VceLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_395__VceLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_396__VceLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_396__VceLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_397__VceLevel_3_Divider_MASK 0xff +#define DPM_TABLE_397__VceLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_397__VceLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_397__VceLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_398__VceLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_398__VceLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_399__VceLevel_4_Divider_MASK 0xff +#define DPM_TABLE_399__VceLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_399__VceLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_399__VceLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_400__VceLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_400__VceLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_401__VceLevel_5_Divider_MASK 0xff +#define DPM_TABLE_401__VceLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_401__VceLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_401__VceLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_402__VceLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_402__VceLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_403__VceLevel_6_Divider_MASK 0xff +#define DPM_TABLE_403__VceLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_403__VceLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_403__VceLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_404__VceLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_404__VceLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_405__VceLevel_7_Divider_MASK 0xff +#define DPM_TABLE_405__VceLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_405__VceLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_405__VceLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_406__AcpLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_407__AcpLevel_0_Divider_MASK 0xff +#define DPM_TABLE_407__AcpLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_407__AcpLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_408__AcpLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_409__AcpLevel_1_Divider_MASK 0xff +#define DPM_TABLE_409__AcpLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_409__AcpLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_410__AcpLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_411__AcpLevel_2_Divider_MASK 0xff +#define DPM_TABLE_411__AcpLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_411__AcpLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_412__AcpLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_413__AcpLevel_3_Divider_MASK 0xff +#define DPM_TABLE_413__AcpLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_413__AcpLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_414__AcpLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_415__AcpLevel_4_Divider_MASK 0xff +#define DPM_TABLE_415__AcpLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_415__AcpLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_416__AcpLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_417__AcpLevel_5_Divider_MASK 0xff +#define DPM_TABLE_417__AcpLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_417__AcpLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_418__AcpLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_419__AcpLevel_6_Divider_MASK 0xff +#define DPM_TABLE_419__AcpLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_419__AcpLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_420__AcpLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_421__AcpLevel_7_Divider_MASK 0xff +#define DPM_TABLE_421__AcpLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_421__AcpLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_422__SamuLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_423__SamuLevel_0_Divider_MASK 0xff +#define DPM_TABLE_423__SamuLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_423__SamuLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_424__SamuLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_425__SamuLevel_1_Divider_MASK 0xff +#define DPM_TABLE_425__SamuLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_425__SamuLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_426__SamuLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_427__SamuLevel_2_Divider_MASK 0xff +#define DPM_TABLE_427__SamuLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_427__SamuLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_428__SamuLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_429__SamuLevel_3_Divider_MASK 0xff +#define DPM_TABLE_429__SamuLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_429__SamuLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_430__SamuLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_431__SamuLevel_4_Divider_MASK 0xff +#define DPM_TABLE_431__SamuLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_431__SamuLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_432__SamuLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_433__SamuLevel_5_Divider_MASK 0xff +#define DPM_TABLE_433__SamuLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_433__SamuLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_434__SamuLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_435__SamuLevel_6_Divider_MASK 0xff +#define DPM_TABLE_435__SamuLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_435__SamuLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_436__SamuLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_437__SamuLevel_7_Divider_MASK 0xff +#define DPM_TABLE_437__SamuLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_437__SamuLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_438__Ulv_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_440__Ulv_VddcPhase_MASK 0xff +#define DPM_TABLE_440__Ulv_VddcPhase__SHIFT 0x0 +#define DPM_TABLE_440__Ulv_VddcOffsetVid_MASK 0xff00 +#define DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT 0x8 +#define DPM_TABLE_440__Ulv_VddcOffset_MASK 0xffff0000 +#define DPM_TABLE_440__Ulv_VddcOffset__SHIFT 0x10 +#define DPM_TABLE_441__Ulv_Reserved_MASK 0xffffffff +#define DPM_TABLE_441__Ulv_Reserved__SHIFT 0x0 +#define DPM_TABLE_442__SclkStepSize_MASK 0xffffffff +#define DPM_TABLE_442__SclkStepSize__SHIFT 0x0 +#define DPM_TABLE_443__Smio_0_MASK 0xffffffff +#define DPM_TABLE_443__Smio_0__SHIFT 0x0 +#define DPM_TABLE_444__Smio_1_MASK 0xffffffff +#define DPM_TABLE_444__Smio_1__SHIFT 0x0 +#define DPM_TABLE_445__Smio_2_MASK 0xffffffff +#define DPM_TABLE_445__Smio_2__SHIFT 0x0 +#define DPM_TABLE_446__Smio_3_MASK 0xffffffff +#define DPM_TABLE_446__Smio_3__SHIFT 0x0 +#define DPM_TABLE_447__Smio_4_MASK 0xffffffff +#define DPM_TABLE_447__Smio_4__SHIFT 0x0 +#define DPM_TABLE_448__Smio_5_MASK 0xffffffff +#define DPM_TABLE_448__Smio_5__SHIFT 0x0 +#define DPM_TABLE_449__Smio_6_MASK 0xffffffff +#define DPM_TABLE_449__Smio_6__SHIFT 0x0 +#define DPM_TABLE_450__Smio_7_MASK 0xffffffff +#define DPM_TABLE_450__Smio_7__SHIFT 0x0 +#define DPM_TABLE_451__Smio_8_MASK 0xffffffff +#define DPM_TABLE_451__Smio_8__SHIFT 0x0 +#define DPM_TABLE_452__Smio_9_MASK 0xffffffff +#define DPM_TABLE_452__Smio_9__SHIFT 0x0 +#define DPM_TABLE_453__Smio_10_MASK 0xffffffff +#define DPM_TABLE_453__Smio_10__SHIFT 0x0 +#define DPM_TABLE_454__Smio_11_MASK 0xffffffff +#define DPM_TABLE_454__Smio_11__SHIFT 0x0 +#define DPM_TABLE_455__Smio_12_MASK 0xffffffff +#define DPM_TABLE_455__Smio_12__SHIFT 0x0 +#define DPM_TABLE_456__Smio_13_MASK 0xffffffff +#define DPM_TABLE_456__Smio_13__SHIFT 0x0 +#define DPM_TABLE_457__Smio_14_MASK 0xffffffff +#define DPM_TABLE_457__Smio_14__SHIFT 0x0 +#define DPM_TABLE_458__Smio_15_MASK 0xffffffff +#define DPM_TABLE_458__Smio_15__SHIFT 0x0 +#define DPM_TABLE_459__Smio_16_MASK 0xffffffff +#define DPM_TABLE_459__Smio_16__SHIFT 0x0 +#define DPM_TABLE_460__Smio_17_MASK 0xffffffff +#define DPM_TABLE_460__Smio_17__SHIFT 0x0 +#define DPM_TABLE_461__Smio_18_MASK 0xffffffff +#define DPM_TABLE_461__Smio_18__SHIFT 0x0 +#define DPM_TABLE_462__Smio_19_MASK 0xffffffff +#define DPM_TABLE_462__Smio_19__SHIFT 0x0 +#define DPM_TABLE_463__Smio_20_MASK 0xffffffff +#define DPM_TABLE_463__Smio_20__SHIFT 0x0 +#define DPM_TABLE_464__Smio_21_MASK 0xffffffff +#define DPM_TABLE_464__Smio_21__SHIFT 0x0 +#define DPM_TABLE_465__Smio_22_MASK 0xffffffff +#define DPM_TABLE_465__Smio_22__SHIFT 0x0 +#define DPM_TABLE_466__Smio_23_MASK 0xffffffff +#define DPM_TABLE_466__Smio_23__SHIFT 0x0 +#define DPM_TABLE_467__Smio_24_MASK 0xffffffff +#define DPM_TABLE_467__Smio_24__SHIFT 0x0 +#define DPM_TABLE_468__Smio_25_MASK 0xffffffff +#define DPM_TABLE_468__Smio_25__SHIFT 0x0 +#define DPM_TABLE_469__Smio_26_MASK 0xffffffff +#define DPM_TABLE_469__Smio_26__SHIFT 0x0 +#define DPM_TABLE_470__Smio_27_MASK 0xffffffff +#define DPM_TABLE_470__Smio_27__SHIFT 0x0 +#define DPM_TABLE_471__Smio_28_MASK 0xffffffff +#define DPM_TABLE_471__Smio_28__SHIFT 0x0 +#define DPM_TABLE_472__Smio_29_MASK 0xffffffff +#define DPM_TABLE_472__Smio_29__SHIFT 0x0 +#define DPM_TABLE_473__Smio_30_MASK 0xffffffff +#define DPM_TABLE_473__Smio_30__SHIFT 0x0 +#define DPM_TABLE_474__Smio_31_MASK 0xffffffff +#define DPM_TABLE_474__Smio_31__SHIFT 0x0 +#define DPM_TABLE_475__SamuBootLevel_MASK 0xff +#define DPM_TABLE_475__SamuBootLevel__SHIFT 0x0 +#define DPM_TABLE_475__AcpBootLevel_MASK 0xff00 +#define DPM_TABLE_475__AcpBootLevel__SHIFT 0x8 +#define DPM_TABLE_475__VceBootLevel_MASK 0xff0000 +#define DPM_TABLE_475__VceBootLevel__SHIFT 0x10 +#define DPM_TABLE_475__UvdBootLevel_MASK 0xff000000 +#define DPM_TABLE_475__UvdBootLevel__SHIFT 0x18 +#define DPM_TABLE_476__SAMUInterval_MASK 0xff +#define DPM_TABLE_476__SAMUInterval__SHIFT 0x0 +#define DPM_TABLE_476__ACPInterval_MASK 0xff00 +#define DPM_TABLE_476__ACPInterval__SHIFT 0x8 +#define DPM_TABLE_476__VCEInterval_MASK 0xff0000 +#define DPM_TABLE_476__VCEInterval__SHIFT 0x10 +#define DPM_TABLE_476__UVDInterval_MASK 0xff000000 +#define DPM_TABLE_476__UVDInterval__SHIFT 0x18 +#define DPM_TABLE_477__GraphicsInterval_MASK 0xff +#define DPM_TABLE_477__GraphicsInterval__SHIFT 0x0 +#define DPM_TABLE_477__GraphicsThermThrottleEnable_MASK 0xff00 +#define DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT 0x8 +#define DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK 0xff0000 +#define DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT 0x10 +#define DPM_TABLE_477__GraphicsBootLevel_MASK 0xff000000 +#define DPM_TABLE_477__GraphicsBootLevel__SHIFT 0x18 +#define DPM_TABLE_478__TemperatureLimitHigh_MASK 0xffff +#define DPM_TABLE_478__TemperatureLimitHigh__SHIFT 0x0 +#define DPM_TABLE_478__ThermalInterval_MASK 0xff0000 +#define DPM_TABLE_478__ThermalInterval__SHIFT 0x10 +#define DPM_TABLE_478__VoltageInterval_MASK 0xff000000 +#define DPM_TABLE_478__VoltageInterval__SHIFT 0x18 +#define DPM_TABLE_479__MemoryVoltageChangeEnable_MASK 0xff +#define DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT 0x0 +#define DPM_TABLE_479__MemoryBootLevel_MASK 0xff00 +#define DPM_TABLE_479__MemoryBootLevel__SHIFT 0x8 +#define DPM_TABLE_479__TemperatureLimitLow_MASK 0xffff0000 +#define DPM_TABLE_479__TemperatureLimitLow__SHIFT 0x10 +#define DPM_TABLE_480__VddcVddciDelta_MASK 0xffff +#define DPM_TABLE_480__VddcVddciDelta__SHIFT 0x0 +#define DPM_TABLE_480__MemoryThermThrottleEnable_MASK 0xff0000 +#define DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT 0x10 +#define DPM_TABLE_480__MemoryInterval_MASK 0xff000000 +#define DPM_TABLE_480__MemoryInterval__SHIFT 0x18 +#define DPM_TABLE_481__PhaseResponseTime_MASK 0xffff +#define DPM_TABLE_481__PhaseResponseTime__SHIFT 0x0 +#define DPM_TABLE_481__VoltageResponseTime_MASK 0xffff0000 +#define DPM_TABLE_481__VoltageResponseTime__SHIFT 0x10 +#define DPM_TABLE_482__DTEMode_MASK 0xff +#define DPM_TABLE_482__DTEMode__SHIFT 0x0 +#define DPM_TABLE_482__DTEInterval_MASK 0xff00 +#define DPM_TABLE_482__DTEInterval__SHIFT 0x8 +#define DPM_TABLE_482__PCIeGenInterval_MASK 0xff0000 +#define DPM_TABLE_482__PCIeGenInterval__SHIFT 0x10 +#define DPM_TABLE_482__PCIeBootLinkLevel_MASK 0xff000000 +#define DPM_TABLE_482__PCIeBootLinkLevel__SHIFT 0x18 +#define DPM_TABLE_483__ThermGpio_MASK 0xff +#define DPM_TABLE_483__ThermGpio__SHIFT 0x0 +#define DPM_TABLE_483__AcDcGpio_MASK 0xff00 +#define DPM_TABLE_483__AcDcGpio__SHIFT 0x8 +#define DPM_TABLE_483__VRHotGpio_MASK 0xff0000 +#define DPM_TABLE_483__VRHotGpio__SHIFT 0x10 +#define DPM_TABLE_483__SVI2Enable_MASK 0xff000000 +#define DPM_TABLE_483__SVI2Enable__SHIFT 0x18 +#define DPM_TABLE_484__PPM_TemperatureLimit_MASK 0xffff +#define DPM_TABLE_484__PPM_TemperatureLimit__SHIFT 0x0 +#define DPM_TABLE_484__PPM_PkgPwrLimit_MASK 0xffff0000 +#define DPM_TABLE_484__PPM_PkgPwrLimit__SHIFT 0x10 +#define DPM_TABLE_485__TargetTdp_MASK 0xffff +#define DPM_TABLE_485__TargetTdp__SHIFT 0x0 +#define DPM_TABLE_485__DefaultTdp_MASK 0xffff0000 +#define DPM_TABLE_485__DefaultTdp__SHIFT 0x10 +#define DPM_TABLE_486__FpsLowThreshold_MASK 0xffff +#define DPM_TABLE_486__FpsLowThreshold__SHIFT 0x0 +#define DPM_TABLE_486__FpsHighThreshold_MASK 0xffff0000 +#define DPM_TABLE_486__FpsHighThreshold__SHIFT 0x10 +#define DPM_TABLE_487__BAPMTI_R_0_1_0_MASK 0xffff +#define DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT 0x0 +#define DPM_TABLE_487__BAPMTI_R_0_0_0_MASK 0xffff0000 +#define DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT 0x10 +#define DPM_TABLE_488__BAPMTI_R_1_0_0_MASK 0xffff +#define DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT 0x0 +#define DPM_TABLE_488__BAPMTI_R_0_2_0_MASK 0xffff0000 +#define DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT 0x10 +#define DPM_TABLE_489__BAPMTI_R_1_2_0_MASK 0xffff +#define DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT 0x0 +#define DPM_TABLE_489__BAPMTI_R_1_1_0_MASK 0xffff0000 +#define DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT 0x10 +#define DPM_TABLE_490__BAPMTI_R_2_1_0_MASK 0xffff +#define DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT 0x0 +#define DPM_TABLE_490__BAPMTI_R_2_0_0_MASK 0xffff0000 +#define DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT 0x10 +#define DPM_TABLE_491__BAPMTI_R_3_0_0_MASK 0xffff +#define DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT 0x0 +#define DPM_TABLE_491__BAPMTI_R_2_2_0_MASK 0xffff0000 +#define DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT 0x10 +#define DPM_TABLE_492__BAPMTI_R_3_2_0_MASK 0xffff +#define DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT 0x0 +#define DPM_TABLE_492__BAPMTI_R_3_1_0_MASK 0xffff0000 +#define DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT 0x10 +#define DPM_TABLE_493__BAPMTI_R_4_1_0_MASK 0xffff +#define DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT 0x0 +#define DPM_TABLE_493__BAPMTI_R_4_0_0_MASK 0xffff0000 +#define DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT 0x10 +#define DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK 0xffff +#define DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT 0x0 +#define DPM_TABLE_494__BAPMTI_R_4_2_0_MASK 0xffff0000 +#define DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT 0x10 +#define DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK 0xffff +#define DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT 0x0 +#define DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK 0xffff0000 +#define DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT 0x10 +#define DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK 0xffff +#define DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT 0x0 +#define DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK 0xffff0000 +#define DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT 0x10 +#define DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK 0xffff +#define DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT 0x0 +#define DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK 0xffff0000 +#define DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT 0x10 +#define DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK 0xffff +#define DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT 0x0 +#define DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK 0xffff0000 +#define DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT 0x10 +#define DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK 0xffff +#define DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT 0x0 +#define DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK 0xffff0000 +#define DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT 0x10 +#define DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK 0xffff +#define DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT 0x0 +#define DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK 0xffff0000 +#define DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT 0x10 +#define DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK 0xffff +#define DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT 0x0 +#define DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK 0xffff0000 +#define DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT 0x10 +#define DPM_TABLE_502__GpuTjHyst_MASK 0xff +#define DPM_TABLE_502__GpuTjHyst__SHIFT 0x0 +#define DPM_TABLE_502__GpuTjMax_MASK 0xff00 +#define DPM_TABLE_502__GpuTjMax__SHIFT 0x8 +#define DPM_TABLE_502__DTETjOffset_MASK 0xff0000 +#define DPM_TABLE_502__DTETjOffset__SHIFT 0x10 +#define DPM_TABLE_502__DTEAmbientTempBase_MASK 0xff000000 +#define DPM_TABLE_502__DTEAmbientTempBase__SHIFT 0x18 +#define DPM_TABLE_503__BootVddci_MASK 0xffff +#define DPM_TABLE_503__BootVddci__SHIFT 0x0 +#define DPM_TABLE_503__BootVddc_MASK 0xffff0000 +#define DPM_TABLE_503__BootVddc__SHIFT 0x10 +#define DPM_TABLE_504__padding_MASK 0xff +#define DPM_TABLE_504__padding__SHIFT 0x0 +#define DPM_TABLE_504__PccGpio_MASK 0xff00 +#define DPM_TABLE_504__PccGpio__SHIFT 0x8 +#define DPM_TABLE_504__BootMVdd_MASK 0xffff0000 +#define DPM_TABLE_504__BootMVdd__SHIFT 0x10 +#define DPM_TABLE_505__BAPM_TEMP_GRADIENT_MASK 0xffffffff +#define DPM_TABLE_505__BAPM_TEMP_GRADIENT__SHIFT 0x0 +#define DPM_TABLE_506__LowSclkInterruptThreshold_MASK 0xffffffff +#define DPM_TABLE_506__LowSclkInterruptThreshold__SHIFT 0x0 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe +#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 +#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 +#define TDC_STATUS__VDD_Boost_MASK 0xff +#define TDC_STATUS__VDD_Boost__SHIFT 0x0 +#define TDC_STATUS__VDD_Throttle_MASK 0xff00 +#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 +#define TDC_STATUS__VDDC_Boost_MASK 0xff0000 +#define TDC_STATUS__VDDC_Boost__SHIFT 0x10 +#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000 +#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18 +#define TDC_MV_AVERAGE__IDD_MASK 0xffff +#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 +#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000 +#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10 +#define TDC_VRM_LIMIT__IDD_MASK 0xffff +#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 +#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000 +#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10 +#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 +#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 +#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 +#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 +#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 +#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 +#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 +#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 +#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 +#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 +#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20 +#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5 +#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40 +#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6 +#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 +#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 +#define FEATURE_STATUS__BAPM_ON_MASK 0x100 +#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 +#define FEATURE_STATUS__LPMX_ON_MASK 0x200 +#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 +#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 +#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa +#define FEATURE_STATUS__LHTC_ON_MASK 0x800 +#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb +#define FEATURE_STATUS__VPC_ON_MASK 0x1000 +#define FEATURE_STATUS__VPC_ON__SHIFT 0xc +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd +#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 +#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe +#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 +#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf +#define FEATURE_STATUS__AVS_ON_MASK 0x10000 +#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 +#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 +#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 +#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 +#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 +#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 +#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 +#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 +#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 +#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 +#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 +#define FEATURE_STATUS__RESERVED_MASK 0xffc00000 +#define FEATURE_STATUS__RESERVED__SHIFT 0x16 +#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff +#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime__SHIFT 0x18 +#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff +#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00 +#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8 +#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000 +#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000 +#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18 +#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_82__data_4_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_82__data_4_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_83__data_4_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_83__data_4_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_84__data_4_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_84__data_4_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_85__data_4_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_85__data_4_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_86__data_4_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_86__data_4_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_87__data_4_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_87__data_4_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_88__data_4_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_88__data_4_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_89__data_4_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_89__data_4_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_90__data_4_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_90__data_4_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_91__data_4_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_91__data_4_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_92__data_4_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_93__data_4_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_93__data_4_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_94__data_4_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_94__data_4_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_95__data_4_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_95__data_4_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_96__data_4_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_96__data_4_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_97__data_4_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_97__data_4_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_98__data_5_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_98__data_5_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_99__data_5_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_99__data_5_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_100__data_5_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_100__data_5_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_101__data_5_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_102__data_5_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_103__data_5_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_103__data_5_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_104__data_5_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_104__data_5_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_105__data_5_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_105__data_5_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_106__data_5_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_106__data_5_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_107__data_5_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_107__data_5_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_108__data_5_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_109__data_5_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_109__data_5_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_110__data_5_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_111__data_5_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_111__data_5_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_112__data_5_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_112__data_5_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_113__data_5_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_113__data_5_value_15__SHIFT 0x0 +#define FAN_TABLE_1__TempMin_MASK 0xffff +#define FAN_TABLE_1__TempMin__SHIFT 0x0 +#define FAN_TABLE_1__FdoMode_MASK 0xffff0000 +#define FAN_TABLE_1__FdoMode__SHIFT 0x10 +#define FAN_TABLE_2__TempMax_MASK 0xffff +#define FAN_TABLE_2__TempMax__SHIFT 0x0 +#define FAN_TABLE_2__TempMed_MASK 0xffff0000 +#define FAN_TABLE_2__TempMed__SHIFT 0x10 +#define FAN_TABLE_3__Slope2_MASK 0xffff +#define FAN_TABLE_3__Slope2__SHIFT 0x0 +#define FAN_TABLE_3__Slope1_MASK 0xffff0000 +#define FAN_TABLE_3__Slope1__SHIFT 0x10 +#define FAN_TABLE_4__HystUp_MASK 0xffff +#define FAN_TABLE_4__HystUp__SHIFT 0x0 +#define FAN_TABLE_4__FdoMin_MASK 0xffff0000 +#define FAN_TABLE_4__FdoMin__SHIFT 0x10 +#define FAN_TABLE_5__HystSlope_MASK 0xffff +#define FAN_TABLE_5__HystSlope__SHIFT 0x0 +#define FAN_TABLE_5__HystDown_MASK 0xffff0000 +#define FAN_TABLE_5__HystDown__SHIFT 0x10 +#define FAN_TABLE_6__TempCurr_MASK 0xffff +#define FAN_TABLE_6__TempCurr__SHIFT 0x0 +#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000 +#define FAN_TABLE_6__TempRespLim__SHIFT 0x10 +#define FAN_TABLE_7__PwmCurr_MASK 0xffff +#define FAN_TABLE_7__PwmCurr__SHIFT 0x0 +#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000 +#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10 +#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff +#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0 +#define FAN_TABLE_9__Padding_MASK 0xff +#define FAN_TABLE_9__Padding__SHIFT 0x0 +#define FAN_TABLE_9__TempSrc_MASK 0xff00 +#define FAN_TABLE_9__TempSrc__SHIFT 0x8 +#define FAN_TABLE_9__FdoMax_MASK 0xffff0000 +#define FAN_TABLE_9__FdoMax__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_28__Reserved_0_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_28__Reserved_0__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_29__Reserved_1_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_29__Reserved_1__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_30__Reserved_2_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_30__Reserved_2__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff +#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00 +#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8 +#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000 +#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10 +#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000 +#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18 +#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff +#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0 +#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00 +#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8 +#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000 +#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10 +#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000 +#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18 +#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff +#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0 +#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00 +#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8 +#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000 +#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10 +#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000 +#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18 +#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff +#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0 +#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00 +#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8 +#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000 +#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10 +#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000 +#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18 +#define PM_FUSES_5__VddCVid_3_MASK 0xff +#define PM_FUSES_5__VddCVid_3__SHIFT 0x0 +#define PM_FUSES_5__VddCVid_2_MASK 0xff00 +#define PM_FUSES_5__VddCVid_2__SHIFT 0x8 +#define PM_FUSES_5__VddCVid_1_MASK 0xff0000 +#define PM_FUSES_5__VddCVid_1__SHIFT 0x10 +#define PM_FUSES_5__VddCVid_0_MASK 0xff000000 +#define PM_FUSES_5__VddCVid_0__SHIFT 0x18 +#define PM_FUSES_6__VddCVid_7_MASK 0xff +#define PM_FUSES_6__VddCVid_7__SHIFT 0x0 +#define PM_FUSES_6__VddCVid_6_MASK 0xff00 +#define PM_FUSES_6__VddCVid_6__SHIFT 0x8 +#define PM_FUSES_6__VddCVid_5_MASK 0xff0000 +#define PM_FUSES_6__VddCVid_5__SHIFT 0x10 +#define PM_FUSES_6__VddCVid_4_MASK 0xff000000 +#define PM_FUSES_6__VddCVid_4__SHIFT 0x18 +#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff +#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0 +#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00 +#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8 +#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000 +#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10 +#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000 +#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18 +#define PM_FUSES_8__TDC_MAWt_MASK 0xff +#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8 +#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000 +#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10 +#define PM_FUSES_9__Reserved_MASK 0xff +#define PM_FUSES_9__Reserved__SHIFT 0x0 +#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00 +#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8 +#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000 +#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10 +#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000 +#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18 +#define PM_FUSES_10__BapmVddCVidHiSidd2_3_MASK 0xff +#define PM_FUSES_10__BapmVddCVidHiSidd2_3__SHIFT 0x0 +#define PM_FUSES_10__BapmVddCVidHiSidd2_2_MASK 0xff00 +#define PM_FUSES_10__BapmVddCVidHiSidd2_2__SHIFT 0x8 +#define PM_FUSES_10__BapmVddCVidHiSidd2_1_MASK 0xff0000 +#define PM_FUSES_10__BapmVddCVidHiSidd2_1__SHIFT 0x10 +#define PM_FUSES_10__BapmVddCVidHiSidd2_0_MASK 0xff000000 +#define PM_FUSES_10__BapmVddCVidHiSidd2_0__SHIFT 0x18 +#define PM_FUSES_11__BapmVddCVidHiSidd2_7_MASK 0xff +#define PM_FUSES_11__BapmVddCVidHiSidd2_7__SHIFT 0x0 +#define PM_FUSES_11__BapmVddCVidHiSidd2_6_MASK 0xff00 +#define PM_FUSES_11__BapmVddCVidHiSidd2_6__SHIFT 0x8 +#define PM_FUSES_11__BapmVddCVidHiSidd2_5_MASK 0xff0000 +#define PM_FUSES_11__BapmVddCVidHiSidd2_5__SHIFT 0x10 +#define PM_FUSES_11__BapmVddCVidHiSidd2_4_MASK 0xff000000 +#define PM_FUSES_11__BapmVddCVidHiSidd2_4__SHIFT 0x18 +#define PM_FUSES_12__FuzzyFan_ErrorRateSetDelta_MASK 0xffff +#define PM_FUSES_12__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0 +#define PM_FUSES_12__FuzzyFan_ErrorSetDelta_MASK 0xffff0000 +#define PM_FUSES_12__FuzzyFan_ErrorSetDelta__SHIFT 0x10 +#define PM_FUSES_13__Reserved6_MASK 0xffff +#define PM_FUSES_13__Reserved6__SHIFT 0x0 +#define PM_FUSES_13__FuzzyFan_PwmSetDelta_MASK 0xffff0000 +#define PM_FUSES_13__FuzzyFan_PwmSetDelta__SHIFT 0x10 +#define PM_FUSES_14__GnbLPML_3_MASK 0xff +#define PM_FUSES_14__GnbLPML_3__SHIFT 0x0 +#define PM_FUSES_14__GnbLPML_2_MASK 0xff00 +#define PM_FUSES_14__GnbLPML_2__SHIFT 0x8 +#define PM_FUSES_14__GnbLPML_1_MASK 0xff0000 +#define PM_FUSES_14__GnbLPML_1__SHIFT 0x10 +#define PM_FUSES_14__GnbLPML_0_MASK 0xff000000 +#define PM_FUSES_14__GnbLPML_0__SHIFT 0x18 +#define PM_FUSES_15__GnbLPML_7_MASK 0xff +#define PM_FUSES_15__GnbLPML_7__SHIFT 0x0 +#define PM_FUSES_15__GnbLPML_6_MASK 0xff00 +#define PM_FUSES_15__GnbLPML_6__SHIFT 0x8 +#define PM_FUSES_15__GnbLPML_5_MASK 0xff0000 +#define PM_FUSES_15__GnbLPML_5__SHIFT 0x10 +#define PM_FUSES_15__GnbLPML_4_MASK 0xff000000 +#define PM_FUSES_15__GnbLPML_4__SHIFT 0x18 +#define PM_FUSES_16__GnbLPML_11_MASK 0xff +#define PM_FUSES_16__GnbLPML_11__SHIFT 0x0 +#define PM_FUSES_16__GnbLPML_10_MASK 0xff00 +#define PM_FUSES_16__GnbLPML_10__SHIFT 0x8 +#define PM_FUSES_16__GnbLPML_9_MASK 0xff0000 +#define PM_FUSES_16__GnbLPML_9__SHIFT 0x10 +#define PM_FUSES_16__GnbLPML_8_MASK 0xff000000 +#define PM_FUSES_16__GnbLPML_8__SHIFT 0x18 +#define PM_FUSES_17__GnbLPML_15_MASK 0xff +#define PM_FUSES_17__GnbLPML_15__SHIFT 0x0 +#define PM_FUSES_17__GnbLPML_14_MASK 0xff00 +#define PM_FUSES_17__GnbLPML_14__SHIFT 0x8 +#define PM_FUSES_17__GnbLPML_13_MASK 0xff0000 +#define PM_FUSES_17__GnbLPML_13__SHIFT 0x10 +#define PM_FUSES_17__GnbLPML_12_MASK 0xff000000 +#define PM_FUSES_17__GnbLPML_12__SHIFT 0x18 +#define PM_FUSES_18__Reserved1_1_MASK 0xff +#define PM_FUSES_18__Reserved1_1__SHIFT 0x0 +#define PM_FUSES_18__Reserved1_0_MASK 0xff00 +#define PM_FUSES_18__Reserved1_0__SHIFT 0x8 +#define PM_FUSES_18__GnbLPMLMinVid_MASK 0xff0000 +#define PM_FUSES_18__GnbLPMLMinVid__SHIFT 0x10 +#define PM_FUSES_18__GnbLPMLMaxVid_MASK 0xff000000 +#define PM_FUSES_18__GnbLPMLMaxVid__SHIFT 0x18 +#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd_MASK 0xffff +#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd__SHIFT 0x0 +#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000 +#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd__SHIFT 0x10 +#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_52__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0 +#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8 +#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3 +#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0 +#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4 +#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000 +#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe +#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000 +#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19 +#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000 +#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a +#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff +#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 +#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000 +#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11 +#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000 +#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12 +#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff +#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0 +#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00 +#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8 +#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000 +#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10 +#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000 +#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18 +#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf +#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 +#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0 +#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 +#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff +#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 +#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff +#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 +#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00 +#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL1__M_MASK 0xff0000 +#define CG_FDO_CTRL1__M__SHIFT 0x10 +#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000 +#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 +#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000 +#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e +#define CG_FDO_CTRL2__TMIN_MASK 0xff +#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 +#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800 +#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb +#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000 +#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe +#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000 +#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 +#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7 +#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 +#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8 +#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 +#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff +#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 +#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe +#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1 +#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00 +#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11 +#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000 +#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12 +#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000 +#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18 +#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000 +#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19 +#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000 +#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a +#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000 +#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b +#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000 +#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c +#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000 +#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d +#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000 +#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_INT_DATA__Z_MASK 0x7ff +#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON0_INT_DATA__VALID_MASK 0x800 +#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_INT_DATA__Z_MASK 0x7ff +#define THM_TMON1_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON1_INT_DATA__VALID_MASK 0x800 +#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON1_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 +#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40 +#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17 +#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000 +#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf +#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 +#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 +#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 +#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 +#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 +#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf +#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 +#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1 +#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0 +#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe +#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0 +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2 +#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1 +#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4 +#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10 +#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000 +#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a +#define ROM_STATUS__ROM_BUSY_MASK 0x1 +#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf +#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define ROM_INDEX__ROM_INDEX_MASK 0xffffff +#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 +#define ROM_DATA__ROM_DATA_MASK 0xffffffff +#define ROM_DATA__ROM_DATA__SHIFT 0x0 +#define ROM_START__ROM_START_MASK 0xffffff +#define ROM_START__ROM_START__SHIFT 0x0 +#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff +#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 +#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000 +#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 +#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1 +#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 +#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 + +#endif /* SMU_7_1_0_SH_MASK_H */ -- cgit v1.2.3 From c4712a10e7bbf109fa3d2dcbfea28e8df3793183 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:30:46 -0400 Subject: drm/amdgpu: add SMU 7.1.1 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h | 1123 +++++ .../drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h | 1205 +++++ .../amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h | 4864 ++++++++++++++++++++ 3 files changed, 7192 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h new file mode 100644 index 000000000000..3014d4a58c43 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h @@ -0,0 +1,1123 @@ +/* + * SMU_7_1_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_1_D_H +#define SMU_7_1_1_D_H + +#define mmGCK_SMC_IND_INDEX 0x80 +#define mmGCK0_GCK_SMC_IND_INDEX 0x80 +#define mmGCK1_GCK_SMC_IND_INDEX 0x82 +#define mmGCK2_GCK_SMC_IND_INDEX 0x84 +#define mmGCK3_GCK_SMC_IND_INDEX 0x86 +#define mmGCK_SMC_IND_DATA 0x81 +#define mmGCK0_GCK_SMC_IND_DATA 0x81 +#define mmGCK1_GCK_SMC_IND_DATA 0x83 +#define mmGCK2_GCK_SMC_IND_DATA 0x85 +#define mmGCK3_GCK_SMC_IND_DATA 0x87 +#define ixCG_DCLK_CNTL 0xc050009c +#define ixCG_DCLK_STATUS 0xc05000a0 +#define ixCG_VCLK_CNTL 0xc05000a4 +#define ixCG_VCLK_STATUS 0xc05000a8 +#define ixCG_ECLK_CNTL 0xc05000ac +#define ixCG_ECLK_STATUS 0xc05000b0 +#define ixCG_ACLK_CNTL 0xc05000dc +#define ixGCK_DFS_BYPASS_CNTL 0xc0500118 +#define ixCG_SPLL_FUNC_CNTL 0xc0500140 +#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 +#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 +#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c +#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 +#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 +#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 +#define ixSPLL_CNTL_MODE 0xc0500160 +#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 +#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +#define ixMPLL_BYPASSCLK_SEL 0xc050019c +#define ixCG_CLKPIN_CNTL 0xc05001a0 +#define ixCG_CLKPIN_CNTL_2 0xc05001a4 +#define ixCG_CLKPIN_CNTL_DC 0xc0500204 +#define ixTHM_CLK_CNTL 0xc05001a8 +#define ixMISC_CLK_CTRL 0xc05001ac +#define ixGCK_PLL_TEST_CNTL 0xc05001c0 +#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 +#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 +#define mmSMC_IND_INDEX 0x80 +#define mmSMC0_SMC_IND_INDEX 0x80 +#define mmSMC1_SMC_IND_INDEX 0x82 +#define mmSMC2_SMC_IND_INDEX 0x84 +#define mmSMC3_SMC_IND_INDEX 0x86 +#define mmSMC_IND_DATA 0x81 +#define mmSMC0_SMC_IND_DATA 0x81 +#define mmSMC1_SMC_IND_DATA 0x83 +#define mmSMC2_SMC_IND_DATA 0x85 +#define mmSMC3_SMC_IND_DATA 0x87 +#define mmSMC_IND_INDEX_0 0x80 +#define mmSMC_IND_DATA_0 0x81 +#define mmSMC_IND_INDEX_1 0x82 +#define mmSMC_IND_DATA_1 0x83 +#define mmSMC_IND_INDEX_2 0x84 +#define mmSMC_IND_DATA_2 0x85 +#define mmSMC_IND_INDEX_3 0x86 +#define mmSMC_IND_DATA_3 0x87 +#define mmSMC_IND_INDEX_4 0x88 +#define mmSMC_IND_DATA_4 0x89 +#define mmSMC_IND_INDEX_5 0x8a +#define mmSMC_IND_DATA_5 0x8b +#define mmSMC_IND_INDEX_6 0x8c +#define mmSMC_IND_DATA_6 0x8d +#define mmSMC_IND_INDEX_7 0x8e +#define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_ACCESS_CNTL 0x92 +#define mmSMC_MESSAGE_0 0x94 +#define mmSMC_RESP_0 0x95 +#define mmSMC_MESSAGE_1 0x96 +#define mmSMC_RESP_1 0x97 +#define mmSMC_MESSAGE_2 0x98 +#define mmSMC_RESP_2 0x99 +#define mmSMC_MESSAGE_3 0x9a +#define mmSMC_RESP_3 0x9b +#define mmSMC_MESSAGE_4 0x9c +#define mmSMC_RESP_4 0x9d +#define mmSMC_MESSAGE_5 0x9e +#define mmSMC_RESP_5 0x9f +#define mmSMC_MESSAGE_6 0xa0 +#define mmSMC_RESP_6 0xa1 +#define mmSMC_MESSAGE_7 0xa2 +#define mmSMC_RESP_7 0xa3 +#define mmSMC_MSG_ARG_0 0xa4 +#define mmSMC_MSG_ARG_1 0xa5 +#define mmSMC_MSG_ARG_2 0xa6 +#define mmSMC_MSG_ARG_3 0xa7 +#define mmSMC_MSG_ARG_4 0xa8 +#define mmSMC_MSG_ARG_5 0xa9 +#define mmSMC_MSG_ARG_6 0xaa +#define mmSMC_MSG_ARG_7 0xab +#define mmSMC_MESSAGE_8 0xb5 +#define mmSMC_RESP_8 0xb6 +#define mmSMC_MESSAGE_9 0xb7 +#define mmSMC_RESP_9 0xb8 +#define mmSMC_MESSAGE_10 0xb9 +#define mmSMC_RESP_10 0xba +#define mmSMC_MESSAGE_11 0xbb +#define mmSMC_RESP_11 0xbc +#define mmSMC_MSG_ARG_8 0xbd +#define mmSMC_MSG_ARG_9 0xbe +#define mmSMC_MSG_ARG_10 0xbf +#define mmSMC_MSG_ARG_11 0x93 +#define ixSMC_SYSCON_RESET_CNTL 0x80000000 +#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 +#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 +#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c +#define ixSMC_SYSCON_MISC_CNTL 0x80000010 +#define ixSMC_SYSCON_MSG_ARG_0 0x80000068 +#define ixSMC_PC_C 0x80000370 +#define ixSMC_SCRATCH9 0x80000424 +#define mmGPIOPAD_SW_INT_STAT 0x180 +#define mmGPIOPAD_STRENGTH 0x181 +#define mmGPIOPAD_MASK 0x182 +#define mmGPIOPAD_A 0x183 +#define mmGPIOPAD_EN 0x184 +#define mmGPIOPAD_Y 0x185 +#define mmGPIOPAD_PINSTRAPS 0x186 +#define mmGPIOPAD_INT_STAT_EN 0x187 +#define mmGPIOPAD_INT_STAT 0x188 +#define mmGPIOPAD_INT_STAT_AK 0x189 +#define mmGPIOPAD_INT_EN 0x18a +#define mmGPIOPAD_INT_TYPE 0x18b +#define mmGPIOPAD_INT_POLARITY 0x18c +#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d +#define mmGPIOPAD_RCVR_SEL 0x191 +#define mmGPIOPAD_PU_EN 0x192 +#define mmGPIOPAD_PD_EN 0x193 +#define mmCG_FPS_CNT 0x1b6 +#define mmSMU_IND_INDEX_0 0x1a6 +#define mmSMU_IND_DATA_0 0x1a7 +#define mmSMU_IND_INDEX_1 0x1a8 +#define mmSMU_IND_DATA_1 0x1a9 +#define mmSMU_IND_INDEX_2 0x1aa +#define mmSMU_IND_DATA_2 0x1ab +#define mmSMU_IND_INDEX_3 0x1ac +#define mmSMU_IND_DATA_3 0x1ad +#define mmSMU_IND_INDEX_4 0x1ae +#define mmSMU_IND_DATA_4 0x1af +#define mmSMU_IND_INDEX_5 0x1b0 +#define mmSMU_IND_DATA_5 0x1b1 +#define mmSMU_IND_INDEX_6 0x1b2 +#define mmSMU_IND_DATA_6 0x1b3 +#define mmSMU_IND_INDEX_7 0x1b4 +#define mmSMU_IND_DATA_7 0x1b5 +#define mmSMU_SMC_IND_INDEX 0x80 +#define mmSMU0_SMU_SMC_IND_INDEX 0x80 +#define mmSMU1_SMU_SMC_IND_INDEX 0x82 +#define mmSMU2_SMU_SMC_IND_INDEX 0x84 +#define mmSMU3_SMU_SMC_IND_INDEX 0x86 +#define mmSMU_SMC_IND_DATA 0x81 +#define mmSMU0_SMU_SMC_IND_DATA 0x81 +#define mmSMU1_SMU_SMC_IND_DATA 0x83 +#define mmSMU2_SMU_SMC_IND_DATA 0x85 +#define mmSMU3_SMU_SMC_IND_DATA 0x87 +#define ixRCU_UC_EVENTS 0xc0000004 +#define ixRCU_MISC_CTRL 0xc0000010 +#define ixCC_RCU_FUSES 0xc00c0000 +#define ixCC_SMU_MISC_FUSES 0xc00c0004 +#define ixCC_SCLK_VID_FUSES 0xc00c0008 +#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c +#define ixCC_GIO_IOC_FUSES 0xc00c0010 +#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c +#define ixCC_TST_ID_STRAPS 0xc00c0020 +#define ixCC_FCTRL_FUSES 0xc00c0024 +#define ixCC_HARVEST_FUSES 0xc00c0028 +#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 +#define ixSMU_STATUS 0xe0003088 +#define ixSMU_FIRMWARE 0xe00030a4 +#define ixSMU_INPUT_DATA 0xe00030b8 +#define ixSMU_EFUSE_0 0xc0100000 +#define ixMCARB_DRAM_TIMING_TABLE_1 0x33018 +#define ixMCARB_DRAM_TIMING_TABLE_2 0x3301c +#define ixMCARB_DRAM_TIMING_TABLE_3 0x33020 +#define ixMCARB_DRAM_TIMING_TABLE_4 0x33024 +#define ixMCARB_DRAM_TIMING_TABLE_5 0x33028 +#define ixMCARB_DRAM_TIMING_TABLE_6 0x3302c +#define ixMCARB_DRAM_TIMING_TABLE_7 0x33030 +#define ixMCARB_DRAM_TIMING_TABLE_8 0x33034 +#define ixMCARB_DRAM_TIMING_TABLE_9 0x33038 +#define ixMCARB_DRAM_TIMING_TABLE_10 0x3303c +#define ixMCARB_DRAM_TIMING_TABLE_11 0x33040 +#define ixMCARB_DRAM_TIMING_TABLE_12 0x33044 +#define ixMCARB_DRAM_TIMING_TABLE_13 0x33048 +#define ixMCARB_DRAM_TIMING_TABLE_14 0x3304c +#define ixMCARB_DRAM_TIMING_TABLE_15 0x33050 +#define ixMCARB_DRAM_TIMING_TABLE_16 0x33054 +#define ixMCARB_DRAM_TIMING_TABLE_17 0x33058 +#define ixMCARB_DRAM_TIMING_TABLE_18 0x3305c +#define ixMCARB_DRAM_TIMING_TABLE_19 0x33060 +#define ixMCARB_DRAM_TIMING_TABLE_20 0x33064 +#define ixMCARB_DRAM_TIMING_TABLE_21 0x33068 +#define ixMCARB_DRAM_TIMING_TABLE_22 0x3306c +#define ixMCARB_DRAM_TIMING_TABLE_23 0x33070 +#define ixMCARB_DRAM_TIMING_TABLE_24 0x33074 +#define ixMCARB_DRAM_TIMING_TABLE_25 0x33078 +#define ixMCARB_DRAM_TIMING_TABLE_26 0x3307c +#define ixMCARB_DRAM_TIMING_TABLE_27 0x33080 +#define ixMCARB_DRAM_TIMING_TABLE_28 0x33084 +#define ixMCARB_DRAM_TIMING_TABLE_29 0x33088 +#define ixMCARB_DRAM_TIMING_TABLE_30 0x3308c +#define ixMCARB_DRAM_TIMING_TABLE_31 0x33090 +#define ixMCARB_DRAM_TIMING_TABLE_32 0x33094 +#define ixMCARB_DRAM_TIMING_TABLE_33 0x33098 +#define ixMCARB_DRAM_TIMING_TABLE_34 0x3309c +#define ixMCARB_DRAM_TIMING_TABLE_35 0x330a0 +#define ixMCARB_DRAM_TIMING_TABLE_36 0x330a4 +#define ixMCARB_DRAM_TIMING_TABLE_37 0x330a8 +#define ixMCARB_DRAM_TIMING_TABLE_38 0x330ac +#define ixMCARB_DRAM_TIMING_TABLE_39 0x330b0 +#define ixMCARB_DRAM_TIMING_TABLE_40 0x330b4 +#define ixMCARB_DRAM_TIMING_TABLE_41 0x330b8 +#define ixMCARB_DRAM_TIMING_TABLE_42 0x330bc +#define ixMCARB_DRAM_TIMING_TABLE_43 0x330c0 +#define ixMCARB_DRAM_TIMING_TABLE_44 0x330c4 +#define ixMCARB_DRAM_TIMING_TABLE_45 0x330c8 +#define ixMCARB_DRAM_TIMING_TABLE_46 0x330cc +#define ixMCARB_DRAM_TIMING_TABLE_47 0x330d0 +#define ixMCARB_DRAM_TIMING_TABLE_48 0x330d4 +#define ixMCARB_DRAM_TIMING_TABLE_49 0x330d8 +#define ixMCARB_DRAM_TIMING_TABLE_50 0x330dc +#define ixMCARB_DRAM_TIMING_TABLE_51 0x330e0 +#define ixMCARB_DRAM_TIMING_TABLE_52 0x330e4 +#define ixMCARB_DRAM_TIMING_TABLE_53 0x330e8 +#define ixMCARB_DRAM_TIMING_TABLE_54 0x330ec +#define ixMCARB_DRAM_TIMING_TABLE_55 0x330f0 +#define ixMCARB_DRAM_TIMING_TABLE_56 0x330f4 +#define ixMCARB_DRAM_TIMING_TABLE_57 0x330f8 +#define ixMCARB_DRAM_TIMING_TABLE_58 0x330fc +#define ixMCARB_DRAM_TIMING_TABLE_59 0x33100 +#define ixMCARB_DRAM_TIMING_TABLE_60 0x33104 +#define ixMCARB_DRAM_TIMING_TABLE_61 0x33108 +#define ixMCARB_DRAM_TIMING_TABLE_62 0x3310c +#define ixMCARB_DRAM_TIMING_TABLE_63 0x33110 +#define ixMCARB_DRAM_TIMING_TABLE_64 0x33114 +#define ixMCARB_DRAM_TIMING_TABLE_65 0x33118 +#define ixMCARB_DRAM_TIMING_TABLE_66 0x3311c +#define ixMCARB_DRAM_TIMING_TABLE_67 0x33120 +#define ixMCARB_DRAM_TIMING_TABLE_68 0x33124 +#define ixMCARB_DRAM_TIMING_TABLE_69 0x33128 +#define ixMCARB_DRAM_TIMING_TABLE_70 0x3312c +#define ixMCARB_DRAM_TIMING_TABLE_71 0x33130 +#define ixMCARB_DRAM_TIMING_TABLE_72 0x33134 +#define ixMCARB_DRAM_TIMING_TABLE_73 0x33138 +#define ixMCARB_DRAM_TIMING_TABLE_74 0x3313c +#define ixMCARB_DRAM_TIMING_TABLE_75 0x33140 +#define ixMCARB_DRAM_TIMING_TABLE_76 0x33144 +#define ixMCARB_DRAM_TIMING_TABLE_77 0x33148 +#define ixMCARB_DRAM_TIMING_TABLE_78 0x3314c +#define ixMCARB_DRAM_TIMING_TABLE_79 0x33150 +#define ixMCARB_DRAM_TIMING_TABLE_80 0x33154 +#define ixMCARB_DRAM_TIMING_TABLE_81 0x33158 +#define ixMCARB_DRAM_TIMING_TABLE_82 0x3315c +#define ixMCARB_DRAM_TIMING_TABLE_83 0x33160 +#define ixMCARB_DRAM_TIMING_TABLE_84 0x33164 +#define ixMCARB_DRAM_TIMING_TABLE_85 0x33168 +#define ixMCARB_DRAM_TIMING_TABLE_86 0x3316c +#define ixMCARB_DRAM_TIMING_TABLE_87 0x33170 +#define ixMCARB_DRAM_TIMING_TABLE_88 0x33174 +#define ixMCARB_DRAM_TIMING_TABLE_89 0x33178 +#define ixMCARB_DRAM_TIMING_TABLE_90 0x3317c +#define ixMCARB_DRAM_TIMING_TABLE_91 0x33180 +#define ixMCARB_DRAM_TIMING_TABLE_92 0x33184 +#define ixMCARB_DRAM_TIMING_TABLE_93 0x33188 +#define ixMCARB_DRAM_TIMING_TABLE_94 0x3318c +#define ixMCARB_DRAM_TIMING_TABLE_95 0x33190 +#define ixMCARB_DRAM_TIMING_TABLE_96 0x33194 +#define ixMC_REGISTERS_TABLE_1 0x33198 +#define ixMC_REGISTERS_TABLE_2 0x3319c +#define ixMC_REGISTERS_TABLE_3 0x331a0 +#define ixMC_REGISTERS_TABLE_4 0x331a4 +#define ixMC_REGISTERS_TABLE_5 0x331a8 +#define ixMC_REGISTERS_TABLE_6 0x331ac +#define ixMC_REGISTERS_TABLE_7 0x331b0 +#define ixMC_REGISTERS_TABLE_8 0x331b4 +#define ixMC_REGISTERS_TABLE_9 0x331b8 +#define ixMC_REGISTERS_TABLE_10 0x331bc +#define ixMC_REGISTERS_TABLE_11 0x331c0 +#define ixMC_REGISTERS_TABLE_12 0x331c4 +#define ixMC_REGISTERS_TABLE_13 0x331c8 +#define ixMC_REGISTERS_TABLE_14 0x331cc +#define ixMC_REGISTERS_TABLE_15 0x331d0 +#define ixMC_REGISTERS_TABLE_16 0x331d4 +#define ixMC_REGISTERS_TABLE_17 0x331d8 +#define ixMC_REGISTERS_TABLE_18 0x331dc +#define ixMC_REGISTERS_TABLE_19 0x331e0 +#define ixMC_REGISTERS_TABLE_20 0x331e4 +#define ixMC_REGISTERS_TABLE_21 0x331e8 +#define ixMC_REGISTERS_TABLE_22 0x331ec +#define ixMC_REGISTERS_TABLE_23 0x331f0 +#define ixMC_REGISTERS_TABLE_24 0x331f4 +#define ixMC_REGISTERS_TABLE_25 0x331f8 +#define ixMC_REGISTERS_TABLE_26 0x331fc +#define ixMC_REGISTERS_TABLE_27 0x33200 +#define ixMC_REGISTERS_TABLE_28 0x33204 +#define ixMC_REGISTERS_TABLE_29 0x33208 +#define ixMC_REGISTERS_TABLE_30 0x3320c +#define ixMC_REGISTERS_TABLE_31 0x33210 +#define ixMC_REGISTERS_TABLE_32 0x33214 +#define ixMC_REGISTERS_TABLE_33 0x33218 +#define ixMC_REGISTERS_TABLE_34 0x3321c +#define ixMC_REGISTERS_TABLE_35 0x33220 +#define ixMC_REGISTERS_TABLE_36 0x33224 +#define ixMC_REGISTERS_TABLE_37 0x33228 +#define ixMC_REGISTERS_TABLE_38 0x3322c +#define ixMC_REGISTERS_TABLE_39 0x33230 +#define ixMC_REGISTERS_TABLE_40 0x33234 +#define ixMC_REGISTERS_TABLE_41 0x33238 +#define ixMC_REGISTERS_TABLE_42 0x3323c +#define ixMC_REGISTERS_TABLE_43 0x33240 +#define ixMC_REGISTERS_TABLE_44 0x33244 +#define ixMC_REGISTERS_TABLE_45 0x33248 +#define ixMC_REGISTERS_TABLE_46 0x3324c +#define ixMC_REGISTERS_TABLE_47 0x33250 +#define ixMC_REGISTERS_TABLE_48 0x33254 +#define ixMC_REGISTERS_TABLE_49 0x33258 +#define ixMC_REGISTERS_TABLE_50 0x3325c +#define ixMC_REGISTERS_TABLE_51 0x33260 +#define ixMC_REGISTERS_TABLE_52 0x33264 +#define ixMC_REGISTERS_TABLE_53 0x33268 +#define ixMC_REGISTERS_TABLE_54 0x3326c +#define ixMC_REGISTERS_TABLE_55 0x33270 +#define ixMC_REGISTERS_TABLE_56 0x33274 +#define ixMC_REGISTERS_TABLE_57 0x33278 +#define ixMC_REGISTERS_TABLE_58 0x3327c +#define ixMC_REGISTERS_TABLE_59 0x33280 +#define ixMC_REGISTERS_TABLE_60 0x33284 +#define ixMC_REGISTERS_TABLE_61 0x33288 +#define ixMC_REGISTERS_TABLE_62 0x3328c +#define ixMC_REGISTERS_TABLE_63 0x33290 +#define ixMC_REGISTERS_TABLE_64 0x33294 +#define ixMC_REGISTERS_TABLE_65 0x33298 +#define ixMC_REGISTERS_TABLE_66 0x3329c +#define ixMC_REGISTERS_TABLE_67 0x332a0 +#define ixMC_REGISTERS_TABLE_68 0x332a4 +#define ixMC_REGISTERS_TABLE_69 0x332a8 +#define ixMC_REGISTERS_TABLE_70 0x332ac +#define ixMC_REGISTERS_TABLE_71 0x332b0 +#define ixMC_REGISTERS_TABLE_72 0x332b4 +#define ixMC_REGISTERS_TABLE_73 0x332b8 +#define ixMC_REGISTERS_TABLE_74 0x332bc +#define ixMC_REGISTERS_TABLE_75 0x332c0 +#define ixMC_REGISTERS_TABLE_76 0x332c4 +#define ixMC_REGISTERS_TABLE_77 0x332c8 +#define ixMC_REGISTERS_TABLE_78 0x332cc +#define ixMC_REGISTERS_TABLE_79 0x332d0 +#define ixMC_REGISTERS_TABLE_80 0x332d4 +#define ixMC_REGISTERS_TABLE_81 0x332d8 +#define ixDPM_TABLE_1 0x332dc +#define ixDPM_TABLE_2 0x332e0 +#define ixDPM_TABLE_3 0x332e4 +#define ixDPM_TABLE_4 0x332e8 +#define ixDPM_TABLE_5 0x332ec +#define ixDPM_TABLE_6 0x332f0 +#define ixDPM_TABLE_7 0x332f4 +#define ixDPM_TABLE_8 0x332f8 +#define ixDPM_TABLE_9 0x332fc +#define ixDPM_TABLE_10 0x33300 +#define ixDPM_TABLE_11 0x33304 +#define ixDPM_TABLE_12 0x33308 +#define ixDPM_TABLE_13 0x3330c +#define ixDPM_TABLE_14 0x33310 +#define ixDPM_TABLE_15 0x33314 +#define ixDPM_TABLE_16 0x33318 +#define ixDPM_TABLE_17 0x3331c +#define ixDPM_TABLE_18 0x33320 +#define ixDPM_TABLE_19 0x33324 +#define ixDPM_TABLE_20 0x33328 +#define ixDPM_TABLE_21 0x3332c +#define ixDPM_TABLE_22 0x33330 +#define ixDPM_TABLE_23 0x33334 +#define ixDPM_TABLE_24 0x33338 +#define ixDPM_TABLE_25 0x3333c +#define ixDPM_TABLE_26 0x33340 +#define ixDPM_TABLE_27 0x33344 +#define ixDPM_TABLE_28 0x33348 +#define ixDPM_TABLE_29 0x3334c +#define ixDPM_TABLE_30 0x33350 +#define ixDPM_TABLE_31 0x33354 +#define ixDPM_TABLE_32 0x33358 +#define ixDPM_TABLE_33 0x3335c +#define ixDPM_TABLE_34 0x33360 +#define ixDPM_TABLE_35 0x33364 +#define ixDPM_TABLE_36 0x33368 +#define ixDPM_TABLE_37 0x3336c +#define ixDPM_TABLE_38 0x33370 +#define ixDPM_TABLE_39 0x33374 +#define ixDPM_TABLE_40 0x33378 +#define ixDPM_TABLE_41 0x3337c +#define ixDPM_TABLE_42 0x33380 +#define ixDPM_TABLE_43 0x33384 +#define ixDPM_TABLE_44 0x33388 +#define ixDPM_TABLE_45 0x3338c +#define ixDPM_TABLE_46 0x33390 +#define ixDPM_TABLE_47 0x33394 +#define ixDPM_TABLE_48 0x33398 +#define ixDPM_TABLE_49 0x3339c +#define ixDPM_TABLE_50 0x333a0 +#define ixDPM_TABLE_51 0x333a4 +#define ixDPM_TABLE_52 0x333a8 +#define ixDPM_TABLE_53 0x333ac +#define ixDPM_TABLE_54 0x333b0 +#define ixDPM_TABLE_55 0x333b4 +#define ixDPM_TABLE_56 0x333b8 +#define ixDPM_TABLE_57 0x333bc +#define ixDPM_TABLE_58 0x333c0 +#define ixDPM_TABLE_59 0x333c4 +#define ixDPM_TABLE_60 0x333c8 +#define ixDPM_TABLE_61 0x333cc +#define ixDPM_TABLE_62 0x333d0 +#define ixDPM_TABLE_63 0x333d4 +#define ixDPM_TABLE_64 0x333d8 +#define ixDPM_TABLE_65 0x333dc +#define ixDPM_TABLE_66 0x333e0 +#define ixDPM_TABLE_67 0x333e4 +#define ixDPM_TABLE_68 0x333e8 +#define ixDPM_TABLE_69 0x333ec +#define ixDPM_TABLE_70 0x333f0 +#define ixDPM_TABLE_71 0x333f4 +#define ixDPM_TABLE_72 0x333f8 +#define ixDPM_TABLE_73 0x333fc +#define ixDPM_TABLE_74 0x33400 +#define ixDPM_TABLE_75 0x33404 +#define ixDPM_TABLE_76 0x33408 +#define ixDPM_TABLE_77 0x3340c +#define ixDPM_TABLE_78 0x33410 +#define ixDPM_TABLE_79 0x33414 +#define ixDPM_TABLE_80 0x33418 +#define ixDPM_TABLE_81 0x3341c +#define ixDPM_TABLE_82 0x33420 +#define ixDPM_TABLE_83 0x33424 +#define ixDPM_TABLE_84 0x33428 +#define ixDPM_TABLE_85 0x3342c +#define ixDPM_TABLE_86 0x33430 +#define ixDPM_TABLE_87 0x33434 +#define ixDPM_TABLE_88 0x33438 +#define ixDPM_TABLE_89 0x3343c +#define ixDPM_TABLE_90 0x33440 +#define ixDPM_TABLE_91 0x33444 +#define ixDPM_TABLE_92 0x33448 +#define ixDPM_TABLE_93 0x3344c +#define ixDPM_TABLE_94 0x33450 +#define ixDPM_TABLE_95 0x33454 +#define ixDPM_TABLE_96 0x33458 +#define ixDPM_TABLE_97 0x3345c +#define ixDPM_TABLE_98 0x33460 +#define ixDPM_TABLE_99 0x33464 +#define ixDPM_TABLE_100 0x33468 +#define ixDPM_TABLE_101 0x3346c +#define ixDPM_TABLE_102 0x33470 +#define ixDPM_TABLE_103 0x33474 +#define ixDPM_TABLE_104 0x33478 +#define ixDPM_TABLE_105 0x3347c +#define ixDPM_TABLE_106 0x33480 +#define ixDPM_TABLE_107 0x33484 +#define ixDPM_TABLE_108 0x33488 +#define ixDPM_TABLE_109 0x3348c +#define ixDPM_TABLE_110 0x33490 +#define ixDPM_TABLE_111 0x33494 +#define ixDPM_TABLE_112 0x33498 +#define ixDPM_TABLE_113 0x3349c +#define ixDPM_TABLE_114 0x334a0 +#define ixDPM_TABLE_115 0x334a4 +#define ixDPM_TABLE_116 0x334a8 +#define ixDPM_TABLE_117 0x334ac +#define ixDPM_TABLE_118 0x334b0 +#define ixDPM_TABLE_119 0x334b4 +#define ixDPM_TABLE_120 0x334b8 +#define ixDPM_TABLE_121 0x334bc +#define ixDPM_TABLE_122 0x334c0 +#define ixDPM_TABLE_123 0x334c4 +#define ixDPM_TABLE_124 0x334c8 +#define ixDPM_TABLE_125 0x334cc +#define ixDPM_TABLE_126 0x334d0 +#define ixDPM_TABLE_127 0x334d4 +#define ixDPM_TABLE_128 0x334d8 +#define ixDPM_TABLE_129 0x334dc +#define ixDPM_TABLE_130 0x334e0 +#define ixDPM_TABLE_131 0x334e4 +#define ixDPM_TABLE_132 0x334e8 +#define ixDPM_TABLE_133 0x334ec +#define ixDPM_TABLE_134 0x334f0 +#define ixDPM_TABLE_135 0x334f4 +#define ixDPM_TABLE_136 0x334f8 +#define ixDPM_TABLE_137 0x334fc +#define ixDPM_TABLE_138 0x33500 +#define ixDPM_TABLE_139 0x33504 +#define ixDPM_TABLE_140 0x33508 +#define ixDPM_TABLE_141 0x3350c +#define ixDPM_TABLE_142 0x33510 +#define ixDPM_TABLE_143 0x33514 +#define ixDPM_TABLE_144 0x33518 +#define ixDPM_TABLE_145 0x3351c +#define ixDPM_TABLE_146 0x33520 +#define ixDPM_TABLE_147 0x33524 +#define ixDPM_TABLE_148 0x33528 +#define ixDPM_TABLE_149 0x3352c +#define ixDPM_TABLE_150 0x33530 +#define ixDPM_TABLE_151 0x33534 +#define ixDPM_TABLE_152 0x33538 +#define ixDPM_TABLE_153 0x3353c +#define ixDPM_TABLE_154 0x33540 +#define ixDPM_TABLE_155 0x33544 +#define ixDPM_TABLE_156 0x33548 +#define ixDPM_TABLE_157 0x3354c +#define ixDPM_TABLE_158 0x33550 +#define ixDPM_TABLE_159 0x33554 +#define ixDPM_TABLE_160 0x33558 +#define ixDPM_TABLE_161 0x3355c +#define ixDPM_TABLE_162 0x33560 +#define ixDPM_TABLE_163 0x33564 +#define ixDPM_TABLE_164 0x33568 +#define ixDPM_TABLE_165 0x3356c +#define ixDPM_TABLE_166 0x33570 +#define ixDPM_TABLE_167 0x33574 +#define ixDPM_TABLE_168 0x33578 +#define ixDPM_TABLE_169 0x3357c +#define ixDPM_TABLE_170 0x33580 +#define ixDPM_TABLE_171 0x33584 +#define ixDPM_TABLE_172 0x33588 +#define ixDPM_TABLE_173 0x3358c +#define ixDPM_TABLE_174 0x33590 +#define ixDPM_TABLE_175 0x33594 +#define ixDPM_TABLE_176 0x33598 +#define ixDPM_TABLE_177 0x3359c +#define ixDPM_TABLE_178 0x335a0 +#define ixDPM_TABLE_179 0x335a4 +#define ixDPM_TABLE_180 0x335a8 +#define ixDPM_TABLE_181 0x335ac +#define ixDPM_TABLE_182 0x335b0 +#define ixDPM_TABLE_183 0x335b4 +#define ixDPM_TABLE_184 0x335b8 +#define ixDPM_TABLE_185 0x335bc +#define ixDPM_TABLE_186 0x335c0 +#define ixDPM_TABLE_187 0x335c4 +#define ixDPM_TABLE_188 0x335c8 +#define ixDPM_TABLE_189 0x335cc +#define ixDPM_TABLE_190 0x335d0 +#define ixDPM_TABLE_191 0x335d4 +#define ixDPM_TABLE_192 0x335d8 +#define ixDPM_TABLE_193 0x335dc +#define ixDPM_TABLE_194 0x335e0 +#define ixDPM_TABLE_195 0x335e4 +#define ixDPM_TABLE_196 0x335e8 +#define ixDPM_TABLE_197 0x335ec +#define ixDPM_TABLE_198 0x335f0 +#define ixDPM_TABLE_199 0x335f4 +#define ixDPM_TABLE_200 0x335f8 +#define ixDPM_TABLE_201 0x335fc +#define ixDPM_TABLE_202 0x33600 +#define ixDPM_TABLE_203 0x33604 +#define ixDPM_TABLE_204 0x33608 +#define ixDPM_TABLE_205 0x3360c +#define ixDPM_TABLE_206 0x33610 +#define ixDPM_TABLE_207 0x33614 +#define ixDPM_TABLE_208 0x33618 +#define ixDPM_TABLE_209 0x3361c +#define ixDPM_TABLE_210 0x33620 +#define ixDPM_TABLE_211 0x33624 +#define ixDPM_TABLE_212 0x33628 +#define ixDPM_TABLE_213 0x3362c +#define ixDPM_TABLE_214 0x33630 +#define ixDPM_TABLE_215 0x33634 +#define ixDPM_TABLE_216 0x33638 +#define ixDPM_TABLE_217 0x3363c +#define ixDPM_TABLE_218 0x33640 +#define ixDPM_TABLE_219 0x33644 +#define ixDPM_TABLE_220 0x33648 +#define ixDPM_TABLE_221 0x3364c +#define ixDPM_TABLE_222 0x33650 +#define ixDPM_TABLE_223 0x33654 +#define ixDPM_TABLE_224 0x33658 +#define ixDPM_TABLE_225 0x3365c +#define ixDPM_TABLE_226 0x33660 +#define ixDPM_TABLE_227 0x33664 +#define ixDPM_TABLE_228 0x33668 +#define ixDPM_TABLE_229 0x3366c +#define ixDPM_TABLE_230 0x33670 +#define ixDPM_TABLE_231 0x33674 +#define ixDPM_TABLE_232 0x33678 +#define ixDPM_TABLE_233 0x3367c +#define ixDPM_TABLE_234 0x33680 +#define ixDPM_TABLE_235 0x33684 +#define ixDPM_TABLE_236 0x33688 +#define ixDPM_TABLE_237 0x3368c +#define ixDPM_TABLE_238 0x33690 +#define ixDPM_TABLE_239 0x33694 +#define ixDPM_TABLE_240 0x33698 +#define ixDPM_TABLE_241 0x3369c +#define ixDPM_TABLE_242 0x336a0 +#define ixDPM_TABLE_243 0x336a4 +#define ixDPM_TABLE_244 0x336a8 +#define ixDPM_TABLE_245 0x336ac +#define ixDPM_TABLE_246 0x336b0 +#define ixDPM_TABLE_247 0x336b4 +#define ixDPM_TABLE_248 0x336b8 +#define ixDPM_TABLE_249 0x336bc +#define ixDPM_TABLE_250 0x336c0 +#define ixDPM_TABLE_251 0x336c4 +#define ixDPM_TABLE_252 0x336c8 +#define ixDPM_TABLE_253 0x336cc +#define ixDPM_TABLE_254 0x336d0 +#define ixDPM_TABLE_255 0x336d4 +#define ixDPM_TABLE_256 0x336d8 +#define ixDPM_TABLE_257 0x336dc +#define ixDPM_TABLE_258 0x336e0 +#define ixDPM_TABLE_259 0x336e4 +#define ixDPM_TABLE_260 0x336e8 +#define ixDPM_TABLE_261 0x336ec +#define ixDPM_TABLE_262 0x336f0 +#define ixDPM_TABLE_263 0x336f4 +#define ixDPM_TABLE_264 0x336f8 +#define ixDPM_TABLE_265 0x336fc +#define ixDPM_TABLE_266 0x33700 +#define ixDPM_TABLE_267 0x33704 +#define ixDPM_TABLE_268 0x33708 +#define ixDPM_TABLE_269 0x3370c +#define ixDPM_TABLE_270 0x33710 +#define ixDPM_TABLE_271 0x33714 +#define ixDPM_TABLE_272 0x33718 +#define ixDPM_TABLE_273 0x3371c +#define ixDPM_TABLE_274 0x33720 +#define ixDPM_TABLE_275 0x33724 +#define ixDPM_TABLE_276 0x33728 +#define ixDPM_TABLE_277 0x3372c +#define ixDPM_TABLE_278 0x33730 +#define ixDPM_TABLE_279 0x33734 +#define ixDPM_TABLE_280 0x33738 +#define ixDPM_TABLE_281 0x3373c +#define ixDPM_TABLE_282 0x33740 +#define ixDPM_TABLE_283 0x33744 +#define ixDPM_TABLE_284 0x33748 +#define ixDPM_TABLE_285 0x3374c +#define ixDPM_TABLE_286 0x33750 +#define ixDPM_TABLE_287 0x33754 +#define ixDPM_TABLE_288 0x33758 +#define ixDPM_TABLE_289 0x3375c +#define ixDPM_TABLE_290 0x33760 +#define ixDPM_TABLE_291 0x33764 +#define ixDPM_TABLE_292 0x33768 +#define ixDPM_TABLE_293 0x3376c +#define ixDPM_TABLE_294 0x33770 +#define ixDPM_TABLE_295 0x33774 +#define ixDPM_TABLE_296 0x33778 +#define ixDPM_TABLE_297 0x3377c +#define ixDPM_TABLE_298 0x33780 +#define ixDPM_TABLE_299 0x33784 +#define ixDPM_TABLE_300 0x33788 +#define ixDPM_TABLE_301 0x3378c +#define ixDPM_TABLE_302 0x33790 +#define ixDPM_TABLE_303 0x33794 +#define ixDPM_TABLE_304 0x33798 +#define ixDPM_TABLE_305 0x3379c +#define ixDPM_TABLE_306 0x337a0 +#define ixDPM_TABLE_307 0x337a4 +#define ixDPM_TABLE_308 0x337a8 +#define ixDPM_TABLE_309 0x337ac +#define ixDPM_TABLE_310 0x337b0 +#define ixDPM_TABLE_311 0x337b4 +#define ixDPM_TABLE_312 0x337b8 +#define ixDPM_TABLE_313 0x337bc +#define ixDPM_TABLE_314 0x337c0 +#define ixDPM_TABLE_315 0x337c4 +#define ixDPM_TABLE_316 0x337c8 +#define ixDPM_TABLE_317 0x337cc +#define ixDPM_TABLE_318 0x337d0 +#define ixDPM_TABLE_319 0x337d4 +#define ixDPM_TABLE_320 0x337d8 +#define ixDPM_TABLE_321 0x337dc +#define ixDPM_TABLE_322 0x337e0 +#define ixDPM_TABLE_323 0x337e4 +#define ixDPM_TABLE_324 0x337e8 +#define ixDPM_TABLE_325 0x337ec +#define ixDPM_TABLE_326 0x337f0 +#define ixDPM_TABLE_327 0x337f4 +#define ixDPM_TABLE_328 0x337f8 +#define ixDPM_TABLE_329 0x337fc +#define ixDPM_TABLE_330 0x33800 +#define ixDPM_TABLE_331 0x33804 +#define ixDPM_TABLE_332 0x33808 +#define ixDPM_TABLE_333 0x3380c +#define ixDPM_TABLE_334 0x33810 +#define ixDPM_TABLE_335 0x33814 +#define ixDPM_TABLE_336 0x33818 +#define ixDPM_TABLE_337 0x3381c +#define ixDPM_TABLE_338 0x33820 +#define ixDPM_TABLE_339 0x33824 +#define ixDPM_TABLE_340 0x33828 +#define ixDPM_TABLE_341 0x3382c +#define ixDPM_TABLE_342 0x33830 +#define ixDPM_TABLE_343 0x33834 +#define ixDPM_TABLE_344 0x33838 +#define ixDPM_TABLE_345 0x3383c +#define ixDPM_TABLE_346 0x33840 +#define ixDPM_TABLE_347 0x33844 +#define ixDPM_TABLE_348 0x33848 +#define ixDPM_TABLE_349 0x3384c +#define ixDPM_TABLE_350 0x33850 +#define ixDPM_TABLE_351 0x33854 +#define ixDPM_TABLE_352 0x33858 +#define ixDPM_TABLE_353 0x3385c +#define ixDPM_TABLE_354 0x33860 +#define ixDPM_TABLE_355 0x33864 +#define ixDPM_TABLE_356 0x33868 +#define ixDPM_TABLE_357 0x3386c +#define ixDPM_TABLE_358 0x33870 +#define ixDPM_TABLE_359 0x33874 +#define ixDPM_TABLE_360 0x33878 +#define ixDPM_TABLE_361 0x3387c +#define ixDPM_TABLE_362 0x33880 +#define ixDPM_TABLE_363 0x33884 +#define ixDPM_TABLE_364 0x33888 +#define ixDPM_TABLE_365 0x3388c +#define ixDPM_TABLE_366 0x33890 +#define ixDPM_TABLE_367 0x33894 +#define ixDPM_TABLE_368 0x33898 +#define ixDPM_TABLE_369 0x3389c +#define ixDPM_TABLE_370 0x338a0 +#define ixSOFT_REGISTERS_TABLE_1 0x338c8 +#define ixSOFT_REGISTERS_TABLE_2 0x338cc +#define ixSOFT_REGISTERS_TABLE_3 0x338d0 +#define ixSOFT_REGISTERS_TABLE_4 0x338d4 +#define ixSOFT_REGISTERS_TABLE_5 0x338d8 +#define ixSOFT_REGISTERS_TABLE_6 0x338dc +#define ixSOFT_REGISTERS_TABLE_7 0x338e0 +#define ixSOFT_REGISTERS_TABLE_8 0x338e4 +#define ixSOFT_REGISTERS_TABLE_9 0x338e8 +#define ixSOFT_REGISTERS_TABLE_10 0x338ec +#define ixSOFT_REGISTERS_TABLE_11 0x338f0 +#define ixSOFT_REGISTERS_TABLE_12 0x338f4 +#define ixSOFT_REGISTERS_TABLE_13 0x338f8 +#define ixSOFT_REGISTERS_TABLE_14 0x338fc +#define ixSOFT_REGISTERS_TABLE_15 0x33900 +#define ixSOFT_REGISTERS_TABLE_16 0x33904 +#define ixSOFT_REGISTERS_TABLE_17 0x33908 +#define ixSOFT_REGISTERS_TABLE_18 0x3390c +#define ixSOFT_REGISTERS_TABLE_19 0x33910 +#define ixSOFT_REGISTERS_TABLE_20 0x33914 +#define ixSOFT_REGISTERS_TABLE_21 0x33918 +#define ixSOFT_REGISTERS_TABLE_22 0x3391c +#define ixSOFT_REGISTERS_TABLE_23 0x33920 +#define ixSOFT_REGISTERS_TABLE_24 0x33924 +#define ixSOFT_REGISTERS_TABLE_25 0x33928 +#define ixSOFT_REGISTERS_TABLE_26 0x3392c +#define ixSOFT_REGISTERS_TABLE_27 0x33930 +#define ixSOFT_REGISTERS_TABLE_28 0x33934 +#define ixSOFT_REGISTERS_TABLE_29 0x33938 +#define ixFIRMWARE_FLAGS 0x33000 +#define ixTDC_STATUS 0x33004 +#define ixTDC_MV_AVERAGE 0x33008 +#define ixTDC_VRM_LIMIT 0x3300c +#define ixFEATURE_STATUS 0x33010 +#define ixENTITY_TEMPERATURES_1 0x33014 +#define ixPM_FUSES_1 0x3394c +#define ixPM_FUSES_2 0x33950 +#define ixPM_FUSES_3 0x33954 +#define ixPM_FUSES_4 0x33958 +#define ixPM_FUSES_5 0x3395c +#define ixPM_FUSES_6 0x33960 +#define ixPM_FUSES_7 0x33964 +#define ixPM_FUSES_8 0x33968 +#define ixPM_FUSES_9 0x3396c +#define ixPM_FUSES_10 0x33970 +#define ixPM_FUSES_11 0x33974 +#define ixPM_FUSES_12 0x33978 +#define ixPM_FUSES_13 0x3397c +#define ixPM_FUSES_14 0x33980 +#define ixPM_FUSES_15 0x33984 +#define ixPM_FUSES_16 0x33988 +#define ixPM_FUSES_17 0x3398c +#define ixPM_FUSES_18 0x33990 +#define ixPM_FUSES_19 0x33994 +#define ixPM_FUSES_20 0x33998 +#define ixPM_FUSES_21 0x3399c +#define ixSMU_PM_STATUS_0 0x33e00 +#define ixSMU_PM_STATUS_1 0x33e04 +#define ixSMU_PM_STATUS_2 0x33e08 +#define ixSMU_PM_STATUS_3 0x33e0c +#define ixSMU_PM_STATUS_4 0x33e10 +#define ixSMU_PM_STATUS_5 0x33e14 +#define ixSMU_PM_STATUS_6 0x33e18 +#define ixSMU_PM_STATUS_7 0x33e1c +#define ixSMU_PM_STATUS_8 0x33e20 +#define ixSMU_PM_STATUS_9 0x33e24 +#define ixSMU_PM_STATUS_10 0x33e28 +#define ixSMU_PM_STATUS_11 0x33e2c +#define ixSMU_PM_STATUS_12 0x33e30 +#define ixSMU_PM_STATUS_13 0x33e34 +#define ixSMU_PM_STATUS_14 0x33e38 +#define ixSMU_PM_STATUS_15 0x33e3c +#define ixSMU_PM_STATUS_16 0x33e40 +#define ixSMU_PM_STATUS_17 0x33e44 +#define ixSMU_PM_STATUS_18 0x33e48 +#define ixSMU_PM_STATUS_19 0x33e4c +#define ixSMU_PM_STATUS_20 0x33e50 +#define ixSMU_PM_STATUS_21 0x33e54 +#define ixSMU_PM_STATUS_22 0x33e58 +#define ixSMU_PM_STATUS_23 0x33e5c +#define ixSMU_PM_STATUS_24 0x33e60 +#define ixSMU_PM_STATUS_25 0x33e64 +#define ixSMU_PM_STATUS_26 0x33e68 +#define ixSMU_PM_STATUS_27 0x33e6c +#define ixSMU_PM_STATUS_28 0x33e70 +#define ixSMU_PM_STATUS_29 0x33e74 +#define ixSMU_PM_STATUS_30 0x33e78 +#define ixSMU_PM_STATUS_31 0x33e7c +#define ixSMU_PM_STATUS_32 0x33e80 +#define ixSMU_PM_STATUS_33 0x33e84 +#define ixSMU_PM_STATUS_34 0x33e88 +#define ixSMU_PM_STATUS_35 0x33e8c +#define ixSMU_PM_STATUS_36 0x33e90 +#define ixSMU_PM_STATUS_37 0x33e94 +#define ixSMU_PM_STATUS_38 0x33e98 +#define ixSMU_PM_STATUS_39 0x33e9c +#define ixSMU_PM_STATUS_40 0x33ea0 +#define ixSMU_PM_STATUS_41 0x33ea4 +#define ixSMU_PM_STATUS_42 0x33ea8 +#define ixSMU_PM_STATUS_43 0x33eac +#define ixSMU_PM_STATUS_44 0x33eb0 +#define ixSMU_PM_STATUS_45 0x33eb4 +#define ixSMU_PM_STATUS_46 0x33eb8 +#define ixSMU_PM_STATUS_47 0x33ebc +#define ixSMU_PM_STATUS_48 0x33ec0 +#define ixSMU_PM_STATUS_49 0x33ec4 +#define ixSMU_PM_STATUS_50 0x33ec8 +#define ixSMU_PM_STATUS_51 0x33ecc +#define ixSMU_PM_STATUS_52 0x33ed0 +#define ixSMU_PM_STATUS_53 0x33ed4 +#define ixSMU_PM_STATUS_54 0x33ed8 +#define ixSMU_PM_STATUS_55 0x33edc +#define ixSMU_PM_STATUS_56 0x33ee0 +#define ixSMU_PM_STATUS_57 0x33ee4 +#define ixSMU_PM_STATUS_58 0x33ee8 +#define ixSMU_PM_STATUS_59 0x33eec +#define ixSMU_PM_STATUS_60 0x33ef0 +#define ixSMU_PM_STATUS_61 0x33ef4 +#define ixSMU_PM_STATUS_62 0x33ef8 +#define ixSMU_PM_STATUS_63 0x33efc +#define ixSMU_PM_STATUS_64 0x33f00 +#define ixSMU_PM_STATUS_65 0x33f04 +#define ixSMU_PM_STATUS_66 0x33f08 +#define ixSMU_PM_STATUS_67 0x33f0c +#define ixSMU_PM_STATUS_68 0x33f10 +#define ixSMU_PM_STATUS_69 0x33f14 +#define ixSMU_PM_STATUS_70 0x33f18 +#define ixSMU_PM_STATUS_71 0x33f1c +#define ixSMU_PM_STATUS_72 0x33f20 +#define ixSMU_PM_STATUS_73 0x33f24 +#define ixSMU_PM_STATUS_74 0x33f28 +#define ixSMU_PM_STATUS_75 0x33f2c +#define ixSMU_PM_STATUS_76 0x33f30 +#define ixSMU_PM_STATUS_77 0x33f34 +#define ixSMU_PM_STATUS_78 0x33f38 +#define ixSMU_PM_STATUS_79 0x33f3c +#define ixSMU_PM_STATUS_80 0x33f40 +#define ixSMU_PM_STATUS_81 0x33f44 +#define ixSMU_PM_STATUS_82 0x33f48 +#define ixSMU_PM_STATUS_83 0x33f4c +#define ixSMU_PM_STATUS_84 0x33f50 +#define ixSMU_PM_STATUS_85 0x33f54 +#define ixSMU_PM_STATUS_86 0x33f58 +#define ixSMU_PM_STATUS_87 0x33f5c +#define ixSMU_PM_STATUS_88 0x33f60 +#define ixSMU_PM_STATUS_89 0x33f64 +#define ixSMU_PM_STATUS_90 0x33f68 +#define ixSMU_PM_STATUS_91 0x33f6c +#define ixSMU_PM_STATUS_92 0x33f70 +#define ixSMU_PM_STATUS_93 0x33f74 +#define ixSMU_PM_STATUS_94 0x33f78 +#define ixSMU_PM_STATUS_95 0x33f7c +#define ixSMU_PM_STATUS_96 0x33f80 +#define ixSMU_PM_STATUS_97 0x33f84 +#define ixSMU_PM_STATUS_98 0x33f88 +#define ixSMU_PM_STATUS_99 0x33f8c +#define ixSMU_PM_STATUS_100 0x33f90 +#define ixSMU_PM_STATUS_101 0x33f94 +#define ixSMU_PM_STATUS_102 0x33f98 +#define ixSMU_PM_STATUS_103 0x33f9c +#define ixSMU_PM_STATUS_104 0x33fa0 +#define ixSMU_PM_STATUS_105 0x33fa4 +#define ixSMU_PM_STATUS_106 0x33fa8 +#define ixSMU_PM_STATUS_107 0x33fac +#define ixSMU_PM_STATUS_108 0x33fb0 +#define ixSMU_PM_STATUS_109 0x33fb4 +#define ixSMU_PM_STATUS_110 0x33fb8 +#define ixSMU_PM_STATUS_111 0x33fbc +#define ixSMU_PM_STATUS_112 0x33fc0 +#define ixSMU_PM_STATUS_113 0x33fc4 +#define ixSMU_PM_STATUS_114 0x33fc8 +#define ixSMU_PM_STATUS_115 0x33fcc +#define ixSMU_PM_STATUS_116 0x33fd0 +#define ixSMU_PM_STATUS_117 0x33fd4 +#define ixSMU_PM_STATUS_118 0x33fd8 +#define ixSMU_PM_STATUS_119 0x33fdc +#define ixSMU_PM_STATUS_120 0x33fe0 +#define ixSMU_PM_STATUS_121 0x33fe4 +#define ixSMU_PM_STATUS_122 0x33fe8 +#define ixSMU_PM_STATUS_123 0x33fec +#define ixSMU_PM_STATUS_124 0x33ff0 +#define ixSMU_PM_STATUS_125 0x33ff4 +#define ixSMU_PM_STATUS_126 0x33ff8 +#define ixSMU_PM_STATUS_127 0x33ffc +#define ixCG_THERMAL_INT_ENA 0xc2100024 +#define ixCG_THERMAL_INT_CTRL 0xc2100028 +#define ixCG_THERMAL_INT_STATUS 0xc210002c +#define ixCG_THERMAL_CTRL 0xc0300004 +#define ixCG_THERMAL_STATUS 0xc0300008 +#define ixCG_THERMAL_INT 0xc030000c +#define ixCG_MULT_THERMAL_CTRL 0xc0300010 +#define ixCG_MULT_THERMAL_STATUS 0xc0300014 +#define ixCG_FDO_CTRL0 0xc0300064 +#define ixCG_FDO_CTRL1 0xc0300068 +#define ixCG_FDO_CTRL2 0xc030006c +#define ixCG_TACH_CTRL 0xc0300070 +#define ixCG_TACH_STATUS 0xc0300074 +#define ixCC_THM_STRAPS0 0xc0300080 +#define ixTHM_TMON0_RDIL0_DATA 0xc0300100 +#define ixTHM_TMON0_RDIL1_DATA 0xc0300104 +#define ixTHM_TMON0_RDIL2_DATA 0xc0300108 +#define ixTHM_TMON0_RDIL3_DATA 0xc030010c +#define ixTHM_TMON0_RDIL4_DATA 0xc0300110 +#define ixTHM_TMON0_RDIL5_DATA 0xc0300114 +#define ixTHM_TMON0_RDIL6_DATA 0xc0300118 +#define ixTHM_TMON0_RDIL7_DATA 0xc030011c +#define ixTHM_TMON0_RDIL8_DATA 0xc0300120 +#define ixTHM_TMON0_RDIL9_DATA 0xc0300124 +#define ixTHM_TMON0_RDIL10_DATA 0xc0300128 +#define ixTHM_TMON0_RDIL11_DATA 0xc030012c +#define ixTHM_TMON0_RDIL12_DATA 0xc0300130 +#define ixTHM_TMON0_RDIL13_DATA 0xc0300134 +#define ixTHM_TMON0_RDIL14_DATA 0xc0300138 +#define ixTHM_TMON0_RDIL15_DATA 0xc030013c +#define ixTHM_TMON0_RDIR0_DATA 0xc0300140 +#define ixTHM_TMON0_RDIR1_DATA 0xc0300144 +#define ixTHM_TMON0_RDIR2_DATA 0xc0300148 +#define ixTHM_TMON0_RDIR3_DATA 0xc030014c +#define ixTHM_TMON0_RDIR4_DATA 0xc0300150 +#define ixTHM_TMON0_RDIR5_DATA 0xc0300154 +#define ixTHM_TMON0_RDIR6_DATA 0xc0300158 +#define ixTHM_TMON0_RDIR7_DATA 0xc030015c +#define ixTHM_TMON0_RDIR8_DATA 0xc0300160 +#define ixTHM_TMON0_RDIR9_DATA 0xc0300164 +#define ixTHM_TMON0_RDIR10_DATA 0xc0300168 +#define ixTHM_TMON0_RDIR11_DATA 0xc030016c +#define ixTHM_TMON0_RDIR12_DATA 0xc0300170 +#define ixTHM_TMON0_RDIR13_DATA 0xc0300174 +#define ixTHM_TMON0_RDIR14_DATA 0xc0300178 +#define ixTHM_TMON0_RDIR15_DATA 0xc030017c +#define ixTHM_TMON0_INT_DATA 0xc0300300 +#define ixTHM_TMON0_DEBUG 0xc0300310 +#define ixTHM_TMON0_STATUS 0xc0300320 +#define ixGENERAL_PWRMGT 0xc0200000 +#define ixCNB_PWRMGT_CNTL 0xc0200004 +#define ixSCLK_PWRMGT_CNTL 0xc0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 +#define ixPWR_PCC_CONTROL 0xc0200018 +#define ixPWR_PCC_GPIO_SELECT 0xc020001c +#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 +#define ixPLL_TEST_CNTL 0xc020003c +#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 +#define ixCG_DISPLAY_GAP_CNTL 0xc0200060 +#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 +#define ixCG_ACPI_CNTL 0xc0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 +#define ixCG_ULV_PARAMETER 0xc020015c +#define ixSCLK_MIN_DIV 0xc02003ac +#define ixPWR_DISP_TIMER_0_CONTROL 0xc0200390 +#define ixPWR_DISP_TIMER_1_CONTROL 0xc020037c +#define ixPWR_DISP_TIMER_2_CONTROL 0xc02003d0 +#define ixPWR_DISP_TIMER_3_CONTROL 0xc02003d4 +#define ixPWR_DISP_TIMER_4_CONTROL 0xc02003d8 +#define ixPWR_DISP_TIMER_5_CONTROL 0xc02003dc +#define ixPWR_DISP_TIMER_6_CONTROL 0xc02003e0 +#define ixPWR_DISP_TIMER_7_CONTROL 0xc02003e4 +#define ixPWR_DISP_TIMER_8_CONTROL 0xc02003e8 +#define ixPWR_DISP_TIMER_9_CONTROL 0xc02003ec +#define ixPWR_DISP_TIMER_10_CONTROL 0xc02003f0 +#define ixPWR_DISP_TIMER_11_CONTROL 0xc02003f4 +#define ixPWR_DISP_TIMER_12_CONTROL 0xc02003f8 +#define ixPWR_DISP_TIMER_13_CONTROL 0xc02003fc +#define ixPWR_DISP_TIMER_14_CONTROL 0xc0200074 +#define ixPWR_DISP_TIMER_15_CONTROL 0xc0200078 +#define ixPWR_DISP_TIMER_CONTROL2 0xc0200378 +#define ixVDDGFX_IDLE_PARAMETER 0xc020036c +#define ixVDDGFX_IDLE_CONTROL 0xc0200370 +#define ixVDDGFX_IDLE_EXIT 0xc0200374 +#define ixLCAC_MC0_CNTL 0xc0400130 +#define ixLCAC_MC0_OVR_SEL 0xc0400134 +#define ixLCAC_MC0_OVR_VAL 0xc0400138 +#define ixLCAC_MC1_CNTL 0xc040013c +#define ixLCAC_MC1_OVR_SEL 0xc0400140 +#define ixLCAC_MC1_OVR_VAL 0xc0400144 +#define ixLCAC_MC2_CNTL 0xc0400148 +#define ixLCAC_MC2_OVR_SEL 0xc040014c +#define ixLCAC_MC2_OVR_VAL 0xc0400150 +#define ixLCAC_MC3_CNTL 0xc0400154 +#define ixLCAC_MC3_OVR_SEL 0xc0400158 +#define ixLCAC_MC3_OVR_VAL 0xc040015c +#define ixLCAC_CPL_CNTL 0xc0400160 +#define ixLCAC_CPL_OVR_SEL 0xc0400164 +#define ixLCAC_CPL_OVR_VAL 0xc0400168 +#define mmROM_SMC_IND_INDEX 0x80 +#define mmROM0_ROM_SMC_IND_INDEX 0x80 +#define mmROM1_ROM_SMC_IND_INDEX 0x82 +#define mmROM2_ROM_SMC_IND_INDEX 0x84 +#define mmROM3_ROM_SMC_IND_INDEX 0x86 +#define mmROM_SMC_IND_DATA 0x81 +#define mmROM0_ROM_SMC_IND_DATA 0x81 +#define mmROM1_ROM_SMC_IND_DATA 0x83 +#define mmROM2_ROM_SMC_IND_DATA 0x85 +#define mmROM3_ROM_SMC_IND_DATA 0x87 +#define ixROM_CNTL 0xc0600000 +#define ixPAGE_MIRROR_CNTL 0xc0600004 +#define ixROM_STATUS 0xc0600008 +#define ixCGTT_ROM_CLK_CTRL0 0xc060000c +#define ixROM_INDEX 0xc0600010 +#define ixROM_DATA 0xc0600014 +#define ixROM_START 0xc0600018 +#define ixROM_SW_CNTL 0xc060001c +#define ixROM_SW_STATUS 0xc0600020 +#define ixROM_SW_COMMAND 0xc0600024 +#define ixROM_SW_DATA_1 0xc0600028 +#define ixROM_SW_DATA_2 0xc060002c +#define ixROM_SW_DATA_3 0xc0600030 +#define ixROM_SW_DATA_4 0xc0600034 +#define ixROM_SW_DATA_5 0xc0600038 +#define ixROM_SW_DATA_6 0xc060003c +#define ixROM_SW_DATA_7 0xc0600040 +#define ixROM_SW_DATA_8 0xc0600044 +#define ixROM_SW_DATA_9 0xc0600048 +#define ixROM_SW_DATA_10 0xc060004c +#define ixROM_SW_DATA_11 0xc0600050 +#define ixROM_SW_DATA_12 0xc0600054 +#define ixROM_SW_DATA_13 0xc0600058 +#define ixROM_SW_DATA_14 0xc060005c +#define ixROM_SW_DATA_15 0xc0600060 +#define ixROM_SW_DATA_16 0xc0600064 +#define ixROM_SW_DATA_17 0xc0600068 +#define ixROM_SW_DATA_18 0xc060006c +#define ixROM_SW_DATA_19 0xc0600070 +#define ixROM_SW_DATA_20 0xc0600074 +#define ixROM_SW_DATA_21 0xc0600078 +#define ixROM_SW_DATA_22 0xc060007c +#define ixROM_SW_DATA_23 0xc0600080 +#define ixROM_SW_DATA_24 0xc0600084 +#define ixROM_SW_DATA_25 0xc0600088 +#define ixROM_SW_DATA_26 0xc060008c +#define ixROM_SW_DATA_27 0xc0600090 +#define ixROM_SW_DATA_28 0xc0600094 +#define ixROM_SW_DATA_29 0xc0600098 +#define ixROM_SW_DATA_30 0xc060009c +#define ixROM_SW_DATA_31 0xc06000a0 +#define ixROM_SW_DATA_32 0xc06000a4 +#define ixROM_SW_DATA_33 0xc06000a8 +#define ixROM_SW_DATA_34 0xc06000ac +#define ixROM_SW_DATA_35 0xc06000b0 +#define ixROM_SW_DATA_36 0xc06000b4 +#define ixROM_SW_DATA_37 0xc06000b8 +#define ixROM_SW_DATA_38 0xc06000bc +#define ixROM_SW_DATA_39 0xc06000c0 +#define ixROM_SW_DATA_40 0xc06000c4 +#define ixROM_SW_DATA_41 0xc06000c8 +#define ixROM_SW_DATA_42 0xc06000cc +#define ixROM_SW_DATA_43 0xc06000d0 +#define ixROM_SW_DATA_44 0xc06000d4 +#define ixROM_SW_DATA_45 0xc06000d8 +#define ixROM_SW_DATA_46 0xc06000dc +#define ixROM_SW_DATA_47 0xc06000e0 +#define ixROM_SW_DATA_48 0xc06000e4 +#define ixROM_SW_DATA_49 0xc06000e8 +#define ixROM_SW_DATA_50 0xc06000ec +#define ixROM_SW_DATA_51 0xc06000f0 +#define ixROM_SW_DATA_52 0xc06000f4 +#define ixROM_SW_DATA_53 0xc06000f8 +#define ixROM_SW_DATA_54 0xc06000fc +#define ixROM_SW_DATA_55 0xc0600100 +#define ixROM_SW_DATA_56 0xc0600104 +#define ixROM_SW_DATA_57 0xc0600108 +#define ixROM_SW_DATA_58 0xc060010c +#define ixROM_SW_DATA_59 0xc0600110 +#define ixROM_SW_DATA_60 0xc0600114 +#define ixROM_SW_DATA_61 0xc0600118 +#define ixROM_SW_DATA_62 0xc060011c +#define ixROM_SW_DATA_63 0xc0600120 +#define ixROM_SW_DATA_64 0xc0600124 + +#endif /* SMU_7_1_1_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h new file mode 100644 index 000000000000..c1a7aba19223 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h @@ -0,0 +1,1205 @@ +/* + * SMU_7_1_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_1_ENUM_H +#define SMU_7_1_1_ENUM_H + +#define CG_SRBM_START_ADDR 0x600 +#define CG_SRBM_END_ADDR 0x8ff +#define RCU_CCF_DWORDS0 0x80 +#define RCU_CCF_BITS0 0x1000 +#define RCU_CCF_DWORDS1 0x0 +#define RCU_CCF_BITS1 0x0 +#define RCU_SAM_BYTES 0x0 +#define RCU_SAM_RTL_BYTES 0x0 +#define RCU_SMU_BYTES 0x0 +#define RCU_SMU_RTL_BYTES 0x0 +#define SFP_CHAIN_ADDR 0x0 +#define SFP_BYTES 0x80 +#define SFP_SADR 0x180 +#define SFP_EADR 0x1ff +#define SAMU_KEY_CHAIN_ADR 0x0 +#define SAMU_KEY_SADR 0x0 +#define SAMU_KEY_EADR 0x0 +#define SMU_KEY_CHAIN_ADR 0x0 +#define SMU_KEY_SADR 0x0 +#define SMU_KEY_EADR 0x0 +#define SMC_MSG_TEST 0x1 +#define SMC_MSG_PHY_LN_OFF 0x2 +#define SMC_MSG_PHY_LN_ON 0x3 +#define SMC_MSG_DDI_PHY_OFF 0x4 +#define SMC_MSG_DDI_PHY_ON 0x5 +#define SMC_MSG_CASCADE_PLL_OFF 0x6 +#define SMC_MSG_CASCADE_PLL_ON 0x7 +#define SMC_MSG_PWR_OFF_x16 0x8 +#define SMC_MSG_CONFIG_LCLK_DPM 0x9 +#define SMC_MSG_FLUSH_DATA_CACHE 0xa +#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb +#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc +#define SMC_MSG_CONFIG_BAPM 0xd +#define SMC_MSG_CONFIG_TDC_LIMIT 0xe +#define SMC_MSG_CONFIG_LPMx 0xf +#define SMC_MSG_CONFIG_HTC_LIMIT 0x10 +#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11 +#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12 +#define SMC_MSG_CONFIG_TDP_CNTL 0x13 +#define SMC_MSG_EN_PM_CNTL 0x14 +#define SMC_MSG_DIS_PM_CNTL 0x15 +#define SMC_MSG_CONFIG_NBDPM 0x16 +#define SMC_MSG_CONFIG_LOADLINE 0x17 +#define SMC_MSG_ADJUST_LOADLINE 0x18 +#define SMC_MSG_RESET 0x20 +#define SMC_MSG_VOLTAGE 0x25 +#define SMC_VERSION_MAJOR 0x7 +#define SMC_VERSION_MINOR 0x0 +#define SMC_HEADER_SIZE 0x40 +#define ROM_SIGNATURE 0xaa55 +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_uvdu_0 = 0x2, + DBG_CLIENT_BLKID_uvdu_1 = 0x3, + DBG_CLIENT_BLKID_uvdu_2 = 0x4, + DBG_CLIENT_BLKID_uvdu_3 = 0x5, + DBG_CLIENT_BLKID_uvdu_4 = 0x6, + DBG_CLIENT_BLKID_uvdu_5 = 0x7, + DBG_CLIENT_BLKID_uvdu_6 = 0x8, + DBG_CLIENT_BLKID_uvdb_0 = 0x9, + DBG_CLIENT_BLKID_uvdc_0 = 0xa, + DBG_CLIENT_BLKID_uvdc_1 = 0xb, + DBG_CLIENT_BLKID_uvdf_0 = 0xc, + DBG_CLIENT_BLKID_uvdf_1 = 0xd, + DBG_CLIENT_BLKID_uvdm_0 = 0xe, + DBG_CLIENT_BLKID_uvdm_1 = 0xf, + DBG_CLIENT_BLKID_uvdm_2 = 0x10, + DBG_CLIENT_BLKID_uvdm_3 = 0x11, + DBG_CLIENT_BLKID_vcea_0 = 0x12, + DBG_CLIENT_BLKID_vcea_1 = 0x13, + DBG_CLIENT_BLKID_vcea_2 = 0x14, + DBG_CLIENT_BLKID_vcea_3 = 0x15, + DBG_CLIENT_BLKID_vceb_0 = 0x16, + DBG_CLIENT_BLKID_vcec_0 = 0x17, + DBG_CLIENT_BLKID_dco = 0x18, + DBG_CLIENT_BLKID_xdma = 0x19, + DBG_CLIENT_BLKID_dci_pg = 0x1a, + DBG_CLIENT_BLKID_smu_0 = 0x1b, + DBG_CLIENT_BLKID_smu_1 = 0x1c, + DBG_CLIENT_BLKID_smu_2 = 0x1d, + DBG_CLIENT_BLKID_gck = 0x1e, + DBG_CLIENT_BLKID_tmonw0 = 0x1f, + DBG_CLIENT_BLKID_tmonw1 = 0x20, + DBG_CLIENT_BLKID_grbm = 0x21, + DBG_CLIENT_BLKID_rlc = 0x22, + DBG_CLIENT_BLKID_ds0 = 0x23, + DBG_CLIENT_BLKID_cpg_0 = 0x24, + DBG_CLIENT_BLKID_cpg_1 = 0x25, + DBG_CLIENT_BLKID_cpc_0 = 0x26, + DBG_CLIENT_BLKID_cpc_1 = 0x27, + DBG_CLIENT_BLKID_cpf_0 = 0x28, + DBG_CLIENT_BLKID_cpf_1 = 0x29, + DBG_CLIENT_BLKID_scf0 = 0x2a, + DBG_CLIENT_BLKID_scf1 = 0x2b, + DBG_CLIENT_BLKID_scf2 = 0x2c, + DBG_CLIENT_BLKID_scf3 = 0x2d, + DBG_CLIENT_BLKID_pc0 = 0x2e, + DBG_CLIENT_BLKID_pc1 = 0x2f, + DBG_CLIENT_BLKID_pc2 = 0x30, + DBG_CLIENT_BLKID_pc3 = 0x31, + DBG_CLIENT_BLKID_vgt0 = 0x32, + DBG_CLIENT_BLKID_vgt1 = 0x33, + DBG_CLIENT_BLKID_vgt2 = 0x34, + DBG_CLIENT_BLKID_vgt3 = 0x35, + DBG_CLIENT_BLKID_sx00 = 0x36, + DBG_CLIENT_BLKID_sx10 = 0x37, + DBG_CLIENT_BLKID_sx20 = 0x38, + DBG_CLIENT_BLKID_sx30 = 0x39, + DBG_CLIENT_BLKID_cb001 = 0x3a, + DBG_CLIENT_BLKID_cb200 = 0x3b, + DBG_CLIENT_BLKID_cb201 = 0x3c, + DBG_CLIENT_BLKID_cbr0 = 0x3d, + DBG_CLIENT_BLKID_cb000 = 0x3e, + DBG_CLIENT_BLKID_cb101 = 0x3f, + DBG_CLIENT_BLKID_cb300 = 0x40, + DBG_CLIENT_BLKID_cb301 = 0x41, + DBG_CLIENT_BLKID_cbr1 = 0x42, + DBG_CLIENT_BLKID_cb100 = 0x43, + DBG_CLIENT_BLKID_ia0 = 0x44, + DBG_CLIENT_BLKID_ia1 = 0x45, + DBG_CLIENT_BLKID_bci0 = 0x46, + DBG_CLIENT_BLKID_bci1 = 0x47, + DBG_CLIENT_BLKID_bci2 = 0x48, + DBG_CLIENT_BLKID_bci3 = 0x49, + DBG_CLIENT_BLKID_pa0 = 0x4a, + DBG_CLIENT_BLKID_pa1 = 0x4b, + DBG_CLIENT_BLKID_spim0 = 0x4c, + DBG_CLIENT_BLKID_spim1 = 0x4d, + DBG_CLIENT_BLKID_spim2 = 0x4e, + DBG_CLIENT_BLKID_spim3 = 0x4f, + DBG_CLIENT_BLKID_sdma = 0x50, + DBG_CLIENT_BLKID_ih = 0x51, + DBG_CLIENT_BLKID_sem = 0x52, + DBG_CLIENT_BLKID_srbm = 0x53, + DBG_CLIENT_BLKID_hdp = 0x54, + DBG_CLIENT_BLKID_acp_0 = 0x55, + DBG_CLIENT_BLKID_acp_1 = 0x56, + DBG_CLIENT_BLKID_sam = 0x57, + DBG_CLIENT_BLKID_mcc0 = 0x58, + DBG_CLIENT_BLKID_mcc1 = 0x59, + DBG_CLIENT_BLKID_mcc2 = 0x5a, + DBG_CLIENT_BLKID_mcc3 = 0x5b, + DBG_CLIENT_BLKID_mcd0 = 0x5c, + DBG_CLIENT_BLKID_mcd1 = 0x5d, + DBG_CLIENT_BLKID_mcd2 = 0x5e, + DBG_CLIENT_BLKID_mcd3 = 0x5f, + DBG_CLIENT_BLKID_mcb = 0x60, + DBG_CLIENT_BLKID_vmc = 0x61, + DBG_CLIENT_BLKID_gmcon = 0x62, + DBG_CLIENT_BLKID_gdc_0 = 0x63, + DBG_CLIENT_BLKID_gdc_1 = 0x64, + DBG_CLIENT_BLKID_gdc_2 = 0x65, + DBG_CLIENT_BLKID_gdc_3 = 0x66, + DBG_CLIENT_BLKID_gdc_4 = 0x67, + DBG_CLIENT_BLKID_gdc_5 = 0x68, + DBG_CLIENT_BLKID_gdc_6 = 0x69, + DBG_CLIENT_BLKID_gdc_7 = 0x6a, + DBG_CLIENT_BLKID_gdc_8 = 0x6b, + DBG_CLIENT_BLKID_gdc_9 = 0x6c, + DBG_CLIENT_BLKID_gdc_10 = 0x6d, + DBG_CLIENT_BLKID_gdc_11 = 0x6e, + DBG_CLIENT_BLKID_gdc_12 = 0x6f, + DBG_CLIENT_BLKID_gdc_13 = 0x70, + DBG_CLIENT_BLKID_gdc_14 = 0x71, + DBG_CLIENT_BLKID_gdc_15 = 0x72, + DBG_CLIENT_BLKID_gdc_16 = 0x73, + DBG_CLIENT_BLKID_gdc_17 = 0x74, + DBG_CLIENT_BLKID_gdc_18 = 0x75, + DBG_CLIENT_BLKID_gdc_19 = 0x76, + DBG_CLIENT_BLKID_gdc_20 = 0x77, + DBG_CLIENT_BLKID_gdc_21 = 0x78, + DBG_CLIENT_BLKID_gdc_22 = 0x79, + DBG_CLIENT_BLKID_gdc_23 = 0x7a, + DBG_CLIENT_BLKID_gdc_24 = 0x7b, + DBG_CLIENT_BLKID_gdc_25 = 0x7c, + DBG_CLIENT_BLKID_gdc_26 = 0x7d, + DBG_CLIENT_BLKID_gdc_27 = 0x7e, + DBG_CLIENT_BLKID_gdc_28 = 0x7f, + DBG_CLIENT_BLKID_wd = 0x80, + DBG_CLIENT_BLKID_sdma_0 = 0x81, + DBG_CLIENT_BLKID_sdma_1 = 0x82, + DBG_CLIENT_BLKID_sammsp = 0x83, + DBG_CLIENT_BLKID_dci_0 = 0x84, + DBG_CLIENT_BLKID_dccg0_0 = 0x85, + DBG_CLIENT_BLKID_dcfe01_0 = 0x86, + DBG_CLIENT_BLKID_dcfe02_0 = 0x87, + DBG_CLIENT_BLKID_dcfe03_0 = 0x88, + DBG_CLIENT_BLKID_dccg0_1 = 0x89, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; + +#endif /* SMU_7_1_1_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h new file mode 100644 index 000000000000..2c997f7b5d13 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h @@ -0,0 +1,4864 @@ +/* + * SMU_7_1_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_1_SH_MASK_H +#define SMU_7_1_1_SH_MASK_H + +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f +#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 +#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f +#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 +#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f +#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 +#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f +#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d +#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 +#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 +#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 +#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 +#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 +#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 +#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1 +#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1 +#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN_MASK 0x200 +#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN__SHIFT 0x9 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa +#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff +#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 +#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 +#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 +#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 +#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa +#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 +#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_0__SMC_RESP_MASK 0xffff +#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_1__SMC_RESP_MASK 0xffff +#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_2__SMC_RESP_MASK 0xffff +#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_3__SMC_RESP_MASK 0xffff +#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_4__SMC_RESP_MASK 0xffff +#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_5__SMC_RESP_MASK 0xffff +#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_6__SMC_RESP_MASK 0xffff +#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_7__SMC_RESP_MASK 0xffff +#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_8__SMC_RESP_MASK 0xffff +#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_9__SMC_RESP_MASK 0xffff +#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_10__SMC_RESP_MASK 0xffff +#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_11__SMC_RESP_MASK 0xffff +#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 +#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 +#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 +#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 +#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 +#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffff +#define SMC_PC_C__smc_pc_c__SHIFT 0x0 +#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff +#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4 +#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff +#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 +#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff +#define GPIOPAD_A__GPIO_A__SHIFT 0x0 +#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff +#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0 +#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff +#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f +#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff +#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000 +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f +#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6 +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0 +#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff +#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 +#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff +#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 +#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff +#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 +#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 +#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3 +#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 +#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 +#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 +#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa +#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 +#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 +#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 +#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 +#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 +#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 +#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 +#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 +#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 +#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 +#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 +#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 +#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 +#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 +#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 +#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 +#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 +#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 +#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 +#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 +#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 +#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 +#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 +#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000 +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000 +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10 +#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000 +#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13 +#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000 +#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16 +#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000 +#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17 +#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000 +#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18 +#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000 +#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19 +#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000 +#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 +#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc +#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 +#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 +#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 +#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 +#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c +#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 +#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d +#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff +#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 +#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 +#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 +#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 +#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 +#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 +#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 +#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e +#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 +#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a +#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 +#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 +#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6 +#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1 +#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10 +#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4 +#define CC_HARVEST_FUSES__ACP_EXISTS_MASK 0x40 +#define CC_HARVEST_FUSES__ACP_EXISTS__SHIFT 0x6 +#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00 +#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8 +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 +#define SMU_STATUS__SMU_DONE_MASK 0x1 +#define SMU_STATUS__SMU_DONE__SHIFT 0x0 +#define SMU_STATUS__SMU_PASS_MASK 0x2 +#define SMU_STATUS__SMU_PASS__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 +#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 +#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 +#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 +#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 +#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 +#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 +#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 +#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 +#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff +#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 +#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 +#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f +#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff +#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18 +#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff +#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00 +#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8 +#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000 +#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000 +#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18 +#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0 +#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff +#define DPM_TABLE_28__SystemFlags__SHIFT 0x0 +#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff +#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0 +#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff +#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0 +#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff +#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0 +#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff +#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0 +#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff +#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0 +#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff +#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0 +#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff +#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff +#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff +#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff +#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff +#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000 +#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10 +#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff +#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0 +#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00 +#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000 +#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10 +#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff +#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0 +#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00 +#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000 +#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10 +#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff +#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0 +#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00 +#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000 +#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10 +#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff +#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0 +#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00 +#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff +#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff +#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff +#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff +#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff +#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff +#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff +#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff +#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_68__MasterDeepSleepControl_MASK 0xff +#define DPM_TABLE_68__MasterDeepSleepControl__SHIFT 0x0 +#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00 +#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8 +#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000 +#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10 +#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000 +#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18 +#define DPM_TABLE_69__Reserved_0_MASK 0xffffffff +#define DPM_TABLE_69__Reserved_0__SHIFT 0x0 +#define DPM_TABLE_70__Reserved_1_MASK 0xffffffff +#define DPM_TABLE_70__Reserved_1__SHIFT 0x0 +#define DPM_TABLE_71__Reserved_2_MASK 0xffffffff +#define DPM_TABLE_71__Reserved_2__SHIFT 0x0 +#define DPM_TABLE_72__Reserved_3_MASK 0xffffffff +#define DPM_TABLE_72__Reserved_3__SHIFT 0x0 +#define DPM_TABLE_73__Reserved_4_MASK 0xffffffff +#define DPM_TABLE_73__Reserved_4__SHIFT 0x0 +#define DPM_TABLE_74__GraphicsLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_74__GraphicsLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel_MASK 0xffff +#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_84__GraphicsLevel_0_SclkDid_MASK 0xff000000 +#define DPM_TABLE_84__GraphicsLevel_0_SclkDid__SHIFT 0x18 +#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle_MASK 0xff +#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_85__GraphicsLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_85__GraphicsLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_85__GraphicsLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_85__GraphicsLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_86__GraphicsLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_86__GraphicsLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel_MASK 0xffff +#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_96__GraphicsLevel_1_SclkDid_MASK 0xff000000 +#define DPM_TABLE_96__GraphicsLevel_1_SclkDid__SHIFT 0x18 +#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle_MASK 0xff +#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_97__GraphicsLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_97__GraphicsLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_97__GraphicsLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_97__GraphicsLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_98__GraphicsLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_98__GraphicsLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel_MASK 0xffff +#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_108__GraphicsLevel_2_SclkDid_MASK 0xff000000 +#define DPM_TABLE_108__GraphicsLevel_2_SclkDid__SHIFT 0x18 +#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle_MASK 0xff +#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_109__GraphicsLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_109__GraphicsLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_109__GraphicsLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_109__GraphicsLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_110__GraphicsLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_110__GraphicsLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel_MASK 0xffff +#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_120__GraphicsLevel_3_SclkDid_MASK 0xff000000 +#define DPM_TABLE_120__GraphicsLevel_3_SclkDid__SHIFT 0x18 +#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle_MASK 0xff +#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_121__GraphicsLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_121__GraphicsLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_121__GraphicsLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_121__GraphicsLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_122__GraphicsLevel_4_MinVddc_MASK 0xffffffff +#define DPM_TABLE_122__GraphicsLevel_4_MinVddc__SHIFT 0x0 +#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel_MASK 0xffff +#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_132__GraphicsLevel_4_SclkDid_MASK 0xff000000 +#define DPM_TABLE_132__GraphicsLevel_4_SclkDid__SHIFT 0x18 +#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle_MASK 0xff +#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_133__GraphicsLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_133__GraphicsLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_133__GraphicsLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_133__GraphicsLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_134__GraphicsLevel_5_MinVddc_MASK 0xffffffff +#define DPM_TABLE_134__GraphicsLevel_5_MinVddc__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel_MASK 0xffff +#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_144__GraphicsLevel_5_SclkDid_MASK 0xff000000 +#define DPM_TABLE_144__GraphicsLevel_5_SclkDid__SHIFT 0x18 +#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle_MASK 0xff +#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_145__GraphicsLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_145__GraphicsLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_145__GraphicsLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_145__GraphicsLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_146__GraphicsLevel_6_MinVddc_MASK 0xffffffff +#define DPM_TABLE_146__GraphicsLevel_6_MinVddc__SHIFT 0x0 +#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel_MASK 0xffff +#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_156__GraphicsLevel_6_SclkDid_MASK 0xff000000 +#define DPM_TABLE_156__GraphicsLevel_6_SclkDid__SHIFT 0x18 +#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle_MASK 0xff +#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_157__GraphicsLevel_6_DownHyst_MASK 0xff0000 +#define DPM_TABLE_157__GraphicsLevel_6_DownHyst__SHIFT 0x10 +#define DPM_TABLE_157__GraphicsLevel_6_UpHyst_MASK 0xff000000 +#define DPM_TABLE_157__GraphicsLevel_6_UpHyst__SHIFT 0x18 +#define DPM_TABLE_158__GraphicsLevel_7_MinVddc_MASK 0xffffffff +#define DPM_TABLE_158__GraphicsLevel_7_MinVddc__SHIFT 0x0 +#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel_MASK 0xffff +#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_168__GraphicsLevel_7_SclkDid_MASK 0xff000000 +#define DPM_TABLE_168__GraphicsLevel_7_SclkDid__SHIFT 0x18 +#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle_MASK 0xff +#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_169__GraphicsLevel_7_DownHyst_MASK 0xff0000 +#define DPM_TABLE_169__GraphicsLevel_7_DownHyst__SHIFT 0x10 +#define DPM_TABLE_169__GraphicsLevel_7_UpHyst_MASK 0xff000000 +#define DPM_TABLE_169__GraphicsLevel_7_UpHyst__SHIFT 0x18 +#define DPM_TABLE_170__MemoryACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_170__MemoryACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_172__MemoryACPILevel_MinVddci_MASK 0xffffffff +#define DPM_TABLE_172__MemoryACPILevel_MinVddci__SHIFT 0x0 +#define DPM_TABLE_173__MemoryACPILevel_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_173__MemoryACPILevel_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_175__MemoryACPILevel_StutterEnable_MASK 0xff +#define DPM_TABLE_175__MemoryACPILevel_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_175__MemoryACPILevel_RttEnable_MASK 0xff00 +#define DPM_TABLE_175__MemoryACPILevel_RttEnable__SHIFT 0x8 +#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity_MASK 0xff +#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_177__MemoryACPILevel_padding_MASK 0xff +#define DPM_TABLE_177__MemoryACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_177__MemoryACPILevel_DownHyst_MASK 0xff0000 +#define DPM_TABLE_177__MemoryACPILevel_DownHyst__SHIFT 0x10 +#define DPM_TABLE_177__MemoryACPILevel_UpHyst_MASK 0xff000000 +#define DPM_TABLE_177__MemoryACPILevel_UpHyst__SHIFT 0x18 +#define DPM_TABLE_178__MemoryACPILevel_padding1_MASK 0xff +#define DPM_TABLE_178__MemoryACPILevel_padding1__SHIFT 0x0 +#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_185__MemoryACPILevel_DllCntl_MASK 0xffffffff +#define DPM_TABLE_185__MemoryACPILevel_DllCntl__SHIFT 0x0 +#define DPM_TABLE_186__MemoryACPILevel_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_186__MemoryACPILevel_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_187__MemoryACPILevel_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_187__MemoryACPILevel_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_188__MemoryLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_188__MemoryLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_190__MemoryLevel_0_MinVddci_MASK 0xffffffff +#define DPM_TABLE_190__MemoryLevel_0_MinVddci__SHIFT 0x0 +#define DPM_TABLE_191__MemoryLevel_0_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_191__MemoryLevel_0_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_193__MemoryLevel_0_StutterEnable_MASK 0xff +#define DPM_TABLE_193__MemoryLevel_0_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_193__MemoryLevel_0_RttEnable_MASK 0xff00 +#define DPM_TABLE_193__MemoryLevel_0_RttEnable__SHIFT 0x8 +#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity_MASK 0xff +#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_195__MemoryLevel_0_padding_MASK 0xff +#define DPM_TABLE_195__MemoryLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_195__MemoryLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_195__MemoryLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_195__MemoryLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_195__MemoryLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_196__MemoryLevel_0_padding1_MASK 0xff +#define DPM_TABLE_196__MemoryLevel_0_padding1__SHIFT 0x0 +#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_203__MemoryLevel_0_DllCntl_MASK 0xffffffff +#define DPM_TABLE_203__MemoryLevel_0_DllCntl__SHIFT 0x0 +#define DPM_TABLE_204__MemoryLevel_0_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_204__MemoryLevel_0_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_205__MemoryLevel_0_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_205__MemoryLevel_0_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_206__MemoryLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_206__MemoryLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_208__MemoryLevel_1_MinVddci_MASK 0xffffffff +#define DPM_TABLE_208__MemoryLevel_1_MinVddci__SHIFT 0x0 +#define DPM_TABLE_209__MemoryLevel_1_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_209__MemoryLevel_1_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_211__MemoryLevel_1_StutterEnable_MASK 0xff +#define DPM_TABLE_211__MemoryLevel_1_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_211__MemoryLevel_1_RttEnable_MASK 0xff00 +#define DPM_TABLE_211__MemoryLevel_1_RttEnable__SHIFT 0x8 +#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity_MASK 0xff +#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_213__MemoryLevel_1_padding_MASK 0xff +#define DPM_TABLE_213__MemoryLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_213__MemoryLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_213__MemoryLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_213__MemoryLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_213__MemoryLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_214__MemoryLevel_1_padding1_MASK 0xff +#define DPM_TABLE_214__MemoryLevel_1_padding1__SHIFT 0x0 +#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_221__MemoryLevel_1_DllCntl_MASK 0xffffffff +#define DPM_TABLE_221__MemoryLevel_1_DllCntl__SHIFT 0x0 +#define DPM_TABLE_222__MemoryLevel_1_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_222__MemoryLevel_1_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_223__MemoryLevel_1_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_223__MemoryLevel_1_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_224__MemoryLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_224__MemoryLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_226__MemoryLevel_2_MinVddci_MASK 0xffffffff +#define DPM_TABLE_226__MemoryLevel_2_MinVddci__SHIFT 0x0 +#define DPM_TABLE_227__MemoryLevel_2_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_227__MemoryLevel_2_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_229__MemoryLevel_2_StutterEnable_MASK 0xff +#define DPM_TABLE_229__MemoryLevel_2_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_229__MemoryLevel_2_RttEnable_MASK 0xff00 +#define DPM_TABLE_229__MemoryLevel_2_RttEnable__SHIFT 0x8 +#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity_MASK 0xff +#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_231__MemoryLevel_2_padding_MASK 0xff +#define DPM_TABLE_231__MemoryLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_231__MemoryLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_231__MemoryLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_231__MemoryLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_231__MemoryLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_232__MemoryLevel_2_padding1_MASK 0xff +#define DPM_TABLE_232__MemoryLevel_2_padding1__SHIFT 0x0 +#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_239__MemoryLevel_2_DllCntl_MASK 0xffffffff +#define DPM_TABLE_239__MemoryLevel_2_DllCntl__SHIFT 0x0 +#define DPM_TABLE_240__MemoryLevel_2_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_240__MemoryLevel_2_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_241__MemoryLevel_2_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_241__MemoryLevel_2_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_242__MemoryLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_242__MemoryLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_244__MemoryLevel_3_MinVddci_MASK 0xffffffff +#define DPM_TABLE_244__MemoryLevel_3_MinVddci__SHIFT 0x0 +#define DPM_TABLE_245__MemoryLevel_3_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_245__MemoryLevel_3_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_3_StutterEnable_MASK 0xff +#define DPM_TABLE_247__MemoryLevel_3_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_3_RttEnable_MASK 0xff00 +#define DPM_TABLE_247__MemoryLevel_3_RttEnable__SHIFT 0x8 +#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity_MASK 0xff +#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_249__MemoryLevel_3_padding_MASK 0xff +#define DPM_TABLE_249__MemoryLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_249__MemoryLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_249__MemoryLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_249__MemoryLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_249__MemoryLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_250__MemoryLevel_3_padding1_MASK 0xff +#define DPM_TABLE_250__MemoryLevel_3_padding1__SHIFT 0x0 +#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_257__MemoryLevel_3_DllCntl_MASK 0xffffffff +#define DPM_TABLE_257__MemoryLevel_3_DllCntl__SHIFT 0x0 +#define DPM_TABLE_258__MemoryLevel_3_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_258__MemoryLevel_3_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_259__MemoryLevel_3_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_259__MemoryLevel_3_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_260__LinkLevel_0_SPC_MASK 0xff +#define DPM_TABLE_260__LinkLevel_0_SPC__SHIFT 0x0 +#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_261__LinkLevel_0_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_261__LinkLevel_0_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_262__LinkLevel_0_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_262__LinkLevel_0_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_263__LinkLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_263__LinkLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_264__LinkLevel_1_SPC_MASK 0xff +#define DPM_TABLE_264__LinkLevel_1_SPC__SHIFT 0x0 +#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_265__LinkLevel_1_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_265__LinkLevel_1_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_266__LinkLevel_1_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_266__LinkLevel_1_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_267__LinkLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_267__LinkLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_268__LinkLevel_2_SPC_MASK 0xff +#define DPM_TABLE_268__LinkLevel_2_SPC__SHIFT 0x0 +#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_269__LinkLevel_2_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_269__LinkLevel_2_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_270__LinkLevel_2_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_270__LinkLevel_2_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_271__LinkLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_271__LinkLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_272__LinkLevel_3_SPC_MASK 0xff +#define DPM_TABLE_272__LinkLevel_3_SPC__SHIFT 0x0 +#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_273__LinkLevel_3_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_273__LinkLevel_3_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_274__LinkLevel_3_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_274__LinkLevel_3_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_275__LinkLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_275__LinkLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_276__LinkLevel_4_SPC_MASK 0xff +#define DPM_TABLE_276__LinkLevel_4_SPC__SHIFT 0x0 +#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_277__LinkLevel_4_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_277__LinkLevel_4_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_278__LinkLevel_4_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_278__LinkLevel_4_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_279__LinkLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_279__LinkLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_280__LinkLevel_5_SPC_MASK 0xff +#define DPM_TABLE_280__LinkLevel_5_SPC__SHIFT 0x0 +#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_281__LinkLevel_5_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_281__LinkLevel_5_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_282__LinkLevel_5_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_282__LinkLevel_5_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_283__LinkLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_283__LinkLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_284__LinkLevel_6_SPC_MASK 0xff +#define DPM_TABLE_284__LinkLevel_6_SPC__SHIFT 0x0 +#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_285__LinkLevel_6_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_285__LinkLevel_6_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_286__LinkLevel_6_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_286__LinkLevel_6_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_287__LinkLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_287__LinkLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_288__LinkLevel_7_SPC_MASK 0xff +#define DPM_TABLE_288__LinkLevel_7_SPC__SHIFT 0x0 +#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_289__LinkLevel_7_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_289__LinkLevel_7_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_290__LinkLevel_7_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_290__LinkLevel_7_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_291__LinkLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_291__LinkLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_292__ACPILevel_Flags_MASK 0xffffffff +#define DPM_TABLE_292__ACPILevel_Flags__SHIFT 0x0 +#define DPM_TABLE_293__ACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_293__ACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_294__ACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_294__ACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_295__ACPILevel_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_295__ACPILevel_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_296__ACPILevel_padding_MASK 0xff +#define DPM_TABLE_296__ACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_296__ACPILevel_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_296__ACPILevel_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_296__ACPILevel_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_296__ACPILevel_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_296__ACPILevel_SclkDid_MASK 0xff000000 +#define DPM_TABLE_296__ACPILevel_SclkDid__SHIFT 0x18 +#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff +#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0 +#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_303__ACPILevel_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_303__ACPILevel_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_305__SclkStepSize_MASK 0xffffffff +#define DPM_TABLE_305__SclkStepSize__SHIFT 0x0 +#define DPM_TABLE_306__Smio_0_MASK 0xffffffff +#define DPM_TABLE_306__Smio_0__SHIFT 0x0 +#define DPM_TABLE_307__Smio_1_MASK 0xffffffff +#define DPM_TABLE_307__Smio_1__SHIFT 0x0 +#define DPM_TABLE_308__Smio_2_MASK 0xffffffff +#define DPM_TABLE_308__Smio_2__SHIFT 0x0 +#define DPM_TABLE_309__Smio_3_MASK 0xffffffff +#define DPM_TABLE_309__Smio_3__SHIFT 0x0 +#define DPM_TABLE_310__Smio_4_MASK 0xffffffff +#define DPM_TABLE_310__Smio_4__SHIFT 0x0 +#define DPM_TABLE_311__Smio_5_MASK 0xffffffff +#define DPM_TABLE_311__Smio_5__SHIFT 0x0 +#define DPM_TABLE_312__Smio_6_MASK 0xffffffff +#define DPM_TABLE_312__Smio_6__SHIFT 0x0 +#define DPM_TABLE_313__Smio_7_MASK 0xffffffff +#define DPM_TABLE_313__Smio_7__SHIFT 0x0 +#define DPM_TABLE_314__Smio_8_MASK 0xffffffff +#define DPM_TABLE_314__Smio_8__SHIFT 0x0 +#define DPM_TABLE_315__Smio_9_MASK 0xffffffff +#define DPM_TABLE_315__Smio_9__SHIFT 0x0 +#define DPM_TABLE_316__Smio_10_MASK 0xffffffff +#define DPM_TABLE_316__Smio_10__SHIFT 0x0 +#define DPM_TABLE_317__Smio_11_MASK 0xffffffff +#define DPM_TABLE_317__Smio_11__SHIFT 0x0 +#define DPM_TABLE_318__Smio_12_MASK 0xffffffff +#define DPM_TABLE_318__Smio_12__SHIFT 0x0 +#define DPM_TABLE_319__Smio_13_MASK 0xffffffff +#define DPM_TABLE_319__Smio_13__SHIFT 0x0 +#define DPM_TABLE_320__Smio_14_MASK 0xffffffff +#define DPM_TABLE_320__Smio_14__SHIFT 0x0 +#define DPM_TABLE_321__Smio_15_MASK 0xffffffff +#define DPM_TABLE_321__Smio_15__SHIFT 0x0 +#define DPM_TABLE_322__Smio_16_MASK 0xffffffff +#define DPM_TABLE_322__Smio_16__SHIFT 0x0 +#define DPM_TABLE_323__Smio_17_MASK 0xffffffff +#define DPM_TABLE_323__Smio_17__SHIFT 0x0 +#define DPM_TABLE_324__Smio_18_MASK 0xffffffff +#define DPM_TABLE_324__Smio_18__SHIFT 0x0 +#define DPM_TABLE_325__Smio_19_MASK 0xffffffff +#define DPM_TABLE_325__Smio_19__SHIFT 0x0 +#define DPM_TABLE_326__Smio_20_MASK 0xffffffff +#define DPM_TABLE_326__Smio_20__SHIFT 0x0 +#define DPM_TABLE_327__Smio_21_MASK 0xffffffff +#define DPM_TABLE_327__Smio_21__SHIFT 0x0 +#define DPM_TABLE_328__Smio_22_MASK 0xffffffff +#define DPM_TABLE_328__Smio_22__SHIFT 0x0 +#define DPM_TABLE_329__Smio_23_MASK 0xffffffff +#define DPM_TABLE_329__Smio_23__SHIFT 0x0 +#define DPM_TABLE_330__Smio_24_MASK 0xffffffff +#define DPM_TABLE_330__Smio_24__SHIFT 0x0 +#define DPM_TABLE_331__Smio_25_MASK 0xffffffff +#define DPM_TABLE_331__Smio_25__SHIFT 0x0 +#define DPM_TABLE_332__Smio_26_MASK 0xffffffff +#define DPM_TABLE_332__Smio_26__SHIFT 0x0 +#define DPM_TABLE_333__Smio_27_MASK 0xffffffff +#define DPM_TABLE_333__Smio_27__SHIFT 0x0 +#define DPM_TABLE_334__Smio_28_MASK 0xffffffff +#define DPM_TABLE_334__Smio_28__SHIFT 0x0 +#define DPM_TABLE_335__Smio_29_MASK 0xffffffff +#define DPM_TABLE_335__Smio_29__SHIFT 0x0 +#define DPM_TABLE_336__Smio_30_MASK 0xffffffff +#define DPM_TABLE_336__Smio_30__SHIFT 0x0 +#define DPM_TABLE_337__Smio_31_MASK 0xffffffff +#define DPM_TABLE_337__Smio_31__SHIFT 0x0 +#define DPM_TABLE_338__GraphicsInterval_MASK 0xff +#define DPM_TABLE_338__GraphicsInterval__SHIFT 0x0 +#define DPM_TABLE_338__GraphicsThermThrottleEnable_MASK 0xff00 +#define DPM_TABLE_338__GraphicsThermThrottleEnable__SHIFT 0x8 +#define DPM_TABLE_338__GraphicsVoltageChangeEnable_MASK 0xff0000 +#define DPM_TABLE_338__GraphicsVoltageChangeEnable__SHIFT 0x10 +#define DPM_TABLE_338__GraphicsBootLevel_MASK 0xff000000 +#define DPM_TABLE_338__GraphicsBootLevel__SHIFT 0x18 +#define DPM_TABLE_339__TemperatureLimitHigh_MASK 0xffff +#define DPM_TABLE_339__TemperatureLimitHigh__SHIFT 0x0 +#define DPM_TABLE_339__ThermalInterval_MASK 0xff0000 +#define DPM_TABLE_339__ThermalInterval__SHIFT 0x10 +#define DPM_TABLE_339__VoltageInterval_MASK 0xff000000 +#define DPM_TABLE_339__VoltageInterval__SHIFT 0x18 +#define DPM_TABLE_340__MemoryVoltageChangeEnable_MASK 0xff +#define DPM_TABLE_340__MemoryVoltageChangeEnable__SHIFT 0x0 +#define DPM_TABLE_340__MemoryBootLevel_MASK 0xff00 +#define DPM_TABLE_340__MemoryBootLevel__SHIFT 0x8 +#define DPM_TABLE_340__TemperatureLimitLow_MASK 0xffff0000 +#define DPM_TABLE_340__TemperatureLimitLow__SHIFT 0x10 +#define DPM_TABLE_341__padding2_MASK 0xff +#define DPM_TABLE_341__padding2__SHIFT 0x0 +#define DPM_TABLE_341__MergedVddci_MASK 0xff00 +#define DPM_TABLE_341__MergedVddci__SHIFT 0x8 +#define DPM_TABLE_341__MemoryThermThrottleEnable_MASK 0xff0000 +#define DPM_TABLE_341__MemoryThermThrottleEnable__SHIFT 0x10 +#define DPM_TABLE_341__MemoryInterval_MASK 0xff000000 +#define DPM_TABLE_341__MemoryInterval__SHIFT 0x18 +#define DPM_TABLE_342__PhaseResponseTime_MASK 0xffff +#define DPM_TABLE_342__PhaseResponseTime__SHIFT 0x0 +#define DPM_TABLE_342__VoltageResponseTime_MASK 0xffff0000 +#define DPM_TABLE_342__VoltageResponseTime__SHIFT 0x10 +#define DPM_TABLE_343__DTEMode_MASK 0xff +#define DPM_TABLE_343__DTEMode__SHIFT 0x0 +#define DPM_TABLE_343__DTEInterval_MASK 0xff00 +#define DPM_TABLE_343__DTEInterval__SHIFT 0x8 +#define DPM_TABLE_343__PCIeGenInterval_MASK 0xff0000 +#define DPM_TABLE_343__PCIeGenInterval__SHIFT 0x10 +#define DPM_TABLE_343__PCIeBootLinkLevel_MASK 0xff000000 +#define DPM_TABLE_343__PCIeBootLinkLevel__SHIFT 0x18 +#define DPM_TABLE_344__ThermGpio_MASK 0xff +#define DPM_TABLE_344__ThermGpio__SHIFT 0x0 +#define DPM_TABLE_344__AcDcGpio_MASK 0xff00 +#define DPM_TABLE_344__AcDcGpio__SHIFT 0x8 +#define DPM_TABLE_344__VRHotGpio_MASK 0xff0000 +#define DPM_TABLE_344__VRHotGpio__SHIFT 0x10 +#define DPM_TABLE_344__SVI2Enable_MASK 0xff000000 +#define DPM_TABLE_344__SVI2Enable__SHIFT 0x18 +#define DPM_TABLE_345__DisplayCac_MASK 0xffffffff +#define DPM_TABLE_345__DisplayCac__SHIFT 0x0 +#define DPM_TABLE_346__NomPwr_MASK 0xffff +#define DPM_TABLE_346__NomPwr__SHIFT 0x0 +#define DPM_TABLE_346__MaxPwr_MASK 0xffff0000 +#define DPM_TABLE_346__MaxPwr__SHIFT 0x10 +#define DPM_TABLE_347__FpsLowThreshold_MASK 0xffff +#define DPM_TABLE_347__FpsLowThreshold__SHIFT 0x0 +#define DPM_TABLE_347__FpsHighThreshold_MASK 0xffff0000 +#define DPM_TABLE_347__FpsHighThreshold__SHIFT 0x10 +#define DPM_TABLE_348__BAPMTI_R_0_1_0_MASK 0xffff +#define DPM_TABLE_348__BAPMTI_R_0_1_0__SHIFT 0x0 +#define DPM_TABLE_348__BAPMTI_R_0_0_0_MASK 0xffff0000 +#define DPM_TABLE_348__BAPMTI_R_0_0_0__SHIFT 0x10 +#define DPM_TABLE_349__BAPMTI_R_1_0_0_MASK 0xffff +#define DPM_TABLE_349__BAPMTI_R_1_0_0__SHIFT 0x0 +#define DPM_TABLE_349__BAPMTI_R_0_2_0_MASK 0xffff0000 +#define DPM_TABLE_349__BAPMTI_R_0_2_0__SHIFT 0x10 +#define DPM_TABLE_350__BAPMTI_R_1_2_0_MASK 0xffff +#define DPM_TABLE_350__BAPMTI_R_1_2_0__SHIFT 0x0 +#define DPM_TABLE_350__BAPMTI_R_1_1_0_MASK 0xffff0000 +#define DPM_TABLE_350__BAPMTI_R_1_1_0__SHIFT 0x10 +#define DPM_TABLE_351__BAPMTI_R_2_1_0_MASK 0xffff +#define DPM_TABLE_351__BAPMTI_R_2_1_0__SHIFT 0x0 +#define DPM_TABLE_351__BAPMTI_R_2_0_0_MASK 0xffff0000 +#define DPM_TABLE_351__BAPMTI_R_2_0_0__SHIFT 0x10 +#define DPM_TABLE_352__BAPMTI_R_3_0_0_MASK 0xffff +#define DPM_TABLE_352__BAPMTI_R_3_0_0__SHIFT 0x0 +#define DPM_TABLE_352__BAPMTI_R_2_2_0_MASK 0xffff0000 +#define DPM_TABLE_352__BAPMTI_R_2_2_0__SHIFT 0x10 +#define DPM_TABLE_353__BAPMTI_R_3_2_0_MASK 0xffff +#define DPM_TABLE_353__BAPMTI_R_3_2_0__SHIFT 0x0 +#define DPM_TABLE_353__BAPMTI_R_3_1_0_MASK 0xffff0000 +#define DPM_TABLE_353__BAPMTI_R_3_1_0__SHIFT 0x10 +#define DPM_TABLE_354__BAPMTI_R_4_1_0_MASK 0xffff +#define DPM_TABLE_354__BAPMTI_R_4_1_0__SHIFT 0x0 +#define DPM_TABLE_354__BAPMTI_R_4_0_0_MASK 0xffff0000 +#define DPM_TABLE_354__BAPMTI_R_4_0_0__SHIFT 0x10 +#define DPM_TABLE_355__BAPMTI_RC_0_0_0_MASK 0xffff +#define DPM_TABLE_355__BAPMTI_RC_0_0_0__SHIFT 0x0 +#define DPM_TABLE_355__BAPMTI_R_4_2_0_MASK 0xffff0000 +#define DPM_TABLE_355__BAPMTI_R_4_2_0__SHIFT 0x10 +#define DPM_TABLE_356__BAPMTI_RC_0_2_0_MASK 0xffff +#define DPM_TABLE_356__BAPMTI_RC_0_2_0__SHIFT 0x0 +#define DPM_TABLE_356__BAPMTI_RC_0_1_0_MASK 0xffff0000 +#define DPM_TABLE_356__BAPMTI_RC_0_1_0__SHIFT 0x10 +#define DPM_TABLE_357__BAPMTI_RC_1_1_0_MASK 0xffff +#define DPM_TABLE_357__BAPMTI_RC_1_1_0__SHIFT 0x0 +#define DPM_TABLE_357__BAPMTI_RC_1_0_0_MASK 0xffff0000 +#define DPM_TABLE_357__BAPMTI_RC_1_0_0__SHIFT 0x10 +#define DPM_TABLE_358__BAPMTI_RC_2_0_0_MASK 0xffff +#define DPM_TABLE_358__BAPMTI_RC_2_0_0__SHIFT 0x0 +#define DPM_TABLE_358__BAPMTI_RC_1_2_0_MASK 0xffff0000 +#define DPM_TABLE_358__BAPMTI_RC_1_2_0__SHIFT 0x10 +#define DPM_TABLE_359__BAPMTI_RC_2_2_0_MASK 0xffff +#define DPM_TABLE_359__BAPMTI_RC_2_2_0__SHIFT 0x0 +#define DPM_TABLE_359__BAPMTI_RC_2_1_0_MASK 0xffff0000 +#define DPM_TABLE_359__BAPMTI_RC_2_1_0__SHIFT 0x10 +#define DPM_TABLE_360__BAPMTI_RC_3_1_0_MASK 0xffff +#define DPM_TABLE_360__BAPMTI_RC_3_1_0__SHIFT 0x0 +#define DPM_TABLE_360__BAPMTI_RC_3_0_0_MASK 0xffff0000 +#define DPM_TABLE_360__BAPMTI_RC_3_0_0__SHIFT 0x10 +#define DPM_TABLE_361__BAPMTI_RC_4_0_0_MASK 0xffff +#define DPM_TABLE_361__BAPMTI_RC_4_0_0__SHIFT 0x0 +#define DPM_TABLE_361__BAPMTI_RC_3_2_0_MASK 0xffff0000 +#define DPM_TABLE_361__BAPMTI_RC_3_2_0__SHIFT 0x10 +#define DPM_TABLE_362__BAPMTI_RC_4_2_0_MASK 0xffff +#define DPM_TABLE_362__BAPMTI_RC_4_2_0__SHIFT 0x0 +#define DPM_TABLE_362__BAPMTI_RC_4_1_0_MASK 0xffff0000 +#define DPM_TABLE_362__BAPMTI_RC_4_1_0__SHIFT 0x10 +#define DPM_TABLE_363__GpuTjHyst_MASK 0xff +#define DPM_TABLE_363__GpuTjHyst__SHIFT 0x0 +#define DPM_TABLE_363__GpuTjMax_MASK 0xff00 +#define DPM_TABLE_363__GpuTjMax__SHIFT 0x8 +#define DPM_TABLE_363__DTETjOffset_MASK 0xff0000 +#define DPM_TABLE_363__DTETjOffset__SHIFT 0x10 +#define DPM_TABLE_363__DTEAmbientTempBase_MASK 0xff000000 +#define DPM_TABLE_363__DTEAmbientTempBase__SHIFT 0x18 +#define DPM_TABLE_364__BootVddci_MASK 0xffff +#define DPM_TABLE_364__BootVddci__SHIFT 0x0 +#define DPM_TABLE_364__BootVddc_MASK 0xffff0000 +#define DPM_TABLE_364__BootVddc__SHIFT 0x10 +#define DPM_TABLE_365__padding_MASK 0xffff +#define DPM_TABLE_365__padding__SHIFT 0x0 +#define DPM_TABLE_365__BootMVdd_MASK 0xffff0000 +#define DPM_TABLE_365__BootMVdd__SHIFT 0x10 +#define DPM_TABLE_366__BAPM_TEMP_GRADIENT_MASK 0xffffffff +#define DPM_TABLE_366__BAPM_TEMP_GRADIENT__SHIFT 0x0 +#define DPM_TABLE_367__LowSclkInterruptThreshold_MASK 0xffffffff +#define DPM_TABLE_367__LowSclkInterruptThreshold__SHIFT 0x0 +#define DPM_TABLE_368__VddGfxReChkWait_MASK 0xffffffff +#define DPM_TABLE_368__VddGfxReChkWait__SHIFT 0x0 +#define DPM_TABLE_369__PPM_TemperatureLimit_MASK 0xffff +#define DPM_TABLE_369__PPM_TemperatureLimit__SHIFT 0x0 +#define DPM_TABLE_369__PPM_PkgPwrLimit_MASK 0xffff0000 +#define DPM_TABLE_369__PPM_PkgPwrLimit__SHIFT 0x10 +#define DPM_TABLE_370__TargetTdp_MASK 0xffff +#define DPM_TABLE_370__TargetTdp__SHIFT 0x0 +#define DPM_TABLE_370__DefaultTdp_MASK 0xffff0000 +#define DPM_TABLE_370__DefaultTdp__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_25__UlvEnterCount_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_25__UlvEnterCount__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_26__UlvTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_26__UlvTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_28__Reserved_0_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_28__Reserved_0__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_29__Reserved_1_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_29__Reserved_1__SHIFT 0x0 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe +#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 +#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 +#define TDC_STATUS__VDD_Boost_MASK 0xff +#define TDC_STATUS__VDD_Boost__SHIFT 0x0 +#define TDC_STATUS__VDD_Throttle_MASK 0xff00 +#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 +#define TDC_STATUS__VDDC_Boost_MASK 0xff0000 +#define TDC_STATUS__VDDC_Boost__SHIFT 0x10 +#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000 +#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18 +#define TDC_MV_AVERAGE__IDD_MASK 0xffff +#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 +#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000 +#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10 +#define TDC_VRM_LIMIT__IDD_MASK 0xffff +#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 +#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000 +#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10 +#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 +#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 +#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 +#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 +#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 +#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 +#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 +#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 +#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 +#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 +#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x20 +#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x5 +#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x40 +#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x6 +#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 +#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 +#define FEATURE_STATUS__BAPM_ON_MASK 0x100 +#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 +#define FEATURE_STATUS__LPMX_ON_MASK 0x200 +#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 +#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 +#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa +#define FEATURE_STATUS__LHTC_ON_MASK 0x800 +#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb +#define FEATURE_STATUS__VPC_ON_MASK 0x1000 +#define FEATURE_STATUS__VPC_ON__SHIFT 0xc +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd +#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 +#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe +#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 +#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf +#define FEATURE_STATUS__AVS_ON_MASK 0x10000 +#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 +#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 +#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 +#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 +#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 +#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 +#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 +#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 +#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 +#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 +#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 +#define FEATURE_STATUS__RESERVED_MASK 0xffc00000 +#define FEATURE_STATUS__RESERVED__SHIFT 0x16 +#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff +#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff +#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00 +#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8 +#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000 +#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10 +#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000 +#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18 +#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff +#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0 +#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00 +#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8 +#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000 +#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10 +#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000 +#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18 +#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff +#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0 +#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00 +#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8 +#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000 +#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10 +#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000 +#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18 +#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff +#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0 +#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00 +#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8 +#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000 +#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10 +#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000 +#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18 +#define PM_FUSES_5__VddCVid_3_MASK 0xff +#define PM_FUSES_5__VddCVid_3__SHIFT 0x0 +#define PM_FUSES_5__VddCVid_2_MASK 0xff00 +#define PM_FUSES_5__VddCVid_2__SHIFT 0x8 +#define PM_FUSES_5__VddCVid_1_MASK 0xff0000 +#define PM_FUSES_5__VddCVid_1__SHIFT 0x10 +#define PM_FUSES_5__VddCVid_0_MASK 0xff000000 +#define PM_FUSES_5__VddCVid_0__SHIFT 0x18 +#define PM_FUSES_6__VddCVid_7_MASK 0xff +#define PM_FUSES_6__VddCVid_7__SHIFT 0x0 +#define PM_FUSES_6__VddCVid_6_MASK 0xff00 +#define PM_FUSES_6__VddCVid_6__SHIFT 0x8 +#define PM_FUSES_6__VddCVid_5_MASK 0xff0000 +#define PM_FUSES_6__VddCVid_5__SHIFT 0x10 +#define PM_FUSES_6__VddCVid_4_MASK 0xff000000 +#define PM_FUSES_6__VddCVid_4__SHIFT 0x18 +#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff +#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0 +#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00 +#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8 +#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000 +#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10 +#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000 +#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18 +#define PM_FUSES_8__TDC_MAWt_MASK 0xff +#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8 +#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000 +#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10 +#define PM_FUSES_9__Reserved_MASK 0xff +#define PM_FUSES_9__Reserved__SHIFT 0x0 +#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00 +#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8 +#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000 +#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10 +#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000 +#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18 +#define PM_FUSES_10__LPMLTemperatureScaler_3_MASK 0xff +#define PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT 0x0 +#define PM_FUSES_10__LPMLTemperatureScaler_2_MASK 0xff00 +#define PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT 0x8 +#define PM_FUSES_10__LPMLTemperatureScaler_1_MASK 0xff0000 +#define PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT 0x10 +#define PM_FUSES_10__LPMLTemperatureScaler_0_MASK 0xff000000 +#define PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT 0x18 +#define PM_FUSES_11__LPMLTemperatureScaler_7_MASK 0xff +#define PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT 0x0 +#define PM_FUSES_11__LPMLTemperatureScaler_6_MASK 0xff00 +#define PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT 0x8 +#define PM_FUSES_11__LPMLTemperatureScaler_5_MASK 0xff0000 +#define PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT 0x10 +#define PM_FUSES_11__LPMLTemperatureScaler_4_MASK 0xff000000 +#define PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT 0x18 +#define PM_FUSES_12__LPMLTemperatureScaler_11_MASK 0xff +#define PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT 0x0 +#define PM_FUSES_12__LPMLTemperatureScaler_10_MASK 0xff00 +#define PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT 0x8 +#define PM_FUSES_12__LPMLTemperatureScaler_9_MASK 0xff0000 +#define PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT 0x10 +#define PM_FUSES_12__LPMLTemperatureScaler_8_MASK 0xff000000 +#define PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT 0x18 +#define PM_FUSES_13__LPMLTemperatureScaler_15_MASK 0xff +#define PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT 0x0 +#define PM_FUSES_13__LPMLTemperatureScaler_14_MASK 0xff00 +#define PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT 0x8 +#define PM_FUSES_13__LPMLTemperatureScaler_13_MASK 0xff0000 +#define PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT 0x10 +#define PM_FUSES_13__LPMLTemperatureScaler_12_MASK 0xff000000 +#define PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT 0x18 +#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta_MASK 0xffff +#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0 +#define PM_FUSES_14__FuzzyFan_ErrorSetDelta_MASK 0xffff0000 +#define PM_FUSES_14__FuzzyFan_ErrorSetDelta__SHIFT 0x10 +#define PM_FUSES_15__Reserved6_MASK 0xffff +#define PM_FUSES_15__Reserved6__SHIFT 0x0 +#define PM_FUSES_15__FuzzyFan_PwmSetDelta_MASK 0xffff0000 +#define PM_FUSES_15__FuzzyFan_PwmSetDelta__SHIFT 0x10 +#define PM_FUSES_16__GnbLPML_3_MASK 0xff +#define PM_FUSES_16__GnbLPML_3__SHIFT 0x0 +#define PM_FUSES_16__GnbLPML_2_MASK 0xff00 +#define PM_FUSES_16__GnbLPML_2__SHIFT 0x8 +#define PM_FUSES_16__GnbLPML_1_MASK 0xff0000 +#define PM_FUSES_16__GnbLPML_1__SHIFT 0x10 +#define PM_FUSES_16__GnbLPML_0_MASK 0xff000000 +#define PM_FUSES_16__GnbLPML_0__SHIFT 0x18 +#define PM_FUSES_17__GnbLPML_7_MASK 0xff +#define PM_FUSES_17__GnbLPML_7__SHIFT 0x0 +#define PM_FUSES_17__GnbLPML_6_MASK 0xff00 +#define PM_FUSES_17__GnbLPML_6__SHIFT 0x8 +#define PM_FUSES_17__GnbLPML_5_MASK 0xff0000 +#define PM_FUSES_17__GnbLPML_5__SHIFT 0x10 +#define PM_FUSES_17__GnbLPML_4_MASK 0xff000000 +#define PM_FUSES_17__GnbLPML_4__SHIFT 0x18 +#define PM_FUSES_18__GnbLPML_11_MASK 0xff +#define PM_FUSES_18__GnbLPML_11__SHIFT 0x0 +#define PM_FUSES_18__GnbLPML_10_MASK 0xff00 +#define PM_FUSES_18__GnbLPML_10__SHIFT 0x8 +#define PM_FUSES_18__GnbLPML_9_MASK 0xff0000 +#define PM_FUSES_18__GnbLPML_9__SHIFT 0x10 +#define PM_FUSES_18__GnbLPML_8_MASK 0xff000000 +#define PM_FUSES_18__GnbLPML_8__SHIFT 0x18 +#define PM_FUSES_19__GnbLPML_15_MASK 0xff +#define PM_FUSES_19__GnbLPML_15__SHIFT 0x0 +#define PM_FUSES_19__GnbLPML_14_MASK 0xff00 +#define PM_FUSES_19__GnbLPML_14__SHIFT 0x8 +#define PM_FUSES_19__GnbLPML_13_MASK 0xff0000 +#define PM_FUSES_19__GnbLPML_13__SHIFT 0x10 +#define PM_FUSES_19__GnbLPML_12_MASK 0xff000000 +#define PM_FUSES_19__GnbLPML_12__SHIFT 0x18 +#define PM_FUSES_20__Reserved1_1_MASK 0xff +#define PM_FUSES_20__Reserved1_1__SHIFT 0x0 +#define PM_FUSES_20__Reserved1_0_MASK 0xff00 +#define PM_FUSES_20__Reserved1_0__SHIFT 0x8 +#define PM_FUSES_20__GnbLPMLMinVid_MASK 0xff0000 +#define PM_FUSES_20__GnbLPMLMinVid__SHIFT 0x10 +#define PM_FUSES_20__GnbLPMLMaxVid_MASK 0xff000000 +#define PM_FUSES_20__GnbLPMLMaxVid__SHIFT 0x18 +#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd_MASK 0xffff +#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd__SHIFT 0x0 +#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000 +#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd__SHIFT 0x10 +#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_52__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0 +#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8 +#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3 +#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0 +#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4 +#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000 +#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe +#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000 +#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19 +#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000 +#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a +#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff +#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 +#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000 +#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11 +#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000 +#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12 +#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff +#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0 +#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00 +#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8 +#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000 +#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10 +#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000 +#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18 +#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf +#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 +#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0 +#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 +#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000 +#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 +#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff +#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 +#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff +#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 +#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00 +#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL1__M_MASK 0xff0000 +#define CG_FDO_CTRL1__M__SHIFT 0x10 +#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000 +#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 +#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000 +#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e +#define CG_FDO_CTRL2__TMIN_MASK 0xff +#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 +#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800 +#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb +#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000 +#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe +#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000 +#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 +#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7 +#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 +#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8 +#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 +#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff +#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 +#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe +#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1 +#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00 +#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11 +#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000 +#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12 +#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000 +#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18 +#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000 +#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19 +#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000 +#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a +#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000 +#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b +#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000 +#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c +#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000 +#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d +#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000 +#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_INT_DATA__Z_MASK 0x7ff +#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON0_INT_DATA__VALID_MASK 0x800 +#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 +#define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f +#define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0 +#define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20 +#define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1 +#define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0 +#define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff +#define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf +#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 +#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 +#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 +#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 +#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 +#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf +#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 +#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff +#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2 +#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1 +#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4 +#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10 +#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000 +#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a +#define ROM_STATUS__ROM_BUSY_MASK 0x1 +#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf +#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define ROM_INDEX__ROM_INDEX_MASK 0xffffff +#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 +#define ROM_DATA__ROM_DATA_MASK 0xffffffff +#define ROM_DATA__ROM_DATA__SHIFT 0x0 +#define ROM_START__ROM_START_MASK 0xffffff +#define ROM_START__ROM_START__SHIFT 0x0 +#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff +#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 +#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000 +#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 +#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1 +#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 +#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 + +#endif /* SMU_7_1_1_SH_MASK_H */ -- cgit v1.2.3 From bc136e1329f65ad7cd33fdfdb182e72233b4dcb8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:31:26 -0400 Subject: drm/amdgpu: add SMU 7.1.2 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h | 1273 +++++ .../drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h | 1246 +++++ .../amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h | 5834 ++++++++++++++++++++ 3 files changed, 8353 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h new file mode 100644 index 000000000000..933917479985 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h @@ -0,0 +1,1273 @@ +/* + * SMU_7_1_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_2_D_H +#define SMU_7_1_2_D_H + +#define mmGCK_SMC_IND_INDEX 0x80 +#define mmGCK0_GCK_SMC_IND_INDEX 0x80 +#define mmGCK1_GCK_SMC_IND_INDEX 0x82 +#define mmGCK2_GCK_SMC_IND_INDEX 0x84 +#define mmGCK3_GCK_SMC_IND_INDEX 0x86 +#define mmGCK_SMC_IND_DATA 0x81 +#define mmGCK0_GCK_SMC_IND_DATA 0x81 +#define mmGCK1_GCK_SMC_IND_DATA 0x83 +#define mmGCK2_GCK_SMC_IND_DATA 0x85 +#define mmGCK3_GCK_SMC_IND_DATA 0x87 +#define ixCG_DCLK_CNTL 0xc050009c +#define ixCG_DCLK_STATUS 0xc05000a0 +#define ixCG_VCLK_CNTL 0xc05000a4 +#define ixCG_VCLK_STATUS 0xc05000a8 +#define ixCG_ECLK_CNTL 0xc05000ac +#define ixCG_ECLK_STATUS 0xc05000b0 +#define ixCG_ACLK_CNTL 0xc05000dc +#define ixGCK_DFS_BYPASS_CNTL 0xc0500118 +#define ixCG_SPLL_FUNC_CNTL 0xc0500140 +#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 +#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 +#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c +#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 +#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 +#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 +#define ixSPLL_CNTL_MODE 0xc0500160 +#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 +#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +#define ixMPLL_BYPASSCLK_SEL 0xc050019c +#define ixCG_CLKPIN_CNTL 0xc05001a0 +#define ixCG_CLKPIN_CNTL_2 0xc05001a4 +#define ixCG_CLKPIN_CNTL_DC 0xc0500204 +#define ixTHM_CLK_CNTL 0xc05001a8 +#define ixMISC_CLK_CTRL 0xc05001ac +#define ixGCK_PLL_TEST_CNTL 0xc05001c0 +#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 +#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 +#define mmSMC_IND_INDEX 0x80 +#define mmSMC0_SMC_IND_INDEX 0x80 +#define mmSMC1_SMC_IND_INDEX 0x82 +#define mmSMC2_SMC_IND_INDEX 0x84 +#define mmSMC3_SMC_IND_INDEX 0x86 +#define mmSMC_IND_DATA 0x81 +#define mmSMC0_SMC_IND_DATA 0x81 +#define mmSMC1_SMC_IND_DATA 0x83 +#define mmSMC2_SMC_IND_DATA 0x85 +#define mmSMC3_SMC_IND_DATA 0x87 +#define mmSMC_IND_INDEX_0 0x80 +#define mmSMC_IND_DATA_0 0x81 +#define mmSMC_IND_INDEX_1 0x82 +#define mmSMC_IND_DATA_1 0x83 +#define mmSMC_IND_INDEX_2 0x84 +#define mmSMC_IND_DATA_2 0x85 +#define mmSMC_IND_INDEX_3 0x86 +#define mmSMC_IND_DATA_3 0x87 +#define mmSMC_IND_INDEX_4 0x88 +#define mmSMC_IND_DATA_4 0x89 +#define mmSMC_IND_INDEX_5 0x8a +#define mmSMC_IND_DATA_5 0x8b +#define mmSMC_IND_INDEX_6 0x8c +#define mmSMC_IND_DATA_6 0x8d +#define mmSMC_IND_INDEX_7 0x8e +#define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_ACCESS_CNTL 0x92 +#define mmSMC_MESSAGE_0 0x94 +#define mmSMC_RESP_0 0x95 +#define mmSMC_MESSAGE_1 0x96 +#define mmSMC_RESP_1 0x97 +#define mmSMC_MESSAGE_2 0x98 +#define mmSMC_RESP_2 0x99 +#define mmSMC_MESSAGE_3 0x9a +#define mmSMC_RESP_3 0x9b +#define mmSMC_MESSAGE_4 0x9c +#define mmSMC_RESP_4 0x9d +#define mmSMC_MESSAGE_5 0x9e +#define mmSMC_RESP_5 0x9f +#define mmSMC_MESSAGE_6 0xa0 +#define mmSMC_RESP_6 0xa1 +#define mmSMC_MESSAGE_7 0xa2 +#define mmSMC_RESP_7 0xa3 +#define mmSMC_MSG_ARG_0 0xa4 +#define mmSMC_MSG_ARG_1 0xa5 +#define mmSMC_MSG_ARG_2 0xa6 +#define mmSMC_MSG_ARG_3 0xa7 +#define mmSMC_MSG_ARG_4 0xa8 +#define mmSMC_MSG_ARG_5 0xa9 +#define mmSMC_MSG_ARG_6 0xaa +#define mmSMC_MSG_ARG_7 0xab +#define mmSMC_MESSAGE_8 0xb5 +#define mmSMC_RESP_8 0xb6 +#define mmSMC_MESSAGE_9 0xb7 +#define mmSMC_RESP_9 0xb8 +#define mmSMC_MESSAGE_10 0xb9 +#define mmSMC_RESP_10 0xba +#define mmSMC_MESSAGE_11 0xbb +#define mmSMC_RESP_11 0xbc +#define mmSMC_MSG_ARG_8 0xbd +#define mmSMC_MSG_ARG_9 0xbe +#define mmSMC_MSG_ARG_10 0xbf +#define mmSMC_MSG_ARG_11 0x93 +#define ixSMC_SYSCON_RESET_CNTL 0x80000000 +#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 +#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 +#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c +#define ixSMC_SYSCON_MISC_CNTL 0x80000010 +#define ixSMC_SYSCON_MSG_ARG_0 0x80000068 +#define ixSMC_PC_C 0x80000370 +#define ixSMC_SCRATCH9 0x80000424 +#define mmGPIOPAD_SW_INT_STAT 0x180 +#define mmGPIOPAD_STRENGTH 0x181 +#define mmGPIOPAD_MASK 0x182 +#define mmGPIOPAD_A 0x183 +#define mmGPIOPAD_EN 0x184 +#define mmGPIOPAD_Y 0x185 +#define mmGPIOPAD_PINSTRAPS 0x186 +#define mmGPIOPAD_INT_STAT_EN 0x187 +#define mmGPIOPAD_INT_STAT 0x188 +#define mmGPIOPAD_INT_STAT_AK 0x189 +#define mmGPIOPAD_INT_EN 0x18a +#define mmGPIOPAD_INT_TYPE 0x18b +#define mmGPIOPAD_INT_POLARITY 0x18c +#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d +#define mmGPIOPAD_RCVR_SEL 0x191 +#define mmGPIOPAD_PU_EN 0x192 +#define mmGPIOPAD_PD_EN 0x193 +#define mmCG_FPS_CNT 0x1b6 +#define mmSMU_IND_INDEX_0 0x1a6 +#define mmSMU_IND_DATA_0 0x1a7 +#define mmSMU_IND_INDEX_1 0x1a8 +#define mmSMU_IND_DATA_1 0x1a9 +#define mmSMU_IND_INDEX_2 0x1aa +#define mmSMU_IND_DATA_2 0x1ab +#define mmSMU_IND_INDEX_3 0x1ac +#define mmSMU_IND_DATA_3 0x1ad +#define mmSMU_IND_INDEX_4 0x1ae +#define mmSMU_IND_DATA_4 0x1af +#define mmSMU_IND_INDEX_5 0x1b0 +#define mmSMU_IND_DATA_5 0x1b1 +#define mmSMU_IND_INDEX_6 0x1b2 +#define mmSMU_IND_DATA_6 0x1b3 +#define mmSMU_IND_INDEX_7 0x1b4 +#define mmSMU_IND_DATA_7 0x1b5 +#define mmSMU_SMC_IND_INDEX 0x80 +#define mmSMU0_SMU_SMC_IND_INDEX 0x80 +#define mmSMU1_SMU_SMC_IND_INDEX 0x82 +#define mmSMU2_SMU_SMC_IND_INDEX 0x84 +#define mmSMU3_SMU_SMC_IND_INDEX 0x86 +#define mmSMU_SMC_IND_DATA 0x81 +#define mmSMU0_SMU_SMC_IND_DATA 0x81 +#define mmSMU1_SMU_SMC_IND_DATA 0x83 +#define mmSMU2_SMU_SMC_IND_DATA 0x85 +#define mmSMU3_SMU_SMC_IND_DATA 0x87 +#define ixRCU_UC_EVENTS 0xc0000004 +#define ixRCU_MISC_CTRL 0xc0000010 +#define ixRCU_VIRT_RESET_REQ 0xc0000024 +#define ixCC_RCU_FUSES 0xc00c0000 +#define ixCC_SMU_MISC_FUSES 0xc00c0004 +#define ixCC_SCLK_VID_FUSES 0xc00c0008 +#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c +#define ixCC_GIO_IOC_FUSES 0xc00c0010 +#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c +#define ixCC_TST_ID_STRAPS 0xc00c0020 +#define ixCC_FCTRL_FUSES 0xc00c0024 +#define ixCC_HARVEST_FUSES 0xc00c0028 +#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 +#define ixSMU_STATUS 0xe0003088 +#define ixSMU_FIRMWARE 0xe00030a4 +#define ixSMU_INPUT_DATA 0xe00030b8 +#define ixSMU_EFUSE_0 0xc0100000 +#define ixFIRMWARE_FLAGS 0x3f800 +#define ixTDC_STATUS 0x3f804 +#define ixTDC_MV_AVERAGE 0x3f808 +#define ixTDC_VRM_LIMIT 0x3f80c +#define ixFEATURE_STATUS 0x3f810 +#define ixENTITY_TEMPERATURES_1 0x3f814 +#define ixDPM_TABLE_1 0x3f000 +#define ixDPM_TABLE_2 0x3f004 +#define ixDPM_TABLE_3 0x3f008 +#define ixDPM_TABLE_4 0x3f00c +#define ixDPM_TABLE_5 0x3f010 +#define ixDPM_TABLE_6 0x3f014 +#define ixDPM_TABLE_7 0x3f018 +#define ixDPM_TABLE_8 0x3f01c +#define ixDPM_TABLE_9 0x3f020 +#define ixDPM_TABLE_10 0x3f024 +#define ixDPM_TABLE_11 0x3f028 +#define ixDPM_TABLE_12 0x3f02c +#define ixDPM_TABLE_13 0x3f030 +#define ixDPM_TABLE_14 0x3f034 +#define ixDPM_TABLE_15 0x3f038 +#define ixDPM_TABLE_16 0x3f03c +#define ixDPM_TABLE_17 0x3f040 +#define ixDPM_TABLE_18 0x3f044 +#define ixDPM_TABLE_19 0x3f048 +#define ixDPM_TABLE_20 0x3f04c +#define ixDPM_TABLE_21 0x3f050 +#define ixDPM_TABLE_22 0x3f054 +#define ixDPM_TABLE_23 0x3f058 +#define ixDPM_TABLE_24 0x3f05c +#define ixDPM_TABLE_25 0x3f060 +#define ixDPM_TABLE_26 0x3f064 +#define ixDPM_TABLE_27 0x3f068 +#define ixDPM_TABLE_28 0x3f06c +#define ixDPM_TABLE_29 0x3f070 +#define ixDPM_TABLE_30 0x3f074 +#define ixDPM_TABLE_31 0x3f078 +#define ixDPM_TABLE_32 0x3f07c +#define ixDPM_TABLE_33 0x3f080 +#define ixDPM_TABLE_34 0x3f084 +#define ixDPM_TABLE_35 0x3f088 +#define ixDPM_TABLE_36 0x3f08c +#define ixDPM_TABLE_37 0x3f090 +#define ixDPM_TABLE_38 0x3f094 +#define ixDPM_TABLE_39 0x3f098 +#define ixDPM_TABLE_40 0x3f09c +#define ixDPM_TABLE_41 0x3f0a0 +#define ixDPM_TABLE_42 0x3f0a4 +#define ixDPM_TABLE_43 0x3f0a8 +#define ixDPM_TABLE_44 0x3f0ac +#define ixDPM_TABLE_45 0x3f0b0 +#define ixDPM_TABLE_46 0x3f0b4 +#define ixDPM_TABLE_47 0x3f0b8 +#define ixDPM_TABLE_48 0x3f0bc +#define ixDPM_TABLE_49 0x3f0c0 +#define ixDPM_TABLE_50 0x3f0c4 +#define ixDPM_TABLE_51 0x3f0c8 +#define ixDPM_TABLE_52 0x3f0cc +#define ixDPM_TABLE_53 0x3f0d0 +#define ixDPM_TABLE_54 0x3f0d4 +#define ixDPM_TABLE_55 0x3f0d8 +#define ixDPM_TABLE_56 0x3f0dc +#define ixDPM_TABLE_57 0x3f0e0 +#define ixDPM_TABLE_58 0x3f0e4 +#define ixDPM_TABLE_59 0x3f0e8 +#define ixDPM_TABLE_60 0x3f0ec +#define ixDPM_TABLE_61 0x3f0f0 +#define ixDPM_TABLE_62 0x3f0f4 +#define ixDPM_TABLE_63 0x3f0f8 +#define ixDPM_TABLE_64 0x3f0fc +#define ixDPM_TABLE_65 0x3f100 +#define ixDPM_TABLE_66 0x3f104 +#define ixDPM_TABLE_67 0x3f108 +#define ixDPM_TABLE_68 0x3f10c +#define ixDPM_TABLE_69 0x3f110 +#define ixDPM_TABLE_70 0x3f114 +#define ixDPM_TABLE_71 0x3f118 +#define ixDPM_TABLE_72 0x3f11c +#define ixDPM_TABLE_73 0x3f120 +#define ixDPM_TABLE_74 0x3f124 +#define ixDPM_TABLE_75 0x3f128 +#define ixDPM_TABLE_76 0x3f12c +#define ixDPM_TABLE_77 0x3f130 +#define ixDPM_TABLE_78 0x3f134 +#define ixDPM_TABLE_79 0x3f138 +#define ixDPM_TABLE_80 0x3f13c +#define ixDPM_TABLE_81 0x3f140 +#define ixDPM_TABLE_82 0x3f144 +#define ixDPM_TABLE_83 0x3f148 +#define ixDPM_TABLE_84 0x3f14c +#define ixDPM_TABLE_85 0x3f150 +#define ixDPM_TABLE_86 0x3f154 +#define ixDPM_TABLE_87 0x3f158 +#define ixDPM_TABLE_88 0x3f15c +#define ixDPM_TABLE_89 0x3f160 +#define ixDPM_TABLE_90 0x3f164 +#define ixDPM_TABLE_91 0x3f168 +#define ixDPM_TABLE_92 0x3f16c +#define ixDPM_TABLE_93 0x3f170 +#define ixDPM_TABLE_94 0x3f174 +#define ixDPM_TABLE_95 0x3f178 +#define ixDPM_TABLE_96 0x3f17c +#define ixDPM_TABLE_97 0x3f180 +#define ixDPM_TABLE_98 0x3f184 +#define ixDPM_TABLE_99 0x3f188 +#define ixDPM_TABLE_100 0x3f18c +#define ixDPM_TABLE_101 0x3f190 +#define ixDPM_TABLE_102 0x3f194 +#define ixDPM_TABLE_103 0x3f198 +#define ixDPM_TABLE_104 0x3f19c +#define ixDPM_TABLE_105 0x3f1a0 +#define ixDPM_TABLE_106 0x3f1a4 +#define ixDPM_TABLE_107 0x3f1a8 +#define ixDPM_TABLE_108 0x3f1ac +#define ixDPM_TABLE_109 0x3f1b0 +#define ixDPM_TABLE_110 0x3f1b4 +#define ixDPM_TABLE_111 0x3f1b8 +#define ixDPM_TABLE_112 0x3f1bc +#define ixDPM_TABLE_113 0x3f1c0 +#define ixDPM_TABLE_114 0x3f1c4 +#define ixDPM_TABLE_115 0x3f1c8 +#define ixDPM_TABLE_116 0x3f1cc +#define ixDPM_TABLE_117 0x3f1d0 +#define ixDPM_TABLE_118 0x3f1d4 +#define ixDPM_TABLE_119 0x3f1d8 +#define ixDPM_TABLE_120 0x3f1dc +#define ixDPM_TABLE_121 0x3f1e0 +#define ixDPM_TABLE_122 0x3f1e4 +#define ixDPM_TABLE_123 0x3f1e8 +#define ixDPM_TABLE_124 0x3f1ec +#define ixDPM_TABLE_125 0x3f1f0 +#define ixDPM_TABLE_126 0x3f1f4 +#define ixDPM_TABLE_127 0x3f1f8 +#define ixDPM_TABLE_128 0x3f1fc +#define ixDPM_TABLE_129 0x3f200 +#define ixDPM_TABLE_130 0x3f204 +#define ixDPM_TABLE_131 0x3f208 +#define ixDPM_TABLE_132 0x3f20c +#define ixDPM_TABLE_133 0x3f210 +#define ixDPM_TABLE_134 0x3f214 +#define ixDPM_TABLE_135 0x3f218 +#define ixDPM_TABLE_136 0x3f21c +#define ixDPM_TABLE_137 0x3f220 +#define ixDPM_TABLE_138 0x3f224 +#define ixDPM_TABLE_139 0x3f228 +#define ixDPM_TABLE_140 0x3f22c +#define ixDPM_TABLE_141 0x3f230 +#define ixDPM_TABLE_142 0x3f234 +#define ixDPM_TABLE_143 0x3f238 +#define ixDPM_TABLE_144 0x3f23c +#define ixDPM_TABLE_145 0x3f240 +#define ixDPM_TABLE_146 0x3f244 +#define ixDPM_TABLE_147 0x3f248 +#define ixDPM_TABLE_148 0x3f24c +#define ixDPM_TABLE_149 0x3f250 +#define ixDPM_TABLE_150 0x3f254 +#define ixDPM_TABLE_151 0x3f258 +#define ixDPM_TABLE_152 0x3f25c +#define ixDPM_TABLE_153 0x3f260 +#define ixDPM_TABLE_154 0x3f264 +#define ixDPM_TABLE_155 0x3f268 +#define ixDPM_TABLE_156 0x3f26c +#define ixDPM_TABLE_157 0x3f270 +#define ixDPM_TABLE_158 0x3f274 +#define ixDPM_TABLE_159 0x3f278 +#define ixDPM_TABLE_160 0x3f27c +#define ixDPM_TABLE_161 0x3f280 +#define ixDPM_TABLE_162 0x3f284 +#define ixDPM_TABLE_163 0x3f288 +#define ixDPM_TABLE_164 0x3f28c +#define ixDPM_TABLE_165 0x3f290 +#define ixDPM_TABLE_166 0x3f294 +#define ixDPM_TABLE_167 0x3f298 +#define ixDPM_TABLE_168 0x3f29c +#define ixDPM_TABLE_169 0x3f2a0 +#define ixDPM_TABLE_170 0x3f2a4 +#define ixDPM_TABLE_171 0x3f2a8 +#define ixDPM_TABLE_172 0x3f2ac +#define ixDPM_TABLE_173 0x3f2b0 +#define ixDPM_TABLE_174 0x3f2b4 +#define ixDPM_TABLE_175 0x3f2b8 +#define ixDPM_TABLE_176 0x3f2bc +#define ixDPM_TABLE_177 0x3f2c0 +#define ixDPM_TABLE_178 0x3f2c4 +#define ixDPM_TABLE_179 0x3f2c8 +#define ixDPM_TABLE_180 0x3f2cc +#define ixDPM_TABLE_181 0x3f2d0 +#define ixDPM_TABLE_182 0x3f2d4 +#define ixDPM_TABLE_183 0x3f2d8 +#define ixDPM_TABLE_184 0x3f2dc +#define ixDPM_TABLE_185 0x3f2e0 +#define ixDPM_TABLE_186 0x3f2e4 +#define ixDPM_TABLE_187 0x3f2e8 +#define ixDPM_TABLE_188 0x3f2ec +#define ixDPM_TABLE_189 0x3f2f0 +#define ixDPM_TABLE_190 0x3f2f4 +#define ixDPM_TABLE_191 0x3f2f8 +#define ixDPM_TABLE_192 0x3f2fc +#define ixDPM_TABLE_193 0x3f300 +#define ixDPM_TABLE_194 0x3f304 +#define ixDPM_TABLE_195 0x3f308 +#define ixDPM_TABLE_196 0x3f30c +#define ixDPM_TABLE_197 0x3f310 +#define ixDPM_TABLE_198 0x3f314 +#define ixDPM_TABLE_199 0x3f318 +#define ixDPM_TABLE_200 0x3f31c +#define ixDPM_TABLE_201 0x3f320 +#define ixDPM_TABLE_202 0x3f324 +#define ixDPM_TABLE_203 0x3f328 +#define ixDPM_TABLE_204 0x3f32c +#define ixDPM_TABLE_205 0x3f330 +#define ixDPM_TABLE_206 0x3f334 +#define ixDPM_TABLE_207 0x3f338 +#define ixDPM_TABLE_208 0x3f33c +#define ixDPM_TABLE_209 0x3f340 +#define ixDPM_TABLE_210 0x3f344 +#define ixDPM_TABLE_211 0x3f348 +#define ixDPM_TABLE_212 0x3f34c +#define ixDPM_TABLE_213 0x3f350 +#define ixDPM_TABLE_214 0x3f354 +#define ixDPM_TABLE_215 0x3f358 +#define ixDPM_TABLE_216 0x3f35c +#define ixDPM_TABLE_217 0x3f360 +#define ixDPM_TABLE_218 0x3f364 +#define ixDPM_TABLE_219 0x3f368 +#define ixDPM_TABLE_220 0x3f36c +#define ixDPM_TABLE_221 0x3f370 +#define ixDPM_TABLE_222 0x3f374 +#define ixDPM_TABLE_223 0x3f378 +#define ixDPM_TABLE_224 0x3f37c +#define ixDPM_TABLE_225 0x3f380 +#define ixDPM_TABLE_226 0x3f384 +#define ixDPM_TABLE_227 0x3f388 +#define ixDPM_TABLE_228 0x3f38c +#define ixDPM_TABLE_229 0x3f390 +#define ixDPM_TABLE_230 0x3f394 +#define ixDPM_TABLE_231 0x3f398 +#define ixDPM_TABLE_232 0x3f39c +#define ixDPM_TABLE_233 0x3f3a0 +#define ixDPM_TABLE_234 0x3f3a4 +#define ixDPM_TABLE_235 0x3f3a8 +#define ixDPM_TABLE_236 0x3f3ac +#define ixDPM_TABLE_237 0x3f3b0 +#define ixDPM_TABLE_238 0x3f3b4 +#define ixDPM_TABLE_239 0x3f3b8 +#define ixDPM_TABLE_240 0x3f3bc +#define ixDPM_TABLE_241 0x3f3c0 +#define ixDPM_TABLE_242 0x3f3c4 +#define ixDPM_TABLE_243 0x3f3c8 +#define ixDPM_TABLE_244 0x3f3cc +#define ixDPM_TABLE_245 0x3f3d0 +#define ixDPM_TABLE_246 0x3f3d4 +#define ixDPM_TABLE_247 0x3f3d8 +#define ixDPM_TABLE_248 0x3f3dc +#define ixDPM_TABLE_249 0x3f3e0 +#define ixDPM_TABLE_250 0x3f3e4 +#define ixDPM_TABLE_251 0x3f3e8 +#define ixDPM_TABLE_252 0x3f3ec +#define ixDPM_TABLE_253 0x3f3f0 +#define ixDPM_TABLE_254 0x3f3f4 +#define ixDPM_TABLE_255 0x3f3f8 +#define ixDPM_TABLE_256 0x3f3fc +#define ixDPM_TABLE_257 0x3f400 +#define ixDPM_TABLE_258 0x3f404 +#define ixDPM_TABLE_259 0x3f408 +#define ixDPM_TABLE_260 0x3f40c +#define ixDPM_TABLE_261 0x3f410 +#define ixDPM_TABLE_262 0x3f414 +#define ixDPM_TABLE_263 0x3f418 +#define ixDPM_TABLE_264 0x3f41c +#define ixDPM_TABLE_265 0x3f420 +#define ixDPM_TABLE_266 0x3f424 +#define ixDPM_TABLE_267 0x3f428 +#define ixDPM_TABLE_268 0x3f42c +#define ixDPM_TABLE_269 0x3f430 +#define ixDPM_TABLE_270 0x3f434 +#define ixDPM_TABLE_271 0x3f438 +#define ixDPM_TABLE_272 0x3f43c +#define ixDPM_TABLE_273 0x3f440 +#define ixDPM_TABLE_274 0x3f444 +#define ixDPM_TABLE_275 0x3f448 +#define ixDPM_TABLE_276 0x3f44c +#define ixDPM_TABLE_277 0x3f450 +#define ixDPM_TABLE_278 0x3f454 +#define ixDPM_TABLE_279 0x3f458 +#define ixDPM_TABLE_280 0x3f45c +#define ixDPM_TABLE_281 0x3f460 +#define ixDPM_TABLE_282 0x3f464 +#define ixDPM_TABLE_283 0x3f468 +#define ixDPM_TABLE_284 0x3f46c +#define ixDPM_TABLE_285 0x3f470 +#define ixDPM_TABLE_286 0x3f474 +#define ixDPM_TABLE_287 0x3f478 +#define ixDPM_TABLE_288 0x3f47c +#define ixDPM_TABLE_289 0x3f480 +#define ixDPM_TABLE_290 0x3f484 +#define ixDPM_TABLE_291 0x3f488 +#define ixDPM_TABLE_292 0x3f48c +#define ixDPM_TABLE_293 0x3f490 +#define ixDPM_TABLE_294 0x3f494 +#define ixDPM_TABLE_295 0x3f498 +#define ixDPM_TABLE_296 0x3f49c +#define ixDPM_TABLE_297 0x3f4a0 +#define ixDPM_TABLE_298 0x3f4a4 +#define ixDPM_TABLE_299 0x3f4a8 +#define ixDPM_TABLE_300 0x3f4ac +#define ixDPM_TABLE_301 0x3f4b0 +#define ixDPM_TABLE_302 0x3f4b4 +#define ixDPM_TABLE_303 0x3f4b8 +#define ixDPM_TABLE_304 0x3f4bc +#define ixDPM_TABLE_305 0x3f4c0 +#define ixDPM_TABLE_306 0x3f4c4 +#define ixDPM_TABLE_307 0x3f4c8 +#define ixDPM_TABLE_308 0x3f4cc +#define ixDPM_TABLE_309 0x3f4d0 +#define ixDPM_TABLE_310 0x3f4d4 +#define ixDPM_TABLE_311 0x3f4d8 +#define ixDPM_TABLE_312 0x3f4dc +#define ixDPM_TABLE_313 0x3f4e0 +#define ixDPM_TABLE_314 0x3f4e4 +#define ixDPM_TABLE_315 0x3f4e8 +#define ixDPM_TABLE_316 0x3f4ec +#define ixDPM_TABLE_317 0x3f4f0 +#define ixDPM_TABLE_318 0x3f4f4 +#define ixDPM_TABLE_319 0x3f4f8 +#define ixDPM_TABLE_320 0x3f4fc +#define ixDPM_TABLE_321 0x3f500 +#define ixDPM_TABLE_322 0x3f504 +#define ixDPM_TABLE_323 0x3f508 +#define ixDPM_TABLE_324 0x3f50c +#define ixDPM_TABLE_325 0x3f510 +#define ixDPM_TABLE_326 0x3f514 +#define ixDPM_TABLE_327 0x3f518 +#define ixDPM_TABLE_328 0x3f51c +#define ixDPM_TABLE_329 0x3f520 +#define ixDPM_TABLE_330 0x3f524 +#define ixDPM_TABLE_331 0x3f528 +#define ixDPM_TABLE_332 0x3f52c +#define ixDPM_TABLE_333 0x3f530 +#define ixDPM_TABLE_334 0x3f534 +#define ixDPM_TABLE_335 0x3f538 +#define ixDPM_TABLE_336 0x3f53c +#define ixDPM_TABLE_337 0x3f540 +#define ixDPM_TABLE_338 0x3f544 +#define ixDPM_TABLE_339 0x3f548 +#define ixDPM_TABLE_340 0x3f54c +#define ixDPM_TABLE_341 0x3f550 +#define ixDPM_TABLE_342 0x3f554 +#define ixDPM_TABLE_343 0x3f558 +#define ixDPM_TABLE_344 0x3f55c +#define ixDPM_TABLE_345 0x3f560 +#define ixDPM_TABLE_346 0x3f564 +#define ixDPM_TABLE_347 0x3f568 +#define ixDPM_TABLE_348 0x3f56c +#define ixDPM_TABLE_349 0x3f570 +#define ixDPM_TABLE_350 0x3f574 +#define ixDPM_TABLE_351 0x3f578 +#define ixDPM_TABLE_352 0x3f57c +#define ixDPM_TABLE_353 0x3f580 +#define ixDPM_TABLE_354 0x3f584 +#define ixDPM_TABLE_355 0x3f588 +#define ixDPM_TABLE_356 0x3f58c +#define ixDPM_TABLE_357 0x3f590 +#define ixDPM_TABLE_358 0x3f594 +#define ixDPM_TABLE_359 0x3f598 +#define ixDPM_TABLE_360 0x3f59c +#define ixDPM_TABLE_361 0x3f5a0 +#define ixDPM_TABLE_362 0x3f5a4 +#define ixDPM_TABLE_363 0x3f5a8 +#define ixDPM_TABLE_364 0x3f5ac +#define ixDPM_TABLE_365 0x3f5b0 +#define ixDPM_TABLE_366 0x3f5b4 +#define ixDPM_TABLE_367 0x3f5b8 +#define ixDPM_TABLE_368 0x3f5bc +#define ixDPM_TABLE_369 0x3f5c0 +#define ixDPM_TABLE_370 0x3f5c4 +#define ixDPM_TABLE_371 0x3f5c8 +#define ixDPM_TABLE_372 0x3f5cc +#define ixDPM_TABLE_373 0x3f5d0 +#define ixDPM_TABLE_374 0x3f5d4 +#define ixDPM_TABLE_375 0x3f5d8 +#define ixDPM_TABLE_376 0x3f5dc +#define ixDPM_TABLE_377 0x3f5e0 +#define ixDPM_TABLE_378 0x3f5e4 +#define ixDPM_TABLE_379 0x3f5e8 +#define ixDPM_TABLE_380 0x3f5ec +#define ixDPM_TABLE_381 0x3f5f0 +#define ixDPM_TABLE_382 0x3f5f4 +#define ixDPM_TABLE_383 0x3f5f8 +#define ixDPM_TABLE_384 0x3f5fc +#define ixDPM_TABLE_385 0x3f600 +#define ixDPM_TABLE_386 0x3f604 +#define ixDPM_TABLE_387 0x3f608 +#define ixDPM_TABLE_388 0x3f60c +#define ixDPM_TABLE_389 0x3f610 +#define ixDPM_TABLE_390 0x3f614 +#define ixDPM_TABLE_391 0x3f618 +#define ixDPM_TABLE_392 0x3f61c +#define ixDPM_TABLE_393 0x3f620 +#define ixDPM_TABLE_394 0x3f624 +#define ixDPM_TABLE_395 0x3f628 +#define ixDPM_TABLE_396 0x3f62c +#define ixDPM_TABLE_397 0x3f630 +#define ixDPM_TABLE_398 0x3f634 +#define ixDPM_TABLE_399 0x3f638 +#define ixDPM_TABLE_400 0x3f63c +#define ixDPM_TABLE_401 0x3f640 +#define ixDPM_TABLE_402 0x3f644 +#define ixDPM_TABLE_403 0x3f648 +#define ixDPM_TABLE_404 0x3f64c +#define ixDPM_TABLE_405 0x3f650 +#define ixDPM_TABLE_406 0x3f654 +#define ixDPM_TABLE_407 0x3f658 +#define ixDPM_TABLE_408 0x3f65c +#define ixDPM_TABLE_409 0x3f660 +#define ixDPM_TABLE_410 0x3f664 +#define ixDPM_TABLE_411 0x3f668 +#define ixDPM_TABLE_412 0x3f66c +#define ixDPM_TABLE_413 0x3f670 +#define ixDPM_TABLE_414 0x3f674 +#define ixDPM_TABLE_415 0x3f678 +#define ixDPM_TABLE_416 0x3f67c +#define ixDPM_TABLE_417 0x3f680 +#define ixDPM_TABLE_418 0x3f684 +#define ixDPM_TABLE_419 0x3f688 +#define ixDPM_TABLE_420 0x3f68c +#define ixDPM_TABLE_421 0x3f690 +#define ixDPM_TABLE_422 0x3f694 +#define ixDPM_TABLE_423 0x3f698 +#define ixDPM_TABLE_424 0x3f69c +#define ixDPM_TABLE_425 0x3f6a0 +#define ixDPM_TABLE_426 0x3f6a4 +#define ixDPM_TABLE_427 0x3f6a8 +#define ixDPM_TABLE_428 0x3f6ac +#define ixDPM_TABLE_429 0x3f6b0 +#define ixDPM_TABLE_430 0x3f6b4 +#define ixDPM_TABLE_431 0x3f6b8 +#define ixDPM_TABLE_432 0x3f6bc +#define ixDPM_TABLE_433 0x3f6c0 +#define ixDPM_TABLE_434 0x3f6c4 +#define ixDPM_TABLE_435 0x3f6c8 +#define ixDPM_TABLE_436 0x3f6cc +#define ixDPM_TABLE_437 0x3f6d0 +#define ixDPM_TABLE_438 0x3f6d4 +#define ixDPM_TABLE_439 0x3f6d8 +#define ixDPM_TABLE_440 0x3f6dc +#define ixDPM_TABLE_441 0x3f6e0 +#define ixDPM_TABLE_442 0x3f6e4 +#define ixDPM_TABLE_443 0x3f6e8 +#define ixDPM_TABLE_444 0x3f6ec +#define ixDPM_TABLE_445 0x3f6f0 +#define ixDPM_TABLE_446 0x3f6f4 +#define ixDPM_TABLE_447 0x3f6f8 +#define ixDPM_TABLE_448 0x3f6fc +#define ixDPM_TABLE_449 0x3f700 +#define ixDPM_TABLE_450 0x3f704 +#define ixDPM_TABLE_451 0x3f708 +#define ixDPM_TABLE_452 0x3f70c +#define ixDPM_TABLE_453 0x3f710 +#define ixDPM_TABLE_454 0x3f714 +#define ixDPM_TABLE_455 0x3f718 +#define ixDPM_TABLE_456 0x3f71c +#define ixDPM_TABLE_457 0x3f720 +#define ixDPM_TABLE_458 0x3f724 +#define ixDPM_TABLE_459 0x3f728 +#define ixDPM_TABLE_460 0x3f72c +#define ixDPM_TABLE_461 0x3f730 +#define ixDPM_TABLE_462 0x3f734 +#define ixDPM_TABLE_463 0x3f738 +#define ixDPM_TABLE_464 0x3f73c +#define ixDPM_TABLE_465 0x3f740 +#define ixDPM_TABLE_466 0x3f744 +#define ixDPM_TABLE_467 0x3f748 +#define ixDPM_TABLE_468 0x3f74c +#define ixDPM_TABLE_469 0x3f750 +#define ixDPM_TABLE_470 0x3f754 +#define ixDPM_TABLE_471 0x3f758 +#define ixDPM_TABLE_472 0x3f75c +#define ixDPM_TABLE_473 0x3f760 +#define ixDPM_TABLE_474 0x3f764 +#define ixDPM_TABLE_475 0x3f768 +#define ixDPM_TABLE_476 0x3f76c +#define ixDPM_TABLE_477 0x3f770 +#define ixDPM_TABLE_478 0x3f774 +#define ixDPM_TABLE_479 0x3f778 +#define ixDPM_TABLE_480 0x3f77c +#define ixDPM_TABLE_481 0x3f780 +#define ixDPM_TABLE_482 0x3f784 +#define ixDPM_TABLE_483 0x3f788 +#define ixDPM_TABLE_484 0x3f78c +#define ixDPM_TABLE_485 0x3f790 +#define ixDPM_TABLE_486 0x3f794 +#define ixDPM_TABLE_487 0x3f798 +#define ixDPM_TABLE_488 0x3f79c +#define ixDPM_TABLE_489 0x3f7a0 +#define ixDPM_TABLE_490 0x3f7a4 +#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f900 +#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f904 +#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f908 +#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f90c +#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f910 +#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f914 +#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f918 +#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f91c +#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f920 +#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f924 +#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f928 +#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f92c +#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f930 +#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f934 +#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f938 +#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f93c +#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f940 +#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f944 +#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f948 +#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f94c +#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f950 +#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f954 +#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f958 +#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f95c +#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f960 +#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f964 +#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f968 +#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f96c +#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f970 +#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f974 +#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f978 +#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f97c +#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f980 +#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f984 +#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f988 +#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f98c +#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f990 +#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f994 +#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f998 +#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f99c +#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f9a0 +#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f9a4 +#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f9a8 +#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f9ac +#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f9b0 +#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f9b4 +#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f9b8 +#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f9bc +#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f9c0 +#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f9c4 +#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f9c8 +#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f9cc +#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f9d0 +#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f9d4 +#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f9d8 +#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f9dc +#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f9e0 +#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f9e4 +#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f9e8 +#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f9ec +#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f9f0 +#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f9f4 +#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f9f8 +#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f9fc +#define ixMCARB_DRAM_TIMING_TABLE_65 0x3fa00 +#define ixMCARB_DRAM_TIMING_TABLE_66 0x3fa04 +#define ixMCARB_DRAM_TIMING_TABLE_67 0x3fa08 +#define ixMCARB_DRAM_TIMING_TABLE_68 0x3fa0c +#define ixMCARB_DRAM_TIMING_TABLE_69 0x3fa10 +#define ixMCARB_DRAM_TIMING_TABLE_70 0x3fa14 +#define ixMCARB_DRAM_TIMING_TABLE_71 0x3fa18 +#define ixMCARB_DRAM_TIMING_TABLE_72 0x3fa1c +#define ixMCARB_DRAM_TIMING_TABLE_73 0x3fa20 +#define ixMCARB_DRAM_TIMING_TABLE_74 0x3fa24 +#define ixMCARB_DRAM_TIMING_TABLE_75 0x3fa28 +#define ixMCARB_DRAM_TIMING_TABLE_76 0x3fa2c +#define ixMCARB_DRAM_TIMING_TABLE_77 0x3fa30 +#define ixMCARB_DRAM_TIMING_TABLE_78 0x3fa34 +#define ixMCARB_DRAM_TIMING_TABLE_79 0x3fa38 +#define ixMCARB_DRAM_TIMING_TABLE_80 0x3fa3c +#define ixMCARB_DRAM_TIMING_TABLE_81 0x3fa40 +#define ixMCARB_DRAM_TIMING_TABLE_82 0x3fa44 +#define ixMCARB_DRAM_TIMING_TABLE_83 0x3fa48 +#define ixMCARB_DRAM_TIMING_TABLE_84 0x3fa4c +#define ixMCARB_DRAM_TIMING_TABLE_85 0x3fa50 +#define ixMCARB_DRAM_TIMING_TABLE_86 0x3fa54 +#define ixMCARB_DRAM_TIMING_TABLE_87 0x3fa58 +#define ixMCARB_DRAM_TIMING_TABLE_88 0x3fa5c +#define ixMCARB_DRAM_TIMING_TABLE_89 0x3fa60 +#define ixMCARB_DRAM_TIMING_TABLE_90 0x3fa64 +#define ixMCARB_DRAM_TIMING_TABLE_91 0x3fa68 +#define ixMCARB_DRAM_TIMING_TABLE_92 0x3fa6c +#define ixMCARB_DRAM_TIMING_TABLE_93 0x3fa70 +#define ixMCARB_DRAM_TIMING_TABLE_94 0x3fa74 +#define ixMCARB_DRAM_TIMING_TABLE_95 0x3fa78 +#define ixMCARB_DRAM_TIMING_TABLE_96 0x3fa7c +#define ixMC_REGISTERS_TABLE_1 0x3fa80 +#define ixMC_REGISTERS_TABLE_2 0x3fa84 +#define ixMC_REGISTERS_TABLE_3 0x3fa88 +#define ixMC_REGISTERS_TABLE_4 0x3fa8c +#define ixMC_REGISTERS_TABLE_5 0x3fa90 +#define ixMC_REGISTERS_TABLE_6 0x3fa94 +#define ixMC_REGISTERS_TABLE_7 0x3fa98 +#define ixMC_REGISTERS_TABLE_8 0x3fa9c +#define ixMC_REGISTERS_TABLE_9 0x3faa0 +#define ixMC_REGISTERS_TABLE_10 0x3faa4 +#define ixMC_REGISTERS_TABLE_11 0x3faa8 +#define ixMC_REGISTERS_TABLE_12 0x3faac +#define ixMC_REGISTERS_TABLE_13 0x3fab0 +#define ixMC_REGISTERS_TABLE_14 0x3fab4 +#define ixMC_REGISTERS_TABLE_15 0x3fab8 +#define ixMC_REGISTERS_TABLE_16 0x3fabc +#define ixMC_REGISTERS_TABLE_17 0x3fac0 +#define ixMC_REGISTERS_TABLE_18 0x3fac4 +#define ixMC_REGISTERS_TABLE_19 0x3fac8 +#define ixMC_REGISTERS_TABLE_20 0x3facc +#define ixMC_REGISTERS_TABLE_21 0x3fad0 +#define ixMC_REGISTERS_TABLE_22 0x3fad4 +#define ixMC_REGISTERS_TABLE_23 0x3fad8 +#define ixMC_REGISTERS_TABLE_24 0x3fadc +#define ixMC_REGISTERS_TABLE_25 0x3fae0 +#define ixMC_REGISTERS_TABLE_26 0x3fae4 +#define ixMC_REGISTERS_TABLE_27 0x3fae8 +#define ixMC_REGISTERS_TABLE_28 0x3faec +#define ixMC_REGISTERS_TABLE_29 0x3faf0 +#define ixMC_REGISTERS_TABLE_30 0x3faf4 +#define ixMC_REGISTERS_TABLE_31 0x3faf8 +#define ixMC_REGISTERS_TABLE_32 0x3fafc +#define ixMC_REGISTERS_TABLE_33 0x3fb00 +#define ixMC_REGISTERS_TABLE_34 0x3fb04 +#define ixMC_REGISTERS_TABLE_35 0x3fb08 +#define ixMC_REGISTERS_TABLE_36 0x3fb0c +#define ixMC_REGISTERS_TABLE_37 0x3fb10 +#define ixMC_REGISTERS_TABLE_38 0x3fb14 +#define ixMC_REGISTERS_TABLE_39 0x3fb18 +#define ixMC_REGISTERS_TABLE_40 0x3fb1c +#define ixMC_REGISTERS_TABLE_41 0x3fb20 +#define ixMC_REGISTERS_TABLE_42 0x3fb24 +#define ixMC_REGISTERS_TABLE_43 0x3fb28 +#define ixMC_REGISTERS_TABLE_44 0x3fb2c +#define ixMC_REGISTERS_TABLE_45 0x3fb30 +#define ixMC_REGISTERS_TABLE_46 0x3fb34 +#define ixMC_REGISTERS_TABLE_47 0x3fb38 +#define ixMC_REGISTERS_TABLE_48 0x3fb3c +#define ixMC_REGISTERS_TABLE_49 0x3fb40 +#define ixMC_REGISTERS_TABLE_50 0x3fb44 +#define ixMC_REGISTERS_TABLE_51 0x3fb48 +#define ixMC_REGISTERS_TABLE_52 0x3fb4c +#define ixMC_REGISTERS_TABLE_53 0x3fb50 +#define ixMC_REGISTERS_TABLE_54 0x3fb54 +#define ixMC_REGISTERS_TABLE_55 0x3fb58 +#define ixMC_REGISTERS_TABLE_56 0x3fb5c +#define ixMC_REGISTERS_TABLE_57 0x3fb60 +#define ixMC_REGISTERS_TABLE_58 0x3fb64 +#define ixMC_REGISTERS_TABLE_59 0x3fb68 +#define ixMC_REGISTERS_TABLE_60 0x3fb6c +#define ixMC_REGISTERS_TABLE_61 0x3fb70 +#define ixMC_REGISTERS_TABLE_62 0x3fb74 +#define ixMC_REGISTERS_TABLE_63 0x3fb78 +#define ixMC_REGISTERS_TABLE_64 0x3fb7c +#define ixMC_REGISTERS_TABLE_65 0x3fb80 +#define ixMC_REGISTERS_TABLE_66 0x3fb84 +#define ixMC_REGISTERS_TABLE_67 0x3fb88 +#define ixMC_REGISTERS_TABLE_68 0x3fb8c +#define ixMC_REGISTERS_TABLE_69 0x3fb90 +#define ixMC_REGISTERS_TABLE_70 0x3fb94 +#define ixMC_REGISTERS_TABLE_71 0x3fb98 +#define ixMC_REGISTERS_TABLE_72 0x3fb9c +#define ixMC_REGISTERS_TABLE_73 0x3fba0 +#define ixMC_REGISTERS_TABLE_74 0x3fba4 +#define ixMC_REGISTERS_TABLE_75 0x3fba8 +#define ixMC_REGISTERS_TABLE_76 0x3fbac +#define ixMC_REGISTERS_TABLE_77 0x3fbb0 +#define ixMC_REGISTERS_TABLE_78 0x3fbb4 +#define ixMC_REGISTERS_TABLE_79 0x3fbb8 +#define ixMC_REGISTERS_TABLE_80 0x3fbbc +#define ixMC_REGISTERS_TABLE_81 0x3fbc0 +#define ixFAN_TABLE_1 0x3fbc4 +#define ixFAN_TABLE_2 0x3fbc8 +#define ixFAN_TABLE_3 0x3fbcc +#define ixFAN_TABLE_4 0x3fbd0 +#define ixFAN_TABLE_5 0x3fbd4 +#define ixFAN_TABLE_6 0x3fbd8 +#define ixFAN_TABLE_7 0x3fbdc +#define ixFAN_TABLE_8 0x3fbe0 +#define ixFAN_TABLE_9 0x3fbe4 +#define ixSOFT_REGISTERS_TABLE_1 0x3fbe8 +#define ixSOFT_REGISTERS_TABLE_2 0x3fbec +#define ixSOFT_REGISTERS_TABLE_3 0x3fbf0 +#define ixSOFT_REGISTERS_TABLE_4 0x3fbf4 +#define ixSOFT_REGISTERS_TABLE_5 0x3fbf8 +#define ixSOFT_REGISTERS_TABLE_6 0x3fbfc +#define ixSOFT_REGISTERS_TABLE_7 0x3fc00 +#define ixSOFT_REGISTERS_TABLE_8 0x3fc04 +#define ixSOFT_REGISTERS_TABLE_9 0x3fc08 +#define ixSOFT_REGISTERS_TABLE_10 0x3fc0c +#define ixSOFT_REGISTERS_TABLE_11 0x3fc10 +#define ixSOFT_REGISTERS_TABLE_12 0x3fc14 +#define ixSOFT_REGISTERS_TABLE_13 0x3fc18 +#define ixSOFT_REGISTERS_TABLE_14 0x3fc1c +#define ixSOFT_REGISTERS_TABLE_15 0x3fc20 +#define ixSOFT_REGISTERS_TABLE_16 0x3fc24 +#define ixSOFT_REGISTERS_TABLE_17 0x3fc28 +#define ixSOFT_REGISTERS_TABLE_18 0x3fc2c +#define ixSOFT_REGISTERS_TABLE_19 0x3fc30 +#define ixSOFT_REGISTERS_TABLE_20 0x3fc34 +#define ixSOFT_REGISTERS_TABLE_21 0x3fc38 +#define ixSOFT_REGISTERS_TABLE_22 0x3fc3c +#define ixSOFT_REGISTERS_TABLE_23 0x3fc40 +#define ixSOFT_REGISTERS_TABLE_24 0x3fc44 +#define ixSOFT_REGISTERS_TABLE_25 0x3fc48 +#define ixSOFT_REGISTERS_TABLE_26 0x3fc4c +#define ixSOFT_REGISTERS_TABLE_27 0x3fc50 +#define ixSOFT_REGISTERS_TABLE_28 0x3fc54 +#define ixSOFT_REGISTERS_TABLE_29 0x3fc58 +#define ixSOFT_REGISTERS_TABLE_30 0x3fc5c +#define ixPM_FUSES_1 0x3fc60 +#define ixPM_FUSES_2 0x3fc64 +#define ixPM_FUSES_3 0x3fc68 +#define ixPM_FUSES_4 0x3fc6c +#define ixPM_FUSES_5 0x3fc70 +#define ixPM_FUSES_6 0x3fc74 +#define ixPM_FUSES_7 0x3fc78 +#define ixPM_FUSES_8 0x3fc7c +#define ixPM_FUSES_9 0x3fc80 +#define ixPM_FUSES_10 0x3fc84 +#define ixPM_FUSES_11 0x3fc88 +#define ixPM_FUSES_12 0x3fc8c +#define ixPM_FUSES_13 0x3fc90 +#define ixPM_FUSES_14 0x3fc94 +#define ixPM_FUSES_15 0x3fc98 +#define ixSMU_PM_STATUS_0 0x3fe00 +#define ixSMU_PM_STATUS_1 0x3fe04 +#define ixSMU_PM_STATUS_2 0x3fe08 +#define ixSMU_PM_STATUS_3 0x3fe0c +#define ixSMU_PM_STATUS_4 0x3fe10 +#define ixSMU_PM_STATUS_5 0x3fe14 +#define ixSMU_PM_STATUS_6 0x3fe18 +#define ixSMU_PM_STATUS_7 0x3fe1c +#define ixSMU_PM_STATUS_8 0x3fe20 +#define ixSMU_PM_STATUS_9 0x3fe24 +#define ixSMU_PM_STATUS_10 0x3fe28 +#define ixSMU_PM_STATUS_11 0x3fe2c +#define ixSMU_PM_STATUS_12 0x3fe30 +#define ixSMU_PM_STATUS_13 0x3fe34 +#define ixSMU_PM_STATUS_14 0x3fe38 +#define ixSMU_PM_STATUS_15 0x3fe3c +#define ixSMU_PM_STATUS_16 0x3fe40 +#define ixSMU_PM_STATUS_17 0x3fe44 +#define ixSMU_PM_STATUS_18 0x3fe48 +#define ixSMU_PM_STATUS_19 0x3fe4c +#define ixSMU_PM_STATUS_20 0x3fe50 +#define ixSMU_PM_STATUS_21 0x3fe54 +#define ixSMU_PM_STATUS_22 0x3fe58 +#define ixSMU_PM_STATUS_23 0x3fe5c +#define ixSMU_PM_STATUS_24 0x3fe60 +#define ixSMU_PM_STATUS_25 0x3fe64 +#define ixSMU_PM_STATUS_26 0x3fe68 +#define ixSMU_PM_STATUS_27 0x3fe6c +#define ixSMU_PM_STATUS_28 0x3fe70 +#define ixSMU_PM_STATUS_29 0x3fe74 +#define ixSMU_PM_STATUS_30 0x3fe78 +#define ixSMU_PM_STATUS_31 0x3fe7c +#define ixSMU_PM_STATUS_32 0x3fe80 +#define ixSMU_PM_STATUS_33 0x3fe84 +#define ixSMU_PM_STATUS_34 0x3fe88 +#define ixSMU_PM_STATUS_35 0x3fe8c +#define ixSMU_PM_STATUS_36 0x3fe90 +#define ixSMU_PM_STATUS_37 0x3fe94 +#define ixSMU_PM_STATUS_38 0x3fe98 +#define ixSMU_PM_STATUS_39 0x3fe9c +#define ixSMU_PM_STATUS_40 0x3fea0 +#define ixSMU_PM_STATUS_41 0x3fea4 +#define ixSMU_PM_STATUS_42 0x3fea8 +#define ixSMU_PM_STATUS_43 0x3feac +#define ixSMU_PM_STATUS_44 0x3feb0 +#define ixSMU_PM_STATUS_45 0x3feb4 +#define ixSMU_PM_STATUS_46 0x3feb8 +#define ixSMU_PM_STATUS_47 0x3febc +#define ixSMU_PM_STATUS_48 0x3fec0 +#define ixSMU_PM_STATUS_49 0x3fec4 +#define ixSMU_PM_STATUS_50 0x3fec8 +#define ixSMU_PM_STATUS_51 0x3fecc +#define ixSMU_PM_STATUS_52 0x3fed0 +#define ixSMU_PM_STATUS_53 0x3fed4 +#define ixSMU_PM_STATUS_54 0x3fed8 +#define ixSMU_PM_STATUS_55 0x3fedc +#define ixSMU_PM_STATUS_56 0x3fee0 +#define ixSMU_PM_STATUS_57 0x3fee4 +#define ixSMU_PM_STATUS_58 0x3fee8 +#define ixSMU_PM_STATUS_59 0x3feec +#define ixSMU_PM_STATUS_60 0x3fef0 +#define ixSMU_PM_STATUS_61 0x3fef4 +#define ixSMU_PM_STATUS_62 0x3fef8 +#define ixSMU_PM_STATUS_63 0x3fefc +#define ixSMU_PM_STATUS_64 0x3ff00 +#define ixSMU_PM_STATUS_65 0x3ff04 +#define ixSMU_PM_STATUS_66 0x3ff08 +#define ixSMU_PM_STATUS_67 0x3ff0c +#define ixSMU_PM_STATUS_68 0x3ff10 +#define ixSMU_PM_STATUS_69 0x3ff14 +#define ixSMU_PM_STATUS_70 0x3ff18 +#define ixSMU_PM_STATUS_71 0x3ff1c +#define ixSMU_PM_STATUS_72 0x3ff20 +#define ixSMU_PM_STATUS_73 0x3ff24 +#define ixSMU_PM_STATUS_74 0x3ff28 +#define ixSMU_PM_STATUS_75 0x3ff2c +#define ixSMU_PM_STATUS_76 0x3ff30 +#define ixSMU_PM_STATUS_77 0x3ff34 +#define ixSMU_PM_STATUS_78 0x3ff38 +#define ixSMU_PM_STATUS_79 0x3ff3c +#define ixSMU_PM_STATUS_80 0x3ff40 +#define ixSMU_PM_STATUS_81 0x3ff44 +#define ixSMU_PM_STATUS_82 0x3ff48 +#define ixSMU_PM_STATUS_83 0x3ff4c +#define ixSMU_PM_STATUS_84 0x3ff50 +#define ixSMU_PM_STATUS_85 0x3ff54 +#define ixSMU_PM_STATUS_86 0x3ff58 +#define ixSMU_PM_STATUS_87 0x3ff5c +#define ixSMU_PM_STATUS_88 0x3ff60 +#define ixSMU_PM_STATUS_89 0x3ff64 +#define ixSMU_PM_STATUS_90 0x3ff68 +#define ixSMU_PM_STATUS_91 0x3ff6c +#define ixSMU_PM_STATUS_92 0x3ff70 +#define ixSMU_PM_STATUS_93 0x3ff74 +#define ixSMU_PM_STATUS_94 0x3ff78 +#define ixSMU_PM_STATUS_95 0x3ff7c +#define ixSMU_PM_STATUS_96 0x3ff80 +#define ixSMU_PM_STATUS_97 0x3ff84 +#define ixSMU_PM_STATUS_98 0x3ff88 +#define ixSMU_PM_STATUS_99 0x3ff8c +#define ixSMU_PM_STATUS_100 0x3ff90 +#define ixSMU_PM_STATUS_101 0x3ff94 +#define ixSMU_PM_STATUS_102 0x3ff98 +#define ixSMU_PM_STATUS_103 0x3ff9c +#define ixSMU_PM_STATUS_104 0x3ffa0 +#define ixSMU_PM_STATUS_105 0x3ffa4 +#define ixSMU_PM_STATUS_106 0x3ffa8 +#define ixSMU_PM_STATUS_107 0x3ffac +#define ixSMU_PM_STATUS_108 0x3ffb0 +#define ixSMU_PM_STATUS_109 0x3ffb4 +#define ixSMU_PM_STATUS_110 0x3ffb8 +#define ixSMU_PM_STATUS_111 0x3ffbc +#define ixSMU_PM_STATUS_112 0x3ffc0 +#define ixSMU_PM_STATUS_113 0x3ffc4 +#define ixSMU_PM_STATUS_114 0x3ffc8 +#define ixSMU_PM_STATUS_115 0x3ffcc +#define ixSMU_PM_STATUS_116 0x3ffd0 +#define ixSMU_PM_STATUS_117 0x3ffd4 +#define ixSMU_PM_STATUS_118 0x3ffd8 +#define ixSMU_PM_STATUS_119 0x3ffdc +#define ixSMU_PM_STATUS_120 0x3ffe0 +#define ixSMU_PM_STATUS_121 0x3ffe4 +#define ixSMU_PM_STATUS_122 0x3ffe8 +#define ixSMU_PM_STATUS_123 0x3ffec +#define ixSMU_PM_STATUS_124 0x3fff0 +#define ixSMU_PM_STATUS_125 0x3fff4 +#define ixSMU_PM_STATUS_126 0x3fff8 +#define ixSMU_PM_STATUS_127 0x3fffc +#define ixCG_THERMAL_INT_ENA 0xc2100024 +#define ixCG_THERMAL_INT_CTRL 0xc2100028 +#define ixCG_THERMAL_INT_STATUS 0xc210002c +#define ixCG_THERMAL_CTRL 0xc0300004 +#define ixCG_THERMAL_STATUS 0xc0300008 +#define ixCG_THERMAL_INT 0xc030000c +#define ixCG_MULT_THERMAL_CTRL 0xc0300010 +#define ixCG_MULT_THERMAL_STATUS 0xc0300014 +#define ixCG_FDO_CTRL0 0xc0300064 +#define ixCG_FDO_CTRL1 0xc0300068 +#define ixCG_FDO_CTRL2 0xc030006c +#define ixCG_TACH_CTRL 0xc0300070 +#define ixCG_TACH_STATUS 0xc0300074 +#define ixCC_THM_STRAPS0 0xc0300080 +#define ixTHM_TMON0_RDIL0_DATA 0xc0300100 +#define ixTHM_TMON0_RDIL1_DATA 0xc0300104 +#define ixTHM_TMON0_RDIL2_DATA 0xc0300108 +#define ixTHM_TMON0_RDIL3_DATA 0xc030010c +#define ixTHM_TMON0_RDIL4_DATA 0xc0300110 +#define ixTHM_TMON0_RDIL5_DATA 0xc0300114 +#define ixTHM_TMON0_RDIL6_DATA 0xc0300118 +#define ixTHM_TMON0_RDIL7_DATA 0xc030011c +#define ixTHM_TMON0_RDIL8_DATA 0xc0300120 +#define ixTHM_TMON0_RDIL9_DATA 0xc0300124 +#define ixTHM_TMON0_RDIL10_DATA 0xc0300128 +#define ixTHM_TMON0_RDIL11_DATA 0xc030012c +#define ixTHM_TMON0_RDIL12_DATA 0xc0300130 +#define ixTHM_TMON0_RDIL13_DATA 0xc0300134 +#define ixTHM_TMON0_RDIL14_DATA 0xc0300138 +#define ixTHM_TMON0_RDIL15_DATA 0xc030013c +#define ixTHM_TMON0_RDIR0_DATA 0xc0300140 +#define ixTHM_TMON0_RDIR1_DATA 0xc0300144 +#define ixTHM_TMON0_RDIR2_DATA 0xc0300148 +#define ixTHM_TMON0_RDIR3_DATA 0xc030014c +#define ixTHM_TMON0_RDIR4_DATA 0xc0300150 +#define ixTHM_TMON0_RDIR5_DATA 0xc0300154 +#define ixTHM_TMON0_RDIR6_DATA 0xc0300158 +#define ixTHM_TMON0_RDIR7_DATA 0xc030015c +#define ixTHM_TMON0_RDIR8_DATA 0xc0300160 +#define ixTHM_TMON0_RDIR9_DATA 0xc0300164 +#define ixTHM_TMON0_RDIR10_DATA 0xc0300168 +#define ixTHM_TMON0_RDIR11_DATA 0xc030016c +#define ixTHM_TMON0_RDIR12_DATA 0xc0300170 +#define ixTHM_TMON0_RDIR13_DATA 0xc0300174 +#define ixTHM_TMON0_RDIR14_DATA 0xc0300178 +#define ixTHM_TMON0_RDIR15_DATA 0xc030017c +#define ixTHM_TMON1_RDIL0_DATA 0xc0300180 +#define ixTHM_TMON1_RDIL1_DATA 0xc0300184 +#define ixTHM_TMON1_RDIL2_DATA 0xc0300188 +#define ixTHM_TMON1_RDIL3_DATA 0xc030018c +#define ixTHM_TMON1_RDIL4_DATA 0xc0300190 +#define ixTHM_TMON1_RDIL5_DATA 0xc0300194 +#define ixTHM_TMON1_RDIL6_DATA 0xc0300198 +#define ixTHM_TMON1_RDIL7_DATA 0xc030019c +#define ixTHM_TMON1_RDIL8_DATA 0xc03001a0 +#define ixTHM_TMON1_RDIL9_DATA 0xc03001a4 +#define ixTHM_TMON1_RDIL10_DATA 0xc03001a8 +#define ixTHM_TMON1_RDIL11_DATA 0xc03001ac +#define ixTHM_TMON1_RDIL12_DATA 0xc03001b0 +#define ixTHM_TMON1_RDIL13_DATA 0xc03001b4 +#define ixTHM_TMON1_RDIL14_DATA 0xc03001b8 +#define ixTHM_TMON1_RDIL15_DATA 0xc03001bc +#define ixTHM_TMON1_RDIR0_DATA 0xc03001c0 +#define ixTHM_TMON1_RDIR1_DATA 0xc03001c4 +#define ixTHM_TMON1_RDIR2_DATA 0xc03001c8 +#define ixTHM_TMON1_RDIR3_DATA 0xc03001cc +#define ixTHM_TMON1_RDIR4_DATA 0xc03001d0 +#define ixTHM_TMON1_RDIR5_DATA 0xc03001d4 +#define ixTHM_TMON1_RDIR6_DATA 0xc03001d8 +#define ixTHM_TMON1_RDIR7_DATA 0xc03001dc +#define ixTHM_TMON1_RDIR8_DATA 0xc03001e0 +#define ixTHM_TMON1_RDIR9_DATA 0xc03001e4 +#define ixTHM_TMON1_RDIR10_DATA 0xc03001e8 +#define ixTHM_TMON1_RDIR11_DATA 0xc03001ec +#define ixTHM_TMON1_RDIR12_DATA 0xc03001f0 +#define ixTHM_TMON1_RDIR13_DATA 0xc03001f4 +#define ixTHM_TMON1_RDIR14_DATA 0xc03001f8 +#define ixTHM_TMON1_RDIR15_DATA 0xc03001fc +#define ixTHM_TMON0_INT_DATA 0xc0300300 +#define ixTHM_TMON1_INT_DATA 0xc0300304 +#define ixTHM_TMON0_DEBUG 0xc0300310 +#define ixTHM_TMON1_DEBUG 0xc0300314 +#define ixTHM_TMON0_STATUS 0xc0300320 +#define ixTHM_TMON1_STATUS 0xc0300324 +#define ixGENERAL_PWRMGT 0xc0200000 +#define ixCNB_PWRMGT_CNTL 0xc0200004 +#define ixSCLK_PWRMGT_CNTL 0xc0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 +#define ixPWR_PCC_CONTROL 0xc0200018 +#define ixPWR_PCC_GPIO_SELECT 0xc020001c +#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 +#define ixPLL_TEST_CNTL 0xc020003c +#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 +#define ixCG_DISPLAY_GAP_CNTL 0xc0200060 +#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 +#define ixCG_ACPI_CNTL 0xc0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 +#define ixCG_ULV_PARAMETER 0xc020015c +#define ixSCLK_MIN_DIV 0xc02003ac +#define ixPWR_CKS_ENABLE 0xc020034c +#define ixPWR_CKS_CNTL 0xc0200350 +#define ixPWR_DISP_TIMER_CONTROL 0xc02003c0 +#define ixPWR_DISP_TIMER_DEBUG 0xc02003c4 +#define ixPWR_DISP_TIMER2_CONTROL 0xc02003c8 +#define ixPWR_DISP_TIMER2_DEBUG 0xc02003cc +#define ixPWR_DISP_TIMER_CONTROL2 0xc0200378 +#define ixVDDGFX_IDLE_PARAMETER 0xc020036c +#define ixVDDGFX_IDLE_CONTROL 0xc0200370 +#define ixVDDGFX_IDLE_EXIT 0xc0200374 +#define ixLCAC_MC0_CNTL 0xc0400130 +#define ixLCAC_MC0_OVR_SEL 0xc0400134 +#define ixLCAC_MC0_OVR_VAL 0xc0400138 +#define ixLCAC_MC1_CNTL 0xc040013c +#define ixLCAC_MC1_OVR_SEL 0xc0400140 +#define ixLCAC_MC1_OVR_VAL 0xc0400144 +#define ixLCAC_MC2_CNTL 0xc0400148 +#define ixLCAC_MC2_OVR_SEL 0xc040014c +#define ixLCAC_MC2_OVR_VAL 0xc0400150 +#define ixLCAC_MC3_CNTL 0xc0400154 +#define ixLCAC_MC3_OVR_SEL 0xc0400158 +#define ixLCAC_MC3_OVR_VAL 0xc040015c +#define ixLCAC_CPL_CNTL 0xc0400160 +#define ixLCAC_CPL_OVR_SEL 0xc0400164 +#define ixLCAC_CPL_OVR_VAL 0xc0400168 +#define mmROM_SMC_IND_INDEX 0x80 +#define mmROM0_ROM_SMC_IND_INDEX 0x80 +#define mmROM1_ROM_SMC_IND_INDEX 0x82 +#define mmROM2_ROM_SMC_IND_INDEX 0x84 +#define mmROM3_ROM_SMC_IND_INDEX 0x86 +#define mmROM_SMC_IND_DATA 0x81 +#define mmROM0_ROM_SMC_IND_DATA 0x81 +#define mmROM1_ROM_SMC_IND_DATA 0x83 +#define mmROM2_ROM_SMC_IND_DATA 0x85 +#define mmROM3_ROM_SMC_IND_DATA 0x87 +#define ixROM_CNTL 0xc0600000 +#define ixPAGE_MIRROR_CNTL 0xc0600004 +#define ixROM_STATUS 0xc0600008 +#define ixCGTT_ROM_CLK_CTRL0 0xc060000c +#define ixROM_INDEX 0xc0600010 +#define ixROM_DATA 0xc0600014 +#define ixROM_START 0xc0600018 +#define ixROM_SW_CNTL 0xc060001c +#define ixROM_SW_STATUS 0xc0600020 +#define ixROM_SW_COMMAND 0xc0600024 +#define ixROM_SW_DATA_1 0xc0600028 +#define ixROM_SW_DATA_2 0xc060002c +#define ixROM_SW_DATA_3 0xc0600030 +#define ixROM_SW_DATA_4 0xc0600034 +#define ixROM_SW_DATA_5 0xc0600038 +#define ixROM_SW_DATA_6 0xc060003c +#define ixROM_SW_DATA_7 0xc0600040 +#define ixROM_SW_DATA_8 0xc0600044 +#define ixROM_SW_DATA_9 0xc0600048 +#define ixROM_SW_DATA_10 0xc060004c +#define ixROM_SW_DATA_11 0xc0600050 +#define ixROM_SW_DATA_12 0xc0600054 +#define ixROM_SW_DATA_13 0xc0600058 +#define ixROM_SW_DATA_14 0xc060005c +#define ixROM_SW_DATA_15 0xc0600060 +#define ixROM_SW_DATA_16 0xc0600064 +#define ixROM_SW_DATA_17 0xc0600068 +#define ixROM_SW_DATA_18 0xc060006c +#define ixROM_SW_DATA_19 0xc0600070 +#define ixROM_SW_DATA_20 0xc0600074 +#define ixROM_SW_DATA_21 0xc0600078 +#define ixROM_SW_DATA_22 0xc060007c +#define ixROM_SW_DATA_23 0xc0600080 +#define ixROM_SW_DATA_24 0xc0600084 +#define ixROM_SW_DATA_25 0xc0600088 +#define ixROM_SW_DATA_26 0xc060008c +#define ixROM_SW_DATA_27 0xc0600090 +#define ixROM_SW_DATA_28 0xc0600094 +#define ixROM_SW_DATA_29 0xc0600098 +#define ixROM_SW_DATA_30 0xc060009c +#define ixROM_SW_DATA_31 0xc06000a0 +#define ixROM_SW_DATA_32 0xc06000a4 +#define ixROM_SW_DATA_33 0xc06000a8 +#define ixROM_SW_DATA_34 0xc06000ac +#define ixROM_SW_DATA_35 0xc06000b0 +#define ixROM_SW_DATA_36 0xc06000b4 +#define ixROM_SW_DATA_37 0xc06000b8 +#define ixROM_SW_DATA_38 0xc06000bc +#define ixROM_SW_DATA_39 0xc06000c0 +#define ixROM_SW_DATA_40 0xc06000c4 +#define ixROM_SW_DATA_41 0xc06000c8 +#define ixROM_SW_DATA_42 0xc06000cc +#define ixROM_SW_DATA_43 0xc06000d0 +#define ixROM_SW_DATA_44 0xc06000d4 +#define ixROM_SW_DATA_45 0xc06000d8 +#define ixROM_SW_DATA_46 0xc06000dc +#define ixROM_SW_DATA_47 0xc06000e0 +#define ixROM_SW_DATA_48 0xc06000e4 +#define ixROM_SW_DATA_49 0xc06000e8 +#define ixROM_SW_DATA_50 0xc06000ec +#define ixROM_SW_DATA_51 0xc06000f0 +#define ixROM_SW_DATA_52 0xc06000f4 +#define ixROM_SW_DATA_53 0xc06000f8 +#define ixROM_SW_DATA_54 0xc06000fc +#define ixROM_SW_DATA_55 0xc0600100 +#define ixROM_SW_DATA_56 0xc0600104 +#define ixROM_SW_DATA_57 0xc0600108 +#define ixROM_SW_DATA_58 0xc060010c +#define ixROM_SW_DATA_59 0xc0600110 +#define ixROM_SW_DATA_60 0xc0600114 +#define ixROM_SW_DATA_61 0xc0600118 +#define ixROM_SW_DATA_62 0xc060011c +#define ixROM_SW_DATA_63 0xc0600120 +#define ixROM_SW_DATA_64 0xc0600124 + +#endif /* SMU_7_1_2_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h new file mode 100644 index 000000000000..73bbf506b1c9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h @@ -0,0 +1,1246 @@ +/* + * SMU_7_1_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_2_ENUM_H +#define SMU_7_1_2_ENUM_H + +#define CG_SRBM_START_ADDR 0x600 +#define CG_SRBM_END_ADDR 0x8ff +#define RCU_CCF_DWORDS0 0xa0 +#define RCU_CCF_BITS0 0x1400 +#define RCU_CCF_DWORDS1 0x0 +#define RCU_CCF_BITS1 0x0 +#define RCU_SAM_BYTES 0x2c +#define RCU_SAM_RTL_BYTES 0x2c +#define RCU_SMU_BYTES 0x14 +#define RCU_SMU_RTL_BYTES 0x14 +#define SFP_CHAIN_ADDR 0x0 +#define SFP_BYTES 0x140 +#define SFP_SADR 0xc0 +#define SFP_EADR 0x1ff +#define SAMU_KEY_CHAIN_ADR 0x0 +#define SAMU_KEY_SADR 0x2a0 +#define SAMU_KEY_EADR 0x2cb +#define SMU_KEY_CHAIN_ADR 0x0 +#define SMU_KEY_SADR 0x2cc +#define SMU_KEY_EADR 0x2df +#define SMC_MSG_TEST 0x1 +#define SMC_MSG_PHY_LN_OFF 0x2 +#define SMC_MSG_PHY_LN_ON 0x3 +#define SMC_MSG_DDI_PHY_OFF 0x4 +#define SMC_MSG_DDI_PHY_ON 0x5 +#define SMC_MSG_CASCADE_PLL_OFF 0x6 +#define SMC_MSG_CASCADE_PLL_ON 0x7 +#define SMC_MSG_PWR_OFF_x16 0x8 +#define SMC_MSG_CONFIG_LCLK_DPM 0x9 +#define SMC_MSG_FLUSH_DATA_CACHE 0xa +#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb +#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc +#define SMC_MSG_CONFIG_BAPM 0xd +#define SMC_MSG_CONFIG_TDC_LIMIT 0xe +#define SMC_MSG_CONFIG_LPMx 0xf +#define SMC_MSG_CONFIG_HTC_LIMIT 0x10 +#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11 +#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12 +#define SMC_MSG_CONFIG_TDP_CNTL 0x13 +#define SMC_MSG_EN_PM_CNTL 0x14 +#define SMC_MSG_DIS_PM_CNTL 0x15 +#define SMC_MSG_CONFIG_NBDPM 0x16 +#define SMC_MSG_CONFIG_LOADLINE 0x17 +#define SMC_MSG_ADJUST_LOADLINE 0x18 +#define SMC_MSG_RESET 0x20 +#define SMC_MSG_VOLTAGE 0x25 +#define SMC_VERSION_MAJOR 0x7 +#define SMC_VERSION_MINOR 0x0 +#define SMC_HEADER_SIZE 0x40 +#define ROM_SIGNATURE 0xaa55 +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_scf2 = 0x2, + DBG_CLIENT_BLKID_mcd5 = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_sx30 = 0x5, + DBG_CLIENT_BLKID_mcd2 = 0x6, + DBG_CLIENT_BLKID_bci1 = 0x7, + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, + DBG_CLIENT_BLKID_mcc0 = 0x9, + DBG_CLIENT_BLKID_uvdf_0 = 0xa, + DBG_CLIENT_BLKID_uvdf_1 = 0xb, + DBG_CLIENT_BLKID_bci0 = 0xc, + DBG_CLIENT_BLKID_vcec0_0 = 0xd, + DBG_CLIENT_BLKID_cb100 = 0xe, + DBG_CLIENT_BLKID_cb001 = 0xf, + DBG_CLIENT_BLKID_mcd4 = 0x10, + DBG_CLIENT_BLKID_tmonw00 = 0x11, + DBG_CLIENT_BLKID_cb101 = 0x12, + DBG_CLIENT_BLKID_sx10 = 0x13, + DBG_CLIENT_BLKID_cb301 = 0x14, + DBG_CLIENT_BLKID_tmonw01 = 0x15, + DBG_CLIENT_BLKID_vcea0_0 = 0x16, + DBG_CLIENT_BLKID_vcea0_1 = 0x17, + DBG_CLIENT_BLKID_vcea0_2 = 0x18, + DBG_CLIENT_BLKID_vcea0_3 = 0x19, + DBG_CLIENT_BLKID_scf1 = 0x1a, + DBG_CLIENT_BLKID_sx20 = 0x1b, + DBG_CLIENT_BLKID_spim1 = 0x1c, + DBG_CLIENT_BLKID_pa10 = 0x1d, + DBG_CLIENT_BLKID_pa00 = 0x1e, + DBG_CLIENT_BLKID_gmcon = 0x1f, + DBG_CLIENT_BLKID_mcb = 0x20, + DBG_CLIENT_BLKID_vgt0 = 0x21, + DBG_CLIENT_BLKID_pc0 = 0x22, + DBG_CLIENT_BLKID_bci2 = 0x23, + DBG_CLIENT_BLKID_uvdb_0 = 0x24, + DBG_CLIENT_BLKID_spim3 = 0x25, + DBG_CLIENT_BLKID_cpc_0 = 0x26, + DBG_CLIENT_BLKID_cpc_1 = 0x27, + DBG_CLIENT_BLKID_uvdm_0 = 0x28, + DBG_CLIENT_BLKID_uvdm_1 = 0x29, + DBG_CLIENT_BLKID_uvdm_2 = 0x2a, + DBG_CLIENT_BLKID_uvdm_3 = 0x2b, + DBG_CLIENT_BLKID_cb000 = 0x2c, + DBG_CLIENT_BLKID_spim0 = 0x2d, + DBG_CLIENT_BLKID_mcc2 = 0x2e, + DBG_CLIENT_BLKID_ds0 = 0x2f, + DBG_CLIENT_BLKID_srbm = 0x30, + DBG_CLIENT_BLKID_ih = 0x31, + DBG_CLIENT_BLKID_sem = 0x32, + DBG_CLIENT_BLKID_sdma_0 = 0x33, + DBG_CLIENT_BLKID_sdma_1 = 0x34, + DBG_CLIENT_BLKID_hdp = 0x35, + DBG_CLIENT_BLKID_acp_0 = 0x36, + DBG_CLIENT_BLKID_acp_1 = 0x37, + DBG_CLIENT_BLKID_cb200 = 0x38, + DBG_CLIENT_BLKID_scf3 = 0x39, + DBG_CLIENT_BLKID_vceb1_0 = 0x3a, + DBG_CLIENT_BLKID_vcea1_0 = 0x3b, + DBG_CLIENT_BLKID_vcea1_1 = 0x3c, + DBG_CLIENT_BLKID_vcea1_2 = 0x3d, + DBG_CLIENT_BLKID_vcea1_3 = 0x3e, + DBG_CLIENT_BLKID_bci3 = 0x3f, + DBG_CLIENT_BLKID_mcd0 = 0x40, + DBG_CLIENT_BLKID_pa11 = 0x41, + DBG_CLIENT_BLKID_pa01 = 0x42, + DBG_CLIENT_BLKID_cb201 = 0x43, + DBG_CLIENT_BLKID_spim2 = 0x44, + DBG_CLIENT_BLKID_vgt2 = 0x45, + DBG_CLIENT_BLKID_pc2 = 0x46, + DBG_CLIENT_BLKID_smu_0 = 0x47, + DBG_CLIENT_BLKID_smu_1 = 0x48, + DBG_CLIENT_BLKID_smu_2 = 0x49, + DBG_CLIENT_BLKID_cb1 = 0x4a, + DBG_CLIENT_BLKID_ia0 = 0x4b, + DBG_CLIENT_BLKID_wd = 0x4c, + DBG_CLIENT_BLKID_ia1 = 0x4d, + DBG_CLIENT_BLKID_vcec1_0 = 0x4e, + DBG_CLIENT_BLKID_scf0 = 0x4f, + DBG_CLIENT_BLKID_vgt1 = 0x50, + DBG_CLIENT_BLKID_pc1 = 0x51, + DBG_CLIENT_BLKID_cb0 = 0x52, + DBG_CLIENT_BLKID_gdc_one_0 = 0x53, + DBG_CLIENT_BLKID_gdc_one_1 = 0x54, + DBG_CLIENT_BLKID_gdc_one_2 = 0x55, + DBG_CLIENT_BLKID_gdc_one_3 = 0x56, + DBG_CLIENT_BLKID_gdc_one_4 = 0x57, + DBG_CLIENT_BLKID_gdc_one_5 = 0x58, + DBG_CLIENT_BLKID_gdc_one_6 = 0x59, + DBG_CLIENT_BLKID_gdc_one_7 = 0x5a, + DBG_CLIENT_BLKID_gdc_one_8 = 0x5b, + DBG_CLIENT_BLKID_gdc_one_9 = 0x5c, + DBG_CLIENT_BLKID_gdc_one_10 = 0x5d, + DBG_CLIENT_BLKID_gdc_one_11 = 0x5e, + DBG_CLIENT_BLKID_gdc_one_12 = 0x5f, + DBG_CLIENT_BLKID_gdc_one_13 = 0x60, + DBG_CLIENT_BLKID_gdc_one_14 = 0x61, + DBG_CLIENT_BLKID_gdc_one_15 = 0x62, + DBG_CLIENT_BLKID_gdc_one_16 = 0x63, + DBG_CLIENT_BLKID_gdc_one_17 = 0x64, + DBG_CLIENT_BLKID_gdc_one_18 = 0x65, + DBG_CLIENT_BLKID_gdc_one_19 = 0x66, + DBG_CLIENT_BLKID_gdc_one_20 = 0x67, + DBG_CLIENT_BLKID_gdc_one_21 = 0x68, + DBG_CLIENT_BLKID_gdc_one_22 = 0x69, + DBG_CLIENT_BLKID_gdc_one_23 = 0x6a, + DBG_CLIENT_BLKID_gdc_one_24 = 0x6b, + DBG_CLIENT_BLKID_gdc_one_25 = 0x6c, + DBG_CLIENT_BLKID_gdc_one_26 = 0x6d, + DBG_CLIENT_BLKID_gdc_one_27 = 0x6e, + DBG_CLIENT_BLKID_gdc_one_28 = 0x6f, + DBG_CLIENT_BLKID_gdc_one_29 = 0x70, + DBG_CLIENT_BLKID_gdc_one_30 = 0x71, + DBG_CLIENT_BLKID_gdc_one_31 = 0x72, + DBG_CLIENT_BLKID_gdc_one_32 = 0x73, + DBG_CLIENT_BLKID_gdc_one_33 = 0x74, + DBG_CLIENT_BLKID_gdc_one_34 = 0x75, + DBG_CLIENT_BLKID_gdc_one_35 = 0x76, + DBG_CLIENT_BLKID_vceb0_0 = 0x77, + DBG_CLIENT_BLKID_vgt3 = 0x78, + DBG_CLIENT_BLKID_pc3 = 0x79, + DBG_CLIENT_BLKID_mcd3 = 0x7a, + DBG_CLIENT_BLKID_uvdu_0 = 0x7b, + DBG_CLIENT_BLKID_uvdu_1 = 0x7c, + DBG_CLIENT_BLKID_uvdu_2 = 0x7d, + DBG_CLIENT_BLKID_uvdu_3 = 0x7e, + DBG_CLIENT_BLKID_uvdu_4 = 0x7f, + DBG_CLIENT_BLKID_uvdu_5 = 0x80, + DBG_CLIENT_BLKID_uvdu_6 = 0x81, + DBG_CLIENT_BLKID_cb300 = 0x82, + DBG_CLIENT_BLKID_mcd1 = 0x83, + DBG_CLIENT_BLKID_sx00 = 0x84, + DBG_CLIENT_BLKID_uvdc_0 = 0x85, + DBG_CLIENT_BLKID_uvdc_1 = 0x86, + DBG_CLIENT_BLKID_mcc3 = 0x87, + DBG_CLIENT_BLKID_cpg_0 = 0x88, + DBG_CLIENT_BLKID_cpg_1 = 0x89, + DBG_CLIENT_BLKID_gck = 0x8a, + DBG_CLIENT_BLKID_mcc1 = 0x8b, + DBG_CLIENT_BLKID_cpf_0 = 0x8c, + DBG_CLIENT_BLKID_cpf_1 = 0x8d, + DBG_CLIENT_BLKID_rlc = 0x8e, + DBG_CLIENT_BLKID_grbm = 0x8f, + DBG_CLIENT_BLKID_sammsp = 0x90, + DBG_CLIENT_BLKID_dci_pg = 0x91, + DBG_CLIENT_BLKID_dci_0 = 0x92, + DBG_CLIENT_BLKID_dccg0_0 = 0x93, + DBG_CLIENT_BLKID_dccg0_1 = 0x94, + DBG_CLIENT_BLKID_dcfe01_0 = 0x95, + DBG_CLIENT_BLKID_dcfe02_0 = 0x96, + DBG_CLIENT_BLKID_dcfe03_0 = 0x97, + DBG_CLIENT_BLKID_dcfe04_0 = 0x98, + DBG_CLIENT_BLKID_dcfe05_0 = 0x99, + DBG_CLIENT_BLKID_dcfe06_0 = 0x9a, + DBG_CLIENT_BLKID_RESERVED_LAST = 0x9b, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* SMU_7_1_2_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h new file mode 100644 index 000000000000..518fd02e9d35 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h @@ -0,0 +1,5834 @@ +/* + * SMU_7_1_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_2_SH_MASK_H +#define SMU_7_1_2_SH_MASK_H + +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f +#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 +#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f +#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 +#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f +#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 +#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f +#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d +#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 +#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 +#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 +#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 +#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 +#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 +#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1 +#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa +#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff +#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 +#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 +#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 +#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 +#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa +#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 +#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_0__SMC_RESP_MASK 0xffff +#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_1__SMC_RESP_MASK 0xffff +#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_2__SMC_RESP_MASK 0xffff +#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_3__SMC_RESP_MASK 0xffff +#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_4__SMC_RESP_MASK 0xffff +#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_5__SMC_RESP_MASK 0xffff +#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_6__SMC_RESP_MASK 0xffff +#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_7__SMC_RESP_MASK 0xffff +#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_8__SMC_RESP_MASK 0xffff +#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_9__SMC_RESP_MASK 0xffff +#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_10__SMC_RESP_MASK 0xffff +#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_11__SMC_RESP_MASK 0xffff +#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 +#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 +#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 +#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 +#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 +#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 +#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding_MASK 0x2 +#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding__SHIFT 0x1 +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffff +#define SMC_PC_C__smc_pc_c__SHIFT 0x0 +#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff +#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4 +#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff +#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 +#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff +#define GPIOPAD_A__GPIO_A__SHIFT 0x0 +#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff +#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0 +#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff +#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f +#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff +#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000 +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f +#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6 +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0 +#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff +#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 +#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff +#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 +#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff +#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 +#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 +#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3 +#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 +#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 +#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 +#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa +#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 +#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 +#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 +#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 +#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 +#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 +#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 +#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 +#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 +#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 +#define RCU_VIRT_RESET_REQ__VF_MASK 0xffff +#define RCU_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define RCU_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define RCU_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 +#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 +#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 +#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 +#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 +#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 +#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 +#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 +#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 +#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 +#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 +#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 +#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 +#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000 +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000 +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10 +#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000 +#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13 +#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000 +#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16 +#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000 +#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17 +#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000 +#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18 +#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000 +#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19 +#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000 +#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 +#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc +#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 +#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 +#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 +#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 +#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c +#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 +#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d +#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff +#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 +#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 +#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 +#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 +#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 +#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 +#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 +#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e +#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 +#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a +#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 +#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 +#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6 +#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1 +#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10 +#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4 +#define CC_HARVEST_FUSES__ACP_DISABLE_MASK 0x40 +#define CC_HARVEST_FUSES__ACP_DISABLE__SHIFT 0x6 +#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00 +#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8 +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 +#define SMU_STATUS__SMU_DONE_MASK 0x1 +#define SMU_STATUS__SMU_DONE__SHIFT 0x0 +#define SMU_STATUS__SMU_PASS_MASK 0x2 +#define SMU_STATUS__SMU_PASS__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 +#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 +#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 +#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 +#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 +#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 +#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 +#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 +#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 +#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff +#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 +#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 +#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f +#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff +#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe +#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 +#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 +#define TDC_STATUS__VDD_Boost_MASK 0xff +#define TDC_STATUS__VDD_Boost__SHIFT 0x0 +#define TDC_STATUS__VDD_Throttle_MASK 0xff00 +#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 +#define TDC_STATUS__VDDC_Boost_MASK 0xff0000 +#define TDC_STATUS__VDDC_Boost__SHIFT 0x10 +#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000 +#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18 +#define TDC_MV_AVERAGE__IDD_MASK 0xffff +#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 +#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000 +#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10 +#define TDC_VRM_LIMIT__IDD_MASK 0xffff +#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 +#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000 +#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10 +#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 +#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 +#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 +#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 +#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 +#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 +#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 +#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 +#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 +#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 +#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20 +#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5 +#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40 +#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6 +#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 +#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 +#define FEATURE_STATUS__BAPM_ON_MASK 0x100 +#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 +#define FEATURE_STATUS__LPMX_ON_MASK 0x200 +#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 +#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 +#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa +#define FEATURE_STATUS__LHTC_ON_MASK 0x800 +#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb +#define FEATURE_STATUS__VPC_ON_MASK 0x1000 +#define FEATURE_STATUS__VPC_ON__SHIFT 0xc +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd +#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 +#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe +#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 +#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf +#define FEATURE_STATUS__AVS_ON_MASK 0x10000 +#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 +#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 +#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 +#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 +#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 +#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 +#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 +#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 +#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 +#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 +#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 +#define FEATURE_STATUS__RESERVED_MASK 0xffc00000 +#define FEATURE_STATUS__RESERVED__SHIFT 0x16 +#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff +#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0 +#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff +#define DPM_TABLE_28__SystemFlags__SHIFT 0x0 +#define DPM_TABLE_29__VRConfig_MASK 0xffffffff +#define DPM_TABLE_29__VRConfig__SHIFT 0x0 +#define DPM_TABLE_30__SmioMask1_MASK 0xffffffff +#define DPM_TABLE_30__SmioMask1__SHIFT 0x0 +#define DPM_TABLE_31__SmioMask2_MASK 0xffffffff +#define DPM_TABLE_31__SmioMask2__SHIFT 0x0 +#define DPM_TABLE_32__SmioTable1_Pattern_0_padding_MASK 0xff +#define DPM_TABLE_32__SmioTable1_Pattern_0_padding__SHIFT 0x0 +#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio_MASK 0xff00 +#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio__SHIFT 0x8 +#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_33__SmioTable1_Pattern_1_padding_MASK 0xff +#define DPM_TABLE_33__SmioTable1_Pattern_1_padding__SHIFT 0x0 +#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio_MASK 0xff00 +#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio__SHIFT 0x8 +#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_34__SmioTable1_Pattern_2_padding_MASK 0xff +#define DPM_TABLE_34__SmioTable1_Pattern_2_padding__SHIFT 0x0 +#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio_MASK 0xff00 +#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio__SHIFT 0x8 +#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_35__SmioTable1_Pattern_3_padding_MASK 0xff +#define DPM_TABLE_35__SmioTable1_Pattern_3_padding__SHIFT 0x0 +#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio_MASK 0xff00 +#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio__SHIFT 0x8 +#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_36__SmioTable2_Pattern_0_padding_MASK 0xff +#define DPM_TABLE_36__SmioTable2_Pattern_0_padding__SHIFT 0x0 +#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio_MASK 0xff00 +#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio__SHIFT 0x8 +#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_37__SmioTable2_Pattern_1_padding_MASK 0xff +#define DPM_TABLE_37__SmioTable2_Pattern_1_padding__SHIFT 0x0 +#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio_MASK 0xff00 +#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio__SHIFT 0x8 +#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_38__SmioTable2_Pattern_2_padding_MASK 0xff +#define DPM_TABLE_38__SmioTable2_Pattern_2_padding__SHIFT 0x0 +#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio_MASK 0xff00 +#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio__SHIFT 0x8 +#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_39__SmioTable2_Pattern_3_padding_MASK 0xff +#define DPM_TABLE_39__SmioTable2_Pattern_3_padding__SHIFT 0x0 +#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio_MASK 0xff00 +#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio__SHIFT 0x8 +#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_40__VddcLevelCount_MASK 0xffffffff +#define DPM_TABLE_40__VddcLevelCount__SHIFT 0x0 +#define DPM_TABLE_41__VddciLevelCount_MASK 0xffffffff +#define DPM_TABLE_41__VddciLevelCount__SHIFT 0x0 +#define DPM_TABLE_42__VddGfxLevelCount_MASK 0xffffffff +#define DPM_TABLE_42__VddGfxLevelCount__SHIFT 0x0 +#define DPM_TABLE_43__MvddLevelCount_MASK 0xffffffff +#define DPM_TABLE_43__MvddLevelCount__SHIFT 0x0 +#define DPM_TABLE_44__VddcTable_1_MASK 0xffff +#define DPM_TABLE_44__VddcTable_1__SHIFT 0x0 +#define DPM_TABLE_44__VddcTable_0_MASK 0xffff0000 +#define DPM_TABLE_44__VddcTable_0__SHIFT 0x10 +#define DPM_TABLE_45__VddcTable_3_MASK 0xffff +#define DPM_TABLE_45__VddcTable_3__SHIFT 0x0 +#define DPM_TABLE_45__VddcTable_2_MASK 0xffff0000 +#define DPM_TABLE_45__VddcTable_2__SHIFT 0x10 +#define DPM_TABLE_46__VddcTable_5_MASK 0xffff +#define DPM_TABLE_46__VddcTable_5__SHIFT 0x0 +#define DPM_TABLE_46__VddcTable_4_MASK 0xffff0000 +#define DPM_TABLE_46__VddcTable_4__SHIFT 0x10 +#define DPM_TABLE_47__VddcTable_7_MASK 0xffff +#define DPM_TABLE_47__VddcTable_7__SHIFT 0x0 +#define DPM_TABLE_47__VddcTable_6_MASK 0xffff0000 +#define DPM_TABLE_47__VddcTable_6__SHIFT 0x10 +#define DPM_TABLE_48__VddcTable_9_MASK 0xffff +#define DPM_TABLE_48__VddcTable_9__SHIFT 0x0 +#define DPM_TABLE_48__VddcTable_8_MASK 0xffff0000 +#define DPM_TABLE_48__VddcTable_8__SHIFT 0x10 +#define DPM_TABLE_49__VddcTable_11_MASK 0xffff +#define DPM_TABLE_49__VddcTable_11__SHIFT 0x0 +#define DPM_TABLE_49__VddcTable_10_MASK 0xffff0000 +#define DPM_TABLE_49__VddcTable_10__SHIFT 0x10 +#define DPM_TABLE_50__VddcTable_13_MASK 0xffff +#define DPM_TABLE_50__VddcTable_13__SHIFT 0x0 +#define DPM_TABLE_50__VddcTable_12_MASK 0xffff0000 +#define DPM_TABLE_50__VddcTable_12__SHIFT 0x10 +#define DPM_TABLE_51__VddcTable_15_MASK 0xffff +#define DPM_TABLE_51__VddcTable_15__SHIFT 0x0 +#define DPM_TABLE_51__VddcTable_14_MASK 0xffff0000 +#define DPM_TABLE_51__VddcTable_14__SHIFT 0x10 +#define DPM_TABLE_52__VddGfxTable_1_MASK 0xffff +#define DPM_TABLE_52__VddGfxTable_1__SHIFT 0x0 +#define DPM_TABLE_52__VddGfxTable_0_MASK 0xffff0000 +#define DPM_TABLE_52__VddGfxTable_0__SHIFT 0x10 +#define DPM_TABLE_53__VddGfxTable_3_MASK 0xffff +#define DPM_TABLE_53__VddGfxTable_3__SHIFT 0x0 +#define DPM_TABLE_53__VddGfxTable_2_MASK 0xffff0000 +#define DPM_TABLE_53__VddGfxTable_2__SHIFT 0x10 +#define DPM_TABLE_54__VddGfxTable_5_MASK 0xffff +#define DPM_TABLE_54__VddGfxTable_5__SHIFT 0x0 +#define DPM_TABLE_54__VddGfxTable_4_MASK 0xffff0000 +#define DPM_TABLE_54__VddGfxTable_4__SHIFT 0x10 +#define DPM_TABLE_55__VddGfxTable_7_MASK 0xffff +#define DPM_TABLE_55__VddGfxTable_7__SHIFT 0x0 +#define DPM_TABLE_55__VddGfxTable_6_MASK 0xffff0000 +#define DPM_TABLE_55__VddGfxTable_6__SHIFT 0x10 +#define DPM_TABLE_56__VddGfxTable_9_MASK 0xffff +#define DPM_TABLE_56__VddGfxTable_9__SHIFT 0x0 +#define DPM_TABLE_56__VddGfxTable_8_MASK 0xffff0000 +#define DPM_TABLE_56__VddGfxTable_8__SHIFT 0x10 +#define DPM_TABLE_57__VddGfxTable_11_MASK 0xffff +#define DPM_TABLE_57__VddGfxTable_11__SHIFT 0x0 +#define DPM_TABLE_57__VddGfxTable_10_MASK 0xffff0000 +#define DPM_TABLE_57__VddGfxTable_10__SHIFT 0x10 +#define DPM_TABLE_58__VddGfxTable_13_MASK 0xffff +#define DPM_TABLE_58__VddGfxTable_13__SHIFT 0x0 +#define DPM_TABLE_58__VddGfxTable_12_MASK 0xffff0000 +#define DPM_TABLE_58__VddGfxTable_12__SHIFT 0x10 +#define DPM_TABLE_59__VddGfxTable_15_MASK 0xffff +#define DPM_TABLE_59__VddGfxTable_15__SHIFT 0x0 +#define DPM_TABLE_59__VddGfxTable_14_MASK 0xffff0000 +#define DPM_TABLE_59__VddGfxTable_14__SHIFT 0x10 +#define DPM_TABLE_60__VddciTable_1_MASK 0xffff +#define DPM_TABLE_60__VddciTable_1__SHIFT 0x0 +#define DPM_TABLE_60__VddciTable_0_MASK 0xffff0000 +#define DPM_TABLE_60__VddciTable_0__SHIFT 0x10 +#define DPM_TABLE_61__VddciTable_3_MASK 0xffff +#define DPM_TABLE_61__VddciTable_3__SHIFT 0x0 +#define DPM_TABLE_61__VddciTable_2_MASK 0xffff0000 +#define DPM_TABLE_61__VddciTable_2__SHIFT 0x10 +#define DPM_TABLE_62__VddciTable_5_MASK 0xffff +#define DPM_TABLE_62__VddciTable_5__SHIFT 0x0 +#define DPM_TABLE_62__VddciTable_4_MASK 0xffff0000 +#define DPM_TABLE_62__VddciTable_4__SHIFT 0x10 +#define DPM_TABLE_63__VddciTable_7_MASK 0xffff +#define DPM_TABLE_63__VddciTable_7__SHIFT 0x0 +#define DPM_TABLE_63__VddciTable_6_MASK 0xffff0000 +#define DPM_TABLE_63__VddciTable_6__SHIFT 0x10 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3_MASK 0xff +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3__SHIFT 0x0 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2_MASK 0xff00 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2__SHIFT 0x8 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1_MASK 0xff0000 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1__SHIFT 0x10 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0_MASK 0xff000000 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0__SHIFT 0x18 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7_MASK 0xff +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7__SHIFT 0x0 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6_MASK 0xff00 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6__SHIFT 0x8 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5_MASK 0xff0000 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5__SHIFT 0x10 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4_MASK 0xff000000 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4__SHIFT 0x18 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11_MASK 0xff +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11__SHIFT 0x0 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10_MASK 0xff00 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10__SHIFT 0x8 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9_MASK 0xff0000 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9__SHIFT 0x10 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8_MASK 0xff000000 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8__SHIFT 0x18 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15_MASK 0xff +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15__SHIFT 0x0 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14_MASK 0xff00 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14__SHIFT 0x8 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13_MASK 0xff0000 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13__SHIFT 0x10 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12_MASK 0xff000000 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12__SHIFT 0x18 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3_MASK 0xff +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3__SHIFT 0x0 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2_MASK 0xff00 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2__SHIFT 0x8 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1_MASK 0xff0000 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1__SHIFT 0x10 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0_MASK 0xff000000 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0__SHIFT 0x18 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7_MASK 0xff +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7__SHIFT 0x0 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6_MASK 0xff00 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6__SHIFT 0x8 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5_MASK 0xff0000 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5__SHIFT 0x10 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4_MASK 0xff000000 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4__SHIFT 0x18 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11_MASK 0xff +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11__SHIFT 0x0 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10_MASK 0xff00 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10__SHIFT 0x8 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9_MASK 0xff0000 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9__SHIFT 0x10 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8_MASK 0xff000000 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8__SHIFT 0x18 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15_MASK 0xff +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15__SHIFT 0x0 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14_MASK 0xff00 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14__SHIFT 0x8 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13_MASK 0xff0000 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13__SHIFT 0x10 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12_MASK 0xff000000 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12__SHIFT 0x18 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3_MASK 0xff +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3__SHIFT 0x0 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2_MASK 0xff00 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2__SHIFT 0x8 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1_MASK 0xff0000 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1__SHIFT 0x10 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0_MASK 0xff000000 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0__SHIFT 0x18 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7_MASK 0xff +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7__SHIFT 0x0 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6_MASK 0xff00 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6__SHIFT 0x8 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5_MASK 0xff0000 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5__SHIFT 0x10 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4_MASK 0xff000000 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4__SHIFT 0x18 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11_MASK 0xff +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11__SHIFT 0x0 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10_MASK 0xff00 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10__SHIFT 0x8 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9_MASK 0xff0000 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9__SHIFT 0x10 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8_MASK 0xff000000 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8__SHIFT 0x18 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15_MASK 0xff +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15__SHIFT 0x0 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14_MASK 0xff00 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14__SHIFT 0x8 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13_MASK 0xff0000 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13__SHIFT 0x10 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12_MASK 0xff000000 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12__SHIFT 0x18 +#define DPM_TABLE_76__BapmVddcVidHiSidd_3_MASK 0xff +#define DPM_TABLE_76__BapmVddcVidHiSidd_3__SHIFT 0x0 +#define DPM_TABLE_76__BapmVddcVidHiSidd_2_MASK 0xff00 +#define DPM_TABLE_76__BapmVddcVidHiSidd_2__SHIFT 0x8 +#define DPM_TABLE_76__BapmVddcVidHiSidd_1_MASK 0xff0000 +#define DPM_TABLE_76__BapmVddcVidHiSidd_1__SHIFT 0x10 +#define DPM_TABLE_76__BapmVddcVidHiSidd_0_MASK 0xff000000 +#define DPM_TABLE_76__BapmVddcVidHiSidd_0__SHIFT 0x18 +#define DPM_TABLE_77__BapmVddcVidHiSidd_7_MASK 0xff +#define DPM_TABLE_77__BapmVddcVidHiSidd_7__SHIFT 0x0 +#define DPM_TABLE_77__BapmVddcVidHiSidd_6_MASK 0xff00 +#define DPM_TABLE_77__BapmVddcVidHiSidd_6__SHIFT 0x8 +#define DPM_TABLE_77__BapmVddcVidHiSidd_5_MASK 0xff0000 +#define DPM_TABLE_77__BapmVddcVidHiSidd_5__SHIFT 0x10 +#define DPM_TABLE_77__BapmVddcVidHiSidd_4_MASK 0xff000000 +#define DPM_TABLE_77__BapmVddcVidHiSidd_4__SHIFT 0x18 +#define DPM_TABLE_78__BapmVddcVidHiSidd_11_MASK 0xff +#define DPM_TABLE_78__BapmVddcVidHiSidd_11__SHIFT 0x0 +#define DPM_TABLE_78__BapmVddcVidHiSidd_10_MASK 0xff00 +#define DPM_TABLE_78__BapmVddcVidHiSidd_10__SHIFT 0x8 +#define DPM_TABLE_78__BapmVddcVidHiSidd_9_MASK 0xff0000 +#define DPM_TABLE_78__BapmVddcVidHiSidd_9__SHIFT 0x10 +#define DPM_TABLE_78__BapmVddcVidHiSidd_8_MASK 0xff000000 +#define DPM_TABLE_78__BapmVddcVidHiSidd_8__SHIFT 0x18 +#define DPM_TABLE_79__BapmVddcVidHiSidd_15_MASK 0xff +#define DPM_TABLE_79__BapmVddcVidHiSidd_15__SHIFT 0x0 +#define DPM_TABLE_79__BapmVddcVidHiSidd_14_MASK 0xff00 +#define DPM_TABLE_79__BapmVddcVidHiSidd_14__SHIFT 0x8 +#define DPM_TABLE_79__BapmVddcVidHiSidd_13_MASK 0xff0000 +#define DPM_TABLE_79__BapmVddcVidHiSidd_13__SHIFT 0x10 +#define DPM_TABLE_79__BapmVddcVidHiSidd_12_MASK 0xff000000 +#define DPM_TABLE_79__BapmVddcVidHiSidd_12__SHIFT 0x18 +#define DPM_TABLE_80__BapmVddcVidLoSidd_3_MASK 0xff +#define DPM_TABLE_80__BapmVddcVidLoSidd_3__SHIFT 0x0 +#define DPM_TABLE_80__BapmVddcVidLoSidd_2_MASK 0xff00 +#define DPM_TABLE_80__BapmVddcVidLoSidd_2__SHIFT 0x8 +#define DPM_TABLE_80__BapmVddcVidLoSidd_1_MASK 0xff0000 +#define DPM_TABLE_80__BapmVddcVidLoSidd_1__SHIFT 0x10 +#define DPM_TABLE_80__BapmVddcVidLoSidd_0_MASK 0xff000000 +#define DPM_TABLE_80__BapmVddcVidLoSidd_0__SHIFT 0x18 +#define DPM_TABLE_81__BapmVddcVidLoSidd_7_MASK 0xff +#define DPM_TABLE_81__BapmVddcVidLoSidd_7__SHIFT 0x0 +#define DPM_TABLE_81__BapmVddcVidLoSidd_6_MASK 0xff00 +#define DPM_TABLE_81__BapmVddcVidLoSidd_6__SHIFT 0x8 +#define DPM_TABLE_81__BapmVddcVidLoSidd_5_MASK 0xff0000 +#define DPM_TABLE_81__BapmVddcVidLoSidd_5__SHIFT 0x10 +#define DPM_TABLE_81__BapmVddcVidLoSidd_4_MASK 0xff000000 +#define DPM_TABLE_81__BapmVddcVidLoSidd_4__SHIFT 0x18 +#define DPM_TABLE_82__BapmVddcVidLoSidd_11_MASK 0xff +#define DPM_TABLE_82__BapmVddcVidLoSidd_11__SHIFT 0x0 +#define DPM_TABLE_82__BapmVddcVidLoSidd_10_MASK 0xff00 +#define DPM_TABLE_82__BapmVddcVidLoSidd_10__SHIFT 0x8 +#define DPM_TABLE_82__BapmVddcVidLoSidd_9_MASK 0xff0000 +#define DPM_TABLE_82__BapmVddcVidLoSidd_9__SHIFT 0x10 +#define DPM_TABLE_82__BapmVddcVidLoSidd_8_MASK 0xff000000 +#define DPM_TABLE_82__BapmVddcVidLoSidd_8__SHIFT 0x18 +#define DPM_TABLE_83__BapmVddcVidLoSidd_15_MASK 0xff +#define DPM_TABLE_83__BapmVddcVidLoSidd_15__SHIFT 0x0 +#define DPM_TABLE_83__BapmVddcVidLoSidd_14_MASK 0xff00 +#define DPM_TABLE_83__BapmVddcVidLoSidd_14__SHIFT 0x8 +#define DPM_TABLE_83__BapmVddcVidLoSidd_13_MASK 0xff0000 +#define DPM_TABLE_83__BapmVddcVidLoSidd_13__SHIFT 0x10 +#define DPM_TABLE_83__BapmVddcVidLoSidd_12_MASK 0xff000000 +#define DPM_TABLE_83__BapmVddcVidLoSidd_12__SHIFT 0x18 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_3_MASK 0xff +#define DPM_TABLE_84__BapmVddcVidHiSidd2_3__SHIFT 0x0 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_2_MASK 0xff00 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_2__SHIFT 0x8 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_1_MASK 0xff0000 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_1__SHIFT 0x10 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_0_MASK 0xff000000 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_0__SHIFT 0x18 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_7_MASK 0xff +#define DPM_TABLE_85__BapmVddcVidHiSidd2_7__SHIFT 0x0 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_6_MASK 0xff00 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_6__SHIFT 0x8 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_5_MASK 0xff0000 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_5__SHIFT 0x10 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_4_MASK 0xff000000 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_4__SHIFT 0x18 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_11_MASK 0xff +#define DPM_TABLE_86__BapmVddcVidHiSidd2_11__SHIFT 0x0 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_10_MASK 0xff00 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_10__SHIFT 0x8 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_9_MASK 0xff0000 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_9__SHIFT 0x10 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_8_MASK 0xff000000 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_8__SHIFT 0x18 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_15_MASK 0xff +#define DPM_TABLE_87__BapmVddcVidHiSidd2_15__SHIFT 0x0 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_14_MASK 0xff00 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_14__SHIFT 0x8 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_13_MASK 0xff0000 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_13__SHIFT 0x10 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_12_MASK 0xff000000 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_12__SHIFT 0x18 +#define DPM_TABLE_88__MasterDeepSleepControl_MASK 0xff +#define DPM_TABLE_88__MasterDeepSleepControl__SHIFT 0x0 +#define DPM_TABLE_88__LinkLevelCount_MASK 0xff00 +#define DPM_TABLE_88__LinkLevelCount__SHIFT 0x8 +#define DPM_TABLE_88__MemoryDpmLevelCount_MASK 0xff0000 +#define DPM_TABLE_88__MemoryDpmLevelCount__SHIFT 0x10 +#define DPM_TABLE_88__GraphicsDpmLevelCount_MASK 0xff000000 +#define DPM_TABLE_88__GraphicsDpmLevelCount__SHIFT 0x18 +#define DPM_TABLE_89__SamuLevelCount_MASK 0xff +#define DPM_TABLE_89__SamuLevelCount__SHIFT 0x0 +#define DPM_TABLE_89__AcpLevelCount_MASK 0xff00 +#define DPM_TABLE_89__AcpLevelCount__SHIFT 0x8 +#define DPM_TABLE_89__VceLevelCount_MASK 0xff0000 +#define DPM_TABLE_89__VceLevelCount__SHIFT 0x10 +#define DPM_TABLE_89__UvdLevelCount_MASK 0xff000000 +#define DPM_TABLE_89__UvdLevelCount__SHIFT 0x18 +#define DPM_TABLE_90__Reserved_0_MASK 0xffffffff +#define DPM_TABLE_90__Reserved_0__SHIFT 0x0 +#define DPM_TABLE_91__Reserved_1_MASK 0xffffffff +#define DPM_TABLE_91__Reserved_1__SHIFT 0x0 +#define DPM_TABLE_92__Reserved_2_MASK 0xffffffff +#define DPM_TABLE_92__Reserved_2__SHIFT 0x0 +#define DPM_TABLE_93__Reserved_3_MASK 0xffffffff +#define DPM_TABLE_93__Reserved_3__SHIFT 0x0 +#define DPM_TABLE_94__Reserved_4_MASK 0xffffffff +#define DPM_TABLE_94__Reserved_4__SHIFT 0x0 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel_MASK 0xffff +#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_104__GraphicsLevel_0_SclkDid_MASK 0xff000000 +#define DPM_TABLE_104__GraphicsLevel_0_SclkDid__SHIFT 0x18 +#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle_MASK 0xff +#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_105__GraphicsLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_105__GraphicsLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_105__GraphicsLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_105__GraphicsLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel_MASK 0xffff +#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_115__GraphicsLevel_1_SclkDid_MASK 0xff000000 +#define DPM_TABLE_115__GraphicsLevel_1_SclkDid__SHIFT 0x18 +#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle_MASK 0xff +#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_116__GraphicsLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_116__GraphicsLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_116__GraphicsLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_116__GraphicsLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel_MASK 0xffff +#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_126__GraphicsLevel_2_SclkDid_MASK 0xff000000 +#define DPM_TABLE_126__GraphicsLevel_2_SclkDid__SHIFT 0x18 +#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle_MASK 0xff +#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_127__GraphicsLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_127__GraphicsLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_127__GraphicsLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_127__GraphicsLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel_MASK 0xffff +#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_137__GraphicsLevel_3_SclkDid_MASK 0xff000000 +#define DPM_TABLE_137__GraphicsLevel_3_SclkDid__SHIFT 0x18 +#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle_MASK 0xff +#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_138__GraphicsLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_138__GraphicsLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_138__GraphicsLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_138__GraphicsLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel_MASK 0xffff +#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_148__GraphicsLevel_4_SclkDid_MASK 0xff000000 +#define DPM_TABLE_148__GraphicsLevel_4_SclkDid__SHIFT 0x18 +#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle_MASK 0xff +#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_149__GraphicsLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_149__GraphicsLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_149__GraphicsLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_149__GraphicsLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel_MASK 0xffff +#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_159__GraphicsLevel_5_SclkDid_MASK 0xff000000 +#define DPM_TABLE_159__GraphicsLevel_5_SclkDid__SHIFT 0x18 +#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle_MASK 0xff +#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_160__GraphicsLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_160__GraphicsLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_160__GraphicsLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_160__GraphicsLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18 +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel_MASK 0xffff +#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_181__GraphicsLevel_7_SclkDid_MASK 0xff000000 +#define DPM_TABLE_181__GraphicsLevel_7_SclkDid__SHIFT 0x18 +#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle_MASK 0xff +#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_182__GraphicsLevel_7_DownHyst_MASK 0xff0000 +#define DPM_TABLE_182__GraphicsLevel_7_DownHyst__SHIFT 0x10 +#define DPM_TABLE_182__GraphicsLevel_7_UpHyst_MASK 0xff000000 +#define DPM_TABLE_182__GraphicsLevel_7_UpHyst__SHIFT 0x18 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_184__MemoryACPILevel_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_184__MemoryACPILevel_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_186__MemoryACPILevel_StutterEnable_MASK 0xff +#define DPM_TABLE_186__MemoryACPILevel_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_186__MemoryACPILevel_RttEnable_MASK 0xff00 +#define DPM_TABLE_186__MemoryACPILevel_RttEnable__SHIFT 0x8 +#define DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_186__MemoryACPILevel_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_186__MemoryACPILevel_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_187__MemoryACPILevel_EnabledForActivity_MASK 0xff +#define DPM_TABLE_187__MemoryACPILevel_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_187__MemoryACPILevel_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_187__MemoryACPILevel_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_187__MemoryACPILevel_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_187__MemoryACPILevel_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_188__MemoryACPILevel_padding_MASK 0xff +#define DPM_TABLE_188__MemoryACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_188__MemoryACPILevel_DownHyst_MASK 0xff0000 +#define DPM_TABLE_188__MemoryACPILevel_DownHyst__SHIFT 0x10 +#define DPM_TABLE_188__MemoryACPILevel_UpHyst_MASK 0xff000000 +#define DPM_TABLE_188__MemoryACPILevel_UpHyst__SHIFT 0x18 +#define DPM_TABLE_189__MemoryACPILevel_padding1_MASK 0xff +#define DPM_TABLE_189__MemoryACPILevel_padding1__SHIFT 0x0 +#define DPM_TABLE_189__MemoryACPILevel_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_189__MemoryACPILevel_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_189__MemoryACPILevel_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_189__MemoryACPILevel_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_196__MemoryACPILevel_DllCntl_MASK 0xffffffff +#define DPM_TABLE_196__MemoryACPILevel_DllCntl__SHIFT 0x0 +#define DPM_TABLE_197__MemoryACPILevel_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_197__MemoryACPILevel_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_198__MemoryACPILevel_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_198__MemoryACPILevel_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_200__MemoryLevel_0_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_200__MemoryLevel_0_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_201__MemoryLevel_0_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_201__MemoryLevel_0_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_202__MemoryLevel_0_StutterEnable_MASK 0xff +#define DPM_TABLE_202__MemoryLevel_0_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_202__MemoryLevel_0_RttEnable_MASK 0xff00 +#define DPM_TABLE_202__MemoryLevel_0_RttEnable__SHIFT 0x8 +#define DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_202__MemoryLevel_0_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_202__MemoryLevel_0_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_203__MemoryLevel_0_EnabledForActivity_MASK 0xff +#define DPM_TABLE_203__MemoryLevel_0_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_203__MemoryLevel_0_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_203__MemoryLevel_0_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_203__MemoryLevel_0_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_203__MemoryLevel_0_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_204__MemoryLevel_0_padding_MASK 0xff +#define DPM_TABLE_204__MemoryLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_204__MemoryLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_204__MemoryLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_204__MemoryLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_204__MemoryLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_205__MemoryLevel_0_padding1_MASK 0xff +#define DPM_TABLE_205__MemoryLevel_0_padding1__SHIFT 0x0 +#define DPM_TABLE_205__MemoryLevel_0_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_205__MemoryLevel_0_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_205__MemoryLevel_0_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_205__MemoryLevel_0_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_212__MemoryLevel_0_DllCntl_MASK 0xffffffff +#define DPM_TABLE_212__MemoryLevel_0_DllCntl__SHIFT 0x0 +#define DPM_TABLE_213__MemoryLevel_0_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_213__MemoryLevel_0_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_214__MemoryLevel_0_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_214__MemoryLevel_0_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_216__MemoryLevel_1_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_216__MemoryLevel_1_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_217__MemoryLevel_1_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_217__MemoryLevel_1_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_218__MemoryLevel_1_StutterEnable_MASK 0xff +#define DPM_TABLE_218__MemoryLevel_1_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_218__MemoryLevel_1_RttEnable_MASK 0xff00 +#define DPM_TABLE_218__MemoryLevel_1_RttEnable__SHIFT 0x8 +#define DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_218__MemoryLevel_1_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_218__MemoryLevel_1_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_219__MemoryLevel_1_EnabledForActivity_MASK 0xff +#define DPM_TABLE_219__MemoryLevel_1_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_219__MemoryLevel_1_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_219__MemoryLevel_1_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_219__MemoryLevel_1_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_219__MemoryLevel_1_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_220__MemoryLevel_1_padding_MASK 0xff +#define DPM_TABLE_220__MemoryLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_220__MemoryLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_220__MemoryLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_220__MemoryLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_220__MemoryLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_221__MemoryLevel_1_padding1_MASK 0xff +#define DPM_TABLE_221__MemoryLevel_1_padding1__SHIFT 0x0 +#define DPM_TABLE_221__MemoryLevel_1_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_221__MemoryLevel_1_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_221__MemoryLevel_1_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_221__MemoryLevel_1_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_1_DllCntl_MASK 0xffffffff +#define DPM_TABLE_228__MemoryLevel_1_DllCntl__SHIFT 0x0 +#define DPM_TABLE_229__MemoryLevel_1_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_229__MemoryLevel_1_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_230__MemoryLevel_1_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_230__MemoryLevel_1_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_232__MemoryLevel_2_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_232__MemoryLevel_2_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_233__MemoryLevel_2_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_233__MemoryLevel_2_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_234__MemoryLevel_2_StutterEnable_MASK 0xff +#define DPM_TABLE_234__MemoryLevel_2_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_234__MemoryLevel_2_RttEnable_MASK 0xff00 +#define DPM_TABLE_234__MemoryLevel_2_RttEnable__SHIFT 0x8 +#define DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_234__MemoryLevel_2_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_234__MemoryLevel_2_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_235__MemoryLevel_2_EnabledForActivity_MASK 0xff +#define DPM_TABLE_235__MemoryLevel_2_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_235__MemoryLevel_2_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_235__MemoryLevel_2_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_235__MemoryLevel_2_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_235__MemoryLevel_2_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_236__MemoryLevel_2_padding_MASK 0xff +#define DPM_TABLE_236__MemoryLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_236__MemoryLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_236__MemoryLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_236__MemoryLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_236__MemoryLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_237__MemoryLevel_2_padding1_MASK 0xff +#define DPM_TABLE_237__MemoryLevel_2_padding1__SHIFT 0x0 +#define DPM_TABLE_237__MemoryLevel_2_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_237__MemoryLevel_2_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_237__MemoryLevel_2_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_237__MemoryLevel_2_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_244__MemoryLevel_2_DllCntl_MASK 0xffffffff +#define DPM_TABLE_244__MemoryLevel_2_DllCntl__SHIFT 0x0 +#define DPM_TABLE_245__MemoryLevel_2_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_245__MemoryLevel_2_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_2_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_246__MemoryLevel_2_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_248__MemoryLevel_3_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_248__MemoryLevel_3_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_249__MemoryLevel_3_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_249__MemoryLevel_3_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_250__MemoryLevel_3_StutterEnable_MASK 0xff +#define DPM_TABLE_250__MemoryLevel_3_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_250__MemoryLevel_3_RttEnable_MASK 0xff00 +#define DPM_TABLE_250__MemoryLevel_3_RttEnable__SHIFT 0x8 +#define DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_250__MemoryLevel_3_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_250__MemoryLevel_3_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_251__MemoryLevel_3_EnabledForActivity_MASK 0xff +#define DPM_TABLE_251__MemoryLevel_3_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_251__MemoryLevel_3_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_251__MemoryLevel_3_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_251__MemoryLevel_3_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_251__MemoryLevel_3_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_252__MemoryLevel_3_padding_MASK 0xff +#define DPM_TABLE_252__MemoryLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_252__MemoryLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_252__MemoryLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_252__MemoryLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_252__MemoryLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_253__MemoryLevel_3_padding1_MASK 0xff +#define DPM_TABLE_253__MemoryLevel_3_padding1__SHIFT 0x0 +#define DPM_TABLE_253__MemoryLevel_3_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_253__MemoryLevel_3_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_253__MemoryLevel_3_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_253__MemoryLevel_3_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_260__MemoryLevel_3_DllCntl_MASK 0xffffffff +#define DPM_TABLE_260__MemoryLevel_3_DllCntl__SHIFT 0x0 +#define DPM_TABLE_261__MemoryLevel_3_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_261__MemoryLevel_3_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_262__MemoryLevel_3_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_262__MemoryLevel_3_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_263__LinkLevel_0_SPC_MASK 0xff +#define DPM_TABLE_263__LinkLevel_0_SPC__SHIFT 0x0 +#define DPM_TABLE_263__LinkLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_263__LinkLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_263__LinkLevel_0_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_263__LinkLevel_0_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_263__LinkLevel_0_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_263__LinkLevel_0_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_264__LinkLevel_0_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_264__LinkLevel_0_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_265__LinkLevel_0_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_265__LinkLevel_0_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_266__LinkLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_266__LinkLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_267__LinkLevel_1_SPC_MASK 0xff +#define DPM_TABLE_267__LinkLevel_1_SPC__SHIFT 0x0 +#define DPM_TABLE_267__LinkLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_267__LinkLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_267__LinkLevel_1_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_267__LinkLevel_1_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_267__LinkLevel_1_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_267__LinkLevel_1_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_268__LinkLevel_1_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_268__LinkLevel_1_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_269__LinkLevel_1_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_269__LinkLevel_1_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_270__LinkLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_270__LinkLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_271__LinkLevel_2_SPC_MASK 0xff +#define DPM_TABLE_271__LinkLevel_2_SPC__SHIFT 0x0 +#define DPM_TABLE_271__LinkLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_271__LinkLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_271__LinkLevel_2_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_271__LinkLevel_2_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_271__LinkLevel_2_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_271__LinkLevel_2_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_272__LinkLevel_2_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_272__LinkLevel_2_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_273__LinkLevel_2_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_273__LinkLevel_2_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_274__LinkLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_274__LinkLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_275__LinkLevel_3_SPC_MASK 0xff +#define DPM_TABLE_275__LinkLevel_3_SPC__SHIFT 0x0 +#define DPM_TABLE_275__LinkLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_275__LinkLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_275__LinkLevel_3_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_275__LinkLevel_3_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_275__LinkLevel_3_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_275__LinkLevel_3_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_276__LinkLevel_3_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_276__LinkLevel_3_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_277__LinkLevel_3_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_277__LinkLevel_3_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_278__LinkLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_278__LinkLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_279__LinkLevel_4_SPC_MASK 0xff +#define DPM_TABLE_279__LinkLevel_4_SPC__SHIFT 0x0 +#define DPM_TABLE_279__LinkLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_279__LinkLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_279__LinkLevel_4_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_279__LinkLevel_4_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_279__LinkLevel_4_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_279__LinkLevel_4_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_280__LinkLevel_4_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_280__LinkLevel_4_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_281__LinkLevel_4_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_281__LinkLevel_4_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_282__LinkLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_282__LinkLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_283__LinkLevel_5_SPC_MASK 0xff +#define DPM_TABLE_283__LinkLevel_5_SPC__SHIFT 0x0 +#define DPM_TABLE_283__LinkLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_283__LinkLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_283__LinkLevel_5_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_283__LinkLevel_5_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_283__LinkLevel_5_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_283__LinkLevel_5_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_284__LinkLevel_5_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_284__LinkLevel_5_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_285__LinkLevel_5_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_285__LinkLevel_5_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_286__LinkLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_286__LinkLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_287__LinkLevel_6_SPC_MASK 0xff +#define DPM_TABLE_287__LinkLevel_6_SPC__SHIFT 0x0 +#define DPM_TABLE_287__LinkLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_287__LinkLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_287__LinkLevel_6_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_287__LinkLevel_6_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_287__LinkLevel_6_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_287__LinkLevel_6_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_288__LinkLevel_6_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_288__LinkLevel_6_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_289__LinkLevel_6_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_289__LinkLevel_6_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_290__LinkLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_290__LinkLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_291__LinkLevel_7_SPC_MASK 0xff +#define DPM_TABLE_291__LinkLevel_7_SPC__SHIFT 0x0 +#define DPM_TABLE_291__LinkLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_291__LinkLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_291__LinkLevel_7_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_291__LinkLevel_7_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_291__LinkLevel_7_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_291__LinkLevel_7_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_292__LinkLevel_7_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_292__LinkLevel_7_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_293__LinkLevel_7_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_293__LinkLevel_7_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_294__LinkLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_294__LinkLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_295__ACPILevel_Flags_MASK 0xffffffff +#define DPM_TABLE_295__ACPILevel_Flags__SHIFT 0x0 +#define DPM_TABLE_296__ACPILevel_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_296__ACPILevel_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_297__ACPILevel_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_297__ACPILevel_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_298__ACPILevel_padding_MASK 0xff +#define DPM_TABLE_298__ACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_298__ACPILevel_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_298__ACPILevel_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_298__ACPILevel_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_298__ACPILevel_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_298__ACPILevel_SclkDid_MASK 0xff000000 +#define DPM_TABLE_298__ACPILevel_SclkDid__SHIFT 0x18 +#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff +#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0 +#define DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_305__ACPILevel_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_305__ACPILevel_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_306__ACPILevel_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_306__ACPILevel_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_307__UvdLevel_0_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_307__UvdLevel_0_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_308__UvdLevel_0_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_308__UvdLevel_0_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_310__UvdLevel_0_padding_1_MASK 0xff +#define DPM_TABLE_310__UvdLevel_0_padding_1__SHIFT 0x0 +#define DPM_TABLE_310__UvdLevel_0_padding_0_MASK 0xff00 +#define DPM_TABLE_310__UvdLevel_0_padding_0__SHIFT 0x8 +#define DPM_TABLE_310__UvdLevel_0_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_310__UvdLevel_0_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_310__UvdLevel_0_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_310__UvdLevel_0_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_311__UvdLevel_1_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_311__UvdLevel_1_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_312__UvdLevel_1_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_312__UvdLevel_1_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_314__UvdLevel_1_padding_1_MASK 0xff +#define DPM_TABLE_314__UvdLevel_1_padding_1__SHIFT 0x0 +#define DPM_TABLE_314__UvdLevel_1_padding_0_MASK 0xff00 +#define DPM_TABLE_314__UvdLevel_1_padding_0__SHIFT 0x8 +#define DPM_TABLE_314__UvdLevel_1_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_314__UvdLevel_1_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_314__UvdLevel_1_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_314__UvdLevel_1_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_315__UvdLevel_2_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_315__UvdLevel_2_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_316__UvdLevel_2_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_316__UvdLevel_2_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_318__UvdLevel_2_padding_1_MASK 0xff +#define DPM_TABLE_318__UvdLevel_2_padding_1__SHIFT 0x0 +#define DPM_TABLE_318__UvdLevel_2_padding_0_MASK 0xff00 +#define DPM_TABLE_318__UvdLevel_2_padding_0__SHIFT 0x8 +#define DPM_TABLE_318__UvdLevel_2_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_318__UvdLevel_2_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_318__UvdLevel_2_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_318__UvdLevel_2_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_319__UvdLevel_3_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_319__UvdLevel_3_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_320__UvdLevel_3_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_320__UvdLevel_3_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_322__UvdLevel_3_padding_1_MASK 0xff +#define DPM_TABLE_322__UvdLevel_3_padding_1__SHIFT 0x0 +#define DPM_TABLE_322__UvdLevel_3_padding_0_MASK 0xff00 +#define DPM_TABLE_322__UvdLevel_3_padding_0__SHIFT 0x8 +#define DPM_TABLE_322__UvdLevel_3_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_322__UvdLevel_3_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_322__UvdLevel_3_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_322__UvdLevel_3_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_323__UvdLevel_4_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_323__UvdLevel_4_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_324__UvdLevel_4_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_324__UvdLevel_4_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_326__UvdLevel_4_padding_1_MASK 0xff +#define DPM_TABLE_326__UvdLevel_4_padding_1__SHIFT 0x0 +#define DPM_TABLE_326__UvdLevel_4_padding_0_MASK 0xff00 +#define DPM_TABLE_326__UvdLevel_4_padding_0__SHIFT 0x8 +#define DPM_TABLE_326__UvdLevel_4_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_326__UvdLevel_4_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_326__UvdLevel_4_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_326__UvdLevel_4_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_327__UvdLevel_5_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_327__UvdLevel_5_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_328__UvdLevel_5_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_328__UvdLevel_5_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_330__UvdLevel_5_padding_1_MASK 0xff +#define DPM_TABLE_330__UvdLevel_5_padding_1__SHIFT 0x0 +#define DPM_TABLE_330__UvdLevel_5_padding_0_MASK 0xff00 +#define DPM_TABLE_330__UvdLevel_5_padding_0__SHIFT 0x8 +#define DPM_TABLE_330__UvdLevel_5_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_330__UvdLevel_5_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_330__UvdLevel_5_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_330__UvdLevel_5_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_331__UvdLevel_6_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_331__UvdLevel_6_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_332__UvdLevel_6_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_332__UvdLevel_6_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_334__UvdLevel_6_padding_1_MASK 0xff +#define DPM_TABLE_334__UvdLevel_6_padding_1__SHIFT 0x0 +#define DPM_TABLE_334__UvdLevel_6_padding_0_MASK 0xff00 +#define DPM_TABLE_334__UvdLevel_6_padding_0__SHIFT 0x8 +#define DPM_TABLE_334__UvdLevel_6_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_334__UvdLevel_6_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_334__UvdLevel_6_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_334__UvdLevel_6_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_335__UvdLevel_7_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_335__UvdLevel_7_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_336__UvdLevel_7_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_336__UvdLevel_7_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_338__UvdLevel_7_padding_1_MASK 0xff +#define DPM_TABLE_338__UvdLevel_7_padding_1__SHIFT 0x0 +#define DPM_TABLE_338__UvdLevel_7_padding_0_MASK 0xff00 +#define DPM_TABLE_338__UvdLevel_7_padding_0__SHIFT 0x8 +#define DPM_TABLE_338__UvdLevel_7_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_338__UvdLevel_7_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_338__UvdLevel_7_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_338__UvdLevel_7_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_339__VceLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_339__VceLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_341__VceLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_341__VceLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_341__VceLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_341__VceLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_341__VceLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_341__VceLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_341__VceLevel_0_Divider_MASK 0xff000000 +#define DPM_TABLE_341__VceLevel_0_Divider__SHIFT 0x18 +#define DPM_TABLE_342__VceLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_342__VceLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_344__VceLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_344__VceLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_344__VceLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_344__VceLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_344__VceLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_344__VceLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_344__VceLevel_1_Divider_MASK 0xff000000 +#define DPM_TABLE_344__VceLevel_1_Divider__SHIFT 0x18 +#define DPM_TABLE_345__VceLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_345__VceLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_347__VceLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_347__VceLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_347__VceLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_347__VceLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_347__VceLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_347__VceLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_347__VceLevel_2_Divider_MASK 0xff000000 +#define DPM_TABLE_347__VceLevel_2_Divider__SHIFT 0x18 +#define DPM_TABLE_348__VceLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_348__VceLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_350__VceLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_350__VceLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_350__VceLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_350__VceLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_350__VceLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_350__VceLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_350__VceLevel_3_Divider_MASK 0xff000000 +#define DPM_TABLE_350__VceLevel_3_Divider__SHIFT 0x18 +#define DPM_TABLE_351__VceLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_351__VceLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_353__VceLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_353__VceLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_353__VceLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_353__VceLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_353__VceLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_353__VceLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_353__VceLevel_4_Divider_MASK 0xff000000 +#define DPM_TABLE_353__VceLevel_4_Divider__SHIFT 0x18 +#define DPM_TABLE_354__VceLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_354__VceLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_356__VceLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_356__VceLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_356__VceLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_356__VceLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_356__VceLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_356__VceLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_356__VceLevel_5_Divider_MASK 0xff000000 +#define DPM_TABLE_356__VceLevel_5_Divider__SHIFT 0x18 +#define DPM_TABLE_357__VceLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_357__VceLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_359__VceLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_359__VceLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_359__VceLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_359__VceLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_359__VceLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_359__VceLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_359__VceLevel_6_Divider_MASK 0xff000000 +#define DPM_TABLE_359__VceLevel_6_Divider__SHIFT 0x18 +#define DPM_TABLE_360__VceLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_360__VceLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_362__VceLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_362__VceLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_362__VceLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_362__VceLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_362__VceLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_362__VceLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_362__VceLevel_7_Divider_MASK 0xff000000 +#define DPM_TABLE_362__VceLevel_7_Divider__SHIFT 0x18 +#define DPM_TABLE_363__AcpLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_363__AcpLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_365__AcpLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_365__AcpLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_365__AcpLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_365__AcpLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_365__AcpLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_365__AcpLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_365__AcpLevel_0_Divider_MASK 0xff000000 +#define DPM_TABLE_365__AcpLevel_0_Divider__SHIFT 0x18 +#define DPM_TABLE_366__AcpLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_366__AcpLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_368__AcpLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_368__AcpLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_368__AcpLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_368__AcpLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_368__AcpLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_368__AcpLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_368__AcpLevel_1_Divider_MASK 0xff000000 +#define DPM_TABLE_368__AcpLevel_1_Divider__SHIFT 0x18 +#define DPM_TABLE_369__AcpLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_369__AcpLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_371__AcpLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_371__AcpLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_371__AcpLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_371__AcpLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_371__AcpLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_371__AcpLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_371__AcpLevel_2_Divider_MASK 0xff000000 +#define DPM_TABLE_371__AcpLevel_2_Divider__SHIFT 0x18 +#define DPM_TABLE_372__AcpLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_372__AcpLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_374__AcpLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_374__AcpLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_374__AcpLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_374__AcpLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_374__AcpLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_374__AcpLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_374__AcpLevel_3_Divider_MASK 0xff000000 +#define DPM_TABLE_374__AcpLevel_3_Divider__SHIFT 0x18 +#define DPM_TABLE_375__AcpLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_375__AcpLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_377__AcpLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_377__AcpLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_377__AcpLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_377__AcpLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_377__AcpLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_377__AcpLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_377__AcpLevel_4_Divider_MASK 0xff000000 +#define DPM_TABLE_377__AcpLevel_4_Divider__SHIFT 0x18 +#define DPM_TABLE_378__AcpLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_378__AcpLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_380__AcpLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_380__AcpLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_380__AcpLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_380__AcpLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_380__AcpLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_380__AcpLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_380__AcpLevel_5_Divider_MASK 0xff000000 +#define DPM_TABLE_380__AcpLevel_5_Divider__SHIFT 0x18 +#define DPM_TABLE_381__AcpLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_381__AcpLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_383__AcpLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_383__AcpLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_383__AcpLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_383__AcpLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_383__AcpLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_383__AcpLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_383__AcpLevel_6_Divider_MASK 0xff000000 +#define DPM_TABLE_383__AcpLevel_6_Divider__SHIFT 0x18 +#define DPM_TABLE_384__AcpLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_384__AcpLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_386__AcpLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_386__AcpLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_386__AcpLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_386__AcpLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_386__AcpLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_386__AcpLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_386__AcpLevel_7_Divider_MASK 0xff000000 +#define DPM_TABLE_386__AcpLevel_7_Divider__SHIFT 0x18 +#define DPM_TABLE_387__SamuLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_387__SamuLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_389__SamuLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_389__SamuLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_389__SamuLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_389__SamuLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_389__SamuLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_389__SamuLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_389__SamuLevel_0_Divider_MASK 0xff000000 +#define DPM_TABLE_389__SamuLevel_0_Divider__SHIFT 0x18 +#define DPM_TABLE_390__SamuLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_390__SamuLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_392__SamuLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_392__SamuLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_392__SamuLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_392__SamuLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_392__SamuLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_392__SamuLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_392__SamuLevel_1_Divider_MASK 0xff000000 +#define DPM_TABLE_392__SamuLevel_1_Divider__SHIFT 0x18 +#define DPM_TABLE_393__SamuLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_393__SamuLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_395__SamuLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_395__SamuLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_395__SamuLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_395__SamuLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_395__SamuLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_395__SamuLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_395__SamuLevel_2_Divider_MASK 0xff000000 +#define DPM_TABLE_395__SamuLevel_2_Divider__SHIFT 0x18 +#define DPM_TABLE_396__SamuLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_396__SamuLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_398__SamuLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_398__SamuLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_398__SamuLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_398__SamuLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_398__SamuLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_398__SamuLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_398__SamuLevel_3_Divider_MASK 0xff000000 +#define DPM_TABLE_398__SamuLevel_3_Divider__SHIFT 0x18 +#define DPM_TABLE_399__SamuLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_399__SamuLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_401__SamuLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_401__SamuLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_401__SamuLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_401__SamuLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_401__SamuLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_401__SamuLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_401__SamuLevel_4_Divider_MASK 0xff000000 +#define DPM_TABLE_401__SamuLevel_4_Divider__SHIFT 0x18 +#define DPM_TABLE_402__SamuLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_402__SamuLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_404__SamuLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_404__SamuLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_404__SamuLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_404__SamuLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_404__SamuLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_404__SamuLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_404__SamuLevel_5_Divider_MASK 0xff000000 +#define DPM_TABLE_404__SamuLevel_5_Divider__SHIFT 0x18 +#define DPM_TABLE_405__SamuLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_405__SamuLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_407__SamuLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_407__SamuLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_407__SamuLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_407__SamuLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_407__SamuLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_407__SamuLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_407__SamuLevel_6_Divider_MASK 0xff000000 +#define DPM_TABLE_407__SamuLevel_6_Divider__SHIFT 0x18 +#define DPM_TABLE_408__SamuLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_408__SamuLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_410__SamuLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_410__SamuLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_410__SamuLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_410__SamuLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_410__SamuLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_410__SamuLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_410__SamuLevel_7_Divider_MASK 0xff000000 +#define DPM_TABLE_410__SamuLevel_7_Divider__SHIFT 0x18 +#define DPM_TABLE_411__Ulv_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_411__Ulv_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_412__Ulv_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_412__Ulv_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_413__Ulv_VddcPhase_MASK 0xff +#define DPM_TABLE_413__Ulv_VddcPhase__SHIFT 0x0 +#define DPM_TABLE_413__Ulv_VddcOffsetVid_MASK 0xff00 +#define DPM_TABLE_413__Ulv_VddcOffsetVid__SHIFT 0x8 +#define DPM_TABLE_413__Ulv_VddcOffset_MASK 0xffff0000 +#define DPM_TABLE_413__Ulv_VddcOffset__SHIFT 0x10 +#define DPM_TABLE_414__Ulv_Reserved_MASK 0xffffffff +#define DPM_TABLE_414__Ulv_Reserved__SHIFT 0x0 +#define DPM_TABLE_415__SclkStepSize_MASK 0xffffffff +#define DPM_TABLE_415__SclkStepSize__SHIFT 0x0 +#define DPM_TABLE_416__Smio_0_MASK 0xffffffff +#define DPM_TABLE_416__Smio_0__SHIFT 0x0 +#define DPM_TABLE_417__Smio_1_MASK 0xffffffff +#define DPM_TABLE_417__Smio_1__SHIFT 0x0 +#define DPM_TABLE_418__Smio_2_MASK 0xffffffff +#define DPM_TABLE_418__Smio_2__SHIFT 0x0 +#define DPM_TABLE_419__Smio_3_MASK 0xffffffff +#define DPM_TABLE_419__Smio_3__SHIFT 0x0 +#define DPM_TABLE_420__Smio_4_MASK 0xffffffff +#define DPM_TABLE_420__Smio_4__SHIFT 0x0 +#define DPM_TABLE_421__Smio_5_MASK 0xffffffff +#define DPM_TABLE_421__Smio_5__SHIFT 0x0 +#define DPM_TABLE_422__Smio_6_MASK 0xffffffff +#define DPM_TABLE_422__Smio_6__SHIFT 0x0 +#define DPM_TABLE_423__Smio_7_MASK 0xffffffff +#define DPM_TABLE_423__Smio_7__SHIFT 0x0 +#define DPM_TABLE_424__Smio_8_MASK 0xffffffff +#define DPM_TABLE_424__Smio_8__SHIFT 0x0 +#define DPM_TABLE_425__Smio_9_MASK 0xffffffff +#define DPM_TABLE_425__Smio_9__SHIFT 0x0 +#define DPM_TABLE_426__Smio_10_MASK 0xffffffff +#define DPM_TABLE_426__Smio_10__SHIFT 0x0 +#define DPM_TABLE_427__Smio_11_MASK 0xffffffff +#define DPM_TABLE_427__Smio_11__SHIFT 0x0 +#define DPM_TABLE_428__Smio_12_MASK 0xffffffff +#define DPM_TABLE_428__Smio_12__SHIFT 0x0 +#define DPM_TABLE_429__Smio_13_MASK 0xffffffff +#define DPM_TABLE_429__Smio_13__SHIFT 0x0 +#define DPM_TABLE_430__Smio_14_MASK 0xffffffff +#define DPM_TABLE_430__Smio_14__SHIFT 0x0 +#define DPM_TABLE_431__Smio_15_MASK 0xffffffff +#define DPM_TABLE_431__Smio_15__SHIFT 0x0 +#define DPM_TABLE_432__Smio_16_MASK 0xffffffff +#define DPM_TABLE_432__Smio_16__SHIFT 0x0 +#define DPM_TABLE_433__Smio_17_MASK 0xffffffff +#define DPM_TABLE_433__Smio_17__SHIFT 0x0 +#define DPM_TABLE_434__Smio_18_MASK 0xffffffff +#define DPM_TABLE_434__Smio_18__SHIFT 0x0 +#define DPM_TABLE_435__Smio_19_MASK 0xffffffff +#define DPM_TABLE_435__Smio_19__SHIFT 0x0 +#define DPM_TABLE_436__Smio_20_MASK 0xffffffff +#define DPM_TABLE_436__Smio_20__SHIFT 0x0 +#define DPM_TABLE_437__Smio_21_MASK 0xffffffff +#define DPM_TABLE_437__Smio_21__SHIFT 0x0 +#define DPM_TABLE_438__Smio_22_MASK 0xffffffff +#define DPM_TABLE_438__Smio_22__SHIFT 0x0 +#define DPM_TABLE_439__Smio_23_MASK 0xffffffff +#define DPM_TABLE_439__Smio_23__SHIFT 0x0 +#define DPM_TABLE_440__Smio_24_MASK 0xffffffff +#define DPM_TABLE_440__Smio_24__SHIFT 0x0 +#define DPM_TABLE_441__Smio_25_MASK 0xffffffff +#define DPM_TABLE_441__Smio_25__SHIFT 0x0 +#define DPM_TABLE_442__Smio_26_MASK 0xffffffff +#define DPM_TABLE_442__Smio_26__SHIFT 0x0 +#define DPM_TABLE_443__Smio_27_MASK 0xffffffff +#define DPM_TABLE_443__Smio_27__SHIFT 0x0 +#define DPM_TABLE_444__Smio_28_MASK 0xffffffff +#define DPM_TABLE_444__Smio_28__SHIFT 0x0 +#define DPM_TABLE_445__Smio_29_MASK 0xffffffff +#define DPM_TABLE_445__Smio_29__SHIFT 0x0 +#define DPM_TABLE_446__Smio_30_MASK 0xffffffff +#define DPM_TABLE_446__Smio_30__SHIFT 0x0 +#define DPM_TABLE_447__Smio_31_MASK 0xffffffff +#define DPM_TABLE_447__Smio_31__SHIFT 0x0 +#define DPM_TABLE_448__SamuBootLevel_MASK 0xff +#define DPM_TABLE_448__SamuBootLevel__SHIFT 0x0 +#define DPM_TABLE_448__AcpBootLevel_MASK 0xff00 +#define DPM_TABLE_448__AcpBootLevel__SHIFT 0x8 +#define DPM_TABLE_448__VceBootLevel_MASK 0xff0000 +#define DPM_TABLE_448__VceBootLevel__SHIFT 0x10 +#define DPM_TABLE_448__UvdBootLevel_MASK 0xff000000 +#define DPM_TABLE_448__UvdBootLevel__SHIFT 0x18 +#define DPM_TABLE_449__GraphicsInterval_MASK 0xff +#define DPM_TABLE_449__GraphicsInterval__SHIFT 0x0 +#define DPM_TABLE_449__GraphicsThermThrottleEnable_MASK 0xff00 +#define DPM_TABLE_449__GraphicsThermThrottleEnable__SHIFT 0x8 +#define DPM_TABLE_449__GraphicsVoltageChangeEnable_MASK 0xff0000 +#define DPM_TABLE_449__GraphicsVoltageChangeEnable__SHIFT 0x10 +#define DPM_TABLE_449__GraphicsBootLevel_MASK 0xff000000 +#define DPM_TABLE_449__GraphicsBootLevel__SHIFT 0x18 +#define DPM_TABLE_450__TemperatureLimitHigh_MASK 0xffff +#define DPM_TABLE_450__TemperatureLimitHigh__SHIFT 0x0 +#define DPM_TABLE_450__ThermalInterval_MASK 0xff0000 +#define DPM_TABLE_450__ThermalInterval__SHIFT 0x10 +#define DPM_TABLE_450__VoltageInterval_MASK 0xff000000 +#define DPM_TABLE_450__VoltageInterval__SHIFT 0x18 +#define DPM_TABLE_451__MemoryVoltageChangeEnable_MASK 0xff +#define DPM_TABLE_451__MemoryVoltageChangeEnable__SHIFT 0x0 +#define DPM_TABLE_451__MemoryBootLevel_MASK 0xff00 +#define DPM_TABLE_451__MemoryBootLevel__SHIFT 0x8 +#define DPM_TABLE_451__TemperatureLimitLow_MASK 0xffff0000 +#define DPM_TABLE_451__TemperatureLimitLow__SHIFT 0x10 +#define DPM_TABLE_452__MemoryThermThrottleEnable_MASK 0xff +#define DPM_TABLE_452__MemoryThermThrottleEnable__SHIFT 0x0 +#define DPM_TABLE_452__MemoryInterval_MASK 0xff00 +#define DPM_TABLE_452__MemoryInterval__SHIFT 0x8 +#define DPM_TABLE_452__BootMVdd_MASK 0xffff0000 +#define DPM_TABLE_452__BootMVdd__SHIFT 0x10 +#define DPM_TABLE_453__PhaseResponseTime_MASK 0xffff +#define DPM_TABLE_453__PhaseResponseTime__SHIFT 0x0 +#define DPM_TABLE_453__VoltageResponseTime_MASK 0xffff0000 +#define DPM_TABLE_453__VoltageResponseTime__SHIFT 0x10 +#define DPM_TABLE_454__DTEMode_MASK 0xff +#define DPM_TABLE_454__DTEMode__SHIFT 0x0 +#define DPM_TABLE_454__DTEInterval_MASK 0xff00 +#define DPM_TABLE_454__DTEInterval__SHIFT 0x8 +#define DPM_TABLE_454__PCIeGenInterval_MASK 0xff0000 +#define DPM_TABLE_454__PCIeGenInterval__SHIFT 0x10 +#define DPM_TABLE_454__PCIeBootLinkLevel_MASK 0xff000000 +#define DPM_TABLE_454__PCIeBootLinkLevel__SHIFT 0x18 +#define DPM_TABLE_455__ThermGpio_MASK 0xff +#define DPM_TABLE_455__ThermGpio__SHIFT 0x0 +#define DPM_TABLE_455__AcDcGpio_MASK 0xff00 +#define DPM_TABLE_455__AcDcGpio__SHIFT 0x8 +#define DPM_TABLE_455__VRHotGpio_MASK 0xff0000 +#define DPM_TABLE_455__VRHotGpio__SHIFT 0x10 +#define DPM_TABLE_455__SVI2Enable_MASK 0xff000000 +#define DPM_TABLE_455__SVI2Enable__SHIFT 0x18 +#define DPM_TABLE_456__PPM_TemperatureLimit_MASK 0xffff +#define DPM_TABLE_456__PPM_TemperatureLimit__SHIFT 0x0 +#define DPM_TABLE_456__PPM_PkgPwrLimit_MASK 0xffff0000 +#define DPM_TABLE_456__PPM_PkgPwrLimit__SHIFT 0x10 +#define DPM_TABLE_457__TargetTdp_MASK 0xffff +#define DPM_TABLE_457__TargetTdp__SHIFT 0x0 +#define DPM_TABLE_457__DefaultTdp_MASK 0xffff0000 +#define DPM_TABLE_457__DefaultTdp__SHIFT 0x10 +#define DPM_TABLE_458__FpsLowThreshold_MASK 0xffff +#define DPM_TABLE_458__FpsLowThreshold__SHIFT 0x0 +#define DPM_TABLE_458__FpsHighThreshold_MASK 0xffff0000 +#define DPM_TABLE_458__FpsHighThreshold__SHIFT 0x10 +#define DPM_TABLE_459__BAPMTI_R_0_1_0_MASK 0xffff +#define DPM_TABLE_459__BAPMTI_R_0_1_0__SHIFT 0x0 +#define DPM_TABLE_459__BAPMTI_R_0_0_0_MASK 0xffff0000 +#define DPM_TABLE_459__BAPMTI_R_0_0_0__SHIFT 0x10 +#define DPM_TABLE_460__BAPMTI_R_1_0_0_MASK 0xffff +#define DPM_TABLE_460__BAPMTI_R_1_0_0__SHIFT 0x0 +#define DPM_TABLE_460__BAPMTI_R_0_2_0_MASK 0xffff0000 +#define DPM_TABLE_460__BAPMTI_R_0_2_0__SHIFT 0x10 +#define DPM_TABLE_461__BAPMTI_R_1_2_0_MASK 0xffff +#define DPM_TABLE_461__BAPMTI_R_1_2_0__SHIFT 0x0 +#define DPM_TABLE_461__BAPMTI_R_1_1_0_MASK 0xffff0000 +#define DPM_TABLE_461__BAPMTI_R_1_1_0__SHIFT 0x10 +#define DPM_TABLE_462__BAPMTI_R_2_1_0_MASK 0xffff +#define DPM_TABLE_462__BAPMTI_R_2_1_0__SHIFT 0x0 +#define DPM_TABLE_462__BAPMTI_R_2_0_0_MASK 0xffff0000 +#define DPM_TABLE_462__BAPMTI_R_2_0_0__SHIFT 0x10 +#define DPM_TABLE_463__BAPMTI_R_3_0_0_MASK 0xffff +#define DPM_TABLE_463__BAPMTI_R_3_0_0__SHIFT 0x0 +#define DPM_TABLE_463__BAPMTI_R_2_2_0_MASK 0xffff0000 +#define DPM_TABLE_463__BAPMTI_R_2_2_0__SHIFT 0x10 +#define DPM_TABLE_464__BAPMTI_R_3_2_0_MASK 0xffff +#define DPM_TABLE_464__BAPMTI_R_3_2_0__SHIFT 0x0 +#define DPM_TABLE_464__BAPMTI_R_3_1_0_MASK 0xffff0000 +#define DPM_TABLE_464__BAPMTI_R_3_1_0__SHIFT 0x10 +#define DPM_TABLE_465__BAPMTI_R_4_1_0_MASK 0xffff +#define DPM_TABLE_465__BAPMTI_R_4_1_0__SHIFT 0x0 +#define DPM_TABLE_465__BAPMTI_R_4_0_0_MASK 0xffff0000 +#define DPM_TABLE_465__BAPMTI_R_4_0_0__SHIFT 0x10 +#define DPM_TABLE_466__BAPMTI_RC_0_0_0_MASK 0xffff +#define DPM_TABLE_466__BAPMTI_RC_0_0_0__SHIFT 0x0 +#define DPM_TABLE_466__BAPMTI_R_4_2_0_MASK 0xffff0000 +#define DPM_TABLE_466__BAPMTI_R_4_2_0__SHIFT 0x10 +#define DPM_TABLE_467__BAPMTI_RC_0_2_0_MASK 0xffff +#define DPM_TABLE_467__BAPMTI_RC_0_2_0__SHIFT 0x0 +#define DPM_TABLE_467__BAPMTI_RC_0_1_0_MASK 0xffff0000 +#define DPM_TABLE_467__BAPMTI_RC_0_1_0__SHIFT 0x10 +#define DPM_TABLE_468__BAPMTI_RC_1_1_0_MASK 0xffff +#define DPM_TABLE_468__BAPMTI_RC_1_1_0__SHIFT 0x0 +#define DPM_TABLE_468__BAPMTI_RC_1_0_0_MASK 0xffff0000 +#define DPM_TABLE_468__BAPMTI_RC_1_0_0__SHIFT 0x10 +#define DPM_TABLE_469__BAPMTI_RC_2_0_0_MASK 0xffff +#define DPM_TABLE_469__BAPMTI_RC_2_0_0__SHIFT 0x0 +#define DPM_TABLE_469__BAPMTI_RC_1_2_0_MASK 0xffff0000 +#define DPM_TABLE_469__BAPMTI_RC_1_2_0__SHIFT 0x10 +#define DPM_TABLE_470__BAPMTI_RC_2_2_0_MASK 0xffff +#define DPM_TABLE_470__BAPMTI_RC_2_2_0__SHIFT 0x0 +#define DPM_TABLE_470__BAPMTI_RC_2_1_0_MASK 0xffff0000 +#define DPM_TABLE_470__BAPMTI_RC_2_1_0__SHIFT 0x10 +#define DPM_TABLE_471__BAPMTI_RC_3_1_0_MASK 0xffff +#define DPM_TABLE_471__BAPMTI_RC_3_1_0__SHIFT 0x0 +#define DPM_TABLE_471__BAPMTI_RC_3_0_0_MASK 0xffff0000 +#define DPM_TABLE_471__BAPMTI_RC_3_0_0__SHIFT 0x10 +#define DPM_TABLE_472__BAPMTI_RC_4_0_0_MASK 0xffff +#define DPM_TABLE_472__BAPMTI_RC_4_0_0__SHIFT 0x0 +#define DPM_TABLE_472__BAPMTI_RC_3_2_0_MASK 0xffff0000 +#define DPM_TABLE_472__BAPMTI_RC_3_2_0__SHIFT 0x10 +#define DPM_TABLE_473__BAPMTI_RC_4_2_0_MASK 0xffff +#define DPM_TABLE_473__BAPMTI_RC_4_2_0__SHIFT 0x0 +#define DPM_TABLE_473__BAPMTI_RC_4_1_0_MASK 0xffff0000 +#define DPM_TABLE_473__BAPMTI_RC_4_1_0__SHIFT 0x10 +#define DPM_TABLE_474__GpuTjHyst_MASK 0xff +#define DPM_TABLE_474__GpuTjHyst__SHIFT 0x0 +#define DPM_TABLE_474__GpuTjMax_MASK 0xff00 +#define DPM_TABLE_474__GpuTjMax__SHIFT 0x8 +#define DPM_TABLE_474__DTETjOffset_MASK 0xff0000 +#define DPM_TABLE_474__DTETjOffset__SHIFT 0x10 +#define DPM_TABLE_474__DTEAmbientTempBase_MASK 0xff000000 +#define DPM_TABLE_474__DTEAmbientTempBase__SHIFT 0x18 +#define DPM_TABLE_475__BootVoltage_Phases_MASK 0xff +#define DPM_TABLE_475__BootVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_475__BootVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_475__BootVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_475__BootVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_475__BootVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_475__BootVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_475__BootVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_476__BAPM_TEMP_GRADIENT_MASK 0xffffffff +#define DPM_TABLE_476__BAPM_TEMP_GRADIENT__SHIFT 0x0 +#define DPM_TABLE_477__LowSclkInterruptThreshold_MASK 0xffffffff +#define DPM_TABLE_477__LowSclkInterruptThreshold__SHIFT 0x0 +#define DPM_TABLE_478__VddGfxReChkWait_MASK 0xffffffff +#define DPM_TABLE_478__VddGfxReChkWait__SHIFT 0x0 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1_MASK 0xff +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1__SHIFT 0x0 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0_MASK 0xff00 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0__SHIFT 0x8 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID_MASK 0xff0000 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID__SHIFT 0x10 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID_MASK 0xff000000 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID__SHIFT 0x18 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3_MASK 0xff +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3__SHIFT 0x0 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2_MASK 0xff00 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2__SHIFT 0x8 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1_MASK 0xff0000 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1__SHIFT 0x10 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0_MASK 0xff000000 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0__SHIFT 0x18 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7_MASK 0xff +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7__SHIFT 0x0 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6_MASK 0xff00 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6__SHIFT 0x8 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5_MASK 0xff0000 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5__SHIFT 0x10 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4_MASK 0xff000000 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4__SHIFT 0x18 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1_MASK 0xff +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1__SHIFT 0x0 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0_MASK 0xff00 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0__SHIFT 0x8 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID_MASK 0xff0000 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID__SHIFT 0x10 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID_MASK 0xff000000 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID__SHIFT 0x18 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3_MASK 0xff +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3__SHIFT 0x0 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2_MASK 0xff00 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2__SHIFT 0x8 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1_MASK 0xff0000 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1__SHIFT 0x10 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0_MASK 0xff000000 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0__SHIFT 0x18 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7_MASK 0xff +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7__SHIFT 0x0 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6_MASK 0xff00 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6__SHIFT 0x8 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5_MASK 0xff0000 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5__SHIFT 0x10 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4_MASK 0xff000000 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4__SHIFT 0x18 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1_MASK 0xff +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1__SHIFT 0x0 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0_MASK 0xff00 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0__SHIFT 0x8 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID_MASK 0xff0000 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID__SHIFT 0x10 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID_MASK 0xff000000 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID__SHIFT 0x18 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3_MASK 0xff +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3__SHIFT 0x0 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2_MASK 0xff00 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2__SHIFT 0x8 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1_MASK 0xff0000 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1__SHIFT 0x10 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0_MASK 0xff000000 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0__SHIFT 0x18 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7_MASK 0xff +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7__SHIFT 0x0 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6_MASK 0xff00 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6__SHIFT 0x8 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5_MASK 0xff0000 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5__SHIFT 0x10 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4_MASK 0xff000000 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4__SHIFT 0x18 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1_MASK 0xff +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1__SHIFT 0x0 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0_MASK 0xff00 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0__SHIFT 0x8 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID_MASK 0xff0000 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID__SHIFT 0x10 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID_MASK 0xff000000 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID__SHIFT 0x18 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3_MASK 0xff +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3__SHIFT 0x0 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2_MASK 0xff00 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2__SHIFT 0x8 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1_MASK 0xff0000 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1__SHIFT 0x10 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0_MASK 0xff000000 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0__SHIFT 0x18 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7_MASK 0xff +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7__SHIFT 0x0 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6_MASK 0xff00 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6__SHIFT 0x8 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5_MASK 0xff0000 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5__SHIFT 0x10 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4_MASK 0xff000000 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18 +#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff +#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00 +#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8 +#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000 +#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000 +#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18 +#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0 +#define FAN_TABLE_1__TempMin_MASK 0xffff +#define FAN_TABLE_1__TempMin__SHIFT 0x0 +#define FAN_TABLE_1__FdoMode_MASK 0xffff0000 +#define FAN_TABLE_1__FdoMode__SHIFT 0x10 +#define FAN_TABLE_2__TempMax_MASK 0xffff +#define FAN_TABLE_2__TempMax__SHIFT 0x0 +#define FAN_TABLE_2__TempMed_MASK 0xffff0000 +#define FAN_TABLE_2__TempMed__SHIFT 0x10 +#define FAN_TABLE_3__Slope2_MASK 0xffff +#define FAN_TABLE_3__Slope2__SHIFT 0x0 +#define FAN_TABLE_3__Slope1_MASK 0xffff0000 +#define FAN_TABLE_3__Slope1__SHIFT 0x10 +#define FAN_TABLE_4__HystUp_MASK 0xffff +#define FAN_TABLE_4__HystUp__SHIFT 0x0 +#define FAN_TABLE_4__FdoMin_MASK 0xffff0000 +#define FAN_TABLE_4__FdoMin__SHIFT 0x10 +#define FAN_TABLE_5__HystSlope_MASK 0xffff +#define FAN_TABLE_5__HystSlope__SHIFT 0x0 +#define FAN_TABLE_5__HystDown_MASK 0xffff0000 +#define FAN_TABLE_5__HystDown__SHIFT 0x10 +#define FAN_TABLE_6__TempCurr_MASK 0xffff +#define FAN_TABLE_6__TempCurr__SHIFT 0x0 +#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000 +#define FAN_TABLE_6__TempRespLim__SHIFT 0x10 +#define FAN_TABLE_7__PwmCurr_MASK 0xffff +#define FAN_TABLE_7__PwmCurr__SHIFT 0x0 +#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000 +#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10 +#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff +#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0 +#define FAN_TABLE_9__Padding_MASK 0xff +#define FAN_TABLE_9__Padding__SHIFT 0x0 +#define FAN_TABLE_9__TempSrc_MASK 0xff00 +#define FAN_TABLE_9__TempSrc__SHIFT 0x8 +#define FAN_TABLE_9__FdoMax_MASK 0xffff0000 +#define FAN_TABLE_9__FdoMax__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_29__Reserved_0_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_29__Reserved_0__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_30__Reserved_1_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_30__Reserved_1__SHIFT 0x0 +#define PM_FUSES_1__SviLoadLineOffsetVddC_MASK 0xff +#define PM_FUSES_1__SviLoadLineOffsetVddC__SHIFT 0x0 +#define PM_FUSES_1__SviLoadLineTrimVddC_MASK 0xff00 +#define PM_FUSES_1__SviLoadLineTrimVddC__SHIFT 0x8 +#define PM_FUSES_1__SviLoadLineVddC_MASK 0xff0000 +#define PM_FUSES_1__SviLoadLineVddC__SHIFT 0x10 +#define PM_FUSES_1__SviLoadLineEn_MASK 0xff000000 +#define PM_FUSES_1__SviLoadLineEn__SHIFT 0x18 +#define PM_FUSES_2__TDC_MAWt_MASK 0xff +#define PM_FUSES_2__TDC_MAWt__SHIFT 0x0 +#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00 +#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8 +#define PM_FUSES_2__TDC_VDDC_PkgLimit_MASK 0xffff0000 +#define PM_FUSES_2__TDC_VDDC_PkgLimit__SHIFT 0x10 +#define PM_FUSES_3__Reserved_MASK 0xff +#define PM_FUSES_3__Reserved__SHIFT 0x0 +#define PM_FUSES_3__LPMLTemperatureMax_MASK 0xff00 +#define PM_FUSES_3__LPMLTemperatureMax__SHIFT 0x8 +#define PM_FUSES_3__LPMLTemperatureMin_MASK 0xff0000 +#define PM_FUSES_3__LPMLTemperatureMin__SHIFT 0x10 +#define PM_FUSES_3__TdcWaterfallCtl_MASK 0xff000000 +#define PM_FUSES_3__TdcWaterfallCtl__SHIFT 0x18 +#define PM_FUSES_4__LPMLTemperatureScaler_3_MASK 0xff +#define PM_FUSES_4__LPMLTemperatureScaler_3__SHIFT 0x0 +#define PM_FUSES_4__LPMLTemperatureScaler_2_MASK 0xff00 +#define PM_FUSES_4__LPMLTemperatureScaler_2__SHIFT 0x8 +#define PM_FUSES_4__LPMLTemperatureScaler_1_MASK 0xff0000 +#define PM_FUSES_4__LPMLTemperatureScaler_1__SHIFT 0x10 +#define PM_FUSES_4__LPMLTemperatureScaler_0_MASK 0xff000000 +#define PM_FUSES_4__LPMLTemperatureScaler_0__SHIFT 0x18 +#define PM_FUSES_5__LPMLTemperatureScaler_7_MASK 0xff +#define PM_FUSES_5__LPMLTemperatureScaler_7__SHIFT 0x0 +#define PM_FUSES_5__LPMLTemperatureScaler_6_MASK 0xff00 +#define PM_FUSES_5__LPMLTemperatureScaler_6__SHIFT 0x8 +#define PM_FUSES_5__LPMLTemperatureScaler_5_MASK 0xff0000 +#define PM_FUSES_5__LPMLTemperatureScaler_5__SHIFT 0x10 +#define PM_FUSES_5__LPMLTemperatureScaler_4_MASK 0xff000000 +#define PM_FUSES_5__LPMLTemperatureScaler_4__SHIFT 0x18 +#define PM_FUSES_6__LPMLTemperatureScaler_11_MASK 0xff +#define PM_FUSES_6__LPMLTemperatureScaler_11__SHIFT 0x0 +#define PM_FUSES_6__LPMLTemperatureScaler_10_MASK 0xff00 +#define PM_FUSES_6__LPMLTemperatureScaler_10__SHIFT 0x8 +#define PM_FUSES_6__LPMLTemperatureScaler_9_MASK 0xff0000 +#define PM_FUSES_6__LPMLTemperatureScaler_9__SHIFT 0x10 +#define PM_FUSES_6__LPMLTemperatureScaler_8_MASK 0xff000000 +#define PM_FUSES_6__LPMLTemperatureScaler_8__SHIFT 0x18 +#define PM_FUSES_7__LPMLTemperatureScaler_15_MASK 0xff +#define PM_FUSES_7__LPMLTemperatureScaler_15__SHIFT 0x0 +#define PM_FUSES_7__LPMLTemperatureScaler_14_MASK 0xff00 +#define PM_FUSES_7__LPMLTemperatureScaler_14__SHIFT 0x8 +#define PM_FUSES_7__LPMLTemperatureScaler_13_MASK 0xff0000 +#define PM_FUSES_7__LPMLTemperatureScaler_13__SHIFT 0x10 +#define PM_FUSES_7__LPMLTemperatureScaler_12_MASK 0xff000000 +#define PM_FUSES_7__LPMLTemperatureScaler_12__SHIFT 0x18 +#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta_MASK 0xffff +#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0 +#define PM_FUSES_8__FuzzyFan_ErrorSetDelta_MASK 0xffff0000 +#define PM_FUSES_8__FuzzyFan_ErrorSetDelta__SHIFT 0x10 +#define PM_FUSES_9__Reserved6_MASK 0xffff +#define PM_FUSES_9__Reserved6__SHIFT 0x0 +#define PM_FUSES_9__FuzzyFan_PwmSetDelta_MASK 0xffff0000 +#define PM_FUSES_9__FuzzyFan_PwmSetDelta__SHIFT 0x10 +#define PM_FUSES_10__GnbLPML_3_MASK 0xff +#define PM_FUSES_10__GnbLPML_3__SHIFT 0x0 +#define PM_FUSES_10__GnbLPML_2_MASK 0xff00 +#define PM_FUSES_10__GnbLPML_2__SHIFT 0x8 +#define PM_FUSES_10__GnbLPML_1_MASK 0xff0000 +#define PM_FUSES_10__GnbLPML_1__SHIFT 0x10 +#define PM_FUSES_10__GnbLPML_0_MASK 0xff000000 +#define PM_FUSES_10__GnbLPML_0__SHIFT 0x18 +#define PM_FUSES_11__GnbLPML_7_MASK 0xff +#define PM_FUSES_11__GnbLPML_7__SHIFT 0x0 +#define PM_FUSES_11__GnbLPML_6_MASK 0xff00 +#define PM_FUSES_11__GnbLPML_6__SHIFT 0x8 +#define PM_FUSES_11__GnbLPML_5_MASK 0xff0000 +#define PM_FUSES_11__GnbLPML_5__SHIFT 0x10 +#define PM_FUSES_11__GnbLPML_4_MASK 0xff000000 +#define PM_FUSES_11__GnbLPML_4__SHIFT 0x18 +#define PM_FUSES_12__GnbLPML_11_MASK 0xff +#define PM_FUSES_12__GnbLPML_11__SHIFT 0x0 +#define PM_FUSES_12__GnbLPML_10_MASK 0xff00 +#define PM_FUSES_12__GnbLPML_10__SHIFT 0x8 +#define PM_FUSES_12__GnbLPML_9_MASK 0xff0000 +#define PM_FUSES_12__GnbLPML_9__SHIFT 0x10 +#define PM_FUSES_12__GnbLPML_8_MASK 0xff000000 +#define PM_FUSES_12__GnbLPML_8__SHIFT 0x18 +#define PM_FUSES_13__GnbLPML_15_MASK 0xff +#define PM_FUSES_13__GnbLPML_15__SHIFT 0x0 +#define PM_FUSES_13__GnbLPML_14_MASK 0xff00 +#define PM_FUSES_13__GnbLPML_14__SHIFT 0x8 +#define PM_FUSES_13__GnbLPML_13_MASK 0xff0000 +#define PM_FUSES_13__GnbLPML_13__SHIFT 0x10 +#define PM_FUSES_13__GnbLPML_12_MASK 0xff000000 +#define PM_FUSES_13__GnbLPML_12__SHIFT 0x18 +#define PM_FUSES_14__Reserved1_1_MASK 0xff +#define PM_FUSES_14__Reserved1_1__SHIFT 0x0 +#define PM_FUSES_14__Reserved1_0_MASK 0xff00 +#define PM_FUSES_14__Reserved1_0__SHIFT 0x8 +#define PM_FUSES_14__GnbLPMLMinVid_MASK 0xff0000 +#define PM_FUSES_14__GnbLPMLMinVid__SHIFT 0x10 +#define PM_FUSES_14__GnbLPMLMaxVid_MASK 0xff000000 +#define PM_FUSES_14__GnbLPMLMaxVid__SHIFT 0x18 +#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd_MASK 0xffff +#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd__SHIFT 0x0 +#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000 +#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd__SHIFT 0x10 +#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_52__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0 +#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8 +#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3 +#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0 +#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4 +#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000 +#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe +#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000 +#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19 +#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000 +#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a +#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff +#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 +#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000 +#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11 +#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000 +#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12 +#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff +#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0 +#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00 +#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8 +#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000 +#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10 +#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000 +#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18 +#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf +#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 +#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x1f0 +#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 +#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000 +#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 +#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff +#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 +#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff +#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 +#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00 +#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL1__M_MASK 0xff0000 +#define CG_FDO_CTRL1__M__SHIFT 0x10 +#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000 +#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 +#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000 +#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e +#define CG_FDO_CTRL2__TMIN_MASK 0xff +#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 +#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800 +#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb +#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000 +#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe +#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000 +#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 +#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7 +#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 +#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8 +#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 +#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff +#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 +#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe +#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1 +#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00 +#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11 +#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000 +#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12 +#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000 +#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18 +#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000 +#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19 +#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000 +#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a +#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000 +#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b +#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000 +#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c +#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000 +#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d +#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000 +#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_INT_DATA__Z_MASK 0x7ff +#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON0_INT_DATA__VALID_MASK 0x800 +#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_INT_DATA__Z_MASK 0x7ff +#define THM_TMON1_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON1_INT_DATA__VALID_MASK 0x800 +#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON1_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 +#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5 +#define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f +#define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0 +#define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20 +#define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5 +#define THM_TMON1_STATUS__CURRENT_RDI_MASK 0x1f +#define THM_TMON1_STATUS__CURRENT_RDI__SHIFT 0x0 +#define THM_TMON1_STATUS__MEAS_DONE_MASK 0x20 +#define THM_TMON1_STATUS__MEAS_DONE__SHIFT 0x5 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1 +#define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0 +#define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff +#define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf +#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 +#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 +#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 +#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 +#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 +#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf +#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 +#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define PWR_CKS_ENABLE__STRETCH_ENABLE_MASK 0x1 +#define PWR_CKS_ENABLE__STRETCH_ENABLE__SHIFT 0x0 +#define PWR_CKS_ENABLE__masterReset_MASK 0x2 +#define PWR_CKS_ENABLE__masterReset__SHIFT 0x1 +#define PWR_CKS_ENABLE__staticEnable_MASK 0x4 +#define PWR_CKS_ENABLE__staticEnable__SHIFT 0x2 +#define PWR_CKS_CNTL__CKS_BYPASS_MASK 0x1 +#define PWR_CKS_CNTL__CKS_BYPASS__SHIFT 0x0 +#define PWR_CKS_CNTL__CKS_PCCEnable_MASK 0x2 +#define PWR_CKS_CNTL__CKS_PCCEnable__SHIFT 0x1 +#define PWR_CKS_CNTL__CKS_TEMP_COMP_MASK 0x4 +#define PWR_CKS_CNTL__CKS_TEMP_COMP__SHIFT 0x2 +#define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT_MASK 0x78 +#define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT__SHIFT 0x3 +#define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS_MASK 0x80 +#define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS__SHIFT 0x7 +#define PWR_CKS_CNTL__CKS_SAMPLE_SIZE_MASK 0xf00 +#define PWR_CKS_CNTL__CKS_SAMPLE_SIZE__SHIFT 0x8 +#define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES_MASK 0xf000 +#define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES__SHIFT 0xc +#define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ_MASK 0x10000 +#define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ__SHIFT 0x10 +#define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP_MASK 0x20000 +#define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP__SHIFT 0x11 +#define PWR_CKS_CNTL__CKS_LDO_REFSEL_MASK 0x3c0000 +#define PWR_CKS_CNTL__CKS_LDO_REFSEL__SHIFT 0x12 +#define PWR_CKS_CNTL__DDT_DEBUS_SEL_MASK 0x400000 +#define PWR_CKS_CNTL__DDT_DEBUS_SEL__SHIFT 0x16 +#define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL_MASK 0x7f800000 +#define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL__SHIFT 0x17 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x4 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x4 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 +#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff +#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2 +#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1 +#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4 +#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10 +#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000 +#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a +#define ROM_STATUS__ROM_BUSY_MASK 0x1 +#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf +#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define ROM_INDEX__ROM_INDEX_MASK 0xffffff +#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 +#define ROM_DATA__ROM_DATA_MASK 0xffffffff +#define ROM_DATA__ROM_DATA__SHIFT 0x0 +#define ROM_START__ROM_START_MASK 0xffffff +#define ROM_START__ROM_START__SHIFT 0x0 +#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff +#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 +#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000 +#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 +#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1 +#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 +#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 + +#endif /* SMU_7_1_2_SH_MASK_H */ -- cgit v1.2.3 From 47e6898750169db73219f77fbe467ddacd5aabda Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:32:09 -0400 Subject: drm/amdgpu: add SMU 8.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the SMU (System Management Unit) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h | 671 +++++ .../drm/amd/include/asic_reg/smu/smu_8_0_enum.h | 1072 +++++++ .../drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h | 2964 ++++++++++++++++++++ 3 files changed, 4707 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h new file mode 100644 index 000000000000..b404815ab2c4 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h @@ -0,0 +1,671 @@ +/* + * SMU_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_8_0_D_H +#define SMU_8_0_D_H + +#define ixTHM_TCON_CSR_CONFIG 0xd82014a4 +#define ixTHM_TCON_CSR_DATA 0xd82014a8 +#define ixTHM_TCON_HTC 0xd8200c64 +#define ixTHM_TCON_CUR_TMP 0xd8200ca4 +#define ixTHM_TCON_THERM_TRIP 0xd8200ce4 +#define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00 +#define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04 +#define ixTHM_THERMAL_INT_ENA 0xd8200d10 +#define ixTHM_THERMAL_INT_CTRL 0xd8200d14 +#define ixTHM_THERMAL_INT_STATUS 0xd8200d18 +#define ixTMON0_RDIL0_DATA 0xd8202000 +#define ixTMON0_RDIL1_DATA 0xd8202004 +#define ixTMON0_RDIL2_DATA 0xd8202008 +#define ixTMON0_RDIL3_DATA 0xd820200c +#define ixTMON0_RDIL4_DATA 0xd8202010 +#define ixTMON0_RDIL5_DATA 0xd8202014 +#define ixTMON0_RDIL6_DATA 0xd8202018 +#define ixTMON0_RDIL7_DATA 0xd820201c +#define ixTMON0_RDIL8_DATA 0xd8202020 +#define ixTMON0_RDIL9_DATA 0xd8202024 +#define ixTMON0_RDIL10_DATA 0xd8202028 +#define ixTMON0_RDIL11_DATA 0xd820202c +#define ixTMON0_RDIL12_DATA 0xd8202030 +#define ixTMON0_RDIL13_DATA 0xd8202034 +#define ixTMON0_RDIL14_DATA 0xd8202038 +#define ixTMON0_RDIL15_DATA 0xd820203c +#define ixTMON0_RDIR0_DATA 0xd8202040 +#define ixTMON0_RDIR1_DATA 0xd8202044 +#define ixTMON0_RDIR2_DATA 0xd8202048 +#define ixTMON0_RDIR3_DATA 0xd820204c +#define ixTMON0_RDIR4_DATA 0xd8202050 +#define ixTMON0_RDIR5_DATA 0xd8202054 +#define ixTMON0_RDIR6_DATA 0xd8202058 +#define ixTMON0_RDIR7_DATA 0xd820205c +#define ixTMON0_RDIR8_DATA 0xd8202060 +#define ixTMON0_RDIR9_DATA 0xd8202064 +#define ixTMON0_RDIR10_DATA 0xd8202068 +#define ixTMON0_RDIR11_DATA 0xd820206c +#define ixTMON0_RDIR12_DATA 0xd8202070 +#define ixTMON0_RDIR13_DATA 0xd8202074 +#define ixTMON0_RDIR14_DATA 0xd8202078 +#define ixTMON0_RDIR15_DATA 0xd820207c +#define ixTMON0_INT_DATA 0xd8202080 +#define ixTMON0_RDIL_PRESENT0 0xd8202084 +#define ixTMON0_RDIL_PRESENT1 0xd8202088 +#define ixTMON0_RDIR_PRESENT0 0xd820208c +#define ixTMON0_RDIR_PRESENT1 0xd8202090 +#define ixTMON0_CONFIG 0xd8202098 +#define ixTMON0_TEMP_CALC_COEFF0 0xd82020a0 +#define ixTMON0_TEMP_CALC_COEFF1 0xd82020a4 +#define ixTMON0_TEMP_CALC_COEFF2 0xd82020a8 +#define ixTMON0_TEMP_CALC_COEFF3 0xd82020ac +#define ixTMON0_TEMP_CALC_COEFF4 0xd82020b0 +#define ixTMON0_DEBUG0 0xd82020b4 +#define ixTMON0_DEBUG1 0xd82020b8 +#define ixTMON1_RDIL0_DATA 0xd8202100 +#define ixTMON1_RDIL1_DATA 0xd8202104 +#define ixTMON1_RDIL2_DATA 0xd8202108 +#define ixTMON1_RDIL3_DATA 0xd820210c +#define ixTMON1_RDIL4_DATA 0xd8202110 +#define ixTMON1_RDIL5_DATA 0xd8202114 +#define ixTMON1_RDIL6_DATA 0xd8202118 +#define ixTMON1_RDIL7_DATA 0xd820211c +#define ixTMON1_RDIL8_DATA 0xd8202120 +#define ixTMON1_RDIL9_DATA 0xd8202124 +#define ixTMON1_RDIL10_DATA 0xd8202128 +#define ixTMON1_RDIL11_DATA 0xd820212c +#define ixTMON1_RDIL12_DATA 0xd8202130 +#define ixTMON1_RDIL13_DATA 0xd8202134 +#define ixTMON1_RDIL14_DATA 0xd8202138 +#define ixTMON1_RDIL15_DATA 0xd820213c +#define ixTMON1_RDIR0_DATA 0xd8202140 +#define ixTMON1_RDIR1_DATA 0xd8202144 +#define ixTMON1_RDIR2_DATA 0xd8202148 +#define ixTMON1_RDIR3_DATA 0xd820214c +#define ixTMON1_RDIR4_DATA 0xd8202150 +#define ixTMON1_RDIR5_DATA 0xd8202154 +#define ixTMON1_RDIR6_DATA 0xd8202158 +#define ixTMON1_RDIR7_DATA 0xd820215c +#define ixTMON1_RDIR8_DATA 0xd8202160 +#define ixTMON1_RDIR9_DATA 0xd8202164 +#define ixTMON1_RDIR10_DATA 0xd8202168 +#define ixTMON1_RDIR11_DATA 0xd820216c +#define ixTMON1_RDIR12_DATA 0xd8202170 +#define ixTMON1_RDIR13_DATA 0xd8202174 +#define ixTMON1_RDIR14_DATA 0xd8202178 +#define ixTMON1_RDIR15_DATA 0xd820217c +#define ixTMON1_INT_DATA 0xd8202180 +#define ixTMON1_RDIL_PRESENT0 0xd8202184 +#define ixTMON1_RDIL_PRESENT1 0xd8202188 +#define ixTMON1_RDIR_PRESENT0 0xd820218c +#define ixTMON1_RDIR_PRESENT1 0xd8202190 +#define ixTMON1_CONFIG 0xd8202198 +#define ixTMON1_TEMP_CALC_COEFF0 0xd82021a0 +#define ixTMON1_TEMP_CALC_COEFF1 0xd82021a4 +#define ixTMON1_TEMP_CALC_COEFF2 0xd82021a8 +#define ixTMON1_TEMP_CALC_COEFF3 0xd82021ac +#define ixTMON1_TEMP_CALC_COEFF4 0xd82021b0 +#define ixTMON1_DEBUG0 0xd82021b4 +#define ixTMON1_DEBUG1 0xd82021b8 +#define ixTHM_TMON0_REMOTE_START 0xd8202800 +#define ixTHM_TMON0_REMOTE_END 0xd82028fc +#define ixTHM_TMON1_REMOTE_START 0xd8202900 +#define ixTHM_TMON1_REMOTE_END 0xd82029fc +#define ixTHM_TCON_LOCAL0 0xd8202e00 +#define ixTHM_TCON_LOCAL1 0xd8202e04 +#define ixTHM_TCON_LOCAL2 0xd8202e08 +#define ixTHM_TCON_LOCAL3 0xd8202e0c +#define ixTHM_TCON_LOCAL4 0xd8202e10 +#define ixTHM_TCON_LOCAL5 0xd8202e14 +#define ixTHM_TCON_LOCAL6 0xd8202e18 +#define ixTHM_TCON_LOCAL7 0xd8202e1c +#define ixTHM_TCON_LOCAL8 0xd8202e20 +#define ixTHM_TCON_LOCAL9 0xd8202e24 +#define ixTHM_TCON_LOCAL10 0xd8202e28 +#define ixTHM_TCON_LOCAL11 0xd8202e2c +#define ixTHM_TCON_LOCAL12 0xd8202e30 +#define ixTHM_TCON_LOCAL13 0xd8202ef8 +#define ixTHM_TCON_LOCAL14 0xd8202efc +#define ixTHM_FUSE0 0xd8210000 +#define ixTHM_FUSE1 0xd8210004 +#define ixTHM_FUSE2 0xd8210008 +#define ixTHM_FUSE3 0xd821000c +#define ixTHM_FUSE4 0xd8210010 +#define ixTHM_FUSE5 0xd8210014 +#define ixTHM_FUSE6 0xd8210018 +#define ixTHM_FUSE7 0xd821001c +#define ixTHM_FUSE8 0xd8210020 +#define ixTHM_FUSE9 0xd8210024 +#define ixTHM_FUSE10 0xd8210028 +#define ixTHM_FUSE11 0xd821002c +#define ixTHM_FUSE12 0xd8210030 +#define mmMP0PUB_IND_INDEX 0x180 +#define mmMP_SMUIF0_MP0PUB_IND_INDEX 0x180 +#define mmMP_SMUIF1_MP0PUB_IND_INDEX 0x182 +#define mmMP_SMUIF2_MP0PUB_IND_INDEX 0x184 +#define mmMP_SMUIF3_MP0PUB_IND_INDEX 0x186 +#define mmMP_SMUIF4_MP0PUB_IND_INDEX 0x188 +#define mmMP_SMUIF5_MP0PUB_IND_INDEX 0x18a +#define mmMP_SMUIF6_MP0PUB_IND_INDEX 0x18c +#define mmMP_SMUIF7_MP0PUB_IND_INDEX 0x18e +#define mmMP_SMUIF8_MP0PUB_IND_INDEX 0x190 +#define mmMP_SMUIF9_MP0PUB_IND_INDEX 0x192 +#define mmMP_SMUIF10_MP0PUB_IND_INDEX 0x194 +#define mmMP_SMUIF11_MP0PUB_IND_INDEX 0x196 +#define mmMP_SMUIF12_MP0PUB_IND_INDEX 0x198 +#define mmMP_SMUIF13_MP0PUB_IND_INDEX 0x19a +#define mmMP_SMUIF14_MP0PUB_IND_INDEX 0x19c +#define mmMP_SMUIF15_MP0PUB_IND_INDEX 0x19e +#define mmMP0PUB_IND_DATA 0x181 +#define mmMP_SMUIF0_MP0PUB_IND_DATA 0x181 +#define mmMP_SMUIF1_MP0PUB_IND_DATA 0x183 +#define mmMP_SMUIF2_MP0PUB_IND_DATA 0x185 +#define mmMP_SMUIF3_MP0PUB_IND_DATA 0x187 +#define mmMP_SMUIF4_MP0PUB_IND_DATA 0x189 +#define mmMP_SMUIF5_MP0PUB_IND_DATA 0x18b +#define mmMP_SMUIF6_MP0PUB_IND_DATA 0x18d +#define mmMP_SMUIF7_MP0PUB_IND_DATA 0x18f +#define mmMP_SMUIF8_MP0PUB_IND_DATA 0x191 +#define mmMP_SMUIF9_MP0PUB_IND_DATA 0x193 +#define mmMP_SMUIF10_MP0PUB_IND_DATA 0x195 +#define mmMP_SMUIF11_MP0PUB_IND_DATA 0x197 +#define mmMP_SMUIF12_MP0PUB_IND_DATA 0x199 +#define mmMP_SMUIF13_MP0PUB_IND_DATA 0x19b +#define mmMP_SMUIF14_MP0PUB_IND_DATA 0x19d +#define mmMP_SMUIF15_MP0PUB_IND_DATA 0x19f +#define mmMP0PUB_IND_INDEX_0 0x180 +#define mmMP0PUB_IND_DATA_0 0x181 +#define mmMP0PUB_IND_INDEX_1 0x182 +#define mmMP0PUB_IND_DATA_1 0x183 +#define mmMP0PUB_IND_INDEX_2 0x184 +#define mmMP0PUB_IND_DATA_2 0x185 +#define mmMP0PUB_IND_INDEX_3 0x186 +#define mmMP0PUB_IND_DATA_3 0x187 +#define mmMP0PUB_IND_INDEX_4 0x188 +#define mmMP0PUB_IND_DATA_4 0x189 +#define mmMP0PUB_IND_INDEX_5 0x18a +#define mmMP0PUB_IND_DATA_5 0x18b +#define mmMP0PUB_IND_INDEX_6 0x18c +#define mmMP0PUB_IND_DATA_6 0x18d +#define mmMP0PUB_IND_INDEX_7 0x18e +#define mmMP0PUB_IND_DATA_7 0x18f +#define mmMP0PUB_IND_INDEX_8 0x190 +#define mmMP0PUB_IND_DATA_8 0x191 +#define mmMP0PUB_IND_INDEX_9 0x192 +#define mmMP0PUB_IND_DATA_9 0x193 +#define mmMP0PUB_IND_INDEX_10 0x194 +#define mmMP0PUB_IND_DATA_10 0x195 +#define mmMP0PUB_IND_INDEX_11 0x196 +#define mmMP0PUB_IND_DATA_11 0x197 +#define mmMP0PUB_IND_INDEX_12 0x198 +#define mmMP0PUB_IND_DATA_12 0x199 +#define mmMP0PUB_IND_INDEX_13 0x19a +#define mmMP0PUB_IND_DATA_13 0x19b +#define mmMP0PUB_IND_INDEX_14 0x19c +#define mmMP0PUB_IND_DATA_14 0x19d +#define mmMP0PUB_IND_INDEX_15 0x19e +#define mmMP0PUB_IND_DATA_15 0x19f +#define mmMP0_IND_ACCESS_CNTL 0x1a0 +#define mmMP0_MSP_MESSAGE_0 0x1a1 +#define mmMP0_MSP_MESSAGE_1 0x1a2 +#define mmMP0_MSP_MESSAGE_2 0x1a3 +#define mmMP0_MSP_MESSAGE_3 0x1a4 +#define mmMP0_MSP_MESSAGE_4 0x1a5 +#define mmMP0_MSP_MESSAGE_5 0x1a6 +#define mmMP0_MSP_MESSAGE_6 0x1a7 +#define mmMP0_MSP_MESSAGE_7 0x1a8 +#define mmSAM_IH_EXT_ERR_INTR 0x1a9 +#define mmSAM_IH_EXT_ERR_INTR_STATUS 0x1aa +#define mmMP0_DISP_TIMER0_CTRL0 0x1ab +#define mmMP0_DISP_TIMER0_CTRL1 0x1ac +#define mmMP0_DISP_TIMER0_CMP_AUTOINC 0x1ad +#define mmMP0_DISP_TIMER0_INTEN 0x1ae +#define mmMP0_DISP_TIMER0_OCMP_0_0 0x1af +#define mmMP0_DISP_TIMER0_OCMP_0_1 0x1b0 +#define mmMP0_DISP_TIMER0_CNT 0x1b1 +#define mmMP0_DISP_TIMER1_CTRL0 0x1b2 +#define mmMP0_DISP_TIMER1_CTRL1 0x1b3 +#define mmMP0_DISP_TIMER1_CMP_AUTOINC 0x1b4 +#define mmMP0_DISP_TIMER1_INTEN 0x1b5 +#define mmMP0_DISP_TIMER1_OCMP_0_0 0x1b6 +#define mmMP0_DISP_TIMER1_OCMP_0_1 0x1b7 +#define mmMP0_DISP_TIMER1_CNT 0x1b8 +#define mmSMU_MP1_SRBM2P_MSG_0 0x1c0 +#define mmSMU_MP1_SRBM2P_MSG_1 0x1c1 +#define mmSMU_MP1_SRBM2P_MSG_2 0x1c2 +#define mmSMU_MP1_SRBM2P_MSG_3 0x1c3 +#define mmSMU_MP1_SRBM2P_MSG_4 0x1c4 +#define mmSMU_MP1_SRBM2P_MSG_5 0x1c5 +#define mmSMU_MP1_SRBM2P_MSG_6 0x1c6 +#define mmSMU_MP1_SRBM2P_MSG_7 0x1c7 +#define mmSMU_MP1_SRBM2P_MSG_8 0x1c8 +#define mmSMU_MP1_SRBM2P_MSG_9 0x1c9 +#define mmSMU_MP1_SRBM2P_MSG_10 0x1ca +#define mmSMU_MP1_SRBM2P_MSG_11 0x1cb +#define mmSMU_MP1_SRBM2P_MSG_12 0x1cc +#define mmSMU_MP1_SRBM2P_MSG_13 0x1cd +#define mmSMU_MP1_SRBM2P_MSG_14 0x1ce +#define mmSMU_MP1_SRBM2P_MSG_15 0x1cf +#define mmSMU_MP1_SRBM2P_RESP_0 0x1d0 +#define mmSMU_MP1_SRBM2P_RESP_1 0x1d1 +#define mmSMU_MP1_SRBM2P_RESP_2 0x1d2 +#define mmSMU_MP1_SRBM2P_RESP_3 0x1d3 +#define mmSMU_MP1_SRBM2P_RESP_4 0x1d4 +#define mmSMU_MP1_SRBM2P_RESP_5 0x1d5 +#define mmSMU_MP1_SRBM2P_RESP_6 0x1d6 +#define mmSMU_MP1_SRBM2P_RESP_7 0x1d7 +#define mmSMU_MP1_SRBM2P_RESP_8 0x1d8 +#define mmSMU_MP1_SRBM2P_RESP_9 0x1d9 +#define mmSMU_MP1_SRBM2P_RESP_10 0x1da +#define mmSMU_MP1_SRBM2P_RESP_11 0x1db +#define mmSMU_MP1_SRBM2P_RESP_12 0x1dc +#define mmSMU_MP1_SRBM2P_RESP_13 0x1dd +#define mmSMU_MP1_SRBM2P_RESP_14 0x1de +#define mmSMU_MP1_SRBM2P_RESP_15 0x1df +#define mmSMU_MP1_SRBM2P_ARG_0 0x1e0 +#define mmSMU_MP1_SRBM2P_ARG_1 0x1e1 +#define mmSMU_MP1_SRBM2P_ARG_2 0x1e2 +#define mmSMU_MP1_SRBM2P_ARG_3 0x1e3 +#define mmSMU_MP1_SRBM2P_ARG_4 0x1e4 +#define mmSMU_MP1_SRBM2P_ARG_5 0x1e5 +#define mmSMU_MP1_SRBM2P_ARG_6 0x1e6 +#define mmSMU_MP1_SRBM2P_ARG_7 0x1e7 +#define mmSMU_MP1_SRBM2P_ARG_8 0x1e8 +#define mmSMU_MP1_SRBM2P_ARG_9 0x1e9 +#define mmSMU_MP1_SRBM2P_ARG_10 0x1ea +#define mmSMU_MP1_SRBM2P_ARG_11 0x1eb +#define mmSMU_MP1_SRBM2P_ARG_12 0x1ec +#define mmSMU_MP1_SRBM2P_ARG_13 0x1ed +#define mmSMU_MP1_SRBM2P_ARG_14 0x1ee +#define mmSMU_MP1_SRBM2P_ARG_15 0x1ef +#define mmSMU_MP1_ACP2MP_RESP 0x1f0 +#define mmSMU_MP1_DC2MP_RESP 0x1f1 +#define mmSMU_MP1_UVD2MP_RESP 0x1f2 +#define mmSMU_MP1_VCE2MP_RESP 0x1f3 +#define mmSMU_MP1_RLC2MP_RESP 0x1f4 +#define mmMP_FPS_CNT 0x1f5 +#define mmSMU_DISP0_TIMER_INT_CONTROL 0x1f6 +#define mmSMU_DISP1_TIMER_INT_CONTROL 0x1f7 +#define mmSMU_SRBM_CONFIG 0x1f8 +#define ixMP_FPS_CNT_XBAR 0xcf200800 +#define ixMP_SRBM_CONFIG_XBAR 0xcf200804 +#define ixMP_SRBM_CONTROL 0xcf200c00 +#define ixMP_SRBM_ACCVIO_LOG 0xcf200c04 +#define ixMP_SRBM_ACCVIO_ADDR 0xcf200c08 +#define ixMP_CRBBM_CONTROL 0xcf200c0c +#define ixMP_CRBBM_ACCVIO_LOG 0xcf200c10 +#define ixMP_CRBBM_ACCVIO_ADDR 0xcf200c14 +#define ixMP_DRAM_CNTL_WRREQ_CNTL 0xcf200000 +#define ixMP_DRAM_CNTL_WRREQ_CNTL_1 0xcf200004 +#define ixMP_DRAM_CNTL_WRREQ_LOW_ADDR 0xcf200008 +#define ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR 0xcf20000c +#define ixMP_DRAM_CNTL_WRREQ_MASK 0xcf200010 +#define ixMP_DRAM_CNTL_WRREQ_DATA_0 0xcf200014 +#define ixMP_DRAM_CNTL_WRREQ_DATA_1 0xcf200018 +#define ixMP_DRAM_CNTL_WRREQ_DATA_2 0xcf20001c +#define ixMP_DRAM_CNTL_WRREQ_DATA_3 0xcf200020 +#define ixMP_DRAM_CNTL_WRREQ_DATA_4 0xcf200024 +#define ixMP_DRAM_CNTL_WRREQ_DATA_5 0xcf200028 +#define ixMP_DRAM_CNTL_WRREQ_DATA_6 0xcf20002c +#define ixMP_DRAM_CNTL_WRREQ_DATA_7 0xcf200030 +#define ixMP_DRAM_CNTL_WRREQ_STATUS 0xcf200038 +#define ixMP_DRAM_CNTL_WRRET_STATUS_0 0xcf20003c +#define ixMP_DRAM_CNTL_RDREQ_ADDR 0xcf200040 +#define ixMP_DRAM_CNTL_RDREQ_CNTL 0xcf200044 +#define ixMP_DRAM_CNTL_RDREQ_CNTL_1 0xcf200048 +#define ixMP_DRAM_CNTL_RDRET_VALID 0xcf20004c +#define ixMP_DRAM_CNTL_RDRET_NACK 0xcf200050 +#define ixMP_DRAM_CNTL_RDRET_DATA_0 0xcf200054 +#define ixMP_DRAM_CNTL_RDRET_DATA_1 0xcf200058 +#define ixMP_DRAM_CNTL_RDRET_DATA_2 0xcf20005c +#define ixMP_DRAM_CNTL_RDRET_DATA_3 0xcf200060 +#define ixMP_DRAM_CNTL_RDRET_DATA_4 0xcf200064 +#define ixMP_DRAM_CNTL_RDRET_DATA_5 0xcf200068 +#define ixMP_DRAM_CNTL_RDRET_DATA_6 0xcf20006c +#define ixMP_DRAM_CNTL_RDRET_DATA_7 0xcf200070 +#define ixMP_DRAM_CNTL_RDRET_DATA_8 0xcf200074 +#define ixMP_DRAM_CNTL_RDRET_DATA_9 0xcf200078 +#define ixMP_DRAM_CNTL_RDRET_DATA_10 0xcf20007c +#define ixMP_DRAM_CNTL_RDRET_DATA_11 0xcf200080 +#define ixMP_DRAM_CNTL_RDRET_DATA_12 0xcf200084 +#define ixMP_DRAM_CNTL_RDRET_DATA_13 0xcf200088 +#define ixMP_DRAM_CNTL_RDRET_DATA_14 0xcf20008c +#define ixMP_DRAM_CNTL_RDRET_DATA_15 0xcf200090 +#define ixMP_DRAM_CNTL_RDRET_DATA_16 0xcf200094 +#define ixMP_DRAM_CNTL_RDRET_DATA_17 0xcf200098 +#define ixMP_DRAM_CNTL_RDRET_DATA_18 0xcf20009c +#define ixMP_DRAM_CNTL_RDRET_DATA_19 0xcf2000a0 +#define ixMP_DRAM_CNTL_RDRET_DATA_20 0xcf2000a4 +#define ixMP_DRAM_CNTL_RDRET_DATA_21 0xcf2000a8 +#define ixMP_DRAM_CNTL_RDRET_DATA_22 0xcf2000ac +#define ixMP_DRAM_CNTL_RDRET_DATA_23 0xcf2000b0 +#define ixMP_DRAM_CNTL_RDRET_DATA_24 0xcf2000b4 +#define ixMP_DRAM_CNTL_RDRET_DATA_25 0xcf2000b8 +#define ixMP_DRAM_CNTL_RDRET_DATA_26 0xcf2000bc +#define ixMP_DRAM_CNTL_RDRET_DATA_27 0xcf2000c0 +#define ixMP_DRAM_CNTL_RDRET_DATA_28 0xcf2000c4 +#define ixMP_DRAM_CNTL_RDRET_DATA_29 0xcf2000c8 +#define ixMP_DRAM_CNTL_RDRET_DATA_30 0xcf2000cc +#define ixMP_DRAM_CNTL_RDRET_DATA_31 0xcf2000d0 +#define ixMP_DRAM_CNTL_RDRET_DATA_32 0xcf2000d4 +#define ixMP_DRAM_CNTL_RDRET_DATA_33 0xcf2000d8 +#define ixMP_DRAM_CNTL_RDRET_DATA_34 0xcf2000dc +#define ixMP_DRAM_CNTL_RDRET_DATA_35 0xcf2000e0 +#define ixMP_DRAM_CNTL_RDRET_DATA_36 0xcf2000e4 +#define ixMP_DRAM_CNTL_RDRET_DATA_37 0xcf2000e8 +#define ixMP_DRAM_CNTL_RDRET_DATA_38 0xcf2000ec +#define ixMP_DRAM_CNTL_RDRET_DATA_39 0xcf2000f0 +#define ixMP_DRAM_CNTL_RDRET_DATA_40 0xcf2000f4 +#define ixMP_DRAM_CNTL_RDRET_DATA_41 0xcf2000f8 +#define ixMP_DRAM_CNTL_RDRET_DATA_42 0xcf2000fc +#define ixMP_DRAM_CNTL_RDRET_DATA_43 0xcf200100 +#define ixMP_DRAM_CNTL_RDRET_DATA_44 0xcf200104 +#define ixMP_DRAM_CNTL_RDRET_DATA_45 0xcf200108 +#define ixMP_DRAM_CNTL_RDRET_DATA_46 0xcf20010c +#define ixMP_DRAM_CNTL_RDRET_DATA_47 0xcf200110 +#define ixMP_DRAM_CNTL_RDRET_DATA_48 0xcf200114 +#define ixMP_DRAM_CNTL_RDRET_DATA_49 0xcf200118 +#define ixMP_DRAM_CNTL_RDRET_DATA_50 0xcf20011c +#define ixMP_DRAM_CNTL_RDRET_DATA_51 0xcf200120 +#define ixMP_DRAM_CNTL_RDRET_DATA_52 0xcf200124 +#define ixMP_DRAM_CNTL_RDRET_DATA_53 0xcf200128 +#define ixMP_DRAM_CNTL_RDRET_DATA_54 0xcf20012c +#define ixMP_DRAM_CNTL_RDRET_DATA_55 0xcf200130 +#define ixMP_DRAM_CNTL_RDRET_DATA_56 0xcf200134 +#define ixMP_DRAM_CNTL_RDRET_DATA_57 0xcf200138 +#define ixMP_DRAM_CNTL_RDRET_DATA_58 0xcf20013c +#define ixMP_DRAM_CNTL_RDRET_DATA_59 0xcf200140 +#define ixMP_DRAM_CNTL_RDRET_DATA_60 0xcf200144 +#define ixMP_DRAM_CNTL_RDRET_DATA_61 0xcf200148 +#define ixMP_DRAM_CNTL_RDRET_DATA_62 0xcf20014c +#define ixMP_DRAM_CNTL_RDRET_DATA_63 0xcf200150 +#define ixMP_IOC_CTRL 0xcf100000 +#define ixMP_IOC_RDDATA 0xcf100004 +#define ixMP_IOC_PHASE1 0xcf100008 +#define ixMP_IOC_PHASE2 0xcf10000c +#define ixMP_IOC_PHASE3 0xcf100010 +#define ixMP_IOC_READ_0 0xcf100024 +#define ixMP_IOC_READ_1 0xcf100028 +#define ixMP_IOC_READ_2 0xcf10002c +#define ixMP_IOC_READ_3 0xcf100030 +#define ixMP_IOC_READ_4 0xcf100034 +#define ixMP_IOC_READ_5 0xcf100038 +#define ixMP_IOC_READ_6 0xcf10003c +#define ixMP_IOC_READ_7 0xcf100040 +#define ixMP_IOC_READ_8 0xcf100044 +#define ixMP_IOC_READ_9 0xcf100048 +#define ixMP_IOC_READ_10 0xcf10004c +#define ixMP_IOC_READ_11 0xcf100050 +#define ixMP_IOC_READ_12 0xcf100054 +#define ixMP_IOC_READ_13 0xcf100058 +#define ixMP_IOC_READ_14 0xcf10005c +#define ixMP_IOC_READ_15 0xcf100060 +#define ixMP_IOC_WRITE_0 0xcf100064 +#define ixMP_IOC_WRITE_1 0xcf100068 +#define ixMP_IOC_WRITE_2 0xcf10006c +#define ixMP_IOC_WRITE_3 0xcf100070 +#define ixMP_IOC_WRITE_4 0xcf100074 +#define ixMP_IOC_WRITE_5 0xcf100078 +#define ixMP_IOC_WRITE_6 0xcf10007c +#define ixMP_IOC_WRITE_7 0xcf100080 +#define ixMP_IOC_WRITE_8 0xcf100084 +#define ixMP_IOC_WRITE_9 0xcf100088 +#define ixMP_IOC_WRITE_10 0xcf10008c +#define ixMP_IOC_WRITE_11 0xcf100090 +#define ixMP_IOC_WRITE_12 0xcf100094 +#define ixMP_IOC_WRITE_13 0xcf100098 +#define ixMP_IOC_WRITE_14 0xcf10009c +#define ixMP_IOC_WRITE_15 0xcf1000a0 +#define ixMP_INTERRUPT_CONTROL 0xcf200400 +#define ixMP0_SW_INT 0xcf200404 +#define ixMP0_SW_INT_CTXID 0xcf200408 +#define ixMP1_SW_INT 0xcf20040c +#define ixMP1_SW_INT_CTXID 0xcf200410 +#define ixDISP_TIMER_ID 0xcf200414 +#define mmPWRHW_SMC_IND_INDEX 0x180 +#define mmPWRHW0_PWRHW_SMC_IND_INDEX 0x180 +#define mmPWRHW1_PWRHW_SMC_IND_INDEX 0x182 +#define mmPWRHW2_PWRHW_SMC_IND_INDEX 0x184 +#define mmPWRHW3_PWRHW_SMC_IND_INDEX 0x186 +#define mmPWRHW_SMC_IND_DATA 0x181 +#define mmPWRHW0_PWRHW_SMC_IND_DATA 0x181 +#define mmPWRHW1_PWRHW_SMC_IND_DATA 0x183 +#define mmPWRHW2_PWRHW_SMC_IND_DATA 0x185 +#define mmPWRHW3_PWRHW_SMC_IND_DATA 0x187 +#define ixCURRENT_STATE_CPU0 0xd0210000 +#define ixCURRENT_STATE_CPU1 0xd0210010 +#define ixCPU_REDUN_DONE0 0xd0210004 +#define ixCPU_REDUN_DONE1 0xd0210014 +#define ixCURRENT_VID_CPU0 0xd0210008 +#define ixCURRENT_VID_CPU1 0xd0210018 +#define ixUNBPM_PWRMGT_ACK 0xd0211000 +#define ixCURRENT_FREQ_STATE_NB 0xd0211004 +#define ixCURRENT_PSTATE_NB 0xd0211008 +#define ixUNBPM_MSG_INT_CONFIG 0xd021100c +#define ixUNBPM_NBPWRMGT_CMD 0xd0211010 +#define ixUNBPM_NBPWRMGT_FSM_CFG 0xd0211014 +#define ixDDR0_FUSE_SSB_XFER 0xd0211018 +#define ixDDR0_FUSE_SSB_XFER_CFG 0xd021101c +#define ixDDR1_FUSE_SSB_XFER 0xd0211020 +#define ixDDR1_FUSE_SSB_XFER_CFG 0xd0211024 +#define ixUNBPM_FUSES_VAL_PWROK 0xd0211028 +#define ixSYNFIFO_CLK_RATIO 0xd021102c +#define ixMISC_SMU_PWRMGT_CFG0 0xd0211030 +#define ixMISC_GNB_PWRMGT_CFG1 0xd0211034 +#define ixMISC_SMU_PWRMGT_CFG1 0xd0211038 +#define ixMISC_GNB_PWRMGT_DATA 0xd021103c +#define ixGN_GNB_SLOW 0xd0211040 +#define ixGN_FORCE_NBPS1 0xd0211044 +#define ixMISC_SMU_PWRMGT_DATA 0xd0211048 +#define ixNB_COF 0xd021104c +#define ixUNBPM_CK_IRESET 0xd0211050 +#define ixCURRENT_VID_NB 0xd0211054 +#define ixSPR_FUSE_PSTATEPWR1 0xd0211058 +#define ixSPR_FUSE_PSTATEPWR2 0xd021105c +#define ixSPR_FUSE_PSTATEPWR3 0xd0211060 +#define ixSPR_FUSE_THERMAL_SCRATCH 0xd0211064 +#define ixSPR_PRODUCT_INFO0 0xd0211068 +#define ixSPR_SERIALNUM_REG1 0xd021106c +#define ixSPR_SERIALNUM_REG2 0xd0211070 +#define ixSPR_PRODUCT_INFO1 0xd0211074 +#define ixSPR_EXT_PRODUCT_INFO 0xd021107c +#define ixSPR_MSIDFUSE 0xd0211080 +#define ixSPR_LINK_PRODUCT_INFO 0xd0211084 +#define ixSPR_BRAND_NAME_ADDR 0xd0211088 +#define ixSPR_BRAND_NAME_DATA 0xd021108c +#define ixSPR_COMBO_PHY_PRODUCT_INFO 0xd0211090 +#define ixMISC_GNB_PWRMGT_CFG0 0xd0211094 +#define ixUNBPM_EXIT_TO_PSTATE 0xd0211098 +#define ixUNBPM_WARM_RESET_HS_STATUS 0xd021109c +#define ixUNBPM_VOLTAGE_CNTL 0xd02110a0 +#define ixUNBPM_VOLTAGE_STATUS 0xd02110a4 +#define ixNUM_BOOST_STATES 0xd02110a8 +#define ixWARM_RESET_NB_CONTROL 0xd02110ac +#define ixONION_NO_STREAMS_PEND 0xd02110b0 +#define ixSPR_PROGRAMMABLE_CTRL 0xd02110b4 +#define ixPHN_FUSERX_MISC_FUSES 0xd02110b8 +#define ixUNBPM_PWRCTRL_MISC 0xd02110bc +#define ixCSTATE_ACTIVE_SAMPLER 0xd02110c0 +#define ixUNBPM_DEBUG_CONFIG_STATUS 0xd02110c4 +#define ixUNBPM_AXIMST_LAST_CMD 0xd02110c8 +#define ixUNB_IF_INTRGEN_LAST_SENT 0xd02110cc +#define ixUNBPM_DEBUG_BUS_CNTL 0xd02110d0 +#define ixUNBPM_PWRMGT_REQ_DBG_STATUS 0xd02110d4 +#define ixUNBPM_VIDCHG_REQ_DBG_STATUS 0xd02110d8 +#define ixUNBPM_SCRATCH_0 0xd021e000 +#define ixUNBPM_SCRATCH_1 0xd021e004 +#define ixPOWERON_CPU_0 0xd0220000 +#define ixPOWERREADY_CPU_0 0xd0220004 +#define ixPGRUNFEEDBACK_CPU_0 0xd0220008 +#define ixRCC3ON_CPU_0 0xd022000c +#define ixRCC3EXITDONE_CPU_0 0xd0220010 +#define ixCORE_FUNC_LATE_SSB_XFER_0 0xd0220014 +#define ixCORE_FUNC_LATE_SSB_XFER_CFG_0 0xd0220018 +#define ixCORE_REDUN_SSB_XFER_0 0xd022001c +#define ixCORE_REDUN_SSB_XFER_CFG_0 0xd0220020 +#define ixCORE_APM_SSB_XFER_0 0xd0220024 +#define ixCORE_APM_SSB_XFER_CFG_0 0xd0220028 +#define ixCOREPM_PWRCTRL_MISC_0 0xd022002c +#define ixLDOIVRON_CPU_0 0xd0220030 +#define ixLDOIVREXITDONE_CPU_0 0xd0220034 +#define ixRCC3_TARGETPSMREF_CPU_0 0xd0220038 +#define ixIVR_TARGETPSMREF_CPU_0 0xd022003c +#define ixCK_JTCOOLRESET_LATCHED_CPU_0 0xd0220044 +#define ixCK_DISABLECORE_CPU_0 0xd0220048 +#define ixCOREPM_ID_0 0xd022004c +#define ixCOREPM_SCRATCH_0 0xd0220050 +#define ixRCC3_WAKEMIN_CPU_0 0xd0220054 +#define ixSPMI_CONFIG0_0 0xd0221000 +#define ixSPMI_CONFIG1_0 0xd0221004 +#define ixSPMI_FSM_READ_TRIGGER_0 0xd0221008 +#define ixSPMI_FSM_WRITE_TRIGGER_0 0xd022100c +#define ixSPMI_FSM_RESET_TRIGGER_0 0xd0221010 +#define ixSPMI_FSM_BUSY_0 0xd0221014 +#define ixSPMI_PATH_0 0xd0221018 +#define ixSPMI_C6_STATE_0 0xd022101c +#define ixSPMI_JTAG_OVER_0 0xd0221020 +#define ixSPMI_SRAM_ADDRESS_0 0xd0221024 +#define ixSPMI_SRAM_DATA_0 0xd0221028 +#define ixSPMI_RESET_0 0xd022102c +#define ixSPMI_FORCE_CLOCK_GATERS_0 0xd0221030 +#define ixSPMI_SPARE_0 0xd0221034 +#define ixSPMI_SPARE_EX_0 0xd0221038 +#define ixSPMI_SRAM_CLK_GATER_0 0xd022103c +#define ixPOWERON_CPU_1 0xd0230000 +#define ixPOWERREADY_CPU_1 0xd0230004 +#define ixPGRUNFEEDBACK_CPU_1 0xd0230008 +#define ixRCC3ON_CPU_1 0xd023000c +#define ixRCC3EXITDONE_CPU_1 0xd0230010 +#define ixCORE_FUNC_LATE_SSB_XFER_1 0xd0230014 +#define ixCORE_FUNC_LATE_SSB_XFER_CFG_1 0xd0230018 +#define ixCORE_REDUN_SSB_XFER_1 0xd023001c +#define ixCORE_REDUN_SSB_XFER_CFG_1 0xd0230020 +#define ixCORE_APM_SSB_XFER_1 0xd0230024 +#define ixCORE_APM_SSB_XFER_CFG_1 0xd0230028 +#define ixCOREPM_PWRCTRL_MISC_1 0xd023002c +#define ixLDOIVRON_CPU_1 0xd0230030 +#define ixLDOIVREXITDONE_CPU_1 0xd0230034 +#define ixRCC3_TARGETPSMREF_CPU_1 0xd0230038 +#define ixIVR_TARGETPSMREF_CPU_1 0xd023003c +#define ixCK_JTCOOLRESET_LATCHED_CPU_1 0xd0230044 +#define ixCK_DISABLECORE_CPU_1 0xd0230048 +#define ixCOREPM_ID_1 0xd023004c +#define ixCOREPM_SCRATCH_1 0xd0230050 +#define ixRCC3_WAKEMIN_CPU_1 0xd0230054 +#define ixSPMI_CONFIG0_1 0xd0231000 +#define ixSPMI_CONFIG1_1 0xd0231004 +#define ixSPMI_FSM_READ_TRIGGER_1 0xd0231008 +#define ixSPMI_FSM_WRITE_TRIGGER_1 0xd023100c +#define ixSPMI_FSM_RESET_TRIGGER_1 0xd0231010 +#define ixSPMI_FSM_BUSY_1 0xd0231014 +#define ixSPMI_PATH_1 0xd0231018 +#define ixSPMI_C6_STATE_1 0xd023101c +#define ixSPMI_JTAG_OVER_1 0xd0231020 +#define ixSPMI_SRAM_ADDRESS_1 0xd0231024 +#define ixSPMI_SRAM_DATA_1 0xd0231028 +#define ixSPMI_RESET_1 0xd023102c +#define ixSPMI_FORCE_CLOCK_GATERS_1 0xd0231030 +#define ixSPMI_SPARE_1 0xd0231034 +#define ixSPMI_SPARE_EX_1 0xd0231038 +#define ixSPMI_SRAM_CLK_GATER_1 0xd023103c +#define ixGENERAL_PWRMGT 0xd0200000 +#define ixCNB_PWRMGT_CNTL 0xd0200004 +#define ixSCLK_PWRMGT_CNTL 0xd0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xd0200014 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xd02000f0 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_2 0xd02000f4 +#define ixCG_FREQ_TRAN_VOTING_0 0xd02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xd02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xd02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xd02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xd02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xd02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xd02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xd02001c4 +#define ixCG_STATIC_SCREEN_PARAMETER 0xd0200044 +#define ixCG_ACPI_CNTL 0xd0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xd0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xd0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xd020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xd0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xd020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xd0200310 +#define ixSMU_VOLTAGE_STATUS 0xd0200094 +#define ixCG_ULV_PARAMETER 0xd020015c +#define ixPWR_DC_RESP 0xd0200300 +#define ixPWR_VCE_RESP 0xd0200304 +#define ixPWR_UVD_RESP 0xd0200308 +#define ixPWR_ACP_RESP 0xd020030c +#define ixPWR_DC_REQ 0xd020031c +#define ixSCLK_MIN_DIV 0xd02003ac +#define ixPCIE_PGFSM_CONFIG 0xd02002d0 +#define ixPCIE_PGFSM_WRITE 0xd02002d4 +#define ixSERDES_BUSY 0xd02002d8 +#define ixPCIE_PGFSM2_CONFIG 0xd02002dc +#define ixPCIE_PGFSM2_WRITE 0xd02002e0 +#define ixSERDES2_BUSY 0xd02002e4 +#define ixPCIE_PGFSM_0_READ 0xd02002e8 +#define ixPCIE_PGFSM_1_READ 0xd02002ec +#define ixPWR_ACPI_INTERRUPT 0xd0200318 +#define ixVDDGFX_IDLE_PARAMETER 0xd020036c +#define ixVDDGFX_IDLE_CONTROL 0xd0200370 +#define ixVDDGFX_IDLE_EXIT 0xd0200374 +#define ixREG_SCLK_DEEP_SLEEP_EXIT 0xd0200378 +#define ixCAC_WEIGHT_LKG_DC_3 0xd020803c +#define ixLCAC_MC0_CNTL 0xd0208130 +#define ixLCAC_MC0_OVR_SEL 0xd0208134 +#define ixLCAC_MC0_OVR_VAL 0xd0208138 +#define ixLCAC_MC1_CNTL 0xd020813c +#define ixLCAC_MC1_OVR_SEL 0xd0208140 +#define ixLCAC_MC1_OVR_VAL 0xd0208144 +#define ixLCAC_MC2_CNTL 0xd0208148 +#define ixLCAC_MC2_OVR_SEL 0xd020814c +#define ixLCAC_MC2_OVR_VAL 0xd0208150 +#define ixLCAC_MC3_CNTL 0xd0208154 +#define ixLCAC_MC3_OVR_SEL 0xd0208158 +#define ixLCAC_MC3_OVR_VAL 0xd020815c +#define ixLCAC_CPL_CNTL 0xd0208160 +#define ixLCAC_CPL_OVR_SEL 0xd0208164 +#define ixLCAC_CPL_OVR_VAL 0xd0208168 +#define ixMISC_UNB_PWRMGT_CFG0 0xd020c000 +#define ixMISC_UNB_PWRMGT_CFG1 0xd020c004 +#define ixMISC_UNB_PWRMGT_DATA 0xd020c00c +#define ixGNBPM_SMU_PWRMGT_DATA 0xd020c010 +#define ixDMA_ACTIVE_SAMPLER_CFG 0xd020c014 +#define ixSOUTHBRIDGE_TYPE 0xd020c01c +#define ixGNBPM_SMU_PWRMGT_STATUS 0xd020c020 +#define ixALLOW_SR_INTR_CTRL 0xd020c024 +#define mmGC_CAC_LKG_AGGR_LOWER 0x3294 +#define mmGC_CAC_LKG_AGGR_UPPER 0x3295 +#define ixGC_CAC_WEIGHT_CU_0 0x32 +#define ixGC_CAC_WEIGHT_CU_1 0x33 +#define ixGC_CAC_WEIGHT_CU_2 0x34 +#define ixGC_CAC_WEIGHT_CU_3 0x35 +#define ixGC_CAC_ACC_CU0 0xba +#define ixGC_CAC_ACC_CU1 0xbb +#define ixGC_CAC_ACC_CU2 0xbc +#define ixGC_CAC_ACC_CU3 0xbd +#define ixGC_CAC_ACC_CU4 0xbe +#define ixGC_CAC_ACC_CU5 0xbf +#define ixGC_CAC_ACC_CU6 0xc0 +#define ixGC_CAC_ACC_CU7 0xc1 +#define ixGC_CAC_OVRD_CU 0xe7 + +#endif /* SMU_8_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h new file mode 100644 index 000000000000..e1540c181bf8 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h @@ -0,0 +1,1072 @@ +/* + * SMU_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_8_0_ENUM_H +#define SMU_8_0_ENUM_H + +typedef enum DebugBlockId { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_UVDU = 0xd, + DBG_BLOCK_ID_SQA = 0xe, + DBG_BLOCK_ID_SDMA0 = 0xf, + DBG_BLOCK_ID_SDMA1 = 0x10, + DBG_BLOCK_ID_SPIM = 0x11, + DBG_BLOCK_ID_GDS = 0x12, + DBG_BLOCK_ID_VC0 = 0x13, + DBG_BLOCK_ID_VC1 = 0x14, + DBG_BLOCK_ID_PA0 = 0x15, + DBG_BLOCK_ID_PA1 = 0x16, + DBG_BLOCK_ID_CP0 = 0x17, + DBG_BLOCK_ID_CP1 = 0x18, + DBG_BLOCK_ID_CP2 = 0x19, + DBG_BLOCK_ID_XBR = 0x1a, + DBG_BLOCK_ID_UVDM = 0x1b, + DBG_BLOCK_ID_VGT0 = 0x1c, + DBG_BLOCK_ID_VGT1 = 0x1d, + DBG_BLOCK_ID_IA = 0x1e, + DBG_BLOCK_ID_SXM0 = 0x1f, + DBG_BLOCK_ID_SXM1 = 0x20, + DBG_BLOCK_ID_SCT0 = 0x21, + DBG_BLOCK_ID_SCT1 = 0x22, + DBG_BLOCK_ID_SPM0 = 0x23, + DBG_BLOCK_ID_SPM1 = 0x24, + DBG_BLOCK_ID_UNUSED0 = 0x25, + DBG_BLOCK_ID_UNUSED1 = 0x26, + DBG_BLOCK_ID_TCAA = 0x27, + DBG_BLOCK_ID_TCAB = 0x28, + DBG_BLOCK_ID_TCCA = 0x29, + DBG_BLOCK_ID_TCCB = 0x2a, + DBG_BLOCK_ID_MCC0 = 0x2b, + DBG_BLOCK_ID_MCC1 = 0x2c, + DBG_BLOCK_ID_MCC2 = 0x2d, + DBG_BLOCK_ID_MCC3 = 0x2e, + DBG_BLOCK_ID_SXS0 = 0x2f, + DBG_BLOCK_ID_SXS1 = 0x30, + DBG_BLOCK_ID_SXS2 = 0x31, + DBG_BLOCK_ID_SXS3 = 0x32, + DBG_BLOCK_ID_SXS4 = 0x33, + DBG_BLOCK_ID_SXS5 = 0x34, + DBG_BLOCK_ID_SXS6 = 0x35, + DBG_BLOCK_ID_SXS7 = 0x36, + DBG_BLOCK_ID_SXS8 = 0x37, + DBG_BLOCK_ID_SXS9 = 0x38, + DBG_BLOCK_ID_BCI0 = 0x39, + DBG_BLOCK_ID_BCI1 = 0x3a, + DBG_BLOCK_ID_BCI2 = 0x3b, + DBG_BLOCK_ID_BCI3 = 0x3c, + DBG_BLOCK_ID_MCB = 0x3d, + DBG_BLOCK_ID_UNUSED6 = 0x3e, + DBG_BLOCK_ID_SQA00 = 0x3f, + DBG_BLOCK_ID_SQA01 = 0x40, + DBG_BLOCK_ID_SQA02 = 0x41, + DBG_BLOCK_ID_SQA10 = 0x42, + DBG_BLOCK_ID_SQA11 = 0x43, + DBG_BLOCK_ID_SQA12 = 0x44, + DBG_BLOCK_ID_UNUSED7 = 0x45, + DBG_BLOCK_ID_UNUSED8 = 0x46, + DBG_BLOCK_ID_SQB00 = 0x47, + DBG_BLOCK_ID_SQB01 = 0x48, + DBG_BLOCK_ID_SQB10 = 0x49, + DBG_BLOCK_ID_SQB11 = 0x4a, + DBG_BLOCK_ID_SQ00 = 0x4b, + DBG_BLOCK_ID_SQ01 = 0x4c, + DBG_BLOCK_ID_SQ10 = 0x4d, + DBG_BLOCK_ID_SQ11 = 0x4e, + DBG_BLOCK_ID_CB00 = 0x4f, + DBG_BLOCK_ID_CB01 = 0x50, + DBG_BLOCK_ID_CB02 = 0x51, + DBG_BLOCK_ID_CB03 = 0x52, + DBG_BLOCK_ID_CB04 = 0x53, + DBG_BLOCK_ID_UNUSED9 = 0x54, + DBG_BLOCK_ID_UNUSED10 = 0x55, + DBG_BLOCK_ID_UNUSED11 = 0x56, + DBG_BLOCK_ID_CB10 = 0x57, + DBG_BLOCK_ID_CB11 = 0x58, + DBG_BLOCK_ID_CB12 = 0x59, + DBG_BLOCK_ID_CB13 = 0x5a, + DBG_BLOCK_ID_CB14 = 0x5b, + DBG_BLOCK_ID_UNUSED12 = 0x5c, + DBG_BLOCK_ID_UNUSED13 = 0x5d, + DBG_BLOCK_ID_UNUSED14 = 0x5e, + DBG_BLOCK_ID_TCP0 = 0x5f, + DBG_BLOCK_ID_TCP1 = 0x60, + DBG_BLOCK_ID_TCP2 = 0x61, + DBG_BLOCK_ID_TCP3 = 0x62, + DBG_BLOCK_ID_TCP4 = 0x63, + DBG_BLOCK_ID_TCP5 = 0x64, + DBG_BLOCK_ID_TCP6 = 0x65, + DBG_BLOCK_ID_TCP7 = 0x66, + DBG_BLOCK_ID_TCP8 = 0x67, + DBG_BLOCK_ID_TCP9 = 0x68, + DBG_BLOCK_ID_TCP10 = 0x69, + DBG_BLOCK_ID_TCP11 = 0x6a, + DBG_BLOCK_ID_TCP12 = 0x6b, + DBG_BLOCK_ID_TCP13 = 0x6c, + DBG_BLOCK_ID_TCP14 = 0x6d, + DBG_BLOCK_ID_TCP15 = 0x6e, + DBG_BLOCK_ID_TCP16 = 0x6f, + DBG_BLOCK_ID_TCP17 = 0x70, + DBG_BLOCK_ID_TCP18 = 0x71, + DBG_BLOCK_ID_TCP19 = 0x72, + DBG_BLOCK_ID_TCP20 = 0x73, + DBG_BLOCK_ID_TCP21 = 0x74, + DBG_BLOCK_ID_TCP22 = 0x75, + DBG_BLOCK_ID_TCP23 = 0x76, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, + DBG_BLOCK_ID_DB00 = 0x7f, + DBG_BLOCK_ID_DB01 = 0x80, + DBG_BLOCK_ID_DB02 = 0x81, + DBG_BLOCK_ID_DB03 = 0x82, + DBG_BLOCK_ID_DB04 = 0x83, + DBG_BLOCK_ID_UNUSED15 = 0x84, + DBG_BLOCK_ID_UNUSED16 = 0x85, + DBG_BLOCK_ID_UNUSED17 = 0x86, + DBG_BLOCK_ID_DB10 = 0x87, + DBG_BLOCK_ID_DB11 = 0x88, + DBG_BLOCK_ID_DB12 = 0x89, + DBG_BLOCK_ID_DB13 = 0x8a, + DBG_BLOCK_ID_DB14 = 0x8b, + DBG_BLOCK_ID_UNUSED18 = 0x8c, + DBG_BLOCK_ID_UNUSED19 = 0x8d, + DBG_BLOCK_ID_UNUSED20 = 0x8e, + DBG_BLOCK_ID_TCC0 = 0x8f, + DBG_BLOCK_ID_TCC1 = 0x90, + DBG_BLOCK_ID_TCC2 = 0x91, + DBG_BLOCK_ID_TCC3 = 0x92, + DBG_BLOCK_ID_TCC4 = 0x93, + DBG_BLOCK_ID_TCC5 = 0x94, + DBG_BLOCK_ID_TCC6 = 0x95, + DBG_BLOCK_ID_TCC7 = 0x96, + DBG_BLOCK_ID_SPS00 = 0x97, + DBG_BLOCK_ID_SPS01 = 0x98, + DBG_BLOCK_ID_SPS02 = 0x99, + DBG_BLOCK_ID_SPS10 = 0x9a, + DBG_BLOCK_ID_SPS11 = 0x9b, + DBG_BLOCK_ID_SPS12 = 0x9c, + DBG_BLOCK_ID_UNUSED21 = 0x9d, + DBG_BLOCK_ID_UNUSED22 = 0x9e, + DBG_BLOCK_ID_TA00 = 0x9f, + DBG_BLOCK_ID_TA01 = 0xa0, + DBG_BLOCK_ID_TA02 = 0xa1, + DBG_BLOCK_ID_TA03 = 0xa2, + DBG_BLOCK_ID_TA04 = 0xa3, + DBG_BLOCK_ID_TA05 = 0xa4, + DBG_BLOCK_ID_TA06 = 0xa5, + DBG_BLOCK_ID_TA07 = 0xa6, + DBG_BLOCK_ID_TA08 = 0xa7, + DBG_BLOCK_ID_TA09 = 0xa8, + DBG_BLOCK_ID_TA0A = 0xa9, + DBG_BLOCK_ID_TA0B = 0xaa, + DBG_BLOCK_ID_UNUSED23 = 0xab, + DBG_BLOCK_ID_UNUSED24 = 0xac, + DBG_BLOCK_ID_UNUSED25 = 0xad, + DBG_BLOCK_ID_UNUSED26 = 0xae, + DBG_BLOCK_ID_TA10 = 0xaf, + DBG_BLOCK_ID_TA11 = 0xb0, + DBG_BLOCK_ID_TA12 = 0xb1, + DBG_BLOCK_ID_TA13 = 0xb2, + DBG_BLOCK_ID_TA14 = 0xb3, + DBG_BLOCK_ID_TA15 = 0xb4, + DBG_BLOCK_ID_TA16 = 0xb5, + DBG_BLOCK_ID_TA17 = 0xb6, + DBG_BLOCK_ID_TA18 = 0xb7, + DBG_BLOCK_ID_TA19 = 0xb8, + DBG_BLOCK_ID_TA1A = 0xb9, + DBG_BLOCK_ID_TA1B = 0xba, + DBG_BLOCK_ID_UNUSED27 = 0xbb, + DBG_BLOCK_ID_UNUSED28 = 0xbc, + DBG_BLOCK_ID_UNUSED29 = 0xbd, + DBG_BLOCK_ID_UNUSED30 = 0xbe, + DBG_BLOCK_ID_TD00 = 0xbf, + DBG_BLOCK_ID_TD01 = 0xc0, + DBG_BLOCK_ID_TD02 = 0xc1, + DBG_BLOCK_ID_TD03 = 0xc2, + DBG_BLOCK_ID_TD04 = 0xc3, + DBG_BLOCK_ID_TD05 = 0xc4, + DBG_BLOCK_ID_TD06 = 0xc5, + DBG_BLOCK_ID_TD07 = 0xc6, + DBG_BLOCK_ID_TD08 = 0xc7, + DBG_BLOCK_ID_TD09 = 0xc8, + DBG_BLOCK_ID_TD0A = 0xc9, + DBG_BLOCK_ID_TD0B = 0xca, + DBG_BLOCK_ID_UNUSED31 = 0xcb, + DBG_BLOCK_ID_UNUSED32 = 0xcc, + DBG_BLOCK_ID_UNUSED33 = 0xcd, + DBG_BLOCK_ID_UNUSED34 = 0xce, + DBG_BLOCK_ID_TD10 = 0xcf, + DBG_BLOCK_ID_TD11 = 0xd0, + DBG_BLOCK_ID_TD12 = 0xd1, + DBG_BLOCK_ID_TD13 = 0xd2, + DBG_BLOCK_ID_TD14 = 0xd3, + DBG_BLOCK_ID_TD15 = 0xd4, + DBG_BLOCK_ID_TD16 = 0xd5, + DBG_BLOCK_ID_TD17 = 0xd6, + DBG_BLOCK_ID_TD18 = 0xd7, + DBG_BLOCK_ID_TD19 = 0xd8, + DBG_BLOCK_ID_TD1A = 0xd9, + DBG_BLOCK_ID_TD1B = 0xda, + DBG_BLOCK_ID_UNUSED35 = 0xdb, + DBG_BLOCK_ID_UNUSED36 = 0xdc, + DBG_BLOCK_ID_UNUSED37 = 0xdd, + DBG_BLOCK_ID_UNUSED38 = 0xde, + DBG_BLOCK_ID_LDS00 = 0xdf, + DBG_BLOCK_ID_LDS01 = 0xe0, + DBG_BLOCK_ID_LDS02 = 0xe1, + DBG_BLOCK_ID_LDS03 = 0xe2, + DBG_BLOCK_ID_LDS04 = 0xe3, + DBG_BLOCK_ID_LDS05 = 0xe4, + DBG_BLOCK_ID_LDS06 = 0xe5, + DBG_BLOCK_ID_LDS07 = 0xe6, + DBG_BLOCK_ID_LDS08 = 0xe7, + DBG_BLOCK_ID_LDS09 = 0xe8, + DBG_BLOCK_ID_LDS0A = 0xe9, + DBG_BLOCK_ID_LDS0B = 0xea, + DBG_BLOCK_ID_UNUSED39 = 0xeb, + DBG_BLOCK_ID_UNUSED40 = 0xec, + DBG_BLOCK_ID_UNUSED41 = 0xed, + DBG_BLOCK_ID_UNUSED42 = 0xee, + DBG_BLOCK_ID_LDS10 = 0xef, + DBG_BLOCK_ID_LDS11 = 0xf0, + DBG_BLOCK_ID_LDS12 = 0xf1, + DBG_BLOCK_ID_LDS13 = 0xf2, + DBG_BLOCK_ID_LDS14 = 0xf3, + DBG_BLOCK_ID_LDS15 = 0xf4, + DBG_BLOCK_ID_LDS16 = 0xf5, + DBG_BLOCK_ID_LDS17 = 0xf6, + DBG_BLOCK_ID_LDS18 = 0xf7, + DBG_BLOCK_ID_LDS19 = 0xf8, + DBG_BLOCK_ID_LDS1A = 0xf9, + DBG_BLOCK_ID_LDS1B = 0xfa, + DBG_BLOCK_ID_UNUSED43 = 0xfb, + DBG_BLOCK_ID_UNUSED44 = 0xfc, + DBG_BLOCK_ID_UNUSED45 = 0xfd, + DBG_BLOCK_ID_UNUSED46 = 0xfe, +} DebugBlockId; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_UVD_BY2 = 0x7, + DBG_BLOCK_ID_SDMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_VC0_BY2 = 0xa, + DBG_BLOCK_ID_PA_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_PC0_BY2 = 0xe, + DBG_BLOCK_ID_BCI0_BY2 = 0xf, + DBG_BLOCK_ID_SXM0_BY2 = 0x10, + DBG_BLOCK_ID_SCT0_BY2 = 0x11, + DBG_BLOCK_ID_SPM0_BY2 = 0x12, + DBG_BLOCK_ID_BCI2_BY2 = 0x13, + DBG_BLOCK_ID_TCA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_MCD_BY2 = 0x18, + DBG_BLOCK_ID_MCD2_BY2 = 0x19, + DBG_BLOCK_ID_MCD4_BY2 = 0x1a, + DBG_BLOCK_ID_MCB_BY2 = 0x1b, + DBG_BLOCK_ID_SQA_BY2 = 0x1c, + DBG_BLOCK_ID_SQA02_BY2 = 0x1d, + DBG_BLOCK_ID_SQA11_BY2 = 0x1e, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, + DBG_BLOCK_ID_SQB_BY2 = 0x20, + DBG_BLOCK_ID_SQB10_BY2 = 0x21, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, + DBG_BLOCK_ID_CB_BY2 = 0x24, + DBG_BLOCK_ID_CB02_BY2 = 0x25, + DBG_BLOCK_ID_CB10_BY2 = 0x26, + DBG_BLOCK_ID_CB12_BY2 = 0x27, + DBG_BLOCK_ID_SXS_BY2 = 0x28, + DBG_BLOCK_ID_SXS2_BY2 = 0x29, + DBG_BLOCK_ID_SXS4_BY2 = 0x2a, + DBG_BLOCK_ID_SXS6_BY2 = 0x2b, + DBG_BLOCK_ID_DB_BY2 = 0x2c, + DBG_BLOCK_ID_DB02_BY2 = 0x2d, + DBG_BLOCK_ID_DB10_BY2 = 0x2e, + DBG_BLOCK_ID_DB12_BY2 = 0x2f, + DBG_BLOCK_ID_TCP_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_TCC_BY2 = 0x40, + DBG_BLOCK_ID_TCC2_BY2 = 0x41, + DBG_BLOCK_ID_TCC4_BY2 = 0x42, + DBG_BLOCK_ID_TCC6_BY2 = 0x43, + DBG_BLOCK_ID_SPS_BY2 = 0x44, + DBG_BLOCK_ID_SPS02_BY2 = 0x45, + DBG_BLOCK_ID_SPS11_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, + DBG_BLOCK_ID_TA_BY2 = 0x48, + DBG_BLOCK_ID_TA02_BY2 = 0x49, + DBG_BLOCK_ID_TA04_BY2 = 0x4a, + DBG_BLOCK_ID_TA06_BY2 = 0x4b, + DBG_BLOCK_ID_TA08_BY2 = 0x4c, + DBG_BLOCK_ID_TA0A_BY2 = 0x4d, + DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, + DBG_BLOCK_ID_TA10_BY2 = 0x50, + DBG_BLOCK_ID_TA12_BY2 = 0x51, + DBG_BLOCK_ID_TA14_BY2 = 0x52, + DBG_BLOCK_ID_TA16_BY2 = 0x53, + DBG_BLOCK_ID_TA18_BY2 = 0x54, + DBG_BLOCK_ID_TA1A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, + DBG_BLOCK_ID_TD_BY2 = 0x58, + DBG_BLOCK_ID_TD02_BY2 = 0x59, + DBG_BLOCK_ID_TD04_BY2 = 0x5a, + DBG_BLOCK_ID_TD06_BY2 = 0x5b, + DBG_BLOCK_ID_TD08_BY2 = 0x5c, + DBG_BLOCK_ID_TD0A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, + DBG_BLOCK_ID_TD10_BY2 = 0x60, + DBG_BLOCK_ID_TD12_BY2 = 0x61, + DBG_BLOCK_ID_TD14_BY2 = 0x62, + DBG_BLOCK_ID_TD16_BY2 = 0x63, + DBG_BLOCK_ID_TD18_BY2 = 0x64, + DBG_BLOCK_ID_TD1A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, + DBG_BLOCK_ID_LDS_BY2 = 0x68, + DBG_BLOCK_ID_LDS02_BY2 = 0x69, + DBG_BLOCK_ID_LDS04_BY2 = 0x6a, + DBG_BLOCK_ID_LDS06_BY2 = 0x6b, + DBG_BLOCK_ID_LDS08_BY2 = 0x6c, + DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, + DBG_BLOCK_ID_LDS10_BY2 = 0x70, + DBG_BLOCK_ID_LDS12_BY2 = 0x71, + DBG_BLOCK_ID_LDS14_BY2 = 0x72, + DBG_BLOCK_ID_LDS16_BY2 = 0x73, + DBG_BLOCK_ID_LDS18_BY2 = 0x74, + DBG_BLOCK_ID_LDS1A_BY2 = 0x75, + DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, + DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_SDMA0_BY4 = 0x4, + DBG_BLOCK_ID_VC0_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, + DBG_BLOCK_ID_SXM0_BY4 = 0x8, + DBG_BLOCK_ID_SPM0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC_BY4 = 0xb, + DBG_BLOCK_ID_MCD_BY4 = 0xc, + DBG_BLOCK_ID_MCD4_BY4 = 0xd, + DBG_BLOCK_ID_SQA_BY4 = 0xe, + DBG_BLOCK_ID_SQA11_BY4 = 0xf, + DBG_BLOCK_ID_SQB_BY4 = 0x10, + DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, + DBG_BLOCK_ID_CB_BY4 = 0x12, + DBG_BLOCK_ID_CB10_BY4 = 0x13, + DBG_BLOCK_ID_SXS_BY4 = 0x14, + DBG_BLOCK_ID_SXS4_BY4 = 0x15, + DBG_BLOCK_ID_DB_BY4 = 0x16, + DBG_BLOCK_ID_DB10_BY4 = 0x17, + DBG_BLOCK_ID_TCP_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_TCC_BY4 = 0x20, + DBG_BLOCK_ID_TCC4_BY4 = 0x21, + DBG_BLOCK_ID_SPS_BY4 = 0x22, + DBG_BLOCK_ID_SPS11_BY4 = 0x23, + DBG_BLOCK_ID_TA_BY4 = 0x24, + DBG_BLOCK_ID_TA04_BY4 = 0x25, + DBG_BLOCK_ID_TA08_BY4 = 0x26, + DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, + DBG_BLOCK_ID_TA10_BY4 = 0x28, + DBG_BLOCK_ID_TA14_BY4 = 0x29, + DBG_BLOCK_ID_TA18_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, + DBG_BLOCK_ID_TD_BY4 = 0x2c, + DBG_BLOCK_ID_TD04_BY4 = 0x2d, + DBG_BLOCK_ID_TD08_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, + DBG_BLOCK_ID_TD10_BY4 = 0x30, + DBG_BLOCK_ID_TD14_BY4 = 0x31, + DBG_BLOCK_ID_TD18_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, + DBG_BLOCK_ID_LDS_BY4 = 0x34, + DBG_BLOCK_ID_LDS04_BY4 = 0x35, + DBG_BLOCK_ID_LDS08_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, + DBG_BLOCK_ID_LDS10_BY4 = 0x38, + DBG_BLOCK_ID_LDS14_BY4 = 0x39, + DBG_BLOCK_ID_LDS18_BY4 = 0x3a, + DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_SDMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_SXM0_BY8 = 0x4, + DBG_BLOCK_ID_TCA_BY8 = 0x5, + DBG_BLOCK_ID_MCD_BY8 = 0x6, + DBG_BLOCK_ID_SQA_BY8 = 0x7, + DBG_BLOCK_ID_SQB_BY8 = 0x8, + DBG_BLOCK_ID_CB_BY8 = 0x9, + DBG_BLOCK_ID_SXS_BY8 = 0xa, + DBG_BLOCK_ID_DB_BY8 = 0xb, + DBG_BLOCK_ID_TCP_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_TCC_BY8 = 0x10, + DBG_BLOCK_ID_SPS_BY8 = 0x11, + DBG_BLOCK_ID_TA_BY8 = 0x12, + DBG_BLOCK_ID_TA08_BY8 = 0x13, + DBG_BLOCK_ID_TA10_BY8 = 0x14, + DBG_BLOCK_ID_TA18_BY8 = 0x15, + DBG_BLOCK_ID_TD_BY8 = 0x16, + DBG_BLOCK_ID_TD08_BY8 = 0x17, + DBG_BLOCK_ID_TD10_BY8 = 0x18, + DBG_BLOCK_ID_TD18_BY8 = 0x19, + DBG_BLOCK_ID_LDS_BY8 = 0x1a, + DBG_BLOCK_ID_LDS08_BY8 = 0x1b, + DBG_BLOCK_ID_LDS10_BY8 = 0x1c, + DBG_BLOCK_ID_LDS18_BY8 = 0x1d, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_SDMA0_BY16 = 0x1, + DBG_BLOCK_ID_SXM_BY16 = 0x2, + DBG_BLOCK_ID_MCD_BY16 = 0x3, + DBG_BLOCK_ID_SQB_BY16 = 0x4, + DBG_BLOCK_ID_SXS_BY16 = 0x5, + DBG_BLOCK_ID_TCP_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_TCC_BY16 = 0x8, + DBG_BLOCK_ID_TA_BY16 = 0x9, + DBG_BLOCK_ID_TA10_BY16 = 0xa, + DBG_BLOCK_ID_TD_BY16 = 0xb, + DBG_BLOCK_ID_TD10_BY16 = 0xc, + DBG_BLOCK_ID_LDS_BY16 = 0xd, + DBG_BLOCK_ID_LDS10_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; +#define CG_SRBM_START_ADDR 0x600 +#define CG_SRBM_END_ADDR 0x8ff +#define CG_SRBM_DEC0_START_ADDR 0x200 +#define CG_SRBM_DEC0_END_ADDR 0x2ff + +#endif /* SMU_8_0_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h new file mode 100644 index 000000000000..3dbe24df7e02 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h @@ -0,0 +1,2964 @@ +/* + * SMU_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_8_0_SH_MASK_H +#define SMU_8_0_SH_MASK_H + +#define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff +#define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0 +#define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400 +#define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa +#define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff +#define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0 +#define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000 +#define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc +#define THM_TCON_HTC__HTC_EN_MASK 0x1 +#define THM_TCON_HTC__HTC_EN__SHIFT 0x0 +#define THM_TCON_HTC__RSVD0_MASK 0x2 +#define THM_TCON_HTC__RSVD0__SHIFT 0x1 +#define THM_TCON_HTC__HTC_P_STATE_EN_MASK 0x4 +#define THM_TCON_HTC__HTC_P_STATE_EN__SHIFT 0x2 +#define THM_TCON_HTC__RSVD1_MASK 0x8 +#define THM_TCON_HTC__RSVD1__SHIFT 0x3 +#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x10 +#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 +#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x20 +#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 +#define THM_TCON_HTC__HTC_APIC_HI_EN_MASK 0x40 +#define THM_TCON_HTC__HTC_APIC_HI_EN__SHIFT 0x6 +#define THM_TCON_HTC__HTC_APIC_LO_EN_MASK 0x80 +#define THM_TCON_HTC__HTC_APIC_LO_EN__SHIFT 0x7 +#define THM_TCON_HTC__HTC_DIAG_MASK 0x100 +#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 +#define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x200 +#define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9 +#define THM_TCON_HTC__HTC_TO_GNB_EN_MASK 0x400 +#define THM_TCON_HTC__HTC_TO_GNB_EN__SHIFT 0xa +#define THM_TCON_HTC__PROCHOT_TO_GNB_EN_MASK 0x800 +#define THM_TCON_HTC__PROCHOT_TO_GNB_EN__SHIFT 0xb +#define THM_TCON_HTC__RSVD2_MASK 0xf000 +#define THM_TCON_HTC__RSVD2__SHIFT 0xc +#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x7f0000 +#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 +#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x800000 +#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x17 +#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0xf000000 +#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x18 +#define THM_TCON_HTC__HTC_PSTATE_LIMIT_MASK 0x70000000 +#define THM_TCON_HTC__HTC_PSTATE_LIMIT__SHIFT 0x1c +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x1f +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x60 +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x80 +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x1f00 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x30000 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x40000 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x80000 +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 +#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xffe00000 +#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 +#define THM_TCON_THERM_TRIP__RSVD0_MASK 0x1 +#define THM_TCON_THERM_TRIP__RSVD0__SHIFT 0x0 +#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x2 +#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 +#define THM_TCON_THERM_TRIP__RSVD1_MASK 0x4 +#define THM_TCON_THERM_TRIP__RSVD1__SHIFT 0x2 +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x8 +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 +#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x10 +#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 +#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x20 +#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 +#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7fffffc0 +#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0x6 +#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000 +#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f +#define THM_GPIO_PROCHOT_CTRL__TX12_EN_MASK 0x1 +#define THM_GPIO_PROCHOT_CTRL__TX12_EN__SHIFT 0x0 +#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x2 +#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x4 +#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x8 +#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_PROCHOT_CTRL__SN_MASK 0x10 +#define THM_GPIO_PROCHOT_CTRL__SN__SHIFT 0x4 +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x100 +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x8 +#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x200 +#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x9 +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x400 +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0xa +#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x800 +#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0xb +#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x1000 +#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0xc +#define THM_GPIO_THERMTRIP_CTRL__TX12_EN_MASK 0x1 +#define THM_GPIO_THERMTRIP_CTRL__TX12_EN__SHIFT 0x0 +#define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x2 +#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x4 +#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x8 +#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_THERMTRIP_CTRL__SN_MASK 0x10 +#define THM_GPIO_THERMTRIP_CTRL__SN__SHIFT 0x4 +#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x100 +#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x8 +#define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x200 +#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x9 +#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x400 +#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0xa +#define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x800 +#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0xb +#define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x1000 +#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0xc +#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define TMON0_RDIL0_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL0_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL1_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL1_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL2_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL2_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL3_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL3_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL4_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL4_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL5_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL5_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL6_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL6_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL7_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL7_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL8_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL8_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL9_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL9_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL10_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL10_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL11_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL11_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL12_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL12_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL13_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL13_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL14_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL14_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL15_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL15_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR0_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR0_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR1_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR1_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR2_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR2_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR3_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR3_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR4_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR4_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR5_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR5_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR6_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR6_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR7_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR7_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR8_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR8_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR9_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR9_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR10_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR10_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR11_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR11_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR12_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR12_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR13_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR13_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR14_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR14_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR15_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR15_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_INT_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_INT_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK 0xff +#define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT 0x0 +#define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK 0xff +#define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT 0x0 +#define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK 0xff +#define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT 0x0 +#define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK 0xff +#define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT 0x0 +#define TMON0_CONFIG__NUM_ACQ_MASK 0x7 +#define TMON0_CONFIG__NUM_ACQ__SHIFT 0x0 +#define TMON0_CONFIG__FORCE_MAX_ACQ_MASK 0x8 +#define TMON0_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3 +#define TMON0_CONFIG__RDI_INTERLEAVE_MASK 0x10 +#define TMON0_CONFIG__RDI_INTERLEAVE__SHIFT 0x4 +#define TMON0_CONFIG__RE_CALIB_EN_MASK 0x40 +#define TMON0_CONFIG__RE_CALIB_EN__SHIFT 0x6 +#define TMON0_TEMP_CALC_COEFF0__Z_MASK 0x7ff +#define TMON0_TEMP_CALC_COEFF0__Z__SHIFT 0x0 +#define TMON0_TEMP_CALC_COEFF1__A_MASK 0xfff +#define TMON0_TEMP_CALC_COEFF1__A__SHIFT 0x0 +#define TMON0_TEMP_CALC_COEFF2__B_MASK 0x3f +#define TMON0_TEMP_CALC_COEFF2__B__SHIFT 0x0 +#define TMON0_TEMP_CALC_COEFF3__C_MASK 0x7ff +#define TMON0_TEMP_CALC_COEFF3__C__SHIFT 0x0 +#define TMON0_TEMP_CALC_COEFF4__K_MASK 0x1 +#define TMON0_TEMP_CALC_COEFF4__K__SHIFT 0x0 +#define TMON0_DEBUG0__DEBUG_Z_MASK 0x7ff +#define TMON0_DEBUG0__DEBUG_Z__SHIFT 0x0 +#define TMON0_DEBUG0__DEBUG_Z_EN_MASK 0x800 +#define TMON0_DEBUG0__DEBUG_Z_EN__SHIFT 0xb +#define TMON0_DEBUG1__DEBUG_RDI_MASK 0x1f +#define TMON0_DEBUG1__DEBUG_RDI__SHIFT 0x0 +#define TMON1_RDIL0_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL0_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL1_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL1_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL2_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL2_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL3_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL3_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL4_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL4_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL5_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL5_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL6_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL6_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL7_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL7_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL8_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL8_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL9_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL9_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL10_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL10_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL11_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL11_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL12_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL12_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL13_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL13_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL14_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL14_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL15_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL15_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR0_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR0_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR1_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR1_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR2_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR2_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR3_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR3_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR4_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR4_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR5_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR5_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR6_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR6_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR7_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR7_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR8_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR8_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR9_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR9_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR10_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR10_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR11_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR11_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR12_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR12_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR13_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR13_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR14_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR14_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR15_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR15_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_INT_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_INT_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK 0xff +#define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT 0x0 +#define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK 0xff +#define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT 0x0 +#define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK 0xff +#define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT 0x0 +#define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK 0xff +#define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT 0x0 +#define TMON1_CONFIG__NUM_ACQ_MASK 0x7 +#define TMON1_CONFIG__NUM_ACQ__SHIFT 0x0 +#define TMON1_CONFIG__FORCE_MAX_ACQ_MASK 0x8 +#define TMON1_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3 +#define TMON1_CONFIG__RDI_INTERLEAVE_MASK 0x10 +#define TMON1_CONFIG__RDI_INTERLEAVE__SHIFT 0x4 +#define TMON1_CONFIG__RE_CALIB_EN_MASK 0x40 +#define TMON1_CONFIG__RE_CALIB_EN__SHIFT 0x6 +#define TMON1_TEMP_CALC_COEFF0__Z_MASK 0x7ff +#define TMON1_TEMP_CALC_COEFF0__Z__SHIFT 0x0 +#define TMON1_TEMP_CALC_COEFF1__A_MASK 0xfff +#define TMON1_TEMP_CALC_COEFF1__A__SHIFT 0x0 +#define TMON1_TEMP_CALC_COEFF2__B_MASK 0x3f +#define TMON1_TEMP_CALC_COEFF2__B__SHIFT 0x0 +#define TMON1_TEMP_CALC_COEFF3__C_MASK 0x7ff +#define TMON1_TEMP_CALC_COEFF3__C__SHIFT 0x0 +#define TMON1_TEMP_CALC_COEFF4__K_MASK 0x1 +#define TMON1_TEMP_CALC_COEFF4__K__SHIFT 0x0 +#define TMON1_DEBUG0__DEBUG_Z_MASK 0x7ff +#define TMON1_DEBUG0__DEBUG_Z__SHIFT 0x0 +#define TMON1_DEBUG0__DEBUG_Z_EN_MASK 0x800 +#define TMON1_DEBUG0__DEBUG_Z_EN__SHIFT 0xb +#define TMON1_DEBUG1__DEBUG_RDI_MASK 0x1f +#define TMON1_DEBUG1__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON0_REMOTE_START__DATA_MASK 0xffffffff +#define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0 +#define THM_TMON0_REMOTE_END__DATA_MASK 0xffffffff +#define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0 +#define THM_TMON1_REMOTE_START__DATA_MASK 0xffffffff +#define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0 +#define THM_TMON1_REMOTE_END__DATA_MASK 0xffffffff +#define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0 +#define THM_TCON_LOCAL0__HaltPolling_MASK 0x1 +#define THM_TCON_LOCAL0__HaltPolling__SHIFT 0x0 +#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x2 +#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1 +#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x4 +#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2 +#define THM_TCON_LOCAL1__PwrDn_Limit_Temp_MASK 0x7 +#define THM_TCON_LOCAL1__PwrDn_Limit_Temp__SHIFT 0x0 +#define THM_TCON_LOCAL1__PwrDn_DelaySlope_MASK 0x38 +#define THM_TCON_LOCAL1__PwrDn_DelaySlope__SHIFT 0x3 +#define THM_TCON_LOCAL1__PwrDn_MinDelay_MASK 0x1c0 +#define THM_TCON_LOCAL1__PwrDn_MinDelay__SHIFT 0x6 +#define THM_TCON_LOCAL2__PwrDn_MaxDlyMult_MASK 0x3 +#define THM_TCON_LOCAL2__PwrDn_MaxDlyMult__SHIFT 0x0 +#define THM_TCON_LOCAL2__PwrDn_NumSensors_MASK 0xc +#define THM_TCON_LOCAL2__PwrDn_NumSensors__SHIFT 0x2 +#define THM_TCON_LOCAL2__start_mission_polling_MASK 0x10 +#define THM_TCON_LOCAL2__start_mission_polling__SHIFT 0x4 +#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x20 +#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 +#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x40 +#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 +#define THM_TCON_LOCAL2__csrslave_use_corrected_MASK 0x80 +#define THM_TCON_LOCAL2__csrslave_use_corrected__SHIFT 0x7 +#define THM_TCON_LOCAL2__smu_use_corrected_MASK 0x100 +#define THM_TCON_LOCAL2__smu_use_corrected__SHIFT 0x8 +#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x800 +#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb +#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x7ff +#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 +#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0xff +#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 +#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x7ff +#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 +#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0xff +#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 +#define THM_TCON_LOCAL7__THERMID_MASK 0xff +#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 +#define THM_TCON_LOCAL8__THERMMAX_MASK 0x7ff +#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 +#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x7ff +#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0 +#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0xf +#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x7ff +#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0 +#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0xf +#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL13__PowerDownTmon0_MASK 0x1 +#define THM_TCON_LOCAL13__PowerDownTmon0__SHIFT 0x0 +#define THM_TCON_LOCAL13__PowerDownTmon1_MASK 0x2 +#define THM_TCON_LOCAL13__PowerDownTmon1__SHIFT 0x1 +#define THM_TCON_LOCAL14__boot_done_MASK 0x1 +#define THM_TCON_LOCAL14__boot_done__SHIFT 0x0 +#define THM_FUSE0__FUSE_TmonRsInterleave_MASK 0x1 +#define THM_FUSE0__FUSE_TmonRsInterleave__SHIFT 0x0 +#define THM_FUSE0__FUSE_TmonNumAcq_MASK 0xe +#define THM_FUSE0__FUSE_TmonNumAcq__SHIFT 0x1 +#define THM_FUSE0__FUSE_TmonForceMaxAcq_MASK 0x10 +#define THM_FUSE0__FUSE_TmonForceMaxAcq__SHIFT 0x4 +#define THM_FUSE0__FUSE_TmonClkDiv_MASK 0x60 +#define THM_FUSE0__FUSE_TmonClkDiv__SHIFT 0x5 +#define THM_FUSE0__FUSE_TmonBGAdj1_MASK 0x7f80 +#define THM_FUSE0__FUSE_TmonBGAdj1__SHIFT 0x7 +#define THM_FUSE0__FUSE_TmonBGAdj0_MASK 0x7f8000 +#define THM_FUSE0__FUSE_TmonBGAdj0__SHIFT 0xf +#define THM_FUSE0__FUSE_TconZtValue_MASK 0xff800000 +#define THM_FUSE0__FUSE_TconZtValue__SHIFT 0x17 +#define THM_FUSE1__FUSE_TconZtValue_MASK 0x3 +#define THM_FUSE1__FUSE_TconZtValue__SHIFT 0x0 +#define THM_FUSE1__FUSE_TconUseSecondary_MASK 0xc +#define THM_FUSE1__FUSE_TconUseSecondary__SHIFT 0x2 +#define THM_FUSE1__FUSE_TconTmpAdjLoRes_MASK 0x10 +#define THM_FUSE1__FUSE_TconTmpAdjLoRes__SHIFT 0x4 +#define THM_FUSE1__FUSE_TconPwrUpStaggerTime_MASK 0x60 +#define THM_FUSE1__FUSE_TconPwrUpStaggerTime__SHIFT 0x5 +#define THM_FUSE1__FUSE_TconPwrDnTmpLmt_MASK 0x380 +#define THM_FUSE1__FUSE_TconPwrDnTmpLmt__SHIFT 0x7 +#define THM_FUSE1__FUSE_TconPwrDnNumSensors_MASK 0xc00 +#define THM_FUSE1__FUSE_TconPwrDnNumSensors__SHIFT 0xa +#define THM_FUSE1__FUSE_TconPwrDnMinDelay_MASK 0x7000 +#define THM_FUSE1__FUSE_TconPwrDnMinDelay__SHIFT 0xc +#define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult_MASK 0x18000 +#define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult__SHIFT 0xf +#define THM_FUSE1__FUSE_TconPwrDnDelaySlope_MASK 0xe0000 +#define THM_FUSE1__FUSE_TconPwrDnDelaySlope__SHIFT 0x11 +#define THM_FUSE1__FUSE_TconKValue_MASK 0x100000 +#define THM_FUSE1__FUSE_TconKValue__SHIFT 0x14 +#define THM_FUSE1__FUSE_TconDtValue31_MASK 0x7e00000 +#define THM_FUSE1__FUSE_TconDtValue31__SHIFT 0x15 +#define THM_FUSE1__FUSE_TconDtValue30_MASK 0xf8000000 +#define THM_FUSE1__FUSE_TconDtValue30__SHIFT 0x1b +#define THM_FUSE2__FUSE_TconDtValue30_MASK 0x1 +#define THM_FUSE2__FUSE_TconDtValue30__SHIFT 0x0 +#define THM_FUSE2__FUSE_TconDtValue29_MASK 0x7e +#define THM_FUSE2__FUSE_TconDtValue29__SHIFT 0x1 +#define THM_FUSE2__FUSE_TconDtValue28_MASK 0x1f80 +#define THM_FUSE2__FUSE_TconDtValue28__SHIFT 0x7 +#define THM_FUSE2__FUSE_TconDtValue27_MASK 0x7e000 +#define THM_FUSE2__FUSE_TconDtValue27__SHIFT 0xd +#define THM_FUSE2__FUSE_TconDtValue26_MASK 0x1f80000 +#define THM_FUSE2__FUSE_TconDtValue26__SHIFT 0x13 +#define THM_FUSE2__FUSE_TconDtValue25_MASK 0x7e000000 +#define THM_FUSE2__FUSE_TconDtValue25__SHIFT 0x19 +#define THM_FUSE2__FUSE_TconDtValue24_MASK 0x80000000 +#define THM_FUSE2__FUSE_TconDtValue24__SHIFT 0x1f +#define THM_FUSE3__FUSE_TconDtValue24_MASK 0x1f +#define THM_FUSE3__FUSE_TconDtValue24__SHIFT 0x0 +#define THM_FUSE3__FUSE_TconDtValue23_MASK 0x7e0 +#define THM_FUSE3__FUSE_TconDtValue23__SHIFT 0x5 +#define THM_FUSE3__FUSE_TconDtValue22_MASK 0x1f800 +#define THM_FUSE3__FUSE_TconDtValue22__SHIFT 0xb +#define THM_FUSE3__FUSE_TconDtValue21_MASK 0x7e0000 +#define THM_FUSE3__FUSE_TconDtValue21__SHIFT 0x11 +#define THM_FUSE3__FUSE_TconDtValue20_MASK 0x1f800000 +#define THM_FUSE3__FUSE_TconDtValue20__SHIFT 0x17 +#define THM_FUSE3__FUSE_TconDtValue19_MASK 0xe0000000 +#define THM_FUSE3__FUSE_TconDtValue19__SHIFT 0x1d +#define THM_FUSE4__FUSE_TconDtValue19_MASK 0x7 +#define THM_FUSE4__FUSE_TconDtValue19__SHIFT 0x0 +#define THM_FUSE4__FUSE_TconDtValue18_MASK 0x1f8 +#define THM_FUSE4__FUSE_TconDtValue18__SHIFT 0x3 +#define THM_FUSE4__FUSE_TconDtValue17_MASK 0x7e00 +#define THM_FUSE4__FUSE_TconDtValue17__SHIFT 0x9 +#define THM_FUSE4__FUSE_TconDtValue16_MASK 0x1f8000 +#define THM_FUSE4__FUSE_TconDtValue16__SHIFT 0xf +#define THM_FUSE4__FUSE_TconDtValue15_MASK 0x7e00000 +#define THM_FUSE4__FUSE_TconDtValue15__SHIFT 0x15 +#define THM_FUSE4__FUSE_TconDtValue14_MASK 0xf8000000 +#define THM_FUSE4__FUSE_TconDtValue14__SHIFT 0x1b +#define THM_FUSE5__FUSE_TconDtValue14_MASK 0x1 +#define THM_FUSE5__FUSE_TconDtValue14__SHIFT 0x0 +#define THM_FUSE5__FUSE_TconDtValue13_MASK 0x7e +#define THM_FUSE5__FUSE_TconDtValue13__SHIFT 0x1 +#define THM_FUSE5__FUSE_TconDtValue12_MASK 0x1f80 +#define THM_FUSE5__FUSE_TconDtValue12__SHIFT 0x7 +#define THM_FUSE5__FUSE_TconDtValue11_MASK 0x7e000 +#define THM_FUSE5__FUSE_TconDtValue11__SHIFT 0xd +#define THM_FUSE5__FUSE_TconDtValue10_MASK 0x1f80000 +#define THM_FUSE5__FUSE_TconDtValue10__SHIFT 0x13 +#define THM_FUSE5__FUSE_TconDtValue9_MASK 0x7e000000 +#define THM_FUSE5__FUSE_TconDtValue9__SHIFT 0x19 +#define THM_FUSE5__FUSE_TconDtValue8_MASK 0x80000000 +#define THM_FUSE5__FUSE_TconDtValue8__SHIFT 0x1f +#define THM_FUSE6__FUSE_TconDtValue8_MASK 0x1f +#define THM_FUSE6__FUSE_TconDtValue8__SHIFT 0x0 +#define THM_FUSE6__FUSE_TconDtValue7_MASK 0x7e0 +#define THM_FUSE6__FUSE_TconDtValue7__SHIFT 0x5 +#define THM_FUSE6__FUSE_TconDtValue6_MASK 0x1f800 +#define THM_FUSE6__FUSE_TconDtValue6__SHIFT 0xb +#define THM_FUSE6__FUSE_TconDtValue5_MASK 0x7e0000 +#define THM_FUSE6__FUSE_TconDtValue5__SHIFT 0x11 +#define THM_FUSE6__FUSE_TconDtValue4_MASK 0x1f800000 +#define THM_FUSE6__FUSE_TconDtValue4__SHIFT 0x17 +#define THM_FUSE6__FUSE_TconDtValue3_MASK 0xe0000000 +#define THM_FUSE6__FUSE_TconDtValue3__SHIFT 0x1d +#define THM_FUSE7__FUSE_TconDtValue3_MASK 0x7 +#define THM_FUSE7__FUSE_TconDtValue3__SHIFT 0x0 +#define THM_FUSE7__FUSE_TconDtValue2_MASK 0x1f8 +#define THM_FUSE7__FUSE_TconDtValue2__SHIFT 0x3 +#define THM_FUSE7__FUSE_TconDtValue1_MASK 0x7e00 +#define THM_FUSE7__FUSE_TconDtValue1__SHIFT 0x9 +#define THM_FUSE7__FUSE_TconDtValue0_MASK 0x1f8000 +#define THM_FUSE7__FUSE_TconDtValue0__SHIFT 0xf +#define THM_FUSE7__FUSE_TconCtValue1_MASK 0xffe00000 +#define THM_FUSE7__FUSE_TconCtValue1__SHIFT 0x15 +#define THM_FUSE8__FUSE_TconCtValue0_MASK 0x7ff +#define THM_FUSE8__FUSE_TconCtValue0__SHIFT 0x0 +#define THM_FUSE8__FUSE_TconBtValue_MASK 0x1f800 +#define THM_FUSE8__FUSE_TconBtValue__SHIFT 0xb +#define THM_FUSE8__FUSE_TconBootDelay_MASK 0x60000 +#define THM_FUSE8__FUSE_TconBootDelay__SHIFT 0x11 +#define THM_FUSE8__FUSE_TconAtValue1_MASK 0x7ff80000 +#define THM_FUSE8__FUSE_TconAtValue1__SHIFT 0x13 +#define THM_FUSE8__FUSE_TconAtValue0_MASK 0x80000000 +#define THM_FUSE8__FUSE_TconAtValue0__SHIFT 0x1f +#define THM_FUSE9__FUSE_TconAtValue0_MASK 0x7ff +#define THM_FUSE9__FUSE_TconAtValue0__SHIFT 0x0 +#define THM_FUSE9__FUSE_ThermTripLimit_MASK 0x7f800 +#define THM_FUSE9__FUSE_ThermTripLimit__SHIFT 0xb +#define THM_FUSE9__FUSE_ThermTripEn_MASK 0x80000 +#define THM_FUSE9__FUSE_ThermTripEn__SHIFT 0x13 +#define THM_FUSE9__FUSE_HtcTmpLmt_MASK 0x7f00000 +#define THM_FUSE9__FUSE_HtcTmpLmt__SHIFT 0x14 +#define THM_FUSE9__FUSE_HtcMsrLock_MASK 0x8000000 +#define THM_FUSE9__FUSE_HtcMsrLock__SHIFT 0x1b +#define THM_FUSE9__FUSE_HtcHystLmt_MASK 0xf0000000 +#define THM_FUSE9__FUSE_HtcHystLmt__SHIFT 0x1c +#define THM_FUSE10__FUSE_HtcDis_MASK 0x1 +#define THM_FUSE10__FUSE_HtcDis__SHIFT 0x0 +#define THM_FUSE10__FUSE_HtcClkInact_MASK 0xe +#define THM_FUSE10__FUSE_HtcClkInact__SHIFT 0x1 +#define THM_FUSE10__FUSE_HtcClkAct_MASK 0x70 +#define THM_FUSE10__FUSE_HtcClkAct__SHIFT 0x4 +#define THM_FUSE10__FUSE_UnusedBits_MASK 0xffffff80 +#define THM_FUSE10__FUSE_UnusedBits__SHIFT 0x7 +#define THM_FUSE11__PA_SPARE_MASK 0xff +#define THM_FUSE11__PA_SPARE__SHIFT 0x0 +#define THM_FUSE12__FusesValid_MASK 0x1 +#define THM_FUSE12__FusesValid__SHIFT 0x0 +#define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf +#define MP0_MSP_MESSAGE_0__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_0__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_1__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_1__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_2__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_2__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_3__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_3__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_4__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_4__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_5__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_5__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_6__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_6__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_7__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_7__MP0_MSP_MSG__SHIFT 0x0 +#define SAM_IH_EXT_ERR_INTR__UVD_MASK 0x1 +#define SAM_IH_EXT_ERR_INTR__UVD__SHIFT 0x0 +#define SAM_IH_EXT_ERR_INTR__VCE_MASK 0x2 +#define SAM_IH_EXT_ERR_INTR__VCE__SHIFT 0x1 +#define SAM_IH_EXT_ERR_INTR__ISP_MASK 0x4 +#define SAM_IH_EXT_ERR_INTR__ISP__SHIFT 0x2 +#define SAM_IH_EXT_ERR_INTR__RESERVED_MASK 0xfffffff8 +#define SAM_IH_EXT_ERR_INTR__RESERVED__SHIFT 0x3 +#define SAM_IH_EXT_ERR_INTR_STATUS__UVD_MASK 0x1 +#define SAM_IH_EXT_ERR_INTR_STATUS__UVD__SHIFT 0x0 +#define SAM_IH_EXT_ERR_INTR_STATUS__VCE_MASK 0x2 +#define SAM_IH_EXT_ERR_INTR_STATUS__VCE__SHIFT 0x1 +#define SAM_IH_EXT_ERR_INTR_STATUS__ISP_MASK 0x4 +#define SAM_IH_EXT_ERR_INTR_STATUS__ISP__SHIFT 0x2 +#define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED_MASK 0xfffffff8 +#define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED__SHIFT 0x3 +#define MP0_DISP_TIMER0_CTRL0__START_MASK 0x1 +#define MP0_DISP_TIMER0_CTRL0__START__SHIFT 0x0 +#define MP0_DISP_TIMER0_CTRL0__CLEAR_MASK 0x100 +#define MP0_DISP_TIMER0_CTRL0__CLEAR__SHIFT 0x8 +#define MP0_DISP_TIMER0_CTRL0__DEC_MASK 0x10000 +#define MP0_DISP_TIMER0_CTRL0__DEC__SHIFT 0x10 +#define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE_MASK 0x1000000 +#define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE__SHIFT 0x18 +#define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN_MASK 0x1 +#define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN__SHIFT 0x0 +#define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN_MASK 0x100 +#define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x8 +#define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN_MASK 0x10000 +#define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN__SHIFT 0x10 +#define MP0_DISP_TIMER0_CTRL1__RESERVED_MASK 0xff000000 +#define MP0_DISP_TIMER0_CTRL1__RESERVED__SHIFT 0x18 +#define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC_MASK 0xf +#define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC__SHIFT 0x0 +#define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED_MASK 0xfffffff0 +#define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED__SHIFT 0x4 +#define MP0_DISP_TIMER0_INTEN__INTEN_MASK 0xf +#define MP0_DISP_TIMER0_INTEN__INTEN__SHIFT 0x0 +#define MP0_DISP_TIMER0_INTEN__RESERVED_MASK 0xfffffff0 +#define MP0_DISP_TIMER0_INTEN__RESERVED__SHIFT 0x4 +#define MP0_DISP_TIMER0_OCMP_0_0__OCMP_MASK 0xffffffff +#define MP0_DISP_TIMER0_OCMP_0_0__OCMP__SHIFT 0x0 +#define MP0_DISP_TIMER0_OCMP_0_1__OCMP_MASK 0xffffffff +#define MP0_DISP_TIMER0_OCMP_0_1__OCMP__SHIFT 0x0 +#define MP0_DISP_TIMER0_CNT__COUNT_MASK 0xffffffff +#define MP0_DISP_TIMER0_CNT__COUNT__SHIFT 0x0 +#define MP0_DISP_TIMER1_CTRL0__START_MASK 0x1 +#define MP0_DISP_TIMER1_CTRL0__START__SHIFT 0x0 +#define MP0_DISP_TIMER1_CTRL0__CLEAR_MASK 0x100 +#define MP0_DISP_TIMER1_CTRL0__CLEAR__SHIFT 0x8 +#define MP0_DISP_TIMER1_CTRL0__DEC_MASK 0x10000 +#define MP0_DISP_TIMER1_CTRL0__DEC__SHIFT 0x10 +#define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE_MASK 0x1000000 +#define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE__SHIFT 0x18 +#define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN_MASK 0x1 +#define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN__SHIFT 0x0 +#define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN_MASK 0x100 +#define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x8 +#define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN_MASK 0x10000 +#define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN__SHIFT 0x10 +#define MP0_DISP_TIMER1_CTRL1__RESERVED_MASK 0xff000000 +#define MP0_DISP_TIMER1_CTRL1__RESERVED__SHIFT 0x18 +#define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC_MASK 0xf +#define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC__SHIFT 0x0 +#define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED_MASK 0xfffffff0 +#define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED__SHIFT 0x4 +#define MP0_DISP_TIMER1_INTEN__INTEN_MASK 0xf +#define MP0_DISP_TIMER1_INTEN__INTEN__SHIFT 0x0 +#define MP0_DISP_TIMER1_INTEN__RESERVED_MASK 0xfffffff0 +#define MP0_DISP_TIMER1_INTEN__RESERVED__SHIFT 0x4 +#define MP0_DISP_TIMER1_OCMP_0_0__OCMP_MASK 0xffffffff +#define MP0_DISP_TIMER1_OCMP_0_0__OCMP__SHIFT 0x0 +#define MP0_DISP_TIMER1_OCMP_0_1__OCMP_MASK 0xffffffff +#define MP0_DISP_TIMER1_OCMP_0_1__OCMP__SHIFT 0x0 +#define MP0_DISP_TIMER1_CNT__COUNT_MASK 0xffffffff +#define MP0_DISP_TIMER1_CNT__COUNT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_0__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_0__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_1__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_1__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_2__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_2__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_3__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_3__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_4__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_4__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_5__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_5__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_6__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_6__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_7__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_7__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_8__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_8__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_9__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_9__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_10__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_10__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_11__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_11__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_12__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_12__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_13__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_13__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_14__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_14__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_15__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_15__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_0__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_0__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_1__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_1__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_2__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_2__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_3__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_3__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_4__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_4__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_5__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_5__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_6__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_6__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_7__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_7__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_8__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_8__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_9__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_9__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_10__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_10__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_11__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_11__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_12__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_12__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_13__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_13__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_14__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_14__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_15__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_15__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_0__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_0__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_1__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_1__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_2__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_2__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_3__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_3__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_4__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_4__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_5__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_5__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_6__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_6__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_7__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_7__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_8__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_8__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_9__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_9__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_10__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_10__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_11__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_11__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_12__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_12__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_13__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_13__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_14__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_14__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_15__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_15__CONTENT__SHIFT 0x0 +#define SMU_MP1_ACP2MP_RESP__CONTENT_MASK 0xffffffff +#define SMU_MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0 +#define SMU_MP1_DC2MP_RESP__CONTENT_MASK 0xffffffff +#define SMU_MP1_DC2MP_RESP__CONTENT__SHIFT 0x0 +#define SMU_MP1_UVD2MP_RESP__CONTENT_MASK 0xffffffff +#define SMU_MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0 +#define SMU_MP1_VCE2MP_RESP__CONTENT_MASK 0xffffffff +#define SMU_MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0 +#define SMU_MP1_RLC2MP_RESP__CONTENT_MASK 0xffffffff +#define SMU_MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0 +#define MP_FPS_CNT__FPS_CNT_MASK 0xffffffff +#define MP_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT_MASK 0x1 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT__SHIFT 0x0 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK__SHIFT 0x1 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE_MASK 0x4 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK_MASK 0x8 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK__SHIFT 0x3 +#define SMU_DISP0_TIMER_INT_CONTROL__MASK_MASK 0x10 +#define SMU_DISP0_TIMER_INT_CONTROL__MASK__SHIFT 0x4 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT_MASK 0x1 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT__SHIFT 0x0 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK__SHIFT 0x1 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE_MASK 0x4 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK_MASK 0x8 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK__SHIFT 0x3 +#define SMU_DISP1_TIMER_INT_CONTROL__MASK_MASK 0x10 +#define SMU_DISP1_TIMER_INT_CONTROL__MASK__SHIFT 0x4 +#define SMU_SRBM_CONFIG__MSTR_CREDITS_MASK 0x1f +#define SMU_SRBM_CONFIG__MSTR_CREDITS__SHIFT 0x0 +#define MP_FPS_CNT_XBAR__FPS_CNT_MASK 0xffffffff +#define MP_FPS_CNT_XBAR__FPS_CNT__SHIFT 0x0 +#define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS_MASK 0x1f +#define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS__SHIFT 0x0 +#define MP_SRBM_CONTROL__ACC_VIO_EN_MASK 0x1 +#define MP_SRBM_CONTROL__ACC_VIO_EN__SHIFT 0x0 +#define MP_SRBM_CONTROL__ALLOW_NS_ACC_MASK 0x2 +#define MP_SRBM_CONTROL__ALLOW_NS_ACC__SHIFT 0x1 +#define MP_SRBM_CONTROL__SOFT_RST_MASK_MASK 0x4 +#define MP_SRBM_CONTROL__SOFT_RST_MASK__SHIFT 0x2 +#define MP_SRBM_CONTROL__SOFT_RST_STS_MASK 0x8 +#define MP_SRBM_CONTROL__SOFT_RST_STS__SHIFT 0x3 +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP_MASK 0x1 +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT 0x0 +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID_MASK 0xe +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID__SHIFT 0x1 +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID_MASK 0x80000000 +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT 0x1f +#define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK 0xffffffff +#define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT 0x0 +#define MP_CRBBM_CONTROL__ACC_VIO_EN_MASK 0x1 +#define MP_CRBBM_CONTROL__ACC_VIO_EN__SHIFT 0x0 +#define MP_CRBBM_CONTROL__MP0_ACCESS_MASK 0x2 +#define MP_CRBBM_CONTROL__MP0_ACCESS__SHIFT 0x1 +#define MP_CRBBM_CONTROL__ALLOW_NS_ACC_MASK 0x4 +#define MP_CRBBM_CONTROL__ALLOW_NS_ACC__SHIFT 0x2 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP_MASK 0x1 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT 0x0 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF_MASK 0x2 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF__SHIFT 0x1 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID_MASK 0x80000000 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT 0x1f +#define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK 0xffffffff +#define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_CNTL__tag_MASK 0x1ffff +#define MP_DRAM_CNTL_WRREQ_CNTL__tag__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_CNTL__urg_MASK 0x1e0000 +#define MP_DRAM_CNTL_WRREQ_CNTL__urg__SHIFT 0x11 +#define MP_DRAM_CNTL_WRREQ_CNTL__stall_MASK 0x200000 +#define MP_DRAM_CNTL_WRREQ_CNTL__stall__SHIFT 0x15 +#define MP_DRAM_CNTL_WRREQ_CNTL__priv_MASK 0x400000 +#define MP_DRAM_CNTL_WRREQ_CNTL__priv__SHIFT 0x16 +#define MP_DRAM_CNTL_WRREQ_CNTL__cid_MASK 0xff800000 +#define MP_DRAM_CNTL_WRREQ_CNTL__cid__SHIFT 0x17 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vf_MASK 0x1 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vf__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid_MASK 0xfe +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid__SHIFT 0x1 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__physical_MASK 0x100 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__physical__SHIFT 0x8 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop_MASK 0x200 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop__SHIFT 0x9 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__inval_MASK 0x400 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__inval__SHIFT 0xa +#define MP_DRAM_CNTL_WRREQ_CNTL_1__op_MASK 0x3f800 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__op__SHIFT 0xb +#define MP_DRAM_CNTL_WRREQ_CNTL_1__swap_MASK 0x300000 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__swap__SHIFT 0x14 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid_MASK 0x3c00000 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid__SHIFT 0x16 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__atc_MASK 0x4000000 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__atc__SHIFT 0x1a +#define MP_DRAM_CNTL_WRREQ_CNTL_1__fed_MASK 0x8000000 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__fed__SHIFT 0x1b +#define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37_MASK 0x7ff +#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved_MASK 0xfffff800 +#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved__SHIFT 0xb +#define MP_DRAM_CNTL_WRREQ_MASK__mask_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_MASK__mask__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_0__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_0__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_1__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_1__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_2__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_2__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_3__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_3__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_4__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_4__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_5__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_5__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_6__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_6__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_7__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_7__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter_MASK 0x1f +#define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved0_MASK 0xe0 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved0__SHIFT 0x5 +#define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty_MASK 0x100 +#define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty__SHIFT 0x8 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved1_MASK 0xfe00 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved1__SHIFT 0x9 +#define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer_MASK 0xf0000 +#define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer__SHIFT 0x10 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved2_MASK 0xfff00000 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved2__SHIFT 0x14 +#define MP_DRAM_CNTL_WRRET_STATUS_0__valid_MASK 0x1 +#define MP_DRAM_CNTL_WRRET_STATUS_0__valid__SHIFT 0x0 +#define MP_DRAM_CNTL_WRRET_STATUS_0__nack_MASK 0x6 +#define MP_DRAM_CNTL_WRRET_STATUS_0__nack__SHIFT 0x1 +#define MP_DRAM_CNTL_WRRET_STATUS_0__reserved_MASK 0xfff8 +#define MP_DRAM_CNTL_WRRET_STATUS_0__reserved__SHIFT 0x3 +#define MP_DRAM_CNTL_WRRET_STATUS_0__tag_MASK 0xffff0000 +#define MP_DRAM_CNTL_WRRET_STATUS_0__tag__SHIFT 0x10 +#define MP_DRAM_CNTL_RDREQ_ADDR__addr_MASK 0xffffffff +#define MP_DRAM_CNTL_RDREQ_ADDR__addr__SHIFT 0x0 +#define MP_DRAM_CNTL_RDREQ_CNTL__tag_MASK 0xffff +#define MP_DRAM_CNTL_RDREQ_CNTL__tag__SHIFT 0x0 +#define MP_DRAM_CNTL_RDREQ_CNTL__mask_MASK 0xff0000 +#define MP_DRAM_CNTL_RDREQ_CNTL__mask__SHIFT 0x10 +#define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40_MASK 0xff000000 +#define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40__SHIFT 0x18 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__urg_MASK 0xf +#define MP_DRAM_CNTL_RDREQ_CNTL_1__urg__SHIFT 0x0 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__stall_MASK 0x10 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__stall__SHIFT 0x4 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__priv_MASK 0x20 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__priv__SHIFT 0x5 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__swap_MASK 0xc0 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__swap__SHIFT 0x6 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__cid_MASK 0x1ff00 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__cid__SHIFT 0x8 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid_MASK 0x1e0000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid__SHIFT 0x11 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__atc_MASK 0x200000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__atc__SHIFT 0x15 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__physical_MASK 0x400000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__physical__SHIFT 0x16 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__exe_MASK 0x800000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__exe__SHIFT 0x17 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop_MASK 0x1000000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop__SHIFT 0x18 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__shared_MASK 0x2000000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__shared__SHIFT 0x19 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vf_MASK 0x4000000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vf__SHIFT 0x1a +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid_MASK 0xf8000000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid__SHIFT 0x1b +#define MP_DRAM_CNTL_RDRET_VALID__vld_0_MASK 0x1 +#define MP_DRAM_CNTL_RDRET_VALID__vld_0__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_VALID__vld_1_MASK 0x2 +#define MP_DRAM_CNTL_RDRET_VALID__vld_1__SHIFT 0x1 +#define MP_DRAM_CNTL_RDRET_VALID__vld_2_MASK 0x4 +#define MP_DRAM_CNTL_RDRET_VALID__vld_2__SHIFT 0x2 +#define MP_DRAM_CNTL_RDRET_VALID__vld_3_MASK 0x8 +#define MP_DRAM_CNTL_RDRET_VALID__vld_3__SHIFT 0x3 +#define MP_DRAM_CNTL_RDRET_VALID__vld_4_MASK 0x10 +#define MP_DRAM_CNTL_RDRET_VALID__vld_4__SHIFT 0x4 +#define MP_DRAM_CNTL_RDRET_VALID__vld_5_MASK 0x20 +#define MP_DRAM_CNTL_RDRET_VALID__vld_5__SHIFT 0x5 +#define MP_DRAM_CNTL_RDRET_VALID__vld_6_MASK 0x40 +#define MP_DRAM_CNTL_RDRET_VALID__vld_6__SHIFT 0x6 +#define MP_DRAM_CNTL_RDRET_VALID__vld_7_MASK 0x80 +#define MP_DRAM_CNTL_RDRET_VALID__vld_7__SHIFT 0x7 +#define MP_DRAM_CNTL_RDRET_VALID__reserved_MASK 0xffff00 +#define MP_DRAM_CNTL_RDRET_VALID__reserved__SHIFT 0x8 +#define MP_DRAM_CNTL_RDRET_VALID__atomic_MASK 0xff000000 +#define MP_DRAM_CNTL_RDRET_VALID__atomic__SHIFT 0x18 +#define MP_DRAM_CNTL_RDRET_NACK__nack_0_MASK 0x3 +#define MP_DRAM_CNTL_RDRET_NACK__nack_0__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_NACK__nack_1_MASK 0xc +#define MP_DRAM_CNTL_RDRET_NACK__nack_1__SHIFT 0x2 +#define MP_DRAM_CNTL_RDRET_NACK__nack_2_MASK 0x30 +#define MP_DRAM_CNTL_RDRET_NACK__nack_2__SHIFT 0x4 +#define MP_DRAM_CNTL_RDRET_NACK__nack_3_MASK 0xc0 +#define MP_DRAM_CNTL_RDRET_NACK__nack_3__SHIFT 0x6 +#define MP_DRAM_CNTL_RDRET_NACK__nack_4_MASK 0x300 +#define MP_DRAM_CNTL_RDRET_NACK__nack_4__SHIFT 0x8 +#define MP_DRAM_CNTL_RDRET_NACK__nack_5_MASK 0xc00 +#define MP_DRAM_CNTL_RDRET_NACK__nack_5__SHIFT 0xa +#define MP_DRAM_CNTL_RDRET_NACK__nack_6_MASK 0x3000 +#define MP_DRAM_CNTL_RDRET_NACK__nack_6__SHIFT 0xc +#define MP_DRAM_CNTL_RDRET_NACK__nack_7_MASK 0xc000 +#define MP_DRAM_CNTL_RDRET_NACK__nack_7__SHIFT 0xe +#define MP_DRAM_CNTL_RDRET_NACK__reserved_MASK 0xffff0000 +#define MP_DRAM_CNTL_RDRET_NACK__reserved__SHIFT 0x10 +#define MP_DRAM_CNTL_RDRET_DATA_0__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_0__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_1__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_1__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_2__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_2__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_3__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_3__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_4__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_4__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_5__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_5__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_6__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_6__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_7__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_7__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_8__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_8__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_9__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_9__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_10__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_10__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_11__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_11__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_12__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_12__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_13__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_13__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_14__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_14__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_15__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_15__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_16__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_16__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_17__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_17__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_18__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_18__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_19__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_19__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_20__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_20__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_21__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_21__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_22__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_22__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_23__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_23__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_24__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_24__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_25__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_25__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_26__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_26__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_27__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_27__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_28__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_28__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_29__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_29__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_30__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_30__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_31__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_31__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_32__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_32__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_33__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_33__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_34__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_34__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_35__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_35__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_36__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_36__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_37__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_37__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_38__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_38__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_39__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_39__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_40__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_40__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_41__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_41__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_42__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_42__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_43__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_43__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_44__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_44__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_45__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_45__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_46__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_46__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_47__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_47__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_48__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_48__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_49__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_49__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_50__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_50__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_51__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_51__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_52__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_52__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_53__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_53__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_54__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_54__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_55__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_55__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_56__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_56__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_57__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_57__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_58__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_58__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_59__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_59__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_60__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_60__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_61__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_61__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_62__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_62__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_63__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_63__DATA__SHIFT 0x0 +#define MP_IOC_CTRL__IOC_mst_send_MASK 0x1 +#define MP_IOC_CTRL__IOC_mst_send__SHIFT 0x0 +#define MP_IOC_CTRL__IOC_mst_stop_MASK 0x2 +#define MP_IOC_CTRL__IOC_mst_stop__SHIFT 0x1 +#define MP_IOC_CTRL__IOC_mst_force_active_MASK 0x4 +#define MP_IOC_CTRL__IOC_mst_force_active__SHIFT 0x2 +#define MP_IOC_CTRL__IOC_mst_rdValid_MASK 0x8 +#define MP_IOC_CTRL__IOC_mst_rdValid__SHIFT 0x3 +#define MP_IOC_CTRL__IOC_mst_busy_MASK 0x10 +#define MP_IOC_CTRL__IOC_mst_busy__SHIFT 0x4 +#define MP_IOC_CTRL__IOC_mst_disabled_MASK 0x20 +#define MP_IOC_CTRL__IOC_mst_disabled__SHIFT 0x5 +#define MP_IOC_CTRL__IOC_mst_debug_rst_MASK 0x40 +#define MP_IOC_CTRL__IOC_mst_debug_rst__SHIFT 0x6 +#define MP_IOC_CTRL__IOC_mst_stop_ack_MASK 0x80 +#define MP_IOC_CTRL__IOC_mst_stop_ack__SHIFT 0x7 +#define MP_IOC_CTRL__IOC_mst_rderr_MASK 0x300 +#define MP_IOC_CTRL__IOC_mst_rderr__SHIFT 0x8 +#define MP_IOC_RDDATA__IOC_mst_rdData_MASK 0xffffffff +#define MP_IOC_RDDATA__IOC_mst_rdData__SHIFT 0x0 +#define MP_IOC_PHASE1__BiuCqfC_AwqReqCommit_MASK 0x2 +#define MP_IOC_PHASE1__BiuCqfC_AwqReqCommit__SHIFT 0x1 +#define MP_IOC_PHASE1__BiuCqfC_AltReqRdCmd_MASK 0x4 +#define MP_IOC_PHASE1__BiuCqfC_AltReqRdCmd__SHIFT 0x2 +#define MP_IOC_PHASE1__BiuCqfC_AltReqAddrLo_MASK 0xfffffff8 +#define MP_IOC_PHASE1__BiuCqfC_AltReqAddrLo__SHIFT 0x3 +#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrMid_MASK 0xff +#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrMid__SHIFT 0x0 +#define MP_IOC_PHASE2__BiuCqfC_AltReqMask_MASK 0xff00 +#define MP_IOC_PHASE2__BiuCqfC_AltReqMask__SHIFT 0x8 +#define MP_IOC_PHASE2__BiuCqfC_AltReqSize_MASK 0x30000 +#define MP_IOC_PHASE2__BiuCqfC_AltReqSize__SHIFT 0x10 +#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrHi_MASK 0xff000000 +#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrHi__SHIFT 0x18 +#define MP_IOC_PHASE3__BiuDbfC_C2aDataOut_MASK 0xffffffff +#define MP_IOC_PHASE3__BiuDbfC_C2aDataOut__SHIFT 0x0 +#define MP_IOC_READ_0__data_MASK 0xffffffff +#define MP_IOC_READ_0__data__SHIFT 0x0 +#define MP_IOC_READ_1__data_MASK 0xffffffff +#define MP_IOC_READ_1__data__SHIFT 0x0 +#define MP_IOC_READ_2__data_MASK 0xffffffff +#define MP_IOC_READ_2__data__SHIFT 0x0 +#define MP_IOC_READ_3__data_MASK 0xffffffff +#define MP_IOC_READ_3__data__SHIFT 0x0 +#define MP_IOC_READ_4__data_MASK 0xffffffff +#define MP_IOC_READ_4__data__SHIFT 0x0 +#define MP_IOC_READ_5__data_MASK 0xffffffff +#define MP_IOC_READ_5__data__SHIFT 0x0 +#define MP_IOC_READ_6__data_MASK 0xffffffff +#define MP_IOC_READ_6__data__SHIFT 0x0 +#define MP_IOC_READ_7__data_MASK 0xffffffff +#define MP_IOC_READ_7__data__SHIFT 0x0 +#define MP_IOC_READ_8__data_MASK 0xffffffff +#define MP_IOC_READ_8__data__SHIFT 0x0 +#define MP_IOC_READ_9__data_MASK 0xffffffff +#define MP_IOC_READ_9__data__SHIFT 0x0 +#define MP_IOC_READ_10__data_MASK 0xffffffff +#define MP_IOC_READ_10__data__SHIFT 0x0 +#define MP_IOC_READ_11__data_MASK 0xffffffff +#define MP_IOC_READ_11__data__SHIFT 0x0 +#define MP_IOC_READ_12__data_MASK 0xffffffff +#define MP_IOC_READ_12__data__SHIFT 0x0 +#define MP_IOC_READ_13__data_MASK 0xffffffff +#define MP_IOC_READ_13__data__SHIFT 0x0 +#define MP_IOC_READ_14__data_MASK 0xffffffff +#define MP_IOC_READ_14__data__SHIFT 0x0 +#define MP_IOC_READ_15__data_MASK 0xffffffff +#define MP_IOC_READ_15__data__SHIFT 0x0 +#define MP_IOC_WRITE_0__data_MASK 0xffffffff +#define MP_IOC_WRITE_0__data__SHIFT 0x0 +#define MP_IOC_WRITE_1__data_MASK 0xffffffff +#define MP_IOC_WRITE_1__data__SHIFT 0x0 +#define MP_IOC_WRITE_2__data_MASK 0xffffffff +#define MP_IOC_WRITE_2__data__SHIFT 0x0 +#define MP_IOC_WRITE_3__data_MASK 0xffffffff +#define MP_IOC_WRITE_3__data__SHIFT 0x0 +#define MP_IOC_WRITE_4__data_MASK 0xffffffff +#define MP_IOC_WRITE_4__data__SHIFT 0x0 +#define MP_IOC_WRITE_5__data_MASK 0xffffffff +#define MP_IOC_WRITE_5__data__SHIFT 0x0 +#define MP_IOC_WRITE_6__data_MASK 0xffffffff +#define MP_IOC_WRITE_6__data__SHIFT 0x0 +#define MP_IOC_WRITE_7__data_MASK 0xffffffff +#define MP_IOC_WRITE_7__data__SHIFT 0x0 +#define MP_IOC_WRITE_8__data_MASK 0xffffffff +#define MP_IOC_WRITE_8__data__SHIFT 0x0 +#define MP_IOC_WRITE_9__data_MASK 0xffffffff +#define MP_IOC_WRITE_9__data__SHIFT 0x0 +#define MP_IOC_WRITE_10__data_MASK 0xffffffff +#define MP_IOC_WRITE_10__data__SHIFT 0x0 +#define MP_IOC_WRITE_11__data_MASK 0xffffffff +#define MP_IOC_WRITE_11__data__SHIFT 0x0 +#define MP_IOC_WRITE_12__data_MASK 0xffffffff +#define MP_IOC_WRITE_12__data__SHIFT 0x0 +#define MP_IOC_WRITE_13__data_MASK 0xffffffff +#define MP_IOC_WRITE_13__data__SHIFT 0x0 +#define MP_IOC_WRITE_14__data_MASK 0xffffffff +#define MP_IOC_WRITE_14__data__SHIFT 0x0 +#define MP_IOC_WRITE_15__data_MASK 0xffffffff +#define MP_IOC_WRITE_15__data__SHIFT 0x0 +#define MP_INTERRUPT_CONTROL__MAX_CREDIT_VALUE_MASK 0x1f +#define MP_INTERRUPT_CONTROL__MAX_CREDIT_VALUE__SHIFT 0x0 +#define MP_INTERRUPT_CONTROL__MP0_SW_TRIG_MASK_MASK 0x20 +#define MP_INTERRUPT_CONTROL__MP0_SW_TRIG_MASK__SHIFT 0x5 +#define MP_INTERRUPT_CONTROL__MP0_SW_INT_ACK_MASK 0x40 +#define MP_INTERRUPT_CONTROL__MP0_SW_INT_ACK__SHIFT 0x6 +#define MP_INTERRUPT_CONTROL__MP1_SW_TRIG_MASK_MASK 0x80 +#define MP_INTERRUPT_CONTROL__MP1_SW_TRIG_MASK__SHIFT 0x7 +#define MP_INTERRUPT_CONTROL__MP1_SW_INT_ACK_MASK 0x100 +#define MP_INTERRUPT_CONTROL__MP1_SW_INT_ACK__SHIFT 0x8 +#define MP0_SW_INT__VALID_MASK 0x1 +#define MP0_SW_INT__VALID__SHIFT 0x0 +#define MP0_SW_INT__INT_ID_MASK 0x1fe +#define MP0_SW_INT__INT_ID__SHIFT 0x1 +#define MP0_SW_INT_CTXID__CTXID_MASK 0xfffffff +#define MP0_SW_INT_CTXID__CTXID__SHIFT 0x0 +#define MP1_SW_INT__VALID_MASK 0x1 +#define MP1_SW_INT__VALID__SHIFT 0x0 +#define MP1_SW_INT__INT_ID_MASK 0x1fe +#define MP1_SW_INT__INT_ID__SHIFT 0x1 +#define MP1_SW_INT_CTXID__CTXID_MASK 0xfffffff +#define MP1_SW_INT_CTXID__CTXID__SHIFT 0x0 +#define DISP_TIMER_ID__DISP_T0_INT_ID_MASK 0xff +#define DISP_TIMER_ID__DISP_T0_INT_ID__SHIFT 0x0 +#define DISP_TIMER_ID__DISP_T1_INT_ID_MASK 0xff00 +#define DISP_TIMER_ID__DISP_T1_INT_ID__SHIFT 0x8 +#define PWRHW_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define PWRHW_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define PWRHW_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define PWRHW_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CURRENT_STATE_CPU0__CURRENT_PSTATE_ID_MASK 0x7 +#define CURRENT_STATE_CPU0__CURRENT_PSTATE_ID__SHIFT 0x0 +#define CURRENT_STATE_CPU0__CURRENT_DID_MASK 0x38 +#define CURRENT_STATE_CPU0__CURRENT_DID__SHIFT 0x3 +#define CURRENT_STATE_CPU0__CURRENT_FID_MASK 0xfc0 +#define CURRENT_STATE_CPU0__CURRENT_FID__SHIFT 0x6 +#define CURRENT_STATE_CPU0__CPU_COF_MASK 0xfff000 +#define CURRENT_STATE_CPU0__CPU_COF__SHIFT 0xc +#define CURRENT_STATE_CPU0__CPU_COF_IND_PROG_MASK 0x7f000000 +#define CURRENT_STATE_CPU0__CPU_COF_IND_PROG__SHIFT 0x18 +#define CURRENT_STATE_CPU1__CURRENT_PSTATE_ID_MASK 0x7 +#define CURRENT_STATE_CPU1__CURRENT_PSTATE_ID__SHIFT 0x0 +#define CURRENT_STATE_CPU1__CURRENT_DID_MASK 0x38 +#define CURRENT_STATE_CPU1__CURRENT_DID__SHIFT 0x3 +#define CURRENT_STATE_CPU1__CURRENT_FID_MASK 0xfc0 +#define CURRENT_STATE_CPU1__CURRENT_FID__SHIFT 0x6 +#define CURRENT_STATE_CPU1__CPU_COF_MASK 0xfff000 +#define CURRENT_STATE_CPU1__CPU_COF__SHIFT 0xc +#define CURRENT_STATE_CPU1__CPU_COF_IND_PROG_MASK 0x7f000000 +#define CURRENT_STATE_CPU1__CPU_COF_IND_PROG__SHIFT 0x18 +#define CPU_REDUN_DONE0__CPU_REDUN_DONE_MASK 0x1 +#define CPU_REDUN_DONE0__CPU_REDUN_DONE__SHIFT 0x0 +#define CPU_REDUN_DONE1__CPU_REDUN_DONE_MASK 0x1 +#define CPU_REDUN_DONE1__CPU_REDUN_DONE__SHIFT 0x0 +#define CURRENT_VID_CPU0__CURRENT_VID_MASK 0xff +#define CURRENT_VID_CPU0__CURRENT_VID__SHIFT 0x0 +#define CURRENT_VID_CPU1__CURRENT_VID_MASK 0xff +#define CURRENT_VID_CPU1__CURRENT_VID__SHIFT 0x0 +#define UNBPM_PWRMGT_ACK__REQUESTOR_CODE_MASK 0x1f +#define UNBPM_PWRMGT_ACK__REQUESTOR_CODE__SHIFT 0x0 +#define UNBPM_PWRMGT_ACK__REQUEST_ACK_MASK 0x100 +#define UNBPM_PWRMGT_ACK__REQUEST_ACK__SHIFT 0x8 +#define UNBPM_PWRMGT_ACK__REQUEST_NACK_MASK 0x10000 +#define UNBPM_PWRMGT_ACK__REQUEST_NACK__SHIFT 0x10 +#define UNBPM_PWRMGT_ACK__ERROR_CODE_MASK 0xff000000 +#define UNBPM_PWRMGT_ACK__ERROR_CODE__SHIFT 0x18 +#define CURRENT_FREQ_STATE_NB__CURRENT_FID_MASK 0xff +#define CURRENT_FREQ_STATE_NB__CURRENT_FID__SHIFT 0x0 +#define CURRENT_FREQ_STATE_NB__CURRENT_DID_MASK 0xff00 +#define CURRENT_FREQ_STATE_NB__CURRENT_DID__SHIFT 0x8 +#define CURRENT_FREQ_STATE_NB__NB_LOW_POWER_MASK 0xff0000 +#define CURRENT_FREQ_STATE_NB__NB_LOW_POWER__SHIFT 0x10 +#define CURRENT_FREQ_STATE_NB__NB_STUTTER_MODE_MASK 0xff000000 +#define CURRENT_FREQ_STATE_NB__NB_STUTTER_MODE__SHIFT 0x18 +#define CURRENT_PSTATE_NB__CURRENT_PSTATE_ID_MASK 0xff +#define CURRENT_PSTATE_NB__CURRENT_PSTATE_ID__SHIFT 0x0 +#define CURRENT_PSTATE_NB__CURRENT_PSTATE_LO_MASK 0x100 +#define CURRENT_PSTATE_NB__CURRENT_PSTATE_LO__SHIFT 0x8 +#define CURRENT_PSTATE_NB__CURRENT_MEM_PSTATE_ID_MASK 0x200 +#define CURRENT_PSTATE_NB__CURRENT_MEM_PSTATE_ID__SHIFT 0x9 +#define UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR_MASK 0xffffffff +#define UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR__SHIFT 0x0 +#define UNBPM_NBPWRMGT_CMD__TARGET_BLOCK_MASK 0x3 +#define UNBPM_NBPWRMGT_CMD__TARGET_BLOCK__SHIFT 0x0 +#define UNBPM_NBPWRMGT_CMD__TARGET_CMD_MASK 0x100 +#define UNBPM_NBPWRMGT_CMD__TARGET_CMD__SHIFT 0x8 +#define UNBPM_NBPWRMGT_CMD__DCT_SR_MAP_MASK 0xff0000 +#define UNBPM_NBPWRMGT_CMD__DCT_SR_MAP__SHIFT 0x10 +#define UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK_MASK 0x1000000 +#define UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK__SHIFT 0x18 +#define UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS_MASK 0x2000000 +#define UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS__SHIFT 0x19 +#define UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER_MASK 0x4000000 +#define UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER__SHIFT 0x1a +#define UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE_MASK 0x8000000 +#define UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE__SHIFT 0x1b +#define UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT_MASK 0x2 +#define UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT__SHIFT 0x1 +#define DDR0_FUSE_SSB_XFER__START_STATUS_XFER_MASK 0x1 +#define DDR0_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT 0x0 +#define DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR_MASK 0x7ff +#define DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR__SHIFT 0x0 +#define DDR1_FUSE_SSB_XFER__START_STATUS_XFER_MASK 0x1 +#define DDR1_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT 0x0 +#define DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR_MASK 0x7ff +#define DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR__SHIFT 0x0 +#define UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK_MASK 0x1 +#define UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK__SHIFT 0x0 +#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER0_MASK 0x1 +#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER0__SHIFT 0x0 +#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER1_MASK 0x2 +#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER1__SHIFT 0x1 +#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER0_MASK 0x4 +#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER0__SHIFT 0x2 +#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER1_MASK 0x8 +#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER1__SHIFT 0x3 +#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN0_MASK 0x10 +#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN0__SHIFT 0x4 +#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN1_MASK 0x20 +#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN1__SHIFT 0x5 +#define MISC_SMU_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff +#define MISC_SMU_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0 +#define MISC_GNB_PWRMGT_CFG1__TIMER_EN_MASK 0x1 +#define MISC_GNB_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0 +#define MISC_GNB_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe +#define MISC_GNB_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1 +#define MISC_GNB_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000 +#define MISC_GNB_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11 +#define MISC_SMU_PWRMGT_CFG1__TIMER_EN_MASK 0x1 +#define MISC_SMU_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0 +#define MISC_SMU_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe +#define MISC_SMU_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1 +#define MISC_SMU_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000 +#define MISC_SMU_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11 +#define MISC_GNB_PWRMGT_DATA__GN_ON_INB_WAKE_MASK 0x1 +#define MISC_GNB_PWRMGT_DATA__GN_ON_INB_WAKE__SHIFT 0x0 +#define MISC_GNB_PWRMGT_DATA__GN_ALLOW_NB_PSTATES_MASK 0x2 +#define MISC_GNB_PWRMGT_DATA__GN_ALLOW_NB_PSTATES__SHIFT 0x1 +#define MISC_GNB_PWRMGT_DATA__GN_FLUSH_REQ_TOGGLE_MASK 0x4 +#define MISC_GNB_PWRMGT_DATA__GN_FLUSH_REQ_TOGGLE__SHIFT 0x2 +#define MISC_GNB_PWRMGT_DATA__GN_CROSS_TRIGGER_MASK 0x78 +#define MISC_GNB_PWRMGT_DATA__GN_CROSS_TRIGGER__SHIFT 0x3 +#define MISC_GNB_PWRMGT_DATA__GN_STOP_CLOCKS_MASK 0x80 +#define MISC_GNB_PWRMGT_DATA__GN_STOP_CLOCKS__SHIFT 0x7 +#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH0LINK_WAKE_MASK 0x100 +#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH0LINK_WAKE__SHIFT 0x8 +#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH1LINK_WAKE_MASK 0x200 +#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH1LINK_WAKE__SHIFT 0x9 +#define GN_GNB_SLOW__GN_GNB_SLOW_DATA_MASK 0x1 +#define GN_GNB_SLOW__GN_GNB_SLOW_DATA__SHIFT 0x0 +#define GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA_MASK 0x1 +#define GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA__SHIFT 0x0 +#define MISC_SMU_PWRMGT_DATA__NB_NBPS_MASK 0x1 +#define MISC_SMU_PWRMGT_DATA__NB_NBPS__SHIFT 0x0 +#define MISC_SMU_PWRMGT_DATA__NB_MEMPS_MASK 0x2 +#define MISC_SMU_PWRMGT_DATA__NB_MEMPS__SHIFT 0x1 +#define NB_COF__NB_COF_MASK 0xffff +#define NB_COF__NB_COF__SHIFT 0x0 +#define UNBPM_CK_IRESET__CK_IRESET_LOCAL_MASK 0x1 +#define UNBPM_CK_IRESET__CK_IRESET_LOCAL__SHIFT 0x0 +#define CURRENT_VID_NB__CURRENT_VID_MASK 0xff +#define CURRENT_VID_NB__CURRENT_VID__SHIFT 0x0 +#define SPR_FUSE_PSTATEPWR1__PwrValue0_MASK 0xff +#define SPR_FUSE_PSTATEPWR1__PwrValue0__SHIFT 0x0 +#define SPR_FUSE_PSTATEPWR1__PwrValue1_MASK 0xff00 +#define SPR_FUSE_PSTATEPWR1__PwrValue1__SHIFT 0x8 +#define SPR_FUSE_PSTATEPWR1__PwrValue2_MASK 0xff0000 +#define SPR_FUSE_PSTATEPWR1__PwrValue2__SHIFT 0x10 +#define SPR_FUSE_PSTATEPWR1__PwrValue3_MASK 0xff000000 +#define SPR_FUSE_PSTATEPWR1__PwrValue3__SHIFT 0x18 +#define SPR_FUSE_PSTATEPWR2__PwrValue4_MASK 0xff +#define SPR_FUSE_PSTATEPWR2__PwrValue4__SHIFT 0x0 +#define SPR_FUSE_PSTATEPWR2__PwrDiv0_MASK 0x300 +#define SPR_FUSE_PSTATEPWR2__PwrDiv0__SHIFT 0x8 +#define SPR_FUSE_PSTATEPWR2__PwrDiv1_MASK 0xc00 +#define SPR_FUSE_PSTATEPWR2__PwrDiv1__SHIFT 0xa +#define SPR_FUSE_PSTATEPWR2__PwrDiv2_MASK 0x3000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv2__SHIFT 0xc +#define SPR_FUSE_PSTATEPWR2__PwrDiv3_MASK 0xc000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv3__SHIFT 0xe +#define SPR_FUSE_PSTATEPWR2__PwrDiv4_MASK 0x30000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv4__SHIFT 0x10 +#define SPR_FUSE_PSTATEPWR2__PwrDiv5_MASK 0xc0000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv5__SHIFT 0x12 +#define SPR_FUSE_PSTATEPWR2__PwrDiv6_MASK 0x300000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv6__SHIFT 0x14 +#define SPR_FUSE_PSTATEPWR2__PwrDiv7_MASK 0xc00000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv7__SHIFT 0x16 +#define SPR_FUSE_PSTATEPWR2__Reserved_MASK 0xff000000 +#define SPR_FUSE_PSTATEPWR2__Reserved__SHIFT 0x18 +#define SPR_FUSE_PSTATEPWR3__PwrValue5_MASK 0xff +#define SPR_FUSE_PSTATEPWR3__PwrValue5__SHIFT 0x0 +#define SPR_FUSE_PSTATEPWR3__PwrValue6_MASK 0xff00 +#define SPR_FUSE_PSTATEPWR3__PwrValue6__SHIFT 0x8 +#define SPR_FUSE_PSTATEPWR3__PwrValue7_MASK 0xff0000 +#define SPR_FUSE_PSTATEPWR3__PwrValue7__SHIFT 0x10 +#define SPR_FUSE_PSTATEPWR3__Reserved_MASK 0xff000000 +#define SPR_FUSE_PSTATEPWR3__Reserved__SHIFT 0x18 +#define SPR_FUSE_THERMAL_SCRATCH__ThermalScratch_MASK 0xffffffff +#define SPR_FUSE_THERMAL_SCRATCH__ThermalScratch__SHIFT 0x0 +#define SPR_PRODUCT_INFO0__BrandId_MASK 0xffff +#define SPR_PRODUCT_INFO0__BrandId__SHIFT 0x0 +#define SPR_PRODUCT_INFO0__Reserved0_MASK 0x70000 +#define SPR_PRODUCT_INFO0__Reserved0__SHIFT 0x10 +#define SPR_PRODUCT_INFO0__SerialNumRdDis_MASK 0x80000 +#define SPR_PRODUCT_INFO0__SerialNumRdDis__SHIFT 0x13 +#define SPR_PRODUCT_INFO0__Reserved1_MASK 0xfff00000 +#define SPR_PRODUCT_INFO0__Reserved1__SHIFT 0x14 +#define SPR_SERIALNUM_REG1__SPR_SERIALNUM_REG1_MASK 0xffffffff +#define SPR_SERIALNUM_REG1__SPR_SERIALNUM_REG1__SHIFT 0x0 +#define SPR_SERIALNUM_REG2__SPR_SERIALNUM_REG2_MASK 0xffffffff +#define SPR_SERIALNUM_REG2__SPR_SERIALNUM_REG2__SHIFT 0x0 +#define SPR_PRODUCT_INFO1__DiDtMode_MASK 0x1 +#define SPR_PRODUCT_INFO1__DiDtMode__SHIFT 0x0 +#define SPR_PRODUCT_INFO1__DiDtCfg0_MASK 0x3e +#define SPR_PRODUCT_INFO1__DiDtCfg0__SHIFT 0x1 +#define SPR_PRODUCT_INFO1__DiDtCfg1_MASK 0x3fc0 +#define SPR_PRODUCT_INFO1__DiDtCfg1__SHIFT 0x6 +#define SPR_PRODUCT_INFO1__DiDtCfg2_MASK 0xc000 +#define SPR_PRODUCT_INFO1__DiDtCfg2__SHIFT 0xe +#define SPR_PRODUCT_INFO1__DiDtCfg3_MASK 0x10000 +#define SPR_PRODUCT_INFO1__DiDtCfg3__SHIFT 0x10 +#define SPR_PRODUCT_INFO1__DiDtCfg4_MASK 0x1e0000 +#define SPR_PRODUCT_INFO1__DiDtCfg4__SHIFT 0x11 +#define SPR_PRODUCT_INFO1__Reserved_MASK 0xffe00000 +#define SPR_PRODUCT_INFO1__Reserved__SHIFT 0x15 +#define SPR_EXT_PRODUCT_INFO__Reserved_MASK 0xffffffff +#define SPR_EXT_PRODUCT_INFO__Reserved__SHIFT 0x0 +#define SPR_MSIDFUSE__MSID_MASK 0xffffff +#define SPR_MSIDFUSE__MSID__SHIFT 0x0 +#define SPR_MSIDFUSE__Reserved_MASK 0xff000000 +#define SPR_MSIDFUSE__Reserved__SHIFT 0x18 +#define SPR_LINK_PRODUCT_INFO__Reserved_MASK 0xffffffff +#define SPR_LINK_PRODUCT_INFO__Reserved__SHIFT 0x0 +#define SPR_BRAND_NAME_ADDR__Index_MASK 0xf +#define SPR_BRAND_NAME_ADDR__Index__SHIFT 0x0 +#define SPR_BRAND_NAME_ADDR__Reserved_MASK 0xfffffff0 +#define SPR_BRAND_NAME_ADDR__Reserved__SHIFT 0x4 +#define SPR_BRAND_NAME_DATA__DATA_MASK 0xffffffff +#define SPR_BRAND_NAME_DATA__DATA__SHIFT 0x0 +#define SPR_COMBO_PHY_PRODUCT_INFO__SPR_COMBO_PHY_PRODUCT_INFO_MASK 0xffffffff +#define SPR_COMBO_PHY_PRODUCT_INFO__SPR_COMBO_PHY_PRODUCT_INFO__SHIFT 0x0 +#define MISC_GNB_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff +#define MISC_GNB_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0 +#define UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE_MASK 0x1 +#define UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE__SHIFT 0x0 +#define UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE_MASK 0x1 +#define UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE__SHIFT 0x0 +#define UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE_MASK 0x2 +#define UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE__SHIFT 0x1 +#define UNBPM_VOLTAGE_CNTL__VOLTAGE_EN_MASK 0x1 +#define UNBPM_VOLTAGE_CNTL__VOLTAGE_EN__SHIFT 0x0 +#define UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL_MASK 0x1fe +#define UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL__SHIFT 0x1 +#define UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS_MASK 0x1 +#define UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS__SHIFT 0x0 +#define UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL_MASK 0x1fe +#define UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL__SHIFT 0x1 +#define NUM_BOOST_STATES__NUM_BOOST_STATES_MASK 0x7 +#define NUM_BOOST_STATES__NUM_BOOST_STATES__SHIFT 0x0 +#define WARM_RESET_NB_CONTROL__WARM_RESET_CPU_VID_MASK 0xff +#define WARM_RESET_NB_CONTROL__WARM_RESET_CPU_VID__SHIFT 0x0 +#define WARM_RESET_NB_CONTROL__NB_DISABLE_CORE_MASK 0xff00 +#define WARM_RESET_NB_CONTROL__NB_DISABLE_CORE__SHIFT 0x8 +#define ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND_MASK 0x1 +#define ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND__SHIFT 0x0 +#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0_MASK 0x2 +#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0__SHIFT 0x1 +#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1_MASK 0x4 +#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1__SHIFT 0x2 +#define SPR_PROGRAMMABLE_CTRL__PllRegUpTime_MASK 0x3 +#define SPR_PROGRAMMABLE_CTRL__PllRegUpTime__SHIFT 0x0 +#define SPR_PROGRAMMABLE_CTRL__PllVddOutUpTime_MASK 0xc +#define SPR_PROGRAMMABLE_CTRL__PllVddOutUpTime__SHIFT 0x2 +#define SPR_PROGRAMMABLE_CTRL__ResonanceTime_MASK 0x30 +#define SPR_PROGRAMMABLE_CTRL__ResonanceTime__SHIFT 0x4 +#define SPR_PROGRAMMABLE_CTRL__C6PLLPwrDnReg_MASK 0x40 +#define SPR_PROGRAMMABLE_CTRL__C6PLLPwrDnReg__SHIFT 0x6 +#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnVCO_MASK 0x80 +#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnVCO__SHIFT 0x7 +#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnReg_MASK 0x100 +#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnReg__SHIFT 0x8 +#define SPR_PROGRAMMABLE_CTRL__NbPLLPwrDnReg_MASK 0x200 +#define SPR_PROGRAMMABLE_CTRL__NbPLLPwrDnReg__SHIFT 0x9 +#define SPR_PROGRAMMABLE_CTRL__SOIWait_MASK 0x3c00 +#define SPR_PROGRAMMABLE_CTRL__SOIWait__SHIFT 0xa +#define PHN_FUSERX_MISC_FUSES__Spare_MASK 0xff +#define PHN_FUSERX_MISC_FUSES__Spare__SHIFT 0x0 +#define PHN_FUSERX_MISC_FUSES__OverClockRefClkDis_MASK 0x100 +#define PHN_FUSERX_MISC_FUSES__OverClockRefClkDis__SHIFT 0x8 +#define PHN_FUSERX_MISC_FUSES__MemPstate_MASK 0x1e00 +#define PHN_FUSERX_MISC_FUSES__MemPstate__SHIFT 0x9 +#define PHN_FUSERX_MISC_FUSES__NbPstateHi_MASK 0x6000 +#define PHN_FUSERX_MISC_FUSES__NbPstateHi__SHIFT 0xd +#define PHN_FUSERX_MISC_FUSES__NbPstateLo_MASK 0x18000 +#define PHN_FUSERX_MISC_FUSES__NbPstateLo__SHIFT 0xf +#define PHN_FUSERX_MISC_FUSES__ScanCLK400MHz_MASK 0x20000 +#define PHN_FUSERX_MISC_FUSES__ScanCLK400MHz__SHIFT 0x11 +#define PHN_FUSERX_MISC_FUSES__CoreDis_MASK 0x3c0000 +#define PHN_FUSERX_MISC_FUSES__CoreDis__SHIFT 0x12 +#define PHN_FUSERX_MISC_FUSES__PHN_FusesValid_MASK 0x80000000 +#define PHN_FUSERX_MISC_FUSES__PHN_FusesValid__SHIFT 0x1f +#define UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS_MASK 0x1 +#define UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS__SHIFT 0x0 +#define CSTATE_ACTIVE_SAMPLER__SAMPLE_TIME_MASK 0x1f +#define CSTATE_ACTIVE_SAMPLER__SAMPLE_TIME__SHIFT 0x0 +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS_MASK 0xf +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS__SHIFT 0x0 +#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH_MASK 0x10 +#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH__SHIFT 0x4 +#define UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN_MASK 0x20 +#define UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN__SHIFT 0x5 +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE_MASK 0x100 +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE__SHIFT 0x8 +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY_MASK 0x200 +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY__SHIFT 0x9 +#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT_MASK 0x3c00 +#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT__SHIFT 0xa +#define UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS_MASK 0xff0000 +#define UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS__SHIFT 0x10 +#define UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD_MASK 0xffffffff +#define UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD__SHIFT 0x0 +#define UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT_MASK 0xffff +#define UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT__SHIFT 0x0 +#define UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT_MASK 0xffff0000 +#define UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT__SHIFT 0x10 +#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN_MASK 0x1 +#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN__SHIFT 0x0 +#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM_MASK 0x1fe +#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM__SHIFT 0x1 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb_MASK 0x1 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb__SHIFT 0x0 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct_MASK 0x6 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct__SHIFT 0x1 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu_MASK 0x38 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu__SHIFT 0x3 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog_MASK 0x40 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog__SHIFT 0x6 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo_MASK 0x80 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo__SHIFT 0x7 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate_MASK 0x100 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate__SHIFT 0x8 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid_MASK 0x7e00 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid__SHIFT 0x9 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid_MASK 0x38000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid__SHIFT 0xf +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate_MASK 0x40000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate__SHIFT 0x12 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId_MASK 0x380000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId__SHIFT 0x13 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn_MASK 0x400000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn__SHIFT 0x16 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn_MASK 0x800000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn__SHIFT 0x17 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding_MASK 0x7000000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding__SHIFT 0x18 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid_MASK 0x1 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid__SHIFT 0x0 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane_MASK 0x6 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane__SHIFT 0x1 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp_MASK 0x8 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp__SHIFT 0x3 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid_MASK 0xff0 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid__SHIFT 0x4 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime_MASK 0x7000 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime__SHIFT 0xc +#define UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy_MASK 0x10000 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy__SHIFT 0x10 +#define UNBPM_SCRATCH_0__DATA_MASK 0xffffffff +#define UNBPM_SCRATCH_0__DATA__SHIFT 0x0 +#define UNBPM_SCRATCH_1__DATA_MASK 0xffffffff +#define UNBPM_SCRATCH_1__DATA__SHIFT 0x0 +#define POWERON_CPU_0__POWERON_MASK 0x1 +#define POWERON_CPU_0__POWERON__SHIFT 0x0 +#define POWERREADY_CPU_0__POWERREADY_MASK 0x1 +#define POWERREADY_CPU_0__POWERREADY__SHIFT 0x0 +#define PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK_MASK 0x1 +#define PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK__SHIFT 0x0 +#define RCC3ON_CPU_0__CK_RCC3ON_MASK 0x1 +#define RCC3ON_CPU_0__CK_RCC3ON__SHIFT 0x0 +#define RCC3ON_CPU_0__RCC3_PSM_EN_MASK 0x2 +#define RCC3ON_CPU_0__RCC3_PSM_EN__SHIFT 0x1 +#define RCC3ON_CPU_0__RCC3_PSM_CLK_DIV_MASK 0xc +#define RCC3ON_CPU_0__RCC3_PSM_CLK_DIV__SHIFT 0x2 +#define RCC3ON_CPU_0__RCC3_AVG_EN_MASK 0x10 +#define RCC3ON_CPU_0__RCC3_AVG_EN__SHIFT 0x4 +#define RCC3ON_CPU_0__RCC3_AVG_DIV_MASK 0x7e0 +#define RCC3ON_CPU_0__RCC3_AVG_DIV__SHIFT 0x5 +#define RCC3ON_CPU_0__RCC3_DIDT_TIMER_MASK 0x1f800 +#define RCC3ON_CPU_0__RCC3_DIDT_TIMER__SHIFT 0xb +#define RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0_MASK 0xfffe0000 +#define RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0__SHIFT 0x11 +#define RCC3EXITDONE_CPU_0__RCC3EXITDONE_MASK 0x1 +#define RCC3EXITDONE_CPU_0__RCC3EXITDONE__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_0__START_STATUS_XFER_MASK 0x1 +#define CORE_FUNC_LATE_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_FUNC_LAST_ADDR_MASK 0x7ff +#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_FUNC_LAST_ADDR__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_LATE_LAST_ADDR_MASK 0x7ff0000 +#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_LATE_LAST_ADDR__SHIFT 0x10 +#define CORE_REDUN_SSB_XFER_0__START_STATUS_XFER_MASK 0x1 +#define CORE_REDUN_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0 +#define CORE_REDUN_SSB_XFER_CFG_0__FUSE_REDUN_LAST_ADDR_MASK 0x7ff +#define CORE_REDUN_SSB_XFER_CFG_0__FUSE_REDUN_LAST_ADDR__SHIFT 0x0 +#define CORE_APM_SSB_XFER_0__START_STATUS_XFER_MASK 0x1 +#define CORE_APM_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0 +#define CORE_APM_SSB_XFER_CFG_0__FUSE_APM_LAST_ADDR_MASK 0x7ff +#define CORE_APM_SSB_XFER_CFG_0__FUSE_APM_LAST_ADDR__SHIFT 0x0 +#define COREPM_PWRCTRL_MISC_0__PWRGATEMASTERDIS_MASK 0x1 +#define COREPM_PWRCTRL_MISC_0__PWRGATEMASTERDIS__SHIFT 0x0 +#define LDOIVRON_CPU_0__CK_LDOIVRON_MASK 0x1 +#define LDOIVRON_CPU_0__CK_LDOIVRON__SHIFT 0x0 +#define LDOIVREXITDONE_CPU_0__LDOIVREXITDONE_MASK 0x1 +#define LDOIVREXITDONE_CPU_0__LDOIVREXITDONE__SHIFT 0x0 +#define RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF_MASK 0x3fff +#define RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF__SHIFT 0x0 +#define IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF_MASK 0x3fff +#define IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF__SHIFT 0x0 +#define CK_JTCOOLRESET_LATCHED_CPU_0__CK_JTCOOLRESET_LATCHED_MASK 0x1 +#define CK_JTCOOLRESET_LATCHED_CPU_0__CK_JTCOOLRESET_LATCHED__SHIFT 0x0 +#define CK_DISABLECORE_CPU_0__CK_DISABLECORE_MASK 0x1 +#define CK_DISABLECORE_CPU_0__CK_DISABLECORE__SHIFT 0x0 +#define COREPM_ID_0__COREPM_INDEX_MASK 0x1 +#define COREPM_ID_0__COREPM_INDEX__SHIFT 0x0 +#define COREPM_SCRATCH_0__SCRATCH_DATA_MASK 0xffffffff +#define COREPM_SCRATCH_0__SCRATCH_DATA__SHIFT 0x0 +#define RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15_MASK 0xffffffff +#define RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15__SHIFT 0x0 +#define SPMI_CONFIG0_0__SPMI_ENABLE_MASK 0x1 +#define SPMI_CONFIG0_0__SPMI_ENABLE__SHIFT 0x0 +#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS_MASK 0x7c +#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2 +#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES_MASK 0xf80 +#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES__SHIFT 0x7 +#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES_MASK 0x1f000 +#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES__SHIFT 0xc +#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK 0x3e0000 +#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT 0x11 +#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK 0x7c00000 +#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT 0x16 +#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK 0x1f +#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT 0x0 +#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE_MASK 0xffe0 +#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE__SHIFT 0x5 +#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER_MASK 0x1 +#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER_MASK 0x1 +#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER_MASK 0x1 +#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_BUSY_0__FSM_BUSY_MASK 0x1 +#define SPMI_FSM_BUSY_0__FSM_BUSY__SHIFT 0x0 +#define SPMI_PATH_0__PATH_ENABLE_REQ_MASK 0x1 +#define SPMI_PATH_0__PATH_ENABLE_REQ__SHIFT 0x0 +#define SPMI_PATH_0__PATH_ENABLE_ACK_MASK 0x2 +#define SPMI_PATH_0__PATH_ENABLE_ACK__SHIFT 0x1 +#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear_MASK 0x10 +#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear__SHIFT 0x4 +#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_MASK 0x1 +#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED__SHIFT 0x0 +#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2 +#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT 0x1 +#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6_MASK 0xfffc +#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2 +#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED_MASK 0x1 +#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT 0x0 +#define SPMI_SRAM_ADDRESS_0__SRAM_ADDRESS_MASK 0xffffffff +#define SPMI_SRAM_ADDRESS_0__SRAM_ADDRESS__SHIFT 0x0 +#define SPMI_SRAM_DATA_0__SRAM_DATA_MASK 0xffffffff +#define SPMI_SRAM_DATA_0__SRAM_DATA__SHIFT 0x0 +#define SPMI_RESET_0__ASYNC_RESET_0_MASK 0x1 +#define SPMI_RESET_0__ASYNC_RESET_0__SHIFT 0x0 +#define SPMI_RESET_0__SYNC_RESET_MASK 0x80000000 +#define SPMI_RESET_0__SYNC_RESET__SHIFT 0x1f +#define SPMI_FORCE_CLOCK_GATERS_0__CLOCK_GATER_0_FORCE_MASK 0x1 +#define SPMI_FORCE_CLOCK_GATERS_0__CLOCK_GATER_0_FORCE__SHIFT 0x0 +#define SPMI_FORCE_CLOCK_GATERS_0__SRAM_CLOCK_GATER_FORCE_MASK 0x100 +#define SPMI_FORCE_CLOCK_GATERS_0__SRAM_CLOCK_GATER_FORCE__SHIFT 0x8 +#define SPMI_SPARE_0__SPARE_DATA_MASK 0xffffffff +#define SPMI_SPARE_0__SPARE_DATA__SHIFT 0x0 +#define SPMI_SPARE_EX_0__SPARE_DATA_EX_MASK 0xffffffff +#define SPMI_SPARE_EX_0__SPARE_DATA_EX__SHIFT 0x0 +#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_EN_MASK 0x1 +#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_EN__SHIFT 0x0 +#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_TIMER_MASK 0x7fe +#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_TIMER__SHIFT 0x1 +#define POWERON_CPU_1__POWERON_MASK 0x1 +#define POWERON_CPU_1__POWERON__SHIFT 0x0 +#define POWERREADY_CPU_1__POWERREADY_MASK 0x1 +#define POWERREADY_CPU_1__POWERREADY__SHIFT 0x0 +#define PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK_MASK 0x1 +#define PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK__SHIFT 0x0 +#define RCC3ON_CPU_1__CK_RCC3ON_MASK 0x1 +#define RCC3ON_CPU_1__CK_RCC3ON__SHIFT 0x0 +#define RCC3ON_CPU_1__RCC3_PSM_EN_MASK 0x2 +#define RCC3ON_CPU_1__RCC3_PSM_EN__SHIFT 0x1 +#define RCC3ON_CPU_1__RCC3_PSM_CLK_DIV_MASK 0xc +#define RCC3ON_CPU_1__RCC3_PSM_CLK_DIV__SHIFT 0x2 +#define RCC3ON_CPU_1__RCC3_AVG_EN_MASK 0x10 +#define RCC3ON_CPU_1__RCC3_AVG_EN__SHIFT 0x4 +#define RCC3ON_CPU_1__RCC3_AVG_DIV_MASK 0x7e0 +#define RCC3ON_CPU_1__RCC3_AVG_DIV__SHIFT 0x5 +#define RCC3ON_CPU_1__RCC3_DIDT_TIMER_MASK 0x1f800 +#define RCC3ON_CPU_1__RCC3_DIDT_TIMER__SHIFT 0xb +#define RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0_MASK 0xfffe0000 +#define RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0__SHIFT 0x11 +#define RCC3EXITDONE_CPU_1__RCC3EXITDONE_MASK 0x1 +#define RCC3EXITDONE_CPU_1__RCC3EXITDONE__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_1__START_STATUS_XFER_MASK 0x1 +#define CORE_FUNC_LATE_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_FUNC_LAST_ADDR_MASK 0x7ff +#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_FUNC_LAST_ADDR__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_LATE_LAST_ADDR_MASK 0x7ff0000 +#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_LATE_LAST_ADDR__SHIFT 0x10 +#define CORE_REDUN_SSB_XFER_1__START_STATUS_XFER_MASK 0x1 +#define CORE_REDUN_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0 +#define CORE_REDUN_SSB_XFER_CFG_1__FUSE_REDUN_LAST_ADDR_MASK 0x7ff +#define CORE_REDUN_SSB_XFER_CFG_1__FUSE_REDUN_LAST_ADDR__SHIFT 0x0 +#define CORE_APM_SSB_XFER_1__START_STATUS_XFER_MASK 0x1 +#define CORE_APM_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0 +#define CORE_APM_SSB_XFER_CFG_1__FUSE_APM_LAST_ADDR_MASK 0x7ff +#define CORE_APM_SSB_XFER_CFG_1__FUSE_APM_LAST_ADDR__SHIFT 0x0 +#define COREPM_PWRCTRL_MISC_1__PWRGATEMASTERDIS_MASK 0x1 +#define COREPM_PWRCTRL_MISC_1__PWRGATEMASTERDIS__SHIFT 0x0 +#define LDOIVRON_CPU_1__CK_LDOIVRON_MASK 0x1 +#define LDOIVRON_CPU_1__CK_LDOIVRON__SHIFT 0x0 +#define LDOIVREXITDONE_CPU_1__LDOIVREXITDONE_MASK 0x1 +#define LDOIVREXITDONE_CPU_1__LDOIVREXITDONE__SHIFT 0x0 +#define RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF_MASK 0x3fff +#define RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF__SHIFT 0x0 +#define IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF_MASK 0x3fff +#define IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF__SHIFT 0x0 +#define CK_JTCOOLRESET_LATCHED_CPU_1__CK_JTCOOLRESET_LATCHED_MASK 0x1 +#define CK_JTCOOLRESET_LATCHED_CPU_1__CK_JTCOOLRESET_LATCHED__SHIFT 0x0 +#define CK_DISABLECORE_CPU_1__CK_DISABLECORE_MASK 0x1 +#define CK_DISABLECORE_CPU_1__CK_DISABLECORE__SHIFT 0x0 +#define COREPM_ID_1__COREPM_INDEX_MASK 0x1 +#define COREPM_ID_1__COREPM_INDEX__SHIFT 0x0 +#define COREPM_SCRATCH_1__SCRATCH_DATA_MASK 0xffffffff +#define COREPM_SCRATCH_1__SCRATCH_DATA__SHIFT 0x0 +#define RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15_MASK 0xffffffff +#define RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15__SHIFT 0x0 +#define SPMI_CONFIG0_1__SPMI_ENABLE_MASK 0x1 +#define SPMI_CONFIG0_1__SPMI_ENABLE__SHIFT 0x0 +#define SPMI_CONFIG0_1__SPMI_PATH_NUM_TIMING_FLOPS_MASK 0x7c +#define SPMI_CONFIG0_1__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2 +#define SPMI_CONFIG0_1__SPMI_SIGNALING_DELAY_CYCLES_MASK 0xf80 +#define SPMI_CONFIG0_1__SPMI_SIGNALING_DELAY_CYCLES__SHIFT 0x7 +#define SPMI_CONFIG0_1__SPMI_SIGNALING_HOLD_CYCLES_MASK 0x1f000 +#define SPMI_CONFIG0_1__SPMI_SIGNALING_HOLD_CYCLES__SHIFT 0xc +#define SPMI_CONFIG0_1__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK 0x3e0000 +#define SPMI_CONFIG0_1__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT 0x11 +#define SPMI_CONFIG0_1__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK 0x7c00000 +#define SPMI_CONFIG0_1__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT 0x16 +#define SPMI_CONFIG1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK 0x1f +#define SPMI_CONFIG1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT 0x0 +#define SPMI_CONFIG1_1__SPMI_CHAIN_SIZE_MASK 0xffe0 +#define SPMI_CONFIG1_1__SPMI_CHAIN_SIZE__SHIFT 0x5 +#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER_MASK 0x1 +#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER_MASK 0x1 +#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER_MASK 0x1 +#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_BUSY_1__FSM_BUSY_MASK 0x1 +#define SPMI_FSM_BUSY_1__FSM_BUSY__SHIFT 0x0 +#define SPMI_PATH_1__PATH_ENABLE_REQ_MASK 0x1 +#define SPMI_PATH_1__PATH_ENABLE_REQ__SHIFT 0x0 +#define SPMI_PATH_1__PATH_ENABLE_ACK_MASK 0x2 +#define SPMI_PATH_1__PATH_ENABLE_ACK__SHIFT 0x1 +#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear_MASK 0x10 +#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear__SHIFT 0x4 +#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_MASK 0x1 +#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED__SHIFT 0x0 +#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2 +#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT 0x1 +#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6_MASK 0xfffc +#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2 +#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED_MASK 0x1 +#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT 0x0 +#define SPMI_SRAM_ADDRESS_1__SRAM_ADDRESS_MASK 0xffffffff +#define SPMI_SRAM_ADDRESS_1__SRAM_ADDRESS__SHIFT 0x0 +#define SPMI_SRAM_DATA_1__SRAM_DATA_MASK 0xffffffff +#define SPMI_SRAM_DATA_1__SRAM_DATA__SHIFT 0x0 +#define SPMI_RESET_1__ASYNC_RESET_0_MASK 0x1 +#define SPMI_RESET_1__ASYNC_RESET_0__SHIFT 0x0 +#define SPMI_RESET_1__SYNC_RESET_MASK 0x80000000 +#define SPMI_RESET_1__SYNC_RESET__SHIFT 0x1f +#define SPMI_FORCE_CLOCK_GATERS_1__CLOCK_GATER_0_FORCE_MASK 0x1 +#define SPMI_FORCE_CLOCK_GATERS_1__CLOCK_GATER_0_FORCE__SHIFT 0x0 +#define SPMI_FORCE_CLOCK_GATERS_1__SRAM_CLOCK_GATER_FORCE_MASK 0x100 +#define SPMI_FORCE_CLOCK_GATERS_1__SRAM_CLOCK_GATER_FORCE__SHIFT 0x8 +#define SPMI_SPARE_1__SPARE_DATA_MASK 0xffffffff +#define SPMI_SPARE_1__SPARE_DATA__SHIFT 0x0 +#define SPMI_SPARE_EX_1__SPARE_DATA_EX_MASK 0xffffffff +#define SPMI_SPARE_EX_1__SPARE_DATA_EX__SHIFT 0x0 +#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_EN_MASK 0x1 +#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_EN__SHIFT 0x0 +#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_TIMER_MASK 0x7fe +#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_TIMER__SHIFT 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40 +#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6 +#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000 +#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_0__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_0__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_1__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_2__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_3__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_4__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_5__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_6__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_7__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_0_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_0_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_0_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_0_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_CG_MC_STAT_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_CG_MC_STAT_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL2__REG_SCLK_DEEP_SLEEP_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL2__REG_SCLK_DEEP_SLEEP_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_SLAVE_SCLK_BUSY_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_SLAVE_SCLK_BUSY_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_MASTER_SCLK_BUSY_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_MASTER_SCLK_BUSY_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE0_IDLE_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE0_IDLE_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE1_IDLE_MASK_MASK 0x400000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE1_IDLE_MASK__SHIFT 0x16 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUIOAGR_IDLE_MASK_MASK 0x800000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUIOAGR_IDLE_MASK__SHIFT 0x17 +#define LCLK_DEEP_SLEEP_CNTL2__SPG_SMU_IDLE_MASK_MASK 0x1000000 +#define LCLK_DEEP_SLEEP_CNTL2__SPG_SMU_IDLE_MASK__SHIFT 0x18 +#define LCLK_DEEP_SLEEP_CNTL2__APG_SMU_IDLE_MASK_MASK 0x2000000 +#define LCLK_DEEP_SLEEP_CNTL2__APG_SMU_IDLE_MASK__SHIFT 0x19 +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE0_MASK_MASK 0x4000000 +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE0_MASK__SHIFT 0x1a +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE1_MASK_MASK 0x8000000 +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE1_MASK__SHIFT 0x1b +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE2_MASK_MASK 0x10000000 +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE2_MASK__SHIFT 0x1c +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE3_MASK_MASK 0x20000000 +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE3_MASK__SHIFT 0x1d +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xc0000000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x1e +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS_MASK 0x1 +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS__SHIFT 0x0 +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK 0x1fe +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT 0x1 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define PWR_DC_RESP__RESPONSE_MASK 0x1 +#define PWR_DC_RESP__RESPONSE__SHIFT 0x0 +#define PWR_VCE_RESP__RESPONSE_MASK 0xffffffff +#define PWR_VCE_RESP__RESPONSE__SHIFT 0x0 +#define PWR_UVD_RESP__RESPONSE_MASK 0xffffffff +#define PWR_UVD_RESP__RESPONSE__SHIFT 0x0 +#define PWR_ACP_RESP__RESPONSE_MASK 0xffffffff +#define PWR_ACP_RESP__RESPONSE__SHIFT 0x0 +#define PWR_DC_REQ__REQUEST_MASK 0x1 +#define PWR_DC_REQ__REQUEST__SHIFT 0x0 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define PCIE_PGFSM_CONFIG__FSM_ADDR_MASK 0xff +#define PCIE_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define PCIE_PGFSM_CONFIG__Power_Down_MASK 0x100 +#define PCIE_PGFSM_CONFIG__Power_Down__SHIFT 0x8 +#define PCIE_PGFSM_CONFIG__Power_Up_MASK 0x200 +#define PCIE_PGFSM_CONFIG__Power_Up__SHIFT 0x9 +#define PCIE_PGFSM_CONFIG__P1_Select_MASK 0x400 +#define PCIE_PGFSM_CONFIG__P1_Select__SHIFT 0xa +#define PCIE_PGFSM_CONFIG__P2_Select_MASK 0x800 +#define PCIE_PGFSM_CONFIG__P2_Select__SHIFT 0xb +#define PCIE_PGFSM_CONFIG__Write_Op_MASK 0x1000 +#define PCIE_PGFSM_CONFIG__Write_Op__SHIFT 0xc +#define PCIE_PGFSM_CONFIG__Read_Op_MASK 0x2000 +#define PCIE_PGFSM_CONFIG__Read_Op__SHIFT 0xd +#define PCIE_PGFSM_CONFIG__Reserved_MASK 0xfffc000 +#define PCIE_PGFSM_CONFIG__Reserved__SHIFT 0xe +#define PCIE_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 +#define PCIE_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define PCIE_PGFSM_WRITE__Write_value_MASK 0xffffffff +#define PCIE_PGFSM_WRITE__Write_value__SHIFT 0x0 +#define SERDES_BUSY__PCIE_SERDES_BUSY_MASK 0x1 +#define SERDES_BUSY__PCIE_SERDES_BUSY__SHIFT 0x0 +#define PCIE_PGFSM2_CONFIG__FSM_ADDR_MASK 0xff +#define PCIE_PGFSM2_CONFIG__FSM_ADDR__SHIFT 0x0 +#define PCIE_PGFSM2_CONFIG__Power_Down_MASK 0x100 +#define PCIE_PGFSM2_CONFIG__Power_Down__SHIFT 0x8 +#define PCIE_PGFSM2_CONFIG__Power_Up_MASK 0x200 +#define PCIE_PGFSM2_CONFIG__Power_Up__SHIFT 0x9 +#define PCIE_PGFSM2_CONFIG__P1_Select_MASK 0x400 +#define PCIE_PGFSM2_CONFIG__P1_Select__SHIFT 0xa +#define PCIE_PGFSM2_CONFIG__P2_Select_MASK 0x800 +#define PCIE_PGFSM2_CONFIG__P2_Select__SHIFT 0xb +#define PCIE_PGFSM2_CONFIG__Write_Op_MASK 0x1000 +#define PCIE_PGFSM2_CONFIG__Write_Op__SHIFT 0xc +#define PCIE_PGFSM2_CONFIG__Read_Op_MASK 0x2000 +#define PCIE_PGFSM2_CONFIG__Read_Op__SHIFT 0xd +#define PCIE_PGFSM2_CONFIG__Reserved_MASK 0xfffc000 +#define PCIE_PGFSM2_CONFIG__Reserved__SHIFT 0xe +#define PCIE_PGFSM2_CONFIG__REG_ADDR_MASK 0xf0000000 +#define PCIE_PGFSM2_CONFIG__REG_ADDR__SHIFT 0x1c +#define PCIE_PGFSM2_WRITE__Write_value_MASK 0xffffffff +#define PCIE_PGFSM2_WRITE__Write_value__SHIFT 0x0 +#define SERDES2_BUSY__PCIE_SERDES_BUSY_MASK 0x1 +#define SERDES2_BUSY__PCIE_SERDES_BUSY__SHIFT 0x0 +#define PCIE_PGFSM_0_READ__Read_value_MASK 0xffffff +#define PCIE_PGFSM_0_READ__Read_value__SHIFT 0x0 +#define PCIE_PGFSM_0_READ__Read_valid_MASK 0x1000000 +#define PCIE_PGFSM_0_READ__Read_valid__SHIFT 0x18 +#define PCIE_PGFSM_1_READ__Read_value_MASK 0xffffff +#define PCIE_PGFSM_1_READ__Read_value__SHIFT 0x0 +#define PCIE_PGFSM_1_READ__Read_valid_MASK 0x1000000 +#define PCIE_PGFSM_1_READ__Read_valid__SHIFT 0x18 +#define PWR_ACPI_INTERRUPT__BIF_CG_req_MASK 0x1 +#define PWR_ACPI_INTERRUPT__BIF_CG_req__SHIFT 0x0 +#define PWR_ACPI_INTERRUPT__AZ_CG_req_MASK 0x2 +#define PWR_ACPI_INTERRUPT__AZ_CG_req__SHIFT 0x1 +#define PWR_ACPI_INTERRUPT__AZ_CG_resp_MASK 0x4 +#define PWR_ACPI_INTERRUPT__AZ_CG_resp__SHIFT 0x2 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0 +#define REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit_MASK 0x1 +#define REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit__SHIFT 0x0 +#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG4_MASK 0xffff +#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG4__SHIFT 0x0 +#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG5_MASK 0xffff0000 +#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG5__SHIFT 0x10 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 +#define MISC_UNB_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff +#define MISC_UNB_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0 +#define MISC_UNB_PWRMGT_CFG1__TIMER_EN_MASK 0x1 +#define MISC_UNB_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0 +#define MISC_UNB_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe +#define MISC_UNB_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1 +#define MISC_UNB_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000 +#define MISC_UNB_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11 +#define MISC_UNB_PWRMGT_DATA__NB_CROSS_TRIGGER_MASK 0xf +#define MISC_UNB_PWRMGT_DATA__NB_CROSS_TRIGGER__SHIFT 0x0 +#define MISC_UNB_PWRMGT_DATA__NB_PRE_SELF_REFRESH_MASK 0x10 +#define MISC_UNB_PWRMGT_DATA__NB_PRE_SELF_REFRESH__SHIFT 0x4 +#define MISC_UNB_PWRMGT_DATA__NB_REQ_NB_PSTATE_MASK 0x20 +#define MISC_UNB_PWRMGT_DATA__NB_REQ_NB_PSTATE__SHIFT 0x5 +#define MISC_UNB_PWRMGT_DATA__NB_FLUSH_ACK_TOGGLE_MASK 0x40 +#define MISC_UNB_PWRMGT_DATA__NB_FLUSH_ACK_TOGGLE__SHIFT 0x6 +#define MISC_UNB_PWRMGT_DATA__NB_ON_INB_WAKE_ACK_MASK 0x80 +#define MISC_UNB_PWRMGT_DATA__NB_ON_INB_WAKE_ACK__SHIFT 0x7 +#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH0LINK_WAKE_ACK_MASK 0x100 +#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH0LINK_WAKE_ACK__SHIFT 0x8 +#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH1LINK_WAKE_ACK_MASK 0x200 +#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH1LINK_WAKE_ACK__SHIFT 0x9 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6_MASK 0x1 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6__SHIFT 0x0 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive_MASK 0x2 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive__SHIFT 0x1 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt_MASK 0x4 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt__SHIFT 0x2 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE_MASK 0xf8 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE__SHIFT 0x3 +#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN_MASK 0x1 +#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN__SHIFT 0x0 +#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD_MASK 0x1fffe +#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD__SHIFT 0x1 +#define DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT_MASK 0x60000 +#define DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT__SHIFT 0x11 +#define SOUTHBRIDGE_TYPE__DISCRETE_SB_MASK 0x1 +#define SOUTHBRIDGE_TYPE__DISCRETE_SB__SHIFT 0x0 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6_MASK 0x1 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6__SHIFT 0x0 +#define GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive_MASK 0x2 +#define GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive__SHIFT 0x1 +#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt_MASK 0x4 +#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt__SHIFT 0x2 +#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit_MASK 0x8 +#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit__SHIFT 0x3 +#define GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh_MASK 0x10 +#define GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh__SHIFT 0x4 +#define GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate_MASK 0x20 +#define GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate__SHIFT 0x5 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate_MASK 0x40 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate__SHIFT 0x6 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh_MASK 0x80 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh__SHIFT 0x7 +#define GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake_MASK 0x100 +#define GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake__SHIFT 0x8 +#define GNBPM_SMU_PWRMGT_STATUS__SPARE_MASK 0xfe00 +#define GNBPM_SMU_PWRMGT_STATUS__SPARE__SHIFT 0x9 +#define ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL_MASK 0x3 +#define ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL__SHIFT 0x0 +#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xffffffff +#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0 +#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xffffffff +#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0xffff +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xffff0000 +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0xffff +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xffff0000 +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0xffff +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xffff0000 +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0xffff +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xffff0000 +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10 +#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0xffff +#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0xffff0000 +#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10 + +#endif /* SMU_8_0_SH_MASK_H */ -- cgit v1.2.3 From 8630f839e0d0c439098b084d8867b82e3aa6084a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:33:44 -0400 Subject: drm/amdgpu: add UVD 4.2 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h | 95 +++ .../drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h | 800 +++++++++++++++++++++ 2 files changed, 895 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h new file mode 100644 index 000000000000..f3e53b118361 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h @@ -0,0 +1,95 @@ +/* + * UVD_4_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_4_2_D_H +#define UVD_4_2_D_H + +#define mmUVD_SEMA_ADDR_LOW 0x3bc0 +#define mmUVD_SEMA_ADDR_HIGH 0x3bc1 +#define mmUVD_SEMA_CMD 0x3bc2 +#define mmUVD_GPCOM_VCPU_CMD 0x3bc3 +#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 +#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 +#define mmUVD_ENGINE_CNTL 0x3bc6 +#define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 +#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 +#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 +#define mmUVD_SEMA_CNTL 0x3d00 +#define mmUVD_LMI_EXT40_ADDR 0x3d26 +#define mmUVD_CTX_INDEX 0x3d28 +#define mmUVD_CTX_DATA 0x3d29 +#define mmUVD_CGC_GATE 0x3d2a +#define mmUVD_CGC_STATUS 0x3d2b +#define mmUVD_CGC_CTRL 0x3d2c +#define mmUVD_CGC_UDEC_STATUS 0x3d2d +#define mmUVD_LMI_CTRL2 0x3d3d +#define mmUVD_MASTINT_EN 0x3d40 +#define mmUVD_LMI_ADDR_EXT 0x3d65 +#define mmUVD_LMI_CTRL 0x3d66 +#define mmUVD_LMI_STATUS 0x3d67 +#define mmUVD_LMI_SWAP_CNTL 0x3d6d +#define mmUVD_MP_SWAP_CNTL 0x3d6f +#define mmUVD_MPC_CNTL 0x3d77 +#define mmUVD_MPC_SET_MUXA0 0x3d79 +#define mmUVD_MPC_SET_MUXA1 0x3d7a +#define mmUVD_MPC_SET_MUXB0 0x3d7b +#define mmUVD_MPC_SET_MUXB1 0x3d7c +#define mmUVD_MPC_SET_MUX 0x3d7d +#define mmUVD_MPC_SET_ALU 0x3d7e +#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 +#define mmUVD_VCPU_CACHE_SIZE0 0x3d83 +#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 +#define mmUVD_VCPU_CACHE_SIZE1 0x3d85 +#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 +#define mmUVD_VCPU_CACHE_SIZE2 0x3d87 +#define mmUVD_VCPU_CNTL 0x3d98 +#define mmUVD_SOFT_RESET 0x3da0 +#define mmUVD_RBC_IB_BASE 0x3da1 +#define mmUVD_RBC_IB_SIZE 0x3da2 +#define mmUVD_RBC_RB_BASE 0x3da3 +#define mmUVD_RBC_RB_RPTR 0x3da4 +#define mmUVD_RBC_RB_WPTR 0x3da5 +#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 +#define mmUVD_RBC_RB_CNTL 0x3da9 +#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa +#define mmUVD_STATUS 0x3daf +#define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 +#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1 +#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2 +#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 +#define mmUVD_CONTEXT_ID 0x3dbd +#define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1 +#define ixUVD_LMI_CACHE_CTRL 0x9b +#define ixUVD_LMI_SWAP_CNTL2 0xaa +#define ixUVD_LMI_ADDR_EXT2 0xab +#define ixUVD_CGC_MEM_CTRL 0xc0 +#define ixUVD_CGC_CTRL2 0xc1 +#define mmUVD_PGFSM_CONFIG 0x38f8 +#define mmUVD_PGFSM_READ_TILE1 0x38fa +#define mmUVD_PGFSM_READ_TILE2 0x38fb +#define mmUVD_POWER_STATUS 0x38fc +#define ixUVD_MIF_CURR_ADDR_CONFIG 0x48 +#define ixUVD_MIF_REF_ADDR_CONFIG 0x4c +#define ixUVD_MIF_RECON1_ADDR_CONFIG 0x114 + +#endif /* UVD_4_2_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h new file mode 100644 index 000000000000..65e8be9e9781 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h @@ -0,0 +1,800 @@ +/* + * UVD_4_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_4_2_SH_MASK_H +#define UVD_4_2_SH_MASK_H + +#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff +#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 +#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff +#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 +#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf +#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 +#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 +#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 +#define UVD_SEMA_CMD__MODE_MASK 0x40 +#define UVD_SEMA_CMD__MODE__SHIFT 0x6 +#define UVD_SEMA_CMD__VMID_EN_MASK 0x80 +#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 +#define UVD_SEMA_CMD__VMID_MASK 0xf00 +#define UVD_SEMA_CMD__VMID__SHIFT 0x8 +#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 +#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe +#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff +#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 +#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff +#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 +#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 +#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 +#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 +#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff +#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 +#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 +#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 +#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 +#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f +#define UVD_CTX_INDEX__INDEX_MASK 0x1ff +#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 +#define UVD_CTX_DATA__DATA_MASK 0xffffffff +#define UVD_CTX_DATA__DATA__SHIFT 0x0 +#define UVD_CGC_GATE__SYS_MASK 0x1 +#define UVD_CGC_GATE__SYS__SHIFT 0x0 +#define UVD_CGC_GATE__UDEC_MASK 0x2 +#define UVD_CGC_GATE__UDEC__SHIFT 0x1 +#define UVD_CGC_GATE__MPEG2_MASK 0x4 +#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 +#define UVD_CGC_GATE__REGS_MASK 0x8 +#define UVD_CGC_GATE__REGS__SHIFT 0x3 +#define UVD_CGC_GATE__RBC_MASK 0x10 +#define UVD_CGC_GATE__RBC__SHIFT 0x4 +#define UVD_CGC_GATE__LMI_MC_MASK 0x20 +#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 +#define UVD_CGC_GATE__LMI_UMC_MASK 0x40 +#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 +#define UVD_CGC_GATE__IDCT_MASK 0x80 +#define UVD_CGC_GATE__IDCT__SHIFT 0x7 +#define UVD_CGC_GATE__MPRD_MASK 0x100 +#define UVD_CGC_GATE__MPRD__SHIFT 0x8 +#define UVD_CGC_GATE__MPC_MASK 0x200 +#define UVD_CGC_GATE__MPC__SHIFT 0x9 +#define UVD_CGC_GATE__LBSI_MASK 0x400 +#define UVD_CGC_GATE__LBSI__SHIFT 0xa +#define UVD_CGC_GATE__LRBBM_MASK 0x800 +#define UVD_CGC_GATE__LRBBM__SHIFT 0xb +#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 +#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc +#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 +#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd +#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 +#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe +#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 +#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf +#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 +#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 +#define UVD_CGC_GATE__WCB_MASK 0x20000 +#define UVD_CGC_GATE__WCB__SHIFT 0x11 +#define UVD_CGC_GATE__VCPU_MASK 0x40000 +#define UVD_CGC_GATE__VCPU__SHIFT 0x12 +#define UVD_CGC_GATE__SCPU_MASK 0x80000 +#define UVD_CGC_GATE__SCPU__SHIFT 0x13 +#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 +#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 +#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 +#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 +#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 +#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 +#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 +#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 +#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 +#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 +#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 +#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 +#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 +#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 +#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 +#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 +#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 +#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 +#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 +#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 +#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 +#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa +#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 +#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb +#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 +#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc +#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 +#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd +#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 +#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe +#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 +#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf +#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 +#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 +#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 +#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 +#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 +#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 +#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 +#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 +#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 +#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 +#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 +#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 +#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 +#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 +#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 +#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 +#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 +#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 +#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 +#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 +#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 +#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a +#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 +#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b +#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 +#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c +#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 +#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 +#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 +#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 +#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 +#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb +#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 +#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc +#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 +#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd +#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 +#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe +#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 +#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf +#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 +#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 +#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 +#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 +#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 +#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 +#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 +#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 +#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 +#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 +#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 +#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 +#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 +#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 +#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 +#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 +#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 +#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 +#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 +#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 +#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 +#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a +#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 +#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b +#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 +#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c +#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 +#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d +#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 +#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e +#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 +#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 +#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 +#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 +#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 +#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 +#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 +#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 +#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 +#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 +#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 +#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 +#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 +#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 +#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 +#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 +#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 +#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 +#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 +#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 +#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 +#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa +#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 +#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb +#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 +#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc +#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 +#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd +#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 +#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe +#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 +#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 +#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 +#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 +#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 +#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 +#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 +#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 +#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 +#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 +#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 +#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 +#define UVD_MASTINT_EN__SYS_EN_MASK 0x4 +#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 +#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 +#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 +#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf +#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 +#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 +#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 +#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 +#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 +#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 +#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc +#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 +#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 +#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 +#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 +#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 +#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 +#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 +#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 +#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 +#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 +#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 +#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb +#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 +#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc +#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 +#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd +#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 +#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe +#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 +#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a +#define UVD_LMI_CTRL__RFU_MASK 0xf8000000 +#define UVD_LMI_CTRL__RFU__SHIFT 0x1b +#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 +#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 +#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 +#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 +#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 +#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 +#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 +#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 +#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa +#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 +#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e +#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 +#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 +#define UVD_MPC_CNTL__PERF_RST_MASK 0x40 +#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 +#define UVD_MPC_CNTL__DBG_MUX_MASK 0x700 +#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 +#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 +#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 +#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 +#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 +#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f +#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 +#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 +#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc +#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 +#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 +#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f +#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 +#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 +#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc +#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f +#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 +#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 +#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc +#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 +#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 +#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f +#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 +#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 +#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc +#define UVD_MPC_SET_MUX__SET_0_MASK 0x7 +#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 +#define UVD_MPC_SET_MUX__SET_1_MASK 0x38 +#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 +#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 +#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 +#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 +#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 +#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 +#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 +#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf +#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 +#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 +#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 +#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 +#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 +#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 +#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 +#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 +#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 +#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 +#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa +#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 +#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb +#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 +#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd +#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 +#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 +#define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x20000 +#define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x11 +#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 +#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 +#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 +#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c +#define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000 +#define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x1d +#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 +#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e +#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 +#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f +#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 +#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 +#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 +#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 +#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 +#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 +#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 +#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 +#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 +#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 +#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 +#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 +#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 +#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 +#define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x200 +#define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x9 +#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 +#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa +#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 +#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb +#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 +#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd +#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 +#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe +#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 +#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf +#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 +#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 +#define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0 +#define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x6 +#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 +#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0 +#define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x6 +#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 +#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 +#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f +#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 +#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 +#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 +#define UVD_STATUS__RBC_BUSY_MASK 0x1 +#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 +#define UVD_STATUS__VCPU_REPORT_MASK 0xfe +#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff +#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 +#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 +#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 +#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 +#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 +#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 +#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 +#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 +#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 +#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 +#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 +#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 +#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 +#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf +#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 +#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 +#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 +#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 +#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 +#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 +#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 +#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 +#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 +#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 +#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 +#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 +#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa +#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 +#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb +#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 +#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc +#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 +#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 +#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c +#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff +#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb +#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc +#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd +#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c +#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 +#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 +#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1 +#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e + +#endif /* UVD_4_2_SH_MASK_H */ -- cgit v1.2.3 From 7aa27c37739c1bea219b744b351c3a74f6eb6674 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:34:14 -0400 Subject: drm/amdgpu: add UVD 5.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h | 114 ++ .../drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h | 1211 ++++++++++++++++++++ .../drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h | 1046 +++++++++++++++++ 3 files changed, 2371 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h new file mode 100644 index 000000000000..eb4cf53427da --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h @@ -0,0 +1,114 @@ +/* + * UVD_5_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_5_0_D_H +#define UVD_5_0_D_H + +#define mmUVD_SEMA_ADDR_LOW 0x3bc0 +#define mmUVD_SEMA_ADDR_HIGH 0x3bc1 +#define mmUVD_SEMA_CMD 0x3bc2 +#define mmUVD_GPCOM_VCPU_CMD 0x3bc3 +#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 +#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 +#define mmUVD_ENGINE_CNTL 0x3bc6 +#define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 +#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 +#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 +#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 +#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66 +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e +#define mmUVD_SEMA_CNTL 0x3d00 +#define mmUVD_LMI_EXT40_ADDR 0x3d26 +#define mmUVD_CTX_INDEX 0x3d28 +#define mmUVD_CTX_DATA 0x3d29 +#define mmUVD_CGC_GATE 0x3d2a +#define mmUVD_CGC_STATUS 0x3d2b +#define mmUVD_CGC_CTRL 0x3d2c +#define mmUVD_CGC_UDEC_STATUS 0x3d2d +#define mmUVD_LMI_CTRL2 0x3d3d +#define mmUVD_MASTINT_EN 0x3d40 +#define mmUVD_LMI_ADDR_EXT 0x3d65 +#define mmUVD_LMI_CTRL 0x3d66 +#define mmUVD_LMI_STATUS 0x3d67 +#define mmUVD_LMI_SWAP_CNTL 0x3d6d +#define mmUVD_MP_SWAP_CNTL 0x3d6f +#define mmUVD_MPC_CNTL 0x3d77 +#define mmUVD_MPC_SET_MUXA0 0x3d79 +#define mmUVD_MPC_SET_MUXA1 0x3d7a +#define mmUVD_MPC_SET_MUXB0 0x3d7b +#define mmUVD_MPC_SET_MUXB1 0x3d7c +#define mmUVD_MPC_SET_MUX 0x3d7d +#define mmUVD_MPC_SET_ALU 0x3d7e +#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 +#define mmUVD_VCPU_CACHE_SIZE0 0x3d83 +#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 +#define mmUVD_VCPU_CACHE_SIZE1 0x3d85 +#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 +#define mmUVD_VCPU_CACHE_SIZE2 0x3d87 +#define mmUVD_VCPU_CNTL 0x3d98 +#define mmUVD_SOFT_RESET 0x3da0 +#define mmUVD_LMI_RBC_IB_VMID 0x3da1 +#define mmUVD_RBC_IB_SIZE 0x3da2 +#define mmUVD_LMI_RBC_RB_VMID 0x3da3 +#define mmUVD_RBC_RB_RPTR 0x3da4 +#define mmUVD_RBC_RB_WPTR 0x3da5 +#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 +#define mmUVD_RBC_RB_CNTL 0x3da9 +#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa +#define mmUVD_STATUS 0x3daf +#define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 +#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1 +#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2 +#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 +#define mmUVD_CONTEXT_ID 0x3dbd +#define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1 +#define mmUVD_SUVD_CGC_GATE 0x3be4 +#define mmUVD_SUVD_CGC_STATUS 0x3be5 +#define mmUVD_SUVD_CGC_CTRL 0x3be6 +#define ixUVD_LMI_VMID_INTERNAL 0x99 +#define ixUVD_LMI_VMID_INTERNAL2 0x9a +#define ixUVD_LMI_CACHE_CTRL 0x9b +#define ixUVD_LMI_SWAP_CNTL2 0xaa +#define ixUVD_LMI_ADDR_EXT2 0xab +#define ixUVD_CGC_MEM_CTRL 0xc0 +#define ixUVD_CGC_CTRL2 0xc1 +#define ixUVD_LMI_VMID_INTERNAL3 0x162 +#define mmUVD_PGFSM_CONFIG 0x38c0 +#define mmUVD_PGFSM_READ_TILE1 0x38c2 +#define mmUVD_PGFSM_READ_TILE2 0x38c3 +#define mmUVD_POWER_STATUS 0x38c4 +#define mmUVD_PGFSM_READ_TILE3 0x38c5 +#define mmUVD_PGFSM_READ_TILE4 0x38c6 +#define mmUVD_PGFSM_READ_TILE5 0x38c8 +#define mmUVD_PGFSM_READ_TILE6 0x38ee +#define mmUVD_PGFSM_READ_TILE7 0x38ef +#define mmUVD_MIF_CURR_ADDR_CONFIG 0x3992 +#define mmUVD_MIF_REF_ADDR_CONFIG 0x3993 +#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5 +#define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4 +#define mmUVD_JPEG_ADDR_CONFIG 0x3a1f + +#endif /* UVD_5_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h new file mode 100644 index 000000000000..981086f8ee4e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h @@ -0,0 +1,1211 @@ +/* + * UVD_5_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_5_0_ENUM_H +#define UVD_5_0_ENUM_H + +typedef enum UVDFirmwareCommand { + UVDFC_FENCE = 0x0, + UVDFC_TRAP = 0x1, + UVDFC_DECODED_ADDR = 0x2, + UVDFC_MBLOCK_ADDR = 0x3, + UVDFC_ITBUF_ADDR = 0x4, + UVDFC_DISPLAY_ADDR = 0x5, + UVDFC_EOD = 0x6, + UVDFC_DISPLAY_PITCH = 0x7, + UVDFC_DISPLAY_TILING = 0x8, + UVDFC_BITSTREAM_ADDR = 0x9, + UVDFC_BITSTREAM_SIZE = 0xa, +} UVDFirmwareCommand; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_scf2 = 0x2, + DBG_CLIENT_BLKID_mcd5 = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_sx30 = 0x5, + DBG_CLIENT_BLKID_mcd2 = 0x6, + DBG_CLIENT_BLKID_bci1 = 0x7, + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, + DBG_CLIENT_BLKID_mcc0 = 0x9, + DBG_CLIENT_BLKID_uvdf_0 = 0xa, + DBG_CLIENT_BLKID_uvdf_1 = 0xb, + DBG_CLIENT_BLKID_uvdf_2 = 0xc, + DBG_CLIENT_BLKID_uvdi_0 = 0xd, + DBG_CLIENT_BLKID_bci0 = 0xe, + DBG_CLIENT_BLKID_vcec0_0 = 0xf, + DBG_CLIENT_BLKID_cb100 = 0x10, + DBG_CLIENT_BLKID_cb001 = 0x11, + DBG_CLIENT_BLKID_mcd4 = 0x12, + DBG_CLIENT_BLKID_tmonw00 = 0x13, + DBG_CLIENT_BLKID_cb101 = 0x14, + DBG_CLIENT_BLKID_sx10 = 0x15, + DBG_CLIENT_BLKID_cb301 = 0x16, + DBG_CLIENT_BLKID_tmonw01 = 0x17, + DBG_CLIENT_BLKID_vcea0_0 = 0x18, + DBG_CLIENT_BLKID_vcea0_1 = 0x19, + DBG_CLIENT_BLKID_vcea0_2 = 0x1a, + DBG_CLIENT_BLKID_vcea0_3 = 0x1b, + DBG_CLIENT_BLKID_scf1 = 0x1c, + DBG_CLIENT_BLKID_sx20 = 0x1d, + DBG_CLIENT_BLKID_spim1 = 0x1e, + DBG_CLIENT_BLKID_pa10 = 0x1f, + DBG_CLIENT_BLKID_pa00 = 0x20, + DBG_CLIENT_BLKID_gmcon = 0x21, + DBG_CLIENT_BLKID_mcb = 0x22, + DBG_CLIENT_BLKID_vgt0 = 0x23, + DBG_CLIENT_BLKID_pc0 = 0x24, + DBG_CLIENT_BLKID_bci2 = 0x25, + DBG_CLIENT_BLKID_uvdb_0 = 0x26, + DBG_CLIENT_BLKID_spim3 = 0x27, + DBG_CLIENT_BLKID_cpc_0 = 0x28, + DBG_CLIENT_BLKID_cpc_1 = 0x29, + DBG_CLIENT_BLKID_uvdm_0 = 0x2a, + DBG_CLIENT_BLKID_uvdm_1 = 0x2b, + DBG_CLIENT_BLKID_uvdm_2 = 0x2c, + DBG_CLIENT_BLKID_uvdm_3 = 0x2d, + DBG_CLIENT_BLKID_cb000 = 0x2e, + DBG_CLIENT_BLKID_spim0 = 0x2f, + DBG_CLIENT_BLKID_mcc2 = 0x30, + DBG_CLIENT_BLKID_ds0 = 0x31, + DBG_CLIENT_BLKID_srbm = 0x32, + DBG_CLIENT_BLKID_ih = 0x33, + DBG_CLIENT_BLKID_sem = 0x34, + DBG_CLIENT_BLKID_sdma_0 = 0x35, + DBG_CLIENT_BLKID_sdma_1 = 0x36, + DBG_CLIENT_BLKID_hdp = 0x37, + DBG_CLIENT_BLKID_acp_0 = 0x38, + DBG_CLIENT_BLKID_acp_1 = 0x39, + DBG_CLIENT_BLKID_cb200 = 0x3a, + DBG_CLIENT_BLKID_scf3 = 0x3b, + DBG_CLIENT_BLKID_vceb1_0 = 0x3c, + DBG_CLIENT_BLKID_vcea1_0 = 0x3d, + DBG_CLIENT_BLKID_vcea1_1 = 0x3e, + DBG_CLIENT_BLKID_vcea1_2 = 0x3f, + DBG_CLIENT_BLKID_vcea1_3 = 0x40, + DBG_CLIENT_BLKID_bci3 = 0x41, + DBG_CLIENT_BLKID_mcd0 = 0x42, + DBG_CLIENT_BLKID_pa11 = 0x43, + DBG_CLIENT_BLKID_pa01 = 0x44, + DBG_CLIENT_BLKID_cb201 = 0x45, + DBG_CLIENT_BLKID_spim2 = 0x46, + DBG_CLIENT_BLKID_vgt2 = 0x47, + DBG_CLIENT_BLKID_pc2 = 0x48, + DBG_CLIENT_BLKID_smu_0 = 0x49, + DBG_CLIENT_BLKID_smu_1 = 0x4a, + DBG_CLIENT_BLKID_smu_2 = 0x4b, + DBG_CLIENT_BLKID_cb1 = 0x4c, + DBG_CLIENT_BLKID_ia0 = 0x4d, + DBG_CLIENT_BLKID_wd = 0x4e, + DBG_CLIENT_BLKID_ia1 = 0x4f, + DBG_CLIENT_BLKID_vcec1_0 = 0x50, + DBG_CLIENT_BLKID_scf0 = 0x51, + DBG_CLIENT_BLKID_vgt1 = 0x52, + DBG_CLIENT_BLKID_pc1 = 0x53, + DBG_CLIENT_BLKID_cb0 = 0x54, + DBG_CLIENT_BLKID_gdc_one_0 = 0x55, + DBG_CLIENT_BLKID_gdc_one_1 = 0x56, + DBG_CLIENT_BLKID_gdc_one_2 = 0x57, + DBG_CLIENT_BLKID_gdc_one_3 = 0x58, + DBG_CLIENT_BLKID_gdc_one_4 = 0x59, + DBG_CLIENT_BLKID_gdc_one_5 = 0x5a, + DBG_CLIENT_BLKID_gdc_one_6 = 0x5b, + DBG_CLIENT_BLKID_gdc_one_7 = 0x5c, + DBG_CLIENT_BLKID_gdc_one_8 = 0x5d, + DBG_CLIENT_BLKID_gdc_one_9 = 0x5e, + DBG_CLIENT_BLKID_gdc_one_10 = 0x5f, + DBG_CLIENT_BLKID_gdc_one_11 = 0x60, + DBG_CLIENT_BLKID_gdc_one_12 = 0x61, + DBG_CLIENT_BLKID_gdc_one_13 = 0x62, + DBG_CLIENT_BLKID_gdc_one_14 = 0x63, + DBG_CLIENT_BLKID_gdc_one_15 = 0x64, + DBG_CLIENT_BLKID_gdc_one_16 = 0x65, + DBG_CLIENT_BLKID_gdc_one_17 = 0x66, + DBG_CLIENT_BLKID_gdc_one_18 = 0x67, + DBG_CLIENT_BLKID_gdc_one_19 = 0x68, + DBG_CLIENT_BLKID_gdc_one_20 = 0x69, + DBG_CLIENT_BLKID_gdc_one_21 = 0x6a, + DBG_CLIENT_BLKID_gdc_one_22 = 0x6b, + DBG_CLIENT_BLKID_gdc_one_23 = 0x6c, + DBG_CLIENT_BLKID_gdc_one_24 = 0x6d, + DBG_CLIENT_BLKID_gdc_one_25 = 0x6e, + DBG_CLIENT_BLKID_gdc_one_26 = 0x6f, + DBG_CLIENT_BLKID_gdc_one_27 = 0x70, + DBG_CLIENT_BLKID_gdc_one_28 = 0x71, + DBG_CLIENT_BLKID_gdc_one_29 = 0x72, + DBG_CLIENT_BLKID_gdc_one_30 = 0x73, + DBG_CLIENT_BLKID_gdc_one_31 = 0x74, + DBG_CLIENT_BLKID_gdc_one_32 = 0x75, + DBG_CLIENT_BLKID_gdc_one_33 = 0x76, + DBG_CLIENT_BLKID_gdc_one_34 = 0x77, + DBG_CLIENT_BLKID_gdc_one_35 = 0x78, + DBG_CLIENT_BLKID_vceb0_0 = 0x79, + DBG_CLIENT_BLKID_vgt3 = 0x7a, + DBG_CLIENT_BLKID_pc3 = 0x7b, + DBG_CLIENT_BLKID_mcd3 = 0x7c, + DBG_CLIENT_BLKID_uvdu_0 = 0x7d, + DBG_CLIENT_BLKID_uvdu_1 = 0x7e, + DBG_CLIENT_BLKID_uvdu_2 = 0x7f, + DBG_CLIENT_BLKID_uvdu_3 = 0x80, + DBG_CLIENT_BLKID_uvdu_4 = 0x81, + DBG_CLIENT_BLKID_uvdu_5 = 0x82, + DBG_CLIENT_BLKID_uvdu_6 = 0x83, + DBG_CLIENT_BLKID_cb300 = 0x84, + DBG_CLIENT_BLKID_mcd1 = 0x85, + DBG_CLIENT_BLKID_sx00 = 0x86, + DBG_CLIENT_BLKID_uvdc_0 = 0x87, + DBG_CLIENT_BLKID_uvdc_1 = 0x88, + DBG_CLIENT_BLKID_mcc3 = 0x89, + DBG_CLIENT_BLKID_cpg_0 = 0x8a, + DBG_CLIENT_BLKID_cpg_1 = 0x8b, + DBG_CLIENT_BLKID_gck = 0x8c, + DBG_CLIENT_BLKID_mcc1 = 0x8d, + DBG_CLIENT_BLKID_cpf_0 = 0x8e, + DBG_CLIENT_BLKID_cpf_1 = 0x8f, + DBG_CLIENT_BLKID_rlc = 0x90, + DBG_CLIENT_BLKID_grbm = 0x91, + DBG_CLIENT_BLKID_sammsp = 0x92, + DBG_CLIENT_BLKID_dci_pg = 0x93, + DBG_CLIENT_BLKID_dci_0 = 0x94, + DBG_CLIENT_BLKID_dccg0_0 = 0x95, + DBG_CLIENT_BLKID_dccg0_1 = 0x96, + DBG_CLIENT_BLKID_dcfe01_0 = 0x97, + DBG_CLIENT_BLKID_dcfe02_0 = 0x98, + DBG_CLIENT_BLKID_dcfe03_0 = 0x99, + DBG_CLIENT_BLKID_dcfe04_0 = 0x9a, + DBG_CLIENT_BLKID_dcfe05_0 = 0x9b, + DBG_CLIENT_BLKID_dcfe06_0 = 0x9c, + DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* UVD_5_0_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h new file mode 100644 index 000000000000..64749b72a0a6 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h @@ -0,0 +1,1046 @@ +/* + * UVD_5_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_5_0_SH_MASK_H +#define UVD_5_0_SH_MASK_H + +#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff +#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 +#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff +#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 +#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf +#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 +#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 +#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 +#define UVD_SEMA_CMD__MODE_MASK 0x40 +#define UVD_SEMA_CMD__MODE__SHIFT 0x6 +#define UVD_SEMA_CMD__VMID_EN_MASK 0x80 +#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 +#define UVD_SEMA_CMD__VMID_MASK 0xf00 +#define UVD_SEMA_CMD__VMID__SHIFT 0x8 +#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 +#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe +#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff +#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 +#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff +#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 +#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 +#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 +#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 +#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff +#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 +#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 +#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 +#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 +#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f +#define UVD_CTX_INDEX__INDEX_MASK 0x1ff +#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 +#define UVD_CTX_DATA__DATA_MASK 0xffffffff +#define UVD_CTX_DATA__DATA__SHIFT 0x0 +#define UVD_CGC_GATE__SYS_MASK 0x1 +#define UVD_CGC_GATE__SYS__SHIFT 0x0 +#define UVD_CGC_GATE__UDEC_MASK 0x2 +#define UVD_CGC_GATE__UDEC__SHIFT 0x1 +#define UVD_CGC_GATE__MPEG2_MASK 0x4 +#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 +#define UVD_CGC_GATE__REGS_MASK 0x8 +#define UVD_CGC_GATE__REGS__SHIFT 0x3 +#define UVD_CGC_GATE__RBC_MASK 0x10 +#define UVD_CGC_GATE__RBC__SHIFT 0x4 +#define UVD_CGC_GATE__LMI_MC_MASK 0x20 +#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 +#define UVD_CGC_GATE__LMI_UMC_MASK 0x40 +#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 +#define UVD_CGC_GATE__IDCT_MASK 0x80 +#define UVD_CGC_GATE__IDCT__SHIFT 0x7 +#define UVD_CGC_GATE__MPRD_MASK 0x100 +#define UVD_CGC_GATE__MPRD__SHIFT 0x8 +#define UVD_CGC_GATE__MPC_MASK 0x200 +#define UVD_CGC_GATE__MPC__SHIFT 0x9 +#define UVD_CGC_GATE__LBSI_MASK 0x400 +#define UVD_CGC_GATE__LBSI__SHIFT 0xa +#define UVD_CGC_GATE__LRBBM_MASK 0x800 +#define UVD_CGC_GATE__LRBBM__SHIFT 0xb +#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 +#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc +#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 +#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd +#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 +#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe +#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 +#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf +#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 +#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 +#define UVD_CGC_GATE__WCB_MASK 0x20000 +#define UVD_CGC_GATE__WCB__SHIFT 0x11 +#define UVD_CGC_GATE__VCPU_MASK 0x40000 +#define UVD_CGC_GATE__VCPU__SHIFT 0x12 +#define UVD_CGC_GATE__SCPU_MASK 0x80000 +#define UVD_CGC_GATE__SCPU__SHIFT 0x13 +#define UVD_CGC_GATE__JPEG_MASK 0x100000 +#define UVD_CGC_GATE__JPEG__SHIFT 0x14 +#define UVD_CGC_GATE__JPEG2_MASK 0x200000 +#define UVD_CGC_GATE__JPEG2__SHIFT 0x15 +#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 +#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 +#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 +#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 +#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 +#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 +#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 +#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 +#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 +#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 +#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 +#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 +#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 +#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 +#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 +#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 +#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 +#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 +#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 +#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 +#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 +#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa +#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 +#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb +#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 +#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc +#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 +#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd +#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 +#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe +#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 +#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf +#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 +#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 +#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 +#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 +#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 +#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 +#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 +#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 +#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 +#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 +#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 +#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 +#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 +#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 +#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 +#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 +#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 +#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 +#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 +#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 +#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 +#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a +#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 +#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b +#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 +#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c +#define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000 +#define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000 +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f +#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 +#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 +#define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2 +#define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 +#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 +#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 +#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 +#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb +#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 +#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc +#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 +#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd +#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 +#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe +#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 +#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf +#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 +#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 +#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 +#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 +#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 +#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 +#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 +#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 +#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 +#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 +#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 +#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 +#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 +#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 +#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 +#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 +#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 +#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 +#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 +#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 +#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 +#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a +#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 +#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b +#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 +#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c +#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 +#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d +#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 +#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e +#define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000 +#define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f +#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 +#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 +#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 +#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 +#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 +#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 +#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 +#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 +#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 +#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 +#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 +#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 +#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 +#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 +#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 +#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 +#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 +#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 +#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 +#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 +#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 +#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa +#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 +#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb +#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 +#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc +#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 +#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd +#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 +#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe +#define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000 +#define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf +#define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000 +#define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10 +#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000 +#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11 +#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000 +#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12 +#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 +#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 +#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 +#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 +#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 +#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 +#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 +#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 +#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 +#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 +#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 +#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 +#define UVD_MASTINT_EN__SYS_EN_MASK 0x4 +#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 +#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 +#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 +#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf +#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 +#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 +#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 +#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 +#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 +#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 +#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc +#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 +#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 +#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 +#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 +#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 +#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 +#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 +#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 +#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 +#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 +#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 +#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb +#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 +#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc +#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 +#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd +#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 +#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe +#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 +#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a +#define UVD_LMI_CTRL__RFU_MASK 0xf8000000 +#define UVD_LMI_CTRL__RFU__SHIFT 0x1b +#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 +#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 +#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 +#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 +#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 +#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 +#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 +#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 +#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa +#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 +#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e +#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 +#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 +#define UVD_MPC_CNTL__PERF_RST_MASK 0x40 +#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 +#define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00 +#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 +#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 +#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 +#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 +#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 +#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f +#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 +#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 +#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc +#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 +#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 +#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f +#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 +#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 +#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc +#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f +#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 +#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 +#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc +#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 +#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 +#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f +#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 +#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 +#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc +#define UVD_MPC_SET_MUX__SET_0_MASK 0x7 +#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 +#define UVD_MPC_SET_MUX__SET_1_MASK 0x38 +#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 +#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 +#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 +#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 +#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 +#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 +#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 +#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf +#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 +#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 +#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 +#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 +#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 +#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 +#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 +#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 +#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 +#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 +#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa +#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 +#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb +#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 +#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd +#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 +#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 +#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000 +#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 +#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 +#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 +#define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000 +#define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 +#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 +#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c +#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 +#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e +#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 +#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f +#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 +#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 +#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 +#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 +#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 +#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 +#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 +#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 +#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 +#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 +#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 +#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 +#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 +#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 +#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200 +#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9 +#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 +#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa +#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 +#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb +#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 +#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd +#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 +#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe +#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 +#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf +#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 +#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 +#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000 +#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000 +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000 +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000 +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000 +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000 +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 +#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000 +#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 +#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000 +#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 +#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000 +#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000 +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000 +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000 +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000 +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000 +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000 +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f +#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf +#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 +#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 +#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf +#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 +#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 +#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 +#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f +#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 +#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 +#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 +#define UVD_STATUS__RBC_BUSY_MASK 0x1 +#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 +#define UVD_STATUS__VCPU_REPORT_MASK 0xfe +#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff +#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 +#define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 +#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define UVD_SUVD_CGC_GATE__SIT_MASK 0x2 +#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define UVD_SUVD_CGC_GATE__SMP_MASK 0x4 +#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define UVD_SUVD_CGC_GATE__SCM_MASK 0x8 +#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define UVD_SUVD_CGC_GATE__SDB_MASK 0x10 +#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 +#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40 +#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80 +#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100 +#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200 +#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400 +#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800 +#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 +#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x2000 +#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x4000 +#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1 +#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 +#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2 +#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 +#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4 +#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 +#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8 +#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 +#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10 +#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 +#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20 +#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100 +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400 +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800 +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000 +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000 +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd +#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x4000 +#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe +#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x8000 +#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf +#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 +#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2 +#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4 +#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8 +#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10 +#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x20 +#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x40 +#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf +#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0 +#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0 +#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4 +#define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00 +#define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8 +#define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000 +#define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc +#define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000 +#define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10 +#define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000 +#define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14 +#define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000 +#define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18 +#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000 +#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c +#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf +#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0 +#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0 +#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4 +#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00 +#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8 +#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000 +#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc +#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000 +#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10 +#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000 +#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14 +#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000 +#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18 +#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000 +#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c +#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 +#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 +#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 +#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 +#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 +#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 +#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 +#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 +#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 +#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 +#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 +#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 +#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf +#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 +#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 +#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 +#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 +#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 +#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 +#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 +#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 +#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 +#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 +#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 +#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 +#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa +#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 +#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb +#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 +#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc +#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 +#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd +#define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000 +#define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe +#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000 +#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 +#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c +#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc +#define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID_MASK 0xf0000 +#define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID__SHIFT 0x10 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff +#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb +#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc +#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd +#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c +#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 +#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 +#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 +#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 +#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 +#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 +#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8 +#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3 +#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10 +#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4 +#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20 +#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5 +#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0 +#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6 +#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 +#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 +#define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200 +#define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9 +#define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400 +#define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa +#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0 +#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0 +#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0 +#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0 +#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e + +#endif /* UVD_5_0_SH_MASK_H */ -- cgit v1.2.3 From 3b1e08cb29565d30d3bb87b26fefb126c1e00d89 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:34:40 -0400 Subject: drm/amdgpu: add UVD 6.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h | 115 +++ .../drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h | 1081 ++++++++++++++++++++ .../drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h | 1034 +++++++++++++++++++ 3 files changed, 2230 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h new file mode 100644 index 000000000000..b2d4aaf045bc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h @@ -0,0 +1,115 @@ +/* + * UVD_6_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_6_0_D_H +#define UVD_6_0_D_H + +#define mmUVD_SEMA_ADDR_LOW 0x3bc0 +#define mmUVD_SEMA_ADDR_HIGH 0x3bc1 +#define mmUVD_SEMA_CMD 0x3bc2 +#define mmUVD_GPCOM_VCPU_CMD 0x3bc3 +#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 +#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 +#define mmUVD_ENGINE_CNTL 0x3bc6 +#define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 +#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 +#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 +#define mmUVD_POWER_STATUS_U 0x3bfd +#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 +#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66 +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e +#define mmUVD_SEMA_CNTL 0x3d00 +#define mmUVD_LMI_EXT40_ADDR 0x3d26 +#define mmUVD_CTX_INDEX 0x3d28 +#define mmUVD_CTX_DATA 0x3d29 +#define mmUVD_CGC_GATE 0x3d2a +#define mmUVD_CGC_STATUS 0x3d2b +#define mmUVD_CGC_CTRL 0x3d2c +#define mmUVD_CGC_UDEC_STATUS 0x3d2d +#define mmUVD_LMI_CTRL2 0x3d3d +#define mmUVD_MASTINT_EN 0x3d40 +#define mmUVD_LMI_ADDR_EXT 0x3d65 +#define mmUVD_LMI_CTRL 0x3d66 +#define mmUVD_LMI_STATUS 0x3d67 +#define mmUVD_LMI_SWAP_CNTL 0x3d6d +#define mmUVD_MP_SWAP_CNTL 0x3d6f +#define mmUVD_MPC_CNTL 0x3d77 +#define mmUVD_MPC_SET_MUXA0 0x3d79 +#define mmUVD_MPC_SET_MUXA1 0x3d7a +#define mmUVD_MPC_SET_MUXB0 0x3d7b +#define mmUVD_MPC_SET_MUXB1 0x3d7c +#define mmUVD_MPC_SET_MUX 0x3d7d +#define mmUVD_MPC_SET_ALU 0x3d7e +#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 +#define mmUVD_VCPU_CACHE_SIZE0 0x3d83 +#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 +#define mmUVD_VCPU_CACHE_SIZE1 0x3d85 +#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 +#define mmUVD_VCPU_CACHE_SIZE2 0x3d87 +#define mmUVD_VCPU_CNTL 0x3d98 +#define mmUVD_SOFT_RESET 0x3da0 +#define mmUVD_LMI_RBC_IB_VMID 0x3da1 +#define mmUVD_RBC_IB_SIZE 0x3da2 +#define mmUVD_LMI_RBC_RB_VMID 0x3da3 +#define mmUVD_RBC_RB_RPTR 0x3da4 +#define mmUVD_RBC_RB_WPTR 0x3da5 +#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 +#define mmUVD_RBC_RB_CNTL 0x3da9 +#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa +#define mmUVD_STATUS 0x3daf +#define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 +#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1 +#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2 +#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 +#define mmUVD_CONTEXT_ID 0x3dbd +#define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1 +#define mmUVD_SUVD_CGC_GATE 0x3be4 +#define mmUVD_SUVD_CGC_STATUS 0x3be5 +#define mmUVD_SUVD_CGC_CTRL 0x3be6 +#define ixUVD_LMI_VMID_INTERNAL 0x99 +#define ixUVD_LMI_VMID_INTERNAL2 0x9a +#define ixUVD_LMI_CACHE_CTRL 0x9b +#define ixUVD_LMI_SWAP_CNTL2 0xaa +#define ixUVD_LMI_ADDR_EXT2 0xab +#define ixUVD_CGC_MEM_CTRL 0xc0 +#define ixUVD_CGC_CTRL2 0xc1 +#define ixUVD_LMI_VMID_INTERNAL3 0x162 +#define mmUVD_PGFSM_CONFIG 0x38c0 +#define mmUVD_PGFSM_READ_TILE1 0x38c2 +#define mmUVD_PGFSM_READ_TILE2 0x38c3 +#define mmUVD_POWER_STATUS 0x38c4 +#define mmUVD_PGFSM_READ_TILE3 0x38c5 +#define mmUVD_PGFSM_READ_TILE4 0x38c6 +#define mmUVD_PGFSM_READ_TILE5 0x38c8 +#define mmUVD_PGFSM_READ_TILE6 0x38ee +#define mmUVD_PGFSM_READ_TILE7 0x38ef +#define mmUVD_MIF_CURR_ADDR_CONFIG 0x3992 +#define mmUVD_MIF_REF_ADDR_CONFIG 0x3993 +#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5 +#define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4 +#define mmUVD_JPEG_ADDR_CONFIG 0x3a1f + +#endif /* UVD_6_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h new file mode 100644 index 000000000000..ecf47ba55c2d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h @@ -0,0 +1,1081 @@ +/* + * UVD_6_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_6_0_ENUM_H +#define UVD_6_0_ENUM_H + +typedef enum UVDFirmwareCommand { + UVDFC_FENCE = 0x0, + UVDFC_TRAP = 0x1, + UVDFC_DECODED_ADDR = 0x2, + UVDFC_MBLOCK_ADDR = 0x3, + UVDFC_ITBUF_ADDR = 0x4, + UVDFC_DISPLAY_ADDR = 0x5, + UVDFC_EOD = 0x6, + UVDFC_DISPLAY_PITCH = 0x7, + UVDFC_DISPLAY_TILING = 0x8, + UVDFC_BITSTREAM_ADDR = 0x9, + UVDFC_BITSTREAM_SIZE = 0xa, +} UVDFirmwareCommand; +typedef enum DebugBlockId { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_UVDU = 0xd, + DBG_BLOCK_ID_SQA = 0xe, + DBG_BLOCK_ID_SDMA0 = 0xf, + DBG_BLOCK_ID_SDMA1 = 0x10, + DBG_BLOCK_ID_SPIM = 0x11, + DBG_BLOCK_ID_GDS = 0x12, + DBG_BLOCK_ID_VC0 = 0x13, + DBG_BLOCK_ID_VC1 = 0x14, + DBG_BLOCK_ID_PA0 = 0x15, + DBG_BLOCK_ID_PA1 = 0x16, + DBG_BLOCK_ID_CP0 = 0x17, + DBG_BLOCK_ID_CP1 = 0x18, + DBG_BLOCK_ID_CP2 = 0x19, + DBG_BLOCK_ID_XBR = 0x1a, + DBG_BLOCK_ID_UVDM = 0x1b, + DBG_BLOCK_ID_VGT0 = 0x1c, + DBG_BLOCK_ID_VGT1 = 0x1d, + DBG_BLOCK_ID_IA = 0x1e, + DBG_BLOCK_ID_SXM0 = 0x1f, + DBG_BLOCK_ID_SXM1 = 0x20, + DBG_BLOCK_ID_SCT0 = 0x21, + DBG_BLOCK_ID_SCT1 = 0x22, + DBG_BLOCK_ID_SPM0 = 0x23, + DBG_BLOCK_ID_SPM1 = 0x24, + DBG_BLOCK_ID_UNUSED0 = 0x25, + DBG_BLOCK_ID_UNUSED1 = 0x26, + DBG_BLOCK_ID_TCAA = 0x27, + DBG_BLOCK_ID_TCAB = 0x28, + DBG_BLOCK_ID_TCCA = 0x29, + DBG_BLOCK_ID_TCCB = 0x2a, + DBG_BLOCK_ID_MCC0 = 0x2b, + DBG_BLOCK_ID_MCC1 = 0x2c, + DBG_BLOCK_ID_MCC2 = 0x2d, + DBG_BLOCK_ID_MCC3 = 0x2e, + DBG_BLOCK_ID_SXS0 = 0x2f, + DBG_BLOCK_ID_SXS1 = 0x30, + DBG_BLOCK_ID_SXS2 = 0x31, + DBG_BLOCK_ID_SXS3 = 0x32, + DBG_BLOCK_ID_SXS4 = 0x33, + DBG_BLOCK_ID_SXS5 = 0x34, + DBG_BLOCK_ID_SXS6 = 0x35, + DBG_BLOCK_ID_SXS7 = 0x36, + DBG_BLOCK_ID_SXS8 = 0x37, + DBG_BLOCK_ID_SXS9 = 0x38, + DBG_BLOCK_ID_BCI0 = 0x39, + DBG_BLOCK_ID_BCI1 = 0x3a, + DBG_BLOCK_ID_BCI2 = 0x3b, + DBG_BLOCK_ID_BCI3 = 0x3c, + DBG_BLOCK_ID_MCB = 0x3d, + DBG_BLOCK_ID_UNUSED6 = 0x3e, + DBG_BLOCK_ID_SQA00 = 0x3f, + DBG_BLOCK_ID_SQA01 = 0x40, + DBG_BLOCK_ID_SQA02 = 0x41, + DBG_BLOCK_ID_SQA10 = 0x42, + DBG_BLOCK_ID_SQA11 = 0x43, + DBG_BLOCK_ID_SQA12 = 0x44, + DBG_BLOCK_ID_UNUSED7 = 0x45, + DBG_BLOCK_ID_UNUSED8 = 0x46, + DBG_BLOCK_ID_SQB00 = 0x47, + DBG_BLOCK_ID_SQB01 = 0x48, + DBG_BLOCK_ID_SQB10 = 0x49, + DBG_BLOCK_ID_SQB11 = 0x4a, + DBG_BLOCK_ID_SQ00 = 0x4b, + DBG_BLOCK_ID_SQ01 = 0x4c, + DBG_BLOCK_ID_SQ10 = 0x4d, + DBG_BLOCK_ID_SQ11 = 0x4e, + DBG_BLOCK_ID_CB00 = 0x4f, + DBG_BLOCK_ID_CB01 = 0x50, + DBG_BLOCK_ID_CB02 = 0x51, + DBG_BLOCK_ID_CB03 = 0x52, + DBG_BLOCK_ID_CB04 = 0x53, + DBG_BLOCK_ID_UNUSED9 = 0x54, + DBG_BLOCK_ID_UNUSED10 = 0x55, + DBG_BLOCK_ID_UNUSED11 = 0x56, + DBG_BLOCK_ID_CB10 = 0x57, + DBG_BLOCK_ID_CB11 = 0x58, + DBG_BLOCK_ID_CB12 = 0x59, + DBG_BLOCK_ID_CB13 = 0x5a, + DBG_BLOCK_ID_CB14 = 0x5b, + DBG_BLOCK_ID_UNUSED12 = 0x5c, + DBG_BLOCK_ID_UNUSED13 = 0x5d, + DBG_BLOCK_ID_UNUSED14 = 0x5e, + DBG_BLOCK_ID_TCP0 = 0x5f, + DBG_BLOCK_ID_TCP1 = 0x60, + DBG_BLOCK_ID_TCP2 = 0x61, + DBG_BLOCK_ID_TCP3 = 0x62, + DBG_BLOCK_ID_TCP4 = 0x63, + DBG_BLOCK_ID_TCP5 = 0x64, + DBG_BLOCK_ID_TCP6 = 0x65, + DBG_BLOCK_ID_TCP7 = 0x66, + DBG_BLOCK_ID_TCP8 = 0x67, + DBG_BLOCK_ID_TCP9 = 0x68, + DBG_BLOCK_ID_TCP10 = 0x69, + DBG_BLOCK_ID_TCP11 = 0x6a, + DBG_BLOCK_ID_TCP12 = 0x6b, + DBG_BLOCK_ID_TCP13 = 0x6c, + DBG_BLOCK_ID_TCP14 = 0x6d, + DBG_BLOCK_ID_TCP15 = 0x6e, + DBG_BLOCK_ID_TCP16 = 0x6f, + DBG_BLOCK_ID_TCP17 = 0x70, + DBG_BLOCK_ID_TCP18 = 0x71, + DBG_BLOCK_ID_TCP19 = 0x72, + DBG_BLOCK_ID_TCP20 = 0x73, + DBG_BLOCK_ID_TCP21 = 0x74, + DBG_BLOCK_ID_TCP22 = 0x75, + DBG_BLOCK_ID_TCP23 = 0x76, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, + DBG_BLOCK_ID_DB00 = 0x7f, + DBG_BLOCK_ID_DB01 = 0x80, + DBG_BLOCK_ID_DB02 = 0x81, + DBG_BLOCK_ID_DB03 = 0x82, + DBG_BLOCK_ID_DB04 = 0x83, + DBG_BLOCK_ID_UNUSED15 = 0x84, + DBG_BLOCK_ID_UNUSED16 = 0x85, + DBG_BLOCK_ID_UNUSED17 = 0x86, + DBG_BLOCK_ID_DB10 = 0x87, + DBG_BLOCK_ID_DB11 = 0x88, + DBG_BLOCK_ID_DB12 = 0x89, + DBG_BLOCK_ID_DB13 = 0x8a, + DBG_BLOCK_ID_DB14 = 0x8b, + DBG_BLOCK_ID_UNUSED18 = 0x8c, + DBG_BLOCK_ID_UNUSED19 = 0x8d, + DBG_BLOCK_ID_UNUSED20 = 0x8e, + DBG_BLOCK_ID_TCC0 = 0x8f, + DBG_BLOCK_ID_TCC1 = 0x90, + DBG_BLOCK_ID_TCC2 = 0x91, + DBG_BLOCK_ID_TCC3 = 0x92, + DBG_BLOCK_ID_TCC4 = 0x93, + DBG_BLOCK_ID_TCC5 = 0x94, + DBG_BLOCK_ID_TCC6 = 0x95, + DBG_BLOCK_ID_TCC7 = 0x96, + DBG_BLOCK_ID_SPS00 = 0x97, + DBG_BLOCK_ID_SPS01 = 0x98, + DBG_BLOCK_ID_SPS02 = 0x99, + DBG_BLOCK_ID_SPS10 = 0x9a, + DBG_BLOCK_ID_SPS11 = 0x9b, + DBG_BLOCK_ID_SPS12 = 0x9c, + DBG_BLOCK_ID_UNUSED21 = 0x9d, + DBG_BLOCK_ID_UNUSED22 = 0x9e, + DBG_BLOCK_ID_TA00 = 0x9f, + DBG_BLOCK_ID_TA01 = 0xa0, + DBG_BLOCK_ID_TA02 = 0xa1, + DBG_BLOCK_ID_TA03 = 0xa2, + DBG_BLOCK_ID_TA04 = 0xa3, + DBG_BLOCK_ID_TA05 = 0xa4, + DBG_BLOCK_ID_TA06 = 0xa5, + DBG_BLOCK_ID_TA07 = 0xa6, + DBG_BLOCK_ID_TA08 = 0xa7, + DBG_BLOCK_ID_TA09 = 0xa8, + DBG_BLOCK_ID_TA0A = 0xa9, + DBG_BLOCK_ID_TA0B = 0xaa, + DBG_BLOCK_ID_UNUSED23 = 0xab, + DBG_BLOCK_ID_UNUSED24 = 0xac, + DBG_BLOCK_ID_UNUSED25 = 0xad, + DBG_BLOCK_ID_UNUSED26 = 0xae, + DBG_BLOCK_ID_TA10 = 0xaf, + DBG_BLOCK_ID_TA11 = 0xb0, + DBG_BLOCK_ID_TA12 = 0xb1, + DBG_BLOCK_ID_TA13 = 0xb2, + DBG_BLOCK_ID_TA14 = 0xb3, + DBG_BLOCK_ID_TA15 = 0xb4, + DBG_BLOCK_ID_TA16 = 0xb5, + DBG_BLOCK_ID_TA17 = 0xb6, + DBG_BLOCK_ID_TA18 = 0xb7, + DBG_BLOCK_ID_TA19 = 0xb8, + DBG_BLOCK_ID_TA1A = 0xb9, + DBG_BLOCK_ID_TA1B = 0xba, + DBG_BLOCK_ID_UNUSED27 = 0xbb, + DBG_BLOCK_ID_UNUSED28 = 0xbc, + DBG_BLOCK_ID_UNUSED29 = 0xbd, + DBG_BLOCK_ID_UNUSED30 = 0xbe, + DBG_BLOCK_ID_TD00 = 0xbf, + DBG_BLOCK_ID_TD01 = 0xc0, + DBG_BLOCK_ID_TD02 = 0xc1, + DBG_BLOCK_ID_TD03 = 0xc2, + DBG_BLOCK_ID_TD04 = 0xc3, + DBG_BLOCK_ID_TD05 = 0xc4, + DBG_BLOCK_ID_TD06 = 0xc5, + DBG_BLOCK_ID_TD07 = 0xc6, + DBG_BLOCK_ID_TD08 = 0xc7, + DBG_BLOCK_ID_TD09 = 0xc8, + DBG_BLOCK_ID_TD0A = 0xc9, + DBG_BLOCK_ID_TD0B = 0xca, + DBG_BLOCK_ID_UNUSED31 = 0xcb, + DBG_BLOCK_ID_UNUSED32 = 0xcc, + DBG_BLOCK_ID_UNUSED33 = 0xcd, + DBG_BLOCK_ID_UNUSED34 = 0xce, + DBG_BLOCK_ID_TD10 = 0xcf, + DBG_BLOCK_ID_TD11 = 0xd0, + DBG_BLOCK_ID_TD12 = 0xd1, + DBG_BLOCK_ID_TD13 = 0xd2, + DBG_BLOCK_ID_TD14 = 0xd3, + DBG_BLOCK_ID_TD15 = 0xd4, + DBG_BLOCK_ID_TD16 = 0xd5, + DBG_BLOCK_ID_TD17 = 0xd6, + DBG_BLOCK_ID_TD18 = 0xd7, + DBG_BLOCK_ID_TD19 = 0xd8, + DBG_BLOCK_ID_TD1A = 0xd9, + DBG_BLOCK_ID_TD1B = 0xda, + DBG_BLOCK_ID_UNUSED35 = 0xdb, + DBG_BLOCK_ID_UNUSED36 = 0xdc, + DBG_BLOCK_ID_UNUSED37 = 0xdd, + DBG_BLOCK_ID_UNUSED38 = 0xde, + DBG_BLOCK_ID_LDS00 = 0xdf, + DBG_BLOCK_ID_LDS01 = 0xe0, + DBG_BLOCK_ID_LDS02 = 0xe1, + DBG_BLOCK_ID_LDS03 = 0xe2, + DBG_BLOCK_ID_LDS04 = 0xe3, + DBG_BLOCK_ID_LDS05 = 0xe4, + DBG_BLOCK_ID_LDS06 = 0xe5, + DBG_BLOCK_ID_LDS07 = 0xe6, + DBG_BLOCK_ID_LDS08 = 0xe7, + DBG_BLOCK_ID_LDS09 = 0xe8, + DBG_BLOCK_ID_LDS0A = 0xe9, + DBG_BLOCK_ID_LDS0B = 0xea, + DBG_BLOCK_ID_UNUSED39 = 0xeb, + DBG_BLOCK_ID_UNUSED40 = 0xec, + DBG_BLOCK_ID_UNUSED41 = 0xed, + DBG_BLOCK_ID_UNUSED42 = 0xee, + DBG_BLOCK_ID_LDS10 = 0xef, + DBG_BLOCK_ID_LDS11 = 0xf0, + DBG_BLOCK_ID_LDS12 = 0xf1, + DBG_BLOCK_ID_LDS13 = 0xf2, + DBG_BLOCK_ID_LDS14 = 0xf3, + DBG_BLOCK_ID_LDS15 = 0xf4, + DBG_BLOCK_ID_LDS16 = 0xf5, + DBG_BLOCK_ID_LDS17 = 0xf6, + DBG_BLOCK_ID_LDS18 = 0xf7, + DBG_BLOCK_ID_LDS19 = 0xf8, + DBG_BLOCK_ID_LDS1A = 0xf9, + DBG_BLOCK_ID_LDS1B = 0xfa, + DBG_BLOCK_ID_UNUSED43 = 0xfb, + DBG_BLOCK_ID_UNUSED44 = 0xfc, + DBG_BLOCK_ID_UNUSED45 = 0xfd, + DBG_BLOCK_ID_UNUSED46 = 0xfe, +} DebugBlockId; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_UVD_BY2 = 0x7, + DBG_BLOCK_ID_SDMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_VC0_BY2 = 0xa, + DBG_BLOCK_ID_PA_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_PC0_BY2 = 0xe, + DBG_BLOCK_ID_BCI0_BY2 = 0xf, + DBG_BLOCK_ID_SXM0_BY2 = 0x10, + DBG_BLOCK_ID_SCT0_BY2 = 0x11, + DBG_BLOCK_ID_SPM0_BY2 = 0x12, + DBG_BLOCK_ID_BCI2_BY2 = 0x13, + DBG_BLOCK_ID_TCA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_MCD_BY2 = 0x18, + DBG_BLOCK_ID_MCD2_BY2 = 0x19, + DBG_BLOCK_ID_MCD4_BY2 = 0x1a, + DBG_BLOCK_ID_MCB_BY2 = 0x1b, + DBG_BLOCK_ID_SQA_BY2 = 0x1c, + DBG_BLOCK_ID_SQA02_BY2 = 0x1d, + DBG_BLOCK_ID_SQA11_BY2 = 0x1e, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, + DBG_BLOCK_ID_SQB_BY2 = 0x20, + DBG_BLOCK_ID_SQB10_BY2 = 0x21, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, + DBG_BLOCK_ID_CB_BY2 = 0x24, + DBG_BLOCK_ID_CB02_BY2 = 0x25, + DBG_BLOCK_ID_CB10_BY2 = 0x26, + DBG_BLOCK_ID_CB12_BY2 = 0x27, + DBG_BLOCK_ID_SXS_BY2 = 0x28, + DBG_BLOCK_ID_SXS2_BY2 = 0x29, + DBG_BLOCK_ID_SXS4_BY2 = 0x2a, + DBG_BLOCK_ID_SXS6_BY2 = 0x2b, + DBG_BLOCK_ID_DB_BY2 = 0x2c, + DBG_BLOCK_ID_DB02_BY2 = 0x2d, + DBG_BLOCK_ID_DB10_BY2 = 0x2e, + DBG_BLOCK_ID_DB12_BY2 = 0x2f, + DBG_BLOCK_ID_TCP_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_TCC_BY2 = 0x40, + DBG_BLOCK_ID_TCC2_BY2 = 0x41, + DBG_BLOCK_ID_TCC4_BY2 = 0x42, + DBG_BLOCK_ID_TCC6_BY2 = 0x43, + DBG_BLOCK_ID_SPS_BY2 = 0x44, + DBG_BLOCK_ID_SPS02_BY2 = 0x45, + DBG_BLOCK_ID_SPS11_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, + DBG_BLOCK_ID_TA_BY2 = 0x48, + DBG_BLOCK_ID_TA02_BY2 = 0x49, + DBG_BLOCK_ID_TA04_BY2 = 0x4a, + DBG_BLOCK_ID_TA06_BY2 = 0x4b, + DBG_BLOCK_ID_TA08_BY2 = 0x4c, + DBG_BLOCK_ID_TA0A_BY2 = 0x4d, + DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, + DBG_BLOCK_ID_TA10_BY2 = 0x50, + DBG_BLOCK_ID_TA12_BY2 = 0x51, + DBG_BLOCK_ID_TA14_BY2 = 0x52, + DBG_BLOCK_ID_TA16_BY2 = 0x53, + DBG_BLOCK_ID_TA18_BY2 = 0x54, + DBG_BLOCK_ID_TA1A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, + DBG_BLOCK_ID_TD_BY2 = 0x58, + DBG_BLOCK_ID_TD02_BY2 = 0x59, + DBG_BLOCK_ID_TD04_BY2 = 0x5a, + DBG_BLOCK_ID_TD06_BY2 = 0x5b, + DBG_BLOCK_ID_TD08_BY2 = 0x5c, + DBG_BLOCK_ID_TD0A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, + DBG_BLOCK_ID_TD10_BY2 = 0x60, + DBG_BLOCK_ID_TD12_BY2 = 0x61, + DBG_BLOCK_ID_TD14_BY2 = 0x62, + DBG_BLOCK_ID_TD16_BY2 = 0x63, + DBG_BLOCK_ID_TD18_BY2 = 0x64, + DBG_BLOCK_ID_TD1A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, + DBG_BLOCK_ID_LDS_BY2 = 0x68, + DBG_BLOCK_ID_LDS02_BY2 = 0x69, + DBG_BLOCK_ID_LDS04_BY2 = 0x6a, + DBG_BLOCK_ID_LDS06_BY2 = 0x6b, + DBG_BLOCK_ID_LDS08_BY2 = 0x6c, + DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, + DBG_BLOCK_ID_LDS10_BY2 = 0x70, + DBG_BLOCK_ID_LDS12_BY2 = 0x71, + DBG_BLOCK_ID_LDS14_BY2 = 0x72, + DBG_BLOCK_ID_LDS16_BY2 = 0x73, + DBG_BLOCK_ID_LDS18_BY2 = 0x74, + DBG_BLOCK_ID_LDS1A_BY2 = 0x75, + DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, + DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_SDMA0_BY4 = 0x4, + DBG_BLOCK_ID_VC0_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, + DBG_BLOCK_ID_SXM0_BY4 = 0x8, + DBG_BLOCK_ID_SPM0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC_BY4 = 0xb, + DBG_BLOCK_ID_MCD_BY4 = 0xc, + DBG_BLOCK_ID_MCD4_BY4 = 0xd, + DBG_BLOCK_ID_SQA_BY4 = 0xe, + DBG_BLOCK_ID_SQA11_BY4 = 0xf, + DBG_BLOCK_ID_SQB_BY4 = 0x10, + DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, + DBG_BLOCK_ID_CB_BY4 = 0x12, + DBG_BLOCK_ID_CB10_BY4 = 0x13, + DBG_BLOCK_ID_SXS_BY4 = 0x14, + DBG_BLOCK_ID_SXS4_BY4 = 0x15, + DBG_BLOCK_ID_DB_BY4 = 0x16, + DBG_BLOCK_ID_DB10_BY4 = 0x17, + DBG_BLOCK_ID_TCP_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_TCC_BY4 = 0x20, + DBG_BLOCK_ID_TCC4_BY4 = 0x21, + DBG_BLOCK_ID_SPS_BY4 = 0x22, + DBG_BLOCK_ID_SPS11_BY4 = 0x23, + DBG_BLOCK_ID_TA_BY4 = 0x24, + DBG_BLOCK_ID_TA04_BY4 = 0x25, + DBG_BLOCK_ID_TA08_BY4 = 0x26, + DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, + DBG_BLOCK_ID_TA10_BY4 = 0x28, + DBG_BLOCK_ID_TA14_BY4 = 0x29, + DBG_BLOCK_ID_TA18_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, + DBG_BLOCK_ID_TD_BY4 = 0x2c, + DBG_BLOCK_ID_TD04_BY4 = 0x2d, + DBG_BLOCK_ID_TD08_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, + DBG_BLOCK_ID_TD10_BY4 = 0x30, + DBG_BLOCK_ID_TD14_BY4 = 0x31, + DBG_BLOCK_ID_TD18_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, + DBG_BLOCK_ID_LDS_BY4 = 0x34, + DBG_BLOCK_ID_LDS04_BY4 = 0x35, + DBG_BLOCK_ID_LDS08_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, + DBG_BLOCK_ID_LDS10_BY4 = 0x38, + DBG_BLOCK_ID_LDS14_BY4 = 0x39, + DBG_BLOCK_ID_LDS18_BY4 = 0x3a, + DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_SDMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_SXM0_BY8 = 0x4, + DBG_BLOCK_ID_TCA_BY8 = 0x5, + DBG_BLOCK_ID_MCD_BY8 = 0x6, + DBG_BLOCK_ID_SQA_BY8 = 0x7, + DBG_BLOCK_ID_SQB_BY8 = 0x8, + DBG_BLOCK_ID_CB_BY8 = 0x9, + DBG_BLOCK_ID_SXS_BY8 = 0xa, + DBG_BLOCK_ID_DB_BY8 = 0xb, + DBG_BLOCK_ID_TCP_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_TCC_BY8 = 0x10, + DBG_BLOCK_ID_SPS_BY8 = 0x11, + DBG_BLOCK_ID_TA_BY8 = 0x12, + DBG_BLOCK_ID_TA08_BY8 = 0x13, + DBG_BLOCK_ID_TA10_BY8 = 0x14, + DBG_BLOCK_ID_TA18_BY8 = 0x15, + DBG_BLOCK_ID_TD_BY8 = 0x16, + DBG_BLOCK_ID_TD08_BY8 = 0x17, + DBG_BLOCK_ID_TD10_BY8 = 0x18, + DBG_BLOCK_ID_TD18_BY8 = 0x19, + DBG_BLOCK_ID_LDS_BY8 = 0x1a, + DBG_BLOCK_ID_LDS08_BY8 = 0x1b, + DBG_BLOCK_ID_LDS10_BY8 = 0x1c, + DBG_BLOCK_ID_LDS18_BY8 = 0x1d, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_SDMA0_BY16 = 0x1, + DBG_BLOCK_ID_SXM_BY16 = 0x2, + DBG_BLOCK_ID_MCD_BY16 = 0x3, + DBG_BLOCK_ID_SQB_BY16 = 0x4, + DBG_BLOCK_ID_SXS_BY16 = 0x5, + DBG_BLOCK_ID_TCP_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_TCC_BY16 = 0x8, + DBG_BLOCK_ID_TA_BY16 = 0x9, + DBG_BLOCK_ID_TA10_BY16 = 0xa, + DBG_BLOCK_ID_TD_BY16 = 0xb, + DBG_BLOCK_ID_TD10_BY16 = 0xc, + DBG_BLOCK_ID_LDS_BY16 = 0xd, + DBG_BLOCK_ID_LDS10_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* UVD_6_0_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h new file mode 100644 index 000000000000..9917c543d895 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h @@ -0,0 +1,1034 @@ +/* + * UVD_6_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef UVD_6_0_SH_MASK_H +#define UVD_6_0_SH_MASK_H + +#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff +#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 +#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff +#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 +#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf +#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 +#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 +#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 +#define UVD_SEMA_CMD__MODE_MASK 0x40 +#define UVD_SEMA_CMD__MODE__SHIFT 0x6 +#define UVD_SEMA_CMD__VMID_EN_MASK 0x80 +#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 +#define UVD_SEMA_CMD__VMID_MASK 0xf00 +#define UVD_SEMA_CMD__VMID__SHIFT 0x8 +#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 +#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe +#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff +#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 +#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff +#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 +#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 +#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_POWER_STATUS_U__UVD_POWER_STATUS_MASK 0x3 +#define UVD_POWER_STATUS_U__UVD_POWER_STATUS__SHIFT 0x0 +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 +#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 +#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff +#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 +#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 +#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 +#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 +#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f +#define UVD_CTX_INDEX__INDEX_MASK 0x1ff +#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 +#define UVD_CTX_DATA__DATA_MASK 0xffffffff +#define UVD_CTX_DATA__DATA__SHIFT 0x0 +#define UVD_CGC_GATE__SYS_MASK 0x1 +#define UVD_CGC_GATE__SYS__SHIFT 0x0 +#define UVD_CGC_GATE__UDEC_MASK 0x2 +#define UVD_CGC_GATE__UDEC__SHIFT 0x1 +#define UVD_CGC_GATE__MPEG2_MASK 0x4 +#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 +#define UVD_CGC_GATE__REGS_MASK 0x8 +#define UVD_CGC_GATE__REGS__SHIFT 0x3 +#define UVD_CGC_GATE__RBC_MASK 0x10 +#define UVD_CGC_GATE__RBC__SHIFT 0x4 +#define UVD_CGC_GATE__LMI_MC_MASK 0x20 +#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 +#define UVD_CGC_GATE__LMI_UMC_MASK 0x40 +#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 +#define UVD_CGC_GATE__IDCT_MASK 0x80 +#define UVD_CGC_GATE__IDCT__SHIFT 0x7 +#define UVD_CGC_GATE__MPRD_MASK 0x100 +#define UVD_CGC_GATE__MPRD__SHIFT 0x8 +#define UVD_CGC_GATE__MPC_MASK 0x200 +#define UVD_CGC_GATE__MPC__SHIFT 0x9 +#define UVD_CGC_GATE__LBSI_MASK 0x400 +#define UVD_CGC_GATE__LBSI__SHIFT 0xa +#define UVD_CGC_GATE__LRBBM_MASK 0x800 +#define UVD_CGC_GATE__LRBBM__SHIFT 0xb +#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 +#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc +#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 +#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd +#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 +#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe +#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 +#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf +#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 +#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 +#define UVD_CGC_GATE__WCB_MASK 0x20000 +#define UVD_CGC_GATE__WCB__SHIFT 0x11 +#define UVD_CGC_GATE__VCPU_MASK 0x40000 +#define UVD_CGC_GATE__VCPU__SHIFT 0x12 +#define UVD_CGC_GATE__SCPU_MASK 0x80000 +#define UVD_CGC_GATE__SCPU__SHIFT 0x13 +#define UVD_CGC_GATE__JPEG_MASK 0x100000 +#define UVD_CGC_GATE__JPEG__SHIFT 0x14 +#define UVD_CGC_GATE__JPEG2_MASK 0x200000 +#define UVD_CGC_GATE__JPEG2__SHIFT 0x15 +#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 +#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 +#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 +#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 +#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 +#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 +#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 +#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 +#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 +#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 +#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 +#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 +#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 +#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 +#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 +#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 +#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 +#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 +#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 +#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 +#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 +#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa +#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 +#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb +#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 +#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc +#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 +#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd +#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 +#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe +#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 +#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf +#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 +#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 +#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 +#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 +#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 +#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 +#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 +#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 +#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 +#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 +#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 +#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 +#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 +#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 +#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 +#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 +#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 +#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 +#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 +#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 +#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 +#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a +#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 +#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b +#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 +#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c +#define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000 +#define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000 +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f +#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 +#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 +#define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2 +#define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 +#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 +#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 +#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 +#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb +#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 +#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc +#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 +#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd +#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 +#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe +#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 +#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf +#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 +#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 +#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 +#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 +#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 +#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 +#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 +#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 +#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 +#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 +#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 +#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 +#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 +#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 +#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 +#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 +#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 +#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 +#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 +#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 +#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 +#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a +#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 +#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b +#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 +#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c +#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 +#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d +#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 +#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e +#define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000 +#define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f +#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 +#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 +#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 +#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 +#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 +#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 +#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 +#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 +#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 +#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 +#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 +#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 +#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 +#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 +#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 +#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 +#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 +#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 +#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 +#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 +#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 +#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa +#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 +#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb +#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 +#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc +#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 +#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd +#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 +#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe +#define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000 +#define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf +#define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000 +#define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10 +#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000 +#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11 +#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000 +#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12 +#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 +#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 +#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 +#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 +#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 +#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 +#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 +#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 +#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 +#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 +#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 +#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 +#define UVD_MASTINT_EN__SYS_EN_MASK 0x4 +#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 +#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 +#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 +#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf +#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 +#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 +#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 +#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 +#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 +#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 +#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc +#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 +#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 +#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 +#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 +#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 +#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 +#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 +#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 +#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 +#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 +#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 +#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb +#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 +#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc +#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 +#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd +#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 +#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe +#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 +#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a +#define UVD_LMI_CTRL__RFU_MASK 0xf8000000 +#define UVD_LMI_CTRL__RFU__SHIFT 0x1b +#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 +#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 +#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 +#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 +#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 +#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 +#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 +#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 +#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa +#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 +#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 +#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc +#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 +#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 +#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 +#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 +#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 +#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 +#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 +#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 +#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 +#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 +#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 +#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 +#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 +#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e +#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 +#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 +#define UVD_MPC_CNTL__PERF_RST_MASK 0x40 +#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 +#define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00 +#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 +#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 +#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 +#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 +#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 +#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f +#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 +#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 +#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc +#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 +#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 +#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f +#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 +#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 +#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc +#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f +#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 +#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 +#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc +#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 +#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 +#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f +#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 +#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 +#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc +#define UVD_MPC_SET_MUX__SET_0_MASK 0x7 +#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 +#define UVD_MPC_SET_MUX__SET_1_MASK 0x38 +#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 +#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 +#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 +#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 +#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 +#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 +#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 +#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf +#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 +#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 +#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 +#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 +#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 +#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 +#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 +#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 +#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 +#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 +#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa +#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 +#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb +#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 +#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd +#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 +#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 +#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000 +#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 +#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 +#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 +#define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000 +#define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 +#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 +#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c +#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 +#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e +#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 +#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f +#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 +#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 +#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 +#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 +#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 +#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 +#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 +#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 +#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 +#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 +#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 +#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 +#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 +#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 +#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200 +#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9 +#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 +#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa +#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 +#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb +#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 +#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd +#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 +#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe +#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 +#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf +#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 +#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 +#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000 +#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000 +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000 +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000 +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000 +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000 +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 +#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000 +#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 +#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000 +#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 +#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000 +#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000 +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000 +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000 +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000 +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000 +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000 +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f +#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf +#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 +#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 +#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf +#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 +#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 +#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 +#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f +#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 +#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 +#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 +#define UVD_STATUS__RBC_BUSY_MASK 0x1 +#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 +#define UVD_STATUS__VCPU_REPORT_MASK 0xfe +#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff +#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 +#define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 +#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define UVD_SUVD_CGC_GATE__SIT_MASK 0x2 +#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define UVD_SUVD_CGC_GATE__SMP_MASK 0x4 +#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define UVD_SUVD_CGC_GATE__SCM_MASK 0x8 +#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define UVD_SUVD_CGC_GATE__SDB_MASK 0x10 +#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 +#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40 +#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80 +#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100 +#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200 +#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400 +#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800 +#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 +#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1 +#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 +#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2 +#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 +#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4 +#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 +#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8 +#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 +#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10 +#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 +#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20 +#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100 +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400 +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800 +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000 +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000 +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd +#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 +#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2 +#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4 +#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8 +#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10 +#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf +#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0 +#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0 +#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4 +#define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00 +#define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8 +#define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000 +#define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc +#define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000 +#define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10 +#define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000 +#define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14 +#define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000 +#define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18 +#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000 +#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c +#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf +#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0 +#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0 +#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4 +#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00 +#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8 +#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000 +#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc +#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000 +#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10 +#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000 +#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14 +#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000 +#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18 +#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000 +#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c +#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 +#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 +#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 +#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 +#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 +#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 +#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 +#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 +#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 +#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 +#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 +#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 +#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf +#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 +#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 +#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 +#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 +#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 +#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 +#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 +#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 +#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 +#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 +#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 +#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 +#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa +#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 +#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb +#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 +#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc +#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 +#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd +#define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000 +#define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe +#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000 +#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 +#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c +#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000 +#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc +#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff +#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb +#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc +#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd +#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 +#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c +#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 +#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 +#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 +#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 +#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 +#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 +#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8 +#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3 +#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10 +#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4 +#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20 +#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5 +#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0 +#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6 +#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 +#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 +#define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200 +#define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9 +#define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400 +#define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa +#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0 +#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0 +#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0 +#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0 +#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff +#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e + +#endif /* UVD_6_0_SH_MASK_H */ -- cgit v1.2.3 From 683595a6f3c32d86952b57495bdecab370606b09 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:35:39 -0400 Subject: drm/amdgpu: add VCE 2.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the VCE (Video Codec Engine) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h | 68 ++++++++++++++ .../drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h | 104 +++++++++++++++++++++ 2 files changed, 172 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h new file mode 100644 index 000000000000..906433834d01 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h @@ -0,0 +1,68 @@ +/* + * VCE_2_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VCE_2_0_D_H +#define VCE_2_0_D_H + +#define mmVCE_STATUS 0x8001 +#define mmVCE_VCPU_CNTL 0x8005 +#define mmVCE_VCPU_CACHE_OFFSET0 0x8009 +#define mmVCE_VCPU_CACHE_SIZE0 0x800a +#define mmVCE_VCPU_CACHE_OFFSET1 0x800b +#define mmVCE_VCPU_CACHE_SIZE1 0x800c +#define mmVCE_VCPU_CACHE_OFFSET2 0x800d +#define mmVCE_VCPU_CACHE_SIZE2 0x800e +#define mmVCE_SOFT_RESET 0x8048 +#define mmVCE_RB_BASE_LO2 0x805b +#define mmVCE_RB_BASE_HI2 0x805c +#define mmVCE_RB_SIZE2 0x805d +#define mmVCE_RB_RPTR2 0x805e +#define mmVCE_RB_WPTR2 0x805f +#define mmVCE_RB_BASE_LO 0x8060 +#define mmVCE_RB_BASE_HI 0x8061 +#define mmVCE_RB_SIZE 0x8062 +#define mmVCE_RB_RPTR 0x8063 +#define mmVCE_RB_WPTR 0x8064 +#define mmVCE_RB_ARB_CTRL 0x809f +#define mmVCE_CLOCK_GATING_A 0x80be +#define mmVCE_CLOCK_GATING_B 0x80bf +#define mmVCE_UENC_DMA_DCLK_CTRL 0x8390 +#define mmVCE_CGTT_CLK_OVERRIDE 0x81e8 +#define mmVCE_UENC_CLOCK_GATING 0x81ef +#define mmVCE_UENC_REG_CLOCK_GATING 0x81f0 +#define mmVCE_SYS_INT_EN 0x84c0 +#define mmVCE_SYS_INT_STATUS 0x84c1 +#define mmVCE_SYS_INT_ACK 0x84c1 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8517 +#define mmVCE_LMI_CTRL2 0x851d +#define mmVCE_LMI_SWAP_CNTL3 0x851e +#define mmVCE_LMI_CTRL 0x8526 +#define mmVCE_LMI_STATUS 0x8527 +#define mmVCE_LMI_VM_CTRL 0x8528 +#define mmVCE_LMI_SWAP_CNTL 0x852d +#define mmVCE_LMI_SWAP_CNTL1 0x852e +#define mmVCE_LMI_SWAP_CNTL2 0x8533 +#define mmVCE_LMI_MISC_CTRL 0x8535 +#define mmVCE_LMI_CACHE_CTRL 0x853d + +#endif /* VCE_2_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h new file mode 100644 index 000000000000..9b4b952b9830 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h @@ -0,0 +1,104 @@ +/* + * VCE_2_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VCE_2_0_SH_MASK_H +#define VCE_2_0_SH_MASK_H + +#define VCE_STATUS__JOB_BUSY_MASK 0x1 +#define VCE_STATUS__JOB_BUSY__SHIFT 0x0 +#define VCE_STATUS__VCPU_REPORT_MASK 0xfe +#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1 +#define VCE_STATUS__UENC_BUSY_MASK 0x100 +#define VCE_STATUS__UENC_BUSY__SHIFT 0x8 +#define VCE_VCPU_CNTL__CLK_EN_MASK 0x1 +#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0 +#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000 +#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12 +#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0xfffffff +#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0 +#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0xffffff +#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0 +#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0xfffffff +#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0 +#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0xffffff +#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0 +#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0xfffffff +#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0 +#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0xffffff +#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0 +#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x1 +#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0 +#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0 +#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 +#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffff +#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 +#define VCE_RB_SIZE2__RB_SIZE_MASK 0x7ffff0 +#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4 +#define VCE_RB_RPTR2__RB_RPTR_MASK 0x7ffff0 +#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4 +#define VCE_RB_WPTR2__RB_WPTR_MASK 0x7ffff0 +#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4 +#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0 +#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 +#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffff +#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define VCE_RB_SIZE__RB_SIZE_MASK 0x7ffff0 +#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define VCE_RB_RPTR__RB_RPTR_MASK 0x7ffff0 +#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define VCE_RB_WPTR__RB_WPTR_MASK 0x7ffff0 +#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x1 +#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x0 +#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2 +#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x1 +#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x4 +#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2 +#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x8 +#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3 +#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x8 +#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3 +#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x8 +#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3 +#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffff +#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0 +#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 +#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 +#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3 +#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0 +#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 +#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 +#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3 +#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0 +#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x3ffc +#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2 +#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3 +#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0 +#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x3ffc +#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2 +#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0xff +#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0 +#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x1 +#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0 + +#endif /* VCE_2_0_SH_MASK_H */ -- cgit v1.2.3 From c481a6802e156a3666f1820674ed0c0828787bfa Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:36:06 -0400 Subject: drm/amdgpu: add VCE 3.0 register headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are register headers for the VCE (Video Codec Engine) block on the GPU. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- .../gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h | 73 +++++++++++++ .../drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h | 120 +++++++++++++++++++++ 2 files changed, 193 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h new file mode 100644 index 000000000000..3e698b7f42a2 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h @@ -0,0 +1,73 @@ +/* + * VCE_3_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VCE_3_0_D_H +#define VCE_3_0_D_H + +#define mmVCE_STATUS 0x8001 +#define mmVCE_VCPU_CNTL 0x8005 +#define mmVCE_VCPU_CACHE_OFFSET0 0x8009 +#define mmVCE_VCPU_CACHE_SIZE0 0x800a +#define mmVCE_VCPU_CACHE_OFFSET1 0x800b +#define mmVCE_VCPU_CACHE_SIZE1 0x800c +#define mmVCE_VCPU_CACHE_OFFSET2 0x800d +#define mmVCE_VCPU_CACHE_SIZE2 0x800e +#define mmVCE_SOFT_RESET 0x8048 +#define mmVCE_RB_BASE_LO2 0x805b +#define mmVCE_RB_BASE_HI2 0x805c +#define mmVCE_RB_SIZE2 0x805d +#define mmVCE_RB_RPTR2 0x805e +#define mmVCE_RB_WPTR2 0x805f +#define mmVCE_RB_BASE_LO 0x8060 +#define mmVCE_RB_BASE_HI 0x8061 +#define mmVCE_RB_SIZE 0x8062 +#define mmVCE_RB_RPTR 0x8063 +#define mmVCE_RB_WPTR 0x8064 +#define mmVCE_RB_ARB_CTRL 0x809f +#define mmVCE_CLOCK_GATING_A 0x80be +#define mmVCE_CLOCK_GATING_B 0x80bf +#define mmVCE_RB_BASE_LO3 0x80d4 +#define mmVCE_RB_BASE_HI3 0x80d5 +#define mmVCE_RB_SIZE3 0x80d6 +#define mmVCE_RB_RPTR3 0x80d7 +#define mmVCE_RB_WPTR3 0x80d8 +#define mmVCE_UENC_DMA_DCLK_CTRL 0x8390 +#define mmVCE_UENC_CLOCK_GATING 0x81ef +#define mmVCE_UENC_REG_CLOCK_GATING 0x81f0 +#define mmVCE_UENC_CLOCK_GATING_2 0x8210 +#define mmVCE_SYS_INT_EN 0x8540 +#define mmVCE_SYS_INT_STATUS 0x8541 +#define mmVCE_SYS_INT_ACK 0x8541 +#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8597 +#define mmVCE_LMI_CTRL2 0x859d +#define mmVCE_LMI_SWAP_CNTL3 0x859e +#define mmVCE_LMI_CTRL 0x85a6 +#define mmVCE_LMI_STATUS 0x85a7 +#define mmVCE_LMI_VM_CTRL 0x85a8 +#define mmVCE_LMI_SWAP_CNTL 0x85ad +#define mmVCE_LMI_SWAP_CNTL1 0x85ae +#define mmVCE_LMI_SWAP_CNTL2 0x85b3 +#define mmVCE_LMI_MISC_CTRL 0x85b5 +#define mmVCE_LMI_CACHE_CTRL 0x85bd + +#endif /* VCE_3_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h new file mode 100644 index 000000000000..235dc13561e9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h @@ -0,0 +1,120 @@ +/* + * VCE_3_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef VCE_3_0_SH_MASK_H +#define VCE_3_0_SH_MASK_H + +#define VCE_STATUS__JOB_BUSY_MASK 0x1 +#define VCE_STATUS__JOB_BUSY__SHIFT 0x0 +#define VCE_STATUS__VCPU_REPORT_MASK 0xfe +#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1 +#define VCE_STATUS__UENC_BUSY_MASK 0x100 +#define VCE_STATUS__UENC_BUSY__SHIFT 0x8 +#define VCE_STATUS__VCE_CONFIGURATION_MASK 0xc00000 +#define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16 +#define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x3000000 +#define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18 +#define VCE_VCPU_CNTL__CLK_EN_MASK 0x1 +#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0 +#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000 +#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12 +#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0xfffffff +#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0 +#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0xffffff +#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0 +#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0xfffffff +#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0 +#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0xffffff +#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0 +#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0xfffffff +#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0 +#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0xffffff +#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0 +#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x1 +#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0 +#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0 +#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 +#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffff +#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 +#define VCE_RB_SIZE2__RB_SIZE_MASK 0x7ffff0 +#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4 +#define VCE_RB_RPTR2__RB_RPTR_MASK 0x7ffff0 +#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4 +#define VCE_RB_WPTR2__RB_WPTR_MASK 0x7ffff0 +#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4 +#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0 +#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 +#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffff +#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define VCE_RB_SIZE__RB_SIZE_MASK 0x7ffff0 +#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define VCE_RB_RPTR__RB_RPTR_MASK 0x7ffff0 +#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define VCE_RB_WPTR__RB_WPTR_MASK 0x7ffff0 +#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK 0x10000 +#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE__SHIFT 0x10 +#define VCE_RB_BASE_LO3__RB_BASE_LO_MASK 0xffffffc0 +#define VCE_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 +#define VCE_RB_BASE_HI3__RB_BASE_HI_MASK 0xffffffff +#define VCE_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 +#define VCE_RB_SIZE3__RB_SIZE_MASK 0x7ffff0 +#define VCE_RB_SIZE3__RB_SIZE__SHIFT 0x4 +#define VCE_RB_RPTR3__RB_RPTR_MASK 0x7ffff0 +#define VCE_RB_RPTR3__RB_RPTR__SHIFT 0x4 +#define VCE_RB_WPTR3__RB_WPTR_MASK 0x7ffff0 +#define VCE_RB_WPTR3__RB_WPTR__SHIFT 0x4 +#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x1 +#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x0 +#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2 +#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x1 +#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x4 +#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2 +#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x8 +#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3 +#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x8 +#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3 +#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x8 +#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3 +#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffff +#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0 +#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 +#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 +#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3 +#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0 +#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 +#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 +#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3 +#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0 +#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x3ffc +#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2 +#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3 +#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0 +#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x3ffc +#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2 +#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0xff +#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0 +#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x1 +#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0 + +#endif /* VCE_3_0_SH_MASK_H */ -- cgit v1.2.3 From a02860aa2b2d082ad133067eaea5f33c4ca465e1 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Apr 2015 16:44:53 -0400 Subject: drm/amdgpu: add atombios headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These headers define the atombios table structure and driver interface. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ObjectID.h | 736 +++ drivers/gpu/drm/amd/amdgpu/atombios.h | 8555 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/pptable.h | 698 +++ 3 files changed, 9989 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/ObjectID.h create mode 100644 drivers/gpu/drm/amd/amdgpu/atombios.h create mode 100644 drivers/gpu/drm/amd/amdgpu/pptable.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/ObjectID.h b/drivers/gpu/drm/amd/amdgpu/ObjectID.h new file mode 100644 index 000000000000..06192698bd96 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/ObjectID.h @@ -0,0 +1,736 @@ +/* +* Copyright 2006-2007 Advanced Micro Devices, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +*/ +/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */ + +#ifndef _OBJECTID_H +#define _OBJECTID_H + +#if defined(_X86_) +#pragma pack(1) +#endif + +/****************************************************/ +/* Graphics Object Type Definition */ +/****************************************************/ +#define GRAPH_OBJECT_TYPE_NONE 0x0 +#define GRAPH_OBJECT_TYPE_GPU 0x1 +#define GRAPH_OBJECT_TYPE_ENCODER 0x2 +#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 +#define GRAPH_OBJECT_TYPE_ROUTER 0x4 +/* deleted */ +#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6 +#define GRAPH_OBJECT_TYPE_GENERIC 0x7 + +/****************************************************/ +/* Encoder Object ID Definition */ +/****************************************************/ +#define ENCODER_OBJECT_ID_NONE 0x00 + +/* Radeon Class Display Hardware */ +#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 +#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02 +#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03 +#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04 +#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */ +#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06 +#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07 + +/* External Third Party Encoders */ +#define ENCODER_OBJECT_ID_SI170B 0x08 +#define ENCODER_OBJECT_ID_CH7303 0x09 +#define ENCODER_OBJECT_ID_CH7301 0x0A +#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */ +#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C +#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D +#define ENCODER_OBJECT_ID_TITFP513 0x0E +#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */ +#define ENCODER_OBJECT_ID_VT1623 0x10 +#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11 +#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12 +#define ENCODER_OBJECT_ID_ALMOND 0x22 +#define ENCODER_OBJECT_ID_TRAVIS 0x23 +#define ENCODER_OBJECT_ID_NUTMEG 0x22 +#define ENCODER_OBJECT_ID_HDMI_ANX9805 0x26 + +/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */ +#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13 +#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14 +#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15 +#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */ +#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */ +#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */ +#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19 +#define ENCODER_OBJECT_ID_VT1625 0x1A +#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B +#define ENCODER_OBJECT_ID_DP_AN9801 0x1C +#define ENCODER_OBJECT_ID_DP_DP501 0x1D +#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E +#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F +#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 0x20 +#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 0x21 +#define ENCODER_OBJECT_ID_INTERNAL_VCE 0x24 +#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 0x25 +#define ENCODER_OBJECT_ID_INTERNAL_AMCLK 0x27 + +#define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO 0xFF + +/****************************************************/ +/* Connector Object ID Definition */ +/****************************************************/ +#define CONNECTOR_OBJECT_ID_NONE 0x00 +#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 +#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 +#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 +#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04 +#define CONNECTOR_OBJECT_ID_VGA 0x05 +#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06 +#define CONNECTOR_OBJECT_ID_SVIDEO 0x07 +#define CONNECTOR_OBJECT_ID_YPbPr 0x08 +#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09 +#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */ +#define CONNECTOR_OBJECT_ID_SCART 0x0B +#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C +#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D +#define CONNECTOR_OBJECT_ID_LVDS 0x0E +#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F +#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10 +#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11 +#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12 +#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13 +#define CONNECTOR_OBJECT_ID_eDP 0x14 +#define CONNECTOR_OBJECT_ID_MXM 0x15 +#define CONNECTOR_OBJECT_ID_LVDS_eDP 0x16 + +/* deleted */ + +/****************************************************/ +/* Router Object ID Definition */ +/****************************************************/ +#define ROUTER_OBJECT_ID_NONE 0x00 +#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01 + +/****************************************************/ +/* Generic Object ID Definition */ +/****************************************************/ +#define GENERIC_OBJECT_ID_NONE 0x00 +#define GENERIC_OBJECT_ID_GLSYNC 0x01 +#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE 0x02 +#define GENERIC_OBJECT_ID_MXM_OPM 0x03 +#define GENERIC_OBJECT_ID_STEREO_PIN 0x04 //This object could show up from Misc Object table, it follows ATOM_OBJECT format, and contains one ATOM_OBJECT_GPIO_CNTL_RECORD for the stereo pin + +/****************************************************/ +/* Graphics Object ENUM ID Definition */ +/****************************************************/ +#define GRAPH_OBJECT_ENUM_ID1 0x01 +#define GRAPH_OBJECT_ENUM_ID2 0x02 +#define GRAPH_OBJECT_ENUM_ID3 0x03 +#define GRAPH_OBJECT_ENUM_ID4 0x04 +#define GRAPH_OBJECT_ENUM_ID5 0x05 +#define GRAPH_OBJECT_ENUM_ID6 0x06 +#define GRAPH_OBJECT_ENUM_ID7 0x07 + +/****************************************************/ +/* Graphics Object ID Bit definition */ +/****************************************************/ +#define OBJECT_ID_MASK 0x00FF +#define ENUM_ID_MASK 0x0700 +#define RESERVED1_ID_MASK 0x0800 +#define OBJECT_TYPE_MASK 0x7000 +#define RESERVED2_ID_MASK 0x8000 + +#define OBJECT_ID_SHIFT 0x00 +#define ENUM_ID_SHIFT 0x08 +#define OBJECT_TYPE_SHIFT 0x0C + + +/****************************************************/ +/* Graphics Object family definition */ +/****************************************************/ +#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \ + GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT) +/****************************************************/ +/* GPU Object ID definition - Shared with BIOS */ +/****************************************************/ +#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT) + +/****************************************************/ +/* Encoder Object ID definition - Shared with BIOS */ +/****************************************************/ +/* +#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 +#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 +#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 +#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 +#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 +#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 +#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 +#define ENCODER_SIL170B_ENUM_ID1 0x2108 +#define ENCODER_CH7303_ENUM_ID1 0x2109 +#define ENCODER_CH7301_ENUM_ID1 0x210A +#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B +#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C +#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D +#define ENCODER_TITFP513_ENUM_ID1 0x210E +#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F +#define ENCODER_VT1623_ENUM_ID1 0x2110 +#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111 +#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112 +#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 +#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 +#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 +#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 +#define ENCODER_SI178_ENUM_ID1 0x2117 +#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 +#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 +#define ENCODER_VT1625_ENUM_ID1 0x211A +#define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B +#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C +#define ENCODER_DP_DP501_ENUM_ID1 0x211D +#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E +*/ +#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT) + +#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT) + +#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT) + +#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT) + +#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) + +#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) + + +#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT) + + +#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT) + +#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT) + +#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT) + +#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) + + +#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) + + +#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT + +#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) + +#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) + +#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT) + +#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT) + +#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT) + +#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY3_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY3_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 << OBJECT_ID_SHIFT) + +#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT) + +#define ENCODER_ALMOND_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT) + +#define ENCODER_ALMOND_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT) + +#define ENCODER_TRAVIS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT) + +#define ENCODER_TRAVIS_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT) + +#define ENCODER_NUTMEG_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_NUTMEG << OBJECT_ID_SHIFT) + +#define ENCODER_VCE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_VCE << OBJECT_ID_SHIFT) + +#define ENCODER_HDMI_ANX9805_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_HDMI_ANX9805 << OBJECT_ID_SHIFT) + +/****************************************************/ +/* Connector Object ID definition - Shared with BIOS */ +/****************************************************/ +/* +#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101 +#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102 +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103 +#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104 +#define CONNECTOR_VGA_ENUM_ID1 0x3105 +#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106 +#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107 +#define CONNECTOR_YPbPr_ENUM_ID1 0x3108 +#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109 +#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A +#define CONNECTOR_SCART_ENUM_ID1 0x310B +#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C +#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D +#define CONNECTOR_LVDS_ENUM_ID1 0x310E +#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F +#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110 +*/ +#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT) + +#define CONNECTOR_LVDS_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT) + +#define CONNECTOR_eDP_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT) + +#define CONNECTOR_eDP_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT) + +#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) + +#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) + +#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) + +#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) + +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) + +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) + +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) + +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) + +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) + +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) + +#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) + +#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) + +#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) + +#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) + +#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) + +#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) + +#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) + +#define CONNECTOR_COMPOSITE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) + +#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT) + +#define CONNECTOR_SVIDEO_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT) + +#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT) + +#define CONNECTOR_YPbPr_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT) + +#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT) + +#define CONNECTOR_D_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT) + +#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT) + +#define CONNECTOR_9PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT) + +#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT) + +#define CONNECTOR_SCART_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT) + +#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) + +#define CONNECTOR_HDMI_TYPE_A_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) + +#define CONNECTOR_HDMI_TYPE_A_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) + +#define CONNECTOR_HDMI_TYPE_A_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) + +#define CONNECTOR_HDMI_TYPE_A_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) + +#define CONNECTOR_HDMI_TYPE_A_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) + +#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT) + +#define CONNECTOR_HDMI_TYPE_B_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT) + +#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) + +#define CONNECTOR_7PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) + +#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) + +#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) + +#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) + +#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) + + +#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) + +#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) + +#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) + +#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) + +#define CONNECTOR_DISPLAYPORT_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) + +#define CONNECTOR_DISPLAYPORT_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) + +#define CONNECTOR_DISPLAYPORT_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) + +#define CONNECTOR_DISPLAYPORT_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) + +#define CONNECTOR_MXM_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_A + +#define CONNECTOR_MXM_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_B + +#define CONNECTOR_MXM_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_C + +#define CONNECTOR_MXM_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_D + +#define CONNECTOR_MXM_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_TXxx + +#define CONNECTOR_MXM_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_UXxx + +#define CONNECTOR_MXM_ENUM_ID7 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DAC + +#define CONNECTOR_LVDS_eDP_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT) + +#define CONNECTOR_LVDS_eDP_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT) + +/****************************************************/ +/* Router Object ID definition - Shared with BIOS */ +/****************************************************/ +#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT) + +/* deleted */ + +/****************************************************/ +/* Generic Object ID definition - Shared with BIOS */ +/****************************************************/ +#define GENERICOBJECT_GLSYNC_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + GENERIC_OBJECT_ID_GLSYNC << OBJECT_ID_SHIFT) + +#define GENERICOBJECT_PX2_NON_DRIVABLE_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT) + +#define GENERICOBJECT_PX2_NON_DRIVABLE_ID2 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT) + +#define GENERICOBJECT_MXM_OPM_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT) + +#define GENERICOBJECT_STEREO_PIN_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + GENERIC_OBJECT_ID_STEREO_PIN << OBJECT_ID_SHIFT) + +/****************************************************/ +/* Object Cap definition - Shared with BIOS */ +/****************************************************/ +#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L +#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L + + +#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01 +#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02 +#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03 + +#if defined(_X86_) +#pragma pack() +#endif + +#endif /*GRAPHICTYPE */ + + + + diff --git a/drivers/gpu/drm/amd/amdgpu/atombios.h b/drivers/gpu/drm/amd/amdgpu/atombios.h new file mode 100644 index 000000000000..44c5d4a4d1bf --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atombios.h @@ -0,0 +1,8555 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + + +/****************************************************************************/ +/*Portion I: Definitions shared between VBIOS and Driver */ +/****************************************************************************/ + +#ifndef _ATOMBIOS_H +#define _ATOMBIOS_H + +#define ATOM_VERSION_MAJOR 0x00020000 +#define ATOM_VERSION_MINOR 0x00000002 + +#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) + +/* Endianness should be specified before inclusion, + * default to little endian + */ +#ifndef ATOM_BIG_ENDIAN +#error Endian not specified +#endif + +#ifdef _H2INC + #ifndef ULONG + typedef unsigned long ULONG; + #endif + + #ifndef UCHAR + typedef unsigned char UCHAR; + #endif + + #ifndef USHORT + typedef unsigned short USHORT; + #endif +#endif + +#define ATOM_DAC_A 0 +#define ATOM_DAC_B 1 +#define ATOM_EXT_DAC 2 + +#define ATOM_CRTC1 0 +#define ATOM_CRTC2 1 +#define ATOM_CRTC3 2 +#define ATOM_CRTC4 3 +#define ATOM_CRTC5 4 +#define ATOM_CRTC6 5 + +#define ATOM_UNDERLAY_PIPE0 16 +#define ATOM_UNDERLAY_PIPE1 17 + +#define ATOM_CRTC_INVALID 0xFF + +#define ATOM_DIGA 0 +#define ATOM_DIGB 1 + +#define ATOM_PPLL1 0 +#define ATOM_PPLL2 1 +#define ATOM_DCPLL 2 +#define ATOM_PPLL0 2 +#define ATOM_PPLL3 3 + +#define ATOM_EXT_PLL1 8 +#define ATOM_EXT_PLL2 9 +#define ATOM_EXT_CLOCK 10 +#define ATOM_PPLL_INVALID 0xFF + +#define ENCODER_REFCLK_SRC_P1PLL 0 +#define ENCODER_REFCLK_SRC_P2PLL 1 +#define ENCODER_REFCLK_SRC_DCPLL 2 +#define ENCODER_REFCLK_SRC_EXTCLK 3 +#define ENCODER_REFCLK_SRC_INVALID 0xFF + +#define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication +#define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication +#define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode +#define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios + +#define ATOM_DISABLE 0 +#define ATOM_ENABLE 1 +#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) +#define ATOM_LCD_BLON (ATOM_ENABLE+2) +#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) +#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) +#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) +#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) +#define ATOM_INIT (ATOM_DISABLE+7) +#define ATOM_GET_STATUS (ATOM_DISABLE+8) + +#define ATOM_BLANKING 1 +#define ATOM_BLANKING_OFF 0 + + +#define ATOM_CRT1 0 +#define ATOM_CRT2 1 + +#define ATOM_TV_NTSC 1 +#define ATOM_TV_NTSCJ 2 +#define ATOM_TV_PAL 3 +#define ATOM_TV_PALM 4 +#define ATOM_TV_PALCN 5 +#define ATOM_TV_PALN 6 +#define ATOM_TV_PAL60 7 +#define ATOM_TV_SECAM 8 +#define ATOM_TV_CV 16 + +#define ATOM_DAC1_PS2 1 +#define ATOM_DAC1_CV 2 +#define ATOM_DAC1_NTSC 3 +#define ATOM_DAC1_PAL 4 + +#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 +#define ATOM_DAC2_CV ATOM_DAC1_CV +#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC +#define ATOM_DAC2_PAL ATOM_DAC1_PAL + +#define ATOM_PM_ON 0 +#define ATOM_PM_STANDBY 1 +#define ATOM_PM_SUSPEND 2 +#define ATOM_PM_OFF 3 + +// For ATOM_LVDS_INFO_V12 +// Bit0:{=0:single, =1:dual}, +// Bit1 {=0:666RGB, =1:888RGB}, +// Bit2:3:{Grey level} +// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} +#define ATOM_PANEL_MISC_DUAL 0x00000001 +#define ATOM_PANEL_MISC_888RGB 0x00000002 +#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C +#define ATOM_PANEL_MISC_FPDI 0x00000010 +#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 +#define ATOM_PANEL_MISC_SPATIAL 0x00000020 +#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 +#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 + +#define MEMTYPE_DDR1 "DDR1" +#define MEMTYPE_DDR2 "DDR2" +#define MEMTYPE_DDR3 "DDR3" +#define MEMTYPE_DDR4 "DDR4" + +#define ASIC_BUS_TYPE_PCI "PCI" +#define ASIC_BUS_TYPE_AGP "AGP" +#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" + +//Maximum size of that FireGL flag string +#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support +#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) + +#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop +#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING + +#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support +#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) + +#define HW_ASSISTED_I2C_STATUS_FAILURE 2 +#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 + +#pragma pack(1) // BIOS data must use byte aligment + +// Define offset to location of ROM header. +#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L +#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L + +#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 +#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 //including the terminator 0x0! +#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f +#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e + +/****************************************************************************/ +// Common header for all tables (Data table, Command table). +// Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. +// And the pointer actually points to this header. +/****************************************************************************/ + +typedef struct _ATOM_COMMON_TABLE_HEADER +{ + USHORT usStructureSize; + UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible + UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware + //Image can't be updated, while Driver needs to carry the new table! +}ATOM_COMMON_TABLE_HEADER; + +/****************************************************************************/ +// Structure stores the ROM header. +/****************************************************************************/ +typedef struct _ATOM_ROM_HEADER +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, + //atombios should init it as "ATOM", don't change the position + USHORT usBiosRuntimeSegmentAddress; + USHORT usProtectedModeInfoOffset; + USHORT usConfigFilenameOffset; + USHORT usCRC_BlockOffset; + USHORT usBIOS_BootupMessageOffset; + USHORT usInt10Offset; + USHORT usPciBusDevInitCode; + USHORT usIoBaseAddress; + USHORT usSubsystemVendorID; + USHORT usSubsystemID; + USHORT usPCI_InfoOffset; + USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position + USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position + UCHAR ucExtendedFunctionCode; + UCHAR ucReserved; +}ATOM_ROM_HEADER; + +//==============================Command Table Portion==================================== + + +/****************************************************************************/ +// Structures used in Command.mtb +/****************************************************************************/ +typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ + USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 + USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON + USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios + USHORT DIGxEncoderControl; //Only used by Bios + USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 + USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed + USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 + USHORT GPIOPinControl; //Atomic Table, only used by Bios + USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 + USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 + USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 + USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT MemoryPLLInit; //Atomic Table, used only by Bios + USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. + USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios + USHORT SetUniphyInstance; //Atomic Table, only used by Bios + USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 + USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 + USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead + USHORT GetConditionalGoldenSetting; //Only used by Bios + USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1 + USHORT PatchMCSetting; //only used by BIOS + USHORT MC_SEQ_Control; //only used by BIOS + USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting + USHORT EnableScaler; //Atomic Table, used only by Bios + USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 + USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios + USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 + USHORT SetCRTC_Replication; //Atomic Table, used only by Bios + USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios + USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios + USHORT LUT_AutoFill; //Atomic Table, only used by Bios + USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios + USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 + USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios + USHORT MemoryCleanUp; //Atomic Table, only used by Bios + USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios + USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components + USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components + USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init + USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock + USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock + USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios + USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT MemoryTraining; //Atomic Table, used only by Bios + USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 + USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 + USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" + USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender + USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios + USHORT DPEncoderService; //Function Table,only used by Bios + USHORT GetVoltageInfo; //Function Table,only used by Bios since SI +}ATOM_MASTER_LIST_OF_COMMAND_TABLES; + +// For backward compatible +#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction +#define DPTranslatorControl DIG2EncoderControl +#define UNIPHYTransmitterControl DIG1TransmitterControl +#define LVTMATransmitterControl DIG2TransmitterControl +#define SetCRTC_DPM_State GetConditionalGoldenSetting +#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance +#define HPDInterruptService ReadHWAssistedI2CStatus +#define EnableVGA_Access GetSCLKOverMCLKRatio +#define EnableYUV GetDispObjectInfo +#define DynamicClockGating EnableDispPowerGating +#define SetupHWAssistedI2CStatus ComputeMemoryClockParam +#define DAC2OutputControl ReadEfuseValue + +#define TMDSAEncoderControl PatchMCSetting +#define LVDSEncoderControl MC_SEQ_Control +#define LCD1OutputControl HW_Misc_Operation +#define TV1OutputControl Gfx_Harvesting +#define TVEncoderControl SMC_Init + +typedef struct _ATOM_MASTER_COMMAND_TABLE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; +}ATOM_MASTER_COMMAND_TABLE; + +/****************************************************************************/ +// Structures used in every command table +/****************************************************************************/ +typedef struct _ATOM_TABLE_ATTRIBUTE +{ +#if ATOM_BIG_ENDIAN + USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag + USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), +#else + USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), + USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag +#endif +}ATOM_TABLE_ATTRIBUTE; + +/****************************************************************************/ +// Common header for all command tables. +// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. +// And the pointer actually points to this header. +/****************************************************************************/ +typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER +{ + ATOM_COMMON_TABLE_HEADER CommonHeader; + ATOM_TABLE_ATTRIBUTE TableAttribute; +}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; + +/****************************************************************************/ +// Structures used by ComputeMemoryEnginePLLTable +/****************************************************************************/ + +#define COMPUTE_MEMORY_PLL_PARAM 1 +#define COMPUTE_ENGINE_PLL_PARAM 2 +#define ADJUST_MC_SETTING_PARAM 3 + +/****************************************************************************/ +// Structures used by AdjustMemoryControllerTable +/****************************************************************************/ +typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ +{ +#if ATOM_BIG_ENDIAN + ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block + ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] + ULONG ulClockFreq:24; +#else + ULONG ulClockFreq:24; + ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] + ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block +#endif +}ATOM_ADJUST_MEMORY_CLOCK_FREQ; +#define POINTER_RETURN_FLAG 0x80 + +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS +{ + ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div + UCHAR ucAction; //0:reserved //1:Memory //2:Engine + UCHAR ucReserved; //may expand to return larger Fbdiv later + UCHAR ucFbDiv; //return value + UCHAR ucPostDiv; //return value +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; + +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 +{ + ULONG ulClock; //When return, [23:0] return real clock + UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register + USHORT usFbDiv; //return Feedback value to be written to register + UCHAR ucPostDiv; //return post div to be written to register +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; + +#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS + +#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value +#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) +#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition +#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change +#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup +#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL +#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK + +#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) +#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition +#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change +#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup +#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL +#define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path + +typedef struct _ATOM_COMPUTE_CLOCK_FREQ +{ +#if ATOM_BIG_ENDIAN + ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM + ULONG ulClockFreq:24; // in unit of 10kHz +#else + ULONG ulClockFreq:24; // in unit of 10kHz + ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM +#endif +}ATOM_COMPUTE_CLOCK_FREQ; + +typedef struct _ATOM_S_MPLL_FB_DIVIDER +{ + USHORT usFbDivFrac; + USHORT usFbDiv; +}ATOM_S_MPLL_FB_DIVIDER; + +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 +{ + union + { + ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter + ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter + }; + UCHAR ucRefDiv; //Output Parameter + UCHAR ucPostDiv; //Output Parameter + UCHAR ucCntlFlag; //Output Parameter + UCHAR ucReserved; +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; + +// ucCntlFlag +#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 +#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 +#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 +#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 + + +// V4 are only used for APU which PLL outside GPU +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 +{ +#if ATOM_BIG_ENDIAN + ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly + ULONG ulClock:24; //Input= target clock, output = actual clock +#else + ULONG ulClock:24; //Input= target clock, output = actual clock + ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly +#endif +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; + +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 +{ + union + { + ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter + ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter + }; + UCHAR ucRefDiv; //Output Parameter + UCHAR ucPostDiv; //Output Parameter + union + { + UCHAR ucCntlFlag; //Output Flags + UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode + }; + UCHAR ucReserved; +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; + + +typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 +{ + ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter + ULONG ulReserved[2]; +}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; + +//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag +#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f +#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 +#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 + + +typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 +{ + COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider + ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider + UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider + UCHAR ucPllPostDiv; //Output Parameter: PLL post divider + UCHAR ucPllCntlFlag; //Output Flags: control flag + UCHAR ucReserved; +}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; + +//ucPllCntlFlag +#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 + + +// ucInputFlag +#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode + +// use for ComputeMemoryClockParamTable +typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 +{ + union + { + ULONG ulClock; + ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) + }; + UCHAR ucDllSpeed; //Output + UCHAR ucPostDiv; //Output + union{ + UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode + UCHAR ucPllCntlFlag; //Output: + }; + UCHAR ucBWCntl; +}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; + +// definition of ucInputFlag +#define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 +// definition of ucPllCntlFlag +#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 +#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 +#define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 +#define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 + +//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL +#define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 + +typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER +{ + ATOM_COMPUTE_CLOCK_FREQ ulClock; + ULONG ulReserved[2]; +}DYNAMICE_MEMORY_SETTINGS_PARAMETER; + +typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER +{ + ATOM_COMPUTE_CLOCK_FREQ ulClock; + ULONG ulMemoryClock; + ULONG ulReserved; +}DYNAMICE_ENGINE_SETTINGS_PARAMETER; + +/****************************************************************************/ +// Structures used by SetEngineClockTable +/****************************************************************************/ +typedef struct _SET_ENGINE_CLOCK_PARAMETERS +{ + ULONG ulTargetEngineClock; //In 10Khz unit +}SET_ENGINE_CLOCK_PARAMETERS; + +typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION +{ + ULONG ulTargetEngineClock; //In 10Khz unit + COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; +}SET_ENGINE_CLOCK_PS_ALLOCATION; + +/****************************************************************************/ +// Structures used by SetMemoryClockTable +/****************************************************************************/ +typedef struct _SET_MEMORY_CLOCK_PARAMETERS +{ + ULONG ulTargetMemoryClock; //In 10Khz unit +}SET_MEMORY_CLOCK_PARAMETERS; + +typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION +{ + ULONG ulTargetMemoryClock; //In 10Khz unit + COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; +}SET_MEMORY_CLOCK_PS_ALLOCATION; + +/****************************************************************************/ +// Structures used by ASIC_Init.ctb +/****************************************************************************/ +typedef struct _ASIC_INIT_PARAMETERS +{ + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit +}ASIC_INIT_PARAMETERS; + +typedef struct _ASIC_INIT_PS_ALLOCATION +{ + ASIC_INIT_PARAMETERS sASICInitClocks; + SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure +}ASIC_INIT_PS_ALLOCATION; + +typedef struct _ASIC_INIT_CLOCK_PARAMETERS +{ + ULONG ulClkFreqIn10Khz:24; + ULONG ucClkFlag:8; +}ASIC_INIT_CLOCK_PARAMETERS; + +typedef struct _ASIC_INIT_PARAMETERS_V1_2 +{ + ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit + ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit +}ASIC_INIT_PARAMETERS_V1_2; + +typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2 +{ + ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks; + ULONG ulReserved[8]; +}ASIC_INIT_PS_ALLOCATION_V1_2; + +/****************************************************************************/ +// Structure used by DynamicClockGatingTable.ctb +/****************************************************************************/ +typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[3]; +}DYNAMIC_CLOCK_GATING_PARAMETERS; +#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS + +/****************************************************************************/ +// Structure used by EnableDispPowerGatingTable.ctb +/****************************************************************************/ +typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 +{ + UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[2]; +}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; + +typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION +{ + UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... + UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT + UCHAR ucPadding[2]; + ULONG ulReserved[4]; +}ENABLE_DISP_POWER_GATING_PS_ALLOCATION; + +/****************************************************************************/ +// Structure used by EnableASIC_StaticPwrMgtTable.ctb +/****************************************************************************/ +typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[3]; +}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; +#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS + +/****************************************************************************/ +// Structures used by DAC_LoadDetectionTable.ctb +/****************************************************************************/ +typedef struct _DAC_LOAD_DETECTION_PARAMETERS +{ + USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} + UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} + UCHAR ucMisc; //Valid only when table revision =1.3 and above +}DAC_LOAD_DETECTION_PARAMETERS; + +// DAC_LOAD_DETECTION_PARAMETERS.ucMisc +#define DAC_LOAD_MISC_YPrPb 0x01 + +typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION +{ + DAC_LOAD_DETECTION_PARAMETERS sDacload; + ULONG Reserved[2];// Don't set this one, allocation for EXT DAC +}DAC_LOAD_DETECTION_PS_ALLOCATION; + +/****************************************************************************/ +// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb +/****************************************************************************/ +typedef struct _DAC_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder + // 7: ATOM_ENCODER_INIT Initialize DAC +}DAC_ENCODER_CONTROL_PARAMETERS; + +#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS + +/****************************************************************************/ +// Structures used by DIG1EncoderControlTable +// DIG2EncoderControlTable +// ExternalEncoderControlTable +/****************************************************************************/ +typedef struct _DIG_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucConfig; + // [2] Link Select: + // =0: PHY linkA if bfLane<3 + // =1: PHY linkB if bfLanes<3 + // =0: PHY linkA+B if bfLanes=3 + // [3] Transmitter Sel + // =0: UNIPHY or PCIEPHY + // =1: LVTMA + UCHAR ucAction; // =0: turn off encoder + // =1: turn on encoder + UCHAR ucEncoderMode; + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder + // =3: HDMI encoder + // =4: SDVO encoder + UCHAR ucLaneNum; // how many lanes to enable + UCHAR ucReserved[2]; +}DIG_ENCODER_CONTROL_PARAMETERS; +#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS +#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS + +//ucConfig +#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 +#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 +#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 +#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 +#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 +#define ATOM_ENCODER_CONFIG_LINKA 0x00 +#define ATOM_ENCODER_CONFIG_LINKB 0x04 +#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA +#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB +#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 +#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 +#define ATOM_ENCODER_CONFIG_LVTMA 0x08 +#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 +#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 +#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 +// ucAction +// ATOM_ENABLE: Enable Encoder +// ATOM_DISABLE: Disable Encoder + +//ucEncoderMode +#define ATOM_ENCODER_MODE_DP 0 +#define ATOM_ENCODER_MODE_LVDS 1 +#define ATOM_ENCODER_MODE_DVI 2 +#define ATOM_ENCODER_MODE_HDMI 3 +#define ATOM_ENCODER_MODE_SDVO 4 +#define ATOM_ENCODER_MODE_DP_AUDIO 5 +#define ATOM_ENCODER_MODE_TV 13 +#define ATOM_ENCODER_MODE_CV 14 +#define ATOM_ENCODER_MODE_CRT 15 +#define ATOM_ENCODER_MODE_DVO 16 +#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 +#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 + + +typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 +{ +#if ATOM_BIG_ENDIAN + UCHAR ucReserved1:2; + UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF + UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F + UCHAR ucReserved:1; + UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz +#else + UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz + UCHAR ucReserved:1; + UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F + UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF + UCHAR ucReserved1:2; +#endif +}ATOM_DIG_ENCODER_CONFIG_V2; + + +typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + ATOM_DIG_ENCODER_CONFIG_V2 acConfig; + UCHAR ucAction; + UCHAR ucEncoderMode; + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder + // =3: HDMI encoder + // =4: SDVO encoder + UCHAR ucLaneNum; // how many lanes to enable + UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS + UCHAR ucReserved; +}DIG_ENCODER_CONTROL_PARAMETERS_V2; + +//ucConfig +#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 +#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 +#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 +#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 +#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 +#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 +#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 + +// ucAction: +// ATOM_DISABLE +// ATOM_ENABLE +#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 +#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 +#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a +#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 +#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b +#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c +#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d +#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e +#define ATOM_ENCODER_CMD_SETUP 0x0f +#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 + +// ucStatus +#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 +#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 + +//ucTableFormatRevision=1 +//ucTableContentRevision=3 +// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver +typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 +{ +#if ATOM_BIG_ENDIAN + UCHAR ucReserved1:1; + UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) + UCHAR ucReserved:3; + UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz +#else + UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz + UCHAR ucReserved:3; + UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) + UCHAR ucReserved1:1; +#endif +}ATOM_DIG_ENCODER_CONFIG_V3; + +#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 +#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 +#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 +#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 +#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 +#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 +#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 +#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 +#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 +#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 + +typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + ATOM_DIG_ENCODER_CONFIG_V3 acConfig; + UCHAR ucAction; + union{ + UCHAR ucEncoderMode; + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder + // =3: HDMI encoder + // =4: SDVO encoder + // =5: DP audio + UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE + // =0: external DP + // =0x1: internal DP2 + // =0x11: internal DP1 for NutMeg/Travis DP translator + }; + UCHAR ucLaneNum; // how many lanes to enable + UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP + UCHAR ucReserved; +}DIG_ENCODER_CONTROL_PARAMETERS_V3; + +//ucTableFormatRevision=1 +//ucTableContentRevision=4 +// start from NI +// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver +typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 +{ +#if ATOM_BIG_ENDIAN + UCHAR ucReserved1:1; + UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) + UCHAR ucReserved:2; + UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version +#else + UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version + UCHAR ucReserved:2; + UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) + UCHAR ucReserved1:1; +#endif +}ATOM_DIG_ENCODER_CONFIG_V4; + +#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 +#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 +#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 +#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 +#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 +#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 +#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 +#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 +#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 +#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 +#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 +#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 +#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 + +typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + union{ + ATOM_DIG_ENCODER_CONFIG_V4 acConfig; + UCHAR ucConfig; + }; + UCHAR ucAction; + union{ + UCHAR ucEncoderMode; + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder + // =3: HDMI encoder + // =4: SDVO encoder + // =5: DP audio + UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE + // =0: external DP + // =0x1: internal DP2 + // =0x11: internal DP1 for NutMeg/Travis DP translator + }; + UCHAR ucLaneNum; // how many lanes to enable + UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP + UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version +}DIG_ENCODER_CONTROL_PARAMETERS_V4; + +// define ucBitPerColor: +#define PANEL_BPC_UNDEFINE 0x00 +#define PANEL_6BIT_PER_COLOR 0x01 +#define PANEL_8BIT_PER_COLOR 0x02 +#define PANEL_10BIT_PER_COLOR 0x03 +#define PANEL_12BIT_PER_COLOR 0x04 +#define PANEL_16BIT_PER_COLOR 0x05 + +//define ucPanelMode +#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 +#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 +#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 + +/****************************************************************************/ +// Structures used by UNIPHYTransmitterControlTable +// LVTMATransmitterControlTable +// DVOOutputControlTable +/****************************************************************************/ +typedef struct _ATOM_DP_VS_MODE +{ + UCHAR ucLaneSel; + UCHAR ucLaneSet; +}ATOM_DP_VS_MODE; + +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS +{ + union + { + USHORT usPixelClock; // in 10KHz; for bios convenient + USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h + ATOM_DP_VS_MODE asMode; // DP Voltage swing mode + }; + UCHAR ucConfig; + // [0]=0: 4 lane Link, + // =1: 8 lane Link ( Dual Links TMDS ) + // [1]=0: InCoherent mode + // =1: Coherent Mode + // [2] Link Select: + // =0: PHY linkA if bfLane<3 + // =1: PHY linkB if bfLanes<3 + // =0: PHY linkA+B if bfLanes=3 + // [5:4]PCIE lane Sel + // =0: lane 0~3 or 0~7 + // =1: lane 4~7 + // =2: lane 8~11 or 8~15 + // =3: lane 12~15 + UCHAR ucAction; // =0: turn off encoder + // =1: turn on encoder + UCHAR ucReserved[4]; +}DIG_TRANSMITTER_CONTROL_PARAMETERS; + +#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS + +//ucInitInfo +#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff + +//ucConfig +#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 +#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 +#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 +#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 +#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 +#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 + +#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE +#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE +#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE + +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 +#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 +#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 +#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 +#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 +#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 +#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 +#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 + +//ucAction +#define ATOM_TRANSMITTER_ACTION_DISABLE 0 +#define ATOM_TRANSMITTER_ACTION_ENABLE 1 +#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 +#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 +#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 +#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 +#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 +#define ATOM_TRANSMITTER_ACTION_INIT 7 +#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 +#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 +#define ATOM_TRANSMITTER_ACTION_SETUP 10 +#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 +#define ATOM_TRANSMITTER_ACTION_POWER_ON 12 +#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 + +// Following are used for DigTransmitterControlTable ver1.2 +typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 +{ +#if ATOM_BIG_ENDIAN + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) + UCHAR ucReserved:1; + UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector +#else + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) + UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector + UCHAR ucReserved:1; + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) +#endif +}ATOM_DIG_TRANSMITTER_CONFIG_V2; + +//ucConfig +//Bit0 +#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 + +//Bit1 +#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 + +//Bit2 +#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 +#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 + +// Bit3 +#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 +#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP +#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP + +// Bit4 +#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 + +// Bit7:6 +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD +#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF + +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 +{ + union + { + USHORT usPixelClock; // in 10KHz; for bios convenient + USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h + ATOM_DP_VS_MODE asMode; // DP Voltage swing mode + }; + ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; + UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX + UCHAR ucReserved[4]; +}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; + +typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 +{ +#if ATOM_BIG_ENDIAN + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) + UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector +#else + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F + UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) +#endif +}ATOM_DIG_TRANSMITTER_CONFIG_V3; + + +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 +{ + union + { + USHORT usPixelClock; // in 10KHz; for bios convenient + USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h + ATOM_DP_VS_MODE asMode; // DP Voltage swing mode + }; + ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; + UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX + UCHAR ucLaneNum; + UCHAR ucReserved[3]; +}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; + +//ucConfig +//Bit0 +#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 + +//Bit1 +#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 + +//Bit2 +#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 +#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 + +// Bit3 +#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 +#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 +#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 + +// Bit5:4 +#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 +#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 +#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 +#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 + +// Bit7:6 +#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 +#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB +#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD +#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF + + +/****************************************************************************/ +// Structures used by UNIPHYTransmitterControlTable V1.4 +// ASIC Families: NI +// ucTableFormatRevision=1 +// ucTableContentRevision=4 +/****************************************************************************/ +typedef struct _ATOM_DP_VS_MODE_V4 +{ + UCHAR ucLaneSel; + union + { + UCHAR ucLaneSet; + struct { +#if ATOM_BIG_ENDIAN + UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 + UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level + UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level +#else + UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level + UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level + UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 +#endif + }; + }; +}ATOM_DP_VS_MODE_V4; + +typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 +{ +#if ATOM_BIG_ENDIAN + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) + UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector +#else + UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector + UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) + UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E + // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F + UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F + UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New + UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) + // =1 Dig Transmitter 2 ( Uniphy CD ) + // =2 Dig Transmitter 3 ( Uniphy EF ) +#endif +}ATOM_DIG_TRANSMITTER_CONFIG_V4; + +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 +{ + union + { + USHORT usPixelClock; // in 10KHz; for bios convenient + USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h + ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version + }; + union + { + ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; + UCHAR ucConfig; + }; + UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX + UCHAR ucLaneNum; + UCHAR ucReserved[3]; +}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; + +//ucConfig +//Bit0 +#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 +//Bit1 +#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 +//Bit2 +#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 +#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 +// Bit3 +#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 +#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 +#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 +// Bit5:4 +#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 +#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 +#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 +#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 +#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 +// Bit7:6 +#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 +#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB +#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD +#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF + + +typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 +{ +#if ATOM_BIG_ENDIAN + UCHAR ucReservd1:1; + UCHAR ucHPDSel:3; + UCHAR ucPhyClkSrcId:2; + UCHAR ucCoherentMode:1; + UCHAR ucReserved:1; +#else + UCHAR ucReserved:1; + UCHAR ucCoherentMode:1; + UCHAR ucPhyClkSrcId:2; + UCHAR ucHPDSel:3; + UCHAR ucReservd1:1; +#endif +}ATOM_DIG_TRANSMITTER_CONFIG_V5; + +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 +{ + USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio + UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF + UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx + UCHAR ucLaneNum; // indicate lane number 1-8 + UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h + UCHAR ucDigMode; // indicate DIG mode + union{ + ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; + UCHAR ucConfig; + }; + UCHAR ucDigEncoderSel; // indicate DIG front end encoder + UCHAR ucDPLaneSet; + UCHAR ucReserved; + UCHAR ucReserved1; +}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; + +//ucPhyId +#define ATOM_PHY_ID_UNIPHYA 0 +#define ATOM_PHY_ID_UNIPHYB 1 +#define ATOM_PHY_ID_UNIPHYC 2 +#define ATOM_PHY_ID_UNIPHYD 3 +#define ATOM_PHY_ID_UNIPHYE 4 +#define ATOM_PHY_ID_UNIPHYF 5 +#define ATOM_PHY_ID_UNIPHYG 6 + +// ucDigEncoderSel +#define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 +#define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 +#define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 +#define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 +#define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 +#define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 +#define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 + +// ucDigMode +#define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 +#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 +#define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 +#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 +#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 +#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 + +// ucDPLaneSet +#define DP_LANE_SET__0DB_0_4V 0x00 +#define DP_LANE_SET__0DB_0_6V 0x01 +#define DP_LANE_SET__0DB_0_8V 0x02 +#define DP_LANE_SET__0DB_1_2V 0x03 +#define DP_LANE_SET__3_5DB_0_4V 0x08 +#define DP_LANE_SET__3_5DB_0_6V 0x09 +#define DP_LANE_SET__3_5DB_0_8V 0x0a +#define DP_LANE_SET__6DB_0_4V 0x10 +#define DP_LANE_SET__6DB_0_6V 0x11 +#define DP_LANE_SET__9_5DB_0_4V 0x18 + +// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; +// Bit1 +#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 + +// Bit3:2 +#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c +#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 + +#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 +#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 +#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 +#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c +// Bit6:4 +#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 +#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 + +#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 +#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 +#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 +#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 +#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 +#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 +#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 + +#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 + + +/****************************************************************************/ +// Structures used by ExternalEncoderControlTable V1.3 +// ASIC Families: Evergreen, Llano, NI +// ucTableFormatRevision=1 +// ucTableContentRevision=3 +/****************************************************************************/ + +typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 +{ + union{ + USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT + USHORT usConnectorId; // connector id, valid when ucAction = INIT + }; + UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT + UCHAR ucAction; // + UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT + UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT + UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP + UCHAR ucReserved; +}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; + +// ucAction +#define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 +#define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 +#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 +#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f +#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 +#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 +#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 +#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 + +// ucConfig +#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 +#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 +#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 +#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 +#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS 0x70 +#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 +#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 +#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 + +typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 +{ + EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; + ULONG ulReserved[2]; +}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; + + +/****************************************************************************/ +// Structures used by DAC1OuputControlTable +// DAC2OuputControlTable +// LVTMAOutputControlTable (Before DEC30) +// TMDSAOutputControlTable (Before DEC30) +/****************************************************************************/ +typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +{ + UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE + // When the display is LCD, in addition to above: + // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| + // ATOM_LCD_SELFTEST_STOP + + UCHAR aucPadding[3]; // padding to DWORD aligned +}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; + +#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS + + +#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION +#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS + + +typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2 +{ + // Possible value of ucAction + // ATOM_TRANSMITTER_ACTION_LCD_BLON + // ATOM_TRANSMITTER_ACTION_LCD_BLOFF + // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL + // ATOM_TRANSMITTER_ACTION_POWER_ON + // ATOM_TRANSMITTER_ACTION_POWER_OFF + UCHAR ucAction; + UCHAR ucBriLevel; + USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz +}LVTMA_OUTPUT_CONTROL_PARAMETERS_V2; + + + +/****************************************************************************/ +// Structures used by BlankCRTCTable +/****************************************************************************/ +typedef struct _BLANK_CRTC_PARAMETERS +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF + USHORT usBlackColorRCr; + USHORT usBlackColorGY; + USHORT usBlackColorBCb; +}BLANK_CRTC_PARAMETERS; +#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS + +/****************************************************************************/ +// Structures used by EnableCRTCTable +// EnableCRTCMemReqTable +// UpdateCRTC_DoubleBufferRegistersTable +/****************************************************************************/ +typedef struct _ENABLE_CRTC_PARAMETERS +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[2]; +}ENABLE_CRTC_PARAMETERS; +#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS + +/****************************************************************************/ +// Structures used by SetCRTC_OverScanTable +/****************************************************************************/ +typedef struct _SET_CRTC_OVERSCAN_PARAMETERS +{ + USHORT usOverscanRight; // right + USHORT usOverscanLeft; // left + USHORT usOverscanBottom; // bottom + USHORT usOverscanTop; // top + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucPadding[3]; +}SET_CRTC_OVERSCAN_PARAMETERS; +#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS + +/****************************************************************************/ +// Structures used by SetCRTC_ReplicationTable +/****************************************************************************/ +typedef struct _SET_CRTC_REPLICATION_PARAMETERS +{ + UCHAR ucH_Replication; // horizontal replication + UCHAR ucV_Replication; // vertical replication + UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucPadding; +}SET_CRTC_REPLICATION_PARAMETERS; +#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS + +/****************************************************************************/ +// Structures used by SelectCRTC_SourceTable +/****************************************************************************/ +typedef struct _SELECT_CRTC_SOURCE_PARAMETERS +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... + UCHAR ucPadding[2]; +}SELECT_CRTC_SOURCE_PARAMETERS; +#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS + +typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO + UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO + UCHAR ucPadding; +}SELECT_CRTC_SOURCE_PARAMETERS_V2; + +//ucEncoderID +//#define ASIC_INT_DAC1_ENCODER_ID 0x00 +//#define ASIC_INT_TV_ENCODER_ID 0x02 +//#define ASIC_INT_DIG1_ENCODER_ID 0x03 +//#define ASIC_INT_DAC2_ENCODER_ID 0x04 +//#define ASIC_EXT_TV_ENCODER_ID 0x06 +//#define ASIC_INT_DVO_ENCODER_ID 0x07 +//#define ASIC_INT_DIG2_ENCODER_ID 0x09 +//#define ASIC_EXT_DIG_ENCODER_ID 0x05 + +//ucEncodeMode +//#define ATOM_ENCODER_MODE_DP 0 +//#define ATOM_ENCODER_MODE_LVDS 1 +//#define ATOM_ENCODER_MODE_DVI 2 +//#define ATOM_ENCODER_MODE_HDMI 3 +//#define ATOM_ENCODER_MODE_SDVO 4 +//#define ATOM_ENCODER_MODE_TV 13 +//#define ATOM_ENCODER_MODE_CV 14 +//#define ATOM_ENCODER_MODE_CRT 15 + + +typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3 +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO + UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO + UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR +}SELECT_CRTC_SOURCE_PARAMETERS_V3; + + +/****************************************************************************/ +// Structures used by SetPixelClockTable +// GetPixelClockTable +/****************************************************************************/ +//Major revision=1., Minor revision=1 +typedef struct _PIXEL_CLOCK_PARAMETERS +{ + USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) + // 0 means disable PPLL + USHORT usRefDiv; // Reference divider + USHORT usFbDiv; // feedback divider + UCHAR ucPostDiv; // post divider + UCHAR ucFracFbDiv; // fractional feedback divider + UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 + UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER + UCHAR ucCRTC; // Which CRTC uses this Ppll + UCHAR ucPadding; +}PIXEL_CLOCK_PARAMETERS; + +//Major revision=1., Minor revision=2, add ucMiscIfno +//ucMiscInfo: +#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 +#define MISC_DEVICE_INDEX_MASK 0xF0 +#define MISC_DEVICE_INDEX_SHIFT 4 + +typedef struct _PIXEL_CLOCK_PARAMETERS_V2 +{ + USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) + // 0 means disable PPLL + USHORT usRefDiv; // Reference divider + USHORT usFbDiv; // feedback divider + UCHAR ucPostDiv; // post divider + UCHAR ucFracFbDiv; // fractional feedback divider + UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 + UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER + UCHAR ucCRTC; // Which CRTC uses this Ppll + UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog +}PIXEL_CLOCK_PARAMETERS_V2; + +//Major revision=1., Minor revision=3, structure/definition change +//ucEncoderMode: +//ATOM_ENCODER_MODE_DP +//ATOM_ENOCDER_MODE_LVDS +//ATOM_ENOCDER_MODE_DVI +//ATOM_ENOCDER_MODE_HDMI +//ATOM_ENOCDER_MODE_SDVO +//ATOM_ENCODER_MODE_TV 13 +//ATOM_ENCODER_MODE_CV 14 +//ATOM_ENCODER_MODE_CRT 15 + +//ucDVOConfig +//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 +//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 +//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 +//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c +//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 +//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 +//#define DVO_ENCODER_CONFIG_24BIT 0x08 + +//ucMiscInfo: also changed, see below +#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 +#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 +#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 +#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 +#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 +#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 +#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 +// V1.4 for RoadRunner +#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 +#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 + + +typedef struct _PIXEL_CLOCK_PARAMETERS_V3 +{ + USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) + // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. + USHORT usRefDiv; // Reference divider + USHORT usFbDiv; // feedback divider + UCHAR ucPostDiv; // post divider + UCHAR ucFracFbDiv; // fractional feedback divider + UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 + UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h + union + { + UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ + UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit + }; + UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel + // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source + // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider +}PIXEL_CLOCK_PARAMETERS_V3; + +#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 +#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST + + +typedef struct _PIXEL_CLOCK_PARAMETERS_V5 +{ + UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to + // drive the pixel clock. not used for DCPLL case. + union{ + UCHAR ucReserved; + UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. + }; + USHORT usPixelClock; // target the pixel clock to drive the CRTC timing + // 0 means disable PPLL/DCPLL. + USHORT usFbDiv; // feedback divider integer part. + UCHAR ucPostDiv; // post divider. + UCHAR ucRefDiv; // Reference divider + UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL + UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, + // indicate which graphic encoder will be used. + UCHAR ucEncoderMode; // Encoder mode: + UCHAR ucMiscInfo; // bit[0]= Force program PPLL + // bit[1]= when VGA timing is used. + // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp + // bit[4]= RefClock source for PPLL. + // =0: XTLAIN( default mode ) + // =1: other external clock source, which is pre-defined + // by VBIOS depend on the feature required. + // bit[7:5]: reserved. + ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) + +}PIXEL_CLOCK_PARAMETERS_V5; + +#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 +#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 +#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c +#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 +#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 +#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 +#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 + +typedef struct _CRTC_PIXEL_CLOCK_FREQ +{ +#if ATOM_BIG_ENDIAN + ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to + // drive the pixel clock. not used for DCPLL case. + ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. + // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. +#else + ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. + // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. + ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to + // drive the pixel clock. not used for DCPLL case. +#endif +}CRTC_PIXEL_CLOCK_FREQ; + +typedef struct _PIXEL_CLOCK_PARAMETERS_V6 +{ + union{ + CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency + ULONG ulDispEngClkFreq; // dispclk frequency + }; + USHORT usFbDiv; // feedback divider integer part. + UCHAR ucPostDiv; // post divider. + UCHAR ucRefDiv; // Reference divider + UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL + UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, + // indicate which graphic encoder will be used. + UCHAR ucEncoderMode; // Encoder mode: + UCHAR ucMiscInfo; // bit[0]= Force program PPLL + // bit[1]= when VGA timing is used. + // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp + // bit[4]= RefClock source for PPLL. + // =0: XTLAIN( default mode ) + // =1: other external clock source, which is pre-defined + // by VBIOS depend on the feature required. + // bit[7:5]: reserved. + ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) + +}PIXEL_CLOCK_PARAMETERS_V6; + +#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 +#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 +#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c +#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 +#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 +#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) +#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 +#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) +#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c +#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 +#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 +#define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x40 + +typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 +{ + PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; +}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; + +typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 +{ + UCHAR ucStatus; + UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock + UCHAR ucReserved[2]; +}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; + +typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 +{ + PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; +}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; + + +/****************************************************************************/ +// Structures used by AdjustDisplayPllTable +/****************************************************************************/ +typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS +{ + USHORT usPixelClock; + UCHAR ucTransmitterID; + UCHAR ucEncodeMode; + union + { + UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit + UCHAR ucConfig; //if none DVO, not defined yet + }; + UCHAR ucReserved[3]; +}ADJUST_DISPLAY_PLL_PARAMETERS; + +#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 +#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS + +typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 +{ + USHORT usPixelClock; // target pixel clock + UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h + UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI + UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX + UCHAR ucExtTransmitterID; // external encoder id. + UCHAR ucReserved[2]; +}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; + +// usDispPllConfig v1.2 for RoadRunner +#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO +#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS +#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI +#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS + + +typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 +{ + ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc + UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) + UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider + UCHAR ucReserved[2]; +}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; + +typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 +{ + union + { + ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; + ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; + }; +} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; + +/****************************************************************************/ +// Structures used by EnableYUVTable +/****************************************************************************/ +typedef struct _ENABLE_YUV_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) + UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format + UCHAR ucPadding[2]; +}ENABLE_YUV_PARAMETERS; +#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS + +/****************************************************************************/ +// Structures used by GetMemoryClockTable +/****************************************************************************/ +typedef struct _GET_MEMORY_CLOCK_PARAMETERS +{ + ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit +} GET_MEMORY_CLOCK_PARAMETERS; +#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS + +/****************************************************************************/ +// Structures used by GetEngineClockTable +/****************************************************************************/ +typedef struct _GET_ENGINE_CLOCK_PARAMETERS +{ + ULONG ulReturnEngineClock; // current engine speed in 10KHz unit +} GET_ENGINE_CLOCK_PARAMETERS; +#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS + +/****************************************************************************/ +// Following Structures and constant may be obsolete +/****************************************************************************/ +//Maxium 8 bytes,the data read in will be placed in the parameter space. +//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed +typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS +{ + USHORT usPrescale; //Ratio between Engine clock and I2C clock + USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID + USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status + //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte + UCHAR ucSlaveAddr; //Read from which slave + UCHAR ucLineNumber; //Read from which HW assisted line +}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; +#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS + + +#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 +#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 +#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 +#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 +#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 + +typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS +{ + USHORT usPrescale; //Ratio between Engine clock and I2C clock + USHORT usByteOffset; //Write to which byte + //Upper portion of usByteOffset is Format of data + //1bytePS+offsetPS + //2bytesPS+offsetPS + //blockID+offsetPS + //blockID+offsetID + //blockID+counterID+offsetID + UCHAR ucData; //PS data1 + UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 + UCHAR ucSlaveAddr; //Write to which slave + UCHAR ucLineNumber; //Write from which HW assisted line +}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; + +#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS + +typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS +{ + USHORT usPrescale; //Ratio between Engine clock and I2C clock + UCHAR ucSlaveAddr; //Write to which slave + UCHAR ucLineNumber; //Write from which HW assisted line +}SET_UP_HW_I2C_DATA_PARAMETERS; + +/**************************************************************************/ +#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS + + +/****************************************************************************/ +// Structures used by PowerConnectorDetectionTable +/****************************************************************************/ +typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS +{ + UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected + UCHAR ucPwrBehaviorId; + USHORT usPwrBudget; //how much power currently boot to in unit of watt +}POWER_CONNECTOR_DETECTION_PARAMETERS; + +typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION +{ + UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected + UCHAR ucReserved; + USHORT usPwrBudget; //how much power currently boot to in unit of watt + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; + + +/****************************LVDS SS Command Table Definitions**********************/ + +/****************************************************************************/ +// Structures used by EnableSpreadSpectrumOnPPLLTable +/****************************************************************************/ +typedef struct _ENABLE_LVDS_SS_PARAMETERS +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD + UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY + UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[3]; +}ENABLE_LVDS_SS_PARAMETERS; + +//ucTableFormatRevision=1,ucTableContentRevision=2 +typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD + UCHAR ucSpreadSpectrumStep; // + UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE + UCHAR ucSpreadSpectrumDelay; + UCHAR ucSpreadSpectrumRange; + UCHAR ucPadding; +}ENABLE_LVDS_SS_PARAMETERS_V2; + +//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. +typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD + UCHAR ucSpreadSpectrumStep; // + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucSpreadSpectrumDelay; + UCHAR ucSpreadSpectrumRange; + UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 +}ENABLE_SPREAD_SPECTRUM_ON_PPLL; + + typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. + // Bit[1]: 1-Ext. 0-Int. + // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL + // Bits[7:4] reserved + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] + USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC +}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; + +#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 +#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 +#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 +#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c +#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 +#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 +#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 +#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF +#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 +#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 +#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 + +// Used by DCE5.0 + typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 +{ + USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 + UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. + // Bit[1]: 1-Ext. 0-Int. + // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL + // Bits[7:4] reserved + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] + USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC +}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; + + +#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 +#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 +#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 +#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c +#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 +#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 +#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 +#define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL +#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF +#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 +#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 +#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 + +#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL + +typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION +{ + PIXEL_CLOCK_PARAMETERS sPCLKInput; + ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion +}SET_PIXEL_CLOCK_PS_ALLOCATION; + + + +#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION + +/****************************************************************************/ +// Structures used by ### +/****************************************************************************/ +typedef struct _MEMORY_TRAINING_PARAMETERS +{ + ULONG ulTargetMemoryClock; //In 10Khz unit +}MEMORY_TRAINING_PARAMETERS; +#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS + + +typedef struct _MEMORY_TRAINING_PARAMETERS_V1_2 +{ + USHORT usMemTrainingMode; + USHORT usReserved; +}MEMORY_TRAINING_PARAMETERS_V1_2; + +//usMemTrainingMode +#define NORMAL_MEMORY_TRAINING_MODE 0 +#define ENTER_DRAM_SELFREFRESH_MODE 1 +#define EXIT_DRAM_SELFRESH_MODE 2 + +/****************************LVDS and other encoder command table definitions **********************/ + + +/****************************************************************************/ +// Structures used by LVDSEncoderControlTable (Before DEC30) +// LVTMAEncoderControlTable (Before DEC30) +// TMDSAEncoderControlTable (Before DEC30) +/****************************************************************************/ +typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucMisc; // bit0=0: Enable single link + // =1: Enable dual link + // Bit1=0: 666RGB + // =1: 888RGB + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder +}LVDS_ENCODER_CONTROL_PARAMETERS; + +#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS + +#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS +#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS + +#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS +#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS + +//ucTableFormatRevision=1,ucTableContentRevision=2 +typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder + UCHAR ucTruncate; // bit0=0: Disable truncate + // =1: Enable truncate + // bit4=0: 666RGB + // =1: 888RGB + UCHAR ucSpatial; // bit0=0: Disable spatial dithering + // =1: Enable spatial dithering + // bit4=0: 666RGB + // =1: 888RGB + UCHAR ucTemporal; // bit0=0: Disable temporal dithering + // =1: Enable temporal dithering + // bit4=0: 666RGB + // =1: 888RGB + // bit5=0: Gray level 2 + // =1: Gray level 4 + UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E + // =1: 25FRC_SEL pattern F + // bit6:5=0: 50FRC_SEL pattern A + // =1: 50FRC_SEL pattern B + // =2: 50FRC_SEL pattern C + // =3: 50FRC_SEL pattern D + // bit7=0: 75FRC_SEL pattern E + // =1: 75FRC_SEL pattern F +}LVDS_ENCODER_CONTROL_PARAMETERS_V2; + +#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 + +#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 +#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 + +#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 +#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 + + +#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 +#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 + +#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 + +#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 + +/****************************************************************************/ +// Structures used by ### +/****************************************************************************/ +typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS +{ + UCHAR ucEnable; // Enable or Disable External TMDS encoder + UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} + UCHAR ucPadding[2]; +}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; + +typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION +{ + ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion +}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; + +#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 +typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 +{ + ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion +}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; + +typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION +{ + DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; + +/****************************************************************************/ +// Structures used by DVOEncoderControlTable +/****************************************************************************/ +//ucTableFormatRevision=1,ucTableContentRevision=3 +//ucDVOConfig: +#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 +#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 +#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 +#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c +#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 +#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 +#define DVO_ENCODER_CONFIG_24BIT 0x08 + +typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 +{ + USHORT usPixelClock; + UCHAR ucDVOConfig; + UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT + UCHAR ucReseved[4]; +}DVO_ENCODER_CONTROL_PARAMETERS_V3; +#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 + +typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 +{ + USHORT usPixelClock; + UCHAR ucDVOConfig; + UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT + UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR + UCHAR ucReseved[3]; +}DVO_ENCODER_CONTROL_PARAMETERS_V1_4; +#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 + + +//ucTableFormatRevision=1 +//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for +// bit1=0: non-coherent mode +// =1: coherent mode + +//========================================================================================== +//Only change is here next time when changing encoder parameter definitions again! +#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST + +#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST + +#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST + +#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS +#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION + +//========================================================================================== +#define PANEL_ENCODER_MISC_DUAL 0x01 +#define PANEL_ENCODER_MISC_COHERENT 0x02 +#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 +#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 + +#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE +#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE +#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) + +#define PANEL_ENCODER_TRUNCATE_EN 0x01 +#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 +#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 +#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 +#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 +#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 +#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 +#define PANEL_ENCODER_25FRC_MASK 0x10 +#define PANEL_ENCODER_25FRC_E 0x00 +#define PANEL_ENCODER_25FRC_F 0x10 +#define PANEL_ENCODER_50FRC_MASK 0x60 +#define PANEL_ENCODER_50FRC_A 0x00 +#define PANEL_ENCODER_50FRC_B 0x20 +#define PANEL_ENCODER_50FRC_C 0x40 +#define PANEL_ENCODER_50FRC_D 0x60 +#define PANEL_ENCODER_75FRC_MASK 0x80 +#define PANEL_ENCODER_75FRC_E 0x00 +#define PANEL_ENCODER_75FRC_F 0x80 + +/****************************************************************************/ +// Structures used by SetVoltageTable +/****************************************************************************/ +#define SET_VOLTAGE_TYPE_ASIC_VDDC 1 +#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 +#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 +#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 +#define SET_VOLTAGE_INIT_MODE 5 +#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic + +#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 +#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 +#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 + +#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 +#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 +#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 + +typedef struct _SET_VOLTAGE_PARAMETERS +{ + UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ + UCHAR ucVoltageMode; // To set all, to set source A or source B or ... + UCHAR ucVoltageIndex; // An index to tell which voltage level + UCHAR ucReserved; +}SET_VOLTAGE_PARAMETERS; + +typedef struct _SET_VOLTAGE_PARAMETERS_V2 +{ + UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ + UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode + USHORT usVoltageLevel; // real voltage level +}SET_VOLTAGE_PARAMETERS_V2; + +// used by both SetVoltageTable v1.3 and v1.4 +typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 +{ + UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI + UCHAR ucVoltageMode; // Indicate action: Set voltage level + USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) +}SET_VOLTAGE_PARAMETERS_V1_3; + +//ucVoltageType +#define VOLTAGE_TYPE_VDDC 1 +#define VOLTAGE_TYPE_MVDDC 2 +#define VOLTAGE_TYPE_MVDDQ 3 +#define VOLTAGE_TYPE_VDDCI 4 +#define VOLTAGE_TYPE_VDDGFX 5 +#define VOLTAGE_TYPE_PCC 6 + +#define VOLTAGE_TYPE_GENERIC_I2C_1 0x11 +#define VOLTAGE_TYPE_GENERIC_I2C_2 0x12 +#define VOLTAGE_TYPE_GENERIC_I2C_3 0x13 +#define VOLTAGE_TYPE_GENERIC_I2C_4 0x14 +#define VOLTAGE_TYPE_GENERIC_I2C_5 0x15 +#define VOLTAGE_TYPE_GENERIC_I2C_6 0x16 +#define VOLTAGE_TYPE_GENERIC_I2C_7 0x17 +#define VOLTAGE_TYPE_GENERIC_I2C_8 0x18 +#define VOLTAGE_TYPE_GENERIC_I2C_9 0x19 +#define VOLTAGE_TYPE_GENERIC_I2C_10 0x1A + +//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode +#define ATOM_SET_VOLTAGE 0 //Set voltage Level +#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator +#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator +#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 +#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 +#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 + +// define vitual voltage id in usVoltageLevel +#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 +#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 +#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 +#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 +#define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05 +#define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06 +#define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07 +#define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08 + +typedef struct _SET_VOLTAGE_PS_ALLOCATION +{ + SET_VOLTAGE_PARAMETERS sASICSetVoltage; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +}SET_VOLTAGE_PS_ALLOCATION; + +// New Added from SI for GetVoltageInfoTable, input parameter structure +typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 +{ + UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI + UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info + USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id + ULONG ulReserved; +}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; + +// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID +typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 +{ + ULONG ulVotlageGpioState; + ULONG ulVoltageGPioMask; +}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; + +// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID +typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 +{ + USHORT usVoltageLevel; + USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator + ULONG ulReseved; +}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; + +// GetVoltageInfo v1.1 ucVoltageMode +#define ATOM_GET_VOLTAGE_VID 0x00 +#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 +#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 +#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info + +// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state +#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 +// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state +#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 + +#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 +#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 + + +// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure +typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 +{ + UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI + UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info + USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id + ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table +}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; + +// New in GetVoltageInfo v1.2 ucVoltageMode +#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 + +// New Added from CI Hawaii for EVV feature +typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 +{ + USHORT usVoltageLevel; // real voltage level in unit of mv + USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator + USHORT usTDP_Current; // TDP_Current in unit of 0.01A + USHORT usTDP_Power; // TDP_Current in unit of 0.1W +}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; + +/****************************************************************************/ +// Structures used by TVEncoderControlTable +/****************************************************************************/ +typedef struct _TV_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder +}TV_ENCODER_CONTROL_PARAMETERS; + +typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION +{ + TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one +}TV_ENCODER_CONTROL_PS_ALLOCATION; + +//==============================Data Table Portion==================================== + + +/****************************************************************************/ +// Structure used in Data.mtb +/****************************************************************************/ +typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES +{ + USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! + USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios + USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios + USHORT StandardVESA_Timing; // Only used by Bios + USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 + USHORT PaletteData; // Only used by BIOS + USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info + USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 + USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 + USHORT SupportedDevicesInfo; // Will be obsolete from R600 + USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 + USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 + USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 + USHORT VESA_ToInternalModeLUT; // Only used by Bios + USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 + USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 + USHORT GPUVirtualizationInfo; // Will be obsolete from R600 + USHORT SaveRestoreInfo; // Only used by Bios + USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info + USHORT OemInfo; // Defined and used by external SW, should be obsolete soon + USHORT XTMDS_Info; // Will be obsolete from R600 + USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used + USHORT Object_Header; // Shared by various SW components,latest version 1.1 + USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! + USHORT MC_InitParameter; // Only used by command table + USHORT ASIC_VDDC_Info; // Will be obsolete from R600 + USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" + USHORT TV_VideoMode; // Only used by command table + USHORT VRAM_Info; // Only used by command table, latest version 1.3 + USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 + USHORT IntegratedSystemInfo; // Shared by various SW components + USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 + USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 + USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 + USHORT ServiceInfo; +}ATOM_MASTER_LIST_OF_DATA_TABLES; + +typedef struct _ATOM_MASTER_DATA_TABLE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; +}ATOM_MASTER_DATA_TABLE; + +// For backward compatible +#define LVDS_Info LCD_Info +#define DAC_Info PaletteData +#define TMDS_Info DIGTransmitterInfo +#define CompassionateData GPUVirtualizationInfo + +/****************************************************************************/ +// Structure used in MultimediaCapabilityInfoTable +/****************************************************************************/ +typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulSignature; // HW info table signature string "$ATI" + UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) + UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) + UCHAR ucVideoPortInfo; // Provides the video port capabilities + UCHAR ucHostPortInfo; // Provides host port configuration information +}ATOM_MULTIMEDIA_CAPABILITY_INFO; + + +/****************************************************************************/ +// Structure used in MultimediaConfigInfoTable +/****************************************************************************/ +typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulSignature; // MM info table signature sting "$MMT" + UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) + UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) + UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting + UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) + UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) + UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) + UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) + UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) +}ATOM_MULTIMEDIA_CONFIG_INFO; + + +/****************************************************************************/ +// Structures used in FirmwareInfoTable +/****************************************************************************/ + +// usBIOSCapability Defintion: +// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; +// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; +// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; +// Others: Reserved +#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 +#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 +#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 +#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. +#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. +#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 +#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 +#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 +#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 +#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 +#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 +#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 +#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip +#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip + + +#ifndef _H2INC + +//Please don't add or expand this bitfield structure below, this one will retire soon.! +typedef struct _ATOM_FIRMWARE_CAPABILITY +{ +#if ATOM_BIG_ENDIAN + USHORT Reserved:1; + USHORT SCL2Redefined:1; + USHORT PostWithoutModeSet:1; + USHORT HyperMemory_Size:4; + USHORT HyperMemory_Support:1; + USHORT PPMode_Assigned:1; + USHORT WMI_SUPPORT:1; + USHORT GPUControlsBL:1; + USHORT EngineClockSS_Support:1; + USHORT MemoryClockSS_Support:1; + USHORT ExtendedDesktopSupport:1; + USHORT DualCRTC_Support:1; + USHORT FirmwarePosted:1; +#else + USHORT FirmwarePosted:1; + USHORT DualCRTC_Support:1; + USHORT ExtendedDesktopSupport:1; + USHORT MemoryClockSS_Support:1; + USHORT EngineClockSS_Support:1; + USHORT GPUControlsBL:1; + USHORT WMI_SUPPORT:1; + USHORT PPMode_Assigned:1; + USHORT HyperMemory_Support:1; + USHORT HyperMemory_Size:4; + USHORT PostWithoutModeSet:1; + USHORT SCL2Redefined:1; + USHORT Reserved:1; +#endif +}ATOM_FIRMWARE_CAPABILITY; + +typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS +{ + ATOM_FIRMWARE_CAPABILITY sbfAccess; + USHORT susAccess; +}ATOM_FIRMWARE_CAPABILITY_ACCESS; + +#else + +typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS +{ + USHORT susAccess; +}ATOM_FIRMWARE_CAPABILITY_ACCESS; + +#endif + +typedef struct _ATOM_FIRMWARE_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucPadding[3]; //Don't use them + ULONG aulReservedForBIOS[3]; //Don't use them + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO; + +typedef struct _ATOM_FIRMWARE_INFO_V1_2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + UCHAR ucPadding[2]; //Don't use them + ULONG aulReservedForBIOS[2]; //Don't use them + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO_V1_2; + +typedef struct _ATOM_FIRMWARE_INFO_V1_3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + UCHAR ucPadding[2]; //Don't use them + ULONG aulReservedForBIOS; //Don't use them + ULONG ul3DAccelerationEngineClock;//In 10Khz unit + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO_V1_3; + +typedef struct _ATOM_FIRMWARE_INFO_V1_4 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + USHORT usBootUpVDDCVoltage; //In MV unit + USHORT usLcdMinPixelClockPLL_Output; // In MHz unit + USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit + ULONG ul3DAccelerationEngineClock;//In 10Khz unit + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO_V1_4; + +//the structure below to be used from Cypress +typedef struct _ATOM_FIRMWARE_INFO_V2_1 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulReserved1; + ULONG ulReserved2; + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock + ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit + UCHAR ucReserved1; //Was ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + USHORT usBootUpVDDCVoltage; //In MV unit + USHORT usLcdMinPixelClockPLL_Output; // In MHz unit + USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit + ULONG ulReserved4; //Was ulAsicMaximumVoltage + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usCoreReferenceClock; //In 10Khz unit + USHORT usMemoryReferenceClock; //In 10Khz unit + USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock + UCHAR ucMemoryModule_ID; //Indicate what is the board design + UCHAR ucReserved4[3]; + +}ATOM_FIRMWARE_INFO_V2_1; + +//the structure below to be used from NI +//ucTableFormatRevision=2 +//ucTableContentRevision=2 + +typedef struct _PRODUCT_BRANDING +{ + UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level + UCHAR ucReserved:2; // Bit[3:2] Reserved + UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID +}PRODUCT_BRANDING; + +typedef struct _ATOM_FIRMWARE_INFO_V2_2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulSPLL_OutputFreq; //In 10Khz unit + ULONG ulGPUPLL_OutputFreq; //In 10Khz unit + ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* + ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? + ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. + UCHAR ucReserved3; //Was ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + USHORT usBootUpVDDCVoltage; //In MV unit + USHORT usLcdMinPixelClockPLL_Output; // In MHz unit + USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit + ULONG ulReserved4; //Was ulAsicMaximumVoltage + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + UCHAR ucRemoteDisplayConfig; + UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input + ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input + ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output + USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usCoreReferenceClock; //In 10Khz unit + USHORT usMemoryReferenceClock; //In 10Khz unit + USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock + UCHAR ucMemoryModule_ID; //Indicate what is the board design + UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION] + PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level. + UCHAR ucReserved9; + USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; + USHORT usBootUpVDDGFXVoltage; //In unit of mv; + ULONG ulReserved10[3]; // New added comparing to previous version +}ATOM_FIRMWARE_INFO_V2_2; + +#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 + + +// definition of ucRemoteDisplayConfig +#define REMOTE_DISPLAY_DISABLE 0x00 +#define REMOTE_DISPLAY_ENABLE 0x01 + +/****************************************************************************/ +// Structures used in IntegratedSystemInfoTable +/****************************************************************************/ +#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 +#define IGP_CAP_FLAG_AC_CARD 0x4 +#define IGP_CAP_FLAG_SDVO_CARD 0x8 +#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 + +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; //in 10kHz unit + ULONG ulBootUpMemoryClock; //in 10kHz unit + ULONG ulMaxSystemMemoryClock; //in 10kHz unit + ULONG ulMinSystemMemoryClock; //in 10kHz unit + UCHAR ucNumberOfCyclesInPeriodHi; + UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. + USHORT usReserved1; + USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage + USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage + ULONG ulReserved[2]; + + USHORT usFSBClock; //In MHz unit + USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable + //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card + //Bit[4]==1: P/2 mode, ==0: P/1 mode + USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal + USHORT usK8MemoryClock; //in MHz unit + USHORT usK8SyncStartDelay; //in 0.01 us unit + USHORT usK8DataReturnTime; //in 0.01 us unit + UCHAR ucMaxNBVoltage; + UCHAR ucMinNBVoltage; + UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved + UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod + UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime + UCHAR ucHTLinkWidth; //16 bit vs. 8 bit + UCHAR ucMaxNBVoltageHigh; + UCHAR ucMinNBVoltageHigh; +}ATOM_INTEGRATED_SYSTEM_INFO; + +/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO +ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock + For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock +ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 + For AMD IGP,for now this can be 0 +ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 + For AMD IGP,for now this can be 0 + +usFSBClock: For Intel IGP,it's FSB Freq + For AMD IGP,it's HT Link Speed + +usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 +usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation +usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation + +VC:Voltage Control +ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. +ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. + +ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. +ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 + +ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. +ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. + + +usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. +usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. +*/ + + +/* +The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; +Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. +The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. + +SW components can access the IGP system infor structure in the same way as before +*/ + + +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; //in 10kHz unit + ULONG ulReserved1[2]; //must be 0x0 for the reserved + ULONG ulBootUpUMAClock; //in 10kHz unit + ULONG ulBootUpSidePortClock; //in 10kHz unit + ULONG ulMinSidePortClock; //in 10kHz unit + ULONG ulReserved2[6]; //must be 0x0 for the reserved + ULONG ulSystemConfig; //see explanation below + ULONG ulBootUpReqDisplayVector; + ULONG ulOtherDisplayMisc; + ULONG ulDDISlot1Config; + ULONG ulDDISlot2Config; + UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved + UCHAR ucUMAChannelNumber; + UCHAR ucDockingPinBit; + UCHAR ucDockingPinPolarity; + ULONG ulDockingPinCFGInfo; + ULONG ulCPUCapInfo; + USHORT usNumberOfCyclesInPeriod; + USHORT usMaxNBVoltage; + USHORT usMinNBVoltage; + USHORT usBootUpNBVoltage; + ULONG ulHTLinkFreq; //in 10Khz + USHORT usMinHTLinkWidth; + USHORT usMaxHTLinkWidth; + USHORT usUMASyncStartDelay; + USHORT usUMADataReturnTime; + USHORT usLinkStatusZeroTime; + USHORT usDACEfuse; //for storing badgap value (for RS880 only) + ULONG ulHighVoltageHTLinkFreq; // in 10Khz + ULONG ulLowVoltageHTLinkFreq; // in 10Khz + USHORT usMaxUpStreamHTLinkWidth; + USHORT usMaxDownStreamHTLinkWidth; + USHORT usMinUpStreamHTLinkWidth; + USHORT usMinDownStreamHTLinkWidth; + USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. + USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. + ULONG ulReserved3[96]; //must be 0x0 +}ATOM_INTEGRATED_SYSTEM_INFO_V2; + +/* +ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; +ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present +ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock + +ulSystemConfig: +Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; +Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state + =0: system boots up at driver control state. Power state depends on PowerPlay table. +Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. +Bit[3]=1: Only one power state(Performance) will be supported. + =0: Multiple power states supported from PowerPlay table. +Bit[4]=1: CLMC is supported and enabled on current system. + =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. +Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. + =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. +Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. + =0: Voltage settings is determined by powerplay table. +Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. + =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. +Bit[8]=1: CDLF is supported and enabled on current system. + =0: CDLF is not supported or enabled on current system. +Bit[9]=1: DLL Shut Down feature is enabled on current system. + =0: DLL Shut Down feature is not enabled or supported on current system. + +ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. + +ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; + [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; + +ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). + [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) + [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) + When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. + in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: + one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. + + [15:8] - Lane configuration attribute; + [23:16]- Connector type, possible value: + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D + CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D + CONNECTOR_OBJECT_ID_HDMI_TYPE_A + CONNECTOR_OBJECT_ID_DISPLAYPORT + CONNECTOR_OBJECT_ID_eDP + [31:24]- Reserved + +ulDDISlot2Config: Same as Slot1. +ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. +For IGP, Hypermemory is the only memory type showed in CCC. + +ucUMAChannelNumber: how many channels for the UMA; + +ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin +ucDockingPinBit: which bit in this register to read the pin status; +ucDockingPinPolarity:Polarity of the pin when docked; + +ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 + +usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. + +usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. +usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. + GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 + PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 + GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE + +usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. + + +ulHTLinkFreq: Bootup HT link Frequency in 10Khz. +usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. + If CDLW enabled, both upstream and downstream width should be the same during bootup. +usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. + If CDLW enabled, both upstream and downstream width should be the same during bootup. + +usUMASyncStartDelay: Memory access latency, required for watermark calculation +usUMADataReturnTime: Memory access latency, required for watermark calculation +usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us +for Griffin or Greyhound. SBIOS needs to convert to actual time by: + if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) + if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) + if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) + if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) + +ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. + This must be less than or equal to ulHTLinkFreq(bootup frequency). +ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. + This must be less than or equal to ulHighVoltageHTLinkFreq. + +usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. +usMaxDownStreamHTLinkWidth: same as above. +usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. +usMinDownStreamHTLinkWidth: same as above. +*/ + +// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition +#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 +#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 +#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 +#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 +#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 +#define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 + +#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code + +#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 +#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 +#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 +#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 +#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 +#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 +#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 +#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 +#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 +#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 + +#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF + +#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F +#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 +#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 +#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 +#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 +#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 + +#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 +#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 +#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 + +#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 + +// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; //in 10kHz unit + ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. + ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge + ULONG ulBootUpUMAClock; //in 10kHz unit + ULONG ulReserved1[8]; //must be 0x0 for the reserved + ULONG ulBootUpReqDisplayVector; + ULONG ulOtherDisplayMisc; + ULONG ulReserved2[4]; //must be 0x0 for the reserved + ULONG ulSystemConfig; //TBD + ULONG ulCPUCapInfo; //TBD + USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; + USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; + USHORT usBootUpNBVoltage; //boot up NB voltage + UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD + UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD + ULONG ulReserved3[4]; //must be 0x0 for the reserved + ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition + ULONG ulDDISlot2Config; + ULONG ulDDISlot3Config; + ULONG ulDDISlot4Config; + ULONG ulReserved4[4]; //must be 0x0 for the reserved + UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved + UCHAR ucUMAChannelNumber; + USHORT usReserved; + ULONG ulReserved5[4]; //must be 0x0 for the reserved + ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default + ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback + ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications + ULONG ulReserved6[61]; //must be 0x0 +}ATOM_INTEGRATED_SYSTEM_INFO_V5; + + + +/****************************************************************************/ +// Structure used in GPUVirtualizationInfoTable +/****************************************************************************/ +typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_1 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulMCUcodeRomStartAddr; + ULONG ulMCUcodeLength; + ULONG ulSMCUcodeRomStartAddr; + ULONG ulSMCUcodeLength; + ULONG ulRLCVUcodeRomStartAddr; + ULONG ulRLCVUcodeLength; + ULONG ulTOCUcodeStartAddr; + ULONG ulTOCUcodeLength; + ULONG ulSMCPatchTableStartAddr; + ULONG ulSmcPatchTableLength; + ULONG ulSystemFlag; +}ATOM_GPU_VIRTUALIZATION_INFO_V2_1; + + +#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 +#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 +#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 +#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 +#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 +#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 +#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 +#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 +#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 +#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 +#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A +#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B +#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C +#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D + +// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable +#define ASIC_INT_DAC1_ENCODER_ID 0x00 +#define ASIC_INT_TV_ENCODER_ID 0x02 +#define ASIC_INT_DIG1_ENCODER_ID 0x03 +#define ASIC_INT_DAC2_ENCODER_ID 0x04 +#define ASIC_EXT_TV_ENCODER_ID 0x06 +#define ASIC_INT_DVO_ENCODER_ID 0x07 +#define ASIC_INT_DIG2_ENCODER_ID 0x09 +#define ASIC_EXT_DIG_ENCODER_ID 0x05 +#define ASIC_EXT_DIG2_ENCODER_ID 0x08 +#define ASIC_INT_DIG3_ENCODER_ID 0x0a +#define ASIC_INT_DIG4_ENCODER_ID 0x0b +#define ASIC_INT_DIG5_ENCODER_ID 0x0c +#define ASIC_INT_DIG6_ENCODER_ID 0x0d +#define ASIC_INT_DIG7_ENCODER_ID 0x0e + +//define Encoder attribute +#define ATOM_ANALOG_ENCODER 0 +#define ATOM_DIGITAL_ENCODER 1 +#define ATOM_DP_ENCODER 2 + +#define ATOM_ENCODER_ENUM_MASK 0x70 +#define ATOM_ENCODER_ENUM_ID1 0x00 +#define ATOM_ENCODER_ENUM_ID2 0x10 +#define ATOM_ENCODER_ENUM_ID3 0x20 +#define ATOM_ENCODER_ENUM_ID4 0x30 +#define ATOM_ENCODER_ENUM_ID5 0x40 +#define ATOM_ENCODER_ENUM_ID6 0x50 + +#define ATOM_DEVICE_CRT1_INDEX 0x00000000 +#define ATOM_DEVICE_LCD1_INDEX 0x00000001 +#define ATOM_DEVICE_TV1_INDEX 0x00000002 +#define ATOM_DEVICE_DFP1_INDEX 0x00000003 +#define ATOM_DEVICE_CRT2_INDEX 0x00000004 +#define ATOM_DEVICE_LCD2_INDEX 0x00000005 +#define ATOM_DEVICE_DFP6_INDEX 0x00000006 +#define ATOM_DEVICE_DFP2_INDEX 0x00000007 +#define ATOM_DEVICE_CV_INDEX 0x00000008 +#define ATOM_DEVICE_DFP3_INDEX 0x00000009 +#define ATOM_DEVICE_DFP4_INDEX 0x0000000A +#define ATOM_DEVICE_DFP5_INDEX 0x0000000B + +#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C +#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D +#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E +#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F +#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) +#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO +#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) + +#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) + +#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) +#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) +#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) +#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) +#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) +#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) +#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) +#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) +#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) +#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) +#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) +#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) + + +#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) +#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) +#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT +#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) + +#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 +#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 +#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 +#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 +#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 +#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 +#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 +#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 +#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 +#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 +#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 +#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A +#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B +#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E +#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F + + +#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F +#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 +#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 +#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 +#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 +#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 + +#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 + +#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F +#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 + +#define ATOM_DEVICE_I2C_ID_MASK 0x00000070 +#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 +#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 +#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 +#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 +#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 + +#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 +#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 +#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 +#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 + +// usDeviceSupport: +// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported +// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported +// Bit 2 = 0 - no TV1 support= 1- TV1 is supported +// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported +// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported +// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported +// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported +// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported +// Bit 8 = 0 - no CV support= 1- CV is supported +// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported +// Bit 10= 0 - no DFP4 support= 1- DFP4 is supported +// Bit 11= 0 - no DFP5 support= 1- DFP5 is supported +// +// + +/****************************************************************************/ +// Structure used in MclkSS_InfoTable +/****************************************************************************/ +// ucI2C_ConfigID +// [7:0] - I2C LINE Associate ID +// = 0 - no I2C +// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) +// = 0, [6:0]=SW assisted I2C ID +// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use +// = 2, HW engine for Multimedia use +// = 3-7 Reserved for future I2C engines +// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C + +typedef struct _ATOM_I2C_ID_CONFIG +{ +#if ATOM_BIG_ENDIAN + UCHAR bfHW_Capable:1; + UCHAR bfHW_EngineID:3; + UCHAR bfI2C_LineMux:4; +#else + UCHAR bfI2C_LineMux:4; + UCHAR bfHW_EngineID:3; + UCHAR bfHW_Capable:1; +#endif +}ATOM_I2C_ID_CONFIG; + +typedef union _ATOM_I2C_ID_CONFIG_ACCESS +{ + ATOM_I2C_ID_CONFIG sbfAccess; + UCHAR ucAccess; +}ATOM_I2C_ID_CONFIG_ACCESS; + + +/****************************************************************************/ +// Structure used in GPIO_I2C_InfoTable +/****************************************************************************/ +typedef struct _ATOM_GPIO_I2C_ASSIGMENT +{ + USHORT usClkMaskRegisterIndex; + USHORT usClkEnRegisterIndex; + USHORT usClkY_RegisterIndex; + USHORT usClkA_RegisterIndex; + USHORT usDataMaskRegisterIndex; + USHORT usDataEnRegisterIndex; + USHORT usDataY_RegisterIndex; + USHORT usDataA_RegisterIndex; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; + UCHAR ucClkMaskShift; + UCHAR ucClkEnShift; + UCHAR ucClkY_Shift; + UCHAR ucClkA_Shift; + UCHAR ucDataMaskShift; + UCHAR ucDataEnShift; + UCHAR ucDataY_Shift; + UCHAR ucDataA_Shift; + UCHAR ucReserved1; + UCHAR ucReserved2; +}ATOM_GPIO_I2C_ASSIGMENT; + +typedef struct _ATOM_GPIO_I2C_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; +}ATOM_GPIO_I2C_INFO; + +/****************************************************************************/ +// Common Structure used in other structures +/****************************************************************************/ + +#ifndef _H2INC + +//Please don't add or expand this bitfield structure below, this one will retire soon.! +typedef struct _ATOM_MODE_MISC_INFO +{ +#if ATOM_BIG_ENDIAN + USHORT Reserved:6; + USHORT RGB888:1; + USHORT DoubleClock:1; + USHORT Interlace:1; + USHORT CompositeSync:1; + USHORT V_ReplicationBy2:1; + USHORT H_ReplicationBy2:1; + USHORT VerticalCutOff:1; + USHORT VSyncPolarity:1; //0=Active High, 1=Active Low + USHORT HSyncPolarity:1; //0=Active High, 1=Active Low + USHORT HorizontalCutOff:1; +#else + USHORT HorizontalCutOff:1; + USHORT HSyncPolarity:1; //0=Active High, 1=Active Low + USHORT VSyncPolarity:1; //0=Active High, 1=Active Low + USHORT VerticalCutOff:1; + USHORT H_ReplicationBy2:1; + USHORT V_ReplicationBy2:1; + USHORT CompositeSync:1; + USHORT Interlace:1; + USHORT DoubleClock:1; + USHORT RGB888:1; + USHORT Reserved:6; +#endif +}ATOM_MODE_MISC_INFO; + +typedef union _ATOM_MODE_MISC_INFO_ACCESS +{ + ATOM_MODE_MISC_INFO sbfAccess; + USHORT usAccess; +}ATOM_MODE_MISC_INFO_ACCESS; + +#else + +typedef union _ATOM_MODE_MISC_INFO_ACCESS +{ + USHORT usAccess; +}ATOM_MODE_MISC_INFO_ACCESS; + +#endif + +// usModeMiscInfo- +#define ATOM_H_CUTOFF 0x01 +#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low +#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low +#define ATOM_V_CUTOFF 0x08 +#define ATOM_H_REPLICATIONBY2 0x10 +#define ATOM_V_REPLICATIONBY2 0x20 +#define ATOM_COMPOSITESYNC 0x40 +#define ATOM_INTERLACE 0x80 +#define ATOM_DOUBLE_CLOCK_MODE 0x100 +#define ATOM_RGB888_MODE 0x200 + +//usRefreshRate- +#define ATOM_REFRESH_43 43 +#define ATOM_REFRESH_47 47 +#define ATOM_REFRESH_56 56 +#define ATOM_REFRESH_60 60 +#define ATOM_REFRESH_65 65 +#define ATOM_REFRESH_70 70 +#define ATOM_REFRESH_72 72 +#define ATOM_REFRESH_75 75 +#define ATOM_REFRESH_85 85 + +// ATOM_MODE_TIMING data are exactly the same as VESA timing data. +// Translation from EDID to ATOM_MODE_TIMING, use the following formula. +// +// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK +// = EDID_HA + EDID_HBL +// VESA_HDISP = VESA_ACTIVE = EDID_HA +// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH +// = EDID_HA + EDID_HSO +// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW +// VESA_BORDER = EDID_BORDER + + +/****************************************************************************/ +// Structure used in SetCRTC_UsingDTDTimingTable +/****************************************************************************/ +typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS +{ + USHORT usH_Size; + USHORT usH_Blanking_Time; + USHORT usV_Size; + USHORT usV_Blanking_Time; + USHORT usH_SyncOffset; + USHORT usH_SyncWidth; + USHORT usV_SyncOffset; + USHORT usV_SyncWidth; + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + UCHAR ucH_Border; // From DFP EDID + UCHAR ucV_Border; + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucPadding[3]; +}SET_CRTC_USING_DTD_TIMING_PARAMETERS; + +/****************************************************************************/ +// Structure used in SetCRTC_TimingTable +/****************************************************************************/ +typedef struct _SET_CRTC_TIMING_PARAMETERS +{ + USHORT usH_Total; // horizontal total + USHORT usH_Disp; // horizontal display + USHORT usH_SyncStart; // horozontal Sync start + USHORT usH_SyncWidth; // horizontal Sync width + USHORT usV_Total; // vertical total + USHORT usV_Disp; // vertical display + USHORT usV_SyncStart; // vertical Sync start + USHORT usV_SyncWidth; // vertical Sync width + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucOverscanRight; // right + UCHAR ucOverscanLeft; // left + UCHAR ucOverscanBottom; // bottom + UCHAR ucOverscanTop; // top + UCHAR ucReserved; +}SET_CRTC_TIMING_PARAMETERS; +#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS + + +/****************************************************************************/ +// Structure used in StandardVESA_TimingTable +// AnalogTV_InfoTable +// ComponentVideoInfoTable +/****************************************************************************/ +typedef struct _ATOM_MODE_TIMING +{ + USHORT usCRTC_H_Total; + USHORT usCRTC_H_Disp; + USHORT usCRTC_H_SyncStart; + USHORT usCRTC_H_SyncWidth; + USHORT usCRTC_V_Total; + USHORT usCRTC_V_Disp; + USHORT usCRTC_V_SyncStart; + USHORT usCRTC_V_SyncWidth; + USHORT usPixelClock; //in 10Khz unit + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + USHORT usCRTC_OverscanRight; + USHORT usCRTC_OverscanLeft; + USHORT usCRTC_OverscanBottom; + USHORT usCRTC_OverscanTop; + USHORT usReserve; + UCHAR ucInternalModeNumber; + UCHAR ucRefreshRate; +}ATOM_MODE_TIMING; + +typedef struct _ATOM_DTD_FORMAT +{ + USHORT usPixClk; + USHORT usHActive; + USHORT usHBlanking_Time; + USHORT usVActive; + USHORT usVBlanking_Time; + USHORT usHSyncOffset; + USHORT usHSyncWidth; + USHORT usVSyncOffset; + USHORT usVSyncWidth; + USHORT usImageHSize; + USHORT usImageVSize; + UCHAR ucHBorder; + UCHAR ucVBorder; + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + UCHAR ucInternalModeNumber; + UCHAR ucRefreshRate; +}ATOM_DTD_FORMAT; + +/****************************************************************************/ +// Structure used in LVDS_InfoTable +// * Need a document to describe this table +/****************************************************************************/ +#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 +#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 +#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 +#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 +#define SUPPORTED_LCD_REFRESHRATE_48Hz 0x0040 + +//ucTableFormatRevision=1 +//ucTableContentRevision=1 +typedef struct _ATOM_LVDS_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_DTD_FORMAT sLCDTiming; + USHORT usModePatchTableOffset; + USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. + USHORT usOffDelayInMs; + UCHAR ucPowerSequenceDigOntoDEin10Ms; + UCHAR ucPowerSequenceDEtoBLOnin10Ms; + UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} + // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} + // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} + // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} + UCHAR ucPanelDefaultRefreshRate; + UCHAR ucPanelIdentification; + UCHAR ucSS_Id; +}ATOM_LVDS_INFO; + +//ucTableFormatRevision=1 +//ucTableContentRevision=2 +typedef struct _ATOM_LVDS_INFO_V12 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_DTD_FORMAT sLCDTiming; + USHORT usExtInfoTableOffset; + USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. + USHORT usOffDelayInMs; + UCHAR ucPowerSequenceDigOntoDEin10Ms; + UCHAR ucPowerSequenceDEtoBLOnin10Ms; + UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} + // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} + // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} + // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} + UCHAR ucPanelDefaultRefreshRate; + UCHAR ucPanelIdentification; + UCHAR ucSS_Id; + USHORT usLCDVenderID; + USHORT usLCDProductID; + UCHAR ucLCDPanel_SpecialHandlingCap; + UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable + UCHAR ucReserved[2]; +}ATOM_LVDS_INFO_V12; + +//Definitions for ucLCDPanel_SpecialHandlingCap: + +//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. +//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL +#define LCDPANEL_CAP_READ_EDID 0x1 + +//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together +//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static +//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 +#define LCDPANEL_CAP_DRR_SUPPORTED 0x2 + +//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. +#define LCDPANEL_CAP_eDP 0x4 + + +//Color Bit Depth definition in EDID V1.4 @BYTE 14h +//Bit 6 5 4 + // 0 0 0 - Color bit depth is undefined + // 0 0 1 - 6 Bits per Primary Color + // 0 1 0 - 8 Bits per Primary Color + // 0 1 1 - 10 Bits per Primary Color + // 1 0 0 - 12 Bits per Primary Color + // 1 0 1 - 14 Bits per Primary Color + // 1 1 0 - 16 Bits per Primary Color + // 1 1 1 - Reserved + +#define PANEL_COLOR_BIT_DEPTH_MASK 0x70 + +// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} +#define PANEL_RANDOM_DITHER 0x80 +#define PANEL_RANDOM_DITHER_MASK 0x80 + +#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this + + +typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT +{ + UCHAR ucSupportedRefreshRate; + UCHAR ucMinRefreshRateForDRR; +}ATOM_LCD_REFRESH_RATE_SUPPORT; + +/****************************************************************************/ +// Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 +// ASIC Families: NI +// ucTableFormatRevision=1 +// ucTableContentRevision=3 +/****************************************************************************/ +typedef struct _ATOM_LCD_INFO_V13 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_DTD_FORMAT sLCDTiming; + USHORT usExtInfoTableOffset; + union + { + USHORT usSupportedRefreshRate; + ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport; + }; + ULONG ulReserved0; + UCHAR ucLCD_Misc; // Reorganized in V13 + // Bit0: {=0:single, =1:dual}, + // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, + // Bit3:2: {Grey level} + // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) + // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? + UCHAR ucPanelDefaultRefreshRate; + UCHAR ucPanelIdentification; + UCHAR ucSS_Id; + USHORT usLCDVenderID; + USHORT usLCDProductID; + UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 + // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own + // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED + // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) + // Bit7-3: Reserved + UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable + USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 + + UCHAR ucPowerSequenceDIGONtoDE_in4Ms; + UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; + UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; + UCHAR ucPowerSequenceDEtoDIGON_in4Ms; + + UCHAR ucOffDelay_in4Ms; + UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; + UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; + UCHAR ucReserved1; + + UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh + UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h + UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h + UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h + + USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. + UCHAR uceDPToLVDSRxId; + UCHAR ucLcdReservd; + ULONG ulReserved[2]; +}ATOM_LCD_INFO_V13; + +#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 + +//Definitions for ucLCD_Misc +#define ATOM_PANEL_MISC_V13_DUAL 0x00000001 +#define ATOM_PANEL_MISC_V13_FPDI 0x00000002 +#define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C +#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 +#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 +#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 +#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 + +//Color Bit Depth definition in EDID V1.4 @BYTE 14h +//Bit 6 5 4 + // 0 0 0 - Color bit depth is undefined + // 0 0 1 - 6 Bits per Primary Color + // 0 1 0 - 8 Bits per Primary Color + // 0 1 1 - 10 Bits per Primary Color + // 1 0 0 - 12 Bits per Primary Color + // 1 0 1 - 14 Bits per Primary Color + // 1 1 0 - 16 Bits per Primary Color + // 1 1 1 - Reserved + +//Definitions for ucLCDPanel_SpecialHandlingCap: + +//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. +//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL +#define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version + +//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together +//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static +//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 +#define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version + +//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. +#define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version + +//uceDPToLVDSRxId +#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip +#define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init +#define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init + +typedef struct _ATOM_PATCH_RECORD_MODE +{ + UCHAR ucRecordType; + USHORT usHDisp; + USHORT usVDisp; +}ATOM_PATCH_RECORD_MODE; + +typedef struct _ATOM_LCD_RTS_RECORD +{ + UCHAR ucRecordType; + UCHAR ucRTSValue; +}ATOM_LCD_RTS_RECORD; + +//!! If the record below exits, it shoud always be the first record for easy use in command table!!! +// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. +typedef struct _ATOM_LCD_MODE_CONTROL_CAP +{ + UCHAR ucRecordType; + USHORT usLCDCap; +}ATOM_LCD_MODE_CONTROL_CAP; + +#define LCD_MODE_CAP_BL_OFF 1 +#define LCD_MODE_CAP_CRTC_OFF 2 +#define LCD_MODE_CAP_PANEL_OFF 4 + + +typedef struct _ATOM_FAKE_EDID_PATCH_RECORD +{ + UCHAR ucRecordType; + UCHAR ucFakeEDIDLength; // = 128 means EDID lenght is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128 + UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. +} ATOM_FAKE_EDID_PATCH_RECORD; + +typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD +{ + UCHAR ucRecordType; + USHORT usHSize; + USHORT usVSize; +}ATOM_PANEL_RESOLUTION_PATCH_RECORD; + +#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 +#define LCD_RTS_RECORD_TYPE 2 +#define LCD_CAP_RECORD_TYPE 3 +#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 +#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 +#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 +#define ATOM_RECORD_END_TYPE 0xFF + +/****************************Spread Spectrum Info Table Definitions **********************/ + +//ucTableFormatRevision=1 +//ucTableContentRevision=2 +typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD + UCHAR ucSS_Step; + UCHAR ucSS_Delay; + UCHAR ucSS_Id; + UCHAR ucRecommendedRef_Div; + UCHAR ucSS_Range; //it was reserved for V11 +}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; + +#define ATOM_MAX_SS_ENTRY 16 +#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. +#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. +#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz +#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz + + + +#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 +#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 +#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 +#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 +#define ATOM_INTERNAL_SS_MASK 0x00000000 +#define ATOM_EXTERNAL_SS_MASK 0x00000002 +#define EXEC_SS_STEP_SIZE_SHIFT 2 +#define EXEC_SS_DELAY_SHIFT 4 +#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 + +typedef struct _ATOM_SPREAD_SPECTRUM_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; +}ATOM_SPREAD_SPECTRUM_INFO; + + +/****************************************************************************/ +// Structure used in AnalogTV_InfoTable (Top level) +/****************************************************************************/ +//ucTVBootUpDefaultStd definiton: + +//ATOM_TV_NTSC 1 +//ATOM_TV_NTSCJ 2 +//ATOM_TV_PAL 3 +//ATOM_TV_PALM 4 +//ATOM_TV_PALCN 5 +//ATOM_TV_PALN 6 +//ATOM_TV_PAL60 7 +//ATOM_TV_SECAM 8 + +//ucTVSuppportedStd definition: +#define NTSC_SUPPORT 0x1 +#define NTSCJ_SUPPORT 0x2 + +#define PAL_SUPPORT 0x4 +#define PALM_SUPPORT 0x8 +#define PALCN_SUPPORT 0x10 +#define PALN_SUPPORT 0x20 +#define PAL60_SUPPORT 0x40 +#define SECAM_SUPPORT 0x80 + +#define MAX_SUPPORTED_TV_TIMING 2 + +typedef struct _ATOM_ANALOG_TV_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucTV_SuppportedStandard; + UCHAR ucTV_BootUpDefaultStandard; + UCHAR ucExt_TV_ASIC_ID; + UCHAR ucExt_TV_ASIC_SlaveAddr; + ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; +}ATOM_ANALOG_TV_INFO; + +typedef struct _ATOM_DPCD_INFO +{ + UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 + UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane + UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP + UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) +}ATOM_DPCD_INFO; + +#define ATOM_DPCD_MAX_LANE_MASK 0x1F + +/**************************************************************************/ +// VRAM usage and their defintions + +// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. +// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. +// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! +// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR +// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX + +// Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU). +//#ifndef VESA_MEMORY_IN_64K_BLOCK +//#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) +//#endif + +#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes +#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes +#define ATOM_HWICON_INFOTABLE_SIZE 32 +#define MAX_DTD_MODE_IN_VRAM 6 +#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) +#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) +//20 bytes for Encoder Type and DPCD in STD EDID area +#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) +#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) + +#define ATOM_HWICON1_SURFACE_ADDR 0 +#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) +#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) +#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) +#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) +#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 + +//The size below is in Kb! +#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) + +#define ATOM_VRAM_RESERVE_V2_SIZE 32 + +#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L +#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 +#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 +#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 + +/***********************************************************************************/ +// Structure used in VRAM_UsageByFirmwareTable +// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm +// at running time. +// note2: From RV770, the memory is more than 32bit addressable, so we will change +// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains +// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware +// (in offset to start of memory address) is KB aligned instead of byte aligend. +// Note3: +/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged +constant across VGA or non VGA adapter, +for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: + +If (ulStartAddrUsedByFirmware!=0) +FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; +Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose +else //Non VGA case + if (FB_Size<=2Gb) + FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; + else + FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB + +CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ + +/***********************************************************************************/ +#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 + +typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO +{ + ULONG ulStartAddrUsedByFirmware; + USHORT usFirmwareUseInKb; + USHORT usReserved; +}ATOM_FIRMWARE_VRAM_RESERVE_INFO; + +typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; +}ATOM_VRAM_USAGE_BY_FIRMWARE; + +// change verion to 1.5, when allow driver to allocate the vram area for command table access. +typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 +{ + ULONG ulStartAddrUsedByFirmware; + USHORT usFirmwareUseInKb; + USHORT usFBUsedByDrvInKb; +}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; + +typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; +}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; + +/****************************************************************************/ +// Structure used in GPIO_Pin_LUTTable +/****************************************************************************/ +typedef struct _ATOM_GPIO_PIN_ASSIGNMENT +{ + USHORT usGpioPin_AIndex; + UCHAR ucGpioPinBitShift; + UCHAR ucGPIO_ID; +}ATOM_GPIO_PIN_ASSIGNMENT; + +//ucGPIO_ID pre-define id for multiple usage +// GPIO use to control PCIE_VDDC in certain SLT board +#define PCIE_VDDC_CONTROL_GPIO_PINID 56 + +//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC swithing feature is enable +#define PP_AC_DC_SWITCH_GPIO_PINID 60 +//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable +#define VDDC_VRHOT_GPIO_PINID 61 +//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled +#define VDDC_PCC_GPIO_PINID 62 +// Only used on certain SLT/PA board to allow utility to cut Efuse. +#define EFUSE_CUT_ENABLE_GPIO_PINID 63 +// ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= +#define DRAM_SELF_REFRESH_GPIO_PINID 64 +// Thermal interrupt output->system thermal chip GPIO pin +#define THERMAL_INT_OUTPUT_GPIO_PINID 65 + + +typedef struct _ATOM_GPIO_PIN_LUT +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; +}ATOM_GPIO_PIN_LUT; + +/****************************************************************************/ +// Structure used in ComponentVideoInfoTable +/****************************************************************************/ +#define GPIO_PIN_ACTIVE_HIGH 0x1 +#define MAX_SUPPORTED_CV_STANDARDS 5 + +// definitions for ATOM_D_INFO.ucSettings +#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] +#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out +#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] + +typedef struct _ATOM_GPIO_INFO +{ + USHORT usAOffset; + UCHAR ucSettings; + UCHAR ucReserved; +}ATOM_GPIO_INFO; + +// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) +#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 + +// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i +#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; +#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] + +// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode +//Line 3 out put 5V. +#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 +#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 +#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 + +//Line 3 out put 2.2V +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 + +//Line 3 out put 0V +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 + +#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] + +#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 + +//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. +#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. +#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. + + +typedef struct _ATOM_COMPONENT_VIDEO_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMask_PinRegisterIndex; + USHORT usEN_PinRegisterIndex; + USHORT usY_PinRegisterIndex; + USHORT usA_PinRegisterIndex; + UCHAR ucBitShift; + UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low + ATOM_DTD_FORMAT sReserved; // must be zeroed out + UCHAR ucMiscInfo; + UCHAR uc480i; + UCHAR uc480p; + UCHAR uc720p; + UCHAR uc1080i; + UCHAR ucLetterBoxMode; + UCHAR ucReserved[3]; + UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector + ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; + ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; +}ATOM_COMPONENT_VIDEO_INFO; + +//ucTableFormatRevision=2 +//ucTableContentRevision=1 +typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucMiscInfo; + UCHAR uc480i; + UCHAR uc480p; + UCHAR uc720p; + UCHAR uc1080i; + UCHAR ucReserved; + UCHAR ucLetterBoxMode; + UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector + ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; + ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; +}ATOM_COMPONENT_VIDEO_INFO_V21; + +#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 + +/****************************************************************************/ +// Structure used in object_InfoTable +/****************************************************************************/ +typedef struct _ATOM_OBJECT_HEADER +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + USHORT usConnectorObjectTableOffset; + USHORT usRouterObjectTableOffset; + USHORT usEncoderObjectTableOffset; + USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. + USHORT usDisplayPathTableOffset; +}ATOM_OBJECT_HEADER; + +typedef struct _ATOM_OBJECT_HEADER_V3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + USHORT usConnectorObjectTableOffset; + USHORT usRouterObjectTableOffset; + USHORT usEncoderObjectTableOffset; + USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. + USHORT usDisplayPathTableOffset; + USHORT usMiscObjectTableOffset; +}ATOM_OBJECT_HEADER_V3; + + +typedef struct _ATOM_DISPLAY_OBJECT_PATH +{ + USHORT usDeviceTag; //supported device + USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH + USHORT usConnObjectId; //Connector Object ID + USHORT usGPUObjectId; //GPU ID + USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. +}ATOM_DISPLAY_OBJECT_PATH; + +typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH +{ + USHORT usDeviceTag; //supported device + USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH + USHORT usConnObjectId; //Connector Object ID + USHORT usGPUObjectId; //GPU ID + USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder +}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; + +typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE +{ + UCHAR ucNumOfDispPath; + UCHAR ucVersion; + UCHAR ucPadding[2]; + ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; +}ATOM_DISPLAY_OBJECT_PATH_TABLE; + +typedef struct _ATOM_OBJECT //each object has this structure +{ + USHORT usObjectID; + USHORT usSrcDstTableOffset; + USHORT usRecordOffset; //this pointing to a bunch of records defined below + USHORT usReserved; +}ATOM_OBJECT; + +typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure +{ + UCHAR ucNumberOfObjects; + UCHAR ucPadding[3]; + ATOM_OBJECT asObjects[1]; +}ATOM_OBJECT_TABLE; + +typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure +{ + UCHAR ucNumberOfSrc; + USHORT usSrcObjectID[1]; + UCHAR ucNumberOfDst; + USHORT usDstObjectID[1]; +}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; + + +//Two definitions below are for OPM on MXM module designs + +#define EXT_HPDPIN_LUTINDEX_0 0 +#define EXT_HPDPIN_LUTINDEX_1 1 +#define EXT_HPDPIN_LUTINDEX_2 2 +#define EXT_HPDPIN_LUTINDEX_3 3 +#define EXT_HPDPIN_LUTINDEX_4 4 +#define EXT_HPDPIN_LUTINDEX_5 5 +#define EXT_HPDPIN_LUTINDEX_6 6 +#define EXT_HPDPIN_LUTINDEX_7 7 +#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) + +#define EXT_AUXDDC_LUTINDEX_0 0 +#define EXT_AUXDDC_LUTINDEX_1 1 +#define EXT_AUXDDC_LUTINDEX_2 2 +#define EXT_AUXDDC_LUTINDEX_3 3 +#define EXT_AUXDDC_LUTINDEX_4 4 +#define EXT_AUXDDC_LUTINDEX_5 5 +#define EXT_AUXDDC_LUTINDEX_6 6 +#define EXT_AUXDDC_LUTINDEX_7 7 +#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) + +//ucChannelMapping are defined as following +//for DP connector, eDP, DP to VGA/LVDS +//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING +{ +#if ATOM_BIG_ENDIAN + UCHAR ucDP_Lane3_Source:2; + UCHAR ucDP_Lane2_Source:2; + UCHAR ucDP_Lane1_Source:2; + UCHAR ucDP_Lane0_Source:2; +#else + UCHAR ucDP_Lane0_Source:2; + UCHAR ucDP_Lane1_Source:2; + UCHAR ucDP_Lane2_Source:2; + UCHAR ucDP_Lane3_Source:2; +#endif +}ATOM_DP_CONN_CHANNEL_MAPPING; + +//for DVI/HDMI, in dual link case, both links have to have same mapping. +//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING +{ +#if ATOM_BIG_ENDIAN + UCHAR ucDVI_CLK_Source:2; + UCHAR ucDVI_DATA0_Source:2; + UCHAR ucDVI_DATA1_Source:2; + UCHAR ucDVI_DATA2_Source:2; +#else + UCHAR ucDVI_DATA2_Source:2; + UCHAR ucDVI_DATA1_Source:2; + UCHAR ucDVI_DATA0_Source:2; + UCHAR ucDVI_CLK_Source:2; +#endif +}ATOM_DVI_CONN_CHANNEL_MAPPING; + +typedef struct _EXT_DISPLAY_PATH +{ + USHORT usDeviceTag; //A bit vector to show what devices are supported + USHORT usDeviceACPIEnum; //16bit device ACPI id. + USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions + UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT + UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT + USHORT usExtEncoderObjId; //external encoder object id + union{ + UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping + ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; + ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; + }; + UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted + USHORT usCaps; + USHORT usReserved; +}EXT_DISPLAY_PATH; + +#define NUMBER_OF_UCHAR_FOR_GUID 16 +#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 + +//usCaps +#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 +#define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x02 +#define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 0x04 +#define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT 0x08 + +typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string + EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. + UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. + UCHAR uc3DStereoPinId; // use for eDP panel + UCHAR ucRemoteDisplayConfig; + UCHAR uceDPToLVDSRxId; + UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value + UCHAR Reserved[3]; // for potential expansion +}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; + +//Related definitions, all records are differnt but they have a commond header +typedef struct _ATOM_COMMON_RECORD_HEADER +{ + UCHAR ucRecordType; //An emun to indicate the record type + UCHAR ucRecordSize; //The size of the whole record in byte +}ATOM_COMMON_RECORD_HEADER; + + +#define ATOM_I2C_RECORD_TYPE 1 +#define ATOM_HPD_INT_RECORD_TYPE 2 +#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 +#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 +#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE +#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE +#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 +#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE +#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 +#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 +#define ATOM_CONNECTOR_CF_RECORD_TYPE 11 +#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 +#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 +#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 +#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 +#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table +#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table +#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record +#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 +#define ATOM_ENCODER_CAP_RECORD_TYPE 20 +#define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 + + +//Must be updated when new record type is added,equal to that record definition! +#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE + +typedef struct _ATOM_I2C_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + ATOM_I2C_ID_CONFIG sucI2cId; + UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC +}ATOM_I2C_RECORD; + +typedef struct _ATOM_HPD_INT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info + UCHAR ucPlugged_PinState; +}ATOM_HPD_INT_RECORD; + + +typedef struct _ATOM_OUTPUT_PROTECTION_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucProtectionFlag; + UCHAR ucReserved; +}ATOM_OUTPUT_PROTECTION_RECORD; + +typedef struct _ATOM_CONNECTOR_DEVICE_TAG +{ + ULONG ulACPIDeviceEnum; //Reserved for now + USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" + USHORT usPadding; +}ATOM_CONNECTOR_DEVICE_TAG; + +typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucNumberOfDevice; + UCHAR ucReserved; + ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation +}ATOM_CONNECTOR_DEVICE_TAG_RECORD; + + +typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucConfigGPIOID; + UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in + UCHAR ucFlowinGPIPID; + UCHAR ucExtInGPIPID; +}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; + +typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucCTL1GPIO_ID; + UCHAR ucCTL1GPIOState; //Set to 1 when it's active high + UCHAR ucCTL2GPIO_ID; + UCHAR ucCTL2GPIOState; //Set to 1 when it's active high + UCHAR ucCTL3GPIO_ID; + UCHAR ucCTL3GPIOState; //Set to 1 when it's active high + UCHAR ucCTLFPGA_IN_ID; + UCHAR ucPadding[3]; +}ATOM_ENCODER_FPGA_CONTROL_RECORD; + +typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info + UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected +}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; + +typedef struct _ATOM_JTAG_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucTMSGPIO_ID; + UCHAR ucTMSGPIOState; //Set to 1 when it's active high + UCHAR ucTCKGPIO_ID; + UCHAR ucTCKGPIOState; //Set to 1 when it's active high + UCHAR ucTDOGPIO_ID; + UCHAR ucTDOGPIOState; //Set to 1 when it's active high + UCHAR ucTDIGPIO_ID; + UCHAR ucTDIGPIOState; //Set to 1 when it's active high + UCHAR ucPadding[2]; +}ATOM_JTAG_RECORD; + + +//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually +typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR +{ + UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table + UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin +}ATOM_GPIO_PIN_CONTROL_PAIR; + +typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucFlags; // Future expnadibility + UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object + ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins +}ATOM_OBJECT_GPIO_CNTL_RECORD; + +//Definitions for GPIO pin state +#define GPIO_PIN_TYPE_INPUT 0x00 +#define GPIO_PIN_TYPE_OUTPUT 0x10 +#define GPIO_PIN_TYPE_HW_CONTROL 0x20 + +//For GPIO_PIN_TYPE_OUTPUT the following is defined +#define GPIO_PIN_OUTPUT_STATE_MASK 0x01 +#define GPIO_PIN_OUTPUT_STATE_SHIFT 0 +#define GPIO_PIN_STATE_ACTIVE_LOW 0x0 +#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 + +// Indexes to GPIO array in GLSync record +// GLSync record is for Frame Lock/Gen Lock feature. +#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 +#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 +#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 +#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 +#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 +#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 +#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 +#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 +#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 +#define ATOM_GPIO_INDEX_GLSYNC_MAX 9 + +typedef struct _ATOM_ENCODER_DVO_CF_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + ULONG ulStrengthControl; // DVOA strength control for CF + UCHAR ucPadding[2]; +}ATOM_ENCODER_DVO_CF_RECORD; + +// Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap +#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder +#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled +#define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not. + +typedef struct _ATOM_ENCODER_CAP_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + union { + USHORT usEncoderCap; + struct { +#if ATOM_BIG_ENDIAN + USHORT usReserved:14; // Bit1-15 may be defined for other capability in future + USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable + USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. +#else + USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. + USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable + USHORT usReserved:14; // Bit1-15 may be defined for other capability in future +#endif + }; + }; +}ATOM_ENCODER_CAP_RECORD; + +// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle +#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 +#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 + +typedef struct _ATOM_CONNECTOR_CF_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + USHORT usMaxPixClk; + UCHAR ucFlowCntlGpioId; + UCHAR ucSwapCntlGpioId; + UCHAR ucConnectedDvoBundle; + UCHAR ucPadding; +}ATOM_CONNECTOR_CF_RECORD; + +typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + ATOM_DTD_FORMAT asTiming; +}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; + +typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE + UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A + UCHAR ucReserved; +}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; + + +typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state + UCHAR ucMuxControlPin; + UCHAR ucMuxState[2]; //for alligment purpose +}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; + +typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucMuxType; + UCHAR ucMuxControlPin; + UCHAR ucMuxState[2]; //for alligment purpose +}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; + +// define ucMuxType +#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f +#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 + +typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table +}ATOM_CONNECTOR_HPDPIN_LUT_RECORD; + +typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE +{ + ATOM_COMMON_RECORD_HEADER sheader; + ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID +}ATOM_CONNECTOR_AUXDDC_LUT_RECORD; + +typedef struct _ATOM_OBJECT_LINK_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + USHORT usObjectID; //could be connector, encorder or other object in object.h +}ATOM_OBJECT_LINK_RECORD; + +typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + USHORT usReserved; +}ATOM_CONNECTOR_REMOTE_CAP_RECORD; + +typedef struct _ATOM_CONNECTOR_LAYOUT_INFO +{ + USHORT usConnectorObjectId; + UCHAR ucConnectorType; + UCHAR ucPosition; +}ATOM_CONNECTOR_LAYOUT_INFO; + +// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size +#define CONNECTOR_TYPE_DVI_D 1 +#define CONNECTOR_TYPE_DVI_I 2 +#define CONNECTOR_TYPE_VGA 3 +#define CONNECTOR_TYPE_HDMI 4 +#define CONNECTOR_TYPE_DISPLAY_PORT 5 +#define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6 + +typedef struct _ATOM_BRACKET_LAYOUT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucLength; + UCHAR ucWidth; + UCHAR ucConnNum; + UCHAR ucReserved; + ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1]; +}ATOM_BRACKET_LAYOUT_RECORD; + + +/****************************************************************************/ +// Structure used in XXXX +/****************************************************************************/ +typedef struct _ATOM_VOLTAGE_INFO_HEADER +{ + USHORT usVDDCBaseLevel; //In number of 50mv unit + USHORT usReserved; //For possible extension table offset + UCHAR ucNumOfVoltageEntries; + UCHAR ucBytesPerVoltageEntry; + UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit + UCHAR ucDefaultVoltageEntry; + UCHAR ucVoltageControlI2cLine; + UCHAR ucVoltageControlAddress; + UCHAR ucVoltageControlOffset; +}ATOM_VOLTAGE_INFO_HEADER; + +typedef struct _ATOM_VOLTAGE_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_INFO_HEADER viHeader; + UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry +}ATOM_VOLTAGE_INFO; + + +typedef struct _ATOM_VOLTAGE_FORMULA +{ + USHORT usVoltageBaseLevel; // In number of 1mv unit + USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit + UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage + UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv + UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep + UCHAR ucReserved; + UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries +}ATOM_VOLTAGE_FORMULA; + +typedef struct _VOLTAGE_LUT_ENTRY +{ + USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code + USHORT usVoltageValue; // The corresponding Voltage Value, in mV +}VOLTAGE_LUT_ENTRY; + +typedef struct _ATOM_VOLTAGE_FORMULA_V2 +{ + UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage + UCHAR ucReserved[3]; + VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries +}ATOM_VOLTAGE_FORMULA_V2; + +typedef struct _ATOM_VOLTAGE_CONTROL +{ + UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine + UCHAR ucVoltageControlI2cLine; + UCHAR ucVoltageControlAddress; + UCHAR ucVoltageControlOffset; + USHORT usGpioPin_AIndex; //GPIO_PAD register index + UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff + UCHAR ucReserved; +}ATOM_VOLTAGE_CONTROL; + +// Define ucVoltageControlId +#define VOLTAGE_CONTROLLED_BY_HW 0x00 +#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F +#define VOLTAGE_CONTROLLED_BY_GPIO 0x80 +#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage +#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI +#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage +#define VOLTAGE_CONTROL_ID_DS4402 0x04 +#define VOLTAGE_CONTROL_ID_UP6266 0x05 +#define VOLTAGE_CONTROL_ID_SCORPIO 0x06 +#define VOLTAGE_CONTROL_ID_VT1556M 0x07 +#define VOLTAGE_CONTROL_ID_CHL822x 0x08 +#define VOLTAGE_CONTROL_ID_VT1586M 0x09 +#define VOLTAGE_CONTROL_ID_UP1637 0x0A +#define VOLTAGE_CONTROL_ID_CHL8214 0x0B +#define VOLTAGE_CONTROL_ID_UP1801 0x0C +#define VOLTAGE_CONTROL_ID_ST6788A 0x0D +#define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E +#define VOLTAGE_CONTROL_ID_AD527x 0x0F +#define VOLTAGE_CONTROL_ID_NCP81022 0x10 +#define VOLTAGE_CONTROL_ID_LTC2635 0x11 +#define VOLTAGE_CONTROL_ID_NCP4208 0x12 +#define VOLTAGE_CONTROL_ID_IR35xx 0x13 +#define VOLTAGE_CONTROL_ID_RT9403 0x14 + +#define VOLTAGE_CONTROL_ID_GENERIC_I2C 0x40 + +typedef struct _ATOM_VOLTAGE_OBJECT +{ + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucSize; //Size of Object + ATOM_VOLTAGE_CONTROL asControl; //describ how to control + ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID +}ATOM_VOLTAGE_OBJECT; + +typedef struct _ATOM_VOLTAGE_OBJECT_V2 +{ + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucSize; //Size of Object + ATOM_VOLTAGE_CONTROL asControl; //describ how to control + ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID +}ATOM_VOLTAGE_OBJECT_V2; + +typedef struct _ATOM_VOLTAGE_OBJECT_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control +}ATOM_VOLTAGE_OBJECT_INFO; + +typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control +}ATOM_VOLTAGE_OBJECT_INFO_V2; + +typedef struct _ATOM_LEAKID_VOLTAGE +{ + UCHAR ucLeakageId; + UCHAR ucReserved; + USHORT usVoltage; +}ATOM_LEAKID_VOLTAGE; + +typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase + USHORT usSize; //Size of Object +}ATOM_VOLTAGE_OBJECT_HEADER_V3; + +// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode +#define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 +#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 +#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 +#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 +#define VOLTAGE_OBJ_EVV 8 +#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 +#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 +#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 + +typedef struct _VOLTAGE_LUT_ENTRY_V2 +{ + ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register + USHORT usVoltageValue; // The corresponding Voltage Value, in mV +}VOLTAGE_LUT_ENTRY_V2; + +typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 +{ + USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register + USHORT usVoltageId; + USHORT usLeakageId; // The corresponding Voltage Value, in mV +}LEAKAGE_VOLTAGE_LUT_ENTRY_V2; + + +typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 +{ + ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ + UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id + UCHAR ucVoltageControlI2cLine; + UCHAR ucVoltageControlAddress; + UCHAR ucVoltageControlOffset; + UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data + UCHAR ulReserved[3]; + VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff +}ATOM_I2C_VOLTAGE_OBJECT_V3; + +// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag +#define VOLTAGE_DATA_ONE_BYTE 0 +#define VOLTAGE_DATA_TWO_BYTE 1 + +typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 +{ + ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT + UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode + UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table + UCHAR ucPhaseDelay; // phase delay in unit of micro second + UCHAR ucReserved; + ULONG ulGpioMaskVal; // GPIO Mask value + VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; +}ATOM_GPIO_VOLTAGE_OBJECT_V3; + +typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 +{ + ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 + UCHAR ucLeakageCntlId; // default is 0 + UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table + UCHAR ucReserved[2]; + ULONG ulMaxVoltageLevel; + LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; +}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; + + +typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 +{ + ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 +// 14:7 � PSI0_VID +// 6 � PSI0_EN +// 5 � PSI1 +// 4:2 � load line slope trim. +// 1:0 � offset trim, + USHORT usLoadLine_PSI; +// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 + UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 + UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 + ULONG ulReserved; +}ATOM_SVID2_VOLTAGE_OBJECT_V3; + +typedef union _ATOM_VOLTAGE_OBJECT_V3{ + ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; + ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; + ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; + ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; +}ATOM_VOLTAGE_OBJECT_V3; + +typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control +}ATOM_VOLTAGE_OBJECT_INFO_V3_1; + + +typedef struct _ATOM_ASIC_PROFILE_VOLTAGE +{ + UCHAR ucProfileId; + UCHAR ucReserved; + USHORT usSize; + USHORT usEfuseSpareStartAddr; + USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, + ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage +}ATOM_ASIC_PROFILE_VOLTAGE; + +//ucProfileId +#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 +#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 +#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 + +typedef struct _ATOM_ASIC_PROFILING_INFO +{ + ATOM_COMMON_TABLE_HEADER asHeader; + ATOM_ASIC_PROFILE_VOLTAGE asVoltage; +}ATOM_ASIC_PROFILING_INFO; + +typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 +{ + ATOM_COMMON_TABLE_HEADER asHeader; + UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table + USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) + + UCHAR ucElbVDDC_Num; + USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) + USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array + + UCHAR ucElbVDDCI_Num; + USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) + USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array +}ATOM_ASIC_PROFILING_INFO_V2_1; + + +//Here is parameter to convert Efuse value to Measure value +//Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2 +typedef struct _EFUSE_LOGISTIC_FUNC_PARAM +{ + USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 + UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 + UCHAR ucEfuseLength; // Efuse bits length, + ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number + ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2 +}EFUSE_LOGISTIC_FUNC_PARAM; + +//Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min ) +typedef struct _EFUSE_LINEAR_FUNC_PARAM +{ + USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 + UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 + UCHAR ucEfuseLength; // Efuse bits length, + ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number + ULONG ulEfuseMin; // Min +}EFUSE_LINEAR_FUNC_PARAM; + + +typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 +{ + ATOM_COMMON_TABLE_HEADER asHeader; + ULONG ulEvvDerateTdp; + ULONG ulEvvDerateTdc; + ULONG ulBoardCoreTemp; + ULONG ulMaxVddc; + ULONG ulMinVddc; + ULONG ulLoadLineSlop; + ULONG ulLeakageTemp; + ULONG ulLeakageVoltage; + EFUSE_LINEAR_FUNC_PARAM sCACm; + EFUSE_LINEAR_FUNC_PARAM sCACb; + EFUSE_LOGISTIC_FUNC_PARAM sKt_b; + EFUSE_LOGISTIC_FUNC_PARAM sKv_m; + EFUSE_LOGISTIC_FUNC_PARAM sKv_b; + USHORT usLkgEuseIndex; + UCHAR ucLkgEfuseBitLSB; + UCHAR ucLkgEfuseLength; + ULONG ulLkgEncodeLn_MaxDivMin; + ULONG ulLkgEncodeMax; + ULONG ulLkgEncodeMin; + ULONG ulEfuseLogisticAlpha; + USHORT usPowerDpm0; + USHORT usCurrentDpm0; + USHORT usPowerDpm1; + USHORT usCurrentDpm1; + USHORT usPowerDpm2; + USHORT usCurrentDpm2; + USHORT usPowerDpm3; + USHORT usCurrentDpm3; + USHORT usPowerDpm4; + USHORT usCurrentDpm4; + USHORT usPowerDpm5; + USHORT usCurrentDpm5; + USHORT usPowerDpm6; + USHORT usCurrentDpm6; + USHORT usPowerDpm7; + USHORT usCurrentDpm7; +}ATOM_ASIC_PROFILING_INFO_V3_1; + + +typedef struct _ATOM_ASIC_PROFILING_INFO_V3_2 +{ + ATOM_COMMON_TABLE_HEADER asHeader; + ULONG ulEvvLkgFactor; + ULONG ulBoardCoreTemp; + ULONG ulMaxVddc; + ULONG ulMinVddc; + ULONG ulLoadLineSlop; + ULONG ulLeakageTemp; + ULONG ulLeakageVoltage; + EFUSE_LINEAR_FUNC_PARAM sCACm; + EFUSE_LINEAR_FUNC_PARAM sCACb; + EFUSE_LOGISTIC_FUNC_PARAM sKt_b; + EFUSE_LOGISTIC_FUNC_PARAM sKv_m; + EFUSE_LOGISTIC_FUNC_PARAM sKv_b; + USHORT usLkgEuseIndex; + UCHAR ucLkgEfuseBitLSB; + UCHAR ucLkgEfuseLength; + ULONG ulLkgEncodeLn_MaxDivMin; + ULONG ulLkgEncodeMax; + ULONG ulLkgEncodeMin; + ULONG ulEfuseLogisticAlpha; + USHORT usPowerDpm0; + USHORT usPowerDpm1; + USHORT usPowerDpm2; + USHORT usPowerDpm3; + USHORT usPowerDpm4; + USHORT usPowerDpm5; + USHORT usPowerDpm6; + USHORT usPowerDpm7; + ULONG ulTdpDerateDPM0; + ULONG ulTdpDerateDPM1; + ULONG ulTdpDerateDPM2; + ULONG ulTdpDerateDPM3; + ULONG ulTdpDerateDPM4; + ULONG ulTdpDerateDPM5; + ULONG ulTdpDerateDPM6; + ULONG ulTdpDerateDPM7; +}ATOM_ASIC_PROFILING_INFO_V3_2; + + +// for Tonga/Fiji speed EVV algorithm +typedef struct _ATOM_ASIC_PROFILING_INFO_V3_3 +{ + ATOM_COMMON_TABLE_HEADER asHeader; + ULONG ulEvvLkgFactor; + ULONG ulBoardCoreTemp; + ULONG ulMaxVddc; + ULONG ulMinVddc; + ULONG ulLoadLineSlop; + ULONG ulLeakageTemp; + ULONG ulLeakageVoltage; + EFUSE_LINEAR_FUNC_PARAM sCACm; + EFUSE_LINEAR_FUNC_PARAM sCACb; + EFUSE_LOGISTIC_FUNC_PARAM sKt_b; + EFUSE_LOGISTIC_FUNC_PARAM sKv_m; + EFUSE_LOGISTIC_FUNC_PARAM sKv_b; + USHORT usLkgEuseIndex; + UCHAR ucLkgEfuseBitLSB; + UCHAR ucLkgEfuseLength; + ULONG ulLkgEncodeLn_MaxDivMin; + ULONG ulLkgEncodeMax; + ULONG ulLkgEncodeMin; + ULONG ulEfuseLogisticAlpha; + USHORT usPowerDpm0; + USHORT usPowerDpm1; + USHORT usPowerDpm2; + USHORT usPowerDpm3; + USHORT usPowerDpm4; + USHORT usPowerDpm5; + USHORT usPowerDpm6; + USHORT usPowerDpm7; + ULONG ulTdpDerateDPM0; + ULONG ulTdpDerateDPM1; + ULONG ulTdpDerateDPM2; + ULONG ulTdpDerateDPM3; + ULONG ulTdpDerateDPM4; + ULONG ulTdpDerateDPM5; + ULONG ulTdpDerateDPM6; + ULONG ulTdpDerateDPM7; + EFUSE_LINEAR_FUNC_PARAM sRoFuse; + ULONG ulRoAlpha; + ULONG ulRoBeta; + ULONG ulRoGamma; + ULONG ulRoEpsilon; + ULONG ulATermRo; + ULONG ulBTermRo; + ULONG ulCTermRo; + ULONG ulSclkMargin; + ULONG ulFmaxPercent; + ULONG ulCRPercent; + ULONG ulSFmaxPercent; + ULONG ulSCRPercent; + ULONG ulSDCMargine; +}ATOM_ASIC_PROFILING_INFO_V3_3; + +typedef struct _ATOM_POWER_SOURCE_OBJECT +{ + UCHAR ucPwrSrcId; // Power source + UCHAR ucPwrSensorType; // GPIO, I2C or none + UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id + UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect + UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect + UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect + UCHAR ucPwrSensActiveState; // high active or low active + UCHAR ucReserve[3]; // reserve + USHORT usSensPwr; // in unit of watt +}ATOM_POWER_SOURCE_OBJECT; + +typedef struct _ATOM_POWER_SOURCE_INFO +{ + ATOM_COMMON_TABLE_HEADER asHeader; + UCHAR asPwrbehave[16]; + ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; +}ATOM_POWER_SOURCE_INFO; + + +//Define ucPwrSrcId +#define POWERSOURCE_PCIE_ID1 0x00 +#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 +#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 +#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 +#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 + +//define ucPwrSensorId +#define POWER_SENSOR_ALWAYS 0x00 +#define POWER_SENSOR_GPIO 0x01 +#define POWER_SENSOR_I2C 0x02 + +typedef struct _ATOM_CLK_VOLT_CAPABILITY +{ + ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table + ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz +}ATOM_CLK_VOLT_CAPABILITY; + + +typedef struct _ATOM_CLK_VOLT_CAPABILITY_V2 +{ + USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv, + ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz +}ATOM_CLK_VOLT_CAPABILITY_V2; + +typedef struct _ATOM_AVAILABLE_SCLK_LIST +{ + ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz + USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK + USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK +}ATOM_AVAILABLE_SCLK_LIST; + +// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition +#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] + +// this IntegrateSystemInfoTable is used for Liano/Ontario APU +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; + ULONG ulDentistVCOFreq; + ULONG ulBootUpUMAClock; + ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; + ULONG ulBootUpReqDisplayVector; + ULONG ulOtherDisplayMisc; + ULONG ulGPUCapInfo; + ULONG ulSB_MMIO_Base_Addr; + USHORT usRequestedPWMFreqInHz; + UCHAR ucHtcTmpLmt; + UCHAR ucHtcHystLmt; + ULONG ulMinEngineClock; + ULONG ulSystemConfig; + ULONG ulCPUCapInfo; + USHORT usNBP0Voltage; + USHORT usNBP1Voltage; + USHORT usBootUpNBVoltage; + USHORT usExtDispConnInfoOffset; + USHORT usPanelRefreshRateRange; + UCHAR ucMemoryType; + UCHAR ucUMAChannelNumber; + ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; + ULONG ulCSR_M3_ARB_CNTL_UVD[10]; + ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; + ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; + ULONG ulGMCRestoreResetTime; + ULONG ulMinimumNClk; + ULONG ulIdleNClk; + ULONG ulDDR_DLL_PowerUpTime; + ULONG ulDDR_PLL_PowerUpTime; + USHORT usPCIEClkSSPercentage; + USHORT usPCIEClkSSType; + USHORT usLvdsSSPercentage; + USHORT usLvdsSSpreadRateIn10Hz; + USHORT usHDMISSPercentage; + USHORT usHDMISSpreadRateIn10Hz; + USHORT usDVISSPercentage; + USHORT usDVISSpreadRateIn10Hz; + ULONG SclkDpmBoostMargin; + ULONG SclkDpmThrottleMargin; + USHORT SclkDpmTdpLimitPG; + USHORT SclkDpmTdpLimitBoost; + ULONG ulBoostEngineCLock; + UCHAR ulBoostVid_2bit; + UCHAR EnableBoost; + USHORT GnbTdpLimit; + USHORT usMaxLVDSPclkFreqInSingleLink; + UCHAR ucLvdsMisc; + UCHAR ucLVDSReserved; + ULONG ulReserved3[15]; + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; +}ATOM_INTEGRATED_SYSTEM_INFO_V6; + +// ulGPUCapInfo +#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 +#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 + +//ucLVDSMisc: +#define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 +#define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 +#define SYS_INFO_LVDSMISC__888_BPC 0x04 +#define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 +#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 +// new since Trinity +#define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20 + +// not used any more +#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 +#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 + +/********************************************************************************************************************** + ATOM_INTEGRATED_SYSTEM_INFO_V6 Description +ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock +ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. +ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. +sDISPCLK_Voltage: Report Display clock voltage requirement. + +ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: + ATOM_DEVICE_CRT1_SUPPORT 0x0001 + ATOM_DEVICE_CRT2_SUPPORT 0x0010 + ATOM_DEVICE_DFP1_SUPPORT 0x0008 + ATOM_DEVICE_DFP6_SUPPORT 0x0040 + ATOM_DEVICE_DFP2_SUPPORT 0x0080 + ATOM_DEVICE_DFP3_SUPPORT 0x0200 + ATOM_DEVICE_DFP4_SUPPORT 0x0400 + ATOM_DEVICE_DFP5_SUPPORT 0x0800 + ATOM_DEVICE_LCD1_SUPPORT 0x0002 +ulOtherDisplayMisc: Other display related flags, not defined yet. +ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. + =1: TMDS/HDMI Coherent Mode use signel PLL mode. + bit[3]=0: Enable HW AUX mode detection logic + =1: Disable HW AUX mode dettion logic +ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. + +usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). + Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; + + When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: + 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; + VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, + Changing BL using VBIOS function is functional in both driver and non-driver present environment; + and enabling VariBri under the driver environment from PP table is optional. + + 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating + that BL control from GPU is expected. + VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 + Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but + it's per platform + and enabling VariBri under the driver environment from PP table is optional. + +ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. + Threshold on value to enter HTC_active state. +ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. + To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. +ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. +ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled + =1: PCIE Power Gating Enabled + Bit[1]=0: DDR-DLL shut-down feature disabled. + 1: DDR-DLL shut-down feature enabled. + Bit[2]=0: DDR-PLL Power down feature disabled. + 1: DDR-PLL Power down feature enabled. +ulCPUCapInfo: TBD +usNBP0Voltage: VID for voltage on NB P0 State +usNBP1Voltage: VID for voltage on NB P1 State +usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. +usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure +usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set + to indicate a range. + SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 + SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 + SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 + SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 +ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. +ucUMAChannelNumber: System memory channel numbers. +ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default +ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. +ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. +sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high +ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. +ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. +ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. +ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. +ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. +usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. +usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. +usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. +usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz +ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode + [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped + [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color + [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used + [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) +**********************************************************************************************************************/ + +// this Table is used for Liano/Ontario APU +typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 +{ + ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; + ULONG ulPowerplayTable[128]; +}ATOM_FUSION_SYSTEM_INFO_V1; + + +typedef struct _ATOM_TDP_CONFIG_BITS +{ +#if ATOM_BIG_ENDIAN + ULONG uReserved:2; + ULONG uTDP_Value:14; // Original TDP value in tens of milli watts + ULONG uCTDP_Value:14; // Override value in tens of milli watts + ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) +#else + ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) + ULONG uCTDP_Value:14; // Override value in tens of milli watts + ULONG uTDP_Value:14; // Original TDP value in tens of milli watts + ULONG uReserved:2; +#endif +}ATOM_TDP_CONFIG_BITS; + +typedef union _ATOM_TDP_CONFIG +{ + ATOM_TDP_CONFIG_BITS TDP_config; + ULONG TDP_config_all; +}ATOM_TDP_CONFIG; + +/********************************************************************************************************************** + ATOM_FUSION_SYSTEM_INFO_V1 Description +sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. +ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] +**********************************************************************************************************************/ + +// this IntegrateSystemInfoTable is used for Trinity APU +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; + ULONG ulDentistVCOFreq; + ULONG ulBootUpUMAClock; + ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; + ULONG ulBootUpReqDisplayVector; + ULONG ulOtherDisplayMisc; + ULONG ulGPUCapInfo; + ULONG ulSB_MMIO_Base_Addr; + USHORT usRequestedPWMFreqInHz; + UCHAR ucHtcTmpLmt; + UCHAR ucHtcHystLmt; + ULONG ulMinEngineClock; + ULONG ulSystemConfig; + ULONG ulCPUCapInfo; + USHORT usNBP0Voltage; + USHORT usNBP1Voltage; + USHORT usBootUpNBVoltage; + USHORT usExtDispConnInfoOffset; + USHORT usPanelRefreshRateRange; + UCHAR ucMemoryType; + UCHAR ucUMAChannelNumber; + UCHAR strVBIOSMsg[40]; + ATOM_TDP_CONFIG asTdpConfig; + ULONG ulReserved[19]; + ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; + ULONG ulGMCRestoreResetTime; + ULONG ulMinimumNClk; + ULONG ulIdleNClk; + ULONG ulDDR_DLL_PowerUpTime; + ULONG ulDDR_PLL_PowerUpTime; + USHORT usPCIEClkSSPercentage; + USHORT usPCIEClkSSType; + USHORT usLvdsSSPercentage; + USHORT usLvdsSSpreadRateIn10Hz; + USHORT usHDMISSPercentage; + USHORT usHDMISSpreadRateIn10Hz; + USHORT usDVISSPercentage; + USHORT usDVISSpreadRateIn10Hz; + ULONG SclkDpmBoostMargin; + ULONG SclkDpmThrottleMargin; + USHORT SclkDpmTdpLimitPG; + USHORT SclkDpmTdpLimitBoost; + ULONG ulBoostEngineCLock; + UCHAR ulBoostVid_2bit; + UCHAR EnableBoost; + USHORT GnbTdpLimit; + USHORT usMaxLVDSPclkFreqInSingleLink; + UCHAR ucLvdsMisc; + UCHAR ucTravisLVDSVolAdjust; + UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; + UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; + UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; + UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; + UCHAR ucLVDSOffToOnDelay_in4Ms; + UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; + UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; + UCHAR ucMinAllowedBL_Level; + ULONG ulLCDBitDepthControlVal; + ULONG ulNbpStateMemclkFreq[4]; + USHORT usNBP2Voltage; + USHORT usNBP3Voltage; + ULONG ulNbpStateNClkFreq[4]; + UCHAR ucNBDPMEnable; + UCHAR ucReserved[3]; + UCHAR ucDPMState0VclkFid; + UCHAR ucDPMState0DclkFid; + UCHAR ucDPMState1VclkFid; + UCHAR ucDPMState1DclkFid; + UCHAR ucDPMState2VclkFid; + UCHAR ucDPMState2DclkFid; + UCHAR ucDPMState3VclkFid; + UCHAR ucDPMState3DclkFid; + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; +}ATOM_INTEGRATED_SYSTEM_INFO_V1_7; + +// ulOtherDisplayMisc +#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 +#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 +#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 +#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 + +// ulGPUCapInfo +#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 +#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 +#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 +#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10 +//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML +#define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE 0x00010000 + +//ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML +#define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE 0x00020000 + +/********************************************************************************************************************** + ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description +ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock +ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. +ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. +sDISPCLK_Voltage: Report Display clock voltage requirement. + +ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: + ATOM_DEVICE_CRT1_SUPPORT 0x0001 + ATOM_DEVICE_DFP1_SUPPORT 0x0008 + ATOM_DEVICE_DFP6_SUPPORT 0x0040 + ATOM_DEVICE_DFP2_SUPPORT 0x0080 + ATOM_DEVICE_DFP3_SUPPORT 0x0200 + ATOM_DEVICE_DFP4_SUPPORT 0x0400 + ATOM_DEVICE_DFP5_SUPPORT 0x0800 + ATOM_DEVICE_LCD1_SUPPORT 0x0002 +ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. + =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. + bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS + =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS + bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS + =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS + bit[3]=0: VBIOS fast boot is disable + =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) +ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. + =1: TMDS/HDMI Coherent Mode use signel PLL mode. + bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) + =1: DP mode use single PLL mode + bit[3]=0: Enable AUX HW mode detection logic + =1: Disable AUX HW mode detection logic + +ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. + +usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). + Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; + + When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: + 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; + VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, + Changing BL using VBIOS function is functional in both driver and non-driver present environment; + and enabling VariBri under the driver environment from PP table is optional. + + 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating + that BL control from GPU is expected. + VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 + Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but + it's per platform + and enabling VariBri under the driver environment from PP table is optional. + +ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. + Threshold on value to enter HTC_active state. +ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. + To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. +ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. +ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled + =1: PCIE Power Gating Enabled + Bit[1]=0: DDR-DLL shut-down feature disabled. + 1: DDR-DLL shut-down feature enabled. + Bit[2]=0: DDR-PLL Power down feature disabled. + 1: DDR-PLL Power down feature enabled. +ulCPUCapInfo: TBD +usNBP0Voltage: VID for voltage on NB P0 State +usNBP1Voltage: VID for voltage on NB P1 State +usNBP2Voltage: VID for voltage on NB P2 State +usNBP3Voltage: VID for voltage on NB P3 State +usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. +usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure +usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set + to indicate a range. + SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 + SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 + SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 + SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 +ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. +ucUMAChannelNumber: System memory channel numbers. +ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default +ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. +ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. +sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high +ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. +ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. +ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. +ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. +ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. +usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. +usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. +usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. +usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz +ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode + [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped + [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color + [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used + [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) + [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 +ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust + value to program Travis register LVDS_CTRL_4 +ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). + =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. +ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). + =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. + +ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. + =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. + +ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. + =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. + +ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. + =0 means to use VBIOS default delay which is 125 ( 500ms ). + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. + +ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: + LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. + =0 means to use VBIOS default delay which is 0 ( 0ms ). + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. + +ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: + LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. + =0 means to use VBIOS default delay which is 0 ( 0ms ). + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. + +ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. + +ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. + +**********************************************************************************************************************/ + +// this IntegrateSystemInfoTable is used for Kaveri & Kabini APU +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; + ULONG ulDentistVCOFreq; + ULONG ulBootUpUMAClock; + ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; + ULONG ulBootUpReqDisplayVector; + ULONG ulVBIOSMisc; + ULONG ulGPUCapInfo; + ULONG ulDISP_CLK2Freq; + USHORT usRequestedPWMFreqInHz; + UCHAR ucHtcTmpLmt; + UCHAR ucHtcHystLmt; + ULONG ulReserved2; + ULONG ulSystemConfig; + ULONG ulCPUCapInfo; + ULONG ulReserved3; + USHORT usGPUReservedSysMemSize; + USHORT usExtDispConnInfoOffset; + USHORT usPanelRefreshRateRange; + UCHAR ucMemoryType; + UCHAR ucUMAChannelNumber; + UCHAR strVBIOSMsg[40]; + ATOM_TDP_CONFIG asTdpConfig; + ULONG ulReserved[19]; + ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; + ULONG ulGMCRestoreResetTime; + ULONG ulReserved4; + ULONG ulIdleNClk; + ULONG ulDDR_DLL_PowerUpTime; + ULONG ulDDR_PLL_PowerUpTime; + USHORT usPCIEClkSSPercentage; + USHORT usPCIEClkSSType; + USHORT usLvdsSSPercentage; + USHORT usLvdsSSpreadRateIn10Hz; + USHORT usHDMISSPercentage; + USHORT usHDMISSpreadRateIn10Hz; + USHORT usDVISSPercentage; + USHORT usDVISSpreadRateIn10Hz; + ULONG ulGPUReservedSysMemBaseAddrLo; + ULONG ulGPUReservedSysMemBaseAddrHi; + ATOM_CLK_VOLT_CAPABILITY s5thDISPCLK_Voltage; + ULONG ulReserved5; + USHORT usMaxLVDSPclkFreqInSingleLink; + UCHAR ucLvdsMisc; + UCHAR ucTravisLVDSVolAdjust; + UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; + UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; + UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; + UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; + UCHAR ucLVDSOffToOnDelay_in4Ms; + UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; + UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; + UCHAR ucMinAllowedBL_Level; + ULONG ulLCDBitDepthControlVal; + ULONG ulNbpStateMemclkFreq[4]; + ULONG ulPSPVersion; + ULONG ulNbpStateNClkFreq[4]; + USHORT usNBPStateVoltage[4]; + USHORT usBootUpNBVoltage; + USHORT usReserved2; + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; +}ATOM_INTEGRATED_SYSTEM_INFO_V1_8; + +/********************************************************************************************************************** + ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description +ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock +ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. +ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. +sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). + +ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: + ATOM_DEVICE_CRT1_SUPPORT 0x0001 + ATOM_DEVICE_DFP1_SUPPORT 0x0008 + ATOM_DEVICE_DFP6_SUPPORT 0x0040 + ATOM_DEVICE_DFP2_SUPPORT 0x0080 + ATOM_DEVICE_DFP3_SUPPORT 0x0200 + ATOM_DEVICE_DFP4_SUPPORT 0x0400 + ATOM_DEVICE_DFP5_SUPPORT 0x0800 + ATOM_DEVICE_LCD1_SUPPORT 0x0002 + +ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface + bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. + =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. + bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS + =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS + bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS + =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS + bit[3]=0: VBIOS fast boot is disable + =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) + +ulGPUCapInfo: bit[0~2]= Reserved + bit[3]=0: Enable AUX HW mode detection logic + =1: Disable AUX HW mode detection logic + bit[4]=0: Disable DFS bypass feature + =1: Enable DFS bypass feature + +usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). + Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; + + When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: + 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; + VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, + Changing BL using VBIOS function is functional in both driver and non-driver present environment; + and enabling VariBri under the driver environment from PP table is optional. + + 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating + that BL control from GPU is expected. + VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 + Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but + it's per platform + and enabling VariBri under the driver environment from PP table is optional. + +ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. +ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. + To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. + +ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled + =1: PCIE Power Gating Enabled + Bit[1]=0: DDR-DLL shut-down feature disabled. + 1: DDR-DLL shut-down feature enabled. + Bit[2]=0: DDR-PLL Power down feature disabled. + 1: DDR-PLL Power down feature enabled. + Bit[3]=0: GNB DPM is disabled + =1: GNB DPM is enabled +ulCPUCapInfo: TBD + +usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure +usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set + to indicate a range. + SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 + SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 + SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 + SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 + +ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. +ucUMAChannelNumber: System memory channel numbers. + +strVBIOSMsg[40]: VBIOS boot up customized message string + +sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high + +ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. +ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. +ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. +ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. + +usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. +usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. +usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. +usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. + +usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. +ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. +ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. + +usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz +ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode + [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped + [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color + [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used + [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) + [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 +ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust + value to program Travis register LVDS_CTRL_4 +ucLVDSPwrOnSeqDIGONtoDE_in4Ms: + LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). + =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. +ucLVDSPwrOnDEtoVARY_BL_in4Ms: + LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). + =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. +ucLVDSPwrOffVARY_BLtoDE_in4Ms: + LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. + =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. +ucLVDSPwrOffDEtoDIGON_in4Ms: + LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. + =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. +ucLVDSOffToOnDelay_in4Ms: + LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. + =0 means to use VBIOS default delay which is 125 ( 500ms ). + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. +ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: + LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. + =0 means to use VBIOS default delay which is 0 ( 0ms ). + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. + +ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: + LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. + =0 means to use VBIOS default delay which is 0 ( 0ms ). + This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. +ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. + +ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL + +ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). +ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State +usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage +usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded +sExtDispConnInfo: Display connector information table provided to VBIOS + +**********************************************************************************************************************/ + +// this Table is used for Kaveri/Kabini APU +typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 +{ + ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition + ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure +}ATOM_FUSION_SYSTEM_INFO_V2; + + +typedef struct _ATOM_I2C_REG_INFO +{ + UCHAR ucI2cRegIndex; + UCHAR ucI2cRegVal; +}ATOM_I2C_REG_INFO; + +// this IntegrateSystemInfoTable is used for Carrizo +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; + ULONG ulDentistVCOFreq; + ULONG ulBootUpUMAClock; + ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; // no longer used, keep it as is to avoid driver compiling error + ULONG ulBootUpReqDisplayVector; + ULONG ulVBIOSMisc; + ULONG ulGPUCapInfo; + ULONG ulDISP_CLK2Freq; + USHORT usRequestedPWMFreqInHz; + UCHAR ucHtcTmpLmt; + UCHAR ucHtcHystLmt; + ULONG ulReserved2; + ULONG ulSystemConfig; + ULONG ulCPUCapInfo; + ULONG ulReserved3; + USHORT usGPUReservedSysMemSize; + USHORT usExtDispConnInfoOffset; + USHORT usPanelRefreshRateRange; + UCHAR ucMemoryType; + UCHAR ucUMAChannelNumber; + UCHAR strVBIOSMsg[40]; + ATOM_TDP_CONFIG asTdpConfig; + UCHAR ucExtHDMIReDrvSlvAddr; + UCHAR ucExtHDMIReDrvRegNum; + ATOM_I2C_REG_INFO asExtHDMIRegSetting[9]; + ULONG ulReserved[2]; + ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; + ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; // no longer used, keep it as is to avoid driver compiling error + ULONG ulGMCRestoreResetTime; + ULONG ulReserved4; + ULONG ulIdleNClk; + ULONG ulDDR_DLL_PowerUpTime; + ULONG ulDDR_PLL_PowerUpTime; + USHORT usPCIEClkSSPercentage; + USHORT usPCIEClkSSType; + USHORT usLvdsSSPercentage; + USHORT usLvdsSSpreadRateIn10Hz; + USHORT usHDMISSPercentage; + USHORT usHDMISSpreadRateIn10Hz; + USHORT usDVISSPercentage; + USHORT usDVISSpreadRateIn10Hz; + ULONG ulGPUReservedSysMemBaseAddrLo; + ULONG ulGPUReservedSysMemBaseAddrHi; + ULONG ulReserved5[3]; + USHORT usMaxLVDSPclkFreqInSingleLink; + UCHAR ucLvdsMisc; + UCHAR ucTravisLVDSVolAdjust; + UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; + UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; + UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; + UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; + UCHAR ucLVDSOffToOnDelay_in4Ms; + UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; + UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; + UCHAR ucMinAllowedBL_Level; + ULONG ulLCDBitDepthControlVal; + ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed. + ULONG ulPSPVersion; + ULONG ulNbpStateNClkFreq[4]; + USHORT usNBPStateVoltage[4]; + USHORT usBootUpNBVoltage; + UCHAR ucEDPv1_4VSMode; + UCHAR ucReserved2; + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; +}ATOM_INTEGRATED_SYSTEM_INFO_V1_9; + + +// definition for ucEDPv1_4VSMode +#define EDP_VS_LEGACY_MODE 0 +#define EDP_VS_LOW_VDIFF_MODE 1 +#define EDP_VS_HIGH_VDIFF_MODE 2 +#define EDP_VS_STRETCH_MODE 3 +#define EDP_VS_SINGLE_VDIFF_MODE 4 +#define EDP_VS_VARIABLE_PREM_MODE 5 + + +// this IntegrateSystemInfoTable is used for Carrizo +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; + ULONG ulDentistVCOFreq; + ULONG ulBootUpUMAClock; + ULONG ulReserved0[8]; + ULONG ulBootUpReqDisplayVector; + ULONG ulVBIOSMisc; + ULONG ulGPUCapInfo; + ULONG ulReserved1; + USHORT usRequestedPWMFreqInHz; + UCHAR ucHtcTmpLmt; + UCHAR ucHtcHystLmt; + ULONG ulReserved2; + ULONG ulSystemConfig; + ULONG ulCPUCapInfo; + ULONG ulReserved3; + USHORT usGPUReservedSysMemSize; + USHORT usExtDispConnInfoOffset; + USHORT usPanelRefreshRateRange; + UCHAR ucMemoryType; + UCHAR ucUMAChannelNumber; + UCHAR strVBIOSMsg[40]; + ATOM_TDP_CONFIG asTdpConfig; + ULONG ulReserved[7]; + ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; + ULONG ulReserved6[10]; + ULONG ulGMCRestoreResetTime; + ULONG ulReserved4; + ULONG ulIdleNClk; + ULONG ulDDR_DLL_PowerUpTime; + ULONG ulDDR_PLL_PowerUpTime; + USHORT usPCIEClkSSPercentage; + USHORT usPCIEClkSSType; + USHORT usLvdsSSPercentage; + USHORT usLvdsSSpreadRateIn10Hz; + USHORT usHDMISSPercentage; + USHORT usHDMISSpreadRateIn10Hz; + USHORT usDVISSPercentage; + USHORT usDVISSpreadRateIn10Hz; + ULONG ulGPUReservedSysMemBaseAddrLo; + ULONG ulGPUReservedSysMemBaseAddrHi; + ULONG ulReserved5[3]; + USHORT usMaxLVDSPclkFreqInSingleLink; + UCHAR ucLvdsMisc; + UCHAR ucTravisLVDSVolAdjust; + UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; + UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; + UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; + UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; + UCHAR ucLVDSOffToOnDelay_in4Ms; + UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; + UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; + UCHAR ucMinAllowedBL_Level; + ULONG ulLCDBitDepthControlVal; + ULONG ulNbpStateMemclkFreq[2]; + ULONG ulReserved7[2]; + ULONG ulPSPVersion; + ULONG ulNbpStateNClkFreq[4]; + USHORT usNBPStateVoltage[4]; + USHORT usBootUpNBVoltage; + UCHAR ucEDPv1_4VSMode; + UCHAR ucReserved2; + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; +}ATOM_INTEGRATED_SYSTEM_INFO_V1_10; + +/**************************************************************************/ +// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design +//Memory SS Info Table +//Define Memory Clock SS chip ID +#define ICS91719 1 +#define ICS91720 2 + +//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol +typedef struct _ATOM_I2C_DATA_RECORD +{ + UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" + UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually +}ATOM_I2C_DATA_RECORD; + + +//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information +typedef struct _ATOM_I2C_DEVICE_SETUP_INFO +{ + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. + UCHAR ucSSChipID; //SS chip being used + UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip + UCHAR ucNumOfI2CDataRecords; //number of data block + ATOM_I2C_DATA_RECORD asI2CData[1]; +}ATOM_I2C_DEVICE_SETUP_INFO; + +//========================================================================================== +typedef struct _ATOM_ASIC_MVDD_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; +}ATOM_ASIC_MVDD_INFO; + +//========================================================================================== +#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO + +//========================================================================================== +/**************************************************************************/ + +typedef struct _ATOM_ASIC_SS_ASSIGNMENT +{ + ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz + USHORT usSpreadSpectrumPercentage; //in unit of 0.01% + USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq + UCHAR ucClockIndication; //Indicate which clock source needs SS + UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. + UCHAR ucReserved[2]; +}ATOM_ASIC_SS_ASSIGNMENT; + +//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. +//SS is not required or enabled if a match is not found. +#define ASIC_INTERNAL_MEMORY_SS 1 +#define ASIC_INTERNAL_ENGINE_SS 2 +#define ASIC_INTERNAL_UVD_SS 3 +#define ASIC_INTERNAL_SS_ON_TMDS 4 +#define ASIC_INTERNAL_SS_ON_HDMI 5 +#define ASIC_INTERNAL_SS_ON_LVDS 6 +#define ASIC_INTERNAL_SS_ON_DP 7 +#define ASIC_INTERNAL_SS_ON_DCPLL 8 +#define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 +#define ASIC_INTERNAL_VCE_SS 10 +#define ASIC_INTERNAL_GPUPLL_SS 11 + + +typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 +{ + ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz + //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) + USHORT usSpreadSpectrumPercentage; //in unit of 0.01% + USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq + UCHAR ucClockIndication; //Indicate which clock source needs SS + UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS + UCHAR ucReserved[2]; +}ATOM_ASIC_SS_ASSIGNMENT_V2; + +//ucSpreadSpectrumMode +//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 +//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 +//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 +//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 +//#define ATOM_INTERNAL_SS_MASK 0x00000000 +//#define ATOM_EXTERNAL_SS_MASK 0x00000002 + +typedef struct _ATOM_ASIC_INTERNAL_SS_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; +}ATOM_ASIC_INTERNAL_SS_INFO; + +typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. +}ATOM_ASIC_INTERNAL_SS_INFO_V2; + +typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 +{ + ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz + //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) + USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4 + USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq + UCHAR ucClockIndication; //Indicate which clock source needs SS + UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS + UCHAR ucReserved[2]; +}ATOM_ASIC_SS_ASSIGNMENT_V3; + +//ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode +#define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 +#define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 +#define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 + +typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. +}ATOM_ASIC_INTERNAL_SS_INFO_V3; + + +//==============================Scratch Pad Definition Portion=============================== +#define ATOM_DEVICE_CONNECT_INFO_DEF 0 +#define ATOM_ROM_LOCATION_DEF 1 +#define ATOM_TV_STANDARD_DEF 2 +#define ATOM_ACTIVE_INFO_DEF 3 +#define ATOM_LCD_INFO_DEF 4 +#define ATOM_DOS_REQ_INFO_DEF 5 +#define ATOM_ACC_CHANGE_INFO_DEF 6 +#define ATOM_DOS_MODE_INFO_DEF 7 +#define ATOM_I2C_CHANNEL_STATUS_DEF 8 +#define ATOM_I2C_CHANNEL_STATUS1_DEF 9 +#define ATOM_INTERNAL_TIMER_DEF 10 + +// BIOS_0_SCRATCH Definition +#define ATOM_S0_CRT1_MONO 0x00000001L +#define ATOM_S0_CRT1_COLOR 0x00000002L +#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) + +#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L +#define ATOM_S0_TV1_SVIDEO_A 0x00000008L +#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) + +#define ATOM_S0_CV_A 0x00000010L +#define ATOM_S0_CV_DIN_A 0x00000020L +#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) + + +#define ATOM_S0_CRT2_MONO 0x00000100L +#define ATOM_S0_CRT2_COLOR 0x00000200L +#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) + +#define ATOM_S0_TV1_COMPOSITE 0x00000400L +#define ATOM_S0_TV1_SVIDEO 0x00000800L +#define ATOM_S0_TV1_SCART 0x00004000L +#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) + +#define ATOM_S0_CV 0x00001000L +#define ATOM_S0_CV_DIN 0x00002000L +#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) + +#define ATOM_S0_DFP1 0x00010000L +#define ATOM_S0_DFP2 0x00020000L +#define ATOM_S0_LCD1 0x00040000L +#define ATOM_S0_LCD2 0x00080000L +#define ATOM_S0_DFP6 0x00100000L +#define ATOM_S0_DFP3 0x00200000L +#define ATOM_S0_DFP4 0x00400000L +#define ATOM_S0_DFP5 0x00800000L + + +#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 + +#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with + // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx + +#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L +#define ATOM_S0_THERMAL_STATE_SHIFT 26 + +#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L +#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 + +#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 +#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 +#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 +#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 + +//Byte aligned defintion for BIOS usage +#define ATOM_S0_CRT1_MONOb0 0x01 +#define ATOM_S0_CRT1_COLORb0 0x02 +#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) + +#define ATOM_S0_TV1_COMPOSITEb0 0x04 +#define ATOM_S0_TV1_SVIDEOb0 0x08 +#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) + +#define ATOM_S0_CVb0 0x10 +#define ATOM_S0_CV_DINb0 0x20 +#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) + +#define ATOM_S0_CRT2_MONOb1 0x01 +#define ATOM_S0_CRT2_COLORb1 0x02 +#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) + +#define ATOM_S0_TV1_COMPOSITEb1 0x04 +#define ATOM_S0_TV1_SVIDEOb1 0x08 +#define ATOM_S0_TV1_SCARTb1 0x40 +#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) + +#define ATOM_S0_CVb1 0x10 +#define ATOM_S0_CV_DINb1 0x20 +#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) + +#define ATOM_S0_DFP1b2 0x01 +#define ATOM_S0_DFP2b2 0x02 +#define ATOM_S0_LCD1b2 0x04 +#define ATOM_S0_LCD2b2 0x08 +#define ATOM_S0_DFP6b2 0x10 +#define ATOM_S0_DFP3b2 0x20 +#define ATOM_S0_DFP4b2 0x40 +#define ATOM_S0_DFP5b2 0x80 + + +#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C +#define ATOM_S0_THERMAL_STATE_SHIFTb3 2 + +#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 +#define ATOM_S0_LCD1_SHIFT 18 + +// BIOS_1_SCRATCH Definition +#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL +#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L + +// BIOS_2_SCRATCH Definition +#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL +#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L +#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 + +#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L +#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 +#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L + +#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L +#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L + +#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 +#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 +#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 +#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 +#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 +#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L + + +//Byte aligned defintion for BIOS usage +#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F +#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF +#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 + +#define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode +#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 +#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 + + +// BIOS_3_SCRATCH Definition +#define ATOM_S3_CRT1_ACTIVE 0x00000001L +#define ATOM_S3_LCD1_ACTIVE 0x00000002L +#define ATOM_S3_TV1_ACTIVE 0x00000004L +#define ATOM_S3_DFP1_ACTIVE 0x00000008L +#define ATOM_S3_CRT2_ACTIVE 0x00000010L +#define ATOM_S3_LCD2_ACTIVE 0x00000020L +#define ATOM_S3_DFP6_ACTIVE 0x00000040L +#define ATOM_S3_DFP2_ACTIVE 0x00000080L +#define ATOM_S3_CV_ACTIVE 0x00000100L +#define ATOM_S3_DFP3_ACTIVE 0x00000200L +#define ATOM_S3_DFP4_ACTIVE 0x00000400L +#define ATOM_S3_DFP5_ACTIVE 0x00000800L + + +#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL + +#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L +#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L + +#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L +#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L +#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L +#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L +#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L +#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L +#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L +#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L +#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L +#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L +#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L +#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L + + +#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L +#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L +//Below two definitions are not supported in pplib, but in the old powerplay in DAL +#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L +#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L + + + +//Byte aligned defintion for BIOS usage +#define ATOM_S3_CRT1_ACTIVEb0 0x01 +#define ATOM_S3_LCD1_ACTIVEb0 0x02 +#define ATOM_S3_TV1_ACTIVEb0 0x04 +#define ATOM_S3_DFP1_ACTIVEb0 0x08 +#define ATOM_S3_CRT2_ACTIVEb0 0x10 +#define ATOM_S3_LCD2_ACTIVEb0 0x20 +#define ATOM_S3_DFP6_ACTIVEb0 0x40 +#define ATOM_S3_DFP2_ACTIVEb0 0x80 +#define ATOM_S3_CV_ACTIVEb1 0x01 +#define ATOM_S3_DFP3_ACTIVEb1 0x02 +#define ATOM_S3_DFP4_ACTIVEb1 0x04 +#define ATOM_S3_DFP5_ACTIVEb1 0x08 + + +#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF + +#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 +#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 +#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 +#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 +#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 +#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 +#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 +#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 +#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 +#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 +#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 +#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 + + +#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF + + +// BIOS_4_SCRATCH Definition +#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL +#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L +#define ATOM_S4_LCD1_REFRESH_SHIFT 8 + +//Byte aligned defintion for BIOS usage +#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF +#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 +#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 + +// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! +#define ATOM_S5_DOS_REQ_CRT1b0 0x01 +#define ATOM_S5_DOS_REQ_LCD1b0 0x02 +#define ATOM_S5_DOS_REQ_TV1b0 0x04 +#define ATOM_S5_DOS_REQ_DFP1b0 0x08 +#define ATOM_S5_DOS_REQ_CRT2b0 0x10 +#define ATOM_S5_DOS_REQ_LCD2b0 0x20 +#define ATOM_S5_DOS_REQ_DFP6b0 0x40 +#define ATOM_S5_DOS_REQ_DFP2b0 0x80 +#define ATOM_S5_DOS_REQ_CVb1 0x01 +#define ATOM_S5_DOS_REQ_DFP3b1 0x02 +#define ATOM_S5_DOS_REQ_DFP4b1 0x04 +#define ATOM_S5_DOS_REQ_DFP5b1 0x08 + + +#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF + +#define ATOM_S5_DOS_REQ_CRT1 0x0001 +#define ATOM_S5_DOS_REQ_LCD1 0x0002 +#define ATOM_S5_DOS_REQ_TV1 0x0004 +#define ATOM_S5_DOS_REQ_DFP1 0x0008 +#define ATOM_S5_DOS_REQ_CRT2 0x0010 +#define ATOM_S5_DOS_REQ_LCD2 0x0020 +#define ATOM_S5_DOS_REQ_DFP6 0x0040 +#define ATOM_S5_DOS_REQ_DFP2 0x0080 +#define ATOM_S5_DOS_REQ_CV 0x0100 +#define ATOM_S5_DOS_REQ_DFP3 0x0200 +#define ATOM_S5_DOS_REQ_DFP4 0x0400 +#define ATOM_S5_DOS_REQ_DFP5 0x0800 + +#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 +#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 +#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 +#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 +#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ + (ATOM_S5_DOS_FORCE_CVb3<<8)) +// BIOS_6_SCRATCH Definition +#define ATOM_S6_DEVICE_CHANGE 0x00000001L +#define ATOM_S6_SCALER_CHANGE 0x00000002L +#define ATOM_S6_LID_CHANGE 0x00000004L +#define ATOM_S6_DOCKING_CHANGE 0x00000008L +#define ATOM_S6_ACC_MODE 0x00000010L +#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L +#define ATOM_S6_LID_STATE 0x00000040L +#define ATOM_S6_DOCK_STATE 0x00000080L +#define ATOM_S6_CRITICAL_STATE 0x00000100L +#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L +#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L +#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L +#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD +#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD + +#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion +#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion + +#define ATOM_S6_ACC_REQ_CRT1 0x00010000L +#define ATOM_S6_ACC_REQ_LCD1 0x00020000L +#define ATOM_S6_ACC_REQ_TV1 0x00040000L +#define ATOM_S6_ACC_REQ_DFP1 0x00080000L +#define ATOM_S6_ACC_REQ_CRT2 0x00100000L +#define ATOM_S6_ACC_REQ_LCD2 0x00200000L +#define ATOM_S6_ACC_REQ_DFP6 0x00400000L +#define ATOM_S6_ACC_REQ_DFP2 0x00800000L +#define ATOM_S6_ACC_REQ_CV 0x01000000L +#define ATOM_S6_ACC_REQ_DFP3 0x02000000L +#define ATOM_S6_ACC_REQ_DFP4 0x04000000L +#define ATOM_S6_ACC_REQ_DFP5 0x08000000L + +#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L +#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L +#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L +#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L +#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L + +//Byte aligned defintion for BIOS usage +#define ATOM_S6_DEVICE_CHANGEb0 0x01 +#define ATOM_S6_SCALER_CHANGEb0 0x02 +#define ATOM_S6_LID_CHANGEb0 0x04 +#define ATOM_S6_DOCKING_CHANGEb0 0x08 +#define ATOM_S6_ACC_MODEb0 0x10 +#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 +#define ATOM_S6_LID_STATEb0 0x40 +#define ATOM_S6_DOCK_STATEb0 0x80 +#define ATOM_S6_CRITICAL_STATEb1 0x01 +#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 +#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 +#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 +#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 +#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 + +#define ATOM_S6_ACC_REQ_CRT1b2 0x01 +#define ATOM_S6_ACC_REQ_LCD1b2 0x02 +#define ATOM_S6_ACC_REQ_TV1b2 0x04 +#define ATOM_S6_ACC_REQ_DFP1b2 0x08 +#define ATOM_S6_ACC_REQ_CRT2b2 0x10 +#define ATOM_S6_ACC_REQ_LCD2b2 0x20 +#define ATOM_S6_ACC_REQ_DFP6b2 0x40 +#define ATOM_S6_ACC_REQ_DFP2b2 0x80 +#define ATOM_S6_ACC_REQ_CVb3 0x01 +#define ATOM_S6_ACC_REQ_DFP3b3 0x02 +#define ATOM_S6_ACC_REQ_DFP4b3 0x04 +#define ATOM_S6_ACC_REQ_DFP5b3 0x08 + +#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 +#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 +#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 +#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 +#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 + +#define ATOM_S6_DEVICE_CHANGE_SHIFT 0 +#define ATOM_S6_SCALER_CHANGE_SHIFT 1 +#define ATOM_S6_LID_CHANGE_SHIFT 2 +#define ATOM_S6_DOCKING_CHANGE_SHIFT 3 +#define ATOM_S6_ACC_MODE_SHIFT 4 +#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 +#define ATOM_S6_LID_STATE_SHIFT 6 +#define ATOM_S6_DOCK_STATE_SHIFT 7 +#define ATOM_S6_CRITICAL_STATE_SHIFT 8 +#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 +#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 +#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 +#define ATOM_S6_REQ_SCALER_SHIFT 12 +#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 +#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 +#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 +#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 +#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 +#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 +#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 + +// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! +#define ATOM_S7_DOS_MODE_TYPEb0 0x03 +#define ATOM_S7_DOS_MODE_VGAb0 0x00 +#define ATOM_S7_DOS_MODE_VESAb0 0x01 +#define ATOM_S7_DOS_MODE_EXTb0 0x02 +#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C +#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 +#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 +#define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02 +#define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200 +#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF + +#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 + +// BIOS_8_SCRATCH Definition +#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF +#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 + +#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 +#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 + +// BIOS_9_SCRATCH Definition +#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK +#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF +#endif +#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK +#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 +#endif +#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT +#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 +#endif +#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT +#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 +#endif + + +#define ATOM_FLAG_SET 0x20 +#define ATOM_FLAG_CLEAR 0 +#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) +#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) + +#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) + +#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) + +#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) + +#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) + +#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) + +#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) +#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) + +#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) + +#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) + +#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) +#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) +#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) + +/****************************************************************************/ +//Portion II: Definitinos only used in Driver +/****************************************************************************/ + +// Macros used by driver + +#ifdef __cplusplus +#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast(&(static_cast(0))->FieldName)-static_cast(0))/sizeof(USHORT)) + +#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) +#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) +#else // not __cplusplus +#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) + +#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) +#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) +#endif // __cplusplus + +#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION +#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION + +/****************************************************************************/ +//Portion III: Definitinos only used in VBIOS +/****************************************************************************/ +#define ATOM_DAC_SRC 0x80 +#define ATOM_SRC_DAC1 0 +#define ATOM_SRC_DAC2 0x80 + + + +typedef struct _MEMORY_PLLINIT_PARAMETERS +{ + ULONG ulTargetMemoryClock; //In 10Khz unit + UCHAR ucAction; //not define yet + UCHAR ucFbDiv_Hi; //Fbdiv Hi byte + UCHAR ucFbDiv; //FB value + UCHAR ucPostDiv; //Post div +}MEMORY_PLLINIT_PARAMETERS; + +#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS + + +#define GPIO_PIN_WRITE 0x01 +#define GPIO_PIN_READ 0x00 + +typedef struct _GPIO_PIN_CONTROL_PARAMETERS +{ + UCHAR ucGPIO_ID; //return value, read from GPIO pins + UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update + UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask + UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write +}GPIO_PIN_CONTROL_PARAMETERS; + +typedef struct _ENABLE_SCALER_PARAMETERS +{ + UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 + UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION + UCHAR ucTVStandard; // + UCHAR ucPadding[1]; +}ENABLE_SCALER_PARAMETERS; +#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS + +//ucEnable: +#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 +#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 +#define SCALER_ENABLE_2TAP_ALPHA_MODE 2 +#define SCALER_ENABLE_MULTITAP_MODE 3 + +typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS +{ + ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position + UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset + UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset + UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE +}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; + +typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION +{ + ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; + ENABLE_CRTC_PARAMETERS sReserved; +}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; + +typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS +{ + USHORT usHight; // Image Hight + USHORT usWidth; // Image Width + UCHAR ucSurface; // Surface 1 or 2 + UCHAR ucPadding[3]; +}ENABLE_GRAPH_SURFACE_PARAMETERS; + +typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 +{ + USHORT usHight; // Image Hight + USHORT usWidth; // Image Width + UCHAR ucSurface; // Surface 1 or 2 + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[2]; +}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; + +typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 +{ + USHORT usHight; // Image Hight + USHORT usWidth; // Image Width + UCHAR ucSurface; // Surface 1 or 2 + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. +}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; + +typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 +{ + USHORT usHight; // Image Hight + USHORT usWidth; // Image Width + USHORT usGraphPitch; + UCHAR ucColorDepth; + UCHAR ucPixelFormat; + UCHAR ucSurface; // Surface 1 or 2 + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucModeType; + UCHAR ucReserved; +}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; + +// ucEnable +#define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f +#define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 + +typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION +{ + ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; + ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one +}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; + +typedef struct _MEMORY_CLEAN_UP_PARAMETERS +{ + USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address + USHORT usMemorySize; //8Kb blocks aligned +}MEMORY_CLEAN_UP_PARAMETERS; + +#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS + +typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS +{ + USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC + USHORT usY_Size; +}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; + +typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 +{ + union{ + USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC + USHORT usSurface; + }; + USHORT usY_Size; + USHORT usDispXStart; + USHORT usDispYStart; +}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; + + +typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 +{ + UCHAR ucLutId; + UCHAR ucAction; + USHORT usLutStartIndex; + USHORT usLutLength; + USHORT usLutOffsetInVram; +}PALETTE_DATA_CONTROL_PARAMETERS_V3; + +// ucAction: +#define PALETTE_DATA_AUTO_FILL 1 +#define PALETTE_DATA_READ 2 +#define PALETTE_DATA_WRITE 3 + + +typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 +{ + UCHAR ucInterruptId; + UCHAR ucServiceId; + UCHAR ucStatus; + UCHAR ucReserved; +}INTERRUPT_SERVICE_PARAMETER_V2; + +// ucInterruptId +#define HDP1_INTERRUPT_ID 1 +#define HDP2_INTERRUPT_ID 2 +#define HDP3_INTERRUPT_ID 3 +#define HDP4_INTERRUPT_ID 4 +#define HDP5_INTERRUPT_ID 5 +#define HDP6_INTERRUPT_ID 6 +#define SW_INTERRUPT_ID 11 + +// ucAction +#define INTERRUPT_SERVICE_GEN_SW_INT 1 +#define INTERRUPT_SERVICE_GET_STATUS 2 + + // ucStatus +#define INTERRUPT_STATUS__INT_TRIGGER 1 +#define INTERRUPT_STATUS__HPD_HIGH 2 + +typedef struct _EFUSE_INPUT_PARAMETER +{ + USHORT usEfuseIndex; + UCHAR ucBitShift; + UCHAR ucBitLength; +}EFUSE_INPUT_PARAMETER; + +// ReadEfuseValue command table input/output parameter +typedef union _READ_EFUSE_VALUE_PARAMETER +{ + EFUSE_INPUT_PARAMETER sEfuse; + ULONG ulEfuseValue; +}READ_EFUSE_VALUE_PARAMETER; + +typedef struct _INDIRECT_IO_ACCESS +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR IOAccessSequence[256]; +} INDIRECT_IO_ACCESS; + +#define INDIRECT_READ 0x00 +#define INDIRECT_WRITE 0x80 + +#define INDIRECT_IO_MM 0 +#define INDIRECT_IO_PLL 1 +#define INDIRECT_IO_MC 2 +#define INDIRECT_IO_PCIE 3 +#define INDIRECT_IO_PCIEP 4 +#define INDIRECT_IO_NBMISC 5 +#define INDIRECT_IO_SMU 5 + +#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ +#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE +#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ +#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE +#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ +#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE +#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ +#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE +#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ +#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE +#define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ +#define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE + + +typedef struct _ATOM_OEM_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; +}ATOM_OEM_INFO; + +typedef struct _ATOM_TV_MODE +{ + UCHAR ucVMode_Num; //Video mode number + UCHAR ucTV_Mode_Num; //Internal TV mode number +}ATOM_TV_MODE; + +typedef struct _ATOM_BIOS_INT_TVSTD_MODE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table + USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table + USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table + USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table + USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table +}ATOM_BIOS_INT_TVSTD_MODE; + + +typedef struct _ATOM_TV_MODE_SCALER_PTR +{ + USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients + USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients + UCHAR ucTV_Mode_Num; +}ATOM_TV_MODE_SCALER_PTR; + +typedef struct _ATOM_STANDARD_VESA_TIMING +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation +}ATOM_STANDARD_VESA_TIMING; + + +typedef struct _ATOM_STD_FORMAT +{ + USHORT usSTD_HDisp; + USHORT usSTD_VDisp; + USHORT usSTD_RefreshRate; + USHORT usReserved; +}ATOM_STD_FORMAT; + +typedef struct _ATOM_VESA_TO_EXTENDED_MODE +{ + USHORT usVESA_ModeNumber; + USHORT usExtendedModeNumber; +}ATOM_VESA_TO_EXTENDED_MODE; + +typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; +}ATOM_VESA_TO_INTENAL_MODE_LUT; + +/*************** ATOM Memory Related Data Structure ***********************/ +typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ + UCHAR ucMemoryType; + UCHAR ucMemoryVendor; + UCHAR ucAdjMCId; + UCHAR ucDynClkId; + ULONG ulDllResetClkRange; +}ATOM_MEMORY_VENDOR_BLOCK; + + +typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ +#if ATOM_BIG_ENDIAN + ULONG ucMemBlkId:8; + ULONG ulMemClockRange:24; +#else + ULONG ulMemClockRange:24; + ULONG ucMemBlkId:8; +#endif +}ATOM_MEMORY_SETTING_ID_CONFIG; + +typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS +{ + ATOM_MEMORY_SETTING_ID_CONFIG slAccess; + ULONG ulAccess; +}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; + + +typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ + ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; + ULONG aulMemData[1]; +}ATOM_MEMORY_SETTING_DATA_BLOCK; + + +typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ + USHORT usRegIndex; // MC register index + UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf +}ATOM_INIT_REG_INDEX_FORMAT; + + +typedef struct _ATOM_INIT_REG_BLOCK{ + USHORT usRegIndexTblSize; //size of asRegIndexBuf + USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK + ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; + ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; +}ATOM_INIT_REG_BLOCK; + +#define END_OF_REG_INDEX_BLOCK 0x0ffff +#define END_OF_REG_DATA_BLOCK 0x00000000 +#define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS +#define CLOCK_RANGE_HIGHEST 0x00ffffff + +#define VALUE_DWORD SIZEOF ULONG +#define VALUE_SAME_AS_ABOVE 0 +#define VALUE_MASK_DWORD 0x84 + +#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) +#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) +#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) +//#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code +#define ACCESS_PLACEHOLDER 0x80 + + +typedef struct _ATOM_MC_INIT_PARAM_TABLE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usAdjustARB_SEQDataOffset; + USHORT usMCInitMemTypeTblOffset; + USHORT usMCInitCommonTblOffset; + USHORT usMCInitPowerDownTblOffset; + ULONG ulARB_SEQDataBuf[32]; + ATOM_INIT_REG_BLOCK asMCInitMemType; + ATOM_INIT_REG_BLOCK asMCInitCommon; +}ATOM_MC_INIT_PARAM_TABLE; + + +typedef struct _ATOM_REG_INIT_SETTING +{ + USHORT usRegIndex; + ULONG ulRegValue; +}ATOM_REG_INIT_SETTING; + +typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulMCUcodeVersion; + ULONG ulMCUcodeRomStartAddr; + ULONG ulMCUcodeLength; + USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings. + USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY regsiter setting +}ATOM_MC_INIT_PARAM_TABLE_V2_1; + + +#define _4Mx16 0x2 +#define _4Mx32 0x3 +#define _8Mx16 0x12 +#define _8Mx32 0x13 +#define _8Mx128 0x15 +#define _16Mx16 0x22 +#define _16Mx32 0x23 +#define _16Mx128 0x25 +#define _32Mx16 0x32 +#define _32Mx32 0x33 +#define _32Mx128 0x35 +#define _64Mx32 0x43 +#define _64Mx8 0x41 +#define _64Mx16 0x42 +#define _128Mx8 0x51 +#define _128Mx16 0x52 +#define _128Mx32 0x53 +#define _256Mx8 0x61 +#define _256Mx16 0x62 +#define _512Mx8 0x71 + + +#define SAMSUNG 0x1 +#define INFINEON 0x2 +#define ELPIDA 0x3 +#define ETRON 0x4 +#define NANYA 0x5 +#define HYNIX 0x6 +#define MOSEL 0x7 +#define WINBOND 0x8 +#define ESMT 0x9 +#define MICRON 0xF + +#define QIMONDA INFINEON +#define PROMOS MOSEL +#define KRETON INFINEON +#define ELIXIR NANYA +#define MEZZA ELPIDA + + +/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// + +#define UCODE_ROM_START_ADDRESS 0x1b800 +#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode + +//uCode block header for reference + +typedef struct _MCuCodeHeader +{ + ULONG ulSignature; + UCHAR ucRevision; + UCHAR ucChecksum; + UCHAR ucReserved1; + UCHAR ucReserved2; + USHORT usParametersLength; + USHORT usUCodeLength; + USHORT usReserved1; + USHORT usReserved2; +} MCuCodeHeader; + +////////////////////////////////////////////////////////////////////////////////// + +#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 + +#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF +typedef struct _ATOM_VRAM_MODULE_V1 +{ + ULONG ulReserved; + USHORT usEMRSValue; + USHORT usMRSValue; + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender + UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... + UCHAR ucRow; // Number of Row,in power of 2; + UCHAR ucColumn; // Number of Column,in power of 2; + UCHAR ucBank; // Nunber of Bank; + UCHAR ucRank; // Number of Rank, in power of 2 + UCHAR ucChannelNum; // Number of channel; + UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 + UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; + UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; + UCHAR ucReserved[2]; +}ATOM_VRAM_MODULE_V1; + + +typedef struct _ATOM_VRAM_MODULE_V2 +{ + ULONG ulReserved; + ULONG ulFlags; // To enable/disable functionalities based on memory type + ULONG ulEngineClock; // Override of default engine clock for particular memory type + ULONG ulMemoryClock; // Override of default memory clock for particular memory type + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + USHORT usEMRSValue; + USHORT usMRSValue; + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed + UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... + UCHAR ucRow; // Number of Row,in power of 2; + UCHAR ucColumn; // Number of Column,in power of 2; + UCHAR ucBank; // Nunber of Bank; + UCHAR ucRank; // Number of Rank, in power of 2 + UCHAR ucChannelNum; // Number of channel; + UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 + UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; + UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; + UCHAR ucRefreshRateFactor; + UCHAR ucReserved[3]; +}ATOM_VRAM_MODULE_V2; + + +typedef struct _ATOM_MEMORY_TIMING_FORMAT +{ + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + union{ + USHORT usMRS; // mode register + USHORT usDDR3_MR0; + }; + union{ + USHORT usEMRS; // extended mode register + USHORT usDDR3_MR1; + }; + UCHAR ucCL; // CAS latency + UCHAR ucWL; // WRITE Latency + UCHAR uctRAS; // tRAS + UCHAR uctRC; // tRC + UCHAR uctRFC; // tRFC + UCHAR uctRCDR; // tRCDR + UCHAR uctRCDW; // tRCDW + UCHAR uctRP; // tRP + UCHAR uctRRD; // tRRD + UCHAR uctWR; // tWR + UCHAR uctWTR; // tWTR + UCHAR uctPDIX; // tPDIX + UCHAR uctFAW; // tFAW + UCHAR uctAOND; // tAOND + union + { + struct { + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon + UCHAR ucReserved; + }; + USHORT usDDR3_MR2; + }; +}ATOM_MEMORY_TIMING_FORMAT; + + +typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 +{ + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + USHORT usMRS; // mode register + USHORT usEMRS; // extended mode register + UCHAR ucCL; // CAS latency + UCHAR ucWL; // WRITE Latency + UCHAR uctRAS; // tRAS + UCHAR uctRC; // tRC + UCHAR uctRFC; // tRFC + UCHAR uctRCDR; // tRCDR + UCHAR uctRCDW; // tRCDW + UCHAR uctRP; // tRP + UCHAR uctRRD; // tRRD + UCHAR uctWR; // tWR + UCHAR uctWTR; // tWTR + UCHAR uctPDIX; // tPDIX + UCHAR uctFAW; // tFAW + UCHAR uctAOND; // tAOND + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon +////////////////////////////////////GDDR parameters/////////////////////////////////// + UCHAR uctCCDL; // + UCHAR uctCRCRL; // + UCHAR uctCRCWL; // + UCHAR uctCKE; // + UCHAR uctCKRSE; // + UCHAR uctCKRSX; // + UCHAR uctFAW32; // + UCHAR ucMR5lo; // + UCHAR ucMR5hi; // + UCHAR ucTerminator; +}ATOM_MEMORY_TIMING_FORMAT_V1; + + + + +typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 +{ + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + USHORT usMRS; // mode register + USHORT usEMRS; // extended mode register + UCHAR ucCL; // CAS latency + UCHAR ucWL; // WRITE Latency + UCHAR uctRAS; // tRAS + UCHAR uctRC; // tRC + UCHAR uctRFC; // tRFC + UCHAR uctRCDR; // tRCDR + UCHAR uctRCDW; // tRCDW + UCHAR uctRP; // tRP + UCHAR uctRRD; // tRRD + UCHAR uctWR; // tWR + UCHAR uctWTR; // tWTR + UCHAR uctPDIX; // tPDIX + UCHAR uctFAW; // tFAW + UCHAR uctAOND; // tAOND + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon +////////////////////////////////////GDDR parameters/////////////////////////////////// + UCHAR uctCCDL; // + UCHAR uctCRCRL; // + UCHAR uctCRCWL; // + UCHAR uctCKE; // + UCHAR uctCKRSE; // + UCHAR uctCKRSX; // + UCHAR uctFAW32; // + UCHAR ucMR4lo; // + UCHAR ucMR4hi; // + UCHAR ucMR5lo; // + UCHAR ucMR5hi; // + UCHAR ucTerminator; + UCHAR ucReserved; +}ATOM_MEMORY_TIMING_FORMAT_V2; + + +typedef struct _ATOM_MEMORY_FORMAT +{ + ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock + union{ + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usDDR3_Reserved; // Not used for DDR3 memory + }; + union{ + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + USHORT usDDR3_MR3; // Used for DDR3 memory + }; + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed + UCHAR ucRow; // Number of Row,in power of 2; + UCHAR ucColumn; // Number of Column,in power of 2; + UCHAR ucBank; // Nunber of Bank; + UCHAR ucRank; // Number of Rank, in power of 2 + UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 + UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) + UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms + UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 + UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble + UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc + ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; // Memory Timing block sort from lower clock to higher clock +}ATOM_MEMORY_FORMAT; + + +typedef struct _ATOM_VRAM_MODULE_V3 +{ + ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination + USHORT usSize; // size of ATOM_VRAM_MODULE_V3 + USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage + USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucChannelNum; // board dependent parameter:Number of channel; + UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit + UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv + UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters + UCHAR ucFlag; // To enable/disable functionalities based on memory type + ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec +}ATOM_VRAM_MODULE_V3; + + +//ATOM_VRAM_MODULE_V3.ucNPL_RT +#define NPL_RT_MASK 0x0f +#define BATTERY_ODT_MASK 0xc0 + +#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 + +typedef struct _ATOM_VRAM_MODULE_V4 +{ + ULONG ulChannelMapCfg; // board dependent parameter: Channel combination + USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE + USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; + UCHAR ucChannelNum; // Number of channels present in this module config + UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits + UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 + UCHAR ucFlag; // To enable/disable functionalities based on memory type + UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 + UCHAR ucVREFI; // board dependent parameter + UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters + UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble + UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros + UCHAR ucReserved[3]; + +//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level + union{ + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usDDR3_Reserved; + }; + union{ + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + USHORT usDDR3_MR3; // Used for DDR3 memory + }; + UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed + UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) + UCHAR ucReserved2[2]; + ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock +}ATOM_VRAM_MODULE_V4; + +#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 +#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 +#define VRAM_MODULE_V4_MISC_BL_MASK 0x4 +#define VRAM_MODULE_V4_MISC_BL8 0x4 +#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 + +typedef struct _ATOM_VRAM_MODULE_V5 +{ + ULONG ulChannelMapCfg; // board dependent parameter: Channel combination + USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE + USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; + UCHAR ucChannelNum; // Number of channels present in this module config + UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits + UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 + UCHAR ucFlag; // To enable/disable functionalities based on memory type + UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 + UCHAR ucVREFI; // board dependent parameter + UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters + UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble + UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros + UCHAR ucReserved[3]; + +//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed + UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) + UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth + UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth + ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock +}ATOM_VRAM_MODULE_V5; + + +typedef struct _ATOM_VRAM_MODULE_V6 +{ + ULONG ulChannelMapCfg; // board dependent parameter: Channel combination + USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE + USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; + UCHAR ucChannelNum; // Number of channels present in this module config + UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits + UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 + UCHAR ucFlag; // To enable/disable functionalities based on memory type + UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 + UCHAR ucVREFI; // board dependent parameter + UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters + UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble + UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! + // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros + UCHAR ucReserved[3]; + +//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed + UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) + UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth + UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth + ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock +}ATOM_VRAM_MODULE_V6; + +typedef struct _ATOM_VRAM_MODULE_V7 +{ +// Design Specific Values + ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP + USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 + USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) + USHORT usEnableChannels; // bit vector which indicate which channels are enabled + UCHAR ucExtMemoryID; // Current memory module ID + UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 + UCHAR ucChannelNum; // Number of mem. channels supported in this module + UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT + UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 + UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used. + UCHAR ucMisc; // RANK_OF_THISMEMORY etc. + UCHAR ucVREFI; // Not used. + UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. + UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble + UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros + USHORT usSEQSettingOffset; + UCHAR ucReserved; +// Memory Module specific values + USHORT usEMRS2Value; // EMRS2/MR2 Value. + USHORT usEMRS3Value; // EMRS3/MR3 Value. + UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code + UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) + UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory + UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth + char strMemPNString[20]; // part number end with '0'. +}ATOM_VRAM_MODULE_V7; + + +typedef struct _ATOM_VRAM_MODULE_V8 +{ +// Design Specific Values + ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP + USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 + USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) + USHORT usEnableChannels; // bit vector which indicate which channels are enabled + UCHAR ucExtMemoryID; // Current memory module ID + UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 + UCHAR ucChannelNum; // Number of mem. channels supported in this module + UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT + UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 + UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit ) + UCHAR ucMisc; // RANK_OF_THISMEMORY etc. + UCHAR ucVREFI; // Not used. + USHORT usReserved; // Not used + USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros + UCHAR ucMcTunningSetId; // MC phy registers set per. + UCHAR ucRowNum; +// Memory Module specific values + USHORT usEMRS2Value; // EMRS2/MR2 Value. + USHORT usEMRS3Value; // EMRS3/MR3 Value. + UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code + UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) + UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory + UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth + + ULONG ulChannelMapCfg1; // channel mapping for channel8~15 + ULONG ulBankMapCfg; + ULONG ulReserved; + char strMemPNString[20]; // part number end with '0'. +}ATOM_VRAM_MODULE_V8; + + +typedef struct _ATOM_VRAM_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucNumOfVRAMModule; + ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; +}ATOM_VRAM_INFO_V2; + +typedef struct _ATOM_VRAM_INFO_V3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting + USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting + USHORT usRerseved; + UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator + UCHAR ucNumOfVRAMModule; + ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; + ATOM_INIT_REG_BLOCK asMemPatch; // for allocation + +}ATOM_VRAM_INFO_V3; + +#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 + +typedef struct _ATOM_VRAM_INFO_V4 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting + USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting + USHORT usRerseved; + UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 + ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] + UCHAR ucReservde[4]; + UCHAR ucNumOfVRAMModule; + ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; + ATOM_INIT_REG_BLOCK asMemPatch; // for allocation +}ATOM_VRAM_INFO_V4; + +typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting + USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting + USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings + USHORT usReserved[3]; + UCHAR ucNumOfVRAMModule; // indicate number of VRAM module + UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list + UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version + UCHAR ucReserved; + ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; +}ATOM_VRAM_INFO_HEADER_V2_1; + +typedef struct _ATOM_VRAM_INFO_HEADER_V2_2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting + USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting + USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings + USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set + USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping + USHORT usReserved1; + UCHAR ucNumOfVRAMModule; // indicate number of VRAM module + UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list + UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version + UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset + ATOM_VRAM_MODULE_V8 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; +}ATOM_VRAM_INFO_HEADER_V2_2; + + +typedef struct _ATOM_DRAM_DATA_REMAP +{ + UCHAR ucByteRemapCh0; + UCHAR ucByteRemapCh1; + ULONG ulByte0BitRemapCh0; + ULONG ulByte1BitRemapCh0; + ULONG ulByte2BitRemapCh0; + ULONG ulByte3BitRemapCh0; + ULONG ulByte0BitRemapCh1; + ULONG ulByte1BitRemapCh1; + ULONG ulByte2BitRemapCh1; + ULONG ulByte3BitRemapCh1; +}ATOM_DRAM_DATA_REMAP; + +typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator +}ATOM_VRAM_GPIO_DETECTION_INFO; + + +typedef struct _ATOM_MEMORY_TRAINING_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucTrainingLoop; + UCHAR ucReserved[3]; + ATOM_INIT_REG_BLOCK asMemTrainingSetting; +}ATOM_MEMORY_TRAINING_INFO; + + +typedef struct SW_I2C_CNTL_DATA_PARAMETERS +{ + UCHAR ucControl; + UCHAR ucData; + UCHAR ucSatus; + UCHAR ucTemp; +} SW_I2C_CNTL_DATA_PARAMETERS; + +#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS + +typedef struct _SW_I2C_IO_DATA_PARAMETERS +{ + USHORT GPIO_Info; + UCHAR ucAct; + UCHAR ucData; + } SW_I2C_IO_DATA_PARAMETERS; + +#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS + +/****************************SW I2C CNTL DEFINITIONS**********************/ +#define SW_I2C_IO_RESET 0 +#define SW_I2C_IO_GET 1 +#define SW_I2C_IO_DRIVE 2 +#define SW_I2C_IO_SET 3 +#define SW_I2C_IO_START 4 + +#define SW_I2C_IO_CLOCK 0 +#define SW_I2C_IO_DATA 0x80 + +#define SW_I2C_IO_ZERO 0 +#define SW_I2C_IO_ONE 0x100 + +#define SW_I2C_CNTL_READ 0 +#define SW_I2C_CNTL_WRITE 1 +#define SW_I2C_CNTL_START 2 +#define SW_I2C_CNTL_STOP 3 +#define SW_I2C_CNTL_OPEN 4 +#define SW_I2C_CNTL_CLOSE 5 +#define SW_I2C_CNTL_WRITE1BIT 6 + +//==============================VESA definition Portion=============================== +#define VESA_OEM_PRODUCT_REV '01.00' +#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support +#define VESA_MODE_WIN_ATTRIBUTE 7 +#define VESA_WIN_SIZE 64 + +typedef struct _PTR_32_BIT_STRUCTURE +{ + USHORT Offset16; + USHORT Segment16; +} PTR_32_BIT_STRUCTURE; + +typedef union _PTR_32_BIT_UNION +{ + PTR_32_BIT_STRUCTURE SegmentOffset; + ULONG Ptr32_Bit; +} PTR_32_BIT_UNION; + +typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE +{ + UCHAR VbeSignature[4]; + USHORT VbeVersion; + PTR_32_BIT_UNION OemStringPtr; + UCHAR Capabilities[4]; + PTR_32_BIT_UNION VideoModePtr; + USHORT TotalMemory; +} VBE_1_2_INFO_BLOCK_UPDATABLE; + + +typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE +{ + VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; + USHORT OemSoftRev; + PTR_32_BIT_UNION OemVendorNamePtr; + PTR_32_BIT_UNION OemProductNamePtr; + PTR_32_BIT_UNION OemProductRevPtr; +} VBE_2_0_INFO_BLOCK_UPDATABLE; + +typedef union _VBE_VERSION_UNION +{ + VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; + VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; +} VBE_VERSION_UNION; + +typedef struct _VBE_INFO_BLOCK +{ + VBE_VERSION_UNION UpdatableVBE_Info; + UCHAR Reserved[222]; + UCHAR OemData[256]; +} VBE_INFO_BLOCK; + +typedef struct _VBE_FP_INFO +{ + USHORT HSize; + USHORT VSize; + USHORT FPType; + UCHAR RedBPP; + UCHAR GreenBPP; + UCHAR BlueBPP; + UCHAR ReservedBPP; + ULONG RsvdOffScrnMemSize; + ULONG RsvdOffScrnMEmPtr; + UCHAR Reserved[14]; +} VBE_FP_INFO; + +typedef struct _VESA_MODE_INFO_BLOCK +{ +// Mandatory information for all VBE revisions + USHORT ModeAttributes; // dw ? ; mode attributes + UCHAR WinAAttributes; // db ? ; window A attributes + UCHAR WinBAttributes; // db ? ; window B attributes + USHORT WinGranularity; // dw ? ; window granularity + USHORT WinSize; // dw ? ; window size + USHORT WinASegment; // dw ? ; window A start segment + USHORT WinBSegment; // dw ? ; window B start segment + ULONG WinFuncPtr; // dd ? ; real mode pointer to window function + USHORT BytesPerScanLine;// dw ? ; bytes per scan line + +//; Mandatory information for VBE 1.2 and above + USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters + USHORT YResolution; // dw ? ; vertical resolution in pixels or characters + UCHAR XCharSize; // db ? ; character cell width in pixels + UCHAR YCharSize; // db ? ; character cell height in pixels + UCHAR NumberOfPlanes; // db ? ; number of memory planes + UCHAR BitsPerPixel; // db ? ; bits per pixel + UCHAR NumberOfBanks; // db ? ; number of banks + UCHAR MemoryModel; // db ? ; memory model type + UCHAR BankSize; // db ? ; bank size in KB + UCHAR NumberOfImagePages;// db ? ; number of images + UCHAR ReservedForPageFunction;//db 1 ; reserved for page function + +//; Direct Color fields(required for direct/6 and YUV/7 memory models) + UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits + UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask + UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits + UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask + UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits + UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask + UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits + UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask + UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes + +//; Mandatory information for VBE 2.0 and above + ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer + ULONG Reserved_1; // dd 0 ; reserved - always set to 0 + USHORT Reserved_2; // dw 0 ; reserved - always set to 0 + +//; Mandatory information for VBE 3.0 and above + USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes + UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes + UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes + UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) + UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) + UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) + UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) + UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) + UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) + UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) + UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) + ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode + UCHAR Reserved; // db 190 dup (0) +} VESA_MODE_INFO_BLOCK; + +// BIOS function CALLS +#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code +#define ATOM_BIOS_FUNCTION_COP_MODE 0x00 +#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 +#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 +#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 +#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B +#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E +#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F +#define ATOM_BIOS_FUNCTION_STV_STD 0x16 +#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 +#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 + +#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 +#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 +#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 +#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A +#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B +#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 +#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 + +#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D +#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E +#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F +#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 +#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 +#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state +#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state +#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 +#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 +#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported + + +#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS +#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 +#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 +#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. +#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY +#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND +#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF +#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) + +#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L +#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L +#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL + +// structure used for VBIOS only + +//DispOutInfoTable +typedef struct _ASIC_TRANSMITTER_INFO +{ + USHORT usTransmitterObjId; + USHORT usSupportDevice; + UCHAR ucTransmitterCmdTblId; + UCHAR ucConfig; + UCHAR ucEncoderID; //available 1st encoder ( default ) + UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) + UCHAR uc2ndEncoderID; + UCHAR ucReserved; +}ASIC_TRANSMITTER_INFO; + +#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 +#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 +#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 +#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 +#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 +#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 +#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 +#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 +#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 + +typedef struct _ASIC_ENCODER_INFO +{ + UCHAR ucEncoderID; + UCHAR ucEncoderConfig; + USHORT usEncoderCmdTblId; +}ASIC_ENCODER_INFO; + +typedef struct _ATOM_DISP_OUT_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT ptrTransmitterInfo; + USHORT ptrEncoderInfo; + ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; + ASIC_ENCODER_INFO asEncoderInfo[1]; +}ATOM_DISP_OUT_INFO; + + +typedef struct _ATOM_DISP_OUT_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT ptrTransmitterInfo; + USHORT ptrEncoderInfo; + USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. + ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; + ASIC_ENCODER_INFO asEncoderInfo[1]; +}ATOM_DISP_OUT_INFO_V2; + + +typedef struct _ATOM_DISP_CLOCK_ID { + UCHAR ucPpllId; + UCHAR ucPpllAttribute; +}ATOM_DISP_CLOCK_ID; + +// ucPpllAttribute +#define CLOCK_SOURCE_SHAREABLE 0x01 +#define CLOCK_SOURCE_DP_MODE 0x02 +#define CLOCK_SOURCE_NONE_DP_MODE 0x04 + +//DispOutInfoTable +typedef struct _ASIC_TRANSMITTER_INFO_V2 +{ + USHORT usTransmitterObjId; + USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object + UCHAR ucTransmitterCmdTblId; + UCHAR ucConfig; + UCHAR ucEncoderID; // available 1st encoder ( default ) + UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) + UCHAR uc2ndEncoderID; + UCHAR ucReserved; +}ASIC_TRANSMITTER_INFO_V2; + +typedef struct _ATOM_DISP_OUT_INFO_V3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT ptrTransmitterInfo; + USHORT ptrEncoderInfo; + USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. + USHORT usReserved; + UCHAR ucDCERevision; + UCHAR ucMaxDispEngineNum; + UCHAR ucMaxActiveDispEngineNum; + UCHAR ucMaxPPLLNum; + UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE + UCHAR ucDispCaps; + UCHAR ucReserved[2]; + ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only +}ATOM_DISP_OUT_INFO_V3; + +//ucDispCaps +#define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01 +#define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02 + +typedef enum CORE_REF_CLK_SOURCE{ + CLOCK_SRC_XTALIN=0, + CLOCK_SRC_XO_IN=1, + CLOCK_SRC_XO_IN2=2, +}CORE_REF_CLK_SOURCE; + +// DispDevicePriorityInfo +typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT asDevicePriority[16]; +}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; + +//ProcessAuxChannelTransactionTable +typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS +{ + USHORT lpAuxRequest; + USHORT lpDataOut; + UCHAR ucChannelID; + union + { + UCHAR ucReplyStatus; + UCHAR ucDelay; + }; + UCHAR ucDataOutLen; + UCHAR ucReserved; +}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; + +//ProcessAuxChannelTransactionTable +typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 +{ + USHORT lpAuxRequest; + USHORT lpDataOut; + UCHAR ucChannelID; + union + { + UCHAR ucReplyStatus; + UCHAR ucDelay; + }; + UCHAR ucDataOutLen; + UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 +}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; + +#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS + +//GetSinkType + +typedef struct _DP_ENCODER_SERVICE_PARAMETERS +{ + USHORT ucLinkClock; + union + { + UCHAR ucConfig; // for DP training command + UCHAR ucI2cId; // use for GET_SINK_TYPE command + }; + UCHAR ucAction; + UCHAR ucStatus; + UCHAR ucLaneNum; + UCHAR ucReserved[2]; +}DP_ENCODER_SERVICE_PARAMETERS; + +// ucAction +#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 + +#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS + + +typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 +{ + USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION + UCHAR ucAuxId; + UCHAR ucAction; + UCHAR ucSinkType; // Iput and Output parameters. + UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION + UCHAR ucReserved[2]; +}DP_ENCODER_SERVICE_PARAMETERS_V2; + +typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 +{ + DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; + PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; +}DP_ENCODER_SERVICE_PS_ALLOCATION_V2; + +// ucAction +#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 +#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 + + +// DP_TRAINING_TABLE +#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR +#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) +#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) +#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) +#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) +#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) +#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) +#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) +#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) +#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) +#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) +#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) +#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) + + +typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS +{ + UCHAR ucI2CSpeed; + union + { + UCHAR ucRegIndex; + UCHAR ucStatus; + }; + USHORT lpI2CDataOut; + UCHAR ucFlag; + UCHAR ucTransBytes; + UCHAR ucSlaveAddr; + UCHAR ucLineNumber; +}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; + +#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS + +//ucFlag +#define HW_I2C_WRITE 1 +#define HW_I2C_READ 0 +#define I2C_2BYTE_ADDR 0x02 + +/****************************************************************************/ +// Structures used by HW_Misc_OperationTable +/****************************************************************************/ +typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 +{ + UCHAR ucCmd; // Input: To tell which action to take + UCHAR ucReserved[3]; + ULONG ulReserved; +}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; + +typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 +{ + UCHAR ucReturnCode; // Output: Return value base on action was taken + UCHAR ucReserved[3]; + ULONG ulReserved; +}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; + +// Actions code +#define ATOM_GET_SDI_SUPPORT 0xF0 + +// Return code +#define ATOM_UNKNOWN_CMD 0 +#define ATOM_FEATURE_NOT_SUPPORTED 1 +#define ATOM_FEATURE_SUPPORTED 2 + +typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION +{ + ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; + PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; +}ATOM_HW_MISC_OPERATION_PS_ALLOCATION; + +/****************************************************************************/ + +typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 +{ + UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... + UCHAR ucReserved[3]; +}SET_HWBLOCK_INSTANCE_PARAMETER_V2; + +#define HWBLKINST_INSTANCE_MASK 0x07 +#define HWBLKINST_HWBLK_MASK 0xF0 +#define HWBLKINST_HWBLK_SHIFT 0x04 + +//ucHWBlock +#define SELECT_DISP_ENGINE 0 +#define SELECT_DISP_PLL 1 +#define SELECT_DCIO_UNIPHY_LINK0 2 +#define SELECT_DCIO_UNIPHY_LINK1 3 +#define SELECT_DCIO_IMPCAL 4 +#define SELECT_DCIO_DIG 6 +#define SELECT_CRTC_PIXEL_RATE 7 +#define SELECT_VGA_BLK 8 + +// DIGTransmitterInfoTable structure used to program UNIPHY settings +typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock + USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info + USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range + USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info + USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings +}DIG_TRANSMITTER_INFO_HEADER_V3_1; + +typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock + USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info + USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range + USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info + USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings + USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info + USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings +}DIG_TRANSMITTER_INFO_HEADER_V3_2; + + +typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock + USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info + USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range + USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info + USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings + USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info + USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings + USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock + USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock + USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock + USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock + USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock + USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock +}DIG_TRANSMITTER_INFO_HEADER_V3_3; + + +typedef struct _CLOCK_CONDITION_REGESTER_INFO{ + USHORT usRegisterIndex; + UCHAR ucStartBit; + UCHAR ucEndBit; +}CLOCK_CONDITION_REGESTER_INFO; + +typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ + USHORT usMaxClockFreq; + UCHAR ucEncodeMode; + UCHAR ucPhySel; + ULONG ulAnalogSetting[1]; +}CLOCK_CONDITION_SETTING_ENTRY; + +typedef struct _CLOCK_CONDITION_SETTING_INFO{ + USHORT usEntrySize; + CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; +}CLOCK_CONDITION_SETTING_INFO; + +typedef struct _PHY_CONDITION_REG_VAL{ + ULONG ulCondition; + ULONG ulRegVal; +}PHY_CONDITION_REG_VAL; + +typedef struct _PHY_CONDITION_REG_VAL_V2{ + ULONG ulCondition; + UCHAR ucCondition2; + ULONG ulRegVal; +}PHY_CONDITION_REG_VAL_V2; + +typedef struct _PHY_CONDITION_REG_INFO{ + USHORT usRegIndex; + USHORT usSize; + PHY_CONDITION_REG_VAL asRegVal[1]; +}PHY_CONDITION_REG_INFO; + +typedef struct _PHY_CONDITION_REG_INFO_V2{ + USHORT usRegIndex; + USHORT usSize; + PHY_CONDITION_REG_VAL_V2 asRegVal[1]; +}PHY_CONDITION_REG_INFO_V2; + +typedef struct _PHY_ANALOG_SETTING_INFO{ + UCHAR ucEncodeMode; + UCHAR ucPhySel; + USHORT usSize; + PHY_CONDITION_REG_INFO asAnalogSetting[1]; +}PHY_ANALOG_SETTING_INFO; + +typedef struct _PHY_ANALOG_SETTING_INFO_V2{ + UCHAR ucEncodeMode; + UCHAR ucPhySel; + USHORT usSize; + PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1]; +}PHY_ANALOG_SETTING_INFO_V2; + + +typedef struct _GFX_HAVESTING_PARAMETERS { + UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM + UCHAR ucReserved; //reserved + UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array + UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array +} GFX_HAVESTING_PARAMETERS; + +//ucGfxBlkId +#define GFX_HARVESTING_CU_ID 0 +#define GFX_HARVESTING_RB_ID 1 +#define GFX_HARVESTING_PRIM_ID 2 + + +typedef struct _VBIOS_ROM_HEADER{ + UCHAR PciRomSignature[2]; + UCHAR ucPciRomSizeIn512bytes; + UCHAR ucJumpCoreMainInitBIOS; + USHORT usLabelCoreMainInitBIOS; + UCHAR PciReservedSpace[18]; + USHORT usPciDataStructureOffset; + UCHAR Rsvd1d_1a[4]; + char strIbm[3]; + UCHAR CheckSum[14]; + UCHAR ucBiosMsgNumber; + char str761295520[16]; + USHORT usLabelCoreVPOSTNoMode; + USHORT usSpecialPostOffset; + UCHAR ucSpeicalPostImageSizeIn512Bytes; + UCHAR Rsved47_45[3]; + USHORT usROM_HeaderInformationTableOffset; + UCHAR Rsved4f_4a[6]; + char strBuildTimeStamp[20]; + UCHAR ucJumpCoreXFuncFarHandler; + USHORT usCoreXFuncFarHandlerOffset; + UCHAR ucRsved67; + UCHAR ucJumpCoreVFuncFarHandler; + USHORT usCoreVFuncFarHandlerOffset; + UCHAR Rsved6d_6b[3]; + USHORT usATOM_BIOS_MESSAGE_Offset; +}VBIOS_ROM_HEADER; + +/****************************************************************************/ +//Portion VI: Definitinos for vbios MC scratch registers that driver used +/****************************************************************************/ + +#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 +#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 +#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 +#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 +#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 +#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 +#define MC_MISC0__MEMORY_TYPE__HBM 0x60000000 +#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 + +#define ATOM_MEM_TYPE_DDR_STRING "DDR" +#define ATOM_MEM_TYPE_DDR2_STRING "DDR2" +#define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3" +#define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4" +#define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5" +#define ATOM_MEM_TYPE_HBM_STRING "HBM" +#define ATOM_MEM_TYPE_DDR3_STRING "DDR3" + +/****************************************************************************/ +//Portion VII: Definitinos being oboselete +/****************************************************************************/ + +//========================================================================================== +//Remove the definitions below when driver is ready! +typedef struct _ATOM_DAC_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMaxFrequency; // in 10kHz unit + USHORT usReserved; +}ATOM_DAC_INFO; + + +typedef struct _COMPASSIONATE_DATA +{ + ATOM_COMMON_TABLE_HEADER sHeader; + + //============================== DAC1 portion + UCHAR ucDAC1_BG_Adjustment; + UCHAR ucDAC1_DAC_Adjustment; + USHORT usDAC1_FORCE_Data; + //============================== DAC2 portion + UCHAR ucDAC2_CRT2_BG_Adjustment; + UCHAR ucDAC2_CRT2_DAC_Adjustment; + USHORT usDAC2_CRT2_FORCE_Data; + USHORT usDAC2_CRT2_MUX_RegisterIndex; + UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low + UCHAR ucDAC2_NTSC_BG_Adjustment; + UCHAR ucDAC2_NTSC_DAC_Adjustment; + USHORT usDAC2_TV1_FORCE_Data; + USHORT usDAC2_TV1_MUX_RegisterIndex; + UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low + UCHAR ucDAC2_CV_BG_Adjustment; + UCHAR ucDAC2_CV_DAC_Adjustment; + USHORT usDAC2_CV_FORCE_Data; + USHORT usDAC2_CV_MUX_RegisterIndex; + UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low + UCHAR ucDAC2_PAL_BG_Adjustment; + UCHAR ucDAC2_PAL_DAC_Adjustment; + USHORT usDAC2_TV2_FORCE_Data; +}COMPASSIONATE_DATA; + +/****************************Supported Device Info Table Definitions**********************/ +// ucConnectInfo: +// [7:4] - connector type +// = 1 - VGA connector +// = 2 - DVI-I +// = 3 - DVI-D +// = 4 - DVI-A +// = 5 - SVIDEO +// = 6 - COMPOSITE +// = 7 - LVDS +// = 8 - DIGITAL LINK +// = 9 - SCART +// = 0xA - HDMI_type A +// = 0xB - HDMI_type B +// = 0xE - Special case1 (DVI+DIN) +// Others=TBD +// [3:0] - DAC Associated +// = 0 - no DAC +// = 1 - DACA +// = 2 - DACB +// = 3 - External DAC +// Others=TBD +// + +typedef struct _ATOM_CONNECTOR_INFO +{ +#if ATOM_BIG_ENDIAN + UCHAR bfConnectorType:4; + UCHAR bfAssociatedDAC:4; +#else + UCHAR bfAssociatedDAC:4; + UCHAR bfConnectorType:4; +#endif +}ATOM_CONNECTOR_INFO; + +typedef union _ATOM_CONNECTOR_INFO_ACCESS +{ + ATOM_CONNECTOR_INFO sbfAccess; + UCHAR ucAccess; +}ATOM_CONNECTOR_INFO_ACCESS; + +typedef struct _ATOM_CONNECTOR_INFO_I2C +{ + ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; +}ATOM_CONNECTOR_INFO_I2C; + + +typedef struct _ATOM_SUPPORTED_DEVICES_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; +}ATOM_SUPPORTED_DEVICES_INFO; + +#define NO_INT_SRC_MAPPED 0xFF + +typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP +{ + UCHAR ucIntSrcBitmap; +}ATOM_CONNECTOR_INC_SRC_BITMAP; + +typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; + ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; +}ATOM_SUPPORTED_DEVICES_INFO_2; + +typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; + ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; +}ATOM_SUPPORTED_DEVICES_INFO_2d1; + +#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 + + + +typedef struct _ATOM_MISC_CONTROL_INFO +{ + USHORT usFrequency; + UCHAR ucPLL_ChargePump; // PLL charge-pump gain control + UCHAR ucPLL_DutyCycle; // PLL duty cycle control + UCHAR ucPLL_VCO_Gain; // PLL VCO gain control + UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control +}ATOM_MISC_CONTROL_INFO; + + +#define ATOM_MAX_MISC_INFO 4 + +typedef struct _ATOM_TMDS_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMaxFrequency; // in 10Khz + ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; +}ATOM_TMDS_INFO; + + +typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE +{ + UCHAR ucTVStandard; //Same as TV standards defined above, + UCHAR ucPadding[1]; +}ATOM_ENCODER_ANALOG_ATTRIBUTE; + +typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE +{ + UCHAR ucAttribute; //Same as other digital encoder attributes defined above + UCHAR ucPadding[1]; +}ATOM_ENCODER_DIGITAL_ATTRIBUTE; + +typedef union _ATOM_ENCODER_ATTRIBUTE +{ + ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; + ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; +}ATOM_ENCODER_ATTRIBUTE; + + +typedef struct _DVO_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; + USHORT usEncoderID; + UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. + UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT + ATOM_ENCODER_ATTRIBUTE usDevAttr; +}DVO_ENCODER_CONTROL_PARAMETERS; + +typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION +{ + DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion +}DVO_ENCODER_CONTROL_PS_ALLOCATION; + + +#define ATOM_XTMDS_ASIC_SI164_ID 1 +#define ATOM_XTMDS_ASIC_SI178_ID 2 +#define ATOM_XTMDS_ASIC_TFP513_ID 3 +#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 +#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 +#define ATOM_XTMDS_MVPU_FPGA 0x00000004 + + +typedef struct _ATOM_XTMDS_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usSingleLinkMaxFrequency; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip + UCHAR ucXtransimitterID; + UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported + UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters + // due to design. This ID is used to alert driver that the sequence is not "standard"! + UCHAR ucMasterAddress; // Address to control Master xTMDS Chip + UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip +}ATOM_XTMDS_INFO; + +typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off + UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... + UCHAR ucPadding[2]; +}DFP_DPMS_STATUS_CHANGE_PARAMETERS; + +/****************************Legacy Power Play Table Definitions **********************/ + +//Definitions for ulPowerPlayMiscInfo +#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L +#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L +#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L + +#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L +#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L + +#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L + +#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L +#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L +#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program + +#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L +#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L +#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L +#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L +#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L +#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L +#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L + +#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L +#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L +#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L +#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L +#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L + +#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved +#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 + +#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L +#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L +#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L +#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic +#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic +#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode + +#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) +#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 +#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L + +#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L +#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L +#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L +#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L +#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L +#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L +#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. + //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback +#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L +#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L +#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L + +//ucTableFormatRevision=1 +//ucTableContentRevision=1 +typedef struct _ATOM_POWERMODE_INFO +{ + ULONG ulMiscInfo; //The power level should be arranged in ascending order + ULONG ulReserved1; // must set to 0 + ULONG ulReserved2; // must set to 0 + USHORT usEngineClock; + USHORT usMemoryClock; + UCHAR ucVoltageDropIndex; // index to GPIO table + UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate + UCHAR ucMinTemperature; + UCHAR ucMaxTemperature; + UCHAR ucNumPciELanes; // number of PCIE lanes +}ATOM_POWERMODE_INFO; + +//ucTableFormatRevision=2 +//ucTableContentRevision=1 +typedef struct _ATOM_POWERMODE_INFO_V2 +{ + ULONG ulMiscInfo; //The power level should be arranged in ascending order + ULONG ulMiscInfo2; + ULONG ulEngineClock; + ULONG ulMemoryClock; + UCHAR ucVoltageDropIndex; // index to GPIO table + UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate + UCHAR ucMinTemperature; + UCHAR ucMaxTemperature; + UCHAR ucNumPciELanes; // number of PCIE lanes +}ATOM_POWERMODE_INFO_V2; + +//ucTableFormatRevision=2 +//ucTableContentRevision=2 +typedef struct _ATOM_POWERMODE_INFO_V3 +{ + ULONG ulMiscInfo; //The power level should be arranged in ascending order + ULONG ulMiscInfo2; + ULONG ulEngineClock; + ULONG ulMemoryClock; + UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table + UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate + UCHAR ucMinTemperature; + UCHAR ucMaxTemperature; + UCHAR ucNumPciELanes; // number of PCIE lanes + UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table +}ATOM_POWERMODE_INFO_V3; + + +#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 + +#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 +#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 + +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog + + +typedef struct _ATOM_POWERPLAY_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucOverdriveThermalController; + UCHAR ucOverdriveI2cLine; + UCHAR ucOverdriveIntBitmap; + UCHAR ucOverdriveControllerAddress; + UCHAR ucSizeOfPowerModeEntry; + UCHAR ucNumOfPowerModeEntries; + ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +}ATOM_POWERPLAY_INFO; + +typedef struct _ATOM_POWERPLAY_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucOverdriveThermalController; + UCHAR ucOverdriveI2cLine; + UCHAR ucOverdriveIntBitmap; + UCHAR ucOverdriveControllerAddress; + UCHAR ucSizeOfPowerModeEntry; + UCHAR ucNumOfPowerModeEntries; + ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +}ATOM_POWERPLAY_INFO_V2; + +typedef struct _ATOM_POWERPLAY_INFO_V3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucOverdriveThermalController; + UCHAR ucOverdriveI2cLine; + UCHAR ucOverdriveIntBitmap; + UCHAR ucOverdriveControllerAddress; + UCHAR ucSizeOfPowerModeEntry; + UCHAR ucNumOfPowerModeEntries; + ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +}ATOM_POWERPLAY_INFO_V3; + + + +/**************************************************************************/ + + +// Following definitions are for compatiblity issue in different SW components. +#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 +#define Object_Info Object_Header +#define AdjustARB_SEQ MC_InitParameter +#define VRAM_GPIO_DetectionInfo VoltageObjectInfo +#define ASIC_VDDCI_Info ASIC_ProfilingInfo +#define ASIC_MVDDQ_Info MemoryTrainingInfo +#define SS_Info PPLL_SS_Info +#define ASIC_MVDDC_Info ASIC_InternalSS_Info +#define DispDevicePriorityInfo SaveRestoreInfo +#define DispOutInfo TV_VideoMode + + +#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE +#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE + +//New device naming, remove them when both DAL/VBIOS is ready +#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS +#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS + +#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS +#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS + +#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS +#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION + +#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT +#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT + +#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX +#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX + +#define ATOM_DEVICE_DFP2I_INDEX 0x00000009 +#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) + +#define ATOM_S0_DFP1I ATOM_S0_DFP1 +#define ATOM_S0_DFP1X ATOM_S0_DFP2 + +#define ATOM_S0_DFP2I 0x00200000L +#define ATOM_S0_DFP2Ib2 0x20 + +#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE +#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE + +#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L +#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 + +#define ATOM_S3_DFP2I_ACTIVEb1 0x02 + +#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE +#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE + +#define ATOM_S3_DFP2I_ACTIVE 0x00000200L + +#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE +#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE +#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L + + +#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 +#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 + +#define ATOM_S5_DOS_REQ_DFP2I 0x0200 +#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 +#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 + +#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 +#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L + +#define TMDS1XEncoderControl DVOEncoderControl +#define DFP1XOutputControl DVOOutputControl + +#define ExternalDFPOutputControl DFP1XOutputControl +#define EnableExternalTMDS_Encoder TMDS1XEncoderControl + +#define DFP1IOutputControl TMDSAOutputControl +#define DFP2IOutputControl LVTMAOutputControl + +#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS +#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION + +#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS +#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION + +#define ucDac1Standard ucDacStandard +#define ucDac2Standard ucDacStandard + +#define TMDS1EncoderControl TMDSAEncoderControl +#define TMDS2EncoderControl LVTMAEncoderControl + +#define DFP1OutputControl TMDSAOutputControl +#define DFP2OutputControl LVTMAOutputControl +#define CRT1OutputControl DAC1OutputControl +#define CRT2OutputControl DAC2OutputControl + +//These two lines will be removed for sure in a few days, will follow up with Michael V. +#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL +#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL + +#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L +#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE +#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE +#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE +#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE + +#define ATOM_S6_ACC_REQ_TV2 0x00400000L +#define ATOM_DEVICE_TV2_INDEX 0x00000006 +#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) +#define ATOM_S0_TV2 0x00100000L +#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE +#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE + +/*********************************************************************************/ + +#pragma pack() // BIOS data must use byte aligment + +#pragma pack(1) + +typedef struct _ATOM_HOLE_INFO +{ + USHORT usOffset; // offset of the hole ( from the start of the binary ) + USHORT usLength; // length of the hole ( in bytes ) +}ATOM_HOLE_INFO; + +typedef struct _ATOM_SERVICE_DESCRIPTION +{ + UCHAR ucRevision; // Holes set revision + UCHAR ucAlgorithm; // Hash algorithm + UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production ) + UCHAR ucReserved; + USHORT usSigOffset; // Signature offset ( from the start of the binary ) + USHORT usSigLength; // Signature length +}ATOM_SERVICE_DESCRIPTION; + + +typedef struct _ATOM_SERVICE_INFO +{ + ATOM_COMMON_TABLE_HEADER asHeader; + ATOM_SERVICE_DESCRIPTION asDescr; + UCHAR ucholesNo; // number of holes that follow + ATOM_HOLE_INFO holes[1]; // array of hole descriptions +}ATOM_SERVICE_INFO; + + + +#pragma pack() // BIOS data must use byte aligment + +// +// AMD ACPI Table +// +#pragma pack(1) + +typedef struct { + ULONG Signature; + ULONG TableLength; //Length + UCHAR Revision; + UCHAR Checksum; + UCHAR OemId[6]; + UCHAR OemTableId[8]; //UINT64 OemTableId; + ULONG OemRevision; + ULONG CreatorId; + ULONG CreatorRevision; +} AMD_ACPI_DESCRIPTION_HEADER; +/* +//EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h +typedef struct { + UINT32 Signature; //0x0 + UINT32 Length; //0x4 + UINT8 Revision; //0x8 + UINT8 Checksum; //0x9 + UINT8 OemId[6]; //0xA + UINT64 OemTableId; //0x10 + UINT32 OemRevision; //0x18 + UINT32 CreatorId; //0x1C + UINT32 CreatorRevision; //0x20 +}EFI_ACPI_DESCRIPTION_HEADER; +*/ +typedef struct { + AMD_ACPI_DESCRIPTION_HEADER SHeader; + UCHAR TableUUID[16]; //0x24 + ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. + ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. + ULONG Reserved[4]; //0x3C +}UEFI_ACPI_VFCT; + +typedef struct { + ULONG PCIBus; //0x4C + ULONG PCIDevice; //0x50 + ULONG PCIFunction; //0x54 + USHORT VendorID; //0x58 + USHORT DeviceID; //0x5A + USHORT SSVID; //0x5C + USHORT SSID; //0x5E + ULONG Revision; //0x60 + ULONG ImageLength; //0x64 +}VFCT_IMAGE_HEADER; + + +typedef struct { + VFCT_IMAGE_HEADER VbiosHeader; + UCHAR VbiosContent[1]; +}GOP_VBIOS_CONTENT; + +typedef struct { + VFCT_IMAGE_HEADER Lib1Header; + UCHAR Lib1Content[1]; +}GOP_LIB1_CONTENT; + +#pragma pack() + + +#endif /* _ATOMBIOS_H */ + +#include "pptable.h" + diff --git a/drivers/gpu/drm/amd/amdgpu/pptable.h b/drivers/gpu/drm/amd/amdgpu/pptable.h new file mode 100644 index 000000000000..0030f726e68c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/pptable.h @@ -0,0 +1,698 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _PPTABLE_H +#define _PPTABLE_H + +#pragma pack(1) + +typedef struct _ATOM_PPLIB_THERMALCONTROLLER + +{ + UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* + UCHAR ucI2cLine; // as interpreted by DAL I2C + UCHAR ucI2cAddress; + UCHAR ucFanParameters; // Fan Control Parameters. + UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. + UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. + UCHAR ucReserved; // ---- + UCHAR ucFlags; // to be defined +} ATOM_PPLIB_THERMALCONTROLLER; + +#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f +#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. + +#define ATOM_PP_THERMALCONTROLLER_NONE 0 +#define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib +#define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib +#define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib +#define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib +#define ATOM_PP_THERMALCONTROLLER_LM64 5 +#define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib +#define ATOM_PP_THERMALCONTROLLER_RV6xx 7 +#define ATOM_PP_THERMALCONTROLLER_RV770 8 +#define ATOM_PP_THERMALCONTROLLER_ADT7473 9 +#define ATOM_PP_THERMALCONTROLLER_KONG 10 +#define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 +#define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 +#define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. +#define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally +#define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 +#define ATOM_PP_THERMALCONTROLLER_SISLANDS 16 +#define ATOM_PP_THERMALCONTROLLER_LM96163 17 +#define ATOM_PP_THERMALCONTROLLER_CISLANDS 18 +#define ATOM_PP_THERMALCONTROLLER_KAVERI 19 + + +// Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. +// We probably should reserve the bit 0x80 for this use. +// To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). +// The driver can pick the correct internal controller based on the ASIC. + +#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller +#define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller + +typedef struct _ATOM_PPLIB_STATE +{ + UCHAR ucNonClockStateIndex; + UCHAR ucClockStateIndices[1]; // variable-sized +} ATOM_PPLIB_STATE; + + +typedef struct _ATOM_PPLIB_FANTABLE +{ + UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. + UCHAR ucTHyst; // Temperature hysteresis. Integer. + USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. + USHORT usTMed; // The middle temperature where we change slopes. + USHORT usTHigh; // The high point above TMed for adjusting the second slope. + USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). + USHORT usPWMMed; // The PWM value (in percent) at TMed. + USHORT usPWMHigh; // The PWM value at THigh. +} ATOM_PPLIB_FANTABLE; + +typedef struct _ATOM_PPLIB_FANTABLE2 +{ + ATOM_PPLIB_FANTABLE basicTable; + USHORT usTMax; // The max temperature +} ATOM_PPLIB_FANTABLE2; + +typedef struct _ATOM_PPLIB_FANTABLE3 +{ + ATOM_PPLIB_FANTABLE2 basicTable2; + UCHAR ucFanControlMode; + USHORT usFanPWMMax; + USHORT usFanOutputSensitivity; +} ATOM_PPLIB_FANTABLE3; + +typedef struct _ATOM_PPLIB_EXTENDEDHEADER +{ + USHORT usSize; + ULONG ulMaxEngineClock; // For Overdrive. + ULONG ulMaxMemoryClock; // For Overdrive. + // Add extra system parameters here, always adjust size to include all fields. + USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table + USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table + USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table + USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table + USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table + /* points to ATOM_PPLIB_POWERTUNE_Table */ + USHORT usPowerTuneTableOffset; + /* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */ + USHORT usSclkVddgfxTableOffset; +} ATOM_PPLIB_EXTENDEDHEADER; + +//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps +#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 +#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 +#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 +#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 +#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 +#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 +#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 +#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 +#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 +#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 +#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 +#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 +#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 +#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. +#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). +#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. +#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. +#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. +#define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE 0x00040000 // Does the driver supports new CAC voltage table. +#define ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY 0x00080000 // Does the driver supports revert GPIO5 polarity. +#define ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17 0x00100000 // Does the driver supports thermal2GPIO17. +#define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE 0x00200000 // Does the driver supports VR HOT GPIO Configurable. +#define ATOM_PP_PLATFORM_CAP_TEMP_INVERSION 0x00400000 // Does the driver supports Temp Inversion feature. +#define ATOM_PP_PLATFORM_CAP_EVV 0x00800000 + +typedef struct _ATOM_PPLIB_POWERPLAYTABLE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + + UCHAR ucDataRevision; + + UCHAR ucNumStates; + UCHAR ucStateEntrySize; + UCHAR ucClockInfoSize; + UCHAR ucNonClockSize; + + // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures + USHORT usStateArrayOffset; + + // offset from start of this table to array of ASIC-specific structures, + // currently ATOM_PPLIB_CLOCK_INFO. + USHORT usClockInfoArrayOffset; + + // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO + USHORT usNonClockInfoArrayOffset; + + USHORT usBackbiasTime; // in microseconds + USHORT usVoltageTime; // in microseconds + USHORT usTableSize; //the size of this structure, or the extended structure + + ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* + + ATOM_PPLIB_THERMALCONTROLLER sThermalController; + + USHORT usBootClockInfoOffset; + USHORT usBootNonClockInfoOffset; + +} ATOM_PPLIB_POWERPLAYTABLE; + +typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 +{ + ATOM_PPLIB_POWERPLAYTABLE basicTable; + UCHAR ucNumCustomThermalPolicy; + USHORT usCustomThermalPolicyArrayOffset; +}ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; + +typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 +{ + ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; + USHORT usFormatID; // To be used ONLY by PPGen. + USHORT usFanTableOffset; + USHORT usExtendendedHeaderOffset; +} ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; + +typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 +{ + ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; + ULONG ulGoldenPPID; // PPGen use only + ULONG ulGoldenRevision; // PPGen use only + USHORT usVddcDependencyOnSCLKOffset; + USHORT usVddciDependencyOnMCLKOffset; + USHORT usVddcDependencyOnMCLKOffset; + USHORT usMaxClockVoltageOnDCOffset; + USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table + USHORT usMvddDependencyOnMCLKOffset; +} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; + +typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 +{ + ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; + ULONG ulTDPLimit; + ULONG ulNearTDPLimit; + ULONG ulSQRampingThreshold; + USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table + ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table + USHORT usTDPODLimit; + USHORT usLoadLineSlope; // in milliOhms * 100 +} ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; + +//// ATOM_PPLIB_NONCLOCK_INFO::usClassification +#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 +#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 +#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 +#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 +#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 +#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 +// 2, 4, 6, 7 are reserved + +#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 +#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 +#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 +#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 +#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 +#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 +#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 +#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 +#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 +#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 +#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 +#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 +#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 + +//// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 +#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 +#define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 +#define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D) + +//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings +#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 +#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 + +// 0 is 2.5Gb/s, 1 is 5Gb/s +#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 +#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 + +// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec +#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 +#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 + +// lookup into reduced refresh-rate table +#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 +#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 + +#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 +#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 +// 2-15 TBD as needed. + +#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 +#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 + +#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 + +#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 + +//memory related flags +#define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 + +//M3 Arb //2bits, current 3 sets of parameters in total +#define ATOM_PPLIB_M3ARB_MASK 0x00060000 +#define ATOM_PPLIB_M3ARB_SHIFT 17 + +#define ATOM_PPLIB_ENABLE_DRR 0x00080000 + +// remaining 16 bits are reserved +typedef struct _ATOM_PPLIB_THERMAL_STATE +{ + UCHAR ucMinTemperature; + UCHAR ucMaxTemperature; + UCHAR ucThermalAction; +}ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; + +// Contained in an array starting at the offset +// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. +// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex +#define ATOM_PPLIB_NONCLOCKINFO_VER1 12 +#define ATOM_PPLIB_NONCLOCKINFO_VER2 24 +typedef struct _ATOM_PPLIB_NONCLOCK_INFO +{ + USHORT usClassification; + UCHAR ucMinTemperature; + UCHAR ucMaxTemperature; + ULONG ulCapsAndSettings; + UCHAR ucRequiredPower; + USHORT usClassification2; + ULONG ulVCLK; + ULONG ulDCLK; + UCHAR ucUnused[5]; +} ATOM_PPLIB_NONCLOCK_INFO; + +// Contained in an array starting at the offset +// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. +// referenced from ATOM_PPLIB_STATE::ucClockStateIndices +typedef struct _ATOM_PPLIB_R600_CLOCK_INFO +{ + USHORT usEngineClockLow; + UCHAR ucEngineClockHigh; + + USHORT usMemoryClockLow; + UCHAR ucMemoryClockHigh; + + USHORT usVDDC; + USHORT usUnused1; + USHORT usUnused2; + + ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* + +} ATOM_PPLIB_R600_CLOCK_INFO; + +// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO +#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 +#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 +#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 +#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 +#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 +#define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). + +typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO + +{ + USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). + UCHAR ucLowEngineClockHigh; + USHORT usHighEngineClockLow; // High Engine clock in MHz. + UCHAR ucHighEngineClockHigh; + USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. + UCHAR ucMemoryClockHigh; // Currentyl unused. + UCHAR ucPadding; // For proper alignment and size. + USHORT usVDDC; // For the 780, use: None, Low, High, Variable + UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} + UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could + USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). + ULONG ulFlags; +} ATOM_PPLIB_RS780_CLOCK_INFO; + +#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 +#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 +#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 +#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 + +#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. +#define ATOM_PPLIB_RS780_SPMCLK_LOW 1 +#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 + +#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 +#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 +#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 + +typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO +{ + USHORT usEngineClockLow; + UCHAR ucEngineClockHigh; + + USHORT usMemoryClockLow; + UCHAR ucMemoryClockHigh; + + USHORT usVDDC; + USHORT usVDDCI; + USHORT usUnused; + + ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* + +} ATOM_PPLIB_EVERGREEN_CLOCK_INFO; + +typedef struct _ATOM_PPLIB_SI_CLOCK_INFO +{ + USHORT usEngineClockLow; + UCHAR ucEngineClockHigh; + + USHORT usMemoryClockLow; + UCHAR ucMemoryClockHigh; + + USHORT usVDDC; + USHORT usVDDCI; + UCHAR ucPCIEGen; + UCHAR ucUnused1; + + ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now + +} ATOM_PPLIB_SI_CLOCK_INFO; + +typedef struct _ATOM_PPLIB_CI_CLOCK_INFO +{ + USHORT usEngineClockLow; + UCHAR ucEngineClockHigh; + + USHORT usMemoryClockLow; + UCHAR ucMemoryClockHigh; + + UCHAR ucPCIEGen; + USHORT usPCIELane; +} ATOM_PPLIB_CI_CLOCK_INFO; + +typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ + USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz + UCHAR ucEngineClockHigh; //clockfrequency >> 16. + UCHAR vddcIndex; //2-bit vddc index; + USHORT tdpLimit; + //please initalize to 0 + USHORT rsv1; + //please initialize to 0s + ULONG rsv2[2]; +}ATOM_PPLIB_SUMO_CLOCK_INFO; + +typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO { + UCHAR index; + UCHAR rsv[3]; +} ATOM_PPLIB_CZ_CLOCK_INFO; + +typedef struct _ATOM_PPLIB_STATE_V2 +{ + //number of valid dpm levels in this state; Driver uses it to calculate the whole + //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) + UCHAR ucNumDPMLevels; + + //a index to the array of nonClockInfos + UCHAR nonClockInfoIndex; + /** + * Driver will read the first ucNumDPMLevels in this array + */ + UCHAR clockInfoIndex[1]; +} ATOM_PPLIB_STATE_V2; + +typedef struct _StateArray{ + //how many states we have + UCHAR ucNumEntries; + + ATOM_PPLIB_STATE_V2 states[1]; +}StateArray; + + +typedef struct _ClockInfoArray{ + //how many clock levels we have + UCHAR ucNumEntries; + + //sizeof(ATOM_PPLIB_CLOCK_INFO) + UCHAR ucEntrySize; + + UCHAR clockInfo[1]; +}ClockInfoArray; + +typedef struct _NonClockInfoArray{ + + //how many non-clock levels we have. normally should be same as number of states + UCHAR ucNumEntries; + //sizeof(ATOM_PPLIB_NONCLOCK_INFO) + UCHAR ucEntrySize; + + ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; +}NonClockInfoArray; + +typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record +{ + USHORT usClockLow; + UCHAR ucClockHigh; + USHORT usVoltage; +}ATOM_PPLIB_Clock_Voltage_Dependency_Record; + +typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table +{ + UCHAR ucNumEntries; // Number of entries. + ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. +}ATOM_PPLIB_Clock_Voltage_Dependency_Table; + +typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record +{ + USHORT usSclkLow; + UCHAR ucSclkHigh; + USHORT usMclkLow; + UCHAR ucMclkHigh; + USHORT usVddc; + USHORT usVddci; +}ATOM_PPLIB_Clock_Voltage_Limit_Record; + +typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table +{ + UCHAR ucNumEntries; // Number of entries. + ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. +}ATOM_PPLIB_Clock_Voltage_Limit_Table; + +union _ATOM_PPLIB_CAC_Leakage_Record +{ + struct + { + USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations; For CI and newer, we use this as the real VDDC value. in CI we read it as StdVoltageHiSidd + ULONG ulLeakageValue; // For CI and newer we use this as the "fake" standar VDDC value. in CI we read it as StdVoltageLoSidd + + }; + struct + { + USHORT usVddc1; + USHORT usVddc2; + USHORT usVddc3; + }; +}; + +typedef union _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record; + +typedef struct _ATOM_PPLIB_CAC_Leakage_Table +{ + UCHAR ucNumEntries; // Number of entries. + ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries. +}ATOM_PPLIB_CAC_Leakage_Table; + +typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record +{ + USHORT usVoltage; + USHORT usSclkLow; + UCHAR ucSclkHigh; + USHORT usMclkLow; + UCHAR ucMclkHigh; +}ATOM_PPLIB_PhaseSheddingLimits_Record; + +typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table +{ + UCHAR ucNumEntries; // Number of entries. + ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries. +}ATOM_PPLIB_PhaseSheddingLimits_Table; + +typedef struct _VCEClockInfo{ + USHORT usEVClkLow; + UCHAR ucEVClkHigh; + USHORT usECClkLow; + UCHAR ucECClkHigh; +}VCEClockInfo; + +typedef struct _VCEClockInfoArray{ + UCHAR ucNumEntries; + VCEClockInfo entries[1]; +}VCEClockInfoArray; + +typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record +{ + USHORT usVoltage; + UCHAR ucVCEClockInfoIndex; +}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record; + +typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table +{ + UCHAR numEntries; + ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1]; +}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table; + +typedef struct _ATOM_PPLIB_VCE_State_Record +{ + UCHAR ucVCEClockInfoIndex; + UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary +}ATOM_PPLIB_VCE_State_Record; + +typedef struct _ATOM_PPLIB_VCE_State_Table +{ + UCHAR numEntries; + ATOM_PPLIB_VCE_State_Record entries[1]; +}ATOM_PPLIB_VCE_State_Table; + + +typedef struct _ATOM_PPLIB_VCE_Table +{ + UCHAR revid; +// VCEClockInfoArray array; +// ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits; +// ATOM_PPLIB_VCE_State_Table states; +}ATOM_PPLIB_VCE_Table; + + +typedef struct _UVDClockInfo{ + USHORT usVClkLow; + UCHAR ucVClkHigh; + USHORT usDClkLow; + UCHAR ucDClkHigh; +}UVDClockInfo; + +typedef struct _UVDClockInfoArray{ + UCHAR ucNumEntries; + UVDClockInfo entries[1]; +}UVDClockInfoArray; + +typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record +{ + USHORT usVoltage; + UCHAR ucUVDClockInfoIndex; +}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record; + +typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table +{ + UCHAR numEntries; + ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1]; +}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table; + +typedef struct _ATOM_PPLIB_UVD_Table +{ + UCHAR revid; +// UVDClockInfoArray array; +// ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits; +}ATOM_PPLIB_UVD_Table; + +typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record +{ + USHORT usVoltage; + USHORT usSAMClockLow; + UCHAR ucSAMClockHigh; +}ATOM_PPLIB_SAMClk_Voltage_Limit_Record; + +typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{ + UCHAR numEntries; + ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[1]; +}ATOM_PPLIB_SAMClk_Voltage_Limit_Table; + +typedef struct _ATOM_PPLIB_SAMU_Table +{ + UCHAR revid; + ATOM_PPLIB_SAMClk_Voltage_Limit_Table limits; +}ATOM_PPLIB_SAMU_Table; + +typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record +{ + USHORT usVoltage; + USHORT usACPClockLow; + UCHAR ucACPClockHigh; +}ATOM_PPLIB_ACPClk_Voltage_Limit_Record; + +typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{ + UCHAR numEntries; + ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1]; +}ATOM_PPLIB_ACPClk_Voltage_Limit_Table; + +typedef struct _ATOM_PPLIB_ACP_Table +{ + UCHAR revid; + ATOM_PPLIB_ACPClk_Voltage_Limit_Table limits; +}ATOM_PPLIB_ACP_Table; + +typedef struct _ATOM_PowerTune_Table{ + USHORT usTDP; + USHORT usConfigurableTDP; + USHORT usTDC; + USHORT usBatteryPowerLimit; + USHORT usSmallPowerLimit; + USHORT usLowCACLeakage; + USHORT usHighCACLeakage; +}ATOM_PowerTune_Table; + +typedef struct _ATOM_PPLIB_POWERTUNE_Table +{ + UCHAR revid; + ATOM_PowerTune_Table power_tune_table; +}ATOM_PPLIB_POWERTUNE_Table; + +typedef struct _ATOM_PPLIB_POWERTUNE_Table_V1 +{ + UCHAR revid; + ATOM_PowerTune_Table power_tune_table; + USHORT usMaximumPowerDeliveryLimit; + USHORT usReserve[7]; +} ATOM_PPLIB_POWERTUNE_Table_V1; + +#define ATOM_PPM_A_A 1 +#define ATOM_PPM_A_I 2 +typedef struct _ATOM_PPLIB_PPM_Table +{ + UCHAR ucRevId; + UCHAR ucPpmDesign; //A+I or A+A + USHORT usCpuCoreNumber; + ULONG ulPlatformTDP; + ULONG ulSmallACPlatformTDP; + ULONG ulPlatformTDC; + ULONG ulSmallACPlatformTDC; + ULONG ulApuTDP; + ULONG ulDGpuTDP; + ULONG ulDGpuUlvPower; + ULONG ulTjmax; +} ATOM_PPLIB_PPM_Table; + +#pragma pack() + +#endif -- cgit v1.2.3 From bd098eb0ee07790a2379aab4d2124f95773d8192 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Apr 2015 16:46:13 -0400 Subject: drm/amdgpu: add clearstate_defs.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This header provides for format for the GCA blocks clear state (i.e., default state). Each GCA version has a specific clear state. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/clearstate_defs.h | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_defs.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_defs.h b/drivers/gpu/drm/amd/amdgpu/clearstate_defs.h new file mode 100644 index 000000000000..3eda707d7388 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/clearstate_defs.h @@ -0,0 +1,44 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef CLEARSTATE_DEFS_H +#define CLEARSTATE_DEFS_H + +enum section_id { + SECT_NONE, + SECT_CONTEXT, + SECT_CLEAR, + SECT_CTRLCONST +}; + +struct cs_extent_def { + const unsigned int *extent; + const unsigned int reg_index; + const unsigned int reg_count; +}; + +struct cs_section_def { + const struct cs_extent_def *section; + const enum section_id id; +}; + +#endif -- cgit v1.2.3 From b111f7e4d27b48164782d4d2f55634cb05dd0c7c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Apr 2015 16:48:06 -0400 Subject: drm/amdgpu: add ppsmc.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This header provides the smc message interface for the driver. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ppsmc.h | 196 +++++++++++++++++++++++++++++++++++++ 1 file changed, 196 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/ppsmc.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/ppsmc.h b/drivers/gpu/drm/amd/amdgpu/ppsmc.h new file mode 100644 index 000000000000..7837f2ecc357 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/ppsmc.h @@ -0,0 +1,196 @@ +/* + * Copyright 2011 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef PP_SMC_H +#define PP_SMC_H + +#pragma pack(push, 1) + +#define PPSMC_SWSTATE_FLAG_DC 0x01 +#define PPSMC_SWSTATE_FLAG_UVD 0x02 +#define PPSMC_SWSTATE_FLAG_VCE 0x04 +#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08 + +#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 +#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 +#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff + +#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 +#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 +#define PPSMC_SYSTEMFLAG_GDDR5 0x04 +#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO 0x40 + +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 +#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 +#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x02 + +#define PPSMC_DISPLAY_WATERMARK_LOW 0 +#define PPSMC_DISPLAY_WATERMARK_HIGH 1 + +#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 +#define PPSMC_STATEFLAG_POWERBOOST 0x02 +#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 +#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 + +#define FDO_MODE_HARDWARE 0 +#define FDO_MODE_PIECE_WISE_LINEAR 1 + +enum FAN_CONTROL { + FAN_CONTROL_FUZZY, + FAN_CONTROL_TABLE +}; + +#define PPSMC_Result_OK ((uint8_t)0x01) +#define PPSMC_Result_Failed ((uint8_t)0xFF) + +typedef uint8_t PPSMC_Result; + +#define PPSMC_MSG_Halt ((uint8_t)0x10) +#define PPSMC_MSG_Resume ((uint8_t)0x11) +#define PPSMC_MSG_ZeroLevelsDisabled ((uint8_t)0x13) +#define PPSMC_MSG_OneLevelsDisabled ((uint8_t)0x14) +#define PPSMC_MSG_TwoLevelsDisabled ((uint8_t)0x15) +#define PPSMC_MSG_EnableThermalInterrupt ((uint8_t)0x16) +#define PPSMC_MSG_RunningOnAC ((uint8_t)0x17) +#define PPSMC_MSG_SwitchToSwState ((uint8_t)0x20) +#define PPSMC_MSG_SwitchToInitialState ((uint8_t)0x40) +#define PPSMC_MSG_NoForcedLevel ((uint8_t)0x41) +#define PPSMC_MSG_ForceHigh ((uint8_t)0x42) +#define PPSMC_MSG_ForceMediumOrHigh ((uint8_t)0x43) +#define PPSMC_MSG_SwitchToMinimumPower ((uint8_t)0x51) +#define PPSMC_MSG_ResumeFromMinimumPower ((uint8_t)0x52) +#define PPSMC_MSG_EnableCac ((uint8_t)0x53) +#define PPSMC_MSG_DisableCac ((uint8_t)0x54) +#define PPSMC_TDPClampingActive ((uint8_t)0x59) +#define PPSMC_TDPClampingInactive ((uint8_t)0x5A) +#define PPSMC_StartFanControl ((uint8_t)0x5B) +#define PPSMC_StopFanControl ((uint8_t)0x5C) +#define PPSMC_MSG_NoDisplay ((uint8_t)0x5D) +#define PPSMC_MSG_HasDisplay ((uint8_t)0x5E) +#define PPSMC_MSG_UVDPowerOFF ((uint8_t)0x60) +#define PPSMC_MSG_UVDPowerON ((uint8_t)0x61) +#define PPSMC_MSG_EnableULV ((uint8_t)0x62) +#define PPSMC_MSG_DisableULV ((uint8_t)0x63) +#define PPSMC_MSG_EnterULV ((uint8_t)0x64) +#define PPSMC_MSG_ExitULV ((uint8_t)0x65) +#define PPSMC_CACLongTermAvgEnable ((uint8_t)0x6E) +#define PPSMC_CACLongTermAvgDisable ((uint8_t)0x6F) +#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint8_t)0x7A) +#define PPSMC_FlushDataCache ((uint8_t)0x80) +#define PPSMC_MSG_SetEnabledLevels ((uint8_t)0x82) +#define PPSMC_MSG_SetForcedLevels ((uint8_t)0x83) +#define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84) +#define PPSMC_MSG_EnableDTE ((uint8_t)0x87) +#define PPSMC_MSG_DisableDTE ((uint8_t)0x88) +#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint8_t)0x96) +#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint8_t)0x97) + +/* CI/KV/KB */ +#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) +#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) +#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) +#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) +#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) +#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) +#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) +#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) +#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) +#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) +#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) +#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) +#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) +#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) +#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) +#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) +#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) +#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) +#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) +#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) +#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) +#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) +#define PPSMC_MSG_DPM_Enable ((uint16_t) 0x14e) +#define PPSMC_MSG_DPM_Disable ((uint16_t) 0x14f) +#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0x150) +#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0x151) +#define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0x154) +#define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0x155) +#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0x156) +#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0x157) +#define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0x158) +#define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0x159) +#define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0x15a) +#define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0x15b) +#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) +#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) +#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) +#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) +#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) +#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) +#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) +#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) +#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) +#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) +#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) +#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) +#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) +#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) +#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) +#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) +#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) + +#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) +#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) + +#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) +#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) + +/* TN */ +#define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) +#define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) +#define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) +#define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) +#define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a) +#define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) +#define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) +#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) +#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) +#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) +#define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) +#define PPSMC_MSG_DisableBAPM ((uint32_t) 0x121) +#define PPSMC_MSG_UVD_DPM_Config ((uint32_t) 0x124) + +#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) +#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) +#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) +#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) +#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) + +typedef uint16_t PPSMC_Msg; + +#pragma pack(pop) + +#endif -- cgit v1.2.3 From 8a94f39580e4f3c8df82f3e88e9ef1c35d607501 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Apr 2015 16:49:21 -0400 Subject: drm/amdgpu: add amdgpu_family.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This header defines asic families and attributes. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_family.h | 62 ++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_family.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_family.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_family.h new file mode 100644 index 000000000000..0698764354a2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_family.h @@ -0,0 +1,62 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ + +/* this file defines the CHIP_ and family flags used in the pciids, + * its is common between kms and non-kms because duplicating it and + * changing one place is fail. + */ +#ifndef AMDGPU_FAMILY_H +#define AMDGPU_FAMILY_H +/* + * Supported ASIC types + */ +enum amdgpu_asic_type { + CHIP_BONAIRE = 0, + CHIP_KAVERI, + CHIP_KABINI, + CHIP_HAWAII, + CHIP_MULLINS, + CHIP_TOPAZ, + CHIP_TONGA, + CHIP_CARRIZO, + CHIP_LAST, +}; + +/* + * Chip flags + */ +enum amdgpu_chip_flags { + AMDGPU_ASIC_MASK = 0x0000ffffUL, + AMDGPU_FLAGS_MASK = 0xffff0000UL, + AMDGPU_IS_MOBILITY = 0x00010000UL, + AMDGPU_IS_APU = 0x00020000UL, + AMDGPU_IS_PX = 0x00040000UL, + AMDGPU_EXP_HW_SUPPORT = 0x00080000UL, +}; + +#endif -- cgit v1.2.3 From 97b2e202fba05b87d720318a6500a337100dab4d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Apr 2015 16:51:00 -0400 Subject: drm/amdgpu: add amdgpu.h (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is the main header file for amdgpu. v2: remove stable comments Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2387 +++++++++++++++++++++++++++++++++++ 1 file changed, 2387 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h new file mode 100644 index 000000000000..65246abcee27 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -0,0 +1,2387 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef __AMDGPU_H__ +#define __AMDGPU_H__ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "amdgpu_family.h" +#include "amdgpu_mode.h" +#include "amdgpu_ih.h" +#include "amdgpu_irq.h" +#include "amdgpu_ucode.h" +#include "amdgpu_gds.h" + +/* + * Modules parameters. + */ +extern int amdgpu_modeset; +extern int amdgpu_vram_limit; +extern int amdgpu_gart_size; +extern int amdgpu_benchmarking; +extern int amdgpu_testing; +extern int amdgpu_audio; +extern int amdgpu_disp_priority; +extern int amdgpu_hw_i2c; +extern int amdgpu_pcie_gen2; +extern int amdgpu_msi; +extern int amdgpu_lockup_timeout; +extern int amdgpu_dpm; +extern int amdgpu_smc_load_fw; +extern int amdgpu_aspm; +extern int amdgpu_runtime_pm; +extern int amdgpu_hard_reset; +extern unsigned amdgpu_ip_block_mask; +extern int amdgpu_bapm; +extern int amdgpu_deep_color; +extern int amdgpu_vm_size; +extern int amdgpu_vm_block_size; + +#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ +#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) +/* AMDGPU_IB_POOL_SIZE must be a power of 2 */ +#define AMDGPU_IB_POOL_SIZE 16 +#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 +#define AMDGPUFB_CONN_LIMIT 4 +#define AMDGPU_BIOS_NUM_SCRATCH 8 + +/* fence seq are set to this number when signaled */ +#define AMDGPU_FENCE_SIGNALED_SEQ 0LL + +/* max number of rings */ +#define AMDGPU_MAX_RINGS 16 +#define AMDGPU_MAX_GFX_RINGS 1 +#define AMDGPU_MAX_COMPUTE_RINGS 8 +#define AMDGPU_MAX_VCE_RINGS 2 + +/* number of hw syncs before falling back on blocking */ +#define AMDGPU_NUM_SYNCS 4 + +/* hardcode that limit for now */ +#define AMDGPU_VA_RESERVED_SIZE (8 << 20) + +/* hard reset data */ +#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b + +/* reset flags */ +#define AMDGPU_RESET_GFX (1 << 0) +#define AMDGPU_RESET_COMPUTE (1 << 1) +#define AMDGPU_RESET_DMA (1 << 2) +#define AMDGPU_RESET_CP (1 << 3) +#define AMDGPU_RESET_GRBM (1 << 4) +#define AMDGPU_RESET_DMA1 (1 << 5) +#define AMDGPU_RESET_RLC (1 << 6) +#define AMDGPU_RESET_SEM (1 << 7) +#define AMDGPU_RESET_IH (1 << 8) +#define AMDGPU_RESET_VMC (1 << 9) +#define AMDGPU_RESET_MC (1 << 10) +#define AMDGPU_RESET_DISPLAY (1 << 11) +#define AMDGPU_RESET_UVD (1 << 12) +#define AMDGPU_RESET_VCE (1 << 13) +#define AMDGPU_RESET_VCE1 (1 << 14) + +/* CG block flags */ +#define AMDGPU_CG_BLOCK_GFX (1 << 0) +#define AMDGPU_CG_BLOCK_MC (1 << 1) +#define AMDGPU_CG_BLOCK_SDMA (1 << 2) +#define AMDGPU_CG_BLOCK_UVD (1 << 3) +#define AMDGPU_CG_BLOCK_VCE (1 << 4) +#define AMDGPU_CG_BLOCK_HDP (1 << 5) +#define AMDGPU_CG_BLOCK_BIF (1 << 6) + +/* CG flags */ +#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) +#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) +#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) +#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) +#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) +#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) +#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) +#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) +#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) +#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) +#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) +#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) +#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) +#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) +#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) +#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) +#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) + +/* PG flags */ +#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) +#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) +#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) +#define AMDGPU_PG_SUPPORT_UVD (1 << 3) +#define AMDGPU_PG_SUPPORT_VCE (1 << 4) +#define AMDGPU_PG_SUPPORT_CP (1 << 5) +#define AMDGPU_PG_SUPPORT_GDS (1 << 6) +#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) +#define AMDGPU_PG_SUPPORT_SDMA (1 << 8) +#define AMDGPU_PG_SUPPORT_ACP (1 << 9) +#define AMDGPU_PG_SUPPORT_SAMU (1 << 10) + +/* GFX current status */ +#define AMDGPU_GFX_NORMAL_MODE 0x00000000L +#define AMDGPU_GFX_SAFE_MODE 0x00000001L +#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L +#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L +#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L + +/* max cursor sizes (in pixels) */ +#define CIK_CURSOR_WIDTH 128 +#define CIK_CURSOR_HEIGHT 128 + +struct amdgpu_device; +struct amdgpu_fence; +struct amdgpu_ib; +struct amdgpu_vm; +struct amdgpu_ring; +struct amdgpu_semaphore; +struct amdgpu_cs_parser; +struct amdgpu_irq_src; + +enum amdgpu_cp_irq { + AMDGPU_CP_IRQ_GFX_EOP = 0, + AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, + AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, + AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, + AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, + AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, + AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, + AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, + AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, + + AMDGPU_CP_IRQ_LAST +}; + +enum amdgpu_sdma_irq { + AMDGPU_SDMA_IRQ_TRAP0 = 0, + AMDGPU_SDMA_IRQ_TRAP1, + + AMDGPU_SDMA_IRQ_LAST +}; + +enum amdgpu_thermal_irq { + AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, + AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, + + AMDGPU_THERMAL_IRQ_LAST +}; + +/* + * IP block functions + */ +enum amdgpu_ip_block_type { + AMDGPU_IP_BLOCK_TYPE_COMMON, + AMDGPU_IP_BLOCK_TYPE_GMC, + AMDGPU_IP_BLOCK_TYPE_IH, + AMDGPU_IP_BLOCK_TYPE_SMC, + AMDGPU_IP_BLOCK_TYPE_DCE, + AMDGPU_IP_BLOCK_TYPE_GFX, + AMDGPU_IP_BLOCK_TYPE_SDMA, + AMDGPU_IP_BLOCK_TYPE_UVD, + AMDGPU_IP_BLOCK_TYPE_VCE, +}; + +enum amdgpu_clockgating_state { + AMDGPU_CG_STATE_GATE = 0, + AMDGPU_CG_STATE_UNGATE, +}; + +enum amdgpu_powergating_state { + AMDGPU_PG_STATE_GATE = 0, + AMDGPU_PG_STATE_UNGATE, +}; + +struct amdgpu_ip_funcs { + /* sets up early driver state (pre sw_init), does not configure hw - Optional */ + int (*early_init)(struct amdgpu_device *adev); + /* sets up late driver/hw state (post hw_init) - Optional */ + int (*late_init)(struct amdgpu_device *adev); + /* sets up driver state, does not configure hw */ + int (*sw_init)(struct amdgpu_device *adev); + /* tears down driver state, does not configure hw */ + int (*sw_fini)(struct amdgpu_device *adev); + /* sets up the hw state */ + int (*hw_init)(struct amdgpu_device *adev); + /* tears down the hw state */ + int (*hw_fini)(struct amdgpu_device *adev); + /* handles IP specific hw/sw changes for suspend */ + int (*suspend)(struct amdgpu_device *adev); + /* handles IP specific hw/sw changes for resume */ + int (*resume)(struct amdgpu_device *adev); + /* returns current IP block idle status */ + bool (*is_idle)(struct amdgpu_device *adev); + /* poll for idle */ + int (*wait_for_idle)(struct amdgpu_device *adev); + /* soft reset the IP block */ + int (*soft_reset)(struct amdgpu_device *adev); + /* dump the IP block status registers */ + void (*print_status)(struct amdgpu_device *adev); + /* enable/disable cg for the IP block */ + int (*set_clockgating_state)(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state); + /* enable/disable pg for the IP block */ + int (*set_powergating_state)(struct amdgpu_device *adev, + enum amdgpu_powergating_state state); +}; + +int amdgpu_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_ip_block_type block_type, + enum amdgpu_clockgating_state state); +int amdgpu_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_ip_block_type block_type, + enum amdgpu_powergating_state state); + +struct amdgpu_ip_block_version { + enum amdgpu_ip_block_type type; + u32 major; + u32 minor; + u32 rev; + const struct amdgpu_ip_funcs *funcs; +}; + +int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, + enum amdgpu_ip_block_type type, + u32 major, u32 minor); + +const struct amdgpu_ip_block_version * amdgpu_get_ip_block( + struct amdgpu_device *adev, + enum amdgpu_ip_block_type type); + +/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ +struct amdgpu_buffer_funcs { + /* maximum bytes in a single operation */ + uint32_t copy_max_bytes; + + /* number of dw to reserve per operation */ + unsigned copy_num_dw; + + /* used for buffer migration */ + void (*emit_copy_buffer)(struct amdgpu_ring *ring, + /* src addr in bytes */ + uint64_t src_offset, + /* dst addr in bytes */ + uint64_t dst_offset, + /* number of byte to transfer */ + uint32_t byte_count); + + /* maximum bytes in a single operation */ + uint32_t fill_max_bytes; + + /* number of dw to reserve per operation */ + unsigned fill_num_dw; + + /* used for buffer clearing */ + void (*emit_fill_buffer)(struct amdgpu_ring *ring, + /* value to write to memory */ + uint32_t src_data, + /* dst addr in bytes */ + uint64_t dst_offset, + /* number of byte to fill */ + uint32_t byte_count); +}; + +/* provided by hw blocks that can write ptes, e.g., sdma */ +struct amdgpu_vm_pte_funcs { + /* copy pte entries from GART */ + void (*copy_pte)(struct amdgpu_ib *ib, + uint64_t pe, uint64_t src, + unsigned count); + /* write pte one entry at a time with addr mapping */ + void (*write_pte)(struct amdgpu_ib *ib, + uint64_t pe, + uint64_t addr, unsigned count, + uint32_t incr, uint32_t flags); + /* for linear pte/pde updates without addr mapping */ + void (*set_pte_pde)(struct amdgpu_ib *ib, + uint64_t pe, + uint64_t addr, unsigned count, + uint32_t incr, uint32_t flags); + /* pad the indirect buffer to the necessary number of dw */ + void (*pad_ib)(struct amdgpu_ib *ib); +}; + +/* provided by the gmc block */ +struct amdgpu_gart_funcs { + /* flush the vm tlb via mmio */ + void (*flush_gpu_tlb)(struct amdgpu_device *adev, + uint32_t vmid); + /* write pte/pde updates using the cpu */ + int (*set_pte_pde)(struct amdgpu_device *adev, + void *cpu_pt_addr, /* cpu addr of page table */ + uint32_t gpu_page_idx, /* pte/pde to update */ + uint64_t addr, /* addr to write into pte/pde */ + uint32_t flags); /* access flags */ +}; + +/* provided by the ih block */ +struct amdgpu_ih_funcs { + /* ring read/write ptr handling, called from interrupt context */ + u32 (*get_wptr)(struct amdgpu_device *adev); + void (*decode_iv)(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry); + void (*set_rptr)(struct amdgpu_device *adev); +}; + +/* provided by hw blocks that expose a ring buffer for commands */ +struct amdgpu_ring_funcs { + /* ring read/write ptr handling */ + u32 (*get_rptr)(struct amdgpu_ring *ring); + u32 (*get_wptr)(struct amdgpu_ring *ring); + void (*set_wptr)(struct amdgpu_ring *ring); + /* validating and patching of IBs */ + int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); + /* command emit functions */ + void (*emit_ib)(struct amdgpu_ring *ring, + struct amdgpu_ib *ib); + void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, + uint64_t seq, bool write64bit); + bool (*emit_semaphore)(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore, + bool emit_wait); + void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, + uint64_t pd_addr); + void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, + uint32_t gds_base, uint32_t gds_size, + uint32_t gws_base, uint32_t gws_size, + uint32_t oa_base, uint32_t oa_size); + /* testing functions */ + int (*test_ring)(struct amdgpu_ring *ring); + int (*test_ib)(struct amdgpu_ring *ring); + bool (*is_lockup)(struct amdgpu_ring *ring); +}; + +/* + * BIOS. + */ +bool amdgpu_get_bios(struct amdgpu_device *adev); +bool amdgpu_read_bios(struct amdgpu_device *adev); + +/* + * Dummy page + */ +struct amdgpu_dummy_page { + struct page *page; + dma_addr_t addr; +}; +int amdgpu_dummy_page_init(struct amdgpu_device *adev); +void amdgpu_dummy_page_fini(struct amdgpu_device *adev); + + +/* + * Clocks + */ + +#define AMDGPU_MAX_PPLL 3 + +struct amdgpu_clock { + struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; + struct amdgpu_pll spll; + struct amdgpu_pll mpll; + /* 10 Khz units */ + uint32_t default_mclk; + uint32_t default_sclk; + uint32_t default_dispclk; + uint32_t current_dispclk; + uint32_t dp_extclk; + uint32_t max_pixel_clock; +}; + +/* + * Fences. + */ +struct amdgpu_fence_driver { + struct amdgpu_ring *ring; + uint64_t gpu_addr; + volatile uint32_t *cpu_addr; + /* sync_seq is protected by ring emission lock */ + uint64_t sync_seq[AMDGPU_MAX_RINGS]; + atomic64_t last_seq; + bool initialized; + bool delayed_irq; + struct amdgpu_irq_src *irq_src; + unsigned irq_type; + struct delayed_work lockup_work; +}; + +/* some special values for the owner field */ +#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) +#define AMDGPU_FENCE_OWNER_VM ((void*)1ul) +#define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul) + +struct amdgpu_fence { + struct fence base; + + /* RB, DMA, etc. */ + struct amdgpu_ring *ring; + uint64_t seq; + + /* filp or special value for fence creator */ + void *owner; + + wait_queue_t fence_wake; +}; + +struct amdgpu_user_fence { + /* write-back bo */ + struct amdgpu_bo *bo; + /* write-back address offset to bo start */ + uint32_t offset; +}; + +int amdgpu_fence_driver_init(struct amdgpu_device *adev); +void amdgpu_fence_driver_fini(struct amdgpu_device *adev); +void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); + +void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); +int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, + struct amdgpu_irq_src *irq_src, + unsigned irq_type); +int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, + struct amdgpu_fence **fence); +void amdgpu_fence_process(struct amdgpu_ring *ring); +int amdgpu_fence_wait_next(struct amdgpu_ring *ring); +int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); +unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); + +bool amdgpu_fence_signaled(struct amdgpu_fence *fence); +int amdgpu_fence_wait(struct amdgpu_fence *fence, bool interruptible); +int amdgpu_fence_wait_any(struct amdgpu_device *adev, + struct amdgpu_fence **fences, + bool intr); +long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev, + u64 *target_seq, bool intr, + long timeout); +struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence); +void amdgpu_fence_unref(struct amdgpu_fence **fence); + +bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, + struct amdgpu_ring *ring); +void amdgpu_fence_note_sync(struct amdgpu_fence *fence, + struct amdgpu_ring *ring); + +static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a, + struct amdgpu_fence *b) +{ + if (!a) { + return b; + } + + if (!b) { + return a; + } + + BUG_ON(a->ring != b->ring); + + if (a->seq > b->seq) { + return a; + } else { + return b; + } +} + +static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a, + struct amdgpu_fence *b) +{ + if (!a) { + return false; + } + + if (!b) { + return true; + } + + BUG_ON(a->ring != b->ring); + + return a->seq < b->seq; +} + +int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user, + void *owner, struct amdgpu_fence **fence); + +/* + * TTM. + */ +struct amdgpu_mman { + struct ttm_bo_global_ref bo_global_ref; + struct drm_global_reference mem_global_ref; + struct ttm_bo_device bdev; + bool mem_global_referenced; + bool initialized; + +#if defined(CONFIG_DEBUG_FS) + struct dentry *vram; + struct dentry *gtt; +#endif + + /* buffer handling */ + const struct amdgpu_buffer_funcs *buffer_funcs; + struct amdgpu_ring *buffer_funcs_ring; +}; + +int amdgpu_copy_buffer(struct amdgpu_ring *ring, + uint64_t src_offset, + uint64_t dst_offset, + uint32_t byte_count, + struct reservation_object *resv, + struct amdgpu_fence **fence); +int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); + +struct amdgpu_bo_list_entry { + struct amdgpu_bo *robj; + struct ttm_validate_buffer tv; + struct amdgpu_bo_va *bo_va; + unsigned prefered_domains; + unsigned allowed_domains; + uint32_t priority; +}; + +struct amdgpu_bo_va_mapping { + struct list_head list; + struct interval_tree_node it; + uint64_t offset; + uint32_t flags; +}; + +/* bo virtual addresses in a specific vm */ +struct amdgpu_bo_va { + /* protected by bo being reserved */ + struct list_head bo_list; + uint64_t addr; + struct amdgpu_fence *last_pt_update; + unsigned ref_count; + + /* protected by vm mutex */ + struct list_head mappings; + struct list_head vm_status; + + /* constant after initialization */ + struct amdgpu_vm *vm; + struct amdgpu_bo *bo; +}; + +struct amdgpu_bo { + /* Protected by gem.mutex */ + struct list_head list; + /* Protected by tbo.reserved */ + u32 initial_domain; + struct ttm_place placements[4]; + struct ttm_placement placement; + struct ttm_buffer_object tbo; + struct ttm_bo_kmap_obj kmap; + u64 flags; + unsigned pin_count; + void *kptr; + u64 tiling_flags; + u64 metadata_flags; + void *metadata; + u32 metadata_size; + /* list of all virtual address to which this bo + * is associated to + */ + struct list_head va; + /* Constant after initialization */ + struct amdgpu_device *adev; + struct drm_gem_object gem_base; + + struct ttm_bo_kmap_obj dma_buf_vmap; + pid_t pid; + struct amdgpu_mn *mn; + struct list_head mn_list; +}; +#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) + +void amdgpu_gem_object_free(struct drm_gem_object *obj); +int amdgpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file_priv); +void amdgpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file_priv); +unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); +struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); +struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg); +struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, + struct drm_gem_object *gobj, + int flags); +int amdgpu_gem_prime_pin(struct drm_gem_object *obj); +void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); +struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); +void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); +void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); +int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); + +/* sub-allocation manager, it has to be protected by another lock. + * By conception this is an helper for other part of the driver + * like the indirect buffer or semaphore, which both have their + * locking. + * + * Principe is simple, we keep a list of sub allocation in offset + * order (first entry has offset == 0, last entry has the highest + * offset). + * + * When allocating new object we first check if there is room at + * the end total_size - (last_object_offset + last_object_size) >= + * alloc_size. If so we allocate new object there. + * + * When there is not enough room at the end, we start waiting for + * each sub object until we reach object_offset+object_size >= + * alloc_size, this object then become the sub object we return. + * + * Alignment can't be bigger than page size. + * + * Hole are not considered for allocation to keep things simple. + * Assumption is that there won't be hole (all object on same + * alignment). + */ +struct amdgpu_sa_manager { + wait_queue_head_t wq; + struct amdgpu_bo *bo; + struct list_head *hole; + struct list_head flist[AMDGPU_MAX_RINGS]; + struct list_head olist; + unsigned size; + uint64_t gpu_addr; + void *cpu_ptr; + uint32_t domain; + uint32_t align; +}; + +struct amdgpu_sa_bo; + +/* sub-allocation buffer */ +struct amdgpu_sa_bo { + struct list_head olist; + struct list_head flist; + struct amdgpu_sa_manager *manager; + unsigned soffset; + unsigned eoffset; + struct amdgpu_fence *fence; +}; + +/* + * GEM objects. + */ +struct amdgpu_gem { + struct mutex mutex; + struct list_head objects; +}; + +int amdgpu_gem_init(struct amdgpu_device *adev); +void amdgpu_gem_fini(struct amdgpu_device *adev); +int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, + int alignment, u32 initial_domain, + u64 flags, bool kernel, + struct drm_gem_object **obj); + +int amdgpu_mode_dumb_create(struct drm_file *file_priv, + struct drm_device *dev, + struct drm_mode_create_dumb *args); +int amdgpu_mode_dumb_mmap(struct drm_file *filp, + struct drm_device *dev, + uint32_t handle, uint64_t *offset_p); + +/* + * Semaphores. + */ +struct amdgpu_semaphore { + struct amdgpu_sa_bo *sa_bo; + signed waiters; + uint64_t gpu_addr; +}; + +int amdgpu_semaphore_create(struct amdgpu_device *adev, + struct amdgpu_semaphore **semaphore); +bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore); +bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore); +void amdgpu_semaphore_free(struct amdgpu_device *adev, + struct amdgpu_semaphore **semaphore, + struct amdgpu_fence *fence); + +/* + * Synchronization + */ +struct amdgpu_sync { + struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; + struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS]; + struct amdgpu_fence *last_vm_update; +}; + +void amdgpu_sync_create(struct amdgpu_sync *sync); +void amdgpu_sync_fence(struct amdgpu_sync *sync, + struct amdgpu_fence *fence); +int amdgpu_sync_resv(struct amdgpu_device *adev, + struct amdgpu_sync *sync, + struct reservation_object *resv, + void *owner); +int amdgpu_sync_rings(struct amdgpu_sync *sync, + struct amdgpu_ring *ring); +void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, + struct amdgpu_fence *fence); + +/* + * GART structures, functions & helpers + */ +struct amdgpu_mc; + +#define AMDGPU_GPU_PAGE_SIZE 4096 +#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) +#define AMDGPU_GPU_PAGE_SHIFT 12 +#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) + +struct amdgpu_gart { + dma_addr_t table_addr; + struct amdgpu_bo *robj; + void *ptr; + unsigned num_gpu_pages; + unsigned num_cpu_pages; + unsigned table_size; + struct page **pages; + dma_addr_t *pages_addr; + bool ready; + const struct amdgpu_gart_funcs *gart_funcs; +}; + +int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); +void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); +int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); +void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); +int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); +void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); +int amdgpu_gart_init(struct amdgpu_device *adev); +void amdgpu_gart_fini(struct amdgpu_device *adev); +void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, + int pages); +int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, + int pages, struct page **pagelist, + dma_addr_t *dma_addr, uint32_t flags); + +/* + * GPU MC structures, functions & helpers + */ +struct amdgpu_mc { + resource_size_t aper_size; + resource_size_t aper_base; + resource_size_t agp_base; + /* for some chips with <= 32MB we need to lie + * about vram size near mc fb location */ + u64 mc_vram_size; + u64 visible_vram_size; + u64 gtt_size; + u64 gtt_start; + u64 gtt_end; + u64 vram_start; + u64 vram_end; + unsigned vram_width; + u64 real_vram_size; + int vram_mtrr; + u64 gtt_base_align; + u64 mc_mask; + const struct firmware *fw; /* MC firmware */ + uint32_t fw_version; + struct amdgpu_irq_src vm_fault; + bool is_gddr5; +}; + +/* + * GPU doorbell structures, functions & helpers + */ +typedef enum _AMDGPU_DOORBELL_ASSIGNMENT +{ + AMDGPU_DOORBELL_KIQ = 0x000, + AMDGPU_DOORBELL_HIQ = 0x001, + AMDGPU_DOORBELL_DIQ = 0x002, + AMDGPU_DOORBELL_MEC_RING0 = 0x010, + AMDGPU_DOORBELL_MEC_RING1 = 0x011, + AMDGPU_DOORBELL_MEC_RING2 = 0x012, + AMDGPU_DOORBELL_MEC_RING3 = 0x013, + AMDGPU_DOORBELL_MEC_RING4 = 0x014, + AMDGPU_DOORBELL_MEC_RING5 = 0x015, + AMDGPU_DOORBELL_MEC_RING6 = 0x016, + AMDGPU_DOORBELL_MEC_RING7 = 0x017, + AMDGPU_DOORBELL_GFX_RING0 = 0x020, + AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, + AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, + AMDGPU_DOORBELL_IH = 0x1E8, + AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, + AMDGPU_DOORBELL_INVALID = 0xFFFF +} AMDGPU_DOORBELL_ASSIGNMENT; + +struct amdgpu_doorbell { + /* doorbell mmio */ + resource_size_t base; + resource_size_t size; + u32 __iomem *ptr; + u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ +}; + +void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, + phys_addr_t *aperture_base, + size_t *aperture_size, + size_t *start_offset); + +/* + * IRQS. + */ + +struct amdgpu_flip_work { + struct work_struct flip_work; + struct work_struct unpin_work; + struct amdgpu_device *adev; + int crtc_id; + uint64_t base; + struct drm_pending_vblank_event *event; + struct amdgpu_bo *old_rbo; + struct fence *fence; +}; + + +/* + * CP & rings. + */ + +struct amdgpu_ib { + struct amdgpu_sa_bo *sa_bo; + uint32_t length_dw; + uint64_t gpu_addr; + uint32_t *ptr; + struct amdgpu_ring *ring; + struct amdgpu_fence *fence; + struct amdgpu_user_fence *user; + struct amdgpu_vm *vm; + bool is_const_ib; + bool flush_hdp_writefifo; + struct amdgpu_sync sync; + bool gds_needed; + uint32_t gds_base, gds_size; + uint32_t gws_base, gws_size; + uint32_t oa_base, oa_size; +}; + +enum amdgpu_ring_type { + AMDGPU_RING_TYPE_GFX, + AMDGPU_RING_TYPE_COMPUTE, + AMDGPU_RING_TYPE_SDMA, + AMDGPU_RING_TYPE_UVD, + AMDGPU_RING_TYPE_VCE +}; + +struct amdgpu_ring { + struct amdgpu_device *adev; + const struct amdgpu_ring_funcs *funcs; + struct amdgpu_fence_driver fence_drv; + + struct mutex *ring_lock; + struct amdgpu_bo *ring_obj; + volatile uint32_t *ring; + unsigned rptr_offs; + u64 next_rptr_gpu_addr; + volatile u32 *next_rptr_cpu_addr; + unsigned wptr; + unsigned wptr_old; + unsigned ring_size; + unsigned ring_free_dw; + int count_dw; + atomic_t last_rptr; + atomic64_t last_activity; + uint64_t gpu_addr; + uint32_t align_mask; + uint32_t ptr_mask; + bool ready; + u32 nop; + u32 idx; + u64 last_semaphore_signal_addr; + u64 last_semaphore_wait_addr; + u32 me; + u32 pipe; + u32 queue; + struct amdgpu_bo *mqd_obj; + u32 doorbell_index; + bool use_doorbell; + unsigned wptr_offs; + unsigned next_rptr_offs; + unsigned fence_offs; + struct drm_file *current_filp; + bool need_ctx_switch; + enum amdgpu_ring_type type; + char name[16]; +}; + +/* + * VM + */ + +/* maximum number of VMIDs */ +#define AMDGPU_NUM_VM 16 + +/* number of entries in page table */ +#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) + +/* PTBs (Page Table Blocks) need to be aligned to 32K */ +#define AMDGPU_VM_PTB_ALIGN_SIZE 32768 +#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) +#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) + +#define AMDGPU_PTE_VALID (1 << 0) +#define AMDGPU_PTE_SYSTEM (1 << 1) +#define AMDGPU_PTE_SNOOPED (1 << 2) + +/* VI only */ +#define AMDGPU_PTE_EXECUTABLE (1 << 4) + +#define AMDGPU_PTE_READABLE (1 << 5) +#define AMDGPU_PTE_WRITEABLE (1 << 6) + +/* PTE (Page Table Entry) fragment field for different page sizes */ +#define AMDGPU_PTE_FRAG_4KB (0 << 7) +#define AMDGPU_PTE_FRAG_64KB (4 << 7) +#define AMDGPU_LOG2_PAGES_PER_FRAG 4 + +struct amdgpu_vm_pt { + struct amdgpu_bo *bo; + uint64_t addr; +}; + +struct amdgpu_vm_id { + unsigned id; + uint64_t pd_gpu_addr; + /* last flushed PD/PT update */ + struct amdgpu_fence *flushed_updates; + /* last use of vmid */ + struct amdgpu_fence *last_id_use; +}; + +struct amdgpu_vm { + struct mutex mutex; + + struct rb_root va; + + /* protecting invalidated and freed */ + spinlock_t status_lock; + + /* BOs moved, but not yet updated in the PT */ + struct list_head invalidated; + + /* BOs freed, but not yet updated in the PT */ + struct list_head freed; + + /* contains the page directory */ + struct amdgpu_bo *page_directory; + unsigned max_pde_used; + + /* array of page tables, one for each page directory entry */ + struct amdgpu_vm_pt *page_tables; + + /* for id and flush management per ring */ + struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; +}; + +struct amdgpu_vm_manager { + struct amdgpu_fence *active[AMDGPU_NUM_VM]; + uint32_t max_pfn; + /* number of VMIDs */ + unsigned nvm; + /* vram base address for page table entry */ + u64 vram_base_offset; + /* is vm enabled? */ + bool enabled; + /* for hw to save the PD addr on suspend/resume */ + uint32_t saved_table_addr[AMDGPU_NUM_VM]; + /* vm pte handling */ + const struct amdgpu_vm_pte_funcs *vm_pte_funcs; + struct amdgpu_ring *vm_pte_funcs_ring; +}; + +/* + * context related structures + */ + +struct amdgpu_ctx_state { + uint64_t flags; + uint64_t hangs; +}; + +struct amdgpu_ctx { + /* call kref_get()before CS start and kref_put() after CS fence signaled */ + struct kref refcount; + struct amdgpu_fpriv *fpriv; + struct amdgpu_ctx_state state; + uint32_t id; +}; + +struct amdgpu_ctx_mgr { + struct amdgpu_device *adev; + struct idr ctx_handles; + /* lock for IDR system */ + struct mutex hlock; +}; + +/* + * file private structure + */ + +struct amdgpu_fpriv { + struct amdgpu_vm vm; + struct mutex bo_list_lock; + struct idr bo_list_handles; + struct amdgpu_ctx_mgr ctx_mgr; +}; + +/* + * residency list + */ + +struct amdgpu_bo_list { + struct mutex lock; + struct amdgpu_bo *gds_obj; + struct amdgpu_bo *gws_obj; + struct amdgpu_bo *oa_obj; + bool has_userptr; + unsigned num_entries; + struct amdgpu_bo_list_entry *array; +}; + +struct amdgpu_bo_list * +amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); +void amdgpu_bo_list_put(struct amdgpu_bo_list *list); +void amdgpu_bo_list_free(struct amdgpu_bo_list *list); + +/* + * GFX stuff + */ +#include "clearstate_defs.h" + +struct amdgpu_rlc { + /* for power gating */ + struct amdgpu_bo *save_restore_obj; + uint64_t save_restore_gpu_addr; + volatile uint32_t *sr_ptr; + const u32 *reg_list; + u32 reg_list_size; + /* for clear state */ + struct amdgpu_bo *clear_state_obj; + uint64_t clear_state_gpu_addr; + volatile uint32_t *cs_ptr; + const struct cs_section_def *cs_data; + u32 clear_state_size; + /* for cp tables */ + struct amdgpu_bo *cp_table_obj; + uint64_t cp_table_gpu_addr; + volatile uint32_t *cp_table_ptr; + u32 cp_table_size; +}; + +struct amdgpu_mec { + struct amdgpu_bo *hpd_eop_obj; + u64 hpd_eop_gpu_addr; + u32 num_pipe; + u32 num_mec; + u32 num_queue; +}; + +/* + * GPU scratch registers structures, functions & helpers + */ +struct amdgpu_scratch { + unsigned num_reg; + uint32_t reg_base; + bool free[32]; + uint32_t reg[32]; +}; + +/* + * GFX configurations + */ +struct amdgpu_gca_config { + unsigned max_shader_engines; + unsigned max_tile_pipes; + unsigned max_cu_per_sh; + unsigned max_sh_per_se; + unsigned max_backends_per_se; + unsigned max_texture_channel_caches; + unsigned max_gprs; + unsigned max_gs_threads; + unsigned max_hw_contexts; + unsigned sc_prim_fifo_size_frontend; + unsigned sc_prim_fifo_size_backend; + unsigned sc_hiz_tile_fifo_size; + unsigned sc_earlyz_tile_fifo_size; + + unsigned num_tile_pipes; + unsigned backend_enable_mask; + unsigned mem_max_burst_length_bytes; + unsigned mem_row_size_in_kb; + unsigned shader_engine_tile_size; + unsigned num_gpus; + unsigned multi_gpu_tile_size; + unsigned mc_arb_ramcfg; + unsigned gb_addr_config; + + uint32_t tile_mode_array[32]; + uint32_t macrotile_mode_array[16]; +}; + +struct amdgpu_gfx { + struct mutex gpu_clock_mutex; + struct amdgpu_gca_config config; + struct amdgpu_rlc rlc; + struct amdgpu_mec mec; + struct amdgpu_scratch scratch; + const struct firmware *me_fw; /* ME firmware */ + uint32_t me_fw_version; + const struct firmware *pfp_fw; /* PFP firmware */ + uint32_t pfp_fw_version; + const struct firmware *ce_fw; /* CE firmware */ + uint32_t ce_fw_version; + const struct firmware *rlc_fw; /* RLC firmware */ + uint32_t rlc_fw_version; + const struct firmware *mec_fw; /* MEC firmware */ + uint32_t mec_fw_version; + const struct firmware *mec2_fw; /* MEC2 firmware */ + uint32_t mec2_fw_version; + struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; + unsigned num_gfx_rings; + struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; + unsigned num_compute_rings; + struct amdgpu_irq_src eop_irq; + struct amdgpu_irq_src priv_reg_irq; + struct amdgpu_irq_src priv_inst_irq; + /* gfx status */ + uint32_t gfx_current_status; + /* sync signal for const engine */ + unsigned ce_sync_offs; +}; + +int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, + unsigned size, struct amdgpu_ib *ib); +void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); +int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, + struct amdgpu_ib *ib, void *owner); +int amdgpu_ib_pool_init(struct amdgpu_device *adev); +void amdgpu_ib_pool_fini(struct amdgpu_device *adev); +int amdgpu_ib_ring_tests(struct amdgpu_device *adev); +/* Ring access between begin & end cannot sleep */ +void amdgpu_ring_free_size(struct amdgpu_ring *ring); +int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); +int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); +void amdgpu_ring_commit(struct amdgpu_ring *ring); +void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); +void amdgpu_ring_undo(struct amdgpu_ring *ring); +void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); +void amdgpu_ring_lockup_update(struct amdgpu_ring *ring); +bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring); +unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, + uint32_t **data); +int amdgpu_ring_restore(struct amdgpu_ring *ring, + unsigned size, uint32_t *data); +int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, + unsigned ring_size, u32 nop, u32 align_mask, + struct amdgpu_irq_src *irq_src, unsigned irq_type, + enum amdgpu_ring_type ring_type); +void amdgpu_ring_fini(struct amdgpu_ring *ring); + +/* + * CS. + */ +struct amdgpu_cs_chunk { + uint32_t chunk_id; + uint32_t length_dw; + uint32_t *kdata; + void __user *user_ptr; +}; + +struct amdgpu_cs_parser { + struct amdgpu_device *adev; + struct drm_file *filp; + uint32_t ctx_id; + struct amdgpu_bo_list *bo_list; + /* chunks */ + unsigned nchunks; + struct amdgpu_cs_chunk *chunks; + /* relocations */ + struct amdgpu_bo_list_entry *vm_bos; + struct amdgpu_bo_list_entry *ib_bos; + struct list_head validated; + + struct amdgpu_ib *ibs; + uint32_t num_ibs; + + struct ww_acquire_ctx ticket; + + /* user fence */ + struct amdgpu_user_fence uf; +}; + +static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) +{ + return p->ibs[ib_idx].ptr[idx]; +} + +/* + * Writeback + */ +#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ + +struct amdgpu_wb { + struct amdgpu_bo *wb_obj; + volatile uint32_t *wb; + uint64_t gpu_addr; + u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ + unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; +}; + +int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); +void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); + +/** + * struct amdgpu_pm - power management datas + * It keeps track of various data needed to take powermanagement decision. + */ + +enum amdgpu_pm_state_type { + /* not used for dpm */ + POWER_STATE_TYPE_DEFAULT, + POWER_STATE_TYPE_POWERSAVE, + /* user selectable states */ + POWER_STATE_TYPE_BATTERY, + POWER_STATE_TYPE_BALANCED, + POWER_STATE_TYPE_PERFORMANCE, + /* internal states */ + POWER_STATE_TYPE_INTERNAL_UVD, + POWER_STATE_TYPE_INTERNAL_UVD_SD, + POWER_STATE_TYPE_INTERNAL_UVD_HD, + POWER_STATE_TYPE_INTERNAL_UVD_HD2, + POWER_STATE_TYPE_INTERNAL_UVD_MVC, + POWER_STATE_TYPE_INTERNAL_BOOT, + POWER_STATE_TYPE_INTERNAL_THERMAL, + POWER_STATE_TYPE_INTERNAL_ACPI, + POWER_STATE_TYPE_INTERNAL_ULV, + POWER_STATE_TYPE_INTERNAL_3DPERF, +}; + +enum amdgpu_int_thermal_type { + THERMAL_TYPE_NONE, + THERMAL_TYPE_EXTERNAL, + THERMAL_TYPE_EXTERNAL_GPIO, + THERMAL_TYPE_RV6XX, + THERMAL_TYPE_RV770, + THERMAL_TYPE_ADT7473_WITH_INTERNAL, + THERMAL_TYPE_EVERGREEN, + THERMAL_TYPE_SUMO, + THERMAL_TYPE_NI, + THERMAL_TYPE_SI, + THERMAL_TYPE_EMC2103_WITH_INTERNAL, + THERMAL_TYPE_CI, + THERMAL_TYPE_KV, +}; + +enum amdgpu_dpm_auto_throttle_src { + AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, + AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL +}; + +enum amdgpu_dpm_event_src { + AMDGPU_DPM_EVENT_SRC_ANALOG = 0, + AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, + AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, + AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, + AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 +}; + +#define AMDGPU_MAX_VCE_LEVELS 6 + +enum amdgpu_vce_level { + AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ + AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ + AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ + AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ + AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ + AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ +}; + +struct amdgpu_ps { + u32 caps; /* vbios flags */ + u32 class; /* vbios flags */ + u32 class2; /* vbios flags */ + /* UVD clocks */ + u32 vclk; + u32 dclk; + /* VCE clocks */ + u32 evclk; + u32 ecclk; + bool vce_active; + enum amdgpu_vce_level vce_level; + /* asic priv */ + void *ps_priv; +}; + +struct amdgpu_dpm_thermal { + /* thermal interrupt work */ + struct work_struct work; + /* low temperature threshold */ + int min_temp; + /* high temperature threshold */ + int max_temp; + /* was last interrupt low to high or high to low */ + bool high_to_low; + /* interrupt source */ + struct amdgpu_irq_src irq; +}; + +enum amdgpu_clk_action +{ + AMDGPU_SCLK_UP = 1, + AMDGPU_SCLK_DOWN +}; + +struct amdgpu_blacklist_clocks +{ + u32 sclk; + u32 mclk; + enum amdgpu_clk_action action; +}; + +struct amdgpu_clock_and_voltage_limits { + u32 sclk; + u32 mclk; + u16 vddc; + u16 vddci; +}; + +struct amdgpu_clock_array { + u32 count; + u32 *values; +}; + +struct amdgpu_clock_voltage_dependency_entry { + u32 clk; + u16 v; +}; + +struct amdgpu_clock_voltage_dependency_table { + u32 count; + struct amdgpu_clock_voltage_dependency_entry *entries; +}; + +union amdgpu_cac_leakage_entry { + struct { + u16 vddc; + u32 leakage; + }; + struct { + u16 vddc1; + u16 vddc2; + u16 vddc3; + }; +}; + +struct amdgpu_cac_leakage_table { + u32 count; + union amdgpu_cac_leakage_entry *entries; +}; + +struct amdgpu_phase_shedding_limits_entry { + u16 voltage; + u32 sclk; + u32 mclk; +}; + +struct amdgpu_phase_shedding_limits_table { + u32 count; + struct amdgpu_phase_shedding_limits_entry *entries; +}; + +struct amdgpu_uvd_clock_voltage_dependency_entry { + u32 vclk; + u32 dclk; + u16 v; +}; + +struct amdgpu_uvd_clock_voltage_dependency_table { + u8 count; + struct amdgpu_uvd_clock_voltage_dependency_entry *entries; +}; + +struct amdgpu_vce_clock_voltage_dependency_entry { + u32 ecclk; + u32 evclk; + u16 v; +}; + +struct amdgpu_vce_clock_voltage_dependency_table { + u8 count; + struct amdgpu_vce_clock_voltage_dependency_entry *entries; +}; + +struct amdgpu_ppm_table { + u8 ppm_design; + u16 cpu_core_number; + u32 platform_tdp; + u32 small_ac_platform_tdp; + u32 platform_tdc; + u32 small_ac_platform_tdc; + u32 apu_tdp; + u32 dgpu_tdp; + u32 dgpu_ulv_power; + u32 tj_max; +}; + +struct amdgpu_cac_tdp_table { + u16 tdp; + u16 configurable_tdp; + u16 tdc; + u16 battery_power_limit; + u16 small_power_limit; + u16 low_cac_leakage; + u16 high_cac_leakage; + u16 maximum_power_delivery_limit; +}; + +struct amdgpu_dpm_dynamic_state { + struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; + struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; + struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; + struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; + struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; + struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; + struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; + struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; + struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; + struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; + struct amdgpu_clock_array valid_sclk_values; + struct amdgpu_clock_array valid_mclk_values; + struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; + struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; + u32 mclk_sclk_ratio; + u32 sclk_mclk_delta; + u16 vddc_vddci_delta; + u16 min_vddc_for_pcie_gen2; + struct amdgpu_cac_leakage_table cac_leakage_table; + struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; + struct amdgpu_ppm_table *ppm_table; + struct amdgpu_cac_tdp_table *cac_tdp_table; +}; + +struct amdgpu_dpm_fan { + u16 t_min; + u16 t_med; + u16 t_high; + u16 pwm_min; + u16 pwm_med; + u16 pwm_high; + u8 t_hyst; + u32 cycle_delay; + u16 t_max; + u8 control_mode; + u16 default_max_fan_pwm; + u16 default_fan_output_sensitivity; + u16 fan_output_sensitivity; + bool ucode_fan_control; +}; + +enum amdgpu_pcie_gen { + AMDGPU_PCIE_GEN1 = 0, + AMDGPU_PCIE_GEN2 = 1, + AMDGPU_PCIE_GEN3 = 2, + AMDGPU_PCIE_GEN_INVALID = 0xffff +}; + +enum amdgpu_dpm_forced_level { + AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, + AMDGPU_DPM_FORCED_LEVEL_LOW = 1, + AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, +}; + +struct amdgpu_vce_state { + /* vce clocks */ + u32 evclk; + u32 ecclk; + /* gpu clocks */ + u32 sclk; + u32 mclk; + u8 clk_idx; + u8 pstate; +}; + +struct amdgpu_dpm_funcs { + int (*get_temperature)(struct amdgpu_device *adev); + int (*pre_set_power_state)(struct amdgpu_device *adev); + int (*set_power_state)(struct amdgpu_device *adev); + void (*post_set_power_state)(struct amdgpu_device *adev); + void (*display_configuration_changed)(struct amdgpu_device *adev); + u32 (*get_sclk)(struct amdgpu_device *adev, bool low); + u32 (*get_mclk)(struct amdgpu_device *adev, bool low); + void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); + void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); + int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); + bool (*vblank_too_short)(struct amdgpu_device *adev); + void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); + void (*enable_bapm)(struct amdgpu_device *adev, bool enable); + void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); + u32 (*get_fan_control_mode)(struct amdgpu_device *adev); + int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); + int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); +}; + +struct amdgpu_dpm { + struct amdgpu_ps *ps; + /* number of valid power states */ + int num_ps; + /* current power state that is active */ + struct amdgpu_ps *current_ps; + /* requested power state */ + struct amdgpu_ps *requested_ps; + /* boot up power state */ + struct amdgpu_ps *boot_ps; + /* default uvd power state */ + struct amdgpu_ps *uvd_ps; + /* vce requirements */ + struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; + enum amdgpu_vce_level vce_level; + enum amdgpu_pm_state_type state; + enum amdgpu_pm_state_type user_state; + u32 platform_caps; + u32 voltage_response_time; + u32 backbias_response_time; + void *priv; + u32 new_active_crtcs; + int new_active_crtc_count; + u32 current_active_crtcs; + int current_active_crtc_count; + struct amdgpu_dpm_dynamic_state dyn_state; + struct amdgpu_dpm_fan fan; + u32 tdp_limit; + u32 near_tdp_limit; + u32 near_tdp_limit_adjusted; + u32 sq_ramping_threshold; + u32 cac_leakage; + u16 tdp_od_limit; + u32 tdp_adjustment; + u16 load_line_slope; + bool power_control; + bool ac_power; + /* special states active */ + bool thermal_active; + bool uvd_active; + bool vce_active; + /* thermal handling */ + struct amdgpu_dpm_thermal thermal; + /* forced levels */ + enum amdgpu_dpm_forced_level forced_level; +}; + +struct amdgpu_pm { + struct mutex mutex; + /* write locked while reprogramming mclk */ + struct rw_semaphore mclk_lock; + u32 current_sclk; + u32 current_mclk; + u32 default_sclk; + u32 default_mclk; + struct amdgpu_i2c_chan *i2c_bus; + /* internal thermal controller on rv6xx+ */ + enum amdgpu_int_thermal_type int_thermal_type; + struct device *int_hwmon_dev; + /* fan control parameters */ + bool no_fan; + u8 fan_pulses_per_revolution; + u8 fan_min_rpm; + u8 fan_max_rpm; + /* dpm */ + bool dpm_enabled; + struct amdgpu_dpm dpm; + const struct firmware *fw; /* SMC firmware */ + uint32_t fw_version; + const struct amdgpu_dpm_funcs *funcs; +}; + +/* + * UVD + */ +#define AMDGPU_MAX_UVD_HANDLES 10 +#define AMDGPU_UVD_STACK_SIZE (1024*1024) +#define AMDGPU_UVD_HEAP_SIZE (1024*1024) +#define AMDGPU_UVD_FIRMWARE_OFFSET 256 + +struct amdgpu_uvd { + struct amdgpu_bo *vcpu_bo; + void *cpu_addr; + uint64_t gpu_addr; + void *saved_bo; + atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; + struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; + struct delayed_work idle_work; + const struct firmware *fw; /* UVD firmware */ + struct amdgpu_ring ring; + struct amdgpu_irq_src irq; + bool address_64_bit; +}; + +/* + * VCE + */ +#define AMDGPU_MAX_VCE_HANDLES 16 +#define AMDGPU_VCE_STACK_SIZE (1024*1024) +#define AMDGPU_VCE_HEAP_SIZE (4*1024*1024) +#define AMDGPU_VCE_FIRMWARE_OFFSET 256 + +struct amdgpu_vce { + struct amdgpu_bo *vcpu_bo; + uint64_t gpu_addr; + unsigned fw_version; + unsigned fb_version; + atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; + struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; + struct delayed_work idle_work; + const struct firmware *fw; /* VCE firmware */ + struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; + struct amdgpu_irq_src irq; +}; + +/* + * SDMA + */ +struct amdgpu_sdma { + /* SDMA firmware */ + const struct firmware *fw; + uint32_t fw_version; + + struct amdgpu_ring ring; +}; + +/* + * Firmware + */ +struct amdgpu_firmware { + struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; + bool smu_load; + struct amdgpu_bo *fw_buf; + unsigned int fw_size; +}; + +/* + * Benchmarking + */ +void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); + + +/* + * Testing + */ +void amdgpu_test_moves(struct amdgpu_device *adev); +void amdgpu_test_ring_sync(struct amdgpu_device *adev, + struct amdgpu_ring *cpA, + struct amdgpu_ring *cpB); +void amdgpu_test_syncing(struct amdgpu_device *adev); + +/* + * MMU Notifier + */ +#if defined(CONFIG_MMU_NOTIFIER) +int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); +void amdgpu_mn_unregister(struct amdgpu_bo *bo); +#else +static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +{ + return -ENODEV; +} +static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} +#endif + +/* + * Debugfs + */ +struct amdgpu_debugfs { + struct drm_info_list *files; + unsigned num_files; +}; + +int amdgpu_debugfs_add_files(struct amdgpu_device *adev, + struct drm_info_list *files, + unsigned nfiles); +int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); + +#if defined(CONFIG_DEBUG_FS) +int amdgpu_debugfs_init(struct drm_minor *minor); +void amdgpu_debugfs_cleanup(struct drm_minor *minor); +#endif + +/* + * amdgpu smumgr functions + */ +struct amdgpu_smumgr_funcs { + int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); + int (*request_smu_load_fw)(struct amdgpu_device *adev); + int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); +}; + +/* + * amdgpu smumgr + */ +struct amdgpu_smumgr { + struct amdgpu_bo *toc_buf; + struct amdgpu_bo *smu_buf; + /* asic priv smu data */ + void *priv; + spinlock_t smu_lock; + /* smumgr functions */ + const struct amdgpu_smumgr_funcs *smumgr_funcs; + /* ucode loading complete flag */ + uint32_t fw_flags; +}; + +/* + * ASIC specific register table accessible by UMD + */ +struct amdgpu_allowed_register_entry { + uint32_t reg_offset; + bool untouched; + bool grbm_indexed; +}; + +struct amdgpu_cu_info { + uint32_t number; /* total active CU number */ + uint32_t ao_cu_mask; + uint32_t bitmap[4][4]; +}; + + +/* + * ASIC specific functions. + */ +struct amdgpu_asic_funcs { + bool (*read_disabled_bios)(struct amdgpu_device *adev); + int (*read_register)(struct amdgpu_device *adev, u32 se_num, + u32 sh_num, u32 reg_offset, u32 *value); + void (*set_vga_state)(struct amdgpu_device *adev, bool state); + int (*reset)(struct amdgpu_device *adev); + /* wait for mc_idle */ + int (*wait_for_mc_idle)(struct amdgpu_device *adev); + /* get the reference clock */ + u32 (*get_xclk)(struct amdgpu_device *adev); + /* get the gpu clock counter */ + uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); + int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); + /* MM block clocks */ + int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); + int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); +}; + +/* + * IOCTL. + */ +int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); +int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + +int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); +int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); +int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); +int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); +int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); +int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); +int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); + +int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + +/* VRAM scratch page for HDP bug, default vram page */ +struct amdgpu_vram_scratch { + struct amdgpu_bo *robj; + volatile uint32_t *ptr; + u64 gpu_addr; +}; + +/* + * ACPI + */ +struct amdgpu_atif_notification_cfg { + bool enabled; + int command_code; +}; + +struct amdgpu_atif_notifications { + bool display_switch; + bool expansion_mode_change; + bool thermal_state; + bool forced_power_state; + bool system_power_state; + bool display_conf_change; + bool px_gfx_switch; + bool brightness_change; + bool dgpu_display_event; +}; + +struct amdgpu_atif_functions { + bool system_params; + bool sbios_requests; + bool select_active_disp; + bool lid_state; + bool get_tv_standard; + bool set_tv_standard; + bool get_panel_expansion_mode; + bool set_panel_expansion_mode; + bool temperature_change; + bool graphics_device_types; +}; + +struct amdgpu_atif { + struct amdgpu_atif_notifications notifications; + struct amdgpu_atif_functions functions; + struct amdgpu_atif_notification_cfg notification_cfg; + struct amdgpu_encoder *encoder_for_bl; +}; + +struct amdgpu_atcs_functions { + bool get_ext_state; + bool pcie_perf_req; + bool pcie_dev_rdy; + bool pcie_bus_width; +}; + +struct amdgpu_atcs { + struct amdgpu_atcs_functions functions; +}; + +int amdgpu_ctx_alloc(struct amdgpu_device *adev,struct amdgpu_fpriv *fpriv, + uint32_t *id,uint32_t flags); +int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, + uint32_t id); +int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, + uint32_t id,struct amdgpu_ctx_state *state); + +void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv); + +extern int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + +/* + * Core structure, functions and helpers. + */ +typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); +typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); + +typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); +typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); + +struct amdgpu_device { + struct device *dev; + struct drm_device *ddev; + struct pci_dev *pdev; + struct rw_semaphore exclusive_lock; + + /* ASIC */ + enum amdgpu_asic_type asic_type; + uint32_t family; + uint32_t rev_id; + uint32_t external_rev_id; + unsigned long flags; + int usec_timeout; + const struct amdgpu_asic_funcs *asic_funcs; + bool shutdown; + bool suspend; + bool need_dma32; + bool accel_working; + bool needs_reset; + struct work_struct reset_work; + struct notifier_block acpi_nb; + struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; + struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; + unsigned debugfs_count; +#if defined(CONFIG_DEBUG_FS) + struct dentry *debugfs_regs; +#endif + struct amdgpu_atif atif; + struct amdgpu_atcs atcs; + struct mutex srbm_mutex; + /* GRBM index mutex. Protects concurrent access to GRBM index */ + struct mutex grbm_idx_mutex; + struct dev_pm_domain vga_pm_domain; + bool have_disp_power_ref; + + /* BIOS */ + uint8_t *bios; + bool is_atom_bios; + uint16_t bios_header_start; + struct amdgpu_bo *stollen_vga_memory; + uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; + + /* Register/doorbell mmio */ + resource_size_t rmmio_base; + resource_size_t rmmio_size; + void __iomem *rmmio; + /* protects concurrent MM_INDEX/DATA based register access */ + spinlock_t mmio_idx_lock; + /* protects concurrent SMC based register access */ + spinlock_t smc_idx_lock; + amdgpu_rreg_t smc_rreg; + amdgpu_wreg_t smc_wreg; + /* protects concurrent PCIE register access */ + spinlock_t pcie_idx_lock; + amdgpu_rreg_t pcie_rreg; + amdgpu_wreg_t pcie_wreg; + /* protects concurrent UVD register access */ + spinlock_t uvd_ctx_idx_lock; + amdgpu_rreg_t uvd_ctx_rreg; + amdgpu_wreg_t uvd_ctx_wreg; + /* protects concurrent DIDT register access */ + spinlock_t didt_idx_lock; + amdgpu_rreg_t didt_rreg; + amdgpu_wreg_t didt_wreg; + /* protects concurrent ENDPOINT (audio) register access */ + spinlock_t audio_endpt_idx_lock; + amdgpu_block_rreg_t audio_endpt_rreg; + amdgpu_block_wreg_t audio_endpt_wreg; + void __iomem *rio_mem; + resource_size_t rio_mem_size; + struct amdgpu_doorbell doorbell; + + /* clock/pll info */ + struct amdgpu_clock clock; + + /* MC */ + struct amdgpu_mc mc; + struct amdgpu_gart gart; + struct amdgpu_dummy_page dummy_page; + struct amdgpu_vm_manager vm_manager; + + /* memory management */ + struct amdgpu_mman mman; + struct amdgpu_gem gem; + struct amdgpu_vram_scratch vram_scratch; + struct amdgpu_wb wb; + atomic64_t vram_usage; + atomic64_t vram_vis_usage; + atomic64_t gtt_usage; + atomic64_t num_bytes_moved; + + /* display */ + struct amdgpu_mode_info mode_info; + struct work_struct hotplug_work; + struct amdgpu_irq_src crtc_irq; + struct amdgpu_irq_src pageflip_irq; + struct amdgpu_irq_src hpd_irq; + + /* rings */ + wait_queue_head_t fence_queue; + unsigned fence_context; + struct mutex ring_lock; + unsigned num_rings; + struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; + bool ib_pool_ready; + struct amdgpu_sa_manager ring_tmp_bo; + + /* interrupts */ + struct amdgpu_irq irq; + + /* dpm */ + struct amdgpu_pm pm; + u32 cg_flags; + u32 pg_flags; + + /* amdgpu smumgr */ + struct amdgpu_smumgr smu; + + /* gfx */ + struct amdgpu_gfx gfx; + + /* sdma */ + struct amdgpu_sdma sdma[2]; + struct amdgpu_irq_src sdma_trap_irq; + struct amdgpu_irq_src sdma_illegal_inst_irq; + + /* uvd */ + bool has_uvd; + struct amdgpu_uvd uvd; + + /* vce */ + struct amdgpu_vce vce; + + /* firmwares */ + struct amdgpu_firmware firmware; + + /* GDS */ + struct amdgpu_gds gds; + + const struct amdgpu_ip_block_version *ip_blocks; + int num_ip_blocks; + bool *ip_block_enabled; + struct mutex mn_lock; + DECLARE_HASHTABLE(mn_hash, 7); + + /* tracking pinned memory */ + u64 vram_pin_size; + u64 gart_pin_size; +}; + +bool amdgpu_device_is_px(struct drm_device *dev); +int amdgpu_device_init(struct amdgpu_device *adev, + struct drm_device *ddev, + struct pci_dev *pdev, + uint32_t flags); +void amdgpu_device_fini(struct amdgpu_device *adev); +int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); + +uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, + bool always_indirect); +void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, + bool always_indirect); +u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); +void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); + +u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); +void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); + +/* + * Cast helper + */ +extern const struct fence_ops amdgpu_fence_ops; +static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) +{ + struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); + + if (__f->base.ops == &amdgpu_fence_ops) + return __f; + + return NULL; +} + +/* + * Registers read & write functions. + */ +#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) +#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) +#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) +#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) +#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) +#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) +#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) +#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) +#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) +#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) +#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) +#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) +#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) +#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) +#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) +#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) +#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) +#define WREG32_P(reg, val, mask) \ + do { \ + uint32_t tmp_ = RREG32(reg); \ + tmp_ &= (mask); \ + tmp_ |= ((val) & ~(mask)); \ + WREG32(reg, tmp_); \ + } while (0) +#define WREG32_AND(reg, and) WREG32_P(reg, 0, and) +#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) +#define WREG32_PLL_P(reg, val, mask) \ + do { \ + uint32_t tmp_ = RREG32_PLL(reg); \ + tmp_ &= (mask); \ + tmp_ |= ((val) & ~(mask)); \ + WREG32_PLL(reg, tmp_); \ + } while (0) +#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) +#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) +#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) + +#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) +#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) + +#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT +#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK + +#define REG_SET_FIELD(orig_val, reg, field, field_val) \ + (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ + (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) + +#define REG_GET_FIELD(value, reg, field) \ + (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) + +/* + * BIOS helpers. + */ +#define RBIOS8(i) (adev->bios[i]) +#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) +#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) + +/* + * RING helpers. + */ +static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) +{ + if (ring->count_dw <= 0) + DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); + ring->ring[ring->wptr++] = v; + ring->wptr &= ring->ptr_mask; + ring->count_dw--; + ring->ring_free_dw--; +} + +/* + * ASICs macro. + */ +#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) +#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) +#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) +#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) +#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) +#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) +#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) +#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) +#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) +#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) +#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) +#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) +#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) +#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) +#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) +#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) +#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) +#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) +#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) +#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r)) +#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) +#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) +#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) +#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) +#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) +#define amdgpu_ring_emit_fence(r, addr, seq, write64bit) (r)->funcs->emit_fence((r), (addr), (seq), (write64bit)) +#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) +#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) +#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) +#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) +#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) +#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) +#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) +#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) +#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) +#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) +#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) +#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) +#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) +#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) +#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) +#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) +#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) +#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) +#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) +#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) +#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) +#define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b)) +#define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b)) +#define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev)) +#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) +#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) +#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) +#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) +#define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l)) +#define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l)) +#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) +#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)) +#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) +#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) +#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) +#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) +#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) +#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) +#define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s)) +#define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s)) + +#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) + +/* Common functions */ +int amdgpu_gpu_reset(struct amdgpu_device *adev); +void amdgpu_pci_config_reset(struct amdgpu_device *adev); +bool amdgpu_card_posted(struct amdgpu_device *adev); +void amdgpu_update_display_priority(struct amdgpu_device *adev); +bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); +int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); +int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, + u32 ip_instance, u32 ring, + struct amdgpu_ring **out_ring); +void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); +bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); +int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, + uint32_t flags); +bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); +bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); +uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, + struct ttm_mem_reg *mem); +void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); +void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); +void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); +void amdgpu_program_register_sequence(struct amdgpu_device *adev, + const u32 *registers, + const u32 array_size); + +bool amdgpu_device_is_px(struct drm_device *dev); +/* atpx handler */ +#if defined(CONFIG_VGA_SWITCHEROO) +void amdgpu_register_atpx_handler(void); +void amdgpu_unregister_atpx_handler(void); +#else +static inline void amdgpu_register_atpx_handler(void) {} +static inline void amdgpu_unregister_atpx_handler(void) {} +#endif + +/* + * KMS + */ +extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; +extern int amdgpu_max_kms_ioctl; + +int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); +int amdgpu_driver_unload_kms(struct drm_device *dev); +void amdgpu_driver_lastclose_kms(struct drm_device *dev); +int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); +void amdgpu_driver_postclose_kms(struct drm_device *dev, + struct drm_file *file_priv); +void amdgpu_driver_preclose_kms(struct drm_device *dev, + struct drm_file *file_priv); +int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); +int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); +u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc); +int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc); +void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc); +int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, + int *max_error, + struct timeval *vblank_time, + unsigned flags); +long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg); + +/* + * vm + */ +int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); +void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); +struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct list_head *head); +struct amdgpu_fence *amdgpu_vm_grab_id(struct amdgpu_ring *ring, + struct amdgpu_vm *vm); +void amdgpu_vm_flush(struct amdgpu_ring *ring, + struct amdgpu_vm *vm, + struct amdgpu_fence *updates); +void amdgpu_vm_fence(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_fence *fence); +uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); +int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, + struct amdgpu_vm *vm); +int amdgpu_vm_clear_freed(struct amdgpu_device *adev, + struct amdgpu_vm *vm); +int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, + struct amdgpu_vm *vm); +int amdgpu_vm_bo_update(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + struct ttm_mem_reg *mem); +void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, + struct amdgpu_bo *bo); +struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, + struct amdgpu_bo *bo); +struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_bo *bo); +int amdgpu_vm_bo_map(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + uint64_t addr, uint64_t offset, + uint64_t size, uint32_t flags); +int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + uint64_t addr); +void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va); + +/* + * functions used by amdgpu_encoder.c + */ +struct amdgpu_afmt_acr { + u32 clock; + + int n_32khz; + int cts_32khz; + + int n_44_1khz; + int cts_44_1khz; + + int n_48khz; + int cts_48khz; + +}; + +struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); + +/* amdgpu_acpi.c */ +#if defined(CONFIG_ACPI) +int amdgpu_acpi_init(struct amdgpu_device *adev); +void amdgpu_acpi_fini(struct amdgpu_device *adev); +bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); +int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, + u8 perf_req, bool advertise); +int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); +#else +static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } +static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } +#endif + +struct amdgpu_bo_va_mapping * +amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, + uint64_t addr, struct amdgpu_bo **bo); + +#include "amdgpu_object.h" + +#endif -- cgit v1.2.3 From d38ceaf99ed015f2a0b9af3499791bd3a3daae21 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Apr 2015 16:55:21 -0400 Subject: drm/amdgpu: add core driver (v4) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the non-asic specific core driver code. v2: remove extra kconfig option v3: implement minor fixes from Fengguang Wu v4: fix cast in amdgpu_ucode.c Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/Kconfig | 21 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/amd/amdgpu/Kconfig | 17 + drivers/gpu/drm/amd/amdgpu/Makefile | 49 + drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 768 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h | 445 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c | 105 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 1598 +++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 206 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 572 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 221 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 359 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 268 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 1907 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h | 42 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 825 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 161 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1971 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 832 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 955 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 85 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 439 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h | 48 + drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 245 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 432 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1139 ++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 371 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h | 72 + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 735 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 72 + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 30 + drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c | 395 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h | 44 + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 345 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 216 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 62 + drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.c | 47 + drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 456 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 92 + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 674 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 319 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 586 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 646 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 196 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c | 350 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h | 38 + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 801 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h | 35 + drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 125 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 561 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 419 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c | 102 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 231 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 552 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 209 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c | 9 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1249 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 317 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 176 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 976 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 39 + drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 727 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 47 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1248 +++++++++++++ drivers/gpu/drm/amd/amdgpu/atom-bits.h | 48 + drivers/gpu/drm/amd/amdgpu/atom-names.h | 100 ++ drivers/gpu/drm/amd/amdgpu/atom-types.h | 42 + drivers/gpu/drm/amd/amdgpu/atom.c | 1408 +++++++++++++++ drivers/gpu/drm/amd/amdgpu/atom.h | 159 ++ drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 807 +++++++++ drivers/gpu/drm/amd/amdgpu/atombios_crtc.h | 58 + drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 774 ++++++++ drivers/gpu/drm/amd/amdgpu/atombios_dp.h | 42 + drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 2066 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/atombios_encoders.h | 73 + drivers/gpu/drm/amd/amdgpu/atombios_i2c.c | 158 ++ drivers/gpu/drm/amd/amdgpu/atombios_i2c.h | 31 + drivers/gpu/drm/amd/amdgpu/cikd.h | 550 ++++++ 78 files changed, 33596 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/Kconfig create mode 100644 drivers/gpu/drm/amd/amdgpu/Makefile create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_test.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c create mode 100644 drivers/gpu/drm/amd/amdgpu/atom-bits.h create mode 100644 drivers/gpu/drm/amd/amdgpu/atom-names.h create mode 100644 drivers/gpu/drm/amd/amdgpu/atom-types.h create mode 100644 drivers/gpu/drm/amd/amdgpu/atom.c create mode 100644 drivers/gpu/drm/amd/amdgpu/atom.h create mode 100644 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c create mode 100644 drivers/gpu/drm/amd/amdgpu/atombios_crtc.h create mode 100644 drivers/gpu/drm/amd/amdgpu/atombios_dp.c create mode 100644 drivers/gpu/drm/amd/amdgpu/atombios_dp.h create mode 100644 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c create mode 100644 drivers/gpu/drm/amd/amdgpu/atombios_encoders.h create mode 100644 drivers/gpu/drm/amd/amdgpu/atombios_i2c.c create mode 100644 drivers/gpu/drm/amd/amdgpu/atombios_i2c.h create mode 100644 drivers/gpu/drm/amd/amdgpu/cikd.h (limited to 'drivers') diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index d4b65457122d..c46ca311d8c3 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -120,6 +120,27 @@ config DRM_RADEON source "drivers/gpu/drm/radeon/Kconfig" +config DRM_AMDGPU + tristate "AMD GPU" + depends on DRM && PCI + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FW_LOADER + select DRM_KMS_HELPER + select DRM_KMS_FB_HELPER + select DRM_TTM + select POWER_SUPPLY + select HWMON + select BACKLIGHT_CLASS_DEVICE + select INTERVAL_TREE + help + Choose this option if you have a recent AMD Radeon graphics card. + + If M is selected, the module will be called amdgpu. + +source "drivers/gpu/drm/amd/amdgpu/Kconfig" + source "drivers/gpu/drm/nouveau/Kconfig" config DRM_I810 diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 15eb710ec114..5713d0534504 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_DRM_TDFX) += tdfx/ obj-$(CONFIG_DRM_R128) += r128/ obj-$(CONFIG_HSA_AMD) += amd/amdkfd/ obj-$(CONFIG_DRM_RADEON)+= radeon/ +obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/ obj-$(CONFIG_DRM_MGA) += mga/ obj-$(CONFIG_DRM_I810) += i810/ obj-$(CONFIG_DRM_I915) += i915/ diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig new file mode 100644 index 000000000000..b30fcfa4b1f2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -0,0 +1,17 @@ +config DRM_AMDGPU_CIK + bool "Enable amdgpu support for CIK parts" + depends on DRM_AMDGPU + help + Choose this option if you want to enable experimental support + for CIK asics. + + CIK is already supported in radeon. CIK support in amdgpu + is for experimentation and testing. + +config DRM_AMDGPU_USERPTR + bool "Always enable userptr write support" + depends on DRM_AMDGPU + select MMU_NOTIFIER + help + This option selects CONFIG_MMU_NOTIFIER if it isn't already + selected to enabled full userptr support. diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile new file mode 100644 index 000000000000..01276a592bc5 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -0,0 +1,49 @@ +# +# Makefile for the drm device driver. This driver provides support for the +# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. + +ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg + +amdgpu-y := amdgpu_drv.o + +# add KMS driver +amdgpu-y += amdgpu_device.o amdgpu_kms.o \ + amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \ + atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \ + amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \ + amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \ + amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o amdgpu_test.o \ + amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ + atombios_encoders.o amdgpu_semaphore.o amdgpu_sa.o atombios_i2c.o \ + amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ + amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o + +# add IH block +amdgpu-y += \ + amdgpu_irq.o \ + amdgpu_ih.o + +# add SMC block +amdgpu-y += \ + amdgpu_dpm.o + +# add GFX block +amdgpu-y += \ + amdgpu_gfx.o + +# add UVD block +amdgpu-y += \ + amdgpu_uvd.o + +# add VCE block +amdgpu-y += \ + amdgpu_vce.o + +amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o +amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o +amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o +amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o + +obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o + +CFLAGS_amdgpu_trace_points.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c new file mode 100644 index 000000000000..aef4a7aac0f7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -0,0 +1,768 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_acpi.h" +#include "atom.h" + +#define ACPI_AC_CLASS "ac_adapter" + +extern void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); + +struct atif_verify_interface { + u16 size; /* structure size in bytes (includes size field) */ + u16 version; /* version */ + u32 notification_mask; /* supported notifications mask */ + u32 function_bits; /* supported functions bit vector */ +} __packed; + +struct atif_system_params { + u16 size; /* structure size in bytes (includes size field) */ + u32 valid_mask; /* valid flags mask */ + u32 flags; /* flags */ + u8 command_code; /* notify command code */ +} __packed; + +struct atif_sbios_requests { + u16 size; /* structure size in bytes (includes size field) */ + u32 pending; /* pending sbios requests */ + u8 panel_exp_mode; /* panel expansion mode */ + u8 thermal_gfx; /* thermal state: target gfx controller */ + u8 thermal_state; /* thermal state: state id (0: exit state, non-0: state) */ + u8 forced_power_gfx; /* forced power state: target gfx controller */ + u8 forced_power_state; /* forced power state: state id */ + u8 system_power_src; /* system power source */ + u8 backlight_level; /* panel backlight level (0-255) */ +} __packed; + +#define ATIF_NOTIFY_MASK 0x3 +#define ATIF_NOTIFY_NONE 0 +#define ATIF_NOTIFY_81 1 +#define ATIF_NOTIFY_N 2 + +struct atcs_verify_interface { + u16 size; /* structure size in bytes (includes size field) */ + u16 version; /* version */ + u32 function_bits; /* supported functions bit vector */ +} __packed; + +#define ATCS_VALID_FLAGS_MASK 0x3 + +struct atcs_pref_req_input { + u16 size; /* structure size in bytes (includes size field) */ + u16 client_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */ + u16 valid_flags_mask; /* valid flags mask */ + u16 flags; /* flags */ + u8 req_type; /* request type */ + u8 perf_req; /* performance request */ +} __packed; + +struct atcs_pref_req_output { + u16 size; /* structure size in bytes (includes size field) */ + u8 ret_val; /* return value */ +} __packed; + +/* Call the ATIF method + */ +/** + * amdgpu_atif_call - call an ATIF method + * + * @handle: acpi handle + * @function: the ATIF function to execute + * @params: ATIF function params + * + * Executes the requested ATIF function (all asics). + * Returns a pointer to the acpi output buffer. + */ +static union acpi_object *amdgpu_atif_call(acpi_handle handle, int function, + struct acpi_buffer *params) +{ + acpi_status status; + union acpi_object atif_arg_elements[2]; + struct acpi_object_list atif_arg; + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + + atif_arg.count = 2; + atif_arg.pointer = &atif_arg_elements[0]; + + atif_arg_elements[0].type = ACPI_TYPE_INTEGER; + atif_arg_elements[0].integer.value = function; + + if (params) { + atif_arg_elements[1].type = ACPI_TYPE_BUFFER; + atif_arg_elements[1].buffer.length = params->length; + atif_arg_elements[1].buffer.pointer = params->pointer; + } else { + /* We need a second fake parameter */ + atif_arg_elements[1].type = ACPI_TYPE_INTEGER; + atif_arg_elements[1].integer.value = 0; + } + + status = acpi_evaluate_object(handle, "ATIF", &atif_arg, &buffer); + + /* Fail only if calling the method fails and ATIF is supported */ + if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { + DRM_DEBUG_DRIVER("failed to evaluate ATIF got %s\n", + acpi_format_exception(status)); + kfree(buffer.pointer); + return NULL; + } + + return buffer.pointer; +} + +/** + * amdgpu_atif_parse_notification - parse supported notifications + * + * @n: supported notifications struct + * @mask: supported notifications mask from ATIF + * + * Use the supported notifications mask from ATIF function + * ATIF_FUNCTION_VERIFY_INTERFACE to determine what notifications + * are supported (all asics). + */ +static void amdgpu_atif_parse_notification(struct amdgpu_atif_notifications *n, u32 mask) +{ + n->display_switch = mask & ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED; + n->expansion_mode_change = mask & ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED; + n->thermal_state = mask & ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED; + n->forced_power_state = mask & ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED; + n->system_power_state = mask & ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED; + n->display_conf_change = mask & ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED; + n->px_gfx_switch = mask & ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED; + n->brightness_change = mask & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED; + n->dgpu_display_event = mask & ATIF_DGPU_DISPLAY_EVENT_SUPPORTED; +} + +/** + * amdgpu_atif_parse_functions - parse supported functions + * + * @f: supported functions struct + * @mask: supported functions mask from ATIF + * + * Use the supported functions mask from ATIF function + * ATIF_FUNCTION_VERIFY_INTERFACE to determine what functions + * are supported (all asics). + */ +static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mask) +{ + f->system_params = mask & ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED; + f->sbios_requests = mask & ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED; + f->select_active_disp = mask & ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED; + f->lid_state = mask & ATIF_GET_LID_STATE_SUPPORTED; + f->get_tv_standard = mask & ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED; + f->set_tv_standard = mask & ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED; + f->get_panel_expansion_mode = mask & ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED; + f->set_panel_expansion_mode = mask & ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED; + f->temperature_change = mask & ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED; + f->graphics_device_types = mask & ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED; +} + +/** + * amdgpu_atif_verify_interface - verify ATIF + * + * @handle: acpi handle + * @atif: amdgpu atif struct + * + * Execute the ATIF_FUNCTION_VERIFY_INTERFACE ATIF function + * to initialize ATIF and determine what features are supported + * (all asics). + * returns 0 on success, error on failure. + */ +static int amdgpu_atif_verify_interface(acpi_handle handle, + struct amdgpu_atif *atif) +{ + union acpi_object *info; + struct atif_verify_interface output; + size_t size; + int err = 0; + + info = amdgpu_atif_call(handle, ATIF_FUNCTION_VERIFY_INTERFACE, NULL); + if (!info) + return -EIO; + + memset(&output, 0, sizeof(output)); + + size = *(u16 *) info->buffer.pointer; + if (size < 12) { + DRM_INFO("ATIF buffer is too small: %zu\n", size); + err = -EINVAL; + goto out; + } + size = min(sizeof(output), size); + + memcpy(&output, info->buffer.pointer, size); + + /* TODO: check version? */ + DRM_DEBUG_DRIVER("ATIF version %u\n", output.version); + + amdgpu_atif_parse_notification(&atif->notifications, output.notification_mask); + amdgpu_atif_parse_functions(&atif->functions, output.function_bits); + +out: + kfree(info); + return err; +} + +/** + * amdgpu_atif_get_notification_params - determine notify configuration + * + * @handle: acpi handle + * @n: atif notification configuration struct + * + * Execute the ATIF_FUNCTION_GET_SYSTEM_PARAMETERS ATIF function + * to determine if a notifier is used and if so which one + * (all asics). This is either Notify(VGA, 0x81) or Notify(VGA, n) + * where n is specified in the result if a notifier is used. + * Returns 0 on success, error on failure. + */ +static int amdgpu_atif_get_notification_params(acpi_handle handle, + struct amdgpu_atif_notification_cfg *n) +{ + union acpi_object *info; + struct atif_system_params params; + size_t size; + int err = 0; + + info = amdgpu_atif_call(handle, ATIF_FUNCTION_GET_SYSTEM_PARAMETERS, NULL); + if (!info) { + err = -EIO; + goto out; + } + + size = *(u16 *) info->buffer.pointer; + if (size < 10) { + err = -EINVAL; + goto out; + } + + memset(¶ms, 0, sizeof(params)); + size = min(sizeof(params), size); + memcpy(¶ms, info->buffer.pointer, size); + + DRM_DEBUG_DRIVER("SYSTEM_PARAMS: mask = %#x, flags = %#x\n", + params.flags, params.valid_mask); + params.flags = params.flags & params.valid_mask; + + if ((params.flags & ATIF_NOTIFY_MASK) == ATIF_NOTIFY_NONE) { + n->enabled = false; + n->command_code = 0; + } else if ((params.flags & ATIF_NOTIFY_MASK) == ATIF_NOTIFY_81) { + n->enabled = true; + n->command_code = 0x81; + } else { + if (size < 11) { + err = -EINVAL; + goto out; + } + n->enabled = true; + n->command_code = params.command_code; + } + +out: + DRM_DEBUG_DRIVER("Notification %s, command code = %#x\n", + (n->enabled ? "enabled" : "disabled"), + n->command_code); + kfree(info); + return err; +} + +/** + * amdgpu_atif_get_sbios_requests - get requested sbios event + * + * @handle: acpi handle + * @req: atif sbios request struct + * + * Execute the ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS ATIF function + * to determine what requests the sbios is making to the driver + * (all asics). + * Returns 0 on success, error on failure. + */ +static int amdgpu_atif_get_sbios_requests(acpi_handle handle, + struct atif_sbios_requests *req) +{ + union acpi_object *info; + size_t size; + int count = 0; + + info = amdgpu_atif_call(handle, ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS, NULL); + if (!info) + return -EIO; + + size = *(u16 *)info->buffer.pointer; + if (size < 0xd) { + count = -EINVAL; + goto out; + } + memset(req, 0, sizeof(*req)); + + size = min(sizeof(*req), size); + memcpy(req, info->buffer.pointer, size); + DRM_DEBUG_DRIVER("SBIOS pending requests: %#x\n", req->pending); + + count = hweight32(req->pending); + +out: + kfree(info); + return count; +} + +/** + * amdgpu_atif_handler - handle ATIF notify requests + * + * @adev: amdgpu_device pointer + * @event: atif sbios request struct + * + * Checks the acpi event and if it matches an atif event, + * handles it. + * Returns NOTIFY code + */ +int amdgpu_atif_handler(struct amdgpu_device *adev, + struct acpi_bus_event *event) +{ + struct amdgpu_atif *atif = &adev->atif; + struct atif_sbios_requests req; + acpi_handle handle; + int count; + + DRM_DEBUG_DRIVER("event, device_class = %s, type = %#x\n", + event->device_class, event->type); + + if (strcmp(event->device_class, ACPI_VIDEO_CLASS) != 0) + return NOTIFY_DONE; + + if (!atif->notification_cfg.enabled || + event->type != atif->notification_cfg.command_code) + /* Not our event */ + return NOTIFY_DONE; + + /* Check pending SBIOS requests */ + handle = ACPI_HANDLE(&adev->pdev->dev); + count = amdgpu_atif_get_sbios_requests(handle, &req); + + if (count <= 0) + return NOTIFY_DONE; + + DRM_DEBUG_DRIVER("ATIF: %d pending SBIOS requests\n", count); + + if (req.pending & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST) { + struct amdgpu_encoder *enc = atif->encoder_for_bl; + + if (enc) { + struct amdgpu_encoder_atom_dig *dig = enc->enc_priv; + + DRM_DEBUG_DRIVER("Changing brightness to %d\n", + req.backlight_level); + + amdgpu_display_backlight_set_level(adev, enc, req.backlight_level); + +#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) + backlight_force_update(dig->bl_dev, + BACKLIGHT_UPDATE_HOTKEY); +#endif + } + } + /* TODO: check other events */ + + /* We've handled the event, stop the notifier chain. The ACPI interface + * overloads ACPI_VIDEO_NOTIFY_PROBE, we don't want to send that to + * userspace if the event was generated only to signal a SBIOS + * request. + */ + return NOTIFY_BAD; +} + +/* Call the ATCS method + */ +/** + * amdgpu_atcs_call - call an ATCS method + * + * @handle: acpi handle + * @function: the ATCS function to execute + * @params: ATCS function params + * + * Executes the requested ATCS function (all asics). + * Returns a pointer to the acpi output buffer. + */ +static union acpi_object *amdgpu_atcs_call(acpi_handle handle, int function, + struct acpi_buffer *params) +{ + acpi_status status; + union acpi_object atcs_arg_elements[2]; + struct acpi_object_list atcs_arg; + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + + atcs_arg.count = 2; + atcs_arg.pointer = &atcs_arg_elements[0]; + + atcs_arg_elements[0].type = ACPI_TYPE_INTEGER; + atcs_arg_elements[0].integer.value = function; + + if (params) { + atcs_arg_elements[1].type = ACPI_TYPE_BUFFER; + atcs_arg_elements[1].buffer.length = params->length; + atcs_arg_elements[1].buffer.pointer = params->pointer; + } else { + /* We need a second fake parameter */ + atcs_arg_elements[1].type = ACPI_TYPE_INTEGER; + atcs_arg_elements[1].integer.value = 0; + } + + status = acpi_evaluate_object(handle, "ATCS", &atcs_arg, &buffer); + + /* Fail only if calling the method fails and ATIF is supported */ + if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { + DRM_DEBUG_DRIVER("failed to evaluate ATCS got %s\n", + acpi_format_exception(status)); + kfree(buffer.pointer); + return NULL; + } + + return buffer.pointer; +} + +/** + * amdgpu_atcs_parse_functions - parse supported functions + * + * @f: supported functions struct + * @mask: supported functions mask from ATCS + * + * Use the supported functions mask from ATCS function + * ATCS_FUNCTION_VERIFY_INTERFACE to determine what functions + * are supported (all asics). + */ +static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mask) +{ + f->get_ext_state = mask & ATCS_GET_EXTERNAL_STATE_SUPPORTED; + f->pcie_perf_req = mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED; + f->pcie_dev_rdy = mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED; + f->pcie_bus_width = mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED; +} + +/** + * amdgpu_atcs_verify_interface - verify ATCS + * + * @handle: acpi handle + * @atcs: amdgpu atcs struct + * + * Execute the ATCS_FUNCTION_VERIFY_INTERFACE ATCS function + * to initialize ATCS and determine what features are supported + * (all asics). + * returns 0 on success, error on failure. + */ +static int amdgpu_atcs_verify_interface(acpi_handle handle, + struct amdgpu_atcs *atcs) +{ + union acpi_object *info; + struct atcs_verify_interface output; + size_t size; + int err = 0; + + info = amdgpu_atcs_call(handle, ATCS_FUNCTION_VERIFY_INTERFACE, NULL); + if (!info) + return -EIO; + + memset(&output, 0, sizeof(output)); + + size = *(u16 *) info->buffer.pointer; + if (size < 8) { + DRM_INFO("ATCS buffer is too small: %zu\n", size); + err = -EINVAL; + goto out; + } + size = min(sizeof(output), size); + + memcpy(&output, info->buffer.pointer, size); + + /* TODO: check version? */ + DRM_DEBUG_DRIVER("ATCS version %u\n", output.version); + + amdgpu_atcs_parse_functions(&atcs->functions, output.function_bits); + +out: + kfree(info); + return err; +} + +/** + * amdgpu_acpi_is_pcie_performance_request_supported + * + * @adev: amdgpu_device pointer + * + * Check if the ATCS pcie_perf_req and pcie_dev_rdy methods + * are supported (all asics). + * returns true if supported, false if not. + */ +bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev) +{ + struct amdgpu_atcs *atcs = &adev->atcs; + + if (atcs->functions.pcie_perf_req && atcs->functions.pcie_dev_rdy) + return true; + + return false; +} + +/** + * amdgpu_acpi_pcie_notify_device_ready + * + * @adev: amdgpu_device pointer + * + * Executes the PCIE_DEVICE_READY_NOTIFICATION method + * (all asics). + * returns 0 on success, error on failure. + */ +int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev) +{ + acpi_handle handle; + union acpi_object *info; + struct amdgpu_atcs *atcs = &adev->atcs; + + /* Get the device handle */ + handle = ACPI_HANDLE(&adev->pdev->dev); + if (!handle) + return -EINVAL; + + if (!atcs->functions.pcie_dev_rdy) + return -EINVAL; + + info = amdgpu_atcs_call(handle, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION, NULL); + if (!info) + return -EIO; + + kfree(info); + + return 0; +} + +/** + * amdgpu_acpi_pcie_performance_request + * + * @adev: amdgpu_device pointer + * @perf_req: requested perf level (pcie gen speed) + * @advertise: set advertise caps flag if set + * + * Executes the PCIE_PERFORMANCE_REQUEST method to + * change the pcie gen speed (all asics). + * returns 0 on success, error on failure. + */ +int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, + u8 perf_req, bool advertise) +{ + acpi_handle handle; + union acpi_object *info; + struct amdgpu_atcs *atcs = &adev->atcs; + struct atcs_pref_req_input atcs_input; + struct atcs_pref_req_output atcs_output; + struct acpi_buffer params; + size_t size; + u32 retry = 3; + + /* Get the device handle */ + handle = ACPI_HANDLE(&adev->pdev->dev); + if (!handle) + return -EINVAL; + + if (!atcs->functions.pcie_perf_req) + return -EINVAL; + + atcs_input.size = sizeof(struct atcs_pref_req_input); + /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */ + atcs_input.client_id = adev->pdev->devfn | (adev->pdev->bus->number << 8); + atcs_input.valid_flags_mask = ATCS_VALID_FLAGS_MASK; + atcs_input.flags = ATCS_WAIT_FOR_COMPLETION; + if (advertise) + atcs_input.flags |= ATCS_ADVERTISE_CAPS; + atcs_input.req_type = ATCS_PCIE_LINK_SPEED; + atcs_input.perf_req = perf_req; + + params.length = sizeof(struct atcs_pref_req_input); + params.pointer = &atcs_input; + + while (retry--) { + info = amdgpu_atcs_call(handle, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST, ¶ms); + if (!info) + return -EIO; + + memset(&atcs_output, 0, sizeof(atcs_output)); + + size = *(u16 *) info->buffer.pointer; + if (size < 3) { + DRM_INFO("ATCS buffer is too small: %zu\n", size); + kfree(info); + return -EINVAL; + } + size = min(sizeof(atcs_output), size); + + memcpy(&atcs_output, info->buffer.pointer, size); + + kfree(info); + + switch (atcs_output.ret_val) { + case ATCS_REQUEST_REFUSED: + default: + return -EINVAL; + case ATCS_REQUEST_COMPLETE: + return 0; + case ATCS_REQUEST_IN_PROGRESS: + udelay(10); + break; + } + } + + return 0; +} + +/** + * amdgpu_acpi_event - handle notify events + * + * @nb: notifier block + * @val: val + * @data: acpi event + * + * Calls relevant amdgpu functions in response to various + * acpi events. + * Returns NOTIFY code + */ +static int amdgpu_acpi_event(struct notifier_block *nb, + unsigned long val, + void *data) +{ + struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, acpi_nb); + struct acpi_bus_event *entry = (struct acpi_bus_event *)data; + + if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) { + if (power_supply_is_system_supplied() > 0) + DRM_DEBUG_DRIVER("pm: AC\n"); + else + DRM_DEBUG_DRIVER("pm: DC\n"); + + amdgpu_pm_acpi_event_handler(adev); + } + + /* Check for pending SBIOS requests */ + return amdgpu_atif_handler(adev, entry); +} + +/* Call all ACPI methods here */ +/** + * amdgpu_acpi_init - init driver acpi support + * + * @adev: amdgpu_device pointer + * + * Verifies the AMD ACPI interfaces and registers with the acpi + * notifier chain (all asics). + * Returns 0 on success, error on failure. + */ +int amdgpu_acpi_init(struct amdgpu_device *adev) +{ + acpi_handle handle; + struct amdgpu_atif *atif = &adev->atif; + struct amdgpu_atcs *atcs = &adev->atcs; + int ret; + + /* Get the device handle */ + handle = ACPI_HANDLE(&adev->pdev->dev); + + if (!adev->bios || !handle) + return 0; + + /* Call the ATCS method */ + ret = amdgpu_atcs_verify_interface(handle, atcs); + if (ret) { + DRM_DEBUG_DRIVER("Call to ATCS verify_interface failed: %d\n", ret); + } + + /* Call the ATIF method */ + ret = amdgpu_atif_verify_interface(handle, atif); + if (ret) { + DRM_DEBUG_DRIVER("Call to ATIF verify_interface failed: %d\n", ret); + goto out; + } + + if (atif->notifications.brightness_change) { + struct drm_encoder *tmp; + + /* Find the encoder controlling the brightness */ + list_for_each_entry(tmp, &adev->ddev->mode_config.encoder_list, + head) { + struct amdgpu_encoder *enc = to_amdgpu_encoder(tmp); + + if ((enc->devices & (ATOM_DEVICE_LCD_SUPPORT)) && + enc->enc_priv) { + if (adev->is_atom_bios) { + struct amdgpu_encoder_atom_dig *dig = enc->enc_priv; + if (dig->bl_dev) { + atif->encoder_for_bl = enc; + break; + } + } + } + } + } + + if (atif->functions.sbios_requests && !atif->functions.system_params) { + /* XXX check this workraround, if sbios request function is + * present we have to see how it's configured in the system + * params + */ + atif->functions.system_params = true; + } + + if (atif->functions.system_params) { + ret = amdgpu_atif_get_notification_params(handle, + &atif->notification_cfg); + if (ret) { + DRM_DEBUG_DRIVER("Call to GET_SYSTEM_PARAMS failed: %d\n", + ret); + /* Disable notification */ + atif->notification_cfg.enabled = false; + } + } + +out: + adev->acpi_nb.notifier_call = amdgpu_acpi_event; + register_acpi_notifier(&adev->acpi_nb); + + return ret; +} + +/** + * amdgpu_acpi_fini - tear down driver acpi support + * + * @adev: amdgpu_device pointer + * + * Unregisters with the acpi notifier chain (all asics). + */ +void amdgpu_acpi_fini(struct amdgpu_device *adev) +{ + unregister_acpi_notifier(&adev->acpi_nb); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h new file mode 100644 index 000000000000..01a29c3d7011 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h @@ -0,0 +1,445 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef AMDGPU_ACPI_H +#define AMDGPU_ACPI_H + +struct amdgpu_device; +struct acpi_bus_event; + +int amdgpu_atif_handler(struct amdgpu_device *adev, + struct acpi_bus_event *event); + +/* AMD hw uses four ACPI control methods: + * 1. ATIF + * ARG0: (ACPI_INTEGER) function code + * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes + * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes + * ATIF provides an entry point for the gfx driver to interact with the sbios. + * The AMD ACPI notification mechanism uses Notify (VGA, 0x81) or a custom + * notification. Which notification is used as indicated by the ATIF Control + * Method GET_SYSTEM_PARAMETERS. When the driver receives Notify (VGA, 0x81) or + * a custom notification it invokes ATIF Control Method GET_SYSTEM_BIOS_REQUESTS + * to identify pending System BIOS requests and associated parameters. For + * example, if one of the pending requests is DISPLAY_SWITCH_REQUEST, the driver + * will perform display device detection and invoke ATIF Control Method + * SELECT_ACTIVE_DISPLAYS. + * + * 2. ATPX + * ARG0: (ACPI_INTEGER) function code + * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes + * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes + * ATPX methods are used on PowerXpress systems to handle mux switching and + * discrete GPU power control. + * + * 3. ATRM + * ARG0: (ACPI_INTEGER) offset of vbios rom data + * ARG1: (ACPI_BUFFER) size of the buffer to fill (up to 4K). + * OUTPUT: (ACPI_BUFFER) output buffer + * ATRM provides an interfacess to access the discrete GPU vbios image on + * PowerXpress systems with multiple GPUs. + * + * 4. ATCS + * ARG0: (ACPI_INTEGER) function code + * ARG1: (ACPI_BUFFER) parameter buffer, 256 bytes + * OUTPUT: (ACPI_BUFFER) output buffer, 256 bytes + * ATCS provides an interface to AMD chipset specific functionality. + * + */ +/* ATIF */ +#define ATIF_FUNCTION_VERIFY_INTERFACE 0x0 +/* ARG0: ATIF_FUNCTION_VERIFY_INTERFACE + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * WORD - version + * DWORD - supported notifications mask + * DWORD - supported functions bit vector + */ +/* Notifications mask */ +# define ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED (1 << 0) +# define ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED (1 << 1) +# define ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED (1 << 2) +# define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED (1 << 3) +# define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED (1 << 4) +# define ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED (1 << 5) +# define ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED (1 << 6) +# define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED (1 << 7) +# define ATIF_DGPU_DISPLAY_EVENT_SUPPORTED (1 << 8) +/* supported functions vector */ +# define ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED (1 << 0) +# define ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED (1 << 1) +# define ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED (1 << 2) +# define ATIF_GET_LID_STATE_SUPPORTED (1 << 3) +# define ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED (1 << 4) +# define ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED (1 << 5) +# define ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED (1 << 6) +# define ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED (1 << 7) +# define ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED (1 << 12) +# define ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED (1 << 14) +#define ATIF_FUNCTION_GET_SYSTEM_PARAMETERS 0x1 +/* ARG0: ATIF_FUNCTION_GET_SYSTEM_PARAMETERS + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * DWORD - valid flags mask + * DWORD - flags + * + * OR + * + * WORD - structure size in bytes (includes size field) + * DWORD - valid flags mask + * DWORD - flags + * BYTE - notify command code + * + * flags + * bits 1:0: + * 0 - Notify(VGA, 0x81) is not used for notification + * 1 - Notify(VGA, 0x81) is used for notification + * 2 - Notify(VGA, n) is used for notification where + * n (0xd0-0xd9) is specified in notify command code. + * bit 2: + * 1 - lid changes not reported though int10 + */ +#define ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS 0x2 +/* ARG0: ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * DWORD - pending sbios requests + * BYTE - panel expansion mode + * BYTE - thermal state: target gfx controller + * BYTE - thermal state: state id (0: exit state, non-0: state) + * BYTE - forced power state: target gfx controller + * BYTE - forced power state: state id + * BYTE - system power source + * BYTE - panel backlight level (0-255) + */ +/* pending sbios requests */ +# define ATIF_DISPLAY_SWITCH_REQUEST (1 << 0) +# define ATIF_EXPANSION_MODE_CHANGE_REQUEST (1 << 1) +# define ATIF_THERMAL_STATE_CHANGE_REQUEST (1 << 2) +# define ATIF_FORCED_POWER_STATE_CHANGE_REQUEST (1 << 3) +# define ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST (1 << 4) +# define ATIF_DISPLAY_CONF_CHANGE_REQUEST (1 << 5) +# define ATIF_PX_GFX_SWITCH_REQUEST (1 << 6) +# define ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST (1 << 7) +# define ATIF_DGPU_DISPLAY_EVENT (1 << 8) +/* panel expansion mode */ +# define ATIF_PANEL_EXPANSION_DISABLE 0 +# define ATIF_PANEL_EXPANSION_FULL 1 +# define ATIF_PANEL_EXPANSION_ASPECT 2 +/* target gfx controller */ +# define ATIF_TARGET_GFX_SINGLE 0 +# define ATIF_TARGET_GFX_PX_IGPU 1 +# define ATIF_TARGET_GFX_PX_DGPU 2 +/* system power source */ +# define ATIF_POWER_SOURCE_AC 1 +# define ATIF_POWER_SOURCE_DC 2 +# define ATIF_POWER_SOURCE_RESTRICTED_AC_1 3 +# define ATIF_POWER_SOURCE_RESTRICTED_AC_2 4 +#define ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS 0x3 +/* ARG0: ATIF_FUNCTION_SELECT_ACTIVE_DISPLAYS + * ARG1: + * WORD - structure size in bytes (includes size field) + * WORD - selected displays + * WORD - connected displays + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * WORD - selected displays + */ +# define ATIF_LCD1 (1 << 0) +# define ATIF_CRT1 (1 << 1) +# define ATIF_TV (1 << 2) +# define ATIF_DFP1 (1 << 3) +# define ATIF_CRT2 (1 << 4) +# define ATIF_LCD2 (1 << 5) +# define ATIF_DFP2 (1 << 7) +# define ATIF_CV (1 << 8) +# define ATIF_DFP3 (1 << 9) +# define ATIF_DFP4 (1 << 10) +# define ATIF_DFP5 (1 << 11) +# define ATIF_DFP6 (1 << 12) +#define ATIF_FUNCTION_GET_LID_STATE 0x4 +/* ARG0: ATIF_FUNCTION_GET_LID_STATE + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * BYTE - lid state (0: open, 1: closed) + * + * GET_LID_STATE only works at boot and resume, for general lid + * status, use the kernel provided status + */ +#define ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS 0x5 +/* ARG0: ATIF_FUNCTION_GET_TV_STANDARD_FROM_CMOS + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * BYTE - 0 + * BYTE - TV standard + */ +# define ATIF_TV_STD_NTSC 0 +# define ATIF_TV_STD_PAL 1 +# define ATIF_TV_STD_PALM 2 +# define ATIF_TV_STD_PAL60 3 +# define ATIF_TV_STD_NTSCJ 4 +# define ATIF_TV_STD_PALCN 5 +# define ATIF_TV_STD_PALN 6 +# define ATIF_TV_STD_SCART_RGB 9 +#define ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS 0x6 +/* ARG0: ATIF_FUNCTION_SET_TV_STANDARD_IN_CMOS + * ARG1: + * WORD - structure size in bytes (includes size field) + * BYTE - 0 + * BYTE - TV standard + * OUTPUT: none + */ +#define ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS 0x7 +/* ARG0: ATIF_FUNCTION_GET_PANEL_EXPANSION_MODE_FROM_CMOS + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * BYTE - panel expansion mode + */ +#define ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS 0x8 +/* ARG0: ATIF_FUNCTION_SET_PANEL_EXPANSION_MODE_IN_CMOS + * ARG1: + * WORD - structure size in bytes (includes size field) + * BYTE - panel expansion mode + * OUTPUT: none + */ +#define ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION 0xD +/* ARG0: ATIF_FUNCTION_TEMPERATURE_CHANGE_NOTIFICATION + * ARG1: + * WORD - structure size in bytes (includes size field) + * WORD - gfx controller id + * BYTE - current temperature (degress Celsius) + * OUTPUT: none + */ +#define ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES 0xF +/* ARG0: ATIF_FUNCTION_GET_GRAPHICS_DEVICE_TYPES + * ARG1: none + * OUTPUT: + * WORD - number of gfx devices + * WORD - device structure size in bytes (excludes device size field) + * DWORD - flags \ + * WORD - bus number } repeated structure + * WORD - device number / + */ +/* flags */ +# define ATIF_PX_REMOVABLE_GRAPHICS_DEVICE (1 << 0) +# define ATIF_XGP_PORT (1 << 1) +# define ATIF_VGA_ENABLED_GRAPHICS_DEVICE (1 << 2) +# define ATIF_XGP_PORT_IN_DOCK (1 << 3) + +/* ATPX */ +#define ATPX_FUNCTION_VERIFY_INTERFACE 0x0 +/* ARG0: ATPX_FUNCTION_VERIFY_INTERFACE + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * WORD - version + * DWORD - supported functions bit vector + */ +/* supported functions vector */ +# define ATPX_GET_PX_PARAMETERS_SUPPORTED (1 << 0) +# define ATPX_POWER_CONTROL_SUPPORTED (1 << 1) +# define ATPX_DISPLAY_MUX_CONTROL_SUPPORTED (1 << 2) +# define ATPX_I2C_MUX_CONTROL_SUPPORTED (1 << 3) +# define ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED (1 << 4) +# define ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED (1 << 5) +# define ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED (1 << 7) +# define ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED (1 << 8) +#define ATPX_FUNCTION_GET_PX_PARAMETERS 0x1 +/* ARG0: ATPX_FUNCTION_GET_PX_PARAMETERS + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * DWORD - valid flags mask + * DWORD - flags + */ +/* flags */ +# define ATPX_LVDS_I2C_AVAILABLE_TO_BOTH_GPUS (1 << 0) +# define ATPX_CRT1_I2C_AVAILABLE_TO_BOTH_GPUS (1 << 1) +# define ATPX_DVI1_I2C_AVAILABLE_TO_BOTH_GPUS (1 << 2) +# define ATPX_CRT1_RGB_SIGNAL_MUXED (1 << 3) +# define ATPX_TV_SIGNAL_MUXED (1 << 4) +# define ATPX_DFP_SIGNAL_MUXED (1 << 5) +# define ATPX_SEPARATE_MUX_FOR_I2C (1 << 6) +# define ATPX_DYNAMIC_PX_SUPPORTED (1 << 7) +# define ATPX_ACF_NOT_SUPPORTED (1 << 8) +# define ATPX_FIXED_NOT_SUPPORTED (1 << 9) +# define ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED (1 << 10) +# define ATPX_DGPU_REQ_POWER_FOR_DISPLAYS (1 << 11) +#define ATPX_FUNCTION_POWER_CONTROL 0x2 +/* ARG0: ATPX_FUNCTION_POWER_CONTROL + * ARG1: + * WORD - structure size in bytes (includes size field) + * BYTE - dGPU power state (0: power off, 1: power on) + * OUTPUT: none + */ +#define ATPX_FUNCTION_DISPLAY_MUX_CONTROL 0x3 +/* ARG0: ATPX_FUNCTION_DISPLAY_MUX_CONTROL + * ARG1: + * WORD - structure size in bytes (includes size field) + * WORD - display mux control (0: iGPU, 1: dGPU) + * OUTPUT: none + */ +# define ATPX_INTEGRATED_GPU 0 +# define ATPX_DISCRETE_GPU 1 +#define ATPX_FUNCTION_I2C_MUX_CONTROL 0x4 +/* ARG0: ATPX_FUNCTION_I2C_MUX_CONTROL + * ARG1: + * WORD - structure size in bytes (includes size field) + * WORD - i2c/aux/hpd mux control (0: iGPU, 1: dGPU) + * OUTPUT: none + */ +#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION 0x5 +/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION + * ARG1: + * WORD - structure size in bytes (includes size field) + * WORD - target gpu (0: iGPU, 1: dGPU) + * OUTPUT: none + */ +#define ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION 0x6 +/* ARG0: ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION + * ARG1: + * WORD - structure size in bytes (includes size field) + * WORD - target gpu (0: iGPU, 1: dGPU) + * OUTPUT: none + */ +#define ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING 0x8 +/* ARG0: ATPX_FUNCTION_GET_DISPLAY_CONNECTORS_MAPPING + * ARG1: none + * OUTPUT: + * WORD - number of display connectors + * WORD - connector structure size in bytes (excludes connector size field) + * BYTE - flags \ + * BYTE - ATIF display vector bit position } repeated + * BYTE - adapter id (0: iGPU, 1-n: dGPU ordered by pcie bus number) } structure + * WORD - connector ACPI id / + */ +/* flags */ +# define ATPX_DISPLAY_OUTPUT_SUPPORTED_BY_ADAPTER_ID_DEVICE (1 << 0) +# define ATPX_DISPLAY_HPD_SUPPORTED_BY_ADAPTER_ID_DEVICE (1 << 1) +# define ATPX_DISPLAY_I2C_SUPPORTED_BY_ADAPTER_ID_DEVICE (1 << 2) +#define ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS 0x9 +/* ARG0: ATPX_FUNCTION_GET_DISPLAY_DETECTION_PORTS + * ARG1: none + * OUTPUT: + * WORD - number of HPD/DDC ports + * WORD - port structure size in bytes (excludes port size field) + * BYTE - ATIF display vector bit position \ + * BYTE - hpd id } reapeated structure + * BYTE - ddc id / + * + * available on A+A systems only + */ +/* hpd id */ +# define ATPX_HPD_NONE 0 +# define ATPX_HPD1 1 +# define ATPX_HPD2 2 +# define ATPX_HPD3 3 +# define ATPX_HPD4 4 +# define ATPX_HPD5 5 +# define ATPX_HPD6 6 +/* ddc id */ +# define ATPX_DDC_NONE 0 +# define ATPX_DDC1 1 +# define ATPX_DDC2 2 +# define ATPX_DDC3 3 +# define ATPX_DDC4 4 +# define ATPX_DDC5 5 +# define ATPX_DDC6 6 +# define ATPX_DDC7 7 +# define ATPX_DDC8 8 + +/* ATCS */ +#define ATCS_FUNCTION_VERIFY_INTERFACE 0x0 +/* ARG0: ATCS_FUNCTION_VERIFY_INTERFACE + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * WORD - version + * DWORD - supported functions bit vector + */ +/* supported functions vector */ +# define ATCS_GET_EXTERNAL_STATE_SUPPORTED (1 << 0) +# define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED (1 << 1) +# define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED (1 << 2) +# define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED (1 << 3) +#define ATCS_FUNCTION_GET_EXTERNAL_STATE 0x1 +/* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * DWORD - valid flags mask + * DWORD - flags (0: undocked, 1: docked) + */ +/* flags */ +# define ATCS_DOCKED (1 << 0) +#define ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST 0x2 +/* ARG0: ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST + * ARG1: + * WORD - structure size in bytes (includes size field) + * WORD - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) + * WORD - valid flags mask + * WORD - flags + * BYTE - request type + * BYTE - performance request + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * BYTE - return value + */ +/* flags */ +# define ATCS_ADVERTISE_CAPS (1 << 0) +# define ATCS_WAIT_FOR_COMPLETION (1 << 1) +/* request type */ +# define ATCS_PCIE_LINK_SPEED 1 +/* performance request */ +# define ATCS_REMOVE 0 +# define ATCS_FORCE_LOW_POWER 1 +# define ATCS_PERF_LEVEL_1 2 /* PCIE Gen 1 */ +# define ATCS_PERF_LEVEL_2 3 /* PCIE Gen 2 */ +# define ATCS_PERF_LEVEL_3 4 /* PCIE Gen 3 */ +/* return value */ +# define ATCS_REQUEST_REFUSED 1 +# define ATCS_REQUEST_COMPLETE 2 +# define ATCS_REQUEST_IN_PROGRESS 3 +#define ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION 0x3 +/* ARG0: ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION + * ARG1: none + * OUTPUT: none + */ +#define ATCS_FUNCTION_SET_PCIE_BUS_WIDTH 0x4 +/* ARG0: ATCS_FUNCTION_SET_PCIE_BUS_WIDTH + * ARG1: + * WORD - structure size in bytes (includes size field) + * WORD - client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) + * BYTE - number of active lanes + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * BYTE - number of active lanes + */ + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c new file mode 100644 index 000000000000..857ba0897159 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c @@ -0,0 +1,105 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Christian König. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Christian König + */ +#include +#include +#include +#include +#include "amdgpu.h" + +static const struct amdgpu_afmt_acr amdgpu_afmt_predefined_acr[] = { + /* 32kHz 44.1kHz 48kHz */ + /* Clock N CTS N CTS N CTS */ + { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */ + { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ + { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ + { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ + { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ + { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ + { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */ + { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ + { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */ + { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ +}; + + +/* + * calculate CTS and N values if they are not found in the table + */ +static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) +{ + int n, cts; + unsigned long div, mul; + + /* Safe, but overly large values */ + n = 128 * freq; + cts = clock * 1000; + + /* Smallest valid fraction */ + div = gcd(n, cts); + + n /= div; + cts /= div; + + /* + * The optimal N is 128*freq/1000. Calculate the closest larger + * value that doesn't truncate any bits. + */ + mul = ((128*freq/1000) + (n-1))/n; + + n *= mul; + cts *= mul; + + /* Check that we are in spec (not always possible) */ + if (n < (128*freq/1500)) + printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n"); + if (n > (128*freq/300)) + printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n"); + + *N = n; + *CTS = cts; + + DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n", + *N, *CTS, freq); +} + +struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) +{ + struct amdgpu_afmt_acr res; + u8 i; + + /* Precalculated values for common clocks */ + for (i = 0; i < ARRAY_SIZE(amdgpu_afmt_predefined_acr); i++) { + if (amdgpu_afmt_predefined_acr[i].clock == clock) + return amdgpu_afmt_predefined_acr[i]; + } + + /* And odd clocks get manually calculated */ + amdgpu_afmt_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); + amdgpu_afmt_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); + amdgpu_afmt_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); + + return res; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c new file mode 100644 index 000000000000..6a588371d54a --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -0,0 +1,1598 @@ +/* + * Copyright 2007-8 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + */ +#include +#include +#include "amdgpu.h" +#include "amdgpu_atombios.h" +#include "amdgpu_i2c.h" + +#include "atom.h" +#include "atom-bits.h" +#include "atombios_encoders.h" +#include "bif/bif_4_1_d.h" + +static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev, + ATOM_GPIO_I2C_ASSIGMENT *gpio, + u8 index) +{ + +} + +static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) +{ + struct amdgpu_i2c_bus_rec i2c; + + memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); + + i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex); + i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex); + i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex); + i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex); + i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex); + i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex); + i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex); + i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex); + i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); + i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); + i2c.en_clk_mask = (1 << gpio->ucClkEnShift); + i2c.en_data_mask = (1 << gpio->ucDataEnShift); + i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); + i2c.y_data_mask = (1 << gpio->ucDataY_Shift); + i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); + i2c.a_data_mask = (1 << gpio->ucDataA_Shift); + + if (gpio->sucI2cId.sbfAccess.bfHW_Capable) + i2c.hw_capable = true; + else + i2c.hw_capable = false; + + if (gpio->sucI2cId.ucAccess == 0xa0) + i2c.mm_i2c = true; + else + i2c.mm_i2c = false; + + i2c.i2c_id = gpio->sucI2cId.ucAccess; + + if (i2c.mask_clk_reg) + i2c.valid = true; + else + i2c.valid = false; + + return i2c; +} + +struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev, + uint8_t id) +{ + struct atom_context *ctx = adev->mode_info.atom_context; + ATOM_GPIO_I2C_ASSIGMENT *gpio; + struct amdgpu_i2c_bus_rec i2c; + int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); + struct _ATOM_GPIO_I2C_INFO *i2c_info; + uint16_t data_offset, size; + int i, num_indices; + + memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); + i2c.valid = false; + + if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { + i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); + + num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / + sizeof(ATOM_GPIO_I2C_ASSIGMENT); + + gpio = &i2c_info->asGPIO_Info[0]; + for (i = 0; i < num_indices; i++) { + + amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); + + if (gpio->sucI2cId.ucAccess == id) { + i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); + break; + } + gpio = (ATOM_GPIO_I2C_ASSIGMENT *) + ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); + } + } + + return i2c; +} + +void amdgpu_atombios_i2c_init(struct amdgpu_device *adev) +{ + struct atom_context *ctx = adev->mode_info.atom_context; + ATOM_GPIO_I2C_ASSIGMENT *gpio; + struct amdgpu_i2c_bus_rec i2c; + int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); + struct _ATOM_GPIO_I2C_INFO *i2c_info; + uint16_t data_offset, size; + int i, num_indices; + char stmp[32]; + + if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { + i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); + + num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / + sizeof(ATOM_GPIO_I2C_ASSIGMENT); + + gpio = &i2c_info->asGPIO_Info[0]; + for (i = 0; i < num_indices; i++) { + amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); + + i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); + + if (i2c.valid) { + sprintf(stmp, "0x%x", i2c.i2c_id); + adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp); + } + gpio = (ATOM_GPIO_I2C_ASSIGMENT *) + ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); + } + } +} + +struct amdgpu_gpio_rec +amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev, + u8 id) +{ + struct atom_context *ctx = adev->mode_info.atom_context; + struct amdgpu_gpio_rec gpio; + int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); + struct _ATOM_GPIO_PIN_LUT *gpio_info; + ATOM_GPIO_PIN_ASSIGNMENT *pin; + u16 data_offset, size; + int i, num_indices; + + memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec)); + gpio.valid = false; + + if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { + gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); + + num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / + sizeof(ATOM_GPIO_PIN_ASSIGNMENT); + + pin = gpio_info->asGPIO_Pin; + for (i = 0; i < num_indices; i++) { + if (id == pin->ucGPIO_ID) { + gpio.id = pin->ucGPIO_ID; + gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex); + gpio.shift = pin->ucGpioPinBitShift; + gpio.mask = (1 << pin->ucGpioPinBitShift); + gpio.valid = true; + break; + } + pin = (ATOM_GPIO_PIN_ASSIGNMENT *) + ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); + } + } + + return gpio; +} + +static struct amdgpu_hpd +amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev, + struct amdgpu_gpio_rec *gpio) +{ + struct amdgpu_hpd hpd; + u32 reg; + + memset(&hpd, 0, sizeof(struct amdgpu_hpd)); + + reg = amdgpu_display_hpd_get_gpio_reg(adev); + + hpd.gpio = *gpio; + if (gpio->reg == reg) { + switch(gpio->mask) { + case (1 << 0): + hpd.hpd = AMDGPU_HPD_1; + break; + case (1 << 8): + hpd.hpd = AMDGPU_HPD_2; + break; + case (1 << 16): + hpd.hpd = AMDGPU_HPD_3; + break; + case (1 << 24): + hpd.hpd = AMDGPU_HPD_4; + break; + case (1 << 26): + hpd.hpd = AMDGPU_HPD_5; + break; + case (1 << 28): + hpd.hpd = AMDGPU_HPD_6; + break; + default: + hpd.hpd = AMDGPU_HPD_NONE; + break; + } + } else + hpd.hpd = AMDGPU_HPD_NONE; + return hpd; +} + +static bool amdgpu_atombios_apply_quirks(struct amdgpu_device *adev, + uint32_t supported_device, + int *connector_type, + struct amdgpu_i2c_bus_rec *i2c_bus, + uint16_t *line_mux, + struct amdgpu_hpd *hpd) +{ + return true; +} + +static const int object_connector_convert[] = { + DRM_MODE_CONNECTOR_Unknown, + DRM_MODE_CONNECTOR_DVII, + DRM_MODE_CONNECTOR_DVII, + DRM_MODE_CONNECTOR_DVID, + DRM_MODE_CONNECTOR_DVID, + DRM_MODE_CONNECTOR_VGA, + DRM_MODE_CONNECTOR_Composite, + DRM_MODE_CONNECTOR_SVIDEO, + DRM_MODE_CONNECTOR_Unknown, + DRM_MODE_CONNECTOR_Unknown, + DRM_MODE_CONNECTOR_9PinDIN, + DRM_MODE_CONNECTOR_Unknown, + DRM_MODE_CONNECTOR_HDMIA, + DRM_MODE_CONNECTOR_HDMIB, + DRM_MODE_CONNECTOR_LVDS, + DRM_MODE_CONNECTOR_9PinDIN, + DRM_MODE_CONNECTOR_Unknown, + DRM_MODE_CONNECTOR_Unknown, + DRM_MODE_CONNECTOR_Unknown, + DRM_MODE_CONNECTOR_DisplayPort, + DRM_MODE_CONNECTOR_eDP, + DRM_MODE_CONNECTOR_Unknown +}; + +bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + struct atom_context *ctx = mode_info->atom_context; + int index = GetIndexIntoMasterTable(DATA, Object_Header); + u16 size, data_offset; + u8 frev, crev; + ATOM_CONNECTOR_OBJECT_TABLE *con_obj; + ATOM_ENCODER_OBJECT_TABLE *enc_obj; + ATOM_OBJECT_TABLE *router_obj; + ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; + ATOM_OBJECT_HEADER *obj_header; + int i, j, k, path_size, device_support; + int connector_type; + u16 conn_id, connector_object_id; + struct amdgpu_i2c_bus_rec ddc_bus; + struct amdgpu_router router; + struct amdgpu_gpio_rec gpio; + struct amdgpu_hpd hpd; + + if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) + return false; + + if (crev < 2) + return false; + + obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); + path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) + (ctx->bios + data_offset + + le16_to_cpu(obj_header->usDisplayPathTableOffset)); + con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) + (ctx->bios + data_offset + + le16_to_cpu(obj_header->usConnectorObjectTableOffset)); + enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) + (ctx->bios + data_offset + + le16_to_cpu(obj_header->usEncoderObjectTableOffset)); + router_obj = (ATOM_OBJECT_TABLE *) + (ctx->bios + data_offset + + le16_to_cpu(obj_header->usRouterObjectTableOffset)); + device_support = le16_to_cpu(obj_header->usDeviceSupport); + + path_size = 0; + for (i = 0; i < path_obj->ucNumOfDispPath; i++) { + uint8_t *addr = (uint8_t *) path_obj->asDispPath; + ATOM_DISPLAY_OBJECT_PATH *path; + addr += path_size; + path = (ATOM_DISPLAY_OBJECT_PATH *) addr; + path_size += le16_to_cpu(path->usSize); + + if (device_support & le16_to_cpu(path->usDeviceTag)) { + uint8_t con_obj_id, con_obj_num, con_obj_type; + + con_obj_id = + (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) + >> OBJECT_ID_SHIFT; + con_obj_num = + (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) + >> ENUM_ID_SHIFT; + con_obj_type = + (le16_to_cpu(path->usConnObjectId) & + OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; + + connector_type = + object_connector_convert[con_obj_id]; + connector_object_id = con_obj_id; + + if (connector_type == DRM_MODE_CONNECTOR_Unknown) + continue; + + router.ddc_valid = false; + router.cd_valid = false; + for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { + uint8_t grph_obj_id, grph_obj_num, grph_obj_type; + + grph_obj_id = + (le16_to_cpu(path->usGraphicObjIds[j]) & + OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; + grph_obj_num = + (le16_to_cpu(path->usGraphicObjIds[j]) & + ENUM_ID_MASK) >> ENUM_ID_SHIFT; + grph_obj_type = + (le16_to_cpu(path->usGraphicObjIds[j]) & + OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; + + if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { + for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { + u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); + if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { + ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) + (ctx->bios + data_offset + + le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); + ATOM_ENCODER_CAP_RECORD *cap_record; + u16 caps = 0; + + while (record->ucRecordSize > 0 && + record->ucRecordType > 0 && + record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { + switch (record->ucRecordType) { + case ATOM_ENCODER_CAP_RECORD_TYPE: + cap_record =(ATOM_ENCODER_CAP_RECORD *) + record; + caps = le16_to_cpu(cap_record->usEncoderCap); + break; + } + record = (ATOM_COMMON_RECORD_HEADER *) + ((char *)record + record->ucRecordSize); + } + amdgpu_display_add_encoder(adev, encoder_obj, + le16_to_cpu(path->usDeviceTag), + caps); + } + } + } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { + for (k = 0; k < router_obj->ucNumberOfObjects; k++) { + u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); + if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { + ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) + (ctx->bios + data_offset + + le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); + ATOM_I2C_RECORD *i2c_record; + ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; + ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; + ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; + ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = + (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) + (ctx->bios + data_offset + + le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); + u8 *num_dst_objs = (u8 *) + ((u8 *)router_src_dst_table + 1 + + (router_src_dst_table->ucNumberOfSrc * 2)); + u16 *dst_objs = (u16 *)(num_dst_objs + 1); + int enum_id; + + router.router_id = router_obj_id; + for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { + if (le16_to_cpu(path->usConnObjectId) == + le16_to_cpu(dst_objs[enum_id])) + break; + } + + while (record->ucRecordSize > 0 && + record->ucRecordType > 0 && + record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { + switch (record->ucRecordType) { + case ATOM_I2C_RECORD_TYPE: + i2c_record = + (ATOM_I2C_RECORD *) + record; + i2c_config = + (ATOM_I2C_ID_CONFIG_ACCESS *) + &i2c_record->sucI2cId; + router.i2c_info = + amdgpu_atombios_lookup_i2c_gpio(adev, + i2c_config-> + ucAccess); + router.i2c_addr = i2c_record->ucI2CAddr >> 1; + break; + case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: + ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) + record; + router.ddc_valid = true; + router.ddc_mux_type = ddc_path->ucMuxType; + router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; + router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; + break; + case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: + cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) + record; + router.cd_valid = true; + router.cd_mux_type = cd_path->ucMuxType; + router.cd_mux_control_pin = cd_path->ucMuxControlPin; + router.cd_mux_state = cd_path->ucMuxState[enum_id]; + break; + } + record = (ATOM_COMMON_RECORD_HEADER *) + ((char *)record + record->ucRecordSize); + } + } + } + } + } + + /* look up gpio for ddc, hpd */ + ddc_bus.valid = false; + hpd.hpd = AMDGPU_HPD_NONE; + if ((le16_to_cpu(path->usDeviceTag) & + (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { + for (j = 0; j < con_obj->ucNumberOfObjects; j++) { + if (le16_to_cpu(path->usConnObjectId) == + le16_to_cpu(con_obj->asObjects[j]. + usObjectID)) { + ATOM_COMMON_RECORD_HEADER + *record = + (ATOM_COMMON_RECORD_HEADER + *) + (ctx->bios + data_offset + + le16_to_cpu(con_obj-> + asObjects[j]. + usRecordOffset)); + ATOM_I2C_RECORD *i2c_record; + ATOM_HPD_INT_RECORD *hpd_record; + ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; + + while (record->ucRecordSize > 0 && + record->ucRecordType > 0 && + record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { + switch (record->ucRecordType) { + case ATOM_I2C_RECORD_TYPE: + i2c_record = + (ATOM_I2C_RECORD *) + record; + i2c_config = + (ATOM_I2C_ID_CONFIG_ACCESS *) + &i2c_record->sucI2cId; + ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev, + i2c_config-> + ucAccess); + break; + case ATOM_HPD_INT_RECORD_TYPE: + hpd_record = + (ATOM_HPD_INT_RECORD *) + record; + gpio = amdgpu_atombios_lookup_gpio(adev, + hpd_record->ucHPDIntGPIOID); + hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio); + hpd.plugged_state = hpd_record->ucPlugged_PinState; + break; + } + record = + (ATOM_COMMON_RECORD_HEADER + *) ((char *)record + + + record-> + ucRecordSize); + } + break; + } + } + } + + /* needed for aux chan transactions */ + ddc_bus.hpd = hpd.hpd; + + conn_id = le16_to_cpu(path->usConnObjectId); + + if (!amdgpu_atombios_apply_quirks + (adev, le16_to_cpu(path->usDeviceTag), &connector_type, + &ddc_bus, &conn_id, &hpd)) + continue; + + amdgpu_display_add_connector(adev, + conn_id, + le16_to_cpu(path->usDeviceTag), + connector_type, &ddc_bus, + connector_object_id, + &hpd, + &router); + + } + } + + amdgpu_link_encoder_connector(adev->ddev); + + return true; +} + +union firmware_info { + ATOM_FIRMWARE_INFO info; + ATOM_FIRMWARE_INFO_V1_2 info_12; + ATOM_FIRMWARE_INFO_V1_3 info_13; + ATOM_FIRMWARE_INFO_V1_4 info_14; + ATOM_FIRMWARE_INFO_V2_1 info_21; + ATOM_FIRMWARE_INFO_V2_2 info_22; +}; + +int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); + uint8_t frev, crev; + uint16_t data_offset; + int ret = -EINVAL; + + if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) { + int i; + struct amdgpu_pll *ppll = &adev->clock.ppll[0]; + struct amdgpu_pll *spll = &adev->clock.spll; + struct amdgpu_pll *mpll = &adev->clock.mpll; + union firmware_info *firmware_info = + (union firmware_info *)(mode_info->atom_context->bios + + data_offset); + /* pixel clocks */ + ppll->reference_freq = + le16_to_cpu(firmware_info->info.usReferenceClock); + ppll->reference_div = 0; + + if (crev < 2) + ppll->pll_out_min = + le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); + else + ppll->pll_out_min = + le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); + ppll->pll_out_max = + le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); + + if (crev >= 4) { + ppll->lcd_pll_out_min = + le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; + if (ppll->lcd_pll_out_min == 0) + ppll->lcd_pll_out_min = ppll->pll_out_min; + ppll->lcd_pll_out_max = + le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; + if (ppll->lcd_pll_out_max == 0) + ppll->lcd_pll_out_max = ppll->pll_out_max; + } else { + ppll->lcd_pll_out_min = ppll->pll_out_min; + ppll->lcd_pll_out_max = ppll->pll_out_max; + } + + if (ppll->pll_out_min == 0) + ppll->pll_out_min = 64800; + + ppll->pll_in_min = + le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); + ppll->pll_in_max = + le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); + + ppll->min_post_div = 2; + ppll->max_post_div = 0x7f; + ppll->min_frac_feedback_div = 0; + ppll->max_frac_feedback_div = 9; + ppll->min_ref_div = 2; + ppll->max_ref_div = 0x3ff; + ppll->min_feedback_div = 4; + ppll->max_feedback_div = 0xfff; + ppll->best_vco = 0; + + for (i = 1; i < AMDGPU_MAX_PPLL; i++) + adev->clock.ppll[i] = *ppll; + + /* system clock */ + spll->reference_freq = + le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); + spll->reference_div = 0; + + spll->pll_out_min = + le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); + spll->pll_out_max = + le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); + + /* ??? */ + if (spll->pll_out_min == 0) + spll->pll_out_min = 64800; + + spll->pll_in_min = + le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); + spll->pll_in_max = + le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); + + spll->min_post_div = 1; + spll->max_post_div = 1; + spll->min_ref_div = 2; + spll->max_ref_div = 0xff; + spll->min_feedback_div = 4; + spll->max_feedback_div = 0xff; + spll->best_vco = 0; + + /* memory clock */ + mpll->reference_freq = + le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); + mpll->reference_div = 0; + + mpll->pll_out_min = + le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); + mpll->pll_out_max = + le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); + + /* ??? */ + if (mpll->pll_out_min == 0) + mpll->pll_out_min = 64800; + + mpll->pll_in_min = + le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); + mpll->pll_in_max = + le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); + + adev->clock.default_sclk = + le32_to_cpu(firmware_info->info.ulDefaultEngineClock); + adev->clock.default_mclk = + le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); + + mpll->min_post_div = 1; + mpll->max_post_div = 1; + mpll->min_ref_div = 2; + mpll->max_ref_div = 0xff; + mpll->min_feedback_div = 4; + mpll->max_feedback_div = 0xff; + mpll->best_vco = 0; + + /* disp clock */ + adev->clock.default_dispclk = + le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); + if (adev->clock.default_dispclk == 0) + adev->clock.default_dispclk = 54000; /* 540 Mhz */ + adev->clock.dp_extclk = + le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); + adev->clock.current_dispclk = adev->clock.default_dispclk; + + adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); + if (adev->clock.max_pixel_clock == 0) + adev->clock.max_pixel_clock = 40000; + + /* not technically a clock, but... */ + adev->mode_info.firmware_flags = + le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); + + ret = 0; + } + + adev->pm.current_sclk = adev->clock.default_sclk; + adev->pm.current_mclk = adev->clock.default_mclk; + + return ret; +} + +union igp_info { + struct _ATOM_INTEGRATED_SYSTEM_INFO info; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9; +}; + +static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev, + struct amdgpu_atom_ss *ss, + int id) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); + u16 data_offset, size; + union igp_info *igp_info; + u8 frev, crev; + u16 percentage = 0, rate = 0; + + /* get any igp specific overrides */ + if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, + &frev, &crev, &data_offset)) { + igp_info = (union igp_info *) + (mode_info->atom_context->bios + data_offset); + switch (crev) { + case 6: + switch (id) { + case ASIC_INTERNAL_SS_ON_TMDS: + percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); + rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); + break; + case ASIC_INTERNAL_SS_ON_HDMI: + percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); + rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); + break; + case ASIC_INTERNAL_SS_ON_LVDS: + percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); + rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); + break; + } + break; + case 7: + switch (id) { + case ASIC_INTERNAL_SS_ON_TMDS: + percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); + rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); + break; + case ASIC_INTERNAL_SS_ON_HDMI: + percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); + rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); + break; + case ASIC_INTERNAL_SS_ON_LVDS: + percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); + rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); + break; + } + break; + case 8: + switch (id) { + case ASIC_INTERNAL_SS_ON_TMDS: + percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); + rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); + break; + case ASIC_INTERNAL_SS_ON_HDMI: + percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); + rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); + break; + case ASIC_INTERNAL_SS_ON_LVDS: + percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); + rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); + break; + } + break; + case 9: + switch (id) { + case ASIC_INTERNAL_SS_ON_TMDS: + percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage); + rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz); + break; + case ASIC_INTERNAL_SS_ON_HDMI: + percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage); + rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz); + break; + case ASIC_INTERNAL_SS_ON_LVDS: + percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage); + rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz); + break; + } + break; + default: + DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); + break; + } + if (percentage) + ss->percentage = percentage; + if (rate) + ss->rate = rate; + } +} + +union asic_ss_info { + struct _ATOM_ASIC_INTERNAL_SS_INFO info; + struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; + struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; +}; + +union asic_ss_assignment { + struct _ATOM_ASIC_SS_ASSIGNMENT v1; + struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; + struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; +}; + +bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, + struct amdgpu_atom_ss *ss, + int id, u32 clock) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); + uint16_t data_offset, size; + union asic_ss_info *ss_info; + union asic_ss_assignment *ss_assign; + uint8_t frev, crev; + int i, num_indices; + + if (id == ASIC_INTERNAL_MEMORY_SS) { + if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) + return false; + } + if (id == ASIC_INTERNAL_ENGINE_SS) { + if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) + return false; + } + + memset(ss, 0, sizeof(struct amdgpu_atom_ss)); + if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, + &frev, &crev, &data_offset)) { + + ss_info = + (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); + + switch (frev) { + case 1: + num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / + sizeof(ATOM_ASIC_SS_ASSIGNMENT); + + ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); + for (i = 0; i < num_indices; i++) { + if ((ss_assign->v1.ucClockIndication == id) && + (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { + ss->percentage = + le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); + ss->type = ss_assign->v1.ucSpreadSpectrumMode; + ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); + ss->percentage_divider = 100; + return true; + } + ss_assign = (union asic_ss_assignment *) + ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); + } + break; + case 2: + num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); + ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); + for (i = 0; i < num_indices; i++) { + if ((ss_assign->v2.ucClockIndication == id) && + (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { + ss->percentage = + le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); + ss->type = ss_assign->v2.ucSpreadSpectrumMode; + ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); + ss->percentage_divider = 100; + if ((crev == 2) && + ((id == ASIC_INTERNAL_ENGINE_SS) || + (id == ASIC_INTERNAL_MEMORY_SS))) + ss->rate /= 100; + return true; + } + ss_assign = (union asic_ss_assignment *) + ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); + } + break; + case 3: + num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); + ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); + for (i = 0; i < num_indices; i++) { + if ((ss_assign->v3.ucClockIndication == id) && + (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { + ss->percentage = + le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); + ss->type = ss_assign->v3.ucSpreadSpectrumMode; + ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); + if (ss_assign->v3.ucSpreadSpectrumMode & + SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) + ss->percentage_divider = 1000; + else + ss->percentage_divider = 100; + if ((id == ASIC_INTERNAL_ENGINE_SS) || + (id == ASIC_INTERNAL_MEMORY_SS)) + ss->rate /= 100; + if (adev->flags & AMDGPU_IS_APU) + amdgpu_atombios_get_igp_ss_overrides(adev, ss, id); + return true; + } + ss_assign = (union asic_ss_assignment *) + ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); + } + break; + default: + DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); + break; + } + + } + return false; +} + +union get_clock_dividers { + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; + struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; + struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; + struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; +}; + +int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, + u8 clock_type, + u32 clock, + bool strobe_mode, + struct atom_clock_dividers *dividers) +{ + union get_clock_dividers args; + int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); + u8 frev, crev; + + memset(&args, 0, sizeof(args)); + memset(dividers, 0, sizeof(struct atom_clock_dividers)); + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) + return -EINVAL; + + switch (crev) { + case 4: + /* fusion */ + args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + + dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; + dividers->real_clock = le32_to_cpu(args.v4.ulClock); + break; + case 6: + /* CI */ + /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ + args.v6_in.ulClock.ulComputeClockFlag = clock_type; + args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + + dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); + dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); + dividers->ref_div = args.v6_out.ucPllRefDiv; + dividers->post_div = args.v6_out.ucPllPostDiv; + dividers->flags = args.v6_out.ucPllCntlFlag; + dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); + dividers->post_divider = args.v6_out.ulClock.ucPostDiv; + break; + default: + return -EINVAL; + } + return 0; +} + +int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, + u32 clock, + bool strobe_mode, + struct atom_mpll_param *mpll_param) +{ + COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; + int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); + u8 frev, crev; + + memset(&args, 0, sizeof(args)); + memset(mpll_param, 0, sizeof(struct atom_mpll_param)); + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) + return -EINVAL; + + switch (frev) { + case 2: + switch (crev) { + case 1: + /* SI */ + args.ulClock = cpu_to_le32(clock); /* 10 khz */ + args.ucInputFlag = 0; + if (strobe_mode) + args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + + mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); + mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); + mpll_param->post_div = args.ucPostDiv; + mpll_param->dll_speed = args.ucDllSpeed; + mpll_param->bwcntl = args.ucBWCntl; + mpll_param->vco_mode = + (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); + mpll_param->yclk_sel = + (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; + mpll_param->qdr = + (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; + mpll_param->half_rate = + (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return 0; +} + +uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev) +{ + GET_ENGINE_CLOCK_PS_ALLOCATION args; + int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + return le32_to_cpu(args.ulReturnEngineClock); +} + +uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev) +{ + GET_MEMORY_CLOCK_PS_ALLOCATION args; + int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + return le32_to_cpu(args.ulReturnMemoryClock); +} + +void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev, + uint32_t eng_clock) +{ + SET_ENGINE_CLOCK_PS_ALLOCATION args; + int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); + + args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev, + uint32_t mem_clock) +{ + SET_MEMORY_CLOCK_PS_ALLOCATION args; + int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); + + if (adev->flags & AMDGPU_IS_APU) + return; + + args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, + u32 eng_clock, u32 mem_clock) +{ + SET_ENGINE_CLOCK_PS_ALLOCATION args; + int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); + u32 tmp; + + memset(&args, 0, sizeof(args)); + + tmp = eng_clock & SET_CLOCK_FREQ_MASK; + tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); + + args.ulTargetEngineClock = cpu_to_le32(tmp); + if (mem_clock) + args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +union set_voltage { + struct _SET_VOLTAGE_PS_ALLOCATION alloc; + struct _SET_VOLTAGE_PARAMETERS v1; + struct _SET_VOLTAGE_PARAMETERS_V2 v2; + struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; +}; + +void amdgpu_atombios_set_voltage(struct amdgpu_device *adev, + u16 voltage_level, + u8 voltage_type) +{ + union set_voltage args; + int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); + u8 frev, crev, volt_index = voltage_level; + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) + return; + + /* 0xff01 is a flag rather then an actual voltage */ + if (voltage_level == 0xff01) + return; + + switch (crev) { + case 1: + args.v1.ucVoltageType = voltage_type; + args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; + args.v1.ucVoltageIndex = volt_index; + break; + case 2: + args.v2.ucVoltageType = voltage_type; + args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; + args.v2.usVoltageLevel = cpu_to_le16(voltage_level); + break; + case 3: + args.v3.ucVoltageType = voltage_type; + args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; + args.v3.usVoltageLevel = cpu_to_le16(voltage_level); + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + return; + } + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev, + u16 *leakage_id) +{ + union set_voltage args; + int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); + u8 frev, crev; + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) + return -EINVAL; + + switch (crev) { + case 3: + case 4: + args.v3.ucVoltageType = 0; + args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; + args.v3.usVoltageLevel = 0; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + + *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + return -EINVAL; + } + + return 0; +} + +int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev, + u16 *vddc, u16 *vddci, + u16 virtual_voltage_id, + u16 vbios_voltage_id) +{ + int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); + u8 frev, crev; + u16 data_offset, size; + int i, j; + ATOM_ASIC_PROFILING_INFO_V2_1 *profile; + u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; + + *vddc = 0; + *vddci = 0; + + if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, + &frev, &crev, &data_offset)) + return -EINVAL; + + profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) + (adev->mode_info.atom_context->bios + data_offset); + + switch (frev) { + case 1: + return -EINVAL; + case 2: + switch (crev) { + case 1: + if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) + return -EINVAL; + leakage_bin = (u16 *) + (adev->mode_info.atom_context->bios + data_offset + + le16_to_cpu(profile->usLeakageBinArrayOffset)); + vddc_id_buf = (u16 *) + (adev->mode_info.atom_context->bios + data_offset + + le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); + vddc_buf = (u16 *) + (adev->mode_info.atom_context->bios + data_offset + + le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); + vddci_id_buf = (u16 *) + (adev->mode_info.atom_context->bios + data_offset + + le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); + vddci_buf = (u16 *) + (adev->mode_info.atom_context->bios + data_offset + + le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); + + if (profile->ucElbVDDC_Num > 0) { + for (i = 0; i < profile->ucElbVDDC_Num; i++) { + if (vddc_id_buf[i] == virtual_voltage_id) { + for (j = 0; j < profile->ucLeakageBinNum; j++) { + if (vbios_voltage_id <= leakage_bin[j]) { + *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; + break; + } + } + break; + } + } + } + if (profile->ucElbVDDCI_Num > 0) { + for (i = 0; i < profile->ucElbVDDCI_Num; i++) { + if (vddci_id_buf[i] == virtual_voltage_id) { + for (j = 0; j < profile->ucLeakageBinNum; j++) { + if (vbios_voltage_id <= leakage_bin[j]) { + *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; + break; + } + } + break; + } + } + } + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + return -EINVAL; + } + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + return -EINVAL; + } + + return 0; +} + +union get_voltage_info { + struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; + struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; +}; + +int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev, + u16 virtual_voltage_id, + u16 *voltage) +{ + int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); + u32 entry_id; + u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; + union get_voltage_info args; + + for (entry_id = 0; entry_id < count; entry_id++) { + if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == + virtual_voltage_id) + break; + } + + if (entry_id >= count) + return -EINVAL; + + args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; + args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; + args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); + args.in.ulSCLKFreq = + cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + + *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); + + return 0; +} + +union voltage_object_info { + struct _ATOM_VOLTAGE_OBJECT_INFO v1; + struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; + struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; +}; + +union voltage_object { + struct _ATOM_VOLTAGE_OBJECT v1; + struct _ATOM_VOLTAGE_OBJECT_V2 v2; + union _ATOM_VOLTAGE_OBJECT_V3 v3; +}; + + +static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, + u8 voltage_type, u8 voltage_mode) +{ + u32 size = le16_to_cpu(v3->sHeader.usStructureSize); + u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); + u8 *start = (u8*)v3; + + while (offset < size) { + ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); + if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && + (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) + return vo; + offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); + } + return NULL; +} + +bool +amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, + u8 voltage_type, u8 voltage_mode) +{ + int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); + u8 frev, crev; + u16 data_offset, size; + union voltage_object_info *voltage_info; + + if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, + &frev, &crev, &data_offset)) { + voltage_info = (union voltage_object_info *) + (adev->mode_info.atom_context->bios + data_offset); + + switch (frev) { + case 3: + switch (crev) { + case 1: + if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, + voltage_type, voltage_mode)) + return true; + break; + default: + DRM_ERROR("unknown voltage object table\n"); + return false; + } + break; + default: + DRM_ERROR("unknown voltage object table\n"); + return false; + } + + } + return false; +} + +int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, + u8 voltage_type, u8 voltage_mode, + struct atom_voltage_table *voltage_table) +{ + int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); + u8 frev, crev; + u16 data_offset, size; + int i; + union voltage_object_info *voltage_info; + union voltage_object *voltage_object = NULL; + + if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, + &frev, &crev, &data_offset)) { + voltage_info = (union voltage_object_info *) + (adev->mode_info.atom_context->bios + data_offset); + + switch (frev) { + case 3: + switch (crev) { + case 1: + voltage_object = (union voltage_object *) + amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, + voltage_type, voltage_mode); + if (voltage_object) { + ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = + &voltage_object->v3.asGpioVoltageObj; + VOLTAGE_LUT_ENTRY_V2 *lut; + if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) + return -EINVAL; + lut = &gpio->asVolGpioLut[0]; + for (i = 0; i < gpio->ucGpioEntryNum; i++) { + voltage_table->entries[i].value = + le16_to_cpu(lut->usVoltageValue); + voltage_table->entries[i].smio_low = + le32_to_cpu(lut->ulVoltageId); + lut = (VOLTAGE_LUT_ENTRY_V2 *) + ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); + } + voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); + voltage_table->count = gpio->ucGpioEntryNum; + voltage_table->phase_delay = gpio->ucPhaseDelay; + return 0; + } + break; + default: + DRM_ERROR("unknown voltage object table\n"); + return -EINVAL; + } + break; + default: + DRM_ERROR("unknown voltage object table\n"); + return -EINVAL; + } + } + return -EINVAL; +} + +union vram_info { + struct _ATOM_VRAM_INFO_V3 v1_3; + struct _ATOM_VRAM_INFO_V4 v1_4; + struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; +}; + +#define MEM_ID_MASK 0xff000000 +#define MEM_ID_SHIFT 24 +#define CLOCK_RANGE_MASK 0x00ffffff +#define CLOCK_RANGE_SHIFT 0 +#define LOW_NIBBLE_MASK 0xf +#define DATA_EQU_PREV 0 +#define DATA_FROM_TABLE 4 + +int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, + u8 module_index, + struct atom_mc_reg_table *reg_table) +{ + int index = GetIndexIntoMasterTable(DATA, VRAM_Info); + u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; + u32 i = 0, j; + u16 data_offset, size; + union vram_info *vram_info; + + memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); + + if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, + &frev, &crev, &data_offset)) { + vram_info = (union vram_info *) + (adev->mode_info.atom_context->bios + data_offset); + switch (frev) { + case 1: + DRM_ERROR("old table version %d, %d\n", frev, crev); + return -EINVAL; + case 2: + switch (crev) { + case 1: + if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { + ATOM_INIT_REG_BLOCK *reg_block = + (ATOM_INIT_REG_BLOCK *) + ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); + ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = + (ATOM_MEMORY_SETTING_DATA_BLOCK *) + ((u8 *)reg_block + (2 * sizeof(u16)) + + le16_to_cpu(reg_block->usRegIndexTblSize)); + ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; + num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / + sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; + if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; + while (i < num_entries) { + if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) + break; + reg_table->mc_reg_address[i].s1 = + (u16)(le16_to_cpu(format->usRegIndex)); + reg_table->mc_reg_address[i].pre_reg_data = + (u8)(format->ucPreRegDataLength); + i++; + format = (ATOM_INIT_REG_INDEX_FORMAT *) + ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); + } + reg_table->last = i; + while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && + (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { + t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) + >> MEM_ID_SHIFT); + if (module_index == t_mem_id) { + reg_table->mc_reg_table_entry[num_ranges].mclk_max = + (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) + >> CLOCK_RANGE_SHIFT); + for (i = 0, j = 1; i < reg_table->last; i++) { + if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { + reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = + (u32)le32_to_cpu(*((u32 *)reg_data + j)); + j++; + } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { + reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = + reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; + } + } + num_ranges++; + } + reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) + ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); + } + if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) + return -EINVAL; + reg_table->num_entries = num_ranges; + } else + return -EINVAL; + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + return -EINVAL; + } + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + return -EINVAL; + } + return 0; + } + return -EINVAL; +} + +void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock) +{ + uint32_t bios_6_scratch; + + bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); + + if (lock) { + bios_6_scratch |= ATOM_S6_CRITICAL_STATE; + bios_6_scratch &= ~ATOM_S6_ACC_MODE; + } else { + bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; + bios_6_scratch |= ATOM_S6_ACC_MODE; + } + + WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); +} + +void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev) +{ + uint32_t bios_2_scratch, bios_6_scratch; + + bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); + bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); + + /* let the bios control the backlight */ + bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; + + /* tell the bios not to handle mode switching */ + bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; + + /* clear the vbios dpms state */ + bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; + + WREG32(mmBIOS_SCRATCH_2, bios_2_scratch); + WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); +} + +void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) + adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i); +} + +void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) + WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]); +} + +/* Atom needs data in little endian format + * so swap as appropriate when copying data to + * or from atom. Note that atom operates on + * dw units. + */ +void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) +{ +#ifdef __BIG_ENDIAN + u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ + u32 *dst32, *src32; + int i; + + memcpy(src_tmp, src, num_bytes); + src32 = (u32 *)src_tmp; + dst32 = (u32 *)dst_tmp; + if (to_le) { + for (i = 0; i < ((num_bytes + 3) / 4); i++) + dst32[i] = cpu_to_le32(src32[i]); + memcpy(dst, dst_tmp, num_bytes); + } else { + u8 dws = num_bytes & ~3; + for (i = 0; i < ((num_bytes + 3) / 4); i++) + dst32[i] = le32_to_cpu(src32[i]); + memcpy(dst, dst_tmp, dws); + if (num_bytes % 4) { + for (i = 0; i < (num_bytes % 4); i++) + dst[dws+i] = dst_tmp[dws+i]; + } + } +#else + memcpy(dst, src, num_bytes); +#endif +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h new file mode 100644 index 000000000000..0ebb959ea435 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h @@ -0,0 +1,206 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_ATOMBIOS_H__ +#define __AMDGPU_ATOMBIOS_H__ + +struct atom_clock_dividers { + u32 post_div; + union { + struct { +#ifdef __BIG_ENDIAN + u32 reserved : 6; + u32 whole_fb_div : 12; + u32 frac_fb_div : 14; +#else + u32 frac_fb_div : 14; + u32 whole_fb_div : 12; + u32 reserved : 6; +#endif + }; + u32 fb_div; + }; + u32 ref_div; + bool enable_post_div; + bool enable_dithen; + u32 vco_mode; + u32 real_clock; + /* added for CI */ + u32 post_divider; + u32 flags; +}; + +struct atom_mpll_param { + union { + struct { +#ifdef __BIG_ENDIAN + u32 reserved : 8; + u32 clkfrac : 12; + u32 clkf : 12; +#else + u32 clkf : 12; + u32 clkfrac : 12; + u32 reserved : 8; +#endif + }; + u32 fb_div; + }; + u32 post_div; + u32 bwcntl; + u32 dll_speed; + u32 vco_mode; + u32 yclk_sel; + u32 qdr; + u32 half_rate; +}; + +#define MEM_TYPE_GDDR5 0x50 +#define MEM_TYPE_GDDR4 0x40 +#define MEM_TYPE_GDDR3 0x30 +#define MEM_TYPE_DDR2 0x20 +#define MEM_TYPE_GDDR1 0x10 +#define MEM_TYPE_DDR3 0xb0 +#define MEM_TYPE_MASK 0xf0 + +struct atom_memory_info { + u8 mem_vendor; + u8 mem_type; +}; + +#define MAX_AC_TIMING_ENTRIES 16 + +struct atom_memory_clock_range_table +{ + u8 num_entries; + u8 rsv[3]; + u32 mclk[MAX_AC_TIMING_ENTRIES]; +}; + +#define VBIOS_MC_REGISTER_ARRAY_SIZE 32 +#define VBIOS_MAX_AC_TIMING_ENTRIES 20 + +struct atom_mc_reg_entry { + u32 mclk_max; + u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; +}; + +struct atom_mc_register_address { + u16 s1; + u8 pre_reg_data; +}; + +struct atom_mc_reg_table { + u8 last; + u8 num_entries; + struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; + struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; +}; + +#define MAX_VOLTAGE_ENTRIES 32 + +struct atom_voltage_table_entry +{ + u16 value; + u32 smio_low; +}; + +struct atom_voltage_table +{ + u32 count; + u32 mask_low; + u32 phase_delay; + struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; +}; + +struct amdgpu_gpio_rec +amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev, + u8 id); + +struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev, + uint8_t id); +void amdgpu_atombios_i2c_init(struct amdgpu_device *adev); + +bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev); + +int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev); + +bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, + struct amdgpu_atom_ss *ss, + int id, u32 clock); + +int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, + u8 clock_type, + u32 clock, + bool strobe_mode, + struct atom_clock_dividers *dividers); + +int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, + u32 clock, + bool strobe_mode, + struct atom_mpll_param *mpll_param); + +uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev); +uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev); +void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev, + uint32_t eng_clock); +void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev, + uint32_t mem_clock); +void amdgpu_atombios_set_voltage(struct amdgpu_device *adev, + u16 voltage_level, + u8 voltage_type); + +void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, + u32 eng_clock, u32 mem_clock); + +int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev, + u16 *leakage_id); + +int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev, + u16 *vddc, u16 *vddci, + u16 virtual_voltage_id, + u16 vbios_voltage_id); + +int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev, + u16 virtual_voltage_id, + u16 *voltage); + +bool +amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, + u8 voltage_type, u8 voltage_mode); + +int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, + u8 voltage_type, u8 voltage_mode, + struct atom_voltage_table *voltage_table); + +int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, + u8 module_index, + struct atom_mc_reg_table *reg_table); + +void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock); +void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev); +void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev); +void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev); + +void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c new file mode 100644 index 000000000000..3f7aaa45bf8e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c @@ -0,0 +1,572 @@ +/* + * Copyright (c) 2010 Red Hat Inc. + * Author : Dave Airlie + * + * Licensed under GPLv2 + * + * ATPX support for both Intel/ATI + */ +#include +#include +#include +#include + +#include "amdgpu_acpi.h" + +struct amdgpu_atpx_functions { + bool px_params; + bool power_cntl; + bool disp_mux_cntl; + bool i2c_mux_cntl; + bool switch_start; + bool switch_end; + bool disp_connectors_mapping; + bool disp_detetion_ports; +}; + +struct amdgpu_atpx { + acpi_handle handle; + struct amdgpu_atpx_functions functions; +}; + +static struct amdgpu_atpx_priv { + bool atpx_detected; + /* handle for device - and atpx */ + acpi_handle dhandle; + acpi_handle other_handle; + struct amdgpu_atpx atpx; +} amdgpu_atpx_priv; + +struct atpx_verify_interface { + u16 size; /* structure size in bytes (includes size field) */ + u16 version; /* version */ + u32 function_bits; /* supported functions bit vector */ +} __packed; + +struct atpx_px_params { + u16 size; /* structure size in bytes (includes size field) */ + u32 valid_flags; /* which flags are valid */ + u32 flags; /* flags */ +} __packed; + +struct atpx_power_control { + u16 size; + u8 dgpu_state; +} __packed; + +struct atpx_mux { + u16 size; + u16 mux; +} __packed; + +bool amdgpu_has_atpx(void) { + return amdgpu_atpx_priv.atpx_detected; +} + +/** + * amdgpu_atpx_call - call an ATPX method + * + * @handle: acpi handle + * @function: the ATPX function to execute + * @params: ATPX function params + * + * Executes the requested ATPX function (all asics). + * Returns a pointer to the acpi output buffer. + */ +static union acpi_object *amdgpu_atpx_call(acpi_handle handle, int function, + struct acpi_buffer *params) +{ + acpi_status status; + union acpi_object atpx_arg_elements[2]; + struct acpi_object_list atpx_arg; + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + + atpx_arg.count = 2; + atpx_arg.pointer = &atpx_arg_elements[0]; + + atpx_arg_elements[0].type = ACPI_TYPE_INTEGER; + atpx_arg_elements[0].integer.value = function; + + if (params) { + atpx_arg_elements[1].type = ACPI_TYPE_BUFFER; + atpx_arg_elements[1].buffer.length = params->length; + atpx_arg_elements[1].buffer.pointer = params->pointer; + } else { + /* We need a second fake parameter */ + atpx_arg_elements[1].type = ACPI_TYPE_INTEGER; + atpx_arg_elements[1].integer.value = 0; + } + + status = acpi_evaluate_object(handle, NULL, &atpx_arg, &buffer); + + /* Fail only if calling the method fails and ATPX is supported */ + if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { + printk("failed to evaluate ATPX got %s\n", + acpi_format_exception(status)); + kfree(buffer.pointer); + return NULL; + } + + return buffer.pointer; +} + +/** + * amdgpu_atpx_parse_functions - parse supported functions + * + * @f: supported functions struct + * @mask: supported functions mask from ATPX + * + * Use the supported functions mask from ATPX function + * ATPX_FUNCTION_VERIFY_INTERFACE to determine what functions + * are supported (all asics). + */ +static void amdgpu_atpx_parse_functions(struct amdgpu_atpx_functions *f, u32 mask) +{ + f->px_params = mask & ATPX_GET_PX_PARAMETERS_SUPPORTED; + f->power_cntl = mask & ATPX_POWER_CONTROL_SUPPORTED; + f->disp_mux_cntl = mask & ATPX_DISPLAY_MUX_CONTROL_SUPPORTED; + f->i2c_mux_cntl = mask & ATPX_I2C_MUX_CONTROL_SUPPORTED; + f->switch_start = mask & ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED; + f->switch_end = mask & ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED; + f->disp_connectors_mapping = mask & ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED; + f->disp_detetion_ports = mask & ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED; +} + +/** + * amdgpu_atpx_validate_functions - validate ATPX functions + * + * @atpx: amdgpu atpx struct + * + * Validate that required functions are enabled (all asics). + * returns 0 on success, error on failure. + */ +static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx) +{ + /* make sure required functions are enabled */ + /* dGPU power control is required */ + atpx->functions.power_cntl = true; + + if (atpx->functions.px_params) { + union acpi_object *info; + struct atpx_px_params output; + size_t size; + u32 valid_bits; + + info = amdgpu_atpx_call(atpx->handle, ATPX_FUNCTION_GET_PX_PARAMETERS, NULL); + if (!info) + return -EIO; + + memset(&output, 0, sizeof(output)); + + size = *(u16 *) info->buffer.pointer; + if (size < 10) { + printk("ATPX buffer is too small: %zu\n", size); + kfree(info); + return -EINVAL; + } + size = min(sizeof(output), size); + + memcpy(&output, info->buffer.pointer, size); + + valid_bits = output.flags & output.valid_flags; + /* if separate mux flag is set, mux controls are required */ + if (valid_bits & ATPX_SEPARATE_MUX_FOR_I2C) { + atpx->functions.i2c_mux_cntl = true; + atpx->functions.disp_mux_cntl = true; + } + /* if any outputs are muxed, mux controls are required */ + if (valid_bits & (ATPX_CRT1_RGB_SIGNAL_MUXED | + ATPX_TV_SIGNAL_MUXED | + ATPX_DFP_SIGNAL_MUXED)) + atpx->functions.disp_mux_cntl = true; + + kfree(info); + } + return 0; +} + +/** + * amdgpu_atpx_verify_interface - verify ATPX + * + * @atpx: amdgpu atpx struct + * + * Execute the ATPX_FUNCTION_VERIFY_INTERFACE ATPX function + * to initialize ATPX and determine what features are supported + * (all asics). + * returns 0 on success, error on failure. + */ +static int amdgpu_atpx_verify_interface(struct amdgpu_atpx *atpx) +{ + union acpi_object *info; + struct atpx_verify_interface output; + size_t size; + int err = 0; + + info = amdgpu_atpx_call(atpx->handle, ATPX_FUNCTION_VERIFY_INTERFACE, NULL); + if (!info) + return -EIO; + + memset(&output, 0, sizeof(output)); + + size = *(u16 *) info->buffer.pointer; + if (size < 8) { + printk("ATPX buffer is too small: %zu\n", size); + err = -EINVAL; + goto out; + } + size = min(sizeof(output), size); + + memcpy(&output, info->buffer.pointer, size); + + /* TODO: check version? */ + printk("ATPX version %u, functions 0x%08x\n", + output.version, output.function_bits); + + amdgpu_atpx_parse_functions(&atpx->functions, output.function_bits); + +out: + kfree(info); + return err; +} + +/** + * amdgpu_atpx_set_discrete_state - power up/down discrete GPU + * + * @atpx: atpx info struct + * @state: discrete GPU state (0 = power down, 1 = power up) + * + * Execute the ATPX_FUNCTION_POWER_CONTROL ATPX function to + * power down/up the discrete GPU (all asics). + * Returns 0 on success, error on failure. + */ +static int amdgpu_atpx_set_discrete_state(struct amdgpu_atpx *atpx, u8 state) +{ + struct acpi_buffer params; + union acpi_object *info; + struct atpx_power_control input; + + if (atpx->functions.power_cntl) { + input.size = 3; + input.dgpu_state = state; + params.length = input.size; + params.pointer = &input; + info = amdgpu_atpx_call(atpx->handle, + ATPX_FUNCTION_POWER_CONTROL, + ¶ms); + if (!info) + return -EIO; + kfree(info); + } + return 0; +} + +/** + * amdgpu_atpx_switch_disp_mux - switch display mux + * + * @atpx: atpx info struct + * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU) + * + * Execute the ATPX_FUNCTION_DISPLAY_MUX_CONTROL ATPX function to + * switch the display mux between the discrete GPU and integrated GPU + * (all asics). + * Returns 0 on success, error on failure. + */ +static int amdgpu_atpx_switch_disp_mux(struct amdgpu_atpx *atpx, u16 mux_id) +{ + struct acpi_buffer params; + union acpi_object *info; + struct atpx_mux input; + + if (atpx->functions.disp_mux_cntl) { + input.size = 4; + input.mux = mux_id; + params.length = input.size; + params.pointer = &input; + info = amdgpu_atpx_call(atpx->handle, + ATPX_FUNCTION_DISPLAY_MUX_CONTROL, + ¶ms); + if (!info) + return -EIO; + kfree(info); + } + return 0; +} + +/** + * amdgpu_atpx_switch_i2c_mux - switch i2c/hpd mux + * + * @atpx: atpx info struct + * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU) + * + * Execute the ATPX_FUNCTION_I2C_MUX_CONTROL ATPX function to + * switch the i2c/hpd mux between the discrete GPU and integrated GPU + * (all asics). + * Returns 0 on success, error on failure. + */ +static int amdgpu_atpx_switch_i2c_mux(struct amdgpu_atpx *atpx, u16 mux_id) +{ + struct acpi_buffer params; + union acpi_object *info; + struct atpx_mux input; + + if (atpx->functions.i2c_mux_cntl) { + input.size = 4; + input.mux = mux_id; + params.length = input.size; + params.pointer = &input; + info = amdgpu_atpx_call(atpx->handle, + ATPX_FUNCTION_I2C_MUX_CONTROL, + ¶ms); + if (!info) + return -EIO; + kfree(info); + } + return 0; +} + +/** + * amdgpu_atpx_switch_start - notify the sbios of a GPU switch + * + * @atpx: atpx info struct + * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU) + * + * Execute the ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION ATPX + * function to notify the sbios that a switch between the discrete GPU and + * integrated GPU has begun (all asics). + * Returns 0 on success, error on failure. + */ +static int amdgpu_atpx_switch_start(struct amdgpu_atpx *atpx, u16 mux_id) +{ + struct acpi_buffer params; + union acpi_object *info; + struct atpx_mux input; + + if (atpx->functions.switch_start) { + input.size = 4; + input.mux = mux_id; + params.length = input.size; + params.pointer = &input; + info = amdgpu_atpx_call(atpx->handle, + ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION, + ¶ms); + if (!info) + return -EIO; + kfree(info); + } + return 0; +} + +/** + * amdgpu_atpx_switch_end - notify the sbios of a GPU switch + * + * @atpx: atpx info struct + * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU) + * + * Execute the ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION ATPX + * function to notify the sbios that a switch between the discrete GPU and + * integrated GPU has ended (all asics). + * Returns 0 on success, error on failure. + */ +static int amdgpu_atpx_switch_end(struct amdgpu_atpx *atpx, u16 mux_id) +{ + struct acpi_buffer params; + union acpi_object *info; + struct atpx_mux input; + + if (atpx->functions.switch_end) { + input.size = 4; + input.mux = mux_id; + params.length = input.size; + params.pointer = &input; + info = amdgpu_atpx_call(atpx->handle, + ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION, + ¶ms); + if (!info) + return -EIO; + kfree(info); + } + return 0; +} + +/** + * amdgpu_atpx_switchto - switch to the requested GPU + * + * @id: GPU to switch to + * + * Execute the necessary ATPX functions to switch between the discrete GPU and + * integrated GPU (all asics). + * Returns 0 on success, error on failure. + */ +static int amdgpu_atpx_switchto(enum vga_switcheroo_client_id id) +{ + u16 gpu_id; + + if (id == VGA_SWITCHEROO_IGD) + gpu_id = ATPX_INTEGRATED_GPU; + else + gpu_id = ATPX_DISCRETE_GPU; + + amdgpu_atpx_switch_start(&amdgpu_atpx_priv.atpx, gpu_id); + amdgpu_atpx_switch_disp_mux(&amdgpu_atpx_priv.atpx, gpu_id); + amdgpu_atpx_switch_i2c_mux(&amdgpu_atpx_priv.atpx, gpu_id); + amdgpu_atpx_switch_end(&amdgpu_atpx_priv.atpx, gpu_id); + + return 0; +} + +/** + * amdgpu_atpx_power_state - power down/up the requested GPU + * + * @id: GPU to power down/up + * @state: requested power state (0 = off, 1 = on) + * + * Execute the necessary ATPX function to power down/up the discrete GPU + * (all asics). + * Returns 0 on success, error on failure. + */ +static int amdgpu_atpx_power_state(enum vga_switcheroo_client_id id, + enum vga_switcheroo_state state) +{ + /* on w500 ACPI can't change intel gpu state */ + if (id == VGA_SWITCHEROO_IGD) + return 0; + + amdgpu_atpx_set_discrete_state(&amdgpu_atpx_priv.atpx, state); + return 0; +} + +/** + * amdgpu_atpx_pci_probe_handle - look up the ATPX handle + * + * @pdev: pci device + * + * Look up the ATPX handles (all asics). + * Returns true if the handles are found, false if not. + */ +static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev) +{ + acpi_handle dhandle, atpx_handle; + acpi_status status; + + dhandle = ACPI_HANDLE(&pdev->dev); + if (!dhandle) + return false; + + status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); + if (ACPI_FAILURE(status)) { + amdgpu_atpx_priv.other_handle = dhandle; + return false; + } + amdgpu_atpx_priv.dhandle = dhandle; + amdgpu_atpx_priv.atpx.handle = atpx_handle; + return true; +} + +/** + * amdgpu_atpx_init - verify the ATPX interface + * + * Verify the ATPX interface (all asics). + * Returns 0 on success, error on failure. + */ +static int amdgpu_atpx_init(void) +{ + int r; + + /* set up the ATPX handle */ + r = amdgpu_atpx_verify_interface(&amdgpu_atpx_priv.atpx); + if (r) + return r; + + /* validate the atpx setup */ + r = amdgpu_atpx_validate(&amdgpu_atpx_priv.atpx); + if (r) + return r; + + return 0; +} + +/** + * amdgpu_atpx_get_client_id - get the client id + * + * @pdev: pci device + * + * look up whether we are the integrated or discrete GPU (all asics). + * Returns the client id. + */ +static int amdgpu_atpx_get_client_id(struct pci_dev *pdev) +{ + if (amdgpu_atpx_priv.dhandle == ACPI_HANDLE(&pdev->dev)) + return VGA_SWITCHEROO_IGD; + else + return VGA_SWITCHEROO_DIS; +} + +static struct vga_switcheroo_handler amdgpu_atpx_handler = { + .switchto = amdgpu_atpx_switchto, + .power_state = amdgpu_atpx_power_state, + .init = amdgpu_atpx_init, + .get_client_id = amdgpu_atpx_get_client_id, +}; + +/** + * amdgpu_atpx_detect - detect whether we have PX + * + * Check if we have a PX system (all asics). + * Returns true if we have a PX system, false if not. + */ +static bool amdgpu_atpx_detect(void) +{ + char acpi_method_name[255] = { 0 }; + struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name}; + struct pci_dev *pdev = NULL; + bool has_atpx = false; + int vga_count = 0; + + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { + vga_count++; + + has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true); + } + + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { + vga_count++; + + has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true); + } + + if (has_atpx && vga_count == 2) { + acpi_get_name(amdgpu_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer); + printk(KERN_INFO "VGA switcheroo: detected switching method %s handle\n", + acpi_method_name); + amdgpu_atpx_priv.atpx_detected = true; + return true; + } + return false; +} + +/** + * amdgpu_register_atpx_handler - register with vga_switcheroo + * + * Register the PX callbacks with vga_switcheroo (all asics). + */ +void amdgpu_register_atpx_handler(void) +{ + bool r; + + /* detect if we have any ATPX + 2 VGA in the system */ + r = amdgpu_atpx_detect(); + if (!r) + return; + + vga_switcheroo_register_handler(&amdgpu_atpx_handler); +} + +/** + * amdgpu_unregister_atpx_handler - unregister with vga_switcheroo + * + * Unregister the PX callbacks with vga_switcheroo (all asics). + */ +void amdgpu_unregister_atpx_handler(void) +{ + vga_switcheroo_unregister_handler(); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c new file mode 100644 index 000000000000..2742b9a35cbc --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c @@ -0,0 +1,221 @@ +/* + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Jerome Glisse + */ +#include +#include +#include "amdgpu.h" + +#define AMDGPU_BENCHMARK_ITERATIONS 1024 +#define AMDGPU_BENCHMARK_COMMON_MODES_N 17 + +static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, + uint64_t saddr, uint64_t daddr, int n) +{ + unsigned long start_jiffies; + unsigned long end_jiffies; + struct amdgpu_fence *fence = NULL; + int i, r; + + start_jiffies = jiffies; + for (i = 0; i < n; i++) { + struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; + r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence); + if (r) + goto exit_do_move; + r = amdgpu_fence_wait(fence, false); + if (r) + goto exit_do_move; + amdgpu_fence_unref(&fence); + } + end_jiffies = jiffies; + r = jiffies_to_msecs(end_jiffies - start_jiffies); + +exit_do_move: + if (fence) + amdgpu_fence_unref(&fence); + return r; +} + + +static void amdgpu_benchmark_log_results(int n, unsigned size, + unsigned int time, + unsigned sdomain, unsigned ddomain, + char *kind) +{ + unsigned int throughput = (n * (size >> 10)) / time; + DRM_INFO("amdgpu: %s %u bo moves of %u kB from" + " %d to %d in %u ms, throughput: %u Mb/s or %u MB/s\n", + kind, n, size >> 10, sdomain, ddomain, time, + throughput * 8, throughput); +} + +static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size, + unsigned sdomain, unsigned ddomain) +{ + struct amdgpu_bo *dobj = NULL; + struct amdgpu_bo *sobj = NULL; + uint64_t saddr, daddr; + int r, n; + int time; + + n = AMDGPU_BENCHMARK_ITERATIONS; + r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, sdomain, 0, NULL, &sobj); + if (r) { + goto out_cleanup; + } + r = amdgpu_bo_reserve(sobj, false); + if (unlikely(r != 0)) + goto out_cleanup; + r = amdgpu_bo_pin(sobj, sdomain, &saddr); + amdgpu_bo_unreserve(sobj); + if (r) { + goto out_cleanup; + } + r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, ddomain, 0, NULL, &dobj); + if (r) { + goto out_cleanup; + } + r = amdgpu_bo_reserve(dobj, false); + if (unlikely(r != 0)) + goto out_cleanup; + r = amdgpu_bo_pin(dobj, ddomain, &daddr); + amdgpu_bo_unreserve(dobj); + if (r) { + goto out_cleanup; + } + + if (adev->mman.buffer_funcs) { + time = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n); + if (time < 0) + goto out_cleanup; + if (time > 0) + amdgpu_benchmark_log_results(n, size, time, + sdomain, ddomain, "dma"); + } + +out_cleanup: + if (sobj) { + r = amdgpu_bo_reserve(sobj, false); + if (likely(r == 0)) { + amdgpu_bo_unpin(sobj); + amdgpu_bo_unreserve(sobj); + } + amdgpu_bo_unref(&sobj); + } + if (dobj) { + r = amdgpu_bo_reserve(dobj, false); + if (likely(r == 0)) { + amdgpu_bo_unpin(dobj); + amdgpu_bo_unreserve(dobj); + } + amdgpu_bo_unref(&dobj); + } + + if (r) { + DRM_ERROR("Error while benchmarking BO move.\n"); + } +} + +void amdgpu_benchmark(struct amdgpu_device *adev, int test_number) +{ + int i; + int common_modes[AMDGPU_BENCHMARK_COMMON_MODES_N] = { + 640 * 480 * 4, + 720 * 480 * 4, + 800 * 600 * 4, + 848 * 480 * 4, + 1024 * 768 * 4, + 1152 * 768 * 4, + 1280 * 720 * 4, + 1280 * 800 * 4, + 1280 * 854 * 4, + 1280 * 960 * 4, + 1280 * 1024 * 4, + 1440 * 900 * 4, + 1400 * 1050 * 4, + 1680 * 1050 * 4, + 1600 * 1200 * 4, + 1920 * 1080 * 4, + 1920 * 1200 * 4 + }; + + switch (test_number) { + case 1: + /* simple test, VRAM to GTT and GTT to VRAM */ + amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_DOMAIN_VRAM); + amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_DOMAIN_GTT); + break; + case 2: + /* simple test, VRAM to VRAM */ + amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_DOMAIN_VRAM); + break; + case 3: + /* GTT to VRAM, buffer size sweep, powers of 2 */ + for (i = 1; i <= 16384; i <<= 1) + amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_DOMAIN_VRAM); + break; + case 4: + /* VRAM to GTT, buffer size sweep, powers of 2 */ + for (i = 1; i <= 16384; i <<= 1) + amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_DOMAIN_GTT); + break; + case 5: + /* VRAM to VRAM, buffer size sweep, powers of 2 */ + for (i = 1; i <= 16384; i <<= 1) + amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_DOMAIN_VRAM); + break; + case 6: + /* GTT to VRAM, buffer size sweep, common modes */ + for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++) + amdgpu_benchmark_move(adev, common_modes[i], + AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_DOMAIN_VRAM); + break; + case 7: + /* VRAM to GTT, buffer size sweep, common modes */ + for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++) + amdgpu_benchmark_move(adev, common_modes[i], + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_DOMAIN_GTT); + break; + case 8: + /* VRAM to VRAM, buffer size sweep, common modes */ + for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++) + amdgpu_benchmark_move(adev, common_modes[i], + AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_DOMAIN_VRAM); + break; + + default: + DRM_ERROR("Unknown benchmark\n"); + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c new file mode 100644 index 000000000000..d7a3ab2624f0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -0,0 +1,359 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include +#include "amdgpu.h" +#include "atom.h" + +#include +#include +#include +/* + * BIOS. + */ + +/* If you boot an IGP board with a discrete card as the primary, + * the IGP rom is not accessible via the rom bar as the IGP rom is + * part of the system bios. On boot, the system bios puts a + * copy of the igp rom at the start of vram if a discrete card is + * present. + */ +static bool igp_read_bios_from_vram(struct amdgpu_device *adev) +{ + uint8_t __iomem *bios; + resource_size_t vram_base; + resource_size_t size = 256 * 1024; /* ??? */ + + if (!(adev->flags & AMDGPU_IS_APU)) + if (!amdgpu_card_posted(adev)) + return false; + + adev->bios = NULL; + vram_base = pci_resource_start(adev->pdev, 0); + bios = ioremap(vram_base, size); + if (!bios) { + return false; + } + + if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { + iounmap(bios); + return false; + } + adev->bios = kmalloc(size, GFP_KERNEL); + if (adev->bios == NULL) { + iounmap(bios); + return false; + } + memcpy_fromio(adev->bios, bios, size); + iounmap(bios); + return true; +} + +bool amdgpu_read_bios(struct amdgpu_device *adev) +{ + uint8_t __iomem *bios; + size_t size; + + adev->bios = NULL; + /* XXX: some cards may return 0 for rom size? ddx has a workaround */ + bios = pci_map_rom(adev->pdev, &size); + if (!bios) { + return false; + } + + if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { + pci_unmap_rom(adev->pdev, bios); + return false; + } + adev->bios = kmemdup(bios, size, GFP_KERNEL); + if (adev->bios == NULL) { + pci_unmap_rom(adev->pdev, bios); + return false; + } + pci_unmap_rom(adev->pdev, bios); + return true; +} + +static bool amdgpu_read_platform_bios(struct amdgpu_device *adev) +{ + uint8_t __iomem *bios; + size_t size; + + adev->bios = NULL; + + bios = pci_platform_rom(adev->pdev, &size); + if (!bios) { + return false; + } + + if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { + return false; + } + adev->bios = kmemdup(bios, size, GFP_KERNEL); + if (adev->bios == NULL) { + return false; + } + + return true; +} + +#ifdef CONFIG_ACPI +/* ATRM is used to get the BIOS on the discrete cards in + * dual-gpu systems. + */ +/* retrieve the ROM in 4k blocks */ +#define ATRM_BIOS_PAGE 4096 +/** + * amdgpu_atrm_call - fetch a chunk of the vbios + * + * @atrm_handle: acpi ATRM handle + * @bios: vbios image pointer + * @offset: offset of vbios image data to fetch + * @len: length of vbios image data to fetch + * + * Executes ATRM to fetch a chunk of the discrete + * vbios image on PX systems (all asics). + * Returns the length of the buffer fetched. + */ +static int amdgpu_atrm_call(acpi_handle atrm_handle, uint8_t *bios, + int offset, int len) +{ + acpi_status status; + union acpi_object atrm_arg_elements[2], *obj; + struct acpi_object_list atrm_arg; + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; + + atrm_arg.count = 2; + atrm_arg.pointer = &atrm_arg_elements[0]; + + atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; + atrm_arg_elements[0].integer.value = offset; + + atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; + atrm_arg_elements[1].integer.value = len; + + status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); + if (ACPI_FAILURE(status)) { + printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); + return -ENODEV; + } + + obj = (union acpi_object *)buffer.pointer; + memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); + len = obj->buffer.length; + kfree(buffer.pointer); + return len; +} + +static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev) +{ + int ret; + int size = 256 * 1024; + int i; + struct pci_dev *pdev = NULL; + acpi_handle dhandle, atrm_handle; + acpi_status status; + bool found = false; + + /* ATRM is for the discrete card only */ + if (adev->flags & AMDGPU_IS_APU) + return false; + + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { + dhandle = ACPI_HANDLE(&pdev->dev); + if (!dhandle) + continue; + + status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); + if (!ACPI_FAILURE(status)) { + found = true; + break; + } + } + + if (!found) { + while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { + dhandle = ACPI_HANDLE(&pdev->dev); + if (!dhandle) + continue; + + status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); + if (!ACPI_FAILURE(status)) { + found = true; + break; + } + } + } + + if (!found) + return false; + + adev->bios = kmalloc(size, GFP_KERNEL); + if (!adev->bios) { + DRM_ERROR("Unable to allocate bios\n"); + return false; + } + + for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { + ret = amdgpu_atrm_call(atrm_handle, + adev->bios, + (i * ATRM_BIOS_PAGE), + ATRM_BIOS_PAGE); + if (ret < ATRM_BIOS_PAGE) + break; + } + + if (i == 0 || adev->bios[0] != 0x55 || adev->bios[1] != 0xaa) { + kfree(adev->bios); + return false; + } + return true; +} +#else +static inline bool amdgpu_atrm_get_bios(struct amdgpu_device *adev) +{ + return false; +} +#endif + +static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev) +{ + if (adev->flags & AMDGPU_IS_APU) + return igp_read_bios_from_vram(adev); + else + return amdgpu_asic_read_disabled_bios(adev); +} + +#ifdef CONFIG_ACPI +static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev) +{ + bool ret = false; + struct acpi_table_header *hdr; + acpi_size tbl_size; + UEFI_ACPI_VFCT *vfct; + GOP_VBIOS_CONTENT *vbios; + VFCT_IMAGE_HEADER *vhdr; + + if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) + return false; + if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { + DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); + goto out_unmap; + } + + vfct = (UEFI_ACPI_VFCT *)hdr; + if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { + DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); + goto out_unmap; + } + + vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); + vhdr = &vbios->VbiosHeader; + DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", + vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, + vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); + + if (vhdr->PCIBus != adev->pdev->bus->number || + vhdr->PCIDevice != PCI_SLOT(adev->pdev->devfn) || + vhdr->PCIFunction != PCI_FUNC(adev->pdev->devfn) || + vhdr->VendorID != adev->pdev->vendor || + vhdr->DeviceID != adev->pdev->device) { + DRM_INFO("ACPI VFCT table is not for this card\n"); + goto out_unmap; + } + + if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { + DRM_ERROR("ACPI VFCT image truncated\n"); + goto out_unmap; + } + + adev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); + ret = !!adev->bios; + +out_unmap: + return ret; +} +#else +static inline bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev) +{ + return false; +} +#endif + +bool amdgpu_get_bios(struct amdgpu_device *adev) +{ + bool r; + uint16_t tmp; + + r = amdgpu_atrm_get_bios(adev); + if (r == false) + r = amdgpu_acpi_vfct_bios(adev); + if (r == false) + r = igp_read_bios_from_vram(adev); + if (r == false) + r = amdgpu_read_bios(adev); + if (r == false) { + r = amdgpu_read_disabled_bios(adev); + } + if (r == false) { + r = amdgpu_read_platform_bios(adev); + } + if (r == false || adev->bios == NULL) { + DRM_ERROR("Unable to locate a BIOS ROM\n"); + adev->bios = NULL; + return false; + } + if (adev->bios[0] != 0x55 || adev->bios[1] != 0xaa) { + printk("BIOS signature incorrect %x %x\n", adev->bios[0], adev->bios[1]); + goto free_bios; + } + + tmp = RBIOS16(0x18); + if (RBIOS8(tmp + 0x14) != 0x0) { + DRM_INFO("Not an x86 BIOS ROM, not using.\n"); + goto free_bios; + } + + adev->bios_header_start = RBIOS16(0x48); + if (!adev->bios_header_start) { + goto free_bios; + } + tmp = adev->bios_header_start + 4; + if (!memcmp(adev->bios + tmp, "ATOM", 4) || + !memcmp(adev->bios + tmp, "MOTA", 4)) { + adev->is_atom_bios = true; + } else { + adev->is_atom_bios = false; + } + + DRM_DEBUG("%sBIOS detected\n", adev->is_atom_bios ? "ATOM" : "COM"); + return true; +free_bios: + kfree(adev->bios); + adev->bios = NULL; + return false; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c new file mode 100644 index 000000000000..819fb861ac04 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -0,0 +1,268 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: + * Christian König + */ + +#include +#include "amdgpu.h" + +static int amdgpu_bo_list_create(struct amdgpu_fpriv *fpriv, + struct amdgpu_bo_list **result, + int *id) +{ + int r; + + *result = kzalloc(sizeof(struct amdgpu_bo_list), GFP_KERNEL); + if (!*result) + return -ENOMEM; + + mutex_lock(&fpriv->bo_list_lock); + r = idr_alloc(&fpriv->bo_list_handles, *result, + 0, 0, GFP_KERNEL); + if (r < 0) { + mutex_unlock(&fpriv->bo_list_lock); + kfree(*result); + return r; + } + *id = r; + + mutex_init(&(*result)->lock); + (*result)->num_entries = 0; + (*result)->array = NULL; + + mutex_lock(&(*result)->lock); + mutex_unlock(&fpriv->bo_list_lock); + + return 0; +} + +static void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id) +{ + struct amdgpu_bo_list *list; + + mutex_lock(&fpriv->bo_list_lock); + list = idr_find(&fpriv->bo_list_handles, id); + if (list) { + mutex_lock(&list->lock); + idr_remove(&fpriv->bo_list_handles, id); + mutex_unlock(&list->lock); + amdgpu_bo_list_free(list); + } + mutex_unlock(&fpriv->bo_list_lock); +} + +static int amdgpu_bo_list_set(struct amdgpu_device *adev, + struct drm_file *filp, + struct amdgpu_bo_list *list, + struct drm_amdgpu_bo_list_entry *info, + unsigned num_entries) +{ + struct amdgpu_bo_list_entry *array; + struct amdgpu_bo *gds_obj = adev->gds.gds_gfx_bo; + struct amdgpu_bo *gws_obj = adev->gds.gws_gfx_bo; + struct amdgpu_bo *oa_obj = adev->gds.oa_gfx_bo; + + bool has_userptr = false; + unsigned i; + + array = drm_malloc_ab(num_entries, sizeof(struct amdgpu_bo_list_entry)); + if (!array) + return -ENOMEM; + memset(array, 0, num_entries * sizeof(struct amdgpu_bo_list_entry)); + + for (i = 0; i < num_entries; ++i) { + struct amdgpu_bo_list_entry *entry = &array[i]; + struct drm_gem_object *gobj; + + gobj = drm_gem_object_lookup(adev->ddev, filp, info[i].bo_handle); + if (!gobj) + goto error_free; + + entry->robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); + drm_gem_object_unreference_unlocked(gobj); + entry->priority = info[i].bo_priority; + entry->prefered_domains = entry->robj->initial_domain; + entry->allowed_domains = entry->prefered_domains; + if (entry->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) + entry->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; + if (amdgpu_ttm_tt_has_userptr(entry->robj->tbo.ttm)) { + has_userptr = true; + entry->prefered_domains = AMDGPU_GEM_DOMAIN_GTT; + entry->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; + } + entry->tv.bo = &entry->robj->tbo; + entry->tv.shared = true; + + if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_GDS) + gds_obj = entry->robj; + if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_GWS) + gws_obj = entry->robj; + if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_OA) + oa_obj = entry->robj; + } + + for (i = 0; i < list->num_entries; ++i) + amdgpu_bo_unref(&list->array[i].robj); + + drm_free_large(list->array); + + list->gds_obj = gds_obj; + list->gws_obj = gws_obj; + list->oa_obj = oa_obj; + list->has_userptr = has_userptr; + list->array = array; + list->num_entries = num_entries; + + return 0; + +error_free: + drm_free_large(array); + return -ENOENT; +} + +struct amdgpu_bo_list * +amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id) +{ + struct amdgpu_bo_list *result; + + mutex_lock(&fpriv->bo_list_lock); + result = idr_find(&fpriv->bo_list_handles, id); + if (result) + mutex_lock(&result->lock); + mutex_unlock(&fpriv->bo_list_lock); + return result; +} + +void amdgpu_bo_list_put(struct amdgpu_bo_list *list) +{ + mutex_unlock(&list->lock); +} + +void amdgpu_bo_list_free(struct amdgpu_bo_list *list) +{ + unsigned i; + + for (i = 0; i < list->num_entries; ++i) + amdgpu_bo_unref(&list->array[i].robj); + + mutex_destroy(&list->lock); + drm_free_large(list->array); + kfree(list); +} + +int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + const uint32_t info_size = sizeof(struct drm_amdgpu_bo_list_entry); + + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + union drm_amdgpu_bo_list *args = data; + uint32_t handle = args->in.list_handle; + const void __user *uptr = (const void*)(long)args->in.bo_info_ptr; + + struct drm_amdgpu_bo_list_entry *info; + struct amdgpu_bo_list *list; + + int r; + + info = drm_malloc_ab(args->in.bo_number, + sizeof(struct drm_amdgpu_bo_list_entry)); + if (!info) + return -ENOMEM; + + /* copy the handle array from userspace to a kernel buffer */ + r = -EFAULT; + if (likely(info_size == args->in.bo_info_size)) { + unsigned long bytes = args->in.bo_number * + args->in.bo_info_size; + + if (copy_from_user(info, uptr, bytes)) + goto error_free; + + } else { + unsigned long bytes = min(args->in.bo_info_size, info_size); + unsigned i; + + memset(info, 0, args->in.bo_number * info_size); + for (i = 0; i < args->in.bo_number; ++i) { + if (copy_from_user(&info[i], uptr, bytes)) + goto error_free; + + uptr += args->in.bo_info_size; + } + } + + switch (args->in.operation) { + case AMDGPU_BO_LIST_OP_CREATE: + r = amdgpu_bo_list_create(fpriv, &list, &handle); + if (r) + goto error_free; + + r = amdgpu_bo_list_set(adev, filp, list, info, + args->in.bo_number); + amdgpu_bo_list_put(list); + if (r) + goto error_free; + + break; + + case AMDGPU_BO_LIST_OP_DESTROY: + amdgpu_bo_list_destroy(fpriv, handle); + handle = 0; + break; + + case AMDGPU_BO_LIST_OP_UPDATE: + r = -ENOENT; + list = amdgpu_bo_list_get(fpriv, handle); + if (!list) + goto error_free; + + r = amdgpu_bo_list_set(adev, filp, list, info, + args->in.bo_number); + amdgpu_bo_list_put(list); + if (r) + goto error_free; + + break; + + default: + r = -EINVAL; + goto error_free; + } + + memset(args, 0, sizeof(*args)); + args->out.list_handle = handle; + drm_free_large(info); + + return 0; + +error_free: + drm_free_large(info); + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c new file mode 100644 index 000000000000..6a8d28f81780 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -0,0 +1,1907 @@ +/* + * Copyright 2007-8 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + */ +#include +#include +#include +#include +#include +#include "amdgpu.h" +#include "atom.h" +#include "atombios_encoders.h" +#include "atombios_dp.h" +#include "amdgpu_connectors.h" +#include "amdgpu_i2c.h" + +#include + +void amdgpu_connector_hotplug(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + /* bail if the connector does not have hpd pin, e.g., + * VGA, TV, etc. + */ + if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) + return; + + amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); + + /* if the connector is already off, don't turn it back on */ + if (connector->dpms != DRM_MODE_DPMS_ON) + return; + + /* just deal with DP (not eDP) here. */ + if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { + struct amdgpu_connector_atom_dig *dig_connector = + amdgpu_connector->con_priv; + + /* if existing sink type was not DP no need to retrain */ + if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) + return; + + /* first get sink type as it may be reset after (un)plug */ + dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); + /* don't do anything if sink is not display port, i.e., + * passive dp->(dvi|hdmi) adaptor + */ + if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { + int saved_dpms = connector->dpms; + /* Only turn off the display if it's physically disconnected */ + if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); + } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { + /* set it to OFF so that drm_helper_connector_dpms() + * won't return immediately since the current state + * is ON at this point. + */ + connector->dpms = DRM_MODE_DPMS_OFF; + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); + } + connector->dpms = saved_dpms; + } + } +} + +static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) +{ + struct drm_crtc *crtc = encoder->crtc; + + if (crtc && crtc->enabled) { + drm_crtc_helper_set_mode(crtc, &crtc->mode, + crtc->x, crtc->y, crtc->primary->fb); + } +} + +int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *dig_connector; + int bpc = 8; + unsigned mode_clock, max_tmds_clock; + + switch (connector->connector_type) { + case DRM_MODE_CONNECTOR_DVII: + case DRM_MODE_CONNECTOR_HDMIB: + if (amdgpu_connector->use_digital) { + if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { + if (connector->display_info.bpc) + bpc = connector->display_info.bpc; + } + } + break; + case DRM_MODE_CONNECTOR_DVID: + case DRM_MODE_CONNECTOR_HDMIA: + if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { + if (connector->display_info.bpc) + bpc = connector->display_info.bpc; + } + break; + case DRM_MODE_CONNECTOR_DisplayPort: + dig_connector = amdgpu_connector->con_priv; + if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || + (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || + drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { + if (connector->display_info.bpc) + bpc = connector->display_info.bpc; + } + break; + case DRM_MODE_CONNECTOR_eDP: + case DRM_MODE_CONNECTOR_LVDS: + if (connector->display_info.bpc) + bpc = connector->display_info.bpc; + else { + struct drm_connector_helper_funcs *connector_funcs = + connector->helper_private; + struct drm_encoder *encoder = connector_funcs->best_encoder(connector); + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + + if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) + bpc = 6; + else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) + bpc = 8; + } + break; + } + + if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { + /* + * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make + * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at + * 12 bpc is always supported on hdmi deep color sinks, as this is + * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. + */ + if (bpc > 12) { + DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", + connector->name, bpc); + bpc = 12; + } + + /* Any defined maximum tmds clock limit we must not exceed? */ + if (connector->max_tmds_clock > 0) { + /* mode_clock is clock in kHz for mode to be modeset on this connector */ + mode_clock = amdgpu_connector->pixelclock_for_modeset; + + /* Maximum allowable input clock in kHz */ + max_tmds_clock = connector->max_tmds_clock * 1000; + + DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", + connector->name, mode_clock, max_tmds_clock); + + /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ + if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { + if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && + (mode_clock * 5/4 <= max_tmds_clock)) + bpc = 10; + else + bpc = 8; + + DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", + connector->name, bpc); + } + + if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { + bpc = 8; + DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", + connector->name, bpc); + } else if (bpc > 8) { + /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ + DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", + connector->name); + bpc = 8; + } + } + } + + if ((amdgpu_deep_color == 0) && (bpc > 8)) { + DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", + connector->name); + bpc = 8; + } + + DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", + connector->name, connector->display_info.bpc, bpc); + + return bpc; +} + +static void +amdgpu_connector_update_scratch_regs(struct drm_connector *connector, + enum drm_connector_status status) +{ + struct drm_encoder *best_encoder = NULL; + struct drm_encoder *encoder = NULL; + struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; + bool connected; + int i; + + best_encoder = connector_funcs->best_encoder(connector); + + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (connector->encoder_ids[i] == 0) + break; + + encoder = drm_encoder_find(connector->dev, + connector->encoder_ids[i]); + if (!encoder) + continue; + + if ((encoder == best_encoder) && (status == connector_status_connected)) + connected = true; + else + connected = false; + + amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); + + } +} + +static struct drm_encoder * +amdgpu_connector_find_encoder(struct drm_connector *connector, + int encoder_type) +{ + struct drm_encoder *encoder; + int i; + + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (connector->encoder_ids[i] == 0) + break; + encoder = drm_encoder_find(connector->dev, + connector->encoder_ids[i]); + if (!encoder) + continue; + + if (encoder->encoder_type == encoder_type) + return encoder; + } + return NULL; +} + +struct edid *amdgpu_connector_edid(struct drm_connector *connector) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct drm_property_blob *edid_blob = connector->edid_blob_ptr; + + if (amdgpu_connector->edid) { + return amdgpu_connector->edid; + } else if (edid_blob) { + struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); + if (edid) + amdgpu_connector->edid = edid; + } + return amdgpu_connector->edid; +} + +static struct edid * +amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) +{ + struct edid *edid; + + if (adev->mode_info.bios_hardcoded_edid) { + edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); + if (edid) { + memcpy((unsigned char *)edid, + (unsigned char *)adev->mode_info.bios_hardcoded_edid, + adev->mode_info.bios_hardcoded_edid_size); + return edid; + } + } + return NULL; +} + +static void amdgpu_connector_get_edid(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + if (amdgpu_connector->edid) + return; + + /* on hw with routers, select right port */ + if (amdgpu_connector->router.ddc_valid) + amdgpu_i2c_router_select_ddc_port(amdgpu_connector); + + if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != + ENCODER_OBJECT_ID_NONE) && + amdgpu_connector->ddc_bus->has_aux) { + amdgpu_connector->edid = drm_get_edid(connector, + &amdgpu_connector->ddc_bus->aux.ddc); + } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || + (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { + struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; + + if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || + dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && + amdgpu_connector->ddc_bus->has_aux) + amdgpu_connector->edid = drm_get_edid(connector, + &amdgpu_connector->ddc_bus->aux.ddc); + else if (amdgpu_connector->ddc_bus) + amdgpu_connector->edid = drm_get_edid(connector, + &amdgpu_connector->ddc_bus->adapter); + } else if (amdgpu_connector->ddc_bus) { + amdgpu_connector->edid = drm_get_edid(connector, + &amdgpu_connector->ddc_bus->adapter); + } + + if (!amdgpu_connector->edid) { + /* some laptops provide a hardcoded edid in rom for LCDs */ + if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || + (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) + amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); + } +} + +static void amdgpu_connector_free_edid(struct drm_connector *connector) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + if (amdgpu_connector->edid) { + kfree(amdgpu_connector->edid); + amdgpu_connector->edid = NULL; + } +} + +static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + int ret; + + if (amdgpu_connector->edid) { + drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid); + ret = drm_add_edid_modes(connector, amdgpu_connector->edid); + drm_edid_to_eld(connector, amdgpu_connector->edid); + return ret; + } + drm_mode_connector_update_edid_property(connector, NULL); + return 0; +} + +static struct drm_encoder * +amdgpu_connector_best_single_encoder(struct drm_connector *connector) +{ + int enc_id = connector->encoder_ids[0]; + + /* pick the encoder ids */ + if (enc_id) + return drm_encoder_find(connector->dev, enc_id); + return NULL; +} + +static void amdgpu_get_native_mode(struct drm_connector *connector) +{ + struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); + struct amdgpu_encoder *amdgpu_encoder; + + if (encoder == NULL) + return; + + amdgpu_encoder = to_amdgpu_encoder(encoder); + + if (!list_empty(&connector->probed_modes)) { + struct drm_display_mode *preferred_mode = + list_first_entry(&connector->probed_modes, + struct drm_display_mode, head); + + amdgpu_encoder->native_mode = *preferred_mode; + } else { + amdgpu_encoder->native_mode.clock = 0; + } +} + +static struct drm_display_mode * +amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_display_mode *mode = NULL; + struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; + + if (native_mode->hdisplay != 0 && + native_mode->vdisplay != 0 && + native_mode->clock != 0) { + mode = drm_mode_duplicate(dev, native_mode); + mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; + drm_mode_set_name(mode); + + DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); + } else if (native_mode->hdisplay != 0 && + native_mode->vdisplay != 0) { + /* mac laptops without an edid */ + /* Note that this is not necessarily the exact panel mode, + * but an approximation based on the cvt formula. For these + * systems we should ideally read the mode info out of the + * registers or add a mode table, but this works and is much + * simpler. + */ + mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); + mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; + DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); + } + return mode; +} + +static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_display_mode *mode = NULL; + struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; + int i; + struct mode_size { + int w; + int h; + } common_modes[17] = { + { 640, 480}, + { 720, 480}, + { 800, 600}, + { 848, 480}, + {1024, 768}, + {1152, 768}, + {1280, 720}, + {1280, 800}, + {1280, 854}, + {1280, 960}, + {1280, 1024}, + {1440, 900}, + {1400, 1050}, + {1680, 1050}, + {1600, 1200}, + {1920, 1080}, + {1920, 1200} + }; + + for (i = 0; i < 17; i++) { + if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { + if (common_modes[i].w > 1024 || + common_modes[i].h > 768) + continue; + } + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + if (common_modes[i].w > native_mode->hdisplay || + common_modes[i].h > native_mode->vdisplay || + (common_modes[i].w == native_mode->hdisplay && + common_modes[i].h == native_mode->vdisplay)) + continue; + } + if (common_modes[i].w < 320 || common_modes[i].h < 200) + continue; + + mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); + drm_mode_probed_add(connector, mode); + } +} + +static int amdgpu_connector_set_property(struct drm_connector *connector, + struct drm_property *property, + uint64_t val) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + struct drm_encoder *encoder; + struct amdgpu_encoder *amdgpu_encoder; + + if (property == adev->mode_info.coherent_mode_property) { + struct amdgpu_encoder_atom_dig *dig; + bool new_coherent_mode; + + /* need to find digital encoder on connector */ + encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); + if (!encoder) + return 0; + + amdgpu_encoder = to_amdgpu_encoder(encoder); + + if (!amdgpu_encoder->enc_priv) + return 0; + + dig = amdgpu_encoder->enc_priv; + new_coherent_mode = val ? true : false; + if (dig->coherent_mode != new_coherent_mode) { + dig->coherent_mode = new_coherent_mode; + amdgpu_connector_property_change_mode(&amdgpu_encoder->base); + } + } + + if (property == adev->mode_info.audio_property) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + /* need to find digital encoder on connector */ + encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); + if (!encoder) + return 0; + + amdgpu_encoder = to_amdgpu_encoder(encoder); + + if (amdgpu_connector->audio != val) { + amdgpu_connector->audio = val; + amdgpu_connector_property_change_mode(&amdgpu_encoder->base); + } + } + + if (property == adev->mode_info.dither_property) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + /* need to find digital encoder on connector */ + encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); + if (!encoder) + return 0; + + amdgpu_encoder = to_amdgpu_encoder(encoder); + + if (amdgpu_connector->dither != val) { + amdgpu_connector->dither = val; + amdgpu_connector_property_change_mode(&amdgpu_encoder->base); + } + } + + if (property == adev->mode_info.underscan_property) { + /* need to find digital encoder on connector */ + encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); + if (!encoder) + return 0; + + amdgpu_encoder = to_amdgpu_encoder(encoder); + + if (amdgpu_encoder->underscan_type != val) { + amdgpu_encoder->underscan_type = val; + amdgpu_connector_property_change_mode(&amdgpu_encoder->base); + } + } + + if (property == adev->mode_info.underscan_hborder_property) { + /* need to find digital encoder on connector */ + encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); + if (!encoder) + return 0; + + amdgpu_encoder = to_amdgpu_encoder(encoder); + + if (amdgpu_encoder->underscan_hborder != val) { + amdgpu_encoder->underscan_hborder = val; + amdgpu_connector_property_change_mode(&amdgpu_encoder->base); + } + } + + if (property == adev->mode_info.underscan_vborder_property) { + /* need to find digital encoder on connector */ + encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); + if (!encoder) + return 0; + + amdgpu_encoder = to_amdgpu_encoder(encoder); + + if (amdgpu_encoder->underscan_vborder != val) { + amdgpu_encoder->underscan_vborder = val; + amdgpu_connector_property_change_mode(&amdgpu_encoder->base); + } + } + + if (property == adev->mode_info.load_detect_property) { + struct amdgpu_connector *amdgpu_connector = + to_amdgpu_connector(connector); + + if (val == 0) + amdgpu_connector->dac_load_detect = false; + else + amdgpu_connector->dac_load_detect = true; + } + + if (property == dev->mode_config.scaling_mode_property) { + enum amdgpu_rmx_type rmx_type; + + if (connector->encoder) { + amdgpu_encoder = to_amdgpu_encoder(connector->encoder); + } else { + struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; + amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); + } + + switch (val) { + default: + case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; + case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; + case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; + case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; + } + if (amdgpu_encoder->rmx_type == rmx_type) + return 0; + + if ((rmx_type != DRM_MODE_SCALE_NONE) && + (amdgpu_encoder->native_mode.clock == 0)) + return 0; + + amdgpu_encoder->rmx_type = rmx_type; + + amdgpu_connector_property_change_mode(&amdgpu_encoder->base); + } + + return 0; +} + +static void +amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; + struct drm_display_mode *t, *mode; + + /* If the EDID preferred mode doesn't match the native mode, use it */ + list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { + if (mode->type & DRM_MODE_TYPE_PREFERRED) { + if (mode->hdisplay != native_mode->hdisplay || + mode->vdisplay != native_mode->vdisplay) + memcpy(native_mode, mode, sizeof(*mode)); + } + } + + /* Try to get native mode details from EDID if necessary */ + if (!native_mode->clock) { + list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { + if (mode->hdisplay == native_mode->hdisplay && + mode->vdisplay == native_mode->vdisplay) { + *native_mode = *mode; + drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); + DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); + break; + } + } + } + + if (!native_mode->clock) { + DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); + amdgpu_encoder->rmx_type = RMX_OFF; + } +} + +static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) +{ + struct drm_encoder *encoder; + int ret = 0; + struct drm_display_mode *mode; + + amdgpu_connector_get_edid(connector); + ret = amdgpu_connector_ddc_get_modes(connector); + if (ret > 0) { + encoder = amdgpu_connector_best_single_encoder(connector); + if (encoder) { + amdgpu_connector_fixup_lcd_native_mode(encoder, connector); + /* add scaled modes */ + amdgpu_connector_add_common_modes(encoder, connector); + } + return ret; + } + + encoder = amdgpu_connector_best_single_encoder(connector); + if (!encoder) + return 0; + + /* we have no EDID modes */ + mode = amdgpu_connector_lcd_native_mode(encoder); + if (mode) { + ret = 1; + drm_mode_probed_add(connector, mode); + /* add the width/height from vbios tables if available */ + connector->display_info.width_mm = mode->width_mm; + connector->display_info.height_mm = mode->height_mm; + /* add scaled modes */ + amdgpu_connector_add_common_modes(encoder, connector); + } + + return ret; +} + +static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); + + if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) + return MODE_PANEL; + + if (encoder) { + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; + + /* AVIVO hardware supports downscaling modes larger than the panel + * to the panel size, but I'm not sure this is desirable. + */ + if ((mode->hdisplay > native_mode->hdisplay) || + (mode->vdisplay > native_mode->vdisplay)) + return MODE_PANEL; + + /* if scaling is disabled, block non-native modes */ + if (amdgpu_encoder->rmx_type == RMX_OFF) { + if ((mode->hdisplay != native_mode->hdisplay) || + (mode->vdisplay != native_mode->vdisplay)) + return MODE_PANEL; + } + } + + return MODE_OK; +} + +static enum drm_connector_status +amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); + enum drm_connector_status ret = connector_status_disconnected; + int r; + + r = pm_runtime_get_sync(connector->dev->dev); + if (r < 0) + return connector_status_disconnected; + + if (encoder) { + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; + + /* check if panel is valid */ + if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) + ret = connector_status_connected; + + } + + /* check for edid as well */ + amdgpu_connector_get_edid(connector); + if (amdgpu_connector->edid) + ret = connector_status_connected; + /* check acpi lid status ??? */ + + amdgpu_connector_update_scratch_regs(connector, ret); + pm_runtime_mark_last_busy(connector->dev->dev); + pm_runtime_put_autosuspend(connector->dev->dev); + return ret; +} + +static void amdgpu_connector_destroy(struct drm_connector *connector) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + if (amdgpu_connector->ddc_bus->has_aux) + drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); + amdgpu_connector_free_edid(connector); + kfree(amdgpu_connector->con_priv); + drm_connector_unregister(connector); + drm_connector_cleanup(connector); + kfree(connector); +} + +static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, + struct drm_property *property, + uint64_t value) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_encoder *amdgpu_encoder; + enum amdgpu_rmx_type rmx_type; + + DRM_DEBUG_KMS("\n"); + if (property != dev->mode_config.scaling_mode_property) + return 0; + + if (connector->encoder) + amdgpu_encoder = to_amdgpu_encoder(connector->encoder); + else { + struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; + amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); + } + + switch (value) { + case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; + case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; + case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; + default: + case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; + } + if (amdgpu_encoder->rmx_type == rmx_type) + return 0; + + amdgpu_encoder->rmx_type = rmx_type; + + amdgpu_connector_property_change_mode(&amdgpu_encoder->base); + return 0; +} + + +static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { + .get_modes = amdgpu_connector_lvds_get_modes, + .mode_valid = amdgpu_connector_lvds_mode_valid, + .best_encoder = amdgpu_connector_best_single_encoder, +}; + +static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { + .dpms = drm_helper_connector_dpms, + .detect = amdgpu_connector_lvds_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = amdgpu_connector_destroy, + .set_property = amdgpu_connector_set_lcd_property, +}; + +static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) +{ + int ret; + + amdgpu_connector_get_edid(connector); + ret = amdgpu_connector_ddc_get_modes(connector); + + return ret; +} + +static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + + /* XXX check mode bandwidth */ + + if ((mode->clock / 10) > adev->clock.max_pixel_clock) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static enum drm_connector_status +amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct drm_encoder *encoder; + struct drm_encoder_helper_funcs *encoder_funcs; + bool dret = false; + enum drm_connector_status ret = connector_status_disconnected; + int r; + + r = pm_runtime_get_sync(connector->dev->dev); + if (r < 0) + return connector_status_disconnected; + + encoder = amdgpu_connector_best_single_encoder(connector); + if (!encoder) + ret = connector_status_disconnected; + + if (amdgpu_connector->ddc_bus) + dret = amdgpu_ddc_probe(amdgpu_connector, false); + if (dret) { + amdgpu_connector->detected_by_load = false; + amdgpu_connector_free_edid(connector); + amdgpu_connector_get_edid(connector); + + if (!amdgpu_connector->edid) { + DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", + connector->name); + ret = connector_status_connected; + } else { + amdgpu_connector->use_digital = + !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); + + /* some oems have boards with separate digital and analog connectors + * with a shared ddc line (often vga + hdmi) + */ + if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { + amdgpu_connector_free_edid(connector); + ret = connector_status_disconnected; + } else { + ret = connector_status_connected; + } + } + } else { + + /* if we aren't forcing don't do destructive polling */ + if (!force) { + /* only return the previous status if we last + * detected a monitor via load. + */ + if (amdgpu_connector->detected_by_load) + ret = connector->status; + goto out; + } + + if (amdgpu_connector->dac_load_detect && encoder) { + encoder_funcs = encoder->helper_private; + ret = encoder_funcs->detect(encoder, connector); + if (ret != connector_status_disconnected) + amdgpu_connector->detected_by_load = true; + } + } + + amdgpu_connector_update_scratch_regs(connector, ret); + +out: + pm_runtime_mark_last_busy(connector->dev->dev); + pm_runtime_put_autosuspend(connector->dev->dev); + + return ret; +} + +static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { + .get_modes = amdgpu_connector_vga_get_modes, + .mode_valid = amdgpu_connector_vga_mode_valid, + .best_encoder = amdgpu_connector_best_single_encoder, +}; + +static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { + .dpms = drm_helper_connector_dpms, + .detect = amdgpu_connector_vga_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = amdgpu_connector_destroy, + .set_property = amdgpu_connector_set_property, +}; + +static bool +amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + enum drm_connector_status status; + + if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { + if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) + status = connector_status_connected; + else + status = connector_status_disconnected; + if (connector->status == status) + return true; + } + + return false; +} + +/* + * DVI is complicated + * Do a DDC probe, if DDC probe passes, get the full EDID so + * we can do analog/digital monitor detection at this point. + * If the monitor is an analog monitor or we got no DDC, + * we need to find the DAC encoder object for this connector. + * If we got no DDC, we do load detection on the DAC encoder object. + * If we got analog DDC or load detection passes on the DAC encoder + * we have to check if this analog encoder is shared with anyone else (TV) + * if its shared we have to set the other connector to disconnected. + */ +static enum drm_connector_status +amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct drm_encoder *encoder = NULL; + struct drm_encoder_helper_funcs *encoder_funcs; + int i, r; + enum drm_connector_status ret = connector_status_disconnected; + bool dret = false, broken_edid = false; + + r = pm_runtime_get_sync(connector->dev->dev); + if (r < 0) + return connector_status_disconnected; + + if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { + ret = connector->status; + goto exit; + } + + if (amdgpu_connector->ddc_bus) + dret = amdgpu_ddc_probe(amdgpu_connector, false); + if (dret) { + amdgpu_connector->detected_by_load = false; + amdgpu_connector_free_edid(connector); + amdgpu_connector_get_edid(connector); + + if (!amdgpu_connector->edid) { + DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", + connector->name); + ret = connector_status_connected; + broken_edid = true; /* defer use_digital to later */ + } else { + amdgpu_connector->use_digital = + !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); + + /* some oems have boards with separate digital and analog connectors + * with a shared ddc line (often vga + hdmi) + */ + if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { + amdgpu_connector_free_edid(connector); + ret = connector_status_disconnected; + } else { + ret = connector_status_connected; + } + + /* This gets complicated. We have boards with VGA + HDMI with a + * shared DDC line and we have boards with DVI-D + HDMI with a shared + * DDC line. The latter is more complex because with DVI<->HDMI adapters + * you don't really know what's connected to which port as both are digital. + */ + if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { + struct drm_connector *list_connector; + struct amdgpu_connector *list_amdgpu_connector; + list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { + if (connector == list_connector) + continue; + list_amdgpu_connector = to_amdgpu_connector(list_connector); + if (list_amdgpu_connector->shared_ddc && + (list_amdgpu_connector->ddc_bus->rec.i2c_id == + amdgpu_connector->ddc_bus->rec.i2c_id)) { + /* cases where both connectors are digital */ + if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { + /* hpd is our only option in this case */ + if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { + amdgpu_connector_free_edid(connector); + ret = connector_status_disconnected; + } + } + } + } + } + } + } + + if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) + goto out; + + /* DVI-D and HDMI-A are digital only */ + if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || + (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) + goto out; + + /* if we aren't forcing don't do destructive polling */ + if (!force) { + /* only return the previous status if we last + * detected a monitor via load. + */ + if (amdgpu_connector->detected_by_load) + ret = connector->status; + goto out; + } + + /* find analog encoder */ + if (amdgpu_connector->dac_load_detect) { + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (connector->encoder_ids[i] == 0) + break; + + encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); + if (!encoder) + continue; + + if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && + encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) + continue; + + encoder_funcs = encoder->helper_private; + if (encoder_funcs->detect) { + if (!broken_edid) { + if (ret != connector_status_connected) { + /* deal with analog monitors without DDC */ + ret = encoder_funcs->detect(encoder, connector); + if (ret == connector_status_connected) { + amdgpu_connector->use_digital = false; + } + if (ret != connector_status_disconnected) + amdgpu_connector->detected_by_load = true; + } + } else { + enum drm_connector_status lret; + /* assume digital unless load detected otherwise */ + amdgpu_connector->use_digital = true; + lret = encoder_funcs->detect(encoder, connector); + DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); + if (lret == connector_status_connected) + amdgpu_connector->use_digital = false; + } + break; + } + } + } + +out: + /* updated in get modes as well since we need to know if it's analog or digital */ + amdgpu_connector_update_scratch_regs(connector, ret); + +exit: + pm_runtime_mark_last_busy(connector->dev->dev); + pm_runtime_put_autosuspend(connector->dev->dev); + + return ret; +} + +/* okay need to be smart in here about which encoder to pick */ +static struct drm_encoder * +amdgpu_connector_dvi_encoder(struct drm_connector *connector) +{ + int enc_id = connector->encoder_ids[0]; + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct drm_encoder *encoder; + int i; + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (connector->encoder_ids[i] == 0) + break; + + encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); + if (!encoder) + continue; + + if (amdgpu_connector->use_digital == true) { + if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) + return encoder; + } else { + if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || + encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) + return encoder; + } + } + + /* see if we have a default encoder TODO */ + + /* then check use digitial */ + /* pick the first one */ + if (enc_id) + return drm_encoder_find(connector->dev, enc_id); + return NULL; +} + +static void amdgpu_connector_dvi_force(struct drm_connector *connector) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + if (connector->force == DRM_FORCE_ON) + amdgpu_connector->use_digital = false; + if (connector->force == DRM_FORCE_ON_DIGITAL) + amdgpu_connector->use_digital = true; +} + +static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + /* XXX check mode bandwidth */ + + if (amdgpu_connector->use_digital && (mode->clock > 165000)) { + if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || + (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || + (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { + return MODE_OK; + } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { + /* HDMI 1.3+ supports max clock of 340 Mhz */ + if (mode->clock > 340000) + return MODE_CLOCK_HIGH; + else + return MODE_OK; + } else { + return MODE_CLOCK_HIGH; + } + } + + /* check against the max pixel clock */ + if ((mode->clock / 10) > adev->clock.max_pixel_clock) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { + .get_modes = amdgpu_connector_vga_get_modes, + .mode_valid = amdgpu_connector_dvi_mode_valid, + .best_encoder = amdgpu_connector_dvi_encoder, +}; + +static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { + .dpms = drm_helper_connector_dpms, + .detect = amdgpu_connector_dvi_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .set_property = amdgpu_connector_set_property, + .destroy = amdgpu_connector_destroy, + .force = amdgpu_connector_dvi_force, +}; + +static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; + struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); + int ret; + + if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || + (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { + struct drm_display_mode *mode; + + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { + if (!amdgpu_dig_connector->edp_on) + amdgpu_atombios_encoder_set_edp_panel_power(connector, + ATOM_TRANSMITTER_ACTION_POWER_ON); + amdgpu_connector_get_edid(connector); + ret = amdgpu_connector_ddc_get_modes(connector); + if (!amdgpu_dig_connector->edp_on) + amdgpu_atombios_encoder_set_edp_panel_power(connector, + ATOM_TRANSMITTER_ACTION_POWER_OFF); + } else { + /* need to setup ddc on the bridge */ + if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != + ENCODER_OBJECT_ID_NONE) { + if (encoder) + amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); + } + amdgpu_connector_get_edid(connector); + ret = amdgpu_connector_ddc_get_modes(connector); + } + + if (ret > 0) { + if (encoder) { + amdgpu_connector_fixup_lcd_native_mode(encoder, connector); + /* add scaled modes */ + amdgpu_connector_add_common_modes(encoder, connector); + } + return ret; + } + + if (!encoder) + return 0; + + /* we have no EDID modes */ + mode = amdgpu_connector_lcd_native_mode(encoder); + if (mode) { + ret = 1; + drm_mode_probed_add(connector, mode); + /* add the width/height from vbios tables if available */ + connector->display_info.width_mm = mode->width_mm; + connector->display_info.height_mm = mode->height_mm; + /* add scaled modes */ + amdgpu_connector_add_common_modes(encoder, connector); + } + } else { + /* need to setup ddc on the bridge */ + if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != + ENCODER_OBJECT_ID_NONE) { + if (encoder) + amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); + } + amdgpu_connector_get_edid(connector); + ret = amdgpu_connector_ddc_get_modes(connector); + + amdgpu_get_native_mode(connector); + } + + return ret; +} + +u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) +{ + struct drm_encoder *encoder; + struct amdgpu_encoder *amdgpu_encoder; + int i; + + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (connector->encoder_ids[i] == 0) + break; + + encoder = drm_encoder_find(connector->dev, + connector->encoder_ids[i]); + if (!encoder) + continue; + + amdgpu_encoder = to_amdgpu_encoder(encoder); + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_TRAVIS: + case ENCODER_OBJECT_ID_NUTMEG: + return amdgpu_encoder->encoder_id; + default: + break; + } + } + + return ENCODER_OBJECT_ID_NONE; +} + +static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) +{ + struct drm_encoder *encoder; + struct amdgpu_encoder *amdgpu_encoder; + int i; + bool found = false; + + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { + if (connector->encoder_ids[i] == 0) + break; + encoder = drm_encoder_find(connector->dev, + connector->encoder_ids[i]); + if (!encoder) + continue; + + amdgpu_encoder = to_amdgpu_encoder(encoder); + if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) + found = true; + } + + return found; +} + +bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + + if ((adev->clock.default_dispclk >= 53900) && + amdgpu_connector_encoder_is_hbr2(connector)) { + return true; + } + + return false; +} + +static enum drm_connector_status +amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + enum drm_connector_status ret = connector_status_disconnected; + struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; + struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); + int r; + + r = pm_runtime_get_sync(connector->dev->dev); + if (r < 0) + return connector_status_disconnected; + + if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { + ret = connector->status; + goto out; + } + + amdgpu_connector_free_edid(connector); + + if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || + (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { + if (encoder) { + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; + + /* check if panel is valid */ + if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) + ret = connector_status_connected; + } + /* eDP is always DP */ + amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; + if (!amdgpu_dig_connector->edp_on) + amdgpu_atombios_encoder_set_edp_panel_power(connector, + ATOM_TRANSMITTER_ACTION_POWER_ON); + if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) + ret = connector_status_connected; + if (!amdgpu_dig_connector->edp_on) + amdgpu_atombios_encoder_set_edp_panel_power(connector, + ATOM_TRANSMITTER_ACTION_POWER_OFF); + } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != + ENCODER_OBJECT_ID_NONE) { + /* DP bridges are always DP */ + amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; + /* get the DPCD from the bridge */ + amdgpu_atombios_dp_get_dpcd(amdgpu_connector); + + if (encoder) { + /* setup ddc on the bridge */ + amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); + /* bridge chips are always aux */ + if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */ + ret = connector_status_connected; + else if (amdgpu_connector->dac_load_detect) { /* try load detection */ + struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; + ret = encoder_funcs->detect(encoder, connector); + } + } + } else { + amdgpu_dig_connector->dp_sink_type = + amdgpu_atombios_dp_get_sinktype(amdgpu_connector); + if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { + ret = connector_status_connected; + if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) + amdgpu_atombios_dp_get_dpcd(amdgpu_connector); + } else { + if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { + if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) + ret = connector_status_connected; + } else { + /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ + if (amdgpu_ddc_probe(amdgpu_connector, false)) + ret = connector_status_connected; + } + } + } + + amdgpu_connector_update_scratch_regs(connector, ret); +out: + pm_runtime_mark_last_busy(connector->dev->dev); + pm_runtime_put_autosuspend(connector->dev->dev); + + return ret; +} + +static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; + + /* XXX check mode bandwidth */ + + if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || + (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { + struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); + + if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) + return MODE_PANEL; + + if (encoder) { + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; + + /* AVIVO hardware supports downscaling modes larger than the panel + * to the panel size, but I'm not sure this is desirable. + */ + if ((mode->hdisplay > native_mode->hdisplay) || + (mode->vdisplay > native_mode->vdisplay)) + return MODE_PANEL; + + /* if scaling is disabled, block non-native modes */ + if (amdgpu_encoder->rmx_type == RMX_OFF) { + if ((mode->hdisplay != native_mode->hdisplay) || + (mode->vdisplay != native_mode->vdisplay)) + return MODE_PANEL; + } + } + return MODE_OK; + } else { + if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || + (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { + return amdgpu_atombios_dp_mode_valid_helper(connector, mode); + } else { + if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { + /* HDMI 1.3+ supports max clock of 340 Mhz */ + if (mode->clock > 340000) + return MODE_CLOCK_HIGH; + } else { + if (mode->clock > 165000) + return MODE_CLOCK_HIGH; + } + } + } + + return MODE_OK; +} + +static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { + .get_modes = amdgpu_connector_dp_get_modes, + .mode_valid = amdgpu_connector_dp_mode_valid, + .best_encoder = amdgpu_connector_dvi_encoder, +}; + +static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { + .dpms = drm_helper_connector_dpms, + .detect = amdgpu_connector_dp_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .set_property = amdgpu_connector_set_property, + .destroy = amdgpu_connector_destroy, + .force = amdgpu_connector_dvi_force, +}; + +static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { + .dpms = drm_helper_connector_dpms, + .detect = amdgpu_connector_dp_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .set_property = amdgpu_connector_set_lcd_property, + .destroy = amdgpu_connector_destroy, + .force = amdgpu_connector_dvi_force, +}; + +void +amdgpu_connector_add(struct amdgpu_device *adev, + uint32_t connector_id, + uint32_t supported_device, + int connector_type, + struct amdgpu_i2c_bus_rec *i2c_bus, + uint16_t connector_object_id, + struct amdgpu_hpd *hpd, + struct amdgpu_router *router) +{ + struct drm_device *dev = adev->ddev; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector; + struct amdgpu_connector_atom_dig *amdgpu_dig_connector; + struct drm_encoder *encoder; + struct amdgpu_encoder *amdgpu_encoder; + uint32_t subpixel_order = SubPixelNone; + bool shared_ddc = false; + bool is_dp_bridge = false; + bool has_aux = false; + + if (connector_type == DRM_MODE_CONNECTOR_Unknown) + return; + + /* see if we already added it */ + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + amdgpu_connector = to_amdgpu_connector(connector); + if (amdgpu_connector->connector_id == connector_id) { + amdgpu_connector->devices |= supported_device; + return; + } + if (amdgpu_connector->ddc_bus && i2c_bus->valid) { + if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { + amdgpu_connector->shared_ddc = true; + shared_ddc = true; + } + if (amdgpu_connector->router_bus && router->ddc_valid && + (amdgpu_connector->router.router_id == router->router_id)) { + amdgpu_connector->shared_ddc = false; + shared_ddc = false; + } + } + } + + /* check if it's a dp bridge */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + amdgpu_encoder = to_amdgpu_encoder(encoder); + if (amdgpu_encoder->devices & supported_device) { + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_TRAVIS: + case ENCODER_OBJECT_ID_NUTMEG: + is_dp_bridge = true; + break; + default: + break; + } + } + } + + amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); + if (!amdgpu_connector) + return; + + connector = &amdgpu_connector->base; + + amdgpu_connector->connector_id = connector_id; + amdgpu_connector->devices = supported_device; + amdgpu_connector->shared_ddc = shared_ddc; + amdgpu_connector->connector_object_id = connector_object_id; + amdgpu_connector->hpd = *hpd; + + amdgpu_connector->router = *router; + if (router->ddc_valid || router->cd_valid) { + amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); + if (!amdgpu_connector->router_bus) + DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); + } + + if (is_dp_bridge) { + amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); + if (!amdgpu_dig_connector) + goto failed; + amdgpu_connector->con_priv = amdgpu_dig_connector; + if (i2c_bus->valid) { + amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); + if (amdgpu_connector->ddc_bus) + has_aux = true; + else + DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + } + switch (connector_type) { + case DRM_MODE_CONNECTOR_VGA: + case DRM_MODE_CONNECTOR_DVIA: + default: + drm_connector_init(dev, &amdgpu_connector->base, + &amdgpu_connector_dp_funcs, connector_type); + drm_connector_helper_add(&amdgpu_connector->base, + &amdgpu_connector_dp_helper_funcs); + connector->interlace_allowed = true; + connector->doublescan_allowed = true; + amdgpu_connector->dac_load_detect = true; + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.load_detect_property, + 1); + drm_object_attach_property(&amdgpu_connector->base.base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_NONE); + break; + case DRM_MODE_CONNECTOR_DVII: + case DRM_MODE_CONNECTOR_DVID: + case DRM_MODE_CONNECTOR_HDMIA: + case DRM_MODE_CONNECTOR_HDMIB: + case DRM_MODE_CONNECTOR_DisplayPort: + drm_connector_init(dev, &amdgpu_connector->base, + &amdgpu_connector_dp_funcs, connector_type); + drm_connector_helper_add(&amdgpu_connector->base, + &amdgpu_connector_dp_helper_funcs); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_property, + UNDERSCAN_OFF); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_hborder_property, + 0); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_vborder_property, + 0); + + drm_object_attach_property(&amdgpu_connector->base.base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_NONE); + + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.dither_property, + AMDGPU_FMT_DITHER_DISABLE); + + if (amdgpu_audio != 0) + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.audio_property, + AMDGPU_AUDIO_AUTO); + + subpixel_order = SubPixelHorizontalRGB; + connector->interlace_allowed = true; + if (connector_type == DRM_MODE_CONNECTOR_HDMIB) + connector->doublescan_allowed = true; + else + connector->doublescan_allowed = false; + if (connector_type == DRM_MODE_CONNECTOR_DVII) { + amdgpu_connector->dac_load_detect = true; + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.load_detect_property, + 1); + } + break; + case DRM_MODE_CONNECTOR_LVDS: + case DRM_MODE_CONNECTOR_eDP: + drm_connector_init(dev, &amdgpu_connector->base, + &amdgpu_connector_edp_funcs, connector_type); + drm_connector_helper_add(&amdgpu_connector->base, + &amdgpu_connector_dp_helper_funcs); + drm_object_attach_property(&amdgpu_connector->base.base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_FULLSCREEN); + subpixel_order = SubPixelHorizontalRGB; + connector->interlace_allowed = false; + connector->doublescan_allowed = false; + break; + } + } else { + switch (connector_type) { + case DRM_MODE_CONNECTOR_VGA: + drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); + drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); + if (i2c_bus->valid) { + amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); + if (!amdgpu_connector->ddc_bus) + DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + } + amdgpu_connector->dac_load_detect = true; + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.load_detect_property, + 1); + drm_object_attach_property(&amdgpu_connector->base.base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_NONE); + /* no HPD on analog connectors */ + amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; + connector->polled = DRM_CONNECTOR_POLL_CONNECT; + connector->interlace_allowed = true; + connector->doublescan_allowed = true; + break; + case DRM_MODE_CONNECTOR_DVIA: + drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); + drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); + if (i2c_bus->valid) { + amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); + if (!amdgpu_connector->ddc_bus) + DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + } + amdgpu_connector->dac_load_detect = true; + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.load_detect_property, + 1); + drm_object_attach_property(&amdgpu_connector->base.base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_NONE); + /* no HPD on analog connectors */ + amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; + connector->interlace_allowed = true; + connector->doublescan_allowed = true; + break; + case DRM_MODE_CONNECTOR_DVII: + case DRM_MODE_CONNECTOR_DVID: + amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); + if (!amdgpu_dig_connector) + goto failed; + amdgpu_connector->con_priv = amdgpu_dig_connector; + drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); + drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); + if (i2c_bus->valid) { + amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); + if (!amdgpu_connector->ddc_bus) + DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + } + subpixel_order = SubPixelHorizontalRGB; + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.coherent_mode_property, + 1); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_property, + UNDERSCAN_OFF); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_hborder_property, + 0); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_vborder_property, + 0); + drm_object_attach_property(&amdgpu_connector->base.base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_NONE); + + if (amdgpu_audio != 0) { + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.audio_property, + AMDGPU_AUDIO_AUTO); + } + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.dither_property, + AMDGPU_FMT_DITHER_DISABLE); + if (connector_type == DRM_MODE_CONNECTOR_DVII) { + amdgpu_connector->dac_load_detect = true; + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.load_detect_property, + 1); + } + connector->interlace_allowed = true; + if (connector_type == DRM_MODE_CONNECTOR_DVII) + connector->doublescan_allowed = true; + else + connector->doublescan_allowed = false; + break; + case DRM_MODE_CONNECTOR_HDMIA: + case DRM_MODE_CONNECTOR_HDMIB: + amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); + if (!amdgpu_dig_connector) + goto failed; + amdgpu_connector->con_priv = amdgpu_dig_connector; + drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); + drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); + if (i2c_bus->valid) { + amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); + if (!amdgpu_connector->ddc_bus) + DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + } + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.coherent_mode_property, + 1); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_property, + UNDERSCAN_OFF); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_hborder_property, + 0); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_vborder_property, + 0); + drm_object_attach_property(&amdgpu_connector->base.base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_NONE); + if (amdgpu_audio != 0) { + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.audio_property, + AMDGPU_AUDIO_AUTO); + } + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.dither_property, + AMDGPU_FMT_DITHER_DISABLE); + subpixel_order = SubPixelHorizontalRGB; + connector->interlace_allowed = true; + if (connector_type == DRM_MODE_CONNECTOR_HDMIB) + connector->doublescan_allowed = true; + else + connector->doublescan_allowed = false; + break; + case DRM_MODE_CONNECTOR_DisplayPort: + amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); + if (!amdgpu_dig_connector) + goto failed; + amdgpu_connector->con_priv = amdgpu_dig_connector; + drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); + drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); + if (i2c_bus->valid) { + amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); + if (amdgpu_connector->ddc_bus) + has_aux = true; + else + DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + } + subpixel_order = SubPixelHorizontalRGB; + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.coherent_mode_property, + 1); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_property, + UNDERSCAN_OFF); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_hborder_property, + 0); + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.underscan_vborder_property, + 0); + drm_object_attach_property(&amdgpu_connector->base.base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_NONE); + if (amdgpu_audio != 0) { + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.audio_property, + AMDGPU_AUDIO_AUTO); + } + drm_object_attach_property(&amdgpu_connector->base.base, + adev->mode_info.dither_property, + AMDGPU_FMT_DITHER_DISABLE); + connector->interlace_allowed = true; + /* in theory with a DP to VGA converter... */ + connector->doublescan_allowed = false; + break; + case DRM_MODE_CONNECTOR_eDP: + amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); + if (!amdgpu_dig_connector) + goto failed; + amdgpu_connector->con_priv = amdgpu_dig_connector; + drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); + drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); + if (i2c_bus->valid) { + amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); + if (amdgpu_connector->ddc_bus) + has_aux = true; + else + DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + } + drm_object_attach_property(&amdgpu_connector->base.base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_FULLSCREEN); + subpixel_order = SubPixelHorizontalRGB; + connector->interlace_allowed = false; + connector->doublescan_allowed = false; + break; + case DRM_MODE_CONNECTOR_LVDS: + amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); + if (!amdgpu_dig_connector) + goto failed; + amdgpu_connector->con_priv = amdgpu_dig_connector; + drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); + drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); + if (i2c_bus->valid) { + amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); + if (!amdgpu_connector->ddc_bus) + DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + } + drm_object_attach_property(&amdgpu_connector->base.base, + dev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_FULLSCREEN); + subpixel_order = SubPixelHorizontalRGB; + connector->interlace_allowed = false; + connector->doublescan_allowed = false; + break; + } + } + + if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { + if (i2c_bus->valid) + connector->polled = DRM_CONNECTOR_POLL_CONNECT; + } else + connector->polled = DRM_CONNECTOR_POLL_HPD; + + connector->display_info.subpixel_order = subpixel_order; + drm_connector_register(connector); + + if (has_aux) + amdgpu_atombios_dp_aux_init(amdgpu_connector); + + return; + +failed: + drm_connector_cleanup(connector); + kfree(connector); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h new file mode 100644 index 000000000000..61fcef15ad72 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h @@ -0,0 +1,42 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_CONNECTORS_H__ +#define __AMDGPU_CONNECTORS_H__ + +struct edid *amdgpu_connector_edid(struct drm_connector *connector); +void amdgpu_connector_hotplug(struct drm_connector *connector); +int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector); +u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); +bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector); +void +amdgpu_connector_add(struct amdgpu_device *adev, + uint32_t connector_id, + uint32_t supported_device, + int connector_type, + struct amdgpu_i2c_bus_rec *i2c_bus, + uint16_t connector_object_id, + struct amdgpu_hpd *hpd, + struct amdgpu_router *router); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c new file mode 100644 index 000000000000..70a90312d0a4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -0,0 +1,825 @@ +/* + * Copyright 2008 Jerome Glisse. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_trace.h" + +#define AMDGPU_CS_MAX_PRIORITY 32u +#define AMDGPU_CS_NUM_BUCKETS (AMDGPU_CS_MAX_PRIORITY + 1) + +/* This is based on the bucket sort with O(n) time complexity. + * An item with priority "i" is added to bucket[i]. The lists are then + * concatenated in descending order. + */ +struct amdgpu_cs_buckets { + struct list_head bucket[AMDGPU_CS_NUM_BUCKETS]; +}; + +static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b) +{ + unsigned i; + + for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) + INIT_LIST_HEAD(&b->bucket[i]); +} + +static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b, + struct list_head *item, unsigned priority) +{ + /* Since buffers which appear sooner in the relocation list are + * likely to be used more often than buffers which appear later + * in the list, the sort mustn't change the ordering of buffers + * with the same priority, i.e. it must be stable. + */ + list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]); +} + +static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b, + struct list_head *out_list) +{ + unsigned i; + + /* Connect the sorted buckets in the output list. */ + for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) { + list_splice(&b->bucket[i], out_list); + } +} + +int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, + u32 ip_instance, u32 ring, + struct amdgpu_ring **out_ring) +{ + /* Right now all IPs have only one instance - multiple rings. */ + if (ip_instance != 0) { + DRM_ERROR("invalid ip instance: %d\n", ip_instance); + return -EINVAL; + } + + switch (ip_type) { + default: + DRM_ERROR("unknown ip type: %d\n", ip_type); + return -EINVAL; + case AMDGPU_HW_IP_GFX: + if (ring < adev->gfx.num_gfx_rings) { + *out_ring = &adev->gfx.gfx_ring[ring]; + } else { + DRM_ERROR("only %d gfx rings are supported now\n", + adev->gfx.num_gfx_rings); + return -EINVAL; + } + break; + case AMDGPU_HW_IP_COMPUTE: + if (ring < adev->gfx.num_compute_rings) { + *out_ring = &adev->gfx.compute_ring[ring]; + } else { + DRM_ERROR("only %d compute rings are supported now\n", + adev->gfx.num_compute_rings); + return -EINVAL; + } + break; + case AMDGPU_HW_IP_DMA: + if (ring < 2) { + *out_ring = &adev->sdma[ring].ring; + } else { + DRM_ERROR("only two SDMA rings are supported\n"); + return -EINVAL; + } + break; + case AMDGPU_HW_IP_UVD: + *out_ring = &adev->uvd.ring; + break; + case AMDGPU_HW_IP_VCE: + if (ring < 2){ + *out_ring = &adev->vce.ring[ring]; + } else { + DRM_ERROR("only two VCE rings are supported\n"); + return -EINVAL; + } + break; + } + return 0; +} + +int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) +{ + union drm_amdgpu_cs *cs = data; + uint64_t *chunk_array_user; + uint64_t *chunk_array = NULL; + struct amdgpu_fpriv *fpriv = p->filp->driver_priv; + unsigned size, i; + int r = 0; + + if (!cs->in.num_chunks) + goto out; + + p->ctx_id = cs->in.ctx_id; + p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); + + /* get chunks */ + INIT_LIST_HEAD(&p->validated); + chunk_array = kcalloc(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); + if (chunk_array == NULL) { + r = -ENOMEM; + goto out; + } + + chunk_array_user = (uint64_t *)(unsigned long)(cs->in.chunks); + if (copy_from_user(chunk_array, chunk_array_user, + sizeof(uint64_t)*cs->in.num_chunks)) { + r = -EFAULT; + goto out; + } + + p->nchunks = cs->in.num_chunks; + p->chunks = kcalloc(p->nchunks, sizeof(struct amdgpu_cs_chunk), + GFP_KERNEL); + if (p->chunks == NULL) { + r = -ENOMEM; + goto out; + } + + for (i = 0; i < p->nchunks; i++) { + struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; + struct drm_amdgpu_cs_chunk user_chunk; + uint32_t __user *cdata; + + chunk_ptr = (void __user *)(unsigned long)chunk_array[i]; + if (copy_from_user(&user_chunk, chunk_ptr, + sizeof(struct drm_amdgpu_cs_chunk))) { + r = -EFAULT; + goto out; + } + p->chunks[i].chunk_id = user_chunk.chunk_id; + p->chunks[i].length_dw = user_chunk.length_dw; + if (p->chunks[i].chunk_id == AMDGPU_CHUNK_ID_IB) + p->num_ibs++; + + size = p->chunks[i].length_dw; + cdata = (void __user *)(unsigned long)user_chunk.chunk_data; + p->chunks[i].user_ptr = cdata; + + p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); + if (p->chunks[i].kdata == NULL) { + r = -ENOMEM; + goto out; + } + size *= sizeof(uint32_t); + if (copy_from_user(p->chunks[i].kdata, cdata, size)) { + r = -EFAULT; + goto out; + } + + if (p->chunks[i].chunk_id == AMDGPU_CHUNK_ID_FENCE) { + size = sizeof(struct drm_amdgpu_cs_chunk_fence); + if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) { + uint32_t handle; + struct drm_gem_object *gobj; + struct drm_amdgpu_cs_chunk_fence *fence_data; + + fence_data = (void *)p->chunks[i].kdata; + handle = fence_data->handle; + gobj = drm_gem_object_lookup(p->adev->ddev, + p->filp, handle); + if (gobj == NULL) { + r = -EINVAL; + goto out; + } + + p->uf.bo = gem_to_amdgpu_bo(gobj); + p->uf.offset = fence_data->offset; + } else { + r = -EINVAL; + goto out; + } + } + } + + p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL); + if (!p->ibs) { + r = -ENOMEM; + goto out; + } + + p->ib_bos = kcalloc(p->num_ibs, sizeof(struct amdgpu_bo_list_entry), + GFP_KERNEL); + if (!p->ib_bos) + r = -ENOMEM; + +out: + kfree(chunk_array); + return r; +} + +/* Returns how many bytes TTM can move per IB. + */ +static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) +{ + u64 real_vram_size = adev->mc.real_vram_size; + u64 vram_usage = atomic64_read(&adev->vram_usage); + + /* This function is based on the current VRAM usage. + * + * - If all of VRAM is free, allow relocating the number of bytes that + * is equal to 1/4 of the size of VRAM for this IB. + + * - If more than one half of VRAM is occupied, only allow relocating + * 1 MB of data for this IB. + * + * - From 0 to one half of used VRAM, the threshold decreases + * linearly. + * __________________ + * 1/4 of -|\ | + * VRAM | \ | + * | \ | + * | \ | + * | \ | + * | \ | + * | \ | + * | \________|1 MB + * |----------------| + * VRAM 0 % 100 % + * used used + * + * Note: It's a threshold, not a limit. The threshold must be crossed + * for buffer relocations to stop, so any buffer of an arbitrary size + * can be moved as long as the threshold isn't crossed before + * the relocation takes place. We don't want to disable buffer + * relocations completely. + * + * The idea is that buffers should be placed in VRAM at creation time + * and TTM should only do a minimum number of relocations during + * command submission. In practice, you need to submit at least + * a dozen IBs to move all buffers to VRAM if they are in GTT. + * + * Also, things can get pretty crazy under memory pressure and actual + * VRAM usage can change a lot, so playing safe even at 50% does + * consistently increase performance. + */ + + u64 half_vram = real_vram_size >> 1; + u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; + u64 bytes_moved_threshold = half_free_vram >> 1; + return max(bytes_moved_threshold, 1024*1024ull); +} + +int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p) +{ + struct amdgpu_fpriv *fpriv = p->filp->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; + struct amdgpu_device *adev = p->adev; + struct amdgpu_bo_list_entry *lobj; + struct list_head duplicates; + struct amdgpu_bo *bo; + u64 bytes_moved = 0, initial_bytes_moved; + u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev); + int r; + + INIT_LIST_HEAD(&duplicates); + r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates); + if (unlikely(r != 0)) { + return r; + } + + list_for_each_entry(lobj, &p->validated, tv.head) { + bo = lobj->robj; + if (!bo->pin_count) { + u32 domain = lobj->prefered_domains; + u32 current_domain = + amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); + + /* Check if this buffer will be moved and don't move it + * if we have moved too many buffers for this IB already. + * + * Note that this allows moving at least one buffer of + * any size, because it doesn't take the current "bo" + * into account. We don't want to disallow buffer moves + * completely. + */ + if (current_domain != AMDGPU_GEM_DOMAIN_CPU && + (domain & current_domain) == 0 && /* will be moved */ + bytes_moved > bytes_moved_threshold) { + /* don't move it */ + domain = current_domain; + } + + retry: + amdgpu_ttm_placement_from_domain(bo, domain); + initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); + r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + bytes_moved += atomic64_read(&adev->num_bytes_moved) - + initial_bytes_moved; + + if (unlikely(r)) { + if (r != -ERESTARTSYS && domain != lobj->allowed_domains) { + domain = lobj->allowed_domains; + goto retry; + } + ttm_eu_backoff_reservation(&p->ticket, &p->validated); + return r; + } + } + lobj->bo_va = amdgpu_vm_bo_find(vm, bo); + } + return 0; +} + +static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p) +{ + struct amdgpu_fpriv *fpriv = p->filp->driver_priv; + struct amdgpu_cs_buckets buckets; + bool need_mmap_lock; + int i, r; + + if (p->bo_list == NULL) + return 0; + + need_mmap_lock = p->bo_list->has_userptr; + amdgpu_cs_buckets_init(&buckets); + for (i = 0; i < p->bo_list->num_entries; i++) + amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head, + p->bo_list->array[i].priority); + + amdgpu_cs_buckets_get_list(&buckets, &p->validated); + p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm, + &p->validated); + + for (i = 0; i < p->num_ibs; i++) { + if (!p->ib_bos[i].robj) + continue; + + list_add(&p->ib_bos[i].tv.head, &p->validated); + } + + if (need_mmap_lock) + down_read(¤t->mm->mmap_sem); + + r = amdgpu_cs_list_validate(p); + + if (need_mmap_lock) + up_read(¤t->mm->mmap_sem); + + return r; +} + +static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) +{ + struct amdgpu_bo_list_entry *e; + int r; + + list_for_each_entry(e, &p->validated, tv.head) { + struct reservation_object *resv = e->robj->tbo.resv; + r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp); + + if (r) + return r; + } + return 0; +} + +static int cmp_size_smaller_first(void *priv, struct list_head *a, + struct list_head *b) +{ + struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head); + struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head); + + /* Sort A before B if A is smaller. */ + return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; +} + +/** + * cs_parser_fini() - clean parser states + * @parser: parser structure holding parsing context. + * @error: error number + * + * If error is set than unvalidate buffer, otherwise just free memory + * used by parsing context. + **/ +static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) +{ + unsigned i; + + if (!error) { + /* Sort the buffer list from the smallest to largest buffer, + * which affects the order of buffers in the LRU list. + * This assures that the smallest buffers are added first + * to the LRU list, so they are likely to be later evicted + * first, instead of large buffers whose eviction is more + * expensive. + * + * This slightly lowers the number of bytes moved by TTM + * per frame under memory pressure. + */ + list_sort(NULL, &parser->validated, cmp_size_smaller_first); + + ttm_eu_fence_buffer_objects(&parser->ticket, + &parser->validated, + &parser->ibs[parser->num_ibs-1].fence->base); + } else if (backoff) { + ttm_eu_backoff_reservation(&parser->ticket, + &parser->validated); + } + + if (parser->bo_list) + amdgpu_bo_list_put(parser->bo_list); + drm_free_large(parser->vm_bos); + for (i = 0; i < parser->nchunks; i++) + drm_free_large(parser->chunks[i].kdata); + kfree(parser->chunks); + for (i = 0; i < parser->num_ibs; i++) { + struct amdgpu_bo *bo = parser->ib_bos[i].robj; + amdgpu_ib_free(parser->adev, &parser->ibs[i]); + + if (bo) + drm_gem_object_unreference_unlocked(&bo->gem_base); + } + kfree(parser->ibs); + kfree(parser->ib_bos); + if (parser->uf.bo) + drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base); +} + +static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, + struct amdgpu_vm *vm) +{ + struct amdgpu_device *adev = p->adev; + struct amdgpu_bo_va *bo_va; + struct amdgpu_bo *bo; + int i, r; + + r = amdgpu_vm_update_page_directory(adev, vm); + if (r) + return r; + + r = amdgpu_vm_clear_freed(adev, vm); + if (r) + return r; + + if (p->bo_list) { + for (i = 0; i < p->bo_list->num_entries; i++) { + /* ignore duplicates */ + bo = p->bo_list->array[i].robj; + if (!bo) + continue; + + bo_va = p->bo_list->array[i].bo_va; + if (bo_va == NULL) + continue; + + r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); + if (r) + return r; + + amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update); + } + } + + for (i = 0; i < p->num_ibs; i++) { + bo = p->ib_bos[i].robj; + if (!bo) + continue; + + bo_va = p->ib_bos[i].bo_va; + if (!bo_va) + continue; + + r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); + if (r) + return r; + + amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update); + } + return amdgpu_vm_clear_invalids(adev, vm); +} + +static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, + struct amdgpu_cs_parser *parser) +{ + struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; + struct amdgpu_ring *ring; + int i, r; + + if (parser->num_ibs == 0) + return 0; + + /* Only for UVD/VCE VM emulation */ + for (i = 0; i < parser->num_ibs; i++) { + ring = parser->ibs[i].ring; + if (ring->funcs->parse_cs) { + r = amdgpu_ring_parse_cs(ring, parser, i); + if (r) + return r; + } + } + + mutex_lock(&vm->mutex); + r = amdgpu_bo_vm_update_pte(parser, vm); + if (r) { + goto out; + } + amdgpu_cs_sync_rings(parser); + + r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs, + parser->filp); + +out: + mutex_unlock(&vm->mutex); + return r; +} + +static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) +{ + if (r == -EDEADLK) { + r = amdgpu_gpu_reset(adev); + if (!r) + r = -EAGAIN; + } + return r; +} + +static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, + struct amdgpu_cs_parser *parser) +{ + struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; + int i, j; + int r; + + for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) { + struct amdgpu_cs_chunk *chunk; + struct amdgpu_ib *ib; + struct drm_amdgpu_cs_chunk_ib *chunk_ib; + struct amdgpu_bo_list_entry *ib_bo; + struct amdgpu_ring *ring; + struct drm_gem_object *gobj; + struct amdgpu_bo *aobj; + void *kptr; + + chunk = &parser->chunks[i]; + ib = &parser->ibs[j]; + chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; + + if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) + continue; + + gobj = drm_gem_object_lookup(adev->ddev, parser->filp, chunk_ib->handle); + if (gobj == NULL) + return -ENOENT; + aobj = gem_to_amdgpu_bo(gobj); + + r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, + chunk_ib->ip_instance, chunk_ib->ring, + &ring); + if (r) { + drm_gem_object_unreference_unlocked(gobj); + return r; + } + + if (ring->funcs->parse_cs) { + r = amdgpu_bo_reserve(aobj, false); + if (r) { + drm_gem_object_unreference_unlocked(gobj); + return r; + } + + r = amdgpu_bo_kmap(aobj, &kptr); + if (r) { + amdgpu_bo_unreserve(aobj); + drm_gem_object_unreference_unlocked(gobj); + return r; + } + + r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib); + if (r) { + DRM_ERROR("Failed to get ib !\n"); + amdgpu_bo_unreserve(aobj); + drm_gem_object_unreference_unlocked(gobj); + return r; + } + + memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); + amdgpu_bo_kunmap(aobj); + amdgpu_bo_unreserve(aobj); + } else { + r = amdgpu_ib_get(ring, vm, 0, ib); + if (r) { + DRM_ERROR("Failed to get ib !\n"); + drm_gem_object_unreference_unlocked(gobj); + return r; + } + + ib->gpu_addr = chunk_ib->va_start; + } + ib->length_dw = chunk_ib->ib_bytes / 4; + + if (chunk_ib->flags & AMDGPU_IB_FLAG_CE) + ib->is_const_ib = true; + if (chunk_ib->flags & AMDGPU_IB_FLAG_GDS) + ib->gds_needed = true; + if (ib->ring->current_filp != parser->filp) { + ib->ring->need_ctx_switch = true; + ib->ring->current_filp = parser->filp; + } + + ib_bo = &parser->ib_bos[j]; + ib_bo->robj = aobj; + ib_bo->prefered_domains = aobj->initial_domain; + ib_bo->allowed_domains = aobj->initial_domain; + ib_bo->priority = 0; + ib_bo->tv.bo = &aobj->tbo; + ib_bo->tv.shared = true; + j++; + } + + if (!parser->num_ibs) + return 0; + + /* add GDS resources to first IB */ + if (parser->bo_list) { + struct amdgpu_bo *gds = parser->bo_list->gds_obj; + struct amdgpu_bo *gws = parser->bo_list->gws_obj; + struct amdgpu_bo *oa = parser->bo_list->oa_obj; + struct amdgpu_ib *ib = &parser->ibs[0]; + + if (gds) { + ib->gds_base = amdgpu_bo_gpu_offset(gds); + ib->gds_size = amdgpu_bo_size(gds); + } + if (gws) { + ib->gws_base = amdgpu_bo_gpu_offset(gws); + ib->gws_size = amdgpu_bo_size(gws); + } + if (oa) { + ib->oa_base = amdgpu_bo_gpu_offset(oa); + ib->oa_size = amdgpu_bo_size(oa); + } + } + + /* wrap the last IB with user fence */ + if (parser->uf.bo) { + struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1]; + + /* UVD & VCE fw doesn't support user fences */ + if (ib->ring->type == AMDGPU_RING_TYPE_UVD || + ib->ring->type == AMDGPU_RING_TYPE_VCE) + return -EINVAL; + + ib->user = &parser->uf; + } + + return 0; +} + +int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) +{ + struct amdgpu_device *adev = dev->dev_private; + union drm_amdgpu_cs *cs = data; + struct amdgpu_cs_parser parser; + int r, i; + + down_read(&adev->exclusive_lock); + if (!adev->accel_working) { + up_read(&adev->exclusive_lock); + return -EBUSY; + } + /* initialize parser */ + memset(&parser, 0, sizeof(struct amdgpu_cs_parser)); + parser.filp = filp; + parser.adev = adev; + r = amdgpu_cs_parser_init(&parser, data); + if (r) { + DRM_ERROR("Failed to initialize parser !\n"); + amdgpu_cs_parser_fini(&parser, r, false); + up_read(&adev->exclusive_lock); + r = amdgpu_cs_handle_lockup(adev, r); + return r; + } + + r = amdgpu_cs_ib_fill(adev, &parser); + if (!r) { + r = amdgpu_cs_parser_relocs(&parser); + if (r && r != -ERESTARTSYS) + DRM_ERROR("Failed to parse relocation %d!\n", r); + } + + if (r) { + amdgpu_cs_parser_fini(&parser, r, false); + up_read(&adev->exclusive_lock); + r = amdgpu_cs_handle_lockup(adev, r); + return r; + } + + for (i = 0; i < parser.num_ibs; i++) + trace_amdgpu_cs(&parser, i); + + r = amdgpu_cs_ib_vm_chunk(adev, &parser); + if (r) { + goto out; + } + + cs->out.handle = parser.ibs[parser.num_ibs - 1].fence->seq; +out: + amdgpu_cs_parser_fini(&parser, r, true); + up_read(&adev->exclusive_lock); + r = amdgpu_cs_handle_lockup(adev, r); + return r; +} + +/** + * amdgpu_cs_wait_ioctl - wait for a command submission to finish + * + * @dev: drm device + * @data: data from userspace + * @filp: file private + * + * Wait for the command submission identified by handle to finish. + */ +int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + union drm_amdgpu_wait_cs *wait = data; + struct amdgpu_device *adev = dev->dev_private; + uint64_t seq[AMDGPU_MAX_RINGS] = {0}; + struct amdgpu_ring *ring = NULL; + unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); + long r; + + r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, + wait->in.ring, &ring); + if (r) + return r; + + seq[ring->idx] = wait->in.handle; + + r = amdgpu_fence_wait_seq_timeout(adev, seq, true, timeout); + if (r < 0) + return r; + + memset(wait, 0, sizeof(*wait)); + wait->out.status = (r == 0); + + return 0; +} + +/** + * amdgpu_cs_find_bo_va - find bo_va for VM address + * + * @parser: command submission parser context + * @addr: VM address + * @bo: resulting BO of the mapping found + * + * Search the buffer objects in the command submission context for a certain + * virtual memory address. Returns allocation structure when found, NULL + * otherwise. + */ +struct amdgpu_bo_va_mapping * +amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, + uint64_t addr, struct amdgpu_bo **bo) +{ + struct amdgpu_bo_list_entry *reloc; + struct amdgpu_bo_va_mapping *mapping; + + addr /= AMDGPU_GPU_PAGE_SIZE; + + list_for_each_entry(reloc, &parser->validated, tv.head) { + if (!reloc->bo_va) + continue; + + list_for_each_entry(mapping, &reloc->bo_va->mappings, list) { + if (mapping->it.start > addr || + addr > mapping->it.last) + continue; + + *bo = reloc->bo_va->bo; + return mapping; + } + } + + return NULL; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c new file mode 100644 index 000000000000..235010a83f8f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -0,0 +1,161 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: monk liu + */ + +#include +#include "amdgpu.h" + +static void amdgpu_ctx_do_release(struct kref *ref) +{ + struct amdgpu_ctx *ctx; + struct amdgpu_ctx_mgr *mgr; + + ctx = container_of(ref, struct amdgpu_ctx, refcount); + mgr = &ctx->fpriv->ctx_mgr; + + mutex_lock(&mgr->hlock); + idr_remove(&mgr->ctx_handles, ctx->id); + mutex_unlock(&mgr->hlock); + kfree(ctx); +} + +int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t *id, uint32_t flags) +{ + int r; + struct amdgpu_ctx *ctx; + struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; + + ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + mutex_lock(&mgr->hlock); + r = idr_alloc(&mgr->ctx_handles, ctx, 0, 0, GFP_KERNEL); + if (r < 0) { + mutex_unlock(&mgr->hlock); + kfree(ctx); + return r; + } + mutex_unlock(&mgr->hlock); + *id = (uint32_t)r; + + memset(ctx, 0, sizeof(*ctx)); + ctx->id = *id; + ctx->fpriv = fpriv; + kref_init(&ctx->refcount); + + return 0; +} + +int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id) +{ + int r; + struct amdgpu_ctx *ctx; + struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; + + rcu_read_lock(); + ctx = idr_find(&mgr->ctx_handles, id); + rcu_read_unlock(); + if (ctx) { + /* if no task is pending on this context, free it */ + r = kref_put(&ctx->refcount, amdgpu_ctx_do_release); + if (r == 1) + return 0;//context is removed successfully + else { + /* context is still in using */ + kref_get(&ctx->refcount); + return -ERESTARTSYS; + } + } + return -EINVAL; +} + +int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id, struct amdgpu_ctx_state *state) +{ + struct amdgpu_ctx *ctx; + struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; + + rcu_read_lock(); + ctx = idr_find(&mgr->ctx_handles, id); + rcu_read_unlock(); + if (ctx) { + /* state should alter with CS activity */ + *state = ctx->state; + return 0; + } + return -EINVAL; +} + +void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv) +{ + struct idr *idp; + struct amdgpu_ctx *ctx; + uint32_t id; + struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; + idp = &mgr->ctx_handles; + + idr_for_each_entry(idp,ctx,id) { + if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1) + DRM_ERROR("ctx (id=%ul) is still alive\n",ctx->id); + } + + mutex_destroy(&mgr->hlock); +} + +int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + int r; + uint32_t id; + uint32_t flags; + struct amdgpu_ctx_state state; + + union drm_amdgpu_ctx *args = data; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + + r = 0; + id = args->in.ctx_id; + flags = args->in.flags; + + switch (args->in.op) { + case AMDGPU_CTX_OP_ALLOC_CTX: + r = amdgpu_ctx_alloc(adev, fpriv, &id, flags); + args->out.alloc.ctx_id = id; + break; + case AMDGPU_CTX_OP_FREE_CTX: + r = amdgpu_ctx_free(adev, fpriv, id); + break; + case AMDGPU_CTX_OP_QUERY_STATE: + r = amdgpu_ctx_query(adev, fpriv, id, &state); + if (r == 0) { + args->out.state.flags = state.flags; + args->out.state.hangs = state.hangs; + } + break; + default: + return -EINVAL; + } + + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c new file mode 100644 index 000000000000..cd4bb90fa85c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -0,0 +1,1971 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_i2c.h" +#include "atom.h" +#include "amdgpu_atombios.h" +#include "bif/bif_4_1_d.h" + +static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); +static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); + +static const char *amdgpu_asic_name[] = { + "BONAIRE", + "KAVERI", + "KABINI", + "HAWAII", + "MULLINS", + "TOPAZ", + "TONGA", + "CARRIZO", + "LAST", +}; + +bool amdgpu_device_is_px(struct drm_device *dev) +{ + struct amdgpu_device *adev = dev->dev_private; + + if (adev->flags & AMDGPU_IS_PX) + return true; + return false; +} + +/* + * MMIO register access helper functions. + */ +uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, + bool always_indirect) +{ + if ((reg * 4) < adev->rmmio_size && !always_indirect) + return readl(((void __iomem *)adev->rmmio) + (reg * 4)); + else { + unsigned long flags; + uint32_t ret; + + spin_lock_irqsave(&adev->mmio_idx_lock, flags); + writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); + ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); + spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); + + return ret; + } +} + +void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, + bool always_indirect) +{ + if ((reg * 4) < adev->rmmio_size && !always_indirect) + writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); + else { + unsigned long flags; + + spin_lock_irqsave(&adev->mmio_idx_lock, flags); + writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); + writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); + spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); + } +} + +u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) +{ + if ((reg * 4) < adev->rio_mem_size) + return ioread32(adev->rio_mem + (reg * 4)); + else { + iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); + return ioread32(adev->rio_mem + (mmMM_DATA * 4)); + } +} + +void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + + if ((reg * 4) < adev->rio_mem_size) + iowrite32(v, adev->rio_mem + (reg * 4)); + else { + iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); + iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); + } +} + +/** + * amdgpu_mm_rdoorbell - read a doorbell dword + * + * @adev: amdgpu_device pointer + * @index: doorbell index + * + * Returns the value in the doorbell aperture at the + * requested doorbell index (CIK). + */ +u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) +{ + if (index < adev->doorbell.num_doorbells) { + return readl(adev->doorbell.ptr + index); + } else { + DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); + return 0; + } +} + +/** + * amdgpu_mm_wdoorbell - write a doorbell dword + * + * @adev: amdgpu_device pointer + * @index: doorbell index + * @v: value to write + * + * Writes @v to the doorbell aperture at the + * requested doorbell index (CIK). + */ +void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) +{ + if (index < adev->doorbell.num_doorbells) { + writel(v, adev->doorbell.ptr + index); + } else { + DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); + } +} + +/** + * amdgpu_invalid_rreg - dummy reg read function + * + * @adev: amdgpu device pointer + * @reg: offset of register + * + * Dummy register read function. Used for register blocks + * that certain asics don't have (all asics). + * Returns the value in the register. + */ +static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) +{ + DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); + BUG(); + return 0; +} + +/** + * amdgpu_invalid_wreg - dummy reg write function + * + * @adev: amdgpu device pointer + * @reg: offset of register + * @v: value to write to the register + * + * Dummy register read function. Used for register blocks + * that certain asics don't have (all asics). + */ +static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) +{ + DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", + reg, v); + BUG(); +} + +/** + * amdgpu_block_invalid_rreg - dummy reg read function + * + * @adev: amdgpu device pointer + * @block: offset of instance + * @reg: offset of register + * + * Dummy register read function. Used for register blocks + * that certain asics don't have (all asics). + * Returns the value in the register. + */ +static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, + uint32_t block, uint32_t reg) +{ + DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", + reg, block); + BUG(); + return 0; +} + +/** + * amdgpu_block_invalid_wreg - dummy reg write function + * + * @adev: amdgpu device pointer + * @block: offset of instance + * @reg: offset of register + * @v: value to write to the register + * + * Dummy register read function. Used for register blocks + * that certain asics don't have (all asics). + */ +static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, + uint32_t block, + uint32_t reg, uint32_t v) +{ + DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", + reg, block, v); + BUG(); +} + +static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) +{ + int r; + + if (adev->vram_scratch.robj == NULL) { + r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, + PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0, + NULL, &adev->vram_scratch.robj); + if (r) { + return r; + } + } + + r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); + if (unlikely(r != 0)) + return r; + r = amdgpu_bo_pin(adev->vram_scratch.robj, + AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); + if (r) { + amdgpu_bo_unreserve(adev->vram_scratch.robj); + return r; + } + r = amdgpu_bo_kmap(adev->vram_scratch.robj, + (void **)&adev->vram_scratch.ptr); + if (r) + amdgpu_bo_unpin(adev->vram_scratch.robj); + amdgpu_bo_unreserve(adev->vram_scratch.robj); + + return r; +} + +static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) +{ + int r; + + if (adev->vram_scratch.robj == NULL) { + return; + } + r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); + if (likely(r == 0)) { + amdgpu_bo_kunmap(adev->vram_scratch.robj); + amdgpu_bo_unpin(adev->vram_scratch.robj); + amdgpu_bo_unreserve(adev->vram_scratch.robj); + } + amdgpu_bo_unref(&adev->vram_scratch.robj); +} + +/** + * amdgpu_program_register_sequence - program an array of registers. + * + * @adev: amdgpu_device pointer + * @registers: pointer to the register array + * @array_size: size of the register array + * + * Programs an array or registers with and and or masks. + * This is a helper for setting golden registers. + */ +void amdgpu_program_register_sequence(struct amdgpu_device *adev, + const u32 *registers, + const u32 array_size) +{ + u32 tmp, reg, and_mask, or_mask; + int i; + + if (array_size % 3) + return; + + for (i = 0; i < array_size; i +=3) { + reg = registers[i + 0]; + and_mask = registers[i + 1]; + or_mask = registers[i + 2]; + + if (and_mask == 0xffffffff) { + tmp = or_mask; + } else { + tmp = RREG32(reg); + tmp &= ~and_mask; + tmp |= or_mask; + } + WREG32(reg, tmp); + } +} + +void amdgpu_pci_config_reset(struct amdgpu_device *adev) +{ + pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); +} + +/* + * GPU doorbell aperture helpers function. + */ +/** + * amdgpu_doorbell_init - Init doorbell driver information. + * + * @adev: amdgpu_device pointer + * + * Init doorbell driver information (CIK) + * Returns 0 on success, error on failure. + */ +static int amdgpu_doorbell_init(struct amdgpu_device *adev) +{ + /* doorbell bar mapping */ + adev->doorbell.base = pci_resource_start(adev->pdev, 2); + adev->doorbell.size = pci_resource_len(adev->pdev, 2); + + adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), + AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); + if (adev->doorbell.num_doorbells == 0) + return -EINVAL; + + adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32)); + if (adev->doorbell.ptr == NULL) { + return -ENOMEM; + } + DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base); + DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size); + + return 0; +} + +/** + * amdgpu_doorbell_fini - Tear down doorbell driver information. + * + * @adev: amdgpu_device pointer + * + * Tear down doorbell driver information (CIK) + */ +static void amdgpu_doorbell_fini(struct amdgpu_device *adev) +{ + iounmap(adev->doorbell.ptr); + adev->doorbell.ptr = NULL; +} + +/** + * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to + * setup amdkfd + * + * @adev: amdgpu_device pointer + * @aperture_base: output returning doorbell aperture base physical address + * @aperture_size: output returning doorbell aperture size in bytes + * @start_offset: output returning # of doorbell bytes reserved for amdgpu. + * + * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, + * takes doorbells required for its own rings and reports the setup to amdkfd. + * amdgpu reserved doorbells are at the start of the doorbell aperture. + */ +void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, + phys_addr_t *aperture_base, + size_t *aperture_size, + size_t *start_offset) +{ + /* + * The first num_doorbells are used by amdgpu. + * amdkfd takes whatever's left in the aperture. + */ + if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { + *aperture_base = adev->doorbell.base; + *aperture_size = adev->doorbell.size; + *start_offset = adev->doorbell.num_doorbells * sizeof(u32); + } else { + *aperture_base = 0; + *aperture_size = 0; + *start_offset = 0; + } +} + +/* + * amdgpu_wb_*() + * Writeback is the the method by which the the GPU updates special pages + * in memory with the status of certain GPU events (fences, ring pointers, + * etc.). + */ + +/** + * amdgpu_wb_fini - Disable Writeback and free memory + * + * @adev: amdgpu_device pointer + * + * Disables Writeback and frees the Writeback memory (all asics). + * Used at driver shutdown. + */ +static void amdgpu_wb_fini(struct amdgpu_device *adev) +{ + if (adev->wb.wb_obj) { + if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) { + amdgpu_bo_kunmap(adev->wb.wb_obj); + amdgpu_bo_unpin(adev->wb.wb_obj); + amdgpu_bo_unreserve(adev->wb.wb_obj); + } + amdgpu_bo_unref(&adev->wb.wb_obj); + adev->wb.wb = NULL; + adev->wb.wb_obj = NULL; + } +} + +/** + * amdgpu_wb_init- Init Writeback driver info and allocate memory + * + * @adev: amdgpu_device pointer + * + * Disables Writeback and frees the Writeback memory (all asics). + * Used at driver startup. + * Returns 0 on success or an -error on failure. + */ +static int amdgpu_wb_init(struct amdgpu_device *adev) +{ + int r; + + if (adev->wb.wb_obj == NULL) { + r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, NULL, &adev->wb.wb_obj); + if (r) { + dev_warn(adev->dev, "(%d) create WB bo failed\n", r); + return r; + } + r = amdgpu_bo_reserve(adev->wb.wb_obj, false); + if (unlikely(r != 0)) { + amdgpu_wb_fini(adev); + return r; + } + r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT, + &adev->wb.gpu_addr); + if (r) { + amdgpu_bo_unreserve(adev->wb.wb_obj); + dev_warn(adev->dev, "(%d) pin WB bo failed\n", r); + amdgpu_wb_fini(adev); + return r; + } + r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb); + amdgpu_bo_unreserve(adev->wb.wb_obj); + if (r) { + dev_warn(adev->dev, "(%d) map WB bo failed\n", r); + amdgpu_wb_fini(adev); + return r; + } + + adev->wb.num_wb = AMDGPU_MAX_WB; + memset(&adev->wb.used, 0, sizeof(adev->wb.used)); + + /* clear wb memory */ + memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE); + } + + return 0; +} + +/** + * amdgpu_wb_get - Allocate a wb entry + * + * @adev: amdgpu_device pointer + * @wb: wb index + * + * Allocate a wb slot for use by the driver (all asics). + * Returns 0 on success or -EINVAL on failure. + */ +int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) +{ + unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); + if (offset < adev->wb.num_wb) { + __set_bit(offset, adev->wb.used); + *wb = offset; + return 0; + } else { + return -EINVAL; + } +} + +/** + * amdgpu_wb_free - Free a wb entry + * + * @adev: amdgpu_device pointer + * @wb: wb index + * + * Free a wb slot allocated for use by the driver (all asics) + */ +void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) +{ + if (wb < adev->wb.num_wb) + __clear_bit(wb, adev->wb.used); +} + +/** + * amdgpu_vram_location - try to find VRAM location + * @adev: amdgpu device structure holding all necessary informations + * @mc: memory controller structure holding memory informations + * @base: base address at which to put VRAM + * + * Function will place try to place VRAM at base address provided + * as parameter (which is so far either PCI aperture address or + * for IGP TOM base address). + * + * If there is not enough space to fit the unvisible VRAM in the 32bits + * address space then we limit the VRAM size to the aperture. + * + * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, + * this shouldn't be a problem as we are using the PCI aperture as a reference. + * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but + * not IGP. + * + * Note: we use mc_vram_size as on some board we need to program the mc to + * cover the whole aperture even if VRAM size is inferior to aperture size + * Novell bug 204882 + along with lots of ubuntu ones + * + * Note: when limiting vram it's safe to overwritte real_vram_size because + * we are not in case where real_vram_size is inferior to mc_vram_size (ie + * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu + * ones) + * + * Note: IGP TOM addr should be the same as the aperture addr, we don't + * explicitly check for that thought. + * + * FIXME: when reducing VRAM size align new size on power of 2. + */ +void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) +{ + uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; + + mc->vram_start = base; + if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { + dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); + mc->real_vram_size = mc->aper_size; + mc->mc_vram_size = mc->aper_size; + } + mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; + if (limit && limit < mc->real_vram_size) + mc->real_vram_size = limit; + dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", + mc->mc_vram_size >> 20, mc->vram_start, + mc->vram_end, mc->real_vram_size >> 20); +} + +/** + * amdgpu_gtt_location - try to find GTT location + * @adev: amdgpu device structure holding all necessary informations + * @mc: memory controller structure holding memory informations + * + * Function will place try to place GTT before or after VRAM. + * + * If GTT size is bigger than space left then we ajust GTT size. + * Thus function will never fails. + * + * FIXME: when reducing GTT size align new size on power of 2. + */ +void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) +{ + u64 size_af, size_bf; + + size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; + size_bf = mc->vram_start & ~mc->gtt_base_align; + if (size_bf > size_af) { + if (mc->gtt_size > size_bf) { + dev_warn(adev->dev, "limiting GTT\n"); + mc->gtt_size = size_bf; + } + mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; + } else { + if (mc->gtt_size > size_af) { + dev_warn(adev->dev, "limiting GTT\n"); + mc->gtt_size = size_af; + } + mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; + } + mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; + dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", + mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); +} + +/* + * GPU helpers function. + */ +/** + * amdgpu_card_posted - check if the hw has already been initialized + * + * @adev: amdgpu_device pointer + * + * Check if the asic has been initialized (all asics). + * Used at driver startup. + * Returns true if initialized or false if not. + */ +bool amdgpu_card_posted(struct amdgpu_device *adev) +{ + uint32_t reg; + + /* then check MEM_SIZE, in case the crtcs are off */ + reg = RREG32(mmCONFIG_MEMSIZE); + + if (reg) + return true; + + return false; + +} + +/** + * amdgpu_boot_test_post_card - check and possibly initialize the hw + * + * @adev: amdgpu_device pointer + * + * Check if the asic is initialized and if not, attempt to initialize + * it (all asics). + * Returns true if initialized or false if not. + */ +bool amdgpu_boot_test_post_card(struct amdgpu_device *adev) +{ + if (amdgpu_card_posted(adev)) + return true; + + if (adev->bios) { + DRM_INFO("GPU not posted. posting now...\n"); + if (adev->is_atom_bios) + amdgpu_atom_asic_init(adev->mode_info.atom_context); + return true; + } else { + dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n"); + return false; + } +} + +/** + * amdgpu_dummy_page_init - init dummy page used by the driver + * + * @adev: amdgpu_device pointer + * + * Allocate the dummy page used by the driver (all asics). + * This dummy page is used by the driver as a filler for gart entries + * when pages are taken out of the GART + * Returns 0 on sucess, -ENOMEM on failure. + */ +int amdgpu_dummy_page_init(struct amdgpu_device *adev) +{ + if (adev->dummy_page.page) + return 0; + adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); + if (adev->dummy_page.page == NULL) + return -ENOMEM; + adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, + 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { + dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); + __free_page(adev->dummy_page.page); + adev->dummy_page.page = NULL; + return -ENOMEM; + } + return 0; +} + +/** + * amdgpu_dummy_page_fini - free dummy page used by the driver + * + * @adev: amdgpu_device pointer + * + * Frees the dummy page used by the driver (all asics). + */ +void amdgpu_dummy_page_fini(struct amdgpu_device *adev) +{ + if (adev->dummy_page.page == NULL) + return; + pci_unmap_page(adev->pdev, adev->dummy_page.addr, + PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + __free_page(adev->dummy_page.page); + adev->dummy_page.page = NULL; +} + + +/* ATOM accessor methods */ +/* + * ATOM is an interpreted byte code stored in tables in the vbios. The + * driver registers callbacks to access registers and the interpreter + * in the driver parses the tables and executes then to program specific + * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, + * atombios.h, and atom.c + */ + +/** + * cail_pll_read - read PLL register + * + * @info: atom card_info pointer + * @reg: PLL register offset + * + * Provides a PLL register accessor for the atom interpreter (r4xx+). + * Returns the value of the PLL register. + */ +static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) +{ + return 0; +} + +/** + * cail_pll_write - write PLL register + * + * @info: atom card_info pointer + * @reg: PLL register offset + * @val: value to write to the pll register + * + * Provides a PLL register accessor for the atom interpreter (r4xx+). + */ +static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) +{ + +} + +/** + * cail_mc_read - read MC (Memory Controller) register + * + * @info: atom card_info pointer + * @reg: MC register offset + * + * Provides an MC register accessor for the atom interpreter (r4xx+). + * Returns the value of the MC register. + */ +static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) +{ + return 0; +} + +/** + * cail_mc_write - write MC (Memory Controller) register + * + * @info: atom card_info pointer + * @reg: MC register offset + * @val: value to write to the pll register + * + * Provides a MC register accessor for the atom interpreter (r4xx+). + */ +static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) +{ + +} + +/** + * cail_reg_write - write MMIO register + * + * @info: atom card_info pointer + * @reg: MMIO register offset + * @val: value to write to the pll register + * + * Provides a MMIO register accessor for the atom interpreter (r4xx+). + */ +static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) +{ + struct amdgpu_device *adev = info->dev->dev_private; + + WREG32(reg, val); +} + +/** + * cail_reg_read - read MMIO register + * + * @info: atom card_info pointer + * @reg: MMIO register offset + * + * Provides an MMIO register accessor for the atom interpreter (r4xx+). + * Returns the value of the MMIO register. + */ +static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) +{ + struct amdgpu_device *adev = info->dev->dev_private; + uint32_t r; + + r = RREG32(reg); + return r; +} + +/** + * cail_ioreg_write - write IO register + * + * @info: atom card_info pointer + * @reg: IO register offset + * @val: value to write to the pll register + * + * Provides a IO register accessor for the atom interpreter (r4xx+). + */ +static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) +{ + struct amdgpu_device *adev = info->dev->dev_private; + + WREG32_IO(reg, val); +} + +/** + * cail_ioreg_read - read IO register + * + * @info: atom card_info pointer + * @reg: IO register offset + * + * Provides an IO register accessor for the atom interpreter (r4xx+). + * Returns the value of the IO register. + */ +static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) +{ + struct amdgpu_device *adev = info->dev->dev_private; + uint32_t r; + + r = RREG32_IO(reg); + return r; +} + +/** + * amdgpu_atombios_fini - free the driver info and callbacks for atombios + * + * @adev: amdgpu_device pointer + * + * Frees the driver info and register access callbacks for the ATOM + * interpreter (r4xx+). + * Called at driver shutdown. + */ +static void amdgpu_atombios_fini(struct amdgpu_device *adev) +{ + if (adev->mode_info.atom_context) + kfree(adev->mode_info.atom_context->scratch); + kfree(adev->mode_info.atom_context); + adev->mode_info.atom_context = NULL; + kfree(adev->mode_info.atom_card_info); + adev->mode_info.atom_card_info = NULL; +} + +/** + * amdgpu_atombios_init - init the driver info and callbacks for atombios + * + * @adev: amdgpu_device pointer + * + * Initializes the driver info and register access callbacks for the + * ATOM interpreter (r4xx+). + * Returns 0 on sucess, -ENOMEM on failure. + * Called at driver startup. + */ +static int amdgpu_atombios_init(struct amdgpu_device *adev) +{ + struct card_info *atom_card_info = + kzalloc(sizeof(struct card_info), GFP_KERNEL); + + if (!atom_card_info) + return -ENOMEM; + + adev->mode_info.atom_card_info = atom_card_info; + atom_card_info->dev = adev->ddev; + atom_card_info->reg_read = cail_reg_read; + atom_card_info->reg_write = cail_reg_write; + /* needed for iio ops */ + if (adev->rio_mem) { + atom_card_info->ioreg_read = cail_ioreg_read; + atom_card_info->ioreg_write = cail_ioreg_write; + } else { + DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); + atom_card_info->ioreg_read = cail_reg_read; + atom_card_info->ioreg_write = cail_reg_write; + } + atom_card_info->mc_read = cail_mc_read; + atom_card_info->mc_write = cail_mc_write; + atom_card_info->pll_read = cail_pll_read; + atom_card_info->pll_write = cail_pll_write; + + adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); + if (!adev->mode_info.atom_context) { + amdgpu_atombios_fini(adev); + return -ENOMEM; + } + + mutex_init(&adev->mode_info.atom_context->mutex); + amdgpu_atombios_scratch_regs_init(adev); + amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context); + return 0; +} + +/* if we get transitioned to only one device, take VGA back */ +/** + * amdgpu_vga_set_decode - enable/disable vga decode + * + * @cookie: amdgpu_device pointer + * @state: enable/disable vga decode + * + * Enable/disable vga decode (all asics). + * Returns VGA resource flags. + */ +static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) +{ + struct amdgpu_device *adev = cookie; + amdgpu_asic_set_vga_state(adev, state); + if (state) + return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | + VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; + else + return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; +} + +/** + * amdgpu_check_pot_argument - check that argument is a power of two + * + * @arg: value to check + * + * Validates that a certain argument is a power of two (all asics). + * Returns true if argument is valid. + */ +static bool amdgpu_check_pot_argument(int arg) +{ + return (arg & (arg - 1)) == 0; +} + +/** + * amdgpu_check_arguments - validate module params + * + * @adev: amdgpu_device pointer + * + * Validates certain module parameters and updates + * the associated values used by the driver (all asics). + */ +static void amdgpu_check_arguments(struct amdgpu_device *adev) +{ + /* vramlimit must be a power of two */ + if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) { + dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n", + amdgpu_vram_limit); + amdgpu_vram_limit = 0; + } + + if (amdgpu_gart_size != -1) { + /* gtt size must be power of two and greater or equal to 32M */ + if (amdgpu_gart_size < 32) { + dev_warn(adev->dev, "gart size (%d) too small\n", + amdgpu_gart_size); + amdgpu_gart_size = -1; + } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) { + dev_warn(adev->dev, "gart size (%d) must be a power of 2\n", + amdgpu_gart_size); + amdgpu_gart_size = -1; + } + } + + if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { + dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", + amdgpu_vm_size); + amdgpu_vm_size = 4; + } + + if (amdgpu_vm_size < 1) { + dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", + amdgpu_vm_size); + amdgpu_vm_size = 4; + } + + /* + * Max GPUVM size for Cayman, SI and CI are 40 bits. + */ + if (amdgpu_vm_size > 1024) { + dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", + amdgpu_vm_size); + amdgpu_vm_size = 4; + } + + /* defines number of bits in page table versus page directory, + * a page is 4KB so we have 12 bits offset, minimum 9 bits in the + * page table and the remaining bits are in the page directory */ + if (amdgpu_vm_block_size == -1) { + + /* Total bits covered by PD + PTs */ + unsigned bits = ilog2(amdgpu_vm_size) + 18; + + /* Make sure the PD is 4K in size up to 8GB address space. + Above that split equal between PD and PTs */ + if (amdgpu_vm_size <= 8) + amdgpu_vm_block_size = bits - 9; + else + amdgpu_vm_block_size = (bits + 3) / 2; + + } else if (amdgpu_vm_block_size < 9) { + dev_warn(adev->dev, "VM page table size (%d) too small\n", + amdgpu_vm_block_size); + amdgpu_vm_block_size = 9; + } + + if (amdgpu_vm_block_size > 24 || + (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { + dev_warn(adev->dev, "VM page table size (%d) too large\n", + amdgpu_vm_block_size); + amdgpu_vm_block_size = 9; + } +} + +/** + * amdgpu_switcheroo_set_state - set switcheroo state + * + * @pdev: pci dev pointer + * @state: vga switcheroo state + * + * Callback for the switcheroo driver. Suspends or resumes the + * the asics before or after it is powered up using ACPI methods. + */ +static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) +{ + struct drm_device *dev = pci_get_drvdata(pdev); + + if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) + return; + + if (state == VGA_SWITCHEROO_ON) { + unsigned d3_delay = dev->pdev->d3_delay; + + printk(KERN_INFO "amdgpu: switched on\n"); + /* don't suspend or resume card normally */ + dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; + + amdgpu_resume_kms(dev, true, true); + + dev->pdev->d3_delay = d3_delay; + + dev->switch_power_state = DRM_SWITCH_POWER_ON; + drm_kms_helper_poll_enable(dev); + } else { + printk(KERN_INFO "amdgpu: switched off\n"); + drm_kms_helper_poll_disable(dev); + dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; + amdgpu_suspend_kms(dev, true, true); + dev->switch_power_state = DRM_SWITCH_POWER_OFF; + } +} + +/** + * amdgpu_switcheroo_can_switch - see if switcheroo state can change + * + * @pdev: pci dev pointer + * + * Callback for the switcheroo driver. Check of the switcheroo + * state can be changed. + * Returns true if the state can be changed, false if not. + */ +static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) +{ + struct drm_device *dev = pci_get_drvdata(pdev); + + /* + * FIXME: open_count is protected by drm_global_mutex but that would lead to + * locking inversion with the driver load path. And the access here is + * completely racy anyway. So don't bother with locking for now. + */ + return dev->open_count == 0; +} + +static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { + .set_gpu_state = amdgpu_switcheroo_set_state, + .reprobe = NULL, + .can_switch = amdgpu_switcheroo_can_switch, +}; + +int amdgpu_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_ip_block_type block_type, + enum amdgpu_clockgating_state state) +{ + int i, r = 0; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (adev->ip_blocks[i].type == block_type) { + r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, + state); + if (r) + return r; + } + } + return r; +} + +int amdgpu_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_ip_block_type block_type, + enum amdgpu_powergating_state state) +{ + int i, r = 0; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (adev->ip_blocks[i].type == block_type) { + r = adev->ip_blocks[i].funcs->set_powergating_state(adev, + state); + if (r) + return r; + } + } + return r; +} + +const struct amdgpu_ip_block_version * amdgpu_get_ip_block( + struct amdgpu_device *adev, + enum amdgpu_ip_block_type type) +{ + int i; + + for (i = 0; i < adev->num_ip_blocks; i++) + if (adev->ip_blocks[i].type == type) + return &adev->ip_blocks[i]; + + return NULL; +} + +/** + * amdgpu_ip_block_version_cmp + * + * @adev: amdgpu_device pointer + * @type: enum amdgpu_ip_block_type + * @major: major version + * @minor: minor version + * + * return 0 if equal or greater + * return 1 if smaller or the ip_block doesn't exist + */ +int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, + enum amdgpu_ip_block_type type, + u32 major, u32 minor) +{ + const struct amdgpu_ip_block_version *ip_block; + ip_block = amdgpu_get_ip_block(adev, type); + + if (ip_block && ((ip_block->major > major) || + ((ip_block->major == major) && + (ip_block->minor >= minor)))) + return 0; + + return 1; +} + +static int amdgpu_early_init(struct amdgpu_device *adev) +{ + int i, r = -EINVAL; + + switch (adev->asic_type) { + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + + + + if (adev->ip_blocks == NULL) { + DRM_ERROR("No IP blocks found!\n"); + return r; + } + + for (i = 0; i < adev->num_ip_blocks; i++) { + if ((amdgpu_ip_block_mask & (1 << i)) == 0) { + DRM_ERROR("disabled ip block: %d\n", i); + adev->ip_block_enabled[i] = false; + } else { + if (adev->ip_blocks[i].funcs->early_init) { + r = adev->ip_blocks[i].funcs->early_init(adev); + if (r) + return r; + } + adev->ip_block_enabled[i] = true; + } + } + + return 0; +} + +static int amdgpu_init(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_block_enabled[i]) + continue; + r = adev->ip_blocks[i].funcs->sw_init(adev); + if (r) + return r; + /* need to do gmc hw init early so we can allocate gpu mem */ + if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) { + r = amdgpu_vram_scratch_init(adev); + if (r) + return r; + r = adev->ip_blocks[i].funcs->hw_init(adev); + if (r) + return r; + r = amdgpu_wb_init(adev); + if (r) + return r; + } + } + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_block_enabled[i]) + continue; + /* gmc hw init is done early */ + if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) + continue; + r = adev->ip_blocks[i].funcs->hw_init(adev); + if (r) + return r; + } + + return 0; +} + +static int amdgpu_late_init(struct amdgpu_device *adev) +{ + int i = 0, r; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_block_enabled[i]) + continue; + /* enable clockgating to save power */ + r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, + AMDGPU_CG_STATE_GATE); + if (r) + return r; + if (adev->ip_blocks[i].funcs->late_init) { + r = adev->ip_blocks[i].funcs->late_init(adev); + if (r) + return r; + } + } + + return 0; +} + +static int amdgpu_fini(struct amdgpu_device *adev) +{ + int i, r; + + for (i = adev->num_ip_blocks - 1; i >= 0; i--) { + if (!adev->ip_block_enabled[i]) + continue; + if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) { + amdgpu_wb_fini(adev); + amdgpu_vram_scratch_fini(adev); + } + /* ungate blocks before hw fini so that we can shutdown the blocks safely */ + r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, + AMDGPU_CG_STATE_UNGATE); + if (r) + return r; + r = adev->ip_blocks[i].funcs->hw_fini(adev); + /* XXX handle errors */ + } + + for (i = adev->num_ip_blocks - 1; i >= 0; i--) { + if (!adev->ip_block_enabled[i]) + continue; + r = adev->ip_blocks[i].funcs->sw_fini(adev); + /* XXX handle errors */ + adev->ip_block_enabled[i] = false; + } + + return 0; +} + +static int amdgpu_suspend(struct amdgpu_device *adev) +{ + int i, r; + + for (i = adev->num_ip_blocks - 1; i >= 0; i--) { + if (!adev->ip_block_enabled[i]) + continue; + /* ungate blocks so that suspend can properly shut them down */ + r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, + AMDGPU_CG_STATE_UNGATE); + /* XXX handle errors */ + r = adev->ip_blocks[i].funcs->suspend(adev); + /* XXX handle errors */ + } + + return 0; +} + +static int amdgpu_resume(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_block_enabled[i]) + continue; + r = adev->ip_blocks[i].funcs->resume(adev); + if (r) + return r; + } + + return 0; +} + +/** + * amdgpu_device_init - initialize the driver + * + * @adev: amdgpu_device pointer + * @pdev: drm dev pointer + * @pdev: pci dev pointer + * @flags: driver flags + * + * Initializes the driver info and hw (all asics). + * Returns 0 for success or an error on failure. + * Called at driver startup. + */ +int amdgpu_device_init(struct amdgpu_device *adev, + struct drm_device *ddev, + struct pci_dev *pdev, + uint32_t flags) +{ + int r, i; + bool runtime = false; + + adev->shutdown = false; + adev->dev = &pdev->dev; + adev->ddev = ddev; + adev->pdev = pdev; + adev->flags = flags; + adev->asic_type = flags & AMDGPU_ASIC_MASK; + adev->is_atom_bios = false; + adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; + adev->mc.gtt_size = 512 * 1024 * 1024; + adev->accel_working = false; + adev->num_rings = 0; + adev->mman.buffer_funcs = NULL; + adev->mman.buffer_funcs_ring = NULL; + adev->vm_manager.vm_pte_funcs = NULL; + adev->vm_manager.vm_pte_funcs_ring = NULL; + adev->gart.gart_funcs = NULL; + adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); + + adev->smc_rreg = &amdgpu_invalid_rreg; + adev->smc_wreg = &amdgpu_invalid_wreg; + adev->pcie_rreg = &amdgpu_invalid_rreg; + adev->pcie_wreg = &amdgpu_invalid_wreg; + adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; + adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; + adev->didt_rreg = &amdgpu_invalid_rreg; + adev->didt_wreg = &amdgpu_invalid_wreg; + adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; + adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; + + DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", + amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, + pdev->subsystem_vendor, pdev->subsystem_device); + + /* mutex initialization are all done here so we + * can recall function without having locking issues */ + mutex_init(&adev->ring_lock); + atomic_set(&adev->irq.ih.lock, 0); + mutex_init(&adev->gem.mutex); + mutex_init(&adev->pm.mutex); + mutex_init(&adev->gfx.gpu_clock_mutex); + mutex_init(&adev->srbm_mutex); + mutex_init(&adev->grbm_idx_mutex); + init_rwsem(&adev->pm.mclk_lock); + init_rwsem(&adev->exclusive_lock); + mutex_init(&adev->mn_lock); + hash_init(adev->mn_hash); + + amdgpu_check_arguments(adev); + + /* Registers mapping */ + /* TODO: block userspace mapping of io register */ + spin_lock_init(&adev->mmio_idx_lock); + spin_lock_init(&adev->smc_idx_lock); + spin_lock_init(&adev->pcie_idx_lock); + spin_lock_init(&adev->uvd_ctx_idx_lock); + spin_lock_init(&adev->didt_idx_lock); + spin_lock_init(&adev->audio_endpt_idx_lock); + + adev->rmmio_base = pci_resource_start(adev->pdev, 5); + adev->rmmio_size = pci_resource_len(adev->pdev, 5); + adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); + if (adev->rmmio == NULL) { + return -ENOMEM; + } + DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); + DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); + + /* doorbell bar mapping */ + amdgpu_doorbell_init(adev); + + /* io port mapping */ + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { + adev->rio_mem_size = pci_resource_len(adev->pdev, i); + adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); + break; + } + } + if (adev->rio_mem == NULL) + DRM_ERROR("Unable to find PCI I/O BAR\n"); + + /* early init functions */ + r = amdgpu_early_init(adev); + if (r) + return r; + + /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ + /* this will fail for cards that aren't VGA class devices, just + * ignore it */ + vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); + + if (amdgpu_runtime_pm == 1) + runtime = true; + if (amdgpu_device_is_px(ddev)) + runtime = true; + vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime); + if (runtime) + vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); + + /* Read BIOS */ + if (!amdgpu_get_bios(adev)) + return -EINVAL; + /* Must be an ATOMBIOS */ + if (!adev->is_atom_bios) { + dev_err(adev->dev, "Expecting atombios for GPU\n"); + return -EINVAL; + } + r = amdgpu_atombios_init(adev); + if (r) + return r; + + /* Post card if necessary */ + if (!amdgpu_card_posted(adev)) { + if (!adev->bios) { + dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n"); + return -EINVAL; + } + DRM_INFO("GPU not posted. posting now...\n"); + amdgpu_atom_asic_init(adev->mode_info.atom_context); + } + + /* Initialize clocks */ + r = amdgpu_atombios_get_clock_info(adev); + if (r) + return r; + /* init i2c buses */ + amdgpu_atombios_i2c_init(adev); + + /* Fence driver */ + r = amdgpu_fence_driver_init(adev); + if (r) + return r; + + /* init the mode config */ + drm_mode_config_init(adev->ddev); + + r = amdgpu_init(adev); + if (r) { + amdgpu_fini(adev); + return r; + } + + adev->accel_working = true; + + amdgpu_fbdev_init(adev); + + r = amdgpu_ib_pool_init(adev); + if (r) { + dev_err(adev->dev, "IB initialization failed (%d).\n", r); + return r; + } + + r = amdgpu_ib_ring_tests(adev); + if (r) + DRM_ERROR("ib ring test failed (%d).\n", r); + + r = amdgpu_gem_debugfs_init(adev); + if (r) { + DRM_ERROR("registering gem debugfs failed (%d).\n", r); + } + + r = amdgpu_debugfs_regs_init(adev); + if (r) { + DRM_ERROR("registering register debugfs failed (%d).\n", r); + } + + if ((amdgpu_testing & 1)) { + if (adev->accel_working) + amdgpu_test_moves(adev); + else + DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); + } + if ((amdgpu_testing & 2)) { + if (adev->accel_working) + amdgpu_test_syncing(adev); + else + DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n"); + } + if (amdgpu_benchmarking) { + if (adev->accel_working) + amdgpu_benchmark(adev, amdgpu_benchmarking); + else + DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); + } + + /* enable clockgating, etc. after ib tests, etc. since some blocks require + * explicit gating rather than handling it automatically. + */ + r = amdgpu_late_init(adev); + if (r) + return r; + + return 0; +} + +static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev); + +/** + * amdgpu_device_fini - tear down the driver + * + * @adev: amdgpu_device pointer + * + * Tear down the driver info (all asics). + * Called at driver shutdown. + */ +void amdgpu_device_fini(struct amdgpu_device *adev) +{ + int r; + + DRM_INFO("amdgpu: finishing device.\n"); + adev->shutdown = true; + /* evict vram memory */ + amdgpu_bo_evict_vram(adev); + amdgpu_ib_pool_fini(adev); + amdgpu_fence_driver_fini(adev); + amdgpu_fbdev_fini(adev); + r = amdgpu_fini(adev); + if (adev->ip_block_enabled) + kfree(adev->ip_block_enabled); + adev->ip_block_enabled = NULL; + adev->accel_working = false; + /* free i2c buses */ + amdgpu_i2c_fini(adev); + amdgpu_atombios_fini(adev); + kfree(adev->bios); + adev->bios = NULL; + vga_switcheroo_unregister_client(adev->pdev); + vga_client_register(adev->pdev, NULL, NULL, NULL); + if (adev->rio_mem) + pci_iounmap(adev->pdev, adev->rio_mem); + adev->rio_mem = NULL; + iounmap(adev->rmmio); + adev->rmmio = NULL; + amdgpu_doorbell_fini(adev); + amdgpu_debugfs_regs_cleanup(adev); + amdgpu_debugfs_remove_files(adev); +} + + +/* + * Suspend & resume. + */ +/** + * amdgpu_suspend_kms - initiate device suspend + * + * @pdev: drm dev pointer + * @state: suspend state + * + * Puts the hw in the suspend state (all asics). + * Returns 0 for success or an error on failure. + * Called at driver suspend. + */ +int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) +{ + struct amdgpu_device *adev; + struct drm_crtc *crtc; + struct drm_connector *connector; + int i, r; + bool force_completion = false; + + if (dev == NULL || dev->dev_private == NULL) { + return -ENODEV; + } + + adev = dev->dev_private; + + if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) + return 0; + + drm_kms_helper_poll_disable(dev); + + /* turn off display hw */ + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); + } + + /* unpin the front buffers */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); + struct amdgpu_bo *robj; + + if (rfb == NULL || rfb->obj == NULL) { + continue; + } + robj = gem_to_amdgpu_bo(rfb->obj); + /* don't unpin kernel fb objects */ + if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { + r = amdgpu_bo_reserve(robj, false); + if (r == 0) { + amdgpu_bo_unpin(robj); + amdgpu_bo_unreserve(robj); + } + } + } + /* evict vram memory */ + amdgpu_bo_evict_vram(adev); + + /* wait for gpu to finish processing current batch */ + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + if (!ring) + continue; + + r = amdgpu_fence_wait_empty(ring); + if (r) { + /* delay GPU reset to resume */ + force_completion = true; + } + } + if (force_completion) { + amdgpu_fence_driver_force_completion(adev); + } + + r = amdgpu_suspend(adev); + + /* evict remaining vram memory */ + amdgpu_bo_evict_vram(adev); + + pci_save_state(dev->pdev); + if (suspend) { + /* Shut down the device */ + pci_disable_device(dev->pdev); + pci_set_power_state(dev->pdev, PCI_D3hot); + } + + if (fbcon) { + console_lock(); + amdgpu_fbdev_set_suspend(adev, 1); + console_unlock(); + } + return 0; +} + +/** + * amdgpu_resume_kms - initiate device resume + * + * @pdev: drm dev pointer + * + * Bring the hw back to operating state (all asics). + * Returns 0 for success or an error on failure. + * Called at driver resume. + */ +int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon) +{ + struct drm_connector *connector; + struct amdgpu_device *adev = dev->dev_private; + int r; + + if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) + return 0; + + if (fbcon) { + console_lock(); + } + if (resume) { + pci_set_power_state(dev->pdev, PCI_D0); + pci_restore_state(dev->pdev); + if (pci_enable_device(dev->pdev)) { + if (fbcon) + console_unlock(); + return -1; + } + } + + /* post card */ + amdgpu_atom_asic_init(adev->mode_info.atom_context); + + r = amdgpu_resume(adev); + + r = amdgpu_ib_ring_tests(adev); + if (r) + DRM_ERROR("ib ring test failed (%d).\n", r); + + r = amdgpu_late_init(adev); + if (r) + return r; + + /* blat the mode back in */ + if (fbcon) { + drm_helper_resume_force_mode(dev); + /* turn on display hw */ + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); + } + } + + drm_kms_helper_poll_enable(dev); + + if (fbcon) { + amdgpu_fbdev_set_suspend(adev, 0); + console_unlock(); + } + + return 0; +} + +/** + * amdgpu_gpu_reset - reset the asic + * + * @adev: amdgpu device pointer + * + * Attempt the reset the GPU if it has hung (all asics). + * Returns 0 for success or an error on failure. + */ +int amdgpu_gpu_reset(struct amdgpu_device *adev) +{ + unsigned ring_sizes[AMDGPU_MAX_RINGS]; + uint32_t *ring_data[AMDGPU_MAX_RINGS]; + + bool saved = false; + + int i, r; + int resched; + + down_write(&adev->exclusive_lock); + + if (!adev->needs_reset) { + up_write(&adev->exclusive_lock); + return 0; + } + + adev->needs_reset = false; + + /* block TTM */ + resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); + + r = amdgpu_suspend(adev); + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_ring *ring = adev->rings[i]; + if (!ring) + continue; + + ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]); + if (ring_sizes[i]) { + saved = true; + dev_info(adev->dev, "Saved %d dwords of commands " + "on ring %d.\n", ring_sizes[i], i); + } + } + +retry: + r = amdgpu_asic_reset(adev); + if (!r) { + dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); + r = amdgpu_resume(adev); + } + + if (!r) { + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_ring *ring = adev->rings[i]; + if (!ring) + continue; + + amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]); + ring_sizes[i] = 0; + ring_data[i] = NULL; + } + + r = amdgpu_ib_ring_tests(adev); + if (r) { + dev_err(adev->dev, "ib ring test failed (%d).\n", r); + if (saved) { + saved = false; + r = amdgpu_suspend(adev); + goto retry; + } + } + } else { + amdgpu_fence_driver_force_completion(adev); + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + if (adev->rings[i]) + kfree(ring_data[i]); + } + } + + drm_helper_resume_force_mode(adev->ddev); + + ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); + if (r) { + /* bad news, how to tell it to userspace ? */ + dev_info(adev->dev, "GPU reset failed\n"); + } + + up_write(&adev->exclusive_lock); + return r; +} + + +/* + * Debugfs + */ +int amdgpu_debugfs_add_files(struct amdgpu_device *adev, + struct drm_info_list *files, + unsigned nfiles) +{ + unsigned i; + + for (i = 0; i < adev->debugfs_count; i++) { + if (adev->debugfs[i].files == files) { + /* Already registered */ + return 0; + } + } + + i = adev->debugfs_count + 1; + if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { + DRM_ERROR("Reached maximum number of debugfs components.\n"); + DRM_ERROR("Report so we increase " + "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); + return -EINVAL; + } + adev->debugfs[adev->debugfs_count].files = files; + adev->debugfs[adev->debugfs_count].num_files = nfiles; + adev->debugfs_count = i; +#if defined(CONFIG_DEBUG_FS) + drm_debugfs_create_files(files, nfiles, + adev->ddev->control->debugfs_root, + adev->ddev->control); + drm_debugfs_create_files(files, nfiles, + adev->ddev->primary->debugfs_root, + adev->ddev->primary); +#endif + return 0; +} + +static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + unsigned i; + + for (i = 0; i < adev->debugfs_count; i++) { + drm_debugfs_remove_files(adev->debugfs[i].files, + adev->debugfs[i].num_files, + adev->ddev->control); + drm_debugfs_remove_files(adev->debugfs[i].files, + adev->debugfs[i].num_files, + adev->ddev->primary); + } +#endif +} + +#if defined(CONFIG_DEBUG_FS) + +static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + if (*pos > adev->rmmio_size) + return result; + + value = RREG32(*pos >> 2); + r = put_user(value, (uint32_t *)buf); + if (r) + return r; + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + uint32_t value; + + if (*pos > adev->rmmio_size) + return result; + + r = get_user(value, (uint32_t *)buf); + if (r) + return r; + + WREG32(*pos >> 2, value); + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static const struct file_operations amdgpu_debugfs_regs_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_regs_read, + .write = amdgpu_debugfs_regs_write, + .llseek = default_llseek +}; + +static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) +{ + struct drm_minor *minor = adev->ddev->primary; + struct dentry *ent, *root = minor->debugfs_root; + + ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root, + adev, &amdgpu_debugfs_regs_fops); + if (IS_ERR(ent)) + return PTR_ERR(ent); + i_size_write(ent->d_inode, adev->rmmio_size); + adev->debugfs_regs = ent; + + return 0; +} + +static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) +{ + debugfs_remove(adev->debugfs_regs); + adev->debugfs_regs = NULL; +} + +int amdgpu_debugfs_init(struct drm_minor *minor) +{ + return 0; +} + +void amdgpu_debugfs_cleanup(struct drm_minor *minor) +{ +} +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c new file mode 100644 index 000000000000..f22c0671c3eb --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -0,0 +1,832 @@ +/* + * Copyright 2007-8 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + */ +#include +#include +#include "amdgpu.h" +#include "amdgpu_i2c.h" +#include "atom.h" +#include "amdgpu_connectors.h" +#include + +#include +#include +#include + + +static void amdgpu_flip_work_func(struct work_struct *__work) +{ + struct amdgpu_flip_work *work = + container_of(__work, struct amdgpu_flip_work, flip_work); + struct amdgpu_device *adev = work->adev; + struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; + + struct drm_crtc *crtc = &amdgpuCrtc->base; + struct amdgpu_fence *fence; + unsigned long flags; + int r; + + down_read(&adev->exclusive_lock); + if (work->fence) { + fence = to_amdgpu_fence(work->fence); + if (fence) { + r = amdgpu_fence_wait(fence, false); + if (r == -EDEADLK) { + up_read(&adev->exclusive_lock); + r = amdgpu_gpu_reset(adev); + down_read(&adev->exclusive_lock); + } + } else + r = fence_wait(work->fence, false); + + if (r) + DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); + + /* We continue with the page flip even if we failed to wait on + * the fence, otherwise the DRM core and userspace will be + * confused about which BO the CRTC is scanning out + */ + + fence_put(work->fence); + work->fence = NULL; + } + + /* We borrow the event spin lock for protecting flip_status */ + spin_lock_irqsave(&crtc->dev->event_lock, flags); + + /* set the proper interrupt */ + amdgpu_irq_get(adev, &adev->pageflip_irq, work->crtc_id); + /* do the flip (mmio) */ + adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base); + /* set the flip status */ + amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; + + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + up_read(&adev->exclusive_lock); +} + +/* + * Handle unpin events outside the interrupt handler proper. + */ +static void amdgpu_unpin_work_func(struct work_struct *__work) +{ + struct amdgpu_flip_work *work = + container_of(__work, struct amdgpu_flip_work, unpin_work); + int r; + + /* unpin of the old buffer */ + r = amdgpu_bo_reserve(work->old_rbo, false); + if (likely(r == 0)) { + r = amdgpu_bo_unpin(work->old_rbo); + if (unlikely(r != 0)) { + DRM_ERROR("failed to unpin buffer after flip\n"); + } + amdgpu_bo_unreserve(work->old_rbo); + } else + DRM_ERROR("failed to reserve buffer after flip\n"); + + drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); + kfree(work); +} + +int amdgpu_crtc_page_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t page_flip_flags) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_framebuffer *old_amdgpu_fb; + struct amdgpu_framebuffer *new_amdgpu_fb; + struct drm_gem_object *obj; + struct amdgpu_flip_work *work; + struct amdgpu_bo *new_rbo; + unsigned long flags; + u64 tiling_flags; + u64 base; + int r; + + work = kzalloc(sizeof *work, GFP_KERNEL); + if (work == NULL) + return -ENOMEM; + + INIT_WORK(&work->flip_work, amdgpu_flip_work_func); + INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func); + + work->event = event; + work->adev = adev; + work->crtc_id = amdgpu_crtc->crtc_id; + + /* schedule unpin of the old buffer */ + old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); + obj = old_amdgpu_fb->obj; + + /* take a reference to the old object */ + drm_gem_object_reference(obj); + work->old_rbo = gem_to_amdgpu_bo(obj); + + new_amdgpu_fb = to_amdgpu_framebuffer(fb); + obj = new_amdgpu_fb->obj; + new_rbo = gem_to_amdgpu_bo(obj); + + /* pin the new buffer */ + r = amdgpu_bo_reserve(new_rbo, false); + if (unlikely(r != 0)) { + DRM_ERROR("failed to reserve new rbo buffer before flip\n"); + goto cleanup; + } + + r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, &base); + if (unlikely(r != 0)) { + amdgpu_bo_unreserve(new_rbo); + r = -EINVAL; + DRM_ERROR("failed to pin new rbo buffer before flip\n"); + goto cleanup; + } + + work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); + amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags); + amdgpu_bo_unreserve(new_rbo); + + work->base = base; + + r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id); + if (r) { + DRM_ERROR("failed to get vblank before flip\n"); + goto pflip_cleanup; + } + + /* we borrow the event spin lock for protecting flip_wrok */ + spin_lock_irqsave(&crtc->dev->event_lock, flags); + if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { + DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + r = -EBUSY; + goto vblank_cleanup; + } + + amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; + amdgpu_crtc->pflip_works = work; + + /* update crtc fb */ + crtc->primary->fb = fb; + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + queue_work(amdgpu_crtc->pflip_queue, &work->flip_work); + return 0; + +vblank_cleanup: + drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id); + +pflip_cleanup: + if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) { + DRM_ERROR("failed to reserve new rbo in error path\n"); + goto cleanup; + } + if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) { + DRM_ERROR("failed to unpin new rbo in error path\n"); + } + amdgpu_bo_unreserve(new_rbo); + +cleanup: + drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); + fence_put(work->fence); + kfree(work); + + return r; +} + +int amdgpu_crtc_set_config(struct drm_mode_set *set) +{ + struct drm_device *dev; + struct amdgpu_device *adev; + struct drm_crtc *crtc; + bool active = false; + int ret; + + if (!set || !set->crtc) + return -EINVAL; + + dev = set->crtc->dev; + + ret = pm_runtime_get_sync(dev->dev); + if (ret < 0) + return ret; + + ret = drm_crtc_helper_set_config(set); + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) + if (crtc->enabled) + active = true; + + pm_runtime_mark_last_busy(dev->dev); + + adev = dev->dev_private; + /* if we have active crtcs and we don't have a power ref, + take the current one */ + if (active && !adev->have_disp_power_ref) { + adev->have_disp_power_ref = true; + return ret; + } + /* if we have no active crtcs, then drop the power ref + we got before */ + if (!active && adev->have_disp_power_ref) { + pm_runtime_put_autosuspend(dev->dev); + adev->have_disp_power_ref = false; + } + + /* drop the power reference we got coming in here */ + pm_runtime_put_autosuspend(dev->dev); + return ret; +} + +static const char *encoder_names[38] = { + "NONE", + "INTERNAL_LVDS", + "INTERNAL_TMDS1", + "INTERNAL_TMDS2", + "INTERNAL_DAC1", + "INTERNAL_DAC2", + "INTERNAL_SDVOA", + "INTERNAL_SDVOB", + "SI170B", + "CH7303", + "CH7301", + "INTERNAL_DVO1", + "EXTERNAL_SDVOA", + "EXTERNAL_SDVOB", + "TITFP513", + "INTERNAL_LVTM1", + "VT1623", + "HDMI_SI1930", + "HDMI_INTERNAL", + "INTERNAL_KLDSCP_TMDS1", + "INTERNAL_KLDSCP_DVO1", + "INTERNAL_KLDSCP_DAC1", + "INTERNAL_KLDSCP_DAC2", + "SI178", + "MVPU_FPGA", + "INTERNAL_DDI", + "VT1625", + "HDMI_SI1932", + "DP_AN9801", + "DP_DP501", + "INTERNAL_UNIPHY", + "INTERNAL_KLDSCP_LVTMA", + "INTERNAL_UNIPHY1", + "INTERNAL_UNIPHY2", + "NUTMEG", + "TRAVIS", + "INTERNAL_VCE", + "INTERNAL_UNIPHY3", +}; + +static const char *hpd_names[6] = { + "HPD1", + "HPD2", + "HPD3", + "HPD4", + "HPD5", + "HPD6", +}; + +void amdgpu_print_display_setup(struct drm_device *dev) +{ + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector; + struct drm_encoder *encoder; + struct amdgpu_encoder *amdgpu_encoder; + uint32_t devices; + int i = 0; + + DRM_INFO("AMDGPU Display Connectors\n"); + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + amdgpu_connector = to_amdgpu_connector(connector); + DRM_INFO("Connector %d:\n", i); + DRM_INFO(" %s\n", connector->name); + if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) + DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); + if (amdgpu_connector->ddc_bus) { + DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + amdgpu_connector->ddc_bus->rec.mask_clk_reg, + amdgpu_connector->ddc_bus->rec.mask_data_reg, + amdgpu_connector->ddc_bus->rec.a_clk_reg, + amdgpu_connector->ddc_bus->rec.a_data_reg, + amdgpu_connector->ddc_bus->rec.en_clk_reg, + amdgpu_connector->ddc_bus->rec.en_data_reg, + amdgpu_connector->ddc_bus->rec.y_clk_reg, + amdgpu_connector->ddc_bus->rec.y_data_reg); + if (amdgpu_connector->router.ddc_valid) + DRM_INFO(" DDC Router 0x%x/0x%x\n", + amdgpu_connector->router.ddc_mux_control_pin, + amdgpu_connector->router.ddc_mux_state); + if (amdgpu_connector->router.cd_valid) + DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", + amdgpu_connector->router.cd_mux_control_pin, + amdgpu_connector->router.cd_mux_state); + } else { + if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || + connector->connector_type == DRM_MODE_CONNECTOR_DVII || + connector->connector_type == DRM_MODE_CONNECTOR_DVID || + connector->connector_type == DRM_MODE_CONNECTOR_DVIA || + connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || + connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) + DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); + } + DRM_INFO(" Encoders:\n"); + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + amdgpu_encoder = to_amdgpu_encoder(encoder); + devices = amdgpu_encoder->devices & amdgpu_connector->devices; + if (devices) { + if (devices & ATOM_DEVICE_CRT1_SUPPORT) + DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + if (devices & ATOM_DEVICE_CRT2_SUPPORT) + DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + if (devices & ATOM_DEVICE_LCD1_SUPPORT) + DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + if (devices & ATOM_DEVICE_DFP1_SUPPORT) + DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + if (devices & ATOM_DEVICE_DFP2_SUPPORT) + DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + if (devices & ATOM_DEVICE_DFP3_SUPPORT) + DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + if (devices & ATOM_DEVICE_DFP4_SUPPORT) + DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + if (devices & ATOM_DEVICE_DFP5_SUPPORT) + DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + if (devices & ATOM_DEVICE_DFP6_SUPPORT) + DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + if (devices & ATOM_DEVICE_TV1_SUPPORT) + DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + if (devices & ATOM_DEVICE_CV_SUPPORT) + DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + } + } + i++; + } +} + +/** + * amdgpu_ddc_probe + * + */ +bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, + bool use_aux) +{ + u8 out = 0x0; + u8 buf[8]; + int ret; + struct i2c_msg msgs[] = { + { + .addr = DDC_ADDR, + .flags = 0, + .len = 1, + .buf = &out, + }, + { + .addr = DDC_ADDR, + .flags = I2C_M_RD, + .len = 8, + .buf = buf, + } + }; + + /* on hw with routers, select right port */ + if (amdgpu_connector->router.ddc_valid) + amdgpu_i2c_router_select_ddc_port(amdgpu_connector); + + if (use_aux) { + ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); + } else { + ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); + } + + if (ret != 2) + /* Couldn't find an accessible DDC on this connector */ + return false; + /* Probe also for valid EDID header + * EDID header starts with: + * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. + * Only the first 6 bytes must be valid as + * drm_edid_block_valid() can fix the last 2 bytes */ + if (drm_edid_header_is_valid(buf) < 6) { + /* Couldn't find an accessible EDID on this + * connector */ + return false; + } + return true; +} + +static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb) +{ + struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); + + if (amdgpu_fb->obj) { + drm_gem_object_unreference_unlocked(amdgpu_fb->obj); + } + drm_framebuffer_cleanup(fb); + kfree(amdgpu_fb); +} + +static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb, + struct drm_file *file_priv, + unsigned int *handle) +{ + struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); + + return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle); +} + +static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { + .destroy = amdgpu_user_framebuffer_destroy, + .create_handle = amdgpu_user_framebuffer_create_handle, +}; + +int +amdgpu_framebuffer_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj) +{ + int ret; + rfb->obj = obj; + drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); + ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); + if (ret) { + rfb->obj = NULL; + return ret; + } + return 0; +} + +static struct drm_framebuffer * +amdgpu_user_framebuffer_create(struct drm_device *dev, + struct drm_file *file_priv, + struct drm_mode_fb_cmd2 *mode_cmd) +{ + struct drm_gem_object *obj; + struct amdgpu_framebuffer *amdgpu_fb; + int ret; + + obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); + if (obj == NULL) { + dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " + "can't create framebuffer\n", mode_cmd->handles[0]); + return ERR_PTR(-ENOENT); + } + + amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); + if (amdgpu_fb == NULL) { + drm_gem_object_unreference_unlocked(obj); + return ERR_PTR(-ENOMEM); + } + + ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); + if (ret) { + kfree(amdgpu_fb); + drm_gem_object_unreference_unlocked(obj); + return ERR_PTR(ret); + } + + return &amdgpu_fb->base; +} + +static void amdgpu_output_poll_changed(struct drm_device *dev) +{ + struct amdgpu_device *adev = dev->dev_private; + amdgpu_fb_output_poll_changed(adev); +} + +const struct drm_mode_config_funcs amdgpu_mode_funcs = { + .fb_create = amdgpu_user_framebuffer_create, + .output_poll_changed = amdgpu_output_poll_changed +}; + +static struct drm_prop_enum_list amdgpu_underscan_enum_list[] = +{ { UNDERSCAN_OFF, "off" }, + { UNDERSCAN_ON, "on" }, + { UNDERSCAN_AUTO, "auto" }, +}; + +static struct drm_prop_enum_list amdgpu_audio_enum_list[] = +{ { AMDGPU_AUDIO_DISABLE, "off" }, + { AMDGPU_AUDIO_ENABLE, "on" }, + { AMDGPU_AUDIO_AUTO, "auto" }, +}; + +/* XXX support different dither options? spatial, temporal, both, etc. */ +static struct drm_prop_enum_list amdgpu_dither_enum_list[] = +{ { AMDGPU_FMT_DITHER_DISABLE, "off" }, + { AMDGPU_FMT_DITHER_ENABLE, "on" }, +}; + +int amdgpu_modeset_create_props(struct amdgpu_device *adev) +{ + int sz; + + if (adev->is_atom_bios) { + adev->mode_info.coherent_mode_property = + drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); + if (!adev->mode_info.coherent_mode_property) + return -ENOMEM; + } + + adev->mode_info.load_detect_property = + drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); + if (!adev->mode_info.load_detect_property) + return -ENOMEM; + + drm_mode_create_scaling_mode_property(adev->ddev); + + sz = ARRAY_SIZE(amdgpu_underscan_enum_list); + adev->mode_info.underscan_property = + drm_property_create_enum(adev->ddev, 0, + "underscan", + amdgpu_underscan_enum_list, sz); + + adev->mode_info.underscan_hborder_property = + drm_property_create_range(adev->ddev, 0, + "underscan hborder", 0, 128); + if (!adev->mode_info.underscan_hborder_property) + return -ENOMEM; + + adev->mode_info.underscan_vborder_property = + drm_property_create_range(adev->ddev, 0, + "underscan vborder", 0, 128); + if (!adev->mode_info.underscan_vborder_property) + return -ENOMEM; + + sz = ARRAY_SIZE(amdgpu_audio_enum_list); + adev->mode_info.audio_property = + drm_property_create_enum(adev->ddev, 0, + "audio", + amdgpu_audio_enum_list, sz); + + sz = ARRAY_SIZE(amdgpu_dither_enum_list); + adev->mode_info.dither_property = + drm_property_create_enum(adev->ddev, 0, + "dither", + amdgpu_dither_enum_list, sz); + + return 0; +} + +void amdgpu_update_display_priority(struct amdgpu_device *adev) +{ + /* adjustment options for the display watermarks */ + if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) + adev->mode_info.disp_priority = 0; + else + adev->mode_info.disp_priority = amdgpu_disp_priority; + +} + +static bool is_hdtv_mode(const struct drm_display_mode *mode) +{ + /* try and guess if this is a tv or a monitor */ + if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ + (mode->vdisplay == 576) || /* 576p */ + (mode->vdisplay == 720) || /* 720p */ + (mode->vdisplay == 1080)) /* 1080p */ + return true; + else + return false; +} + +bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct drm_device *dev = crtc->dev; + struct drm_encoder *encoder; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_encoder *amdgpu_encoder; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector; + u32 src_v = 1, dst_v = 1; + u32 src_h = 1, dst_h = 1; + + amdgpu_crtc->h_border = 0; + amdgpu_crtc->v_border = 0; + + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc != crtc) + continue; + amdgpu_encoder = to_amdgpu_encoder(encoder); + connector = amdgpu_get_connector_for_encoder(encoder); + amdgpu_connector = to_amdgpu_connector(connector); + + /* set scaling */ + if (amdgpu_encoder->rmx_type == RMX_OFF) + amdgpu_crtc->rmx_type = RMX_OFF; + else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || + mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) + amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; + else + amdgpu_crtc->rmx_type = RMX_OFF; + /* copy native mode */ + memcpy(&amdgpu_crtc->native_mode, + &amdgpu_encoder->native_mode, + sizeof(struct drm_display_mode)); + src_v = crtc->mode.vdisplay; + dst_v = amdgpu_crtc->native_mode.vdisplay; + src_h = crtc->mode.hdisplay; + dst_h = amdgpu_crtc->native_mode.hdisplay; + + /* fix up for overscan on hdmi */ + if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && + ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || + ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && + drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && + is_hdtv_mode(mode)))) { + if (amdgpu_encoder->underscan_hborder != 0) + amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; + else + amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; + if (amdgpu_encoder->underscan_vborder != 0) + amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; + else + amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; + amdgpu_crtc->rmx_type = RMX_FULL; + src_v = crtc->mode.vdisplay; + dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); + src_h = crtc->mode.hdisplay; + dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); + } + } + if (amdgpu_crtc->rmx_type != RMX_OFF) { + fixed20_12 a, b; + a.full = dfixed_const(src_v); + b.full = dfixed_const(dst_v); + amdgpu_crtc->vsc.full = dfixed_div(a, b); + a.full = dfixed_const(src_h); + b.full = dfixed_const(dst_h); + amdgpu_crtc->hsc.full = dfixed_div(a, b); + } else { + amdgpu_crtc->vsc.full = dfixed_const(1); + amdgpu_crtc->hsc.full = dfixed_const(1); + } + return true; +} + +/* + * Retrieve current video scanout position of crtc on a given gpu, and + * an optional accurate timestamp of when query happened. + * + * \param dev Device to query. + * \param crtc Crtc to query. + * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). + * \param *vpos Location where vertical scanout position should be stored. + * \param *hpos Location where horizontal scanout position should go. + * \param *stime Target location for timestamp taken immediately before + * scanout position query. Can be NULL to skip timestamp. + * \param *etime Target location for timestamp taken immediately after + * scanout position query. Can be NULL to skip timestamp. + * + * Returns vpos as a positive number while in active scanout area. + * Returns vpos as a negative number inside vblank, counting the number + * of scanlines to go until end of vblank, e.g., -1 means "one scanline + * until start of active scanout / end of vblank." + * + * \return Flags, or'ed together as follows: + * + * DRM_SCANOUTPOS_VALID = Query successful. + * DRM_SCANOUTPOS_INVBL = Inside vblank. + * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of + * this flag means that returned position may be offset by a constant but + * unknown small number of scanlines wrt. real scanout position. + * + */ +int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags, + int *vpos, int *hpos, ktime_t *stime, ktime_t *etime) +{ + u32 vbl = 0, position = 0; + int vbl_start, vbl_end, vtotal, ret = 0; + bool in_vbl = true; + + struct amdgpu_device *adev = dev->dev_private; + + /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ + + /* Get optional system timestamp before query. */ + if (stime) + *stime = ktime_get(); + + if (amdgpu_display_page_flip_get_scanoutpos(adev, crtc, &vbl, &position) == 0) + ret |= DRM_SCANOUTPOS_VALID; + + /* Get optional system timestamp after query. */ + if (etime) + *etime = ktime_get(); + + /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ + + /* Decode into vertical and horizontal scanout position. */ + *vpos = position & 0x1fff; + *hpos = (position >> 16) & 0x1fff; + + /* Valid vblank area boundaries from gpu retrieved? */ + if (vbl > 0) { + /* Yes: Decode. */ + ret |= DRM_SCANOUTPOS_ACCURATE; + vbl_start = vbl & 0x1fff; + vbl_end = (vbl >> 16) & 0x1fff; + } + else { + /* No: Fake something reasonable which gives at least ok results. */ + vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; + vbl_end = 0; + } + + /* Test scanout position against vblank region. */ + if ((*vpos < vbl_start) && (*vpos >= vbl_end)) + in_vbl = false; + + /* Check if inside vblank area and apply corrective offsets: + * vpos will then be >=0 in video scanout area, but negative + * within vblank area, counting down the number of lines until + * start of scanout. + */ + + /* Inside "upper part" of vblank area? Apply corrective offset if so: */ + if (in_vbl && (*vpos >= vbl_start)) { + vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; + *vpos = *vpos - vtotal; + } + + /* Correct for shifted end of vbl at vbl_end. */ + *vpos = *vpos - vbl_end; + + /* In vblank? */ + if (in_vbl) + ret |= DRM_SCANOUTPOS_IN_VBLANK; + + /* Is vpos outside nominal vblank area, but less than + * 1/100 of a frame height away from start of vblank? + * If so, assume this isn't a massively delayed vblank + * interrupt, but a vblank interrupt that fired a few + * microseconds before true start of vblank. Compensate + * by adding a full frame duration to the final timestamp. + * Happens, e.g., on ATI R500, R600. + * + * We only do this if DRM_CALLED_FROM_VBLIRQ. + */ + if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) { + vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay; + vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal; + + if (vbl_start - *vpos < vtotal / 100) { + *vpos -= vtotal; + + /* Signal this correction as "applied". */ + ret |= 0x8; + } + } + + return ret; +} + +int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) +{ + if (crtc < 0 || crtc >= adev->mode_info.num_crtc) + return AMDGPU_CRTC_IRQ_NONE; + + switch (crtc) { + case 0: + return AMDGPU_CRTC_IRQ_VBLANK1; + case 1: + return AMDGPU_CRTC_IRQ_VBLANK2; + case 2: + return AMDGPU_CRTC_IRQ_VBLANK3; + case 3: + return AMDGPU_CRTC_IRQ_VBLANK4; + case 4: + return AMDGPU_CRTC_IRQ_VBLANK5; + case 5: + return AMDGPU_CRTC_IRQ_VBLANK6; + default: + return AMDGPU_CRTC_IRQ_NONE; + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c new file mode 100644 index 000000000000..7b7f4aba60c0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -0,0 +1,955 @@ +/* + * Copyright 2011 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ + +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_atombios.h" +#include "amdgpu_i2c.h" +#include "amdgpu_dpm.h" +#include "atom.h" + +void amdgpu_dpm_print_class_info(u32 class, u32 class2) +{ + printk("\tui class: "); + switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { + case ATOM_PPLIB_CLASSIFICATION_UI_NONE: + default: + printk("none\n"); + break; + case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: + printk("battery\n"); + break; + case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: + printk("balanced\n"); + break; + case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: + printk("performance\n"); + break; + } + printk("\tinternal class: "); + if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) && + (class2 == 0)) + printk("none"); + else { + if (class & ATOM_PPLIB_CLASSIFICATION_BOOT) + printk("boot "); + if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL) + printk("thermal "); + if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) + printk("limited_pwr "); + if (class & ATOM_PPLIB_CLASSIFICATION_REST) + printk("rest "); + if (class & ATOM_PPLIB_CLASSIFICATION_FORCED) + printk("forced "); + if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) + printk("3d_perf "); + if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE) + printk("ovrdrv "); + if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) + printk("uvd "); + if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW) + printk("3d_low "); + if (class & ATOM_PPLIB_CLASSIFICATION_ACPI) + printk("acpi "); + if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) + printk("uvd_hd2 "); + if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) + printk("uvd_hd "); + if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) + printk("uvd_sd "); + if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) + printk("limited_pwr2 "); + if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) + printk("ulv "); + if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) + printk("uvd_mvc "); + } + printk("\n"); +} + +void amdgpu_dpm_print_cap_info(u32 caps) +{ + printk("\tcaps: "); + if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) + printk("single_disp "); + if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK) + printk("video "); + if (caps & ATOM_PPLIB_DISALLOW_ON_DC) + printk("no_dc "); + printk("\n"); +} + +void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, + struct amdgpu_ps *rps) +{ + printk("\tstatus: "); + if (rps == adev->pm.dpm.current_ps) + printk("c "); + if (rps == adev->pm.dpm.requested_ps) + printk("r "); + if (rps == adev->pm.dpm.boot_ps) + printk("b "); + printk("\n"); +} + +u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev) +{ + struct drm_device *dev = adev->ddev; + struct drm_crtc *crtc; + struct amdgpu_crtc *amdgpu_crtc; + u32 line_time_us, vblank_lines; + u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */ + + if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + amdgpu_crtc = to_amdgpu_crtc(crtc); + if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) { + line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) / + amdgpu_crtc->hw_mode.clock; + vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end - + amdgpu_crtc->hw_mode.crtc_vdisplay + + (amdgpu_crtc->v_border * 2); + vblank_time_us = vblank_lines * line_time_us; + break; + } + } + } + + return vblank_time_us; +} + +u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev) +{ + struct drm_device *dev = adev->ddev; + struct drm_crtc *crtc; + struct amdgpu_crtc *amdgpu_crtc; + u32 vrefresh = 0; + + if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + amdgpu_crtc = to_amdgpu_crtc(crtc); + if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) { + vrefresh = amdgpu_crtc->hw_mode.vrefresh; + break; + } + } + } + + return vrefresh; +} + +void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, + u32 *p, u32 *u) +{ + u32 b_c = 0; + u32 i_c; + u32 tmp; + + i_c = (i * r_c) / 100; + tmp = i_c >> p_b; + + while (tmp) { + b_c++; + tmp >>= 1; + } + + *u = (b_c + 1) / 2; + *p = i_c / (1 << (2 * (*u))); +} + +int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th) +{ + u32 k, a, ah, al; + u32 t1; + + if ((fl == 0) || (fh == 0) || (fl > fh)) + return -EINVAL; + + k = (100 * fh) / fl; + t1 = (t * (k - 100)); + a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100)); + a = (a + 5) / 10; + ah = ((a * t) + 5000) / 10000; + al = a - ah; + + *th = t - ah; + *tl = t + al; + + return 0; +} + +bool amdgpu_is_uvd_state(u32 class, u32 class2) +{ + if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) + return true; + if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) + return true; + if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) + return true; + if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) + return true; + if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) + return true; + return false; +} + +bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor) +{ + switch (sensor) { + case THERMAL_TYPE_RV6XX: + case THERMAL_TYPE_RV770: + case THERMAL_TYPE_EVERGREEN: + case THERMAL_TYPE_SUMO: + case THERMAL_TYPE_NI: + case THERMAL_TYPE_SI: + case THERMAL_TYPE_CI: + case THERMAL_TYPE_KV: + return true; + case THERMAL_TYPE_ADT7473_WITH_INTERNAL: + case THERMAL_TYPE_EMC2103_WITH_INTERNAL: + return false; /* need special handling */ + case THERMAL_TYPE_NONE: + case THERMAL_TYPE_EXTERNAL: + case THERMAL_TYPE_EXTERNAL_GPIO: + default: + return false; + } +} + +union power_info { + struct _ATOM_POWERPLAY_INFO info; + struct _ATOM_POWERPLAY_INFO_V2 info_2; + struct _ATOM_POWERPLAY_INFO_V3 info_3; + struct _ATOM_PPLIB_POWERPLAYTABLE pplib; + struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; + struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; + struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4; + struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5; +}; + +union fan_info { + struct _ATOM_PPLIB_FANTABLE fan; + struct _ATOM_PPLIB_FANTABLE2 fan2; + struct _ATOM_PPLIB_FANTABLE3 fan3; +}; + +static int amdgpu_parse_clk_voltage_dep_table(struct amdgpu_clock_voltage_dependency_table *amdgpu_table, + ATOM_PPLIB_Clock_Voltage_Dependency_Table *atom_table) +{ + u32 size = atom_table->ucNumEntries * + sizeof(struct amdgpu_clock_voltage_dependency_entry); + int i; + ATOM_PPLIB_Clock_Voltage_Dependency_Record *entry; + + amdgpu_table->entries = kzalloc(size, GFP_KERNEL); + if (!amdgpu_table->entries) + return -ENOMEM; + + entry = &atom_table->entries[0]; + for (i = 0; i < atom_table->ucNumEntries; i++) { + amdgpu_table->entries[i].clk = le16_to_cpu(entry->usClockLow) | + (entry->ucClockHigh << 16); + amdgpu_table->entries[i].v = le16_to_cpu(entry->usVoltage); + entry = (ATOM_PPLIB_Clock_Voltage_Dependency_Record *) + ((u8 *)entry + sizeof(ATOM_PPLIB_Clock_Voltage_Dependency_Record)); + } + amdgpu_table->count = atom_table->ucNumEntries; + + return 0; +} + +int amdgpu_get_platform_caps(struct amdgpu_device *adev) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + union power_info *power_info; + int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); + u16 data_offset; + u8 frev, crev; + + if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) + return -EINVAL; + power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); + + adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); + adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); + adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); + + return 0; +} + +/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */ +#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12 +#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14 +#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16 +#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18 +#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20 +#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22 +#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8 24 +#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V9 26 + +int amdgpu_parse_extended_power_table(struct amdgpu_device *adev) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + union power_info *power_info; + union fan_info *fan_info; + ATOM_PPLIB_Clock_Voltage_Dependency_Table *dep_table; + int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); + u16 data_offset; + u8 frev, crev; + int ret, i; + + if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) + return -EINVAL; + power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); + + /* fan table */ + if (le16_to_cpu(power_info->pplib.usTableSize) >= + sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) { + if (power_info->pplib3.usFanTableOffset) { + fan_info = (union fan_info *)(mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib3.usFanTableOffset)); + adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; + adev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); + adev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed); + adev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh); + adev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin); + adev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed); + adev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh); + if (fan_info->fan.ucFanTableFormat >= 2) + adev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax); + else + adev->pm.dpm.fan.t_max = 10900; + adev->pm.dpm.fan.cycle_delay = 100000; + if (fan_info->fan.ucFanTableFormat >= 3) { + adev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode; + adev->pm.dpm.fan.default_max_fan_pwm = + le16_to_cpu(fan_info->fan3.usFanPWMMax); + adev->pm.dpm.fan.default_fan_output_sensitivity = 4836; + adev->pm.dpm.fan.fan_output_sensitivity = + le16_to_cpu(fan_info->fan3.usFanOutputSensitivity); + } + adev->pm.dpm.fan.ucode_fan_control = true; + } + } + + /* clock dependancy tables, shedding tables */ + if (le16_to_cpu(power_info->pplib.usTableSize) >= + sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE4)) { + if (power_info->pplib4.usVddcDependencyOnSCLKOffset) { + dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, + dep_table); + if (ret) { + amdgpu_free_extended_power_table(adev); + return ret; + } + } + if (power_info->pplib4.usVddciDependencyOnMCLKOffset) { + dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, + dep_table); + if (ret) { + amdgpu_free_extended_power_table(adev); + return ret; + } + } + if (power_info->pplib4.usVddcDependencyOnMCLKOffset) { + dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, + dep_table); + if (ret) { + amdgpu_free_extended_power_table(adev); + return ret; + } + } + if (power_info->pplib4.usMvddDependencyOnMCLKOffset) { + dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset)); + ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, + dep_table); + if (ret) { + amdgpu_free_extended_power_table(adev); + return ret; + } + } + if (power_info->pplib4.usMaxClockVoltageOnDCOffset) { + ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v = + (ATOM_PPLIB_Clock_Voltage_Limit_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib4.usMaxClockVoltageOnDCOffset)); + if (clk_v->ucNumEntries) { + adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = + le16_to_cpu(clk_v->entries[0].usSclkLow) | + (clk_v->entries[0].ucSclkHigh << 16); + adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = + le16_to_cpu(clk_v->entries[0].usMclkLow) | + (clk_v->entries[0].ucMclkHigh << 16); + adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = + le16_to_cpu(clk_v->entries[0].usVddc); + adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = + le16_to_cpu(clk_v->entries[0].usVddci); + } + } + if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) { + ATOM_PPLIB_PhaseSheddingLimits_Table *psl = + (ATOM_PPLIB_PhaseSheddingLimits_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset)); + ATOM_PPLIB_PhaseSheddingLimits_Record *entry; + + adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = + kzalloc(psl->ucNumEntries * + sizeof(struct amdgpu_phase_shedding_limits_entry), + GFP_KERNEL); + if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { + amdgpu_free_extended_power_table(adev); + return -ENOMEM; + } + + entry = &psl->entries[0]; + for (i = 0; i < psl->ucNumEntries; i++) { + adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = + le16_to_cpu(entry->usSclkLow) | (entry->ucSclkHigh << 16); + adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk = + le16_to_cpu(entry->usMclkLow) | (entry->ucMclkHigh << 16); + adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage = + le16_to_cpu(entry->usVoltage); + entry = (ATOM_PPLIB_PhaseSheddingLimits_Record *) + ((u8 *)entry + sizeof(ATOM_PPLIB_PhaseSheddingLimits_Record)); + } + adev->pm.dpm.dyn_state.phase_shedding_limits_table.count = + psl->ucNumEntries; + } + } + + /* cac data */ + if (le16_to_cpu(power_info->pplib.usTableSize) >= + sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5)) { + adev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit); + adev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit); + adev->pm.dpm.near_tdp_limit_adjusted = adev->pm.dpm.near_tdp_limit; + adev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit); + if (adev->pm.dpm.tdp_od_limit) + adev->pm.dpm.power_control = true; + else + adev->pm.dpm.power_control = false; + adev->pm.dpm.tdp_adjustment = 0; + adev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold); + adev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage); + adev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope); + if (power_info->pplib5.usCACLeakageTableOffset) { + ATOM_PPLIB_CAC_Leakage_Table *cac_table = + (ATOM_PPLIB_CAC_Leakage_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib5.usCACLeakageTableOffset)); + ATOM_PPLIB_CAC_Leakage_Record *entry; + u32 size = cac_table->ucNumEntries * sizeof(struct amdgpu_cac_leakage_table); + adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); + if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) { + amdgpu_free_extended_power_table(adev); + return -ENOMEM; + } + entry = &cac_table->entries[0]; + for (i = 0; i < cac_table->ucNumEntries; i++) { + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { + adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 = + le16_to_cpu(entry->usVddc1); + adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 = + le16_to_cpu(entry->usVddc2); + adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 = + le16_to_cpu(entry->usVddc3); + } else { + adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc = + le16_to_cpu(entry->usVddc); + adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage = + le32_to_cpu(entry->ulLeakageValue); + } + entry = (ATOM_PPLIB_CAC_Leakage_Record *) + ((u8 *)entry + sizeof(ATOM_PPLIB_CAC_Leakage_Record)); + } + adev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries; + } + } + + /* ext tables */ + if (le16_to_cpu(power_info->pplib.usTableSize) >= + sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) { + ATOM_PPLIB_EXTENDEDHEADER *ext_hdr = (ATOM_PPLIB_EXTENDEDHEADER *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib3.usExtendendedHeaderOffset)); + if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2) && + ext_hdr->usVCETableOffset) { + VCEClockInfoArray *array = (VCEClockInfoArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usVCETableOffset) + 1); + ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits = + (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usVCETableOffset) + 1 + + 1 + array->ucNumEntries * sizeof(VCEClockInfo)); + ATOM_PPLIB_VCE_State_Table *states = + (ATOM_PPLIB_VCE_State_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usVCETableOffset) + 1 + + 1 + (array->ucNumEntries * sizeof (VCEClockInfo)) + + 1 + (limits->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record))); + ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *entry; + ATOM_PPLIB_VCE_State_Record *state_entry; + VCEClockInfo *vce_clk; + u32 size = limits->numEntries * + sizeof(struct amdgpu_vce_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); + if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { + amdgpu_free_extended_power_table(adev); + return -ENOMEM; + } + adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; + state_entry = &states->entries[0]; + for (i = 0; i < limits->numEntries; i++) { + vce_clk = (VCEClockInfo *) + ((u8 *)&array->entries[0] + + (entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo))); + adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = + le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16); + adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = + le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16); + adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v = + le16_to_cpu(entry->usVoltage); + entry = (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record *) + ((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record)); + } + for (i = 0; i < states->numEntries; i++) { + if (i >= AMDGPU_MAX_VCE_LEVELS) + break; + vce_clk = (VCEClockInfo *) + ((u8 *)&array->entries[0] + + (state_entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo))); + adev->pm.dpm.vce_states[i].evclk = + le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16); + adev->pm.dpm.vce_states[i].ecclk = + le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16); + adev->pm.dpm.vce_states[i].clk_idx = + state_entry->ucClockInfoIndex & 0x3f; + adev->pm.dpm.vce_states[i].pstate = + (state_entry->ucClockInfoIndex & 0xc0) >> 6; + state_entry = (ATOM_PPLIB_VCE_State_Record *) + ((u8 *)state_entry + sizeof(ATOM_PPLIB_VCE_State_Record)); + } + } + if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3) && + ext_hdr->usUVDTableOffset) { + UVDClockInfoArray *array = (UVDClockInfoArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usUVDTableOffset) + 1); + ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *limits = + (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usUVDTableOffset) + 1 + + 1 + (array->ucNumEntries * sizeof (UVDClockInfo))); + ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *entry; + u32 size = limits->numEntries * + sizeof(struct amdgpu_uvd_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); + if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { + amdgpu_free_extended_power_table(adev); + return -ENOMEM; + } + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; + for (i = 0; i < limits->numEntries; i++) { + UVDClockInfo *uvd_clk = (UVDClockInfo *) + ((u8 *)&array->entries[0] + + (entry->ucUVDClockInfoIndex * sizeof(UVDClockInfo))); + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = + le16_to_cpu(uvd_clk->usVClkLow) | (uvd_clk->ucVClkHigh << 16); + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = + le16_to_cpu(uvd_clk->usDClkLow) | (uvd_clk->ucDClkHigh << 16); + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = + le16_to_cpu(entry->usVoltage); + entry = (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *) + ((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record)); + } + } + if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4) && + ext_hdr->usSAMUTableOffset) { + ATOM_PPLIB_SAMClk_Voltage_Limit_Table *limits = + (ATOM_PPLIB_SAMClk_Voltage_Limit_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usSAMUTableOffset) + 1); + ATOM_PPLIB_SAMClk_Voltage_Limit_Record *entry; + u32 size = limits->numEntries * + sizeof(struct amdgpu_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); + if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { + amdgpu_free_extended_power_table(adev); + return -ENOMEM; + } + adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; + for (i = 0; i < limits->numEntries; i++) { + adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk = + le16_to_cpu(entry->usSAMClockLow) | (entry->ucSAMClockHigh << 16); + adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v = + le16_to_cpu(entry->usVoltage); + entry = (ATOM_PPLIB_SAMClk_Voltage_Limit_Record *) + ((u8 *)entry + sizeof(ATOM_PPLIB_SAMClk_Voltage_Limit_Record)); + } + } + if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) && + ext_hdr->usPPMTableOffset) { + ATOM_PPLIB_PPM_Table *ppm = (ATOM_PPLIB_PPM_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usPPMTableOffset)); + adev->pm.dpm.dyn_state.ppm_table = + kzalloc(sizeof(struct amdgpu_ppm_table), GFP_KERNEL); + if (!adev->pm.dpm.dyn_state.ppm_table) { + amdgpu_free_extended_power_table(adev); + return -ENOMEM; + } + adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; + adev->pm.dpm.dyn_state.ppm_table->cpu_core_number = + le16_to_cpu(ppm->usCpuCoreNumber); + adev->pm.dpm.dyn_state.ppm_table->platform_tdp = + le32_to_cpu(ppm->ulPlatformTDP); + adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp = + le32_to_cpu(ppm->ulSmallACPlatformTDP); + adev->pm.dpm.dyn_state.ppm_table->platform_tdc = + le32_to_cpu(ppm->ulPlatformTDC); + adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc = + le32_to_cpu(ppm->ulSmallACPlatformTDC); + adev->pm.dpm.dyn_state.ppm_table->apu_tdp = + le32_to_cpu(ppm->ulApuTDP); + adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = + le32_to_cpu(ppm->ulDGpuTDP); + adev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power = + le32_to_cpu(ppm->ulDGpuUlvPower); + adev->pm.dpm.dyn_state.ppm_table->tj_max = + le32_to_cpu(ppm->ulTjmax); + } + if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6) && + ext_hdr->usACPTableOffset) { + ATOM_PPLIB_ACPClk_Voltage_Limit_Table *limits = + (ATOM_PPLIB_ACPClk_Voltage_Limit_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usACPTableOffset) + 1); + ATOM_PPLIB_ACPClk_Voltage_Limit_Record *entry; + u32 size = limits->numEntries * + sizeof(struct amdgpu_clock_voltage_dependency_entry); + adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = + kzalloc(size, GFP_KERNEL); + if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { + amdgpu_free_extended_power_table(adev); + return -ENOMEM; + } + adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = + limits->numEntries; + entry = &limits->entries[0]; + for (i = 0; i < limits->numEntries; i++) { + adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk = + le16_to_cpu(entry->usACPClockLow) | (entry->ucACPClockHigh << 16); + adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v = + le16_to_cpu(entry->usVoltage); + entry = (ATOM_PPLIB_ACPClk_Voltage_Limit_Record *) + ((u8 *)entry + sizeof(ATOM_PPLIB_ACPClk_Voltage_Limit_Record)); + } + } + if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7) && + ext_hdr->usPowerTuneTableOffset) { + u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); + ATOM_PowerTune_Table *pt; + adev->pm.dpm.dyn_state.cac_tdp_table = + kzalloc(sizeof(struct amdgpu_cac_tdp_table), GFP_KERNEL); + if (!adev->pm.dpm.dyn_state.cac_tdp_table) { + amdgpu_free_extended_power_table(adev); + return -ENOMEM; + } + if (rev > 0) { + ATOM_PPLIB_POWERTUNE_Table_V1 *ppt = (ATOM_PPLIB_POWERTUNE_Table_V1 *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); + adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = + ppt->usMaximumPowerDeliveryLimit; + pt = &ppt->power_tune_table; + } else { + ATOM_PPLIB_POWERTUNE_Table *ppt = (ATOM_PPLIB_POWERTUNE_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); + adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255; + pt = &ppt->power_tune_table; + } + adev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP); + adev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp = + le16_to_cpu(pt->usConfigurableTDP); + adev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC); + adev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit = + le16_to_cpu(pt->usBatteryPowerLimit); + adev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit = + le16_to_cpu(pt->usSmallPowerLimit); + adev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage = + le16_to_cpu(pt->usLowCACLeakage); + adev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage = + le16_to_cpu(pt->usHighCACLeakage); + } + if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8) && + ext_hdr->usSclkVddgfxTableOffset) { + dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(ext_hdr->usSclkVddgfxTableOffset)); + ret = amdgpu_parse_clk_voltage_dep_table( + &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk, + dep_table); + if (ret) { + kfree(adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk.entries); + return ret; + } + } + } + + return 0; +} + +void amdgpu_free_extended_power_table(struct amdgpu_device *adev) +{ + struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state; + + kfree(dyn_state->vddc_dependency_on_sclk.entries); + kfree(dyn_state->vddci_dependency_on_mclk.entries); + kfree(dyn_state->vddc_dependency_on_mclk.entries); + kfree(dyn_state->mvdd_dependency_on_mclk.entries); + kfree(dyn_state->cac_leakage_table.entries); + kfree(dyn_state->phase_shedding_limits_table.entries); + kfree(dyn_state->ppm_table); + kfree(dyn_state->cac_tdp_table); + kfree(dyn_state->vce_clock_voltage_dependency_table.entries); + kfree(dyn_state->uvd_clock_voltage_dependency_table.entries); + kfree(dyn_state->samu_clock_voltage_dependency_table.entries); + kfree(dyn_state->acp_clock_voltage_dependency_table.entries); + kfree(dyn_state->vddgfx_dependency_on_sclk.entries); +} + +static const char *pp_lib_thermal_controller_names[] = { + "NONE", + "lm63", + "adm1032", + "adm1030", + "max6649", + "lm64", + "f75375", + "RV6xx", + "RV770", + "adt7473", + "NONE", + "External GPIO", + "Evergreen", + "emc2103", + "Sumo", + "Northern Islands", + "Southern Islands", + "lm96163", + "Sea Islands", + "Kaveri/Kabini", +}; + +void amdgpu_add_thermal_controller(struct amdgpu_device *adev) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + ATOM_PPLIB_POWERPLAYTABLE *power_table; + int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); + ATOM_PPLIB_THERMALCONTROLLER *controller; + struct amdgpu_i2c_bus_rec i2c_bus; + u16 data_offset; + u8 frev, crev; + + if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) + return; + power_table = (ATOM_PPLIB_POWERPLAYTABLE *) + (mode_info->atom_context->bios + data_offset); + controller = &power_table->sThermalController; + + /* add the i2c bus for thermal/fan chip */ + if (controller->ucType > 0) { + if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) + adev->pm.no_fan = true; + adev->pm.fan_pulses_per_revolution = + controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; + if (adev->pm.fan_pulses_per_revolution) { + adev->pm.fan_min_rpm = controller->ucFanMinRPM; + adev->pm.fan_max_rpm = controller->ucFanMaxRPM; + } + if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { + DRM_INFO("Internal thermal controller %s fan control\n", + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; + } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { + DRM_INFO("Internal thermal controller %s fan control\n", + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_RV770; + } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { + DRM_INFO("Internal thermal controller %s fan control\n", + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; + } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { + DRM_INFO("Internal thermal controller %s fan control\n", + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_SUMO; + } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { + DRM_INFO("Internal thermal controller %s fan control\n", + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_NI; + } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { + DRM_INFO("Internal thermal controller %s fan control\n", + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_SI; + } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { + DRM_INFO("Internal thermal controller %s fan control\n", + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_CI; + } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { + DRM_INFO("Internal thermal controller %s fan control\n", + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_KV; + } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) { + DRM_INFO("External GPIO thermal controller %s fan control\n", + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; + } else if (controller->ucType == + ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) { + DRM_INFO("ADT7473 with internal thermal controller %s fan control\n", + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; + } else if (controller->ucType == + ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) { + DRM_INFO("EMC2103 with internal thermal controller %s fan control\n", + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; + } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { + DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", + pp_lib_thermal_controller_names[controller->ucType], + controller->ucI2cAddress >> 1, + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; + i2c_bus = amdgpu_atombios_lookup_i2c_gpio(adev, controller->ucI2cLine); + adev->pm.i2c_bus = amdgpu_i2c_lookup(adev, &i2c_bus); + if (adev->pm.i2c_bus) { + struct i2c_board_info info = { }; + const char *name = pp_lib_thermal_controller_names[controller->ucType]; + info.addr = controller->ucI2cAddress >> 1; + strlcpy(info.type, name, sizeof(info.type)); + i2c_new_device(&adev->pm.i2c_bus->adapter, &info); + } + } else { + DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", + controller->ucType, + controller->ucI2cAddress >> 1, + (controller->ucFanParameters & + ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); + } + } +} + +enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev, + u32 sys_mask, + enum amdgpu_pcie_gen asic_gen, + enum amdgpu_pcie_gen default_gen) +{ + switch (asic_gen) { + case AMDGPU_PCIE_GEN1: + return AMDGPU_PCIE_GEN1; + case AMDGPU_PCIE_GEN2: + return AMDGPU_PCIE_GEN2; + case AMDGPU_PCIE_GEN3: + return AMDGPU_PCIE_GEN3; + default: + if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3)) + return AMDGPU_PCIE_GEN3; + else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2)) + return AMDGPU_PCIE_GEN2; + else + return AMDGPU_PCIE_GEN1; + } + return AMDGPU_PCIE_GEN1; +} + +u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev, + u16 asic_lanes, + u16 default_lanes) +{ + switch (asic_lanes) { + case 0: + default: + return default_lanes; + case 1: + return 1; + case 2: + return 2; + case 4: + return 4; + case 8: + return 8; + case 12: + return 12; + case 16: + return 16; + } +} + +u8 amdgpu_encode_pci_lane_width(u32 lanes) +{ + u8 encoded_lanes[] = { 0, 1, 2, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0, 6 }; + + if (lanes > 16) + return 0; + + return encoded_lanes[lanes]; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h new file mode 100644 index 000000000000..3738a96c2619 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h @@ -0,0 +1,85 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __AMDGPU_DPM_H__ +#define __AMDGPU_DPM_H__ + +#define R600_SSTU_DFLT 0 +#define R600_SST_DFLT 0x00C8 + +/* XXX are these ok? */ +#define R600_TEMP_RANGE_MIN (90 * 1000) +#define R600_TEMP_RANGE_MAX (120 * 1000) + +#define FDO_PWM_MODE_STATIC 1 +#define FDO_PWM_MODE_STATIC_RPM 5 + +enum amdgpu_td { + AMDGPU_TD_AUTO, + AMDGPU_TD_UP, + AMDGPU_TD_DOWN, +}; + +enum amdgpu_display_watermark { + AMDGPU_DISPLAY_WATERMARK_LOW = 0, + AMDGPU_DISPLAY_WATERMARK_HIGH = 1, +}; + +enum amdgpu_display_gap +{ + AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, + AMDGPU_PM_DISPLAY_GAP_VBLANK = 1, + AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2, + AMDGPU_PM_DISPLAY_GAP_IGNORE = 3, +}; + +void amdgpu_dpm_print_class_info(u32 class, u32 class2); +void amdgpu_dpm_print_cap_info(u32 caps); +void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, + struct amdgpu_ps *rps); +u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev); +u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev); +bool amdgpu_is_uvd_state(u32 class, u32 class2); +void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, + u32 *p, u32 *u); +int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th); + +bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor); + +int amdgpu_get_platform_caps(struct amdgpu_device *adev); + +int amdgpu_parse_extended_power_table(struct amdgpu_device *adev); +void amdgpu_free_extended_power_table(struct amdgpu_device *adev); + +void amdgpu_add_thermal_controller(struct amdgpu_device *adev); + +enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev, + u32 sys_mask, + enum amdgpu_pcie_gen asic_gen, + enum amdgpu_pcie_gen default_gen); + +u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev, + u16 asic_lanes, + u16 default_lanes); +u8 amdgpu_encode_pci_lane_width(u32 lanes); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c new file mode 100644 index 000000000000..d1af448795f3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -0,0 +1,439 @@ +/** + * \file amdgpu_drv.c + * AMD Amdgpu driver + * + * \author Gareth Hughes + */ + +/* + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include "amdgpu_drv.h" + +#include +#include +#include +#include +#include +#include "drm_crtc_helper.h" + +#include "amdgpu.h" +#include "amdgpu_irq.h" + +/* + * KMS wrapper. + * - 3.0.0 - initial driver + */ +#define KMS_DRIVER_MAJOR 3 +#define KMS_DRIVER_MINOR 0 +#define KMS_DRIVER_PATCHLEVEL 0 + +int amdgpu_vram_limit = 0; +int amdgpu_gart_size = -1; /* auto */ +int amdgpu_benchmarking = 0; +int amdgpu_testing = 0; +int amdgpu_audio = -1; +int amdgpu_disp_priority = 0; +int amdgpu_hw_i2c = 0; +int amdgpu_pcie_gen2 = -1; +int amdgpu_msi = -1; +int amdgpu_lockup_timeout = 10000; +int amdgpu_dpm = -1; +int amdgpu_smc_load_fw = 1; +int amdgpu_aspm = -1; +int amdgpu_runtime_pm = -1; +int amdgpu_hard_reset = 0; +unsigned amdgpu_ip_block_mask = 0xffffffff; +int amdgpu_bapm = -1; +int amdgpu_deep_color = 0; +int amdgpu_vm_size = 8; +int amdgpu_vm_block_size = -1; +int amdgpu_exp_hw_support = 0; + +MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); +module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); + +MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); +module_param_named(gartsize, amdgpu_gart_size, int, 0600); + +MODULE_PARM_DESC(benchmark, "Run benchmark"); +module_param_named(benchmark, amdgpu_benchmarking, int, 0444); + +MODULE_PARM_DESC(test, "Run tests"); +module_param_named(test, amdgpu_testing, int, 0444); + +MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); +module_param_named(audio, amdgpu_audio, int, 0444); + +MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); +module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); + +MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); +module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); + +MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); +module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); + +MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); +module_param_named(msi, amdgpu_msi, int, 0444); + +MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); +module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); + +MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); +module_param_named(dpm, amdgpu_dpm, int, 0444); + +MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); +module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); + +MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); +module_param_named(aspm, amdgpu_aspm, int, 0444); + +MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); +module_param_named(runpm, amdgpu_runtime_pm, int, 0444); + +MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); +module_param_named(hard_reset, amdgpu_hard_reset, int, 0444); + +MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); +module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); + +MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); +module_param_named(bapm, amdgpu_bapm, int, 0444); + +MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); +module_param_named(deep_color, amdgpu_deep_color, int, 0444); + +MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); +module_param_named(vm_size, amdgpu_vm_size, int, 0444); + +MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); +module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); + +MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); +module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); + +static struct pci_device_id pciidlist[] = { + + {0, 0, 0} +}; + +MODULE_DEVICE_TABLE(pci, pciidlist); + +static struct drm_driver kms_driver; + +static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) +{ + struct apertures_struct *ap; + bool primary = false; + + ap = alloc_apertures(1); + if (!ap) + return -ENOMEM; + + ap->ranges[0].base = pci_resource_start(pdev, 0); + ap->ranges[0].size = pci_resource_len(pdev, 0); + +#ifdef CONFIG_X86 + primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; +#endif + remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); + kfree(ap); + + return 0; +} + +static int amdgpu_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + unsigned long flags = ent->driver_data; + int ret; + + if ((flags & AMDGPU_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { + DRM_INFO("This hardware requires experimental hardware support.\n" + "See modparam exp_hw_support\n"); + return -ENODEV; + } + + /* Get rid of things like offb */ + ret = amdgpu_kick_out_firmware_fb(pdev); + if (ret) + return ret; + + return drm_get_pci_dev(pdev, ent, &kms_driver); +} + +static void +amdgpu_pci_remove(struct pci_dev *pdev) +{ + struct drm_device *dev = pci_get_drvdata(pdev); + + drm_put_dev(dev); +} + +static int amdgpu_pmops_suspend(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + return amdgpu_suspend_kms(drm_dev, true, true); +} + +static int amdgpu_pmops_resume(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + return amdgpu_resume_kms(drm_dev, true, true); +} + +static int amdgpu_pmops_freeze(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + return amdgpu_suspend_kms(drm_dev, false, true); +} + +static int amdgpu_pmops_thaw(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + return amdgpu_resume_kms(drm_dev, false, true); +} + +static int amdgpu_pmops_runtime_suspend(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + int ret; + + if (!amdgpu_device_is_px(drm_dev)) { + pm_runtime_forbid(dev); + return -EBUSY; + } + + drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; + drm_kms_helper_poll_disable(drm_dev); + vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); + + ret = amdgpu_suspend_kms(drm_dev, false, false); + pci_save_state(pdev); + pci_disable_device(pdev); + pci_ignore_hotplug(pdev); + pci_set_power_state(pdev, PCI_D3cold); + drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; + + return 0; +} + +static int amdgpu_pmops_runtime_resume(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + int ret; + + if (!amdgpu_device_is_px(drm_dev)) + return -EINVAL; + + drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; + + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); + ret = pci_enable_device(pdev); + if (ret) + return ret; + pci_set_master(pdev); + + ret = amdgpu_resume_kms(drm_dev, false, false); + drm_kms_helper_poll_enable(drm_dev); + vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); + drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; + return 0; +} + +static int amdgpu_pmops_runtime_idle(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + struct drm_crtc *crtc; + + if (!amdgpu_device_is_px(drm_dev)) { + pm_runtime_forbid(dev); + return -EBUSY; + } + + list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { + if (crtc->enabled) { + DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); + return -EBUSY; + } + } + + pm_runtime_mark_last_busy(dev); + pm_runtime_autosuspend(dev); + /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ + return 1; +} + +long amdgpu_drm_ioctl(struct file *filp, + unsigned int cmd, unsigned long arg) +{ + struct drm_file *file_priv = filp->private_data; + struct drm_device *dev; + long ret; + dev = file_priv->minor->dev; + ret = pm_runtime_get_sync(dev->dev); + if (ret < 0) + return ret; + + ret = drm_ioctl(filp, cmd, arg); + + pm_runtime_mark_last_busy(dev->dev); + pm_runtime_put_autosuspend(dev->dev); + return ret; +} + +static const struct dev_pm_ops amdgpu_pm_ops = { + .suspend = amdgpu_pmops_suspend, + .resume = amdgpu_pmops_resume, + .freeze = amdgpu_pmops_freeze, + .thaw = amdgpu_pmops_thaw, + .poweroff = amdgpu_pmops_freeze, + .restore = amdgpu_pmops_resume, + .runtime_suspend = amdgpu_pmops_runtime_suspend, + .runtime_resume = amdgpu_pmops_runtime_resume, + .runtime_idle = amdgpu_pmops_runtime_idle, +}; + +static const struct file_operations amdgpu_driver_kms_fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .unlocked_ioctl = amdgpu_drm_ioctl, + .mmap = amdgpu_mmap, + .poll = drm_poll, + .read = drm_read, +#ifdef CONFIG_COMPAT + .compat_ioctl = amdgpu_kms_compat_ioctl, +#endif +}; + +static struct drm_driver kms_driver = { + .driver_features = + DRIVER_USE_AGP | + DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | + DRIVER_PRIME | DRIVER_RENDER, + .dev_priv_size = 0, + .load = amdgpu_driver_load_kms, + .open = amdgpu_driver_open_kms, + .preclose = amdgpu_driver_preclose_kms, + .postclose = amdgpu_driver_postclose_kms, + .lastclose = amdgpu_driver_lastclose_kms, + .set_busid = drm_pci_set_busid, + .unload = amdgpu_driver_unload_kms, + .get_vblank_counter = amdgpu_get_vblank_counter_kms, + .enable_vblank = amdgpu_enable_vblank_kms, + .disable_vblank = amdgpu_disable_vblank_kms, + .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, + .get_scanout_position = amdgpu_get_crtc_scanoutpos, +#if defined(CONFIG_DEBUG_FS) + .debugfs_init = amdgpu_debugfs_init, + .debugfs_cleanup = amdgpu_debugfs_cleanup, +#endif + .irq_preinstall = amdgpu_irq_preinstall, + .irq_postinstall = amdgpu_irq_postinstall, + .irq_uninstall = amdgpu_irq_uninstall, + .irq_handler = amdgpu_irq_handler, + .ioctls = amdgpu_ioctls_kms, + .gem_free_object = amdgpu_gem_object_free, + .gem_open_object = amdgpu_gem_object_open, + .gem_close_object = amdgpu_gem_object_close, + .dumb_create = amdgpu_mode_dumb_create, + .dumb_map_offset = amdgpu_mode_dumb_mmap, + .dumb_destroy = drm_gem_dumb_destroy, + .fops = &amdgpu_driver_kms_fops, + + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, + .gem_prime_export = amdgpu_gem_prime_export, + .gem_prime_import = drm_gem_prime_import, + .gem_prime_pin = amdgpu_gem_prime_pin, + .gem_prime_unpin = amdgpu_gem_prime_unpin, + .gem_prime_res_obj = amdgpu_gem_prime_res_obj, + .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, + .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, + .gem_prime_vmap = amdgpu_gem_prime_vmap, + .gem_prime_vunmap = amdgpu_gem_prime_vunmap, + + .name = DRIVER_NAME, + .desc = DRIVER_DESC, + .date = DRIVER_DATE, + .major = KMS_DRIVER_MAJOR, + .minor = KMS_DRIVER_MINOR, + .patchlevel = KMS_DRIVER_PATCHLEVEL, +}; + +static struct drm_driver *driver; +static struct pci_driver *pdriver; + +static struct pci_driver amdgpu_kms_pci_driver = { + .name = DRIVER_NAME, + .id_table = pciidlist, + .probe = amdgpu_pci_probe, + .remove = amdgpu_pci_remove, + .driver.pm = &amdgpu_pm_ops, +}; + +static int __init amdgpu_init(void) +{ +#ifdef CONFIG_VGA_CONSOLE + if (vgacon_text_force()) { + DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); + return -EINVAL; + } +#endif + DRM_INFO("amdgpu kernel modesetting enabled.\n"); + driver = &kms_driver; + pdriver = &amdgpu_kms_pci_driver; + driver->driver_features |= DRIVER_MODESET; + driver->num_ioctls = amdgpu_max_kms_ioctl; + amdgpu_register_atpx_handler(); + + /* let modprobe override vga console setting */ + return drm_pci_init(driver, pdriver); +} + +static void __exit amdgpu_exit(void) +{ + drm_pci_exit(driver, pdriver); + amdgpu_unregister_atpx_handler(); +} + +module_init(amdgpu_init); +module_exit(amdgpu_exit); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h new file mode 100644 index 000000000000..cceeb33c447a --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h @@ -0,0 +1,48 @@ +/* amdgpu_drv.h -- Private header for amdgpu driver -*- linux-c -*- + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_DRV_H__ +#define __AMDGPU_DRV_H__ + +#include +#include + +#include "amdgpu_family.h" + +/* General customization: + */ + +#define DRIVER_AUTHOR "AMD linux driver team" + +#define DRIVER_NAME "amdgpu" +#define DRIVER_DESC "AMD GPU" +#define DRIVER_DATE "20150101" + +long amdgpu_drm_ioctl(struct file *filp, + unsigned int cmd, unsigned long arg); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c new file mode 100644 index 000000000000..94138abe093b --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -0,0 +1,245 @@ +/* + * Copyright 2007-8 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + */ +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_connectors.h" +#include "atom.h" +#include "atombios_encoders.h" + +void +amdgpu_link_encoder_connector(struct drm_device *dev) +{ + struct amdgpu_device *adev = dev->dev_private; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector; + struct drm_encoder *encoder; + struct amdgpu_encoder *amdgpu_encoder; + + /* walk the list and link encoders to connectors */ + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + amdgpu_connector = to_amdgpu_connector(connector); + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + amdgpu_encoder = to_amdgpu_encoder(encoder); + if (amdgpu_encoder->devices & amdgpu_connector->devices) { + drm_mode_connector_attach_encoder(connector, encoder); + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + amdgpu_atombios_encoder_init_backlight(amdgpu_encoder, connector); + adev->mode_info.bl_encoder = amdgpu_encoder; + } + } + } + } +} + +void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_connector *connector; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + amdgpu_encoder->active_device = amdgpu_encoder->devices & amdgpu_connector->devices; + DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", + amdgpu_encoder->active_device, amdgpu_encoder->devices, + amdgpu_connector->devices, encoder->encoder_type); + } + } +} + +struct drm_connector * +amdgpu_get_connector_for_encoder(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + amdgpu_connector = to_amdgpu_connector(connector); + if (amdgpu_encoder->active_device & amdgpu_connector->devices) + return connector; + } + return NULL; +} + +struct drm_connector * +amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + amdgpu_connector = to_amdgpu_connector(connector); + if (amdgpu_encoder->devices & amdgpu_connector->devices) + return connector; + } + return NULL; +} + +struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_encoder *other_encoder; + struct amdgpu_encoder *other_amdgpu_encoder; + + if (amdgpu_encoder->is_ext_encoder) + return NULL; + + list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { + if (other_encoder == encoder) + continue; + other_amdgpu_encoder = to_amdgpu_encoder(other_encoder); + if (other_amdgpu_encoder->is_ext_encoder && + (amdgpu_encoder->devices & other_amdgpu_encoder->devices)) + return other_encoder; + } + return NULL; +} + +u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder) +{ + struct drm_encoder *other_encoder = amdgpu_get_external_encoder(encoder); + + if (other_encoder) { + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(other_encoder); + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_TRAVIS: + case ENCODER_OBJECT_ID_NUTMEG: + return amdgpu_encoder->encoder_id; + default: + return ENCODER_OBJECT_ID_NONE; + } + } + return ENCODER_OBJECT_ID_NONE; +} + +void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, + struct drm_display_mode *adjusted_mode) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; + unsigned hblank = native_mode->htotal - native_mode->hdisplay; + unsigned vblank = native_mode->vtotal - native_mode->vdisplay; + unsigned hover = native_mode->hsync_start - native_mode->hdisplay; + unsigned vover = native_mode->vsync_start - native_mode->vdisplay; + unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; + unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start; + + adjusted_mode->clock = native_mode->clock; + adjusted_mode->flags = native_mode->flags; + + adjusted_mode->hdisplay = native_mode->hdisplay; + adjusted_mode->vdisplay = native_mode->vdisplay; + + adjusted_mode->htotal = native_mode->hdisplay + hblank; + adjusted_mode->hsync_start = native_mode->hdisplay + hover; + adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; + + adjusted_mode->vtotal = native_mode->vdisplay + vblank; + adjusted_mode->vsync_start = native_mode->vdisplay + vover; + adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width; + + drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); + + adjusted_mode->crtc_hdisplay = native_mode->hdisplay; + adjusted_mode->crtc_vdisplay = native_mode->vdisplay; + + adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank; + adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover; + adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width; + + adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank; + adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover; + adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width; + +} + +bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, + u32 pixel_clock) +{ + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector; + struct amdgpu_connector_atom_dig *dig_connector; + + connector = amdgpu_get_connector_for_encoder(encoder); + /* if we don't have an active device yet, just use one of + * the connectors tied to the encoder. + */ + if (!connector) + connector = amdgpu_get_connector_for_encoder_init(encoder); + amdgpu_connector = to_amdgpu_connector(connector); + + switch (connector->connector_type) { + case DRM_MODE_CONNECTOR_DVII: + case DRM_MODE_CONNECTOR_HDMIB: + if (amdgpu_connector->use_digital) { + /* HDMI 1.3 supports up to 340 Mhz over single link */ + if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { + if (pixel_clock > 340000) + return true; + else + return false; + } else { + if (pixel_clock > 165000) + return true; + else + return false; + } + } else + return false; + case DRM_MODE_CONNECTOR_DVID: + case DRM_MODE_CONNECTOR_HDMIA: + case DRM_MODE_CONNECTOR_DisplayPort: + dig_connector = amdgpu_connector->con_priv; + if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || + (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) + return false; + else { + /* HDMI 1.3 supports up to 340 Mhz over single link */ + if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { + if (pixel_clock > 340000) + return true; + else + return false; + } else { + if (pixel_clock > 165000) + return true; + else + return false; + } + } + default: + return false; + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c new file mode 100644 index 000000000000..2b1735d2efd6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -0,0 +1,432 @@ +/* + * Copyright © 2007 David Airlie + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * David Airlie + */ +#include +#include +#include + +#include +#include +#include +#include +#include "amdgpu.h" + +#include + +#include + +/* object hierarchy - + this contains a helper + a amdgpu fb + the helper contains a pointer to amdgpu framebuffer baseclass. +*/ +struct amdgpu_fbdev { + struct drm_fb_helper helper; + struct amdgpu_framebuffer rfb; + struct list_head fbdev_list; + struct amdgpu_device *adev; +}; + +static struct fb_ops amdgpufb_ops = { + .owner = THIS_MODULE, + .fb_check_var = drm_fb_helper_check_var, + .fb_set_par = drm_fb_helper_set_par, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_pan_display = drm_fb_helper_pan_display, + .fb_blank = drm_fb_helper_blank, + .fb_setcmap = drm_fb_helper_setcmap, + .fb_debug_enter = drm_fb_helper_debug_enter, + .fb_debug_leave = drm_fb_helper_debug_leave, +}; + + +int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled) +{ + int aligned = width; + int pitch_mask = 0; + + switch (bpp / 8) { + case 1: + pitch_mask = 255; + break; + case 2: + pitch_mask = 127; + break; + case 3: + case 4: + pitch_mask = 63; + break; + } + + aligned += pitch_mask; + aligned &= ~pitch_mask; + return aligned; +} + +static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) +{ + struct amdgpu_bo *rbo = gem_to_amdgpu_bo(gobj); + int ret; + + ret = amdgpu_bo_reserve(rbo, false); + if (likely(ret == 0)) { + amdgpu_bo_kunmap(rbo); + amdgpu_bo_unpin(rbo); + amdgpu_bo_unreserve(rbo); + } + drm_gem_object_unreference_unlocked(gobj); +} + +static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, + struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object **gobj_p) +{ + struct amdgpu_device *adev = rfbdev->adev; + struct drm_gem_object *gobj = NULL; + struct amdgpu_bo *rbo = NULL; + bool fb_tiled = false; /* useful for testing */ + u32 tiling_flags = 0; + int ret; + int aligned_size, size; + int height = mode_cmd->height; + u32 bpp, depth; + + drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); + + /* need to align pitch with crtc limits */ + mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, bpp, + fb_tiled) * ((bpp + 1) / 8); + + height = ALIGN(mode_cmd->height, 8); + size = mode_cmd->pitches[0] * height; + aligned_size = ALIGN(size, PAGE_SIZE); + ret = amdgpu_gem_object_create(adev, aligned_size, 0, + AMDGPU_GEM_DOMAIN_VRAM, + 0, true, + &gobj); + if (ret) { + printk(KERN_ERR "failed to allocate framebuffer (%d)\n", + aligned_size); + return -ENOMEM; + } + rbo = gem_to_amdgpu_bo(gobj); + + if (fb_tiled) + tiling_flags = AMDGPU_TILING_MACRO; + +#ifdef __BIG_ENDIAN + switch (bpp) { + case 32: + tiling_flags |= AMDGPU_TILING_SWAP_32BIT; + break; + case 16: + tiling_flags |= AMDGPU_TILING_SWAP_16BIT; + default: + break; + } +#endif + + ret = amdgpu_bo_reserve(rbo, false); + if (unlikely(ret != 0)) + goto out_unref; + + if (tiling_flags) { + ret = amdgpu_bo_set_tiling_flags(rbo, + tiling_flags | AMDGPU_TILING_SURFACE); + if (ret) + dev_err(adev->dev, "FB failed to set tiling flags\n"); + } + + + ret = amdgpu_bo_pin_restricted(rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL); + if (ret) { + amdgpu_bo_unreserve(rbo); + goto out_unref; + } + ret = amdgpu_bo_kmap(rbo, NULL); + amdgpu_bo_unreserve(rbo); + if (ret) { + goto out_unref; + } + + *gobj_p = gobj; + return 0; +out_unref: + amdgpufb_destroy_pinned_object(gobj); + *gobj_p = NULL; + return ret; +} + +static int amdgpufb_create(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes) +{ + struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper; + struct amdgpu_device *adev = rfbdev->adev; + struct fb_info *info; + struct drm_framebuffer *fb = NULL; + struct drm_mode_fb_cmd2 mode_cmd; + struct drm_gem_object *gobj = NULL; + struct amdgpu_bo *rbo = NULL; + struct device *device = &adev->pdev->dev; + int ret; + unsigned long tmp; + + mode_cmd.width = sizes->surface_width; + mode_cmd.height = sizes->surface_height; + + if (sizes->surface_bpp == 24) + sizes->surface_bpp = 32; + + mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, + sizes->surface_depth); + + ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj); + if (ret) { + DRM_ERROR("failed to create fbcon object %d\n", ret); + return ret; + } + + rbo = gem_to_amdgpu_bo(gobj); + + /* okay we have an object now allocate the framebuffer */ + info = framebuffer_alloc(0, device); + if (info == NULL) { + ret = -ENOMEM; + goto out_unref; + } + + info->par = rfbdev; + + ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj); + if (ret) { + DRM_ERROR("failed to initialize framebuffer %d\n", ret); + goto out_unref; + } + + fb = &rfbdev->rfb.base; + + /* setup helper */ + rfbdev->helper.fb = fb; + rfbdev->helper.fbdev = info; + + memset_io(rbo->kptr, 0x0, amdgpu_bo_size(rbo)); + + strcpy(info->fix.id, "amdgpudrmfb"); + + drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); + + info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT; + info->fbops = &amdgpufb_ops; + + tmp = amdgpu_bo_gpu_offset(rbo) - adev->mc.vram_start; + info->fix.smem_start = adev->mc.aper_base + tmp; + info->fix.smem_len = amdgpu_bo_size(rbo); + info->screen_base = rbo->kptr; + info->screen_size = amdgpu_bo_size(rbo); + + drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height); + + /* setup aperture base/size for vesafb takeover */ + info->apertures = alloc_apertures(1); + if (!info->apertures) { + ret = -ENOMEM; + goto out_unref; + } + info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base; + info->apertures->ranges[0].size = adev->mc.aper_size; + + /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ + + if (info->screen_base == NULL) { + ret = -ENOSPC; + goto out_unref; + } + + ret = fb_alloc_cmap(&info->cmap, 256, 0); + if (ret) { + ret = -ENOMEM; + goto out_unref; + } + + DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); + DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base); + DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(rbo)); + DRM_INFO("fb depth is %d\n", fb->depth); + DRM_INFO(" pitch is %d\n", fb->pitches[0]); + + vga_switcheroo_client_fb_set(adev->ddev->pdev, info); + return 0; + +out_unref: + if (rbo) { + + } + if (fb && ret) { + drm_gem_object_unreference(gobj); + drm_framebuffer_unregister_private(fb); + drm_framebuffer_cleanup(fb); + kfree(fb); + } + return ret; +} + +void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev) +{ + if (adev->mode_info.rfbdev) + drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper); +} + +static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) +{ + struct fb_info *info; + struct amdgpu_framebuffer *rfb = &rfbdev->rfb; + + if (rfbdev->helper.fbdev) { + info = rfbdev->helper.fbdev; + + unregister_framebuffer(info); + if (info->cmap.len) + fb_dealloc_cmap(&info->cmap); + framebuffer_release(info); + } + + if (rfb->obj) { + amdgpufb_destroy_pinned_object(rfb->obj); + rfb->obj = NULL; + } + drm_fb_helper_fini(&rfbdev->helper); + drm_framebuffer_unregister_private(&rfb->base); + drm_framebuffer_cleanup(&rfb->base); + + return 0; +} + +/** Sets the color ramps on behalf of fbcon */ +static void amdgpu_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, + u16 blue, int regno) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + amdgpu_crtc->lut_r[regno] = red >> 6; + amdgpu_crtc->lut_g[regno] = green >> 6; + amdgpu_crtc->lut_b[regno] = blue >> 6; +} + +/** Gets the color ramps on behalf of fbcon */ +static void amdgpu_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, int regno) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + *red = amdgpu_crtc->lut_r[regno] << 6; + *green = amdgpu_crtc->lut_g[regno] << 6; + *blue = amdgpu_crtc->lut_b[regno] << 6; +} + +static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = { + .gamma_set = amdgpu_crtc_fb_gamma_set, + .gamma_get = amdgpu_crtc_fb_gamma_get, + .fb_probe = amdgpufb_create, +}; + +int amdgpu_fbdev_init(struct amdgpu_device *adev) +{ + struct amdgpu_fbdev *rfbdev; + int bpp_sel = 32; + int ret; + + /* don't init fbdev on hw without DCE */ + if (!adev->mode_info.mode_config_initialized) + return 0; + + /* select 8 bpp console on low vram cards */ + if (adev->mc.real_vram_size <= (32*1024*1024)) + bpp_sel = 8; + + rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); + if (!rfbdev) + return -ENOMEM; + + rfbdev->adev = adev; + adev->mode_info.rfbdev = rfbdev; + + drm_fb_helper_prepare(adev->ddev, &rfbdev->helper, + &amdgpu_fb_helper_funcs); + + ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper, + adev->mode_info.num_crtc, + AMDGPUFB_CONN_LIMIT); + if (ret) { + kfree(rfbdev); + return ret; + } + + drm_fb_helper_single_add_all_connectors(&rfbdev->helper); + + /* disable all the possible outputs/crtcs before entering KMS mode */ + drm_helper_disable_unused_functions(adev->ddev); + + drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); + return 0; +} + +void amdgpu_fbdev_fini(struct amdgpu_device *adev) +{ + if (!adev->mode_info.rfbdev) + return; + + amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev); + kfree(adev->mode_info.rfbdev); + adev->mode_info.rfbdev = NULL; +} + +void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state) +{ + if (adev->mode_info.rfbdev) + fb_set_suspend(adev->mode_info.rfbdev->helper.fbdev, state); +} + +int amdgpu_fbdev_total_size(struct amdgpu_device *adev) +{ + struct amdgpu_bo *robj; + int size = 0; + + if (!adev->mode_info.rfbdev) + return 0; + + robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj); + size += amdgpu_bo_size(robj); + return size; +} + +bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) +{ + if (!adev->mode_info.rfbdev) + return false; + if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj)) + return true; + return false; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c new file mode 100644 index 000000000000..fc63855ed517 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -0,0 +1,1139 @@ +/* + * Copyright 2009 Jerome Glisse. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: + * Jerome Glisse + * Dave Airlie + */ +#include +#include +#include +#include +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_trace.h" + +/* + * Fences + * Fences mark an event in the GPUs pipeline and are used + * for GPU/CPU synchronization. When the fence is written, + * it is expected that all buffers associated with that fence + * are no longer in use by the associated ring on the GPU and + * that the the relevant GPU caches have been flushed. + */ + +/** + * amdgpu_fence_write - write a fence value + * + * @ring: ring the fence is associated with + * @seq: sequence number to write + * + * Writes a fence value to memory (all asics). + */ +static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) +{ + struct amdgpu_fence_driver *drv = &ring->fence_drv; + + if (drv->cpu_addr) + *drv->cpu_addr = cpu_to_le32(seq); +} + +/** + * amdgpu_fence_read - read a fence value + * + * @ring: ring the fence is associated with + * + * Reads a fence value from memory (all asics). + * Returns the value of the fence read from memory. + */ +static u32 amdgpu_fence_read(struct amdgpu_ring *ring) +{ + struct amdgpu_fence_driver *drv = &ring->fence_drv; + u32 seq = 0; + + if (drv->cpu_addr) + seq = le32_to_cpu(*drv->cpu_addr); + else + seq = lower_32_bits(atomic64_read(&drv->last_seq)); + + return seq; +} + +/** + * amdgpu_fence_schedule_check - schedule lockup check + * + * @ring: pointer to struct amdgpu_ring + * + * Queues a delayed work item to check for lockups. + */ +static void amdgpu_fence_schedule_check(struct amdgpu_ring *ring) +{ + /* + * Do not reset the timer here with mod_delayed_work, + * this can livelock in an interaction with TTM delayed destroy. + */ + queue_delayed_work(system_power_efficient_wq, + &ring->fence_drv.lockup_work, + AMDGPU_FENCE_JIFFIES_TIMEOUT); +} + +/** + * amdgpu_fence_emit - emit a fence on the requested ring + * + * @ring: ring the fence is associated with + * @owner: creator of the fence + * @fence: amdgpu fence object + * + * Emits a fence command on the requested ring (all asics). + * Returns 0 on success, -ENOMEM on failure. + */ +int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, + struct amdgpu_fence **fence) +{ + struct amdgpu_device *adev = ring->adev; + + /* we are protected by the ring emission mutex */ + *fence = kmalloc(sizeof(struct amdgpu_fence), GFP_KERNEL); + if ((*fence) == NULL) { + return -ENOMEM; + } + (*fence)->seq = ++ring->fence_drv.sync_seq[ring->idx]; + (*fence)->ring = ring; + (*fence)->owner = owner; + fence_init(&(*fence)->base, &amdgpu_fence_ops, + &adev->fence_queue.lock, adev->fence_context + ring->idx, + (*fence)->seq); + amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, (*fence)->seq, false); + trace_amdgpu_fence_emit(ring->adev->ddev, ring->idx, (*fence)->seq); + return 0; +} + +/** + * amdgpu_fence_check_signaled - callback from fence_queue + * + * this function is called with fence_queue lock held, which is also used + * for the fence locking itself, so unlocked variants are used for + * fence_signal, and remove_wait_queue. + */ +static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key) +{ + struct amdgpu_fence *fence; + struct amdgpu_device *adev; + u64 seq; + int ret; + + fence = container_of(wait, struct amdgpu_fence, fence_wake); + adev = fence->ring->adev; + + /* + * We cannot use amdgpu_fence_process here because we're already + * in the waitqueue, in a call from wake_up_all. + */ + seq = atomic64_read(&fence->ring->fence_drv.last_seq); + if (seq >= fence->seq) { + ret = fence_signal_locked(&fence->base); + if (!ret) + FENCE_TRACE(&fence->base, "signaled from irq context\n"); + else + FENCE_TRACE(&fence->base, "was already signaled\n"); + + amdgpu_irq_put(adev, fence->ring->fence_drv.irq_src, + fence->ring->fence_drv.irq_type); + __remove_wait_queue(&adev->fence_queue, &fence->fence_wake); + fence_put(&fence->base); + } else + FENCE_TRACE(&fence->base, "pending\n"); + return 0; +} + +/** + * amdgpu_fence_activity - check for fence activity + * + * @ring: pointer to struct amdgpu_ring + * + * Checks the current fence value and calculates the last + * signalled fence value. Returns true if activity occured + * on the ring, and the fence_queue should be waken up. + */ +static bool amdgpu_fence_activity(struct amdgpu_ring *ring) +{ + uint64_t seq, last_seq, last_emitted; + unsigned count_loop = 0; + bool wake = false; + + /* Note there is a scenario here for an infinite loop but it's + * very unlikely to happen. For it to happen, the current polling + * process need to be interrupted by another process and another + * process needs to update the last_seq btw the atomic read and + * xchg of the current process. + * + * More over for this to go in infinite loop there need to be + * continuously new fence signaled ie radeon_fence_read needs + * to return a different value each time for both the currently + * polling process and the other process that xchg the last_seq + * btw atomic read and xchg of the current process. And the + * value the other process set as last seq must be higher than + * the seq value we just read. Which means that current process + * need to be interrupted after radeon_fence_read and before + * atomic xchg. + * + * To be even more safe we count the number of time we loop and + * we bail after 10 loop just accepting the fact that we might + * have temporarly set the last_seq not to the true real last + * seq but to an older one. + */ + last_seq = atomic64_read(&ring->fence_drv.last_seq); + do { + last_emitted = ring->fence_drv.sync_seq[ring->idx]; + seq = amdgpu_fence_read(ring); + seq |= last_seq & 0xffffffff00000000LL; + if (seq < last_seq) { + seq &= 0xffffffff; + seq |= last_emitted & 0xffffffff00000000LL; + } + + if (seq <= last_seq || seq > last_emitted) { + break; + } + /* If we loop over we don't want to return without + * checking if a fence is signaled as it means that the + * seq we just read is different from the previous on. + */ + wake = true; + last_seq = seq; + if ((count_loop++) > 10) { + /* We looped over too many time leave with the + * fact that we might have set an older fence + * seq then the current real last seq as signaled + * by the hw. + */ + break; + } + } while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq); + + if (seq < last_emitted) + amdgpu_fence_schedule_check(ring); + + return wake; +} + +/** + * amdgpu_fence_check_lockup - check for hardware lockup + * + * @work: delayed work item + * + * Checks for fence activity and if there is none probe + * the hardware if a lockup occured. + */ +static void amdgpu_fence_check_lockup(struct work_struct *work) +{ + struct amdgpu_fence_driver *fence_drv; + struct amdgpu_ring *ring; + + fence_drv = container_of(work, struct amdgpu_fence_driver, + lockup_work.work); + ring = fence_drv->ring; + + if (!down_read_trylock(&ring->adev->exclusive_lock)) { + /* just reschedule the check if a reset is going on */ + amdgpu_fence_schedule_check(ring); + return; + } + + if (fence_drv->delayed_irq && ring->adev->ddev->irq_enabled) { + fence_drv->delayed_irq = false; + amdgpu_irq_update(ring->adev, fence_drv->irq_src, + fence_drv->irq_type); + } + + if (amdgpu_fence_activity(ring)) + wake_up_all(&ring->adev->fence_queue); + else if (amdgpu_ring_is_lockup(ring)) { + /* good news we believe it's a lockup */ + dev_warn(ring->adev->dev, "GPU lockup (current fence id " + "0x%016llx last fence id 0x%016llx on ring %d)\n", + (uint64_t)atomic64_read(&fence_drv->last_seq), + fence_drv->sync_seq[ring->idx], ring->idx); + + /* remember that we need an reset */ + ring->adev->needs_reset = true; + wake_up_all(&ring->adev->fence_queue); + } + up_read(&ring->adev->exclusive_lock); +} + +/** + * amdgpu_fence_process - process a fence + * + * @adev: amdgpu_device pointer + * @ring: ring index the fence is associated with + * + * Checks the current fence value and wakes the fence queue + * if the sequence number has increased (all asics). + */ +void amdgpu_fence_process(struct amdgpu_ring *ring) +{ + uint64_t seq, last_seq, last_emitted; + unsigned count_loop = 0; + bool wake = false; + + /* Note there is a scenario here for an infinite loop but it's + * very unlikely to happen. For it to happen, the current polling + * process need to be interrupted by another process and another + * process needs to update the last_seq btw the atomic read and + * xchg of the current process. + * + * More over for this to go in infinite loop there need to be + * continuously new fence signaled ie amdgpu_fence_read needs + * to return a different value each time for both the currently + * polling process and the other process that xchg the last_seq + * btw atomic read and xchg of the current process. And the + * value the other process set as last seq must be higher than + * the seq value we just read. Which means that current process + * need to be interrupted after amdgpu_fence_read and before + * atomic xchg. + * + * To be even more safe we count the number of time we loop and + * we bail after 10 loop just accepting the fact that we might + * have temporarly set the last_seq not to the true real last + * seq but to an older one. + */ + last_seq = atomic64_read(&ring->fence_drv.last_seq); + do { + last_emitted = ring->fence_drv.sync_seq[ring->idx]; + seq = amdgpu_fence_read(ring); + seq |= last_seq & 0xffffffff00000000LL; + if (seq < last_seq) { + seq &= 0xffffffff; + seq |= last_emitted & 0xffffffff00000000LL; + } + + if (seq <= last_seq || seq > last_emitted) { + break; + } + /* If we loop over we don't want to return without + * checking if a fence is signaled as it means that the + * seq we just read is different from the previous on. + */ + wake = true; + last_seq = seq; + if ((count_loop++) > 10) { + /* We looped over too many time leave with the + * fact that we might have set an older fence + * seq then the current real last seq as signaled + * by the hw. + */ + break; + } + } while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq); + + if (wake) + wake_up_all(&ring->adev->fence_queue); +} + +/** + * amdgpu_fence_seq_signaled - check if a fence sequence number has signaled + * + * @ring: ring the fence is associated with + * @seq: sequence number + * + * Check if the last signaled fence sequnce number is >= the requested + * sequence number (all asics). + * Returns true if the fence has signaled (current fence value + * is >= requested value) or false if it has not (current fence + * value is < the requested value. Helper function for + * amdgpu_fence_signaled(). + */ +static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq) +{ + if (atomic64_read(&ring->fence_drv.last_seq) >= seq) + return true; + + /* poll new last sequence at least once */ + amdgpu_fence_process(ring); + if (atomic64_read(&ring->fence_drv.last_seq) >= seq) + return true; + + return false; +} + +static bool amdgpu_fence_is_signaled(struct fence *f) +{ + struct amdgpu_fence *fence = to_amdgpu_fence(f); + struct amdgpu_ring *ring = fence->ring; + struct amdgpu_device *adev = ring->adev; + + if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) + return true; + + if (down_read_trylock(&adev->exclusive_lock)) { + amdgpu_fence_process(ring); + up_read(&adev->exclusive_lock); + + if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) + return true; + } + return false; +} + +/** + * amdgpu_fence_enable_signaling - enable signalling on fence + * @fence: fence + * + * This function is called with fence_queue lock held, and adds a callback + * to fence_queue that checks if this fence is signaled, and if so it + * signals the fence and removes itself. + */ +static bool amdgpu_fence_enable_signaling(struct fence *f) +{ + struct amdgpu_fence *fence = to_amdgpu_fence(f); + struct amdgpu_ring *ring = fence->ring; + struct amdgpu_device *adev = ring->adev; + + if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) + return false; + + if (down_read_trylock(&adev->exclusive_lock)) { + amdgpu_irq_get(adev, ring->fence_drv.irq_src, + ring->fence_drv.irq_type); + if (amdgpu_fence_activity(ring)) + wake_up_all_locked(&adev->fence_queue); + + /* did fence get signaled after we enabled the sw irq? */ + if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) { + amdgpu_irq_put(adev, ring->fence_drv.irq_src, + ring->fence_drv.irq_type); + up_read(&adev->exclusive_lock); + return false; + } + + up_read(&adev->exclusive_lock); + } else { + /* we're probably in a lockup, lets not fiddle too much */ + if (amdgpu_irq_get_delayed(adev, ring->fence_drv.irq_src, + ring->fence_drv.irq_type)) + ring->fence_drv.delayed_irq = true; + amdgpu_fence_schedule_check(ring); + } + + fence->fence_wake.flags = 0; + fence->fence_wake.private = NULL; + fence->fence_wake.func = amdgpu_fence_check_signaled; + __add_wait_queue(&adev->fence_queue, &fence->fence_wake); + fence_get(f); + FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); + return true; +} + +/** + * amdgpu_fence_signaled - check if a fence has signaled + * + * @fence: amdgpu fence object + * + * Check if the requested fence has signaled (all asics). + * Returns true if the fence has signaled or false if it has not. + */ +bool amdgpu_fence_signaled(struct amdgpu_fence *fence) +{ + if (!fence) + return true; + + if (fence->seq == AMDGPU_FENCE_SIGNALED_SEQ) + return true; + + if (amdgpu_fence_seq_signaled(fence->ring, fence->seq)) { + fence->seq = AMDGPU_FENCE_SIGNALED_SEQ; + if (!fence_signal(&fence->base)) + FENCE_TRACE(&fence->base, "signaled from amdgpu_fence_signaled\n"); + return true; + } + + return false; +} + +/** + * amdgpu_fence_any_seq_signaled - check if any sequence number is signaled + * + * @adev: amdgpu device pointer + * @seq: sequence numbers + * + * Check if the last signaled fence sequnce number is >= the requested + * sequence number (all asics). + * Returns true if any has signaled (current value is >= requested value) + * or false if it has not. Helper function for amdgpu_fence_wait_seq. + */ +static bool amdgpu_fence_any_seq_signaled(struct amdgpu_device *adev, u64 *seq) +{ + unsigned i; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + if (!adev->rings[i] || !seq[i]) + continue; + + if (amdgpu_fence_seq_signaled(adev->rings[i], seq[i])) + return true; + } + + return false; +} + +/** + * amdgpu_fence_wait_seq_timeout - wait for a specific sequence numbers + * + * @adev: amdgpu device pointer + * @target_seq: sequence number(s) we want to wait for + * @intr: use interruptable sleep + * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait + * + * Wait for the requested sequence number(s) to be written by any ring + * (all asics). Sequnce number array is indexed by ring id. + * @intr selects whether to use interruptable (true) or non-interruptable + * (false) sleep when waiting for the sequence number. Helper function + * for amdgpu_fence_wait_*(). + * Returns remaining time if the sequence number has passed, 0 when + * the wait timeout, or an error for all other cases. + * -EDEADLK is returned when a GPU lockup has been detected. + */ +long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev, u64 *target_seq, + bool intr, long timeout) +{ + uint64_t last_seq[AMDGPU_MAX_RINGS]; + bool signaled; + int i, r; + + while (!amdgpu_fence_any_seq_signaled(adev, target_seq)) { + + /* Save current sequence values, used to check for GPU lockups */ + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !target_seq[i]) + continue; + + last_seq[i] = atomic64_read(&ring->fence_drv.last_seq); + trace_amdgpu_fence_wait_begin(adev->ddev, i, target_seq[i]); + amdgpu_irq_get(adev, ring->fence_drv.irq_src, + ring->fence_drv.irq_type); + } + + if (intr) { + r = wait_event_interruptible_timeout(adev->fence_queue, ( + (signaled = amdgpu_fence_any_seq_signaled(adev, target_seq)) + || adev->needs_reset), AMDGPU_FENCE_JIFFIES_TIMEOUT); + } else { + r = wait_event_timeout(adev->fence_queue, ( + (signaled = amdgpu_fence_any_seq_signaled(adev, target_seq)) + || adev->needs_reset), AMDGPU_FENCE_JIFFIES_TIMEOUT); + } + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !target_seq[i]) + continue; + + amdgpu_irq_put(adev, ring->fence_drv.irq_src, + ring->fence_drv.irq_type); + trace_amdgpu_fence_wait_end(adev->ddev, i, target_seq[i]); + } + + if (unlikely(r < 0)) + return r; + + if (unlikely(!signaled)) { + + if (adev->needs_reset) + return -EDEADLK; + + /* we were interrupted for some reason and fence + * isn't signaled yet, resume waiting */ + if (r) + continue; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !target_seq[i]) + continue; + + if (last_seq[i] != atomic64_read(&ring->fence_drv.last_seq)) + break; + } + + if (i != AMDGPU_MAX_RINGS) + continue; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + if (!adev->rings[i] || !target_seq[i]) + continue; + + if (amdgpu_ring_is_lockup(adev->rings[i])) + break; + } + + if (i < AMDGPU_MAX_RINGS) { + /* good news we believe it's a lockup */ + dev_warn(adev->dev, "GPU lockup (waiting for " + "0x%016llx last fence id 0x%016llx on" + " ring %d)\n", + target_seq[i], last_seq[i], i); + + /* remember that we need an reset */ + adev->needs_reset = true; + wake_up_all(&adev->fence_queue); + return -EDEADLK; + } + + if (timeout < MAX_SCHEDULE_TIMEOUT) { + timeout -= AMDGPU_FENCE_JIFFIES_TIMEOUT; + if (timeout <= 0) { + return 0; + } + } + } + } + return timeout; +} + +/** + * amdgpu_fence_wait - wait for a fence to signal + * + * @fence: amdgpu fence object + * @intr: use interruptable sleep + * + * Wait for the requested fence to signal (all asics). + * @intr selects whether to use interruptable (true) or non-interruptable + * (false) sleep when waiting for the fence. + * Returns 0 if the fence has passed, error for all other cases. + */ +int amdgpu_fence_wait(struct amdgpu_fence *fence, bool intr) +{ + uint64_t seq[AMDGPU_MAX_RINGS] = {}; + long r; + + seq[fence->ring->idx] = fence->seq; + if (seq[fence->ring->idx] == AMDGPU_FENCE_SIGNALED_SEQ) + return 0; + + r = amdgpu_fence_wait_seq_timeout(fence->ring->adev, seq, intr, MAX_SCHEDULE_TIMEOUT); + if (r < 0) { + return r; + } + + fence->seq = AMDGPU_FENCE_SIGNALED_SEQ; + r = fence_signal(&fence->base); + if (!r) + FENCE_TRACE(&fence->base, "signaled from fence_wait\n"); + return 0; +} + +/** + * amdgpu_fence_wait_any - wait for a fence to signal on any ring + * + * @adev: amdgpu device pointer + * @fences: amdgpu fence object(s) + * @intr: use interruptable sleep + * + * Wait for any requested fence to signal (all asics). Fence + * array is indexed by ring id. @intr selects whether to use + * interruptable (true) or non-interruptable (false) sleep when + * waiting for the fences. Used by the suballocator. + * Returns 0 if any fence has passed, error for all other cases. + */ +int amdgpu_fence_wait_any(struct amdgpu_device *adev, + struct amdgpu_fence **fences, + bool intr) +{ + uint64_t seq[AMDGPU_MAX_RINGS]; + unsigned i, num_rings = 0; + long r; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + seq[i] = 0; + + if (!fences[i]) { + continue; + } + + seq[i] = fences[i]->seq; + ++num_rings; + + /* test if something was allready signaled */ + if (seq[i] == AMDGPU_FENCE_SIGNALED_SEQ) + return 0; + } + + /* nothing to wait for ? */ + if (num_rings == 0) + return -ENOENT; + + r = amdgpu_fence_wait_seq_timeout(adev, seq, intr, MAX_SCHEDULE_TIMEOUT); + if (r < 0) { + return r; + } + return 0; +} + +/** + * amdgpu_fence_wait_next - wait for the next fence to signal + * + * @adev: amdgpu device pointer + * @ring: ring index the fence is associated with + * + * Wait for the next fence on the requested ring to signal (all asics). + * Returns 0 if the next fence has passed, error for all other cases. + * Caller must hold ring lock. + */ +int amdgpu_fence_wait_next(struct amdgpu_ring *ring) +{ + uint64_t seq[AMDGPU_MAX_RINGS] = {}; + long r; + + seq[ring->idx] = atomic64_read(&ring->fence_drv.last_seq) + 1ULL; + if (seq[ring->idx] >= ring->fence_drv.sync_seq[ring->idx]) { + /* nothing to wait for, last_seq is + already the last emited fence */ + return -ENOENT; + } + r = amdgpu_fence_wait_seq_timeout(ring->adev, seq, false, MAX_SCHEDULE_TIMEOUT); + if (r < 0) + return r; + return 0; +} + +/** + * amdgpu_fence_wait_empty - wait for all fences to signal + * + * @adev: amdgpu device pointer + * @ring: ring index the fence is associated with + * + * Wait for all fences on the requested ring to signal (all asics). + * Returns 0 if the fences have passed, error for all other cases. + * Caller must hold ring lock. + */ +int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint64_t seq[AMDGPU_MAX_RINGS] = {}; + long r; + + seq[ring->idx] = ring->fence_drv.sync_seq[ring->idx]; + if (!seq[ring->idx]) + return 0; + + r = amdgpu_fence_wait_seq_timeout(adev, seq, false, MAX_SCHEDULE_TIMEOUT); + if (r < 0) { + if (r == -EDEADLK) + return -EDEADLK; + + dev_err(adev->dev, "error waiting for ring[%d] to become idle (%ld)\n", + ring->idx, r); + } + return 0; +} + +/** + * amdgpu_fence_ref - take a ref on a fence + * + * @fence: amdgpu fence object + * + * Take a reference on a fence (all asics). + * Returns the fence. + */ +struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence) +{ + fence_get(&fence->base); + return fence; +} + +/** + * amdgpu_fence_unref - remove a ref on a fence + * + * @fence: amdgpu fence object + * + * Remove a reference on a fence (all asics). + */ +void amdgpu_fence_unref(struct amdgpu_fence **fence) +{ + struct amdgpu_fence *tmp = *fence; + + *fence = NULL; + if (tmp) + fence_put(&tmp->base); +} + +/** + * amdgpu_fence_count_emitted - get the count of emitted fences + * + * @ring: ring the fence is associated with + * + * Get the number of fences emitted on the requested ring (all asics). + * Returns the number of emitted fences on the ring. Used by the + * dynpm code to ring track activity. + */ +unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) +{ + uint64_t emitted; + + /* We are not protected by ring lock when reading the last sequence + * but it's ok to report slightly wrong fence count here. + */ + amdgpu_fence_process(ring); + emitted = ring->fence_drv.sync_seq[ring->idx] + - atomic64_read(&ring->fence_drv.last_seq); + /* to avoid 32bits warp around */ + if (emitted > 0x10000000) + emitted = 0x10000000; + + return (unsigned)emitted; +} + +/** + * amdgpu_fence_need_sync - do we need a semaphore + * + * @fence: amdgpu fence object + * @dst_ring: which ring to check against + * + * Check if the fence needs to be synced against another ring + * (all asics). If so, we need to emit a semaphore. + * Returns true if we need to sync with another ring, false if + * not. + */ +bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, + struct amdgpu_ring *dst_ring) +{ + struct amdgpu_fence_driver *fdrv; + + if (!fence) + return false; + + if (fence->ring == dst_ring) + return false; + + /* we are protected by the ring mutex */ + fdrv = &dst_ring->fence_drv; + if (fence->seq <= fdrv->sync_seq[fence->ring->idx]) + return false; + + return true; +} + +/** + * amdgpu_fence_note_sync - record the sync point + * + * @fence: amdgpu fence object + * @dst_ring: which ring to check against + * + * Note the sequence number at which point the fence will + * be synced with the requested ring (all asics). + */ +void amdgpu_fence_note_sync(struct amdgpu_fence *fence, + struct amdgpu_ring *dst_ring) +{ + struct amdgpu_fence_driver *dst, *src; + unsigned i; + + if (!fence) + return; + + if (fence->ring == dst_ring) + return; + + /* we are protected by the ring mutex */ + src = &fence->ring->fence_drv; + dst = &dst_ring->fence_drv; + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + if (i == dst_ring->idx) + continue; + + dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]); + } +} + +/** + * amdgpu_fence_driver_start_ring - make the fence driver + * ready for use on the requested ring. + * + * @ring: ring to start the fence driver on + * @irq_src: interrupt source to use for this ring + * @irq_type: interrupt type to use for this ring + * + * Make the fence driver ready for processing (all asics). + * Not all asics have all rings, so each asic will only + * start the fence driver on the rings it has. + * Returns 0 for success, errors for failure. + */ +int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, + struct amdgpu_irq_src *irq_src, + unsigned irq_type) +{ + struct amdgpu_device *adev = ring->adev; + uint64_t index; + + if (ring != &adev->uvd.ring) { + ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; + ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); + } else { + /* put fence directly behind firmware */ + index = ALIGN(adev->uvd.fw->size, 8); + ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index; + ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index; + } + amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq)); + ring->fence_drv.initialized = true; + ring->fence_drv.irq_src = irq_src; + ring->fence_drv.irq_type = irq_type; + dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " + "cpu addr 0x%p\n", ring->idx, + ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); + return 0; +} + +/** + * amdgpu_fence_driver_init_ring - init the fence driver + * for the requested ring. + * + * @ring: ring to init the fence driver on + * + * Init the fence driver for the requested ring (all asics). + * Helper function for amdgpu_fence_driver_init(). + */ +void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) +{ + int i; + + ring->fence_drv.cpu_addr = NULL; + ring->fence_drv.gpu_addr = 0; + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) + ring->fence_drv.sync_seq[i] = 0; + + atomic64_set(&ring->fence_drv.last_seq, 0); + ring->fence_drv.initialized = false; + + INIT_DELAYED_WORK(&ring->fence_drv.lockup_work, + amdgpu_fence_check_lockup); + ring->fence_drv.ring = ring; +} + +/** + * amdgpu_fence_driver_init - init the fence driver + * for all possible rings. + * + * @adev: amdgpu device pointer + * + * Init the fence driver for all possible rings (all asics). + * Not all asics have all rings, so each asic will only + * start the fence driver on the rings it has using + * amdgpu_fence_driver_start_ring(). + * Returns 0 for success. + */ +int amdgpu_fence_driver_init(struct amdgpu_device *adev) +{ + init_waitqueue_head(&adev->fence_queue); + if (amdgpu_debugfs_fence_init(adev)) + dev_err(adev->dev, "fence debugfs file creation failed\n"); + + return 0; +} + +/** + * amdgpu_fence_driver_fini - tear down the fence driver + * for all possible rings. + * + * @adev: amdgpu device pointer + * + * Tear down the fence driver for all possible rings (all asics). + */ +void amdgpu_fence_driver_fini(struct amdgpu_device *adev) +{ + int i, r; + + mutex_lock(&adev->ring_lock); + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + if (!ring || !ring->fence_drv.initialized) + continue; + r = amdgpu_fence_wait_empty(ring); + if (r) { + /* no need to trigger GPU reset as we are unloading */ + amdgpu_fence_driver_force_completion(adev); + } + wake_up_all(&adev->fence_queue); + ring->fence_drv.initialized = false; + } + mutex_unlock(&adev->ring_lock); +} + +/** + * amdgpu_fence_driver_force_completion - force all fence waiter to complete + * + * @adev: amdgpu device pointer + * + * In case of GPU reset failure make sure no process keep waiting on fence + * that will never complete. + */ +void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + if (!ring || !ring->fence_drv.initialized) + continue; + + amdgpu_fence_write(ring, ring->fence_drv.sync_seq[i]); + } +} + + +/* + * Fence debugfs + */ +#if defined(CONFIG_DEBUG_FS) +static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + int i, j; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_ring *ring = adev->rings[i]; + if (!ring || !ring->fence_drv.initialized) + continue; + + amdgpu_fence_process(ring); + + seq_printf(m, "--- ring %d ---\n", i); + seq_printf(m, "Last signaled fence 0x%016llx\n", + (unsigned long long)atomic64_read(&ring->fence_drv.last_seq)); + seq_printf(m, "Last emitted 0x%016llx\n", + ring->fence_drv.sync_seq[i]); + + for (j = 0; j < AMDGPU_MAX_RINGS; ++j) { + struct amdgpu_ring *other = adev->rings[j]; + if (i != j && other && other->fence_drv.initialized) + seq_printf(m, "Last sync to ring %d 0x%016llx\n", + j, ring->fence_drv.sync_seq[j]); + } + } + return 0; +} + +static struct drm_info_list amdgpu_debugfs_fence_list[] = { + {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, +}; +#endif + +int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 1); +#else + return 0; +#endif +} + +static const char *amdgpu_fence_get_driver_name(struct fence *fence) +{ + return "amdgpu"; +} + +static const char *amdgpu_fence_get_timeline_name(struct fence *f) +{ + struct amdgpu_fence *fence = to_amdgpu_fence(f); + return (const char *)fence->ring->name; +} + +static inline bool amdgpu_test_signaled(struct amdgpu_fence *fence) +{ + return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags); +} + +struct amdgpu_wait_cb { + struct fence_cb base; + struct task_struct *task; +}; + +static void amdgpu_fence_wait_cb(struct fence *fence, struct fence_cb *cb) +{ + struct amdgpu_wait_cb *wait = + container_of(cb, struct amdgpu_wait_cb, base); + wake_up_process(wait->task); +} + +static signed long amdgpu_fence_default_wait(struct fence *f, bool intr, + signed long t) +{ + struct amdgpu_fence *fence = to_amdgpu_fence(f); + struct amdgpu_device *adev = fence->ring->adev; + struct amdgpu_wait_cb cb; + + cb.task = current; + + if (fence_add_callback(f, &cb.base, amdgpu_fence_wait_cb)) + return t; + + while (t > 0) { + if (intr) + set_current_state(TASK_INTERRUPTIBLE); + else + set_current_state(TASK_UNINTERRUPTIBLE); + + /* + * amdgpu_test_signaled must be called after + * set_current_state to prevent a race with wake_up_process + */ + if (amdgpu_test_signaled(fence)) + break; + + if (adev->needs_reset) { + t = -EDEADLK; + break; + } + + t = schedule_timeout(t); + + if (t > 0 && intr && signal_pending(current)) + t = -ERESTARTSYS; + } + + __set_current_state(TASK_RUNNING); + fence_remove_callback(f, &cb.base); + + return t; +} + +const struct fence_ops amdgpu_fence_ops = { + .get_driver_name = amdgpu_fence_get_driver_name, + .get_timeline_name = amdgpu_fence_get_timeline_name, + .enable_signaling = amdgpu_fence_enable_signaling, + .signaled = amdgpu_fence_is_signaled, + .wait = amdgpu_fence_default_wait, + .release = NULL, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c new file mode 100644 index 000000000000..e02db0b2e839 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -0,0 +1,371 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include +#include +#include "amdgpu.h" + +/* + * GART + * The GART (Graphics Aperture Remapping Table) is an aperture + * in the GPU's address space. System pages can be mapped into + * the aperture and look like contiguous pages from the GPU's + * perspective. A page table maps the pages in the aperture + * to the actual backing pages in system memory. + * + * Radeon GPUs support both an internal GART, as described above, + * and AGP. AGP works similarly, but the GART table is configured + * and maintained by the northbridge rather than the driver. + * Radeon hw has a separate AGP aperture that is programmed to + * point to the AGP aperture provided by the northbridge and the + * requests are passed through to the northbridge aperture. + * Both AGP and internal GART can be used at the same time, however + * that is not currently supported by the driver. + * + * This file handles the common internal GART management. + */ + +/* + * Common GART table functions. + */ +/** + * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table + * + * @adev: amdgpu_device pointer + * + * Allocate system memory for GART page table + * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the + * gart table to be in system memory. + * Returns 0 for success, -ENOMEM for failure. + */ +int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) +{ + void *ptr; + + ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size, + &adev->gart.table_addr); + if (ptr == NULL) { + return -ENOMEM; + } +#ifdef CONFIG_X86 + if (0) { + set_memory_uc((unsigned long)ptr, + adev->gart.table_size >> PAGE_SHIFT); + } +#endif + adev->gart.ptr = ptr; + memset((void *)adev->gart.ptr, 0, adev->gart.table_size); + return 0; +} + +/** + * amdgpu_gart_table_ram_free - free system ram for gart page table + * + * @adev: amdgpu_device pointer + * + * Free system memory for GART page table + * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the + * gart table to be in system memory. + */ +void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) +{ + if (adev->gart.ptr == NULL) { + return; + } +#ifdef CONFIG_X86 + if (0) { + set_memory_wb((unsigned long)adev->gart.ptr, + adev->gart.table_size >> PAGE_SHIFT); + } +#endif + pci_free_consistent(adev->pdev, adev->gart.table_size, + (void *)adev->gart.ptr, + adev->gart.table_addr); + adev->gart.ptr = NULL; + adev->gart.table_addr = 0; +} + +/** + * amdgpu_gart_table_vram_alloc - allocate vram for gart page table + * + * @adev: amdgpu_device pointer + * + * Allocate video memory for GART page table + * (pcie r4xx, r5xx+). These asics require the + * gart table to be in video memory. + * Returns 0 for success, error for failure. + */ +int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) +{ + int r; + + if (adev->gart.robj == NULL) { + r = amdgpu_bo_create(adev, adev->gart.table_size, + PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0, + NULL, &adev->gart.robj); + if (r) { + return r; + } + } + return 0; +} + +/** + * amdgpu_gart_table_vram_pin - pin gart page table in vram + * + * @adev: amdgpu_device pointer + * + * Pin the GART page table in vram so it will not be moved + * by the memory manager (pcie r4xx, r5xx+). These asics require the + * gart table to be in video memory. + * Returns 0 for success, error for failure. + */ +int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev) +{ + uint64_t gpu_addr; + int r; + + r = amdgpu_bo_reserve(adev->gart.robj, false); + if (unlikely(r != 0)) + return r; + r = amdgpu_bo_pin(adev->gart.robj, + AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr); + if (r) { + amdgpu_bo_unreserve(adev->gart.robj); + return r; + } + r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr); + if (r) + amdgpu_bo_unpin(adev->gart.robj); + amdgpu_bo_unreserve(adev->gart.robj); + adev->gart.table_addr = gpu_addr; + return r; +} + +/** + * amdgpu_gart_table_vram_unpin - unpin gart page table in vram + * + * @adev: amdgpu_device pointer + * + * Unpin the GART page table in vram (pcie r4xx, r5xx+). + * These asics require the gart table to be in video memory. + */ +void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev) +{ + int r; + + if (adev->gart.robj == NULL) { + return; + } + r = amdgpu_bo_reserve(adev->gart.robj, false); + if (likely(r == 0)) { + amdgpu_bo_kunmap(adev->gart.robj); + amdgpu_bo_unpin(adev->gart.robj); + amdgpu_bo_unreserve(adev->gart.robj); + adev->gart.ptr = NULL; + } +} + +/** + * amdgpu_gart_table_vram_free - free gart page table vram + * + * @adev: amdgpu_device pointer + * + * Free the video memory used for the GART page table + * (pcie r4xx, r5xx+). These asics require the gart table to + * be in video memory. + */ +void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) +{ + if (adev->gart.robj == NULL) { + return; + } + amdgpu_bo_unref(&adev->gart.robj); +} + +/* + * Common gart functions. + */ +/** + * amdgpu_gart_unbind - unbind pages from the gart page table + * + * @adev: amdgpu_device pointer + * @offset: offset into the GPU's gart aperture + * @pages: number of pages to unbind + * + * Unbinds the requested pages from the gart page table and + * replaces them with the dummy page (all asics). + */ +void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, + int pages) +{ + unsigned t; + unsigned p; + int i, j; + u64 page_base; + uint32_t flags = AMDGPU_PTE_SYSTEM; + + if (!adev->gart.ready) { + WARN(1, "trying to unbind memory from uninitialized GART !\n"); + return; + } + + t = offset / AMDGPU_GPU_PAGE_SIZE; + p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); + for (i = 0; i < pages; i++, p++) { + if (adev->gart.pages[p]) { + adev->gart.pages[p] = NULL; + adev->gart.pages_addr[p] = adev->dummy_page.addr; + page_base = adev->gart.pages_addr[p]; + if (!adev->gart.ptr) + continue; + + for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { + amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, + t, page_base, flags); + page_base += AMDGPU_GPU_PAGE_SIZE; + } + } + } + mb(); + amdgpu_gart_flush_gpu_tlb(adev, 0); +} + +/** + * amdgpu_gart_bind - bind pages into the gart page table + * + * @adev: amdgpu_device pointer + * @offset: offset into the GPU's gart aperture + * @pages: number of pages to bind + * @pagelist: pages to bind + * @dma_addr: DMA addresses of pages + * + * Binds the requested pages to the gart page table + * (all asics). + * Returns 0 for success, -EINVAL for failure. + */ +int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, + int pages, struct page **pagelist, dma_addr_t *dma_addr, + uint32_t flags) +{ + unsigned t; + unsigned p; + uint64_t page_base; + int i, j; + + if (!adev->gart.ready) { + WARN(1, "trying to bind memory to uninitialized GART !\n"); + return -EINVAL; + } + + t = offset / AMDGPU_GPU_PAGE_SIZE; + p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); + + for (i = 0; i < pages; i++, p++) { + adev->gart.pages_addr[p] = dma_addr[i]; + adev->gart.pages[p] = pagelist[i]; + if (adev->gart.ptr) { + page_base = adev->gart.pages_addr[p]; + for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { + amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, t, page_base, flags); + page_base += AMDGPU_GPU_PAGE_SIZE; + } + } + } + mb(); + amdgpu_gart_flush_gpu_tlb(adev, 0); + return 0; +} + +/** + * amdgpu_gart_init - init the driver info for managing the gart + * + * @adev: amdgpu_device pointer + * + * Allocate the dummy page and init the gart driver info (all asics). + * Returns 0 for success, error for failure. + */ +int amdgpu_gart_init(struct amdgpu_device *adev) +{ + int r, i; + + if (adev->gart.pages) { + return 0; + } + /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ + if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { + DRM_ERROR("Page size is smaller than GPU page size!\n"); + return -EINVAL; + } + r = amdgpu_dummy_page_init(adev); + if (r) + return r; + /* Compute table size */ + adev->gart.num_cpu_pages = adev->mc.gtt_size / PAGE_SIZE; + adev->gart.num_gpu_pages = adev->mc.gtt_size / AMDGPU_GPU_PAGE_SIZE; + DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", + adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); + /* Allocate pages table */ + adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages); + if (adev->gart.pages == NULL) { + amdgpu_gart_fini(adev); + return -ENOMEM; + } + adev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) * + adev->gart.num_cpu_pages); + if (adev->gart.pages_addr == NULL) { + amdgpu_gart_fini(adev); + return -ENOMEM; + } + /* set GART entry to point to the dummy page by default */ + for (i = 0; i < adev->gart.num_cpu_pages; i++) { + adev->gart.pages_addr[i] = adev->dummy_page.addr; + } + return 0; +} + +/** + * amdgpu_gart_fini - tear down the driver info for managing the gart + * + * @adev: amdgpu_device pointer + * + * Tear down the gart driver info and free the dummy page (all asics). + */ +void amdgpu_gart_fini(struct amdgpu_device *adev) +{ + if (adev->gart.pages && adev->gart.pages_addr && adev->gart.ready) { + /* unbind pages */ + amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages); + } + adev->gart.ready = false; + vfree(adev->gart.pages); + vfree(adev->gart.pages_addr); + adev->gart.pages = NULL; + adev->gart.pages_addr = NULL; + + amdgpu_dummy_page_fini(adev); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h new file mode 100644 index 000000000000..c3f4e85594ff --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h @@ -0,0 +1,72 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_GDS_H__ +#define __AMDGPU_GDS_H__ + +/* Because TTM request that alloacted buffer should be PAGE_SIZE aligned, + * we should report GDS/GWS/OA size as PAGE_SIZE aligned + * */ +#define AMDGPU_GDS_SHIFT 2 +#define AMDGPU_GWS_SHIFT PAGE_SHIFT +#define AMDGPU_OA_SHIFT PAGE_SHIFT + +#define AMDGPU_PL_GDS TTM_PL_PRIV0 +#define AMDGPU_PL_GWS TTM_PL_PRIV1 +#define AMDGPU_PL_OA TTM_PL_PRIV2 + +#define AMDGPU_PL_FLAG_GDS TTM_PL_FLAG_PRIV0 +#define AMDGPU_PL_FLAG_GWS TTM_PL_FLAG_PRIV1 +#define AMDGPU_PL_FLAG_OA TTM_PL_FLAG_PRIV2 + +struct amdgpu_ring; +struct amdgpu_bo; + +struct amdgpu_gds_asic_info { + uint32_t total_size; + uint32_t gfx_partition_size; + uint32_t cs_partition_size; +}; + +struct amdgpu_gds { + struct amdgpu_gds_asic_info mem; + struct amdgpu_gds_asic_info gws; + struct amdgpu_gds_asic_info oa; + /* At present, GDS, GWS and OA resources for gfx (graphics) + * is always pre-allocated and available for graphics operation. + * Such resource is shared between all gfx clients. + * TODO: move this operation to user space + * */ + struct amdgpu_bo* gds_gfx_bo; + struct amdgpu_bo* gws_gfx_bo; + struct amdgpu_bo* oa_gfx_bo; +}; + +struct amdgpu_gds_reg_offset { + uint32_t mem_base; + uint32_t mem_size; + uint32_t gws; + uint32_t oa; +}; + +#endif /* __AMDGPU_GDS_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c new file mode 100644 index 000000000000..5fd0bc73b302 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -0,0 +1,735 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include +#include +#include +#include "amdgpu.h" + +void amdgpu_gem_object_free(struct drm_gem_object *gobj) +{ + struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); + + if (robj) { + if (robj->gem_base.import_attach) + drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); + amdgpu_bo_unref(&robj); + } +} + +int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, + int alignment, u32 initial_domain, + u64 flags, bool kernel, + struct drm_gem_object **obj) +{ + struct amdgpu_bo *robj; + unsigned long max_size; + int r; + + *obj = NULL; + /* At least align on page size */ + if (alignment < PAGE_SIZE) { + alignment = PAGE_SIZE; + } + + if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) { + /* Maximum bo size is the unpinned gtt size since we use the gtt to + * handle vram to system pool migrations. + */ + max_size = adev->mc.gtt_size - adev->gart_pin_size; + if (size > max_size) { + DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", + size >> 20, max_size >> 20); + return -ENOMEM; + } + } +retry: + r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, flags, NULL, &robj); + if (r) { + if (r != -ERESTARTSYS) { + if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { + initial_domain |= AMDGPU_GEM_DOMAIN_GTT; + goto retry; + } + DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", + size, initial_domain, alignment, r); + } + return r; + } + *obj = &robj->gem_base; + robj->pid = task_pid_nr(current); + + mutex_lock(&adev->gem.mutex); + list_add_tail(&robj->list, &adev->gem.objects); + mutex_unlock(&adev->gem.mutex); + + return 0; +} + +int amdgpu_gem_init(struct amdgpu_device *adev) +{ + INIT_LIST_HEAD(&adev->gem.objects); + return 0; +} + +void amdgpu_gem_fini(struct amdgpu_device *adev) +{ + amdgpu_bo_force_delete(adev); +} + +/* + * Call from drm_gem_handle_create which appear in both new and open ioctl + * case. + */ +int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) +{ + struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = rbo->adev; + struct amdgpu_fpriv *fpriv = file_priv->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; + struct amdgpu_bo_va *bo_va; + int r; + + r = amdgpu_bo_reserve(rbo, false); + if (r) { + return r; + } + + bo_va = amdgpu_vm_bo_find(vm, rbo); + if (!bo_va) { + bo_va = amdgpu_vm_bo_add(adev, vm, rbo); + } else { + ++bo_va->ref_count; + } + amdgpu_bo_unreserve(rbo); + + return 0; +} + +void amdgpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file_priv) +{ + struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = rbo->adev; + struct amdgpu_fpriv *fpriv = file_priv->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; + struct amdgpu_bo_va *bo_va; + int r; + + r = amdgpu_bo_reserve(rbo, true); + if (r) { + dev_err(adev->dev, "leaking bo va because " + "we fail to reserve bo (%d)\n", r); + return; + } + bo_va = amdgpu_vm_bo_find(vm, rbo); + if (bo_va) { + if (--bo_va->ref_count == 0) { + amdgpu_vm_bo_rmv(adev, bo_va); + } + } + amdgpu_bo_unreserve(rbo); +} + +static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) +{ + if (r == -EDEADLK) { + r = amdgpu_gpu_reset(adev); + if (!r) + r = -EAGAIN; + } + return r; +} + +/* + * GEM ioctls. + */ +int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct amdgpu_device *adev = dev->dev_private; + union drm_amdgpu_gem_create *args = data; + uint64_t size = args->in.bo_size; + struct drm_gem_object *gobj; + uint32_t handle; + bool kernel = false; + int r; + + down_read(&adev->exclusive_lock); + /* create a gem object to contain this object in */ + if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | + AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { + kernel = true; + if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) + size = size << AMDGPU_GDS_SHIFT; + else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) + size = size << AMDGPU_GWS_SHIFT; + else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) + size = size << AMDGPU_OA_SHIFT; + else { + r = -EINVAL; + goto error_unlock; + } + } + size = roundup(size, PAGE_SIZE); + + r = amdgpu_gem_object_create(adev, size, args->in.alignment, + (u32)(0xffffffff & args->in.domains), + args->in.domain_flags, + kernel, &gobj); + if (r) + goto error_unlock; + + r = drm_gem_handle_create(filp, gobj, &handle); + /* drop reference from allocate - handle holds it now */ + drm_gem_object_unreference_unlocked(gobj); + if (r) + goto error_unlock; + + memset(args, 0, sizeof(*args)); + args->out.handle = handle; + up_read(&adev->exclusive_lock); + return 0; + +error_unlock: + up_read(&adev->exclusive_lock); + r = amdgpu_gem_handle_lockup(adev, r); + return r; +} + +int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct amdgpu_device *adev = dev->dev_private; + struct drm_amdgpu_gem_userptr *args = data; + struct drm_gem_object *gobj; + struct amdgpu_bo *bo; + uint32_t handle; + int r; + + if (offset_in_page(args->addr | args->size)) + return -EINVAL; + + /* reject unknown flag values */ + if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | + AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | + AMDGPU_GEM_USERPTR_REGISTER)) + return -EINVAL; + + if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) || + !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { + + /* if we want to write to it we must require anonymous + memory and install a MMU notifier */ + return -EACCES; + } + + down_read(&adev->exclusive_lock); + + /* create a gem object to contain this object in */ + r = amdgpu_gem_object_create(adev, args->size, 0, + AMDGPU_GEM_DOMAIN_CPU, 0, + 0, &gobj); + if (r) + goto handle_lockup; + + bo = gem_to_amdgpu_bo(gobj); + r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); + if (r) + goto release_object; + + if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { + r = amdgpu_mn_register(bo, args->addr); + if (r) + goto release_object; + } + + if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { + down_read(¤t->mm->mmap_sem); + r = amdgpu_bo_reserve(bo, true); + if (r) { + up_read(¤t->mm->mmap_sem); + goto release_object; + } + + amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); + r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + amdgpu_bo_unreserve(bo); + up_read(¤t->mm->mmap_sem); + if (r) + goto release_object; + } + + r = drm_gem_handle_create(filp, gobj, &handle); + /* drop reference from allocate - handle holds it now */ + drm_gem_object_unreference_unlocked(gobj); + if (r) + goto handle_lockup; + + args->handle = handle; + up_read(&adev->exclusive_lock); + return 0; + +release_object: + drm_gem_object_unreference_unlocked(gobj); + +handle_lockup: + up_read(&adev->exclusive_lock); + r = amdgpu_gem_handle_lockup(adev, r); + + return r; +} + +int amdgpu_mode_dumb_mmap(struct drm_file *filp, + struct drm_device *dev, + uint32_t handle, uint64_t *offset_p) +{ + struct drm_gem_object *gobj; + struct amdgpu_bo *robj; + + gobj = drm_gem_object_lookup(dev, filp, handle); + if (gobj == NULL) { + return -ENOENT; + } + robj = gem_to_amdgpu_bo(gobj); + if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) { + drm_gem_object_unreference_unlocked(gobj); + return -EPERM; + } + *offset_p = amdgpu_bo_mmap_offset(robj); + drm_gem_object_unreference_unlocked(gobj); + return 0; +} + +int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + union drm_amdgpu_gem_mmap *args = data; + uint32_t handle = args->in.handle; + memset(args, 0, sizeof(*args)); + return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); +} + +/** + * amdgpu_gem_timeout - calculate jiffies timeout from absolute value + * + * @timeout_ns: timeout in ns + * + * Calculate the timeout in jiffies from an absolute timeout in ns. + */ +unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) +{ + unsigned long timeout_jiffies; + ktime_t timeout; + + /* clamp timeout if it's to large */ + if (((int64_t)timeout_ns) < 0) + return MAX_SCHEDULE_TIMEOUT; + + timeout = ktime_sub_ns(ktime_get(), timeout_ns); + if (ktime_to_ns(timeout) < 0) + return 0; + + timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); + /* clamp timeout to avoid unsigned-> signed overflow */ + if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) + return MAX_SCHEDULE_TIMEOUT - 1; + + return timeout_jiffies; +} + +int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct amdgpu_device *adev = dev->dev_private; + union drm_amdgpu_gem_wait_idle *args = data; + struct drm_gem_object *gobj; + struct amdgpu_bo *robj; + uint32_t handle = args->in.handle; + unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); + int r = 0; + long ret; + + gobj = drm_gem_object_lookup(dev, filp, handle); + if (gobj == NULL) { + return -ENOENT; + } + robj = gem_to_amdgpu_bo(gobj); + if (timeout == 0) + ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true); + else + ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout); + + /* ret == 0 means not signaled, + * ret > 0 means signaled + * ret < 0 means interrupted before timeout + */ + if (ret >= 0) { + memset(args, 0, sizeof(*args)); + args->out.status = (ret == 0); + } else + r = ret; + + drm_gem_object_unreference_unlocked(gobj); + r = amdgpu_gem_handle_lockup(adev, r); + return r; +} + +int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct drm_amdgpu_gem_metadata *args = data; + struct drm_gem_object *gobj; + struct amdgpu_bo *robj; + int r = -1; + + DRM_DEBUG("%d \n", args->handle); + gobj = drm_gem_object_lookup(dev, filp, args->handle); + if (gobj == NULL) + return -ENOENT; + robj = gem_to_amdgpu_bo(gobj); + + r = amdgpu_bo_reserve(robj, false); + if (unlikely(r != 0)) + goto out; + + if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { + amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); + r = amdgpu_bo_get_metadata(robj, args->data.data, + sizeof(args->data.data), + &args->data.data_size_bytes, + &args->data.flags); + } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { + r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); + if (!r) + r = amdgpu_bo_set_metadata(robj, args->data.data, + args->data.data_size_bytes, + args->data.flags); + } + + amdgpu_bo_unreserve(robj); +out: + drm_gem_object_unreference_unlocked(gobj); + return r; +} + +/** + * amdgpu_gem_va_update_vm -update the bo_va in its VM + * + * @adev: amdgpu_device pointer + * @bo_va: bo_va to update + * + * Update the bo_va directly after setting it's address. Errors are not + * vital here, so they are not reported back to userspace. + */ +static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va) +{ + struct ttm_validate_buffer tv, *entry; + struct amdgpu_bo_list_entry *vm_bos; + struct ww_acquire_ctx ticket; + struct list_head list; + unsigned domain; + int r; + + INIT_LIST_HEAD(&list); + + tv.bo = &bo_va->bo->tbo; + tv.shared = true; + list_add(&tv.head, &list); + + vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list); + if (!vm_bos) + return; + + r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL); + if (r) + goto error_free; + + list_for_each_entry(entry, &list, head) { + domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type); + /* if anything is swapped out don't swap it in here, + just abort and wait for the next CS */ + if (domain == AMDGPU_GEM_DOMAIN_CPU) + goto error_unreserve; + } + + mutex_lock(&bo_va->vm->mutex); + r = amdgpu_vm_clear_freed(adev, bo_va->vm); + if (r) + goto error_unlock; + + r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); + +error_unlock: + mutex_unlock(&bo_va->vm->mutex); + +error_unreserve: + ttm_eu_backoff_reservation(&ticket, &list); + +error_free: + drm_free_large(vm_bos); + + if (r) + DRM_ERROR("Couldn't update BO_VA (%d)\n", r); +} + + + +int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + union drm_amdgpu_gem_va *args = data; + struct drm_gem_object *gobj; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_bo *rbo; + struct amdgpu_bo_va *bo_va; + uint32_t invalid_flags, va_flags = 0; + int r = 0; + + if (!adev->vm_manager.enabled) { + memset(args, 0, sizeof(*args)); + args->out.result = AMDGPU_VA_RESULT_ERROR; + return -ENOTTY; + } + + if (args->in.va_address < AMDGPU_VA_RESERVED_SIZE) { + dev_err(&dev->pdev->dev, + "va_address 0x%lX is in reserved area 0x%X\n", + (unsigned long)args->in.va_address, + AMDGPU_VA_RESERVED_SIZE); + memset(args, 0, sizeof(*args)); + args->out.result = AMDGPU_VA_RESULT_ERROR; + return -EINVAL; + } + + invalid_flags = ~(AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | + AMDGPU_VM_PAGE_EXECUTABLE); + if ((args->in.flags & invalid_flags)) { + dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", + args->in.flags, invalid_flags); + memset(args, 0, sizeof(*args)); + args->out.result = AMDGPU_VA_RESULT_ERROR; + return -EINVAL; + } + + switch (args->in.operation) { + case AMDGPU_VA_OP_MAP: + case AMDGPU_VA_OP_UNMAP: + break; + default: + dev_err(&dev->pdev->dev, "unsupported operation %d\n", + args->in.operation); + memset(args, 0, sizeof(*args)); + args->out.result = AMDGPU_VA_RESULT_ERROR; + return -EINVAL; + } + + gobj = drm_gem_object_lookup(dev, filp, args->in.handle); + if (gobj == NULL) { + memset(args, 0, sizeof(*args)); + args->out.result = AMDGPU_VA_RESULT_ERROR; + return -ENOENT; + } + rbo = gem_to_amdgpu_bo(gobj); + r = amdgpu_bo_reserve(rbo, false); + if (r) { + if (r != -ERESTARTSYS) { + memset(args, 0, sizeof(*args)); + args->out.result = AMDGPU_VA_RESULT_ERROR; + } + drm_gem_object_unreference_unlocked(gobj); + return r; + } + bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); + if (!bo_va) { + memset(args, 0, sizeof(*args)); + args->out.result = AMDGPU_VA_RESULT_ERROR; + drm_gem_object_unreference_unlocked(gobj); + return -ENOENT; + } + + switch (args->in.operation) { + case AMDGPU_VA_OP_MAP: + if (args->in.flags & AMDGPU_VM_PAGE_READABLE) + va_flags |= AMDGPU_PTE_READABLE; + if (args->in.flags & AMDGPU_VM_PAGE_WRITEABLE) + va_flags |= AMDGPU_PTE_WRITEABLE; + if (args->in.flags & AMDGPU_VM_PAGE_EXECUTABLE) + va_flags |= AMDGPU_PTE_EXECUTABLE; + r = amdgpu_vm_bo_map(adev, bo_va, args->in.va_address, 0, + amdgpu_bo_size(bo_va->bo), va_flags); + break; + case AMDGPU_VA_OP_UNMAP: + r = amdgpu_vm_bo_unmap(adev, bo_va, args->in.va_address); + break; + default: + break; + } + + if (!r) { + amdgpu_gem_va_update_vm(adev, bo_va); + memset(args, 0, sizeof(*args)); + args->out.result = AMDGPU_VA_RESULT_OK; + } else { + memset(args, 0, sizeof(*args)); + args->out.result = AMDGPU_VA_RESULT_ERROR; + } + + drm_gem_object_unreference_unlocked(gobj); + return r; +} + +int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct drm_amdgpu_gem_op *args = data; + struct drm_gem_object *gobj; + struct amdgpu_bo *robj; + int r; + + gobj = drm_gem_object_lookup(dev, filp, args->handle); + if (gobj == NULL) { + return -ENOENT; + } + robj = gem_to_amdgpu_bo(gobj); + + r = amdgpu_bo_reserve(robj, false); + if (unlikely(r)) + goto out; + + switch (args->op) { + case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { + struct drm_amdgpu_gem_create_in info; + void __user *out = (void __user *)(long)args->value; + + info.bo_size = robj->gem_base.size; + info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; + info.domains = robj->initial_domain; + info.domain_flags = robj->flags; + if (copy_to_user(out, &info, sizeof(info))) + r = -EFAULT; + break; + } + case AMDGPU_GEM_OP_SET_INITIAL_DOMAIN: + if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) { + r = -EPERM; + break; + } + robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM | + AMDGPU_GEM_DOMAIN_GTT | + AMDGPU_GEM_DOMAIN_CPU); + break; + default: + r = -EINVAL; + } + + amdgpu_bo_unreserve(robj); +out: + drm_gem_object_unreference_unlocked(gobj); + return r; +} + +int amdgpu_mode_dumb_create(struct drm_file *file_priv, + struct drm_device *dev, + struct drm_mode_create_dumb *args) +{ + struct amdgpu_device *adev = dev->dev_private; + struct drm_gem_object *gobj; + uint32_t handle; + int r; + + args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); + args->size = args->pitch * args->height; + args->size = ALIGN(args->size, PAGE_SIZE); + + r = amdgpu_gem_object_create(adev, args->size, 0, + AMDGPU_GEM_DOMAIN_VRAM, + 0, ttm_bo_type_device, + &gobj); + if (r) + return -ENOMEM; + + r = drm_gem_handle_create(file_priv, gobj, &handle); + /* drop reference from allocate - handle holds it now */ + drm_gem_object_unreference_unlocked(gobj); + if (r) { + return r; + } + args->handle = handle; + return 0; +} + +#if defined(CONFIG_DEBUG_FS) +static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_bo *rbo; + unsigned i = 0; + + mutex_lock(&adev->gem.mutex); + list_for_each_entry(rbo, &adev->gem.objects, list) { + unsigned domain; + const char *placement; + + domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type); + switch (domain) { + case AMDGPU_GEM_DOMAIN_VRAM: + placement = "VRAM"; + break; + case AMDGPU_GEM_DOMAIN_GTT: + placement = " GTT"; + break; + case AMDGPU_GEM_DOMAIN_CPU: + default: + placement = " CPU"; + break; + } + seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n", + i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20, + placement, (unsigned long)rbo->pid); + i++; + } + mutex_unlock(&adev->gem.mutex); + return 0; +} + +static struct drm_info_list amdgpu_debugfs_gem_list[] = { + {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, +}; +#endif + +int amdgpu_gem_debugfs_init(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); +#endif + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c new file mode 100644 index 000000000000..9f95da4f0536 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -0,0 +1,72 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include "amdgpu.h" + +/* + * GPU scratch registers helpers function. + */ +/** + * amdgpu_gfx_scratch_get - Allocate a scratch register + * + * @adev: amdgpu_device pointer + * @reg: scratch register mmio offset + * + * Allocate a CP scratch register for use by the driver (all asics). + * Returns 0 on success or -EINVAL on failure. + */ +int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg) +{ + int i; + + for (i = 0; i < adev->gfx.scratch.num_reg; i++) { + if (adev->gfx.scratch.free[i]) { + adev->gfx.scratch.free[i] = false; + *reg = adev->gfx.scratch.reg[i]; + return 0; + } + } + return -EINVAL; +} + +/** + * amdgpu_gfx_scratch_free - Free a scratch register + * + * @adev: amdgpu_device pointer + * @reg: scratch register mmio offset + * + * Free a CP scratch register allocated for use by the driver (all asics) + */ +void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg) +{ + int i; + + for (i = 0; i < adev->gfx.scratch.num_reg; i++) { + if (adev->gfx.scratch.reg[i] == reg) { + adev->gfx.scratch.free[i] = true; + return; + } + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h new file mode 100644 index 000000000000..dc06cbda7be6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -0,0 +1,30 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_GFX_H__ +#define __AMDGPU_GFX_H__ + +int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); +void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c new file mode 100644 index 000000000000..31a676376d73 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c @@ -0,0 +1,395 @@ +/* + * Copyright 2007-8 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + */ +#include + +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_i2c.h" +#include "amdgpu_atombios.h" +#include "atom.h" +#include "atombios_dp.h" +#include "atombios_i2c.h" + +/* bit banging i2c */ +static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap) +{ + struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); + struct amdgpu_device *adev = i2c->dev->dev_private; + struct amdgpu_i2c_bus_rec *rec = &i2c->rec; + uint32_t temp; + + mutex_lock(&i2c->mutex); + + /* switch the pads to ddc mode */ + if (rec->hw_capable) { + temp = RREG32(rec->mask_clk_reg); + temp &= ~(1 << 16); + WREG32(rec->mask_clk_reg, temp); + } + + /* clear the output pin values */ + temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; + WREG32(rec->a_clk_reg, temp); + + temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; + WREG32(rec->a_data_reg, temp); + + /* set the pins to input */ + temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; + WREG32(rec->en_clk_reg, temp); + + temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; + WREG32(rec->en_data_reg, temp); + + /* mask the gpio pins for software use */ + temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; + WREG32(rec->mask_clk_reg, temp); + temp = RREG32(rec->mask_clk_reg); + + temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; + WREG32(rec->mask_data_reg, temp); + temp = RREG32(rec->mask_data_reg); + + return 0; +} + +static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap) +{ + struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); + struct amdgpu_device *adev = i2c->dev->dev_private; + struct amdgpu_i2c_bus_rec *rec = &i2c->rec; + uint32_t temp; + + /* unmask the gpio pins for software use */ + temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; + WREG32(rec->mask_clk_reg, temp); + temp = RREG32(rec->mask_clk_reg); + + temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; + WREG32(rec->mask_data_reg, temp); + temp = RREG32(rec->mask_data_reg); + + mutex_unlock(&i2c->mutex); +} + +static int amdgpu_i2c_get_clock(void *i2c_priv) +{ + struct amdgpu_i2c_chan *i2c = i2c_priv; + struct amdgpu_device *adev = i2c->dev->dev_private; + struct amdgpu_i2c_bus_rec *rec = &i2c->rec; + uint32_t val; + + /* read the value off the pin */ + val = RREG32(rec->y_clk_reg); + val &= rec->y_clk_mask; + + return (val != 0); +} + + +static int amdgpu_i2c_get_data(void *i2c_priv) +{ + struct amdgpu_i2c_chan *i2c = i2c_priv; + struct amdgpu_device *adev = i2c->dev->dev_private; + struct amdgpu_i2c_bus_rec *rec = &i2c->rec; + uint32_t val; + + /* read the value off the pin */ + val = RREG32(rec->y_data_reg); + val &= rec->y_data_mask; + + return (val != 0); +} + +static void amdgpu_i2c_set_clock(void *i2c_priv, int clock) +{ + struct amdgpu_i2c_chan *i2c = i2c_priv; + struct amdgpu_device *adev = i2c->dev->dev_private; + struct amdgpu_i2c_bus_rec *rec = &i2c->rec; + uint32_t val; + + /* set pin direction */ + val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; + val |= clock ? 0 : rec->en_clk_mask; + WREG32(rec->en_clk_reg, val); +} + +static void amdgpu_i2c_set_data(void *i2c_priv, int data) +{ + struct amdgpu_i2c_chan *i2c = i2c_priv; + struct amdgpu_device *adev = i2c->dev->dev_private; + struct amdgpu_i2c_bus_rec *rec = &i2c->rec; + uint32_t val; + + /* set pin direction */ + val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; + val |= data ? 0 : rec->en_data_mask; + WREG32(rec->en_data_reg, val); +} + +static const struct i2c_algorithm amdgpu_atombios_i2c_algo = { + .master_xfer = amdgpu_atombios_i2c_xfer, + .functionality = amdgpu_atombios_i2c_func, +}; + +struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, + struct amdgpu_i2c_bus_rec *rec, + const char *name) +{ + struct amdgpu_i2c_chan *i2c; + int ret; + + /* don't add the mm_i2c bus unless hw_i2c is enabled */ + if (rec->mm_i2c && (amdgpu_hw_i2c == 0)) + return NULL; + + i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL); + if (i2c == NULL) + return NULL; + + i2c->rec = *rec; + i2c->adapter.owner = THIS_MODULE; + i2c->adapter.class = I2C_CLASS_DDC; + i2c->adapter.dev.parent = &dev->pdev->dev; + i2c->dev = dev; + i2c_set_adapdata(&i2c->adapter, i2c); + mutex_init(&i2c->mutex); + if (rec->hw_capable && + amdgpu_hw_i2c) { + /* hw i2c using atom */ + snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), + "AMDGPU i2c hw bus %s", name); + i2c->adapter.algo = &amdgpu_atombios_i2c_algo; + ret = i2c_add_adapter(&i2c->adapter); + if (ret) { + DRM_ERROR("Failed to register hw i2c %s\n", name); + goto out_free; + } + } else { + /* set the amdgpu bit adapter */ + snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), + "AMDGPU i2c bit bus %s", name); + i2c->adapter.algo_data = &i2c->bit; + i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer; + i2c->bit.post_xfer = amdgpu_i2c_post_xfer; + i2c->bit.setsda = amdgpu_i2c_set_data; + i2c->bit.setscl = amdgpu_i2c_set_clock; + i2c->bit.getsda = amdgpu_i2c_get_data; + i2c->bit.getscl = amdgpu_i2c_get_clock; + i2c->bit.udelay = 10; + i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ + i2c->bit.data = i2c; + ret = i2c_bit_add_bus(&i2c->adapter); + if (ret) { + DRM_ERROR("Failed to register bit i2c %s\n", name); + goto out_free; + } + } + + return i2c; +out_free: + kfree(i2c); + return NULL; + +} + +void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c) +{ + if (!i2c) + return; + i2c_del_adapter(&i2c->adapter); + kfree(i2c); +} + +/* Add the default buses */ +void amdgpu_i2c_init(struct amdgpu_device *adev) +{ + if (amdgpu_hw_i2c) + DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); + + if (adev->is_atom_bios) + amdgpu_atombios_i2c_init(adev); +} + +/* remove all the buses */ +void amdgpu_i2c_fini(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { + if (adev->i2c_bus[i]) { + amdgpu_i2c_destroy(adev->i2c_bus[i]); + adev->i2c_bus[i] = NULL; + } + } +} + +/* Add additional buses */ +void amdgpu_i2c_add(struct amdgpu_device *adev, + struct amdgpu_i2c_bus_rec *rec, + const char *name) +{ + struct drm_device *dev = adev->ddev; + int i; + + for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { + if (!adev->i2c_bus[i]) { + adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name); + return; + } + } +} + +/* looks up bus based on id */ +struct amdgpu_i2c_chan * +amdgpu_i2c_lookup(struct amdgpu_device *adev, + struct amdgpu_i2c_bus_rec *i2c_bus) +{ + int i; + + for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { + if (adev->i2c_bus[i] && + (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { + return adev->i2c_bus[i]; + } + } + return NULL; +} + +static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus, + u8 slave_addr, + u8 addr, + u8 *val) +{ + u8 out_buf[2]; + u8 in_buf[2]; + struct i2c_msg msgs[] = { + { + .addr = slave_addr, + .flags = 0, + .len = 1, + .buf = out_buf, + }, + { + .addr = slave_addr, + .flags = I2C_M_RD, + .len = 1, + .buf = in_buf, + } + }; + + out_buf[0] = addr; + out_buf[1] = 0; + + if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { + *val = in_buf[0]; + DRM_DEBUG("val = 0x%02x\n", *val); + } else { + DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", + addr, *val); + } +} + +static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus, + u8 slave_addr, + u8 addr, + u8 val) +{ + uint8_t out_buf[2]; + struct i2c_msg msg = { + .addr = slave_addr, + .flags = 0, + .len = 2, + .buf = out_buf, + }; + + out_buf[0] = addr; + out_buf[1] = val; + + if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) + DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", + addr, val); +} + +/* ddc router switching */ +void +amdgpu_i2c_router_select_ddc_port(struct amdgpu_connector *amdgpu_connector) +{ + u8 val; + + if (!amdgpu_connector->router.ddc_valid) + return; + + if (!amdgpu_connector->router_bus) + return; + + amdgpu_i2c_get_byte(amdgpu_connector->router_bus, + amdgpu_connector->router.i2c_addr, + 0x3, &val); + val &= ~amdgpu_connector->router.ddc_mux_control_pin; + amdgpu_i2c_put_byte(amdgpu_connector->router_bus, + amdgpu_connector->router.i2c_addr, + 0x3, val); + amdgpu_i2c_get_byte(amdgpu_connector->router_bus, + amdgpu_connector->router.i2c_addr, + 0x1, &val); + val &= ~amdgpu_connector->router.ddc_mux_control_pin; + val |= amdgpu_connector->router.ddc_mux_state; + amdgpu_i2c_put_byte(amdgpu_connector->router_bus, + amdgpu_connector->router.i2c_addr, + 0x1, val); +} + +/* clock/data router switching */ +void +amdgpu_i2c_router_select_cd_port(struct amdgpu_connector *amdgpu_connector) +{ + u8 val; + + if (!amdgpu_connector->router.cd_valid) + return; + + if (!amdgpu_connector->router_bus) + return; + + amdgpu_i2c_get_byte(amdgpu_connector->router_bus, + amdgpu_connector->router.i2c_addr, + 0x3, &val); + val &= ~amdgpu_connector->router.cd_mux_control_pin; + amdgpu_i2c_put_byte(amdgpu_connector->router_bus, + amdgpu_connector->router.i2c_addr, + 0x3, val); + amdgpu_i2c_get_byte(amdgpu_connector->router_bus, + amdgpu_connector->router.i2c_addr, + 0x1, &val); + val &= ~amdgpu_connector->router.cd_mux_control_pin; + val |= amdgpu_connector->router.cd_mux_state; + amdgpu_i2c_put_byte(amdgpu_connector->router_bus, + amdgpu_connector->router.i2c_addr, + 0x1, val); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h new file mode 100644 index 000000000000..d81e19b53973 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h @@ -0,0 +1,44 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_I2C_H__ +#define __AMDGPU_I2C_H__ + +struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, + struct amdgpu_i2c_bus_rec *rec, + const char *name); +void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c); +void amdgpu_i2c_init(struct amdgpu_device *adev); +void amdgpu_i2c_fini(struct amdgpu_device *adev); +void amdgpu_i2c_add(struct amdgpu_device *adev, + struct amdgpu_i2c_bus_rec *rec, + const char *name); +struct amdgpu_i2c_chan * +amdgpu_i2c_lookup(struct amdgpu_device *adev, + struct amdgpu_i2c_bus_rec *i2c_bus); +void +amdgpu_i2c_router_select_ddc_port(struct amdgpu_connector *amdgpu_connector); +void +amdgpu_i2c_router_select_cd_port(struct amdgpu_connector *amdgpu_connector); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c new file mode 100644 index 000000000000..847cab2b3fff --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -0,0 +1,345 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + * Christian König + */ +#include +#include +#include +#include +#include "amdgpu.h" +#include "atom.h" + +/* + * IB + * IBs (Indirect Buffers) and areas of GPU accessible memory where + * commands are stored. You can put a pointer to the IB in the + * command ring and the hw will fetch the commands from the IB + * and execute them. Generally userspace acceleration drivers + * produce command buffers which are send to the kernel and + * put in IBs for execution by the requested ring. + */ +static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); + +/** + * amdgpu_ib_get - request an IB (Indirect Buffer) + * + * @ring: ring index the IB is associated with + * @size: requested IB size + * @ib: IB object returned + * + * Request an IB (all asics). IBs are allocated using the + * suballocator. + * Returns 0 on success, error on failure. + */ +int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, + unsigned size, struct amdgpu_ib *ib) +{ + struct amdgpu_device *adev = ring->adev; + int r; + + if (size) { + r = amdgpu_sa_bo_new(adev, &adev->ring_tmp_bo, + &ib->sa_bo, size, 256); + if (r) { + dev_err(adev->dev, "failed to get a new IB (%d)\n", r); + return r; + } + + ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); + + if (!vm) + ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); + else + ib->gpu_addr = 0; + + } else { + ib->sa_bo = NULL; + ib->ptr = NULL; + ib->gpu_addr = 0; + } + + amdgpu_sync_create(&ib->sync); + + ib->ring = ring; + ib->fence = NULL; + ib->user = NULL; + ib->vm = vm; + ib->is_const_ib = false; + ib->gds_base = 0; + ib->gds_size = 0; + ib->gws_base = 0; + ib->gws_size = 0; + ib->oa_base = 0; + ib->oa_size = 0; + + return 0; +} + +/** + * amdgpu_ib_free - free an IB (Indirect Buffer) + * + * @adev: amdgpu_device pointer + * @ib: IB object to free + * + * Free an IB (all asics). + */ +void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib) +{ + amdgpu_sync_free(adev, &ib->sync, ib->fence); + amdgpu_sa_bo_free(adev, &ib->sa_bo, ib->fence); + amdgpu_fence_unref(&ib->fence); +} + +/** + * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring + * + * @adev: amdgpu_device pointer + * @num_ibs: number of IBs to schedule + * @ibs: IB objects to schedule + * @owner: owner for creating the fences + * + * Schedule an IB on the associated ring (all asics). + * Returns 0 on success, error on failure. + * + * On SI, there are two parallel engines fed from the primary ring, + * the CE (Constant Engine) and the DE (Drawing Engine). Since + * resource descriptors have moved to memory, the CE allows you to + * prime the caches while the DE is updating register state so that + * the resource descriptors will be already in cache when the draw is + * processed. To accomplish this, the userspace driver submits two + * IBs, one for the CE and one for the DE. If there is a CE IB (called + * a CONST_IB), it will be put on the ring prior to the DE IB. Prior + * to SI there was just a DE IB. + */ +int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, + struct amdgpu_ib *ibs, void *owner) +{ + struct amdgpu_ring *ring; + struct amdgpu_vm *vm = ibs->vm; + struct amdgpu_ib *ib = &ibs[0]; + unsigned i; + int r = 0; + bool flush_hdp = true; + + if (num_ibs == 0) + return -EINVAL; + + ring = ibs->ring; + if (!ring->ready) { + dev_err(adev->dev, "couldn't schedule ib\n"); + return -EINVAL; + } + + r = amdgpu_ring_lock(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs); + if (r) { + dev_err(adev->dev, "scheduling IB failed (%d).\n", r); + return r; + } + + if (vm) { + /* grab a vm id if necessary */ + struct amdgpu_fence *vm_id_fence = NULL; + vm_id_fence = amdgpu_vm_grab_id(ibs->ring, ibs->vm); + amdgpu_sync_fence(&ibs->sync, vm_id_fence); + } + + r = amdgpu_sync_rings(&ibs->sync, ring); + if (r) { + amdgpu_ring_unlock_undo(ring); + dev_err(adev->dev, "failed to sync rings (%d)\n", r); + return r; + } + + if (vm) { + /* do context switch */ + amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update); + } + + if (ring->funcs->emit_gds_switch && ib->vm && ib->gds_needed) + amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id, + ib->gds_base, ib->gds_size, + ib->gws_base, ib->gws_size, + ib->oa_base, ib->oa_size); + + for (i = 0; i < num_ibs; ++i) { + ib = &ibs[i]; + + if (ib->ring != ring) { + amdgpu_ring_unlock_undo(ring); + return -EINVAL; + } + ib->flush_hdp_writefifo = flush_hdp; + flush_hdp = false; + amdgpu_ring_emit_ib(ring, ib); + } + + r = amdgpu_fence_emit(ring, owner, &ib->fence); + if (r) { + dev_err(adev->dev, "failed to emit fence (%d)\n", r); + amdgpu_ring_unlock_undo(ring); + return r; + } + + /* wrap the last IB with fence */ + if (ib->user) { + uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); + addr += ib->user->offset; + amdgpu_ring_emit_fence(ring, addr, ib->fence->seq, true); + } + + if (ib->vm) + amdgpu_vm_fence(adev, ib->vm, ib->fence); + + amdgpu_ring_unlock_commit(ring); + return 0; +} + +/** + * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool + * + * @adev: amdgpu_device pointer + * + * Initialize the suballocator to manage a pool of memory + * for use as IBs (all asics). + * Returns 0 on success, error on failure. + */ +int amdgpu_ib_pool_init(struct amdgpu_device *adev) +{ + int r; + + if (adev->ib_pool_ready) { + return 0; + } + r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, + AMDGPU_IB_POOL_SIZE*64*1024, + AMDGPU_GPU_PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT); + if (r) { + return r; + } + + r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); + if (r) { + return r; + } + + adev->ib_pool_ready = true; + if (amdgpu_debugfs_sa_init(adev)) { + dev_err(adev->dev, "failed to register debugfs file for SA\n"); + } + return 0; +} + +/** + * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool + * + * @adev: amdgpu_device pointer + * + * Tear down the suballocator managing the pool of memory + * for use as IBs (all asics). + */ +void amdgpu_ib_pool_fini(struct amdgpu_device *adev) +{ + if (adev->ib_pool_ready) { + amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); + amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); + adev->ib_pool_ready = false; + } +} + +/** + * amdgpu_ib_ring_tests - test IBs on the rings + * + * @adev: amdgpu_device pointer + * + * Test an IB (Indirect Buffer) on each ring. + * If the test fails, disable the ring. + * Returns 0 on success, error if the primary GFX ring + * IB test fails. + */ +int amdgpu_ib_ring_tests(struct amdgpu_device *adev) +{ + unsigned i; + int r; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !ring->ready) + continue; + + r = amdgpu_ring_test_ib(ring); + if (r) { + ring->ready = false; + adev->needs_reset = false; + + if (ring == &adev->gfx.gfx_ring[0]) { + /* oh, oh, that's really bad */ + DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); + adev->accel_working = false; + return r; + + } else { + /* still not good, but we can live with it */ + DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); + } + } + } + return 0; +} + +/* + * Debugfs info + */ +#if defined(CONFIG_DEBUG_FS) + +static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + + amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); + + return 0; + +} + +static struct drm_info_list amdgpu_debugfs_sa_list[] = { + {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, +}; + +#endif + +static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); +#else + return 0; +#endif +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c new file mode 100644 index 000000000000..db5422e65ec5 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -0,0 +1,216 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "amdgpu.h" +#include "amdgpu_ih.h" + +/** + * amdgpu_ih_ring_alloc - allocate memory for the IH ring + * + * @adev: amdgpu_device pointer + * + * Allocate a ring buffer for the interrupt controller. + * Returns 0 for success, errors for failure. + */ +static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev) +{ + int r; + + /* Allocate ring buffer */ + if (adev->irq.ih.ring_obj == NULL) { + r = amdgpu_bo_create(adev, adev->irq.ih.ring_size, + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, + NULL, &adev->irq.ih.ring_obj); + if (r) { + DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r); + return r; + } + r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false); + if (unlikely(r != 0)) + return r; + r = amdgpu_bo_pin(adev->irq.ih.ring_obj, + AMDGPU_GEM_DOMAIN_GTT, + &adev->irq.ih.gpu_addr); + if (r) { + amdgpu_bo_unreserve(adev->irq.ih.ring_obj); + DRM_ERROR("amdgpu: failed to pin ih ring buffer (%d).\n", r); + return r; + } + r = amdgpu_bo_kmap(adev->irq.ih.ring_obj, + (void **)&adev->irq.ih.ring); + amdgpu_bo_unreserve(adev->irq.ih.ring_obj); + if (r) { + DRM_ERROR("amdgpu: failed to map ih ring buffer (%d).\n", r); + return r; + } + } + return 0; +} + +/** + * amdgpu_ih_ring_init - initialize the IH state + * + * @adev: amdgpu_device pointer + * + * Initializes the IH state and allocates a buffer + * for the IH ring buffer. + * Returns 0 for success, errors for failure. + */ +int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size, + bool use_bus_addr) +{ + u32 rb_bufsz; + int r; + + /* Align ring size */ + rb_bufsz = order_base_2(ring_size / 4); + ring_size = (1 << rb_bufsz) * 4; + adev->irq.ih.ring_size = ring_size; + adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1; + adev->irq.ih.rptr = 0; + adev->irq.ih.use_bus_addr = use_bus_addr; + + if (adev->irq.ih.use_bus_addr) { + if (!adev->irq.ih.ring) { + /* add 8 bytes for the rptr/wptr shadows and + * add them to the end of the ring allocation. + */ + adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL); + if (adev->irq.ih.ring == NULL) + return -ENOMEM; + adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev, + (void *)adev->irq.ih.ring, + adev->irq.ih.ring_size, + PCI_DMA_BIDIRECTIONAL); + if (pci_dma_mapping_error(adev->pdev, adev->irq.ih.rb_dma_addr)) { + dev_err(&adev->pdev->dev, "Failed to DMA MAP the IH RB page\n"); + kfree((void *)adev->irq.ih.ring); + return -ENOMEM; + } + adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0; + adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1; + } + return 0; + } else { + r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs); + if (r) { + dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r); + return r; + } + + r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs); + if (r) { + amdgpu_wb_free(adev, adev->irq.ih.wptr_offs); + dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r); + return r; + } + + return amdgpu_ih_ring_alloc(adev); + } +} + +/** + * amdgpu_ih_ring_fini - tear down the IH state + * + * @adev: amdgpu_device pointer + * + * Tears down the IH state and frees buffer + * used for the IH ring buffer. + */ +void amdgpu_ih_ring_fini(struct amdgpu_device *adev) +{ + int r; + + if (adev->irq.ih.use_bus_addr) { + if (adev->irq.ih.ring) { + /* add 8 bytes for the rptr/wptr shadows and + * add them to the end of the ring allocation. + */ + pci_unmap_single(adev->pdev, adev->irq.ih.rb_dma_addr, + adev->irq.ih.ring_size + 8, PCI_DMA_BIDIRECTIONAL); + kfree((void *)adev->irq.ih.ring); + adev->irq.ih.ring = NULL; + } + } else { + if (adev->irq.ih.ring_obj) { + r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false); + if (likely(r == 0)) { + amdgpu_bo_kunmap(adev->irq.ih.ring_obj); + amdgpu_bo_unpin(adev->irq.ih.ring_obj); + amdgpu_bo_unreserve(adev->irq.ih.ring_obj); + } + amdgpu_bo_unref(&adev->irq.ih.ring_obj); + adev->irq.ih.ring = NULL; + adev->irq.ih.ring_obj = NULL; + } + amdgpu_wb_free(adev, adev->irq.ih.wptr_offs); + amdgpu_wb_free(adev, adev->irq.ih.rptr_offs); + } +} + +/** + * amdgpu_ih_process - interrupt handler + * + * @adev: amdgpu_device pointer + * + * Interrupt hander (VI), walk the IH ring. + * Returns irq process return code. + */ +int amdgpu_ih_process(struct amdgpu_device *adev) +{ + struct amdgpu_iv_entry entry; + u32 wptr; + + if (!adev->irq.ih.enabled || adev->shutdown) + return IRQ_NONE; + + wptr = amdgpu_ih_get_wptr(adev); + +restart_ih: + /* is somebody else already processing irqs? */ + if (atomic_xchg(&adev->irq.ih.lock, 1)) + return IRQ_NONE; + + DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr); + + /* Order reading of wptr vs. reading of IH ring data */ + rmb(); + + while (adev->irq.ih.rptr != wptr) { + amdgpu_ih_decode_iv(adev, &entry); + adev->irq.ih.rptr &= adev->irq.ih.ptr_mask; + + amdgpu_irq_dispatch(adev, &entry); + } + amdgpu_ih_set_rptr(adev); + atomic_set(&adev->irq.ih.lock, 0); + + /* make sure wptr hasn't changed while processing */ + wptr = amdgpu_ih_get_wptr(adev); + if (wptr != adev->irq.ih.rptr) + goto restart_ih; + + return IRQ_HANDLED; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h new file mode 100644 index 000000000000..c62b09e555d6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -0,0 +1,62 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_IH_H__ +#define __AMDGPU_IH_H__ + +struct amdgpu_device; + +/* + * R6xx+ IH ring + */ +struct amdgpu_ih_ring { + struct amdgpu_bo *ring_obj; + volatile uint32_t *ring; + unsigned rptr; + unsigned ring_size; + uint64_t gpu_addr; + uint32_t ptr_mask; + atomic_t lock; + bool enabled; + unsigned wptr_offs; + unsigned rptr_offs; + u32 doorbell_index; + bool use_doorbell; + bool use_bus_addr; + dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */ +}; + +struct amdgpu_iv_entry { + unsigned src_id; + unsigned src_data; + unsigned ring_id; + unsigned vm_id; + unsigned pas_id; +}; + +int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size, + bool use_bus_addr); +void amdgpu_ih_ring_fini(struct amdgpu_device *adev); +int amdgpu_ih_process(struct amdgpu_device *adev); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.c new file mode 100644 index 000000000000..26482914dc4b --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.c @@ -0,0 +1,47 @@ +/** + * \file amdgpu_ioc32.c + * + * 32-bit ioctl compatibility routines for the AMDGPU DRM. + * + * \author Paul Mackerras + * + * Copyright (C) Paul Mackerras 2005 + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ +#include + +#include +#include +#include "amdgpu_drv.h" + +long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + unsigned int nr = DRM_IOCTL_NR(cmd); + int ret; + + if (nr < DRM_COMMAND_BASE) + return drm_compat_ioctl(filp, cmd, arg); + + ret = amdgpu_drm_ioctl(filp, cmd, arg); + + return ret; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c new file mode 100644 index 000000000000..2187960baf7c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -0,0 +1,456 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_ih.h" +#include "atom.h" +#include "amdgpu_connectors.h" + +#include + +#define AMDGPU_WAIT_IDLE_TIMEOUT 200 + +/* + * Handle hotplug events outside the interrupt handler proper. + */ +/** + * amdgpu_hotplug_work_func - display hotplug work handler + * + * @work: work struct + * + * This is the hot plug event work handler (all asics). + * The work gets scheduled from the irq handler if there + * was a hot plug interrupt. It walks the connector table + * and calls the hotplug handler for each one, then sends + * a drm hotplug event to alert userspace. + */ +static void amdgpu_hotplug_work_func(struct work_struct *work) +{ + struct amdgpu_device *adev = container_of(work, struct amdgpu_device, + hotplug_work); + struct drm_device *dev = adev->ddev; + struct drm_mode_config *mode_config = &dev->mode_config; + struct drm_connector *connector; + + if (mode_config->num_connector) { + list_for_each_entry(connector, &mode_config->connector_list, head) + amdgpu_connector_hotplug(connector); + } + /* Just fire off a uevent and let userspace tell us what to do */ + drm_helper_hpd_irq_event(dev); +} + +/** + * amdgpu_irq_reset_work_func - execute gpu reset + * + * @work: work struct + * + * Execute scheduled gpu reset (cayman+). + * This function is called when the irq handler + * thinks we need a gpu reset. + */ +static void amdgpu_irq_reset_work_func(struct work_struct *work) +{ + struct amdgpu_device *adev = container_of(work, struct amdgpu_device, + reset_work); + + amdgpu_gpu_reset(adev); +} + +/* Disable *all* interrupts */ +static void amdgpu_irq_disable_all(struct amdgpu_device *adev) +{ + unsigned long irqflags; + unsigned i, j; + int r; + + spin_lock_irqsave(&adev->irq.lock, irqflags); + for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) { + struct amdgpu_irq_src *src = adev->irq.sources[i]; + + if (!src || !src->funcs->set || !src->num_types) + continue; + + for (j = 0; j < src->num_types; ++j) { + atomic_set(&src->enabled_types[j], 0); + r = src->funcs->set(adev, src, j, + AMDGPU_IRQ_STATE_DISABLE); + if (r) + DRM_ERROR("error disabling interrupt (%d)\n", + r); + } + } + spin_unlock_irqrestore(&adev->irq.lock, irqflags); +} + +/** + * amdgpu_irq_preinstall - drm irq preinstall callback + * + * @dev: drm dev pointer + * + * Gets the hw ready to enable irqs (all asics). + * This function disables all interrupt sources on the GPU. + */ +void amdgpu_irq_preinstall(struct drm_device *dev) +{ + struct amdgpu_device *adev = dev->dev_private; + + /* Disable *all* interrupts */ + amdgpu_irq_disable_all(adev); + /* Clear bits */ + amdgpu_ih_process(adev); +} + +/** + * amdgpu_irq_postinstall - drm irq preinstall callback + * + * @dev: drm dev pointer + * + * Handles stuff to be done after enabling irqs (all asics). + * Returns 0 on success. + */ +int amdgpu_irq_postinstall(struct drm_device *dev) +{ + dev->max_vblank_count = 0x001fffff; + return 0; +} + +/** + * amdgpu_irq_uninstall - drm irq uninstall callback + * + * @dev: drm dev pointer + * + * This function disables all interrupt sources on the GPU (all asics). + */ +void amdgpu_irq_uninstall(struct drm_device *dev) +{ + struct amdgpu_device *adev = dev->dev_private; + + if (adev == NULL) { + return; + } + amdgpu_irq_disable_all(adev); +} + +/** + * amdgpu_irq_handler - irq handler + * + * @int irq, void *arg: args + * + * This is the irq handler for the amdgpu driver (all asics). + */ +irqreturn_t amdgpu_irq_handler(int irq, void *arg) +{ + struct drm_device *dev = (struct drm_device *) arg; + struct amdgpu_device *adev = dev->dev_private; + irqreturn_t ret; + + ret = amdgpu_ih_process(adev); + if (ret == IRQ_HANDLED) + pm_runtime_mark_last_busy(dev->dev); + return ret; +} + +/** + * amdgpu_msi_ok - asic specific msi checks + * + * @adev: amdgpu device pointer + * + * Handles asic specific MSI checks to determine if + * MSIs should be enabled on a particular chip (all asics). + * Returns true if MSIs should be enabled, false if MSIs + * should not be enabled. + */ +static bool amdgpu_msi_ok(struct amdgpu_device *adev) +{ + /* force MSI on */ + if (amdgpu_msi == 1) + return true; + else if (amdgpu_msi == 0) + return false; + + return true; +} + +/** + * amdgpu_irq_init - init driver interrupt info + * + * @adev: amdgpu device pointer + * + * Sets up the work irq handlers, vblank init, MSIs, etc. (all asics). + * Returns 0 for success, error for failure. + */ +int amdgpu_irq_init(struct amdgpu_device *adev) +{ + int r = 0; + + spin_lock_init(&adev->irq.lock); + r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc); + if (r) { + return r; + } + /* enable msi */ + adev->irq.msi_enabled = false; + + if (amdgpu_msi_ok(adev)) { + int ret = pci_enable_msi(adev->pdev); + if (!ret) { + adev->irq.msi_enabled = true; + dev_info(adev->dev, "amdgpu: using MSI.\n"); + } + } + + INIT_WORK(&adev->hotplug_work, amdgpu_hotplug_work_func); + INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func); + + adev->irq.installed = true; + r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq); + if (r) { + adev->irq.installed = false; + flush_work(&adev->hotplug_work); + return r; + } + + DRM_INFO("amdgpu: irq initialized.\n"); + return 0; +} + +/** + * amdgpu_irq_fini - tear down driver interrupt info + * + * @adev: amdgpu device pointer + * + * Tears down the work irq handlers, vblank handlers, MSIs, etc. (all asics). + */ +void amdgpu_irq_fini(struct amdgpu_device *adev) +{ + unsigned i; + + drm_vblank_cleanup(adev->ddev); + if (adev->irq.installed) { + drm_irq_uninstall(adev->ddev); + adev->irq.installed = false; + if (adev->irq.msi_enabled) + pci_disable_msi(adev->pdev); + flush_work(&adev->hotplug_work); + } + + for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) { + struct amdgpu_irq_src *src = adev->irq.sources[i]; + + if (!src) + continue; + + kfree(src->enabled_types); + src->enabled_types = NULL; + } +} + +/** + * amdgpu_irq_add_id - register irq source + * + * @adev: amdgpu device pointer + * @src_id: source id for this source + * @source: irq source + * + */ +int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id, + struct amdgpu_irq_src *source) +{ + if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) + return -EINVAL; + + if (adev->irq.sources[src_id] != NULL) + return -EINVAL; + + if (!source->funcs) + return -EINVAL; + + if (source->num_types && !source->enabled_types) { + atomic_t *types; + + types = kcalloc(source->num_types, sizeof(atomic_t), + GFP_KERNEL); + if (!types) + return -ENOMEM; + + source->enabled_types = types; + } + + adev->irq.sources[src_id] = source; + return 0; +} + +/** + * amdgpu_irq_dispatch - dispatch irq to IP blocks + * + * @adev: amdgpu device pointer + * @entry: interrupt vector + * + * Dispatches the irq to the different IP blocks + */ +void amdgpu_irq_dispatch(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry) +{ + unsigned src_id = entry->src_id; + struct amdgpu_irq_src *src; + int r; + + if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) { + DRM_DEBUG("Invalid src_id in IV: %d\n", src_id); + return; + } + + src = adev->irq.sources[src_id]; + if (!src) { + DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id); + return; + } + + r = src->funcs->process(adev, src, entry); + if (r) + DRM_ERROR("error processing interrupt (%d)\n", r); +} + +/** + * amdgpu_irq_update - update hw interrupt state + * + * @adev: amdgpu device pointer + * @src: interrupt src you want to enable + * @type: type of interrupt you want to update + * + * Updates the interrupt state for a specific src (all asics). + */ +int amdgpu_irq_update(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, unsigned type) +{ + unsigned long irqflags; + enum amdgpu_interrupt_state state; + int r; + + spin_lock_irqsave(&adev->irq.lock, irqflags); + + /* we need to determine after taking the lock, otherwise + we might disable just enabled interrupts again */ + if (amdgpu_irq_enabled(adev, src, type)) + state = AMDGPU_IRQ_STATE_ENABLE; + else + state = AMDGPU_IRQ_STATE_DISABLE; + + r = src->funcs->set(adev, src, type, state); + spin_unlock_irqrestore(&adev->irq.lock, irqflags); + return r; +} + +/** + * amdgpu_irq_get - enable interrupt + * + * @adev: amdgpu device pointer + * @src: interrupt src you want to enable + * @type: type of interrupt you want to enable + * + * Enables the interrupt type for a specific src (all asics). + */ +int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, + unsigned type) +{ + if (!adev->ddev->irq_enabled) + return -ENOENT; + + if (type >= src->num_types) + return -EINVAL; + + if (!src->enabled_types || !src->funcs->set) + return -EINVAL; + + if (atomic_inc_return(&src->enabled_types[type]) == 1) + return amdgpu_irq_update(adev, src, type); + + return 0; +} + +bool amdgpu_irq_get_delayed(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type) +{ + if ((type >= src->num_types) || !src->enabled_types) + return false; + return atomic_inc_return(&src->enabled_types[type]) == 1; +} + +/** + * amdgpu_irq_put - disable interrupt + * + * @adev: amdgpu device pointer + * @src: interrupt src you want to disable + * @type: type of interrupt you want to disable + * + * Disables the interrupt type for a specific src (all asics). + */ +int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, + unsigned type) +{ + if (!adev->ddev->irq_enabled) + return -ENOENT; + + if (type >= src->num_types) + return -EINVAL; + + if (!src->enabled_types || !src->funcs->set) + return -EINVAL; + + if (atomic_dec_and_test(&src->enabled_types[type])) + return amdgpu_irq_update(adev, src, type); + + return 0; +} + +/** + * amdgpu_irq_enabled - test if irq is enabled or not + * + * @adev: amdgpu device pointer + * @idx: interrupt src you want to test + * + * Tests if the given interrupt source is enabled or not + */ +bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, + unsigned type) +{ + if (!adev->ddev->irq_enabled) + return false; + + if (type >= src->num_types) + return false; + + if (!src->enabled_types || !src->funcs->set) + return false; + + return !!atomic_read(&src->enabled_types[type]); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h new file mode 100644 index 000000000000..8299795f2b2d --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -0,0 +1,92 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_IRQ_H__ +#define __AMDGPU_IRQ_H__ + +#include "amdgpu_ih.h" + +#define AMDGPU_MAX_IRQ_SRC_ID 0x100 + +struct amdgpu_device; +struct amdgpu_iv_entry; + +enum amdgpu_interrupt_state { + AMDGPU_IRQ_STATE_DISABLE, + AMDGPU_IRQ_STATE_ENABLE, +}; + +struct amdgpu_irq_src { + unsigned num_types; + atomic_t *enabled_types; + const struct amdgpu_irq_src_funcs *funcs; +}; + +/* provided by interrupt generating IP blocks */ +struct amdgpu_irq_src_funcs { + int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source, + unsigned type, enum amdgpu_interrupt_state state); + + int (*process)(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry); +}; + +struct amdgpu_irq { + bool installed; + spinlock_t lock; + /* interrupt sources */ + struct amdgpu_irq_src *sources[AMDGPU_MAX_IRQ_SRC_ID]; + + /* status, etc. */ + bool msi_enabled; /* msi enabled */ + + /* interrupt ring */ + struct amdgpu_ih_ring ih; + const struct amdgpu_ih_funcs *ih_funcs; +}; + +void amdgpu_irq_preinstall(struct drm_device *dev); +int amdgpu_irq_postinstall(struct drm_device *dev); +void amdgpu_irq_uninstall(struct drm_device *dev); +irqreturn_t amdgpu_irq_handler(int irq, void *arg); + +int amdgpu_irq_init(struct amdgpu_device *adev); +void amdgpu_irq_fini(struct amdgpu_device *adev); +int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id, + struct amdgpu_irq_src *source); +void amdgpu_irq_dispatch(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry); +int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src, + unsigned type); +int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, + unsigned type); +bool amdgpu_irq_get_delayed(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type); +int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, + unsigned type); +bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, + unsigned type); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c new file mode 100644 index 000000000000..c271da34998d --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -0,0 +1,674 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include +#include "amdgpu.h" +#include +#include "amdgpu_uvd.h" +#include "amdgpu_vce.h" + +#include +#include +#include + +#if defined(CONFIG_VGA_SWITCHEROO) +bool amdgpu_has_atpx(void); +#else +static inline bool amdgpu_has_atpx(void) { return false; } +#endif + +/** + * amdgpu_driver_unload_kms - Main unload function for KMS. + * + * @dev: drm dev pointer + * + * This is the main unload function for KMS (all asics). + * Returns 0 on success. + */ +int amdgpu_driver_unload_kms(struct drm_device *dev) +{ + struct amdgpu_device *adev = dev->dev_private; + + if (adev == NULL) + return 0; + + if (adev->rmmio == NULL) + goto done_free; + + pm_runtime_get_sync(dev->dev); + + amdgpu_acpi_fini(adev); + + amdgpu_device_fini(adev); + +done_free: + kfree(adev); + dev->dev_private = NULL; + return 0; +} + +/** + * amdgpu_driver_load_kms - Main load function for KMS. + * + * @dev: drm dev pointer + * @flags: device flags + * + * This is the main load function for KMS (all asics). + * Returns 0 on success, error on failure. + */ +int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) +{ + struct amdgpu_device *adev; + int r, acpi_status; + + adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); + if (adev == NULL) { + return -ENOMEM; + } + dev->dev_private = (void *)adev; + + if ((amdgpu_runtime_pm != 0) && + amdgpu_has_atpx() && + ((flags & AMDGPU_IS_APU) == 0)) + flags |= AMDGPU_IS_PX; + + /* amdgpu_device_init should report only fatal error + * like memory allocation failure or iomapping failure, + * or memory manager initialization failure, it must + * properly initialize the GPU MC controller and permit + * VRAM allocation + */ + r = amdgpu_device_init(adev, dev, dev->pdev, flags); + if (r) { + dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); + goto out; + } + + /* Call ACPI methods: require modeset init + * but failure is not fatal + */ + if (!r) { + acpi_status = amdgpu_acpi_init(adev); + if (acpi_status) + dev_dbg(&dev->pdev->dev, + "Error during ACPI methods call\n"); + } + + if (amdgpu_device_is_px(dev)) { + pm_runtime_use_autosuspend(dev->dev); + pm_runtime_set_autosuspend_delay(dev->dev, 5000); + pm_runtime_set_active(dev->dev); + pm_runtime_allow(dev->dev); + pm_runtime_mark_last_busy(dev->dev); + pm_runtime_put_autosuspend(dev->dev); + } + +out: + if (r) + amdgpu_driver_unload_kms(dev); + + + return r; +} + +/* + * Userspace get information ioctl + */ +/** + * amdgpu_info_ioctl - answer a device specific request. + * + * @adev: amdgpu device pointer + * @data: request object + * @filp: drm filp + * + * This function is used to pass device specific parameters to the userspace + * drivers. Examples include: pci device id, pipeline parms, tiling params, + * etc. (all asics). + * Returns 0 on success, -EINVAL on failure. + */ +static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) +{ + struct amdgpu_device *adev = dev->dev_private; + struct drm_amdgpu_info *info = data; + struct amdgpu_mode_info *minfo = &adev->mode_info; + void __user *out = (void __user *)(long)info->return_pointer; + uint32_t size = info->return_size; + struct drm_crtc *crtc; + uint32_t ui32 = 0; + uint64_t ui64 = 0; + int i, found; + + if (!info->return_size || !info->return_pointer) + return -EINVAL; + + switch (info->query) { + case AMDGPU_INFO_ACCEL_WORKING: + ui32 = adev->accel_working; + return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; + case AMDGPU_INFO_CRTC_FROM_ID: + for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { + crtc = (struct drm_crtc *)minfo->crtcs[i]; + if (crtc && crtc->base.id == info->mode_crtc.id) { + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + ui32 = amdgpu_crtc->crtc_id; + found = 1; + break; + } + } + if (!found) { + DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); + return -EINVAL; + } + return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; + case AMDGPU_INFO_HW_IP_INFO: { + struct drm_amdgpu_info_hw_ip ip = {}; + enum amdgpu_ip_block_type type; + uint32_t ring_mask = 0; + + if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) + return -EINVAL; + + switch (info->query_hw_ip.type) { + case AMDGPU_HW_IP_GFX: + type = AMDGPU_IP_BLOCK_TYPE_GFX; + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); + break; + case AMDGPU_HW_IP_COMPUTE: + type = AMDGPU_IP_BLOCK_TYPE_GFX; + for (i = 0; i < adev->gfx.num_compute_rings; i++) + ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); + break; + case AMDGPU_HW_IP_DMA: + type = AMDGPU_IP_BLOCK_TYPE_SDMA; + ring_mask = adev->sdma[0].ring.ready ? 1 : 0; + ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1); + break; + case AMDGPU_HW_IP_UVD: + type = AMDGPU_IP_BLOCK_TYPE_UVD; + ring_mask = adev->uvd.ring.ready ? 1 : 0; + break; + case AMDGPU_HW_IP_VCE: + type = AMDGPU_IP_BLOCK_TYPE_VCE; + for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++) + ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); + break; + default: + return -EINVAL; + } + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (adev->ip_blocks[i].type == type && + adev->ip_block_enabled[i]) { + ip.hw_ip_version_major = adev->ip_blocks[i].major; + ip.hw_ip_version_minor = adev->ip_blocks[i].minor; + ip.capabilities_flags = 0; + ip.available_rings = ring_mask; + break; + } + } + return copy_to_user(out, &ip, + min((size_t)size, sizeof(ip))) ? -EFAULT : 0; + } + case AMDGPU_INFO_HW_IP_COUNT: { + enum amdgpu_ip_block_type type; + uint32_t count = 0; + + switch (info->query_hw_ip.type) { + case AMDGPU_HW_IP_GFX: + type = AMDGPU_IP_BLOCK_TYPE_GFX; + break; + case AMDGPU_HW_IP_COMPUTE: + type = AMDGPU_IP_BLOCK_TYPE_GFX; + break; + case AMDGPU_HW_IP_DMA: + type = AMDGPU_IP_BLOCK_TYPE_SDMA; + break; + case AMDGPU_HW_IP_UVD: + type = AMDGPU_IP_BLOCK_TYPE_UVD; + break; + case AMDGPU_HW_IP_VCE: + type = AMDGPU_IP_BLOCK_TYPE_VCE; + break; + default: + return -EINVAL; + } + + for (i = 0; i < adev->num_ip_blocks; i++) + if (adev->ip_blocks[i].type == type && + adev->ip_block_enabled[i] && + count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) + count++; + + return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; + } + case AMDGPU_INFO_TIMESTAMP: + ui64 = amdgpu_asic_get_gpu_clock_counter(adev); + return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; + case AMDGPU_INFO_FW_VERSION: { + struct drm_amdgpu_info_firmware fw_info; + + /* We only support one instance of each IP block right now. */ + if (info->query_fw.ip_instance != 0) + return -EINVAL; + + switch (info->query_fw.fw_type) { + case AMDGPU_INFO_FW_VCE: + fw_info.ver = adev->vce.fw_version; + fw_info.feature = adev->vce.fb_version; + break; + case AMDGPU_INFO_FW_UVD: + fw_info.ver = 0; + fw_info.feature = 0; + break; + case AMDGPU_INFO_FW_GMC: + fw_info.ver = adev->mc.fw_version; + fw_info.feature = 0; + break; + case AMDGPU_INFO_FW_GFX_ME: + fw_info.ver = adev->gfx.me_fw_version; + fw_info.feature = 0; + break; + case AMDGPU_INFO_FW_GFX_PFP: + fw_info.ver = adev->gfx.pfp_fw_version; + fw_info.feature = 0; + break; + case AMDGPU_INFO_FW_GFX_CE: + fw_info.ver = adev->gfx.ce_fw_version; + fw_info.feature = 0; + break; + case AMDGPU_INFO_FW_GFX_RLC: + fw_info.ver = adev->gfx.rlc_fw_version; + fw_info.feature = 0; + break; + case AMDGPU_INFO_FW_GFX_MEC: + if (info->query_fw.index == 0) + fw_info.ver = adev->gfx.mec_fw_version; + else if (info->query_fw.index == 1) + fw_info.ver = adev->gfx.mec2_fw_version; + else + return -EINVAL; + fw_info.feature = 0; + break; + case AMDGPU_INFO_FW_SMC: + fw_info.ver = adev->pm.fw_version; + fw_info.feature = 0; + break; + case AMDGPU_INFO_FW_SDMA: + if (info->query_fw.index >= 2) + return -EINVAL; + fw_info.ver = adev->sdma[info->query_fw.index].fw_version; + fw_info.feature = 0; + break; + default: + return -EINVAL; + } + return copy_to_user(out, &fw_info, + min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; + } + case AMDGPU_INFO_NUM_BYTES_MOVED: + ui64 = atomic64_read(&adev->num_bytes_moved); + return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; + case AMDGPU_INFO_VRAM_USAGE: + ui64 = atomic64_read(&adev->vram_usage); + return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; + case AMDGPU_INFO_VIS_VRAM_USAGE: + ui64 = atomic64_read(&adev->vram_vis_usage); + return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; + case AMDGPU_INFO_GTT_USAGE: + ui64 = atomic64_read(&adev->gtt_usage); + return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; + case AMDGPU_INFO_GDS_CONFIG: { + struct drm_amdgpu_info_gds gds_info; + + gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; + gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; + gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; + gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; + gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; + gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; + gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; + return copy_to_user(out, &gds_info, + min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; + } + case AMDGPU_INFO_VRAM_GTT: { + struct drm_amdgpu_info_vram_gtt vram_gtt; + + vram_gtt.vram_size = adev->mc.real_vram_size; + vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; + vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size; + vram_gtt.gtt_size = adev->mc.gtt_size; + vram_gtt.gtt_size -= adev->gart_pin_size; + return copy_to_user(out, &vram_gtt, + min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; + } + case AMDGPU_INFO_READ_MMR_REG: { + unsigned n, alloc_size = info->read_mmr_reg.count * 4; + uint32_t *regs; + unsigned se_num = (info->read_mmr_reg.instance >> + AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & + AMDGPU_INFO_MMR_SE_INDEX_MASK; + unsigned sh_num = (info->read_mmr_reg.instance >> + AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & + AMDGPU_INFO_MMR_SH_INDEX_MASK; + + /* set full masks if the userspace set all bits + * in the bitfields */ + if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) + se_num = 0xffffffff; + if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) + sh_num = 0xffffffff; + + regs = kmalloc(alloc_size, GFP_KERNEL); + if (!regs) + return -ENOMEM; + + for (i = 0; i < info->read_mmr_reg.count; i++) + if (amdgpu_asic_read_register(adev, se_num, sh_num, + info->read_mmr_reg.dword_offset + i, + ®s[i])) { + DRM_DEBUG_KMS("unallowed offset %#x\n", + info->read_mmr_reg.dword_offset + i); + kfree(regs); + return -EFAULT; + } + n = copy_to_user(out, regs, min(size, alloc_size)); + kfree(regs); + return n ? -EFAULT : 0; + } + case AMDGPU_INFO_DEV_INFO: { + struct drm_amdgpu_info_device dev_info; + struct amdgpu_cu_info cu_info; + + dev_info.device_id = dev->pdev->device; + dev_info.chip_rev = adev->rev_id; + dev_info.external_rev = adev->external_rev_id; + dev_info.pci_rev = dev->pdev->revision; + dev_info.family = adev->family; + dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; + dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; + /* return all clocks in KHz */ + dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; + if (adev->pm.dpm_enabled) + dev_info.max_engine_clock = + adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; + else + dev_info.max_engine_clock = adev->pm.default_sclk * 10; + dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; + dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * + adev->gfx.config.max_shader_engines; + dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; + dev_info._pad = 0; + dev_info.ids_flags = 0; + if (adev->flags & AMDGPU_IS_APU) + dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; + dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; + dev_info.virtual_address_alignment = max(PAGE_SIZE, 0x10000UL); + dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * + AMDGPU_GPU_PAGE_SIZE; + dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; + + amdgpu_asic_get_cu_info(adev, &cu_info); + dev_info.cu_active_number = cu_info.number; + dev_info.cu_ao_mask = cu_info.ao_cu_mask; + memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap)); + + return copy_to_user(out, &dev_info, + min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; + } + default: + DRM_DEBUG_KMS("Invalid request %d\n", info->query); + return -EINVAL; + } + return 0; +} + + +/* + * Outdated mess for old drm with Xorg being in charge (void function now). + */ +/** + * amdgpu_driver_firstopen_kms - drm callback for last close + * + * @dev: drm dev pointer + * + * Switch vga switcheroo state after last close (all asics). + */ +void amdgpu_driver_lastclose_kms(struct drm_device *dev) +{ + vga_switcheroo_process_delayed_switch(); +} + +/** + * amdgpu_driver_open_kms - drm callback for open + * + * @dev: drm dev pointer + * @file_priv: drm file + * + * On device open, init vm on cayman+ (all asics). + * Returns 0 on success, error on failure. + */ +int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) +{ + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_fpriv *fpriv; + int r; + + file_priv->driver_priv = NULL; + + r = pm_runtime_get_sync(dev->dev); + if (r < 0) + return r; + + fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); + if (unlikely(!fpriv)) + return -ENOMEM; + + r = amdgpu_vm_init(adev, &fpriv->vm); + if (r) + goto error_free; + + mutex_init(&fpriv->bo_list_lock); + idr_init(&fpriv->bo_list_handles); + + /* init context manager */ + mutex_init(&fpriv->ctx_mgr.hlock); + idr_init(&fpriv->ctx_mgr.ctx_handles); + fpriv->ctx_mgr.adev = adev; + + file_priv->driver_priv = fpriv; + + pm_runtime_mark_last_busy(dev->dev); + pm_runtime_put_autosuspend(dev->dev); + return 0; + +error_free: + kfree(fpriv); + + return r; +} + +/** + * amdgpu_driver_postclose_kms - drm callback for post close + * + * @dev: drm dev pointer + * @file_priv: drm file + * + * On device post close, tear down vm on cayman+ (all asics). + */ +void amdgpu_driver_postclose_kms(struct drm_device *dev, + struct drm_file *file_priv) +{ + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_fpriv *fpriv = file_priv->driver_priv; + struct amdgpu_bo_list *list; + int handle; + + if (!fpriv) + return; + + amdgpu_vm_fini(adev, &fpriv->vm); + + idr_for_each_entry(&fpriv->bo_list_handles, list, handle) + amdgpu_bo_list_free(list); + + idr_destroy(&fpriv->bo_list_handles); + mutex_destroy(&fpriv->bo_list_lock); + + /* release context */ + amdgpu_ctx_fini(fpriv); + + kfree(fpriv); + file_priv->driver_priv = NULL; +} + +/** + * amdgpu_driver_preclose_kms - drm callback for pre close + * + * @dev: drm dev pointer + * @file_priv: drm file + * + * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx + * (all asics). + */ +void amdgpu_driver_preclose_kms(struct drm_device *dev, + struct drm_file *file_priv) +{ + struct amdgpu_device *adev = dev->dev_private; + + amdgpu_uvd_free_handles(adev, file_priv); + amdgpu_vce_free_handles(adev, file_priv); +} + +/* + * VBlank related functions. + */ +/** + * amdgpu_get_vblank_counter_kms - get frame count + * + * @dev: drm dev pointer + * @crtc: crtc to get the frame count from + * + * Gets the frame count on the requested crtc (all asics). + * Returns frame count on success, -EINVAL on failure. + */ +u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc) +{ + struct amdgpu_device *adev = dev->dev_private; + + if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { + DRM_ERROR("Invalid crtc %d\n", crtc); + return -EINVAL; + } + + return amdgpu_display_vblank_get_counter(adev, crtc); +} + +/** + * amdgpu_enable_vblank_kms - enable vblank interrupt + * + * @dev: drm dev pointer + * @crtc: crtc to enable vblank interrupt for + * + * Enable the interrupt on the requested crtc (all asics). + * Returns 0 on success, -EINVAL on failure. + */ +int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc) +{ + struct amdgpu_device *adev = dev->dev_private; + int idx = amdgpu_crtc_idx_to_irq_type(adev, crtc); + + return amdgpu_irq_get(adev, &adev->crtc_irq, idx); +} + +/** + * amdgpu_disable_vblank_kms - disable vblank interrupt + * + * @dev: drm dev pointer + * @crtc: crtc to disable vblank interrupt for + * + * Disable the interrupt on the requested crtc (all asics). + */ +void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc) +{ + struct amdgpu_device *adev = dev->dev_private; + int idx = amdgpu_crtc_idx_to_irq_type(adev, crtc); + + amdgpu_irq_put(adev, &adev->crtc_irq, idx); +} + +/** + * amdgpu_get_vblank_timestamp_kms - get vblank timestamp + * + * @dev: drm dev pointer + * @crtc: crtc to get the timestamp for + * @max_error: max error + * @vblank_time: time value + * @flags: flags passed to the driver + * + * Gets the timestamp on the requested crtc based on the + * scanout position. (all asics). + * Returns postive status flags on success, negative error on failure. + */ +int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, + int *max_error, + struct timeval *vblank_time, + unsigned flags) +{ + struct drm_crtc *drmcrtc; + struct amdgpu_device *adev = dev->dev_private; + + if (crtc < 0 || crtc >= dev->num_crtcs) { + DRM_ERROR("Invalid crtc %d\n", crtc); + return -EINVAL; + } + + /* Get associated drm_crtc: */ + drmcrtc = &adev->mode_info.crtcs[crtc]->base; + + /* Helper routine in DRM core does all the work: */ + return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, + vblank_time, flags, + drmcrtc, &drmcrtc->hwmode); +} + +const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + /* KMS */ + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), +}; +int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c new file mode 100644 index 000000000000..e94429185660 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c @@ -0,0 +1,319 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: + * Christian König + */ + +#include +#include +#include +#include +#include + +#include "amdgpu.h" + +struct amdgpu_mn { + /* constant after initialisation */ + struct amdgpu_device *adev; + struct mm_struct *mm; + struct mmu_notifier mn; + + /* only used on destruction */ + struct work_struct work; + + /* protected by adev->mn_lock */ + struct hlist_node node; + + /* objects protected by lock */ + struct mutex lock; + struct rb_root objects; +}; + +struct amdgpu_mn_node { + struct interval_tree_node it; + struct list_head bos; +}; + +/** + * amdgpu_mn_destroy - destroy the rmn + * + * @work: previously sheduled work item + * + * Lazy destroys the notifier from a work item + */ +static void amdgpu_mn_destroy(struct work_struct *work) +{ + struct amdgpu_mn *rmn = container_of(work, struct amdgpu_mn, work); + struct amdgpu_device *adev = rmn->adev; + struct amdgpu_mn_node *node, *next_node; + struct amdgpu_bo *bo, *next_bo; + + mutex_lock(&adev->mn_lock); + mutex_lock(&rmn->lock); + hash_del(&rmn->node); + rbtree_postorder_for_each_entry_safe(node, next_node, &rmn->objects, + it.rb) { + + interval_tree_remove(&node->it, &rmn->objects); + list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) { + bo->mn = NULL; + list_del_init(&bo->mn_list); + } + kfree(node); + } + mutex_unlock(&rmn->lock); + mutex_unlock(&adev->mn_lock); + mmu_notifier_unregister(&rmn->mn, rmn->mm); + kfree(rmn); +} + +/** + * amdgpu_mn_release - callback to notify about mm destruction + * + * @mn: our notifier + * @mn: the mm this callback is about + * + * Shedule a work item to lazy destroy our notifier. + */ +static void amdgpu_mn_release(struct mmu_notifier *mn, + struct mm_struct *mm) +{ + struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn); + INIT_WORK(&rmn->work, amdgpu_mn_destroy); + schedule_work(&rmn->work); +} + +/** + * amdgpu_mn_invalidate_range_start - callback to notify about mm change + * + * @mn: our notifier + * @mn: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * We block for all BOs between start and end to be idle and + * unmap them by move them into system domain again. + */ +static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end) +{ + struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + + /* notification is exclusive, but interval is inclusive */ + end -= 1; + + mutex_lock(&rmn->lock); + + it = interval_tree_iter_first(&rmn->objects, start, end); + while (it) { + struct amdgpu_mn_node *node; + struct amdgpu_bo *bo; + int r; + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, start, end); + + list_for_each_entry(bo, &node->bos, mn_list) { + + r = amdgpu_bo_reserve(bo, true); + if (r) { + DRM_ERROR("(%d) failed to reserve user bo\n", r); + continue; + } + + r = reservation_object_wait_timeout_rcu(bo->tbo.resv, + true, false, MAX_SCHEDULE_TIMEOUT); + if (r) + DRM_ERROR("(%d) failed to wait for user bo\n", r); + + amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); + r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + if (r) + DRM_ERROR("(%d) failed to validate user bo\n", r); + + amdgpu_bo_unreserve(bo); + } + } + + mutex_unlock(&rmn->lock); +} + +static const struct mmu_notifier_ops amdgpu_mn_ops = { + .release = amdgpu_mn_release, + .invalidate_range_start = amdgpu_mn_invalidate_range_start, +}; + +/** + * amdgpu_mn_get - create notifier context + * + * @adev: amdgpu device pointer + * + * Creates a notifier context for current->mm. + */ +static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev) +{ + struct mm_struct *mm = current->mm; + struct amdgpu_mn *rmn; + int r; + + down_write(&mm->mmap_sem); + mutex_lock(&adev->mn_lock); + + hash_for_each_possible(adev->mn_hash, rmn, node, (unsigned long)mm) + if (rmn->mm == mm) + goto release_locks; + + rmn = kzalloc(sizeof(*rmn), GFP_KERNEL); + if (!rmn) { + rmn = ERR_PTR(-ENOMEM); + goto release_locks; + } + + rmn->adev = adev; + rmn->mm = mm; + rmn->mn.ops = &amdgpu_mn_ops; + mutex_init(&rmn->lock); + rmn->objects = RB_ROOT; + + r = __mmu_notifier_register(&rmn->mn, mm); + if (r) + goto free_rmn; + + hash_add(adev->mn_hash, &rmn->node, (unsigned long)mm); + +release_locks: + mutex_unlock(&adev->mn_lock); + up_write(&mm->mmap_sem); + + return rmn; + +free_rmn: + mutex_unlock(&adev->mn_lock); + up_write(&mm->mmap_sem); + kfree(rmn); + + return ERR_PTR(r); +} + +/** + * amdgpu_mn_register - register a BO for notifier updates + * + * @bo: amdgpu buffer object + * @addr: userptr addr we should monitor + * + * Registers an MMU notifier for the given BO at the specified address. + * Returns 0 on success, -ERRNO if anything goes wrong. + */ +int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +{ + unsigned long end = addr + amdgpu_bo_size(bo) - 1; + struct amdgpu_device *adev = bo->adev; + struct amdgpu_mn *rmn; + struct amdgpu_mn_node *node = NULL; + struct list_head bos; + struct interval_tree_node *it; + + rmn = amdgpu_mn_get(adev); + if (IS_ERR(rmn)) + return PTR_ERR(rmn); + + INIT_LIST_HEAD(&bos); + + mutex_lock(&rmn->lock); + + while ((it = interval_tree_iter_first(&rmn->objects, addr, end))) { + kfree(node); + node = container_of(it, struct amdgpu_mn_node, it); + interval_tree_remove(&node->it, &rmn->objects); + addr = min(it->start, addr); + end = max(it->last, end); + list_splice(&node->bos, &bos); + } + + if (!node) { + node = kmalloc(sizeof(struct amdgpu_mn_node), GFP_KERNEL); + if (!node) { + mutex_unlock(&rmn->lock); + return -ENOMEM; + } + } + + bo->mn = rmn; + + node->it.start = addr; + node->it.last = end; + INIT_LIST_HEAD(&node->bos); + list_splice(&bos, &node->bos); + list_add(&bo->mn_list, &node->bos); + + interval_tree_insert(&node->it, &rmn->objects); + + mutex_unlock(&rmn->lock); + + return 0; +} + +/** + * amdgpu_mn_unregister - unregister a BO for notifier updates + * + * @bo: amdgpu buffer object + * + * Remove any registration of MMU notifier updates from the buffer object. + */ +void amdgpu_mn_unregister(struct amdgpu_bo *bo) +{ + struct amdgpu_device *adev = bo->adev; + struct amdgpu_mn *rmn; + struct list_head *head; + + mutex_lock(&adev->mn_lock); + rmn = bo->mn; + if (rmn == NULL) { + mutex_unlock(&adev->mn_lock); + return; + } + + mutex_lock(&rmn->lock); + /* save the next list entry for later */ + head = bo->mn_list.next; + + bo->mn = NULL; + list_del(&bo->mn_list); + + if (list_empty(head)) { + struct amdgpu_mn_node *node; + node = container_of(head, struct amdgpu_mn_node, bos); + interval_tree_remove(&node->it, &rmn->objects); + kfree(node); + } + + mutex_unlock(&rmn->lock); + mutex_unlock(&adev->mn_lock); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h new file mode 100644 index 000000000000..64efe5b52e65 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -0,0 +1,586 @@ +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * Copyright 2008 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Original Authors: + * Kevin E. Martin, Rickard E. Faith, Alan Hourihane + * + * Kernel port Author: Dave Airlie + */ + +#ifndef AMDGPU_MODE_H +#define AMDGPU_MODE_H + +#include +#include +#include +#include +#include +#include +#include +#include + +struct amdgpu_bo; +struct amdgpu_device; +struct amdgpu_encoder; +struct amdgpu_router; +struct amdgpu_hpd; + +#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) +#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) +#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) +#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) + +#define AMDGPU_MAX_HPD_PINS 6 +#define AMDGPU_MAX_CRTCS 6 +#define AMDGPU_MAX_AFMT_BLOCKS 7 + +enum amdgpu_rmx_type { + RMX_OFF, + RMX_FULL, + RMX_CENTER, + RMX_ASPECT +}; + +enum amdgpu_underscan_type { + UNDERSCAN_OFF, + UNDERSCAN_ON, + UNDERSCAN_AUTO, +}; + +#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 +#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 + +enum amdgpu_hpd_id { + AMDGPU_HPD_1 = 0, + AMDGPU_HPD_2, + AMDGPU_HPD_3, + AMDGPU_HPD_4, + AMDGPU_HPD_5, + AMDGPU_HPD_6, + AMDGPU_HPD_LAST, + AMDGPU_HPD_NONE = 0xff, +}; + +enum amdgpu_crtc_irq { + AMDGPU_CRTC_IRQ_VBLANK1 = 0, + AMDGPU_CRTC_IRQ_VBLANK2, + AMDGPU_CRTC_IRQ_VBLANK3, + AMDGPU_CRTC_IRQ_VBLANK4, + AMDGPU_CRTC_IRQ_VBLANK5, + AMDGPU_CRTC_IRQ_VBLANK6, + AMDGPU_CRTC_IRQ_VLINE1, + AMDGPU_CRTC_IRQ_VLINE2, + AMDGPU_CRTC_IRQ_VLINE3, + AMDGPU_CRTC_IRQ_VLINE4, + AMDGPU_CRTC_IRQ_VLINE5, + AMDGPU_CRTC_IRQ_VLINE6, + AMDGPU_CRTC_IRQ_LAST, + AMDGPU_CRTC_IRQ_NONE = 0xff +}; + +enum amdgpu_pageflip_irq { + AMDGPU_PAGEFLIP_IRQ_D1 = 0, + AMDGPU_PAGEFLIP_IRQ_D2, + AMDGPU_PAGEFLIP_IRQ_D3, + AMDGPU_PAGEFLIP_IRQ_D4, + AMDGPU_PAGEFLIP_IRQ_D5, + AMDGPU_PAGEFLIP_IRQ_D6, + AMDGPU_PAGEFLIP_IRQ_LAST, + AMDGPU_PAGEFLIP_IRQ_NONE = 0xff +}; + +enum amdgpu_flip_status { + AMDGPU_FLIP_NONE, + AMDGPU_FLIP_PENDING, + AMDGPU_FLIP_SUBMITTED +}; + +#define AMDGPU_MAX_I2C_BUS 16 + +/* amdgpu gpio-based i2c + * 1. "mask" reg and bits + * grabs the gpio pins for software use + * 0=not held 1=held + * 2. "a" reg and bits + * output pin value + * 0=low 1=high + * 3. "en" reg and bits + * sets the pin direction + * 0=input 1=output + * 4. "y" reg and bits + * input pin value + * 0=low 1=high + */ +struct amdgpu_i2c_bus_rec { + bool valid; + /* id used by atom */ + uint8_t i2c_id; + /* id used by atom */ + enum amdgpu_hpd_id hpd; + /* can be used with hw i2c engine */ + bool hw_capable; + /* uses multi-media i2c engine */ + bool mm_i2c; + /* regs and bits */ + uint32_t mask_clk_reg; + uint32_t mask_data_reg; + uint32_t a_clk_reg; + uint32_t a_data_reg; + uint32_t en_clk_reg; + uint32_t en_data_reg; + uint32_t y_clk_reg; + uint32_t y_data_reg; + uint32_t mask_clk_mask; + uint32_t mask_data_mask; + uint32_t a_clk_mask; + uint32_t a_data_mask; + uint32_t en_clk_mask; + uint32_t en_data_mask; + uint32_t y_clk_mask; + uint32_t y_data_mask; +}; + +#define AMDGPU_MAX_BIOS_CONNECTOR 16 + +/* pll flags */ +#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) +#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) +#define AMDGPU_PLL_USE_REF_DIV (1 << 2) +#define AMDGPU_PLL_LEGACY (1 << 3) +#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) +#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) +#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) +#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) +#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) +#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) +#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) +#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) +#define AMDGPU_PLL_USE_POST_DIV (1 << 12) +#define AMDGPU_PLL_IS_LCD (1 << 13) +#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) + +struct amdgpu_pll { + /* reference frequency */ + uint32_t reference_freq; + + /* fixed dividers */ + uint32_t reference_div; + uint32_t post_div; + + /* pll in/out limits */ + uint32_t pll_in_min; + uint32_t pll_in_max; + uint32_t pll_out_min; + uint32_t pll_out_max; + uint32_t lcd_pll_out_min; + uint32_t lcd_pll_out_max; + uint32_t best_vco; + + /* divider limits */ + uint32_t min_ref_div; + uint32_t max_ref_div; + uint32_t min_post_div; + uint32_t max_post_div; + uint32_t min_feedback_div; + uint32_t max_feedback_div; + uint32_t min_frac_feedback_div; + uint32_t max_frac_feedback_div; + + /* flags for the current clock */ + uint32_t flags; + + /* pll id */ + uint32_t id; +}; + +struct amdgpu_i2c_chan { + struct i2c_adapter adapter; + struct drm_device *dev; + struct i2c_algo_bit_data bit; + struct amdgpu_i2c_bus_rec rec; + struct drm_dp_aux aux; + bool has_aux; + struct mutex mutex; +}; + +struct amdgpu_fbdev; + +struct amdgpu_afmt { + bool enabled; + int offset; + bool last_buffer_filled_status; + int id; + struct amdgpu_audio_pin *pin; +}; + +/* + * Audio + */ +struct amdgpu_audio_pin { + int channels; + int rate; + int bits_per_sample; + u8 status_bits; + u8 category_code; + u32 offset; + bool connected; + u32 id; +}; + +struct amdgpu_audio { + bool enabled; + struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; + int num_pins; +}; + +struct amdgpu_mode_mc_save { + u32 vga_render_control; + u32 vga_hdp_control; + bool crtc_enabled[AMDGPU_MAX_CRTCS]; +}; + +struct amdgpu_display_funcs { + /* vga render */ + void (*set_vga_render_state)(struct amdgpu_device *adev, bool render); + /* display watermarks */ + void (*bandwidth_update)(struct amdgpu_device *adev); + /* get frame count */ + u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); + /* wait for vblank */ + void (*vblank_wait)(struct amdgpu_device *adev, int crtc); + /* is dce hung */ + bool (*is_display_hung)(struct amdgpu_device *adev); + /* set backlight level */ + void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, + u8 level); + /* get backlight level */ + u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); + /* hotplug detect */ + bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); + void (*hpd_set_polarity)(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd); + u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); + /* pageflipping */ + void (*page_flip)(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base); + int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, + u32 *vbl, u32 *position); + /* display topology setup */ + void (*add_encoder)(struct amdgpu_device *adev, + uint32_t encoder_enum, + uint32_t supported_device, + u16 caps); + void (*add_connector)(struct amdgpu_device *adev, + uint32_t connector_id, + uint32_t supported_device, + int connector_type, + struct amdgpu_i2c_bus_rec *i2c_bus, + uint16_t connector_object_id, + struct amdgpu_hpd *hpd, + struct amdgpu_router *router); + void (*stop_mc_access)(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save); + void (*resume_mc_access)(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save); +}; + +struct amdgpu_mode_info { + struct atom_context *atom_context; + struct card_info *atom_card_info; + bool mode_config_initialized; + struct amdgpu_crtc *crtcs[6]; + struct amdgpu_afmt *afmt[7]; + /* DVI-I properties */ + struct drm_property *coherent_mode_property; + /* DAC enable load detect */ + struct drm_property *load_detect_property; + /* underscan */ + struct drm_property *underscan_property; + struct drm_property *underscan_hborder_property; + struct drm_property *underscan_vborder_property; + /* audio */ + struct drm_property *audio_property; + /* FMT dithering */ + struct drm_property *dither_property; + /* hardcoded DFP edid from BIOS */ + struct edid *bios_hardcoded_edid; + int bios_hardcoded_edid_size; + + /* pointer to fbdev info structure */ + struct amdgpu_fbdev *rfbdev; + /* firmware flags */ + u16 firmware_flags; + /* pointer to backlight encoder */ + struct amdgpu_encoder *bl_encoder; + struct amdgpu_audio audio; /* audio stuff */ + int num_crtc; /* number of crtcs */ + int num_hpd; /* number of hpd pins */ + int num_dig; /* number of dig blocks */ + int disp_priority; + const struct amdgpu_display_funcs *funcs; +}; + +#define AMDGPU_MAX_BL_LEVEL 0xFF + +#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) + +struct amdgpu_backlight_privdata { + struct amdgpu_encoder *encoder; + uint8_t negative; +}; + +#endif + +struct amdgpu_atom_ss { + uint16_t percentage; + uint16_t percentage_divider; + uint8_t type; + uint16_t step; + uint8_t delay; + uint8_t range; + uint8_t refdiv; + /* asic_ss */ + uint16_t rate; + uint16_t amount; +}; + +struct amdgpu_crtc { + struct drm_crtc base; + int crtc_id; + u16 lut_r[256], lut_g[256], lut_b[256]; + bool enabled; + bool can_tile; + uint32_t crtc_offset; + struct drm_gem_object *cursor_bo; + uint64_t cursor_addr; + int cursor_width; + int cursor_height; + int max_cursor_width; + int max_cursor_height; + enum amdgpu_rmx_type rmx_type; + u8 h_border; + u8 v_border; + fixed20_12 vsc; + fixed20_12 hsc; + struct drm_display_mode native_mode; + u32 pll_id; + /* page flipping */ + struct workqueue_struct *pflip_queue; + struct amdgpu_flip_work *pflip_works; + enum amdgpu_flip_status pflip_status; + int deferred_flip_completion; + /* pll sharing */ + struct amdgpu_atom_ss ss; + bool ss_enabled; + u32 adjusted_clock; + int bpc; + u32 pll_reference_div; + u32 pll_post_div; + u32 pll_flags; + struct drm_encoder *encoder; + struct drm_connector *connector; + /* for dpm */ + u32 line_time; + u32 wm_low; + u32 wm_high; + struct drm_display_mode hw_mode; +}; + +struct amdgpu_encoder_atom_dig { + bool linkb; + /* atom dig */ + bool coherent_mode; + int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ + /* atom lvds/edp */ + uint32_t lcd_misc; + uint16_t panel_pwr_delay; + uint32_t lcd_ss_id; + /* panel mode */ + struct drm_display_mode native_mode; + struct backlight_device *bl_dev; + int dpms_mode; + uint8_t backlight_level; + int panel_mode; + struct amdgpu_afmt *afmt; +}; + +struct amdgpu_encoder { + struct drm_encoder base; + uint32_t encoder_enum; + uint32_t encoder_id; + uint32_t devices; + uint32_t active_device; + uint32_t flags; + uint32_t pixel_clock; + enum amdgpu_rmx_type rmx_type; + enum amdgpu_underscan_type underscan_type; + uint32_t underscan_hborder; + uint32_t underscan_vborder; + struct drm_display_mode native_mode; + void *enc_priv; + int audio_polling_active; + bool is_ext_encoder; + u16 caps; +}; + +struct amdgpu_connector_atom_dig { + /* displayport */ + u8 dpcd[DP_RECEIVER_CAP_SIZE]; + u8 dp_sink_type; + int dp_clock; + int dp_lane_count; + bool edp_on; +}; + +struct amdgpu_gpio_rec { + bool valid; + u8 id; + u32 reg; + u32 mask; + u32 shift; +}; + +struct amdgpu_hpd { + enum amdgpu_hpd_id hpd; + u8 plugged_state; + struct amdgpu_gpio_rec gpio; +}; + +struct amdgpu_router { + u32 router_id; + struct amdgpu_i2c_bus_rec i2c_info; + u8 i2c_addr; + /* i2c mux */ + bool ddc_valid; + u8 ddc_mux_type; + u8 ddc_mux_control_pin; + u8 ddc_mux_state; + /* clock/data mux */ + bool cd_valid; + u8 cd_mux_type; + u8 cd_mux_control_pin; + u8 cd_mux_state; +}; + +enum amdgpu_connector_audio { + AMDGPU_AUDIO_DISABLE = 0, + AMDGPU_AUDIO_ENABLE = 1, + AMDGPU_AUDIO_AUTO = 2 +}; + +enum amdgpu_connector_dither { + AMDGPU_FMT_DITHER_DISABLE = 0, + AMDGPU_FMT_DITHER_ENABLE = 1, +}; + +struct amdgpu_connector { + struct drm_connector base; + uint32_t connector_id; + uint32_t devices; + struct amdgpu_i2c_chan *ddc_bus; + /* some systems have an hdmi and vga port with a shared ddc line */ + bool shared_ddc; + bool use_digital; + /* we need to mind the EDID between detect + and get modes due to analog/digital/tvencoder */ + struct edid *edid; + void *con_priv; + bool dac_load_detect; + bool detected_by_load; /* if the connection status was determined by load */ + uint16_t connector_object_id; + struct amdgpu_hpd hpd; + struct amdgpu_router router; + struct amdgpu_i2c_chan *router_bus; + enum amdgpu_connector_audio audio; + enum amdgpu_connector_dither dither; + unsigned pixelclock_for_modeset; +}; + +struct amdgpu_framebuffer { + struct drm_framebuffer base; + struct drm_gem_object *obj; +}; + +#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ + ((em) == ATOM_ENCODER_MODE_DP_MST)) + +void amdgpu_link_encoder_connector(struct drm_device *dev); + +struct drm_connector * +amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); +struct drm_connector * +amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); +bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, + u32 pixel_clock); + +u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); +struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); + +bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux); + +void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); + +int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, + unsigned int flags, + int *vpos, int *hpos, ktime_t *stime, + ktime_t *etime); + +int amdgpu_framebuffer_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj); + +int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); + +void amdgpu_enc_destroy(struct drm_encoder *encoder); +void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); +bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); +void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, + struct drm_display_mode *adjusted_mode); +int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); + +/* fbdev layer */ +int amdgpu_fbdev_init(struct amdgpu_device *adev); +void amdgpu_fbdev_fini(struct amdgpu_device *adev); +void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); +int amdgpu_fbdev_total_size(struct amdgpu_device *adev); +bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); + +void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev); + + +int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); + +/* amdgpu_display.c */ +void amdgpu_print_display_setup(struct drm_device *dev); +int amdgpu_modeset_create_props(struct amdgpu_device *adev); +int amdgpu_crtc_set_config(struct drm_mode_set *set); +int amdgpu_crtc_page_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t page_flip_flags); +extern const struct drm_mode_config_funcs amdgpu_mode_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c new file mode 100644 index 000000000000..b51582714c21 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -0,0 +1,646 @@ +/* + * Copyright 2009 Jerome Glisse. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: + * Jerome Glisse + * Thomas Hellstrom + * Dave Airlie + */ +#include +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_trace.h" + + +int amdgpu_ttm_init(struct amdgpu_device *adev); +void amdgpu_ttm_fini(struct amdgpu_device *adev); + +static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev, + struct ttm_mem_reg * mem) +{ + u64 ret = 0; + if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) { + ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) > + adev->mc.visible_vram_size ? + adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT): + mem->size; + } + return ret; +} + +static void amdgpu_update_memory_usage(struct amdgpu_device *adev, + struct ttm_mem_reg *old_mem, + struct ttm_mem_reg *new_mem) +{ + u64 vis_size; + if (!adev) + return; + + if (new_mem) { + switch (new_mem->mem_type) { + case TTM_PL_TT: + atomic64_add(new_mem->size, &adev->gtt_usage); + break; + case TTM_PL_VRAM: + atomic64_add(new_mem->size, &adev->vram_usage); + vis_size = amdgpu_get_vis_part_size(adev, new_mem); + atomic64_add(vis_size, &adev->vram_vis_usage); + break; + } + } + + if (old_mem) { + switch (old_mem->mem_type) { + case TTM_PL_TT: + atomic64_sub(old_mem->size, &adev->gtt_usage); + break; + case TTM_PL_VRAM: + atomic64_sub(old_mem->size, &adev->vram_usage); + vis_size = amdgpu_get_vis_part_size(adev, old_mem); + atomic64_sub(vis_size, &adev->vram_vis_usage); + break; + } + } +} + +static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) +{ + struct amdgpu_bo *bo; + + bo = container_of(tbo, struct amdgpu_bo, tbo); + + amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL); + amdgpu_mn_unregister(bo); + + mutex_lock(&bo->adev->gem.mutex); + list_del_init(&bo->list); + mutex_unlock(&bo->adev->gem.mutex); + drm_gem_object_release(&bo->gem_base); + kfree(bo->metadata); + kfree(bo); +} + +bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) +{ + if (bo->destroy == &amdgpu_ttm_bo_destroy) + return true; + return false; +} + +void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain) +{ + u32 c = 0, i; + rbo->placement.placement = rbo->placements; + rbo->placement.busy_placement = rbo->placements; + + if (domain & AMDGPU_GEM_DOMAIN_VRAM) { + if (rbo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS && + rbo->adev->mc.visible_vram_size < rbo->adev->mc.real_vram_size) { + rbo->placements[c].fpfn = + rbo->adev->mc.visible_vram_size >> PAGE_SHIFT; + rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | + TTM_PL_FLAG_VRAM; + } + rbo->placements[c].fpfn = 0; + rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | + TTM_PL_FLAG_VRAM; + } + + if (domain & AMDGPU_GEM_DOMAIN_GTT) { + if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_UC) { + rbo->placements[c].fpfn = 0; + rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_TT; + } else if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) { + rbo->placements[c].fpfn = 0; + rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT | + TTM_PL_FLAG_UNCACHED; + } else { + rbo->placements[c].fpfn = 0; + rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; + } + } + + if (domain & AMDGPU_GEM_DOMAIN_CPU) { + if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_UC) { + rbo->placements[c].fpfn = 0; + rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_SYSTEM; + } else if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) { + rbo->placements[c].fpfn = 0; + rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM | + TTM_PL_FLAG_UNCACHED; + } else { + rbo->placements[c].fpfn = 0; + rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; + } + } + + if (domain & AMDGPU_GEM_DOMAIN_GDS) { + rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | + AMDGPU_PL_FLAG_GDS; + } + if (domain & AMDGPU_GEM_DOMAIN_GWS) { + rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | + AMDGPU_PL_FLAG_GWS; + } + if (domain & AMDGPU_GEM_DOMAIN_OA) { + rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | + AMDGPU_PL_FLAG_OA; + } + + if (!c) { + rbo->placements[c].fpfn = 0; + rbo->placements[c++].flags = TTM_PL_MASK_CACHING | + TTM_PL_FLAG_SYSTEM; + } + rbo->placement.num_placement = c; + rbo->placement.num_busy_placement = c; + + for (i = 0; i < c; i++) { + if ((rbo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && + (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && + !rbo->placements[i].fpfn) + rbo->placements[i].lpfn = + rbo->adev->mc.visible_vram_size >> PAGE_SHIFT; + else + rbo->placements[i].lpfn = 0; + } + + if (rbo->tbo.mem.size > 512 * 1024) { + for (i = 0; i < c; i++) { + rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN; + } + } +} + +int amdgpu_bo_create(struct amdgpu_device *adev, + unsigned long size, int byte_align, bool kernel, u32 domain, u64 flags, + struct sg_table *sg, struct amdgpu_bo **bo_ptr) +{ + struct amdgpu_bo *bo; + enum ttm_bo_type type; + unsigned long page_align; + size_t acc_size; + int r; + + /* VI has a hw bug where VM PTEs have to be allocated in groups of 8. + * do this as a temporary workaround + */ + if (!(domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) { + if (adev->asic_type >= CHIP_TOPAZ) { + if (byte_align & 0x7fff) + byte_align = ALIGN(byte_align, 0x8000); + if (size & 0x7fff) + size = ALIGN(size, 0x8000); + } + } + + page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; + size = ALIGN(size, PAGE_SIZE); + + if (kernel) { + type = ttm_bo_type_kernel; + } else if (sg) { + type = ttm_bo_type_sg; + } else { + type = ttm_bo_type_device; + } + *bo_ptr = NULL; + + acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, + sizeof(struct amdgpu_bo)); + + bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); + if (bo == NULL) + return -ENOMEM; + r = drm_gem_object_init(adev->ddev, &bo->gem_base, size); + if (unlikely(r)) { + kfree(bo); + return r; + } + bo->adev = adev; + INIT_LIST_HEAD(&bo->list); + INIT_LIST_HEAD(&bo->va); + bo->initial_domain = domain & (AMDGPU_GEM_DOMAIN_VRAM | + AMDGPU_GEM_DOMAIN_GTT | + AMDGPU_GEM_DOMAIN_CPU | + AMDGPU_GEM_DOMAIN_GDS | + AMDGPU_GEM_DOMAIN_GWS | + AMDGPU_GEM_DOMAIN_OA); + + bo->flags = flags; + amdgpu_ttm_placement_from_domain(bo, domain); + /* Kernel allocation are uninterruptible */ + down_read(&adev->pm.mclk_lock); + r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, + &bo->placement, page_align, !kernel, NULL, + acc_size, sg, NULL, &amdgpu_ttm_bo_destroy); + up_read(&adev->pm.mclk_lock); + if (unlikely(r != 0)) { + return r; + } + *bo_ptr = bo; + + trace_amdgpu_bo_create(bo); + + return 0; +} + +int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) +{ + bool is_iomem; + int r; + + if (bo->kptr) { + if (ptr) { + *ptr = bo->kptr; + } + return 0; + } + r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); + if (r) { + return r; + } + bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); + if (ptr) { + *ptr = bo->kptr; + } + return 0; +} + +void amdgpu_bo_kunmap(struct amdgpu_bo *bo) +{ + if (bo->kptr == NULL) + return; + bo->kptr = NULL; + ttm_bo_kunmap(&bo->kmap); +} + +struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) +{ + if (bo == NULL) + return NULL; + + ttm_bo_reference(&bo->tbo); + return bo; +} + +void amdgpu_bo_unref(struct amdgpu_bo **bo) +{ + struct ttm_buffer_object *tbo; + + if ((*bo) == NULL) + return; + + tbo = &((*bo)->tbo); + ttm_bo_unref(&tbo); + if (tbo == NULL) + *bo = NULL; +} + +int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, u64 max_offset, + u64 *gpu_addr) +{ + int r, i; + + if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm)) + return -EPERM; + + if (bo->pin_count) { + bo->pin_count++; + if (gpu_addr) + *gpu_addr = amdgpu_bo_gpu_offset(bo); + + if (max_offset != 0) { + u64 domain_start; + + if (domain == AMDGPU_GEM_DOMAIN_VRAM) + domain_start = bo->adev->mc.vram_start; + else + domain_start = bo->adev->mc.gtt_start; + WARN_ON_ONCE(max_offset < + (amdgpu_bo_gpu_offset(bo) - domain_start)); + } + + return 0; + } + amdgpu_ttm_placement_from_domain(bo, domain); + for (i = 0; i < bo->placement.num_placement; i++) { + /* force to pin into visible video ram */ + if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && + !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && + (!max_offset || max_offset > bo->adev->mc.visible_vram_size)) + bo->placements[i].lpfn = + bo->adev->mc.visible_vram_size >> PAGE_SHIFT; + else + bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; + + bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; + } + + r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + if (likely(r == 0)) { + bo->pin_count = 1; + if (gpu_addr != NULL) + *gpu_addr = amdgpu_bo_gpu_offset(bo); + if (domain == AMDGPU_GEM_DOMAIN_VRAM) + bo->adev->vram_pin_size += amdgpu_bo_size(bo); + else + bo->adev->gart_pin_size += amdgpu_bo_size(bo); + } else { + dev_err(bo->adev->dev, "%p pin failed\n", bo); + } + return r; +} + +int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) +{ + return amdgpu_bo_pin_restricted(bo, domain, 0, gpu_addr); +} + +int amdgpu_bo_unpin(struct amdgpu_bo *bo) +{ + int r, i; + + if (!bo->pin_count) { + dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo); + return 0; + } + bo->pin_count--; + if (bo->pin_count) + return 0; + for (i = 0; i < bo->placement.num_placement; i++) { + bo->placements[i].lpfn = 0; + bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; + } + r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + if (likely(r == 0)) { + if (bo->tbo.mem.mem_type == TTM_PL_VRAM) + bo->adev->vram_pin_size -= amdgpu_bo_size(bo); + else + bo->adev->gart_pin_size -= amdgpu_bo_size(bo); + } else { + dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo); + } + return r; +} + +int amdgpu_bo_evict_vram(struct amdgpu_device *adev) +{ + /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ + if (0 && (adev->flags & AMDGPU_IS_APU)) { + /* Useless to evict on IGP chips */ + return 0; + } + return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); +} + +void amdgpu_bo_force_delete(struct amdgpu_device *adev) +{ + struct amdgpu_bo *bo, *n; + + if (list_empty(&adev->gem.objects)) { + return; + } + dev_err(adev->dev, "Userspace still has active objects !\n"); + list_for_each_entry_safe(bo, n, &adev->gem.objects, list) { + mutex_lock(&adev->ddev->struct_mutex); + dev_err(adev->dev, "%p %p %lu %lu force free\n", + &bo->gem_base, bo, (unsigned long)bo->gem_base.size, + *((unsigned long *)&bo->gem_base.refcount)); + mutex_lock(&bo->adev->gem.mutex); + list_del_init(&bo->list); + mutex_unlock(&bo->adev->gem.mutex); + /* this should unref the ttm bo */ + drm_gem_object_unreference(&bo->gem_base); + mutex_unlock(&adev->ddev->struct_mutex); + } +} + +int amdgpu_bo_init(struct amdgpu_device *adev) +{ + /* Add an MTRR for the VRAM */ + adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, + adev->mc.aper_size); + DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", + adev->mc.mc_vram_size >> 20, + (unsigned long long)adev->mc.aper_size >> 20); + DRM_INFO("RAM width %dbits DDR\n", + adev->mc.vram_width); + return amdgpu_ttm_init(adev); +} + +void amdgpu_bo_fini(struct amdgpu_device *adev) +{ + amdgpu_ttm_fini(adev); + arch_phys_wc_del(adev->mc.vram_mtrr); +} + +int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, + struct vm_area_struct *vma) +{ + return ttm_fbdev_mmap(vma, &bo->tbo); +} + +int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) +{ + unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; + + bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK; + bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK; + mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK; + tilesplit = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK; + stilesplit = (tiling_flags >> AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK; + switch (bankw) { + case 0: + case 1: + case 2: + case 4: + case 8: + break; + default: + return -EINVAL; + } + switch (bankh) { + case 0: + case 1: + case 2: + case 4: + case 8: + break; + default: + return -EINVAL; + } + switch (mtaspect) { + case 0: + case 1: + case 2: + case 4: + case 8: + break; + default: + return -EINVAL; + } + if (tilesplit > 6) { + return -EINVAL; + } + if (stilesplit > 6) { + return -EINVAL; + } + + bo->tiling_flags = tiling_flags; + return 0; +} + +void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) +{ + lockdep_assert_held(&bo->tbo.resv->lock.base); + + if (tiling_flags) + *tiling_flags = bo->tiling_flags; +} + +int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, + uint32_t metadata_size, uint64_t flags) +{ + void *buffer; + + if (!metadata_size) { + if (bo->metadata_size) { + kfree(bo->metadata); + bo->metadata_size = 0; + } + return 0; + } + + if (metadata == NULL) + return -EINVAL; + + buffer = kzalloc(metadata_size, GFP_KERNEL); + if (buffer == NULL) + return -ENOMEM; + + memcpy(buffer, metadata, metadata_size); + + kfree(bo->metadata); + bo->metadata_flags = flags; + bo->metadata = buffer; + bo->metadata_size = metadata_size; + + return 0; +} + +int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, + size_t buffer_size, uint32_t *metadata_size, + uint64_t *flags) +{ + if (!buffer && !metadata_size) + return -EINVAL; + + if (buffer) { + if (buffer_size < bo->metadata_size) + return -EINVAL; + + if (bo->metadata_size) + memcpy(buffer, bo->metadata, bo->metadata_size); + } + + if (metadata_size) + *metadata_size = bo->metadata_size; + if (flags) + *flags = bo->metadata_flags; + + return 0; +} + +void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, + struct ttm_mem_reg *new_mem) +{ + struct amdgpu_bo *rbo; + + if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) + return; + + rbo = container_of(bo, struct amdgpu_bo, tbo); + amdgpu_vm_bo_invalidate(rbo->adev, rbo); + + /* update statistics */ + if (!new_mem) + return; + + /* move_notify is called before move happens */ + amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem); +} + +int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) +{ + struct amdgpu_device *adev; + struct amdgpu_bo *rbo; + unsigned long offset, size; + int r; + + if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) + return 0; + rbo = container_of(bo, struct amdgpu_bo, tbo); + adev = rbo->adev; + if (bo->mem.mem_type == TTM_PL_VRAM) { + size = bo->mem.num_pages << PAGE_SHIFT; + offset = bo->mem.start << PAGE_SHIFT; + if ((offset + size) > adev->mc.visible_vram_size) { + /* hurrah the memory is not visible ! */ + amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_VRAM); + rbo->placements[0].lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; + r = ttm_bo_validate(bo, &rbo->placement, false, false); + if (unlikely(r != 0)) + return r; + offset = bo->mem.start << PAGE_SHIFT; + /* this should not happen */ + if ((offset + size) > adev->mc.visible_vram_size) + return -EINVAL; + } + } + return 0; +} + +/** + * amdgpu_bo_fence - add fence to buffer object + * + * @bo: buffer object in question + * @fence: fence to add + * @shared: true if fence should be added shared + * + */ +void amdgpu_bo_fence(struct amdgpu_bo *bo, struct amdgpu_fence *fence, + bool shared) +{ + struct reservation_object *resv = bo->tbo.resv; + + if (shared) + reservation_object_add_shared_fence(resv, &fence->base); + else + reservation_object_add_excl_fence(resv, &fence->base); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h new file mode 100644 index 000000000000..b1e0a03c1d78 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -0,0 +1,196 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#ifndef __AMDGPU_OBJECT_H__ +#define __AMDGPU_OBJECT_H__ + +#include +#include "amdgpu.h" + +/** + * amdgpu_mem_type_to_domain - return domain corresponding to mem_type + * @mem_type: ttm memory type + * + * Returns corresponding domain of the ttm mem_type + */ +static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) +{ + switch (mem_type) { + case TTM_PL_VRAM: + return AMDGPU_GEM_DOMAIN_VRAM; + case TTM_PL_TT: + return AMDGPU_GEM_DOMAIN_GTT; + case TTM_PL_SYSTEM: + return AMDGPU_GEM_DOMAIN_CPU; + case AMDGPU_PL_GDS: + return AMDGPU_GEM_DOMAIN_GDS; + case AMDGPU_PL_GWS: + return AMDGPU_GEM_DOMAIN_GWS; + case AMDGPU_PL_OA: + return AMDGPU_GEM_DOMAIN_OA; + default: + break; + } + return 0; +} + +/** + * amdgpu_bo_reserve - reserve bo + * @bo: bo structure + * @no_intr: don't return -ERESTARTSYS on pending signal + * + * Returns: + * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by + * a signal. Release all buffer reservations and return to user-space. + */ +static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) +{ + int r; + + r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0); + if (unlikely(r != 0)) { + if (r != -ERESTARTSYS) + dev_err(bo->adev->dev, "%p reserve failed\n", bo); + return r; + } + return 0; +} + +static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo) +{ + ttm_bo_unreserve(&bo->tbo); +} + +/** + * amdgpu_bo_gpu_offset - return GPU offset of bo + * @bo: amdgpu object for which we query the offset + * + * Returns current GPU offset of the object. + * + * Note: object should either be pinned or reserved when calling this + * function, it might be useful to add check for this for debugging. + */ +static inline u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) +{ + return bo->tbo.offset; +} + +static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo) +{ + return bo->tbo.num_pages << PAGE_SHIFT; +} + +static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo) +{ + return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; +} + +static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo) +{ + return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; +} + +/** + * amdgpu_bo_mmap_offset - return mmap offset of bo + * @bo: amdgpu object for which we query the offset + * + * Returns mmap offset of the object. + */ +static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) +{ + return drm_vma_node_offset_addr(&bo->tbo.vma_node); +} + +int amdgpu_bo_create(struct amdgpu_device *adev, + unsigned long size, int byte_align, + bool kernel, u32 domain, u64 flags, + struct sg_table *sg, + struct amdgpu_bo **bo_ptr); +int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); +void amdgpu_bo_kunmap(struct amdgpu_bo *bo); +struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); +void amdgpu_bo_unref(struct amdgpu_bo **bo); +int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr); +int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, + u64 max_offset, u64 *gpu_addr); +int amdgpu_bo_unpin(struct amdgpu_bo *bo); +int amdgpu_bo_evict_vram(struct amdgpu_device *adev); +void amdgpu_bo_force_delete(struct amdgpu_device *adev); +int amdgpu_bo_init(struct amdgpu_device *adev); +void amdgpu_bo_fini(struct amdgpu_device *adev); +int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, + struct vm_area_struct *vma); +int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); +void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags); +int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, + uint32_t metadata_size, uint64_t flags); +int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, + size_t buffer_size, uint32_t *metadata_size, + uint64_t *flags); +void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, + struct ttm_mem_reg *new_mem); +int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); +void amdgpu_bo_fence(struct amdgpu_bo *bo, struct amdgpu_fence *fence, + bool shared); + +/* + * sub allocation + */ + +static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo) +{ + return sa_bo->manager->gpu_addr + sa_bo->soffset; +} + +static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo) +{ + return sa_bo->manager->cpu_ptr + sa_bo->soffset; +} + +int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, + struct amdgpu_sa_manager *sa_manager, + unsigned size, u32 align, u32 domain); +void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev, + struct amdgpu_sa_manager *sa_manager); +int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev, + struct amdgpu_sa_manager *sa_manager); +int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev, + struct amdgpu_sa_manager *sa_manager); +int amdgpu_sa_bo_new(struct amdgpu_device *adev, + struct amdgpu_sa_manager *sa_manager, + struct amdgpu_sa_bo **sa_bo, + unsigned size, unsigned align); +void amdgpu_sa_bo_free(struct amdgpu_device *adev, + struct amdgpu_sa_bo **sa_bo, + struct amdgpu_fence *fence); +#if defined(CONFIG_DEBUG_FS) +void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, + struct seq_file *m); +#endif + + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c new file mode 100644 index 000000000000..d15314957732 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c @@ -0,0 +1,350 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include +#include "amdgpu.h" +#include "atom.h" +#include "atombios_encoders.h" +#include +#include + +/** + * amdgpu_pll_reduce_ratio - fractional number reduction + * + * @nom: nominator + * @den: denominator + * @nom_min: minimum value for nominator + * @den_min: minimum value for denominator + * + * Find the greatest common divisor and apply it on both nominator and + * denominator, but make nominator and denominator are at least as large + * as their minimum values. + */ +static void amdgpu_pll_reduce_ratio(unsigned *nom, unsigned *den, + unsigned nom_min, unsigned den_min) +{ + unsigned tmp; + + /* reduce the numbers to a simpler ratio */ + tmp = gcd(*nom, *den); + *nom /= tmp; + *den /= tmp; + + /* make sure nominator is large enough */ + if (*nom < nom_min) { + tmp = DIV_ROUND_UP(nom_min, *nom); + *nom *= tmp; + *den *= tmp; + } + + /* make sure the denominator is large enough */ + if (*den < den_min) { + tmp = DIV_ROUND_UP(den_min, *den); + *nom *= tmp; + *den *= tmp; + } +} + +/** + * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation + * + * @nom: nominator + * @den: denominator + * @post_div: post divider + * @fb_div_max: feedback divider maximum + * @ref_div_max: reference divider maximum + * @fb_div: resulting feedback divider + * @ref_div: resulting reference divider + * + * Calculate feedback and reference divider for a given post divider. Makes + * sure we stay within the limits. + */ +static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, + unsigned fb_div_max, unsigned ref_div_max, + unsigned *fb_div, unsigned *ref_div) +{ + /* limit reference * post divider to a maximum */ + ref_div_max = min(128 / post_div, ref_div_max); + + /* get matching reference and feedback divider */ + *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); + *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); + + /* limit fb divider to its maximum */ + if (*fb_div > fb_div_max) { + *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); + *fb_div = fb_div_max; + } +} + +/** + * amdgpu_pll_compute - compute PLL paramaters + * + * @pll: information about the PLL + * @dot_clock_p: resulting pixel clock + * fb_div_p: resulting feedback divider + * frac_fb_div_p: fractional part of the feedback divider + * ref_div_p: resulting reference divider + * post_div_p: resulting reference divider + * + * Try to calculate the PLL parameters to generate the given frequency: + * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) + */ +void amdgpu_pll_compute(struct amdgpu_pll *pll, + u32 freq, + u32 *dot_clock_p, + u32 *fb_div_p, + u32 *frac_fb_div_p, + u32 *ref_div_p, + u32 *post_div_p) +{ + unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ? + freq : freq / 10; + + unsigned fb_div_min, fb_div_max, fb_div; + unsigned post_div_min, post_div_max, post_div; + unsigned ref_div_min, ref_div_max, ref_div; + unsigned post_div_best, diff_best; + unsigned nom, den; + + /* determine allowed feedback divider range */ + fb_div_min = pll->min_feedback_div; + fb_div_max = pll->max_feedback_div; + + if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { + fb_div_min *= 10; + fb_div_max *= 10; + } + + /* determine allowed ref divider range */ + if (pll->flags & AMDGPU_PLL_USE_REF_DIV) + ref_div_min = pll->reference_div; + else + ref_div_min = pll->min_ref_div; + + if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && + pll->flags & AMDGPU_PLL_USE_REF_DIV) + ref_div_max = pll->reference_div; + else + ref_div_max = pll->max_ref_div; + + /* determine allowed post divider range */ + if (pll->flags & AMDGPU_PLL_USE_POST_DIV) { + post_div_min = pll->post_div; + post_div_max = pll->post_div; + } else { + unsigned vco_min, vco_max; + + if (pll->flags & AMDGPU_PLL_IS_LCD) { + vco_min = pll->lcd_pll_out_min; + vco_max = pll->lcd_pll_out_max; + } else { + vco_min = pll->pll_out_min; + vco_max = pll->pll_out_max; + } + + if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { + vco_min *= 10; + vco_max *= 10; + } + + post_div_min = vco_min / target_clock; + if ((target_clock * post_div_min) < vco_min) + ++post_div_min; + if (post_div_min < pll->min_post_div) + post_div_min = pll->min_post_div; + + post_div_max = vco_max / target_clock; + if ((target_clock * post_div_max) > vco_max) + --post_div_max; + if (post_div_max > pll->max_post_div) + post_div_max = pll->max_post_div; + } + + /* represent the searched ratio as fractional number */ + nom = target_clock; + den = pll->reference_freq; + + /* reduce the numbers to a simpler ratio */ + amdgpu_pll_reduce_ratio(&nom, &den, fb_div_min, post_div_min); + + /* now search for a post divider */ + if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP) + post_div_best = post_div_min; + else + post_div_best = post_div_max; + diff_best = ~0; + + for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { + unsigned diff; + amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, + ref_div_max, &fb_div, &ref_div); + diff = abs(target_clock - (pll->reference_freq * fb_div) / + (ref_div * post_div)); + + if (diff < diff_best || (diff == diff_best && + !(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) { + + post_div_best = post_div; + diff_best = diff; + } + } + post_div = post_div_best; + + /* get the feedback and reference divider for the optimal value */ + amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, + &fb_div, &ref_div); + + /* reduce the numbers to a simpler ratio once more */ + /* this also makes sure that the reference divider is large enough */ + amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); + + /* avoid high jitter with small fractional dividers */ + if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { + fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60); + if (fb_div < fb_div_min) { + unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); + fb_div *= tmp; + ref_div *= tmp; + } + } + + /* and finally save the result */ + if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { + *fb_div_p = fb_div / 10; + *frac_fb_div_p = fb_div % 10; + } else { + *fb_div_p = fb_div; + *frac_fb_div_p = 0; + } + + *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + + (pll->reference_freq * *frac_fb_div_p)) / + (ref_div * post_div * 10); + *ref_div_p = ref_div; + *post_div_p = post_div; + + DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", + freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, + ref_div, post_div); +} + +/** + * amdgpu_pll_get_use_mask - look up a mask of which pplls are in use + * + * @crtc: drm crtc + * + * Returns the mask of which PPLLs (Pixel PLLs) are in use. + */ +u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_crtc *test_crtc; + struct amdgpu_crtc *test_amdgpu_crtc; + u32 pll_in_use = 0; + + list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { + if (crtc == test_crtc) + continue; + + test_amdgpu_crtc = to_amdgpu_crtc(test_crtc); + if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID) + pll_in_use |= (1 << test_amdgpu_crtc->pll_id); + } + return pll_in_use; +} + +/** + * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP + * + * @crtc: drm crtc + * + * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is + * also in DP mode. For DP, a single PPLL can be used for all DP + * crtcs/encoders. + */ +int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_crtc *test_crtc; + struct amdgpu_crtc *test_amdgpu_crtc; + + list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { + if (crtc == test_crtc) + continue; + test_amdgpu_crtc = to_amdgpu_crtc(test_crtc); + if (test_amdgpu_crtc->encoder && + ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) { + /* for DP use the same PLL for all */ + if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID) + return test_amdgpu_crtc->pll_id; + } + } + return ATOM_PPLL_INVALID; +} + +/** + * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc + * + * @crtc: drm crtc + * @encoder: drm encoder + * + * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can + * be shared (i.e., same clock). + */ +int amdgpu_pll_get_shared_nondp_ppll(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct drm_crtc *test_crtc; + struct amdgpu_crtc *test_amdgpu_crtc; + u32 adjusted_clock, test_adjusted_clock; + + adjusted_clock = amdgpu_crtc->adjusted_clock; + + if (adjusted_clock == 0) + return ATOM_PPLL_INVALID; + + list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { + if (crtc == test_crtc) + continue; + test_amdgpu_crtc = to_amdgpu_crtc(test_crtc); + if (test_amdgpu_crtc->encoder && + !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) { + /* check if we are already driving this connector with another crtc */ + if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) { + /* if we are, return that pll */ + if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID) + return test_amdgpu_crtc->pll_id; + } + /* for non-DP check the clock */ + test_adjusted_clock = test_amdgpu_crtc->adjusted_clock; + if ((crtc->mode.clock == test_crtc->mode.clock) && + (adjusted_clock == test_adjusted_clock) && + (amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) && + (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)) + return test_amdgpu_crtc->pll_id; + } + } + return ATOM_PPLL_INVALID; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h new file mode 100644 index 000000000000..db6136f68b82 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h @@ -0,0 +1,38 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_PLL_H__ +#define __AMDGPU_PLL_H__ + +void amdgpu_pll_compute(struct amdgpu_pll *pll, + u32 freq, + u32 *dot_clock_p, + u32 *fb_div_p, + u32 *frac_fb_div_p, + u32 *ref_div_p, + u32 *post_div_p); +u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc); +int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc); +int amdgpu_pll_get_shared_nondp_ppll(struct drm_crtc *crtc); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c new file mode 100644 index 000000000000..89782543f854 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -0,0 +1,801 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Rafał Miłecki + * Alex Deucher + */ +#include +#include "amdgpu.h" +#include "amdgpu_drv.h" +#include "amdgpu_pm.h" +#include "amdgpu_dpm.h" +#include "atom.h" +#include +#include +#include + +static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev); + +void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) +{ + if (adev->pm.dpm_enabled) { + mutex_lock(&adev->pm.mutex); + if (power_supply_is_system_supplied() > 0) + adev->pm.dpm.ac_power = true; + else + adev->pm.dpm.ac_power = false; + if (adev->pm.funcs->enable_bapm) + amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power); + mutex_unlock(&adev->pm.mutex); + } +} + +static ssize_t amdgpu_get_dpm_state(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = ddev->dev_private; + enum amdgpu_pm_state_type pm = adev->pm.dpm.user_state; + + return snprintf(buf, PAGE_SIZE, "%s\n", + (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : + (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); +} + +static ssize_t amdgpu_set_dpm_state(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = ddev->dev_private; + + mutex_lock(&adev->pm.mutex); + if (strncmp("battery", buf, strlen("battery")) == 0) + adev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; + else if (strncmp("balanced", buf, strlen("balanced")) == 0) + adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; + else if (strncmp("performance", buf, strlen("performance")) == 0) + adev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; + else { + mutex_unlock(&adev->pm.mutex); + count = -EINVAL; + goto fail; + } + mutex_unlock(&adev->pm.mutex); + + /* Can't set dpm state when the card is off */ + if (!(adev->flags & AMDGPU_IS_PX) || + (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) + amdgpu_pm_compute_clocks(adev); +fail: + return count; +} + +static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = ddev->dev_private; + enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level; + + return snprintf(buf, PAGE_SIZE, "%s\n", + (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" : + (level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); +} + +static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = ddev->dev_private; + enum amdgpu_dpm_forced_level level; + int ret = 0; + + mutex_lock(&adev->pm.mutex); + if (strncmp("low", buf, strlen("low")) == 0) { + level = AMDGPU_DPM_FORCED_LEVEL_LOW; + } else if (strncmp("high", buf, strlen("high")) == 0) { + level = AMDGPU_DPM_FORCED_LEVEL_HIGH; + } else if (strncmp("auto", buf, strlen("auto")) == 0) { + level = AMDGPU_DPM_FORCED_LEVEL_AUTO; + } else { + count = -EINVAL; + goto fail; + } + if (adev->pm.funcs->force_performance_level) { + if (adev->pm.dpm.thermal_active) { + count = -EINVAL; + goto fail; + } + ret = amdgpu_dpm_force_performance_level(adev, level); + if (ret) + count = -EINVAL; + } +fail: + mutex_unlock(&adev->pm.mutex); + + return count; +} + +static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state); +static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, + amdgpu_get_dpm_forced_performance_level, + amdgpu_set_dpm_forced_performance_level); + +static ssize_t amdgpu_hwmon_show_temp(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + int temp; + + if (adev->pm.funcs->get_temperature) + temp = amdgpu_dpm_get_temperature(adev); + else + temp = 0; + + return snprintf(buf, PAGE_SIZE, "%d\n", temp); +} + +static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + int hyst = to_sensor_dev_attr(attr)->index; + int temp; + + if (hyst) + temp = adev->pm.dpm.thermal.min_temp; + else + temp = adev->pm.dpm.thermal.max_temp; + + return snprintf(buf, PAGE_SIZE, "%d\n", temp); +} + +static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + u32 pwm_mode = 0; + + if (adev->pm.funcs->get_fan_control_mode) + pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); + + /* never 0 (full-speed), fuse or smc-controlled always */ + return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); +} + +static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + int err; + int value; + + if(!adev->pm.funcs->set_fan_control_mode) + return -EINVAL; + + err = kstrtoint(buf, 10, &value); + if (err) + return err; + + switch (value) { + case 1: /* manual, percent-based */ + amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC); + break; + default: /* disable */ + amdgpu_dpm_set_fan_control_mode(adev, 0); + break; + } + + return count; +} + +static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%i\n", 0); +} + +static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%i\n", 255); +} + +static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + int err; + u32 value; + + err = kstrtou32(buf, 10, &value); + if (err) + return err; + + value = (value * 100) / 255; + + err = amdgpu_dpm_set_fan_speed_percent(adev, value); + if (err) + return err; + + return count; +} + +static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amdgpu_device *adev = dev_get_drvdata(dev); + int err; + u32 speed; + + err = amdgpu_dpm_get_fan_speed_percent(adev, &speed); + if (err) + return err; + + speed = (speed * 255) / 100; + + return sprintf(buf, "%i\n", speed); +} + +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0); +static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); +static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); +static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); +static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); +static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); +static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); + +static struct attribute *hwmon_attributes[] = { + &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_temp1_crit.dev_attr.attr, + &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, + &sensor_dev_attr_pwm1.dev_attr.attr, + &sensor_dev_attr_pwm1_enable.dev_attr.attr, + &sensor_dev_attr_pwm1_min.dev_attr.attr, + &sensor_dev_attr_pwm1_max.dev_attr.attr, + NULL +}; + +static umode_t hwmon_attributes_visible(struct kobject *kobj, + struct attribute *attr, int index) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct amdgpu_device *adev = dev_get_drvdata(dev); + umode_t effective_mode = attr->mode; + + /* Skip limit attributes if DPM is not enabled */ + if (!adev->pm.dpm_enabled && + (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || + attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) + return 0; + + /* Skip fan attributes if fan is not present */ + if (adev->pm.no_fan && + (attr == &sensor_dev_attr_pwm1.dev_attr.attr || + attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || + attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || + attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) + return 0; + + /* mask fan attributes if we have no bindings for this asic to expose */ + if ((!adev->pm.funcs->get_fan_speed_percent && + attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ + (!adev->pm.funcs->get_fan_control_mode && + attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ + effective_mode &= ~S_IRUGO; + + if ((!adev->pm.funcs->set_fan_speed_percent && + attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ + (!adev->pm.funcs->set_fan_control_mode && + attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ + effective_mode &= ~S_IWUSR; + + /* hide max/min values if we can't both query and manage the fan */ + if ((!adev->pm.funcs->set_fan_speed_percent && + !adev->pm.funcs->get_fan_speed_percent) && + (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || + attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) + return 0; + + return effective_mode; +} + +static const struct attribute_group hwmon_attrgroup = { + .attrs = hwmon_attributes, + .is_visible = hwmon_attributes_visible, +}; + +static const struct attribute_group *hwmon_groups[] = { + &hwmon_attrgroup, + NULL +}; + +void amdgpu_dpm_thermal_work_handler(struct work_struct *work) +{ + struct amdgpu_device *adev = + container_of(work, struct amdgpu_device, + pm.dpm.thermal.work); + /* switch to the thermal state */ + enum amdgpu_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; + + if (!adev->pm.dpm_enabled) + return; + + if (adev->pm.funcs->get_temperature) { + int temp = amdgpu_dpm_get_temperature(adev); + + if (temp < adev->pm.dpm.thermal.min_temp) + /* switch back the user state */ + dpm_state = adev->pm.dpm.user_state; + } else { + if (adev->pm.dpm.thermal.high_to_low) + /* switch back the user state */ + dpm_state = adev->pm.dpm.user_state; + } + mutex_lock(&adev->pm.mutex); + if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) + adev->pm.dpm.thermal_active = true; + else + adev->pm.dpm.thermal_active = false; + adev->pm.dpm.state = dpm_state; + mutex_unlock(&adev->pm.mutex); + + amdgpu_pm_compute_clocks(adev); +} + +static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev, + enum amdgpu_pm_state_type dpm_state) +{ + int i; + struct amdgpu_ps *ps; + u32 ui_class; + bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ? + true : false; + + /* check if the vblank period is too short to adjust the mclk */ + if (single_display && adev->pm.funcs->vblank_too_short) { + if (amdgpu_dpm_vblank_too_short(adev)) + single_display = false; + } + + /* certain older asics have a separare 3D performance state, + * so try that first if the user selected performance + */ + if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) + dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; + /* balanced states don't exist at the moment */ + if (dpm_state == POWER_STATE_TYPE_BALANCED) + dpm_state = POWER_STATE_TYPE_PERFORMANCE; + +restart_search: + /* Pick the best power state based on current conditions */ + for (i = 0; i < adev->pm.dpm.num_ps; i++) { + ps = &adev->pm.dpm.ps[i]; + ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; + switch (dpm_state) { + /* user states */ + case POWER_STATE_TYPE_BATTERY: + if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { + if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { + if (single_display) + return ps; + } else + return ps; + } + break; + case POWER_STATE_TYPE_BALANCED: + if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { + if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { + if (single_display) + return ps; + } else + return ps; + } + break; + case POWER_STATE_TYPE_PERFORMANCE: + if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { + if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { + if (single_display) + return ps; + } else + return ps; + } + break; + /* internal states */ + case POWER_STATE_TYPE_INTERNAL_UVD: + if (adev->pm.dpm.uvd_ps) + return adev->pm.dpm.uvd_ps; + else + break; + case POWER_STATE_TYPE_INTERNAL_UVD_SD: + if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) + return ps; + break; + case POWER_STATE_TYPE_INTERNAL_UVD_HD: + if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) + return ps; + break; + case POWER_STATE_TYPE_INTERNAL_UVD_HD2: + if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) + return ps; + break; + case POWER_STATE_TYPE_INTERNAL_UVD_MVC: + if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) + return ps; + break; + case POWER_STATE_TYPE_INTERNAL_BOOT: + return adev->pm.dpm.boot_ps; + case POWER_STATE_TYPE_INTERNAL_THERMAL: + if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) + return ps; + break; + case POWER_STATE_TYPE_INTERNAL_ACPI: + if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) + return ps; + break; + case POWER_STATE_TYPE_INTERNAL_ULV: + if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) + return ps; + break; + case POWER_STATE_TYPE_INTERNAL_3DPERF: + if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) + return ps; + break; + default: + break; + } + } + /* use a fallback state if we didn't match */ + switch (dpm_state) { + case POWER_STATE_TYPE_INTERNAL_UVD_SD: + dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; + goto restart_search; + case POWER_STATE_TYPE_INTERNAL_UVD_HD: + case POWER_STATE_TYPE_INTERNAL_UVD_HD2: + case POWER_STATE_TYPE_INTERNAL_UVD_MVC: + if (adev->pm.dpm.uvd_ps) { + return adev->pm.dpm.uvd_ps; + } else { + dpm_state = POWER_STATE_TYPE_PERFORMANCE; + goto restart_search; + } + case POWER_STATE_TYPE_INTERNAL_THERMAL: + dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; + goto restart_search; + case POWER_STATE_TYPE_INTERNAL_ACPI: + dpm_state = POWER_STATE_TYPE_BATTERY; + goto restart_search; + case POWER_STATE_TYPE_BATTERY: + case POWER_STATE_TYPE_BALANCED: + case POWER_STATE_TYPE_INTERNAL_3DPERF: + dpm_state = POWER_STATE_TYPE_PERFORMANCE; + goto restart_search; + default: + break; + } + + return NULL; +} + +static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) +{ + int i; + struct amdgpu_ps *ps; + enum amdgpu_pm_state_type dpm_state; + int ret; + + /* if dpm init failed */ + if (!adev->pm.dpm_enabled) + return; + + if (adev->pm.dpm.user_state != adev->pm.dpm.state) { + /* add other state override checks here */ + if ((!adev->pm.dpm.thermal_active) && + (!adev->pm.dpm.uvd_active)) + adev->pm.dpm.state = adev->pm.dpm.user_state; + } + dpm_state = adev->pm.dpm.state; + + ps = amdgpu_dpm_pick_power_state(adev, dpm_state); + if (ps) + adev->pm.dpm.requested_ps = ps; + else + return; + + /* no need to reprogram if nothing changed unless we are on BTC+ */ + if (adev->pm.dpm.current_ps == adev->pm.dpm.requested_ps) { + /* vce just modifies an existing state so force a change */ + if (ps->vce_active != adev->pm.dpm.vce_active) + goto force; + if (adev->flags & AMDGPU_IS_APU) { + /* for APUs if the num crtcs changed but state is the same, + * all we need to do is update the display configuration. + */ + if (adev->pm.dpm.new_active_crtcs != adev->pm.dpm.current_active_crtcs) { + /* update display watermarks based on new power state */ + amdgpu_display_bandwidth_update(adev); + /* update displays */ + amdgpu_dpm_display_configuration_changed(adev); + adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; + adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; + } + return; + } else { + /* for BTC+ if the num crtcs hasn't changed and state is the same, + * nothing to do, if the num crtcs is > 1 and state is the same, + * update display configuration. + */ + if (adev->pm.dpm.new_active_crtcs == + adev->pm.dpm.current_active_crtcs) { + return; + } else if ((adev->pm.dpm.current_active_crtc_count > 1) && + (adev->pm.dpm.new_active_crtc_count > 1)) { + /* update display watermarks based on new power state */ + amdgpu_display_bandwidth_update(adev); + /* update displays */ + amdgpu_dpm_display_configuration_changed(adev); + adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; + adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; + return; + } + } + } + +force: + if (amdgpu_dpm == 1) { + printk("switching from power state:\n"); + amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); + printk("switching to power state:\n"); + amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps); + } + + mutex_lock(&adev->ddev->struct_mutex); + down_write(&adev->pm.mclk_lock); + mutex_lock(&adev->ring_lock); + + /* update whether vce is active */ + ps->vce_active = adev->pm.dpm.vce_active; + + ret = amdgpu_dpm_pre_set_power_state(adev); + if (ret) + goto done; + + /* update display watermarks based on new power state */ + amdgpu_display_bandwidth_update(adev); + /* update displays */ + amdgpu_dpm_display_configuration_changed(adev); + + adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; + adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; + + /* wait for the rings to drain */ + for (i = 0; i < AMDGPU_MAX_RINGS; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + if (ring && ring->ready) + amdgpu_fence_wait_empty(ring); + } + + /* program the new power state */ + amdgpu_dpm_set_power_state(adev); + + /* update current power state */ + adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps; + + amdgpu_dpm_post_set_power_state(adev); + + if (adev->pm.funcs->force_performance_level) { + if (adev->pm.dpm.thermal_active) { + enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level; + /* force low perf level for thermal */ + amdgpu_dpm_force_performance_level(adev, AMDGPU_DPM_FORCED_LEVEL_LOW); + /* save the user's level */ + adev->pm.dpm.forced_level = level; + } else { + /* otherwise, user selected level */ + amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level); + } + } + +done: + mutex_unlock(&adev->ring_lock); + up_write(&adev->pm.mclk_lock); + mutex_unlock(&adev->ddev->struct_mutex); +} + +void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) +{ + if (adev->pm.funcs->powergate_uvd) { + mutex_lock(&adev->pm.mutex); + /* enable/disable UVD */ + amdgpu_dpm_powergate_uvd(adev, !enable); + mutex_unlock(&adev->pm.mutex); + } else { + if (enable) { + mutex_lock(&adev->pm.mutex); + adev->pm.dpm.uvd_active = true; + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; + mutex_unlock(&adev->pm.mutex); + } else { + mutex_lock(&adev->pm.mutex); + adev->pm.dpm.uvd_active = false; + mutex_unlock(&adev->pm.mutex); + } + + amdgpu_pm_compute_clocks(adev); + } +} + +void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) +{ + if (enable) { + mutex_lock(&adev->pm.mutex); + adev->pm.dpm.vce_active = true; + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL; + mutex_unlock(&adev->pm.mutex); + } else { + mutex_lock(&adev->pm.mutex); + adev->pm.dpm.vce_active = false; + mutex_unlock(&adev->pm.mutex); + } + + amdgpu_pm_compute_clocks(adev); +} + +void amdgpu_pm_print_power_states(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->pm.dpm.num_ps; i++) { + printk("== power state %d ==\n", i); + amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); + } +} + +int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) +{ + int ret; + + if (adev->pm.funcs->get_temperature == NULL) + return 0; + adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, + DRIVER_NAME, adev, + hwmon_groups); + if (IS_ERR(adev->pm.int_hwmon_dev)) { + ret = PTR_ERR(adev->pm.int_hwmon_dev); + dev_err(adev->dev, + "Unable to register hwmon device: %d\n", ret); + return ret; + } + + ret = device_create_file(adev->dev, &dev_attr_power_dpm_state); + if (ret) { + DRM_ERROR("failed to create device file for dpm state\n"); + return ret; + } + ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level); + if (ret) { + DRM_ERROR("failed to create device file for dpm state\n"); + return ret; + } + ret = amdgpu_debugfs_pm_init(adev); + if (ret) { + DRM_ERROR("Failed to register debugfs file for dpm!\n"); + return ret; + } + + return 0; +} + +void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) +{ + if (adev->pm.int_hwmon_dev) + hwmon_device_unregister(adev->pm.int_hwmon_dev); + device_remove_file(adev->dev, &dev_attr_power_dpm_state); + device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level); +} + +void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) +{ + struct drm_device *ddev = adev->ddev; + struct drm_crtc *crtc; + struct amdgpu_crtc *amdgpu_crtc; + + if (!adev->pm.dpm_enabled) + return; + + mutex_lock(&adev->pm.mutex); + + /* update active crtc counts */ + adev->pm.dpm.new_active_crtcs = 0; + adev->pm.dpm.new_active_crtc_count = 0; + if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { + list_for_each_entry(crtc, + &ddev->mode_config.crtc_list, head) { + amdgpu_crtc = to_amdgpu_crtc(crtc); + if (crtc->enabled) { + adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); + adev->pm.dpm.new_active_crtc_count++; + } + } + } + + /* update battery/ac status */ + if (power_supply_is_system_supplied() > 0) + adev->pm.dpm.ac_power = true; + else + adev->pm.dpm.ac_power = false; + + amdgpu_dpm_change_power_state_locked(adev); + + mutex_unlock(&adev->pm.mutex); + +} + +/* + * Debugfs info + */ +#if defined(CONFIG_DEBUG_FS) + +static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + + if (adev->pm.dpm_enabled) { + mutex_lock(&adev->pm.mutex); + if (adev->pm.funcs->debugfs_print_current_performance_level) + amdgpu_dpm_debugfs_print_current_performance_level(adev, m); + else + seq_printf(m, "Debugfs support not implemented for this asic\n"); + mutex_unlock(&adev->pm.mutex); + } + + return 0; +} + +static struct drm_info_list amdgpu_pm_info_list[] = { + {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL}, +}; +#endif + +static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list)); +#else + return 0; +#endif +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h new file mode 100644 index 000000000000..5fd7734f15ca --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h @@ -0,0 +1,35 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_PM_H__ +#define __AMDGPU_PM_H__ + +int amdgpu_pm_sysfs_init(struct amdgpu_device *adev); +void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev); +void amdgpu_pm_print_power_states(struct amdgpu_device *adev); +void amdgpu_pm_compute_clocks(struct amdgpu_device *adev); +void amdgpu_dpm_thermal_work_handler(struct work_struct *work); +void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable); +void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c new file mode 100644 index 000000000000..d9652fe32d6a --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c @@ -0,0 +1,125 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * based on nouveau_prime.c + * + * Authors: Alex Deucher + */ +#include + +#include "amdgpu.h" +#include +#include + +struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int npages = bo->tbo.num_pages; + + return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages); +} + +void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int ret; + + ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, + &bo->dma_buf_vmap); + if (ret) + return ERR_PTR(ret); + + return bo->dma_buf_vmap.virtual; +} + +void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + + ttm_bo_kunmap(&bo->dma_buf_vmap); +} + +struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg) +{ + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_bo *bo; + int ret; + + ret = amdgpu_bo_create(adev, attach->dmabuf->size, PAGE_SIZE, false, + AMDGPU_GEM_DOMAIN_GTT, 0, sg, &bo); + if (ret) + return ERR_PTR(ret); + + mutex_lock(&adev->gem.mutex); + list_add_tail(&bo->list, &adev->gem.objects); + mutex_unlock(&adev->gem.mutex); + + return &bo->gem_base; +} + +int amdgpu_gem_prime_pin(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int ret = 0; + + ret = amdgpu_bo_reserve(bo, false); + if (unlikely(ret != 0)) + return ret; + + /* pin buffer into GTT */ + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL); + amdgpu_bo_unreserve(bo); + return ret; +} + +void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int ret = 0; + + ret = amdgpu_bo_reserve(bo, false); + if (unlikely(ret != 0)) + return; + + amdgpu_bo_unpin(bo); + amdgpu_bo_unreserve(bo); +} + +struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + + return bo->tbo.resv; +} + +struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, + struct drm_gem_object *gobj, + int flags) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); + + if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm)) + return ERR_PTR(-EPERM); + + return drm_gem_prime_export(dev, gobj, flags); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c new file mode 100644 index 000000000000..855e2196657a --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -0,0 +1,561 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + * Christian König + */ +#include +#include +#include +#include +#include "amdgpu.h" +#include "atom.h" + +/* + * Rings + * Most engines on the GPU are fed via ring buffers. Ring + * buffers are areas of GPU accessible memory that the host + * writes commands into and the GPU reads commands out of. + * There is a rptr (read pointer) that determines where the + * GPU is currently reading, and a wptr (write pointer) + * which determines where the host has written. When the + * pointers are equal, the ring is idle. When the host + * writes commands to the ring buffer, it increments the + * wptr. The GPU then starts fetching commands and executes + * them until the pointers are equal again. + */ +static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring); + +/** + * amdgpu_ring_free_size - update the free size + * + * @adev: amdgpu_device pointer + * @ring: amdgpu_ring structure holding ring information + * + * Update the free dw slots in the ring buffer (all asics). + */ +void amdgpu_ring_free_size(struct amdgpu_ring *ring) +{ + uint32_t rptr = amdgpu_ring_get_rptr(ring); + + /* This works because ring_size is a power of 2 */ + ring->ring_free_dw = rptr + (ring->ring_size / 4); + ring->ring_free_dw -= ring->wptr; + ring->ring_free_dw &= ring->ptr_mask; + if (!ring->ring_free_dw) { + /* this is an empty ring */ + ring->ring_free_dw = ring->ring_size / 4; + /* update lockup info to avoid false positive */ + amdgpu_ring_lockup_update(ring); + } +} + +/** + * amdgpu_ring_alloc - allocate space on the ring buffer + * + * @adev: amdgpu_device pointer + * @ring: amdgpu_ring structure holding ring information + * @ndw: number of dwords to allocate in the ring buffer + * + * Allocate @ndw dwords in the ring buffer (all asics). + * Returns 0 on success, error on failure. + */ +int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw) +{ + int r; + + /* make sure we aren't trying to allocate more space than there is on the ring */ + if (ndw > (ring->ring_size / 4)) + return -ENOMEM; + /* Align requested size with padding so unlock_commit can + * pad safely */ + amdgpu_ring_free_size(ring); + ndw = (ndw + ring->align_mask) & ~ring->align_mask; + while (ndw > (ring->ring_free_dw - 1)) { + amdgpu_ring_free_size(ring); + if (ndw < ring->ring_free_dw) { + break; + } + r = amdgpu_fence_wait_next(ring); + if (r) + return r; + } + ring->count_dw = ndw; + ring->wptr_old = ring->wptr; + return 0; +} + +/** + * amdgpu_ring_lock - lock the ring and allocate space on it + * + * @adev: amdgpu_device pointer + * @ring: amdgpu_ring structure holding ring information + * @ndw: number of dwords to allocate in the ring buffer + * + * Lock the ring and allocate @ndw dwords in the ring buffer + * (all asics). + * Returns 0 on success, error on failure. + */ +int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw) +{ + int r; + + mutex_lock(ring->ring_lock); + r = amdgpu_ring_alloc(ring, ndw); + if (r) { + mutex_unlock(ring->ring_lock); + return r; + } + return 0; +} + +/** + * amdgpu_ring_commit - tell the GPU to execute the new + * commands on the ring buffer + * + * @adev: amdgpu_device pointer + * @ring: amdgpu_ring structure holding ring information + * + * Update the wptr (write pointer) to tell the GPU to + * execute new commands on the ring buffer (all asics). + */ +void amdgpu_ring_commit(struct amdgpu_ring *ring) +{ + /* We pad to match fetch size */ + while (ring->wptr & ring->align_mask) { + amdgpu_ring_write(ring, ring->nop); + } + mb(); + amdgpu_ring_set_wptr(ring); +} + +/** + * amdgpu_ring_unlock_commit - tell the GPU to execute the new + * commands on the ring buffer and unlock it + * + * @ring: amdgpu_ring structure holding ring information + * + * Call amdgpu_ring_commit() then unlock the ring (all asics). + */ +void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring) +{ + amdgpu_ring_commit(ring); + mutex_unlock(ring->ring_lock); +} + +/** + * amdgpu_ring_undo - reset the wptr + * + * @ring: amdgpu_ring structure holding ring information + * + * Reset the driver's copy of the wptr (all asics). + */ +void amdgpu_ring_undo(struct amdgpu_ring *ring) +{ + ring->wptr = ring->wptr_old; +} + +/** + * amdgpu_ring_unlock_undo - reset the wptr and unlock the ring + * + * @ring: amdgpu_ring structure holding ring information + * + * Call amdgpu_ring_undo() then unlock the ring (all asics). + */ +void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring) +{ + amdgpu_ring_undo(ring); + mutex_unlock(ring->ring_lock); +} + +/** + * amdgpu_ring_lockup_update - update lockup variables + * + * @ring: amdgpu_ring structure holding ring information + * + * Update the last rptr value and timestamp (all asics). + */ +void amdgpu_ring_lockup_update(struct amdgpu_ring *ring) +{ + atomic_set(&ring->last_rptr, amdgpu_ring_get_rptr(ring)); + atomic64_set(&ring->last_activity, jiffies_64); +} + +/** + * amdgpu_ring_test_lockup() - check if ring is lockedup by recording information + * @ring: amdgpu_ring structure holding ring information + * + */ +bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring) +{ + uint32_t rptr = amdgpu_ring_get_rptr(ring); + uint64_t last = atomic64_read(&ring->last_activity); + uint64_t elapsed; + + if (rptr != atomic_read(&ring->last_rptr)) { + /* ring is still working, no lockup */ + amdgpu_ring_lockup_update(ring); + return false; + } + + elapsed = jiffies_to_msecs(jiffies_64 - last); + if (amdgpu_lockup_timeout && elapsed >= amdgpu_lockup_timeout) { + dev_err(ring->adev->dev, "ring %d stalled for more than %llumsec\n", + ring->idx, elapsed); + return true; + } + /* give a chance to the GPU ... */ + return false; +} + +/** + * amdgpu_ring_backup - Back up the content of a ring + * + * @ring: the ring we want to back up + * + * Saves all unprocessed commits from a ring, returns the number of dwords saved. + */ +unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, + uint32_t **data) +{ + unsigned size, ptr, i; + + /* just in case lock the ring */ + mutex_lock(ring->ring_lock); + *data = NULL; + + if (ring->ring_obj == NULL) { + mutex_unlock(ring->ring_lock); + return 0; + } + + /* it doesn't make sense to save anything if all fences are signaled */ + if (!amdgpu_fence_count_emitted(ring)) { + mutex_unlock(ring->ring_lock); + return 0; + } + + ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); + + size = ring->wptr + (ring->ring_size / 4); + size -= ptr; + size &= ring->ptr_mask; + if (size == 0) { + mutex_unlock(ring->ring_lock); + return 0; + } + + /* and then save the content of the ring */ + *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); + if (!*data) { + mutex_unlock(ring->ring_lock); + return 0; + } + for (i = 0; i < size; ++i) { + (*data)[i] = ring->ring[ptr++]; + ptr &= ring->ptr_mask; + } + + mutex_unlock(ring->ring_lock); + return size; +} + +/** + * amdgpu_ring_restore - append saved commands to the ring again + * + * @ring: ring to append commands to + * @size: number of dwords we want to write + * @data: saved commands + * + * Allocates space on the ring and restore the previously saved commands. + */ +int amdgpu_ring_restore(struct amdgpu_ring *ring, + unsigned size, uint32_t *data) +{ + int i, r; + + if (!size || !data) + return 0; + + /* restore the saved ring content */ + r = amdgpu_ring_lock(ring, size); + if (r) + return r; + + for (i = 0; i < size; ++i) { + amdgpu_ring_write(ring, data[i]); + } + + amdgpu_ring_unlock_commit(ring); + kfree(data); + return 0; +} + +/** + * amdgpu_ring_init - init driver ring struct. + * + * @adev: amdgpu_device pointer + * @ring: amdgpu_ring structure holding ring information + * @ring_size: size of the ring + * @nop: nop packet for this ring + * + * Initialize the driver information for the selected ring (all asics). + * Returns 0 on success, error on failure. + */ +int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, + unsigned ring_size, u32 nop, u32 align_mask, + struct amdgpu_irq_src *irq_src, unsigned irq_type, + enum amdgpu_ring_type ring_type) +{ + u32 rb_bufsz; + int r; + + if (ring->adev == NULL) { + if (adev->num_rings >= AMDGPU_MAX_RINGS) + return -EINVAL; + + ring->adev = adev; + ring->idx = adev->num_rings++; + adev->rings[ring->idx] = ring; + amdgpu_fence_driver_init_ring(ring); + } + + r = amdgpu_wb_get(adev, &ring->rptr_offs); + if (r) { + dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); + return r; + } + + r = amdgpu_wb_get(adev, &ring->wptr_offs); + if (r) { + dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); + return r; + } + + r = amdgpu_wb_get(adev, &ring->fence_offs); + if (r) { + dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); + return r; + } + + r = amdgpu_wb_get(adev, &ring->next_rptr_offs); + if (r) { + dev_err(adev->dev, "(%d) ring next_rptr wb alloc failed\n", r); + return r; + } + ring->next_rptr_gpu_addr = adev->wb.gpu_addr + (ring->next_rptr_offs * 4); + ring->next_rptr_cpu_addr = &adev->wb.wb[ring->next_rptr_offs]; + + r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type); + if (r) { + dev_err(adev->dev, "failed initializing fences (%d).\n", r); + return r; + } + + ring->ring_lock = &adev->ring_lock; + /* Align ring size */ + rb_bufsz = order_base_2(ring_size / 8); + ring_size = (1 << (rb_bufsz + 1)) * 4; + ring->ring_size = ring_size; + ring->align_mask = align_mask; + ring->nop = nop; + ring->type = ring_type; + + /* Allocate ring buffer */ + if (ring->ring_obj == NULL) { + r = amdgpu_bo_create(adev, ring->ring_size, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, + NULL, &ring->ring_obj); + if (r) { + dev_err(adev->dev, "(%d) ring create failed\n", r); + return r; + } + r = amdgpu_bo_reserve(ring->ring_obj, false); + if (unlikely(r != 0)) + return r; + r = amdgpu_bo_pin(ring->ring_obj, AMDGPU_GEM_DOMAIN_GTT, + &ring->gpu_addr); + if (r) { + amdgpu_bo_unreserve(ring->ring_obj); + dev_err(adev->dev, "(%d) ring pin failed\n", r); + return r; + } + r = amdgpu_bo_kmap(ring->ring_obj, + (void **)&ring->ring); + amdgpu_bo_unreserve(ring->ring_obj); + if (r) { + dev_err(adev->dev, "(%d) ring map failed\n", r); + return r; + } + } + ring->ptr_mask = (ring->ring_size / 4) - 1; + ring->ring_free_dw = ring->ring_size / 4; + + if (amdgpu_debugfs_ring_init(adev, ring)) { + DRM_ERROR("Failed to register debugfs file for rings !\n"); + } + amdgpu_ring_lockup_update(ring); + return 0; +} + +/** + * amdgpu_ring_fini - tear down the driver ring struct. + * + * @adev: amdgpu_device pointer + * @ring: amdgpu_ring structure holding ring information + * + * Tear down the driver information for the selected ring (all asics). + */ +void amdgpu_ring_fini(struct amdgpu_ring *ring) +{ + int r; + struct amdgpu_bo *ring_obj; + + if (ring->ring_lock == NULL) + return; + + mutex_lock(ring->ring_lock); + ring_obj = ring->ring_obj; + ring->ready = false; + ring->ring = NULL; + ring->ring_obj = NULL; + mutex_unlock(ring->ring_lock); + + amdgpu_wb_free(ring->adev, ring->fence_offs); + amdgpu_wb_free(ring->adev, ring->rptr_offs); + amdgpu_wb_free(ring->adev, ring->wptr_offs); + amdgpu_wb_free(ring->adev, ring->next_rptr_offs); + + if (ring_obj) { + r = amdgpu_bo_reserve(ring_obj, false); + if (likely(r == 0)) { + amdgpu_bo_kunmap(ring_obj); + amdgpu_bo_unpin(ring_obj); + amdgpu_bo_unreserve(ring_obj); + } + amdgpu_bo_unref(&ring_obj); + } +} + +/* + * Debugfs info + */ +#if defined(CONFIG_DEBUG_FS) + +static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + int roffset = *(int*)node->info_ent->data; + struct amdgpu_ring *ring = (void *)(((uint8_t*)adev) + roffset); + + uint32_t rptr, wptr, rptr_next; + unsigned count, i, j; + + amdgpu_ring_free_size(ring); + count = (ring->ring_size / 4) - ring->ring_free_dw; + + wptr = amdgpu_ring_get_wptr(ring); + seq_printf(m, "wptr: 0x%08x [%5d]\n", + wptr, wptr); + + rptr = amdgpu_ring_get_rptr(ring); + seq_printf(m, "rptr: 0x%08x [%5d]\n", + rptr, rptr); + + rptr_next = ~0; + + seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", + ring->wptr, ring->wptr); + seq_printf(m, "last semaphore signal addr : 0x%016llx\n", + ring->last_semaphore_signal_addr); + seq_printf(m, "last semaphore wait addr : 0x%016llx\n", + ring->last_semaphore_wait_addr); + seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); + seq_printf(m, "%u dwords in ring\n", count); + + if (!ring->ready) + return 0; + + /* print 8 dw before current rptr as often it's the last executed + * packet that is the root issue + */ + i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; + for (j = 0; j <= (count + 32); j++) { + seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]); + if (rptr == i) + seq_puts(m, " *"); + if (rptr_next == i) + seq_puts(m, " #"); + seq_puts(m, "\n"); + i = (i + 1) & ring->ptr_mask; + } + return 0; +} + +/* TODO: clean this up !*/ +static int amdgpu_gfx_index = offsetof(struct amdgpu_device, gfx.gfx_ring[0]); +static int cayman_cp1_index = offsetof(struct amdgpu_device, gfx.compute_ring[0]); +static int cayman_cp2_index = offsetof(struct amdgpu_device, gfx.compute_ring[1]); +static int amdgpu_dma1_index = offsetof(struct amdgpu_device, sdma[0].ring); +static int amdgpu_dma2_index = offsetof(struct amdgpu_device, sdma[1].ring); +static int r600_uvd_index = offsetof(struct amdgpu_device, uvd.ring); +static int si_vce1_index = offsetof(struct amdgpu_device, vce.ring[0]); +static int si_vce2_index = offsetof(struct amdgpu_device, vce.ring[1]); + +static struct drm_info_list amdgpu_debugfs_ring_info_list[] = { + {"amdgpu_ring_gfx", amdgpu_debugfs_ring_info, 0, &amdgpu_gfx_index}, + {"amdgpu_ring_cp1", amdgpu_debugfs_ring_info, 0, &cayman_cp1_index}, + {"amdgpu_ring_cp2", amdgpu_debugfs_ring_info, 0, &cayman_cp2_index}, + {"amdgpu_ring_dma1", amdgpu_debugfs_ring_info, 0, &amdgpu_dma1_index}, + {"amdgpu_ring_dma2", amdgpu_debugfs_ring_info, 0, &amdgpu_dma2_index}, + {"amdgpu_ring_uvd", amdgpu_debugfs_ring_info, 0, &r600_uvd_index}, + {"amdgpu_ring_vce1", amdgpu_debugfs_ring_info, 0, &si_vce1_index}, + {"amdgpu_ring_vce2", amdgpu_debugfs_ring_info, 0, &si_vce2_index}, +}; + +#endif + +static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) +{ +#if defined(CONFIG_DEBUG_FS) + unsigned i; + for (i = 0; i < ARRAY_SIZE(amdgpu_debugfs_ring_info_list); ++i) { + struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i]; + int roffset = *(int*)amdgpu_debugfs_ring_info_list[i].data; + struct amdgpu_ring *other = (void *)(((uint8_t*)adev) + roffset); + unsigned r; + + if (other != ring) + continue; + + r = amdgpu_debugfs_add_files(adev, info, 1); + if (r) + return r; + } +#endif + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c new file mode 100644 index 000000000000..eb20987ce18d --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c @@ -0,0 +1,419 @@ +/* + * Copyright 2011 Red Hat Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: + * Jerome Glisse + */ +/* Algorithm: + * + * We store the last allocated bo in "hole", we always try to allocate + * after the last allocated bo. Principle is that in a linear GPU ring + * progression was is after last is the oldest bo we allocated and thus + * the first one that should no longer be in use by the GPU. + * + * If it's not the case we skip over the bo after last to the closest + * done bo if such one exist. If none exist and we are not asked to + * block we report failure to allocate. + * + * If we are asked to block we wait on all the oldest fence of all + * rings. We just wait for any of those fence to complete. + */ +#include +#include "amdgpu.h" + +static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo); +static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager); + +int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, + struct amdgpu_sa_manager *sa_manager, + unsigned size, u32 align, u32 domain) +{ + int i, r; + + init_waitqueue_head(&sa_manager->wq); + sa_manager->bo = NULL; + sa_manager->size = size; + sa_manager->domain = domain; + sa_manager->align = align; + sa_manager->hole = &sa_manager->olist; + INIT_LIST_HEAD(&sa_manager->olist); + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + INIT_LIST_HEAD(&sa_manager->flist[i]); + } + + r = amdgpu_bo_create(adev, size, align, true, + domain, 0, NULL, &sa_manager->bo); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r); + return r; + } + + return r; +} + +void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev, + struct amdgpu_sa_manager *sa_manager) +{ + struct amdgpu_sa_bo *sa_bo, *tmp; + + if (!list_empty(&sa_manager->olist)) { + sa_manager->hole = &sa_manager->olist, + amdgpu_sa_bo_try_free(sa_manager); + if (!list_empty(&sa_manager->olist)) { + dev_err(adev->dev, "sa_manager is not empty, clearing anyway\n"); + } + } + list_for_each_entry_safe(sa_bo, tmp, &sa_manager->olist, olist) { + amdgpu_sa_bo_remove_locked(sa_bo); + } + amdgpu_bo_unref(&sa_manager->bo); + sa_manager->size = 0; +} + +int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev, + struct amdgpu_sa_manager *sa_manager) +{ + int r; + + if (sa_manager->bo == NULL) { + dev_err(adev->dev, "no bo for sa manager\n"); + return -EINVAL; + } + + /* map the buffer */ + r = amdgpu_bo_reserve(sa_manager->bo, false); + if (r) { + dev_err(adev->dev, "(%d) failed to reserve manager bo\n", r); + return r; + } + r = amdgpu_bo_pin(sa_manager->bo, sa_manager->domain, &sa_manager->gpu_addr); + if (r) { + amdgpu_bo_unreserve(sa_manager->bo); + dev_err(adev->dev, "(%d) failed to pin manager bo\n", r); + return r; + } + r = amdgpu_bo_kmap(sa_manager->bo, &sa_manager->cpu_ptr); + amdgpu_bo_unreserve(sa_manager->bo); + return r; +} + +int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev, + struct amdgpu_sa_manager *sa_manager) +{ + int r; + + if (sa_manager->bo == NULL) { + dev_err(adev->dev, "no bo for sa manager\n"); + return -EINVAL; + } + + r = amdgpu_bo_reserve(sa_manager->bo, false); + if (!r) { + amdgpu_bo_kunmap(sa_manager->bo); + amdgpu_bo_unpin(sa_manager->bo); + amdgpu_bo_unreserve(sa_manager->bo); + } + return r; +} + +static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo) +{ + struct amdgpu_sa_manager *sa_manager = sa_bo->manager; + if (sa_manager->hole == &sa_bo->olist) { + sa_manager->hole = sa_bo->olist.prev; + } + list_del_init(&sa_bo->olist); + list_del_init(&sa_bo->flist); + amdgpu_fence_unref(&sa_bo->fence); + kfree(sa_bo); +} + +static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager) +{ + struct amdgpu_sa_bo *sa_bo, *tmp; + + if (sa_manager->hole->next == &sa_manager->olist) + return; + + sa_bo = list_entry(sa_manager->hole->next, struct amdgpu_sa_bo, olist); + list_for_each_entry_safe_from(sa_bo, tmp, &sa_manager->olist, olist) { + if (sa_bo->fence == NULL || !amdgpu_fence_signaled(sa_bo->fence)) { + return; + } + amdgpu_sa_bo_remove_locked(sa_bo); + } +} + +static inline unsigned amdgpu_sa_bo_hole_soffset(struct amdgpu_sa_manager *sa_manager) +{ + struct list_head *hole = sa_manager->hole; + + if (hole != &sa_manager->olist) { + return list_entry(hole, struct amdgpu_sa_bo, olist)->eoffset; + } + return 0; +} + +static inline unsigned amdgpu_sa_bo_hole_eoffset(struct amdgpu_sa_manager *sa_manager) +{ + struct list_head *hole = sa_manager->hole; + + if (hole->next != &sa_manager->olist) { + return list_entry(hole->next, struct amdgpu_sa_bo, olist)->soffset; + } + return sa_manager->size; +} + +static bool amdgpu_sa_bo_try_alloc(struct amdgpu_sa_manager *sa_manager, + struct amdgpu_sa_bo *sa_bo, + unsigned size, unsigned align) +{ + unsigned soffset, eoffset, wasted; + + soffset = amdgpu_sa_bo_hole_soffset(sa_manager); + eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager); + wasted = (align - (soffset % align)) % align; + + if ((eoffset - soffset) >= (size + wasted)) { + soffset += wasted; + + sa_bo->manager = sa_manager; + sa_bo->soffset = soffset; + sa_bo->eoffset = soffset + size; + list_add(&sa_bo->olist, sa_manager->hole); + INIT_LIST_HEAD(&sa_bo->flist); + sa_manager->hole = &sa_bo->olist; + return true; + } + return false; +} + +/** + * amdgpu_sa_event - Check if we can stop waiting + * + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to allocate + * @align: alignment we need to match + * + * Check if either there is a fence we can wait for or + * enough free memory to satisfy the allocation directly + */ +static bool amdgpu_sa_event(struct amdgpu_sa_manager *sa_manager, + unsigned size, unsigned align) +{ + unsigned soffset, eoffset, wasted; + int i; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + if (!list_empty(&sa_manager->flist[i])) { + return true; + } + } + + soffset = amdgpu_sa_bo_hole_soffset(sa_manager); + eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager); + wasted = (align - (soffset % align)) % align; + + if ((eoffset - soffset) >= (size + wasted)) { + return true; + } + + return false; +} + +static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager, + struct amdgpu_fence **fences, + unsigned *tries) +{ + struct amdgpu_sa_bo *best_bo = NULL; + unsigned i, soffset, best, tmp; + + /* if hole points to the end of the buffer */ + if (sa_manager->hole->next == &sa_manager->olist) { + /* try again with its beginning */ + sa_manager->hole = &sa_manager->olist; + return true; + } + + soffset = amdgpu_sa_bo_hole_soffset(sa_manager); + /* to handle wrap around we add sa_manager->size */ + best = sa_manager->size * 2; + /* go over all fence list and try to find the closest sa_bo + * of the current last + */ + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_sa_bo *sa_bo; + + if (list_empty(&sa_manager->flist[i])) { + continue; + } + + sa_bo = list_first_entry(&sa_manager->flist[i], + struct amdgpu_sa_bo, flist); + + if (!amdgpu_fence_signaled(sa_bo->fence)) { + fences[i] = sa_bo->fence; + continue; + } + + /* limit the number of tries each ring gets */ + if (tries[i] > 2) { + continue; + } + + tmp = sa_bo->soffset; + if (tmp < soffset) { + /* wrap around, pretend it's after */ + tmp += sa_manager->size; + } + tmp -= soffset; + if (tmp < best) { + /* this sa bo is the closest one */ + best = tmp; + best_bo = sa_bo; + } + } + + if (best_bo) { + ++tries[best_bo->fence->ring->idx]; + sa_manager->hole = best_bo->olist.prev; + + /* we knew that this one is signaled, + so it's save to remote it */ + amdgpu_sa_bo_remove_locked(best_bo); + return true; + } + return false; +} + +int amdgpu_sa_bo_new(struct amdgpu_device *adev, + struct amdgpu_sa_manager *sa_manager, + struct amdgpu_sa_bo **sa_bo, + unsigned size, unsigned align) +{ + struct amdgpu_fence *fences[AMDGPU_MAX_RINGS]; + unsigned tries[AMDGPU_MAX_RINGS]; + int i, r; + + BUG_ON(align > sa_manager->align); + BUG_ON(size > sa_manager->size); + + *sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL); + if ((*sa_bo) == NULL) { + return -ENOMEM; + } + (*sa_bo)->manager = sa_manager; + (*sa_bo)->fence = NULL; + INIT_LIST_HEAD(&(*sa_bo)->olist); + INIT_LIST_HEAD(&(*sa_bo)->flist); + + spin_lock(&sa_manager->wq.lock); + do { + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + fences[i] = NULL; + tries[i] = 0; + } + + do { + amdgpu_sa_bo_try_free(sa_manager); + + if (amdgpu_sa_bo_try_alloc(sa_manager, *sa_bo, + size, align)) { + spin_unlock(&sa_manager->wq.lock); + return 0; + } + + /* see if we can skip over some allocations */ + } while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries)); + + spin_unlock(&sa_manager->wq.lock); + r = amdgpu_fence_wait_any(adev, fences, false); + spin_lock(&sa_manager->wq.lock); + /* if we have nothing to wait for block */ + if (r == -ENOENT) { + r = wait_event_interruptible_locked( + sa_manager->wq, + amdgpu_sa_event(sa_manager, size, align) + ); + } + + } while (!r); + + spin_unlock(&sa_manager->wq.lock); + kfree(*sa_bo); + *sa_bo = NULL; + return r; +} + +void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo, + struct amdgpu_fence *fence) +{ + struct amdgpu_sa_manager *sa_manager; + + if (sa_bo == NULL || *sa_bo == NULL) { + return; + } + + sa_manager = (*sa_bo)->manager; + spin_lock(&sa_manager->wq.lock); + if (fence && !amdgpu_fence_signaled(fence)) { + (*sa_bo)->fence = amdgpu_fence_ref(fence); + list_add_tail(&(*sa_bo)->flist, + &sa_manager->flist[fence->ring->idx]); + } else { + amdgpu_sa_bo_remove_locked(*sa_bo); + } + wake_up_all_locked(&sa_manager->wq); + spin_unlock(&sa_manager->wq.lock); + *sa_bo = NULL; +} + +#if defined(CONFIG_DEBUG_FS) +void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, + struct seq_file *m) +{ + struct amdgpu_sa_bo *i; + + spin_lock(&sa_manager->wq.lock); + list_for_each_entry(i, &sa_manager->olist, olist) { + uint64_t soffset = i->soffset + sa_manager->gpu_addr; + uint64_t eoffset = i->eoffset + sa_manager->gpu_addr; + if (&i->olist == sa_manager->hole) { + seq_printf(m, ">"); + } else { + seq_printf(m, " "); + } + seq_printf(m, "[0x%010llx 0x%010llx] size %8lld", + soffset, eoffset, eoffset - soffset); + if (i->fence) { + seq_printf(m, " protected by 0x%016llx on ring %d", + i->fence->seq, i->fence->ring->idx); + } + seq_printf(m, "\n"); + } + spin_unlock(&sa_manager->wq.lock); +} +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c new file mode 100644 index 000000000000..d6d41a42ab65 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c @@ -0,0 +1,102 @@ +/* + * Copyright 2011 Christian König. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: + * Christian König + */ +#include +#include "amdgpu.h" +#include "amdgpu_trace.h" + +int amdgpu_semaphore_create(struct amdgpu_device *adev, + struct amdgpu_semaphore **semaphore) +{ + int r; + + *semaphore = kmalloc(sizeof(struct amdgpu_semaphore), GFP_KERNEL); + if (*semaphore == NULL) { + return -ENOMEM; + } + r = amdgpu_sa_bo_new(adev, &adev->ring_tmp_bo, + &(*semaphore)->sa_bo, 8, 8); + if (r) { + kfree(*semaphore); + *semaphore = NULL; + return r; + } + (*semaphore)->waiters = 0; + (*semaphore)->gpu_addr = amdgpu_sa_bo_gpu_addr((*semaphore)->sa_bo); + + *((uint64_t *)amdgpu_sa_bo_cpu_addr((*semaphore)->sa_bo)) = 0; + + return 0; +} + +bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore) +{ + trace_amdgpu_semaphore_signale(ring->idx, semaphore); + + if (amdgpu_ring_emit_semaphore(ring, semaphore, false)) { + --semaphore->waiters; + + /* for debugging lockup only, used by sysfs debug files */ + ring->last_semaphore_signal_addr = semaphore->gpu_addr; + return true; + } + return false; +} + +bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore) +{ + trace_amdgpu_semaphore_wait(ring->idx, semaphore); + + if (amdgpu_ring_emit_semaphore(ring, semaphore, true)) { + ++semaphore->waiters; + + /* for debugging lockup only, used by sysfs debug files */ + ring->last_semaphore_wait_addr = semaphore->gpu_addr; + return true; + } + return false; +} + +void amdgpu_semaphore_free(struct amdgpu_device *adev, + struct amdgpu_semaphore **semaphore, + struct amdgpu_fence *fence) +{ + if (semaphore == NULL || *semaphore == NULL) { + return; + } + if ((*semaphore)->waiters > 0) { + dev_err(adev->dev, "semaphore %p has more waiters than signalers," + " hardware lockup imminent!\n", *semaphore); + } + amdgpu_sa_bo_free(adev, &(*semaphore)->sa_bo, fence); + kfree(*semaphore); + *semaphore = NULL; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c new file mode 100644 index 000000000000..855d56ac7115 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -0,0 +1,231 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: + * Christian König + */ + +#include +#include "amdgpu.h" +#include "amdgpu_trace.h" + +/** + * amdgpu_sync_create - zero init sync object + * + * @sync: sync object to initialize + * + * Just clear the sync object for now. + */ +void amdgpu_sync_create(struct amdgpu_sync *sync) +{ + unsigned i; + + for (i = 0; i < AMDGPU_NUM_SYNCS; ++i) + sync->semaphores[i] = NULL; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) + sync->sync_to[i] = NULL; + + sync->last_vm_update = NULL; +} + +/** + * amdgpu_sync_fence - use the semaphore to sync to a fence + * + * @sync: sync object to add fence to + * @fence: fence to sync to + * + * Sync to the fence using the semaphore objects + */ +void amdgpu_sync_fence(struct amdgpu_sync *sync, + struct amdgpu_fence *fence) +{ + struct amdgpu_fence *other; + + if (!fence) + return; + + other = sync->sync_to[fence->ring->idx]; + sync->sync_to[fence->ring->idx] = amdgpu_fence_ref( + amdgpu_fence_later(fence, other)); + amdgpu_fence_unref(&other); + + if (fence->owner == AMDGPU_FENCE_OWNER_VM) { + other = sync->last_vm_update; + sync->last_vm_update = amdgpu_fence_ref( + amdgpu_fence_later(fence, other)); + amdgpu_fence_unref(&other); + } +} + +/** + * amdgpu_sync_resv - use the semaphores to sync to a reservation object + * + * @sync: sync object to add fences from reservation object to + * @resv: reservation object with embedded fence + * @shared: true if we should only sync to the exclusive fence + * + * Sync to the fence using the semaphore objects + */ +int amdgpu_sync_resv(struct amdgpu_device *adev, + struct amdgpu_sync *sync, + struct reservation_object *resv, + void *owner) +{ + struct reservation_object_list *flist; + struct fence *f; + struct amdgpu_fence *fence; + unsigned i; + int r = 0; + + /* always sync to the exclusive fence */ + f = reservation_object_get_excl(resv); + fence = f ? to_amdgpu_fence(f) : NULL; + if (fence && fence->ring->adev == adev) + amdgpu_sync_fence(sync, fence); + else if (f) + r = fence_wait(f, true); + + flist = reservation_object_get_list(resv); + if (!flist || r) + return r; + + for (i = 0; i < flist->shared_count; ++i) { + f = rcu_dereference_protected(flist->shared[i], + reservation_object_held(resv)); + fence = to_amdgpu_fence(f); + if (fence && fence->ring->adev == adev) { + if (fence->owner != owner || + fence->owner == AMDGPU_FENCE_OWNER_UNDEFINED) + amdgpu_sync_fence(sync, fence); + } else { + r = fence_wait(f, true); + if (r) + break; + } + } + return r; +} + +/** + * amdgpu_sync_rings - sync ring to all registered fences + * + * @sync: sync object to use + * @ring: ring that needs sync + * + * Ensure that all registered fences are signaled before letting + * the ring continue. The caller must hold the ring lock. + */ +int amdgpu_sync_rings(struct amdgpu_sync *sync, + struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + unsigned count = 0; + int i, r; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_fence *fence = sync->sync_to[i]; + struct amdgpu_semaphore *semaphore; + struct amdgpu_ring *other = adev->rings[i]; + + /* check if we really need to sync */ + if (!amdgpu_fence_need_sync(fence, ring)) + continue; + + /* prevent GPU deadlocks */ + if (!other->ready) { + dev_err(adev->dev, "Syncing to a disabled ring!"); + return -EINVAL; + } + + if (count >= AMDGPU_NUM_SYNCS) { + /* not enough room, wait manually */ + r = amdgpu_fence_wait(fence, false); + if (r) + return r; + continue; + } + r = amdgpu_semaphore_create(adev, &semaphore); + if (r) + return r; + + sync->semaphores[count++] = semaphore; + + /* allocate enough space for sync command */ + r = amdgpu_ring_alloc(other, 16); + if (r) + return r; + + /* emit the signal semaphore */ + if (!amdgpu_semaphore_emit_signal(other, semaphore)) { + /* signaling wasn't successful wait manually */ + amdgpu_ring_undo(other); + r = amdgpu_fence_wait(fence, false); + if (r) + return r; + continue; + } + + /* we assume caller has already allocated space on waiters ring */ + if (!amdgpu_semaphore_emit_wait(ring, semaphore)) { + /* waiting wasn't successful wait manually */ + amdgpu_ring_undo(other); + r = amdgpu_fence_wait(fence, false); + if (r) + return r; + continue; + } + + amdgpu_ring_commit(other); + amdgpu_fence_note_sync(fence, ring); + } + + return 0; +} + +/** + * amdgpu_sync_free - free the sync object + * + * @adev: amdgpu_device pointer + * @sync: sync object to use + * @fence: fence to use for the free + * + * Free the sync object by freeing all semaphores in it. + */ +void amdgpu_sync_free(struct amdgpu_device *adev, + struct amdgpu_sync *sync, + struct amdgpu_fence *fence) +{ + unsigned i; + + for (i = 0; i < AMDGPU_NUM_SYNCS; ++i) + amdgpu_semaphore_free(adev, &sync->semaphores[i], fence); + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) + amdgpu_fence_unref(&sync->sync_to[i]); + + amdgpu_fence_unref(&sync->last_vm_update); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c new file mode 100644 index 000000000000..df202999fbfe --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c @@ -0,0 +1,552 @@ +/* + * Copyright 2009 VMware, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Michel Dänzer + */ +#include +#include +#include "amdgpu.h" +#include "amdgpu_uvd.h" +#include "amdgpu_vce.h" + +/* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */ +static void amdgpu_do_test_moves(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; + struct amdgpu_bo *vram_obj = NULL; + struct amdgpu_bo **gtt_obj = NULL; + uint64_t gtt_addr, vram_addr; + unsigned n, size; + int i, r; + + size = 1024 * 1024; + + /* Number of tests = + * (Total GTT - IB pool - writeback page - ring buffers) / test size + */ + n = adev->mc.gtt_size - AMDGPU_IB_POOL_SIZE*64*1024; + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) + if (adev->rings[i]) + n -= adev->rings[i]->ring_size; + if (adev->wb.wb_obj) + n -= AMDGPU_GPU_PAGE_SIZE; + if (adev->irq.ih.ring_obj) + n -= adev->irq.ih.ring_size; + n /= size; + + gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL); + if (!gtt_obj) { + DRM_ERROR("Failed to allocate %d pointers\n", n); + r = 1; + goto out_cleanup; + } + + r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0, + NULL, &vram_obj); + if (r) { + DRM_ERROR("Failed to create VRAM object\n"); + goto out_cleanup; + } + r = amdgpu_bo_reserve(vram_obj, false); + if (unlikely(r != 0)) + goto out_unref; + r = amdgpu_bo_pin(vram_obj, AMDGPU_GEM_DOMAIN_VRAM, &vram_addr); + if (r) { + DRM_ERROR("Failed to pin VRAM object\n"); + goto out_unres; + } + for (i = 0; i < n; i++) { + void *gtt_map, *vram_map; + void **gtt_start, **gtt_end; + void **vram_start, **vram_end; + struct amdgpu_fence *fence = NULL; + + r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, NULL, gtt_obj + i); + if (r) { + DRM_ERROR("Failed to create GTT object %d\n", i); + goto out_lclean; + } + + r = amdgpu_bo_reserve(gtt_obj[i], false); + if (unlikely(r != 0)) + goto out_lclean_unref; + r = amdgpu_bo_pin(gtt_obj[i], AMDGPU_GEM_DOMAIN_GTT, >t_addr); + if (r) { + DRM_ERROR("Failed to pin GTT object %d\n", i); + goto out_lclean_unres; + } + + r = amdgpu_bo_kmap(gtt_obj[i], >t_map); + if (r) { + DRM_ERROR("Failed to map GTT object %d\n", i); + goto out_lclean_unpin; + } + + for (gtt_start = gtt_map, gtt_end = gtt_map + size; + gtt_start < gtt_end; + gtt_start++) + *gtt_start = gtt_start; + + amdgpu_bo_kunmap(gtt_obj[i]); + + r = amdgpu_copy_buffer(ring, gtt_addr, vram_addr, + size, NULL, &fence); + + if (r) { + DRM_ERROR("Failed GTT->VRAM copy %d\n", i); + goto out_lclean_unpin; + } + + r = amdgpu_fence_wait(fence, false); + if (r) { + DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i); + goto out_lclean_unpin; + } + + amdgpu_fence_unref(&fence); + + r = amdgpu_bo_kmap(vram_obj, &vram_map); + if (r) { + DRM_ERROR("Failed to map VRAM object after copy %d\n", i); + goto out_lclean_unpin; + } + + for (gtt_start = gtt_map, gtt_end = gtt_map + size, + vram_start = vram_map, vram_end = vram_map + size; + vram_start < vram_end; + gtt_start++, vram_start++) { + if (*vram_start != gtt_start) { + DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, " + "expected 0x%p (GTT/VRAM offset " + "0x%16llx/0x%16llx)\n", + i, *vram_start, gtt_start, + (unsigned long long) + (gtt_addr - adev->mc.gtt_start + + (void*)gtt_start - gtt_map), + (unsigned long long) + (vram_addr - adev->mc.vram_start + + (void*)gtt_start - gtt_map)); + amdgpu_bo_kunmap(vram_obj); + goto out_lclean_unpin; + } + *vram_start = vram_start; + } + + amdgpu_bo_kunmap(vram_obj); + + r = amdgpu_copy_buffer(ring, vram_addr, gtt_addr, + size, NULL, &fence); + + if (r) { + DRM_ERROR("Failed VRAM->GTT copy %d\n", i); + goto out_lclean_unpin; + } + + r = amdgpu_fence_wait(fence, false); + if (r) { + DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i); + goto out_lclean_unpin; + } + + amdgpu_fence_unref(&fence); + + r = amdgpu_bo_kmap(gtt_obj[i], >t_map); + if (r) { + DRM_ERROR("Failed to map GTT object after copy %d\n", i); + goto out_lclean_unpin; + } + + for (gtt_start = gtt_map, gtt_end = gtt_map + size, + vram_start = vram_map, vram_end = vram_map + size; + gtt_start < gtt_end; + gtt_start++, vram_start++) { + if (*gtt_start != vram_start) { + DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, " + "expected 0x%p (VRAM/GTT offset " + "0x%16llx/0x%16llx)\n", + i, *gtt_start, vram_start, + (unsigned long long) + (vram_addr - adev->mc.vram_start + + (void*)vram_start - vram_map), + (unsigned long long) + (gtt_addr - adev->mc.gtt_start + + (void*)vram_start - vram_map)); + amdgpu_bo_kunmap(gtt_obj[i]); + goto out_lclean_unpin; + } + } + + amdgpu_bo_kunmap(gtt_obj[i]); + + DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", + gtt_addr - adev->mc.gtt_start); + continue; + +out_lclean_unpin: + amdgpu_bo_unpin(gtt_obj[i]); +out_lclean_unres: + amdgpu_bo_unreserve(gtt_obj[i]); +out_lclean_unref: + amdgpu_bo_unref(>t_obj[i]); +out_lclean: + for (--i; i >= 0; --i) { + amdgpu_bo_unpin(gtt_obj[i]); + amdgpu_bo_unreserve(gtt_obj[i]); + amdgpu_bo_unref(>t_obj[i]); + } + if (fence) + amdgpu_fence_unref(&fence); + break; + } + + amdgpu_bo_unpin(vram_obj); +out_unres: + amdgpu_bo_unreserve(vram_obj); +out_unref: + amdgpu_bo_unref(&vram_obj); +out_cleanup: + kfree(gtt_obj); + if (r) { + printk(KERN_WARNING "Error while testing BO move.\n"); + } +} + +void amdgpu_test_moves(struct amdgpu_device *adev) +{ + if (adev->mman.buffer_funcs) + amdgpu_do_test_moves(adev); +} + +static int amdgpu_test_create_and_emit_fence(struct amdgpu_device *adev, + struct amdgpu_ring *ring, + struct amdgpu_fence **fence) +{ + uint32_t handle = ring->idx ^ 0xdeafbeef; + int r; + + if (ring == &adev->uvd.ring) { + r = amdgpu_uvd_get_create_msg(ring, handle, NULL); + if (r) { + DRM_ERROR("Failed to get dummy create msg\n"); + return r; + } + + r = amdgpu_uvd_get_destroy_msg(ring, handle, fence); + if (r) { + DRM_ERROR("Failed to get dummy destroy msg\n"); + return r; + } + + } else if (ring == &adev->vce.ring[0] || + ring == &adev->vce.ring[1]) { + r = amdgpu_vce_get_create_msg(ring, handle, NULL); + if (r) { + DRM_ERROR("Failed to get dummy create msg\n"); + return r; + } + + r = amdgpu_vce_get_destroy_msg(ring, handle, fence); + if (r) { + DRM_ERROR("Failed to get dummy destroy msg\n"); + return r; + } + + } else { + r = amdgpu_ring_lock(ring, 64); + if (r) { + DRM_ERROR("Failed to lock ring A %d\n", ring->idx); + return r; + } + amdgpu_fence_emit(ring, AMDGPU_FENCE_OWNER_UNDEFINED, fence); + amdgpu_ring_unlock_commit(ring); + } + return 0; +} + +void amdgpu_test_ring_sync(struct amdgpu_device *adev, + struct amdgpu_ring *ringA, + struct amdgpu_ring *ringB) +{ + struct amdgpu_fence *fence1 = NULL, *fence2 = NULL; + struct amdgpu_semaphore *semaphore = NULL; + int r; + + r = amdgpu_semaphore_create(adev, &semaphore); + if (r) { + DRM_ERROR("Failed to create semaphore\n"); + goto out_cleanup; + } + + r = amdgpu_ring_lock(ringA, 64); + if (r) { + DRM_ERROR("Failed to lock ring A %d\n", ringA->idx); + goto out_cleanup; + } + amdgpu_semaphore_emit_wait(ringA, semaphore); + amdgpu_ring_unlock_commit(ringA); + + r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence1); + if (r) + goto out_cleanup; + + r = amdgpu_ring_lock(ringA, 64); + if (r) { + DRM_ERROR("Failed to lock ring A %d\n", ringA->idx); + goto out_cleanup; + } + amdgpu_semaphore_emit_wait(ringA, semaphore); + amdgpu_ring_unlock_commit(ringA); + + r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence2); + if (r) + goto out_cleanup; + + mdelay(1000); + + if (amdgpu_fence_signaled(fence1)) { + DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n"); + goto out_cleanup; + } + + r = amdgpu_ring_lock(ringB, 64); + if (r) { + DRM_ERROR("Failed to lock ring B %p\n", ringB); + goto out_cleanup; + } + amdgpu_semaphore_emit_signal(ringB, semaphore); + amdgpu_ring_unlock_commit(ringB); + + r = amdgpu_fence_wait(fence1, false); + if (r) { + DRM_ERROR("Failed to wait for sync fence 1\n"); + goto out_cleanup; + } + + mdelay(1000); + + if (amdgpu_fence_signaled(fence2)) { + DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n"); + goto out_cleanup; + } + + r = amdgpu_ring_lock(ringB, 64); + if (r) { + DRM_ERROR("Failed to lock ring B %p\n", ringB); + goto out_cleanup; + } + amdgpu_semaphore_emit_signal(ringB, semaphore); + amdgpu_ring_unlock_commit(ringB); + + r = amdgpu_fence_wait(fence2, false); + if (r) { + DRM_ERROR("Failed to wait for sync fence 1\n"); + goto out_cleanup; + } + +out_cleanup: + amdgpu_semaphore_free(adev, &semaphore, NULL); + + if (fence1) + amdgpu_fence_unref(&fence1); + + if (fence2) + amdgpu_fence_unref(&fence2); + + if (r) + printk(KERN_WARNING "Error while testing ring sync (%d).\n", r); +} + +static void amdgpu_test_ring_sync2(struct amdgpu_device *adev, + struct amdgpu_ring *ringA, + struct amdgpu_ring *ringB, + struct amdgpu_ring *ringC) +{ + struct amdgpu_fence *fenceA = NULL, *fenceB = NULL; + struct amdgpu_semaphore *semaphore = NULL; + bool sigA, sigB; + int i, r; + + r = amdgpu_semaphore_create(adev, &semaphore); + if (r) { + DRM_ERROR("Failed to create semaphore\n"); + goto out_cleanup; + } + + r = amdgpu_ring_lock(ringA, 64); + if (r) { + DRM_ERROR("Failed to lock ring A %d\n", ringA->idx); + goto out_cleanup; + } + amdgpu_semaphore_emit_wait(ringA, semaphore); + amdgpu_ring_unlock_commit(ringA); + + r = amdgpu_test_create_and_emit_fence(adev, ringA, &fenceA); + if (r) + goto out_cleanup; + + r = amdgpu_ring_lock(ringB, 64); + if (r) { + DRM_ERROR("Failed to lock ring B %d\n", ringB->idx); + goto out_cleanup; + } + amdgpu_semaphore_emit_wait(ringB, semaphore); + amdgpu_ring_unlock_commit(ringB); + r = amdgpu_test_create_and_emit_fence(adev, ringB, &fenceB); + if (r) + goto out_cleanup; + + mdelay(1000); + + if (amdgpu_fence_signaled(fenceA)) { + DRM_ERROR("Fence A signaled without waiting for semaphore.\n"); + goto out_cleanup; + } + if (amdgpu_fence_signaled(fenceB)) { + DRM_ERROR("Fence B signaled without waiting for semaphore.\n"); + goto out_cleanup; + } + + r = amdgpu_ring_lock(ringC, 64); + if (r) { + DRM_ERROR("Failed to lock ring B %p\n", ringC); + goto out_cleanup; + } + amdgpu_semaphore_emit_signal(ringC, semaphore); + amdgpu_ring_unlock_commit(ringC); + + for (i = 0; i < 30; ++i) { + mdelay(100); + sigA = amdgpu_fence_signaled(fenceA); + sigB = amdgpu_fence_signaled(fenceB); + if (sigA || sigB) + break; + } + + if (!sigA && !sigB) { + DRM_ERROR("Neither fence A nor B has been signaled\n"); + goto out_cleanup; + } else if (sigA && sigB) { + DRM_ERROR("Both fence A and B has been signaled\n"); + goto out_cleanup; + } + + DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B'); + + r = amdgpu_ring_lock(ringC, 64); + if (r) { + DRM_ERROR("Failed to lock ring B %p\n", ringC); + goto out_cleanup; + } + amdgpu_semaphore_emit_signal(ringC, semaphore); + amdgpu_ring_unlock_commit(ringC); + + mdelay(1000); + + r = amdgpu_fence_wait(fenceA, false); + if (r) { + DRM_ERROR("Failed to wait for sync fence A\n"); + goto out_cleanup; + } + r = amdgpu_fence_wait(fenceB, false); + if (r) { + DRM_ERROR("Failed to wait for sync fence B\n"); + goto out_cleanup; + } + +out_cleanup: + amdgpu_semaphore_free(adev, &semaphore, NULL); + + if (fenceA) + amdgpu_fence_unref(&fenceA); + + if (fenceB) + amdgpu_fence_unref(&fenceB); + + if (r) + printk(KERN_WARNING "Error while testing ring sync (%d).\n", r); +} + +static bool amdgpu_test_sync_possible(struct amdgpu_ring *ringA, + struct amdgpu_ring *ringB) +{ + if (ringA == &ringA->adev->vce.ring[0] && + ringB == &ringB->adev->vce.ring[1]) + return false; + + return true; +} + +void amdgpu_test_syncing(struct amdgpu_device *adev) +{ + int i, j, k; + + for (i = 1; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_ring *ringA = adev->rings[i]; + if (!ringA || !ringA->ready) + continue; + + for (j = 0; j < i; ++j) { + struct amdgpu_ring *ringB = adev->rings[j]; + if (!ringB || !ringB->ready) + continue; + + if (!amdgpu_test_sync_possible(ringA, ringB)) + continue; + + DRM_INFO("Testing syncing between rings %d and %d...\n", i, j); + amdgpu_test_ring_sync(adev, ringA, ringB); + + DRM_INFO("Testing syncing between rings %d and %d...\n", j, i); + amdgpu_test_ring_sync(adev, ringB, ringA); + + for (k = 0; k < j; ++k) { + struct amdgpu_ring *ringC = adev->rings[k]; + if (!ringC || !ringC->ready) + continue; + + if (!amdgpu_test_sync_possible(ringA, ringC)) + continue; + + if (!amdgpu_test_sync_possible(ringB, ringC)) + continue; + + DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k); + amdgpu_test_ring_sync2(adev, ringA, ringB, ringC); + + DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j); + amdgpu_test_ring_sync2(adev, ringA, ringC, ringB); + + DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k); + amdgpu_test_ring_sync2(adev, ringB, ringA, ringC); + + DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i); + amdgpu_test_ring_sync2(adev, ringB, ringC, ringA); + + DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j); + amdgpu_test_ring_sync2(adev, ringC, ringA, ringB); + + DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i); + amdgpu_test_ring_sync2(adev, ringC, ringB, ringA); + } + } + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h new file mode 100644 index 000000000000..b57647e582d4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -0,0 +1,209 @@ +#if !defined(_AMDGPU_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _AMDGPU_TRACE_H_ + +#include +#include +#include + +#include + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM amdgpu +#define TRACE_SYSTEM_STRING __stringify(TRACE_SYSTEM) +#define TRACE_INCLUDE_FILE amdgpu_trace + +TRACE_EVENT(amdgpu_bo_create, + TP_PROTO(struct amdgpu_bo *bo), + TP_ARGS(bo), + TP_STRUCT__entry( + __field(struct amdgpu_bo *, bo) + __field(u32, pages) + ), + + TP_fast_assign( + __entry->bo = bo; + __entry->pages = bo->tbo.num_pages; + ), + TP_printk("bo=%p, pages=%u", __entry->bo, __entry->pages) +); + +TRACE_EVENT(amdgpu_cs, + TP_PROTO(struct amdgpu_cs_parser *p, int i), + TP_ARGS(p, i), + TP_STRUCT__entry( + __field(u32, ring) + __field(u32, dw) + __field(u32, fences) + ), + + TP_fast_assign( + __entry->ring = p->ibs[i].ring->idx; + __entry->dw = p->ibs[i].length_dw; + __entry->fences = amdgpu_fence_count_emitted( + p->ibs[i].ring); + ), + TP_printk("ring=%u, dw=%u, fences=%u", + __entry->ring, __entry->dw, + __entry->fences) +); + +TRACE_EVENT(amdgpu_vm_grab_id, + TP_PROTO(unsigned vmid, int ring), + TP_ARGS(vmid, ring), + TP_STRUCT__entry( + __field(u32, vmid) + __field(u32, ring) + ), + + TP_fast_assign( + __entry->vmid = vmid; + __entry->ring = ring; + ), + TP_printk("vmid=%u, ring=%u", __entry->vmid, __entry->ring) +); + +TRACE_EVENT(amdgpu_vm_bo_update, + TP_PROTO(struct amdgpu_bo_va_mapping *mapping), + TP_ARGS(mapping), + TP_STRUCT__entry( + __field(u64, soffset) + __field(u64, eoffset) + __field(u32, flags) + ), + + TP_fast_assign( + __entry->soffset = mapping->it.start; + __entry->eoffset = mapping->it.last + 1; + __entry->flags = mapping->flags; + ), + TP_printk("soffs=%010llx, eoffs=%010llx, flags=%08x", + __entry->soffset, __entry->eoffset, __entry->flags) +); + +TRACE_EVENT(amdgpu_vm_set_page, + TP_PROTO(uint64_t pe, uint64_t addr, unsigned count, + uint32_t incr, uint32_t flags), + TP_ARGS(pe, addr, count, incr, flags), + TP_STRUCT__entry( + __field(u64, pe) + __field(u64, addr) + __field(u32, count) + __field(u32, incr) + __field(u32, flags) + ), + + TP_fast_assign( + __entry->pe = pe; + __entry->addr = addr; + __entry->count = count; + __entry->incr = incr; + __entry->flags = flags; + ), + TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%08x, count=%u", + __entry->pe, __entry->addr, __entry->incr, + __entry->flags, __entry->count) +); + +TRACE_EVENT(amdgpu_vm_flush, + TP_PROTO(uint64_t pd_addr, unsigned ring, unsigned id), + TP_ARGS(pd_addr, ring, id), + TP_STRUCT__entry( + __field(u64, pd_addr) + __field(u32, ring) + __field(u32, id) + ), + + TP_fast_assign( + __entry->pd_addr = pd_addr; + __entry->ring = ring; + __entry->id = id; + ), + TP_printk("pd_addr=%010Lx, ring=%u, id=%u", + __entry->pd_addr, __entry->ring, __entry->id) +); + +DECLARE_EVENT_CLASS(amdgpu_fence_request, + + TP_PROTO(struct drm_device *dev, int ring, u32 seqno), + + TP_ARGS(dev, ring, seqno), + + TP_STRUCT__entry( + __field(u32, dev) + __field(int, ring) + __field(u32, seqno) + ), + + TP_fast_assign( + __entry->dev = dev->primary->index; + __entry->ring = ring; + __entry->seqno = seqno; + ), + + TP_printk("dev=%u, ring=%d, seqno=%u", + __entry->dev, __entry->ring, __entry->seqno) +); + +DEFINE_EVENT(amdgpu_fence_request, amdgpu_fence_emit, + + TP_PROTO(struct drm_device *dev, int ring, u32 seqno), + + TP_ARGS(dev, ring, seqno) +); + +DEFINE_EVENT(amdgpu_fence_request, amdgpu_fence_wait_begin, + + TP_PROTO(struct drm_device *dev, int ring, u32 seqno), + + TP_ARGS(dev, ring, seqno) +); + +DEFINE_EVENT(amdgpu_fence_request, amdgpu_fence_wait_end, + + TP_PROTO(struct drm_device *dev, int ring, u32 seqno), + + TP_ARGS(dev, ring, seqno) +); + +DECLARE_EVENT_CLASS(amdgpu_semaphore_request, + + TP_PROTO(int ring, struct amdgpu_semaphore *sem), + + TP_ARGS(ring, sem), + + TP_STRUCT__entry( + __field(int, ring) + __field(signed, waiters) + __field(uint64_t, gpu_addr) + ), + + TP_fast_assign( + __entry->ring = ring; + __entry->waiters = sem->waiters; + __entry->gpu_addr = sem->gpu_addr; + ), + + TP_printk("ring=%u, waiters=%d, addr=%010Lx", __entry->ring, + __entry->waiters, __entry->gpu_addr) +); + +DEFINE_EVENT(amdgpu_semaphore_request, amdgpu_semaphore_signale, + + TP_PROTO(int ring, struct amdgpu_semaphore *sem), + + TP_ARGS(ring, sem) +); + +DEFINE_EVENT(amdgpu_semaphore_request, amdgpu_semaphore_wait, + + TP_PROTO(int ring, struct amdgpu_semaphore *sem), + + TP_ARGS(ring, sem) +); + +#endif + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#include diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c new file mode 100644 index 000000000000..385b7e1d72f9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c @@ -0,0 +1,9 @@ +/* Copyright Red Hat Inc 2010. + * Author : Dave Airlie + */ +#include +#include +#include "amdgpu.h" + +#define CREATE_TRACE_POINTS +#include "amdgpu_trace.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c new file mode 100644 index 000000000000..120e6e7c4647 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -0,0 +1,1249 @@ +/* + * Copyright 2009 Jerome Glisse. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: + * Jerome Glisse + * Thomas Hellstrom + * Dave Airlie + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "amdgpu.h" +#include "bif/bif_4_1_d.h" + +#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) + +static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); +static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev); + +static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev) +{ + struct amdgpu_mman *mman; + struct amdgpu_device *adev; + + mman = container_of(bdev, struct amdgpu_mman, bdev); + adev = container_of(mman, struct amdgpu_device, mman); + return adev; +} + + +/* + * Global memory. + */ +static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref) +{ + return ttm_mem_global_init(ref->object); +} + +static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref) +{ + ttm_mem_global_release(ref->object); +} + +static int amdgpu_ttm_global_init(struct amdgpu_device *adev) +{ + struct drm_global_reference *global_ref; + int r; + + adev->mman.mem_global_referenced = false; + global_ref = &adev->mman.mem_global_ref; + global_ref->global_type = DRM_GLOBAL_TTM_MEM; + global_ref->size = sizeof(struct ttm_mem_global); + global_ref->init = &amdgpu_ttm_mem_global_init; + global_ref->release = &amdgpu_ttm_mem_global_release; + r = drm_global_item_ref(global_ref); + if (r != 0) { + DRM_ERROR("Failed setting up TTM memory accounting " + "subsystem.\n"); + return r; + } + + adev->mman.bo_global_ref.mem_glob = + adev->mman.mem_global_ref.object; + global_ref = &adev->mman.bo_global_ref.ref; + global_ref->global_type = DRM_GLOBAL_TTM_BO; + global_ref->size = sizeof(struct ttm_bo_global); + global_ref->init = &ttm_bo_global_init; + global_ref->release = &ttm_bo_global_release; + r = drm_global_item_ref(global_ref); + if (r != 0) { + DRM_ERROR("Failed setting up TTM BO subsystem.\n"); + drm_global_item_unref(&adev->mman.mem_global_ref); + return r; + } + + adev->mman.mem_global_referenced = true; + return 0; +} + +static void amdgpu_ttm_global_fini(struct amdgpu_device *adev) +{ + if (adev->mman.mem_global_referenced) { + drm_global_item_unref(&adev->mman.bo_global_ref.ref); + drm_global_item_unref(&adev->mman.mem_global_ref); + adev->mman.mem_global_referenced = false; + } +} + +static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) +{ + return 0; +} + +static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, + struct ttm_mem_type_manager *man) +{ + struct amdgpu_device *adev; + + adev = amdgpu_get_adev(bdev); + + switch (type) { + case TTM_PL_SYSTEM: + /* System memory */ + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; + man->available_caching = TTM_PL_MASK_CACHING; + man->default_caching = TTM_PL_FLAG_CACHED; + break; + case TTM_PL_TT: + man->func = &ttm_bo_manager_func; + man->gpu_offset = adev->mc.gtt_start; + man->available_caching = TTM_PL_MASK_CACHING; + man->default_caching = TTM_PL_FLAG_CACHED; + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; + break; + case TTM_PL_VRAM: + /* "On-card" video ram */ + man->func = &ttm_bo_manager_func; + man->gpu_offset = adev->mc.vram_start; + man->flags = TTM_MEMTYPE_FLAG_FIXED | + TTM_MEMTYPE_FLAG_MAPPABLE; + man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; + man->default_caching = TTM_PL_FLAG_WC; + break; + case AMDGPU_PL_GDS: + case AMDGPU_PL_GWS: + case AMDGPU_PL_OA: + /* On-chip GDS memory*/ + man->func = &ttm_bo_manager_func; + man->gpu_offset = 0; + man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA; + man->available_caching = TTM_PL_FLAG_UNCACHED; + man->default_caching = TTM_PL_FLAG_UNCACHED; + break; + default: + DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); + return -EINVAL; + } + return 0; +} + +static void amdgpu_evict_flags(struct ttm_buffer_object *bo, + struct ttm_placement *placement) +{ + struct amdgpu_bo *rbo; + static struct ttm_place placements = { + .fpfn = 0, + .lpfn = 0, + .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM + }; + + if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) { + placement->placement = &placements; + placement->busy_placement = &placements; + placement->num_placement = 1; + placement->num_busy_placement = 1; + return; + } + rbo = container_of(bo, struct amdgpu_bo, tbo); + switch (bo->mem.mem_type) { + case TTM_PL_VRAM: + if (rbo->adev->mman.buffer_funcs_ring->ready == false) + amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU); + else + amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT); + break; + case TTM_PL_TT: + default: + amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU); + } + *placement = rbo->placement; +} + +static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) +{ + struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo); + + return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); +} + +static void amdgpu_move_null(struct ttm_buffer_object *bo, + struct ttm_mem_reg *new_mem) +{ + struct ttm_mem_reg *old_mem = &bo->mem; + + BUG_ON(old_mem->mm_node != NULL); + *old_mem = *new_mem; + new_mem->mm_node = NULL; +} + +static int amdgpu_move_blit(struct ttm_buffer_object *bo, + bool evict, bool no_wait_gpu, + struct ttm_mem_reg *new_mem, + struct ttm_mem_reg *old_mem) +{ + struct amdgpu_device *adev; + struct amdgpu_ring *ring; + uint64_t old_start, new_start; + struct amdgpu_fence *fence; + int r; + + adev = amdgpu_get_adev(bo->bdev); + ring = adev->mman.buffer_funcs_ring; + old_start = old_mem->start << PAGE_SHIFT; + new_start = new_mem->start << PAGE_SHIFT; + + switch (old_mem->mem_type) { + case TTM_PL_VRAM: + old_start += adev->mc.vram_start; + break; + case TTM_PL_TT: + old_start += adev->mc.gtt_start; + break; + default: + DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); + return -EINVAL; + } + switch (new_mem->mem_type) { + case TTM_PL_VRAM: + new_start += adev->mc.vram_start; + break; + case TTM_PL_TT: + new_start += adev->mc.gtt_start; + break; + default: + DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); + return -EINVAL; + } + if (!ring->ready) { + DRM_ERROR("Trying to move memory with ring turned off.\n"); + return -EINVAL; + } + + BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0); + + r = amdgpu_copy_buffer(ring, old_start, new_start, + new_mem->num_pages * PAGE_SIZE, /* bytes */ + bo->resv, &fence); + /* FIXME: handle copy error */ + r = ttm_bo_move_accel_cleanup(bo, &fence->base, + evict, no_wait_gpu, new_mem); + amdgpu_fence_unref(&fence); + return r; +} + +static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, + bool evict, bool interruptible, + bool no_wait_gpu, + struct ttm_mem_reg *new_mem) +{ + struct amdgpu_device *adev; + struct ttm_mem_reg *old_mem = &bo->mem; + struct ttm_mem_reg tmp_mem; + struct ttm_place placements; + struct ttm_placement placement; + int r; + + adev = amdgpu_get_adev(bo->bdev); + tmp_mem = *new_mem; + tmp_mem.mm_node = NULL; + placement.num_placement = 1; + placement.placement = &placements; + placement.num_busy_placement = 1; + placement.busy_placement = &placements; + placements.fpfn = 0; + placements.lpfn = 0; + placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, + interruptible, no_wait_gpu); + if (unlikely(r)) { + return r; + } + + r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); + if (unlikely(r)) { + goto out_cleanup; + } + + r = ttm_tt_bind(bo->ttm, &tmp_mem); + if (unlikely(r)) { + goto out_cleanup; + } + r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); + if (unlikely(r)) { + goto out_cleanup; + } + r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); +out_cleanup: + ttm_bo_mem_put(bo, &tmp_mem); + return r; +} + +static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, + bool evict, bool interruptible, + bool no_wait_gpu, + struct ttm_mem_reg *new_mem) +{ + struct amdgpu_device *adev; + struct ttm_mem_reg *old_mem = &bo->mem; + struct ttm_mem_reg tmp_mem; + struct ttm_placement placement; + struct ttm_place placements; + int r; + + adev = amdgpu_get_adev(bo->bdev); + tmp_mem = *new_mem; + tmp_mem.mm_node = NULL; + placement.num_placement = 1; + placement.placement = &placements; + placement.num_busy_placement = 1; + placement.busy_placement = &placements; + placements.fpfn = 0; + placements.lpfn = 0; + placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, + interruptible, no_wait_gpu); + if (unlikely(r)) { + return r; + } + r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); + if (unlikely(r)) { + goto out_cleanup; + } + r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); + if (unlikely(r)) { + goto out_cleanup; + } +out_cleanup: + ttm_bo_mem_put(bo, &tmp_mem); + return r; +} + +static int amdgpu_bo_move(struct ttm_buffer_object *bo, + bool evict, bool interruptible, + bool no_wait_gpu, + struct ttm_mem_reg *new_mem) +{ + struct amdgpu_device *adev; + struct ttm_mem_reg *old_mem = &bo->mem; + int r; + + adev = amdgpu_get_adev(bo->bdev); + if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { + amdgpu_move_null(bo, new_mem); + return 0; + } + if ((old_mem->mem_type == TTM_PL_TT && + new_mem->mem_type == TTM_PL_SYSTEM) || + (old_mem->mem_type == TTM_PL_SYSTEM && + new_mem->mem_type == TTM_PL_TT)) { + /* bind is enough */ + amdgpu_move_null(bo, new_mem); + return 0; + } + if (adev->mman.buffer_funcs == NULL || + adev->mman.buffer_funcs_ring == NULL || + !adev->mman.buffer_funcs_ring->ready) { + /* use memcpy */ + goto memcpy; + } + + if (old_mem->mem_type == TTM_PL_VRAM && + new_mem->mem_type == TTM_PL_SYSTEM) { + r = amdgpu_move_vram_ram(bo, evict, interruptible, + no_wait_gpu, new_mem); + } else if (old_mem->mem_type == TTM_PL_SYSTEM && + new_mem->mem_type == TTM_PL_VRAM) { + r = amdgpu_move_ram_vram(bo, evict, interruptible, + no_wait_gpu, new_mem); + } else { + r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); + } + + if (r) { +memcpy: + r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); + if (r) { + return r; + } + } + + /* update statistics */ + atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); + return 0; +} + +static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) +{ + struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; + struct amdgpu_device *adev = amdgpu_get_adev(bdev); + + mem->bus.addr = NULL; + mem->bus.offset = 0; + mem->bus.size = mem->num_pages << PAGE_SHIFT; + mem->bus.base = 0; + mem->bus.is_iomem = false; + if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) + return -EINVAL; + switch (mem->mem_type) { + case TTM_PL_SYSTEM: + /* system memory */ + return 0; + case TTM_PL_TT: + break; + case TTM_PL_VRAM: + mem->bus.offset = mem->start << PAGE_SHIFT; + /* check if it's visible */ + if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size) + return -EINVAL; + mem->bus.base = adev->mc.aper_base; + mem->bus.is_iomem = true; +#ifdef __alpha__ + /* + * Alpha: use bus.addr to hold the ioremap() return, + * so we can modify bus.base below. + */ + if (mem->placement & TTM_PL_FLAG_WC) + mem->bus.addr = + ioremap_wc(mem->bus.base + mem->bus.offset, + mem->bus.size); + else + mem->bus.addr = + ioremap_nocache(mem->bus.base + mem->bus.offset, + mem->bus.size); + + /* + * Alpha: Use just the bus offset plus + * the hose/domain memory base for bus.base. + * It then can be used to build PTEs for VRAM + * access, as done in ttm_bo_vm_fault(). + */ + mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + + adev->ddev->hose->dense_mem_base; +#endif + break; + default: + return -EINVAL; + } + return 0; +} + +static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) +{ +} + +/* + * TTM backend functions. + */ +struct amdgpu_ttm_tt { + struct ttm_dma_tt ttm; + struct amdgpu_device *adev; + u64 offset; + uint64_t userptr; + struct mm_struct *usermm; + uint32_t userflags; +}; + +/* prepare the sg table with the user pages */ +static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) +{ + struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned pinned = 0, nents; + int r; + + int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); + enum dma_data_direction direction = write ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE; + + if (current->mm != gtt->usermm) + return -EPERM; + + if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { + /* check that we only pin down anonymous memory + to prevent problems with writeback */ + unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; + struct vm_area_struct *vma; + + vma = find_vma(gtt->usermm, gtt->userptr); + if (!vma || vma->vm_file || vma->vm_end < end) + return -EPERM; + } + + do { + unsigned num_pages = ttm->num_pages - pinned; + uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; + struct page **pages = ttm->pages + pinned; + + r = get_user_pages(current, current->mm, userptr, num_pages, + write, 0, pages, NULL); + if (r < 0) + goto release_pages; + + pinned += r; + + } while (pinned < ttm->num_pages); + + r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, + ttm->num_pages << PAGE_SHIFT, + GFP_KERNEL); + if (r) + goto release_sg; + + r = -ENOMEM; + nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); + if (nents != ttm->sg->nents) + goto release_sg; + + drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, + gtt->ttm.dma_address, ttm->num_pages); + + return 0; + +release_sg: + kfree(ttm->sg); + +release_pages: + release_pages(ttm->pages, pinned, 0); + return r; +} + +static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) +{ + struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); + struct amdgpu_ttm_tt *gtt = (void *)ttm; + struct scatterlist *sg; + int i; + + int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); + enum dma_data_direction direction = write ? + DMA_BIDIRECTIONAL : DMA_TO_DEVICE; + + /* double check that we don't free the table twice */ + if (!ttm->sg->sgl) + return; + + /* free the sg table and pages again */ + dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); + + for_each_sg(ttm->sg->sgl, sg, ttm->sg->nents, i) { + struct page *page = sg_page(sg); + + if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) + set_page_dirty(page); + + mark_page_accessed(page); + page_cache_release(page); + } + + sg_free_table(ttm->sg); +} + +static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, + struct ttm_mem_reg *bo_mem) +{ + struct amdgpu_ttm_tt *gtt = (void*)ttm; + uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); + int r; + + if (gtt->userptr) + amdgpu_ttm_tt_pin_userptr(ttm); + + gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); + if (!ttm->num_pages) { + WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", + ttm->num_pages, bo_mem, ttm); + } + + if (bo_mem->mem_type == AMDGPU_PL_GDS || + bo_mem->mem_type == AMDGPU_PL_GWS || + bo_mem->mem_type == AMDGPU_PL_OA) + return -EINVAL; + + r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, + ttm->pages, gtt->ttm.dma_address, flags); + + if (r) { + DRM_ERROR("failed to bind %lu pages at 0x%08X\n", + ttm->num_pages, (unsigned)gtt->offset); + return r; + } + return 0; +} + +static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ + if (gtt->adev->gart.ready) + amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); + + if (gtt->userptr) + amdgpu_ttm_tt_unpin_userptr(ttm); + + return 0; +} + +static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + ttm_dma_tt_fini(>t->ttm); + kfree(gtt); +} + +static struct ttm_backend_func amdgpu_backend_func = { + .bind = &amdgpu_ttm_backend_bind, + .unbind = &amdgpu_ttm_backend_unbind, + .destroy = &amdgpu_ttm_backend_destroy, +}; + +static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, + unsigned long size, uint32_t page_flags, + struct page *dummy_read_page) +{ + struct amdgpu_device *adev; + struct amdgpu_ttm_tt *gtt; + + adev = amdgpu_get_adev(bdev); + + gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); + if (gtt == NULL) { + return NULL; + } + gtt->ttm.ttm.func = &amdgpu_backend_func; + gtt->adev = adev; + if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { + kfree(gtt); + return NULL; + } + return >t->ttm.ttm; +} + +static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) +{ + struct amdgpu_device *adev; + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + int r; + bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); + + if (ttm->state != tt_unpopulated) + return 0; + + if (gtt && gtt->userptr) { + ttm->sg = kcalloc(1, sizeof(struct sg_table), GFP_KERNEL); + if (!ttm->sg) + return -ENOMEM; + + ttm->page_flags |= TTM_PAGE_FLAG_SG; + ttm->state = tt_unbound; + return 0; + } + + if (slave && ttm->sg) { + drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, + gtt->ttm.dma_address, ttm->num_pages); + ttm->state = tt_unbound; + return 0; + } + + adev = amdgpu_get_adev(ttm->bdev); + +#ifdef CONFIG_SWIOTLB + if (swiotlb_nr_tbl()) { + return ttm_dma_populate(>t->ttm, adev->dev); + } +#endif + + r = ttm_pool_populate(ttm); + if (r) { + return r; + } + + for (i = 0; i < ttm->num_pages; i++) { + gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i], + 0, PAGE_SIZE, + PCI_DMA_BIDIRECTIONAL); + if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) { + while (--i) { + pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], + PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + gtt->ttm.dma_address[i] = 0; + } + ttm_pool_unpopulate(ttm); + return -EFAULT; + } + } + return 0; +} + +static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) +{ + struct amdgpu_device *adev; + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); + + if (gtt && gtt->userptr) { + kfree(ttm->sg); + ttm->page_flags &= ~TTM_PAGE_FLAG_SG; + return; + } + + if (slave) + return; + + adev = amdgpu_get_adev(ttm->bdev); + +#ifdef CONFIG_SWIOTLB + if (swiotlb_nr_tbl()) { + ttm_dma_unpopulate(>t->ttm, adev->dev); + return; + } +#endif + + for (i = 0; i < ttm->num_pages; i++) { + if (gtt->ttm.dma_address[i]) { + pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], + PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + } + } + + ttm_pool_unpopulate(ttm); +} + +int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, + uint32_t flags) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + if (gtt == NULL) + return -EINVAL; + + gtt->userptr = addr; + gtt->usermm = current->mm; + gtt->userflags = flags; + return 0; +} + +bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + if (gtt == NULL) + return false; + + return !!gtt->userptr; +} + +bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + if (gtt == NULL) + return false; + + return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); +} + +uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, + struct ttm_mem_reg *mem) +{ + uint32_t flags = 0; + + if (mem && mem->mem_type != TTM_PL_SYSTEM) + flags |= AMDGPU_PTE_VALID; + + if (mem && mem->mem_type == TTM_PL_TT) + flags |= AMDGPU_PTE_SYSTEM; + + if (!ttm || ttm->caching_state == tt_cached) + flags |= AMDGPU_PTE_SNOOPED; + + if (adev->asic_type >= CHIP_TOPAZ) + flags |= AMDGPU_PTE_EXECUTABLE; + + flags |= AMDGPU_PTE_READABLE; + + if (!amdgpu_ttm_tt_is_readonly(ttm)) + flags |= AMDGPU_PTE_WRITEABLE; + + return flags; +} + +static struct ttm_bo_driver amdgpu_bo_driver = { + .ttm_tt_create = &amdgpu_ttm_tt_create, + .ttm_tt_populate = &amdgpu_ttm_tt_populate, + .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, + .invalidate_caches = &amdgpu_invalidate_caches, + .init_mem_type = &amdgpu_init_mem_type, + .evict_flags = &amdgpu_evict_flags, + .move = &amdgpu_bo_move, + .verify_access = &amdgpu_verify_access, + .move_notify = &amdgpu_bo_move_notify, + .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, + .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, + .io_mem_free = &amdgpu_ttm_io_mem_free, +}; + +int amdgpu_ttm_init(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_ttm_global_init(adev); + if (r) { + return r; + } + /* No others user of address space so set it to 0 */ + r = ttm_bo_device_init(&adev->mman.bdev, + adev->mman.bo_global_ref.ref.object, + &amdgpu_bo_driver, + adev->ddev->anon_inode->i_mapping, + DRM_FILE_PAGE_OFFSET, + adev->need_dma32); + if (r) { + DRM_ERROR("failed initializing buffer object driver(%d).\n", r); + return r; + } + adev->mman.initialized = true; + r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, + adev->mc.real_vram_size >> PAGE_SHIFT); + if (r) { + DRM_ERROR("Failed initializing VRAM heap.\n"); + return r; + } + /* Change the size here instead of the init above so only lpfn is affected */ + amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); + + r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, 0, + NULL, &adev->stollen_vga_memory); + if (r) { + return r; + } + r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); + if (r) + return r; + r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL); + amdgpu_bo_unreserve(adev->stollen_vga_memory); + if (r) { + amdgpu_bo_unref(&adev->stollen_vga_memory); + return r; + } + DRM_INFO("amdgpu: %uM of VRAM memory ready\n", + (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); + r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, + adev->mc.gtt_size >> PAGE_SHIFT); + if (r) { + DRM_ERROR("Failed initializing GTT heap.\n"); + return r; + } + DRM_INFO("amdgpu: %uM of GTT memory ready.\n", + (unsigned)(adev->mc.gtt_size / (1024 * 1024))); + + adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT; + adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT; + adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT; + adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT; + adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT; + adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT; + adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT; + adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT; + adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT; + /* GDS Memory */ + r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, + adev->gds.mem.total_size >> PAGE_SHIFT); + if (r) { + DRM_ERROR("Failed initializing GDS heap.\n"); + return r; + } + + /* GWS */ + r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, + adev->gds.gws.total_size >> PAGE_SHIFT); + if (r) { + DRM_ERROR("Failed initializing gws heap.\n"); + return r; + } + + /* OA */ + r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, + adev->gds.oa.total_size >> PAGE_SHIFT); + if (r) { + DRM_ERROR("Failed initializing oa heap.\n"); + return r; + } + + r = amdgpu_ttm_debugfs_init(adev); + if (r) { + DRM_ERROR("Failed to init debugfs\n"); + return r; + } + return 0; +} + +void amdgpu_ttm_fini(struct amdgpu_device *adev) +{ + int r; + + if (!adev->mman.initialized) + return; + amdgpu_ttm_debugfs_fini(adev); + if (adev->stollen_vga_memory) { + r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); + if (r == 0) { + amdgpu_bo_unpin(adev->stollen_vga_memory); + amdgpu_bo_unreserve(adev->stollen_vga_memory); + } + amdgpu_bo_unref(&adev->stollen_vga_memory); + } + ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); + ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); + ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); + ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); + ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); + ttm_bo_device_release(&adev->mman.bdev); + amdgpu_gart_fini(adev); + amdgpu_ttm_global_fini(adev); + adev->mman.initialized = false; + DRM_INFO("amdgpu: ttm finalized\n"); +} + +/* this should only be called at bootup or when userspace + * isn't running */ +void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size) +{ + struct ttm_mem_type_manager *man; + + if (!adev->mman.initialized) + return; + + man = &adev->mman.bdev.man[TTM_PL_VRAM]; + /* this just adjusts TTM size idea, which sets lpfn to the correct value */ + man->size = size >> PAGE_SHIFT; +} + +static struct vm_operations_struct amdgpu_ttm_vm_ops; +static const struct vm_operations_struct *ttm_vm_ops = NULL; + +static int amdgpu_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ + struct ttm_buffer_object *bo; + struct amdgpu_device *adev; + int r; + + bo = (struct ttm_buffer_object *)vma->vm_private_data; + if (bo == NULL) { + return VM_FAULT_NOPAGE; + } + adev = amdgpu_get_adev(bo->bdev); + down_read(&adev->pm.mclk_lock); + r = ttm_vm_ops->fault(vma, vmf); + up_read(&adev->pm.mclk_lock); + return r; +} + +int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct drm_file *file_priv; + struct amdgpu_device *adev; + int r; + + if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { + return -EINVAL; + } + + file_priv = filp->private_data; + adev = file_priv->minor->dev->dev_private; + if (adev == NULL) { + return -EINVAL; + } + r = ttm_bo_mmap(filp, vma, &adev->mman.bdev); + if (unlikely(r != 0)) { + return r; + } + if (unlikely(ttm_vm_ops == NULL)) { + ttm_vm_ops = vma->vm_ops; + amdgpu_ttm_vm_ops = *ttm_vm_ops; + amdgpu_ttm_vm_ops.fault = &amdgpu_ttm_fault; + } + vma->vm_ops = &amdgpu_ttm_vm_ops; + return 0; +} + +int amdgpu_copy_buffer(struct amdgpu_ring *ring, + uint64_t src_offset, + uint64_t dst_offset, + uint32_t byte_count, + struct reservation_object *resv, + struct amdgpu_fence **fence) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_sync sync; + uint32_t max_bytes; + unsigned num_loops, num_dw; + unsigned i; + int r; + + /* sync other rings */ + amdgpu_sync_create(&sync); + if (resv) { + r = amdgpu_sync_resv(adev, &sync, resv, false); + if (r) { + DRM_ERROR("sync failed (%d).\n", r); + amdgpu_sync_free(adev, &sync, NULL); + return r; + } + } + + max_bytes = adev->mman.buffer_funcs->copy_max_bytes; + num_loops = DIV_ROUND_UP(byte_count, max_bytes); + num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw; + + /* for fence and sync */ + num_dw += 64 + AMDGPU_NUM_SYNCS * 8; + + r = amdgpu_ring_lock(ring, num_dw); + if (r) { + DRM_ERROR("ring lock failed (%d).\n", r); + amdgpu_sync_free(adev, &sync, NULL); + return r; + } + + amdgpu_sync_rings(&sync, ring); + + for (i = 0; i < num_loops; i++) { + uint32_t cur_size_in_bytes = min(byte_count, max_bytes); + + amdgpu_emit_copy_buffer(adev, ring, src_offset, dst_offset, + cur_size_in_bytes); + + src_offset += cur_size_in_bytes; + dst_offset += cur_size_in_bytes; + byte_count -= cur_size_in_bytes; + } + + r = amdgpu_fence_emit(ring, AMDGPU_FENCE_OWNER_MOVE, fence); + if (r) { + amdgpu_ring_unlock_undo(ring); + amdgpu_sync_free(adev, &sync, NULL); + return r; + } + + amdgpu_ring_unlock_commit(ring); + amdgpu_sync_free(adev, &sync, *fence); + + return 0; +} + +#if defined(CONFIG_DEBUG_FS) + +static int amdgpu_mm_dump_table(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + unsigned ttm_pl = *(int *)node->info_ent->data; + struct drm_device *dev = node->minor->dev; + struct amdgpu_device *adev = dev->dev_private; + struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv; + int ret; + struct ttm_bo_global *glob = adev->mman.bdev.glob; + + spin_lock(&glob->lru_lock); + ret = drm_mm_dump_table(m, mm); + spin_unlock(&glob->lru_lock); + return ret; +} + +static int ttm_pl_vram = TTM_PL_VRAM; +static int ttm_pl_tt = TTM_PL_TT; + +static struct drm_info_list amdgpu_ttm_debugfs_list[] = { + {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram}, + {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt}, + {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, +#ifdef CONFIG_SWIOTLB + {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} +#endif +}; + +static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + ssize_t result = 0; + int r; + + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + + while (size) { + unsigned long flags; + uint32_t value; + + if (*pos >= adev->mc.mc_vram_size) + return result; + + spin_lock_irqsave(&adev->mmio_idx_lock, flags); + WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); + WREG32(mmMM_INDEX_HI, *pos >> 31); + value = RREG32(mmMM_DATA); + spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); + + r = put_user(value, (uint32_t *)buf); + if (r) + return r; + + result += 4; + buf += 4; + *pos += 4; + size -= 4; + } + + return result; +} + +static const struct file_operations amdgpu_ttm_vram_fops = { + .owner = THIS_MODULE, + .read = amdgpu_ttm_vram_read, + .llseek = default_llseek +}; + +static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = f->f_inode->i_private; + ssize_t result = 0; + int r; + + while (size) { + loff_t p = *pos / PAGE_SIZE; + unsigned off = *pos & ~PAGE_MASK; + size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); + struct page *page; + void *ptr; + + if (p >= adev->gart.num_cpu_pages) + return result; + + page = adev->gart.pages[p]; + if (page) { + ptr = kmap(page); + ptr += off; + + r = copy_to_user(buf, ptr, cur_size); + kunmap(adev->gart.pages[p]); + } else + r = clear_user(buf, cur_size); + + if (r) + return -EFAULT; + + result += cur_size; + buf += cur_size; + *pos += cur_size; + size -= cur_size; + } + + return result; +} + +static const struct file_operations amdgpu_ttm_gtt_fops = { + .owner = THIS_MODULE, + .read = amdgpu_ttm_gtt_read, + .llseek = default_llseek +}; + +#endif + +static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + unsigned count; + + struct drm_minor *minor = adev->ddev->primary; + struct dentry *ent, *root = minor->debugfs_root; + + ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root, + adev, &amdgpu_ttm_vram_fops); + if (IS_ERR(ent)) + return PTR_ERR(ent); + i_size_write(ent->d_inode, adev->mc.mc_vram_size); + adev->mman.vram = ent; + + ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root, + adev, &amdgpu_ttm_gtt_fops); + if (IS_ERR(ent)) + return PTR_ERR(ent); + i_size_write(ent->d_inode, adev->mc.gtt_size); + adev->mman.gtt = ent; + + count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); + +#ifdef CONFIG_SWIOTLB + if (!swiotlb_nr_tbl()) + --count; +#endif + + return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); +#else + + return 0; +#endif +} + +static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + + debugfs_remove(adev->mman.vram); + adev->mman.vram = NULL; + + debugfs_remove(adev->mman.gtt); + adev->mman.gtt = NULL; +#endif +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c new file mode 100644 index 000000000000..482e66797ae6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -0,0 +1,317 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_ucode.h" + +static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) +{ + DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); + DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); + DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); + DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); + DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); + DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); + DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); + DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); + DRM_DEBUG("ucode_array_offset_bytes: %u\n", + le32_to_cpu(hdr->ucode_array_offset_bytes)); + DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); +} + +void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) +{ + uint16_t version_major = le16_to_cpu(hdr->header_version_major); + uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); + + DRM_DEBUG("MC\n"); + amdgpu_ucode_print_common_hdr(hdr); + + if (version_major == 1) { + const struct mc_firmware_header_v1_0 *mc_hdr = + container_of(hdr, struct mc_firmware_header_v1_0, header); + + DRM_DEBUG("io_debug_size_bytes: %u\n", + le32_to_cpu(mc_hdr->io_debug_size_bytes)); + DRM_DEBUG("io_debug_array_offset_bytes: %u\n", + le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); + } else { + DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); + } +} + +void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) +{ + uint16_t version_major = le16_to_cpu(hdr->header_version_major); + uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); + + DRM_DEBUG("SMC\n"); + amdgpu_ucode_print_common_hdr(hdr); + + if (version_major == 1) { + const struct smc_firmware_header_v1_0 *smc_hdr = + container_of(hdr, struct smc_firmware_header_v1_0, header); + + DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr)); + } else { + DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); + } +} + +void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) +{ + uint16_t version_major = le16_to_cpu(hdr->header_version_major); + uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); + + DRM_DEBUG("GFX\n"); + amdgpu_ucode_print_common_hdr(hdr); + + if (version_major == 1) { + const struct gfx_firmware_header_v1_0 *gfx_hdr = + container_of(hdr, struct gfx_firmware_header_v1_0, header); + + DRM_DEBUG("ucode_feature_version: %u\n", + le32_to_cpu(gfx_hdr->ucode_feature_version)); + DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); + DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); + } else { + DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); + } +} + +void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) +{ + uint16_t version_major = le16_to_cpu(hdr->header_version_major); + uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); + + DRM_DEBUG("RLC\n"); + amdgpu_ucode_print_common_hdr(hdr); + + if (version_major == 1) { + const struct rlc_firmware_header_v1_0 *rlc_hdr = + container_of(hdr, struct rlc_firmware_header_v1_0, header); + + DRM_DEBUG("ucode_feature_version: %u\n", + le32_to_cpu(rlc_hdr->ucode_feature_version)); + DRM_DEBUG("save_and_restore_offset: %u\n", + le32_to_cpu(rlc_hdr->save_and_restore_offset)); + DRM_DEBUG("clear_state_descriptor_offset: %u\n", + le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); + DRM_DEBUG("avail_scratch_ram_locations: %u\n", + le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); + DRM_DEBUG("master_pkt_description_offset: %u\n", + le32_to_cpu(rlc_hdr->master_pkt_description_offset)); + } else if (version_major == 2) { + const struct rlc_firmware_header_v2_0 *rlc_hdr = + container_of(hdr, struct rlc_firmware_header_v2_0, header); + + DRM_DEBUG("ucode_feature_version: %u\n", + le32_to_cpu(rlc_hdr->ucode_feature_version)); + DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); + DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); + DRM_DEBUG("save_and_restore_offset: %u\n", + le32_to_cpu(rlc_hdr->save_and_restore_offset)); + DRM_DEBUG("clear_state_descriptor_offset: %u\n", + le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); + DRM_DEBUG("avail_scratch_ram_locations: %u\n", + le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); + DRM_DEBUG("reg_restore_list_size: %u\n", + le32_to_cpu(rlc_hdr->reg_restore_list_size)); + DRM_DEBUG("reg_list_format_start: %u\n", + le32_to_cpu(rlc_hdr->reg_list_format_start)); + DRM_DEBUG("reg_list_format_separate_start: %u\n", + le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); + DRM_DEBUG("starting_offsets_start: %u\n", + le32_to_cpu(rlc_hdr->starting_offsets_start)); + DRM_DEBUG("reg_list_format_size_bytes: %u\n", + le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); + DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", + le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); + DRM_DEBUG("reg_list_size_bytes: %u\n", + le32_to_cpu(rlc_hdr->reg_list_size_bytes)); + DRM_DEBUG("reg_list_array_offset_bytes: %u\n", + le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); + DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", + le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); + DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", + le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); + DRM_DEBUG("reg_list_separate_size_bytes: %u\n", + le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); + DRM_DEBUG("reg_list_separate_size_bytes: %u\n", + le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); + } else { + DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); + } +} + +void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) +{ + uint16_t version_major = le16_to_cpu(hdr->header_version_major); + uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); + + DRM_DEBUG("SDMA\n"); + amdgpu_ucode_print_common_hdr(hdr); + + if (version_major == 1) { + const struct sdma_firmware_header_v1_0 *sdma_hdr = + container_of(hdr, struct sdma_firmware_header_v1_0, header); + + DRM_DEBUG("ucode_feature_version: %u\n", + le32_to_cpu(sdma_hdr->ucode_feature_version)); + DRM_DEBUG("ucode_change_version: %u\n", + le32_to_cpu(sdma_hdr->ucode_change_version)); + DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); + DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); + if (version_minor >= 1) { + const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = + container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); + DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); + } + } else { + DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", + version_major, version_minor); + } +} + +int amdgpu_ucode_validate(const struct firmware *fw) +{ + const struct common_firmware_header *hdr = + (const struct common_firmware_header *)fw->data; + + if (fw->size == le32_to_cpu(hdr->size_bytes)) + return 0; + + return -EINVAL; +} + +bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, + uint16_t hdr_major, uint16_t hdr_minor) +{ + if ((hdr->common.header_version_major == hdr_major) && + (hdr->common.header_version_minor == hdr_minor)) + return false; + return true; +} + +static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode, + uint64_t mc_addr, void *kptr) +{ + const struct common_firmware_header *header = NULL; + + if (NULL == ucode->fw) + return 0; + + ucode->mc_addr = mc_addr; + ucode->kaddr = kptr; + + header = (const struct common_firmware_header *)ucode->fw->data; + memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + + le32_to_cpu(header->ucode_array_offset_bytes)), + le32_to_cpu(header->ucode_size_bytes)); + + return 0; +} + +int amdgpu_ucode_init_bo(struct amdgpu_device *adev) +{ + struct amdgpu_bo **bo = &adev->firmware.fw_buf; + uint64_t fw_mc_addr; + void *fw_buf_ptr = NULL; + uint64_t fw_offset = 0; + int i, err; + struct amdgpu_firmware_info *ucode = NULL; + const struct common_firmware_header *header = NULL; + + err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, NULL, bo); + if (err) { + dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); + err = -ENOMEM; + goto failed; + } + + err = amdgpu_bo_reserve(*bo, false); + if (err) { + amdgpu_bo_unref(bo); + dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err); + goto failed; + } + + err = amdgpu_bo_pin(*bo, AMDGPU_GEM_DOMAIN_GTT, &fw_mc_addr); + if (err) { + amdgpu_bo_unreserve(*bo); + amdgpu_bo_unref(bo); + dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err); + goto failed; + } + + err = amdgpu_bo_kmap(*bo, &fw_buf_ptr); + if (err) { + dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err); + amdgpu_bo_unpin(*bo); + amdgpu_bo_unreserve(*bo); + amdgpu_bo_unref(bo); + goto failed; + } + + amdgpu_bo_unreserve(*bo); + + fw_offset = 0; + for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) { + ucode = &adev->firmware.ucode[i]; + if (ucode->fw) { + header = (const struct common_firmware_header *)ucode->fw->data; + amdgpu_ucode_init_single_fw(ucode, fw_mc_addr + fw_offset, + fw_buf_ptr + fw_offset); + fw_offset += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + } + } + +failed: + if (err) + adev->firmware.smu_load = false; + + return err; +} + +int amdgpu_ucode_fini_bo(struct amdgpu_device *adev) +{ + int i; + struct amdgpu_firmware_info *ucode = NULL; + + for (i = 0; i < AMDGPU_UCODE_ID_MAXIMUM; i++) { + ucode = &adev->firmware.ucode[i]; + if (ucode->fw) { + ucode->mc_addr = 0; + ucode->kaddr = NULL; + } + } + amdgpu_bo_unref(&adev->firmware.fw_buf); + adev->firmware.fw_buf = NULL; + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h new file mode 100644 index 000000000000..e468be4e28fa --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -0,0 +1,176 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __AMDGPU_UCODE_H__ +#define __AMDGPU_UCODE_H__ + +struct common_firmware_header { + uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ + uint32_t header_size_bytes; /* size of just the header in bytes */ + uint16_t header_version_major; /* header version */ + uint16_t header_version_minor; /* header version */ + uint16_t ip_version_major; /* IP version */ + uint16_t ip_version_minor; /* IP version */ + uint32_t ucode_version; + uint32_t ucode_size_bytes; /* size of ucode in bytes */ + uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ + uint32_t crc32; /* crc32 checksum of the payload */ +}; + +/* version_major=1, version_minor=0 */ +struct mc_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t io_debug_size_bytes; /* size of debug array in dwords */ + uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ +}; + +/* version_major=1, version_minor=0 */ +struct smc_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t ucode_start_addr; +}; + +/* version_major=1, version_minor=0 */ +struct gfx_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t jt_offset; /* jt location */ + uint32_t jt_size; /* size of jt */ +}; + +/* version_major=1, version_minor=0 */ +struct rlc_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t save_and_restore_offset; + uint32_t clear_state_descriptor_offset; + uint32_t avail_scratch_ram_locations; + uint32_t master_pkt_description_offset; +}; + +/* version_major=2, version_minor=0 */ +struct rlc_firmware_header_v2_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t jt_offset; /* jt location */ + uint32_t jt_size; /* size of jt */ + uint32_t save_and_restore_offset; + uint32_t clear_state_descriptor_offset; + uint32_t avail_scratch_ram_locations; + uint32_t reg_restore_list_size; + uint32_t reg_list_format_start; + uint32_t reg_list_format_separate_start; + uint32_t starting_offsets_start; + uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ + uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ + uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ + uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ + uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ + uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ + uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ + uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ +}; + +/* version_major=1, version_minor=0 */ +struct sdma_firmware_header_v1_0 { + struct common_firmware_header header; + uint32_t ucode_feature_version; + uint32_t ucode_change_version; + uint32_t jt_offset; /* jt location */ + uint32_t jt_size; /* size of jt */ +}; + +/* version_major=1, version_minor=1 */ +struct sdma_firmware_header_v1_1 { + struct sdma_firmware_header_v1_0 v1_0; + uint32_t digest_size; +}; + +/* header is fixed size */ +union amdgpu_firmware_header { + struct common_firmware_header common; + struct mc_firmware_header_v1_0 mc; + struct smc_firmware_header_v1_0 smc; + struct gfx_firmware_header_v1_0 gfx; + struct rlc_firmware_header_v1_0 rlc; + struct rlc_firmware_header_v2_0 rlc_v2_0; + struct sdma_firmware_header_v1_0 sdma; + struct sdma_firmware_header_v1_1 sdma_v1_1; + uint8_t raw[0x100]; +}; + +/* + * fw loading support + */ +enum AMDGPU_UCODE_ID { + AMDGPU_UCODE_ID_SDMA0 = 0, + AMDGPU_UCODE_ID_SDMA1, + AMDGPU_UCODE_ID_CP_CE, + AMDGPU_UCODE_ID_CP_PFP, + AMDGPU_UCODE_ID_CP_ME, + AMDGPU_UCODE_ID_CP_MEC1, + AMDGPU_UCODE_ID_CP_MEC2, + AMDGPU_UCODE_ID_RLC_G, + AMDGPU_UCODE_ID_MAXIMUM, +}; + +/* engine firmware status */ +enum AMDGPU_UCODE_STATUS { + AMDGPU_UCODE_STATUS_INVALID, + AMDGPU_UCODE_STATUS_NOT_LOADED, + AMDGPU_UCODE_STATUS_LOADED, +}; + +/* conform to smu_ucode_xfer_cz.h */ +#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 +#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 +#define AMDGPU_CPCE_UCODE_LOADED 0x00000004 +#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 +#define AMDGPU_CPME_UCODE_LOADED 0x00000010 +#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 +#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 +#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 + +/* amdgpu firmware info */ +struct amdgpu_firmware_info { + /* ucode ID */ + enum AMDGPU_UCODE_ID ucode_id; + /* request_firmware */ + const struct firmware *fw; + /* starting mc address */ + uint64_t mc_addr; + /* kernel linear address */ + void *kaddr; +}; + +void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); +void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); +void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); +void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); +void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); +int amdgpu_ucode_validate(const struct firmware *fw); +bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, + uint16_t hdr_major, uint16_t hdr_minor); +int amdgpu_ucode_init_bo(struct amdgpu_device *adev); +int amdgpu_ucode_fini_bo(struct amdgpu_device *adev); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c new file mode 100644 index 000000000000..c03bce6f32a9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -0,0 +1,976 @@ +/* + * Copyright 2011 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* + * Authors: + * Christian König + */ + +#include +#include +#include +#include + +#include "amdgpu.h" +#include "amdgpu_pm.h" +#include "amdgpu_uvd.h" +#include "cikd.h" +#include "uvd/uvd_4_2_d.h" + +/* 1 second timeout */ +#define UVD_IDLE_TIMEOUT_MS 1000 + +/* Firmware Names */ +#ifdef CONFIG_DRM_AMDGPU_CIK +#define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" +#define FIRMWARE_KABINI "radeon/kabini_uvd.bin" +#define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" +#define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" +#define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" +#endif +#define FIRMWARE_TONGA "radeon/tonga_uvd.bin" +#define FIRMWARE_CARRIZO "radeon/carrizo_uvd.bin" + +/** + * amdgpu_uvd_cs_ctx - Command submission parser context + * + * Used for emulating virtual memory support on UVD 4.2. + */ +struct amdgpu_uvd_cs_ctx { + struct amdgpu_cs_parser *parser; + unsigned reg, count; + unsigned data0, data1; + unsigned idx; + unsigned ib_idx; + + /* does the IB has a msg command */ + bool has_msg_cmd; + + /* minimum buffer sizes */ + unsigned *buf_sizes; +}; + +#ifdef CONFIG_DRM_AMDGPU_CIK +MODULE_FIRMWARE(FIRMWARE_BONAIRE); +MODULE_FIRMWARE(FIRMWARE_KABINI); +MODULE_FIRMWARE(FIRMWARE_KAVERI); +MODULE_FIRMWARE(FIRMWARE_HAWAII); +MODULE_FIRMWARE(FIRMWARE_MULLINS); +#endif +MODULE_FIRMWARE(FIRMWARE_TONGA); +MODULE_FIRMWARE(FIRMWARE_CARRIZO); + +static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); +static void amdgpu_uvd_idle_work_handler(struct work_struct *work); + +int amdgpu_uvd_sw_init(struct amdgpu_device *adev) +{ + unsigned long bo_size; + const char *fw_name; + const struct common_firmware_header *hdr; + unsigned version_major, version_minor, family_id; + int i, r; + + INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); + + switch (adev->asic_type) { +#ifdef CONFIG_DRM_AMDGPU_CIK + case CHIP_BONAIRE: + fw_name = FIRMWARE_BONAIRE; + break; + case CHIP_KABINI: + fw_name = FIRMWARE_KABINI; + break; + case CHIP_KAVERI: + fw_name = FIRMWARE_KAVERI; + break; + case CHIP_HAWAII: + fw_name = FIRMWARE_HAWAII; + break; + case CHIP_MULLINS: + fw_name = FIRMWARE_MULLINS; + break; +#endif + case CHIP_TONGA: + fw_name = FIRMWARE_TONGA; + break; + case CHIP_CARRIZO: + fw_name = FIRMWARE_CARRIZO; + break; + default: + return -EINVAL; + } + + r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); + if (r) { + dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", + fw_name); + return r; + } + + r = amdgpu_ucode_validate(adev->uvd.fw); + if (r) { + dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", + fw_name); + release_firmware(adev->uvd.fw); + adev->uvd.fw = NULL; + return r; + } + + hdr = (const struct common_firmware_header *)adev->uvd.fw->data; + family_id = le32_to_cpu(hdr->ucode_version) & 0xff; + version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; + version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; + DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", + version_major, version_minor, family_id); + + bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) + + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE; + r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->uvd.vcpu_bo); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); + return r; + } + + r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); + if (r) { + amdgpu_bo_unref(&adev->uvd.vcpu_bo); + dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r); + return r; + } + + r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM, + &adev->uvd.gpu_addr); + if (r) { + amdgpu_bo_unreserve(adev->uvd.vcpu_bo); + amdgpu_bo_unref(&adev->uvd.vcpu_bo); + dev_err(adev->dev, "(%d) UVD bo pin failed\n", r); + return r; + } + + r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr); + if (r) { + dev_err(adev->dev, "(%d) UVD map failed\n", r); + return r; + } + + amdgpu_bo_unreserve(adev->uvd.vcpu_bo); + + for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + atomic_set(&adev->uvd.handles[i], 0); + adev->uvd.filp[i] = NULL; + } + + /* from uvd v5.0 HW addressing capacity increased to 64 bits */ + if (!amdgpu_ip_block_version_cmp(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 5, 0)) + adev->uvd.address_64_bit = true; + + return 0; +} + +int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) +{ + int r; + + if (adev->uvd.vcpu_bo == NULL) + return 0; + + r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false); + if (!r) { + amdgpu_bo_kunmap(adev->uvd.vcpu_bo); + amdgpu_bo_unpin(adev->uvd.vcpu_bo); + amdgpu_bo_unreserve(adev->uvd.vcpu_bo); + } + + amdgpu_bo_unref(&adev->uvd.vcpu_bo); + + amdgpu_ring_fini(&adev->uvd.ring); + + release_firmware(adev->uvd.fw); + + return 0; +} + +int amdgpu_uvd_suspend(struct amdgpu_device *adev) +{ + unsigned size; + void *ptr; + const struct common_firmware_header *hdr; + int i; + + if (adev->uvd.vcpu_bo == NULL) + return 0; + + for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) + if (atomic_read(&adev->uvd.handles[i])) + break; + + if (i == AMDGPU_MAX_UVD_HANDLES) + return 0; + + hdr = (const struct common_firmware_header *)adev->uvd.fw->data; + + size = amdgpu_bo_size(adev->uvd.vcpu_bo); + size -= le32_to_cpu(hdr->ucode_size_bytes); + + ptr = adev->uvd.cpu_addr; + ptr += le32_to_cpu(hdr->ucode_size_bytes); + + adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); + memcpy(adev->uvd.saved_bo, ptr, size); + + return 0; +} + +int amdgpu_uvd_resume(struct amdgpu_device *adev) +{ + unsigned size; + void *ptr; + const struct common_firmware_header *hdr; + unsigned offset; + + if (adev->uvd.vcpu_bo == NULL) + return -EINVAL; + + hdr = (const struct common_firmware_header *)adev->uvd.fw->data; + offset = le32_to_cpu(hdr->ucode_array_offset_bytes); + memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset, + (adev->uvd.fw->size) - offset); + + size = amdgpu_bo_size(adev->uvd.vcpu_bo); + size -= le32_to_cpu(hdr->ucode_size_bytes); + ptr = adev->uvd.cpu_addr; + ptr += le32_to_cpu(hdr->ucode_size_bytes); + + if (adev->uvd.saved_bo != NULL) { + memcpy(ptr, adev->uvd.saved_bo, size); + kfree(adev->uvd.saved_bo); + adev->uvd.saved_bo = NULL; + } else + memset(ptr, 0, size); + + return 0; +} + +void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) +{ + struct amdgpu_ring *ring = &adev->uvd.ring; + int i, r; + + for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + uint32_t handle = atomic_read(&adev->uvd.handles[i]); + if (handle != 0 && adev->uvd.filp[i] == filp) { + struct amdgpu_fence *fence; + + amdgpu_uvd_note_usage(adev); + + r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence); + if (r) { + DRM_ERROR("Error destroying UVD (%d)!\n", r); + continue; + } + + amdgpu_fence_wait(fence, false); + amdgpu_fence_unref(&fence); + + adev->uvd.filp[i] = NULL; + atomic_set(&adev->uvd.handles[i], 0); + } + } +} + +static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo) +{ + int i; + for (i = 0; i < rbo->placement.num_placement; ++i) { + rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; + rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; + } +} + +/** + * amdgpu_uvd_cs_pass1 - first parsing round + * + * @ctx: UVD parser context + * + * Make sure UVD message and feedback buffers are in VRAM and + * nobody is violating an 256MB boundary. + */ +static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) +{ + struct amdgpu_bo_va_mapping *mapping; + struct amdgpu_bo *bo; + uint32_t cmd, lo, hi; + uint64_t addr; + int r = 0; + + lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); + hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); + addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); + + mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); + if (mapping == NULL) { + DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); + return -EINVAL; + } + + if (!ctx->parser->adev->uvd.address_64_bit) { + /* check if it's a message or feedback command */ + cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; + if (cmd == 0x0 || cmd == 0x3) { + /* yes, force it into VRAM */ + uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; + amdgpu_ttm_placement_from_domain(bo, domain); + } + amdgpu_uvd_force_into_uvd_segment(bo); + + r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + } + + return r; +} + +/** + * amdgpu_uvd_cs_msg_decode - handle UVD decode message + * + * @msg: pointer to message structure + * @buf_sizes: returned buffer sizes + * + * Peek into the decode message and calculate the necessary buffer sizes. + */ +static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) +{ + unsigned stream_type = msg[4]; + unsigned width = msg[6]; + unsigned height = msg[7]; + unsigned dpb_size = msg[9]; + unsigned pitch = msg[28]; + unsigned level = msg[57]; + + unsigned width_in_mb = width / 16; + unsigned height_in_mb = ALIGN(height / 16, 2); + unsigned fs_in_mb = width_in_mb * height_in_mb; + + unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; + + image_size = width * height; + image_size += image_size / 2; + image_size = ALIGN(image_size, 1024); + + switch (stream_type) { + case 0: /* H264 */ + case 7: /* H264 Perf */ + switch(level) { + case 30: + num_dpb_buffer = 8100 / fs_in_mb; + break; + case 31: + num_dpb_buffer = 18000 / fs_in_mb; + break; + case 32: + num_dpb_buffer = 20480 / fs_in_mb; + break; + case 41: + num_dpb_buffer = 32768 / fs_in_mb; + break; + case 42: + num_dpb_buffer = 34816 / fs_in_mb; + break; + case 50: + num_dpb_buffer = 110400 / fs_in_mb; + break; + case 51: + num_dpb_buffer = 184320 / fs_in_mb; + break; + default: + num_dpb_buffer = 184320 / fs_in_mb; + break; + } + num_dpb_buffer++; + if (num_dpb_buffer > 17) + num_dpb_buffer = 17; + + /* reference picture buffer */ + min_dpb_size = image_size * num_dpb_buffer; + + /* macroblock context buffer */ + min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; + + /* IT surface buffer */ + min_dpb_size += width_in_mb * height_in_mb * 32; + break; + + case 1: /* VC1 */ + + /* reference picture buffer */ + min_dpb_size = image_size * 3; + + /* CONTEXT_BUFFER */ + min_dpb_size += width_in_mb * height_in_mb * 128; + + /* IT surface buffer */ + min_dpb_size += width_in_mb * 64; + + /* DB surface buffer */ + min_dpb_size += width_in_mb * 128; + + /* BP */ + tmp = max(width_in_mb, height_in_mb); + min_dpb_size += ALIGN(tmp * 7 * 16, 64); + break; + + case 3: /* MPEG2 */ + + /* reference picture buffer */ + min_dpb_size = image_size * 3; + break; + + case 4: /* MPEG4 */ + + /* reference picture buffer */ + min_dpb_size = image_size * 3; + + /* CM */ + min_dpb_size += width_in_mb * height_in_mb * 64; + + /* IT surface buffer */ + min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); + break; + + default: + DRM_ERROR("UVD codec not handled %d!\n", stream_type); + return -EINVAL; + } + + if (width > pitch) { + DRM_ERROR("Invalid UVD decoding target pitch!\n"); + return -EINVAL; + } + + if (dpb_size < min_dpb_size) { + DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", + dpb_size, min_dpb_size); + return -EINVAL; + } + + buf_sizes[0x1] = dpb_size; + buf_sizes[0x2] = image_size; + return 0; +} + +/** + * amdgpu_uvd_cs_msg - handle UVD message + * + * @ctx: UVD parser context + * @bo: buffer object containing the message + * @offset: offset into the buffer object + * + * Peek into the UVD message and extract the session id. + * Make sure that we don't open up to many sessions. + */ +static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, + struct amdgpu_bo *bo, unsigned offset) +{ + struct amdgpu_device *adev = ctx->parser->adev; + int32_t *msg, msg_type, handle; + struct fence *f; + void *ptr; + + int i, r; + + if (offset & 0x3F) { + DRM_ERROR("UVD messages must be 64 byte aligned!\n"); + return -EINVAL; + } + + f = reservation_object_get_excl(bo->tbo.resv); + if (f) { + r = amdgpu_fence_wait((struct amdgpu_fence *)f, false); + if (r) { + DRM_ERROR("Failed waiting for UVD message (%d)!\n", r); + return r; + } + } + + r = amdgpu_bo_kmap(bo, &ptr); + if (r) { + DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); + return r; + } + + msg = ptr + offset; + + msg_type = msg[1]; + handle = msg[2]; + + if (handle == 0) { + DRM_ERROR("Invalid UVD handle!\n"); + return -EINVAL; + } + + if (msg_type == 1) { + /* it's a decode msg, calc buffer sizes */ + r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes); + amdgpu_bo_kunmap(bo); + if (r) + return r; + + } else if (msg_type == 2) { + /* it's a destroy msg, free the handle */ + for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) + atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); + amdgpu_bo_kunmap(bo); + return 0; + } else { + /* it's a create msg */ + amdgpu_bo_kunmap(bo); + + if (msg_type != 0) { + DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); + return -EINVAL; + } + + /* it's a create msg, no special handling needed */ + } + + /* create or decode, validate the handle */ + for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + if (atomic_read(&adev->uvd.handles[i]) == handle) + return 0; + } + + /* handle not found try to alloc a new one */ + for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { + if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { + adev->uvd.filp[i] = ctx->parser->filp; + return 0; + } + } + + DRM_ERROR("No more free UVD handles!\n"); + return -EINVAL; +} + +/** + * amdgpu_uvd_cs_pass2 - second parsing round + * + * @ctx: UVD parser context + * + * Patch buffer addresses, make sure buffer sizes are correct. + */ +static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) +{ + struct amdgpu_bo_va_mapping *mapping; + struct amdgpu_bo *bo; + struct amdgpu_ib *ib; + uint32_t cmd, lo, hi; + uint64_t start, end; + uint64_t addr; + int r; + + lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); + hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); + addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); + + mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo); + if (mapping == NULL) + return -EINVAL; + + start = amdgpu_bo_gpu_offset(bo); + + end = (mapping->it.last + 1 - mapping->it.start); + end = end * AMDGPU_GPU_PAGE_SIZE + start; + + addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE; + start += addr; + + ib = &ctx->parser->ibs[ctx->ib_idx]; + ib->ptr[ctx->data0] = start & 0xFFFFFFFF; + ib->ptr[ctx->data1] = start >> 32; + + cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; + if (cmd < 0x4) { + if ((end - start) < ctx->buf_sizes[cmd]) { + DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, + (unsigned)(end - start), + ctx->buf_sizes[cmd]); + return -EINVAL; + } + + } else if ((cmd != 0x100) && (cmd != 0x204)) { + DRM_ERROR("invalid UVD command %X!\n", cmd); + return -EINVAL; + } + + if (!ctx->parser->adev->uvd.address_64_bit) { + if ((start >> 28) != ((end - 1) >> 28)) { + DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", + start, end); + return -EINVAL; + } + + if ((cmd == 0 || cmd == 0x3) && + (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { + DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", + start, end); + return -EINVAL; + } + } + + if (cmd == 0) { + ctx->has_msg_cmd = true; + r = amdgpu_uvd_cs_msg(ctx, bo, addr); + if (r) + return r; + } else if (!ctx->has_msg_cmd) { + DRM_ERROR("Message needed before other commands are send!\n"); + return -EINVAL; + } + + return 0; +} + +/** + * amdgpu_uvd_cs_reg - parse register writes + * + * @ctx: UVD parser context + * @cb: callback function + * + * Parse the register writes, call cb on each complete command. + */ +static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, + int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) +{ + struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx]; + int i, r; + + ctx->idx++; + for (i = 0; i <= ctx->count; ++i) { + unsigned reg = ctx->reg + i; + + if (ctx->idx >= ib->length_dw) { + DRM_ERROR("Register command after end of CS!\n"); + return -EINVAL; + } + + switch (reg) { + case mmUVD_GPCOM_VCPU_DATA0: + ctx->data0 = ctx->idx; + break; + case mmUVD_GPCOM_VCPU_DATA1: + ctx->data1 = ctx->idx; + break; + case mmUVD_GPCOM_VCPU_CMD: + r = cb(ctx); + if (r) + return r; + break; + case mmUVD_ENGINE_CNTL: + break; + default: + DRM_ERROR("Invalid reg 0x%X!\n", reg); + return -EINVAL; + } + ctx->idx++; + } + return 0; +} + +/** + * amdgpu_uvd_cs_packets - parse UVD packets + * + * @ctx: UVD parser context + * @cb: callback function + * + * Parse the command stream packets. + */ +static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, + int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) +{ + struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx]; + int r; + + for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { + uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); + unsigned type = CP_PACKET_GET_TYPE(cmd); + switch (type) { + case PACKET_TYPE0: + ctx->reg = CP_PACKET0_GET_REG(cmd); + ctx->count = CP_PACKET_GET_COUNT(cmd); + r = amdgpu_uvd_cs_reg(ctx, cb); + if (r) + return r; + break; + case PACKET_TYPE2: + ++ctx->idx; + break; + default: + DRM_ERROR("Unknown packet type %d !\n", type); + return -EINVAL; + } + } + return 0; +} + +/** + * amdgpu_uvd_ring_parse_cs - UVD command submission parser + * + * @parser: Command submission parser context + * + * Parse the command stream, patch in addresses as necessary. + */ +int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) +{ + struct amdgpu_uvd_cs_ctx ctx = {}; + unsigned buf_sizes[] = { + [0x00000000] = 2048, + [0x00000001] = 32 * 1024 * 1024, + [0x00000002] = 2048 * 1152 * 3, + [0x00000003] = 2048, + }; + struct amdgpu_ib *ib = &parser->ibs[ib_idx]; + int r; + + if (ib->length_dw % 16) { + DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", + ib->length_dw); + return -EINVAL; + } + + ctx.parser = parser; + ctx.buf_sizes = buf_sizes; + ctx.ib_idx = ib_idx; + + /* first round, make sure the buffers are actually in the UVD segment */ + r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); + if (r) + return r; + + /* second round, patch buffer addresses into the command stream */ + r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); + if (r) + return r; + + if (!ctx.has_msg_cmd) { + DRM_ERROR("UVD-IBs need a msg command!\n"); + return -EINVAL; + } + + amdgpu_uvd_note_usage(ctx.parser->adev); + + return 0; +} + +static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, + struct amdgpu_bo *bo, + struct amdgpu_fence **fence) +{ + struct ttm_validate_buffer tv; + struct ww_acquire_ctx ticket; + struct list_head head; + struct amdgpu_ib ib; + uint64_t addr; + int i, r; + + memset(&tv, 0, sizeof(tv)); + tv.bo = &bo->tbo; + + INIT_LIST_HEAD(&head); + list_add(&tv.head, &head); + + r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); + if (r) + return r; + + if (!bo->adev->uvd.address_64_bit) { + amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); + amdgpu_uvd_force_into_uvd_segment(bo); + } + + r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + if (r) + goto err; + + r = amdgpu_ib_get(ring, NULL, 64, &ib); + if (r) + goto err; + + addr = amdgpu_bo_gpu_offset(bo); + ib.ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); + ib.ptr[1] = addr; + ib.ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); + ib.ptr[3] = addr >> 32; + ib.ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); + ib.ptr[5] = 0; + for (i = 6; i < 16; ++i) + ib.ptr[i] = PACKET2(0); + ib.length_dw = 16; + + r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); + if (r) + goto err; + ttm_eu_fence_buffer_objects(&ticket, &head, &ib.fence->base); + + if (fence) + *fence = amdgpu_fence_ref(ib.fence); + + amdgpu_ib_free(ring->adev, &ib); + amdgpu_bo_unref(&bo); + return 0; + +err: + ttm_eu_backoff_reservation(&ticket, &head); + return r; +} + +/* multiple fence commands without any stream commands in between can + crash the vcpu so just try to emmit a dummy create/destroy msg to + avoid this */ +int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, + struct amdgpu_fence **fence) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_bo *bo; + uint32_t *msg; + int r, i; + + r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo); + if (r) + return r; + + r = amdgpu_bo_reserve(bo, false); + if (r) { + amdgpu_bo_unref(&bo); + return r; + } + + r = amdgpu_bo_kmap(bo, (void **)&msg); + if (r) { + amdgpu_bo_unreserve(bo); + amdgpu_bo_unref(&bo); + return r; + } + + /* stitch together an UVD create msg */ + msg[0] = cpu_to_le32(0x00000de4); + msg[1] = cpu_to_le32(0x00000000); + msg[2] = cpu_to_le32(handle); + msg[3] = cpu_to_le32(0x00000000); + msg[4] = cpu_to_le32(0x00000000); + msg[5] = cpu_to_le32(0x00000000); + msg[6] = cpu_to_le32(0x00000000); + msg[7] = cpu_to_le32(0x00000780); + msg[8] = cpu_to_le32(0x00000440); + msg[9] = cpu_to_le32(0x00000000); + msg[10] = cpu_to_le32(0x01b37000); + for (i = 11; i < 1024; ++i) + msg[i] = cpu_to_le32(0x0); + + amdgpu_bo_kunmap(bo); + amdgpu_bo_unreserve(bo); + + return amdgpu_uvd_send_msg(ring, bo, fence); +} + +int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, + struct amdgpu_fence **fence) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_bo *bo; + uint32_t *msg; + int r, i; + + r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo); + if (r) + return r; + + r = amdgpu_bo_reserve(bo, false); + if (r) { + amdgpu_bo_unref(&bo); + return r; + } + + r = amdgpu_bo_kmap(bo, (void **)&msg); + if (r) { + amdgpu_bo_unreserve(bo); + amdgpu_bo_unref(&bo); + return r; + } + + /* stitch together an UVD destroy msg */ + msg[0] = cpu_to_le32(0x00000de4); + msg[1] = cpu_to_le32(0x00000002); + msg[2] = cpu_to_le32(handle); + msg[3] = cpu_to_le32(0x00000000); + for (i = 4; i < 1024; ++i) + msg[i] = cpu_to_le32(0x0); + + amdgpu_bo_kunmap(bo); + amdgpu_bo_unreserve(bo); + + return amdgpu_uvd_send_msg(ring, bo, fence); +} + +static void amdgpu_uvd_idle_work_handler(struct work_struct *work) +{ + struct amdgpu_device *adev = + container_of(work, struct amdgpu_device, uvd.idle_work.work); + unsigned i, fences, handles = 0; + + fences = amdgpu_fence_count_emitted(&adev->uvd.ring); + + for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) + if (atomic_read(&adev->uvd.handles[i])) + ++handles; + + if (fences == 0 && handles == 0) { + if (adev->pm.dpm_enabled) { + amdgpu_dpm_enable_uvd(adev, false); + } else { + amdgpu_asic_set_uvd_clocks(adev, 0, 0); + } + } else { + schedule_delayed_work(&adev->uvd.idle_work, + msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); + } +} + +static void amdgpu_uvd_note_usage(struct amdgpu_device *adev) +{ + bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); + set_clocks &= schedule_delayed_work(&adev->uvd.idle_work, + msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); + + if (set_clocks) { + if (adev->pm.dpm_enabled) { + amdgpu_dpm_enable_uvd(adev, true); + } else { + amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); + } + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h new file mode 100644 index 000000000000..2255aa710e33 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h @@ -0,0 +1,39 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_UVD_H__ +#define __AMDGPU_UVD_H__ + +int amdgpu_uvd_sw_init(struct amdgpu_device *adev); +int amdgpu_uvd_sw_fini(struct amdgpu_device *adev); +int amdgpu_uvd_suspend(struct amdgpu_device *adev); +int amdgpu_uvd_resume(struct amdgpu_device *adev); +int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, + struct amdgpu_fence **fence); +int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, + struct amdgpu_fence **fence); +void amdgpu_uvd_free_handles(struct amdgpu_device *adev, + struct drm_file *filp); +int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c new file mode 100644 index 000000000000..c65d93cb540d --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -0,0 +1,727 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * Authors: Christian König + */ + +#include +#include +#include +#include + +#include "amdgpu.h" +#include "amdgpu_pm.h" +#include "amdgpu_vce.h" +#include "cikd.h" + +/* 1 second timeout */ +#define VCE_IDLE_TIMEOUT_MS 1000 + +/* Firmware Names */ +#ifdef CONFIG_DRM_AMDGPU_CIK +#define FIRMWARE_BONAIRE "radeon/bonaire_vce.bin" +#define FIRMWARE_KABINI "radeon/kabini_vce.bin" +#define FIRMWARE_KAVERI "radeon/kaveri_vce.bin" +#define FIRMWARE_HAWAII "radeon/hawaii_vce.bin" +#define FIRMWARE_MULLINS "radeon/mullins_vce.bin" +#endif +#define FIRMWARE_TONGA "radeon/tonga_vce.bin" +#define FIRMWARE_CARRIZO "radeon/carrizo_vce.bin" + +#ifdef CONFIG_DRM_AMDGPU_CIK +MODULE_FIRMWARE(FIRMWARE_BONAIRE); +MODULE_FIRMWARE(FIRMWARE_KABINI); +MODULE_FIRMWARE(FIRMWARE_KAVERI); +MODULE_FIRMWARE(FIRMWARE_HAWAII); +MODULE_FIRMWARE(FIRMWARE_MULLINS); +#endif +MODULE_FIRMWARE(FIRMWARE_TONGA); +MODULE_FIRMWARE(FIRMWARE_CARRIZO); + +static void amdgpu_vce_idle_work_handler(struct work_struct *work); + +/** + * amdgpu_vce_init - allocate memory, load vce firmware + * + * @adev: amdgpu_device pointer + * + * First step to get VCE online, allocate memory and load the firmware + */ +int amdgpu_vce_sw_init(struct amdgpu_device *adev) +{ + unsigned long size; + const char *fw_name; + const struct common_firmware_header *hdr; + unsigned ucode_version, version_major, version_minor, binary_id; + int i, r; + + INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler); + + switch (adev->asic_type) { +#ifdef CONFIG_DRM_AMDGPU_CIK + case CHIP_BONAIRE: + fw_name = FIRMWARE_BONAIRE; + break; + case CHIP_KAVERI: + fw_name = FIRMWARE_KAVERI; + break; + case CHIP_KABINI: + fw_name = FIRMWARE_KABINI; + break; + case CHIP_HAWAII: + fw_name = FIRMWARE_HAWAII; + break; + case CHIP_MULLINS: + fw_name = FIRMWARE_MULLINS; + break; +#endif + case CHIP_TONGA: + fw_name = FIRMWARE_TONGA; + break; + case CHIP_CARRIZO: + fw_name = FIRMWARE_CARRIZO; + break; + + default: + return -EINVAL; + } + + r = request_firmware(&adev->vce.fw, fw_name, adev->dev); + if (r) { + dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n", + fw_name); + return r; + } + + r = amdgpu_ucode_validate(adev->vce.fw); + if (r) { + dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n", + fw_name); + release_firmware(adev->vce.fw); + adev->vce.fw = NULL; + return r; + } + + hdr = (const struct common_firmware_header *)adev->vce.fw->data; + + ucode_version = le32_to_cpu(hdr->ucode_version); + version_major = (ucode_version >> 20) & 0xfff; + version_minor = (ucode_version >> 8) & 0xfff; + binary_id = ucode_version & 0xff; + DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n", + version_major, version_minor, binary_id); + adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) | + (binary_id << 8)); + + /* allocate firmware, stack and heap BO */ + + size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes)) + + AMDGPU_VCE_STACK_SIZE + AMDGPU_VCE_HEAP_SIZE; + r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->vce.vcpu_bo); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r); + return r; + } + + r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false); + if (r) { + amdgpu_bo_unref(&adev->vce.vcpu_bo); + dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r); + return r; + } + + r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM, + &adev->vce.gpu_addr); + amdgpu_bo_unreserve(adev->vce.vcpu_bo); + if (r) { + amdgpu_bo_unref(&adev->vce.vcpu_bo); + dev_err(adev->dev, "(%d) VCE bo pin failed\n", r); + return r; + } + + for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) { + atomic_set(&adev->vce.handles[i], 0); + adev->vce.filp[i] = NULL; + } + + return 0; +} + +/** + * amdgpu_vce_fini - free memory + * + * @adev: amdgpu_device pointer + * + * Last step on VCE teardown, free firmware memory + */ +int amdgpu_vce_sw_fini(struct amdgpu_device *adev) +{ + if (adev->vce.vcpu_bo == NULL) + return 0; + + amdgpu_bo_unref(&adev->vce.vcpu_bo); + + amdgpu_ring_fini(&adev->vce.ring[0]); + amdgpu_ring_fini(&adev->vce.ring[1]); + + release_firmware(adev->vce.fw); + + return 0; +} + +/** + * amdgpu_vce_suspend - unpin VCE fw memory + * + * @adev: amdgpu_device pointer + * + */ +int amdgpu_vce_suspend(struct amdgpu_device *adev) +{ + int i; + + if (adev->vce.vcpu_bo == NULL) + return 0; + + for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) + if (atomic_read(&adev->vce.handles[i])) + break; + + if (i == AMDGPU_MAX_VCE_HANDLES) + return 0; + + /* TODO: suspending running encoding sessions isn't supported */ + return -EINVAL; +} + +/** + * amdgpu_vce_resume - pin VCE fw memory + * + * @adev: amdgpu_device pointer + * + */ +int amdgpu_vce_resume(struct amdgpu_device *adev) +{ + void *cpu_addr; + const struct common_firmware_header *hdr; + unsigned offset; + int r; + + if (adev->vce.vcpu_bo == NULL) + return -EINVAL; + + r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false); + if (r) { + dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r); + return r; + } + + r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr); + if (r) { + amdgpu_bo_unreserve(adev->vce.vcpu_bo); + dev_err(adev->dev, "(%d) VCE map failed\n", r); + return r; + } + + hdr = (const struct common_firmware_header *)adev->vce.fw->data; + offset = le32_to_cpu(hdr->ucode_array_offset_bytes); + memcpy(cpu_addr, (adev->vce.fw->data) + offset, + (adev->vce.fw->size) - offset); + + amdgpu_bo_kunmap(adev->vce.vcpu_bo); + + amdgpu_bo_unreserve(adev->vce.vcpu_bo); + + return 0; +} + +/** + * amdgpu_vce_idle_work_handler - power off VCE + * + * @work: pointer to work structure + * + * power of VCE when it's not used any more + */ +static void amdgpu_vce_idle_work_handler(struct work_struct *work) +{ + struct amdgpu_device *adev = + container_of(work, struct amdgpu_device, vce.idle_work.work); + + if ((amdgpu_fence_count_emitted(&adev->vce.ring[0]) == 0) && + (amdgpu_fence_count_emitted(&adev->vce.ring[1]) == 0)) { + if (adev->pm.dpm_enabled) { + amdgpu_dpm_enable_vce(adev, false); + } else { + amdgpu_asic_set_vce_clocks(adev, 0, 0); + } + } else { + schedule_delayed_work(&adev->vce.idle_work, + msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS)); + } +} + +/** + * amdgpu_vce_note_usage - power up VCE + * + * @adev: amdgpu_device pointer + * + * Make sure VCE is powerd up when we want to use it + */ +static void amdgpu_vce_note_usage(struct amdgpu_device *adev) +{ + bool streams_changed = false; + bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work); + set_clocks &= schedule_delayed_work(&adev->vce.idle_work, + msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS)); + + if (adev->pm.dpm_enabled) { + /* XXX figure out if the streams changed */ + streams_changed = false; + } + + if (set_clocks || streams_changed) { + if (adev->pm.dpm_enabled) { + amdgpu_dpm_enable_vce(adev, true); + } else { + amdgpu_asic_set_vce_clocks(adev, 53300, 40000); + } + } +} + +/** + * amdgpu_vce_free_handles - free still open VCE handles + * + * @adev: amdgpu_device pointer + * @filp: drm file pointer + * + * Close all VCE handles still open by this file pointer + */ +void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp) +{ + struct amdgpu_ring *ring = &adev->vce.ring[0]; + int i, r; + for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) { + uint32_t handle = atomic_read(&adev->vce.handles[i]); + if (!handle || adev->vce.filp[i] != filp) + continue; + + amdgpu_vce_note_usage(adev); + + r = amdgpu_vce_get_destroy_msg(ring, handle, NULL); + if (r) + DRM_ERROR("Error destroying VCE handle (%d)!\n", r); + + adev->vce.filp[i] = NULL; + atomic_set(&adev->vce.handles[i], 0); + } +} + +/** + * amdgpu_vce_get_create_msg - generate a VCE create msg + * + * @adev: amdgpu_device pointer + * @ring: ring we should submit the msg to + * @handle: VCE session handle to use + * @fence: optional fence to return + * + * Open up a stream for HW test + */ +int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, + struct amdgpu_fence **fence) +{ + const unsigned ib_size_dw = 1024; + struct amdgpu_ib ib; + uint64_t dummy; + int i, r; + + r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, &ib); + if (r) { + DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); + return r; + } + + dummy = ib.gpu_addr + 1024; + + /* stitch together an VCE create msg */ + ib.length_dw = 0; + ib.ptr[ib.length_dw++] = 0x0000000c; /* len */ + ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */ + ib.ptr[ib.length_dw++] = handle; + + ib.ptr[ib.length_dw++] = 0x00000030; /* len */ + ib.ptr[ib.length_dw++] = 0x01000001; /* create cmd */ + ib.ptr[ib.length_dw++] = 0x00000000; + ib.ptr[ib.length_dw++] = 0x00000042; + ib.ptr[ib.length_dw++] = 0x0000000a; + ib.ptr[ib.length_dw++] = 0x00000001; + ib.ptr[ib.length_dw++] = 0x00000080; + ib.ptr[ib.length_dw++] = 0x00000060; + ib.ptr[ib.length_dw++] = 0x00000100; + ib.ptr[ib.length_dw++] = 0x00000100; + ib.ptr[ib.length_dw++] = 0x0000000c; + ib.ptr[ib.length_dw++] = 0x00000000; + + ib.ptr[ib.length_dw++] = 0x00000014; /* len */ + ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */ + ib.ptr[ib.length_dw++] = upper_32_bits(dummy); + ib.ptr[ib.length_dw++] = dummy; + ib.ptr[ib.length_dw++] = 0x00000001; + + for (i = ib.length_dw; i < ib_size_dw; ++i) + ib.ptr[i] = 0x0; + + r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); + if (r) { + DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); + } + + if (fence) + *fence = amdgpu_fence_ref(ib.fence); + + amdgpu_ib_free(ring->adev, &ib); + + return r; +} + +/** + * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg + * + * @adev: amdgpu_device pointer + * @ring: ring we should submit the msg to + * @handle: VCE session handle to use + * @fence: optional fence to return + * + * Close up a stream for HW test or if userspace failed to do so + */ +int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, + struct amdgpu_fence **fence) +{ + const unsigned ib_size_dw = 1024; + struct amdgpu_ib ib; + uint64_t dummy; + int i, r; + + r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, &ib); + if (r) { + DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); + return r; + } + + dummy = ib.gpu_addr + 1024; + + /* stitch together an VCE destroy msg */ + ib.length_dw = 0; + ib.ptr[ib.length_dw++] = 0x0000000c; /* len */ + ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */ + ib.ptr[ib.length_dw++] = handle; + + ib.ptr[ib.length_dw++] = 0x00000014; /* len */ + ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */ + ib.ptr[ib.length_dw++] = upper_32_bits(dummy); + ib.ptr[ib.length_dw++] = dummy; + ib.ptr[ib.length_dw++] = 0x00000001; + + ib.ptr[ib.length_dw++] = 0x00000008; /* len */ + ib.ptr[ib.length_dw++] = 0x02000001; /* destroy cmd */ + + for (i = ib.length_dw; i < ib_size_dw; ++i) + ib.ptr[i] = 0x0; + + r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); + if (r) { + DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); + } + + if (fence) + *fence = amdgpu_fence_ref(ib.fence); + + amdgpu_ib_free(ring->adev, &ib); + + return r; +} + +/** + * amdgpu_vce_cs_reloc - command submission relocation + * + * @p: parser context + * @lo: address of lower dword + * @hi: address of higher dword + * + * Patch relocation inside command stream with real buffer address + */ +int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx, int lo, int hi) +{ + struct amdgpu_bo_va_mapping *mapping; + struct amdgpu_ib *ib = &p->ibs[ib_idx]; + struct amdgpu_bo *bo; + uint64_t addr; + + addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) | + ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32; + + mapping = amdgpu_cs_find_mapping(p, addr, &bo); + if (mapping == NULL) { + DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d\n", + addr, lo, hi); + return -EINVAL; + } + + addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE; + addr += amdgpu_bo_gpu_offset(bo); + + ib->ptr[lo] = addr & 0xFFFFFFFF; + ib->ptr[hi] = addr >> 32; + + return 0; +} + +/** + * amdgpu_vce_cs_parse - parse and validate the command stream + * + * @p: parser context + * + */ +int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) +{ + uint32_t handle = 0; + bool destroy = false; + int i, r, idx = 0; + struct amdgpu_ib *ib = &p->ibs[ib_idx]; + + amdgpu_vce_note_usage(p->adev); + + while (idx < ib->length_dw) { + uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx); + uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1); + + if ((len < 8) || (len & 3)) { + DRM_ERROR("invalid VCE command length (%d)!\n", len); + return -EINVAL; + } + + switch (cmd) { + case 0x00000001: // session + handle = amdgpu_get_ib_value(p, ib_idx, idx + 2); + break; + + case 0x00000002: // task info + case 0x01000001: // create + case 0x04000001: // config extension + case 0x04000002: // pic control + case 0x04000005: // rate control + case 0x04000007: // motion estimation + case 0x04000008: // rdo + case 0x04000009: // vui + case 0x05000002: // auxiliary buffer + break; + + case 0x03000001: // encode + r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9); + if (r) + return r; + + r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11); + if (r) + return r; + break; + + case 0x02000001: // destroy + destroy = true; + break; + + case 0x05000001: // context buffer + case 0x05000004: // video bitstream buffer + case 0x05000005: // feedback buffer + r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2); + if (r) + return r; + break; + + default: + DRM_ERROR("invalid VCE command (0x%x)!\n", cmd); + return -EINVAL; + } + + idx += len / 4; + } + + if (destroy) { + /* IB contains a destroy msg, free the handle */ + for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) + atomic_cmpxchg(&p->adev->vce.handles[i], handle, 0); + + return 0; + } + + /* create or encode, validate the handle */ + for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) { + if (atomic_read(&p->adev->vce.handles[i]) == handle) + return 0; + } + + /* handle not found try to alloc a new one */ + for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) { + if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) { + p->adev->vce.filp[i] = p->filp; + return 0; + } + } + + DRM_ERROR("No more free VCE handles!\n"); + + return -EINVAL; +} + +/** + * amdgpu_vce_ring_emit_semaphore - emit a semaphore command + * + * @ring: engine to use + * @semaphore: address of semaphore + * @emit_wait: true=emit wait, false=emit signal + * + */ +bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore, + bool emit_wait) +{ + uint64_t addr = semaphore->gpu_addr; + + amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE); + amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); + amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); + amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0)); + if (!emit_wait) + amdgpu_ring_write(ring, VCE_CMD_END); + + return true; +} + +/** + * amdgpu_vce_ring_emit_ib - execute indirect buffer + * + * @ring: engine to use + * @ib: the IB to execute + * + */ +void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) +{ + amdgpu_ring_write(ring, VCE_CMD_IB); + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, ib->length_dw); +} + +/** + * amdgpu_vce_ring_emit_fence - add a fence command to the ring + * + * @ring: engine to use + * @fence: the fence + * + */ +void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + bool write64bits) +{ + WARN_ON(write64bits); + + amdgpu_ring_write(ring, VCE_CMD_FENCE); + amdgpu_ring_write(ring, addr); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, seq); + amdgpu_ring_write(ring, VCE_CMD_TRAP); + amdgpu_ring_write(ring, VCE_CMD_END); +} + +/** + * amdgpu_vce_ring_test_ring - test if VCE ring is working + * + * @ring: the engine to test on + * + */ +int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t rptr = amdgpu_ring_get_rptr(ring); + unsigned i; + int r; + + r = amdgpu_ring_lock(ring, 16); + if (r) { + DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n", + ring->idx, r); + return r; + } + amdgpu_ring_write(ring, VCE_CMD_END); + amdgpu_ring_unlock_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + if (amdgpu_ring_get_rptr(ring) != rptr) + break; + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", + ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed\n", + ring->idx); + r = -ETIMEDOUT; + } + + return r; +} + +/** + * amdgpu_vce_ring_test_ib - test if VCE IBs are working + * + * @ring: the engine to test on + * + */ +int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring) +{ + struct amdgpu_fence *fence = NULL; + int r; + + r = amdgpu_vce_get_create_msg(ring, 1, NULL); + if (r) { + DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); + goto error; + } + + r = amdgpu_vce_get_destroy_msg(ring, 1, &fence); + if (r) { + DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); + goto error; + } + + r = amdgpu_fence_wait(fence, false); + if (r) { + DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + } else { + DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + } +error: + amdgpu_fence_unref(&fence); + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h new file mode 100644 index 000000000000..b9411e43db25 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -0,0 +1,47 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_VCE_H__ +#define __AMDGPU_VCE_H__ + +int amdgpu_vce_sw_init(struct amdgpu_device *adev); +int amdgpu_vce_sw_fini(struct amdgpu_device *adev); +int amdgpu_vce_suspend(struct amdgpu_device *adev); +int amdgpu_vce_resume(struct amdgpu_device *adev); +int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, + struct amdgpu_fence **fence); +int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, + struct amdgpu_fence **fence); +void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp); +int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx, int lo, int hi); +int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx); +bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore, + bool emit_wait); +void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); +void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + bool write64bit); +int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring); +int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c new file mode 100644 index 000000000000..1cc01fb409dc --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -0,0 +1,1248 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * Copyright 2009 Jerome Glisse. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include +#include +#include "amdgpu.h" +#include "amdgpu_trace.h" + +/* + * GPUVM + * GPUVM is similar to the legacy gart on older asics, however + * rather than there being a single global gart table + * for the entire GPU, there are multiple VM page tables active + * at any given time. The VM page tables can contain a mix + * vram pages and system memory pages and system memory pages + * can be mapped as snooped (cached system pages) or unsnooped + * (uncached system pages). + * Each VM has an ID associated with it and there is a page table + * associated with each VMID. When execting a command buffer, + * the kernel tells the the ring what VMID to use for that command + * buffer. VMIDs are allocated dynamically as commands are submitted. + * The userspace drivers maintain their own address space and the kernel + * sets up their pages tables accordingly when they submit their + * command buffers and a VMID is assigned. + * Cayman/Trinity support up to 8 active VMs at any given time; + * SI supports 16. + */ + +/** + * amdgpu_vm_num_pde - return the number of page directory entries + * + * @adev: amdgpu_device pointer + * + * Calculate the number of page directory entries (cayman+). + */ +static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) +{ + return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; +} + +/** + * amdgpu_vm_directory_size - returns the size of the page directory in bytes + * + * @adev: amdgpu_device pointer + * + * Calculate the size of the page directory in bytes (cayman+). + */ +static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) +{ + return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); +} + +/** + * amdgpu_vm_get_bos - add the vm BOs to a validation list + * + * @vm: vm providing the BOs + * @head: head of validation list + * + * Add the page directory to the list of BOs to + * validate for command submission (cayman+). + */ +struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct list_head *head) +{ + struct amdgpu_bo_list_entry *list; + unsigned i, idx; + + list = drm_malloc_ab(vm->max_pde_used + 2, + sizeof(struct amdgpu_bo_list_entry)); + if (!list) + return NULL; + + /* add the vm page table to the list */ + list[0].robj = vm->page_directory; + list[0].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM; + list[0].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM; + list[0].priority = 0; + list[0].tv.bo = &vm->page_directory->tbo; + list[0].tv.shared = true; + list_add(&list[0].tv.head, head); + + for (i = 0, idx = 1; i <= vm->max_pde_used; i++) { + if (!vm->page_tables[i].bo) + continue; + + list[idx].robj = vm->page_tables[i].bo; + list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM; + list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM; + list[idx].priority = 0; + list[idx].tv.bo = &list[idx].robj->tbo; + list[idx].tv.shared = true; + list_add(&list[idx++].tv.head, head); + } + + return list; +} + +/** + * amdgpu_vm_grab_id - allocate the next free VMID + * + * @ring: ring we want to submit job to + * @vm: vm to allocate id for + * + * Allocate an id for the vm (cayman+). + * Returns the fence we need to sync to (if any). + * + * Global and local mutex must be locked! + */ +struct amdgpu_fence *amdgpu_vm_grab_id(struct amdgpu_ring *ring, + struct amdgpu_vm *vm) +{ + struct amdgpu_fence *best[AMDGPU_MAX_RINGS] = {}; + struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; + struct amdgpu_device *adev = ring->adev; + + unsigned choices[2] = {}; + unsigned i; + + /* check if the id is still valid */ + if (vm_id->id && vm_id->last_id_use && + vm_id->last_id_use == adev->vm_manager.active[vm_id->id]) + return NULL; + + /* we definately need to flush */ + vm_id->pd_gpu_addr = ~0ll; + + /* skip over VMID 0, since it is the system VM */ + for (i = 1; i < adev->vm_manager.nvm; ++i) { + struct amdgpu_fence *fence = adev->vm_manager.active[i]; + + if (fence == NULL) { + /* found a free one */ + vm_id->id = i; + trace_amdgpu_vm_grab_id(i, ring->idx); + return NULL; + } + + if (amdgpu_fence_is_earlier(fence, best[fence->ring->idx])) { + best[fence->ring->idx] = fence; + choices[fence->ring == ring ? 0 : 1] = i; + } + } + + for (i = 0; i < 2; ++i) { + if (choices[i]) { + vm_id->id = choices[i]; + trace_amdgpu_vm_grab_id(choices[i], ring->idx); + return adev->vm_manager.active[choices[i]]; + } + } + + /* should never happen */ + BUG(); + return NULL; +} + +/** + * amdgpu_vm_flush - hardware flush the vm + * + * @ring: ring to use for flush + * @vm: vm we want to flush + * @updates: last vm update that we waited for + * + * Flush the vm (cayman+). + * + * Global and local mutex must be locked! + */ +void amdgpu_vm_flush(struct amdgpu_ring *ring, + struct amdgpu_vm *vm, + struct amdgpu_fence *updates) +{ + uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); + struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; + + if (pd_addr != vm_id->pd_gpu_addr || !vm_id->flushed_updates || + amdgpu_fence_is_earlier(vm_id->flushed_updates, updates)) { + + trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id); + amdgpu_fence_unref(&vm_id->flushed_updates); + vm_id->flushed_updates = amdgpu_fence_ref(updates); + vm_id->pd_gpu_addr = pd_addr; + amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr); + } +} + +/** + * amdgpu_vm_fence - remember fence for vm + * + * @adev: amdgpu_device pointer + * @vm: vm we want to fence + * @fence: fence to remember + * + * Fence the vm (cayman+). + * Set the fence used to protect page table and id. + * + * Global and local mutex must be locked! + */ +void amdgpu_vm_fence(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_fence *fence) +{ + unsigned ridx = fence->ring->idx; + unsigned vm_id = vm->ids[ridx].id; + + amdgpu_fence_unref(&adev->vm_manager.active[vm_id]); + adev->vm_manager.active[vm_id] = amdgpu_fence_ref(fence); + + amdgpu_fence_unref(&vm->ids[ridx].last_id_use); + vm->ids[ridx].last_id_use = amdgpu_fence_ref(fence); +} + +/** + * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo + * + * @vm: requested vm + * @bo: requested buffer object + * + * Find @bo inside the requested vm (cayman+). + * Search inside the @bos vm list for the requested vm + * Returns the found bo_va or NULL if none is found + * + * Object has to be reserved! + */ +struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, + struct amdgpu_bo *bo) +{ + struct amdgpu_bo_va *bo_va; + + list_for_each_entry(bo_va, &bo->va, bo_list) { + if (bo_va->vm == vm) { + return bo_va; + } + } + return NULL; +} + +/** + * amdgpu_vm_update_pages - helper to call the right asic function + * + * @adev: amdgpu_device pointer + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: hw access flags + * @gtt_flags: GTT hw access flags + * + * Traces the parameters and calls the right asic functions + * to setup the page table using the DMA. + */ +static void amdgpu_vm_update_pages(struct amdgpu_device *adev, + struct amdgpu_ib *ib, + uint64_t pe, uint64_t addr, + unsigned count, uint32_t incr, + uint32_t flags, uint32_t gtt_flags) +{ + trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); + + if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) { + uint64_t src = adev->gart.table_addr + (addr >> 12) * 8; + amdgpu_vm_copy_pte(adev, ib, pe, src, count); + + } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) { + amdgpu_vm_write_pte(adev, ib, pe, addr, + count, incr, flags); + + } else { + amdgpu_vm_set_pte_pde(adev, ib, pe, addr, + count, incr, flags); + } +} + +/** + * amdgpu_vm_clear_bo - initially clear the page dir/table + * + * @adev: amdgpu_device pointer + * @bo: bo to clear + */ +static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, + struct amdgpu_bo *bo) +{ + struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; + struct amdgpu_ib ib; + unsigned entries; + uint64_t addr; + int r; + + r = amdgpu_bo_reserve(bo, false); + if (r) + return r; + + r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + if (r) + goto error_unreserve; + + addr = amdgpu_bo_gpu_offset(bo); + entries = amdgpu_bo_size(bo) / 8; + + r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, &ib); + if (r) + goto error_unreserve; + + ib.length_dw = 0; + + amdgpu_vm_update_pages(adev, &ib, addr, 0, entries, 0, 0, 0); + amdgpu_vm_pad_ib(adev, &ib); + WARN_ON(ib.length_dw > 64); + + r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_VM); + if (r) + goto error_free; + + amdgpu_bo_fence(bo, ib.fence, false); + +error_free: + amdgpu_ib_free(adev, &ib); + +error_unreserve: + amdgpu_bo_unreserve(bo); + return r; +} + +/** + * amdgpu_vm_map_gart - get the physical address of a gart page + * + * @adev: amdgpu_device pointer + * @addr: the unmapped addr + * + * Look up the physical address of the page that the pte resolves + * to (cayman+). + * Returns the physical address of the page. + */ +uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr) +{ + uint64_t result; + + /* page table offset */ + result = adev->gart.pages_addr[addr >> PAGE_SHIFT]; + + /* in case cpu page size != gpu page size*/ + result |= addr & (~PAGE_MASK); + + return result; +} + +/** + * amdgpu_vm_update_pdes - make sure that page directory is valid + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * @start: start of GPU address range + * @end: end of GPU address range + * + * Allocates new page tables if necessary + * and updates the page directory (cayman+). + * Returns 0 for success, error for failure. + * + * Global and local mutex must be locked! + */ +int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, + struct amdgpu_vm *vm) +{ + struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; + struct amdgpu_bo *pd = vm->page_directory; + uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); + uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; + uint64_t last_pde = ~0, last_pt = ~0; + unsigned count = 0, pt_idx, ndw; + struct amdgpu_ib ib; + int r; + + /* padding, etc. */ + ndw = 64; + + /* assume the worst case */ + ndw += vm->max_pde_used * 6; + + /* update too big for an IB */ + if (ndw > 0xfffff) + return -ENOMEM; + + r = amdgpu_ib_get(ring, NULL, ndw * 4, &ib); + if (r) + return r; + ib.length_dw = 0; + + /* walk over the address space and update the page directory */ + for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { + struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo; + uint64_t pde, pt; + + if (bo == NULL) + continue; + + pt = amdgpu_bo_gpu_offset(bo); + if (vm->page_tables[pt_idx].addr == pt) + continue; + vm->page_tables[pt_idx].addr = pt; + + pde = pd_addr + pt_idx * 8; + if (((last_pde + 8 * count) != pde) || + ((last_pt + incr * count) != pt)) { + + if (count) { + amdgpu_vm_update_pages(adev, &ib, last_pde, + last_pt, count, incr, + AMDGPU_PTE_VALID, 0); + } + + count = 1; + last_pde = pde; + last_pt = pt; + } else { + ++count; + } + } + + if (count) + amdgpu_vm_update_pages(adev, &ib, last_pde, last_pt, count, + incr, AMDGPU_PTE_VALID, 0); + + if (ib.length_dw != 0) { + amdgpu_vm_pad_ib(adev, &ib); + amdgpu_sync_resv(adev, &ib.sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM); + WARN_ON(ib.length_dw > ndw); + r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_VM); + if (r) { + amdgpu_ib_free(adev, &ib); + return r; + } + amdgpu_bo_fence(pd, ib.fence, false); + } + amdgpu_ib_free(adev, &ib); + + return 0; +} + +/** + * amdgpu_vm_frag_ptes - add fragment information to PTEs + * + * @adev: amdgpu_device pointer + * @ib: IB for the update + * @pe_start: first PTE to handle + * @pe_end: last PTE to handle + * @addr: addr those PTEs should point to + * @flags: hw mapping flags + * @gtt_flags: GTT hw mapping flags + * + * Global and local mutex must be locked! + */ +static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, + struct amdgpu_ib *ib, + uint64_t pe_start, uint64_t pe_end, + uint64_t addr, uint32_t flags, + uint32_t gtt_flags) +{ + /** + * The MC L1 TLB supports variable sized pages, based on a fragment + * field in the PTE. When this field is set to a non-zero value, page + * granularity is increased from 4KB to (1 << (12 + frag)). The PTE + * flags are considered valid for all PTEs within the fragment range + * and corresponding mappings are assumed to be physically contiguous. + * + * The L1 TLB can store a single PTE for the whole fragment, + * significantly increasing the space available for translation + * caching. This leads to large improvements in throughput when the + * TLB is under pressure. + * + * The L2 TLB distributes small and large fragments into two + * asymmetric partitions. The large fragment cache is significantly + * larger. Thus, we try to use large fragments wherever possible. + * Userspace can support this by aligning virtual base address and + * allocation size to the fragment size. + */ + + /* SI and newer are optimized for 64KB */ + uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; + uint64_t frag_align = 0x80; + + uint64_t frag_start = ALIGN(pe_start, frag_align); + uint64_t frag_end = pe_end & ~(frag_align - 1); + + unsigned count; + + /* system pages are non continuously */ + if ((flags & AMDGPU_PTE_SYSTEM) || !(flags & AMDGPU_PTE_VALID) || + (frag_start >= frag_end)) { + + count = (pe_end - pe_start) / 8; + amdgpu_vm_update_pages(adev, ib, pe_start, addr, count, + AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); + return; + } + + /* handle the 4K area at the beginning */ + if (pe_start != frag_start) { + count = (frag_start - pe_start) / 8; + amdgpu_vm_update_pages(adev, ib, pe_start, addr, count, + AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); + addr += AMDGPU_GPU_PAGE_SIZE * count; + } + + /* handle the area in the middle */ + count = (frag_end - frag_start) / 8; + amdgpu_vm_update_pages(adev, ib, frag_start, addr, count, + AMDGPU_GPU_PAGE_SIZE, flags | frag_flags, + gtt_flags); + + /* handle the 4K area at the end */ + if (frag_end != pe_end) { + addr += AMDGPU_GPU_PAGE_SIZE * count; + count = (pe_end - frag_end) / 8; + amdgpu_vm_update_pages(adev, ib, frag_end, addr, count, + AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); + } +} + +/** + * amdgpu_vm_update_ptes - make sure that page tables are valid + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * @start: start of GPU address range + * @end: end of GPU address range + * @dst: destination address to map to + * @flags: mapping flags + * + * Update the page tables in the range @start - @end (cayman+). + * + * Global and local mutex must be locked! + */ +static int amdgpu_vm_update_ptes(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_ib *ib, + uint64_t start, uint64_t end, + uint64_t dst, uint32_t flags, + uint32_t gtt_flags) +{ + uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; + uint64_t last_pte = ~0, last_dst = ~0; + unsigned count = 0; + uint64_t addr; + + /* walk over the address space and update the page tables */ + for (addr = start; addr < end; ) { + uint64_t pt_idx = addr >> amdgpu_vm_block_size; + struct amdgpu_bo *pt = vm->page_tables[pt_idx].bo; + unsigned nptes; + uint64_t pte; + int r; + + amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, + AMDGPU_FENCE_OWNER_VM); + r = reservation_object_reserve_shared(pt->tbo.resv); + if (r) + return r; + + if ((addr & ~mask) == (end & ~mask)) + nptes = end - addr; + else + nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); + + pte = amdgpu_bo_gpu_offset(pt); + pte += (addr & mask) * 8; + + if ((last_pte + 8 * count) != pte) { + + if (count) { + amdgpu_vm_frag_ptes(adev, ib, last_pte, + last_pte + 8 * count, + last_dst, flags, + gtt_flags); + } + + count = nptes; + last_pte = pte; + last_dst = dst; + } else { + count += nptes; + } + + addr += nptes; + dst += nptes * AMDGPU_GPU_PAGE_SIZE; + } + + if (count) { + amdgpu_vm_frag_ptes(adev, ib, last_pte, + last_pte + 8 * count, + last_dst, flags, gtt_flags); + } + + return 0; +} + +/** + * amdgpu_vm_fence_pts - fence page tables after an update + * + * @vm: requested vm + * @start: start of GPU address range + * @end: end of GPU address range + * @fence: fence to use + * + * Fence the page tables in the range @start - @end (cayman+). + * + * Global and local mutex must be locked! + */ +static void amdgpu_vm_fence_pts(struct amdgpu_vm *vm, + uint64_t start, uint64_t end, + struct amdgpu_fence *fence) +{ + unsigned i; + + start >>= amdgpu_vm_block_size; + end >>= amdgpu_vm_block_size; + + for (i = start; i <= end; ++i) + amdgpu_bo_fence(vm->page_tables[i].bo, fence, true); +} + +/** + * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * @mapping: mapped range and flags to use for the update + * @addr: addr to set the area to + * @gtt_flags: flags as they are used for GTT + * @fence: optional resulting fence + * + * Fill in the page table entries for @mapping. + * Returns 0 for success, -EINVAL for failure. + * + * Object have to be reserved and mutex must be locked! + */ +static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_bo_va_mapping *mapping, + uint64_t addr, uint32_t gtt_flags, + struct amdgpu_fence **fence) +{ + struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; + unsigned nptes, ncmds, ndw; + uint32_t flags = gtt_flags; + struct amdgpu_ib ib; + int r; + + /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here + * but in case of something, we filter the flags in first place + */ + if (!(mapping->flags & AMDGPU_PTE_READABLE)) + flags &= ~AMDGPU_PTE_READABLE; + if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) + flags &= ~AMDGPU_PTE_WRITEABLE; + + trace_amdgpu_vm_bo_update(mapping); + + nptes = mapping->it.last - mapping->it.start + 1; + + /* + * reserve space for one command every (1 << BLOCK_SIZE) + * entries or 2k dwords (whatever is smaller) + */ + ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; + + /* padding, etc. */ + ndw = 64; + + if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) { + /* only copy commands needed */ + ndw += ncmds * 7; + + } else if (flags & AMDGPU_PTE_SYSTEM) { + /* header for write data commands */ + ndw += ncmds * 4; + + /* body of write data command */ + ndw += nptes * 2; + + } else { + /* set page commands needed */ + ndw += ncmds * 10; + + /* two extra commands for begin/end of fragment */ + ndw += 2 * 10; + } + + /* update too big for an IB */ + if (ndw > 0xfffff) + return -ENOMEM; + + r = amdgpu_ib_get(ring, NULL, ndw * 4, &ib); + if (r) + return r; + ib.length_dw = 0; + + if (!(flags & AMDGPU_PTE_VALID)) { + unsigned i; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + struct amdgpu_fence *f = vm->ids[i].last_id_use; + amdgpu_sync_fence(&ib.sync, f); + } + } + + r = amdgpu_vm_update_ptes(adev, vm, &ib, mapping->it.start, + mapping->it.last + 1, addr + mapping->offset, + flags, gtt_flags); + + if (r) { + amdgpu_ib_free(adev, &ib); + return r; + } + + amdgpu_vm_pad_ib(adev, &ib); + WARN_ON(ib.length_dw > ndw); + + r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_VM); + if (r) { + amdgpu_ib_free(adev, &ib); + return r; + } + amdgpu_vm_fence_pts(vm, mapping->it.start, + mapping->it.last + 1, ib.fence); + if (fence) { + amdgpu_fence_unref(fence); + *fence = amdgpu_fence_ref(ib.fence); + } + amdgpu_ib_free(adev, &ib); + + return 0; +} + +/** + * amdgpu_vm_bo_update - update all BO mappings in the vm page table + * + * @adev: amdgpu_device pointer + * @bo_va: requested BO and VM object + * @mem: ttm mem + * + * Fill in the page table entries for @bo_va. + * Returns 0 for success, -EINVAL for failure. + * + * Object have to be reserved and mutex must be locked! + */ +int amdgpu_vm_bo_update(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + struct ttm_mem_reg *mem) +{ + struct amdgpu_vm *vm = bo_va->vm; + struct amdgpu_bo_va_mapping *mapping; + uint32_t flags; + uint64_t addr; + int r; + + if (mem) { + addr = mem->start << PAGE_SHIFT; + if (mem->mem_type != TTM_PL_TT) + addr += adev->vm_manager.vram_base_offset; + } else { + addr = 0; + } + + if (addr == bo_va->addr) + return 0; + + flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); + + list_for_each_entry(mapping, &bo_va->mappings, list) { + r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, addr, + flags, &bo_va->last_pt_update); + if (r) + return r; + } + + bo_va->addr = addr; + spin_lock(&vm->status_lock); + list_del_init(&bo_va->vm_status); + spin_unlock(&vm->status_lock); + + return 0; +} + +/** + * amdgpu_vm_clear_freed - clear freed BOs in the PT + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * + * Make sure all freed BOs are cleared in the PT. + * Returns 0 for success. + * + * PTs have to be reserved and mutex must be locked! + */ +int amdgpu_vm_clear_freed(struct amdgpu_device *adev, + struct amdgpu_vm *vm) +{ + struct amdgpu_bo_va_mapping *mapping; + int r; + + while (!list_empty(&vm->freed)) { + mapping = list_first_entry(&vm->freed, + struct amdgpu_bo_va_mapping, list); + list_del(&mapping->list); + + r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL); + kfree(mapping); + if (r) + return r; + + } + return 0; + +} + +/** + * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * + * Make sure all invalidated BOs are cleared in the PT. + * Returns 0 for success. + * + * PTs have to be reserved and mutex must be locked! + */ +int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, + struct amdgpu_vm *vm) +{ + struct amdgpu_bo_va *bo_va; + int r; + + spin_lock(&vm->status_lock); + while (!list_empty(&vm->invalidated)) { + bo_va = list_first_entry(&vm->invalidated, + struct amdgpu_bo_va, vm_status); + spin_unlock(&vm->status_lock); + + r = amdgpu_vm_bo_update(adev, bo_va, NULL); + if (r) + return r; + + spin_lock(&vm->status_lock); + } + spin_unlock(&vm->status_lock); + + return 0; +} + +/** + * amdgpu_vm_bo_add - add a bo to a specific vm + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * @bo: amdgpu buffer object + * + * Add @bo into the requested vm (cayman+). + * Add @bo to the list of bos associated with the vm + * Returns newly added bo_va or NULL for failure + * + * Object has to be reserved! + */ +struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_bo *bo) +{ + struct amdgpu_bo_va *bo_va; + + bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); + if (bo_va == NULL) { + return NULL; + } + bo_va->vm = vm; + bo_va->bo = bo; + bo_va->addr = 0; + bo_va->ref_count = 1; + INIT_LIST_HEAD(&bo_va->bo_list); + INIT_LIST_HEAD(&bo_va->mappings); + INIT_LIST_HEAD(&bo_va->vm_status); + + mutex_lock(&vm->mutex); + list_add_tail(&bo_va->bo_list, &bo->va); + mutex_unlock(&vm->mutex); + + return bo_va; +} + +/** + * amdgpu_vm_bo_map - map bo inside a vm + * + * @adev: amdgpu_device pointer + * @bo_va: bo_va to store the address + * @saddr: where to map the BO + * @offset: requested offset in the BO + * @flags: attributes of pages (read/write/valid/etc.) + * + * Add a mapping of the BO at the specefied addr into the VM. + * Returns 0 for success, error for failure. + * + * Object has to be reserved and gets unreserved by this function! + */ +int amdgpu_vm_bo_map(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + uint64_t saddr, uint64_t offset, + uint64_t size, uint32_t flags) +{ + struct amdgpu_bo_va_mapping *mapping; + struct amdgpu_vm *vm = bo_va->vm; + struct interval_tree_node *it; + unsigned last_pfn, pt_idx; + uint64_t eaddr; + int r; + + /* make sure object fit at this offset */ + eaddr = saddr + size; + if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) { + amdgpu_bo_unreserve(bo_va->bo); + return -EINVAL; + } + + last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; + if (last_pfn > adev->vm_manager.max_pfn) { + dev_err(adev->dev, "va above limit (0x%08X > 0x%08X)\n", + last_pfn, adev->vm_manager.max_pfn); + amdgpu_bo_unreserve(bo_va->bo); + return -EINVAL; + } + + mutex_lock(&vm->mutex); + + saddr /= AMDGPU_GPU_PAGE_SIZE; + eaddr /= AMDGPU_GPU_PAGE_SIZE; + + it = interval_tree_iter_first(&vm->va, saddr, eaddr - 1); + if (it) { + struct amdgpu_bo_va_mapping *tmp; + tmp = container_of(it, struct amdgpu_bo_va_mapping, it); + /* bo and tmp overlap, invalid addr */ + dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " + "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, + tmp->it.start, tmp->it.last + 1); + amdgpu_bo_unreserve(bo_va->bo); + r = -EINVAL; + goto error_unlock; + } + + mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); + if (!mapping) { + amdgpu_bo_unreserve(bo_va->bo); + r = -ENOMEM; + goto error_unlock; + } + + INIT_LIST_HEAD(&mapping->list); + mapping->it.start = saddr; + mapping->it.last = eaddr - 1; + mapping->offset = offset; + mapping->flags = flags; + + list_add(&mapping->list, &bo_va->mappings); + interval_tree_insert(&mapping->it, &vm->va); + + /* Make sure the page tables are allocated */ + saddr >>= amdgpu_vm_block_size; + eaddr >>= amdgpu_vm_block_size; + + BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); + + if (eaddr > vm->max_pde_used) + vm->max_pde_used = eaddr; + + amdgpu_bo_unreserve(bo_va->bo); + + /* walk over the address space and allocate the page tables */ + for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { + struct amdgpu_bo *pt; + + if (vm->page_tables[pt_idx].bo) + continue; + + /* drop mutex to allocate and clear page table */ + mutex_unlock(&vm->mutex); + + r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, + AMDGPU_GPU_PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &pt); + if (r) + goto error_free; + + r = amdgpu_vm_clear_bo(adev, pt); + if (r) { + amdgpu_bo_unref(&pt); + goto error_free; + } + + /* aquire mutex again */ + mutex_lock(&vm->mutex); + if (vm->page_tables[pt_idx].bo) { + /* someone else allocated the pt in the meantime */ + mutex_unlock(&vm->mutex); + amdgpu_bo_unref(&pt); + mutex_lock(&vm->mutex); + continue; + } + + vm->page_tables[pt_idx].addr = 0; + vm->page_tables[pt_idx].bo = pt; + } + + mutex_unlock(&vm->mutex); + return 0; + +error_free: + mutex_lock(&vm->mutex); + list_del(&mapping->list); + interval_tree_remove(&mapping->it, &vm->va); + kfree(mapping); + +error_unlock: + mutex_unlock(&vm->mutex); + return r; +} + +/** + * amdgpu_vm_bo_unmap - remove bo mapping from vm + * + * @adev: amdgpu_device pointer + * @bo_va: bo_va to remove the address from + * @saddr: where to the BO is mapped + * + * Remove a mapping of the BO at the specefied addr from the VM. + * Returns 0 for success, error for failure. + * + * Object has to be reserved and gets unreserved by this function! + */ +int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va, + uint64_t saddr) +{ + struct amdgpu_bo_va_mapping *mapping; + struct amdgpu_vm *vm = bo_va->vm; + + list_for_each_entry(mapping, &bo_va->mappings, list) { + if (mapping->it.start == saddr) + break; + } + + if (&mapping->list == &bo_va->mappings) { + amdgpu_bo_unreserve(bo_va->bo); + return -ENOENT; + } + + mutex_lock(&vm->mutex); + list_del(&mapping->list); + interval_tree_remove(&mapping->it, &vm->va); + + if (bo_va->addr) { + /* clear the old address */ + list_add(&mapping->list, &vm->freed); + } else { + kfree(mapping); + } + mutex_unlock(&vm->mutex); + amdgpu_bo_unreserve(bo_va->bo); + + return 0; +} + +/** + * amdgpu_vm_bo_rmv - remove a bo to a specific vm + * + * @adev: amdgpu_device pointer + * @bo_va: requested bo_va + * + * Remove @bo_va->bo from the requested vm (cayman+). + * + * Object have to be reserved! + */ +void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, + struct amdgpu_bo_va *bo_va) +{ + struct amdgpu_bo_va_mapping *mapping, *next; + struct amdgpu_vm *vm = bo_va->vm; + + list_del(&bo_va->bo_list); + + mutex_lock(&vm->mutex); + + spin_lock(&vm->status_lock); + list_del(&bo_va->vm_status); + spin_unlock(&vm->status_lock); + + list_for_each_entry_safe(mapping, next, &bo_va->mappings, list) { + list_del(&mapping->list); + interval_tree_remove(&mapping->it, &vm->va); + if (bo_va->addr) + list_add(&mapping->list, &vm->freed); + else + kfree(mapping); + } + amdgpu_fence_unref(&bo_va->last_pt_update); + kfree(bo_va); + + mutex_unlock(&vm->mutex); +} + +/** + * amdgpu_vm_bo_invalidate - mark the bo as invalid + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * @bo: amdgpu buffer object + * + * Mark @bo as invalid (cayman+). + */ +void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, + struct amdgpu_bo *bo) +{ + struct amdgpu_bo_va *bo_va; + + list_for_each_entry(bo_va, &bo->va, bo_list) { + if (bo_va->addr) { + spin_lock(&bo_va->vm->status_lock); + list_del(&bo_va->vm_status); + list_add(&bo_va->vm_status, &bo_va->vm->invalidated); + spin_unlock(&bo_va->vm->status_lock); + } + } +} + +/** + * amdgpu_vm_init - initialize a vm instance + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * + * Init @vm fields (cayman+). + */ +int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) +{ + const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, + AMDGPU_VM_PTE_COUNT * 8); + unsigned pd_size, pd_entries, pts_size; + int i, r; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + vm->ids[i].id = 0; + vm->ids[i].flushed_updates = NULL; + vm->ids[i].last_id_use = NULL; + } + mutex_init(&vm->mutex); + vm->va = RB_ROOT; + spin_lock_init(&vm->status_lock); + INIT_LIST_HEAD(&vm->invalidated); + INIT_LIST_HEAD(&vm->freed); + + pd_size = amdgpu_vm_directory_size(adev); + pd_entries = amdgpu_vm_num_pdes(adev); + + /* allocate page table array */ + pts_size = pd_entries * sizeof(struct amdgpu_vm_pt); + vm->page_tables = kzalloc(pts_size, GFP_KERNEL); + if (vm->page_tables == NULL) { + DRM_ERROR("Cannot allocate memory for page table array\n"); + return -ENOMEM; + } + + r = amdgpu_bo_create(adev, pd_size, align, true, + AMDGPU_GEM_DOMAIN_VRAM, 0, + NULL, &vm->page_directory); + if (r) + return r; + + r = amdgpu_vm_clear_bo(adev, vm->page_directory); + if (r) { + amdgpu_bo_unref(&vm->page_directory); + vm->page_directory = NULL; + return r; + } + + return 0; +} + +/** + * amdgpu_vm_fini - tear down a vm instance + * + * @adev: amdgpu_device pointer + * @vm: requested vm + * + * Tear down @vm (cayman+). + * Unbind the VM and remove all bos from the vm bo list + */ +void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) +{ + struct amdgpu_bo_va_mapping *mapping, *tmp; + int i; + + if (!RB_EMPTY_ROOT(&vm->va)) { + dev_err(adev->dev, "still active bo inside vm\n"); + } + rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { + list_del(&mapping->list); + interval_tree_remove(&mapping->it, &vm->va); + kfree(mapping); + } + list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { + list_del(&mapping->list); + kfree(mapping); + } + + for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) + amdgpu_bo_unref(&vm->page_tables[i].bo); + kfree(vm->page_tables); + + amdgpu_bo_unref(&vm->page_directory); + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + amdgpu_fence_unref(&vm->ids[i].flushed_updates); + amdgpu_fence_unref(&vm->ids[i].last_id_use); + } + + mutex_destroy(&vm->mutex); +} diff --git a/drivers/gpu/drm/amd/amdgpu/atom-bits.h b/drivers/gpu/drm/amd/amdgpu/atom-bits.h new file mode 100644 index 000000000000..e8fae5c77514 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atom-bits.h @@ -0,0 +1,48 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Stanislaw Skowronek + */ + +#ifndef ATOM_BITS_H +#define ATOM_BITS_H + +static inline uint8_t get_u8(void *bios, int ptr) +{ + return ((unsigned char *)bios)[ptr]; +} +#define U8(ptr) get_u8(ctx->ctx->bios, (ptr)) +#define CU8(ptr) get_u8(ctx->bios, (ptr)) +static inline uint16_t get_u16(void *bios, int ptr) +{ + return get_u8(bios ,ptr)|(((uint16_t)get_u8(bios, ptr+1))<<8); +} +#define U16(ptr) get_u16(ctx->ctx->bios, (ptr)) +#define CU16(ptr) get_u16(ctx->bios, (ptr)) +static inline uint32_t get_u32(void *bios, int ptr) +{ + return get_u16(bios, ptr)|(((uint32_t)get_u16(bios, ptr+2))<<16); +} +#define U32(ptr) get_u32(ctx->ctx->bios, (ptr)) +#define CU32(ptr) get_u32(ctx->bios, (ptr)) +#define CSTR(ptr) (((char *)(ctx->bios))+(ptr)) + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/atom-names.h b/drivers/gpu/drm/amd/amdgpu/atom-names.h new file mode 100644 index 000000000000..6f907a5ffa5f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atom-names.h @@ -0,0 +1,100 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Stanislaw Skowronek + */ + +#ifndef ATOM_NAMES_H +#define ATOM_NAMES_H + +#include "atom.h" + +#ifdef ATOM_DEBUG + +#define ATOM_OP_NAMES_CNT 123 +static char *atom_op_names[ATOM_OP_NAMES_CNT] = { +"RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL", +"MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC", +"OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG", +"SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL", +"SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS", +"SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG", +"MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS", +"DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS", +"ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB", +"SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT", +"SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS", +"COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH", +"JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL", +"JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS", +"TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC", +"CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB", +"CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS", +"MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG", +"RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB", +"XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL", +"SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC", +"DEBUG", "CTB_DS", +}; + +#define ATOM_TABLE_NAMES_CNT 74 +static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = { +"ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit", +"VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit", +"GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl", +"GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock", +"DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice", +"MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController", +"EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange", +"DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl", +"DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl", +"CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl", +"TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl", +"EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock", +"EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing", +"SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source", +"EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters", +"LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock", +"GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection", +"DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp", +"ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C", +"ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection", +"MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion", +"VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining", +"EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl", +"CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource", +"MemoryDeviceInit", "EnableYUV", +}; + +#define ATOM_IO_NAMES_CNT 5 +static char *atom_io_names[ATOM_IO_NAMES_CNT] = { +"MM", "PLL", "MC", "PCIE", "PCIE PORT", +}; + +#else + +#define ATOM_OP_NAMES_CNT 0 +#define ATOM_TABLE_NAMES_CNT 0 +#define ATOM_IO_NAMES_CNT 0 + +#endif + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/atom-types.h b/drivers/gpu/drm/amd/amdgpu/atom-types.h new file mode 100644 index 000000000000..1125b866cdb0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atom-types.h @@ -0,0 +1,42 @@ +/* + * Copyright 2008 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Dave Airlie + */ + +#ifndef ATOM_TYPES_H +#define ATOM_TYPES_H + +/* sync atom types to kernel types */ + +typedef uint16_t USHORT; +typedef uint32_t ULONG; +typedef uint8_t UCHAR; + + +#ifndef ATOM_BIG_ENDIAN +#if defined(__BIG_ENDIAN) +#define ATOM_BIG_ENDIAN 1 +#else +#define ATOM_BIG_ENDIAN 0 +#endif +#endif +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c new file mode 100644 index 000000000000..a0346a90d805 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -0,0 +1,1408 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Stanislaw Skowronek + */ + +#include +#include +#include +#include + +#define ATOM_DEBUG + +#include "atom.h" +#include "atom-names.h" +#include "atom-bits.h" +#include "amdgpu.h" + +#define ATOM_COND_ABOVE 0 +#define ATOM_COND_ABOVEOREQUAL 1 +#define ATOM_COND_ALWAYS 2 +#define ATOM_COND_BELOW 3 +#define ATOM_COND_BELOWOREQUAL 4 +#define ATOM_COND_EQUAL 5 +#define ATOM_COND_NOTEQUAL 6 + +#define ATOM_PORT_ATI 0 +#define ATOM_PORT_PCI 1 +#define ATOM_PORT_SYSIO 2 + +#define ATOM_UNIT_MICROSEC 0 +#define ATOM_UNIT_MILLISEC 1 + +#define PLL_INDEX 2 +#define PLL_DATA 3 + +typedef struct { + struct atom_context *ctx; + uint32_t *ps, *ws; + int ps_shift; + uint16_t start; + unsigned last_jump; + unsigned long last_jump_jiffies; + bool abort; +} atom_exec_context; + +int amdgpu_atom_debug = 0; +static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); +int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); + +static uint32_t atom_arg_mask[8] = + { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, +0xFF000000 }; +static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; + +static int atom_dst_to_src[8][4] = { + /* translate destination alignment field to the source alignment encoding */ + {0, 0, 0, 0}, + {1, 2, 3, 0}, + {1, 2, 3, 0}, + {1, 2, 3, 0}, + {4, 5, 6, 7}, + {4, 5, 6, 7}, + {4, 5, 6, 7}, + {4, 5, 6, 7}, +}; +static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 }; + +static int debug_depth = 0; +#ifdef ATOM_DEBUG +static void debug_print_spaces(int n) +{ + while (n--) + printk(" "); +} + +#define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0) +#define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0) +#else +#define DEBUG(...) do { } while (0) +#define SDEBUG(...) do { } while (0) +#endif + +static uint32_t atom_iio_execute(struct atom_context *ctx, int base, + uint32_t index, uint32_t data) +{ + uint32_t temp = 0xCDCDCDCD; + + while (1) + switch (CU8(base)) { + case ATOM_IIO_NOP: + base++; + break; + case ATOM_IIO_READ: + temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1)); + base += 3; + break; + case ATOM_IIO_WRITE: + ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); + base += 3; + break; + case ATOM_IIO_CLEAR: + temp &= + ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << + CU8(base + 2)); + base += 3; + break; + case ATOM_IIO_SET: + temp |= + (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + + 2); + base += 3; + break; + case ATOM_IIO_MOVE_INDEX: + temp &= + ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << + CU8(base + 3)); + temp |= + ((index >> CU8(base + 2)) & + (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + + 3); + base += 4; + break; + case ATOM_IIO_MOVE_DATA: + temp &= + ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << + CU8(base + 3)); + temp |= + ((data >> CU8(base + 2)) & + (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + + 3); + base += 4; + break; + case ATOM_IIO_MOVE_ATTR: + temp &= + ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << + CU8(base + 3)); + temp |= + ((ctx-> + io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - + CU8 + (base + + + 1)))) + << CU8(base + 3); + base += 4; + break; + case ATOM_IIO_END: + return temp; + default: + printk(KERN_INFO "Unknown IIO opcode.\n"); + return 0; + } +} + +static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, + int *ptr, uint32_t *saved, int print) +{ + uint32_t idx, val = 0xCDCDCDCD, align, arg; + struct atom_context *gctx = ctx->ctx; + arg = attr & 7; + align = (attr >> 3) & 7; + switch (arg) { + case ATOM_ARG_REG: + idx = U16(*ptr); + (*ptr) += 2; + if (print) + DEBUG("REG[0x%04X]", idx); + idx += gctx->reg_block; + switch (gctx->io_mode) { + case ATOM_IO_MM: + val = gctx->card->reg_read(gctx->card, idx); + break; + case ATOM_IO_PCI: + printk(KERN_INFO + "PCI registers are not implemented.\n"); + return 0; + case ATOM_IO_SYSIO: + printk(KERN_INFO + "SYSIO registers are not implemented.\n"); + return 0; + default: + if (!(gctx->io_mode & 0x80)) { + printk(KERN_INFO "Bad IO mode.\n"); + return 0; + } + if (!gctx->iio[gctx->io_mode & 0x7F]) { + printk(KERN_INFO + "Undefined indirect IO read method %d.\n", + gctx->io_mode & 0x7F); + return 0; + } + val = + atom_iio_execute(gctx, + gctx->iio[gctx->io_mode & 0x7F], + idx, 0); + } + break; + case ATOM_ARG_PS: + idx = U8(*ptr); + (*ptr)++; + /* get_unaligned_le32 avoids unaligned accesses from atombios + * tables, noticed on a DEC Alpha. */ + val = get_unaligned_le32((u32 *)&ctx->ps[idx]); + if (print) + DEBUG("PS[0x%02X,0x%04X]", idx, val); + break; + case ATOM_ARG_WS: + idx = U8(*ptr); + (*ptr)++; + if (print) + DEBUG("WS[0x%02X]", idx); + switch (idx) { + case ATOM_WS_QUOTIENT: + val = gctx->divmul[0]; + break; + case ATOM_WS_REMAINDER: + val = gctx->divmul[1]; + break; + case ATOM_WS_DATAPTR: + val = gctx->data_block; + break; + case ATOM_WS_SHIFT: + val = gctx->shift; + break; + case ATOM_WS_OR_MASK: + val = 1 << gctx->shift; + break; + case ATOM_WS_AND_MASK: + val = ~(1 << gctx->shift); + break; + case ATOM_WS_FB_WINDOW: + val = gctx->fb_base; + break; + case ATOM_WS_ATTRIBUTES: + val = gctx->io_attr; + break; + case ATOM_WS_REGPTR: + val = gctx->reg_block; + break; + default: + val = ctx->ws[idx]; + } + break; + case ATOM_ARG_ID: + idx = U16(*ptr); + (*ptr) += 2; + if (print) { + if (gctx->data_block) + DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); + else + DEBUG("ID[0x%04X]", idx); + } + val = U32(idx + gctx->data_block); + break; + case ATOM_ARG_FB: + idx = U8(*ptr); + (*ptr)++; + if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { + DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n", + gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); + val = 0; + } else + val = gctx->scratch[(gctx->fb_base / 4) + idx]; + if (print) + DEBUG("FB[0x%02X]", idx); + break; + case ATOM_ARG_IMM: + switch (align) { + case ATOM_SRC_DWORD: + val = U32(*ptr); + (*ptr) += 4; + if (print) + DEBUG("IMM 0x%08X\n", val); + return val; + case ATOM_SRC_WORD0: + case ATOM_SRC_WORD8: + case ATOM_SRC_WORD16: + val = U16(*ptr); + (*ptr) += 2; + if (print) + DEBUG("IMM 0x%04X\n", val); + return val; + case ATOM_SRC_BYTE0: + case ATOM_SRC_BYTE8: + case ATOM_SRC_BYTE16: + case ATOM_SRC_BYTE24: + val = U8(*ptr); + (*ptr)++; + if (print) + DEBUG("IMM 0x%02X\n", val); + return val; + } + return 0; + case ATOM_ARG_PLL: + idx = U8(*ptr); + (*ptr)++; + if (print) + DEBUG("PLL[0x%02X]", idx); + val = gctx->card->pll_read(gctx->card, idx); + break; + case ATOM_ARG_MC: + idx = U8(*ptr); + (*ptr)++; + if (print) + DEBUG("MC[0x%02X]", idx); + val = gctx->card->mc_read(gctx->card, idx); + break; + } + if (saved) + *saved = val; + val &= atom_arg_mask[align]; + val >>= atom_arg_shift[align]; + if (print) + switch (align) { + case ATOM_SRC_DWORD: + DEBUG(".[31:0] -> 0x%08X\n", val); + break; + case ATOM_SRC_WORD0: + DEBUG(".[15:0] -> 0x%04X\n", val); + break; + case ATOM_SRC_WORD8: + DEBUG(".[23:8] -> 0x%04X\n", val); + break; + case ATOM_SRC_WORD16: + DEBUG(".[31:16] -> 0x%04X\n", val); + break; + case ATOM_SRC_BYTE0: + DEBUG(".[7:0] -> 0x%02X\n", val); + break; + case ATOM_SRC_BYTE8: + DEBUG(".[15:8] -> 0x%02X\n", val); + break; + case ATOM_SRC_BYTE16: + DEBUG(".[23:16] -> 0x%02X\n", val); + break; + case ATOM_SRC_BYTE24: + DEBUG(".[31:24] -> 0x%02X\n", val); + break; + } + return val; +} + +static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr) +{ + uint32_t align = (attr >> 3) & 7, arg = attr & 7; + switch (arg) { + case ATOM_ARG_REG: + case ATOM_ARG_ID: + (*ptr) += 2; + break; + case ATOM_ARG_PLL: + case ATOM_ARG_MC: + case ATOM_ARG_PS: + case ATOM_ARG_WS: + case ATOM_ARG_FB: + (*ptr)++; + break; + case ATOM_ARG_IMM: + switch (align) { + case ATOM_SRC_DWORD: + (*ptr) += 4; + return; + case ATOM_SRC_WORD0: + case ATOM_SRC_WORD8: + case ATOM_SRC_WORD16: + (*ptr) += 2; + return; + case ATOM_SRC_BYTE0: + case ATOM_SRC_BYTE8: + case ATOM_SRC_BYTE16: + case ATOM_SRC_BYTE24: + (*ptr)++; + return; + } + return; + } +} + +static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) +{ + return atom_get_src_int(ctx, attr, ptr, NULL, 1); +} + +static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr) +{ + uint32_t val = 0xCDCDCDCD; + + switch (align) { + case ATOM_SRC_DWORD: + val = U32(*ptr); + (*ptr) += 4; + break; + case ATOM_SRC_WORD0: + case ATOM_SRC_WORD8: + case ATOM_SRC_WORD16: + val = U16(*ptr); + (*ptr) += 2; + break; + case ATOM_SRC_BYTE0: + case ATOM_SRC_BYTE8: + case ATOM_SRC_BYTE16: + case ATOM_SRC_BYTE24: + val = U8(*ptr); + (*ptr)++; + break; + } + return val; +} + +static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, + int *ptr, uint32_t *saved, int print) +{ + return atom_get_src_int(ctx, + arg | atom_dst_to_src[(attr >> 3) & + 7][(attr >> 6) & 3] << 3, + ptr, saved, print); +} + +static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr) +{ + atom_skip_src_int(ctx, + arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & + 3] << 3, ptr); +} + +static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, + int *ptr, uint32_t val, uint32_t saved) +{ + uint32_t align = + atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = + val, idx; + struct atom_context *gctx = ctx->ctx; + old_val &= atom_arg_mask[align] >> atom_arg_shift[align]; + val <<= atom_arg_shift[align]; + val &= atom_arg_mask[align]; + saved &= ~atom_arg_mask[align]; + val |= saved; + switch (arg) { + case ATOM_ARG_REG: + idx = U16(*ptr); + (*ptr) += 2; + DEBUG("REG[0x%04X]", idx); + idx += gctx->reg_block; + switch (gctx->io_mode) { + case ATOM_IO_MM: + if (idx == 0) + gctx->card->reg_write(gctx->card, idx, + val << 2); + else + gctx->card->reg_write(gctx->card, idx, val); + break; + case ATOM_IO_PCI: + printk(KERN_INFO + "PCI registers are not implemented.\n"); + return; + case ATOM_IO_SYSIO: + printk(KERN_INFO + "SYSIO registers are not implemented.\n"); + return; + default: + if (!(gctx->io_mode & 0x80)) { + printk(KERN_INFO "Bad IO mode.\n"); + return; + } + if (!gctx->iio[gctx->io_mode & 0xFF]) { + printk(KERN_INFO + "Undefined indirect IO write method %d.\n", + gctx->io_mode & 0x7F); + return; + } + atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], + idx, val); + } + break; + case ATOM_ARG_PS: + idx = U8(*ptr); + (*ptr)++; + DEBUG("PS[0x%02X]", idx); + ctx->ps[idx] = cpu_to_le32(val); + break; + case ATOM_ARG_WS: + idx = U8(*ptr); + (*ptr)++; + DEBUG("WS[0x%02X]", idx); + switch (idx) { + case ATOM_WS_QUOTIENT: + gctx->divmul[0] = val; + break; + case ATOM_WS_REMAINDER: + gctx->divmul[1] = val; + break; + case ATOM_WS_DATAPTR: + gctx->data_block = val; + break; + case ATOM_WS_SHIFT: + gctx->shift = val; + break; + case ATOM_WS_OR_MASK: + case ATOM_WS_AND_MASK: + break; + case ATOM_WS_FB_WINDOW: + gctx->fb_base = val; + break; + case ATOM_WS_ATTRIBUTES: + gctx->io_attr = val; + break; + case ATOM_WS_REGPTR: + gctx->reg_block = val; + break; + default: + ctx->ws[idx] = val; + } + break; + case ATOM_ARG_FB: + idx = U8(*ptr); + (*ptr)++; + if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { + DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n", + gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); + } else + gctx->scratch[(gctx->fb_base / 4) + idx] = val; + DEBUG("FB[0x%02X]", idx); + break; + case ATOM_ARG_PLL: + idx = U8(*ptr); + (*ptr)++; + DEBUG("PLL[0x%02X]", idx); + gctx->card->pll_write(gctx->card, idx, val); + break; + case ATOM_ARG_MC: + idx = U8(*ptr); + (*ptr)++; + DEBUG("MC[0x%02X]", idx); + gctx->card->mc_write(gctx->card, idx, val); + return; + } + switch (align) { + case ATOM_SRC_DWORD: + DEBUG(".[31:0] <- 0x%08X\n", old_val); + break; + case ATOM_SRC_WORD0: + DEBUG(".[15:0] <- 0x%04X\n", old_val); + break; + case ATOM_SRC_WORD8: + DEBUG(".[23:8] <- 0x%04X\n", old_val); + break; + case ATOM_SRC_WORD16: + DEBUG(".[31:16] <- 0x%04X\n", old_val); + break; + case ATOM_SRC_BYTE0: + DEBUG(".[7:0] <- 0x%02X\n", old_val); + break; + case ATOM_SRC_BYTE8: + DEBUG(".[15:8] <- 0x%02X\n", old_val); + break; + case ATOM_SRC_BYTE16: + DEBUG(".[23:16] <- 0x%02X\n", old_val); + break; + case ATOM_SRC_BYTE24: + DEBUG(".[31:24] <- 0x%02X\n", old_val); + break; + } +} + +static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t dst, src, saved; + int dptr = *ptr; + SDEBUG(" dst: "); + dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); + SDEBUG(" src: "); + src = atom_get_src(ctx, attr, ptr); + dst += src; + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, dst, saved); +} + +static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t dst, src, saved; + int dptr = *ptr; + SDEBUG(" dst: "); + dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); + SDEBUG(" src: "); + src = atom_get_src(ctx, attr, ptr); + dst &= src; + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, dst, saved); +} + +static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg) +{ + printk("ATOM BIOS beeped!\n"); +} + +static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg) +{ + int idx = U8((*ptr)++); + int r = 0; + + if (idx < ATOM_TABLE_NAMES_CNT) + SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]); + else + SDEBUG(" table: %d\n", idx); + if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) + r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); + if (r) { + ctx->abort = true; + } +} + +static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t saved; + int dptr = *ptr; + attr &= 0x38; + attr |= atom_def_dst[attr >> 3] << 6; + atom_get_dst(ctx, arg, attr, ptr, &saved, 0); + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, 0, saved); +} + +static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t dst, src; + SDEBUG(" src1: "); + dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); + SDEBUG(" src2: "); + src = atom_get_src(ctx, attr, ptr); + ctx->ctx->cs_equal = (dst == src); + ctx->ctx->cs_above = (dst > src); + SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE", + ctx->ctx->cs_above ? "GT" : "LE"); +} + +static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) +{ + unsigned count = U8((*ptr)++); + SDEBUG(" count: %d\n", count); + if (arg == ATOM_UNIT_MICROSEC) + udelay(count); + else if (!drm_can_sleep()) + mdelay(count); + else + msleep(count); +} + +static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t dst, src; + SDEBUG(" src1: "); + dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); + SDEBUG(" src2: "); + src = atom_get_src(ctx, attr, ptr); + if (src != 0) { + ctx->ctx->divmul[0] = dst / src; + ctx->ctx->divmul[1] = dst % src; + } else { + ctx->ctx->divmul[0] = 0; + ctx->ctx->divmul[1] = 0; + } +} + +static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg) +{ + /* functionally, a nop */ +} + +static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) +{ + int execute = 0, target = U16(*ptr); + unsigned long cjiffies; + + (*ptr) += 2; + switch (arg) { + case ATOM_COND_ABOVE: + execute = ctx->ctx->cs_above; + break; + case ATOM_COND_ABOVEOREQUAL: + execute = ctx->ctx->cs_above || ctx->ctx->cs_equal; + break; + case ATOM_COND_ALWAYS: + execute = 1; + break; + case ATOM_COND_BELOW: + execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal); + break; + case ATOM_COND_BELOWOREQUAL: + execute = !ctx->ctx->cs_above; + break; + case ATOM_COND_EQUAL: + execute = ctx->ctx->cs_equal; + break; + case ATOM_COND_NOTEQUAL: + execute = !ctx->ctx->cs_equal; + break; + } + if (arg != ATOM_COND_ALWAYS) + SDEBUG(" taken: %s\n", execute ? "yes" : "no"); + SDEBUG(" target: 0x%04X\n", target); + if (execute) { + if (ctx->last_jump == (ctx->start + target)) { + cjiffies = jiffies; + if (time_after(cjiffies, ctx->last_jump_jiffies)) { + cjiffies -= ctx->last_jump_jiffies; + if ((jiffies_to_msecs(cjiffies) > 5000)) { + DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n"); + ctx->abort = true; + } + } else { + /* jiffies wrap around we will just wait a little longer */ + ctx->last_jump_jiffies = jiffies; + } + } else { + ctx->last_jump = ctx->start + target; + ctx->last_jump_jiffies = jiffies; + } + *ptr = ctx->start + target; + } +} + +static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t dst, mask, src, saved; + int dptr = *ptr; + SDEBUG(" dst: "); + dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); + mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr); + SDEBUG(" mask: 0x%08x", mask); + SDEBUG(" src: "); + src = atom_get_src(ctx, attr, ptr); + dst &= mask; + dst |= src; + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, dst, saved); +} + +static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t src, saved; + int dptr = *ptr; + if (((attr >> 3) & 7) != ATOM_SRC_DWORD) + atom_get_dst(ctx, arg, attr, ptr, &saved, 0); + else { + atom_skip_dst(ctx, arg, attr, ptr); + saved = 0xCDCDCDCD; + } + SDEBUG(" src: "); + src = atom_get_src(ctx, attr, ptr); + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, src, saved); +} + +static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t dst, src; + SDEBUG(" src1: "); + dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); + SDEBUG(" src2: "); + src = atom_get_src(ctx, attr, ptr); + ctx->ctx->divmul[0] = dst * src; +} + +static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg) +{ + /* nothing */ +} + +static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t dst, src, saved; + int dptr = *ptr; + SDEBUG(" dst: "); + dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); + SDEBUG(" src: "); + src = atom_get_src(ctx, attr, ptr); + dst |= src; + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, dst, saved); +} + +static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t val = U8((*ptr)++); + SDEBUG("POST card output: 0x%02X\n", val); +} + +static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg) +{ + printk(KERN_INFO "unimplemented!\n"); +} + +static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg) +{ + printk(KERN_INFO "unimplemented!\n"); +} + +static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg) +{ + printk(KERN_INFO "unimplemented!\n"); +} + +static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg) +{ + int idx = U8(*ptr); + (*ptr)++; + SDEBUG(" block: %d\n", idx); + if (!idx) + ctx->ctx->data_block = 0; + else if (idx == 255) + ctx->ctx->data_block = ctx->start; + else + ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx); + SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block); +} + +static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + SDEBUG(" fb_base: "); + ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr); +} + +static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg) +{ + int port; + switch (arg) { + case ATOM_PORT_ATI: + port = U16(*ptr); + if (port < ATOM_IO_NAMES_CNT) + SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]); + else + SDEBUG(" port: %d\n", port); + if (!port) + ctx->ctx->io_mode = ATOM_IO_MM; + else + ctx->ctx->io_mode = ATOM_IO_IIO | port; + (*ptr) += 2; + break; + case ATOM_PORT_PCI: + ctx->ctx->io_mode = ATOM_IO_PCI; + (*ptr)++; + break; + case ATOM_PORT_SYSIO: + ctx->ctx->io_mode = ATOM_IO_SYSIO; + (*ptr)++; + break; + } +} + +static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg) +{ + ctx->ctx->reg_block = U16(*ptr); + (*ptr) += 2; + SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); +} + +static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++), shift; + uint32_t saved, dst; + int dptr = *ptr; + attr &= 0x38; + attr |= atom_def_dst[attr >> 3] << 6; + SDEBUG(" dst: "); + dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); + shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); + SDEBUG(" shift: %d\n", shift); + dst <<= shift; + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, dst, saved); +} + +static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++), shift; + uint32_t saved, dst; + int dptr = *ptr; + attr &= 0x38; + attr |= atom_def_dst[attr >> 3] << 6; + SDEBUG(" dst: "); + dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); + shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); + SDEBUG(" shift: %d\n", shift); + dst >>= shift; + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, dst, saved); +} + +static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++), shift; + uint32_t saved, dst; + int dptr = *ptr; + uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; + SDEBUG(" dst: "); + dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); + /* op needs to full dst value */ + dst = saved; + shift = atom_get_src(ctx, attr, ptr); + SDEBUG(" shift: %d\n", shift); + dst <<= shift; + dst &= atom_arg_mask[dst_align]; + dst >>= atom_arg_shift[dst_align]; + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, dst, saved); +} + +static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++), shift; + uint32_t saved, dst; + int dptr = *ptr; + uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; + SDEBUG(" dst: "); + dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); + /* op needs to full dst value */ + dst = saved; + shift = atom_get_src(ctx, attr, ptr); + SDEBUG(" shift: %d\n", shift); + dst >>= shift; + dst &= atom_arg_mask[dst_align]; + dst >>= atom_arg_shift[dst_align]; + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, dst, saved); +} + +static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t dst, src, saved; + int dptr = *ptr; + SDEBUG(" dst: "); + dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); + SDEBUG(" src: "); + src = atom_get_src(ctx, attr, ptr); + dst -= src; + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, dst, saved); +} + +static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t src, val, target; + SDEBUG(" switch: "); + src = atom_get_src(ctx, attr, ptr); + while (U16(*ptr) != ATOM_CASE_END) + if (U8(*ptr) == ATOM_CASE_MAGIC) { + (*ptr)++; + SDEBUG(" case: "); + val = + atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM, + ptr); + target = U16(*ptr); + if (val == src) { + SDEBUG(" target: %04X\n", target); + *ptr = ctx->start + target; + return; + } + (*ptr) += 2; + } else { + printk(KERN_INFO "Bad case.\n"); + return; + } + (*ptr) += 2; +} + +static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t dst, src; + SDEBUG(" src1: "); + dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); + SDEBUG(" src2: "); + src = atom_get_src(ctx, attr, ptr); + ctx->ctx->cs_equal = ((dst & src) == 0); + SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE"); +} + +static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg) +{ + uint8_t attr = U8((*ptr)++); + uint32_t dst, src, saved; + int dptr = *ptr; + SDEBUG(" dst: "); + dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); + SDEBUG(" src: "); + src = atom_get_src(ctx, attr, ptr); + dst ^= src; + SDEBUG(" dst: "); + atom_put_dst(ctx, arg, attr, &dptr, dst, saved); +} + +static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg) +{ + printk(KERN_INFO "unimplemented!\n"); +} + +static struct { + void (*func) (atom_exec_context *, int *, int); + int arg; +} opcode_table[ATOM_OP_CNT] = { + { + NULL, 0}, { + atom_op_move, ATOM_ARG_REG}, { + atom_op_move, ATOM_ARG_PS}, { + atom_op_move, ATOM_ARG_WS}, { + atom_op_move, ATOM_ARG_FB}, { + atom_op_move, ATOM_ARG_PLL}, { + atom_op_move, ATOM_ARG_MC}, { + atom_op_and, ATOM_ARG_REG}, { + atom_op_and, ATOM_ARG_PS}, { + atom_op_and, ATOM_ARG_WS}, { + atom_op_and, ATOM_ARG_FB}, { + atom_op_and, ATOM_ARG_PLL}, { + atom_op_and, ATOM_ARG_MC}, { + atom_op_or, ATOM_ARG_REG}, { + atom_op_or, ATOM_ARG_PS}, { + atom_op_or, ATOM_ARG_WS}, { + atom_op_or, ATOM_ARG_FB}, { + atom_op_or, ATOM_ARG_PLL}, { + atom_op_or, ATOM_ARG_MC}, { + atom_op_shift_left, ATOM_ARG_REG}, { + atom_op_shift_left, ATOM_ARG_PS}, { + atom_op_shift_left, ATOM_ARG_WS}, { + atom_op_shift_left, ATOM_ARG_FB}, { + atom_op_shift_left, ATOM_ARG_PLL}, { + atom_op_shift_left, ATOM_ARG_MC}, { + atom_op_shift_right, ATOM_ARG_REG}, { + atom_op_shift_right, ATOM_ARG_PS}, { + atom_op_shift_right, ATOM_ARG_WS}, { + atom_op_shift_right, ATOM_ARG_FB}, { + atom_op_shift_right, ATOM_ARG_PLL}, { + atom_op_shift_right, ATOM_ARG_MC}, { + atom_op_mul, ATOM_ARG_REG}, { + atom_op_mul, ATOM_ARG_PS}, { + atom_op_mul, ATOM_ARG_WS}, { + atom_op_mul, ATOM_ARG_FB}, { + atom_op_mul, ATOM_ARG_PLL}, { + atom_op_mul, ATOM_ARG_MC}, { + atom_op_div, ATOM_ARG_REG}, { + atom_op_div, ATOM_ARG_PS}, { + atom_op_div, ATOM_ARG_WS}, { + atom_op_div, ATOM_ARG_FB}, { + atom_op_div, ATOM_ARG_PLL}, { + atom_op_div, ATOM_ARG_MC}, { + atom_op_add, ATOM_ARG_REG}, { + atom_op_add, ATOM_ARG_PS}, { + atom_op_add, ATOM_ARG_WS}, { + atom_op_add, ATOM_ARG_FB}, { + atom_op_add, ATOM_ARG_PLL}, { + atom_op_add, ATOM_ARG_MC}, { + atom_op_sub, ATOM_ARG_REG}, { + atom_op_sub, ATOM_ARG_PS}, { + atom_op_sub, ATOM_ARG_WS}, { + atom_op_sub, ATOM_ARG_FB}, { + atom_op_sub, ATOM_ARG_PLL}, { + atom_op_sub, ATOM_ARG_MC}, { + atom_op_setport, ATOM_PORT_ATI}, { + atom_op_setport, ATOM_PORT_PCI}, { + atom_op_setport, ATOM_PORT_SYSIO}, { + atom_op_setregblock, 0}, { + atom_op_setfbbase, 0}, { + atom_op_compare, ATOM_ARG_REG}, { + atom_op_compare, ATOM_ARG_PS}, { + atom_op_compare, ATOM_ARG_WS}, { + atom_op_compare, ATOM_ARG_FB}, { + atom_op_compare, ATOM_ARG_PLL}, { + atom_op_compare, ATOM_ARG_MC}, { + atom_op_switch, 0}, { + atom_op_jump, ATOM_COND_ALWAYS}, { + atom_op_jump, ATOM_COND_EQUAL}, { + atom_op_jump, ATOM_COND_BELOW}, { + atom_op_jump, ATOM_COND_ABOVE}, { + atom_op_jump, ATOM_COND_BELOWOREQUAL}, { + atom_op_jump, ATOM_COND_ABOVEOREQUAL}, { + atom_op_jump, ATOM_COND_NOTEQUAL}, { + atom_op_test, ATOM_ARG_REG}, { + atom_op_test, ATOM_ARG_PS}, { + atom_op_test, ATOM_ARG_WS}, { + atom_op_test, ATOM_ARG_FB}, { + atom_op_test, ATOM_ARG_PLL}, { + atom_op_test, ATOM_ARG_MC}, { + atom_op_delay, ATOM_UNIT_MILLISEC}, { + atom_op_delay, ATOM_UNIT_MICROSEC}, { + atom_op_calltable, 0}, { + atom_op_repeat, 0}, { + atom_op_clear, ATOM_ARG_REG}, { + atom_op_clear, ATOM_ARG_PS}, { + atom_op_clear, ATOM_ARG_WS}, { + atom_op_clear, ATOM_ARG_FB}, { + atom_op_clear, ATOM_ARG_PLL}, { + atom_op_clear, ATOM_ARG_MC}, { + atom_op_nop, 0}, { + atom_op_eot, 0}, { + atom_op_mask, ATOM_ARG_REG}, { + atom_op_mask, ATOM_ARG_PS}, { + atom_op_mask, ATOM_ARG_WS}, { + atom_op_mask, ATOM_ARG_FB}, { + atom_op_mask, ATOM_ARG_PLL}, { + atom_op_mask, ATOM_ARG_MC}, { + atom_op_postcard, 0}, { + atom_op_beep, 0}, { + atom_op_savereg, 0}, { + atom_op_restorereg, 0}, { + atom_op_setdatablock, 0}, { + atom_op_xor, ATOM_ARG_REG}, { + atom_op_xor, ATOM_ARG_PS}, { + atom_op_xor, ATOM_ARG_WS}, { + atom_op_xor, ATOM_ARG_FB}, { + atom_op_xor, ATOM_ARG_PLL}, { + atom_op_xor, ATOM_ARG_MC}, { + atom_op_shl, ATOM_ARG_REG}, { + atom_op_shl, ATOM_ARG_PS}, { + atom_op_shl, ATOM_ARG_WS}, { + atom_op_shl, ATOM_ARG_FB}, { + atom_op_shl, ATOM_ARG_PLL}, { + atom_op_shl, ATOM_ARG_MC}, { + atom_op_shr, ATOM_ARG_REG}, { + atom_op_shr, ATOM_ARG_PS}, { + atom_op_shr, ATOM_ARG_WS}, { + atom_op_shr, ATOM_ARG_FB}, { + atom_op_shr, ATOM_ARG_PLL}, { + atom_op_shr, ATOM_ARG_MC}, { +atom_op_debug, 0},}; + +static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) +{ + int base = CU16(ctx->cmd_table + 4 + 2 * index); + int len, ws, ps, ptr; + unsigned char op; + atom_exec_context ectx; + int ret = 0; + + if (!base) + return -EINVAL; + + len = CU16(base + ATOM_CT_SIZE_PTR); + ws = CU8(base + ATOM_CT_WS_PTR); + ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; + ptr = base + ATOM_CT_CODE_PTR; + + SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); + + ectx.ctx = ctx; + ectx.ps_shift = ps / 4; + ectx.start = base; + ectx.ps = params; + ectx.abort = false; + ectx.last_jump = 0; + if (ws) + ectx.ws = kzalloc(4 * ws, GFP_KERNEL); + else + ectx.ws = NULL; + + debug_depth++; + while (1) { + op = CU8(ptr++); + if (op < ATOM_OP_NAMES_CNT) + SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1); + else + SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1); + if (ectx.abort) { + DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n", + base, len, ws, ps, ptr - 1); + ret = -EINVAL; + goto free; + } + + if (op < ATOM_OP_CNT && op > 0) + opcode_table[op].func(&ectx, &ptr, + opcode_table[op].arg); + else + break; + + if (op == ATOM_OP_EOT) + break; + } + debug_depth--; + SDEBUG("<<\n"); + +free: + if (ws) + kfree(ectx.ws); + return ret; +} + +int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) +{ + int r; + + mutex_lock(&ctx->mutex); + /* reset data block */ + ctx->data_block = 0; + /* reset reg block */ + ctx->reg_block = 0; + /* reset fb window */ + ctx->fb_base = 0; + /* reset io mode */ + ctx->io_mode = ATOM_IO_MM; + /* reset divmul */ + ctx->divmul[0] = 0; + ctx->divmul[1] = 0; + r = amdgpu_atom_execute_table_locked(ctx, index, params); + mutex_unlock(&ctx->mutex); + return r; +} + +static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; + +static void atom_index_iio(struct atom_context *ctx, int base) +{ + ctx->iio = kzalloc(2 * 256, GFP_KERNEL); + if (!ctx->iio) + return; + while (CU8(base) == ATOM_IIO_START) { + ctx->iio[CU8(base + 1)] = base + 2; + base += 2; + while (CU8(base) != ATOM_IIO_END) + base += atom_iio_len[CU8(base)]; + base += 3; + } +} + +struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) +{ + int base; + struct atom_context *ctx = + kzalloc(sizeof(struct atom_context), GFP_KERNEL); + char *str; + char name[512]; + int i; + + if (!ctx) + return NULL; + + ctx->card = card; + ctx->bios = bios; + + if (CU16(0) != ATOM_BIOS_MAGIC) { + printk(KERN_INFO "Invalid BIOS magic.\n"); + kfree(ctx); + return NULL; + } + if (strncmp + (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC, + strlen(ATOM_ATI_MAGIC))) { + printk(KERN_INFO "Invalid ATI magic.\n"); + kfree(ctx); + return NULL; + } + + base = CU16(ATOM_ROM_TABLE_PTR); + if (strncmp + (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, + strlen(ATOM_ROM_MAGIC))) { + printk(KERN_INFO "Invalid ATOM magic.\n"); + kfree(ctx); + return NULL; + } + + ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); + ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); + atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4); + if (!ctx->iio) { + amdgpu_atom_destroy(ctx); + return NULL; + } + + str = CSTR(CU16(base + ATOM_ROM_MSG_PTR)); + while (*str && ((*str == '\n') || (*str == '\r'))) + str++; + /* name string isn't always 0 terminated */ + for (i = 0; i < 511; i++) { + name[i] = str[i]; + if (name[i] < '.' || name[i] > 'z') { + name[i] = 0; + break; + } + } + printk(KERN_INFO "ATOM BIOS: %s\n", name); + + return ctx; +} + +int amdgpu_atom_asic_init(struct atom_context *ctx) +{ + int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR); + uint32_t ps[16]; + int ret; + + memset(ps, 0, 64); + + ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR)); + ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR)); + if (!ps[0] || !ps[1]) + return 1; + + if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) + return 1; + ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps); + if (ret) + return ret; + + memset(ps, 0, 64); + + return ret; +} + +void amdgpu_atom_destroy(struct atom_context *ctx) +{ + kfree(ctx->iio); + kfree(ctx); +} + +bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, + uint16_t * size, uint8_t * frev, uint8_t * crev, + uint16_t * data_start) +{ + int offset = index * 2 + 4; + int idx = CU16(ctx->data_table + offset); + u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4); + + if (!mdt[index]) + return false; + + if (size) + *size = CU16(idx); + if (frev) + *frev = CU8(idx + 2); + if (crev) + *crev = CU8(idx + 3); + *data_start = idx; + return true; +} + +bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev, + uint8_t * crev) +{ + int offset = index * 2 + 4; + int idx = CU16(ctx->cmd_table + offset); + u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4); + + if (!mct[index]) + return false; + + if (frev) + *frev = CU8(idx + 2); + if (crev) + *crev = CU8(idx + 3); + return true; +} + +int amdgpu_atom_allocate_fb_scratch(struct atom_context *ctx) +{ + int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware); + uint16_t data_offset; + int usage_bytes = 0; + struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage; + + if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { + firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset); + + DRM_DEBUG("atom firmware requested %08x %dkb\n", + le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware), + le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb)); + + usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024; + } + ctx->scratch_size_bytes = 0; + if (usage_bytes == 0) + usage_bytes = 20 * 1024; + /* allocate some scratch memory */ + ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); + if (!ctx->scratch) + return -ENOMEM; + ctx->scratch_size_bytes = usage_bytes; + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h new file mode 100644 index 000000000000..09d0f8230708 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atom.h @@ -0,0 +1,159 @@ +/* + * Copyright 2008 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: Stanislaw Skowronek + */ + +#ifndef ATOM_H +#define ATOM_H + +#include +#include + +#define ATOM_BIOS_MAGIC 0xAA55 +#define ATOM_ATI_MAGIC_PTR 0x30 +#define ATOM_ATI_MAGIC " 761295520" +#define ATOM_ROM_TABLE_PTR 0x48 + +#define ATOM_ROM_MAGIC "ATOM" +#define ATOM_ROM_MAGIC_PTR 4 + +#define ATOM_ROM_MSG_PTR 0x10 +#define ATOM_ROM_CMD_PTR 0x1E +#define ATOM_ROM_DATA_PTR 0x20 + +#define ATOM_CMD_INIT 0 +#define ATOM_CMD_SETSCLK 0x0A +#define ATOM_CMD_SETMCLK 0x0B +#define ATOM_CMD_SETPCLK 0x0C +#define ATOM_CMD_SPDFANCNTL 0x39 + +#define ATOM_DATA_FWI_PTR 0xC +#define ATOM_DATA_IIO_PTR 0x32 + +#define ATOM_FWI_DEFSCLK_PTR 8 +#define ATOM_FWI_DEFMCLK_PTR 0xC +#define ATOM_FWI_MAXSCLK_PTR 0x24 +#define ATOM_FWI_MAXMCLK_PTR 0x28 + +#define ATOM_CT_SIZE_PTR 0 +#define ATOM_CT_WS_PTR 4 +#define ATOM_CT_PS_PTR 5 +#define ATOM_CT_PS_MASK 0x7F +#define ATOM_CT_CODE_PTR 6 + +#define ATOM_OP_CNT 123 +#define ATOM_OP_EOT 91 + +#define ATOM_CASE_MAGIC 0x63 +#define ATOM_CASE_END 0x5A5A + +#define ATOM_ARG_REG 0 +#define ATOM_ARG_PS 1 +#define ATOM_ARG_WS 2 +#define ATOM_ARG_FB 3 +#define ATOM_ARG_ID 4 +#define ATOM_ARG_IMM 5 +#define ATOM_ARG_PLL 6 +#define ATOM_ARG_MC 7 + +#define ATOM_SRC_DWORD 0 +#define ATOM_SRC_WORD0 1 +#define ATOM_SRC_WORD8 2 +#define ATOM_SRC_WORD16 3 +#define ATOM_SRC_BYTE0 4 +#define ATOM_SRC_BYTE8 5 +#define ATOM_SRC_BYTE16 6 +#define ATOM_SRC_BYTE24 7 + +#define ATOM_WS_QUOTIENT 0x40 +#define ATOM_WS_REMAINDER 0x41 +#define ATOM_WS_DATAPTR 0x42 +#define ATOM_WS_SHIFT 0x43 +#define ATOM_WS_OR_MASK 0x44 +#define ATOM_WS_AND_MASK 0x45 +#define ATOM_WS_FB_WINDOW 0x46 +#define ATOM_WS_ATTRIBUTES 0x47 +#define ATOM_WS_REGPTR 0x48 + +#define ATOM_IIO_NOP 0 +#define ATOM_IIO_START 1 +#define ATOM_IIO_READ 2 +#define ATOM_IIO_WRITE 3 +#define ATOM_IIO_CLEAR 4 +#define ATOM_IIO_SET 5 +#define ATOM_IIO_MOVE_INDEX 6 +#define ATOM_IIO_MOVE_ATTR 7 +#define ATOM_IIO_MOVE_DATA 8 +#define ATOM_IIO_END 9 + +#define ATOM_IO_MM 0 +#define ATOM_IO_PCI 1 +#define ATOM_IO_SYSIO 2 +#define ATOM_IO_IIO 0x80 + +struct card_info { + struct drm_device *dev; + void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ + uint32_t (* reg_read)(struct card_info *, uint32_t); /* filled by driver */ + void (* ioreg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ + uint32_t (* ioreg_read)(struct card_info *, uint32_t); /* filled by driver */ + void (* mc_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ + uint32_t (* mc_read)(struct card_info *, uint32_t); /* filled by driver */ + void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ + uint32_t (* pll_read)(struct card_info *, uint32_t); /* filled by driver */ +}; + +struct atom_context { + struct card_info *card; + struct mutex mutex; + void *bios; + uint32_t cmd_table, data_table; + uint16_t *iio; + + uint16_t data_block; + uint32_t fb_base; + uint32_t divmul[2]; + uint16_t io_attr; + uint16_t reg_block; + uint8_t shift; + int cs_equal, cs_above; + int io_mode; + uint32_t *scratch; + int scratch_size_bytes; +}; + +extern int amdgpu_atom_debug; + +struct atom_context *amdgpu_atom_parse(struct card_info *, void *); +int amdgpu_atom_execute_table(struct atom_context *, int, uint32_t *); +int amdgpu_atom_asic_init(struct atom_context *); +void amdgpu_atom_destroy(struct atom_context *); +bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size, + uint8_t *frev, uint8_t *crev, uint16_t *data_start); +bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, + uint8_t *frev, uint8_t *crev); +int amdgpu_atom_allocate_fb_scratch(struct atom_context *ctx); +#include "atom-types.h" +#include "atombios.h" +#include "ObjectID.h" + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c new file mode 100644 index 000000000000..49aa35016653 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c @@ -0,0 +1,807 @@ +/* + * Copyright 2007-8 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + */ +#include +#include +#include +#include +#include "amdgpu.h" +#include "atom.h" +#include "atom-bits.h" +#include "atombios_encoders.h" +#include "amdgpu_atombios.h" +#include "amdgpu_pll.h" +#include "amdgpu_connectors.h" + +void amdgpu_atombios_crtc_overscan_setup(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + SET_CRTC_OVERSCAN_PS_ALLOCATION args; + int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); + int a1, a2; + + memset(&args, 0, sizeof(args)); + + args.ucCRTC = amdgpu_crtc->crtc_id; + + switch (amdgpu_crtc->rmx_type) { + case RMX_CENTER: + args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); + args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); + args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); + args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); + break; + case RMX_ASPECT: + a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; + a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; + + if (a1 > a2) { + args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); + args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); + } else if (a2 > a1) { + args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); + args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); + } + break; + case RMX_FULL: + default: + args.usOverscanRight = cpu_to_le16(amdgpu_crtc->h_border); + args.usOverscanLeft = cpu_to_le16(amdgpu_crtc->h_border); + args.usOverscanBottom = cpu_to_le16(amdgpu_crtc->v_border); + args.usOverscanTop = cpu_to_le16(amdgpu_crtc->v_border); + break; + } + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + ENABLE_SCALER_PS_ALLOCATION args; + int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); + + memset(&args, 0, sizeof(args)); + + args.ucScaler = amdgpu_crtc->crtc_id; + + switch (amdgpu_crtc->rmx_type) { + case RMX_FULL: + args.ucEnable = ATOM_SCALER_EXPANSION; + break; + case RMX_CENTER: + args.ucEnable = ATOM_SCALER_CENTER; + break; + case RMX_ASPECT: + args.ucEnable = ATOM_SCALER_EXPANSION; + break; + default: + args.ucEnable = ATOM_SCALER_DISABLE; + break; + } + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + int index = + GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); + ENABLE_CRTC_PS_ALLOCATION args; + + memset(&args, 0, sizeof(args)); + + args.ucCRTC = amdgpu_crtc->crtc_id; + args.ucEnable = lock; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); + ENABLE_CRTC_PS_ALLOCATION args; + + memset(&args, 0, sizeof(args)); + + args.ucCRTC = amdgpu_crtc->crtc_id; + args.ucEnable = state; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); + BLANK_CRTC_PS_ALLOCATION args; + + memset(&args, 0, sizeof(args)); + + args.ucCRTC = amdgpu_crtc->crtc_id; + args.ucBlanking = state; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); + ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; + + memset(&args, 0, sizeof(args)); + + args.ucDispPipeId = amdgpu_crtc->crtc_id; + args.ucEnable = state; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev) +{ + int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); + ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; + + memset(&args, 0, sizeof(args)); + + args.ucEnable = ATOM_INIT; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc, + struct drm_display_mode *mode) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + SET_CRTC_USING_DTD_TIMING_PARAMETERS args; + int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); + u16 misc = 0; + + memset(&args, 0, sizeof(args)); + args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2)); + args.usH_Blanking_Time = + cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (amdgpu_crtc->h_border * 2)); + args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (amdgpu_crtc->v_border * 2)); + args.usV_Blanking_Time = + cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (amdgpu_crtc->v_border * 2)); + args.usH_SyncOffset = + cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + amdgpu_crtc->h_border); + args.usH_SyncWidth = + cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); + args.usV_SyncOffset = + cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + amdgpu_crtc->v_border); + args.usV_SyncWidth = + cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); + args.ucH_Border = amdgpu_crtc->h_border; + args.ucV_Border = amdgpu_crtc->v_border; + + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + misc |= ATOM_VSYNC_POLARITY; + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + misc |= ATOM_HSYNC_POLARITY; + if (mode->flags & DRM_MODE_FLAG_CSYNC) + misc |= ATOM_COMPOSITESYNC; + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + misc |= ATOM_INTERLACE; + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) + misc |= ATOM_DOUBLE_CLOCK_MODE; + + args.susModeMiscInfo.usAccess = cpu_to_le16(misc); + args.ucCRTC = amdgpu_crtc->crtc_id; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +union atom_enable_ss { + ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; + ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; + ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; +}; + +static void amdgpu_atombios_crtc_program_ss(struct amdgpu_device *adev, + int enable, + int pll_id, + int crtc_id, + struct amdgpu_atom_ss *ss) +{ + unsigned i; + int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); + union atom_enable_ss args; + + if (enable) { + /* Don't mess with SS if percentage is 0 or external ss. + * SS is already disabled previously, and disabling it + * again can cause display problems if the pll is already + * programmed. + */ + if (ss->percentage == 0) + return; + if (ss->type & ATOM_EXTERNAL_SS_MASK) + return; + } else { + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (adev->mode_info.crtcs[i] && + adev->mode_info.crtcs[i]->enabled && + i != crtc_id && + pll_id == adev->mode_info.crtcs[i]->pll_id) { + /* one other crtc is using this pll don't turn + * off spread spectrum as it might turn off + * display on active crtc + */ + return; + } + } + } + + memset(&args, 0, sizeof(args)); + + args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); + args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; + switch (pll_id) { + case ATOM_PPLL1: + args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; + break; + case ATOM_PPLL2: + args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; + break; + case ATOM_DCPLL: + args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; + break; + case ATOM_PPLL_INVALID: + return; + } + args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); + args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); + args.v3.ucEnable = enable; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +union adjust_pixel_clock { + ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; + ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; +}; + +static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc, + struct drm_display_mode *mode) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct drm_encoder *encoder = amdgpu_crtc->encoder; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + u32 adjusted_clock = mode->clock; + int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(encoder); + u32 dp_clock = mode->clock; + u32 clock = mode->clock; + int bpc = amdgpu_crtc->bpc; + bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock); + union adjust_pixel_clock args; + u8 frev, crev; + int index; + + amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV; + + if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || + (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { + if (connector) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *dig_connector = + amdgpu_connector->con_priv; + + dp_clock = dig_connector->dp_clock; + } + } + + /* use recommended ref_div for ss */ + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + if (amdgpu_crtc->ss_enabled) { + if (amdgpu_crtc->ss.refdiv) { + amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV; + amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv; + amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; + } + } + } + + /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ + if (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) + adjusted_clock = mode->clock * 2; + if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + amdgpu_crtc->pll_flags |= AMDGPU_PLL_PREFER_CLOSEST_LOWER; + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) + amdgpu_crtc->pll_flags |= AMDGPU_PLL_IS_LCD; + + + /* adjust pll for deep color modes */ + if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { + switch (bpc) { + case 8: + default: + break; + case 10: + clock = (clock * 5) / 4; + break; + case 12: + clock = (clock * 3) / 2; + break; + case 16: + clock = clock * 2; + break; + } + } + + /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock + * accordingly based on the encoder/transmitter to work around + * special hw requirements. + */ + index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, + &crev)) + return adjusted_clock; + + memset(&args, 0, sizeof(args)); + + switch (frev) { + case 1: + switch (crev) { + case 1: + case 2: + args.v1.usPixelClock = cpu_to_le16(clock / 10); + args.v1.ucTransmitterID = amdgpu_encoder->encoder_id; + args.v1.ucEncodeMode = encoder_mode; + if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage) + args.v1.ucConfig |= + ADJUST_DISPLAY_CONFIG_SS_ENABLE; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, + index, (uint32_t *)&args); + adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; + break; + case 3: + args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); + args.v3.sInput.ucTransmitterID = amdgpu_encoder->encoder_id; + args.v3.sInput.ucEncodeMode = encoder_mode; + args.v3.sInput.ucDispPllConfig = 0; + if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage) + args.v3.sInput.ucDispPllConfig |= + DISPPLL_CONFIG_SS_ENABLE; + if (ENCODER_MODE_IS_DP(encoder_mode)) { + args.v3.sInput.ucDispPllConfig |= + DISPPLL_CONFIG_COHERENT_MODE; + /* 16200 or 27000 */ + args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); + } else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + if (dig->coherent_mode) + args.v3.sInput.ucDispPllConfig |= + DISPPLL_CONFIG_COHERENT_MODE; + if (is_duallink) + args.v3.sInput.ucDispPllConfig |= + DISPPLL_CONFIG_DUAL_LINK; + } + if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != + ENCODER_OBJECT_ID_NONE) + args.v3.sInput.ucExtTransmitterID = + amdgpu_encoder_get_dp_bridge_encoder_id(encoder); + else + args.v3.sInput.ucExtTransmitterID = 0; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, + index, (uint32_t *)&args); + adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; + if (args.v3.sOutput.ucRefDiv) { + amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; + amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV; + amdgpu_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; + } + if (args.v3.sOutput.ucPostDiv) { + amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; + amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_POST_DIV; + amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; + } + break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); + return adjusted_clock; + } + break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); + return adjusted_clock; + } + + return adjusted_clock; +} + +union set_pixel_clock { + SET_PIXEL_CLOCK_PS_ALLOCATION base; + PIXEL_CLOCK_PARAMETERS v1; + PIXEL_CLOCK_PARAMETERS_V2 v2; + PIXEL_CLOCK_PARAMETERS_V3 v3; + PIXEL_CLOCK_PARAMETERS_V5 v5; + PIXEL_CLOCK_PARAMETERS_V6 v6; +}; + +/* on DCE5, make sure the voltage is high enough to support the + * required disp clk. + */ +void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev, + u32 dispclk) +{ + u8 frev, crev; + int index; + union set_pixel_clock args; + + memset(&args, 0, sizeof(args)); + + index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, + &crev)) + return; + + switch (frev) { + case 1: + switch (crev) { + case 5: + /* if the default dcpll clock is specified, + * SetPixelClock provides the dividers + */ + args.v5.ucCRTC = ATOM_CRTC_INVALID; + args.v5.usPixelClock = cpu_to_le16(dispclk); + args.v5.ucPpll = ATOM_DCPLL; + break; + case 6: + /* if the default dcpll clock is specified, + * SetPixelClock provides the dividers + */ + args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); + args.v6.ucPpll = ATOM_EXT_PLL1; + break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); + return; + } + break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); + return; + } + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id) +{ + if (ENCODER_MODE_IS_DP(encoder_mode)) { + if (pll_id < ATOM_EXT_PLL1) + return true; + else + return false; + } else { + return true; + } +} + +void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, + u32 crtc_id, + int pll_id, + u32 encoder_mode, + u32 encoder_id, + u32 clock, + u32 ref_div, + u32 fb_div, + u32 frac_fb_div, + u32 post_div, + int bpc, + bool ss_enabled, + struct amdgpu_atom_ss *ss) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + u8 frev, crev; + int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); + union set_pixel_clock args; + + memset(&args, 0, sizeof(args)); + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, + &crev)) + return; + + switch (frev) { + case 1: + switch (crev) { + case 1: + if (clock == ATOM_DISABLE) + return; + args.v1.usPixelClock = cpu_to_le16(clock / 10); + args.v1.usRefDiv = cpu_to_le16(ref_div); + args.v1.usFbDiv = cpu_to_le16(fb_div); + args.v1.ucFracFbDiv = frac_fb_div; + args.v1.ucPostDiv = post_div; + args.v1.ucPpll = pll_id; + args.v1.ucCRTC = crtc_id; + args.v1.ucRefDivSrc = 1; + break; + case 2: + args.v2.usPixelClock = cpu_to_le16(clock / 10); + args.v2.usRefDiv = cpu_to_le16(ref_div); + args.v2.usFbDiv = cpu_to_le16(fb_div); + args.v2.ucFracFbDiv = frac_fb_div; + args.v2.ucPostDiv = post_div; + args.v2.ucPpll = pll_id; + args.v2.ucCRTC = crtc_id; + args.v2.ucRefDivSrc = 1; + break; + case 3: + args.v3.usPixelClock = cpu_to_le16(clock / 10); + args.v3.usRefDiv = cpu_to_le16(ref_div); + args.v3.usFbDiv = cpu_to_le16(fb_div); + args.v3.ucFracFbDiv = frac_fb_div; + args.v3.ucPostDiv = post_div; + args.v3.ucPpll = pll_id; + if (crtc_id == ATOM_CRTC2) + args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; + else + args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; + if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) + args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; + args.v3.ucTransmitterId = encoder_id; + args.v3.ucEncoderMode = encoder_mode; + break; + case 5: + args.v5.ucCRTC = crtc_id; + args.v5.usPixelClock = cpu_to_le16(clock / 10); + args.v5.ucRefDiv = ref_div; + args.v5.usFbDiv = cpu_to_le16(fb_div); + args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); + args.v5.ucPostDiv = post_div; + args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ + if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) && + (pll_id < ATOM_EXT_PLL1)) + args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; + if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { + switch (bpc) { + case 8: + default: + args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; + break; + case 10: + /* yes this is correct, the atom define is wrong */ + args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; + break; + case 12: + /* yes this is correct, the atom define is wrong */ + args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; + break; + } + } + args.v5.ucTransmitterID = encoder_id; + args.v5.ucEncoderMode = encoder_mode; + args.v5.ucPpll = pll_id; + break; + case 6: + args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); + args.v6.ucRefDiv = ref_div; + args.v6.usFbDiv = cpu_to_le16(fb_div); + args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); + args.v6.ucPostDiv = post_div; + args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ + if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) && + (pll_id < ATOM_EXT_PLL1) && + !is_pixel_clock_source_from_pll(encoder_mode, pll_id)) + args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; + if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { + switch (bpc) { + case 8: + default: + args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; + break; + case 10: + args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; + break; + case 12: + args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; + break; + case 16: + args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; + break; + } + } + args.v6.ucTransmitterID = encoder_id; + args.v6.ucEncoderMode = encoder_mode; + args.v6.ucPpll = pll_id; + break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); + return; + } + break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); + return; + } + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +int amdgpu_atombios_crtc_prepare_pll(struct drm_crtc *crtc, + struct drm_display_mode *mode) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = + to_amdgpu_encoder(amdgpu_crtc->encoder); + int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); + + amdgpu_crtc->bpc = 8; + amdgpu_crtc->ss_enabled = false; + + if ((amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || + (amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector = + amdgpu_get_connector_for_encoder(amdgpu_crtc->encoder); + struct amdgpu_connector *amdgpu_connector = + to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *dig_connector = + amdgpu_connector->con_priv; + int dp_clock; + + /* Assign mode clock for hdmi deep color max clock limit check */ + amdgpu_connector->pixelclock_for_modeset = mode->clock; + amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector); + + switch (encoder_mode) { + case ATOM_ENCODER_MODE_DP_MST: + case ATOM_ENCODER_MODE_DP: + /* DP/eDP */ + dp_clock = dig_connector->dp_clock / 10; + amdgpu_crtc->ss_enabled = + amdgpu_atombios_get_asic_ss_info(adev, &amdgpu_crtc->ss, + ASIC_INTERNAL_SS_ON_DP, + dp_clock); + break; + case ATOM_ENCODER_MODE_LVDS: + amdgpu_crtc->ss_enabled = + amdgpu_atombios_get_asic_ss_info(adev, + &amdgpu_crtc->ss, + dig->lcd_ss_id, + mode->clock / 10); + break; + case ATOM_ENCODER_MODE_DVI: + amdgpu_crtc->ss_enabled = + amdgpu_atombios_get_asic_ss_info(adev, + &amdgpu_crtc->ss, + ASIC_INTERNAL_SS_ON_TMDS, + mode->clock / 10); + break; + case ATOM_ENCODER_MODE_HDMI: + amdgpu_crtc->ss_enabled = + amdgpu_atombios_get_asic_ss_info(adev, + &amdgpu_crtc->ss, + ASIC_INTERNAL_SS_ON_HDMI, + mode->clock / 10); + break; + default: + break; + } + } + + /* adjust pixel clock as needed */ + amdgpu_crtc->adjusted_clock = amdgpu_atombios_crtc_adjust_pll(crtc, mode); + + return 0; +} + +void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = + to_amdgpu_encoder(amdgpu_crtc->encoder); + u32 pll_clock = mode->clock; + u32 clock = mode->clock; + u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; + struct amdgpu_pll *pll; + int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); + + /* pass the actual clock to amdgpu_atombios_crtc_program_pll for HDMI */ + if ((encoder_mode == ATOM_ENCODER_MODE_HDMI) && + (amdgpu_crtc->bpc > 8)) + clock = amdgpu_crtc->adjusted_clock; + + switch (amdgpu_crtc->pll_id) { + case ATOM_PPLL1: + pll = &adev->clock.ppll[0]; + break; + case ATOM_PPLL2: + pll = &adev->clock.ppll[1]; + break; + case ATOM_PPLL0: + case ATOM_PPLL_INVALID: + default: + pll = &adev->clock.ppll[2]; + break; + } + + /* update pll params */ + pll->flags = amdgpu_crtc->pll_flags; + pll->reference_div = amdgpu_crtc->pll_reference_div; + pll->post_div = amdgpu_crtc->pll_post_div; + + amdgpu_pll_compute(pll, amdgpu_crtc->adjusted_clock, &pll_clock, + &fb_div, &frac_fb_div, &ref_div, &post_div); + + amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, amdgpu_crtc->pll_id, + amdgpu_crtc->crtc_id, &amdgpu_crtc->ss); + + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, + encoder_mode, amdgpu_encoder->encoder_id, clock, + ref_div, fb_div, frac_fb_div, post_div, + amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); + + if (amdgpu_crtc->ss_enabled) { + /* calculate ss amount and step size */ + u32 step_size; + u32 amount = (((fb_div * 10) + frac_fb_div) * + (u32)amdgpu_crtc->ss.percentage) / + (100 * (u32)amdgpu_crtc->ss.percentage_divider); + amdgpu_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; + amdgpu_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & + ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; + if (amdgpu_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) + step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) / + (125 * 25 * pll->reference_freq / 100); + else + step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) / + (125 * 25 * pll->reference_freq / 100); + amdgpu_crtc->ss.step = step_size; + + amdgpu_atombios_crtc_program_ss(adev, ATOM_ENABLE, amdgpu_crtc->pll_id, + amdgpu_crtc->crtc_id, &amdgpu_crtc->ss); + } +} + diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h new file mode 100644 index 000000000000..c67083335b13 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h @@ -0,0 +1,58 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __ATOMBIOS_CRTC_H__ +#define __ATOMBIOS_CRTC_H__ + +void amdgpu_atombios_crtc_overscan_setup(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); +void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc); +void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock); +void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state); +void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state); +void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state); +void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev); +void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc, + struct drm_display_mode *mode); +void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev, + u32 dispclk); +void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, + u32 crtc_id, + int pll_id, + u32 encoder_mode, + u32 encoder_id, + u32 clock, + u32 ref_div, + u32 fb_div, + u32 frac_fb_div, + u32 post_div, + int bpc, + bool ss_enabled, + struct amdgpu_atom_ss *ss); +int amdgpu_atombios_crtc_prepare_pll(struct drm_crtc *crtc, + struct drm_display_mode *mode); +void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, + struct drm_display_mode *mode); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c new file mode 100644 index 000000000000..e00b8adde18d --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -0,0 +1,774 @@ +/* + * Copyright 2007-8 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + * Jerome Glisse + */ +#include +#include +#include "amdgpu.h" + +#include "atom.h" +#include "atom-bits.h" +#include "atombios_encoders.h" +#include "atombios_dp.h" +#include "amdgpu_connectors.h" +#include "amdgpu_atombios.h" +#include + +/* move these to drm_dp_helper.c/h */ +#define DP_LINK_CONFIGURATION_SIZE 9 +#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE + +static char *voltage_names[] = { + "0.4V", "0.6V", "0.8V", "1.2V" +}; +static char *pre_emph_names[] = { + "0dB", "3.5dB", "6dB", "9.5dB" +}; + +/***** amdgpu AUX functions *****/ + +union aux_channel_transaction { + PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; + PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; +}; + +static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan, + u8 *send, int send_bytes, + u8 *recv, int recv_size, + u8 delay, u8 *ack) +{ + struct drm_device *dev = chan->dev; + struct amdgpu_device *adev = dev->dev_private; + union aux_channel_transaction args; + int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); + unsigned char *base; + int recv_bytes; + int r = 0; + + memset(&args, 0, sizeof(args)); + + mutex_lock(&chan->mutex); + + base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1); + + amdgpu_atombios_copy_swap(base, send, send_bytes, true); + + args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); + args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4)); + args.v2.ucDataOutLen = 0; + args.v2.ucChannelID = chan->rec.i2c_id; + args.v2.ucDelay = delay / 10; + args.v2.ucHPD_ID = chan->rec.hpd; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + + *ack = args.v2.ucReplyStatus; + + /* timeout */ + if (args.v2.ucReplyStatus == 1) { + DRM_DEBUG_KMS("dp_aux_ch timeout\n"); + r = -ETIMEDOUT; + goto done; + } + + /* flags not zero */ + if (args.v2.ucReplyStatus == 2) { + DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); + r = -EIO; + goto done; + } + + /* error */ + if (args.v2.ucReplyStatus == 3) { + DRM_DEBUG_KMS("dp_aux_ch error\n"); + r = -EIO; + goto done; + } + + recv_bytes = args.v1.ucDataOutLen; + if (recv_bytes > recv_size) + recv_bytes = recv_size; + + if (recv && recv_size) + amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false); + + r = recv_bytes; +done: + mutex_unlock(&chan->mutex); + + return r; +} + +#define BARE_ADDRESS_SIZE 3 +#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) + +static ssize_t +amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) +{ + struct amdgpu_i2c_chan *chan = + container_of(aux, struct amdgpu_i2c_chan, aux); + int ret; + u8 tx_buf[20]; + size_t tx_size; + u8 ack, delay = 0; + + if (WARN_ON(msg->size > 16)) + return -E2BIG; + + tx_buf[0] = msg->address & 0xff; + tx_buf[1] = msg->address >> 8; + tx_buf[2] = msg->request << 4; + tx_buf[3] = msg->size ? (msg->size - 1) : 0; + + switch (msg->request & ~DP_AUX_I2C_MOT) { + case DP_AUX_NATIVE_WRITE: + case DP_AUX_I2C_WRITE: + /* tx_size needs to be 4 even for bare address packets since the atom + * table needs the info in tx_buf[3]. + */ + tx_size = HEADER_SIZE + msg->size; + if (msg->size == 0) + tx_buf[3] |= BARE_ADDRESS_SIZE << 4; + else + tx_buf[3] |= tx_size << 4; + memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); + ret = amdgpu_atombios_dp_process_aux_ch(chan, + tx_buf, tx_size, NULL, 0, delay, &ack); + if (ret >= 0) + /* Return payload size. */ + ret = msg->size; + break; + case DP_AUX_NATIVE_READ: + case DP_AUX_I2C_READ: + /* tx_size needs to be 4 even for bare address packets since the atom + * table needs the info in tx_buf[3]. + */ + tx_size = HEADER_SIZE; + if (msg->size == 0) + tx_buf[3] |= BARE_ADDRESS_SIZE << 4; + else + tx_buf[3] |= tx_size << 4; + ret = amdgpu_atombios_dp_process_aux_ch(chan, + tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); + break; + default: + ret = -EINVAL; + break; + } + + if (ret >= 0) + msg->reply = ack >> 4; + + return ret; +} + +void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector) +{ + int ret; + + amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd; + amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; + amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer; + ret = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); + if (!ret) + amdgpu_connector->ddc_bus->has_aux = true; + + WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret); +} + +/***** general DP utility functions *****/ + +#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 +#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 + +static void amdgpu_atombios_dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], + int lane_count, + u8 train_set[4]) +{ + u8 v = 0; + u8 p = 0; + int lane; + + for (lane = 0; lane < lane_count; lane++) { + u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); + u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); + + DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", + lane, + voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], + pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); + + if (this_v > v) + v = this_v; + if (this_p > p) + p = this_p; + } + + if (v >= DP_VOLTAGE_MAX) + v |= DP_TRAIN_MAX_SWING_REACHED; + + if (p >= DP_PRE_EMPHASIS_MAX) + p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; + + DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", + voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], + pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); + + for (lane = 0; lane < 4; lane++) + train_set[lane] = v | p; +} + +/* convert bits per color to bits per pixel */ +/* get bpc from the EDID */ +static int amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc) +{ + if (bpc == 0) + return 24; + else + return bpc * 3; +} + +/* get the max pix clock supported by the link rate and lane num */ +static int amdgpu_atombios_dp_get_max_dp_pix_clock(int link_rate, + int lane_num, + int bpp) +{ + return (link_rate * lane_num * 8) / bpp; +} + +/***** amdgpu specific DP functions *****/ + +/* First get the min lane# when low rate is used according to pixel clock + * (prefer low rate), second check max lane# supported by DP panel, + * if the max lane# < low rate lane# then use max lane# instead. + */ +static int amdgpu_atombios_dp_get_dp_lane_number(struct drm_connector *connector, + u8 dpcd[DP_DPCD_SIZE], + int pix_clock) +{ + int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector)); + int max_link_rate = drm_dp_max_link_rate(dpcd); + int max_lane_num = drm_dp_max_lane_count(dpcd); + int lane_num; + int max_dp_pix_clock; + + for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { + max_dp_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); + if (pix_clock <= max_dp_pix_clock) + break; + } + + return lane_num; +} + +static int amdgpu_atombios_dp_get_dp_link_clock(struct drm_connector *connector, + u8 dpcd[DP_DPCD_SIZE], + int pix_clock) +{ + int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector)); + int lane_num, max_pix_clock; + + if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) == + ENCODER_OBJECT_ID_NUTMEG) + return 270000; + + lane_num = amdgpu_atombios_dp_get_dp_lane_number(connector, dpcd, pix_clock); + max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(162000, lane_num, bpp); + if (pix_clock <= max_pix_clock) + return 162000; + max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(270000, lane_num, bpp); + if (pix_clock <= max_pix_clock) + return 270000; + if (amdgpu_connector_is_dp12_capable(connector)) { + max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(540000, lane_num, bpp); + if (pix_clock <= max_pix_clock) + return 540000; + } + + return drm_dp_max_link_rate(dpcd); +} + +static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev, + int action, int dp_clock, + u8 ucconfig, u8 lane_num) +{ + DP_ENCODER_SERVICE_PARAMETERS args; + int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); + + memset(&args, 0, sizeof(args)); + args.ucLinkClock = dp_clock / 10; + args.ucConfig = ucconfig; + args.ucAction = action; + args.ucLaneNum = lane_num; + args.ucStatus = 0; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + return args.ucStatus; +} + +u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector) +{ + struct drm_device *dev = amdgpu_connector->base.dev; + struct amdgpu_device *adev = dev->dev_private; + + return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, + amdgpu_connector->ddc_bus->rec.i2c_id, 0); +} + +static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector) +{ + struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; + u8 buf[3]; + + if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) + return; + + if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) + DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", + buf[0], buf[1], buf[2]); + + if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) + DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", + buf[0], buf[1], buf[2]); +} + +int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector) +{ + struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; + u8 msg[DP_DPCD_SIZE]; + int ret, i; + + ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, msg, + DP_DPCD_SIZE); + if (ret > 0) { + memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); + DRM_DEBUG_KMS("DPCD: "); + for (i = 0; i < DP_DPCD_SIZE; i++) + DRM_DEBUG_KMS("%02x ", msg[i]); + DRM_DEBUG_KMS("\n"); + + amdgpu_atombios_dp_probe_oui(amdgpu_connector); + + return 0; + } + dig_connector->dpcd[0] = 0; + return -EINVAL; +} + +int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *dig_connector; + int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; + u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector); + u8 tmp; + + if (!amdgpu_connector->con_priv) + return panel_mode; + + dig_connector = amdgpu_connector->con_priv; + + if (dp_bridge != ENCODER_OBJECT_ID_NONE) { + /* DP bridge chips */ + if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, + DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { + if (tmp & 1) + panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; + else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || + (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) + panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; + else + panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; + } + } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { + /* eDP */ + if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, + DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { + if (tmp & 1) + panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; + } + } + + return panel_mode; +} + +void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector, + const struct drm_display_mode *mode) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *dig_connector; + + if (!amdgpu_connector->con_priv) + return; + dig_connector = amdgpu_connector->con_priv; + + if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || + (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { + dig_connector->dp_clock = + amdgpu_atombios_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); + dig_connector->dp_lane_count = + amdgpu_atombios_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); + } +} + +int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *dig_connector; + int dp_clock; + + if (!amdgpu_connector->con_priv) + return MODE_CLOCK_HIGH; + dig_connector = amdgpu_connector->con_priv; + + dp_clock = + amdgpu_atombios_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); + + if ((dp_clock == 540000) && + (!amdgpu_connector_is_dp12_capable(connector))) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector) +{ + u8 link_status[DP_LINK_STATUS_SIZE]; + struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; + + if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status) + <= 0) + return false; + if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) + return false; + return true; +} + +void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector, + u8 power_state) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *dig_connector; + + if (!amdgpu_connector->con_priv) + return; + + dig_connector = amdgpu_connector->con_priv; + + /* power up/down the sink */ + if (dig_connector->dpcd[0] >= 0x11) { + drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux, + DP_SET_POWER, power_state); + usleep_range(1000, 2000); + } +} + +struct amdgpu_atombios_dp_link_train_info { + struct amdgpu_device *adev; + struct drm_encoder *encoder; + struct drm_connector *connector; + int dp_clock; + int dp_lane_count; + bool tp3_supported; + u8 dpcd[DP_RECEIVER_CAP_SIZE]; + u8 train_set[4]; + u8 link_status[DP_LINK_STATUS_SIZE]; + u8 tries; + struct drm_dp_aux *aux; +}; + +static void +amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info) +{ + /* set the initial vs/emph on the source */ + amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder, + ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, + 0, dp_info->train_set[0]); /* sets all lanes at once */ + + /* set the vs/emph on the sink */ + drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, + dp_info->train_set, dp_info->dp_lane_count); +} + +static void +amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp) +{ + int rtp = 0; + + /* set training pattern on the source */ + switch (tp) { + case DP_TRAINING_PATTERN_1: + rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; + break; + case DP_TRAINING_PATTERN_2: + rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; + break; + case DP_TRAINING_PATTERN_3: + rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; + break; + } + amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0); + + /* enable training pattern on the sink */ + drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); +} + +static int +amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u8 tmp; + + /* power up the sink */ + amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); + + /* possibly enable downspread on the sink */ + if (dp_info->dpcd[3] & 0x1) + drm_dp_dpcd_writeb(dp_info->aux, + DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); + else + drm_dp_dpcd_writeb(dp_info->aux, + DP_DOWNSPREAD_CTRL, 0); + + if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) + drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); + + /* set the lane count on the sink */ + tmp = dp_info->dp_lane_count; + if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) + tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; + drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); + + /* set the link rate on the sink */ + tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); + drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); + + /* start training on the source */ + amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, + ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); + + /* disable the training pattern on the sink */ + drm_dp_dpcd_writeb(dp_info->aux, + DP_TRAINING_PATTERN_SET, + DP_TRAINING_PATTERN_DISABLE); + + return 0; +} + +static int +amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info) +{ + udelay(400); + + /* disable the training pattern on the sink */ + drm_dp_dpcd_writeb(dp_info->aux, + DP_TRAINING_PATTERN_SET, + DP_TRAINING_PATTERN_DISABLE); + + /* disable the training pattern on the source */ + amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, + ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); + + return 0; +} + +static int +amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info) +{ + bool clock_recovery; + u8 voltage; + int i; + + amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); + memset(dp_info->train_set, 0, 4); + amdgpu_atombios_dp_update_vs_emph(dp_info); + + udelay(400); + + /* clock recovery loop */ + clock_recovery = false; + dp_info->tries = 0; + voltage = 0xff; + while (1) { + drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); + + if (drm_dp_dpcd_read_link_status(dp_info->aux, + dp_info->link_status) <= 0) { + DRM_ERROR("displayport link status failed\n"); + break; + } + + if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { + clock_recovery = true; + break; + } + + for (i = 0; i < dp_info->dp_lane_count; i++) { + if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) + break; + } + if (i == dp_info->dp_lane_count) { + DRM_ERROR("clock recovery reached max voltage\n"); + break; + } + + if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { + ++dp_info->tries; + if (dp_info->tries == 5) { + DRM_ERROR("clock recovery tried 5 times\n"); + break; + } + } else + dp_info->tries = 0; + + voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; + + /* Compute new train_set as requested by sink */ + amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, + dp_info->train_set); + + amdgpu_atombios_dp_update_vs_emph(dp_info); + } + if (!clock_recovery) { + DRM_ERROR("clock recovery failed\n"); + return -1; + } else { + DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", + dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, + (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT); + return 0; + } +} + +static int +amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info) +{ + bool channel_eq; + + if (dp_info->tp3_supported) + amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); + else + amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); + + /* channel equalization loop */ + dp_info->tries = 0; + channel_eq = false; + while (1) { + drm_dp_link_train_channel_eq_delay(dp_info->dpcd); + + if (drm_dp_dpcd_read_link_status(dp_info->aux, + dp_info->link_status) <= 0) { + DRM_ERROR("displayport link status failed\n"); + break; + } + + if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { + channel_eq = true; + break; + } + + /* Try 5 times */ + if (dp_info->tries > 5) { + DRM_ERROR("channel eq failed: 5 tries\n"); + break; + } + + /* Compute new train_set as requested by sink */ + amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, + dp_info->train_set); + + amdgpu_atombios_dp_update_vs_emph(dp_info); + dp_info->tries++; + } + + if (!channel_eq) { + DRM_ERROR("channel eq failed\n"); + return -1; + } else { + DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", + dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, + (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) + >> DP_TRAIN_PRE_EMPHASIS_SHIFT); + return 0; + } +} + +void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig; + struct amdgpu_connector *amdgpu_connector; + struct amdgpu_connector_atom_dig *dig_connector; + struct amdgpu_atombios_dp_link_train_info dp_info; + u8 tmp; + + if (!amdgpu_encoder->enc_priv) + return; + dig = amdgpu_encoder->enc_priv; + + amdgpu_connector = to_amdgpu_connector(connector); + if (!amdgpu_connector->con_priv) + return; + dig_connector = amdgpu_connector->con_priv; + + if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && + (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) + return; + + if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) + == 1) { + if (tmp & DP_TPS3_SUPPORTED) + dp_info.tp3_supported = true; + else + dp_info.tp3_supported = false; + } else { + dp_info.tp3_supported = false; + } + + memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); + dp_info.adev = adev; + dp_info.encoder = encoder; + dp_info.connector = connector; + dp_info.dp_lane_count = dig_connector->dp_lane_count; + dp_info.dp_clock = dig_connector->dp_clock; + dp_info.aux = &amdgpu_connector->ddc_bus->aux; + + if (amdgpu_atombios_dp_link_train_init(&dp_info)) + goto done; + if (amdgpu_atombios_dp_link_train_cr(&dp_info)) + goto done; + if (amdgpu_atombios_dp_link_train_ce(&dp_info)) + goto done; +done: + if (amdgpu_atombios_dp_link_train_finish(&dp_info)) + return; +} diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.h b/drivers/gpu/drm/amd/amdgpu/atombios_dp.h new file mode 100644 index 000000000000..f59d85eaddf0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.h @@ -0,0 +1,42 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __ATOMBIOS_DP_H__ +#define __ATOMBIOS_DP_H__ + +void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector); +u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector); +int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector); +int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder, + struct drm_connector *connector); +void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector, + const struct drm_display_mode *mode); +int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector, + struct drm_display_mode *mode); +bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector); +void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector, + u8 power_state); +void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder, + struct drm_connector *connector); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c new file mode 100644 index 000000000000..ae8caca61e04 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -0,0 +1,2066 @@ +/* + * Copyright 2007-11 Advanced Micro Devices, Inc. + * Copyright 2008 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Dave Airlie + * Alex Deucher + */ +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_connectors.h" +#include "atom.h" +#include "atombios_encoders.h" +#include "atombios_dp.h" +#include +#include "bif/bif_4_1_d.h" + +static u8 +amdgpu_atombios_encoder_get_backlight_level_from_reg(struct amdgpu_device *adev) +{ + u8 backlight_level; + u32 bios_2_scratch; + + bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); + + backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> + ATOM_S2_CURRENT_BL_LEVEL_SHIFT); + + return backlight_level; +} + +static void +amdgpu_atombios_encoder_set_backlight_level_to_reg(struct amdgpu_device *adev, + u8 backlight_level) +{ + u32 bios_2_scratch; + + bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); + + bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; + bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & + ATOM_S2_CURRENT_BL_LEVEL_MASK); + + WREG32(mmBIOS_SCRATCH_2, bios_2_scratch); +} + +u8 +amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder) +{ + struct drm_device *dev = amdgpu_encoder->base.dev; + struct amdgpu_device *adev = dev->dev_private; + + if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) + return 0; + + return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); +} + +void +amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder, + u8 level) +{ + struct drm_encoder *encoder = &amdgpu_encoder->base; + struct drm_device *dev = amdgpu_encoder->base.dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder_atom_dig *dig; + + if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) + return; + + if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && + amdgpu_encoder->enc_priv) { + dig = amdgpu_encoder->enc_priv; + dig->backlight_level = level; + amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, dig->backlight_level); + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + if (dig->backlight_level == 0) + amdgpu_atombios_encoder_setup_dig_transmitter(encoder, + ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); + else { + amdgpu_atombios_encoder_setup_dig_transmitter(encoder, + ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); + amdgpu_atombios_encoder_setup_dig_transmitter(encoder, + ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); + } + break; + default: + break; + } + } +} + +#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) + +static u8 amdgpu_atombios_encoder_backlight_level(struct backlight_device *bd) +{ + u8 level; + + /* Convert brightness to hardware level */ + if (bd->props.brightness < 0) + level = 0; + else if (bd->props.brightness > AMDGPU_MAX_BL_LEVEL) + level = AMDGPU_MAX_BL_LEVEL; + else + level = bd->props.brightness; + + return level; +} + +static int amdgpu_atombios_encoder_update_backlight_status(struct backlight_device *bd) +{ + struct amdgpu_backlight_privdata *pdata = bl_get_data(bd); + struct amdgpu_encoder *amdgpu_encoder = pdata->encoder; + + amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder, + amdgpu_atombios_encoder_backlight_level(bd)); + + return 0; +} + +static int +amdgpu_atombios_encoder_get_backlight_brightness(struct backlight_device *bd) +{ + struct amdgpu_backlight_privdata *pdata = bl_get_data(bd); + struct amdgpu_encoder *amdgpu_encoder = pdata->encoder; + struct drm_device *dev = amdgpu_encoder->base.dev; + struct amdgpu_device *adev = dev->dev_private; + + return amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); +} + +static const struct backlight_ops amdgpu_atombios_encoder_backlight_ops = { + .get_brightness = amdgpu_atombios_encoder_get_backlight_brightness, + .update_status = amdgpu_atombios_encoder_update_backlight_status, +}; + +void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encoder, + struct drm_connector *drm_connector) +{ + struct drm_device *dev = amdgpu_encoder->base.dev; + struct amdgpu_device *adev = dev->dev_private; + struct backlight_device *bd; + struct backlight_properties props; + struct amdgpu_backlight_privdata *pdata; + struct amdgpu_encoder_atom_dig *dig; + u8 backlight_level; + char bl_name[16]; + + /* Mac laptops with multiple GPUs use the gmux driver for backlight + * so don't register a backlight device + */ + if ((adev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && + (adev->pdev->device == 0x6741)) + return; + + if (!amdgpu_encoder->enc_priv) + return; + + if (!adev->is_atom_bios) + return; + + if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) + return; + + pdata = kmalloc(sizeof(struct amdgpu_backlight_privdata), GFP_KERNEL); + if (!pdata) { + DRM_ERROR("Memory allocation failed\n"); + goto error; + } + + memset(&props, 0, sizeof(props)); + props.max_brightness = AMDGPU_MAX_BL_LEVEL; + props.type = BACKLIGHT_RAW; + snprintf(bl_name, sizeof(bl_name), + "amdgpu_bl%d", dev->primary->index); + bd = backlight_device_register(bl_name, drm_connector->kdev, + pdata, &amdgpu_atombios_encoder_backlight_ops, &props); + if (IS_ERR(bd)) { + DRM_ERROR("Backlight registration failed\n"); + goto error; + } + + pdata->encoder = amdgpu_encoder; + + backlight_level = amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); + + dig = amdgpu_encoder->enc_priv; + dig->bl_dev = bd; + + bd->props.brightness = amdgpu_atombios_encoder_get_backlight_brightness(bd); + bd->props.power = FB_BLANK_UNBLANK; + backlight_update_status(bd); + + DRM_INFO("amdgpu atom DIG backlight initialized\n"); + + return; + +error: + kfree(pdata); + return; +} + +void +amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *amdgpu_encoder) +{ + struct drm_device *dev = amdgpu_encoder->base.dev; + struct amdgpu_device *adev = dev->dev_private; + struct backlight_device *bd = NULL; + struct amdgpu_encoder_atom_dig *dig; + + if (!amdgpu_encoder->enc_priv) + return; + + if (!adev->is_atom_bios) + return; + + if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) + return; + + dig = amdgpu_encoder->enc_priv; + bd = dig->bl_dev; + dig->bl_dev = NULL; + + if (bd) { + struct amdgpu_legacy_backlight_privdata *pdata; + + pdata = bl_get_data(bd); + backlight_device_unregister(bd); + kfree(pdata); + + DRM_INFO("amdgpu atom LVDS backlight unloaded\n"); + } +} + +#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ + +void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *encoder) +{ +} + +void amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *encoder) +{ +} + +#endif + +bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + return true; + default: + return false; + } +} + +bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + + /* set the active encoder to connector routing */ + amdgpu_encoder_set_active_device(encoder); + drm_mode_set_crtcinfo(adjusted_mode, 0); + + /* hw bug */ + if ((mode->flags & DRM_MODE_FLAG_INTERLACE) + && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) + adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; + + /* get the native mode for scaling */ + if (amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) + amdgpu_panel_mode_fixup(encoder, adjusted_mode); + else if (amdgpu_encoder->rmx_type != RMX_OFF) + amdgpu_panel_mode_fixup(encoder, adjusted_mode); + + if ((amdgpu_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || + (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + amdgpu_atombios_dp_set_link_config(connector, adjusted_mode); + } + + return true; +} + +static void +amdgpu_atombios_encoder_setup_dac(struct drm_encoder *encoder, int action) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + DAC_ENCODER_CONTROL_PS_ALLOCATION args; + int index = 0; + + memset(&args, 0, sizeof(args)); + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_DAC1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); + break; + case ENCODER_OBJECT_ID_INTERNAL_DAC2: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); + break; + } + + args.ucAction = action; + args.ucDacStandard = ATOM_DAC1_PS2; + args.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + +} + +static u8 amdgpu_atombios_encoder_get_bpc(struct drm_encoder *encoder) +{ + int bpc = 8; + + if (encoder->crtc) { + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + bpc = amdgpu_crtc->bpc; + } + + switch (bpc) { + case 0: + return PANEL_BPC_UNDEFINE; + case 6: + return PANEL_6BIT_PER_COLOR; + case 8: + default: + return PANEL_8BIT_PER_COLOR; + case 10: + return PANEL_10BIT_PER_COLOR; + case 12: + return PANEL_12BIT_PER_COLOR; + case 16: + return PANEL_16BIT_PER_COLOR; + } +} + +union dvo_encoder_control { + ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; + DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; + DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; + DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; +}; + +static void +amdgpu_atombios_encoder_setup_dvo(struct drm_encoder *encoder, int action) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + union dvo_encoder_control args; + int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); + uint8_t frev, crev; + + memset(&args, 0, sizeof(args)); + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) + return; + + switch (frev) { + case 1: + switch (crev) { + case 1: + /* R4xx, R5xx */ + args.ext_tmds.sXTmdsEncoder.ucEnable = action; + + if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; + + args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; + break; + case 2: + /* RS600/690/740 */ + args.dvo.sDVOEncoder.ucAction = action; + args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + /* DFP1, CRT1, TV1 depending on the type of port */ + args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; + + if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; + break; + case 3: + /* R6xx */ + args.dvo_v3.ucAction = action; + args.dvo_v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + args.dvo_v3.ucDVOConfig = 0; /* XXX */ + break; + case 4: + /* DCE8 */ + args.dvo_v4.ucAction = action; + args.dvo_v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + args.dvo_v4.ucDVOConfig = 0; /* XXX */ + args.dvo_v4.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder); + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + break; + } + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + break; + } + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector; + struct amdgpu_connector_atom_dig *dig_connector; + + /* dp bridges are always DP */ + if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) + return ATOM_ENCODER_MODE_DP; + + /* DVO is always DVO */ + if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || + (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) + return ATOM_ENCODER_MODE_DVO; + + connector = amdgpu_get_connector_for_encoder(encoder); + /* if we don't have an active device yet, just use one of + * the connectors tied to the encoder. + */ + if (!connector) + connector = amdgpu_get_connector_for_encoder_init(encoder); + amdgpu_connector = to_amdgpu_connector(connector); + + switch (connector->connector_type) { + case DRM_MODE_CONNECTOR_DVII: + case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ + if (amdgpu_audio != 0) { + if (amdgpu_connector->use_digital && + (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE)) + return ATOM_ENCODER_MODE_HDMI; + else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && + (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) + return ATOM_ENCODER_MODE_HDMI; + else if (amdgpu_connector->use_digital) + return ATOM_ENCODER_MODE_DVI; + else + return ATOM_ENCODER_MODE_CRT; + } else if (amdgpu_connector->use_digital) { + return ATOM_ENCODER_MODE_DVI; + } else { + return ATOM_ENCODER_MODE_CRT; + } + break; + case DRM_MODE_CONNECTOR_DVID: + case DRM_MODE_CONNECTOR_HDMIA: + default: + if (amdgpu_audio != 0) { + if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE) + return ATOM_ENCODER_MODE_HDMI; + else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && + (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) + return ATOM_ENCODER_MODE_HDMI; + else + return ATOM_ENCODER_MODE_DVI; + } else { + return ATOM_ENCODER_MODE_DVI; + } + break; + case DRM_MODE_CONNECTOR_LVDS: + return ATOM_ENCODER_MODE_LVDS; + break; + case DRM_MODE_CONNECTOR_DisplayPort: + dig_connector = amdgpu_connector->con_priv; + if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || + (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { + return ATOM_ENCODER_MODE_DP; + } else if (amdgpu_audio != 0) { + if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE) + return ATOM_ENCODER_MODE_HDMI; + else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && + (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) + return ATOM_ENCODER_MODE_HDMI; + else + return ATOM_ENCODER_MODE_DVI; + } else { + return ATOM_ENCODER_MODE_DVI; + } + break; + case DRM_MODE_CONNECTOR_eDP: + return ATOM_ENCODER_MODE_DP; + case DRM_MODE_CONNECTOR_DVIA: + case DRM_MODE_CONNECTOR_VGA: + return ATOM_ENCODER_MODE_CRT; + break; + case DRM_MODE_CONNECTOR_Composite: + case DRM_MODE_CONNECTOR_SVIDEO: + case DRM_MODE_CONNECTOR_9PinDIN: + /* fix me */ + return ATOM_ENCODER_MODE_TV; + /*return ATOM_ENCODER_MODE_CV;*/ + break; + } +} + +/* + * DIG Encoder/Transmitter Setup + * + * DCE 6.0 + * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). + * Supports up to 6 digital outputs + * - 6 DIG encoder blocks. + * - DIG to PHY mapping is hardcoded + * DIG1 drives UNIPHY0 link A, A+B + * DIG2 drives UNIPHY0 link B + * DIG3 drives UNIPHY1 link A, A+B + * DIG4 drives UNIPHY1 link B + * DIG5 drives UNIPHY2 link A, A+B + * DIG6 drives UNIPHY2 link B + * + * Routing + * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) + * Examples: + * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI + * crtc1 -> dig1 -> UNIPHY0 link B -> DP + * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS + * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI + */ + +union dig_encoder_control { + DIG_ENCODER_CONTROL_PS_ALLOCATION v1; + DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; + DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; + DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; +}; + +void +amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder, + int action, int panel_mode) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + union dig_encoder_control args; + int index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); + uint8_t frev, crev; + int dp_clock = 0; + int dp_lane_count = 0; + int hpd_id = AMDGPU_HPD_NONE; + + if (connector) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *dig_connector = + amdgpu_connector->con_priv; + + dp_clock = dig_connector->dp_clock; + dp_lane_count = dig_connector->dp_lane_count; + hpd_id = amdgpu_connector->hpd.hpd; + } + + /* no dig encoder assigned */ + if (dig->dig_encoder == -1) + return; + + memset(&args, 0, sizeof(args)); + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) + return; + + switch (frev) { + case 1: + switch (crev) { + case 1: + args.v1.ucAction = action; + args.v1.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) + args.v3.ucPanelMode = panel_mode; + else + args.v1.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); + + if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) + args.v1.ucLaneNum = dp_lane_count; + else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v1.ucLaneNum = 8; + else + args.v1.ucLaneNum = 4; + + if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) + args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; + break; + } + if (dig->linkb) + args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; + else + args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; + break; + case 2: + case 3: + args.v3.ucAction = action; + args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) + args.v3.ucPanelMode = panel_mode; + else + args.v3.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); + + if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) + args.v3.ucLaneNum = dp_lane_count; + else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v3.ucLaneNum = 8; + else + args.v3.ucLaneNum = 4; + + if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) + args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; + args.v3.acConfig.ucDigSel = dig->dig_encoder; + args.v3.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder); + break; + case 4: + args.v4.ucAction = action; + args.v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) + args.v4.ucPanelMode = panel_mode; + else + args.v4.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); + + if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) + args.v4.ucLaneNum = dp_lane_count; + else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v4.ucLaneNum = 8; + else + args.v4.ucLaneNum = 4; + + if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { + if (dp_clock == 540000) + args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; + else if (dp_clock == 324000) + args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; + else if (dp_clock == 270000) + args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; + else + args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; + } + args.v4.acConfig.ucDigSel = dig->dig_encoder; + args.v4.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder); + if (hpd_id == AMDGPU_HPD_NONE) + args.v4.ucHPD_ID = 0; + else + args.v4.ucHPD_ID = hpd_id + 1; + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + break; + } + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + break; + } + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + +} + +union dig_transmitter_control { + DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; + DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; + DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; + DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; + DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; +}; + +void +amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int action, + uint8_t lane_num, uint8_t lane_set) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + union dig_transmitter_control args; + int index = 0; + uint8_t frev, crev; + bool is_dp = false; + int pll_id = 0; + int dp_clock = 0; + int dp_lane_count = 0; + int connector_object_id = 0; + int igp_lane_info = 0; + int dig_encoder = dig->dig_encoder; + int hpd_id = AMDGPU_HPD_NONE; + + if (action == ATOM_TRANSMITTER_ACTION_INIT) { + connector = amdgpu_get_connector_for_encoder_init(encoder); + /* just needed to avoid bailing in the encoder check. the encoder + * isn't used for init + */ + dig_encoder = 0; + } else + connector = amdgpu_get_connector_for_encoder(encoder); + + if (connector) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *dig_connector = + amdgpu_connector->con_priv; + + hpd_id = amdgpu_connector->hpd.hpd; + dp_clock = dig_connector->dp_clock; + dp_lane_count = dig_connector->dp_lane_count; + connector_object_id = + (amdgpu_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; + } + + if (encoder->crtc) { + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + pll_id = amdgpu_crtc->pll_id; + } + + /* no dig encoder assigned */ + if (dig_encoder == -1) + return; + + if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder))) + is_dp = true; + + memset(&args, 0, sizeof(args)); + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: + index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); + break; + } + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) + return; + + switch (frev) { + case 1: + switch (crev) { + case 1: + args.v1.ucAction = action; + if (action == ATOM_TRANSMITTER_ACTION_INIT) { + args.v1.usInitInfo = cpu_to_le16(connector_object_id); + } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { + args.v1.asMode.ucLaneSel = lane_num; + args.v1.asMode.ucLaneSet = lane_set; + } else { + if (is_dp) + args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); + else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v1.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10); + else + args.v1.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + } + + args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; + + if (dig_encoder) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; + else + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; + + if ((adev->flags & AMDGPU_IS_APU) && + (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { + if (is_dp || + !amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) { + if (igp_lane_info & 0x1) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; + else if (igp_lane_info & 0x2) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; + else if (igp_lane_info & 0x4) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; + else if (igp_lane_info & 0x8) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; + } else { + if (igp_lane_info & 0x3) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; + else if (igp_lane_info & 0xc) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; + } + } + + if (dig->linkb) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; + else + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; + + if (is_dp) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; + else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { + if (dig->coherent_mode) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; + if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; + } + break; + case 2: + args.v2.ucAction = action; + if (action == ATOM_TRANSMITTER_ACTION_INIT) { + args.v2.usInitInfo = cpu_to_le16(connector_object_id); + } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { + args.v2.asMode.ucLaneSel = lane_num; + args.v2.asMode.ucLaneSet = lane_set; + } else { + if (is_dp) + args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); + else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v2.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10); + else + args.v2.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + } + + args.v2.acConfig.ucEncoderSel = dig_encoder; + if (dig->linkb) + args.v2.acConfig.ucLinkSel = 1; + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + args.v2.acConfig.ucTransmitterSel = 0; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + args.v2.acConfig.ucTransmitterSel = 1; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + args.v2.acConfig.ucTransmitterSel = 2; + break; + } + + if (is_dp) { + args.v2.acConfig.fCoherentMode = 1; + args.v2.acConfig.fDPConnector = 1; + } else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { + if (dig->coherent_mode) + args.v2.acConfig.fCoherentMode = 1; + if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v2.acConfig.fDualLinkConnector = 1; + } + break; + case 3: + args.v3.ucAction = action; + if (action == ATOM_TRANSMITTER_ACTION_INIT) { + args.v3.usInitInfo = cpu_to_le16(connector_object_id); + } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { + args.v3.asMode.ucLaneSel = lane_num; + args.v3.asMode.ucLaneSet = lane_set; + } else { + if (is_dp) + args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); + else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v3.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10); + else + args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + } + + if (is_dp) + args.v3.ucLaneNum = dp_lane_count; + else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v3.ucLaneNum = 8; + else + args.v3.ucLaneNum = 4; + + if (dig->linkb) + args.v3.acConfig.ucLinkSel = 1; + if (dig_encoder & 1) + args.v3.acConfig.ucEncoderSel = 1; + + /* Select the PLL for the PHY + * DP PHY should be clocked from external src if there is + * one. + */ + /* On DCE4, if there is an external clock, it generates the DP ref clock */ + if (is_dp && adev->clock.dp_extclk) + args.v3.acConfig.ucRefClkSource = 2; /* external src */ + else + args.v3.acConfig.ucRefClkSource = pll_id; + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + args.v3.acConfig.ucTransmitterSel = 0; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + args.v3.acConfig.ucTransmitterSel = 1; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + args.v3.acConfig.ucTransmitterSel = 2; + break; + } + + if (is_dp) + args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ + else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { + if (dig->coherent_mode) + args.v3.acConfig.fCoherentMode = 1; + if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v3.acConfig.fDualLinkConnector = 1; + } + break; + case 4: + args.v4.ucAction = action; + if (action == ATOM_TRANSMITTER_ACTION_INIT) { + args.v4.usInitInfo = cpu_to_le16(connector_object_id); + } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { + args.v4.asMode.ucLaneSel = lane_num; + args.v4.asMode.ucLaneSet = lane_set; + } else { + if (is_dp) + args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); + else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v4.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10); + else + args.v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + } + + if (is_dp) + args.v4.ucLaneNum = dp_lane_count; + else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v4.ucLaneNum = 8; + else + args.v4.ucLaneNum = 4; + + if (dig->linkb) + args.v4.acConfig.ucLinkSel = 1; + if (dig_encoder & 1) + args.v4.acConfig.ucEncoderSel = 1; + + /* Select the PLL for the PHY + * DP PHY should be clocked from external src if there is + * one. + */ + /* On DCE5 DCPLL usually generates the DP ref clock */ + if (is_dp) { + if (adev->clock.dp_extclk) + args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; + else + args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; + } else + args.v4.acConfig.ucRefClkSource = pll_id; + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + args.v4.acConfig.ucTransmitterSel = 0; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + args.v4.acConfig.ucTransmitterSel = 1; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + args.v4.acConfig.ucTransmitterSel = 2; + break; + } + + if (is_dp) + args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ + else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { + if (dig->coherent_mode) + args.v4.acConfig.fCoherentMode = 1; + if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v4.acConfig.fDualLinkConnector = 1; + } + break; + case 5: + args.v5.ucAction = action; + if (is_dp) + args.v5.usSymClock = cpu_to_le16(dp_clock / 10); + else + args.v5.usSymClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + if (dig->linkb) + args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; + else + args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + if (dig->linkb) + args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; + else + args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + if (dig->linkb) + args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; + else + args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; + break; + } + if (is_dp) + args.v5.ucLaneNum = dp_lane_count; + else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v5.ucLaneNum = 8; + else + args.v5.ucLaneNum = 4; + args.v5.ucConnObjId = connector_object_id; + args.v5.ucDigMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); + + if (is_dp && adev->clock.dp_extclk) + args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; + else + args.v5.asConfig.ucPhyClkSrcId = pll_id; + + if (is_dp) + args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ + else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { + if (dig->coherent_mode) + args.v5.asConfig.ucCoherentMode = 1; + } + if (hpd_id == AMDGPU_HPD_NONE) + args.v5.asConfig.ucHPDSel = 0; + else + args.v5.asConfig.ucHPDSel = hpd_id + 1; + args.v5.ucDigEncoderSel = 1 << dig_encoder; + args.v5.ucDPLaneSet = lane_set; + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + break; + } + break; + default: + DRM_ERROR("Unknown table version %d, %d\n", frev, crev); + break; + } + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +bool +amdgpu_atombios_encoder_set_edp_panel_power(struct drm_connector *connector, + int action) +{ + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct drm_device *dev = amdgpu_connector->base.dev; + struct amdgpu_device *adev = dev->dev_private; + union dig_transmitter_control args; + int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); + uint8_t frev, crev; + + if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) + goto done; + + if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && + (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) + goto done; + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) + goto done; + + memset(&args, 0, sizeof(args)); + + args.v1.ucAction = action; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + + /* wait for the panel to power up */ + if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { + int i; + + for (i = 0; i < 300; i++) { + if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) + return true; + mdelay(1); + } + return false; + } +done: + return true; +} + +union external_encoder_control { + EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; + EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; +}; + +static void +amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder *encoder, + struct drm_encoder *ext_encoder, + int action) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder *ext_amdgpu_encoder = to_amdgpu_encoder(ext_encoder); + union external_encoder_control args; + struct drm_connector *connector; + int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); + u8 frev, crev; + int dp_clock = 0; + int dp_lane_count = 0; + int connector_object_id = 0; + u32 ext_enum = (ext_amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; + + if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) + connector = amdgpu_get_connector_for_encoder_init(encoder); + else + connector = amdgpu_get_connector_for_encoder(encoder); + + if (connector) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_connector_atom_dig *dig_connector = + amdgpu_connector->con_priv; + + dp_clock = dig_connector->dp_clock; + dp_lane_count = dig_connector->dp_lane_count; + connector_object_id = + (amdgpu_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; + } + + memset(&args, 0, sizeof(args)); + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) + return; + + switch (frev) { + case 1: + /* no params on frev 1 */ + break; + case 2: + switch (crev) { + case 1: + case 2: + args.v1.sDigEncoder.ucAction = action; + args.v1.sDigEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + args.v1.sDigEncoder.ucEncoderMode = + amdgpu_atombios_encoder_get_encoder_mode(encoder); + + if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { + if (dp_clock == 270000) + args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; + args.v1.sDigEncoder.ucLaneNum = dp_lane_count; + } else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v1.sDigEncoder.ucLaneNum = 8; + else + args.v1.sDigEncoder.ucLaneNum = 4; + break; + case 3: + args.v3.sExtEncoder.ucAction = action; + if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) + args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); + else + args.v3.sExtEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); + args.v3.sExtEncoder.ucEncoderMode = + amdgpu_atombios_encoder_get_encoder_mode(encoder); + + if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { + if (dp_clock == 270000) + args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; + else if (dp_clock == 540000) + args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; + args.v3.sExtEncoder.ucLaneNum = dp_lane_count; + } else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) + args.v3.sExtEncoder.ucLaneNum = 8; + else + args.v3.sExtEncoder.ucLaneNum = 4; + switch (ext_enum) { + case GRAPH_OBJECT_ENUM_ID1: + args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; + break; + case GRAPH_OBJECT_ENUM_ID2: + args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; + break; + case GRAPH_OBJECT_ENUM_ID3: + args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; + break; + } + args.v3.sExtEncoder.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder); + break; + default: + DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); + return; + } + break; + default: + DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); + return; + } + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +static void +amdgpu_atombios_encoder_setup_dig(struct drm_encoder *encoder, int action) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + struct amdgpu_connector *amdgpu_connector = NULL; + struct amdgpu_connector_atom_dig *amdgpu_dig_connector = NULL; + + if (connector) { + amdgpu_connector = to_amdgpu_connector(connector); + amdgpu_dig_connector = amdgpu_connector->con_priv; + } + + if (action == ATOM_ENABLE) { + if (!connector) + dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; + else + dig->panel_mode = amdgpu_atombios_dp_get_panel_mode(encoder, connector); + + /* setup and enable the encoder */ + amdgpu_atombios_encoder_setup_dig_encoder(encoder, ATOM_ENCODER_CMD_SETUP, 0); + amdgpu_atombios_encoder_setup_dig_encoder(encoder, + ATOM_ENCODER_CMD_SETUP_PANEL_MODE, + dig->panel_mode); + if (ext_encoder) + amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, + EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); + if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) && + connector) { + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { + amdgpu_atombios_encoder_set_edp_panel_power(connector, + ATOM_TRANSMITTER_ACTION_POWER_ON); + amdgpu_dig_connector->edp_on = true; + } + } + /* enable the transmitter */ + amdgpu_atombios_encoder_setup_dig_transmitter(encoder, + ATOM_TRANSMITTER_ACTION_ENABLE, + 0, 0); + if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) && + connector) { + /* DP_SET_POWER_D0 is set in amdgpu_atombios_dp_link_train */ + amdgpu_atombios_dp_link_train(encoder, connector); + amdgpu_atombios_encoder_setup_dig_encoder(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); + } + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) + amdgpu_atombios_encoder_setup_dig_transmitter(encoder, + ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); + if (ext_encoder) + amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, ATOM_ENABLE); + } else { + if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) && + connector) + amdgpu_atombios_encoder_setup_dig_encoder(encoder, + ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); + if (ext_encoder) + amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, ATOM_DISABLE); + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) + amdgpu_atombios_encoder_setup_dig_transmitter(encoder, + ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); + + if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) && + connector) + amdgpu_atombios_dp_set_rx_power_state(connector, DP_SET_POWER_D3); + /* disable the transmitter */ + amdgpu_atombios_encoder_setup_dig_transmitter(encoder, + ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); + if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)) && + connector) { + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { + amdgpu_atombios_encoder_set_edp_panel_power(connector, + ATOM_TRANSMITTER_ACTION_POWER_OFF); + amdgpu_dig_connector->edp_on = false; + } + } + } +} + +void +amdgpu_atombios_encoder_dpms(struct drm_encoder *encoder, int mode) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + + DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", + amdgpu_encoder->encoder_id, mode, amdgpu_encoder->devices, + amdgpu_encoder->active_device); + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + switch (mode) { + case DRM_MODE_DPMS_ON: + amdgpu_atombios_encoder_setup_dig(encoder, ATOM_ENABLE); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + amdgpu_atombios_encoder_setup_dig(encoder, ATOM_DISABLE); + break; + } + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: + switch (mode) { + case DRM_MODE_DPMS_ON: + amdgpu_atombios_encoder_setup_dvo(encoder, ATOM_ENABLE); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + amdgpu_atombios_encoder_setup_dvo(encoder, ATOM_DISABLE); + break; + } + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + switch (mode) { + case DRM_MODE_DPMS_ON: + amdgpu_atombios_encoder_setup_dac(encoder, ATOM_ENABLE); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + amdgpu_atombios_encoder_setup_dac(encoder, ATOM_DISABLE); + break; + } + break; + default: + return; + } +} + +union crtc_source_param { + SELECT_CRTC_SOURCE_PS_ALLOCATION v1; + SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; + SELECT_CRTC_SOURCE_PARAMETERS_V3 v3; +}; + +void +amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + union crtc_source_param args; + int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); + uint8_t frev, crev; + struct amdgpu_encoder_atom_dig *dig; + + memset(&args, 0, sizeof(args)); + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) + return; + + switch (frev) { + case 1: + switch (crev) { + case 1: + default: + args.v1.ucCRTC = amdgpu_crtc->crtc_id; + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_TMDS1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: + args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; + break; + case ENCODER_OBJECT_ID_INTERNAL_LVDS: + case ENCODER_OBJECT_ID_INTERNAL_LVTM1: + if (amdgpu_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) + args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; + else + args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; + break; + case ENCODER_OBJECT_ID_INTERNAL_DVO1: + case ENCODER_OBJECT_ID_INTERNAL_DDI: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: + args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; + break; + case ENCODER_OBJECT_ID_INTERNAL_DAC1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; + else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; + else + args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; + break; + case ENCODER_OBJECT_ID_INTERNAL_DAC2: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; + else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; + else + args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; + break; + } + break; + case 2: + args.v2.ucCRTC = amdgpu_crtc->crtc_id; + if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + + if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) + args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; + else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) + args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; + else + args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); + } else if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; + } else { + args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); + } + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + dig = amdgpu_encoder->enc_priv; + switch (dig->dig_encoder) { + case 0: + args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; + break; + case 1: + args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; + break; + case 2: + args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; + break; + case 3: + args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; + break; + case 4: + args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; + break; + case 5: + args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; + break; + case 6: + args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; + break; + } + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: + args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; + else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; + else + args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; + else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; + else + args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; + break; + } + break; + case 3: + args.v3.ucCRTC = amdgpu_crtc->crtc_id; + if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + + if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) + args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; + else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) + args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; + else + args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); + } else if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; + } else { + args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); + } + args.v3.ucDstBpc = amdgpu_atombios_encoder_get_bpc(encoder); + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + dig = amdgpu_encoder->enc_priv; + switch (dig->dig_encoder) { + case 0: + args.v3.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; + break; + case 1: + args.v3.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; + break; + case 2: + args.v3.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; + break; + case 3: + args.v3.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; + break; + case 4: + args.v3.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; + break; + case 5: + args.v3.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; + break; + case 6: + args.v3.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; + break; + } + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: + args.v3.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID; + else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID; + else + args.v3.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) + args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID; + else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) + args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID; + else + args.v3.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; + break; + } + break; + } + break; + default: + DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); + return; + } + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); +} + +/* This only needs to be called once at startup */ +void +amdgpu_atombios_encoder_init_dig(struct amdgpu_device *adev) +{ + struct drm_device *dev = adev->ddev; + struct drm_encoder *encoder; + + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder); + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + amdgpu_atombios_encoder_setup_dig_transmitter(encoder, ATOM_TRANSMITTER_ACTION_INIT, + 0, 0); + break; + } + + if (ext_encoder) + amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, + EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); + } +} + +static bool +amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | + ATOM_DEVICE_CV_SUPPORT | + ATOM_DEVICE_CRT_SUPPORT)) { + DAC_LOAD_DETECTION_PS_ALLOCATION args; + int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); + uint8_t frev, crev; + + memset(&args, 0, sizeof(args)); + + if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) + return false; + + args.sDacload.ucMisc = 0; + + if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || + (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) + args.sDacload.ucDacType = ATOM_DAC_A; + else + args.sDacload.ucDacType = ATOM_DAC_B; + + if (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) + args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); + else if (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) + args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); + else if (amdgpu_connector->devices & ATOM_DEVICE_CV_SUPPORT) { + args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); + if (crev >= 3) + args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; + } else if (amdgpu_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { + args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); + if (crev >= 3) + args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; + } + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + + return true; + } else + return false; +} + +enum drm_connector_status +amdgpu_atombios_encoder_dac_detect(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + uint32_t bios_0_scratch; + + if (!amdgpu_atombios_encoder_dac_load_detect(encoder, connector)) { + DRM_DEBUG_KMS("detect returned false \n"); + return connector_status_unknown; + } + + bios_0_scratch = RREG32(mmBIOS_SCRATCH_0); + + DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, amdgpu_encoder->devices); + if (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { + if (bios_0_scratch & ATOM_S0_CRT1_MASK) + return connector_status_connected; + } + if (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { + if (bios_0_scratch & ATOM_S0_CRT2_MASK) + return connector_status_connected; + } + if (amdgpu_connector->devices & ATOM_DEVICE_CV_SUPPORT) { + if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) + return connector_status_connected; + } + if (amdgpu_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { + if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) + return connector_status_connected; /* CTV */ + else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) + return connector_status_connected; /* STV */ + } + return connector_status_disconnected; +} + +enum drm_connector_status +amdgpu_atombios_encoder_dig_detect(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder); + u32 bios_0_scratch; + + if (!ext_encoder) + return connector_status_unknown; + + if ((amdgpu_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) + return connector_status_unknown; + + /* load detect on the dp bridge */ + amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, + EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); + + bios_0_scratch = RREG32(mmBIOS_SCRATCH_0); + + DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, amdgpu_encoder->devices); + if (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { + if (bios_0_scratch & ATOM_S0_CRT1_MASK) + return connector_status_connected; + } + if (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { + if (bios_0_scratch & ATOM_S0_CRT2_MASK) + return connector_status_connected; + } + if (amdgpu_connector->devices & ATOM_DEVICE_CV_SUPPORT) { + if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) + return connector_status_connected; + } + if (amdgpu_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { + if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) + return connector_status_connected; /* CTV */ + else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) + return connector_status_connected; /* STV */ + } + return connector_status_disconnected; +} + +void +amdgpu_atombios_encoder_setup_ext_encoder_ddc(struct drm_encoder *encoder) +{ + struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder); + + if (ext_encoder) + /* ddc_setup on the dp bridge */ + amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, + EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); + +} + +void +amdgpu_atombios_encoder_set_bios_scratch_regs(struct drm_connector *connector, + struct drm_encoder *encoder, + bool connected) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_connector *amdgpu_connector = + to_amdgpu_connector(connector); + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; + + bios_0_scratch = RREG32(mmBIOS_SCRATCH_0); + bios_3_scratch = RREG32(mmBIOS_SCRATCH_3); + bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); + + if ((amdgpu_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && + (amdgpu_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { + if (connected) { + DRM_DEBUG_KMS("LCD1 connected\n"); + bios_0_scratch |= ATOM_S0_LCD1; + bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; + bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; + } else { + DRM_DEBUG_KMS("LCD1 disconnected\n"); + bios_0_scratch &= ~ATOM_S0_LCD1; + bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; + bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; + } + } + if ((amdgpu_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && + (amdgpu_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { + if (connected) { + DRM_DEBUG_KMS("CRT1 connected\n"); + bios_0_scratch |= ATOM_S0_CRT1_COLOR; + bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; + bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; + } else { + DRM_DEBUG_KMS("CRT1 disconnected\n"); + bios_0_scratch &= ~ATOM_S0_CRT1_MASK; + bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; + bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; + } + } + if ((amdgpu_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && + (amdgpu_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { + if (connected) { + DRM_DEBUG_KMS("CRT2 connected\n"); + bios_0_scratch |= ATOM_S0_CRT2_COLOR; + bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; + bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; + } else { + DRM_DEBUG_KMS("CRT2 disconnected\n"); + bios_0_scratch &= ~ATOM_S0_CRT2_MASK; + bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; + bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; + } + } + if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && + (amdgpu_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { + if (connected) { + DRM_DEBUG_KMS("DFP1 connected\n"); + bios_0_scratch |= ATOM_S0_DFP1; + bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; + bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; + } else { + DRM_DEBUG_KMS("DFP1 disconnected\n"); + bios_0_scratch &= ~ATOM_S0_DFP1; + bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; + bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; + } + } + if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && + (amdgpu_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { + if (connected) { + DRM_DEBUG_KMS("DFP2 connected\n"); + bios_0_scratch |= ATOM_S0_DFP2; + bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; + bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; + } else { + DRM_DEBUG_KMS("DFP2 disconnected\n"); + bios_0_scratch &= ~ATOM_S0_DFP2; + bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; + bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; + } + } + if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && + (amdgpu_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { + if (connected) { + DRM_DEBUG_KMS("DFP3 connected\n"); + bios_0_scratch |= ATOM_S0_DFP3; + bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; + bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; + } else { + DRM_DEBUG_KMS("DFP3 disconnected\n"); + bios_0_scratch &= ~ATOM_S0_DFP3; + bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; + bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; + } + } + if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && + (amdgpu_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { + if (connected) { + DRM_DEBUG_KMS("DFP4 connected\n"); + bios_0_scratch |= ATOM_S0_DFP4; + bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; + bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; + } else { + DRM_DEBUG_KMS("DFP4 disconnected\n"); + bios_0_scratch &= ~ATOM_S0_DFP4; + bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; + bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; + } + } + if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && + (amdgpu_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { + if (connected) { + DRM_DEBUG_KMS("DFP5 connected\n"); + bios_0_scratch |= ATOM_S0_DFP5; + bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; + bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; + } else { + DRM_DEBUG_KMS("DFP5 disconnected\n"); + bios_0_scratch &= ~ATOM_S0_DFP5; + bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; + bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; + } + } + if ((amdgpu_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && + (amdgpu_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { + if (connected) { + DRM_DEBUG_KMS("DFP6 connected\n"); + bios_0_scratch |= ATOM_S0_DFP6; + bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; + bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; + } else { + DRM_DEBUG_KMS("DFP6 disconnected\n"); + bios_0_scratch &= ~ATOM_S0_DFP6; + bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; + bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; + } + } + + WREG32(mmBIOS_SCRATCH_0, bios_0_scratch); + WREG32(mmBIOS_SCRATCH_3, bios_3_scratch); + WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); +} + +union lvds_info { + struct _ATOM_LVDS_INFO info; + struct _ATOM_LVDS_INFO_V12 info_12; +}; + +struct amdgpu_encoder_atom_dig * +amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder) +{ + struct drm_device *dev = encoder->base.dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index = GetIndexIntoMasterTable(DATA, LVDS_Info); + uint16_t data_offset, misc; + union lvds_info *lvds_info; + uint8_t frev, crev; + struct amdgpu_encoder_atom_dig *lvds = NULL; + int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; + + if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) { + lvds_info = + (union lvds_info *)(mode_info->atom_context->bios + data_offset); + lvds = + kzalloc(sizeof(struct amdgpu_encoder_atom_dig), GFP_KERNEL); + + if (!lvds) + return NULL; + + lvds->native_mode.clock = + le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; + lvds->native_mode.hdisplay = + le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); + lvds->native_mode.vdisplay = + le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); + lvds->native_mode.htotal = lvds->native_mode.hdisplay + + le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); + lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + + le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); + lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + + le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); + lvds->native_mode.vtotal = lvds->native_mode.vdisplay + + le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); + lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + + le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); + lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + + le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); + lvds->panel_pwr_delay = + le16_to_cpu(lvds_info->info.usOffDelayInMs); + lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; + + misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); + if (misc & ATOM_VSYNC_POLARITY) + lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; + if (misc & ATOM_HSYNC_POLARITY) + lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; + if (misc & ATOM_COMPOSITESYNC) + lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; + if (misc & ATOM_INTERLACE) + lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; + if (misc & ATOM_DOUBLE_CLOCK_MODE) + lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; + + lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); + lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); + + /* set crtc values */ + drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); + + lvds->lcd_ss_id = lvds_info->info.ucSS_Id; + + encoder->native_mode = lvds->native_mode; + + if (encoder_enum == 2) + lvds->linkb = true; + else + lvds->linkb = false; + + /* parse the lcd record table */ + if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { + ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; + ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; + bool bad_record = false; + u8 *record; + + if ((frev == 1) && (crev < 2)) + /* absolute */ + record = (u8 *)(mode_info->atom_context->bios + + le16_to_cpu(lvds_info->info.usModePatchTableOffset)); + else + /* relative */ + record = (u8 *)(mode_info->atom_context->bios + + data_offset + + le16_to_cpu(lvds_info->info.usModePatchTableOffset)); + while (*record != ATOM_RECORD_END_TYPE) { + switch (*record) { + case LCD_MODE_PATCH_RECORD_MODE_TYPE: + record += sizeof(ATOM_PATCH_RECORD_MODE); + break; + case LCD_RTS_RECORD_TYPE: + record += sizeof(ATOM_LCD_RTS_RECORD); + break; + case LCD_CAP_RECORD_TYPE: + record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); + break; + case LCD_FAKE_EDID_PATCH_RECORD_TYPE: + fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; + if (fake_edid_record->ucFakeEDIDLength) { + struct edid *edid; + int edid_size = + max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); + edid = kmalloc(edid_size, GFP_KERNEL); + if (edid) { + memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], + fake_edid_record->ucFakeEDIDLength); + + if (drm_edid_is_valid(edid)) { + adev->mode_info.bios_hardcoded_edid = edid; + adev->mode_info.bios_hardcoded_edid_size = edid_size; + } else + kfree(edid); + } + } + record += fake_edid_record->ucFakeEDIDLength ? + fake_edid_record->ucFakeEDIDLength + 2 : + sizeof(ATOM_FAKE_EDID_PATCH_RECORD); + break; + case LCD_PANEL_RESOLUTION_RECORD_TYPE: + panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; + lvds->native_mode.width_mm = panel_res_record->usHSize; + lvds->native_mode.height_mm = panel_res_record->usVSize; + record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); + break; + default: + DRM_ERROR("Bad LCD record %d\n", *record); + bad_record = true; + break; + } + if (bad_record) + break; + } + } + } + return lvds; +} + +struct amdgpu_encoder_atom_dig * +amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder *amdgpu_encoder) +{ + int encoder_enum = (amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; + struct amdgpu_encoder_atom_dig *dig = kzalloc(sizeof(struct amdgpu_encoder_atom_dig), GFP_KERNEL); + + if (!dig) + return NULL; + + /* coherent mode by default */ + dig->coherent_mode = true; + dig->dig_encoder = -1; + + if (encoder_enum == 2) + dig->linkb = true; + else + dig->linkb = false; + + return dig; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h new file mode 100644 index 000000000000..2bdec40515ce --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.h @@ -0,0 +1,73 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __ATOMBIOS_ENCODER_H__ +#define __ATOMBIOS_ENCODER_H__ + +u8 +amdgpu_atombios_encoder_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder); +void +amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder, + u8 level); +void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encoder, + struct drm_connector *drm_connector); +void +amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *amdgpu_encoder); +bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder); +bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); +int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder); +void +amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder, + int action, int panel_mode); +void +amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int action, + uint8_t lane_num, uint8_t lane_set); +bool +amdgpu_atombios_encoder_set_edp_panel_power(struct drm_connector *connector, + int action); +void +amdgpu_atombios_encoder_dpms(struct drm_encoder *encoder, int mode); +void +amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder); +void +amdgpu_atombios_encoder_init_dig(struct amdgpu_device *adev); +enum drm_connector_status +amdgpu_atombios_encoder_dac_detect(struct drm_encoder *encoder, + struct drm_connector *connector); +enum drm_connector_status +amdgpu_atombios_encoder_dig_detect(struct drm_encoder *encoder, + struct drm_connector *connector); +void +amdgpu_atombios_encoder_setup_ext_encoder_ddc(struct drm_encoder *encoder); +void +amdgpu_atombios_encoder_set_bios_scratch_regs(struct drm_connector *connector, + struct drm_encoder *encoder, + bool connected); +struct amdgpu_encoder_atom_dig * +amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder); +struct amdgpu_encoder_atom_dig * +amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder *amdgpu_encoder); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c new file mode 100644 index 000000000000..13cdb01e9b45 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c @@ -0,0 +1,158 @@ +/* + * Copyright 2011 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + * + */ +#include +#include +#include "amdgpu.h" +#include "atom.h" +#include "amdgpu_atombios.h" + +#define TARGET_HW_I2C_CLOCK 50 + +/* these are a limitation of ProcessI2cChannelTransaction not the hw */ +#define ATOM_MAX_HW_I2C_WRITE 3 +#define ATOM_MAX_HW_I2C_READ 255 + +static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan, + u8 slave_addr, u8 flags, + u8 *buf, u8 num) +{ + struct drm_device *dev = chan->dev; + struct amdgpu_device *adev = dev->dev_private; + PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args; + int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction); + unsigned char *base; + u16 out = cpu_to_le16(0); + int r = 0; + + memset(&args, 0, sizeof(args)); + + mutex_lock(&chan->mutex); + + base = (unsigned char *)adev->mode_info.atom_context->scratch; + + if (flags & HW_I2C_WRITE) { + if (num > ATOM_MAX_HW_I2C_WRITE) { + DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 3)\n", num); + r = -EINVAL; + goto done; + } + if (buf == NULL) + args.ucRegIndex = 0; + else + args.ucRegIndex = buf[0]; + if (num) + num--; + if (num) + memcpy(&out, &buf[1], num); + args.lpI2CDataOut = cpu_to_le16(out); + } else { + if (num > ATOM_MAX_HW_I2C_READ) { + DRM_ERROR("hw i2c: tried to read too many bytes (%d vs 255)\n", num); + r = -EINVAL; + goto done; + } + args.ucRegIndex = 0; + args.lpI2CDataOut = 0; + } + + args.ucFlag = flags; + args.ucI2CSpeed = TARGET_HW_I2C_CLOCK; + args.ucTransBytes = num; + args.ucSlaveAddr = slave_addr << 1; + args.ucLineNumber = chan->rec.i2c_id; + + amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); + + /* error */ + if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) { + DRM_DEBUG_KMS("hw_i2c error\n"); + r = -EIO; + goto done; + } + + if (!(flags & HW_I2C_WRITE)) + amdgpu_atombios_copy_swap(buf, base, num, false); + +done: + mutex_unlock(&chan->mutex); + + return r; +} + +int amdgpu_atombios_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num) +{ + struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); + struct i2c_msg *p; + int i, remaining, current_count, buffer_offset, max_bytes, ret; + u8 flags; + + /* check for bus probe */ + p = &msgs[0]; + if ((num == 1) && (p->len == 0)) { + ret = amdgpu_atombios_i2c_process_i2c_ch(i2c, + p->addr, HW_I2C_WRITE, + NULL, 0); + if (ret) + return ret; + else + return num; + } + + for (i = 0; i < num; i++) { + p = &msgs[i]; + remaining = p->len; + buffer_offset = 0; + /* max_bytes are a limitation of ProcessI2cChannelTransaction not the hw */ + if (p->flags & I2C_M_RD) { + max_bytes = ATOM_MAX_HW_I2C_READ; + flags = HW_I2C_READ; + } else { + max_bytes = ATOM_MAX_HW_I2C_WRITE; + flags = HW_I2C_WRITE; + } + while (remaining) { + if (remaining > max_bytes) + current_count = max_bytes; + else + current_count = remaining; + ret = amdgpu_atombios_i2c_process_i2c_ch(i2c, + p->addr, flags, + &p->buf[buffer_offset], current_count); + if (ret) + return ret; + remaining -= current_count; + buffer_offset += current_count; + } + } + + return num; +} + +u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.h b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.h new file mode 100644 index 000000000000..d6128d9de56e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.h @@ -0,0 +1,31 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __ATOMBIOS_I2C_H__ +#define __ATOMBIOS_I2C_H__ + +int amdgpu_atombios_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num); +u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h new file mode 100644 index 000000000000..11828e2cdf34 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cikd.h @@ -0,0 +1,550 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ +#ifndef CIK_H +#define CIK_H + +#define MC_SEQ_MISC0__GDDR5__SHIFT 0x1c +#define MC_SEQ_MISC0__GDDR5_MASK 0xf0000000 +#define MC_SEQ_MISC0__GDDR5_VALUE 5 + +#define CP_ME_TABLE_SIZE 96 + +/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ +#define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) +#define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) +#define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) +#define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) +#define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) +#define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) + +#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 +#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 + +#define CIK_RB_BITMAP_WIDTH_PER_SH 2 +#define HAWAII_RB_BITMAP_WIDTH_PER_SH 4 + +#define AMDGPU_NUM_OF_VMIDS 8 + +#define PIPEID(x) ((x) << 0) +#define MEID(x) ((x) << 2) +#define VMID(x) ((x) << 4) +#define QUEUEID(x) ((x) << 8) + +#define mmCC_DRM_ID_STRAPS 0x1559 +#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 + +#define mmCHUB_CONTROL 0x619 +#define BYPASS_VM (1 << 0) + +#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) + +#define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 +#define LUT_10BIT_BYPASS_EN (1 << 8) + +# define CURSOR_MONO 0 +# define CURSOR_24_1 1 +# define CURSOR_24_8_PRE_MULT 2 +# define CURSOR_24_8_UNPRE_MULT 3 +# define CURSOR_URGENT_ALWAYS 0 +# define CURSOR_URGENT_1_8 1 +# define CURSOR_URGENT_1_4 2 +# define CURSOR_URGENT_3_8 3 +# define CURSOR_URGENT_1_2 4 + +# define GRPH_DEPTH_8BPP 0 +# define GRPH_DEPTH_16BPP 1 +# define GRPH_DEPTH_32BPP 2 +/* 8 BPP */ +# define GRPH_FORMAT_INDEXED 0 +/* 16 BPP */ +# define GRPH_FORMAT_ARGB1555 0 +# define GRPH_FORMAT_ARGB565 1 +# define GRPH_FORMAT_ARGB4444 2 +# define GRPH_FORMAT_AI88 3 +# define GRPH_FORMAT_MONO16 4 +# define GRPH_FORMAT_BGRA5551 5 +/* 32 BPP */ +# define GRPH_FORMAT_ARGB8888 0 +# define GRPH_FORMAT_ARGB2101010 1 +# define GRPH_FORMAT_32BPP_DIG 2 +# define GRPH_FORMAT_8B_ARGB2101010 3 +# define GRPH_FORMAT_BGRA1010102 4 +# define GRPH_FORMAT_8B_BGRA1010102 5 +# define GRPH_FORMAT_RGB111110 6 +# define GRPH_FORMAT_BGR101111 7 +# define ADDR_SURF_MACRO_TILE_ASPECT_1 0 +# define ADDR_SURF_MACRO_TILE_ASPECT_2 1 +# define ADDR_SURF_MACRO_TILE_ASPECT_4 2 +# define ADDR_SURF_MACRO_TILE_ASPECT_8 3 +# define GRPH_ARRAY_LINEAR_GENERAL 0 +# define GRPH_ARRAY_LINEAR_ALIGNED 1 +# define GRPH_ARRAY_1D_TILED_THIN1 2 +# define GRPH_ARRAY_2D_TILED_THIN1 4 +# define DISPLAY_MICRO_TILING 0 +# define THIN_MICRO_TILING 1 +# define DEPTH_MICRO_TILING 2 +# define ROTATED_MICRO_TILING 4 +# define GRPH_ENDIAN_NONE 0 +# define GRPH_ENDIAN_8IN16 1 +# define GRPH_ENDIAN_8IN32 2 +# define GRPH_ENDIAN_8IN64 3 +# define GRPH_RED_SEL_R 0 +# define GRPH_RED_SEL_G 1 +# define GRPH_RED_SEL_B 2 +# define GRPH_RED_SEL_A 3 +# define GRPH_GREEN_SEL_G 0 +# define GRPH_GREEN_SEL_B 1 +# define GRPH_GREEN_SEL_A 2 +# define GRPH_GREEN_SEL_R 3 +# define GRPH_BLUE_SEL_B 0 +# define GRPH_BLUE_SEL_A 1 +# define GRPH_BLUE_SEL_R 2 +# define GRPH_BLUE_SEL_G 3 +# define GRPH_ALPHA_SEL_A 0 +# define GRPH_ALPHA_SEL_R 1 +# define GRPH_ALPHA_SEL_G 2 +# define GRPH_ALPHA_SEL_B 3 +# define INPUT_GAMMA_USE_LUT 0 +# define INPUT_GAMMA_BYPASS 1 +# define INPUT_GAMMA_SRGB_24 2 +# define INPUT_GAMMA_XVYCC_222 3 + +# define INPUT_CSC_BYPASS 0 +# define INPUT_CSC_PROG_COEFF 1 +# define INPUT_CSC_PROG_SHARED_MATRIXA 2 + +# define OUTPUT_CSC_BYPASS 0 +# define OUTPUT_CSC_TV_RGB 1 +# define OUTPUT_CSC_YCBCR_601 2 +# define OUTPUT_CSC_YCBCR_709 3 +# define OUTPUT_CSC_PROG_COEFF 4 +# define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 + +# define DEGAMMA_BYPASS 0 +# define DEGAMMA_SRGB_24 1 +# define DEGAMMA_XVYCC_222 2 +# define GAMUT_REMAP_BYPASS 0 +# define GAMUT_REMAP_PROG_COEFF 1 +# define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 +# define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 + +# define REGAMMA_BYPASS 0 +# define REGAMMA_SRGB_24 1 +# define REGAMMA_XVYCC_222 2 +# define REGAMMA_PROG_A 3 +# define REGAMMA_PROG_B 4 + +# define FMT_CLAMP_6BPC 0 +# define FMT_CLAMP_8BPC 1 +# define FMT_CLAMP_10BPC 2 + +# define HDMI_24BIT_DEEP_COLOR 0 +# define HDMI_30BIT_DEEP_COLOR 1 +# define HDMI_36BIT_DEEP_COLOR 2 +# define HDMI_ACR_HW 0 +# define HDMI_ACR_32 1 +# define HDMI_ACR_44 2 +# define HDMI_ACR_48 3 +# define HDMI_ACR_X1 1 +# define HDMI_ACR_X2 2 +# define HDMI_ACR_X4 4 +# define AFMT_AVI_INFO_Y_RGB 0 +# define AFMT_AVI_INFO_Y_YCBCR422 1 +# define AFMT_AVI_INFO_Y_YCBCR444 2 + +#define NO_AUTO 0 +#define ES_AUTO 1 +#define GS_AUTO 2 +#define ES_AND_GS_AUTO 3 + +# define ARRAY_MODE(x) ((x) << 2) +# define PIPE_CONFIG(x) ((x) << 6) +# define TILE_SPLIT(x) ((x) << 11) +# define MICRO_TILE_MODE_NEW(x) ((x) << 22) +# define SAMPLE_SPLIT(x) ((x) << 25) +# define BANK_WIDTH(x) ((x) << 0) +# define BANK_HEIGHT(x) ((x) << 2) +# define MACRO_TILE_ASPECT(x) ((x) << 4) +# define NUM_BANKS(x) ((x) << 6) + +#define MSG_ENTER_RLC_SAFE_MODE 1 +#define MSG_EXIT_RLC_SAFE_MODE 0 + +/* + * PM4 + */ +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) +#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ + ((reg) & 0xFFFF) | \ + ((n) & 0x3FFF) << 16) +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) + +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) + +#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ + (((op) & 0xFF) << 8) | \ + ((n) & 0x3FFF) << 16) + +#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) + +/* Packet 3 types */ +#define PACKET3_NOP 0x10 +#define PACKET3_SET_BASE 0x11 +#define PACKET3_BASE_INDEX(x) ((x) << 0) +#define CE_PARTITION_BASE 3 +#define PACKET3_CLEAR_STATE 0x12 +#define PACKET3_INDEX_BUFFER_SIZE 0x13 +#define PACKET3_DISPATCH_DIRECT 0x15 +#define PACKET3_DISPATCH_INDIRECT 0x16 +#define PACKET3_ATOMIC_GDS 0x1D +#define PACKET3_ATOMIC_MEM 0x1E +#define PACKET3_OCCLUSION_QUERY 0x1F +#define PACKET3_SET_PREDICATION 0x20 +#define PACKET3_REG_RMW 0x21 +#define PACKET3_COND_EXEC 0x22 +#define PACKET3_PRED_EXEC 0x23 +#define PACKET3_DRAW_INDIRECT 0x24 +#define PACKET3_DRAW_INDEX_INDIRECT 0x25 +#define PACKET3_INDEX_BASE 0x26 +#define PACKET3_DRAW_INDEX_2 0x27 +#define PACKET3_CONTEXT_CONTROL 0x28 +#define PACKET3_INDEX_TYPE 0x2A +#define PACKET3_DRAW_INDIRECT_MULTI 0x2C +#define PACKET3_DRAW_INDEX_AUTO 0x2D +#define PACKET3_NUM_INSTANCES 0x2F +#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 +#define PACKET3_INDIRECT_BUFFER_CONST 0x33 +#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 +#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 +#define PACKET3_DRAW_PREAMBLE 0x36 +#define PACKET3_WRITE_DATA 0x37 +#define WRITE_DATA_DST_SEL(x) ((x) << 8) + /* 0 - register + * 1 - memory (sync - via GRBM) + * 2 - gl2 + * 3 - gds + * 4 - reserved + * 5 - memory (async - direct) + */ +#define WR_ONE_ADDR (1 << 16) +#define WR_CONFIRM (1 << 20) +#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + */ +#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) + /* 0 - me + * 1 - pfp + * 2 - ce + */ +#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 +#define PACKET3_MEM_SEMAPHORE 0x39 +# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) +# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ +# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ +# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) +# define PACKET3_SEM_SEL_WAIT (0x7 << 29) +#define PACKET3_COPY_DW 0x3B +#define PACKET3_WAIT_REG_MEM 0x3C +#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) + /* 0 - always + * 1 - < + * 2 - <= + * 3 - == + * 4 - != + * 5 - >= + * 6 - > + */ +#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) + /* 0 - reg + * 1 - mem + */ +#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) + /* 0 - wait_reg_mem + * 1 - wr_wait_wr_reg + */ +#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) + /* 0 - me + * 1 - pfp + */ +#define PACKET3_INDIRECT_BUFFER 0x3F +#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) +#define INDIRECT_BUFFER_VALID (1 << 23) +#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +#define PACKET3_COPY_DATA 0x40 +#define PACKET3_PFP_SYNC_ME 0x42 +#define PACKET3_SURFACE_SYNC 0x43 +# define PACKET3_DEST_BASE_0_ENA (1 << 0) +# define PACKET3_DEST_BASE_1_ENA (1 << 1) +# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) +# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) +# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) +# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) +# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) +# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) +# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) +# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) +# define PACKET3_DB_DEST_BASE_ENA (1 << 14) +# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) +# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ +# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ +# define PACKET3_DEST_BASE_2_ENA (1 << 19) +# define PACKET3_DEST_BASE_3_ENA (1 << 21) +# define PACKET3_TCL1_ACTION_ENA (1 << 22) +# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ +# define PACKET3_CB_ACTION_ENA (1 << 25) +# define PACKET3_DB_ACTION_ENA (1 << 26) +# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) +# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) +# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) +#define PACKET3_COND_WRITE 0x45 +#define PACKET3_EVENT_WRITE 0x46 +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) + /* 0 - any non-TS event + * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* + * 2 - SAMPLE_PIPELINESTAT + * 3 - SAMPLE_STREAMOUTSTAT* + * 4 - *S_PARTIAL_FLUSH + * 5 - EOP events + * 6 - EOS events + */ +#define PACKET3_EVENT_WRITE_EOP 0x47 +#define EOP_TCL1_VOL_ACTION_EN (1 << 12) +#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ +#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ +#define EOP_TCL1_ACTION_EN (1 << 16) +#define EOP_TC_ACTION_EN (1 << 17) /* L2 */ +#define EOP_TCL2_VOLATILE (1 << 24) +#define EOP_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +#define DATA_SEL(x) ((x) << 29) + /* 0 - discard + * 1 - send low 32bit data + * 2 - send 64bit data + * 3 - send 64bit GPU counter value + * 4 - send 64bit sys counter value + */ +#define INT_SEL(x) ((x) << 24) + /* 0 - none + * 1 - interrupt only (DATA_SEL = 0) + * 2 - interrupt when data write is confirmed + */ +#define DST_SEL(x) ((x) << 16) + /* 0 - MC + * 1 - TC/L2 + */ +#define PACKET3_EVENT_WRITE_EOS 0x48 +#define PACKET3_RELEASE_MEM 0x49 +#define PACKET3_PREAMBLE_CNTL 0x4A +# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) +# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) +#define PACKET3_DMA_DATA 0x50 +/* 1. header + * 2. CONTROL + * 3. SRC_ADDR_LO or DATA [31:0] + * 4. SRC_ADDR_HI [31:0] + * 5. DST_ADDR_LO [31:0] + * 6. DST_ADDR_HI [7:0] + * 7. COMMAND [30:21] | BYTE_COUNT [20:0] + */ +/* CONTROL */ +# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) + /* 0 - ME + * 1 - PFP + */ +# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) +# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) + /* 0 - DST_ADDR using DAS + * 1 - GDS + * 3 - DST_ADDR using L2 + */ +# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) +# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) + /* 0 - SRC_ADDR using SAS + * 1 - GDS + * 2 - DATA + * 3 - SRC_ADDR using L2 + */ +# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) +/* COMMAND */ +# define PACKET3_DMA_DATA_DIS_WC (1 << 21) +# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) + /* 0 - none + * 1 - 8 in 16 + * 2 - 8 in 32 + * 3 - 8 in 64 + */ +# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) + /* 0 - none + * 1 - 8 in 16 + * 2 - 8 in 32 + * 3 - 8 in 64 + */ +# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) +# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) +# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) +#define PACKET3_AQUIRE_MEM 0x58 +#define PACKET3_REWIND 0x59 +#define PACKET3_LOAD_UCONFIG_REG 0x5E +#define PACKET3_LOAD_SH_REG 0x5F +#define PACKET3_LOAD_CONFIG_REG 0x60 +#define PACKET3_LOAD_CONTEXT_REG 0x61 +#define PACKET3_SET_CONFIG_REG 0x68 +#define PACKET3_SET_CONFIG_REG_START 0x00002000 +#define PACKET3_SET_CONFIG_REG_END 0x00002c00 +#define PACKET3_SET_CONTEXT_REG 0x69 +#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 +#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 +#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 +#define PACKET3_SET_SH_REG 0x76 +#define PACKET3_SET_SH_REG_START 0x00002c00 +#define PACKET3_SET_SH_REG_END 0x00003000 +#define PACKET3_SET_SH_REG_OFFSET 0x77 +#define PACKET3_SET_QUEUE_REG 0x78 +#define PACKET3_SET_UCONFIG_REG 0x79 +#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 +#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 +#define PACKET3_SCRATCH_RAM_WRITE 0x7D +#define PACKET3_SCRATCH_RAM_READ 0x7E +#define PACKET3_LOAD_CONST_RAM 0x80 +#define PACKET3_WRITE_CONST_RAM 0x81 +#define PACKET3_DUMP_CONST_RAM 0x83 +#define PACKET3_INCREMENT_CE_COUNTER 0x84 +#define PACKET3_INCREMENT_DE_COUNTER 0x85 +#define PACKET3_WAIT_ON_CE_COUNTER 0x86 +#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 +#define PACKET3_SWITCH_BUFFER 0x8B + +/* SDMA - first instance at 0xd000, second at 0xd800 */ +#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ +#define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ +#define SDMA_MAX_INSTANCE 2 + +#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ + (((sub_op) & 0xFF) << 8) | \ + (((op) & 0xFF) << 0)) +/* sDMA opcodes */ +#define SDMA_OPCODE_NOP 0 +#define SDMA_OPCODE_COPY 1 +# define SDMA_COPY_SUB_OPCODE_LINEAR 0 +# define SDMA_COPY_SUB_OPCODE_TILED 1 +# define SDMA_COPY_SUB_OPCODE_SOA 3 +# define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 +# define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 +# define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 +#define SDMA_OPCODE_WRITE 2 +# define SDMA_WRITE_SUB_OPCODE_LINEAR 0 +# define SDMA_WRTIE_SUB_OPCODE_TILED 1 +#define SDMA_OPCODE_INDIRECT_BUFFER 4 +#define SDMA_OPCODE_FENCE 5 +#define SDMA_OPCODE_TRAP 6 +#define SDMA_OPCODE_SEMAPHORE 7 +# define SDMA_SEMAPHORE_EXTRA_O (1 << 13) + /* 0 - increment + * 1 - write 1 + */ +# define SDMA_SEMAPHORE_EXTRA_S (1 << 14) + /* 0 - wait + * 1 - signal + */ +# define SDMA_SEMAPHORE_EXTRA_M (1 << 15) + /* mailbox */ +#define SDMA_OPCODE_POLL_REG_MEM 8 +# define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) + /* 0 - wait_reg_mem + * 1 - wr_wait_wr_reg + */ +# define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) + /* 0 - always + * 1 - < + * 2 - <= + * 3 - == + * 4 - != + * 5 - >= + * 6 - > + */ +# define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) + /* 0 = register + * 1 = memory + */ +#define SDMA_OPCODE_COND_EXEC 9 +#define SDMA_OPCODE_CONSTANT_FILL 11 +# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) + /* 0 = byte fill + * 2 = DW fill + */ +#define SDMA_OPCODE_GENERATE_PTE_PDE 12 +#define SDMA_OPCODE_TIMESTAMP 13 +# define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 +# define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 +# define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 +#define SDMA_OPCODE_SRBM_WRITE 14 +# define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) + /* byte mask */ + +#define VCE_CMD_NO_OP 0x00000000 +#define VCE_CMD_END 0x00000001 +#define VCE_CMD_IB 0x00000002 +#define VCE_CMD_FENCE 0x00000003 +#define VCE_CMD_TRAP 0x00000004 +#define VCE_CMD_IB_AUTO 0x00000005 +#define VCE_CMD_SEMAPHORE 0x00000006 + +#endif -- cgit v1.2.3 From 17b10f941f939da459072a066c6e5e9af9dda610 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 16 Apr 2015 15:48:09 -0400 Subject: drm/amdgpu: fix const warnings in amdgpu_connectors.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 6a8d28f81780..27df17a0e620 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -135,7 +135,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) if (connector->display_info.bpc) bpc = connector->display_info.bpc; else { - struct drm_connector_helper_funcs *connector_funcs = + const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; struct drm_encoder *encoder = connector_funcs->best_encoder(connector); struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); @@ -216,7 +216,7 @@ amdgpu_connector_update_scratch_regs(struct drm_connector *connector, { struct drm_encoder *best_encoder = NULL; struct drm_encoder *encoder = NULL; - struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; + const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; bool connected; int i; @@ -597,7 +597,7 @@ static int amdgpu_connector_set_property(struct drm_connector *connector, if (connector->encoder) { amdgpu_encoder = to_amdgpu_encoder(connector->encoder); } else { - struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; + const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); } @@ -788,7 +788,7 @@ static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, if (connector->encoder) amdgpu_encoder = to_amdgpu_encoder(connector->encoder); else { - struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; + const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); } @@ -852,7 +852,7 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct drm_encoder *encoder; - struct drm_encoder_helper_funcs *encoder_funcs; + const struct drm_encoder_helper_funcs *encoder_funcs; bool dret = false; enum drm_connector_status ret = connector_status_disconnected; int r; @@ -971,7 +971,7 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) struct amdgpu_device *adev = dev->dev_private; struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct drm_encoder *encoder = NULL; - struct drm_encoder_helper_funcs *encoder_funcs; + const struct drm_encoder_helper_funcs *encoder_funcs; int i, r; enum drm_connector_status ret = connector_status_disconnected; bool dret = false, broken_edid = false; @@ -1391,7 +1391,7 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */ ret = connector_status_connected; else if (amdgpu_connector->dac_load_detect) { /* try load detection */ - struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; + const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; ret = encoder_funcs->detect(encoder, connector); } } -- cgit v1.2.3 From 18da4340e651dd41d698fc54084b9139b614539b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 17 Apr 2015 10:50:02 -0400 Subject: drm/amdgpu: Do not directly dereference pointers to BIOS area. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use readb() and memcpy_fromio() accessors instead. Ported from radeon commit: f2c9e560b406f2f6b14b345c7da33467dee9cdf2 Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index d7a3ab2624f0..ceb444f6d418 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -75,7 +75,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev) bool amdgpu_read_bios(struct amdgpu_device *adev) { - uint8_t __iomem *bios; + uint8_t __iomem *bios, val1, val2; size_t size; adev->bios = NULL; @@ -85,15 +85,19 @@ bool amdgpu_read_bios(struct amdgpu_device *adev) return false; } - if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { + val1 = readb(&bios[0]); + val2 = readb(&bios[1]); + + if (size == 0 || val1 != 0x55 || val2 != 0xaa) { pci_unmap_rom(adev->pdev, bios); return false; } - adev->bios = kmemdup(bios, size, GFP_KERNEL); + adev->bios = kzalloc(size, GFP_KERNEL); if (adev->bios == NULL) { pci_unmap_rom(adev->pdev, bios); return false; } + memcpy_fromio(adev->bios, bios, size); pci_unmap_rom(adev->pdev, bios); return true; } -- cgit v1.2.3 From a2e73f56fa6282481927ec43aa9362c03c2e2104 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Apr 2015 17:09:27 -0400 Subject: drm/amdgpu: Add support for CIK parts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds support for CIK parts. These parts are also supported by radeon which is the preferred option, so there is a config option to enable support for CIK parts in amdgpu for testing. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 + drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 6684 ++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/ci_dpm.h | 348 ++ drivers/gpu/drm/amd/amdgpu/ci_smc.c | 279 ++ drivers/gpu/drm/amd/amdgpu/cik.c | 2505 +++++++++++ drivers/gpu/drm/amd/amdgpu/cik.h | 33 + drivers/gpu/drm/amd/amdgpu/cik_dpm.h | 30 + drivers/gpu/drm/amd/amdgpu/cik_ih.c | 453 ++ drivers/gpu/drm/amd/amdgpu/cik_ih.h | 29 + drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1422 ++++++ drivers/gpu/drm/amd/amdgpu/cik_sdma.h | 29 + drivers/gpu/drm/amd/amdgpu/clearstate_ci.h | 944 ++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 3830 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.h | 29 + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5635 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h | 37 + drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1307 ++++++ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h | 36 + drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 3336 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/kv_dpm.h | 229 + drivers/gpu/drm/amd/amdgpu/kv_smc.c | 219 + drivers/gpu/drm/amd/amdgpu/smu7.h | 170 + drivers/gpu/drm/amd/amdgpu/smu7_discrete.h | 514 +++ drivers/gpu/drm/amd/amdgpu/smu7_fusion.h | 300 ++ drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 888 ++++ drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h | 29 + drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 642 +++ drivers/gpu/drm/amd/amdgpu/vce_v2_0.h | 29 + 29 files changed, 30008 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/ci_dpm.c create mode 100644 drivers/gpu/drm/amd/amdgpu/ci_dpm.h create mode 100644 drivers/gpu/drm/amd/amdgpu/ci_smc.c create mode 100644 drivers/gpu/drm/amd/amdgpu/cik.c create mode 100644 drivers/gpu/drm/amd/amdgpu/cik.h create mode 100644 drivers/gpu/drm/amd/amdgpu/cik_dpm.h create mode 100644 drivers/gpu/drm/amd/amdgpu/cik_ih.c create mode 100644 drivers/gpu/drm/amd/amdgpu/cik_ih.h create mode 100644 drivers/gpu/drm/amd/amdgpu/cik_sdma.c create mode 100644 drivers/gpu/drm/amd/amdgpu/cik_sdma.h create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_ci.h create mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v8_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/kv_dpm.c create mode 100644 drivers/gpu/drm/amd/amdgpu/kv_dpm.h create mode 100644 drivers/gpu/drm/amd/amdgpu/kv_smc.c create mode 100644 drivers/gpu/drm/amd/amdgpu/smu7.h create mode 100644 drivers/gpu/drm/amd/amdgpu/smu7_discrete.h create mode 100644 drivers/gpu/drm/amd/amdgpu/smu7_fusion.h create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v2_0.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 01276a592bc5..aec28866945f 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -18,6 +18,9 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o +amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o gmc_v7_0.o cik_ih.o kv_smc.o kv_dpm.o \ + ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o + # add IH block amdgpu-y += \ amdgpu_irq.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index cd4bb90fa85c..548e0843d95a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -38,6 +38,9 @@ #include "amdgpu_i2c.h" #include "atom.h" #include "amdgpu_atombios.h" +#ifdef CONFIG_DRM_AMDGPU_CIK +#include "cik.h" +#endif #include "bif/bif_4_1_d.h" static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); @@ -1154,6 +1157,22 @@ static int amdgpu_early_init(struct amdgpu_device *adev) int i, r = -EINVAL; switch (adev->asic_type) { +#ifdef CONFIG_DRM_AMDGPU_CIK + case CHIP_BONAIRE: + case CHIP_HAWAII: + case CHIP_KAVERI: + case CHIP_KABINI: + case CHIP_MULLINS: + if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) + adev->family = AMDGPU_FAMILY_CI; + else + adev->family = AMDGPU_FAMILY_KV; + + r = cik_set_ip_blocks(adev); + if (r) + return r; + break; +#endif default: /* FIXME: not supported yet */ return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c new file mode 100644 index 000000000000..5a9dad8e55c9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -0,0 +1,6684 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_pm.h" +#include "amdgpu_ucode.h" +#include "cikd.h" +#include "amdgpu_dpm.h" +#include "ci_dpm.h" +#include "gfx_v7_0.h" +#include "atom.h" +#include + +#include "smu/smu_7_0_1_d.h" +#include "smu/smu_7_0_1_sh_mask.h" + +#include "dce/dce_8_0_d.h" +#include "dce/dce_8_0_sh_mask.h" + +#include "bif/bif_4_1_d.h" +#include "bif/bif_4_1_sh_mask.h" + +#include "gca/gfx_7_2_d.h" +#include "gca/gfx_7_2_sh_mask.h" + +#include "gmc/gmc_7_1_d.h" +#include "gmc/gmc_7_1_sh_mask.h" + +MODULE_FIRMWARE("radeon/bonaire_smc.bin"); +MODULE_FIRMWARE("radeon/hawaii_smc.bin"); + +#define MC_CG_ARB_FREQ_F0 0x0a +#define MC_CG_ARB_FREQ_F1 0x0b +#define MC_CG_ARB_FREQ_F2 0x0c +#define MC_CG_ARB_FREQ_F3 0x0d + +#define SMC_RAM_END 0x40000 + +#define VOLTAGE_SCALE 4 +#define VOLTAGE_VID_OFFSET_SCALE1 625 +#define VOLTAGE_VID_OFFSET_SCALE2 100 + +static const struct ci_pt_defaults defaults_hawaii_xt = +{ + 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000, + { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 }, + { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 } +}; + +static const struct ci_pt_defaults defaults_hawaii_pro = +{ + 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062, + { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 }, + { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 } +}; + +static const struct ci_pt_defaults defaults_bonaire_xt = +{ + 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, + { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 }, + { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } +}; + +static const struct ci_pt_defaults defaults_bonaire_pro = +{ + 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062, + { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F }, + { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB } +}; + +static const struct ci_pt_defaults defaults_saturn_xt = +{ + 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000, + { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D }, + { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 } +}; + +static const struct ci_pt_defaults defaults_saturn_pro = +{ + 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000, + { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A }, + { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 } +}; + +static const struct ci_pt_config_reg didt_config_ci[] = +{ + { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND }, + { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND }, + { 0xFFFFFFFF } +}; + +static u8 ci_get_memory_module_index(struct amdgpu_device *adev) +{ + return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff); +} + +#define MC_CG_ARB_FREQ_F0 0x0a +#define MC_CG_ARB_FREQ_F1 0x0b +#define MC_CG_ARB_FREQ_F2 0x0c +#define MC_CG_ARB_FREQ_F3 0x0d + +static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev, + u32 arb_freq_src, u32 arb_freq_dest) +{ + u32 mc_arb_dram_timing; + u32 mc_arb_dram_timing2; + u32 burst_time; + u32 mc_cg_config; + + switch (arb_freq_src) { + case MC_CG_ARB_FREQ_F0: + mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING); + mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2); + burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >> + MC_ARB_BURST_TIME__STATE0__SHIFT; + break; + case MC_CG_ARB_FREQ_F1: + mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING_1); + mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1); + burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >> + MC_ARB_BURST_TIME__STATE1__SHIFT; + break; + default: + return -EINVAL; + } + + switch (arb_freq_dest) { + case MC_CG_ARB_FREQ_F0: + WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); + WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); + WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT), + ~MC_ARB_BURST_TIME__STATE0_MASK); + break; + case MC_CG_ARB_FREQ_F1: + WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); + WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); + WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT), + ~MC_ARB_BURST_TIME__STATE1_MASK); + break; + default: + return -EINVAL; + } + + mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F; + WREG32(mmMC_CG_CONFIG, mc_cg_config); + WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT, + ~MC_ARB_CG__CG_ARB_REQ_MASK); + + return 0; +} + +static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock) +{ + u8 mc_para_index; + + if (memory_clock < 10000) + mc_para_index = 0; + else if (memory_clock >= 80000) + mc_para_index = 0x0f; + else + mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); + return mc_para_index; +} + +static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) +{ + u8 mc_para_index; + + if (strobe_mode) { + if (memory_clock < 12500) + mc_para_index = 0x00; + else if (memory_clock > 47500) + mc_para_index = 0x0f; + else + mc_para_index = (u8)((memory_clock - 10000) / 2500); + } else { + if (memory_clock < 65000) + mc_para_index = 0x00; + else if (memory_clock > 135000) + mc_para_index = 0x0f; + else + mc_para_index = (u8)((memory_clock - 60000) / 5000); + } + return mc_para_index; +} + +static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, + u32 max_voltage_steps, + struct atom_voltage_table *voltage_table) +{ + unsigned int i, diff; + + if (voltage_table->count <= max_voltage_steps) + return; + + diff = voltage_table->count - max_voltage_steps; + + for (i = 0; i < max_voltage_steps; i++) + voltage_table->entries[i] = voltage_table->entries[i + diff]; + + voltage_table->count = max_voltage_steps; +} + +static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev, + struct atom_voltage_table_entry *voltage_table, + u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd); +static int ci_set_power_limit(struct amdgpu_device *adev, u32 n); +static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev, + u32 target_tdp); +static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate); +static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev); +static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev); + +static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, + PPSMC_Msg msg, u32 parameter); +static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev); +static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev); + +static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = adev->pm.dpm.priv; + + return pi; +} + +static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps) +{ + struct ci_ps *ps = rps->ps_priv; + + return ps; +} + +static void ci_initialize_powertune_defaults(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + switch (adev->pdev->device) { + case 0x6649: + case 0x6650: + case 0x6651: + case 0x6658: + case 0x665C: + case 0x665D: + default: + pi->powertune_defaults = &defaults_bonaire_xt; + break; + case 0x6640: + case 0x6641: + case 0x6646: + case 0x6647: + pi->powertune_defaults = &defaults_saturn_xt; + break; + case 0x67B8: + case 0x67B0: + pi->powertune_defaults = &defaults_hawaii_xt; + break; + case 0x67BA: + case 0x67B1: + pi->powertune_defaults = &defaults_hawaii_pro; + break; + case 0x67A0: + case 0x67A1: + case 0x67A2: + case 0x67A8: + case 0x67A9: + case 0x67AA: + case 0x67B9: + case 0x67BE: + pi->powertune_defaults = &defaults_bonaire_xt; + break; + } + + pi->dte_tj_offset = 0; + + pi->caps_power_containment = true; + pi->caps_cac = false; + pi->caps_sq_ramping = false; + pi->caps_db_ramping = false; + pi->caps_td_ramping = false; + pi->caps_tcp_ramping = false; + + if (pi->caps_power_containment) { + pi->caps_cac = true; + if (adev->asic_type == CHIP_HAWAII) + pi->enable_bapm_feature = false; + else + pi->enable_bapm_feature = true; + pi->enable_tdc_limit_feature = true; + pi->enable_pkg_pwr_tracking_feature = true; + } +} + +static u8 ci_convert_to_vid(u16 vddc) +{ + return (6200 - (vddc * VOLTAGE_SCALE)) / 25; +} + +static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; + u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; + u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; + u32 i; + + if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) + return -EINVAL; + if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8) + return -EINVAL; + if (adev->pm.dpm.dyn_state.cac_leakage_table.count != + adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) + return -EINVAL; + + for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { + lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); + hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); + hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); + } else { + lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); + hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); + } + } + return 0; +} + +static int ci_populate_vddc_vid(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u8 *vid = pi->smc_powertune_table.VddCVid; + u32 i; + + if (pi->vddc_voltage_table.count > 8) + return -EINVAL; + + for (i = 0; i < pi->vddc_voltage_table.count; i++) + vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); + + return 0; +} + +static int ci_populate_svi_load_line(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; + + pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; + pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; + pi->smc_powertune_table.SviLoadLineTrimVddC = 3; + pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; + + return 0; +} + +static int ci_populate_tdc_limit(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; + u16 tdc_limit; + + tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; + pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); + pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = + pt_defaults->tdc_vddc_throttle_release_limit_perc; + pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; + + return 0; +} + +static int ci_populate_dw8(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; + int ret; + + ret = amdgpu_ci_read_smc_sram_dword(adev, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, PmFuseTable) + + offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl), + (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, + pi->sram_end); + if (ret) + return -EINVAL; + else + pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; + + return 0; +} + +static int ci_populate_fuzzy_fan(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || + (adev->pm.dpm.fan.fan_output_sensitivity == 0)) + adev->pm.dpm.fan.fan_output_sensitivity = + adev->pm.dpm.fan.default_fan_output_sensitivity; + + pi->smc_powertune_table.FuzzyFan_PwmSetDelta = + cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity); + + return 0; +} + +static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; + u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; + int i, min, max; + + min = max = hi_vid[0]; + for (i = 0; i < 8; i++) { + if (0 != hi_vid[i]) { + if (min > hi_vid[i]) + min = hi_vid[i]; + if (max < hi_vid[i]) + max = hi_vid[i]; + } + + if (0 != lo_vid[i]) { + if (min > lo_vid[i]) + min = lo_vid[i]; + if (max < lo_vid[i]) + max = lo_vid[i]; + } + } + + if ((min == 0) || (max == 0)) + return -EINVAL; + pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; + pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; + + return 0; +} + +static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; + u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; + struct amdgpu_cac_tdp_table *cac_tdp_table = + adev->pm.dpm.dyn_state.cac_tdp_table; + + hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256; + lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256; + + pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); + pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); + + return 0; +} + +static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; + SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; + struct amdgpu_cac_tdp_table *cac_tdp_table = + adev->pm.dpm.dyn_state.cac_tdp_table; + struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; + int i, j, k; + const u16 *def1; + const u16 *def2; + + dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; + dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; + + dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; + dpm_table->GpuTjMax = + (u8)(pi->thermal_temp_setting.temperature_high / 1000); + dpm_table->GpuTjHyst = 8; + + dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; + + if (ppm) { + dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); + dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); + } else { + dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); + dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); + } + + dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient); + def1 = pt_defaults->bapmti_r; + def2 = pt_defaults->bapmti_rc; + + for (i = 0; i < SMU7_DTE_ITERATIONS; i++) { + for (j = 0; j < SMU7_DTE_SOURCES; j++) { + for (k = 0; k < SMU7_DTE_SINKS; k++) { + dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); + dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); + def1++; + def2++; + } + } + } + + return 0; +} + +static int ci_populate_pm_base(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 pm_fuse_table_offset; + int ret; + + if (pi->caps_power_containment) { + ret = amdgpu_ci_read_smc_sram_dword(adev, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, PmFuseTable), + &pm_fuse_table_offset, pi->sram_end); + if (ret) + return ret; + ret = ci_populate_bapm_vddc_vid_sidd(adev); + if (ret) + return ret; + ret = ci_populate_vddc_vid(adev); + if (ret) + return ret; + ret = ci_populate_svi_load_line(adev); + if (ret) + return ret; + ret = ci_populate_tdc_limit(adev); + if (ret) + return ret; + ret = ci_populate_dw8(adev); + if (ret) + return ret; + ret = ci_populate_fuzzy_fan(adev); + if (ret) + return ret; + ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev); + if (ret) + return ret; + ret = ci_populate_bapm_vddc_base_leakage_sidd(adev); + if (ret) + return ret; + ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset, + (u8 *)&pi->smc_powertune_table, + sizeof(SMU7_Discrete_PmFuses), pi->sram_end); + if (ret) + return ret; + } + + return 0; +} + +static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 data; + + if (pi->caps_sq_ramping) { + data = RREG32_DIDT(ixDIDT_SQ_CTRL0); + if (enable) + data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; + else + data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; + WREG32_DIDT(ixDIDT_SQ_CTRL0, data); + } + + if (pi->caps_db_ramping) { + data = RREG32_DIDT(ixDIDT_DB_CTRL0); + if (enable) + data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; + else + data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; + WREG32_DIDT(ixDIDT_DB_CTRL0, data); + } + + if (pi->caps_td_ramping) { + data = RREG32_DIDT(ixDIDT_TD_CTRL0); + if (enable) + data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; + else + data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; + WREG32_DIDT(ixDIDT_TD_CTRL0, data); + } + + if (pi->caps_tcp_ramping) { + data = RREG32_DIDT(ixDIDT_TCP_CTRL0); + if (enable) + data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; + else + data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; + WREG32_DIDT(ixDIDT_TCP_CTRL0, data); + } +} + +static int ci_program_pt_config_registers(struct amdgpu_device *adev, + const struct ci_pt_config_reg *cac_config_regs) +{ + const struct ci_pt_config_reg *config_regs = cac_config_regs; + u32 data; + u32 cache = 0; + + if (config_regs == NULL) + return -EINVAL; + + while (config_regs->offset != 0xFFFFFFFF) { + if (config_regs->type == CISLANDS_CONFIGREG_CACHE) { + cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); + } else { + switch (config_regs->type) { + case CISLANDS_CONFIGREG_SMC_IND: + data = RREG32_SMC(config_regs->offset); + break; + case CISLANDS_CONFIGREG_DIDT_IND: + data = RREG32_DIDT(config_regs->offset); + break; + default: + data = RREG32(config_regs->offset); + break; + } + + data &= ~config_regs->mask; + data |= ((config_regs->value << config_regs->shift) & config_regs->mask); + data |= cache; + + switch (config_regs->type) { + case CISLANDS_CONFIGREG_SMC_IND: + WREG32_SMC(config_regs->offset, data); + break; + case CISLANDS_CONFIGREG_DIDT_IND: + WREG32_DIDT(config_regs->offset, data); + break; + default: + WREG32(config_regs->offset, data); + break; + } + cache = 0; + } + config_regs++; + } + return 0; +} + +static int ci_enable_didt(struct amdgpu_device *adev, bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + int ret; + + if (pi->caps_sq_ramping || pi->caps_db_ramping || + pi->caps_td_ramping || pi->caps_tcp_ramping) { + gfx_v7_0_enter_rlc_safe_mode(adev); + + if (enable) { + ret = ci_program_pt_config_registers(adev, didt_config_ci); + if (ret) { + gfx_v7_0_exit_rlc_safe_mode(adev); + return ret; + } + } + + ci_do_enable_didt(adev, enable); + + gfx_v7_0_exit_rlc_safe_mode(adev); + } + + return 0; +} + +static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + PPSMC_Result smc_result; + int ret = 0; + + if (enable) { + pi->power_containment_features = 0; + if (pi->caps_power_containment) { + if (pi->enable_bapm_feature) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); + if (smc_result != PPSMC_Result_OK) + ret = -EINVAL; + else + pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; + } + + if (pi->enable_tdc_limit_feature) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable); + if (smc_result != PPSMC_Result_OK) + ret = -EINVAL; + else + pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; + } + + if (pi->enable_pkg_pwr_tracking_feature) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable); + if (smc_result != PPSMC_Result_OK) { + ret = -EINVAL; + } else { + struct amdgpu_cac_tdp_table *cac_tdp_table = + adev->pm.dpm.dyn_state.cac_tdp_table; + u32 default_pwr_limit = + (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); + + pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; + + ci_set_power_limit(adev, default_pwr_limit); + } + } + } + } else { + if (pi->caps_power_containment && pi->power_containment_features) { + if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) + amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable); + + if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) + amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); + + if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) + amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable); + pi->power_containment_features = 0; + } + } + + return ret; +} + +static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + PPSMC_Result smc_result; + int ret = 0; + + if (pi->caps_cac) { + if (enable) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); + if (smc_result != PPSMC_Result_OK) { + ret = -EINVAL; + pi->cac_enabled = false; + } else { + pi->cac_enabled = true; + } + } else if (pi->cac_enabled) { + amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); + pi->cac_enabled = false; + } + } + + return ret; +} + +static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev, + bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + PPSMC_Result smc_result = PPSMC_Result_OK; + + if (pi->thermal_sclk_dpm_enabled) { + if (enable) + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM); + else + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM); + } + + if (smc_result == PPSMC_Result_OK) + return 0; + else + return -EINVAL; +} + +static int ci_power_control_set_level(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct amdgpu_cac_tdp_table *cac_tdp_table = + adev->pm.dpm.dyn_state.cac_tdp_table; + s32 adjust_percent; + s32 target_tdp; + int ret = 0; + bool adjust_polarity = false; /* ??? */ + + if (pi->caps_power_containment) { + adjust_percent = adjust_polarity ? + adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment); + target_tdp = ((100 + adjust_percent) * + (s32)cac_tdp_table->configurable_tdp) / 100; + + ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp); + } + + return ret; +} + +static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (pi->uvd_power_gated == gate) + return; + + pi->uvd_power_gated = gate; + + ci_update_uvd_dpm(adev, gate); +} + +static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev) +{ + u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); + u32 switch_limit = adev->mc.is_gddr5 ? 450 : 300; + + if (vblank_time < switch_limit) + return true; + else + return false; + +} + +static void ci_apply_state_adjust_rules(struct amdgpu_device *adev, + struct amdgpu_ps *rps) +{ + struct ci_ps *ps = ci_get_ps(rps); + struct ci_power_info *pi = ci_get_pi(adev); + struct amdgpu_clock_and_voltage_limits *max_limits; + bool disable_mclk_switching; + u32 sclk, mclk; + int i; + + if (rps->vce_active) { + rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; + rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; + } else { + rps->evclk = 0; + rps->ecclk = 0; + } + + if ((adev->pm.dpm.new_active_crtc_count > 1) || + ci_dpm_vblank_too_short(adev)) + disable_mclk_switching = true; + else + disable_mclk_switching = false; + + if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) + pi->battery_state = true; + else + pi->battery_state = false; + + if (adev->pm.dpm.ac_power) + max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; + else + max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; + + if (adev->pm.dpm.ac_power == false) { + for (i = 0; i < ps->performance_level_count; i++) { + if (ps->performance_levels[i].mclk > max_limits->mclk) + ps->performance_levels[i].mclk = max_limits->mclk; + if (ps->performance_levels[i].sclk > max_limits->sclk) + ps->performance_levels[i].sclk = max_limits->sclk; + } + } + + /* XXX validate the min clocks required for display */ + + if (disable_mclk_switching) { + mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; + sclk = ps->performance_levels[0].sclk; + } else { + mclk = ps->performance_levels[0].mclk; + sclk = ps->performance_levels[0].sclk; + } + + if (rps->vce_active) { + if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) + sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; + if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) + mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; + } + + ps->performance_levels[0].sclk = sclk; + ps->performance_levels[0].mclk = mclk; + + if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) + ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; + + if (disable_mclk_switching) { + if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) + ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; + } else { + if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk) + ps->performance_levels[1].mclk = ps->performance_levels[0].mclk; + } +} + +static int ci_thermal_set_temperature_range(struct amdgpu_device *adev, + int min_temp, int max_temp) +{ + int low_temp = 0 * 1000; + int high_temp = 255 * 1000; + u32 tmp; + + if (low_temp < min_temp) + low_temp = min_temp; + if (high_temp > max_temp) + high_temp = max_temp; + if (high_temp < low_temp) { + DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); + return -EINVAL; + } + + tmp = RREG32_SMC(ixCG_THERMAL_INT); + tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK); + tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) | + ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT; + WREG32_SMC(ixCG_THERMAL_INT, tmp); + +#if 0 + /* XXX: need to figure out how to handle this properly */ + tmp = RREG32_SMC(ixCG_THERMAL_CTRL); + tmp &= DIG_THERM_DPM_MASK; + tmp |= DIG_THERM_DPM(high_temp / 1000); + WREG32_SMC(ixCG_THERMAL_CTRL, tmp); +#endif + + adev->pm.dpm.thermal.min_temp = low_temp; + adev->pm.dpm.thermal.max_temp = high_temp; + return 0; +} + +static int ci_thermal_enable_alert(struct amdgpu_device *adev, + bool enable) +{ + u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT); + PPSMC_Result result; + + if (enable) { + thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK | + CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK); + WREG32_SMC(ixCG_THERMAL_INT, thermal_int); + result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable); + if (result != PPSMC_Result_OK) { + DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); + return -EINVAL; + } + } else { + thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK | + CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; + WREG32_SMC(ixCG_THERMAL_INT, thermal_int); + result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable); + if (result != PPSMC_Result_OK) { + DRM_DEBUG_KMS("Could not disable thermal interrupts.\n"); + return -EINVAL; + } + } + + return 0; +} + +static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 tmp; + + if (pi->fan_ctrl_is_in_default_mode) { + tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) + >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; + pi->fan_ctrl_default_mode = tmp; + tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) + >> CG_FDO_CTRL2__TMIN__SHIFT; + pi->t_min = tmp; + pi->fan_ctrl_is_in_default_mode = false; + } + + tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; + tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT; + WREG32_SMC(ixCG_FDO_CTRL2, tmp); + + tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; + tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; + WREG32_SMC(ixCG_FDO_CTRL2, tmp); +} + +static int ci_thermal_setup_fan_table(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; + u32 duty100; + u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; + u16 fdo_min, slope1, slope2; + u32 reference_clock, tmp; + int ret; + u64 tmp64; + + if (!pi->fan_table_start) { + adev->pm.dpm.fan.ucode_fan_control = false; + return 0; + } + + duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) + >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; + + if (duty100 == 0) { + adev->pm.dpm.fan.ucode_fan_control = false; + return 0; + } + + tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; + do_div(tmp64, 10000); + fdo_min = (u16)tmp64; + + t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; + t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; + + pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; + pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; + + slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); + slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); + + fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); + fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); + fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); + + fan_table.Slope1 = cpu_to_be16(slope1); + fan_table.Slope2 = cpu_to_be16(slope2); + + fan_table.FdoMin = cpu_to_be16(fdo_min); + + fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst); + + fan_table.HystUp = cpu_to_be16(1); + + fan_table.HystSlope = cpu_to_be16(1); + + fan_table.TempRespLim = cpu_to_be16(5); + + reference_clock = amdgpu_asic_get_xclk(adev); + + fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * + reference_clock) / 1600); + + fan_table.FdoMax = cpu_to_be16((u16)duty100); + + tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) + >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT; + fan_table.TempSrc = (uint8_t)tmp; + + ret = amdgpu_ci_copy_bytes_to_smc(adev, + pi->fan_table_start, + (u8 *)(&fan_table), + sizeof(fan_table), + pi->sram_end); + + if (ret) { + DRM_ERROR("Failed to load fan table to the SMC."); + adev->pm.dpm.fan.ucode_fan_control = false; + } + + return 0; +} + +static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + PPSMC_Result ret; + + if (pi->caps_od_fuzzy_fan_control_support) { + ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_StartFanControl, + FAN_CONTROL_FUZZY); + if (ret != PPSMC_Result_OK) + return -EINVAL; + ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetFanPwmMax, + adev->pm.dpm.fan.default_max_fan_pwm); + if (ret != PPSMC_Result_OK) + return -EINVAL; + } else { + ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_StartFanControl, + FAN_CONTROL_TABLE); + if (ret != PPSMC_Result_OK) + return -EINVAL; + } + + pi->fan_is_controlled_by_smc = true; + return 0; +} + + +static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) +{ + PPSMC_Result ret; + struct ci_power_info *pi = ci_get_pi(adev); + + ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl); + if (ret == PPSMC_Result_OK) { + pi->fan_is_controlled_by_smc = false; + return 0; + } else { + return -EINVAL; + } +} + +static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev, + u32 *speed) +{ + u32 duty, duty100; + u64 tmp64; + + if (adev->pm.no_fan) + return -ENOENT; + + duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) + >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; + duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK) + >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT; + + if (duty100 == 0) + return -EINVAL; + + tmp64 = (u64)duty * 100; + do_div(tmp64, duty100); + *speed = (u32)tmp64; + + if (*speed > 100) + *speed = 100; + + return 0; +} + +static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev, + u32 speed) +{ + u32 tmp; + u32 duty, duty100; + u64 tmp64; + struct ci_power_info *pi = ci_get_pi(adev); + + if (adev->pm.no_fan) + return -ENOENT; + + if (pi->fan_is_controlled_by_smc) + return -EINVAL; + + if (speed > 100) + return -EINVAL; + + duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) + >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; + + if (duty100 == 0) + return -EINVAL; + + tmp64 = (u64)speed * duty100; + do_div(tmp64, 100); + duty = (u32)tmp64; + + tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK; + tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT; + WREG32_SMC(ixCG_FDO_CTRL0, tmp); + + return 0; +} + +static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode) +{ + if (mode) { + /* stop auto-manage */ + if (adev->pm.dpm.fan.ucode_fan_control) + ci_fan_ctrl_stop_smc_fan_control(adev); + ci_fan_ctrl_set_static_mode(adev, mode); + } else { + /* restart auto-manage */ + if (adev->pm.dpm.fan.ucode_fan_control) + ci_thermal_start_smc_fan_control(adev); + else + ci_fan_ctrl_set_default_mode(adev); + } +} + +static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 tmp; + + if (pi->fan_is_controlled_by_smc) + return 0; + + tmp = RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK; + return (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT); +} + +#if 0 +static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev, + u32 *speed) +{ + u32 tach_period; + u32 xclk = amdgpu_asic_get_xclk(adev); + + if (adev->pm.no_fan) + return -ENOENT; + + if (adev->pm.fan_pulses_per_revolution == 0) + return -ENOENT; + + tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK) + >> CG_TACH_STATUS__TACH_PERIOD__SHIFT; + if (tach_period == 0) + return -ENOENT; + + *speed = 60 * xclk * 10000 / tach_period; + + return 0; +} + +static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev, + u32 speed) +{ + u32 tach_period, tmp; + u32 xclk = amdgpu_asic_get_xclk(adev); + + if (adev->pm.no_fan) + return -ENOENT; + + if (adev->pm.fan_pulses_per_revolution == 0) + return -ENOENT; + + if ((speed < adev->pm.fan_min_rpm) || + (speed > adev->pm.fan_max_rpm)) + return -EINVAL; + + if (adev->pm.dpm.fan.ucode_fan_control) + ci_fan_ctrl_stop_smc_fan_control(adev); + + tach_period = 60 * xclk * 10000 / (8 * speed); + tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK; + tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT; + WREG32_SMC(CG_TACH_CTRL, tmp); + + ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM); + + return 0; +} +#endif + +static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 tmp; + + if (!pi->fan_ctrl_is_in_default_mode) { + tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; + tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; + WREG32_SMC(ixCG_FDO_CTRL2, tmp); + + tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; + tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT; + WREG32_SMC(ixCG_FDO_CTRL2, tmp); + pi->fan_ctrl_is_in_default_mode = true; + } +} + +static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev) +{ + if (adev->pm.dpm.fan.ucode_fan_control) { + ci_fan_ctrl_start_smc_fan_control(adev); + ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC); + } +} + +static void ci_thermal_initialize(struct amdgpu_device *adev) +{ + u32 tmp; + + if (adev->pm.fan_pulses_per_revolution) { + tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK; + tmp |= (adev->pm.fan_pulses_per_revolution - 1) + << CG_TACH_CTRL__EDGE_PER_REV__SHIFT; + WREG32_SMC(ixCG_TACH_CTRL, tmp); + } + + tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK; + tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT; + WREG32_SMC(ixCG_FDO_CTRL2, tmp); +} + +static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev) +{ + int ret; + + ci_thermal_initialize(adev); + ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX); + if (ret) + return ret; + ret = ci_thermal_enable_alert(adev, true); + if (ret) + return ret; + if (adev->pm.dpm.fan.ucode_fan_control) { + ret = ci_thermal_setup_fan_table(adev); + if (ret) + return ret; + ci_thermal_start_smc_fan_control(adev); + } + + return 0; +} + +static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev) +{ + if (!adev->pm.no_fan) + ci_fan_ctrl_set_default_mode(adev); +} + +#if 0 +static int ci_read_smc_soft_register(struct amdgpu_device *adev, + u16 reg_offset, u32 *value) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + return amdgpu_ci_read_smc_sram_dword(adev, + pi->soft_regs_start + reg_offset, + value, pi->sram_end); +} +#endif + +static int ci_write_smc_soft_register(struct amdgpu_device *adev, + u16 reg_offset, u32 value) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + return amdgpu_ci_write_smc_sram_dword(adev, + pi->soft_regs_start + reg_offset, + value, pi->sram_end); +} + +static void ci_init_fps_limits(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + SMU7_Discrete_DpmTable *table = &pi->smc_state_table; + + if (pi->caps_fps) { + u16 tmp; + + tmp = 45; + table->FpsHighT = cpu_to_be16(tmp); + + tmp = 30; + table->FpsLowT = cpu_to_be16(tmp); + } +} + +static int ci_update_sclk_t(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + int ret = 0; + u32 low_sclk_interrupt_t = 0; + + if (pi->caps_sclk_throttle_low_notification) { + low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); + + ret = amdgpu_ci_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT), + (u8 *)&low_sclk_interrupt_t, + sizeof(u32), pi->sram_end); + + } + + return ret; +} + +static void ci_get_leakage_voltages(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u16 leakage_id, virtual_voltage_id; + u16 vddc, vddci; + int i; + + pi->vddc_leakage.count = 0; + pi->vddci_leakage.count = 0; + + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { + for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { + virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; + if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0) + continue; + if (vddc != 0 && vddc != virtual_voltage_id) { + pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; + pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; + pi->vddc_leakage.count++; + } + } + } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) { + for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { + virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; + if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci, + virtual_voltage_id, + leakage_id) == 0) { + if (vddc != 0 && vddc != virtual_voltage_id) { + pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; + pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; + pi->vddc_leakage.count++; + } + if (vddci != 0 && vddci != virtual_voltage_id) { + pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; + pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; + pi->vddci_leakage.count++; + } + } + } + } +} + +static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) +{ + struct ci_power_info *pi = ci_get_pi(adev); + bool want_thermal_protection; + enum amdgpu_dpm_event_src dpm_event_src; + u32 tmp; + + switch (sources) { + case 0: + default: + want_thermal_protection = false; + break; + case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL): + want_thermal_protection = true; + dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL; + break; + case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL): + want_thermal_protection = true; + dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL; + break; + case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | + (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)): + want_thermal_protection = true; + dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; + break; + } + + if (want_thermal_protection) { +#if 0 + /* XXX: need to figure out how to handle this properly */ + tmp = RREG32_SMC(ixCG_THERMAL_CTRL); + tmp &= DPM_EVENT_SRC_MASK; + tmp |= DPM_EVENT_SRC(dpm_event_src); + WREG32_SMC(ixCG_THERMAL_CTRL, tmp); +#endif + + tmp = RREG32_SMC(ixGENERAL_PWRMGT); + if (pi->thermal_protection) + tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK; + else + tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK; + WREG32_SMC(ixGENERAL_PWRMGT, tmp); + } else { + tmp = RREG32_SMC(ixGENERAL_PWRMGT); + tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK; + WREG32_SMC(ixGENERAL_PWRMGT, tmp); + } +} + +static void ci_enable_auto_throttle_source(struct amdgpu_device *adev, + enum amdgpu_dpm_auto_throttle_src source, + bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (enable) { + if (!(pi->active_auto_throttle_sources & (1 << source))) { + pi->active_auto_throttle_sources |= 1 << source; + ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); + } + } else { + if (pi->active_auto_throttle_sources & (1 << source)) { + pi->active_auto_throttle_sources &= ~(1 << source); + ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); + } + } +} + +static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev) +{ + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) + amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt); +} + +static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + PPSMC_Result smc_result; + + if (!pi->need_update_smu7_dpm_table) + return 0; + + if ((!pi->sclk_dpm_key_disabled) && + (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + if ((!pi->mclk_dpm_key_disabled) && + (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + pi->need_update_smu7_dpm_table = 0; + return 0; +} + +static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + PPSMC_Result smc_result; + + if (enable) { + if (!pi->sclk_dpm_key_disabled) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + if (!pi->mclk_dpm_key_disabled) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + + WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK, + ~MC_SEQ_CNTL_3__CAC_EN_MASK); + + WREG32_SMC(ixLCAC_MC0_CNTL, 0x05); + WREG32_SMC(ixLCAC_MC1_CNTL, 0x05); + WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005); + + udelay(10); + + WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005); + WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005); + WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005); + } + } else { + if (!pi->sclk_dpm_key_disabled) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + if (!pi->mclk_dpm_key_disabled) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + } + + return 0; +} + +static int ci_start_dpm(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + PPSMC_Result smc_result; + int ret; + u32 tmp; + + tmp = RREG32_SMC(ixGENERAL_PWRMGT); + tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK; + WREG32_SMC(ixGENERAL_PWRMGT, tmp); + + tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL); + tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK; + WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp); + + ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000); + + WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK); + + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + + ret = ci_enable_sclk_mclk_dpm(adev, true); + if (ret) + return ret; + + if (!pi->pcie_dpm_key_disabled) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + return 0; +} + +static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + PPSMC_Result smc_result; + + if (!pi->need_update_smu7_dpm_table) + return 0; + + if ((!pi->sclk_dpm_key_disabled) && + (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + if ((!pi->mclk_dpm_key_disabled) && + (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + return 0; +} + +static int ci_stop_dpm(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + PPSMC_Result smc_result; + int ret; + u32 tmp; + + tmp = RREG32_SMC(ixGENERAL_PWRMGT); + tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK; + WREG32_SMC(ixGENERAL_PWRMGT, tmp); + + tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL); + tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK; + WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp); + + if (!pi->pcie_dpm_key_disabled) { + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + ret = ci_enable_sclk_mclk_dpm(adev, false); + if (ret) + return ret; + + smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + + return 0; +} + +static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable) +{ + u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL); + + if (enable) + tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK; + else + tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK; + WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp); +} + +#if 0 +static int ci_notify_hw_of_power_source(struct amdgpu_device *adev, + bool ac_power) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct amdgpu_cac_tdp_table *cac_tdp_table = + adev->pm.dpm.dyn_state.cac_tdp_table; + u32 power_limit; + + if (ac_power) + power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); + else + power_limit = (u32)(cac_tdp_table->battery_power_limit * 256); + + ci_set_power_limit(adev, power_limit); + + if (pi->caps_automatic_dc_transition) { + if (ac_power) + amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC); + else + amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp); + } + + return 0; +} +#endif + +static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, + PPSMC_Msg msg, u32 parameter) +{ + WREG32(mmSMC_MSG_ARG_0, parameter); + return amdgpu_ci_send_msg_to_smc(adev, msg); +} + +static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev, + PPSMC_Msg msg, u32 *parameter) +{ + PPSMC_Result smc_result; + + smc_result = amdgpu_ci_send_msg_to_smc(adev, msg); + + if ((smc_result == PPSMC_Result_OK) && parameter) + *parameter = RREG32(mmSMC_MSG_ARG_0); + + return smc_result; +} + +static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (!pi->sclk_dpm_key_disabled) { + PPSMC_Result smc_result = + amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + return 0; +} + +static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (!pi->mclk_dpm_key_disabled) { + PPSMC_Result smc_result = + amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + return 0; +} + +static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (!pi->pcie_dpm_key_disabled) { + PPSMC_Result smc_result = + amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + return 0; +} + +static int ci_set_power_limit(struct amdgpu_device *adev, u32 n) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { + PPSMC_Result smc_result = + amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + + return 0; +} + +static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev, + u32 target_tdp) +{ + PPSMC_Result smc_result = + amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + return 0; +} + +#if 0 +static int ci_set_boot_state(struct amdgpu_device *adev) +{ + return ci_enable_sclk_mclk_dpm(adev, false); +} +#endif + +static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev) +{ + u32 sclk_freq; + PPSMC_Result smc_result = + amdgpu_ci_send_msg_to_smc_return_parameter(adev, + PPSMC_MSG_API_GetSclkFrequency, + &sclk_freq); + if (smc_result != PPSMC_Result_OK) + sclk_freq = 0; + + return sclk_freq; +} + +static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev) +{ + u32 mclk_freq; + PPSMC_Result smc_result = + amdgpu_ci_send_msg_to_smc_return_parameter(adev, + PPSMC_MSG_API_GetMclkFrequency, + &mclk_freq); + if (smc_result != PPSMC_Result_OK) + mclk_freq = 0; + + return mclk_freq; +} + +static void ci_dpm_start_smc(struct amdgpu_device *adev) +{ + int i; + + amdgpu_ci_program_jump_on_start(adev); + amdgpu_ci_start_smc_clock(adev); + amdgpu_ci_start_smc(adev); + for (i = 0; i < adev->usec_timeout; i++) { + if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) + break; + } +} + +static void ci_dpm_stop_smc(struct amdgpu_device *adev) +{ + amdgpu_ci_reset_smc(adev); + amdgpu_ci_stop_smc_clock(adev); +} + +static int ci_process_firmware_header(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 tmp; + int ret; + + ret = amdgpu_ci_read_smc_sram_dword(adev, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, DpmTable), + &tmp, pi->sram_end); + if (ret) + return ret; + + pi->dpm_table_start = tmp; + + ret = amdgpu_ci_read_smc_sram_dword(adev, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, SoftRegisters), + &tmp, pi->sram_end); + if (ret) + return ret; + + pi->soft_regs_start = tmp; + + ret = amdgpu_ci_read_smc_sram_dword(adev, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, mcRegisterTable), + &tmp, pi->sram_end); + if (ret) + return ret; + + pi->mc_reg_table_start = tmp; + + ret = amdgpu_ci_read_smc_sram_dword(adev, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, FanTable), + &tmp, pi->sram_end); + if (ret) + return ret; + + pi->fan_table_start = tmp; + + ret = amdgpu_ci_read_smc_sram_dword(adev, + SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, mcArbDramTimingTable), + &tmp, pi->sram_end); + if (ret) + return ret; + + pi->arb_table_start = tmp; + + return 0; +} + +static void ci_read_clock_registers(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + pi->clock_registers.cg_spll_func_cntl = + RREG32_SMC(ixCG_SPLL_FUNC_CNTL); + pi->clock_registers.cg_spll_func_cntl_2 = + RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2); + pi->clock_registers.cg_spll_func_cntl_3 = + RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3); + pi->clock_registers.cg_spll_func_cntl_4 = + RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4); + pi->clock_registers.cg_spll_spread_spectrum = + RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM); + pi->clock_registers.cg_spll_spread_spectrum_2 = + RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2); + pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL); + pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL); + pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL); + pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL); + pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL); + pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1); + pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2); + pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1); + pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2); +} + +static void ci_init_sclk_t(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + pi->low_sclk_interrupt_t = 0; +} + +static void ci_enable_thermal_protection(struct amdgpu_device *adev, + bool enable) +{ + u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT); + + if (enable) + tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK; + else + tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK; + WREG32_SMC(ixGENERAL_PWRMGT, tmp); +} + +static void ci_enable_acpi_power_management(struct amdgpu_device *adev) +{ + u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT); + + tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK; + + WREG32_SMC(ixGENERAL_PWRMGT, tmp); +} + +#if 0 +static int ci_enter_ulp_state(struct amdgpu_device *adev) +{ + + WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); + + udelay(25000); + + return 0; +} + +static int ci_exit_ulp_state(struct amdgpu_device *adev) +{ + int i; + + WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); + + udelay(7000); + + for (i = 0; i < adev->usec_timeout; i++) { + if (RREG32(mmSMC_RESP_0) == 1) + break; + udelay(1000); + } + + return 0; +} +#endif + +static int ci_notify_smc_display_change(struct amdgpu_device *adev, + bool has_display) +{ + PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; + + return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; +} + +static int ci_enable_ds_master_switch(struct amdgpu_device *adev, + bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (enable) { + if (pi->caps_sclk_ds) { + if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK) + return -EINVAL; + } else { + if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) + return -EINVAL; + } + } else { + if (pi->caps_sclk_ds) { + if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) + return -EINVAL; + } + } + + return 0; +} + +static void ci_program_display_gap(struct amdgpu_device *adev) +{ + u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL); + u32 pre_vbi_time_in_us; + u32 frame_time_in_us; + u32 ref_clock = adev->clock.spll.reference_freq; + u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev); + u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); + + tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK; + if (adev->pm.dpm.new_active_crtc_count > 0) + tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT); + else + tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT); + WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp); + + if (refresh_rate == 0) + refresh_rate = 60; + if (vblank_time == 0xffffffff) + vblank_time = 500; + frame_time_in_us = 1000000 / refresh_rate; + pre_vbi_time_in_us = + frame_time_in_us - 200 - vblank_time; + tmp = pre_vbi_time_in_us * (ref_clock / 100); + + WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp); + ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64); + ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); + + + ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1)); + +} + +static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 tmp; + + if (enable) { + if (pi->caps_sclk_ss_support) { + tmp = RREG32_SMC(ixGENERAL_PWRMGT); + tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK; + WREG32_SMC(ixGENERAL_PWRMGT, tmp); + } + } else { + tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM); + tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK; + WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp); + + tmp = RREG32_SMC(ixGENERAL_PWRMGT); + tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK; + WREG32_SMC(ixGENERAL_PWRMGT, tmp); + } +} + +static void ci_program_sstp(struct amdgpu_device *adev) +{ + WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER, + ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) | + (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT))); +} + +static void ci_enable_display_gap(struct amdgpu_device *adev) +{ + u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL); + + tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK | + CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK); + tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) | + (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT)); + + WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp); +} + +static void ci_program_vc(struct amdgpu_device *adev) +{ + u32 tmp; + + tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL); + tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK); + WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp); + + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7); +} + +static void ci_clear_vc(struct amdgpu_device *adev) +{ + u32 tmp; + + tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL); + tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK); + WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp); + + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0); + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0); +} + +static int ci_upload_firmware(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + int i, ret; + + for (i = 0; i < adev->usec_timeout; i++) { + if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK) + break; + } + WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1); + + amdgpu_ci_stop_smc_clock(adev); + amdgpu_ci_reset_smc(adev); + + ret = amdgpu_ci_load_smc_ucode(adev, pi->sram_end); + + return ret; + +} + +static int ci_get_svi2_voltage_table(struct amdgpu_device *adev, + struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table, + struct atom_voltage_table *voltage_table) +{ + u32 i; + + if (voltage_dependency_table == NULL) + return -EINVAL; + + voltage_table->mask_low = 0; + voltage_table->phase_delay = 0; + + voltage_table->count = voltage_dependency_table->count; + for (i = 0; i < voltage_table->count; i++) { + voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; + voltage_table->entries[i].smio_low = 0; + } + + return 0; +} + +static int ci_construct_voltage_tables(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + int ret; + + if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { + ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, + VOLTAGE_OBJ_GPIO_LUT, + &pi->vddc_voltage_table); + if (ret) + return ret; + } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { + ret = ci_get_svi2_voltage_table(adev, + &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, + &pi->vddc_voltage_table); + if (ret) + return ret; + } + + if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) + ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC, + &pi->vddc_voltage_table); + + if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { + ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI, + VOLTAGE_OBJ_GPIO_LUT, + &pi->vddci_voltage_table); + if (ret) + return ret; + } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { + ret = ci_get_svi2_voltage_table(adev, + &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, + &pi->vddci_voltage_table); + if (ret) + return ret; + } + + if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) + ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI, + &pi->vddci_voltage_table); + + if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { + ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC, + VOLTAGE_OBJ_GPIO_LUT, + &pi->mvdd_voltage_table); + if (ret) + return ret; + } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { + ret = ci_get_svi2_voltage_table(adev, + &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, + &pi->mvdd_voltage_table); + if (ret) + return ret; + } + + if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) + ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD, + &pi->mvdd_voltage_table); + + return 0; +} + +static void ci_populate_smc_voltage_table(struct amdgpu_device *adev, + struct atom_voltage_table_entry *voltage_table, + SMU7_Discrete_VoltageLevel *smc_voltage_table) +{ + int ret; + + ret = ci_get_std_voltage_value_sidd(adev, voltage_table, + &smc_voltage_table->StdVoltageHiSidd, + &smc_voltage_table->StdVoltageLoSidd); + + if (ret) { + smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE; + smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE; + } + + smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE); + smc_voltage_table->StdVoltageHiSidd = + cpu_to_be16(smc_voltage_table->StdVoltageHiSidd); + smc_voltage_table->StdVoltageLoSidd = + cpu_to_be16(smc_voltage_table->StdVoltageLoSidd); +} + +static int ci_populate_smc_vddc_table(struct amdgpu_device *adev, + SMU7_Discrete_DpmTable *table) +{ + struct ci_power_info *pi = ci_get_pi(adev); + unsigned int count; + + table->VddcLevelCount = pi->vddc_voltage_table.count; + for (count = 0; count < table->VddcLevelCount; count++) { + ci_populate_smc_voltage_table(adev, + &pi->vddc_voltage_table.entries[count], + &table->VddcLevel[count]); + + if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) + table->VddcLevel[count].Smio |= + pi->vddc_voltage_table.entries[count].smio_low; + else + table->VddcLevel[count].Smio = 0; + } + table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); + + return 0; +} + +static int ci_populate_smc_vddci_table(struct amdgpu_device *adev, + SMU7_Discrete_DpmTable *table) +{ + unsigned int count; + struct ci_power_info *pi = ci_get_pi(adev); + + table->VddciLevelCount = pi->vddci_voltage_table.count; + for (count = 0; count < table->VddciLevelCount; count++) { + ci_populate_smc_voltage_table(adev, + &pi->vddci_voltage_table.entries[count], + &table->VddciLevel[count]); + + if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) + table->VddciLevel[count].Smio |= + pi->vddci_voltage_table.entries[count].smio_low; + else + table->VddciLevel[count].Smio = 0; + } + table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); + + return 0; +} + +static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev, + SMU7_Discrete_DpmTable *table) +{ + struct ci_power_info *pi = ci_get_pi(adev); + unsigned int count; + + table->MvddLevelCount = pi->mvdd_voltage_table.count; + for (count = 0; count < table->MvddLevelCount; count++) { + ci_populate_smc_voltage_table(adev, + &pi->mvdd_voltage_table.entries[count], + &table->MvddLevel[count]); + + if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) + table->MvddLevel[count].Smio |= + pi->mvdd_voltage_table.entries[count].smio_low; + else + table->MvddLevel[count].Smio = 0; + } + table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); + + return 0; +} + +static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev, + SMU7_Discrete_DpmTable *table) +{ + int ret; + + ret = ci_populate_smc_vddc_table(adev, table); + if (ret) + return ret; + + ret = ci_populate_smc_vddci_table(adev, table); + if (ret) + return ret; + + ret = ci_populate_smc_mvdd_table(adev, table); + if (ret) + return ret; + + return 0; +} + +static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, + SMU7_Discrete_VoltageLevel *voltage) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 i = 0; + + if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { + for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { + if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { + voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; + break; + } + } + + if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) + return -EINVAL; + } + + return -EINVAL; +} + +static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev, + struct atom_voltage_table_entry *voltage_table, + u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd) +{ + u16 v_index, idx; + bool voltage_found = false; + *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE; + *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE; + + if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) + return -EINVAL; + + if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { + for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { + if (voltage_table->value == + adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { + voltage_found = true; + if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) + idx = v_index; + else + idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1; + *std_voltage_lo_sidd = + adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; + *std_voltage_hi_sidd = + adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; + break; + } + } + + if (!voltage_found) { + for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { + if (voltage_table->value <= + adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { + voltage_found = true; + if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) + idx = v_index; + else + idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1; + *std_voltage_lo_sidd = + adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; + *std_voltage_hi_sidd = + adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; + break; + } + } + } + } + + return 0; +} + +static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev, + const struct amdgpu_phase_shedding_limits_table *limits, + u32 sclk, + u32 *phase_shedding) +{ + unsigned int i; + + *phase_shedding = 1; + + for (i = 0; i < limits->count; i++) { + if (sclk < limits->entries[i].sclk) { + *phase_shedding = i; + break; + } + } +} + +static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev, + const struct amdgpu_phase_shedding_limits_table *limits, + u32 mclk, + u32 *phase_shedding) +{ + unsigned int i; + + *phase_shedding = 1; + + for (i = 0; i < limits->count; i++) { + if (mclk < limits->entries[i].mclk) { + *phase_shedding = i; + break; + } + } +} + +static int ci_init_arb_table_index(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 tmp; + int ret; + + ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start, + &tmp, pi->sram_end); + if (ret) + return ret; + + tmp &= 0x00FFFFFF; + tmp |= MC_CG_ARB_FREQ_F1 << 24; + + return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start, + tmp, pi->sram_end); +} + +static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev, + struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table, + u32 clock, u32 *voltage) +{ + u32 i = 0; + + if (allowed_clock_voltage_table->count == 0) + return -EINVAL; + + for (i = 0; i < allowed_clock_voltage_table->count; i++) { + if (allowed_clock_voltage_table->entries[i].clk >= clock) { + *voltage = allowed_clock_voltage_table->entries[i].v; + return 0; + } + } + + *voltage = allowed_clock_voltage_table->entries[i-1].v; + + return 0; +} + +static u8 ci_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, + u32 sclk, u32 min_sclk_in_sr) +{ + u32 i; + u32 tmp; + u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ? + min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK; + + if (sclk < min) + return 0; + + for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { + tmp = sclk / (1 << i); + if (tmp >= min || i == 0) + break; + } + + return (u8)i; +} + +static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) +{ + return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); +} + +static int ci_reset_to_default(struct amdgpu_device *adev) +{ + return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? + 0 : -EINVAL; +} + +static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev) +{ + u32 tmp; + + tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8; + + if (tmp == MC_CG_ARB_FREQ_F0) + return 0; + + return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0); +} + +static void ci_register_patching_mc_arb(struct amdgpu_device *adev, + const u32 engine_clock, + const u32 memory_clock, + u32 *dram_timimg2) +{ + bool patch; + u32 tmp, tmp2; + + tmp = RREG32(mmMC_SEQ_MISC0); + patch = ((tmp & 0x0000f00) == 0x300) ? true : false; + + if (patch && + ((adev->pdev->device == 0x67B0) || + (adev->pdev->device == 0x67B1))) { + if ((memory_clock > 100000) && (memory_clock <= 125000)) { + tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; + *dram_timimg2 &= ~0x00ff0000; + *dram_timimg2 |= tmp2 << 16; + } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { + tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; + *dram_timimg2 &= ~0x00ff0000; + *dram_timimg2 |= tmp2 << 16; + } + } +} + +static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev, + u32 sclk, + u32 mclk, + SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs) +{ + u32 dram_timing; + u32 dram_timing2; + u32 burst_time; + + amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk); + + dram_timing = RREG32(mmMC_ARB_DRAM_TIMING); + dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2); + burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK; + + ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2); + + arb_regs->McArbDramTiming = cpu_to_be32(dram_timing); + arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2); + arb_regs->McArbBurstTime = (u8)burst_time; + + return 0; +} + +static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + SMU7_Discrete_MCArbDramTimingTable arb_regs; + u32 i, j; + int ret = 0; + + memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable)); + + for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { + for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { + ret = ci_populate_memory_timing_parameters(adev, + pi->dpm_table.sclk_table.dpm_levels[i].value, + pi->dpm_table.mclk_table.dpm_levels[j].value, + &arb_regs.entries[i][j]); + if (ret) + break; + } + } + + if (ret == 0) + ret = amdgpu_ci_copy_bytes_to_smc(adev, + pi->arb_table_start, + (u8 *)&arb_regs, + sizeof(SMU7_Discrete_MCArbDramTimingTable), + pi->sram_end); + + return ret; +} + +static int ci_program_memory_timing_parameters(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (pi->need_update_smu7_dpm_table == 0) + return 0; + + return ci_do_program_memory_timing_parameters(adev); +} + +static void ci_populate_smc_initial_state(struct amdgpu_device *adev, + struct amdgpu_ps *amdgpu_boot_state) +{ + struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state); + struct ci_power_info *pi = ci_get_pi(adev); + u32 level = 0; + + for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { + if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= + boot_state->performance_levels[0].sclk) { + pi->smc_state_table.GraphicsBootLevel = level; + break; + } + } + + for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { + if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= + boot_state->performance_levels[0].mclk) { + pi->smc_state_table.MemoryBootLevel = level; + break; + } + } +} + +static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) +{ + u32 i; + u32 mask_value = 0; + + for (i = dpm_table->count; i > 0; i--) { + mask_value = mask_value << 1; + if (dpm_table->dpm_levels[i-1].enabled) + mask_value |= 0x1; + else + mask_value &= 0xFFFFFFFE; + } + + return mask_value; +} + +static void ci_populate_smc_link_level(struct amdgpu_device *adev, + SMU7_Discrete_DpmTable *table) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_dpm_table *dpm_table = &pi->dpm_table; + u32 i; + + for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { + table->LinkLevel[i].PcieGenSpeed = + (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; + table->LinkLevel[i].PcieLaneCount = + amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); + table->LinkLevel[i].EnabledForActivity = 1; + table->LinkLevel[i].DownT = cpu_to_be32(5); + table->LinkLevel[i].UpT = cpu_to_be32(30); + } + + pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; + pi->dpm_level_enable_mask.pcie_dpm_enable_mask = + ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); +} + +static int ci_populate_smc_uvd_level(struct amdgpu_device *adev, + SMU7_Discrete_DpmTable *table) +{ + u32 count; + struct atom_clock_dividers dividers; + int ret = -EINVAL; + + table->UvdLevelCount = + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; + + for (count = 0; count < table->UvdLevelCount; count++) { + table->UvdLevel[count].VclkFrequency = + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; + table->UvdLevel[count].DclkFrequency = + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; + table->UvdLevel[count].MinVddc = + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; + table->UvdLevel[count].MinVddcPhases = 1; + + ret = amdgpu_atombios_get_clock_dividers(adev, + COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + table->UvdLevel[count].VclkFrequency, false, ÷rs); + if (ret) + return ret; + + table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; + + ret = amdgpu_atombios_get_clock_dividers(adev, + COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + table->UvdLevel[count].DclkFrequency, false, ÷rs); + if (ret) + return ret; + + table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; + + table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); + table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); + table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); + } + + return ret; +} + +static int ci_populate_smc_vce_level(struct amdgpu_device *adev, + SMU7_Discrete_DpmTable *table) +{ + u32 count; + struct atom_clock_dividers dividers; + int ret = -EINVAL; + + table->VceLevelCount = + adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; + + for (count = 0; count < table->VceLevelCount; count++) { + table->VceLevel[count].Frequency = + adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; + table->VceLevel[count].MinVoltage = + (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; + table->VceLevel[count].MinPhases = 1; + + ret = amdgpu_atombios_get_clock_dividers(adev, + COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + table->VceLevel[count].Frequency, false, ÷rs); + if (ret) + return ret; + + table->VceLevel[count].Divider = (u8)dividers.post_divider; + + table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); + table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); + } + + return ret; + +} + +static int ci_populate_smc_acp_level(struct amdgpu_device *adev, + SMU7_Discrete_DpmTable *table) +{ + u32 count; + struct atom_clock_dividers dividers; + int ret = -EINVAL; + + table->AcpLevelCount = (u8) + (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); + + for (count = 0; count < table->AcpLevelCount; count++) { + table->AcpLevel[count].Frequency = + adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; + table->AcpLevel[count].MinVoltage = + adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; + table->AcpLevel[count].MinPhases = 1; + + ret = amdgpu_atombios_get_clock_dividers(adev, + COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + table->AcpLevel[count].Frequency, false, ÷rs); + if (ret) + return ret; + + table->AcpLevel[count].Divider = (u8)dividers.post_divider; + + table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); + table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); + } + + return ret; +} + +static int ci_populate_smc_samu_level(struct amdgpu_device *adev, + SMU7_Discrete_DpmTable *table) +{ + u32 count; + struct atom_clock_dividers dividers; + int ret = -EINVAL; + + table->SamuLevelCount = + adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; + + for (count = 0; count < table->SamuLevelCount; count++) { + table->SamuLevel[count].Frequency = + adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; + table->SamuLevel[count].MinVoltage = + adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; + table->SamuLevel[count].MinPhases = 1; + + ret = amdgpu_atombios_get_clock_dividers(adev, + COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + table->SamuLevel[count].Frequency, false, ÷rs); + if (ret) + return ret; + + table->SamuLevel[count].Divider = (u8)dividers.post_divider; + + table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); + table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); + } + + return ret; +} + +static int ci_calculate_mclk_params(struct amdgpu_device *adev, + u32 memory_clock, + SMU7_Discrete_MemoryLevel *mclk, + bool strobe_mode, + bool dll_state_on) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 dll_cntl = pi->clock_registers.dll_cntl; + u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; + u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; + u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; + u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; + u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; + u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; + u32 mpll_ss1 = pi->clock_registers.mpll_ss1; + u32 mpll_ss2 = pi->clock_registers.mpll_ss2; + struct atom_mpll_param mpll_param; + int ret; + + ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param); + if (ret) + return ret; + + mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK; + mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT); + + mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK | + MPLL_FUNC_CNTL_1__VCO_MODE_MASK); + mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT | + (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) | + (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT); + + mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK; + mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT); + + if (adev->mc.is_gddr5) { + mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK | + MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK); + mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) | + (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT); + } + + if (pi->caps_mclk_ss_support) { + struct amdgpu_atom_ss ss; + u32 freq_nom; + u32 tmp; + u32 reference_clock = adev->clock.mpll.reference_freq; + + if (mpll_param.qdr == 1) + freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); + else + freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); + + tmp = (freq_nom / reference_clock); + tmp = tmp * tmp; + if (amdgpu_atombios_get_asic_ss_info(adev, &ss, + ASIC_INTERNAL_MEMORY_SS, freq_nom)) { + u32 clks = reference_clock * 5 / ss.rate; + u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); + + mpll_ss1 &= ~MPLL_SS1__CLKV_MASK; + mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT); + + mpll_ss2 &= ~MPLL_SS2__CLKS_MASK; + mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT); + } + } + + mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK; + mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT); + + if (dll_state_on) + mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK | + MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK; + else + mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK | + MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK); + + mclk->MclkFrequency = memory_clock; + mclk->MpllFuncCntl = mpll_func_cntl; + mclk->MpllFuncCntl_1 = mpll_func_cntl_1; + mclk->MpllFuncCntl_2 = mpll_func_cntl_2; + mclk->MpllAdFuncCntl = mpll_ad_func_cntl; + mclk->MpllDqFuncCntl = mpll_dq_func_cntl; + mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; + mclk->DllCntl = dll_cntl; + mclk->MpllSs1 = mpll_ss1; + mclk->MpllSs2 = mpll_ss2; + + return 0; +} + +static int ci_populate_single_memory_level(struct amdgpu_device *adev, + u32 memory_clock, + SMU7_Discrete_MemoryLevel *memory_level) +{ + struct ci_power_info *pi = ci_get_pi(adev); + int ret; + bool dll_state_on; + + if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { + ret = ci_get_dependency_volt_by_clk(adev, + &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, + memory_clock, &memory_level->MinVddc); + if (ret) + return ret; + } + + if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { + ret = ci_get_dependency_volt_by_clk(adev, + &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, + memory_clock, &memory_level->MinVddci); + if (ret) + return ret; + } + + if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { + ret = ci_get_dependency_volt_by_clk(adev, + &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, + memory_clock, &memory_level->MinMvdd); + if (ret) + return ret; + } + + memory_level->MinVddcPhases = 1; + + if (pi->vddc_phase_shed_control) + ci_populate_phase_value_based_on_mclk(adev, + &adev->pm.dpm.dyn_state.phase_shedding_limits_table, + memory_clock, + &memory_level->MinVddcPhases); + + memory_level->EnabledForThrottle = 1; + memory_level->EnabledForActivity = 1; + memory_level->UpH = 0; + memory_level->DownH = 100; + memory_level->VoltageDownH = 0; + memory_level->ActivityLevel = (u16)pi->mclk_activity_target; + + memory_level->StutterEnable = false; + memory_level->StrobeEnable = false; + memory_level->EdcReadEnable = false; + memory_level->EdcWriteEnable = false; + memory_level->RttEnable = false; + + memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; + + if (pi->mclk_stutter_mode_threshold && + (memory_clock <= pi->mclk_stutter_mode_threshold) && + (pi->uvd_enabled == false) && + (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) && + (adev->pm.dpm.new_active_crtc_count <= 2)) + memory_level->StutterEnable = true; + + if (pi->mclk_strobe_mode_threshold && + (memory_clock <= pi->mclk_strobe_mode_threshold)) + memory_level->StrobeEnable = 1; + + if (adev->mc.is_gddr5) { + memory_level->StrobeRatio = + ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); + if (pi->mclk_edc_enable_threshold && + (memory_clock > pi->mclk_edc_enable_threshold)) + memory_level->EdcReadEnable = true; + + if (pi->mclk_edc_wr_enable_threshold && + (memory_clock > pi->mclk_edc_wr_enable_threshold)) + memory_level->EdcWriteEnable = true; + + if (memory_level->StrobeEnable) { + if (ci_get_mclk_frequency_ratio(memory_clock, true) >= + ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf)) + dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false; + else + dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false; + } else { + dll_state_on = pi->dll_default_on; + } + } else { + memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock); + dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false; + } + + ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); + if (ret) + return ret; + + memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); + memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); + memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); + memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); + + memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); + memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); + memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl); + memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1); + memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2); + memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl); + memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl); + memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl); + memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl); + memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1); + memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2); + + return 0; +} + +static int ci_populate_smc_acpi_level(struct amdgpu_device *adev, + SMU7_Discrete_DpmTable *table) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct atom_clock_dividers dividers; + SMU7_Discrete_VoltageLevel voltage_level; + u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; + u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; + u32 dll_cntl = pi->clock_registers.dll_cntl; + u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; + int ret; + + table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; + + if (pi->acpi_vddc) + table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); + else + table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); + + table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; + + table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq; + + ret = amdgpu_atombios_get_clock_dividers(adev, + COMPUTE_GPUCLK_INPUT_FLAG_SCLK, + table->ACPILevel.SclkFrequency, false, ÷rs); + if (ret) + return ret; + + table->ACPILevel.SclkDid = (u8)dividers.post_divider; + table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; + table->ACPILevel.DeepSleepDivId = 0; + + spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK; + spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK; + + spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; + spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT); + + table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; + table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; + table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; + table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; + table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; + table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; + table->ACPILevel.CcPwrDynRm = 0; + table->ACPILevel.CcPwrDynRm1 = 0; + + table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); + table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); + table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); + table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); + table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); + table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); + table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); + table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); + table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); + table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); + table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); + + table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; + table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; + + if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { + if (pi->acpi_vddci) + table->MemoryACPILevel.MinVddci = + cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); + else + table->MemoryACPILevel.MinVddci = + cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); + } + + if (ci_populate_mvdd_value(adev, 0, &voltage_level)) + table->MemoryACPILevel.MinMvdd = 0; + else + table->MemoryACPILevel.MinMvdd = + cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE); + + mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK | + MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK; + mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK | + MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK); + + dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK); + + table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); + table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); + table->MemoryACPILevel.MpllAdFuncCntl = + cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); + table->MemoryACPILevel.MpllDqFuncCntl = + cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); + table->MemoryACPILevel.MpllFuncCntl = + cpu_to_be32(pi->clock_registers.mpll_func_cntl); + table->MemoryACPILevel.MpllFuncCntl_1 = + cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); + table->MemoryACPILevel.MpllFuncCntl_2 = + cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); + table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); + table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); + + table->MemoryACPILevel.EnabledForThrottle = 0; + table->MemoryACPILevel.EnabledForActivity = 0; + table->MemoryACPILevel.UpH = 0; + table->MemoryACPILevel.DownH = 100; + table->MemoryACPILevel.VoltageDownH = 0; + table->MemoryACPILevel.ActivityLevel = + cpu_to_be16((u16)pi->mclk_activity_target); + + table->MemoryACPILevel.StutterEnable = false; + table->MemoryACPILevel.StrobeEnable = false; + table->MemoryACPILevel.EdcReadEnable = false; + table->MemoryACPILevel.EdcWriteEnable = false; + table->MemoryACPILevel.RttEnable = false; + + return 0; +} + + +static int ci_enable_ulv(struct amdgpu_device *adev, bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_ulv_parm *ulv = &pi->ulv; + + if (ulv->supported) { + if (enable) + return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? + 0 : -EINVAL; + else + return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? + 0 : -EINVAL; + } + + return 0; +} + +static int ci_populate_ulv_level(struct amdgpu_device *adev, + SMU7_Discrete_Ulv *state) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u16 ulv_voltage = adev->pm.dpm.backbias_response_time; + + state->CcPwrDynRm = 0; + state->CcPwrDynRm1 = 0; + + if (ulv_voltage == 0) { + pi->ulv.supported = false; + return 0; + } + + if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { + if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) + state->VddcOffset = 0; + else + state->VddcOffset = + adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; + } else { + if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) + state->VddcOffsetVid = 0; + else + state->VddcOffsetVid = (u8) + ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * + VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); + } + state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; + + state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm); + state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1); + state->VddcOffset = cpu_to_be16(state->VddcOffset); + + return 0; +} + +static int ci_calculate_sclk_params(struct amdgpu_device *adev, + u32 engine_clock, + SMU7_Discrete_GraphicsLevel *sclk) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct atom_clock_dividers dividers; + u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; + u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; + u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; + u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; + u32 reference_clock = adev->clock.spll.reference_freq; + u32 reference_divider; + u32 fbdiv; + int ret; + + ret = amdgpu_atombios_get_clock_dividers(adev, + COMPUTE_GPUCLK_INPUT_FLAG_SCLK, + engine_clock, false, ÷rs); + if (ret) + return ret; + + reference_divider = 1 + dividers.ref_div; + fbdiv = dividers.fb_div & 0x3FFFFFF; + + spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK; + spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT); + spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK; + + if (pi->caps_sclk_ss_support) { + struct amdgpu_atom_ss ss; + u32 vco_freq = engine_clock * dividers.post_div; + + if (amdgpu_atombios_get_asic_ss_info(adev, &ss, + ASIC_INTERNAL_ENGINE_SS, vco_freq)) { + u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); + u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); + + cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK); + cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT); + cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT); + + cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK; + cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT); + } + } + + sclk->SclkFrequency = engine_clock; + sclk->CgSpllFuncCntl3 = spll_func_cntl_3; + sclk->CgSpllFuncCntl4 = spll_func_cntl_4; + sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; + sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; + sclk->SclkDid = (u8)dividers.post_divider; + + return 0; +} + +static int ci_populate_single_graphic_level(struct amdgpu_device *adev, + u32 engine_clock, + u16 sclk_activity_level_t, + SMU7_Discrete_GraphicsLevel *graphic_level) +{ + struct ci_power_info *pi = ci_get_pi(adev); + int ret; + + ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level); + if (ret) + return ret; + + ret = ci_get_dependency_volt_by_clk(adev, + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, + engine_clock, &graphic_level->MinVddc); + if (ret) + return ret; + + graphic_level->SclkFrequency = engine_clock; + + graphic_level->Flags = 0; + graphic_level->MinVddcPhases = 1; + + if (pi->vddc_phase_shed_control) + ci_populate_phase_value_based_on_sclk(adev, + &adev->pm.dpm.dyn_state.phase_shedding_limits_table, + engine_clock, + &graphic_level->MinVddcPhases); + + graphic_level->ActivityLevel = sclk_activity_level_t; + + graphic_level->CcPwrDynRm = 0; + graphic_level->CcPwrDynRm1 = 0; + graphic_level->EnabledForThrottle = 1; + graphic_level->UpH = 0; + graphic_level->DownH = 0; + graphic_level->VoltageDownH = 0; + graphic_level->PowerThrottle = 0; + + if (pi->caps_sclk_ds) + graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(adev, + engine_clock, + CISLAND_MINIMUM_ENGINE_CLOCK); + + graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; + + graphic_level->Flags = cpu_to_be32(graphic_level->Flags); + graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); + graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); + graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); + graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); + graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3); + graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4); + graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum); + graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); + graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); + graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1); + graphic_level->EnabledForActivity = 1; + + return 0; +} + +static int ci_populate_all_graphic_levels(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_dpm_table *dpm_table = &pi->dpm_table; + u32 level_array_address = pi->dpm_table_start + + offsetof(SMU7_Discrete_DpmTable, GraphicsLevel); + u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) * + SMU7_MAX_LEVELS_GRAPHICS; + SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; + u32 i, ret; + + memset(levels, 0, level_array_size); + + for (i = 0; i < dpm_table->sclk_table.count; i++) { + ret = ci_populate_single_graphic_level(adev, + dpm_table->sclk_table.dpm_levels[i].value, + (u16)pi->activity_target[i], + &pi->smc_state_table.GraphicsLevel[i]); + if (ret) + return ret; + if (i > 1) + pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; + if (i == (dpm_table->sclk_table.count - 1)) + pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = + PPSMC_DISPLAY_WATERMARK_HIGH; + } + + pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; + pi->dpm_level_enable_mask.sclk_dpm_enable_mask = + ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); + + ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address, + (u8 *)levels, level_array_size, + pi->sram_end); + if (ret) + return ret; + + return 0; +} + +static int ci_populate_ulv_state(struct amdgpu_device *adev, + SMU7_Discrete_Ulv *ulv_level) +{ + return ci_populate_ulv_level(adev, ulv_level); +} + +static int ci_populate_all_memory_levels(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_dpm_table *dpm_table = &pi->dpm_table; + u32 level_array_address = pi->dpm_table_start + + offsetof(SMU7_Discrete_DpmTable, MemoryLevel); + u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * + SMU7_MAX_LEVELS_MEMORY; + SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; + u32 i, ret; + + memset(levels, 0, level_array_size); + + for (i = 0; i < dpm_table->mclk_table.count; i++) { + if (dpm_table->mclk_table.dpm_levels[i].value == 0) + return -EINVAL; + ret = ci_populate_single_memory_level(adev, + dpm_table->mclk_table.dpm_levels[i].value, + &pi->smc_state_table.MemoryLevel[i]); + if (ret) + return ret; + } + + if ((dpm_table->mclk_table.count >= 2) && + ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) { + pi->smc_state_table.MemoryLevel[1].MinVddc = + pi->smc_state_table.MemoryLevel[0].MinVddc; + pi->smc_state_table.MemoryLevel[1].MinVddcPhases = + pi->smc_state_table.MemoryLevel[0].MinVddcPhases; + } + + pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); + + pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; + pi->dpm_level_enable_mask.mclk_dpm_enable_mask = + ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); + + pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = + PPSMC_DISPLAY_WATERMARK_HIGH; + + ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address, + (u8 *)levels, level_array_size, + pi->sram_end); + if (ret) + return ret; + + return 0; +} + +static void ci_reset_single_dpm_table(struct amdgpu_device *adev, + struct ci_single_dpm_table* dpm_table, + u32 count) +{ + u32 i; + + dpm_table->count = count; + for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) + dpm_table->dpm_levels[i].enabled = false; +} + +static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, + u32 index, u32 pcie_gen, u32 pcie_lanes) +{ + dpm_table->dpm_levels[index].value = pcie_gen; + dpm_table->dpm_levels[index].param1 = pcie_lanes; + dpm_table->dpm_levels[index].enabled = true; +} + +static int ci_setup_default_pcie_tables(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) + return -EINVAL; + + if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { + pi->pcie_gen_powersaving = pi->pcie_gen_performance; + pi->pcie_lane_powersaving = pi->pcie_lane_performance; + } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { + pi->pcie_gen_performance = pi->pcie_gen_powersaving; + pi->pcie_lane_performance = pi->pcie_lane_powersaving; + } + + ci_reset_single_dpm_table(adev, + &pi->dpm_table.pcie_speed_table, + SMU7_MAX_LEVELS_LINK); + + if (adev->asic_type == CHIP_BONAIRE) + ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, + pi->pcie_gen_powersaving.min, + pi->pcie_lane_powersaving.max); + else + ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, + pi->pcie_gen_powersaving.min, + pi->pcie_lane_powersaving.min); + ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, + pi->pcie_gen_performance.min, + pi->pcie_lane_performance.min); + ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, + pi->pcie_gen_powersaving.min, + pi->pcie_lane_powersaving.max); + ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, + pi->pcie_gen_performance.min, + pi->pcie_lane_performance.max); + ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, + pi->pcie_gen_powersaving.max, + pi->pcie_lane_powersaving.max); + ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, + pi->pcie_gen_performance.max, + pi->pcie_lane_performance.max); + + pi->dpm_table.pcie_speed_table.count = 6; + + return 0; +} + +static int ci_setup_default_dpm_tables(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk; + struct amdgpu_cac_leakage_table *std_voltage_table = + &adev->pm.dpm.dyn_state.cac_leakage_table; + u32 i; + + if (allowed_sclk_vddc_table == NULL) + return -EINVAL; + if (allowed_sclk_vddc_table->count < 1) + return -EINVAL; + if (allowed_mclk_table == NULL) + return -EINVAL; + if (allowed_mclk_table->count < 1) + return -EINVAL; + + memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); + + ci_reset_single_dpm_table(adev, + &pi->dpm_table.sclk_table, + SMU7_MAX_LEVELS_GRAPHICS); + ci_reset_single_dpm_table(adev, + &pi->dpm_table.mclk_table, + SMU7_MAX_LEVELS_MEMORY); + ci_reset_single_dpm_table(adev, + &pi->dpm_table.vddc_table, + SMU7_MAX_LEVELS_VDDC); + ci_reset_single_dpm_table(adev, + &pi->dpm_table.vddci_table, + SMU7_MAX_LEVELS_VDDCI); + ci_reset_single_dpm_table(adev, + &pi->dpm_table.mvdd_table, + SMU7_MAX_LEVELS_MVDD); + + pi->dpm_table.sclk_table.count = 0; + for (i = 0; i < allowed_sclk_vddc_table->count; i++) { + if ((i == 0) || + (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != + allowed_sclk_vddc_table->entries[i].clk)) { + pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = + allowed_sclk_vddc_table->entries[i].clk; + pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = + (i == 0) ? true : false; + pi->dpm_table.sclk_table.count++; + } + } + + pi->dpm_table.mclk_table.count = 0; + for (i = 0; i < allowed_mclk_table->count; i++) { + if ((i == 0) || + (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != + allowed_mclk_table->entries[i].clk)) { + pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = + allowed_mclk_table->entries[i].clk; + pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = + (i == 0) ? true : false; + pi->dpm_table.mclk_table.count++; + } + } + + for (i = 0; i < allowed_sclk_vddc_table->count; i++) { + pi->dpm_table.vddc_table.dpm_levels[i].value = + allowed_sclk_vddc_table->entries[i].v; + pi->dpm_table.vddc_table.dpm_levels[i].param1 = + std_voltage_table->entries[i].leakage; + pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; + } + pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; + + allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk; + if (allowed_mclk_table) { + for (i = 0; i < allowed_mclk_table->count; i++) { + pi->dpm_table.vddci_table.dpm_levels[i].value = + allowed_mclk_table->entries[i].v; + pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; + } + pi->dpm_table.vddci_table.count = allowed_mclk_table->count; + } + + allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; + if (allowed_mclk_table) { + for (i = 0; i < allowed_mclk_table->count; i++) { + pi->dpm_table.mvdd_table.dpm_levels[i].value = + allowed_mclk_table->entries[i].v; + pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; + } + pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; + } + + ci_setup_default_pcie_tables(adev); + + return 0; +} + +static int ci_find_boot_level(struct ci_single_dpm_table *table, + u32 value, u32 *boot_level) +{ + u32 i; + int ret = -EINVAL; + + for(i = 0; i < table->count; i++) { + if (value == table->dpm_levels[i].value) { + *boot_level = i; + ret = 0; + } + } + + return ret; +} + +static int ci_init_smc_table(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_ulv_parm *ulv = &pi->ulv; + struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; + SMU7_Discrete_DpmTable *table = &pi->smc_state_table; + int ret; + + ret = ci_setup_default_dpm_tables(adev); + if (ret) + return ret; + + if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) + ci_populate_smc_voltage_tables(adev, table); + + ci_init_fps_limits(adev); + + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) + table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; + + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) + table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; + + if (adev->mc.is_gddr5) + table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; + + if (ulv->supported) { + ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv); + if (ret) + return ret; + WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter); + } + + ret = ci_populate_all_graphic_levels(adev); + if (ret) + return ret; + + ret = ci_populate_all_memory_levels(adev); + if (ret) + return ret; + + ci_populate_smc_link_level(adev, table); + + ret = ci_populate_smc_acpi_level(adev, table); + if (ret) + return ret; + + ret = ci_populate_smc_vce_level(adev, table); + if (ret) + return ret; + + ret = ci_populate_smc_acp_level(adev, table); + if (ret) + return ret; + + ret = ci_populate_smc_samu_level(adev, table); + if (ret) + return ret; + + ret = ci_do_program_memory_timing_parameters(adev); + if (ret) + return ret; + + ret = ci_populate_smc_uvd_level(adev, table); + if (ret) + return ret; + + table->UvdBootLevel = 0; + table->VceBootLevel = 0; + table->AcpBootLevel = 0; + table->SamuBootLevel = 0; + table->GraphicsBootLevel = 0; + table->MemoryBootLevel = 0; + + ret = ci_find_boot_level(&pi->dpm_table.sclk_table, + pi->vbios_boot_state.sclk_bootup_value, + (u32 *)&pi->smc_state_table.GraphicsBootLevel); + + ret = ci_find_boot_level(&pi->dpm_table.mclk_table, + pi->vbios_boot_state.mclk_bootup_value, + (u32 *)&pi->smc_state_table.MemoryBootLevel); + + table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; + table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; + table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; + + ci_populate_smc_initial_state(adev, amdgpu_boot_state); + + ret = ci_populate_bapm_parameters_in_dpm_table(adev); + if (ret) + return ret; + + table->UVDInterval = 1; + table->VCEInterval = 1; + table->ACPInterval = 1; + table->SAMUInterval = 1; + table->GraphicsVoltageChangeEnable = 1; + table->GraphicsThermThrottleEnable = 1; + table->GraphicsInterval = 1; + table->VoltageInterval = 1; + table->ThermalInterval = 1; + table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * + CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); + table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * + CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000); + table->MemoryVoltageChangeEnable = 1; + table->MemoryInterval = 1; + table->VoltageResponseTime = 0; + table->VddcVddciDelta = 4000; + table->PhaseResponseTime = 0; + table->MemoryThermThrottleEnable = 1; + table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; + table->PCIeGenInterval = 1; + if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) + table->SVI2Enable = 1; + else + table->SVI2Enable = 0; + + table->ThermGpio = 17; + table->SclkStepSize = 0x4000; + + table->SystemFlags = cpu_to_be32(table->SystemFlags); + table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); + table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); + table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); + table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); + table->SclkStepSize = cpu_to_be32(table->SclkStepSize); + table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); + table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); + table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); + table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); + table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); + table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); + table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); + table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); + + ret = amdgpu_ci_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Discrete_DpmTable, SystemFlags), + (u8 *)&table->SystemFlags, + sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController), + pi->sram_end); + if (ret) + return ret; + + return 0; +} + +static void ci_trim_single_dpm_states(struct amdgpu_device *adev, + struct ci_single_dpm_table *dpm_table, + u32 low_limit, u32 high_limit) +{ + u32 i; + + for (i = 0; i < dpm_table->count; i++) { + if ((dpm_table->dpm_levels[i].value < low_limit) || + (dpm_table->dpm_levels[i].value > high_limit)) + dpm_table->dpm_levels[i].enabled = false; + else + dpm_table->dpm_levels[i].enabled = true; + } +} + +static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev, + u32 speed_low, u32 lanes_low, + u32 speed_high, u32 lanes_high) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; + u32 i, j; + + for (i = 0; i < pcie_table->count; i++) { + if ((pcie_table->dpm_levels[i].value < speed_low) || + (pcie_table->dpm_levels[i].param1 < lanes_low) || + (pcie_table->dpm_levels[i].value > speed_high) || + (pcie_table->dpm_levels[i].param1 > lanes_high)) + pcie_table->dpm_levels[i].enabled = false; + else + pcie_table->dpm_levels[i].enabled = true; + } + + for (i = 0; i < pcie_table->count; i++) { + if (pcie_table->dpm_levels[i].enabled) { + for (j = i + 1; j < pcie_table->count; j++) { + if (pcie_table->dpm_levels[j].enabled) { + if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) && + (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1)) + pcie_table->dpm_levels[j].enabled = false; + } + } + } + } +} + +static int ci_trim_dpm_states(struct amdgpu_device *adev, + struct amdgpu_ps *amdgpu_state) +{ + struct ci_ps *state = ci_get_ps(amdgpu_state); + struct ci_power_info *pi = ci_get_pi(adev); + u32 high_limit_count; + + if (state->performance_level_count < 1) + return -EINVAL; + + if (state->performance_level_count == 1) + high_limit_count = 0; + else + high_limit_count = 1; + + ci_trim_single_dpm_states(adev, + &pi->dpm_table.sclk_table, + state->performance_levels[0].sclk, + state->performance_levels[high_limit_count].sclk); + + ci_trim_single_dpm_states(adev, + &pi->dpm_table.mclk_table, + state->performance_levels[0].mclk, + state->performance_levels[high_limit_count].mclk); + + ci_trim_pcie_dpm_states(adev, + state->performance_levels[0].pcie_gen, + state->performance_levels[0].pcie_lane, + state->performance_levels[high_limit_count].pcie_gen, + state->performance_levels[high_limit_count].pcie_lane); + + return 0; +} + +static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev) +{ + struct amdgpu_clock_voltage_dependency_table *disp_voltage_table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; + struct amdgpu_clock_voltage_dependency_table *vddc_table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + u32 requested_voltage = 0; + u32 i; + + if (disp_voltage_table == NULL) + return -EINVAL; + if (!disp_voltage_table->count) + return -EINVAL; + + for (i = 0; i < disp_voltage_table->count; i++) { + if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk) + requested_voltage = disp_voltage_table->entries[i].v; + } + + for (i = 0; i < vddc_table->count; i++) { + if (requested_voltage <= vddc_table->entries[i].v) { + requested_voltage = vddc_table->entries[i].v; + return (amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_VddC_Request, + requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ? + 0 : -EINVAL; + } + } + + return -EINVAL; +} + +static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + PPSMC_Result result; + + ci_apply_disp_minimum_voltage_request(adev); + + if (!pi->sclk_dpm_key_disabled) { + if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { + result = amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + pi->dpm_level_enable_mask.sclk_dpm_enable_mask); + if (result != PPSMC_Result_OK) + return -EINVAL; + } + } + + if (!pi->mclk_dpm_key_disabled) { + if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { + result = amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + pi->dpm_level_enable_mask.mclk_dpm_enable_mask); + if (result != PPSMC_Result_OK) + return -EINVAL; + } + } + +#if 0 + if (!pi->pcie_dpm_key_disabled) { + if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { + result = amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_PCIeDPM_SetEnabledMask, + pi->dpm_level_enable_mask.pcie_dpm_enable_mask); + if (result != PPSMC_Result_OK) + return -EINVAL; + } + } +#endif + + return 0; +} + +static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev, + struct amdgpu_ps *amdgpu_state) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_ps *state = ci_get_ps(amdgpu_state); + struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; + u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; + struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; + u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; + u32 i; + + pi->need_update_smu7_dpm_table = 0; + + for (i = 0; i < sclk_table->count; i++) { + if (sclk == sclk_table->dpm_levels[i].value) + break; + } + + if (i >= sclk_table->count) { + pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; + } else { + /* XXX check display min clock requirements */ + if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK) + pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; + } + + for (i = 0; i < mclk_table->count; i++) { + if (mclk == mclk_table->dpm_levels[i].value) + break; + } + + if (i >= mclk_table->count) + pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; + + if (adev->pm.dpm.current_active_crtc_count != + adev->pm.dpm.new_active_crtc_count) + pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; +} + +static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev, + struct amdgpu_ps *amdgpu_state) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_ps *state = ci_get_ps(amdgpu_state); + u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; + u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; + struct ci_dpm_table *dpm_table = &pi->dpm_table; + int ret; + + if (!pi->need_update_smu7_dpm_table) + return 0; + + if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) + dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; + + if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) + dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk; + + if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { + ret = ci_populate_all_graphic_levels(adev); + if (ret) + return ret; + } + + if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { + ret = ci_populate_all_memory_levels(adev); + if (ret) + return ret; + } + + return 0; +} + +static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + const struct amdgpu_clock_and_voltage_limits *max_limits; + int i; + + if (adev->pm.dpm.ac_power) + max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; + else + max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; + + if (enable) { + pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; + + for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { + if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { + pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; + + if (!pi->caps_uvd_dpm) + break; + } + } + + amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_UVDDPM_SetEnabledMask, + pi->dpm_level_enable_mask.uvd_dpm_enable_mask); + + if (pi->last_mclk_dpm_enable_mask & 0x1) { + pi->uvd_enabled = true; + pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; + amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + pi->dpm_level_enable_mask.mclk_dpm_enable_mask); + } + } else { + if (pi->last_mclk_dpm_enable_mask & 0x1) { + pi->uvd_enabled = false; + pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; + amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + pi->dpm_level_enable_mask.mclk_dpm_enable_mask); + } + } + + return (amdgpu_ci_send_msg_to_smc(adev, enable ? + PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ? + 0 : -EINVAL; +} + +static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + const struct amdgpu_clock_and_voltage_limits *max_limits; + int i; + + if (adev->pm.dpm.ac_power) + max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; + else + max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; + + if (enable) { + pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; + for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { + if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { + pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; + + if (!pi->caps_vce_dpm) + break; + } + } + + amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_VCEDPM_SetEnabledMask, + pi->dpm_level_enable_mask.vce_dpm_enable_mask); + } + + return (amdgpu_ci_send_msg_to_smc(adev, enable ? + PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ? + 0 : -EINVAL; +} + +#if 0 +static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + const struct amdgpu_clock_and_voltage_limits *max_limits; + int i; + + if (adev->pm.dpm.ac_power) + max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; + else + max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; + + if (enable) { + pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0; + for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) { + if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { + pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i; + + if (!pi->caps_samu_dpm) + break; + } + } + + amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SAMUDPM_SetEnabledMask, + pi->dpm_level_enable_mask.samu_dpm_enable_mask); + } + return (amdgpu_ci_send_msg_to_smc(adev, enable ? + PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ? + 0 : -EINVAL; +} + +static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable) +{ + struct ci_power_info *pi = ci_get_pi(adev); + const struct amdgpu_clock_and_voltage_limits *max_limits; + int i; + + if (adev->pm.dpm.ac_power) + max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; + else + max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; + + if (enable) { + pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0; + for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) { + if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { + pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i; + + if (!pi->caps_acp_dpm) + break; + } + } + + amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_ACPDPM_SetEnabledMask, + pi->dpm_level_enable_mask.acp_dpm_enable_mask); + } + + return (amdgpu_ci_send_msg_to_smc(adev, enable ? + PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ? + 0 : -EINVAL; +} +#endif + +static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 tmp; + + if (!gate) { + if (pi->caps_uvd_dpm || + (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) + pi->smc_state_table.UvdBootLevel = 0; + else + pi->smc_state_table.UvdBootLevel = + adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; + + tmp = RREG32_SMC(ixDPM_TABLE_475); + tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK; + tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT); + WREG32_SMC(ixDPM_TABLE_475, tmp); + } + + return ci_enable_uvd_dpm(adev, !gate); +} + +static u8 ci_get_vce_boot_level(struct amdgpu_device *adev) +{ + u8 i; + u32 min_evclk = 30000; /* ??? */ + struct amdgpu_vce_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + + for (i = 0; i < table->count; i++) { + if (table->entries[i].evclk >= min_evclk) + return i; + } + + return table->count - 1; +} + +static int ci_update_vce_dpm(struct amdgpu_device *adev, + struct amdgpu_ps *amdgpu_new_state, + struct amdgpu_ps *amdgpu_current_state) +{ + struct ci_power_info *pi = ci_get_pi(adev); + int ret = 0; + u32 tmp; + + if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) { + if (amdgpu_new_state->evclk) { + /* turn the clocks on when encoding */ + ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, + AMDGPU_CG_STATE_UNGATE); + if (ret) + return ret; + + pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev); + tmp = RREG32_SMC(ixDPM_TABLE_475); + tmp &= ~DPM_TABLE_475__VceBootLevel_MASK; + tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT); + WREG32_SMC(ixDPM_TABLE_475, tmp); + + ret = ci_enable_vce_dpm(adev, true); + } else { + /* turn the clocks off when not encoding */ + ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, + AMDGPU_CG_STATE_GATE); + if (ret) + return ret; + + ret = ci_enable_vce_dpm(adev, false); + } + } + return ret; +} + +#if 0 +static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate) +{ + return ci_enable_samu_dpm(adev, gate); +} + +static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 tmp; + + if (!gate) { + pi->smc_state_table.AcpBootLevel = 0; + + tmp = RREG32_SMC(ixDPM_TABLE_475); + tmp &= ~AcpBootLevel_MASK; + tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel); + WREG32_SMC(ixDPM_TABLE_475, tmp); + } + + return ci_enable_acp_dpm(adev, !gate); +} +#endif + +static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev, + struct amdgpu_ps *amdgpu_state) +{ + struct ci_power_info *pi = ci_get_pi(adev); + int ret; + + ret = ci_trim_dpm_states(adev, amdgpu_state); + if (ret) + return ret; + + pi->dpm_level_enable_mask.sclk_dpm_enable_mask = + ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); + pi->dpm_level_enable_mask.mclk_dpm_enable_mask = + ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); + pi->last_mclk_dpm_enable_mask = + pi->dpm_level_enable_mask.mclk_dpm_enable_mask; + if (pi->uvd_enabled) { + if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) + pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; + } + pi->dpm_level_enable_mask.pcie_dpm_enable_mask = + ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); + + return 0; +} + +static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev, + u32 level_mask) +{ + u32 level = 0; + + while ((level_mask & (1 << level)) == 0) + level++; + + return level; +} + + +static int ci_dpm_force_performance_level(struct amdgpu_device *adev, + enum amdgpu_dpm_forced_level level) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 tmp, levels, i; + int ret; + + if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) { + if ((!pi->pcie_dpm_key_disabled) && + pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { + levels = 0; + tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; + while (tmp >>= 1) + levels++; + if (levels) { + ret = ci_dpm_force_state_pcie(adev, level); + if (ret) + return ret; + for (i = 0; i < adev->usec_timeout; i++) { + tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) & + TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >> + TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT; + if (tmp == levels) + break; + udelay(1); + } + } + } + if ((!pi->sclk_dpm_key_disabled) && + pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { + levels = 0; + tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; + while (tmp >>= 1) + levels++; + if (levels) { + ret = ci_dpm_force_state_sclk(adev, levels); + if (ret) + return ret; + for (i = 0; i < adev->usec_timeout; i++) { + tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >> + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT; + if (tmp == levels) + break; + udelay(1); + } + } + } + if ((!pi->mclk_dpm_key_disabled) && + pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { + levels = 0; + tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; + while (tmp >>= 1) + levels++; + if (levels) { + ret = ci_dpm_force_state_mclk(adev, levels); + if (ret) + return ret; + for (i = 0; i < adev->usec_timeout; i++) { + tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >> + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT; + if (tmp == levels) + break; + udelay(1); + } + } + } + if ((!pi->pcie_dpm_key_disabled) && + pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { + levels = 0; + tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; + while (tmp >>= 1) + levels++; + if (levels) { + ret = ci_dpm_force_state_pcie(adev, level); + if (ret) + return ret; + for (i = 0; i < adev->usec_timeout; i++) { + tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) & + TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >> + TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT; + if (tmp == levels) + break; + udelay(1); + } + } + } + } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) { + if ((!pi->sclk_dpm_key_disabled) && + pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { + levels = ci_get_lowest_enabled_level(adev, + pi->dpm_level_enable_mask.sclk_dpm_enable_mask); + ret = ci_dpm_force_state_sclk(adev, levels); + if (ret) + return ret; + for (i = 0; i < adev->usec_timeout; i++) { + tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >> + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT; + if (tmp == levels) + break; + udelay(1); + } + } + if ((!pi->mclk_dpm_key_disabled) && + pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { + levels = ci_get_lowest_enabled_level(adev, + pi->dpm_level_enable_mask.mclk_dpm_enable_mask); + ret = ci_dpm_force_state_mclk(adev, levels); + if (ret) + return ret; + for (i = 0; i < adev->usec_timeout; i++) { + tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >> + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT; + if (tmp == levels) + break; + udelay(1); + } + } + if ((!pi->pcie_dpm_key_disabled) && + pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { + levels = ci_get_lowest_enabled_level(adev, + pi->dpm_level_enable_mask.pcie_dpm_enable_mask); + ret = ci_dpm_force_state_pcie(adev, levels); + if (ret) + return ret; + for (i = 0; i < adev->usec_timeout; i++) { + tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) & + TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >> + TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT; + if (tmp == levels) + break; + udelay(1); + } + } + } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) { + if (!pi->pcie_dpm_key_disabled) { + PPSMC_Result smc_result; + + smc_result = amdgpu_ci_send_msg_to_smc(adev, + PPSMC_MSG_PCIeDPM_UnForceLevel); + if (smc_result != PPSMC_Result_OK) + return -EINVAL; + } + ret = ci_upload_dpm_level_enable_mask(adev); + if (ret) + return ret; + } + + adev->pm.dpm.forced_level = level; + + return 0; +} + +static int ci_set_mc_special_registers(struct amdgpu_device *adev, + struct ci_mc_reg_table *table) +{ + u8 i, j, k; + u32 temp_reg; + + for (i = 0, j = table->last; i < table->last; i++) { + if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; + switch(table->mc_reg_address[i].s1) { + case mmMC_SEQ_MISC1: + temp_reg = RREG32(mmMC_PMG_CMD_EMRS); + table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; + table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; + for (k = 0; k < table->num_entries; k++) { + table->mc_reg_table_entry[k].mc_data[j] = + ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); + } + j++; + if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; + + temp_reg = RREG32(mmMC_PMG_CMD_MRS); + table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; + table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; + for (k = 0; k < table->num_entries; k++) { + table->mc_reg_table_entry[k].mc_data[j] = + (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); + if (!adev->mc.is_gddr5) + table->mc_reg_table_entry[k].mc_data[j] |= 0x100; + } + j++; + if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; + + if (!adev->mc.is_gddr5) { + table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; + table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; + for (k = 0; k < table->num_entries; k++) { + table->mc_reg_table_entry[k].mc_data[j] = + (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; + } + j++; + if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; + } + break; + case mmMC_SEQ_RESERVE_M: + temp_reg = RREG32(mmMC_PMG_CMD_MRS1); + table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; + table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; + for (k = 0; k < table->num_entries; k++) { + table->mc_reg_table_entry[k].mc_data[j] = + (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); + } + j++; + if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; + break; + default: + break; + } + + } + + table->last = j; + + return 0; +} + +static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) +{ + bool result = true; + + switch(in_reg) { + case mmMC_SEQ_RAS_TIMING: + *out_reg = mmMC_SEQ_RAS_TIMING_LP; + break; + case mmMC_SEQ_DLL_STBY: + *out_reg = mmMC_SEQ_DLL_STBY_LP; + break; + case mmMC_SEQ_G5PDX_CMD0: + *out_reg = mmMC_SEQ_G5PDX_CMD0_LP; + break; + case mmMC_SEQ_G5PDX_CMD1: + *out_reg = mmMC_SEQ_G5PDX_CMD1_LP; + break; + case mmMC_SEQ_G5PDX_CTRL: + *out_reg = mmMC_SEQ_G5PDX_CTRL_LP; + break; + case mmMC_SEQ_CAS_TIMING: + *out_reg = mmMC_SEQ_CAS_TIMING_LP; + break; + case mmMC_SEQ_MISC_TIMING: + *out_reg = mmMC_SEQ_MISC_TIMING_LP; + break; + case mmMC_SEQ_MISC_TIMING2: + *out_reg = mmMC_SEQ_MISC_TIMING2_LP; + break; + case mmMC_SEQ_PMG_DVS_CMD: + *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP; + break; + case mmMC_SEQ_PMG_DVS_CTL: + *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP; + break; + case mmMC_SEQ_RD_CTL_D0: + *out_reg = mmMC_SEQ_RD_CTL_D0_LP; + break; + case mmMC_SEQ_RD_CTL_D1: + *out_reg = mmMC_SEQ_RD_CTL_D1_LP; + break; + case mmMC_SEQ_WR_CTL_D0: + *out_reg = mmMC_SEQ_WR_CTL_D0_LP; + break; + case mmMC_SEQ_WR_CTL_D1: + *out_reg = mmMC_SEQ_WR_CTL_D1_LP; + break; + case mmMC_PMG_CMD_EMRS: + *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP; + break; + case mmMC_PMG_CMD_MRS: + *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP; + break; + case mmMC_PMG_CMD_MRS1: + *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP; + break; + case mmMC_SEQ_PMG_TIMING: + *out_reg = mmMC_SEQ_PMG_TIMING_LP; + break; + case mmMC_PMG_CMD_MRS2: + *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP; + break; + case mmMC_SEQ_WR_CTL_2: + *out_reg = mmMC_SEQ_WR_CTL_2_LP; + break; + default: + result = false; + break; + } + + return result; +} + +static void ci_set_valid_flag(struct ci_mc_reg_table *table) +{ + u8 i, j; + + for (i = 0; i < table->last; i++) { + for (j = 1; j < table->num_entries; j++) { + if (table->mc_reg_table_entry[j-1].mc_data[i] != + table->mc_reg_table_entry[j].mc_data[i]) { + table->valid_flag |= 1 << i; + break; + } + } + } +} + +static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) +{ + u32 i; + u16 address; + + for (i = 0; i < table->last; i++) { + table->mc_reg_address[i].s0 = + ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? + address : table->mc_reg_address[i].s1; + } +} + +static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, + struct ci_mc_reg_table *ci_table) +{ + u8 i, j; + + if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; + if (table->num_entries > MAX_AC_TIMING_ENTRIES) + return -EINVAL; + + for (i = 0; i < table->last; i++) + ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; + + ci_table->last = table->last; + + for (i = 0; i < table->num_entries; i++) { + ci_table->mc_reg_table_entry[i].mclk_max = + table->mc_reg_table_entry[i].mclk_max; + for (j = 0; j < table->last; j++) + ci_table->mc_reg_table_entry[i].mc_data[j] = + table->mc_reg_table_entry[i].mc_data[j]; + } + ci_table->num_entries = table->num_entries; + + return 0; +} + +static int ci_register_patching_mc_seq(struct amdgpu_device *adev, + struct ci_mc_reg_table *table) +{ + u8 i, k; + u32 tmp; + bool patch; + + tmp = RREG32(mmMC_SEQ_MISC0); + patch = ((tmp & 0x0000f00) == 0x300) ? true : false; + + if (patch && + ((adev->pdev->device == 0x67B0) || + (adev->pdev->device == 0x67B1))) { + for (i = 0; i < table->last; i++) { + if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; + switch (table->mc_reg_address[i].s1) { + case mmMC_SEQ_MISC1: + for (k = 0; k < table->num_entries; k++) { + if ((table->mc_reg_table_entry[k].mclk_max == 125000) || + (table->mc_reg_table_entry[k].mclk_max == 137500)) + table->mc_reg_table_entry[k].mc_data[i] = + (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) | + 0x00000007; + } + break; + case mmMC_SEQ_WR_CTL_D0: + for (k = 0; k < table->num_entries; k++) { + if ((table->mc_reg_table_entry[k].mclk_max == 125000) || + (table->mc_reg_table_entry[k].mclk_max == 137500)) + table->mc_reg_table_entry[k].mc_data[i] = + (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | + 0x0000D0DD; + } + break; + case mmMC_SEQ_WR_CTL_D1: + for (k = 0; k < table->num_entries; k++) { + if ((table->mc_reg_table_entry[k].mclk_max == 125000) || + (table->mc_reg_table_entry[k].mclk_max == 137500)) + table->mc_reg_table_entry[k].mc_data[i] = + (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | + 0x0000D0DD; + } + break; + case mmMC_SEQ_WR_CTL_2: + for (k = 0; k < table->num_entries; k++) { + if ((table->mc_reg_table_entry[k].mclk_max == 125000) || + (table->mc_reg_table_entry[k].mclk_max == 137500)) + table->mc_reg_table_entry[k].mc_data[i] = 0; + } + break; + case mmMC_SEQ_CAS_TIMING: + for (k = 0; k < table->num_entries; k++) { + if (table->mc_reg_table_entry[k].mclk_max == 125000) + table->mc_reg_table_entry[k].mc_data[i] = + (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | + 0x000C0140; + else if (table->mc_reg_table_entry[k].mclk_max == 137500) + table->mc_reg_table_entry[k].mc_data[i] = + (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | + 0x000C0150; + } + break; + case mmMC_SEQ_MISC_TIMING: + for (k = 0; k < table->num_entries; k++) { + if (table->mc_reg_table_entry[k].mclk_max == 125000) + table->mc_reg_table_entry[k].mc_data[i] = + (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | + 0x00000030; + else if (table->mc_reg_table_entry[k].mclk_max == 137500) + table->mc_reg_table_entry[k].mc_data[i] = + (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | + 0x00000035; + } + break; + default: + break; + } + } + + WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3); + tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA); + tmp = (tmp & 0xFFF8FFFF) | (1 << 16); + WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3); + WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp); + } + + return 0; +} + +static int ci_initialize_mc_reg_table(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct atom_mc_reg_table *table; + struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; + u8 module_index = ci_get_memory_module_index(adev); + int ret; + + table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); + if (!table) + return -ENOMEM; + + WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING)); + WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING)); + WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY)); + WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0)); + WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1)); + WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL)); + WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD)); + WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL)); + WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING)); + WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2)); + WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS)); + WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS)); + WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1)); + WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0)); + WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1)); + WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0)); + WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1)); + WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING)); + WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2)); + WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2)); + + ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table); + if (ret) + goto init_mc_done; + + ret = ci_copy_vbios_mc_reg_table(table, ci_table); + if (ret) + goto init_mc_done; + + ci_set_s0_mc_reg_index(ci_table); + + ret = ci_register_patching_mc_seq(adev, ci_table); + if (ret) + goto init_mc_done; + + ret = ci_set_mc_special_registers(adev, ci_table); + if (ret) + goto init_mc_done; + + ci_set_valid_flag(ci_table); + +init_mc_done: + kfree(table); + + return ret; +} + +static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev, + SMU7_Discrete_MCRegisters *mc_reg_table) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 i, j; + + for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { + if (pi->mc_reg_table.valid_flag & (1 << j)) { + if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; + mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); + mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); + i++; + } + } + + mc_reg_table->last = (u8)i; + + return 0; +} + +static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry, + SMU7_Discrete_MCRegisterSet *data, + u32 num_entries, u32 valid_flag) +{ + u32 i, j; + + for (i = 0, j = 0; j < num_entries; j++) { + if (valid_flag & (1 << j)) { + data->value[i] = cpu_to_be32(entry->mc_data[j]); + i++; + } + } +} + +static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, + const u32 memory_clock, + SMU7_Discrete_MCRegisterSet *mc_reg_table_data) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 i = 0; + + for(i = 0; i < pi->mc_reg_table.num_entries; i++) { + if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) + break; + } + + if ((i == pi->mc_reg_table.num_entries) && (i > 0)) + --i; + + ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], + mc_reg_table_data, pi->mc_reg_table.last, + pi->mc_reg_table.valid_flag); +} + +static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, + SMU7_Discrete_MCRegisters *mc_reg_table) +{ + struct ci_power_info *pi = ci_get_pi(adev); + u32 i; + + for (i = 0; i < pi->dpm_table.mclk_table.count; i++) + ci_convert_mc_reg_table_entry_to_smc(adev, + pi->dpm_table.mclk_table.dpm_levels[i].value, + &mc_reg_table->data[i]); +} + +static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + int ret; + + memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); + + ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table); + if (ret) + return ret; + ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table); + + return amdgpu_ci_copy_bytes_to_smc(adev, + pi->mc_reg_table_start, + (u8 *)&pi->smc_mc_reg_table, + sizeof(SMU7_Discrete_MCRegisters), + pi->sram_end); +} + +static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + + if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) + return 0; + + memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); + + ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table); + + return amdgpu_ci_copy_bytes_to_smc(adev, + pi->mc_reg_table_start + + offsetof(SMU7_Discrete_MCRegisters, data[0]), + (u8 *)&pi->smc_mc_reg_table.data[0], + sizeof(SMU7_Discrete_MCRegisterSet) * + pi->dpm_table.mclk_table.count, + pi->sram_end); +} + +static void ci_enable_voltage_control(struct amdgpu_device *adev) +{ + u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT); + + tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK; + WREG32_SMC(ixGENERAL_PWRMGT, tmp); +} + +static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev, + struct amdgpu_ps *amdgpu_state) +{ + struct ci_ps *state = ci_get_ps(amdgpu_state); + int i; + u16 pcie_speed, max_speed = 0; + + for (i = 0; i < state->performance_level_count; i++) { + pcie_speed = state->performance_levels[i].pcie_gen; + if (max_speed < pcie_speed) + max_speed = pcie_speed; + } + + return max_speed; +} + +static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev) +{ + u32 speed_cntl = 0; + + speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) & + PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK; + speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; + + return (u16)speed_cntl; +} + +static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev) +{ + u32 link_width = 0; + + link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) & + PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK; + link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; + + switch (link_width) { + case 1: + return 1; + case 2: + return 2; + case 3: + return 4; + case 4: + return 8; + case 0: + case 6: + default: + return 16; + } +} + +static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev, + struct amdgpu_ps *amdgpu_new_state, + struct amdgpu_ps *amdgpu_current_state) +{ + struct ci_power_info *pi = ci_get_pi(adev); + enum amdgpu_pcie_gen target_link_speed = + ci_get_maximum_link_speed(adev, amdgpu_new_state); + enum amdgpu_pcie_gen current_link_speed; + + if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID) + current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state); + else + current_link_speed = pi->force_pcie_gen; + + pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; + pi->pspp_notify_required = false; + if (target_link_speed > current_link_speed) { + switch (target_link_speed) { +#ifdef CONFIG_ACPI + case AMDGPU_PCIE_GEN3: + if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) + break; + pi->force_pcie_gen = AMDGPU_PCIE_GEN2; + if (current_link_speed == AMDGPU_PCIE_GEN2) + break; + case AMDGPU_PCIE_GEN2: + if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) + break; +#endif + default: + pi->force_pcie_gen = ci_get_current_pcie_speed(adev); + break; + } + } else { + if (target_link_speed < current_link_speed) + pi->pspp_notify_required = true; + } +} + +static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, + struct amdgpu_ps *amdgpu_new_state, + struct amdgpu_ps *amdgpu_current_state) +{ + struct ci_power_info *pi = ci_get_pi(adev); + enum amdgpu_pcie_gen target_link_speed = + ci_get_maximum_link_speed(adev, amdgpu_new_state); + u8 request; + + if (pi->pspp_notify_required) { + if (target_link_speed == AMDGPU_PCIE_GEN3) + request = PCIE_PERF_REQ_PECI_GEN3; + else if (target_link_speed == AMDGPU_PCIE_GEN2) + request = PCIE_PERF_REQ_PECI_GEN2; + else + request = PCIE_PERF_REQ_PECI_GEN1; + + if ((request == PCIE_PERF_REQ_PECI_GEN1) && + (ci_get_current_pcie_speed(adev) > 0)) + return; + +#ifdef CONFIG_ACPI + amdgpu_acpi_pcie_performance_request(adev, request, false); +#endif + } +} + +static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk; + struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table = + &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk; + + if (allowed_sclk_vddc_table == NULL) + return -EINVAL; + if (allowed_sclk_vddc_table->count < 1) + return -EINVAL; + if (allowed_mclk_vddc_table == NULL) + return -EINVAL; + if (allowed_mclk_vddc_table->count < 1) + return -EINVAL; + if (allowed_mclk_vddci_table == NULL) + return -EINVAL; + if (allowed_mclk_vddci_table->count < 1) + return -EINVAL; + + pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; + pi->max_vddc_in_pp_table = + allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; + + pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; + pi->max_vddci_in_pp_table = + allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; + + adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = + allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; + adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = + allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; + adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = + allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; + adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = + allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; + + return 0; +} + +static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; + u32 leakage_index; + + for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { + if (leakage_table->leakage_id[leakage_index] == *vddc) { + *vddc = leakage_table->actual_voltage[leakage_index]; + break; + } + } +} + +static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; + u32 leakage_index; + + for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { + if (leakage_table->leakage_id[leakage_index] == *vddci) { + *vddci = leakage_table->actual_voltage[leakage_index]; + break; + } + } +} + +static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev, + struct amdgpu_clock_voltage_dependency_table *table) +{ + u32 i; + + if (table) { + for (i = 0; i < table->count; i++) + ci_patch_with_vddc_leakage(adev, &table->entries[i].v); + } +} + +static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev, + struct amdgpu_clock_voltage_dependency_table *table) +{ + u32 i; + + if (table) { + for (i = 0; i < table->count; i++) + ci_patch_with_vddci_leakage(adev, &table->entries[i].v); + } +} + +static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev, + struct amdgpu_vce_clock_voltage_dependency_table *table) +{ + u32 i; + + if (table) { + for (i = 0; i < table->count; i++) + ci_patch_with_vddc_leakage(adev, &table->entries[i].v); + } +} + +static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev, + struct amdgpu_uvd_clock_voltage_dependency_table *table) +{ + u32 i; + + if (table) { + for (i = 0; i < table->count; i++) + ci_patch_with_vddc_leakage(adev, &table->entries[i].v); + } +} + +static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev, + struct amdgpu_phase_shedding_limits_table *table) +{ + u32 i; + + if (table) { + for (i = 0; i < table->count; i++) + ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage); + } +} + +static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev, + struct amdgpu_clock_and_voltage_limits *table) +{ + if (table) { + ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc); + ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci); + } +} + +static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev, + struct amdgpu_cac_leakage_table *table) +{ + u32 i; + + if (table) { + for (i = 0; i < table->count; i++) + ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc); + } +} + +static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev) +{ + + ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev, + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); + ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev, + &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); + ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev, + &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); + ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev, + &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); + ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev, + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); + ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev, + &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); + ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev, + &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); + ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev, + &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); + ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev, + &adev->pm.dpm.dyn_state.phase_shedding_limits_table); + ci_patch_clock_voltage_limits_with_vddc_leakage(adev, + &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); + ci_patch_clock_voltage_limits_with_vddc_leakage(adev, + &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc); + ci_patch_cac_leakage_table_with_vddc_leakage(adev, + &adev->pm.dpm.dyn_state.cac_leakage_table); + +} + +static void ci_update_current_ps(struct amdgpu_device *adev, + struct amdgpu_ps *rps) +{ + struct ci_ps *new_ps = ci_get_ps(rps); + struct ci_power_info *pi = ci_get_pi(adev); + + pi->current_rps = *rps; + pi->current_ps = *new_ps; + pi->current_rps.ps_priv = &pi->current_ps; +} + +static void ci_update_requested_ps(struct amdgpu_device *adev, + struct amdgpu_ps *rps) +{ + struct ci_ps *new_ps = ci_get_ps(rps); + struct ci_power_info *pi = ci_get_pi(adev); + + pi->requested_rps = *rps; + pi->requested_ps = *new_ps; + pi->requested_rps.ps_priv = &pi->requested_ps; +} + +static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; + struct amdgpu_ps *new_ps = &requested_ps; + + ci_update_requested_ps(adev, new_ps); + + ci_apply_state_adjust_rules(adev, &pi->requested_rps); + + return 0; +} + +static void ci_dpm_post_set_power_state(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct amdgpu_ps *new_ps = &pi->requested_rps; + + ci_update_current_ps(adev, new_ps); +} + + +static void ci_dpm_setup_asic(struct amdgpu_device *adev) +{ + ci_read_clock_registers(adev); + ci_enable_acpi_power_management(adev); + ci_init_sclk_t(adev); +} + +static int ci_dpm_enable(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; + int ret; + + if (amdgpu_ci_is_smc_running(adev)) + return -EINVAL; + if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { + ci_enable_voltage_control(adev); + ret = ci_construct_voltage_tables(adev); + if (ret) { + DRM_ERROR("ci_construct_voltage_tables failed\n"); + return ret; + } + } + if (pi->caps_dynamic_ac_timing) { + ret = ci_initialize_mc_reg_table(adev); + if (ret) + pi->caps_dynamic_ac_timing = false; + } + if (pi->dynamic_ss) + ci_enable_spread_spectrum(adev, true); + if (pi->thermal_protection) + ci_enable_thermal_protection(adev, true); + ci_program_sstp(adev); + ci_enable_display_gap(adev); + ci_program_vc(adev); + ret = ci_upload_firmware(adev); + if (ret) { + DRM_ERROR("ci_upload_firmware failed\n"); + return ret; + } + ret = ci_process_firmware_header(adev); + if (ret) { + DRM_ERROR("ci_process_firmware_header failed\n"); + return ret; + } + ret = ci_initial_switch_from_arb_f0_to_f1(adev); + if (ret) { + DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n"); + return ret; + } + ret = ci_init_smc_table(adev); + if (ret) { + DRM_ERROR("ci_init_smc_table failed\n"); + return ret; + } + ret = ci_init_arb_table_index(adev); + if (ret) { + DRM_ERROR("ci_init_arb_table_index failed\n"); + return ret; + } + if (pi->caps_dynamic_ac_timing) { + ret = ci_populate_initial_mc_reg_table(adev); + if (ret) { + DRM_ERROR("ci_populate_initial_mc_reg_table failed\n"); + return ret; + } + } + ret = ci_populate_pm_base(adev); + if (ret) { + DRM_ERROR("ci_populate_pm_base failed\n"); + return ret; + } + ci_dpm_start_smc(adev); + ci_enable_vr_hot_gpio_interrupt(adev); + ret = ci_notify_smc_display_change(adev, false); + if (ret) { + DRM_ERROR("ci_notify_smc_display_change failed\n"); + return ret; + } + ci_enable_sclk_control(adev, true); + ret = ci_enable_ulv(adev, true); + if (ret) { + DRM_ERROR("ci_enable_ulv failed\n"); + return ret; + } + ret = ci_enable_ds_master_switch(adev, true); + if (ret) { + DRM_ERROR("ci_enable_ds_master_switch failed\n"); + return ret; + } + ret = ci_start_dpm(adev); + if (ret) { + DRM_ERROR("ci_start_dpm failed\n"); + return ret; + } + ret = ci_enable_didt(adev, true); + if (ret) { + DRM_ERROR("ci_enable_didt failed\n"); + return ret; + } + ret = ci_enable_smc_cac(adev, true); + if (ret) { + DRM_ERROR("ci_enable_smc_cac failed\n"); + return ret; + } + ret = ci_enable_power_containment(adev, true); + if (ret) { + DRM_ERROR("ci_enable_power_containment failed\n"); + return ret; + } + + ret = ci_power_control_set_level(adev); + if (ret) { + DRM_ERROR("ci_power_control_set_level failed\n"); + return ret; + } + + ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true); + + ret = ci_enable_thermal_based_sclk_dpm(adev, true); + if (ret) { + DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n"); + return ret; + } + + ci_thermal_start_thermal_controller(adev); + + ci_update_current_ps(adev, boot_ps); + + if (adev->irq.installed && + amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) { +#if 0 + PPSMC_Result result; +#endif + ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, + CISLANDS_TEMP_RANGE_MAX); + if (ret) { + DRM_ERROR("ci_thermal_set_temperature_range failed\n"); + return ret; + } + amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, + AMDGPU_THERMAL_IRQ_LOW_TO_HIGH); + amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, + AMDGPU_THERMAL_IRQ_HIGH_TO_LOW); + +#if 0 + result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); + + if (result != PPSMC_Result_OK) + DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); +#endif + } + + return 0; +} + +static void ci_dpm_disable(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; + + amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, + AMDGPU_THERMAL_IRQ_LOW_TO_HIGH); + amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, + AMDGPU_THERMAL_IRQ_HIGH_TO_LOW); + + ci_dpm_powergate_uvd(adev, false); + + if (!amdgpu_ci_is_smc_running(adev)) + return; + + ci_thermal_stop_thermal_controller(adev); + + if (pi->thermal_protection) + ci_enable_thermal_protection(adev, false); + ci_enable_power_containment(adev, false); + ci_enable_smc_cac(adev, false); + ci_enable_didt(adev, false); + ci_enable_spread_spectrum(adev, false); + ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false); + ci_stop_dpm(adev); + ci_enable_ds_master_switch(adev, false); + ci_enable_ulv(adev, false); + ci_clear_vc(adev); + ci_reset_to_default(adev); + ci_dpm_stop_smc(adev); + ci_force_switch_to_arb_f0(adev); + ci_enable_thermal_based_sclk_dpm(adev, false); + + ci_update_current_ps(adev, boot_ps); +} + +static int ci_dpm_set_power_state(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct amdgpu_ps *new_ps = &pi->requested_rps; + struct amdgpu_ps *old_ps = &pi->current_rps; + int ret; + + ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps); + if (pi->pcie_performance_request) + ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps); + ret = ci_freeze_sclk_mclk_dpm(adev); + if (ret) { + DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n"); + return ret; + } + ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps); + if (ret) { + DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n"); + return ret; + } + ret = ci_generate_dpm_level_enable_mask(adev, new_ps); + if (ret) { + DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n"); + return ret; + } + + ret = ci_update_vce_dpm(adev, new_ps, old_ps); + if (ret) { + DRM_ERROR("ci_update_vce_dpm failed\n"); + return ret; + } + + ret = ci_update_sclk_t(adev); + if (ret) { + DRM_ERROR("ci_update_sclk_t failed\n"); + return ret; + } + if (pi->caps_dynamic_ac_timing) { + ret = ci_update_and_upload_mc_reg_table(adev); + if (ret) { + DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n"); + return ret; + } + } + ret = ci_program_memory_timing_parameters(adev); + if (ret) { + DRM_ERROR("ci_program_memory_timing_parameters failed\n"); + return ret; + } + ret = ci_unfreeze_sclk_mclk_dpm(adev); + if (ret) { + DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n"); + return ret; + } + ret = ci_upload_dpm_level_enable_mask(adev); + if (ret) { + DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n"); + return ret; + } + if (pi->pcie_performance_request) + ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps); + + return 0; +} + +#if 0 +static void ci_dpm_reset_asic(struct amdgpu_device *adev) +{ + ci_set_boot_state(adev); +} +#endif + +static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev) +{ + ci_program_display_gap(adev); +} + +union power_info { + struct _ATOM_POWERPLAY_INFO info; + struct _ATOM_POWERPLAY_INFO_V2 info_2; + struct _ATOM_POWERPLAY_INFO_V3 info_3; + struct _ATOM_PPLIB_POWERPLAYTABLE pplib; + struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; + struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; +}; + +union pplib_clock_info { + struct _ATOM_PPLIB_R600_CLOCK_INFO r600; + struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; + struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; + struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; + struct _ATOM_PPLIB_SI_CLOCK_INFO si; + struct _ATOM_PPLIB_CI_CLOCK_INFO ci; +}; + +union pplib_power_state { + struct _ATOM_PPLIB_STATE v1; + struct _ATOM_PPLIB_STATE_V2 v2; +}; + +static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev, + struct amdgpu_ps *rps, + struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, + u8 table_rev) +{ + rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); + rps->class = le16_to_cpu(non_clock_info->usClassification); + rps->class2 = le16_to_cpu(non_clock_info->usClassification2); + + if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { + rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); + rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); + } else { + rps->vclk = 0; + rps->dclk = 0; + } + + if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) + adev->pm.dpm.boot_ps = rps; + if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) + adev->pm.dpm.uvd_ps = rps; +} + +static void ci_parse_pplib_clock_info(struct amdgpu_device *adev, + struct amdgpu_ps *rps, int index, + union pplib_clock_info *clock_info) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_ps *ps = ci_get_ps(rps); + struct ci_pl *pl = &ps->performance_levels[index]; + + ps->performance_level_count = index + 1; + + pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); + pl->sclk |= clock_info->ci.ucEngineClockHigh << 16; + pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); + pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16; + + pl->pcie_gen = amdgpu_get_pcie_gen_support(adev, + pi->sys_pcie_mask, + pi->vbios_boot_state.pcie_gen_bootup_value, + clock_info->ci.ucPCIEGen); + pl->pcie_lane = amdgpu_get_pcie_lane_support(adev, + pi->vbios_boot_state.pcie_lane_bootup_value, + le16_to_cpu(clock_info->ci.usPCIELane)); + + if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { + pi->acpi_pcie_gen = pl->pcie_gen; + } + + if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { + pi->ulv.supported = true; + pi->ulv.pl = *pl; + pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; + } + + /* patch up boot state */ + if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { + pl->mclk = pi->vbios_boot_state.mclk_bootup_value; + pl->sclk = pi->vbios_boot_state.sclk_bootup_value; + pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; + pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; + } + + switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { + case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: + pi->use_pcie_powersaving_levels = true; + if (pi->pcie_gen_powersaving.max < pl->pcie_gen) + pi->pcie_gen_powersaving.max = pl->pcie_gen; + if (pi->pcie_gen_powersaving.min > pl->pcie_gen) + pi->pcie_gen_powersaving.min = pl->pcie_gen; + if (pi->pcie_lane_powersaving.max < pl->pcie_lane) + pi->pcie_lane_powersaving.max = pl->pcie_lane; + if (pi->pcie_lane_powersaving.min > pl->pcie_lane) + pi->pcie_lane_powersaving.min = pl->pcie_lane; + break; + case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: + pi->use_pcie_performance_levels = true; + if (pi->pcie_gen_performance.max < pl->pcie_gen) + pi->pcie_gen_performance.max = pl->pcie_gen; + if (pi->pcie_gen_performance.min > pl->pcie_gen) + pi->pcie_gen_performance.min = pl->pcie_gen; + if (pi->pcie_lane_performance.max < pl->pcie_lane) + pi->pcie_lane_performance.max = pl->pcie_lane; + if (pi->pcie_lane_performance.min > pl->pcie_lane) + pi->pcie_lane_performance.min = pl->pcie_lane; + break; + default: + break; + } +} + +static int ci_parse_power_table(struct amdgpu_device *adev) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; + union pplib_power_state *power_state; + int i, j, k, non_clock_array_index, clock_array_index; + union pplib_clock_info *clock_info; + struct _StateArray *state_array; + struct _ClockInfoArray *clock_info_array; + struct _NonClockInfoArray *non_clock_info_array; + union power_info *power_info; + int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); + u16 data_offset; + u8 frev, crev; + u8 *power_state_offset; + struct ci_ps *ps; + + if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) + return -EINVAL; + power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); + + amdgpu_add_thermal_controller(adev); + + state_array = (struct _StateArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usStateArrayOffset)); + clock_info_array = (struct _ClockInfoArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); + non_clock_info_array = (struct _NonClockInfoArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); + + adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) * + state_array->ucNumEntries, GFP_KERNEL); + if (!adev->pm.dpm.ps) + return -ENOMEM; + power_state_offset = (u8 *)state_array->states; + for (i = 0; i < state_array->ucNumEntries; i++) { + u8 *idx; + power_state = (union pplib_power_state *)power_state_offset; + non_clock_array_index = power_state->v2.nonClockInfoIndex; + non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) + &non_clock_info_array->nonClockInfo[non_clock_array_index]; + ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL); + if (ps == NULL) { + kfree(adev->pm.dpm.ps); + return -ENOMEM; + } + adev->pm.dpm.ps[i].ps_priv = ps; + ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], + non_clock_info, + non_clock_info_array->ucEntrySize); + k = 0; + idx = (u8 *)&power_state->v2.clockInfoIndex[0]; + for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { + clock_array_index = idx[j]; + if (clock_array_index >= clock_info_array->ucNumEntries) + continue; + if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS) + break; + clock_info = (union pplib_clock_info *) + ((u8 *)&clock_info_array->clockInfo[0] + + (clock_array_index * clock_info_array->ucEntrySize)); + ci_parse_pplib_clock_info(adev, + &adev->pm.dpm.ps[i], k, + clock_info); + k++; + } + power_state_offset += 2 + power_state->v2.ucNumDPMLevels; + } + adev->pm.dpm.num_ps = state_array->ucNumEntries; + + /* fill in the vce power states */ + for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) { + u32 sclk, mclk; + clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; + clock_info = (union pplib_clock_info *) + &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; + sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); + sclk |= clock_info->ci.ucEngineClockHigh << 16; + mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); + mclk |= clock_info->ci.ucMemoryClockHigh << 16; + adev->pm.dpm.vce_states[i].sclk = sclk; + adev->pm.dpm.vce_states[i].mclk = mclk; + } + + return 0; +} + +static int ci_get_vbios_boot_values(struct amdgpu_device *adev, + struct ci_vbios_boot_state *boot_state) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); + ATOM_FIRMWARE_INFO_V2_2 *firmware_info; + u8 frev, crev; + u16 data_offset; + + if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) { + firmware_info = + (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios + + data_offset); + boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage); + boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage); + boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage); + boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev); + boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev); + boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock); + boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock); + + return 0; + } + return -EINVAL; +} + +static void ci_dpm_fini(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->pm.dpm.num_ps; i++) { + kfree(adev->pm.dpm.ps[i].ps_priv); + } + kfree(adev->pm.dpm.ps); + kfree(adev->pm.dpm.priv); + kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); + amdgpu_free_extended_power_table(adev); +} + +/** + * ci_dpm_init_microcode - load ucode images from disk + * + * @adev: amdgpu_device pointer + * + * Use the firmware interface to load the ucode images into + * the driver (not loaded into hw). + * Returns 0 on success, error on failure. + */ +static int ci_dpm_init_microcode(struct amdgpu_device *adev) +{ + const char *chip_name; + char fw_name[30]; + int err; + + DRM_DEBUG("\n"); + + switch (adev->asic_type) { + case CHIP_BONAIRE: + chip_name = "bonaire"; + break; + case CHIP_HAWAII: + chip_name = "hawaii"; + break; + case CHIP_KAVERI: + case CHIP_KABINI: + default: BUG(); + } + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); + err = request_firmware(&adev->pm.fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->pm.fw); + +out: + if (err) { + printk(KERN_ERR + "cik_smc: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(adev->pm.fw); + adev->pm.fw = NULL; + } + return err; +} + +static int ci_dpm_init(struct amdgpu_device *adev) +{ + int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); + SMU7_Discrete_DpmTable *dpm_table; + struct amdgpu_gpio_rec gpio; + u16 data_offset, size; + u8 frev, crev; + struct ci_power_info *pi; + int ret; + u32 mask; + + ret = ci_dpm_init_microcode(adev); + if (ret) + return ret; + + pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); + if (pi == NULL) + return -ENOMEM; + adev->pm.dpm.priv = pi; + + ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); + if (ret) + pi->sys_pcie_mask = 0; + else + pi->sys_pcie_mask = mask; + pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; + + pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1; + pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3; + pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1; + pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3; + + pi->pcie_lane_performance.max = 0; + pi->pcie_lane_performance.min = 16; + pi->pcie_lane_powersaving.max = 0; + pi->pcie_lane_powersaving.min = 16; + + ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state); + if (ret) { + ci_dpm_fini(adev); + return ret; + } + + ret = amdgpu_get_platform_caps(adev); + if (ret) { + ci_dpm_fini(adev); + return ret; + } + + ret = amdgpu_parse_extended_power_table(adev); + if (ret) { + ci_dpm_fini(adev); + return ret; + } + + ret = ci_parse_power_table(adev); + if (ret) { + ci_dpm_fini(adev); + return ret; + } + + pi->dll_default_on = false; + pi->sram_end = SMC_RAM_END; + + pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; + pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; + pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; + pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; + pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; + pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; + pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; + pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; + + pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; + + pi->sclk_dpm_key_disabled = 0; + pi->mclk_dpm_key_disabled = 0; + pi->pcie_dpm_key_disabled = 0; + pi->thermal_sclk_dpm_enabled = 0; + + pi->caps_sclk_ds = true; + + pi->mclk_strobe_mode_threshold = 40000; + pi->mclk_stutter_mode_threshold = 40000; + pi->mclk_edc_enable_threshold = 40000; + pi->mclk_edc_wr_enable_threshold = 40000; + + ci_initialize_powertune_defaults(adev); + + pi->caps_fps = false; + + pi->caps_sclk_throttle_low_notification = false; + + pi->caps_uvd_dpm = true; + pi->caps_vce_dpm = true; + + ci_get_leakage_voltages(adev); + ci_patch_dependency_tables_with_leakage(adev); + ci_set_private_data_variables_based_on_pptable(adev); + + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = + kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL); + if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { + ci_dpm_fini(adev); + return -ENOMEM; + } + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; + adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; + + adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; + adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; + adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; + + adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; + adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; + adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; + adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; + + if (adev->asic_type == CHIP_HAWAII) { + pi->thermal_temp_setting.temperature_low = 94500; + pi->thermal_temp_setting.temperature_high = 95000; + pi->thermal_temp_setting.temperature_shutdown = 104000; + } else { + pi->thermal_temp_setting.temperature_low = 99500; + pi->thermal_temp_setting.temperature_high = 100000; + pi->thermal_temp_setting.temperature_shutdown = 104000; + } + + pi->uvd_enabled = false; + + dpm_table = &pi->smc_state_table; + + gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID); + if (gpio.valid) { + dpm_table->VRHotGpio = gpio.shift; + adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; + } else { + dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN; + adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; + } + + gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID); + if (gpio.valid) { + dpm_table->AcDcGpio = gpio.shift; + adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; + } else { + dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN; + adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; + } + + gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID); + if (gpio.valid) { + u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL); + + switch (gpio.shift) { + case 0: + tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK; + tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT; + break; + case 1: + tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK; + tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT; + break; + case 2: + tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK; + break; + case 3: + tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK; + break; + case 4: + tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK; + break; + default: + DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift); + break; + } + WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp); + } + + pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; + pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; + pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; + if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) + pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; + else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) + pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; + + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { + if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) + pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; + else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) + pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; + else + adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; + } + + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { + if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) + pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; + else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) + pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; + else + adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; + } + + pi->vddc_phase_shed_control = true; + +#if defined(CONFIG_ACPI) + pi->pcie_performance_request = + amdgpu_acpi_is_pcie_performance_request_supported(adev); +#else + pi->pcie_performance_request = false; +#endif + + if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, + &frev, &crev, &data_offset)) { + pi->caps_sclk_ss_support = true; + pi->caps_mclk_ss_support = true; + pi->dynamic_ss = true; + } else { + pi->caps_sclk_ss_support = false; + pi->caps_mclk_ss_support = false; + pi->dynamic_ss = true; + } + + if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE) + pi->thermal_protection = true; + else + pi->thermal_protection = false; + + pi->caps_dynamic_ac_timing = true; + + pi->uvd_power_gated = false; + + /* make sure dc limits are valid */ + if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || + (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) + adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = + adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; + + pi->fan_ctrl_is_in_default_mode = true; + + return 0; +} + +static void +ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, + struct seq_file *m) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct amdgpu_ps *rps = &pi->current_rps; + u32 sclk = ci_get_average_sclk_freq(adev); + u32 mclk = ci_get_average_mclk_freq(adev); + + seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); + seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis"); + seq_printf(m, "power level avg sclk: %u mclk: %u\n", + sclk, mclk); +} + +static void ci_dpm_print_power_state(struct amdgpu_device *adev, + struct amdgpu_ps *rps) +{ + struct ci_ps *ps = ci_get_ps(rps); + struct ci_pl *pl; + int i; + + amdgpu_dpm_print_class_info(rps->class, rps->class2); + amdgpu_dpm_print_cap_info(rps->caps); + printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); + for (i = 0; i < ps->performance_level_count; i++) { + pl = &ps->performance_levels[i]; + printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n", + i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane); + } + amdgpu_dpm_print_ps_status(adev, rps); +} + +static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); + + if (low) + return requested_state->performance_levels[0].sclk; + else + return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; +} + +static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); + + if (low) + return requested_state->performance_levels[0].mclk; + else + return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; +} + +/* get temperature in millidegrees */ +static int ci_dpm_get_temp(struct amdgpu_device *adev) +{ + u32 temp; + int actual_temp = 0; + + temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> + CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; + + if (temp & 0x200) + actual_temp = 255; + else + actual_temp = temp & 0x1ff; + + actual_temp = actual_temp * 1000; + + return actual_temp; +} + +static int ci_set_temperature_range(struct amdgpu_device *adev) +{ + int ret; + + ret = ci_thermal_enable_alert(adev, false); + if (ret) + return ret; + ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, + CISLANDS_TEMP_RANGE_MAX); + if (ret) + return ret; + ret = ci_thermal_enable_alert(adev, true); + if (ret) + return ret; + return ret; +} + +static int ci_dpm_early_init(struct amdgpu_device *adev) +{ + ci_dpm_set_dpm_funcs(adev); + ci_dpm_set_irq_funcs(adev); + + return 0; +} + +static int ci_dpm_late_init(struct amdgpu_device *adev) +{ + int ret; + + if (!amdgpu_dpm) + return 0; + + ret = ci_set_temperature_range(adev); + if (ret) + return ret; + + ci_dpm_powergate_uvd(adev, true); + + return 0; +} + +static int ci_dpm_sw_init(struct amdgpu_device *adev) +{ + int ret; + + ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); + if (ret) + return ret; + + ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq); + if (ret) + return ret; + + /* default to balanced state */ + adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; + adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; + adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO; + adev->pm.default_sclk = adev->clock.default_sclk; + adev->pm.default_mclk = adev->clock.default_mclk; + adev->pm.current_sclk = adev->clock.default_sclk; + adev->pm.current_mclk = adev->clock.default_mclk; + adev->pm.int_thermal_type = THERMAL_TYPE_NONE; + + if (amdgpu_dpm == 0) + return 0; + + INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); + mutex_lock(&adev->pm.mutex); + ret = ci_dpm_init(adev); + if (ret) + goto dpm_failed; + adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; + if (amdgpu_dpm == 1) + amdgpu_pm_print_power_states(adev); + ret = amdgpu_pm_sysfs_init(adev); + if (ret) + goto dpm_failed; + mutex_unlock(&adev->pm.mutex); + DRM_INFO("amdgpu: dpm initialized\n"); + + return 0; + +dpm_failed: + ci_dpm_fini(adev); + mutex_unlock(&adev->pm.mutex); + DRM_ERROR("amdgpu: dpm initialization failed\n"); + return ret; +} + +static int ci_dpm_sw_fini(struct amdgpu_device *adev) +{ + mutex_lock(&adev->pm.mutex); + amdgpu_pm_sysfs_fini(adev); + ci_dpm_fini(adev); + mutex_unlock(&adev->pm.mutex); + + return 0; +} + +static int ci_dpm_hw_init(struct amdgpu_device *adev) +{ + int ret; + + if (!amdgpu_dpm) + return 0; + + mutex_lock(&adev->pm.mutex); + ci_dpm_setup_asic(adev); + ret = ci_dpm_enable(adev); + if (ret) + adev->pm.dpm_enabled = false; + else + adev->pm.dpm_enabled = true; + mutex_unlock(&adev->pm.mutex); + + return ret; +} + +static int ci_dpm_hw_fini(struct amdgpu_device *adev) +{ + if (adev->pm.dpm_enabled) { + mutex_lock(&adev->pm.mutex); + ci_dpm_disable(adev); + mutex_unlock(&adev->pm.mutex); + } + + return 0; +} + +static int ci_dpm_suspend(struct amdgpu_device *adev) +{ + if (adev->pm.dpm_enabled) { + mutex_lock(&adev->pm.mutex); + /* disable dpm */ + ci_dpm_disable(adev); + /* reset the power state */ + adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; + mutex_unlock(&adev->pm.mutex); + } + return 0; +} + +static int ci_dpm_resume(struct amdgpu_device *adev) +{ + int ret; + + if (adev->pm.dpm_enabled) { + /* asic init will reset to the boot state */ + mutex_lock(&adev->pm.mutex); + ci_dpm_setup_asic(adev); + ret = ci_dpm_enable(adev); + if (ret) + adev->pm.dpm_enabled = false; + else + adev->pm.dpm_enabled = true; + mutex_unlock(&adev->pm.mutex); + if (adev->pm.dpm_enabled) + amdgpu_pm_compute_clocks(adev); + } + return 0; +} + +static bool ci_dpm_is_idle(struct amdgpu_device *adev) +{ + /* XXX */ + return true; +} + +static int ci_dpm_wait_for_idle(struct amdgpu_device *adev) +{ + /* XXX */ + return 0; +} + +static void ci_dpm_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "CIK DPM registers\n"); + dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n", + RREG32(mmBIOS_SCRATCH_4)); + dev_info(adev->dev, " MC_ARB_DRAM_TIMING=0x%08X\n", + RREG32(mmMC_ARB_DRAM_TIMING)); + dev_info(adev->dev, " MC_ARB_DRAM_TIMING2=0x%08X\n", + RREG32(mmMC_ARB_DRAM_TIMING2)); + dev_info(adev->dev, " MC_ARB_BURST_TIME=0x%08X\n", + RREG32(mmMC_ARB_BURST_TIME)); + dev_info(adev->dev, " MC_ARB_DRAM_TIMING_1=0x%08X\n", + RREG32(mmMC_ARB_DRAM_TIMING_1)); + dev_info(adev->dev, " MC_ARB_DRAM_TIMING2_1=0x%08X\n", + RREG32(mmMC_ARB_DRAM_TIMING2_1)); + dev_info(adev->dev, " MC_CG_CONFIG=0x%08X\n", + RREG32(mmMC_CG_CONFIG)); + dev_info(adev->dev, " MC_ARB_CG=0x%08X\n", + RREG32(mmMC_ARB_CG)); + dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n", + RREG32_DIDT(ixDIDT_SQ_CTRL0)); + dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n", + RREG32_DIDT(ixDIDT_DB_CTRL0)); + dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n", + RREG32_DIDT(ixDIDT_TD_CTRL0)); + dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n", + RREG32_DIDT(ixDIDT_TCP_CTRL0)); + dev_info(adev->dev, " CG_THERMAL_INT=0x%08X\n", + RREG32_SMC(ixCG_THERMAL_INT)); + dev_info(adev->dev, " CG_THERMAL_CTRL=0x%08X\n", + RREG32_SMC(ixCG_THERMAL_CTRL)); + dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n", + RREG32_SMC(ixGENERAL_PWRMGT)); + dev_info(adev->dev, " MC_SEQ_CNTL_3=0x%08X\n", + RREG32(mmMC_SEQ_CNTL_3)); + dev_info(adev->dev, " LCAC_MC0_CNTL=0x%08X\n", + RREG32_SMC(ixLCAC_MC0_CNTL)); + dev_info(adev->dev, " LCAC_MC1_CNTL=0x%08X\n", + RREG32_SMC(ixLCAC_MC1_CNTL)); + dev_info(adev->dev, " LCAC_CPL_CNTL=0x%08X\n", + RREG32_SMC(ixLCAC_CPL_CNTL)); + dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n", + RREG32_SMC(ixSCLK_PWRMGT_CNTL)); + dev_info(adev->dev, " BIF_LNCNT_RESET=0x%08X\n", + RREG32(mmBIF_LNCNT_RESET)); + dev_info(adev->dev, " FIRMWARE_FLAGS=0x%08X\n", + RREG32_SMC(ixFIRMWARE_FLAGS)); + dev_info(adev->dev, " CG_SPLL_FUNC_CNTL=0x%08X\n", + RREG32_SMC(ixCG_SPLL_FUNC_CNTL)); + dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_2=0x%08X\n", + RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2)); + dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_3=0x%08X\n", + RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3)); + dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_4=0x%08X\n", + RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4)); + dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM=0x%08X\n", + RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM)); + dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n", + RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2)); + dev_info(adev->dev, " DLL_CNTL=0x%08X\n", + RREG32(mmDLL_CNTL)); + dev_info(adev->dev, " MCLK_PWRMGT_CNTL=0x%08X\n", + RREG32(mmMCLK_PWRMGT_CNTL)); + dev_info(adev->dev, " MPLL_AD_FUNC_CNTL=0x%08X\n", + RREG32(mmMPLL_AD_FUNC_CNTL)); + dev_info(adev->dev, " MPLL_DQ_FUNC_CNTL=0x%08X\n", + RREG32(mmMPLL_DQ_FUNC_CNTL)); + dev_info(adev->dev, " MPLL_FUNC_CNTL=0x%08X\n", + RREG32(mmMPLL_FUNC_CNTL)); + dev_info(adev->dev, " MPLL_FUNC_CNTL_1=0x%08X\n", + RREG32(mmMPLL_FUNC_CNTL_1)); + dev_info(adev->dev, " MPLL_FUNC_CNTL_2=0x%08X\n", + RREG32(mmMPLL_FUNC_CNTL_2)); + dev_info(adev->dev, " MPLL_SS1=0x%08X\n", + RREG32(mmMPLL_SS1)); + dev_info(adev->dev, " MPLL_SS2=0x%08X\n", + RREG32(mmMPLL_SS2)); + dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL=0x%08X\n", + RREG32_SMC(ixCG_DISPLAY_GAP_CNTL)); + dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL2=0x%08X\n", + RREG32_SMC(ixCG_DISPLAY_GAP_CNTL2)); + dev_info(adev->dev, " CG_STATIC_SCREEN_PARAMETER=0x%08X\n", + RREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER)); + dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n", + RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0)); + dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_1=0x%08X\n", + RREG32_SMC(ixCG_FREQ_TRAN_VOTING_1)); + dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_2=0x%08X\n", + RREG32_SMC(ixCG_FREQ_TRAN_VOTING_2)); + dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_3=0x%08X\n", + RREG32_SMC(ixCG_FREQ_TRAN_VOTING_3)); + dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_4=0x%08X\n", + RREG32_SMC(ixCG_FREQ_TRAN_VOTING_4)); + dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_5=0x%08X\n", + RREG32_SMC(ixCG_FREQ_TRAN_VOTING_5)); + dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_6=0x%08X\n", + RREG32_SMC(ixCG_FREQ_TRAN_VOTING_6)); + dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_7=0x%08X\n", + RREG32_SMC(ixCG_FREQ_TRAN_VOTING_7)); + dev_info(adev->dev, " RCU_UC_EVENTS=0x%08X\n", + RREG32_SMC(ixRCU_UC_EVENTS)); + dev_info(adev->dev, " DPM_TABLE_475=0x%08X\n", + RREG32_SMC(ixDPM_TABLE_475)); + dev_info(adev->dev, " MC_SEQ_RAS_TIMING_LP=0x%08X\n", + RREG32(mmMC_SEQ_RAS_TIMING_LP)); + dev_info(adev->dev, " MC_SEQ_RAS_TIMING=0x%08X\n", + RREG32(mmMC_SEQ_RAS_TIMING)); + dev_info(adev->dev, " MC_SEQ_CAS_TIMING_LP=0x%08X\n", + RREG32(mmMC_SEQ_CAS_TIMING_LP)); + dev_info(adev->dev, " MC_SEQ_CAS_TIMING=0x%08X\n", + RREG32(mmMC_SEQ_CAS_TIMING)); + dev_info(adev->dev, " MC_SEQ_DLL_STBY_LP=0x%08X\n", + RREG32(mmMC_SEQ_DLL_STBY_LP)); + dev_info(adev->dev, " MC_SEQ_DLL_STBY=0x%08X\n", + RREG32(mmMC_SEQ_DLL_STBY)); + dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0_LP=0x%08X\n", + RREG32(mmMC_SEQ_G5PDX_CMD0_LP)); + dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0=0x%08X\n", + RREG32(mmMC_SEQ_G5PDX_CMD0)); + dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1_LP=0x%08X\n", + RREG32(mmMC_SEQ_G5PDX_CMD1_LP)); + dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1=0x%08X\n", + RREG32(mmMC_SEQ_G5PDX_CMD1)); + dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL_LP=0x%08X\n", + RREG32(mmMC_SEQ_G5PDX_CTRL_LP)); + dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL=0x%08X\n", + RREG32(mmMC_SEQ_G5PDX_CTRL)); + dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n", + RREG32(mmMC_SEQ_PMG_DVS_CMD_LP)); + dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD=0x%08X\n", + RREG32(mmMC_SEQ_PMG_DVS_CMD)); + dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n", + RREG32(mmMC_SEQ_PMG_DVS_CTL_LP)); + dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL=0x%08X\n", + RREG32(mmMC_SEQ_PMG_DVS_CTL)); + dev_info(adev->dev, " MC_SEQ_MISC_TIMING_LP=0x%08X\n", + RREG32(mmMC_SEQ_MISC_TIMING_LP)); + dev_info(adev->dev, " MC_SEQ_MISC_TIMING=0x%08X\n", + RREG32(mmMC_SEQ_MISC_TIMING)); + dev_info(adev->dev, " MC_SEQ_MISC_TIMING2_LP=0x%08X\n", + RREG32(mmMC_SEQ_MISC_TIMING2_LP)); + dev_info(adev->dev, " MC_SEQ_MISC_TIMING2=0x%08X\n", + RREG32(mmMC_SEQ_MISC_TIMING2)); + dev_info(adev->dev, " MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n", + RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP)); + dev_info(adev->dev, " MC_PMG_CMD_EMRS=0x%08X\n", + RREG32(mmMC_PMG_CMD_EMRS)); + dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n", + RREG32(mmMC_SEQ_PMG_CMD_MRS_LP)); + dev_info(adev->dev, " MC_PMG_CMD_MRS=0x%08X\n", + RREG32(mmMC_PMG_CMD_MRS)); + dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n", + RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP)); + dev_info(adev->dev, " MC_PMG_CMD_MRS1=0x%08X\n", + RREG32(mmMC_PMG_CMD_MRS1)); + dev_info(adev->dev, " MC_SEQ_WR_CTL_D0_LP=0x%08X\n", + RREG32(mmMC_SEQ_WR_CTL_D0_LP)); + dev_info(adev->dev, " MC_SEQ_WR_CTL_D0=0x%08X\n", + RREG32(mmMC_SEQ_WR_CTL_D0)); + dev_info(adev->dev, " MC_SEQ_WR_CTL_D1_LP=0x%08X\n", + RREG32(mmMC_SEQ_WR_CTL_D1_LP)); + dev_info(adev->dev, " MC_SEQ_WR_CTL_D1=0x%08X\n", + RREG32(mmMC_SEQ_WR_CTL_D1)); + dev_info(adev->dev, " MC_SEQ_RD_CTL_D0_LP=0x%08X\n", + RREG32(mmMC_SEQ_RD_CTL_D0_LP)); + dev_info(adev->dev, " MC_SEQ_RD_CTL_D0=0x%08X\n", + RREG32(mmMC_SEQ_RD_CTL_D0)); + dev_info(adev->dev, " MC_SEQ_RD_CTL_D1_LP=0x%08X\n", + RREG32(mmMC_SEQ_RD_CTL_D1_LP)); + dev_info(adev->dev, " MC_SEQ_RD_CTL_D1=0x%08X\n", + RREG32(mmMC_SEQ_RD_CTL_D1)); + dev_info(adev->dev, " MC_SEQ_PMG_TIMING_LP=0x%08X\n", + RREG32(mmMC_SEQ_PMG_TIMING_LP)); + dev_info(adev->dev, " MC_SEQ_PMG_TIMING=0x%08X\n", + RREG32(mmMC_SEQ_PMG_TIMING)); + dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n", + RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP)); + dev_info(adev->dev, " MC_PMG_CMD_MRS2=0x%08X\n", + RREG32(mmMC_PMG_CMD_MRS2)); + dev_info(adev->dev, " MC_SEQ_WR_CTL_2_LP=0x%08X\n", + RREG32(mmMC_SEQ_WR_CTL_2_LP)); + dev_info(adev->dev, " MC_SEQ_WR_CTL_2=0x%08X\n", + RREG32(mmMC_SEQ_WR_CTL_2)); + dev_info(adev->dev, " PCIE_LC_SPEED_CNTL=0x%08X\n", + RREG32_PCIE(ixPCIE_LC_SPEED_CNTL)); + dev_info(adev->dev, " PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n", + RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL)); + dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n", + RREG32(mmSMC_IND_INDEX_0)); + dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n", + RREG32(mmSMC_IND_DATA_0)); + dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n", + RREG32(mmSMC_IND_ACCESS_CNTL)); + dev_info(adev->dev, " SMC_RESP_0=0x%08X\n", + RREG32(mmSMC_RESP_0)); + dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n", + RREG32(mmSMC_MESSAGE_0)); + dev_info(adev->dev, " SMC_SYSCON_RESET_CNTL=0x%08X\n", + RREG32_SMC(ixSMC_SYSCON_RESET_CNTL)); + dev_info(adev->dev, " SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n", + RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0)); + dev_info(adev->dev, " SMC_SYSCON_MISC_CNTL=0x%08X\n", + RREG32_SMC(ixSMC_SYSCON_MISC_CNTL)); + dev_info(adev->dev, " SMC_PC_C=0x%08X\n", + RREG32_SMC(ixSMC_PC_C)); +} + +static int ci_dpm_soft_reset(struct amdgpu_device *adev) +{ + return 0; +} + +static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 cg_thermal_int; + + switch (type) { + case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH: + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT); + cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; + WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT); + cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; + WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int); + break; + default: + break; + } + break; + + case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW: + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT); + cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; + WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT); + cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; + WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int); + break; + default: + break; + } + break; + + default: + break; + } + return 0; +} + +static int ci_dpm_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + bool queue_thermal = false; + + if (entry == NULL) + return -EINVAL; + + switch (entry->src_id) { + case 230: /* thermal low to high */ + DRM_DEBUG("IH: thermal low to high\n"); + adev->pm.dpm.thermal.high_to_low = false; + queue_thermal = true; + break; + case 231: /* thermal high to low */ + DRM_DEBUG("IH: thermal high to low\n"); + adev->pm.dpm.thermal.high_to_low = true; + queue_thermal = true; + break; + default: + break; + } + + if (queue_thermal) + schedule_work(&adev->pm.dpm.thermal.work); + + return 0; +} + +static int ci_dpm_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static int ci_dpm_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs ci_dpm_ip_funcs = { + .early_init = ci_dpm_early_init, + .late_init = ci_dpm_late_init, + .sw_init = ci_dpm_sw_init, + .sw_fini = ci_dpm_sw_fini, + .hw_init = ci_dpm_hw_init, + .hw_fini = ci_dpm_hw_fini, + .suspend = ci_dpm_suspend, + .resume = ci_dpm_resume, + .is_idle = ci_dpm_is_idle, + .wait_for_idle = ci_dpm_wait_for_idle, + .soft_reset = ci_dpm_soft_reset, + .print_status = ci_dpm_print_status, + .set_clockgating_state = ci_dpm_set_clockgating_state, + .set_powergating_state = ci_dpm_set_powergating_state, +}; + +static const struct amdgpu_dpm_funcs ci_dpm_funcs = { + .get_temperature = &ci_dpm_get_temp, + .pre_set_power_state = &ci_dpm_pre_set_power_state, + .set_power_state = &ci_dpm_set_power_state, + .post_set_power_state = &ci_dpm_post_set_power_state, + .display_configuration_changed = &ci_dpm_display_configuration_changed, + .get_sclk = &ci_dpm_get_sclk, + .get_mclk = &ci_dpm_get_mclk, + .print_power_state = &ci_dpm_print_power_state, + .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, + .force_performance_level = &ci_dpm_force_performance_level, + .vblank_too_short = &ci_dpm_vblank_too_short, + .powergate_uvd = &ci_dpm_powergate_uvd, + .set_fan_control_mode = &ci_dpm_set_fan_control_mode, + .get_fan_control_mode = &ci_dpm_get_fan_control_mode, + .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent, + .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent, +}; + +static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev) +{ + if (adev->pm.funcs == NULL) + adev->pm.funcs = &ci_dpm_funcs; +} + +static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = { + .set = ci_dpm_set_interrupt_state, + .process = ci_dpm_process_interrupt, +}; + +static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; + adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.h b/drivers/gpu/drm/amd/amdgpu/ci_dpm.h new file mode 100644 index 000000000000..faccc30c93bf --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.h @@ -0,0 +1,348 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __CI_DPM_H__ +#define __CI_DPM_H__ + +#include "amdgpu_atombios.h" +#include "ppsmc.h" + +#define SMU__NUM_SCLK_DPM_STATE 8 +#define SMU__NUM_MCLK_DPM_LEVELS 6 +#define SMU__NUM_LCLK_DPM_LEVELS 8 +#define SMU__NUM_PCIE_DPM_LEVELS 8 +#include "smu7_discrete.h" + +#define CISLANDS_MAX_HARDWARE_POWERLEVELS 2 + +#define CISLANDS_UNUSED_GPIO_PIN 0x7F + +struct ci_pl { + u32 mclk; + u32 sclk; + enum amdgpu_pcie_gen pcie_gen; + u16 pcie_lane; +}; + +struct ci_ps { + u16 performance_level_count; + bool dc_compatible; + u32 sclk_t; + struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS]; +}; + +struct ci_dpm_level { + bool enabled; + u32 value; + u32 param1; +}; + +#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5 +#define MAX_REGULAR_DPM_NUMBER 8 +#define CISLAND_MINIMUM_ENGINE_CLOCK 800 + +struct ci_single_dpm_table { + u32 count; + struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; +}; + +struct ci_dpm_table { + struct ci_single_dpm_table sclk_table; + struct ci_single_dpm_table mclk_table; + struct ci_single_dpm_table pcie_speed_table; + struct ci_single_dpm_table vddc_table; + struct ci_single_dpm_table vddci_table; + struct ci_single_dpm_table mvdd_table; +}; + +struct ci_mc_reg_entry { + u32 mclk_max; + u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; +}; + +struct ci_mc_reg_table { + u8 last; + u8 num_entries; + u16 valid_flag; + struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; + SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; +}; + +struct ci_ulv_parm +{ + bool supported; + u32 cg_ulv_parameter; + u32 volt_change_delay; + struct ci_pl pl; +}; + +#define CISLANDS_MAX_LEAKAGE_COUNT 8 + +struct ci_leakage_voltage { + u16 count; + u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT]; + u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT]; +}; + +struct ci_dpm_level_enable_mask { + u32 uvd_dpm_enable_mask; + u32 vce_dpm_enable_mask; + u32 acp_dpm_enable_mask; + u32 samu_dpm_enable_mask; + u32 sclk_dpm_enable_mask; + u32 mclk_dpm_enable_mask; + u32 pcie_dpm_enable_mask; +}; + +struct ci_vbios_boot_state +{ + u16 mvdd_bootup_value; + u16 vddc_bootup_value; + u16 vddci_bootup_value; + u32 sclk_bootup_value; + u32 mclk_bootup_value; + u16 pcie_gen_bootup_value; + u16 pcie_lane_bootup_value; +}; + +struct ci_clock_registers { + u32 cg_spll_func_cntl; + u32 cg_spll_func_cntl_2; + u32 cg_spll_func_cntl_3; + u32 cg_spll_func_cntl_4; + u32 cg_spll_spread_spectrum; + u32 cg_spll_spread_spectrum_2; + u32 dll_cntl; + u32 mclk_pwrmgt_cntl; + u32 mpll_ad_func_cntl; + u32 mpll_dq_func_cntl; + u32 mpll_func_cntl; + u32 mpll_func_cntl_1; + u32 mpll_func_cntl_2; + u32 mpll_ss1; + u32 mpll_ss2; +}; + +struct ci_thermal_temperature_setting { + s32 temperature_low; + s32 temperature_high; + s32 temperature_shutdown; +}; + +struct ci_pcie_perf_range { + u16 max; + u16 min; +}; + +enum ci_pt_config_reg_type { + CISLANDS_CONFIGREG_MMR = 0, + CISLANDS_CONFIGREG_SMC_IND, + CISLANDS_CONFIGREG_DIDT_IND, + CISLANDS_CONFIGREG_CACHE, + CISLANDS_CONFIGREG_MAX +}; + +#define POWERCONTAINMENT_FEATURE_BAPM 0x00000001 +#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 +#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 + +struct ci_pt_config_reg { + u32 offset; + u32 mask; + u32 shift; + u32 value; + enum ci_pt_config_reg_type type; +}; + +struct ci_pt_defaults { + u8 svi_load_line_en; + u8 svi_load_line_vddc; + u8 tdc_vddc_throttle_release_limit_perc; + u8 tdc_mawt; + u8 tdc_waterfall_ctl; + u8 dte_ambient_temp_base; + u32 display_cac; + u32 bapm_temp_gradient; + u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; + u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; +}; + +#define DPMTABLE_OD_UPDATE_SCLK 0x00000001 +#define DPMTABLE_OD_UPDATE_MCLK 0x00000002 +#define DPMTABLE_UPDATE_SCLK 0x00000004 +#define DPMTABLE_UPDATE_MCLK 0x00000008 + +struct ci_power_info { + struct ci_dpm_table dpm_table; + u32 voltage_control; + u32 mvdd_control; + u32 vddci_control; + u32 active_auto_throttle_sources; + struct ci_clock_registers clock_registers; + u16 acpi_vddc; + u16 acpi_vddci; + enum amdgpu_pcie_gen force_pcie_gen; + enum amdgpu_pcie_gen acpi_pcie_gen; + struct ci_leakage_voltage vddc_leakage; + struct ci_leakage_voltage vddci_leakage; + u16 max_vddc_in_pp_table; + u16 min_vddc_in_pp_table; + u16 max_vddci_in_pp_table; + u16 min_vddci_in_pp_table; + u32 mclk_strobe_mode_threshold; + u32 mclk_stutter_mode_threshold; + u32 mclk_edc_enable_threshold; + u32 mclk_edc_wr_enable_threshold; + struct ci_vbios_boot_state vbios_boot_state; + /* smc offsets */ + u32 sram_end; + u32 dpm_table_start; + u32 soft_regs_start; + u32 mc_reg_table_start; + u32 fan_table_start; + u32 arb_table_start; + /* smc tables */ + SMU7_Discrete_DpmTable smc_state_table; + SMU7_Discrete_MCRegisters smc_mc_reg_table; + SMU7_Discrete_PmFuses smc_powertune_table; + /* other stuff */ + struct ci_mc_reg_table mc_reg_table; + struct atom_voltage_table vddc_voltage_table; + struct atom_voltage_table vddci_voltage_table; + struct atom_voltage_table mvdd_voltage_table; + struct ci_ulv_parm ulv; + u32 power_containment_features; + const struct ci_pt_defaults *powertune_defaults; + u32 dte_tj_offset; + bool vddc_phase_shed_control; + struct ci_thermal_temperature_setting thermal_temp_setting; + struct ci_dpm_level_enable_mask dpm_level_enable_mask; + u32 need_update_smu7_dpm_table; + u32 sclk_dpm_key_disabled; + u32 mclk_dpm_key_disabled; + u32 pcie_dpm_key_disabled; + u32 thermal_sclk_dpm_enabled; + struct ci_pcie_perf_range pcie_gen_performance; + struct ci_pcie_perf_range pcie_lane_performance; + struct ci_pcie_perf_range pcie_gen_powersaving; + struct ci_pcie_perf_range pcie_lane_powersaving; + u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS]; + u32 mclk_activity_target; + u32 low_sclk_interrupt_t; + u32 last_mclk_dpm_enable_mask; + u32 sys_pcie_mask; + /* caps */ + bool caps_power_containment; + bool caps_cac; + bool caps_sq_ramping; + bool caps_db_ramping; + bool caps_td_ramping; + bool caps_tcp_ramping; + bool caps_fps; + bool caps_sclk_ds; + bool caps_sclk_ss_support; + bool caps_mclk_ss_support; + bool caps_uvd_dpm; + bool caps_vce_dpm; + bool caps_samu_dpm; + bool caps_acp_dpm; + bool caps_automatic_dc_transition; + bool caps_sclk_throttle_low_notification; + bool caps_dynamic_ac_timing; + bool caps_od_fuzzy_fan_control_support; + /* flags */ + bool thermal_protection; + bool pcie_performance_request; + bool dynamic_ss; + bool dll_default_on; + bool cac_enabled; + bool uvd_enabled; + bool battery_state; + bool pspp_notify_required; + bool enable_bapm_feature; + bool enable_tdc_limit_feature; + bool enable_pkg_pwr_tracking_feature; + bool use_pcie_performance_levels; + bool use_pcie_powersaving_levels; + bool uvd_power_gated; + /* driver states */ + struct amdgpu_ps current_rps; + struct ci_ps current_ps; + struct amdgpu_ps requested_rps; + struct ci_ps requested_ps; + /* fan control */ + bool fan_ctrl_is_in_default_mode; + bool fan_is_controlled_by_smc; + u32 t_min; + u32 fan_ctrl_default_mode; +}; + +#define CISLANDS_VOLTAGE_CONTROL_NONE 0x0 +#define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1 +#define CISLANDS_VOLTAGE_CONTROL_BY_SVID2 0x2 + +#define CISLANDS_Q88_FORMAT_CONVERSION_UNIT 256 + +#define CISLANDS_VRC_DFLT0 0x3FFFC000 +#define CISLANDS_VRC_DFLT1 0x000400 +#define CISLANDS_VRC_DFLT2 0xC00080 +#define CISLANDS_VRC_DFLT3 0xC00200 +#define CISLANDS_VRC_DFLT4 0xC01680 +#define CISLANDS_VRC_DFLT5 0xC00033 +#define CISLANDS_VRC_DFLT6 0xC00033 +#define CISLANDS_VRC_DFLT7 0x3FFFC000 + +#define CISLANDS_CGULVPARAMETER_DFLT 0x00040035 +#define CISLAND_TARGETACTIVITY_DFLT 30 +#define CISLAND_MCLK_TARGETACTIVITY_DFLT 10 + +#define PCIE_PERF_REQ_REMOVE_REGISTRY 0 +#define PCIE_PERF_REQ_FORCE_LOWPOWER 1 +#define PCIE_PERF_REQ_PECI_GEN1 2 +#define PCIE_PERF_REQ_PECI_GEN2 3 +#define PCIE_PERF_REQ_PECI_GEN3 4 + +#define CISLANDS_SSTU_DFLT 0 +#define CISLANDS_SST_DFLT 0x00C8 + +/* XXX are these ok? */ +#define CISLANDS_TEMP_RANGE_MIN (90 * 1000) +#define CISLANDS_TEMP_RANGE_MAX (120 * 1000) + +int amdgpu_ci_copy_bytes_to_smc(struct amdgpu_device *adev, + u32 smc_start_address, + const u8 *src, u32 byte_count, u32 limit); +void amdgpu_ci_start_smc(struct amdgpu_device *adev); +void amdgpu_ci_reset_smc(struct amdgpu_device *adev); +int amdgpu_ci_program_jump_on_start(struct amdgpu_device *adev); +void amdgpu_ci_stop_smc_clock(struct amdgpu_device *adev); +void amdgpu_ci_start_smc_clock(struct amdgpu_device *adev); +bool amdgpu_ci_is_smc_running(struct amdgpu_device *adev); +PPSMC_Result amdgpu_ci_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg); +PPSMC_Result amdgpu_ci_wait_for_smc_inactive(struct amdgpu_device *adev); +int amdgpu_ci_load_smc_ucode(struct amdgpu_device *adev, u32 limit); +int amdgpu_ci_read_smc_sram_dword(struct amdgpu_device *adev, + u32 smc_address, u32 *value, u32 limit); +int amdgpu_ci_write_smc_sram_dword(struct amdgpu_device *adev, + u32 smc_address, u32 value, u32 limit); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/ci_smc.c b/drivers/gpu/drm/amd/amdgpu/ci_smc.c new file mode 100644 index 000000000000..7eb9069db8e3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/ci_smc.c @@ -0,0 +1,279 @@ +/* + * Copyright 2011 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ + +#include +#include "drmP.h" +#include "amdgpu.h" +#include "cikd.h" +#include "ppsmc.h" +#include "amdgpu_ucode.h" +#include "ci_dpm.h" + +#include "smu/smu_7_0_1_d.h" +#include "smu/smu_7_0_1_sh_mask.h" + +static int ci_set_smc_sram_address(struct amdgpu_device *adev, + u32 smc_address, u32 limit) +{ + if (smc_address & 3) + return -EINVAL; + if ((smc_address + 3) > limit) + return -EINVAL; + + WREG32(mmSMC_IND_INDEX_0, smc_address); + WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); + + return 0; +} + +int amdgpu_ci_copy_bytes_to_smc(struct amdgpu_device *adev, + u32 smc_start_address, + const u8 *src, u32 byte_count, u32 limit) +{ + unsigned long flags; + u32 data, original_data; + u32 addr; + u32 extra_shift; + int ret = 0; + + if (smc_start_address & 3) + return -EINVAL; + if ((smc_start_address + byte_count) > limit) + return -EINVAL; + + addr = smc_start_address; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + while (byte_count >= 4) { + /* SMC address space is BE */ + data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; + + ret = ci_set_smc_sram_address(adev, addr, limit); + if (ret) + goto done; + + WREG32(mmSMC_IND_DATA_0, data); + + src += 4; + byte_count -= 4; + addr += 4; + } + + /* RMW for the final bytes */ + if (byte_count > 0) { + data = 0; + + ret = ci_set_smc_sram_address(adev, addr, limit); + if (ret) + goto done; + + original_data = RREG32(mmSMC_IND_DATA_0); + + extra_shift = 8 * (4 - byte_count); + + while (byte_count > 0) { + data = (data << 8) + *src++; + byte_count--; + } + + data <<= extra_shift; + + data |= (original_data & ~((~0UL) << extra_shift)); + + ret = ci_set_smc_sram_address(adev, addr, limit); + if (ret) + goto done; + + WREG32(mmSMC_IND_DATA_0, data); + } + +done: + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + + return ret; +} + +void amdgpu_ci_start_smc(struct amdgpu_device *adev) +{ + u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); + + tmp &= ~SMC_SYSCON_RESET_CNTL__rst_reg_MASK; + WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); +} + +void amdgpu_ci_reset_smc(struct amdgpu_device *adev) +{ + u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); + + tmp |= SMC_SYSCON_RESET_CNTL__rst_reg_MASK; + WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); +} + +int amdgpu_ci_program_jump_on_start(struct amdgpu_device *adev) +{ + static u8 data[] = { 0xE0, 0x00, 0x80, 0x40 }; + + return amdgpu_ci_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1); +} + +void amdgpu_ci_stop_smc_clock(struct amdgpu_device *adev) +{ + u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + + tmp |= SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK; + + WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp); +} + +void amdgpu_ci_start_smc_clock(struct amdgpu_device *adev) +{ + u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + + tmp &= ~SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK; + + WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp); +} + +bool amdgpu_ci_is_smc_running(struct amdgpu_device *adev) +{ + u32 clk = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + u32 pc_c = RREG32_SMC(ixSMC_PC_C); + + if (!(clk & SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK) && (0x20100 <= pc_c)) + return true; + + return false; +} + +PPSMC_Result amdgpu_ci_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg) +{ + u32 tmp; + int i; + + if (!amdgpu_ci_is_smc_running(adev)) + return PPSMC_Result_Failed; + + WREG32(mmSMC_MESSAGE_0, msg); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(mmSMC_RESP_0); + if (tmp != 0) + break; + udelay(1); + } + tmp = RREG32(mmSMC_RESP_0); + + return (PPSMC_Result)tmp; +} + +PPSMC_Result amdgpu_ci_wait_for_smc_inactive(struct amdgpu_device *adev) +{ + u32 tmp; + int i; + + if (!amdgpu_ci_is_smc_running(adev)) + return PPSMC_Result_OK; + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + if ((tmp & SMC_SYSCON_CLOCK_CNTL_0__cken_MASK) == 0) + break; + udelay(1); + } + + return PPSMC_Result_OK; +} + +int amdgpu_ci_load_smc_ucode(struct amdgpu_device *adev, u32 limit) +{ + const struct smc_firmware_header_v1_0 *hdr; + unsigned long flags; + u32 ucode_start_address; + u32 ucode_size; + const u8 *src; + u32 data; + + if (!adev->pm.fw) + return -EINVAL; + + hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data; + amdgpu_ucode_print_smc_hdr(&hdr->header); + + adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); + ucode_start_address = le32_to_cpu(hdr->ucode_start_addr); + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); + src = (const u8 *) + (adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + if (ucode_size & 3) + return -EINVAL; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + WREG32(mmSMC_IND_INDEX_0, ucode_start_address); + WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK, + ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); + while (ucode_size >= 4) { + /* SMC address space is BE */ + data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; + + WREG32(mmSMC_IND_DATA_0, data); + + src += 4; + ucode_size -= 4; + } + WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + + return 0; +} + +int amdgpu_ci_read_smc_sram_dword(struct amdgpu_device *adev, + u32 smc_address, u32 *value, u32 limit) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + ret = ci_set_smc_sram_address(adev, smc_address, limit); + if (ret == 0) + *value = RREG32(mmSMC_IND_DATA_0); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + + return ret; +} + +int amdgpu_ci_write_smc_sram_dword(struct amdgpu_device *adev, + u32 smc_address, u32 value, u32 limit) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + ret = ci_set_smc_sram_address(adev, smc_address, limit); + if (ret == 0) + WREG32(mmSMC_IND_DATA_0, value); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + + return ret; +} diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c new file mode 100644 index 000000000000..74ce0be2fbb7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -0,0 +1,2505 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ +#include +#include +#include +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_atombios.h" +#include "amdgpu_ih.h" +#include "amdgpu_uvd.h" +#include "amdgpu_vce.h" +#include "cikd.h" +#include "atom.h" + +#include "cik.h" +#include "gmc_v7_0.h" +#include "cik_ih.h" +#include "dce_v8_0.h" +#include "gfx_v7_0.h" +#include "cik_sdma.h" +#include "uvd_v4_2.h" +#include "vce_v2_0.h" +#include "cik_dpm.h" + +#include "uvd/uvd_4_2_d.h" + +#include "smu/smu_7_0_1_d.h" +#include "smu/smu_7_0_1_sh_mask.h" + +#include "dce/dce_8_0_d.h" +#include "dce/dce_8_0_sh_mask.h" + +#include "bif/bif_4_1_d.h" +#include "bif/bif_4_1_sh_mask.h" + +#include "gca/gfx_7_2_d.h" +#include "gca/gfx_7_2_enum.h" +#include "gca/gfx_7_2_sh_mask.h" + +#include "gmc/gmc_7_1_d.h" +#include "gmc/gmc_7_1_sh_mask.h" + +#include "oss/oss_2_0_d.h" +#include "oss/oss_2_0_sh_mask.h" + +/* + * Indirect registers accessor + */ +static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + WREG32(mmPCIE_INDEX, reg); + (void)RREG32(mmPCIE_INDEX); + r = RREG32(mmPCIE_DATA); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + return r; +} + +static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + WREG32(mmPCIE_INDEX, reg); + (void)RREG32(mmPCIE_INDEX); + WREG32(mmPCIE_DATA, v); + (void)RREG32(mmPCIE_DATA); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); +} + +static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + WREG32(mmSMC_IND_INDEX_0, (reg)); + r = RREG32(mmSMC_IND_DATA_0); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + return r; +} + +static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + WREG32(mmSMC_IND_INDEX_0, (reg)); + WREG32(mmSMC_IND_DATA_0, (v)); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); +} + +static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); + r = RREG32(mmUVD_CTX_DATA); + spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + return r; +} + +static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); + WREG32(mmUVD_CTX_DATA, (v)); + spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); +} + +static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->didt_idx_lock, flags); + WREG32(mmDIDT_IND_INDEX, (reg)); + r = RREG32(mmDIDT_IND_DATA); + spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + return r; +} + +static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&adev->didt_idx_lock, flags); + WREG32(mmDIDT_IND_INDEX, (reg)); + WREG32(mmDIDT_IND_DATA, (v)); + spin_unlock_irqrestore(&adev->didt_idx_lock, flags); +} + +static const u32 bonaire_golden_spm_registers[] = +{ + 0xc200, 0xe0ffffff, 0xe0000000 +}; + +static const u32 bonaire_golden_common_registers[] = +{ + 0x31dc, 0xffffffff, 0x00000800, + 0x31dd, 0xffffffff, 0x00000800, + 0x31e6, 0xffffffff, 0x00007fbf, + 0x31e7, 0xffffffff, 0x00007faf +}; + +static const u32 bonaire_golden_registers[] = +{ + 0xcd5, 0x00000333, 0x00000333, + 0xcd4, 0x000c0fc0, 0x00040200, + 0x2684, 0x00010000, 0x00058208, + 0xf000, 0xffff1fff, 0x00140000, + 0xf080, 0xfdfc0fff, 0x00000100, + 0xf08d, 0x40000000, 0x40000200, + 0x260c, 0xffffffff, 0x00000000, + 0x260d, 0xf00fffff, 0x00000400, + 0x260e, 0x0002021c, 0x00020200, + 0x31e, 0x00000080, 0x00000000, + 0x16ec, 0x000000f0, 0x00000070, + 0x16f0, 0xf0311fff, 0x80300000, + 0x263e, 0x73773777, 0x12010001, + 0xd43, 0x00810000, 0x408af000, + 0x1c0c, 0x31000111, 0x00000011, + 0xbd2, 0x73773777, 0x12010001, + 0x883, 0x00007fb6, 0x0021a1b1, + 0x884, 0x00007fb6, 0x002021b1, + 0x860, 0x00007fb6, 0x00002191, + 0x886, 0x00007fb6, 0x002121b1, + 0x887, 0x00007fb6, 0x002021b1, + 0x877, 0x00007fb6, 0x00002191, + 0x878, 0x00007fb6, 0x00002191, + 0xd8a, 0x0000003f, 0x0000000a, + 0xd8b, 0x0000003f, 0x0000000a, + 0xab9, 0x00073ffe, 0x000022a2, + 0x903, 0x000007ff, 0x00000000, + 0x2285, 0xf000003f, 0x00000007, + 0x22fc, 0x00002001, 0x00000001, + 0x22c9, 0xffffffff, 0x00ffffff, + 0xc281, 0x0000ff0f, 0x00000000, + 0xa293, 0x07ffffff, 0x06000000, + 0x136, 0x00000fff, 0x00000100, + 0xf9e, 0x00000001, 0x00000002, + 0x2440, 0x03000000, 0x0362c688, + 0x2300, 0x000000ff, 0x00000001, + 0x390, 0x00001fff, 0x00001fff, + 0x2418, 0x0000007f, 0x00000020, + 0x2542, 0x00010000, 0x00010000, + 0x2b05, 0x000003ff, 0x000000f3, + 0x2b03, 0xffffffff, 0x00001032 +}; + +static const u32 bonaire_mgcg_cgcg_init[] = +{ + 0x3108, 0xffffffff, 0xfffffffc, + 0xc200, 0xffffffff, 0xe0000000, + 0xf0a8, 0xffffffff, 0x00000100, + 0xf082, 0xffffffff, 0x00000100, + 0xf0b0, 0xffffffff, 0xc0000100, + 0xf0b2, 0xffffffff, 0xc0000100, + 0xf0b1, 0xffffffff, 0xc0000100, + 0x1579, 0xffffffff, 0x00600100, + 0xf0a0, 0xffffffff, 0x00000100, + 0xf085, 0xffffffff, 0x06000100, + 0xf088, 0xffffffff, 0x00000100, + 0xf086, 0xffffffff, 0x06000100, + 0xf081, 0xffffffff, 0x00000100, + 0xf0b8, 0xffffffff, 0x00000100, + 0xf089, 0xffffffff, 0x00000100, + 0xf080, 0xffffffff, 0x00000100, + 0xf08c, 0xffffffff, 0x00000100, + 0xf08d, 0xffffffff, 0x00000100, + 0xf094, 0xffffffff, 0x00000100, + 0xf095, 0xffffffff, 0x00000100, + 0xf096, 0xffffffff, 0x00000100, + 0xf097, 0xffffffff, 0x00000100, + 0xf098, 0xffffffff, 0x00000100, + 0xf09f, 0xffffffff, 0x00000100, + 0xf09e, 0xffffffff, 0x00000100, + 0xf084, 0xffffffff, 0x06000100, + 0xf0a4, 0xffffffff, 0x00000100, + 0xf09d, 0xffffffff, 0x00000100, + 0xf0ad, 0xffffffff, 0x00000100, + 0xf0ac, 0xffffffff, 0x00000100, + 0xf09c, 0xffffffff, 0x00000100, + 0xc200, 0xffffffff, 0xe0000000, + 0xf008, 0xffffffff, 0x00010000, + 0xf009, 0xffffffff, 0x00030002, + 0xf00a, 0xffffffff, 0x00040007, + 0xf00b, 0xffffffff, 0x00060005, + 0xf00c, 0xffffffff, 0x00090008, + 0xf00d, 0xffffffff, 0x00010000, + 0xf00e, 0xffffffff, 0x00030002, + 0xf00f, 0xffffffff, 0x00040007, + 0xf010, 0xffffffff, 0x00060005, + 0xf011, 0xffffffff, 0x00090008, + 0xf012, 0xffffffff, 0x00010000, + 0xf013, 0xffffffff, 0x00030002, + 0xf014, 0xffffffff, 0x00040007, + 0xf015, 0xffffffff, 0x00060005, + 0xf016, 0xffffffff, 0x00090008, + 0xf017, 0xffffffff, 0x00010000, + 0xf018, 0xffffffff, 0x00030002, + 0xf019, 0xffffffff, 0x00040007, + 0xf01a, 0xffffffff, 0x00060005, + 0xf01b, 0xffffffff, 0x00090008, + 0xf01c, 0xffffffff, 0x00010000, + 0xf01d, 0xffffffff, 0x00030002, + 0xf01e, 0xffffffff, 0x00040007, + 0xf01f, 0xffffffff, 0x00060005, + 0xf020, 0xffffffff, 0x00090008, + 0xf021, 0xffffffff, 0x00010000, + 0xf022, 0xffffffff, 0x00030002, + 0xf023, 0xffffffff, 0x00040007, + 0xf024, 0xffffffff, 0x00060005, + 0xf025, 0xffffffff, 0x00090008, + 0xf026, 0xffffffff, 0x00010000, + 0xf027, 0xffffffff, 0x00030002, + 0xf028, 0xffffffff, 0x00040007, + 0xf029, 0xffffffff, 0x00060005, + 0xf02a, 0xffffffff, 0x00090008, + 0xf000, 0xffffffff, 0x96e00200, + 0x21c2, 0xffffffff, 0x00900100, + 0x3109, 0xffffffff, 0x0020003f, + 0xe, 0xffffffff, 0x0140001c, + 0xf, 0x000f0000, 0x000f0000, + 0x88, 0xffffffff, 0xc060000c, + 0x89, 0xc0000fff, 0x00000100, + 0x3e4, 0xffffffff, 0x00000100, + 0x3e6, 0x00000101, 0x00000000, + 0x82a, 0xffffffff, 0x00000104, + 0x1579, 0xff000fff, 0x00000100, + 0xc33, 0xc0000fff, 0x00000104, + 0x3079, 0x00000001, 0x00000001, + 0x3403, 0xff000ff0, 0x00000100, + 0x3603, 0xff000ff0, 0x00000100 +}; + +static const u32 spectre_golden_spm_registers[] = +{ + 0xc200, 0xe0ffffff, 0xe0000000 +}; + +static const u32 spectre_golden_common_registers[] = +{ + 0x31dc, 0xffffffff, 0x00000800, + 0x31dd, 0xffffffff, 0x00000800, + 0x31e6, 0xffffffff, 0x00007fbf, + 0x31e7, 0xffffffff, 0x00007faf +}; + +static const u32 spectre_golden_registers[] = +{ + 0xf000, 0xffff1fff, 0x96940200, + 0xf003, 0xffff0001, 0xff000000, + 0xf080, 0xfffc0fff, 0x00000100, + 0x1bb6, 0x00010101, 0x00010000, + 0x260d, 0xf00fffff, 0x00000400, + 0x260e, 0xfffffffc, 0x00020200, + 0x16ec, 0x000000f0, 0x00000070, + 0x16f0, 0xf0311fff, 0x80300000, + 0x263e, 0x73773777, 0x12010001, + 0x26df, 0x00ff0000, 0x00fc0000, + 0xbd2, 0x73773777, 0x12010001, + 0x2285, 0xf000003f, 0x00000007, + 0x22c9, 0xffffffff, 0x00ffffff, + 0xa0d4, 0x3f3f3fff, 0x00000082, + 0xa0d5, 0x0000003f, 0x00000000, + 0xf9e, 0x00000001, 0x00000002, + 0x244f, 0xffff03df, 0x00000004, + 0x31da, 0x00000008, 0x00000008, + 0x2300, 0x000008ff, 0x00000800, + 0x2542, 0x00010000, 0x00010000, + 0x2b03, 0xffffffff, 0x54763210, + 0x853e, 0x01ff01ff, 0x00000002, + 0x8526, 0x007ff800, 0x00200000, + 0x8057, 0xffffffff, 0x00000f40, + 0xc24d, 0xffffffff, 0x00000001 +}; + +static const u32 spectre_mgcg_cgcg_init[] = +{ + 0x3108, 0xffffffff, 0xfffffffc, + 0xc200, 0xffffffff, 0xe0000000, + 0xf0a8, 0xffffffff, 0x00000100, + 0xf082, 0xffffffff, 0x00000100, + 0xf0b0, 0xffffffff, 0x00000100, + 0xf0b2, 0xffffffff, 0x00000100, + 0xf0b1, 0xffffffff, 0x00000100, + 0x1579, 0xffffffff, 0x00600100, + 0xf0a0, 0xffffffff, 0x00000100, + 0xf085, 0xffffffff, 0x06000100, + 0xf088, 0xffffffff, 0x00000100, + 0xf086, 0xffffffff, 0x06000100, + 0xf081, 0xffffffff, 0x00000100, + 0xf0b8, 0xffffffff, 0x00000100, + 0xf089, 0xffffffff, 0x00000100, + 0xf080, 0xffffffff, 0x00000100, + 0xf08c, 0xffffffff, 0x00000100, + 0xf08d, 0xffffffff, 0x00000100, + 0xf094, 0xffffffff, 0x00000100, + 0xf095, 0xffffffff, 0x00000100, + 0xf096, 0xffffffff, 0x00000100, + 0xf097, 0xffffffff, 0x00000100, + 0xf098, 0xffffffff, 0x00000100, + 0xf09f, 0xffffffff, 0x00000100, + 0xf09e, 0xffffffff, 0x00000100, + 0xf084, 0xffffffff, 0x06000100, + 0xf0a4, 0xffffffff, 0x00000100, + 0xf09d, 0xffffffff, 0x00000100, + 0xf0ad, 0xffffffff, 0x00000100, + 0xf0ac, 0xffffffff, 0x00000100, + 0xf09c, 0xffffffff, 0x00000100, + 0xc200, 0xffffffff, 0xe0000000, + 0xf008, 0xffffffff, 0x00010000, + 0xf009, 0xffffffff, 0x00030002, + 0xf00a, 0xffffffff, 0x00040007, + 0xf00b, 0xffffffff, 0x00060005, + 0xf00c, 0xffffffff, 0x00090008, + 0xf00d, 0xffffffff, 0x00010000, + 0xf00e, 0xffffffff, 0x00030002, + 0xf00f, 0xffffffff, 0x00040007, + 0xf010, 0xffffffff, 0x00060005, + 0xf011, 0xffffffff, 0x00090008, + 0xf012, 0xffffffff, 0x00010000, + 0xf013, 0xffffffff, 0x00030002, + 0xf014, 0xffffffff, 0x00040007, + 0xf015, 0xffffffff, 0x00060005, + 0xf016, 0xffffffff, 0x00090008, + 0xf017, 0xffffffff, 0x00010000, + 0xf018, 0xffffffff, 0x00030002, + 0xf019, 0xffffffff, 0x00040007, + 0xf01a, 0xffffffff, 0x00060005, + 0xf01b, 0xffffffff, 0x00090008, + 0xf01c, 0xffffffff, 0x00010000, + 0xf01d, 0xffffffff, 0x00030002, + 0xf01e, 0xffffffff, 0x00040007, + 0xf01f, 0xffffffff, 0x00060005, + 0xf020, 0xffffffff, 0x00090008, + 0xf021, 0xffffffff, 0x00010000, + 0xf022, 0xffffffff, 0x00030002, + 0xf023, 0xffffffff, 0x00040007, + 0xf024, 0xffffffff, 0x00060005, + 0xf025, 0xffffffff, 0x00090008, + 0xf026, 0xffffffff, 0x00010000, + 0xf027, 0xffffffff, 0x00030002, + 0xf028, 0xffffffff, 0x00040007, + 0xf029, 0xffffffff, 0x00060005, + 0xf02a, 0xffffffff, 0x00090008, + 0xf02b, 0xffffffff, 0x00010000, + 0xf02c, 0xffffffff, 0x00030002, + 0xf02d, 0xffffffff, 0x00040007, + 0xf02e, 0xffffffff, 0x00060005, + 0xf02f, 0xffffffff, 0x00090008, + 0xf000, 0xffffffff, 0x96e00200, + 0x21c2, 0xffffffff, 0x00900100, + 0x3109, 0xffffffff, 0x0020003f, + 0xe, 0xffffffff, 0x0140001c, + 0xf, 0x000f0000, 0x000f0000, + 0x88, 0xffffffff, 0xc060000c, + 0x89, 0xc0000fff, 0x00000100, + 0x3e4, 0xffffffff, 0x00000100, + 0x3e6, 0x00000101, 0x00000000, + 0x82a, 0xffffffff, 0x00000104, + 0x1579, 0xff000fff, 0x00000100, + 0xc33, 0xc0000fff, 0x00000104, + 0x3079, 0x00000001, 0x00000001, + 0x3403, 0xff000ff0, 0x00000100, + 0x3603, 0xff000ff0, 0x00000100 +}; + +static const u32 kalindi_golden_spm_registers[] = +{ + 0xc200, 0xe0ffffff, 0xe0000000 +}; + +static const u32 kalindi_golden_common_registers[] = +{ + 0x31dc, 0xffffffff, 0x00000800, + 0x31dd, 0xffffffff, 0x00000800, + 0x31e6, 0xffffffff, 0x00007fbf, + 0x31e7, 0xffffffff, 0x00007faf +}; + +static const u32 kalindi_golden_registers[] = +{ + 0xf000, 0xffffdfff, 0x6e944040, + 0x1579, 0xff607fff, 0xfc000100, + 0xf088, 0xff000fff, 0x00000100, + 0xf089, 0xff000fff, 0x00000100, + 0xf080, 0xfffc0fff, 0x00000100, + 0x1bb6, 0x00010101, 0x00010000, + 0x260c, 0xffffffff, 0x00000000, + 0x260d, 0xf00fffff, 0x00000400, + 0x16ec, 0x000000f0, 0x00000070, + 0x16f0, 0xf0311fff, 0x80300000, + 0x263e, 0x73773777, 0x12010001, + 0x263f, 0xffffffff, 0x00000010, + 0x26df, 0x00ff0000, 0x00fc0000, + 0x200c, 0x00001f0f, 0x0000100a, + 0xbd2, 0x73773777, 0x12010001, + 0x902, 0x000fffff, 0x000c007f, + 0x2285, 0xf000003f, 0x00000007, + 0x22c9, 0x3fff3fff, 0x00ffcfff, + 0xc281, 0x0000ff0f, 0x00000000, + 0xa293, 0x07ffffff, 0x06000000, + 0x136, 0x00000fff, 0x00000100, + 0xf9e, 0x00000001, 0x00000002, + 0x31da, 0x00000008, 0x00000008, + 0x2300, 0x000000ff, 0x00000003, + 0x853e, 0x01ff01ff, 0x00000002, + 0x8526, 0x007ff800, 0x00200000, + 0x8057, 0xffffffff, 0x00000f40, + 0x2231, 0x001f3ae3, 0x00000082, + 0x2235, 0x0000001f, 0x00000010, + 0xc24d, 0xffffffff, 0x00000000 +}; + +static const u32 kalindi_mgcg_cgcg_init[] = +{ + 0x3108, 0xffffffff, 0xfffffffc, + 0xc200, 0xffffffff, 0xe0000000, + 0xf0a8, 0xffffffff, 0x00000100, + 0xf082, 0xffffffff, 0x00000100, + 0xf0b0, 0xffffffff, 0x00000100, + 0xf0b2, 0xffffffff, 0x00000100, + 0xf0b1, 0xffffffff, 0x00000100, + 0x1579, 0xffffffff, 0x00600100, + 0xf0a0, 0xffffffff, 0x00000100, + 0xf085, 0xffffffff, 0x06000100, + 0xf088, 0xffffffff, 0x00000100, + 0xf086, 0xffffffff, 0x06000100, + 0xf081, 0xffffffff, 0x00000100, + 0xf0b8, 0xffffffff, 0x00000100, + 0xf089, 0xffffffff, 0x00000100, + 0xf080, 0xffffffff, 0x00000100, + 0xf08c, 0xffffffff, 0x00000100, + 0xf08d, 0xffffffff, 0x00000100, + 0xf094, 0xffffffff, 0x00000100, + 0xf095, 0xffffffff, 0x00000100, + 0xf096, 0xffffffff, 0x00000100, + 0xf097, 0xffffffff, 0x00000100, + 0xf098, 0xffffffff, 0x00000100, + 0xf09f, 0xffffffff, 0x00000100, + 0xf09e, 0xffffffff, 0x00000100, + 0xf084, 0xffffffff, 0x06000100, + 0xf0a4, 0xffffffff, 0x00000100, + 0xf09d, 0xffffffff, 0x00000100, + 0xf0ad, 0xffffffff, 0x00000100, + 0xf0ac, 0xffffffff, 0x00000100, + 0xf09c, 0xffffffff, 0x00000100, + 0xc200, 0xffffffff, 0xe0000000, + 0xf008, 0xffffffff, 0x00010000, + 0xf009, 0xffffffff, 0x00030002, + 0xf00a, 0xffffffff, 0x00040007, + 0xf00b, 0xffffffff, 0x00060005, + 0xf00c, 0xffffffff, 0x00090008, + 0xf00d, 0xffffffff, 0x00010000, + 0xf00e, 0xffffffff, 0x00030002, + 0xf00f, 0xffffffff, 0x00040007, + 0xf010, 0xffffffff, 0x00060005, + 0xf011, 0xffffffff, 0x00090008, + 0xf000, 0xffffffff, 0x96e00200, + 0x21c2, 0xffffffff, 0x00900100, + 0x3109, 0xffffffff, 0x0020003f, + 0xe, 0xffffffff, 0x0140001c, + 0xf, 0x000f0000, 0x000f0000, + 0x88, 0xffffffff, 0xc060000c, + 0x89, 0xc0000fff, 0x00000100, + 0x82a, 0xffffffff, 0x00000104, + 0x1579, 0xff000fff, 0x00000100, + 0xc33, 0xc0000fff, 0x00000104, + 0x3079, 0x00000001, 0x00000001, + 0x3403, 0xff000ff0, 0x00000100, + 0x3603, 0xff000ff0, 0x00000100 +}; + +static const u32 hawaii_golden_spm_registers[] = +{ + 0xc200, 0xe0ffffff, 0xe0000000 +}; + +static const u32 hawaii_golden_common_registers[] = +{ + 0xc200, 0xffffffff, 0xe0000000, + 0xa0d4, 0xffffffff, 0x3a00161a, + 0xa0d5, 0xffffffff, 0x0000002e, + 0x2684, 0xffffffff, 0x00018208, + 0x263e, 0xffffffff, 0x12011003 +}; + +static const u32 hawaii_golden_registers[] = +{ + 0xcd5, 0x00000333, 0x00000333, + 0x2684, 0x00010000, 0x00058208, + 0x260c, 0xffffffff, 0x00000000, + 0x260d, 0xf00fffff, 0x00000400, + 0x260e, 0x0002021c, 0x00020200, + 0x31e, 0x00000080, 0x00000000, + 0x16ec, 0x000000f0, 0x00000070, + 0x16f0, 0xf0311fff, 0x80300000, + 0xd43, 0x00810000, 0x408af000, + 0x1c0c, 0x31000111, 0x00000011, + 0xbd2, 0x73773777, 0x12010001, + 0x848, 0x0000007f, 0x0000001b, + 0x877, 0x00007fb6, 0x00002191, + 0xd8a, 0x0000003f, 0x0000000a, + 0xd8b, 0x0000003f, 0x0000000a, + 0xab9, 0x00073ffe, 0x000022a2, + 0x903, 0x000007ff, 0x00000000, + 0x22fc, 0x00002001, 0x00000001, + 0x22c9, 0xffffffff, 0x00ffffff, + 0xc281, 0x0000ff0f, 0x00000000, + 0xa293, 0x07ffffff, 0x06000000, + 0xf9e, 0x00000001, 0x00000002, + 0x31da, 0x00000008, 0x00000008, + 0x31dc, 0x00000f00, 0x00000800, + 0x31dd, 0x00000f00, 0x00000800, + 0x31e6, 0x00ffffff, 0x00ff7fbf, + 0x31e7, 0x00ffffff, 0x00ff7faf, + 0x2300, 0x000000ff, 0x00000800, + 0x390, 0x00001fff, 0x00001fff, + 0x2418, 0x0000007f, 0x00000020, + 0x2542, 0x00010000, 0x00010000, + 0x2b80, 0x00100000, 0x000ff07c, + 0x2b05, 0x000003ff, 0x0000000f, + 0x2b04, 0xffffffff, 0x7564fdec, + 0x2b03, 0xffffffff, 0x3120b9a8, + 0x2b02, 0x20000000, 0x0f9c0000 +}; + +static const u32 hawaii_mgcg_cgcg_init[] = +{ + 0x3108, 0xffffffff, 0xfffffffd, + 0xc200, 0xffffffff, 0xe0000000, + 0xf0a8, 0xffffffff, 0x00000100, + 0xf082, 0xffffffff, 0x00000100, + 0xf0b0, 0xffffffff, 0x00000100, + 0xf0b2, 0xffffffff, 0x00000100, + 0xf0b1, 0xffffffff, 0x00000100, + 0x1579, 0xffffffff, 0x00200100, + 0xf0a0, 0xffffffff, 0x00000100, + 0xf085, 0xffffffff, 0x06000100, + 0xf088, 0xffffffff, 0x00000100, + 0xf086, 0xffffffff, 0x06000100, + 0xf081, 0xffffffff, 0x00000100, + 0xf0b8, 0xffffffff, 0x00000100, + 0xf089, 0xffffffff, 0x00000100, + 0xf080, 0xffffffff, 0x00000100, + 0xf08c, 0xffffffff, 0x00000100, + 0xf08d, 0xffffffff, 0x00000100, + 0xf094, 0xffffffff, 0x00000100, + 0xf095, 0xffffffff, 0x00000100, + 0xf096, 0xffffffff, 0x00000100, + 0xf097, 0xffffffff, 0x00000100, + 0xf098, 0xffffffff, 0x00000100, + 0xf09f, 0xffffffff, 0x00000100, + 0xf09e, 0xffffffff, 0x00000100, + 0xf084, 0xffffffff, 0x06000100, + 0xf0a4, 0xffffffff, 0x00000100, + 0xf09d, 0xffffffff, 0x00000100, + 0xf0ad, 0xffffffff, 0x00000100, + 0xf0ac, 0xffffffff, 0x00000100, + 0xf09c, 0xffffffff, 0x00000100, + 0xc200, 0xffffffff, 0xe0000000, + 0xf008, 0xffffffff, 0x00010000, + 0xf009, 0xffffffff, 0x00030002, + 0xf00a, 0xffffffff, 0x00040007, + 0xf00b, 0xffffffff, 0x00060005, + 0xf00c, 0xffffffff, 0x00090008, + 0xf00d, 0xffffffff, 0x00010000, + 0xf00e, 0xffffffff, 0x00030002, + 0xf00f, 0xffffffff, 0x00040007, + 0xf010, 0xffffffff, 0x00060005, + 0xf011, 0xffffffff, 0x00090008, + 0xf012, 0xffffffff, 0x00010000, + 0xf013, 0xffffffff, 0x00030002, + 0xf014, 0xffffffff, 0x00040007, + 0xf015, 0xffffffff, 0x00060005, + 0xf016, 0xffffffff, 0x00090008, + 0xf017, 0xffffffff, 0x00010000, + 0xf018, 0xffffffff, 0x00030002, + 0xf019, 0xffffffff, 0x00040007, + 0xf01a, 0xffffffff, 0x00060005, + 0xf01b, 0xffffffff, 0x00090008, + 0xf01c, 0xffffffff, 0x00010000, + 0xf01d, 0xffffffff, 0x00030002, + 0xf01e, 0xffffffff, 0x00040007, + 0xf01f, 0xffffffff, 0x00060005, + 0xf020, 0xffffffff, 0x00090008, + 0xf021, 0xffffffff, 0x00010000, + 0xf022, 0xffffffff, 0x00030002, + 0xf023, 0xffffffff, 0x00040007, + 0xf024, 0xffffffff, 0x00060005, + 0xf025, 0xffffffff, 0x00090008, + 0xf026, 0xffffffff, 0x00010000, + 0xf027, 0xffffffff, 0x00030002, + 0xf028, 0xffffffff, 0x00040007, + 0xf029, 0xffffffff, 0x00060005, + 0xf02a, 0xffffffff, 0x00090008, + 0xf02b, 0xffffffff, 0x00010000, + 0xf02c, 0xffffffff, 0x00030002, + 0xf02d, 0xffffffff, 0x00040007, + 0xf02e, 0xffffffff, 0x00060005, + 0xf02f, 0xffffffff, 0x00090008, + 0xf030, 0xffffffff, 0x00010000, + 0xf031, 0xffffffff, 0x00030002, + 0xf032, 0xffffffff, 0x00040007, + 0xf033, 0xffffffff, 0x00060005, + 0xf034, 0xffffffff, 0x00090008, + 0xf035, 0xffffffff, 0x00010000, + 0xf036, 0xffffffff, 0x00030002, + 0xf037, 0xffffffff, 0x00040007, + 0xf038, 0xffffffff, 0x00060005, + 0xf039, 0xffffffff, 0x00090008, + 0xf03a, 0xffffffff, 0x00010000, + 0xf03b, 0xffffffff, 0x00030002, + 0xf03c, 0xffffffff, 0x00040007, + 0xf03d, 0xffffffff, 0x00060005, + 0xf03e, 0xffffffff, 0x00090008, + 0x30c6, 0xffffffff, 0x00020200, + 0xcd4, 0xffffffff, 0x00000200, + 0x570, 0xffffffff, 0x00000400, + 0x157a, 0xffffffff, 0x00000000, + 0xbd4, 0xffffffff, 0x00000902, + 0xf000, 0xffffffff, 0x96940200, + 0x21c2, 0xffffffff, 0x00900100, + 0x3109, 0xffffffff, 0x0020003f, + 0xe, 0xffffffff, 0x0140001c, + 0xf, 0x000f0000, 0x000f0000, + 0x88, 0xffffffff, 0xc060000c, + 0x89, 0xc0000fff, 0x00000100, + 0x3e4, 0xffffffff, 0x00000100, + 0x3e6, 0x00000101, 0x00000000, + 0x82a, 0xffffffff, 0x00000104, + 0x1579, 0xff000fff, 0x00000100, + 0xc33, 0xc0000fff, 0x00000104, + 0x3079, 0x00000001, 0x00000001, + 0x3403, 0xff000ff0, 0x00000100, + 0x3603, 0xff000ff0, 0x00000100 +}; + +static const u32 godavari_golden_registers[] = +{ + 0x1579, 0xff607fff, 0xfc000100, + 0x1bb6, 0x00010101, 0x00010000, + 0x260c, 0xffffffff, 0x00000000, + 0x260c0, 0xf00fffff, 0x00000400, + 0x184c, 0xffffffff, 0x00010000, + 0x16ec, 0x000000f0, 0x00000070, + 0x16f0, 0xf0311fff, 0x80300000, + 0x263e, 0x73773777, 0x12010001, + 0x263f, 0xffffffff, 0x00000010, + 0x200c, 0x00001f0f, 0x0000100a, + 0xbd2, 0x73773777, 0x12010001, + 0x902, 0x000fffff, 0x000c007f, + 0x2285, 0xf000003f, 0x00000007, + 0x22c9, 0xffffffff, 0x00ff0fff, + 0xc281, 0x0000ff0f, 0x00000000, + 0xa293, 0x07ffffff, 0x06000000, + 0x136, 0x00000fff, 0x00000100, + 0x3405, 0x00010000, 0x00810001, + 0x3605, 0x00010000, 0x00810001, + 0xf9e, 0x00000001, 0x00000002, + 0x31da, 0x00000008, 0x00000008, + 0x31dc, 0x00000f00, 0x00000800, + 0x31dd, 0x00000f00, 0x00000800, + 0x31e6, 0x00ffffff, 0x00ff7fbf, + 0x31e7, 0x00ffffff, 0x00ff7faf, + 0x2300, 0x000000ff, 0x00000001, + 0x853e, 0x01ff01ff, 0x00000002, + 0x8526, 0x007ff800, 0x00200000, + 0x8057, 0xffffffff, 0x00000f40, + 0x2231, 0x001f3ae3, 0x00000082, + 0x2235, 0x0000001f, 0x00000010, + 0xc24d, 0xffffffff, 0x00000000 +}; + +static void cik_init_golden_registers(struct amdgpu_device *adev) +{ + /* Some of the registers might be dependent on GRBM_GFX_INDEX */ + mutex_lock(&adev->grbm_idx_mutex); + + switch (adev->asic_type) { + case CHIP_BONAIRE: + amdgpu_program_register_sequence(adev, + bonaire_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + bonaire_golden_registers, + (const u32)ARRAY_SIZE(bonaire_golden_registers)); + amdgpu_program_register_sequence(adev, + bonaire_golden_common_registers, + (const u32)ARRAY_SIZE(bonaire_golden_common_registers)); + amdgpu_program_register_sequence(adev, + bonaire_golden_spm_registers, + (const u32)ARRAY_SIZE(bonaire_golden_spm_registers)); + break; + case CHIP_KABINI: + amdgpu_program_register_sequence(adev, + kalindi_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + kalindi_golden_registers, + (const u32)ARRAY_SIZE(kalindi_golden_registers)); + amdgpu_program_register_sequence(adev, + kalindi_golden_common_registers, + (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); + amdgpu_program_register_sequence(adev, + kalindi_golden_spm_registers, + (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); + break; + case CHIP_MULLINS: + amdgpu_program_register_sequence(adev, + kalindi_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + godavari_golden_registers, + (const u32)ARRAY_SIZE(godavari_golden_registers)); + amdgpu_program_register_sequence(adev, + kalindi_golden_common_registers, + (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); + amdgpu_program_register_sequence(adev, + kalindi_golden_spm_registers, + (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); + break; + case CHIP_KAVERI: + amdgpu_program_register_sequence(adev, + spectre_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + spectre_golden_registers, + (const u32)ARRAY_SIZE(spectre_golden_registers)); + amdgpu_program_register_sequence(adev, + spectre_golden_common_registers, + (const u32)ARRAY_SIZE(spectre_golden_common_registers)); + amdgpu_program_register_sequence(adev, + spectre_golden_spm_registers, + (const u32)ARRAY_SIZE(spectre_golden_spm_registers)); + break; + case CHIP_HAWAII: + amdgpu_program_register_sequence(adev, + hawaii_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + hawaii_golden_registers, + (const u32)ARRAY_SIZE(hawaii_golden_registers)); + amdgpu_program_register_sequence(adev, + hawaii_golden_common_registers, + (const u32)ARRAY_SIZE(hawaii_golden_common_registers)); + amdgpu_program_register_sequence(adev, + hawaii_golden_spm_registers, + (const u32)ARRAY_SIZE(hawaii_golden_spm_registers)); + break; + default: + break; + } + mutex_unlock(&adev->grbm_idx_mutex); +} + +/** + * cik_get_xclk - get the xclk + * + * @adev: amdgpu_device pointer + * + * Returns the reference clock used by the gfx engine + * (CIK). + */ +static u32 cik_get_xclk(struct amdgpu_device *adev) +{ + u32 reference_clock = adev->clock.spll.reference_freq; + + if (adev->flags & AMDGPU_IS_APU) { + if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) + return reference_clock / 2; + } else { + if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) + return reference_clock / 4; + } + return reference_clock; +} + +/** + * cik_srbm_select - select specific register instances + * + * @adev: amdgpu_device pointer + * @me: selected ME (micro engine) + * @pipe: pipe + * @queue: queue + * @vmid: VMID + * + * Switches the currently active registers instances. Some + * registers are instanced per VMID, others are instanced per + * me/pipe/queue combination. + */ +void cik_srbm_select(struct amdgpu_device *adev, + u32 me, u32 pipe, u32 queue, u32 vmid) +{ + u32 srbm_gfx_cntl = + (((pipe << SRBM_GFX_CNTL__PIPEID__SHIFT) & SRBM_GFX_CNTL__PIPEID_MASK)| + ((me << SRBM_GFX_CNTL__MEID__SHIFT) & SRBM_GFX_CNTL__MEID_MASK)| + ((vmid << SRBM_GFX_CNTL__VMID__SHIFT) & SRBM_GFX_CNTL__VMID_MASK)| + ((queue << SRBM_GFX_CNTL__QUEUEID__SHIFT) & SRBM_GFX_CNTL__QUEUEID_MASK)); + WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); +} + +static void cik_vga_set_state(struct amdgpu_device *adev, bool state) +{ + uint32_t tmp; + + tmp = RREG32(mmCONFIG_CNTL); + if (state == false) + tmp |= CONFIG_CNTL__VGA_DIS_MASK; + else + tmp &= ~CONFIG_CNTL__VGA_DIS_MASK; + WREG32(mmCONFIG_CNTL, tmp); +} + +static bool cik_read_disabled_bios(struct amdgpu_device *adev) +{ + u32 bus_cntl; + u32 d1vga_control = 0; + u32 d2vga_control = 0; + u32 vga_render_control = 0; + u32 rom_cntl; + bool r; + + bus_cntl = RREG32(mmBUS_CNTL); + if (adev->mode_info.num_crtc) { + d1vga_control = RREG32(mmD1VGA_CONTROL); + d2vga_control = RREG32(mmD2VGA_CONTROL); + vga_render_control = RREG32(mmVGA_RENDER_CONTROL); + } + rom_cntl = RREG32_SMC(ixROM_CNTL); + + /* enable the rom */ + WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); + if (adev->mode_info.num_crtc) { + /* Disable VGA mode */ + WREG32(mmD1VGA_CONTROL, + (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | + D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); + WREG32(mmD2VGA_CONTROL, + (d2vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | + D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); + WREG32(mmVGA_RENDER_CONTROL, + (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); + } + WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); + + r = amdgpu_read_bios(adev); + + /* restore regs */ + WREG32(mmBUS_CNTL, bus_cntl); + if (adev->mode_info.num_crtc) { + WREG32(mmD1VGA_CONTROL, d1vga_control); + WREG32(mmD2VGA_CONTROL, d2vga_control); + WREG32(mmVGA_RENDER_CONTROL, vga_render_control); + } + WREG32_SMC(ixROM_CNTL, rom_cntl); + return r; +} + +static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { + {mmGRBM_STATUS, false}, + {mmGB_ADDR_CONFIG, false}, + {mmMC_ARB_RAMCFG, false}, + {mmGB_TILE_MODE0, false}, + {mmGB_TILE_MODE1, false}, + {mmGB_TILE_MODE2, false}, + {mmGB_TILE_MODE3, false}, + {mmGB_TILE_MODE4, false}, + {mmGB_TILE_MODE5, false}, + {mmGB_TILE_MODE6, false}, + {mmGB_TILE_MODE7, false}, + {mmGB_TILE_MODE8, false}, + {mmGB_TILE_MODE9, false}, + {mmGB_TILE_MODE10, false}, + {mmGB_TILE_MODE11, false}, + {mmGB_TILE_MODE12, false}, + {mmGB_TILE_MODE13, false}, + {mmGB_TILE_MODE14, false}, + {mmGB_TILE_MODE15, false}, + {mmGB_TILE_MODE16, false}, + {mmGB_TILE_MODE17, false}, + {mmGB_TILE_MODE18, false}, + {mmGB_TILE_MODE19, false}, + {mmGB_TILE_MODE20, false}, + {mmGB_TILE_MODE21, false}, + {mmGB_TILE_MODE22, false}, + {mmGB_TILE_MODE23, false}, + {mmGB_TILE_MODE24, false}, + {mmGB_TILE_MODE25, false}, + {mmGB_TILE_MODE26, false}, + {mmGB_TILE_MODE27, false}, + {mmGB_TILE_MODE28, false}, + {mmGB_TILE_MODE29, false}, + {mmGB_TILE_MODE30, false}, + {mmGB_TILE_MODE31, false}, + {mmGB_MACROTILE_MODE0, false}, + {mmGB_MACROTILE_MODE1, false}, + {mmGB_MACROTILE_MODE2, false}, + {mmGB_MACROTILE_MODE3, false}, + {mmGB_MACROTILE_MODE4, false}, + {mmGB_MACROTILE_MODE5, false}, + {mmGB_MACROTILE_MODE6, false}, + {mmGB_MACROTILE_MODE7, false}, + {mmGB_MACROTILE_MODE8, false}, + {mmGB_MACROTILE_MODE9, false}, + {mmGB_MACROTILE_MODE10, false}, + {mmGB_MACROTILE_MODE11, false}, + {mmGB_MACROTILE_MODE12, false}, + {mmGB_MACROTILE_MODE13, false}, + {mmGB_MACROTILE_MODE14, false}, + {mmGB_MACROTILE_MODE15, false}, + {mmCC_RB_BACKEND_DISABLE, false, true}, + {mmGC_USER_RB_BACKEND_DISABLE, false, true}, + {mmGB_BACKEND_MAP, false, false}, + {mmPA_SC_RASTER_CONFIG, false, true}, + {mmPA_SC_RASTER_CONFIG_1, false, true}, +}; + +static uint32_t cik_read_indexed_register(struct amdgpu_device *adev, + u32 se_num, u32 sh_num, + u32 reg_offset) +{ + uint32_t val; + + mutex_lock(&adev->grbm_idx_mutex); + if (se_num != 0xffffffff || sh_num != 0xffffffff) + gfx_v7_0_select_se_sh(adev, se_num, sh_num); + + val = RREG32(reg_offset); + + if (se_num != 0xffffffff || sh_num != 0xffffffff) + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + return val; +} + +static int cik_read_register(struct amdgpu_device *adev, u32 se_num, + u32 sh_num, u32 reg_offset, u32 *value) +{ + uint32_t i; + + *value = 0; + for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) { + if (reg_offset != cik_allowed_read_registers[i].reg_offset) + continue; + + if (!cik_allowed_read_registers[i].untouched) + *value = cik_allowed_read_registers[i].grbm_indexed ? + cik_read_indexed_register(adev, se_num, + sh_num, reg_offset) : + RREG32(reg_offset); + return 0; + } + return -EINVAL; +} + +static void cik_print_gpu_status_regs(struct amdgpu_device *adev) +{ + dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", + RREG32(mmGRBM_STATUS)); + dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", + RREG32(mmGRBM_STATUS2)); + dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", + RREG32(mmGRBM_STATUS_SE0)); + dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", + RREG32(mmGRBM_STATUS_SE1)); + dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", + RREG32(mmGRBM_STATUS_SE2)); + dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", + RREG32(mmGRBM_STATUS_SE3)); + dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", + RREG32(mmSRBM_STATUS)); + dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", + RREG32(mmSRBM_STATUS2)); + dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n", + RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); + dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n", + RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); + dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); + dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT1)); + dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT2)); + dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT3)); + dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", + RREG32(mmCP_CPF_BUSY_STAT)); + dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_CPF_STALLED_STAT1)); + dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); + dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); + dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_CPC_STALLED_STAT1)); + dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); +} + +/** + * cik_gpu_check_soft_reset - check which blocks are busy + * + * @adev: amdgpu_device pointer + * + * Check which blocks are busy and return the relevant reset + * mask to be used by cik_gpu_soft_reset(). + * Returns a mask of the blocks to be reset. + */ +u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev) +{ + u32 reset_mask = 0; + u32 tmp; + + /* GRBM_STATUS */ + tmp = RREG32(mmGRBM_STATUS); + if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | + GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | + GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | + GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | + GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | + GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) + reset_mask |= AMDGPU_RESET_GFX; + + if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) + reset_mask |= AMDGPU_RESET_CP; + + /* GRBM_STATUS2 */ + tmp = RREG32(mmGRBM_STATUS2); + if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) + reset_mask |= AMDGPU_RESET_RLC; + + /* SDMA0_STATUS_REG */ + tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); + if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) + reset_mask |= AMDGPU_RESET_DMA; + + /* SDMA1_STATUS_REG */ + tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); + if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) + reset_mask |= AMDGPU_RESET_DMA1; + + /* SRBM_STATUS2 */ + tmp = RREG32(mmSRBM_STATUS2); + if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) + reset_mask |= AMDGPU_RESET_DMA; + + if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) + reset_mask |= AMDGPU_RESET_DMA1; + + /* SRBM_STATUS */ + tmp = RREG32(mmSRBM_STATUS); + + if (tmp & SRBM_STATUS__IH_BUSY_MASK) + reset_mask |= AMDGPU_RESET_IH; + + if (tmp & SRBM_STATUS__SEM_BUSY_MASK) + reset_mask |= AMDGPU_RESET_SEM; + + if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) + reset_mask |= AMDGPU_RESET_GRBM; + + if (tmp & SRBM_STATUS__VMC_BUSY_MASK) + reset_mask |= AMDGPU_RESET_VMC; + + if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | + SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) + reset_mask |= AMDGPU_RESET_MC; + + if (amdgpu_display_is_display_hung(adev)) + reset_mask |= AMDGPU_RESET_DISPLAY; + + /* Skip MC reset as it's mostly likely not hung, just busy */ + if (reset_mask & AMDGPU_RESET_MC) { + DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); + reset_mask &= ~AMDGPU_RESET_MC; + } + + return reset_mask; +} + +/** + * cik_gpu_soft_reset - soft reset GPU + * + * @adev: amdgpu_device pointer + * @reset_mask: mask of which blocks to reset + * + * Soft reset the blocks specified in @reset_mask. + */ +static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask) +{ + struct amdgpu_mode_mc_save save; + u32 grbm_soft_reset = 0, srbm_soft_reset = 0; + u32 tmp; + + if (reset_mask == 0) + return; + + dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask); + + cik_print_gpu_status_regs(adev); + dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); + dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); + + /* disable CG/PG */ + + /* stop the rlc */ + gfx_v7_0_rlc_stop(adev); + + /* Disable GFX parsing/prefetching */ + WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); + + /* Disable MEC parsing/prefetching */ + WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); + + if (reset_mask & AMDGPU_RESET_DMA) { + /* sdma0 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); + tmp |= SDMA0_F32_CNTL__HALT_MASK; + WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); + } + if (reset_mask & AMDGPU_RESET_DMA1) { + /* sdma1 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); + tmp |= SDMA0_F32_CNTL__HALT_MASK; + WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); + } + + gmc_v7_0_mc_stop(adev, &save); + if (amdgpu_asic_wait_for_mc_idle(adev)) { + dev_warn(adev->dev, "Wait for MC idle timedout !\n"); + } + + if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) + grbm_soft_reset = GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | + GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; + + if (reset_mask & AMDGPU_RESET_CP) { + grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; + + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; + } + + if (reset_mask & AMDGPU_RESET_DMA) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; + + if (reset_mask & AMDGPU_RESET_DMA1) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; + + if (reset_mask & AMDGPU_RESET_DISPLAY) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; + + if (reset_mask & AMDGPU_RESET_RLC) + grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; + + if (reset_mask & AMDGPU_RESET_SEM) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK; + + if (reset_mask & AMDGPU_RESET_IH) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; + + if (reset_mask & AMDGPU_RESET_GRBM) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; + + if (reset_mask & AMDGPU_RESET_VMC) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK; + + if (!(adev->flags & AMDGPU_IS_APU)) { + if (reset_mask & AMDGPU_RESET_MC) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK; + } + + if (grbm_soft_reset) { + tmp = RREG32(mmGRBM_SOFT_RESET); + tmp |= grbm_soft_reset; + dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmGRBM_SOFT_RESET, tmp); + tmp = RREG32(mmGRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~grbm_soft_reset; + WREG32(mmGRBM_SOFT_RESET, tmp); + tmp = RREG32(mmGRBM_SOFT_RESET); + } + + if (srbm_soft_reset) { + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + } + + /* Wait a little for things to settle down */ + udelay(50); + + gmc_v7_0_mc_resume(adev, &save); + udelay(50); + + cik_print_gpu_status_regs(adev); +} + +struct kv_reset_save_regs { + u32 gmcon_reng_execute; + u32 gmcon_misc; + u32 gmcon_misc3; +}; + +static void kv_save_regs_for_reset(struct amdgpu_device *adev, + struct kv_reset_save_regs *save) +{ + save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE); + save->gmcon_misc = RREG32(mmGMCON_MISC); + save->gmcon_misc3 = RREG32(mmGMCON_MISC3); + + WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute & + ~GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK); + WREG32(mmGMCON_MISC, save->gmcon_misc & + ~(GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK | + GMCON_MISC__STCTRL_STUTTER_EN_MASK)); +} + +static void kv_restore_regs_for_reset(struct amdgpu_device *adev, + struct kv_reset_save_regs *save) +{ + int i; + + WREG32(mmGMCON_PGFSM_WRITE, 0); + WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff); + + for (i = 0; i < 5; i++) + WREG32(mmGMCON_PGFSM_WRITE, 0); + + WREG32(mmGMCON_PGFSM_WRITE, 0); + WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff); + + for (i = 0; i < 5; i++) + WREG32(mmGMCON_PGFSM_WRITE, 0); + + WREG32(mmGMCON_PGFSM_WRITE, 0x210000); + WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff); + + for (i = 0; i < 5; i++) + WREG32(mmGMCON_PGFSM_WRITE, 0); + + WREG32(mmGMCON_PGFSM_WRITE, 0x21003); + WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff); + + for (i = 0; i < 5; i++) + WREG32(mmGMCON_PGFSM_WRITE, 0); + + WREG32(mmGMCON_PGFSM_WRITE, 0x2b00); + WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff); + + for (i = 0; i < 5; i++) + WREG32(mmGMCON_PGFSM_WRITE, 0); + + WREG32(mmGMCON_PGFSM_WRITE, 0); + WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff); + + for (i = 0; i < 5; i++) + WREG32(mmGMCON_PGFSM_WRITE, 0); + + WREG32(mmGMCON_PGFSM_WRITE, 0x420000); + WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff); + + for (i = 0; i < 5; i++) + WREG32(mmGMCON_PGFSM_WRITE, 0); + + WREG32(mmGMCON_PGFSM_WRITE, 0x120202); + WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff); + + for (i = 0; i < 5; i++) + WREG32(mmGMCON_PGFSM_WRITE, 0); + + WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36); + WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff); + + for (i = 0; i < 5; i++) + WREG32(mmGMCON_PGFSM_WRITE, 0); + + WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e); + WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff); + + for (i = 0; i < 5; i++) + WREG32(mmGMCON_PGFSM_WRITE, 0); + + WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332); + WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff); + + WREG32(mmGMCON_MISC3, save->gmcon_misc3); + WREG32(mmGMCON_MISC, save->gmcon_misc); + WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute); +} + +static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) +{ + struct amdgpu_mode_mc_save save; + struct kv_reset_save_regs kv_save = { 0 }; + u32 tmp, i; + + dev_info(adev->dev, "GPU pci config reset\n"); + + /* disable dpm? */ + + /* disable cg/pg */ + + /* Disable GFX parsing/prefetching */ + WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | + CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); + + /* Disable MEC parsing/prefetching */ + WREG32(mmCP_MEC_CNTL, + CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); + + /* sdma0 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); + tmp |= SDMA0_F32_CNTL__HALT_MASK; + WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); + /* sdma1 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); + tmp |= SDMA0_F32_CNTL__HALT_MASK; + WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); + /* XXX other engines? */ + + /* halt the rlc, disable cp internal ints */ + gfx_v7_0_rlc_stop(adev); + + udelay(50); + + /* disable mem access */ + gmc_v7_0_mc_stop(adev, &save); + if (amdgpu_asic_wait_for_mc_idle(adev)) { + dev_warn(adev->dev, "Wait for MC idle timed out !\n"); + } + + if (adev->flags & AMDGPU_IS_APU) + kv_save_regs_for_reset(adev, &kv_save); + + /* disable BM */ + pci_clear_master(adev->pdev); + /* reset */ + amdgpu_pci_config_reset(adev); + + udelay(100); + + /* wait for asic to come out of reset */ + for (i = 0; i < adev->usec_timeout; i++) { + if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) + break; + udelay(1); + } + + /* does asic init need to be run first??? */ + if (adev->flags & AMDGPU_IS_APU) + kv_restore_regs_for_reset(adev, &kv_save); +} + +static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) +{ + u32 tmp = RREG32(mmBIOS_SCRATCH_3); + + if (hung) + tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; + else + tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; + + WREG32(mmBIOS_SCRATCH_3, tmp); +} + +/** + * cik_asic_reset - soft reset GPU + * + * @adev: amdgpu_device pointer + * + * Look up which blocks are hung and attempt + * to reset them. + * Returns 0 for success. + */ +static int cik_asic_reset(struct amdgpu_device *adev) +{ + u32 reset_mask; + + reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); + + if (reset_mask) + cik_set_bios_scratch_engine_hung(adev, true); + + /* try soft reset */ + cik_gpu_soft_reset(adev, reset_mask); + + reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); + + /* try pci config reset */ + if (reset_mask && amdgpu_hard_reset) + cik_gpu_pci_config_reset(adev); + + reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); + + if (!reset_mask) + cik_set_bios_scratch_engine_hung(adev, false); + + return 0; +} + +static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock, + u32 cntl_reg, u32 status_reg) +{ + int r, i; + struct atom_clock_dividers dividers; + uint32_t tmp; + + r = amdgpu_atombios_get_clock_dividers(adev, + COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + clock, false, ÷rs); + if (r) + return r; + + tmp = RREG32_SMC(cntl_reg); + tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | + CG_DCLK_CNTL__DCLK_DIVIDER_MASK); + tmp |= dividers.post_divider; + WREG32_SMC(cntl_reg, tmp); + + for (i = 0; i < 100; i++) { + if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + return 0; +} + +static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) +{ + int r = 0; + + r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); + if (r) + return r; + + r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); + return r; +} + +static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) +{ + int r, i; + struct atom_clock_dividers dividers; + u32 tmp; + + r = amdgpu_atombios_get_clock_dividers(adev, + COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + ecclk, false, ÷rs); + if (r) + return r; + + for (i = 0; i < 100; i++) { + if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + tmp = RREG32_SMC(ixCG_ECLK_CNTL); + tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | + CG_ECLK_CNTL__ECLK_DIVIDER_MASK); + tmp |= dividers.post_divider; + WREG32_SMC(ixCG_ECLK_CNTL, tmp); + + for (i = 0; i < 100; i++) { + if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + return 0; +} + +static void cik_pcie_gen3_enable(struct amdgpu_device *adev) +{ + struct pci_dev *root = adev->pdev->bus->self; + int bridge_pos, gpu_pos; + u32 speed_cntl, mask, current_data_rate; + int ret, i; + u16 tmp16; + + if (amdgpu_pcie_gen2 == 0) + return; + + if (adev->flags & AMDGPU_IS_APU) + return; + + ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); + if (ret != 0) + return; + + if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) + return; + + speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); + current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >> + PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; + if (mask & DRM_PCIE_SPEED_80) { + if (current_data_rate == 2) { + DRM_INFO("PCIE gen 3 link speeds already enabled\n"); + return; + } + DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); + } else if (mask & DRM_PCIE_SPEED_50) { + if (current_data_rate == 1) { + DRM_INFO("PCIE gen 2 link speeds already enabled\n"); + return; + } + DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); + } + + bridge_pos = pci_pcie_cap(root); + if (!bridge_pos) + return; + + gpu_pos = pci_pcie_cap(adev->pdev); + if (!gpu_pos) + return; + + if (mask & DRM_PCIE_SPEED_80) { + /* re-try equalization if gen3 is not already enabled */ + if (current_data_rate != 2) { + u16 bridge_cfg, gpu_cfg; + u16 bridge_cfg2, gpu_cfg2; + u32 max_lw, current_lw, tmp; + + pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); + pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + + tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; + pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); + + tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; + pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + + tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); + max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> + PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT; + current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK) + >> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT; + + if (current_lw < max_lw) { + tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); + if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) { + tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK | + PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK); + tmp |= (max_lw << + PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT); + tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK | + PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK | + PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK; + WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp); + } + } + + for (i = 0; i < 10; i++) { + /* check status */ + pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); + if (tmp16 & PCI_EXP_DEVSTA_TRPND) + break; + + pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); + pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + + pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); + pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); + + tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); + tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; + WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); + + tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); + tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK; + WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); + + mdelay(100); + + /* linkctl */ + pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); + tmp16 &= ~PCI_EXP_LNKCTL_HAWD; + tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); + pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); + + pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); + tmp16 &= ~PCI_EXP_LNKCTL_HAWD; + tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); + pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + + /* linkctl2 */ + pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); + tmp16 &= ~((1 << 4) | (7 << 9)); + tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); + pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); + + pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); + tmp16 &= ~((1 << 4) | (7 << 9)); + tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); + pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + + tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); + tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; + WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); + } + } + } + + /* set the link speed */ + speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK | + PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK; + speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; + WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); + + pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); + tmp16 &= ~0xf; + if (mask & DRM_PCIE_SPEED_80) + tmp16 |= 3; /* gen3 */ + else if (mask & DRM_PCIE_SPEED_50) + tmp16 |= 2; /* gen2 */ + else + tmp16 |= 1; /* gen1 */ + pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + + speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); + speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK; + WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); + + for (i = 0; i < adev->usec_timeout; i++) { + speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); + if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0) + break; + udelay(1); + } +} + +static void cik_program_aspm(struct amdgpu_device *adev) +{ + u32 data, orig; + bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false; + bool disable_clkreq = false; + + if (amdgpu_aspm == 0) + return; + + /* XXX double check APUs */ + if (adev->flags & AMDGPU_IS_APU) + return; + + orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); + data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK; + data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) | + PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK; + if (orig != data) + WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); + + orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); + data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK; + if (orig != data) + WREG32_PCIE(ixPCIE_LC_CNTL3, data); + + orig = data = RREG32_PCIE(ixPCIE_P_CNTL); + data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK; + if (orig != data) + WREG32_PCIE(ixPCIE_P_CNTL, data); + + orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); + data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | + PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK); + data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; + if (!disable_l0s) + data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT); + + if (!disable_l1) { + data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT); + data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; + if (orig != data) + WREG32_PCIE(ixPCIE_LC_CNTL, data); + + if (!disable_plloff_in_l1) { + bool clk_req_support; + + orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_0); + data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | + PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); + data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | + (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); + if (orig != data) + WREG32_PCIE(ixPB0_PIF_PWRDOWN_0, data); + + orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_1); + data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | + PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); + data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | + (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); + if (orig != data) + WREG32_PCIE(ixPB0_PIF_PWRDOWN_1, data); + + orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_0); + data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | + PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); + data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | + (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); + if (orig != data) + WREG32_PCIE(ixPB1_PIF_PWRDOWN_0, data); + + orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_1); + data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | + PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); + data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | + (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); + if (orig != data) + WREG32_PCIE(ixPB1_PIF_PWRDOWN_1, data); + + orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); + data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK; + data |= ~(3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT); + if (orig != data) + WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data); + + if (!disable_clkreq) { + struct pci_dev *root = adev->pdev->bus->self; + u32 lnkcap; + + clk_req_support = false; + pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap); + if (lnkcap & PCI_EXP_LNKCAP_CLKPM) + clk_req_support = true; + } else { + clk_req_support = false; + } + + if (clk_req_support) { + orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2); + data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | + PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; + if (orig != data) + WREG32_PCIE(ixPCIE_LC_CNTL2, data); + + orig = data = RREG32_SMC(ixTHM_CLK_CNTL); + data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | + THM_CLK_CNTL__TMON_CLK_SEL_MASK); + data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) | + (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT); + if (orig != data) + WREG32_SMC(ixTHM_CLK_CNTL, data); + + orig = data = RREG32_SMC(ixMISC_CLK_CTRL); + data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK | + MISC_CLK_CTRL__ZCLK_SEL_MASK); + data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) | + (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT); + if (orig != data) + WREG32_SMC(ixMISC_CLK_CTRL, data); + + orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); + data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK; + if (orig != data) + WREG32_SMC(ixCG_CLKPIN_CNTL, data); + + orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2); + data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK; + if (orig != data) + WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); + + orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL); + data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK; + data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT); + if (orig != data) + WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); + } + } + } else { + if (orig != data) + WREG32_PCIE(ixPCIE_LC_CNTL, data); + } + + orig = data = RREG32_PCIE(ixPCIE_CNTL2); + data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | + PCIE_CNTL2__MST_MEM_LS_EN_MASK | + PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; + if (orig != data) + WREG32_PCIE(ixPCIE_CNTL2, data); + + if (!disable_l0s) { + data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); + if ((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == + PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) { + data = RREG32_PCIE(ixPCIE_LC_STATUS1); + if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) && + (data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) { + orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); + data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; + if (orig != data) + WREG32_PCIE(ixPCIE_LC_CNTL, data); + } + } + } +} + +static uint32_t cik_get_rev_id(struct amdgpu_device *adev) +{ + return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) + >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; +} + +static const struct amdgpu_ip_block_version bonaire_ip_blocks[] = +{ + /* ORDER MATTERS! */ + { + .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &cik_common_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &gmc_v7_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_IH, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_ih_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &ci_dpm_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 2, + .rev = 0, + .funcs = &dce_v8_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .major = 7, + .minor = 2, + .rev = 0, + .funcs = &gfx_v7_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_sdma_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .major = 4, + .minor = 2, + .rev = 0, + .funcs = &uvd_v4_2_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vce_v2_0_ip_funcs, + }, +}; + +static const struct amdgpu_ip_block_version hawaii_ip_blocks[] = +{ + /* ORDER MATTERS! */ + { + .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &cik_common_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &gmc_v7_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_IH, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_ih_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &ci_dpm_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 5, + .rev = 0, + .funcs = &dce_v8_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .major = 7, + .minor = 3, + .rev = 0, + .funcs = &gfx_v7_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_sdma_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .major = 4, + .minor = 2, + .rev = 0, + .funcs = &uvd_v4_2_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vce_v2_0_ip_funcs, + }, +}; + +static const struct amdgpu_ip_block_version kabini_ip_blocks[] = +{ + /* ORDER MATTERS! */ + { + .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &cik_common_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &gmc_v7_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_IH, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_ih_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &kv_dpm_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 3, + .rev = 0, + .funcs = &dce_v8_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .major = 7, + .minor = 2, + .rev = 0, + .funcs = &gfx_v7_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_sdma_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .major = 4, + .minor = 2, + .rev = 0, + .funcs = &uvd_v4_2_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vce_v2_0_ip_funcs, + }, +}; + +static const struct amdgpu_ip_block_version mullins_ip_blocks[] = +{ + /* ORDER MATTERS! */ + { + .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &cik_common_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &gmc_v7_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_IH, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_ih_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &kv_dpm_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 3, + .rev = 0, + .funcs = &dce_v8_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .major = 7, + .minor = 2, + .rev = 0, + .funcs = &gfx_v7_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_sdma_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .major = 4, + .minor = 2, + .rev = 0, + .funcs = &uvd_v4_2_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vce_v2_0_ip_funcs, + }, +}; + +static const struct amdgpu_ip_block_version kaveri_ip_blocks[] = +{ + /* ORDER MATTERS! */ + { + .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &cik_common_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &gmc_v7_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_IH, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_ih_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &kv_dpm_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 1, + .rev = 0, + .funcs = &dce_v8_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .major = 7, + .minor = 1, + .rev = 0, + .funcs = &gfx_v7_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_sdma_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .major = 4, + .minor = 2, + .rev = 0, + .funcs = &uvd_v4_2_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vce_v2_0_ip_funcs, + }, +}; + +int cik_set_ip_blocks(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_BONAIRE: + adev->ip_blocks = bonaire_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks); + break; + case CHIP_HAWAII: + adev->ip_blocks = hawaii_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks); + break; + case CHIP_KAVERI: + adev->ip_blocks = kaveri_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks); + break; + case CHIP_KABINI: + adev->ip_blocks = kabini_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks); + break; + case CHIP_MULLINS: + adev->ip_blocks = mullins_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks); + break; + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + + adev->ip_block_enabled = kcalloc(adev->num_ip_blocks, sizeof(bool), GFP_KERNEL); + if (adev->ip_block_enabled == NULL) + return -ENOMEM; + + return 0; +} + +static const struct amdgpu_asic_funcs cik_asic_funcs = +{ + .read_disabled_bios = &cik_read_disabled_bios, + .read_register = &cik_read_register, + .reset = &cik_asic_reset, + .set_vga_state = &cik_vga_set_state, + .get_xclk = &cik_get_xclk, + .set_uvd_clocks = &cik_set_uvd_clocks, + .set_vce_clocks = &cik_set_vce_clocks, + .get_cu_info = &gfx_v7_0_get_cu_info, + /* these should be moved to their own ip modules */ + .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, + .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle, +}; + +static int cik_common_early_init(struct amdgpu_device *adev) +{ + adev->smc_rreg = &cik_smc_rreg; + adev->smc_wreg = &cik_smc_wreg; + adev->pcie_rreg = &cik_pcie_rreg; + adev->pcie_wreg = &cik_pcie_wreg; + adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg; + adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg; + adev->didt_rreg = &cik_didt_rreg; + adev->didt_wreg = &cik_didt_wreg; + + adev->asic_funcs = &cik_asic_funcs; + + adev->has_uvd = true; + + adev->rev_id = cik_get_rev_id(adev); + adev->external_rev_id = 0xFF; + switch (adev->asic_type) { + case CHIP_BONAIRE: + adev->cg_flags = + AMDGPU_CG_SUPPORT_GFX_MGCG | + AMDGPU_CG_SUPPORT_GFX_MGLS | + /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ + AMDGPU_CG_SUPPORT_GFX_CGLS | + AMDGPU_CG_SUPPORT_GFX_CGTS | + AMDGPU_CG_SUPPORT_GFX_CGTS_LS | + AMDGPU_CG_SUPPORT_GFX_CP_LS | + AMDGPU_CG_SUPPORT_MC_LS | + AMDGPU_CG_SUPPORT_MC_MGCG | + AMDGPU_CG_SUPPORT_SDMA_MGCG | + AMDGPU_CG_SUPPORT_SDMA_LS | + AMDGPU_CG_SUPPORT_BIF_LS | + AMDGPU_CG_SUPPORT_VCE_MGCG | + AMDGPU_CG_SUPPORT_UVD_MGCG | + AMDGPU_CG_SUPPORT_HDP_LS | + AMDGPU_CG_SUPPORT_HDP_MGCG; + adev->pg_flags = 0; + adev->external_rev_id = adev->rev_id + 0x14; + break; + case CHIP_HAWAII: + adev->cg_flags = + AMDGPU_CG_SUPPORT_GFX_MGCG | + AMDGPU_CG_SUPPORT_GFX_MGLS | + /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ + AMDGPU_CG_SUPPORT_GFX_CGLS | + AMDGPU_CG_SUPPORT_GFX_CGTS | + AMDGPU_CG_SUPPORT_GFX_CP_LS | + AMDGPU_CG_SUPPORT_MC_LS | + AMDGPU_CG_SUPPORT_MC_MGCG | + AMDGPU_CG_SUPPORT_SDMA_MGCG | + AMDGPU_CG_SUPPORT_SDMA_LS | + AMDGPU_CG_SUPPORT_BIF_LS | + AMDGPU_CG_SUPPORT_VCE_MGCG | + AMDGPU_CG_SUPPORT_UVD_MGCG | + AMDGPU_CG_SUPPORT_HDP_LS | + AMDGPU_CG_SUPPORT_HDP_MGCG; + adev->pg_flags = 0; + adev->external_rev_id = 0x28; + break; + case CHIP_KAVERI: + adev->cg_flags = + AMDGPU_CG_SUPPORT_GFX_MGCG | + AMDGPU_CG_SUPPORT_GFX_MGLS | + /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ + AMDGPU_CG_SUPPORT_GFX_CGLS | + AMDGPU_CG_SUPPORT_GFX_CGTS | + AMDGPU_CG_SUPPORT_GFX_CGTS_LS | + AMDGPU_CG_SUPPORT_GFX_CP_LS | + AMDGPU_CG_SUPPORT_SDMA_MGCG | + AMDGPU_CG_SUPPORT_SDMA_LS | + AMDGPU_CG_SUPPORT_BIF_LS | + AMDGPU_CG_SUPPORT_VCE_MGCG | + AMDGPU_CG_SUPPORT_UVD_MGCG | + AMDGPU_CG_SUPPORT_HDP_LS | + AMDGPU_CG_SUPPORT_HDP_MGCG; + adev->pg_flags = + /*AMDGPU_PG_SUPPORT_GFX_PG | + AMDGPU_PG_SUPPORT_GFX_SMG | + AMDGPU_PG_SUPPORT_GFX_DMG |*/ + AMDGPU_PG_SUPPORT_UVD | + /*AMDGPU_PG_SUPPORT_VCE | + AMDGPU_PG_SUPPORT_CP | + AMDGPU_PG_SUPPORT_GDS | + AMDGPU_PG_SUPPORT_RLC_SMU_HS | + AMDGPU_PG_SUPPORT_ACP | + AMDGPU_PG_SUPPORT_SAMU |*/ + 0; + if (adev->pdev->device == 0x1312 || + adev->pdev->device == 0x1316 || + adev->pdev->device == 0x1317) + adev->external_rev_id = 0x41; + else + adev->external_rev_id = 0x1; + break; + case CHIP_KABINI: + case CHIP_MULLINS: + adev->cg_flags = + AMDGPU_CG_SUPPORT_GFX_MGCG | + AMDGPU_CG_SUPPORT_GFX_MGLS | + /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ + AMDGPU_CG_SUPPORT_GFX_CGLS | + AMDGPU_CG_SUPPORT_GFX_CGTS | + AMDGPU_CG_SUPPORT_GFX_CGTS_LS | + AMDGPU_CG_SUPPORT_GFX_CP_LS | + AMDGPU_CG_SUPPORT_SDMA_MGCG | + AMDGPU_CG_SUPPORT_SDMA_LS | + AMDGPU_CG_SUPPORT_BIF_LS | + AMDGPU_CG_SUPPORT_VCE_MGCG | + AMDGPU_CG_SUPPORT_UVD_MGCG | + AMDGPU_CG_SUPPORT_HDP_LS | + AMDGPU_CG_SUPPORT_HDP_MGCG; + adev->pg_flags = + /*AMDGPU_PG_SUPPORT_GFX_PG | + AMDGPU_PG_SUPPORT_GFX_SMG | */ + AMDGPU_PG_SUPPORT_UVD | + /*AMDGPU_PG_SUPPORT_VCE | + AMDGPU_PG_SUPPORT_CP | + AMDGPU_PG_SUPPORT_GDS | + AMDGPU_PG_SUPPORT_RLC_SMU_HS | + AMDGPU_PG_SUPPORT_SAMU |*/ + 0; + if (adev->asic_type == CHIP_KABINI) { + if (adev->rev_id == 0) + adev->external_rev_id = 0x81; + else if (adev->rev_id == 1) + adev->external_rev_id = 0x82; + else if (adev->rev_id == 2) + adev->external_rev_id = 0x85; + } else + adev->external_rev_id = adev->rev_id + 0xa1; + break; + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + + return 0; +} + +static int cik_common_sw_init(struct amdgpu_device *adev) +{ + return 0; +} + +static int cik_common_sw_fini(struct amdgpu_device *adev) +{ + return 0; +} + +static int cik_common_hw_init(struct amdgpu_device *adev) +{ + /* move the golden regs per IP block */ + cik_init_golden_registers(adev); + /* enable pcie gen2/3 link */ + cik_pcie_gen3_enable(adev); + /* enable aspm */ + cik_program_aspm(adev); + + return 0; +} + +static int cik_common_hw_fini(struct amdgpu_device *adev) +{ + return 0; +} + +static int cik_common_suspend(struct amdgpu_device *adev) +{ + return cik_common_hw_fini(adev); +} + +static int cik_common_resume(struct amdgpu_device *adev) +{ + return cik_common_hw_init(adev); +} + +static bool cik_common_is_idle(struct amdgpu_device *adev) +{ + return true; +} + +static int cik_common_wait_for_idle(struct amdgpu_device *adev) +{ + return 0; +} + +static void cik_common_print_status(struct amdgpu_device *adev) +{ + +} + +static int cik_common_soft_reset(struct amdgpu_device *adev) +{ + /* XXX hard reset?? */ + return 0; +} + +static int cik_common_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static int cik_common_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs cik_common_ip_funcs = { + .early_init = cik_common_early_init, + .late_init = NULL, + .sw_init = cik_common_sw_init, + .sw_fini = cik_common_sw_fini, + .hw_init = cik_common_hw_init, + .hw_fini = cik_common_hw_fini, + .suspend = cik_common_suspend, + .resume = cik_common_resume, + .is_idle = cik_common_is_idle, + .wait_for_idle = cik_common_wait_for_idle, + .soft_reset = cik_common_soft_reset, + .print_status = cik_common_print_status, + .set_clockgating_state = cik_common_set_clockgating_state, + .set_powergating_state = cik_common_set_powergating_state, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h new file mode 100644 index 000000000000..967d630a4dcb --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cik.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __CIK_H__ +#define __CIK_H__ + +extern const struct amdgpu_ip_funcs cik_common_ip_funcs; + +void cik_srbm_select(struct amdgpu_device *adev, + u32 me, u32 pipe, u32 queue, u32 vmid); +int cik_set_ip_blocks(struct amdgpu_device *adev); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h new file mode 100644 index 000000000000..35d8efdcde7e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h @@ -0,0 +1,30 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __CIK_DPM_H__ +#define __CIK_DPM_H__ + +extern const struct amdgpu_ip_funcs ci_dpm_ip_funcs; +extern const struct amdgpu_ip_funcs kv_dpm_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c new file mode 100644 index 000000000000..81e8bbaba3e8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -0,0 +1,453 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_ih.h" +#include "cikd.h" + +#include "bif/bif_4_1_d.h" +#include "bif/bif_4_1_sh_mask.h" + +#include "oss/oss_2_0_d.h" +#include "oss/oss_2_0_sh_mask.h" + +/* + * Interrupts + * Starting with r6xx, interrupts are handled via a ring buffer. + * Ring buffers are areas of GPU accessible memory that the GPU + * writes interrupt vectors into and the host reads vectors out of. + * There is a rptr (read pointer) that determines where the + * host is currently reading, and a wptr (write pointer) + * which determines where the GPU has written. When the + * pointers are equal, the ring is idle. When the GPU + * writes vectors to the ring buffer, it increments the + * wptr. When there is an interrupt, the host then starts + * fetching commands and processing them until the pointers are + * equal again at which point it updates the rptr. + */ + +static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev); + +/** + * cik_ih_enable_interrupts - Enable the interrupt ring buffer + * + * @adev: amdgpu_device pointer + * + * Enable the interrupt ring buffer (CIK). + */ +static void cik_ih_enable_interrupts(struct amdgpu_device *adev) +{ + u32 ih_cntl = RREG32(mmIH_CNTL); + u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); + + ih_cntl |= IH_CNTL__ENABLE_INTR_MASK; + ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK; + WREG32(mmIH_CNTL, ih_cntl); + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + adev->irq.ih.enabled = true; +} + +/** + * cik_ih_disable_interrupts - Disable the interrupt ring buffer + * + * @adev: amdgpu_device pointer + * + * Disable the interrupt ring buffer (CIK). + */ +static void cik_ih_disable_interrupts(struct amdgpu_device *adev) +{ + u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); + u32 ih_cntl = RREG32(mmIH_CNTL); + + ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK; + ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK; + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + WREG32(mmIH_CNTL, ih_cntl); + /* set rptr, wptr to 0 */ + WREG32(mmIH_RB_RPTR, 0); + WREG32(mmIH_RB_WPTR, 0); + adev->irq.ih.enabled = false; + adev->irq.ih.rptr = 0; +} + +/** + * cik_ih_irq_init - init and enable the interrupt ring + * + * @adev: amdgpu_device pointer + * + * Allocate a ring buffer for the interrupt controller, + * enable the RLC, disable interrupts, enable the IH + * ring buffer and enable it (CIK). + * Called at device load and reume. + * Returns 0 for success, errors for failure. + */ +static int cik_ih_irq_init(struct amdgpu_device *adev) +{ + int ret = 0; + int rb_bufsz; + u32 interrupt_cntl, ih_cntl, ih_rb_cntl; + u64 wptr_off; + + /* disable irqs */ + cik_ih_disable_interrupts(adev); + + /* setup interrupt control */ + WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); + interrupt_cntl = RREG32(mmINTERRUPT_CNTL); + /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi + * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN + */ + interrupt_cntl &= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK; + /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ + interrupt_cntl &= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK; + WREG32(mmINTERRUPT_CNTL, interrupt_cntl); + + WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); + rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); + + ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK | + IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK | + (rb_bufsz << 1)); + + ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK; + + /* set the writeback address whether it's enabled or not */ + wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); + WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); + WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); + + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + + /* set rptr, wptr to 0 */ + WREG32(mmIH_RB_RPTR, 0); + WREG32(mmIH_RB_WPTR, 0); + + /* Default settings for IH_CNTL (disabled at first) */ + ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) | + (0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT) | + (0 << IH_CNTL__MC_VMID__SHIFT); + /* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */ + if (adev->irq.msi_enabled) + ih_cntl |= IH_CNTL__RPTR_REARM_MASK; + WREG32(mmIH_CNTL, ih_cntl); + + pci_set_master(adev->pdev); + + /* enable irqs */ + cik_ih_enable_interrupts(adev); + + return ret; +} + +/** + * cik_ih_irq_disable - disable interrupts + * + * @adev: amdgpu_device pointer + * + * Disable interrupts on the hw (CIK). + */ +static void cik_ih_irq_disable(struct amdgpu_device *adev) +{ + cik_ih_disable_interrupts(adev); + /* Wait and acknowledge irq */ + mdelay(1); +} + +/** + * cik_ih_get_wptr - get the IH ring buffer wptr + * + * @adev: amdgpu_device pointer + * + * Get the IH ring buffer wptr from either the register + * or the writeback memory buffer (CIK). Also check for + * ring buffer overflow and deal with it. + * Used by cik_irq_process(). + * Returns the value of the wptr. + */ +static u32 cik_ih_get_wptr(struct amdgpu_device *adev) +{ + u32 wptr, tmp; + + wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); + + if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { + wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; + /* When a ring buffer overflow happen start parsing interrupt + * from the last not overwritten vector (wptr + 16). Hopefully + * this should allow us to catchup. + */ + dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", + wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); + adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; + tmp = RREG32(mmIH_RB_CNTL); + tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; + WREG32(mmIH_RB_CNTL, tmp); + } + return (wptr & adev->irq.ih.ptr_mask); +} + +/* CIK IV Ring + * Each IV ring entry is 128 bits: + * [7:0] - interrupt source id + * [31:8] - reserved + * [59:32] - interrupt source data + * [63:60] - reserved + * [71:64] - RINGID + * CP: + * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0] + * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher + * - for gfx, hw shader state (0=PS...5=LS, 6=CS) + * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes + * PIPE_ID - ME0 0=3D + * - ME1&2 compute dispatcher (4 pipes each) + * SDMA: + * INSTANCE_ID [1:0], QUEUE_ID[1:0] + * INSTANCE_ID - 0 = sdma0, 1 = sdma1 + * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1 + * [79:72] - VMID + * [95:80] - PASID + * [127:96] - reserved + */ + + /** + * cik_ih_decode_iv - decode an interrupt vector + * + * @adev: amdgpu_device pointer + * + * Decodes the interrupt vector at the current rptr + * position and also advance the position. + */ +static void cik_ih_decode_iv(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry) +{ + /* wptr/rptr are in bytes! */ + u32 ring_index = adev->irq.ih.rptr >> 2; + uint32_t dw[4]; + + dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); + dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); + dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); + dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); + + entry->src_id = dw[0] & 0xff; + entry->src_data = dw[1] & 0xfffffff; + entry->ring_id = dw[2] & 0xff; + entry->vm_id = (dw[2] >> 8) & 0xff; + entry->pas_id = (dw[2] >> 16) & 0xffff; + + /* wptr/rptr are in bytes! */ + adev->irq.ih.rptr += 16; +} + +/** + * cik_ih_set_rptr - set the IH ring buffer rptr + * + * @adev: amdgpu_device pointer + * + * Set the IH ring buffer rptr. + */ +static void cik_ih_set_rptr(struct amdgpu_device *adev) +{ + WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); +} + +static int cik_ih_early_init(struct amdgpu_device *adev) +{ + cik_ih_set_interrupt_funcs(adev); + + return 0; +} + +static int cik_ih_sw_init(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_ih_ring_init(adev, 64 * 1024, false); + if (r) + return r; + + r = amdgpu_irq_init(adev); + + return r; +} + +static int cik_ih_sw_fini(struct amdgpu_device *adev) +{ + amdgpu_irq_fini(adev); + amdgpu_ih_ring_fini(adev); + + return 0; +} + +static int cik_ih_hw_init(struct amdgpu_device *adev) +{ + int r; + + r = cik_ih_irq_init(adev); + if (r) + return r; + + return 0; +} + +static int cik_ih_hw_fini(struct amdgpu_device *adev) +{ + cik_ih_irq_disable(adev); + + return 0; +} + +static int cik_ih_suspend(struct amdgpu_device *adev) +{ + return cik_ih_hw_fini(adev); +} + +static int cik_ih_resume(struct amdgpu_device *adev) +{ + return cik_ih_hw_init(adev); +} + +static bool cik_ih_is_idle(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmSRBM_STATUS); + + if (tmp & SRBM_STATUS__IH_BUSY_MASK) + return false; + + return true; +} + +static int cik_ih_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK; + if (!tmp) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static void cik_ih_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "CIK IH registers\n"); + dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", + RREG32(mmSRBM_STATUS)); + dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", + RREG32(mmSRBM_STATUS2)); + dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", + RREG32(mmINTERRUPT_CNTL)); + dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", + RREG32(mmINTERRUPT_CNTL2)); + dev_info(adev->dev, " IH_CNTL=0x%08X\n", + RREG32(mmIH_CNTL)); + dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", + RREG32(mmIH_RB_CNTL)); + dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", + RREG32(mmIH_RB_BASE)); + dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", + RREG32(mmIH_RB_WPTR_ADDR_LO)); + dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", + RREG32(mmIH_RB_WPTR_ADDR_HI)); + dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", + RREG32(mmIH_RB_RPTR)); + dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", + RREG32(mmIH_RB_WPTR)); +} + +static int cik_ih_soft_reset(struct amdgpu_device *adev) +{ + u32 srbm_soft_reset = 0; + u32 tmp = RREG32(mmSRBM_STATUS); + + if (tmp & SRBM_STATUS__IH_BUSY_MASK) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; + + if (srbm_soft_reset) { + cik_ih_print_status(adev); + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + + cik_ih_print_status(adev); + } + + return 0; +} + +static int cik_ih_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static int cik_ih_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs cik_ih_ip_funcs = { + .early_init = cik_ih_early_init, + .late_init = NULL, + .sw_init = cik_ih_sw_init, + .sw_fini = cik_ih_sw_fini, + .hw_init = cik_ih_hw_init, + .hw_fini = cik_ih_hw_fini, + .suspend = cik_ih_suspend, + .resume = cik_ih_resume, + .is_idle = cik_ih_is_idle, + .wait_for_idle = cik_ih_wait_for_idle, + .soft_reset = cik_ih_soft_reset, + .print_status = cik_ih_print_status, + .set_clockgating_state = cik_ih_set_clockgating_state, + .set_powergating_state = cik_ih_set_powergating_state, +}; + +static const struct amdgpu_ih_funcs cik_ih_funcs = { + .get_wptr = cik_ih_get_wptr, + .decode_iv = cik_ih_decode_iv, + .set_rptr = cik_ih_set_rptr +}; + +static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev) +{ + if (adev->irq.ih_funcs == NULL) + adev->irq.ih_funcs = &cik_ih_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.h b/drivers/gpu/drm/amd/amdgpu/cik_ih.h new file mode 100644 index 000000000000..f70162525034 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __CIK_IH_H__ +#define __CIK_IH_H__ + +extern const struct amdgpu_ip_funcs cik_ih_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c new file mode 100644 index 000000000000..ae2bb26fa46e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -0,0 +1,1422 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ +#include +#include +#include "amdgpu.h" +#include "amdgpu_ucode.h" +#include "amdgpu_trace.h" +#include "cikd.h" +#include "cik.h" + +#include "bif/bif_4_1_d.h" +#include "bif/bif_4_1_sh_mask.h" + +#include "gca/gfx_7_2_d.h" + +#include "gmc/gmc_7_1_d.h" +#include "gmc/gmc_7_1_sh_mask.h" + +#include "oss/oss_2_0_d.h" +#include "oss/oss_2_0_sh_mask.h" + +static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = +{ + SDMA0_REGISTER_OFFSET, + SDMA1_REGISTER_OFFSET +}; + +static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); +static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); +static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); +static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); + +MODULE_FIRMWARE("radeon/bonaire_sdma.bin"); +MODULE_FIRMWARE("radeon/bonaire_sdma1.bin"); +MODULE_FIRMWARE("radeon/hawaii_sdma.bin"); +MODULE_FIRMWARE("radeon/hawaii_sdma1.bin"); +MODULE_FIRMWARE("radeon/kaveri_sdma.bin"); +MODULE_FIRMWARE("radeon/kaveri_sdma1.bin"); +MODULE_FIRMWARE("radeon/kabini_sdma.bin"); +MODULE_FIRMWARE("radeon/kabini_sdma1.bin"); +MODULE_FIRMWARE("radeon/mullins_sdma.bin"); +MODULE_FIRMWARE("radeon/mullins_sdma1.bin"); + +u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); + +/* + * sDMA - System DMA + * Starting with CIK, the GPU has new asynchronous + * DMA engines. These engines are used for compute + * and gfx. There are two DMA engines (SDMA0, SDMA1) + * and each one supports 1 ring buffer used for gfx + * and 2 queues used for compute. + * + * The programming model is very similar to the CP + * (ring buffer, IBs, etc.), but sDMA has it's own + * packet format that is different from the PM4 format + * used by the CP. sDMA supports copying data, writing + * embedded data, solid fills, and a number of other + * things. It also has support for tiling/detiling of + * buffers. + */ + +/** + * cik_sdma_init_microcode - load ucode images from disk + * + * @adev: amdgpu_device pointer + * + * Use the firmware interface to load the ucode images into + * the driver (not loaded into hw). + * Returns 0 on success, error on failure. + */ +static int cik_sdma_init_microcode(struct amdgpu_device *adev) +{ + const char *chip_name; + char fw_name[30]; + int err, i; + + DRM_DEBUG("\n"); + + switch (adev->asic_type) { + case CHIP_BONAIRE: + chip_name = "bonaire"; + break; + case CHIP_HAWAII: + chip_name = "hawaii"; + break; + case CHIP_KAVERI: + chip_name = "kaveri"; + break; + case CHIP_KABINI: + chip_name = "kabini"; + break; + case CHIP_MULLINS: + chip_name = "mullins"; + break; + default: BUG(); + } + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + if (i == 0) + snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); + else + snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name); + err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->sdma[i].fw); + } +out: + if (err) { + printk(KERN_ERR + "cik_sdma: Failed to load firmware \"%s\"\n", + fw_name); + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + release_firmware(adev->sdma[i].fw); + adev->sdma[i].fw = NULL; + } + } + return err; +} + +/** + * cik_sdma_ring_get_rptr - get the current read pointer + * + * @ring: amdgpu ring pointer + * + * Get the current rptr from the hardware (CIK+). + */ +static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) +{ + u32 rptr; + + rptr = ring->adev->wb.wb[ring->rptr_offs]; + + return (rptr & 0x3fffc) >> 2; +} + +/** + * cik_sdma_ring_get_wptr - get the current write pointer + * + * @ring: amdgpu ring pointer + * + * Get the current wptr from the hardware (CIK+). + */ +static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1; + + return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; +} + +/** + * cik_sdma_ring_set_wptr - commit the write pointer + * + * @ring: amdgpu ring pointer + * + * Write the wptr back to the hardware (CIK+). + */ +static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1; + + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); +} + +static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *); + +/** + * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine + * + * @ring: amdgpu ring pointer + * @ib: IB object to schedule + * + * Schedule an IB in the DMA ring (CIK). + */ +static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib) +{ + u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; + u32 next_rptr = ring->wptr + 5; + + if (ib->flush_hdp_writefifo) + next_rptr += 6; + + while ((next_rptr & 7) != 4) + next_rptr++; + + next_rptr += 4; + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); + amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); + amdgpu_ring_write(ring, 1); /* number of DWs to follow */ + amdgpu_ring_write(ring, next_rptr); + + if (ib->flush_hdp_writefifo) { + /* flush HDP */ + cik_sdma_hdp_flush_ring_emit(ring); + } + + /* IB packet must end on a 8 DW boundary */ + while ((ring->wptr & 7) != 4) + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); + amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); + amdgpu_ring_write(ring, ib->length_dw); + +} + +/** + * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring + * + * @ring: amdgpu ring pointer + * + * Emit an hdp flush packet on the requested DMA ring. + */ +static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *ring) +{ + u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | + SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ + u32 ref_and_mask; + + if (ring == &ring->adev->sdma[0].ring) + ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; + else + ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; + + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); + amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); + amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); + amdgpu_ring_write(ring, ref_and_mask); /* reference */ + amdgpu_ring_write(ring, ref_and_mask); /* mask */ + amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ +} + +/** + * cik_sdma_ring_emit_fence - emit a fence on the DMA ring + * + * @ring: amdgpu ring pointer + * @fence: amdgpu fence object + * + * Add a DMA fence packet to the ring to write + * the fence seq number and DMA trap packet to generate + * an interrupt if needed (CIK). + */ +static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + bool write64bit) +{ + /* write the fence */ + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + + /* optionally write high bits as well */ + if (write64bit) { + addr += 4; + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(seq)); + } + + /* generate an interrupt */ + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); +} + +/** + * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring + * + * @ring: amdgpu_ring structure holding ring information + * @semaphore: amdgpu semaphore object + * @emit_wait: wait or signal semaphore + * + * Add a DMA semaphore packet to the ring wait on or signal + * other rings (CIK). + */ +static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore, + bool emit_wait) +{ + u64 addr = semaphore->gpu_addr; + u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; + + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); + amdgpu_ring_write(ring, addr & 0xfffffff8); + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); + + return true; +} + +/** + * cik_sdma_gfx_stop - stop the gfx async dma engines + * + * @adev: amdgpu_device pointer + * + * Stop the gfx async dma ring buffers (CIK). + */ +static void cik_sdma_gfx_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *sdma0 = &adev->sdma[0].ring; + struct amdgpu_ring *sdma1 = &adev->sdma[1].ring; + u32 rb_cntl; + int i; + + if ((adev->mman.buffer_funcs_ring == sdma0) || + (adev->mman.buffer_funcs_ring == sdma1)) + amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); + rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; + WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); + WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); + } + sdma0->ready = false; + sdma1->ready = false; +} + +/** + * cik_sdma_rlc_stop - stop the compute async dma engines + * + * @adev: amdgpu_device pointer + * + * Stop the compute async dma queues (CIK). + */ +static void cik_sdma_rlc_stop(struct amdgpu_device *adev) +{ + /* XXX todo */ +} + +/** + * cik_sdma_enable - stop the async dma engines + * + * @adev: amdgpu_device pointer + * @enable: enable/disable the DMA MEs. + * + * Halt or unhalt the async dma engines (CIK). + */ +static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) +{ + u32 me_cntl; + int i; + + if (enable == false) { + cik_sdma_gfx_stop(adev); + cik_sdma_rlc_stop(adev); + } + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); + if (enable) + me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; + else + me_cntl |= SDMA0_F32_CNTL__HALT_MASK; + WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); + } +} + +/** + * cik_sdma_gfx_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the gfx DMA ring buffers and enable them (CIK). + * Returns 0 for success, error for failure. + */ +static int cik_sdma_gfx_resume(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + u32 rb_cntl, ib_cntl; + u32 rb_bufsz; + u32 wb_offset; + int i, j, r; + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + ring = &adev->sdma[i].ring; + wb_offset = (ring->rptr_offs * 4); + + mutex_lock(&adev->srbm_mutex); + for (j = 0; j < 16; j++) { + cik_srbm_select(adev, 0, 0, 0, j); + /* SDMA GFX */ + WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); + WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); + /* XXX SDMA RLC - todo */ + } + cik_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); + WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); + + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = rb_bufsz << 1; +#ifdef __BIG_ENDIAN + rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; +#endif + WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); + + /* set the wb address whether it's enabled or not */ + WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], + upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); + WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], + ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); + + rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; + + WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); + WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); + + ring->wptr = 0; + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); + + /* enable DMA RB */ + WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], + rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); + + ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; +#ifdef __BIG_ENDIAN + ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; +#endif + /* enable DMA IBs */ + WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); + + ring->ready = true; + + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + return r; + } + + if (adev->mman.buffer_funcs_ring == ring) + amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); + } + + return 0; +} + +/** + * cik_sdma_rlc_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the compute DMA queues and enable them (CIK). + * Returns 0 for success, error for failure. + */ +static int cik_sdma_rlc_resume(struct amdgpu_device *adev) +{ + /* XXX todo */ + return 0; +} + +/** + * cik_sdma_load_microcode - load the sDMA ME ucode + * + * @adev: amdgpu_device pointer + * + * Loads the sDMA0/1 ucode. + * Returns 0 for success, -EINVAL if the ucode is not available. + */ +static int cik_sdma_load_microcode(struct amdgpu_device *adev) +{ + const struct sdma_firmware_header_v1_0 *hdr; + const __le32 *fw_data; + u32 fw_size; + int i, j; + + if (!adev->sdma[0].fw || !adev->sdma[1].fw) + return -EINVAL; + + /* halt the MEs */ + cik_sdma_enable(adev, false); + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; + amdgpu_ucode_print_sdma_hdr(&hdr->header); + fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); + fw_data = (const __le32 *) + (adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); + for (j = 0; j < fw_size; j++) + WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); + WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version); + } + + return 0; +} + +/** + * cik_sdma_start - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the DMA engines and enable them (CIK). + * Returns 0 for success, error for failure. + */ +static int cik_sdma_start(struct amdgpu_device *adev) +{ + int r; + + r = cik_sdma_load_microcode(adev); + if (r) + return r; + + /* unhalt the MEs */ + cik_sdma_enable(adev, true); + + /* start the gfx rings and rlc compute queues */ + r = cik_sdma_gfx_resume(adev); + if (r) + return r; + r = cik_sdma_rlc_resume(adev); + if (r) + return r; + + return 0; +} + +/** + * cik_sdma_ring_test_ring - simple async dma engine test + * + * @ring: amdgpu_ring structure holding ring information + * + * Test the DMA engine by writing using it to write an + * value to memory. (CIK). + * Returns 0 for success, error for failure. + */ +static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + unsigned i; + unsigned index; + int r; + u32 tmp; + u64 gpu_addr; + + r = amdgpu_wb_get(adev, &index); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); + return r; + } + + gpu_addr = adev->wb.gpu_addr + (index * 4); + tmp = 0xCAFEDEAD; + adev->wb.wb[index] = cpu_to_le32(tmp); + + r = amdgpu_ring_lock(ring, 5); + if (r) { + DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); + amdgpu_wb_free(adev, index); + return r; + } + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); + amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); + amdgpu_ring_write(ring, 1); /* number of DWs to follow */ + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_unlock_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = le32_to_cpu(adev->wb.wb[index]); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", + ring->idx, tmp); + r = -EINVAL; + } + amdgpu_wb_free(adev, index); + + return r; +} + +/** + * cik_sdma_ring_test_ib - test an IB on the DMA engine + * + * @ring: amdgpu_ring structure holding ring information + * + * Test a simple IB in the DMA ring (CIK). + * Returns 0 on success, error on failure. + */ +static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_ib ib; + unsigned i; + unsigned index; + int r; + u32 tmp = 0; + u64 gpu_addr; + + r = amdgpu_wb_get(adev, &index); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); + return r; + } + + gpu_addr = adev->wb.gpu_addr + (index * 4); + tmp = 0xCAFEDEAD; + adev->wb.wb[index] = cpu_to_le32(tmp); + + r = amdgpu_ib_get(ring, NULL, 256, &ib); + if (r) { + amdgpu_wb_free(adev, index); + DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); + return r; + } + + ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + ib.ptr[1] = lower_32_bits(gpu_addr); + ib.ptr[2] = upper_32_bits(gpu_addr); + ib.ptr[3] = 1; + ib.ptr[4] = 0xDEADBEEF; + ib.length_dw = 5; + + r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); + if (r) { + amdgpu_ib_free(adev, &ib); + amdgpu_wb_free(adev, index); + DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); + return r; + } + r = amdgpu_fence_wait(ib.fence, false); + if (r) { + amdgpu_ib_free(adev, &ib); + amdgpu_wb_free(adev, index); + DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + return r; + } + for (i = 0; i < adev->usec_timeout; i++) { + tmp = le32_to_cpu(adev->wb.wb[index]); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < adev->usec_timeout) { + DRM_INFO("ib test on ring %d succeeded in %u usecs\n", + ib.fence->ring->idx, i); + } else { + DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); + r = -EINVAL; + } + amdgpu_ib_free(adev, &ib); + amdgpu_wb_free(adev, index); + return r; +} + +/** + * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @src: src addr to copy from + * @count: number of page entries to update + * + * Update PTEs by copying them from the GART using sDMA (CIK). + */ +static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, + uint64_t pe, uint64_t src, + unsigned count) +{ + while (count) { + unsigned bytes = count * 8; + if (bytes > 0x1FFFF8) + bytes = 0x1FFFF8; + + ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + ib->ptr[ib->length_dw++] = bytes; + ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ + ib->ptr[ib->length_dw++] = lower_32_bits(src); + ib->ptr[ib->length_dw++] = upper_32_bits(src); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + + pe += bytes; + src += bytes; + count -= bytes / 8; + } +} + +/** + * cik_sdma_vm_write_pages - update PTEs by writing them manually + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: access flags + * + * Update PTEs by writing them manually using sDMA (CIK). + */ +static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, + uint64_t pe, + uint64_t addr, unsigned count, + uint32_t incr, uint32_t flags) +{ + uint64_t value; + unsigned ndw; + + while (count) { + ndw = count * 2; + if (ndw > 0xFFFFE) + ndw = 0xFFFFE; + + /* for non-physically contiguous pages (system) */ + ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + ib->ptr[ib->length_dw++] = pe; + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = ndw; + for (; ndw > 0; ndw -= 2, --count, pe += 8) { + if (flags & AMDGPU_PTE_SYSTEM) { + value = amdgpu_vm_map_gart(ib->ring->adev, addr); + value &= 0xFFFFFFFFFFFFF000ULL; + } else if (flags & AMDGPU_PTE_VALID) { + value = addr; + } else { + value = 0; + } + addr += incr; + value |= flags; + ib->ptr[ib->length_dw++] = value; + ib->ptr[ib->length_dw++] = upper_32_bits(value); + } + } +} + +/** + * cik_sdma_vm_set_pages - update the page tables using sDMA + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: access flags + * + * Update the page tables using sDMA (CIK). + */ +static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, + uint64_t pe, + uint64_t addr, unsigned count, + uint32_t incr, uint32_t flags) +{ + uint64_t value; + unsigned ndw; + + while (count) { + ndw = count; + if (ndw > 0x7FFFF) + ndw = 0x7FFFF; + + if (flags & AMDGPU_PTE_VALID) + value = addr; + else + value = 0; + + /* for physically contiguous pages (vram) */ + ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); + ib->ptr[ib->length_dw++] = pe; /* dst addr */ + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = flags; /* mask */ + ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = value; /* value */ + ib->ptr[ib->length_dw++] = upper_32_bits(value); + ib->ptr[ib->length_dw++] = incr; /* increment size */ + ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = ndw; /* number of entries */ + + pe += ndw * 8; + addr += ndw * incr; + count -= ndw; + } +} + +/** + * cik_sdma_vm_pad_ib - pad the IB to the required number of dw + * + * @ib: indirect buffer to fill with padding + * + */ +static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib) +{ + while (ib->length_dw & 0x7) + ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); +} + +/** + * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA + * + * @ring: amdgpu_ring pointer + * @vm: amdgpu_vm pointer + * + * Update the page table base and flush the VM TLB + * using sDMA (CIK). + */ +static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr) +{ + u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | + SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ + + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); + if (vm_id < 8) { + amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); + } else { + amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); + } + amdgpu_ring_write(ring, pd_addr >> 12); + + /* update SH_MEM_* regs */ + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); + amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); + amdgpu_ring_write(ring, VMID(vm_id)); + + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); + amdgpu_ring_write(ring, mmSH_MEM_BASES); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); + amdgpu_ring_write(ring, mmSH_MEM_CONFIG); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); + amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE); + amdgpu_ring_write(ring, 1); + + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); + amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); + amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); + amdgpu_ring_write(ring, VMID(0)); + + /* flush TLB */ + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); + amdgpu_ring_write(ring, 1 << vm_id); + + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 0); /* reference */ + amdgpu_ring_write(ring, 0); /* mask */ + amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ +} + +static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, + bool enable) +{ + u32 orig, data; + + if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) { + WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); + WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); + } else { + orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); + data |= 0xff000000; + if (data != orig) + WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); + + orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); + data |= 0xff000000; + if (data != orig) + WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); + } +} + +static void cik_enable_sdma_mgls(struct amdgpu_device *adev, + bool enable) +{ + u32 orig, data; + + if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) { + orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); + data |= 0x100; + if (orig != data) + WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); + + orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); + data |= 0x100; + if (orig != data) + WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); + } else { + orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); + data &= ~0x100; + if (orig != data) + WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); + + orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); + data &= ~0x100; + if (orig != data) + WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); + } +} + +static int cik_sdma_early_init(struct amdgpu_device *adev) +{ + cik_sdma_set_ring_funcs(adev); + cik_sdma_set_irq_funcs(adev); + cik_sdma_set_buffer_funcs(adev); + cik_sdma_set_vm_pte_funcs(adev); + + return 0; +} + +static int cik_sdma_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + r = cik_sdma_init_microcode(adev); + if (r) { + DRM_ERROR("Failed to load sdma firmware!\n"); + return r; + } + + /* SDMA trap event */ + r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); + if (r) + return r; + + /* SDMA Privileged inst */ + r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq); + if (r) + return r; + + /* SDMA Privileged inst */ + r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq); + if (r) + return r; + + ring = &adev->sdma[0].ring; + ring->ring_obj = NULL; + + ring = &adev->sdma[1].ring; + ring->ring_obj = NULL; + + ring = &adev->sdma[0].ring; + sprintf(ring->name, "sdma0"); + r = amdgpu_ring_init(adev, ring, 256 * 1024, + SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, + &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0, + AMDGPU_RING_TYPE_SDMA); + if (r) + return r; + + ring = &adev->sdma[1].ring; + sprintf(ring->name, "sdma1"); + r = amdgpu_ring_init(adev, ring, 256 * 1024, + SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, + &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1, + AMDGPU_RING_TYPE_SDMA); + if (r) + return r; + + return r; +} + +static int cik_sdma_sw_fini(struct amdgpu_device *adev) +{ + amdgpu_ring_fini(&adev->sdma[0].ring); + amdgpu_ring_fini(&adev->sdma[1].ring); + + return 0; +} + +static int cik_sdma_hw_init(struct amdgpu_device *adev) +{ + int r; + + r = cik_sdma_start(adev); + if (r) + return r; + + return r; +} + +static int cik_sdma_hw_fini(struct amdgpu_device *adev) +{ + cik_sdma_enable(adev, false); + + return 0; +} + +static int cik_sdma_suspend(struct amdgpu_device *adev) +{ + + return cik_sdma_hw_fini(adev); +} + +static int cik_sdma_resume(struct amdgpu_device *adev) +{ + + return cik_sdma_hw_init(adev); +} + +static bool cik_sdma_is_idle(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmSRBM_STATUS2); + + if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | + SRBM_STATUS2__SDMA1_BUSY_MASK)) + return false; + + return true; +} + +static int cik_sdma_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | + SRBM_STATUS2__SDMA1_BUSY_MASK); + + if (!tmp) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static void cik_sdma_print_status(struct amdgpu_device *adev) +{ + int i, j; + + dev_info(adev->dev, "CIK SDMA registers\n"); + dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", + RREG32(mmSRBM_STATUS2)); + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", + i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); + mutex_lock(&adev->srbm_mutex); + for (j = 0; j < 16; j++) { + cik_srbm_select(adev, 0, 0, 0, j); + dev_info(adev->dev, " VM %d:\n", j); + dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n", + RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); + dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n", + RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); + } + cik_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + } +} + +static int cik_sdma_soft_reset(struct amdgpu_device *adev) +{ + u32 srbm_soft_reset = 0; + u32 tmp = RREG32(mmSRBM_STATUS2); + + if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { + /* sdma0 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); + tmp |= SDMA0_F32_CNTL__HALT_MASK; + WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; + } + if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { + /* sdma1 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); + tmp |= SDMA0_F32_CNTL__HALT_MASK; + WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; + } + + if (srbm_soft_reset) { + cik_sdma_print_status(adev); + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + + cik_sdma_print_status(adev); + } + + return 0; +} + +static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 sdma_cntl; + + switch (type) { + case AMDGPU_SDMA_IRQ_TRAP0: + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); + sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; + WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); + sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; + WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); + break; + default: + break; + } + break; + case AMDGPU_SDMA_IRQ_TRAP1: + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); + sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; + WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); + sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; + WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); + break; + default: + break; + } + break; + default: + break; + } + return 0; +} + +static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + u8 instance_id, queue_id; + + instance_id = (entry->ring_id & 0x3) >> 0; + queue_id = (entry->ring_id & 0xc) >> 2; + DRM_DEBUG("IH: SDMA trap\n"); + switch (instance_id) { + case 0: + switch (queue_id) { + case 0: + amdgpu_fence_process(&adev->sdma[0].ring); + break; + case 1: + /* XXX compute */ + break; + case 2: + /* XXX compute */ + break; + } + break; + case 1: + switch (queue_id) { + case 0: + amdgpu_fence_process(&adev->sdma[1].ring); + break; + case 1: + /* XXX compute */ + break; + case 2: + /* XXX compute */ + break; + } + break; + } + + return 0; +} + +static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal instruction in SDMA command stream\n"); + schedule_work(&adev->reset_work); + return 0; +} + +static int cik_sdma_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + bool gate = false; + + if (state == AMDGPU_CG_STATE_GATE) + gate = true; + + cik_enable_sdma_mgcg(adev, gate); + cik_enable_sdma_mgls(adev, gate); + + return 0; +} + +static int cik_sdma_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs cik_sdma_ip_funcs = { + .early_init = cik_sdma_early_init, + .late_init = NULL, + .sw_init = cik_sdma_sw_init, + .sw_fini = cik_sdma_sw_fini, + .hw_init = cik_sdma_hw_init, + .hw_fini = cik_sdma_hw_fini, + .suspend = cik_sdma_suspend, + .resume = cik_sdma_resume, + .is_idle = cik_sdma_is_idle, + .wait_for_idle = cik_sdma_wait_for_idle, + .soft_reset = cik_sdma_soft_reset, + .print_status = cik_sdma_print_status, + .set_clockgating_state = cik_sdma_set_clockgating_state, + .set_powergating_state = cik_sdma_set_powergating_state, +}; + +/** + * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up + * + * @ring: amdgpu_ring structure holding ring information + * + * Check if the async DMA engine is locked up (CIK). + * Returns true if the engine appears to be locked up, false if not. + */ +static bool cik_sdma_ring_is_lockup(struct amdgpu_ring *ring) +{ + + if (cik_sdma_is_idle(ring->adev)) { + amdgpu_ring_lockup_update(ring); + return false; + } + return amdgpu_ring_test_lockup(ring); +} + +static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { + .get_rptr = cik_sdma_ring_get_rptr, + .get_wptr = cik_sdma_ring_get_wptr, + .set_wptr = cik_sdma_ring_set_wptr, + .parse_cs = NULL, + .emit_ib = cik_sdma_ring_emit_ib, + .emit_fence = cik_sdma_ring_emit_fence, + .emit_semaphore = cik_sdma_ring_emit_semaphore, + .emit_vm_flush = cik_sdma_ring_emit_vm_flush, + .test_ring = cik_sdma_ring_test_ring, + .test_ib = cik_sdma_ring_test_ib, + .is_lockup = cik_sdma_ring_is_lockup, +}; + +static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) +{ + adev->sdma[0].ring.funcs = &cik_sdma_ring_funcs; + adev->sdma[1].ring.funcs = &cik_sdma_ring_funcs; +} + +static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { + .set = cik_sdma_set_trap_irq_state, + .process = cik_sdma_process_trap_irq, +}; + +static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { + .process = cik_sdma_process_illegal_inst_irq, +}; + +static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; + adev->sdma_trap_irq.funcs = &cik_sdma_trap_irq_funcs; + adev->sdma_illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; +} + +/** + * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine + * + * @ring: amdgpu_ring structure holding ring information + * @src_offset: src GPU address + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * + * Copy GPU buffers using the DMA engine (CIK). + * Used by the amdgpu ttm implementation to move pages if + * registered as the asic copy callback. + */ +static void cik_sdma_emit_copy_buffer(struct amdgpu_ring *ring, + uint64_t src_offset, + uint64_t dst_offset, + uint32_t byte_count) +{ + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); + amdgpu_ring_write(ring, byte_count); + amdgpu_ring_write(ring, 0); /* src/dst endian swap */ + amdgpu_ring_write(ring, lower_32_bits(src_offset)); + amdgpu_ring_write(ring, upper_32_bits(src_offset)); + amdgpu_ring_write(ring, lower_32_bits(dst_offset)); + amdgpu_ring_write(ring, upper_32_bits(dst_offset)); +} + +/** + * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine + * + * @ring: amdgpu_ring structure holding ring information + * @src_data: value to write to buffer + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * + * Fill GPU buffers using the DMA engine (CIK). + */ +static void cik_sdma_emit_fill_buffer(struct amdgpu_ring *ring, + uint32_t src_data, + uint64_t dst_offset, + uint32_t byte_count) +{ + amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0)); + amdgpu_ring_write(ring, lower_32_bits(dst_offset)); + amdgpu_ring_write(ring, upper_32_bits(dst_offset)); + amdgpu_ring_write(ring, src_data); + amdgpu_ring_write(ring, byte_count); +} + +static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { + .copy_max_bytes = 0x1fffff, + .copy_num_dw = 7, + .emit_copy_buffer = cik_sdma_emit_copy_buffer, + + .fill_max_bytes = 0x1fffff, + .fill_num_dw = 5, + .emit_fill_buffer = cik_sdma_emit_fill_buffer, +}; + +static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) +{ + if (adev->mman.buffer_funcs == NULL) { + adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; + adev->mman.buffer_funcs_ring = &adev->sdma[0].ring; + } +} + +static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { + .copy_pte = cik_sdma_vm_copy_pte, + .write_pte = cik_sdma_vm_write_pte, + .set_pte_pde = cik_sdma_vm_set_pte_pde, + .pad_ib = cik_sdma_vm_pad_ib, +}; + +static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) +{ + if (adev->vm_manager.vm_pte_funcs == NULL) { + adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; + adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring; + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h new file mode 100644 index 000000000000..42b59960bc53 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __CIK_SDMA_H__ +#define __CIK_SDMA_H__ + +extern const struct amdgpu_ip_funcs cik_sdma_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_ci.h b/drivers/gpu/drm/amd/amdgpu/clearstate_ci.h new file mode 100644 index 000000000000..c3982f9475fb --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/clearstate_ci.h @@ -0,0 +1,944 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +static const unsigned int ci_SECT_CONTEXT_def_1[] = +{ + 0x00000000, // DB_RENDER_CONTROL + 0x00000000, // DB_COUNT_CONTROL + 0x00000000, // DB_DEPTH_VIEW + 0x00000000, // DB_RENDER_OVERRIDE + 0x00000000, // DB_RENDER_OVERRIDE2 + 0x00000000, // DB_HTILE_DATA_BASE + 0, // HOLE + 0, // HOLE + 0x00000000, // DB_DEPTH_BOUNDS_MIN + 0x00000000, // DB_DEPTH_BOUNDS_MAX + 0x00000000, // DB_STENCIL_CLEAR + 0x00000000, // DB_DEPTH_CLEAR + 0x00000000, // PA_SC_SCREEN_SCISSOR_TL + 0x40004000, // PA_SC_SCREEN_SCISSOR_BR + 0, // HOLE + 0x00000000, // DB_DEPTH_INFO + 0x00000000, // DB_Z_INFO + 0x00000000, // DB_STENCIL_INFO + 0x00000000, // DB_Z_READ_BASE + 0x00000000, // DB_STENCIL_READ_BASE + 0x00000000, // DB_Z_WRITE_BASE + 0x00000000, // DB_STENCIL_WRITE_BASE + 0x00000000, // DB_DEPTH_SIZE + 0x00000000, // DB_DEPTH_SLICE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // TA_BC_BASE_ADDR + 0x00000000, // TA_BC_BASE_ADDR_HI + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // COHER_DEST_BASE_HI_0 + 0x00000000, // COHER_DEST_BASE_HI_1 + 0x00000000, // COHER_DEST_BASE_HI_2 + 0x00000000, // COHER_DEST_BASE_HI_3 + 0x00000000, // COHER_DEST_BASE_2 + 0x00000000, // COHER_DEST_BASE_3 + 0x00000000, // PA_SC_WINDOW_OFFSET + 0x80000000, // PA_SC_WINDOW_SCISSOR_TL + 0x40004000, // PA_SC_WINDOW_SCISSOR_BR + 0x0000ffff, // PA_SC_CLIPRECT_RULE + 0x00000000, // PA_SC_CLIPRECT_0_TL + 0x40004000, // PA_SC_CLIPRECT_0_BR + 0x00000000, // PA_SC_CLIPRECT_1_TL + 0x40004000, // PA_SC_CLIPRECT_1_BR + 0x00000000, // PA_SC_CLIPRECT_2_TL + 0x40004000, // PA_SC_CLIPRECT_2_BR + 0x00000000, // PA_SC_CLIPRECT_3_TL + 0x40004000, // PA_SC_CLIPRECT_3_BR + 0xaa99aaaa, // PA_SC_EDGERULE + 0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET + 0xffffffff, // CB_TARGET_MASK + 0xffffffff, // CB_SHADER_MASK + 0x80000000, // PA_SC_GENERIC_SCISSOR_TL + 0x40004000, // PA_SC_GENERIC_SCISSOR_BR + 0x00000000, // COHER_DEST_BASE_0 + 0x00000000, // COHER_DEST_BASE_1 + 0x80000000, // PA_SC_VPORT_SCISSOR_0_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_0_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_1_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_1_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_2_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_2_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_3_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_3_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_4_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_4_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_5_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_5_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_6_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_6_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_7_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_7_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_8_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_8_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_9_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_9_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_10_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_10_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_11_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_11_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_12_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_12_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_13_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_13_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_14_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_14_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_15_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_15_BR + 0x00000000, // PA_SC_VPORT_ZMIN_0 + 0x3f800000, // PA_SC_VPORT_ZMAX_0 + 0x00000000, // PA_SC_VPORT_ZMIN_1 + 0x3f800000, // PA_SC_VPORT_ZMAX_1 + 0x00000000, // PA_SC_VPORT_ZMIN_2 + 0x3f800000, // PA_SC_VPORT_ZMAX_2 + 0x00000000, // PA_SC_VPORT_ZMIN_3 + 0x3f800000, // PA_SC_VPORT_ZMAX_3 + 0x00000000, // PA_SC_VPORT_ZMIN_4 + 0x3f800000, // PA_SC_VPORT_ZMAX_4 + 0x00000000, // PA_SC_VPORT_ZMIN_5 + 0x3f800000, // PA_SC_VPORT_ZMAX_5 + 0x00000000, // PA_SC_VPORT_ZMIN_6 + 0x3f800000, // PA_SC_VPORT_ZMAX_6 + 0x00000000, // PA_SC_VPORT_ZMIN_7 + 0x3f800000, // PA_SC_VPORT_ZMAX_7 + 0x00000000, // PA_SC_VPORT_ZMIN_8 + 0x3f800000, // PA_SC_VPORT_ZMAX_8 + 0x00000000, // PA_SC_VPORT_ZMIN_9 + 0x3f800000, // PA_SC_VPORT_ZMAX_9 + 0x00000000, // PA_SC_VPORT_ZMIN_10 + 0x3f800000, // PA_SC_VPORT_ZMAX_10 + 0x00000000, // PA_SC_VPORT_ZMIN_11 + 0x3f800000, // PA_SC_VPORT_ZMAX_11 + 0x00000000, // PA_SC_VPORT_ZMIN_12 + 0x3f800000, // PA_SC_VPORT_ZMAX_12 + 0x00000000, // PA_SC_VPORT_ZMIN_13 + 0x3f800000, // PA_SC_VPORT_ZMAX_13 + 0x00000000, // PA_SC_VPORT_ZMIN_14 + 0x3f800000, // PA_SC_VPORT_ZMAX_14 + 0x00000000, // PA_SC_VPORT_ZMIN_15 + 0x3f800000, // PA_SC_VPORT_ZMAX_15 +}; +static const unsigned int ci_SECT_CONTEXT_def_2[] = +{ + 0x00000000, // PA_SC_SCREEN_EXTENT_CONTROL + 0, // HOLE + 0x00000000, // CP_PERFMON_CNTX_CNTL + 0x00000000, // CP_RINGID + 0x00000000, // CP_VMID + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0xffffffff, // VGT_MAX_VTX_INDX + 0x00000000, // VGT_MIN_VTX_INDX + 0x00000000, // VGT_INDX_OFFSET + 0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX + 0, // HOLE + 0x00000000, // CB_BLEND_RED + 0x00000000, // CB_BLEND_GREEN + 0x00000000, // CB_BLEND_BLUE + 0x00000000, // CB_BLEND_ALPHA + 0, // HOLE + 0, // HOLE + 0x00000000, // DB_STENCIL_CONTROL + 0x00000000, // DB_STENCILREFMASK + 0x00000000, // DB_STENCILREFMASK_BF + 0, // HOLE + 0x00000000, // PA_CL_VPORT_XSCALE + 0x00000000, // PA_CL_VPORT_XOFFSET + 0x00000000, // PA_CL_VPORT_YSCALE + 0x00000000, // PA_CL_VPORT_YOFFSET + 0x00000000, // PA_CL_VPORT_ZSCALE + 0x00000000, // PA_CL_VPORT_ZOFFSET + 0x00000000, // PA_CL_VPORT_XSCALE_1 + 0x00000000, // PA_CL_VPORT_XOFFSET_1 + 0x00000000, // PA_CL_VPORT_YSCALE_1 + 0x00000000, // PA_CL_VPORT_YOFFSET_1 + 0x00000000, // PA_CL_VPORT_ZSCALE_1 + 0x00000000, // PA_CL_VPORT_ZOFFSET_1 + 0x00000000, // PA_CL_VPORT_XSCALE_2 + 0x00000000, // PA_CL_VPORT_XOFFSET_2 + 0x00000000, // PA_CL_VPORT_YSCALE_2 + 0x00000000, // PA_CL_VPORT_YOFFSET_2 + 0x00000000, // PA_CL_VPORT_ZSCALE_2 + 0x00000000, // PA_CL_VPORT_ZOFFSET_2 + 0x00000000, // PA_CL_VPORT_XSCALE_3 + 0x00000000, // PA_CL_VPORT_XOFFSET_3 + 0x00000000, // PA_CL_VPORT_YSCALE_3 + 0x00000000, // PA_CL_VPORT_YOFFSET_3 + 0x00000000, // PA_CL_VPORT_ZSCALE_3 + 0x00000000, // PA_CL_VPORT_ZOFFSET_3 + 0x00000000, // PA_CL_VPORT_XSCALE_4 + 0x00000000, // PA_CL_VPORT_XOFFSET_4 + 0x00000000, // PA_CL_VPORT_YSCALE_4 + 0x00000000, // PA_CL_VPORT_YOFFSET_4 + 0x00000000, // PA_CL_VPORT_ZSCALE_4 + 0x00000000, // PA_CL_VPORT_ZOFFSET_4 + 0x00000000, // PA_CL_VPORT_XSCALE_5 + 0x00000000, // PA_CL_VPORT_XOFFSET_5 + 0x00000000, // PA_CL_VPORT_YSCALE_5 + 0x00000000, // PA_CL_VPORT_YOFFSET_5 + 0x00000000, // PA_CL_VPORT_ZSCALE_5 + 0x00000000, // PA_CL_VPORT_ZOFFSET_5 + 0x00000000, // PA_CL_VPORT_XSCALE_6 + 0x00000000, // PA_CL_VPORT_XOFFSET_6 + 0x00000000, // PA_CL_VPORT_YSCALE_6 + 0x00000000, // PA_CL_VPORT_YOFFSET_6 + 0x00000000, // PA_CL_VPORT_ZSCALE_6 + 0x00000000, // PA_CL_VPORT_ZOFFSET_6 + 0x00000000, // PA_CL_VPORT_XSCALE_7 + 0x00000000, // PA_CL_VPORT_XOFFSET_7 + 0x00000000, // PA_CL_VPORT_YSCALE_7 + 0x00000000, // PA_CL_VPORT_YOFFSET_7 + 0x00000000, // PA_CL_VPORT_ZSCALE_7 + 0x00000000, // PA_CL_VPORT_ZOFFSET_7 + 0x00000000, // PA_CL_VPORT_XSCALE_8 + 0x00000000, // PA_CL_VPORT_XOFFSET_8 + 0x00000000, // PA_CL_VPORT_YSCALE_8 + 0x00000000, // PA_CL_VPORT_YOFFSET_8 + 0x00000000, // PA_CL_VPORT_ZSCALE_8 + 0x00000000, // PA_CL_VPORT_ZOFFSET_8 + 0x00000000, // PA_CL_VPORT_XSCALE_9 + 0x00000000, // PA_CL_VPORT_XOFFSET_9 + 0x00000000, // PA_CL_VPORT_YSCALE_9 + 0x00000000, // PA_CL_VPORT_YOFFSET_9 + 0x00000000, // PA_CL_VPORT_ZSCALE_9 + 0x00000000, // PA_CL_VPORT_ZOFFSET_9 + 0x00000000, // PA_CL_VPORT_XSCALE_10 + 0x00000000, // PA_CL_VPORT_XOFFSET_10 + 0x00000000, // PA_CL_VPORT_YSCALE_10 + 0x00000000, // PA_CL_VPORT_YOFFSET_10 + 0x00000000, // PA_CL_VPORT_ZSCALE_10 + 0x00000000, // PA_CL_VPORT_ZOFFSET_10 + 0x00000000, // PA_CL_VPORT_XSCALE_11 + 0x00000000, // PA_CL_VPORT_XOFFSET_11 + 0x00000000, // PA_CL_VPORT_YSCALE_11 + 0x00000000, // PA_CL_VPORT_YOFFSET_11 + 0x00000000, // PA_CL_VPORT_ZSCALE_11 + 0x00000000, // PA_CL_VPORT_ZOFFSET_11 + 0x00000000, // PA_CL_VPORT_XSCALE_12 + 0x00000000, // PA_CL_VPORT_XOFFSET_12 + 0x00000000, // PA_CL_VPORT_YSCALE_12 + 0x00000000, // PA_CL_VPORT_YOFFSET_12 + 0x00000000, // PA_CL_VPORT_ZSCALE_12 + 0x00000000, // PA_CL_VPORT_ZOFFSET_12 + 0x00000000, // PA_CL_VPORT_XSCALE_13 + 0x00000000, // PA_CL_VPORT_XOFFSET_13 + 0x00000000, // PA_CL_VPORT_YSCALE_13 + 0x00000000, // PA_CL_VPORT_YOFFSET_13 + 0x00000000, // PA_CL_VPORT_ZSCALE_13 + 0x00000000, // PA_CL_VPORT_ZOFFSET_13 + 0x00000000, // PA_CL_VPORT_XSCALE_14 + 0x00000000, // PA_CL_VPORT_XOFFSET_14 + 0x00000000, // PA_CL_VPORT_YSCALE_14 + 0x00000000, // PA_CL_VPORT_YOFFSET_14 + 0x00000000, // PA_CL_VPORT_ZSCALE_14 + 0x00000000, // PA_CL_VPORT_ZOFFSET_14 + 0x00000000, // PA_CL_VPORT_XSCALE_15 + 0x00000000, // PA_CL_VPORT_XOFFSET_15 + 0x00000000, // PA_CL_VPORT_YSCALE_15 + 0x00000000, // PA_CL_VPORT_YOFFSET_15 + 0x00000000, // PA_CL_VPORT_ZSCALE_15 + 0x00000000, // PA_CL_VPORT_ZOFFSET_15 + 0x00000000, // PA_CL_UCP_0_X + 0x00000000, // PA_CL_UCP_0_Y + 0x00000000, // PA_CL_UCP_0_Z + 0x00000000, // PA_CL_UCP_0_W + 0x00000000, // PA_CL_UCP_1_X + 0x00000000, // PA_CL_UCP_1_Y + 0x00000000, // PA_CL_UCP_1_Z + 0x00000000, // PA_CL_UCP_1_W + 0x00000000, // PA_CL_UCP_2_X + 0x00000000, // PA_CL_UCP_2_Y + 0x00000000, // PA_CL_UCP_2_Z + 0x00000000, // PA_CL_UCP_2_W + 0x00000000, // PA_CL_UCP_3_X + 0x00000000, // PA_CL_UCP_3_Y + 0x00000000, // PA_CL_UCP_3_Z + 0x00000000, // PA_CL_UCP_3_W + 0x00000000, // PA_CL_UCP_4_X + 0x00000000, // PA_CL_UCP_4_Y + 0x00000000, // PA_CL_UCP_4_Z + 0x00000000, // PA_CL_UCP_4_W + 0x00000000, // PA_CL_UCP_5_X + 0x00000000, // PA_CL_UCP_5_Y + 0x00000000, // PA_CL_UCP_5_Z + 0x00000000, // PA_CL_UCP_5_W + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // SPI_PS_INPUT_CNTL_0 + 0x00000000, // SPI_PS_INPUT_CNTL_1 + 0x00000000, // SPI_PS_INPUT_CNTL_2 + 0x00000000, // SPI_PS_INPUT_CNTL_3 + 0x00000000, // SPI_PS_INPUT_CNTL_4 + 0x00000000, // SPI_PS_INPUT_CNTL_5 + 0x00000000, // SPI_PS_INPUT_CNTL_6 + 0x00000000, // SPI_PS_INPUT_CNTL_7 + 0x00000000, // SPI_PS_INPUT_CNTL_8 + 0x00000000, // SPI_PS_INPUT_CNTL_9 + 0x00000000, // SPI_PS_INPUT_CNTL_10 + 0x00000000, // SPI_PS_INPUT_CNTL_11 + 0x00000000, // SPI_PS_INPUT_CNTL_12 + 0x00000000, // SPI_PS_INPUT_CNTL_13 + 0x00000000, // SPI_PS_INPUT_CNTL_14 + 0x00000000, // SPI_PS_INPUT_CNTL_15 + 0x00000000, // SPI_PS_INPUT_CNTL_16 + 0x00000000, // SPI_PS_INPUT_CNTL_17 + 0x00000000, // SPI_PS_INPUT_CNTL_18 + 0x00000000, // SPI_PS_INPUT_CNTL_19 + 0x00000000, // SPI_PS_INPUT_CNTL_20 + 0x00000000, // SPI_PS_INPUT_CNTL_21 + 0x00000000, // SPI_PS_INPUT_CNTL_22 + 0x00000000, // SPI_PS_INPUT_CNTL_23 + 0x00000000, // SPI_PS_INPUT_CNTL_24 + 0x00000000, // SPI_PS_INPUT_CNTL_25 + 0x00000000, // SPI_PS_INPUT_CNTL_26 + 0x00000000, // SPI_PS_INPUT_CNTL_27 + 0x00000000, // SPI_PS_INPUT_CNTL_28 + 0x00000000, // SPI_PS_INPUT_CNTL_29 + 0x00000000, // SPI_PS_INPUT_CNTL_30 + 0x00000000, // SPI_PS_INPUT_CNTL_31 + 0x00000000, // SPI_VS_OUT_CONFIG + 0, // HOLE + 0x00000000, // SPI_PS_INPUT_ENA + 0x00000000, // SPI_PS_INPUT_ADDR + 0x00000000, // SPI_INTERP_CONTROL_0 + 0x00000002, // SPI_PS_IN_CONTROL + 0, // HOLE + 0x00000000, // SPI_BARYC_CNTL + 0, // HOLE + 0x00000000, // SPI_TMPRING_SIZE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // SPI_SHADER_POS_FORMAT + 0x00000000, // SPI_SHADER_Z_FORMAT + 0x00000000, // SPI_SHADER_COL_FORMAT + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // CB_BLEND0_CONTROL + 0x00000000, // CB_BLEND1_CONTROL + 0x00000000, // CB_BLEND2_CONTROL + 0x00000000, // CB_BLEND3_CONTROL + 0x00000000, // CB_BLEND4_CONTROL + 0x00000000, // CB_BLEND5_CONTROL + 0x00000000, // CB_BLEND6_CONTROL + 0x00000000, // CB_BLEND7_CONTROL +}; +static const unsigned int ci_SECT_CONTEXT_def_3[] = +{ + 0x00000000, // PA_CL_POINT_X_RAD + 0x00000000, // PA_CL_POINT_Y_RAD + 0x00000000, // PA_CL_POINT_SIZE + 0x00000000, // PA_CL_POINT_CULL_RAD + 0x00000000, // VGT_DMA_BASE_HI + 0x00000000, // VGT_DMA_BASE +}; +static const unsigned int ci_SECT_CONTEXT_def_4[] = +{ + 0x00000000, // DB_DEPTH_CONTROL + 0x00000000, // DB_EQAA + 0x00000000, // CB_COLOR_CONTROL + 0x00000000, // DB_SHADER_CONTROL + 0x00090000, // PA_CL_CLIP_CNTL + 0x00000004, // PA_SU_SC_MODE_CNTL + 0x00000000, // PA_CL_VTE_CNTL + 0x00000000, // PA_CL_VS_OUT_CNTL + 0x00000000, // PA_CL_NANINF_CNTL + 0x00000000, // PA_SU_LINE_STIPPLE_CNTL + 0x00000000, // PA_SU_LINE_STIPPLE_SCALE + 0x00000000, // PA_SU_PRIM_FILTER_CNTL + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // PA_SU_POINT_SIZE + 0x00000000, // PA_SU_POINT_MINMAX + 0x00000000, // PA_SU_LINE_CNTL + 0x00000000, // PA_SC_LINE_STIPPLE + 0x00000000, // VGT_OUTPUT_PATH_CNTL + 0x00000000, // VGT_HOS_CNTL + 0x00000000, // VGT_HOS_MAX_TESS_LEVEL + 0x00000000, // VGT_HOS_MIN_TESS_LEVEL + 0x00000000, // VGT_HOS_REUSE_DEPTH + 0x00000000, // VGT_GROUP_PRIM_TYPE + 0x00000000, // VGT_GROUP_FIRST_DECR + 0x00000000, // VGT_GROUP_DECR + 0x00000000, // VGT_GROUP_VECT_0_CNTL + 0x00000000, // VGT_GROUP_VECT_1_CNTL + 0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL + 0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL + 0x00000000, // VGT_GS_MODE + 0x00000000, // VGT_GS_ONCHIP_CNTL + 0x00000000, // PA_SC_MODE_CNTL_0 + 0x00000000, // PA_SC_MODE_CNTL_1 + 0x00000000, // VGT_ENHANCE + 0x00000100, // VGT_GS_PER_ES + 0x00000080, // VGT_ES_PER_GS + 0x00000002, // VGT_GS_PER_VS + 0x00000000, // VGT_GSVS_RING_OFFSET_1 + 0x00000000, // VGT_GSVS_RING_OFFSET_2 + 0x00000000, // VGT_GSVS_RING_OFFSET_3 + 0x00000000, // VGT_GS_OUT_PRIM_TYPE + 0x00000000, // IA_ENHANCE +}; +static const unsigned int ci_SECT_CONTEXT_def_5[] = +{ + 0x00000000, // WD_ENHANCE + 0x00000000, // VGT_PRIMITIVEID_EN +}; +static const unsigned int ci_SECT_CONTEXT_def_6[] = +{ + 0x00000000, // VGT_PRIMITIVEID_RESET +}; +static const unsigned int ci_SECT_CONTEXT_def_7[] = +{ + 0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN + 0, // HOLE + 0, // HOLE + 0x00000000, // VGT_INSTANCE_STEP_RATE_0 + 0x00000000, // VGT_INSTANCE_STEP_RATE_1 + 0x000000ff, // IA_MULTI_VGT_PARAM + 0x00000000, // VGT_ESGS_RING_ITEMSIZE + 0x00000000, // VGT_GSVS_RING_ITEMSIZE + 0x00000000, // VGT_REUSE_OFF + 0x00000000, // VGT_VTX_CNT_EN + 0x00000000, // DB_HTILE_SURFACE + 0x00000000, // DB_SRESULTS_COMPARE_STATE0 + 0x00000000, // DB_SRESULTS_COMPARE_STATE1 + 0x00000000, // DB_PRELOAD_CONTROL + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_0 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0 + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_1 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1 + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_2 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2 + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_3 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3 + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET + 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE + 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE + 0, // HOLE + 0x00000000, // VGT_GS_MAX_VERT_OUT + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // VGT_SHADER_STAGES_EN + 0x00000000, // VGT_LS_HS_CONFIG + 0x00000000, // VGT_GS_VERT_ITEMSIZE + 0x00000000, // VGT_GS_VERT_ITEMSIZE_1 + 0x00000000, // VGT_GS_VERT_ITEMSIZE_2 + 0x00000000, // VGT_GS_VERT_ITEMSIZE_3 + 0x00000000, // VGT_TF_PARAM + 0x00000000, // DB_ALPHA_TO_MASK + 0, // HOLE + 0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL + 0x00000000, // PA_SU_POLY_OFFSET_CLAMP + 0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE + 0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET + 0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE + 0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET + 0x00000000, // VGT_GS_INSTANCE_CNT + 0x00000000, // VGT_STRMOUT_CONFIG + 0x00000000, // VGT_STRMOUT_BUFFER_CONFIG + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // PA_SC_CENTROID_PRIORITY_0 + 0x00000000, // PA_SC_CENTROID_PRIORITY_1 + 0x00001000, // PA_SC_LINE_CNTL + 0x00000000, // PA_SC_AA_CONFIG + 0x00000005, // PA_SU_VTX_CNTL + 0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ + 0x3f800000, // PA_CL_GB_VERT_DISC_ADJ + 0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ + 0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 + 0xffffffff, // PA_SC_AA_MASK_X0Y0_X1Y0 + 0xffffffff, // PA_SC_AA_MASK_X0Y1_X1Y1 + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x0000000e, // VGT_VERTEX_REUSE_BLOCK_CNTL + 0x00000010, // VGT_OUT_DEALLOC_CNTL + 0x00000000, // CB_COLOR0_BASE + 0x00000000, // CB_COLOR0_PITCH + 0x00000000, // CB_COLOR0_SLICE + 0x00000000, // CB_COLOR0_VIEW + 0x00000000, // CB_COLOR0_INFO + 0x00000000, // CB_COLOR0_ATTRIB + 0, // HOLE + 0x00000000, // CB_COLOR0_CMASK + 0x00000000, // CB_COLOR0_CMASK_SLICE + 0x00000000, // CB_COLOR0_FMASK + 0x00000000, // CB_COLOR0_FMASK_SLICE + 0x00000000, // CB_COLOR0_CLEAR_WORD0 + 0x00000000, // CB_COLOR0_CLEAR_WORD1 + 0, // HOLE + 0, // HOLE + 0x00000000, // CB_COLOR1_BASE + 0x00000000, // CB_COLOR1_PITCH + 0x00000000, // CB_COLOR1_SLICE + 0x00000000, // CB_COLOR1_VIEW + 0x00000000, // CB_COLOR1_INFO + 0x00000000, // CB_COLOR1_ATTRIB + 0, // HOLE + 0x00000000, // CB_COLOR1_CMASK + 0x00000000, // CB_COLOR1_CMASK_SLICE + 0x00000000, // CB_COLOR1_FMASK + 0x00000000, // CB_COLOR1_FMASK_SLICE + 0x00000000, // CB_COLOR1_CLEAR_WORD0 + 0x00000000, // CB_COLOR1_CLEAR_WORD1 + 0, // HOLE + 0, // HOLE + 0x00000000, // CB_COLOR2_BASE + 0x00000000, // CB_COLOR2_PITCH + 0x00000000, // CB_COLOR2_SLICE + 0x00000000, // CB_COLOR2_VIEW + 0x00000000, // CB_COLOR2_INFO + 0x00000000, // CB_COLOR2_ATTRIB + 0, // HOLE + 0x00000000, // CB_COLOR2_CMASK + 0x00000000, // CB_COLOR2_CMASK_SLICE + 0x00000000, // CB_COLOR2_FMASK + 0x00000000, // CB_COLOR2_FMASK_SLICE + 0x00000000, // CB_COLOR2_CLEAR_WORD0 + 0x00000000, // CB_COLOR2_CLEAR_WORD1 + 0, // HOLE + 0, // HOLE + 0x00000000, // CB_COLOR3_BASE + 0x00000000, // CB_COLOR3_PITCH + 0x00000000, // CB_COLOR3_SLICE + 0x00000000, // CB_COLOR3_VIEW + 0x00000000, // CB_COLOR3_INFO + 0x00000000, // CB_COLOR3_ATTRIB + 0, // HOLE + 0x00000000, // CB_COLOR3_CMASK + 0x00000000, // CB_COLOR3_CMASK_SLICE + 0x00000000, // CB_COLOR3_FMASK + 0x00000000, // CB_COLOR3_FMASK_SLICE + 0x00000000, // CB_COLOR3_CLEAR_WORD0 + 0x00000000, // CB_COLOR3_CLEAR_WORD1 + 0, // HOLE + 0, // HOLE + 0x00000000, // CB_COLOR4_BASE + 0x00000000, // CB_COLOR4_PITCH + 0x00000000, // CB_COLOR4_SLICE + 0x00000000, // CB_COLOR4_VIEW + 0x00000000, // CB_COLOR4_INFO + 0x00000000, // CB_COLOR4_ATTRIB + 0, // HOLE + 0x00000000, // CB_COLOR4_CMASK + 0x00000000, // CB_COLOR4_CMASK_SLICE + 0x00000000, // CB_COLOR4_FMASK + 0x00000000, // CB_COLOR4_FMASK_SLICE + 0x00000000, // CB_COLOR4_CLEAR_WORD0 + 0x00000000, // CB_COLOR4_CLEAR_WORD1 + 0, // HOLE + 0, // HOLE + 0x00000000, // CB_COLOR5_BASE + 0x00000000, // CB_COLOR5_PITCH + 0x00000000, // CB_COLOR5_SLICE + 0x00000000, // CB_COLOR5_VIEW + 0x00000000, // CB_COLOR5_INFO + 0x00000000, // CB_COLOR5_ATTRIB + 0, // HOLE + 0x00000000, // CB_COLOR5_CMASK + 0x00000000, // CB_COLOR5_CMASK_SLICE + 0x00000000, // CB_COLOR5_FMASK + 0x00000000, // CB_COLOR5_FMASK_SLICE + 0x00000000, // CB_COLOR5_CLEAR_WORD0 + 0x00000000, // CB_COLOR5_CLEAR_WORD1 + 0, // HOLE + 0, // HOLE + 0x00000000, // CB_COLOR6_BASE + 0x00000000, // CB_COLOR6_PITCH + 0x00000000, // CB_COLOR6_SLICE + 0x00000000, // CB_COLOR6_VIEW + 0x00000000, // CB_COLOR6_INFO + 0x00000000, // CB_COLOR6_ATTRIB + 0, // HOLE + 0x00000000, // CB_COLOR6_CMASK + 0x00000000, // CB_COLOR6_CMASK_SLICE + 0x00000000, // CB_COLOR6_FMASK + 0x00000000, // CB_COLOR6_FMASK_SLICE + 0x00000000, // CB_COLOR6_CLEAR_WORD0 + 0x00000000, // CB_COLOR6_CLEAR_WORD1 + 0, // HOLE + 0, // HOLE + 0x00000000, // CB_COLOR7_BASE + 0x00000000, // CB_COLOR7_PITCH + 0x00000000, // CB_COLOR7_SLICE + 0x00000000, // CB_COLOR7_VIEW + 0x00000000, // CB_COLOR7_INFO + 0x00000000, // CB_COLOR7_ATTRIB + 0, // HOLE + 0x00000000, // CB_COLOR7_CMASK + 0x00000000, // CB_COLOR7_CMASK_SLICE + 0x00000000, // CB_COLOR7_FMASK + 0x00000000, // CB_COLOR7_FMASK_SLICE + 0x00000000, // CB_COLOR7_CLEAR_WORD0 + 0x00000000, // CB_COLOR7_CLEAR_WORD1 +}; +static const struct cs_extent_def ci_SECT_CONTEXT_defs[] = +{ + {ci_SECT_CONTEXT_def_1, 0x0000a000, 212 }, + {ci_SECT_CONTEXT_def_2, 0x0000a0d6, 274 }, + {ci_SECT_CONTEXT_def_3, 0x0000a1f5, 6 }, + {ci_SECT_CONTEXT_def_4, 0x0000a200, 157 }, + {ci_SECT_CONTEXT_def_5, 0x0000a2a0, 2 }, + {ci_SECT_CONTEXT_def_6, 0x0000a2a3, 1 }, + {ci_SECT_CONTEXT_def_7, 0x0000a2a5, 233 }, + { 0, 0, 0 } +}; +static const struct cs_section_def ci_cs_data[] = { + { ci_SECT_CONTEXT_defs, SECT_CONTEXT }, + { 0, SECT_NONE } +}; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c new file mode 100644 index 000000000000..c1bc6935c88e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -0,0 +1,3830 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_pm.h" +#include "amdgpu_i2c.h" +#include "cikd.h" +#include "atom.h" +#include "amdgpu_atombios.h" +#include "atombios_crtc.h" +#include "atombios_encoders.h" +#include "amdgpu_pll.h" +#include "amdgpu_connectors.h" + +#include "dce/dce_8_0_d.h" +#include "dce/dce_8_0_sh_mask.h" + +#include "gca/gfx_7_2_enum.h" + +#include "gmc/gmc_7_1_d.h" +#include "gmc/gmc_7_1_sh_mask.h" + +#include "oss/oss_2_0_d.h" +#include "oss/oss_2_0_sh_mask.h" + +static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev); +static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev); + +static const u32 crtc_offsets[6] = +{ + CRTC0_REGISTER_OFFSET, + CRTC1_REGISTER_OFFSET, + CRTC2_REGISTER_OFFSET, + CRTC3_REGISTER_OFFSET, + CRTC4_REGISTER_OFFSET, + CRTC5_REGISTER_OFFSET +}; + +static const uint32_t dig_offsets[] = { + CRTC0_REGISTER_OFFSET, + CRTC1_REGISTER_OFFSET, + CRTC2_REGISTER_OFFSET, + CRTC3_REGISTER_OFFSET, + CRTC4_REGISTER_OFFSET, + CRTC5_REGISTER_OFFSET, + (0x13830 - 0x7030) >> 2, +}; + +static const struct { + uint32_t reg; + uint32_t vblank; + uint32_t vline; + uint32_t hpd; + +} interrupt_status_offsets[6] = { { + .reg = mmDISP_INTERRUPT_STATUS, + .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK +} }; + +static const uint32_t hpd_int_control_offsets[6] = { + mmDC_HPD1_INT_CONTROL, + mmDC_HPD2_INT_CONTROL, + mmDC_HPD3_INT_CONTROL, + mmDC_HPD4_INT_CONTROL, + mmDC_HPD5_INT_CONTROL, + mmDC_HPD6_INT_CONTROL, +}; + +static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev, + u32 block_offset, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); + r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); + spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + + return r; +} + +static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev, + u32 block_offset, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); + spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); +} + +static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc) +{ + if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & + CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) + return true; + else + return false; +} + +static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc) +{ + u32 pos1, pos2; + + pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); + pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); + + if (pos1 != pos2) + return true; + else + return false; +} + +/** + * dce_v8_0_vblank_wait - vblank wait asic callback. + * + * @adev: amdgpu_device pointer + * @crtc: crtc to wait for vblank on + * + * Wait for vblank on the requested crtc (evergreen+). + */ +static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc) +{ + unsigned i = 0; + + if (crtc >= adev->mode_info.num_crtc) + return; + + if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) + return; + + /* depending on when we hit vblank, we may be close to active; if so, + * wait for another frame. + */ + while (dce_v8_0_is_in_vblank(adev, crtc)) { + if (i++ % 100 == 0) { + if (!dce_v8_0_is_counter_moving(adev, crtc)) + break; + } + } + + while (!dce_v8_0_is_in_vblank(adev, crtc)) { + if (i++ % 100 == 0) { + if (!dce_v8_0_is_counter_moving(adev, crtc)) + break; + } + } +} + +static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) +{ + if (crtc >= adev->mode_info.num_crtc) + return 0; + else + return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); +} + +/** + * dce_v8_0_page_flip - pageflip callback. + * + * @adev: amdgpu_device pointer + * @crtc_id: crtc to cleanup pageflip on + * @crtc_base: new address of the crtc (GPU MC address) + * + * Does the actual pageflip (evergreen+). + * During vblank we take the crtc lock and wait for the update_pending + * bit to go high, when it does, we release the lock, and allow the + * double buffered update to take place. + * Returns the current update pending status. + */ +static void dce_v8_0_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base) +{ + struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); + int i; + + /* Lock the graphics update lock */ + tmp |= GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK; + WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); + + /* update the scanout addresses */ + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(crtc_base)); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32)crtc_base); + + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(crtc_base)); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32)crtc_base); + + /* Wait for update_pending to go high. */ + for (i = 0; i < adev->usec_timeout; i++) { + if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & + GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) + break; + udelay(1); + } + DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); + + /* Unlock the lock, so double-buffering can take place inside vblank */ + tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK; + WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); +} + +static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, + u32 *vbl, u32 *position) +{ + if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) + return -EINVAL; + + *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); + *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); + + return 0; +} + +/** + * dce_v8_0_hpd_sense - hpd sense callback. + * + * @adev: amdgpu_device pointer + * @hpd: hpd (hotplug detect) pin + * + * Checks if a digital monitor is connected (evergreen+). + * Returns true if connected, false if not connected. + */ +static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + bool connected = false; + + switch (hpd) { + case AMDGPU_HPD_1: + if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) + connected = true; + break; + case AMDGPU_HPD_2: + if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK) + connected = true; + break; + case AMDGPU_HPD_3: + if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK) + connected = true; + break; + case AMDGPU_HPD_4: + if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK) + connected = true; + break; + case AMDGPU_HPD_5: + if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK) + connected = true; + break; + case AMDGPU_HPD_6: + if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK) + connected = true; + break; + default: + break; + } + + return connected; +} + +/** + * dce_v8_0_hpd_set_polarity - hpd set polarity callback. + * + * @adev: amdgpu_device pointer + * @hpd: hpd (hotplug detect) pin + * + * Set the polarity of the hpd pin (evergreen+). + */ +static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + u32 tmp; + bool connected = dce_v8_0_hpd_sense(adev, hpd); + + switch (hpd) { + case AMDGPU_HPD_1: + tmp = RREG32(mmDC_HPD1_INT_CONTROL); + if (connected) + tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; + else + tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; + WREG32(mmDC_HPD1_INT_CONTROL, tmp); + break; + case AMDGPU_HPD_2: + tmp = RREG32(mmDC_HPD2_INT_CONTROL); + if (connected) + tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; + else + tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; + WREG32(mmDC_HPD2_INT_CONTROL, tmp); + break; + case AMDGPU_HPD_3: + tmp = RREG32(mmDC_HPD3_INT_CONTROL); + if (connected) + tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; + else + tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; + WREG32(mmDC_HPD3_INT_CONTROL, tmp); + break; + case AMDGPU_HPD_4: + tmp = RREG32(mmDC_HPD4_INT_CONTROL); + if (connected) + tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; + else + tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; + WREG32(mmDC_HPD4_INT_CONTROL, tmp); + break; + case AMDGPU_HPD_5: + tmp = RREG32(mmDC_HPD5_INT_CONTROL); + if (connected) + tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; + else + tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; + WREG32(mmDC_HPD5_INT_CONTROL, tmp); + break; + case AMDGPU_HPD_6: + tmp = RREG32(mmDC_HPD6_INT_CONTROL); + if (connected) + tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; + else + tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; + WREG32(mmDC_HPD6_INT_CONTROL, tmp); + break; + default: + break; + } +} + +/** + * dce_v8_0_hpd_init - hpd setup callback. + * + * @adev: amdgpu_device pointer + * + * Setup the hpd pins used by the card (evergreen+). + * Enable the pin, set the polarity, and enable the hpd interrupts. + */ +static void dce_v8_0_hpd_init(struct amdgpu_device *adev) +{ + struct drm_device *dev = adev->ddev; + struct drm_connector *connector; + u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) | + (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) | + DC_HPD1_CONTROL__DC_HPD1_EN_MASK; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || + connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { + /* don't try to enable hpd on eDP or LVDS avoid breaking the + * aux dp channel on imac and help (but not completely fix) + * https://bugzilla.redhat.com/show_bug.cgi?id=726143 + * also avoid interrupt storms during dpms. + */ + continue; + } + switch (amdgpu_connector->hpd.hpd) { + case AMDGPU_HPD_1: + WREG32(mmDC_HPD1_CONTROL, tmp); + break; + case AMDGPU_HPD_2: + WREG32(mmDC_HPD2_CONTROL, tmp); + break; + case AMDGPU_HPD_3: + WREG32(mmDC_HPD3_CONTROL, tmp); + break; + case AMDGPU_HPD_4: + WREG32(mmDC_HPD4_CONTROL, tmp); + break; + case AMDGPU_HPD_5: + WREG32(mmDC_HPD5_CONTROL, tmp); + break; + case AMDGPU_HPD_6: + WREG32(mmDC_HPD6_CONTROL, tmp); + break; + default: + break; + } + dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); + amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); + } +} + +/** + * dce_v8_0_hpd_fini - hpd tear down callback. + * + * @adev: amdgpu_device pointer + * + * Tear down the hpd pins used by the card (evergreen+). + * Disable the hpd interrupts. + */ +static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) +{ + struct drm_device *dev = adev->ddev; + struct drm_connector *connector; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + switch (amdgpu_connector->hpd.hpd) { + case AMDGPU_HPD_1: + WREG32(mmDC_HPD1_CONTROL, 0); + break; + case AMDGPU_HPD_2: + WREG32(mmDC_HPD2_CONTROL, 0); + break; + case AMDGPU_HPD_3: + WREG32(mmDC_HPD3_CONTROL, 0); + break; + case AMDGPU_HPD_4: + WREG32(mmDC_HPD4_CONTROL, 0); + break; + case AMDGPU_HPD_5: + WREG32(mmDC_HPD5_CONTROL, 0); + break; + case AMDGPU_HPD_6: + WREG32(mmDC_HPD6_CONTROL, 0); + break; + default: + break; + } + amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); + } +} + +static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev) +{ + return mmDC_GPIO_HPD_A; +} + +static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev) +{ + u32 crtc_hung = 0; + u32 crtc_status[6]; + u32 i, j, tmp; + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { + crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); + crtc_hung |= (1 << i); + } + } + + for (j = 0; j < 10; j++) { + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (crtc_hung & (1 << i)) { + tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); + if (tmp != crtc_status[i]) + crtc_hung &= ~(1 << i); + } + } + if (crtc_hung == 0) + return false; + udelay(100); + } + + return true; +} + +static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save) +{ + u32 crtc_enabled, tmp; + int i; + + save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); + save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); + + /* disable VGA render */ + tmp = RREG32(mmVGA_RENDER_CONTROL); + tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); + WREG32(mmVGA_RENDER_CONTROL, tmp); + + /* blank the display controllers */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), + CRTC_CONTROL, CRTC_MASTER_EN); + if (crtc_enabled) { +#if 0 + u32 frame_count; + int j; + + save->crtc_enabled[i] = true; + tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { + amdgpu_display_vblank_wait(adev, i); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); + WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); + } + /* wait for the next frame */ + frame_count = amdgpu_display_vblank_get_counter(adev, i); + for (j = 0; j < adev->usec_timeout; j++) { + if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) + break; + udelay(1); + } + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { + tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); + WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); + } + tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { + tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); + WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); + } +#else + /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); + tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); + WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); + save->crtc_enabled[i] = false; + /* ***** */ +#endif + } else { + save->crtc_enabled[i] = false; + } + } +} + +static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save) +{ + u32 tmp, frame_count; + int i, j; + + /* update crtc base addresses */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], + upper_32_bits(adev->mc.vram_start)); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], + upper_32_bits(adev->mc.vram_start)); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], + (u32)adev->mc.vram_start); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], + (u32)adev->mc.vram_start); + + if (save->crtc_enabled[i]) { + tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { + tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); + WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); + } + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { + tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); + WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); + } + tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { + tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); + WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); + } + for (j = 0; j < adev->usec_timeout; j++) { + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) + break; + udelay(1); + } + tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); + tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); + /* wait for the next frame */ + frame_count = amdgpu_display_vblank_get_counter(adev, i); + for (j = 0; j < adev->usec_timeout; j++) { + if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) + break; + udelay(1); + } + } + } + + WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); + WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); + + /* Unlock vga access */ + WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); + mdelay(1); + WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); +} + +static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev, + bool render) +{ + u32 tmp; + + /* Lockout access through VGA aperture*/ + tmp = RREG32(mmVGA_HDP_CONTROL); + if (render) + tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); + else + tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); + WREG32(mmVGA_HDP_CONTROL, tmp); + + /* disable VGA render */ + tmp = RREG32(mmVGA_RENDER_CONTROL); + if (render) + tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); + else + tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); + WREG32(mmVGA_RENDER_CONTROL, tmp); +} + +static void dce_v8_0_program_fmt(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + int bpc = 0; + u32 tmp = 0; + enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; + + if (connector) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + bpc = amdgpu_connector_get_monitor_bpc(connector); + dither = amdgpu_connector->dither; + } + + /* LVDS/eDP FMT is set up by atom */ + if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) + return; + + /* not needed for analog */ + if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || + (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) + return; + + if (bpc == 0) + return; + + switch (bpc) { + case 6: + if (dither == AMDGPU_FMT_DITHER_ENABLE) + /* XXX sort out optimal dither settings */ + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | + (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); + else + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | + (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); + break; + case 8: + if (dither == AMDGPU_FMT_DITHER_ENABLE) + /* XXX sort out optimal dither settings */ + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | + (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); + else + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | + (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); + break; + case 10: + if (dither == AMDGPU_FMT_DITHER_ENABLE) + /* XXX sort out optimal dither settings */ + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | + FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | + (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); + else + tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | + (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); + break; + default: + /* not needed */ + break; + } + + WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); +} + + +/* display watermark setup */ +/** + * dce_v8_0_line_buffer_adjust - Set up the line buffer + * + * @adev: amdgpu_device pointer + * @amdgpu_crtc: the selected display controller + * @mode: the current display mode on the selected display + * controller + * + * Setup up the line buffer allocation for + * the selected display controller (CIK). + * Returns the line buffer size in pixels. + */ +static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev, + struct amdgpu_crtc *amdgpu_crtc, + struct drm_display_mode *mode) +{ + u32 tmp, buffer_alloc, i; + u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; + /* + * Line Buffer Setup + * There are 6 line buffers, one for each display controllers. + * There are 3 partitions per LB. Select the number of partitions + * to enable based on the display width. For display widths larger + * than 4096, you need use to use 2 display controllers and combine + * them using the stereo blender. + */ + if (amdgpu_crtc->base.enabled && mode) { + if (mode->crtc_hdisplay < 1920) { + tmp = 1; + buffer_alloc = 2; + } else if (mode->crtc_hdisplay < 2560) { + tmp = 2; + buffer_alloc = 2; + } else if (mode->crtc_hdisplay < 4096) { + tmp = 0; + buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; + } else { + DRM_DEBUG_KMS("Mode too big for LB!\n"); + tmp = 0; + buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; + } + } else { + tmp = 1; + buffer_alloc = 0; + } + + WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, + (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) | + (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT)); + + WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, + (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); + for (i = 0; i < adev->usec_timeout; i++) { + if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & + PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) + break; + udelay(1); + } + + if (amdgpu_crtc->base.enabled && mode) { + switch (tmp) { + case 0: + default: + return 4096 * 2; + case 1: + return 1920 * 2; + case 2: + return 2560 * 2; + } + } + + /* controller not enabled, so no lb used */ + return 0; +} + +/** + * cik_get_number_of_dram_channels - get the number of dram channels + * + * @adev: amdgpu_device pointer + * + * Look up the number of video ram channels (CIK). + * Used for display watermark bandwidth calculations + * Returns the number of dram channels + */ +static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmMC_SHARED_CHMAP); + + switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { + case 0: + default: + return 1; + case 1: + return 2; + case 2: + return 4; + case 3: + return 8; + case 4: + return 3; + case 5: + return 6; + case 6: + return 10; + case 7: + return 12; + case 8: + return 16; + } +} + +struct dce8_wm_params { + u32 dram_channels; /* number of dram channels */ + u32 yclk; /* bandwidth per dram data pin in kHz */ + u32 sclk; /* engine clock in kHz */ + u32 disp_clk; /* display clock in kHz */ + u32 src_width; /* viewport width */ + u32 active_time; /* active display time in ns */ + u32 blank_time; /* blank time in ns */ + bool interlaced; /* mode is interlaced */ + fixed20_12 vsc; /* vertical scale ratio */ + u32 num_heads; /* number of active crtcs */ + u32 bytes_per_pixel; /* bytes per pixel display + overlay */ + u32 lb_size; /* line buffer allocated to pipe */ + u32 vtaps; /* vertical scaler taps */ +}; + +/** + * dce_v8_0_dram_bandwidth - get the dram bandwidth + * + * @wm: watermark calculation data + * + * Calculate the raw dram bandwidth (CIK). + * Used for display watermark bandwidth calculations + * Returns the dram bandwidth in MBytes/s + */ +static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm) +{ + /* Calculate raw DRAM Bandwidth */ + fixed20_12 dram_efficiency; /* 0.7 */ + fixed20_12 yclk, dram_channels, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + yclk.full = dfixed_const(wm->yclk); + yclk.full = dfixed_div(yclk, a); + dram_channels.full = dfixed_const(wm->dram_channels * 4); + a.full = dfixed_const(10); + dram_efficiency.full = dfixed_const(7); + dram_efficiency.full = dfixed_div(dram_efficiency, a); + bandwidth.full = dfixed_mul(dram_channels, yclk); + bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display + * + * @wm: watermark calculation data + * + * Calculate the dram bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the dram bandwidth for display in MBytes/s + */ +static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm) +{ + /* Calculate DRAM Bandwidth and the part allocated to display. */ + fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ + fixed20_12 yclk, dram_channels, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + yclk.full = dfixed_const(wm->yclk); + yclk.full = dfixed_div(yclk, a); + dram_channels.full = dfixed_const(wm->dram_channels * 4); + a.full = dfixed_const(10); + disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ + disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); + bandwidth.full = dfixed_mul(dram_channels, yclk); + bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v8_0_data_return_bandwidth - get the data return bandwidth + * + * @wm: watermark calculation data + * + * Calculate the data return bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the data return bandwidth in MBytes/s + */ +static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm) +{ + /* Calculate the display Data return Bandwidth */ + fixed20_12 return_efficiency; /* 0.8 */ + fixed20_12 sclk, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + sclk.full = dfixed_const(wm->sclk); + sclk.full = dfixed_div(sclk, a); + a.full = dfixed_const(10); + return_efficiency.full = dfixed_const(8); + return_efficiency.full = dfixed_div(return_efficiency, a); + a.full = dfixed_const(32); + bandwidth.full = dfixed_mul(a, sclk); + bandwidth.full = dfixed_mul(bandwidth, return_efficiency); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth + * + * @wm: watermark calculation data + * + * Calculate the dmif bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the dmif bandwidth in MBytes/s + */ +static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm) +{ + /* Calculate the DMIF Request Bandwidth */ + fixed20_12 disp_clk_request_efficiency; /* 0.8 */ + fixed20_12 disp_clk, bandwidth; + fixed20_12 a, b; + + a.full = dfixed_const(1000); + disp_clk.full = dfixed_const(wm->disp_clk); + disp_clk.full = dfixed_div(disp_clk, a); + a.full = dfixed_const(32); + b.full = dfixed_mul(a, disp_clk); + + a.full = dfixed_const(10); + disp_clk_request_efficiency.full = dfixed_const(8); + disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); + + bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v8_0_available_bandwidth - get the min available bandwidth + * + * @wm: watermark calculation data + * + * Calculate the min available bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the min available bandwidth in MBytes/s + */ +static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm) +{ + /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ + u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm); + u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm); + u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm); + + return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); +} + +/** + * dce_v8_0_average_bandwidth - get the average available bandwidth + * + * @wm: watermark calculation data + * + * Calculate the average available bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the average available bandwidth in MBytes/s + */ +static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm) +{ + /* Calculate the display mode Average Bandwidth + * DisplayMode should contain the source and destination dimensions, + * timing, etc. + */ + fixed20_12 bpp; + fixed20_12 line_time; + fixed20_12 src_width; + fixed20_12 bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + line_time.full = dfixed_const(wm->active_time + wm->blank_time); + line_time.full = dfixed_div(line_time, a); + bpp.full = dfixed_const(wm->bytes_per_pixel); + src_width.full = dfixed_const(wm->src_width); + bandwidth.full = dfixed_mul(src_width, bpp); + bandwidth.full = dfixed_mul(bandwidth, wm->vsc); + bandwidth.full = dfixed_div(bandwidth, line_time); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v8_0_latency_watermark - get the latency watermark + * + * @wm: watermark calculation data + * + * Calculate the latency watermark (CIK). + * Used for display watermark bandwidth calculations + * Returns the latency watermark in ns + */ +static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm) +{ + /* First calculate the latency in ns */ + u32 mc_latency = 2000; /* 2000 ns. */ + u32 available_bandwidth = dce_v8_0_available_bandwidth(wm); + u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; + u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; + u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ + u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + + (wm->num_heads * cursor_line_pair_return_time); + u32 latency = mc_latency + other_heads_data_return_time + dc_latency; + u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; + u32 tmp, dmif_size = 12288; + fixed20_12 a, b, c; + + if (wm->num_heads == 0) + return 0; + + a.full = dfixed_const(2); + b.full = dfixed_const(1); + if ((wm->vsc.full > a.full) || + ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || + (wm->vtaps >= 5) || + ((wm->vsc.full >= a.full) && wm->interlaced)) + max_src_lines_per_dst_line = 4; + else + max_src_lines_per_dst_line = 2; + + a.full = dfixed_const(available_bandwidth); + b.full = dfixed_const(wm->num_heads); + a.full = dfixed_div(a, b); + + b.full = dfixed_const(mc_latency + 512); + c.full = dfixed_const(wm->disp_clk); + b.full = dfixed_div(b, c); + + c.full = dfixed_const(dmif_size); + b.full = dfixed_div(c, b); + + tmp = min(dfixed_trunc(a), dfixed_trunc(b)); + + b.full = dfixed_const(1000); + c.full = dfixed_const(wm->disp_clk); + b.full = dfixed_div(c, b); + c.full = dfixed_const(wm->bytes_per_pixel); + b.full = dfixed_mul(b, c); + + lb_fill_bw = min(tmp, dfixed_trunc(b)); + + a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); + b.full = dfixed_const(1000); + c.full = dfixed_const(lb_fill_bw); + b.full = dfixed_div(c, b); + a.full = dfixed_div(a, b); + line_fill_time = dfixed_trunc(a); + + if (line_fill_time < wm->active_time) + return latency; + else + return latency + (line_fill_time - wm->active_time); + +} + +/** + * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check + * average and available dram bandwidth + * + * @wm: watermark calculation data + * + * Check if the display average bandwidth fits in the display + * dram bandwidth (CIK). + * Used for display watermark bandwidth calculations + * Returns true if the display fits, false if not. + */ +static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm) +{ + if (dce_v8_0_average_bandwidth(wm) <= + (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads)) + return true; + else + return false; +} + +/** + * dce_v8_0_average_bandwidth_vs_available_bandwidth - check + * average and available bandwidth + * + * @wm: watermark calculation data + * + * Check if the display average bandwidth fits in the display + * available bandwidth (CIK). + * Used for display watermark bandwidth calculations + * Returns true if the display fits, false if not. + */ +static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm) +{ + if (dce_v8_0_average_bandwidth(wm) <= + (dce_v8_0_available_bandwidth(wm) / wm->num_heads)) + return true; + else + return false; +} + +/** + * dce_v8_0_check_latency_hiding - check latency hiding + * + * @wm: watermark calculation data + * + * Check latency hiding (CIK). + * Used for display watermark bandwidth calculations + * Returns true if the display fits, false if not. + */ +static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm) +{ + u32 lb_partitions = wm->lb_size / wm->src_width; + u32 line_time = wm->active_time + wm->blank_time; + u32 latency_tolerant_lines; + u32 latency_hiding; + fixed20_12 a; + + a.full = dfixed_const(1); + if (wm->vsc.full > a.full) + latency_tolerant_lines = 1; + else { + if (lb_partitions <= (wm->vtaps + 1)) + latency_tolerant_lines = 1; + else + latency_tolerant_lines = 2; + } + + latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); + + if (dce_v8_0_latency_watermark(wm) <= latency_hiding) + return true; + else + return false; +} + +/** + * dce_v8_0_program_watermarks - program display watermarks + * + * @adev: amdgpu_device pointer + * @amdgpu_crtc: the selected display controller + * @lb_size: line buffer size + * @num_heads: number of display controllers in use + * + * Calculate and program the display watermarks for the + * selected display controller (CIK). + */ +static void dce_v8_0_program_watermarks(struct amdgpu_device *adev, + struct amdgpu_crtc *amdgpu_crtc, + u32 lb_size, u32 num_heads) +{ + struct drm_display_mode *mode = &amdgpu_crtc->base.mode; + struct dce8_wm_params wm_low, wm_high; + u32 pixel_period; + u32 line_time = 0; + u32 latency_watermark_a = 0, latency_watermark_b = 0; + u32 tmp, wm_mask; + + if (amdgpu_crtc->base.enabled && num_heads && mode) { + pixel_period = 1000000 / (u32)mode->clock; + line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); + + /* watermark for high clocks */ + if (adev->pm.dpm_enabled) { + wm_high.yclk = + amdgpu_dpm_get_mclk(adev, false) * 10; + wm_high.sclk = + amdgpu_dpm_get_sclk(adev, false) * 10; + } else { + wm_high.yclk = adev->pm.current_mclk * 10; + wm_high.sclk = adev->pm.current_sclk * 10; + } + + wm_high.disp_clk = mode->clock; + wm_high.src_width = mode->crtc_hdisplay; + wm_high.active_time = mode->crtc_hdisplay * pixel_period; + wm_high.blank_time = line_time - wm_high.active_time; + wm_high.interlaced = false; + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + wm_high.interlaced = true; + wm_high.vsc = amdgpu_crtc->vsc; + wm_high.vtaps = 1; + if (amdgpu_crtc->rmx_type != RMX_OFF) + wm_high.vtaps = 2; + wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ + wm_high.lb_size = lb_size; + wm_high.dram_channels = cik_get_number_of_dram_channels(adev); + wm_high.num_heads = num_heads; + + /* set for high clocks */ + latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535); + + /* possibly force display priority to high */ + /* should really do this at mode validation time... */ + if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || + !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) || + !dce_v8_0_check_latency_hiding(&wm_high) || + (adev->mode_info.disp_priority == 2)) { + DRM_DEBUG_KMS("force priority to high\n"); + } + + /* watermark for low clocks */ + if (adev->pm.dpm_enabled) { + wm_low.yclk = + amdgpu_dpm_get_mclk(adev, true) * 10; + wm_low.sclk = + amdgpu_dpm_get_sclk(adev, true) * 10; + } else { + wm_low.yclk = adev->pm.current_mclk * 10; + wm_low.sclk = adev->pm.current_sclk * 10; + } + + wm_low.disp_clk = mode->clock; + wm_low.src_width = mode->crtc_hdisplay; + wm_low.active_time = mode->crtc_hdisplay * pixel_period; + wm_low.blank_time = line_time - wm_low.active_time; + wm_low.interlaced = false; + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + wm_low.interlaced = true; + wm_low.vsc = amdgpu_crtc->vsc; + wm_low.vtaps = 1; + if (amdgpu_crtc->rmx_type != RMX_OFF) + wm_low.vtaps = 2; + wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ + wm_low.lb_size = lb_size; + wm_low.dram_channels = cik_get_number_of_dram_channels(adev); + wm_low.num_heads = num_heads; + + /* set for low clocks */ + latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535); + + /* possibly force display priority to high */ + /* should really do this at mode validation time... */ + if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || + !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) || + !dce_v8_0_check_latency_hiding(&wm_low) || + (adev->mode_info.disp_priority == 2)) { + DRM_DEBUG_KMS("force priority to high\n"); + } + } + + /* select wm A */ + wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); + tmp = wm_mask; + tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); + tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, + ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | + (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); + /* select wm B */ + tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); + tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); + tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, + ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | + (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); + /* restore original selection */ + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); + + /* save values for DPM */ + amdgpu_crtc->line_time = line_time; + amdgpu_crtc->wm_high = latency_watermark_a; + amdgpu_crtc->wm_low = latency_watermark_b; +} + +/** + * dce_v8_0_bandwidth_update - program display watermarks + * + * @adev: amdgpu_device pointer + * + * Calculate and program the display watermarks and line + * buffer allocation (CIK). + */ +static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev) +{ + struct drm_display_mode *mode = NULL; + u32 num_heads = 0, lb_size; + int i; + + amdgpu_update_display_priority(adev); + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (adev->mode_info.crtcs[i]->base.enabled) + num_heads++; + } + for (i = 0; i < adev->mode_info.num_crtc; i++) { + mode = &adev->mode_info.crtcs[i]->base.mode; + lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); + dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i], + lb_size, num_heads); + } +} + +static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev) +{ + int i; + u32 offset, tmp; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + offset = adev->mode_info.audio.pin[i].offset; + tmp = RREG32_AUDIO_ENDPT(offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); + if (((tmp & + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) + adev->mode_info.audio.pin[i].connected = false; + else + adev->mode_info.audio.pin[i].connected = true; + } +} + +static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev) +{ + int i; + + dce_v8_0_audio_get_connected_pins(adev); + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + if (adev->mode_info.audio.pin[i].connected) + return &adev->mode_info.audio.pin[i]; + } + DRM_ERROR("No connected audio pins found!\n"); + return NULL; +} + +static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 offset; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + offset = dig->afmt->offset; + + WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset, + (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT)); +} + +static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, + struct drm_display_mode *mode) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + u32 tmp = 0, offset; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + offset = dig->afmt->pin->offset; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) { + if (connector->latency_present[1]) + tmp = + (connector->video_latency[1] << + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | + (connector->audio_latency[1] << + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); + else + tmp = + (0 << + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | + (0 << + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); + } else { + if (connector->latency_present[0]) + tmp = + (connector->video_latency[0] << + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | + (connector->audio_latency[0] << + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); + else + tmp = + (0 << + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | + (0 << + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); + + } + WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); +} + +static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + u32 offset, tmp; + u8 *sadb = NULL; + int sad_count; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + offset = dig->afmt->pin->offset; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); + if (sad_count < 0) { + DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); + sad_count = 0; + } + + /* program the speaker allocation */ + tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); + tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK | + AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK); + /* set HDMI mode */ + tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK; + if (sad_count) + tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); + else + tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */ + WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); + + kfree(sadb); +} + +static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 offset; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + struct cea_sad *sads; + int i, sad_count; + + static const u16 eld_reg_to_type[][2] = { + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, + }; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + offset = dig->afmt->pin->offset; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); + if (sad_count <= 0) { + DRM_ERROR("Couldn't read SADs: %d\n", sad_count); + return; + } + BUG_ON(!sads); + + for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { + u32 value = 0; + u8 stereo_freqs = 0; + int max_channels = -1; + int j; + + for (j = 0; j < sad_count; j++) { + struct cea_sad *sad = &sads[j]; + + if (sad->format == eld_reg_to_type[i][1]) { + if (sad->channels > max_channels) { + value = (sad->channels << + AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) | + (sad->byte2 << + AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) | + (sad->freq << + AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT); + max_channels = sad->channels; + } + + if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) + stereo_freqs |= sad->freq; + else + break; + } + } + + value |= (stereo_freqs << + AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT); + + WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value); + } + + kfree(sads); +} + +static void dce_v8_0_audio_enable(struct amdgpu_device *adev, + struct amdgpu_audio_pin *pin, + bool enable) +{ + if (!pin) + return; + + WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, + enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); +} + +static const u32 pin_offsets[7] = +{ + (0x1780 - 0x1780), + (0x1786 - 0x1780), + (0x178c - 0x1780), + (0x1792 - 0x1780), + (0x1798 - 0x1780), + (0x179d - 0x1780), + (0x17a4 - 0x1780), +}; + +static int dce_v8_0_audio_init(struct amdgpu_device *adev) +{ + int i; + + if (!amdgpu_audio) + return 0; + + adev->mode_info.audio.enabled = true; + + if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */ + adev->mode_info.audio.num_pins = 7; + else if ((adev->asic_type == CHIP_KABINI) || + (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */ + adev->mode_info.audio.num_pins = 3; + else if ((adev->asic_type == CHIP_BONAIRE) || + (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */ + adev->mode_info.audio.num_pins = 7; + else + adev->mode_info.audio.num_pins = 3; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + adev->mode_info.audio.pin[i].channels = -1; + adev->mode_info.audio.pin[i].rate = -1; + adev->mode_info.audio.pin[i].bits_per_sample = -1; + adev->mode_info.audio.pin[i].status_bits = 0; + adev->mode_info.audio.pin[i].category_code = 0; + adev->mode_info.audio.pin[i].connected = false; + adev->mode_info.audio.pin[i].offset = pin_offsets[i]; + adev->mode_info.audio.pin[i].id = i; + /* disable audio. it will be set up later */ + /* XXX remove once we switch to ip funcs */ + dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + } + + return 0; +} + +static void dce_v8_0_audio_fini(struct amdgpu_device *adev) +{ + int i; + + if (!adev->mode_info.audio.enabled) + return; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) + dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + + adev->mode_info.audio.enabled = false; +} + +/* + * update the N and CTS parameters for a given pixel clock rate + */ +static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + uint32_t offset = dig->afmt->offset; + + WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); + WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz); + + WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); + WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz); + + WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT)); + WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz); +} + +/* + * build a HDMI Video Info Frame + */ +static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, + void *buffer, size_t size) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + uint32_t offset = dig->afmt->offset; + uint8_t *frame = buffer + 3; + uint8_t *header = buffer; + + WREG32(mmAFMT_AVI_INFO0 + offset, + frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); + WREG32(mmAFMT_AVI_INFO1 + offset, + frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); + WREG32(mmAFMT_AVI_INFO2 + offset, + frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); + WREG32(mmAFMT_AVI_INFO3 + offset, + frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); +} + +static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + u32 dto_phase = 24 * 1000; + u32 dto_modulo = clock; + + if (!dig || !dig->afmt) + return; + + /* XXX two dtos; generally use dto0 for hdmi */ + /* Express [24MHz / target pixel clock] as an exact rational + * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE + * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator + */ + WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT)); + WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); + WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); +} + +/* + * update the info frames with the data from the current display mode + */ +static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder, + struct drm_display_mode *mode) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; + struct hdmi_avi_infoframe frame; + uint32_t offset, val; + ssize_t err; + int bpc = 8; + + if (!dig || !dig->afmt) + return; + + /* Silent, r600_hdmi_enable will raise WARN for us */ + if (!dig->afmt->enabled) + return; + offset = dig->afmt->offset; + + /* hdmi deep color mode general control packets setup, if bpc > 8 */ + if (encoder->crtc) { + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + bpc = amdgpu_crtc->bpc; + } + + /* disable audio prior to setting up hw */ + dig->afmt->pin = dce_v8_0_audio_get_pin(adev); + dce_v8_0_audio_enable(adev, dig->afmt->pin, false); + + dce_v8_0_audio_set_dto(encoder, mode->clock); + + WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, + HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */ + + WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000); + + val = RREG32(mmHDMI_CONTROL + offset); + val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; + val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK; + + switch (bpc) { + case 0: + case 6: + case 8: + case 16: + default: + DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", + connector->name, bpc); + break; + case 10: + val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; + val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; + DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", + connector->name); + break; + case 12: + val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; + val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; + DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", + connector->name); + break; + } + + WREG32(mmHDMI_CONTROL + offset, val); + + WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, + HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */ + HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */ + HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */ + + WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset, + HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */ + HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */ + + WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset, + AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */ + + WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset, + (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */ + + WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ + + WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset, + (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */ + (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */ + + WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset, + AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */ + + /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ + + if (bpc > 8) + WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, + HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */ + else + WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, + HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */ + HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */ + + dce_v8_0_afmt_update_ACR(encoder, mode->clock); + + WREG32(mmAFMT_60958_0 + offset, + (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT)); + + WREG32(mmAFMT_60958_1 + offset, + (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT)); + + WREG32(mmAFMT_60958_2 + offset, + (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) | + (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) | + (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) | + (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) | + (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) | + (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT)); + + dce_v8_0_audio_write_speaker_allocation(encoder); + + + WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset, + (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); + + dce_v8_0_afmt_audio_select_pin(encoder); + dce_v8_0_audio_write_sad_regs(encoder); + dce_v8_0_audio_write_latency_fields(encoder, mode); + + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); + if (err < 0) { + DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); + return; + } + + err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); + if (err < 0) { + DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); + return; + } + + dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); + + WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset, + HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */ + HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK); /* required for audio info values to be updated */ + + WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset, + (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */ + ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK); + + WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset, + AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */ + + /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ + WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); + WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); + WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001); + WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001); + + /* enable audio after to setting up hw */ + dce_v8_0_audio_enable(adev, dig->afmt->pin, true); +} + +static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + + if (!dig || !dig->afmt) + return; + + /* Silent, r600_hdmi_enable will raise WARN for us */ + if (enable && dig->afmt->enabled) + return; + if (!enable && !dig->afmt->enabled) + return; + + if (!enable && dig->afmt->pin) { + dce_v8_0_audio_enable(adev, dig->afmt->pin, false); + dig->afmt->pin = NULL; + } + + dig->afmt->enabled = enable; + + DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", + enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); +} + +static void dce_v8_0_afmt_init(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->mode_info.num_dig; i++) + adev->mode_info.afmt[i] = NULL; + + /* DCE8 has audio blocks tied to DIG encoders */ + for (i = 0; i < adev->mode_info.num_dig; i++) { + adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); + if (adev->mode_info.afmt[i]) { + adev->mode_info.afmt[i]->offset = dig_offsets[i]; + adev->mode_info.afmt[i]->id = i; + } + } +} + +static void dce_v8_0_afmt_fini(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->mode_info.num_dig; i++) { + kfree(adev->mode_info.afmt[i]); + adev->mode_info.afmt[i] = NULL; + } +} + +static const u32 vga_control_regs[6] = +{ + mmD1VGA_CONTROL, + mmD2VGA_CONTROL, + mmD3VGA_CONTROL, + mmD4VGA_CONTROL, + mmD5VGA_CONTROL, + mmD6VGA_CONTROL, +}; + +static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + u32 vga_control; + + vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; + if (enable) + WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); + else + WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); +} + +static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + + if (enable) + WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); + else + WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); +} + +static void dce_v8_0_tiling_fields(uint64_t tiling_flags, unsigned *bankw, + unsigned *bankh, unsigned *mtaspect, + unsigned *tile_split) +{ + *bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK; + *bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK; + *mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK; + *tile_split = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK; + switch (*bankw) { + default: + case 1: + *bankw = ADDR_SURF_BANK_WIDTH_1; + break; + case 2: + *bankw = ADDR_SURF_BANK_WIDTH_2; + break; + case 4: + *bankw = ADDR_SURF_BANK_WIDTH_4; + break; + case 8: + *bankw = ADDR_SURF_BANK_WIDTH_8; + break; + } + switch (*bankh) { + default: + case 1: + *bankh = ADDR_SURF_BANK_HEIGHT_1; + break; + case 2: + *bankh = ADDR_SURF_BANK_HEIGHT_2; + break; + case 4: + *bankh = ADDR_SURF_BANK_HEIGHT_4; + break; + case 8: + *bankh = ADDR_SURF_BANK_HEIGHT_8; + break; + } + switch (*mtaspect) { + default: + case 1: + *mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_1; + break; + case 2: + *mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_2; + break; + case 4: + *mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_4; + break; + case 8: + *mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_8; + break; + } +} + +static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int x, int y, int atomic) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_framebuffer *amdgpu_fb; + struct drm_framebuffer *target_fb; + struct drm_gem_object *obj; + struct amdgpu_bo *rbo; + uint64_t fb_location, tiling_flags; + uint32_t fb_format, fb_pitch_pixels; + unsigned bankw, bankh, mtaspect, tile_split; + u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); + u32 pipe_config = (adev->gfx.config.tile_mode_array[10] >> 6) & 0x1f; + u32 tmp, viewport_w, viewport_h; + int r; + bool bypass_lut = false; + + /* no fb bound */ + if (!atomic && !crtc->primary->fb) { + DRM_DEBUG_KMS("No FB bound\n"); + return 0; + } + + if (atomic) { + amdgpu_fb = to_amdgpu_framebuffer(fb); + target_fb = fb; + } + else { + amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); + target_fb = crtc->primary->fb; + } + + /* If atomic, assume fb object is pinned & idle & fenced and + * just update base pointers + */ + obj = amdgpu_fb->obj; + rbo = gem_to_amdgpu_bo(obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r != 0)) + return r; + + if (atomic) + fb_location = amdgpu_bo_gpu_offset(rbo); + else { + r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); + if (unlikely(r != 0)) { + amdgpu_bo_unreserve(rbo); + return -EINVAL; + } + } + + amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); + amdgpu_bo_unreserve(rbo); + + switch (target_fb->pixel_format) { + case DRM_FORMAT_C8: + fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | + (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); + break; + case DRM_FORMAT_XRGB4444: + case DRM_FORMAT_ARGB4444: + fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | + (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); +#ifdef __BIG_ENDIAN + fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); +#endif + break; + case DRM_FORMAT_XRGB1555: + case DRM_FORMAT_ARGB1555: + fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | + (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); +#ifdef __BIG_ENDIAN + fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); +#endif + break; + case DRM_FORMAT_BGRX5551: + case DRM_FORMAT_BGRA5551: + fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | + (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); +#ifdef __BIG_ENDIAN + fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); +#endif + break; + case DRM_FORMAT_RGB565: + fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | + (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); +#ifdef __BIG_ENDIAN + fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); +#endif + break; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | + (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); +#ifdef __BIG_ENDIAN + fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); +#endif + break; + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | + (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); +#ifdef __BIG_ENDIAN + fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); +#endif + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ + bypass_lut = true; + break; + case DRM_FORMAT_BGRX1010102: + case DRM_FORMAT_BGRA1010102: + fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | + (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); +#ifdef __BIG_ENDIAN + fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); +#endif + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ + bypass_lut = true; + break; + default: + DRM_ERROR("Unsupported screen format %s\n", + drm_get_format_name(target_fb->pixel_format)); + return -EINVAL; + } + + if (tiling_flags & AMDGPU_TILING_MACRO) { + unsigned tileb, index, num_banks, tile_split_bytes; + + dce_v8_0_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); + /* Set NUM_BANKS. */ + /* Calculate the macrotile mode index. */ + tile_split_bytes = 64 << tile_split; + tileb = 8 * 8 * target_fb->bits_per_pixel / 8; + tileb = min(tile_split_bytes, tileb); + + for (index = 0; tileb > 64; index++) { + tileb >>= 1; + } + + if (index >= 16) { + DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", + target_fb->bits_per_pixel, tile_split); + return -EINVAL; + } + + num_banks = (adev->gfx.config.macrotile_mode_array[index] >> 6) & 0x3; + fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT); + fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); + fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); + fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); + fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT); + fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); + fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT); + } else if (tiling_flags & AMDGPU_TILING_MICRO) { + fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); + } + + /* Read the pipe config from the 2D TILED SCANOUT mode. + * It should be the same for the other modes too, but not all + * modes set the pipe config field. */ + fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); + + dce_v8_0_vga_enable(crtc, false); + + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(fb_location)); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(fb_location)); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); + WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); + WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); + + /* + * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT + * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to + * retain the full precision throughout the pipeline. + */ + WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, + (bypass_lut ? LUT_10BIT_BYPASS_EN : 0), + ~LUT_10BIT_BYPASS_EN); + + if (bypass_lut) + DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); + + WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); + WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); + + fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); + + dce_v8_0_grph_enable(crtc, true); + + WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, + target_fb->height); + + x &= ~3; + y &= ~1; + WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, + (x << 16) | y); + viewport_w = crtc->mode.hdisplay; + viewport_h = (crtc->mode.vdisplay + 1) & ~1; + WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, + (viewport_w << 16) | viewport_h); + + /* pageflip setup */ + /* make sure flip is at vb rather than hb */ + tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); + tmp &= ~GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK; + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + /* set pageflip to happen only at start of vblank interval (front porch) */ + WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); + + if (!atomic && fb && fb != crtc->primary->fb) { + amdgpu_fb = to_amdgpu_framebuffer(fb); + rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r != 0)) + return r; + amdgpu_bo_unpin(rbo); + amdgpu_bo_unreserve(rbo); + } + + /* Bytes per pixel may have changed */ + dce_v8_0_bandwidth_update(adev); + + return 0; +} + +static void dce_v8_0_set_interleave(struct drm_crtc *crtc, + struct drm_display_mode *mode) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, + LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT); + else + WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); +} + +static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + int i; + + DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); + + WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, + ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | + (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); + WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, + PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); + WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, + PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); + WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, + ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | + (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); + + WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); + + WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); + + WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); + + WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); + + WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); + for (i = 0; i < 256; i++) { + WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, + (amdgpu_crtc->lut_r[i] << 20) | + (amdgpu_crtc->lut_g[i] << 10) | + (amdgpu_crtc->lut_b[i] << 0)); + } + + WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, + ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | + (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | + (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); + WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, + ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | + (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); + WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, + ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | + (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); + WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, + ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | + (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); + /* XXX match this to the depth of the crtc fmt block, move to modeset? */ + WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); + /* XXX this only needs to be programmed once per crtc at startup, + * not sure where the best place for it is + */ + WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, + ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK); +} + +static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + if (dig->linkb) + return 1; + else + return 0; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + if (dig->linkb) + return 3; + else + return 2; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + if (dig->linkb) + return 5; + else + return 4; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + return 6; + break; + default: + DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); + return 0; + } +} + +/** + * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc. + * + * @crtc: drm crtc + * + * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors + * a single PPLL can be used for all DP crtcs/encoders. For non-DP + * monitors a dedicated PPLL must be used. If a particular board has + * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming + * as there is no need to program the PLL itself. If we are not able to + * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to + * avoid messing up an existing monitor. + * + * Asic specific PLL information + * + * DCE 8.x + * KB/KV + * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) + * CI + * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC + * + */ +static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + u32 pll_in_use; + int pll; + + if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { + if (adev->clock.dp_extclk) + /* skip PPLL programming if using ext clock */ + return ATOM_PPLL_INVALID; + else { + /* use the same PPLL for all DP monitors */ + pll = amdgpu_pll_get_shared_dp_ppll(crtc); + if (pll != ATOM_PPLL_INVALID) + return pll; + } + } else { + /* use the same PPLL for all monitors with the same clock */ + pll = amdgpu_pll_get_shared_nondp_ppll(crtc); + if (pll != ATOM_PPLL_INVALID) + return pll; + } + /* otherwise, pick one of the plls */ + if ((adev->asic_type == CHIP_KABINI) || + (adev->asic_type == CHIP_MULLINS)) { + /* KB/ML has PPLL1 and PPLL2 */ + pll_in_use = amdgpu_pll_get_use_mask(crtc); + if (!(pll_in_use & (1 << ATOM_PPLL2))) + return ATOM_PPLL2; + if (!(pll_in_use & (1 << ATOM_PPLL1))) + return ATOM_PPLL1; + DRM_ERROR("unable to allocate a PPLL\n"); + return ATOM_PPLL_INVALID; + } else { + /* CI/KV has PPLL0, PPLL1, and PPLL2 */ + pll_in_use = amdgpu_pll_get_use_mask(crtc); + if (!(pll_in_use & (1 << ATOM_PPLL2))) + return ATOM_PPLL2; + if (!(pll_in_use & (1 << ATOM_PPLL1))) + return ATOM_PPLL1; + if (!(pll_in_use & (1 << ATOM_PPLL0))) + return ATOM_PPLL0; + DRM_ERROR("unable to allocate a PPLL\n"); + return ATOM_PPLL_INVALID; + } + return ATOM_PPLL_INVALID; +} + +static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock) +{ + struct amdgpu_device *adev = crtc->dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + uint32_t cur_lock; + + cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); + if (lock) + cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; + else + cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; + WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); +} + +static void dce_v8_0_hide_cursor(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, + (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | + (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); +} + +static void dce_v8_0_show_cursor(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, + CUR_CONTROL__CURSOR_EN_MASK | + (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | + (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); +} + +static void dce_v8_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, + uint64_t gpu_addr) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + + WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(gpu_addr)); + WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + gpu_addr & 0xffffffff); +} + +static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc, + int x, int y) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + int xorigin = 0, yorigin = 0; + + /* avivo cursor are offset into the total surface */ + x += crtc->x; + y += crtc->y; + DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); + + if (x < 0) { + xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); + x = 0; + } + if (y < 0) { + yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); + y = 0; + } + + dce_v8_0_lock_cursor(crtc, true); + WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); + WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, + ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); + dce_v8_0_lock_cursor(crtc, false); + + return 0; +} + +static int dce_v8_0_crtc_cursor_set(struct drm_crtc *crtc, + struct drm_file *file_priv, + uint32_t handle, + uint32_t width, + uint32_t height) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_gem_object *obj; + struct amdgpu_bo *robj; + uint64_t gpu_addr; + int ret; + + if (!handle) { + /* turn off cursor */ + dce_v8_0_hide_cursor(crtc); + obj = NULL; + goto unpin; + } + + if ((width > amdgpu_crtc->max_cursor_width) || + (height > amdgpu_crtc->max_cursor_height)) { + DRM_ERROR("bad cursor width or height %d x %d\n", width, height); + return -EINVAL; + } + + obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); + if (!obj) { + DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); + return -ENOENT; + } + + robj = gem_to_amdgpu_bo(obj); + ret = amdgpu_bo_reserve(robj, false); + if (unlikely(ret != 0)) + goto fail; + ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, + 0, &gpu_addr); + amdgpu_bo_unreserve(robj); + if (ret) + goto fail; + + amdgpu_crtc->cursor_width = width; + amdgpu_crtc->cursor_height = height; + + dce_v8_0_lock_cursor(crtc, true); + dce_v8_0_set_cursor(crtc, obj, gpu_addr); + dce_v8_0_show_cursor(crtc); + dce_v8_0_lock_cursor(crtc, false); + +unpin: + if (amdgpu_crtc->cursor_bo) { + robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); + ret = amdgpu_bo_reserve(robj, false); + if (likely(ret == 0)) { + amdgpu_bo_unpin(robj); + amdgpu_bo_unreserve(robj); + } + drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); + } + + amdgpu_crtc->cursor_bo = obj; + return 0; +fail: + drm_gem_object_unreference_unlocked(obj); + + return ret; +} + +static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t start, uint32_t size) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + int end = (start + size > 256) ? 256 : start + size, i; + + /* userspace palettes are always correct as is */ + for (i = start; i < end; i++) { + amdgpu_crtc->lut_r[i] = red[i] >> 6; + amdgpu_crtc->lut_g[i] = green[i] >> 6; + amdgpu_crtc->lut_b[i] = blue[i] >> 6; + } + dce_v8_0_crtc_load_lut(crtc); +} + +static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + drm_crtc_cleanup(crtc); + destroy_workqueue(amdgpu_crtc->pflip_queue); + kfree(amdgpu_crtc); +} + +static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { + .cursor_set = dce_v8_0_crtc_cursor_set, + .cursor_move = dce_v8_0_crtc_cursor_move, + .gamma_set = dce_v8_0_crtc_gamma_set, + .set_config = amdgpu_crtc_set_config, + .destroy = dce_v8_0_crtc_destroy, + .page_flip = amdgpu_crtc_page_flip, +}; + +static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + switch (mode) { + case DRM_MODE_DPMS_ON: + amdgpu_crtc->enabled = true; + amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); + dce_v8_0_vga_enable(crtc, true); + amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); + dce_v8_0_vga_enable(crtc, false); + drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); + dce_v8_0_crtc_load_lut(crtc); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id); + if (amdgpu_crtc->enabled) { + dce_v8_0_vga_enable(crtc, true); + amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); + dce_v8_0_vga_enable(crtc, false); + } + amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); + amdgpu_crtc->enabled = false; + break; + } + /* adjust pm to dpms */ + amdgpu_pm_compute_clocks(adev); +} + +static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc) +{ + /* disable crtc pair power gating before programming */ + amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); + amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); + dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); +} + +static void dce_v8_0_crtc_commit(struct drm_crtc *crtc) +{ + dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); + amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); +} + +static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_atom_ss ss; + int i; + + dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); + if (crtc->primary->fb) { + int r; + struct amdgpu_framebuffer *amdgpu_fb; + struct amdgpu_bo *rbo; + + amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); + rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r)) + DRM_ERROR("failed to reserve rbo before unpin\n"); + else { + amdgpu_bo_unpin(rbo); + amdgpu_bo_unreserve(rbo); + } + } + /* disable the GRPH */ + dce_v8_0_grph_enable(crtc, false); + + amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (adev->mode_info.crtcs[i] && + adev->mode_info.crtcs[i]->enabled && + i != amdgpu_crtc->crtc_id && + amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { + /* one other crtc is using this pll don't turn + * off the pll + */ + goto done; + } + } + + switch (amdgpu_crtc->pll_id) { + case ATOM_PPLL1: + case ATOM_PPLL2: + /* disable the ppll */ + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, + 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); + break; + case ATOM_PPLL0: + /* disable the ppll */ + if ((adev->asic_type == CHIP_KAVERI) || + (adev->asic_type == CHIP_BONAIRE) || + (adev->asic_type == CHIP_HAWAII)) + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, + 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); + break; + default: + break; + } +done: + amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; + amdgpu_crtc->adjusted_clock = 0; + amdgpu_crtc->encoder = NULL; + amdgpu_crtc->connector = NULL; +} + +static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode, + int x, int y, struct drm_framebuffer *old_fb) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + if (!amdgpu_crtc->adjusted_clock) + return -EINVAL; + + amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); + amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); + dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); + amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); + amdgpu_atombios_crtc_scaler_setup(crtc); + /* update the hw version fpr dpm */ + amdgpu_crtc->hw_mode = *adjusted_mode; + + return 0; +} + +static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct drm_encoder *encoder; + + /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + amdgpu_crtc->encoder = encoder; + amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); + break; + } + } + if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { + amdgpu_crtc->encoder = NULL; + amdgpu_crtc->connector = NULL; + return false; + } + if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) + return false; + if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) + return false; + /* pick pll */ + amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc); + /* if we can't get a PPLL for a non-DP encoder, fail */ + if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && + !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) + return false; + + return true; +} + +static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, + struct drm_framebuffer *old_fb) +{ + return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); +} + +static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int x, int y, enum mode_set_atomic state) +{ + return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1); +} + +static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { + .dpms = dce_v8_0_crtc_dpms, + .mode_fixup = dce_v8_0_crtc_mode_fixup, + .mode_set = dce_v8_0_crtc_mode_set, + .mode_set_base = dce_v8_0_crtc_set_base, + .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic, + .prepare = dce_v8_0_crtc_prepare, + .commit = dce_v8_0_crtc_commit, + .load_lut = dce_v8_0_crtc_load_lut, + .disable = dce_v8_0_crtc_disable, +}; + +static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) +{ + struct amdgpu_crtc *amdgpu_crtc; + int i; + + amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + + (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); + if (amdgpu_crtc == NULL) + return -ENOMEM; + + drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs); + + drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); + amdgpu_crtc->crtc_id = index; + amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue"); + adev->mode_info.crtcs[index] = amdgpu_crtc; + + amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH; + amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; + adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; + adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; + + for (i = 0; i < 256; i++) { + amdgpu_crtc->lut_r[i] = i << 2; + amdgpu_crtc->lut_g[i] = i << 2; + amdgpu_crtc->lut_b[i] = i << 2; + } + + amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; + + amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; + amdgpu_crtc->adjusted_clock = 0; + amdgpu_crtc->encoder = NULL; + amdgpu_crtc->connector = NULL; + drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs); + + return 0; +} + +static int dce_v8_0_early_init(struct amdgpu_device *adev) +{ + adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; + adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; + + dce_v8_0_set_display_funcs(adev); + dce_v8_0_set_irq_funcs(adev); + + switch (adev->asic_type) { + case CHIP_BONAIRE: + case CHIP_HAWAII: + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; + break; + case CHIP_KAVERI: + adev->mode_info.num_crtc = 4; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 7; + break; + case CHIP_KABINI: + case CHIP_MULLINS: + adev->mode_info.num_crtc = 2; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; /* ? */ + break; + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + + return 0; +} + +static int dce_v8_0_sw_init(struct amdgpu_device *adev) +{ + int r, i; + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); + if (r) + return r; + } + + for (i = 8; i < 20; i += 2) { + r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); + if (r) + return r; + } + + /* HPD hotplug */ + r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); + if (r) + return r; + + adev->mode_info.mode_config_initialized = true; + + adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; + + adev->ddev->mode_config.max_width = 16384; + adev->ddev->mode_config.max_height = 16384; + + adev->ddev->mode_config.preferred_depth = 24; + adev->ddev->mode_config.prefer_shadow = 1; + + adev->ddev->mode_config.fb_base = adev->mc.aper_base; + + r = amdgpu_modeset_create_props(adev); + if (r) + return r; + + adev->ddev->mode_config.max_width = 16384; + adev->ddev->mode_config.max_height = 16384; + + /* allocate crtcs */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + r = dce_v8_0_crtc_init(adev, i); + if (r) + return r; + } + + if (amdgpu_atombios_get_connector_info_from_object_table(adev)) + amdgpu_print_display_setup(adev->ddev); + else + return -EINVAL; + + /* setup afmt */ + dce_v8_0_afmt_init(adev); + + r = dce_v8_0_audio_init(adev); + if (r) + return r; + + drm_kms_helper_poll_init(adev->ddev); + + return r; +} + +static int dce_v8_0_sw_fini(struct amdgpu_device *adev) +{ + kfree(adev->mode_info.bios_hardcoded_edid); + + drm_kms_helper_poll_fini(adev->ddev); + + dce_v8_0_audio_fini(adev); + + dce_v8_0_afmt_fini(adev); + + drm_mode_config_cleanup(adev->ddev); + adev->mode_info.mode_config_initialized = false; + + return 0; +} + +static int dce_v8_0_hw_init(struct amdgpu_device *adev) +{ + int i; + + /* init dig PHYs, disp eng pll */ + amdgpu_atombios_encoder_init_dig(adev); + amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); + + /* initialize hpd */ + dce_v8_0_hpd_init(adev); + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + } + + return 0; +} + +static int dce_v8_0_hw_fini(struct amdgpu_device *adev) +{ + int i; + + dce_v8_0_hpd_fini(adev); + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + } + + return 0; +} + +static int dce_v8_0_suspend(struct amdgpu_device *adev) +{ + struct drm_connector *connector; + + drm_kms_helper_poll_disable(adev->ddev); + + /* turn off display hw */ + list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); + } + + amdgpu_atombios_scratch_regs_save(adev); + + dce_v8_0_hpd_fini(adev); + + return 0; +} + +static int dce_v8_0_resume(struct amdgpu_device *adev) +{ + struct drm_connector *connector; + + amdgpu_atombios_scratch_regs_restore(adev); + + /* init dig PHYs, disp eng pll */ + amdgpu_atombios_encoder_init_dig(adev); + amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); + /* turn on the BL */ + if (adev->mode_info.bl_encoder) { + u8 bl_level = amdgpu_display_backlight_get_level(adev, + adev->mode_info.bl_encoder); + amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, + bl_level); + } + + /* initialize hpd */ + dce_v8_0_hpd_init(adev); + + /* blat the mode back in */ + drm_helper_resume_force_mode(adev->ddev); + /* turn on display hw */ + list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); + } + + drm_kms_helper_poll_enable(adev->ddev); + + return 0; +} + +static bool dce_v8_0_is_idle(struct amdgpu_device *adev) +{ + /* XXX todo */ + return true; +} + +static int dce_v8_0_wait_for_idle(struct amdgpu_device *adev) +{ + /* XXX todo */ + return 0; +} + +static void dce_v8_0_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "DCE 8.x registers\n"); + /* XXX todo */ +} + +static int dce_v8_0_soft_reset(struct amdgpu_device *adev) +{ + u32 srbm_soft_reset = 0, tmp; + + if (dce_v8_0_is_display_hung(adev)) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; + + if (srbm_soft_reset) { + dce_v8_0_print_status(adev); + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + dce_v8_0_print_status(adev); + } + return 0; +} + +static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, + int crtc, + enum amdgpu_interrupt_state state) +{ + u32 reg_block, lb_interrupt_mask; + + if (crtc >= adev->mode_info.num_crtc) { + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + switch (crtc) { + case 0: + reg_block = CRTC0_REGISTER_OFFSET; + break; + case 1: + reg_block = CRTC1_REGISTER_OFFSET; + break; + case 2: + reg_block = CRTC2_REGISTER_OFFSET; + break; + case 3: + reg_block = CRTC3_REGISTER_OFFSET; + break; + case 4: + reg_block = CRTC4_REGISTER_OFFSET; + break; + case 5: + reg_block = CRTC5_REGISTER_OFFSET; + break; + default: + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); + lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; + WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); + break; + case AMDGPU_IRQ_STATE_ENABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); + lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; + WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); + break; + default: + break; + } +} + +static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, + int crtc, + enum amdgpu_interrupt_state state) +{ + u32 reg_block, lb_interrupt_mask; + + if (crtc >= adev->mode_info.num_crtc) { + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + switch (crtc) { + case 0: + reg_block = CRTC0_REGISTER_OFFSET; + break; + case 1: + reg_block = CRTC1_REGISTER_OFFSET; + break; + case 2: + reg_block = CRTC2_REGISTER_OFFSET; + break; + case 3: + reg_block = CRTC3_REGISTER_OFFSET; + break; + case 4: + reg_block = CRTC4_REGISTER_OFFSET; + break; + case 5: + reg_block = CRTC5_REGISTER_OFFSET; + break; + default: + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); + lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; + WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); + break; + case AMDGPU_IRQ_STATE_ENABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); + lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; + WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); + break; + default: + break; + } +} + +static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; + + switch (type) { + case AMDGPU_HPD_1: + dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL; + break; + case AMDGPU_HPD_2: + dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL; + break; + case AMDGPU_HPD_3: + dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL; + break; + case AMDGPU_HPD_4: + dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL; + break; + case AMDGPU_HPD_5: + dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL; + break; + case AMDGPU_HPD_6: + dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL; + break; + default: + DRM_DEBUG("invalid hdp %d\n", type); + return 0; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); + dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; + WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); + dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; + WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); + break; + default: + break; + } + + return 0; +} + +static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + switch (type) { + case AMDGPU_CRTC_IRQ_VBLANK1: + dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK2: + dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK3: + dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK4: + dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK5: + dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK6: + dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state); + break; + case AMDGPU_CRTC_IRQ_VLINE1: + dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state); + break; + case AMDGPU_CRTC_IRQ_VLINE2: + dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state); + break; + case AMDGPU_CRTC_IRQ_VLINE3: + dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state); + break; + case AMDGPU_CRTC_IRQ_VLINE4: + dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state); + break; + case AMDGPU_CRTC_IRQ_VLINE5: + dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state); + break; + case AMDGPU_CRTC_IRQ_VLINE6: + dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state); + break; + default: + break; + } + return 0; +} + +static int dce_v8_0_crtc_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + unsigned crtc = entry->src_id - 1; + uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); + unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); + + switch (entry->src_data) { + case 0: /* vblank */ + if (disp_int & interrupt_status_offsets[crtc].vblank) { + WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); + if (amdgpu_irq_enabled(adev, source, irq_type)) { + drm_handle_vblank(adev->ddev, crtc); + } + DRM_DEBUG("IH: D%d vblank\n", crtc + 1); + } + break; + case 1: /* vline */ + if (disp_int & interrupt_status_offsets[crtc].vline) { + WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK); + DRM_DEBUG("IH: D%d vline\n", crtc + 1); + } + break; + default: + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + break; + } + + return 0; +} + +static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 reg, reg_block; + /* now deal with page flip IRQ */ + switch (type) { + case AMDGPU_PAGEFLIP_IRQ_D1: + reg_block = CRTC0_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D2: + reg_block = CRTC1_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D3: + reg_block = CRTC2_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D4: + reg_block = CRTC3_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D5: + reg_block = CRTC4_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D6: + reg_block = CRTC5_REGISTER_OFFSET; + break; + default: + DRM_ERROR("invalid pageflip crtc %d\n", type); + return -EINVAL; + } + + reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); + if (state == AMDGPU_IRQ_STATE_DISABLE) + WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + else + WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + + return 0; +} + +static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + int reg_block; + unsigned long flags; + unsigned crtc_id; + struct amdgpu_crtc *amdgpu_crtc; + struct amdgpu_flip_work *works; + + crtc_id = (entry->src_id - 8) >> 1; + amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + + /* ack the interrupt */ + switch(crtc_id){ + case AMDGPU_PAGEFLIP_IRQ_D1: + reg_block = CRTC0_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D2: + reg_block = CRTC1_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D3: + reg_block = CRTC2_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D4: + reg_block = CRTC3_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D5: + reg_block = CRTC4_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D6: + reg_block = CRTC5_REGISTER_OFFSET; + break; + default: + DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); + return -EINVAL; + } + + if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) + WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); + + /* IRQ could occur when in initial stage */ + if (amdgpu_crtc == NULL) + return 0; + + spin_lock_irqsave(&adev->ddev->event_lock, flags); + works = amdgpu_crtc->pflip_works; + if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ + DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " + "AMDGPU_FLIP_SUBMITTED(%d)\n", + amdgpu_crtc->pflip_status, + AMDGPU_FLIP_SUBMITTED); + spin_unlock_irqrestore(&adev->ddev->event_lock, flags); + return 0; + } + + /* page flip completed. clean up */ + amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; + amdgpu_crtc->pflip_works = NULL; + + /* wakeup usersapce */ + if (works->event) + drm_send_vblank_event(adev->ddev, crtc_id, works->event); + + spin_unlock_irqrestore(&adev->ddev->event_lock, flags); + + drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); + amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id); + queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); + + return 0; +} + +static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + uint32_t disp_int, mask, int_control, tmp; + unsigned hpd; + + if (entry->src_data > 6) { + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + return 0; + } + + hpd = entry->src_data; + disp_int = RREG32(interrupt_status_offsets[hpd].reg); + mask = interrupt_status_offsets[hpd].hpd; + int_control = hpd_int_control_offsets[hpd]; + + if (disp_int & mask) { + tmp = RREG32(int_control); + tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; + WREG32(int_control, tmp); + schedule_work(&adev->hotplug_work); + DRM_DEBUG("IH: HPD%d\n", hpd + 1); + } + + return 0; + +} + +static int dce_v8_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static int dce_v8_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs dce_v8_0_ip_funcs = { + .early_init = dce_v8_0_early_init, + .late_init = NULL, + .sw_init = dce_v8_0_sw_init, + .sw_fini = dce_v8_0_sw_fini, + .hw_init = dce_v8_0_hw_init, + .hw_fini = dce_v8_0_hw_fini, + .suspend = dce_v8_0_suspend, + .resume = dce_v8_0_resume, + .is_idle = dce_v8_0_is_idle, + .wait_for_idle = dce_v8_0_wait_for_idle, + .soft_reset = dce_v8_0_soft_reset, + .print_status = dce_v8_0_print_status, + .set_clockgating_state = dce_v8_0_set_clockgating_state, + .set_powergating_state = dce_v8_0_set_powergating_state, +}; + +static void +dce_v8_0_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + + amdgpu_encoder->pixel_clock = adjusted_mode->clock; + + /* need to call this here rather than in prepare() since we need some crtc info */ + amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); + + /* set scaler clears this on some chips */ + dce_v8_0_set_interleave(encoder->crtc, mode); + + if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { + dce_v8_0_afmt_enable(encoder, true); + dce_v8_0_afmt_setmode(encoder, adjusted_mode); + } +} + +static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + + if ((amdgpu_encoder->active_device & + (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || + (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != + ENCODER_OBJECT_ID_NONE)) { + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + if (dig) { + dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder); + if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) + dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; + } + } + + amdgpu_atombios_scratch_regs_lock(adev, true); + + if (connector) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + /* select the clock/data port if it uses a router */ + if (amdgpu_connector->router.cd_valid) + amdgpu_i2c_router_select_cd_port(amdgpu_connector); + + /* turn eDP panel on for mode set */ + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) + amdgpu_atombios_encoder_set_edp_panel_power(connector, + ATOM_TRANSMITTER_ACTION_POWER_ON); + } + + /* this is needed for the pll/ss setup to work correctly in some cases */ + amdgpu_atombios_encoder_set_crtc_source(encoder); + /* set up the FMT blocks */ + dce_v8_0_program_fmt(encoder); +} + +static void dce_v8_0_encoder_commit(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + + /* need to call this here as we need the crtc set up */ + amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); + amdgpu_atombios_scratch_regs_lock(adev, false); +} + +static void dce_v8_0_encoder_disable(struct drm_encoder *encoder) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig; + + amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); + + if (amdgpu_atombios_encoder_is_digital(encoder)) { + if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) + dce_v8_0_afmt_enable(encoder, false); + dig = amdgpu_encoder->enc_priv; + dig->dig_encoder = -1; + } + amdgpu_encoder->active_device = 0; +} + +/* these are handled by the primary encoders */ +static void dce_v8_0_ext_prepare(struct drm_encoder *encoder) +{ + +} + +static void dce_v8_0_ext_commit(struct drm_encoder *encoder) +{ + +} + +static void +dce_v8_0_ext_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + +} + +static void dce_v8_0_ext_disable(struct drm_encoder *encoder) +{ + +} + +static void +dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode) +{ + +} + +static bool dce_v8_0_ext_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = { + .dpms = dce_v8_0_ext_dpms, + .mode_fixup = dce_v8_0_ext_mode_fixup, + .prepare = dce_v8_0_ext_prepare, + .mode_set = dce_v8_0_ext_mode_set, + .commit = dce_v8_0_ext_commit, + .disable = dce_v8_0_ext_disable, + /* no detect for TMDS/LVDS yet */ +}; + +static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = { + .dpms = amdgpu_atombios_encoder_dpms, + .mode_fixup = amdgpu_atombios_encoder_mode_fixup, + .prepare = dce_v8_0_encoder_prepare, + .mode_set = dce_v8_0_encoder_mode_set, + .commit = dce_v8_0_encoder_commit, + .disable = dce_v8_0_encoder_disable, + .detect = amdgpu_atombios_encoder_dig_detect, +}; + +static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = { + .dpms = amdgpu_atombios_encoder_dpms, + .mode_fixup = amdgpu_atombios_encoder_mode_fixup, + .prepare = dce_v8_0_encoder_prepare, + .mode_set = dce_v8_0_encoder_mode_set, + .commit = dce_v8_0_encoder_commit, + .detect = amdgpu_atombios_encoder_dac_detect, +}; + +static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) + amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); + kfree(amdgpu_encoder->enc_priv); + drm_encoder_cleanup(encoder); + kfree(amdgpu_encoder); +} + +static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = { + .destroy = dce_v8_0_encoder_destroy, +}; + +static void dce_v8_0_encoder_add(struct amdgpu_device *adev, + uint32_t encoder_enum, + uint32_t supported_device, + u16 caps) +{ + struct drm_device *dev = adev->ddev; + struct drm_encoder *encoder; + struct amdgpu_encoder *amdgpu_encoder; + + /* see if we already added it */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + amdgpu_encoder = to_amdgpu_encoder(encoder); + if (amdgpu_encoder->encoder_enum == encoder_enum) { + amdgpu_encoder->devices |= supported_device; + return; + } + + } + + /* add a new one */ + amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); + if (!amdgpu_encoder) + return; + + encoder = &amdgpu_encoder->base; + switch (adev->mode_info.num_crtc) { + case 1: + encoder->possible_crtcs = 0x1; + break; + case 2: + default: + encoder->possible_crtcs = 0x3; + break; + case 4: + encoder->possible_crtcs = 0xf; + break; + case 6: + encoder->possible_crtcs = 0x3f; + break; + } + + amdgpu_encoder->enc_priv = NULL; + + amdgpu_encoder->encoder_enum = encoder_enum; + amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; + amdgpu_encoder->devices = supported_device; + amdgpu_encoder->rmx_type = RMX_OFF; + amdgpu_encoder->underscan_type = UNDERSCAN_OFF; + amdgpu_encoder->is_ext_encoder = false; + amdgpu_encoder->caps = caps; + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, + DRM_MODE_ENCODER_DAC); + drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs); + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + amdgpu_encoder->rmx_type = RMX_FULL; + drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, + DRM_MODE_ENCODER_LVDS); + amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); + } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { + drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, + DRM_MODE_ENCODER_DAC); + amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); + } else { + drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, + DRM_MODE_ENCODER_TMDS); + amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); + } + drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs); + break; + case ENCODER_OBJECT_ID_SI170B: + case ENCODER_OBJECT_ID_CH7303: + case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: + case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: + case ENCODER_OBJECT_ID_TITFP513: + case ENCODER_OBJECT_ID_VT1623: + case ENCODER_OBJECT_ID_HDMI_SI1930: + case ENCODER_OBJECT_ID_TRAVIS: + case ENCODER_OBJECT_ID_NUTMEG: + /* these are handled by the primary encoders */ + amdgpu_encoder->is_ext_encoder = true; + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) + drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, + DRM_MODE_ENCODER_LVDS); + else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) + drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, + DRM_MODE_ENCODER_DAC); + else + drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, + DRM_MODE_ENCODER_TMDS); + drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs); + break; + } +} + +static const struct amdgpu_display_funcs dce_v8_0_display_funcs = { + .set_vga_render_state = &dce_v8_0_set_vga_render_state, + .bandwidth_update = &dce_v8_0_bandwidth_update, + .vblank_get_counter = &dce_v8_0_vblank_get_counter, + .vblank_wait = &dce_v8_0_vblank_wait, + .is_display_hung = &dce_v8_0_is_display_hung, + .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, + .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, + .hpd_sense = &dce_v8_0_hpd_sense, + .hpd_set_polarity = &dce_v8_0_hpd_set_polarity, + .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg, + .page_flip = &dce_v8_0_page_flip, + .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos, + .add_encoder = &dce_v8_0_encoder_add, + .add_connector = &amdgpu_connector_add, + .stop_mc_access = &dce_v8_0_stop_mc_access, + .resume_mc_access = &dce_v8_0_resume_mc_access, +}; + +static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev) +{ + if (adev->mode_info.funcs == NULL) + adev->mode_info.funcs = &dce_v8_0_display_funcs; +} + +static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = { + .set = dce_v8_0_set_crtc_interrupt_state, + .process = dce_v8_0_crtc_irq, +}; + +static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = { + .set = dce_v8_0_set_pageflip_interrupt_state, + .process = dce_v8_0_pageflip_irq, +}; + +static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = { + .set = dce_v8_0_set_hpd_interrupt_state, + .process = dce_v8_0_hpd_irq, +}; + +static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs; + + adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs; + + adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h new file mode 100644 index 000000000000..3a0a73b41041 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DCE_V8_0_H__ +#define __DCE_V8_0_H__ + +extern const struct amdgpu_ip_funcs dce_v8_0_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c new file mode 100644 index 000000000000..675b096417f4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -0,0 +1,5635 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_ih.h" +#include "amdgpu_gfx.h" +#include "cikd.h" +#include "cik.h" +#include "atom.h" +#include "amdgpu_ucode.h" +#include "clearstate_ci.h" + +#include "uvd/uvd_4_2_d.h" + +#include "dce/dce_8_0_d.h" +#include "dce/dce_8_0_sh_mask.h" + +#include "bif/bif_4_1_d.h" +#include "bif/bif_4_1_sh_mask.h" + +#include "gca/gfx_7_0_d.h" +#include "gca/gfx_7_2_enum.h" +#include "gca/gfx_7_2_sh_mask.h" + +#include "gmc/gmc_7_0_d.h" +#include "gmc/gmc_7_0_sh_mask.h" + +#include "oss/oss_2_0_d.h" +#include "oss/oss_2_0_sh_mask.h" + +#define GFX7_NUM_GFX_RINGS 1 +#define GFX7_NUM_COMPUTE_RINGS 8 + +static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); +static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); +static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); +int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *); + +MODULE_FIRMWARE("radeon/bonaire_pfp.bin"); +MODULE_FIRMWARE("radeon/bonaire_me.bin"); +MODULE_FIRMWARE("radeon/bonaire_ce.bin"); +MODULE_FIRMWARE("radeon/bonaire_rlc.bin"); +MODULE_FIRMWARE("radeon/bonaire_mec.bin"); + +MODULE_FIRMWARE("radeon/hawaii_pfp.bin"); +MODULE_FIRMWARE("radeon/hawaii_me.bin"); +MODULE_FIRMWARE("radeon/hawaii_ce.bin"); +MODULE_FIRMWARE("radeon/hawaii_rlc.bin"); +MODULE_FIRMWARE("radeon/hawaii_mec.bin"); + +MODULE_FIRMWARE("radeon/kaveri_pfp.bin"); +MODULE_FIRMWARE("radeon/kaveri_me.bin"); +MODULE_FIRMWARE("radeon/kaveri_ce.bin"); +MODULE_FIRMWARE("radeon/kaveri_rlc.bin"); +MODULE_FIRMWARE("radeon/kaveri_mec.bin"); +MODULE_FIRMWARE("radeon/kaveri_mec2.bin"); + +MODULE_FIRMWARE("radeon/kabini_pfp.bin"); +MODULE_FIRMWARE("radeon/kabini_me.bin"); +MODULE_FIRMWARE("radeon/kabini_ce.bin"); +MODULE_FIRMWARE("radeon/kabini_rlc.bin"); +MODULE_FIRMWARE("radeon/kabini_mec.bin"); + +MODULE_FIRMWARE("radeon/mullins_pfp.bin"); +MODULE_FIRMWARE("radeon/mullins_me.bin"); +MODULE_FIRMWARE("radeon/mullins_ce.bin"); +MODULE_FIRMWARE("radeon/mullins_rlc.bin"); +MODULE_FIRMWARE("radeon/mullins_mec.bin"); + +static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = +{ + {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, + {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, + {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, + {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, + {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, + {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, + {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, + {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, + {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, + {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, + {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, + {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, + {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, + {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, + {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, + {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} +}; + +static const u32 spectre_rlc_save_restore_register_list[] = +{ + (0x0e00 << 16) | (0xc12c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc140 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc150 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc15c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc168 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc170 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc178 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc204 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2b4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2b8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2bc >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2c0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8228 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x829c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x869c >> 2), + 0x00000000, + (0x0600 << 16) | (0x98f4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x98f8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9900 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc260 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x90e8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c000 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c00c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c1c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9700 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x4e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x5e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x6e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x7e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x8e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x9e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0xae00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0xbe00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x89bc >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8900 >> 2), + 0x00000000, + 0x3, + (0x0e00 << 16) | (0xc130 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc134 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc1fc >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc208 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc264 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc268 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc26c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc270 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc274 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc278 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc27c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc280 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc284 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc288 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc28c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc290 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc294 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc298 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc29c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2a0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2a4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2a8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2ac >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2b0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x301d0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30238 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30250 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30254 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30258 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3025c >> 2), + 0x00000000, + (0x4e00 << 16) | (0xc900 >> 2), + 0x00000000, + (0x5e00 << 16) | (0xc900 >> 2), + 0x00000000, + (0x6e00 << 16) | (0xc900 >> 2), + 0x00000000, + (0x7e00 << 16) | (0xc900 >> 2), + 0x00000000, + (0x8e00 << 16) | (0xc900 >> 2), + 0x00000000, + (0x9e00 << 16) | (0xc900 >> 2), + 0x00000000, + (0xae00 << 16) | (0xc900 >> 2), + 0x00000000, + (0xbe00 << 16) | (0xc900 >> 2), + 0x00000000, + (0x4e00 << 16) | (0xc904 >> 2), + 0x00000000, + (0x5e00 << 16) | (0xc904 >> 2), + 0x00000000, + (0x6e00 << 16) | (0xc904 >> 2), + 0x00000000, + (0x7e00 << 16) | (0xc904 >> 2), + 0x00000000, + (0x8e00 << 16) | (0xc904 >> 2), + 0x00000000, + (0x9e00 << 16) | (0xc904 >> 2), + 0x00000000, + (0xae00 << 16) | (0xc904 >> 2), + 0x00000000, + (0xbe00 << 16) | (0xc904 >> 2), + 0x00000000, + (0x4e00 << 16) | (0xc908 >> 2), + 0x00000000, + (0x5e00 << 16) | (0xc908 >> 2), + 0x00000000, + (0x6e00 << 16) | (0xc908 >> 2), + 0x00000000, + (0x7e00 << 16) | (0xc908 >> 2), + 0x00000000, + (0x8e00 << 16) | (0xc908 >> 2), + 0x00000000, + (0x9e00 << 16) | (0xc908 >> 2), + 0x00000000, + (0xae00 << 16) | (0xc908 >> 2), + 0x00000000, + (0xbe00 << 16) | (0xc908 >> 2), + 0x00000000, + (0x4e00 << 16) | (0xc90c >> 2), + 0x00000000, + (0x5e00 << 16) | (0xc90c >> 2), + 0x00000000, + (0x6e00 << 16) | (0xc90c >> 2), + 0x00000000, + (0x7e00 << 16) | (0xc90c >> 2), + 0x00000000, + (0x8e00 << 16) | (0xc90c >> 2), + 0x00000000, + (0x9e00 << 16) | (0xc90c >> 2), + 0x00000000, + (0xae00 << 16) | (0xc90c >> 2), + 0x00000000, + (0xbe00 << 16) | (0xc90c >> 2), + 0x00000000, + (0x4e00 << 16) | (0xc910 >> 2), + 0x00000000, + (0x5e00 << 16) | (0xc910 >> 2), + 0x00000000, + (0x6e00 << 16) | (0xc910 >> 2), + 0x00000000, + (0x7e00 << 16) | (0xc910 >> 2), + 0x00000000, + (0x8e00 << 16) | (0xc910 >> 2), + 0x00000000, + (0x9e00 << 16) | (0xc910 >> 2), + 0x00000000, + (0xae00 << 16) | (0xc910 >> 2), + 0x00000000, + (0xbe00 << 16) | (0xc910 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc99c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9834 >> 2), + 0x00000000, + (0x0000 << 16) | (0x30f00 >> 2), + 0x00000000, + (0x0001 << 16) | (0x30f00 >> 2), + 0x00000000, + (0x0000 << 16) | (0x30f04 >> 2), + 0x00000000, + (0x0001 << 16) | (0x30f04 >> 2), + 0x00000000, + (0x0000 << 16) | (0x30f08 >> 2), + 0x00000000, + (0x0001 << 16) | (0x30f08 >> 2), + 0x00000000, + (0x0000 << 16) | (0x30f0c >> 2), + 0x00000000, + (0x0001 << 16) | (0x30f0c >> 2), + 0x00000000, + (0x0600 << 16) | (0x9b7c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8a14 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8a18 >> 2), + 0x00000000, + (0x0600 << 16) | (0x30a00 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8bf0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8bcc >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8b24 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30a04 >> 2), + 0x00000000, + (0x0600 << 16) | (0x30a10 >> 2), + 0x00000000, + (0x0600 << 16) | (0x30a14 >> 2), + 0x00000000, + (0x0600 << 16) | (0x30a18 >> 2), + 0x00000000, + (0x0600 << 16) | (0x30a2c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc700 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc704 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc708 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc768 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc770 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc774 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc778 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc77c >> 2), + 0x00000000, + (0x0400 << 16) | (0xc780 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc784 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc788 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc78c >> 2), + 0x00000000, + (0x0400 << 16) | (0xc798 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc79c >> 2), + 0x00000000, + (0x0400 << 16) | (0xc7a0 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc7a4 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc7a8 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc7ac >> 2), + 0x00000000, + (0x0400 << 16) | (0xc7b0 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc7b4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9100 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c010 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x92a8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x92ac >> 2), + 0x00000000, + (0x0e00 << 16) | (0x92b4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x92b8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x92bc >> 2), + 0x00000000, + (0x0e00 << 16) | (0x92c0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x92c4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x92c8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x92cc >> 2), + 0x00000000, + (0x0e00 << 16) | (0x92d0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c00 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c04 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c20 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c38 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c3c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xae00 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9604 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac08 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac0c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac10 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac14 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac58 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac68 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac6c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac70 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac74 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac78 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac7c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac80 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac84 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac88 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac8c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x970c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9714 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9718 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x971c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x4e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x5e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x6e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x7e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x8e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x9e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0xae00 << 16) | (0x31068 >> 2), + 0x00000000, + (0xbe00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xcd10 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xcd14 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88b0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88b4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88b8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88bc >> 2), + 0x00000000, + (0x0400 << 16) | (0x89c0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88c4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88c8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88d0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88d4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88d8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8980 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30938 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3093c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30940 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x89a0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30900 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30904 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x89b4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c210 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c214 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c218 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8904 >> 2), + 0x00000000, + 0x5, + (0x0e00 << 16) | (0x8c28 >> 2), + (0x0e00 << 16) | (0x8c2c >> 2), + (0x0e00 << 16) | (0x8c30 >> 2), + (0x0e00 << 16) | (0x8c34 >> 2), + (0x0e00 << 16) | (0x9600 >> 2), +}; + +static const u32 kalindi_rlc_save_restore_register_list[] = +{ + (0x0e00 << 16) | (0xc12c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc140 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc150 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc15c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc168 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc170 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc204 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2b4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2b8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2bc >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2c0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8228 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x829c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x869c >> 2), + 0x00000000, + (0x0600 << 16) | (0x98f4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x98f8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9900 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc260 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x90e8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c000 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c00c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c1c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9700 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x4e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x5e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x6e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x7e00 << 16) | (0xcd20 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x89bc >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8900 >> 2), + 0x00000000, + 0x3, + (0x0e00 << 16) | (0xc130 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc134 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc1fc >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc208 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc264 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc268 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc26c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc270 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc274 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc28c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc290 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc294 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc298 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2a0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2a4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2a8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc2ac >> 2), + 0x00000000, + (0x0e00 << 16) | (0x301d0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30238 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30250 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30254 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30258 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3025c >> 2), + 0x00000000, + (0x4e00 << 16) | (0xc900 >> 2), + 0x00000000, + (0x5e00 << 16) | (0xc900 >> 2), + 0x00000000, + (0x6e00 << 16) | (0xc900 >> 2), + 0x00000000, + (0x7e00 << 16) | (0xc900 >> 2), + 0x00000000, + (0x4e00 << 16) | (0xc904 >> 2), + 0x00000000, + (0x5e00 << 16) | (0xc904 >> 2), + 0x00000000, + (0x6e00 << 16) | (0xc904 >> 2), + 0x00000000, + (0x7e00 << 16) | (0xc904 >> 2), + 0x00000000, + (0x4e00 << 16) | (0xc908 >> 2), + 0x00000000, + (0x5e00 << 16) | (0xc908 >> 2), + 0x00000000, + (0x6e00 << 16) | (0xc908 >> 2), + 0x00000000, + (0x7e00 << 16) | (0xc908 >> 2), + 0x00000000, + (0x4e00 << 16) | (0xc90c >> 2), + 0x00000000, + (0x5e00 << 16) | (0xc90c >> 2), + 0x00000000, + (0x6e00 << 16) | (0xc90c >> 2), + 0x00000000, + (0x7e00 << 16) | (0xc90c >> 2), + 0x00000000, + (0x4e00 << 16) | (0xc910 >> 2), + 0x00000000, + (0x5e00 << 16) | (0xc910 >> 2), + 0x00000000, + (0x6e00 << 16) | (0xc910 >> 2), + 0x00000000, + (0x7e00 << 16) | (0xc910 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc99c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9834 >> 2), + 0x00000000, + (0x0000 << 16) | (0x30f00 >> 2), + 0x00000000, + (0x0000 << 16) | (0x30f04 >> 2), + 0x00000000, + (0x0000 << 16) | (0x30f08 >> 2), + 0x00000000, + (0x0000 << 16) | (0x30f0c >> 2), + 0x00000000, + (0x0600 << 16) | (0x9b7c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8a14 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8a18 >> 2), + 0x00000000, + (0x0600 << 16) | (0x30a00 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8bf0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8bcc >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8b24 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30a04 >> 2), + 0x00000000, + (0x0600 << 16) | (0x30a10 >> 2), + 0x00000000, + (0x0600 << 16) | (0x30a14 >> 2), + 0x00000000, + (0x0600 << 16) | (0x30a18 >> 2), + 0x00000000, + (0x0600 << 16) | (0x30a2c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc700 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc704 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc708 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xc768 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc770 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc774 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc798 >> 2), + 0x00000000, + (0x0400 << 16) | (0xc79c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9100 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c010 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c00 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c04 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c20 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c38 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8c3c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xae00 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9604 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac08 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac0c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac10 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac14 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac58 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac68 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac6c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac70 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac74 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac78 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac7c >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac80 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac84 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac88 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xac8c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x970c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9714 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x9718 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x971c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x4e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x5e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x6e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x7e00 << 16) | (0x31068 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xcd10 >> 2), + 0x00000000, + (0x0e00 << 16) | (0xcd14 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88b0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88b4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88b8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88bc >> 2), + 0x00000000, + (0x0400 << 16) | (0x89c0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88c4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88c8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88d0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88d4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x88d8 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8980 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30938 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3093c >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30940 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x89a0 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30900 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x30904 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x89b4 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3e1fc >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c210 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c214 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x3c218 >> 2), + 0x00000000, + (0x0e00 << 16) | (0x8904 >> 2), + 0x00000000, + 0x5, + (0x0e00 << 16) | (0x8c28 >> 2), + (0x0e00 << 16) | (0x8c2c >> 2), + (0x0e00 << 16) | (0x8c30 >> 2), + (0x0e00 << 16) | (0x8c34 >> 2), + (0x0e00 << 16) | (0x9600 >> 2), +}; + +static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); +static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); +static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev); +static void gfx_v7_0_init_pg(struct amdgpu_device *adev); + +/* + * Core functions + */ +/** + * gfx_v7_0_init_microcode - load ucode images from disk + * + * @adev: amdgpu_device pointer + * + * Use the firmware interface to load the ucode images into + * the driver (not loaded into hw). + * Returns 0 on success, error on failure. + */ +static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) +{ + const char *chip_name; + char fw_name[30]; + int err; + + DRM_DEBUG("\n"); + + switch (adev->asic_type) { + case CHIP_BONAIRE: + chip_name = "bonaire"; + break; + case CHIP_HAWAII: + chip_name = "hawaii"; + break; + case CHIP_KAVERI: + chip_name = "kaveri"; + break; + case CHIP_KABINI: + chip_name = "kabini"; + break; + case CHIP_MULLINS: + chip_name = "mullins"; + break; + default: BUG(); + } + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); + err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.pfp_fw); + if (err) + goto out; + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); + err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.me_fw); + if (err) + goto out; + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); + err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.ce_fw); + if (err) + goto out; + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name); + err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.mec_fw); + if (err) + goto out; + + if (adev->asic_type == CHIP_KAVERI) { + snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name); + err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.mec2_fw); + if (err) + goto out; + } + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); + err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.rlc_fw); + +out: + if (err) { + printk(KERN_ERR + "gfx7: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(adev->gfx.pfp_fw); + adev->gfx.pfp_fw = NULL; + release_firmware(adev->gfx.me_fw); + adev->gfx.me_fw = NULL; + release_firmware(adev->gfx.ce_fw); + adev->gfx.ce_fw = NULL; + release_firmware(adev->gfx.mec_fw); + adev->gfx.mec_fw = NULL; + release_firmware(adev->gfx.mec2_fw); + adev->gfx.mec2_fw = NULL; + release_firmware(adev->gfx.rlc_fw); + adev->gfx.rlc_fw = NULL; + } + return err; +} + +/** + * gfx_v7_0_tiling_mode_table_init - init the hw tiling table + * + * @adev: amdgpu_device pointer + * + * Starting with SI, the tiling setup is done globally in a + * set of 32 tiling modes. Rather than selecting each set of + * parameters per surface as on older asics, we just select + * which index in the tiling table we want to use, and the + * surface uses those parameters (CIK). + */ +static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) +{ + const u32 num_tile_mode_states = 32; + const u32 num_secondary_tile_mode_states = 16; + u32 reg_offset, gb_tile_moden, split_equal_to_row_size; + + switch (adev->gfx.config.mem_row_size_in_kb) { + case 1: + split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; + break; + case 2: + default: + split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; + break; + case 4: + split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; + break; + } + + switch (adev->asic_type) { + case CHIP_BONAIRE: + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 1: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 2: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 3: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 4: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | + TILE_SPLIT(split_equal_to_row_size)); + break; + case 5: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 6: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | + TILE_SPLIT(split_equal_to_row_size)); + break; + case 7: + gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); + break; + + case 8: + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P4_16x16)); + break; + case 9: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); + break; + case 10: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 11: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 12: + gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); + break; + case 13: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); + break; + case 14: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 15: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 16: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 17: + gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); + break; + case 18: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 19: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); + break; + case 20: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 21: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 22: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 23: + gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); + break; + case 24: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 25: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 26: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 27: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); + break; + case 28: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 29: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 30: + gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); + break; + default: + gb_tile_moden = 0; + break; + } + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); + } + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 1: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 2: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 3: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 4: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 5: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 6: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK)); + break; + case 8: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 9: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 10: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 11: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 12: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 13: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 14: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK)); + break; + default: + gb_tile_moden = 0; + break; + } + adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); + } + break; + case CHIP_HAWAII: + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 1: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 2: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 3: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 4: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | + TILE_SPLIT(split_equal_to_row_size)); + break; + case 5: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | + TILE_SPLIT(split_equal_to_row_size)); + break; + case 6: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | + TILE_SPLIT(split_equal_to_row_size)); + break; + case 7: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | + TILE_SPLIT(split_equal_to_row_size)); + break; + + case 8: + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); + break; + case 9: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); + break; + case 10: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 11: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 12: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 13: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); + break; + case 14: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 15: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 16: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 17: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 18: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 19: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); + break; + case 20: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 21: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 22: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 23: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 24: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 25: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 26: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 27: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); + break; + case 28: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 29: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 30: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + default: + gb_tile_moden = 0; + break; + } + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); + } + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 1: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 2: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 3: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 4: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 5: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK)); + break; + case 6: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK)); + break; + case 8: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 9: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 10: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 11: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 12: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 13: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 14: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK)); + break; + default: + gb_tile_moden = 0; + break; + } + adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); + } + break; + case CHIP_KABINI: + case CHIP_KAVERI: + case CHIP_MULLINS: + default: + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 1: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 2: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 3: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 4: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | + TILE_SPLIT(split_equal_to_row_size)); + break; + case 5: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 6: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | + TILE_SPLIT(split_equal_to_row_size)); + break; + case 7: + gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); + break; + + case 8: + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P2)); + break; + case 9: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); + break; + case 10: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 11: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 12: + gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); + break; + case 13: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); + break; + case 14: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 15: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 16: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 17: + gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); + break; + case 18: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 19: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); + break; + case 20: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 21: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 22: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 23: + gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); + break; + case 24: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 25: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 26: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 27: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); + break; + case 28: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 29: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 30: + gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); + break; + default: + gb_tile_moden = 0; + break; + } + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); + } + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 1: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 2: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 3: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 4: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 5: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 6: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 8: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 9: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 10: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 11: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 12: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 13: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 14: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + default: + gb_tile_moden = 0; + break; + } + adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); + } + break; + } +} + +/** + * gfx_v7_0_select_se_sh - select which SE, SH to address + * + * @adev: amdgpu_device pointer + * @se_num: shader engine to address + * @sh_num: sh block to address + * + * Select which SE, SH combinations to address. Certain + * registers are instanced per SE or SH. 0xffffffff means + * broadcast to all SEs or SHs (CIK). + */ +void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num) +{ + u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK; + + if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) + data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | + GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; + else if (se_num == 0xffffffff) + data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | + (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); + else if (sh_num == 0xffffffff) + data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | + (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); + else + data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | + (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); + WREG32(mmGRBM_GFX_INDEX, data); +} + +/** + * gfx_v7_0_create_bitmask - create a bitmask + * + * @bit_width: length of the mask + * + * create a variable length bit mask (CIK). + * Returns the bitmask. + */ +static u32 gfx_v7_0_create_bitmask(u32 bit_width) +{ + u32 i, mask = 0; + + for (i = 0; i < bit_width; i++) { + mask <<= 1; + mask |= 1; + } + return mask; +} + +/** + * gfx_v7_0_get_rb_disabled - computes the mask of disabled RBs + * + * @adev: amdgpu_device pointer + * @max_rb_num: max RBs (render backends) for the asic + * @se_num: number of SEs (shader engines) for the asic + * @sh_per_se: number of SH blocks per SE for the asic + * + * Calculates the bitmask of disabled RBs (CIK). + * Returns the disabled RB bitmask. + */ +static u32 gfx_v7_0_get_rb_disabled(struct amdgpu_device *adev, + u32 max_rb_num_per_se, + u32 sh_per_se) +{ + u32 data, mask; + + data = RREG32(mmCC_RB_BACKEND_DISABLE); + if (data & 1) + data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; + else + data = 0; + + data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); + + data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; + + mask = gfx_v7_0_create_bitmask(max_rb_num_per_se / sh_per_se); + + return data & mask; +} + +/** + * gfx_v7_0_setup_rb - setup the RBs on the asic + * + * @adev: amdgpu_device pointer + * @se_num: number of SEs (shader engines) for the asic + * @sh_per_se: number of SH blocks per SE for the asic + * @max_rb_num: max RBs (render backends) for the asic + * + * Configures per-SE/SH RB registers (CIK). + */ +static void gfx_v7_0_setup_rb(struct amdgpu_device *adev, + u32 se_num, u32 sh_per_se, + u32 max_rb_num_per_se) +{ + int i, j; + u32 data, mask; + u32 disabled_rbs = 0; + u32 enabled_rbs = 0; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < se_num; i++) { + for (j = 0; j < sh_per_se; j++) { + gfx_v7_0_select_se_sh(adev, i, j); + data = gfx_v7_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se); + if (adev->asic_type == CHIP_HAWAII) + disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH); + else + disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH); + } + } + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + + mask = 1; + for (i = 0; i < max_rb_num_per_se * se_num; i++) { + if (!(disabled_rbs & mask)) + enabled_rbs |= mask; + mask <<= 1; + } + + adev->gfx.config.backend_enable_mask = enabled_rbs; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < se_num; i++) { + gfx_v7_0_select_se_sh(adev, i, 0xffffffff); + data = 0; + for (j = 0; j < sh_per_se; j++) { + switch (enabled_rbs & 3) { + case 0: + if (j == 0) + data |= (RASTER_CONFIG_RB_MAP_3 << + PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT); + else + data |= (RASTER_CONFIG_RB_MAP_0 << + PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT); + break; + case 1: + data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2); + break; + case 2: + data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2); + break; + case 3: + default: + data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2); + break; + } + enabled_rbs >>= 2; + } + WREG32(mmPA_SC_RASTER_CONFIG, data); + } + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); +} + +/** + * gfx_v7_0_gpu_init - setup the 3D engine + * + * @adev: amdgpu_device pointer + * + * Configures the 3D engine and tiling configuration + * registers so that the 3D engine is usable. + */ +static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) +{ + u32 gb_addr_config; + u32 mc_shared_chmap, mc_arb_ramcfg; + u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; + u32 tmp; + int i; + + switch (adev->asic_type) { + case CHIP_BONAIRE: + adev->gfx.config.max_shader_engines = 2; + adev->gfx.config.max_tile_pipes = 4; + adev->gfx.config.max_cu_per_sh = 7; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 2; + adev->gfx.config.max_texture_channel_caches = 4; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_HAWAII: + adev->gfx.config.max_shader_engines = 4; + adev->gfx.config.max_tile_pipes = 16; + adev->gfx.config.max_cu_per_sh = 11; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 4; + adev->gfx.config.max_texture_channel_caches = 16; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_KAVERI: + adev->gfx.config.max_shader_engines = 1; + adev->gfx.config.max_tile_pipes = 4; + if ((adev->pdev->device == 0x1304) || + (adev->pdev->device == 0x1305) || + (adev->pdev->device == 0x130C) || + (adev->pdev->device == 0x130F) || + (adev->pdev->device == 0x1310) || + (adev->pdev->device == 0x1311) || + (adev->pdev->device == 0x131C)) { + adev->gfx.config.max_cu_per_sh = 8; + adev->gfx.config.max_backends_per_se = 2; + } else if ((adev->pdev->device == 0x1309) || + (adev->pdev->device == 0x130A) || + (adev->pdev->device == 0x130D) || + (adev->pdev->device == 0x1313) || + (adev->pdev->device == 0x131D)) { + adev->gfx.config.max_cu_per_sh = 6; + adev->gfx.config.max_backends_per_se = 2; + } else if ((adev->pdev->device == 0x1306) || + (adev->pdev->device == 0x1307) || + (adev->pdev->device == 0x130B) || + (adev->pdev->device == 0x130E) || + (adev->pdev->device == 0x1315) || + (adev->pdev->device == 0x131B)) { + adev->gfx.config.max_cu_per_sh = 4; + adev->gfx.config.max_backends_per_se = 1; + } else { + adev->gfx.config.max_cu_per_sh = 3; + adev->gfx.config.max_backends_per_se = 1; + } + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_texture_channel_caches = 4; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 16; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_KABINI: + case CHIP_MULLINS: + default: + adev->gfx.config.max_shader_engines = 1; + adev->gfx.config.max_tile_pipes = 2; + adev->gfx.config.max_cu_per_sh = 2; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 1; + adev->gfx.config.max_texture_channel_caches = 2; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 16; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; + break; + } + + WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); + + mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); + adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); + mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; + + adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; + adev->gfx.config.mem_max_burst_length_bytes = 256; + if (adev->flags & AMDGPU_IS_APU) { + /* Get memory bank mapping mode. */ + tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); + dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); + dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); + + tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); + dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); + dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); + + /* Validate settings in case only one DIMM installed. */ + if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) + dimm00_addr_map = 0; + if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) + dimm01_addr_map = 0; + if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) + dimm10_addr_map = 0; + if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) + dimm11_addr_map = 0; + + /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ + /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ + if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) + adev->gfx.config.mem_row_size_in_kb = 2; + else + adev->gfx.config.mem_row_size_in_kb = 1; + } else { + tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; + adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; + if (adev->gfx.config.mem_row_size_in_kb > 4) + adev->gfx.config.mem_row_size_in_kb = 4; + } + /* XXX use MC settings? */ + adev->gfx.config.shader_engine_tile_size = 32; + adev->gfx.config.num_gpus = 1; + adev->gfx.config.multi_gpu_tile_size = 64; + + /* fix up row size */ + gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; + switch (adev->gfx.config.mem_row_size_in_kb) { + case 1: + default: + gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); + break; + case 2: + gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); + break; + case 4: + gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); + break; + } + adev->gfx.config.gb_addr_config = gb_addr_config; + + WREG32(mmGB_ADDR_CONFIG, gb_addr_config); + WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); + WREG32(mmDMIF_ADDR_CALC, gb_addr_config); + WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); + WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); + WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); + WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); + WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); + + gfx_v7_0_tiling_mode_table_init(adev); + + gfx_v7_0_setup_rb(adev, adev->gfx.config.max_shader_engines, + adev->gfx.config.max_sh_per_se, + adev->gfx.config.max_backends_per_se); + + /* set HW defaults for 3D engine */ + WREG32(mmCP_MEQ_THRESHOLDS, + (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | + (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); + + mutex_lock(&adev->grbm_idx_mutex); + /* + * making sure that the following register writes will be broadcasted + * to all the shaders + */ + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + + /* XXX SH_MEM regs */ + /* where to put LDS, scratch, GPUVM in FSA64 space */ + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < 16; i++) { + cik_srbm_select(adev, 0, 0, 0, i); + /* CP and shaders */ + WREG32(mmSH_MEM_CONFIG, 0); + WREG32(mmSH_MEM_APE1_BASE, 1); + WREG32(mmSH_MEM_APE1_LIMIT, 0); + WREG32(mmSH_MEM_BASES, 0); + } + cik_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + WREG32(mmSX_DEBUG_1, 0x20); + + WREG32(mmTA_CNTL_AUX, 0x00010000); + + tmp = RREG32(mmSPI_CONFIG_CNTL); + tmp |= 0x03000000; + WREG32(mmSPI_CONFIG_CNTL, tmp); + + WREG32(mmSQ_CONFIG, 1); + + WREG32(mmDB_DEBUG, 0); + + tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; + tmp |= 0x00000400; + WREG32(mmDB_DEBUG2, tmp); + + tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; + tmp |= 0x00020200; + WREG32(mmDB_DEBUG3, tmp); + + tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; + tmp |= 0x00018208; + WREG32(mmCB_HW_CONTROL, tmp); + + WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); + + WREG32(mmPA_SC_FIFO_SIZE, + ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); + + WREG32(mmVGT_NUM_INSTANCES, 1); + + WREG32(mmCP_PERFMON_CNTL, 0); + + WREG32(mmSQ_CONFIG, 0); + + WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, + ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | + (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); + + WREG32(mmVGT_CACHE_INVALIDATION, + (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | + (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); + + WREG32(mmVGT_GS_VERTEX_REUSE, 16); + WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); + + WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | + (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); + WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); + mutex_unlock(&adev->grbm_idx_mutex); + + udelay(50); +} + +/* + * GPU scratch registers helpers function. + */ +/** + * gfx_v7_0_scratch_init - setup driver info for CP scratch regs + * + * @adev: amdgpu_device pointer + * + * Set up the number and offset of the CP scratch registers. + * NOTE: use of CP scratch registers is a legacy inferface and + * is not used by default on newer asics (r6xx+). On newer asics, + * memory buffers are used for fences rather than scratch regs. + */ +static void gfx_v7_0_scratch_init(struct amdgpu_device *adev) +{ + int i; + + adev->gfx.scratch.num_reg = 7; + adev->gfx.scratch.reg_base = mmSCRATCH_REG0; + for (i = 0; i < adev->gfx.scratch.num_reg; i++) { + adev->gfx.scratch.free[i] = true; + adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; + } +} + +/** + * gfx_v7_0_ring_test_ring - basic gfx ring test + * + * @adev: amdgpu_device pointer + * @ring: amdgpu_ring structure holding ring information + * + * Allocate a scratch register and write to it using the gfx ring (CIK). + * Provides a basic gfx ring test to verify that the ring is working. + * Used by gfx_v7_0_cp_gfx_resume(); + * Returns 0 on success, error on failure. + */ +static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = amdgpu_gfx_scratch_get(adev, &scratch); + if (r) { + DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = amdgpu_ring_lock(ring, 3); + if (r) { + DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r); + amdgpu_gfx_scratch_free(adev, scratch); + return r; + } + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); + amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_unlock_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", + ring->idx, scratch, tmp); + r = -EINVAL; + } + amdgpu_gfx_scratch_free(adev, scratch); + return r; +} + +/** + * gfx_v7_0_hdp_flush_cp_ring_emit - emit an hdp flush on the cp + * + * @adev: amdgpu_device pointer + * @ridx: amdgpu ring index + * + * Emits an hdp flush on the cp. + */ +static void gfx_v7_0_hdp_flush_cp_ring_emit(struct amdgpu_ring *ring) +{ + u32 ref_and_mask; + + if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { + switch (ring->me) { + case 1: + ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; + break; + case 2: + ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; + break; + default: + return; + } + } else { + ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; + } + + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ + WAIT_REG_MEM_FUNCTION(3) | /* == */ + WAIT_REG_MEM_ENGINE(1))); /* pfp */ + amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); + amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); + amdgpu_ring_write(ring, ref_and_mask); + amdgpu_ring_write(ring, ref_and_mask); + amdgpu_ring_write(ring, 0x20); /* poll interval */ +} + +/** + * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring + * + * @adev: amdgpu_device pointer + * @fence: amdgpu fence object + * + * Emits a fence sequnce number on the gfx ring and flushes + * GPU caches. + */ +static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, + u64 seq, bool write64bit) +{ + /* Workaround for cache flush problems. First send a dummy EOP + * event down the pipe with seq one below. + */ + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); + amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | + EOP_TC_ACTION_EN | + EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | + EVENT_INDEX(5))); + amdgpu_ring_write(ring, addr & 0xfffffffc); + amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | + DATA_SEL(1) | INT_SEL(0)); + amdgpu_ring_write(ring, lower_32_bits(seq - 1)); + amdgpu_ring_write(ring, upper_32_bits(seq - 1)); + + /* Then send the real EOP event down the pipe. */ + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); + amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | + EOP_TC_ACTION_EN | + EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | + EVENT_INDEX(5))); + amdgpu_ring_write(ring, addr & 0xfffffffc); + amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | + DATA_SEL(write64bit ? 2 : 1) | INT_SEL(2)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + amdgpu_ring_write(ring, upper_32_bits(seq)); +} + +/** + * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring + * + * @adev: amdgpu_device pointer + * @fence: amdgpu fence object + * + * Emits a fence sequnce number on the compute ring and flushes + * GPU caches. + */ +static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, + u64 addr, u64 seq, + bool write64bits) +{ + /* RELEASE_MEM - flush caches, send int */ + amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); + amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | + EOP_TC_ACTION_EN | + EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | + EVENT_INDEX(5))); + amdgpu_ring_write(ring, DATA_SEL(write64bits ? 2 : 1) | INT_SEL(2)); + amdgpu_ring_write(ring, addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + amdgpu_ring_write(ring, upper_32_bits(seq)); +} + +/** + * gfx_v7_0_ring_emit_semaphore - emit a semaphore on the CP ring + * + * @ring: amdgpu ring buffer object + * @semaphore: amdgpu semaphore object + * @emit_wait: Is this a sempahore wait? + * + * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP + * from running ahead of semaphore waits. + */ +static bool gfx_v7_0_ring_emit_semaphore(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore, + bool emit_wait) +{ + uint64_t addr = semaphore->gpu_addr; + unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; + + amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); + amdgpu_ring_write(ring, addr & 0xffffffff); + amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); + + if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) { + /* Prevent the PFP from running ahead of the semaphore wait */ + amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); + amdgpu_ring_write(ring, 0x0); + } + + return true; +} + +/* + * IB stuff + */ +/** + * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring + * + * @ring: amdgpu_ring structure holding ring information + * @ib: amdgpu indirect buffer object + * + * Emits an DE (drawing engine) or CE (constant engine) IB + * on the gfx ring. IBs are usually generated by userspace + * acceleration drivers and submitted to the kernel for + * sheduling on the ring. This function schedules the IB + * on the gfx ring for execution by the GPU. + */ +static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib) +{ + u32 header, control = 0; + u32 next_rptr = ring->wptr + 5; + if (ring->type == AMDGPU_RING_TYPE_COMPUTE) + control |= INDIRECT_BUFFER_VALID; + + if (ib->flush_hdp_writefifo) + next_rptr += 7; + + if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) + next_rptr += 2; + + next_rptr += 4; + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); + amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); + amdgpu_ring_write(ring, next_rptr); + + if (ib->flush_hdp_writefifo) + gfx_v7_0_hdp_flush_cp_ring_emit(ring); + + /* insert SWITCH_BUFFER packet before first IB in the ring frame */ + if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) { + amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); + amdgpu_ring_write(ring, 0); + ring->need_ctx_switch = false; + } + + if (ib->is_const_ib) + header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); + else + header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); + + control |= ib->length_dw | + (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0); + + amdgpu_ring_write(ring, header); + amdgpu_ring_write(ring, +#ifdef __BIG_ENDIAN + (2 << 0) | +#endif + (ib->gpu_addr & 0xFFFFFFFC)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); + amdgpu_ring_write(ring, control); +} + +/** + * gfx_v7_0_ring_test_ib - basic ring IB test + * + * @ring: amdgpu_ring structure holding ring information + * + * Allocate an IB and execute it on the gfx ring (CIK). + * Provides a basic gfx ring test to verify that IBs are working. + * Returns 0 on success, error on failure. + */ +static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_ib ib; + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = amdgpu_gfx_scratch_get(adev, &scratch); + if (r) { + DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = amdgpu_ib_get(ring, NULL, 256, &ib); + if (r) { + DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); + amdgpu_gfx_scratch_free(adev, scratch); + return r; + } + ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); + ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); + ib.ptr[2] = 0xDEADBEEF; + ib.length_dw = 3; + r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); + if (r) { + amdgpu_gfx_scratch_free(adev, scratch); + amdgpu_ib_free(adev, &ib); + DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); + return r; + } + r = amdgpu_fence_wait(ib.fence, false); + if (r) { + DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + amdgpu_gfx_scratch_free(adev, scratch); + amdgpu_ib_free(adev, &ib); + return r; + } + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < adev->usec_timeout) { + DRM_INFO("ib test on ring %d succeeded in %u usecs\n", + ib.fence->ring->idx, i); + } else { + DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + amdgpu_gfx_scratch_free(adev, scratch); + amdgpu_ib_free(adev, &ib); + return r; +} + +/* + * CP. + * On CIK, gfx and compute now have independant command processors. + * + * GFX + * Gfx consists of a single ring and can process both gfx jobs and + * compute jobs. The gfx CP consists of three microengines (ME): + * PFP - Pre-Fetch Parser + * ME - Micro Engine + * CE - Constant Engine + * The PFP and ME make up what is considered the Drawing Engine (DE). + * The CE is an asynchronous engine used for updating buffer desciptors + * used by the DE so that they can be loaded into cache in parallel + * while the DE is processing state update packets. + * + * Compute + * The compute CP consists of two microengines (ME): + * MEC1 - Compute MicroEngine 1 + * MEC2 - Compute MicroEngine 2 + * Each MEC supports 4 compute pipes and each pipe supports 8 queues. + * The queues are exposed to userspace and are programmed directly + * by the compute runtime. + */ +/** + * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs + * + * @adev: amdgpu_device pointer + * @enable: enable or disable the MEs + * + * Halts or unhalts the gfx MEs. + */ +static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) +{ + int i; + + if (enable) { + WREG32(mmCP_ME_CNTL, 0); + } else { + WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK)); + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + adev->gfx.gfx_ring[i].ready = false; + } + udelay(50); +} + +/** + * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode + * + * @adev: amdgpu_device pointer + * + * Loads the gfx PFP, ME, and CE ucode. + * Returns 0 for success, -EINVAL if the ucode is not available. + */ +static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) +{ + const struct gfx_firmware_header_v1_0 *pfp_hdr; + const struct gfx_firmware_header_v1_0 *ce_hdr; + const struct gfx_firmware_header_v1_0 *me_hdr; + const __le32 *fw_data; + unsigned i, fw_size; + + if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) + return -EINVAL; + + pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; + ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; + me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; + + amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); + amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); + amdgpu_ucode_print_gfx_hdr(&me_hdr->header); + adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); + adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); + adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); + + gfx_v7_0_cp_gfx_enable(adev, false); + + /* PFP */ + fw_data = (const __le32 *) + (adev->gfx.pfp_fw->data + + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; + WREG32(mmCP_PFP_UCODE_ADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); + + /* CE */ + fw_data = (const __le32 *) + (adev->gfx.ce_fw->data + + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; + WREG32(mmCP_CE_UCODE_ADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); + + /* ME */ + fw_data = (const __le32 *) + (adev->gfx.me_fw->data + + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; + WREG32(mmCP_ME_RAM_WADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); + + return 0; +} + +/** + * gfx_v7_0_cp_gfx_start - start the gfx ring + * + * @adev: amdgpu_device pointer + * + * Enables the ring and loads the clear state context and other + * packets required to init the ring. + * Returns 0 for success, error for failure. + */ +static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + int r, i; + + /* init the CP */ + WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); + WREG32(mmCP_ENDIAN_SWAP, 0); + WREG32(mmCP_DEVICE_ID, 1); + + gfx_v7_0_cp_gfx_enable(adev, true); + + r = amdgpu_ring_lock(ring, gfx_v7_0_get_csb_size(adev) + 8); + if (r) { + DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + return r; + } + + /* init the CE partitions. CE only used for gfx on CIK */ + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); + amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); + amdgpu_ring_write(ring, 0x8000); + amdgpu_ring_write(ring, 0x8000); + + /* clear state buffer */ + amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); + + amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); + amdgpu_ring_write(ring, 0x80000000); + amdgpu_ring_write(ring, 0x80000000); + + for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { + for (ext = sect->section; ext->extent != NULL; ++ext) { + if (sect->id == SECT_CONTEXT) { + amdgpu_ring_write(ring, + PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); + amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); + for (i = 0; i < ext->reg_count; i++) + amdgpu_ring_write(ring, ext->extent[i]); + } + } + } + + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); + switch (adev->asic_type) { + case CHIP_BONAIRE: + amdgpu_ring_write(ring, 0x16000012); + amdgpu_ring_write(ring, 0x00000000); + break; + case CHIP_KAVERI: + amdgpu_ring_write(ring, 0x00000000); /* XXX */ + amdgpu_ring_write(ring, 0x00000000); + break; + case CHIP_KABINI: + case CHIP_MULLINS: + amdgpu_ring_write(ring, 0x00000000); /* XXX */ + amdgpu_ring_write(ring, 0x00000000); + break; + case CHIP_HAWAII: + amdgpu_ring_write(ring, 0x3a00161a); + amdgpu_ring_write(ring, 0x0000002e); + break; + default: + amdgpu_ring_write(ring, 0x00000000); + amdgpu_ring_write(ring, 0x00000000); + break; + } + + amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); + + amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + amdgpu_ring_write(ring, 0x00000316); + amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ + amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ + + amdgpu_ring_unlock_commit(ring); + + return 0; +} + +/** + * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers + * + * @adev: amdgpu_device pointer + * + * Program the location and size of the gfx ring buffer + * and test it to make sure it's working. + * Returns 0 for success, error for failure. + */ +static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + u32 tmp; + u32 rb_bufsz; + u64 rb_addr, rptr_addr; + int r; + + WREG32(mmCP_SEM_WAIT_TIMER, 0x0); + if (adev->asic_type != CHIP_HAWAII) + WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); + + /* Set the write pointer delay */ + WREG32(mmCP_RB_WPTR_DELAY, 0); + + /* set the RB to use vmid 0 */ + WREG32(mmCP_RB_VMID, 0); + + WREG32(mmSCRATCH_ADDR, 0); + + /* ring 0 - compute and gfx */ + /* Set ring buffer size */ + ring = &adev->gfx.gfx_ring[0]; + rb_bufsz = order_base_2(ring->ring_size / 8); + tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; +#ifdef __BIG_ENDIAN + tmp |= BUF_SWAP_32BIT; +#endif + WREG32(mmCP_RB0_CNTL, tmp); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); + ring->wptr = 0; + WREG32(mmCP_RB0_WPTR, ring->wptr); + + /* set the wb address wether it's enabled or not */ + rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); + WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); + WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); + + /* scratch register shadowing is no longer supported */ + WREG32(mmSCRATCH_UMSK, 0); + + mdelay(1); + WREG32(mmCP_RB0_CNTL, tmp); + + rb_addr = ring->gpu_addr >> 8; + WREG32(mmCP_RB0_BASE, rb_addr); + WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); + + /* start the ring */ + gfx_v7_0_cp_gfx_start(adev); + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + return r; + } + + return 0; +} + +static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) +{ + u32 rptr; + + rptr = ring->adev->wb.wb[ring->rptr_offs]; + + return rptr; +} + +static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u32 wptr; + + wptr = RREG32(mmCP_RB0_WPTR); + + return wptr; +} + +static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + WREG32(mmCP_RB0_WPTR, ring->wptr); + (void)RREG32(mmCP_RB0_WPTR); +} + +static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring) +{ + u32 rptr; + + rptr = ring->adev->wb.wb[ring->rptr_offs]; + + return rptr; +} + +static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) +{ + u32 wptr; + + /* XXX check if swapping is necessary on BE */ + wptr = ring->adev->wb.wb[ring->wptr_offs]; + + return wptr; +} + +static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + /* XXX check if swapping is necessary on BE */ + adev->wb.wb[ring->wptr_offs] = ring->wptr; + WDOORBELL32(ring->doorbell_index, ring->wptr); +} + +/** + * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs + * + * @adev: amdgpu_device pointer + * @enable: enable or disable the MEs + * + * Halts or unhalts the compute MEs. + */ +static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) +{ + int i; + + if (enable) { + WREG32(mmCP_MEC_CNTL, 0); + } else { + WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); + for (i = 0; i < adev->gfx.num_compute_rings; i++) + adev->gfx.compute_ring[i].ready = false; + } + udelay(50); +} + +/** + * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode + * + * @adev: amdgpu_device pointer + * + * Loads the compute MEC1&2 ucode. + * Returns 0 for success, -EINVAL if the ucode is not available. + */ +static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) +{ + const struct gfx_firmware_header_v1_0 *mec_hdr; + const __le32 *fw_data; + unsigned i, fw_size; + + if (!adev->gfx.mec_fw) + return -EINVAL; + + mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; + amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); + adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); + + gfx_v7_0_cp_compute_enable(adev, false); + + /* MEC1 */ + fw_data = (const __le32 *) + (adev->gfx.mec_fw->data + + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; + WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); + + if (adev->asic_type == CHIP_KAVERI) { + const struct gfx_firmware_header_v1_0 *mec2_hdr; + + if (!adev->gfx.mec2_fw) + return -EINVAL; + + mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; + amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); + adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); + + /* MEC2 */ + fw_data = (const __le32 *) + (adev->gfx.mec2_fw->data + + le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; + WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); + } + + return 0; +} + +/** + * gfx_v7_0_cp_compute_start - start the compute queues + * + * @adev: amdgpu_device pointer + * + * Enable the compute queues. + * Returns 0 for success, error for failure. + */ +static int gfx_v7_0_cp_compute_start(struct amdgpu_device *adev) +{ + gfx_v7_0_cp_compute_enable(adev, true); + + return 0; +} + +/** + * gfx_v7_0_cp_compute_fini - stop the compute queues + * + * @adev: amdgpu_device pointer + * + * Stop the compute queues and tear down the driver queue + * info. + */ +static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; + + if (ring->mqd_obj) { + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); + + amdgpu_bo_unpin(ring->mqd_obj); + amdgpu_bo_unreserve(ring->mqd_obj); + + amdgpu_bo_unref(&ring->mqd_obj); + ring->mqd_obj = NULL; + } + } +} + +static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) +{ + int r; + + if (adev->gfx.mec.hpd_eop_obj) { + r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); + amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); + amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); + + amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); + adev->gfx.mec.hpd_eop_obj = NULL; + } +} + +#define MEC_HPD_SIZE 2048 + +static int gfx_v7_0_mec_init(struct amdgpu_device *adev) +{ + int r; + u32 *hpd; + + /* + * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total + * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total + * Nonetheless, we assign only 1 pipe because all other pipes will + * be handled by KFD + */ + adev->gfx.mec.num_mec = 1; + adev->gfx.mec.num_pipe = 1; + adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; + + if (adev->gfx.mec.hpd_eop_obj == NULL) { + r = amdgpu_bo_create(adev, + adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, NULL, + &adev->gfx.mec.hpd_eop_obj); + if (r) { + dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); + return r; + } + } + + r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); + if (unlikely(r != 0)) { + gfx_v7_0_mec_fini(adev); + return r; + } + r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, + &adev->gfx.mec.hpd_eop_gpu_addr); + if (r) { + dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); + gfx_v7_0_mec_fini(adev); + return r; + } + r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); + if (r) { + dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); + gfx_v7_0_mec_fini(adev); + return r; + } + + /* clear memory. Not sure if this is required or not */ + memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); + + amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); + amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); + + return 0; +} + +struct hqd_registers +{ + u32 cp_mqd_base_addr; + u32 cp_mqd_base_addr_hi; + u32 cp_hqd_active; + u32 cp_hqd_vmid; + u32 cp_hqd_persistent_state; + u32 cp_hqd_pipe_priority; + u32 cp_hqd_queue_priority; + u32 cp_hqd_quantum; + u32 cp_hqd_pq_base; + u32 cp_hqd_pq_base_hi; + u32 cp_hqd_pq_rptr; + u32 cp_hqd_pq_rptr_report_addr; + u32 cp_hqd_pq_rptr_report_addr_hi; + u32 cp_hqd_pq_wptr_poll_addr; + u32 cp_hqd_pq_wptr_poll_addr_hi; + u32 cp_hqd_pq_doorbell_control; + u32 cp_hqd_pq_wptr; + u32 cp_hqd_pq_control; + u32 cp_hqd_ib_base_addr; + u32 cp_hqd_ib_base_addr_hi; + u32 cp_hqd_ib_rptr; + u32 cp_hqd_ib_control; + u32 cp_hqd_iq_timer; + u32 cp_hqd_iq_rptr; + u32 cp_hqd_dequeue_request; + u32 cp_hqd_dma_offload; + u32 cp_hqd_sema_cmd; + u32 cp_hqd_msg_type; + u32 cp_hqd_atomic0_preop_lo; + u32 cp_hqd_atomic0_preop_hi; + u32 cp_hqd_atomic1_preop_lo; + u32 cp_hqd_atomic1_preop_hi; + u32 cp_hqd_hq_scheduler0; + u32 cp_hqd_hq_scheduler1; + u32 cp_mqd_control; +}; + +struct bonaire_mqd +{ + u32 header; + u32 dispatch_initiator; + u32 dimensions[3]; + u32 start_idx[3]; + u32 num_threads[3]; + u32 pipeline_stat_enable; + u32 perf_counter_enable; + u32 pgm[2]; + u32 tba[2]; + u32 tma[2]; + u32 pgm_rsrc[2]; + u32 vmid; + u32 resource_limits; + u32 static_thread_mgmt01[2]; + u32 tmp_ring_size; + u32 static_thread_mgmt23[2]; + u32 restart[3]; + u32 thread_trace_enable; + u32 reserved1; + u32 user_data[16]; + u32 vgtcs_invoke_count[2]; + struct hqd_registers queue_state; + u32 dequeue_cntr; + u32 interrupt_queue[64]; +}; + +/** + * gfx_v7_0_cp_compute_resume - setup the compute queue registers + * + * @adev: amdgpu_device pointer + * + * Program the compute queues and test them to make sure they + * are working. + * Returns 0 for success, error for failure. + */ +static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) +{ + int r, i, j; + u32 tmp; + bool use_doorbell = true; + u64 hqd_gpu_addr; + u64 mqd_gpu_addr; + u64 eop_gpu_addr; + u64 wb_gpu_addr; + u32 *buf; + struct bonaire_mqd *mqd; + + r = gfx_v7_0_cp_compute_start(adev); + if (r) + return r; + + /* fix up chicken bits */ + tmp = RREG32(mmCP_CPF_DEBUG); + tmp |= (1 << 23); + WREG32(mmCP_CPF_DEBUG, tmp); + + /* init the pipes */ + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { + int me = (i < 4) ? 1 : 2; + int pipe = (i < 4) ? i : (i - 4); + + eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2); + + cik_srbm_select(adev, me, pipe, 0, 0); + + /* write the EOP addr */ + WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); + WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); + + /* set the VMID assigned */ + WREG32(mmCP_HPD_EOP_VMID, 0); + + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + tmp = RREG32(mmCP_HPD_EOP_CONTROL); + tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; + tmp |= order_base_2(MEC_HPD_SIZE / 8); + WREG32(mmCP_HPD_EOP_CONTROL, tmp); + } + cik_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + /* init the queues. Just two for now. */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; + + if (ring->mqd_obj == NULL) { + r = amdgpu_bo_create(adev, + sizeof(struct bonaire_mqd), + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, NULL, + &ring->mqd_obj); + if (r) { + dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); + return r; + } + } + + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) { + gfx_v7_0_cp_compute_fini(adev); + return r; + } + r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, + &mqd_gpu_addr); + if (r) { + dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); + gfx_v7_0_cp_compute_fini(adev); + return r; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); + if (r) { + dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); + gfx_v7_0_cp_compute_fini(adev); + return r; + } + + /* init the mqd struct */ + memset(buf, 0, sizeof(struct bonaire_mqd)); + + mqd = (struct bonaire_mqd *)buf; + mqd->header = 0xC0310800; + mqd->static_thread_mgmt01[0] = 0xffffffff; + mqd->static_thread_mgmt01[1] = 0xffffffff; + mqd->static_thread_mgmt23[0] = 0xffffffff; + mqd->static_thread_mgmt23[1] = 0xffffffff; + + mutex_lock(&adev->srbm_mutex); + cik_srbm_select(adev, ring->me, + ring->pipe, + ring->queue, 0); + + /* disable wptr polling */ + tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); + tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK; + WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); + + /* enable doorbell? */ + mqd->queue_state.cp_hqd_pq_doorbell_control = + RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); + if (use_doorbell) + mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; + else + mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; + WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, + mqd->queue_state.cp_hqd_pq_doorbell_control); + + /* disable the queue if it's active */ + mqd->queue_state.cp_hqd_dequeue_request = 0; + mqd->queue_state.cp_hqd_pq_rptr = 0; + mqd->queue_state.cp_hqd_pq_wptr= 0; + if (RREG32(mmCP_HQD_ACTIVE) & 1) { + WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); + for (j = 0; j < adev->usec_timeout; j++) { + if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); + WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); + WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); + } + + /* set the pointer to the MQD */ + mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc; + mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); + WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); + WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); + /* set MQD vmid to 0 */ + mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL); + mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; + WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); + + /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ + hqd_gpu_addr = ring->gpu_addr >> 8; + mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr; + mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); + WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); + WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); + + /* set up the HQD, this is similar to CP_RB0_CNTL */ + mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); + mqd->queue_state.cp_hqd_pq_control &= + ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | + CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); + + mqd->queue_state.cp_hqd_pq_control |= + order_base_2(ring->ring_size / 8); + mqd->queue_state.cp_hqd_pq_control |= + (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); +#ifdef __BIG_ENDIAN + mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT; +#endif + mqd->queue_state.cp_hqd_pq_control &= + ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | + CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | + CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); + mqd->queue_state.cp_hqd_pq_control |= + CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | + CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ + WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); + + /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ + wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; + mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; + WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); + WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, + mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi); + + /* set the wb address wether it's enabled or not */ + wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); + mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc; + mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi = + upper_32_bits(wb_gpu_addr) & 0xffff; + WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, + mqd->queue_state.cp_hqd_pq_rptr_report_addr); + WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, + mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi); + + /* enable the doorbell if requested */ + if (use_doorbell) { + mqd->queue_state.cp_hqd_pq_doorbell_control = + RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); + mqd->queue_state.cp_hqd_pq_doorbell_control &= + ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; + mqd->queue_state.cp_hqd_pq_doorbell_control |= + (ring->doorbell_index << + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); + mqd->queue_state.cp_hqd_pq_doorbell_control |= + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; + mqd->queue_state.cp_hqd_pq_doorbell_control &= + ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); + + } else { + mqd->queue_state.cp_hqd_pq_doorbell_control = 0; + } + WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, + mqd->queue_state.cp_hqd_pq_doorbell_control); + + /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ + ring->wptr = 0; + mqd->queue_state.cp_hqd_pq_wptr = ring->wptr; + WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); + mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); + + /* set the vmid for the queue */ + mqd->queue_state.cp_hqd_vmid = 0; + WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); + + /* activate the queue */ + mqd->queue_state.cp_hqd_active = 1; + WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); + + cik_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + amdgpu_bo_kunmap(ring->mqd_obj); + amdgpu_bo_unreserve(ring->mqd_obj); + + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) + ring->ready = false; + } + + return 0; +} + +static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) +{ + gfx_v7_0_cp_gfx_enable(adev, enable); + gfx_v7_0_cp_compute_enable(adev, enable); +} + +static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) +{ + int r; + + r = gfx_v7_0_cp_gfx_load_microcode(adev); + if (r) + return r; + r = gfx_v7_0_cp_compute_load_microcode(adev); + if (r) + return r; + + return 0; +} + +static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, + bool enable) +{ + u32 tmp = RREG32(mmCP_INT_CNTL_RING0); + + if (enable) + tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | + CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); + else + tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | + CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); + WREG32(mmCP_INT_CNTL_RING0, tmp); +} + +static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) +{ + int r; + + gfx_v7_0_enable_gui_idle_interrupt(adev, false); + + r = gfx_v7_0_cp_load_microcode(adev); + if (r) + return r; + + r = gfx_v7_0_cp_gfx_resume(adev); + if (r) + return r; + r = gfx_v7_0_cp_compute_resume(adev); + if (r) + return r; + + gfx_v7_0_enable_gui_idle_interrupt(adev, true); + + return 0; +} + +static void gfx_v7_0_ce_sync_me(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4; + + /* instruct DE to set a magic number */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(5))); + amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); + amdgpu_ring_write(ring, 1); + + /* let CE wait till condition satisfied */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ + WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ + WAIT_REG_MEM_FUNCTION(3) | /* == */ + WAIT_REG_MEM_ENGINE(2))); /* ce */ + amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); + amdgpu_ring_write(ring, 1); + amdgpu_ring_write(ring, 0xffffffff); + amdgpu_ring_write(ring, 4); /* poll interval */ + + /* instruct CE to reset wb of ce_sync to zero */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | + WRITE_DATA_DST_SEL(5) | + WR_CONFIRM)); + amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); + amdgpu_ring_write(ring, 0); +} + +/* + * vm + * VMID 0 is the physical GPU addresses as used by the kernel. + * VMIDs 1-15 are used for userspace clients and are handled + * by the amdgpu vm/hsa code. + */ +/** + * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP + * + * @adev: amdgpu_device pointer + * + * Update the page table base and flush the VM TLB + * using the CP (CIK). + */ +static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr) +{ + int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | + WRITE_DATA_DST_SEL(0))); + if (vm_id < 8) { + amdgpu_ring_write(ring, + (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); + } else { + amdgpu_ring_write(ring, + (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); + } + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, pd_addr >> 12); + + /* update SH_MEM_* regs */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, VMID(vm_id)); + + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, mmSH_MEM_BASES); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */ + amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */ + amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ + amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ + + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, VMID(0)); + + + /* bits 0-15 are the VM contexts0-15 */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 1 << vm_id); + + /* wait for the invalidate to complete */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ + WAIT_REG_MEM_FUNCTION(0) | /* always */ + WAIT_REG_MEM_ENGINE(0))); /* me */ + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 0); /* ref */ + amdgpu_ring_write(ring, 0); /* mask */ + amdgpu_ring_write(ring, 0x20); /* poll interval */ + + /* compute doesn't have PFP */ + if (usepfp) { + /* sync PFP to ME, otherwise we might get invalid PFP reads */ + amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); + amdgpu_ring_write(ring, 0x0); + + /* synce CE with ME to prevent CE fetch CEIB before context switch done */ + gfx_v7_0_ce_sync_me(ring); + } +} + +/* + * RLC + * The RLC is a multi-purpose microengine that handles a + * variety of functions. + */ +static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) +{ + int r; + + /* save restore block */ + if (adev->gfx.rlc.save_restore_obj) { + r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); + amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); + amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); + + amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj); + adev->gfx.rlc.save_restore_obj = NULL; + } + + /* clear state block */ + if (adev->gfx.rlc.clear_state_obj) { + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); + amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + + amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); + adev->gfx.rlc.clear_state_obj = NULL; + } + + /* clear state block */ + if (adev->gfx.rlc.cp_table_obj) { + r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); + amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); + amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); + + amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); + adev->gfx.rlc.cp_table_obj = NULL; + } +} + +static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) +{ + const u32 *src_ptr; + volatile u32 *dst_ptr; + u32 dws, i; + const struct cs_section_def *cs_data; + int r; + + /* allocate rlc buffers */ + if (adev->flags & AMDGPU_IS_APU) { + if (adev->asic_type == CHIP_KAVERI) { + adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; + adev->gfx.rlc.reg_list_size = + (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list); + } else { + adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; + adev->gfx.rlc.reg_list_size = + (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list); + } + } + adev->gfx.rlc.cs_data = ci_cs_data; + adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4; + + src_ptr = adev->gfx.rlc.reg_list; + dws = adev->gfx.rlc.reg_list_size; + dws += (5 * 16) + 48 + 48 + 64; + + cs_data = adev->gfx.rlc.cs_data; + + if (src_ptr) { + /* save restore block */ + if (adev->gfx.rlc.save_restore_obj == NULL) { + r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.save_restore_obj); + if (r) { + dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); + return r; + } + } + + r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); + if (unlikely(r != 0)) { + gfx_v7_0_rlc_fini(adev); + return r; + } + r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.save_restore_gpu_addr); + if (r) { + amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); + dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r); + gfx_v7_0_rlc_fini(adev); + return r; + } + + r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr); + if (r) { + dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r); + gfx_v7_0_rlc_fini(adev); + return r; + } + /* write the sr buffer */ + dst_ptr = adev->gfx.rlc.sr_ptr; + for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) + dst_ptr[i] = cpu_to_le32(src_ptr[i]); + amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); + amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); + } + + if (cs_data) { + /* clear state block */ + adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); + + if (adev->gfx.rlc.clear_state_obj == NULL) { + r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.clear_state_obj); + if (r) { + dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); + gfx_v7_0_rlc_fini(adev); + return r; + } + } + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); + if (unlikely(r != 0)) { + gfx_v7_0_rlc_fini(adev); + return r; + } + r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.clear_state_gpu_addr); + if (r) { + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); + gfx_v7_0_rlc_fini(adev); + return r; + } + + r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); + if (r) { + dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); + gfx_v7_0_rlc_fini(adev); + return r; + } + /* set up the cs buffer */ + dst_ptr = adev->gfx.rlc.cs_ptr; + gfx_v7_0_get_csb_buffer(adev, dst_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + } + + if (adev->gfx.rlc.cp_table_size) { + if (adev->gfx.rlc.cp_table_obj == NULL) { + r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.cp_table_obj); + if (r) { + dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); + gfx_v7_0_rlc_fini(adev); + return r; + } + } + + r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); + if (unlikely(r != 0)) { + dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); + gfx_v7_0_rlc_fini(adev); + return r; + } + r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.cp_table_gpu_addr); + if (r) { + amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); + dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r); + gfx_v7_0_rlc_fini(adev); + return r; + } + r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr); + if (r) { + dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r); + gfx_v7_0_rlc_fini(adev); + return r; + } + + gfx_v7_0_init_cp_pg_table(adev); + + amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); + amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); + + } + + return 0; +} + +static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) +{ + u32 tmp; + + tmp = RREG32(mmRLC_LB_CNTL); + if (enable) + tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; + else + tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; + WREG32(mmRLC_LB_CNTL, tmp); +} + +static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) +{ + u32 i, j, k; + u32 mask; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + gfx_v7_0_select_se_sh(adev, i, j); + for (k = 0; k < adev->usec_timeout; k++) { + if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) + break; + udelay(1); + } + } + } + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + + mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | + RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | + RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | + RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; + for (k = 0; k < adev->usec_timeout; k++) { + if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) + break; + udelay(1); + } +} + +static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) +{ + u32 tmp; + + tmp = RREG32(mmRLC_CNTL); + if (tmp != rlc) + WREG32(mmRLC_CNTL, rlc); +} + +static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) +{ + u32 data, orig; + + orig = data = RREG32(mmRLC_CNTL); + + if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { + u32 i; + + data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; + WREG32(mmRLC_CNTL, data); + + for (i = 0; i < adev->usec_timeout; i++) { + if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) + break; + udelay(1); + } + + gfx_v7_0_wait_for_rlc_serdes(adev); + } + + return orig; +} + +void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev) +{ + u32 tmp, i, mask; + + tmp = 0x1 | (1 << 1); + WREG32(mmRLC_GPR_REG2, tmp); + + mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | + RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK; + for (i = 0; i < adev->usec_timeout; i++) { + if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) + break; + udelay(1); + } + + for (i = 0; i < adev->usec_timeout; i++) { + if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) + break; + udelay(1); + } +} + +void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev) +{ + u32 tmp; + + tmp = 0x1 | (0 << 1); + WREG32(mmRLC_GPR_REG2, tmp); +} + +/** + * gfx_v7_0_rlc_stop - stop the RLC ME + * + * @adev: amdgpu_device pointer + * + * Halt the RLC ME (MicroEngine) (CIK). + */ +void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) +{ + WREG32(mmRLC_CNTL, 0); + + gfx_v7_0_enable_gui_idle_interrupt(adev, false); + + gfx_v7_0_wait_for_rlc_serdes(adev); +} + +/** + * gfx_v7_0_rlc_start - start the RLC ME + * + * @adev: amdgpu_device pointer + * + * Unhalt the RLC ME (MicroEngine) (CIK). + */ +static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) +{ + WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); + + gfx_v7_0_enable_gui_idle_interrupt(adev, true); + + udelay(50); +} + +static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmGRBM_SOFT_RESET); + + tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; + WREG32(mmGRBM_SOFT_RESET, tmp); + udelay(50); + tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; + WREG32(mmGRBM_SOFT_RESET, tmp); + udelay(50); +} + +/** + * gfx_v7_0_rlc_resume - setup the RLC hw + * + * @adev: amdgpu_device pointer + * + * Initialize the RLC registers, load the ucode, + * and start the RLC (CIK). + * Returns 0 for success, -EINVAL if the ucode is not available. + */ +static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) +{ + const struct rlc_firmware_header_v1_0 *hdr; + const __le32 *fw_data; + unsigned i, fw_size; + u32 tmp; + + if (!adev->gfx.rlc_fw) + return -EINVAL; + + hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; + amdgpu_ucode_print_rlc_hdr(&hdr->header); + adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); + + gfx_v7_0_rlc_stop(adev); + + /* disable CG */ + tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; + WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); + + gfx_v7_0_rlc_reset(adev); + + gfx_v7_0_init_pg(adev); + + WREG32(mmRLC_LB_CNTR_INIT, 0); + WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); + + mutex_lock(&adev->grbm_idx_mutex); + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); + WREG32(mmRLC_LB_PARAMS, 0x00600408); + WREG32(mmRLC_LB_CNTL, 0x80000004); + mutex_unlock(&adev->grbm_idx_mutex); + + WREG32(mmRLC_MC_CNTL, 0); + WREG32(mmRLC_UCODE_CNTL, 0); + + fw_data = (const __le32 *) + (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + WREG32(mmRLC_GPM_UCODE_ADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); + + /* XXX - find out what chips support lbpw */ + gfx_v7_0_enable_lbpw(adev, false); + + if (adev->asic_type == CHIP_BONAIRE) + WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); + + gfx_v7_0_rlc_start(adev); + + return 0; +} + +static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) +{ + u32 data, orig, tmp, tmp2; + + orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); + + if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) { + gfx_v7_0_enable_gui_idle_interrupt(adev, true); + + tmp = gfx_v7_0_halt_rlc(adev); + + mutex_lock(&adev->grbm_idx_mutex); + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); + WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); + tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | + RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK | + RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK; + WREG32(mmRLC_SERDES_WR_CTRL, tmp2); + mutex_unlock(&adev->grbm_idx_mutex); + + gfx_v7_0_update_rlc(adev, tmp); + + data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; + } else { + gfx_v7_0_enable_gui_idle_interrupt(adev, false); + + RREG32(mmCB_CGTT_SCLK_CTRL); + RREG32(mmCB_CGTT_SCLK_CTRL); + RREG32(mmCB_CGTT_SCLK_CTRL); + RREG32(mmCB_CGTT_SCLK_CTRL); + + data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); + } + + if (orig != data) + WREG32(mmRLC_CGCG_CGLS_CTRL, data); + +} + +static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) +{ + u32 data, orig, tmp = 0; + + if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) { + if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) { + if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) { + orig = data = RREG32(mmCP_MEM_SLP_CNTL); + data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; + if (orig != data) + WREG32(mmCP_MEM_SLP_CNTL, data); + } + } + + orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); + data |= 0x00000001; + data &= 0xfffffffd; + if (orig != data) + WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); + + tmp = gfx_v7_0_halt_rlc(adev); + + mutex_lock(&adev->grbm_idx_mutex); + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); + WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); + data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | + RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK; + WREG32(mmRLC_SERDES_WR_CTRL, data); + mutex_unlock(&adev->grbm_idx_mutex); + + gfx_v7_0_update_rlc(adev, tmp); + + if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) { + orig = data = RREG32(mmCGTS_SM_CTRL_REG); + data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; + data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); + data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; + data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; + if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) && + (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS)) + data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; + data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; + data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; + data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); + if (orig != data) + WREG32(mmCGTS_SM_CTRL_REG, data); + } + } else { + orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); + data |= 0x00000003; + if (orig != data) + WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); + + data = RREG32(mmRLC_MEM_SLP_CNTL); + if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { + data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; + WREG32(mmRLC_MEM_SLP_CNTL, data); + } + + data = RREG32(mmCP_MEM_SLP_CNTL); + if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { + data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; + WREG32(mmCP_MEM_SLP_CNTL, data); + } + + orig = data = RREG32(mmCGTS_SM_CTRL_REG); + data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; + if (orig != data) + WREG32(mmCGTS_SM_CTRL_REG, data); + + tmp = gfx_v7_0_halt_rlc(adev); + + mutex_lock(&adev->grbm_idx_mutex); + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); + WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); + data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; + WREG32(mmRLC_SERDES_WR_CTRL, data); + mutex_unlock(&adev->grbm_idx_mutex); + + gfx_v7_0_update_rlc(adev, tmp); + } +} + +static void gfx_v7_0_update_cg(struct amdgpu_device *adev, + bool enable) +{ + gfx_v7_0_enable_gui_idle_interrupt(adev, false); + /* order matters! */ + if (enable) { + gfx_v7_0_enable_mgcg(adev, true); + gfx_v7_0_enable_cgcg(adev, true); + } else { + gfx_v7_0_enable_cgcg(adev, false); + gfx_v7_0_enable_mgcg(adev, false); + } + gfx_v7_0_enable_gui_idle_interrupt(adev, true); +} + +static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, + bool enable) +{ + u32 data, orig; + + orig = data = RREG32(mmRLC_PG_CNTL); + if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS)) + data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; + else + data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; + if (orig != data) + WREG32(mmRLC_PG_CNTL, data); +} + +static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, + bool enable) +{ + u32 data, orig; + + orig = data = RREG32(mmRLC_PG_CNTL); + if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS)) + data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; + else + data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; + if (orig != data) + WREG32(mmRLC_PG_CNTL, data); +} + +static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) +{ + u32 data, orig; + + orig = data = RREG32(mmRLC_PG_CNTL); + if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP)) + data &= ~0x8000; + else + data |= 0x8000; + if (orig != data) + WREG32(mmRLC_PG_CNTL, data); +} + +static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) +{ + u32 data, orig; + + orig = data = RREG32(mmRLC_PG_CNTL); + if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS)) + data &= ~0x2000; + else + data |= 0x2000; + if (orig != data) + WREG32(mmRLC_PG_CNTL, data); +} + +static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev) +{ + const __le32 *fw_data; + volatile u32 *dst_ptr; + int me, i, max_me = 4; + u32 bo_offset = 0; + u32 table_offset, table_size; + + if (adev->asic_type == CHIP_KAVERI) + max_me = 5; + + if (adev->gfx.rlc.cp_table_ptr == NULL) + return; + + /* write the cp table buffer */ + dst_ptr = adev->gfx.rlc.cp_table_ptr; + for (me = 0; me < max_me; me++) { + if (me == 0) { + const struct gfx_firmware_header_v1_0 *hdr = + (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; + fw_data = (const __le32 *) + (adev->gfx.ce_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + table_offset = le32_to_cpu(hdr->jt_offset); + table_size = le32_to_cpu(hdr->jt_size); + } else if (me == 1) { + const struct gfx_firmware_header_v1_0 *hdr = + (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; + fw_data = (const __le32 *) + (adev->gfx.pfp_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + table_offset = le32_to_cpu(hdr->jt_offset); + table_size = le32_to_cpu(hdr->jt_size); + } else if (me == 2) { + const struct gfx_firmware_header_v1_0 *hdr = + (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; + fw_data = (const __le32 *) + (adev->gfx.me_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + table_offset = le32_to_cpu(hdr->jt_offset); + table_size = le32_to_cpu(hdr->jt_size); + } else if (me == 3) { + const struct gfx_firmware_header_v1_0 *hdr = + (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; + fw_data = (const __le32 *) + (adev->gfx.mec_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + table_offset = le32_to_cpu(hdr->jt_offset); + table_size = le32_to_cpu(hdr->jt_size); + } else { + const struct gfx_firmware_header_v1_0 *hdr = + (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; + fw_data = (const __le32 *) + (adev->gfx.mec2_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + table_offset = le32_to_cpu(hdr->jt_offset); + table_size = le32_to_cpu(hdr->jt_size); + } + + for (i = 0; i < table_size; i ++) { + dst_ptr[bo_offset + i] = + cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); + } + + bo_offset += table_size; + } +} + +static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, + bool enable) +{ + u32 data, orig; + + if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) { + orig = data = RREG32(mmRLC_PG_CNTL); + data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; + if (orig != data) + WREG32(mmRLC_PG_CNTL, data); + + orig = data = RREG32(mmRLC_AUTO_PG_CTRL); + data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; + if (orig != data) + WREG32(mmRLC_AUTO_PG_CTRL, data); + } else { + orig = data = RREG32(mmRLC_PG_CNTL); + data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; + if (orig != data) + WREG32(mmRLC_PG_CNTL, data); + + orig = data = RREG32(mmRLC_AUTO_PG_CTRL); + data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; + if (orig != data) + WREG32(mmRLC_AUTO_PG_CTRL, data); + + data = RREG32(mmDB_RENDER_CONTROL); + } +} + +static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev, + u32 se, u32 sh) +{ + u32 mask = 0, tmp, tmp1; + int i; + + gfx_v7_0_select_se_sh(adev, se, sh); + tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); + tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + + tmp &= 0xffff0000; + + tmp |= tmp1; + tmp >>= 16; + + for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) { + mask <<= 1; + mask |= 1; + } + + return (~tmp) & mask; +} + +static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) +{ + uint32_t tmp, active_cu_number; + struct amdgpu_cu_info cu_info; + + gfx_v7_0_get_cu_info(adev, &cu_info); + tmp = cu_info.ao_cu_mask; + active_cu_number = cu_info.number; + + WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp); + + tmp = RREG32(mmRLC_MAX_PG_CU); + tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; + tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); + WREG32(mmRLC_MAX_PG_CU, tmp); +} + +static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, + bool enable) +{ + u32 data, orig; + + orig = data = RREG32(mmRLC_PG_CNTL); + if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG)) + data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; + else + data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; + if (orig != data) + WREG32(mmRLC_PG_CNTL, data); +} + +static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, + bool enable) +{ + u32 data, orig; + + orig = data = RREG32(mmRLC_PG_CNTL); + if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG)) + data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; + else + data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; + if (orig != data) + WREG32(mmRLC_PG_CNTL, data); +} + +#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 +#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D + +static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) +{ + u32 data, orig; + u32 i; + + if (adev->gfx.rlc.cs_data) { + WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); + WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); + WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); + WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); + } else { + WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); + for (i = 0; i < 3; i++) + WREG32(mmRLC_GPM_SCRATCH_DATA, 0); + } + if (adev->gfx.rlc.reg_list) { + WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); + for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) + WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); + } + + orig = data = RREG32(mmRLC_PG_CNTL); + data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK; + if (orig != data) + WREG32(mmRLC_PG_CNTL, data); + + WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); + WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); + + data = RREG32(mmCP_RB_WPTR_POLL_CNTL); + data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; + data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); + WREG32(mmCP_RB_WPTR_POLL_CNTL, data); + + data = 0x10101010; + WREG32(mmRLC_PG_DELAY, data); + + data = RREG32(mmRLC_PG_DELAY_2); + data &= ~0xff; + data |= 0x3; + WREG32(mmRLC_PG_DELAY_2, data); + + data = RREG32(mmRLC_AUTO_PG_CTRL); + data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; + data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); + WREG32(mmRLC_AUTO_PG_CTRL, data); + +} + +static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) +{ + gfx_v7_0_enable_gfx_cgpg(adev, enable); + gfx_v7_0_enable_gfx_static_mgpg(adev, enable); + gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); +} + +static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) +{ + u32 count = 0; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + + if (adev->gfx.rlc.cs_data == NULL) + return 0; + + /* begin clear state */ + count += 2; + /* context control state */ + count += 3; + + for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { + for (ext = sect->section; ext->extent != NULL; ++ext) { + if (sect->id == SECT_CONTEXT) + count += 2 + ext->reg_count; + else + return 0; + } + } + /* pa_sc_raster_config/pa_sc_raster_config1 */ + count += 4; + /* end clear state */ + count += 2; + /* clear state */ + count += 2; + + return count; +} + +static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, + volatile u32 *buffer) +{ + u32 count = 0, i; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + + if (adev->gfx.rlc.cs_data == NULL) + return; + if (buffer == NULL) + return; + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); + buffer[count++] = cpu_to_le32(0x80000000); + buffer[count++] = cpu_to_le32(0x80000000); + + for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { + for (ext = sect->section; ext->extent != NULL; ++ext) { + if (sect->id == SECT_CONTEXT) { + buffer[count++] = + cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); + buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); + for (i = 0; i < ext->reg_count; i++) + buffer[count++] = cpu_to_le32(ext->extent[i]); + } else { + return; + } + } + } + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); + switch (adev->asic_type) { + case CHIP_BONAIRE: + buffer[count++] = cpu_to_le32(0x16000012); + buffer[count++] = cpu_to_le32(0x00000000); + break; + case CHIP_KAVERI: + buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ + buffer[count++] = cpu_to_le32(0x00000000); + break; + case CHIP_KABINI: + case CHIP_MULLINS: + buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ + buffer[count++] = cpu_to_le32(0x00000000); + break; + case CHIP_HAWAII: + buffer[count++] = cpu_to_le32(0x3a00161a); + buffer[count++] = cpu_to_le32(0x0000002e); + break; + default: + buffer[count++] = cpu_to_le32(0x00000000); + buffer[count++] = cpu_to_le32(0x00000000); + break; + } + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); + buffer[count++] = cpu_to_le32(0); +} + +static void gfx_v7_0_init_pg(struct amdgpu_device *adev) +{ + if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | + AMDGPU_PG_SUPPORT_GFX_SMG | + AMDGPU_PG_SUPPORT_GFX_DMG | + AMDGPU_PG_SUPPORT_CP | + AMDGPU_PG_SUPPORT_GDS | + AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { + gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); + gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); + if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { + gfx_v7_0_init_gfx_cgpg(adev); + gfx_v7_0_enable_cp_pg(adev, true); + gfx_v7_0_enable_gds_pg(adev, true); + } + gfx_v7_0_init_ao_cu_mask(adev); + gfx_v7_0_update_gfx_pg(adev, true); + } +} + +static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) +{ + if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | + AMDGPU_PG_SUPPORT_GFX_SMG | + AMDGPU_PG_SUPPORT_GFX_DMG | + AMDGPU_PG_SUPPORT_CP | + AMDGPU_PG_SUPPORT_GDS | + AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { + gfx_v7_0_update_gfx_pg(adev, false); + if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { + gfx_v7_0_enable_cp_pg(adev, false); + gfx_v7_0_enable_gds_pg(adev, false); + } + } +} + +/** + * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot + * + * @adev: amdgpu_device pointer + * + * Fetches a GPU clock counter snapshot (SI). + * Returns the 64 bit clock counter snapshot. + */ +uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) +{ + uint64_t clock; + + mutex_lock(&adev->gfx.gpu_clock_mutex); + WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); + clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | + ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); + mutex_unlock(&adev->gfx.gpu_clock_mutex); + return clock; +} + +static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, + uint32_t vmid, + uint32_t gds_base, uint32_t gds_size, + uint32_t gws_base, uint32_t gws_size, + uint32_t oa_base, uint32_t oa_size) +{ + gds_base = gds_base >> AMDGPU_GDS_SHIFT; + gds_size = gds_size >> AMDGPU_GDS_SHIFT; + + gws_base = gws_base >> AMDGPU_GWS_SHIFT; + gws_size = gws_size >> AMDGPU_GWS_SHIFT; + + oa_base = oa_base >> AMDGPU_OA_SHIFT; + oa_size = oa_size >> AMDGPU_OA_SHIFT; + + /* GDS Base */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, gds_base); + + /* GDS Size */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, gds_size); + + /* GWS */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); + + /* OA */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); +} + +static int gfx_v7_0_early_init(struct amdgpu_device *adev) +{ + + adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; + adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS; + gfx_v7_0_set_ring_funcs(adev); + gfx_v7_0_set_irq_funcs(adev); + gfx_v7_0_set_gds_init(adev); + + return 0; +} + +static int gfx_v7_0_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int i, r; + + /* EOP Event */ + r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); + if (r) + return r; + + /* Privileged reg */ + r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); + if (r) + return r; + + /* Privileged inst */ + r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); + if (r) + return r; + + gfx_v7_0_scratch_init(adev); + + r = gfx_v7_0_init_microcode(adev); + if (r) { + DRM_ERROR("Failed to load gfx firmware!\n"); + return r; + } + + r = gfx_v7_0_rlc_init(adev); + if (r) { + DRM_ERROR("Failed to init rlc BOs!\n"); + return r; + } + + /* allocate mec buffers */ + r = gfx_v7_0_mec_init(adev); + if (r) { + DRM_ERROR("Failed to init MEC BOs!\n"); + return r; + } + + r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs); + if (r) { + DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r); + return r; + } + + for (i = 0; i < adev->gfx.num_gfx_rings; i++) { + ring = &adev->gfx.gfx_ring[i]; + ring->ring_obj = NULL; + sprintf(ring->name, "gfx"); + r = amdgpu_ring_init(adev, ring, 1024 * 1024, + PACKET3(PACKET3_NOP, 0x3FFF), 0xf, + &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, + AMDGPU_RING_TYPE_GFX); + if (r) + return r; + } + + /* set up the compute queues */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + unsigned irq_type; + + /* max 32 queues per MEC */ + if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { + DRM_ERROR("Too many (%d) compute rings!\n", i); + break; + } + ring = &adev->gfx.compute_ring[i]; + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; + ring->me = 1; /* first MEC */ + ring->pipe = i / 8; + ring->queue = i % 8; + sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); + irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; + /* type-2 packets are deprecated on MEC, use type-3 instead */ + r = amdgpu_ring_init(adev, ring, 1024 * 1024, + PACKET3(PACKET3_NOP, 0x3FFF), 0xf, + &adev->gfx.eop_irq, irq_type, + AMDGPU_RING_TYPE_COMPUTE); + if (r) + return r; + } + + /* reserve GDS, GWS and OA resource for gfx */ + r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size, + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GDS, 0, + NULL, &adev->gds.gds_gfx_bo); + if (r) + return r; + + r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size, + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GWS, 0, + NULL, &adev->gds.gws_gfx_bo); + if (r) + return r; + + r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size, + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_OA, 0, + NULL, &adev->gds.oa_gfx_bo); + if (r) + return r; + + return r; +} + +static int gfx_v7_0_sw_fini(struct amdgpu_device *adev) +{ + int i; + + amdgpu_bo_unref(&adev->gds.oa_gfx_bo); + amdgpu_bo_unref(&adev->gds.gws_gfx_bo); + amdgpu_bo_unref(&adev->gds.gds_gfx_bo); + + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); + for (i = 0; i < adev->gfx.num_compute_rings; i++) + amdgpu_ring_fini(&adev->gfx.compute_ring[i]); + + amdgpu_wb_free(adev, adev->gfx.ce_sync_offs); + + gfx_v7_0_cp_compute_fini(adev); + gfx_v7_0_rlc_fini(adev); + gfx_v7_0_mec_fini(adev); + + return 0; +} + +static int gfx_v7_0_hw_init(struct amdgpu_device *adev) +{ + int r; + + gfx_v7_0_gpu_init(adev); + + /* init rlc */ + r = gfx_v7_0_rlc_resume(adev); + if (r) + return r; + + r = gfx_v7_0_cp_resume(adev); + if (r) + return r; + + return r; +} + +static int gfx_v7_0_hw_fini(struct amdgpu_device *adev) +{ + gfx_v7_0_cp_enable(adev, false); + gfx_v7_0_rlc_stop(adev); + gfx_v7_0_fini_pg(adev); + + return 0; +} + +static int gfx_v7_0_suspend(struct amdgpu_device *adev) +{ + return gfx_v7_0_hw_fini(adev); +} + +static int gfx_v7_0_resume(struct amdgpu_device *adev) +{ + return gfx_v7_0_hw_init(adev); +} + +static bool gfx_v7_0_is_idle(struct amdgpu_device *adev) +{ + if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) + return false; + else + return true; +} + +static int gfx_v7_0_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; + + if (!tmp) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static void gfx_v7_0_print_status(struct amdgpu_device *adev) +{ + int i; + + dev_info(adev->dev, "GFX 7.x registers\n"); + dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", + RREG32(mmGRBM_STATUS)); + dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", + RREG32(mmGRBM_STATUS2)); + dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", + RREG32(mmGRBM_STATUS_SE0)); + dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", + RREG32(mmGRBM_STATUS_SE1)); + dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", + RREG32(mmGRBM_STATUS_SE2)); + dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", + RREG32(mmGRBM_STATUS_SE3)); + dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); + dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT1)); + dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT2)); + dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT3)); + dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", + RREG32(mmCP_CPF_BUSY_STAT)); + dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_CPF_STALLED_STAT1)); + dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); + dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); + dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_CPC_STALLED_STAT1)); + dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); + + for (i = 0; i < 32; i++) { + dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", + i, RREG32(mmGB_TILE_MODE0 + (i * 4))); + } + for (i = 0; i < 16; i++) { + dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", + i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); + } + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + dev_info(adev->dev, " se: %d\n", i); + gfx_v7_0_select_se_sh(adev, i, 0xffffffff); + dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", + RREG32(mmPA_SC_RASTER_CONFIG)); + dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", + RREG32(mmPA_SC_RASTER_CONFIG_1)); + } + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + + dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", + RREG32(mmGB_ADDR_CONFIG)); + dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", + RREG32(mmHDP_ADDR_CONFIG)); + dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", + RREG32(mmDMIF_ADDR_CALC)); + dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n", + RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET)); + dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n", + RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET)); + dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); + + dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", + RREG32(mmCP_MEQ_THRESHOLDS)); + dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", + RREG32(mmSX_DEBUG_1)); + dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", + RREG32(mmTA_CNTL_AUX)); + dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", + RREG32(mmSPI_CONFIG_CNTL)); + dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", + RREG32(mmSQ_CONFIG)); + dev_info(adev->dev, " DB_DEBUG=0x%08X\n", + RREG32(mmDB_DEBUG)); + dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", + RREG32(mmDB_DEBUG2)); + dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", + RREG32(mmDB_DEBUG3)); + dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", + RREG32(mmCB_HW_CONTROL)); + dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", + RREG32(mmSPI_CONFIG_CNTL_1)); + dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", + RREG32(mmPA_SC_FIFO_SIZE)); + dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", + RREG32(mmVGT_NUM_INSTANCES)); + dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", + RREG32(mmCP_PERFMON_CNTL)); + dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", + RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); + dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", + RREG32(mmVGT_CACHE_INVALIDATION)); + dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", + RREG32(mmVGT_GS_VERTEX_REUSE)); + dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", + RREG32(mmPA_SC_LINE_STIPPLE_STATE)); + dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", + RREG32(mmPA_CL_ENHANCE)); + dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", + RREG32(mmPA_SC_ENHANCE)); + + dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", + RREG32(mmCP_ME_CNTL)); + dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", + RREG32(mmCP_MAX_CONTEXT)); + dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", + RREG32(mmCP_ENDIAN_SWAP)); + dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", + RREG32(mmCP_DEVICE_ID)); + + dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", + RREG32(mmCP_SEM_WAIT_TIMER)); + if (adev->asic_type != CHIP_HAWAII) + dev_info(adev->dev, " CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n", + RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL)); + + dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", + RREG32(mmCP_RB_WPTR_DELAY)); + dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", + RREG32(mmCP_RB_VMID)); + dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", + RREG32(mmCP_RB0_CNTL)); + dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", + RREG32(mmCP_RB0_WPTR)); + dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", + RREG32(mmCP_RB0_RPTR_ADDR)); + dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", + RREG32(mmCP_RB0_RPTR_ADDR_HI)); + dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", + RREG32(mmCP_RB0_CNTL)); + dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", + RREG32(mmCP_RB0_BASE)); + dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", + RREG32(mmCP_RB0_BASE_HI)); + dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", + RREG32(mmCP_MEC_CNTL)); + dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", + RREG32(mmCP_CPF_DEBUG)); + + dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", + RREG32(mmSCRATCH_ADDR)); + dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", + RREG32(mmSCRATCH_UMSK)); + + /* init the pipes */ + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { + int me = (i < 4) ? 1 : 2; + int pipe = (i < 4) ? i : (i - 4); + int queue; + + dev_info(adev->dev, " me: %d, pipe: %d\n", me, pipe); + cik_srbm_select(adev, me, pipe, 0, 0); + dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR=0x%08X\n", + RREG32(mmCP_HPD_EOP_BASE_ADDR)); + dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n", + RREG32(mmCP_HPD_EOP_BASE_ADDR_HI)); + dev_info(adev->dev, " CP_HPD_EOP_VMID=0x%08X\n", + RREG32(mmCP_HPD_EOP_VMID)); + dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n", + RREG32(mmCP_HPD_EOP_CONTROL)); + + for (queue = 0; queue < 8; i++) { + cik_srbm_select(adev, me, pipe, queue, 0); + dev_info(adev->dev, " queue: %d\n", queue); + dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n", + RREG32(mmCP_PQ_WPTR_POLL_CNTL)); + dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", + RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); + dev_info(adev->dev, " CP_HQD_ACTIVE=0x%08X\n", + RREG32(mmCP_HQD_ACTIVE)); + dev_info(adev->dev, " CP_HQD_DEQUEUE_REQUEST=0x%08X\n", + RREG32(mmCP_HQD_DEQUEUE_REQUEST)); + dev_info(adev->dev, " CP_HQD_PQ_RPTR=0x%08X\n", + RREG32(mmCP_HQD_PQ_RPTR)); + dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", + RREG32(mmCP_HQD_PQ_WPTR)); + dev_info(adev->dev, " CP_HQD_PQ_BASE=0x%08X\n", + RREG32(mmCP_HQD_PQ_BASE)); + dev_info(adev->dev, " CP_HQD_PQ_BASE_HI=0x%08X\n", + RREG32(mmCP_HQD_PQ_BASE_HI)); + dev_info(adev->dev, " CP_HQD_PQ_CONTROL=0x%08X\n", + RREG32(mmCP_HQD_PQ_CONTROL)); + dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n", + RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR)); + dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n", + RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI)); + dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n", + RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR)); + dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n", + RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI)); + dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", + RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); + dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", + RREG32(mmCP_HQD_PQ_WPTR)); + dev_info(adev->dev, " CP_HQD_VMID=0x%08X\n", + RREG32(mmCP_HQD_VMID)); + dev_info(adev->dev, " CP_MQD_BASE_ADDR=0x%08X\n", + RREG32(mmCP_MQD_BASE_ADDR)); + dev_info(adev->dev, " CP_MQD_BASE_ADDR_HI=0x%08X\n", + RREG32(mmCP_MQD_BASE_ADDR_HI)); + dev_info(adev->dev, " CP_MQD_CONTROL=0x%08X\n", + RREG32(mmCP_MQD_CONTROL)); + } + } + cik_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", + RREG32(mmCP_INT_CNTL_RING0)); + dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", + RREG32(mmRLC_LB_CNTL)); + dev_info(adev->dev, " RLC_CNTL=0x%08X\n", + RREG32(mmRLC_CNTL)); + dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", + RREG32(mmRLC_CGCG_CGLS_CTRL)); + dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", + RREG32(mmRLC_LB_CNTR_INIT)); + dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", + RREG32(mmRLC_LB_CNTR_MAX)); + dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", + RREG32(mmRLC_LB_INIT_CU_MASK)); + dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", + RREG32(mmRLC_LB_PARAMS)); + dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", + RREG32(mmRLC_LB_CNTL)); + dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", + RREG32(mmRLC_MC_CNTL)); + dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", + RREG32(mmRLC_UCODE_CNTL)); + + if (adev->asic_type == CHIP_BONAIRE) + dev_info(adev->dev, " RLC_DRIVER_CPDMA_STATUS=0x%08X\n", + RREG32(mmRLC_DRIVER_CPDMA_STATUS)); + + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < 16; i++) { + cik_srbm_select(adev, 0, 0, 0, i); + dev_info(adev->dev, " VM %d:\n", i); + dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", + RREG32(mmSH_MEM_CONFIG)); + dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", + RREG32(mmSH_MEM_APE1_BASE)); + dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", + RREG32(mmSH_MEM_APE1_LIMIT)); + dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", + RREG32(mmSH_MEM_BASES)); + } + cik_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); +} + +static int gfx_v7_0_soft_reset(struct amdgpu_device *adev) +{ + u32 grbm_soft_reset = 0, srbm_soft_reset = 0; + u32 tmp; + + /* GRBM_STATUS */ + tmp = RREG32(mmGRBM_STATUS); + if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | + GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | + GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | + GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | + GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | + GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) + grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | + GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; + + if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { + grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; + } + + /* GRBM_STATUS2 */ + tmp = RREG32(mmGRBM_STATUS2); + if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) + grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; + + /* SRBM_STATUS */ + tmp = RREG32(mmSRBM_STATUS); + if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; + + if (grbm_soft_reset || srbm_soft_reset) { + gfx_v7_0_print_status(adev); + /* disable CG/PG */ + gfx_v7_0_fini_pg(adev); + gfx_v7_0_update_cg(adev, false); + + /* stop the rlc */ + gfx_v7_0_rlc_stop(adev); + + /* Disable GFX parsing/prefetching */ + WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); + + /* Disable MEC parsing/prefetching */ + WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); + + if (grbm_soft_reset) { + tmp = RREG32(mmGRBM_SOFT_RESET); + tmp |= grbm_soft_reset; + dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmGRBM_SOFT_RESET, tmp); + tmp = RREG32(mmGRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~grbm_soft_reset; + WREG32(mmGRBM_SOFT_RESET, tmp); + tmp = RREG32(mmGRBM_SOFT_RESET); + } + + if (srbm_soft_reset) { + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + } + /* Wait a little for things to settle down */ + udelay(50); + gfx_v7_0_print_status(adev); + } + return 0; +} + +static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, + enum amdgpu_interrupt_state state) +{ + u32 cp_int_cntl; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + default: + break; + } +} + +static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, + int me, int pipe, + enum amdgpu_interrupt_state state) +{ + u32 mec_int_cntl, mec_int_cntl_reg; + + /* + * amdgpu controls only pipe 0 of MEC1. That's why this function only + * handles the setting of interrupts for this specific pipe. All other + * pipes' interrupts are set by amdkfd. + */ + + if (me == 1) { + switch (pipe) { + case 0: + mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; + break; + default: + DRM_DEBUG("invalid pipe %d\n", pipe); + return; + } + } else { + DRM_DEBUG("invalid me %d\n", me); + return; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + mec_int_cntl = RREG32(mec_int_cntl_reg); + mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mec_int_cntl_reg, mec_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + mec_int_cntl = RREG32(mec_int_cntl_reg); + mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; + WREG32(mec_int_cntl_reg, mec_int_cntl); + break; + default: + break; + } +} + +static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 cp_int_cntl; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + default: + break; + } + + return 0; +} + +static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 cp_int_cntl; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + default: + break; + } + + return 0; +} + +static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + switch (type) { + case AMDGPU_CP_IRQ_GFX_EOP: + gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: + gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: + gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: + gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: + gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: + gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: + gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: + gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: + gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); + break; + default: + break; + } + return 0; +} + +static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + u8 me_id, pipe_id; + struct amdgpu_ring *ring; + int i; + + DRM_DEBUG("IH: CP EOP\n"); + me_id = (entry->ring_id & 0x0c) >> 2; + pipe_id = (entry->ring_id & 0x03) >> 0; + switch (me_id) { + case 0: + amdgpu_fence_process(&adev->gfx.gfx_ring[0]); + break; + case 1: + case 2: + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + if ((ring->me == me_id) & (ring->pipe == pipe_id)) + amdgpu_fence_process(ring); + } + break; + } + return 0; +} + +static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal register access in command stream\n"); + schedule_work(&adev->reset_work); + return 0; +} + +static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal instruction in command stream\n"); + // XXX soft reset the gfx block only + schedule_work(&adev->reset_work); + return 0; +} + +static int gfx_v7_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + bool gate = false; + + if (state == AMDGPU_CG_STATE_GATE) + gate = true; + + gfx_v7_0_enable_gui_idle_interrupt(adev, false); + /* order matters! */ + if (gate) { + gfx_v7_0_enable_mgcg(adev, true); + gfx_v7_0_enable_cgcg(adev, true); + } else { + gfx_v7_0_enable_cgcg(adev, false); + gfx_v7_0_enable_mgcg(adev, false); + } + gfx_v7_0_enable_gui_idle_interrupt(adev, true); + + return 0; +} + +static int gfx_v7_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + bool gate = false; + + if (state == AMDGPU_PG_STATE_GATE) + gate = true; + + if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | + AMDGPU_PG_SUPPORT_GFX_SMG | + AMDGPU_PG_SUPPORT_GFX_DMG | + AMDGPU_PG_SUPPORT_CP | + AMDGPU_PG_SUPPORT_GDS | + AMDGPU_PG_SUPPORT_RLC_SMU_HS)) { + gfx_v7_0_update_gfx_pg(adev, gate); + if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { + gfx_v7_0_enable_cp_pg(adev, gate); + gfx_v7_0_enable_gds_pg(adev, gate); + } + } + + return 0; +} + +const struct amdgpu_ip_funcs gfx_v7_0_ip_funcs = { + .early_init = gfx_v7_0_early_init, + .late_init = NULL, + .sw_init = gfx_v7_0_sw_init, + .sw_fini = gfx_v7_0_sw_fini, + .hw_init = gfx_v7_0_hw_init, + .hw_fini = gfx_v7_0_hw_fini, + .suspend = gfx_v7_0_suspend, + .resume = gfx_v7_0_resume, + .is_idle = gfx_v7_0_is_idle, + .wait_for_idle = gfx_v7_0_wait_for_idle, + .soft_reset = gfx_v7_0_soft_reset, + .print_status = gfx_v7_0_print_status, + .set_clockgating_state = gfx_v7_0_set_clockgating_state, + .set_powergating_state = gfx_v7_0_set_powergating_state, +}; + +/** + * gfx_v7_0_ring_is_lockup - check if the 3D engine is locked up + * + * @adev: amdgpu_device pointer + * @ring: amdgpu_ring structure holding ring information + * + * Check if the 3D engine is locked up (CIK). + * Returns true if the engine is locked, false if not. + */ +static bool gfx_v7_0_ring_is_lockup(struct amdgpu_ring *ring) +{ + if (gfx_v7_0_is_idle(ring->adev)) { + amdgpu_ring_lockup_update(ring); + return false; + } + return amdgpu_ring_test_lockup(ring); +} + +static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { + .get_rptr = gfx_v7_0_ring_get_rptr_gfx, + .get_wptr = gfx_v7_0_ring_get_wptr_gfx, + .set_wptr = gfx_v7_0_ring_set_wptr_gfx, + .parse_cs = NULL, + .emit_ib = gfx_v7_0_ring_emit_ib, + .emit_fence = gfx_v7_0_ring_emit_fence_gfx, + .emit_semaphore = gfx_v7_0_ring_emit_semaphore, + .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, + .test_ring = gfx_v7_0_ring_test_ring, + .test_ib = gfx_v7_0_ring_test_ib, + .is_lockup = gfx_v7_0_ring_is_lockup, +}; + +static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { + .get_rptr = gfx_v7_0_ring_get_rptr_compute, + .get_wptr = gfx_v7_0_ring_get_wptr_compute, + .set_wptr = gfx_v7_0_ring_set_wptr_compute, + .parse_cs = NULL, + .emit_ib = gfx_v7_0_ring_emit_ib, + .emit_fence = gfx_v7_0_ring_emit_fence_compute, + .emit_semaphore = gfx_v7_0_ring_emit_semaphore, + .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, + .test_ring = gfx_v7_0_ring_test_ring, + .test_ib = gfx_v7_0_ring_test_ib, + .is_lockup = gfx_v7_0_ring_is_lockup, +}; + +static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; + for (i = 0; i < adev->gfx.num_compute_rings; i++) + adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; +} + +static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = { + .set = gfx_v7_0_set_eop_interrupt_state, + .process = gfx_v7_0_eop_irq, +}; + +static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = { + .set = gfx_v7_0_set_priv_reg_fault_state, + .process = gfx_v7_0_priv_reg_irq, +}; + +static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = { + .set = gfx_v7_0_set_priv_inst_fault_state, + .process = gfx_v7_0_priv_inst_irq, +}; + +static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; + adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; + + adev->gfx.priv_reg_irq.num_types = 1; + adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; + + adev->gfx.priv_inst_irq.num_types = 1; + adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; +} + +static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) +{ + /* init asci gds info */ + adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); + adev->gds.gws.total_size = 64; + adev->gds.oa.total_size = 16; + + if (adev->gds.mem.total_size == 64 * 1024) { + adev->gds.mem.gfx_partition_size = 4096; + adev->gds.mem.cs_partition_size = 4096; + + adev->gds.gws.gfx_partition_size = 4; + adev->gds.gws.cs_partition_size = 4; + + adev->gds.oa.gfx_partition_size = 4; + adev->gds.oa.cs_partition_size = 1; + } else { + adev->gds.mem.gfx_partition_size = 1024; + adev->gds.mem.cs_partition_size = 1024; + + adev->gds.gws.gfx_partition_size = 16; + adev->gds.gws.cs_partition_size = 16; + + adev->gds.oa.gfx_partition_size = 4; + adev->gds.oa.cs_partition_size = 4; + } +} + + +int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, + struct amdgpu_cu_info *cu_info) +{ + int i, j, k, counter, active_cu_number = 0; + u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; + + if (!adev || !cu_info) + return -EINVAL; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + mask = 1; + ao_bitmap = 0; + counter = 0; + bitmap = gfx_v7_0_get_cu_active_bitmap(adev, i, j); + cu_info->bitmap[i][j] = bitmap; + + for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { + if (bitmap & mask) { + if (counter < 2) + ao_bitmap |= mask; + counter ++; + } + mask <<= 1; + } + active_cu_number += counter; + ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + } + } + + cu_info->number = active_cu_number; + cu_info->ao_cu_mask = ao_cu_mask; + mutex_unlock(&adev->grbm_idx_mutex); + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h new file mode 100644 index 000000000000..668b91a89e1e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h @@ -0,0 +1,37 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __GFX_V7_0_H__ +#define __GFX_V7_0_H__ + +extern const struct amdgpu_ip_funcs gfx_v7_0_ip_funcs; + +/* XXX these shouldn't be exported */ +void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev); +void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev); +void gfx_v7_0_rlc_stop(struct amdgpu_device *adev); +uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev); +void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num); +int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c new file mode 100644 index 000000000000..b9b1df6bdaa4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -0,0 +1,1307 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include "drmP.h" +#include "amdgpu.h" +#include "cikd.h" +#include "cik.h" +#include "gmc_v7_0.h" +#include "amdgpu_ucode.h" + +#include "bif/bif_4_1_d.h" +#include "bif/bif_4_1_sh_mask.h" + +#include "gmc/gmc_7_1_d.h" +#include "gmc/gmc_7_1_sh_mask.h" + +#include "oss/oss_2_0_d.h" +#include "oss/oss_2_0_sh_mask.h" + +static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev); +static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); + +MODULE_FIRMWARE("radeon/boniare_mc.bin"); +MODULE_FIRMWARE("radeon/hawaii_mc.bin"); + +/** + * gmc8_mc_wait_for_idle - wait for MC idle callback. + * + * @adev: amdgpu_device pointer + * + * Wait for the MC (memory controller) to be idle. + * (evergreen+). + * Returns 0 if the MC is idle, -1 if not. + */ +int gmc_v7_0_mc_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(mmSRBM_STATUS) & 0x1F00; + if (!tmp) + return 0; + udelay(1); + } + return -1; +} + +void gmc_v7_0_mc_stop(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save) +{ + u32 blackout; + + if (adev->mode_info.num_crtc) + amdgpu_display_stop_mc_access(adev, save); + + amdgpu_asic_wait_for_mc_idle(adev); + + blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); + if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { + /* Block CPU access */ + WREG32(mmBIF_FB_EN, 0); + /* blackout the MC */ + blackout = REG_SET_FIELD(blackout, + MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); + WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); + } + /* wait for the MC to settle */ + udelay(100); +} + +void gmc_v7_0_mc_resume(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save) +{ + u32 tmp; + + /* unblackout the MC */ + tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); + tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); + WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); + /* allow CPU access */ + tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); + tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); + WREG32(mmBIF_FB_EN, tmp); + + if (adev->mode_info.num_crtc) + amdgpu_display_resume_mc_access(adev, save); +} + +/** + * gmc_v7_0_init_microcode - load ucode images from disk + * + * @adev: amdgpu_device pointer + * + * Use the firmware interface to load the ucode images into + * the driver (not loaded into hw). + * Returns 0 on success, error on failure. + */ +static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) +{ + const char *chip_name; + char fw_name[30]; + int err; + + DRM_DEBUG("\n"); + + switch (adev->asic_type) { + case CHIP_BONAIRE: + chip_name = "bonaire"; + break; + case CHIP_HAWAII: + chip_name = "hawaii"; + break; + case CHIP_KAVERI: + case CHIP_KABINI: + return 0; + default: BUG(); + } + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); + err = request_firmware(&adev->mc.fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->mc.fw); + +out: + if (err) { + printk(KERN_ERR + "cik_mc: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(adev->mc.fw); + adev->mc.fw = NULL; + } + return err; +} + +/** + * gmc_v7_0_mc_load_microcode - load MC ucode into the hw + * + * @adev: amdgpu_device pointer + * + * Load the GDDR MC ucode into the hw (CIK). + * Returns 0 on success, error on failure. + */ +static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) +{ + const struct mc_firmware_header_v1_0 *hdr; + const __le32 *fw_data = NULL; + const __le32 *io_mc_regs = NULL; + u32 running, blackout = 0; + int i, ucode_size, regs_size; + + if (!adev->mc.fw) + return -EINVAL; + + hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; + amdgpu_ucode_print_mc_hdr(&hdr->header); + + adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); + regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); + io_mc_regs = (const __le32 *) + (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + fw_data = (const __le32 *) + (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); + + if (running == 0) { + if (running) { + blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); + WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); + } + + /* reset the engine and set to writable */ + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); + + /* load mc io regs */ + for (i = 0; i < regs_size; i++) { + WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); + WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); + } + /* load the MC ucode */ + for (i = 0; i < ucode_size; i++) + WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); + + /* put the engine back into the active state */ + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); + + /* wait for training to complete */ + for (i = 0; i < adev->usec_timeout; i++) { + if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), + MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) + break; + udelay(1); + } + for (i = 0; i < adev->usec_timeout; i++) { + if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), + MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) + break; + udelay(1); + } + + if (running) + WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); + } + + return 0; +} + +static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, + struct amdgpu_mc *mc) +{ + if (mc->mc_vram_size > 0xFFC0000000ULL) { + /* leave room for at least 1024M GTT */ + dev_warn(adev->dev, "limiting VRAM\n"); + mc->real_vram_size = 0xFFC0000000ULL; + mc->mc_vram_size = 0xFFC0000000ULL; + } + amdgpu_vram_location(adev, &adev->mc, 0); + adev->mc.gtt_base_align = 0; + amdgpu_gtt_location(adev, mc); +} + +/** + * gmc_v7_0_mc_program - program the GPU memory controller + * + * @adev: amdgpu_device pointer + * + * Set the location of vram, gart, and AGP in the GPU's + * physical address space (CIK). + */ +static void gmc_v7_0_mc_program(struct amdgpu_device *adev) +{ + struct amdgpu_mode_mc_save save; + u32 tmp; + int i, j; + + /* Initialize HDP */ + for (i = 0, j = 0; i < 32; i++, j += 0x6) { + WREG32((0xb05 + j), 0x00000000); + WREG32((0xb06 + j), 0x00000000); + WREG32((0xb07 + j), 0x00000000); + WREG32((0xb08 + j), 0x00000000); + WREG32((0xb09 + j), 0x00000000); + } + WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); + + if (adev->mode_info.num_crtc) + amdgpu_display_set_vga_render_state(adev, false); + + gmc_v7_0_mc_stop(adev, &save); + if (amdgpu_asic_wait_for_mc_idle(adev)) { + dev_warn(adev->dev, "Wait for MC idle timedout !\n"); + } + /* Update configuration */ + WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, + adev->mc.vram_start >> 12); + WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, + adev->mc.vram_end >> 12); + WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, + adev->vram_scratch.gpu_addr >> 12); + tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; + tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); + WREG32(mmMC_VM_FB_LOCATION, tmp); + /* XXX double check these! */ + WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); + WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); + WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); + WREG32(mmMC_VM_AGP_BASE, 0); + WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); + WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); + if (amdgpu_asic_wait_for_mc_idle(adev)) { + dev_warn(adev->dev, "Wait for MC idle timedout !\n"); + } + gmc_v7_0_mc_resume(adev, &save); + + WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); + + tmp = RREG32(mmHDP_MISC_CNTL); + tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); + WREG32(mmHDP_MISC_CNTL, tmp); + + tmp = RREG32(mmHDP_HOST_PATH_CNTL); + WREG32(mmHDP_HOST_PATH_CNTL, tmp); +} + +/** + * gmc_v7_0_mc_init - initialize the memory controller driver params + * + * @adev: amdgpu_device pointer + * + * Look up the amount of vram, vram width, and decide how to place + * vram and gart within the GPU's physical address space (CIK). + * Returns 0 for success. + */ +static int gmc_v7_0_mc_init(struct amdgpu_device *adev) +{ + u32 tmp; + int chansize, numchan; + + /* Get VRAM informations */ + tmp = RREG32(mmMC_ARB_RAMCFG); + if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { + chansize = 64; + } else { + chansize = 32; + } + tmp = RREG32(mmMC_SHARED_CHMAP); + switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { + case 0: + default: + numchan = 1; + break; + case 1: + numchan = 2; + break; + case 2: + numchan = 4; + break; + case 3: + numchan = 8; + break; + case 4: + numchan = 3; + break; + case 5: + numchan = 6; + break; + case 6: + numchan = 10; + break; + case 7: + numchan = 12; + break; + case 8: + numchan = 16; + break; + } + adev->mc.vram_width = numchan * chansize; + /* Could aper size report 0 ? */ + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); + /* size in MB on si */ + adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + adev->mc.visible_vram_size = adev->mc.aper_size; + + /* unless the user had overridden it, set the gart + * size equal to the 1024 or vram, whichever is larger. + */ + if (amdgpu_gart_size == -1) + adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); + else + adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; + + gmc_v7_0_vram_gtt_location(adev, &adev->mc); + + return 0; +} + +/* + * GART + * VMID 0 is the physical GPU addresses as used by the kernel. + * VMIDs 1-15 are used for userspace clients and are handled + * by the amdgpu vm/hsa code. + */ + +/** + * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback + * + * @adev: amdgpu_device pointer + * @vmid: vm instance to flush + * + * Flush the TLB for the requested page table (CIK). + */ +static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + uint32_t vmid) +{ + /* flush hdp cache */ + WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); + + /* bits 0-15 are the VM contexts0-15 */ + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); +} + +/** + * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO + * + * @adev: amdgpu_device pointer + * @cpu_pt_addr: cpu address of the page table + * @gpu_page_idx: entry in the page table to update + * @addr: dst addr to write into pte/pde + * @flags: access flags + * + * Update the page tables using the CPU. + */ +static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev, + void *cpu_pt_addr, + uint32_t gpu_page_idx, + uint64_t addr, + uint32_t flags) +{ + void __iomem *ptr = (void *)cpu_pt_addr; + uint64_t value; + + value = addr & 0xFFFFFFFFFFFFF000ULL; + value |= flags; + writeq(value, ptr + (gpu_page_idx * 8)); + + return 0; +} + +/** + * gmc_v7_0_gart_enable - gart enable + * + * @adev: amdgpu_device pointer + * + * This sets up the TLBs, programs the page tables for VMID0, + * sets up the hw for VMIDs 1-15 which are allocated on + * demand, and sets up the global locations for the LDS, GDS, + * and GPUVM for FSA64 clients (CIK). + * Returns 0 for success, errors for failure. + */ +static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) +{ + int r, i; + u32 tmp; + + if (adev->gart.robj == NULL) { + dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); + return -EINVAL; + } + r = amdgpu_gart_table_vram_pin(adev); + if (r) + return r; + /* Setup TLB control */ + tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); + WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); + /* Setup L2 cache */ + tmp = RREG32(mmVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); + WREG32(mmVM_L2_CNTL, tmp); + tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); + WREG32(mmVM_L2_CNTL2, tmp); + tmp = RREG32(mmVM_L2_CNTL3); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); + WREG32(mmVM_L2_CNTL3, tmp); + /* setup context0 */ + WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); + WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(adev->dummy_page.addr >> 12)); + WREG32(mmVM_CONTEXT0_CNTL2, 0); + tmp = RREG32(mmVM_CONTEXT0_CNTL); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + WREG32(mmVM_CONTEXT0_CNTL, tmp); + + WREG32(0x575, 0); + WREG32(0x576, 0); + WREG32(0x577, 0); + + /* empty context1-15 */ + /* FIXME start with 4G, once using 2 level pt switch to full + * vm size space + */ + /* set vm size, must be a multiple of 4 */ + WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); + WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn); + for (i = 1; i < 16; i++) { + if (i < 8) + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, + adev->gart.table_addr >> 12); + else + WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, + adev->gart.table_addr >> 12); + } + + /* enable context1-15 */ + WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(adev->dummy_page.addr >> 12)); + WREG32(mmVM_CONTEXT1_CNTL2, 4); + tmp = RREG32(mmVM_CONTEXT1_CNTL); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, + amdgpu_vm_block_size - 9); + WREG32(mmVM_CONTEXT1_CNTL, tmp); + + if (adev->asic_type == CHIP_KAVERI) { + tmp = RREG32(mmCHUB_CONTROL); + tmp &= ~BYPASS_VM; + WREG32(mmCHUB_CONTROL, tmp); + } + + gmc_v7_0_gart_flush_gpu_tlb(adev, 0); + DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", + (unsigned)(adev->mc.gtt_size >> 20), + (unsigned long long)adev->gart.table_addr); + adev->gart.ready = true; + return 0; +} + +static int gmc_v7_0_gart_init(struct amdgpu_device *adev) +{ + int r; + + if (adev->gart.robj) { + WARN(1, "R600 PCIE GART already initialized\n"); + return 0; + } + /* Initialize common gart structure */ + r = amdgpu_gart_init(adev); + if (r) + return r; + adev->gart.table_size = adev->gart.num_gpu_pages * 8; + return amdgpu_gart_table_vram_alloc(adev); +} + +/** + * gmc_v7_0_gart_disable - gart disable + * + * @adev: amdgpu_device pointer + * + * This disables all VM page table (CIK). + */ +static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) +{ + u32 tmp; + + /* Disable all tables */ + WREG32(mmVM_CONTEXT0_CNTL, 0); + WREG32(mmVM_CONTEXT1_CNTL, 0); + /* Setup TLB control */ + tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); + WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); + /* Setup L2 cache */ + tmp = RREG32(mmVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); + WREG32(mmVM_L2_CNTL, tmp); + WREG32(mmVM_L2_CNTL2, 0); + amdgpu_gart_table_vram_unpin(adev); +} + +/** + * gmc_v7_0_gart_fini - vm fini callback + * + * @adev: amdgpu_device pointer + * + * Tears down the driver GART/VM setup (CIK). + */ +static void gmc_v7_0_gart_fini(struct amdgpu_device *adev) +{ + amdgpu_gart_table_vram_free(adev); + amdgpu_gart_fini(adev); +} + +/* + * vm + * VMID 0 is the physical GPU addresses as used by the kernel. + * VMIDs 1-15 are used for userspace clients and are handled + * by the amdgpu vm/hsa code. + */ +/** + * gmc_v7_0_vm_init - cik vm init callback + * + * @adev: amdgpu_device pointer + * + * Inits cik specific vm parameters (number of VMs, base of vram for + * VMIDs 1-15) (CIK). + * Returns 0 for success. + */ +static int gmc_v7_0_vm_init(struct amdgpu_device *adev) +{ + /* + * number of VMs + * VMID 0 is reserved for System + * amdgpu graphics/compute will use VMIDs 1-7 + * amdkfd will use VMIDs 8-15 + */ + adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS; + + /* base offset of vram pages */ + if (adev->flags & AMDGPU_IS_APU) { + u64 tmp = RREG32(mmMC_VM_FB_OFFSET); + tmp <<= 22; + adev->vm_manager.vram_base_offset = tmp; + } else + adev->vm_manager.vram_base_offset = 0; + + return 0; +} + +/** + * gmc_v7_0_vm_fini - cik vm fini callback + * + * @adev: amdgpu_device pointer + * + * Tear down any asic specific VM setup (CIK). + */ +static void gmc_v7_0_vm_fini(struct amdgpu_device *adev) +{ +} + +/** + * gmc_v7_0_vm_decode_fault - print human readable fault info + * + * @adev: amdgpu_device pointer + * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value + * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value + * + * Print human readable fault information (CIK). + */ +static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, + u32 status, u32 addr, u32 mc_client) +{ + u32 mc_id; + u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); + u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + PROTECTIONS); + char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, + (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; + + mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + MEMORY_CLIENT_ID); + + printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", + protections, vmid, addr, + REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + MEMORY_CLIENT_RW) ? + "write" : "read", block, mc_client, mc_id); +} + + +static const u32 mc_cg_registers[] = { + mmMC_HUB_MISC_HUB_CG, + mmMC_HUB_MISC_SIP_CG, + mmMC_HUB_MISC_VM_CG, + mmMC_XPB_CLK_GAT, + mmATC_MISC_CG, + mmMC_CITF_MISC_WR_CG, + mmMC_CITF_MISC_RD_CG, + mmMC_CITF_MISC_VM_CG, + mmVM_L2_CG, +}; + +static const u32 mc_cg_ls_en[] = { + MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, + MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, + MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, + MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, + ATC_MISC_CG__MEM_LS_ENABLE_MASK, + MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, + MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, + MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, + VM_L2_CG__MEM_LS_ENABLE_MASK, +}; + +static const u32 mc_cg_en[] = { + MC_HUB_MISC_HUB_CG__ENABLE_MASK, + MC_HUB_MISC_SIP_CG__ENABLE_MASK, + MC_HUB_MISC_VM_CG__ENABLE_MASK, + MC_XPB_CLK_GAT__ENABLE_MASK, + ATC_MISC_CG__ENABLE_MASK, + MC_CITF_MISC_WR_CG__ENABLE_MASK, + MC_CITF_MISC_RD_CG__ENABLE_MASK, + MC_CITF_MISC_VM_CG__ENABLE_MASK, + VM_L2_CG__ENABLE_MASK, +}; + +static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, + bool enable) +{ + int i; + u32 orig, data; + + for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { + orig = data = RREG32(mc_cg_registers[i]); + if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) + data |= mc_cg_ls_en[i]; + else + data &= ~mc_cg_ls_en[i]; + if (data != orig) + WREG32(mc_cg_registers[i], data); + } +} + +static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, + bool enable) +{ + int i; + u32 orig, data; + + for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { + orig = data = RREG32(mc_cg_registers[i]); + if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) + data |= mc_cg_en[i]; + else + data &= ~mc_cg_en[i]; + if (data != orig) + WREG32(mc_cg_registers[i], data); + } +} + +static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, + bool enable) +{ + u32 orig, data; + + orig = data = RREG32_PCIE(ixPCIE_CNTL2); + + if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { + data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); + data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); + data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); + data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); + } else { + data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); + data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); + data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); + data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); + } + + if (orig != data) + WREG32_PCIE(ixPCIE_CNTL2, data); +} + +static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, + bool enable) +{ + u32 orig, data; + + orig = data = RREG32(mmHDP_HOST_PATH_CNTL); + + if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) + data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); + else + data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); + + if (orig != data) + WREG32(mmHDP_HOST_PATH_CNTL, data); +} + +static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, + bool enable) +{ + u32 orig, data; + + orig = data = RREG32(mmHDP_MEM_POWER_LS); + + if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) + data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); + else + data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); + + if (orig != data) + WREG32(mmHDP_MEM_POWER_LS, data); +} + +static int gmc_v7_0_early_init(struct amdgpu_device *adev) +{ + gmc_v7_0_set_gart_funcs(adev); + gmc_v7_0_set_irq_funcs(adev); + + if (adev->flags & AMDGPU_IS_APU) { + adev->mc.is_gddr5 = false; + } else { + u32 tmp = RREG32(mmMC_SEQ_MISC0); + + if (((tmp & MC_SEQ_MISC0__GDDR5_MASK) >> + MC_SEQ_MISC0__GDDR5__SHIFT) == MC_SEQ_MISC0__GDDR5_VALUE) + adev->mc.is_gddr5 = true; + else + adev->mc.is_gddr5 = false; + } + + return 0; +} + +static int gmc_v7_0_sw_init(struct amdgpu_device *adev) +{ + int r; + int dma_bits; + + r = amdgpu_gem_init(adev); + if (r) + return r; + + r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); + if (r) + return r; + + r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault); + if (r) + return r; + + /* Adjust VM size here. + * Currently set to 4GB ((1 << 20) 4k pages). + * Max GPUVM size for cayman and SI is 40 bits. + */ + adev->vm_manager.max_pfn = amdgpu_vm_size << 18; + + /* Set the internal MC address mask + * This is the max address of the GPU's + * internal address space. + */ + adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ + + /* set DMA mask + need_dma32 flags. + * PCIE - can handle 40-bits. + * IGP - can handle 40-bits + * PCI - dma32 for legacy pci gart, 40 bits on newer asics + */ + adev->need_dma32 = false; + dma_bits = adev->need_dma32 ? 32 : 40; + r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); + if (r) { + adev->need_dma32 = true; + dma_bits = 32; + printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); + } + r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); + if (r) { + pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); + printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); + } + + r = gmc_v7_0_init_microcode(adev); + if (r) { + DRM_ERROR("Failed to load mc firmware!\n"); + return r; + } + + r = gmc_v7_0_mc_init(adev); + if (r) + return r; + + /* Memory manager */ + r = amdgpu_bo_init(adev); + if (r) + return r; + + r = gmc_v7_0_gart_init(adev); + if (r) + return r; + + if (!adev->vm_manager.enabled) { + r = gmc_v7_0_vm_init(adev); + if (r) { + dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); + return r; + } + adev->vm_manager.enabled = true; + } + + return r; +} + +static int gmc_v7_0_sw_fini(struct amdgpu_device *adev) +{ + int i; + + if (adev->vm_manager.enabled) { + for (i = 0; i < AMDGPU_NUM_VM; ++i) + amdgpu_fence_unref(&adev->vm_manager.active[i]); + gmc_v7_0_vm_fini(adev); + adev->vm_manager.enabled = false; + } + gmc_v7_0_gart_fini(adev); + amdgpu_gem_fini(adev); + amdgpu_bo_fini(adev); + + return 0; +} + +static int gmc_v7_0_hw_init(struct amdgpu_device *adev) +{ + int r; + + gmc_v7_0_mc_program(adev); + + if (!(adev->flags & AMDGPU_IS_APU)) { + r = gmc_v7_0_mc_load_microcode(adev); + if (r) { + DRM_ERROR("Failed to load MC firmware!\n"); + return r; + } + } + + r = gmc_v7_0_gart_enable(adev); + if (r) + return r; + + return r; +} + +static int gmc_v7_0_hw_fini(struct amdgpu_device *adev) +{ + gmc_v7_0_gart_disable(adev); + + return 0; +} + +static int gmc_v7_0_suspend(struct amdgpu_device *adev) +{ + int i; + + if (adev->vm_manager.enabled) { + for (i = 0; i < AMDGPU_NUM_VM; ++i) + amdgpu_fence_unref(&adev->vm_manager.active[i]); + gmc_v7_0_vm_fini(adev); + adev->vm_manager.enabled = false; + } + gmc_v7_0_hw_fini(adev); + + return 0; +} + +static int gmc_v7_0_resume(struct amdgpu_device *adev) +{ + int r; + + r = gmc_v7_0_hw_init(adev); + if (r) + return r; + + if (!adev->vm_manager.enabled) { + r = gmc_v7_0_vm_init(adev); + if (r) { + dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); + return r; + } + adev->vm_manager.enabled = true; + } + + return r; +} + +static bool gmc_v7_0_is_idle(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmSRBM_STATUS); + + if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | + SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) + return false; + + return true; +} + +static int gmc_v7_0_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | + SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | + SRBM_STATUS__MCC_BUSY_MASK | + SRBM_STATUS__MCD_BUSY_MASK | + SRBM_STATUS__VMC_BUSY_MASK); + if (!tmp) + return 0; + udelay(1); + } + return -ETIMEDOUT; + +} + +static void gmc_v7_0_print_status(struct amdgpu_device *adev) +{ + int i, j; + + dev_info(adev->dev, "GMC 8.x registers\n"); + dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", + RREG32(mmSRBM_STATUS)); + dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", + RREG32(mmSRBM_STATUS2)); + + dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); + dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); + dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n", + RREG32(mmMC_VM_MX_L1_TLB_CNTL)); + dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n", + RREG32(mmVM_L2_CNTL)); + dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n", + RREG32(mmVM_L2_CNTL2)); + dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n", + RREG32(mmVM_L2_CNTL3)); + dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)); + dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)); + dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)); + dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n", + RREG32(mmVM_CONTEXT0_CNTL2)); + dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n", + RREG32(mmVM_CONTEXT0_CNTL)); + dev_info(adev->dev, " 0x15D4=0x%08X\n", + RREG32(0x575)); + dev_info(adev->dev, " 0x15D8=0x%08X\n", + RREG32(0x576)); + dev_info(adev->dev, " 0x15DC=0x%08X\n", + RREG32(0x577)); + dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)); + dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)); + dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)); + dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n", + RREG32(mmVM_CONTEXT1_CNTL2)); + dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n", + RREG32(mmVM_CONTEXT1_CNTL)); + for (i = 0; i < 16; i++) { + if (i < 8) + dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", + i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i)); + else + dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", + i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8)); + } + dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n", + RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)); + dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n", + RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)); + dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n", + RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)); + dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n", + RREG32(mmMC_VM_FB_LOCATION)); + dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n", + RREG32(mmMC_VM_AGP_BASE)); + dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n", + RREG32(mmMC_VM_AGP_TOP)); + dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n", + RREG32(mmMC_VM_AGP_BOT)); + + if (adev->asic_type == CHIP_KAVERI) { + dev_info(adev->dev, " CHUB_CONTROL=0x%08X\n", + RREG32(mmCHUB_CONTROL)); + } + + dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n", + RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL)); + dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n", + RREG32(mmHDP_NONSURFACE_BASE)); + dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n", + RREG32(mmHDP_NONSURFACE_INFO)); + dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n", + RREG32(mmHDP_NONSURFACE_SIZE)); + dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n", + RREG32(mmHDP_MISC_CNTL)); + dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n", + RREG32(mmHDP_HOST_PATH_CNTL)); + + for (i = 0, j = 0; i < 32; i++, j += 0x6) { + dev_info(adev->dev, " %d:\n", i); + dev_info(adev->dev, " 0x%04X=0x%08X\n", + 0xb05 + j, RREG32(0xb05 + j)); + dev_info(adev->dev, " 0x%04X=0x%08X\n", + 0xb06 + j, RREG32(0xb06 + j)); + dev_info(adev->dev, " 0x%04X=0x%08X\n", + 0xb07 + j, RREG32(0xb07 + j)); + dev_info(adev->dev, " 0x%04X=0x%08X\n", + 0xb08 + j, RREG32(0xb08 + j)); + dev_info(adev->dev, " 0x%04X=0x%08X\n", + 0xb09 + j, RREG32(0xb09 + j)); + } + + dev_info(adev->dev, " BIF_FB_EN=0x%08X\n", + RREG32(mmBIF_FB_EN)); +} + +static int gmc_v7_0_soft_reset(struct amdgpu_device *adev) +{ + struct amdgpu_mode_mc_save save; + u32 srbm_soft_reset = 0; + u32 tmp = RREG32(mmSRBM_STATUS); + + if (tmp & SRBM_STATUS__VMC_BUSY_MASK) + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, + SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); + + if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | + SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { + if (!(adev->flags & AMDGPU_IS_APU)) + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, + SRBM_SOFT_RESET, SOFT_RESET_MC, 1); + } + + if (srbm_soft_reset) { + gmc_v7_0_print_status(adev); + + gmc_v7_0_mc_stop(adev, &save); + if (gmc_v7_0_wait_for_idle(adev)) { + dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); + } + + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + + gmc_v7_0_mc_resume(adev, &save); + udelay(50); + + gmc_v7_0_print_status(adev); + } + + return 0; +} + +static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 tmp; + u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + /* system context */ + tmp = RREG32(mmVM_CONTEXT0_CNTL); + tmp &= ~bits; + WREG32(mmVM_CONTEXT0_CNTL, tmp); + /* VMs */ + tmp = RREG32(mmVM_CONTEXT1_CNTL); + tmp &= ~bits; + WREG32(mmVM_CONTEXT1_CNTL, tmp); + break; + case AMDGPU_IRQ_STATE_ENABLE: + /* system context */ + tmp = RREG32(mmVM_CONTEXT0_CNTL); + tmp |= bits; + WREG32(mmVM_CONTEXT0_CNTL, tmp); + /* VMs */ + tmp = RREG32(mmVM_CONTEXT1_CNTL); + tmp |= bits; + WREG32(mmVM_CONTEXT1_CNTL, tmp); + break; + default: + break; + } + + return 0; +} + +static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + u32 addr, status, mc_client; + + addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); + status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); + mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); + dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", + entry->src_id, entry->src_data); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + addr); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + status); + gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client); + /* reset addr and status */ + WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); + + return 0; +} + +static int gmc_v7_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + bool gate = false; + + if (state == AMDGPU_CG_STATE_GATE) + gate = true; + + if (!(adev->flags & AMDGPU_IS_APU)) { + gmc_v7_0_enable_mc_mgcg(adev, gate); + gmc_v7_0_enable_mc_ls(adev, gate); + } + gmc_v7_0_enable_bif_mgls(adev, gate); + gmc_v7_0_enable_hdp_mgcg(adev, gate); + gmc_v7_0_enable_hdp_ls(adev, gate); + + return 0; +} + +static int gmc_v7_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs gmc_v7_0_ip_funcs = { + .early_init = gmc_v7_0_early_init, + .late_init = NULL, + .sw_init = gmc_v7_0_sw_init, + .sw_fini = gmc_v7_0_sw_fini, + .hw_init = gmc_v7_0_hw_init, + .hw_fini = gmc_v7_0_hw_fini, + .suspend = gmc_v7_0_suspend, + .resume = gmc_v7_0_resume, + .is_idle = gmc_v7_0_is_idle, + .wait_for_idle = gmc_v7_0_wait_for_idle, + .soft_reset = gmc_v7_0_soft_reset, + .print_status = gmc_v7_0_print_status, + .set_clockgating_state = gmc_v7_0_set_clockgating_state, + .set_powergating_state = gmc_v7_0_set_powergating_state, +}; + +static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = { + .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb, + .set_pte_pde = gmc_v7_0_gart_set_pte_pde, +}; + +static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { + .set = gmc_v7_0_vm_fault_interrupt_state, + .process = gmc_v7_0_process_interrupt, +}; + +static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev) +{ + if (adev->gart.gart_funcs == NULL) + adev->gart.gart_funcs = &gmc_v7_0_gart_funcs; +} + +static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->mc.vm_fault.num_types = 1; + adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h new file mode 100644 index 000000000000..ab1a2fa1afcd --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h @@ -0,0 +1,36 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __GMC_V7_0_H__ +#define __GMC_V7_0_H__ + +extern const struct amdgpu_ip_funcs gmc_v7_0_ip_funcs; + +/* XXX these shouldn't be exported */ +void gmc_v7_0_mc_stop(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save); +void gmc_v7_0_mc_resume(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save); +int gmc_v7_0_mc_wait_for_idle(struct amdgpu_device *adev); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c new file mode 100644 index 000000000000..cd902419e6a1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c @@ -0,0 +1,3336 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_pm.h" +#include "cikd.h" +#include "atom.h" +#include "amdgpu_atombios.h" +#include "amdgpu_dpm.h" +#include "kv_dpm.h" +#include "gfx_v7_0.h" +#include + +#include "smu/smu_7_0_0_d.h" +#include "smu/smu_7_0_0_sh_mask.h" + +#include "gca/gfx_7_2_d.h" +#include "gca/gfx_7_2_sh_mask.h" + +#define KV_MAX_DEEPSLEEP_DIVIDER_ID 5 +#define KV_MINIMUM_ENGINE_CLOCK 800 +#define SMC_RAM_END 0x40000 + +static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev); +static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev); +static int kv_enable_nb_dpm(struct amdgpu_device *adev, + bool enable); +static void kv_init_graphics_levels(struct amdgpu_device *adev); +static int kv_calculate_ds_divider(struct amdgpu_device *adev); +static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev); +static int kv_calculate_dpm_settings(struct amdgpu_device *adev); +static void kv_enable_new_levels(struct amdgpu_device *adev); +static void kv_program_nbps_index_settings(struct amdgpu_device *adev, + struct amdgpu_ps *new_rps); +static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level); +static int kv_set_enabled_levels(struct amdgpu_device *adev); +static int kv_force_dpm_highest(struct amdgpu_device *adev); +static int kv_force_dpm_lowest(struct amdgpu_device *adev); +static void kv_apply_state_adjust_rules(struct amdgpu_device *adev, + struct amdgpu_ps *new_rps, + struct amdgpu_ps *old_rps); +static int kv_set_thermal_temperature_range(struct amdgpu_device *adev, + int min_temp, int max_temp); +static int kv_init_fps_limits(struct amdgpu_device *adev); + +static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate); +static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate); +static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate); +static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate); + + +static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev, + struct sumo_vid_mapping_table *vid_mapping_table, + u32 vid_2bit) +{ + struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + u32 i; + + if (vddc_sclk_table && vddc_sclk_table->count) { + if (vid_2bit < vddc_sclk_table->count) + return vddc_sclk_table->entries[vid_2bit].v; + else + return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v; + } else { + for (i = 0; i < vid_mapping_table->num_entries; i++) { + if (vid_mapping_table->entries[i].vid_2bit == vid_2bit) + return vid_mapping_table->entries[i].vid_7bit; + } + return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit; + } +} + +static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev, + struct sumo_vid_mapping_table *vid_mapping_table, + u32 vid_7bit) +{ + struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + u32 i; + + if (vddc_sclk_table && vddc_sclk_table->count) { + for (i = 0; i < vddc_sclk_table->count; i++) { + if (vddc_sclk_table->entries[i].v == vid_7bit) + return i; + } + return vddc_sclk_table->count - 1; + } else { + for (i = 0; i < vid_mapping_table->num_entries; i++) { + if (vid_mapping_table->entries[i].vid_7bit == vid_7bit) + return vid_mapping_table->entries[i].vid_2bit; + } + + return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit; + } +} + +static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable) +{ +/* This bit selects who handles display phy powergating. + * Clear the bit to let atom handle it. + * Set it to let the driver handle it. + * For now we just let atom handle it. + */ +#if 0 + u32 v = RREG32(mmDOUT_SCRATCH3); + + if (enable) + v |= 0x4; + else + v &= 0xFFFFFFFB; + + WREG32(mmDOUT_SCRATCH3, v); +#endif +} + +static u32 sumo_get_sleep_divider_from_id(u32 id) +{ + return 1 << id; +} + +static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev, + struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, + ATOM_AVAILABLE_SCLK_LIST *table) +{ + u32 i; + u32 n = 0; + u32 prev_sclk = 0; + + for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { + if (table[i].ulSupportedSCLK > prev_sclk) { + sclk_voltage_mapping_table->entries[n].sclk_frequency = + table[i].ulSupportedSCLK; + sclk_voltage_mapping_table->entries[n].vid_2bit = + table[i].usVoltageIndex; + prev_sclk = table[i].ulSupportedSCLK; + n++; + } + } + + sclk_voltage_mapping_table->num_max_dpm_entries = n; +} + +static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev, + struct sumo_vid_mapping_table *vid_mapping_table, + ATOM_AVAILABLE_SCLK_LIST *table) +{ + u32 i, j; + + for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { + if (table[i].ulSupportedSCLK != 0) { + vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit = + table[i].usVoltageID; + vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit = + table[i].usVoltageIndex; + } + } + + for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { + if (vid_mapping_table->entries[i].vid_7bit == 0) { + for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) { + if (vid_mapping_table->entries[j].vid_7bit != 0) { + vid_mapping_table->entries[i] = + vid_mapping_table->entries[j]; + vid_mapping_table->entries[j].vid_7bit = 0; + break; + } + } + + if (j == SUMO_MAX_NUMBER_VOLTAGES) + break; + } + } + + vid_mapping_table->num_entries = i; +} + +static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] = +{ + { 0, 4, 1 }, + { 1, 4, 1 }, + { 2, 5, 1 }, + { 3, 4, 2 }, + { 4, 1, 1 }, + { 5, 5, 2 }, + { 6, 6, 1 }, + { 7, 9, 2 }, + { 0xffffffff } +}; + +static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] = +{ + { 0, 4, 1 }, + { 0xffffffff } +}; + +static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] = +{ + { 0, 4, 1 }, + { 0xffffffff } +}; + +static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] = +{ + { 0, 4, 1 }, + { 0xffffffff } +}; + +static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] = +{ + { 0, 4, 1 }, + { 0xffffffff } +}; + +static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] = +{ + { 0, 4, 1 }, + { 1, 4, 1 }, + { 2, 5, 1 }, + { 3, 4, 1 }, + { 4, 1, 1 }, + { 5, 5, 1 }, + { 6, 6, 1 }, + { 7, 9, 1 }, + { 8, 4, 1 }, + { 9, 2, 1 }, + { 10, 3, 1 }, + { 11, 6, 1 }, + { 12, 8, 2 }, + { 13, 1, 1 }, + { 14, 2, 1 }, + { 15, 3, 1 }, + { 16, 1, 1 }, + { 17, 4, 1 }, + { 18, 3, 1 }, + { 19, 1, 1 }, + { 20, 8, 1 }, + { 21, 5, 1 }, + { 22, 1, 1 }, + { 23, 1, 1 }, + { 24, 4, 1 }, + { 27, 6, 1 }, + { 28, 1, 1 }, + { 0xffffffff } +}; + +static const struct kv_lcac_config_reg sx0_cac_config_reg[] = +{ + { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } +}; + +static const struct kv_lcac_config_reg mc0_cac_config_reg[] = +{ + { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } +}; + +static const struct kv_lcac_config_reg mc1_cac_config_reg[] = +{ + { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } +}; + +static const struct kv_lcac_config_reg mc2_cac_config_reg[] = +{ + { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } +}; + +static const struct kv_lcac_config_reg mc3_cac_config_reg[] = +{ + { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } +}; + +static const struct kv_lcac_config_reg cpl_cac_config_reg[] = +{ + { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } +}; + +static const struct kv_pt_config_reg didt_config_kv[] = +{ + { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, + { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, + { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, + { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, + { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, + { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, + { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, + { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, + { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, + { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, + { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, + { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, + { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, + { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, + { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, + { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, + { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, + { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, + { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, + { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, + { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, + { 0xFFFFFFFF } +}; + +static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps) +{ + struct kv_ps *ps = rps->ps_priv; + + return ps; +} + +static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = adev->pm.dpm.priv; + + return pi; +} + +#if 0 +static void kv_program_local_cac_table(struct amdgpu_device *adev, + const struct kv_lcac_config_values *local_cac_table, + const struct kv_lcac_config_reg *local_cac_reg) +{ + u32 i, count, data; + const struct kv_lcac_config_values *values = local_cac_table; + + while (values->block_id != 0xffffffff) { + count = values->signal_id; + for (i = 0; i < count; i++) { + data = ((values->block_id << local_cac_reg->block_shift) & + local_cac_reg->block_mask); + data |= ((i << local_cac_reg->signal_shift) & + local_cac_reg->signal_mask); + data |= ((values->t << local_cac_reg->t_shift) & + local_cac_reg->t_mask); + data |= ((1 << local_cac_reg->enable_shift) & + local_cac_reg->enable_mask); + WREG32_SMC(local_cac_reg->cntl, data); + } + values++; + } +} +#endif + +static int kv_program_pt_config_registers(struct amdgpu_device *adev, + const struct kv_pt_config_reg *cac_config_regs) +{ + const struct kv_pt_config_reg *config_regs = cac_config_regs; + u32 data; + u32 cache = 0; + + if (config_regs == NULL) + return -EINVAL; + + while (config_regs->offset != 0xFFFFFFFF) { + if (config_regs->type == KV_CONFIGREG_CACHE) { + cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); + } else { + switch (config_regs->type) { + case KV_CONFIGREG_SMC_IND: + data = RREG32_SMC(config_regs->offset); + break; + case KV_CONFIGREG_DIDT_IND: + data = RREG32_DIDT(config_regs->offset); + break; + default: + data = RREG32(config_regs->offset); + break; + } + + data &= ~config_regs->mask; + data |= ((config_regs->value << config_regs->shift) & config_regs->mask); + data |= cache; + cache = 0; + + switch (config_regs->type) { + case KV_CONFIGREG_SMC_IND: + WREG32_SMC(config_regs->offset, data); + break; + case KV_CONFIGREG_DIDT_IND: + WREG32_DIDT(config_regs->offset, data); + break; + default: + WREG32(config_regs->offset, data); + break; + } + } + config_regs++; + } + + return 0; +} + +static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 data; + + if (pi->caps_sq_ramping) { + data = RREG32_DIDT(ixDIDT_SQ_CTRL0); + if (enable) + data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; + else + data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; + WREG32_DIDT(ixDIDT_SQ_CTRL0, data); + } + + if (pi->caps_db_ramping) { + data = RREG32_DIDT(ixDIDT_DB_CTRL0); + if (enable) + data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; + else + data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; + WREG32_DIDT(ixDIDT_DB_CTRL0, data); + } + + if (pi->caps_td_ramping) { + data = RREG32_DIDT(ixDIDT_TD_CTRL0); + if (enable) + data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; + else + data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; + WREG32_DIDT(ixDIDT_TD_CTRL0, data); + } + + if (pi->caps_tcp_ramping) { + data = RREG32_DIDT(ixDIDT_TCP_CTRL0); + if (enable) + data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; + else + data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; + WREG32_DIDT(ixDIDT_TCP_CTRL0, data); + } +} + +static int kv_enable_didt(struct amdgpu_device *adev, bool enable) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret; + + if (pi->caps_sq_ramping || + pi->caps_db_ramping || + pi->caps_td_ramping || + pi->caps_tcp_ramping) { + gfx_v7_0_enter_rlc_safe_mode(adev); + + if (enable) { + ret = kv_program_pt_config_registers(adev, didt_config_kv); + if (ret) { + gfx_v7_0_exit_rlc_safe_mode(adev); + return ret; + } + } + + kv_do_enable_didt(adev, enable); + + gfx_v7_0_exit_rlc_safe_mode(adev); + } + + return 0; +} + +#if 0 +static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + if (pi->caps_cac) { + WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0); + WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0); + kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg); + + WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0); + WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0); + kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg); + + WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0); + WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0); + kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg); + + WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0); + WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0); + kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg); + + WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0); + WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0); + kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg); + + WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0); + WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0); + kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg); + } +} +#endif + +static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret = 0; + + if (pi->caps_cac) { + if (enable) { + ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac); + if (ret) + pi->cac_enabled = false; + else + pi->cac_enabled = true; + } else if (pi->cac_enabled) { + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac); + pi->cac_enabled = false; + } + } + + return ret; +} + +static int kv_process_firmware_header(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 tmp; + int ret; + + ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, DpmTable), + &tmp, pi->sram_end); + + if (ret == 0) + pi->dpm_table_start = tmp; + + ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + + offsetof(SMU7_Firmware_Header, SoftRegisters), + &tmp, pi->sram_end); + + if (ret == 0) + pi->soft_regs_start = tmp; + + return ret; +} + +static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret; + + pi->graphics_voltage_change_enable = 1; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable), + &pi->graphics_voltage_change_enable, + sizeof(u8), pi->sram_end); + + return ret; +} + +static int kv_set_dpm_interval(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret; + + pi->graphics_interval = 1; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, GraphicsInterval), + &pi->graphics_interval, + sizeof(u8), pi->sram_end); + + return ret; +} + +static int kv_set_dpm_boot_state(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel), + &pi->graphics_boot_level, + sizeof(u8), pi->sram_end); + + return ret; +} + +static void kv_program_vc(struct amdgpu_device *adev) +{ + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100); +} + +static void kv_clear_vc(struct amdgpu_device *adev) +{ + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0); +} + +static int kv_set_divider_value(struct amdgpu_device *adev, + u32 index, u32 sclk) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct atom_clock_dividers dividers; + int ret; + + ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, + sclk, false, ÷rs); + if (ret) + return ret; + + pi->graphics_level[index].SclkDid = (u8)dividers.post_div; + pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); + + return 0; +} + +static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev, + u16 voltage) +{ + return 6200 - (voltage * 25); +} + +static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev, + u32 vid_2bit) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 vid_8bit = kv_convert_vid2_to_vid7(adev, + &pi->sys_info.vid_mapping_table, + vid_2bit); + + return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit); +} + + +static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; + pi->graphics_level[index].MinVddNb = + cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid)); + + return 0; +} + +static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + pi->graphics_level[index].AT = cpu_to_be16((u16)at); + + return 0; +} + +static void kv_dpm_power_level_enable(struct amdgpu_device *adev, + u32 index, bool enable) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; +} + +static void kv_start_dpm(struct amdgpu_device *adev) +{ + u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT); + + tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK; + WREG32_SMC(ixGENERAL_PWRMGT, tmp); + + amdgpu_kv_smc_dpm_enable(adev, true); +} + +static void kv_stop_dpm(struct amdgpu_device *adev) +{ + amdgpu_kv_smc_dpm_enable(adev, false); +} + +static void kv_start_am(struct amdgpu_device *adev) +{ + u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); + + sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | + SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK); + sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK; + + WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); +} + +static void kv_reset_am(struct amdgpu_device *adev) +{ + u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); + + sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | + SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK); + + WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); +} + +static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze) +{ + return amdgpu_kv_notify_message_to_smu(adev, freeze ? + PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel); +} + +static int kv_force_lowest_valid(struct amdgpu_device *adev) +{ + return kv_force_dpm_lowest(adev); +} + +static int kv_unforce_levels(struct amdgpu_device *adev) +{ + if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) + return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel); + else + return kv_set_enabled_levels(adev); +} + +static int kv_update_sclk_t(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 low_sclk_interrupt_t = 0; + int ret = 0; + + if (pi->caps_sclk_throttle_low_notification) { + low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT), + (u8 *)&low_sclk_interrupt_t, + sizeof(u32), pi->sram_end); + } + return ret; +} + +static int kv_program_bootup_state(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 i; + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + + if (table && table->count) { + for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { + if (table->entries[i].clk == pi->boot_pl.sclk) + break; + } + + pi->graphics_boot_level = (u8)i; + kv_dpm_power_level_enable(adev, i, true); + } else { + struct sumo_sclk_voltage_mapping_table *table = + &pi->sys_info.sclk_voltage_mapping_table; + + if (table->num_max_dpm_entries == 0) + return -EINVAL; + + for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { + if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) + break; + } + + pi->graphics_boot_level = (u8)i; + kv_dpm_power_level_enable(adev, i, true); + } + return 0; +} + +static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret; + + pi->graphics_therm_throttle_enable = 1; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable), + &pi->graphics_therm_throttle_enable, + sizeof(u8), pi->sram_end); + + return ret; +} + +static int kv_upload_dpm_settings(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, GraphicsLevel), + (u8 *)&pi->graphics_level, + sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS, + pi->sram_end); + + if (ret) + return ret; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount), + &pi->graphics_dpm_level_count, + sizeof(u8), pi->sram_end); + + return ret; +} + +static u32 kv_get_clock_difference(u32 a, u32 b) +{ + return (a >= b) ? a - b : b - a; +} + +static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 value; + + if (pi->caps_enable_dfs_bypass) { + if (kv_get_clock_difference(clk, 40000) < 200) + value = 3; + else if (kv_get_clock_difference(clk, 30000) < 200) + value = 2; + else if (kv_get_clock_difference(clk, 20000) < 200) + value = 7; + else if (kv_get_clock_difference(clk, 15000) < 200) + value = 6; + else if (kv_get_clock_difference(clk, 10000) < 200) + value = 8; + else + value = 0; + } else { + value = 0; + } + + return value; +} + +static int kv_populate_uvd_table(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_uvd_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; + struct atom_clock_dividers dividers; + int ret; + u32 i; + + if (table == NULL || table->count == 0) + return 0; + + pi->uvd_level_count = 0; + for (i = 0; i < table->count; i++) { + if (pi->high_voltage_t && + (pi->high_voltage_t < table->entries[i].v)) + break; + + pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); + pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); + pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); + + pi->uvd_level[i].VClkBypassCntl = + (u8)kv_get_clk_bypass(adev, table->entries[i].vclk); + pi->uvd_level[i].DClkBypassCntl = + (u8)kv_get_clk_bypass(adev, table->entries[i].dclk); + + ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, + table->entries[i].vclk, false, ÷rs); + if (ret) + return ret; + pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; + + ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, + table->entries[i].dclk, false, ÷rs); + if (ret) + return ret; + pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; + + pi->uvd_level_count++; + } + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, UvdLevelCount), + (u8 *)&pi->uvd_level_count, + sizeof(u8), pi->sram_end); + if (ret) + return ret; + + pi->uvd_interval = 1; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, UVDInterval), + &pi->uvd_interval, + sizeof(u8), pi->sram_end); + if (ret) + return ret; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, UvdLevel), + (u8 *)&pi->uvd_level, + sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD, + pi->sram_end); + + return ret; + +} + +static int kv_populate_vce_table(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret; + u32 i; + struct amdgpu_vce_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + struct atom_clock_dividers dividers; + + if (table == NULL || table->count == 0) + return 0; + + pi->vce_level_count = 0; + for (i = 0; i < table->count; i++) { + if (pi->high_voltage_t && + pi->high_voltage_t < table->entries[i].v) + break; + + pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); + pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); + + pi->vce_level[i].ClkBypassCntl = + (u8)kv_get_clk_bypass(adev, table->entries[i].evclk); + + ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, + table->entries[i].evclk, false, ÷rs); + if (ret) + return ret; + pi->vce_level[i].Divider = (u8)dividers.post_div; + + pi->vce_level_count++; + } + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, VceLevelCount), + (u8 *)&pi->vce_level_count, + sizeof(u8), + pi->sram_end); + if (ret) + return ret; + + pi->vce_interval = 1; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, VCEInterval), + (u8 *)&pi->vce_interval, + sizeof(u8), + pi->sram_end); + if (ret) + return ret; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, VceLevel), + (u8 *)&pi->vce_level, + sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE, + pi->sram_end); + + return ret; +} + +static int kv_populate_samu_table(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; + struct atom_clock_dividers dividers; + int ret; + u32 i; + + if (table == NULL || table->count == 0) + return 0; + + pi->samu_level_count = 0; + for (i = 0; i < table->count; i++) { + if (pi->high_voltage_t && + pi->high_voltage_t < table->entries[i].v) + break; + + pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); + pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); + + pi->samu_level[i].ClkBypassCntl = + (u8)kv_get_clk_bypass(adev, table->entries[i].clk); + + ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, + table->entries[i].clk, false, ÷rs); + if (ret) + return ret; + pi->samu_level[i].Divider = (u8)dividers.post_div; + + pi->samu_level_count++; + } + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, SamuLevelCount), + (u8 *)&pi->samu_level_count, + sizeof(u8), + pi->sram_end); + if (ret) + return ret; + + pi->samu_interval = 1; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, SAMUInterval), + (u8 *)&pi->samu_interval, + sizeof(u8), + pi->sram_end); + if (ret) + return ret; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, SamuLevel), + (u8 *)&pi->samu_level, + sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU, + pi->sram_end); + if (ret) + return ret; + + return ret; +} + + +static int kv_populate_acp_table(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; + struct atom_clock_dividers dividers; + int ret; + u32 i; + + if (table == NULL || table->count == 0) + return 0; + + pi->acp_level_count = 0; + for (i = 0; i < table->count; i++) { + pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); + pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); + + ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, + table->entries[i].clk, false, ÷rs); + if (ret) + return ret; + pi->acp_level[i].Divider = (u8)dividers.post_div; + + pi->acp_level_count++; + } + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, AcpLevelCount), + (u8 *)&pi->acp_level_count, + sizeof(u8), + pi->sram_end); + if (ret) + return ret; + + pi->acp_interval = 1; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, ACPInterval), + (u8 *)&pi->acp_interval, + sizeof(u8), + pi->sram_end); + if (ret) + return ret; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, AcpLevel), + (u8 *)&pi->acp_level, + sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP, + pi->sram_end); + if (ret) + return ret; + + return ret; +} + +static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 i; + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + + if (table && table->count) { + for (i = 0; i < pi->graphics_dpm_level_count; i++) { + if (pi->caps_enable_dfs_bypass) { + if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200) + pi->graphics_level[i].ClkBypassCntl = 3; + else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200) + pi->graphics_level[i].ClkBypassCntl = 2; + else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200) + pi->graphics_level[i].ClkBypassCntl = 7; + else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200) + pi->graphics_level[i].ClkBypassCntl = 6; + else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200) + pi->graphics_level[i].ClkBypassCntl = 8; + else + pi->graphics_level[i].ClkBypassCntl = 0; + } else { + pi->graphics_level[i].ClkBypassCntl = 0; + } + } + } else { + struct sumo_sclk_voltage_mapping_table *table = + &pi->sys_info.sclk_voltage_mapping_table; + for (i = 0; i < pi->graphics_dpm_level_count; i++) { + if (pi->caps_enable_dfs_bypass) { + if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200) + pi->graphics_level[i].ClkBypassCntl = 3; + else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200) + pi->graphics_level[i].ClkBypassCntl = 2; + else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200) + pi->graphics_level[i].ClkBypassCntl = 7; + else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200) + pi->graphics_level[i].ClkBypassCntl = 6; + else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200) + pi->graphics_level[i].ClkBypassCntl = 8; + else + pi->graphics_level[i].ClkBypassCntl = 0; + } else { + pi->graphics_level[i].ClkBypassCntl = 0; + } + } + } +} + +static int kv_enable_ulv(struct amdgpu_device *adev, bool enable) +{ + return amdgpu_kv_notify_message_to_smu(adev, enable ? + PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV); +} + +static void kv_reset_acp_boot_level(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + pi->acp_boot_level = 0xff; +} + +static void kv_update_current_ps(struct amdgpu_device *adev, + struct amdgpu_ps *rps) +{ + struct kv_ps *new_ps = kv_get_ps(rps); + struct kv_power_info *pi = kv_get_pi(adev); + + pi->current_rps = *rps; + pi->current_ps = *new_ps; + pi->current_rps.ps_priv = &pi->current_ps; +} + +static void kv_update_requested_ps(struct amdgpu_device *adev, + struct amdgpu_ps *rps) +{ + struct kv_ps *new_ps = kv_get_ps(rps); + struct kv_power_info *pi = kv_get_pi(adev); + + pi->requested_rps = *rps; + pi->requested_ps = *new_ps; + pi->requested_rps.ps_priv = &pi->requested_ps; +} + +static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret; + + if (pi->bapm_enable) { + ret = amdgpu_kv_smc_bapm_enable(adev, enable); + if (ret) + DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); + } +} + +static int kv_dpm_enable(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret; + + ret = kv_process_firmware_header(adev); + if (ret) { + DRM_ERROR("kv_process_firmware_header failed\n"); + return ret; + } + kv_init_fps_limits(adev); + kv_init_graphics_levels(adev); + ret = kv_program_bootup_state(adev); + if (ret) { + DRM_ERROR("kv_program_bootup_state failed\n"); + return ret; + } + kv_calculate_dfs_bypass_settings(adev); + ret = kv_upload_dpm_settings(adev); + if (ret) { + DRM_ERROR("kv_upload_dpm_settings failed\n"); + return ret; + } + ret = kv_populate_uvd_table(adev); + if (ret) { + DRM_ERROR("kv_populate_uvd_table failed\n"); + return ret; + } + ret = kv_populate_vce_table(adev); + if (ret) { + DRM_ERROR("kv_populate_vce_table failed\n"); + return ret; + } + ret = kv_populate_samu_table(adev); + if (ret) { + DRM_ERROR("kv_populate_samu_table failed\n"); + return ret; + } + ret = kv_populate_acp_table(adev); + if (ret) { + DRM_ERROR("kv_populate_acp_table failed\n"); + return ret; + } + kv_program_vc(adev); +#if 0 + kv_initialize_hardware_cac_manager(adev); +#endif + kv_start_am(adev); + if (pi->enable_auto_thermal_throttling) { + ret = kv_enable_auto_thermal_throttling(adev); + if (ret) { + DRM_ERROR("kv_enable_auto_thermal_throttling failed\n"); + return ret; + } + } + ret = kv_enable_dpm_voltage_scaling(adev); + if (ret) { + DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n"); + return ret; + } + ret = kv_set_dpm_interval(adev); + if (ret) { + DRM_ERROR("kv_set_dpm_interval failed\n"); + return ret; + } + ret = kv_set_dpm_boot_state(adev); + if (ret) { + DRM_ERROR("kv_set_dpm_boot_state failed\n"); + return ret; + } + ret = kv_enable_ulv(adev, true); + if (ret) { + DRM_ERROR("kv_enable_ulv failed\n"); + return ret; + } + kv_start_dpm(adev); + ret = kv_enable_didt(adev, true); + if (ret) { + DRM_ERROR("kv_enable_didt failed\n"); + return ret; + } + ret = kv_enable_smc_cac(adev, true); + if (ret) { + DRM_ERROR("kv_enable_smc_cac failed\n"); + return ret; + } + + kv_reset_acp_boot_level(adev); + + ret = amdgpu_kv_smc_bapm_enable(adev, false); + if (ret) { + DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); + return ret; + } + + kv_update_current_ps(adev, adev->pm.dpm.boot_ps); + + if (adev->irq.installed && + amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) { + ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX); + if (ret) { + DRM_ERROR("kv_set_thermal_temperature_range failed\n"); + return ret; + } + amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, + AMDGPU_THERMAL_IRQ_LOW_TO_HIGH); + amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, + AMDGPU_THERMAL_IRQ_HIGH_TO_LOW); + } + + return ret; +} + +static void kv_dpm_disable(struct amdgpu_device *adev) +{ + amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, + AMDGPU_THERMAL_IRQ_LOW_TO_HIGH); + amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, + AMDGPU_THERMAL_IRQ_HIGH_TO_LOW); + + amdgpu_kv_smc_bapm_enable(adev, false); + + if (adev->asic_type == CHIP_MULLINS) + kv_enable_nb_dpm(adev, false); + + /* powerup blocks */ + kv_dpm_powergate_acp(adev, false); + kv_dpm_powergate_samu(adev, false); + kv_dpm_powergate_vce(adev, false); + kv_dpm_powergate_uvd(adev, false); + + kv_enable_smc_cac(adev, false); + kv_enable_didt(adev, false); + kv_clear_vc(adev); + kv_stop_dpm(adev); + kv_enable_ulv(adev, false); + kv_reset_am(adev); + + kv_update_current_ps(adev, adev->pm.dpm.boot_ps); +} + +#if 0 +static int kv_write_smc_soft_register(struct amdgpu_device *adev, + u16 reg_offset, u32 value) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset, + (u8 *)&value, sizeof(u16), pi->sram_end); +} + +static int kv_read_smc_soft_register(struct amdgpu_device *adev, + u16 reg_offset, u32 *value) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset, + value, pi->sram_end); +} +#endif + +static void kv_init_sclk_t(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + pi->low_sclk_interrupt_t = 0; +} + +static int kv_init_fps_limits(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret = 0; + + if (pi->caps_fps) { + u16 tmp; + + tmp = 45; + pi->fps_high_t = cpu_to_be16(tmp); + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, FpsHighT), + (u8 *)&pi->fps_high_t, + sizeof(u16), pi->sram_end); + + tmp = 30; + pi->fps_low_t = cpu_to_be16(tmp); + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, FpsLowT), + (u8 *)&pi->fps_low_t, + sizeof(u16), pi->sram_end); + + } + return ret; +} + +static void kv_init_powergate_state(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + pi->uvd_power_gated = false; + pi->vce_power_gated = false; + pi->samu_power_gated = false; + pi->acp_power_gated = false; + +} + +static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) +{ + return amdgpu_kv_notify_message_to_smu(adev, enable ? + PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable); +} + +static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable) +{ + return amdgpu_kv_notify_message_to_smu(adev, enable ? + PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable); +} + +static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable) +{ + return amdgpu_kv_notify_message_to_smu(adev, enable ? + PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable); +} + +static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable) +{ + return amdgpu_kv_notify_message_to_smu(adev, enable ? + PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable); +} + +static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_uvd_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; + int ret; + u32 mask; + + if (!gate) { + if (table->count) + pi->uvd_boot_level = table->count - 1; + else + pi->uvd_boot_level = 0; + + if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { + mask = 1 << pi->uvd_boot_level; + } else { + mask = 0x1f; + } + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), + (uint8_t *)&pi->uvd_boot_level, + sizeof(u8), pi->sram_end); + if (ret) + return ret; + + amdgpu_kv_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_UVDDPM_SetEnabledMask, + mask); + } + + return kv_enable_uvd_dpm(adev, !gate); +} + +static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk) +{ + u8 i; + struct amdgpu_vce_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + + for (i = 0; i < table->count; i++) { + if (table->entries[i].evclk >= evclk) + break; + } + + return i; +} + +static int kv_update_vce_dpm(struct amdgpu_device *adev, + struct amdgpu_ps *amdgpu_new_state, + struct amdgpu_ps *amdgpu_current_state) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_vce_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + int ret; + + if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) { + kv_dpm_powergate_vce(adev, false); + /* turn the clocks on when encoding */ + ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, + AMDGPU_CG_STATE_UNGATE); + if (ret) + return ret; + if (pi->caps_stable_p_state) + pi->vce_boot_level = table->count - 1; + else + pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, VceBootLevel), + (u8 *)&pi->vce_boot_level, + sizeof(u8), + pi->sram_end); + if (ret) + return ret; + + if (pi->caps_stable_p_state) + amdgpu_kv_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_VCEDPM_SetEnabledMask, + (1 << pi->vce_boot_level)); + + kv_enable_vce_dpm(adev, true); + } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) { + kv_enable_vce_dpm(adev, false); + /* turn the clocks off when not encoding */ + ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, + AMDGPU_CG_STATE_GATE); + if (ret) + return ret; + kv_dpm_powergate_vce(adev, true); + } + + return 0; +} + +static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; + int ret; + + if (!gate) { + if (pi->caps_stable_p_state) + pi->samu_boot_level = table->count - 1; + else + pi->samu_boot_level = 0; + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, SamuBootLevel), + (u8 *)&pi->samu_boot_level, + sizeof(u8), + pi->sram_end); + if (ret) + return ret; + + if (pi->caps_stable_p_state) + amdgpu_kv_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SAMUDPM_SetEnabledMask, + (1 << pi->samu_boot_level)); + } + + return kv_enable_samu_dpm(adev, !gate); +} + +static u8 kv_get_acp_boot_level(struct amdgpu_device *adev) +{ + u8 i; + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; + + for (i = 0; i < table->count; i++) { + if (table->entries[i].clk >= 0) /* XXX */ + break; + } + + if (i >= table->count) + i = table->count - 1; + + return i; +} + +static void kv_update_acp_boot_level(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u8 acp_boot_level; + + if (!pi->caps_stable_p_state) { + acp_boot_level = kv_get_acp_boot_level(adev); + if (acp_boot_level != pi->acp_boot_level) { + pi->acp_boot_level = acp_boot_level; + amdgpu_kv_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_ACPDPM_SetEnabledMask, + (1 << pi->acp_boot_level)); + } + } +} + +static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; + int ret; + + if (!gate) { + if (pi->caps_stable_p_state) + pi->acp_boot_level = table->count - 1; + else + pi->acp_boot_level = kv_get_acp_boot_level(adev); + + ret = amdgpu_kv_copy_bytes_to_smc(adev, + pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, AcpBootLevel), + (u8 *)&pi->acp_boot_level, + sizeof(u8), + pi->sram_end); + if (ret) + return ret; + + if (pi->caps_stable_p_state) + amdgpu_kv_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_ACPDPM_SetEnabledMask, + (1 << pi->acp_boot_level)); + } + + return kv_enable_acp_dpm(adev, !gate); +} + +static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret; + + if (pi->uvd_power_gated == gate) + return; + + pi->uvd_power_gated = gate; + + if (gate) { + if (pi->caps_uvd_pg) { + /* disable clockgating so we can properly shut down the block */ + ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, + AMDGPU_CG_STATE_UNGATE); + /* shutdown the UVD block */ + ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, + AMDGPU_PG_STATE_GATE); + /* XXX: check for errors */ + } + kv_update_uvd_dpm(adev, gate); + if (pi->caps_uvd_pg) + /* power off the UVD block */ + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF); + } else { + if (pi->caps_uvd_pg) { + /* power on the UVD block */ + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); + /* re-init the UVD block */ + ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, + AMDGPU_PG_STATE_UNGATE); + /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */ + ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, + AMDGPU_CG_STATE_GATE); + /* XXX: check for errors */ + } + kv_update_uvd_dpm(adev, gate); + } +} + +static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret; + + if (pi->vce_power_gated == gate) + return; + + pi->vce_power_gated = gate; + + if (gate) { + if (pi->caps_vce_pg) { + /* shutdown the VCE block */ + ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, + AMDGPU_PG_STATE_GATE); + /* XXX: check for errors */ + /* power off the VCE block */ + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF); + } + } else { + if (pi->caps_vce_pg) { + /* power on the VCE block */ + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); + /* re-init the VCE block */ + ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, + AMDGPU_PG_STATE_UNGATE); + /* XXX: check for errors */ + } + } +} + +static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + if (pi->samu_power_gated == gate) + return; + + pi->samu_power_gated = gate; + + if (gate) { + kv_update_samu_dpm(adev, true); + if (pi->caps_samu_pg) + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF); + } else { + if (pi->caps_samu_pg) + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON); + kv_update_samu_dpm(adev, false); + } +} + +static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + if (pi->acp_power_gated == gate) + return; + + if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) + return; + + pi->acp_power_gated = gate; + + if (gate) { + kv_update_acp_dpm(adev, true); + if (pi->caps_acp_pg) + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF); + } else { + if (pi->caps_acp_pg) + amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON); + kv_update_acp_dpm(adev, false); + } +} + +static void kv_set_valid_clock_range(struct amdgpu_device *adev, + struct amdgpu_ps *new_rps) +{ + struct kv_ps *new_ps = kv_get_ps(new_rps); + struct kv_power_info *pi = kv_get_pi(adev); + u32 i; + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + + if (table && table->count) { + for (i = 0; i < pi->graphics_dpm_level_count; i++) { + if ((table->entries[i].clk >= new_ps->levels[0].sclk) || + (i == (pi->graphics_dpm_level_count - 1))) { + pi->lowest_valid = i; + break; + } + } + + for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { + if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) + break; + } + pi->highest_valid = i; + + if (pi->lowest_valid > pi->highest_valid) { + if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > + (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) + pi->highest_valid = pi->lowest_valid; + else + pi->lowest_valid = pi->highest_valid; + } + } else { + struct sumo_sclk_voltage_mapping_table *table = + &pi->sys_info.sclk_voltage_mapping_table; + + for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { + if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || + i == (int)(pi->graphics_dpm_level_count - 1)) { + pi->lowest_valid = i; + break; + } + } + + for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { + if (table->entries[i].sclk_frequency <= + new_ps->levels[new_ps->num_levels - 1].sclk) + break; + } + pi->highest_valid = i; + + if (pi->lowest_valid > pi->highest_valid) { + if ((new_ps->levels[0].sclk - + table->entries[pi->highest_valid].sclk_frequency) > + (table->entries[pi->lowest_valid].sclk_frequency - + new_ps->levels[new_ps->num_levels -1].sclk)) + pi->highest_valid = pi->lowest_valid; + else + pi->lowest_valid = pi->highest_valid; + } + } +} + +static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev, + struct amdgpu_ps *new_rps) +{ + struct kv_ps *new_ps = kv_get_ps(new_rps); + struct kv_power_info *pi = kv_get_pi(adev); + int ret = 0; + u8 clk_bypass_cntl; + + if (pi->caps_enable_dfs_bypass) { + clk_bypass_cntl = new_ps->need_dfs_bypass ? + pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; + ret = amdgpu_kv_copy_bytes_to_smc(adev, + (pi->dpm_table_start + + offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) + + (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + + offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)), + &clk_bypass_cntl, + sizeof(u8), pi->sram_end); + } + + return ret; +} + +static int kv_enable_nb_dpm(struct amdgpu_device *adev, + bool enable) +{ + struct kv_power_info *pi = kv_get_pi(adev); + int ret = 0; + + if (enable) { + if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { + ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable); + if (ret == 0) + pi->nb_dpm_enabled = true; + } + } else { + if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { + ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable); + if (ret == 0) + pi->nb_dpm_enabled = false; + } + } + + return ret; +} + +static int kv_dpm_force_performance_level(struct amdgpu_device *adev, + enum amdgpu_dpm_forced_level level) +{ + int ret; + + if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) { + ret = kv_force_dpm_highest(adev); + if (ret) + return ret; + } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) { + ret = kv_force_dpm_lowest(adev); + if (ret) + return ret; + } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) { + ret = kv_unforce_levels(adev); + if (ret) + return ret; + } + + adev->pm.dpm.forced_level = level; + + return 0; +} + +static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; + struct amdgpu_ps *new_ps = &requested_ps; + + kv_update_requested_ps(adev, new_ps); + + kv_apply_state_adjust_rules(adev, + &pi->requested_rps, + &pi->current_rps); + + return 0; +} + +static int kv_dpm_set_power_state(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_ps *new_ps = &pi->requested_rps; + struct amdgpu_ps *old_ps = &pi->current_rps; + int ret; + + if (pi->bapm_enable) { + ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.dpm.ac_power); + if (ret) { + DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); + return ret; + } + } + + if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { + if (pi->enable_dpm) { + kv_set_valid_clock_range(adev, new_ps); + kv_update_dfs_bypass_settings(adev, new_ps); + ret = kv_calculate_ds_divider(adev); + if (ret) { + DRM_ERROR("kv_calculate_ds_divider failed\n"); + return ret; + } + kv_calculate_nbps_level_settings(adev); + kv_calculate_dpm_settings(adev); + kv_force_lowest_valid(adev); + kv_enable_new_levels(adev); + kv_upload_dpm_settings(adev); + kv_program_nbps_index_settings(adev, new_ps); + kv_unforce_levels(adev); + kv_set_enabled_levels(adev); + kv_force_lowest_valid(adev); + kv_unforce_levels(adev); + + ret = kv_update_vce_dpm(adev, new_ps, old_ps); + if (ret) { + DRM_ERROR("kv_update_vce_dpm failed\n"); + return ret; + } + kv_update_sclk_t(adev); + if (adev->asic_type == CHIP_MULLINS) + kv_enable_nb_dpm(adev, true); + } + } else { + if (pi->enable_dpm) { + kv_set_valid_clock_range(adev, new_ps); + kv_update_dfs_bypass_settings(adev, new_ps); + ret = kv_calculate_ds_divider(adev); + if (ret) { + DRM_ERROR("kv_calculate_ds_divider failed\n"); + return ret; + } + kv_calculate_nbps_level_settings(adev); + kv_calculate_dpm_settings(adev); + kv_freeze_sclk_dpm(adev, true); + kv_upload_dpm_settings(adev); + kv_program_nbps_index_settings(adev, new_ps); + kv_freeze_sclk_dpm(adev, false); + kv_set_enabled_levels(adev); + ret = kv_update_vce_dpm(adev, new_ps, old_ps); + if (ret) { + DRM_ERROR("kv_update_vce_dpm failed\n"); + return ret; + } + kv_update_acp_boot_level(adev); + kv_update_sclk_t(adev); + kv_enable_nb_dpm(adev, true); + } + } + + return 0; +} + +static void kv_dpm_post_set_power_state(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_ps *new_ps = &pi->requested_rps; + + kv_update_current_ps(adev, new_ps); +} + +static void kv_dpm_setup_asic(struct amdgpu_device *adev) +{ + sumo_take_smu_control(adev, true); + kv_init_powergate_state(adev); + kv_init_sclk_t(adev); +} + +#if 0 +static void kv_dpm_reset_asic(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { + kv_force_lowest_valid(adev); + kv_init_graphics_levels(adev); + kv_program_bootup_state(adev); + kv_upload_dpm_settings(adev); + kv_force_lowest_valid(adev); + kv_unforce_levels(adev); + } else { + kv_init_graphics_levels(adev); + kv_program_bootup_state(adev); + kv_freeze_sclk_dpm(adev, true); + kv_upload_dpm_settings(adev); + kv_freeze_sclk_dpm(adev, false); + kv_set_enabled_level(adev, pi->graphics_boot_level); + } +} +#endif + +static void kv_construct_max_power_limits_table(struct amdgpu_device *adev, + struct amdgpu_clock_and_voltage_limits *table) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { + int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; + table->sclk = + pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; + table->vddc = + kv_convert_2bit_index_to_voltage(adev, + pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); + } + + table->mclk = pi->sys_info.nbp_memory_clock[0]; +} + +static void kv_patch_voltage_values(struct amdgpu_device *adev) +{ + int i; + struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table = + &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; + struct amdgpu_vce_clock_voltage_dependency_table *vce_table = + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + struct amdgpu_clock_voltage_dependency_table *samu_table = + &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; + struct amdgpu_clock_voltage_dependency_table *acp_table = + &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; + + if (uvd_table->count) { + for (i = 0; i < uvd_table->count; i++) + uvd_table->entries[i].v = + kv_convert_8bit_index_to_voltage(adev, + uvd_table->entries[i].v); + } + + if (vce_table->count) { + for (i = 0; i < vce_table->count; i++) + vce_table->entries[i].v = + kv_convert_8bit_index_to_voltage(adev, + vce_table->entries[i].v); + } + + if (samu_table->count) { + for (i = 0; i < samu_table->count; i++) + samu_table->entries[i].v = + kv_convert_8bit_index_to_voltage(adev, + samu_table->entries[i].v); + } + + if (acp_table->count) { + for (i = 0; i < acp_table->count; i++) + acp_table->entries[i].v = + kv_convert_8bit_index_to_voltage(adev, + acp_table->entries[i].v); + } + +} + +static void kv_construct_boot_state(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + pi->boot_pl.sclk = pi->sys_info.bootup_sclk; + pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; + pi->boot_pl.ds_divider_index = 0; + pi->boot_pl.ss_divider_index = 0; + pi->boot_pl.allow_gnb_slow = 1; + pi->boot_pl.force_nbp_state = 0; + pi->boot_pl.display_wm = 0; + pi->boot_pl.vce_wm = 0; +} + +static int kv_force_dpm_highest(struct amdgpu_device *adev) +{ + int ret; + u32 enable_mask, i; + + ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); + if (ret) + return ret; + + for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) { + if (enable_mask & (1 << i)) + break; + } + + if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) + return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); + else + return kv_set_enabled_level(adev, i); +} + +static int kv_force_dpm_lowest(struct amdgpu_device *adev) +{ + int ret; + u32 enable_mask, i; + + ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); + if (ret) + return ret; + + for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { + if (enable_mask & (1 << i)) + break; + } + + if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) + return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); + else + return kv_set_enabled_level(adev, i); +} + +static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, + u32 sclk, u32 min_sclk_in_sr) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 i; + u32 temp; + u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ? + min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK; + + if (sclk < min) + return 0; + + if (!pi->caps_sclk_ds) + return 0; + + for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) { + temp = sclk / sumo_get_sleep_divider_from_id(i); + if (temp >= min) + break; + } + + return (u8)i; +} + +static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + int i; + + if (table && table->count) { + for (i = table->count - 1; i >= 0; i--) { + if (pi->high_voltage_t && + (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <= + pi->high_voltage_t)) { + *limit = i; + return 0; + } + } + } else { + struct sumo_sclk_voltage_mapping_table *table = + &pi->sys_info.sclk_voltage_mapping_table; + + for (i = table->num_max_dpm_entries - 1; i >= 0; i--) { + if (pi->high_voltage_t && + (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <= + pi->high_voltage_t)) { + *limit = i; + return 0; + } + } + } + + *limit = 0; + return 0; +} + +static void kv_apply_state_adjust_rules(struct amdgpu_device *adev, + struct amdgpu_ps *new_rps, + struct amdgpu_ps *old_rps) +{ + struct kv_ps *ps = kv_get_ps(new_rps); + struct kv_power_info *pi = kv_get_pi(adev); + u32 min_sclk = 10000; /* ??? */ + u32 sclk, mclk = 0; + int i, limit; + bool force_high; + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + u32 stable_p_state_sclk = 0; + struct amdgpu_clock_and_voltage_limits *max_limits = + &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; + + if (new_rps->vce_active) { + new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; + new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; + } else { + new_rps->evclk = 0; + new_rps->ecclk = 0; + } + + mclk = max_limits->mclk; + sclk = min_sclk; + + if (pi->caps_stable_p_state) { + stable_p_state_sclk = (max_limits->sclk * 75) / 100; + + for (i = table->count - 1; i >= 0; i++) { + if (stable_p_state_sclk >= table->entries[i].clk) { + stable_p_state_sclk = table->entries[i].clk; + break; + } + } + + if (i > 0) + stable_p_state_sclk = table->entries[0].clk; + + sclk = stable_p_state_sclk; + } + + if (new_rps->vce_active) { + if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) + sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; + } + + ps->need_dfs_bypass = true; + + for (i = 0; i < ps->num_levels; i++) { + if (ps->levels[i].sclk < sclk) + ps->levels[i].sclk = sclk; + } + + if (table && table->count) { + for (i = 0; i < ps->num_levels; i++) { + if (pi->high_voltage_t && + (pi->high_voltage_t < + kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { + kv_get_high_voltage_limit(adev, &limit); + ps->levels[i].sclk = table->entries[limit].clk; + } + } + } else { + struct sumo_sclk_voltage_mapping_table *table = + &pi->sys_info.sclk_voltage_mapping_table; + + for (i = 0; i < ps->num_levels; i++) { + if (pi->high_voltage_t && + (pi->high_voltage_t < + kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { + kv_get_high_voltage_limit(adev, &limit); + ps->levels[i].sclk = table->entries[limit].sclk_frequency; + } + } + } + + if (pi->caps_stable_p_state) { + for (i = 0; i < ps->num_levels; i++) { + ps->levels[i].sclk = stable_p_state_sclk; + } + } + + pi->video_start = new_rps->dclk || new_rps->vclk || + new_rps->evclk || new_rps->ecclk; + + if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == + ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) + pi->battery_state = true; + else + pi->battery_state = false; + + if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { + ps->dpm0_pg_nb_ps_lo = 0x1; + ps->dpm0_pg_nb_ps_hi = 0x0; + ps->dpmx_nb_ps_lo = 0x1; + ps->dpmx_nb_ps_hi = 0x0; + } else { + ps->dpm0_pg_nb_ps_lo = 0x3; + ps->dpm0_pg_nb_ps_hi = 0x0; + ps->dpmx_nb_ps_lo = 0x3; + ps->dpmx_nb_ps_hi = 0x0; + + if (pi->sys_info.nb_dpm_enable) { + force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || + pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || + pi->disable_nb_ps3_in_battery; + ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3; + ps->dpm0_pg_nb_ps_hi = 0x2; + ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3; + ps->dpmx_nb_ps_hi = 0x2; + } + } +} + +static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev, + u32 index, bool enable) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; +} + +static int kv_calculate_ds_divider(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 sclk_in_sr = 10000; /* ??? */ + u32 i; + + if (pi->lowest_valid > pi->highest_valid) + return -EINVAL; + + for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { + pi->graphics_level[i].DeepSleepDivId = + kv_get_sleep_divider_id_from_clock(adev, + be32_to_cpu(pi->graphics_level[i].SclkFrequency), + sclk_in_sr); + } + return 0; +} + +static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 i; + bool force_high; + struct amdgpu_clock_and_voltage_limits *max_limits = + &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; + u32 mclk = max_limits->mclk; + + if (pi->lowest_valid > pi->highest_valid) + return -EINVAL; + + if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { + for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { + pi->graphics_level[i].GnbSlow = 1; + pi->graphics_level[i].ForceNbPs1 = 0; + pi->graphics_level[i].UpH = 0; + } + + if (!pi->sys_info.nb_dpm_enable) + return 0; + + force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || + (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); + + if (force_high) { + for (i = pi->lowest_valid; i <= pi->highest_valid; i++) + pi->graphics_level[i].GnbSlow = 0; + } else { + if (pi->battery_state) + pi->graphics_level[0].ForceNbPs1 = 1; + + pi->graphics_level[1].GnbSlow = 0; + pi->graphics_level[2].GnbSlow = 0; + pi->graphics_level[3].GnbSlow = 0; + pi->graphics_level[4].GnbSlow = 0; + } + } else { + for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { + pi->graphics_level[i].GnbSlow = 1; + pi->graphics_level[i].ForceNbPs1 = 0; + pi->graphics_level[i].UpH = 0; + } + + if (pi->sys_info.nb_dpm_enable && pi->battery_state) { + pi->graphics_level[pi->lowest_valid].UpH = 0x28; + pi->graphics_level[pi->lowest_valid].GnbSlow = 0; + if (pi->lowest_valid != pi->highest_valid) + pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; + } + } + return 0; +} + +static int kv_calculate_dpm_settings(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 i; + + if (pi->lowest_valid > pi->highest_valid) + return -EINVAL; + + for (i = pi->lowest_valid; i <= pi->highest_valid; i++) + pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; + + return 0; +} + +static void kv_init_graphics_levels(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 i; + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + + if (table && table->count) { + u32 vid_2bit; + + pi->graphics_dpm_level_count = 0; + for (i = 0; i < table->count; i++) { + if (pi->high_voltage_t && + (pi->high_voltage_t < + kv_convert_8bit_index_to_voltage(adev, table->entries[i].v))) + break; + + kv_set_divider_value(adev, i, table->entries[i].clk); + vid_2bit = kv_convert_vid7_to_vid2(adev, + &pi->sys_info.vid_mapping_table, + table->entries[i].v); + kv_set_vid(adev, i, vid_2bit); + kv_set_at(adev, i, pi->at[i]); + kv_dpm_power_level_enabled_for_throttle(adev, i, true); + pi->graphics_dpm_level_count++; + } + } else { + struct sumo_sclk_voltage_mapping_table *table = + &pi->sys_info.sclk_voltage_mapping_table; + + pi->graphics_dpm_level_count = 0; + for (i = 0; i < table->num_max_dpm_entries; i++) { + if (pi->high_voltage_t && + pi->high_voltage_t < + kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit)) + break; + + kv_set_divider_value(adev, i, table->entries[i].sclk_frequency); + kv_set_vid(adev, i, table->entries[i].vid_2bit); + kv_set_at(adev, i, pi->at[i]); + kv_dpm_power_level_enabled_for_throttle(adev, i, true); + pi->graphics_dpm_level_count++; + } + } + + for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) + kv_dpm_power_level_enable(adev, i, false); +} + +static void kv_enable_new_levels(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 i; + + for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { + if (i >= pi->lowest_valid && i <= pi->highest_valid) + kv_dpm_power_level_enable(adev, i, true); + } +} + +static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level) +{ + u32 new_mask = (1 << level); + + return amdgpu_kv_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + new_mask); +} + +static int kv_set_enabled_levels(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 i, new_mask = 0; + + for (i = pi->lowest_valid; i <= pi->highest_valid; i++) + new_mask |= (1 << i); + + return amdgpu_kv_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + new_mask); +} + +static void kv_program_nbps_index_settings(struct amdgpu_device *adev, + struct amdgpu_ps *new_rps) +{ + struct kv_ps *new_ps = kv_get_ps(new_rps); + struct kv_power_info *pi = kv_get_pi(adev); + u32 nbdpmconfig1; + + if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) + return; + + if (pi->sys_info.nb_dpm_enable) { + nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1); + nbdpmconfig1 &= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK | + NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK | + NB_DPM_CONFIG_1__DpmXNbPsLo_MASK | + NB_DPM_CONFIG_1__DpmXNbPsHi_MASK); + nbdpmconfig1 |= (new_ps->dpm0_pg_nb_ps_lo << NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT) | + (new_ps->dpm0_pg_nb_ps_hi << NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT) | + (new_ps->dpmx_nb_ps_lo << NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT) | + (new_ps->dpmx_nb_ps_hi << NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT); + WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1); + } +} + +static int kv_set_thermal_temperature_range(struct amdgpu_device *adev, + int min_temp, int max_temp) +{ + int low_temp = 0 * 1000; + int high_temp = 255 * 1000; + u32 tmp; + + if (low_temp < min_temp) + low_temp = min_temp; + if (high_temp > max_temp) + high_temp = max_temp; + if (high_temp < low_temp) { + DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); + return -EINVAL; + } + + tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL); + tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK | + CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK); + tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) | + ((49 + (low_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT); + WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp); + + adev->pm.dpm.thermal.min_temp = low_temp; + adev->pm.dpm.thermal.max_temp = high_temp; + + return 0; +} + +union igp_info { + struct _ATOM_INTEGRATED_SYSTEM_INFO info; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; +}; + +static int kv_parse_sys_info_table(struct amdgpu_device *adev) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); + union igp_info *igp_info; + u8 frev, crev; + u16 data_offset; + int i; + + if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) { + igp_info = (union igp_info *)(mode_info->atom_context->bios + + data_offset); + + if (crev != 8) { + DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); + return -EINVAL; + } + pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); + pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); + pi->sys_info.bootup_nb_voltage_index = + le16_to_cpu(igp_info->info_8.usBootUpNBVoltage); + if (igp_info->info_8.ucHtcTmpLmt == 0) + pi->sys_info.htc_tmp_lmt = 203; + else + pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; + if (igp_info->info_8.ucHtcHystLmt == 0) + pi->sys_info.htc_hyst_lmt = 5; + else + pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; + if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { + DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); + } + + if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3)) + pi->sys_info.nb_dpm_enable = true; + else + pi->sys_info.nb_dpm_enable = false; + + for (i = 0; i < KV_NUM_NBPSTATES; i++) { + pi->sys_info.nbp_memory_clock[i] = + le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]); + pi->sys_info.nbp_n_clock[i] = + le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]); + } + if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) & + SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) + pi->caps_enable_dfs_bypass = true; + + sumo_construct_sclk_voltage_mapping_table(adev, + &pi->sys_info.sclk_voltage_mapping_table, + igp_info->info_8.sAvail_SCLK); + + sumo_construct_vid_mapping_table(adev, + &pi->sys_info.vid_mapping_table, + igp_info->info_8.sAvail_SCLK); + + kv_construct_max_power_limits_table(adev, + &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); + } + return 0; +} + +union power_info { + struct _ATOM_POWERPLAY_INFO info; + struct _ATOM_POWERPLAY_INFO_V2 info_2; + struct _ATOM_POWERPLAY_INFO_V3 info_3; + struct _ATOM_PPLIB_POWERPLAYTABLE pplib; + struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; + struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; +}; + +union pplib_clock_info { + struct _ATOM_PPLIB_R600_CLOCK_INFO r600; + struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; + struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; + struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; +}; + +union pplib_power_state { + struct _ATOM_PPLIB_STATE v1; + struct _ATOM_PPLIB_STATE_V2 v2; +}; + +static void kv_patch_boot_state(struct amdgpu_device *adev, + struct kv_ps *ps) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + ps->num_levels = 1; + ps->levels[0] = pi->boot_pl; +} + +static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev, + struct amdgpu_ps *rps, + struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, + u8 table_rev) +{ + struct kv_ps *ps = kv_get_ps(rps); + + rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); + rps->class = le16_to_cpu(non_clock_info->usClassification); + rps->class2 = le16_to_cpu(non_clock_info->usClassification2); + + if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { + rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); + rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); + } else { + rps->vclk = 0; + rps->dclk = 0; + } + + if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { + adev->pm.dpm.boot_ps = rps; + kv_patch_boot_state(adev, ps); + } + if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) + adev->pm.dpm.uvd_ps = rps; +} + +static void kv_parse_pplib_clock_info(struct amdgpu_device *adev, + struct amdgpu_ps *rps, int index, + union pplib_clock_info *clock_info) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct kv_ps *ps = kv_get_ps(rps); + struct kv_pl *pl = &ps->levels[index]; + u32 sclk; + + sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); + sclk |= clock_info->sumo.ucEngineClockHigh << 16; + pl->sclk = sclk; + pl->vddc_index = clock_info->sumo.vddcIndex; + + ps->num_levels = index + 1; + + if (pi->caps_sclk_ds) { + pl->ds_divider_index = 5; + pl->ss_divider_index = 5; + } +} + +static int kv_parse_power_table(struct amdgpu_device *adev) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; + union pplib_power_state *power_state; + int i, j, k, non_clock_array_index, clock_array_index; + union pplib_clock_info *clock_info; + struct _StateArray *state_array; + struct _ClockInfoArray *clock_info_array; + struct _NonClockInfoArray *non_clock_info_array; + union power_info *power_info; + int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); + u16 data_offset; + u8 frev, crev; + u8 *power_state_offset; + struct kv_ps *ps; + + if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) + return -EINVAL; + power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); + + amdgpu_add_thermal_controller(adev); + + state_array = (struct _StateArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usStateArrayOffset)); + clock_info_array = (struct _ClockInfoArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); + non_clock_info_array = (struct _NonClockInfoArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); + + adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) * + state_array->ucNumEntries, GFP_KERNEL); + if (!adev->pm.dpm.ps) + return -ENOMEM; + power_state_offset = (u8 *)state_array->states; + for (i = 0; i < state_array->ucNumEntries; i++) { + u8 *idx; + power_state = (union pplib_power_state *)power_state_offset; + non_clock_array_index = power_state->v2.nonClockInfoIndex; + non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) + &non_clock_info_array->nonClockInfo[non_clock_array_index]; + ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL); + if (ps == NULL) { + kfree(adev->pm.dpm.ps); + return -ENOMEM; + } + adev->pm.dpm.ps[i].ps_priv = ps; + k = 0; + idx = (u8 *)&power_state->v2.clockInfoIndex[0]; + for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { + clock_array_index = idx[j]; + if (clock_array_index >= clock_info_array->ucNumEntries) + continue; + if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) + break; + clock_info = (union pplib_clock_info *) + ((u8 *)&clock_info_array->clockInfo[0] + + (clock_array_index * clock_info_array->ucEntrySize)); + kv_parse_pplib_clock_info(adev, + &adev->pm.dpm.ps[i], k, + clock_info); + k++; + } + kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], + non_clock_info, + non_clock_info_array->ucEntrySize); + power_state_offset += 2 + power_state->v2.ucNumDPMLevels; + } + adev->pm.dpm.num_ps = state_array->ucNumEntries; + + /* fill in the vce power states */ + for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) { + u32 sclk; + clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; + clock_info = (union pplib_clock_info *) + &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; + sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); + sclk |= clock_info->sumo.ucEngineClockHigh << 16; + adev->pm.dpm.vce_states[i].sclk = sclk; + adev->pm.dpm.vce_states[i].mclk = 0; + } + + return 0; +} + +static int kv_dpm_init(struct amdgpu_device *adev) +{ + struct kv_power_info *pi; + int ret, i; + + pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); + if (pi == NULL) + return -ENOMEM; + adev->pm.dpm.priv = pi; + + ret = amdgpu_get_platform_caps(adev); + if (ret) + return ret; + + ret = amdgpu_parse_extended_power_table(adev); + if (ret) + return ret; + + for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) + pi->at[i] = TRINITY_AT_DFLT; + + pi->sram_end = SMC_RAM_END; + + pi->enable_nb_dpm = true; + + pi->caps_power_containment = true; + pi->caps_cac = true; + pi->enable_didt = false; + if (pi->enable_didt) { + pi->caps_sq_ramping = true; + pi->caps_db_ramping = true; + pi->caps_td_ramping = true; + pi->caps_tcp_ramping = true; + } + + pi->caps_sclk_ds = true; + pi->enable_auto_thermal_throttling = true; + pi->disable_nb_ps3_in_battery = false; + if (amdgpu_bapm == 0) + pi->bapm_enable = false; + else + pi->bapm_enable = true; + pi->voltage_drop_t = 0; + pi->caps_sclk_throttle_low_notification = false; + pi->caps_fps = false; /* true? */ + pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false; + pi->caps_uvd_dpm = true; + pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false; + pi->caps_samu_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_SAMU) ? true : false; + pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false; + pi->caps_stable_p_state = false; + + ret = kv_parse_sys_info_table(adev); + if (ret) + return ret; + + kv_patch_voltage_values(adev); + kv_construct_boot_state(adev); + + ret = kv_parse_power_table(adev); + if (ret) + return ret; + + pi->enable_dpm = true; + + return 0; +} + +static void +kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, + struct seq_file *m) +{ + struct kv_power_info *pi = kv_get_pi(adev); + u32 current_index = + (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >> + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT; + u32 sclk, tmp; + u16 vddc; + + if (current_index >= SMU__NUM_SCLK_DPM_STATE) { + seq_printf(m, "invalid dpm profile %d\n", current_index); + } else { + sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); + tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) & + SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> + SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT; + vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp); + seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); + seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); + seq_printf(m, "power level %d sclk: %u vddc: %u\n", + current_index, sclk, vddc); + } +} + +static void +kv_dpm_print_power_state(struct amdgpu_device *adev, + struct amdgpu_ps *rps) +{ + int i; + struct kv_ps *ps = kv_get_ps(rps); + + amdgpu_dpm_print_class_info(rps->class, rps->class2); + amdgpu_dpm_print_cap_info(rps->caps); + printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); + for (i = 0; i < ps->num_levels; i++) { + struct kv_pl *pl = &ps->levels[i]; + printk("\t\tpower level %d sclk: %u vddc: %u\n", + i, pl->sclk, + kv_convert_8bit_index_to_voltage(adev, pl->vddc_index)); + } + amdgpu_dpm_print_ps_status(adev, rps); +} + +static void kv_dpm_fini(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->pm.dpm.num_ps; i++) { + kfree(adev->pm.dpm.ps[i].ps_priv); + } + kfree(adev->pm.dpm.ps); + kfree(adev->pm.dpm.priv); + amdgpu_free_extended_power_table(adev); +} + +static void kv_dpm_display_configuration_changed(struct amdgpu_device *adev) +{ + +} + +static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low) +{ + struct kv_power_info *pi = kv_get_pi(adev); + struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); + + if (low) + return requested_state->levels[0].sclk; + else + return requested_state->levels[requested_state->num_levels - 1].sclk; +} + +static u32 kv_dpm_get_mclk(struct amdgpu_device *adev, bool low) +{ + struct kv_power_info *pi = kv_get_pi(adev); + + return pi->sys_info.bootup_uma_clk; +} + +/* get temperature in millidegrees */ +static int kv_dpm_get_temp(struct amdgpu_device *adev) +{ + u32 temp; + int actual_temp = 0; + + temp = RREG32_SMC(0xC0300E0C); + + if (temp) + actual_temp = (temp / 8) - 49; + else + actual_temp = 0; + + actual_temp = actual_temp * 1000; + + return actual_temp; +} + +static int kv_dpm_early_init(struct amdgpu_device *adev) +{ + kv_dpm_set_dpm_funcs(adev); + kv_dpm_set_irq_funcs(adev); + + return 0; +} + +static int kv_dpm_late_init(struct amdgpu_device *adev) +{ + if (!amdgpu_dpm) + return 0; + + /* powerdown unused blocks for now */ + kv_dpm_powergate_acp(adev, true); + kv_dpm_powergate_samu(adev, true); + kv_dpm_powergate_vce(adev, true); + kv_dpm_powergate_uvd(adev, true); + + return 0; +} + +static int kv_dpm_sw_init(struct amdgpu_device *adev) +{ + int ret; + + ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); + if (ret) + return ret; + + ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq); + if (ret) + return ret; + + /* default to balanced state */ + adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; + adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; + adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO; + adev->pm.default_sclk = adev->clock.default_sclk; + adev->pm.default_mclk = adev->clock.default_mclk; + adev->pm.current_sclk = adev->clock.default_sclk; + adev->pm.current_mclk = adev->clock.default_mclk; + adev->pm.int_thermal_type = THERMAL_TYPE_NONE; + + if (amdgpu_dpm == 0) + return 0; + + INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); + mutex_lock(&adev->pm.mutex); + ret = kv_dpm_init(adev); + if (ret) + goto dpm_failed; + adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; + if (amdgpu_dpm == 1) + amdgpu_pm_print_power_states(adev); + ret = amdgpu_pm_sysfs_init(adev); + if (ret) + goto dpm_failed; + mutex_unlock(&adev->pm.mutex); + DRM_INFO("amdgpu: dpm initialized\n"); + + return 0; + +dpm_failed: + kv_dpm_fini(adev); + mutex_unlock(&adev->pm.mutex); + DRM_ERROR("amdgpu: dpm initialization failed\n"); + return ret; +} + +static int kv_dpm_sw_fini(struct amdgpu_device *adev) +{ + mutex_lock(&adev->pm.mutex); + amdgpu_pm_sysfs_fini(adev); + kv_dpm_fini(adev); + mutex_unlock(&adev->pm.mutex); + + return 0; +} + +static int kv_dpm_hw_init(struct amdgpu_device *adev) +{ + int ret; + + if (!amdgpu_dpm) + return 0; + + mutex_lock(&adev->pm.mutex); + kv_dpm_setup_asic(adev); + ret = kv_dpm_enable(adev); + if (ret) + adev->pm.dpm_enabled = false; + else + adev->pm.dpm_enabled = true; + mutex_unlock(&adev->pm.mutex); + + return ret; +} + +static int kv_dpm_hw_fini(struct amdgpu_device *adev) +{ + if (adev->pm.dpm_enabled) { + mutex_lock(&adev->pm.mutex); + kv_dpm_disable(adev); + mutex_unlock(&adev->pm.mutex); + } + + return 0; +} + +static int kv_dpm_suspend(struct amdgpu_device *adev) +{ + if (adev->pm.dpm_enabled) { + mutex_lock(&adev->pm.mutex); + /* disable dpm */ + kv_dpm_disable(adev); + /* reset the power state */ + adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; + mutex_unlock(&adev->pm.mutex); + } + return 0; +} + +static int kv_dpm_resume(struct amdgpu_device *adev) +{ + int ret; + + if (adev->pm.dpm_enabled) { + /* asic init will reset to the boot state */ + mutex_lock(&adev->pm.mutex); + kv_dpm_setup_asic(adev); + ret = kv_dpm_enable(adev); + if (ret) + adev->pm.dpm_enabled = false; + else + adev->pm.dpm_enabled = true; + mutex_unlock(&adev->pm.mutex); + if (adev->pm.dpm_enabled) + amdgpu_pm_compute_clocks(adev); + } + return 0; +} + +static bool kv_dpm_is_idle(struct amdgpu_device *adev) +{ + /* XXX */ + return true; +} + +static int kv_dpm_wait_for_idle(struct amdgpu_device *adev) +{ + /* XXX */ + return 0; +} + +static void kv_dpm_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "KV/KB DPM registers\n"); + dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n", + RREG32_DIDT(ixDIDT_SQ_CTRL0)); + dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n", + RREG32_DIDT(ixDIDT_DB_CTRL0)); + dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n", + RREG32_DIDT(ixDIDT_TD_CTRL0)); + dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n", + RREG32_DIDT(ixDIDT_TCP_CTRL0)); + dev_info(adev->dev, " LCAC_SX0_OVR_SEL=0x%08X\n", + RREG32_SMC(ixLCAC_SX0_OVR_SEL)); + dev_info(adev->dev, " LCAC_SX0_OVR_VAL=0x%08X\n", + RREG32_SMC(ixLCAC_SX0_OVR_VAL)); + dev_info(adev->dev, " LCAC_MC0_OVR_SEL=0x%08X\n", + RREG32_SMC(ixLCAC_MC0_OVR_SEL)); + dev_info(adev->dev, " LCAC_MC0_OVR_VAL=0x%08X\n", + RREG32_SMC(ixLCAC_MC0_OVR_VAL)); + dev_info(adev->dev, " LCAC_MC1_OVR_SEL=0x%08X\n", + RREG32_SMC(ixLCAC_MC1_OVR_SEL)); + dev_info(adev->dev, " LCAC_MC1_OVR_VAL=0x%08X\n", + RREG32_SMC(ixLCAC_MC1_OVR_VAL)); + dev_info(adev->dev, " LCAC_MC2_OVR_SEL=0x%08X\n", + RREG32_SMC(ixLCAC_MC2_OVR_SEL)); + dev_info(adev->dev, " LCAC_MC2_OVR_VAL=0x%08X\n", + RREG32_SMC(ixLCAC_MC2_OVR_VAL)); + dev_info(adev->dev, " LCAC_MC3_OVR_SEL=0x%08X\n", + RREG32_SMC(ixLCAC_MC3_OVR_SEL)); + dev_info(adev->dev, " LCAC_MC3_OVR_VAL=0x%08X\n", + RREG32_SMC(ixLCAC_MC3_OVR_VAL)); + dev_info(adev->dev, " LCAC_CPL_OVR_SEL=0x%08X\n", + RREG32_SMC(ixLCAC_CPL_OVR_SEL)); + dev_info(adev->dev, " LCAC_CPL_OVR_VAL=0x%08X\n", + RREG32_SMC(ixLCAC_CPL_OVR_VAL)); + dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n", + RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0)); + dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n", + RREG32_SMC(ixGENERAL_PWRMGT)); + dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n", + RREG32_SMC(ixSCLK_PWRMGT_CNTL)); + dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n", + RREG32(mmSMC_MESSAGE_0)); + dev_info(adev->dev, " SMC_RESP_0=0x%08X\n", + RREG32(mmSMC_RESP_0)); + dev_info(adev->dev, " SMC_MSG_ARG_0=0x%08X\n", + RREG32(mmSMC_MSG_ARG_0)); + dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n", + RREG32(mmSMC_IND_INDEX_0)); + dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n", + RREG32(mmSMC_IND_DATA_0)); + dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n", + RREG32(mmSMC_IND_ACCESS_CNTL)); +} + +static int kv_dpm_soft_reset(struct amdgpu_device *adev) +{ + return 0; +} + +static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 cg_thermal_int; + + switch (type) { + case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH: + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); + cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; + WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); + cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; + WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); + break; + default: + break; + } + break; + + case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW: + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); + cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; + WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); + cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; + WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); + break; + default: + break; + } + break; + + default: + break; + } + return 0; +} + +static int kv_dpm_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + bool queue_thermal = false; + + if (entry == NULL) + return -EINVAL; + + switch (entry->src_id) { + case 230: /* thermal low to high */ + DRM_DEBUG("IH: thermal low to high\n"); + adev->pm.dpm.thermal.high_to_low = false; + queue_thermal = true; + break; + case 231: /* thermal high to low */ + DRM_DEBUG("IH: thermal high to low\n"); + adev->pm.dpm.thermal.high_to_low = true; + queue_thermal = true; + break; + default: + break; + } + + if (queue_thermal) + schedule_work(&adev->pm.dpm.thermal.work); + + return 0; +} + +static int kv_dpm_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static int kv_dpm_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs kv_dpm_ip_funcs = { + .early_init = kv_dpm_early_init, + .late_init = kv_dpm_late_init, + .sw_init = kv_dpm_sw_init, + .sw_fini = kv_dpm_sw_fini, + .hw_init = kv_dpm_hw_init, + .hw_fini = kv_dpm_hw_fini, + .suspend = kv_dpm_suspend, + .resume = kv_dpm_resume, + .is_idle = kv_dpm_is_idle, + .wait_for_idle = kv_dpm_wait_for_idle, + .soft_reset = kv_dpm_soft_reset, + .print_status = kv_dpm_print_status, + .set_clockgating_state = kv_dpm_set_clockgating_state, + .set_powergating_state = kv_dpm_set_powergating_state, +}; + +static const struct amdgpu_dpm_funcs kv_dpm_funcs = { + .get_temperature = &kv_dpm_get_temp, + .pre_set_power_state = &kv_dpm_pre_set_power_state, + .set_power_state = &kv_dpm_set_power_state, + .post_set_power_state = &kv_dpm_post_set_power_state, + .display_configuration_changed = &kv_dpm_display_configuration_changed, + .get_sclk = &kv_dpm_get_sclk, + .get_mclk = &kv_dpm_get_mclk, + .print_power_state = &kv_dpm_print_power_state, + .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, + .force_performance_level = &kv_dpm_force_performance_level, + .powergate_uvd = &kv_dpm_powergate_uvd, + .enable_bapm = &kv_dpm_enable_bapm, +}; + +static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev) +{ + if (adev->pm.funcs == NULL) + adev->pm.funcs = &kv_dpm_funcs; +} + +static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = { + .set = kv_dpm_set_interrupt_state, + .process = kv_dpm_process_interrupt, +}; + +static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; + adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.h b/drivers/gpu/drm/amd/amdgpu/kv_dpm.h new file mode 100644 index 000000000000..6df0ed41317c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.h @@ -0,0 +1,229 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __KV_DPM_H__ +#define __KV_DPM_H__ + +#define SMU__NUM_SCLK_DPM_STATE 8 +#define SMU__NUM_MCLK_DPM_LEVELS 4 +#define SMU__NUM_LCLK_DPM_LEVELS 8 +#define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */ +#include "smu7_fusion.h" +#include "ppsmc.h" + +#define SUMO_MAX_HARDWARE_POWERLEVELS 5 + +#define SUMO_MAX_NUMBER_VOLTAGES 4 + +struct sumo_vid_mapping_entry { + u16 vid_2bit; + u16 vid_7bit; +}; + +struct sumo_vid_mapping_table { + u32 num_entries; + struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES]; +}; + +struct sumo_sclk_voltage_mapping_entry { + u32 sclk_frequency; + u16 vid_2bit; + u16 rsv; +}; + +struct sumo_sclk_voltage_mapping_table { + u32 num_max_dpm_entries; + struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS]; +}; + +#define TRINITY_AT_DFLT 30 + +#define KV_NUM_NBPSTATES 4 + +enum kv_pt_config_reg_type { + KV_CONFIGREG_MMR = 0, + KV_CONFIGREG_SMC_IND, + KV_CONFIGREG_DIDT_IND, + KV_CONFIGREG_CACHE, + KV_CONFIGREG_MAX +}; + +struct kv_pt_config_reg { + u32 offset; + u32 mask; + u32 shift; + u32 value; + enum kv_pt_config_reg_type type; +}; + +struct kv_lcac_config_values { + u32 block_id; + u32 signal_id; + u32 t; +}; + +struct kv_lcac_config_reg { + u32 cntl; + u32 block_mask; + u32 block_shift; + u32 signal_mask; + u32 signal_shift; + u32 t_mask; + u32 t_shift; + u32 enable_mask; + u32 enable_shift; +}; + +struct kv_pl { + u32 sclk; + u8 vddc_index; + u8 ds_divider_index; + u8 ss_divider_index; + u8 allow_gnb_slow; + u8 force_nbp_state; + u8 display_wm; + u8 vce_wm; +}; + +struct kv_ps { + struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; + u32 num_levels; + bool need_dfs_bypass; + u8 dpm0_pg_nb_ps_lo; + u8 dpm0_pg_nb_ps_hi; + u8 dpmx_nb_ps_lo; + u8 dpmx_nb_ps_hi; +}; + +struct kv_sys_info { + u32 bootup_uma_clk; + u32 bootup_sclk; + u32 dentist_vco_freq; + u32 nb_dpm_enable; + u32 nbp_memory_clock[KV_NUM_NBPSTATES]; + u32 nbp_n_clock[KV_NUM_NBPSTATES]; + u16 bootup_nb_voltage_index; + u8 htc_tmp_lmt; + u8 htc_hyst_lmt; + struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; + struct sumo_vid_mapping_table vid_mapping_table; + u32 uma_channel_number; +}; + +struct kv_power_info { + u32 at[SUMO_MAX_HARDWARE_POWERLEVELS]; + u32 voltage_drop_t; + struct kv_sys_info sys_info; + struct kv_pl boot_pl; + bool enable_nb_ps_policy; + bool disable_nb_ps3_in_battery; + bool video_start; + bool battery_state; + u32 lowest_valid; + u32 highest_valid; + u16 high_voltage_t; + bool cac_enabled; + bool bapm_enable; + /* smc offsets */ + u32 sram_end; + u32 dpm_table_start; + u32 soft_regs_start; + /* dpm SMU tables */ + u8 graphics_dpm_level_count; + u8 uvd_level_count; + u8 vce_level_count; + u8 acp_level_count; + u8 samu_level_count; + u16 fps_high_t; + SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE]; + SMU7_Fusion_ACPILevel acpi_level; + SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD]; + SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE]; + SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP]; + SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU]; + u8 uvd_boot_level; + u8 vce_boot_level; + u8 acp_boot_level; + u8 samu_boot_level; + u8 uvd_interval; + u8 vce_interval; + u8 acp_interval; + u8 samu_interval; + u8 graphics_boot_level; + u8 graphics_interval; + u8 graphics_therm_throttle_enable; + u8 graphics_voltage_change_enable; + u8 graphics_clk_slow_enable; + u8 graphics_clk_slow_divider; + u8 fps_low_t; + u32 low_sclk_interrupt_t; + bool uvd_power_gated; + bool vce_power_gated; + bool acp_power_gated; + bool samu_power_gated; + bool nb_dpm_enabled; + /* flags */ + bool enable_didt; + bool enable_dpm; + bool enable_auto_thermal_throttling; + bool enable_nb_dpm; + /* caps */ + bool caps_cac; + bool caps_power_containment; + bool caps_sq_ramping; + bool caps_db_ramping; + bool caps_td_ramping; + bool caps_tcp_ramping; + bool caps_sclk_throttle_low_notification; + bool caps_fps; + bool caps_uvd_dpm; + bool caps_uvd_pg; + bool caps_vce_pg; + bool caps_samu_pg; + bool caps_acp_pg; + bool caps_stable_p_state; + bool caps_enable_dfs_bypass; + bool caps_sclk_ds; + struct amdgpu_ps current_rps; + struct kv_ps current_ps; + struct amdgpu_ps requested_rps; + struct kv_ps requested_ps; +}; + +/* XXX are these ok? */ +#define KV_TEMP_RANGE_MIN (90 * 1000) +#define KV_TEMP_RANGE_MAX (120 * 1000) + +/* kv_smc.c */ +int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id); +int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask); +int amdgpu_kv_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, + PPSMC_Msg msg, u32 parameter); +int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, + u32 *value, u32 limit); +int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable); +int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable); +int amdgpu_kv_copy_bytes_to_smc(struct amdgpu_device *adev, + u32 smc_start_address, + const u8 *src, u32 byte_count, u32 limit); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/kv_smc.c b/drivers/gpu/drm/amd/amdgpu/kv_smc.c new file mode 100644 index 000000000000..e6b7b42acfe1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/kv_smc.c @@ -0,0 +1,219 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ + +#include "drmP.h" +#include "amdgpu.h" +#include "cikd.h" +#include "kv_dpm.h" + +#include "smu/smu_7_0_0_d.h" +#include "smu/smu_7_0_0_sh_mask.h" + +int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id) +{ + u32 i; + u32 tmp = 0; + + WREG32(mmSMC_MESSAGE_0, id & SMC_MESSAGE_0__SMC_MSG_MASK); + + for (i = 0; i < adev->usec_timeout; i++) { + if ((RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK) != 0) + break; + udelay(1); + } + tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK; + + if (tmp != 1) { + if (tmp == 0xFF) + return -EINVAL; + else if (tmp == 0xFE) + return -EINVAL; + } + + return 0; +} + +int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask) +{ + int ret; + + ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SCLKDPM_GetEnabledMask); + + if (ret == 0) + *enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0); + + return ret; +} + +int amdgpu_kv_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, + PPSMC_Msg msg, u32 parameter) +{ + + WREG32(mmSMC_MSG_ARG_0, parameter); + + return amdgpu_kv_notify_message_to_smu(adev, msg); +} + +static int kv_set_smc_sram_address(struct amdgpu_device *adev, + u32 smc_address, u32 limit) +{ + if (smc_address & 3) + return -EINVAL; + if ((smc_address + 3) > limit) + return -EINVAL; + + WREG32(mmSMC_IND_INDEX_0, smc_address); + WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, + ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); + + return 0; +} + +int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, + u32 *value, u32 limit) +{ + int ret; + + ret = kv_set_smc_sram_address(adev, smc_address, limit); + if (ret) + return ret; + + *value = RREG32(mmSMC_IND_DATA_0); + return 0; +} + +int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable) +{ + if (enable) + return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DPM_Enable); + else + return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DPM_Disable); +} + +int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable) +{ + if (enable) + return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableBAPM); + else + return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableBAPM); +} + +int amdgpu_kv_copy_bytes_to_smc(struct amdgpu_device *adev, + u32 smc_start_address, + const u8 *src, u32 byte_count, u32 limit) +{ + int ret; + u32 data, original_data, addr, extra_shift, t_byte, count, mask; + + if ((smc_start_address + byte_count) > limit) + return -EINVAL; + + addr = smc_start_address; + t_byte = addr & 3; + + /* RMW for the initial bytes */ + if (t_byte != 0) { + addr -= t_byte; + + ret = kv_set_smc_sram_address(adev, addr, limit); + if (ret) + return ret; + + original_data = RREG32(mmSMC_IND_DATA_0); + + data = 0; + mask = 0; + count = 4; + while (count > 0) { + if (t_byte > 0) { + mask = (mask << 8) | 0xff; + t_byte--; + } else if (byte_count > 0) { + data = (data << 8) + *src++; + byte_count--; + mask <<= 8; + } else { + data <<= 8; + mask = (mask << 8) | 0xff; + } + count--; + } + + data |= original_data & mask; + + ret = kv_set_smc_sram_address(adev, addr, limit); + if (ret) + return ret; + + WREG32(mmSMC_IND_DATA_0, data); + + addr += 4; + } + + while (byte_count >= 4) { + /* SMC address space is BE */ + data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3]; + + ret = kv_set_smc_sram_address(adev, addr, limit); + if (ret) + return ret; + + WREG32(mmSMC_IND_DATA_0, data); + + src += 4; + byte_count -= 4; + addr += 4; + } + + /* RMW for the final bytes */ + if (byte_count > 0) { + data = 0; + + ret = kv_set_smc_sram_address(adev, addr, limit); + if (ret) + return ret; + + original_data = RREG32(mmSMC_IND_DATA_0); + + extra_shift = 8 * (4 - byte_count); + + while (byte_count > 0) { + /* SMC address space is BE */ + data = (data << 8) + *src++; + byte_count--; + } + + data <<= extra_shift; + + data |= (original_data & ~((~0UL) << extra_shift)); + + ret = kv_set_smc_sram_address(adev, addr, limit); + if (ret) + return ret; + + WREG32(mmSMC_IND_DATA_0, data); + } + return 0; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/smu7.h b/drivers/gpu/drm/amd/amdgpu/smu7.h new file mode 100644 index 000000000000..75a380a15292 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smu7.h @@ -0,0 +1,170 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU7_H +#define SMU7_H + +#pragma pack(push, 1) + +#define SMU7_CONTEXT_ID_SMC 1 +#define SMU7_CONTEXT_ID_VBIOS 2 + + +#define SMU7_CONTEXT_ID_SMC 1 +#define SMU7_CONTEXT_ID_VBIOS 2 + +#define SMU7_MAX_LEVELS_VDDC 8 +#define SMU7_MAX_LEVELS_VDDCI 4 +#define SMU7_MAX_LEVELS_MVDD 4 +#define SMU7_MAX_LEVELS_VDDNB 8 + +#define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV +#define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM +#define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels +#define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. +#define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. +#define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE. +#define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP. +#define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. +#define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. + +#define DPM_NO_LIMIT 0 +#define DPM_NO_UP 1 +#define DPM_GO_DOWN 2 +#define DPM_GO_UP 3 + +#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 +#define SMU7_FIRST_DPM_MEMORY_LEVEL 0 + +#define GPIO_CLAMP_MODE_VRHOT 1 +#define GPIO_CLAMP_MODE_THERM 2 +#define GPIO_CLAMP_MODE_DC 4 + +#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 +#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7< + */ + +#include +#include +#include "amdgpu.h" +#include "amdgpu_uvd.h" +#include "cikd.h" + +#include "uvd/uvd_4_2_d.h" +#include "uvd/uvd_4_2_sh_mask.h" + +#include "oss/oss_2_0_d.h" +#include "oss/oss_2_0_sh_mask.h" + +static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); +static void uvd_v4_2_init_cg(struct amdgpu_device *adev); +static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); +static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); +static int uvd_v4_2_start(struct amdgpu_device *adev); +static void uvd_v4_2_stop(struct amdgpu_device *adev); + +/** + * uvd_v4_2_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32(mmUVD_RBC_RB_RPTR); +} + +/** + * uvd_v4_2_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32(mmUVD_RBC_RB_WPTR); +} + +/** + * uvd_v4_2_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); +} + +static int uvd_v4_2_early_init(struct amdgpu_device *adev) +{ + uvd_v4_2_set_ring_funcs(adev); + uvd_v4_2_set_irq_funcs(adev); + + return 0; +} + +static int uvd_v4_2_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + /* UVD TRAP */ + r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); + if (r) + return r; + + r = amdgpu_uvd_sw_init(adev); + if (r) + return r; + + r = amdgpu_uvd_resume(adev); + if (r) + return r; + + ring = &adev->uvd.ring; + sprintf(ring->name, "uvd"); + r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, + &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + + return r; +} + +static int uvd_v4_2_sw_fini(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_uvd_suspend(adev); + if (r) + return r; + + r = amdgpu_uvd_sw_fini(adev); + if (r) + return r; + + return r; +} + +/** + * uvd_v4_2_hw_init - start and test UVD block + * + * @adev: amdgpu_device pointer + * + * Initialize the hardware, boot up the VCPU and do some testing + */ +static int uvd_v4_2_hw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->uvd.ring; + uint32_t tmp; + int r; + + /* raise clocks while booting up the VCPU */ + amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); + + r = uvd_v4_2_start(adev); + if (r) + goto done; + + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + goto done; + } + + r = amdgpu_ring_lock(ring, 10); + if (r) { + DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); + goto done; + } + + tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + /* Clear timeout status bits */ + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); + amdgpu_ring_write(ring, 0x8); + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); + amdgpu_ring_write(ring, 3); + + amdgpu_ring_unlock_commit(ring); + +done: + /* lower clocks again */ + amdgpu_asic_set_uvd_clocks(adev, 0, 0); + + if (!r) + DRM_INFO("UVD initialized successfully.\n"); + + return r; +} + +/** + * uvd_v4_2_hw_fini - stop the hardware block + * + * @adev: amdgpu_device pointer + * + * Stop the UVD block, mark ring as not ready any more + */ +static int uvd_v4_2_hw_fini(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->uvd.ring; + + uvd_v4_2_stop(adev); + ring->ready = false; + + return 0; +} + +static int uvd_v4_2_suspend(struct amdgpu_device *adev) +{ + int r; + + r = uvd_v4_2_hw_fini(adev); + if (r) + return r; + + r = amdgpu_uvd_suspend(adev); + if (r) + return r; + + return r; +} + +static int uvd_v4_2_resume(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_uvd_resume(adev); + if (r) + return r; + + r = uvd_v4_2_hw_init(adev); + if (r) + return r; + + return r; +} + +/** + * uvd_v4_2_start - start UVD block + * + * @adev: amdgpu_device pointer + * + * Setup and start the UVD block + */ +static int uvd_v4_2_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->uvd.ring; + uint32_t rb_bufsz; + int i, j, r; + + /* disable byte swapping */ + u32 lmi_swap_cntl = 0; + u32 mp_swap_cntl = 0; + + uvd_v4_2_mc_resume(adev); + + /* disable clock gating */ + WREG32(mmUVD_CGC_GATE, 0); + + /* disable interupt */ + WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); + + /* Stall UMC and register bus before resetting VCPU */ + WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); + mdelay(1); + + /* put LMI, VCPU, RBC etc... into reset */ + WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | + UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | + UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | + UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); + mdelay(5); + + /* take UVD block out of reset */ + WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); + mdelay(5); + + /* initialize UVD memory controller */ + WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | + (1 << 21) | (1 << 9) | (1 << 20)); + +#ifdef __BIG_ENDIAN + /* swap (8 in 32) RB and IB */ + lmi_swap_cntl = 0xa; + mp_swap_cntl = 0; +#endif + WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); + WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); + + WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); + WREG32(mmUVD_MPC_SET_MUXA1, 0x0); + WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); + WREG32(mmUVD_MPC_SET_MUXB1, 0x0); + WREG32(mmUVD_MPC_SET_ALU, 0); + WREG32(mmUVD_MPC_SET_MUX, 0x88); + + /* take all subblocks out of reset, except VCPU */ + WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(5); + + /* enable VCPU clock */ + WREG32(mmUVD_VCPU_CNTL, 1 << 9); + + /* enable UMC */ + WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); + + /* boot up the VCPU */ + WREG32(mmUVD_SOFT_RESET, 0); + mdelay(10); + + for (i = 0; i < 10; ++i) { + uint32_t status; + for (j = 0; j < 100; ++j) { + status = RREG32(mmUVD_STATUS); + if (status & 2) + break; + mdelay(10); + } + r = 0; + if (status & 2) + break; + + DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); + WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, + ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(10); + WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(10); + r = -1; + } + + if (r) { + DRM_ERROR("UVD not responding, giving up!!!\n"); + return r; + } + + /* enable interupt */ + WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); + + /* force RBC into idle state */ + WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); + + /* Set the write pointer delay */ + WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); + + /* programm the 4GB memory segment for rptr and ring buffer */ + WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | + (0x7 << 16) | (0x1 << 31)); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(mmUVD_RBC_RB_RPTR, 0x0); + + ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); + WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); + + /* set the ring address */ + WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); + + /* Set ring buffer size */ + rb_bufsz = order_base_2(ring->ring_size); + rb_bufsz = (0x1 << 8) | rb_bufsz; + WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); + + return 0; +} + +/** + * uvd_v4_2_stop - stop UVD block + * + * @adev: amdgpu_device pointer + * + * stop the UVD block + */ +static void uvd_v4_2_stop(struct amdgpu_device *adev) +{ + /* force RBC into idle state */ + WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); + + /* Stall UMC and register bus before resetting VCPU */ + WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); + mdelay(1); + + /* put VCPU into reset */ + WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(5); + + /* disable VCPU clock */ + WREG32(mmUVD_VCPU_CNTL, 0x0); + + /* Unstall UMC and register bus */ + WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); +} + +/** + * uvd_v4_2_ring_emit_fence - emit an fence & trap command + * + * @ring: amdgpu_ring pointer + * @fence: fence to emit + * + * Write a fence and a trap command to the ring. + */ +static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + bool write64bit) +{ + WARN_ON(write64bit); + + amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); + amdgpu_ring_write(ring, seq); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); + amdgpu_ring_write(ring, addr & 0xffffffff); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); + amdgpu_ring_write(ring, 2); +} + +/** + * uvd_v4_2_ring_emit_semaphore - emit semaphore command + * + * @ring: amdgpu_ring pointer + * @semaphore: semaphore to emit commands for + * @emit_wait: true if we should emit a wait command + * + * Emit a semaphore command (either wait or signal) to the UVD ring. + */ +static bool uvd_v4_2_ring_emit_semaphore(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore, + bool emit_wait) +{ + uint64_t addr = semaphore->gpu_addr; + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0)); + amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0)); + amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0)); + amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); + + return true; +} + +/** + * uvd_v4_2_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer + * + * Test if we can successfully write to the context register + */ +static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t tmp = 0; + unsigned i; + int r; + + WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); + r = amdgpu_ring_lock(ring, 3); + if (r) { + DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", + ring->idx, r); + return r; + } + amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_unlock_commit(ring); + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(mmUVD_CONTEXT_ID); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", + ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", + ring->idx, tmp); + r = -EINVAL; + } + return r; +} + +/** + * uvd_v4_2_ring_emit_ib - execute indirect buffer + * + * @ring: amdgpu_ring pointer + * @ib: indirect buffer to execute + * + * Write ring commands to execute the indirect buffer + */ +static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib) +{ + amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); + amdgpu_ring_write(ring, ib->gpu_addr); + amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); + amdgpu_ring_write(ring, ib->length_dw); +} + +/** + * uvd_v4_2_ring_test_ib - test ib execution + * + * @ring: amdgpu_ring pointer + * + * Test if we can successfully execute an IB + */ +static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_fence *fence = NULL; + int r; + + r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); + if (r) { + DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r); + return r; + } + + r = amdgpu_uvd_get_create_msg(ring, 1, NULL); + if (r) { + DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); + goto error; + } + + r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence); + if (r) { + DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); + goto error; + } + + r = amdgpu_fence_wait(fence, false); + if (r) { + DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + goto error; + } + DRM_INFO("ib test on ring %d succeeded\n", ring->idx); +error: + amdgpu_fence_unref(&fence); + amdgpu_asic_set_uvd_clocks(adev, 0, 0); + return r; +} + +/** + * uvd_v4_2_mc_resume - memory controller programming + * + * @adev: amdgpu_device pointer + * + * Let the UVD memory controller know it's offsets + */ +static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) +{ + uint64_t addr; + uint32_t size; + + /* programm the VCPU memory controller bits 0-27 */ + addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; + size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; + WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); + WREG32(mmUVD_VCPU_CACHE_SIZE0, size); + + addr += size; + size = AMDGPU_UVD_STACK_SIZE >> 3; + WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); + WREG32(mmUVD_VCPU_CACHE_SIZE1, size); + + addr += size; + size = AMDGPU_UVD_HEAP_SIZE >> 3; + WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); + WREG32(mmUVD_VCPU_CACHE_SIZE2, size); + + /* bits 28-31 */ + addr = (adev->uvd.gpu_addr >> 28) & 0xF; + WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); + + /* bits 32-39 */ + addr = (adev->uvd.gpu_addr >> 32) & 0xFF; + WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); + + uvd_v4_2_init_cg(adev); +} + +static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, + bool enable) +{ + u32 orig, data; + + if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG)) { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data = 0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); + + orig = data = RREG32(mmUVD_CGC_CTRL); + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } else { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data &= ~0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); + + orig = data = RREG32(mmUVD_CGC_CTRL); + data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } +} + +static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, + bool sw_mode) +{ + u32 tmp, tmp2; + + tmp = RREG32(mmUVD_CGC_CTRL); + tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); + tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | + (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | + (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); + + if (sw_mode) { + tmp &= ~0x7ffff800; + tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | + UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | + (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); + } else { + tmp |= 0x7ffff800; + tmp2 = 0; + } + + WREG32(mmUVD_CGC_CTRL, tmp); + WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); +} + +static void uvd_v4_2_init_cg(struct amdgpu_device *adev) +{ + bool hw_mode = true; + + if (hw_mode) { + uvd_v4_2_set_dcm(adev, false); + } else { + u32 tmp = RREG32(mmUVD_CGC_CTRL); + tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + WREG32(mmUVD_CGC_CTRL, tmp); + } +} + +static bool uvd_v4_2_is_idle(struct amdgpu_device *adev) +{ + return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); +} + +static int uvd_v4_2_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) + return 0; + } + return -ETIMEDOUT; +} + +static int uvd_v4_2_soft_reset(struct amdgpu_device *adev) +{ + uvd_v4_2_stop(adev); + + WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, + ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); + mdelay(5); + + return uvd_v4_2_start(adev); +} + +static void uvd_v4_2_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "UVD 4.2 registers\n"); + dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", + RREG32(mmUVD_SEMA_ADDR_LOW)); + dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", + RREG32(mmUVD_SEMA_ADDR_HIGH)); + dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", + RREG32(mmUVD_SEMA_CMD)); + dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", + RREG32(mmUVD_GPCOM_VCPU_CMD)); + dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", + RREG32(mmUVD_GPCOM_VCPU_DATA0)); + dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", + RREG32(mmUVD_GPCOM_VCPU_DATA1)); + dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", + RREG32(mmUVD_ENGINE_CNTL)); + dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_CNTL)); + dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", + RREG32(mmUVD_LMI_EXT40_ADDR)); + dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", + RREG32(mmUVD_CTX_INDEX)); + dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", + RREG32(mmUVD_CTX_DATA)); + dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", + RREG32(mmUVD_CGC_GATE)); + dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", + RREG32(mmUVD_CGC_CTRL)); + dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", + RREG32(mmUVD_LMI_CTRL2)); + dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", + RREG32(mmUVD_MASTINT_EN)); + dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", + RREG32(mmUVD_LMI_ADDR_EXT)); + dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", + RREG32(mmUVD_LMI_CTRL)); + dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", + RREG32(mmUVD_LMI_SWAP_CNTL)); + dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", + RREG32(mmUVD_MP_SWAP_CNTL)); + dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXA0)); + dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXA1)); + dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXB0)); + dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXB1)); + dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUX)); + dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", + RREG32(mmUVD_MPC_SET_ALU)); + dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_OFFSET0)); + dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_SIZE0)); + dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_OFFSET1)); + dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_SIZE1)); + dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_OFFSET2)); + dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_SIZE2)); + dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", + RREG32(mmUVD_VCPU_CNTL)); + dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", + RREG32(mmUVD_SOFT_RESET)); + dev_info(adev->dev, " UVD_RBC_IB_BASE=0x%08X\n", + RREG32(mmUVD_RBC_IB_BASE)); + dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", + RREG32(mmUVD_RBC_IB_SIZE)); + dev_info(adev->dev, " UVD_RBC_RB_BASE=0x%08X\n", + RREG32(mmUVD_RBC_RB_BASE)); + dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", + RREG32(mmUVD_RBC_RB_RPTR)); + dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", + RREG32(mmUVD_RBC_RB_WPTR)); + dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", + RREG32(mmUVD_RBC_RB_WPTR_CNTL)); + dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", + RREG32(mmUVD_RBC_RB_CNTL)); + dev_info(adev->dev, " UVD_STATUS=0x%08X\n", + RREG32(mmUVD_STATUS)); + dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", + RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); + dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); + dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); + dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); + dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", + RREG32(mmUVD_CONTEXT_ID)); +} + +static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + // TODO + return 0; +} + +static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_DEBUG("IH: UVD TRAP\n"); + amdgpu_fence_process(&adev->uvd.ring); + return 0; +} + +static int uvd_v4_2_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + bool gate = false; + + if (state == AMDGPU_CG_STATE_GATE) + gate = true; + + uvd_v4_2_enable_mgcg(adev, gate); + + return 0; +} + +static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + /* This doesn't actually powergate the UVD block. + * That's done in the dpm code via the SMC. This + * just re-inits the block as necessary. The actual + * gating still happens in the dpm code. We should + * revisit this when there is a cleaner line between + * the smc and the hw blocks + */ + if (state == AMDGPU_PG_STATE_GATE) { + uvd_v4_2_stop(adev); + return 0; + } else { + return uvd_v4_2_start(adev); + } +} + +const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs = { + .early_init = uvd_v4_2_early_init, + .late_init = NULL, + .sw_init = uvd_v4_2_sw_init, + .sw_fini = uvd_v4_2_sw_fini, + .hw_init = uvd_v4_2_hw_init, + .hw_fini = uvd_v4_2_hw_fini, + .suspend = uvd_v4_2_suspend, + .resume = uvd_v4_2_resume, + .is_idle = uvd_v4_2_is_idle, + .wait_for_idle = uvd_v4_2_wait_for_idle, + .soft_reset = uvd_v4_2_soft_reset, + .print_status = uvd_v4_2_print_status, + .set_clockgating_state = uvd_v4_2_set_clockgating_state, + .set_powergating_state = uvd_v4_2_set_powergating_state, +}; + +static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { + .get_rptr = uvd_v4_2_ring_get_rptr, + .get_wptr = uvd_v4_2_ring_get_wptr, + .set_wptr = uvd_v4_2_ring_set_wptr, + .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_ib = uvd_v4_2_ring_emit_ib, + .emit_fence = uvd_v4_2_ring_emit_fence, + .emit_semaphore = uvd_v4_2_ring_emit_semaphore, + .test_ring = uvd_v4_2_ring_test_ring, + .test_ib = uvd_v4_2_ring_test_ib, + .is_lockup = amdgpu_ring_test_lockup, +}; + +static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) +{ + adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs; +} + +static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { + .set = uvd_v4_2_set_interrupt_state, + .process = uvd_v4_2_process_interrupt, +}; + +static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->uvd.irq.num_types = 1; + adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h new file mode 100644 index 000000000000..323a6d828dfe --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __UVD_V4_2_H__ +#define __UVD_V4_2_H__ + +extern const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c new file mode 100644 index 000000000000..b47c16da6bf8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -0,0 +1,642 @@ +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * Authors: Christian König + */ + +#include +#include +#include "amdgpu.h" +#include "amdgpu_vce.h" +#include "cikd.h" + +#include "vce/vce_2_0_d.h" +#include "vce/vce_2_0_sh_mask.h" + +#include "oss/oss_2_0_d.h" +#include "oss/oss_2_0_sh_mask.h" + +static void vce_v2_0_mc_resume(struct amdgpu_device *adev); +static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev); +static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev); + +/** + * vce_v2_0_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->vce.ring[0]) + return RREG32(mmVCE_RB_RPTR); + else + return RREG32(mmVCE_RB_RPTR2); +} + +/** + * vce_v2_0_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->vce.ring[0]) + return RREG32(mmVCE_RB_WPTR); + else + return RREG32(mmVCE_RB_WPTR2); +} + +/** + * vce_v2_0_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->vce.ring[0]) + WREG32(mmVCE_RB_WPTR, ring->wptr); + else + WREG32(mmVCE_RB_WPTR2, ring->wptr); +} + +/** + * vce_v2_0_start - start VCE block + * + * @adev: amdgpu_device pointer + * + * Setup and start the VCE block + */ +static int vce_v2_0_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int i, j, r; + + vce_v2_0_mc_resume(adev); + + /* set BUSY flag */ + WREG32_P(mmVCE_STATUS, 1, ~1); + + ring = &adev->vce.ring[0]; + WREG32(mmVCE_RB_RPTR, ring->wptr); + WREG32(mmVCE_RB_WPTR, ring->wptr); + WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); + WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); + + ring = &adev->vce.ring[1]; + WREG32(mmVCE_RB_RPTR2, ring->wptr); + WREG32(mmVCE_RB_WPTR2, ring->wptr); + WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); + WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); + WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); + + WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK); + + WREG32_P(mmVCE_SOFT_RESET, + VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + + mdelay(100); + + WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + + for (i = 0; i < 10; ++i) { + uint32_t status; + for (j = 0; j < 100; ++j) { + status = RREG32(mmVCE_STATUS); + if (status & 2) + break; + mdelay(10); + } + r = 0; + if (status & 2) + break; + + DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n"); + WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(10); + WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(10); + r = -1; + } + + /* clear BUSY flag */ + WREG32_P(mmVCE_STATUS, 0, ~1); + + if (r) { + DRM_ERROR("VCE not responding, giving up!!!\n"); + return r; + } + + return 0; +} + +static int vce_v2_0_early_init(struct amdgpu_device *adev) +{ + vce_v2_0_set_ring_funcs(adev); + vce_v2_0_set_irq_funcs(adev); + + return 0; +} + +static int vce_v2_0_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + /* VCE */ + r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq); + if (r) + return r; + + r = amdgpu_vce_sw_init(adev); + if (r) + return r; + + r = amdgpu_vce_resume(adev); + if (r) + return r; + + ring = &adev->vce.ring[0]; + sprintf(ring->name, "vce0"); + r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, + &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); + if (r) + return r; + + ring = &adev->vce.ring[1]; + sprintf(ring->name, "vce1"); + r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, + &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); + if (r) + return r; + + return r; +} + +static int vce_v2_0_sw_fini(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_vce_suspend(adev); + if (r) + return r; + + r = amdgpu_vce_sw_fini(adev); + if (r) + return r; + + return r; +} + +static int vce_v2_0_hw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + r = vce_v2_0_start(adev); + if (r) + return r; + + ring = &adev->vce.ring[0]; + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + return r; + } + + ring = &adev->vce.ring[1]; + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + return r; + } + + DRM_INFO("VCE initialized successfully.\n"); + + return 0; +} + +static int vce_v2_0_hw_fini(struct amdgpu_device *adev) +{ + // TODO + return 0; +} + +static int vce_v2_0_suspend(struct amdgpu_device *adev) +{ + int r; + + r = vce_v2_0_hw_fini(adev); + if (r) + return r; + + r = amdgpu_vce_suspend(adev); + if (r) + return r; + + return r; +} + +static int vce_v2_0_resume(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_vce_resume(adev); + if (r) + return r; + + r = vce_v2_0_hw_init(adev); + if (r) + return r; + + return r; +} + +static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated) +{ + u32 tmp; + + if (gated) { + tmp = RREG32(mmVCE_CLOCK_GATING_B); + tmp |= 0xe70000; + WREG32(mmVCE_CLOCK_GATING_B, tmp); + + tmp = RREG32(mmVCE_UENC_CLOCK_GATING); + tmp |= 0xff000000; + WREG32(mmVCE_UENC_CLOCK_GATING, tmp); + + tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); + tmp &= ~0x3fc; + WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); + + WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0); + } else { + tmp = RREG32(mmVCE_CLOCK_GATING_B); + tmp |= 0xe7; + tmp &= ~0xe70000; + WREG32(mmVCE_CLOCK_GATING_B, tmp); + + tmp = RREG32(mmVCE_UENC_CLOCK_GATING); + tmp |= 0x1fe000; + tmp &= ~0xff000000; + WREG32(mmVCE_UENC_CLOCK_GATING, tmp); + + tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); + tmp |= 0x3fc; + WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); + } +} + +static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated) +{ + u32 orig, tmp; + + tmp = RREG32(mmVCE_CLOCK_GATING_B); + tmp &= ~0x00060006; + if (gated) { + tmp |= 0xe10000; + } else { + tmp |= 0xe1; + tmp &= ~0xe10000; + } + WREG32(mmVCE_CLOCK_GATING_B, tmp); + + orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING); + tmp &= ~0x1fe000; + tmp &= ~0xff000000; + if (tmp != orig) + WREG32(mmVCE_UENC_CLOCK_GATING, tmp); + + orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); + tmp &= ~0x3fc; + if (tmp != orig) + WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); + + if (gated) + WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0); +} + +static void vce_v2_0_disable_cg(struct amdgpu_device *adev) +{ + WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7); +} + +static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable) +{ + bool sw_cg = false; + + if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_VCE_MGCG)) { + if (sw_cg) + vce_v2_0_set_sw_cg(adev, true); + else + vce_v2_0_set_dyn_cg(adev, true); + } else { + vce_v2_0_disable_cg(adev); + + if (sw_cg) + vce_v2_0_set_sw_cg(adev, false); + else + vce_v2_0_set_dyn_cg(adev, false); + } +} + +static void vce_v2_0_init_cg(struct amdgpu_device *adev) +{ + u32 tmp; + + tmp = RREG32(mmVCE_CLOCK_GATING_A); + tmp &= ~0xfff; + tmp |= ((0 << 0) | (4 << 4)); + tmp |= 0x40000; + WREG32(mmVCE_CLOCK_GATING_A, tmp); + + tmp = RREG32(mmVCE_UENC_CLOCK_GATING); + tmp &= ~0xfff; + tmp |= ((0 << 0) | (4 << 4)); + WREG32(mmVCE_UENC_CLOCK_GATING, tmp); + + tmp = RREG32(mmVCE_CLOCK_GATING_B); + tmp |= 0x10; + tmp &= ~0x100000; + WREG32(mmVCE_CLOCK_GATING_B, tmp); +} + +static void vce_v2_0_mc_resume(struct amdgpu_device *adev) +{ + uint64_t addr = adev->vce.gpu_addr; + uint32_t size; + + WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); + WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); + WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); + WREG32(mmVCE_CLOCK_GATING_B, 0xf7); + + WREG32(mmVCE_LMI_CTRL, 0x00398000); + WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); + WREG32(mmVCE_LMI_SWAP_CNTL, 0); + WREG32(mmVCE_LMI_SWAP_CNTL1, 0); + WREG32(mmVCE_LMI_VM_CTRL, 0); + + addr += AMDGPU_VCE_FIRMWARE_OFFSET; + size = AMDGPU_GPU_PAGE_ALIGN(adev->vce.fw->size); + WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE0, size); + + addr += size; + size = AMDGPU_VCE_STACK_SIZE; + WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE1, size); + + addr += size; + size = AMDGPU_VCE_HEAP_SIZE; + WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE2, size); + + WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); + + WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK, + ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); + + vce_v2_0_init_cg(adev); +} + +static bool vce_v2_0_is_idle(struct amdgpu_device *adev) +{ + return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); +} + +static int vce_v2_0_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK)) + return 0; + } + return -ETIMEDOUT; +} + +static int vce_v2_0_soft_reset(struct amdgpu_device *adev) +{ + WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK, + ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK); + mdelay(5); + + return vce_v2_0_start(adev); +} + +static void vce_v2_0_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "VCE 2.0 registers\n"); + dev_info(adev->dev, " VCE_STATUS=0x%08X\n", + RREG32(mmVCE_STATUS)); + dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n", + RREG32(mmVCE_VCPU_CNTL)); + dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_OFFSET0)); + dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_SIZE0)); + dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_OFFSET1)); + dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_SIZE1)); + dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_OFFSET2)); + dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_SIZE2)); + dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n", + RREG32(mmVCE_SOFT_RESET)); + dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n", + RREG32(mmVCE_RB_BASE_LO2)); + dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n", + RREG32(mmVCE_RB_BASE_HI2)); + dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n", + RREG32(mmVCE_RB_SIZE2)); + dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n", + RREG32(mmVCE_RB_RPTR2)); + dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n", + RREG32(mmVCE_RB_WPTR2)); + dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n", + RREG32(mmVCE_RB_BASE_LO)); + dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n", + RREG32(mmVCE_RB_BASE_HI)); + dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n", + RREG32(mmVCE_RB_SIZE)); + dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n", + RREG32(mmVCE_RB_RPTR)); + dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n", + RREG32(mmVCE_RB_WPTR)); + dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n", + RREG32(mmVCE_CLOCK_GATING_A)); + dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n", + RREG32(mmVCE_CLOCK_GATING_B)); + dev_info(adev->dev, " VCE_CGTT_CLK_OVERRIDE=0x%08X\n", + RREG32(mmVCE_CGTT_CLK_OVERRIDE)); + dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n", + RREG32(mmVCE_UENC_CLOCK_GATING)); + dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n", + RREG32(mmVCE_UENC_REG_CLOCK_GATING)); + dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n", + RREG32(mmVCE_SYS_INT_EN)); + dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n", + RREG32(mmVCE_LMI_CTRL2)); + dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n", + RREG32(mmVCE_LMI_CTRL)); + dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n", + RREG32(mmVCE_LMI_VM_CTRL)); + dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n", + RREG32(mmVCE_LMI_SWAP_CNTL)); + dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n", + RREG32(mmVCE_LMI_SWAP_CNTL1)); + dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n", + RREG32(mmVCE_LMI_CACHE_CTRL)); +} + +static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + uint32_t val = 0; + + if (state == AMDGPU_IRQ_STATE_ENABLE) + val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; + + WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); + return 0; +} + +static int vce_v2_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_DEBUG("IH: VCE\n"); + switch (entry->src_data) { + case 0: + amdgpu_fence_process(&adev->vce.ring[0]); + break; + case 1: + amdgpu_fence_process(&adev->vce.ring[1]); + break; + default: + DRM_ERROR("Unhandled interrupt: %d %d\n", + entry->src_id, entry->src_data); + break; + } + + return 0; +} + +static int vce_v2_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + bool gate = false; + + if (state == AMDGPU_CG_STATE_GATE) + gate = true; + + vce_v2_0_enable_mgcg(adev, gate); + + return 0; +} + +static int vce_v2_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + /* This doesn't actually powergate the VCE block. + * That's done in the dpm code via the SMC. This + * just re-inits the block as necessary. The actual + * gating still happens in the dpm code. We should + * revisit this when there is a cleaner line between + * the smc and the hw blocks + */ + if (state == AMDGPU_PG_STATE_GATE) + /* XXX do we need a vce_v2_0_stop()? */ + return 0; + else + return vce_v2_0_start(adev); +} + +const struct amdgpu_ip_funcs vce_v2_0_ip_funcs = { + .early_init = vce_v2_0_early_init, + .late_init = NULL, + .sw_init = vce_v2_0_sw_init, + .sw_fini = vce_v2_0_sw_fini, + .hw_init = vce_v2_0_hw_init, + .hw_fini = vce_v2_0_hw_fini, + .suspend = vce_v2_0_suspend, + .resume = vce_v2_0_resume, + .is_idle = vce_v2_0_is_idle, + .wait_for_idle = vce_v2_0_wait_for_idle, + .soft_reset = vce_v2_0_soft_reset, + .print_status = vce_v2_0_print_status, + .set_clockgating_state = vce_v2_0_set_clockgating_state, + .set_powergating_state = vce_v2_0_set_powergating_state, +}; + +static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { + .get_rptr = vce_v2_0_ring_get_rptr, + .get_wptr = vce_v2_0_ring_get_wptr, + .set_wptr = vce_v2_0_ring_set_wptr, + .parse_cs = amdgpu_vce_ring_parse_cs, + .emit_ib = amdgpu_vce_ring_emit_ib, + .emit_fence = amdgpu_vce_ring_emit_fence, + .emit_semaphore = amdgpu_vce_ring_emit_semaphore, + .test_ring = amdgpu_vce_ring_test_ring, + .test_ib = amdgpu_vce_ring_test_ib, + .is_lockup = amdgpu_ring_test_lockup, +}; + +static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev) +{ + adev->vce.ring[0].funcs = &vce_v2_0_ring_funcs; + adev->vce.ring[1].funcs = &vce_v2_0_ring_funcs; +} + +static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = { + .set = vce_v2_0_set_interrupt_state, + .process = vce_v2_0_process_interrupt, +}; + +static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->vce.irq.num_types = 1; + adev->vce.irq.funcs = &vce_v2_0_irq_funcs; +}; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h new file mode 100644 index 000000000000..8eb1cf227ea6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VCE_V2_0_H__ +#define __VCE_V2_0_H__ + +extern const struct amdgpu_ip_funcs vce_v2_0_ip_funcs; + +#endif -- cgit v1.2.3 From aaa36a976bbb9b02a54c087ff390c0bad1d18e3e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Apr 2015 17:31:14 -0400 Subject: drm/amdgpu: Add initial VI support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds initial support for VI asics. This includes Iceland, Tonga, and Carrizo. Our inital focus as been Carrizo, so there are still gaps in support for Tonga and Iceland, notably power management. Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 38 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 +- drivers/gpu/drm/amd/amdgpu/clearstate_vi.h | 944 +++++ drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 1712 ++++++++ drivers/gpu/drm/amd/amdgpu/cz_dpm.h | 235 ++ drivers/gpu/drm/amd/amdgpu/cz_ih.c | 435 ++ drivers/gpu/drm/amd/amdgpu/cz_ih.h | 29 + drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h | 185 + drivers/gpu/drm/amd/amdgpu/cz_smc.c | 962 +++++ drivers/gpu/drm/amd/amdgpu/cz_smumgr.h | 94 + drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 3871 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.h | 29 + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 3871 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.h | 29 + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4286 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h | 33 + drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1271 ++++++ drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h | 36 + drivers/gpu/drm/amd/amdgpu/iceland_dpm.c | 172 + drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 435 ++ drivers/gpu/drm/amd/amdgpu/iceland_ih.h | 29 + drivers/gpu/drm/amd/amdgpu/iceland_sdma_pkt_open.h | 2167 ++++++++++ drivers/gpu/drm/amd/amdgpu/iceland_smc.c | 675 +++ drivers/gpu/drm/amd/amdgpu/iceland_smumgr.h | 41 + drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 1447 +++++++ drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h | 29 + drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 1514 +++++++ drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h | 29 + drivers/gpu/drm/amd/amdgpu/smu8.h | 72 + drivers/gpu/drm/amd/amdgpu/smu8_fusion.h | 127 + drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h | 147 + drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h | 100 + drivers/gpu/drm/amd/amdgpu/tonga_dpm.c | 172 + drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 458 +++ drivers/gpu/drm/amd/amdgpu/tonga_ih.h | 29 + drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h | 198 + drivers/gpu/drm/amd/amdgpu/tonga_sdma_pkt_open.h | 2240 ++++++++++ drivers/gpu/drm/amd/amdgpu/tonga_smc.c | 852 ++++ drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h | 42 + drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 830 ++++ drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h | 29 + drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 810 ++++ drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h | 29 + drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 521 +++ drivers/gpu/drm/amd/amdgpu/vce_v3_0.h | 29 + drivers/gpu/drm/amd/amdgpu/vi.c | 1373 +++++++ drivers/gpu/drm/amd/amdgpu/vi.h | 33 + drivers/gpu/drm/amd/amdgpu/vi_dpm.h | 36 + drivers/gpu/drm/amd/amdgpu/vid.h | 363 ++ 49 files changed, 33097 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_vi.h create mode 100644 drivers/gpu/drm/amd/amdgpu/cz_dpm.c create mode 100644 drivers/gpu/drm/amd/amdgpu/cz_dpm.h create mode 100644 drivers/gpu/drm/amd/amdgpu/cz_ih.c create mode 100644 drivers/gpu/drm/amd/amdgpu/cz_ih.h create mode 100644 drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h create mode 100644 drivers/gpu/drm/amd/amdgpu/cz_smc.c create mode 100644 drivers/gpu/drm/amd/amdgpu/cz_smumgr.h create mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v10_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v11_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/iceland_dpm.c create mode 100644 drivers/gpu/drm/amd/amdgpu/iceland_ih.c create mode 100644 drivers/gpu/drm/amd/amdgpu/iceland_ih.h create mode 100644 drivers/gpu/drm/amd/amdgpu/iceland_sdma_pkt_open.h create mode 100644 drivers/gpu/drm/amd/amdgpu/iceland_smc.c create mode 100644 drivers/gpu/drm/amd/amdgpu/iceland_smumgr.h create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/smu8.h create mode 100644 drivers/gpu/drm/amd/amdgpu/smu8_fusion.h create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h create mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_dpm.c create mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_ih.c create mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_ih.h create mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h create mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_sdma_pkt_open.h create mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_smc.c create mode 100644 drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v3_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/vi.c create mode 100644 drivers/gpu/drm/amd/amdgpu/vi.h create mode 100644 drivers/gpu/drm/amd/amdgpu/vi_dpm.h create mode 100644 drivers/gpu/drm/amd/amdgpu/vid.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index aec28866945f..9a573e87cdd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -18,29 +18,57 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o +# add asic specific block amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o gmc_v7_0.o cik_ih.o kv_smc.o kv_dpm.o \ ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o +amdgpu-y += \ + vi.o + +# add GMC block +amdgpu-y += \ + gmc_v8_0.o + # add IH block amdgpu-y += \ amdgpu_irq.o \ - amdgpu_ih.o + amdgpu_ih.o \ + iceland_ih.o \ + tonga_ih.o \ + cz_ih.o # add SMC block amdgpu-y += \ - amdgpu_dpm.o + amdgpu_dpm.o \ + cz_smc.o cz_dpm.o \ + tonga_smc.o tonga_dpm.o \ + iceland_smc.o iceland_dpm.o + +# add DCE block +amdgpu-y += \ + dce_v10_0.o \ + dce_v11_0.o # add GFX block amdgpu-y += \ - amdgpu_gfx.o + amdgpu_gfx.o \ + gfx_v8_0.o + +# add async DMA block +amdgpu-y += \ + sdma_v2_4.o \ + sdma_v3_0.o # add UVD block amdgpu-y += \ - amdgpu_uvd.o + amdgpu_uvd.o \ + uvd_v5_0.o \ + uvd_v6_0.o # add VCE block amdgpu-y += \ - amdgpu_vce.o + amdgpu_vce.o \ + vce_v3_0.o amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 548e0843d95a..61cf5ad78857 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -41,6 +41,7 @@ #ifdef CONFIG_DRM_AMDGPU_CIK #include "cik.h" #endif +#include "vi.h" #include "bif/bif_4_1_d.h" static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); @@ -1154,9 +1155,21 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, static int amdgpu_early_init(struct amdgpu_device *adev) { - int i, r = -EINVAL; + int i, r; switch (adev->asic_type) { + case CHIP_TOPAZ: + case CHIP_TONGA: + case CHIP_CARRIZO: + if (adev->asic_type == CHIP_CARRIZO) + adev->family = AMDGPU_FAMILY_CZ; + else + adev->family = AMDGPU_FAMILY_VI; + + r = vi_set_ip_blocks(adev); + if (r) + return r; + break; #ifdef CONFIG_DRM_AMDGPU_CIK case CHIP_BONAIRE: case CHIP_HAWAII: diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_vi.h b/drivers/gpu/drm/amd/amdgpu/clearstate_vi.h new file mode 100644 index 000000000000..1aab9bef9349 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/clearstate_vi.h @@ -0,0 +1,944 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +static const unsigned int vi_SECT_CONTEXT_def_1[] = +{ + 0x00000000, // DB_RENDER_CONTROL + 0x00000000, // DB_COUNT_CONTROL + 0x00000000, // DB_DEPTH_VIEW + 0x00000000, // DB_RENDER_OVERRIDE + 0x00000000, // DB_RENDER_OVERRIDE2 + 0x00000000, // DB_HTILE_DATA_BASE + 0, // HOLE + 0, // HOLE + 0x00000000, // DB_DEPTH_BOUNDS_MIN + 0x00000000, // DB_DEPTH_BOUNDS_MAX + 0x00000000, // DB_STENCIL_CLEAR + 0x00000000, // DB_DEPTH_CLEAR + 0x00000000, // PA_SC_SCREEN_SCISSOR_TL + 0x40004000, // PA_SC_SCREEN_SCISSOR_BR + 0, // HOLE + 0x00000000, // DB_DEPTH_INFO + 0x00000000, // DB_Z_INFO + 0x00000000, // DB_STENCIL_INFO + 0x00000000, // DB_Z_READ_BASE + 0x00000000, // DB_STENCIL_READ_BASE + 0x00000000, // DB_Z_WRITE_BASE + 0x00000000, // DB_STENCIL_WRITE_BASE + 0x00000000, // DB_DEPTH_SIZE + 0x00000000, // DB_DEPTH_SLICE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // TA_BC_BASE_ADDR + 0x00000000, // TA_BC_BASE_ADDR_HI + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // COHER_DEST_BASE_HI_0 + 0x00000000, // COHER_DEST_BASE_HI_1 + 0x00000000, // COHER_DEST_BASE_HI_2 + 0x00000000, // COHER_DEST_BASE_HI_3 + 0x00000000, // COHER_DEST_BASE_2 + 0x00000000, // COHER_DEST_BASE_3 + 0x00000000, // PA_SC_WINDOW_OFFSET + 0x80000000, // PA_SC_WINDOW_SCISSOR_TL + 0x40004000, // PA_SC_WINDOW_SCISSOR_BR + 0x0000ffff, // PA_SC_CLIPRECT_RULE + 0x00000000, // PA_SC_CLIPRECT_0_TL + 0x40004000, // PA_SC_CLIPRECT_0_BR + 0x00000000, // PA_SC_CLIPRECT_1_TL + 0x40004000, // PA_SC_CLIPRECT_1_BR + 0x00000000, // PA_SC_CLIPRECT_2_TL + 0x40004000, // PA_SC_CLIPRECT_2_BR + 0x00000000, // PA_SC_CLIPRECT_3_TL + 0x40004000, // PA_SC_CLIPRECT_3_BR + 0xaa99aaaa, // PA_SC_EDGERULE + 0x00000000, // PA_SU_HARDWARE_SCREEN_OFFSET + 0xffffffff, // CB_TARGET_MASK + 0xffffffff, // CB_SHADER_MASK + 0x80000000, // PA_SC_GENERIC_SCISSOR_TL + 0x40004000, // PA_SC_GENERIC_SCISSOR_BR + 0x00000000, // COHER_DEST_BASE_0 + 0x00000000, // COHER_DEST_BASE_1 + 0x80000000, // PA_SC_VPORT_SCISSOR_0_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_0_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_1_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_1_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_2_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_2_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_3_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_3_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_4_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_4_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_5_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_5_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_6_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_6_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_7_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_7_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_8_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_8_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_9_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_9_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_10_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_10_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_11_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_11_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_12_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_12_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_13_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_13_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_14_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_14_BR + 0x80000000, // PA_SC_VPORT_SCISSOR_15_TL + 0x40004000, // PA_SC_VPORT_SCISSOR_15_BR + 0x00000000, // PA_SC_VPORT_ZMIN_0 + 0x3f800000, // PA_SC_VPORT_ZMAX_0 + 0x00000000, // PA_SC_VPORT_ZMIN_1 + 0x3f800000, // PA_SC_VPORT_ZMAX_1 + 0x00000000, // PA_SC_VPORT_ZMIN_2 + 0x3f800000, // PA_SC_VPORT_ZMAX_2 + 0x00000000, // PA_SC_VPORT_ZMIN_3 + 0x3f800000, // PA_SC_VPORT_ZMAX_3 + 0x00000000, // PA_SC_VPORT_ZMIN_4 + 0x3f800000, // PA_SC_VPORT_ZMAX_4 + 0x00000000, // PA_SC_VPORT_ZMIN_5 + 0x3f800000, // PA_SC_VPORT_ZMAX_5 + 0x00000000, // PA_SC_VPORT_ZMIN_6 + 0x3f800000, // PA_SC_VPORT_ZMAX_6 + 0x00000000, // PA_SC_VPORT_ZMIN_7 + 0x3f800000, // PA_SC_VPORT_ZMAX_7 + 0x00000000, // PA_SC_VPORT_ZMIN_8 + 0x3f800000, // PA_SC_VPORT_ZMAX_8 + 0x00000000, // PA_SC_VPORT_ZMIN_9 + 0x3f800000, // PA_SC_VPORT_ZMAX_9 + 0x00000000, // PA_SC_VPORT_ZMIN_10 + 0x3f800000, // PA_SC_VPORT_ZMAX_10 + 0x00000000, // PA_SC_VPORT_ZMIN_11 + 0x3f800000, // PA_SC_VPORT_ZMAX_11 + 0x00000000, // PA_SC_VPORT_ZMIN_12 + 0x3f800000, // PA_SC_VPORT_ZMAX_12 + 0x00000000, // PA_SC_VPORT_ZMIN_13 + 0x3f800000, // PA_SC_VPORT_ZMAX_13 + 0x00000000, // PA_SC_VPORT_ZMIN_14 + 0x3f800000, // PA_SC_VPORT_ZMAX_14 + 0x00000000, // PA_SC_VPORT_ZMIN_15 + 0x3f800000, // PA_SC_VPORT_ZMAX_15 +}; +static const unsigned int vi_SECT_CONTEXT_def_2[] = +{ + 0x00000000, // PA_SC_SCREEN_EXTENT_CONTROL + 0, // HOLE + 0x00000000, // CP_PERFMON_CNTX_CNTL + 0x00000000, // CP_RINGID + 0x00000000, // CP_VMID + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0xffffffff, // VGT_MAX_VTX_INDX + 0x00000000, // VGT_MIN_VTX_INDX + 0x00000000, // VGT_INDX_OFFSET + 0x00000000, // VGT_MULTI_PRIM_IB_RESET_INDX + 0, // HOLE + 0x00000000, // CB_BLEND_RED + 0x00000000, // CB_BLEND_GREEN + 0x00000000, // CB_BLEND_BLUE + 0x00000000, // CB_BLEND_ALPHA + 0x00000000, // CB_DCC_CONTROL + 0, // HOLE + 0x00000000, // DB_STENCIL_CONTROL + 0x00000000, // DB_STENCILREFMASK + 0x00000000, // DB_STENCILREFMASK_BF + 0, // HOLE + 0x00000000, // PA_CL_VPORT_XSCALE + 0x00000000, // PA_CL_VPORT_XOFFSET + 0x00000000, // PA_CL_VPORT_YSCALE + 0x00000000, // PA_CL_VPORT_YOFFSET + 0x00000000, // PA_CL_VPORT_ZSCALE + 0x00000000, // PA_CL_VPORT_ZOFFSET + 0x00000000, // PA_CL_VPORT_XSCALE_1 + 0x00000000, // PA_CL_VPORT_XOFFSET_1 + 0x00000000, // PA_CL_VPORT_YSCALE_1 + 0x00000000, // PA_CL_VPORT_YOFFSET_1 + 0x00000000, // PA_CL_VPORT_ZSCALE_1 + 0x00000000, // PA_CL_VPORT_ZOFFSET_1 + 0x00000000, // PA_CL_VPORT_XSCALE_2 + 0x00000000, // PA_CL_VPORT_XOFFSET_2 + 0x00000000, // PA_CL_VPORT_YSCALE_2 + 0x00000000, // PA_CL_VPORT_YOFFSET_2 + 0x00000000, // PA_CL_VPORT_ZSCALE_2 + 0x00000000, // PA_CL_VPORT_ZOFFSET_2 + 0x00000000, // PA_CL_VPORT_XSCALE_3 + 0x00000000, // PA_CL_VPORT_XOFFSET_3 + 0x00000000, // PA_CL_VPORT_YSCALE_3 + 0x00000000, // PA_CL_VPORT_YOFFSET_3 + 0x00000000, // PA_CL_VPORT_ZSCALE_3 + 0x00000000, // PA_CL_VPORT_ZOFFSET_3 + 0x00000000, // PA_CL_VPORT_XSCALE_4 + 0x00000000, // PA_CL_VPORT_XOFFSET_4 + 0x00000000, // PA_CL_VPORT_YSCALE_4 + 0x00000000, // PA_CL_VPORT_YOFFSET_4 + 0x00000000, // PA_CL_VPORT_ZSCALE_4 + 0x00000000, // PA_CL_VPORT_ZOFFSET_4 + 0x00000000, // PA_CL_VPORT_XSCALE_5 + 0x00000000, // PA_CL_VPORT_XOFFSET_5 + 0x00000000, // PA_CL_VPORT_YSCALE_5 + 0x00000000, // PA_CL_VPORT_YOFFSET_5 + 0x00000000, // PA_CL_VPORT_ZSCALE_5 + 0x00000000, // PA_CL_VPORT_ZOFFSET_5 + 0x00000000, // PA_CL_VPORT_XSCALE_6 + 0x00000000, // PA_CL_VPORT_XOFFSET_6 + 0x00000000, // PA_CL_VPORT_YSCALE_6 + 0x00000000, // PA_CL_VPORT_YOFFSET_6 + 0x00000000, // PA_CL_VPORT_ZSCALE_6 + 0x00000000, // PA_CL_VPORT_ZOFFSET_6 + 0x00000000, // PA_CL_VPORT_XSCALE_7 + 0x00000000, // PA_CL_VPORT_XOFFSET_7 + 0x00000000, // PA_CL_VPORT_YSCALE_7 + 0x00000000, // PA_CL_VPORT_YOFFSET_7 + 0x00000000, // PA_CL_VPORT_ZSCALE_7 + 0x00000000, // PA_CL_VPORT_ZOFFSET_7 + 0x00000000, // PA_CL_VPORT_XSCALE_8 + 0x00000000, // PA_CL_VPORT_XOFFSET_8 + 0x00000000, // PA_CL_VPORT_YSCALE_8 + 0x00000000, // PA_CL_VPORT_YOFFSET_8 + 0x00000000, // PA_CL_VPORT_ZSCALE_8 + 0x00000000, // PA_CL_VPORT_ZOFFSET_8 + 0x00000000, // PA_CL_VPORT_XSCALE_9 + 0x00000000, // PA_CL_VPORT_XOFFSET_9 + 0x00000000, // PA_CL_VPORT_YSCALE_9 + 0x00000000, // PA_CL_VPORT_YOFFSET_9 + 0x00000000, // PA_CL_VPORT_ZSCALE_9 + 0x00000000, // PA_CL_VPORT_ZOFFSET_9 + 0x00000000, // PA_CL_VPORT_XSCALE_10 + 0x00000000, // PA_CL_VPORT_XOFFSET_10 + 0x00000000, // PA_CL_VPORT_YSCALE_10 + 0x00000000, // PA_CL_VPORT_YOFFSET_10 + 0x00000000, // PA_CL_VPORT_ZSCALE_10 + 0x00000000, // PA_CL_VPORT_ZOFFSET_10 + 0x00000000, // PA_CL_VPORT_XSCALE_11 + 0x00000000, // PA_CL_VPORT_XOFFSET_11 + 0x00000000, // PA_CL_VPORT_YSCALE_11 + 0x00000000, // PA_CL_VPORT_YOFFSET_11 + 0x00000000, // PA_CL_VPORT_ZSCALE_11 + 0x00000000, // PA_CL_VPORT_ZOFFSET_11 + 0x00000000, // PA_CL_VPORT_XSCALE_12 + 0x00000000, // PA_CL_VPORT_XOFFSET_12 + 0x00000000, // PA_CL_VPORT_YSCALE_12 + 0x00000000, // PA_CL_VPORT_YOFFSET_12 + 0x00000000, // PA_CL_VPORT_ZSCALE_12 + 0x00000000, // PA_CL_VPORT_ZOFFSET_12 + 0x00000000, // PA_CL_VPORT_XSCALE_13 + 0x00000000, // PA_CL_VPORT_XOFFSET_13 + 0x00000000, // PA_CL_VPORT_YSCALE_13 + 0x00000000, // PA_CL_VPORT_YOFFSET_13 + 0x00000000, // PA_CL_VPORT_ZSCALE_13 + 0x00000000, // PA_CL_VPORT_ZOFFSET_13 + 0x00000000, // PA_CL_VPORT_XSCALE_14 + 0x00000000, // PA_CL_VPORT_XOFFSET_14 + 0x00000000, // PA_CL_VPORT_YSCALE_14 + 0x00000000, // PA_CL_VPORT_YOFFSET_14 + 0x00000000, // PA_CL_VPORT_ZSCALE_14 + 0x00000000, // PA_CL_VPORT_ZOFFSET_14 + 0x00000000, // PA_CL_VPORT_XSCALE_15 + 0x00000000, // PA_CL_VPORT_XOFFSET_15 + 0x00000000, // PA_CL_VPORT_YSCALE_15 + 0x00000000, // PA_CL_VPORT_YOFFSET_15 + 0x00000000, // PA_CL_VPORT_ZSCALE_15 + 0x00000000, // PA_CL_VPORT_ZOFFSET_15 + 0x00000000, // PA_CL_UCP_0_X + 0x00000000, // PA_CL_UCP_0_Y + 0x00000000, // PA_CL_UCP_0_Z + 0x00000000, // PA_CL_UCP_0_W + 0x00000000, // PA_CL_UCP_1_X + 0x00000000, // PA_CL_UCP_1_Y + 0x00000000, // PA_CL_UCP_1_Z + 0x00000000, // PA_CL_UCP_1_W + 0x00000000, // PA_CL_UCP_2_X + 0x00000000, // PA_CL_UCP_2_Y + 0x00000000, // PA_CL_UCP_2_Z + 0x00000000, // PA_CL_UCP_2_W + 0x00000000, // PA_CL_UCP_3_X + 0x00000000, // PA_CL_UCP_3_Y + 0x00000000, // PA_CL_UCP_3_Z + 0x00000000, // PA_CL_UCP_3_W + 0x00000000, // PA_CL_UCP_4_X + 0x00000000, // PA_CL_UCP_4_Y + 0x00000000, // PA_CL_UCP_4_Z + 0x00000000, // PA_CL_UCP_4_W + 0x00000000, // PA_CL_UCP_5_X + 0x00000000, // PA_CL_UCP_5_Y + 0x00000000, // PA_CL_UCP_5_Z + 0x00000000, // PA_CL_UCP_5_W + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // SPI_PS_INPUT_CNTL_0 + 0x00000000, // SPI_PS_INPUT_CNTL_1 + 0x00000000, // SPI_PS_INPUT_CNTL_2 + 0x00000000, // SPI_PS_INPUT_CNTL_3 + 0x00000000, // SPI_PS_INPUT_CNTL_4 + 0x00000000, // SPI_PS_INPUT_CNTL_5 + 0x00000000, // SPI_PS_INPUT_CNTL_6 + 0x00000000, // SPI_PS_INPUT_CNTL_7 + 0x00000000, // SPI_PS_INPUT_CNTL_8 + 0x00000000, // SPI_PS_INPUT_CNTL_9 + 0x00000000, // SPI_PS_INPUT_CNTL_10 + 0x00000000, // SPI_PS_INPUT_CNTL_11 + 0x00000000, // SPI_PS_INPUT_CNTL_12 + 0x00000000, // SPI_PS_INPUT_CNTL_13 + 0x00000000, // SPI_PS_INPUT_CNTL_14 + 0x00000000, // SPI_PS_INPUT_CNTL_15 + 0x00000000, // SPI_PS_INPUT_CNTL_16 + 0x00000000, // SPI_PS_INPUT_CNTL_17 + 0x00000000, // SPI_PS_INPUT_CNTL_18 + 0x00000000, // SPI_PS_INPUT_CNTL_19 + 0x00000000, // SPI_PS_INPUT_CNTL_20 + 0x00000000, // SPI_PS_INPUT_CNTL_21 + 0x00000000, // SPI_PS_INPUT_CNTL_22 + 0x00000000, // SPI_PS_INPUT_CNTL_23 + 0x00000000, // SPI_PS_INPUT_CNTL_24 + 0x00000000, // SPI_PS_INPUT_CNTL_25 + 0x00000000, // SPI_PS_INPUT_CNTL_26 + 0x00000000, // SPI_PS_INPUT_CNTL_27 + 0x00000000, // SPI_PS_INPUT_CNTL_28 + 0x00000000, // SPI_PS_INPUT_CNTL_29 + 0x00000000, // SPI_PS_INPUT_CNTL_30 + 0x00000000, // SPI_PS_INPUT_CNTL_31 + 0x00000000, // SPI_VS_OUT_CONFIG + 0, // HOLE + 0x00000000, // SPI_PS_INPUT_ENA + 0x00000000, // SPI_PS_INPUT_ADDR + 0x00000000, // SPI_INTERP_CONTROL_0 + 0x00000002, // SPI_PS_IN_CONTROL + 0, // HOLE + 0x00000000, // SPI_BARYC_CNTL + 0, // HOLE + 0x00000000, // SPI_TMPRING_SIZE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // SPI_SHADER_POS_FORMAT + 0x00000000, // SPI_SHADER_Z_FORMAT + 0x00000000, // SPI_SHADER_COL_FORMAT + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // CB_BLEND0_CONTROL + 0x00000000, // CB_BLEND1_CONTROL + 0x00000000, // CB_BLEND2_CONTROL + 0x00000000, // CB_BLEND3_CONTROL + 0x00000000, // CB_BLEND4_CONTROL + 0x00000000, // CB_BLEND5_CONTROL + 0x00000000, // CB_BLEND6_CONTROL + 0x00000000, // CB_BLEND7_CONTROL +}; +static const unsigned int vi_SECT_CONTEXT_def_3[] = +{ + 0x00000000, // PA_CL_POINT_X_RAD + 0x00000000, // PA_CL_POINT_Y_RAD + 0x00000000, // PA_CL_POINT_SIZE + 0x00000000, // PA_CL_POINT_CULL_RAD + 0x00000000, // VGT_DMA_BASE_HI + 0x00000000, // VGT_DMA_BASE +}; +static const unsigned int vi_SECT_CONTEXT_def_4[] = +{ + 0x00000000, // DB_DEPTH_CONTROL + 0x00000000, // DB_EQAA + 0x00000000, // CB_COLOR_CONTROL + 0x00000000, // DB_SHADER_CONTROL + 0x00090000, // PA_CL_CLIP_CNTL + 0x00000004, // PA_SU_SC_MODE_CNTL + 0x00000000, // PA_CL_VTE_CNTL + 0x00000000, // PA_CL_VS_OUT_CNTL + 0x00000000, // PA_CL_NANINF_CNTL + 0x00000000, // PA_SU_LINE_STIPPLE_CNTL + 0x00000000, // PA_SU_LINE_STIPPLE_SCALE + 0x00000000, // PA_SU_PRIM_FILTER_CNTL + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // PA_SU_POINT_SIZE + 0x00000000, // PA_SU_POINT_MINMAX + 0x00000000, // PA_SU_LINE_CNTL + 0x00000000, // PA_SC_LINE_STIPPLE + 0x00000000, // VGT_OUTPUT_PATH_CNTL + 0x00000000, // VGT_HOS_CNTL + 0x00000000, // VGT_HOS_MAX_TESS_LEVEL + 0x00000000, // VGT_HOS_MIN_TESS_LEVEL + 0x00000000, // VGT_HOS_REUSE_DEPTH + 0x00000000, // VGT_GROUP_PRIM_TYPE + 0x00000000, // VGT_GROUP_FIRST_DECR + 0x00000000, // VGT_GROUP_DECR + 0x00000000, // VGT_GROUP_VECT_0_CNTL + 0x00000000, // VGT_GROUP_VECT_1_CNTL + 0x00000000, // VGT_GROUP_VECT_0_FMT_CNTL + 0x00000000, // VGT_GROUP_VECT_1_FMT_CNTL + 0x00000000, // VGT_GS_MODE + 0x00000000, // VGT_GS_ONCHIP_CNTL + 0x00000000, // PA_SC_MODE_CNTL_0 + 0x00000000, // PA_SC_MODE_CNTL_1 + 0x00000000, // VGT_ENHANCE + 0x00000100, // VGT_GS_PER_ES + 0x00000080, // VGT_ES_PER_GS + 0x00000002, // VGT_GS_PER_VS + 0x00000000, // VGT_GSVS_RING_OFFSET_1 + 0x00000000, // VGT_GSVS_RING_OFFSET_2 + 0x00000000, // VGT_GSVS_RING_OFFSET_3 + 0x00000000, // VGT_GS_OUT_PRIM_TYPE + 0x00000000, // IA_ENHANCE +}; +static const unsigned int vi_SECT_CONTEXT_def_5[] = +{ + 0x00000000, // WD_ENHANCE + 0x00000000, // VGT_PRIMITIVEID_EN +}; +static const unsigned int vi_SECT_CONTEXT_def_6[] = +{ + 0x00000000, // VGT_PRIMITIVEID_RESET +}; +static const unsigned int vi_SECT_CONTEXT_def_7[] = +{ + 0x00000000, // VGT_MULTI_PRIM_IB_RESET_EN + 0, // HOLE + 0, // HOLE + 0x00000000, // VGT_INSTANCE_STEP_RATE_0 + 0x00000000, // VGT_INSTANCE_STEP_RATE_1 + 0x000000ff, // IA_MULTI_VGT_PARAM + 0x00000000, // VGT_ESGS_RING_ITEMSIZE + 0x00000000, // VGT_GSVS_RING_ITEMSIZE + 0x00000000, // VGT_REUSE_OFF + 0x00000000, // VGT_VTX_CNT_EN + 0x00000000, // DB_HTILE_SURFACE + 0x00000000, // DB_SRESULTS_COMPARE_STATE0 + 0x00000000, // DB_SRESULTS_COMPARE_STATE1 + 0x00000000, // DB_PRELOAD_CONTROL + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_0 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_0 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_0 + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_1 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_1 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_1 + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_2 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_2 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_2 + 0x00000000, // VGT_STRMOUT_BUFFER_SIZE_3 + 0x00000000, // VGT_STRMOUT_VTX_STRIDE_3 + 0, // HOLE + 0x00000000, // VGT_STRMOUT_BUFFER_OFFSET_3 + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_OFFSET + 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE + 0x00000000, // VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE + 0, // HOLE + 0x00000000, // VGT_GS_MAX_VERT_OUT + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // VGT_TESS_DISTRIBUTION + 0x00000000, // VGT_SHADER_STAGES_EN + 0x00000000, // VGT_LS_HS_CONFIG + 0x00000000, // VGT_GS_VERT_ITEMSIZE + 0x00000000, // VGT_GS_VERT_ITEMSIZE_1 + 0x00000000, // VGT_GS_VERT_ITEMSIZE_2 + 0x00000000, // VGT_GS_VERT_ITEMSIZE_3 + 0x00000000, // VGT_TF_PARAM + 0x00000000, // DB_ALPHA_TO_MASK + 0x00000000, // VGT_DISPATCH_DRAW_INDEX + 0x00000000, // PA_SU_POLY_OFFSET_DB_FMT_CNTL + 0x00000000, // PA_SU_POLY_OFFSET_CLAMP + 0x00000000, // PA_SU_POLY_OFFSET_FRONT_SCALE + 0x00000000, // PA_SU_POLY_OFFSET_FRONT_OFFSET + 0x00000000, // PA_SU_POLY_OFFSET_BACK_SCALE + 0x00000000, // PA_SU_POLY_OFFSET_BACK_OFFSET + 0x00000000, // VGT_GS_INSTANCE_CNT + 0x00000000, // VGT_STRMOUT_CONFIG + 0x00000000, // VGT_STRMOUT_BUFFER_CONFIG + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x00000000, // PA_SC_CENTROID_PRIORITY_0 + 0x00000000, // PA_SC_CENTROID_PRIORITY_1 + 0x00001000, // PA_SC_LINE_CNTL + 0x00000000, // PA_SC_AA_CONFIG + 0x00000005, // PA_SU_VTX_CNTL + 0x3f800000, // PA_CL_GB_VERT_CLIP_ADJ + 0x3f800000, // PA_CL_GB_VERT_DISC_ADJ + 0x3f800000, // PA_CL_GB_HORZ_CLIP_ADJ + 0x3f800000, // PA_CL_GB_HORZ_DISC_ADJ + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 + 0x00000000, // PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 + 0xffffffff, // PA_SC_AA_MASK_X0Y0_X1Y0 + 0xffffffff, // PA_SC_AA_MASK_X0Y1_X1Y1 + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0, // HOLE + 0x0000001e, // VGT_VERTEX_REUSE_BLOCK_CNTL + 0x00000020, // VGT_OUT_DEALLOC_CNTL + 0x00000000, // CB_COLOR0_BASE + 0x00000000, // CB_COLOR0_PITCH + 0x00000000, // CB_COLOR0_SLICE + 0x00000000, // CB_COLOR0_VIEW + 0x00000000, // CB_COLOR0_INFO + 0x00000000, // CB_COLOR0_ATTRIB + 0x00000000, // CB_COLOR0_DCC_CONTROL + 0x00000000, // CB_COLOR0_CMASK + 0x00000000, // CB_COLOR0_CMASK_SLICE + 0x00000000, // CB_COLOR0_FMASK + 0x00000000, // CB_COLOR0_FMASK_SLICE + 0x00000000, // CB_COLOR0_CLEAR_WORD0 + 0x00000000, // CB_COLOR0_CLEAR_WORD1 + 0x00000000, // CB_COLOR0_DCC_BASE + 0, // HOLE + 0x00000000, // CB_COLOR1_BASE + 0x00000000, // CB_COLOR1_PITCH + 0x00000000, // CB_COLOR1_SLICE + 0x00000000, // CB_COLOR1_VIEW + 0x00000000, // CB_COLOR1_INFO + 0x00000000, // CB_COLOR1_ATTRIB + 0x00000000, // CB_COLOR1_DCC_CONTROL + 0x00000000, // CB_COLOR1_CMASK + 0x00000000, // CB_COLOR1_CMASK_SLICE + 0x00000000, // CB_COLOR1_FMASK + 0x00000000, // CB_COLOR1_FMASK_SLICE + 0x00000000, // CB_COLOR1_CLEAR_WORD0 + 0x00000000, // CB_COLOR1_CLEAR_WORD1 + 0x00000000, // CB_COLOR1_DCC_BASE + 0, // HOLE + 0x00000000, // CB_COLOR2_BASE + 0x00000000, // CB_COLOR2_PITCH + 0x00000000, // CB_COLOR2_SLICE + 0x00000000, // CB_COLOR2_VIEW + 0x00000000, // CB_COLOR2_INFO + 0x00000000, // CB_COLOR2_ATTRIB + 0x00000000, // CB_COLOR2_DCC_CONTROL + 0x00000000, // CB_COLOR2_CMASK + 0x00000000, // CB_COLOR2_CMASK_SLICE + 0x00000000, // CB_COLOR2_FMASK + 0x00000000, // CB_COLOR2_FMASK_SLICE + 0x00000000, // CB_COLOR2_CLEAR_WORD0 + 0x00000000, // CB_COLOR2_CLEAR_WORD1 + 0x00000000, // CB_COLOR2_DCC_BASE + 0, // HOLE + 0x00000000, // CB_COLOR3_BASE + 0x00000000, // CB_COLOR3_PITCH + 0x00000000, // CB_COLOR3_SLICE + 0x00000000, // CB_COLOR3_VIEW + 0x00000000, // CB_COLOR3_INFO + 0x00000000, // CB_COLOR3_ATTRIB + 0x00000000, // CB_COLOR3_DCC_CONTROL + 0x00000000, // CB_COLOR3_CMASK + 0x00000000, // CB_COLOR3_CMASK_SLICE + 0x00000000, // CB_COLOR3_FMASK + 0x00000000, // CB_COLOR3_FMASK_SLICE + 0x00000000, // CB_COLOR3_CLEAR_WORD0 + 0x00000000, // CB_COLOR3_CLEAR_WORD1 + 0x00000000, // CB_COLOR3_DCC_BASE + 0, // HOLE + 0x00000000, // CB_COLOR4_BASE + 0x00000000, // CB_COLOR4_PITCH + 0x00000000, // CB_COLOR4_SLICE + 0x00000000, // CB_COLOR4_VIEW + 0x00000000, // CB_COLOR4_INFO + 0x00000000, // CB_COLOR4_ATTRIB + 0x00000000, // CB_COLOR4_DCC_CONTROL + 0x00000000, // CB_COLOR4_CMASK + 0x00000000, // CB_COLOR4_CMASK_SLICE + 0x00000000, // CB_COLOR4_FMASK + 0x00000000, // CB_COLOR4_FMASK_SLICE + 0x00000000, // CB_COLOR4_CLEAR_WORD0 + 0x00000000, // CB_COLOR4_CLEAR_WORD1 + 0x00000000, // CB_COLOR4_DCC_BASE + 0, // HOLE + 0x00000000, // CB_COLOR5_BASE + 0x00000000, // CB_COLOR5_PITCH + 0x00000000, // CB_COLOR5_SLICE + 0x00000000, // CB_COLOR5_VIEW + 0x00000000, // CB_COLOR5_INFO + 0x00000000, // CB_COLOR5_ATTRIB + 0x00000000, // CB_COLOR5_DCC_CONTROL + 0x00000000, // CB_COLOR5_CMASK + 0x00000000, // CB_COLOR5_CMASK_SLICE + 0x00000000, // CB_COLOR5_FMASK + 0x00000000, // CB_COLOR5_FMASK_SLICE + 0x00000000, // CB_COLOR5_CLEAR_WORD0 + 0x00000000, // CB_COLOR5_CLEAR_WORD1 + 0x00000000, // CB_COLOR5_DCC_BASE + 0, // HOLE + 0x00000000, // CB_COLOR6_BASE + 0x00000000, // CB_COLOR6_PITCH + 0x00000000, // CB_COLOR6_SLICE + 0x00000000, // CB_COLOR6_VIEW + 0x00000000, // CB_COLOR6_INFO + 0x00000000, // CB_COLOR6_ATTRIB + 0x00000000, // CB_COLOR6_DCC_CONTROL + 0x00000000, // CB_COLOR6_CMASK + 0x00000000, // CB_COLOR6_CMASK_SLICE + 0x00000000, // CB_COLOR6_FMASK + 0x00000000, // CB_COLOR6_FMASK_SLICE + 0x00000000, // CB_COLOR6_CLEAR_WORD0 + 0x00000000, // CB_COLOR6_CLEAR_WORD1 + 0x00000000, // CB_COLOR6_DCC_BASE + 0, // HOLE + 0x00000000, // CB_COLOR7_BASE + 0x00000000, // CB_COLOR7_PITCH + 0x00000000, // CB_COLOR7_SLICE + 0x00000000, // CB_COLOR7_VIEW + 0x00000000, // CB_COLOR7_INFO + 0x00000000, // CB_COLOR7_ATTRIB + 0x00000000, // CB_COLOR7_DCC_CONTROL + 0x00000000, // CB_COLOR7_CMASK + 0x00000000, // CB_COLOR7_CMASK_SLICE + 0x00000000, // CB_COLOR7_FMASK + 0x00000000, // CB_COLOR7_FMASK_SLICE + 0x00000000, // CB_COLOR7_CLEAR_WORD0 + 0x00000000, // CB_COLOR7_CLEAR_WORD1 +}; +static const struct cs_extent_def vi_SECT_CONTEXT_defs[] = +{ + {vi_SECT_CONTEXT_def_1, 0x0000a000, 212 }, + {vi_SECT_CONTEXT_def_2, 0x0000a0d6, 274 }, + {vi_SECT_CONTEXT_def_3, 0x0000a1f5, 6 }, + {vi_SECT_CONTEXT_def_4, 0x0000a200, 157 }, + {vi_SECT_CONTEXT_def_5, 0x0000a2a0, 2 }, + {vi_SECT_CONTEXT_def_6, 0x0000a2a3, 1 }, + {vi_SECT_CONTEXT_def_7, 0x0000a2a5, 233 }, + { 0, 0, 0 } +}; +static const struct cs_section_def vi_cs_data[] = { + { vi_SECT_CONTEXT_defs, SECT_CONTEXT }, + { 0, SECT_NONE } +}; diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c new file mode 100644 index 000000000000..b5c8485d8a58 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -0,0 +1,1712 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_pm.h" +#include "amdgpu_atombios.h" +#include "vid.h" +#include "vi_dpm.h" +#include "amdgpu_dpm.h" +#include "cz_dpm.h" +#include "cz_ppsmc.h" +#include "atom.h" + +#include "smu/smu_8_0_d.h" +#include "smu/smu_8_0_sh_mask.h" +#include "gca/gfx_8_0_d.h" +#include "gca/gfx_8_0_sh_mask.h" +#include "gmc/gmc_8_1_d.h" +#include "bif/bif_5_1_d.h" +#include "gfx_v8_0.h" + +static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps) +{ + struct cz_ps *ps = rps->ps_priv; + + return ps; +} + +static struct cz_power_info *cz_get_pi(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = adev->pm.dpm.priv; + + return pi; +} + +static uint16_t cz_convert_8bit_index_to_voltage(struct amdgpu_device *adev, + uint16_t voltage) +{ + uint16_t tmp = 6200 - voltage * 25; + + return tmp; +} + +static void cz_construct_max_power_limits_table(struct amdgpu_device *adev, + struct amdgpu_clock_and_voltage_limits *table) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_clock_voltage_dependency_table *dep_table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + + if (dep_table->count > 0) { + table->sclk = dep_table->entries[dep_table->count - 1].clk; + table->vddc = cz_convert_8bit_index_to_voltage(adev, + dep_table->entries[dep_table->count - 1].v); + } + + table->mclk = pi->sys_info.nbp_memory_clock[0]; + +} + +union igp_info { + struct _ATOM_INTEGRATED_SYSTEM_INFO info; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9; +}; + +static int cz_parse_sys_info_table(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); + union igp_info *igp_info; + u8 frev, crev; + u16 data_offset; + int i = 0; + + if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) { + igp_info = (union igp_info *)(mode_info->atom_context->bios + + data_offset); + + if (crev != 9) { + DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); + return -EINVAL; + } + pi->sys_info.bootup_sclk = + le32_to_cpu(igp_info->info_9.ulBootUpEngineClock); + pi->sys_info.bootup_uma_clk = + le32_to_cpu(igp_info->info_9.ulBootUpUMAClock); + pi->sys_info.dentist_vco_freq = + le32_to_cpu(igp_info->info_9.ulDentistVCOFreq); + pi->sys_info.bootup_nb_voltage_index = + le16_to_cpu(igp_info->info_9.usBootUpNBVoltage); + + if (igp_info->info_9.ucHtcTmpLmt == 0) + pi->sys_info.htc_tmp_lmt = 203; + else + pi->sys_info.htc_tmp_lmt = igp_info->info_9.ucHtcTmpLmt; + + if (igp_info->info_9.ucHtcHystLmt == 0) + pi->sys_info.htc_hyst_lmt = 5; + else + pi->sys_info.htc_hyst_lmt = igp_info->info_9.ucHtcHystLmt; + + if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { + DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); + return -EINVAL; + } + + if (le32_to_cpu(igp_info->info_9.ulSystemConfig) & (1 << 3) && + pi->enable_nb_ps_policy) + pi->sys_info.nb_dpm_enable = true; + else + pi->sys_info.nb_dpm_enable = false; + + for (i = 0; i < CZ_NUM_NBPSTATES; i++) { + if (i < CZ_NUM_NBPMEMORY_CLOCK) + pi->sys_info.nbp_memory_clock[i] = + le32_to_cpu(igp_info->info_9.ulNbpStateMemclkFreq[i]); + pi->sys_info.nbp_n_clock[i] = + le32_to_cpu(igp_info->info_9.ulNbpStateNClkFreq[i]); + } + + for (i = 0; i < CZ_MAX_DISPLAY_CLOCK_LEVEL; i++) + pi->sys_info.display_clock[i] = + le32_to_cpu(igp_info->info_9.sDispClkVoltageMapping[i].ulMaximumSupportedCLK); + + for (i = 0; i < CZ_NUM_NBPSTATES; i++) + pi->sys_info.nbp_voltage_index[i] = + le32_to_cpu(igp_info->info_9.usNBPStateVoltage[i]); + + if (le32_to_cpu(igp_info->info_9.ulGPUCapInfo) & + SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) + pi->caps_enable_dfs_bypass = true; + + pi->sys_info.uma_channel_number = + igp_info->info_9.ucUMAChannelNumber; + + cz_construct_max_power_limits_table(adev, + &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); + } + + return 0; +} + +static void cz_patch_voltage_values(struct amdgpu_device *adev) +{ + int i; + struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table = + &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; + struct amdgpu_vce_clock_voltage_dependency_table *vce_table = + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + struct amdgpu_clock_voltage_dependency_table *acp_table = + &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; + + if (uvd_table->count) { + for (i = 0; i < uvd_table->count; i++) + uvd_table->entries[i].v = + cz_convert_8bit_index_to_voltage(adev, + uvd_table->entries[i].v); + } + + if (vce_table->count) { + for (i = 0; i < vce_table->count; i++) + vce_table->entries[i].v = + cz_convert_8bit_index_to_voltage(adev, + vce_table->entries[i].v); + } + + if (acp_table->count) { + for (i = 0; i < acp_table->count; i++) + acp_table->entries[i].v = + cz_convert_8bit_index_to_voltage(adev, + acp_table->entries[i].v); + } + +} + +static void cz_construct_boot_state(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + + pi->boot_pl.sclk = pi->sys_info.bootup_sclk; + pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; + pi->boot_pl.ds_divider_index = 0; + pi->boot_pl.ss_divider_index = 0; + pi->boot_pl.allow_gnb_slow = 1; + pi->boot_pl.force_nbp_state = 0; + pi->boot_pl.display_wm = 0; + pi->boot_pl.vce_wm = 0; + +} + +static void cz_patch_boot_state(struct amdgpu_device *adev, + struct cz_ps *ps) +{ + struct cz_power_info *pi = cz_get_pi(adev); + + ps->num_levels = 1; + ps->levels[0] = pi->boot_pl; +} + +union pplib_clock_info { + struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; + struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; + struct _ATOM_PPLIB_CZ_CLOCK_INFO carrizo; +}; + +static void cz_parse_pplib_clock_info(struct amdgpu_device *adev, + struct amdgpu_ps *rps, int index, + union pplib_clock_info *clock_info) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct cz_ps *ps = cz_get_ps(rps); + struct cz_pl *pl = &ps->levels[index]; + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + + pl->sclk = table->entries[clock_info->carrizo.index].clk; + pl->vddc_index = table->entries[clock_info->carrizo.index].v; + + ps->num_levels = index + 1; + + if (pi->caps_sclk_ds) { + pl->ds_divider_index = 5; + pl->ss_divider_index = 5; + } + +} + +static void cz_parse_pplib_non_clock_info(struct amdgpu_device *adev, + struct amdgpu_ps *rps, + struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, + u8 table_rev) +{ + struct cz_ps *ps = cz_get_ps(rps); + + rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); + rps->class = le16_to_cpu(non_clock_info->usClassification); + rps->class2 = le16_to_cpu(non_clock_info->usClassification2); + + if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { + rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); + rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); + } else { + rps->vclk = 0; + rps->dclk = 0; + } + + if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { + adev->pm.dpm.boot_ps = rps; + cz_patch_boot_state(adev, ps); + } + if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) + adev->pm.dpm.uvd_ps = rps; + +} + +union power_info { + struct _ATOM_PPLIB_POWERPLAYTABLE pplib; + struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; + struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; + struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4; + struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5; +}; + +union pplib_power_state { + struct _ATOM_PPLIB_STATE v1; + struct _ATOM_PPLIB_STATE_V2 v2; +}; + +static int cz_parse_power_table(struct amdgpu_device *adev) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; + union pplib_power_state *power_state; + int i, j, k, non_clock_array_index, clock_array_index; + union pplib_clock_info *clock_info; + struct _StateArray *state_array; + struct _ClockInfoArray *clock_info_array; + struct _NonClockInfoArray *non_clock_info_array; + union power_info *power_info; + int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); + u16 data_offset; + u8 frev, crev; + u8 *power_state_offset; + struct cz_ps *ps; + + if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) + return -EINVAL; + power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); + + state_array = (struct _StateArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usStateArrayOffset)); + clock_info_array = (struct _ClockInfoArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); + non_clock_info_array = (struct _NonClockInfoArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); + + adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) * + state_array->ucNumEntries, GFP_KERNEL); + + if (!adev->pm.dpm.ps) + return -ENOMEM; + + power_state_offset = (u8 *)state_array->states; + adev->pm.dpm.platform_caps = + le32_to_cpu(power_info->pplib.ulPlatformCaps); + adev->pm.dpm.backbias_response_time = + le16_to_cpu(power_info->pplib.usBackbiasTime); + adev->pm.dpm.voltage_response_time = + le16_to_cpu(power_info->pplib.usVoltageTime); + + for (i = 0; i < state_array->ucNumEntries; i++) { + power_state = (union pplib_power_state *)power_state_offset; + non_clock_array_index = power_state->v2.nonClockInfoIndex; + non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) + &non_clock_info_array->nonClockInfo[non_clock_array_index]; + + ps = kzalloc(sizeof(struct cz_ps), GFP_KERNEL); + if (ps == NULL) { + kfree(adev->pm.dpm.ps); + return -ENOMEM; + } + + adev->pm.dpm.ps[i].ps_priv = ps; + k = 0; + for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { + clock_array_index = power_state->v2.clockInfoIndex[j]; + if (clock_array_index >= clock_info_array->ucNumEntries) + continue; + if (k >= CZ_MAX_HARDWARE_POWERLEVELS) + break; + clock_info = (union pplib_clock_info *) + &clock_info_array->clockInfo[clock_array_index * + clock_info_array->ucEntrySize]; + cz_parse_pplib_clock_info(adev, &adev->pm.dpm.ps[i], + k, clock_info); + k++; + } + cz_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], + non_clock_info, + non_clock_info_array->ucEntrySize); + power_state_offset += 2 + power_state->v2.ucNumDPMLevels; + } + adev->pm.dpm.num_ps = state_array->ucNumEntries; + + return 0; +} + +static int cz_process_firmware_header(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + u32 tmp; + int ret; + + ret = cz_read_smc_sram_dword(adev, SMU8_FIRMWARE_HEADER_LOCATION + + offsetof(struct SMU8_Firmware_Header, + DpmTable), + &tmp, pi->sram_end); + + if (ret == 0) + pi->dpm_table_start = tmp; + + return ret; +} + +static int cz_dpm_init(struct amdgpu_device *adev) +{ + struct cz_power_info *pi; + int ret, i; + + pi = kzalloc(sizeof(struct cz_power_info), GFP_KERNEL); + if (NULL == pi) + return -ENOMEM; + + adev->pm.dpm.priv = pi; + + ret = amdgpu_get_platform_caps(adev); + if (ret) + return ret; + + ret = amdgpu_parse_extended_power_table(adev); + if (ret) + return ret; + + pi->sram_end = SMC_RAM_END; + + /* set up DPM defaults */ + for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) + pi->active_target[i] = CZ_AT_DFLT; + + pi->mgcg_cgtt_local0 = 0x0; + pi->mgcg_cgtt_local1 = 0x0; + pi->clock_slow_down_step = 25000; + pi->skip_clock_slow_down = 1; + pi->enable_nb_ps_policy = 1; + pi->caps_power_containment = true; + pi->caps_cac = true; + pi->didt_enabled = false; + if (pi->didt_enabled) { + pi->caps_sq_ramping = true; + pi->caps_db_ramping = true; + pi->caps_td_ramping = true; + pi->caps_tcp_ramping = true; + } + pi->caps_sclk_ds = true; + pi->voting_clients = 0x00c00033; + pi->auto_thermal_throttling_enabled = true; + pi->bapm_enabled = false; + pi->disable_nb_ps3_in_battery = false; + pi->voltage_drop_threshold = 0; + pi->caps_sclk_throttle_low_notification = false; + pi->gfx_pg_threshold = 500; + pi->caps_fps = true; + /* uvd */ + pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false; + pi->caps_uvd_dpm = true; + /* vce */ + pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false; + pi->caps_vce_dpm = true; + /* acp */ + pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false; + pi->caps_acp_dpm = true; + + pi->caps_stable_power_state = false; + pi->nb_dpm_enabled_by_driver = true; + pi->nb_dpm_enabled = false; + pi->caps_voltage_island = false; + /* flags which indicate need to upload pptable */ + pi->need_pptable_upload = true; + + ret = cz_parse_sys_info_table(adev); + if (ret) + return ret; + + cz_patch_voltage_values(adev); + cz_construct_boot_state(adev); + + ret = cz_parse_power_table(adev); + if (ret) + return ret; + + ret = cz_process_firmware_header(adev); + if (ret) + return ret; + + pi->dpm_enabled = true; + + return 0; +} + +static void cz_dpm_fini(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->pm.dpm.num_ps; i++) + kfree(adev->pm.dpm.ps[i].ps_priv); + + kfree(adev->pm.dpm.ps); + kfree(adev->pm.dpm.priv); + amdgpu_free_extended_power_table(adev); +} + +static void +cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, + struct seq_file *m) +{ + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + u32 current_index = + (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >> + TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT; + u32 sclk, tmp; + u16 vddc; + + if (current_index >= NUM_SCLK_LEVELS) { + seq_printf(m, "invalid dpm profile %d\n", current_index); + } else { + sclk = table->entries[current_index].clk; + tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) & + SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> + SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT; + vddc = cz_convert_8bit_index_to_voltage(adev, (u16)tmp); + seq_printf(m, "power level %d sclk: %u vddc: %u\n", + current_index, sclk, vddc); + } +} + +static void cz_dpm_print_power_state(struct amdgpu_device *adev, + struct amdgpu_ps *rps) +{ + int i; + struct cz_ps *ps = cz_get_ps(rps); + + amdgpu_dpm_print_class_info(rps->class, rps->class2); + amdgpu_dpm_print_cap_info(rps->caps); + + DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); + for (i = 0; i < ps->num_levels; i++) { + struct cz_pl *pl = &ps->levels[i]; + + DRM_INFO("\t\tpower level %d sclk: %u vddc: %u\n", + i, pl->sclk, + cz_convert_8bit_index_to_voltage(adev, pl->vddc_index)); + } + + amdgpu_dpm_print_ps_status(adev, rps); +} + +static void cz_dpm_set_funcs(struct amdgpu_device *adev); + +static int cz_dpm_early_init(struct amdgpu_device *adev) +{ + cz_dpm_set_funcs(adev); + + return 0; +} + +static int cz_dpm_sw_init(struct amdgpu_device *adev) +{ + int ret = 0; + /* fix me to add thermal support TODO */ + + /* default to balanced state */ + adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; + adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; + adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO; + adev->pm.default_sclk = adev->clock.default_sclk; + adev->pm.default_mclk = adev->clock.default_mclk; + adev->pm.current_sclk = adev->clock.default_sclk; + adev->pm.current_mclk = adev->clock.default_mclk; + adev->pm.int_thermal_type = THERMAL_TYPE_NONE; + + if (amdgpu_dpm == 0) + return 0; + + mutex_lock(&adev->pm.mutex); + ret = cz_dpm_init(adev); + if (ret) + goto dpm_init_failed; + + adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; + if (amdgpu_dpm == 1) + amdgpu_pm_print_power_states(adev); + + ret = amdgpu_pm_sysfs_init(adev); + if (ret) + goto dpm_init_failed; + + mutex_unlock(&adev->pm.mutex); + DRM_INFO("amdgpu: dpm initialized\n"); + + return 0; + +dpm_init_failed: + cz_dpm_fini(adev); + mutex_unlock(&adev->pm.mutex); + DRM_ERROR("amdgpu: dpm initialization failed\n"); + + return ret; +} + +static int cz_dpm_sw_fini(struct amdgpu_device *adev) +{ + mutex_lock(&adev->pm.mutex); + amdgpu_pm_sysfs_fini(adev); + cz_dpm_fini(adev); + mutex_unlock(&adev->pm.mutex); + + return 0; +} + +static void cz_reset_ap_mask(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + + pi->active_process_mask = 0; + +} + +static int cz_dpm_download_pptable_from_smu(struct amdgpu_device *adev, + void **table) +{ + int ret = 0; + + ret = cz_smu_download_pptable(adev, table); + + return ret; +} + +static int cz_dpm_upload_pptable_to_smu(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct SMU8_Fusion_ClkTable *clock_table; + struct atom_clock_dividers dividers; + void *table = NULL; + uint8_t i = 0; + int ret = 0; + + struct amdgpu_clock_voltage_dependency_table *vddc_table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + struct amdgpu_clock_voltage_dependency_table *vddgfx_table = + &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk; + struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table = + &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; + struct amdgpu_vce_clock_voltage_dependency_table *vce_table = + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + struct amdgpu_clock_voltage_dependency_table *acp_table = + &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; + + if (!pi->need_pptable_upload) + return 0; + + ret = cz_dpm_download_pptable_from_smu(adev, &table); + if (ret) { + DRM_ERROR("amdgpu: Failed to get power play table from SMU!\n"); + return -EINVAL; + } + + clock_table = (struct SMU8_Fusion_ClkTable *)table; + /* patch clock table */ + if (vddc_table->count > CZ_MAX_HARDWARE_POWERLEVELS || + vddgfx_table->count > CZ_MAX_HARDWARE_POWERLEVELS || + uvd_table->count > CZ_MAX_HARDWARE_POWERLEVELS || + vce_table->count > CZ_MAX_HARDWARE_POWERLEVELS || + acp_table->count > CZ_MAX_HARDWARE_POWERLEVELS) { + DRM_ERROR("amdgpu: Invalid Clock Voltage Dependency Table!\n"); + return -EINVAL; + } + + for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) { + + /* vddc sclk */ + clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid = + (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0; + clock_table->SclkBreakdownTable.ClkLevel[i].Frequency = + (i < vddc_table->count) ? vddc_table->entries[i].clk : 0; + ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + clock_table->SclkBreakdownTable.ClkLevel[i].Frequency, + false, ÷rs); + if (ret) + return ret; + clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid = + (uint8_t)dividers.post_divider; + + /* vddgfx sclk */ + clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid = + (i < vddgfx_table->count) ? (uint8_t)vddgfx_table->entries[i].v : 0; + + /* acp breakdown */ + clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid = + (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0; + clock_table->AclkBreakdownTable.ClkLevel[i].Frequency = + (i < acp_table->count) ? acp_table->entries[i].clk : 0; + ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + clock_table->SclkBreakdownTable.ClkLevel[i].Frequency, + false, ÷rs); + if (ret) + return ret; + clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid = + (uint8_t)dividers.post_divider; + + /* uvd breakdown */ + clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid = + (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0; + clock_table->VclkBreakdownTable.ClkLevel[i].Frequency = + (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; + ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + clock_table->VclkBreakdownTable.ClkLevel[i].Frequency, + false, ÷rs); + if (ret) + return ret; + clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid = + (uint8_t)dividers.post_divider; + + clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid = + (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0; + clock_table->DclkBreakdownTable.ClkLevel[i].Frequency = + (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0; + ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + clock_table->DclkBreakdownTable.ClkLevel[i].Frequency, + false, ÷rs); + if (ret) + return ret; + clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid = + (uint8_t)dividers.post_divider; + + /* vce breakdown */ + clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid = + (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0; + clock_table->EclkBreakdownTable.ClkLevel[i].Frequency = + (i < vce_table->count) ? vce_table->entries[i].ecclk : 0; + ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + clock_table->EclkBreakdownTable.ClkLevel[i].Frequency, + false, ÷rs); + if (ret) + return ret; + clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid = + (uint8_t)dividers.post_divider; + } + + /* its time to upload to SMU */ + ret = cz_smu_upload_pptable(adev); + if (ret) { + DRM_ERROR("amdgpu: Failed to put power play table to SMU!\n"); + return ret; + } + + return 0; +} + +static void cz_init_sclk_limit(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + uint32_t clock = 0, level; + + if (!table || !table->count) { + DRM_ERROR("Invalid Voltage Dependency table.\n"); + return; + } + + pi->sclk_dpm.soft_min_clk = 0; + pi->sclk_dpm.hard_min_clk = 0; + cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel); + level = cz_get_argument(adev); + if (level < table->count) + clock = table->entries[level].clk; + else { + DRM_ERROR("Invalid SLCK Voltage Dependency table entry.\n"); + clock = table->entries[table->count - 1].clk; + } + + pi->sclk_dpm.soft_max_clk = clock; + pi->sclk_dpm.hard_max_clk = clock; + +} + +static void cz_init_uvd_limit(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_uvd_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; + uint32_t clock = 0, level; + + if (!table || !table->count) { + DRM_ERROR("Invalid Voltage Dependency table.\n"); + return; + } + + pi->uvd_dpm.soft_min_clk = 0; + pi->uvd_dpm.hard_min_clk = 0; + cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel); + level = cz_get_argument(adev); + if (level < table->count) + clock = table->entries[level].vclk; + else { + DRM_ERROR("Invalid UVD Voltage Dependency table entry.\n"); + clock = table->entries[table->count - 1].vclk; + } + + pi->uvd_dpm.soft_max_clk = clock; + pi->uvd_dpm.hard_max_clk = clock; + +} + +static void cz_init_vce_limit(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_vce_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + uint32_t clock = 0, level; + + if (!table || !table->count) { + DRM_ERROR("Invalid Voltage Dependency table.\n"); + return; + } + + pi->vce_dpm.soft_min_clk = 0; + pi->vce_dpm.hard_min_clk = 0; + cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel); + level = cz_get_argument(adev); + if (level < table->count) + clock = table->entries[level].evclk; + else { + /* future BIOS would fix this error */ + DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n"); + clock = table->entries[table->count - 1].evclk; + } + + pi->vce_dpm.soft_max_clk = clock; + pi->vce_dpm.hard_max_clk = clock; + +} + +static void cz_init_acp_limit(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; + uint32_t clock = 0, level; + + if (!table || !table->count) { + DRM_ERROR("Invalid Voltage Dependency table.\n"); + return; + } + + pi->acp_dpm.soft_min_clk = 0; + pi->acp_dpm.hard_min_clk = 0; + cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxAclkLevel); + level = cz_get_argument(adev); + if (level < table->count) + clock = table->entries[level].clk; + else { + DRM_ERROR("Invalid ACP Voltage Dependency table entry.\n"); + clock = table->entries[table->count - 1].clk; + } + + pi->acp_dpm.soft_max_clk = clock; + pi->acp_dpm.hard_max_clk = clock; + +} + +static void cz_init_pg_state(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + + pi->uvd_power_gated = false; + pi->vce_power_gated = false; + pi->acp_power_gated = false; + +} + +static void cz_init_sclk_threshold(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + + pi->low_sclk_interrupt_threshold = 0; + +} + +static void cz_dpm_setup_asic(struct amdgpu_device *adev) +{ + cz_reset_ap_mask(adev); + cz_dpm_upload_pptable_to_smu(adev); + cz_init_sclk_limit(adev); + cz_init_uvd_limit(adev); + cz_init_vce_limit(adev); + cz_init_acp_limit(adev); + cz_init_pg_state(adev); + cz_init_sclk_threshold(adev); + +} + +static bool cz_check_smu_feature(struct amdgpu_device *adev, + uint32_t feature) +{ + uint32_t smu_feature = 0; + int ret; + + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_GetFeatureStatus, 0); + if (ret) { + DRM_ERROR("Failed to get SMU features from SMC.\n"); + return false; + } else { + smu_feature = cz_get_argument(adev); + if (feature & smu_feature) + return true; + } + + return false; +} + +static bool cz_check_for_dpm_enabled(struct amdgpu_device *adev) +{ + if (cz_check_smu_feature(adev, + SMU_EnabledFeatureScoreboard_SclkDpmOn)) + return true; + + return false; +} + +static void cz_program_voting_clients(struct amdgpu_device *adev) +{ + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, PPCZ_VOTINGRIGHTSCLIENTS_DFLT0); +} + +static void cz_clear_voting_clients(struct amdgpu_device *adev) +{ + WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0); +} + +static int cz_start_dpm(struct amdgpu_device *adev) +{ + int ret = 0; + + if (amdgpu_dpm) { + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_EnableAllSmuFeatures, SCLK_DPM_MASK); + if (ret) { + DRM_ERROR("SMU feature: SCLK_DPM enable failed\n"); + return -EINVAL; + } + } + + return 0; +} + +static int cz_stop_dpm(struct amdgpu_device *adev) +{ + int ret = 0; + + if (amdgpu_dpm && adev->pm.dpm_enabled) { + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_DisableAllSmuFeatures, SCLK_DPM_MASK); + if (ret) { + DRM_ERROR("SMU feature: SCLK_DPM disable failed\n"); + return -EINVAL; + } + } + + return 0; +} + +static uint32_t cz_get_sclk_level(struct amdgpu_device *adev, + uint32_t clock, uint16_t msg) +{ + int i = 0; + struct amdgpu_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + + switch (msg) { + case PPSMC_MSG_SetSclkSoftMin: + case PPSMC_MSG_SetSclkHardMin: + for (i = 0; i < table->count; i++) + if (clock <= table->entries[i].clk) + break; + if (i == table->count) + i = table->count - 1; + break; + case PPSMC_MSG_SetSclkSoftMax: + case PPSMC_MSG_SetSclkHardMax: + for (i = table->count - 1; i >= 0; i--) + if (clock >= table->entries[i].clk) + break; + if (i < 0) + i = 0; + break; + default: + break; + } + + return i; +} + +static int cz_program_bootup_state(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + uint32_t soft_min_clk = 0; + uint32_t soft_max_clk = 0; + int ret = 0; + + pi->sclk_dpm.soft_min_clk = pi->sys_info.bootup_sclk; + pi->sclk_dpm.soft_max_clk = pi->sys_info.bootup_sclk; + + soft_min_clk = cz_get_sclk_level(adev, + pi->sclk_dpm.soft_min_clk, + PPSMC_MSG_SetSclkSoftMin); + soft_max_clk = cz_get_sclk_level(adev, + pi->sclk_dpm.soft_max_clk, + PPSMC_MSG_SetSclkSoftMax); + + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetSclkSoftMin, soft_min_clk); + if (ret) + return -EINVAL; + + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetSclkSoftMax, soft_max_clk); + if (ret) + return -EINVAL; + + return 0; +} + +/* TODO */ +static int cz_disable_cgpg(struct amdgpu_device *adev) +{ + return 0; +} + +/* TODO */ +static int cz_enable_cgpg(struct amdgpu_device *adev) +{ + return 0; +} + +/* TODO */ +static int cz_program_pt_config_registers(struct amdgpu_device *adev) +{ + return 0; +} + +static void cz_do_enable_didt(struct amdgpu_device *adev, bool enable) +{ + struct cz_power_info *pi = cz_get_pi(adev); + uint32_t reg = 0; + + if (pi->caps_sq_ramping) { + reg = RREG32_DIDT(ixDIDT_SQ_CTRL0); + if (enable) + reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1); + else + reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0); + WREG32_DIDT(ixDIDT_SQ_CTRL0, reg); + } + if (pi->caps_db_ramping) { + reg = RREG32_DIDT(ixDIDT_DB_CTRL0); + if (enable) + reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 1); + else + reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 0); + WREG32_DIDT(ixDIDT_DB_CTRL0, reg); + } + if (pi->caps_td_ramping) { + reg = RREG32_DIDT(ixDIDT_TD_CTRL0); + if (enable) + reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 1); + else + reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 0); + WREG32_DIDT(ixDIDT_TD_CTRL0, reg); + } + if (pi->caps_tcp_ramping) { + reg = RREG32_DIDT(ixDIDT_TCP_CTRL0); + if (enable) + reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1); + else + reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0); + WREG32_DIDT(ixDIDT_TCP_CTRL0, reg); + } + +} + +static int cz_enable_didt(struct amdgpu_device *adev, bool enable) +{ + struct cz_power_info *pi = cz_get_pi(adev); + int ret; + + if (pi->caps_sq_ramping || pi->caps_db_ramping || + pi->caps_td_ramping || pi->caps_tcp_ramping) { + if (adev->gfx.gfx_current_status != AMDGPU_GFX_SAFE_MODE) { + ret = cz_disable_cgpg(adev); + if (ret) { + DRM_ERROR("Pre Di/Dt disable cg/pg failed\n"); + return -EINVAL; + } + adev->gfx.gfx_current_status = AMDGPU_GFX_SAFE_MODE; + } + + ret = cz_program_pt_config_registers(adev); + if (ret) { + DRM_ERROR("Di/Dt config failed\n"); + return -EINVAL; + } + cz_do_enable_didt(adev, enable); + + if (adev->gfx.gfx_current_status == AMDGPU_GFX_SAFE_MODE) { + ret = cz_enable_cgpg(adev); + if (ret) { + DRM_ERROR("Post Di/Dt enable cg/pg failed\n"); + return -EINVAL; + } + adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; + } + } + + return 0; +} + +/* TODO */ +static void cz_reset_acp_boot_level(struct amdgpu_device *adev) +{ +} + +static void cz_update_current_ps(struct amdgpu_device *adev, + struct amdgpu_ps *rps) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct cz_ps *ps = cz_get_ps(rps); + + pi->current_ps = *ps; + pi->current_rps = *rps; + pi->current_rps.ps_priv = ps; + +} + +static void cz_update_requested_ps(struct amdgpu_device *adev, + struct amdgpu_ps *rps) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct cz_ps *ps = cz_get_ps(rps); + + pi->requested_ps = *ps; + pi->requested_rps = *rps; + pi->requested_rps.ps_priv = ps; + +} + +/* PP arbiter support needed TODO */ +static void cz_apply_state_adjust_rules(struct amdgpu_device *adev, + struct amdgpu_ps *new_rps, + struct amdgpu_ps *old_rps) +{ + struct cz_ps *ps = cz_get_ps(new_rps); + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_clock_and_voltage_limits *limits = + &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; + /* 10kHz memory clock */ + uint32_t mclk = 0; + + ps->force_high = false; + ps->need_dfs_bypass = true; + pi->video_start = new_rps->dclk || new_rps->vclk || + new_rps->evclk || new_rps->ecclk; + + if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == + ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) + pi->battery_state = true; + else + pi->battery_state = false; + + if (pi->caps_stable_power_state) + mclk = limits->mclk; + + if (mclk > pi->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK - 1]) + ps->force_high = true; + +} + +static int cz_dpm_enable(struct amdgpu_device *adev) +{ + int ret = 0; + + /* renable will hang up SMU, so check first */ + if (cz_check_for_dpm_enabled(adev)) + return -EINVAL; + + cz_program_voting_clients(adev); + + ret = cz_start_dpm(adev); + if (ret) { + DRM_ERROR("Carrizo DPM enable failed\n"); + return -EINVAL; + } + + ret = cz_program_bootup_state(adev); + if (ret) { + DRM_ERROR("Carrizo bootup state program failed\n"); + return -EINVAL; + } + + ret = cz_enable_didt(adev, true); + if (ret) { + DRM_ERROR("Carrizo enable di/dt failed\n"); + return -EINVAL; + } + + cz_reset_acp_boot_level(adev); + + cz_update_current_ps(adev, adev->pm.dpm.boot_ps); + + return 0; +} + +static int cz_dpm_hw_init(struct amdgpu_device *adev) +{ + int ret; + + if (!amdgpu_dpm) + return 0; + + mutex_lock(&adev->pm.mutex); + + /* init smc in dpm hw init */ + ret = cz_smu_init(adev); + if (ret) { + DRM_ERROR("amdgpu: smc initialization failed\n"); + mutex_unlock(&adev->pm.mutex); + return ret; + } + + /* do the actual fw loading */ + ret = cz_smu_start(adev); + if (ret) { + DRM_ERROR("amdgpu: smc start failed\n"); + mutex_unlock(&adev->pm.mutex); + return ret; + } + + /* cz dpm setup asic */ + cz_dpm_setup_asic(adev); + + /* cz dpm enable */ + ret = cz_dpm_enable(adev); + if (ret) + adev->pm.dpm_enabled = false; + else + adev->pm.dpm_enabled = true; + + mutex_unlock(&adev->pm.mutex); + + return 0; +} + +static int cz_dpm_disable(struct amdgpu_device *adev) +{ + int ret = 0; + + if (!cz_check_for_dpm_enabled(adev)) + return -EINVAL; + + ret = cz_enable_didt(adev, false); + if (ret) { + DRM_ERROR("Carrizo disable di/dt failed\n"); + return -EINVAL; + } + + cz_clear_voting_clients(adev); + cz_stop_dpm(adev); + cz_update_current_ps(adev, adev->pm.dpm.boot_ps); + + return 0; +} + +static int cz_dpm_hw_fini(struct amdgpu_device *adev) +{ + int ret = 0; + + mutex_lock(&adev->pm.mutex); + + cz_smu_fini(adev); + + if (adev->pm.dpm_enabled) { + ret = cz_dpm_disable(adev); + if (ret) + return -EINVAL; + + adev->pm.dpm.current_ps = + adev->pm.dpm.requested_ps = + adev->pm.dpm.boot_ps; + } + + adev->pm.dpm_enabled = false; + + mutex_unlock(&adev->pm.mutex); + + return 0; +} + +static int cz_dpm_suspend(struct amdgpu_device *adev) +{ + int ret = 0; + + if (adev->pm.dpm_enabled) { + mutex_lock(&adev->pm.mutex); + + ret = cz_dpm_disable(adev); + if (ret) + return -EINVAL; + + adev->pm.dpm.current_ps = + adev->pm.dpm.requested_ps = + adev->pm.dpm.boot_ps; + + mutex_unlock(&adev->pm.mutex); + } + + return 0; +} + +static int cz_dpm_resume(struct amdgpu_device *adev) +{ + int ret = 0; + + mutex_lock(&adev->pm.mutex); + ret = cz_smu_init(adev); + if (ret) { + DRM_ERROR("amdgpu: smc resume failed\n"); + mutex_unlock(&adev->pm.mutex); + return ret; + } + + /* do the actual fw loading */ + ret = cz_smu_start(adev); + if (ret) { + DRM_ERROR("amdgpu: smc start failed\n"); + mutex_unlock(&adev->pm.mutex); + return ret; + } + + /* cz dpm setup asic */ + cz_dpm_setup_asic(adev); + + /* cz dpm enable */ + ret = cz_dpm_enable(adev); + if (ret) + adev->pm.dpm_enabled = false; + else + adev->pm.dpm_enabled = true; + + mutex_unlock(&adev->pm.mutex); + /* upon resume, re-compute the clocks */ + if (adev->pm.dpm_enabled) + amdgpu_pm_compute_clocks(adev); + + return 0; +} + +static int cz_dpm_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static int cz_dpm_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +/* borrowed from KV, need future unify */ +static int cz_dpm_get_temperature(struct amdgpu_device *adev) +{ + int actual_temp = 0; + uint32_t temp = RREG32_SMC(0xC0300E0C); + + if (temp) + actual_temp = 1000 * ((temp / 8) - 49); + + return actual_temp; +} + +static int cz_dpm_pre_set_power_state(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; + struct amdgpu_ps *new_ps = &requested_ps; + + cz_update_requested_ps(adev, new_ps); + cz_apply_state_adjust_rules(adev, &pi->requested_rps, + &pi->current_rps); + + return 0; +} + +static int cz_dpm_update_sclk_limit(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_clock_and_voltage_limits *limits = + &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; + uint32_t clock, stable_ps_clock = 0; + + clock = pi->sclk_dpm.soft_min_clk; + + if (pi->caps_stable_power_state) { + stable_ps_clock = limits->sclk * 75 / 100; + if (clock < stable_ps_clock) + clock = stable_ps_clock; + } + + if (clock != pi->sclk_dpm.soft_min_clk) { + pi->sclk_dpm.soft_min_clk = clock; + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetSclkSoftMin, + cz_get_sclk_level(adev, clock, + PPSMC_MSG_SetSclkSoftMin)); + } + + if (pi->caps_stable_power_state && + pi->sclk_dpm.soft_max_clk != clock) { + pi->sclk_dpm.soft_max_clk = clock; + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetSclkSoftMax, + cz_get_sclk_level(adev, clock, + PPSMC_MSG_SetSclkSoftMax)); + } else { + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetSclkSoftMax, + cz_get_sclk_level(adev, + pi->sclk_dpm.soft_max_clk, + PPSMC_MSG_SetSclkSoftMax)); + } + + return 0; +} + +static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev) +{ + int ret = 0; + struct cz_power_info *pi = cz_get_pi(adev); + + if (pi->caps_sclk_ds) { + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetMinDeepSleepSclk, + CZ_MIN_DEEP_SLEEP_SCLK); + } + + return ret; +} + +/* ?? without dal support, is this still needed in setpowerstate list*/ +static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev) +{ + int ret = 0; + struct cz_power_info *pi = cz_get_pi(adev); + + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetWatermarkFrequency, + pi->sclk_dpm.soft_max_clk); + + return ret; +} + +static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev) +{ + int ret = 0; + struct cz_power_info *pi = cz_get_pi(adev); + + /* also depend on dal NBPStateDisableRequired */ + if (pi->nb_dpm_enabled_by_driver && !pi->nb_dpm_enabled) { + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_EnableAllSmuFeatures, + NB_DPM_MASK); + if (ret) { + DRM_ERROR("amdgpu: nb dpm enable failed\n"); + return ret; + } + pi->nb_dpm_enabled = true; + } + + return ret; +} + +static void cz_dpm_nbdpm_lm_pstate_enable(struct amdgpu_device *adev, + bool enable) +{ + if (enable) + cz_send_msg_to_smc(adev, PPSMC_MSG_EnableLowMemoryPstate); + else + cz_send_msg_to_smc(adev, PPSMC_MSG_DisableLowMemoryPstate); + +} + +static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev) +{ + int ret = 0; + struct cz_power_info *pi = cz_get_pi(adev); + struct cz_ps *ps = &pi->requested_ps; + + if (pi->sys_info.nb_dpm_enable) { + if (ps->force_high) + cz_dpm_nbdpm_lm_pstate_enable(adev, true); + else + cz_dpm_nbdpm_lm_pstate_enable(adev, false); + } + + return ret; +} + +/* with dpm enabled */ +static int cz_dpm_set_power_state(struct amdgpu_device *adev) +{ + int ret = 0; + + cz_dpm_update_sclk_limit(adev); + cz_dpm_set_deep_sleep_sclk_threshold(adev); + cz_dpm_set_watermark_threshold(adev); + cz_dpm_enable_nbdpm(adev); + cz_dpm_update_low_memory_pstate(adev); + + return ret; +} + +static void cz_dpm_post_set_power_state(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_ps *ps = &pi->requested_rps; + + cz_update_current_ps(adev, ps); + +} + +static int cz_dpm_force_highest(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + int ret = 0; + + if (pi->sclk_dpm.soft_min_clk != pi->sclk_dpm.soft_max_clk) { + pi->sclk_dpm.soft_min_clk = + pi->sclk_dpm.soft_max_clk; + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetSclkSoftMin, + cz_get_sclk_level(adev, + pi->sclk_dpm.soft_min_clk, + PPSMC_MSG_SetSclkSoftMin)); + if (ret) + return ret; + } + + return ret; +} + +static int cz_dpm_force_lowest(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + int ret = 0; + + if (pi->sclk_dpm.soft_max_clk != pi->sclk_dpm.soft_min_clk) { + pi->sclk_dpm.soft_max_clk = pi->sclk_dpm.soft_min_clk; + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetSclkSoftMax, + cz_get_sclk_level(adev, + pi->sclk_dpm.soft_max_clk, + PPSMC_MSG_SetSclkSoftMax)); + if (ret) + return ret; + } + + return ret; +} + +static uint32_t cz_dpm_get_max_sclk_level(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + + if (!pi->max_sclk_level) { + cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel); + pi->max_sclk_level = cz_get_argument(adev) + 1; + } + + if (pi->max_sclk_level > CZ_MAX_HARDWARE_POWERLEVELS) { + DRM_ERROR("Invalid max sclk level!\n"); + return -EINVAL; + } + + return pi->max_sclk_level; +} + +static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_clock_voltage_dependency_table *dep_table = + &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; + uint32_t level = 0; + int ret = 0; + + pi->sclk_dpm.soft_min_clk = dep_table->entries[0].clk; + level = cz_dpm_get_max_sclk_level(adev) - 1; + if (level < dep_table->count) + pi->sclk_dpm.soft_max_clk = dep_table->entries[level].clk; + else + pi->sclk_dpm.soft_max_clk = + dep_table->entries[dep_table->count - 1].clk; + + /* get min/max sclk soft value + * notify SMU to execute */ + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetSclkSoftMin, + cz_get_sclk_level(adev, + pi->sclk_dpm.soft_min_clk, + PPSMC_MSG_SetSclkSoftMin)); + if (ret) + return ret; + + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetSclkSoftMax, + cz_get_sclk_level(adev, + pi->sclk_dpm.soft_max_clk, + PPSMC_MSG_SetSclkSoftMax)); + if (ret) + return ret; + + DRM_INFO("DPM unforce state min=%d, max=%d.\n", + pi->sclk_dpm.soft_min_clk, + pi->sclk_dpm.soft_max_clk); + + return 0; +} + +static int cz_dpm_force_dpm_level(struct amdgpu_device *adev, + enum amdgpu_dpm_forced_level level) +{ + int ret = 0; + + switch (level) { + case AMDGPU_DPM_FORCED_LEVEL_HIGH: + ret = cz_dpm_force_highest(adev); + if (ret) + return ret; + break; + case AMDGPU_DPM_FORCED_LEVEL_LOW: + ret = cz_dpm_force_lowest(adev); + if (ret) + return ret; + break; + case AMDGPU_DPM_FORCED_LEVEL_AUTO: + ret = cz_dpm_unforce_dpm_levels(adev); + if (ret) + return ret; + break; + default: + break; + } + + return ret; +} + +/* fix me, display configuration change lists here + * mostly dal related*/ +static void cz_dpm_display_configuration_changed(struct amdgpu_device *adev) +{ +} + +static uint32_t cz_dpm_get_sclk(struct amdgpu_device *adev, bool low) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct cz_ps *requested_state = cz_get_ps(&pi->requested_rps); + + if (low) + return requested_state->levels[0].sclk; + else + return requested_state->levels[requested_state->num_levels - 1].sclk; + +} + +static uint32_t cz_dpm_get_mclk(struct amdgpu_device *adev, bool low) +{ + struct cz_power_info *pi = cz_get_pi(adev); + + return pi->sys_info.bootup_uma_clk; +} + +const struct amdgpu_ip_funcs cz_dpm_ip_funcs = { + .early_init = cz_dpm_early_init, + .late_init = NULL, + .sw_init = cz_dpm_sw_init, + .sw_fini = cz_dpm_sw_fini, + .hw_init = cz_dpm_hw_init, + .hw_fini = cz_dpm_hw_fini, + .suspend = cz_dpm_suspend, + .resume = cz_dpm_resume, + .is_idle = NULL, + .wait_for_idle = NULL, + .soft_reset = NULL, + .print_status = NULL, + .set_clockgating_state = cz_dpm_set_clockgating_state, + .set_powergating_state = cz_dpm_set_powergating_state, +}; + +static const struct amdgpu_dpm_funcs cz_dpm_funcs = { + .get_temperature = cz_dpm_get_temperature, + .pre_set_power_state = cz_dpm_pre_set_power_state, + .set_power_state = cz_dpm_set_power_state, + .post_set_power_state = cz_dpm_post_set_power_state, + .display_configuration_changed = cz_dpm_display_configuration_changed, + .get_sclk = cz_dpm_get_sclk, + .get_mclk = cz_dpm_get_mclk, + .print_power_state = cz_dpm_print_power_state, + .debugfs_print_current_performance_level = + cz_dpm_debugfs_print_current_performance_level, + .force_performance_level = cz_dpm_force_dpm_level, + .vblank_too_short = NULL, + .powergate_uvd = NULL, +}; + +static void cz_dpm_set_funcs(struct amdgpu_device *adev) +{ + if (NULL == adev->pm.funcs) + adev->pm.funcs = &cz_dpm_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h new file mode 100644 index 000000000000..ed6449de5dc5 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h @@ -0,0 +1,235 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __CZ_DPM_H__ +#define __CZ_DPM_H__ + +#include "smu8_fusion.h" + +#define CZ_AT_DFLT 30 +#define CZ_NUM_NBPSTATES 4 +#define CZ_NUM_NBPMEMORY_CLOCK 2 +#define CZ_MAX_HARDWARE_POWERLEVELS 8 +#define CZ_MAX_DISPLAY_CLOCK_LEVEL 8 +#define CZ_MAX_DISPLAYPHY_IDS 10 + +#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 + +#define SMC_RAM_END 0x40000 + +#define DPMFlags_SCLK_Enabled 0x00000001 +#define DPMFlags_UVD_Enabled 0x00000002 +#define DPMFlags_VCE_Enabled 0x00000004 +#define DPMFlags_ACP_Enabled 0x00000008 +#define DPMFlags_ForceHighestValid 0x40000000 +#define DPMFlags_Debug 0x80000000 + +/* Do not change the following, it is also defined in SMU8.h */ +#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 +#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00100000 +#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000 +#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000 + +/* temporary solution to SetMinDeepSleepSclk + * should indicate by display adaptor + * 10k Hz unit*/ +#define CZ_MIN_DEEP_SLEEP_SCLK 800 + +enum cz_pt_config_reg_type { + CZ_CONFIGREG_MMR = 0, + CZ_CONFIGREG_SMC_IND, + CZ_CONFIGREG_DIDT_IND, + CZ_CONFIGREG_CACHE, + CZ_CONFIGREG_MAX +}; + +struct cz_pt_config_reg { + uint32_t offset; + uint32_t mask; + uint32_t shift; + uint32_t value; + enum cz_pt_config_reg_type type; +}; + +struct cz_dpm_entry { + uint32_t soft_min_clk; + uint32_t hard_min_clk; + uint32_t soft_max_clk; + uint32_t hard_max_clk; +}; + +struct cz_pl { + uint32_t sclk; + uint8_t vddc_index; + uint8_t ds_divider_index; + uint8_t ss_divider_index; + uint8_t allow_gnb_slow; + uint8_t force_nbp_state; + uint8_t display_wm; + uint8_t vce_wm; +}; + +struct cz_ps { + struct cz_pl levels[CZ_MAX_HARDWARE_POWERLEVELS]; + uint32_t num_levels; + bool need_dfs_bypass; + uint8_t dpm0_pg_nb_ps_lo; + uint8_t dpm0_pg_nb_ps_hi; + uint8_t dpmx_nb_ps_lo; + uint8_t dpmx_nb_ps_hi; + bool force_high; +}; + +struct cz_displayphy_entry { + uint8_t phy_present; + uint8_t active_lane_mapping; + uint8_t display_conf_type; + uint8_t num_active_lanes; +}; + +struct cz_displayphy_info { + bool phy_access_initialized; + struct cz_displayphy_entry entries[CZ_MAX_DISPLAYPHY_IDS]; +}; + +struct cz_sys_info { + uint32_t bootup_uma_clk; + uint32_t bootup_sclk; + uint32_t dentist_vco_freq; + uint32_t nb_dpm_enable; + uint32_t nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK]; + uint32_t nbp_n_clock[CZ_NUM_NBPSTATES]; + uint8_t nbp_voltage_index[CZ_NUM_NBPSTATES]; + uint32_t display_clock[CZ_MAX_DISPLAY_CLOCK_LEVEL]; + uint16_t bootup_nb_voltage_index; + uint8_t htc_tmp_lmt; + uint8_t htc_hyst_lmt; + uint32_t uma_channel_number; +}; + +struct cz_power_info { + uint32_t active_target[CZ_MAX_HARDWARE_POWERLEVELS]; + struct cz_sys_info sys_info; + struct cz_pl boot_pl; + bool disable_nb_ps3_in_battery; + bool battery_state; + uint32_t lowest_valid; + uint32_t highest_valid; + uint16_t high_voltage_threshold; + /* smc offsets */ + uint32_t sram_end; + uint32_t dpm_table_start; + uint32_t soft_regs_start; + /* dpm SMU tables */ + uint8_t uvd_level_count; + uint8_t vce_level_count; + uint8_t acp_level_count; + uint32_t fps_high_threshold; + uint32_t fps_low_threshold; + /* dpm table */ + uint32_t dpm_flags; + struct cz_dpm_entry sclk_dpm; + struct cz_dpm_entry uvd_dpm; + struct cz_dpm_entry vce_dpm; + struct cz_dpm_entry acp_dpm; + + uint8_t uvd_boot_level; + uint8_t uvd_interval; + uint8_t vce_boot_level; + uint8_t vce_interval; + uint8_t acp_boot_level; + uint8_t acp_interval; + + uint8_t graphics_boot_level; + uint8_t graphics_interval; + uint8_t graphics_therm_throttle_enable; + uint8_t graphics_voltage_change_enable; + uint8_t graphics_clk_slow_enable; + uint8_t graphics_clk_slow_divider; + + uint32_t low_sclk_interrupt_threshold; + bool uvd_power_gated; + bool vce_power_gated; + bool acp_power_gated; + + uint32_t active_process_mask; + + uint32_t mgcg_cgtt_local0; + uint32_t mgcg_cgtt_local1; + uint32_t clock_slow_down_step; + uint32_t skip_clock_slow_down; + bool enable_nb_ps_policy; + uint32_t voting_clients; + uint32_t voltage_drop_threshold; + uint32_t gfx_pg_threshold; + uint32_t max_sclk_level; + /* flags */ + bool didt_enabled; + bool video_start; + bool cac_enabled; + bool bapm_enabled; + bool nb_dpm_enabled_by_driver; + bool nb_dpm_enabled; + bool auto_thermal_throttling_enabled; + bool dpm_enabled; + bool need_pptable_upload; + /* caps */ + bool caps_cac; + bool caps_power_containment; + bool caps_sq_ramping; + bool caps_db_ramping; + bool caps_td_ramping; + bool caps_tcp_ramping; + bool caps_sclk_throttle_low_notification; + bool caps_fps; + bool caps_uvd_dpm; + bool caps_uvd_pg; + bool caps_vce_dpm; + bool caps_vce_pg; + bool caps_acp_dpm; + bool caps_acp_pg; + bool caps_stable_power_state; + bool caps_enable_dfs_bypass; + bool caps_sclk_ds; + bool caps_voltage_island; + /* power state */ + struct amdgpu_ps current_rps; + struct cz_ps current_ps; + struct amdgpu_ps requested_rps; + struct cz_ps requested_ps; + + bool uvd_power_down; + bool vce_power_down; + bool acp_power_down; +}; + +/* cz_smc.c */ +uint32_t cz_get_argument(struct amdgpu_device *adev); +int cz_send_msg_to_smc(struct amdgpu_device *adev, uint16_t msg); +int cz_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, + uint16_t msg, uint32_t parameter); +int cz_read_smc_sram_dword(struct amdgpu_device *adev, + uint32_t smc_address, uint32_t *value, uint32_t limit); +int cz_smu_upload_pptable(struct amdgpu_device *adev); +int cz_smu_download_pptable(struct amdgpu_device *adev, void **table); +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c new file mode 100644 index 000000000000..80d508e64a86 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -0,0 +1,435 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_ih.h" +#include "vid.h" + +#include "oss/oss_3_0_1_d.h" +#include "oss/oss_3_0_1_sh_mask.h" + +#include "bif/bif_5_1_d.h" +#include "bif/bif_5_1_sh_mask.h" + +/* + * Interrupts + * Starting with r6xx, interrupts are handled via a ring buffer. + * Ring buffers are areas of GPU accessible memory that the GPU + * writes interrupt vectors into and the host reads vectors out of. + * There is a rptr (read pointer) that determines where the + * host is currently reading, and a wptr (write pointer) + * which determines where the GPU has written. When the + * pointers are equal, the ring is idle. When the GPU + * writes vectors to the ring buffer, it increments the + * wptr. When there is an interrupt, the host then starts + * fetching commands and processing them until the pointers are + * equal again at which point it updates the rptr. + */ + +static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev); + +/** + * cz_ih_enable_interrupts - Enable the interrupt ring buffer + * + * @adev: amdgpu_device pointer + * + * Enable the interrupt ring buffer (VI). + */ +static void cz_ih_enable_interrupts(struct amdgpu_device *adev) +{ + u32 ih_cntl = RREG32(mmIH_CNTL); + u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); + + ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); + WREG32(mmIH_CNTL, ih_cntl); + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + adev->irq.ih.enabled = true; +} + +/** + * cz_ih_disable_interrupts - Disable the interrupt ring buffer + * + * @adev: amdgpu_device pointer + * + * Disable the interrupt ring buffer (VI). + */ +static void cz_ih_disable_interrupts(struct amdgpu_device *adev) +{ + u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); + u32 ih_cntl = RREG32(mmIH_CNTL); + + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); + ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + WREG32(mmIH_CNTL, ih_cntl); + /* set rptr, wptr to 0 */ + WREG32(mmIH_RB_RPTR, 0); + WREG32(mmIH_RB_WPTR, 0); + adev->irq.ih.enabled = false; + adev->irq.ih.rptr = 0; +} + +/** + * cz_ih_irq_init - init and enable the interrupt ring + * + * @adev: amdgpu_device pointer + * + * Allocate a ring buffer for the interrupt controller, + * enable the RLC, disable interrupts, enable the IH + * ring buffer and enable it (VI). + * Called at device load and reume. + * Returns 0 for success, errors for failure. + */ +static int cz_ih_irq_init(struct amdgpu_device *adev) +{ + int ret = 0; + int rb_bufsz; + u32 interrupt_cntl, ih_cntl, ih_rb_cntl; + u64 wptr_off; + + /* disable irqs */ + cz_ih_disable_interrupts(adev); + + /* setup interrupt control */ + WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); + interrupt_cntl = RREG32(mmINTERRUPT_CNTL); + /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi + * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN + */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); + /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); + WREG32(mmINTERRUPT_CNTL, interrupt_cntl); + + /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ + WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); + + rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); + ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); + + /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); + + /* set the writeback address whether it's enabled or not */ + wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); + WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); + WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); + + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + + /* set rptr, wptr to 0 */ + WREG32(mmIH_RB_RPTR, 0); + WREG32(mmIH_RB_WPTR, 0); + + /* Default settings for IH_CNTL (disabled at first) */ + ih_cntl = RREG32(mmIH_CNTL); + ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); + + if (adev->irq.msi_enabled) + ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); + WREG32(mmIH_CNTL, ih_cntl); + + pci_set_master(adev->pdev); + + /* enable interrupts */ + cz_ih_enable_interrupts(adev); + + return ret; +} + +/** + * cz_ih_irq_disable - disable interrupts + * + * @adev: amdgpu_device pointer + * + * Disable interrupts on the hw (VI). + */ +static void cz_ih_irq_disable(struct amdgpu_device *adev) +{ + cz_ih_disable_interrupts(adev); + + /* Wait and acknowledge irq */ + mdelay(1); +} + +/** + * cz_ih_get_wptr - get the IH ring buffer wptr + * + * @adev: amdgpu_device pointer + * + * Get the IH ring buffer wptr from either the register + * or the writeback memory buffer (VI). Also check for + * ring buffer overflow and deal with it. + * Used by cz_irq_process(VI). + * Returns the value of the wptr. + */ +static u32 cz_ih_get_wptr(struct amdgpu_device *adev) +{ + u32 wptr, tmp; + + wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); + + if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { + wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); + /* When a ring buffer overflow happen start parsing interrupt + * from the last not overwritten vector (wptr + 16). Hopefully + * this should allow us to catchup. + */ + dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", + wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); + adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; + tmp = RREG32(mmIH_RB_CNTL); + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); + WREG32(mmIH_RB_CNTL, tmp); + } + return (wptr & adev->irq.ih.ptr_mask); +} + +/** + * cz_ih_decode_iv - decode an interrupt vector + * + * @adev: amdgpu_device pointer + * + * Decodes the interrupt vector at the current rptr + * position and also advance the position. + */ +static void cz_ih_decode_iv(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry) +{ + /* wptr/rptr are in bytes! */ + u32 ring_index = adev->irq.ih.rptr >> 2; + uint32_t dw[4]; + + dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); + dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); + dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); + dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); + + entry->src_id = dw[0] & 0xff; + entry->src_data = dw[1] & 0xfffffff; + entry->ring_id = dw[2] & 0xff; + entry->vm_id = (dw[2] >> 8) & 0xff; + entry->pas_id = (dw[2] >> 16) & 0xffff; + + /* wptr/rptr are in bytes! */ + adev->irq.ih.rptr += 16; +} + +/** + * cz_ih_set_rptr - set the IH ring buffer rptr + * + * @adev: amdgpu_device pointer + * + * Set the IH ring buffer rptr. + */ +static void cz_ih_set_rptr(struct amdgpu_device *adev) +{ + WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); +} + +static int cz_ih_early_init(struct amdgpu_device *adev) +{ + cz_ih_set_interrupt_funcs(adev); + return 0; +} + +static int cz_ih_sw_init(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_ih_ring_init(adev, 64 * 1024, false); + if (r) + return r; + + r = amdgpu_irq_init(adev); + + return r; +} + +static int cz_ih_sw_fini(struct amdgpu_device *adev) +{ + amdgpu_irq_fini(adev); + amdgpu_ih_ring_fini(adev); + + return 0; +} + +static int cz_ih_hw_init(struct amdgpu_device *adev) +{ + int r; + + r = cz_ih_irq_init(adev); + if (r) + return r; + + return 0; +} + +static int cz_ih_hw_fini(struct amdgpu_device *adev) +{ + cz_ih_irq_disable(adev); + + return 0; +} + +static int cz_ih_suspend(struct amdgpu_device *adev) +{ + return cz_ih_hw_fini(adev); +} + +static int cz_ih_resume(struct amdgpu_device *adev) +{ + return cz_ih_hw_init(adev); +} + +static bool cz_ih_is_idle(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmSRBM_STATUS); + + if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) + return false; + + return true; +} + +static int cz_ih_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(mmSRBM_STATUS); + if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static void cz_ih_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "CZ IH registers\n"); + dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", + RREG32(mmSRBM_STATUS)); + dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", + RREG32(mmSRBM_STATUS2)); + dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", + RREG32(mmINTERRUPT_CNTL)); + dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", + RREG32(mmINTERRUPT_CNTL2)); + dev_info(adev->dev, " IH_CNTL=0x%08X\n", + RREG32(mmIH_CNTL)); + dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", + RREG32(mmIH_RB_CNTL)); + dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", + RREG32(mmIH_RB_BASE)); + dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", + RREG32(mmIH_RB_WPTR_ADDR_LO)); + dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", + RREG32(mmIH_RB_WPTR_ADDR_HI)); + dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", + RREG32(mmIH_RB_RPTR)); + dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", + RREG32(mmIH_RB_WPTR)); +} + +static int cz_ih_soft_reset(struct amdgpu_device *adev) +{ + u32 srbm_soft_reset = 0; + u32 tmp = RREG32(mmSRBM_STATUS); + + if (tmp & SRBM_STATUS__IH_BUSY_MASK) + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, + SOFT_RESET_IH, 1); + + if (srbm_soft_reset) { + cz_ih_print_status(adev); + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + + cz_ih_print_status(adev); + } + + return 0; +} + +static int cz_ih_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + // TODO + return 0; +} + +static int cz_ih_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + // TODO + return 0; +} + +const struct amdgpu_ip_funcs cz_ih_ip_funcs = { + .early_init = cz_ih_early_init, + .late_init = NULL, + .sw_init = cz_ih_sw_init, + .sw_fini = cz_ih_sw_fini, + .hw_init = cz_ih_hw_init, + .hw_fini = cz_ih_hw_fini, + .suspend = cz_ih_suspend, + .resume = cz_ih_resume, + .is_idle = cz_ih_is_idle, + .wait_for_idle = cz_ih_wait_for_idle, + .soft_reset = cz_ih_soft_reset, + .print_status = cz_ih_print_status, + .set_clockgating_state = cz_ih_set_clockgating_state, + .set_powergating_state = cz_ih_set_powergating_state, +}; + +static const struct amdgpu_ih_funcs cz_ih_funcs = { + .get_wptr = cz_ih_get_wptr, + .decode_iv = cz_ih_decode_iv, + .set_rptr = cz_ih_set_rptr +}; + +static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev) +{ + if (adev->irq.ih_funcs == NULL) + adev->irq.ih_funcs = &cz_ih_funcs; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.h b/drivers/gpu/drm/amd/amdgpu/cz_ih.h new file mode 100644 index 000000000000..1bce136876ff --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __CZ_IH_H__ +#define __CZ_IH_H__ + +extern const struct amdgpu_ip_funcs cz_ih_ip_funcs; + +#endif /* __CZ_IH_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h b/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h new file mode 100644 index 000000000000..273616ab43db --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h @@ -0,0 +1,185 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef CZ_PP_SMC_H +#define CZ_PP_SMC_H + +#pragma pack(push, 1) + +/* Fan control algorithm:*/ +#define FDO_MODE_HARDWARE 0 +#define FDO_MODE_PIECE_WISE_LINEAR 1 + +enum FAN_CONTROL { + FAN_CONTROL_FUZZY, + FAN_CONTROL_TABLE +}; + +enum DPM_ARRAY { + DPM_ARRAY_HARD_MAX, + DPM_ARRAY_HARD_MIN, + DPM_ARRAY_SOFT_MAX, + DPM_ARRAY_SOFT_MIN +}; + +/* + * Return codes for driver to SMC communication. + * Leave these #define-s, enums might not be exactly 8-bits on the microcontroller. + */ +#define PPSMC_Result_OK ((uint16_t)0x01) +#define PPSMC_Result_NoMore ((uint16_t)0x02) +#define PPSMC_Result_NotNow ((uint16_t)0x03) +#define PPSMC_Result_Failed ((uint16_t)0xFF) +#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) +#define PPSMC_Result_UnknownVT ((uint16_t)0xFD) + +#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) + +/* + * Supported driver messages + */ +#define PPSMC_MSG_Test ((uint16_t) 0x1) +#define PPSMC_MSG_GetFeatureStatus ((uint16_t) 0x2) +#define PPSMC_MSG_EnableAllSmuFeatures ((uint16_t) 0x3) +#define PPSMC_MSG_DisableAllSmuFeatures ((uint16_t) 0x4) +#define PPSMC_MSG_OptimizeBattery ((uint16_t) 0x5) +#define PPSMC_MSG_MaximizePerf ((uint16_t) 0x6) +#define PPSMC_MSG_UVDPowerOFF ((uint16_t) 0x7) +#define PPSMC_MSG_UVDPowerON ((uint16_t) 0x8) +#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x9) +#define PPSMC_MSG_VCEPowerON ((uint16_t) 0xA) +#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0xB) +#define PPSMC_MSG_ACPPowerON ((uint16_t) 0xC) +#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0xD) +#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0xE) +#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0xF) +#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x10) +#define PPSMC_MSG_SetMinDeepSleepSclk ((uint16_t) 0x11) +#define PPSMC_MSG_SetSclkSoftMin ((uint16_t) 0x12) +#define PPSMC_MSG_SetSclkSoftMax ((uint16_t) 0x13) +#define PPSMC_MSG_SetSclkHardMin ((uint16_t) 0x14) +#define PPSMC_MSG_SetSclkHardMax ((uint16_t) 0x15) +#define PPSMC_MSG_SetLclkSoftMin ((uint16_t) 0x16) +#define PPSMC_MSG_SetLclkSoftMax ((uint16_t) 0x17) +#define PPSMC_MSG_SetLclkHardMin ((uint16_t) 0x18) +#define PPSMC_MSG_SetLclkHardMax ((uint16_t) 0x19) +#define PPSMC_MSG_SetUvdSoftMin ((uint16_t) 0x1A) +#define PPSMC_MSG_SetUvdSoftMax ((uint16_t) 0x1B) +#define PPSMC_MSG_SetUvdHardMin ((uint16_t) 0x1C) +#define PPSMC_MSG_SetUvdHardMax ((uint16_t) 0x1D) +#define PPSMC_MSG_SetEclkSoftMin ((uint16_t) 0x1E) +#define PPSMC_MSG_SetEclkSoftMax ((uint16_t) 0x1F) +#define PPSMC_MSG_SetEclkHardMin ((uint16_t) 0x20) +#define PPSMC_MSG_SetEclkHardMax ((uint16_t) 0x21) +#define PPSMC_MSG_SetAclkSoftMin ((uint16_t) 0x22) +#define PPSMC_MSG_SetAclkSoftMax ((uint16_t) 0x23) +#define PPSMC_MSG_SetAclkHardMin ((uint16_t) 0x24) +#define PPSMC_MSG_SetAclkHardMax ((uint16_t) 0x25) +#define PPSMC_MSG_SetNclkSoftMin ((uint16_t) 0x26) +#define PPSMC_MSG_SetNclkSoftMax ((uint16_t) 0x27) +#define PPSMC_MSG_SetNclkHardMin ((uint16_t) 0x28) +#define PPSMC_MSG_SetNclkHardMax ((uint16_t) 0x29) +#define PPSMC_MSG_SetPstateSoftMin ((uint16_t) 0x2A) +#define PPSMC_MSG_SetPstateSoftMax ((uint16_t) 0x2B) +#define PPSMC_MSG_SetPstateHardMin ((uint16_t) 0x2C) +#define PPSMC_MSG_SetPstateHardMax ((uint16_t) 0x2D) +#define PPSMC_MSG_DisableLowMemoryPstate ((uint16_t) 0x2E) +#define PPSMC_MSG_EnableLowMemoryPstate ((uint16_t) 0x2F) +#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x30) +#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x31) +#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x32) +#define PPSMC_MSG_DriverDramAddrHi ((uint16_t) 0x33) +#define PPSMC_MSG_DriverDramAddrLo ((uint16_t) 0x34) +#define PPSMC_MSG_CondExecDramAddrHi ((uint16_t) 0x35) +#define PPSMC_MSG_CondExecDramAddrLo ((uint16_t) 0x36) +#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x37) +#define PPSMC_MSG_DriverResetMode ((uint16_t) 0x38) +#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x39) +#define PPSMC_MSG_SetDisplayPhyConfig ((uint16_t) 0x3A) +#define PPSMC_MSG_GetMaxSclkLevel ((uint16_t) 0x3B) +#define PPSMC_MSG_GetMaxLclkLevel ((uint16_t) 0x3C) +#define PPSMC_MSG_GetMaxUvdLevel ((uint16_t) 0x3D) +#define PPSMC_MSG_GetMaxEclkLevel ((uint16_t) 0x3E) +#define PPSMC_MSG_GetMaxAclkLevel ((uint16_t) 0x3F) +#define PPSMC_MSG_GetMaxNclkLevel ((uint16_t) 0x40) +#define PPSMC_MSG_GetMaxPstate ((uint16_t) 0x41) +#define PPSMC_MSG_DramAddrHiVirtual ((uint16_t) 0x42) +#define PPSMC_MSG_DramAddrLoVirtual ((uint16_t) 0x43) +#define PPSMC_MSG_DramAddrHiPhysical ((uint16_t) 0x44) +#define PPSMC_MSG_DramAddrLoPhysical ((uint16_t) 0x45) +#define PPSMC_MSG_DramBufferSize ((uint16_t) 0x46) +#define PPSMC_MSG_SetMmPwrLogDramAddrHi ((uint16_t) 0x47) +#define PPSMC_MSG_SetMmPwrLogDramAddrLo ((uint16_t) 0x48) +#define PPSMC_MSG_SetClkTableAddrHi ((uint16_t) 0x49) +#define PPSMC_MSG_SetClkTableAddrLo ((uint16_t) 0x4A) +#define PPSMC_MSG_GetConservativePowerLimit ((uint16_t) 0x4B) + +#define PPSMC_MSG_InitJobs ((uint16_t) 0x252) +#define PPSMC_MSG_ExecuteJob ((uint16_t) 0x254) + +#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) +#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) + +#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) +#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) + +#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170) +#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171) + +#define PPSMC_MSG_AllowLowSclkInterrupt ((uint16_t) 0x184) +#define PPSMC_MSG_MmPowerMonitorStart ((uint16_t) 0x18F) +#define PPSMC_MSG_MmPowerMonitorStop ((uint16_t) 0x190) +#define PPSMC_MSG_MmPowerMonitorRestart ((uint16_t) 0x191) + +#define PPSMC_MSG_SetClockGateMask ((uint16_t) 0x260) +#define PPSMC_MSG_SetFpsThresholdLo ((uint16_t) 0x264) +#define PPSMC_MSG_SetFpsThresholdHi ((uint16_t) 0x265) +#define PPSMC_MSG_SetLowSclkIntrThreshold ((uint16_t) 0x266) + +#define PPSMC_MSG_ClkTableXferToDram ((uint16_t) 0x267) +#define PPSMC_MSG_ClkTableXferToSmu ((uint16_t) 0x268) +#define PPSMC_MSG_GetAverageGraphicsActivity ((uint16_t) 0x269) +#define PPSMC_MSG_GetAverageGioActivity ((uint16_t) 0x26A) +#define PPSMC_MSG_SetLoggerBufferSize ((uint16_t) 0x26B) +#define PPSMC_MSG_SetLoggerAddressHigh ((uint16_t) 0x26C) +#define PPSMC_MSG_SetLoggerAddressLow ((uint16_t) 0x26D) +#define PPSMC_MSG_SetWatermarkFrequency ((uint16_t) 0x26E) + +/* REMOVE LATER*/ +#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) + +/* Feature Enable Masks*/ +#define NB_DPM_MASK 0x00000800 +#define VDDGFX_MASK 0x00800000 +#define VCE_DPM_MASK 0x00400000 +#define ACP_DPM_MASK 0x00040000 +#define UVD_DPM_MASK 0x00010000 +#define GFX_CU_PG_MASK 0x00004000 +#define SCLK_DPM_MASK 0x00080000 + +#if !defined(SMC_MICROCODE) +#pragma pack(pop) + +#endif + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smc.c b/drivers/gpu/drm/amd/amdgpu/cz_smc.c new file mode 100644 index 000000000000..a72ffc7d6c26 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cz_smc.c @@ -0,0 +1,962 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include "drmP.h" +#include "amdgpu.h" +#include "smu8.h" +#include "smu8_fusion.h" +#include "cz_ppsmc.h" +#include "cz_smumgr.h" +#include "smu_ucode_xfer_cz.h" +#include "amdgpu_ucode.h" + +#include "smu/smu_8_0_d.h" +#include "smu/smu_8_0_sh_mask.h" +#include "gca/gfx_8_0_d.h" +#include "gca/gfx_8_0_sh_mask.h" + +uint32_t cz_get_argument(struct amdgpu_device *adev) +{ + return RREG32(mmSMU_MP1_SRBM2P_ARG_0); +} + +static struct cz_smu_private_data *cz_smu_get_priv(struct amdgpu_device *adev) +{ + struct cz_smu_private_data *priv = + (struct cz_smu_private_data *)(adev->smu.priv); + + return priv; +} + +int cz_send_msg_to_smc_async(struct amdgpu_device *adev, u16 msg) +{ + int i; + u32 content = 0, tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = REG_GET_FIELD(RREG32(mmSMU_MP1_SRBM2P_RESP_0), + SMU_MP1_SRBM2P_RESP_0, CONTENT); + if (content != tmp) + break; + udelay(1); + } + + /* timeout means wrong logic*/ + if (i == adev->usec_timeout) + return -EINVAL; + + WREG32(mmSMU_MP1_SRBM2P_RESP_0, 0); + WREG32(mmSMU_MP1_SRBM2P_MSG_0, msg); + + return 0; +} + +int cz_send_msg_to_smc(struct amdgpu_device *adev, u16 msg) +{ + int i; + u32 content = 0, tmp = 0; + + if (cz_send_msg_to_smc_async(adev, msg)) + return -EINVAL; + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = REG_GET_FIELD(RREG32(mmSMU_MP1_SRBM2P_RESP_0), + SMU_MP1_SRBM2P_RESP_0, CONTENT); + if (content != tmp) + break; + udelay(1); + } + + /* timeout means wrong logic*/ + if (i == adev->usec_timeout) + return -EINVAL; + + if (PPSMC_Result_OK != tmp) { + dev_err(adev->dev, "SMC Failed to send Message.\n"); + return -EINVAL; + } + + return 0; +} + +int cz_send_msg_to_smc_with_parameter_async(struct amdgpu_device *adev, + u16 msg, u32 parameter) +{ + WREG32(mmSMU_MP1_SRBM2P_ARG_0, parameter); + return cz_send_msg_to_smc_async(adev, msg); +} + +int cz_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, + u16 msg, u32 parameter) +{ + WREG32(mmSMU_MP1_SRBM2P_ARG_0, parameter); + return cz_send_msg_to_smc(adev, msg); +} + +static int cz_set_smc_sram_address(struct amdgpu_device *adev, + u32 smc_address, u32 limit) +{ + if (smc_address & 3) + return -EINVAL; + if ((smc_address + 3) > limit) + return -EINVAL; + + WREG32(mmMP0PUB_IND_INDEX_0, SMN_MP1_SRAM_START_ADDR + smc_address); + + return 0; +} + +int cz_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, + u32 *value, u32 limit) +{ + int ret; + + ret = cz_set_smc_sram_address(adev, smc_address, limit); + if (ret) + return ret; + + *value = RREG32(mmMP0PUB_IND_DATA_0); + + return 0; +} + +int cz_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, + u32 value, u32 limit) +{ + int ret; + + ret = cz_set_smc_sram_address(adev, smc_address, limit); + if (ret) + return ret; + + WREG32(mmMP0PUB_IND_DATA_0, value); + + return 0; +} + +static int cz_smu_request_load_fw(struct amdgpu_device *adev) +{ + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + + uint32_t smc_addr = SMU8_FIRMWARE_HEADER_LOCATION + + offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus); + + cz_write_smc_sram_dword(adev, smc_addr, 0, smc_addr + 4); + + /*prepare toc buffers*/ + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_DriverDramAddrHi, + priv->toc_buffer.mc_addr_high); + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_DriverDramAddrLo, + priv->toc_buffer.mc_addr_low); + cz_send_msg_to_smc(adev, PPSMC_MSG_InitJobs); + + /*execute jobs*/ + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_ExecuteJob, + priv->toc_entry_aram); + + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_ExecuteJob, + priv->toc_entry_power_profiling_index); + + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_ExecuteJob, + priv->toc_entry_initialize_index); + + return 0; +} + +/* + *Check if the FW has been loaded, SMU will not return if loading + *has not finished. + */ +static int cz_smu_check_fw_load_finish(struct amdgpu_device *adev, + uint32_t fw_mask) +{ + int i; + uint32_t index = SMN_MP1_SRAM_START_ADDR + + SMU8_FIRMWARE_HEADER_LOCATION + + offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus); + + WREG32(mmMP0PUB_IND_INDEX, index); + + for (i = 0; i < adev->usec_timeout; i++) { + if (fw_mask == (RREG32(mmMP0PUB_IND_DATA) & fw_mask)) + break; + udelay(1); + } + + if (i >= adev->usec_timeout) { + dev_err(adev->dev, + "SMU check loaded firmware failed, expecting 0x%x, getting 0x%x", + fw_mask, RREG32(mmMP0PUB_IND_DATA)); + return -EINVAL; + } + + return 0; +} + +/* + * interfaces for different ip blocks to check firmware loading status + * 0 for success otherwise failed + */ +static int cz_smu_check_finished(struct amdgpu_device *adev, + enum AMDGPU_UCODE_ID id) +{ + switch (id) { + case AMDGPU_UCODE_ID_SDMA0: + if (adev->smu.fw_flags & AMDGPU_SDMA0_UCODE_LOADED) + return 0; + break; + case AMDGPU_UCODE_ID_SDMA1: + if (adev->smu.fw_flags & AMDGPU_SDMA1_UCODE_LOADED) + return 0; + break; + case AMDGPU_UCODE_ID_CP_CE: + if (adev->smu.fw_flags & AMDGPU_CPCE_UCODE_LOADED) + return 0; + break; + case AMDGPU_UCODE_ID_CP_PFP: + if (adev->smu.fw_flags & AMDGPU_CPPFP_UCODE_LOADED) + return 0; + case AMDGPU_UCODE_ID_CP_ME: + if (adev->smu.fw_flags & AMDGPU_CPME_UCODE_LOADED) + return 0; + break; + case AMDGPU_UCODE_ID_CP_MEC1: + if (adev->smu.fw_flags & AMDGPU_CPMEC1_UCODE_LOADED) + return 0; + break; + case AMDGPU_UCODE_ID_CP_MEC2: + if (adev->smu.fw_flags & AMDGPU_CPMEC2_UCODE_LOADED) + return 0; + break; + case AMDGPU_UCODE_ID_RLC_G: + if (adev->smu.fw_flags & AMDGPU_CPRLC_UCODE_LOADED) + return 0; + break; + case AMDGPU_UCODE_ID_MAXIMUM: + default: + break; + } + + return 1; +} + +static int cz_load_mec_firmware(struct amdgpu_device *adev) +{ + struct amdgpu_firmware_info *ucode = + &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; + uint32_t reg_data; + uint32_t tmp; + + if (ucode->fw == NULL) + return -EINVAL; + + /* Disable MEC parsing/prefetching */ + tmp = RREG32(mmCP_MEC_CNTL); + tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); + WREG32(mmCP_MEC_CNTL, tmp); + + tmp = RREG32(mmCP_CPC_IC_BASE_CNTL); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1); + WREG32(mmCP_CPC_IC_BASE_CNTL, tmp); + + reg_data = lower_32_bits(ucode->mc_addr) & + REG_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO); + WREG32(mmCP_CPC_IC_BASE_LO, reg_data); + + reg_data = upper_32_bits(ucode->mc_addr) & + REG_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI); + WREG32(mmCP_CPC_IC_BASE_HI, reg_data); + + return 0; +} + +int cz_smu_start(struct amdgpu_device *adev) +{ + int ret = 0; + + uint32_t fw_to_check = UCODE_ID_RLC_G_MASK | + UCODE_ID_SDMA0_MASK | + UCODE_ID_SDMA1_MASK | + UCODE_ID_CP_CE_MASK | + UCODE_ID_CP_ME_MASK | + UCODE_ID_CP_PFP_MASK | + UCODE_ID_CP_MEC_JT1_MASK | + UCODE_ID_CP_MEC_JT2_MASK; + + cz_smu_request_load_fw(adev); + ret = cz_smu_check_fw_load_finish(adev, fw_to_check); + if (ret) + return ret; + + /* manually load MEC firmware for CZ */ + if (adev->asic_type == CHIP_CARRIZO) { + ret = cz_load_mec_firmware(adev); + if (ret) { + dev_err(adev->dev, "(%d) Mec Firmware load failed\n", ret); + return ret; + } + } + + /* setup fw load flag */ + adev->smu.fw_flags = AMDGPU_SDMA0_UCODE_LOADED | + AMDGPU_SDMA1_UCODE_LOADED | + AMDGPU_CPCE_UCODE_LOADED | + AMDGPU_CPPFP_UCODE_LOADED | + AMDGPU_CPME_UCODE_LOADED | + AMDGPU_CPMEC1_UCODE_LOADED | + AMDGPU_CPMEC2_UCODE_LOADED | + AMDGPU_CPRLC_UCODE_LOADED; + + return ret; +} + +static uint32_t cz_convert_fw_type(uint32_t fw_type) +{ + enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM; + + switch (fw_type) { + case UCODE_ID_SDMA0: + result = AMDGPU_UCODE_ID_SDMA0; + break; + case UCODE_ID_SDMA1: + result = AMDGPU_UCODE_ID_SDMA1; + break; + case UCODE_ID_CP_CE: + result = AMDGPU_UCODE_ID_CP_CE; + break; + case UCODE_ID_CP_PFP: + result = AMDGPU_UCODE_ID_CP_PFP; + break; + case UCODE_ID_CP_ME: + result = AMDGPU_UCODE_ID_CP_ME; + break; + case UCODE_ID_CP_MEC_JT1: + case UCODE_ID_CP_MEC_JT2: + result = AMDGPU_UCODE_ID_CP_MEC1; + break; + case UCODE_ID_RLC_G: + result = AMDGPU_UCODE_ID_RLC_G; + break; + default: + DRM_ERROR("UCode type is out of range!"); + } + + return result; +} + +static uint8_t cz_smu_translate_firmware_enum_to_arg( + enum cz_scratch_entry firmware_enum) +{ + uint8_t ret = 0; + + switch (firmware_enum) { + case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0: + ret = UCODE_ID_SDMA0; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1: + ret = UCODE_ID_SDMA1; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE: + ret = UCODE_ID_CP_CE; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP: + ret = UCODE_ID_CP_PFP; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME: + ret = UCODE_ID_CP_ME; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1: + ret = UCODE_ID_CP_MEC_JT1; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2: + ret = UCODE_ID_CP_MEC_JT2; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG: + ret = UCODE_ID_GMCON_RENG; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G: + ret = UCODE_ID_RLC_G; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH: + ret = UCODE_ID_RLC_SCRATCH; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM: + ret = UCODE_ID_RLC_SRM_ARAM; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM: + ret = UCODE_ID_RLC_SRM_DRAM; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM: + ret = UCODE_ID_DMCU_ERAM; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM: + ret = UCODE_ID_DMCU_IRAM; + break; + case CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING: + ret = TASK_ARG_INIT_MM_PWR_LOG; + break; + case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT: + case CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING: + case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS: + case CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT: + case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START: + case CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS: + ret = TASK_ARG_REG_MMIO; + break; + case CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE: + ret = TASK_ARG_INIT_CLK_TABLE; + break; + } + + return ret; +} + +static int cz_smu_populate_single_firmware_entry(struct amdgpu_device *adev, + enum cz_scratch_entry firmware_enum, + struct cz_buffer_entry *entry) +{ + uint64_t gpu_addr; + uint32_t data_size; + uint8_t ucode_id = cz_smu_translate_firmware_enum_to_arg(firmware_enum); + enum AMDGPU_UCODE_ID id = cz_convert_fw_type(ucode_id); + struct amdgpu_firmware_info *ucode = &adev->firmware.ucode[id]; + const struct gfx_firmware_header_v1_0 *header; + + if (ucode->fw == NULL) + return -EINVAL; + + gpu_addr = ucode->mc_addr; + header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; + data_size = le32_to_cpu(header->header.ucode_size_bytes); + + if ((firmware_enum == CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1) || + (firmware_enum == CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2)) { + gpu_addr += le32_to_cpu(header->jt_offset) << 2; + data_size = le32_to_cpu(header->jt_size) << 2; + } + + entry->mc_addr_low = lower_32_bits(gpu_addr); + entry->mc_addr_high = upper_32_bits(gpu_addr); + entry->data_size = data_size; + entry->firmware_ID = firmware_enum; + + return 0; +} + +static int cz_smu_populate_single_scratch_entry(struct amdgpu_device *adev, + enum cz_scratch_entry scratch_type, + uint32_t size_in_byte, + struct cz_buffer_entry *entry) +{ + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + uint64_t mc_addr = (((uint64_t) priv->smu_buffer.mc_addr_high) << 32) | + priv->smu_buffer.mc_addr_low; + mc_addr += size_in_byte; + + priv->smu_buffer_used_bytes += size_in_byte; + entry->data_size = size_in_byte; + entry->kaddr = priv->smu_buffer.kaddr + priv->smu_buffer_used_bytes; + entry->mc_addr_low = lower_32_bits(mc_addr); + entry->mc_addr_high = upper_32_bits(mc_addr); + entry->firmware_ID = scratch_type; + + return 0; +} + +static int cz_smu_populate_single_ucode_load_task(struct amdgpu_device *adev, + enum cz_scratch_entry firmware_enum, + bool is_last) +{ + uint8_t i; + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr; + struct SMU_Task *task = &toc->tasks[priv->toc_entry_used_count++]; + + task->type = TASK_TYPE_UCODE_LOAD; + task->arg = cz_smu_translate_firmware_enum_to_arg(firmware_enum); + task->next = is_last ? END_OF_TASK_LIST : priv->toc_entry_used_count; + + for (i = 0; i < priv->driver_buffer_length; i++) + if (priv->driver_buffer[i].firmware_ID == firmware_enum) + break; + + if (i >= priv->driver_buffer_length) { + dev_err(adev->dev, "Invalid Firmware Type\n"); + return -EINVAL; + } + + task->addr.low = priv->driver_buffer[i].mc_addr_low; + task->addr.high = priv->driver_buffer[i].mc_addr_high; + task->size_bytes = priv->driver_buffer[i].data_size; + + return 0; +} + +static int cz_smu_populate_single_scratch_task(struct amdgpu_device *adev, + enum cz_scratch_entry firmware_enum, + uint8_t type, bool is_last) +{ + uint8_t i; + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr; + struct SMU_Task *task = &toc->tasks[priv->toc_entry_used_count++]; + + task->type = type; + task->arg = cz_smu_translate_firmware_enum_to_arg(firmware_enum); + task->next = is_last ? END_OF_TASK_LIST : priv->toc_entry_used_count; + + for (i = 0; i < priv->scratch_buffer_length; i++) + if (priv->scratch_buffer[i].firmware_ID == firmware_enum) + break; + + if (i >= priv->scratch_buffer_length) { + dev_err(adev->dev, "Invalid Firmware Type\n"); + return -EINVAL; + } + + task->addr.low = priv->scratch_buffer[i].mc_addr_low; + task->addr.high = priv->scratch_buffer[i].mc_addr_high; + task->size_bytes = priv->scratch_buffer[i].data_size; + + if (CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS == firmware_enum) { + struct cz_ih_meta_data *pIHReg_restore = + (struct cz_ih_meta_data *)priv->scratch_buffer[i].kaddr; + pIHReg_restore->command = + METADATA_CMD_MODE0 | METADATA_PERFORM_ON_LOAD; + } + + return 0; +} + +static int cz_smu_construct_toc_for_rlc_aram_save(struct amdgpu_device *adev) +{ + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + priv->toc_entry_aram = priv->toc_entry_used_count; + cz_smu_populate_single_scratch_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, + TASK_TYPE_UCODE_SAVE, true); + + return 0; +} + +static int cz_smu_construct_toc_for_vddgfx_enter(struct amdgpu_device *adev) +{ + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr; + + toc->JobList[JOB_GFX_SAVE] = (uint8_t)priv->toc_entry_used_count; + cz_smu_populate_single_scratch_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, + TASK_TYPE_UCODE_SAVE, false); + cz_smu_populate_single_scratch_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, + TASK_TYPE_UCODE_SAVE, true); + + return 0; +} + +static int cz_smu_construct_toc_for_vddgfx_exit(struct amdgpu_device *adev) +{ + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr; + + toc->JobList[JOB_GFX_RESTORE] = (uint8_t)priv->toc_entry_used_count; + + /* populate ucode */ + if (adev->firmware.smu_load) { + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false); + } + + /* populate scratch */ + cz_smu_populate_single_scratch_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, + TASK_TYPE_UCODE_LOAD, false); + cz_smu_populate_single_scratch_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, + TASK_TYPE_UCODE_LOAD, false); + cz_smu_populate_single_scratch_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, + TASK_TYPE_UCODE_LOAD, true); + + return 0; +} + +static int cz_smu_construct_toc_for_power_profiling(struct amdgpu_device *adev) +{ + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + + priv->toc_entry_power_profiling_index = priv->toc_entry_used_count; + + cz_smu_populate_single_scratch_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING, + TASK_TYPE_INITIALIZE, true); + return 0; +} + +static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev) +{ + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + + priv->toc_entry_initialize_index = priv->toc_entry_used_count; + + if (adev->firmware.smu_load) { + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true); + } + + return 0; +} + +static int cz_smu_construct_toc_for_clock_table(struct amdgpu_device *adev) +{ + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + + priv->toc_entry_clock_table = priv->toc_entry_used_count; + + cz_smu_populate_single_scratch_task(adev, + CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE, + TASK_TYPE_INITIALIZE, true); + + return 0; +} + +static int cz_smu_initialize_toc_empty_job_list(struct amdgpu_device *adev) +{ + int i; + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr; + + for (i = 0; i < NUM_JOBLIST_ENTRIES; i++) + toc->JobList[i] = (uint8_t)IGNORE_JOB; + + return 0; +} + +/* + * cz smu uninitialization + */ +int cz_smu_fini(struct amdgpu_device *adev) +{ + amdgpu_bo_unref(&adev->smu.toc_buf); + amdgpu_bo_unref(&adev->smu.smu_buf); + kfree(adev->smu.priv); + adev->smu.priv = NULL; + if (adev->firmware.smu_load) + amdgpu_ucode_fini_bo(adev); + + return 0; +} + +int cz_smu_download_pptable(struct amdgpu_device *adev, void **table) +{ + uint8_t i; + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + + for (i = 0; i < priv->scratch_buffer_length; i++) + if (priv->scratch_buffer[i].firmware_ID == + CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE) + break; + + if (i >= priv->scratch_buffer_length) { + dev_err(adev->dev, "Invalid Scratch Type\n"); + return -EINVAL; + } + + *table = (struct SMU8_Fusion_ClkTable *)priv->scratch_buffer[i].kaddr; + + /* prepare buffer for pptable */ + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetClkTableAddrHi, + priv->scratch_buffer[i].mc_addr_high); + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetClkTableAddrLo, + priv->scratch_buffer[i].mc_addr_low); + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_ExecuteJob, + priv->toc_entry_clock_table); + + /* actual downloading */ + cz_send_msg_to_smc(adev, PPSMC_MSG_ClkTableXferToDram); + + return 0; +} + +int cz_smu_upload_pptable(struct amdgpu_device *adev) +{ + uint8_t i; + struct cz_smu_private_data *priv = cz_smu_get_priv(adev); + + for (i = 0; i < priv->scratch_buffer_length; i++) + if (priv->scratch_buffer[i].firmware_ID == + CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE) + break; + + if (i >= priv->scratch_buffer_length) { + dev_err(adev->dev, "Invalid Scratch Type\n"); + return -EINVAL; + } + + /* prepare SMU */ + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetClkTableAddrHi, + priv->scratch_buffer[i].mc_addr_high); + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetClkTableAddrLo, + priv->scratch_buffer[i].mc_addr_low); + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_ExecuteJob, + priv->toc_entry_clock_table); + + /* actual uploading */ + cz_send_msg_to_smc(adev, PPSMC_MSG_ClkTableXferToSmu); + + return 0; +} + +/* + * cz smumgr functions initialization + */ +static const struct amdgpu_smumgr_funcs cz_smumgr_funcs = { + .check_fw_load_finish = cz_smu_check_finished, + .request_smu_load_fw = NULL, + .request_smu_specific_fw = NULL, +}; + +/* + * cz smu initialization + */ +int cz_smu_init(struct amdgpu_device *adev) +{ + int ret = -EINVAL; + uint64_t mc_addr = 0; + struct amdgpu_bo **toc_buf = &adev->smu.toc_buf; + struct amdgpu_bo **smu_buf = &adev->smu.smu_buf; + void *toc_buf_ptr = NULL; + void *smu_buf_ptr = NULL; + + struct cz_smu_private_data *priv = + kzalloc(sizeof(struct cz_smu_private_data), GFP_KERNEL); + if (priv == NULL) + return -ENOMEM; + + /* allocate firmware buffers */ + if (adev->firmware.smu_load) + amdgpu_ucode_init_bo(adev); + + adev->smu.priv = priv; + adev->smu.fw_flags = 0; + priv->toc_buffer.data_size = 4096; + + priv->smu_buffer.data_size = + ALIGN(UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 32) + + ALIGN(UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, 32) + + ALIGN(UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, 32) + + ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) + + ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32); + + /* prepare toc buffer and smu buffer: + * 1. create amdgpu_bo for toc buffer and smu buffer + * 2. pin mc address + * 3. map kernel virtual address + */ + ret = amdgpu_bo_create(adev, priv->toc_buffer.data_size, PAGE_SIZE, + true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, toc_buf); + + if (ret) { + dev_err(adev->dev, "(%d) SMC TOC buffer allocation failed\n", ret); + return ret; + } + + ret = amdgpu_bo_create(adev, priv->smu_buffer.data_size, PAGE_SIZE, + true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, smu_buf); + + if (ret) { + dev_err(adev->dev, "(%d) SMC Internal buffer allocation failed\n", ret); + return ret; + } + + /* toc buffer reserve/pin/map */ + ret = amdgpu_bo_reserve(adev->smu.toc_buf, false); + if (ret) { + amdgpu_bo_unref(&adev->smu.toc_buf); + dev_err(adev->dev, "(%d) SMC TOC buffer reserve failed\n", ret); + return ret; + } + + ret = amdgpu_bo_pin(adev->smu.toc_buf, AMDGPU_GEM_DOMAIN_GTT, &mc_addr); + if (ret) { + amdgpu_bo_unreserve(adev->smu.toc_buf); + amdgpu_bo_unref(&adev->smu.toc_buf); + dev_err(adev->dev, "(%d) SMC TOC buffer pin failed\n", ret); + return ret; + } + + ret = amdgpu_bo_kmap(*toc_buf, &toc_buf_ptr); + if (ret) + goto smu_init_failed; + + amdgpu_bo_unreserve(adev->smu.toc_buf); + + priv->toc_buffer.mc_addr_low = lower_32_bits(mc_addr); + priv->toc_buffer.mc_addr_high = upper_32_bits(mc_addr); + priv->toc_buffer.kaddr = toc_buf_ptr; + + /* smu buffer reserve/pin/map */ + ret = amdgpu_bo_reserve(adev->smu.smu_buf, false); + if (ret) { + amdgpu_bo_unref(&adev->smu.smu_buf); + dev_err(adev->dev, "(%d) SMC Internal buffer reserve failed\n", ret); + return ret; + } + + ret = amdgpu_bo_pin(adev->smu.smu_buf, AMDGPU_GEM_DOMAIN_GTT, &mc_addr); + if (ret) { + amdgpu_bo_unreserve(adev->smu.smu_buf); + amdgpu_bo_unref(&adev->smu.smu_buf); + dev_err(adev->dev, "(%d) SMC Internal buffer pin failed\n", ret); + return ret; + } + + ret = amdgpu_bo_kmap(*smu_buf, &smu_buf_ptr); + if (ret) + goto smu_init_failed; + + amdgpu_bo_unreserve(adev->smu.smu_buf); + + priv->smu_buffer.mc_addr_low = lower_32_bits(mc_addr); + priv->smu_buffer.mc_addr_high = upper_32_bits(mc_addr); + priv->smu_buffer.kaddr = smu_buf_ptr; + + if (adev->firmware.smu_load) { + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + } + + if (cz_smu_populate_single_scratch_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, + UCODE_ID_RLC_SCRATCH_SIZE_BYTE, + &priv->scratch_buffer[priv->scratch_buffer_length++])) + goto smu_init_failed; + if (cz_smu_populate_single_scratch_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, + UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, + &priv->scratch_buffer[priv->scratch_buffer_length++])) + goto smu_init_failed; + if (cz_smu_populate_single_scratch_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, + UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, + &priv->scratch_buffer[priv->scratch_buffer_length++])) + goto smu_init_failed; + if (cz_smu_populate_single_scratch_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING, + sizeof(struct SMU8_MultimediaPowerLogData), + &priv->scratch_buffer[priv->scratch_buffer_length++])) + goto smu_init_failed; + if (cz_smu_populate_single_scratch_entry(adev, + CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE, + sizeof(struct SMU8_Fusion_ClkTable), + &priv->scratch_buffer[priv->scratch_buffer_length++])) + goto smu_init_failed; + + cz_smu_initialize_toc_empty_job_list(adev); + cz_smu_construct_toc_for_rlc_aram_save(adev); + cz_smu_construct_toc_for_vddgfx_enter(adev); + cz_smu_construct_toc_for_vddgfx_exit(adev); + cz_smu_construct_toc_for_power_profiling(adev); + cz_smu_construct_toc_for_bootup(adev); + cz_smu_construct_toc_for_clock_table(adev); + /* init the smumgr functions */ + adev->smu.smumgr_funcs = &cz_smumgr_funcs; + + return 0; + +smu_init_failed: + amdgpu_bo_unref(toc_buf); + amdgpu_bo_unref(smu_buf); + + return ret; +} diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h b/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h new file mode 100644 index 000000000000..924d355b4e2c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h @@ -0,0 +1,94 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __CZ_SMC_H__ +#define __CZ_SMC_H__ + +#define MAX_NUM_FIRMWARE 8 +#define MAX_NUM_SCRATCH 11 +#define CZ_SCRATCH_SIZE_NONGFX_CLOCKGATING 1024 +#define CZ_SCRATCH_SIZE_NONGFX_GOLDENSETTING 2048 +#define CZ_SCRATCH_SIZE_SDMA_METADATA 1024 +#define CZ_SCRATCH_SIZE_IH ((2*256+1)*4) + +enum cz_scratch_entry { + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0 = 0, + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, + CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, + CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, + CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM, + CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM, + CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING, + CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT, + CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING, + CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS, + CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT, + CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START, + CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS, + CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE +}; + +struct cz_buffer_entry { + uint32_t data_size; + uint32_t mc_addr_low; + uint32_t mc_addr_high; + void *kaddr; + enum cz_scratch_entry firmware_ID; +}; + +struct cz_register_index_data_pair { + uint32_t offset; + uint32_t value; +}; + +struct cz_ih_meta_data { + uint32_t command; + struct cz_register_index_data_pair register_index_value_pair[1]; +}; + +struct cz_smu_private_data { + uint8_t driver_buffer_length; + uint8_t scratch_buffer_length; + uint16_t toc_entry_used_count; + uint16_t toc_entry_initialize_index; + uint16_t toc_entry_power_profiling_index; + uint16_t toc_entry_aram; + uint16_t toc_entry_ih_register_restore_task_index; + uint16_t toc_entry_clock_table; + uint16_t ih_register_restore_task_size; + uint16_t smu_buffer_used_bytes; + + struct cz_buffer_entry toc_buffer; + struct cz_buffer_entry smu_buffer; + struct cz_buffer_entry driver_buffer[MAX_NUM_FIRMWARE]; + struct cz_buffer_entry scratch_buffer[MAX_NUM_SCRATCH]; +}; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c new file mode 100644 index 000000000000..d412291ed70e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -0,0 +1,3871 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_pm.h" +#include "amdgpu_i2c.h" +#include "vid.h" +#include "atom.h" +#include "amdgpu_atombios.h" +#include "atombios_crtc.h" +#include "atombios_encoders.h" +#include "amdgpu_pll.h" +#include "amdgpu_connectors.h" + +#include "dce/dce_10_0_d.h" +#include "dce/dce_10_0_sh_mask.h" +#include "dce/dce_10_0_enum.h" +#include "oss/oss_3_0_d.h" +#include "oss/oss_3_0_sh_mask.h" +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" + +static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); +static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); + +static const u32 crtc_offsets[] = +{ + CRTC0_REGISTER_OFFSET, + CRTC1_REGISTER_OFFSET, + CRTC2_REGISTER_OFFSET, + CRTC3_REGISTER_OFFSET, + CRTC4_REGISTER_OFFSET, + CRTC5_REGISTER_OFFSET, + CRTC6_REGISTER_OFFSET +}; + +static const u32 hpd_offsets[] = +{ + HPD0_REGISTER_OFFSET, + HPD1_REGISTER_OFFSET, + HPD2_REGISTER_OFFSET, + HPD3_REGISTER_OFFSET, + HPD4_REGISTER_OFFSET, + HPD5_REGISTER_OFFSET +}; + +static const uint32_t dig_offsets[] = { + DIG0_REGISTER_OFFSET, + DIG1_REGISTER_OFFSET, + DIG2_REGISTER_OFFSET, + DIG3_REGISTER_OFFSET, + DIG4_REGISTER_OFFSET, + DIG5_REGISTER_OFFSET, + DIG6_REGISTER_OFFSET +}; + +static const struct { + uint32_t reg; + uint32_t vblank; + uint32_t vline; + uint32_t hpd; + +} interrupt_status_offsets[] = { { + .reg = mmDISP_INTERRUPT_STATUS, + .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK +} }; + +static const u32 golden_settings_tonga_a11[] = +{ + mmDCI_CLK_CNTL, 0x00000080, 0x00000000, + mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, + mmFBC_MISC, 0x1f311fff, 0x12300000, + mmHDMI_CONTROL, 0x31000111, 0x00000011, +}; + +static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_TONGA: + amdgpu_program_register_sequence(adev, + golden_settings_tonga_a11, + (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + break; + default: + break; + } +} + +static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, + u32 block_offset, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); + r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); + spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + + return r; +} + +static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, + u32 block_offset, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); + spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); +} + +static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc) +{ + if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & + CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) + return true; + else + return false; +} + +static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc) +{ + u32 pos1, pos2; + + pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); + pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); + + if (pos1 != pos2) + return true; + else + return false; +} + +/** + * dce_v10_0_vblank_wait - vblank wait asic callback. + * + * @adev: amdgpu_device pointer + * @crtc: crtc to wait for vblank on + * + * Wait for vblank on the requested crtc (evergreen+). + */ +static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc) +{ + unsigned i = 0; + + if (crtc >= adev->mode_info.num_crtc) + return; + + if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) + return; + + /* depending on when we hit vblank, we may be close to active; if so, + * wait for another frame. + */ + while (dce_v10_0_is_in_vblank(adev, crtc)) { + if (i++ % 100 == 0) { + if (!dce_v10_0_is_counter_moving(adev, crtc)) + break; + } + } + + while (!dce_v10_0_is_in_vblank(adev, crtc)) { + if (i++ % 100 == 0) { + if (!dce_v10_0_is_counter_moving(adev, crtc)) + break; + } + } +} + +static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) +{ + if (crtc >= adev->mode_info.num_crtc) + return 0; + else + return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); +} + +/** + * dce_v10_0_page_flip - pageflip callback. + * + * @adev: amdgpu_device pointer + * @crtc_id: crtc to cleanup pageflip on + * @crtc_base: new address of the crtc (GPU MC address) + * + * Does the actual pageflip (evergreen+). + * During vblank we take the crtc lock and wait for the update_pending + * bit to go high, when it does, we release the lock, and allow the + * double buffered update to take place. + * Returns the current update pending status. + */ +static void dce_v10_0_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base) +{ + struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); + int i; + + /* Lock the graphics update lock */ + tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); + WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); + + /* update the scanout addresses */ + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(crtc_base)); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + lower_32_bits(crtc_base)); + + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(crtc_base)); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + lower_32_bits(crtc_base)); + + /* Wait for update_pending to go high. */ + for (i = 0; i < adev->usec_timeout; i++) { + if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & + GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) + break; + udelay(1); + } + DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); + + /* Unlock the lock, so double-buffering can take place inside vblank */ + tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); + WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); +} + +static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, + u32 *vbl, u32 *position) +{ + if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) + return -EINVAL; + + *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); + *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); + + return 0; +} + +/** + * dce_v10_0_hpd_sense - hpd sense callback. + * + * @adev: amdgpu_device pointer + * @hpd: hpd (hotplug detect) pin + * + * Checks if a digital monitor is connected (evergreen+). + * Returns true if connected, false if not connected. + */ +static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + int idx; + bool connected = false; + + switch (hpd) { + case AMDGPU_HPD_1: + idx = 0; + break; + case AMDGPU_HPD_2: + idx = 1; + break; + case AMDGPU_HPD_3: + idx = 2; + break; + case AMDGPU_HPD_4: + idx = 3; + break; + case AMDGPU_HPD_5: + idx = 4; + break; + case AMDGPU_HPD_6: + idx = 5; + break; + default: + return connected; + } + + if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & + DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) + connected = true; + + return connected; +} + +/** + * dce_v10_0_hpd_set_polarity - hpd set polarity callback. + * + * @adev: amdgpu_device pointer + * @hpd: hpd (hotplug detect) pin + * + * Set the polarity of the hpd pin (evergreen+). + */ +static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + u32 tmp; + bool connected = dce_v10_0_hpd_sense(adev, hpd); + int idx; + + switch (hpd) { + case AMDGPU_HPD_1: + idx = 0; + break; + case AMDGPU_HPD_2: + idx = 1; + break; + case AMDGPU_HPD_3: + idx = 2; + break; + case AMDGPU_HPD_4: + idx = 3; + break; + case AMDGPU_HPD_5: + idx = 4; + break; + case AMDGPU_HPD_6: + idx = 5; + break; + default: + return; + } + + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); + if (connected) + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); + else + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); +} + +/** + * dce_v10_0_hpd_init - hpd setup callback. + * + * @adev: amdgpu_device pointer + * + * Setup the hpd pins used by the card (evergreen+). + * Enable the pin, set the polarity, and enable the hpd interrupts. + */ +static void dce_v10_0_hpd_init(struct amdgpu_device *adev) +{ + struct drm_device *dev = adev->ddev; + struct drm_connector *connector; + u32 tmp; + int idx; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || + connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { + /* don't try to enable hpd on eDP or LVDS avoid breaking the + * aux dp channel on imac and help (but not completely fix) + * https://bugzilla.redhat.com/show_bug.cgi?id=726143 + * also avoid interrupt storms during dpms. + */ + continue; + } + + switch (amdgpu_connector->hpd.hpd) { + case AMDGPU_HPD_1: + idx = 0; + break; + case AMDGPU_HPD_2: + idx = 1; + break; + case AMDGPU_HPD_3: + idx = 2; + break; + case AMDGPU_HPD_4: + idx = 3; + break; + case AMDGPU_HPD_5: + idx = 4; + break; + case AMDGPU_HPD_6: + idx = 5; + break; + default: + continue; + } + + tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); + tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); + WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); + + tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); + tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, + DC_HPD_CONNECT_INT_DELAY, + AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); + tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, + DC_HPD_DISCONNECT_INT_DELAY, + AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); + WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); + + dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); + amdgpu_irq_get(adev, &adev->hpd_irq, + amdgpu_connector->hpd.hpd); + } +} + +/** + * dce_v10_0_hpd_fini - hpd tear down callback. + * + * @adev: amdgpu_device pointer + * + * Tear down the hpd pins used by the card (evergreen+). + * Disable the hpd interrupts. + */ +static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) +{ + struct drm_device *dev = adev->ddev; + struct drm_connector *connector; + u32 tmp; + int idx; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + switch (amdgpu_connector->hpd.hpd) { + case AMDGPU_HPD_1: + idx = 0; + break; + case AMDGPU_HPD_2: + idx = 1; + break; + case AMDGPU_HPD_3: + idx = 2; + break; + case AMDGPU_HPD_4: + idx = 3; + break; + case AMDGPU_HPD_5: + idx = 4; + break; + case AMDGPU_HPD_6: + idx = 5; + break; + default: + continue; + } + + tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); + tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); + WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); + + amdgpu_irq_put(adev, &adev->hpd_irq, + amdgpu_connector->hpd.hpd); + } +} + +static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) +{ + return mmDC_GPIO_HPD_A; +} + +static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) +{ + u32 crtc_hung = 0; + u32 crtc_status[6]; + u32 i, j, tmp; + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { + crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); + crtc_hung |= (1 << i); + } + } + + for (j = 0; j < 10; j++) { + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (crtc_hung & (1 << i)) { + tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); + if (tmp != crtc_status[i]) + crtc_hung &= ~(1 << i); + } + } + if (crtc_hung == 0) + return false; + udelay(100); + } + + return true; +} + +static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save) +{ + u32 crtc_enabled, tmp; + int i; + + save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); + save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); + + /* disable VGA render */ + tmp = RREG32(mmVGA_RENDER_CONTROL); + tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); + WREG32(mmVGA_RENDER_CONTROL, tmp); + + /* blank the display controllers */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), + CRTC_CONTROL, CRTC_MASTER_EN); + if (crtc_enabled) { +#if 0 + u32 frame_count; + int j; + + save->crtc_enabled[i] = true; + tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { + amdgpu_display_vblank_wait(adev, i); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); + WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); + } + /* wait for the next frame */ + frame_count = amdgpu_display_vblank_get_counter(adev, i); + for (j = 0; j < adev->usec_timeout; j++) { + if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) + break; + udelay(1); + } + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { + tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); + WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); + } + tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { + tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); + WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); + } +#else + /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); + tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); + WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); + save->crtc_enabled[i] = false; + /* ***** */ +#endif + } else { + save->crtc_enabled[i] = false; + } + } +} + +static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save) +{ + u32 tmp, frame_count; + int i, j; + + /* update crtc base addresses */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], + upper_32_bits(adev->mc.vram_start)); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], + upper_32_bits(adev->mc.vram_start)); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], + (u32)adev->mc.vram_start); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], + (u32)adev->mc.vram_start); + + if (save->crtc_enabled[i]) { + tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { + tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); + WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); + } + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { + tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); + WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); + } + tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { + tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); + WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); + } + for (j = 0; j < adev->usec_timeout; j++) { + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) + break; + udelay(1); + } + tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); + tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); + /* wait for the next frame */ + frame_count = amdgpu_display_vblank_get_counter(adev, i); + for (j = 0; j < adev->usec_timeout; j++) { + if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) + break; + udelay(1); + } + } + } + + WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); + WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); + + /* Unlock vga access */ + WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); + mdelay(1); + WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); +} + +static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, + bool render) +{ + u32 tmp; + + /* Lockout access through VGA aperture*/ + tmp = RREG32(mmVGA_HDP_CONTROL); + if (render) + tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); + else + tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); + WREG32(mmVGA_HDP_CONTROL, tmp); + + /* disable VGA render */ + tmp = RREG32(mmVGA_RENDER_CONTROL); + if (render) + tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); + else + tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); + WREG32(mmVGA_RENDER_CONTROL, tmp); +} + +static void dce_v10_0_program_fmt(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + int bpc = 0; + u32 tmp = 0; + enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; + + if (connector) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + bpc = amdgpu_connector_get_monitor_bpc(connector); + dither = amdgpu_connector->dither; + } + + /* LVDS/eDP FMT is set up by atom */ + if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) + return; + + /* not needed for analog */ + if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || + (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) + return; + + if (bpc == 0) + return; + + switch (bpc) { + case 6: + if (dither == AMDGPU_FMT_DITHER_ENABLE) { + /* XXX sort out optimal dither settings */ + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); + } else { + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); + } + break; + case 8: + if (dither == AMDGPU_FMT_DITHER_ENABLE) { + /* XXX sort out optimal dither settings */ + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); + } else { + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); + } + break; + case 10: + if (dither == AMDGPU_FMT_DITHER_ENABLE) { + /* XXX sort out optimal dither settings */ + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); + } else { + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); + } + break; + default: + /* not needed */ + break; + } + + WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); +} + + +/* display watermark setup */ +/** + * dce_v10_0_line_buffer_adjust - Set up the line buffer + * + * @adev: amdgpu_device pointer + * @amdgpu_crtc: the selected display controller + * @mode: the current display mode on the selected display + * controller + * + * Setup up the line buffer allocation for + * the selected display controller (CIK). + * Returns the line buffer size in pixels. + */ +static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, + struct amdgpu_crtc *amdgpu_crtc, + struct drm_display_mode *mode) +{ + u32 tmp, buffer_alloc, i, mem_cfg; + u32 pipe_offset = amdgpu_crtc->crtc_id; + /* + * Line Buffer Setup + * There are 6 line buffers, one for each display controllers. + * There are 3 partitions per LB. Select the number of partitions + * to enable based on the display width. For display widths larger + * than 4096, you need use to use 2 display controllers and combine + * them using the stereo blender. + */ + if (amdgpu_crtc->base.enabled && mode) { + if (mode->crtc_hdisplay < 1920) { + mem_cfg = 1; + buffer_alloc = 2; + } else if (mode->crtc_hdisplay < 2560) { + mem_cfg = 2; + buffer_alloc = 2; + } else if (mode->crtc_hdisplay < 4096) { + mem_cfg = 0; + buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; + } else { + DRM_DEBUG_KMS("Mode too big for LB!\n"); + mem_cfg = 0; + buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; + } + } else { + mem_cfg = 1; + buffer_alloc = 0; + } + + tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); + WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); + tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); + WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); + if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) + break; + udelay(1); + } + + if (amdgpu_crtc->base.enabled && mode) { + switch (mem_cfg) { + case 0: + default: + return 4096 * 2; + case 1: + return 1920 * 2; + case 2: + return 2560 * 2; + } + } + + /* controller not enabled, so no lb used */ + return 0; +} + +/** + * cik_get_number_of_dram_channels - get the number of dram channels + * + * @adev: amdgpu_device pointer + * + * Look up the number of video ram channels (CIK). + * Used for display watermark bandwidth calculations + * Returns the number of dram channels + */ +static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmMC_SHARED_CHMAP); + + switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { + case 0: + default: + return 1; + case 1: + return 2; + case 2: + return 4; + case 3: + return 8; + case 4: + return 3; + case 5: + return 6; + case 6: + return 10; + case 7: + return 12; + case 8: + return 16; + } +} + +struct dce10_wm_params { + u32 dram_channels; /* number of dram channels */ + u32 yclk; /* bandwidth per dram data pin in kHz */ + u32 sclk; /* engine clock in kHz */ + u32 disp_clk; /* display clock in kHz */ + u32 src_width; /* viewport width */ + u32 active_time; /* active display time in ns */ + u32 blank_time; /* blank time in ns */ + bool interlaced; /* mode is interlaced */ + fixed20_12 vsc; /* vertical scale ratio */ + u32 num_heads; /* number of active crtcs */ + u32 bytes_per_pixel; /* bytes per pixel display + overlay */ + u32 lb_size; /* line buffer allocated to pipe */ + u32 vtaps; /* vertical scaler taps */ +}; + +/** + * dce_v10_0_dram_bandwidth - get the dram bandwidth + * + * @wm: watermark calculation data + * + * Calculate the raw dram bandwidth (CIK). + * Used for display watermark bandwidth calculations + * Returns the dram bandwidth in MBytes/s + */ +static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) +{ + /* Calculate raw DRAM Bandwidth */ + fixed20_12 dram_efficiency; /* 0.7 */ + fixed20_12 yclk, dram_channels, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + yclk.full = dfixed_const(wm->yclk); + yclk.full = dfixed_div(yclk, a); + dram_channels.full = dfixed_const(wm->dram_channels * 4); + a.full = dfixed_const(10); + dram_efficiency.full = dfixed_const(7); + dram_efficiency.full = dfixed_div(dram_efficiency, a); + bandwidth.full = dfixed_mul(dram_channels, yclk); + bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display + * + * @wm: watermark calculation data + * + * Calculate the dram bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the dram bandwidth for display in MBytes/s + */ +static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) +{ + /* Calculate DRAM Bandwidth and the part allocated to display. */ + fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ + fixed20_12 yclk, dram_channels, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + yclk.full = dfixed_const(wm->yclk); + yclk.full = dfixed_div(yclk, a); + dram_channels.full = dfixed_const(wm->dram_channels * 4); + a.full = dfixed_const(10); + disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ + disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); + bandwidth.full = dfixed_mul(dram_channels, yclk); + bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v10_0_data_return_bandwidth - get the data return bandwidth + * + * @wm: watermark calculation data + * + * Calculate the data return bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the data return bandwidth in MBytes/s + */ +static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) +{ + /* Calculate the display Data return Bandwidth */ + fixed20_12 return_efficiency; /* 0.8 */ + fixed20_12 sclk, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + sclk.full = dfixed_const(wm->sclk); + sclk.full = dfixed_div(sclk, a); + a.full = dfixed_const(10); + return_efficiency.full = dfixed_const(8); + return_efficiency.full = dfixed_div(return_efficiency, a); + a.full = dfixed_const(32); + bandwidth.full = dfixed_mul(a, sclk); + bandwidth.full = dfixed_mul(bandwidth, return_efficiency); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth + * + * @wm: watermark calculation data + * + * Calculate the dmif bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the dmif bandwidth in MBytes/s + */ +static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) +{ + /* Calculate the DMIF Request Bandwidth */ + fixed20_12 disp_clk_request_efficiency; /* 0.8 */ + fixed20_12 disp_clk, bandwidth; + fixed20_12 a, b; + + a.full = dfixed_const(1000); + disp_clk.full = dfixed_const(wm->disp_clk); + disp_clk.full = dfixed_div(disp_clk, a); + a.full = dfixed_const(32); + b.full = dfixed_mul(a, disp_clk); + + a.full = dfixed_const(10); + disp_clk_request_efficiency.full = dfixed_const(8); + disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); + + bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v10_0_available_bandwidth - get the min available bandwidth + * + * @wm: watermark calculation data + * + * Calculate the min available bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the min available bandwidth in MBytes/s + */ +static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm) +{ + /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ + u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm); + u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm); + u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm); + + return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); +} + +/** + * dce_v10_0_average_bandwidth - get the average available bandwidth + * + * @wm: watermark calculation data + * + * Calculate the average available bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the average available bandwidth in MBytes/s + */ +static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm) +{ + /* Calculate the display mode Average Bandwidth + * DisplayMode should contain the source and destination dimensions, + * timing, etc. + */ + fixed20_12 bpp; + fixed20_12 line_time; + fixed20_12 src_width; + fixed20_12 bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + line_time.full = dfixed_const(wm->active_time + wm->blank_time); + line_time.full = dfixed_div(line_time, a); + bpp.full = dfixed_const(wm->bytes_per_pixel); + src_width.full = dfixed_const(wm->src_width); + bandwidth.full = dfixed_mul(src_width, bpp); + bandwidth.full = dfixed_mul(bandwidth, wm->vsc); + bandwidth.full = dfixed_div(bandwidth, line_time); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v10_0_latency_watermark - get the latency watermark + * + * @wm: watermark calculation data + * + * Calculate the latency watermark (CIK). + * Used for display watermark bandwidth calculations + * Returns the latency watermark in ns + */ +static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) +{ + /* First calculate the latency in ns */ + u32 mc_latency = 2000; /* 2000 ns. */ + u32 available_bandwidth = dce_v10_0_available_bandwidth(wm); + u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; + u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; + u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ + u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + + (wm->num_heads * cursor_line_pair_return_time); + u32 latency = mc_latency + other_heads_data_return_time + dc_latency; + u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; + u32 tmp, dmif_size = 12288; + fixed20_12 a, b, c; + + if (wm->num_heads == 0) + return 0; + + a.full = dfixed_const(2); + b.full = dfixed_const(1); + if ((wm->vsc.full > a.full) || + ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || + (wm->vtaps >= 5) || + ((wm->vsc.full >= a.full) && wm->interlaced)) + max_src_lines_per_dst_line = 4; + else + max_src_lines_per_dst_line = 2; + + a.full = dfixed_const(available_bandwidth); + b.full = dfixed_const(wm->num_heads); + a.full = dfixed_div(a, b); + + b.full = dfixed_const(mc_latency + 512); + c.full = dfixed_const(wm->disp_clk); + b.full = dfixed_div(b, c); + + c.full = dfixed_const(dmif_size); + b.full = dfixed_div(c, b); + + tmp = min(dfixed_trunc(a), dfixed_trunc(b)); + + b.full = dfixed_const(1000); + c.full = dfixed_const(wm->disp_clk); + b.full = dfixed_div(c, b); + c.full = dfixed_const(wm->bytes_per_pixel); + b.full = dfixed_mul(b, c); + + lb_fill_bw = min(tmp, dfixed_trunc(b)); + + a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); + b.full = dfixed_const(1000); + c.full = dfixed_const(lb_fill_bw); + b.full = dfixed_div(c, b); + a.full = dfixed_div(a, b); + line_fill_time = dfixed_trunc(a); + + if (line_fill_time < wm->active_time) + return latency; + else + return latency + (line_fill_time - wm->active_time); + +} + +/** + * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check + * average and available dram bandwidth + * + * @wm: watermark calculation data + * + * Check if the display average bandwidth fits in the display + * dram bandwidth (CIK). + * Used for display watermark bandwidth calculations + * Returns true if the display fits, false if not. + */ +static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) +{ + if (dce_v10_0_average_bandwidth(wm) <= + (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) + return true; + else + return false; +} + +/** + * dce_v10_0_average_bandwidth_vs_available_bandwidth - check + * average and available bandwidth + * + * @wm: watermark calculation data + * + * Check if the display average bandwidth fits in the display + * available bandwidth (CIK). + * Used for display watermark bandwidth calculations + * Returns true if the display fits, false if not. + */ +static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) +{ + if (dce_v10_0_average_bandwidth(wm) <= + (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) + return true; + else + return false; +} + +/** + * dce_v10_0_check_latency_hiding - check latency hiding + * + * @wm: watermark calculation data + * + * Check latency hiding (CIK). + * Used for display watermark bandwidth calculations + * Returns true if the display fits, false if not. + */ +static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm) +{ + u32 lb_partitions = wm->lb_size / wm->src_width; + u32 line_time = wm->active_time + wm->blank_time; + u32 latency_tolerant_lines; + u32 latency_hiding; + fixed20_12 a; + + a.full = dfixed_const(1); + if (wm->vsc.full > a.full) + latency_tolerant_lines = 1; + else { + if (lb_partitions <= (wm->vtaps + 1)) + latency_tolerant_lines = 1; + else + latency_tolerant_lines = 2; + } + + latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); + + if (dce_v10_0_latency_watermark(wm) <= latency_hiding) + return true; + else + return false; +} + +/** + * dce_v10_0_program_watermarks - program display watermarks + * + * @adev: amdgpu_device pointer + * @amdgpu_crtc: the selected display controller + * @lb_size: line buffer size + * @num_heads: number of display controllers in use + * + * Calculate and program the display watermarks for the + * selected display controller (CIK). + */ +static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, + struct amdgpu_crtc *amdgpu_crtc, + u32 lb_size, u32 num_heads) +{ + struct drm_display_mode *mode = &amdgpu_crtc->base.mode; + struct dce10_wm_params wm_low, wm_high; + u32 pixel_period; + u32 line_time = 0; + u32 latency_watermark_a = 0, latency_watermark_b = 0; + u32 tmp, wm_mask; + + if (amdgpu_crtc->base.enabled && num_heads && mode) { + pixel_period = 1000000 / (u32)mode->clock; + line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); + + /* watermark for high clocks */ + if (adev->pm.dpm_enabled) { + wm_high.yclk = + amdgpu_dpm_get_mclk(adev, false) * 10; + wm_high.sclk = + amdgpu_dpm_get_sclk(adev, false) * 10; + } else { + wm_high.yclk = adev->pm.current_mclk * 10; + wm_high.sclk = adev->pm.current_sclk * 10; + } + + wm_high.disp_clk = mode->clock; + wm_high.src_width = mode->crtc_hdisplay; + wm_high.active_time = mode->crtc_hdisplay * pixel_period; + wm_high.blank_time = line_time - wm_high.active_time; + wm_high.interlaced = false; + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + wm_high.interlaced = true; + wm_high.vsc = amdgpu_crtc->vsc; + wm_high.vtaps = 1; + if (amdgpu_crtc->rmx_type != RMX_OFF) + wm_high.vtaps = 2; + wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ + wm_high.lb_size = lb_size; + wm_high.dram_channels = cik_get_number_of_dram_channels(adev); + wm_high.num_heads = num_heads; + + /* set for high clocks */ + latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535); + + /* possibly force display priority to high */ + /* should really do this at mode validation time... */ + if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || + !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) || + !dce_v10_0_check_latency_hiding(&wm_high) || + (adev->mode_info.disp_priority == 2)) { + DRM_DEBUG_KMS("force priority to high\n"); + } + + /* watermark for low clocks */ + if (adev->pm.dpm_enabled) { + wm_low.yclk = + amdgpu_dpm_get_mclk(adev, true) * 10; + wm_low.sclk = + amdgpu_dpm_get_sclk(adev, true) * 10; + } else { + wm_low.yclk = adev->pm.current_mclk * 10; + wm_low.sclk = adev->pm.current_sclk * 10; + } + + wm_low.disp_clk = mode->clock; + wm_low.src_width = mode->crtc_hdisplay; + wm_low.active_time = mode->crtc_hdisplay * pixel_period; + wm_low.blank_time = line_time - wm_low.active_time; + wm_low.interlaced = false; + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + wm_low.interlaced = true; + wm_low.vsc = amdgpu_crtc->vsc; + wm_low.vtaps = 1; + if (amdgpu_crtc->rmx_type != RMX_OFF) + wm_low.vtaps = 2; + wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ + wm_low.lb_size = lb_size; + wm_low.dram_channels = cik_get_number_of_dram_channels(adev); + wm_low.num_heads = num_heads; + + /* set for low clocks */ + latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535); + + /* possibly force display priority to high */ + /* should really do this at mode validation time... */ + if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || + !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) || + !dce_v10_0_check_latency_hiding(&wm_low) || + (adev->mode_info.disp_priority == 2)) { + DRM_DEBUG_KMS("force priority to high\n"); + } + } + + /* select wm A */ + wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); + tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); + tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); + /* select wm B */ + tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); + tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); + tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); + /* restore original selection */ + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); + + /* save values for DPM */ + amdgpu_crtc->line_time = line_time; + amdgpu_crtc->wm_high = latency_watermark_a; + amdgpu_crtc->wm_low = latency_watermark_b; +} + +/** + * dce_v10_0_bandwidth_update - program display watermarks + * + * @adev: amdgpu_device pointer + * + * Calculate and program the display watermarks and line + * buffer allocation (CIK). + */ +static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev) +{ + struct drm_display_mode *mode = NULL; + u32 num_heads = 0, lb_size; + int i; + + amdgpu_update_display_priority(adev); + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (adev->mode_info.crtcs[i]->base.enabled) + num_heads++; + } + for (i = 0; i < adev->mode_info.num_crtc; i++) { + mode = &adev->mode_info.crtcs[i]->base.mode; + lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); + dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], + lb_size, num_heads); + } +} + +static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev) +{ + int i; + u32 offset, tmp; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + offset = adev->mode_info.audio.pin[i].offset; + tmp = RREG32_AUDIO_ENDPT(offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); + if (((tmp & + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) + adev->mode_info.audio.pin[i].connected = false; + else + adev->mode_info.audio.pin[i].connected = true; + } +} + +static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev) +{ + int i; + + dce_v10_0_audio_get_connected_pins(adev); + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + if (adev->mode_info.audio.pin[i].connected) + return &adev->mode_info.audio.pin[i]; + } + DRM_ERROR("No connected audio pins found!\n"); + return NULL; +} + +static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 tmp; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); + WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); +} + +static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, + struct drm_display_mode *mode) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + u32 tmp; + int interlace = 0; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + interlace = 1; + if (connector->latency_present[interlace]) { + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + VIDEO_LIPSYNC, connector->video_latency[interlace]); + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + AUDIO_LIPSYNC, connector->audio_latency[interlace]); + } else { + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + VIDEO_LIPSYNC, 0); + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + AUDIO_LIPSYNC, 0); + } + WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); +} + +static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + u32 tmp; + u8 *sadb = NULL; + int sad_count; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); + if (sad_count < 0) { + DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); + sad_count = 0; + } + + /* program the speaker allocation */ + tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + DP_CONNECTION, 0); + /* set HDMI mode */ + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + HDMI_CONNECTION, 1); + if (sad_count) + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + SPEAKER_ALLOCATION, sadb[0]); + else + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + SPEAKER_ALLOCATION, 5); /* stereo */ + WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); + + kfree(sadb); +} + +static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + struct cea_sad *sads; + int i, sad_count; + + static const u16 eld_reg_to_type[][2] = { + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, + }; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); + if (sad_count <= 0) { + DRM_ERROR("Couldn't read SADs: %d\n", sad_count); + return; + } + BUG_ON(!sads); + + for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { + u32 tmp = 0; + u8 stereo_freqs = 0; + int max_channels = -1; + int j; + + for (j = 0; j < sad_count; j++) { + struct cea_sad *sad = &sads[j]; + + if (sad->format == eld_reg_to_type[i][1]) { + if (sad->channels > max_channels) { + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + MAX_CHANNELS, sad->channels); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + DESCRIPTOR_BYTE_2, sad->byte2); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + SUPPORTED_FREQUENCIES, sad->freq); + max_channels = sad->channels; + } + + if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) + stereo_freqs |= sad->freq; + else + break; + } + } + + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); + WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); + } + + kfree(sads); +} + +static void dce_v10_0_audio_enable(struct amdgpu_device *adev, + struct amdgpu_audio_pin *pin, + bool enable) +{ + if (!pin) + return; + + WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, + enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); +} + +static const u32 pin_offsets[] = +{ + AUD0_REGISTER_OFFSET, + AUD1_REGISTER_OFFSET, + AUD2_REGISTER_OFFSET, + AUD3_REGISTER_OFFSET, + AUD4_REGISTER_OFFSET, + AUD5_REGISTER_OFFSET, + AUD6_REGISTER_OFFSET, +}; + +static int dce_v10_0_audio_init(struct amdgpu_device *adev) +{ + int i; + + if (!amdgpu_audio) + return 0; + + adev->mode_info.audio.enabled = true; + + adev->mode_info.audio.num_pins = 7; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + adev->mode_info.audio.pin[i].channels = -1; + adev->mode_info.audio.pin[i].rate = -1; + adev->mode_info.audio.pin[i].bits_per_sample = -1; + adev->mode_info.audio.pin[i].status_bits = 0; + adev->mode_info.audio.pin[i].category_code = 0; + adev->mode_info.audio.pin[i].connected = false; + adev->mode_info.audio.pin[i].offset = pin_offsets[i]; + adev->mode_info.audio.pin[i].id = i; + /* disable audio. it will be set up later */ + /* XXX remove once we switch to ip funcs */ + dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + } + + return 0; +} + +static void dce_v10_0_audio_fini(struct amdgpu_device *adev) +{ + int i; + + if (!adev->mode_info.audio.enabled) + return; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) + dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + + adev->mode_info.audio.enabled = false; +} + +/* + * update the N and CTS parameters for a given pixel clock rate + */ +static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 tmp; + + tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); + WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); + tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); + WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); + WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); + tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); + WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); + WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); + tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); + WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); + +} + +/* + * build a HDMI Video Info Frame + */ +static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, + void *buffer, size_t size) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + uint8_t *frame = buffer + 3; + uint8_t *header = buffer; + + WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, + frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); + WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, + frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); + WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, + frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); + WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, + frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); +} + +static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + u32 dto_phase = 24 * 1000; + u32 dto_modulo = clock; + u32 tmp; + + if (!dig || !dig->afmt) + return; + + /* XXX two dtos; generally use dto0 for hdmi */ + /* Express [24MHz / target pixel clock] as an exact rational + * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE + * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator + */ + tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); + tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, + amdgpu_crtc->crtc_id); + WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); + WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); + WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); +} + +/* + * update the info frames with the data from the current display mode + */ +static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, + struct drm_display_mode *mode) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; + struct hdmi_avi_infoframe frame; + ssize_t err; + u32 tmp; + int bpc = 8; + + if (!dig || !dig->afmt) + return; + + /* Silent, r600_hdmi_enable will raise WARN for us */ + if (!dig->afmt->enabled) + return; + + /* hdmi deep color mode general control packets setup, if bpc > 8 */ + if (encoder->crtc) { + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + bpc = amdgpu_crtc->bpc; + } + + /* disable audio prior to setting up hw */ + dig->afmt->pin = dce_v10_0_audio_get_pin(adev); + dce_v10_0_audio_enable(adev, dig->afmt->pin, false); + + dce_v10_0_audio_set_dto(encoder, mode->clock); + + tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); + WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ + + WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); + + tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); + switch (bpc) { + case 0: + case 6: + case 8: + case 16: + default: + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); + DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", + connector->name, bpc); + break; + case 10: + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); + DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", + connector->name); + break; + case 12: + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); + DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", + connector->name); + break; + } + WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ + WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); + /* enable audio info frames (frames won't be set until audio is enabled) */ + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); + /* required for audio info values to be updated */ + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); + WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); + /* required for audio info values to be updated */ + tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); + WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); + /* anything other than 0 */ + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); + WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); + + WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ + + tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); + /* set the default audio delay */ + tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); + /* should be suffient for all audio modes and small enough for all hblanks */ + tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); + WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); + /* allow 60958 channel status fields to be updated */ + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); + WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); + if (bpc > 8) + /* clear SW CTS value */ + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); + else + /* select SW CTS value */ + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); + /* allow hw to sent ACR packets when required */ + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); + WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); + + dce_v10_0_afmt_update_ACR(encoder, mode->clock); + + tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); + WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); + WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); + WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); + + dce_v10_0_audio_write_speaker_allocation(encoder); + + WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, + (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); + + dce_v10_0_afmt_audio_select_pin(encoder); + dce_v10_0_audio_write_sad_regs(encoder); + dce_v10_0_audio_write_latency_fields(encoder, mode); + + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); + if (err < 0) { + DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); + return; + } + + err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); + if (err < 0) { + DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); + return; + } + + dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); + + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); + /* enable AVI info frames */ + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); + /* required for audio info values to be updated */ + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); + WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); + WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); + /* send audio packets */ + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); + WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); + + WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); + WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); + WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); + WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); + + /* enable audio after to setting up hw */ + dce_v10_0_audio_enable(adev, dig->afmt->pin, true); +} + +static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + + if (!dig || !dig->afmt) + return; + + /* Silent, r600_hdmi_enable will raise WARN for us */ + if (enable && dig->afmt->enabled) + return; + if (!enable && !dig->afmt->enabled) + return; + + if (!enable && dig->afmt->pin) { + dce_v10_0_audio_enable(adev, dig->afmt->pin, false); + dig->afmt->pin = NULL; + } + + dig->afmt->enabled = enable; + + DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", + enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); +} + +static void dce_v10_0_afmt_init(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->mode_info.num_dig; i++) + adev->mode_info.afmt[i] = NULL; + + /* DCE10 has audio blocks tied to DIG encoders */ + for (i = 0; i < adev->mode_info.num_dig; i++) { + adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); + if (adev->mode_info.afmt[i]) { + adev->mode_info.afmt[i]->offset = dig_offsets[i]; + adev->mode_info.afmt[i]->id = i; + } + } +} + +static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->mode_info.num_dig; i++) { + kfree(adev->mode_info.afmt[i]); + adev->mode_info.afmt[i] = NULL; + } +} + +static const u32 vga_control_regs[6] = +{ + mmD1VGA_CONTROL, + mmD2VGA_CONTROL, + mmD3VGA_CONTROL, + mmD4VGA_CONTROL, + mmD5VGA_CONTROL, + mmD6VGA_CONTROL, +}; + +static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + u32 vga_control; + + vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; + if (enable) + WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); + else + WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); +} + +static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + + if (enable) + WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); + else + WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); +} + +static void dce_v10_0_tiling_fields(uint64_t tiling_flags, unsigned *bankw, + unsigned *bankh, unsigned *mtaspect, + unsigned *tile_split) +{ + *bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK; + *bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK; + *mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK; + *tile_split = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK; + switch (*bankw) { + default: + case 1: + *bankw = ADDR_SURF_BANK_WIDTH_1; + break; + case 2: + *bankw = ADDR_SURF_BANK_WIDTH_2; + break; + case 4: + *bankw = ADDR_SURF_BANK_WIDTH_4; + break; + case 8: + *bankw = ADDR_SURF_BANK_WIDTH_8; + break; + } + switch (*bankh) { + default: + case 1: + *bankh = ADDR_SURF_BANK_HEIGHT_1; + break; + case 2: + *bankh = ADDR_SURF_BANK_HEIGHT_2; + break; + case 4: + *bankh = ADDR_SURF_BANK_HEIGHT_4; + break; + case 8: + *bankh = ADDR_SURF_BANK_HEIGHT_8; + break; + } + switch (*mtaspect) { + default: + case 1: + *mtaspect = ADDR_SURF_MACRO_ASPECT_1; + break; + case 2: + *mtaspect = ADDR_SURF_MACRO_ASPECT_2; + break; + case 4: + *mtaspect = ADDR_SURF_MACRO_ASPECT_4; + break; + case 8: + *mtaspect = ADDR_SURF_MACRO_ASPECT_8; + break; + } +} + +static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int x, int y, int atomic) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_framebuffer *amdgpu_fb; + struct drm_framebuffer *target_fb; + struct drm_gem_object *obj; + struct amdgpu_bo *rbo; + uint64_t fb_location, tiling_flags; + uint32_t fb_format, fb_pitch_pixels; + unsigned bankw, bankh, mtaspect, tile_split; + u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); + /* XXX change to VI */ + u32 pipe_config = (adev->gfx.config.tile_mode_array[10] >> 6) & 0x1f; + u32 tmp, viewport_w, viewport_h; + int r; + bool bypass_lut = false; + + /* no fb bound */ + if (!atomic && !crtc->primary->fb) { + DRM_DEBUG_KMS("No FB bound\n"); + return 0; + } + + if (atomic) { + amdgpu_fb = to_amdgpu_framebuffer(fb); + target_fb = fb; + } + else { + amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); + target_fb = crtc->primary->fb; + } + + /* If atomic, assume fb object is pinned & idle & fenced and + * just update base pointers + */ + obj = amdgpu_fb->obj; + rbo = gem_to_amdgpu_bo(obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r != 0)) + return r; + + if (atomic) + fb_location = amdgpu_bo_gpu_offset(rbo); + else { + r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); + if (unlikely(r != 0)) { + amdgpu_bo_unreserve(rbo); + return -EINVAL; + } + } + + amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); + amdgpu_bo_unreserve(rbo); + + switch (target_fb->pixel_format) { + case DRM_FORMAT_C8: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); + break; + case DRM_FORMAT_XRGB4444: + case DRM_FORMAT_ARGB4444: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN16); +#endif + break; + case DRM_FORMAT_XRGB1555: + case DRM_FORMAT_ARGB1555: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN16); +#endif + break; + case DRM_FORMAT_BGRX5551: + case DRM_FORMAT_BGRA5551: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN16); +#endif + break; + case DRM_FORMAT_RGB565: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN16); +#endif + break; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN32); +#endif + break; + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN32); +#endif + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ + bypass_lut = true; + break; + case DRM_FORMAT_BGRX1010102: + case DRM_FORMAT_BGRA1010102: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN32); +#endif + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ + bypass_lut = true; + break; + default: + DRM_ERROR("Unsupported screen format %s\n", + drm_get_format_name(target_fb->pixel_format)); + return -EINVAL; + } + + if (tiling_flags & AMDGPU_TILING_MACRO) { + unsigned tileb, index, num_banks, tile_split_bytes; + + dce_v10_0_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); + /* Set NUM_BANKS. */ + /* Calculate the macrotile mode index. */ + tile_split_bytes = 64 << tile_split; + tileb = 8 * 8 * target_fb->bits_per_pixel / 8; + tileb = min(tile_split_bytes, tileb); + + for (index = 0; tileb > 64; index++) { + tileb >>= 1; + } + + if (index >= 16) { + DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", + target_fb->bits_per_pixel, tile_split); + return -EINVAL; + } + + num_banks = (adev->gfx.config.macrotile_mode_array[index] >> 6) & 0x3; + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, + ARRAY_2D_TILED_THIN1); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, + tile_split); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, + mtaspect); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, + ADDR_SURF_MICRO_TILING_DISPLAY); + } else if (tiling_flags & AMDGPU_TILING_MICRO) { + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, + ARRAY_1D_TILED_THIN1); + } + + /* Read the pipe config from the 2D TILED SCANOUT mode. + * It should be the same for the other modes too, but not all + * modes set the pipe config field. */ + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, + pipe_config); + + dce_v10_0_vga_enable(crtc, false); + + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(fb_location)); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(fb_location)); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); + WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); + WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); + + /* + * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT + * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to + * retain the full precision throughout the pipeline. + */ + tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); + if (bypass_lut) + tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); + else + tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); + WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); + + if (bypass_lut) + DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); + + WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); + WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); + + fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); + + dce_v10_0_grph_enable(crtc, true); + + WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, + target_fb->height); + + x &= ~3; + y &= ~1; + WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, + (x << 16) | y); + viewport_w = crtc->mode.hdisplay; + viewport_h = (crtc->mode.vdisplay + 1) & ~1; + WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, + (viewport_w << 16) | viewport_h); + + /* pageflip setup */ + /* make sure flip is at vb rather than hb */ + tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, + GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + /* set pageflip to happen only at start of vblank interval (front porch) */ + WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); + + if (!atomic && fb && fb != crtc->primary->fb) { + amdgpu_fb = to_amdgpu_framebuffer(fb); + rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r != 0)) + return r; + amdgpu_bo_unpin(rbo); + amdgpu_bo_unreserve(rbo); + } + + /* Bytes per pixel may have changed */ + dce_v10_0_bandwidth_update(adev); + + return 0; +} + +static void dce_v10_0_set_interleave(struct drm_crtc *crtc, + struct drm_display_mode *mode) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + u32 tmp; + + tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); + else + tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); + WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); +} + +static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + int i; + u32 tmp; + + DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); + + tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); + tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); + WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); + WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); + WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); + tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); + WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); + + WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); + + WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); + + WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); + + WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); + for (i = 0; i < 256; i++) { + WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, + (amdgpu_crtc->lut_r[i] << 20) | + (amdgpu_crtc->lut_g[i] << 10) | + (amdgpu_crtc->lut_b[i] << 0)); + } + + tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); + tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); + tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); + WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); + tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); + WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); + tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); + WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); + tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); + WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + /* XXX match this to the depth of the crtc fmt block, move to modeset? */ + WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); + /* XXX this only needs to be programmed once per crtc at startup, + * not sure where the best place for it is + */ + tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); + WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); +} + +static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + if (dig->linkb) + return 1; + else + return 0; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + if (dig->linkb) + return 3; + else + return 2; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + if (dig->linkb) + return 5; + else + return 4; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + return 6; + break; + default: + DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); + return 0; + } +} + +/** + * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc. + * + * @crtc: drm crtc + * + * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors + * a single PPLL can be used for all DP crtcs/encoders. For non-DP + * monitors a dedicated PPLL must be used. If a particular board has + * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming + * as there is no need to program the PLL itself. If we are not able to + * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to + * avoid messing up an existing monitor. + * + * Asic specific PLL information + * + * DCE 10.x + * Tonga + * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) + * CI + * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC + * + */ +static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + u32 pll_in_use; + int pll; + + if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { + if (adev->clock.dp_extclk) + /* skip PPLL programming if using ext clock */ + return ATOM_PPLL_INVALID; + else { + /* use the same PPLL for all DP monitors */ + pll = amdgpu_pll_get_shared_dp_ppll(crtc); + if (pll != ATOM_PPLL_INVALID) + return pll; + } + } else { + /* use the same PPLL for all monitors with the same clock */ + pll = amdgpu_pll_get_shared_nondp_ppll(crtc); + if (pll != ATOM_PPLL_INVALID) + return pll; + } + + /* DCE10 has PPLL0, PPLL1, and PPLL2 */ + pll_in_use = amdgpu_pll_get_use_mask(crtc); + if (!(pll_in_use & (1 << ATOM_PPLL2))) + return ATOM_PPLL2; + if (!(pll_in_use & (1 << ATOM_PPLL1))) + return ATOM_PPLL1; + if (!(pll_in_use & (1 << ATOM_PPLL0))) + return ATOM_PPLL0; + DRM_ERROR("unable to allocate a PPLL\n"); + return ATOM_PPLL_INVALID; +} + +static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock) +{ + struct amdgpu_device *adev = crtc->dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + uint32_t cur_lock; + + cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); + if (lock) + cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); + else + cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); + WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); +} + +static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + u32 tmp; + + tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); +} + +static void dce_v10_0_show_cursor(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + u32 tmp; + + tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); + tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); +} + +static void dce_v10_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, + uint64_t gpu_addr) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + + WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(gpu_addr)); + WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + lower_32_bits(gpu_addr)); +} + +static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, + int x, int y) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + int xorigin = 0, yorigin = 0; + + /* avivo cursor are offset into the total surface */ + x += crtc->x; + y += crtc->y; + DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); + + if (x < 0) { + xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); + x = 0; + } + if (y < 0) { + yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); + y = 0; + } + + dce_v10_0_lock_cursor(crtc, true); + WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); + WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, + ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); + dce_v10_0_lock_cursor(crtc, false); + + return 0; +} + +static int dce_v10_0_crtc_cursor_set(struct drm_crtc *crtc, + struct drm_file *file_priv, + uint32_t handle, + uint32_t width, + uint32_t height) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_gem_object *obj; + struct amdgpu_bo *robj; + uint64_t gpu_addr; + int ret; + + if (!handle) { + /* turn off cursor */ + dce_v10_0_hide_cursor(crtc); + obj = NULL; + goto unpin; + } + + if ((width > amdgpu_crtc->max_cursor_width) || + (height > amdgpu_crtc->max_cursor_height)) { + DRM_ERROR("bad cursor width or height %d x %d\n", width, height); + return -EINVAL; + } + + obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); + if (!obj) { + DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); + return -ENOENT; + } + + robj = gem_to_amdgpu_bo(obj); + ret = amdgpu_bo_reserve(robj, false); + if (unlikely(ret != 0)) + goto fail; + ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, + 0, &gpu_addr); + amdgpu_bo_unreserve(robj); + if (ret) + goto fail; + + amdgpu_crtc->cursor_width = width; + amdgpu_crtc->cursor_height = height; + + dce_v10_0_lock_cursor(crtc, true); + dce_v10_0_set_cursor(crtc, obj, gpu_addr); + dce_v10_0_show_cursor(crtc); + dce_v10_0_lock_cursor(crtc, false); + +unpin: + if (amdgpu_crtc->cursor_bo) { + robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); + ret = amdgpu_bo_reserve(robj, false); + if (likely(ret == 0)) { + amdgpu_bo_unpin(robj); + amdgpu_bo_unreserve(robj); + } + drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); + } + + amdgpu_crtc->cursor_bo = obj; + return 0; +fail: + drm_gem_object_unreference_unlocked(obj); + + return ret; +} + +static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t start, uint32_t size) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + int end = (start + size > 256) ? 256 : start + size, i; + + /* userspace palettes are always correct as is */ + for (i = start; i < end; i++) { + amdgpu_crtc->lut_r[i] = red[i] >> 6; + amdgpu_crtc->lut_g[i] = green[i] >> 6; + amdgpu_crtc->lut_b[i] = blue[i] >> 6; + } + dce_v10_0_crtc_load_lut(crtc); +} + +static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + drm_crtc_cleanup(crtc); + destroy_workqueue(amdgpu_crtc->pflip_queue); + kfree(amdgpu_crtc); +} + +static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { + .cursor_set = dce_v10_0_crtc_cursor_set, + .cursor_move = dce_v10_0_crtc_cursor_move, + .gamma_set = dce_v10_0_crtc_gamma_set, + .set_config = amdgpu_crtc_set_config, + .destroy = dce_v10_0_crtc_destroy, + .page_flip = amdgpu_crtc_page_flip, +}; + +static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + switch (mode) { + case DRM_MODE_DPMS_ON: + amdgpu_crtc->enabled = true; + amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); + dce_v10_0_vga_enable(crtc, true); + amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); + dce_v10_0_vga_enable(crtc, false); + drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); + dce_v10_0_crtc_load_lut(crtc); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id); + if (amdgpu_crtc->enabled) { + dce_v10_0_vga_enable(crtc, true); + amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); + dce_v10_0_vga_enable(crtc, false); + } + amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); + amdgpu_crtc->enabled = false; + break; + } + /* adjust pm to dpms */ + amdgpu_pm_compute_clocks(adev); +} + +static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) +{ + /* disable crtc pair power gating before programming */ + amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); + amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); + dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); +} + +static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) +{ + dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); + amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); +} + +static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_atom_ss ss; + int i; + + dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); + if (crtc->primary->fb) { + int r; + struct amdgpu_framebuffer *amdgpu_fb; + struct amdgpu_bo *rbo; + + amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); + rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r)) + DRM_ERROR("failed to reserve rbo before unpin\n"); + else { + amdgpu_bo_unpin(rbo); + amdgpu_bo_unreserve(rbo); + } + } + /* disable the GRPH */ + dce_v10_0_grph_enable(crtc, false); + + amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (adev->mode_info.crtcs[i] && + adev->mode_info.crtcs[i]->enabled && + i != amdgpu_crtc->crtc_id && + amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { + /* one other crtc is using this pll don't turn + * off the pll + */ + goto done; + } + } + + switch (amdgpu_crtc->pll_id) { + case ATOM_PPLL0: + case ATOM_PPLL1: + case ATOM_PPLL2: + /* disable the ppll */ + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, + 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); + break; + default: + break; + } +done: + amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; + amdgpu_crtc->adjusted_clock = 0; + amdgpu_crtc->encoder = NULL; + amdgpu_crtc->connector = NULL; +} + +static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode, + int x, int y, struct drm_framebuffer *old_fb) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + if (!amdgpu_crtc->adjusted_clock) + return -EINVAL; + + amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); + amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); + dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); + amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); + amdgpu_atombios_crtc_scaler_setup(crtc); + /* update the hw version fpr dpm */ + amdgpu_crtc->hw_mode = *adjusted_mode; + + return 0; +} + +static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct drm_encoder *encoder; + + /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + amdgpu_crtc->encoder = encoder; + amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); + break; + } + } + if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { + amdgpu_crtc->encoder = NULL; + amdgpu_crtc->connector = NULL; + return false; + } + if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) + return false; + if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) + return false; + /* pick pll */ + amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); + /* if we can't get a PPLL for a non-DP encoder, fail */ + if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && + !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) + return false; + + return true; +} + +static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, + struct drm_framebuffer *old_fb) +{ + return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); +} + +static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int x, int y, enum mode_set_atomic state) +{ + return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); +} + +static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { + .dpms = dce_v10_0_crtc_dpms, + .mode_fixup = dce_v10_0_crtc_mode_fixup, + .mode_set = dce_v10_0_crtc_mode_set, + .mode_set_base = dce_v10_0_crtc_set_base, + .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic, + .prepare = dce_v10_0_crtc_prepare, + .commit = dce_v10_0_crtc_commit, + .load_lut = dce_v10_0_crtc_load_lut, + .disable = dce_v10_0_crtc_disable, +}; + +static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) +{ + struct amdgpu_crtc *amdgpu_crtc; + int i; + + amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + + (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); + if (amdgpu_crtc == NULL) + return -ENOMEM; + + drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); + + drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); + amdgpu_crtc->crtc_id = index; + amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue"); + adev->mode_info.crtcs[index] = amdgpu_crtc; + + amdgpu_crtc->max_cursor_width = 128; + amdgpu_crtc->max_cursor_height = 128; + adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; + adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; + + for (i = 0; i < 256; i++) { + amdgpu_crtc->lut_r[i] = i << 2; + amdgpu_crtc->lut_g[i] = i << 2; + amdgpu_crtc->lut_b[i] = i << 2; + } + + switch (amdgpu_crtc->crtc_id) { + case 0: + default: + amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; + break; + case 1: + amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; + break; + case 2: + amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; + break; + case 3: + amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; + break; + case 4: + amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; + break; + case 5: + amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; + break; + } + + amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; + amdgpu_crtc->adjusted_clock = 0; + amdgpu_crtc->encoder = NULL; + amdgpu_crtc->connector = NULL; + drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); + + return 0; +} + +static int dce_v10_0_early_init(struct amdgpu_device *adev) +{ + adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; + adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; + + dce_v10_0_set_display_funcs(adev); + dce_v10_0_set_irq_funcs(adev); + + switch (adev->asic_type) { + case CHIP_TONGA: + adev->mode_info.num_crtc = 6; /* XXX 7??? */ + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 7; + break; + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + + return 0; +} + +static int dce_v10_0_sw_init(struct amdgpu_device *adev) +{ + int r, i; + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); + if (r) + return r; + } + + for (i = 8; i < 20; i += 2) { + r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); + if (r) + return r; + } + + /* HPD hotplug */ + r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); + if (r) + return r; + + adev->mode_info.mode_config_initialized = true; + + adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; + + adev->ddev->mode_config.max_width = 16384; + adev->ddev->mode_config.max_height = 16384; + + adev->ddev->mode_config.preferred_depth = 24; + adev->ddev->mode_config.prefer_shadow = 1; + + adev->ddev->mode_config.fb_base = adev->mc.aper_base; + + r = amdgpu_modeset_create_props(adev); + if (r) + return r; + + adev->ddev->mode_config.max_width = 16384; + adev->ddev->mode_config.max_height = 16384; + + /* allocate crtcs */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + r = dce_v10_0_crtc_init(adev, i); + if (r) + return r; + } + + if (amdgpu_atombios_get_connector_info_from_object_table(adev)) + amdgpu_print_display_setup(adev->ddev); + else + return -EINVAL; + + /* setup afmt */ + dce_v10_0_afmt_init(adev); + + r = dce_v10_0_audio_init(adev); + if (r) + return r; + + drm_kms_helper_poll_init(adev->ddev); + + return r; +} + +static int dce_v10_0_sw_fini(struct amdgpu_device *adev) +{ + kfree(adev->mode_info.bios_hardcoded_edid); + + drm_kms_helper_poll_fini(adev->ddev); + + dce_v10_0_audio_fini(adev); + + dce_v10_0_afmt_fini(adev); + + drm_mode_config_cleanup(adev->ddev); + adev->mode_info.mode_config_initialized = false; + + return 0; +} + +static int dce_v10_0_hw_init(struct amdgpu_device *adev) +{ + int i; + + dce_v10_0_init_golden_registers(adev); + + /* init dig PHYs, disp eng pll */ + amdgpu_atombios_encoder_init_dig(adev); + amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); + + /* initialize hpd */ + dce_v10_0_hpd_init(adev); + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + } + + return 0; +} + +static int dce_v10_0_hw_fini(struct amdgpu_device *adev) +{ + int i; + + dce_v10_0_hpd_fini(adev); + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + } + + return 0; +} + +static int dce_v10_0_suspend(struct amdgpu_device *adev) +{ + struct drm_connector *connector; + + drm_kms_helper_poll_disable(adev->ddev); + + /* turn off display hw */ + list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); + } + + amdgpu_atombios_scratch_regs_save(adev); + + dce_v10_0_hpd_fini(adev); + + return 0; +} + +static int dce_v10_0_resume(struct amdgpu_device *adev) +{ + struct drm_connector *connector; + + dce_v10_0_init_golden_registers(adev); + + amdgpu_atombios_scratch_regs_restore(adev); + + /* init dig PHYs, disp eng pll */ + amdgpu_atombios_encoder_init_dig(adev); + amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); + /* turn on the BL */ + if (adev->mode_info.bl_encoder) { + u8 bl_level = amdgpu_display_backlight_get_level(adev, + adev->mode_info.bl_encoder); + amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, + bl_level); + } + + /* initialize hpd */ + dce_v10_0_hpd_init(adev); + + /* blat the mode back in */ + drm_helper_resume_force_mode(adev->ddev); + /* turn on display hw */ + list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); + } + + drm_kms_helper_poll_enable(adev->ddev); + + return 0; +} + +static bool dce_v10_0_is_idle(struct amdgpu_device *adev) +{ + /* XXX todo */ + return true; +} + +static int dce_v10_0_wait_for_idle(struct amdgpu_device *adev) +{ + /* XXX todo */ + return 0; +} + +static void dce_v10_0_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "DCE 10.x registers\n"); + /* XXX todo */ +} + +static int dce_v10_0_soft_reset(struct amdgpu_device *adev) +{ + u32 srbm_soft_reset = 0, tmp; + + if (dce_v10_0_is_display_hung(adev)) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; + + if (srbm_soft_reset) { + dce_v10_0_print_status(adev); + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + dce_v10_0_print_status(adev); + } + return 0; +} + +static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, + int crtc, + enum amdgpu_interrupt_state state) +{ + u32 lb_interrupt_mask; + + if (crtc >= adev->mode_info.num_crtc) { + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); + lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, + VBLANK_INTERRUPT_MASK, 0); + WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); + break; + case AMDGPU_IRQ_STATE_ENABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); + lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, + VBLANK_INTERRUPT_MASK, 1); + WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); + break; + default: + break; + } +} + +static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, + int crtc, + enum amdgpu_interrupt_state state) +{ + u32 lb_interrupt_mask; + + if (crtc >= adev->mode_info.num_crtc) { + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); + lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, + VLINE_INTERRUPT_MASK, 0); + WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); + break; + case AMDGPU_IRQ_STATE_ENABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); + lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, + VLINE_INTERRUPT_MASK, 1); + WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); + break; + default: + break; + } +} + +static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned hpd, + enum amdgpu_interrupt_state state) +{ + u32 tmp; + + if (hpd >= adev->mode_info.num_hpd) { + DRM_DEBUG("invalid hdp %d\n", hpd); + return 0; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); + break; + case AMDGPU_IRQ_STATE_ENABLE: + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); + break; + default: + break; + } + + return 0; +} + +static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + switch (type) { + case AMDGPU_CRTC_IRQ_VBLANK1: + dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK2: + dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK3: + dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK4: + dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK5: + dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK6: + dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state); + break; + case AMDGPU_CRTC_IRQ_VLINE1: + dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state); + break; + case AMDGPU_CRTC_IRQ_VLINE2: + dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state); + break; + case AMDGPU_CRTC_IRQ_VLINE3: + dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state); + break; + case AMDGPU_CRTC_IRQ_VLINE4: + dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state); + break; + case AMDGPU_CRTC_IRQ_VLINE5: + dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state); + break; + case AMDGPU_CRTC_IRQ_VLINE6: + dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state); + break; + default: + break; + } + return 0; +} + +static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 reg, reg_block; + /* now deal with page flip IRQ */ + switch (type) { + case AMDGPU_PAGEFLIP_IRQ_D1: + reg_block = CRTC0_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D2: + reg_block = CRTC1_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D3: + reg_block = CRTC2_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D4: + reg_block = CRTC3_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D5: + reg_block = CRTC4_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D6: + reg_block = CRTC5_REGISTER_OFFSET; + break; + default: + DRM_ERROR("invalid pageflip crtc %d\n", type); + return -EINVAL; + } + + reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); + if (state == AMDGPU_IRQ_STATE_DISABLE) + WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + else + WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + + return 0; +} + +static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + int reg_block; + unsigned long flags; + unsigned crtc_id; + struct amdgpu_crtc *amdgpu_crtc; + struct amdgpu_flip_work *works; + + crtc_id = (entry->src_id - 8) >> 1; + amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + + /* ack the interrupt */ + switch(crtc_id){ + case AMDGPU_PAGEFLIP_IRQ_D1: + reg_block = CRTC0_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D2: + reg_block = CRTC1_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D3: + reg_block = CRTC2_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D4: + reg_block = CRTC3_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D5: + reg_block = CRTC4_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D6: + reg_block = CRTC5_REGISTER_OFFSET; + break; + default: + DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); + return -EINVAL; + } + + if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) + WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); + + /* IRQ could occur when in initial stage */ + if (amdgpu_crtc == NULL) + return 0; + + spin_lock_irqsave(&adev->ddev->event_lock, flags); + works = amdgpu_crtc->pflip_works; + if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { + DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " + "AMDGPU_FLIP_SUBMITTED(%d)\n", + amdgpu_crtc->pflip_status, + AMDGPU_FLIP_SUBMITTED); + spin_unlock_irqrestore(&adev->ddev->event_lock, flags); + return 0; + } + + /* page flip completed. clean up */ + amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; + amdgpu_crtc->pflip_works = NULL; + + /* wakeup usersapce */ + if (works->event) + drm_send_vblank_event(adev->ddev, crtc_id, works->event); + + spin_unlock_irqrestore(&adev->ddev->event_lock, flags); + + drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); + amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id); + queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); + + return 0; +} + +static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, + int hpd) +{ + u32 tmp; + + if (hpd >= adev->mode_info.num_hpd) { + DRM_DEBUG("invalid hdp %d\n", hpd); + return; + } + + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); +} + +static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev, + int crtc) +{ + u32 tmp; + + if (crtc >= adev->mode_info.num_crtc) { + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); + tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); + WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); +} + +static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev, + int crtc) +{ + u32 tmp; + + if (crtc >= adev->mode_info.num_crtc) { + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); + tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); + WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); +} + +static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + unsigned crtc = entry->src_id - 1; + uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); + unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); + + switch (entry->src_data) { + case 0: /* vblank */ + if (disp_int & interrupt_status_offsets[crtc].vblank) { + dce_v10_0_crtc_vblank_int_ack(adev, crtc); + if (amdgpu_irq_enabled(adev, source, irq_type)) { + drm_handle_vblank(adev->ddev, crtc); + } + DRM_DEBUG("IH: D%d vblank\n", crtc + 1); + } + break; + case 1: /* vline */ + if (disp_int & interrupt_status_offsets[crtc].vline) { + dce_v10_0_crtc_vline_int_ack(adev, crtc); + DRM_DEBUG("IH: D%d vline\n", crtc + 1); + } + break; + default: + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + break; + } + + return 0; +} + +static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + uint32_t disp_int, mask; + unsigned hpd; + + if (entry->src_data >= adev->mode_info.num_hpd) { + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + return 0; + } + + hpd = entry->src_data; + disp_int = RREG32(interrupt_status_offsets[hpd].reg); + mask = interrupt_status_offsets[hpd].hpd; + + if (disp_int & mask) { + dce_v10_0_hpd_int_ack(adev, hpd); + schedule_work(&adev->hotplug_work); + DRM_DEBUG("IH: HPD%d\n", hpd + 1); + } + + return 0; +} + +static int dce_v10_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static int dce_v10_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs dce_v10_0_ip_funcs = { + .early_init = dce_v10_0_early_init, + .late_init = NULL, + .sw_init = dce_v10_0_sw_init, + .sw_fini = dce_v10_0_sw_fini, + .hw_init = dce_v10_0_hw_init, + .hw_fini = dce_v10_0_hw_fini, + .suspend = dce_v10_0_suspend, + .resume = dce_v10_0_resume, + .is_idle = dce_v10_0_is_idle, + .wait_for_idle = dce_v10_0_wait_for_idle, + .soft_reset = dce_v10_0_soft_reset, + .print_status = dce_v10_0_print_status, + .set_clockgating_state = dce_v10_0_set_clockgating_state, + .set_powergating_state = dce_v10_0_set_powergating_state, +}; + +static void +dce_v10_0_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + + amdgpu_encoder->pixel_clock = adjusted_mode->clock; + + /* need to call this here rather than in prepare() since we need some crtc info */ + amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); + + /* set scaler clears this on some chips */ + dce_v10_0_set_interleave(encoder->crtc, mode); + + if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { + dce_v10_0_afmt_enable(encoder, true); + dce_v10_0_afmt_setmode(encoder, adjusted_mode); + } +} + +static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + + if ((amdgpu_encoder->active_device & + (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || + (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != + ENCODER_OBJECT_ID_NONE)) { + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + if (dig) { + dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); + if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) + dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; + } + } + + amdgpu_atombios_scratch_regs_lock(adev, true); + + if (connector) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + /* select the clock/data port if it uses a router */ + if (amdgpu_connector->router.cd_valid) + amdgpu_i2c_router_select_cd_port(amdgpu_connector); + + /* turn eDP panel on for mode set */ + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) + amdgpu_atombios_encoder_set_edp_panel_power(connector, + ATOM_TRANSMITTER_ACTION_POWER_ON); + } + + /* this is needed for the pll/ss setup to work correctly in some cases */ + amdgpu_atombios_encoder_set_crtc_source(encoder); + /* set up the FMT blocks */ + dce_v10_0_program_fmt(encoder); +} + +static void dce_v10_0_encoder_commit(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + + /* need to call this here as we need the crtc set up */ + amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); + amdgpu_atombios_scratch_regs_lock(adev, false); +} + +static void dce_v10_0_encoder_disable(struct drm_encoder *encoder) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig; + + amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); + + if (amdgpu_atombios_encoder_is_digital(encoder)) { + if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) + dce_v10_0_afmt_enable(encoder, false); + dig = amdgpu_encoder->enc_priv; + dig->dig_encoder = -1; + } + amdgpu_encoder->active_device = 0; +} + +/* these are handled by the primary encoders */ +static void dce_v10_0_ext_prepare(struct drm_encoder *encoder) +{ + +} + +static void dce_v10_0_ext_commit(struct drm_encoder *encoder) +{ + +} + +static void +dce_v10_0_ext_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + +} + +static void dce_v10_0_ext_disable(struct drm_encoder *encoder) +{ + +} + +static void +dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode) +{ + +} + +static bool dce_v10_0_ext_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = { + .dpms = dce_v10_0_ext_dpms, + .mode_fixup = dce_v10_0_ext_mode_fixup, + .prepare = dce_v10_0_ext_prepare, + .mode_set = dce_v10_0_ext_mode_set, + .commit = dce_v10_0_ext_commit, + .disable = dce_v10_0_ext_disable, + /* no detect for TMDS/LVDS yet */ +}; + +static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = { + .dpms = amdgpu_atombios_encoder_dpms, + .mode_fixup = amdgpu_atombios_encoder_mode_fixup, + .prepare = dce_v10_0_encoder_prepare, + .mode_set = dce_v10_0_encoder_mode_set, + .commit = dce_v10_0_encoder_commit, + .disable = dce_v10_0_encoder_disable, + .detect = amdgpu_atombios_encoder_dig_detect, +}; + +static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = { + .dpms = amdgpu_atombios_encoder_dpms, + .mode_fixup = amdgpu_atombios_encoder_mode_fixup, + .prepare = dce_v10_0_encoder_prepare, + .mode_set = dce_v10_0_encoder_mode_set, + .commit = dce_v10_0_encoder_commit, + .detect = amdgpu_atombios_encoder_dac_detect, +}; + +static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) + amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); + kfree(amdgpu_encoder->enc_priv); + drm_encoder_cleanup(encoder); + kfree(amdgpu_encoder); +} + +static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = { + .destroy = dce_v10_0_encoder_destroy, +}; + +static void dce_v10_0_encoder_add(struct amdgpu_device *adev, + uint32_t encoder_enum, + uint32_t supported_device, + u16 caps) +{ + struct drm_device *dev = adev->ddev; + struct drm_encoder *encoder; + struct amdgpu_encoder *amdgpu_encoder; + + /* see if we already added it */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + amdgpu_encoder = to_amdgpu_encoder(encoder); + if (amdgpu_encoder->encoder_enum == encoder_enum) { + amdgpu_encoder->devices |= supported_device; + return; + } + + } + + /* add a new one */ + amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); + if (!amdgpu_encoder) + return; + + encoder = &amdgpu_encoder->base; + switch (adev->mode_info.num_crtc) { + case 1: + encoder->possible_crtcs = 0x1; + break; + case 2: + default: + encoder->possible_crtcs = 0x3; + break; + case 4: + encoder->possible_crtcs = 0xf; + break; + case 6: + encoder->possible_crtcs = 0x3f; + break; + } + + amdgpu_encoder->enc_priv = NULL; + + amdgpu_encoder->encoder_enum = encoder_enum; + amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; + amdgpu_encoder->devices = supported_device; + amdgpu_encoder->rmx_type = RMX_OFF; + amdgpu_encoder->underscan_type = UNDERSCAN_OFF; + amdgpu_encoder->is_ext_encoder = false; + amdgpu_encoder->caps = caps; + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, + DRM_MODE_ENCODER_DAC); + drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + amdgpu_encoder->rmx_type = RMX_FULL; + drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, + DRM_MODE_ENCODER_LVDS); + amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); + } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { + drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, + DRM_MODE_ENCODER_DAC); + amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); + } else { + drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, + DRM_MODE_ENCODER_TMDS); + amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); + } + drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); + break; + case ENCODER_OBJECT_ID_SI170B: + case ENCODER_OBJECT_ID_CH7303: + case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: + case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: + case ENCODER_OBJECT_ID_TITFP513: + case ENCODER_OBJECT_ID_VT1623: + case ENCODER_OBJECT_ID_HDMI_SI1930: + case ENCODER_OBJECT_ID_TRAVIS: + case ENCODER_OBJECT_ID_NUTMEG: + /* these are handled by the primary encoders */ + amdgpu_encoder->is_ext_encoder = true; + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) + drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, + DRM_MODE_ENCODER_LVDS); + else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) + drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, + DRM_MODE_ENCODER_DAC); + else + drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, + DRM_MODE_ENCODER_TMDS); + drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs); + break; + } +} + +static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { + .set_vga_render_state = &dce_v10_0_set_vga_render_state, + .bandwidth_update = &dce_v10_0_bandwidth_update, + .vblank_get_counter = &dce_v10_0_vblank_get_counter, + .vblank_wait = &dce_v10_0_vblank_wait, + .is_display_hung = &dce_v10_0_is_display_hung, + .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, + .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, + .hpd_sense = &dce_v10_0_hpd_sense, + .hpd_set_polarity = &dce_v10_0_hpd_set_polarity, + .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg, + .page_flip = &dce_v10_0_page_flip, + .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos, + .add_encoder = &dce_v10_0_encoder_add, + .add_connector = &amdgpu_connector_add, + .stop_mc_access = &dce_v10_0_stop_mc_access, + .resume_mc_access = &dce_v10_0_resume_mc_access, +}; + +static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev) +{ + if (adev->mode_info.funcs == NULL) + adev->mode_info.funcs = &dce_v10_0_display_funcs; +} + +static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = { + .set = dce_v10_0_set_crtc_irq_state, + .process = dce_v10_0_crtc_irq, +}; + +static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = { + .set = dce_v10_0_set_pageflip_irq_state, + .process = dce_v10_0_pageflip_irq, +}; + +static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { + .set = dce_v10_0_set_hpd_irq_state, + .process = dce_v10_0_hpd_irq, +}; + +static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; + + adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; + + adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h new file mode 100644 index 000000000000..72ca20d1793c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DCE_V10_0_H__ +#define __DCE_V10_0_H__ + +extern const struct amdgpu_ip_funcs dce_v10_0_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c new file mode 100644 index 000000000000..55fef15a4fcf --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -0,0 +1,3871 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_pm.h" +#include "amdgpu_i2c.h" +#include "vid.h" +#include "atom.h" +#include "amdgpu_atombios.h" +#include "atombios_crtc.h" +#include "atombios_encoders.h" +#include "amdgpu_pll.h" +#include "amdgpu_connectors.h" + +#include "dce/dce_11_0_d.h" +#include "dce/dce_11_0_sh_mask.h" +#include "dce/dce_11_0_enum.h" +#include "oss/oss_3_0_d.h" +#include "oss/oss_3_0_sh_mask.h" +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" + +static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); +static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); + +static const u32 crtc_offsets[] = +{ + CRTC0_REGISTER_OFFSET, + CRTC1_REGISTER_OFFSET, + CRTC2_REGISTER_OFFSET, + CRTC3_REGISTER_OFFSET, + CRTC4_REGISTER_OFFSET, + CRTC5_REGISTER_OFFSET, + CRTC6_REGISTER_OFFSET +}; + +static const u32 hpd_offsets[] = +{ + HPD0_REGISTER_OFFSET, + HPD1_REGISTER_OFFSET, + HPD2_REGISTER_OFFSET, + HPD3_REGISTER_OFFSET, + HPD4_REGISTER_OFFSET, + HPD5_REGISTER_OFFSET +}; + +static const uint32_t dig_offsets[] = { + DIG0_REGISTER_OFFSET, + DIG1_REGISTER_OFFSET, + DIG2_REGISTER_OFFSET, + DIG3_REGISTER_OFFSET, + DIG4_REGISTER_OFFSET, + DIG5_REGISTER_OFFSET, + DIG6_REGISTER_OFFSET, + DIG7_REGISTER_OFFSET, + DIG8_REGISTER_OFFSET +}; + +static const struct { + uint32_t reg; + uint32_t vblank; + uint32_t vline; + uint32_t hpd; + +} interrupt_status_offsets[] = { { + .reg = mmDISP_INTERRUPT_STATUS, + .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK +}, { + .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, + .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, + .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, + .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK +} }; + +static const u32 cz_golden_settings_a11[] = +{ + mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, + mmFBC_MISC, 0x1f311fff, 0x14300000, +}; + +static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_CARRIZO: + amdgpu_program_register_sequence(adev, + cz_golden_settings_a11, + (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + break; + default: + break; + } +} + +static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, + u32 block_offset, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); + r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); + spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + + return r; +} + +static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, + u32 block_offset, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); + WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); + spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); +} + +static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc) +{ + if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & + CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) + return true; + else + return false; +} + +static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc) +{ + u32 pos1, pos2; + + pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); + pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); + + if (pos1 != pos2) + return true; + else + return false; +} + +/** + * dce_v11_0_vblank_wait - vblank wait asic callback. + * + * @adev: amdgpu_device pointer + * @crtc: crtc to wait for vblank on + * + * Wait for vblank on the requested crtc (evergreen+). + */ +static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc) +{ + unsigned i = 0; + + if (crtc >= adev->mode_info.num_crtc) + return; + + if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) + return; + + /* depending on when we hit vblank, we may be close to active; if so, + * wait for another frame. + */ + while (dce_v11_0_is_in_vblank(adev, crtc)) { + if (i++ % 100 == 0) { + if (!dce_v11_0_is_counter_moving(adev, crtc)) + break; + } + } + + while (!dce_v11_0_is_in_vblank(adev, crtc)) { + if (i++ % 100 == 0) { + if (!dce_v11_0_is_counter_moving(adev, crtc)) + break; + } + } +} + +static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) +{ + if (crtc >= adev->mode_info.num_crtc) + return 0; + else + return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); +} + +/** + * dce_v11_0_page_flip - pageflip callback. + * + * @adev: amdgpu_device pointer + * @crtc_id: crtc to cleanup pageflip on + * @crtc_base: new address of the crtc (GPU MC address) + * + * Does the actual pageflip (evergreen+). + * During vblank we take the crtc lock and wait for the update_pending + * bit to go high, when it does, we release the lock, and allow the + * double buffered update to take place. + * Returns the current update pending status. + */ +static void dce_v11_0_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base) +{ + struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); + int i; + + /* Lock the graphics update lock */ + tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); + WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); + + /* update the scanout addresses */ + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(crtc_base)); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + lower_32_bits(crtc_base)); + + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(crtc_base)); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + lower_32_bits(crtc_base)); + + /* Wait for update_pending to go high. */ + for (i = 0; i < adev->usec_timeout; i++) { + if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & + GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) + break; + udelay(1); + } + DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); + + /* Unlock the lock, so double-buffering can take place inside vblank */ + tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); + WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); +} + +static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, + u32 *vbl, u32 *position) +{ + if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) + return -EINVAL; + + *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); + *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); + + return 0; +} + +/** + * dce_v11_0_hpd_sense - hpd sense callback. + * + * @adev: amdgpu_device pointer + * @hpd: hpd (hotplug detect) pin + * + * Checks if a digital monitor is connected (evergreen+). + * Returns true if connected, false if not connected. + */ +static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + int idx; + bool connected = false; + + switch (hpd) { + case AMDGPU_HPD_1: + idx = 0; + break; + case AMDGPU_HPD_2: + idx = 1; + break; + case AMDGPU_HPD_3: + idx = 2; + break; + case AMDGPU_HPD_4: + idx = 3; + break; + case AMDGPU_HPD_5: + idx = 4; + break; + case AMDGPU_HPD_6: + idx = 5; + break; + default: + return connected; + } + + if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & + DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) + connected = true; + + return connected; +} + +/** + * dce_v11_0_hpd_set_polarity - hpd set polarity callback. + * + * @adev: amdgpu_device pointer + * @hpd: hpd (hotplug detect) pin + * + * Set the polarity of the hpd pin (evergreen+). + */ +static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + u32 tmp; + bool connected = dce_v11_0_hpd_sense(adev, hpd); + int idx; + + switch (hpd) { + case AMDGPU_HPD_1: + idx = 0; + break; + case AMDGPU_HPD_2: + idx = 1; + break; + case AMDGPU_HPD_3: + idx = 2; + break; + case AMDGPU_HPD_4: + idx = 3; + break; + case AMDGPU_HPD_5: + idx = 4; + break; + case AMDGPU_HPD_6: + idx = 5; + break; + default: + return; + } + + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); + if (connected) + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); + else + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); +} + +/** + * dce_v11_0_hpd_init - hpd setup callback. + * + * @adev: amdgpu_device pointer + * + * Setup the hpd pins used by the card (evergreen+). + * Enable the pin, set the polarity, and enable the hpd interrupts. + */ +static void dce_v11_0_hpd_init(struct amdgpu_device *adev) +{ + struct drm_device *dev = adev->ddev; + struct drm_connector *connector; + u32 tmp; + int idx; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || + connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { + /* don't try to enable hpd on eDP or LVDS avoid breaking the + * aux dp channel on imac and help (but not completely fix) + * https://bugzilla.redhat.com/show_bug.cgi?id=726143 + * also avoid interrupt storms during dpms. + */ + continue; + } + + switch (amdgpu_connector->hpd.hpd) { + case AMDGPU_HPD_1: + idx = 0; + break; + case AMDGPU_HPD_2: + idx = 1; + break; + case AMDGPU_HPD_3: + idx = 2; + break; + case AMDGPU_HPD_4: + idx = 3; + break; + case AMDGPU_HPD_5: + idx = 4; + break; + case AMDGPU_HPD_6: + idx = 5; + break; + default: + continue; + } + + tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); + tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); + WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); + + tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); + tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, + DC_HPD_CONNECT_INT_DELAY, + AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); + tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, + DC_HPD_DISCONNECT_INT_DELAY, + AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); + WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); + + dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); + amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); + } +} + +/** + * dce_v11_0_hpd_fini - hpd tear down callback. + * + * @adev: amdgpu_device pointer + * + * Tear down the hpd pins used by the card (evergreen+). + * Disable the hpd interrupts. + */ +static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) +{ + struct drm_device *dev = adev->ddev; + struct drm_connector *connector; + u32 tmp; + int idx; + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + switch (amdgpu_connector->hpd.hpd) { + case AMDGPU_HPD_1: + idx = 0; + break; + case AMDGPU_HPD_2: + idx = 1; + break; + case AMDGPU_HPD_3: + idx = 2; + break; + case AMDGPU_HPD_4: + idx = 3; + break; + case AMDGPU_HPD_5: + idx = 4; + break; + case AMDGPU_HPD_6: + idx = 5; + break; + default: + continue; + } + + tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); + tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); + WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); + + amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); + } +} + +static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) +{ + return mmDC_GPIO_HPD_A; +} + +static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) +{ + u32 crtc_hung = 0; + u32 crtc_status[6]; + u32 i, j, tmp; + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { + crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); + crtc_hung |= (1 << i); + } + } + + for (j = 0; j < 10; j++) { + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (crtc_hung & (1 << i)) { + tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); + if (tmp != crtc_status[i]) + crtc_hung &= ~(1 << i); + } + } + if (crtc_hung == 0) + return false; + udelay(100); + } + + return true; +} + +static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save) +{ + u32 crtc_enabled, tmp; + int i; + + save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); + save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); + + /* disable VGA render */ + tmp = RREG32(mmVGA_RENDER_CONTROL); + tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); + WREG32(mmVGA_RENDER_CONTROL, tmp); + + /* blank the display controllers */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), + CRTC_CONTROL, CRTC_MASTER_EN); + if (crtc_enabled) { +#if 0 + u32 frame_count; + int j; + + save->crtc_enabled[i] = true; + tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { + amdgpu_display_vblank_wait(adev, i); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); + WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); + } + /* wait for the next frame */ + frame_count = amdgpu_display_vblank_get_counter(adev, i); + for (j = 0; j < adev->usec_timeout; j++) { + if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) + break; + udelay(1); + } + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { + tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); + WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); + } + tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { + tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); + WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); + } +#else + /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); + tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); + WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); + save->crtc_enabled[i] = false; + /* ***** */ +#endif + } else { + save->crtc_enabled[i] = false; + } + } +} + +static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save) +{ + u32 tmp, frame_count; + int i, j; + + /* update crtc base addresses */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], + upper_32_bits(adev->mc.vram_start)); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], + upper_32_bits(adev->mc.vram_start)); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], + (u32)adev->mc.vram_start); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], + (u32)adev->mc.vram_start); + + if (save->crtc_enabled[i]) { + tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { + tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); + WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); + } + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { + tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); + WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); + } + tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { + tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); + WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); + } + for (j = 0; j < adev->usec_timeout; j++) { + tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); + if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) + break; + udelay(1); + } + tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); + tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); + WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); + WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); + /* wait for the next frame */ + frame_count = amdgpu_display_vblank_get_counter(adev, i); + for (j = 0; j < adev->usec_timeout; j++) { + if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) + break; + udelay(1); + } + } + } + + WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); + WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); + + /* Unlock vga access */ + WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); + mdelay(1); + WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); +} + +static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, + bool render) +{ + u32 tmp; + + /* Lockout access through VGA aperture*/ + tmp = RREG32(mmVGA_HDP_CONTROL); + if (render) + tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); + else + tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); + WREG32(mmVGA_HDP_CONTROL, tmp); + + /* disable VGA render */ + tmp = RREG32(mmVGA_RENDER_CONTROL); + if (render) + tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); + else + tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); + WREG32(mmVGA_RENDER_CONTROL, tmp); +} + +static void dce_v11_0_program_fmt(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + int bpc = 0; + u32 tmp = 0; + enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; + + if (connector) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + bpc = amdgpu_connector_get_monitor_bpc(connector); + dither = amdgpu_connector->dither; + } + + /* LVDS/eDP FMT is set up by atom */ + if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) + return; + + /* not needed for analog */ + if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || + (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) + return; + + if (bpc == 0) + return; + + switch (bpc) { + case 6: + if (dither == AMDGPU_FMT_DITHER_ENABLE) { + /* XXX sort out optimal dither settings */ + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); + } else { + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); + } + break; + case 8: + if (dither == AMDGPU_FMT_DITHER_ENABLE) { + /* XXX sort out optimal dither settings */ + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); + } else { + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); + } + break; + case 10: + if (dither == AMDGPU_FMT_DITHER_ENABLE) { + /* XXX sort out optimal dither settings */ + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); + } else { + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); + tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); + } + break; + default: + /* not needed */ + break; + } + + WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); +} + + +/* display watermark setup */ +/** + * dce_v11_0_line_buffer_adjust - Set up the line buffer + * + * @adev: amdgpu_device pointer + * @amdgpu_crtc: the selected display controller + * @mode: the current display mode on the selected display + * controller + * + * Setup up the line buffer allocation for + * the selected display controller (CIK). + * Returns the line buffer size in pixels. + */ +static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, + struct amdgpu_crtc *amdgpu_crtc, + struct drm_display_mode *mode) +{ + u32 tmp, buffer_alloc, i, mem_cfg; + u32 pipe_offset = amdgpu_crtc->crtc_id; + /* + * Line Buffer Setup + * There are 6 line buffers, one for each display controllers. + * There are 3 partitions per LB. Select the number of partitions + * to enable based on the display width. For display widths larger + * than 4096, you need use to use 2 display controllers and combine + * them using the stereo blender. + */ + if (amdgpu_crtc->base.enabled && mode) { + if (mode->crtc_hdisplay < 1920) { + mem_cfg = 1; + buffer_alloc = 2; + } else if (mode->crtc_hdisplay < 2560) { + mem_cfg = 2; + buffer_alloc = 2; + } else if (mode->crtc_hdisplay < 4096) { + mem_cfg = 0; + buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; + } else { + DRM_DEBUG_KMS("Mode too big for LB!\n"); + mem_cfg = 0; + buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; + } + } else { + mem_cfg = 1; + buffer_alloc = 0; + } + + tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); + WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); + tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); + WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); + if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) + break; + udelay(1); + } + + if (amdgpu_crtc->base.enabled && mode) { + switch (mem_cfg) { + case 0: + default: + return 4096 * 2; + case 1: + return 1920 * 2; + case 2: + return 2560 * 2; + } + } + + /* controller not enabled, so no lb used */ + return 0; +} + +/** + * cik_get_number_of_dram_channels - get the number of dram channels + * + * @adev: amdgpu_device pointer + * + * Look up the number of video ram channels (CIK). + * Used for display watermark bandwidth calculations + * Returns the number of dram channels + */ +static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmMC_SHARED_CHMAP); + + switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { + case 0: + default: + return 1; + case 1: + return 2; + case 2: + return 4; + case 3: + return 8; + case 4: + return 3; + case 5: + return 6; + case 6: + return 10; + case 7: + return 12; + case 8: + return 16; + } +} + +struct dce10_wm_params { + u32 dram_channels; /* number of dram channels */ + u32 yclk; /* bandwidth per dram data pin in kHz */ + u32 sclk; /* engine clock in kHz */ + u32 disp_clk; /* display clock in kHz */ + u32 src_width; /* viewport width */ + u32 active_time; /* active display time in ns */ + u32 blank_time; /* blank time in ns */ + bool interlaced; /* mode is interlaced */ + fixed20_12 vsc; /* vertical scale ratio */ + u32 num_heads; /* number of active crtcs */ + u32 bytes_per_pixel; /* bytes per pixel display + overlay */ + u32 lb_size; /* line buffer allocated to pipe */ + u32 vtaps; /* vertical scaler taps */ +}; + +/** + * dce_v11_0_dram_bandwidth - get the dram bandwidth + * + * @wm: watermark calculation data + * + * Calculate the raw dram bandwidth (CIK). + * Used for display watermark bandwidth calculations + * Returns the dram bandwidth in MBytes/s + */ +static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) +{ + /* Calculate raw DRAM Bandwidth */ + fixed20_12 dram_efficiency; /* 0.7 */ + fixed20_12 yclk, dram_channels, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + yclk.full = dfixed_const(wm->yclk); + yclk.full = dfixed_div(yclk, a); + dram_channels.full = dfixed_const(wm->dram_channels * 4); + a.full = dfixed_const(10); + dram_efficiency.full = dfixed_const(7); + dram_efficiency.full = dfixed_div(dram_efficiency, a); + bandwidth.full = dfixed_mul(dram_channels, yclk); + bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display + * + * @wm: watermark calculation data + * + * Calculate the dram bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the dram bandwidth for display in MBytes/s + */ +static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) +{ + /* Calculate DRAM Bandwidth and the part allocated to display. */ + fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ + fixed20_12 yclk, dram_channels, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + yclk.full = dfixed_const(wm->yclk); + yclk.full = dfixed_div(yclk, a); + dram_channels.full = dfixed_const(wm->dram_channels * 4); + a.full = dfixed_const(10); + disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ + disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); + bandwidth.full = dfixed_mul(dram_channels, yclk); + bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v11_0_data_return_bandwidth - get the data return bandwidth + * + * @wm: watermark calculation data + * + * Calculate the data return bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the data return bandwidth in MBytes/s + */ +static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) +{ + /* Calculate the display Data return Bandwidth */ + fixed20_12 return_efficiency; /* 0.8 */ + fixed20_12 sclk, bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + sclk.full = dfixed_const(wm->sclk); + sclk.full = dfixed_div(sclk, a); + a.full = dfixed_const(10); + return_efficiency.full = dfixed_const(8); + return_efficiency.full = dfixed_div(return_efficiency, a); + a.full = dfixed_const(32); + bandwidth.full = dfixed_mul(a, sclk); + bandwidth.full = dfixed_mul(bandwidth, return_efficiency); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth + * + * @wm: watermark calculation data + * + * Calculate the dmif bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the dmif bandwidth in MBytes/s + */ +static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) +{ + /* Calculate the DMIF Request Bandwidth */ + fixed20_12 disp_clk_request_efficiency; /* 0.8 */ + fixed20_12 disp_clk, bandwidth; + fixed20_12 a, b; + + a.full = dfixed_const(1000); + disp_clk.full = dfixed_const(wm->disp_clk); + disp_clk.full = dfixed_div(disp_clk, a); + a.full = dfixed_const(32); + b.full = dfixed_mul(a, disp_clk); + + a.full = dfixed_const(10); + disp_clk_request_efficiency.full = dfixed_const(8); + disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); + + bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v11_0_available_bandwidth - get the min available bandwidth + * + * @wm: watermark calculation data + * + * Calculate the min available bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the min available bandwidth in MBytes/s + */ +static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) +{ + /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ + u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); + u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); + u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); + + return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); +} + +/** + * dce_v11_0_average_bandwidth - get the average available bandwidth + * + * @wm: watermark calculation data + * + * Calculate the average available bandwidth used for display (CIK). + * Used for display watermark bandwidth calculations + * Returns the average available bandwidth in MBytes/s + */ +static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) +{ + /* Calculate the display mode Average Bandwidth + * DisplayMode should contain the source and destination dimensions, + * timing, etc. + */ + fixed20_12 bpp; + fixed20_12 line_time; + fixed20_12 src_width; + fixed20_12 bandwidth; + fixed20_12 a; + + a.full = dfixed_const(1000); + line_time.full = dfixed_const(wm->active_time + wm->blank_time); + line_time.full = dfixed_div(line_time, a); + bpp.full = dfixed_const(wm->bytes_per_pixel); + src_width.full = dfixed_const(wm->src_width); + bandwidth.full = dfixed_mul(src_width, bpp); + bandwidth.full = dfixed_mul(bandwidth, wm->vsc); + bandwidth.full = dfixed_div(bandwidth, line_time); + + return dfixed_trunc(bandwidth); +} + +/** + * dce_v11_0_latency_watermark - get the latency watermark + * + * @wm: watermark calculation data + * + * Calculate the latency watermark (CIK). + * Used for display watermark bandwidth calculations + * Returns the latency watermark in ns + */ +static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) +{ + /* First calculate the latency in ns */ + u32 mc_latency = 2000; /* 2000 ns. */ + u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); + u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; + u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; + u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ + u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + + (wm->num_heads * cursor_line_pair_return_time); + u32 latency = mc_latency + other_heads_data_return_time + dc_latency; + u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; + u32 tmp, dmif_size = 12288; + fixed20_12 a, b, c; + + if (wm->num_heads == 0) + return 0; + + a.full = dfixed_const(2); + b.full = dfixed_const(1); + if ((wm->vsc.full > a.full) || + ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || + (wm->vtaps >= 5) || + ((wm->vsc.full >= a.full) && wm->interlaced)) + max_src_lines_per_dst_line = 4; + else + max_src_lines_per_dst_line = 2; + + a.full = dfixed_const(available_bandwidth); + b.full = dfixed_const(wm->num_heads); + a.full = dfixed_div(a, b); + + b.full = dfixed_const(mc_latency + 512); + c.full = dfixed_const(wm->disp_clk); + b.full = dfixed_div(b, c); + + c.full = dfixed_const(dmif_size); + b.full = dfixed_div(c, b); + + tmp = min(dfixed_trunc(a), dfixed_trunc(b)); + + b.full = dfixed_const(1000); + c.full = dfixed_const(wm->disp_clk); + b.full = dfixed_div(c, b); + c.full = dfixed_const(wm->bytes_per_pixel); + b.full = dfixed_mul(b, c); + + lb_fill_bw = min(tmp, dfixed_trunc(b)); + + a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); + b.full = dfixed_const(1000); + c.full = dfixed_const(lb_fill_bw); + b.full = dfixed_div(c, b); + a.full = dfixed_div(a, b); + line_fill_time = dfixed_trunc(a); + + if (line_fill_time < wm->active_time) + return latency; + else + return latency + (line_fill_time - wm->active_time); + +} + +/** + * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check + * average and available dram bandwidth + * + * @wm: watermark calculation data + * + * Check if the display average bandwidth fits in the display + * dram bandwidth (CIK). + * Used for display watermark bandwidth calculations + * Returns true if the display fits, false if not. + */ +static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) +{ + if (dce_v11_0_average_bandwidth(wm) <= + (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) + return true; + else + return false; +} + +/** + * dce_v11_0_average_bandwidth_vs_available_bandwidth - check + * average and available bandwidth + * + * @wm: watermark calculation data + * + * Check if the display average bandwidth fits in the display + * available bandwidth (CIK). + * Used for display watermark bandwidth calculations + * Returns true if the display fits, false if not. + */ +static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) +{ + if (dce_v11_0_average_bandwidth(wm) <= + (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) + return true; + else + return false; +} + +/** + * dce_v11_0_check_latency_hiding - check latency hiding + * + * @wm: watermark calculation data + * + * Check latency hiding (CIK). + * Used for display watermark bandwidth calculations + * Returns true if the display fits, false if not. + */ +static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) +{ + u32 lb_partitions = wm->lb_size / wm->src_width; + u32 line_time = wm->active_time + wm->blank_time; + u32 latency_tolerant_lines; + u32 latency_hiding; + fixed20_12 a; + + a.full = dfixed_const(1); + if (wm->vsc.full > a.full) + latency_tolerant_lines = 1; + else { + if (lb_partitions <= (wm->vtaps + 1)) + latency_tolerant_lines = 1; + else + latency_tolerant_lines = 2; + } + + latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); + + if (dce_v11_0_latency_watermark(wm) <= latency_hiding) + return true; + else + return false; +} + +/** + * dce_v11_0_program_watermarks - program display watermarks + * + * @adev: amdgpu_device pointer + * @amdgpu_crtc: the selected display controller + * @lb_size: line buffer size + * @num_heads: number of display controllers in use + * + * Calculate and program the display watermarks for the + * selected display controller (CIK). + */ +static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, + struct amdgpu_crtc *amdgpu_crtc, + u32 lb_size, u32 num_heads) +{ + struct drm_display_mode *mode = &amdgpu_crtc->base.mode; + struct dce10_wm_params wm_low, wm_high; + u32 pixel_period; + u32 line_time = 0; + u32 latency_watermark_a = 0, latency_watermark_b = 0; + u32 tmp, wm_mask; + + if (amdgpu_crtc->base.enabled && num_heads && mode) { + pixel_period = 1000000 / (u32)mode->clock; + line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); + + /* watermark for high clocks */ + if (adev->pm.dpm_enabled) { + wm_high.yclk = + amdgpu_dpm_get_mclk(adev, false) * 10; + wm_high.sclk = + amdgpu_dpm_get_sclk(adev, false) * 10; + } else { + wm_high.yclk = adev->pm.current_mclk * 10; + wm_high.sclk = adev->pm.current_sclk * 10; + } + + wm_high.disp_clk = mode->clock; + wm_high.src_width = mode->crtc_hdisplay; + wm_high.active_time = mode->crtc_hdisplay * pixel_period; + wm_high.blank_time = line_time - wm_high.active_time; + wm_high.interlaced = false; + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + wm_high.interlaced = true; + wm_high.vsc = amdgpu_crtc->vsc; + wm_high.vtaps = 1; + if (amdgpu_crtc->rmx_type != RMX_OFF) + wm_high.vtaps = 2; + wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ + wm_high.lb_size = lb_size; + wm_high.dram_channels = cik_get_number_of_dram_channels(adev); + wm_high.num_heads = num_heads; + + /* set for high clocks */ + latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); + + /* possibly force display priority to high */ + /* should really do this at mode validation time... */ + if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || + !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || + !dce_v11_0_check_latency_hiding(&wm_high) || + (adev->mode_info.disp_priority == 2)) { + DRM_DEBUG_KMS("force priority to high\n"); + } + + /* watermark for low clocks */ + if (adev->pm.dpm_enabled) { + wm_low.yclk = + amdgpu_dpm_get_mclk(adev, true) * 10; + wm_low.sclk = + amdgpu_dpm_get_sclk(adev, true) * 10; + } else { + wm_low.yclk = adev->pm.current_mclk * 10; + wm_low.sclk = adev->pm.current_sclk * 10; + } + + wm_low.disp_clk = mode->clock; + wm_low.src_width = mode->crtc_hdisplay; + wm_low.active_time = mode->crtc_hdisplay * pixel_period; + wm_low.blank_time = line_time - wm_low.active_time; + wm_low.interlaced = false; + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + wm_low.interlaced = true; + wm_low.vsc = amdgpu_crtc->vsc; + wm_low.vtaps = 1; + if (amdgpu_crtc->rmx_type != RMX_OFF) + wm_low.vtaps = 2; + wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ + wm_low.lb_size = lb_size; + wm_low.dram_channels = cik_get_number_of_dram_channels(adev); + wm_low.num_heads = num_heads; + + /* set for low clocks */ + latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); + + /* possibly force display priority to high */ + /* should really do this at mode validation time... */ + if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || + !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || + !dce_v11_0_check_latency_hiding(&wm_low) || + (adev->mode_info.disp_priority == 2)) { + DRM_DEBUG_KMS("force priority to high\n"); + } + } + + /* select wm A */ + wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); + tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); + tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); + /* select wm B */ + tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); + tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); + tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); + /* restore original selection */ + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); + + /* save values for DPM */ + amdgpu_crtc->line_time = line_time; + amdgpu_crtc->wm_high = latency_watermark_a; + amdgpu_crtc->wm_low = latency_watermark_b; +} + +/** + * dce_v11_0_bandwidth_update - program display watermarks + * + * @adev: amdgpu_device pointer + * + * Calculate and program the display watermarks and line + * buffer allocation (CIK). + */ +static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) +{ + struct drm_display_mode *mode = NULL; + u32 num_heads = 0, lb_size; + int i; + + amdgpu_update_display_priority(adev); + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (adev->mode_info.crtcs[i]->base.enabled) + num_heads++; + } + for (i = 0; i < adev->mode_info.num_crtc; i++) { + mode = &adev->mode_info.crtcs[i]->base.mode; + lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); + dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], + lb_size, num_heads); + } +} + +static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) +{ + int i; + u32 offset, tmp; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + offset = adev->mode_info.audio.pin[i].offset; + tmp = RREG32_AUDIO_ENDPT(offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); + if (((tmp & + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> + AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) + adev->mode_info.audio.pin[i].connected = false; + else + adev->mode_info.audio.pin[i].connected = true; + } +} + +static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) +{ + int i; + + dce_v11_0_audio_get_connected_pins(adev); + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + if (adev->mode_info.audio.pin[i].connected) + return &adev->mode_info.audio.pin[i]; + } + DRM_ERROR("No connected audio pins found!\n"); + return NULL; +} + +static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 tmp; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); + WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); +} + +static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, + struct drm_display_mode *mode) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + u32 tmp; + int interlace = 0; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + interlace = 1; + if (connector->latency_present[interlace]) { + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + VIDEO_LIPSYNC, connector->video_latency[interlace]); + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + AUDIO_LIPSYNC, connector->audio_latency[interlace]); + } else { + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + VIDEO_LIPSYNC, 0); + tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, + AUDIO_LIPSYNC, 0); + } + WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); +} + +static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + u32 tmp; + u8 *sadb = NULL; + int sad_count; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); + if (sad_count < 0) { + DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); + sad_count = 0; + } + + /* program the speaker allocation */ + tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + DP_CONNECTION, 0); + /* set HDMI mode */ + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + HDMI_CONNECTION, 1); + if (sad_count) + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + SPEAKER_ALLOCATION, sadb[0]); + else + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, + SPEAKER_ALLOCATION, 5); /* stereo */ + WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, + ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); + + kfree(sadb); +} + +static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector; + struct amdgpu_connector *amdgpu_connector = NULL; + struct cea_sad *sads; + int i, sad_count; + + static const u16 eld_reg_to_type[][2] = { + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, + { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, + }; + + if (!dig || !dig->afmt || !dig->afmt->pin) + return; + + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + amdgpu_connector = to_amdgpu_connector(connector); + break; + } + } + + if (!amdgpu_connector) { + DRM_ERROR("Couldn't find encoder's connector\n"); + return; + } + + sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); + if (sad_count <= 0) { + DRM_ERROR("Couldn't read SADs: %d\n", sad_count); + return; + } + BUG_ON(!sads); + + for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { + u32 tmp = 0; + u8 stereo_freqs = 0; + int max_channels = -1; + int j; + + for (j = 0; j < sad_count; j++) { + struct cea_sad *sad = &sads[j]; + + if (sad->format == eld_reg_to_type[i][1]) { + if (sad->channels > max_channels) { + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + MAX_CHANNELS, sad->channels); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + DESCRIPTOR_BYTE_2, sad->byte2); + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + SUPPORTED_FREQUENCIES, sad->freq); + max_channels = sad->channels; + } + + if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) + stereo_freqs |= sad->freq; + else + break; + } + } + + tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, + SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); + WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); + } + + kfree(sads); +} + +static void dce_v11_0_audio_enable(struct amdgpu_device *adev, + struct amdgpu_audio_pin *pin, + bool enable) +{ + if (!pin) + return; + + WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, + enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); +} + +static const u32 pin_offsets[] = +{ + AUD0_REGISTER_OFFSET, + AUD1_REGISTER_OFFSET, + AUD2_REGISTER_OFFSET, + AUD3_REGISTER_OFFSET, + AUD4_REGISTER_OFFSET, + AUD5_REGISTER_OFFSET, + AUD6_REGISTER_OFFSET, +}; + +static int dce_v11_0_audio_init(struct amdgpu_device *adev) +{ + int i; + + if (!amdgpu_audio) + return 0; + + adev->mode_info.audio.enabled = true; + + adev->mode_info.audio.num_pins = 7; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + adev->mode_info.audio.pin[i].channels = -1; + adev->mode_info.audio.pin[i].rate = -1; + adev->mode_info.audio.pin[i].bits_per_sample = -1; + adev->mode_info.audio.pin[i].status_bits = 0; + adev->mode_info.audio.pin[i].category_code = 0; + adev->mode_info.audio.pin[i].connected = false; + adev->mode_info.audio.pin[i].offset = pin_offsets[i]; + adev->mode_info.audio.pin[i].id = i; + /* disable audio. it will be set up later */ + /* XXX remove once we switch to ip funcs */ + dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + } + + return 0; +} + +static void dce_v11_0_audio_fini(struct amdgpu_device *adev) +{ + int i; + + if (!adev->mode_info.audio.enabled) + return; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) + dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + + adev->mode_info.audio.enabled = false; +} + +/* + * update the N and CTS parameters for a given pixel clock rate + */ +static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + u32 tmp; + + tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); + WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); + tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); + WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); + WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); + tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); + WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); + WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); + tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); + WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); + +} + +/* + * build a HDMI Video Info Frame + */ +static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, + void *buffer, size_t size) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + uint8_t *frame = buffer + 3; + uint8_t *header = buffer; + + WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, + frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); + WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, + frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); + WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, + frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); + WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, + frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); +} + +static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + u32 dto_phase = 24 * 1000; + u32 dto_modulo = clock; + u32 tmp; + + if (!dig || !dig->afmt) + return; + + /* XXX two dtos; generally use dto0 for hdmi */ + /* Express [24MHz / target pixel clock] as an exact rational + * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE + * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator + */ + tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); + tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, + amdgpu_crtc->crtc_id); + WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); + WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); + WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); +} + +/* + * update the info frames with the data from the current display mode + */ +static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, + struct drm_display_mode *mode) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; + struct hdmi_avi_infoframe frame; + ssize_t err; + u32 tmp; + int bpc = 8; + + if (!dig || !dig->afmt) + return; + + /* Silent, r600_hdmi_enable will raise WARN for us */ + if (!dig->afmt->enabled) + return; + + /* hdmi deep color mode general control packets setup, if bpc > 8 */ + if (encoder->crtc) { + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); + bpc = amdgpu_crtc->bpc; + } + + /* disable audio prior to setting up hw */ + dig->afmt->pin = dce_v11_0_audio_get_pin(adev); + dce_v11_0_audio_enable(adev, dig->afmt->pin, false); + + dce_v11_0_audio_set_dto(encoder, mode->clock); + + tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); + WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ + + WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); + + tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); + switch (bpc) { + case 0: + case 6: + case 8: + case 16: + default: + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); + DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", + connector->name, bpc); + break; + case 10: + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); + DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", + connector->name); + break; + case 12: + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); + DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", + connector->name); + break; + } + WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ + tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ + WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); + /* enable audio info frames (frames won't be set until audio is enabled) */ + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); + /* required for audio info values to be updated */ + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); + WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); + /* required for audio info values to be updated */ + tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); + WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); + /* anything other than 0 */ + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); + WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); + + WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ + + tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); + /* set the default audio delay */ + tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); + /* should be suffient for all audio modes and small enough for all hblanks */ + tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); + WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); + /* allow 60958 channel status fields to be updated */ + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); + WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); + if (bpc > 8) + /* clear SW CTS value */ + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); + else + /* select SW CTS value */ + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); + /* allow hw to sent ACR packets when required */ + tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); + WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); + + dce_v11_0_afmt_update_ACR(encoder, mode->clock); + + tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); + WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); + WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); + tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); + WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); + + dce_v11_0_audio_write_speaker_allocation(encoder); + + WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, + (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); + + dce_v11_0_afmt_audio_select_pin(encoder); + dce_v11_0_audio_write_sad_regs(encoder); + dce_v11_0_audio_write_latency_fields(encoder, mode); + + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); + if (err < 0) { + DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); + return; + } + + err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); + if (err < 0) { + DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); + return; + } + + dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); + + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); + /* enable AVI info frames */ + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); + /* required for audio info values to be updated */ + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); + WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); + + tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); + tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); + WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); + + tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); + /* send audio packets */ + tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); + WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); + + WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); + WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); + WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); + WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); + + /* enable audio after to setting up hw */ + dce_v11_0_audio_enable(adev, dig->afmt->pin, true); +} + +static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + + if (!dig || !dig->afmt) + return; + + /* Silent, r600_hdmi_enable will raise WARN for us */ + if (enable && dig->afmt->enabled) + return; + if (!enable && !dig->afmt->enabled) + return; + + if (!enable && dig->afmt->pin) { + dce_v11_0_audio_enable(adev, dig->afmt->pin, false); + dig->afmt->pin = NULL; + } + + dig->afmt->enabled = enable; + + DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", + enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); +} + +static void dce_v11_0_afmt_init(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->mode_info.num_dig; i++) + adev->mode_info.afmt[i] = NULL; + + /* DCE11 has audio blocks tied to DIG encoders */ + for (i = 0; i < adev->mode_info.num_dig; i++) { + adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); + if (adev->mode_info.afmt[i]) { + adev->mode_info.afmt[i]->offset = dig_offsets[i]; + adev->mode_info.afmt[i]->id = i; + } + } +} + +static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->mode_info.num_dig; i++) { + kfree(adev->mode_info.afmt[i]); + adev->mode_info.afmt[i] = NULL; + } +} + +static const u32 vga_control_regs[6] = +{ + mmD1VGA_CONTROL, + mmD2VGA_CONTROL, + mmD3VGA_CONTROL, + mmD4VGA_CONTROL, + mmD5VGA_CONTROL, + mmD6VGA_CONTROL, +}; + +static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + u32 vga_control; + + vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; + if (enable) + WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); + else + WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); +} + +static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + + if (enable) + WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); + else + WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); +} + +static void dce_v11_0_tiling_fields(uint64_t tiling_flags, unsigned *bankw, + unsigned *bankh, unsigned *mtaspect, + unsigned *tile_split) +{ + *bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK; + *bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK; + *mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK; + *tile_split = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK; + switch (*bankw) { + default: + case 1: + *bankw = ADDR_SURF_BANK_WIDTH_1; + break; + case 2: + *bankw = ADDR_SURF_BANK_WIDTH_2; + break; + case 4: + *bankw = ADDR_SURF_BANK_WIDTH_4; + break; + case 8: + *bankw = ADDR_SURF_BANK_WIDTH_8; + break; + } + switch (*bankh) { + default: + case 1: + *bankh = ADDR_SURF_BANK_HEIGHT_1; + break; + case 2: + *bankh = ADDR_SURF_BANK_HEIGHT_2; + break; + case 4: + *bankh = ADDR_SURF_BANK_HEIGHT_4; + break; + case 8: + *bankh = ADDR_SURF_BANK_HEIGHT_8; + break; + } + switch (*mtaspect) { + default: + case 1: + *mtaspect = ADDR_SURF_MACRO_ASPECT_1; + break; + case 2: + *mtaspect = ADDR_SURF_MACRO_ASPECT_2; + break; + case 4: + *mtaspect = ADDR_SURF_MACRO_ASPECT_4; + break; + case 8: + *mtaspect = ADDR_SURF_MACRO_ASPECT_8; + break; + } +} + +static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int x, int y, int atomic) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_framebuffer *amdgpu_fb; + struct drm_framebuffer *target_fb; + struct drm_gem_object *obj; + struct amdgpu_bo *rbo; + uint64_t fb_location, tiling_flags; + uint32_t fb_format, fb_pitch_pixels; + unsigned bankw, bankh, mtaspect, tile_split; + u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); + /* XXX change to VI */ + u32 pipe_config = (adev->gfx.config.tile_mode_array[10] >> 6) & 0x1f; + u32 tmp, viewport_w, viewport_h; + int r; + bool bypass_lut = false; + + /* no fb bound */ + if (!atomic && !crtc->primary->fb) { + DRM_DEBUG_KMS("No FB bound\n"); + return 0; + } + + if (atomic) { + amdgpu_fb = to_amdgpu_framebuffer(fb); + target_fb = fb; + } + else { + amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); + target_fb = crtc->primary->fb; + } + + /* If atomic, assume fb object is pinned & idle & fenced and + * just update base pointers + */ + obj = amdgpu_fb->obj; + rbo = gem_to_amdgpu_bo(obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r != 0)) + return r; + + if (atomic) + fb_location = amdgpu_bo_gpu_offset(rbo); + else { + r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); + if (unlikely(r != 0)) { + amdgpu_bo_unreserve(rbo); + return -EINVAL; + } + } + + amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); + amdgpu_bo_unreserve(rbo); + + switch (target_fb->pixel_format) { + case DRM_FORMAT_C8: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); + break; + case DRM_FORMAT_XRGB4444: + case DRM_FORMAT_ARGB4444: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN16); +#endif + break; + case DRM_FORMAT_XRGB1555: + case DRM_FORMAT_ARGB1555: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN16); +#endif + break; + case DRM_FORMAT_BGRX5551: + case DRM_FORMAT_BGRA5551: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN16); +#endif + break; + case DRM_FORMAT_RGB565: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN16); +#endif + break; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN32); +#endif + break; + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN32); +#endif + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ + bypass_lut = true; + break; + case DRM_FORMAT_BGRX1010102: + case DRM_FORMAT_BGRA1010102: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN32); +#endif + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ + bypass_lut = true; + break; + default: + DRM_ERROR("Unsupported screen format %s\n", + drm_get_format_name(target_fb->pixel_format)); + return -EINVAL; + } + + if (tiling_flags & AMDGPU_TILING_MACRO) { + unsigned tileb, index, num_banks, tile_split_bytes; + + dce_v11_0_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); + /* Set NUM_BANKS. */ + /* Calculate the macrotile mode index. */ + tile_split_bytes = 64 << tile_split; + tileb = 8 * 8 * target_fb->bits_per_pixel / 8; + tileb = min(tile_split_bytes, tileb); + + for (index = 0; tileb > 64; index++) { + tileb >>= 1; + } + + if (index >= 16) { + DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", + target_fb->bits_per_pixel, tile_split); + return -EINVAL; + } + + /* XXX fix me for VI */ + num_banks = (adev->gfx.config.macrotile_mode_array[index] >> 6) & 0x3; + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, + ARRAY_2D_TILED_THIN1); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, + tile_split); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, + mtaspect); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, + ADDR_SURF_MICRO_TILING_DISPLAY); + } else if (tiling_flags & AMDGPU_TILING_MICRO) { + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, + ARRAY_1D_TILED_THIN1); + } + + /* Read the pipe config from the 2D TILED SCANOUT mode. + * It should be the same for the other modes too, but not all + * modes set the pipe config field. */ + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, + pipe_config); + + dce_v11_0_vga_enable(crtc, false); + + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(fb_location)); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(fb_location)); + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); + WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); + WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); + WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); + + /* + * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT + * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to + * retain the full precision throughout the pipeline. + */ + tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); + if (bypass_lut) + tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); + else + tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); + WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); + + if (bypass_lut) + DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); + + WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); + WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); + WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); + + fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); + + dce_v11_0_grph_enable(crtc, true); + + WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, + target_fb->height); + + x &= ~3; + y &= ~1; + WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, + (x << 16) | y); + viewport_w = crtc->mode.hdisplay; + viewport_h = (crtc->mode.vdisplay + 1) & ~1; + WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, + (viewport_w << 16) | viewport_h); + + /* pageflip setup */ + /* make sure flip is at vb rather than hb */ + tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, + GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + /* set pageflip to happen only at start of vblank interval (front porch) */ + WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); + + if (!atomic && fb && fb != crtc->primary->fb) { + amdgpu_fb = to_amdgpu_framebuffer(fb); + rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r != 0)) + return r; + amdgpu_bo_unpin(rbo); + amdgpu_bo_unreserve(rbo); + } + + /* Bytes per pixel may have changed */ + dce_v11_0_bandwidth_update(adev); + + return 0; +} + +static void dce_v11_0_set_interleave(struct drm_crtc *crtc, + struct drm_display_mode *mode) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + u32 tmp; + + tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); + else + tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); + WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); +} + +static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + int i; + u32 tmp; + + DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); + + tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); + WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); + WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); + WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); + + WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); + + WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); + WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); + + WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); + WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); + + WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); + for (i = 0; i < 256; i++) { + WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, + (amdgpu_crtc->lut_r[i] << 20) | + (amdgpu_crtc->lut_g[i] << 10) | + (amdgpu_crtc->lut_b[i] << 0)); + } + + tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); + tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); + tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); + WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); + WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); + WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); + WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); + + /* XXX match this to the depth of the crtc fmt block, move to modeset? */ + WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); + /* XXX this only needs to be programmed once per crtc at startup, + * not sure where the best place for it is + */ + tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); + WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); +} + +static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + if (dig->linkb) + return 1; + else + return 0; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + if (dig->linkb) + return 3; + else + return 2; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + if (dig->linkb) + return 5; + else + return 4; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + return 6; + break; + default: + DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); + return 0; + } +} + +/** + * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. + * + * @crtc: drm crtc + * + * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors + * a single PPLL can be used for all DP crtcs/encoders. For non-DP + * monitors a dedicated PPLL must be used. If a particular board has + * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming + * as there is no need to program the PLL itself. If we are not able to + * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to + * avoid messing up an existing monitor. + * + * Asic specific PLL information + * + * DCE 10.x + * Tonga + * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) + * CI + * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC + * + */ +static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + u32 pll_in_use; + int pll; + + if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { + if (adev->clock.dp_extclk) + /* skip PPLL programming if using ext clock */ + return ATOM_PPLL_INVALID; + else { + /* use the same PPLL for all DP monitors */ + pll = amdgpu_pll_get_shared_dp_ppll(crtc); + if (pll != ATOM_PPLL_INVALID) + return pll; + } + } else { + /* use the same PPLL for all monitors with the same clock */ + pll = amdgpu_pll_get_shared_nondp_ppll(crtc); + if (pll != ATOM_PPLL_INVALID) + return pll; + } + + /* XXX need to determine what plls are available on each DCE11 part */ + pll_in_use = amdgpu_pll_get_use_mask(crtc); + if (adev->asic_type == CHIP_CARRIZO) { + if (!(pll_in_use & (1 << ATOM_PPLL1))) + return ATOM_PPLL1; + if (!(pll_in_use & (1 << ATOM_PPLL0))) + return ATOM_PPLL0; + DRM_ERROR("unable to allocate a PPLL\n"); + return ATOM_PPLL_INVALID; + } else { + if (!(pll_in_use & (1 << ATOM_PPLL2))) + return ATOM_PPLL2; + if (!(pll_in_use & (1 << ATOM_PPLL1))) + return ATOM_PPLL1; + if (!(pll_in_use & (1 << ATOM_PPLL0))) + return ATOM_PPLL0; + DRM_ERROR("unable to allocate a PPLL\n"); + return ATOM_PPLL_INVALID; + } + return ATOM_PPLL_INVALID; +} + +static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) +{ + struct amdgpu_device *adev = crtc->dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + uint32_t cur_lock; + + cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); + if (lock) + cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); + else + cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); + WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); +} + +static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + u32 tmp; + + tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); +} + +static void dce_v11_0_show_cursor(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + u32 tmp; + + tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); + tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); + tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); +} + +static void dce_v11_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, + uint64_t gpu_addr) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + + WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(gpu_addr)); + WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + lower_32_bits(gpu_addr)); +} + +static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, + int x, int y) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = crtc->dev->dev_private; + int xorigin = 0, yorigin = 0; + + /* avivo cursor are offset into the total surface */ + x += crtc->x; + y += crtc->y; + DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); + + if (x < 0) { + xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); + x = 0; + } + if (y < 0) { + yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); + y = 0; + } + + dce_v11_0_lock_cursor(crtc, true); + WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); + WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); + WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, + ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); + dce_v11_0_lock_cursor(crtc, false); + + return 0; +} + +static int dce_v11_0_crtc_cursor_set(struct drm_crtc *crtc, + struct drm_file *file_priv, + uint32_t handle, + uint32_t width, + uint32_t height) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_gem_object *obj; + struct amdgpu_bo *robj; + uint64_t gpu_addr; + int ret; + + if (!handle) { + /* turn off cursor */ + dce_v11_0_hide_cursor(crtc); + obj = NULL; + goto unpin; + } + + if ((width > amdgpu_crtc->max_cursor_width) || + (height > amdgpu_crtc->max_cursor_height)) { + DRM_ERROR("bad cursor width or height %d x %d\n", width, height); + return -EINVAL; + } + + obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); + if (!obj) { + DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); + return -ENOENT; + } + + robj = gem_to_amdgpu_bo(obj); + ret = amdgpu_bo_reserve(robj, false); + if (unlikely(ret != 0)) + goto fail; + ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, + 0, &gpu_addr); + amdgpu_bo_unreserve(robj); + if (ret) + goto fail; + + amdgpu_crtc->cursor_width = width; + amdgpu_crtc->cursor_height = height; + + dce_v11_0_lock_cursor(crtc, true); + dce_v11_0_set_cursor(crtc, obj, gpu_addr); + dce_v11_0_show_cursor(crtc); + dce_v11_0_lock_cursor(crtc, false); + +unpin: + if (amdgpu_crtc->cursor_bo) { + robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); + ret = amdgpu_bo_reserve(robj, false); + if (likely(ret == 0)) { + amdgpu_bo_unpin(robj); + amdgpu_bo_unreserve(robj); + } + drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); + } + + amdgpu_crtc->cursor_bo = obj; + return 0; +fail: + drm_gem_object_unreference_unlocked(obj); + + return ret; +} + +static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t start, uint32_t size) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + int end = (start + size > 256) ? 256 : start + size, i; + + /* userspace palettes are always correct as is */ + for (i = start; i < end; i++) { + amdgpu_crtc->lut_r[i] = red[i] >> 6; + amdgpu_crtc->lut_g[i] = green[i] >> 6; + amdgpu_crtc->lut_b[i] = blue[i] >> 6; + } + dce_v11_0_crtc_load_lut(crtc); +} + +static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + drm_crtc_cleanup(crtc); + destroy_workqueue(amdgpu_crtc->pflip_queue); + kfree(amdgpu_crtc); +} + +static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { + .cursor_set = dce_v11_0_crtc_cursor_set, + .cursor_move = dce_v11_0_crtc_cursor_move, + .gamma_set = dce_v11_0_crtc_gamma_set, + .set_config = amdgpu_crtc_set_config, + .destroy = dce_v11_0_crtc_destroy, + .page_flip = amdgpu_crtc_page_flip, +}; + +static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + switch (mode) { + case DRM_MODE_DPMS_ON: + amdgpu_crtc->enabled = true; + amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); + dce_v11_0_vga_enable(crtc, true); + amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); + dce_v11_0_vga_enable(crtc, false); + drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); + dce_v11_0_crtc_load_lut(crtc); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id); + if (amdgpu_crtc->enabled) { + dce_v11_0_vga_enable(crtc, true); + amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); + dce_v11_0_vga_enable(crtc, false); + } + amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); + amdgpu_crtc->enabled = false; + break; + } + /* adjust pm to dpms */ + amdgpu_pm_compute_clocks(adev); +} + +static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) +{ + /* disable crtc pair power gating before programming */ + amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); + amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); + dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); +} + +static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) +{ + dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); + amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); +} + +static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_atom_ss ss; + int i; + + dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); + if (crtc->primary->fb) { + int r; + struct amdgpu_framebuffer *amdgpu_fb; + struct amdgpu_bo *rbo; + + amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); + rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r)) + DRM_ERROR("failed to reserve rbo before unpin\n"); + else { + amdgpu_bo_unpin(rbo); + amdgpu_bo_unreserve(rbo); + } + } + /* disable the GRPH */ + dce_v11_0_grph_enable(crtc, false); + + amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (adev->mode_info.crtcs[i] && + adev->mode_info.crtcs[i]->enabled && + i != amdgpu_crtc->crtc_id && + amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { + /* one other crtc is using this pll don't turn + * off the pll + */ + goto done; + } + } + + switch (amdgpu_crtc->pll_id) { + case ATOM_PPLL0: + case ATOM_PPLL1: + case ATOM_PPLL2: + /* disable the ppll */ + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, + 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); + break; + default: + break; + } +done: + amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; + amdgpu_crtc->adjusted_clock = 0; + amdgpu_crtc->encoder = NULL; + amdgpu_crtc->connector = NULL; +} + +static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode, + int x, int y, struct drm_framebuffer *old_fb) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + if (!amdgpu_crtc->adjusted_clock) + return -EINVAL; + + amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); + amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); + dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); + amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); + amdgpu_atombios_crtc_scaler_setup(crtc); + /* update the hw version fpr dpm */ + amdgpu_crtc->hw_mode = *adjusted_mode; + + return 0; +} + +static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct drm_encoder *encoder; + + /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + amdgpu_crtc->encoder = encoder; + amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); + break; + } + } + if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { + amdgpu_crtc->encoder = NULL; + amdgpu_crtc->connector = NULL; + return false; + } + if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) + return false; + if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) + return false; + /* pick pll */ + amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); + /* if we can't get a PPLL for a non-DP encoder, fail */ + if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && + !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) + return false; + + return true; +} + +static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, + struct drm_framebuffer *old_fb) +{ + return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); +} + +static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + int x, int y, enum mode_set_atomic state) +{ + return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); +} + +static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { + .dpms = dce_v11_0_crtc_dpms, + .mode_fixup = dce_v11_0_crtc_mode_fixup, + .mode_set = dce_v11_0_crtc_mode_set, + .mode_set_base = dce_v11_0_crtc_set_base, + .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, + .prepare = dce_v11_0_crtc_prepare, + .commit = dce_v11_0_crtc_commit, + .load_lut = dce_v11_0_crtc_load_lut, + .disable = dce_v11_0_crtc_disable, +}; + +static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) +{ + struct amdgpu_crtc *amdgpu_crtc; + int i; + + amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + + (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); + if (amdgpu_crtc == NULL) + return -ENOMEM; + + drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); + + drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); + amdgpu_crtc->crtc_id = index; + amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue"); + adev->mode_info.crtcs[index] = amdgpu_crtc; + + amdgpu_crtc->max_cursor_width = 128; + amdgpu_crtc->max_cursor_height = 128; + adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; + adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; + + for (i = 0; i < 256; i++) { + amdgpu_crtc->lut_r[i] = i << 2; + amdgpu_crtc->lut_g[i] = i << 2; + amdgpu_crtc->lut_b[i] = i << 2; + } + + switch (amdgpu_crtc->crtc_id) { + case 0: + default: + amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; + break; + case 1: + amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; + break; + case 2: + amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; + break; + case 3: + amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; + break; + case 4: + amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; + break; + case 5: + amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; + break; + } + + amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; + amdgpu_crtc->adjusted_clock = 0; + amdgpu_crtc->encoder = NULL; + amdgpu_crtc->connector = NULL; + drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); + + return 0; +} + +static int dce_v11_0_early_init(struct amdgpu_device *adev) +{ + adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; + adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; + + dce_v11_0_set_display_funcs(adev); + dce_v11_0_set_irq_funcs(adev); + + switch (adev->asic_type) { + case CHIP_CARRIZO: + adev->mode_info.num_crtc = 4; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 9; + break; + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + + return 0; +} + +static int dce_v11_0_sw_init(struct amdgpu_device *adev) +{ + int r, i; + + for (i = 0; i < adev->mode_info.num_crtc; i++) { + r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); + if (r) + return r; + } + + for (i = 8; i < 20; i += 2) { + r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); + if (r) + return r; + } + + /* HPD hotplug */ + r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); + if (r) + return r; + + adev->mode_info.mode_config_initialized = true; + + adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; + + adev->ddev->mode_config.max_width = 16384; + adev->ddev->mode_config.max_height = 16384; + + adev->ddev->mode_config.preferred_depth = 24; + adev->ddev->mode_config.prefer_shadow = 1; + + adev->ddev->mode_config.fb_base = adev->mc.aper_base; + + r = amdgpu_modeset_create_props(adev); + if (r) + return r; + + adev->ddev->mode_config.max_width = 16384; + adev->ddev->mode_config.max_height = 16384; + + /* allocate crtcs */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + r = dce_v11_0_crtc_init(adev, i); + if (r) + return r; + } + + if (amdgpu_atombios_get_connector_info_from_object_table(adev)) + amdgpu_print_display_setup(adev->ddev); + else + return -EINVAL; + + /* setup afmt */ + dce_v11_0_afmt_init(adev); + + r = dce_v11_0_audio_init(adev); + if (r) + return r; + + drm_kms_helper_poll_init(adev->ddev); + + return r; +} + +static int dce_v11_0_sw_fini(struct amdgpu_device *adev) +{ + kfree(adev->mode_info.bios_hardcoded_edid); + + drm_kms_helper_poll_fini(adev->ddev); + + dce_v11_0_audio_fini(adev); + + dce_v11_0_afmt_fini(adev); + + adev->mode_info.mode_config_initialized = false; + + return 0; +} + +static int dce_v11_0_hw_init(struct amdgpu_device *adev) +{ + int i; + + dce_v11_0_init_golden_registers(adev); + + /* init dig PHYs, disp eng pll */ + amdgpu_atombios_encoder_init_dig(adev); + amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); + + /* initialize hpd */ + dce_v11_0_hpd_init(adev); + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + } + + return 0; +} + +static int dce_v11_0_hw_fini(struct amdgpu_device *adev) +{ + int i; + + dce_v11_0_hpd_fini(adev); + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); + } + + return 0; +} + +static int dce_v11_0_suspend(struct amdgpu_device *adev) +{ + struct drm_connector *connector; + + drm_kms_helper_poll_disable(adev->ddev); + + /* turn off display hw */ + list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); + } + + amdgpu_atombios_scratch_regs_save(adev); + + dce_v11_0_hpd_fini(adev); + + return 0; +} + +static int dce_v11_0_resume(struct amdgpu_device *adev) +{ + struct drm_connector *connector; + + dce_v11_0_init_golden_registers(adev); + + amdgpu_atombios_scratch_regs_restore(adev); + + /* init dig PHYs, disp eng pll */ + amdgpu_atombios_crtc_powergate_init(adev); + amdgpu_atombios_encoder_init_dig(adev); + amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); + /* turn on the BL */ + if (adev->mode_info.bl_encoder) { + u8 bl_level = amdgpu_display_backlight_get_level(adev, + adev->mode_info.bl_encoder); + amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, + bl_level); + } + + /* initialize hpd */ + dce_v11_0_hpd_init(adev); + + /* blat the mode back in */ + drm_helper_resume_force_mode(adev->ddev); + /* turn on display hw */ + list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); + } + + drm_kms_helper_poll_enable(adev->ddev); + + return 0; +} + +static bool dce_v11_0_is_idle(struct amdgpu_device *adev) +{ + /* XXX todo */ + return true; +} + +static int dce_v11_0_wait_for_idle(struct amdgpu_device *adev) +{ + /* XXX todo */ + return 0; +} + +static void dce_v11_0_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "DCE 10.x registers\n"); + /* XXX todo */ +} + +static int dce_v11_0_soft_reset(struct amdgpu_device *adev) +{ + u32 srbm_soft_reset = 0, tmp; + + if (dce_v11_0_is_display_hung(adev)) + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; + + if (srbm_soft_reset) { + dce_v11_0_print_status(adev); + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + dce_v11_0_print_status(adev); + } + return 0; +} + +static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, + int crtc, + enum amdgpu_interrupt_state state) +{ + u32 lb_interrupt_mask; + + if (crtc >= adev->mode_info.num_crtc) { + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); + lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, + VBLANK_INTERRUPT_MASK, 0); + WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); + break; + case AMDGPU_IRQ_STATE_ENABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); + lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, + VBLANK_INTERRUPT_MASK, 1); + WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); + break; + default: + break; + } +} + +static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, + int crtc, + enum amdgpu_interrupt_state state) +{ + u32 lb_interrupt_mask; + + if (crtc >= adev->mode_info.num_crtc) { + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); + lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, + VLINE_INTERRUPT_MASK, 0); + WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); + break; + case AMDGPU_IRQ_STATE_ENABLE: + lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); + lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, + VLINE_INTERRUPT_MASK, 1); + WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); + break; + default: + break; + } +} + +static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned hpd, + enum amdgpu_interrupt_state state) +{ + u32 tmp; + + if (hpd >= adev->mode_info.num_hpd) { + DRM_DEBUG("invalid hdp %d\n", hpd); + return 0; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); + break; + case AMDGPU_IRQ_STATE_ENABLE: + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); + break; + default: + break; + } + + return 0; +} + +static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + switch (type) { + case AMDGPU_CRTC_IRQ_VBLANK1: + dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK2: + dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK3: + dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK4: + dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK5: + dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); + break; + case AMDGPU_CRTC_IRQ_VBLANK6: + dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); + break; + case AMDGPU_CRTC_IRQ_VLINE1: + dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); + break; + case AMDGPU_CRTC_IRQ_VLINE2: + dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); + break; + case AMDGPU_CRTC_IRQ_VLINE3: + dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); + break; + case AMDGPU_CRTC_IRQ_VLINE4: + dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); + break; + case AMDGPU_CRTC_IRQ_VLINE5: + dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); + break; + case AMDGPU_CRTC_IRQ_VLINE6: + dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); + break; + default: + break; + } + return 0; +} + +static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 reg, reg_block; + /* now deal with page flip IRQ */ + switch (type) { + case AMDGPU_PAGEFLIP_IRQ_D1: + reg_block = CRTC0_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D2: + reg_block = CRTC1_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D3: + reg_block = CRTC2_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D4: + reg_block = CRTC3_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D5: + reg_block = CRTC4_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D6: + reg_block = CRTC5_REGISTER_OFFSET; + break; + default: + DRM_ERROR("invalid pageflip crtc %d\n", type); + return -EINVAL; + } + + reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); + if (state == AMDGPU_IRQ_STATE_DISABLE) + WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + else + WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + + return 0; +} + +static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + int reg_block; + unsigned long flags; + unsigned crtc_id; + struct amdgpu_crtc *amdgpu_crtc; + struct amdgpu_flip_work *works; + + crtc_id = (entry->src_id - 8) >> 1; + amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; + + /* ack the interrupt */ + switch(crtc_id){ + case AMDGPU_PAGEFLIP_IRQ_D1: + reg_block = CRTC0_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D2: + reg_block = CRTC1_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D3: + reg_block = CRTC2_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D4: + reg_block = CRTC3_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D5: + reg_block = CRTC4_REGISTER_OFFSET; + break; + case AMDGPU_PAGEFLIP_IRQ_D6: + reg_block = CRTC5_REGISTER_OFFSET; + break; + default: + DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); + return -EINVAL; + } + + if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) + WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); + + /* IRQ could occur when in initial stage */ + if(amdgpu_crtc == NULL) + return 0; + + spin_lock_irqsave(&adev->ddev->event_lock, flags); + works = amdgpu_crtc->pflip_works; + if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ + DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " + "AMDGPU_FLIP_SUBMITTED(%d)\n", + amdgpu_crtc->pflip_status, + AMDGPU_FLIP_SUBMITTED); + spin_unlock_irqrestore(&adev->ddev->event_lock, flags); + return 0; + } + + /* page flip completed. clean up */ + amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; + amdgpu_crtc->pflip_works = NULL; + + /* wakeup usersapce */ + if(works->event) + drm_send_vblank_event(adev->ddev, crtc_id, works->event); + + spin_unlock_irqrestore(&adev->ddev->event_lock, flags); + + drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); + amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id); + queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); + + return 0; +} + +static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, + int hpd) +{ + u32 tmp; + + if (hpd >= adev->mode_info.num_hpd) { + DRM_DEBUG("invalid hdp %d\n", hpd); + return; + } + + tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); + tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); + WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); +} + +static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, + int crtc) +{ + u32 tmp; + + if (crtc >= adev->mode_info.num_crtc) { + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); + tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); + WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); +} + +static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, + int crtc) +{ + u32 tmp; + + if (crtc >= adev->mode_info.num_crtc) { + DRM_DEBUG("invalid crtc %d\n", crtc); + return; + } + + tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); + tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); + WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); +} + +static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + unsigned crtc = entry->src_id - 1; + uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); + unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); + + switch (entry->src_data) { + case 0: /* vblank */ + if (disp_int & interrupt_status_offsets[crtc].vblank) { + dce_v11_0_crtc_vblank_int_ack(adev, crtc); + if (amdgpu_irq_enabled(adev, source, irq_type)) { + drm_handle_vblank(adev->ddev, crtc); + } + DRM_DEBUG("IH: D%d vblank\n", crtc + 1); + } + break; + case 1: /* vline */ + if (disp_int & interrupt_status_offsets[crtc].vline) { + dce_v11_0_crtc_vline_int_ack(adev, crtc); + DRM_DEBUG("IH: D%d vline\n", crtc + 1); + } + break; + default: + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + break; + } + + return 0; +} + +static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + uint32_t disp_int, mask; + unsigned hpd; + + if (entry->src_data >= adev->mode_info.num_hpd) { + DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); + return 0; + } + + hpd = entry->src_data; + disp_int = RREG32(interrupt_status_offsets[hpd].reg); + mask = interrupt_status_offsets[hpd].hpd; + + if (disp_int & mask) { + dce_v11_0_hpd_int_ack(adev, hpd); + schedule_work(&adev->hotplug_work); + DRM_DEBUG("IH: HPD%d\n", hpd + 1); + } + + return 0; +} + +static int dce_v11_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static int dce_v11_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs dce_v11_0_ip_funcs = { + .early_init = dce_v11_0_early_init, + .late_init = NULL, + .sw_init = dce_v11_0_sw_init, + .sw_fini = dce_v11_0_sw_fini, + .hw_init = dce_v11_0_hw_init, + .hw_fini = dce_v11_0_hw_fini, + .suspend = dce_v11_0_suspend, + .resume = dce_v11_0_resume, + .is_idle = dce_v11_0_is_idle, + .wait_for_idle = dce_v11_0_wait_for_idle, + .soft_reset = dce_v11_0_soft_reset, + .print_status = dce_v11_0_print_status, + .set_clockgating_state = dce_v11_0_set_clockgating_state, + .set_powergating_state = dce_v11_0_set_powergating_state, +}; + +static void +dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + + amdgpu_encoder->pixel_clock = adjusted_mode->clock; + + /* need to call this here rather than in prepare() since we need some crtc info */ + amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); + + /* set scaler clears this on some chips */ + dce_v11_0_set_interleave(encoder->crtc, mode); + + if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { + dce_v11_0_afmt_enable(encoder, true); + dce_v11_0_afmt_setmode(encoder, adjusted_mode); + } +} + +static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) +{ + struct amdgpu_device *adev = encoder->dev->dev_private; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); + + if ((amdgpu_encoder->active_device & + (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || + (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != + ENCODER_OBJECT_ID_NONE)) { + struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + if (dig) { + dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); + if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) + dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; + } + } + + amdgpu_atombios_scratch_regs_lock(adev, true); + + if (connector) { + struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + + /* select the clock/data port if it uses a router */ + if (amdgpu_connector->router.cd_valid) + amdgpu_i2c_router_select_cd_port(amdgpu_connector); + + /* turn eDP panel on for mode set */ + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) + amdgpu_atombios_encoder_set_edp_panel_power(connector, + ATOM_TRANSMITTER_ACTION_POWER_ON); + } + + /* this is needed for the pll/ss setup to work correctly in some cases */ + amdgpu_atombios_encoder_set_crtc_source(encoder); + /* set up the FMT blocks */ + dce_v11_0_program_fmt(encoder); +} + +static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_device *adev = dev->dev_private; + + /* need to call this here as we need the crtc set up */ + amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); + amdgpu_atombios_scratch_regs_lock(adev, false); +} + +static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct amdgpu_encoder_atom_dig *dig; + + amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); + + if (amdgpu_atombios_encoder_is_digital(encoder)) { + if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) + dce_v11_0_afmt_enable(encoder, false); + dig = amdgpu_encoder->enc_priv; + dig->dig_encoder = -1; + } + amdgpu_encoder->active_device = 0; +} + +/* these are handled by the primary encoders */ +static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) +{ + +} + +static void dce_v11_0_ext_commit(struct drm_encoder *encoder) +{ + +} + +static void +dce_v11_0_ext_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + +} + +static void dce_v11_0_ext_disable(struct drm_encoder *encoder) +{ + +} + +static void +dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) +{ + +} + +static bool dce_v11_0_ext_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { + .dpms = dce_v11_0_ext_dpms, + .mode_fixup = dce_v11_0_ext_mode_fixup, + .prepare = dce_v11_0_ext_prepare, + .mode_set = dce_v11_0_ext_mode_set, + .commit = dce_v11_0_ext_commit, + .disable = dce_v11_0_ext_disable, + /* no detect for TMDS/LVDS yet */ +}; + +static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { + .dpms = amdgpu_atombios_encoder_dpms, + .mode_fixup = amdgpu_atombios_encoder_mode_fixup, + .prepare = dce_v11_0_encoder_prepare, + .mode_set = dce_v11_0_encoder_mode_set, + .commit = dce_v11_0_encoder_commit, + .disable = dce_v11_0_encoder_disable, + .detect = amdgpu_atombios_encoder_dig_detect, +}; + +static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { + .dpms = amdgpu_atombios_encoder_dpms, + .mode_fixup = amdgpu_atombios_encoder_mode_fixup, + .prepare = dce_v11_0_encoder_prepare, + .mode_set = dce_v11_0_encoder_mode_set, + .commit = dce_v11_0_encoder_commit, + .detect = amdgpu_atombios_encoder_dac_detect, +}; + +static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) + amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); + kfree(amdgpu_encoder->enc_priv); + drm_encoder_cleanup(encoder); + kfree(amdgpu_encoder); +} + +static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { + .destroy = dce_v11_0_encoder_destroy, +}; + +static void dce_v11_0_encoder_add(struct amdgpu_device *adev, + uint32_t encoder_enum, + uint32_t supported_device, + u16 caps) +{ + struct drm_device *dev = adev->ddev; + struct drm_encoder *encoder; + struct amdgpu_encoder *amdgpu_encoder; + + /* see if we already added it */ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + amdgpu_encoder = to_amdgpu_encoder(encoder); + if (amdgpu_encoder->encoder_enum == encoder_enum) { + amdgpu_encoder->devices |= supported_device; + return; + } + + } + + /* add a new one */ + amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); + if (!amdgpu_encoder) + return; + + encoder = &amdgpu_encoder->base; + switch (adev->mode_info.num_crtc) { + case 1: + encoder->possible_crtcs = 0x1; + break; + case 2: + default: + encoder->possible_crtcs = 0x3; + break; + case 4: + encoder->possible_crtcs = 0xf; + break; + case 6: + encoder->possible_crtcs = 0x3f; + break; + } + + amdgpu_encoder->enc_priv = NULL; + + amdgpu_encoder->encoder_enum = encoder_enum; + amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; + amdgpu_encoder->devices = supported_device; + amdgpu_encoder->rmx_type = RMX_OFF; + amdgpu_encoder->underscan_type = UNDERSCAN_OFF; + amdgpu_encoder->is_ext_encoder = false; + amdgpu_encoder->caps = caps; + + switch (amdgpu_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, + DRM_MODE_ENCODER_DAC); + drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { + amdgpu_encoder->rmx_type = RMX_FULL; + drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, + DRM_MODE_ENCODER_LVDS); + amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); + } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { + drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, + DRM_MODE_ENCODER_DAC); + amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); + } else { + drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, + DRM_MODE_ENCODER_TMDS); + amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); + } + drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); + break; + case ENCODER_OBJECT_ID_SI170B: + case ENCODER_OBJECT_ID_CH7303: + case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: + case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: + case ENCODER_OBJECT_ID_TITFP513: + case ENCODER_OBJECT_ID_VT1623: + case ENCODER_OBJECT_ID_HDMI_SI1930: + case ENCODER_OBJECT_ID_TRAVIS: + case ENCODER_OBJECT_ID_NUTMEG: + /* these are handled by the primary encoders */ + amdgpu_encoder->is_ext_encoder = true; + if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) + drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, + DRM_MODE_ENCODER_LVDS); + else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) + drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, + DRM_MODE_ENCODER_DAC); + else + drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, + DRM_MODE_ENCODER_TMDS); + drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); + break; + } +} + +static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { + .set_vga_render_state = &dce_v11_0_set_vga_render_state, + .bandwidth_update = &dce_v11_0_bandwidth_update, + .vblank_get_counter = &dce_v11_0_vblank_get_counter, + .vblank_wait = &dce_v11_0_vblank_wait, + .is_display_hung = &dce_v11_0_is_display_hung, + .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, + .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, + .hpd_sense = &dce_v11_0_hpd_sense, + .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, + .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, + .page_flip = &dce_v11_0_page_flip, + .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, + .add_encoder = &dce_v11_0_encoder_add, + .add_connector = &amdgpu_connector_add, + .stop_mc_access = &dce_v11_0_stop_mc_access, + .resume_mc_access = &dce_v11_0_resume_mc_access, +}; + +static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) +{ + if (adev->mode_info.funcs == NULL) + adev->mode_info.funcs = &dce_v11_0_display_funcs; +} + +static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { + .set = dce_v11_0_set_crtc_irq_state, + .process = dce_v11_0_crtc_irq, +}; + +static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { + .set = dce_v11_0_set_pageflip_irq_state, + .process = dce_v11_0_pageflip_irq, +}; + +static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { + .set = dce_v11_0_set_hpd_irq_state, + .process = dce_v11_0_hpd_irq, +}; + +static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; + + adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; + + adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h new file mode 100644 index 000000000000..eeb9a56b514a --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DCE_V11_0_H__ +#define __DCE_V11_0_H__ + +extern const struct amdgpu_ip_funcs dce_v11_0_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c new file mode 100644 index 000000000000..a8397dd2bce4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -0,0 +1,4286 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_gfx.h" +#include "vi.h" +#include "vid.h" +#include "amdgpu_ucode.h" +#include "clearstate_vi.h" + +#include "gmc/gmc_8_2_d.h" +#include "gmc/gmc_8_2_sh_mask.h" + +#include "oss/oss_3_0_d.h" +#include "oss/oss_3_0_sh_mask.h" + +#include "bif/bif_5_0_d.h" +#include "bif/bif_5_0_sh_mask.h" + +#include "gca/gfx_8_0_d.h" +#include "gca/gfx_8_0_enum.h" +#include "gca/gfx_8_0_sh_mask.h" +#include "gca/gfx_8_0_enum.h" + +#include "uvd/uvd_5_0_d.h" +#include "uvd/uvd_5_0_sh_mask.h" + +#include "dce/dce_10_0_d.h" +#include "dce/dce_10_0_sh_mask.h" + +#define GFX8_NUM_GFX_RINGS 1 +#define GFX8_NUM_COMPUTE_RINGS 8 + +#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 +#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 +#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 + +#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) +#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) +#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) +#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT) +#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) +#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT) +#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT) +#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT) +#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) + +MODULE_FIRMWARE("radeon/carrizo_ce.bin"); +MODULE_FIRMWARE("radeon/carrizo_pfp.bin"); +MODULE_FIRMWARE("radeon/carrizo_me.bin"); +MODULE_FIRMWARE("radeon/carrizo_mec.bin"); +MODULE_FIRMWARE("radeon/carrizo_mec2.bin"); +MODULE_FIRMWARE("radeon/carrizo_rlc.bin"); + +MODULE_FIRMWARE("radeon/tonga_ce.bin"); +MODULE_FIRMWARE("radeon/tonga_pfp.bin"); +MODULE_FIRMWARE("radeon/tonga_me.bin"); +MODULE_FIRMWARE("radeon/tonga_mec.bin"); +MODULE_FIRMWARE("radeon/tonga_mec2.bin"); +MODULE_FIRMWARE("radeon/tonga_rlc.bin"); + +MODULE_FIRMWARE("radeon/topaz_ce.bin"); +MODULE_FIRMWARE("radeon/topaz_pfp.bin"); +MODULE_FIRMWARE("radeon/topaz_me.bin"); +MODULE_FIRMWARE("radeon/topaz_mec.bin"); +MODULE_FIRMWARE("radeon/topaz_mec2.bin"); +MODULE_FIRMWARE("radeon/topaz_rlc.bin"); + +static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = +{ + {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, + {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, + {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, + {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, + {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, + {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, + {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, + {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, + {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, + {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, + {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, + {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, + {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, + {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, + {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, + {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} +}; + +static const u32 golden_settings_tonga_a11[] = +{ + mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208, + mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, + mmDB_DEBUG2, 0xf00fffff, 0x00000400, + mmGB_GPU_ID, 0x0000000f, 0x00000000, + mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, + mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, + mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, + mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, + mmTCC_CTRL, 0x00100000, 0xf31fff7f, + mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb, + mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, + mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, +}; + +static const u32 tonga_golden_common_all[] = +{ + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, + mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, + mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, + mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, + mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF +}; + +static const u32 tonga_mgcg_cgcg_init[] = +{ + mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, + mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, + mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, + mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, + mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, + mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, + mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, + mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, + mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, + mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, + mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, + mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, + mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, +}; + +static const u32 golden_settings_iceland_a11[] = +{ + mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, + mmDB_DEBUG2, 0xf00fffff, 0x00000400, + mmDB_DEBUG3, 0xc0000000, 0xc0000000, + mmGB_GPU_ID, 0x0000000f, 0x00000000, + mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, + mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, + mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002, + mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, + mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, + mmTCC_CTRL, 0x00100000, 0xf31fff7f, + mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, + mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, + mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010, +}; + +static const u32 iceland_golden_common_all[] = +{ + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, + mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, + mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, + mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, + mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF +}; + +static const u32 iceland_mgcg_cgcg_init[] = +{ + mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100, + mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100, + mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100, + mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, + mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, + mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, + mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100, + mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, + mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, + mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, + mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, + mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, + mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, + mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, + mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, + mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, + mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, +}; + +static const u32 cz_golden_settings_a11[] = +{ + mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, + mmDB_DEBUG2, 0xf00fffff, 0x00000400, + mmGB_GPU_ID, 0x0000000f, 0x00000000, + mmPA_SC_ENHANCE, 0xffffffff, 0x00000001, + mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, + mmTA_CNTL_AUX, 0x000f000f, 0x00010000, + mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3, + mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302 +}; + +static const u32 cz_golden_common_all[] = +{ + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, + mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, + mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, + mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, + mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF +}; + +static const u32 cz_mgcg_cgcg_init[] = +{ + mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, + mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, + mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, + mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, + mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, + mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, + mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, + mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, + mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, + mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, + mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, + mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, + mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, + mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, + mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, + mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, + mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, + mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, + mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, +}; + +static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); +static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); +static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); + +static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_TOPAZ: + amdgpu_program_register_sequence(adev, + iceland_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + golden_settings_iceland_a11, + (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + amdgpu_program_register_sequence(adev, + iceland_golden_common_all, + (const u32)ARRAY_SIZE(iceland_golden_common_all)); + break; + case CHIP_TONGA: + amdgpu_program_register_sequence(adev, + tonga_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + golden_settings_tonga_a11, + (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + amdgpu_program_register_sequence(adev, + tonga_golden_common_all, + (const u32)ARRAY_SIZE(tonga_golden_common_all)); + break; + case CHIP_CARRIZO: + amdgpu_program_register_sequence(adev, + cz_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + cz_golden_settings_a11, + (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + amdgpu_program_register_sequence(adev, + cz_golden_common_all, + (const u32)ARRAY_SIZE(cz_golden_common_all)); + break; + default: + break; + } +} + +static void gfx_v8_0_scratch_init(struct amdgpu_device *adev) +{ + int i; + + adev->gfx.scratch.num_reg = 7; + adev->gfx.scratch.reg_base = mmSCRATCH_REG0; + for (i = 0; i < adev->gfx.scratch.num_reg; i++) { + adev->gfx.scratch.free[i] = true; + adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; + } +} + +static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = amdgpu_gfx_scratch_get(adev, &scratch); + if (r) { + DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = amdgpu_ring_lock(ring, 3); + if (r) { + DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", + ring->idx, r); + amdgpu_gfx_scratch_free(adev, scratch); + return r; + } + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); + amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_unlock_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", + ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", + ring->idx, scratch, tmp); + r = -EINVAL; + } + amdgpu_gfx_scratch_free(adev, scratch); + return r; +} + +static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_ib ib; + uint32_t scratch; + uint32_t tmp = 0; + unsigned i; + int r; + + r = amdgpu_gfx_scratch_get(adev, &scratch); + if (r) { + DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r); + return r; + } + WREG32(scratch, 0xCAFEDEAD); + r = amdgpu_ib_get(ring, NULL, 256, &ib); + if (r) { + DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); + amdgpu_gfx_scratch_free(adev, scratch); + return r; + } + ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); + ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); + ib.ptr[2] = 0xDEADBEEF; + ib.length_dw = 3; + r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); + if (r) { + amdgpu_gfx_scratch_free(adev, scratch); + amdgpu_ib_free(adev, &ib); + DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); + return r; + } + r = amdgpu_fence_wait(ib.fence, false); + if (r) { + DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + amdgpu_gfx_scratch_free(adev, scratch); + amdgpu_ib_free(adev, &ib); + return r; + } + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(scratch); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < adev->usec_timeout) { + DRM_INFO("ib test on ring %d succeeded in %u usecs\n", + ib.fence->ring->idx, i); + } else { + DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", + scratch, tmp); + r = -EINVAL; + } + amdgpu_gfx_scratch_free(adev, scratch); + amdgpu_ib_free(adev, &ib); + return r; +} + +static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) +{ + const char *chip_name; + char fw_name[30]; + int err; + struct amdgpu_firmware_info *info = NULL; + const struct common_firmware_header *header = NULL; + + DRM_DEBUG("\n"); + + switch (adev->asic_type) { + case CHIP_TOPAZ: + chip_name = "topaz"; + break; + case CHIP_TONGA: + chip_name = "tonga"; + break; + case CHIP_CARRIZO: + chip_name = "carrizo"; + break; + default: + BUG(); + } + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); + err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.pfp_fw); + if (err) + goto out; + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); + err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.me_fw); + if (err) + goto out; + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); + err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.ce_fw); + if (err) + goto out; + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); + err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.rlc_fw); + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name); + err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->gfx.mec_fw); + if (err) + goto out; + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name); + err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (!err) { + err = amdgpu_ucode_validate(adev->gfx.mec2_fw); + if (err) + goto out; + } else { + err = 0; + adev->gfx.mec2_fw = NULL; + } + + if (adev->firmware.smu_load) { + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; + info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; + info->fw = adev->gfx.pfp_fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; + info->ucode_id = AMDGPU_UCODE_ID_CP_ME; + info->fw = adev->gfx.me_fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; + info->ucode_id = AMDGPU_UCODE_ID_CP_CE; + info->fw = adev->gfx.ce_fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; + info->ucode_id = AMDGPU_UCODE_ID_RLC_G; + info->fw = adev->gfx.rlc_fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; + info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; + info->fw = adev->gfx.mec_fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + + if (adev->gfx.mec2_fw) { + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; + info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; + info->fw = adev->gfx.mec2_fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + } + + } + +out: + if (err) { + dev_err(adev->dev, + "gfx8: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(adev->gfx.pfp_fw); + adev->gfx.pfp_fw = NULL; + release_firmware(adev->gfx.me_fw); + adev->gfx.me_fw = NULL; + release_firmware(adev->gfx.ce_fw); + adev->gfx.ce_fw = NULL; + release_firmware(adev->gfx.rlc_fw); + adev->gfx.rlc_fw = NULL; + release_firmware(adev->gfx.mec_fw); + adev->gfx.mec_fw = NULL; + release_firmware(adev->gfx.mec2_fw); + adev->gfx.mec2_fw = NULL; + } + return err; +} + +static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) +{ + int r; + + if (adev->gfx.mec.hpd_eop_obj) { + r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); + amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); + amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); + + amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); + adev->gfx.mec.hpd_eop_obj = NULL; + } +} + +#define MEC_HPD_SIZE 2048 + +static int gfx_v8_0_mec_init(struct amdgpu_device *adev) +{ + int r; + u32 *hpd; + + /* + * we assign only 1 pipe because all other pipes will + * be handled by KFD + */ + adev->gfx.mec.num_mec = 1; + adev->gfx.mec.num_pipe = 1; + adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; + + if (adev->gfx.mec.hpd_eop_obj == NULL) { + r = amdgpu_bo_create(adev, + adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, NULL, + &adev->gfx.mec.hpd_eop_obj); + if (r) { + dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); + return r; + } + } + + r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); + if (unlikely(r != 0)) { + gfx_v8_0_mec_fini(adev); + return r; + } + r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, + &adev->gfx.mec.hpd_eop_gpu_addr); + if (r) { + dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); + gfx_v8_0_mec_fini(adev); + return r; + } + r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); + if (r) { + dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); + gfx_v8_0_mec_fini(adev); + return r; + } + + memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); + + amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); + amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); + + return 0; +} + +static int gfx_v8_0_sw_init(struct amdgpu_device *adev) +{ + int i, r; + struct amdgpu_ring *ring; + + /* EOP Event */ + r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); + if (r) + return r; + + /* Privileged reg */ + r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); + if (r) + return r; + + /* Privileged inst */ + r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); + if (r) + return r; + + adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; + + gfx_v8_0_scratch_init(adev); + + r = gfx_v8_0_init_microcode(adev); + if (r) { + DRM_ERROR("Failed to load gfx firmware!\n"); + return r; + } + + r = gfx_v8_0_mec_init(adev); + if (r) { + DRM_ERROR("Failed to init MEC BOs!\n"); + return r; + } + + r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs); + if (r) { + DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r); + return r; + } + + /* set up the gfx ring */ + for (i = 0; i < adev->gfx.num_gfx_rings; i++) { + ring = &adev->gfx.gfx_ring[i]; + ring->ring_obj = NULL; + sprintf(ring->name, "gfx"); + /* no gfx doorbells on iceland */ + if (adev->asic_type != CHIP_TOPAZ) { + ring->use_doorbell = true; + ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0; + } + + r = amdgpu_ring_init(adev, ring, 1024 * 1024, + PACKET3(PACKET3_NOP, 0x3FFF), 0xf, + &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, + AMDGPU_RING_TYPE_GFX); + if (r) + return r; + } + + /* set up the compute queues */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + unsigned irq_type; + + /* max 32 queues per MEC */ + if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { + DRM_ERROR("Too many (%d) compute rings!\n", i); + break; + } + ring = &adev->gfx.compute_ring[i]; + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; + ring->me = 1; /* first MEC */ + ring->pipe = i / 8; + ring->queue = i % 8; + sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); + irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; + /* type-2 packets are deprecated on MEC, use type-3 instead */ + r = amdgpu_ring_init(adev, ring, 1024 * 1024, + PACKET3(PACKET3_NOP, 0x3FFF), 0xf, + &adev->gfx.eop_irq, irq_type, + AMDGPU_RING_TYPE_COMPUTE); + if (r) + return r; + } + + /* reserve GDS, GWS and OA resource for gfx */ + r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size, + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GDS, 0, + NULL, &adev->gds.gds_gfx_bo); + if (r) + return r; + + r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size, + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GWS, 0, + NULL, &adev->gds.gws_gfx_bo); + if (r) + return r; + + r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size, + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_OA, 0, + NULL, &adev->gds.oa_gfx_bo); + if (r) + return r; + + return 0; +} + +static int gfx_v8_0_sw_fini(struct amdgpu_device *adev) +{ + int i; + + amdgpu_bo_unref(&adev->gds.oa_gfx_bo); + amdgpu_bo_unref(&adev->gds.gws_gfx_bo); + amdgpu_bo_unref(&adev->gds.gds_gfx_bo); + + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); + for (i = 0; i < adev->gfx.num_compute_rings; i++) + amdgpu_ring_fini(&adev->gfx.compute_ring[i]); + + amdgpu_wb_free(adev, adev->gfx.ce_sync_offs); + + gfx_v8_0_mec_fini(adev); + + return 0; +} + +static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) +{ + const u32 num_tile_mode_states = 32; + const u32 num_secondary_tile_mode_states = 16; + u32 reg_offset, gb_tile_moden, split_equal_to_row_size; + + switch (adev->gfx.config.mem_row_size_in_kb) { + case 1: + split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; + break; + case 2: + default: + split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; + break; + case 4: + split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; + break; + } + + switch (adev->asic_type) { + case CHIP_TOPAZ: + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 1: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 2: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 3: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 4: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 5: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 6: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 8: + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P2)); + break; + case 9: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 10: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 11: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 13: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 14: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 15: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 16: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 18: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 19: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 20: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 21: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 22: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 24: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 25: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 26: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 27: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 28: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 29: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 7: + case 12: + case 17: + case 23: + /* unused idx */ + continue; + default: + gb_tile_moden = 0; + break; + }; + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); + } + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 1: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 2: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 3: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 4: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 5: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 6: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 8: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 9: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 10: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 11: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 12: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 13: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 14: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 7: + /* unused idx */ + continue; + default: + gb_tile_moden = 0; + break; + }; + adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); + } + case CHIP_TONGA: + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 1: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 2: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 3: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 4: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 5: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 6: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 7: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 8: + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); + break; + case 9: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 10: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 11: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 12: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 13: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 14: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 15: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 16: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 17: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 18: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 19: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 20: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 21: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 22: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 23: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 24: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 25: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 26: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 27: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 28: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 29: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 30: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_16x16) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + default: + gb_tile_moden = 0; + break; + }; + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); + } + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 1: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 2: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 3: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 4: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 5: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 6: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 8: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 9: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 10: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 11: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 12: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 13: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK)); + break; + case 14: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | + NUM_BANKS(ADDR_SURF_4_BANK)); + break; + case 7: + /* unused idx */ + continue; + default: + gb_tile_moden = 0; + break; + }; + adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); + } + break; + case CHIP_CARRIZO: + default: + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 1: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 2: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 3: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 4: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 5: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 6: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 8: + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P2)); + break; + case 9: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 10: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 11: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 13: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 14: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 15: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 16: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 18: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 19: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 20: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 21: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 22: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 24: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 25: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 26: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 27: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 28: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 29: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 7: + case 12: + case 17: + case 23: + /* unused idx */ + continue; + default: + gb_tile_moden = 0; + break; + }; + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); + } + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 1: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 2: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 3: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 4: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 5: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 6: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 8: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 9: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 10: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 11: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 12: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 13: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 14: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 7: + /* unused idx */ + continue; + default: + gb_tile_moden = 0; + break; + }; + adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); + } + } +} + +static u32 gfx_v8_0_create_bitmask(u32 bit_width) +{ + u32 i, mask = 0; + + for (i = 0; i < bit_width; i++) { + mask <<= 1; + mask |= 1; + } + return mask; +} + +void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num) +{ + u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); + + if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) { + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + } else if (se_num == 0xffffffff) { + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + } else if (sh_num == 0xffffffff) { + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); + } else { + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); + } + WREG32(mmGRBM_GFX_INDEX, data); +} + +static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev, + u32 max_rb_num_per_se, + u32 sh_per_se) +{ + u32 data, mask; + + data = RREG32(mmCC_RB_BACKEND_DISABLE); + if (data & 1) + data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; + else + data = 0; + + data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); + + data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; + + mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se); + + return data & mask; +} + +static void gfx_v8_0_setup_rb(struct amdgpu_device *adev, + u32 se_num, u32 sh_per_se, + u32 max_rb_num_per_se) +{ + int i, j; + u32 data, mask; + u32 disabled_rbs = 0; + u32 enabled_rbs = 0; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < se_num; i++) { + for (j = 0; j < sh_per_se; j++) { + gfx_v8_0_select_se_sh(adev, i, j); + data = gfx_v8_0_get_rb_disabled(adev, + max_rb_num_per_se, sh_per_se); + disabled_rbs |= data << ((i * sh_per_se + j) * + RB_BITMAP_WIDTH_PER_SH); + } + } + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + + mask = 1; + for (i = 0; i < max_rb_num_per_se * se_num; i++) { + if (!(disabled_rbs & mask)) + enabled_rbs |= mask; + mask <<= 1; + } + + adev->gfx.config.backend_enable_mask = enabled_rbs; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < se_num; i++) { + gfx_v8_0_select_se_sh(adev, i, 0xffffffff); + data = 0; + for (j = 0; j < sh_per_se; j++) { + switch (enabled_rbs & 3) { + case 0: + if (j == 0) + data |= (RASTER_CONFIG_RB_MAP_3 << + PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT); + else + data |= (RASTER_CONFIG_RB_MAP_0 << + PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT); + break; + case 1: + data |= (RASTER_CONFIG_RB_MAP_0 << + (i * sh_per_se + j) * 2); + break; + case 2: + data |= (RASTER_CONFIG_RB_MAP_3 << + (i * sh_per_se + j) * 2); + break; + case 3: + default: + data |= (RASTER_CONFIG_RB_MAP_2 << + (i * sh_per_se + j) * 2); + break; + } + enabled_rbs >>= 2; + } + WREG32(mmPA_SC_RASTER_CONFIG, data); + } + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); +} + +static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) +{ + u32 gb_addr_config; + u32 mc_shared_chmap, mc_arb_ramcfg; + u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; + u32 tmp; + int i; + + switch (adev->asic_type) { + case CHIP_TOPAZ: + adev->gfx.config.max_shader_engines = 1; + adev->gfx.config.max_tile_pipes = 2; + adev->gfx.config.max_cu_per_sh = 6; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 2; + adev->gfx.config.max_texture_channel_caches = 2; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_TONGA: + adev->gfx.config.max_shader_engines = 4; + adev->gfx.config.max_tile_pipes = 8; + adev->gfx.config.max_cu_per_sh = 8; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 2; + adev->gfx.config.max_texture_channel_caches = 8; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_CARRIZO: + adev->gfx.config.max_shader_engines = 1; + adev->gfx.config.max_tile_pipes = 2; + adev->gfx.config.max_cu_per_sh = 8; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 2; + adev->gfx.config.max_texture_channel_caches = 2; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; + break; + default: + adev->gfx.config.max_shader_engines = 2; + adev->gfx.config.max_tile_pipes = 4; + adev->gfx.config.max_cu_per_sh = 2; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 2; + adev->gfx.config.max_texture_channel_caches = 4; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; + break; + } + + tmp = RREG32(mmGRBM_CNTL); + tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff); + WREG32(mmGRBM_CNTL, tmp); + + mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); + adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); + mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; + + adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; + adev->gfx.config.mem_max_burst_length_bytes = 256; + if (adev->flags & AMDGPU_IS_APU) { + /* Get memory bank mapping mode. */ + tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); + dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); + dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); + + tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); + dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); + dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); + + /* Validate settings in case only one DIMM installed. */ + if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) + dimm00_addr_map = 0; + if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) + dimm01_addr_map = 0; + if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) + dimm10_addr_map = 0; + if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) + dimm11_addr_map = 0; + + /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ + /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ + if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) + adev->gfx.config.mem_row_size_in_kb = 2; + else + adev->gfx.config.mem_row_size_in_kb = 1; + } else { + tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); + adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; + if (adev->gfx.config.mem_row_size_in_kb > 4) + adev->gfx.config.mem_row_size_in_kb = 4; + } + + adev->gfx.config.shader_engine_tile_size = 32; + adev->gfx.config.num_gpus = 1; + adev->gfx.config.multi_gpu_tile_size = 64; + + /* fix up row size */ + switch (adev->gfx.config.mem_row_size_in_kb) { + case 1: + default: + gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); + break; + case 2: + gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1); + break; + case 4: + gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2); + break; + } + adev->gfx.config.gb_addr_config = gb_addr_config; + + WREG32(mmGB_ADDR_CONFIG, gb_addr_config); + WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); + WREG32(mmDMIF_ADDR_CALC, gb_addr_config); + WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, + gb_addr_config & 0x70); + WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, + gb_addr_config & 0x70); + WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); + WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); + WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); + + gfx_v8_0_tiling_mode_table_init(adev); + + gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines, + adev->gfx.config.max_sh_per_se, + adev->gfx.config.max_backends_per_se); + + /* XXX SH_MEM regs */ + /* where to put LDS, scratch, GPUVM in FSA64 space */ + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < 16; i++) { + vi_srbm_select(adev, 0, 0, 0, i); + /* CP and shaders */ + if (i == 0) { + tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); + WREG32(mmSH_MEM_CONFIG, tmp); + } else { + tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC); + WREG32(mmSH_MEM_CONFIG, tmp); + } + + WREG32(mmSH_MEM_APE1_BASE, 1); + WREG32(mmSH_MEM_APE1_LIMIT, 0); + WREG32(mmSH_MEM_BASES, 0); + } + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + mutex_lock(&adev->grbm_idx_mutex); + /* + * making sure that the following register writes will be broadcasted + * to all the shaders + */ + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + + WREG32(mmPA_SC_FIFO_SIZE, + (adev->gfx.config.sc_prim_fifo_size_frontend << + PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_prim_fifo_size_backend << + PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_hiz_tile_fifo_size << + PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | + (adev->gfx.config.sc_earlyz_tile_fifo_size << + PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); + mutex_unlock(&adev->grbm_idx_mutex); + +} + +static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev) +{ + u32 i, j, k; + u32 mask; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + gfx_v8_0_select_se_sh(adev, i, j); + for (k = 0; k < adev->usec_timeout; k++) { + if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) + break; + udelay(1); + } + } + } + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + + mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | + RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | + RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | + RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; + for (k = 0; k < adev->usec_timeout; k++) { + if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) + break; + udelay(1); + } +} + +static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, + bool enable) +{ + u32 tmp = RREG32(mmCP_INT_CNTL_RING0); + + if (enable) { + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1); + } else { + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0); + } + WREG32(mmCP_INT_CNTL_RING0, tmp); +} + +void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmRLC_CNTL); + + tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); + WREG32(mmRLC_CNTL, tmp); + + gfx_v8_0_enable_gui_idle_interrupt(adev, false); + + gfx_v8_0_wait_for_rlc_serdes(adev); +} + +static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmGRBM_SOFT_RESET); + + tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); + WREG32(mmGRBM_SOFT_RESET, tmp); + udelay(50); + tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); + WREG32(mmGRBM_SOFT_RESET, tmp); + udelay(50); +} + +static void gfx_v8_0_rlc_start(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmRLC_CNTL); + + tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1); + WREG32(mmRLC_CNTL, tmp); + + /* carrizo do enable cp interrupt after cp inited */ + if (adev->asic_type != CHIP_CARRIZO) + gfx_v8_0_enable_gui_idle_interrupt(adev, true); + + udelay(50); +} + +static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev) +{ + const struct rlc_firmware_header_v2_0 *hdr; + const __le32 *fw_data; + unsigned i, fw_size; + + if (!adev->gfx.rlc_fw) + return -EINVAL; + + hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; + amdgpu_ucode_print_rlc_hdr(&hdr->header); + adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); + + fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + + WREG32(mmRLC_GPM_UCODE_ADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); + + return 0; +} + +static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) +{ + int r; + + gfx_v8_0_rlc_stop(adev); + + /* disable CG */ + WREG32(mmRLC_CGCG_CGLS_CTRL, 0); + + /* disable PG */ + WREG32(mmRLC_PG_CNTL, 0); + + gfx_v8_0_rlc_reset(adev); + + if (!adev->firmware.smu_load) { + /* legacy rlc firmware loading */ + r = gfx_v8_0_rlc_load_microcode(adev); + if (r) + return r; + } else { + r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, + AMDGPU_UCODE_ID_RLC_G); + if (r) + return -EINVAL; + } + + gfx_v8_0_rlc_start(adev); + + return 0; +} + +static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) +{ + int i; + u32 tmp = RREG32(mmCP_ME_CNTL); + + if (enable) { + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); + } else { + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + adev->gfx.gfx_ring[i].ready = false; + } + WREG32(mmCP_ME_CNTL, tmp); + udelay(50); +} + +static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev) +{ + const struct gfx_firmware_header_v1_0 *pfp_hdr; + const struct gfx_firmware_header_v1_0 *ce_hdr; + const struct gfx_firmware_header_v1_0 *me_hdr; + const __le32 *fw_data; + unsigned i, fw_size; + + if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) + return -EINVAL; + + pfp_hdr = (const struct gfx_firmware_header_v1_0 *) + adev->gfx.pfp_fw->data; + ce_hdr = (const struct gfx_firmware_header_v1_0 *) + adev->gfx.ce_fw->data; + me_hdr = (const struct gfx_firmware_header_v1_0 *) + adev->gfx.me_fw->data; + + amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); + amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); + amdgpu_ucode_print_gfx_hdr(&me_hdr->header); + adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); + adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); + adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); + + gfx_v8_0_cp_gfx_enable(adev, false); + + /* PFP */ + fw_data = (const __le32 *) + (adev->gfx.pfp_fw->data + + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; + WREG32(mmCP_PFP_UCODE_ADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); + + /* CE */ + fw_data = (const __le32 *) + (adev->gfx.ce_fw->data + + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; + WREG32(mmCP_CE_UCODE_ADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); + + /* ME */ + fw_data = (const __le32 *) + (adev->gfx.me_fw->data + + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; + WREG32(mmCP_ME_RAM_WADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); + WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); + + return 0; +} + +static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev) +{ + u32 count = 0; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + + /* begin clear state */ + count += 2; + /* context control state */ + count += 3; + + for (sect = vi_cs_data; sect->section != NULL; ++sect) { + for (ext = sect->section; ext->extent != NULL; ++ext) { + if (sect->id == SECT_CONTEXT) + count += 2 + ext->reg_count; + else + return 0; + } + } + /* pa_sc_raster_config/pa_sc_raster_config1 */ + count += 4; + /* end clear state */ + count += 2; + /* clear state */ + count += 2; + + return count; +} + +static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + int r, i; + + /* init the CP */ + WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); + WREG32(mmCP_ENDIAN_SWAP, 0); + WREG32(mmCP_DEVICE_ID, 1); + + gfx_v8_0_cp_gfx_enable(adev, true); + + r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4); + if (r) { + DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + return r; + } + + /* clear state buffer */ + amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); + + amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); + amdgpu_ring_write(ring, 0x80000000); + amdgpu_ring_write(ring, 0x80000000); + + for (sect = vi_cs_data; sect->section != NULL; ++sect) { + for (ext = sect->section; ext->extent != NULL; ++ext) { + if (sect->id == SECT_CONTEXT) { + amdgpu_ring_write(ring, + PACKET3(PACKET3_SET_CONTEXT_REG, + ext->reg_count)); + amdgpu_ring_write(ring, + ext->reg_index - PACKET3_SET_CONTEXT_REG_START); + for (i = 0; i < ext->reg_count; i++) + amdgpu_ring_write(ring, ext->extent[i]); + } + } + } + + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); + switch (adev->asic_type) { + case CHIP_TONGA: + amdgpu_ring_write(ring, 0x16000012); + amdgpu_ring_write(ring, 0x0000002A); + break; + case CHIP_TOPAZ: + case CHIP_CARRIZO: + amdgpu_ring_write(ring, 0x00000002); + amdgpu_ring_write(ring, 0x00000000); + break; + default: + BUG(); + } + + amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); + + amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); + amdgpu_ring_write(ring, 0); + + /* init the CE partitions */ + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); + amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); + amdgpu_ring_write(ring, 0x8000); + amdgpu_ring_write(ring, 0x8000); + + amdgpu_ring_unlock_commit(ring); + + return 0; +} + +static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + u32 tmp; + u32 rb_bufsz; + u64 rb_addr, rptr_addr; + int r; + + /* Set the write pointer delay */ + WREG32(mmCP_RB_WPTR_DELAY, 0); + + /* set the RB to use vmid 0 */ + WREG32(mmCP_RB_VMID, 0); + + /* Set ring buffer size */ + ring = &adev->gfx.gfx_ring[0]; + rb_bufsz = order_base_2(ring->ring_size / 8); + tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); + tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); + tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); + tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); +#ifdef __BIG_ENDIAN + tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); +#endif + WREG32(mmCP_RB0_CNTL, tmp); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); + ring->wptr = 0; + WREG32(mmCP_RB0_WPTR, ring->wptr); + + /* set the wb address wether it's enabled or not */ + rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); + WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); + WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); + + mdelay(1); + WREG32(mmCP_RB0_CNTL, tmp); + + rb_addr = ring->gpu_addr >> 8; + WREG32(mmCP_RB0_BASE, rb_addr); + WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); + + /* no gfx doorbells on iceland */ + if (adev->asic_type != CHIP_TOPAZ) { + tmp = RREG32(mmCP_RB_DOORBELL_CONTROL); + if (ring->use_doorbell) { + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, + DOORBELL_OFFSET, ring->doorbell_index); + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, + DOORBELL_EN, 1); + } else { + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, + DOORBELL_EN, 0); + } + WREG32(mmCP_RB_DOORBELL_CONTROL, tmp); + + if (adev->asic_type == CHIP_TONGA) { + tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, + DOORBELL_RANGE_LOWER, + AMDGPU_DOORBELL_GFX_RING0); + WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp); + + WREG32(mmCP_RB_DOORBELL_RANGE_UPPER, + CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); + } + + } + + /* start the ring */ + gfx_v8_0_cp_gfx_start(adev); + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + return r; + } + + return 0; +} + +static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) +{ + int i; + + if (enable) { + WREG32(mmCP_MEC_CNTL, 0); + } else { + WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); + for (i = 0; i < adev->gfx.num_compute_rings; i++) + adev->gfx.compute_ring[i].ready = false; + } + udelay(50); +} + +static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev) +{ + gfx_v8_0_cp_compute_enable(adev, true); + + return 0; +} + +static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev) +{ + const struct gfx_firmware_header_v1_0 *mec_hdr; + const __le32 *fw_data; + unsigned i, fw_size; + + if (!adev->gfx.mec_fw) + return -EINVAL; + + gfx_v8_0_cp_compute_enable(adev, false); + + mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; + amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); + adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); + + fw_data = (const __le32 *) + (adev->gfx.mec_fw->data + + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; + + /* MEC1 */ + WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i)); + WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); + + /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ + if (adev->gfx.mec2_fw) { + const struct gfx_firmware_header_v1_0 *mec2_hdr; + + mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; + amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); + adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); + + fw_data = (const __le32 *) + (adev->gfx.mec2_fw->data + + le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; + + WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); + for (i = 0; i < fw_size; i++) + WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i)); + WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version); + } + + return 0; +} + +struct vi_mqd { + uint32_t header; /* ordinal0 */ + uint32_t compute_dispatch_initiator; /* ordinal1 */ + uint32_t compute_dim_x; /* ordinal2 */ + uint32_t compute_dim_y; /* ordinal3 */ + uint32_t compute_dim_z; /* ordinal4 */ + uint32_t compute_start_x; /* ordinal5 */ + uint32_t compute_start_y; /* ordinal6 */ + uint32_t compute_start_z; /* ordinal7 */ + uint32_t compute_num_thread_x; /* ordinal8 */ + uint32_t compute_num_thread_y; /* ordinal9 */ + uint32_t compute_num_thread_z; /* ordinal10 */ + uint32_t compute_pipelinestat_enable; /* ordinal11 */ + uint32_t compute_perfcount_enable; /* ordinal12 */ + uint32_t compute_pgm_lo; /* ordinal13 */ + uint32_t compute_pgm_hi; /* ordinal14 */ + uint32_t compute_tba_lo; /* ordinal15 */ + uint32_t compute_tba_hi; /* ordinal16 */ + uint32_t compute_tma_lo; /* ordinal17 */ + uint32_t compute_tma_hi; /* ordinal18 */ + uint32_t compute_pgm_rsrc1; /* ordinal19 */ + uint32_t compute_pgm_rsrc2; /* ordinal20 */ + uint32_t compute_vmid; /* ordinal21 */ + uint32_t compute_resource_limits; /* ordinal22 */ + uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */ + uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */ + uint32_t compute_tmpring_size; /* ordinal25 */ + uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */ + uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */ + uint32_t compute_restart_x; /* ordinal28 */ + uint32_t compute_restart_y; /* ordinal29 */ + uint32_t compute_restart_z; /* ordinal30 */ + uint32_t compute_thread_trace_enable; /* ordinal31 */ + uint32_t compute_misc_reserved; /* ordinal32 */ + uint32_t compute_dispatch_id; /* ordinal33 */ + uint32_t compute_threadgroup_id; /* ordinal34 */ + uint32_t compute_relaunch; /* ordinal35 */ + uint32_t compute_wave_restore_addr_lo; /* ordinal36 */ + uint32_t compute_wave_restore_addr_hi; /* ordinal37 */ + uint32_t compute_wave_restore_control; /* ordinal38 */ + uint32_t reserved9; /* ordinal39 */ + uint32_t reserved10; /* ordinal40 */ + uint32_t reserved11; /* ordinal41 */ + uint32_t reserved12; /* ordinal42 */ + uint32_t reserved13; /* ordinal43 */ + uint32_t reserved14; /* ordinal44 */ + uint32_t reserved15; /* ordinal45 */ + uint32_t reserved16; /* ordinal46 */ + uint32_t reserved17; /* ordinal47 */ + uint32_t reserved18; /* ordinal48 */ + uint32_t reserved19; /* ordinal49 */ + uint32_t reserved20; /* ordinal50 */ + uint32_t reserved21; /* ordinal51 */ + uint32_t reserved22; /* ordinal52 */ + uint32_t reserved23; /* ordinal53 */ + uint32_t reserved24; /* ordinal54 */ + uint32_t reserved25; /* ordinal55 */ + uint32_t reserved26; /* ordinal56 */ + uint32_t reserved27; /* ordinal57 */ + uint32_t reserved28; /* ordinal58 */ + uint32_t reserved29; /* ordinal59 */ + uint32_t reserved30; /* ordinal60 */ + uint32_t reserved31; /* ordinal61 */ + uint32_t reserved32; /* ordinal62 */ + uint32_t reserved33; /* ordinal63 */ + uint32_t reserved34; /* ordinal64 */ + uint32_t compute_user_data_0; /* ordinal65 */ + uint32_t compute_user_data_1; /* ordinal66 */ + uint32_t compute_user_data_2; /* ordinal67 */ + uint32_t compute_user_data_3; /* ordinal68 */ + uint32_t compute_user_data_4; /* ordinal69 */ + uint32_t compute_user_data_5; /* ordinal70 */ + uint32_t compute_user_data_6; /* ordinal71 */ + uint32_t compute_user_data_7; /* ordinal72 */ + uint32_t compute_user_data_8; /* ordinal73 */ + uint32_t compute_user_data_9; /* ordinal74 */ + uint32_t compute_user_data_10; /* ordinal75 */ + uint32_t compute_user_data_11; /* ordinal76 */ + uint32_t compute_user_data_12; /* ordinal77 */ + uint32_t compute_user_data_13; /* ordinal78 */ + uint32_t compute_user_data_14; /* ordinal79 */ + uint32_t compute_user_data_15; /* ordinal80 */ + uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */ + uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */ + uint32_t reserved35; /* ordinal83 */ + uint32_t reserved36; /* ordinal84 */ + uint32_t reserved37; /* ordinal85 */ + uint32_t cp_mqd_query_time_lo; /* ordinal86 */ + uint32_t cp_mqd_query_time_hi; /* ordinal87 */ + uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */ + uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */ + uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */ + uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */ + uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */ + uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */ + uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */ + uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */ + uint32_t reserved38; /* ordinal96 */ + uint32_t reserved39; /* ordinal97 */ + uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */ + uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */ + uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */ + uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */ + uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */ + uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */ + uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */ + uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */ + uint32_t reserved40; /* ordinal106 */ + uint32_t reserved41; /* ordinal107 */ + uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */ + uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */ + uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */ + uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */ + uint32_t reserved42; /* ordinal112 */ + uint32_t reserved43; /* ordinal113 */ + uint32_t cp_pq_exe_status_lo; /* ordinal114 */ + uint32_t cp_pq_exe_status_hi; /* ordinal115 */ + uint32_t cp_packet_id_lo; /* ordinal116 */ + uint32_t cp_packet_id_hi; /* ordinal117 */ + uint32_t cp_packet_exe_status_lo; /* ordinal118 */ + uint32_t cp_packet_exe_status_hi; /* ordinal119 */ + uint32_t gds_save_base_addr_lo; /* ordinal120 */ + uint32_t gds_save_base_addr_hi; /* ordinal121 */ + uint32_t gds_save_mask_lo; /* ordinal122 */ + uint32_t gds_save_mask_hi; /* ordinal123 */ + uint32_t ctx_save_base_addr_lo; /* ordinal124 */ + uint32_t ctx_save_base_addr_hi; /* ordinal125 */ + uint32_t reserved44; /* ordinal126 */ + uint32_t reserved45; /* ordinal127 */ + uint32_t cp_mqd_base_addr_lo; /* ordinal128 */ + uint32_t cp_mqd_base_addr_hi; /* ordinal129 */ + uint32_t cp_hqd_active; /* ordinal130 */ + uint32_t cp_hqd_vmid; /* ordinal131 */ + uint32_t cp_hqd_persistent_state; /* ordinal132 */ + uint32_t cp_hqd_pipe_priority; /* ordinal133 */ + uint32_t cp_hqd_queue_priority; /* ordinal134 */ + uint32_t cp_hqd_quantum; /* ordinal135 */ + uint32_t cp_hqd_pq_base_lo; /* ordinal136 */ + uint32_t cp_hqd_pq_base_hi; /* ordinal137 */ + uint32_t cp_hqd_pq_rptr; /* ordinal138 */ + uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */ + uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */ + uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */ + uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */ + uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */ + uint32_t cp_hqd_pq_wptr; /* ordinal144 */ + uint32_t cp_hqd_pq_control; /* ordinal145 */ + uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */ + uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */ + uint32_t cp_hqd_ib_rptr; /* ordinal148 */ + uint32_t cp_hqd_ib_control; /* ordinal149 */ + uint32_t cp_hqd_iq_timer; /* ordinal150 */ + uint32_t cp_hqd_iq_rptr; /* ordinal151 */ + uint32_t cp_hqd_dequeue_request; /* ordinal152 */ + uint32_t cp_hqd_dma_offload; /* ordinal153 */ + uint32_t cp_hqd_sema_cmd; /* ordinal154 */ + uint32_t cp_hqd_msg_type; /* ordinal155 */ + uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */ + uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */ + uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */ + uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */ + uint32_t cp_hqd_hq_status0; /* ordinal160 */ + uint32_t cp_hqd_hq_control0; /* ordinal161 */ + uint32_t cp_mqd_control; /* ordinal162 */ + uint32_t cp_hqd_hq_status1; /* ordinal163 */ + uint32_t cp_hqd_hq_control1; /* ordinal164 */ + uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */ + uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */ + uint32_t cp_hqd_eop_control; /* ordinal167 */ + uint32_t cp_hqd_eop_rptr; /* ordinal168 */ + uint32_t cp_hqd_eop_wptr; /* ordinal169 */ + uint32_t cp_hqd_eop_done_events; /* ordinal170 */ + uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */ + uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */ + uint32_t cp_hqd_ctx_save_control; /* ordinal173 */ + uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */ + uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */ + uint32_t cp_hqd_wg_state_offset; /* ordinal176 */ + uint32_t cp_hqd_ctx_save_size; /* ordinal177 */ + uint32_t cp_hqd_gds_resource_state; /* ordinal178 */ + uint32_t cp_hqd_error; /* ordinal179 */ + uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */ + uint32_t cp_hqd_eop_dones; /* ordinal181 */ + uint32_t reserved46; /* ordinal182 */ + uint32_t reserved47; /* ordinal183 */ + uint32_t reserved48; /* ordinal184 */ + uint32_t reserved49; /* ordinal185 */ + uint32_t reserved50; /* ordinal186 */ + uint32_t reserved51; /* ordinal187 */ + uint32_t reserved52; /* ordinal188 */ + uint32_t reserved53; /* ordinal189 */ + uint32_t reserved54; /* ordinal190 */ + uint32_t reserved55; /* ordinal191 */ + uint32_t iqtimer_pkt_header; /* ordinal192 */ + uint32_t iqtimer_pkt_dw0; /* ordinal193 */ + uint32_t iqtimer_pkt_dw1; /* ordinal194 */ + uint32_t iqtimer_pkt_dw2; /* ordinal195 */ + uint32_t iqtimer_pkt_dw3; /* ordinal196 */ + uint32_t iqtimer_pkt_dw4; /* ordinal197 */ + uint32_t iqtimer_pkt_dw5; /* ordinal198 */ + uint32_t iqtimer_pkt_dw6; /* ordinal199 */ + uint32_t iqtimer_pkt_dw7; /* ordinal200 */ + uint32_t iqtimer_pkt_dw8; /* ordinal201 */ + uint32_t iqtimer_pkt_dw9; /* ordinal202 */ + uint32_t iqtimer_pkt_dw10; /* ordinal203 */ + uint32_t iqtimer_pkt_dw11; /* ordinal204 */ + uint32_t iqtimer_pkt_dw12; /* ordinal205 */ + uint32_t iqtimer_pkt_dw13; /* ordinal206 */ + uint32_t iqtimer_pkt_dw14; /* ordinal207 */ + uint32_t iqtimer_pkt_dw15; /* ordinal208 */ + uint32_t iqtimer_pkt_dw16; /* ordinal209 */ + uint32_t iqtimer_pkt_dw17; /* ordinal210 */ + uint32_t iqtimer_pkt_dw18; /* ordinal211 */ + uint32_t iqtimer_pkt_dw19; /* ordinal212 */ + uint32_t iqtimer_pkt_dw20; /* ordinal213 */ + uint32_t iqtimer_pkt_dw21; /* ordinal214 */ + uint32_t iqtimer_pkt_dw22; /* ordinal215 */ + uint32_t iqtimer_pkt_dw23; /* ordinal216 */ + uint32_t iqtimer_pkt_dw24; /* ordinal217 */ + uint32_t iqtimer_pkt_dw25; /* ordinal218 */ + uint32_t iqtimer_pkt_dw26; /* ordinal219 */ + uint32_t iqtimer_pkt_dw27; /* ordinal220 */ + uint32_t iqtimer_pkt_dw28; /* ordinal221 */ + uint32_t iqtimer_pkt_dw29; /* ordinal222 */ + uint32_t iqtimer_pkt_dw30; /* ordinal223 */ + uint32_t iqtimer_pkt_dw31; /* ordinal224 */ + uint32_t reserved56; /* ordinal225 */ + uint32_t reserved57; /* ordinal226 */ + uint32_t reserved58; /* ordinal227 */ + uint32_t set_resources_header; /* ordinal228 */ + uint32_t set_resources_dw1; /* ordinal229 */ + uint32_t set_resources_dw2; /* ordinal230 */ + uint32_t set_resources_dw3; /* ordinal231 */ + uint32_t set_resources_dw4; /* ordinal232 */ + uint32_t set_resources_dw5; /* ordinal233 */ + uint32_t set_resources_dw6; /* ordinal234 */ + uint32_t set_resources_dw7; /* ordinal235 */ + uint32_t reserved59; /* ordinal236 */ + uint32_t reserved60; /* ordinal237 */ + uint32_t reserved61; /* ordinal238 */ + uint32_t reserved62; /* ordinal239 */ + uint32_t reserved63; /* ordinal240 */ + uint32_t reserved64; /* ordinal241 */ + uint32_t reserved65; /* ordinal242 */ + uint32_t reserved66; /* ordinal243 */ + uint32_t reserved67; /* ordinal244 */ + uint32_t reserved68; /* ordinal245 */ + uint32_t reserved69; /* ordinal246 */ + uint32_t reserved70; /* ordinal247 */ + uint32_t reserved71; /* ordinal248 */ + uint32_t reserved72; /* ordinal249 */ + uint32_t reserved73; /* ordinal250 */ + uint32_t reserved74; /* ordinal251 */ + uint32_t reserved75; /* ordinal252 */ + uint32_t reserved76; /* ordinal253 */ + uint32_t reserved77; /* ordinal254 */ + uint32_t reserved78; /* ordinal255 */ + + uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */ +}; + +static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; + + if (ring->mqd_obj) { + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); + + amdgpu_bo_unpin(ring->mqd_obj); + amdgpu_bo_unreserve(ring->mqd_obj); + + amdgpu_bo_unref(&ring->mqd_obj); + ring->mqd_obj = NULL; + } + } +} + +static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) +{ + int r, i, j; + u32 tmp; + bool use_doorbell = true; + u64 hqd_gpu_addr; + u64 mqd_gpu_addr; + u64 eop_gpu_addr; + u64 wb_gpu_addr; + u32 *buf; + struct vi_mqd *mqd; + + /* init the pipes */ + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { + int me = (i < 4) ? 1 : 2; + int pipe = (i < 4) ? i : (i - 4); + + eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); + eop_gpu_addr >>= 8; + + vi_srbm_select(adev, me, pipe, 0, 0); + + /* write the EOP addr */ + WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr); + WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr)); + + /* set the VMID assigned */ + WREG32(mmCP_HQD_VMID, 0); + + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + tmp = RREG32(mmCP_HQD_EOP_CONTROL); + tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, + (order_base_2(MEC_HPD_SIZE / 4) - 1)); + WREG32(mmCP_HQD_EOP_CONTROL, tmp); + } + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + /* init the queues. Just two for now. */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; + + if (ring->mqd_obj == NULL) { + r = amdgpu_bo_create(adev, + sizeof(struct vi_mqd), + PAGE_SIZE, true, + AMDGPU_GEM_DOMAIN_GTT, 0, NULL, + &ring->mqd_obj); + if (r) { + dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); + return r; + } + } + + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) { + gfx_v8_0_cp_compute_fini(adev); + return r; + } + r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, + &mqd_gpu_addr); + if (r) { + dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); + gfx_v8_0_cp_compute_fini(adev); + return r; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); + if (r) { + dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); + gfx_v8_0_cp_compute_fini(adev); + return r; + } + + /* init the mqd struct */ + memset(buf, 0, sizeof(struct vi_mqd)); + + mqd = (struct vi_mqd *)buf; + mqd->header = 0xC0310800; + mqd->compute_pipelinestat_enable = 0x00000001; + mqd->compute_static_thread_mgmt_se0 = 0xffffffff; + mqd->compute_static_thread_mgmt_se1 = 0xffffffff; + mqd->compute_static_thread_mgmt_se2 = 0xffffffff; + mqd->compute_static_thread_mgmt_se3 = 0xffffffff; + mqd->compute_misc_reserved = 0x00000003; + + mutex_lock(&adev->srbm_mutex); + vi_srbm_select(adev, ring->me, + ring->pipe, + ring->queue, 0); + + /* disable wptr polling */ + tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); + tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); + WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); + + mqd->cp_hqd_eop_base_addr_lo = + RREG32(mmCP_HQD_EOP_BASE_ADDR); + mqd->cp_hqd_eop_base_addr_hi = + RREG32(mmCP_HQD_EOP_BASE_ADDR_HI); + + /* enable doorbell? */ + tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); + if (use_doorbell) { + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); + } else { + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0); + } + WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp); + mqd->cp_hqd_pq_doorbell_control = tmp; + + /* disable the queue if it's active */ + mqd->cp_hqd_dequeue_request = 0; + mqd->cp_hqd_pq_rptr = 0; + mqd->cp_hqd_pq_wptr= 0; + if (RREG32(mmCP_HQD_ACTIVE) & 1) { + WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); + for (j = 0; j < adev->usec_timeout; j++) { + if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request); + WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr); + WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); + } + + /* set the pointer to the MQD */ + mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; + mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); + WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); + WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); + + /* set MQD vmid to 0 */ + tmp = RREG32(mmCP_MQD_CONTROL); + tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); + WREG32(mmCP_MQD_CONTROL, tmp); + mqd->cp_mqd_control = tmp; + + /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ + hqd_gpu_addr = ring->gpu_addr >> 8; + mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; + mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); + WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); + WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); + + /* set up the HQD, this is similar to CP_RB0_CNTL */ + tmp = RREG32(mmCP_HQD_PQ_CONTROL); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, + (order_base_2(ring->ring_size / 4) - 1)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, + ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); +#ifdef __BIG_ENDIAN + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); +#endif + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); + WREG32(mmCP_HQD_PQ_CONTROL, tmp); + mqd->cp_hqd_pq_control = tmp; + + /* set the wb address wether it's enabled or not */ + wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); + mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_rptr_report_addr_hi = + upper_32_bits(wb_gpu_addr) & 0xffff; + WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, + mqd->cp_hqd_pq_rptr_report_addr_lo); + WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, + mqd->cp_hqd_pq_rptr_report_addr_hi); + + /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ + wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; + WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr); + WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, + mqd->cp_hqd_pq_wptr_poll_addr_hi); + + /* enable the doorbell if requested */ + if (use_doorbell) { + if (adev->asic_type == CHIP_CARRIZO) { + WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, + AMDGPU_DOORBELL_KIQ << 2); + WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, + AMDGPU_DOORBELL_MEC_RING7 << 2); + } + tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_OFFSET, ring->doorbell_index); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0); + mqd->cp_hqd_pq_doorbell_control = tmp; + + } else { + mqd->cp_hqd_pq_doorbell_control = 0; + } + WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, + mqd->cp_hqd_pq_doorbell_control); + + /* set the vmid for the queue */ + mqd->cp_hqd_vmid = 0; + WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid); + + tmp = RREG32(mmCP_HQD_PERSISTENT_STATE); + tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); + WREG32(mmCP_HQD_PERSISTENT_STATE, tmp); + mqd->cp_hqd_persistent_state = tmp; + + /* activate the queue */ + mqd->cp_hqd_active = 1; + WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active); + + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + amdgpu_bo_kunmap(ring->mqd_obj); + amdgpu_bo_unreserve(ring->mqd_obj); + } + + if (use_doorbell) { + tmp = RREG32(mmCP_PQ_STATUS); + tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1); + WREG32(mmCP_PQ_STATUS, tmp); + } + + r = gfx_v8_0_cp_compute_start(adev); + if (r) + return r; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; + + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) + ring->ready = false; + } + + return 0; +} + +static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) +{ + int r; + + if (adev->asic_type != CHIP_CARRIZO) + gfx_v8_0_enable_gui_idle_interrupt(adev, false); + + if (!adev->firmware.smu_load) { + /* legacy firmware loading */ + r = gfx_v8_0_cp_gfx_load_microcode(adev); + if (r) + return r; + + r = gfx_v8_0_cp_compute_load_microcode(adev); + if (r) + return r; + } else { + r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, + AMDGPU_UCODE_ID_CP_CE); + if (r) + return -EINVAL; + + r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, + AMDGPU_UCODE_ID_CP_PFP); + if (r) + return -EINVAL; + + r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, + AMDGPU_UCODE_ID_CP_ME); + if (r) + return -EINVAL; + + r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, + AMDGPU_UCODE_ID_CP_MEC1); + if (r) + return -EINVAL; + } + + r = gfx_v8_0_cp_gfx_resume(adev); + if (r) + return r; + + r = gfx_v8_0_cp_compute_resume(adev); + if (r) + return r; + + gfx_v8_0_enable_gui_idle_interrupt(adev, true); + + return 0; +} + +static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable) +{ + gfx_v8_0_cp_gfx_enable(adev, enable); + gfx_v8_0_cp_compute_enable(adev, enable); +} + +static int gfx_v8_0_hw_init(struct amdgpu_device *adev) +{ + int r; + + gfx_v8_0_init_golden_registers(adev); + + gfx_v8_0_gpu_init(adev); + + r = gfx_v8_0_rlc_resume(adev); + if (r) + return r; + + r = gfx_v8_0_cp_resume(adev); + if (r) + return r; + + return r; +} + +static int gfx_v8_0_hw_fini(struct amdgpu_device *adev) +{ + gfx_v8_0_cp_enable(adev, false); + gfx_v8_0_rlc_stop(adev); + gfx_v8_0_cp_compute_fini(adev); + + return 0; +} + +static int gfx_v8_0_suspend(struct amdgpu_device *adev) +{ + return gfx_v8_0_hw_fini(adev); +} + +static int gfx_v8_0_resume(struct amdgpu_device *adev) +{ + return gfx_v8_0_hw_init(adev); +} + +static bool gfx_v8_0_is_idle(struct amdgpu_device *adev) +{ + if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) + return false; + else + return true; +} + +static int gfx_v8_0_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; + + if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static void gfx_v8_0_print_status(struct amdgpu_device *adev) +{ + int i; + + dev_info(adev->dev, "GFX 8.x registers\n"); + dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", + RREG32(mmGRBM_STATUS)); + dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", + RREG32(mmGRBM_STATUS2)); + dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", + RREG32(mmGRBM_STATUS_SE0)); + dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", + RREG32(mmGRBM_STATUS_SE1)); + dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", + RREG32(mmGRBM_STATUS_SE2)); + dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", + RREG32(mmGRBM_STATUS_SE3)); + dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); + dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT1)); + dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT2)); + dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT3)); + dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", + RREG32(mmCP_CPF_BUSY_STAT)); + dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_CPF_STALLED_STAT1)); + dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); + dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); + dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_CPC_STALLED_STAT1)); + dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); + + for (i = 0; i < 32; i++) { + dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", + i, RREG32(mmGB_TILE_MODE0 + (i * 4))); + } + for (i = 0; i < 16; i++) { + dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", + i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); + } + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + dev_info(adev->dev, " se: %d\n", i); + gfx_v8_0_select_se_sh(adev, i, 0xffffffff); + dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", + RREG32(mmPA_SC_RASTER_CONFIG)); + dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", + RREG32(mmPA_SC_RASTER_CONFIG_1)); + } + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + + dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", + RREG32(mmGB_ADDR_CONFIG)); + dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", + RREG32(mmHDP_ADDR_CONFIG)); + dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", + RREG32(mmDMIF_ADDR_CALC)); + dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n", + RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET)); + dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n", + RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET)); + dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); + + dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", + RREG32(mmCP_MEQ_THRESHOLDS)); + dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", + RREG32(mmSX_DEBUG_1)); + dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", + RREG32(mmTA_CNTL_AUX)); + dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", + RREG32(mmSPI_CONFIG_CNTL)); + dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", + RREG32(mmSQ_CONFIG)); + dev_info(adev->dev, " DB_DEBUG=0x%08X\n", + RREG32(mmDB_DEBUG)); + dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", + RREG32(mmDB_DEBUG2)); + dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", + RREG32(mmDB_DEBUG3)); + dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", + RREG32(mmCB_HW_CONTROL)); + dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", + RREG32(mmSPI_CONFIG_CNTL_1)); + dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", + RREG32(mmPA_SC_FIFO_SIZE)); + dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", + RREG32(mmVGT_NUM_INSTANCES)); + dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", + RREG32(mmCP_PERFMON_CNTL)); + dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", + RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); + dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", + RREG32(mmVGT_CACHE_INVALIDATION)); + dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", + RREG32(mmVGT_GS_VERTEX_REUSE)); + dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", + RREG32(mmPA_SC_LINE_STIPPLE_STATE)); + dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", + RREG32(mmPA_CL_ENHANCE)); + dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", + RREG32(mmPA_SC_ENHANCE)); + + dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", + RREG32(mmCP_ME_CNTL)); + dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", + RREG32(mmCP_MAX_CONTEXT)); + dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", + RREG32(mmCP_ENDIAN_SWAP)); + dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", + RREG32(mmCP_DEVICE_ID)); + + dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", + RREG32(mmCP_SEM_WAIT_TIMER)); + + dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", + RREG32(mmCP_RB_WPTR_DELAY)); + dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", + RREG32(mmCP_RB_VMID)); + dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", + RREG32(mmCP_RB0_CNTL)); + dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", + RREG32(mmCP_RB0_WPTR)); + dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", + RREG32(mmCP_RB0_RPTR_ADDR)); + dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", + RREG32(mmCP_RB0_RPTR_ADDR_HI)); + dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", + RREG32(mmCP_RB0_CNTL)); + dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", + RREG32(mmCP_RB0_BASE)); + dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", + RREG32(mmCP_RB0_BASE_HI)); + dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", + RREG32(mmCP_MEC_CNTL)); + dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", + RREG32(mmCP_CPF_DEBUG)); + + dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", + RREG32(mmSCRATCH_ADDR)); + dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", + RREG32(mmSCRATCH_UMSK)); + + dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", + RREG32(mmCP_INT_CNTL_RING0)); + dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", + RREG32(mmRLC_LB_CNTL)); + dev_info(adev->dev, " RLC_CNTL=0x%08X\n", + RREG32(mmRLC_CNTL)); + dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", + RREG32(mmRLC_CGCG_CGLS_CTRL)); + dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", + RREG32(mmRLC_LB_CNTR_INIT)); + dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", + RREG32(mmRLC_LB_CNTR_MAX)); + dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", + RREG32(mmRLC_LB_INIT_CU_MASK)); + dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", + RREG32(mmRLC_LB_PARAMS)); + dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", + RREG32(mmRLC_LB_CNTL)); + dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", + RREG32(mmRLC_MC_CNTL)); + dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", + RREG32(mmRLC_UCODE_CNTL)); + + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < 16; i++) { + vi_srbm_select(adev, 0, 0, 0, i); + dev_info(adev->dev, " VM %d:\n", i); + dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", + RREG32(mmSH_MEM_CONFIG)); + dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", + RREG32(mmSH_MEM_APE1_BASE)); + dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", + RREG32(mmSH_MEM_APE1_LIMIT)); + dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", + RREG32(mmSH_MEM_BASES)); + } + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); +} + +static int gfx_v8_0_soft_reset(struct amdgpu_device *adev) +{ + u32 grbm_soft_reset = 0, srbm_soft_reset = 0; + u32 tmp; + + /* GRBM_STATUS */ + tmp = RREG32(mmGRBM_STATUS); + if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | + GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | + GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | + GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | + GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | + GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { + grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, + GRBM_SOFT_RESET, SOFT_RESET_CP, 1); + grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, + GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); + } + + if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { + grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, + GRBM_SOFT_RESET, SOFT_RESET_CP, 1); + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, + SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); + } + + /* GRBM_STATUS2 */ + tmp = RREG32(mmGRBM_STATUS2); + if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) + grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, + GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); + + /* SRBM_STATUS */ + tmp = RREG32(mmSRBM_STATUS); + if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING)) + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, + SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); + + if (grbm_soft_reset || srbm_soft_reset) { + gfx_v8_0_print_status(adev); + /* stop the rlc */ + gfx_v8_0_rlc_stop(adev); + + /* Disable GFX parsing/prefetching */ + gfx_v8_0_cp_gfx_enable(adev, false); + + /* Disable MEC parsing/prefetching */ + /* XXX todo */ + + if (grbm_soft_reset) { + tmp = RREG32(mmGRBM_SOFT_RESET); + tmp |= grbm_soft_reset; + dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmGRBM_SOFT_RESET, tmp); + tmp = RREG32(mmGRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~grbm_soft_reset; + WREG32(mmGRBM_SOFT_RESET, tmp); + tmp = RREG32(mmGRBM_SOFT_RESET); + } + + if (srbm_soft_reset) { + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + } + /* Wait a little for things to settle down */ + udelay(50); + gfx_v8_0_print_status(adev); + } + return 0; +} + +/** + * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot + * + * @adev: amdgpu_device pointer + * + * Fetches a GPU clock counter snapshot. + * Returns the 64 bit clock counter snapshot. + */ +uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev) +{ + uint64_t clock; + + mutex_lock(&adev->gfx.gpu_clock_mutex); + WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); + clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | + ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); + mutex_unlock(&adev->gfx.gpu_clock_mutex); + return clock; +} + +static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring, + uint32_t vmid, + uint32_t gds_base, uint32_t gds_size, + uint32_t gws_base, uint32_t gws_size, + uint32_t oa_base, uint32_t oa_size) +{ + gds_base = gds_base >> AMDGPU_GDS_SHIFT; + gds_size = gds_size >> AMDGPU_GDS_SHIFT; + + gws_base = gws_base >> AMDGPU_GWS_SHIFT; + gws_size = gws_size >> AMDGPU_GWS_SHIFT; + + oa_base = oa_base >> AMDGPU_OA_SHIFT; + oa_size = oa_size >> AMDGPU_OA_SHIFT; + + /* GDS Base */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, gds_base); + + /* GDS Size */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, gds_size); + + /* GWS */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); + + /* OA */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); +} + +static int gfx_v8_0_early_init(struct amdgpu_device *adev) +{ + + adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; + adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS; + gfx_v8_0_set_ring_funcs(adev); + gfx_v8_0_set_irq_funcs(adev); + gfx_v8_0_set_gds_init(adev); + + return 0; +} + +static int gfx_v8_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +static int gfx_v8_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) +{ + u32 rptr; + + rptr = ring->adev->wb.wb[ring->rptr_offs]; + + return rptr; +} + +static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u32 wptr; + + if (ring->use_doorbell) + /* XXX check if swapping is necessary on BE */ + wptr = ring->adev->wb.wb[ring->wptr_offs]; + else + wptr = RREG32(mmCP_RB0_WPTR); + + return wptr; +} + +static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) { + /* XXX check if swapping is necessary on BE */ + adev->wb.wb[ring->wptr_offs] = ring->wptr; + WDOORBELL32(ring->doorbell_index, ring->wptr); + } else { + WREG32(mmCP_RB0_WPTR, ring->wptr); + (void)RREG32(mmCP_RB0_WPTR); + } +} + +static void gfx_v8_0_hdp_flush_cp_ring_emit(struct amdgpu_ring *ring) +{ + u32 ref_and_mask, reg_mem_engine; + + if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { + switch (ring->me) { + case 1: + ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; + break; + case 2: + ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; + break; + default: + return; + } + reg_mem_engine = 0; + } else { + ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; + reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */ + } + + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ + WAIT_REG_MEM_FUNCTION(3) | /* == */ + reg_mem_engine)); + amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); + amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); + amdgpu_ring_write(ring, ref_and_mask); + amdgpu_ring_write(ring, ref_and_mask); + amdgpu_ring_write(ring, 0x20); /* poll interval */ +} + +static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib) +{ + u32 header, control = 0; + u32 next_rptr = ring->wptr + 5; + if (ring->type == AMDGPU_RING_TYPE_COMPUTE) + control |= INDIRECT_BUFFER_VALID; + + if (ib->flush_hdp_writefifo) + next_rptr += 7; + + if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) + next_rptr += 2; + + next_rptr += 4; + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); + amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); + amdgpu_ring_write(ring, next_rptr); + + if (ib->flush_hdp_writefifo) + gfx_v8_0_hdp_flush_cp_ring_emit(ring); + + /* insert SWITCH_BUFFER packet before first IB in the ring frame */ + if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) { + amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); + amdgpu_ring_write(ring, 0); + ring->need_ctx_switch = false; + } + + if (ib->is_const_ib) + header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); + else + header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); + + control |= ib->length_dw | + (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0); + + amdgpu_ring_write(ring, header); + amdgpu_ring_write(ring, +#ifdef __BIG_ENDIAN + (2 << 0) | +#endif + (ib->gpu_addr & 0xFFFFFFFC)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); + amdgpu_ring_write(ring, control); +} + +static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, + u64 seq, bool write64bit) +{ + /* EVENT_WRITE_EOP - flush caches, send int */ + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); + amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | + EOP_TC_ACTION_EN | + EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | + EVENT_INDEX(5))); + amdgpu_ring_write(ring, addr & 0xfffffffc); + amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | + DATA_SEL(write64bit ? 2 : 1) | INT_SEL(2)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + amdgpu_ring_write(ring, upper_32_bits(seq)); +} + +/** + * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring + * + * @ring: amdgpu ring buffer object + * @semaphore: amdgpu semaphore object + * @emit_wait: Is this a sempahore wait? + * + * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP + * from running ahead of semaphore waits. + */ +static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore, + bool emit_wait) +{ + uint64_t addr = semaphore->gpu_addr; + unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; + + if (ring->adev->asic_type == CHIP_TOPAZ || + ring->adev->asic_type == CHIP_TONGA) { + amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); + } else { + amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2)); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, sel); + } + + if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) { + /* Prevent the PFP from running ahead of the semaphore wait */ + amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); + amdgpu_ring_write(ring, 0x0); + } + + return true; +} + +static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4; + + /* instruct DE to set a magic number */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(5))); + amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); + amdgpu_ring_write(ring, 1); + + /* let CE wait till condition satisfied */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ + WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ + WAIT_REG_MEM_FUNCTION(3) | /* == */ + WAIT_REG_MEM_ENGINE(2))); /* ce */ + amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); + amdgpu_ring_write(ring, 1); + amdgpu_ring_write(ring, 0xffffffff); + amdgpu_ring_write(ring, 4); /* poll interval */ + + /* instruct CE to reset wb of ce_sync to zero */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | + WRITE_DATA_DST_SEL(5) | + WR_CONFIRM)); + amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); + amdgpu_ring_write(ring, 0); +} + +static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr) +{ + int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + u32 srbm_gfx_cntl = 0; + + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | + WRITE_DATA_DST_SEL(0))); + if (vm_id < 8) { + amdgpu_ring_write(ring, + (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); + } else { + amdgpu_ring_write(ring, + (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); + } + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, pd_addr >> 12); + + /* update SH_MEM_* regs */ + srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id); + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, srbm_gfx_cntl); + + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, mmSH_MEM_BASES); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */ + amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */ + amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ + amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ + + srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0); + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, srbm_gfx_cntl); + + + /* bits 0-15 are the VM contexts0-15 */ + /* invalidate the cache */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | + WRITE_DATA_DST_SEL(0))); + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 1 << vm_id); + + /* wait for the invalidate to complete */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ + WAIT_REG_MEM_FUNCTION(0) | /* always */ + WAIT_REG_MEM_ENGINE(0))); /* me */ + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 0); /* ref */ + amdgpu_ring_write(ring, 0); /* mask */ + amdgpu_ring_write(ring, 0x20); /* poll interval */ + + /* compute doesn't have PFP */ + if (usepfp) { + /* sync PFP to ME, otherwise we might get invalid PFP reads */ + amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); + amdgpu_ring_write(ring, 0x0); + + /* synce CE with ME to prevent CE fetch CEIB before context switch done */ + gfx_v8_0_ce_sync_me(ring); + } +} + +static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring) +{ + if (gfx_v8_0_is_idle(ring->adev)) { + amdgpu_ring_lockup_update(ring); + return false; + } + return amdgpu_ring_test_lockup(ring); +} + +static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring) +{ + return ring->adev->wb.wb[ring->rptr_offs]; +} + +static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring) +{ + return ring->adev->wb.wb[ring->wptr_offs]; +} + +static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + /* XXX check if swapping is necessary on BE */ + adev->wb.wb[ring->wptr_offs] = ring->wptr; + WDOORBELL32(ring->doorbell_index, ring->wptr); +} + +static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, + u64 addr, u64 seq, + bool write64bits) +{ + /* RELEASE_MEM - flush caches, send int */ + amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); + amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | + EOP_TC_ACTION_EN | + EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | + EVENT_INDEX(5))); + amdgpu_ring_write(ring, DATA_SEL(write64bits ? 2 : 1) | INT_SEL(2)); + amdgpu_ring_write(ring, addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + amdgpu_ring_write(ring, upper_32_bits(seq)); +} + +static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, + enum amdgpu_interrupt_state state) +{ + u32 cp_int_cntl; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + TIME_STAMP_INT_ENABLE, 0); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl = + REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + TIME_STAMP_INT_ENABLE, 1); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + default: + break; + } +} + +static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, + int me, int pipe, + enum amdgpu_interrupt_state state) +{ + u32 mec_int_cntl, mec_int_cntl_reg; + + /* + * amdgpu controls only pipe 0 of MEC1. That's why this function only + * handles the setting of interrupts for this specific pipe. All other + * pipes' interrupts are set by amdkfd. + */ + + if (me == 1) { + switch (pipe) { + case 0: + mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; + break; + default: + DRM_DEBUG("invalid pipe %d\n", pipe); + return; + } + } else { + DRM_DEBUG("invalid me %d\n", me); + return; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + mec_int_cntl = RREG32(mec_int_cntl_reg); + mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, + TIME_STAMP_INT_ENABLE, 0); + WREG32(mec_int_cntl_reg, mec_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + mec_int_cntl = RREG32(mec_int_cntl_reg); + mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, + TIME_STAMP_INT_ENABLE, 1); + WREG32(mec_int_cntl_reg, mec_int_cntl); + break; + default: + break; + } +} + +static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 cp_int_cntl; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + PRIV_REG_INT_ENABLE, 0); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + PRIV_REG_INT_ENABLE, 0); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + default: + break; + } + + return 0; +} + +static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 cp_int_cntl; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + PRIV_INSTR_INT_ENABLE, 0); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); + cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, + PRIV_INSTR_INT_ENABLE, 1); + WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); + break; + default: + break; + } + + return 0; +} + +static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + switch (type) { + case AMDGPU_CP_IRQ_GFX_EOP: + gfx_v8_0_set_gfx_eop_interrupt_state(adev, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: + gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: + gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: + gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: + gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: + gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: + gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: + gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: + gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state); + break; + default: + break; + } + return 0; +} + +static int gfx_v8_0_eop_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + int i; + u8 me_id, pipe_id, queue_id; + struct amdgpu_ring *ring; + + DRM_DEBUG("IH: CP EOP\n"); + me_id = (entry->ring_id & 0x0c) >> 2; + pipe_id = (entry->ring_id & 0x03) >> 0; + queue_id = (entry->ring_id & 0x70) >> 4; + + switch (me_id) { + case 0: + amdgpu_fence_process(&adev->gfx.gfx_ring[0]); + break; + case 1: + case 2: + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i]; + /* Per-queue interrupt is supported for MEC starting from VI. + * The interrupt can only be enabled/disabled per pipe instead of per queue. + */ + if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) + amdgpu_fence_process(ring); + } + break; + } + return 0; +} + +static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal register access in command stream\n"); + schedule_work(&adev->reset_work); + return 0; +} + +static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal instruction in command stream\n"); + schedule_work(&adev->reset_work); + return 0; +} + +const struct amdgpu_ip_funcs gfx_v8_0_ip_funcs = { + .early_init = gfx_v8_0_early_init, + .late_init = NULL, + .sw_init = gfx_v8_0_sw_init, + .sw_fini = gfx_v8_0_sw_fini, + .hw_init = gfx_v8_0_hw_init, + .hw_fini = gfx_v8_0_hw_fini, + .suspend = gfx_v8_0_suspend, + .resume = gfx_v8_0_resume, + .is_idle = gfx_v8_0_is_idle, + .wait_for_idle = gfx_v8_0_wait_for_idle, + .soft_reset = gfx_v8_0_soft_reset, + .print_status = gfx_v8_0_print_status, + .set_clockgating_state = gfx_v8_0_set_clockgating_state, + .set_powergating_state = gfx_v8_0_set_powergating_state, +}; + +static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { + .get_rptr = gfx_v8_0_ring_get_rptr_gfx, + .get_wptr = gfx_v8_0_ring_get_wptr_gfx, + .set_wptr = gfx_v8_0_ring_set_wptr_gfx, + .parse_cs = NULL, + .emit_ib = gfx_v8_0_ring_emit_ib, + .emit_fence = gfx_v8_0_ring_emit_fence_gfx, + .emit_semaphore = gfx_v8_0_ring_emit_semaphore, + .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, + .test_ring = gfx_v8_0_ring_test_ring, + .test_ib = gfx_v8_0_ring_test_ib, + .is_lockup = gfx_v8_0_ring_is_lockup, +}; + +static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { + .get_rptr = gfx_v8_0_ring_get_rptr_compute, + .get_wptr = gfx_v8_0_ring_get_wptr_compute, + .set_wptr = gfx_v8_0_ring_set_wptr_compute, + .parse_cs = NULL, + .emit_ib = gfx_v8_0_ring_emit_ib, + .emit_fence = gfx_v8_0_ring_emit_fence_compute, + .emit_semaphore = gfx_v8_0_ring_emit_semaphore, + .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, + .test_ring = gfx_v8_0_ring_test_ring, + .test_ib = gfx_v8_0_ring_test_ib, + .is_lockup = gfx_v8_0_ring_is_lockup, +}; + +static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) + adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; +} + +static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = { + .set = gfx_v8_0_set_eop_interrupt_state, + .process = gfx_v8_0_eop_irq, +}; + +static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = { + .set = gfx_v8_0_set_priv_reg_fault_state, + .process = gfx_v8_0_priv_reg_irq, +}; + +static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = { + .set = gfx_v8_0_set_priv_inst_fault_state, + .process = gfx_v8_0_priv_inst_irq, +}; + +static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; + adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; + + adev->gfx.priv_reg_irq.num_types = 1; + adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; + + adev->gfx.priv_inst_irq.num_types = 1; + adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; +} + +static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev) +{ + /* init asci gds info */ + adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); + adev->gds.gws.total_size = 64; + adev->gds.oa.total_size = 16; + + if (adev->gds.mem.total_size == 64 * 1024) { + adev->gds.mem.gfx_partition_size = 4096; + adev->gds.mem.cs_partition_size = 4096; + + adev->gds.gws.gfx_partition_size = 4; + adev->gds.gws.cs_partition_size = 4; + + adev->gds.oa.gfx_partition_size = 4; + adev->gds.oa.cs_partition_size = 1; + } else { + adev->gds.mem.gfx_partition_size = 1024; + adev->gds.mem.cs_partition_size = 1024; + + adev->gds.gws.gfx_partition_size = 16; + adev->gds.gws.cs_partition_size = 16; + + adev->gds.oa.gfx_partition_size = 4; + adev->gds.oa.cs_partition_size = 4; + } +} + +static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev, + u32 se, u32 sh) +{ + u32 mask = 0, tmp, tmp1; + int i; + + gfx_v8_0_select_se_sh(adev, se, sh); + tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); + tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + + tmp &= 0xffff0000; + + tmp |= tmp1; + tmp >>= 16; + + for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) { + mask <<= 1; + mask |= 1; + } + + return (~tmp) & mask; +} + +int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, + struct amdgpu_cu_info *cu_info) +{ + int i, j, k, counter, active_cu_number = 0; + u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; + + if (!adev || !cu_info) + return -EINVAL; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + mask = 1; + ao_bitmap = 0; + counter = 0; + bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j); + cu_info->bitmap[i][j] = bitmap; + + for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { + if (bitmap & mask) { + if (counter < 2) + ao_bitmap |= mask; + counter ++; + } + mask <<= 1; + } + active_cu_number += counter; + ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + } + } + + cu_info->number = active_cu_number; + cu_info->ao_cu_mask = ao_cu_mask; + mutex_unlock(&adev->grbm_idx_mutex); + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h new file mode 100644 index 000000000000..be8a5f8e176e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __GFX_V8_0_H__ +#define __GFX_V8_0_H__ + +extern const struct amdgpu_ip_funcs gfx_v8_0_ip_funcs; + +uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev); +void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num); +int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c new file mode 100644 index 000000000000..ac8cff85cde3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -0,0 +1,1271 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include "drmP.h" +#include "amdgpu.h" +#include "gmc_v8_0.h" +#include "amdgpu_ucode.h" + +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" + +#include "bif/bif_5_0_d.h" +#include "bif/bif_5_0_sh_mask.h" + +#include "oss/oss_3_0_d.h" +#include "oss/oss_3_0_sh_mask.h" + +#include "vid.h" +#include "vi.h" + +static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); +static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); + +MODULE_FIRMWARE("radeon/topaz_mc.bin"); +MODULE_FIRMWARE("radeon/tonga_mc.bin"); + +static const u32 golden_settings_tonga_a11[] = +{ + mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, + mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, + mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, + mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, +}; + +static const u32 tonga_mgcg_cgcg_init[] = +{ + mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 +}; + +static const u32 golden_settings_iceland_a11[] = +{ + mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, + mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff +}; + +static const u32 iceland_mgcg_cgcg_init[] = +{ + mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 +}; + +static const u32 cz_mgcg_cgcg_init[] = +{ + mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 +}; + +static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_TOPAZ: + amdgpu_program_register_sequence(adev, + iceland_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + golden_settings_iceland_a11, + (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + break; + case CHIP_TONGA: + amdgpu_program_register_sequence(adev, + tonga_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + golden_settings_tonga_a11, + (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + break; + case CHIP_CARRIZO: + amdgpu_program_register_sequence(adev, + cz_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + break; + default: + break; + } +} + +/** + * gmc8_mc_wait_for_idle - wait for MC idle callback. + * + * @adev: amdgpu_device pointer + * + * Wait for the MC (memory controller) to be idle. + * (evergreen+). + * Returns 0 if the MC is idle, -1 if not. + */ +int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK | + SRBM_STATUS__MCB_BUSY_MASK | + SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | + SRBM_STATUS__MCC_BUSY_MASK | + SRBM_STATUS__MCD_BUSY_MASK | + SRBM_STATUS__VMC1_BUSY_MASK); + if (!tmp) + return 0; + udelay(1); + } + return -1; +} + +void gmc_v8_0_mc_stop(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save) +{ + u32 blackout; + + if (adev->mode_info.num_crtc) + amdgpu_display_stop_mc_access(adev, save); + + amdgpu_asic_wait_for_mc_idle(adev); + + blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); + if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { + /* Block CPU access */ + WREG32(mmBIF_FB_EN, 0); + /* blackout the MC */ + blackout = REG_SET_FIELD(blackout, + MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); + WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); + } + /* wait for the MC to settle */ + udelay(100); +} + +void gmc_v8_0_mc_resume(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save) +{ + u32 tmp; + + /* unblackout the MC */ + tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); + tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); + WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); + /* allow CPU access */ + tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); + tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); + WREG32(mmBIF_FB_EN, tmp); + + if (adev->mode_info.num_crtc) + amdgpu_display_resume_mc_access(adev, save); +} + +/** + * gmc_v8_0_init_microcode - load ucode images from disk + * + * @adev: amdgpu_device pointer + * + * Use the firmware interface to load the ucode images into + * the driver (not loaded into hw). + * Returns 0 on success, error on failure. + */ +static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) +{ + const char *chip_name; + char fw_name[30]; + int err; + + DRM_DEBUG("\n"); + + switch (adev->asic_type) { + case CHIP_TOPAZ: + chip_name = "topaz"; + break; + case CHIP_TONGA: + chip_name = "tonga"; + break; + case CHIP_CARRIZO: + return 0; + default: BUG(); + } + + snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); + err = request_firmware(&adev->mc.fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->mc.fw); + +out: + if (err) { + printk(KERN_ERR + "mc: Failed to load firmware \"%s\"\n", + fw_name); + release_firmware(adev->mc.fw); + adev->mc.fw = NULL; + } + return err; +} + +/** + * gmc_v8_0_mc_load_microcode - load MC ucode into the hw + * + * @adev: amdgpu_device pointer + * + * Load the GDDR MC ucode into the hw (CIK). + * Returns 0 on success, error on failure. + */ +static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev) +{ + const struct mc_firmware_header_v1_0 *hdr; + const __le32 *fw_data = NULL; + const __le32 *io_mc_regs = NULL; + u32 running, blackout = 0; + int i, ucode_size, regs_size; + + if (!adev->mc.fw) + return -EINVAL; + + hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; + amdgpu_ucode_print_mc_hdr(&hdr->header); + + adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); + regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); + io_mc_regs = (const __le32 *) + (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + fw_data = (const __le32 *) + (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); + + if (running == 0) { + if (running) { + blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); + WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); + } + + /* reset the engine and set to writable */ + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); + + /* load mc io regs */ + for (i = 0; i < regs_size; i++) { + WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); + WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); + } + /* load the MC ucode */ + for (i = 0; i < ucode_size; i++) + WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); + + /* put the engine back into the active state */ + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); + WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); + + /* wait for training to complete */ + for (i = 0; i < adev->usec_timeout; i++) { + if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), + MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) + break; + udelay(1); + } + for (i = 0; i < adev->usec_timeout; i++) { + if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), + MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) + break; + udelay(1); + } + + if (running) + WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); + } + + return 0; +} + +static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, + struct amdgpu_mc *mc) +{ + if (mc->mc_vram_size > 0xFFC0000000ULL) { + /* leave room for at least 1024M GTT */ + dev_warn(adev->dev, "limiting VRAM\n"); + mc->real_vram_size = 0xFFC0000000ULL; + mc->mc_vram_size = 0xFFC0000000ULL; + } + amdgpu_vram_location(adev, &adev->mc, 0); + adev->mc.gtt_base_align = 0; + amdgpu_gtt_location(adev, mc); +} + +/** + * gmc_v8_0_mc_program - program the GPU memory controller + * + * @adev: amdgpu_device pointer + * + * Set the location of vram, gart, and AGP in the GPU's + * physical address space (CIK). + */ +static void gmc_v8_0_mc_program(struct amdgpu_device *adev) +{ + struct amdgpu_mode_mc_save save; + u32 tmp; + int i, j; + + /* Initialize HDP */ + for (i = 0, j = 0; i < 32; i++, j += 0x6) { + WREG32((0xb05 + j), 0x00000000); + WREG32((0xb06 + j), 0x00000000); + WREG32((0xb07 + j), 0x00000000); + WREG32((0xb08 + j), 0x00000000); + WREG32((0xb09 + j), 0x00000000); + } + WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); + + if (adev->mode_info.num_crtc) + amdgpu_display_set_vga_render_state(adev, false); + + gmc_v8_0_mc_stop(adev, &save); + if (amdgpu_asic_wait_for_mc_idle(adev)) { + dev_warn(adev->dev, "Wait for MC idle timedout !\n"); + } + /* Update configuration */ + WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, + adev->mc.vram_start >> 12); + WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, + adev->mc.vram_end >> 12); + WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, + adev->vram_scratch.gpu_addr >> 12); + tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; + tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); + WREG32(mmMC_VM_FB_LOCATION, tmp); + /* XXX double check these! */ + WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); + WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); + WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); + WREG32(mmMC_VM_AGP_BASE, 0); + WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); + WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); + if (amdgpu_asic_wait_for_mc_idle(adev)) { + dev_warn(adev->dev, "Wait for MC idle timedout !\n"); + } + gmc_v8_0_mc_resume(adev, &save); + + WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); + + tmp = RREG32(mmHDP_MISC_CNTL); + tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); + WREG32(mmHDP_MISC_CNTL, tmp); + + tmp = RREG32(mmHDP_HOST_PATH_CNTL); + WREG32(mmHDP_HOST_PATH_CNTL, tmp); +} + +/** + * gmc_v8_0_mc_init - initialize the memory controller driver params + * + * @adev: amdgpu_device pointer + * + * Look up the amount of vram, vram width, and decide how to place + * vram and gart within the GPU's physical address space (CIK). + * Returns 0 for success. + */ +static int gmc_v8_0_mc_init(struct amdgpu_device *adev) +{ + u32 tmp; + int chansize, numchan; + + /* Get VRAM informations */ + tmp = RREG32(mmMC_ARB_RAMCFG); + if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { + chansize = 64; + } else { + chansize = 32; + } + tmp = RREG32(mmMC_SHARED_CHMAP); + switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { + case 0: + default: + numchan = 1; + break; + case 1: + numchan = 2; + break; + case 2: + numchan = 4; + break; + case 3: + numchan = 8; + break; + case 4: + numchan = 3; + break; + case 5: + numchan = 6; + break; + case 6: + numchan = 10; + break; + case 7: + numchan = 12; + break; + case 8: + numchan = 16; + break; + } + adev->mc.vram_width = numchan * chansize; + /* Could aper size report 0 ? */ + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); + /* size in MB on si */ + adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + adev->mc.visible_vram_size = adev->mc.aper_size; + + /* unless the user had overridden it, set the gart + * size equal to the 1024 or vram, whichever is larger. + */ + if (amdgpu_gart_size == -1) + adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); + else + adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; + + gmc_v8_0_vram_gtt_location(adev, &adev->mc); + + return 0; +} + +/* + * GART + * VMID 0 is the physical GPU addresses as used by the kernel. + * VMIDs 1-15 are used for userspace clients and are handled + * by the amdgpu vm/hsa code. + */ + +/** + * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback + * + * @adev: amdgpu_device pointer + * @vmid: vm instance to flush + * + * Flush the TLB for the requested page table (CIK). + */ +static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + uint32_t vmid) +{ + /* flush hdp cache */ + WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); + + /* bits 0-15 are the VM contexts0-15 */ + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); +} + +/** + * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO + * + * @adev: amdgpu_device pointer + * @cpu_pt_addr: cpu address of the page table + * @gpu_page_idx: entry in the page table to update + * @addr: dst addr to write into pte/pde + * @flags: access flags + * + * Update the page tables using the CPU. + */ +static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev, + void *cpu_pt_addr, + uint32_t gpu_page_idx, + uint64_t addr, + uint32_t flags) +{ + void __iomem *ptr = (void *)cpu_pt_addr; + uint64_t value; + + /* + * PTE format on VI: + * 63:40 reserved + * 39:12 4k physical page base address + * 11:7 fragment + * 6 write + * 5 read + * 4 exe + * 3 reserved + * 2 snooped + * 1 system + * 0 valid + * + * PDE format on VI: + * 63:59 block fragment size + * 58:40 reserved + * 39:1 physical base address of PTE + * bits 5:1 must be 0. + * 0 valid + */ + value = addr & 0x000000FFFFFFF000ULL; + value |= flags; + writeq(value, ptr + (gpu_page_idx * 8)); + + return 0; +} + +/** + * gmc_v8_0_gart_enable - gart enable + * + * @adev: amdgpu_device pointer + * + * This sets up the TLBs, programs the page tables for VMID0, + * sets up the hw for VMIDs 1-15 which are allocated on + * demand, and sets up the global locations for the LDS, GDS, + * and GPUVM for FSA64 clients (CIK). + * Returns 0 for success, errors for failure. + */ +static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) +{ + int r, i; + u32 tmp; + + if (adev->gart.robj == NULL) { + dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); + return -EINVAL; + } + r = amdgpu_gart_table_vram_pin(adev); + if (r) + return r; + /* Setup TLB control */ + tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); + WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); + /* Setup L2 cache */ + tmp = RREG32(mmVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); + WREG32(mmVM_L2_CNTL, tmp); + tmp = RREG32(mmVM_L2_CNTL2); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); + WREG32(mmVM_L2_CNTL2, tmp); + tmp = RREG32(mmVM_L2_CNTL3); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); + WREG32(mmVM_L2_CNTL3, tmp); + /* XXX: set to enable PTE/PDE in system memory */ + tmp = RREG32(mmVM_L2_CNTL4); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); + WREG32(mmVM_L2_CNTL4, tmp); + /* setup context0 */ + WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); + WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(adev->dummy_page.addr >> 12)); + WREG32(mmVM_CONTEXT0_CNTL2, 0); + tmp = RREG32(mmVM_CONTEXT0_CNTL); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + WREG32(mmVM_CONTEXT0_CNTL, tmp); + + WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); + WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); + WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); + + /* empty context1-15 */ + /* FIXME start with 4G, once using 2 level pt switch to full + * vm size space + */ + /* set vm size, must be a multiple of 4 */ + WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); + WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn); + for (i = 1; i < 16; i++) { + if (i < 8) + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, + adev->gart.table_addr >> 12); + else + WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, + adev->gart.table_addr >> 12); + } + + /* enable context1-15 */ + WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(adev->dummy_page.addr >> 12)); + WREG32(mmVM_CONTEXT1_CNTL2, 4); + tmp = RREG32(mmVM_CONTEXT1_CNTL); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, + amdgpu_vm_block_size - 9); + WREG32(mmVM_CONTEXT1_CNTL, tmp); + + gmc_v8_0_gart_flush_gpu_tlb(adev, 0); + DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", + (unsigned)(adev->mc.gtt_size >> 20), + (unsigned long long)adev->gart.table_addr); + adev->gart.ready = true; + return 0; +} + +static int gmc_v8_0_gart_init(struct amdgpu_device *adev) +{ + int r; + + if (adev->gart.robj) { + WARN(1, "R600 PCIE GART already initialized\n"); + return 0; + } + /* Initialize common gart structure */ + r = amdgpu_gart_init(adev); + if (r) + return r; + adev->gart.table_size = adev->gart.num_gpu_pages * 8; + return amdgpu_gart_table_vram_alloc(adev); +} + +/** + * gmc_v8_0_gart_disable - gart disable + * + * @adev: amdgpu_device pointer + * + * This disables all VM page table (CIK). + */ +static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) +{ + u32 tmp; + + /* Disable all tables */ + WREG32(mmVM_CONTEXT0_CNTL, 0); + WREG32(mmVM_CONTEXT1_CNTL, 0); + /* Setup TLB control */ + tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); + WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); + /* Setup L2 cache */ + tmp = RREG32(mmVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); + WREG32(mmVM_L2_CNTL, tmp); + WREG32(mmVM_L2_CNTL2, 0); + amdgpu_gart_table_vram_unpin(adev); +} + +/** + * gmc_v8_0_gart_fini - vm fini callback + * + * @adev: amdgpu_device pointer + * + * Tears down the driver GART/VM setup (CIK). + */ +static void gmc_v8_0_gart_fini(struct amdgpu_device *adev) +{ + amdgpu_gart_table_vram_free(adev); + amdgpu_gart_fini(adev); +} + +/* + * vm + * VMID 0 is the physical GPU addresses as used by the kernel. + * VMIDs 1-15 are used for userspace clients and are handled + * by the amdgpu vm/hsa code. + */ +/** + * gmc_v8_0_vm_init - cik vm init callback + * + * @adev: amdgpu_device pointer + * + * Inits cik specific vm parameters (number of VMs, base of vram for + * VMIDs 1-15) (CIK). + * Returns 0 for success. + */ +static int gmc_v8_0_vm_init(struct amdgpu_device *adev) +{ + /* + * number of VMs + * VMID 0 is reserved for System + * amdgpu graphics/compute will use VMIDs 1-7 + * amdkfd will use VMIDs 8-15 + */ + adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS; + + /* base offset of vram pages */ + if (adev->flags & AMDGPU_IS_APU) { + u64 tmp = RREG32(mmMC_VM_FB_OFFSET); + tmp <<= 22; + adev->vm_manager.vram_base_offset = tmp; + } else + adev->vm_manager.vram_base_offset = 0; + + return 0; +} + +/** + * gmc_v8_0_vm_fini - cik vm fini callback + * + * @adev: amdgpu_device pointer + * + * Tear down any asic specific VM setup (CIK). + */ +static void gmc_v8_0_vm_fini(struct amdgpu_device *adev) +{ +} + +/** + * gmc_v8_0_vm_decode_fault - print human readable fault info + * + * @adev: amdgpu_device pointer + * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value + * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value + * + * Print human readable fault information (CIK). + */ +static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, + u32 status, u32 addr, u32 mc_client) +{ + u32 mc_id; + u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); + u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + PROTECTIONS); + char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, + (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; + + mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + MEMORY_CLIENT_ID); + + printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", + protections, vmid, addr, + REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, + MEMORY_CLIENT_RW) ? + "write" : "read", block, mc_client, mc_id); +} + +static int gmc_v8_0_early_init(struct amdgpu_device *adev) +{ + gmc_v8_0_set_gart_funcs(adev); + gmc_v8_0_set_irq_funcs(adev); + + if (adev->flags & AMDGPU_IS_APU) { + adev->mc.is_gddr5 = false; + } else { + u32 tmp = RREG32(mmMC_SEQ_MISC0); + + if (((tmp & MC_SEQ_MISC0__GDDR5_MASK) >> + MC_SEQ_MISC0__GDDR5__SHIFT) == MC_SEQ_MISC0__GDDR5_VALUE) + adev->mc.is_gddr5 = true; + else + adev->mc.is_gddr5 = false; + } + + return 0; +} + +static int gmc_v8_0_sw_init(struct amdgpu_device *adev) +{ + int r; + int dma_bits; + + r = amdgpu_gem_init(adev); + if (r) + return r; + + r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); + if (r) + return r; + + r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault); + if (r) + return r; + + /* Adjust VM size here. + * Currently set to 4GB ((1 << 20) 4k pages). + * Max GPUVM size for cayman and SI is 40 bits. + */ + adev->vm_manager.max_pfn = amdgpu_vm_size << 18; + + /* Set the internal MC address mask + * This is the max address of the GPU's + * internal address space. + */ + adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ + + /* set DMA mask + need_dma32 flags. + * PCIE - can handle 40-bits. + * IGP - can handle 40-bits + * PCI - dma32 for legacy pci gart, 40 bits on newer asics + */ + adev->need_dma32 = false; + dma_bits = adev->need_dma32 ? 32 : 40; + r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); + if (r) { + adev->need_dma32 = true; + dma_bits = 32; + printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); + } + r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); + if (r) { + pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); + printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); + } + + r = gmc_v8_0_init_microcode(adev); + if (r) { + DRM_ERROR("Failed to load mc firmware!\n"); + return r; + } + + r = gmc_v8_0_mc_init(adev); + if (r) + return r; + + /* Memory manager */ + r = amdgpu_bo_init(adev); + if (r) + return r; + + r = gmc_v8_0_gart_init(adev); + if (r) + return r; + + if (!adev->vm_manager.enabled) { + r = gmc_v8_0_vm_init(adev); + if (r) { + dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); + return r; + } + adev->vm_manager.enabled = true; + } + + return r; +} + +static int gmc_v8_0_sw_fini(struct amdgpu_device *adev) +{ + int i; + + if (adev->vm_manager.enabled) { + for (i = 0; i < AMDGPU_NUM_VM; ++i) + amdgpu_fence_unref(&adev->vm_manager.active[i]); + gmc_v8_0_vm_fini(adev); + adev->vm_manager.enabled = false; + } + gmc_v8_0_gart_fini(adev); + amdgpu_gem_fini(adev); + amdgpu_bo_fini(adev); + + return 0; +} + +static int gmc_v8_0_hw_init(struct amdgpu_device *adev) +{ + int r; + + gmc_v8_0_init_golden_registers(adev); + + gmc_v8_0_mc_program(adev); + + if (!(adev->flags & AMDGPU_IS_APU)) { + r = gmc_v8_0_mc_load_microcode(adev); + if (r) { + DRM_ERROR("Failed to load MC firmware!\n"); + return r; + } + } + + r = gmc_v8_0_gart_enable(adev); + if (r) + return r; + + return r; +} + +static int gmc_v8_0_hw_fini(struct amdgpu_device *adev) +{ + gmc_v8_0_gart_disable(adev); + + return 0; +} + +static int gmc_v8_0_suspend(struct amdgpu_device *adev) +{ + int i; + + if (adev->vm_manager.enabled) { + for (i = 0; i < AMDGPU_NUM_VM; ++i) + amdgpu_fence_unref(&adev->vm_manager.active[i]); + gmc_v8_0_vm_fini(adev); + adev->vm_manager.enabled = false; + } + gmc_v8_0_hw_fini(adev); + + return 0; +} + +static int gmc_v8_0_resume(struct amdgpu_device *adev) +{ + int r; + + r = gmc_v8_0_hw_init(adev); + if (r) + return r; + + if (!adev->vm_manager.enabled) { + r = gmc_v8_0_vm_init(adev); + if (r) { + dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); + return r; + } + adev->vm_manager.enabled = true; + } + + return r; +} + +static bool gmc_v8_0_is_idle(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmSRBM_STATUS); + + if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | + SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) + return false; + + return true; +} + +static int gmc_v8_0_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | + SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | + SRBM_STATUS__MCC_BUSY_MASK | + SRBM_STATUS__MCD_BUSY_MASK | + SRBM_STATUS__VMC_BUSY_MASK | + SRBM_STATUS__VMC1_BUSY_MASK); + if (!tmp) + return 0; + udelay(1); + } + return -ETIMEDOUT; + +} + +static void gmc_v8_0_print_status(struct amdgpu_device *adev) +{ + int i, j; + + dev_info(adev->dev, "GMC 8.x registers\n"); + dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", + RREG32(mmSRBM_STATUS)); + dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", + RREG32(mmSRBM_STATUS2)); + + dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); + dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); + dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n", + RREG32(mmMC_VM_MX_L1_TLB_CNTL)); + dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n", + RREG32(mmVM_L2_CNTL)); + dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n", + RREG32(mmVM_L2_CNTL2)); + dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n", + RREG32(mmVM_L2_CNTL3)); + dev_info(adev->dev, " VM_L2_CNTL4=0x%08X\n", + RREG32(mmVM_L2_CNTL4)); + dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)); + dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)); + dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)); + dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n", + RREG32(mmVM_CONTEXT0_CNTL2)); + dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n", + RREG32(mmVM_CONTEXT0_CNTL)); + dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n", + RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR)); + dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n", + RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR)); + dev_info(adev->dev, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n", + RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET)); + dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)); + dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)); + dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", + RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)); + dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n", + RREG32(mmVM_CONTEXT1_CNTL2)); + dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n", + RREG32(mmVM_CONTEXT1_CNTL)); + for (i = 0; i < 16; i++) { + if (i < 8) + dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", + i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i)); + else + dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", + i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8)); + } + dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n", + RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)); + dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n", + RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)); + dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n", + RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)); + dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n", + RREG32(mmMC_VM_FB_LOCATION)); + dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n", + RREG32(mmMC_VM_AGP_BASE)); + dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n", + RREG32(mmMC_VM_AGP_TOP)); + dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n", + RREG32(mmMC_VM_AGP_BOT)); + + dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n", + RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL)); + dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n", + RREG32(mmHDP_NONSURFACE_BASE)); + dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n", + RREG32(mmHDP_NONSURFACE_INFO)); + dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n", + RREG32(mmHDP_NONSURFACE_SIZE)); + dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n", + RREG32(mmHDP_MISC_CNTL)); + dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n", + RREG32(mmHDP_HOST_PATH_CNTL)); + + for (i = 0, j = 0; i < 32; i++, j += 0x6) { + dev_info(adev->dev, " %d:\n", i); + dev_info(adev->dev, " 0x%04X=0x%08X\n", + 0xb05 + j, RREG32(0xb05 + j)); + dev_info(adev->dev, " 0x%04X=0x%08X\n", + 0xb06 + j, RREG32(0xb06 + j)); + dev_info(adev->dev, " 0x%04X=0x%08X\n", + 0xb07 + j, RREG32(0xb07 + j)); + dev_info(adev->dev, " 0x%04X=0x%08X\n", + 0xb08 + j, RREG32(0xb08 + j)); + dev_info(adev->dev, " 0x%04X=0x%08X\n", + 0xb09 + j, RREG32(0xb09 + j)); + } + + dev_info(adev->dev, " BIF_FB_EN=0x%08X\n", + RREG32(mmBIF_FB_EN)); +} + +static int gmc_v8_0_soft_reset(struct amdgpu_device *adev) +{ + struct amdgpu_mode_mc_save save; + u32 srbm_soft_reset = 0; + u32 tmp = RREG32(mmSRBM_STATUS); + + if (tmp & SRBM_STATUS__VMC_BUSY_MASK) + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, + SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); + + if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | + SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { + if (!(adev->flags & AMDGPU_IS_APU)) + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, + SRBM_SOFT_RESET, SOFT_RESET_MC, 1); + } + + if (srbm_soft_reset) { + gmc_v8_0_print_status(adev); + + gmc_v8_0_mc_stop(adev, &save); + if (gmc_v8_0_wait_for_idle(adev)) { + dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); + } + + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + + gmc_v8_0_mc_resume(adev, &save); + udelay(50); + + gmc_v8_0_print_status(adev); + } + + return 0; +} + +static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 tmp; + u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + /* system context */ + tmp = RREG32(mmVM_CONTEXT0_CNTL); + tmp &= ~bits; + WREG32(mmVM_CONTEXT0_CNTL, tmp); + /* VMs */ + tmp = RREG32(mmVM_CONTEXT1_CNTL); + tmp &= ~bits; + WREG32(mmVM_CONTEXT1_CNTL, tmp); + break; + case AMDGPU_IRQ_STATE_ENABLE: + /* system context */ + tmp = RREG32(mmVM_CONTEXT0_CNTL); + tmp |= bits; + WREG32(mmVM_CONTEXT0_CNTL, tmp); + /* VMs */ + tmp = RREG32(mmVM_CONTEXT1_CNTL); + tmp |= bits; + WREG32(mmVM_CONTEXT1_CNTL, tmp); + break; + default: + break; + } + + return 0; +} + +static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + u32 addr, status, mc_client; + + addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); + status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); + mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); + dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", + entry->src_id, entry->src_data); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + addr); + dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + status); + gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); + /* reset addr and status */ + WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); + + return 0; +} + +static int gmc_v8_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + /* XXX handled via the smc on VI */ + + return 0; +} + +static int gmc_v8_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs gmc_v8_0_ip_funcs = { + .early_init = gmc_v8_0_early_init, + .late_init = NULL, + .sw_init = gmc_v8_0_sw_init, + .sw_fini = gmc_v8_0_sw_fini, + .hw_init = gmc_v8_0_hw_init, + .hw_fini = gmc_v8_0_hw_fini, + .suspend = gmc_v8_0_suspend, + .resume = gmc_v8_0_resume, + .is_idle = gmc_v8_0_is_idle, + .wait_for_idle = gmc_v8_0_wait_for_idle, + .soft_reset = gmc_v8_0_soft_reset, + .print_status = gmc_v8_0_print_status, + .set_clockgating_state = gmc_v8_0_set_clockgating_state, + .set_powergating_state = gmc_v8_0_set_powergating_state, +}; + +static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = { + .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb, + .set_pte_pde = gmc_v8_0_gart_set_pte_pde, +}; + +static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { + .set = gmc_v8_0_vm_fault_interrupt_state, + .process = gmc_v8_0_process_interrupt, +}; + +static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev) +{ + if (adev->gart.gart_funcs == NULL) + adev->gart.gart_funcs = &gmc_v8_0_gart_funcs; +} + +static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->mc.vm_fault.num_types = 1; + adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h new file mode 100644 index 000000000000..2dd7f809d4e1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h @@ -0,0 +1,36 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __GMC_V8_0_H__ +#define __GMC_V8_0_H__ + +extern const struct amdgpu_ip_funcs gmc_v8_0_ip_funcs; + +/* XXX these shouldn't be exported */ +void gmc_v8_0_mc_stop(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save); +void gmc_v8_0_mc_resume(struct amdgpu_device *adev, + struct amdgpu_mode_mc_save *save); +int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c new file mode 100644 index 000000000000..8f5c54be70b0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c @@ -0,0 +1,172 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "drmP.h" +#include "amdgpu.h" +#include "iceland_smumgr.h" + +MODULE_FIRMWARE("radeon/topaz_smc.bin"); + +static void iceland_dpm_set_funcs(struct amdgpu_device *adev); + +static int iceland_dpm_early_init(struct amdgpu_device *adev) +{ + iceland_dpm_set_funcs(adev); + + return 0; +} + +static int iceland_dpm_init_microcode(struct amdgpu_device *adev) +{ + char fw_name[30] = "radeon/topaz_smc.bin"; + int err; + + err = request_firmware(&adev->pm.fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->pm.fw); + +out: + if (err) { + DRM_ERROR("Failed to load firmware \"%s\"", fw_name); + release_firmware(adev->pm.fw); + adev->pm.fw = NULL; + } + return err; +} + +static int iceland_dpm_sw_init(struct amdgpu_device *adev) +{ + int ret; + + ret = iceland_dpm_init_microcode(adev); + if (ret) + return ret; + + return 0; +} + +static int iceland_dpm_sw_fini(struct amdgpu_device *adev) +{ + return 0; +} + +static int iceland_dpm_hw_init(struct amdgpu_device *adev) +{ + int ret; + + mutex_lock(&adev->pm.mutex); + + ret = iceland_smu_init(adev); + if (ret) { + DRM_ERROR("SMU initialization failed\n"); + goto fail; + } + + ret = iceland_smu_start(adev); + if (ret) { + DRM_ERROR("SMU start failed\n"); + goto fail; + } + + mutex_unlock(&adev->pm.mutex); + return 0; + +fail: + adev->firmware.smu_load = false; + mutex_unlock(&adev->pm.mutex); + return -EINVAL; +} + +static int iceland_dpm_hw_fini(struct amdgpu_device *adev) +{ + mutex_lock(&adev->pm.mutex); + iceland_smu_fini(adev); + mutex_unlock(&adev->pm.mutex); + return 0; +} + +static int iceland_dpm_suspend(struct amdgpu_device *adev) +{ + iceland_dpm_hw_fini(adev); + + return 0; +} + +static int iceland_dpm_resume(struct amdgpu_device *adev) +{ + iceland_dpm_hw_init(adev); + + return 0; +} + +static int iceland_dpm_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static int iceland_dpm_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs iceland_dpm_ip_funcs = { + .early_init = iceland_dpm_early_init, + .late_init = NULL, + .sw_init = iceland_dpm_sw_init, + .sw_fini = iceland_dpm_sw_fini, + .hw_init = iceland_dpm_hw_init, + .hw_fini = iceland_dpm_hw_fini, + .suspend = iceland_dpm_suspend, + .resume = iceland_dpm_resume, + .is_idle = NULL, + .wait_for_idle = NULL, + .soft_reset = NULL, + .print_status = NULL, + .set_clockgating_state = iceland_dpm_set_clockgating_state, + .set_powergating_state = iceland_dpm_set_powergating_state, +}; + +static const struct amdgpu_dpm_funcs iceland_dpm_funcs = { + .get_temperature = NULL, + .pre_set_power_state = NULL, + .set_power_state = NULL, + .post_set_power_state = NULL, + .display_configuration_changed = NULL, + .get_sclk = NULL, + .get_mclk = NULL, + .print_power_state = NULL, + .debugfs_print_current_performance_level = NULL, + .force_performance_level = NULL, + .vblank_too_short = NULL, + .powergate_uvd = NULL, +}; + +static void iceland_dpm_set_funcs(struct amdgpu_device *adev) +{ + if (NULL == adev->pm.funcs) + adev->pm.funcs = &iceland_dpm_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c new file mode 100644 index 000000000000..2de8adfac471 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -0,0 +1,435 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_ih.h" +#include "vid.h" + +#include "oss/oss_2_4_d.h" +#include "oss/oss_2_4_sh_mask.h" + +#include "bif/bif_5_1_d.h" +#include "bif/bif_5_1_sh_mask.h" + +/* + * Interrupts + * Starting with r6xx, interrupts are handled via a ring buffer. + * Ring buffers are areas of GPU accessible memory that the GPU + * writes interrupt vectors into and the host reads vectors out of. + * There is a rptr (read pointer) that determines where the + * host is currently reading, and a wptr (write pointer) + * which determines where the GPU has written. When the + * pointers are equal, the ring is idle. When the GPU + * writes vectors to the ring buffer, it increments the + * wptr. When there is an interrupt, the host then starts + * fetching commands and processing them until the pointers are + * equal again at which point it updates the rptr. + */ + +static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev); + +/** + * iceland_ih_enable_interrupts - Enable the interrupt ring buffer + * + * @adev: amdgpu_device pointer + * + * Enable the interrupt ring buffer (VI). + */ +static void iceland_ih_enable_interrupts(struct amdgpu_device *adev) +{ + u32 ih_cntl = RREG32(mmIH_CNTL); + u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); + + ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); + WREG32(mmIH_CNTL, ih_cntl); + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + adev->irq.ih.enabled = true; +} + +/** + * iceland_ih_disable_interrupts - Disable the interrupt ring buffer + * + * @adev: amdgpu_device pointer + * + * Disable the interrupt ring buffer (VI). + */ +static void iceland_ih_disable_interrupts(struct amdgpu_device *adev) +{ + u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); + u32 ih_cntl = RREG32(mmIH_CNTL); + + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); + ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + WREG32(mmIH_CNTL, ih_cntl); + /* set rptr, wptr to 0 */ + WREG32(mmIH_RB_RPTR, 0); + WREG32(mmIH_RB_WPTR, 0); + adev->irq.ih.enabled = false; + adev->irq.ih.rptr = 0; +} + +/** + * iceland_ih_irq_init - init and enable the interrupt ring + * + * @adev: amdgpu_device pointer + * + * Allocate a ring buffer for the interrupt controller, + * enable the RLC, disable interrupts, enable the IH + * ring buffer and enable it (VI). + * Called at device load and reume. + * Returns 0 for success, errors for failure. + */ +static int iceland_ih_irq_init(struct amdgpu_device *adev) +{ + int ret = 0; + int rb_bufsz; + u32 interrupt_cntl, ih_cntl, ih_rb_cntl; + u64 wptr_off; + + /* disable irqs */ + iceland_ih_disable_interrupts(adev); + + /* setup interrupt control */ + WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); + interrupt_cntl = RREG32(mmINTERRUPT_CNTL); + /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi + * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN + */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); + /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); + WREG32(mmINTERRUPT_CNTL, interrupt_cntl); + + /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ + WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); + + rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); + ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); + + /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); + + /* set the writeback address whether it's enabled or not */ + wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); + WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); + WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); + + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + + /* set rptr, wptr to 0 */ + WREG32(mmIH_RB_RPTR, 0); + WREG32(mmIH_RB_WPTR, 0); + + /* Default settings for IH_CNTL (disabled at first) */ + ih_cntl = RREG32(mmIH_CNTL); + ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); + + if (adev->irq.msi_enabled) + ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); + WREG32(mmIH_CNTL, ih_cntl); + + pci_set_master(adev->pdev); + + /* enable interrupts */ + iceland_ih_enable_interrupts(adev); + + return ret; +} + +/** + * iceland_ih_irq_disable - disable interrupts + * + * @adev: amdgpu_device pointer + * + * Disable interrupts on the hw (VI). + */ +static void iceland_ih_irq_disable(struct amdgpu_device *adev) +{ + iceland_ih_disable_interrupts(adev); + + /* Wait and acknowledge irq */ + mdelay(1); +} + +/** + * iceland_ih_get_wptr - get the IH ring buffer wptr + * + * @adev: amdgpu_device pointer + * + * Get the IH ring buffer wptr from either the register + * or the writeback memory buffer (VI). Also check for + * ring buffer overflow and deal with it. + * Used by cz_irq_process(VI). + * Returns the value of the wptr. + */ +static u32 iceland_ih_get_wptr(struct amdgpu_device *adev) +{ + u32 wptr, tmp; + + wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); + + if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { + wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); + /* When a ring buffer overflow happen start parsing interrupt + * from the last not overwritten vector (wptr + 16). Hopefully + * this should allow us to catchup. + */ + dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", + wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); + adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; + tmp = RREG32(mmIH_RB_CNTL); + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); + WREG32(mmIH_RB_CNTL, tmp); + } + return (wptr & adev->irq.ih.ptr_mask); +} + +/** + * iceland_ih_decode_iv - decode an interrupt vector + * + * @adev: amdgpu_device pointer + * + * Decodes the interrupt vector at the current rptr + * position and also advance the position. + */ +static void iceland_ih_decode_iv(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry) +{ + /* wptr/rptr are in bytes! */ + u32 ring_index = adev->irq.ih.rptr >> 2; + uint32_t dw[4]; + + dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); + dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); + dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); + dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); + + entry->src_id = dw[0] & 0xff; + entry->src_data = dw[1] & 0xfffffff; + entry->ring_id = dw[2] & 0xff; + entry->vm_id = (dw[2] >> 8) & 0xff; + entry->pas_id = (dw[2] >> 16) & 0xffff; + + /* wptr/rptr are in bytes! */ + adev->irq.ih.rptr += 16; +} + +/** + * iceland_ih_set_rptr - set the IH ring buffer rptr + * + * @adev: amdgpu_device pointer + * + * Set the IH ring buffer rptr. + */ +static void iceland_ih_set_rptr(struct amdgpu_device *adev) +{ + WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); +} + +static int iceland_ih_early_init(struct amdgpu_device *adev) +{ + iceland_ih_set_interrupt_funcs(adev); + return 0; +} + +static int iceland_ih_sw_init(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_ih_ring_init(adev, 64 * 1024, false); + if (r) + return r; + + r = amdgpu_irq_init(adev); + + return r; +} + +static int iceland_ih_sw_fini(struct amdgpu_device *adev) +{ + amdgpu_irq_fini(adev); + amdgpu_ih_ring_fini(adev); + + return 0; +} + +static int iceland_ih_hw_init(struct amdgpu_device *adev) +{ + int r; + + r = iceland_ih_irq_init(adev); + if (r) + return r; + + return 0; +} + +static int iceland_ih_hw_fini(struct amdgpu_device *adev) +{ + iceland_ih_irq_disable(adev); + + return 0; +} + +static int iceland_ih_suspend(struct amdgpu_device *adev) +{ + return iceland_ih_hw_fini(adev); +} + +static int iceland_ih_resume(struct amdgpu_device *adev) +{ + return iceland_ih_hw_init(adev); +} + +static bool iceland_ih_is_idle(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmSRBM_STATUS); + + if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) + return false; + + return true; +} + +static int iceland_ih_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(mmSRBM_STATUS); + if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static void iceland_ih_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "ICELAND IH registers\n"); + dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", + RREG32(mmSRBM_STATUS)); + dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", + RREG32(mmSRBM_STATUS2)); + dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", + RREG32(mmINTERRUPT_CNTL)); + dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", + RREG32(mmINTERRUPT_CNTL2)); + dev_info(adev->dev, " IH_CNTL=0x%08X\n", + RREG32(mmIH_CNTL)); + dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", + RREG32(mmIH_RB_CNTL)); + dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", + RREG32(mmIH_RB_BASE)); + dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", + RREG32(mmIH_RB_WPTR_ADDR_LO)); + dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", + RREG32(mmIH_RB_WPTR_ADDR_HI)); + dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", + RREG32(mmIH_RB_RPTR)); + dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", + RREG32(mmIH_RB_WPTR)); +} + +static int iceland_ih_soft_reset(struct amdgpu_device *adev) +{ + u32 srbm_soft_reset = 0; + u32 tmp = RREG32(mmSRBM_STATUS); + + if (tmp & SRBM_STATUS__IH_BUSY_MASK) + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, + SOFT_RESET_IH, 1); + + if (srbm_soft_reset) { + iceland_ih_print_status(adev); + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + + iceland_ih_print_status(adev); + } + + return 0; +} + +static int iceland_ih_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + // TODO + return 0; +} + +static int iceland_ih_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + // TODO + return 0; +} + +const struct amdgpu_ip_funcs iceland_ih_ip_funcs = { + .early_init = iceland_ih_early_init, + .late_init = NULL, + .sw_init = iceland_ih_sw_init, + .sw_fini = iceland_ih_sw_fini, + .hw_init = iceland_ih_hw_init, + .hw_fini = iceland_ih_hw_fini, + .suspend = iceland_ih_suspend, + .resume = iceland_ih_resume, + .is_idle = iceland_ih_is_idle, + .wait_for_idle = iceland_ih_wait_for_idle, + .soft_reset = iceland_ih_soft_reset, + .print_status = iceland_ih_print_status, + .set_clockgating_state = iceland_ih_set_clockgating_state, + .set_powergating_state = iceland_ih_set_powergating_state, +}; + +static const struct amdgpu_ih_funcs iceland_ih_funcs = { + .get_wptr = iceland_ih_get_wptr, + .decode_iv = iceland_ih_decode_iv, + .set_rptr = iceland_ih_set_rptr +}; + +static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev) +{ + if (adev->irq.ih_funcs == NULL) + adev->irq.ih_funcs = &iceland_ih_funcs; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h new file mode 100644 index 000000000000..d001895eb93b --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __ICELAND_IH_H__ +#define __ICELAND_IH_H__ + +extern const struct amdgpu_ip_funcs iceland_ih_ip_funcs; + +#endif /* __ICELAND_IH_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_sdma_pkt_open.h b/drivers/gpu/drm/amd/amdgpu/iceland_sdma_pkt_open.h new file mode 100644 index 000000000000..c723602c7b0c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/iceland_sdma_pkt_open.h @@ -0,0 +1,2167 @@ +/* + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __ICELAND_SDMA_PKT_OPEN_H_ +#define __ICELAND_SDMA_PKT_OPEN_H_ + +#define SDMA_OP_NOP 0 +#define SDMA_OP_COPY 1 +#define SDMA_OP_WRITE 2 +#define SDMA_OP_INDIRECT 4 +#define SDMA_OP_FENCE 5 +#define SDMA_OP_TRAP 6 +#define SDMA_OP_SEM 7 +#define SDMA_OP_POLL_REGMEM 8 +#define SDMA_OP_COND_EXE 9 +#define SDMA_OP_ATOMIC 10 +#define SDMA_OP_CONST_FILL 11 +#define SDMA_OP_GEN_PTEPDE 12 +#define SDMA_OP_TIMESTAMP 13 +#define SDMA_OP_SRBM_WRITE 14 +#define SDMA_OP_PRE_EXE 15 +#define SDMA_SUBOP_TIMESTAMP_SET 0 +#define SDMA_SUBOP_TIMESTAMP_GET 1 +#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 +#define SDMA_SUBOP_COPY_LINEAR 0 +#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 +#define SDMA_SUBOP_COPY_TILED 1 +#define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 +#define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 +#define SDMA_SUBOP_COPY_SOA 3 +#define SDMA_SUBOP_WRITE_LINEAR 0 +#define SDMA_SUBOP_WRITE_TILED 1 + +/*define for op field*/ +#define SDMA_PKT_HEADER_op_offset 0 +#define SDMA_PKT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_HEADER_op_shift 0 +#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_HEADER_sub_op_offset 0 +#define SDMA_PKT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_HEADER_sub_op_shift 8 +#define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) + +/* +** Definitions for SDMA_PKT_COPY_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) + +/*define for dst_ha field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift 22 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) + +/*define for src_ha field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift 30 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst2_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) + +/*define for dst2_ha field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift 14 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift) + +/*define for dst1_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) + +/*define for dst1_ha field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift 22 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) + +/*define for src_ha field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift 30 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST1_ADDR_LO word*/ +/*define for dst1_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) + +/*define for DST1_ADDR_HI word*/ +/*define for dst1_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) + +/*define for DST2_ADDR_LO word*/ +/*define for dst2_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) + +/*define for DST2_ADDR_HI word*/ +/*define for dst2_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) + +/*define for elementsize field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) + +/*define for src_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) + +/*define for DW_5 word*/ +/*define for src_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_8 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) + +/*define for DW_9 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) + +/*define for dst_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) + +/*define for DW_10 word*/ +/*define for dst_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) + +/*define for DW_11 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) + +/*define for DW_12 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) + +/*define for dst_ha field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift 22 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) + +/*define for src_ha field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift 30 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for pitch_in_tile field*/ +#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_offset 3 +#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift 0 +#define SDMA_PKT_COPY_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift) + +/*define for height field*/ +#define SDMA_PKT_COPY_TILED_DW_3_height_offset 3 +#define SDMA_PKT_COPY_TILED_DW_3_height_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_3_height_shift 16 +#define SDMA_PKT_COPY_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_height_mask) << SDMA_PKT_COPY_TILED_DW_3_height_shift) + +/*define for DW_4 word*/ +/*define for slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_offset 4 +#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) + +/*define for array_mode field*/ +#define SDMA_PKT_COPY_TILED_DW_5_array_mode_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_DW_5_array_mode_shift 3 +#define SDMA_PKT_COPY_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_array_mode_shift) + +/*define for mit_mode field*/ +#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift 8 +#define SDMA_PKT_COPY_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift) + +/*define for tilesplit_size field*/ +#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift) + +/*define for bank_w field*/ +#define SDMA_PKT_COPY_TILED_DW_5_bank_w_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_5_bank_w_shift 15 +#define SDMA_PKT_COPY_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_w_shift) + +/*define for bank_h field*/ +#define SDMA_PKT_COPY_TILED_DW_5_bank_h_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_5_bank_h_shift 18 +#define SDMA_PKT_COPY_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_h_shift) + +/*define for num_bank field*/ +#define SDMA_PKT_COPY_TILED_DW_5_num_bank_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_5_num_bank_shift 21 +#define SDMA_PKT_COPY_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_DW_5_num_bank_shift) + +/*define for mat_aspt field*/ +#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift 24 +#define SDMA_PKT_COPY_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift) + +/*define for pipe_config field*/ +#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift 26 +#define SDMA_PKT_COPY_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 +#define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 +#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 +#define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 +#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00000FFF +#define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 +#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for LINEAR_PITCH word*/ +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_TILED_COUNT_count_offset 11 +#define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 +#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) + +/*define for videocopy field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) + +/*define for TILED_ADDR_LO_0 word*/ +/*define for tiled_addr0_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) + +/*define for TILED_ADDR_HI_0 word*/ +/*define for tiled_addr0_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) + +/*define for TILED_ADDR_LO_1 word*/ +/*define for tiled_addr1_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) + +/*define for TILED_ADDR_HI_1 word*/ +/*define for tiled_addr1_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) + +/*define for DW_5 word*/ +/*define for pitch_in_tile field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_offset 5 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask 0x000007FF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift) + +/*define for height field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_offset 5 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift) + +/*define for DW_6 word*/ +/*define for slice_pitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_offset 6 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift) + +/*define for DW_7 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) + +/*define for array_mode field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift 3 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift) + +/*define for mit_mode field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIT_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift) + +/*define for tilesplit_size field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift) + +/*define for bank_w field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift 15 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_W(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift) + +/*define for bank_h field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift 18 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_H(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift) + +/*define for num_bank field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift 21 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_NUM_BANK(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift) + +/*define for mat_aspt field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift 24 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift) + +/*define for pipe_config field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift 26 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift) + +/*define for DW_8 word*/ +/*define for x field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) + +/*define for y field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) + +/*define for DW_9 word*/ +/*define for z field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00000FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) + +/*define for DW_10 word*/ +/*define for dst2_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) + +/*define for dst2_ha field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift 14 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_HA(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for LINEAR_PITCH word*/ +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 14 +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_COPY_T2T packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 +#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) + +/*define for src_pitch_in_tile field*/ +#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_offset 4 +#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask 0x00000FFF +#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift 16 +#define SDMA_PKT_COPY_T2T_DW_4_SRC_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift) + +/*define for DW_5 word*/ +/*define for src_slice_pitch field*/ +#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_offset 5 +#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift 0 +#define SDMA_PKT_COPY_T2T_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift) + +/*define for DW_6 word*/ +/*define for src_element_size field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) + +/*define for src_array_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift 3 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift) + +/*define for src_mit_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift 8 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift) + +/*define for src_tilesplit_size field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift) + +/*define for src_bank_w field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift 15 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift) + +/*define for src_bank_h field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift 18 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift) + +/*define for src_num_bank field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift 21 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift) + +/*define for src_mat_aspt field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift 24 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift) + +/*define for src_pipe_config field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift 26 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) + +/*define for DW_10 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) + +/*define for dst_pitch_in_tile field*/ +#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_offset 10 +#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask 0x00000FFF +#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift 16 +#define SDMA_PKT_COPY_T2T_DW_10_DST_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift) + +/*define for DW_11 word*/ +/*define for dst_slice_pitch field*/ +#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_offset 11 +#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift 0 +#define SDMA_PKT_COPY_T2T_DW_11_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift) + +/*define for DW_12 word*/ +/*define for dst_array_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift 3 +#define SDMA_PKT_COPY_T2T_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift) + +/*define for dst_mit_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift 8 +#define SDMA_PKT_COPY_T2T_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift) + +/*define for dst_tilesplit_size field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_T2T_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift) + +/*define for dst_bank_w field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift 15 +#define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift) + +/*define for dst_bank_h field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift 18 +#define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift) + +/*define for dst_num_bank field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift 21 +#define SDMA_PKT_COPY_T2T_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift) + +/*define for dst_mat_aspt field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift 24 +#define SDMA_PKT_COPY_T2T_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift) + +/*define for dst_pipe_config field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift 26 +#define SDMA_PKT_COPY_T2T_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift) + +/*define for DW_13 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) + +/*define for DW_14 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 +#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 +#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for tiled_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) + +/*define for tiled_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) + +/*define for DW_4 word*/ +/*define for tiled_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) + +/*define for pitch_in_tile field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask 0x00000FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift) + +/*define for DW_5 word*/ +/*define for slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_offset 5 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift) + +/*define for DW_6 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) + +/*define for array_mode field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift) + +/*define for mit_mode field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift) + +/*define for tilesplit_size field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift) + +/*define for bank_w field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift 15 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift) + +/*define for bank_h field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift 18 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift) + +/*define for num_bank field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift 21 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift) + +/*define for mat_aspt field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift) + +/*define for pipe_config field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift 26 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for linear_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) + +/*define for linear_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) + +/*define for DW_10 word*/ +/*define for linear_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) + +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) + +/*define for DW_11 word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) + +/*define for DW_12 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) + +/*define for DW_13 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_STRUCT packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) + +/*define for SB_ADDR_LO word*/ +/*define for sb_addr_31_0 field*/ +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) + +/*define for SB_ADDR_HI word*/ +/*define for sb_addr_63_32 field*/ +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) + +/*define for START_INDEX word*/ +/*define for start_index field*/ +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 +#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 +#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 +#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) + +/*define for DW_5 word*/ +/*define for stride field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) + +/*define for struct_sw field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 16 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) + +/*define for struct_ha field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift 22 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 24 +#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) + +/*define for linear_ha field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift 30 +#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_UNTILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x003FFFFF +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) + +/*define for sw field*/ +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 +#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_TILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for pitch_in_tile field*/ +#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_offset 3 +#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask 0x000007FF +#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift) + +/*define for height field*/ +#define SDMA_PKT_WRITE_TILED_DW_3_height_offset 3 +#define SDMA_PKT_WRITE_TILED_DW_3_height_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_3_height_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_height_mask) << SDMA_PKT_WRITE_TILED_DW_3_height_shift) + +/*define for DW_4 word*/ +/*define for slice_pitch field*/ +#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_offset 4 +#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) + +/*define for array_mode field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask 0x0000000F +#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift 3 +#define SDMA_PKT_WRITE_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift) + +/*define for mit_mode field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift 8 +#define SDMA_PKT_WRITE_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift) + +/*define for tilesplit_size field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift 11 +#define SDMA_PKT_WRITE_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift) + +/*define for bank_w field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift 15 +#define SDMA_PKT_WRITE_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift) + +/*define for bank_h field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift 18 +#define SDMA_PKT_WRITE_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift) + +/*define for num_bank field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift 21 +#define SDMA_PKT_WRITE_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift) + +/*define for mat_aspt field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift 24 +#define SDMA_PKT_WRITE_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift) + +/*define for pipe_config field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask 0x0000001F +#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift 26 +#define SDMA_PKT_WRITE_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 +#define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 +#define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 +#define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00000FFF +#define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) + +/*define for sw field*/ +#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 +#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 +#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 +#define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 +#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 +#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 +#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_INCR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for MASK_DW0 word*/ +/*define for mask_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) + +/*define for MASK_DW1 word*/ +/*define for mask_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) + +/*define for INIT_DW0 word*/ +/*define for init_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) + +/*define for INIT_DW1 word*/ +/*define for init_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) + +/*define for INCR_DW0 word*/ +/*define for incr_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) + +/*define for INCR_DW1 word*/ +/*define for incr_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 +#define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF +#define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 +#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_INDIRECT packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_INDIRECT_HEADER_op_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_INDIRECT_HEADER_op_shift 0 +#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 +#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) + +/*define for vmid field*/ +#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F +#define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 +#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) + +/*define for BASE_LO word*/ +/*define for ib_base_31_0 field*/ +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 +#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) + +/*define for BASE_HI word*/ +/*define for ib_base_63_32 field*/ +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 +#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) + +/*define for IB_SIZE word*/ +/*define for ib_size field*/ +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 +#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) + +/*define for CSA_ADDR_LO word*/ +/*define for csa_addr_31_0 field*/ +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) + +/*define for CSA_ADDR_HI word*/ +/*define for csa_addr_63_32 field*/ +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_SEMAPHORE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 +#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 +#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) + +/*define for write_one field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 +#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) + +/*define for signal field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 +#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) + +/*define for mailbox field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 +#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_FENCE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_FENCE_HEADER_op_offset 0 +#define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_FENCE_HEADER_op_shift 0 +#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 +#define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 +#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) + +/*define for DATA word*/ +/*define for data field*/ +#define SDMA_PKT_FENCE_DATA_data_offset 3 +#define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_DATA_data_shift 0 +#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) + + +/* +** Definitions for SDMA_PKT_SRBM_WRITE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 +#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) + +/*define for byte_en field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 +#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) + +/*define for ADDR word*/ +/*define for addr field*/ +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0000FFFF +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 +#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) + +/*define for DATA word*/ +/*define for data field*/ +#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 +#define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF +#define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 +#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) + + +/* +** Definitions for SDMA_PKT_PRE_EXE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 +#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 +#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) + +/*define for dev_sel field*/ +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 +#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) + +/*define for EXEC_COUNT word*/ +/*define for exec_count field*/ +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) + + +/* +** Definitions for SDMA_PKT_COND_EXE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COND_EXE_HEADER_op_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COND_EXE_HEADER_op_shift 0 +#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 +#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) + +/*define for REFERENCE word*/ +/*define for reference field*/ +#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 +#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 +#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) + +/*define for EXEC_COUNT word*/ +/*define for exec_count field*/ +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 +#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) + + +/* +** Definitions for SDMA_PKT_CONSTANT_FILL packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 +#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) + +/*define for sw field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 +#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) + +/*define for fillsize field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 +#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DATA word*/ +/*define for src_data_31_0 field*/ +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 +#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_POLL_REGMEM packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) + +/*define for hdp_flush field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 +#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) + +/*define for func field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 +#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 +#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) + +/*define for mem_poll field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 +#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) + +/*define for VALUE word*/ +/*define for value field*/ +#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 +#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 +#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) + +/*define for MASK word*/ +/*define for mask field*/ +#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 +#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 +#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) + +/*define for DW5 word*/ +/*define for interval field*/ +#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 +#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF +#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 +#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) + +/*define for retry_count field*/ +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 +#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_SET packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) + +/*define for INIT_DATA_LO word*/ +/*define for init_data_31_0 field*/ +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) + +/*define for INIT_DATA_HI word*/ +/*define for init_data_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_GET packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) + +/*define for WRITE_ADDR_LO word*/ +/*define for write_addr_31_3 field*/ +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) + +/*define for WRITE_ADDR_HI word*/ +/*define for write_addr_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) + +/*define for WRITE_ADDR_LO word*/ +/*define for write_addr_31_3 field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) + +/*define for WRITE_ADDR_HI word*/ +/*define for write_addr_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TRAP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TRAP_HEADER_op_offset 0 +#define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TRAP_HEADER_op_shift 0 +#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 +#define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 +#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) + +/*define for INT_CONTEXT word*/ +/*define for int_context field*/ +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 +#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) + + +/* +** Definitions for SDMA_PKT_NOP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_NOP_HEADER_op_offset 0 +#define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_NOP_HEADER_op_shift 0 +#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_NOP_HEADER_sub_op_offset 0 +#define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_NOP_HEADER_sub_op_shift 8 +#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) + + +#endif /* __ICELAND_SDMA_PKT_OPEN_H_ */ diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_smc.c b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c new file mode 100644 index 000000000000..c6f1e2f12b5f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/iceland_smc.c @@ -0,0 +1,675 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "drmP.h" +#include "amdgpu.h" +#include "ppsmc.h" +#include "iceland_smumgr.h" +#include "smu_ucode_xfer_vi.h" +#include "amdgpu_ucode.h" + +#include "smu/smu_7_1_1_d.h" +#include "smu/smu_7_1_1_sh_mask.h" + +#define ICELAND_SMC_SIZE 0x20000 + +static int iceland_set_smc_sram_address(struct amdgpu_device *adev, + uint32_t smc_address, uint32_t limit) +{ + uint32_t val; + + if (smc_address & 3) + return -EINVAL; + + if ((smc_address + 3) > limit) + return -EINVAL; + + WREG32(mmSMC_IND_INDEX_0, smc_address); + + val = RREG32(mmSMC_IND_ACCESS_CNTL); + val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); + WREG32(mmSMC_IND_ACCESS_CNTL, val); + + return 0; +} + +static int iceland_copy_bytes_to_smc(struct amdgpu_device *adev, + uint32_t smc_start_address, + const uint8_t *src, + uint32_t byte_count, uint32_t limit) +{ + uint32_t addr; + uint32_t data, orig_data; + int result = 0; + uint32_t extra_shift; + unsigned long flags; + + if (smc_start_address & 3) + return -EINVAL; + + if ((smc_start_address + byte_count) > limit) + return -EINVAL; + + addr = smc_start_address; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + while (byte_count >= 4) { + /* Bytes are written into the SMC addres space with the MSB first */ + data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3]; + + result = iceland_set_smc_sram_address(adev, addr, limit); + + if (result) + goto out; + + WREG32(mmSMC_IND_DATA_0, data); + + src += 4; + byte_count -= 4; + addr += 4; + } + + if (0 != byte_count) { + /* Now write odd bytes left, do a read modify write cycle */ + data = 0; + + result = iceland_set_smc_sram_address(adev, addr, limit); + if (result) + goto out; + + orig_data = RREG32(mmSMC_IND_DATA_0); + extra_shift = 8 * (4 - byte_count); + + while (byte_count > 0) { + data = (data << 8) + *src++; + byte_count--; + } + + data <<= extra_shift; + data |= (orig_data & ~((~0UL) << extra_shift)); + + result = iceland_set_smc_sram_address(adev, addr, limit); + if (result) + goto out; + + WREG32(mmSMC_IND_DATA_0, data); + } + +out: + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + return result; +} + +void iceland_start_smc(struct amdgpu_device *adev) +{ + uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); + + val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0); + WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); +} + +void iceland_reset_smc(struct amdgpu_device *adev) +{ + uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); + + val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1); + WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); +} + +static int iceland_program_jump_on_start(struct amdgpu_device *adev) +{ + static unsigned char data[] = {0xE0, 0x00, 0x80, 0x40}; + iceland_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1); + + return 0; +} + +void iceland_stop_smc_clock(struct amdgpu_device *adev) +{ + uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + + val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1); + WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val); +} + +void iceland_start_smc_clock(struct amdgpu_device *adev) +{ + uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + + val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); + WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val); +} + +static bool iceland_is_smc_ram_running(struct amdgpu_device *adev) +{ + uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + val = REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable); + + return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C))); +} + +static int wait_smu_response(struct amdgpu_device *adev) +{ + int i; + uint32_t val; + + for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32(mmSMC_RESP_0); + if (REG_GET_FIELD(val, SMC_RESP_0, SMC_RESP)) + break; + udelay(1); + } + + if (i == adev->usec_timeout) + return -EINVAL; + + return 0; +} + +static int iceland_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg) +{ + if (!iceland_is_smc_ram_running(adev)) + return -EINVAL; + + if (wait_smu_response(adev)) { + DRM_ERROR("Failed to send previous message\n"); + return -EINVAL; + } + + WREG32(mmSMC_MESSAGE_0, msg); + + if (wait_smu_response(adev)) { + DRM_ERROR("Failed to send message\n"); + return -EINVAL; + } + + return 0; +} + +static int iceland_send_msg_to_smc_without_waiting(struct amdgpu_device *adev, + PPSMC_Msg msg) +{ + if (!iceland_is_smc_ram_running(adev)) + return -EINVAL;; + + if (wait_smu_response(adev)) { + DRM_ERROR("Failed to send previous message\n"); + return -EINVAL; + } + + WREG32(mmSMC_MESSAGE_0, msg); + + return 0; +} + +static int iceland_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, + PPSMC_Msg msg, + uint32_t parameter) +{ + WREG32(mmSMC_MSG_ARG_0, parameter); + + return iceland_send_msg_to_smc(adev, msg); +} + +static int iceland_send_msg_to_smc_with_parameter_without_waiting( + struct amdgpu_device *adev, + PPSMC_Msg msg, uint32_t parameter) +{ + WREG32(mmSMC_MSG_ARG_0, parameter); + + return iceland_send_msg_to_smc_without_waiting(adev, msg); +} + +#if 0 /* not used yet */ +static int iceland_wait_for_smc_inactive(struct amdgpu_device *adev) +{ + int i; + uint32_t val; + + if (!iceland_is_smc_ram_running(adev)) + return -EINVAL; + + for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + if (REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, cken) == 0) + break; + udelay(1); + } + + if (i == adev->usec_timeout) + return -EINVAL; + + return 0; +} +#endif + +static int iceland_smu_upload_firmware_image(struct amdgpu_device *adev) +{ + const struct smc_firmware_header_v1_0 *hdr; + uint32_t ucode_size; + uint32_t ucode_start_address; + const uint8_t *src; + uint32_t val; + uint32_t byte_count; + uint32_t data; + unsigned long flags; + int i; + + if (!adev->pm.fw) + return -EINVAL; + + hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data; + amdgpu_ucode_print_smc_hdr(&hdr->header); + + adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); + ucode_start_address = le32_to_cpu(hdr->ucode_start_addr); + src = (const uint8_t *) + (adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + if (ucode_size & 3) { + DRM_ERROR("SMC ucode is not 4 bytes aligned\n"); + return -EINVAL; + } + + if (ucode_size > ICELAND_SMC_SIZE) { + DRM_ERROR("SMC address is beyond the SMC RAM area\n"); + return -EINVAL; + } + + for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32_SMC(ixRCU_UC_EVENTS); + if (REG_GET_FIELD(val, RCU_UC_EVENTS, boot_seq_done) == 0) + break; + udelay(1); + } + val = RREG32_SMC(ixSMC_SYSCON_MISC_CNTL); + WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, val | 1); + + iceland_stop_smc_clock(adev); + iceland_reset_smc(adev); + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + WREG32(mmSMC_IND_INDEX_0, ucode_start_address); + + val = RREG32(mmSMC_IND_ACCESS_CNTL); + val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); + WREG32(mmSMC_IND_ACCESS_CNTL, val); + + byte_count = ucode_size; + while (byte_count >= 4) { + data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3]; + WREG32(mmSMC_IND_DATA_0, data); + src += 4; + byte_count -= 4; + } + val = RREG32(mmSMC_IND_ACCESS_CNTL); + val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); + WREG32(mmSMC_IND_ACCESS_CNTL, val); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + + return 0; +} + +#if 0 /* not used yet */ +static int iceland_read_smc_sram_dword(struct amdgpu_device *adev, + uint32_t smc_address, + uint32_t *value, + uint32_t limit) +{ + int result; + unsigned long flags; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + result = iceland_set_smc_sram_address(adev, smc_address, limit); + if (result == 0) + *value = RREG32(mmSMC_IND_DATA_0); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + return result; +} + +static int iceland_write_smc_sram_dword(struct amdgpu_device *adev, + uint32_t smc_address, + uint32_t value, + uint32_t limit) +{ + int result; + unsigned long flags; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + result = iceland_set_smc_sram_address(adev, smc_address, limit); + if (result == 0) + WREG32(mmSMC_IND_DATA_0, value); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + return result; +} + +static int iceland_smu_stop_smc(struct amdgpu_device *adev) +{ + iceland_reset_smc(adev); + iceland_stop_smc_clock(adev); + + return 0; +} +#endif + +static int iceland_smu_start_smc(struct amdgpu_device *adev) +{ + int i; + uint32_t val; + + iceland_program_jump_on_start(adev); + iceland_start_smc_clock(adev); + iceland_start_smc(adev); + + for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32_SMC(ixFIRMWARE_FLAGS); + if (REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED) == 1) + break; + udelay(1); + } + return 0; +} + +static enum AMDGPU_UCODE_ID iceland_convert_fw_type(uint32_t fw_type) +{ + switch (fw_type) { + case UCODE_ID_SDMA0: + return AMDGPU_UCODE_ID_SDMA0; + case UCODE_ID_SDMA1: + return AMDGPU_UCODE_ID_SDMA1; + case UCODE_ID_CP_CE: + return AMDGPU_UCODE_ID_CP_CE; + case UCODE_ID_CP_PFP: + return AMDGPU_UCODE_ID_CP_PFP; + case UCODE_ID_CP_ME: + return AMDGPU_UCODE_ID_CP_ME; + case UCODE_ID_CP_MEC: + case UCODE_ID_CP_MEC_JT1: + return AMDGPU_UCODE_ID_CP_MEC1; + case UCODE_ID_CP_MEC_JT2: + return AMDGPU_UCODE_ID_CP_MEC2; + case UCODE_ID_RLC_G: + return AMDGPU_UCODE_ID_RLC_G; + default: + DRM_ERROR("ucode type is out of range!\n"); + return AMDGPU_UCODE_ID_MAXIMUM; + } +} + +static uint32_t iceland_smu_get_mask_for_fw_type(uint32_t fw_type) +{ + switch (fw_type) { + case AMDGPU_UCODE_ID_SDMA0: + return UCODE_ID_SDMA0_MASK; + case AMDGPU_UCODE_ID_SDMA1: + return UCODE_ID_SDMA1_MASK; + case AMDGPU_UCODE_ID_CP_CE: + return UCODE_ID_CP_CE_MASK; + case AMDGPU_UCODE_ID_CP_PFP: + return UCODE_ID_CP_PFP_MASK; + case AMDGPU_UCODE_ID_CP_ME: + return UCODE_ID_CP_ME_MASK; + case AMDGPU_UCODE_ID_CP_MEC1: + return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT2_MASK; + case AMDGPU_UCODE_ID_CP_MEC2: + return UCODE_ID_CP_MEC_MASK; + case AMDGPU_UCODE_ID_RLC_G: + return UCODE_ID_RLC_G_MASK; + default: + DRM_ERROR("ucode type is out of range!\n"); + return 0; + } +} + +static int iceland_smu_populate_single_firmware_entry(struct amdgpu_device *adev, + uint32_t fw_type, + struct SMU_Entry *entry) +{ + enum AMDGPU_UCODE_ID id = iceland_convert_fw_type(fw_type); + struct amdgpu_firmware_info *ucode = &adev->firmware.ucode[id]; + const struct gfx_firmware_header_v1_0 *header = NULL; + uint64_t gpu_addr; + uint32_t data_size; + + if (ucode->fw == NULL) + return -EINVAL; + + gpu_addr = ucode->mc_addr; + header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; + data_size = le32_to_cpu(header->header.ucode_size_bytes); + + entry->version = (uint16_t)le32_to_cpu(header->header.ucode_version); + entry->id = (uint16_t)fw_type; + entry->image_addr_high = upper_32_bits(gpu_addr); + entry->image_addr_low = lower_32_bits(gpu_addr); + entry->meta_data_addr_high = 0; + entry->meta_data_addr_low = 0; + entry->data_size_byte = data_size; + entry->num_register_entries = 0; + entry->flags = 0; + + return 0; +} + +static int iceland_smu_request_load_fw(struct amdgpu_device *adev) +{ + struct iceland_smu_private_data *private = (struct iceland_smu_private_data *)adev->smu.priv; + struct SMU_DRAMData_TOC *toc; + uint32_t fw_to_load; + + toc = (struct SMU_DRAMData_TOC *)private->header; + toc->num_entries = 0; + toc->structure_version = 1; + + if (!adev->firmware.smu_load) + return 0; + + if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_RLC_G, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for RLC\n"); + return -EINVAL; + } + + if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_CE, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for CE\n"); + return -EINVAL; + } + + if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_PFP, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for PFP\n"); + return -EINVAL; + } + + if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_ME, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for ME\n"); + return -EINVAL; + } + + if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for MEC\n"); + return -EINVAL; + } + + if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT1, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for MEC_JT1\n"); + return -EINVAL; + } + + if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for MEC_JT2\n"); + return -EINVAL; + } + + if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for SDMA0\n"); + return -EINVAL; + } + + if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA1, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for SDMA1\n"); + return -EINVAL; + } + + iceland_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_HI, private->header_addr_high); + iceland_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_LO, private->header_addr_low); + + fw_to_load = UCODE_ID_RLC_G_MASK | + UCODE_ID_SDMA0_MASK | + UCODE_ID_SDMA1_MASK | + UCODE_ID_CP_CE_MASK | + UCODE_ID_CP_ME_MASK | + UCODE_ID_CP_PFP_MASK | + UCODE_ID_CP_MEC_MASK | + UCODE_ID_CP_MEC_JT1_MASK | + UCODE_ID_CP_MEC_JT2_MASK; + + if (iceland_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) { + DRM_ERROR("Fail to request SMU load ucode\n"); + return -EINVAL; + } + + return 0; +} + +static int iceland_smu_check_fw_load_finish(struct amdgpu_device *adev, + uint32_t fw_type) +{ + uint32_t fw_mask = iceland_smu_get_mask_for_fw_type(fw_type); + int i; + + for (i = 0; i < adev->usec_timeout; i++) { + if (fw_mask == (RREG32_SMC(ixSOFT_REGISTERS_TABLE_27) & fw_mask)) + break; + udelay(1); + } + + if (i == adev->usec_timeout) { + DRM_ERROR("check firmware loading failed\n"); + return -EINVAL; + } + + return 0; +} + +int iceland_smu_start(struct amdgpu_device *adev) +{ + int result; + + result = iceland_smu_upload_firmware_image(adev); + if (result) + return result; + result = iceland_smu_start_smc(adev); + if (result) + return result; + + return iceland_smu_request_load_fw(adev); +} + +static const struct amdgpu_smumgr_funcs iceland_smumgr_funcs = { + .check_fw_load_finish = iceland_smu_check_fw_load_finish, + .request_smu_load_fw = NULL, + .request_smu_specific_fw = NULL, +}; + +int iceland_smu_init(struct amdgpu_device *adev) +{ + struct iceland_smu_private_data *private; + uint32_t image_size = ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; + struct amdgpu_bo **toc_buf = &adev->smu.toc_buf; + uint64_t mc_addr; + void *toc_buf_ptr; + int ret; + + private = kzalloc(sizeof(struct iceland_smu_private_data), GFP_KERNEL); + if (NULL == private) + return -ENOMEM; + + /* allocate firmware buffers */ + if (adev->firmware.smu_load) + amdgpu_ucode_init_bo(adev); + + adev->smu.priv = private; + adev->smu.fw_flags = 0; + + /* Allocate FW image data structure and header buffer */ + ret = amdgpu_bo_create(adev, image_size, PAGE_SIZE, + true, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, toc_buf); + if (ret) { + DRM_ERROR("Failed to allocate memory for TOC buffer\n"); + return -ENOMEM; + } + + /* Retrieve GPU address for header buffer and internal buffer */ + ret = amdgpu_bo_reserve(adev->smu.toc_buf, false); + if (ret) { + amdgpu_bo_unref(&adev->smu.toc_buf); + DRM_ERROR("Failed to reserve the TOC buffer\n"); + return -EINVAL; + } + + ret = amdgpu_bo_pin(adev->smu.toc_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr); + if (ret) { + amdgpu_bo_unreserve(adev->smu.toc_buf); + amdgpu_bo_unref(&adev->smu.toc_buf); + DRM_ERROR("Failed to pin the TOC buffer\n"); + return -EINVAL; + } + + ret = amdgpu_bo_kmap(*toc_buf, &toc_buf_ptr); + if (ret) { + amdgpu_bo_unreserve(adev->smu.toc_buf); + amdgpu_bo_unref(&adev->smu.toc_buf); + DRM_ERROR("Failed to map the TOC buffer\n"); + return -EINVAL; + } + + amdgpu_bo_unreserve(adev->smu.toc_buf); + private->header_addr_low = lower_32_bits(mc_addr); + private->header_addr_high = upper_32_bits(mc_addr); + private->header = toc_buf_ptr; + + adev->smu.smumgr_funcs = &iceland_smumgr_funcs; + + return 0; +} + +int iceland_smu_fini(struct amdgpu_device *adev) +{ + amdgpu_bo_unref(&adev->smu.toc_buf); + kfree(adev->smu.priv); + adev->smu.priv = NULL; + if (adev->firmware.fw_buf) + amdgpu_ucode_fini_bo(adev); + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_smumgr.h b/drivers/gpu/drm/amd/amdgpu/iceland_smumgr.h new file mode 100644 index 000000000000..1e0769e110fa --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/iceland_smumgr.h @@ -0,0 +1,41 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef ICELAND_SMUMGR_H +#define ICELAND_SMUMGR_H + +#include "ppsmc.h" + +extern int iceland_smu_init(struct amdgpu_device *adev); +extern int iceland_smu_fini(struct amdgpu_device *adev); +extern int iceland_smu_start(struct amdgpu_device *adev); + +struct iceland_smu_private_data +{ + uint8_t *header; + uint8_t *mec_image; + uint32_t header_addr_high; + uint32_t header_addr_low; +}; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c new file mode 100644 index 000000000000..a83029d548c1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -0,0 +1,1447 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ +#include +#include +#include "amdgpu.h" +#include "amdgpu_ucode.h" +#include "amdgpu_trace.h" +#include "vi.h" +#include "vid.h" + +#include "oss/oss_2_4_d.h" +#include "oss/oss_2_4_sh_mask.h" + +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" + +#include "gca/gfx_8_0_d.h" +#include "gca/gfx_8_0_sh_mask.h" + +#include "bif/bif_5_0_d.h" +#include "bif/bif_5_0_sh_mask.h" + +#include "iceland_sdma_pkt_open.h" + +static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); +static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); +static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); +static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); + +MODULE_FIRMWARE("radeon/topaz_sdma.bin"); +MODULE_FIRMWARE("radeon/topaz_sdma1.bin"); + +static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = +{ + SDMA0_REGISTER_OFFSET, + SDMA1_REGISTER_OFFSET +}; + +static const u32 golden_settings_iceland_a11[] = +{ + mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, + mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, +}; + +static const u32 iceland_mgcg_cgcg_init[] = +{ + mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, + mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 +}; + +/* + * sDMA - System DMA + * Starting with CIK, the GPU has new asynchronous + * DMA engines. These engines are used for compute + * and gfx. There are two DMA engines (SDMA0, SDMA1) + * and each one supports 1 ring buffer used for gfx + * and 2 queues used for compute. + * + * The programming model is very similar to the CP + * (ring buffer, IBs, etc.), but sDMA has it's own + * packet format that is different from the PM4 format + * used by the CP. sDMA supports copying data, writing + * embedded data, solid fills, and a number of other + * things. It also has support for tiling/detiling of + * buffers. + */ + +static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_TOPAZ: + amdgpu_program_register_sequence(adev, + iceland_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + golden_settings_iceland_a11, + (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + break; + default: + break; + } +} + +/** + * sdma_v2_4_init_microcode - load ucode images from disk + * + * @adev: amdgpu_device pointer + * + * Use the firmware interface to load the ucode images into + * the driver (not loaded into hw). + * Returns 0 on success, error on failure. + */ +static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) +{ + const char *chip_name; + char fw_name[30]; + int err, i; + struct amdgpu_firmware_info *info = NULL; + const struct common_firmware_header *header = NULL; + + DRM_DEBUG("\n"); + + switch (adev->asic_type) { + case CHIP_TOPAZ: + chip_name = "topaz"; + break; + default: BUG(); + } + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + if (i == 0) + snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); + else + snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name); + err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->sdma[i].fw); + if (err) + goto out; + + if (adev->firmware.smu_load) { + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; + info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; + info->fw = adev->sdma[i].fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + } + } + +out: + if (err) { + printk(KERN_ERR + "sdma_v2_4: Failed to load firmware \"%s\"\n", + fw_name); + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + release_firmware(adev->sdma[i].fw); + adev->sdma[i].fw = NULL; + } + } + return err; +} + +/** + * sdma_v2_4_ring_get_rptr - get the current read pointer + * + * @ring: amdgpu ring pointer + * + * Get the current rptr from the hardware (VI+). + */ +static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) +{ + u32 rptr; + + /* XXX check if swapping is necessary on BE */ + rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; + + return rptr; +} + +/** + * sdma_v2_4_ring_get_wptr - get the current write pointer + * + * @ring: amdgpu ring pointer + * + * Get the current wptr from the hardware (VI+). + */ +static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; + u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; + + return wptr; +} + +/** + * sdma_v2_4_ring_set_wptr - commit the write pointer + * + * @ring: amdgpu ring pointer + * + * Write the wptr back to the hardware (VI+). + */ +static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; + + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); +} + +static void sdma_v2_4_hdp_flush_ring_emit(struct amdgpu_ring *); + +/** + * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine + * + * @ring: amdgpu ring pointer + * @ib: IB object to schedule + * + * Schedule an IB in the DMA ring (VI). + */ +static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib) +{ + u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; + u32 next_rptr = ring->wptr + 5; + + if (ib->flush_hdp_writefifo) + next_rptr += 6; + + while ((next_rptr & 7) != 2) + next_rptr++; + + next_rptr += 6; + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); + amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); + amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); + amdgpu_ring_write(ring, next_rptr); + + if (ib->flush_hdp_writefifo) { + /* flush HDP */ + sdma_v2_4_hdp_flush_ring_emit(ring); + } + + /* IB packet must end on a 8 DW boundary */ + while ((ring->wptr & 7) != 2) + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP)); + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | + SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); + /* base must be 32 byte aligned */ + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, ib->length_dw); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 0); + +} + +/** + * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring + * + * @ring: amdgpu ring pointer + * + * Emit an hdp flush packet on the requested DMA ring. + */ +static void sdma_v2_4_hdp_flush_ring_emit(struct amdgpu_ring *ring) +{ + u32 ref_and_mask = 0; + + if (ring == &ring->adev->sdma[0].ring) + ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); + else + ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | + SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | + SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ + amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); + amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); + amdgpu_ring_write(ring, ref_and_mask); /* reference */ + amdgpu_ring_write(ring, ref_and_mask); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ +} + +/** + * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring + * + * @ring: amdgpu ring pointer + * @fence: amdgpu fence object + * + * Add a DMA fence packet to the ring to write + * the fence seq number and DMA trap packet to generate + * an interrupt if needed (VI). + */ +static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + bool write64bits) +{ + /* write the fence */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + + /* optionally write high bits as well */ + if (write64bits) { + addr += 4; + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(seq)); + } + + /* generate an interrupt */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); + amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); +} + +/** + * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring + * + * @ring: amdgpu_ring structure holding ring information + * @semaphore: amdgpu semaphore object + * @emit_wait: wait or signal semaphore + * + * Add a DMA semaphore packet to the ring wait on or signal + * other rings (VI). + */ +static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore, + bool emit_wait) +{ + u64 addr = semaphore->gpu_addr; + u32 sig = emit_wait ? 0 : 1; + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) | + SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig)); + amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8); + amdgpu_ring_write(ring, upper_32_bits(addr)); + + return true; +} + +/** + * sdma_v2_4_gfx_stop - stop the gfx async dma engines + * + * @adev: amdgpu_device pointer + * + * Stop the gfx async dma ring buffers (VI). + */ +static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *sdma0 = &adev->sdma[0].ring; + struct amdgpu_ring *sdma1 = &adev->sdma[1].ring; + u32 rb_cntl, ib_cntl; + int i; + + if ((adev->mman.buffer_funcs_ring == sdma0) || + (adev->mman.buffer_funcs_ring == sdma1)) + amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); + WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); + ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); + WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); + } + sdma0->ready = false; + sdma1->ready = false; +} + +/** + * sdma_v2_4_rlc_stop - stop the compute async dma engines + * + * @adev: amdgpu_device pointer + * + * Stop the compute async dma queues (VI). + */ +static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev) +{ + /* XXX todo */ +} + +/** + * sdma_v2_4_enable - stop the async dma engines + * + * @adev: amdgpu_device pointer + * @enable: enable/disable the DMA MEs. + * + * Halt or unhalt the async dma engines (VI). + */ +static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) +{ + u32 f32_cntl; + int i; + + if (enable == false) { + sdma_v2_4_gfx_stop(adev); + sdma_v2_4_rlc_stop(adev); + } + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); + if (enable) + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); + else + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); + WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); + } +} + +/** + * sdma_v2_4_gfx_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the gfx DMA ring buffers and enable them (VI). + * Returns 0 for success, error for failure. + */ +static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + u32 rb_cntl, ib_cntl; + u32 rb_bufsz; + u32 wb_offset; + int i, j, r; + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + ring = &adev->sdma[i].ring; + wb_offset = (ring->rptr_offs * 4); + + mutex_lock(&adev->srbm_mutex); + for (j = 0; j < 16; j++) { + vi_srbm_select(adev, 0, 0, 0, j); + /* SDMA GFX */ + WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); + WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); + } + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); + + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); +#ifdef __BIG_ENDIAN + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, + RPTR_WRITEBACK_SWAP_ENABLE, 1); +#endif + WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); + + /* set the wb address whether it's enabled or not */ + WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], + upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); + WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], + lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); + + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + + WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); + WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); + + ring->wptr = 0; + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); + + /* enable DMA RB */ + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); + WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); + + ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); +#ifdef __BIG_ENDIAN + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); +#endif + /* enable DMA IBs */ + WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); + + ring->ready = true; + + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + return r; + } + + if (adev->mman.buffer_funcs_ring == ring) + amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); + } + + return 0; +} + +/** + * sdma_v2_4_rlc_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the compute DMA queues and enable them (VI). + * Returns 0 for success, error for failure. + */ +static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev) +{ + /* XXX todo */ + return 0; +} + +/** + * sdma_v2_4_load_microcode - load the sDMA ME ucode + * + * @adev: amdgpu_device pointer + * + * Loads the sDMA0/1 ucode. + * Returns 0 for success, -EINVAL if the ucode is not available. + */ +static int sdma_v2_4_load_microcode(struct amdgpu_device *adev) +{ + const struct sdma_firmware_header_v1_0 *hdr; + const __le32 *fw_data; + u32 fw_size; + int i, j; + bool smc_loads_fw = false; /* XXX fix me */ + + if (!adev->sdma[0].fw || !adev->sdma[1].fw) + return -EINVAL; + + /* halt the MEs */ + sdma_v2_4_enable(adev, false); + + if (smc_loads_fw) { + /* XXX query SMC for fw load complete */ + } else { + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; + amdgpu_ucode_print_sdma_hdr(&hdr->header); + fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); + + fw_data = (const __le32 *) + (adev->sdma[i].fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); + for (j = 0; j < fw_size; j++) + WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); + WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version); + } + } + + return 0; +} + +/** + * sdma_v2_4_start - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the DMA engines and enable them (VI). + * Returns 0 for success, error for failure. + */ +static int sdma_v2_4_start(struct amdgpu_device *adev) +{ + int r; + + if (!adev->firmware.smu_load) { + r = sdma_v2_4_load_microcode(adev); + if (r) + return r; + } else { + r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, + AMDGPU_UCODE_ID_SDMA0); + if (r) + return -EINVAL; + r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, + AMDGPU_UCODE_ID_SDMA1); + if (r) + return -EINVAL; + } + + /* unhalt the MEs */ + sdma_v2_4_enable(adev, true); + + /* start the gfx rings and rlc compute queues */ + r = sdma_v2_4_gfx_resume(adev); + if (r) + return r; + r = sdma_v2_4_rlc_resume(adev); + if (r) + return r; + + return 0; +} + +/** + * sdma_v2_4_ring_test_ring - simple async dma engine test + * + * @ring: amdgpu_ring structure holding ring information + * + * Test the DMA engine by writing using it to write an + * value to memory. (VI). + * Returns 0 for success, error for failure. + */ +static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + unsigned i; + unsigned index; + int r; + u32 tmp; + u64 gpu_addr; + + r = amdgpu_wb_get(adev, &index); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); + return r; + } + + gpu_addr = adev->wb.gpu_addr + (index * 4); + tmp = 0xCAFEDEAD; + adev->wb.wb[index] = cpu_to_le32(tmp); + + r = amdgpu_ring_lock(ring, 5); + if (r) { + DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); + amdgpu_wb_free(adev, index); + return r; + } + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); + amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); + amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_unlock_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = le32_to_cpu(adev->wb.wb[index]); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", + ring->idx, tmp); + r = -EINVAL; + } + amdgpu_wb_free(adev, index); + + return r; +} + +/** + * sdma_v2_4_ring_test_ib - test an IB on the DMA engine + * + * @ring: amdgpu_ring structure holding ring information + * + * Test a simple IB in the DMA ring (VI). + * Returns 0 on success, error on failure. + */ +static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_ib ib; + unsigned i; + unsigned index; + int r; + u32 tmp = 0; + u64 gpu_addr; + + r = amdgpu_wb_get(adev, &index); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); + return r; + } + + gpu_addr = adev->wb.gpu_addr + (index * 4); + tmp = 0xCAFEDEAD; + adev->wb.wb[index] = cpu_to_le32(tmp); + + r = amdgpu_ib_get(ring, NULL, 256, &ib); + if (r) { + amdgpu_wb_free(adev, index); + DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); + return r; + } + + ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); + ib.ptr[1] = lower_32_bits(gpu_addr); + ib.ptr[2] = upper_32_bits(gpu_addr); + ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); + ib.ptr[4] = 0xDEADBEEF; + ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); + ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); + ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); + ib.length_dw = 8; + + r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); + if (r) { + amdgpu_ib_free(adev, &ib); + amdgpu_wb_free(adev, index); + DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); + return r; + } + r = amdgpu_fence_wait(ib.fence, false); + if (r) { + amdgpu_ib_free(adev, &ib); + amdgpu_wb_free(adev, index); + DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + return r; + } + for (i = 0; i < adev->usec_timeout; i++) { + tmp = le32_to_cpu(adev->wb.wb[index]); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < adev->usec_timeout) { + DRM_INFO("ib test on ring %d succeeded in %u usecs\n", + ib.fence->ring->idx, i); + } else { + DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); + r = -EINVAL; + } + amdgpu_ib_free(adev, &ib); + amdgpu_wb_free(adev, index); + return r; +} + +/** + * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @src: src addr to copy from + * @count: number of page entries to update + * + * Update PTEs by copying them from the GART using sDMA (CIK). + */ +static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib, + uint64_t pe, uint64_t src, + unsigned count) +{ + while (count) { + unsigned bytes = count * 8; + if (bytes > 0x1FFFF8) + bytes = 0x1FFFF8; + + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + ib->ptr[ib->length_dw++] = bytes; + ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ + ib->ptr[ib->length_dw++] = lower_32_bits(src); + ib->ptr[ib->length_dw++] = upper_32_bits(src); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + + pe += bytes; + src += bytes; + count -= bytes / 8; + } +} + +/** + * sdma_v2_4_vm_write_pte - update PTEs by writing them manually + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: access flags + * + * Update PTEs by writing them manually using sDMA (CIK). + */ +static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, + uint64_t pe, + uint64_t addr, unsigned count, + uint32_t incr, uint32_t flags) +{ + uint64_t value; + unsigned ndw; + + while (count) { + ndw = count * 2; + if (ndw > 0xFFFFE) + ndw = 0xFFFFE; + + /* for non-physically contiguous pages (system) */ + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + ib->ptr[ib->length_dw++] = pe; + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = ndw; + for (; ndw > 0; ndw -= 2, --count, pe += 8) { + if (flags & AMDGPU_PTE_SYSTEM) { + value = amdgpu_vm_map_gart(ib->ring->adev, addr); + value &= 0xFFFFFFFFFFFFF000ULL; + } else if (flags & AMDGPU_PTE_VALID) { + value = addr; + } else { + value = 0; + } + addr += incr; + value |= flags; + ib->ptr[ib->length_dw++] = value; + ib->ptr[ib->length_dw++] = upper_32_bits(value); + } + } +} + +/** + * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: access flags + * + * Update the page tables using sDMA (CIK). + */ +static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, + uint64_t pe, + uint64_t addr, unsigned count, + uint32_t incr, uint32_t flags) +{ + uint64_t value; + unsigned ndw; + + while (count) { + ndw = count; + if (ndw > 0x7FFFF) + ndw = 0x7FFFF; + + if (flags & AMDGPU_PTE_VALID) + value = addr; + else + value = 0; + + /* for physically contiguous pages (vram) */ + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); + ib->ptr[ib->length_dw++] = pe; /* dst addr */ + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = flags; /* mask */ + ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = value; /* value */ + ib->ptr[ib->length_dw++] = upper_32_bits(value); + ib->ptr[ib->length_dw++] = incr; /* increment size */ + ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = ndw; /* number of entries */ + + pe += ndw * 8; + addr += ndw * incr; + count -= ndw; + } +} + +/** + * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw + * + * @ib: indirect buffer to fill with padding + * + */ +static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib) +{ + while (ib->length_dw & 0x7) + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); +} + +/** + * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA + * + * @ring: amdgpu_ring pointer + * @vm: amdgpu_vm pointer + * + * Update the page table base and flush the VM TLB + * using sDMA (VI). + */ +static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr) +{ + u32 srbm_gfx_cntl = 0; + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + if (vm_id < 8) { + amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); + } else { + amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); + } + amdgpu_ring_write(ring, pd_addr >> 12); + + /* update SH_MEM_* regs */ + srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id); + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); + amdgpu_ring_write(ring, srbm_gfx_cntl); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSH_MEM_BASES); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSH_MEM_CONFIG); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE); + amdgpu_ring_write(ring, 1); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT); + amdgpu_ring_write(ring, 0); + + srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0); + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); + amdgpu_ring_write(ring, srbm_gfx_cntl); + + + /* flush TLB */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); + amdgpu_ring_write(ring, 1 << vm_id); + + /* wait for flush */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | + SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | + SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 0); /* reference */ + amdgpu_ring_write(ring, 0); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ +} + +static int sdma_v2_4_early_init(struct amdgpu_device *adev) +{ + sdma_v2_4_set_ring_funcs(adev); + sdma_v2_4_set_buffer_funcs(adev); + sdma_v2_4_set_vm_pte_funcs(adev); + sdma_v2_4_set_irq_funcs(adev); + + return 0; +} + +static int sdma_v2_4_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + /* SDMA trap event */ + r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); + if (r) + return r; + + /* SDMA Privileged inst */ + r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq); + if (r) + return r; + + /* SDMA Privileged inst */ + r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq); + if (r) + return r; + + r = sdma_v2_4_init_microcode(adev); + if (r) { + DRM_ERROR("Failed to load sdma firmware!\n"); + return r; + } + + ring = &adev->sdma[0].ring; + ring->ring_obj = NULL; + ring->use_doorbell = false; + + ring = &adev->sdma[1].ring; + ring->ring_obj = NULL; + ring->use_doorbell = false; + + ring = &adev->sdma[0].ring; + sprintf(ring->name, "sdma0"); + r = amdgpu_ring_init(adev, ring, 256 * 1024, + SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, + &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0, + AMDGPU_RING_TYPE_SDMA); + if (r) + return r; + + ring = &adev->sdma[1].ring; + sprintf(ring->name, "sdma1"); + r = amdgpu_ring_init(adev, ring, 256 * 1024, + SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, + &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1, + AMDGPU_RING_TYPE_SDMA); + if (r) + return r; + + return r; +} + +static int sdma_v2_4_sw_fini(struct amdgpu_device *adev) +{ + amdgpu_ring_fini(&adev->sdma[0].ring); + amdgpu_ring_fini(&adev->sdma[1].ring); + + return 0; +} + +static int sdma_v2_4_hw_init(struct amdgpu_device *adev) +{ + int r; + + sdma_v2_4_init_golden_registers(adev); + + r = sdma_v2_4_start(adev); + if (r) + return r; + + return r; +} + +static int sdma_v2_4_hw_fini(struct amdgpu_device *adev) +{ + sdma_v2_4_enable(adev, false); + + return 0; +} + +static int sdma_v2_4_suspend(struct amdgpu_device *adev) +{ + + return sdma_v2_4_hw_fini(adev); +} + +static int sdma_v2_4_resume(struct amdgpu_device *adev) +{ + + return sdma_v2_4_hw_init(adev); +} + +static bool sdma_v2_4_is_idle(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmSRBM_STATUS2); + + if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | + SRBM_STATUS2__SDMA1_BUSY_MASK)) + return false; + + return true; +} + +static int sdma_v2_4_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | + SRBM_STATUS2__SDMA1_BUSY_MASK); + + if (!tmp) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static void sdma_v2_4_print_status(struct amdgpu_device *adev) +{ + int i, j; + + dev_info(adev->dev, "VI SDMA registers\n"); + dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", + RREG32(mmSRBM_STATUS2)); + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", + i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); + mutex_lock(&adev->srbm_mutex); + for (j = 0; j < 16; j++) { + vi_srbm_select(adev, 0, 0, 0, j); + dev_info(adev->dev, " VM %d:\n", j); + dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", + i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); + } + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + } +} + +static int sdma_v2_4_soft_reset(struct amdgpu_device *adev) +{ + u32 srbm_soft_reset = 0; + u32 tmp = RREG32(mmSRBM_STATUS2); + + if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { + /* sdma0 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); + tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); + WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; + } + if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { + /* sdma1 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); + tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); + WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; + } + + if (srbm_soft_reset) { + sdma_v2_4_print_status(adev); + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + + sdma_v2_4_print_status(adev); + } + + return 0; +} + +static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 sdma_cntl; + + switch (type) { + case AMDGPU_SDMA_IRQ_TRAP0: + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); + sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); + WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); + sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); + WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); + break; + default: + break; + } + break; + case AMDGPU_SDMA_IRQ_TRAP1: + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); + sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); + WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); + sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); + WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); + break; + default: + break; + } + break; + default: + break; + } + return 0; +} + +static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + u8 instance_id, queue_id; + + instance_id = (entry->ring_id & 0x3) >> 0; + queue_id = (entry->ring_id & 0xc) >> 2; + DRM_DEBUG("IH: SDMA trap\n"); + switch (instance_id) { + case 0: + switch (queue_id) { + case 0: + amdgpu_fence_process(&adev->sdma[0].ring); + break; + case 1: + /* XXX compute */ + break; + case 2: + /* XXX compute */ + break; + } + break; + case 1: + switch (queue_id) { + case 0: + amdgpu_fence_process(&adev->sdma[1].ring); + break; + case 1: + /* XXX compute */ + break; + case 2: + /* XXX compute */ + break; + } + break; + } + return 0; +} + +static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal instruction in SDMA command stream\n"); + schedule_work(&adev->reset_work); + return 0; +} + +static int sdma_v2_4_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + /* XXX handled via the smc on VI */ + + return 0; +} + +static int sdma_v2_4_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs sdma_v2_4_ip_funcs = { + .early_init = sdma_v2_4_early_init, + .late_init = NULL, + .sw_init = sdma_v2_4_sw_init, + .sw_fini = sdma_v2_4_sw_fini, + .hw_init = sdma_v2_4_hw_init, + .hw_fini = sdma_v2_4_hw_fini, + .suspend = sdma_v2_4_suspend, + .resume = sdma_v2_4_resume, + .is_idle = sdma_v2_4_is_idle, + .wait_for_idle = sdma_v2_4_wait_for_idle, + .soft_reset = sdma_v2_4_soft_reset, + .print_status = sdma_v2_4_print_status, + .set_clockgating_state = sdma_v2_4_set_clockgating_state, + .set_powergating_state = sdma_v2_4_set_powergating_state, +}; + +/** + * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up + * + * @ring: amdgpu_ring structure holding ring information + * + * Check if the async DMA engine is locked up (VI). + * Returns true if the engine appears to be locked up, false if not. + */ +static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring *ring) +{ + + if (sdma_v2_4_is_idle(ring->adev)) { + amdgpu_ring_lockup_update(ring); + return false; + } + return amdgpu_ring_test_lockup(ring); +} + +static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { + .get_rptr = sdma_v2_4_ring_get_rptr, + .get_wptr = sdma_v2_4_ring_get_wptr, + .set_wptr = sdma_v2_4_ring_set_wptr, + .parse_cs = NULL, + .emit_ib = sdma_v2_4_ring_emit_ib, + .emit_fence = sdma_v2_4_ring_emit_fence, + .emit_semaphore = sdma_v2_4_ring_emit_semaphore, + .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, + .test_ring = sdma_v2_4_ring_test_ring, + .test_ib = sdma_v2_4_ring_test_ib, + .is_lockup = sdma_v2_4_ring_is_lockup, +}; + +static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) +{ + adev->sdma[0].ring.funcs = &sdma_v2_4_ring_funcs; + adev->sdma[1].ring.funcs = &sdma_v2_4_ring_funcs; +} + +static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = { + .set = sdma_v2_4_set_trap_irq_state, + .process = sdma_v2_4_process_trap_irq, +}; + +static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = { + .process = sdma_v2_4_process_illegal_inst_irq, +}; + +static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; + adev->sdma_trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; + adev->sdma_illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; +} + +/** + * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine + * + * @ring: amdgpu_ring structure holding ring information + * @src_offset: src GPU address + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * + * Copy GPU buffers using the DMA engine (VI). + * Used by the amdgpu ttm implementation to move pages if + * registered as the asic copy callback. + */ +static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ring *ring, + uint64_t src_offset, + uint64_t dst_offset, + uint32_t byte_count) +{ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)); + amdgpu_ring_write(ring, byte_count); + amdgpu_ring_write(ring, 0); /* src/dst endian swap */ + amdgpu_ring_write(ring, lower_32_bits(src_offset)); + amdgpu_ring_write(ring, upper_32_bits(src_offset)); + amdgpu_ring_write(ring, lower_32_bits(dst_offset)); + amdgpu_ring_write(ring, upper_32_bits(dst_offset)); +} + +/** + * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine + * + * @ring: amdgpu_ring structure holding ring information + * @src_data: value to write to buffer + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * + * Fill GPU buffers using the DMA engine (VI). + */ +static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ring *ring, + uint32_t src_data, + uint64_t dst_offset, + uint32_t byte_count) +{ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)); + amdgpu_ring_write(ring, lower_32_bits(dst_offset)); + amdgpu_ring_write(ring, upper_32_bits(dst_offset)); + amdgpu_ring_write(ring, src_data); + amdgpu_ring_write(ring, byte_count); +} + +static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { + .copy_max_bytes = 0x1fffff, + .copy_num_dw = 7, + .emit_copy_buffer = sdma_v2_4_emit_copy_buffer, + + .fill_max_bytes = 0x1fffff, + .fill_num_dw = 7, + .emit_fill_buffer = sdma_v2_4_emit_fill_buffer, +}; + +static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) +{ + if (adev->mman.buffer_funcs == NULL) { + adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; + adev->mman.buffer_funcs_ring = &adev->sdma[0].ring; + } +} + +static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { + .copy_pte = sdma_v2_4_vm_copy_pte, + .write_pte = sdma_v2_4_vm_write_pte, + .set_pte_pde = sdma_v2_4_vm_set_pte_pde, + .pad_ib = sdma_v2_4_vm_pad_ib, +}; + +static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) +{ + if (adev->vm_manager.vm_pte_funcs == NULL) { + adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; + adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring; + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h new file mode 100644 index 000000000000..6cdf8941c577 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __SDMA_V2_4_H__ +#define __SDMA_V2_4_H__ + +extern const struct amdgpu_ip_funcs sdma_v2_4_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c new file mode 100644 index 000000000000..dd547c7f6cbc --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -0,0 +1,1514 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ +#include +#include +#include "amdgpu.h" +#include "amdgpu_ucode.h" +#include "amdgpu_trace.h" +#include "vi.h" +#include "vid.h" + +#include "oss/oss_3_0_d.h" +#include "oss/oss_3_0_sh_mask.h" + +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" + +#include "gca/gfx_8_0_d.h" +#include "gca/gfx_8_0_sh_mask.h" + +#include "bif/bif_5_0_d.h" +#include "bif/bif_5_0_sh_mask.h" + +#include "tonga_sdma_pkt_open.h" + +static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); +static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); +static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); +static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); + +MODULE_FIRMWARE("radeon/tonga_sdma.bin"); +MODULE_FIRMWARE("radeon/tonga_sdma1.bin"); +MODULE_FIRMWARE("radeon/carrizo_sdma.bin"); +MODULE_FIRMWARE("radeon/carrizo_sdma1.bin"); + +static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = +{ + SDMA0_REGISTER_OFFSET, + SDMA1_REGISTER_OFFSET +}; + +static const u32 golden_settings_tonga_a11[] = +{ + mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, + mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, + mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, +}; + +static const u32 tonga_mgcg_cgcg_init[] = +{ + mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, + mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 +}; + +static const u32 cz_golden_settings_a11[] = +{ + mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, + mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, + mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, + mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, + mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, + mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, + mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, + mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, + mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, + mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, +}; + +static const u32 cz_mgcg_cgcg_init[] = +{ + mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, + mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 +}; + +/* + * sDMA - System DMA + * Starting with CIK, the GPU has new asynchronous + * DMA engines. These engines are used for compute + * and gfx. There are two DMA engines (SDMA0, SDMA1) + * and each one supports 1 ring buffer used for gfx + * and 2 queues used for compute. + * + * The programming model is very similar to the CP + * (ring buffer, IBs, etc.), but sDMA has it's own + * packet format that is different from the PM4 format + * used by the CP. sDMA supports copying data, writing + * embedded data, solid fills, and a number of other + * things. It also has support for tiling/detiling of + * buffers. + */ + +static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_TONGA: + amdgpu_program_register_sequence(adev, + tonga_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + golden_settings_tonga_a11, + (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + break; + case CHIP_CARRIZO: + amdgpu_program_register_sequence(adev, + cz_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + cz_golden_settings_a11, + (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + break; + default: + break; + } +} + +/** + * sdma_v3_0_init_microcode - load ucode images from disk + * + * @adev: amdgpu_device pointer + * + * Use the firmware interface to load the ucode images into + * the driver (not loaded into hw). + * Returns 0 on success, error on failure. + */ +static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) +{ + const char *chip_name; + char fw_name[30]; + int err, i; + struct amdgpu_firmware_info *info = NULL; + const struct common_firmware_header *header = NULL; + + DRM_DEBUG("\n"); + + switch (adev->asic_type) { + case CHIP_TONGA: + chip_name = "tonga"; + break; + case CHIP_CARRIZO: + chip_name = "carrizo"; + break; + default: BUG(); + } + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + if (i == 0) + snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); + else + snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name); + err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->sdma[i].fw); + if (err) + goto out; + + if (adev->firmware.smu_load) { + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; + info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; + info->fw = adev->sdma[i].fw; + header = (const struct common_firmware_header *)info->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + } + } +out: + if (err) { + printk(KERN_ERR + "sdma_v3_0: Failed to load firmware \"%s\"\n", + fw_name); + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + release_firmware(adev->sdma[i].fw); + adev->sdma[i].fw = NULL; + } + } + return err; +} + +/** + * sdma_v3_0_ring_get_rptr - get the current read pointer + * + * @ring: amdgpu ring pointer + * + * Get the current rptr from the hardware (VI+). + */ +static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) +{ + u32 rptr; + + /* XXX check if swapping is necessary on BE */ + rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; + + return rptr; +} + +/** + * sdma_v3_0_ring_get_wptr - get the current write pointer + * + * @ring: amdgpu ring pointer + * + * Get the current wptr from the hardware (VI+). + */ +static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u32 wptr; + + if (ring->use_doorbell) { + /* XXX check if swapping is necessary on BE */ + wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; + } else { + int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; + + wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; + } + + return wptr; +} + +/** + * sdma_v3_0_ring_set_wptr - commit the write pointer + * + * @ring: amdgpu ring pointer + * + * Write the wptr back to the hardware (VI+). + */ +static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) { + /* XXX check if swapping is necessary on BE */ + adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; + WDOORBELL32(ring->doorbell_index, ring->wptr << 2); + } else { + int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; + + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); + } +} + +static void sdma_v3_0_hdp_flush_ring_emit(struct amdgpu_ring *); + +/** + * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine + * + * @ring: amdgpu ring pointer + * @ib: IB object to schedule + * + * Schedule an IB in the DMA ring (VI). + */ +static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib) +{ + u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; + u32 next_rptr = ring->wptr + 5; + + if (ib->flush_hdp_writefifo) + next_rptr += 6; + + while ((next_rptr & 7) != 2) + next_rptr++; + next_rptr += 6; + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); + amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); + amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); + amdgpu_ring_write(ring, next_rptr); + + /* flush HDP */ + if (ib->flush_hdp_writefifo) { + sdma_v3_0_hdp_flush_ring_emit(ring); + } + + /* IB packet must end on a 8 DW boundary */ + while ((ring->wptr & 7) != 2) + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP)); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | + SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); + /* base must be 32 byte aligned */ + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, ib->length_dw); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 0); + +} + +/** + * sdma_v3_0_hdp_flush_ring_emit - emit an hdp flush on the DMA ring + * + * @ring: amdgpu ring pointer + * + * Emit an hdp flush packet on the requested DMA ring. + */ +static void sdma_v3_0_hdp_flush_ring_emit(struct amdgpu_ring *ring) +{ + u32 ref_and_mask = 0; + + if (ring == &ring->adev->sdma[0].ring) + ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); + else + ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | + SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | + SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ + amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); + amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); + amdgpu_ring_write(ring, ref_and_mask); /* reference */ + amdgpu_ring_write(ring, ref_and_mask); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ +} + +/** + * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring + * + * @ring: amdgpu ring pointer + * @fence: amdgpu fence object + * + * Add a DMA fence packet to the ring to write + * the fence seq number and DMA trap packet to generate + * an interrupt if needed (VI). + */ +static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + bool write64bits) +{ + /* write the fence */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + + /* optionally write high bits as well */ + if (write64bits) { + addr += 4; + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(seq)); + } + + /* generate an interrupt */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); + amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); +} + + +/** + * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring + * + * @ring: amdgpu_ring structure holding ring information + * @semaphore: amdgpu semaphore object + * @emit_wait: wait or signal semaphore + * + * Add a DMA semaphore packet to the ring wait on or signal + * other rings (VI). + */ +static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore, + bool emit_wait) +{ + u64 addr = semaphore->gpu_addr; + u32 sig = emit_wait ? 0 : 1; + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) | + SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig)); + amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8); + amdgpu_ring_write(ring, upper_32_bits(addr)); + + return true; +} + +/** + * sdma_v3_0_gfx_stop - stop the gfx async dma engines + * + * @adev: amdgpu_device pointer + * + * Stop the gfx async dma ring buffers (VI). + */ +static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *sdma0 = &adev->sdma[0].ring; + struct amdgpu_ring *sdma1 = &adev->sdma[1].ring; + u32 rb_cntl, ib_cntl; + int i; + + if ((adev->mman.buffer_funcs_ring == sdma0) || + (adev->mman.buffer_funcs_ring == sdma1)) + amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); + WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); + ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); + WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); + } + sdma0->ready = false; + sdma1->ready = false; +} + +/** + * sdma_v3_0_rlc_stop - stop the compute async dma engines + * + * @adev: amdgpu_device pointer + * + * Stop the compute async dma queues (VI). + */ +static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) +{ + /* XXX todo */ +} + +/** + * sdma_v3_0_enable - stop the async dma engines + * + * @adev: amdgpu_device pointer + * @enable: enable/disable the DMA MEs. + * + * Halt or unhalt the async dma engines (VI). + */ +static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) +{ + u32 f32_cntl; + int i; + + if (enable == false) { + sdma_v3_0_gfx_stop(adev); + sdma_v3_0_rlc_stop(adev); + } + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); + if (enable) + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); + else + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); + WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); + } +} + +/** + * sdma_v3_0_gfx_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the gfx DMA ring buffers and enable them (VI). + * Returns 0 for success, error for failure. + */ +static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + u32 rb_cntl, ib_cntl; + u32 rb_bufsz; + u32 wb_offset; + u32 doorbell; + int i, j, r; + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + ring = &adev->sdma[i].ring; + wb_offset = (ring->rptr_offs * 4); + + mutex_lock(&adev->srbm_mutex); + for (j = 0; j < 16; j++) { + vi_srbm_select(adev, 0, 0, 0, j); + /* SDMA GFX */ + WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); + WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); + } + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + + WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); + + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); +#ifdef __BIG_ENDIAN + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, + RPTR_WRITEBACK_SWAP_ENABLE, 1); +#endif + WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); + + /* set the wb address whether it's enabled or not */ + WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], + upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); + WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], + lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); + + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + + WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); + WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); + + ring->wptr = 0; + WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); + + doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); + + if (ring->use_doorbell) { + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, + OFFSET, ring->doorbell_index); + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); + } else { + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); + } + WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); + + /* enable DMA RB */ + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); + WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); + + ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); +#ifdef __BIG_ENDIAN + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); +#endif + /* enable DMA IBs */ + WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); + + ring->ready = true; + + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + return r; + } + + if (adev->mman.buffer_funcs_ring == ring) + amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); + } + + return 0; +} + +/** + * sdma_v3_0_rlc_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the compute DMA queues and enable them (VI). + * Returns 0 for success, error for failure. + */ +static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) +{ + /* XXX todo */ + return 0; +} + +/** + * sdma_v3_0_load_microcode - load the sDMA ME ucode + * + * @adev: amdgpu_device pointer + * + * Loads the sDMA0/1 ucode. + * Returns 0 for success, -EINVAL if the ucode is not available. + */ +static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) +{ + const struct sdma_firmware_header_v1_0 *hdr; + const __le32 *fw_data; + u32 fw_size; + int i, j; + + if (!adev->sdma[0].fw || !adev->sdma[1].fw) + return -EINVAL; + + /* halt the MEs */ + sdma_v3_0_enable(adev, false); + + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; + amdgpu_ucode_print_sdma_hdr(&hdr->header); + fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); + + fw_data = (const __le32 *) + (adev->sdma[i].fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); + for (j = 0; j < fw_size; j++) + WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); + WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version); + } + + return 0; +} + +/** + * sdma_v3_0_start - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the DMA engines and enable them (VI). + * Returns 0 for success, error for failure. + */ +static int sdma_v3_0_start(struct amdgpu_device *adev) +{ + int r; + + if (!adev->firmware.smu_load) { + r = sdma_v3_0_load_microcode(adev); + if (r) + return r; + } else { + r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, + AMDGPU_UCODE_ID_SDMA0); + if (r) + return -EINVAL; + r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, + AMDGPU_UCODE_ID_SDMA1); + if (r) + return -EINVAL; + } + + /* unhalt the MEs */ + sdma_v3_0_enable(adev, true); + + /* start the gfx rings and rlc compute queues */ + r = sdma_v3_0_gfx_resume(adev); + if (r) + return r; + r = sdma_v3_0_rlc_resume(adev); + if (r) + return r; + + return 0; +} + +/** + * sdma_v3_0_ring_test_ring - simple async dma engine test + * + * @ring: amdgpu_ring structure holding ring information + * + * Test the DMA engine by writing using it to write an + * value to memory. (VI). + * Returns 0 for success, error for failure. + */ +static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + unsigned i; + unsigned index; + int r; + u32 tmp; + u64 gpu_addr; + + r = amdgpu_wb_get(adev, &index); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); + return r; + } + + gpu_addr = adev->wb.gpu_addr + (index * 4); + tmp = 0xCAFEDEAD; + adev->wb.wb[index] = cpu_to_le32(tmp); + + r = amdgpu_ring_lock(ring, 5); + if (r) { + DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); + amdgpu_wb_free(adev, index); + return r; + } + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); + amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); + amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_unlock_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = le32_to_cpu(adev->wb.wb[index]); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", + ring->idx, tmp); + r = -EINVAL; + } + amdgpu_wb_free(adev, index); + + return r; +} + +/** + * sdma_v3_0_ring_test_ib - test an IB on the DMA engine + * + * @ring: amdgpu_ring structure holding ring information + * + * Test a simple IB in the DMA ring (VI). + * Returns 0 on success, error on failure. + */ +static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_ib ib; + unsigned i; + unsigned index; + int r; + u32 tmp = 0; + u64 gpu_addr; + + r = amdgpu_wb_get(adev, &index); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); + return r; + } + + gpu_addr = adev->wb.gpu_addr + (index * 4); + tmp = 0xCAFEDEAD; + adev->wb.wb[index] = cpu_to_le32(tmp); + + r = amdgpu_ib_get(ring, NULL, 256, &ib); + if (r) { + amdgpu_wb_free(adev, index); + DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); + return r; + } + + ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); + ib.ptr[1] = lower_32_bits(gpu_addr); + ib.ptr[2] = upper_32_bits(gpu_addr); + ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); + ib.ptr[4] = 0xDEADBEEF; + ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); + ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); + ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); + ib.length_dw = 8; + + r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); + if (r) { + amdgpu_ib_free(adev, &ib); + amdgpu_wb_free(adev, index); + DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); + return r; + } + r = amdgpu_fence_wait(ib.fence, false); + if (r) { + amdgpu_ib_free(adev, &ib); + amdgpu_wb_free(adev, index); + DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + return r; + } + for (i = 0; i < adev->usec_timeout; i++) { + tmp = le32_to_cpu(adev->wb.wb[index]); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + if (i < adev->usec_timeout) { + DRM_INFO("ib test on ring %d succeeded in %u usecs\n", + ib.fence->ring->idx, i); + } else { + DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); + r = -EINVAL; + } + amdgpu_ib_free(adev, &ib); + amdgpu_wb_free(adev, index); + return r; +} + +/** + * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @src: src addr to copy from + * @count: number of page entries to update + * + * Update PTEs by copying them from the GART using sDMA (CIK). + */ +static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, + uint64_t pe, uint64_t src, + unsigned count) +{ + while (count) { + unsigned bytes = count * 8; + if (bytes > 0x1FFFF8) + bytes = 0x1FFFF8; + + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + ib->ptr[ib->length_dw++] = bytes; + ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ + ib->ptr[ib->length_dw++] = lower_32_bits(src); + ib->ptr[ib->length_dw++] = upper_32_bits(src); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + + pe += bytes; + src += bytes; + count -= bytes / 8; + } +} + +/** + * sdma_v3_0_vm_write_pte - update PTEs by writing them manually + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: access flags + * + * Update PTEs by writing them manually using sDMA (CIK). + */ +static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, + uint64_t pe, + uint64_t addr, unsigned count, + uint32_t incr, uint32_t flags) +{ + uint64_t value; + unsigned ndw; + + while (count) { + ndw = count * 2; + if (ndw > 0xFFFFE) + ndw = 0xFFFFE; + + /* for non-physically contiguous pages (system) */ + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + ib->ptr[ib->length_dw++] = pe; + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = ndw; + for (; ndw > 0; ndw -= 2, --count, pe += 8) { + if (flags & AMDGPU_PTE_SYSTEM) { + value = amdgpu_vm_map_gart(ib->ring->adev, addr); + value &= 0xFFFFFFFFFFFFF000ULL; + } else if (flags & AMDGPU_PTE_VALID) { + value = addr; + } else { + value = 0; + } + addr += incr; + value |= flags; + ib->ptr[ib->length_dw++] = value; + ib->ptr[ib->length_dw++] = upper_32_bits(value); + } + } +} + +/** + * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: access flags + * + * Update the page tables using sDMA (CIK). + */ +static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, + uint64_t pe, + uint64_t addr, unsigned count, + uint32_t incr, uint32_t flags) +{ + uint64_t value; + unsigned ndw; + + while (count) { + ndw = count; + if (ndw > 0x7FFFF) + ndw = 0x7FFFF; + + if (flags & AMDGPU_PTE_VALID) + value = addr; + else + value = 0; + + /* for physically contiguous pages (vram) */ + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); + ib->ptr[ib->length_dw++] = pe; /* dst addr */ + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = flags; /* mask */ + ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = value; /* value */ + ib->ptr[ib->length_dw++] = upper_32_bits(value); + ib->ptr[ib->length_dw++] = incr; /* increment size */ + ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = ndw; /* number of entries */ + + pe += ndw * 8; + addr += ndw * incr; + count -= ndw; + } +} + +/** + * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw + * + * @ib: indirect buffer to fill with padding + * + */ +static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib) +{ + while (ib->length_dw & 0x7) + ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); +} + +/** + * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA + * + * @ring: amdgpu_ring pointer + * @vm: amdgpu_vm pointer + * + * Update the page table base and flush the VM TLB + * using sDMA (VI). + */ +static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vm_id, uint64_t pd_addr) +{ + u32 srbm_gfx_cntl = 0; + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + if (vm_id < 8) { + amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); + } else { + amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); + } + amdgpu_ring_write(ring, pd_addr >> 12); + + /* update SH_MEM_* regs */ + srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id); + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); + amdgpu_ring_write(ring, srbm_gfx_cntl); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSH_MEM_BASES); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSH_MEM_CONFIG); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE); + amdgpu_ring_write(ring, 1); + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT); + amdgpu_ring_write(ring, 0); + + srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0); + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); + amdgpu_ring_write(ring, srbm_gfx_cntl); + + + /* flush TLB */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); + amdgpu_ring_write(ring, 1 << vm_id); + + /* wait for flush */ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | + SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | + SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ + amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 0); /* reference */ + amdgpu_ring_write(ring, 0); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ +} + +static int sdma_v3_0_early_init(struct amdgpu_device *adev) +{ + sdma_v3_0_set_ring_funcs(adev); + sdma_v3_0_set_buffer_funcs(adev); + sdma_v3_0_set_vm_pte_funcs(adev); + sdma_v3_0_set_irq_funcs(adev); + + return 0; +} + +static int sdma_v3_0_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + /* SDMA trap event */ + r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); + if (r) + return r; + + /* SDMA Privileged inst */ + r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq); + if (r) + return r; + + /* SDMA Privileged inst */ + r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq); + if (r) + return r; + + r = sdma_v3_0_init_microcode(adev); + if (r) { + DRM_ERROR("Failed to load sdma firmware!\n"); + return r; + } + + ring = &adev->sdma[0].ring; + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0; + + ring = &adev->sdma[1].ring; + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1; + + ring = &adev->sdma[0].ring; + sprintf(ring->name, "sdma0"); + r = amdgpu_ring_init(adev, ring, 256 * 1024, + SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, + &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0, + AMDGPU_RING_TYPE_SDMA); + if (r) + return r; + + ring = &adev->sdma[1].ring; + sprintf(ring->name, "sdma1"); + r = amdgpu_ring_init(adev, ring, 256 * 1024, + SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, + &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1, + AMDGPU_RING_TYPE_SDMA); + if (r) + return r; + + return r; +} + +static int sdma_v3_0_sw_fini(struct amdgpu_device *adev) +{ + amdgpu_ring_fini(&adev->sdma[0].ring); + amdgpu_ring_fini(&adev->sdma[1].ring); + + return 0; +} + +static int sdma_v3_0_hw_init(struct amdgpu_device *adev) +{ + int r; + + sdma_v3_0_init_golden_registers(adev); + + r = sdma_v3_0_start(adev); + if (r) + return r; + + return r; +} + +static int sdma_v3_0_hw_fini(struct amdgpu_device *adev) +{ + sdma_v3_0_enable(adev, false); + + return 0; +} + +static int sdma_v3_0_suspend(struct amdgpu_device *adev) +{ + + return sdma_v3_0_hw_fini(adev); +} + +static int sdma_v3_0_resume(struct amdgpu_device *adev) +{ + + return sdma_v3_0_hw_init(adev); +} + +static bool sdma_v3_0_is_idle(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmSRBM_STATUS2); + + if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | + SRBM_STATUS2__SDMA1_BUSY_MASK)) + return false; + + return true; +} + +static int sdma_v3_0_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | + SRBM_STATUS2__SDMA1_BUSY_MASK); + + if (!tmp) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static void sdma_v3_0_print_status(struct amdgpu_device *adev) +{ + int i, j; + + dev_info(adev->dev, "VI SDMA registers\n"); + dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", + RREG32(mmSRBM_STATUS2)); + for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", + i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", + i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n", + i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i])); + mutex_lock(&adev->srbm_mutex); + for (j = 0; j < 16; j++) { + vi_srbm_select(adev, 0, 0, 0, j); + dev_info(adev->dev, " VM %d:\n", j); + dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", + i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); + dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", + i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); + } + vi_srbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + } +} + +static int sdma_v3_0_soft_reset(struct amdgpu_device *adev) +{ + u32 srbm_soft_reset = 0; + u32 tmp = RREG32(mmSRBM_STATUS2); + + if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { + /* sdma0 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); + tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); + WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; + } + if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { + /* sdma1 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); + tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); + WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); + srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; + } + + if (srbm_soft_reset) { + sdma_v3_0_print_status(adev); + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + + sdma_v3_0_print_status(adev); + } + + return 0; +} + +static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 sdma_cntl; + + switch (type) { + case AMDGPU_SDMA_IRQ_TRAP0: + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); + sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); + WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); + sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); + WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); + break; + default: + break; + } + break; + case AMDGPU_SDMA_IRQ_TRAP1: + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); + sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); + WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); + break; + case AMDGPU_IRQ_STATE_ENABLE: + sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); + sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); + WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); + break; + default: + break; + } + break; + default: + break; + } + return 0; +} + +static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + u8 instance_id, queue_id; + + instance_id = (entry->ring_id & 0x3) >> 0; + queue_id = (entry->ring_id & 0xc) >> 2; + DRM_DEBUG("IH: SDMA trap\n"); + switch (instance_id) { + case 0: + switch (queue_id) { + case 0: + amdgpu_fence_process(&adev->sdma[0].ring); + break; + case 1: + /* XXX compute */ + break; + case 2: + /* XXX compute */ + break; + } + break; + case 1: + switch (queue_id) { + case 0: + amdgpu_fence_process(&adev->sdma[1].ring); + break; + case 1: + /* XXX compute */ + break; + case 2: + /* XXX compute */ + break; + } + break; + } + return 0; +} + +static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal instruction in SDMA command stream\n"); + schedule_work(&adev->reset_work); + return 0; +} + +static int sdma_v3_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + /* XXX handled via the smc on VI */ + + return 0; +} + +static int sdma_v3_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs sdma_v3_0_ip_funcs = { + .early_init = sdma_v3_0_early_init, + .late_init = NULL, + .sw_init = sdma_v3_0_sw_init, + .sw_fini = sdma_v3_0_sw_fini, + .hw_init = sdma_v3_0_hw_init, + .hw_fini = sdma_v3_0_hw_fini, + .suspend = sdma_v3_0_suspend, + .resume = sdma_v3_0_resume, + .is_idle = sdma_v3_0_is_idle, + .wait_for_idle = sdma_v3_0_wait_for_idle, + .soft_reset = sdma_v3_0_soft_reset, + .print_status = sdma_v3_0_print_status, + .set_clockgating_state = sdma_v3_0_set_clockgating_state, + .set_powergating_state = sdma_v3_0_set_powergating_state, +}; + +/** + * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up + * + * @ring: amdgpu_ring structure holding ring information + * + * Check if the async DMA engine is locked up (VI). + * Returns true if the engine appears to be locked up, false if not. + */ +static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring) +{ + + if (sdma_v3_0_is_idle(ring->adev)) { + amdgpu_ring_lockup_update(ring); + return false; + } + return amdgpu_ring_test_lockup(ring); +} + +static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { + .get_rptr = sdma_v3_0_ring_get_rptr, + .get_wptr = sdma_v3_0_ring_get_wptr, + .set_wptr = sdma_v3_0_ring_set_wptr, + .parse_cs = NULL, + .emit_ib = sdma_v3_0_ring_emit_ib, + .emit_fence = sdma_v3_0_ring_emit_fence, + .emit_semaphore = sdma_v3_0_ring_emit_semaphore, + .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, + .test_ring = sdma_v3_0_ring_test_ring, + .test_ib = sdma_v3_0_ring_test_ib, + .is_lockup = sdma_v3_0_ring_is_lockup, +}; + +static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) +{ + adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs; + adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs; +} + +static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { + .set = sdma_v3_0_set_trap_irq_state, + .process = sdma_v3_0_process_trap_irq, +}; + +static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { + .process = sdma_v3_0_process_illegal_inst_irq, +}; + +static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; + adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; + adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; +} + +/** + * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine + * + * @ring: amdgpu_ring structure holding ring information + * @src_offset: src GPU address + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * + * Copy GPU buffers using the DMA engine (VI). + * Used by the amdgpu ttm implementation to move pages if + * registered as the asic copy callback. + */ +static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ring *ring, + uint64_t src_offset, + uint64_t dst_offset, + uint32_t byte_count) +{ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | + SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)); + amdgpu_ring_write(ring, byte_count); + amdgpu_ring_write(ring, 0); /* src/dst endian swap */ + amdgpu_ring_write(ring, lower_32_bits(src_offset)); + amdgpu_ring_write(ring, upper_32_bits(src_offset)); + amdgpu_ring_write(ring, lower_32_bits(dst_offset)); + amdgpu_ring_write(ring, upper_32_bits(dst_offset)); +} + +/** + * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine + * + * @ring: amdgpu_ring structure holding ring information + * @src_data: value to write to buffer + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * + * Fill GPU buffers using the DMA engine (VI). + */ +static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ring *ring, + uint32_t src_data, + uint64_t dst_offset, + uint32_t byte_count) +{ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)); + amdgpu_ring_write(ring, lower_32_bits(dst_offset)); + amdgpu_ring_write(ring, upper_32_bits(dst_offset)); + amdgpu_ring_write(ring, src_data); + amdgpu_ring_write(ring, byte_count); +} + +static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { + .copy_max_bytes = 0x1fffff, + .copy_num_dw = 7, + .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, + + .fill_max_bytes = 0x1fffff, + .fill_num_dw = 5, + .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, +}; + +static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) +{ + if (adev->mman.buffer_funcs == NULL) { + adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; + adev->mman.buffer_funcs_ring = &adev->sdma[0].ring; + } +} + +static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { + .copy_pte = sdma_v3_0_vm_copy_pte, + .write_pte = sdma_v3_0_vm_write_pte, + .set_pte_pde = sdma_v3_0_vm_set_pte_pde, + .pad_ib = sdma_v3_0_vm_pad_ib, +}; + +static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) +{ + if (adev->vm_manager.vm_pte_funcs == NULL) { + adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; + adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring; + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h new file mode 100644 index 000000000000..85bf2ac59252 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __SDMA_V3_0_H__ +#define __SDMA_V3_0_H__ + +extern const struct amdgpu_ip_funcs sdma_v3_0_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/smu8.h b/drivers/gpu/drm/amd/amdgpu/smu8.h new file mode 100644 index 000000000000..d758d07b6a31 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smu8.h @@ -0,0 +1,72 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU8_H +#define SMU8_H + +#pragma pack(push, 1) + +#define ENABLE_DEBUG_FEATURES + +struct SMU8_Firmware_Header { + uint32_t Version; + uint32_t ImageSize; + uint32_t CodeSize; + uint32_t HeaderSize; + uint32_t EntryPoint; + uint32_t Rtos; + uint32_t UcodeLoadStatus; + uint32_t DpmTable; + uint32_t FanTable; + uint32_t PmFuseTable; + uint32_t Globals; + uint32_t Reserved[20]; + uint32_t Signature; +}; + +struct SMU8_MultimediaPowerLogData { + uint32_t avgTotalPower; + uint32_t avgGpuPower; + uint32_t avgUvdPower; + uint32_t avgVcePower; + + uint32_t avgSclk; + uint32_t avgDclk; + uint32_t avgVclk; + uint32_t avgEclk; + + uint32_t startTimeHi; + uint32_t startTimeLo; + + uint32_t endTimeHi; + uint32_t endTimeLo; +}; + +#define SMU8_FIRMWARE_HEADER_LOCATION 0x1FF80 +#define SMU8_UNBCSR_START_ADDR 0xC0100000 + +#define SMN_MP1_SRAM_START_ADDR 0x10000000 + +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/smu8_fusion.h b/drivers/gpu/drm/amd/amdgpu/smu8_fusion.h new file mode 100644 index 000000000000..5c9cc3c0bbfa --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smu8_fusion.h @@ -0,0 +1,127 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU8_FUSION_H +#define SMU8_FUSION_H + +#include "smu8.h" + +#pragma pack(push, 1) + +#define SMU8_MAX_CUS 2 +#define SMU8_PSMS_PER_CU 4 +#define SMU8_CACS_PER_CU 4 + +struct SMU8_GfxCuPgScoreboard { + uint8_t Enabled; + uint8_t spare[3]; +}; + +struct SMU8_Port80MonitorTable { + uint32_t MmioAddress; + uint32_t MemoryBaseHi; + uint32_t MemoryBaseLo; + uint16_t MemoryBufferSize; + uint16_t MemoryPosition; + uint16_t PollingInterval; + uint8_t EnableCsrShadow; + uint8_t EnableDramShadow; +}; + +/* Clock Table Definitions */ +#define NUM_SCLK_LEVELS 8 +#define NUM_LCLK_LEVELS 8 +#define NUM_UVD_LEVELS 8 +#define NUM_ECLK_LEVELS 8 +#define NUM_ACLK_LEVELS 8 + +struct SMU8_Fusion_ClkLevel { + uint8_t GnbVid; + uint8_t GfxVid; + uint8_t DfsDid; + uint8_t DeepSleepDid; + uint32_t DfsBypass; + uint32_t Frequency; +}; + +struct SMU8_Fusion_SclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_SCLK_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + /* SMU8_Fusion_ClkLevel PwrOffLevel; */ + uint32_t SclkValidMask; + uint32_t MaxSclkIndex; +}; + +struct SMU8_Fusion_LclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_LCLK_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + /* SMU8_Fusion_ClkLevel PwrOffLevel; */ + uint32_t LclkValidMask; + uint32_t MaxLclkIndex; +}; + +struct SMU8_Fusion_EclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ECLK_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + struct SMU8_Fusion_ClkLevel PwrOffLevel; + uint32_t EclkValidMask; + uint32_t MaxEclkIndex; +}; + +struct SMU8_Fusion_VclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + struct SMU8_Fusion_ClkLevel PwrOffLevel; + uint32_t VclkValidMask; + uint32_t MaxVclkIndex; +}; + +struct SMU8_Fusion_DclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + struct SMU8_Fusion_ClkLevel PwrOffLevel; + uint32_t DclkValidMask; + uint32_t MaxDclkIndex; +}; + +struct SMU8_Fusion_AclkBreakdownTable { + struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ACLK_LEVELS]; + struct SMU8_Fusion_ClkLevel DpmOffLevel; + struct SMU8_Fusion_ClkLevel PwrOffLevel; + uint32_t AclkValidMask; + uint32_t MaxAclkIndex; +}; + + +struct SMU8_Fusion_ClkTable { + struct SMU8_Fusion_SclkBreakdownTable SclkBreakdownTable; + struct SMU8_Fusion_LclkBreakdownTable LclkBreakdownTable; + struct SMU8_Fusion_EclkBreakdownTable EclkBreakdownTable; + struct SMU8_Fusion_VclkBreakdownTable VclkBreakdownTable; + struct SMU8_Fusion_DclkBreakdownTable DclkBreakdownTable; + struct SMU8_Fusion_AclkBreakdownTable AclkBreakdownTable; +}; + +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h new file mode 100644 index 000000000000..f8ba071f39c8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_cz.h @@ -0,0 +1,147 @@ +// CZ Ucode Loading Definitions +#ifndef SMU_UCODE_XFER_CZ_H +#define SMU_UCODE_XFER_CZ_H + +#define NUM_JOBLIST_ENTRIES 32 + +#define TASK_TYPE_NO_ACTION 0 +#define TASK_TYPE_UCODE_LOAD 1 +#define TASK_TYPE_UCODE_SAVE 2 +#define TASK_TYPE_REG_LOAD 3 +#define TASK_TYPE_REG_SAVE 4 +#define TASK_TYPE_INITIALIZE 5 + +#define TASK_ARG_REG_SMCIND 0 +#define TASK_ARG_REG_MMIO 1 +#define TASK_ARG_REG_FCH 2 +#define TASK_ARG_REG_UNB 3 + +#define TASK_ARG_INIT_MM_PWR_LOG 0 +#define TASK_ARG_INIT_CLK_TABLE 1 + +#define JOB_GFX_SAVE 0 +#define JOB_GFX_RESTORE 1 +#define JOB_FCH_SAVE 2 +#define JOB_FCH_RESTORE 3 +#define JOB_UNB_SAVE 4 +#define JOB_UNB_RESTORE 5 +#define JOB_GMC_SAVE 6 +#define JOB_GMC_RESTORE 7 +#define JOB_GNB_SAVE 8 +#define JOB_GNB_RESTORE 9 + +#define IGNORE_JOB 0xff +#define END_OF_TASK_LIST (uint16_t)0xffff + +// Size of DRAM regions (in bytes) requested by SMU: +#define SMU_DRAM_REQ_MM_PWR_LOG 48 + +#define UCODE_ID_SDMA0 0 +#define UCODE_ID_SDMA1 1 +#define UCODE_ID_CP_CE 2 +#define UCODE_ID_CP_PFP 3 +#define UCODE_ID_CP_ME 4 +#define UCODE_ID_CP_MEC_JT1 5 +#define UCODE_ID_CP_MEC_JT2 6 +#define UCODE_ID_GMCON_RENG 7 +#define UCODE_ID_RLC_G 8 +#define UCODE_ID_RLC_SCRATCH 9 +#define UCODE_ID_RLC_SRM_ARAM 10 +#define UCODE_ID_RLC_SRM_DRAM 11 +#define UCODE_ID_DMCU_ERAM 12 +#define UCODE_ID_DMCU_IRAM 13 + +#define UCODE_ID_SDMA0_MASK 0x00000001 +#define UCODE_ID_SDMA1_MASK 0x00000002 +#define UCODE_ID_CP_CE_MASK 0x00000004 +#define UCODE_ID_CP_PFP_MASK 0x00000008 +#define UCODE_ID_CP_ME_MASK 0x00000010 +#define UCODE_ID_CP_MEC_JT1_MASK 0x00000020 +#define UCODE_ID_CP_MEC_JT2_MASK 0x00000040 +#define UCODE_ID_GMCON_RENG_MASK 0x00000080 +#define UCODE_ID_RLC_G_MASK 0x00000100 +#define UCODE_ID_RLC_SCRATCH_MASK 0x00000200 +#define UCODE_ID_RLC_SRM_ARAM_MASK 0x00000400 +#define UCODE_ID_RLC_SRM_DRAM_MASK 0x00000800 +#define UCODE_ID_DMCU_ERAM_MASK 0x00001000 +#define UCODE_ID_DMCU_IRAM_MASK 0x00002000 + +#define UCODE_ID_SDMA0_SIZE_BYTE 10368 +#define UCODE_ID_SDMA1_SIZE_BYTE 10368 +#define UCODE_ID_CP_CE_SIZE_BYTE 8576 +#define UCODE_ID_CP_PFP_SIZE_BYTE 16768 +#define UCODE_ID_CP_ME_SIZE_BYTE 16768 +#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE 384 +#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE 384 +#define UCODE_ID_GMCON_RENG_SIZE_BYTE 4096 +#define UCODE_ID_RLC_G_SIZE_BYTE 2048 +#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE 132 +#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE 8192 +#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE 4096 +#define UCODE_ID_DMCU_ERAM_SIZE_BYTE 24576 +#define UCODE_ID_DMCU_IRAM_SIZE_BYTE 1024 + +#define NUM_UCODES 14 + +typedef struct { + uint32_t high; + uint32_t low; +} data_64_t; + +struct SMU_Task { + uint8_t type; + uint8_t arg; + uint16_t next; + data_64_t addr; + uint32_t size_bytes; +}; +typedef struct SMU_Task SMU_Task; + +struct TOC { + uint8_t JobList[NUM_JOBLIST_ENTRIES]; + SMU_Task tasks[1]; +}; + +// META DATA COMMAND Definitions +#define METADATA_CMD_MODE0 0x00000103 +#define METADATA_CMD_MODE1 0x00000113 +#define METADATA_CMD_MODE2 0x00000123 +#define METADATA_CMD_MODE3 0x00000133 +#define METADATA_CMD_DELAY 0x00000203 +#define METADATA_CMD_CHNG_REGSPACE 0x00000303 +#define METADATA_PERFORM_ON_SAVE 0x00001000 +#define METADATA_PERFORM_ON_LOAD 0x00002000 +#define METADATA_CMD_ARG_MASK 0xFFFF0000 +#define METADATA_CMD_ARG_SHIFT 16 + +// Simple register addr/data fields +struct SMU_MetaData_Mode0 { + uint32_t register_address; + uint32_t register_data; +}; +typedef struct SMU_MetaData_Mode0 SMU_MetaData_Mode0; + +// Register addr/data with mask +struct SMU_MetaData_Mode1 { + uint32_t register_address; + uint32_t register_mask; + uint32_t register_data; +}; +typedef struct SMU_MetaData_Mode1 SMU_MetaData_Mode1; + +struct SMU_MetaData_Mode2 { + uint32_t register_address; + uint32_t register_mask; + uint32_t target_value; +}; +typedef struct SMU_MetaData_Mode2 SMU_MetaData_Mode2; + +// Always write data (even on a save operation) +struct SMU_MetaData_Mode3 { + uint32_t register_address; + uint32_t register_mask; + uint32_t register_data; +}; +typedef struct SMU_MetaData_Mode3 SMU_MetaData_Mode3; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h new file mode 100644 index 000000000000..c24a81eebc7c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h @@ -0,0 +1,100 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU_UCODE_XFER_VI_H +#define SMU_UCODE_XFER_VI_H + +#define SMU_DRAMData_TOC_VERSION 1 +#define MAX_IH_REGISTER_COUNT 65535 +#define SMU_DIGEST_SIZE_BYTES 20 +#define SMU_FB_SIZE_BYTES 1048576 +#define SMU_MAX_ENTRIES 12 + +#define UCODE_ID_SMU 0 +#define UCODE_ID_SDMA0 1 +#define UCODE_ID_SDMA1 2 +#define UCODE_ID_CP_CE 3 +#define UCODE_ID_CP_PFP 4 +#define UCODE_ID_CP_ME 5 +#define UCODE_ID_CP_MEC 6 +#define UCODE_ID_CP_MEC_JT1 7 +#define UCODE_ID_CP_MEC_JT2 8 +#define UCODE_ID_GMCON_RENG 9 +#define UCODE_ID_RLC_G 10 +#define UCODE_ID_IH_REG_RESTORE 11 +#define UCODE_ID_VBIOS 12 +#define UCODE_ID_MISC_METADATA 13 +#define UCODE_ID_RLC_SCRATCH 32 +#define UCODE_ID_RLC_SRM_ARAM 33 +#define UCODE_ID_RLC_SRM_DRAM 34 +#define UCODE_ID_MEC_STORAGE 35 +#define UCODE_ID_VBIOS_PARAMETERS 36 +#define UCODE_META_DATA 0xFF + +#define UCODE_ID_SMU_MASK 0x00000001 +#define UCODE_ID_SDMA0_MASK 0x00000002 +#define UCODE_ID_SDMA1_MASK 0x00000004 +#define UCODE_ID_CP_CE_MASK 0x00000008 +#define UCODE_ID_CP_PFP_MASK 0x00000010 +#define UCODE_ID_CP_ME_MASK 0x00000020 +#define UCODE_ID_CP_MEC_MASK 0x00000040 +#define UCODE_ID_CP_MEC_JT1_MASK 0x00000080 +#define UCODE_ID_CP_MEC_JT2_MASK 0x00000100 +#define UCODE_ID_GMCON_RENG_MASK 0x00000200 +#define UCODE_ID_RLC_G_MASK 0x00000400 +#define UCODE_ID_IH_REG_RESTORE_MASK 0x00000800 +#define UCODE_ID_VBIOS_MASK 0x00001000 + +#define UCODE_FLAG_UNHALT_MASK 0x1 + +struct SMU_Entry { +#ifndef __BIG_ENDIAN + uint16_t id; + uint16_t version; + uint32_t image_addr_high; + uint32_t image_addr_low; + uint32_t meta_data_addr_high; + uint32_t meta_data_addr_low; + uint32_t data_size_byte; + uint16_t flags; + uint16_t num_register_entries; +#else + uint16_t version; + uint16_t id; + uint32_t image_addr_high; + uint32_t image_addr_low; + uint32_t meta_data_addr_high; + uint32_t meta_data_addr_low; + uint32_t data_size_byte; + uint16_t num_register_entries; + uint16_t flags; +#endif +}; + +struct SMU_DRAMData_TOC { + uint32_t structure_version; + uint32_t num_entries; + struct SMU_Entry entry[SMU_MAX_ENTRIES]; +}; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c new file mode 100644 index 000000000000..98bd707ac5dc --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c @@ -0,0 +1,172 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "drmP.h" +#include "amdgpu.h" +#include "tonga_smumgr.h" + +MODULE_FIRMWARE("radeon/tonga_smc.bin"); + +static void tonga_dpm_set_funcs(struct amdgpu_device *adev); + +static int tonga_dpm_early_init(struct amdgpu_device *adev) +{ + tonga_dpm_set_funcs(adev); + + return 0; +} + +static int tonga_dpm_init_microcode(struct amdgpu_device *adev) +{ + char fw_name[30] = "radeon/tonga_smc.bin"; + int err; + + err = request_firmware(&adev->pm.fw, fw_name, adev->dev); + if (err) + goto out; + err = amdgpu_ucode_validate(adev->pm.fw); + +out: + if (err) { + DRM_ERROR("Failed to load firmware \"%s\"", fw_name); + release_firmware(adev->pm.fw); + adev->pm.fw = NULL; + } + return err; +} + +static int tonga_dpm_sw_init(struct amdgpu_device *adev) +{ + int ret; + + ret = tonga_dpm_init_microcode(adev); + if (ret) + return ret; + + return 0; +} + +static int tonga_dpm_sw_fini(struct amdgpu_device *adev) +{ + return 0; +} + +static int tonga_dpm_hw_init(struct amdgpu_device *adev) +{ + int ret; + + mutex_lock(&adev->pm.mutex); + + ret = tonga_smu_init(adev); + if (ret) { + DRM_ERROR("SMU initialization failed\n"); + goto fail; + } + + ret = tonga_smu_start(adev); + if (ret) { + DRM_ERROR("SMU start failed\n"); + goto fail; + } + + mutex_unlock(&adev->pm.mutex); + return 0; + +fail: + adev->firmware.smu_load = false; + mutex_unlock(&adev->pm.mutex); + return -EINVAL; +} + +static int tonga_dpm_hw_fini(struct amdgpu_device *adev) +{ + mutex_lock(&adev->pm.mutex); + tonga_smu_fini(adev); + mutex_unlock(&adev->pm.mutex); + return 0; +} + +static int tonga_dpm_suspend(struct amdgpu_device *adev) +{ + tonga_dpm_hw_fini(adev); + + return 0; +} + +static int tonga_dpm_resume(struct amdgpu_device *adev) +{ + tonga_dpm_hw_init(adev); + + return 0; +} + +static int tonga_dpm_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static int tonga_dpm_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs tonga_dpm_ip_funcs = { + .early_init = tonga_dpm_early_init, + .late_init = NULL, + .sw_init = tonga_dpm_sw_init, + .sw_fini = tonga_dpm_sw_fini, + .hw_init = tonga_dpm_hw_init, + .hw_fini = tonga_dpm_hw_fini, + .suspend = tonga_dpm_suspend, + .resume = tonga_dpm_resume, + .is_idle = NULL, + .wait_for_idle = NULL, + .soft_reset = NULL, + .print_status = NULL, + .set_clockgating_state = tonga_dpm_set_clockgating_state, + .set_powergating_state = tonga_dpm_set_powergating_state, +}; + +static const struct amdgpu_dpm_funcs tonga_dpm_funcs = { + .get_temperature = NULL, + .pre_set_power_state = NULL, + .set_power_state = NULL, + .post_set_power_state = NULL, + .display_configuration_changed = NULL, + .get_sclk = NULL, + .get_mclk = NULL, + .print_power_state = NULL, + .debugfs_print_current_performance_level = NULL, + .force_performance_level = NULL, + .vblank_too_short = NULL, + .powergate_uvd = NULL, +}; + +static void tonga_dpm_set_funcs(struct amdgpu_device *adev) +{ + if (NULL == adev->pm.funcs) + adev->pm.funcs = &tonga_dpm_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c new file mode 100644 index 000000000000..cff1b8bce6a4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -0,0 +1,458 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_ih.h" +#include "vid.h" + +#include "oss/oss_3_0_d.h" +#include "oss/oss_3_0_sh_mask.h" + +#include "bif/bif_5_1_d.h" +#include "bif/bif_5_1_sh_mask.h" + +/* + * Interrupts + * Starting with r6xx, interrupts are handled via a ring buffer. + * Ring buffers are areas of GPU accessible memory that the GPU + * writes interrupt vectors into and the host reads vectors out of. + * There is a rptr (read pointer) that determines where the + * host is currently reading, and a wptr (write pointer) + * which determines where the GPU has written. When the + * pointers are equal, the ring is idle. When the GPU + * writes vectors to the ring buffer, it increments the + * wptr. When there is an interrupt, the host then starts + * fetching commands and processing them until the pointers are + * equal again at which point it updates the rptr. + */ + +static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev); + +/** + * tonga_ih_enable_interrupts - Enable the interrupt ring buffer + * + * @adev: amdgpu_device pointer + * + * Enable the interrupt ring buffer (VI). + */ +static void tonga_ih_enable_interrupts(struct amdgpu_device *adev) +{ + u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); + + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + adev->irq.ih.enabled = true; +} + +/** + * tonga_ih_disable_interrupts - Disable the interrupt ring buffer + * + * @adev: amdgpu_device pointer + * + * Disable the interrupt ring buffer (VI). + */ +static void tonga_ih_disable_interrupts(struct amdgpu_device *adev) +{ + u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); + + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + /* set rptr, wptr to 0 */ + WREG32(mmIH_RB_RPTR, 0); + WREG32(mmIH_RB_WPTR, 0); + adev->irq.ih.enabled = false; + adev->irq.ih.rptr = 0; +} + +/** + * tonga_ih_irq_init - init and enable the interrupt ring + * + * @adev: amdgpu_device pointer + * + * Allocate a ring buffer for the interrupt controller, + * enable the RLC, disable interrupts, enable the IH + * ring buffer and enable it (VI). + * Called at device load and reume. + * Returns 0 for success, errors for failure. + */ +static int tonga_ih_irq_init(struct amdgpu_device *adev) +{ + int ret = 0; + int rb_bufsz; + u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr; + u64 wptr_off; + + /* disable irqs */ + tonga_ih_disable_interrupts(adev); + + /* setup interrupt control */ + WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); + interrupt_cntl = RREG32(mmINTERRUPT_CNTL); + /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi + * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN + */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); + /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ + interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); + WREG32(mmINTERRUPT_CNTL, interrupt_cntl); + + /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ + if (adev->irq.ih.use_bus_addr) + WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8); + else + WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); + + rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); + ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); + /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); + + if (adev->irq.msi_enabled) + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); + + WREG32(mmIH_RB_CNTL, ih_rb_cntl); + + /* set the writeback address whether it's enabled or not */ + if (adev->irq.ih.use_bus_addr) + wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); + else + wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); + WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); + WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); + + /* set rptr, wptr to 0 */ + WREG32(mmIH_RB_RPTR, 0); + WREG32(mmIH_RB_WPTR, 0); + + ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR); + if (adev->irq.ih.use_doorbell) { + ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, + OFFSET, adev->irq.ih.doorbell_index); + ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, + ENABLE, 1); + } else { + ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, + ENABLE, 0); + } + WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); + + pci_set_master(adev->pdev); + + /* enable interrupts */ + tonga_ih_enable_interrupts(adev); + + return ret; +} + +/** + * tonga_ih_irq_disable - disable interrupts + * + * @adev: amdgpu_device pointer + * + * Disable interrupts on the hw (VI). + */ +static void tonga_ih_irq_disable(struct amdgpu_device *adev) +{ + tonga_ih_disable_interrupts(adev); + + /* Wait and acknowledge irq */ + mdelay(1); +} + +/** + * tonga_ih_get_wptr - get the IH ring buffer wptr + * + * @adev: amdgpu_device pointer + * + * Get the IH ring buffer wptr from either the register + * or the writeback memory buffer (VI). Also check for + * ring buffer overflow and deal with it. + * Used by cz_irq_process(VI). + * Returns the value of the wptr. + */ +static u32 tonga_ih_get_wptr(struct amdgpu_device *adev) +{ + u32 wptr, tmp; + + if (adev->irq.ih.use_bus_addr) + wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); + else + wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); + + if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { + wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); + /* When a ring buffer overflow happen start parsing interrupt + * from the last not overwritten vector (wptr + 16). Hopefully + * this should allow us to catchup. + */ + dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", + wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); + adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; + tmp = RREG32(mmIH_RB_CNTL); + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); + WREG32(mmIH_RB_CNTL, tmp); + } + return (wptr & adev->irq.ih.ptr_mask); +} + +/** + * tonga_ih_decode_iv - decode an interrupt vector + * + * @adev: amdgpu_device pointer + * + * Decodes the interrupt vector at the current rptr + * position and also advance the position. + */ +static void tonga_ih_decode_iv(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry) +{ + /* wptr/rptr are in bytes! */ + u32 ring_index = adev->irq.ih.rptr >> 2; + uint32_t dw[4]; + + dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); + dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); + dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); + dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); + + entry->src_id = dw[0] & 0xff; + entry->src_data = dw[1] & 0xfffffff; + entry->ring_id = dw[2] & 0xff; + entry->vm_id = (dw[2] >> 8) & 0xff; + entry->pas_id = (dw[2] >> 16) & 0xffff; + + /* wptr/rptr are in bytes! */ + adev->irq.ih.rptr += 16; +} + +/** + * tonga_ih_set_rptr - set the IH ring buffer rptr + * + * @adev: amdgpu_device pointer + * + * Set the IH ring buffer rptr. + */ +static void tonga_ih_set_rptr(struct amdgpu_device *adev) +{ + if (adev->irq.ih.use_doorbell) { + /* XXX check if swapping is necessary on BE */ + if (adev->irq.ih.use_bus_addr) + adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; + else + adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; + WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); + } else { + WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); + } +} + +static int tonga_ih_early_init(struct amdgpu_device *adev) +{ + tonga_ih_set_interrupt_funcs(adev); + return 0; +} + +static int tonga_ih_sw_init(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_ih_ring_init(adev, 4 * 1024, true); + if (r) + return r; + + adev->irq.ih.use_doorbell = true; + adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH; + + r = amdgpu_irq_init(adev); + + return r; +} + +static int tonga_ih_sw_fini(struct amdgpu_device *adev) +{ + amdgpu_irq_fini(adev); + amdgpu_ih_ring_fini(adev); + + return 0; +} + +static int tonga_ih_hw_init(struct amdgpu_device *adev) +{ + int r; + + r = tonga_ih_irq_init(adev); + if (r) + return r; + + return 0; +} + +static int tonga_ih_hw_fini(struct amdgpu_device *adev) +{ + tonga_ih_irq_disable(adev); + + return 0; +} + +static int tonga_ih_suspend(struct amdgpu_device *adev) +{ + return tonga_ih_hw_fini(adev); +} + +static int tonga_ih_resume(struct amdgpu_device *adev) +{ + return tonga_ih_hw_init(adev); +} + +static bool tonga_ih_is_idle(struct amdgpu_device *adev) +{ + u32 tmp = RREG32(mmSRBM_STATUS); + + if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) + return false; + + return true; +} + +static int tonga_ih_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + u32 tmp; + + for (i = 0; i < adev->usec_timeout; i++) { + /* read MC_STATUS */ + tmp = RREG32(mmSRBM_STATUS); + if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static void tonga_ih_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "TONGA IH registers\n"); + dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", + RREG32(mmSRBM_STATUS)); + dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", + RREG32(mmSRBM_STATUS2)); + dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n", + RREG32(mmINTERRUPT_CNTL)); + dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n", + RREG32(mmINTERRUPT_CNTL2)); + dev_info(adev->dev, " IH_CNTL=0x%08X\n", + RREG32(mmIH_CNTL)); + dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n", + RREG32(mmIH_RB_CNTL)); + dev_info(adev->dev, " IH_RB_BASE=0x%08X\n", + RREG32(mmIH_RB_BASE)); + dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n", + RREG32(mmIH_RB_WPTR_ADDR_LO)); + dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n", + RREG32(mmIH_RB_WPTR_ADDR_HI)); + dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n", + RREG32(mmIH_RB_RPTR)); + dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n", + RREG32(mmIH_RB_WPTR)); +} + +static int tonga_ih_soft_reset(struct amdgpu_device *adev) +{ + u32 srbm_soft_reset = 0; + u32 tmp = RREG32(mmSRBM_STATUS); + + if (tmp & SRBM_STATUS__IH_BUSY_MASK) + srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, + SOFT_RESET_IH, 1); + + if (srbm_soft_reset) { + tonga_ih_print_status(adev); + + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + /* Wait a little for things to settle down */ + udelay(50); + + tonga_ih_print_status(adev); + } + + return 0; +} + +static int tonga_ih_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + // TODO + return 0; +} + +static int tonga_ih_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + // TODO + return 0; +} + +const struct amdgpu_ip_funcs tonga_ih_ip_funcs = { + .early_init = tonga_ih_early_init, + .late_init = NULL, + .sw_init = tonga_ih_sw_init, + .sw_fini = tonga_ih_sw_fini, + .hw_init = tonga_ih_hw_init, + .hw_fini = tonga_ih_hw_fini, + .suspend = tonga_ih_suspend, + .resume = tonga_ih_resume, + .is_idle = tonga_ih_is_idle, + .wait_for_idle = tonga_ih_wait_for_idle, + .soft_reset = tonga_ih_soft_reset, + .print_status = tonga_ih_print_status, + .set_clockgating_state = tonga_ih_set_clockgating_state, + .set_powergating_state = tonga_ih_set_powergating_state, +}; + +static const struct amdgpu_ih_funcs tonga_ih_funcs = { + .get_wptr = tonga_ih_get_wptr, + .decode_iv = tonga_ih_decode_iv, + .set_rptr = tonga_ih_set_rptr +}; + +static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev) +{ + if (adev->irq.ih_funcs == NULL) + adev->irq.ih_funcs = &tonga_ih_funcs; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h new file mode 100644 index 000000000000..7c9bae87124e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __TONGA_IH_H__ +#define __TONGA_IH_H__ + +extern const struct amdgpu_ip_funcs tonga_ih_ip_funcs; + +#endif /* __CZ_IH_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h b/drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h new file mode 100644 index 000000000000..811781f69482 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h @@ -0,0 +1,198 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef TONGA_PP_SMC_H +#define TONGA_PP_SMC_H + +#pragma pack(push, 1) + +#define PPSMC_SWSTATE_FLAG_DC 0x01 +#define PPSMC_SWSTATE_FLAG_UVD 0x02 +#define PPSMC_SWSTATE_FLAG_VCE 0x04 +#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08 + +#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 +#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 +#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff + +#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 +#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 +#define PPSMC_SYSTEMFLAG_GDDR5 0x04 + +#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 + +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 +#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 +#define PPSMC_SYSTEMFLAG_12CHANNEL 0x40 + +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 +#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 + +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 +#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 + +#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x10 +#define PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17 0x20 +#define PPSMC_EXTRAFLAGS_PCC_TO_GPIO17 0x40 + +#define PPSMC_DPM2FLAGS_TDPCLMP 0x01 +#define PPSMC_DPM2FLAGS_PWRSHFT 0x02 +#define PPSMC_DPM2FLAGS_OCP 0x04 + +#define PPSMC_DISPLAY_WATERMARK_LOW 0 +#define PPSMC_DISPLAY_WATERMARK_HIGH 1 + +#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 +#define PPSMC_STATEFLAG_POWERBOOST 0x02 +#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04 +#define PPSMC_STATEFLAG_POWERSHIFT 0x08 +#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10 +#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 +#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 + +#define FDO_MODE_HARDWARE 0 +#define FDO_MODE_PIECE_WISE_LINEAR 1 + +enum FAN_CONTROL { + FAN_CONTROL_FUZZY, + FAN_CONTROL_TABLE +}; + +#define PPSMC_Result_OK ((uint16_t)0x01) +#define PPSMC_Result_NoMore ((uint16_t)0x02) +#define PPSMC_Result_NotNow ((uint16_t)0x03) +#define PPSMC_Result_Failed ((uint16_t)0xFF) +#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) +#define PPSMC_Result_UnknownVT ((uint16_t)0xFD) + +typedef uint16_t PPSMC_Result; + +#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) + +#define PPSMC_MSG_Halt ((uint16_t)0x10) +#define PPSMC_MSG_Resume ((uint16_t)0x11) +#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12) +#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13) +#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14) +#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15) +#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16) +#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17) +#define PPSMC_MSG_LevelUp ((uint16_t)0x18) +#define PPSMC_MSG_LevelDown ((uint16_t)0x19) +#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a) +#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20) +#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f) +#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40) +#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41) +#define PPSMC_MSG_ForceHigh ((uint16_t)0x42) +#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43) +#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51) +#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52) +#define PPSMC_MSG_EnableCac ((uint16_t)0x53) +#define PPSMC_MSG_DisableCac ((uint16_t)0x54) +#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55) +#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56) +#define PPSMC_CACHistoryStart ((uint16_t)0x57) +#define PPSMC_CACHistoryStop ((uint16_t)0x58) +#define PPSMC_TDPClampingActive ((uint16_t)0x59) +#define PPSMC_TDPClampingInactive ((uint16_t)0x5A) +#define PPSMC_StartFanControl ((uint16_t)0x5B) +#define PPSMC_StopFanControl ((uint16_t)0x5C) +#define PPSMC_NoDisplay ((uint16_t)0x5D) +#define PPSMC_HasDisplay ((uint16_t)0x5E) +#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60) +#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61) +#define PPSMC_MSG_EnableULV ((uint16_t)0x62) +#define PPSMC_MSG_DisableULV ((uint16_t)0x63) +#define PPSMC_MSG_EnterULV ((uint16_t)0x64) +#define PPSMC_MSG_ExitULV ((uint16_t)0x65) +#define PPSMC_PowerShiftActive ((uint16_t)0x6A) +#define PPSMC_PowerShiftInactive ((uint16_t)0x6B) +#define PPSMC_OCPActive ((uint16_t)0x6C) +#define PPSMC_OCPInactive ((uint16_t)0x6D) +#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E) +#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F) +#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70) +#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71) +#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72) +#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73) +#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74) +#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75) +#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76) +#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77) +#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78) +#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79) +#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A) +#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B) +#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C) +#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D) +#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E) +#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F) +#define PPSMC_FlushDataCache ((uint16_t)0x80) +#define PPSMC_FlushInstrCache ((uint16_t)0x81) +#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82) +#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83) +#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84) +#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85) +#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86) +#define PPSMC_MSG_EnableDTE ((uint16_t)0x87) +#define PPSMC_MSG_DisableDTE ((uint16_t)0x88) +#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89) +#define PPSMC_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A) +#define PPSMC_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B) +#define PPSMC_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C) +#define PPSMC_MSG_ChangeNearTDPLimit ((uint16_t)0x90) +#define PPSMC_MSG_ChangeSafePowerLimit ((uint16_t)0x91) +#define PPSMC_MSG_DPMStateSweepStart ((uint16_t)0x92) +#define PPSMC_MSG_DPMStateSweepStop ((uint16_t)0x93) +#define PPSMC_MSG_OVRDDisableSCLKDS ((uint16_t)0x94) +#define PPSMC_MSG_CancelDisableOVRDSCLKDS ((uint16_t)0x95) +#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint16_t)0x96) +#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint16_t)0x97) +#define PPSMC_MSG_GPIO17 ((uint16_t)0x98) +#define PPSMC_MSG_API_SetSvi2Volt_Vddc ((uint16_t)0x99) +#define PPSMC_MSG_API_SetSvi2Volt_Vddci ((uint16_t)0x9A) +#define PPSMC_MSG_API_SetSvi2Volt_Mvdd ((uint16_t)0x9B) +#define PPSMC_MSG_API_GetSvi2Volt_Vddc ((uint16_t)0x9C) +#define PPSMC_MSG_API_GetSvi2Volt_Vddci ((uint16_t)0x9D) +#define PPSMC_MSG_API_GetSvi2Volt_Mvdd ((uint16_t)0x9E) + +#define PPSMC_MSG_BREAK ((uint16_t)0xF8) + +#define PPSMC_MSG_Test ((uint16_t)0x100) +#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t)0x250) +#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t)0x251) +#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t)0x252) +#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t)0x253) +#define PPSMC_MSG_LoadUcodes ((uint16_t)0x254) + +typedef uint16_t PPSMC_Msg; + +#define PPSMC_EVENT_STATUS_THERMAL 0x00000001 +#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002 +#define PPSMC_EVENT_STATUS_DC 0x00000004 +#define PPSMC_EVENT_STATUS_GPIO17 0x00000008 + +#pragma pack(pop) + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_sdma_pkt_open.h b/drivers/gpu/drm/amd/amdgpu/tonga_sdma_pkt_open.h new file mode 100644 index 000000000000..099b7b56113c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/tonga_sdma_pkt_open.h @@ -0,0 +1,2240 @@ +/* + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __TONGA_SDMA_PKT_OPEN_H_ +#define __TONGA_SDMA_PKT_OPEN_H_ + +#define SDMA_OP_NOP 0 +#define SDMA_OP_COPY 1 +#define SDMA_OP_WRITE 2 +#define SDMA_OP_INDIRECT 4 +#define SDMA_OP_FENCE 5 +#define SDMA_OP_TRAP 6 +#define SDMA_OP_SEM 7 +#define SDMA_OP_POLL_REGMEM 8 +#define SDMA_OP_COND_EXE 9 +#define SDMA_OP_ATOMIC 10 +#define SDMA_OP_CONST_FILL 11 +#define SDMA_OP_GEN_PTEPDE 12 +#define SDMA_OP_TIMESTAMP 13 +#define SDMA_OP_SRBM_WRITE 14 +#define SDMA_OP_PRE_EXE 15 +#define SDMA_SUBOP_TIMESTAMP_SET 0 +#define SDMA_SUBOP_TIMESTAMP_GET 1 +#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 +#define SDMA_SUBOP_COPY_LINEAR 0 +#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 +#define SDMA_SUBOP_COPY_TILED 1 +#define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 +#define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 +#define SDMA_SUBOP_COPY_SOA 3 +#define SDMA_SUBOP_WRITE_LINEAR 0 +#define SDMA_SUBOP_WRITE_TILED 1 + +/*define for op field*/ +#define SDMA_PKT_HEADER_op_offset 0 +#define SDMA_PKT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_HEADER_op_shift 0 +#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_HEADER_sub_op_offset 0 +#define SDMA_PKT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_HEADER_sub_op_shift 8 +#define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) + +/* +** Definitions for SDMA_PKT_COPY_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) + +/*define for dst_ha field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift 22 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) + +/*define for src_ha field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift 30 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst2_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) + +/*define for dst2_ha field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift 14 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift) + +/*define for dst1_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) + +/*define for dst1_ha field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift 22 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) + +/*define for src_ha field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift 30 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST1_ADDR_LO word*/ +/*define for dst1_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) + +/*define for DST1_ADDR_HI word*/ +/*define for dst1_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) + +/*define for DST2_ADDR_LO word*/ +/*define for dst2_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) + +/*define for DST2_ADDR_HI word*/ +/*define for dst2_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) + +/*define for elementsize field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) + +/*define for src_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) + +/*define for DW_5 word*/ +/*define for src_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_8 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) + +/*define for DW_9 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) + +/*define for dst_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) + +/*define for DW_10 word*/ +/*define for dst_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) + +/*define for DW_11 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) + +/*define for DW_12 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) + +/*define for dst_ha field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift 22 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) + +/*define for src_ha field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift 30 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for pitch_in_tile field*/ +#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_offset 3 +#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift 0 +#define SDMA_PKT_COPY_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift) + +/*define for height field*/ +#define SDMA_PKT_COPY_TILED_DW_3_height_offset 3 +#define SDMA_PKT_COPY_TILED_DW_3_height_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_3_height_shift 16 +#define SDMA_PKT_COPY_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_height_mask) << SDMA_PKT_COPY_TILED_DW_3_height_shift) + +/*define for DW_4 word*/ +/*define for slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_offset 4 +#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) + +/*define for array_mode field*/ +#define SDMA_PKT_COPY_TILED_DW_5_array_mode_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_DW_5_array_mode_shift 3 +#define SDMA_PKT_COPY_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_array_mode_shift) + +/*define for mit_mode field*/ +#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift 8 +#define SDMA_PKT_COPY_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift) + +/*define for tilesplit_size field*/ +#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift) + +/*define for bank_w field*/ +#define SDMA_PKT_COPY_TILED_DW_5_bank_w_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_5_bank_w_shift 15 +#define SDMA_PKT_COPY_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_w_shift) + +/*define for bank_h field*/ +#define SDMA_PKT_COPY_TILED_DW_5_bank_h_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_5_bank_h_shift 18 +#define SDMA_PKT_COPY_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_h_shift) + +/*define for num_bank field*/ +#define SDMA_PKT_COPY_TILED_DW_5_num_bank_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_5_num_bank_shift 21 +#define SDMA_PKT_COPY_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_DW_5_num_bank_shift) + +/*define for mat_aspt field*/ +#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift 24 +#define SDMA_PKT_COPY_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift) + +/*define for pipe_config field*/ +#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift 26 +#define SDMA_PKT_COPY_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 +#define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 +#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 +#define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 +#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00000FFF +#define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 +#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for LINEAR_PITCH word*/ +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_TILED_COUNT_count_offset 11 +#define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 +#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) + +/*define for videocopy field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) + +/*define for TILED_ADDR_LO_0 word*/ +/*define for tiled_addr0_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) + +/*define for TILED_ADDR_HI_0 word*/ +/*define for tiled_addr0_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) + +/*define for TILED_ADDR_LO_1 word*/ +/*define for tiled_addr1_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) + +/*define for TILED_ADDR_HI_1 word*/ +/*define for tiled_addr1_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) + +/*define for DW_5 word*/ +/*define for pitch_in_tile field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_offset 5 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask 0x000007FF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift) + +/*define for height field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_offset 5 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift) + +/*define for DW_6 word*/ +/*define for slice_pitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_offset 6 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift) + +/*define for DW_7 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) + +/*define for array_mode field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift 3 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift) + +/*define for mit_mode field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIT_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift) + +/*define for tilesplit_size field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift) + +/*define for bank_w field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift 15 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_W(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift) + +/*define for bank_h field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift 18 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_H(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift) + +/*define for num_bank field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift 21 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_NUM_BANK(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift) + +/*define for mat_aspt field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift 24 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift) + +/*define for pipe_config field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift 26 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift) + +/*define for DW_8 word*/ +/*define for x field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) + +/*define for y field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) + +/*define for DW_9 word*/ +/*define for z field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00000FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) + +/*define for DW_10 word*/ +/*define for dst2_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) + +/*define for dst2_ha field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift 14 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_HA(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for LINEAR_PITCH word*/ +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 14 +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_COPY_T2T packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 +#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) + +/*define for src_pitch_in_tile field*/ +#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_offset 4 +#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask 0x00000FFF +#define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift 16 +#define SDMA_PKT_COPY_T2T_DW_4_SRC_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift) + +/*define for DW_5 word*/ +/*define for src_slice_pitch field*/ +#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_offset 5 +#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift 0 +#define SDMA_PKT_COPY_T2T_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift) + +/*define for DW_6 word*/ +/*define for src_element_size field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) + +/*define for src_array_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift 3 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift) + +/*define for src_mit_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift 8 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift) + +/*define for src_tilesplit_size field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift) + +/*define for src_bank_w field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift 15 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift) + +/*define for src_bank_h field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift 18 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift) + +/*define for src_num_bank field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift 21 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift) + +/*define for src_mat_aspt field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift 24 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift) + +/*define for src_pipe_config field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift 26 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) + +/*define for DW_10 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) + +/*define for dst_pitch_in_tile field*/ +#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_offset 10 +#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask 0x00000FFF +#define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift 16 +#define SDMA_PKT_COPY_T2T_DW_10_DST_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift) + +/*define for DW_11 word*/ +/*define for dst_slice_pitch field*/ +#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_offset 11 +#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift 0 +#define SDMA_PKT_COPY_T2T_DW_11_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift) + +/*define for DW_12 word*/ +/*define for dst_array_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift 3 +#define SDMA_PKT_COPY_T2T_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift) + +/*define for dst_mit_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift 8 +#define SDMA_PKT_COPY_T2T_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift) + +/*define for dst_tilesplit_size field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_T2T_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift) + +/*define for dst_bank_w field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift 15 +#define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift) + +/*define for dst_bank_h field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift 18 +#define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift) + +/*define for dst_num_bank field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift 21 +#define SDMA_PKT_COPY_T2T_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift) + +/*define for dst_mat_aspt field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift 24 +#define SDMA_PKT_COPY_T2T_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift) + +/*define for dst_pipe_config field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift 26 +#define SDMA_PKT_COPY_T2T_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift) + +/*define for DW_13 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) + +/*define for DW_14 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 +#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 +#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for tiled_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) + +/*define for tiled_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) + +/*define for DW_4 word*/ +/*define for tiled_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) + +/*define for pitch_in_tile field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask 0x00000FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift) + +/*define for DW_5 word*/ +/*define for slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_offset 5 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift) + +/*define for DW_6 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) + +/*define for array_mode field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift) + +/*define for mit_mode field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift) + +/*define for tilesplit_size field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift) + +/*define for bank_w field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift 15 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift) + +/*define for bank_h field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift 18 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift) + +/*define for num_bank field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift 21 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift) + +/*define for mat_aspt field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift) + +/*define for pipe_config field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift 26 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for linear_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) + +/*define for linear_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) + +/*define for DW_10 word*/ +/*define for linear_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) + +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) + +/*define for DW_11 word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) + +/*define for DW_12 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) + +/*define for DW_13 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_STRUCT packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) + +/*define for SB_ADDR_LO word*/ +/*define for sb_addr_31_0 field*/ +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) + +/*define for SB_ADDR_HI word*/ +/*define for sb_addr_63_32 field*/ +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) + +/*define for START_INDEX word*/ +/*define for start_index field*/ +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 +#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 +#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 +#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) + +/*define for DW_5 word*/ +/*define for stride field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) + +/*define for struct_sw field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 16 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) + +/*define for struct_ha field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift 22 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 24 +#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) + +/*define for linear_ha field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift 30 +#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_UNTILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x003FFFFF +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) + +/*define for sw field*/ +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 +#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_TILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for pitch_in_tile field*/ +#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_offset 3 +#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask 0x000007FF +#define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift) + +/*define for height field*/ +#define SDMA_PKT_WRITE_TILED_DW_3_height_offset 3 +#define SDMA_PKT_WRITE_TILED_DW_3_height_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_3_height_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_height_mask) << SDMA_PKT_WRITE_TILED_DW_3_height_shift) + +/*define for DW_4 word*/ +/*define for slice_pitch field*/ +#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_offset 4 +#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask 0x003FFFFF +#define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) + +/*define for array_mode field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask 0x0000000F +#define SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift 3 +#define SDMA_PKT_WRITE_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift) + +/*define for mit_mode field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift 8 +#define SDMA_PKT_WRITE_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift) + +/*define for tilesplit_size field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift 11 +#define SDMA_PKT_WRITE_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift) + +/*define for bank_w field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift 15 +#define SDMA_PKT_WRITE_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift) + +/*define for bank_h field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift 18 +#define SDMA_PKT_WRITE_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift) + +/*define for num_bank field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift 21 +#define SDMA_PKT_WRITE_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift) + +/*define for mat_aspt field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift 24 +#define SDMA_PKT_WRITE_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift) + +/*define for pipe_config field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask 0x0000001F +#define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift 26 +#define SDMA_PKT_WRITE_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 +#define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 +#define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 +#define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00000FFF +#define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) + +/*define for sw field*/ +#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 +#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 +#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 +#define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 +#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 +#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 +#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_INCR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for MASK_DW0 word*/ +/*define for mask_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) + +/*define for MASK_DW1 word*/ +/*define for mask_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) + +/*define for INIT_DW0 word*/ +/*define for init_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) + +/*define for INIT_DW1 word*/ +/*define for init_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) + +/*define for INCR_DW0 word*/ +/*define for incr_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) + +/*define for INCR_DW1 word*/ +/*define for incr_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 +#define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF +#define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 +#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_INDIRECT packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_INDIRECT_HEADER_op_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_INDIRECT_HEADER_op_shift 0 +#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 +#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) + +/*define for vmid field*/ +#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F +#define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 +#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) + +/*define for BASE_LO word*/ +/*define for ib_base_31_0 field*/ +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 +#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) + +/*define for BASE_HI word*/ +/*define for ib_base_63_32 field*/ +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 +#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) + +/*define for IB_SIZE word*/ +/*define for ib_size field*/ +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 +#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) + +/*define for CSA_ADDR_LO word*/ +/*define for csa_addr_31_0 field*/ +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) + +/*define for CSA_ADDR_HI word*/ +/*define for csa_addr_63_32 field*/ +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_SEMAPHORE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 +#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 +#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) + +/*define for write_one field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 +#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) + +/*define for signal field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 +#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) + +/*define for mailbox field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 +#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_FENCE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_FENCE_HEADER_op_offset 0 +#define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_FENCE_HEADER_op_shift 0 +#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 +#define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 +#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) + +/*define for DATA word*/ +/*define for data field*/ +#define SDMA_PKT_FENCE_DATA_data_offset 3 +#define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_DATA_data_shift 0 +#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) + + +/* +** Definitions for SDMA_PKT_SRBM_WRITE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 +#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) + +/*define for byte_en field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 +#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) + +/*define for ADDR word*/ +/*define for addr field*/ +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0000FFFF +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 +#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) + +/*define for DATA word*/ +/*define for data field*/ +#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 +#define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF +#define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 +#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) + + +/* +** Definitions for SDMA_PKT_PRE_EXE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 +#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 +#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) + +/*define for dev_sel field*/ +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 +#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) + +/*define for EXEC_COUNT word*/ +/*define for exec_count field*/ +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) + + +/* +** Definitions for SDMA_PKT_COND_EXE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COND_EXE_HEADER_op_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COND_EXE_HEADER_op_shift 0 +#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 +#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) + +/*define for REFERENCE word*/ +/*define for reference field*/ +#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 +#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 +#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) + +/*define for EXEC_COUNT word*/ +/*define for exec_count field*/ +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 +#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) + + +/* +** Definitions for SDMA_PKT_CONSTANT_FILL packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 +#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) + +/*define for sw field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 +#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) + +/*define for fillsize field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 +#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DATA word*/ +/*define for src_data_31_0 field*/ +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 +#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_POLL_REGMEM packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) + +/*define for hdp_flush field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 +#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) + +/*define for func field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 +#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 +#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) + +/*define for mem_poll field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 +#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) + +/*define for VALUE word*/ +/*define for value field*/ +#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 +#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 +#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) + +/*define for MASK word*/ +/*define for mask field*/ +#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 +#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 +#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) + +/*define for DW5 word*/ +/*define for interval field*/ +#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 +#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF +#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 +#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) + +/*define for retry_count field*/ +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 +#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) + + +/* +** Definitions for SDMA_PKT_ATOMIC packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_ATOMIC_HEADER_op_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF +#define SDMA_PKT_ATOMIC_HEADER_op_shift 0 +#define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) + +/*define for loop field*/ +#define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 +#define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 +#define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) + +/*define for atomic_op field*/ +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 +#define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) + +/*define for SRC_DATA_LO word*/ +/*define for src_data_31_0 field*/ +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) + +/*define for SRC_DATA_HI word*/ +/*define for src_data_63_32 field*/ +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) + +/*define for CMP_DATA_LO word*/ +/*define for cmp_data_31_0 field*/ +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) + +/*define for CMP_DATA_HI word*/ +/*define for cmp_data_63_32 field*/ +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) + +/*define for LOOP_INTERVAL word*/ +/*define for loop_interval field*/ +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_SET packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) + +/*define for INIT_DATA_LO word*/ +/*define for init_data_31_0 field*/ +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) + +/*define for INIT_DATA_HI word*/ +/*define for init_data_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_GET packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) + +/*define for WRITE_ADDR_LO word*/ +/*define for write_addr_31_3 field*/ +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) + +/*define for WRITE_ADDR_HI word*/ +/*define for write_addr_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) + +/*define for WRITE_ADDR_LO word*/ +/*define for write_addr_31_3 field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) + +/*define for WRITE_ADDR_HI word*/ +/*define for write_addr_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TRAP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TRAP_HEADER_op_offset 0 +#define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TRAP_HEADER_op_shift 0 +#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 +#define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 +#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) + +/*define for INT_CONTEXT word*/ +/*define for int_context field*/ +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 +#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) + + +/* +** Definitions for SDMA_PKT_NOP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_NOP_HEADER_op_offset 0 +#define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_NOP_HEADER_op_shift 0 +#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_NOP_HEADER_sub_op_offset 0 +#define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_NOP_HEADER_sub_op_shift 8 +#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) + + +#endif /* __TONGA_SDMA_PKT_OPEN_H_ */ diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_smc.c b/drivers/gpu/drm/amd/amdgpu/tonga_smc.c new file mode 100644 index 000000000000..5fc53a40c7ac --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/tonga_smc.c @@ -0,0 +1,852 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "drmP.h" +#include "amdgpu.h" +#include "tonga_ppsmc.h" +#include "tonga_smumgr.h" +#include "smu_ucode_xfer_vi.h" +#include "amdgpu_ucode.h" + +#include "smu/smu_7_1_2_d.h" +#include "smu/smu_7_1_2_sh_mask.h" + +#define TONGA_SMC_SIZE 0x20000 + +static int tonga_set_smc_sram_address(struct amdgpu_device *adev, uint32_t smc_address, uint32_t limit) +{ + uint32_t val; + + if (smc_address & 3) + return -EINVAL; + + if ((smc_address + 3) > limit) + return -EINVAL; + + WREG32(mmSMC_IND_INDEX_0, smc_address); + + val = RREG32(mmSMC_IND_ACCESS_CNTL); + val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); + WREG32(mmSMC_IND_ACCESS_CNTL, val); + + return 0; +} + +static int tonga_copy_bytes_to_smc(struct amdgpu_device *adev, uint32_t smc_start_address, const uint8_t *src, uint32_t byte_count, uint32_t limit) +{ + uint32_t addr; + uint32_t data, orig_data; + int result = 0; + uint32_t extra_shift; + unsigned long flags; + + if (smc_start_address & 3) + return -EINVAL; + + if ((smc_start_address + byte_count) > limit) + return -EINVAL; + + addr = smc_start_address; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + while (byte_count >= 4) { + /* Bytes are written into the SMC addres space with the MSB first */ + data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3]; + + result = tonga_set_smc_sram_address(adev, addr, limit); + + if (result) + goto out; + + WREG32(mmSMC_IND_DATA_0, data); + + src += 4; + byte_count -= 4; + addr += 4; + } + + if (0 != byte_count) { + /* Now write odd bytes left, do a read modify write cycle */ + data = 0; + + result = tonga_set_smc_sram_address(adev, addr, limit); + if (result) + goto out; + + orig_data = RREG32(mmSMC_IND_DATA_0); + extra_shift = 8 * (4 - byte_count); + + while (byte_count > 0) { + data = (data << 8) + *src++; + byte_count--; + } + + data <<= extra_shift; + data |= (orig_data & ~((~0UL) << extra_shift)); + + result = tonga_set_smc_sram_address(adev, addr, limit); + if (result) + goto out; + + WREG32(mmSMC_IND_DATA_0, data); + } + +out: + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + return result; +} + +static int tonga_program_jump_on_start(struct amdgpu_device *adev) +{ + static unsigned char data[] = {0xE0, 0x00, 0x80, 0x40}; + tonga_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1); + + return 0; +} + +static bool tonga_is_smc_ram_running(struct amdgpu_device *adev) +{ + uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + val = REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable); + + return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C))); +} + +static int wait_smu_response(struct amdgpu_device *adev) +{ + int i; + uint32_t val; + + for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32(mmSMC_RESP_0); + if (REG_GET_FIELD(val, SMC_RESP_0, SMC_RESP)) + break; + udelay(1); + } + + if (i == adev->usec_timeout) + return -EINVAL; + + return 0; +} + +static int tonga_send_msg_to_smc_offset(struct amdgpu_device *adev) +{ + if (wait_smu_response(adev)) { + DRM_ERROR("Failed to send previous message\n"); + return -EINVAL; + } + + WREG32(mmSMC_MSG_ARG_0, 0x20000); + WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_Test); + + if (wait_smu_response(adev)) { + DRM_ERROR("Failed to send message\n"); + return -EINVAL; + } + + return 0; +} + +static int tonga_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg) +{ + if (!tonga_is_smc_ram_running(adev)) + { + return -EINVAL;; + } + + if (wait_smu_response(adev)) { + DRM_ERROR("Failed to send previous message\n"); + return -EINVAL; + } + + WREG32(mmSMC_MESSAGE_0, msg); + + if (wait_smu_response(adev)) { + DRM_ERROR("Failed to send message\n"); + return -EINVAL; + } + + return 0; +} + +static int tonga_send_msg_to_smc_without_waiting(struct amdgpu_device *adev, + PPSMC_Msg msg) +{ + if (wait_smu_response(adev)) { + DRM_ERROR("Failed to send previous message\n"); + return -EINVAL; + } + + WREG32(mmSMC_MESSAGE_0, msg); + + return 0; +} + +static int tonga_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, + PPSMC_Msg msg, + uint32_t parameter) +{ + if (!tonga_is_smc_ram_running(adev)) + return -EINVAL; + + if (wait_smu_response(adev)) { + DRM_ERROR("Failed to send previous message\n"); + return -EINVAL; + } + + WREG32(mmSMC_MSG_ARG_0, parameter); + + return tonga_send_msg_to_smc(adev, msg); +} + +static int tonga_send_msg_to_smc_with_parameter_without_waiting( + struct amdgpu_device *adev, + PPSMC_Msg msg, uint32_t parameter) +{ + if (wait_smu_response(adev)) { + DRM_ERROR("Failed to send previous message\n"); + return -EINVAL; + } + + WREG32(mmSMC_MSG_ARG_0, parameter); + + return tonga_send_msg_to_smc_without_waiting(adev, msg); +} + +#if 0 /* not used yet */ +static int tonga_wait_for_smc_inactive(struct amdgpu_device *adev) +{ + int i; + uint32_t val; + + if (!tonga_is_smc_ram_running(adev)) + return -EINVAL; + + for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + if (REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, cken) == 0) + break; + udelay(1); + } + + if (i == adev->usec_timeout) + return -EINVAL; + + return 0; +} +#endif + +static int tonga_smu_upload_firmware_image(struct amdgpu_device *adev) +{ + const struct smc_firmware_header_v1_0 *hdr; + uint32_t ucode_size; + uint32_t ucode_start_address; + const uint8_t *src; + uint32_t val; + uint32_t byte_count; + uint32_t *data; + unsigned long flags; + + if (!adev->pm.fw) + return -EINVAL; + + hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data; + amdgpu_ucode_print_smc_hdr(&hdr->header); + + adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); + ucode_start_address = le32_to_cpu(hdr->ucode_start_addr); + src = (const uint8_t *) + (adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + if (ucode_size & 3) { + DRM_ERROR("SMC ucode is not 4 bytes aligned\n"); + return -EINVAL; + } + + if (ucode_size > TONGA_SMC_SIZE) { + DRM_ERROR("SMC address is beyond the SMC RAM area\n"); + return -EINVAL; + } + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + WREG32(mmSMC_IND_INDEX_0, ucode_start_address); + + val = RREG32(mmSMC_IND_ACCESS_CNTL); + val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1); + WREG32(mmSMC_IND_ACCESS_CNTL, val); + + byte_count = ucode_size; + data = (uint32_t *)src; + for (; byte_count >= 4; data++, byte_count -= 4) + WREG32(mmSMC_IND_DATA_0, data[0]); + + val = RREG32(mmSMC_IND_ACCESS_CNTL); + val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); + WREG32(mmSMC_IND_ACCESS_CNTL, val); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + + return 0; +} + +#if 0 /* not used yet */ +static int tonga_read_smc_sram_dword(struct amdgpu_device *adev, + uint32_t smc_address, + uint32_t *value, + uint32_t limit) +{ + int result; + unsigned long flags; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + result = tonga_set_smc_sram_address(adev, smc_address, limit); + if (result == 0) + *value = RREG32(mmSMC_IND_DATA_0); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + return result; +} + +static int tonga_write_smc_sram_dword(struct amdgpu_device *adev, + uint32_t smc_address, + uint32_t value, + uint32_t limit) +{ + int result; + unsigned long flags; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + result = tonga_set_smc_sram_address(adev, smc_address, limit); + if (result == 0) + WREG32(mmSMC_IND_DATA_0, value); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + return result; +} + +static int tonga_smu_stop_smc(struct amdgpu_device *adev) +{ + uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); + val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1); + WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); + + val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1); + WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val); + + return 0; +} +#endif + +static enum AMDGPU_UCODE_ID tonga_convert_fw_type(uint32_t fw_type) +{ + switch (fw_type) { + case UCODE_ID_SDMA0: + return AMDGPU_UCODE_ID_SDMA0; + case UCODE_ID_SDMA1: + return AMDGPU_UCODE_ID_SDMA1; + case UCODE_ID_CP_CE: + return AMDGPU_UCODE_ID_CP_CE; + case UCODE_ID_CP_PFP: + return AMDGPU_UCODE_ID_CP_PFP; + case UCODE_ID_CP_ME: + return AMDGPU_UCODE_ID_CP_ME; + case UCODE_ID_CP_MEC: + case UCODE_ID_CP_MEC_JT1: + return AMDGPU_UCODE_ID_CP_MEC1; + case UCODE_ID_CP_MEC_JT2: + return AMDGPU_UCODE_ID_CP_MEC2; + case UCODE_ID_RLC_G: + return AMDGPU_UCODE_ID_RLC_G; + default: + DRM_ERROR("ucode type is out of range!\n"); + return AMDGPU_UCODE_ID_MAXIMUM; + } +} + +static int tonga_smu_populate_single_firmware_entry(struct amdgpu_device *adev, + uint32_t fw_type, + struct SMU_Entry *entry) +{ + enum AMDGPU_UCODE_ID id = tonga_convert_fw_type(fw_type); + struct amdgpu_firmware_info *ucode = &adev->firmware.ucode[id]; + const struct gfx_firmware_header_v1_0 *header = NULL; + uint64_t gpu_addr; + uint32_t data_size; + + if (ucode->fw == NULL) + return -EINVAL; + + gpu_addr = ucode->mc_addr; + header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; + data_size = le32_to_cpu(header->header.ucode_size_bytes); + + if ((fw_type == UCODE_ID_CP_MEC_JT1) || + (fw_type == UCODE_ID_CP_MEC_JT2)) { + gpu_addr += le32_to_cpu(header->jt_offset) << 2; + data_size = le32_to_cpu(header->jt_size) << 2; + } + + entry->version = (uint16_t)le32_to_cpu(header->header.ucode_version); + entry->id = (uint16_t)fw_type; + entry->image_addr_high = upper_32_bits(gpu_addr); + entry->image_addr_low = lower_32_bits(gpu_addr); + entry->meta_data_addr_high = 0; + entry->meta_data_addr_low = 0; + entry->data_size_byte = data_size; + entry->num_register_entries = 0; + + if (fw_type == UCODE_ID_RLC_G) + entry->flags = 1; + else + entry->flags = 0; + + return 0; +} + +static int tonga_smu_request_load_fw(struct amdgpu_device *adev) +{ + struct tonga_smu_private_data *private = (struct tonga_smu_private_data *)adev->smu.priv; + struct SMU_DRAMData_TOC *toc; + uint32_t fw_to_load; + + WREG32_SMC(ixSOFT_REGISTERS_TABLE_28, 0); + + tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_HI, private->smu_buffer_addr_high); + tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_LO, private->smu_buffer_addr_low); + + toc = (struct SMU_DRAMData_TOC *)private->header; + toc->num_entries = 0; + toc->structure_version = 1; + + if (!adev->firmware.smu_load) + return 0; + + if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_RLC_G, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for RLC\n"); + return -EINVAL; + } + + if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_CE, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for CE\n"); + return -EINVAL; + } + + if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_PFP, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for PFP\n"); + return -EINVAL; + } + + if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_ME, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for ME\n"); + return -EINVAL; + } + + if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for MEC\n"); + return -EINVAL; + } + + if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT1, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for MEC_JT1\n"); + return -EINVAL; + } + + if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for MEC_JT2\n"); + return -EINVAL; + } + + if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for SDMA0\n"); + return -EINVAL; + } + + if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA1, + &toc->entry[toc->num_entries++])) { + DRM_ERROR("Failed to get firmware entry for SDMA1\n"); + return -EINVAL; + } + + tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_HI, private->header_addr_high); + tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_LO, private->header_addr_low); + + fw_to_load = UCODE_ID_RLC_G_MASK | + UCODE_ID_SDMA0_MASK | + UCODE_ID_SDMA1_MASK | + UCODE_ID_CP_CE_MASK | + UCODE_ID_CP_ME_MASK | + UCODE_ID_CP_PFP_MASK | + UCODE_ID_CP_MEC_MASK; + + if (tonga_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) { + DRM_ERROR("Fail to request SMU load ucode\n"); + return -EINVAL; + } + + return 0; +} + +static uint32_t tonga_smu_get_mask_for_fw_type(uint32_t fw_type) +{ + switch (fw_type) { + case AMDGPU_UCODE_ID_SDMA0: + return UCODE_ID_SDMA0_MASK; + case AMDGPU_UCODE_ID_SDMA1: + return UCODE_ID_SDMA1_MASK; + case AMDGPU_UCODE_ID_CP_CE: + return UCODE_ID_CP_CE_MASK; + case AMDGPU_UCODE_ID_CP_PFP: + return UCODE_ID_CP_PFP_MASK; + case AMDGPU_UCODE_ID_CP_ME: + return UCODE_ID_CP_ME_MASK; + case AMDGPU_UCODE_ID_CP_MEC1: + return UCODE_ID_CP_MEC_MASK; + case AMDGPU_UCODE_ID_CP_MEC2: + return UCODE_ID_CP_MEC_MASK; + case AMDGPU_UCODE_ID_RLC_G: + return UCODE_ID_RLC_G_MASK; + default: + DRM_ERROR("ucode type is out of range!\n"); + return 0; + } +} + +static int tonga_smu_check_fw_load_finish(struct amdgpu_device *adev, + uint32_t fw_type) +{ + uint32_t fw_mask = tonga_smu_get_mask_for_fw_type(fw_type); + int i; + + for (i = 0; i < adev->usec_timeout; i++) { + if (fw_mask == (RREG32_SMC(ixSOFT_REGISTERS_TABLE_28) & fw_mask)) + break; + udelay(1); + } + + if (i == adev->usec_timeout) { + DRM_ERROR("check firmware loading failed\n"); + return -EINVAL; + } + + return 0; +} + +static int tonga_smu_start_in_protection_mode(struct amdgpu_device *adev) +{ + int result; + uint32_t val; + int i; + + /* Assert reset */ + val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); + val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1); + WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); + + result = tonga_smu_upload_firmware_image(adev); + if (result) + return result; + + /* Clear status */ + WREG32_SMC(ixSMU_STATUS, 0); + + /* Enable clock */ + val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); + WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val); + + /* De-assert reset */ + val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); + val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0); + WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); + + /* Set SMU Auto Start */ + val = RREG32_SMC(ixSMU_INPUT_DATA); + val = REG_SET_FIELD(val, SMU_INPUT_DATA, AUTO_START, 1); + WREG32_SMC(ixSMU_INPUT_DATA, val); + + /* Clear firmware interrupt enable flag */ + WREG32_SMC(ixFIRMWARE_FLAGS, 0); + + for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32_SMC(ixRCU_UC_EVENTS); + if (REG_GET_FIELD(val, RCU_UC_EVENTS, INTERRUPTS_ENABLED)) + break; + udelay(1); + } + + if (i == adev->usec_timeout) { + DRM_ERROR("Interrupt is not enabled by firmware\n"); + return -EINVAL; + } + + /* Call Test SMU message with 0x20000 offset + * to trigger SMU start + */ + tonga_send_msg_to_smc_offset(adev); + + /* Wait for done bit to be set */ + for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32_SMC(ixSMU_STATUS); + if (REG_GET_FIELD(val, SMU_STATUS, SMU_DONE)) + break; + udelay(1); + } + + if (i == adev->usec_timeout) { + DRM_ERROR("Timeout for SMU start\n"); + return -EINVAL; + } + + /* Check pass/failed indicator */ + val = RREG32_SMC(ixSMU_STATUS); + if (!REG_GET_FIELD(val, SMU_STATUS, SMU_PASS)) { + DRM_ERROR("SMU Firmware start failed\n"); + return -EINVAL; + } + + /* Wait for firmware to initialize */ + for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32_SMC(ixFIRMWARE_FLAGS); + if(REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED)) + break; + udelay(1); + } + + if (i == adev->usec_timeout) { + DRM_ERROR("SMU firmware initialization failed\n"); + return -EINVAL; + } + + return 0; +} + +static int tonga_smu_start_in_non_protection_mode(struct amdgpu_device *adev) +{ + int i, result; + uint32_t val; + + /* wait for smc boot up */ + for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32_SMC(ixRCU_UC_EVENTS); + val = REG_GET_FIELD(val, RCU_UC_EVENTS, boot_seq_done); + if (val) + break; + udelay(1); + } + + if (i == adev->usec_timeout) { + DRM_ERROR("SMC boot sequence is not completed\n"); + return -EINVAL; + } + + /* Clear firmware interrupt enable flag */ + WREG32_SMC(ixFIRMWARE_FLAGS, 0); + + /* Assert reset */ + val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); + val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1); + WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); + + result = tonga_smu_upload_firmware_image(adev); + if (result) + return result; + + /* Set smc instruct start point at 0x0 */ + tonga_program_jump_on_start(adev); + + /* Enable clock */ + val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); + val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); + WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val); + + /* De-assert reset */ + val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); + val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0); + WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); + + /* Wait for firmware to initialize */ + for (i = 0; i < adev->usec_timeout; i++) { + val = RREG32_SMC(ixFIRMWARE_FLAGS); + if (REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED)) + break; + udelay(1); + } + + if (i == adev->usec_timeout) { + DRM_ERROR("Timeout for SMC firmware initialization\n"); + return -EINVAL; + } + + return 0; +} + +int tonga_smu_start(struct amdgpu_device *adev) +{ + int result; + uint32_t val; + + if (!tonga_is_smc_ram_running(adev)) { + val = RREG32_SMC(ixSMU_FIRMWARE); + if (!REG_GET_FIELD(val, SMU_FIRMWARE, SMU_MODE)) { + result = tonga_smu_start_in_non_protection_mode(adev); + if (result) + return result; + } else { + result = tonga_smu_start_in_protection_mode(adev); + if (result) + return result; + } + } + + return tonga_smu_request_load_fw(adev); +} + +static const struct amdgpu_smumgr_funcs tonga_smumgr_funcs = { + .check_fw_load_finish = tonga_smu_check_fw_load_finish, + .request_smu_load_fw = NULL, + .request_smu_specific_fw = NULL, +}; + +int tonga_smu_init(struct amdgpu_device *adev) +{ + struct tonga_smu_private_data *private; + uint32_t image_size = ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; + uint32_t smu_internal_buffer_size = 200*4096; + struct amdgpu_bo **toc_buf = &adev->smu.toc_buf; + struct amdgpu_bo **smu_buf = &adev->smu.smu_buf; + uint64_t mc_addr; + void *toc_buf_ptr; + void *smu_buf_ptr; + int ret; + + private = kzalloc(sizeof(struct tonga_smu_private_data), GFP_KERNEL); + if (NULL == private) + return -ENOMEM; + + /* allocate firmware buffers */ + if (adev->firmware.smu_load) + amdgpu_ucode_init_bo(adev); + + adev->smu.priv = private; + adev->smu.fw_flags = 0; + + /* Allocate FW image data structure and header buffer */ + ret = amdgpu_bo_create(adev, image_size, PAGE_SIZE, + true, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, toc_buf); + if (ret) { + DRM_ERROR("Failed to allocate memory for TOC buffer\n"); + return -ENOMEM; + } + + /* Allocate buffer for SMU internal buffer */ + ret = amdgpu_bo_create(adev, smu_internal_buffer_size, PAGE_SIZE, + true, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, smu_buf); + if (ret) { + DRM_ERROR("Failed to allocate memory for SMU internal buffer\n"); + return -ENOMEM; + } + + /* Retrieve GPU address for header buffer and internal buffer */ + ret = amdgpu_bo_reserve(adev->smu.toc_buf, false); + if (ret) { + amdgpu_bo_unref(&adev->smu.toc_buf); + DRM_ERROR("Failed to reserve the TOC buffer\n"); + return -EINVAL; + } + + ret = amdgpu_bo_pin(adev->smu.toc_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr); + if (ret) { + amdgpu_bo_unreserve(adev->smu.toc_buf); + amdgpu_bo_unref(&adev->smu.toc_buf); + DRM_ERROR("Failed to pin the TOC buffer\n"); + return -EINVAL; + } + + ret = amdgpu_bo_kmap(*toc_buf, &toc_buf_ptr); + if (ret) { + amdgpu_bo_unreserve(adev->smu.toc_buf); + amdgpu_bo_unref(&adev->smu.toc_buf); + DRM_ERROR("Failed to map the TOC buffer\n"); + return -EINVAL; + } + + amdgpu_bo_unreserve(adev->smu.toc_buf); + private->header_addr_low = lower_32_bits(mc_addr); + private->header_addr_high = upper_32_bits(mc_addr); + private->header = toc_buf_ptr; + + ret = amdgpu_bo_reserve(adev->smu.smu_buf, false); + if (ret) { + amdgpu_bo_unref(&adev->smu.smu_buf); + amdgpu_bo_unref(&adev->smu.toc_buf); + DRM_ERROR("Failed to reserve the SMU internal buffer\n"); + return -EINVAL; + } + + ret = amdgpu_bo_pin(adev->smu.smu_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr); + if (ret) { + amdgpu_bo_unreserve(adev->smu.smu_buf); + amdgpu_bo_unref(&adev->smu.smu_buf); + amdgpu_bo_unref(&adev->smu.toc_buf); + DRM_ERROR("Failed to pin the SMU internal buffer\n"); + return -EINVAL; + } + + ret = amdgpu_bo_kmap(*smu_buf, &smu_buf_ptr); + if (ret) { + amdgpu_bo_unreserve(adev->smu.smu_buf); + amdgpu_bo_unref(&adev->smu.smu_buf); + amdgpu_bo_unref(&adev->smu.toc_buf); + DRM_ERROR("Failed to map the SMU internal buffer\n"); + return -EINVAL; + } + + amdgpu_bo_unreserve(adev->smu.smu_buf); + private->smu_buffer_addr_low = lower_32_bits(mc_addr); + private->smu_buffer_addr_high = upper_32_bits(mc_addr); + + adev->smu.smumgr_funcs = &tonga_smumgr_funcs; + + return 0; +} + +int tonga_smu_fini(struct amdgpu_device *adev) +{ + amdgpu_bo_unref(&adev->smu.toc_buf); + amdgpu_bo_unref(&adev->smu.smu_buf); + kfree(adev->smu.priv); + adev->smu.priv = NULL; + if (adev->firmware.fw_buf) + amdgpu_ucode_fini_bo(adev); + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h b/drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h new file mode 100644 index 000000000000..c031ff99fe3e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/tonga_smumgr.h @@ -0,0 +1,42 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef TONGA_SMUMGR_H +#define TONGA_SMUMGR_H + +#include "tonga_ppsmc.h" + +int tonga_smu_init(struct amdgpu_device *adev); +int tonga_smu_fini(struct amdgpu_device *adev); +int tonga_smu_start(struct amdgpu_device *adev); + +struct tonga_smu_private_data +{ + uint8_t *header; + uint32_t smu_buffer_addr_high; + uint32_t smu_buffer_addr_low; + uint32_t header_addr_high; + uint32_t header_addr_low; +}; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c new file mode 100644 index 000000000000..f3b3026d5932 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -0,0 +1,830 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Christian König + */ + +#include +#include +#include "amdgpu.h" +#include "amdgpu_uvd.h" +#include "vid.h" +#include "uvd/uvd_5_0_d.h" +#include "uvd/uvd_5_0_sh_mask.h" +#include "oss/oss_2_0_d.h" +#include "oss/oss_2_0_sh_mask.h" + +static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); +static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); +static int uvd_v5_0_start(struct amdgpu_device *adev); +static void uvd_v5_0_stop(struct amdgpu_device *adev); + +/** + * uvd_v5_0_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32(mmUVD_RBC_RB_RPTR); +} + +/** + * uvd_v5_0_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32(mmUVD_RBC_RB_WPTR); +} + +/** + * uvd_v5_0_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); +} + +static int uvd_v5_0_early_init(struct amdgpu_device *adev) +{ + uvd_v5_0_set_ring_funcs(adev); + uvd_v5_0_set_irq_funcs(adev); + + return 0; +} + +static int uvd_v5_0_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + /* UVD TRAP */ + r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); + if (r) + return r; + + r = amdgpu_uvd_sw_init(adev); + if (r) + return r; + + r = amdgpu_uvd_resume(adev); + if (r) + return r; + + ring = &adev->uvd.ring; + sprintf(ring->name, "uvd"); + r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, + &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + + return r; +} + +static int uvd_v5_0_sw_fini(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_uvd_suspend(adev); + if (r) + return r; + + r = amdgpu_uvd_sw_fini(adev); + if (r) + return r; + + return r; +} + +/** + * uvd_v5_0_hw_init - start and test UVD block + * + * @adev: amdgpu_device pointer + * + * Initialize the hardware, boot up the VCPU and do some testing + */ +static int uvd_v5_0_hw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->uvd.ring; + uint32_t tmp; + int r; + + /* raise clocks while booting up the VCPU */ + amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); + + r = uvd_v5_0_start(adev); + if (r) + goto done; + + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + goto done; + } + + r = amdgpu_ring_lock(ring, 10); + if (r) { + DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); + goto done; + } + + tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + /* Clear timeout status bits */ + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); + amdgpu_ring_write(ring, 0x8); + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); + amdgpu_ring_write(ring, 3); + + amdgpu_ring_unlock_commit(ring); + +done: + /* lower clocks again */ + amdgpu_asic_set_uvd_clocks(adev, 0, 0); + + if (!r) + DRM_INFO("UVD initialized successfully.\n"); + + return r; +} + +/** + * uvd_v5_0_hw_fini - stop the hardware block + * + * @adev: amdgpu_device pointer + * + * Stop the UVD block, mark ring as not ready any more + */ +static int uvd_v5_0_hw_fini(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->uvd.ring; + + uvd_v5_0_stop(adev); + ring->ready = false; + + return 0; +} + +static int uvd_v5_0_suspend(struct amdgpu_device *adev) +{ + int r; + + r = uvd_v5_0_hw_fini(adev); + if (r) + return r; + + r = amdgpu_uvd_suspend(adev); + if (r) + return r; + + return r; +} + +static int uvd_v5_0_resume(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_uvd_resume(adev); + if (r) + return r; + + r = uvd_v5_0_hw_init(adev); + if (r) + return r; + + return r; +} + +/** + * uvd_v5_0_mc_resume - memory controller programming + * + * @adev: amdgpu_device pointer + * + * Let the UVD memory controller know it's offsets + */ +static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) +{ + uint64_t offset; + uint32_t size; + + /* programm memory controller bits 0-27 */ + WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, + lower_32_bits(adev->uvd.gpu_addr)); + WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, + upper_32_bits(adev->uvd.gpu_addr)); + + offset = AMDGPU_UVD_FIRMWARE_OFFSET; + size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); + WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); + WREG32(mmUVD_VCPU_CACHE_SIZE0, size); + + offset += size; + size = AMDGPU_UVD_STACK_SIZE; + WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); + WREG32(mmUVD_VCPU_CACHE_SIZE1, size); + + offset += size; + size = AMDGPU_UVD_HEAP_SIZE; + WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); + WREG32(mmUVD_VCPU_CACHE_SIZE2, size); +} + +/** + * uvd_v5_0_start - start UVD block + * + * @adev: amdgpu_device pointer + * + * Setup and start the UVD block + */ +static int uvd_v5_0_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->uvd.ring; + uint32_t rb_bufsz, tmp; + uint32_t lmi_swap_cntl; + uint32_t mp_swap_cntl; + int i, j, r; + + /*disable DPG */ + WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); + + /* disable byte swapping */ + lmi_swap_cntl = 0; + mp_swap_cntl = 0; + + uvd_v5_0_mc_resume(adev); + + /* disable clock gating */ + WREG32(mmUVD_CGC_GATE, 0); + + /* disable interupt */ + WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); + + /* stall UMC and register bus before resetting VCPU */ + WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); + mdelay(1); + + /* put LMI, VCPU, RBC etc... into reset */ + WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | + UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | + UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | + UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); + mdelay(5); + + /* take UVD block out of reset */ + WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); + mdelay(5); + + /* initialize UVD memory controller */ + WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | + (1 << 21) | (1 << 9) | (1 << 20)); + +#ifdef __BIG_ENDIAN + /* swap (8 in 32) RB and IB */ + lmi_swap_cntl = 0xa; + mp_swap_cntl = 0; +#endif + WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); + WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); + + WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); + WREG32(mmUVD_MPC_SET_MUXA1, 0x0); + WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); + WREG32(mmUVD_MPC_SET_MUXB1, 0x0); + WREG32(mmUVD_MPC_SET_ALU, 0); + WREG32(mmUVD_MPC_SET_MUX, 0x88); + + /* take all subblocks out of reset, except VCPU */ + WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(5); + + /* enable VCPU clock */ + WREG32(mmUVD_VCPU_CNTL, 1 << 9); + + /* enable UMC */ + WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); + + /* boot up the VCPU */ + WREG32(mmUVD_SOFT_RESET, 0); + mdelay(10); + + for (i = 0; i < 10; ++i) { + uint32_t status; + for (j = 0; j < 100; ++j) { + status = RREG32(mmUVD_STATUS); + if (status & 2) + break; + mdelay(10); + } + r = 0; + if (status & 2) + break; + + DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); + WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, + ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(10); + WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(10); + r = -1; + } + + if (r) { + DRM_ERROR("UVD not responding, giving up!!!\n"); + return r; + } + /* enable master interrupt */ + WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); + + /* clear the bit 4 of UVD_STATUS */ + WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); + + rb_bufsz = order_base_2(ring->ring_size); + tmp = 0; + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); + /* force RBC into idle state */ + WREG32(mmUVD_RBC_RB_CNTL, tmp); + + /* set the write pointer delay */ + WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); + + /* set the wb address */ + WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); + + /* programm the RB_BASE for ring buffer */ + WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, + lower_32_bits(ring->gpu_addr)); + WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, + upper_32_bits(ring->gpu_addr)); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(mmUVD_RBC_RB_RPTR, 0); + + ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); + WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); + + WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); + + return 0; +} + +/** + * uvd_v5_0_stop - stop UVD block + * + * @adev: amdgpu_device pointer + * + * stop the UVD block + */ +static void uvd_v5_0_stop(struct amdgpu_device *adev) +{ + /* force RBC into idle state */ + WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); + + /* Stall UMC and register bus before resetting VCPU */ + WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); + mdelay(1); + + /* put VCPU into reset */ + WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(5); + + /* disable VCPU clock */ + WREG32(mmUVD_VCPU_CNTL, 0x0); + + /* Unstall UMC and register bus */ + WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); +} + +/** + * uvd_v5_0_ring_emit_fence - emit an fence & trap command + * + * @ring: amdgpu_ring pointer + * @fence: fence to emit + * + * Write a fence and a trap command to the ring. + */ +static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + bool write64bit) +{ + WARN_ON(write64bit); + + amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); + amdgpu_ring_write(ring, seq); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); + amdgpu_ring_write(ring, addr & 0xffffffff); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); + amdgpu_ring_write(ring, 2); +} + +/** + * uvd_v5_0_ring_emit_semaphore - emit semaphore command + * + * @ring: amdgpu_ring pointer + * @semaphore: semaphore to emit commands for + * @emit_wait: true if we should emit a wait command + * + * Emit a semaphore command (either wait or signal) to the UVD ring. + */ +static bool uvd_v5_0_ring_emit_semaphore(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore, + bool emit_wait) +{ + uint64_t addr = semaphore->gpu_addr; + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0)); + amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0)); + amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0)); + amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); + + return true; +} + +/** + * uvd_v5_0_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer + * + * Test if we can successfully write to the context register + */ +static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t tmp = 0; + unsigned i; + int r; + + WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); + r = amdgpu_ring_lock(ring, 3); + if (r) { + DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", + ring->idx, r); + return r; + } + amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_unlock_commit(ring); + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(mmUVD_CONTEXT_ID); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", + ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", + ring->idx, tmp); + r = -EINVAL; + } + return r; +} + +/** + * uvd_v5_0_ring_emit_ib - execute indirect buffer + * + * @ring: amdgpu_ring pointer + * @ib: indirect buffer to execute + * + * Write ring commands to execute the indirect buffer + */ +static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib) +{ + amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); + amdgpu_ring_write(ring, ib->length_dw); +} + +/** + * uvd_v5_0_ring_test_ib - test ib execution + * + * @ring: amdgpu_ring pointer + * + * Test if we can successfully execute an IB + */ +static int uvd_v5_0_ring_test_ib(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_fence *fence = NULL; + int r; + + r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); + if (r) { + DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r); + return r; + } + + r = amdgpu_uvd_get_create_msg(ring, 1, NULL); + if (r) { + DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); + goto error; + } + + r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence); + if (r) { + DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); + goto error; + } + + r = amdgpu_fence_wait(fence, false); + if (r) { + DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + goto error; + } + DRM_INFO("ib test on ring %d succeeded\n", ring->idx); +error: + amdgpu_fence_unref(&fence); + amdgpu_asic_set_uvd_clocks(adev, 0, 0); + return r; +} + +static bool uvd_v5_0_is_idle(struct amdgpu_device *adev) +{ + return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); +} + +static int uvd_v5_0_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) + return 0; + } + return -ETIMEDOUT; +} + +static int uvd_v5_0_soft_reset(struct amdgpu_device *adev) +{ + uvd_v5_0_stop(adev); + + WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, + ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); + mdelay(5); + + return uvd_v5_0_start(adev); +} + +static void uvd_v5_0_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "UVD 5.0 registers\n"); + dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", + RREG32(mmUVD_SEMA_ADDR_LOW)); + dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", + RREG32(mmUVD_SEMA_ADDR_HIGH)); + dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", + RREG32(mmUVD_SEMA_CMD)); + dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", + RREG32(mmUVD_GPCOM_VCPU_CMD)); + dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", + RREG32(mmUVD_GPCOM_VCPU_DATA0)); + dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", + RREG32(mmUVD_GPCOM_VCPU_DATA1)); + dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", + RREG32(mmUVD_ENGINE_CNTL)); + dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_CNTL)); + dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", + RREG32(mmUVD_LMI_EXT40_ADDR)); + dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", + RREG32(mmUVD_CTX_INDEX)); + dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", + RREG32(mmUVD_CTX_DATA)); + dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", + RREG32(mmUVD_CGC_GATE)); + dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", + RREG32(mmUVD_CGC_CTRL)); + dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", + RREG32(mmUVD_LMI_CTRL2)); + dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", + RREG32(mmUVD_MASTINT_EN)); + dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", + RREG32(mmUVD_LMI_ADDR_EXT)); + dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", + RREG32(mmUVD_LMI_CTRL)); + dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", + RREG32(mmUVD_LMI_SWAP_CNTL)); + dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", + RREG32(mmUVD_MP_SWAP_CNTL)); + dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXA0)); + dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXA1)); + dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXB0)); + dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXB1)); + dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUX)); + dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", + RREG32(mmUVD_MPC_SET_ALU)); + dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_OFFSET0)); + dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_SIZE0)); + dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_OFFSET1)); + dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_SIZE1)); + dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_OFFSET2)); + dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_SIZE2)); + dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", + RREG32(mmUVD_VCPU_CNTL)); + dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", + RREG32(mmUVD_SOFT_RESET)); + dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n", + RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW)); + dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n", + RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH)); + dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", + RREG32(mmUVD_RBC_IB_SIZE)); + dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n", + RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW)); + dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n", + RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH)); + dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", + RREG32(mmUVD_RBC_RB_RPTR)); + dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", + RREG32(mmUVD_RBC_RB_WPTR)); + dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", + RREG32(mmUVD_RBC_RB_WPTR_CNTL)); + dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", + RREG32(mmUVD_RBC_RB_CNTL)); + dev_info(adev->dev, " UVD_STATUS=0x%08X\n", + RREG32(mmUVD_STATUS)); + dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", + RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); + dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); + dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); + dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); + dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", + RREG32(mmUVD_CONTEXT_ID)); +} + +static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + // TODO + return 0; +} + +static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_DEBUG("IH: UVD TRAP\n"); + amdgpu_fence_process(&adev->uvd.ring); + return 0; +} + +static int uvd_v5_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + //TODO + + return 0; +} + +static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + /* This doesn't actually powergate the UVD block. + * That's done in the dpm code via the SMC. This + * just re-inits the block as necessary. The actual + * gating still happens in the dpm code. We should + * revisit this when there is a cleaner line between + * the smc and the hw blocks + */ + if (state == AMDGPU_PG_STATE_GATE) { + uvd_v5_0_stop(adev); + return 0; + } else { + return uvd_v5_0_start(adev); + } +} + +const struct amdgpu_ip_funcs uvd_v5_0_ip_funcs = { + .early_init = uvd_v5_0_early_init, + .late_init = NULL, + .sw_init = uvd_v5_0_sw_init, + .sw_fini = uvd_v5_0_sw_fini, + .hw_init = uvd_v5_0_hw_init, + .hw_fini = uvd_v5_0_hw_fini, + .suspend = uvd_v5_0_suspend, + .resume = uvd_v5_0_resume, + .is_idle = uvd_v5_0_is_idle, + .wait_for_idle = uvd_v5_0_wait_for_idle, + .soft_reset = uvd_v5_0_soft_reset, + .print_status = uvd_v5_0_print_status, + .set_clockgating_state = uvd_v5_0_set_clockgating_state, + .set_powergating_state = uvd_v5_0_set_powergating_state, +}; + +static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { + .get_rptr = uvd_v5_0_ring_get_rptr, + .get_wptr = uvd_v5_0_ring_get_wptr, + .set_wptr = uvd_v5_0_ring_set_wptr, + .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_ib = uvd_v5_0_ring_emit_ib, + .emit_fence = uvd_v5_0_ring_emit_fence, + .emit_semaphore = uvd_v5_0_ring_emit_semaphore, + .test_ring = uvd_v5_0_ring_test_ring, + .test_ib = uvd_v5_0_ring_test_ib, + .is_lockup = amdgpu_ring_test_lockup, +}; + +static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) +{ + adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs; +} + +static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { + .set = uvd_v5_0_set_interrupt_state, + .process = uvd_v5_0_process_interrupt, +}; + +static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->uvd.irq.num_types = 1; + adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h new file mode 100644 index 000000000000..7d7a15296383 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __UVD_V5_0_H__ +#define __UVD_V5_0_H__ + +extern const struct amdgpu_ip_funcs uvd_v5_0_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c new file mode 100644 index 000000000000..f59942d5c50e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -0,0 +1,810 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Christian König + */ + +#include +#include +#include "amdgpu.h" +#include "amdgpu_uvd.h" +#include "vid.h" +#include "uvd/uvd_6_0_d.h" +#include "uvd/uvd_6_0_sh_mask.h" +#include "oss/oss_2_0_d.h" +#include "oss/oss_2_0_sh_mask.h" + +static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev); +static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev); +static int uvd_v6_0_start(struct amdgpu_device *adev); +static void uvd_v6_0_stop(struct amdgpu_device *adev); + +/** + * uvd_v6_0_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32(mmUVD_RBC_RB_RPTR); +} + +/** + * uvd_v6_0_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32(mmUVD_RBC_RB_WPTR); +} + +/** + * uvd_v6_0_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); +} + +static int uvd_v6_0_early_init(struct amdgpu_device *adev) +{ + uvd_v6_0_set_ring_funcs(adev); + uvd_v6_0_set_irq_funcs(adev); + + return 0; +} + +static int uvd_v6_0_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + /* UVD TRAP */ + r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); + if (r) + return r; + + r = amdgpu_uvd_sw_init(adev); + if (r) + return r; + + r = amdgpu_uvd_resume(adev); + if (r) + return r; + + ring = &adev->uvd.ring; + sprintf(ring->name, "uvd"); + r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, + &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + + return r; +} + +static int uvd_v6_0_sw_fini(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_uvd_suspend(adev); + if (r) + return r; + + r = amdgpu_uvd_sw_fini(adev); + if (r) + return r; + + return r; +} + +/** + * uvd_v6_0_hw_init - start and test UVD block + * + * @adev: amdgpu_device pointer + * + * Initialize the hardware, boot up the VCPU and do some testing + */ +static int uvd_v6_0_hw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->uvd.ring; + uint32_t tmp; + int r; + + r = uvd_v6_0_start(adev); + if (r) + goto done; + + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + goto done; + } + + r = amdgpu_ring_lock(ring, 10); + if (r) { + DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); + goto done; + } + + tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0xFFFFF); + + /* Clear timeout status bits */ + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); + amdgpu_ring_write(ring, 0x8); + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); + amdgpu_ring_write(ring, 3); + + amdgpu_ring_unlock_commit(ring); + +done: + if (!r) + DRM_INFO("UVD initialized successfully.\n"); + + return r; +} + +/** + * uvd_v6_0_hw_fini - stop the hardware block + * + * @adev: amdgpu_device pointer + * + * Stop the UVD block, mark ring as not ready any more + */ +static int uvd_v6_0_hw_fini(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->uvd.ring; + + uvd_v6_0_stop(adev); + ring->ready = false; + + return 0; +} + +static int uvd_v6_0_suspend(struct amdgpu_device *adev) +{ + int r; + + r = uvd_v6_0_hw_fini(adev); + if (r) + return r; + + r = amdgpu_uvd_suspend(adev); + if (r) + return r; + + return r; +} + +static int uvd_v6_0_resume(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_uvd_resume(adev); + if (r) + return r; + + r = uvd_v6_0_hw_init(adev); + if (r) + return r; + + return r; +} + +/** + * uvd_v6_0_mc_resume - memory controller programming + * + * @adev: amdgpu_device pointer + * + * Let the UVD memory controller know it's offsets + */ +static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) +{ + uint64_t offset; + uint32_t size; + + /* programm memory controller bits 0-27 */ + WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, + lower_32_bits(adev->uvd.gpu_addr)); + WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, + upper_32_bits(adev->uvd.gpu_addr)); + + offset = AMDGPU_UVD_FIRMWARE_OFFSET; + size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); + WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); + WREG32(mmUVD_VCPU_CACHE_SIZE0, size); + + offset += size; + size = AMDGPU_UVD_STACK_SIZE; + WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); + WREG32(mmUVD_VCPU_CACHE_SIZE1, size); + + offset += size; + size = AMDGPU_UVD_HEAP_SIZE; + WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); + WREG32(mmUVD_VCPU_CACHE_SIZE2, size); +} + +/** + * uvd_v6_0_start - start UVD block + * + * @adev: amdgpu_device pointer + * + * Setup and start the UVD block + */ +static int uvd_v6_0_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = &adev->uvd.ring; + uint32_t rb_bufsz, tmp; + uint32_t lmi_swap_cntl; + uint32_t mp_swap_cntl; + int i, j, r; + + /*disable DPG */ + WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); + + /* disable byte swapping */ + lmi_swap_cntl = 0; + mp_swap_cntl = 0; + + uvd_v6_0_mc_resume(adev); + + /* disable clock gating */ + WREG32(mmUVD_CGC_GATE, 0); + + /* disable interupt */ + WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); + + /* stall UMC and register bus before resetting VCPU */ + WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); + mdelay(1); + + /* put LMI, VCPU, RBC etc... into reset */ + WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | + UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | + UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | + UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | + UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); + mdelay(5); + + /* take UVD block out of reset */ + WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); + mdelay(5); + + /* initialize UVD memory controller */ + WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | + (1 << 21) | (1 << 9) | (1 << 20)); + +#ifdef __BIG_ENDIAN + /* swap (8 in 32) RB and IB */ + lmi_swap_cntl = 0xa; + mp_swap_cntl = 0; +#endif + WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); + WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); + + WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); + WREG32(mmUVD_MPC_SET_MUXA1, 0x0); + WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); + WREG32(mmUVD_MPC_SET_MUXB1, 0x0); + WREG32(mmUVD_MPC_SET_ALU, 0); + WREG32(mmUVD_MPC_SET_MUX, 0x88); + + /* take all subblocks out of reset, except VCPU */ + WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(5); + + /* enable VCPU clock */ + WREG32(mmUVD_VCPU_CNTL, 1 << 9); + + /* enable UMC */ + WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); + + /* boot up the VCPU */ + WREG32(mmUVD_SOFT_RESET, 0); + mdelay(10); + + for (i = 0; i < 10; ++i) { + uint32_t status; + + for (j = 0; j < 100; ++j) { + status = RREG32(mmUVD_STATUS); + if (status & 2) + break; + mdelay(10); + } + r = 0; + if (status & 2) + break; + + DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); + WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, + ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(10); + WREG32_P(mmUVD_SOFT_RESET, 0, + ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(10); + r = -1; + } + + if (r) { + DRM_ERROR("UVD not responding, giving up!!!\n"); + return r; + } + /* enable master interrupt */ + WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); + + /* clear the bit 4 of UVD_STATUS */ + WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); + + rb_bufsz = order_base_2(ring->ring_size); + tmp = 0; + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); + /* force RBC into idle state */ + WREG32(mmUVD_RBC_RB_CNTL, tmp); + + /* set the write pointer delay */ + WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); + + /* set the wb address */ + WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); + + /* programm the RB_BASE for ring buffer */ + WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, + lower_32_bits(ring->gpu_addr)); + WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, + upper_32_bits(ring->gpu_addr)); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(mmUVD_RBC_RB_RPTR, 0); + + ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); + WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); + + WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); + + return 0; +} + +/** + * uvd_v6_0_stop - stop UVD block + * + * @adev: amdgpu_device pointer + * + * stop the UVD block + */ +static void uvd_v6_0_stop(struct amdgpu_device *adev) +{ + /* force RBC into idle state */ + WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); + + /* Stall UMC and register bus before resetting VCPU */ + WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); + mdelay(1); + + /* put VCPU into reset */ + WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); + mdelay(5); + + /* disable VCPU clock */ + WREG32(mmUVD_VCPU_CNTL, 0x0); + + /* Unstall UMC and register bus */ + WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); +} + +/** + * uvd_v6_0_ring_emit_fence - emit an fence & trap command + * + * @ring: amdgpu_ring pointer + * @fence: fence to emit + * + * Write a fence and a trap command to the ring. + */ +static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + bool write64bit) +{ + WARN_ON(write64bit); + + amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); + amdgpu_ring_write(ring, seq); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); + amdgpu_ring_write(ring, addr & 0xffffffff); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); + amdgpu_ring_write(ring, 0); + + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); + amdgpu_ring_write(ring, 2); +} + +/** + * uvd_v6_0_ring_emit_semaphore - emit semaphore command + * + * @ring: amdgpu_ring pointer + * @semaphore: semaphore to emit commands for + * @emit_wait: true if we should emit a wait command + * + * Emit a semaphore command (either wait or signal) to the UVD ring. + */ +static bool uvd_v6_0_ring_emit_semaphore(struct amdgpu_ring *ring, + struct amdgpu_semaphore *semaphore, + bool emit_wait) +{ + uint64_t addr = semaphore->gpu_addr; + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0)); + amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0)); + amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); + + amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0)); + amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); + + return true; +} + +/** + * uvd_v6_0_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer + * + * Test if we can successfully write to the context register + */ +static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t tmp = 0; + unsigned i; + int r; + + WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); + r = amdgpu_ring_lock(ring, 3); + if (r) { + DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", + ring->idx, r); + return r; + } + amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_unlock_commit(ring); + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(mmUVD_CONTEXT_ID); + if (tmp == 0xDEADBEEF) + break; + DRM_UDELAY(1); + } + + if (i < adev->usec_timeout) { + DRM_INFO("ring test on %d succeeded in %d usecs\n", + ring->idx, i); + } else { + DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", + ring->idx, tmp); + r = -EINVAL; + } + return r; +} + +/** + * uvd_v6_0_ring_emit_ib - execute indirect buffer + * + * @ring: amdgpu_ring pointer + * @ib: indirect buffer to execute + * + * Write ring commands to execute the indirect buffer + */ +static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib) +{ + amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); + amdgpu_ring_write(ring, ib->length_dw); +} + +/** + * uvd_v6_0_ring_test_ib - test ib execution + * + * @ring: amdgpu_ring pointer + * + * Test if we can successfully execute an IB + */ +static int uvd_v6_0_ring_test_ib(struct amdgpu_ring *ring) +{ + struct amdgpu_fence *fence = NULL; + int r; + + r = amdgpu_uvd_get_create_msg(ring, 1, NULL); + if (r) { + DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); + goto error; + } + + r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence); + if (r) { + DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); + goto error; + } + + r = amdgpu_fence_wait(fence, false); + if (r) { + DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + goto error; + } + DRM_INFO("ib test on ring %d succeeded\n", ring->idx); +error: + amdgpu_fence_unref(&fence); + return r; +} + +static bool uvd_v6_0_is_idle(struct amdgpu_device *adev) +{ + return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); +} + +static int uvd_v6_0_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) + return 0; + } + return -ETIMEDOUT; +} + +static int uvd_v6_0_soft_reset(struct amdgpu_device *adev) +{ + uvd_v6_0_stop(adev); + + WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, + ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); + mdelay(5); + + return uvd_v6_0_start(adev); +} + +static void uvd_v6_0_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "UVD 6.0 registers\n"); + dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", + RREG32(mmUVD_SEMA_ADDR_LOW)); + dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", + RREG32(mmUVD_SEMA_ADDR_HIGH)); + dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", + RREG32(mmUVD_SEMA_CMD)); + dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", + RREG32(mmUVD_GPCOM_VCPU_CMD)); + dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", + RREG32(mmUVD_GPCOM_VCPU_DATA0)); + dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", + RREG32(mmUVD_GPCOM_VCPU_DATA1)); + dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", + RREG32(mmUVD_ENGINE_CNTL)); + dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", + RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); + dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_CNTL)); + dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", + RREG32(mmUVD_LMI_EXT40_ADDR)); + dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", + RREG32(mmUVD_CTX_INDEX)); + dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", + RREG32(mmUVD_CTX_DATA)); + dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", + RREG32(mmUVD_CGC_GATE)); + dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", + RREG32(mmUVD_CGC_CTRL)); + dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", + RREG32(mmUVD_LMI_CTRL2)); + dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", + RREG32(mmUVD_MASTINT_EN)); + dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", + RREG32(mmUVD_LMI_ADDR_EXT)); + dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", + RREG32(mmUVD_LMI_CTRL)); + dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", + RREG32(mmUVD_LMI_SWAP_CNTL)); + dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", + RREG32(mmUVD_MP_SWAP_CNTL)); + dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXA0)); + dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXA1)); + dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXB0)); + dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUXB1)); + dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", + RREG32(mmUVD_MPC_SET_MUX)); + dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", + RREG32(mmUVD_MPC_SET_ALU)); + dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_OFFSET0)); + dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_SIZE0)); + dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_OFFSET1)); + dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_SIZE1)); + dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_OFFSET2)); + dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", + RREG32(mmUVD_VCPU_CACHE_SIZE2)); + dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", + RREG32(mmUVD_VCPU_CNTL)); + dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", + RREG32(mmUVD_SOFT_RESET)); + dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", + RREG32(mmUVD_RBC_IB_SIZE)); + dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", + RREG32(mmUVD_RBC_RB_RPTR)); + dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", + RREG32(mmUVD_RBC_RB_WPTR)); + dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", + RREG32(mmUVD_RBC_RB_WPTR_CNTL)); + dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", + RREG32(mmUVD_RBC_RB_CNTL)); + dev_info(adev->dev, " UVD_STATUS=0x%08X\n", + RREG32(mmUVD_STATUS)); + dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", + RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); + dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); + dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); + dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", + RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); + dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", + RREG32(mmUVD_CONTEXT_ID)); +} + +static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + // TODO + return 0; +} + +static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_DEBUG("IH: UVD TRAP\n"); + amdgpu_fence_process(&adev->uvd.ring); + return 0; +} + +static int uvd_v6_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + //TODO + + return 0; +} + +static int uvd_v6_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + /* This doesn't actually powergate the UVD block. + * That's done in the dpm code via the SMC. This + * just re-inits the block as necessary. The actual + * gating still happens in the dpm code. We should + * revisit this when there is a cleaner line between + * the smc and the hw blocks + */ + if (state == AMDGPU_PG_STATE_GATE) { + uvd_v6_0_stop(adev); + return 0; + } else { + return uvd_v6_0_start(adev); + } +} + +const struct amdgpu_ip_funcs uvd_v6_0_ip_funcs = { + .early_init = uvd_v6_0_early_init, + .late_init = NULL, + .sw_init = uvd_v6_0_sw_init, + .sw_fini = uvd_v6_0_sw_fini, + .hw_init = uvd_v6_0_hw_init, + .hw_fini = uvd_v6_0_hw_fini, + .suspend = uvd_v6_0_suspend, + .resume = uvd_v6_0_resume, + .is_idle = uvd_v6_0_is_idle, + .wait_for_idle = uvd_v6_0_wait_for_idle, + .soft_reset = uvd_v6_0_soft_reset, + .print_status = uvd_v6_0_print_status, + .set_clockgating_state = uvd_v6_0_set_clockgating_state, + .set_powergating_state = uvd_v6_0_set_powergating_state, +}; + +static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = { + .get_rptr = uvd_v6_0_ring_get_rptr, + .get_wptr = uvd_v6_0_ring_get_wptr, + .set_wptr = uvd_v6_0_ring_set_wptr, + .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_ib = uvd_v6_0_ring_emit_ib, + .emit_fence = uvd_v6_0_ring_emit_fence, + .emit_semaphore = uvd_v6_0_ring_emit_semaphore, + .test_ring = uvd_v6_0_ring_test_ring, + .test_ib = uvd_v6_0_ring_test_ib, + .is_lockup = amdgpu_ring_test_lockup, +}; + +static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) +{ + adev->uvd.ring.funcs = &uvd_v6_0_ring_funcs; +} + +static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = { + .set = uvd_v6_0_set_interrupt_state, + .process = uvd_v6_0_process_interrupt, +}; + +static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->uvd.irq.num_types = 1; + adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h new file mode 100644 index 000000000000..bc21afc8abac --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __UVD_V6_0_H__ +#define __UVD_V6_0_H__ + +extern const struct amdgpu_ip_funcs uvd_v6_0_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c new file mode 100644 index 000000000000..384c45e74053 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -0,0 +1,521 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * Authors: Christian König + */ + +#include +#include +#include "amdgpu.h" +#include "amdgpu_vce.h" +#include "vid.h" +#include "vce/vce_3_0_d.h" +#include "vce/vce_3_0_sh_mask.h" +#include "oss/oss_2_0_d.h" +#include "oss/oss_2_0_sh_mask.h" + +static void vce_v3_0_mc_resume(struct amdgpu_device *adev); +static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); +static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); + +/** + * vce_v3_0_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->vce.ring[0]) + return RREG32(mmVCE_RB_RPTR); + else + return RREG32(mmVCE_RB_RPTR2); +} + +/** + * vce_v3_0_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->vce.ring[0]) + return RREG32(mmVCE_RB_WPTR); + else + return RREG32(mmVCE_RB_WPTR2); +} + +/** + * vce_v3_0_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring == &adev->vce.ring[0]) + WREG32(mmVCE_RB_WPTR, ring->wptr); + else + WREG32(mmVCE_RB_WPTR2, ring->wptr); +} + +/** + * vce_v3_0_start - start VCE block + * + * @adev: amdgpu_device pointer + * + * Setup and start the VCE block + */ +static int vce_v3_0_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int i, j, r; + + vce_v3_0_mc_resume(adev); + + /* set BUSY flag */ + WREG32_P(mmVCE_STATUS, 1, ~1); + + ring = &adev->vce.ring[0]; + WREG32(mmVCE_RB_RPTR, ring->wptr); + WREG32(mmVCE_RB_WPTR, ring->wptr); + WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); + WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); + + ring = &adev->vce.ring[1]; + WREG32(mmVCE_RB_RPTR2, ring->wptr); + WREG32(mmVCE_RB_WPTR2, ring->wptr); + WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); + WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); + WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); + + WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK); + + WREG32_P(mmVCE_SOFT_RESET, + VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + + mdelay(100); + + WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + + for (i = 0; i < 10; ++i) { + uint32_t status; + for (j = 0; j < 100; ++j) { + status = RREG32(mmVCE_STATUS); + if (status & 2) + break; + mdelay(10); + } + r = 0; + if (status & 2) + break; + + DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n"); + WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(10); + WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(10); + r = -1; + } + + /* clear BUSY flag */ + WREG32_P(mmVCE_STATUS, 0, ~1); + + if (r) { + DRM_ERROR("VCE not responding, giving up!!!\n"); + return r; + } + + return 0; +} + +static int vce_v3_0_early_init(struct amdgpu_device *adev) +{ + vce_v3_0_set_ring_funcs(adev); + vce_v3_0_set_irq_funcs(adev); + + return 0; +} + +static int vce_v3_0_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + /* VCE */ + r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq); + if (r) + return r; + + r = amdgpu_vce_sw_init(adev); + if (r) + return r; + + r = amdgpu_vce_resume(adev); + if (r) + return r; + + ring = &adev->vce.ring[0]; + sprintf(ring->name, "vce0"); + r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, + &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); + if (r) + return r; + + ring = &adev->vce.ring[1]; + sprintf(ring->name, "vce1"); + r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf, + &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); + if (r) + return r; + + return r; +} + +static int vce_v3_0_sw_fini(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_vce_suspend(adev); + if (r) + return r; + + r = amdgpu_vce_sw_fini(adev); + if (r) + return r; + + return r; +} + +static int vce_v3_0_hw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + r = vce_v3_0_start(adev); + if (r) + return r; + + ring = &adev->vce.ring[0]; + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + return r; + } + + ring = &adev->vce.ring[1]; + ring->ready = true; + r = amdgpu_ring_test_ring(ring); + if (r) { + ring->ready = false; + return r; + } + + DRM_INFO("VCE initialized successfully.\n"); + + return 0; +} + +static int vce_v3_0_hw_fini(struct amdgpu_device *adev) +{ + // TODO + return 0; +} + +static int vce_v3_0_suspend(struct amdgpu_device *adev) +{ + int r; + + r = vce_v3_0_hw_fini(adev); + if (r) + return r; + + r = amdgpu_vce_suspend(adev); + if (r) + return r; + + return r; +} + +static int vce_v3_0_resume(struct amdgpu_device *adev) +{ + int r; + + r = amdgpu_vce_resume(adev); + if (r) + return r; + + r = vce_v3_0_hw_init(adev); + if (r) + return r; + + return r; +} + +static void vce_v3_0_mc_resume(struct amdgpu_device *adev) +{ + uint32_t offset, size; + + WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); + WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); + WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); + WREG32(mmVCE_CLOCK_GATING_B, 0xf7); + + WREG32(mmVCE_LMI_CTRL, 0x00398000); + WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); + WREG32(mmVCE_LMI_SWAP_CNTL, 0); + WREG32(mmVCE_LMI_SWAP_CNTL1, 0); + WREG32(mmVCE_LMI_VM_CTRL, 0); + + WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); + offset = AMDGPU_VCE_FIRMWARE_OFFSET; + size = AMDGPU_GPU_PAGE_ALIGN(adev->vce.fw->size); + WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE0, size); + + offset += size; + size = AMDGPU_VCE_STACK_SIZE; + WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE1, size); + + offset += size; + size = AMDGPU_VCE_HEAP_SIZE; + WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE2, size); + + WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); + + WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK, + ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); +} + +static bool vce_v3_0_is_idle(struct amdgpu_device *adev) +{ + return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); +} + +static int vce_v3_0_wait_for_idle(struct amdgpu_device *adev) +{ + unsigned i; + + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK)) + return 0; + } + return -ETIMEDOUT; +} + +static int vce_v3_0_soft_reset(struct amdgpu_device *adev) +{ + WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK, + ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK); + mdelay(5); + + return vce_v3_0_start(adev); +} + +static void vce_v3_0_print_status(struct amdgpu_device *adev) +{ + dev_info(adev->dev, "VCE 3.0 registers\n"); + dev_info(adev->dev, " VCE_STATUS=0x%08X\n", + RREG32(mmVCE_STATUS)); + dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n", + RREG32(mmVCE_VCPU_CNTL)); + dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_OFFSET0)); + dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_SIZE0)); + dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_OFFSET1)); + dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_SIZE1)); + dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_OFFSET2)); + dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n", + RREG32(mmVCE_VCPU_CACHE_SIZE2)); + dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n", + RREG32(mmVCE_SOFT_RESET)); + dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n", + RREG32(mmVCE_RB_BASE_LO2)); + dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n", + RREG32(mmVCE_RB_BASE_HI2)); + dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n", + RREG32(mmVCE_RB_SIZE2)); + dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n", + RREG32(mmVCE_RB_RPTR2)); + dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n", + RREG32(mmVCE_RB_WPTR2)); + dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n", + RREG32(mmVCE_RB_BASE_LO)); + dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n", + RREG32(mmVCE_RB_BASE_HI)); + dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n", + RREG32(mmVCE_RB_SIZE)); + dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n", + RREG32(mmVCE_RB_RPTR)); + dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n", + RREG32(mmVCE_RB_WPTR)); + dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n", + RREG32(mmVCE_CLOCK_GATING_A)); + dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n", + RREG32(mmVCE_CLOCK_GATING_B)); + dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n", + RREG32(mmVCE_UENC_CLOCK_GATING)); + dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n", + RREG32(mmVCE_UENC_REG_CLOCK_GATING)); + dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n", + RREG32(mmVCE_SYS_INT_EN)); + dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n", + RREG32(mmVCE_LMI_CTRL2)); + dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n", + RREG32(mmVCE_LMI_CTRL)); + dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n", + RREG32(mmVCE_LMI_VM_CTRL)); + dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n", + RREG32(mmVCE_LMI_SWAP_CNTL)); + dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n", + RREG32(mmVCE_LMI_SWAP_CNTL1)); + dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n", + RREG32(mmVCE_LMI_CACHE_CTRL)); +} + +static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + uint32_t val = 0; + + if (state == AMDGPU_IRQ_STATE_ENABLE) + val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; + + WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); + return 0; +} + +static int vce_v3_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_DEBUG("IH: VCE\n"); + switch (entry->src_data) { + case 0: + amdgpu_fence_process(&adev->vce.ring[0]); + break; + case 1: + amdgpu_fence_process(&adev->vce.ring[1]); + break; + default: + DRM_ERROR("Unhandled interrupt: %d %d\n", + entry->src_id, entry->src_data); + break; + } + + return 0; +} + +static int vce_v3_0_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + //TODO + return 0; +} + +static int vce_v3_0_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + /* This doesn't actually powergate the VCE block. + * That's done in the dpm code via the SMC. This + * just re-inits the block as necessary. The actual + * gating still happens in the dpm code. We should + * revisit this when there is a cleaner line between + * the smc and the hw blocks + */ + if (state == AMDGPU_PG_STATE_GATE) + /* XXX do we need a vce_v3_0_stop()? */ + return 0; + else + return vce_v3_0_start(adev); +} + +const struct amdgpu_ip_funcs vce_v3_0_ip_funcs = { + .early_init = vce_v3_0_early_init, + .late_init = NULL, + .sw_init = vce_v3_0_sw_init, + .sw_fini = vce_v3_0_sw_fini, + .hw_init = vce_v3_0_hw_init, + .hw_fini = vce_v3_0_hw_fini, + .suspend = vce_v3_0_suspend, + .resume = vce_v3_0_resume, + .is_idle = vce_v3_0_is_idle, + .wait_for_idle = vce_v3_0_wait_for_idle, + .soft_reset = vce_v3_0_soft_reset, + .print_status = vce_v3_0_print_status, + .set_clockgating_state = vce_v3_0_set_clockgating_state, + .set_powergating_state = vce_v3_0_set_powergating_state, +}; + +static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = { + .get_rptr = vce_v3_0_ring_get_rptr, + .get_wptr = vce_v3_0_ring_get_wptr, + .set_wptr = vce_v3_0_ring_set_wptr, + .parse_cs = amdgpu_vce_ring_parse_cs, + .emit_ib = amdgpu_vce_ring_emit_ib, + .emit_fence = amdgpu_vce_ring_emit_fence, + .emit_semaphore = amdgpu_vce_ring_emit_semaphore, + .test_ring = amdgpu_vce_ring_test_ring, + .test_ib = amdgpu_vce_ring_test_ib, + .is_lockup = amdgpu_ring_test_lockup, +}; + +static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev) +{ + adev->vce.ring[0].funcs = &vce_v3_0_ring_funcs; + adev->vce.ring[1].funcs = &vce_v3_0_ring_funcs; +} + +static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = { + .set = vce_v3_0_set_interrupt_state, + .process = vce_v3_0_process_interrupt, +}; + +static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->vce.irq.num_types = 1; + adev->vce.irq.funcs = &vce_v3_0_irq_funcs; +}; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h new file mode 100644 index 000000000000..f3c2ba92a1f1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VCE_V3_0_H__ +#define __VCE_V3_0_H__ + +extern const struct amdgpu_ip_funcs vce_v3_0_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c new file mode 100644 index 000000000000..20a159803983 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -0,0 +1,1373 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include +#include +#include "drmP.h" +#include "amdgpu.h" +#include "amdgpu_atombios.h" +#include "amdgpu_ih.h" +#include "amdgpu_uvd.h" +#include "amdgpu_vce.h" +#include "amdgpu_ucode.h" +#include "atom.h" + +#include "gmc/gmc_8_1_d.h" +#include "gmc/gmc_8_1_sh_mask.h" + +#include "oss/oss_3_0_d.h" +#include "oss/oss_3_0_sh_mask.h" + +#include "bif/bif_5_0_d.h" +#include "bif/bif_5_0_sh_mask.h" + +#include "gca/gfx_8_0_d.h" +#include "gca/gfx_8_0_sh_mask.h" + +#include "smu/smu_7_1_1_d.h" +#include "smu/smu_7_1_1_sh_mask.h" + +#include "uvd/uvd_5_0_d.h" +#include "uvd/uvd_5_0_sh_mask.h" + +#include "vce/vce_3_0_d.h" +#include "vce/vce_3_0_sh_mask.h" + +#include "dce/dce_10_0_d.h" +#include "dce/dce_10_0_sh_mask.h" + +#include "vid.h" +#include "vi.h" +#include "vi_dpm.h" +#include "gmc_v8_0.h" +#include "gfx_v8_0.h" +#include "sdma_v2_4.h" +#include "sdma_v3_0.h" +#include "dce_v10_0.h" +#include "dce_v11_0.h" +#include "iceland_ih.h" +#include "tonga_ih.h" +#include "cz_ih.h" +#include "uvd_v5_0.h" +#include "uvd_v6_0.h" +#include "vce_v3_0.h" + +/* + * Indirect registers accessor + */ +static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + WREG32(mmPCIE_INDEX, reg); + (void)RREG32(mmPCIE_INDEX); + r = RREG32(mmPCIE_DATA); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + return r; +} + +static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&adev->pcie_idx_lock, flags); + WREG32(mmPCIE_INDEX, reg); + (void)RREG32(mmPCIE_INDEX); + WREG32(mmPCIE_DATA, v); + (void)RREG32(mmPCIE_DATA); + spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); +} + +static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + WREG32(mmSMC_IND_INDEX_0, (reg)); + r = RREG32(mmSMC_IND_DATA_0); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + return r; +} + +static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&adev->smc_idx_lock, flags); + WREG32(mmSMC_IND_INDEX_0, (reg)); + WREG32(mmSMC_IND_DATA_0, (v)); + spin_unlock_irqrestore(&adev->smc_idx_lock, flags); +} + +static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); + r = RREG32(mmUVD_CTX_DATA); + spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + return r; +} + +static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); + WREG32(mmUVD_CTX_DATA, (v)); + spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); +} + +static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags; + u32 r; + + spin_lock_irqsave(&adev->didt_idx_lock, flags); + WREG32(mmDIDT_IND_INDEX, (reg)); + r = RREG32(mmDIDT_IND_DATA); + spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + return r; +} + +static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags; + + spin_lock_irqsave(&adev->didt_idx_lock, flags); + WREG32(mmDIDT_IND_INDEX, (reg)); + WREG32(mmDIDT_IND_DATA, (v)); + spin_unlock_irqrestore(&adev->didt_idx_lock, flags); +} + +static const u32 tonga_mgcg_cgcg_init[] = +{ + mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, + mmPCIE_INDEX, 0xffffffff, 0x0140001c, + mmPCIE_DATA, 0x000f0000, 0x00000000, + mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, + mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, + mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, + mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, + mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, + mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, +}; + +static const u32 iceland_mgcg_cgcg_init[] = +{ + mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2, + mmPCIE_DATA, 0x000f0000, 0x00000000, + mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0, + mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, + mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, +}; + +static const u32 cz_mgcg_cgcg_init[] = +{ + mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, + mmPCIE_INDEX, 0xffffffff, 0x0140001c, + mmPCIE_DATA, 0x000f0000, 0x00000000, + mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, + mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, + mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, + mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, +}; + +static void vi_init_golden_registers(struct amdgpu_device *adev) +{ + /* Some of the registers might be dependent on GRBM_GFX_INDEX */ + mutex_lock(&adev->grbm_idx_mutex); + + switch (adev->asic_type) { + case CHIP_TOPAZ: + amdgpu_program_register_sequence(adev, + iceland_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + break; + case CHIP_TONGA: + amdgpu_program_register_sequence(adev, + tonga_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + break; + case CHIP_CARRIZO: + amdgpu_program_register_sequence(adev, + cz_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + break; + default: + break; + } + mutex_unlock(&adev->grbm_idx_mutex); +} + +/** + * vi_get_xclk - get the xclk + * + * @adev: amdgpu_device pointer + * + * Returns the reference clock used by the gfx engine + * (VI). + */ +static u32 vi_get_xclk(struct amdgpu_device *adev) +{ + u32 reference_clock = adev->clock.spll.reference_freq; + u32 tmp; + + if (adev->flags & AMDGPU_IS_APU) + return reference_clock; + + tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); + if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) + return 1000; + + tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); + if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) + return reference_clock / 4; + + return reference_clock; +} + +/** + * vi_srbm_select - select specific register instances + * + * @adev: amdgpu_device pointer + * @me: selected ME (micro engine) + * @pipe: pipe + * @queue: queue + * @vmid: VMID + * + * Switches the currently active registers instances. Some + * registers are instanced per VMID, others are instanced per + * me/pipe/queue combination. + */ +void vi_srbm_select(struct amdgpu_device *adev, + u32 me, u32 pipe, u32 queue, u32 vmid) +{ + u32 srbm_gfx_cntl = 0; + srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe); + srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me); + srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid); + srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue); + WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); +} + +static void vi_vga_set_state(struct amdgpu_device *adev, bool state) +{ + /* todo */ +} + +static bool vi_read_disabled_bios(struct amdgpu_device *adev) +{ + u32 bus_cntl; + u32 d1vga_control = 0; + u32 d2vga_control = 0; + u32 vga_render_control = 0; + u32 rom_cntl; + bool r; + + bus_cntl = RREG32(mmBUS_CNTL); + if (adev->mode_info.num_crtc) { + d1vga_control = RREG32(mmD1VGA_CONTROL); + d2vga_control = RREG32(mmD2VGA_CONTROL); + vga_render_control = RREG32(mmVGA_RENDER_CONTROL); + } + rom_cntl = RREG32_SMC(ixROM_CNTL); + + /* enable the rom */ + WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); + if (adev->mode_info.num_crtc) { + /* Disable VGA mode */ + WREG32(mmD1VGA_CONTROL, + (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | + D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); + WREG32(mmD2VGA_CONTROL, + (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK | + D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK))); + WREG32(mmVGA_RENDER_CONTROL, + (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); + } + WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); + + r = amdgpu_read_bios(adev); + + /* restore regs */ + WREG32(mmBUS_CNTL, bus_cntl); + if (adev->mode_info.num_crtc) { + WREG32(mmD1VGA_CONTROL, d1vga_control); + WREG32(mmD2VGA_CONTROL, d2vga_control); + WREG32(mmVGA_RENDER_CONTROL, vga_render_control); + } + WREG32_SMC(ixROM_CNTL, rom_cntl); + return r; +} +static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { + {mmGB_MACROTILE_MODE7, true}, +}; + +static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { + {mmGB_TILE_MODE7, true}, + {mmGB_TILE_MODE12, true}, + {mmGB_TILE_MODE17, true}, + {mmGB_TILE_MODE23, true}, + {mmGB_MACROTILE_MODE7, true}, +}; + +static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { + {mmGRBM_STATUS, false}, + {mmGB_ADDR_CONFIG, false}, + {mmMC_ARB_RAMCFG, false}, + {mmGB_TILE_MODE0, false}, + {mmGB_TILE_MODE1, false}, + {mmGB_TILE_MODE2, false}, + {mmGB_TILE_MODE3, false}, + {mmGB_TILE_MODE4, false}, + {mmGB_TILE_MODE5, false}, + {mmGB_TILE_MODE6, false}, + {mmGB_TILE_MODE7, false}, + {mmGB_TILE_MODE8, false}, + {mmGB_TILE_MODE9, false}, + {mmGB_TILE_MODE10, false}, + {mmGB_TILE_MODE11, false}, + {mmGB_TILE_MODE12, false}, + {mmGB_TILE_MODE13, false}, + {mmGB_TILE_MODE14, false}, + {mmGB_TILE_MODE15, false}, + {mmGB_TILE_MODE16, false}, + {mmGB_TILE_MODE17, false}, + {mmGB_TILE_MODE18, false}, + {mmGB_TILE_MODE19, false}, + {mmGB_TILE_MODE20, false}, + {mmGB_TILE_MODE21, false}, + {mmGB_TILE_MODE22, false}, + {mmGB_TILE_MODE23, false}, + {mmGB_TILE_MODE24, false}, + {mmGB_TILE_MODE25, false}, + {mmGB_TILE_MODE26, false}, + {mmGB_TILE_MODE27, false}, + {mmGB_TILE_MODE28, false}, + {mmGB_TILE_MODE29, false}, + {mmGB_TILE_MODE30, false}, + {mmGB_TILE_MODE31, false}, + {mmGB_MACROTILE_MODE0, false}, + {mmGB_MACROTILE_MODE1, false}, + {mmGB_MACROTILE_MODE2, false}, + {mmGB_MACROTILE_MODE3, false}, + {mmGB_MACROTILE_MODE4, false}, + {mmGB_MACROTILE_MODE5, false}, + {mmGB_MACROTILE_MODE6, false}, + {mmGB_MACROTILE_MODE7, false}, + {mmGB_MACROTILE_MODE8, false}, + {mmGB_MACROTILE_MODE9, false}, + {mmGB_MACROTILE_MODE10, false}, + {mmGB_MACROTILE_MODE11, false}, + {mmGB_MACROTILE_MODE12, false}, + {mmGB_MACROTILE_MODE13, false}, + {mmGB_MACROTILE_MODE14, false}, + {mmGB_MACROTILE_MODE15, false}, + {mmCC_RB_BACKEND_DISABLE, false, true}, + {mmGC_USER_RB_BACKEND_DISABLE, false, true}, + {mmGB_BACKEND_MAP, false, false}, + {mmPA_SC_RASTER_CONFIG, false, true}, + {mmPA_SC_RASTER_CONFIG_1, false, true}, +}; + +static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num, + u32 sh_num, u32 reg_offset) +{ + uint32_t val; + + mutex_lock(&adev->grbm_idx_mutex); + if (se_num != 0xffffffff || sh_num != 0xffffffff) + gfx_v8_0_select_se_sh(adev, se_num, sh_num); + + val = RREG32(reg_offset); + + if (se_num != 0xffffffff || sh_num != 0xffffffff) + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + return val; +} + +static int vi_read_register(struct amdgpu_device *adev, u32 se_num, + u32 sh_num, u32 reg_offset, u32 *value) +{ + struct amdgpu_allowed_register_entry *asic_register_table = NULL; + struct amdgpu_allowed_register_entry *asic_register_entry; + uint32_t size, i; + + *value = 0; + switch (adev->asic_type) { + case CHIP_TOPAZ: + asic_register_table = tonga_allowed_read_registers; + size = ARRAY_SIZE(tonga_allowed_read_registers); + break; + case CHIP_TONGA: + case CHIP_CARRIZO: + asic_register_table = cz_allowed_read_registers; + size = ARRAY_SIZE(cz_allowed_read_registers); + break; + default: + return -EINVAL; + } + + if (asic_register_table) { + for (i = 0; i < size; i++) { + asic_register_entry = asic_register_table + i; + if (reg_offset != asic_register_entry->reg_offset) + continue; + if (!asic_register_entry->untouched) + *value = asic_register_entry->grbm_indexed ? + vi_read_indexed_register(adev, se_num, + sh_num, reg_offset) : + RREG32(reg_offset); + return 0; + } + } + + for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) { + if (reg_offset != vi_allowed_read_registers[i].reg_offset) + continue; + + if (!vi_allowed_read_registers[i].untouched) + *value = vi_allowed_read_registers[i].grbm_indexed ? + vi_read_indexed_register(adev, se_num, + sh_num, reg_offset) : + RREG32(reg_offset); + return 0; + } + return -EINVAL; +} + +static void vi_print_gpu_status_regs(struct amdgpu_device *adev) +{ + dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", + RREG32(mmGRBM_STATUS)); + dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", + RREG32(mmGRBM_STATUS2)); + dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", + RREG32(mmGRBM_STATUS_SE0)); + dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", + RREG32(mmGRBM_STATUS_SE1)); + dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", + RREG32(mmGRBM_STATUS_SE2)); + dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", + RREG32(mmGRBM_STATUS_SE3)); + dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", + RREG32(mmSRBM_STATUS)); + dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", + RREG32(mmSRBM_STATUS2)); + dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n", + RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); + dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n", + RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); + dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); + dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT1)); + dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT2)); + dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", + RREG32(mmCP_STALLED_STAT3)); + dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", + RREG32(mmCP_CPF_BUSY_STAT)); + dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_CPF_STALLED_STAT1)); + dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); + dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); + dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", + RREG32(mmCP_CPC_STALLED_STAT1)); + dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); +} + +/** + * vi_gpu_check_soft_reset - check which blocks are busy + * + * @adev: amdgpu_device pointer + * + * Check which blocks are busy and return the relevant reset + * mask to be used by vi_gpu_soft_reset(). + * Returns a mask of the blocks to be reset. + */ +u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev) +{ + u32 reset_mask = 0; + u32 tmp; + + /* GRBM_STATUS */ + tmp = RREG32(mmGRBM_STATUS); + if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | + GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | + GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | + GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | + GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | + GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) + reset_mask |= AMDGPU_RESET_GFX; + + if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) + reset_mask |= AMDGPU_RESET_CP; + + /* GRBM_STATUS2 */ + tmp = RREG32(mmGRBM_STATUS2); + if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) + reset_mask |= AMDGPU_RESET_RLC; + + if (tmp & (GRBM_STATUS2__CPF_BUSY_MASK | + GRBM_STATUS2__CPC_BUSY_MASK | + GRBM_STATUS2__CPG_BUSY_MASK)) + reset_mask |= AMDGPU_RESET_CP; + + /* SRBM_STATUS2 */ + tmp = RREG32(mmSRBM_STATUS2); + if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) + reset_mask |= AMDGPU_RESET_DMA; + + if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) + reset_mask |= AMDGPU_RESET_DMA1; + + /* SRBM_STATUS */ + tmp = RREG32(mmSRBM_STATUS); + + if (tmp & SRBM_STATUS__IH_BUSY_MASK) + reset_mask |= AMDGPU_RESET_IH; + + if (tmp & SRBM_STATUS__SEM_BUSY_MASK) + reset_mask |= AMDGPU_RESET_SEM; + + if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) + reset_mask |= AMDGPU_RESET_GRBM; + + if (adev->asic_type != CHIP_TOPAZ) { + if (tmp & (SRBM_STATUS__UVD_RQ_PENDING_MASK | + SRBM_STATUS__UVD_BUSY_MASK)) + reset_mask |= AMDGPU_RESET_UVD; + } + + if (tmp & SRBM_STATUS__VMC_BUSY_MASK) + reset_mask |= AMDGPU_RESET_VMC; + + if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | + SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) + reset_mask |= AMDGPU_RESET_MC; + + /* SDMA0_STATUS_REG */ + tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); + if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) + reset_mask |= AMDGPU_RESET_DMA; + + /* SDMA1_STATUS_REG */ + tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); + if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) + reset_mask |= AMDGPU_RESET_DMA1; +#if 0 + /* VCE_STATUS */ + if (adev->asic_type != CHIP_TOPAZ) { + tmp = RREG32(mmVCE_STATUS); + if (tmp & VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK) + reset_mask |= AMDGPU_RESET_VCE; + if (tmp & VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK) + reset_mask |= AMDGPU_RESET_VCE1; + + } + + if (adev->asic_type != CHIP_TOPAZ) { + if (amdgpu_display_is_display_hung(adev)) + reset_mask |= AMDGPU_RESET_DISPLAY; + } +#endif + + /* Skip MC reset as it's mostly likely not hung, just busy */ + if (reset_mask & AMDGPU_RESET_MC) { + DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); + reset_mask &= ~AMDGPU_RESET_MC; + } + + return reset_mask; +} + +/** + * vi_gpu_soft_reset - soft reset GPU + * + * @adev: amdgpu_device pointer + * @reset_mask: mask of which blocks to reset + * + * Soft reset the blocks specified in @reset_mask. + */ +static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask) +{ + struct amdgpu_mode_mc_save save; + u32 grbm_soft_reset = 0, srbm_soft_reset = 0; + u32 tmp; + + if (reset_mask == 0) + return; + + dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask); + + vi_print_gpu_status_regs(adev); + dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); + dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); + + /* disable CG/PG */ + + /* stop the rlc */ + //XXX + //gfx_v8_0_rlc_stop(adev); + + /* Disable GFX parsing/prefetching */ + tmp = RREG32(mmCP_ME_CNTL); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); + WREG32(mmCP_ME_CNTL, tmp); + + /* Disable MEC parsing/prefetching */ + tmp = RREG32(mmCP_MEC_CNTL); + tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); + WREG32(mmCP_MEC_CNTL, tmp); + + if (reset_mask & AMDGPU_RESET_DMA) { + /* sdma0 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); + tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); + WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); + } + if (reset_mask & AMDGPU_RESET_DMA1) { + /* sdma1 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); + tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); + WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); + } + + gmc_v8_0_mc_stop(adev, &save); + if (amdgpu_asic_wait_for_mc_idle(adev)) { + dev_warn(adev->dev, "Wait for MC idle timedout !\n"); + } + + if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) { + grbm_soft_reset = + REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1); + grbm_soft_reset = + REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); + } + + if (reset_mask & AMDGPU_RESET_CP) { + grbm_soft_reset = + REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1); + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); + } + + if (reset_mask & AMDGPU_RESET_DMA) + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA, 1); + + if (reset_mask & AMDGPU_RESET_DMA1) + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1, 1); + + if (reset_mask & AMDGPU_RESET_DISPLAY) + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_DC, 1); + + if (reset_mask & AMDGPU_RESET_RLC) + grbm_soft_reset = + REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); + + if (reset_mask & AMDGPU_RESET_SEM) + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1); + + if (reset_mask & AMDGPU_RESET_IH) + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_IH, 1); + + if (reset_mask & AMDGPU_RESET_GRBM) + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); + + if (reset_mask & AMDGPU_RESET_VMC) + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); + + if (reset_mask & AMDGPU_RESET_UVD) + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); + + if (reset_mask & AMDGPU_RESET_VCE) + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1); + + if (reset_mask & AMDGPU_RESET_VCE) + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1); + + if (!(adev->flags & AMDGPU_IS_APU)) { + if (reset_mask & AMDGPU_RESET_MC) + srbm_soft_reset = + REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1); + } + + if (grbm_soft_reset) { + tmp = RREG32(mmGRBM_SOFT_RESET); + tmp |= grbm_soft_reset; + dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmGRBM_SOFT_RESET, tmp); + tmp = RREG32(mmGRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~grbm_soft_reset; + WREG32(mmGRBM_SOFT_RESET, tmp); + tmp = RREG32(mmGRBM_SOFT_RESET); + } + + if (srbm_soft_reset) { + tmp = RREG32(mmSRBM_SOFT_RESET); + tmp |= srbm_soft_reset; + dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~srbm_soft_reset; + WREG32(mmSRBM_SOFT_RESET, tmp); + tmp = RREG32(mmSRBM_SOFT_RESET); + } + + /* Wait a little for things to settle down */ + udelay(50); + + gmc_v8_0_mc_resume(adev, &save); + udelay(50); + + vi_print_gpu_status_regs(adev); +} + +static void vi_gpu_pci_config_reset(struct amdgpu_device *adev) +{ + struct amdgpu_mode_mc_save save; + u32 tmp, i; + + dev_info(adev->dev, "GPU pci config reset\n"); + + /* disable dpm? */ + + /* disable cg/pg */ + + /* Disable GFX parsing/prefetching */ + tmp = RREG32(mmCP_ME_CNTL); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); + WREG32(mmCP_ME_CNTL, tmp); + + /* Disable MEC parsing/prefetching */ + tmp = RREG32(mmCP_MEC_CNTL); + tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); + tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); + WREG32(mmCP_MEC_CNTL, tmp); + + /* Disable GFX parsing/prefetching */ + WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | + CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); + + /* Disable MEC parsing/prefetching */ + WREG32(mmCP_MEC_CNTL, + CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); + + /* sdma0 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); + tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); + WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); + + /* sdma1 */ + tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); + tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); + WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); + + /* XXX other engines? */ + + /* halt the rlc, disable cp internal ints */ + //XXX + //gfx_v8_0_rlc_stop(adev); + + udelay(50); + + /* disable mem access */ + gmc_v8_0_mc_stop(adev, &save); + if (amdgpu_asic_wait_for_mc_idle(adev)) { + dev_warn(adev->dev, "Wait for MC idle timed out !\n"); + } + + /* disable BM */ + pci_clear_master(adev->pdev); + /* reset */ + amdgpu_pci_config_reset(adev); + + udelay(100); + + /* wait for asic to come out of reset */ + for (i = 0; i < adev->usec_timeout; i++) { + if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) + break; + udelay(1); + } + +} + +static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) +{ + u32 tmp = RREG32(mmBIOS_SCRATCH_3); + + if (hung) + tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; + else + tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; + + WREG32(mmBIOS_SCRATCH_3, tmp); +} + +/** + * vi_asic_reset - soft reset GPU + * + * @adev: amdgpu_device pointer + * + * Look up which blocks are hung and attempt + * to reset them. + * Returns 0 for success. + */ +static int vi_asic_reset(struct amdgpu_device *adev) +{ + u32 reset_mask; + + reset_mask = vi_gpu_check_soft_reset(adev); + + if (reset_mask) + vi_set_bios_scratch_engine_hung(adev, true); + + /* try soft reset */ + vi_gpu_soft_reset(adev, reset_mask); + + reset_mask = vi_gpu_check_soft_reset(adev); + + /* try pci config reset */ + if (reset_mask && amdgpu_hard_reset) + vi_gpu_pci_config_reset(adev); + + reset_mask = vi_gpu_check_soft_reset(adev); + + if (!reset_mask) + vi_set_bios_scratch_engine_hung(adev, false); + + return 0; +} + +static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, + u32 cntl_reg, u32 status_reg) +{ + int r, i; + struct atom_clock_dividers dividers; + uint32_t tmp; + + r = amdgpu_atombios_get_clock_dividers(adev, + COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, + clock, false, ÷rs); + if (r) + return r; + + tmp = RREG32_SMC(cntl_reg); + tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | + CG_DCLK_CNTL__DCLK_DIVIDER_MASK); + tmp |= dividers.post_divider; + WREG32_SMC(cntl_reg, tmp); + + for (i = 0; i < 100; i++) { + if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) + break; + mdelay(10); + } + if (i == 100) + return -ETIMEDOUT; + + return 0; +} + +static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) +{ + int r; + + r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); + if (r) + return r; + + r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); + + return 0; +} + +static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) +{ + /* todo */ + + return 0; +} + +static void vi_pcie_gen3_enable(struct amdgpu_device *adev) +{ + u32 mask; + int ret; + + if (amdgpu_pcie_gen2 == 0) + return; + + if (adev->flags & AMDGPU_IS_APU) + return; + + ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); + if (ret != 0) + return; + + if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) + return; + + /* todo */ +} + +static void vi_program_aspm(struct amdgpu_device *adev) +{ + + if (amdgpu_aspm == 0) + return; + + /* todo */ +} + +static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, + bool enable) +{ + u32 tmp; + + /* not necessary on CZ */ + if (adev->flags & AMDGPU_IS_APU) + return; + + tmp = RREG32(mmBIF_DOORBELL_APER_EN); + if (enable) + tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1); + else + tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0); + + WREG32(mmBIF_DOORBELL_APER_EN, tmp); +} + +/* topaz has no DCE, UVD, VCE */ +static const struct amdgpu_ip_block_version topaz_ip_blocks[] = +{ + /* ORDER MATTERS! */ + { + .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vi_common_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &gmc_v8_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_IH, + .major = 2, + .minor = 4, + .rev = 0, + .funcs = &iceland_ih_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 1, + .rev = 0, + .funcs = &iceland_dpm_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &gfx_v8_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .major = 2, + .minor = 4, + .rev = 0, + .funcs = &sdma_v2_4_ip_funcs, + }, +}; + +static const struct amdgpu_ip_block_version tonga_ip_blocks[] = +{ + /* ORDER MATTERS! */ + { + .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vi_common_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &gmc_v8_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_IH, + .major = 3, + .minor = 0, + .rev = 0, + .funcs = &tonga_ih_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 1, + .rev = 0, + .funcs = &tonga_dpm_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .major = 10, + .minor = 0, + .rev = 0, + .funcs = &dce_v10_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &gfx_v8_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .major = 3, + .minor = 0, + .rev = 0, + .funcs = &sdma_v3_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .major = 5, + .minor = 0, + .rev = 0, + .funcs = &uvd_v5_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .major = 3, + .minor = 0, + .rev = 0, + .funcs = &vce_v3_0_ip_funcs, + }, +}; + +static const struct amdgpu_ip_block_version cz_ip_blocks[] = +{ + /* ORDER MATTERS! */ + { + .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vi_common_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &gmc_v8_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_IH, + .major = 3, + .minor = 0, + .rev = 0, + .funcs = &cz_ih_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &cz_dpm_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .major = 11, + .minor = 0, + .rev = 0, + .funcs = &dce_v11_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &gfx_v8_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .major = 3, + .minor = 0, + .rev = 0, + .funcs = &sdma_v3_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .major = 6, + .minor = 0, + .rev = 0, + .funcs = &uvd_v6_0_ip_funcs, + }, + { + .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .major = 3, + .minor = 0, + .rev = 0, + .funcs = &vce_v3_0_ip_funcs, + }, +}; + +int vi_set_ip_blocks(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + case CHIP_TOPAZ: + adev->ip_blocks = topaz_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks); + break; + case CHIP_TONGA: + adev->ip_blocks = tonga_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); + break; + case CHIP_CARRIZO: + adev->ip_blocks = cz_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks); + break; + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + + adev->ip_block_enabled = kcalloc(adev->num_ip_blocks, sizeof(bool), GFP_KERNEL); + if (adev->ip_block_enabled == NULL) + return -ENOMEM; + + return 0; +} + +static uint32_t vi_get_rev_id(struct amdgpu_device *adev) +{ + if (adev->asic_type == CHIP_TOPAZ) + return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK) + >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; + else + return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) + >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; +} + +static const struct amdgpu_asic_funcs vi_asic_funcs = +{ + .read_disabled_bios = &vi_read_disabled_bios, + .read_register = &vi_read_register, + .reset = &vi_asic_reset, + .set_vga_state = &vi_vga_set_state, + .get_xclk = &vi_get_xclk, + .set_uvd_clocks = &vi_set_uvd_clocks, + .set_vce_clocks = &vi_set_vce_clocks, + .get_cu_info = &gfx_v8_0_get_cu_info, + /* these should be moved to their own ip modules */ + .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter, + .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle, +}; + +static int vi_common_early_init(struct amdgpu_device *adev) +{ + bool smc_enabled = false; + + adev->smc_rreg = &vi_smc_rreg; + adev->smc_wreg = &vi_smc_wreg; + adev->pcie_rreg = &vi_pcie_rreg; + adev->pcie_wreg = &vi_pcie_wreg; + adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; + adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; + adev->didt_rreg = &vi_didt_rreg; + adev->didt_wreg = &vi_didt_wreg; + + adev->asic_funcs = &vi_asic_funcs; + + if (amdgpu_get_ip_block(adev, AMDGPU_IP_BLOCK_TYPE_SMC) && + (amdgpu_ip_block_mask & (1 << AMDGPU_IP_BLOCK_TYPE_SMC))) + smc_enabled = true; + + adev->rev_id = vi_get_rev_id(adev); + adev->external_rev_id = 0xFF; + switch (adev->asic_type) { + case CHIP_TOPAZ: + adev->has_uvd = false; + adev->cg_flags = 0; + adev->pg_flags = 0; + adev->external_rev_id = 0x1; + if (amdgpu_smc_load_fw && smc_enabled) + adev->firmware.smu_load = true; + break; + case CHIP_TONGA: + adev->has_uvd = true; + adev->cg_flags = 0; + adev->pg_flags = 0; + adev->external_rev_id = adev->rev_id + 0x14; + if (amdgpu_smc_load_fw && smc_enabled) + adev->firmware.smu_load = true; + break; + case CHIP_CARRIZO: + adev->has_uvd = true; + adev->cg_flags = 0; + adev->pg_flags = 0; + adev->external_rev_id = adev->rev_id + 0x1; + if (amdgpu_smc_load_fw && smc_enabled) + adev->firmware.smu_load = true; + break; + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + + return 0; +} + +static int vi_common_sw_init(struct amdgpu_device *adev) +{ + return 0; +} + +static int vi_common_sw_fini(struct amdgpu_device *adev) +{ + return 0; +} + +static int vi_common_hw_init(struct amdgpu_device *adev) +{ + /* move the golden regs per IP block */ + vi_init_golden_registers(adev); + /* enable pcie gen2/3 link */ + vi_pcie_gen3_enable(adev); + /* enable aspm */ + vi_program_aspm(adev); + /* enable the doorbell aperture */ + vi_enable_doorbell_aperture(adev, true); + + return 0; +} + +static int vi_common_hw_fini(struct amdgpu_device *adev) +{ + /* enable the doorbell aperture */ + vi_enable_doorbell_aperture(adev, false); + + return 0; +} + +static int vi_common_suspend(struct amdgpu_device *adev) +{ + return vi_common_hw_fini(adev); +} + +static int vi_common_resume(struct amdgpu_device *adev) +{ + return vi_common_hw_init(adev); +} + +static bool vi_common_is_idle(struct amdgpu_device *adev) +{ + return true; +} + +static int vi_common_wait_for_idle(struct amdgpu_device *adev) +{ + return 0; +} + +static void vi_common_print_status(struct amdgpu_device *adev) +{ + +} + +static int vi_common_soft_reset(struct amdgpu_device *adev) +{ + /* XXX hard reset?? */ + return 0; +} + +static int vi_common_set_clockgating_state(struct amdgpu_device *adev, + enum amdgpu_clockgating_state state) +{ + return 0; +} + +static int vi_common_set_powergating_state(struct amdgpu_device *adev, + enum amdgpu_powergating_state state) +{ + return 0; +} + +const struct amdgpu_ip_funcs vi_common_ip_funcs = { + .early_init = vi_common_early_init, + .late_init = NULL, + .sw_init = vi_common_sw_init, + .sw_fini = vi_common_sw_fini, + .hw_init = vi_common_hw_init, + .hw_fini = vi_common_hw_fini, + .suspend = vi_common_suspend, + .resume = vi_common_resume, + .is_idle = vi_common_is_idle, + .wait_for_idle = vi_common_wait_for_idle, + .soft_reset = vi_common_soft_reset, + .print_status = vi_common_print_status, + .set_clockgating_state = vi_common_set_clockgating_state, + .set_powergating_state = vi_common_set_powergating_state, +}; + diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h new file mode 100644 index 000000000000..d16a5f7e4edd --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vi.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VI_H__ +#define __VI_H__ + +extern const struct amdgpu_ip_funcs vi_common_ip_funcs; + +void vi_srbm_select(struct amdgpu_device *adev, + u32 me, u32 pipe, u32 queue, u32 vmid); +int vi_set_ip_blocks(struct amdgpu_device *adev); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/vi_dpm.h b/drivers/gpu/drm/amd/amdgpu/vi_dpm.h new file mode 100644 index 000000000000..11cb1f7eeba5 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vi_dpm.h @@ -0,0 +1,36 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VI_DPM_H__ +#define __VI_DPM_H__ + +extern const struct amdgpu_ip_funcs cz_dpm_ip_funcs; +int cz_smu_init(struct amdgpu_device *adev); +int cz_smu_start(struct amdgpu_device *adev); +int cz_smu_fini(struct amdgpu_device *adev); + +extern const struct amdgpu_ip_funcs tonga_dpm_ip_funcs; + +extern const struct amdgpu_ip_funcs iceland_dpm_ip_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h new file mode 100644 index 000000000000..385267c31d11 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vid.h @@ -0,0 +1,363 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef VI_H +#define VI_H + +#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ +#define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ +#define SDMA_MAX_INSTANCE 2 + +/* crtc instance offsets */ +#define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c) +#define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c) +#define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c) +#define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c) +#define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c) +#define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c) +#define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c) + +/* dig instance offsets */ +#define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00) +#define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00) +#define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00) +#define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00) +#define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00) +#define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00) +#define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00) +#define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00) +#define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00) + +/* audio endpt instance offsets */ +#define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8) +#define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8) +#define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8) +#define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8) +#define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8) +#define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8) +#define AUD6_REGISTER_OFFSET (0x17c4 - 0x17a8) + +/* hpd instance offsets */ +#define HPD0_REGISTER_OFFSET (0x1898 - 0x1898) +#define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898) +#define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898) +#define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898) +#define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898) +#define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898) + +#define AMDGPU_NUM_OF_VMIDS 8 + +#define RB_BITMAP_WIDTH_PER_SH 2 + +#define MC_SEQ_MISC0__GDDR5__SHIFT 0x1c +#define MC_SEQ_MISC0__GDDR5_MASK 0xf0000000 +#define MC_SEQ_MISC0__GDDR5_VALUE 5 + +/* + * PM4 + */ +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) +#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ + ((reg) & 0xFFFF) | \ + ((n) & 0x3FFF) << 16) +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) + +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) + +#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ + (((op) & 0xFF) << 8) | \ + ((n) & 0x3FFF) << 16) + +#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) + +/* Packet 3 types */ +#define PACKET3_NOP 0x10 +#define PACKET3_SET_BASE 0x11 +#define PACKET3_BASE_INDEX(x) ((x) << 0) +#define CE_PARTITION_BASE 3 +#define PACKET3_CLEAR_STATE 0x12 +#define PACKET3_INDEX_BUFFER_SIZE 0x13 +#define PACKET3_DISPATCH_DIRECT 0x15 +#define PACKET3_DISPATCH_INDIRECT 0x16 +#define PACKET3_ATOMIC_GDS 0x1D +#define PACKET3_ATOMIC_MEM 0x1E +#define PACKET3_OCCLUSION_QUERY 0x1F +#define PACKET3_SET_PREDICATION 0x20 +#define PACKET3_REG_RMW 0x21 +#define PACKET3_COND_EXEC 0x22 +#define PACKET3_PRED_EXEC 0x23 +#define PACKET3_DRAW_INDIRECT 0x24 +#define PACKET3_DRAW_INDEX_INDIRECT 0x25 +#define PACKET3_INDEX_BASE 0x26 +#define PACKET3_DRAW_INDEX_2 0x27 +#define PACKET3_CONTEXT_CONTROL 0x28 +#define PACKET3_INDEX_TYPE 0x2A +#define PACKET3_DRAW_INDIRECT_MULTI 0x2C +#define PACKET3_DRAW_INDEX_AUTO 0x2D +#define PACKET3_NUM_INSTANCES 0x2F +#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 +#define PACKET3_INDIRECT_BUFFER_CONST 0x33 +#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 +#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 +#define PACKET3_DRAW_PREAMBLE 0x36 +#define PACKET3_WRITE_DATA 0x37 +#define WRITE_DATA_DST_SEL(x) ((x) << 8) + /* 0 - register + * 1 - memory (sync - via GRBM) + * 2 - gl2 + * 3 - gds + * 4 - reserved + * 5 - memory (async - direct) + */ +#define WR_ONE_ADDR (1 << 16) +#define WR_CONFIRM (1 << 20) +#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + */ +#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) + /* 0 - me + * 1 - pfp + * 2 - ce + */ +#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 +#define PACKET3_MEM_SEMAPHORE 0x39 +# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) +# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ +# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ +# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) +# define PACKET3_SEM_SEL_WAIT (0x7 << 29) +#define PACKET3_WAIT_REG_MEM 0x3C +#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) + /* 0 - always + * 1 - < + * 2 - <= + * 3 - == + * 4 - != + * 5 - >= + * 6 - > + */ +#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) + /* 0 - reg + * 1 - mem + */ +#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) + /* 0 - wait_reg_mem + * 1 - wr_wait_wr_reg + */ +#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) + /* 0 - me + * 1 - pfp + */ +#define PACKET3_INDIRECT_BUFFER 0x3F +#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) +#define INDIRECT_BUFFER_VALID (1 << 23) +#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +#define PACKET3_COPY_DATA 0x40 +#define PACKET3_PFP_SYNC_ME 0x42 +#define PACKET3_SURFACE_SYNC 0x43 +# define PACKET3_DEST_BASE_0_ENA (1 << 0) +# define PACKET3_DEST_BASE_1_ENA (1 << 1) +# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) +# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) +# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) +# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) +# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) +# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) +# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) +# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) +# define PACKET3_DB_DEST_BASE_ENA (1 << 14) +# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) +# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ +# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ +# define PACKET3_DEST_BASE_2_ENA (1 << 19) +# define PACKET3_DEST_BASE_3_ENA (1 << 21) +# define PACKET3_TCL1_ACTION_ENA (1 << 22) +# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ +# define PACKET3_CB_ACTION_ENA (1 << 25) +# define PACKET3_DB_ACTION_ENA (1 << 26) +# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) +# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) +# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) +#define PACKET3_COND_WRITE 0x45 +#define PACKET3_EVENT_WRITE 0x46 +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) + /* 0 - any non-TS event + * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* + * 2 - SAMPLE_PIPELINESTAT + * 3 - SAMPLE_STREAMOUTSTAT* + * 4 - *S_PARTIAL_FLUSH + * 5 - EOP events + * 6 - EOS events + */ +#define PACKET3_EVENT_WRITE_EOP 0x47 +#define EOP_TCL1_VOL_ACTION_EN (1 << 12) +#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ +#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ +#define EOP_TCL1_ACTION_EN (1 << 16) +#define EOP_TC_ACTION_EN (1 << 17) /* L2 */ +#define EOP_TCL2_VOLATILE (1 << 24) +#define EOP_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +#define DATA_SEL(x) ((x) << 29) + /* 0 - discard + * 1 - send low 32bit data + * 2 - send 64bit data + * 3 - send 64bit GPU counter value + * 4 - send 64bit sys counter value + */ +#define INT_SEL(x) ((x) << 24) + /* 0 - none + * 1 - interrupt only (DATA_SEL = 0) + * 2 - interrupt when data write is confirmed + */ +#define DST_SEL(x) ((x) << 16) + /* 0 - MC + * 1 - TC/L2 + */ +#define PACKET3_EVENT_WRITE_EOS 0x48 +#define PACKET3_RELEASE_MEM 0x49 +#define PACKET3_PREAMBLE_CNTL 0x4A +# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) +# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) +#define PACKET3_DMA_DATA 0x50 +/* 1. header + * 2. CONTROL + * 3. SRC_ADDR_LO or DATA [31:0] + * 4. SRC_ADDR_HI [31:0] + * 5. DST_ADDR_LO [31:0] + * 6. DST_ADDR_HI [7:0] + * 7. COMMAND [30:21] | BYTE_COUNT [20:0] + */ +/* CONTROL */ +# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) + /* 0 - ME + * 1 - PFP + */ +# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) +# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) + /* 0 - DST_ADDR using DAS + * 1 - GDS + * 3 - DST_ADDR using L2 + */ +# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) +# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) + /* 0 - SRC_ADDR using SAS + * 1 - GDS + * 2 - DATA + * 3 - SRC_ADDR using L2 + */ +# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) +/* COMMAND */ +# define PACKET3_DMA_DATA_DIS_WC (1 << 21) +# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) + /* 0 - none + * 1 - 8 in 16 + * 2 - 8 in 32 + * 3 - 8 in 64 + */ +# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) + /* 0 - none + * 1 - 8 in 16 + * 2 - 8 in 32 + * 3 - 8 in 64 + */ +# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) +# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) +# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) +#define PACKET3_AQUIRE_MEM 0x58 +#define PACKET3_REWIND 0x59 +#define PACKET3_LOAD_UCONFIG_REG 0x5E +#define PACKET3_LOAD_SH_REG 0x5F +#define PACKET3_LOAD_CONFIG_REG 0x60 +#define PACKET3_LOAD_CONTEXT_REG 0x61 +#define PACKET3_SET_CONFIG_REG 0x68 +#define PACKET3_SET_CONFIG_REG_START 0x00002000 +#define PACKET3_SET_CONFIG_REG_END 0x00002c00 +#define PACKET3_SET_CONTEXT_REG 0x69 +#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 +#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 +#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 +#define PACKET3_SET_SH_REG 0x76 +#define PACKET3_SET_SH_REG_START 0x00002c00 +#define PACKET3_SET_SH_REG_END 0x00003000 +#define PACKET3_SET_SH_REG_OFFSET 0x77 +#define PACKET3_SET_QUEUE_REG 0x78 +#define PACKET3_SET_UCONFIG_REG 0x79 +#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 +#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 +#define PACKET3_SCRATCH_RAM_WRITE 0x7D +#define PACKET3_SCRATCH_RAM_READ 0x7E +#define PACKET3_LOAD_CONST_RAM 0x80 +#define PACKET3_WRITE_CONST_RAM 0x81 +#define PACKET3_DUMP_CONST_RAM 0x83 +#define PACKET3_INCREMENT_CE_COUNTER 0x84 +#define PACKET3_INCREMENT_DE_COUNTER 0x85 +#define PACKET3_WAIT_ON_CE_COUNTER 0x86 +#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 +#define PACKET3_SWITCH_BUFFER 0x8B + +#define VCE_CMD_NO_OP 0x00000000 +#define VCE_CMD_END 0x00000001 +#define VCE_CMD_IB 0x00000002 +#define VCE_CMD_FENCE 0x00000003 +#define VCE_CMD_TRAP 0x00000004 +#define VCE_CMD_IB_AUTO 0x00000005 +#define VCE_CMD_SEMAPHORE 0x00000006 + +#endif -- cgit v1.2.3 From 89330c391b407f9b94baf2f625de5e71e69071b0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Apr 2015 17:36:52 -0400 Subject: drm/amdgpu: add CIK pci ids MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 83 +++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index d1af448795f3..632a8d1cf292 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -138,6 +138,89 @@ MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disab module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); static struct pci_device_id pciidlist[] = { +#ifdef CONFIG_DRM_AMDGPU_CIK + /* Kaveri */ + {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, + /* Bonaire */ + {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, + {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, + {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, + {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, + {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, + {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, + {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, + {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, + {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, + {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, + /* Hawaii */ + {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, + /* Kabini */ + {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, + {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, + {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, + {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, + {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, + {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, + {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, + {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, + {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, + /* mullins */ + {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, + {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, +#endif {0, 0, 0} }; -- cgit v1.2.3 From 1256a8b89eeaf444bd08bf4b5ed4c71a397ccdca Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 20 Apr 2015 17:37:54 -0400 Subject: drm/amdgpu: add VI pci ids MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 632a8d1cf292..dfd426132792 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -221,6 +221,26 @@ static struct pci_device_id pciidlist[] = { {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, #endif + /* topaz */ + {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, + {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, + {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, + {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, + {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, + /* tonga */ + {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, + {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, + {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, + {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, + {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, + {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, + {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, + /* carrizo */ + {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, + {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, + {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, + {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, + {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, {0, 0, 0} }; -- cgit v1.2.3 From 2d8bd23a057234ce8e540a3a08f4e67abcc551a8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 22 Apr 2015 14:00:49 -0400 Subject: drm/amdgpu: drop ttm two ended allocation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_bo_create() calls amdgpu_ttm_placement_from_domain() before ttm_bo_init() is called. amdgpu_ttm_placement_from_domain() uses the ttm bo size to determine when to select top down allocation but since the ttm bo is not initialized yet the check is always false. It only took affect when buffers were validated later. It also seemed to regress suspend and resume on some systems possibly due to it not taking affect in amdgpu_bo_create(). amdgpu_bo_create() and amdgpu_ttm_placement_from_domain() need to be reworked substantially for this to be optimally effective. Re-enable it at that point. Ported from radeon commit: a239118a24b3bf9089751068e431dfb63dc4168b Signed-off-by: Alex Deucher Reviewed-by: Michel Dänzer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index b51582714c21..f5e17f95e812 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -189,12 +189,6 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain) else rbo->placements[i].lpfn = 0; } - - if (rbo->tbo.mem.size > 512 * 1024) { - for (i = 0; i < c; i++) { - rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN; - } - } } int amdgpu_bo_create(struct amdgpu_device *adev, -- cgit v1.2.3 From 7ab7e8a4096d2af80613113ae4bea497b4f0baf5 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Mon, 27 Apr 2015 13:45:40 +0800 Subject: drm/amdgpu: fix error check issue in amdgpu_mn_invalidate_range_start MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jack Xiao Reviewed-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c index e94429185660..b3a17a9ab1f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c @@ -135,7 +135,7 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn, while (it) { struct amdgpu_mn_node *node; struct amdgpu_bo *bo; - int r; + long r; node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, start, end); @@ -144,19 +144,19 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn, r = amdgpu_bo_reserve(bo, true); if (r) { - DRM_ERROR("(%d) failed to reserve user bo\n", r); + DRM_ERROR("(%ld) failed to reserve user bo\n", r); continue; } r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false, MAX_SCHEDULE_TIMEOUT); - if (r) - DRM_ERROR("(%d) failed to wait for user bo\n", r); + if (r <= 0) + DRM_ERROR("(%ld) failed to wait for user bo\n", r); amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); if (r) - DRM_ERROR("(%d) failed to validate user bo\n", r); + DRM_ERROR("(%ld) failed to validate user bo\n", r); amdgpu_bo_unreserve(bo); } -- cgit v1.2.3 From 840d51445f1527bda37b5d48a203ecff7988ad2b Mon Sep 17 00:00:00 2001 From: "monk.liu" Date: Mon, 27 Apr 2015 15:19:20 +0800 Subject: drm/amdgpu: fix bug occurs when bo_list is NULL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Still need to handle ibs BO and validate them even bo_list is NULL Signed-off-by: Monk.Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 70a90312d0a4..ffbe9aa9f232 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -353,19 +353,19 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p) { struct amdgpu_fpriv *fpriv = p->filp->driver_priv; struct amdgpu_cs_buckets buckets; - bool need_mmap_lock; + bool need_mmap_lock = false; int i, r; - if (p->bo_list == NULL) - return 0; + if (p->bo_list) { + need_mmap_lock = p->bo_list->has_userptr; + amdgpu_cs_buckets_init(&buckets); + for (i = 0; i < p->bo_list->num_entries; i++) + amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head, + p->bo_list->array[i].priority); - need_mmap_lock = p->bo_list->has_userptr; - amdgpu_cs_buckets_init(&buckets); - for (i = 0; i < p->bo_list->num_entries; i++) - amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head, - p->bo_list->array[i].priority); + amdgpu_cs_buckets_get_list(&buckets, &p->validated); + } - amdgpu_cs_buckets_get_list(&buckets, &p->validated); p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm, &p->validated); -- cgit v1.2.3 From decee87a88c05980ebc545c19d4ff252052ddc3e Mon Sep 17 00:00:00 2001 From: "monk.liu" Date: Mon, 27 Apr 2015 10:38:16 +0800 Subject: drm/amdgpu: let bo_list handler start from 1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit this could prevent mis-understanding, because libdrm side will consider no bo_list created if handleis zero Signed-off-by: monk.liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index 819fb861ac04..36d34e0afbc3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -43,7 +43,7 @@ static int amdgpu_bo_list_create(struct amdgpu_fpriv *fpriv, mutex_lock(&fpriv->bo_list_lock); r = idr_alloc(&fpriv->bo_list_handles, *result, - 0, 0, GFP_KERNEL); + 1, 0, GFP_KERNEL); if (r < 0) { mutex_unlock(&fpriv->bo_list_lock); kfree(*result); -- cgit v1.2.3 From 1045745742fc12c1320ccce849ca2810c6563f8d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Apr 2015 11:42:54 -0400 Subject: drm/amdgpu: fix error handling in cz_dpm_hw_fini/cz_dpm_suspend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Need to unlock the mutex on error. Noticed-by: Dan Carpenter Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index b5c8485d8a58..e56f54bf87d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -1274,8 +1274,6 @@ static int cz_dpm_hw_fini(struct amdgpu_device *adev) if (adev->pm.dpm_enabled) { ret = cz_dpm_disable(adev); - if (ret) - return -EINVAL; adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = @@ -1286,7 +1284,7 @@ static int cz_dpm_hw_fini(struct amdgpu_device *adev) mutex_unlock(&adev->pm.mutex); - return 0; + return ret; } static int cz_dpm_suspend(struct amdgpu_device *adev) @@ -1297,8 +1295,6 @@ static int cz_dpm_suspend(struct amdgpu_device *adev) mutex_lock(&adev->pm.mutex); ret = cz_dpm_disable(adev); - if (ret) - return -EINVAL; adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = @@ -1307,7 +1303,7 @@ static int cz_dpm_suspend(struct amdgpu_device *adev) mutex_unlock(&adev->pm.mutex); } - return 0; + return ret; } static int cz_dpm_resume(struct amdgpu_device *adev) -- cgit v1.2.3 From c92b90ccc20bb55a3a0bb8fcc55c18d0710f8cb7 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 30 Apr 2015 11:47:03 -0400 Subject: drm/amdgpu: memset gds_info struct in info ioctl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoids possibility that info may leak via the uninitialized _pad element. Noticed-by: Dan Carpenter Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index c271da34998d..2d50c6dbdcbb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -345,6 +345,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file case AMDGPU_INFO_GDS_CONFIG: { struct drm_amdgpu_info_gds gds_info; + memset(&gds_info, 0, sizeof(gds_info)); gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; -- cgit v1.2.3 From 46651cc5dbee35dd2f25a02de328d3e7310ce64b Mon Sep 17 00:00:00 2001 From: Sonny Jiang Date: Thu, 30 Apr 2015 17:12:14 -0400 Subject: drm/amdgpu fix amdgpu.dpm=0 (v2) Fix crash when disabling dpm. v2: agd5f: fix coding style, cleanup commit message Signed-off-by: Sonny Jiang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index e56f54bf87d2..adf4dbc3f6a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -1206,10 +1206,7 @@ static int cz_dpm_enable(struct amdgpu_device *adev) static int cz_dpm_hw_init(struct amdgpu_device *adev) { - int ret; - - if (!amdgpu_dpm) - return 0; + int ret = 0; mutex_lock(&adev->pm.mutex); @@ -1229,6 +1226,12 @@ static int cz_dpm_hw_init(struct amdgpu_device *adev) return ret; } + if (!amdgpu_dpm) { + adev->pm.dpm_enabled = false; + mutex_unlock(&adev->pm.mutex); + return ret; + } + /* cz dpm setup asic */ cz_dpm_setup_asic(adev); @@ -1326,6 +1329,12 @@ static int cz_dpm_resume(struct amdgpu_device *adev) return ret; } + if (!amdgpu_dpm) { + adev->pm.dpm_enabled = false; + mutex_unlock(&adev->pm.mutex); + return ret; + } + /* cz dpm setup asic */ cz_dpm_setup_asic(adev); -- cgit v1.2.3 From 886712881da15b7f455c43a4ce4121f20035c0fa Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Wed, 6 May 2015 18:44:29 +0800 Subject: drm/amdgpu: remove AMDGPU_GEM_CREATE_CPU_GTT_UC This flag isn't used by user mode drivers, remove it to avoid confusion. And rename GTT_WC to GTT_USWC to make it clear. Signed-off-by: Jammy Zhou Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 ++-------- include/uapi/drm/amdgpu_drm.h | 7 ++----- 2 files changed, 4 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index f5e17f95e812..992b7f5843bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -132,10 +132,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain) } if (domain & AMDGPU_GEM_DOMAIN_GTT) { - if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_UC) { - rbo->placements[c].fpfn = 0; - rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_TT; - } else if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) { + if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { rbo->placements[c].fpfn = 0; rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; @@ -146,10 +143,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain) } if (domain & AMDGPU_GEM_DOMAIN_CPU) { - if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_UC) { - rbo->placements[c].fpfn = 0; - rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_SYSTEM; - } else if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) { + if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { rbo->placements[c].fpfn = 0; rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_UNCACHED; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 9e771fb858b4..77bc5740fd7c 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -73,15 +73,12 @@ #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) /* Flag that CPU access will not work, this VRAM domain is invisible */ #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) -/* Flag that un-cached attributes should be used for GTT */ -#define AMDGPU_GEM_CREATE_CPU_GTT_UC (1 << 2) /* Flag that USWC attributes should be used for GTT */ -#define AMDGPU_GEM_CREATE_CPU_GTT_WC (1 << 3) +#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) /* Flag mask for GTT domain_flags */ #define AMDGPU_GEM_CREATE_CPU_GTT_MASK \ - (AMDGPU_GEM_CREATE_CPU_GTT_WC | \ - AMDGPU_GEM_CREATE_CPU_GTT_UC | \ + (AMDGPU_GEM_CREATE_CPU_GTT_USWC | \ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \ AMDGPU_GEM_CREATE_NO_CPU_ACCESS) -- cgit v1.2.3 From dd08fae1e9b2466380d9447a0643c182cd142149 Mon Sep 17 00:00:00 2001 From: "monk.liu" Date: Thu, 7 May 2015 14:19:18 -0400 Subject: drm/amdgpu: fix userptr BO unpin bug (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit sg could point to array of contigiouse page*, only free page could lead to memory leak. v2: use iterator Signed-off-by: monk.liu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 120e6e7c4647..729e0bb3070f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -555,8 +555,7 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) { struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); struct amdgpu_ttm_tt *gtt = (void *)ttm; - struct scatterlist *sg; - int i; + struct sg_page_iter sg_iter; int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); enum dma_data_direction direction = write ? @@ -569,9 +568,8 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) /* free the sg table and pages again */ dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); - for_each_sg(ttm->sg->sgl, sg, ttm->sg->nents, i) { - struct page *page = sg_page(sg); - + for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) { + struct page *page = sg_page_iter_page(&sg_iter); if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) set_page_dirty(page); -- cgit v1.2.3 From a961ea7349d08d5962b6a619f2c2cca670da41ed Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 4 May 2015 13:20:36 +0200 Subject: drm/amdgpu: fix userptr lockup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: Jammy Zhou Reviewed-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c index b3a17a9ab1f4..b1969f2b2038 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c @@ -142,6 +142,9 @@ static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn, list_for_each_entry(bo, &node->bos, mn_list) { + if (!bo->tbo.ttm || bo->tbo.ttm->state != tt_bound) + continue; + r = amdgpu_bo_reserve(bo, true); if (r) { DRM_ERROR("(%ld) failed to reserve user bo\n", r); -- cgit v1.2.3 From f11358daa93a8ae9fdee5cfe6ef7a0ed0027edee Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 5 May 2015 00:56:45 +0200 Subject: drm/amdgpu: remove unsafe context releasing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If ctx was released between put and get, then "get" would crash. Signed-off-by: Marek Olšák Reviewed-by: Christian König Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 235010a83f8f..ffb13a66e288 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -69,7 +69,6 @@ int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uin int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id) { - int r; struct amdgpu_ctx *ctx; struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; @@ -77,15 +76,8 @@ int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint ctx = idr_find(&mgr->ctx_handles, id); rcu_read_unlock(); if (ctx) { - /* if no task is pending on this context, free it */ - r = kref_put(&ctx->refcount, amdgpu_ctx_do_release); - if (r == 1) - return 0;//context is removed successfully - else { - /* context is still in using */ - kref_get(&ctx->refcount); - return -ERESTARTSYS; - } + kref_put(&ctx->refcount, amdgpu_ctx_do_release); + return 0; } return -EINVAL; } -- cgit v1.2.3 From 0147ee0f5921af606ac0f822107b69b53dd29358 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 5 May 2015 20:52:00 +0200 Subject: drm/amdgpu: make the CTX ioctl thread-safe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The existing locks were protecting the list, but not the elements. v2: rename hlock to lock Signed-off-by: Marek Olšák Reviewed-by: Christian König Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 20 ++++++++++---------- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- 3 files changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 65246abcee27..cef3a43ab0aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1056,7 +1056,7 @@ struct amdgpu_ctx_mgr { struct amdgpu_device *adev; struct idr ctx_handles; /* lock for IDR system */ - struct mutex hlock; + struct mutex lock; }; /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index ffb13a66e288..0dc3a4ebd5d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -33,9 +33,7 @@ static void amdgpu_ctx_do_release(struct kref *ref) ctx = container_of(ref, struct amdgpu_ctx, refcount); mgr = &ctx->fpriv->ctx_mgr; - mutex_lock(&mgr->hlock); idr_remove(&mgr->ctx_handles, ctx->id); - mutex_unlock(&mgr->hlock); kfree(ctx); } @@ -49,20 +47,20 @@ int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uin if (!ctx) return -ENOMEM; - mutex_lock(&mgr->hlock); + mutex_lock(&mgr->lock); r = idr_alloc(&mgr->ctx_handles, ctx, 0, 0, GFP_KERNEL); if (r < 0) { - mutex_unlock(&mgr->hlock); + mutex_unlock(&mgr->lock); kfree(ctx); return r; } - mutex_unlock(&mgr->hlock); *id = (uint32_t)r; memset(ctx, 0, sizeof(*ctx)); ctx->id = *id; ctx->fpriv = fpriv; kref_init(&ctx->refcount); + mutex_unlock(&mgr->lock); return 0; } @@ -72,13 +70,14 @@ int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint struct amdgpu_ctx *ctx; struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; - rcu_read_lock(); + mutex_lock(&mgr->lock); ctx = idr_find(&mgr->ctx_handles, id); - rcu_read_unlock(); if (ctx) { kref_put(&ctx->refcount, amdgpu_ctx_do_release); + mutex_unlock(&mgr->lock); return 0; } + mutex_unlock(&mgr->lock); return -EINVAL; } @@ -87,14 +86,15 @@ int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uin struct amdgpu_ctx *ctx; struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; - rcu_read_lock(); + mutex_lock(&mgr->lock); ctx = idr_find(&mgr->ctx_handles, id); - rcu_read_unlock(); if (ctx) { /* state should alter with CS activity */ *state = ctx->state; + mutex_unlock(&mgr->lock); return 0; } + mutex_unlock(&mgr->lock); return -EINVAL; } @@ -111,7 +111,7 @@ void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv) DRM_ERROR("ctx (id=%ul) is still alive\n",ctx->id); } - mutex_destroy(&mgr->hlock); + mutex_destroy(&mgr->lock); } int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 2d50c6dbdcbb..02c450d0be1a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -497,7 +497,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) idr_init(&fpriv->bo_list_handles); /* init context manager */ - mutex_init(&fpriv->ctx_mgr.hlock); + mutex_init(&fpriv->ctx_mgr.lock); idr_init(&fpriv->ctx_mgr.ctx_handles); fpriv->ctx_mgr.adev = adev; -- cgit v1.2.3 From 74a5d1656e165d5457be64b4d78d3259c2946e93 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Fri, 8 May 2015 14:46:49 +0800 Subject: drm/amdgpu: allow unaligned memory access (v2) Set up the CP and SDMA for proper unaligned memory access. Required for OpenCL 2.x v2: udpate commit message Signed-off-by: Jack Xiao Reviewed-by: Monk Liu Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 6 +++++- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 +++++- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 5 ++++- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 ++++- 5 files changed, 22 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index ae2bb26fa46e..037e3db69547 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -33,6 +33,8 @@ #include "bif/bif_4_1_sh_mask.h" #include "gca/gfx_7_2_d.h" +#include "gca/gfx_7_2_enum.h" +#include "gca/gfx_7_2_sh_mask.h" #include "gmc/gmc_7_1_d.h" #include "gmc/gmc_7_1_sh_mask.h" @@ -837,6 +839,8 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, { u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ + u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); if (vm_id < 8) { @@ -857,7 +861,7 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); amdgpu_ring_write(ring, mmSH_MEM_CONFIG); - amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, sh_mem_cfg); amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 675b096417f4..26df23eaf09e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2022,6 +2022,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) u32 gb_addr_config; u32 mc_shared_chmap, mc_arb_ramcfg; u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; + u32 sh_mem_cfg; u32 tmp; int i; @@ -2214,11 +2215,14 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) /* XXX SH_MEM regs */ /* where to put LDS, scratch, GPUVM in FSA64 space */ + sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); + mutex_lock(&adev->srbm_mutex); for (i = 0; i < 16; i++) { cik_srbm_select(adev, 0, 0, 0, i); /* CP and shaders */ - WREG32(mmSH_MEM_CONFIG, 0); + WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); WREG32(mmSH_MEM_APE1_BASE, 1); WREG32(mmSH_MEM_APE1_LIMIT, 0); WREG32(mmSH_MEM_BASES, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index a8397dd2bce4..3762998df351 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -2050,10 +2050,14 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) if (i == 0) { tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); WREG32(mmSH_MEM_CONFIG, tmp); } else { tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC); + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); WREG32(mmSH_MEM_CONFIG, tmp); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index a83029d548c1..389509aeddf8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -36,6 +36,7 @@ #include "gmc/gmc_8_1_sh_mask.h" #include "gca/gfx_8_0_d.h" +#include "gca/gfx_8_0_enum.h" #include "gca/gfx_8_0_sh_mask.h" #include "bif/bif_5_0_d.h" @@ -900,6 +901,8 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { u32 srbm_gfx_cntl = 0; + u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); @@ -925,7 +928,7 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); amdgpu_ring_write(ring, mmSH_MEM_CONFIG); - amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, sh_mem_cfg); amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index dd547c7f6cbc..d3eda315e719 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -36,6 +36,7 @@ #include "gmc/gmc_8_1_sh_mask.h" #include "gca/gfx_8_0_d.h" +#include "gca/gfx_8_0_enum.h" #include "gca/gfx_8_0_sh_mask.h" #include "bif/bif_5_0_d.h" @@ -963,6 +964,8 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { u32 srbm_gfx_cntl = 0; + u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); @@ -988,7 +991,7 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); amdgpu_ring_write(ring, mmSH_MEM_CONFIG); - amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, sh_mem_cfg); amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); -- cgit v1.2.3 From 66b3cf2ab38f47db2d07fe24a00972fbf822cd74 Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Fri, 8 May 2015 17:29:40 +0800 Subject: drm/amdgpu: add ctx_id to the WAIT_CS IOCTL (v4) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is required to support fence per context. v2: add amdgpu_ctx_get/put v3: improve get/put v4: squash hlock fix Signed-off-by: Jammy Zhou Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 30 ++++++++++++++++++++++++++++++ include/uapi/drm/amdgpu_drm.h | 2 +- 4 files changed, 39 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index cef3a43ab0aa..bf0c607de195 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1902,6 +1902,8 @@ int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id,struct amdgpu_ctx_state *state); void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv); +struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); +int amdgpu_ctx_put(struct amdgpu_ctx *ctx); extern int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index ffbe9aa9f232..86b93245bf9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -768,8 +768,13 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, uint64_t seq[AMDGPU_MAX_RINGS] = {0}; struct amdgpu_ring *ring = NULL; unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); + struct amdgpu_ctx *ctx; long r; + ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); + if (ctx == NULL) + return -EINVAL; + r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, wait->in.ring, &ring); if (r) @@ -778,6 +783,7 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, seq[ring->idx] = wait->in.handle; r = amdgpu_fence_wait_seq_timeout(adev, seq, true, timeout); + amdgpu_ctx_put(ctx); if (r < 0) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 0dc3a4ebd5d3..bcd332e085f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -151,3 +151,33 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, return r; } + +struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) +{ + struct amdgpu_ctx *ctx; + struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; + + mutex_lock(&mgr->lock); + ctx = idr_find(&mgr->ctx_handles, id); + if (ctx) + kref_get(&ctx->refcount); + mutex_unlock(&mgr->lock); + return ctx; +} + +int amdgpu_ctx_put(struct amdgpu_ctx *ctx) +{ + struct amdgpu_fpriv *fpriv; + struct amdgpu_ctx_mgr *mgr; + + if (ctx == NULL) + return -EINVAL; + + fpriv = ctx->fpriv; + mgr = &fpriv->ctx_mgr; + mutex_lock(&mgr->lock); + kref_put(&ctx->refcount, amdgpu_ctx_do_release); + mutex_unlock(&mgr->lock); + + return 0; +} diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 77bc5740fd7c..ca0ea1efa3f4 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -260,7 +260,7 @@ struct drm_amdgpu_wait_cs_in { uint32_t ip_type; uint32_t ip_instance; uint32_t ring; - uint32_t _pad; + uint32_t ctx_id; }; struct drm_amdgpu_wait_cs_out { -- cgit v1.2.3 From 72efa7ebdea084b96f25021d0ba9c29074c2906f Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Fri, 8 May 2015 22:18:47 +0800 Subject: drm/amdgpu: check context id for context switching (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit check the filp is not robust, and sometimes different contexts may have same filp value. v2: check both filp and ctx_id Signed-off-by: Jammy Zhou Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index bf0c607de195..a88302c0c93a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -945,6 +945,7 @@ struct amdgpu_ring { unsigned next_rptr_offs; unsigned fence_offs; struct drm_file *current_filp; + unsigned current_ctx; bool need_ctx_switch; enum amdgpu_ring_type type; char name[16]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 86b93245bf9d..1035e443700f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -642,8 +642,10 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, ib->is_const_ib = true; if (chunk_ib->flags & AMDGPU_IB_FLAG_GDS) ib->gds_needed = true; - if (ib->ring->current_filp != parser->filp) { + if ((ib->ring->current_filp != parser->filp) || + (ib->ring->current_ctx != parser->ctx_id)) { ib->ring->need_ctx_switch = true; + ib->ring->current_ctx = parser->ctx_id; ib->ring->current_filp = parser->filp; } -- cgit v1.2.3 From de807f818b953f11b9a132a2d1997711a79bbfa3 Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Mon, 11 May 2015 23:41:41 +0800 Subject: drm/amdgpu: add flags for amdgpu_ib structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jammy Zhou Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 ++---- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- 5 files changed, 7 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index a88302c0c93a..aaa62f33870f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -892,13 +892,12 @@ struct amdgpu_ib { struct amdgpu_fence *fence; struct amdgpu_user_fence *user; struct amdgpu_vm *vm; - bool is_const_ib; bool flush_hdp_writefifo; struct amdgpu_sync sync; - bool gds_needed; uint32_t gds_base, gds_size; uint32_t gws_base, gws_size; uint32_t oa_base, oa_size; + uint32_t flags; }; enum amdgpu_ring_type { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 1035e443700f..de17f845a84b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -638,10 +638,8 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, } ib->length_dw = chunk_ib->ib_bytes / 4; - if (chunk_ib->flags & AMDGPU_IB_FLAG_CE) - ib->is_const_ib = true; - if (chunk_ib->flags & AMDGPU_IB_FLAG_GDS) - ib->gds_needed = true; + ib->flags = chunk_ib->flags; + if ((ib->ring->current_filp != parser->filp) || (ib->ring->current_ctx != parser->ctx_id)) { ib->ring->need_ctx_switch = true; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 847cab2b3fff..a83ff03ffc80 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -88,13 +88,13 @@ int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, ib->fence = NULL; ib->user = NULL; ib->vm = vm; - ib->is_const_ib = false; ib->gds_base = 0; ib->gds_size = 0; ib->gws_base = 0; ib->gws_size = 0; ib->oa_base = 0; ib->oa_size = 0; + ib->flags = 0; return 0; } @@ -179,7 +179,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update); } - if (ring->funcs->emit_gds_switch && ib->vm && ib->gds_needed) + if (ring->funcs->emit_gds_switch && ib->vm && (ib->flags & AMDGPU_IB_FLAG_GDS)) amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id, ib->gds_base, ib->gds_size, ib->gws_base, ib->gws_size, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 26df23eaf09e..7428c4305418 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2544,7 +2544,7 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring, ring->need_ctx_switch = false; } - if (ib->is_const_ib) + if (ib->flags & AMDGPU_IB_FLAG_CE) header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); else header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 3762998df351..48de9204ff5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3673,7 +3673,7 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring, ring->need_ctx_switch = false; } - if (ib->is_const_ib) + if (ib->flags & AMDGPU_IB_FLAG_CE) header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); else header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); -- cgit v1.2.3 From aa2bdb2476206c7de4473850039daa705230c27b Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Mon, 11 May 2015 23:49:34 +0800 Subject: drm/amdgpu: add CE preamble flag v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CE preamble IB can be dropped for the same context v2: use the flags directly v3: remove 'CE' for potential preamble usage by other rings Signed-off-by: Jammy Zhou Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 7 +++++++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 7 +++++++ include/uapi/drm/amdgpu_drm.h | 3 +++ 3 files changed, 17 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 7428c4305418..cec46ebae5f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2518,6 +2518,13 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring, { u32 header, control = 0; u32 next_rptr = ring->wptr + 5; + + /* drop the CE preamble IB for the same context */ + if ((ring->type == AMDGPU_RING_TYPE_GFX) && + (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && + !ring->need_ctx_switch) + return; + if (ring->type == AMDGPU_RING_TYPE_COMPUTE) control |= INDIRECT_BUFFER_VALID; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 48de9204ff5e..fc8c46209db4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3647,6 +3647,13 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring, { u32 header, control = 0; u32 next_rptr = ring->wptr + 5; + + /* drop the CE preamble IB for the same context */ + if ((ring->type == AMDGPU_RING_TYPE_GFX) && + (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && + !ring->need_ctx_switch) + return; + if (ring->type == AMDGPU_RING_TYPE_COMPUTE) control |= INDIRECT_BUFFER_VALID; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index ca0ea1efa3f4..fb428fe54186 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -369,6 +369,9 @@ union drm_amdgpu_cs { /* GDS is used by this IB */ #define AMDGPU_IB_FLAG_GDS (1<<1) +/* CE Preamble */ +#define AMDGPU_IB_FLAG_PREAMBLE (1<<2) + struct drm_amdgpu_cs_chunk_ib { /** * Handle of GEM object to be used as IB or 0 if it is already in -- cgit v1.2.3 From 66782cec7ad8f48c09d96ee59b713f694265cfa1 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 May 2015 13:52:09 +0200 Subject: drm/amdgpu: always emit GDS switch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Otherwise a process can access the GDS data of another process. Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Jammy Zhou Reviewed-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index a83ff03ffc80..f2442b2cec00 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -179,7 +179,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update); } - if (ring->funcs->emit_gds_switch && ib->vm && (ib->flags & AMDGPU_IB_FLAG_GDS)) + if (vm && ring->funcs->emit_gds_switch) amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id, ib->gds_base, ib->gds_size, ib->gws_base, ib->gws_size, -- cgit v1.2.3 From d2edb07b10fce5127a60671b55ca53921c212bc3 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 May 2015 14:10:34 +0200 Subject: drm/amdgpu: cleanup HDP flush handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Jammy Zhou Reviewed-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 15 +++------------ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 11 +++-------- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 9 ++------- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 13 ++----------- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 15 +++------------ 7 files changed, 18 insertions(+), 54 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index aaa62f33870f..72d9d9ec5c9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -382,6 +382,7 @@ struct amdgpu_ring_funcs { bool emit_wait); void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr); + void (*emit_hdp_flush)(struct amdgpu_ring *ring); void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, uint32_t gds_base, uint32_t gds_size, uint32_t gws_base, uint32_t gws_size, @@ -892,7 +893,6 @@ struct amdgpu_ib { struct amdgpu_fence *fence; struct amdgpu_user_fence *user; struct amdgpu_vm *vm; - bool flush_hdp_writefifo; struct amdgpu_sync sync; uint32_t gds_base, gds_size; uint32_t gws_base, gws_size; @@ -2203,6 +2203,7 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) #define amdgpu_ring_emit_fence(r, addr, seq, write64bit) (r)->funcs->emit_fence((r), (addr), (seq), (write64bit)) #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) +#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index f2442b2cec00..66c66f83b407 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -143,7 +143,6 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, struct amdgpu_ib *ib = &ibs[0]; unsigned i; int r = 0; - bool flush_hdp = true; if (num_ibs == 0) return -EINVAL; @@ -185,6 +184,9 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, ib->gws_base, ib->gws_size, ib->oa_base, ib->oa_size); + if (ring->funcs->emit_hdp_flush) + amdgpu_ring_emit_hdp_flush(ring); + for (i = 0; i < num_ibs; ++i) { ib = &ibs[i]; @@ -192,8 +194,6 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, amdgpu_ring_unlock_undo(ring); return -EINVAL; } - ib->flush_hdp_writefifo = flush_hdp; - flush_hdp = false; amdgpu_ring_emit_ib(ring, ib); } diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 037e3db69547..d5055ea4d112 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -188,8 +188,6 @@ static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); } -static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *); - /** * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine * @@ -204,9 +202,6 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; u32 next_rptr = ring->wptr + 5; - if (ib->flush_hdp_writefifo) - next_rptr += 6; - while ((next_rptr & 7) != 4) next_rptr++; @@ -217,11 +212,6 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, 1); /* number of DWs to follow */ amdgpu_ring_write(ring, next_rptr); - if (ib->flush_hdp_writefifo) { - /* flush HDP */ - cik_sdma_hdp_flush_ring_emit(ring); - } - /* IB packet must end on a 8 DW boundary */ while ((ring->wptr & 7) != 4) amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); @@ -233,13 +223,13 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, } /** - * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring + * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring * * @ring: amdgpu ring pointer * * Emit an hdp flush packet on the requested DMA ring. */ -static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *ring) +static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ @@ -1317,6 +1307,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { .emit_fence = cik_sdma_ring_emit_fence, .emit_semaphore = cik_sdma_ring_emit_semaphore, .emit_vm_flush = cik_sdma_ring_emit_vm_flush, + .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, .test_ring = cik_sdma_ring_test_ring, .test_ib = cik_sdma_ring_test_ib, .is_lockup = cik_sdma_ring_is_lockup, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index cec46ebae5f7..855b5272f4b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2366,14 +2366,14 @@ static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) } /** - * gfx_v7_0_hdp_flush_cp_ring_emit - emit an hdp flush on the cp + * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp * * @adev: amdgpu_device pointer * @ridx: amdgpu ring index * * Emits an hdp flush on the cp. */ -static void gfx_v7_0_hdp_flush_cp_ring_emit(struct amdgpu_ring *ring) +static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask; @@ -2528,9 +2528,6 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring, if (ring->type == AMDGPU_RING_TYPE_COMPUTE) control |= INDIRECT_BUFFER_VALID; - if (ib->flush_hdp_writefifo) - next_rptr += 7; - if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) next_rptr += 2; @@ -2541,9 +2538,6 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); amdgpu_ring_write(ring, next_rptr); - if (ib->flush_hdp_writefifo) - gfx_v7_0_hdp_flush_cp_ring_emit(ring); - /* insert SWITCH_BUFFER packet before first IB in the ring frame */ if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) { amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); @@ -5522,6 +5516,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .emit_semaphore = gfx_v7_0_ring_emit_semaphore, .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, .test_ring = gfx_v7_0_ring_test_ring, .test_ib = gfx_v7_0_ring_test_ib, .is_lockup = gfx_v7_0_ring_is_lockup, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index fc8c46209db4..63ed3b01cea1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3610,7 +3610,7 @@ static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) } } -static void gfx_v8_0_hdp_flush_cp_ring_emit(struct amdgpu_ring *ring) +static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask, reg_mem_engine; @@ -3657,9 +3657,6 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring, if (ring->type == AMDGPU_RING_TYPE_COMPUTE) control |= INDIRECT_BUFFER_VALID; - if (ib->flush_hdp_writefifo) - next_rptr += 7; - if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) next_rptr += 2; @@ -3670,9 +3667,6 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); amdgpu_ring_write(ring, next_rptr); - if (ib->flush_hdp_writefifo) - gfx_v8_0_hdp_flush_cp_ring_emit(ring); - /* insert SWITCH_BUFFER packet before first IB in the ring frame */ if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) { amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); @@ -4149,6 +4143,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .emit_semaphore = gfx_v8_0_ring_emit_semaphore, .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, .test_ring = gfx_v8_0_ring_test_ring, .test_ib = gfx_v8_0_ring_test_ib, .is_lockup = gfx_v8_0_ring_is_lockup, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 389509aeddf8..f1423a412867 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -214,8 +214,6 @@ static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); } -static void sdma_v2_4_hdp_flush_ring_emit(struct amdgpu_ring *); - /** * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine * @@ -230,9 +228,6 @@ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; u32 next_rptr = ring->wptr + 5; - if (ib->flush_hdp_writefifo) - next_rptr += 6; - while ((next_rptr & 7) != 2) next_rptr++; @@ -245,11 +240,6 @@ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); amdgpu_ring_write(ring, next_rptr); - if (ib->flush_hdp_writefifo) { - /* flush HDP */ - sdma_v2_4_hdp_flush_ring_emit(ring); - } - /* IB packet must end on a 8 DW boundary */ while ((ring->wptr & 7) != 2) amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP)); @@ -271,7 +261,7 @@ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, * * Emit an hdp flush packet on the requested DMA ring. */ -static void sdma_v2_4_hdp_flush_ring_emit(struct amdgpu_ring *ring) +static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask = 0; @@ -1340,6 +1330,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { .emit_fence = sdma_v2_4_ring_emit_fence, .emit_semaphore = sdma_v2_4_ring_emit_semaphore, .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, + .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, .test_ring = sdma_v2_4_ring_test_ring, .test_ib = sdma_v2_4_ring_test_ib, .is_lockup = sdma_v2_4_ring_is_lockup, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index d3eda315e719..7c4abff5005d 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -269,8 +269,6 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) } } -static void sdma_v3_0_hdp_flush_ring_emit(struct amdgpu_ring *); - /** * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine * @@ -285,9 +283,6 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; u32 next_rptr = ring->wptr + 5; - if (ib->flush_hdp_writefifo) - next_rptr += 6; - while ((next_rptr & 7) != 2) next_rptr++; next_rptr += 6; @@ -299,11 +294,6 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); amdgpu_ring_write(ring, next_rptr); - /* flush HDP */ - if (ib->flush_hdp_writefifo) { - sdma_v3_0_hdp_flush_ring_emit(ring); - } - /* IB packet must end on a 8 DW boundary */ while ((ring->wptr & 7) != 2) amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP)); @@ -320,13 +310,13 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, } /** - * sdma_v3_0_hdp_flush_ring_emit - emit an hdp flush on the DMA ring + * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring * * @ring: amdgpu ring pointer * * Emit an hdp flush packet on the requested DMA ring. */ -static void sdma_v3_0_hdp_flush_ring_emit(struct amdgpu_ring *ring) +static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask = 0; @@ -1407,6 +1397,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { .emit_fence = sdma_v3_0_ring_emit_fence, .emit_semaphore = sdma_v3_0_ring_emit_semaphore, .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, + .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, .test_ring = sdma_v3_0_ring_test_ring, .test_ib = sdma_v3_0_ring_test_ib, .is_lockup = sdma_v3_0_ring_is_lockup, -- cgit v1.2.3 From d919ad49ac04e1e417ea511d61455786a0f0fdb7 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 May 2015 14:32:17 +0200 Subject: drm/amdgpu: fix dereference before check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Jammy Zhou Reviewed-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 66c66f83b407..74ed94ee7102 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -138,9 +138,9 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib) int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, struct amdgpu_ib *ibs, void *owner) { - struct amdgpu_ring *ring; - struct amdgpu_vm *vm = ibs->vm; struct amdgpu_ib *ib = &ibs[0]; + struct amdgpu_ring *ring; + struct amdgpu_vm *vm; unsigned i; int r = 0; @@ -148,6 +148,8 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, return -EINVAL; ring = ibs->ring; + vm = ibs->vm; + if (!ring->ready) { dev_err(adev->dev, "couldn't schedule ib\n"); return -EINVAL; -- cgit v1.2.3 From 3cb485f34049b7f3a00f6f73d2325e0858f64ddb Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 11 May 2015 15:34:59 +0200 Subject: drm/amdgpu: fix context switch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Properly protect the state and also handle submission failures. Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Jammy Zhou Reviewed-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +++---- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 16 ++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 8 +++++++- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 ++++---- 5 files changed, 26 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 72d9d9ec5c9f..003fa2d12bfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -893,6 +893,7 @@ struct amdgpu_ib { struct amdgpu_fence *fence; struct amdgpu_user_fence *user; struct amdgpu_vm *vm; + struct amdgpu_ctx *ctx; struct amdgpu_sync sync; uint32_t gds_base, gds_size; uint32_t gws_base, gws_size; @@ -943,9 +944,7 @@ struct amdgpu_ring { unsigned wptr_offs; unsigned next_rptr_offs; unsigned fence_offs; - struct drm_file *current_filp; - unsigned current_ctx; - bool need_ctx_switch; + struct amdgpu_ctx *current_ctx; enum amdgpu_ring_type type; char name[16]; }; @@ -1236,7 +1235,7 @@ struct amdgpu_cs_chunk { struct amdgpu_cs_parser { struct amdgpu_device *adev; struct drm_file *filp; - uint32_t ctx_id; + struct amdgpu_ctx *ctx; struct amdgpu_bo_list *bo_list; /* chunks */ unsigned nchunks; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index de17f845a84b..ecb30a1a73cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -138,7 +138,11 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) if (!cs->in.num_chunks) goto out; - p->ctx_id = cs->in.ctx_id; + p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); + if (!p->ctx) { + r = -EINVAL; + goto out; + } p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); /* get chunks */ @@ -445,6 +449,8 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo &parser->validated); } + if (parser->ctx) + amdgpu_ctx_put(parser->ctx); if (parser->bo_list) amdgpu_bo_list_put(parser->bo_list); drm_free_large(parser->vm_bos); @@ -639,13 +645,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, ib->length_dw = chunk_ib->ib_bytes / 4; ib->flags = chunk_ib->flags; - - if ((ib->ring->current_filp != parser->filp) || - (ib->ring->current_ctx != parser->ctx_id)) { - ib->ring->need_ctx_switch = true; - ib->ring->current_ctx = parser->ctx_id; - ib->ring->current_filp = parser->filp; - } + ib->ctx = parser->ctx; ib_bo = &parser->ib_bos[j]; ib_bo->robj = aobj; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 74ed94ee7102..560c5fd347be 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -140,6 +140,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, { struct amdgpu_ib *ib = &ibs[0]; struct amdgpu_ring *ring; + struct amdgpu_ctx *ctx, *old_ctx; struct amdgpu_vm *vm; unsigned i; int r = 0; @@ -148,6 +149,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, return -EINVAL; ring = ibs->ring; + ctx = ibs->ctx; vm = ibs->vm; if (!ring->ready) { @@ -189,19 +191,23 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, if (ring->funcs->emit_hdp_flush) amdgpu_ring_emit_hdp_flush(ring); + old_ctx = ring->current_ctx; for (i = 0; i < num_ibs; ++i) { ib = &ibs[i]; - if (ib->ring != ring) { + if (ib->ring != ring || ib->ctx != ctx || ib->vm != vm) { + ring->current_ctx = old_ctx; amdgpu_ring_unlock_undo(ring); return -EINVAL; } amdgpu_ring_emit_ib(ring, ib); + ring->current_ctx = ctx; } r = amdgpu_fence_emit(ring, owner, &ib->fence); if (r) { dev_err(adev->dev, "failed to emit fence (%d)\n", r); + ring->current_ctx = old_ctx; amdgpu_ring_unlock_undo(ring); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 855b5272f4b5..5315c13a8921 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2516,19 +2516,20 @@ static bool gfx_v7_0_ring_emit_semaphore(struct amdgpu_ring *ring, static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) { + bool need_ctx_switch = ring->current_ctx != ib->ctx; u32 header, control = 0; u32 next_rptr = ring->wptr + 5; /* drop the CE preamble IB for the same context */ if ((ring->type == AMDGPU_RING_TYPE_GFX) && (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && - !ring->need_ctx_switch) + !need_ctx_switch) return; if (ring->type == AMDGPU_RING_TYPE_COMPUTE) control |= INDIRECT_BUFFER_VALID; - if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) + if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) next_rptr += 2; next_rptr += 4; @@ -2539,10 +2540,9 @@ static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, next_rptr); /* insert SWITCH_BUFFER packet before first IB in the ring frame */ - if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) { + if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) { amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); amdgpu_ring_write(ring, 0); - ring->need_ctx_switch = false; } if (ib->flags & AMDGPU_IB_FLAG_CE) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 63ed3b01cea1..188a7abbddaf 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3645,19 +3645,20 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) { + bool need_ctx_switch = ring->current_ctx != ib->ctx; u32 header, control = 0; u32 next_rptr = ring->wptr + 5; /* drop the CE preamble IB for the same context */ if ((ring->type == AMDGPU_RING_TYPE_GFX) && (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && - !ring->need_ctx_switch) + !need_ctx_switch) return; if (ring->type == AMDGPU_RING_TYPE_COMPUTE) control |= INDIRECT_BUFFER_VALID; - if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) + if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) next_rptr += 2; next_rptr += 4; @@ -3668,10 +3669,9 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, next_rptr); /* insert SWITCH_BUFFER packet before first IB in the ring frame */ - if (ring->need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) { + if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) { amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); amdgpu_ring_write(ring, 0); - ring->need_ctx_switch = false; } if (ib->flags & AMDGPU_IB_FLAG_CE) -- cgit v1.2.3 From 02b70c8c9f0351f5ddf70716b9049f3fe50d62e7 Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Tue, 12 May 2015 22:46:45 +0800 Subject: drm/amdgpu: expose the max virtual address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jammy Zhou Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 + include/uapi/drm/amdgpu_drm.h | 2 ++ 2 files changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 02c450d0be1a..35185d6b7d46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -428,6 +428,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file if (adev->flags & AMDGPU_IS_APU) dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; + dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; dev_info.virtual_address_alignment = max(PAGE_SIZE, 0x10000UL); dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * AMDGPU_GPU_PAGE_SIZE; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index fb428fe54186..65da7cd16c0f 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -560,6 +560,8 @@ struct drm_amdgpu_info_device { uint64_t ids_flags; /** Starting virtual address for UMDs. */ uint64_t virtual_address_offset; + /** The maximum virtual address */ + uint64_t virtual_address_max; /** Required alignment of virtual addresses. */ uint32_t virtual_address_alignment; /** Page table entry - fragment size */ -- cgit v1.2.3 From 4b095304ea7f73c178cd906df37185c0b9ad9a60 Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Tue, 12 May 2015 23:17:19 +0800 Subject: drm/amdgpu: do necessary NULL check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jammy Zhou Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index 855d56ac7115..21accbdd0a1a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -101,6 +101,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, unsigned i; int r = 0; + if (resv == NULL) + return -EINVAL; + /* always sync to the exclusive fence */ f = reservation_object_get_excl(resv); fence = f ? to_amdgpu_fence(f) : NULL; @@ -116,12 +119,12 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, for (i = 0; i < flist->shared_count; ++i) { f = rcu_dereference_protected(flist->shared[i], reservation_object_held(resv)); - fence = to_amdgpu_fence(f); + fence = f ? to_amdgpu_fence(f) : NULL; if (fence && fence->ring->adev == adev) { if (fence->owner != owner || fence->owner == AMDGPU_FENCE_OWNER_UNDEFINED) amdgpu_sync_fence(sync, fence); - } else { + } else if (f) { r = fence_wait(f, true); if (r) break; -- cgit v1.2.3 From c65444fe054fb69e95444ddd545adf43f682bb41 Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Wed, 13 May 2015 22:49:04 +0800 Subject: drm/amdgpu: switch to amdgpu folder for firmware files v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: keep using radeon folder for CIK Signed-off-by: Jammy Zhou Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 +-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 52 ++++++++++++++++---------------- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/iceland_dpm.c | 4 +-- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 ++--- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 12 ++++---- drivers/gpu/drm/amd/amdgpu/tonga_dpm.c | 4 +-- 8 files changed, 47 insertions(+), 47 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index c03bce6f32a9..4b0be906d235 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -50,8 +50,8 @@ #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" #endif -#define FIRMWARE_TONGA "radeon/tonga_uvd.bin" -#define FIRMWARE_CARRIZO "radeon/carrizo_uvd.bin" +#define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" +#define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" /** * amdgpu_uvd_cs_ctx - Command submission parser context diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index c65d93cb540d..803ee601c399 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -46,8 +46,8 @@ #define FIRMWARE_HAWAII "radeon/hawaii_vce.bin" #define FIRMWARE_MULLINS "radeon/mullins_vce.bin" #endif -#define FIRMWARE_TONGA "radeon/tonga_vce.bin" -#define FIRMWARE_CARRIZO "radeon/carrizo_vce.bin" +#define FIRMWARE_TONGA "amdgpu/tonga_vce.bin" +#define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin" #ifdef CONFIG_DRM_AMDGPU_CIK MODULE_FIRMWARE(FIRMWARE_BONAIRE); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 188a7abbddaf..4597256cc6e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -66,26 +66,26 @@ #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT) #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) -MODULE_FIRMWARE("radeon/carrizo_ce.bin"); -MODULE_FIRMWARE("radeon/carrizo_pfp.bin"); -MODULE_FIRMWARE("radeon/carrizo_me.bin"); -MODULE_FIRMWARE("radeon/carrizo_mec.bin"); -MODULE_FIRMWARE("radeon/carrizo_mec2.bin"); -MODULE_FIRMWARE("radeon/carrizo_rlc.bin"); - -MODULE_FIRMWARE("radeon/tonga_ce.bin"); -MODULE_FIRMWARE("radeon/tonga_pfp.bin"); -MODULE_FIRMWARE("radeon/tonga_me.bin"); -MODULE_FIRMWARE("radeon/tonga_mec.bin"); -MODULE_FIRMWARE("radeon/tonga_mec2.bin"); -MODULE_FIRMWARE("radeon/tonga_rlc.bin"); - -MODULE_FIRMWARE("radeon/topaz_ce.bin"); -MODULE_FIRMWARE("radeon/topaz_pfp.bin"); -MODULE_FIRMWARE("radeon/topaz_me.bin"); -MODULE_FIRMWARE("radeon/topaz_mec.bin"); -MODULE_FIRMWARE("radeon/topaz_mec2.bin"); -MODULE_FIRMWARE("radeon/topaz_rlc.bin"); +MODULE_FIRMWARE("amdgpu/carrizo_ce.bin"); +MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin"); +MODULE_FIRMWARE("amdgpu/carrizo_me.bin"); +MODULE_FIRMWARE("amdgpu/carrizo_mec.bin"); +MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin"); +MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/tonga_ce.bin"); +MODULE_FIRMWARE("amdgpu/tonga_pfp.bin"); +MODULE_FIRMWARE("amdgpu/tonga_me.bin"); +MODULE_FIRMWARE("amdgpu/tonga_mec.bin"); +MODULE_FIRMWARE("amdgpu/tonga_mec2.bin"); +MODULE_FIRMWARE("amdgpu/tonga_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/topaz_ce.bin"); +MODULE_FIRMWARE("amdgpu/topaz_pfp.bin"); +MODULE_FIRMWARE("amdgpu/topaz_me.bin"); +MODULE_FIRMWARE("amdgpu/topaz_mec.bin"); +MODULE_FIRMWARE("amdgpu/topaz_mec2.bin"); +MODULE_FIRMWARE("amdgpu/topaz_rlc.bin"); static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = { @@ -597,7 +597,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) BUG(); } - snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); if (err) goto out; @@ -605,7 +605,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) if (err) goto out; - snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); if (err) goto out; @@ -613,7 +613,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) if (err) goto out; - snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); if (err) goto out; @@ -621,13 +621,13 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) if (err) goto out; - snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); if (err) goto out; err = amdgpu_ucode_validate(adev->gfx.rlc_fw); - snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); if (err) goto out; @@ -635,7 +635,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) if (err) goto out; - snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); if (!err) { err = amdgpu_ucode_validate(adev->gfx.mec2_fw); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index ac8cff85cde3..7f6c52ff832f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -41,8 +41,8 @@ static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); -MODULE_FIRMWARE("radeon/topaz_mc.bin"); -MODULE_FIRMWARE("radeon/tonga_mc.bin"); +MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); +MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); static const u32 golden_settings_tonga_a11[] = { @@ -206,7 +206,7 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) default: BUG(); } - snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); err = request_firmware(&adev->mc.fw, fw_name, adev->dev); if (err) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c index 8f5c54be70b0..0688b88cb170 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c @@ -26,7 +26,7 @@ #include "amdgpu.h" #include "iceland_smumgr.h" -MODULE_FIRMWARE("radeon/topaz_smc.bin"); +MODULE_FIRMWARE("amdgpu/topaz_smc.bin"); static void iceland_dpm_set_funcs(struct amdgpu_device *adev); @@ -39,7 +39,7 @@ static int iceland_dpm_early_init(struct amdgpu_device *adev) static int iceland_dpm_init_microcode(struct amdgpu_device *adev) { - char fw_name[30] = "radeon/topaz_smc.bin"; + char fw_name[30] = "amdgpu/topaz_smc.bin"; int err; err = request_firmware(&adev->pm.fw, fw_name, adev->dev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index f1423a412867..99b8b326e999 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -49,8 +49,8 @@ static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); -MODULE_FIRMWARE("radeon/topaz_sdma.bin"); -MODULE_FIRMWARE("radeon/topaz_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); +MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin"); static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = { @@ -133,9 +133,9 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) for (i = 0; i < SDMA_MAX_INSTANCE; i++) { if (i == 0) - snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); else - snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); if (err) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 7c4abff5005d..86a5278b65f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -49,10 +49,10 @@ static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); -MODULE_FIRMWARE("radeon/tonga_sdma.bin"); -MODULE_FIRMWARE("radeon/tonga_sdma1.bin"); -MODULE_FIRMWARE("radeon/carrizo_sdma.bin"); -MODULE_FIRMWARE("radeon/carrizo_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); +MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); +MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = { @@ -174,9 +174,9 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) for (i = 0; i < SDMA_MAX_INSTANCE; i++) { if (i == 0) - snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); else - snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); if (err) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c index 98bd707ac5dc..cf97d496a7a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c @@ -26,7 +26,7 @@ #include "amdgpu.h" #include "tonga_smumgr.h" -MODULE_FIRMWARE("radeon/tonga_smc.bin"); +MODULE_FIRMWARE("amdgpu/tonga_smc.bin"); static void tonga_dpm_set_funcs(struct amdgpu_device *adev); @@ -39,7 +39,7 @@ static int tonga_dpm_early_init(struct amdgpu_device *adev) static int tonga_dpm_init_microcode(struct amdgpu_device *adev) { - char fw_name[30] = "radeon/tonga_smc.bin"; + char fw_name[30] = "amdgpu/tonga_smc.bin"; int err; err = request_firmware(&adev->pm.fw, fw_name, adev->dev); -- cgit v1.2.3 From 86c2b79062be6a328014d90d1e4ef6a0afae02ad Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Wed, 13 May 2015 22:52:42 +0800 Subject: drm/amdgpu: rewording some left radeons MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jammy Zhou Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 003fa2d12bfb..66b5bd058799 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -2164,7 +2164,7 @@ static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) { if (ring->count_dw <= 0) - DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); + DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); ring->ring[ring->wptr++] = v; ring->wptr &= ring->ptr_mask; ring->count_dw--; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index fc63855ed517..be4d53508680 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -193,13 +193,13 @@ static bool amdgpu_fence_activity(struct amdgpu_ring *ring) * xchg of the current process. * * More over for this to go in infinite loop there need to be - * continuously new fence signaled ie radeon_fence_read needs + * continuously new fence signaled ie amdgpu_fence_read needs * to return a different value each time for both the currently * polling process and the other process that xchg the last_seq * btw atomic read and xchg of the current process. And the * value the other process set as last seq must be higher than * the seq value we just read. Which means that current process - * need to be interrupted after radeon_fence_read and before + * need to be interrupted after amdgpu_fence_read and before * atomic xchg. * * To be even more safe we count the number of time we loop and -- cgit v1.2.3 From fb4f173734e010f83ce63e9fc33270648bc8d4e9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 12 May 2015 13:06:45 -0400 Subject: drm/amdgpu: add new bonaire pci id MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Reviewed-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index dfd426132792..c392812abd48 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -173,6 +173,7 @@ static struct pci_device_id pciidlist[] = { {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, + {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, /* Hawaii */ {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, -- cgit v1.2.3 From 1f8d962513c6d516b51a643d105fc1335f3214d0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 12 May 2015 13:10:05 -0400 Subject: drm/amdgpu: add some new tonga pci ids MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Reviewed-by: Jammy Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index c392812abd48..6edacceb6cfd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -232,8 +232,10 @@ static struct pci_device_id pciidlist[] = { {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, + {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, + {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, /* carrizo */ -- cgit v1.2.3 From d94aed5a6c947b1fda346aff1fa316dacf4a1a5a Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 5 May 2015 21:13:49 +0200 Subject: drm/amdgpu: add and implement the GPU reset status query MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marek Olšák Reviewed-by: Christian König Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 36 +++++++++++++++++++----------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + include/uapi/drm/amdgpu_drm.h | 11 ++++++++- 4 files changed, 37 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 66b5bd058799..ebff89eb2f4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1040,7 +1040,7 @@ struct amdgpu_vm_manager { struct amdgpu_ctx_state { uint64_t flags; - uint64_t hangs; + uint32_t hangs; }; struct amdgpu_ctx { @@ -1049,6 +1049,7 @@ struct amdgpu_ctx { struct amdgpu_fpriv *fpriv; struct amdgpu_ctx_state state; uint32_t id; + unsigned reset_counter; }; struct amdgpu_ctx_mgr { @@ -1897,8 +1898,6 @@ int amdgpu_ctx_alloc(struct amdgpu_device *adev,struct amdgpu_fpriv *fpriv, uint32_t *id,uint32_t flags); int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id); -int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, - uint32_t id,struct amdgpu_ctx_state *state); void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv); struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); @@ -2006,6 +2005,7 @@ struct amdgpu_device { atomic64_t vram_vis_usage; atomic64_t gtt_usage; atomic64_t num_bytes_moved; + atomic_t gpu_reset_counter; /* display */ struct amdgpu_mode_info mode_info; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index bcd332e085f6..6c66ac8a1891 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -81,21 +81,36 @@ int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint return -EINVAL; } -int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id, struct amdgpu_ctx_state *state) +static int amdgpu_ctx_query(struct amdgpu_device *adev, + struct amdgpu_fpriv *fpriv, uint32_t id, + union drm_amdgpu_ctx_out *out) { struct amdgpu_ctx *ctx; struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; + unsigned reset_counter; mutex_lock(&mgr->lock); ctx = idr_find(&mgr->ctx_handles, id); - if (ctx) { - /* state should alter with CS activity */ - *state = ctx->state; + if (!ctx) { mutex_unlock(&mgr->lock); - return 0; + return -EINVAL; } + + /* TODO: these two are always zero */ + out->state.flags = ctx->state.flags; + out->state.hangs = ctx->state.hangs; + + /* determine if a GPU reset has occured since the last call */ + reset_counter = atomic_read(&adev->gpu_reset_counter); + /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ + if (ctx->reset_counter == reset_counter) + out->state.reset_status = AMDGPU_CTX_NO_RESET; + else + out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; + ctx->reset_counter = reset_counter; + mutex_unlock(&mgr->lock); - return -EINVAL; + return 0; } void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv) @@ -115,12 +130,11 @@ void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv) } int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, - struct drm_file *filp) + struct drm_file *filp) { int r; uint32_t id; uint32_t flags; - struct amdgpu_ctx_state state; union drm_amdgpu_ctx *args = data; struct amdgpu_device *adev = dev->dev_private; @@ -139,11 +153,7 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, r = amdgpu_ctx_free(adev, fpriv, id); break; case AMDGPU_CTX_OP_QUERY_STATE: - r = amdgpu_ctx_query(adev, fpriv, id, &state); - if (r == 0) { - args->out.state.flags = state.flags; - args->out.state.hangs = state.hangs; - } + r = amdgpu_ctx_query(adev, fpriv, id, &args->out); break; default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 61cf5ad78857..3448d9fe88cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1781,6 +1781,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) } adev->needs_reset = false; + atomic_inc(&adev->gpu_reset_counter); /* block TTM */ resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 65da7cd16c0f..46580e950036 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -149,6 +149,12 @@ union drm_amdgpu_bo_list { #define AMDGPU_CTX_OP_STATE_RUNNING 1 +/* GPU reset status */ +#define AMDGPU_CTX_NO_RESET 0 +#define AMDGPU_CTX_GUILTY_RESET 1 /* this the context caused it */ +#define AMDGPU_CTX_INNOCENT_RESET 2 /* some other context caused it */ +#define AMDGPU_CTX_UNKNOWN_RESET 3 /* unknown cause */ + struct drm_amdgpu_ctx_in { uint32_t op; uint32_t flags; @@ -164,7 +170,10 @@ union drm_amdgpu_ctx_out { struct { uint64_t flags; - uint64_t hangs; + /** Number of resets caused by this context so far. */ + uint32_t hangs; + /** Reset status since the last call of the ioctl. */ + uint32_t reset_status; } state; }; -- cgit v1.2.3 From 9e14c65c5715b16bcbf5d5c64de2bb8a973a0afa Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 15 May 2015 11:52:18 -0400 Subject: drm/amdgpu: take the mode_config mutex when handling hpds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since we may modify display state. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 2187960baf7c..b4d36f0f2153 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -59,10 +59,12 @@ static void amdgpu_hotplug_work_func(struct work_struct *work) struct drm_mode_config *mode_config = &dev->mode_config; struct drm_connector *connector; + mutex_lock(&mode_config->mutex); if (mode_config->num_connector) { list_for_each_entry(connector, &mode_config->connector_list, head) amdgpu_connector_hotplug(connector); } + mutex_unlock(&mode_config->mutex); /* Just fire off a uevent and let userspace tell us what to do */ drm_helper_hpd_irq_event(dev); } -- cgit v1.2.3 From dc5f428d6155ceb3b9045851fd94fd8abff61502 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 18 May 2015 18:09:23 -0400 Subject: drm/amdgpu: make some DP parameters const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Ported from similar radeon patch. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index e00b8adde18d..7287aa8c27cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -203,9 +203,9 @@ void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector) #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 -static void amdgpu_atombios_dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], - int lane_count, - u8 train_set[4]) +static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane_count, + u8 train_set[4]) { u8 v = 0; u8 p = 0; @@ -265,8 +265,8 @@ static int amdgpu_atombios_dp_get_max_dp_pix_clock(int link_rate, * if the max lane# < low rate lane# then use max lane# instead. */ static int amdgpu_atombios_dp_get_dp_lane_number(struct drm_connector *connector, - u8 dpcd[DP_DPCD_SIZE], - int pix_clock) + const u8 dpcd[DP_DPCD_SIZE], + int pix_clock) { int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector)); int max_link_rate = drm_dp_max_link_rate(dpcd); @@ -284,8 +284,8 @@ static int amdgpu_atombios_dp_get_dp_lane_number(struct drm_connector *connector } static int amdgpu_atombios_dp_get_dp_link_clock(struct drm_connector *connector, - u8 dpcd[DP_DPCD_SIZE], - int pix_clock) + const u8 dpcd[DP_DPCD_SIZE], + int pix_clock) { int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector)); int lane_num, max_pix_clock; -- cgit v1.2.3 From 7af93b506956cd3efbea3c8e79a9420ac8819a7e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 18 May 2015 18:12:02 -0400 Subject: drm/amdgpu: simplify DPCD debug output MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use %*ph rather than walking the array. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 7287aa8c27cf..d54c4b81f0f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -358,16 +358,15 @@ int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector) { struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; u8 msg[DP_DPCD_SIZE]; - int ret, i; + int ret; ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, msg, DP_DPCD_SIZE); if (ret > 0) { memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); - DRM_DEBUG_KMS("DPCD: "); - for (i = 0; i < DP_DPCD_SIZE; i++) - DRM_DEBUG_KMS("%02x ", msg[i]); - DRM_DEBUG_KMS("\n"); + + DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), + dig_connector->dpcd); amdgpu_atombios_dp_probe_oui(amdgpu_connector); -- cgit v1.2.3 From 67ed0092328dbc5f88759be9a32a95b151583e1b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 18 May 2015 18:15:07 -0400 Subject: drm/amdgpu: retry dcpd fetch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Retry the dpcd fetch several times. Some eDP panels fail several times before the fetch is successful. bug: https://bugs.freedesktop.org/show_bug.cgi?id=73530 Ported from radeon. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index d54c4b81f0f3..9ba0a7d5bc8e 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -358,19 +358,21 @@ int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector) { struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; u8 msg[DP_DPCD_SIZE]; - int ret; + int ret, i; - ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, msg, - DP_DPCD_SIZE); - if (ret > 0) { - memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); + for (i = 0; i < 7; i++) { + ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, msg, + DP_DPCD_SIZE); + if (ret == DP_DPCD_SIZE) { + memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); - DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), - dig_connector->dpcd); + DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), + dig_connector->dpcd); - amdgpu_atombios_dp_probe_oui(amdgpu_connector); + amdgpu_atombios_dp_probe_oui(amdgpu_connector); - return 0; + return 0; + } } dig_connector->dpcd[0] = 0; return -EINVAL; -- cgit v1.2.3 From 25a595e48261e8d44970b6a5cfafc283f9a9fbc5 Mon Sep 17 00:00:00 2001 From: Christian König Date: Wed, 13 May 2015 14:21:06 +0200 Subject: drm/amdgpu: fix VM_CONTEXT*_PAGE_TABLE_END_ADDR handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: Jammy Zhou Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index b9b1df6bdaa4..ab096723a588 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -485,7 +485,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) WREG32(mmVM_L2_CNTL3, tmp); /* setup context0 */ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); - WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, (adev->mc.gtt_end >> 12) - 1); WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, (u32)(adev->dummy_page.addr >> 12)); @@ -506,7 +506,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) */ /* set vm size, must be a multiple of 4 */ WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); - WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn); + WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); for (i = 1; i < 16; i++) { if (i < 8) WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 7f6c52ff832f..f816165acd70 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -589,7 +589,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) WREG32(mmVM_L2_CNTL4, tmp); /* setup context0 */ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); - WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, (adev->mc.gtt_end >> 12) - 1); WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, (u32)(adev->dummy_page.addr >> 12)); @@ -610,7 +610,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) */ /* set vm size, must be a multiple of 4 */ WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); - WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn); + WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); for (i = 1; i < 16; i++) { if (i < 8) WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, -- cgit v1.2.3 From 271c81256612b162a9ae0f8c0f0a055a7523cea5 Mon Sep 17 00:00:00 2001 From: Christian König Date: Wed, 13 May 2015 14:30:53 +0200 Subject: drm/amdgpu: enforce AMDGPU_GEM_CREATE_NO_CPU_ACCESS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Deny user and kernel mapping if we said we never want to do so. Signed-off-by: Christian König Reviewed-by: Jammy Zhou Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 5fd0bc73b302..8dd843da799f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -316,7 +316,8 @@ int amdgpu_mode_dumb_mmap(struct drm_file *filp, return -ENOENT; } robj = gem_to_amdgpu_bo(gobj); - if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) { + if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm) || + (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { drm_gem_object_unreference_unlocked(gobj); return -EPERM; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 992b7f5843bc..a721f5044557 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -263,6 +263,9 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) bool is_iomem; int r; + if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) + return -EPERM; + if (bo->kptr) { if (ptr) { *ptr = bo->kptr; -- cgit v1.2.3 From 0be52de91c5e275dff61f0ed2314d84c9d68b385 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 18 May 2015 14:37:27 +0200 Subject: drm/amdgpu: validate amdgpu_vm_bo_map parameters MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: Jammy Zhou Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 1cc01fb409dc..b25e533fd6e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -936,6 +936,13 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, uint64_t eaddr; int r; + /* validate the parameters */ + if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || + size == 0 || size & AMDGPU_GPU_PAGE_MASK) { + amdgpu_bo_unreserve(bo_va->bo); + return -EINVAL; + } + /* make sure object fit at this offset */ eaddr = saddr + size; if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) { -- cgit v1.2.3 From 9f7eb5367d0001536c361bd1400e14521f854ff1 Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 18 May 2015 16:05:57 +0200 Subject: drm/amdgpu: actually use the VM map parameters MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: Jammy Zhou Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 8dd843da799f..c90b74da0027 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -583,8 +583,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, va_flags |= AMDGPU_PTE_WRITEABLE; if (args->in.flags & AMDGPU_VM_PAGE_EXECUTABLE) va_flags |= AMDGPU_PTE_EXECUTABLE; - r = amdgpu_vm_bo_map(adev, bo_va, args->in.va_address, 0, - amdgpu_bo_size(bo_va->bo), va_flags); + r = amdgpu_vm_bo_map(adev, bo_va, args->in.va_address, + args->in.offset_in_bo, args->in.map_size, + va_flags); break; case AMDGPU_VA_OP_UNMAP: r = amdgpu_vm_bo_unmap(adev, bo_va, args->in.va_address); -- cgit v1.2.3 From 63ab1c2beefe36d49a19f9f715fefdc293546e39 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Thu, 14 May 2015 23:03:57 +0200 Subject: drm/amdgpu: don't set unused tiling flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marek Olšák Reviewed-by: Alex Deucher Acked-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 2b1735d2efd6..ef611986b2b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -137,25 +137,13 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, if (fb_tiled) tiling_flags = AMDGPU_TILING_MACRO; -#ifdef __BIG_ENDIAN - switch (bpp) { - case 32: - tiling_flags |= AMDGPU_TILING_SWAP_32BIT; - break; - case 16: - tiling_flags |= AMDGPU_TILING_SWAP_16BIT; - default: - break; - } -#endif - ret = amdgpu_bo_reserve(rbo, false); if (unlikely(ret != 0)) goto out_unref; if (tiling_flags) { ret = amdgpu_bo_set_tiling_flags(rbo, - tiling_flags | AMDGPU_TILING_SURFACE); + tiling_flags); if (ret) dev_err(adev->dev, "FB failed to set tiling flags\n"); } -- cgit v1.2.3 From fbd76d59efe061c89d4ba14eef3a2cac1e3056c2 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Thu, 14 May 2015 23:48:26 +0200 Subject: drm/amdgpu: rework tiling flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marek Olšák Reviewed-by: Alex Deucher Acked-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 43 +------------- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 92 ++++------------------------- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 93 ++++-------------------------- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 91 ++++------------------------- include/uapi/drm/amdgpu_drm.h | 40 +++++++------ 6 files changed, 58 insertions(+), 304 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index ef611986b2b6..73b7aad5a872 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -32,6 +32,7 @@ #include #include #include "amdgpu.h" +#include "cikd.h" #include @@ -135,7 +136,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, rbo = gem_to_amdgpu_bo(gobj); if (fb_tiled) - tiling_flags = AMDGPU_TILING_MACRO; + tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); ret = amdgpu_bo_reserve(rbo, false); if (unlikely(ret != 0)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index a721f5044557..b545f614628c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -459,49 +459,8 @@ int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) { - unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; - - bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK; - bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK; - mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK; - tilesplit = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK; - stilesplit = (tiling_flags >> AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK; - switch (bankw) { - case 0: - case 1: - case 2: - case 4: - case 8: - break; - default: + if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) return -EINVAL; - } - switch (bankh) { - case 0: - case 1: - case 2: - case 4: - case 8: - break; - default: - return -EINVAL; - } - switch (mtaspect) { - case 0: - case 1: - case 2: - case 4: - case 8: - break; - default: - return -EINVAL; - } - if (tilesplit > 6) { - return -EINVAL; - } - if (stilesplit > 6) { - return -EINVAL; - } bo->tiling_flags = tiling_flags; return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index d412291ed70e..37b96236fe2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2008,61 +2008,6 @@ static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); } -static void dce_v10_0_tiling_fields(uint64_t tiling_flags, unsigned *bankw, - unsigned *bankh, unsigned *mtaspect, - unsigned *tile_split) -{ - *bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK; - *bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK; - *mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK; - *tile_split = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK; - switch (*bankw) { - default: - case 1: - *bankw = ADDR_SURF_BANK_WIDTH_1; - break; - case 2: - *bankw = ADDR_SURF_BANK_WIDTH_2; - break; - case 4: - *bankw = ADDR_SURF_BANK_WIDTH_4; - break; - case 8: - *bankw = ADDR_SURF_BANK_WIDTH_8; - break; - } - switch (*bankh) { - default: - case 1: - *bankh = ADDR_SURF_BANK_HEIGHT_1; - break; - case 2: - *bankh = ADDR_SURF_BANK_HEIGHT_2; - break; - case 4: - *bankh = ADDR_SURF_BANK_HEIGHT_4; - break; - case 8: - *bankh = ADDR_SURF_BANK_HEIGHT_8; - break; - } - switch (*mtaspect) { - default: - case 1: - *mtaspect = ADDR_SURF_MACRO_ASPECT_1; - break; - case 2: - *mtaspect = ADDR_SURF_MACRO_ASPECT_2; - break; - case 4: - *mtaspect = ADDR_SURF_MACRO_ASPECT_4; - break; - case 8: - *mtaspect = ADDR_SURF_MACRO_ASPECT_8; - break; - } -} - static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, int x, int y, int atomic) @@ -2076,10 +2021,8 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, struct amdgpu_bo *rbo; uint64_t fb_location, tiling_flags; uint32_t fb_format, fb_pitch_pixels; - unsigned bankw, bankh, mtaspect, tile_split; u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); - /* XXX change to VI */ - u32 pipe_config = (adev->gfx.config.tile_mode_array[10] >> 6) & 0x1f; + u32 pipe_config; u32 tmp, viewport_w, viewport_h; int r; bool bypass_lut = false; @@ -2121,6 +2064,8 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); amdgpu_bo_unreserve(rbo); + pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); + switch (target_fb->pixel_format) { case DRM_FORMAT_C8: fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); @@ -2198,27 +2143,15 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, return -EINVAL; } - if (tiling_flags & AMDGPU_TILING_MACRO) { - unsigned tileb, index, num_banks, tile_split_bytes; - - dce_v10_0_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); - /* Set NUM_BANKS. */ - /* Calculate the macrotile mode index. */ - tile_split_bytes = 64 << tile_split; - tileb = 8 * 8 * target_fb->bits_per_pixel / 8; - tileb = min(tile_split_bytes, tileb); + if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { + unsigned bankw, bankh, mtaspect, tile_split, num_banks; - for (index = 0; tileb > 64; index++) { - tileb >>= 1; - } - - if (index >= 16) { - DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", - target_fb->bits_per_pixel, tile_split); - return -EINVAL; - } + bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); + bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); + mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); + tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); + num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); - num_banks = (adev->gfx.config.macrotile_mode_array[index] >> 6) & 0x3; fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, ARRAY_2D_TILED_THIN1); @@ -2230,14 +2163,11 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, mtaspect); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, ADDR_SURF_MICRO_TILING_DISPLAY); - } else if (tiling_flags & AMDGPU_TILING_MICRO) { + } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, ARRAY_1D_TILED_THIN1); } - /* Read the pipe config from the 2D TILED SCANOUT mode. - * It should be the same for the other modes too, but not all - * modes set the pipe config field. */ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, pipe_config); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 55fef15a4fcf..04a5d4cd75b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2006,61 +2006,6 @@ static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); } -static void dce_v11_0_tiling_fields(uint64_t tiling_flags, unsigned *bankw, - unsigned *bankh, unsigned *mtaspect, - unsigned *tile_split) -{ - *bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK; - *bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK; - *mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK; - *tile_split = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK; - switch (*bankw) { - default: - case 1: - *bankw = ADDR_SURF_BANK_WIDTH_1; - break; - case 2: - *bankw = ADDR_SURF_BANK_WIDTH_2; - break; - case 4: - *bankw = ADDR_SURF_BANK_WIDTH_4; - break; - case 8: - *bankw = ADDR_SURF_BANK_WIDTH_8; - break; - } - switch (*bankh) { - default: - case 1: - *bankh = ADDR_SURF_BANK_HEIGHT_1; - break; - case 2: - *bankh = ADDR_SURF_BANK_HEIGHT_2; - break; - case 4: - *bankh = ADDR_SURF_BANK_HEIGHT_4; - break; - case 8: - *bankh = ADDR_SURF_BANK_HEIGHT_8; - break; - } - switch (*mtaspect) { - default: - case 1: - *mtaspect = ADDR_SURF_MACRO_ASPECT_1; - break; - case 2: - *mtaspect = ADDR_SURF_MACRO_ASPECT_2; - break; - case 4: - *mtaspect = ADDR_SURF_MACRO_ASPECT_4; - break; - case 8: - *mtaspect = ADDR_SURF_MACRO_ASPECT_8; - break; - } -} - static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, int x, int y, int atomic) @@ -2074,10 +2019,8 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, struct amdgpu_bo *rbo; uint64_t fb_location, tiling_flags; uint32_t fb_format, fb_pitch_pixels; - unsigned bankw, bankh, mtaspect, tile_split; u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); - /* XXX change to VI */ - u32 pipe_config = (adev->gfx.config.tile_mode_array[10] >> 6) & 0x1f; + u32 pipe_config; u32 tmp, viewport_w, viewport_h; int r; bool bypass_lut = false; @@ -2119,6 +2062,8 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); amdgpu_bo_unreserve(rbo); + pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); + switch (target_fb->pixel_format) { case DRM_FORMAT_C8: fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); @@ -2196,28 +2141,15 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, return -EINVAL; } - if (tiling_flags & AMDGPU_TILING_MACRO) { - unsigned tileb, index, num_banks, tile_split_bytes; - - dce_v11_0_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); - /* Set NUM_BANKS. */ - /* Calculate the macrotile mode index. */ - tile_split_bytes = 64 << tile_split; - tileb = 8 * 8 * target_fb->bits_per_pixel / 8; - tileb = min(tile_split_bytes, tileb); + if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { + unsigned bankw, bankh, mtaspect, tile_split, num_banks; - for (index = 0; tileb > 64; index++) { - tileb >>= 1; - } - - if (index >= 16) { - DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", - target_fb->bits_per_pixel, tile_split); - return -EINVAL; - } + bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); + bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); + mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); + tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); + num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); - /* XXX fix me for VI */ - num_banks = (adev->gfx.config.macrotile_mode_array[index] >> 6) & 0x3; fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, ARRAY_2D_TILED_THIN1); @@ -2229,14 +2161,11 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, mtaspect); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, ADDR_SURF_MICRO_TILING_DISPLAY); - } else if (tiling_flags & AMDGPU_TILING_MICRO) { + } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, ARRAY_1D_TILED_THIN1); } - /* Read the pipe config from the 2D TILED SCANOUT mode. - * It should be the same for the other modes too, but not all - * modes set the pipe config field. */ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, pipe_config); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index c1bc6935c88e..9f2ff8d374f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1976,61 +1976,6 @@ static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable) WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); } -static void dce_v8_0_tiling_fields(uint64_t tiling_flags, unsigned *bankw, - unsigned *bankh, unsigned *mtaspect, - unsigned *tile_split) -{ - *bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK; - *bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK; - *mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK; - *tile_split = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK; - switch (*bankw) { - default: - case 1: - *bankw = ADDR_SURF_BANK_WIDTH_1; - break; - case 2: - *bankw = ADDR_SURF_BANK_WIDTH_2; - break; - case 4: - *bankw = ADDR_SURF_BANK_WIDTH_4; - break; - case 8: - *bankw = ADDR_SURF_BANK_WIDTH_8; - break; - } - switch (*bankh) { - default: - case 1: - *bankh = ADDR_SURF_BANK_HEIGHT_1; - break; - case 2: - *bankh = ADDR_SURF_BANK_HEIGHT_2; - break; - case 4: - *bankh = ADDR_SURF_BANK_HEIGHT_4; - break; - case 8: - *bankh = ADDR_SURF_BANK_HEIGHT_8; - break; - } - switch (*mtaspect) { - default: - case 1: - *mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_1; - break; - case 2: - *mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_2; - break; - case 4: - *mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_4; - break; - case 8: - *mtaspect = ADDR_SURF_MACRO_TILE_ASPECT_8; - break; - } -} - static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, int x, int y, int atomic) @@ -2044,9 +1989,8 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, struct amdgpu_bo *rbo; uint64_t fb_location, tiling_flags; uint32_t fb_format, fb_pitch_pixels; - unsigned bankw, bankh, mtaspect, tile_split; u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); - u32 pipe_config = (adev->gfx.config.tile_mode_array[10] >> 6) & 0x1f; + u32 pipe_config; u32 tmp, viewport_w, viewport_h; int r; bool bypass_lut = false; @@ -2088,6 +2032,8 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); amdgpu_bo_unreserve(rbo); + pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); + switch (target_fb->pixel_format) { case DRM_FORMAT_C8: fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | @@ -2158,27 +2104,15 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, return -EINVAL; } - if (tiling_flags & AMDGPU_TILING_MACRO) { - unsigned tileb, index, num_banks, tile_split_bytes; - - dce_v8_0_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); - /* Set NUM_BANKS. */ - /* Calculate the macrotile mode index. */ - tile_split_bytes = 64 << tile_split; - tileb = 8 * 8 * target_fb->bits_per_pixel / 8; - tileb = min(tile_split_bytes, tileb); + if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { + unsigned bankw, bankh, mtaspect, tile_split, num_banks; - for (index = 0; tileb > 64; index++) { - tileb >>= 1; - } - - if (index >= 16) { - DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", - target_fb->bits_per_pixel, tile_split); - return -EINVAL; - } + bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); + bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); + mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); + tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); + num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); - num_banks = (adev->gfx.config.macrotile_mode_array[index] >> 6) & 0x3; fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT); fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); @@ -2186,13 +2120,10 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT); fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT); - } else if (tiling_flags & AMDGPU_TILING_MICRO) { + } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); } - /* Read the pipe config from the 2D TILED SCANOUT mode. - * It should be the same for the other modes too, but not all - * modes set the pipe config field. */ fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); dce_v8_0_vga_enable(crtc, false); diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 46580e950036..d9b9b6f8de2b 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -199,24 +199,28 @@ struct drm_amdgpu_gem_userptr { uint32_t handle; }; -#define AMDGPU_TILING_MACRO 0x1 -#define AMDGPU_TILING_MICRO 0x2 -#define AMDGPU_TILING_SWAP_16BIT 0x4 -#define AMDGPU_TILING_R600_NO_SCANOUT AMDGPU_TILING_SWAP_16BIT -#define AMDGPU_TILING_SWAP_32BIT 0x8 -/* this object requires a surface when mapped - i.e. front buffer */ -#define AMDGPU_TILING_SURFACE 0x10 -#define AMDGPU_TILING_MICRO_SQUARE 0x20 -#define AMDGPU_TILING_EG_BANKW_SHIFT 8 -#define AMDGPU_TILING_EG_BANKW_MASK 0xf -#define AMDGPU_TILING_EG_BANKH_SHIFT 12 -#define AMDGPU_TILING_EG_BANKH_MASK 0xf -#define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 -#define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf -#define AMDGPU_TILING_EG_TILE_SPLIT_SHIFT 24 -#define AMDGPU_TILING_EG_TILE_SPLIT_MASK 0xf -#define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 -#define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf +/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ +#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 +#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf +#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 +#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f +#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 +#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 +#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 +#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 +#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 +#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 +#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 +#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 +#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 +#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 +#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 +#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 + +#define AMDGPU_TILING_SET(field, value) \ + (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) +#define AMDGPU_TILING_GET(value, field) \ + (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 -- cgit v1.2.3 From 15a16ff6065b8d51e27ebe24c0393195ab817f27 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 21 May 2015 02:24:48 -0400 Subject: drm/amdgpu: remove unused TRACE_SYSTEM_STRING define MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Port of 77cb2fea1e5fc4b083dd967f231bbf6edd96150e to amdgpu. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index b57647e582d4..b56dd64bd4ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -9,7 +9,6 @@ #undef TRACE_SYSTEM #define TRACE_SYSTEM amdgpu -#define TRACE_SYSTEM_STRING __stringify(TRACE_SYSTEM) #define TRACE_INCLUDE_FILE amdgpu_trace TRACE_EVENT(amdgpu_bo_create, -- cgit v1.2.3 From e982262214674ce4d4a24ec6088134f4c641930a Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Wed, 6 May 2015 14:31:27 -0400 Subject: drm/amdgpu: recalculate VCE firmware BO size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Firmware required BO size changes in terms of ASIC family Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 5 +---- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 2 +- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 13 +++++++++---- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 13 +++++++++---- 5 files changed, 20 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ebff89eb2f4c..52d684563b18 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1664,8 +1664,6 @@ struct amdgpu_uvd { * VCE */ #define AMDGPU_MAX_VCE_HANDLES 16 -#define AMDGPU_VCE_STACK_SIZE (1024*1024) -#define AMDGPU_VCE_HEAP_SIZE (4*1024*1024) #define AMDGPU_VCE_FIRMWARE_OFFSET 256 struct amdgpu_vce { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 803ee601c399..62018b37273e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -68,9 +68,8 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work); * * First step to get VCE online, allocate memory and load the firmware */ -int amdgpu_vce_sw_init(struct amdgpu_device *adev) +int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) { - unsigned long size; const char *fw_name; const struct common_firmware_header *hdr; unsigned ucode_version, version_major, version_minor, binary_id; @@ -136,8 +135,6 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev) /* allocate firmware, stack and heap BO */ - size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes)) + - AMDGPU_VCE_STACK_SIZE + AMDGPU_VCE_HEAP_SIZE; r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->vce.vcpu_bo); if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index b9411e43db25..4294854912e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -24,7 +24,7 @@ #ifndef __AMDGPU_VCE_H__ #define __AMDGPU_VCE_H__ -int amdgpu_vce_sw_init(struct amdgpu_device *adev); +int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size); int amdgpu_vce_sw_fini(struct amdgpu_device *adev); int amdgpu_vce_suspend(struct amdgpu_device *adev); int amdgpu_vce_resume(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index b47c16da6bf8..f200df3cf97a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -37,6 +37,10 @@ #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" +#define VCE_V2_0_FW_SIZE (256 * 1024) +#define VCE_V2_0_STACK_SIZE (64 * 1024) +#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES) + static void vce_v2_0_mc_resume(struct amdgpu_device *adev); static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev); @@ -183,7 +187,8 @@ static int vce_v2_0_sw_init(struct amdgpu_device *adev) if (r) return r; - r = amdgpu_vce_sw_init(adev); + r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE + + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE); if (r) return r; @@ -415,17 +420,17 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev) WREG32(mmVCE_LMI_VM_CTRL, 0); addr += AMDGPU_VCE_FIRMWARE_OFFSET; - size = AMDGPU_GPU_PAGE_ALIGN(adev->vce.fw->size); + size = VCE_V2_0_FW_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE0, size); addr += size; - size = AMDGPU_VCE_STACK_SIZE; + size = VCE_V2_0_STACK_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE1, size); addr += size; - size = AMDGPU_VCE_HEAP_SIZE; + size = VCE_V2_0_DATA_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE2, size); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 384c45e74053..ee29436f364e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -35,6 +35,10 @@ #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" +#define VCE_V3_0_FW_SIZE (384 * 1024) +#define VCE_V3_0_STACK_SIZE (64 * 1024) +#define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024)) + static void vce_v3_0_mc_resume(struct amdgpu_device *adev); static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); @@ -181,7 +185,8 @@ static int vce_v3_0_sw_init(struct amdgpu_device *adev) if (r) return r; - r = amdgpu_vce_sw_init(adev); + r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE + + (VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2); if (r) return r; @@ -304,17 +309,17 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev) WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); offset = AMDGPU_VCE_FIRMWARE_OFFSET; - size = AMDGPU_GPU_PAGE_ALIGN(adev->vce.fw->size); + size = VCE_V3_0_FW_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE0, size); offset += size; - size = AMDGPU_VCE_STACK_SIZE; + size = VCE_V3_0_STACK_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE1, size); offset += size; - size = AMDGPU_VCE_HEAP_SIZE; + size = VCE_V3_0_DATA_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE2, size); -- cgit v1.2.3 From 5bbc553a1acce5d1792ba778273ffbea5af1695d Mon Sep 17 00:00:00 2001 From: Leo Liu Date: Wed, 6 May 2015 15:20:41 -0400 Subject: drm/amdgpu: implement VCE two instances support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit VCE 3.0 has two indentical instances in the engine, they share the same registers name in differrent memory block distinguished by the grbm_gfx_index, we set to master instance after init, it will dispatch task to slave instance. These two instances will share the same firmware, but have their own stacks and heaps. v2: add mutex for using grbm_gfx_index Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 141 +++++++++++++++++++++------------- 1 file changed, 87 insertions(+), 54 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index ee29436f364e..57e0e167c83b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -34,12 +34,16 @@ #include "vce/vce_3_0_sh_mask.h" #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" +#include "gca/gfx_8_0_d.h" + +#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04 +#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10 #define VCE_V3_0_FW_SIZE (384 * 1024) #define VCE_V3_0_STACK_SIZE (64 * 1024) #define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024)) -static void vce_v3_0_mc_resume(struct amdgpu_device *adev); +static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx); static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); @@ -104,12 +108,70 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring) static int vce_v3_0_start(struct amdgpu_device *adev) { struct amdgpu_ring *ring; - int i, j, r; + int idx, i, j, r; + + mutex_lock(&adev->grbm_idx_mutex); + for (idx = 0; idx < 2; ++idx) { + if(idx == 0) + WREG32_P(mmGRBM_GFX_INDEX, 0, + ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); + else + WREG32_P(mmGRBM_GFX_INDEX, + GRBM_GFX_INDEX__VCE_INSTANCE_MASK, + ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); + + vce_v3_0_mc_resume(adev, idx); + + /* set BUSY flag */ + WREG32_P(mmVCE_STATUS, 1, ~1); + + WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, + ~VCE_VCPU_CNTL__CLK_EN_MASK); + + WREG32_P(mmVCE_SOFT_RESET, + VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + + mdelay(100); + + WREG32_P(mmVCE_SOFT_RESET, 0, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + + for (i = 0; i < 10; ++i) { + uint32_t status; + for (j = 0; j < 100; ++j) { + status = RREG32(mmVCE_STATUS); + if (status & 2) + break; + mdelay(10); + } + r = 0; + if (status & 2) + break; + + DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n"); + WREG32_P(mmVCE_SOFT_RESET, + VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(10); + WREG32_P(mmVCE_SOFT_RESET, 0, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(10); + r = -1; + } + + /* clear BUSY flag */ + WREG32_P(mmVCE_STATUS, 0, ~1); - vce_v3_0_mc_resume(adev); + if (r) { + DRM_ERROR("VCE not responding, giving up!!!\n"); + mutex_unlock(&adev->grbm_idx_mutex); + return r; + } + } - /* set BUSY flag */ - WREG32_P(mmVCE_STATUS, 1, ~1); + WREG32_P(mmGRBM_GFX_INDEX, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK); + mutex_unlock(&adev->grbm_idx_mutex); ring = &adev->vce.ring[0]; WREG32(mmVCE_RB_RPTR, ring->wptr); @@ -125,45 +187,6 @@ static int vce_v3_0_start(struct amdgpu_device *adev) WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); - WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK); - - WREG32_P(mmVCE_SOFT_RESET, - VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, - ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); - - mdelay(100); - - WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); - - for (i = 0; i < 10; ++i) { - uint32_t status; - for (j = 0; j < 100; ++j) { - status = RREG32(mmVCE_STATUS); - if (status & 2) - break; - mdelay(10); - } - r = 0; - if (status & 2) - break; - - DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n"); - WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, - ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); - mdelay(10); - WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); - mdelay(10); - r = -1; - } - - /* clear BUSY flag */ - WREG32_P(mmVCE_STATUS, 0, ~1); - - if (r) { - DRM_ERROR("VCE not responding, giving up!!!\n"); - return r; - } - return 0; } @@ -292,7 +315,7 @@ static int vce_v3_0_resume(struct amdgpu_device *adev) return r; } -static void vce_v3_0_mc_resume(struct amdgpu_device *adev) +static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) { uint32_t offset, size; @@ -313,15 +336,25 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev) WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE0, size); - offset += size; - size = VCE_V3_0_STACK_SIZE; - WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); - WREG32(mmVCE_VCPU_CACHE_SIZE1, size); - - offset += size; - size = VCE_V3_0_DATA_SIZE; - WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); - WREG32(mmVCE_VCPU_CACHE_SIZE2, size); + if (idx == 0) { + offset += size; + size = VCE_V3_0_STACK_SIZE; + WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE1, size); + offset += size; + size = VCE_V3_0_DATA_SIZE; + WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE2, size); + } else { + offset += size + VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE; + size = VCE_V3_0_STACK_SIZE; + WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE1, size); + offset += size; + size = VCE_V3_0_DATA_SIZE; + WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE2, size); + } WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); -- cgit v1.2.3 From 564ea7900cffbe2eddb3bcfb09b700ad7942aef4 Mon Sep 17 00:00:00 2001 From: Sonny Jiang Date: Tue, 12 May 2015 16:13:35 -0400 Subject: drm/amdgpu: enable uvd dpm and powergating MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable UVD dpm (dynamic power management) and powergating. UVD dpm dynamically scales the UVD clocks on demand. Powergating turns off the power to the block when it's not in use. Signed-off-by: Sonny Jiang Acked-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 90 ++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/cz_dpm.h | 2 + drivers/gpu/drm/amd/amdgpu/vi.c | 2 +- 3 files changed, 91 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index adf4dbc3f6a0..2649b505d2d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -42,6 +42,8 @@ #include "bif/bif_5_1_d.h" #include "gfx_v8_0.h" +static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate); + static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps) { struct cz_ps *ps = rps->ps_priv; @@ -474,6 +476,7 @@ static int cz_dpm_init(struct amdgpu_device *adev) return ret; pi->dpm_enabled = true; + pi->uvd_dynamic_pg = false; return 0; } @@ -546,6 +549,15 @@ static int cz_dpm_early_init(struct amdgpu_device *adev) return 0; } + +static int cz_dpm_late_init(struct amdgpu_device *adev) +{ + /* powerdown unused blocks for now */ + cz_dpm_powergate_uvd(adev, true); + + return 0; +} + static int cz_dpm_sw_init(struct amdgpu_device *adev) { int ret = 0; @@ -1260,6 +1272,9 @@ static int cz_dpm_disable(struct amdgpu_device *adev) return -EINVAL; } + /* powerup blocks */ + cz_dpm_powergate_uvd(adev, false); + cz_clear_voting_clients(adev); cz_stop_dpm(adev); cz_update_current_ps(adev, adev->pm.dpm.boot_ps); @@ -1677,9 +1692,80 @@ static uint32_t cz_dpm_get_mclk(struct amdgpu_device *adev, bool low) return pi->sys_info.bootup_uma_clk; } +static int cz_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) +{ + struct cz_power_info *pi = cz_get_pi(adev); + int ret = 0; + + if (enable && pi->caps_uvd_dpm ) { + pi->dpm_flags |= DPMFlags_UVD_Enabled; + DRM_DEBUG("UVD DPM Enabled.\n"); + + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_EnableAllSmuFeatures, UVD_DPM_MASK); + } else { + pi->dpm_flags &= ~DPMFlags_UVD_Enabled; + DRM_DEBUG("UVD DPM Stopped\n"); + + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_DisableAllSmuFeatures, UVD_DPM_MASK); + } + + return ret; +} + +static int cz_update_uvd_dpm(struct amdgpu_device *adev, bool gate) +{ + return cz_enable_uvd_dpm(adev, !gate); +} + + +static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) +{ + struct cz_power_info *pi = cz_get_pi(adev); + int ret; + + if (pi->uvd_power_gated == gate) + return; + + pi->uvd_power_gated = gate; + + if (gate) { + if (pi->caps_uvd_pg) { + /* disable clockgating so we can properly shut down the block */ + ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, + AMDGPU_CG_STATE_UNGATE); + /* shutdown the UVD block */ + ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, + AMDGPU_PG_STATE_GATE); + /* XXX: check for errors */ + } + cz_update_uvd_dpm(adev, gate); + if (pi->caps_uvd_pg) + /* power off the UVD block */ + cz_send_msg_to_smc(adev, PPSMC_MSG_UVDPowerOFF); + } else { + if (pi->caps_uvd_pg) { + /* power on the UVD block */ + if (pi->uvd_dynamic_pg) + cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 1); + else + cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0); + /* re-init the UVD block */ + ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, + AMDGPU_PG_STATE_UNGATE); + /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */ + ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, + AMDGPU_CG_STATE_GATE); + /* XXX: check for errors */ + } + cz_update_uvd_dpm(adev, gate); + } +} + const struct amdgpu_ip_funcs cz_dpm_ip_funcs = { .early_init = cz_dpm_early_init, - .late_init = NULL, + .late_init = cz_dpm_late_init, .sw_init = cz_dpm_sw_init, .sw_fini = cz_dpm_sw_fini, .hw_init = cz_dpm_hw_init, @@ -1707,7 +1793,7 @@ static const struct amdgpu_dpm_funcs cz_dpm_funcs = { cz_dpm_debugfs_print_current_performance_level, .force_performance_level = cz_dpm_force_dpm_level, .vblank_too_short = NULL, - .powergate_uvd = NULL, + .powergate_uvd = cz_dpm_powergate_uvd, }; static void cz_dpm_set_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h index ed6449de5dc5..782a74107664 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h @@ -221,6 +221,8 @@ struct cz_power_info { bool uvd_power_down; bool vce_power_down; bool acp_power_down; + + bool uvd_dynamic_pg; }; /* cz_smc.c */ diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 20a159803983..59a073aa42a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1266,7 +1266,7 @@ static int vi_common_early_init(struct amdgpu_device *adev) case CHIP_CARRIZO: adev->has_uvd = true; adev->cg_flags = 0; - adev->pg_flags = 0; + adev->pg_flags = AMDGPU_PG_SUPPORT_UVD; adev->external_rev_id = adev->rev_id + 0x1; if (amdgpu_smc_load_fw && smc_enabled) adev->firmware.smu_load = true; -- cgit v1.2.3 From 5fb1941d0ce70d8ce56b12edcb1a1f2ba07629dd Mon Sep 17 00:00:00 2001 From: Christian König Date: Thu, 21 May 2015 17:03:46 +0200 Subject: drm/amdgpu: port fault_reserve_notify changes from radeon MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 55 +++++++++++++++++++----------- 1 file changed, 35 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index b545f614628c..dcc6af97f59d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -549,30 +549,45 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) { struct amdgpu_device *adev; - struct amdgpu_bo *rbo; - unsigned long offset, size; - int r; + struct amdgpu_bo *abo; + unsigned long offset, size, lpfn; + int i, r; if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) return 0; - rbo = container_of(bo, struct amdgpu_bo, tbo); - adev = rbo->adev; - if (bo->mem.mem_type == TTM_PL_VRAM) { - size = bo->mem.num_pages << PAGE_SHIFT; - offset = bo->mem.start << PAGE_SHIFT; - if ((offset + size) > adev->mc.visible_vram_size) { - /* hurrah the memory is not visible ! */ - amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_VRAM); - rbo->placements[0].lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; - r = ttm_bo_validate(bo, &rbo->placement, false, false); - if (unlikely(r != 0)) - return r; - offset = bo->mem.start << PAGE_SHIFT; - /* this should not happen */ - if ((offset + size) > adev->mc.visible_vram_size) - return -EINVAL; - } + + abo = container_of(bo, struct amdgpu_bo, tbo); + adev = abo->adev; + if (bo->mem.mem_type != TTM_PL_VRAM) + return 0; + + size = bo->mem.num_pages << PAGE_SHIFT; + offset = bo->mem.start << PAGE_SHIFT; + if ((offset + size) <= adev->mc.visible_vram_size) + return 0; + + /* hurrah the memory is not visible ! */ + amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM); + lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; + for (i = 0; i < abo->placement.num_placement; i++) { + /* Force into visible VRAM */ + if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) && + (!abo->placements[i].lpfn || abo->placements[i].lpfn > lpfn)) + abo->placements[i].lpfn = lpfn; + } + r = ttm_bo_validate(bo, &abo->placement, false, false); + if (unlikely(r == -ENOMEM)) { + amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); + return ttm_bo_validate(bo, &abo->placement, false, false); + } else if (unlikely(r != 0)) { + return r; } + + offset = bo->mem.start << PAGE_SHIFT; + /* this should never happen */ + if ((offset + size) > adev->mc.visible_vram_size) + return -EINVAL; + return 0; } -- cgit v1.2.3 From 9269a606866012c472e6dc614fd7b7c0eaa647a2 Mon Sep 17 00:00:00 2001 From: Christian König Date: Fri, 22 May 2015 10:55:47 +0200 Subject: drm/amdgpu: drop AMDGPU_FENCE_SIGNALED_SEQ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's causing issues with VMID handling and comparing the fence value two times actually doesn't make handling faster. Port of radeon commit "d6d5c5b8364bcc4d52cddc68bcb0a330d2af20f3". Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 12 ------------ 2 files changed, 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 52d684563b18..411cfb91170f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -84,9 +84,6 @@ extern int amdgpu_vm_block_size; #define AMDGPUFB_CONN_LIMIT 4 #define AMDGPU_BIOS_NUM_SCRATCH 8 -/* fence seq are set to this number when signaled */ -#define AMDGPU_FENCE_SIGNALED_SEQ 0LL - /* max number of rings */ #define AMDGPU_MAX_RINGS 16 #define AMDGPU_MAX_GFX_RINGS 1 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index be4d53508680..9ce6023a4261 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -463,11 +463,7 @@ bool amdgpu_fence_signaled(struct amdgpu_fence *fence) if (!fence) return true; - if (fence->seq == AMDGPU_FENCE_SIGNALED_SEQ) - return true; - if (amdgpu_fence_seq_signaled(fence->ring, fence->seq)) { - fence->seq = AMDGPU_FENCE_SIGNALED_SEQ; if (!fence_signal(&fence->base)) FENCE_TRACE(&fence->base, "signaled from amdgpu_fence_signaled\n"); return true; @@ -637,15 +633,11 @@ int amdgpu_fence_wait(struct amdgpu_fence *fence, bool intr) long r; seq[fence->ring->idx] = fence->seq; - if (seq[fence->ring->idx] == AMDGPU_FENCE_SIGNALED_SEQ) - return 0; - r = amdgpu_fence_wait_seq_timeout(fence->ring->adev, seq, intr, MAX_SCHEDULE_TIMEOUT); if (r < 0) { return r; } - fence->seq = AMDGPU_FENCE_SIGNALED_SEQ; r = fence_signal(&fence->base); if (!r) FENCE_TRACE(&fence->base, "signaled from fence_wait\n"); @@ -682,10 +674,6 @@ int amdgpu_fence_wait_any(struct amdgpu_device *adev, seq[i] = fences[i]->seq; ++num_rings; - - /* test if something was allready signaled */ - if (seq[i] == AMDGPU_FENCE_SIGNALED_SEQ) - return 0; } /* nothing to wait for ? */ -- cgit v1.2.3 From 5fc3aeeb9e553a20ce62544f7176c6c4aca52d71 Mon Sep 17 00:00:00 2001 From: yanyang1 Date: Fri, 22 May 2015 14:39:35 -0400 Subject: drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2) The structure is renamed and moved to amd_shared.h to make the component independent. This makes it easier to add new components in the future. v2: fix include path Reviewed-by: Jammy Zhou Signed-off-by: yanyang1 Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 75 ++--------------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 +++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 24 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 57 ++++++++----- drivers/gpu/drm/amd/amdgpu/cik.c | 130 +++++++++++++++-------------- drivers/gpu/drm/amd/amdgpu/cik.h | 2 +- drivers/gpu/drm/amd/amdgpu/cik_dpm.h | 4 +- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 54 ++++++++---- drivers/gpu/drm/amd/amdgpu/cik_ih.h | 2 +- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 53 +++++++----- drivers/gpu/drm/amd/amdgpu/cik_sdma.h | 2 +- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 53 +++++++----- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 53 ++++++++---- drivers/gpu/drm/amd/amdgpu/cz_ih.h | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 50 ++++++----- drivers/gpu/drm/amd/amdgpu/dce_v10_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 50 ++++++----- drivers/gpu/drm/amd/amdgpu/dce_v11_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 50 ++++++----- drivers/gpu/drm/amd/amdgpu/dce_v8_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 57 ++++++++----- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 51 +++++++---- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 52 +++++++----- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 51 ++++++----- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/iceland_dpm.c | 34 +++++--- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 55 +++++++----- drivers/gpu/drm/amd/amdgpu/iceland_ih.h | 2 +- drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 89 +++++++++++--------- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 51 ++++++----- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 52 +++++++----- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/tonga_dpm.c | 35 +++++--- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 51 +++++++---- drivers/gpu/drm/amd/amdgpu/tonga_ih.h | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 53 ++++++++---- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 52 +++++++----- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 52 +++++++----- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 54 +++++++----- drivers/gpu/drm/amd/amdgpu/vce_v2_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 52 +++++++----- drivers/gpu/drm/amd/amdgpu/vce_v3_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/vi.c | 96 +++++++++++---------- drivers/gpu/drm/amd/amdgpu/vi.h | 2 +- drivers/gpu/drm/amd/amdgpu/vi_dpm.h | 6 +- drivers/gpu/drm/amd/include/amd_shared.h | 81 ++++++++++++++++++ 55 files changed, 1067 insertions(+), 707 deletions(-) create mode 100644 drivers/gpu/drm/amd/include/amd_shared.h (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 9a573e87cdd3..616dfd4a1398 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -2,7 +2,8 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg +ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/amd/include/asic_reg \ + -Idrivers/gpu/drm/amd/include amdgpu-y := amdgpu_drv.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 411cfb91170f..80f0bea52e33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -44,6 +44,7 @@ #include +#include "amd_shared.h" #include "amdgpu_family.h" #include "amdgpu_mode.h" #include "amdgpu_ih.h" @@ -205,86 +206,28 @@ enum amdgpu_thermal_irq { AMDGPU_THERMAL_IRQ_LAST }; -/* - * IP block functions - */ -enum amdgpu_ip_block_type { - AMDGPU_IP_BLOCK_TYPE_COMMON, - AMDGPU_IP_BLOCK_TYPE_GMC, - AMDGPU_IP_BLOCK_TYPE_IH, - AMDGPU_IP_BLOCK_TYPE_SMC, - AMDGPU_IP_BLOCK_TYPE_DCE, - AMDGPU_IP_BLOCK_TYPE_GFX, - AMDGPU_IP_BLOCK_TYPE_SDMA, - AMDGPU_IP_BLOCK_TYPE_UVD, - AMDGPU_IP_BLOCK_TYPE_VCE, -}; - -enum amdgpu_clockgating_state { - AMDGPU_CG_STATE_GATE = 0, - AMDGPU_CG_STATE_UNGATE, -}; - -enum amdgpu_powergating_state { - AMDGPU_PG_STATE_GATE = 0, - AMDGPU_PG_STATE_UNGATE, -}; - -struct amdgpu_ip_funcs { - /* sets up early driver state (pre sw_init), does not configure hw - Optional */ - int (*early_init)(struct amdgpu_device *adev); - /* sets up late driver/hw state (post hw_init) - Optional */ - int (*late_init)(struct amdgpu_device *adev); - /* sets up driver state, does not configure hw */ - int (*sw_init)(struct amdgpu_device *adev); - /* tears down driver state, does not configure hw */ - int (*sw_fini)(struct amdgpu_device *adev); - /* sets up the hw state */ - int (*hw_init)(struct amdgpu_device *adev); - /* tears down the hw state */ - int (*hw_fini)(struct amdgpu_device *adev); - /* handles IP specific hw/sw changes for suspend */ - int (*suspend)(struct amdgpu_device *adev); - /* handles IP specific hw/sw changes for resume */ - int (*resume)(struct amdgpu_device *adev); - /* returns current IP block idle status */ - bool (*is_idle)(struct amdgpu_device *adev); - /* poll for idle */ - int (*wait_for_idle)(struct amdgpu_device *adev); - /* soft reset the IP block */ - int (*soft_reset)(struct amdgpu_device *adev); - /* dump the IP block status registers */ - void (*print_status)(struct amdgpu_device *adev); - /* enable/disable cg for the IP block */ - int (*set_clockgating_state)(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state); - /* enable/disable pg for the IP block */ - int (*set_powergating_state)(struct amdgpu_device *adev, - enum amdgpu_powergating_state state); -}; - int amdgpu_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_ip_block_type block_type, - enum amdgpu_clockgating_state state); + enum amd_ip_block_type block_type, + enum amd_clockgating_state state); int amdgpu_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_ip_block_type block_type, - enum amdgpu_powergating_state state); + enum amd_ip_block_type block_type, + enum amd_powergating_state state); struct amdgpu_ip_block_version { - enum amdgpu_ip_block_type type; + enum amd_ip_block_type type; u32 major; u32 minor; u32 rev; - const struct amdgpu_ip_funcs *funcs; + const struct amd_ip_funcs *funcs; }; int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, - enum amdgpu_ip_block_type type, + enum amd_ip_block_type type, u32 major, u32 minor); const struct amdgpu_ip_block_version * amdgpu_get_ip_block( struct amdgpu_device *adev, - enum amdgpu_ip_block_type type); + enum amd_ip_block_type type); /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ struct amdgpu_buffer_funcs { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 3448d9fe88cd..d9d26f2e7bd7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1081,14 +1081,14 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { }; int amdgpu_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_ip_block_type block_type, - enum amdgpu_clockgating_state state) + enum amd_ip_block_type block_type, + enum amd_clockgating_state state) { int i, r = 0; for (i = 0; i < adev->num_ip_blocks; i++) { if (adev->ip_blocks[i].type == block_type) { - r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, + r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, state); if (r) return r; @@ -1098,14 +1098,14 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev, } int amdgpu_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_ip_block_type block_type, - enum amdgpu_powergating_state state) + enum amd_ip_block_type block_type, + enum amd_powergating_state state) { int i, r = 0; for (i = 0; i < adev->num_ip_blocks; i++) { if (adev->ip_blocks[i].type == block_type) { - r = adev->ip_blocks[i].funcs->set_powergating_state(adev, + r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev, state); if (r) return r; @@ -1116,7 +1116,7 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev, const struct amdgpu_ip_block_version * amdgpu_get_ip_block( struct amdgpu_device *adev, - enum amdgpu_ip_block_type type) + enum amd_ip_block_type type) { int i; @@ -1131,7 +1131,7 @@ const struct amdgpu_ip_block_version * amdgpu_get_ip_block( * amdgpu_ip_block_version_cmp * * @adev: amdgpu_device pointer - * @type: enum amdgpu_ip_block_type + * @type: enum amd_ip_block_type * @major: major version * @minor: minor version * @@ -1139,7 +1139,7 @@ const struct amdgpu_ip_block_version * amdgpu_get_ip_block( * return 1 if smaller or the ip_block doesn't exist */ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, - enum amdgpu_ip_block_type type, + enum amd_ip_block_type type, u32 major, u32 minor) { const struct amdgpu_ip_block_version *ip_block; @@ -1204,7 +1204,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev) adev->ip_block_enabled[i] = false; } else { if (adev->ip_blocks[i].funcs->early_init) { - r = adev->ip_blocks[i].funcs->early_init(adev); + r = adev->ip_blocks[i].funcs->early_init((void *)adev); if (r) return r; } @@ -1222,15 +1222,15 @@ static int amdgpu_init(struct amdgpu_device *adev) for (i = 0; i < adev->num_ip_blocks; i++) { if (!adev->ip_block_enabled[i]) continue; - r = adev->ip_blocks[i].funcs->sw_init(adev); + r = adev->ip_blocks[i].funcs->sw_init((void *)adev); if (r) return r; /* need to do gmc hw init early so we can allocate gpu mem */ - if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) { + if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { r = amdgpu_vram_scratch_init(adev); if (r) return r; - r = adev->ip_blocks[i].funcs->hw_init(adev); + r = adev->ip_blocks[i].funcs->hw_init((void *)adev); if (r) return r; r = amdgpu_wb_init(adev); @@ -1243,9 +1243,9 @@ static int amdgpu_init(struct amdgpu_device *adev) if (!adev->ip_block_enabled[i]) continue; /* gmc hw init is done early */ - if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) + if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) continue; - r = adev->ip_blocks[i].funcs->hw_init(adev); + r = adev->ip_blocks[i].funcs->hw_init((void *)adev); if (r) return r; } @@ -1261,12 +1261,12 @@ static int amdgpu_late_init(struct amdgpu_device *adev) if (!adev->ip_block_enabled[i]) continue; /* enable clockgating to save power */ - r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, - AMDGPU_CG_STATE_GATE); + r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, + AMD_CG_STATE_GATE); if (r) return r; if (adev->ip_blocks[i].funcs->late_init) { - r = adev->ip_blocks[i].funcs->late_init(adev); + r = adev->ip_blocks[i].funcs->late_init((void *)adev); if (r) return r; } @@ -1282,23 +1282,23 @@ static int amdgpu_fini(struct amdgpu_device *adev) for (i = adev->num_ip_blocks - 1; i >= 0; i--) { if (!adev->ip_block_enabled[i]) continue; - if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) { + if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { amdgpu_wb_fini(adev); amdgpu_vram_scratch_fini(adev); } /* ungate blocks before hw fini so that we can shutdown the blocks safely */ - r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, - AMDGPU_CG_STATE_UNGATE); + r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, + AMD_CG_STATE_UNGATE); if (r) return r; - r = adev->ip_blocks[i].funcs->hw_fini(adev); + r = adev->ip_blocks[i].funcs->hw_fini((void *)adev); /* XXX handle errors */ } for (i = adev->num_ip_blocks - 1; i >= 0; i--) { if (!adev->ip_block_enabled[i]) continue; - r = adev->ip_blocks[i].funcs->sw_fini(adev); + r = adev->ip_blocks[i].funcs->sw_fini((void *)adev); /* XXX handle errors */ adev->ip_block_enabled[i] = false; } @@ -1314,8 +1314,8 @@ static int amdgpu_suspend(struct amdgpu_device *adev) if (!adev->ip_block_enabled[i]) continue; /* ungate blocks so that suspend can properly shut them down */ - r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, - AMDGPU_CG_STATE_UNGATE); + r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, + AMD_CG_STATE_UNGATE); /* XXX handle errors */ r = adev->ip_blocks[i].funcs->suspend(adev); /* XXX handle errors */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 35185d6b7d46..b6dd3751d9a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -186,7 +186,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; case AMDGPU_INFO_HW_IP_INFO: { struct drm_amdgpu_info_hw_ip ip = {}; - enum amdgpu_ip_block_type type; + enum amd_ip_block_type type; uint32_t ring_mask = 0; if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) @@ -194,26 +194,26 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file switch (info->query_hw_ip.type) { case AMDGPU_HW_IP_GFX: - type = AMDGPU_IP_BLOCK_TYPE_GFX; + type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_gfx_rings; i++) ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); break; case AMDGPU_HW_IP_COMPUTE: - type = AMDGPU_IP_BLOCK_TYPE_GFX; + type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_compute_rings; i++) ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); break; case AMDGPU_HW_IP_DMA: - type = AMDGPU_IP_BLOCK_TYPE_SDMA; + type = AMD_IP_BLOCK_TYPE_SDMA; ring_mask = adev->sdma[0].ring.ready ? 1 : 0; ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1); break; case AMDGPU_HW_IP_UVD: - type = AMDGPU_IP_BLOCK_TYPE_UVD; + type = AMD_IP_BLOCK_TYPE_UVD; ring_mask = adev->uvd.ring.ready ? 1 : 0; break; case AMDGPU_HW_IP_VCE: - type = AMDGPU_IP_BLOCK_TYPE_VCE; + type = AMD_IP_BLOCK_TYPE_VCE; for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++) ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); break; @@ -235,24 +235,24 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file min((size_t)size, sizeof(ip))) ? -EFAULT : 0; } case AMDGPU_INFO_HW_IP_COUNT: { - enum amdgpu_ip_block_type type; + enum amd_ip_block_type type; uint32_t count = 0; switch (info->query_hw_ip.type) { case AMDGPU_HW_IP_GFX: - type = AMDGPU_IP_BLOCK_TYPE_GFX; + type = AMD_IP_BLOCK_TYPE_GFX; break; case AMDGPU_HW_IP_COMPUTE: - type = AMDGPU_IP_BLOCK_TYPE_GFX; + type = AMD_IP_BLOCK_TYPE_GFX; break; case AMDGPU_HW_IP_DMA: - type = AMDGPU_IP_BLOCK_TYPE_SDMA; + type = AMD_IP_BLOCK_TYPE_SDMA; break; case AMDGPU_HW_IP_UVD: - type = AMDGPU_IP_BLOCK_TYPE_UVD; + type = AMD_IP_BLOCK_TYPE_UVD; break; case AMDGPU_HW_IP_VCE: - type = AMDGPU_IP_BLOCK_TYPE_VCE; + type = AMD_IP_BLOCK_TYPE_VCE; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 4b0be906d235..375759c8639c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -185,7 +185,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) } /* from uvd v5.0 HW addressing capacity increased to 64 bits */ - if (!amdgpu_ip_block_version_cmp(adev, AMDGPU_IP_BLOCK_TYPE_UVD, 5, 0)) + if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) adev->uvd.address_64_bit = true; return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 5a9dad8e55c9..03809f1bcfd5 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -4227,8 +4227,8 @@ static int ci_update_vce_dpm(struct amdgpu_device *adev, if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) { if (amdgpu_new_state->evclk) { /* turn the clocks on when encoding */ - ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, - AMDGPU_CG_STATE_UNGATE); + ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_CG_STATE_UNGATE); if (ret) return ret; @@ -4241,8 +4241,8 @@ static int ci_update_vce_dpm(struct amdgpu_device *adev, ret = ci_enable_vce_dpm(adev, true); } else { /* turn the clocks off when not encoding */ - ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, - AMDGPU_CG_STATE_GATE); + ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_CG_STATE_GATE); if (ret) return ret; @@ -6171,17 +6171,20 @@ static int ci_set_temperature_range(struct amdgpu_device *adev) return ret; } -static int ci_dpm_early_init(struct amdgpu_device *adev) +static int ci_dpm_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + ci_dpm_set_dpm_funcs(adev); ci_dpm_set_irq_funcs(adev); return 0; } -static int ci_dpm_late_init(struct amdgpu_device *adev) +static int ci_dpm_late_init(void *handle) { int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (!amdgpu_dpm) return 0; @@ -6195,9 +6198,10 @@ static int ci_dpm_late_init(struct amdgpu_device *adev) return 0; } -static int ci_dpm_sw_init(struct amdgpu_device *adev) +static int ci_dpm_sw_init(void *handle) { int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); if (ret) @@ -6243,8 +6247,10 @@ dpm_failed: return ret; } -static int ci_dpm_sw_fini(struct amdgpu_device *adev) +static int ci_dpm_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + mutex_lock(&adev->pm.mutex); amdgpu_pm_sysfs_fini(adev); ci_dpm_fini(adev); @@ -6253,10 +6259,12 @@ static int ci_dpm_sw_fini(struct amdgpu_device *adev) return 0; } -static int ci_dpm_hw_init(struct amdgpu_device *adev) +static int ci_dpm_hw_init(void *handle) { int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (!amdgpu_dpm) return 0; @@ -6272,8 +6280,10 @@ static int ci_dpm_hw_init(struct amdgpu_device *adev) return ret; } -static int ci_dpm_hw_fini(struct amdgpu_device *adev) +static int ci_dpm_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (adev->pm.dpm_enabled) { mutex_lock(&adev->pm.mutex); ci_dpm_disable(adev); @@ -6283,8 +6293,10 @@ static int ci_dpm_hw_fini(struct amdgpu_device *adev) return 0; } -static int ci_dpm_suspend(struct amdgpu_device *adev) +static int ci_dpm_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (adev->pm.dpm_enabled) { mutex_lock(&adev->pm.mutex); /* disable dpm */ @@ -6296,9 +6308,10 @@ static int ci_dpm_suspend(struct amdgpu_device *adev) return 0; } -static int ci_dpm_resume(struct amdgpu_device *adev) +static int ci_dpm_resume(void *handle) { int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev->pm.dpm_enabled) { /* asic init will reset to the boot state */ @@ -6316,20 +6329,22 @@ static int ci_dpm_resume(struct amdgpu_device *adev) return 0; } -static bool ci_dpm_is_idle(struct amdgpu_device *adev) +static bool ci_dpm_is_idle(void *handle) { /* XXX */ return true; } -static int ci_dpm_wait_for_idle(struct amdgpu_device *adev) +static int ci_dpm_wait_for_idle(void *handle) { /* XXX */ return 0; } -static void ci_dpm_print_status(struct amdgpu_device *adev) +static void ci_dpm_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + dev_info(adev->dev, "CIK DPM registers\n"); dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n", RREG32(mmBIOS_SCRATCH_4)); @@ -6535,7 +6550,7 @@ static void ci_dpm_print_status(struct amdgpu_device *adev) RREG32_SMC(ixSMC_PC_C)); } -static int ci_dpm_soft_reset(struct amdgpu_device *adev) +static int ci_dpm_soft_reset(void *handle) { return 0; } @@ -6618,19 +6633,19 @@ static int ci_dpm_process_interrupt(struct amdgpu_device *adev, return 0; } -static int ci_dpm_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int ci_dpm_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } -static int ci_dpm_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int ci_dpm_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs ci_dpm_ip_funcs = { +const struct amd_ip_funcs ci_dpm_ip_funcs = { .early_init = ci_dpm_early_init, .late_init = ci_dpm_late_init, .sw_init = ci_dpm_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 74ce0be2fbb7..5dab578d6462 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1892,63 +1892,63 @@ static const struct amdgpu_ip_block_version bonaire_ip_blocks[] = { /* ORDER MATTERS! */ { - .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 1, .minor = 0, .rev = 0, .funcs = &cik_common_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .type = AMD_IP_BLOCK_TYPE_GMC, .major = 7, .minor = 0, .rev = 0, .funcs = &gmc_v7_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_IH, + .type = AMD_IP_BLOCK_TYPE_IH, .major = 2, .minor = 0, .rev = 0, .funcs = &cik_ih_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .type = AMD_IP_BLOCK_TYPE_SMC, .major = 7, .minor = 0, .rev = 0, .funcs = &ci_dpm_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .type = AMD_IP_BLOCK_TYPE_DCE, .major = 8, .minor = 2, .rev = 0, .funcs = &dce_v8_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .type = AMD_IP_BLOCK_TYPE_GFX, .major = 7, .minor = 2, .rev = 0, .funcs = &gfx_v7_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 2, .minor = 0, .rev = 0, .funcs = &cik_sdma_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .type = AMD_IP_BLOCK_TYPE_UVD, .major = 4, .minor = 2, .rev = 0, .funcs = &uvd_v4_2_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .type = AMD_IP_BLOCK_TYPE_VCE, .major = 2, .minor = 0, .rev = 0, @@ -1960,63 +1960,63 @@ static const struct amdgpu_ip_block_version hawaii_ip_blocks[] = { /* ORDER MATTERS! */ { - .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 1, .minor = 0, .rev = 0, .funcs = &cik_common_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .type = AMD_IP_BLOCK_TYPE_GMC, .major = 7, .minor = 0, .rev = 0, .funcs = &gmc_v7_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_IH, + .type = AMD_IP_BLOCK_TYPE_IH, .major = 2, .minor = 0, .rev = 0, .funcs = &cik_ih_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .type = AMD_IP_BLOCK_TYPE_SMC, .major = 7, .minor = 0, .rev = 0, .funcs = &ci_dpm_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .type = AMD_IP_BLOCK_TYPE_DCE, .major = 8, .minor = 5, .rev = 0, .funcs = &dce_v8_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .type = AMD_IP_BLOCK_TYPE_GFX, .major = 7, .minor = 3, .rev = 0, .funcs = &gfx_v7_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 2, .minor = 0, .rev = 0, .funcs = &cik_sdma_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .type = AMD_IP_BLOCK_TYPE_UVD, .major = 4, .minor = 2, .rev = 0, .funcs = &uvd_v4_2_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .type = AMD_IP_BLOCK_TYPE_VCE, .major = 2, .minor = 0, .rev = 0, @@ -2028,63 +2028,63 @@ static const struct amdgpu_ip_block_version kabini_ip_blocks[] = { /* ORDER MATTERS! */ { - .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 1, .minor = 0, .rev = 0, .funcs = &cik_common_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .type = AMD_IP_BLOCK_TYPE_GMC, .major = 7, .minor = 0, .rev = 0, .funcs = &gmc_v7_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_IH, + .type = AMD_IP_BLOCK_TYPE_IH, .major = 2, .minor = 0, .rev = 0, .funcs = &cik_ih_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .type = AMD_IP_BLOCK_TYPE_SMC, .major = 7, .minor = 0, .rev = 0, .funcs = &kv_dpm_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .type = AMD_IP_BLOCK_TYPE_DCE, .major = 8, .minor = 3, .rev = 0, .funcs = &dce_v8_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .type = AMD_IP_BLOCK_TYPE_GFX, .major = 7, .minor = 2, .rev = 0, .funcs = &gfx_v7_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 2, .minor = 0, .rev = 0, .funcs = &cik_sdma_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .type = AMD_IP_BLOCK_TYPE_UVD, .major = 4, .minor = 2, .rev = 0, .funcs = &uvd_v4_2_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .type = AMD_IP_BLOCK_TYPE_VCE, .major = 2, .minor = 0, .rev = 0, @@ -2096,63 +2096,63 @@ static const struct amdgpu_ip_block_version mullins_ip_blocks[] = { /* ORDER MATTERS! */ { - .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 1, .minor = 0, .rev = 0, .funcs = &cik_common_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .type = AMD_IP_BLOCK_TYPE_GMC, .major = 7, .minor = 0, .rev = 0, .funcs = &gmc_v7_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_IH, + .type = AMD_IP_BLOCK_TYPE_IH, .major = 2, .minor = 0, .rev = 0, .funcs = &cik_ih_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .type = AMD_IP_BLOCK_TYPE_SMC, .major = 7, .minor = 0, .rev = 0, .funcs = &kv_dpm_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .type = AMD_IP_BLOCK_TYPE_DCE, .major = 8, .minor = 3, .rev = 0, .funcs = &dce_v8_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .type = AMD_IP_BLOCK_TYPE_GFX, .major = 7, .minor = 2, .rev = 0, .funcs = &gfx_v7_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 2, .minor = 0, .rev = 0, .funcs = &cik_sdma_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .type = AMD_IP_BLOCK_TYPE_UVD, .major = 4, .minor = 2, .rev = 0, .funcs = &uvd_v4_2_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .type = AMD_IP_BLOCK_TYPE_VCE, .major = 2, .minor = 0, .rev = 0, @@ -2164,63 +2164,63 @@ static const struct amdgpu_ip_block_version kaveri_ip_blocks[] = { /* ORDER MATTERS! */ { - .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 1, .minor = 0, .rev = 0, .funcs = &cik_common_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .type = AMD_IP_BLOCK_TYPE_GMC, .major = 7, .minor = 0, .rev = 0, .funcs = &gmc_v7_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_IH, + .type = AMD_IP_BLOCK_TYPE_IH, .major = 2, .minor = 0, .rev = 0, .funcs = &cik_ih_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .type = AMD_IP_BLOCK_TYPE_SMC, .major = 7, .minor = 0, .rev = 0, .funcs = &kv_dpm_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .type = AMD_IP_BLOCK_TYPE_DCE, .major = 8, .minor = 1, .rev = 0, .funcs = &dce_v8_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .type = AMD_IP_BLOCK_TYPE_GFX, .major = 7, .minor = 1, .rev = 0, .funcs = &gfx_v7_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 2, .minor = 0, .rev = 0, .funcs = &cik_sdma_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .type = AMD_IP_BLOCK_TYPE_UVD, .major = 4, .minor = 2, .rev = 0, .funcs = &uvd_v4_2_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .type = AMD_IP_BLOCK_TYPE_VCE, .major = 2, .minor = 0, .rev = 0, @@ -2278,8 +2278,10 @@ static const struct amdgpu_asic_funcs cik_asic_funcs = .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle, }; -static int cik_common_early_init(struct amdgpu_device *adev) +static int cik_common_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + adev->smc_rreg = &cik_smc_rreg; adev->smc_wreg = &cik_smc_wreg; adev->pcie_rreg = &cik_pcie_rreg; @@ -2417,18 +2419,20 @@ static int cik_common_early_init(struct amdgpu_device *adev) return 0; } -static int cik_common_sw_init(struct amdgpu_device *adev) +static int cik_common_sw_init(void *handle) { return 0; } -static int cik_common_sw_fini(struct amdgpu_device *adev) +static int cik_common_sw_fini(void *handle) { return 0; } -static int cik_common_hw_init(struct amdgpu_device *adev) +static int cik_common_hw_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + /* move the golden regs per IP block */ cik_init_golden_registers(adev); /* enable pcie gen2/3 link */ @@ -2439,55 +2443,59 @@ static int cik_common_hw_init(struct amdgpu_device *adev) return 0; } -static int cik_common_hw_fini(struct amdgpu_device *adev) +static int cik_common_hw_fini(void *handle) { return 0; } -static int cik_common_suspend(struct amdgpu_device *adev) +static int cik_common_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return cik_common_hw_fini(adev); } -static int cik_common_resume(struct amdgpu_device *adev) +static int cik_common_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return cik_common_hw_init(adev); } -static bool cik_common_is_idle(struct amdgpu_device *adev) +static bool cik_common_is_idle(void *handle) { return true; } -static int cik_common_wait_for_idle(struct amdgpu_device *adev) +static int cik_common_wait_for_idle(void *handle) { return 0; } -static void cik_common_print_status(struct amdgpu_device *adev) +static void cik_common_print_status(void *handle) { } -static int cik_common_soft_reset(struct amdgpu_device *adev) +static int cik_common_soft_reset(void *handle) { /* XXX hard reset?? */ return 0; } -static int cik_common_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int cik_common_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } -static int cik_common_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int cik_common_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs cik_common_ip_funcs = { +const struct amd_ip_funcs cik_common_ip_funcs = { .early_init = cik_common_early_init, .late_init = NULL, .sw_init = cik_common_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h index 967d630a4dcb..5ebd2d7a0327 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.h +++ b/drivers/gpu/drm/amd/amdgpu/cik.h @@ -24,7 +24,7 @@ #ifndef __CIK_H__ #define __CIK_H__ -extern const struct amdgpu_ip_funcs cik_common_ip_funcs; +extern const struct amd_ip_funcs cik_common_ip_funcs; void cik_srbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); diff --git a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h index 35d8efdcde7e..b1c8e7b446ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h @@ -24,7 +24,7 @@ #ifndef __CIK_DPM_H__ #define __CIK_DPM_H__ -extern const struct amdgpu_ip_funcs ci_dpm_ip_funcs; -extern const struct amdgpu_ip_funcs kv_dpm_ip_funcs; +extern const struct amd_ip_funcs ci_dpm_ip_funcs; +extern const struct amd_ip_funcs kv_dpm_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index 81e8bbaba3e8..8993c50cb89f 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -271,16 +271,19 @@ static void cik_ih_set_rptr(struct amdgpu_device *adev) WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); } -static int cik_ih_early_init(struct amdgpu_device *adev) +static int cik_ih_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + cik_ih_set_interrupt_funcs(adev); return 0; } -static int cik_ih_sw_init(struct amdgpu_device *adev) +static int cik_ih_sw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_ih_ring_init(adev, 64 * 1024, false); if (r) @@ -291,17 +294,20 @@ static int cik_ih_sw_init(struct amdgpu_device *adev) return r; } -static int cik_ih_sw_fini(struct amdgpu_device *adev) +static int cik_ih_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_irq_fini(adev); amdgpu_ih_ring_fini(adev); return 0; } -static int cik_ih_hw_init(struct amdgpu_device *adev) +static int cik_ih_hw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = cik_ih_irq_init(adev); if (r) @@ -310,25 +316,32 @@ static int cik_ih_hw_init(struct amdgpu_device *adev) return 0; } -static int cik_ih_hw_fini(struct amdgpu_device *adev) +static int cik_ih_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + cik_ih_irq_disable(adev); return 0; } -static int cik_ih_suspend(struct amdgpu_device *adev) +static int cik_ih_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return cik_ih_hw_fini(adev); } -static int cik_ih_resume(struct amdgpu_device *adev) +static int cik_ih_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return cik_ih_hw_init(adev); } -static bool cik_ih_is_idle(struct amdgpu_device *adev) +static bool cik_ih_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & SRBM_STATUS__IH_BUSY_MASK) @@ -337,10 +350,11 @@ static bool cik_ih_is_idle(struct amdgpu_device *adev) return true; } -static int cik_ih_wait_for_idle(struct amdgpu_device *adev) +static int cik_ih_wait_for_idle(void *handle) { unsigned i; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ @@ -352,8 +366,10 @@ static int cik_ih_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static void cik_ih_print_status(struct amdgpu_device *adev) +static void cik_ih_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + dev_info(adev->dev, "CIK IH registers\n"); dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", RREG32(mmSRBM_STATUS)); @@ -379,8 +395,10 @@ static void cik_ih_print_status(struct amdgpu_device *adev) RREG32(mmIH_RB_WPTR)); } -static int cik_ih_soft_reset(struct amdgpu_device *adev) +static int cik_ih_soft_reset(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 srbm_soft_reset = 0; u32 tmp = RREG32(mmSRBM_STATUS); @@ -388,7 +406,7 @@ static int cik_ih_soft_reset(struct amdgpu_device *adev) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; if (srbm_soft_reset) { - cik_ih_print_status(adev); + cik_ih_print_status((void *)adev); tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; @@ -405,25 +423,25 @@ static int cik_ih_soft_reset(struct amdgpu_device *adev) /* Wait a little for things to settle down */ udelay(50); - cik_ih_print_status(adev); + cik_ih_print_status((void *)adev); } return 0; } -static int cik_ih_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int cik_ih_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } -static int cik_ih_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int cik_ih_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs cik_ih_ip_funcs = { +const struct amd_ip_funcs cik_ih_ip_funcs = { .early_init = cik_ih_early_init, .late_init = NULL, .sw_init = cik_ih_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.h b/drivers/gpu/drm/amd/amdgpu/cik_ih.h index f70162525034..6b0f375ec244 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.h @@ -24,6 +24,6 @@ #ifndef __CIK_IH_H__ #define __CIK_IH_H__ -extern const struct amdgpu_ip_funcs cik_ih_ip_funcs; +extern const struct amd_ip_funcs cik_ih_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index d5055ea4d112..7c816b5cf17a 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -927,8 +927,10 @@ static void cik_enable_sdma_mgls(struct amdgpu_device *adev, } } -static int cik_sdma_early_init(struct amdgpu_device *adev) +static int cik_sdma_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + cik_sdma_set_ring_funcs(adev); cik_sdma_set_irq_funcs(adev); cik_sdma_set_buffer_funcs(adev); @@ -937,9 +939,10 @@ static int cik_sdma_early_init(struct amdgpu_device *adev) return 0; } -static int cik_sdma_sw_init(struct amdgpu_device *adev) +static int cik_sdma_sw_init(void *handle) { struct amdgpu_ring *ring; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = cik_sdma_init_microcode(adev); @@ -990,17 +993,20 @@ static int cik_sdma_sw_init(struct amdgpu_device *adev) return r; } -static int cik_sdma_sw_fini(struct amdgpu_device *adev) +static int cik_sdma_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_ring_fini(&adev->sdma[0].ring); amdgpu_ring_fini(&adev->sdma[1].ring); return 0; } -static int cik_sdma_hw_init(struct amdgpu_device *adev) +static int cik_sdma_hw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = cik_sdma_start(adev); if (r) @@ -1009,27 +1015,32 @@ static int cik_sdma_hw_init(struct amdgpu_device *adev) return r; } -static int cik_sdma_hw_fini(struct amdgpu_device *adev) +static int cik_sdma_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + cik_sdma_enable(adev, false); return 0; } -static int cik_sdma_suspend(struct amdgpu_device *adev) +static int cik_sdma_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; return cik_sdma_hw_fini(adev); } -static int cik_sdma_resume(struct amdgpu_device *adev) +static int cik_sdma_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; return cik_sdma_hw_init(adev); } -static bool cik_sdma_is_idle(struct amdgpu_device *adev) +static bool cik_sdma_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS2); if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | @@ -1039,10 +1050,11 @@ static bool cik_sdma_is_idle(struct amdgpu_device *adev) return true; } -static int cik_sdma_wait_for_idle(struct amdgpu_device *adev) +static int cik_sdma_wait_for_idle(void *handle) { unsigned i; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | @@ -1055,9 +1067,10 @@ static int cik_sdma_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static void cik_sdma_print_status(struct amdgpu_device *adev) +static void cik_sdma_print_status(void *handle) { int i, j; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dev_info(adev->dev, "CIK SDMA registers\n"); dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", @@ -1103,9 +1116,10 @@ static void cik_sdma_print_status(struct amdgpu_device *adev) } } -static int cik_sdma_soft_reset(struct amdgpu_device *adev) +static int cik_sdma_soft_reset(void *handle) { u32 srbm_soft_reset = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS2); if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { @@ -1124,7 +1138,7 @@ static int cik_sdma_soft_reset(struct amdgpu_device *adev) } if (srbm_soft_reset) { - cik_sdma_print_status(adev); + cik_sdma_print_status((void *)adev); tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; @@ -1141,7 +1155,7 @@ static int cik_sdma_soft_reset(struct amdgpu_device *adev) /* Wait a little for things to settle down */ udelay(50); - cik_sdma_print_status(adev); + cik_sdma_print_status((void *)adev); } return 0; @@ -1243,12 +1257,13 @@ static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, return 0; } -static int cik_sdma_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int cik_sdma_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { bool gate = false; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (state == AMDGPU_CG_STATE_GATE) + if (state == AMD_CG_STATE_GATE) gate = true; cik_enable_sdma_mgcg(adev, gate); @@ -1257,13 +1272,13 @@ static int cik_sdma_set_clockgating_state(struct amdgpu_device *adev, return 0; } -static int cik_sdma_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int cik_sdma_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs cik_sdma_ip_funcs = { +const struct amd_ip_funcs cik_sdma_ip_funcs = { .early_init = cik_sdma_early_init, .late_init = NULL, .sw_init = cik_sdma_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h index 42b59960bc53..027727c677b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.h +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.h @@ -24,6 +24,6 @@ #ifndef __CIK_SDMA_H__ #define __CIK_SDMA_H__ -extern const struct amdgpu_ip_funcs cik_sdma_ip_funcs; +extern const struct amd_ip_funcs cik_sdma_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index 2649b505d2d0..f275b5d2d060 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -542,24 +542,29 @@ static void cz_dpm_print_power_state(struct amdgpu_device *adev, static void cz_dpm_set_funcs(struct amdgpu_device *adev); -static int cz_dpm_early_init(struct amdgpu_device *adev) +static int cz_dpm_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + cz_dpm_set_funcs(adev); return 0; } -static int cz_dpm_late_init(struct amdgpu_device *adev) +static int cz_dpm_late_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + /* powerdown unused blocks for now */ cz_dpm_powergate_uvd(adev, true); return 0; } -static int cz_dpm_sw_init(struct amdgpu_device *adev) +static int cz_dpm_sw_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int ret = 0; /* fix me to add thermal support TODO */ @@ -602,8 +607,10 @@ dpm_init_failed: return ret; } -static int cz_dpm_sw_fini(struct amdgpu_device *adev) +static int cz_dpm_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + mutex_lock(&adev->pm.mutex); amdgpu_pm_sysfs_fini(adev); cz_dpm_fini(adev); @@ -1216,8 +1223,9 @@ static int cz_dpm_enable(struct amdgpu_device *adev) return 0; } -static int cz_dpm_hw_init(struct amdgpu_device *adev) +static int cz_dpm_hw_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int ret = 0; mutex_lock(&adev->pm.mutex); @@ -1282,9 +1290,10 @@ static int cz_dpm_disable(struct amdgpu_device *adev) return 0; } -static int cz_dpm_hw_fini(struct amdgpu_device *adev) +static int cz_dpm_hw_fini(void *handle) { int ret = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; mutex_lock(&adev->pm.mutex); @@ -1305,9 +1314,10 @@ static int cz_dpm_hw_fini(struct amdgpu_device *adev) return ret; } -static int cz_dpm_suspend(struct amdgpu_device *adev) +static int cz_dpm_suspend(void *handle) { int ret = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev->pm.dpm_enabled) { mutex_lock(&adev->pm.mutex); @@ -1324,9 +1334,10 @@ static int cz_dpm_suspend(struct amdgpu_device *adev) return ret; } -static int cz_dpm_resume(struct amdgpu_device *adev) +static int cz_dpm_resume(void *handle) { int ret = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; mutex_lock(&adev->pm.mutex); ret = cz_smu_init(adev); @@ -1368,14 +1379,14 @@ static int cz_dpm_resume(struct amdgpu_device *adev) return 0; } -static int cz_dpm_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int cz_dpm_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } -static int cz_dpm_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int cz_dpm_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } @@ -1733,11 +1744,11 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) if (gate) { if (pi->caps_uvd_pg) { /* disable clockgating so we can properly shut down the block */ - ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, - AMDGPU_CG_STATE_UNGATE); + ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_CG_STATE_UNGATE); /* shutdown the UVD block */ - ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, - AMDGPU_PG_STATE_GATE); + ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_GATE); /* XXX: check for errors */ } cz_update_uvd_dpm(adev, gate); @@ -1752,18 +1763,18 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) else cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0); /* re-init the UVD block */ - ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, - AMDGPU_PG_STATE_UNGATE); + ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_UNGATE); /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */ - ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, - AMDGPU_CG_STATE_GATE); + ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_CG_STATE_GATE); /* XXX: check for errors */ } cz_update_uvd_dpm(adev, gate); } } -const struct amdgpu_ip_funcs cz_dpm_ip_funcs = { +const struct amd_ip_funcs cz_dpm_ip_funcs = { .early_init = cz_dpm_early_init, .late_init = cz_dpm_late_init, .sw_init = cz_dpm_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index 80d508e64a86..bc751bfbcae2 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -250,15 +250,18 @@ static void cz_ih_set_rptr(struct amdgpu_device *adev) WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); } -static int cz_ih_early_init(struct amdgpu_device *adev) +static int cz_ih_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + cz_ih_set_interrupt_funcs(adev); return 0; } -static int cz_ih_sw_init(struct amdgpu_device *adev) +static int cz_ih_sw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_ih_ring_init(adev, 64 * 1024, false); if (r) @@ -269,17 +272,20 @@ static int cz_ih_sw_init(struct amdgpu_device *adev) return r; } -static int cz_ih_sw_fini(struct amdgpu_device *adev) +static int cz_ih_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_irq_fini(adev); amdgpu_ih_ring_fini(adev); return 0; } -static int cz_ih_hw_init(struct amdgpu_device *adev) +static int cz_ih_hw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = cz_ih_irq_init(adev); if (r) @@ -288,25 +294,32 @@ static int cz_ih_hw_init(struct amdgpu_device *adev) return 0; } -static int cz_ih_hw_fini(struct amdgpu_device *adev) +static int cz_ih_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + cz_ih_irq_disable(adev); return 0; } -static int cz_ih_suspend(struct amdgpu_device *adev) +static int cz_ih_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return cz_ih_hw_fini(adev); } -static int cz_ih_resume(struct amdgpu_device *adev) +static int cz_ih_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return cz_ih_hw_init(adev); } -static bool cz_ih_is_idle(struct amdgpu_device *adev) +static bool cz_ih_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS); if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) @@ -315,10 +328,11 @@ static bool cz_ih_is_idle(struct amdgpu_device *adev) return true; } -static int cz_ih_wait_for_idle(struct amdgpu_device *adev) +static int cz_ih_wait_for_idle(void *handle) { unsigned i; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ @@ -330,8 +344,10 @@ static int cz_ih_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static void cz_ih_print_status(struct amdgpu_device *adev) +static void cz_ih_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + dev_info(adev->dev, "CZ IH registers\n"); dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", RREG32(mmSRBM_STATUS)); @@ -357,9 +373,10 @@ static void cz_ih_print_status(struct amdgpu_device *adev) RREG32(mmIH_RB_WPTR)); } -static int cz_ih_soft_reset(struct amdgpu_device *adev) +static int cz_ih_soft_reset(void *handle) { u32 srbm_soft_reset = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & SRBM_STATUS__IH_BUSY_MASK) @@ -367,7 +384,7 @@ static int cz_ih_soft_reset(struct amdgpu_device *adev) SOFT_RESET_IH, 1); if (srbm_soft_reset) { - cz_ih_print_status(adev); + cz_ih_print_status((void *)adev); tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; @@ -384,27 +401,27 @@ static int cz_ih_soft_reset(struct amdgpu_device *adev) /* Wait a little for things to settle down */ udelay(50); - cz_ih_print_status(adev); + cz_ih_print_status((void *)adev); } return 0; } -static int cz_ih_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int cz_ih_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { // TODO return 0; } -static int cz_ih_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int cz_ih_set_powergating_state(void *handle, + enum amd_powergating_state state) { // TODO return 0; } -const struct amdgpu_ip_funcs cz_ih_ip_funcs = { +const struct amd_ip_funcs cz_ih_ip_funcs = { .early_init = cz_ih_early_init, .late_init = NULL, .sw_init = cz_ih_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.h b/drivers/gpu/drm/amd/amdgpu/cz_ih.h index 1bce136876ff..fc4057a2ecb9 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.h @@ -24,6 +24,6 @@ #ifndef __CZ_IH_H__ #define __CZ_IH_H__ -extern const struct amdgpu_ip_funcs cz_ih_ip_funcs; +extern const struct amd_ip_funcs cz_ih_ip_funcs; #endif /* __CZ_IH_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 37b96236fe2c..da9a4b9a1f6c 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2864,8 +2864,10 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) return 0; } -static int dce_v10_0_early_init(struct amdgpu_device *adev) +static int dce_v10_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; @@ -2886,9 +2888,10 @@ static int dce_v10_0_early_init(struct amdgpu_device *adev) return 0; } -static int dce_v10_0_sw_init(struct amdgpu_device *adev) +static int dce_v10_0_sw_init(void *handle) { int r, i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->mode_info.num_crtc; i++) { r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); @@ -2950,8 +2953,10 @@ static int dce_v10_0_sw_init(struct amdgpu_device *adev) return r; } -static int dce_v10_0_sw_fini(struct amdgpu_device *adev) +static int dce_v10_0_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + kfree(adev->mode_info.bios_hardcoded_edid); drm_kms_helper_poll_fini(adev->ddev); @@ -2966,9 +2971,10 @@ static int dce_v10_0_sw_fini(struct amdgpu_device *adev) return 0; } -static int dce_v10_0_hw_init(struct amdgpu_device *adev) +static int dce_v10_0_hw_init(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dce_v10_0_init_golden_registers(adev); @@ -2986,9 +2992,10 @@ static int dce_v10_0_hw_init(struct amdgpu_device *adev) return 0; } -static int dce_v10_0_hw_fini(struct amdgpu_device *adev) +static int dce_v10_0_hw_fini(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dce_v10_0_hpd_fini(adev); @@ -2999,9 +3006,10 @@ static int dce_v10_0_hw_fini(struct amdgpu_device *adev) return 0; } -static int dce_v10_0_suspend(struct amdgpu_device *adev) +static int dce_v10_0_suspend(void *handle) { struct drm_connector *connector; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; drm_kms_helper_poll_disable(adev->ddev); @@ -3017,9 +3025,10 @@ static int dce_v10_0_suspend(struct amdgpu_device *adev) return 0; } -static int dce_v10_0_resume(struct amdgpu_device *adev) +static int dce_v10_0_resume(void *handle) { struct drm_connector *connector; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dce_v10_0_init_golden_registers(adev); @@ -3051,33 +3060,34 @@ static int dce_v10_0_resume(struct amdgpu_device *adev) return 0; } -static bool dce_v10_0_is_idle(struct amdgpu_device *adev) +static bool dce_v10_0_is_idle(void *handle) { - /* XXX todo */ return true; } -static int dce_v10_0_wait_for_idle(struct amdgpu_device *adev) +static int dce_v10_0_wait_for_idle(void *handle) { - /* XXX todo */ return 0; } -static void dce_v10_0_print_status(struct amdgpu_device *adev) +static void dce_v10_0_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + dev_info(adev->dev, "DCE 10.x registers\n"); /* XXX todo */ } -static int dce_v10_0_soft_reset(struct amdgpu_device *adev) +static int dce_v10_0_soft_reset(void *handle) { u32 srbm_soft_reset = 0, tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (dce_v10_0_is_display_hung(adev)) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; if (srbm_soft_reset) { - dce_v10_0_print_status(adev); + dce_v10_0_print_status((void *)adev); tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; @@ -3093,7 +3103,7 @@ static int dce_v10_0_soft_reset(struct amdgpu_device *adev) /* Wait a little for things to settle down */ udelay(50); - dce_v10_0_print_status(adev); + dce_v10_0_print_status((void *)adev); } return 0; } @@ -3449,19 +3459,19 @@ static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, return 0; } -static int dce_v10_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int dce_v10_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } -static int dce_v10_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int dce_v10_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs dce_v10_0_ip_funcs = { +const struct amd_ip_funcs dce_v10_0_ip_funcs = { .early_init = dce_v10_0_early_init, .late_init = NULL, .sw_init = dce_v10_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h index 72ca20d1793c..1bfa48ddd8a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.h @@ -24,6 +24,6 @@ #ifndef __DCE_V10_0_H__ #define __DCE_V10_0_H__ -extern const struct amdgpu_ip_funcs dce_v10_0_ip_funcs; +extern const struct amd_ip_funcs dce_v10_0_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 04a5d4cd75b6..edd9d17ba82a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2863,8 +2863,10 @@ static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) return 0; } -static int dce_v11_0_early_init(struct amdgpu_device *adev) +static int dce_v11_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; @@ -2885,9 +2887,10 @@ static int dce_v11_0_early_init(struct amdgpu_device *adev) return 0; } -static int dce_v11_0_sw_init(struct amdgpu_device *adev) +static int dce_v11_0_sw_init(void *handle) { int r, i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->mode_info.num_crtc; i++) { r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); @@ -2949,8 +2952,10 @@ static int dce_v11_0_sw_init(struct amdgpu_device *adev) return r; } -static int dce_v11_0_sw_fini(struct amdgpu_device *adev) +static int dce_v11_0_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + kfree(adev->mode_info.bios_hardcoded_edid); drm_kms_helper_poll_fini(adev->ddev); @@ -2964,9 +2969,10 @@ static int dce_v11_0_sw_fini(struct amdgpu_device *adev) return 0; } -static int dce_v11_0_hw_init(struct amdgpu_device *adev) +static int dce_v11_0_hw_init(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dce_v11_0_init_golden_registers(adev); @@ -2984,9 +2990,10 @@ static int dce_v11_0_hw_init(struct amdgpu_device *adev) return 0; } -static int dce_v11_0_hw_fini(struct amdgpu_device *adev) +static int dce_v11_0_hw_fini(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dce_v11_0_hpd_fini(adev); @@ -2997,9 +3004,10 @@ static int dce_v11_0_hw_fini(struct amdgpu_device *adev) return 0; } -static int dce_v11_0_suspend(struct amdgpu_device *adev) +static int dce_v11_0_suspend(void *handle) { struct drm_connector *connector; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; drm_kms_helper_poll_disable(adev->ddev); @@ -3015,9 +3023,10 @@ static int dce_v11_0_suspend(struct amdgpu_device *adev) return 0; } -static int dce_v11_0_resume(struct amdgpu_device *adev) +static int dce_v11_0_resume(void *handle) { struct drm_connector *connector; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dce_v11_0_init_golden_registers(adev); @@ -3050,33 +3059,34 @@ static int dce_v11_0_resume(struct amdgpu_device *adev) return 0; } -static bool dce_v11_0_is_idle(struct amdgpu_device *adev) +static bool dce_v11_0_is_idle(void *handle) { - /* XXX todo */ return true; } -static int dce_v11_0_wait_for_idle(struct amdgpu_device *adev) +static int dce_v11_0_wait_for_idle(void *handle) { - /* XXX todo */ return 0; } -static void dce_v11_0_print_status(struct amdgpu_device *adev) +static void dce_v11_0_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + dev_info(adev->dev, "DCE 10.x registers\n"); /* XXX todo */ } -static int dce_v11_0_soft_reset(struct amdgpu_device *adev) +static int dce_v11_0_soft_reset(void *handle) { u32 srbm_soft_reset = 0, tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (dce_v11_0_is_display_hung(adev)) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; if (srbm_soft_reset) { - dce_v11_0_print_status(adev); + dce_v11_0_print_status((void *)adev); tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; @@ -3092,7 +3102,7 @@ static int dce_v11_0_soft_reset(struct amdgpu_device *adev) /* Wait a little for things to settle down */ udelay(50); - dce_v11_0_print_status(adev); + dce_v11_0_print_status((void *)adev); } return 0; } @@ -3448,19 +3458,19 @@ static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, return 0; } -static int dce_v11_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int dce_v11_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } -static int dce_v11_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int dce_v11_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs dce_v11_0_ip_funcs = { +const struct amd_ip_funcs dce_v11_0_ip_funcs = { .early_init = dce_v11_0_early_init, .late_init = NULL, .sw_init = dce_v11_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h index eeb9a56b514a..84e4618f5253 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h @@ -24,6 +24,6 @@ #ifndef __DCE_V11_0_H__ #define __DCE_V11_0_H__ -extern const struct amdgpu_ip_funcs dce_v11_0_ip_funcs; +extern const struct amd_ip_funcs dce_v11_0_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 9f2ff8d374f3..1d291f1d5b79 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2794,8 +2794,10 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) return 0; } -static int dce_v8_0_early_init(struct amdgpu_device *adev) +static int dce_v8_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; @@ -2828,9 +2830,10 @@ static int dce_v8_0_early_init(struct amdgpu_device *adev) return 0; } -static int dce_v8_0_sw_init(struct amdgpu_device *adev) +static int dce_v8_0_sw_init(void *handle) { int r, i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->mode_info.num_crtc; i++) { r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); @@ -2892,8 +2895,10 @@ static int dce_v8_0_sw_init(struct amdgpu_device *adev) return r; } -static int dce_v8_0_sw_fini(struct amdgpu_device *adev) +static int dce_v8_0_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + kfree(adev->mode_info.bios_hardcoded_edid); drm_kms_helper_poll_fini(adev->ddev); @@ -2908,9 +2913,10 @@ static int dce_v8_0_sw_fini(struct amdgpu_device *adev) return 0; } -static int dce_v8_0_hw_init(struct amdgpu_device *adev) +static int dce_v8_0_hw_init(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* init dig PHYs, disp eng pll */ amdgpu_atombios_encoder_init_dig(adev); @@ -2926,9 +2932,10 @@ static int dce_v8_0_hw_init(struct amdgpu_device *adev) return 0; } -static int dce_v8_0_hw_fini(struct amdgpu_device *adev) +static int dce_v8_0_hw_fini(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dce_v8_0_hpd_fini(adev); @@ -2939,9 +2946,10 @@ static int dce_v8_0_hw_fini(struct amdgpu_device *adev) return 0; } -static int dce_v8_0_suspend(struct amdgpu_device *adev) +static int dce_v8_0_suspend(void *handle) { struct drm_connector *connector; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; drm_kms_helper_poll_disable(adev->ddev); @@ -2957,9 +2965,10 @@ static int dce_v8_0_suspend(struct amdgpu_device *adev) return 0; } -static int dce_v8_0_resume(struct amdgpu_device *adev) +static int dce_v8_0_resume(void *handle) { struct drm_connector *connector; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; amdgpu_atombios_scratch_regs_restore(adev); @@ -2989,33 +2998,34 @@ static int dce_v8_0_resume(struct amdgpu_device *adev) return 0; } -static bool dce_v8_0_is_idle(struct amdgpu_device *adev) +static bool dce_v8_0_is_idle(void *handle) { - /* XXX todo */ return true; } -static int dce_v8_0_wait_for_idle(struct amdgpu_device *adev) +static int dce_v8_0_wait_for_idle(void *handle) { - /* XXX todo */ return 0; } -static void dce_v8_0_print_status(struct amdgpu_device *adev) +static void dce_v8_0_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + dev_info(adev->dev, "DCE 8.x registers\n"); /* XXX todo */ } -static int dce_v8_0_soft_reset(struct amdgpu_device *adev) +static int dce_v8_0_soft_reset(void *handle) { u32 srbm_soft_reset = 0, tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (dce_v8_0_is_display_hung(adev)) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; if (srbm_soft_reset) { - dce_v8_0_print_status(adev); + dce_v8_0_print_status((void *)adev); tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; @@ -3031,7 +3041,7 @@ static int dce_v8_0_soft_reset(struct amdgpu_device *adev) /* Wait a little for things to settle down */ udelay(50); - dce_v8_0_print_status(adev); + dce_v8_0_print_status((void *)adev); } return 0; } @@ -3409,19 +3419,19 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, } -static int dce_v8_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int dce_v8_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } -static int dce_v8_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int dce_v8_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs dce_v8_0_ip_funcs = { +const struct amd_ip_funcs dce_v8_0_ip_funcs = { .early_init = dce_v8_0_early_init, .late_init = NULL, .sw_init = dce_v8_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h index 3a0a73b41041..77016852b252 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.h @@ -24,6 +24,6 @@ #ifndef __DCE_V8_0_H__ #define __DCE_V8_0_H__ -extern const struct amdgpu_ip_funcs dce_v8_0_ip_funcs; +extern const struct amd_ip_funcs dce_v8_0_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 5315c13a8921..0057699cb8fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4682,8 +4682,9 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } -static int gfx_v7_0_early_init(struct amdgpu_device *adev) +static int gfx_v7_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS; @@ -4694,9 +4695,10 @@ static int gfx_v7_0_early_init(struct amdgpu_device *adev) return 0; } -static int gfx_v7_0_sw_init(struct amdgpu_device *adev) +static int gfx_v7_0_sw_init(void *handle) { struct amdgpu_ring *ring; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int i, r; /* EOP Event */ @@ -4805,9 +4807,10 @@ static int gfx_v7_0_sw_init(struct amdgpu_device *adev) return r; } -static int gfx_v7_0_sw_fini(struct amdgpu_device *adev) +static int gfx_v7_0_sw_fini(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; amdgpu_bo_unref(&adev->gds.oa_gfx_bo); amdgpu_bo_unref(&adev->gds.gws_gfx_bo); @@ -4827,9 +4830,10 @@ static int gfx_v7_0_sw_fini(struct amdgpu_device *adev) return 0; } -static int gfx_v7_0_hw_init(struct amdgpu_device *adev) +static int gfx_v7_0_hw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v7_0_gpu_init(adev); @@ -4845,8 +4849,10 @@ static int gfx_v7_0_hw_init(struct amdgpu_device *adev) return r; } -static int gfx_v7_0_hw_fini(struct amdgpu_device *adev) +static int gfx_v7_0_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + gfx_v7_0_cp_enable(adev, false); gfx_v7_0_rlc_stop(adev); gfx_v7_0_fini_pg(adev); @@ -4854,28 +4860,35 @@ static int gfx_v7_0_hw_fini(struct amdgpu_device *adev) return 0; } -static int gfx_v7_0_suspend(struct amdgpu_device *adev) +static int gfx_v7_0_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return gfx_v7_0_hw_fini(adev); } -static int gfx_v7_0_resume(struct amdgpu_device *adev) +static int gfx_v7_0_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return gfx_v7_0_hw_init(adev); } -static bool gfx_v7_0_is_idle(struct amdgpu_device *adev) +static bool gfx_v7_0_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) return false; else return true; } -static int gfx_v7_0_wait_for_idle(struct amdgpu_device *adev) +static int gfx_v7_0_wait_for_idle(void *handle) { unsigned i; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ @@ -4888,9 +4901,10 @@ static int gfx_v7_0_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static void gfx_v7_0_print_status(struct amdgpu_device *adev) +static void gfx_v7_0_print_status(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dev_info(adev->dev, "GFX 7.x registers\n"); dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", @@ -5147,10 +5161,11 @@ static void gfx_v7_0_print_status(struct amdgpu_device *adev) mutex_unlock(&adev->srbm_mutex); } -static int gfx_v7_0_soft_reset(struct amdgpu_device *adev) +static int gfx_v7_0_soft_reset(void *handle) { u32 grbm_soft_reset = 0, srbm_soft_reset = 0; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* GRBM_STATUS */ tmp = RREG32(mmGRBM_STATUS); @@ -5179,7 +5194,7 @@ static int gfx_v7_0_soft_reset(struct amdgpu_device *adev) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; if (grbm_soft_reset || srbm_soft_reset) { - gfx_v7_0_print_status(adev); + gfx_v7_0_print_status((void *)adev); /* disable CG/PG */ gfx_v7_0_fini_pg(adev); gfx_v7_0_update_cg(adev, false); @@ -5222,7 +5237,7 @@ static int gfx_v7_0_soft_reset(struct amdgpu_device *adev) } /* Wait a little for things to settle down */ udelay(50); - gfx_v7_0_print_status(adev); + gfx_v7_0_print_status((void *)adev); } return 0; } @@ -5425,12 +5440,13 @@ static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, return 0; } -static int gfx_v7_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int gfx_v7_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { bool gate = false; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (state == AMDGPU_CG_STATE_GATE) + if (state == AMD_CG_STATE_GATE) gate = true; gfx_v7_0_enable_gui_idle_interrupt(adev, false); @@ -5447,12 +5463,13 @@ static int gfx_v7_0_set_clockgating_state(struct amdgpu_device *adev, return 0; } -static int gfx_v7_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int gfx_v7_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { bool gate = false; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (state == AMDGPU_PG_STATE_GATE) + if (state == AMD_PG_STATE_GATE) gate = true; if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | @@ -5471,7 +5488,7 @@ static int gfx_v7_0_set_powergating_state(struct amdgpu_device *adev, return 0; } -const struct amdgpu_ip_funcs gfx_v7_0_ip_funcs = { +const struct amd_ip_funcs gfx_v7_0_ip_funcs = { .early_init = gfx_v7_0_early_init, .late_init = NULL, .sw_init = gfx_v7_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h index 668b91a89e1e..c04bfbabfc88 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h @@ -24,7 +24,7 @@ #ifndef __GFX_V7_0_H__ #define __GFX_V7_0_H__ -extern const struct amdgpu_ip_funcs gfx_v7_0_ip_funcs; +extern const struct amd_ip_funcs gfx_v7_0_ip_funcs; /* XXX these shouldn't be exported */ void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 4597256cc6e2..a7d687da10d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -784,10 +784,11 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev) return 0; } -static int gfx_v8_0_sw_init(struct amdgpu_device *adev) +static int gfx_v8_0_sw_init(void *handle) { int i, r; struct amdgpu_ring *ring; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* EOP Event */ r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); @@ -897,9 +898,10 @@ static int gfx_v8_0_sw_init(struct amdgpu_device *adev) return 0; } -static int gfx_v8_0_sw_fini(struct amdgpu_device *adev) +static int gfx_v8_0_sw_fini(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; amdgpu_bo_unref(&adev->gds.oa_gfx_bo); amdgpu_bo_unref(&adev->gds.gws_gfx_bo); @@ -3148,9 +3150,10 @@ static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable) gfx_v8_0_cp_compute_enable(adev, enable); } -static int gfx_v8_0_hw_init(struct amdgpu_device *adev) +static int gfx_v8_0_hw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v8_0_init_golden_registers(adev); @@ -3167,8 +3170,10 @@ static int gfx_v8_0_hw_init(struct amdgpu_device *adev) return r; } -static int gfx_v8_0_hw_fini(struct amdgpu_device *adev) +static int gfx_v8_0_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + gfx_v8_0_cp_enable(adev, false); gfx_v8_0_rlc_stop(adev); gfx_v8_0_cp_compute_fini(adev); @@ -3176,28 +3181,35 @@ static int gfx_v8_0_hw_fini(struct amdgpu_device *adev) return 0; } -static int gfx_v8_0_suspend(struct amdgpu_device *adev) +static int gfx_v8_0_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return gfx_v8_0_hw_fini(adev); } -static int gfx_v8_0_resume(struct amdgpu_device *adev) +static int gfx_v8_0_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return gfx_v8_0_hw_init(adev); } -static bool gfx_v8_0_is_idle(struct amdgpu_device *adev) +static bool gfx_v8_0_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) return false; else return true; } -static int gfx_v8_0_wait_for_idle(struct amdgpu_device *adev) +static int gfx_v8_0_wait_for_idle(void *handle) { unsigned i; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ @@ -3210,9 +3222,10 @@ static int gfx_v8_0_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static void gfx_v8_0_print_status(struct amdgpu_device *adev) +static void gfx_v8_0_print_status(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dev_info(adev->dev, "GFX 8.x registers\n"); dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", @@ -3398,10 +3411,11 @@ static void gfx_v8_0_print_status(struct amdgpu_device *adev) mutex_unlock(&adev->srbm_mutex); } -static int gfx_v8_0_soft_reset(struct amdgpu_device *adev) +static int gfx_v8_0_soft_reset(void *handle) { u32 grbm_soft_reset = 0, srbm_soft_reset = 0; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* GRBM_STATUS */ tmp = RREG32(mmGRBM_STATUS); @@ -3437,7 +3451,7 @@ static int gfx_v8_0_soft_reset(struct amdgpu_device *adev) SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); if (grbm_soft_reset || srbm_soft_reset) { - gfx_v8_0_print_status(adev); + gfx_v8_0_print_status((void *)adev); /* stop the rlc */ gfx_v8_0_rlc_stop(adev); @@ -3476,7 +3490,7 @@ static int gfx_v8_0_soft_reset(struct amdgpu_device *adev) } /* Wait a little for things to settle down */ udelay(50); - gfx_v8_0_print_status(adev); + gfx_v8_0_print_status((void *)adev); } return 0; } @@ -3549,8 +3563,9 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring, amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } -static int gfx_v8_0_early_init(struct amdgpu_device *adev) +static int gfx_v8_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS; @@ -3561,14 +3576,14 @@ static int gfx_v8_0_early_init(struct amdgpu_device *adev) return 0; } -static int gfx_v8_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int gfx_v8_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -static int gfx_v8_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int gfx_v8_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } @@ -4116,7 +4131,7 @@ static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev, return 0; } -const struct amdgpu_ip_funcs gfx_v8_0_ip_funcs = { +const struct amd_ip_funcs gfx_v8_0_ip_funcs = { .early_init = gfx_v8_0_early_init, .late_init = NULL, .sw_init = gfx_v8_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h index be8a5f8e176e..021e05193cb9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h @@ -24,7 +24,7 @@ #ifndef __GFX_V8_0_H__ #define __GFX_V8_0_H__ -extern const struct amdgpu_ip_funcs gfx_v8_0_ip_funcs; +extern const struct amd_ip_funcs gfx_v8_0_ip_funcs; uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev); void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index ab096723a588..01cd6b207d26 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -812,8 +812,10 @@ static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, WREG32(mmHDP_MEM_POWER_LS, data); } -static int gmc_v7_0_early_init(struct amdgpu_device *adev) +static int gmc_v7_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + gmc_v7_0_set_gart_funcs(adev); gmc_v7_0_set_irq_funcs(adev); @@ -832,10 +834,11 @@ static int gmc_v7_0_early_init(struct amdgpu_device *adev) return 0; } -static int gmc_v7_0_sw_init(struct amdgpu_device *adev) +static int gmc_v7_0_sw_init(void *handle) { int r; int dma_bits; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_gem_init(adev); if (r) @@ -911,9 +914,10 @@ static int gmc_v7_0_sw_init(struct amdgpu_device *adev) return r; } -static int gmc_v7_0_sw_fini(struct amdgpu_device *adev) +static int gmc_v7_0_sw_fini(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev->vm_manager.enabled) { for (i = 0; i < AMDGPU_NUM_VM; ++i) @@ -928,9 +932,10 @@ static int gmc_v7_0_sw_fini(struct amdgpu_device *adev) return 0; } -static int gmc_v7_0_hw_init(struct amdgpu_device *adev) +static int gmc_v7_0_hw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; gmc_v7_0_mc_program(adev); @@ -949,16 +954,19 @@ static int gmc_v7_0_hw_init(struct amdgpu_device *adev) return r; } -static int gmc_v7_0_hw_fini(struct amdgpu_device *adev) +static int gmc_v7_0_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + gmc_v7_0_gart_disable(adev); return 0; } -static int gmc_v7_0_suspend(struct amdgpu_device *adev) +static int gmc_v7_0_suspend(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev->vm_manager.enabled) { for (i = 0; i < AMDGPU_NUM_VM; ++i) @@ -971,9 +979,10 @@ static int gmc_v7_0_suspend(struct amdgpu_device *adev) return 0; } -static int gmc_v7_0_resume(struct amdgpu_device *adev) +static int gmc_v7_0_resume(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = gmc_v7_0_hw_init(adev); if (r) @@ -991,8 +1000,9 @@ static int gmc_v7_0_resume(struct amdgpu_device *adev) return r; } -static bool gmc_v7_0_is_idle(struct amdgpu_device *adev) +static bool gmc_v7_0_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | @@ -1002,10 +1012,11 @@ static bool gmc_v7_0_is_idle(struct amdgpu_device *adev) return true; } -static int gmc_v7_0_wait_for_idle(struct amdgpu_device *adev) +static int gmc_v7_0_wait_for_idle(void *handle) { unsigned i; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ @@ -1022,9 +1033,10 @@ static int gmc_v7_0_wait_for_idle(struct amdgpu_device *adev) } -static void gmc_v7_0_print_status(struct amdgpu_device *adev) +static void gmc_v7_0_print_status(void *handle) { int i, j; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dev_info(adev->dev, "GMC 8.x registers\n"); dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", @@ -1129,8 +1141,9 @@ static void gmc_v7_0_print_status(struct amdgpu_device *adev) RREG32(mmBIF_FB_EN)); } -static int gmc_v7_0_soft_reset(struct amdgpu_device *adev) +static int gmc_v7_0_soft_reset(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_mode_mc_save save; u32 srbm_soft_reset = 0; u32 tmp = RREG32(mmSRBM_STATUS); @@ -1147,7 +1160,7 @@ static int gmc_v7_0_soft_reset(struct amdgpu_device *adev) } if (srbm_soft_reset) { - gmc_v7_0_print_status(adev); + gmc_v7_0_print_status((void *)adev); gmc_v7_0_mc_stop(adev, &save); if (gmc_v7_0_wait_for_idle(adev)) { @@ -1173,7 +1186,7 @@ static int gmc_v7_0_soft_reset(struct amdgpu_device *adev) gmc_v7_0_mc_resume(adev, &save); udelay(50); - gmc_v7_0_print_status(adev); + gmc_v7_0_print_status((void *)adev); } return 0; @@ -1242,12 +1255,13 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, return 0; } -static int gmc_v7_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int gmc_v7_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { bool gate = false; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (state == AMDGPU_CG_STATE_GATE) + if (state == AMD_CG_STATE_GATE) gate = true; if (!(adev->flags & AMDGPU_IS_APU)) { @@ -1261,13 +1275,13 @@ static int gmc_v7_0_set_clockgating_state(struct amdgpu_device *adev, return 0; } -static int gmc_v7_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int gmc_v7_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs gmc_v7_0_ip_funcs = { +const struct amd_ip_funcs gmc_v7_0_ip_funcs = { .early_init = gmc_v7_0_early_init, .late_init = NULL, .sw_init = gmc_v7_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h index ab1a2fa1afcd..36fcbbc46ada 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.h @@ -24,7 +24,7 @@ #ifndef __GMC_V7_0_H__ #define __GMC_V7_0_H__ -extern const struct amdgpu_ip_funcs gmc_v7_0_ip_funcs; +extern const struct amd_ip_funcs gmc_v7_0_ip_funcs; /* XXX these shouldn't be exported */ void gmc_v7_0_mc_stop(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index f816165acd70..675483a612c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -786,8 +786,10 @@ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, "write" : "read", block, mc_client, mc_id); } -static int gmc_v8_0_early_init(struct amdgpu_device *adev) +static int gmc_v8_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + gmc_v8_0_set_gart_funcs(adev); gmc_v8_0_set_irq_funcs(adev); @@ -806,10 +808,11 @@ static int gmc_v8_0_early_init(struct amdgpu_device *adev) return 0; } -static int gmc_v8_0_sw_init(struct amdgpu_device *adev) +static int gmc_v8_0_sw_init(void *handle) { int r; int dma_bits; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_gem_init(adev); if (r) @@ -885,9 +888,10 @@ static int gmc_v8_0_sw_init(struct amdgpu_device *adev) return r; } -static int gmc_v8_0_sw_fini(struct amdgpu_device *adev) +static int gmc_v8_0_sw_fini(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev->vm_manager.enabled) { for (i = 0; i < AMDGPU_NUM_VM; ++i) @@ -902,9 +906,10 @@ static int gmc_v8_0_sw_fini(struct amdgpu_device *adev) return 0; } -static int gmc_v8_0_hw_init(struct amdgpu_device *adev) +static int gmc_v8_0_hw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; gmc_v8_0_init_golden_registers(adev); @@ -925,16 +930,19 @@ static int gmc_v8_0_hw_init(struct amdgpu_device *adev) return r; } -static int gmc_v8_0_hw_fini(struct amdgpu_device *adev) +static int gmc_v8_0_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + gmc_v8_0_gart_disable(adev); return 0; } -static int gmc_v8_0_suspend(struct amdgpu_device *adev) +static int gmc_v8_0_suspend(void *handle) { int i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev->vm_manager.enabled) { for (i = 0; i < AMDGPU_NUM_VM; ++i) @@ -947,9 +955,10 @@ static int gmc_v8_0_suspend(struct amdgpu_device *adev) return 0; } -static int gmc_v8_0_resume(struct amdgpu_device *adev) +static int gmc_v8_0_resume(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = gmc_v8_0_hw_init(adev); if (r) @@ -967,8 +976,9 @@ static int gmc_v8_0_resume(struct amdgpu_device *adev) return r; } -static bool gmc_v8_0_is_idle(struct amdgpu_device *adev) +static bool gmc_v8_0_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | @@ -978,10 +988,11 @@ static bool gmc_v8_0_is_idle(struct amdgpu_device *adev) return true; } -static int gmc_v8_0_wait_for_idle(struct amdgpu_device *adev) +static int gmc_v8_0_wait_for_idle(void *handle) { unsigned i; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ @@ -999,9 +1010,10 @@ static int gmc_v8_0_wait_for_idle(struct amdgpu_device *adev) } -static void gmc_v8_0_print_status(struct amdgpu_device *adev) +static void gmc_v8_0_print_status(void *handle) { int i, j; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dev_info(adev->dev, "GMC 8.x registers\n"); dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", @@ -1103,10 +1115,11 @@ static void gmc_v8_0_print_status(struct amdgpu_device *adev) RREG32(mmBIF_FB_EN)); } -static int gmc_v8_0_soft_reset(struct amdgpu_device *adev) +static int gmc_v8_0_soft_reset(void *handle) { struct amdgpu_mode_mc_save save; u32 srbm_soft_reset = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & SRBM_STATUS__VMC_BUSY_MASK) @@ -1121,7 +1134,7 @@ static int gmc_v8_0_soft_reset(struct amdgpu_device *adev) } if (srbm_soft_reset) { - gmc_v8_0_print_status(adev); + gmc_v8_0_print_status((void *)adev); gmc_v8_0_mc_stop(adev, &save); if (gmc_v8_0_wait_for_idle(adev)) { @@ -1147,7 +1160,7 @@ static int gmc_v8_0_soft_reset(struct amdgpu_device *adev) gmc_v8_0_mc_resume(adev, &save); udelay(50); - gmc_v8_0_print_status(adev); + gmc_v8_0_print_status((void *)adev); } return 0; @@ -1217,21 +1230,19 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, return 0; } -static int gmc_v8_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int gmc_v8_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { - /* XXX handled via the smc on VI */ - return 0; } -static int gmc_v8_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int gmc_v8_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs gmc_v8_0_ip_funcs = { +const struct amd_ip_funcs gmc_v8_0_ip_funcs = { .early_init = gmc_v8_0_early_init, .late_init = NULL, .sw_init = gmc_v8_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h index 2dd7f809d4e1..973436086b38 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.h @@ -24,7 +24,7 @@ #ifndef __GMC_V8_0_H__ #define __GMC_V8_0_H__ -extern const struct amdgpu_ip_funcs gmc_v8_0_ip_funcs; +extern const struct amd_ip_funcs gmc_v8_0_ip_funcs; /* XXX these shouldn't be exported */ void gmc_v8_0_mc_stop(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c index 0688b88cb170..4b773f29167a 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c @@ -30,8 +30,10 @@ MODULE_FIRMWARE("amdgpu/topaz_smc.bin"); static void iceland_dpm_set_funcs(struct amdgpu_device *adev); -static int iceland_dpm_early_init(struct amdgpu_device *adev) +static int iceland_dpm_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + iceland_dpm_set_funcs(adev); return 0; @@ -56,9 +58,10 @@ out: return err; } -static int iceland_dpm_sw_init(struct amdgpu_device *adev) +static int iceland_dpm_sw_init(void *handle) { int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; ret = iceland_dpm_init_microcode(adev); if (ret) @@ -67,14 +70,15 @@ static int iceland_dpm_sw_init(struct amdgpu_device *adev) return 0; } -static int iceland_dpm_sw_fini(struct amdgpu_device *adev) +static int iceland_dpm_sw_fini(void *handle) { return 0; } -static int iceland_dpm_hw_init(struct amdgpu_device *adev) +static int iceland_dpm_hw_init(void *handle) { int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; mutex_lock(&adev->pm.mutex); @@ -99,41 +103,47 @@ fail: return -EINVAL; } -static int iceland_dpm_hw_fini(struct amdgpu_device *adev) +static int iceland_dpm_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + mutex_lock(&adev->pm.mutex); iceland_smu_fini(adev); mutex_unlock(&adev->pm.mutex); return 0; } -static int iceland_dpm_suspend(struct amdgpu_device *adev) +static int iceland_dpm_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + iceland_dpm_hw_fini(adev); return 0; } -static int iceland_dpm_resume(struct amdgpu_device *adev) +static int iceland_dpm_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + iceland_dpm_hw_init(adev); return 0; } -static int iceland_dpm_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int iceland_dpm_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } -static int iceland_dpm_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int iceland_dpm_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs iceland_dpm_ip_funcs = { +const struct amd_ip_funcs iceland_dpm_ip_funcs = { .early_init = iceland_dpm_early_init, .late_init = NULL, .sw_init = iceland_dpm_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 2de8adfac471..779532d350ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -250,15 +250,18 @@ static void iceland_ih_set_rptr(struct amdgpu_device *adev) WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); } -static int iceland_ih_early_init(struct amdgpu_device *adev) +static int iceland_ih_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + iceland_ih_set_interrupt_funcs(adev); return 0; } -static int iceland_ih_sw_init(struct amdgpu_device *adev) +static int iceland_ih_sw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_ih_ring_init(adev, 64 * 1024, false); if (r) @@ -269,17 +272,20 @@ static int iceland_ih_sw_init(struct amdgpu_device *adev) return r; } -static int iceland_ih_sw_fini(struct amdgpu_device *adev) +static int iceland_ih_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_irq_fini(adev); amdgpu_ih_ring_fini(adev); return 0; } -static int iceland_ih_hw_init(struct amdgpu_device *adev) +static int iceland_ih_hw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = iceland_ih_irq_init(adev); if (r) @@ -288,25 +294,32 @@ static int iceland_ih_hw_init(struct amdgpu_device *adev) return 0; } -static int iceland_ih_hw_fini(struct amdgpu_device *adev) +static int iceland_ih_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + iceland_ih_irq_disable(adev); return 0; } -static int iceland_ih_suspend(struct amdgpu_device *adev) +static int iceland_ih_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return iceland_ih_hw_fini(adev); } -static int iceland_ih_resume(struct amdgpu_device *adev) +static int iceland_ih_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return iceland_ih_hw_init(adev); } -static bool iceland_ih_is_idle(struct amdgpu_device *adev) +static bool iceland_ih_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS); if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) @@ -315,10 +328,11 @@ static bool iceland_ih_is_idle(struct amdgpu_device *adev) return true; } -static int iceland_ih_wait_for_idle(struct amdgpu_device *adev) +static int iceland_ih_wait_for_idle(void *handle) { unsigned i; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ @@ -330,8 +344,10 @@ static int iceland_ih_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static void iceland_ih_print_status(struct amdgpu_device *adev) +static void iceland_ih_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + dev_info(adev->dev, "ICELAND IH registers\n"); dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", RREG32(mmSRBM_STATUS)); @@ -357,9 +373,10 @@ static void iceland_ih_print_status(struct amdgpu_device *adev) RREG32(mmIH_RB_WPTR)); } -static int iceland_ih_soft_reset(struct amdgpu_device *adev) +static int iceland_ih_soft_reset(void *handle) { u32 srbm_soft_reset = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & SRBM_STATUS__IH_BUSY_MASK) @@ -367,7 +384,7 @@ static int iceland_ih_soft_reset(struct amdgpu_device *adev) SOFT_RESET_IH, 1); if (srbm_soft_reset) { - iceland_ih_print_status(adev); + iceland_ih_print_status((void *)adev); tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; @@ -384,27 +401,25 @@ static int iceland_ih_soft_reset(struct amdgpu_device *adev) /* Wait a little for things to settle down */ udelay(50); - iceland_ih_print_status(adev); + iceland_ih_print_status((void *)adev); } return 0; } -static int iceland_ih_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int iceland_ih_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { - // TODO return 0; } -static int iceland_ih_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int iceland_ih_set_powergating_state(void *handle, + enum amd_powergating_state state) { - // TODO return 0; } -const struct amdgpu_ip_funcs iceland_ih_ip_funcs = { +const struct amd_ip_funcs iceland_ih_ip_funcs = { .early_init = iceland_ih_early_init, .late_init = NULL, .sw_init = iceland_ih_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h index d001895eb93b..57558cddfbcb 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.h @@ -24,6 +24,6 @@ #ifndef __ICELAND_IH_H__ #define __ICELAND_IH_H__ -extern const struct amdgpu_ip_funcs iceland_ih_ip_funcs; +extern const struct amd_ip_funcs iceland_ih_ip_funcs; #endif /* __ICELAND_IH_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c index cd902419e6a1..94ec04a9c4d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c @@ -1552,8 +1552,8 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev, if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) { kv_dpm_powergate_vce(adev, false); /* turn the clocks on when encoding */ - ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, - AMDGPU_CG_STATE_UNGATE); + ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_CG_STATE_UNGATE); if (ret) return ret; if (pi->caps_stable_p_state) @@ -1579,8 +1579,8 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev, } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) { kv_enable_vce_dpm(adev, false); /* turn the clocks off when not encoding */ - ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, - AMDGPU_CG_STATE_GATE); + ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_CG_STATE_GATE); if (ret) return ret; kv_dpm_powergate_vce(adev, true); @@ -1697,11 +1697,11 @@ static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) if (gate) { if (pi->caps_uvd_pg) { /* disable clockgating so we can properly shut down the block */ - ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, - AMDGPU_CG_STATE_UNGATE); + ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_CG_STATE_UNGATE); /* shutdown the UVD block */ - ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, - AMDGPU_PG_STATE_GATE); + ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_GATE); /* XXX: check for errors */ } kv_update_uvd_dpm(adev, gate); @@ -1713,11 +1713,11 @@ static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) /* power on the UVD block */ amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); /* re-init the UVD block */ - ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, - AMDGPU_PG_STATE_UNGATE); + ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_PG_STATE_UNGATE); /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */ - ret = amdgpu_set_clockgating_state(adev, AMDGPU_IP_BLOCK_TYPE_UVD, - AMDGPU_CG_STATE_GATE); + ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, + AMD_CG_STATE_GATE); /* XXX: check for errors */ } kv_update_uvd_dpm(adev, gate); @@ -1737,8 +1737,8 @@ static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) if (gate) { if (pi->caps_vce_pg) { /* shutdown the VCE block */ - ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, - AMDGPU_PG_STATE_GATE); + ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_PG_STATE_GATE); /* XXX: check for errors */ /* power off the VCE block */ amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF); @@ -1748,8 +1748,8 @@ static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) /* power on the VCE block */ amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); /* re-init the VCE block */ - ret = amdgpu_set_powergating_state(adev, AMDGPU_IP_BLOCK_TYPE_VCE, - AMDGPU_PG_STATE_UNGATE); + ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_PG_STATE_UNGATE); /* XXX: check for errors */ } } @@ -2981,20 +2981,21 @@ static int kv_dpm_get_temp(struct amdgpu_device *adev) return actual_temp; } -static int kv_dpm_early_init(struct amdgpu_device *adev) +static int kv_dpm_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + kv_dpm_set_dpm_funcs(adev); kv_dpm_set_irq_funcs(adev); return 0; } -static int kv_dpm_late_init(struct amdgpu_device *adev) +static int kv_dpm_late_init(void *handle) { - if (!amdgpu_dpm) - return 0; - /* powerdown unused blocks for now */ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + kv_dpm_powergate_acp(adev, true); kv_dpm_powergate_samu(adev, true); kv_dpm_powergate_vce(adev, true); @@ -3003,9 +3004,10 @@ static int kv_dpm_late_init(struct amdgpu_device *adev) return 0; } -static int kv_dpm_sw_init(struct amdgpu_device *adev) +static int kv_dpm_sw_init(void *handle) { int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); if (ret) @@ -3051,8 +3053,10 @@ dpm_failed: return ret; } -static int kv_dpm_sw_fini(struct amdgpu_device *adev) +static int kv_dpm_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + mutex_lock(&adev->pm.mutex); amdgpu_pm_sysfs_fini(adev); kv_dpm_fini(adev); @@ -3061,12 +3065,10 @@ static int kv_dpm_sw_fini(struct amdgpu_device *adev) return 0; } -static int kv_dpm_hw_init(struct amdgpu_device *adev) +static int kv_dpm_hw_init(void *handle) { int ret; - - if (!amdgpu_dpm) - return 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; mutex_lock(&adev->pm.mutex); kv_dpm_setup_asic(adev); @@ -3080,8 +3082,10 @@ static int kv_dpm_hw_init(struct amdgpu_device *adev) return ret; } -static int kv_dpm_hw_fini(struct amdgpu_device *adev) +static int kv_dpm_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (adev->pm.dpm_enabled) { mutex_lock(&adev->pm.mutex); kv_dpm_disable(adev); @@ -3091,8 +3095,10 @@ static int kv_dpm_hw_fini(struct amdgpu_device *adev) return 0; } -static int kv_dpm_suspend(struct amdgpu_device *adev) +static int kv_dpm_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + if (adev->pm.dpm_enabled) { mutex_lock(&adev->pm.mutex); /* disable dpm */ @@ -3104,9 +3110,10 @@ static int kv_dpm_suspend(struct amdgpu_device *adev) return 0; } -static int kv_dpm_resume(struct amdgpu_device *adev) +static int kv_dpm_resume(void *handle) { int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev->pm.dpm_enabled) { /* asic init will reset to the boot state */ @@ -3124,20 +3131,20 @@ static int kv_dpm_resume(struct amdgpu_device *adev) return 0; } -static bool kv_dpm_is_idle(struct amdgpu_device *adev) +static bool kv_dpm_is_idle(void *handle) { - /* XXX */ return true; } -static int kv_dpm_wait_for_idle(struct amdgpu_device *adev) +static int kv_dpm_wait_for_idle(void *handle) { - /* XXX */ return 0; } -static void kv_dpm_print_status(struct amdgpu_device *adev) +static void kv_dpm_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + dev_info(adev->dev, "KV/KB DPM registers\n"); dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n", RREG32_DIDT(ixDIDT_SQ_CTRL0)); @@ -3191,7 +3198,7 @@ static void kv_dpm_print_status(struct amdgpu_device *adev) RREG32(mmSMC_IND_ACCESS_CNTL)); } -static int kv_dpm_soft_reset(struct amdgpu_device *adev) +static int kv_dpm_soft_reset(void *handle) { return 0; } @@ -3274,19 +3281,19 @@ static int kv_dpm_process_interrupt(struct amdgpu_device *adev, return 0; } -static int kv_dpm_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int kv_dpm_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } -static int kv_dpm_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int kv_dpm_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs kv_dpm_ip_funcs = { +const struct amd_ip_funcs kv_dpm_ip_funcs = { .early_init = kv_dpm_early_init, .late_init = kv_dpm_late_init, .sw_init = kv_dpm_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 99b8b326e999..64de8f60e3a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -955,8 +955,10 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ } -static int sdma_v2_4_early_init(struct amdgpu_device *adev) +static int sdma_v2_4_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + sdma_v2_4_set_ring_funcs(adev); sdma_v2_4_set_buffer_funcs(adev); sdma_v2_4_set_vm_pte_funcs(adev); @@ -965,10 +967,11 @@ static int sdma_v2_4_early_init(struct amdgpu_device *adev) return 0; } -static int sdma_v2_4_sw_init(struct amdgpu_device *adev) +static int sdma_v2_4_sw_init(void *handle) { struct amdgpu_ring *ring; int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* SDMA trap event */ r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); @@ -1020,17 +1023,20 @@ static int sdma_v2_4_sw_init(struct amdgpu_device *adev) return r; } -static int sdma_v2_4_sw_fini(struct amdgpu_device *adev) +static int sdma_v2_4_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_ring_fini(&adev->sdma[0].ring); amdgpu_ring_fini(&adev->sdma[1].ring); return 0; } -static int sdma_v2_4_hw_init(struct amdgpu_device *adev) +static int sdma_v2_4_hw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; sdma_v2_4_init_golden_registers(adev); @@ -1041,27 +1047,32 @@ static int sdma_v2_4_hw_init(struct amdgpu_device *adev) return r; } -static int sdma_v2_4_hw_fini(struct amdgpu_device *adev) +static int sdma_v2_4_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + sdma_v2_4_enable(adev, false); return 0; } -static int sdma_v2_4_suspend(struct amdgpu_device *adev) +static int sdma_v2_4_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; return sdma_v2_4_hw_fini(adev); } -static int sdma_v2_4_resume(struct amdgpu_device *adev) +static int sdma_v2_4_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; return sdma_v2_4_hw_init(adev); } -static bool sdma_v2_4_is_idle(struct amdgpu_device *adev) +static bool sdma_v2_4_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS2); if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | @@ -1071,10 +1082,11 @@ static bool sdma_v2_4_is_idle(struct amdgpu_device *adev) return true; } -static int sdma_v2_4_wait_for_idle(struct amdgpu_device *adev) +static int sdma_v2_4_wait_for_idle(void *handle) { unsigned i; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | @@ -1087,9 +1099,10 @@ static int sdma_v2_4_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static void sdma_v2_4_print_status(struct amdgpu_device *adev) +static void sdma_v2_4_print_status(void *handle) { int i, j; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dev_info(adev->dev, "VI SDMA registers\n"); dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", @@ -1133,9 +1146,10 @@ static void sdma_v2_4_print_status(struct amdgpu_device *adev) } } -static int sdma_v2_4_soft_reset(struct amdgpu_device *adev) +static int sdma_v2_4_soft_reset(void *handle) { u32 srbm_soft_reset = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS2); if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { @@ -1154,7 +1168,7 @@ static int sdma_v2_4_soft_reset(struct amdgpu_device *adev) } if (srbm_soft_reset) { - sdma_v2_4_print_status(adev); + sdma_v2_4_print_status((void *)adev); tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; @@ -1171,7 +1185,7 @@ static int sdma_v2_4_soft_reset(struct amdgpu_device *adev) /* Wait a little for things to settle down */ udelay(50); - sdma_v2_4_print_status(adev); + sdma_v2_4_print_status((void *)adev); } return 0; @@ -1272,21 +1286,20 @@ static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev, return 0; } -static int sdma_v2_4_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int sdma_v2_4_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { /* XXX handled via the smc on VI */ - return 0; } -static int sdma_v2_4_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int sdma_v2_4_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs sdma_v2_4_ip_funcs = { +const struct amd_ip_funcs sdma_v2_4_ip_funcs = { .early_init = sdma_v2_4_early_init, .late_init = NULL, .sw_init = sdma_v2_4_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h index 6cdf8941c577..07349f5ee10f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.h @@ -24,6 +24,6 @@ #ifndef __SDMA_V2_4_H__ #define __SDMA_V2_4_H__ -extern const struct amdgpu_ip_funcs sdma_v2_4_ip_funcs; +extern const struct amd_ip_funcs sdma_v2_4_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 86a5278b65f6..bf3cefc447ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1018,8 +1018,10 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ } -static int sdma_v3_0_early_init(struct amdgpu_device *adev) +static int sdma_v3_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + sdma_v3_0_set_ring_funcs(adev); sdma_v3_0_set_buffer_funcs(adev); sdma_v3_0_set_vm_pte_funcs(adev); @@ -1028,10 +1030,11 @@ static int sdma_v3_0_early_init(struct amdgpu_device *adev) return 0; } -static int sdma_v3_0_sw_init(struct amdgpu_device *adev) +static int sdma_v3_0_sw_init(void *handle) { struct amdgpu_ring *ring; int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* SDMA trap event */ r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); @@ -1085,17 +1088,20 @@ static int sdma_v3_0_sw_init(struct amdgpu_device *adev) return r; } -static int sdma_v3_0_sw_fini(struct amdgpu_device *adev) +static int sdma_v3_0_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_ring_fini(&adev->sdma[0].ring); amdgpu_ring_fini(&adev->sdma[1].ring); return 0; } -static int sdma_v3_0_hw_init(struct amdgpu_device *adev) +static int sdma_v3_0_hw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; sdma_v3_0_init_golden_registers(adev); @@ -1106,27 +1112,32 @@ static int sdma_v3_0_hw_init(struct amdgpu_device *adev) return r; } -static int sdma_v3_0_hw_fini(struct amdgpu_device *adev) +static int sdma_v3_0_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + sdma_v3_0_enable(adev, false); return 0; } -static int sdma_v3_0_suspend(struct amdgpu_device *adev) +static int sdma_v3_0_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; return sdma_v3_0_hw_fini(adev); } -static int sdma_v3_0_resume(struct amdgpu_device *adev) +static int sdma_v3_0_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; return sdma_v3_0_hw_init(adev); } -static bool sdma_v3_0_is_idle(struct amdgpu_device *adev) +static bool sdma_v3_0_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS2); if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | @@ -1136,10 +1147,11 @@ static bool sdma_v3_0_is_idle(struct amdgpu_device *adev) return true; } -static int sdma_v3_0_wait_for_idle(struct amdgpu_device *adev) +static int sdma_v3_0_wait_for_idle(void *handle) { unsigned i; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | @@ -1152,9 +1164,10 @@ static int sdma_v3_0_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static void sdma_v3_0_print_status(struct amdgpu_device *adev) +static void sdma_v3_0_print_status(void *handle) { int i, j; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dev_info(adev->dev, "VI SDMA registers\n"); dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", @@ -1200,9 +1213,10 @@ static void sdma_v3_0_print_status(struct amdgpu_device *adev) } } -static int sdma_v3_0_soft_reset(struct amdgpu_device *adev) +static int sdma_v3_0_soft_reset(void *handle) { u32 srbm_soft_reset = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS2); if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { @@ -1221,7 +1235,7 @@ static int sdma_v3_0_soft_reset(struct amdgpu_device *adev) } if (srbm_soft_reset) { - sdma_v3_0_print_status(adev); + sdma_v3_0_print_status((void *)adev); tmp = RREG32(mmSRBM_SOFT_RESET); tmp |= srbm_soft_reset; @@ -1238,7 +1252,7 @@ static int sdma_v3_0_soft_reset(struct amdgpu_device *adev) /* Wait a little for things to settle down */ udelay(50); - sdma_v3_0_print_status(adev); + sdma_v3_0_print_status((void *)adev); } return 0; @@ -1339,21 +1353,19 @@ static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, return 0; } -static int sdma_v3_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int sdma_v3_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { - /* XXX handled via the smc on VI */ - return 0; } -static int sdma_v3_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int sdma_v3_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs sdma_v3_0_ip_funcs = { +const struct amd_ip_funcs sdma_v3_0_ip_funcs = { .early_init = sdma_v3_0_early_init, .late_init = NULL, .sw_init = sdma_v3_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h index 85bf2ac59252..0cb9698a3054 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.h @@ -24,6 +24,6 @@ #ifndef __SDMA_V3_0_H__ #define __SDMA_V3_0_H__ -extern const struct amdgpu_ip_funcs sdma_v3_0_ip_funcs; +extern const struct amd_ip_funcs sdma_v3_0_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c index cf97d496a7a4..2d5b1bd52afa 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c @@ -30,8 +30,10 @@ MODULE_FIRMWARE("amdgpu/tonga_smc.bin"); static void tonga_dpm_set_funcs(struct amdgpu_device *adev); -static int tonga_dpm_early_init(struct amdgpu_device *adev) +static int tonga_dpm_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + tonga_dpm_set_funcs(adev); return 0; @@ -41,7 +43,6 @@ static int tonga_dpm_init_microcode(struct amdgpu_device *adev) { char fw_name[30] = "amdgpu/tonga_smc.bin"; int err; - err = request_firmware(&adev->pm.fw, fw_name, adev->dev); if (err) goto out; @@ -56,9 +57,10 @@ out: return err; } -static int tonga_dpm_sw_init(struct amdgpu_device *adev) +static int tonga_dpm_sw_init(void *handle) { int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; ret = tonga_dpm_init_microcode(adev); if (ret) @@ -67,14 +69,15 @@ static int tonga_dpm_sw_init(struct amdgpu_device *adev) return 0; } -static int tonga_dpm_sw_fini(struct amdgpu_device *adev) +static int tonga_dpm_sw_fini(void *handle) { return 0; } -static int tonga_dpm_hw_init(struct amdgpu_device *adev) +static int tonga_dpm_hw_init(void *handle) { int ret; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; mutex_lock(&adev->pm.mutex); @@ -99,41 +102,47 @@ fail: return -EINVAL; } -static int tonga_dpm_hw_fini(struct amdgpu_device *adev) +static int tonga_dpm_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + mutex_lock(&adev->pm.mutex); tonga_smu_fini(adev); mutex_unlock(&adev->pm.mutex); return 0; } -static int tonga_dpm_suspend(struct amdgpu_device *adev) +static int tonga_dpm_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + tonga_dpm_hw_fini(adev); return 0; } -static int tonga_dpm_resume(struct amdgpu_device *adev) +static int tonga_dpm_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + tonga_dpm_hw_init(adev); return 0; } -static int tonga_dpm_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int tonga_dpm_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } -static int tonga_dpm_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int tonga_dpm_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs tonga_dpm_ip_funcs = { +const struct amd_ip_funcs tonga_dpm_ip_funcs = { .early_init = tonga_dpm_early_init, .late_init = NULL, .sw_init = tonga_dpm_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index cff1b8bce6a4..743c372837aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -270,15 +270,18 @@ static void tonga_ih_set_rptr(struct amdgpu_device *adev) } } -static int tonga_ih_early_init(struct amdgpu_device *adev) +static int tonga_ih_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + tonga_ih_set_interrupt_funcs(adev); return 0; } -static int tonga_ih_sw_init(struct amdgpu_device *adev) +static int tonga_ih_sw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_ih_ring_init(adev, 4 * 1024, true); if (r) @@ -292,17 +295,20 @@ static int tonga_ih_sw_init(struct amdgpu_device *adev) return r; } -static int tonga_ih_sw_fini(struct amdgpu_device *adev) +static int tonga_ih_sw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_irq_fini(adev); amdgpu_ih_ring_fini(adev); return 0; } -static int tonga_ih_hw_init(struct amdgpu_device *adev) +static int tonga_ih_hw_init(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = tonga_ih_irq_init(adev); if (r) @@ -311,25 +317,32 @@ static int tonga_ih_hw_init(struct amdgpu_device *adev) return 0; } -static int tonga_ih_hw_fini(struct amdgpu_device *adev) +static int tonga_ih_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + tonga_ih_irq_disable(adev); return 0; } -static int tonga_ih_suspend(struct amdgpu_device *adev) +static int tonga_ih_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return tonga_ih_hw_fini(adev); } -static int tonga_ih_resume(struct amdgpu_device *adev) +static int tonga_ih_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return tonga_ih_hw_init(adev); } -static bool tonga_ih_is_idle(struct amdgpu_device *adev) +static bool tonga_ih_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS); if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) @@ -338,10 +351,11 @@ static bool tonga_ih_is_idle(struct amdgpu_device *adev) return true; } -static int tonga_ih_wait_for_idle(struct amdgpu_device *adev) +static int tonga_ih_wait_for_idle(void *handle) { unsigned i; u32 tmp; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ @@ -353,8 +367,10 @@ static int tonga_ih_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static void tonga_ih_print_status(struct amdgpu_device *adev) +static void tonga_ih_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + dev_info(adev->dev, "TONGA IH registers\n"); dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", RREG32(mmSRBM_STATUS)); @@ -380,9 +396,10 @@ static void tonga_ih_print_status(struct amdgpu_device *adev) RREG32(mmIH_RB_WPTR)); } -static int tonga_ih_soft_reset(struct amdgpu_device *adev) +static int tonga_ih_soft_reset(void *handle) { u32 srbm_soft_reset = 0; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & SRBM_STATUS__IH_BUSY_MASK) @@ -413,21 +430,19 @@ static int tonga_ih_soft_reset(struct amdgpu_device *adev) return 0; } -static int tonga_ih_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int tonga_ih_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { - // TODO return 0; } -static int tonga_ih_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int tonga_ih_set_powergating_state(void *handle, + enum amd_powergating_state state) { - // TODO return 0; } -const struct amdgpu_ip_funcs tonga_ih_ip_funcs = { +const struct amd_ip_funcs tonga_ih_ip_funcs = { .early_init = tonga_ih_early_init, .late_init = NULL, .sw_init = tonga_ih_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h index 7c9bae87124e..7392d70fa4a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.h @@ -24,6 +24,6 @@ #ifndef __TONGA_IH_H__ #define __TONGA_IH_H__ -extern const struct amdgpu_ip_funcs tonga_ih_ip_funcs; +extern const struct amd_ip_funcs tonga_ih_ip_funcs; #endif /* __CZ_IH_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 6e4cb604f928..292932a73c81 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -83,17 +83,20 @@ static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); } -static int uvd_v4_2_early_init(struct amdgpu_device *adev) +static int uvd_v4_2_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + uvd_v4_2_set_ring_funcs(adev); uvd_v4_2_set_irq_funcs(adev); return 0; } -static int uvd_v4_2_sw_init(struct amdgpu_device *adev) +static int uvd_v4_2_sw_init(void *handle) { struct amdgpu_ring *ring; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; /* UVD TRAP */ @@ -117,9 +120,10 @@ static int uvd_v4_2_sw_init(struct amdgpu_device *adev) return r; } -static int uvd_v4_2_sw_fini(struct amdgpu_device *adev) +static int uvd_v4_2_sw_fini(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_uvd_suspend(adev); if (r) @@ -139,8 +143,9 @@ static int uvd_v4_2_sw_fini(struct amdgpu_device *adev) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int uvd_v4_2_hw_init(struct amdgpu_device *adev) +static int uvd_v4_2_hw_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_ring *ring = &adev->uvd.ring; uint32_t tmp; int r; @@ -203,8 +208,9 @@ done: * * Stop the UVD block, mark ring as not ready any more */ -static int uvd_v4_2_hw_fini(struct amdgpu_device *adev) +static int uvd_v4_2_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_ring *ring = &adev->uvd.ring; uvd_v4_2_stop(adev); @@ -213,9 +219,10 @@ static int uvd_v4_2_hw_fini(struct amdgpu_device *adev) return 0; } -static int uvd_v4_2_suspend(struct amdgpu_device *adev) +static int uvd_v4_2_suspend(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = uvd_v4_2_hw_fini(adev); if (r) @@ -228,9 +235,10 @@ static int uvd_v4_2_suspend(struct amdgpu_device *adev) return r; } -static int uvd_v4_2_resume(struct amdgpu_device *adev) +static int uvd_v4_2_resume(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_uvd_resume(adev); if (r) @@ -662,14 +670,17 @@ static void uvd_v4_2_init_cg(struct amdgpu_device *adev) } } -static bool uvd_v4_2_is_idle(struct amdgpu_device *adev) +static bool uvd_v4_2_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); } -static int uvd_v4_2_wait_for_idle(struct amdgpu_device *adev) +static int uvd_v4_2_wait_for_idle(void *handle) { unsigned i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) @@ -678,8 +689,10 @@ static int uvd_v4_2_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static int uvd_v4_2_soft_reset(struct amdgpu_device *adev) +static int uvd_v4_2_soft_reset(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + uvd_v4_2_stop(adev); WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, @@ -689,8 +702,9 @@ static int uvd_v4_2_soft_reset(struct amdgpu_device *adev) return uvd_v4_2_start(adev); } -static void uvd_v4_2_print_status(struct amdgpu_device *adev) +static void uvd_v4_2_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dev_info(adev->dev, "UVD 4.2 registers\n"); dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", RREG32(mmUVD_SEMA_ADDR_LOW)); @@ -810,12 +824,13 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, return 0; } -static int uvd_v4_2_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int uvd_v4_2_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { bool gate = false; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (state == AMDGPU_CG_STATE_GATE) + if (state == AMD_CG_STATE_GATE) gate = true; uvd_v4_2_enable_mgcg(adev, gate); @@ -823,8 +838,8 @@ static int uvd_v4_2_set_clockgating_state(struct amdgpu_device *adev, return 0; } -static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int uvd_v4_2_set_powergating_state(void *handle, + enum amd_powergating_state state) { /* This doesn't actually powergate the UVD block. * That's done in the dpm code via the SMC. This @@ -833,7 +848,9 @@ static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev, * revisit this when there is a cleaner line between * the smc and the hw blocks */ - if (state == AMDGPU_PG_STATE_GATE) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (state == AMD_PG_STATE_GATE) { uvd_v4_2_stop(adev); return 0; } else { @@ -841,7 +858,7 @@ static int uvd_v4_2_set_powergating_state(struct amdgpu_device *adev, } } -const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs = { +const struct amd_ip_funcs uvd_v4_2_ip_funcs = { .early_init = uvd_v4_2_early_init, .late_init = NULL, .sw_init = uvd_v4_2_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h index 323a6d828dfe..0a615dd50840 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.h @@ -24,6 +24,6 @@ #ifndef __UVD_V4_2_H__ #define __UVD_V4_2_H__ -extern const struct amdgpu_ip_funcs uvd_v4_2_ip_funcs; +extern const struct amd_ip_funcs uvd_v4_2_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index f3b3026d5932..004c56496fc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -79,17 +79,20 @@ static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); } -static int uvd_v5_0_early_init(struct amdgpu_device *adev) +static int uvd_v5_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + uvd_v5_0_set_ring_funcs(adev); uvd_v5_0_set_irq_funcs(adev); return 0; } -static int uvd_v5_0_sw_init(struct amdgpu_device *adev) +static int uvd_v5_0_sw_init(void *handle) { struct amdgpu_ring *ring; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; /* UVD TRAP */ @@ -113,9 +116,10 @@ static int uvd_v5_0_sw_init(struct amdgpu_device *adev) return r; } -static int uvd_v5_0_sw_fini(struct amdgpu_device *adev) +static int uvd_v5_0_sw_fini(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_uvd_suspend(adev); if (r) @@ -135,8 +139,9 @@ static int uvd_v5_0_sw_fini(struct amdgpu_device *adev) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int uvd_v5_0_hw_init(struct amdgpu_device *adev) +static int uvd_v5_0_hw_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_ring *ring = &adev->uvd.ring; uint32_t tmp; int r; @@ -199,8 +204,9 @@ done: * * Stop the UVD block, mark ring as not ready any more */ -static int uvd_v5_0_hw_fini(struct amdgpu_device *adev) +static int uvd_v5_0_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_ring *ring = &adev->uvd.ring; uvd_v5_0_stop(adev); @@ -209,9 +215,10 @@ static int uvd_v5_0_hw_fini(struct amdgpu_device *adev) return 0; } -static int uvd_v5_0_suspend(struct amdgpu_device *adev) +static int uvd_v5_0_suspend(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = uvd_v5_0_hw_fini(adev); if (r) @@ -224,9 +231,10 @@ static int uvd_v5_0_suspend(struct amdgpu_device *adev) return r; } -static int uvd_v5_0_resume(struct amdgpu_device *adev) +static int uvd_v5_0_resume(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_uvd_resume(adev); if (r) @@ -605,14 +613,17 @@ error: return r; } -static bool uvd_v5_0_is_idle(struct amdgpu_device *adev) +static bool uvd_v5_0_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); } -static int uvd_v5_0_wait_for_idle(struct amdgpu_device *adev) +static int uvd_v5_0_wait_for_idle(void *handle) { unsigned i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) @@ -621,8 +632,10 @@ static int uvd_v5_0_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static int uvd_v5_0_soft_reset(struct amdgpu_device *adev) +static int uvd_v5_0_soft_reset(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + uvd_v5_0_stop(adev); WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, @@ -632,8 +645,9 @@ static int uvd_v5_0_soft_reset(struct amdgpu_device *adev) return uvd_v5_0_start(adev); } -static void uvd_v5_0_print_status(struct amdgpu_device *adev) +static void uvd_v5_0_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dev_info(adev->dev, "UVD 5.0 registers\n"); dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", RREG32(mmUVD_SEMA_ADDR_LOW)); @@ -757,16 +771,14 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, return 0; } -static int uvd_v5_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int uvd_v5_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { - //TODO - return 0; } -static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int uvd_v5_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { /* This doesn't actually powergate the UVD block. * That's done in the dpm code via the SMC. This @@ -775,7 +787,9 @@ static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev, * revisit this when there is a cleaner line between * the smc and the hw blocks */ - if (state == AMDGPU_PG_STATE_GATE) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (state == AMD_PG_STATE_GATE) { uvd_v5_0_stop(adev); return 0; } else { @@ -783,7 +797,7 @@ static int uvd_v5_0_set_powergating_state(struct amdgpu_device *adev, } } -const struct amdgpu_ip_funcs uvd_v5_0_ip_funcs = { +const struct amd_ip_funcs uvd_v5_0_ip_funcs = { .early_init = uvd_v5_0_early_init, .late_init = NULL, .sw_init = uvd_v5_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h index 7d7a15296383..e3b3c49fa5de 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.h @@ -24,6 +24,6 @@ #ifndef __UVD_V5_0_H__ #define __UVD_V5_0_H__ -extern const struct amdgpu_ip_funcs uvd_v5_0_ip_funcs; +extern const struct amd_ip_funcs uvd_v5_0_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index f59942d5c50e..8c790fb31e2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -79,18 +79,21 @@ static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); } -static int uvd_v6_0_early_init(struct amdgpu_device *adev) +static int uvd_v6_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + uvd_v6_0_set_ring_funcs(adev); uvd_v6_0_set_irq_funcs(adev); return 0; } -static int uvd_v6_0_sw_init(struct amdgpu_device *adev) +static int uvd_v6_0_sw_init(void *handle) { struct amdgpu_ring *ring; int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* UVD TRAP */ r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); @@ -113,9 +116,10 @@ static int uvd_v6_0_sw_init(struct amdgpu_device *adev) return r; } -static int uvd_v6_0_sw_fini(struct amdgpu_device *adev) +static int uvd_v6_0_sw_fini(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_uvd_suspend(adev); if (r) @@ -135,8 +139,9 @@ static int uvd_v6_0_sw_fini(struct amdgpu_device *adev) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int uvd_v6_0_hw_init(struct amdgpu_device *adev) +static int uvd_v6_0_hw_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_ring *ring = &adev->uvd.ring; uint32_t tmp; int r; @@ -193,8 +198,9 @@ done: * * Stop the UVD block, mark ring as not ready any more */ -static int uvd_v6_0_hw_fini(struct amdgpu_device *adev) +static int uvd_v6_0_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_ring *ring = &adev->uvd.ring; uvd_v6_0_stop(adev); @@ -203,9 +209,10 @@ static int uvd_v6_0_hw_fini(struct amdgpu_device *adev) return 0; } -static int uvd_v6_0_suspend(struct amdgpu_device *adev) +static int uvd_v6_0_suspend(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = uvd_v6_0_hw_fini(adev); if (r) @@ -218,9 +225,10 @@ static int uvd_v6_0_suspend(struct amdgpu_device *adev) return r; } -static int uvd_v6_0_resume(struct amdgpu_device *adev) +static int uvd_v6_0_resume(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_uvd_resume(adev); if (r) @@ -593,14 +601,17 @@ error: return r; } -static bool uvd_v6_0_is_idle(struct amdgpu_device *adev) +static bool uvd_v6_0_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); } -static int uvd_v6_0_wait_for_idle(struct amdgpu_device *adev) +static int uvd_v6_0_wait_for_idle(void *handle) { unsigned i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) @@ -609,8 +620,10 @@ static int uvd_v6_0_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static int uvd_v6_0_soft_reset(struct amdgpu_device *adev) +static int uvd_v6_0_soft_reset(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + uvd_v6_0_stop(adev); WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, @@ -620,8 +633,9 @@ static int uvd_v6_0_soft_reset(struct amdgpu_device *adev) return uvd_v6_0_start(adev); } -static void uvd_v6_0_print_status(struct amdgpu_device *adev) +static void uvd_v6_0_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; dev_info(adev->dev, "UVD 6.0 registers\n"); dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", RREG32(mmUVD_SEMA_ADDR_LOW)); @@ -737,16 +751,14 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, return 0; } -static int uvd_v6_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int uvd_v6_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { - //TODO - return 0; } -static int uvd_v6_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int uvd_v6_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { /* This doesn't actually powergate the UVD block. * That's done in the dpm code via the SMC. This @@ -755,7 +767,9 @@ static int uvd_v6_0_set_powergating_state(struct amdgpu_device *adev, * revisit this when there is a cleaner line between * the smc and the hw blocks */ - if (state == AMDGPU_PG_STATE_GATE) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (state == AMD_PG_STATE_GATE) { uvd_v6_0_stop(adev); return 0; } else { @@ -763,7 +777,7 @@ static int uvd_v6_0_set_powergating_state(struct amdgpu_device *adev, } } -const struct amdgpu_ip_funcs uvd_v6_0_ip_funcs = { +const struct amd_ip_funcs uvd_v6_0_ip_funcs = { .early_init = uvd_v6_0_early_init, .late_init = NULL, .sw_init = uvd_v6_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h index bc21afc8abac..6b92a2352986 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.h @@ -24,6 +24,6 @@ #ifndef __UVD_V6_0_H__ #define __UVD_V6_0_H__ -extern const struct amdgpu_ip_funcs uvd_v6_0_ip_funcs; +extern const struct amd_ip_funcs uvd_v6_0_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index f200df3cf97a..303d961d57bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -169,18 +169,21 @@ static int vce_v2_0_start(struct amdgpu_device *adev) return 0; } -static int vce_v2_0_early_init(struct amdgpu_device *adev) +static int vce_v2_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + vce_v2_0_set_ring_funcs(adev); vce_v2_0_set_irq_funcs(adev); return 0; } -static int vce_v2_0_sw_init(struct amdgpu_device *adev) +static int vce_v2_0_sw_init(void *handle) { struct amdgpu_ring *ring; int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* VCE */ r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq); @@ -213,9 +216,10 @@ static int vce_v2_0_sw_init(struct amdgpu_device *adev) return r; } -static int vce_v2_0_sw_fini(struct amdgpu_device *adev) +static int vce_v2_0_sw_fini(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_vce_suspend(adev); if (r) @@ -228,10 +232,11 @@ static int vce_v2_0_sw_fini(struct amdgpu_device *adev) return r; } -static int vce_v2_0_hw_init(struct amdgpu_device *adev) +static int vce_v2_0_hw_init(void *handle) { struct amdgpu_ring *ring; int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = vce_v2_0_start(adev); if (r) @@ -258,15 +263,15 @@ static int vce_v2_0_hw_init(struct amdgpu_device *adev) return 0; } -static int vce_v2_0_hw_fini(struct amdgpu_device *adev) +static int vce_v2_0_hw_fini(void *handle) { - // TODO return 0; } -static int vce_v2_0_suspend(struct amdgpu_device *adev) +static int vce_v2_0_suspend(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = vce_v2_0_hw_fini(adev); if (r) @@ -279,9 +284,10 @@ static int vce_v2_0_suspend(struct amdgpu_device *adev) return r; } -static int vce_v2_0_resume(struct amdgpu_device *adev) +static int vce_v2_0_resume(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_vce_resume(adev); if (r) @@ -442,14 +448,17 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev) vce_v2_0_init_cg(adev); } -static bool vce_v2_0_is_idle(struct amdgpu_device *adev) +static bool vce_v2_0_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); } -static int vce_v2_0_wait_for_idle(struct amdgpu_device *adev) +static int vce_v2_0_wait_for_idle(void *handle) { unsigned i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK)) @@ -458,8 +467,10 @@ static int vce_v2_0_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static int vce_v2_0_soft_reset(struct amdgpu_device *adev) +static int vce_v2_0_soft_reset(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK, ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK); mdelay(5); @@ -467,8 +478,10 @@ static int vce_v2_0_soft_reset(struct amdgpu_device *adev) return vce_v2_0_start(adev); } -static void vce_v2_0_print_status(struct amdgpu_device *adev) +static void vce_v2_0_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + dev_info(adev->dev, "VCE 2.0 registers\n"); dev_info(adev->dev, " VCE_STATUS=0x%08X\n", RREG32(mmVCE_STATUS)); @@ -569,12 +582,13 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev, return 0; } -static int vce_v2_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int vce_v2_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { bool gate = false; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (state == AMDGPU_CG_STATE_GATE) + if (state == AMD_CG_STATE_GATE) gate = true; vce_v2_0_enable_mgcg(adev, gate); @@ -582,8 +596,8 @@ static int vce_v2_0_set_clockgating_state(struct amdgpu_device *adev, return 0; } -static int vce_v2_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int vce_v2_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { /* This doesn't actually powergate the VCE block. * That's done in the dpm code via the SMC. This @@ -592,14 +606,16 @@ static int vce_v2_0_set_powergating_state(struct amdgpu_device *adev, * revisit this when there is a cleaner line between * the smc and the hw blocks */ - if (state == AMDGPU_PG_STATE_GATE) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (state == AMD_PG_STATE_GATE) /* XXX do we need a vce_v2_0_stop()? */ return 0; else return vce_v2_0_start(adev); } -const struct amdgpu_ip_funcs vce_v2_0_ip_funcs = { +const struct amd_ip_funcs vce_v2_0_ip_funcs = { .early_init = vce_v2_0_early_init, .late_init = NULL, .sw_init = vce_v2_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h index 8eb1cf227ea6..0d2ae8a01acd 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.h @@ -24,6 +24,6 @@ #ifndef __VCE_V2_0_H__ #define __VCE_V2_0_H__ -extern const struct amdgpu_ip_funcs vce_v2_0_ip_funcs; +extern const struct amd_ip_funcs vce_v2_0_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 57e0e167c83b..d62c4002e39c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -190,16 +190,19 @@ static int vce_v3_0_start(struct amdgpu_device *adev) return 0; } -static int vce_v3_0_early_init(struct amdgpu_device *adev) +static int vce_v3_0_early_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + vce_v3_0_set_ring_funcs(adev); vce_v3_0_set_irq_funcs(adev); return 0; } -static int vce_v3_0_sw_init(struct amdgpu_device *adev) +static int vce_v3_0_sw_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_ring *ring; int r; @@ -234,9 +237,10 @@ static int vce_v3_0_sw_init(struct amdgpu_device *adev) return r; } -static int vce_v3_0_sw_fini(struct amdgpu_device *adev) +static int vce_v3_0_sw_fini(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_vce_suspend(adev); if (r) @@ -249,10 +253,11 @@ static int vce_v3_0_sw_fini(struct amdgpu_device *adev) return r; } -static int vce_v3_0_hw_init(struct amdgpu_device *adev) +static int vce_v3_0_hw_init(void *handle) { struct amdgpu_ring *ring; int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = vce_v3_0_start(adev); if (r) @@ -279,15 +284,15 @@ static int vce_v3_0_hw_init(struct amdgpu_device *adev) return 0; } -static int vce_v3_0_hw_fini(struct amdgpu_device *adev) +static int vce_v3_0_hw_fini(void *handle) { - // TODO return 0; } -static int vce_v3_0_suspend(struct amdgpu_device *adev) +static int vce_v3_0_suspend(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = vce_v3_0_hw_fini(adev); if (r) @@ -300,9 +305,10 @@ static int vce_v3_0_suspend(struct amdgpu_device *adev) return r; } -static int vce_v3_0_resume(struct amdgpu_device *adev) +static int vce_v3_0_resume(void *handle) { int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_vce_resume(adev); if (r) @@ -362,14 +368,17 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); } -static bool vce_v3_0_is_idle(struct amdgpu_device *adev) +static bool vce_v3_0_is_idle(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); } -static int vce_v3_0_wait_for_idle(struct amdgpu_device *adev) +static int vce_v3_0_wait_for_idle(void *handle) { unsigned i; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (i = 0; i < adev->usec_timeout; i++) { if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK)) @@ -378,8 +387,10 @@ static int vce_v3_0_wait_for_idle(struct amdgpu_device *adev) return -ETIMEDOUT; } -static int vce_v3_0_soft_reset(struct amdgpu_device *adev) +static int vce_v3_0_soft_reset(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK, ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK); mdelay(5); @@ -387,8 +398,10 @@ static int vce_v3_0_soft_reset(struct amdgpu_device *adev) return vce_v3_0_start(adev); } -static void vce_v3_0_print_status(struct amdgpu_device *adev) +static void vce_v3_0_print_status(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + dev_info(adev->dev, "VCE 3.0 registers\n"); dev_info(adev->dev, " VCE_STATUS=0x%08X\n", RREG32(mmVCE_STATUS)); @@ -487,15 +500,14 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev, return 0; } -static int vce_v3_0_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int vce_v3_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { - //TODO return 0; } -static int vce_v3_0_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int vce_v3_0_set_powergating_state(void *handle, + enum amd_powergating_state state) { /* This doesn't actually powergate the VCE block. * That's done in the dpm code via the SMC. This @@ -504,14 +516,16 @@ static int vce_v3_0_set_powergating_state(struct amdgpu_device *adev, * revisit this when there is a cleaner line between * the smc and the hw blocks */ - if (state == AMDGPU_PG_STATE_GATE) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (state == AMD_PG_STATE_GATE) /* XXX do we need a vce_v3_0_stop()? */ return 0; else return vce_v3_0_start(adev); } -const struct amdgpu_ip_funcs vce_v3_0_ip_funcs = { +const struct amd_ip_funcs vce_v3_0_ip_funcs = { .early_init = vce_v3_0_early_init, .late_init = NULL, .sw_init = vce_v3_0_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h index f3c2ba92a1f1..b45af65da81f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.h @@ -24,6 +24,6 @@ #ifndef __VCE_V3_0_H__ #define __VCE_V3_0_H__ -extern const struct amdgpu_ip_funcs vce_v3_0_ip_funcs; +extern const struct amd_ip_funcs vce_v3_0_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 59a073aa42a4..be7c17610696 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -994,42 +994,42 @@ static const struct amdgpu_ip_block_version topaz_ip_blocks[] = { /* ORDER MATTERS! */ { - .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 2, .minor = 0, .rev = 0, .funcs = &vi_common_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .type = AMD_IP_BLOCK_TYPE_GMC, .major = 8, .minor = 0, .rev = 0, .funcs = &gmc_v8_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_IH, + .type = AMD_IP_BLOCK_TYPE_IH, .major = 2, .minor = 4, .rev = 0, .funcs = &iceland_ih_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .type = AMD_IP_BLOCK_TYPE_SMC, .major = 7, .minor = 1, .rev = 0, .funcs = &iceland_dpm_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .type = AMD_IP_BLOCK_TYPE_GFX, .major = 8, .minor = 0, .rev = 0, .funcs = &gfx_v8_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 2, .minor = 4, .rev = 0, @@ -1041,63 +1041,63 @@ static const struct amdgpu_ip_block_version tonga_ip_blocks[] = { /* ORDER MATTERS! */ { - .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 2, .minor = 0, .rev = 0, .funcs = &vi_common_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .type = AMD_IP_BLOCK_TYPE_GMC, .major = 8, .minor = 0, .rev = 0, .funcs = &gmc_v8_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_IH, + .type = AMD_IP_BLOCK_TYPE_IH, .major = 3, .minor = 0, .rev = 0, .funcs = &tonga_ih_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .type = AMD_IP_BLOCK_TYPE_SMC, .major = 7, .minor = 1, .rev = 0, .funcs = &tonga_dpm_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .type = AMD_IP_BLOCK_TYPE_DCE, .major = 10, .minor = 0, .rev = 0, .funcs = &dce_v10_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .type = AMD_IP_BLOCK_TYPE_GFX, .major = 8, .minor = 0, .rev = 0, .funcs = &gfx_v8_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 3, .minor = 0, .rev = 0, .funcs = &sdma_v3_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .type = AMD_IP_BLOCK_TYPE_UVD, .major = 5, .minor = 0, .rev = 0, .funcs = &uvd_v5_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .type = AMD_IP_BLOCK_TYPE_VCE, .major = 3, .minor = 0, .rev = 0, @@ -1109,63 +1109,63 @@ static const struct amdgpu_ip_block_version cz_ip_blocks[] = { /* ORDER MATTERS! */ { - .type = AMDGPU_IP_BLOCK_TYPE_COMMON, + .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 2, .minor = 0, .rev = 0, .funcs = &vi_common_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GMC, + .type = AMD_IP_BLOCK_TYPE_GMC, .major = 8, .minor = 0, .rev = 0, .funcs = &gmc_v8_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_IH, + .type = AMD_IP_BLOCK_TYPE_IH, .major = 3, .minor = 0, .rev = 0, .funcs = &cz_ih_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SMC, + .type = AMD_IP_BLOCK_TYPE_SMC, .major = 8, .minor = 0, .rev = 0, .funcs = &cz_dpm_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_DCE, + .type = AMD_IP_BLOCK_TYPE_DCE, .major = 11, .minor = 0, .rev = 0, .funcs = &dce_v11_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_GFX, + .type = AMD_IP_BLOCK_TYPE_GFX, .major = 8, .minor = 0, .rev = 0, .funcs = &gfx_v8_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_SDMA, + .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 3, .minor = 0, .rev = 0, .funcs = &sdma_v3_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_UVD, + .type = AMD_IP_BLOCK_TYPE_UVD, .major = 6, .minor = 0, .rev = 0, .funcs = &uvd_v6_0_ip_funcs, }, { - .type = AMDGPU_IP_BLOCK_TYPE_VCE, + .type = AMD_IP_BLOCK_TYPE_VCE, .major = 3, .minor = 0, .rev = 0, @@ -1225,9 +1225,10 @@ static const struct amdgpu_asic_funcs vi_asic_funcs = .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle, }; -static int vi_common_early_init(struct amdgpu_device *adev) +static int vi_common_early_init(void *handle) { bool smc_enabled = false; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; adev->smc_rreg = &vi_smc_rreg; adev->smc_wreg = &vi_smc_wreg; @@ -1240,8 +1241,8 @@ static int vi_common_early_init(struct amdgpu_device *adev) adev->asic_funcs = &vi_asic_funcs; - if (amdgpu_get_ip_block(adev, AMDGPU_IP_BLOCK_TYPE_SMC) && - (amdgpu_ip_block_mask & (1 << AMDGPU_IP_BLOCK_TYPE_SMC))) + if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) && + (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC))) smc_enabled = true; adev->rev_id = vi_get_rev_id(adev); @@ -1279,18 +1280,20 @@ static int vi_common_early_init(struct amdgpu_device *adev) return 0; } -static int vi_common_sw_init(struct amdgpu_device *adev) +static int vi_common_sw_init(void *handle) { return 0; } -static int vi_common_sw_fini(struct amdgpu_device *adev) +static int vi_common_sw_fini(void *handle) { return 0; } -static int vi_common_hw_init(struct amdgpu_device *adev) +static int vi_common_hw_init(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + /* move the golden regs per IP block */ vi_init_golden_registers(adev); /* enable pcie gen2/3 link */ @@ -1303,58 +1306,63 @@ static int vi_common_hw_init(struct amdgpu_device *adev) return 0; } -static int vi_common_hw_fini(struct amdgpu_device *adev) +static int vi_common_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + /* enable the doorbell aperture */ vi_enable_doorbell_aperture(adev, false); return 0; } -static int vi_common_suspend(struct amdgpu_device *adev) +static int vi_common_suspend(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return vi_common_hw_fini(adev); } -static int vi_common_resume(struct amdgpu_device *adev) +static int vi_common_resume(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + return vi_common_hw_init(adev); } -static bool vi_common_is_idle(struct amdgpu_device *adev) +static bool vi_common_is_idle(void *handle) { return true; } -static int vi_common_wait_for_idle(struct amdgpu_device *adev) +static int vi_common_wait_for_idle(void *handle) { return 0; } -static void vi_common_print_status(struct amdgpu_device *adev) +static void vi_common_print_status(void *handle) { - + return; } -static int vi_common_soft_reset(struct amdgpu_device *adev) +static int vi_common_soft_reset(void *handle) { - /* XXX hard reset?? */ return 0; } -static int vi_common_set_clockgating_state(struct amdgpu_device *adev, - enum amdgpu_clockgating_state state) +static int vi_common_set_clockgating_state(void *handle, + enum amd_clockgating_state state) { return 0; } -static int vi_common_set_powergating_state(struct amdgpu_device *adev, - enum amdgpu_powergating_state state) +static int vi_common_set_powergating_state(void *handle, + enum amd_powergating_state state) { return 0; } -const struct amdgpu_ip_funcs vi_common_ip_funcs = { +const struct amd_ip_funcs vi_common_ip_funcs = { .early_init = vi_common_early_init, .late_init = NULL, .sw_init = vi_common_sw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h index d16a5f7e4edd..502094042462 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.h +++ b/drivers/gpu/drm/amd/amdgpu/vi.h @@ -24,7 +24,7 @@ #ifndef __VI_H__ #define __VI_H__ -extern const struct amdgpu_ip_funcs vi_common_ip_funcs; +extern const struct amd_ip_funcs vi_common_ip_funcs; void vi_srbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); diff --git a/drivers/gpu/drm/amd/amdgpu/vi_dpm.h b/drivers/gpu/drm/amd/amdgpu/vi_dpm.h index 11cb1f7eeba5..3b45332f5df4 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/vi_dpm.h @@ -24,13 +24,13 @@ #ifndef __VI_DPM_H__ #define __VI_DPM_H__ -extern const struct amdgpu_ip_funcs cz_dpm_ip_funcs; +extern const struct amd_ip_funcs cz_dpm_ip_funcs; int cz_smu_init(struct amdgpu_device *adev); int cz_smu_start(struct amdgpu_device *adev); int cz_smu_fini(struct amdgpu_device *adev); -extern const struct amdgpu_ip_funcs tonga_dpm_ip_funcs; +extern const struct amd_ip_funcs tonga_dpm_ip_funcs; -extern const struct amdgpu_ip_funcs iceland_dpm_ip_funcs; +extern const struct amd_ip_funcs iceland_dpm_ip_funcs; #endif diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h new file mode 100644 index 000000000000..5bdf1b4397a0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -0,0 +1,81 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __AMD_SHARED_H__ +#define __AMD_SHARED_H__ + +enum amd_ip_block_type { + AMD_IP_BLOCK_TYPE_COMMON, + AMD_IP_BLOCK_TYPE_GMC, + AMD_IP_BLOCK_TYPE_IH, + AMD_IP_BLOCK_TYPE_SMC, + AMD_IP_BLOCK_TYPE_DCE, + AMD_IP_BLOCK_TYPE_GFX, + AMD_IP_BLOCK_TYPE_SDMA, + AMD_IP_BLOCK_TYPE_UVD, + AMD_IP_BLOCK_TYPE_VCE, +}; + +enum amd_clockgating_state { + AMD_CG_STATE_GATE = 0, + AMD_CG_STATE_UNGATE, +}; + +enum amd_powergating_state { + AMD_PG_STATE_GATE = 0, + AMD_PG_STATE_UNGATE, +}; + +struct amd_ip_funcs { + /* sets up early driver state (pre sw_init), does not configure hw - Optional */ + int (*early_init)(void *handle); + /* sets up late driver/hw state (post hw_init) - Optional */ + int (*late_init)(void *handle); + /* sets up driver state, does not configure hw */ + int (*sw_init)(void *handle); + /* tears down driver state, does not configure hw */ + int (*sw_fini)(void *handle); + /* sets up the hw state */ + int (*hw_init)(void *handle); + /* tears down the hw state */ + int (*hw_fini)(void *handle); + /* handles IP specific hw/sw changes for suspend */ + int (*suspend)(void *handle); + /* handles IP specific hw/sw changes for resume */ + int (*resume)(void *handle); + /* returns current IP block idle status */ + bool (*is_idle)(void *handle); + /* poll for idle */ + int (*wait_for_idle)(void *handle); + /* soft reset the IP block */ + int (*soft_reset)(void *handle); + /* dump the IP block status registers */ + void (*print_status)(void *handle); + /* enable/disable cg for the IP block */ + int (*set_clockgating_state)(void *handle, + enum amd_clockgating_state state); + /* enable/disable pg for the IP block */ + int (*set_powergating_state)(void *handle, + enum amd_powergating_state state); +}; + +#endif /* __AMD_SHARED_H__ */ -- cgit v1.2.3 From 7e5a547f64af66fd906f266f0e8c9bde213d025c Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Fri, 24 Apr 2015 17:37:30 +0800 Subject: drm/amdgpu: implement the allocation range (v3) Pass a ttm_placement pointer to amdgpu_bo_create_restricted add min_offset to amdgpu_bo_pin_restricted. This makes it easier to allocate memory with address restrictions. With this patch we can also enable 2-ended allocation again. v2: fix rebase conflicts v3: memset placements before using Reviewed-by: Jammy Zhou Signed-off-by: Chunming Zhou Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 176 +++++++++++++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 9 +- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +- 8 files changed, 136 insertions(+), 64 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 80f0bea52e33..8eb5c5529304 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -43,6 +43,7 @@ #include #include +#include #include "amd_shared.h" #include "amdgpu_family.h" @@ -542,12 +543,14 @@ struct amdgpu_bo_va { struct amdgpu_bo *bo; }; +#define AMDGPU_GEM_DOMAIN_MAX 0x3 + struct amdgpu_bo { /* Protected by gem.mutex */ struct list_head list; /* Protected by tbo.reserved */ u32 initial_domain; - struct ttm_place placements[4]; + struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; struct ttm_placement placement; struct ttm_buffer_object tbo; struct ttm_bo_kmap_obj kmap; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index f22c0671c3eb..b16b9256883e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -159,7 +159,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, goto cleanup; } - r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, &base); + r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); if (unlikely(r != 0)) { amdgpu_bo_unreserve(new_rbo); r = -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 73b7aad5a872..c1645d21f8e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -150,7 +150,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, } - ret = amdgpu_bo_pin_restricted(rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL); + ret = amdgpu_bo_pin_restricted(rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, NULL); if (ret) { amdgpu_bo_unreserve(rbo); goto out_unref; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index dcc6af97f59d..62cabfb5dff8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -41,13 +41,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev, - struct ttm_mem_reg * mem) + struct ttm_mem_reg *mem) { u64 ret = 0; if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) { ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) > adev->mc.visible_vram_size ? - adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT): + adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) : mem->size; } return ret; @@ -112,82 +112,111 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) return false; } -void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain) +static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, + struct ttm_placement *placement, + struct ttm_place *placements, + u32 domain, u64 flags) { u32 c = 0, i; - rbo->placement.placement = rbo->placements; - rbo->placement.busy_placement = rbo->placements; + + placement->placement = placements; + placement->busy_placement = placements; if (domain & AMDGPU_GEM_DOMAIN_VRAM) { - if (rbo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS && - rbo->adev->mc.visible_vram_size < rbo->adev->mc.real_vram_size) { - rbo->placements[c].fpfn = - rbo->adev->mc.visible_vram_size >> PAGE_SHIFT; - rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | - TTM_PL_FLAG_VRAM; + if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS && + adev->mc.visible_vram_size < adev->mc.real_vram_size) { + placements[c].fpfn = + adev->mc.visible_vram_size >> PAGE_SHIFT; + placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | + TTM_PL_FLAG_VRAM; } - rbo->placements[c].fpfn = 0; - rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | - TTM_PL_FLAG_VRAM; + placements[c].fpfn = 0; + placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | + TTM_PL_FLAG_VRAM; } if (domain & AMDGPU_GEM_DOMAIN_GTT) { - if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { - rbo->placements[c].fpfn = 0; - rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT | - TTM_PL_FLAG_UNCACHED; + if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { + placements[c].fpfn = 0; + placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT | + TTM_PL_FLAG_UNCACHED; } else { - rbo->placements[c].fpfn = 0; - rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; + placements[c].fpfn = 0; + placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; } } if (domain & AMDGPU_GEM_DOMAIN_CPU) { - if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { - rbo->placements[c].fpfn = 0; - rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM | - TTM_PL_FLAG_UNCACHED; + if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { + placements[c].fpfn = 0; + placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM | + TTM_PL_FLAG_UNCACHED; } else { - rbo->placements[c].fpfn = 0; - rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; + placements[c].fpfn = 0; + placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; } } if (domain & AMDGPU_GEM_DOMAIN_GDS) { - rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | - AMDGPU_PL_FLAG_GDS; + placements[c].fpfn = 0; + placements[c++].flags = TTM_PL_FLAG_UNCACHED | + AMDGPU_PL_FLAG_GDS; } if (domain & AMDGPU_GEM_DOMAIN_GWS) { - rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | - AMDGPU_PL_FLAG_GWS; + placements[c].fpfn = 0; + placements[c++].flags = TTM_PL_FLAG_UNCACHED | + AMDGPU_PL_FLAG_GWS; } if (domain & AMDGPU_GEM_DOMAIN_OA) { - rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | - AMDGPU_PL_FLAG_OA; + placements[c].fpfn = 0; + placements[c++].flags = TTM_PL_FLAG_UNCACHED | + AMDGPU_PL_FLAG_OA; } if (!c) { - rbo->placements[c].fpfn = 0; - rbo->placements[c++].flags = TTM_PL_MASK_CACHING | - TTM_PL_FLAG_SYSTEM; + placements[c].fpfn = 0; + placements[c++].flags = TTM_PL_MASK_CACHING | + TTM_PL_FLAG_SYSTEM; } - rbo->placement.num_placement = c; - rbo->placement.num_busy_placement = c; + placement->num_placement = c; + placement->num_busy_placement = c; for (i = 0; i < c; i++) { - if ((rbo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && - (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && - !rbo->placements[i].fpfn) - rbo->placements[i].lpfn = - rbo->adev->mc.visible_vram_size >> PAGE_SHIFT; + if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && + (placements[i].flags & TTM_PL_FLAG_VRAM) && + !placements[i].fpfn) + placements[i].lpfn = + adev->mc.visible_vram_size >> PAGE_SHIFT; else - rbo->placements[i].lpfn = 0; + placements[i].lpfn = 0; } } -int amdgpu_bo_create(struct amdgpu_device *adev, - unsigned long size, int byte_align, bool kernel, u32 domain, u64 flags, - struct sg_table *sg, struct amdgpu_bo **bo_ptr) +void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain) +{ + amdgpu_ttm_placement_init(rbo->adev, &rbo->placement, + rbo->placements, domain, rbo->flags); +} + +static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, + struct ttm_placement *placement) +{ + BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1)); + + memcpy(bo->placements, placement->placement, + placement->num_placement * sizeof(struct ttm_place)); + bo->placement.num_placement = placement->num_placement; + bo->placement.num_busy_placement = placement->num_busy_placement; + bo->placement.placement = bo->placements; + bo->placement.busy_placement = bo->placements; +} + +int amdgpu_bo_create_restricted(struct amdgpu_device *adev, + unsigned long size, int byte_align, + bool kernel, u32 domain, u64 flags, + struct sg_table *sg, + struct ttm_placement *placement, + struct amdgpu_bo **bo_ptr) { struct amdgpu_bo *bo; enum ttm_bo_type type; @@ -241,7 +270,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, AMDGPU_GEM_DOMAIN_OA); bo->flags = flags; - amdgpu_ttm_placement_from_domain(bo, domain); + amdgpu_fill_placement_to_bo(bo, placement); /* Kernel allocation are uninterruptible */ down_read(&adev->pm.mclk_lock); r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, @@ -258,6 +287,27 @@ int amdgpu_bo_create(struct amdgpu_device *adev, return 0; } +int amdgpu_bo_create(struct amdgpu_device *adev, + unsigned long size, int byte_align, + bool kernel, u32 domain, u64 flags, + struct sg_table *sg, struct amdgpu_bo **bo_ptr) +{ + struct ttm_placement placement = {0}; + struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; + + memset(&placements, 0, + (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); + + amdgpu_ttm_placement_init(adev, &placement, + placements, domain, flags); + + return amdgpu_bo_create_restricted(adev, size, byte_align, + kernel, domain, flags, + sg, + &placement, + bo_ptr); +} + int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) { bool is_iomem; @@ -313,14 +363,19 @@ void amdgpu_bo_unref(struct amdgpu_bo **bo) *bo = NULL; } -int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, u64 max_offset, +int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, + u64 min_offset, u64 max_offset, u64 *gpu_addr) { int r, i; + unsigned fpfn, lpfn; if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm)) return -EPERM; + if (WARN_ON_ONCE(min_offset > max_offset)) + return -EINVAL; + if (bo->pin_count) { bo->pin_count++; if (gpu_addr) @@ -328,7 +383,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, u64 max_offset, if (max_offset != 0) { u64 domain_start; - if (domain == AMDGPU_GEM_DOMAIN_VRAM) domain_start = bo->adev->mc.vram_start; else @@ -343,13 +397,21 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, u64 max_offset, for (i = 0; i < bo->placement.num_placement; i++) { /* force to pin into visible video ram */ if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && - !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && - (!max_offset || max_offset > bo->adev->mc.visible_vram_size)) - bo->placements[i].lpfn = - bo->adev->mc.visible_vram_size >> PAGE_SHIFT; - else - bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; - + !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && + (!max_offset || max_offset > bo->adev->mc.visible_vram_size)) { + if (WARN_ON_ONCE(min_offset > + bo->adev->mc.visible_vram_size)) + return -EINVAL; + fpfn = min_offset >> PAGE_SHIFT; + lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT; + } else { + fpfn = min_offset >> PAGE_SHIFT; + lpfn = max_offset >> PAGE_SHIFT; + } + if (fpfn > bo->placements[i].fpfn) + bo->placements[i].fpfn = fpfn; + if (lpfn && lpfn < bo->placements[i].lpfn) + bo->placements[i].lpfn = lpfn; bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; } @@ -370,7 +432,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, u64 max_offset, int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) { - return amdgpu_bo_pin_restricted(bo, domain, 0, gpu_addr); + return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr); } int amdgpu_bo_unpin(struct amdgpu_bo *bo) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index b1e0a03c1d78..675bdc30e41d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -130,13 +130,20 @@ int amdgpu_bo_create(struct amdgpu_device *adev, bool kernel, u32 domain, u64 flags, struct sg_table *sg, struct amdgpu_bo **bo_ptr); +int amdgpu_bo_create_restricted(struct amdgpu_device *adev, + unsigned long size, int byte_align, + bool kernel, u32 domain, u64 flags, + struct sg_table *sg, + struct ttm_placement *placement, + struct amdgpu_bo **bo_ptr); int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); void amdgpu_bo_kunmap(struct amdgpu_bo *bo); struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); void amdgpu_bo_unref(struct amdgpu_bo **bo); int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr); int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, - u64 max_offset, u64 *gpu_addr); + u64 min_offset, u64 max_offset, + u64 *gpu_addr); int amdgpu_bo_unpin(struct amdgpu_bo *bo); int amdgpu_bo_evict_vram(struct amdgpu_device *adev); void amdgpu_bo_force_delete(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index da9a4b9a1f6c..926c8e0789b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2553,7 +2553,7 @@ static int dce_v10_0_crtc_cursor_set(struct drm_crtc *crtc, if (unlikely(ret != 0)) goto fail; ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, - 0, &gpu_addr); + 0, 0, &gpu_addr); amdgpu_bo_unreserve(robj); if (ret) goto fail; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index edd9d17ba82a..bc60fd1844f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2552,7 +2552,7 @@ static int dce_v11_0_crtc_cursor_set(struct drm_crtc *crtc, if (unlikely(ret != 0)) goto fail; ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, - 0, &gpu_addr); + 0, 0, &gpu_addr); amdgpu_bo_unreserve(robj); if (ret) goto fail; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 1d291f1d5b79..9e8b9f1fad18 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2496,7 +2496,7 @@ static int dce_v8_0_crtc_cursor_set(struct drm_crtc *crtc, if (unlikely(ret != 0)) goto fail; ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, - 0, &gpu_addr); + 0, 0, &gpu_addr); amdgpu_bo_unreserve(robj); if (ret) goto fail; -- cgit v1.2.3 From ca95261325cfdff85eb2c9107198c714e266cb5b Mon Sep 17 00:00:00 2001 From: "monk.liu" Date: Mon, 25 May 2015 14:44:05 +0800 Subject: drm/amdgpu: fix bug of vm_bo_map (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit call reservation_object_reserve_shared before amdgpu_bo_fence Signed-off-by: monk.liu Reviewed-by: Christian König Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index b25e533fd6e8..cc6dca2581a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -315,6 +315,10 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, if (r) return r; + r = reservation_object_reserve_shared(bo->tbo.resv); + if (r) + return r; + r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); if (r) goto error_unreserve; -- cgit v1.2.3 From 3d5a08c114585e5b9f890807b04d2730dafde5e1 Mon Sep 17 00:00:00 2001 From: "monk.liu" Date: Tue, 26 May 2015 10:22:41 +0800 Subject: drm/amdgpu: max_pde_used usage should be under protect MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Need to take the lock when accessing this. Signed-off-by: monk.liu Reviewed-by: Christian König Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index cc6dca2581a6..dcb2d3859cf1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -90,10 +90,13 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, struct amdgpu_bo_list_entry *list; unsigned i, idx; + mutex_lock(&vm->mutex); list = drm_malloc_ab(vm->max_pde_used + 2, sizeof(struct amdgpu_bo_list_entry)); - if (!list) + if (!list) { + mutex_unlock(&vm->mutex); return NULL; + } /* add the vm page table to the list */ list[0].robj = vm->page_directory; @@ -116,6 +119,7 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, list[idx].tv.shared = true; list_add(&list[idx++].tv.head, head); } + mutex_unlock(&vm->mutex); return list; } -- cgit v1.2.3 From cfe2c9780756b63af695078c110b755876b09dfc Mon Sep 17 00:00:00 2001 From: "monk.liu" Date: Tue, 26 May 2015 15:01:54 +0800 Subject: drm/amdgpu: sync fence of clear_invalids (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit bo_va may un-initialized, fix it. Signed-off-by: monk.liu Reviewed-by: Christian König Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++++-- 3 files changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 8eb5c5529304..6c8c24ba463d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -2268,7 +2268,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, int amdgpu_vm_clear_freed(struct amdgpu_device *adev, struct amdgpu_vm *vm); int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, - struct amdgpu_vm *vm); + struct amdgpu_vm *vm, struct amdgpu_sync *sync); int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, struct ttm_mem_reg *mem); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index ecb30a1a73cc..fefa48a59a7d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -520,7 +520,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update); } - return amdgpu_vm_clear_invalids(adev, vm); + return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync); } static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index dcb2d3859cf1..4d26b303b495 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -858,9 +858,9 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, * PTs have to be reserved and mutex must be locked! */ int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, - struct amdgpu_vm *vm) + struct amdgpu_vm *vm, struct amdgpu_sync *sync) { - struct amdgpu_bo_va *bo_va; + struct amdgpu_bo_va *bo_va = NULL; int r; spin_lock(&vm->status_lock); @@ -877,6 +877,8 @@ int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, } spin_unlock(&vm->status_lock); + if (bo_va) + amdgpu_sync_fence(sync, bo_va->last_pt_update); return 0; } -- cgit v1.2.3 From aeb0aeac2e4f23bb58a642c720883ceba407c072 Mon Sep 17 00:00:00 2001 From: "monk.liu" Date: Tue, 26 May 2015 15:03:45 +0800 Subject: drm/amdgpu: fence should be added to shared slot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: monk.liu Reviewed-by: Christian König Reviewed-by: jammy zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 4d26b303b495..fd28e890693e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -344,7 +344,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, if (r) goto error_free; - amdgpu_bo_fence(bo, ib.fence, false); + amdgpu_bo_fence(bo, ib.fence, true); error_free: amdgpu_ib_free(adev, &ib); @@ -462,7 +462,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, amdgpu_ib_free(adev, &ib); return r; } - amdgpu_bo_fence(pd, ib.fence, false); + amdgpu_bo_fence(pd, ib.fence, true); } amdgpu_ib_free(adev, &ib); -- cgit v1.2.3 From d8f65a2376268dfb2963152754d41208dc43d906 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Wed, 27 May 2015 14:30:38 +0200 Subject: drm/amdgpu: rename GEM_OP_SET_INITIAL_DOMAIN -> GEM_OP_SET_PLACEMENT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marek Olšák Reviewed-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +- include/uapi/drm/amdgpu_drm.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index c90b74da0027..ad5b9c676fd8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -638,7 +638,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, r = -EFAULT; break; } - case AMDGPU_GEM_OP_SET_INITIAL_DOMAIN: + case AMDGPU_GEM_OP_SET_PLACEMENT: if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) { r = -EPERM; break; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 64a07ac3b4b9..cd54891b1d5c 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -284,8 +284,8 @@ struct drm_amdgpu_gem_op { uint64_t value; /* input or return value */ }; -#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 -#define AMDGPU_GEM_OP_SET_INITIAL_DOMAIN 1 +#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 +#define AMDGPU_GEM_OP_SET_PLACEMENT 1 #define AMDGPU_VA_OP_MAP 1 #define AMDGPU_VA_OP_UNMAP 2 -- cgit v1.2.3 From b9a7faaeb2b0271ca9a7d8436a055da219a35ec8 Mon Sep 17 00:00:00 2001 From: "monk.liu" Date: Wed, 27 May 2015 14:03:22 +0800 Subject: drm/amdgpu: remove all sh mem register modification in vm flush MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Leave that at the values set during init. No need to update them repeatedly. Signed-off-by: monk.liu Signed-off-by: David Zhang Reviewed-by: Christian König Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 27 ------------------------ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 27 ------------------------ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 30 --------------------------- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 38 ---------------------------------- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 38 ---------------------------------- 5 files changed, 160 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 7c816b5cf17a..ef5e9f9b5ab2 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -829,8 +829,6 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, { u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ - u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, - SH_MEM_ALIGNMENT_MODE_UNALIGNED); amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); if (vm_id < 8) { @@ -840,31 +838,6 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, } amdgpu_ring_write(ring, pd_addr >> 12); - /* update SH_MEM_* regs */ - amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); - amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); - amdgpu_ring_write(ring, VMID(vm_id)); - - amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); - amdgpu_ring_write(ring, mmSH_MEM_BASES); - amdgpu_ring_write(ring, 0); - - amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); - amdgpu_ring_write(ring, mmSH_MEM_CONFIG); - amdgpu_ring_write(ring, sh_mem_cfg); - - amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); - amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE); - amdgpu_ring_write(ring, 1); - - amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); - amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT); - amdgpu_ring_write(ring, 0); - - amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); - amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); - amdgpu_ring_write(ring, VMID(0)); - /* flush TLB */ amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 0057699cb8fa..58a20be93c14 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -3593,33 +3593,6 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, pd_addr >> 12); - /* update SH_MEM_* regs */ - amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); - amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | - WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); - amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, VMID(vm_id)); - - amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); - amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | - WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, mmSH_MEM_BASES); - amdgpu_ring_write(ring, 0); - - amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */ - amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */ - amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ - amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ - - amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); - amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | - WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); - amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, VMID(0)); - - /* bits 0-15 are the VM contexts0-15 */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index a7d687da10d7..c3aebdffeea1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3800,7 +3800,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); - u32 srbm_gfx_cntl = 0; amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | @@ -3815,35 +3814,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, pd_addr >> 12); - /* update SH_MEM_* regs */ - srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id); - amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); - amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | - WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); - amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, srbm_gfx_cntl); - - amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); - amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | - WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, mmSH_MEM_BASES); - amdgpu_ring_write(ring, 0); - - amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */ - amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */ - amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ - amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ - - srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0); - amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); - amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | - WRITE_DATA_DST_SEL(0))); - amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); - amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, srbm_gfx_cntl); - - /* bits 0-15 are the VM contexts0-15 */ /* invalidate the cache */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 64de8f60e3a5..d09aa7eeb40e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -890,10 +890,6 @@ static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib) static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { - u32 srbm_gfx_cntl = 0; - u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, - SH_MEM_ALIGNMENT_MODE_UNALIGNED); - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); if (vm_id < 8) { @@ -903,40 +899,6 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, } amdgpu_ring_write(ring, pd_addr >> 12); - /* update SH_MEM_* regs */ - srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id); - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); - amdgpu_ring_write(ring, srbm_gfx_cntl); - - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSH_MEM_BASES); - amdgpu_ring_write(ring, 0); - - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSH_MEM_CONFIG); - amdgpu_ring_write(ring, sh_mem_cfg); - - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE); - amdgpu_ring_write(ring, 1); - - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT); - amdgpu_ring_write(ring, 0); - - srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0); - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); - amdgpu_ring_write(ring, srbm_gfx_cntl); - - /* flush TLB */ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index bf3cefc447ca..555c0e1e4c97 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -953,10 +953,6 @@ static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib) static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { - u32 srbm_gfx_cntl = 0; - u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, - SH_MEM_ALIGNMENT_MODE_UNALIGNED); - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); if (vm_id < 8) { @@ -966,40 +962,6 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, } amdgpu_ring_write(ring, pd_addr >> 12); - /* update SH_MEM_* regs */ - srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id); - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); - amdgpu_ring_write(ring, srbm_gfx_cntl); - - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSH_MEM_BASES); - amdgpu_ring_write(ring, 0); - - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSH_MEM_CONFIG); - amdgpu_ring_write(ring, sh_mem_cfg); - - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE); - amdgpu_ring_write(ring, 1); - - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT); - amdgpu_ring_write(ring, 0); - - srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0); - amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | - SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); - amdgpu_ring_write(ring, mmSRBM_GFX_CNTL); - amdgpu_ring_write(ring, srbm_gfx_cntl); - - /* flush TLB */ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); -- cgit v1.2.3 From 8dacc127fcb3b60e6893ec74ee2f615d78dcbc4e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 11 May 2015 16:20:58 -0400 Subject: drm/amdgpu: fix description of vm_size module parameter (v2) default is 8GB, not 4GB. v2: fix fallback setting when the user provides an invalid input Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index d9d26f2e7bd7..175dc67130c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -968,13 +968,13 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", amdgpu_vm_size); - amdgpu_vm_size = 4; + amdgpu_vm_size = 8; } if (amdgpu_vm_size < 1) { dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", amdgpu_vm_size); - amdgpu_vm_size = 4; + amdgpu_vm_size = 8; } /* @@ -983,7 +983,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) if (amdgpu_vm_size > 1024) { dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", amdgpu_vm_size); - amdgpu_vm_size = 4; + amdgpu_vm_size = 8; } /* defines number of bits in page table versus page directory, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6edacceb6cfd..56da962231fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -128,7 +128,7 @@ module_param_named(bapm, amdgpu_bapm, int, 0444); MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); module_param_named(deep_color, amdgpu_deep_color, int, 0444); -MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); +MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 8GB)"); module_param_named(vm_size, amdgpu_vm_size, int, 0444); MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); -- cgit v1.2.3 From e176fe176d3a02d9409e0f36502799083ae13e1b Mon Sep 17 00:00:00 2001 From: Christian König Date: Wed, 27 May 2015 10:22:47 +0200 Subject: drm/amdgpu: remove mclk_lock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not needed any more. Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 40 +++--------------------------- 5 files changed, 4 insertions(+), 43 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 6c8c24ba463d..4300e3d4b1cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1558,8 +1558,6 @@ struct amdgpu_dpm { struct amdgpu_pm { struct mutex mutex; - /* write locked while reprogramming mclk */ - struct rw_semaphore mclk_lock; u32 current_sclk; u32 current_mclk; u32 default_sclk; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 175dc67130c3..36be03ce76c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1401,7 +1401,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->gfx.gpu_clock_mutex); mutex_init(&adev->srbm_mutex); mutex_init(&adev->grbm_idx_mutex); - init_rwsem(&adev->pm.mclk_lock); init_rwsem(&adev->exclusive_lock); mutex_init(&adev->mn_lock); hash_init(adev->mn_hash); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 62cabfb5dff8..7d801e016e31 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -272,11 +272,9 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, bo->flags = flags; amdgpu_fill_placement_to_bo(bo, placement); /* Kernel allocation are uninterruptible */ - down_read(&adev->pm.mclk_lock); r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, &bo->placement, page_align, !kernel, NULL, acc_size, sg, NULL, &amdgpu_ttm_bo_destroy); - up_read(&adev->pm.mclk_lock); if (unlikely(r != 0)) { return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 89782543f854..605a9e42f943 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -581,7 +581,6 @@ force: } mutex_lock(&adev->ddev->struct_mutex); - down_write(&adev->pm.mclk_lock); mutex_lock(&adev->ring_lock); /* update whether vce is active */ @@ -629,7 +628,6 @@ force: done: mutex_unlock(&adev->ring_lock); - up_write(&adev->pm.mclk_lock); mutex_unlock(&adev->ddev->struct_mutex); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 729e0bb3070f..d3706a498293 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -966,52 +966,20 @@ void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size) man->size = size >> PAGE_SHIFT; } -static struct vm_operations_struct amdgpu_ttm_vm_ops; -static const struct vm_operations_struct *ttm_vm_ops = NULL; - -static int amdgpu_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) -{ - struct ttm_buffer_object *bo; - struct amdgpu_device *adev; - int r; - - bo = (struct ttm_buffer_object *)vma->vm_private_data; - if (bo == NULL) { - return VM_FAULT_NOPAGE; - } - adev = amdgpu_get_adev(bo->bdev); - down_read(&adev->pm.mclk_lock); - r = ttm_vm_ops->fault(vma, vmf); - up_read(&adev->pm.mclk_lock); - return r; -} - int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) { struct drm_file *file_priv; struct amdgpu_device *adev; - int r; - if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { + if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) return -EINVAL; - } file_priv = filp->private_data; adev = file_priv->minor->dev->dev_private; - if (adev == NULL) { + if (adev == NULL) return -EINVAL; - } - r = ttm_bo_mmap(filp, vma, &adev->mman.bdev); - if (unlikely(r != 0)) { - return r; - } - if (unlikely(ttm_vm_ops == NULL)) { - ttm_vm_ops = vma->vm_ops; - amdgpu_ttm_vm_ops = *ttm_vm_ops; - amdgpu_ttm_vm_ops.fault = &amdgpu_ttm_fault; - } - vma->vm_ops = &amdgpu_ttm_vm_ops; - return 0; + + return ttm_bo_mmap(filp, vma, &adev->mman.bdev); } int amdgpu_copy_buffer(struct amdgpu_ring *ring, -- cgit v1.2.3 From faad24cf2372794759b40085aeb3a2504f3fa0c2 Mon Sep 17 00:00:00 2001 From: Christian König Date: Thu, 28 May 2015 22:02:26 +0200 Subject: drm/amdgpu: stop loading firmware with pm.mutex locked MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Loading firmware is a rather complicated process, in the end we add a dependency between the pm mutex and the mm semaphore which results in a harmless but annoying error message. Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 03809f1bcfd5..b1a4fbc22e69 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -5839,10 +5839,6 @@ static int ci_dpm_init(struct amdgpu_device *adev) int ret; u32 mask; - ret = ci_dpm_init_microcode(adev); - if (ret) - return ret; - pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); if (pi == NULL) return -ENOMEM; @@ -6224,6 +6220,10 @@ static int ci_dpm_sw_init(void *handle) if (amdgpu_dpm == 0) return 0; + ret = ci_dpm_init_microcode(adev); + if (ret) + return ret; + INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); mutex_lock(&adev->pm.mutex); ret = ci_dpm_init(adev); -- cgit v1.2.3 From 86fa0bdc6fd7b2debc07ce86f1bcd5fb254822e3 Mon Sep 17 00:00:00 2001 From: Christian König Date: Tue, 5 May 2015 16:36:01 +0200 Subject: drm/amdgpu: add HEVC/H.265 UVD support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 375759c8639c..2f7a5efa21c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -460,6 +460,14 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); break; + case 16: /* H265 */ + image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; + image_size = ALIGN(image_size, 256); + + num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; + min_dpb_size = image_size * num_dpb_buffer; + break; + default: DRM_ERROR("UVD codec not handled %d!\n", stream_type); return -EINVAL; -- cgit v1.2.3 From d9b5327ad757164418e8d4e260a343377e99f205 Mon Sep 17 00:00:00 2001 From: "monk.liu" Date: Tue, 2 Jun 2015 15:50:33 +0800 Subject: drm/amdgpu: fix no hdp flush for compute ring MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No pfp on compute. Signed-off-by: monk.liu Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 58a20be93c14..ed2f35de1d4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2376,6 +2376,7 @@ static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask; + int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { switch (ring->me) { @@ -2395,7 +2396,7 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ WAIT_REG_MEM_FUNCTION(3) | /* == */ - WAIT_REG_MEM_ENGINE(1))); /* pfp */ + WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); amdgpu_ring_write(ring, ref_and_mask); @@ -5522,6 +5523,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { .emit_semaphore = gfx_v7_0_ring_emit_semaphore, .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, .test_ring = gfx_v7_0_ring_test_ring, .test_ib = gfx_v7_0_ring_test_ib, .is_lockup = gfx_v7_0_ring_is_lockup, -- cgit v1.2.3 From 35074d2d404049c386e7e70a9e48cf77f1379364 Mon Sep 17 00:00:00 2001 From: "monk.liu" Date: Wed, 3 Jun 2015 16:32:49 +0800 Subject: drm/amdgpu: add hdp flush for gfx8 compute ring MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We had forgotten to register the callback. Signed-off-by: monk.liu Reviewed-by: Christian König Reviewed-by: jammy zhou --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index c3aebdffeea1..ffdba1965029 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4144,6 +4144,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { .emit_semaphore = gfx_v8_0_ring_emit_semaphore, .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, .test_ring = gfx_v8_0_ring_test_ring, .test_ib = gfx_v8_0_ring_test_ib, .is_lockup = gfx_v8_0_ring_is_lockup, -- cgit v1.2.3 From 32bf7106e072b59cade754062ed86023309f50d9 Mon Sep 17 00:00:00 2001 From: Ken Wang Date: Wed, 3 Jun 2015 17:36:54 +0800 Subject: drm/amdgpu add max_memory_clock for interface query (v2) Add a query for the max memory clock. v2: handle the dpm enabled case properly Signed-off-by: Ken Wang Reviewd-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 ++++++-- include/uapi/drm/amdgpu_drm.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index b6dd3751d9a5..3c182b6c5a27 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -414,11 +414,15 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; /* return all clocks in KHz */ dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; - if (adev->pm.dpm_enabled) + if (adev->pm.dpm_enabled) { dev_info.max_engine_clock = adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; - else + dev_info.max_memory_clock = + adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10; + } else { dev_info.max_engine_clock = adev->pm.default_sclk * 10; + dev_info.max_memory_clock = adev->pm.default_mclk * 10; + } dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * adev->gfx.config.max_shader_engines; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index cd54891b1d5c..420c762f2ed7 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -553,6 +553,7 @@ struct drm_amdgpu_info_device { uint32_t num_shader_arrays_per_engine; uint32_t gpu_counter_freq; /* in KHz */ uint64_t max_engine_clock; /* in KHz */ + uint64_t max_memory_clock; /* in KHz */ /* cu information */ uint32_t cu_active_number; uint32_t cu_ao_mask; -- cgit v1.2.3 From a101a8995ab8072125d0bb4d95425c9fb37ff809 Mon Sep 17 00:00:00 2001 From: Ken Wang Date: Wed, 3 Jun 2015 17:47:54 +0800 Subject: drm/amdgpu add ce_ram_size for interface query Add a query for the CE ram size. User mode drivers will want to use this to determine how much size of the cache on the CE. Signed-off-by: Ken Wang Reviewd-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 ++ include/uapi/drm/amdgpu_drm.h | 2 ++ 5 files changed, 9 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 4300e3d4b1cd..6c99b7560a27 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1136,6 +1136,8 @@ struct amdgpu_gfx { uint32_t gfx_current_status; /* sync signal for const engine */ unsigned ce_sync_offs; + /* ce ram size*/ + unsigned ce_ram_size; }; int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 3c182b6c5a27..9ede2446dcd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -441,6 +441,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file amdgpu_asic_get_cu_info(adev, &cu_info); dev_info.cu_active_number = cu_info.number; dev_info.cu_ao_mask = cu_info.ao_cu_mask; + dev_info.ce_ram_size = adev->gfx.ce_ram_size; memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap)); return copy_to_user(out, &dev_info, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index ed2f35de1d4f..faa39b38f0f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4820,6 +4820,8 @@ static int gfx_v7_0_hw_init(void *handle) if (r) return r; + adev->gfx.ce_ram_size = 0x8000; + return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index ffdba1965029..1895de433446 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -895,6 +895,8 @@ static int gfx_v8_0_sw_init(void *handle) if (r) return r; + adev->gfx.ce_ram_size = 0x8000; + return 0; } diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 420c762f2ed7..e24cc2e318df 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -573,6 +573,8 @@ struct drm_amdgpu_info_device { /** Page table entry - fragment size */ uint32_t pte_fragment_size; uint32_t gart_page_size; + /** constant engine ram size*/ + uint32_t ce_ram_size; }; struct drm_amdgpu_info_hw_ip { -- cgit v1.2.3 From 02558a006c0cf92e612c9d6d1c6058ca1a6dbe6a Mon Sep 17 00:00:00 2001 From: Ken Wang Date: Wed, 3 Jun 2015 19:52:06 +0800 Subject: drm/amdgpu: add me/ce/pfp_feature_version interface query Provide this information to usermode drivers. We were previously missing this info. Signed-off-by: Ken Wang Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 +++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 +++ 4 files changed, 12 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 6c99b7560a27..4bdc3265b410 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1125,6 +1125,9 @@ struct amdgpu_gfx { uint32_t mec_fw_version; const struct firmware *mec2_fw; /* MEC2 firmware */ uint32_t mec2_fw_version; + uint32_t me_feature_version; + uint32_t ce_feature_version; + uint32_t pfp_feature_version; struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; unsigned num_gfx_rings; struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 9ede2446dcd6..12b756e8c6b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -291,15 +291,15 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file break; case AMDGPU_INFO_FW_GFX_ME: fw_info.ver = adev->gfx.me_fw_version; - fw_info.feature = 0; + fw_info.feature = adev->gfx.me_feature_version; break; case AMDGPU_INFO_FW_GFX_PFP: fw_info.ver = adev->gfx.pfp_fw_version; - fw_info.feature = 0; + fw_info.feature = adev->gfx.pfp_feature_version; break; case AMDGPU_INFO_FW_GFX_CE: fw_info.ver = adev->gfx.ce_fw_version; - fw_info.feature = 0; + fw_info.feature = adev->gfx.ce_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC: fw_info.ver = adev->gfx.rlc_fw_version; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index faa39b38f0f3..5fefe402e085 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2705,6 +2705,9 @@ static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); + adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); + adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); + adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); gfx_v7_0_cp_gfx_enable(adev, false); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 1895de433446..04b91523008c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -2279,6 +2279,9 @@ static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev) adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); + adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); + adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); + adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); gfx_v8_0_cp_gfx_enable(adev, false); -- cgit v1.2.3 From 71062f435eaf0ff7867a1188e5c7887b0a5871ff Mon Sep 17 00:00:00 2001 From: Ken Wang Date: Thu, 4 Jun 2015 21:26:57 +0800 Subject: drm/amdgpu: add ib_size/start_alignment interface query Query the IB alignment requirements from the kernel rather than hardcoding them in the user mode drivers. Signed-off-by: Ken Wang Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 ++++++++++++++ include/uapi/drm/amdgpu_drm.h | 4 ++++ 2 files changed, 18 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 12b756e8c6b8..f1e5d87ef1f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -188,6 +188,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file struct drm_amdgpu_info_hw_ip ip = {}; enum amd_ip_block_type type; uint32_t ring_mask = 0; + uint32_t ib_start_alignment = 0; + uint32_t ib_size_alignment = 0; if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) return -EINVAL; @@ -197,25 +199,35 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_gfx_rings; i++) ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); + ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; + ib_size_alignment = 8; break; case AMDGPU_HW_IP_COMPUTE: type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_compute_rings; i++) ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); + ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; + ib_size_alignment = 8; break; case AMDGPU_HW_IP_DMA: type = AMD_IP_BLOCK_TYPE_SDMA; ring_mask = adev->sdma[0].ring.ready ? 1 : 0; ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1); + ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; + ib_size_alignment = 1; break; case AMDGPU_HW_IP_UVD: type = AMD_IP_BLOCK_TYPE_UVD; ring_mask = adev->uvd.ring.ready ? 1 : 0; + ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; + ib_size_alignment = 8; break; case AMDGPU_HW_IP_VCE: type = AMD_IP_BLOCK_TYPE_VCE; for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++) ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); + ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; + ib_size_alignment = 8; break; default: return -EINVAL; @@ -228,6 +240,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file ip.hw_ip_version_minor = adev->ip_blocks[i].minor; ip.capabilities_flags = 0; ip.available_rings = ring_mask; + ip.ib_start_alignment = ib_start_alignment; + ip.ib_size_alignment = ib_size_alignment; break; } } diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index e24cc2e318df..3af5bd0e23a8 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -583,6 +583,10 @@ struct drm_amdgpu_info_hw_ip { uint32_t hw_ip_version_minor; /** Capabilities */ uint64_t capabilities_flags; + /** command buffer address start alignment*/ + uint32_t ib_start_alignment; + /** command buffer size alignment*/ + uint32_t ib_size_alignment; /** Bitmask of available rings. Bit 0 means ring 0, etc. */ uint32_t available_rings; uint32_t _pad; -- cgit v1.2.3 From 81c59f54125f9ff84546b6ba26c321662562703d Mon Sep 17 00:00:00 2001 From: Ken Wang Date: Wed, 3 Jun 2015 21:02:01 +0800 Subject: drm/amdgpu: add vram_type and vram_bit_width for interface query (v2) Track the type of vram on the board and provide a query for it. User mode drivers and tools want this information for determining bandwidth information and form informational purposes. v2: fix build when CI support is not enabled Signed-off-by: Ken Wang Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++ drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 12 ++++++------ drivers/gpu/drm/amd/amdgpu/cikd.h | 11 ++++++++--- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 32 +++++++++++++++++++++++++------- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 33 ++++++++++++++++++++++++++------- drivers/gpu/drm/amd/amdgpu/vid.h | 11 ++++++++--- include/uapi/drm/amdgpu_drm.h | 13 +++++++++++++ 8 files changed, 89 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 4bdc3265b410..149b76913091 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -767,7 +767,7 @@ struct amdgpu_mc { const struct firmware *fw; /* MC firmware */ uint32_t fw_version; struct amdgpu_irq_src vm_fault; - bool is_gddr5; + uint32_t vram_type; }; /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index f1e5d87ef1f7..5533434c7a8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -457,6 +457,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file dev_info.cu_ao_mask = cu_info.ao_cu_mask; dev_info.ce_ram_size = adev->gfx.ce_ram_size; memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap)); + dev_info.vram_type = adev->mc.vram_type; + dev_info.vram_bit_width = adev->mc.vram_width; return copy_to_user(out, &dev_info, min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index b1a4fbc22e69..82e8d0730517 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -891,7 +891,7 @@ static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev) { u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); - u32 switch_limit = adev->mc.is_gddr5 ? 450 : 300; + u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300; if (vblank_time < switch_limit) return true; @@ -2920,7 +2920,7 @@ static int ci_calculate_mclk_params(struct amdgpu_device *adev, mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK; mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT); - if (adev->mc.is_gddr5) { + if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK | MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK); mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) | @@ -3043,7 +3043,7 @@ static int ci_populate_single_memory_level(struct amdgpu_device *adev, (memory_clock <= pi->mclk_strobe_mode_threshold)) memory_level->StrobeEnable = 1; - if (adev->mc.is_gddr5) { + if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { memory_level->StrobeRatio = ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); if (pi->mclk_edc_enable_threshold && @@ -3681,7 +3681,7 @@ static int ci_init_smc_table(struct amdgpu_device *adev) if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; - if (adev->mc.is_gddr5) + if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; if (ulv->supported) { @@ -4498,14 +4498,14 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev, for (k = 0; k < table->num_entries; k++) { table->mc_reg_table_entry[k].mc_data[j] = (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); - if (!adev->mc.is_gddr5) + if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) table->mc_reg_table_entry[k].mc_data[j] |= 0x100; } j++; if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) return -EINVAL; - if (!adev->mc.is_gddr5) { + if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) { diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h index 11828e2cdf34..220865a44814 100644 --- a/drivers/gpu/drm/amd/amdgpu/cikd.h +++ b/drivers/gpu/drm/amd/amdgpu/cikd.h @@ -24,9 +24,14 @@ #ifndef CIK_H #define CIK_H -#define MC_SEQ_MISC0__GDDR5__SHIFT 0x1c -#define MC_SEQ_MISC0__GDDR5_MASK 0xf0000000 -#define MC_SEQ_MISC0__GDDR5_VALUE 5 +#define MC_SEQ_MISC0__MT__MASK 0xf0000000 +#define MC_SEQ_MISC0__MT__GDDR1 0x10000000 +#define MC_SEQ_MISC0__MT__DDR2 0x20000000 +#define MC_SEQ_MISC0__MT__GDDR3 0x30000000 +#define MC_SEQ_MISC0__MT__GDDR4 0x40000000 +#define MC_SEQ_MISC0__MT__GDDR5 0x50000000 +#define MC_SEQ_MISC0__MT__HBM 0x60000000 +#define MC_SEQ_MISC0__MT__DDR3 0xB0000000 #define CP_ME_TABLE_SIZE 96 diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 01cd6b207d26..ae37fce36520 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -812,6 +812,28 @@ static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, WREG32(mmHDP_MEM_POWER_LS, data); } +static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) +{ + switch (mc_seq_vram_type) { + case MC_SEQ_MISC0__MT__GDDR1: + return AMDGPU_VRAM_TYPE_GDDR1; + case MC_SEQ_MISC0__MT__DDR2: + return AMDGPU_VRAM_TYPE_DDR2; + case MC_SEQ_MISC0__MT__GDDR3: + return AMDGPU_VRAM_TYPE_GDDR3; + case MC_SEQ_MISC0__MT__GDDR4: + return AMDGPU_VRAM_TYPE_GDDR4; + case MC_SEQ_MISC0__MT__GDDR5: + return AMDGPU_VRAM_TYPE_GDDR5; + case MC_SEQ_MISC0__MT__HBM: + return AMDGPU_VRAM_TYPE_HBM; + case MC_SEQ_MISC0__MT__DDR3: + return AMDGPU_VRAM_TYPE_DDR3; + default: + return AMDGPU_VRAM_TYPE_UNKNOWN; + } +} + static int gmc_v7_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -820,15 +842,11 @@ static int gmc_v7_0_early_init(void *handle) gmc_v7_0_set_irq_funcs(adev); if (adev->flags & AMDGPU_IS_APU) { - adev->mc.is_gddr5 = false; + adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; } else { u32 tmp = RREG32(mmMC_SEQ_MISC0); - - if (((tmp & MC_SEQ_MISC0__GDDR5_MASK) >> - MC_SEQ_MISC0__GDDR5__SHIFT) == MC_SEQ_MISC0__GDDR5_VALUE) - adev->mc.is_gddr5 = true; - else - adev->mc.is_gddr5 = false; + tmp &= MC_SEQ_MISC0__MT__MASK; + adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp); } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 675483a612c2..6206fcd39df9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -38,6 +38,7 @@ #include "vid.h" #include "vi.h" + static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); @@ -786,6 +787,28 @@ static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, "write" : "read", block, mc_client, mc_id); } +static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) +{ + switch (mc_seq_vram_type) { + case MC_SEQ_MISC0__MT__GDDR1: + return AMDGPU_VRAM_TYPE_GDDR1; + case MC_SEQ_MISC0__MT__DDR2: + return AMDGPU_VRAM_TYPE_DDR2; + case MC_SEQ_MISC0__MT__GDDR3: + return AMDGPU_VRAM_TYPE_GDDR3; + case MC_SEQ_MISC0__MT__GDDR4: + return AMDGPU_VRAM_TYPE_GDDR4; + case MC_SEQ_MISC0__MT__GDDR5: + return AMDGPU_VRAM_TYPE_GDDR5; + case MC_SEQ_MISC0__MT__HBM: + return AMDGPU_VRAM_TYPE_HBM; + case MC_SEQ_MISC0__MT__DDR3: + return AMDGPU_VRAM_TYPE_DDR3; + default: + return AMDGPU_VRAM_TYPE_UNKNOWN; + } +} + static int gmc_v8_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -794,15 +817,11 @@ static int gmc_v8_0_early_init(void *handle) gmc_v8_0_set_irq_funcs(adev); if (adev->flags & AMDGPU_IS_APU) { - adev->mc.is_gddr5 = false; + adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; } else { u32 tmp = RREG32(mmMC_SEQ_MISC0); - - if (((tmp & MC_SEQ_MISC0__GDDR5_MASK) >> - MC_SEQ_MISC0__GDDR5__SHIFT) == MC_SEQ_MISC0__GDDR5_VALUE) - adev->mc.is_gddr5 = true; - else - adev->mc.is_gddr5 = false; + tmp &= MC_SEQ_MISC0__MT__MASK; + adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h index 385267c31d11..31bb89452e12 100644 --- a/drivers/gpu/drm/amd/amdgpu/vid.h +++ b/drivers/gpu/drm/amd/amdgpu/vid.h @@ -68,9 +68,14 @@ #define RB_BITMAP_WIDTH_PER_SH 2 -#define MC_SEQ_MISC0__GDDR5__SHIFT 0x1c -#define MC_SEQ_MISC0__GDDR5_MASK 0xf0000000 -#define MC_SEQ_MISC0__GDDR5_VALUE 5 +#define MC_SEQ_MISC0__MT__MASK 0xf0000000 +#define MC_SEQ_MISC0__MT__GDDR1 0x10000000 +#define MC_SEQ_MISC0__MT__DDR2 0x20000000 +#define MC_SEQ_MISC0__MT__GDDR3 0x30000000 +#define MC_SEQ_MISC0__MT__GDDR4 0x40000000 +#define MC_SEQ_MISC0__MT__GDDR5 0x50000000 +#define MC_SEQ_MISC0__MT__HBM 0x60000000 +#define MC_SEQ_MISC0__MT__DDR3 0xB0000000 /* * PM4 diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 3af5bd0e23a8..c90f4f0d059e 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -540,6 +540,15 @@ struct drm_amdgpu_info_firmware { uint32_t feature; }; +#define AMDGPU_VRAM_TYPE_UNKNOWN 0 +#define AMDGPU_VRAM_TYPE_GDDR1 1 +#define AMDGPU_VRAM_TYPE_DDR2 2 +#define AMDGPU_VRAM_TYPE_GDDR3 3 +#define AMDGPU_VRAM_TYPE_GDDR4 4 +#define AMDGPU_VRAM_TYPE_GDDR5 5 +#define AMDGPU_VRAM_TYPE_HBM 6 +#define AMDGPU_VRAM_TYPE_DDR3 7 + struct drm_amdgpu_info_device { /** PCI Device ID */ uint32_t device_id; @@ -575,6 +584,10 @@ struct drm_amdgpu_info_device { uint32_t gart_page_size; /** constant engine ram size*/ uint32_t ce_ram_size; + /** video memory type infro*/ + uint32_t vram_type; + /** video memory bit width*/ + uint32_t vram_bit_width; }; struct drm_amdgpu_info_hw_ip { -- cgit v1.2.3 From 3ccec53c294cbec2af44b6b24f70349637c45428 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Tue, 2 Jun 2015 17:44:49 +0200 Subject: drm/amdgpu: only support IBs in the buffer list (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_cs_find_mapping doesn't work without all buffers being validated, so the TTM validation must be done first. v2: only use amdgpu_cs_find_mapping for UVD/VCE VM emulation Signed-off-by: Marek Olšák Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 95 +++++++++------------------------- include/uapi/drm/amdgpu_drm.h | 6 +-- 3 files changed, 25 insertions(+), 77 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 149b76913091..c33c1af36fa2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1191,7 +1191,6 @@ struct amdgpu_cs_parser { struct amdgpu_cs_chunk *chunks; /* relocations */ struct amdgpu_bo_list_entry *vm_bos; - struct amdgpu_bo_list_entry *ib_bos; struct list_head validated; struct amdgpu_ib *ibs; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index fefa48a59a7d..f6b224a69b3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -230,11 +230,6 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) goto out; } - p->ib_bos = kcalloc(p->num_ibs, sizeof(struct amdgpu_bo_list_entry), - GFP_KERNEL); - if (!p->ib_bos) - r = -ENOMEM; - out: kfree(chunk_array); return r; @@ -373,13 +368,6 @@ static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p) p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm, &p->validated); - for (i = 0; i < p->num_ibs; i++) { - if (!p->ib_bos[i].robj) - continue; - - list_add(&p->ib_bos[i].tv.head, &p->validated); - } - if (need_mmap_lock) down_read(¤t->mm->mmap_sem); @@ -457,15 +445,9 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo for (i = 0; i < parser->nchunks; i++) drm_free_large(parser->chunks[i].kdata); kfree(parser->chunks); - for (i = 0; i < parser->num_ibs; i++) { - struct amdgpu_bo *bo = parser->ib_bos[i].robj; + for (i = 0; i < parser->num_ibs; i++) amdgpu_ib_free(parser->adev, &parser->ibs[i]); - - if (bo) - drm_gem_object_unreference_unlocked(&bo->gem_base); - } kfree(parser->ibs); - kfree(parser->ib_bos); if (parser->uf.bo) drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base); } @@ -505,21 +487,6 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, } } - for (i = 0; i < p->num_ibs; i++) { - bo = p->ib_bos[i].robj; - if (!bo) - continue; - - bo_va = p->ib_bos[i].bo_va; - if (!bo_va) - continue; - - r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); - if (r) - return r; - - amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update); - } return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync); } @@ -581,11 +548,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, struct amdgpu_cs_chunk *chunk; struct amdgpu_ib *ib; struct drm_amdgpu_cs_chunk_ib *chunk_ib; - struct amdgpu_bo_list_entry *ib_bo; struct amdgpu_ring *ring; - struct drm_gem_object *gobj; - struct amdgpu_bo *aobj; - void *kptr; chunk = &parser->chunks[i]; ib = &parser->ibs[j]; @@ -594,66 +557,49 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) continue; - gobj = drm_gem_object_lookup(adev->ddev, parser->filp, chunk_ib->handle); - if (gobj == NULL) - return -ENOENT; - aobj = gem_to_amdgpu_bo(gobj); - r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, chunk_ib->ip_instance, chunk_ib->ring, &ring); - if (r) { - drm_gem_object_unreference_unlocked(gobj); + if (r) return r; - } if (ring->funcs->parse_cs) { - r = amdgpu_bo_reserve(aobj, false); - if (r) { - drm_gem_object_unreference_unlocked(gobj); - return r; + struct amdgpu_bo *aobj = NULL; + void *kptr; + + amdgpu_cs_find_mapping(parser, chunk_ib->va_start, &aobj); + if (!aobj) { + DRM_ERROR("IB va_start is invalid\n"); + return -EINVAL; } + /* the IB should be reserved at this point */ r = amdgpu_bo_kmap(aobj, &kptr); if (r) { - amdgpu_bo_unreserve(aobj); - drm_gem_object_unreference_unlocked(gobj); return r; } r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib); if (r) { DRM_ERROR("Failed to get ib !\n"); - amdgpu_bo_unreserve(aobj); - drm_gem_object_unreference_unlocked(gobj); return r; } memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); amdgpu_bo_kunmap(aobj); - amdgpu_bo_unreserve(aobj); } else { r = amdgpu_ib_get(ring, vm, 0, ib); if (r) { DRM_ERROR("Failed to get ib !\n"); - drm_gem_object_unreference_unlocked(gobj); return r; } ib->gpu_addr = chunk_ib->va_start; } - ib->length_dw = chunk_ib->ib_bytes / 4; + ib->length_dw = chunk_ib->ib_bytes / 4; ib->flags = chunk_ib->flags; ib->ctx = parser->ctx; - - ib_bo = &parser->ib_bos[j]; - ib_bo->robj = aobj; - ib_bo->prefered_domains = aobj->initial_domain; - ib_bo->allowed_domains = aobj->initial_domain; - ib_bo->priority = 0; - ib_bo->tv.bo = &aobj->tbo; - ib_bo->tv.shared = true; j++; } @@ -702,6 +648,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) union drm_amdgpu_cs *cs = data; struct amdgpu_cs_parser parser; int r, i; + bool reserved_buffers = false; down_read(&adev->exclusive_lock); if (!adev->accel_working) { @@ -721,15 +668,21 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return r; } - r = amdgpu_cs_ib_fill(adev, &parser); - if (!r) { - r = amdgpu_cs_parser_relocs(&parser); - if (r && r != -ERESTARTSYS) - DRM_ERROR("Failed to parse relocation %d!\n", r); + r = amdgpu_cs_parser_relocs(&parser); + if (r) { + if (r != -ERESTARTSYS) { + if (r == -ENOMEM) + DRM_ERROR("Not enough memory for command submission!\n"); + else + DRM_ERROR("Failed to process the buffer list %d!\n", r); + } + } else { + reserved_buffers = true; + r = amdgpu_cs_ib_fill(adev, &parser); } if (r) { - amdgpu_cs_parser_fini(&parser, r, false); + amdgpu_cs_parser_fini(&parser, r, reserved_buffers); up_read(&adev->exclusive_lock); r = amdgpu_cs_handle_lockup(adev, r); return r; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index c90f4f0d059e..780a5815fb12 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -378,11 +378,7 @@ union drm_amdgpu_cs { #define AMDGPU_IB_FLAG_PREAMBLE (1<<2) struct drm_amdgpu_cs_chunk_ib { - /** - * Handle of GEM object to be used as IB or 0 if it is already in - * residency list. - */ - uint32_t handle; + uint32_t _pad; uint32_t flags; /* IB Flags */ uint64_t va_start; /* Virtual address to begin IB execution */ uint32_t ib_bytes; /* Size of submission */ -- cgit v1.2.3 From 2fa19535ca6abcbfd1ccc9ef694db52f49f77747 Mon Sep 17 00:00:00 2001 From: Frediano Ziglio Date: Wed, 3 Jun 2015 12:09:09 +0100 Subject: drm/qxl: Do not cause spice-server to clean our objects If objects are moved back from system memory to VRAM (and spice id created again) memory is already initialized so we need to set flag to not clear memory. If you don't do it after a while using desktop many images turns to black or transparents. Signed-off-by: Frediano Ziglio Cc: stable@vger.kernel.org Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_cmd.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_cmd.c b/drivers/gpu/drm/qxl/qxl_cmd.c index 97823644d347..f33251d67914 100644 --- a/drivers/gpu/drm/qxl/qxl_cmd.c +++ b/drivers/gpu/drm/qxl/qxl_cmd.c @@ -505,6 +505,7 @@ int qxl_hw_surface_alloc(struct qxl_device *qdev, cmd = (struct qxl_surface_cmd *)qxl_release_map(qdev, release); cmd->type = QXL_SURFACE_CMD_CREATE; + cmd->flags = QXL_SURF_FLAG_KEEP_DATA; cmd->u.surface_create.format = surf->surf.format; cmd->u.surface_create.width = surf->surf.width; cmd->u.surface_create.height = surf->surf.height; -- cgit v1.2.3 From 8451cc964c1d193b989c41a44e5e77109cc696f8 Mon Sep 17 00:00:00 2001 From: Frediano Ziglio Date: Wed, 3 Jun 2015 12:09:10 +0100 Subject: drm/qxl: Do not leak memory if qxl_release_list_add fails If the function fails reference counter to the object is not decremented causing leaks. This is hard to spot as it happens only on very low memory situations. Signed-off-by: Frediano Ziglio Cc: stable@vger.kernel.org Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_ioctl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c index b110883f8253..7354a4cda59d 100644 --- a/drivers/gpu/drm/qxl/qxl_ioctl.c +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c @@ -122,8 +122,10 @@ static struct qxl_bo *qxlhw_handle_to_bo(struct qxl_device *qdev, qobj = gem_to_qxl_bo(gobj); ret = qxl_release_list_add(release, qobj); - if (ret) + if (ret) { + drm_gem_object_unreference_unlocked(gobj); return NULL; + } return qobj; } -- cgit v1.2.3 From 55cc3df08a2c6a9c9c20b34ba26de0512a750b5e Mon Sep 17 00:00:00 2001 From: Frediano Ziglio Date: Wed, 3 Jun 2015 12:09:11 +0100 Subject: drm/qxl: Fix print statement not using uninitialized variable reloc_info[i] is not still initialized in the print statement. Signed-off-by: Frediano Ziglio Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_ioctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c index 7354a4cda59d..9bf1368bc92c 100644 --- a/drivers/gpu/drm/qxl/qxl_ioctl.c +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c @@ -212,7 +212,7 @@ static int qxl_process_single_command(struct qxl_device *qdev, /* add the bos to the list of bos to validate - need to validate first then process relocs? */ if (reloc.reloc_type != QXL_RELOC_TYPE_BO && reloc.reloc_type != QXL_RELOC_TYPE_SURF) { - DRM_DEBUG("unknown reloc type %d\n", reloc_info[i].type); + DRM_DEBUG("unknown reloc type %d\n", reloc.reloc_type); ret = -EINVAL; goto out_free_bos; -- cgit v1.2.3 From fe2af53baec1b3b64ee343d4e7e6a351e52e3b48 Mon Sep 17 00:00:00 2001 From: Frediano Ziglio Date: Wed, 3 Jun 2015 12:09:12 +0100 Subject: drm/qxl: Avoid double free on error Is we are not able to get source bo object from handle we free destination bo object and call cleanup code however destination object was already inserted in reloc_info array (num_relocs was already incremented) so on cleanup we free destination again. Signed-off-by: Frediano Ziglio Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_ioctl.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c index 9bf1368bc92c..77fcde6f3465 100644 --- a/drivers/gpu/drm/qxl/qxl_ioctl.c +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c @@ -240,8 +240,6 @@ static int qxl_process_single_command(struct qxl_device *qdev, qxlhw_handle_to_bo(qdev, file_priv, reloc.src_handle, release); if (!reloc_info[i].src_bo) { - if (reloc_info[i].dst_bo != cmd_bo) - drm_gem_object_unreference_unlocked(&reloc_info[i].dst_bo->gem_base); ret = -EINVAL; goto out_free_bos; } -- cgit v1.2.3 From c610c7137c02eb9812b4e7871abe5b0642ff58d2 Mon Sep 17 00:00:00 2001 From: Frediano Ziglio Date: Wed, 3 Jun 2015 12:09:13 +0100 Subject: drm/qxl: Handle all errors in qxl_surface_evict Only EBUSY error was handled. This could cause code to believe reserve was successful while it failed. Signed-off-by: Frediano Ziglio Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_cmd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_cmd.c b/drivers/gpu/drm/qxl/qxl_cmd.c index f33251d67914..3d270a4f4fd7 100644 --- a/drivers/gpu/drm/qxl/qxl_cmd.c +++ b/drivers/gpu/drm/qxl/qxl_cmd.c @@ -618,8 +618,8 @@ static int qxl_reap_surf(struct qxl_device *qdev, struct qxl_bo *surf, bool stal int ret; ret = qxl_bo_reserve(surf, false); - if (ret == -EBUSY) - return -EBUSY; + if (ret) + return ret; if (stall) mutex_unlock(&qdev->surf_evict_mutex); @@ -628,9 +628,9 @@ static int qxl_reap_surf(struct qxl_device *qdev, struct qxl_bo *surf, bool stal if (stall) mutex_lock(&qdev->surf_evict_mutex); - if (ret == -EBUSY) { + if (ret) { qxl_bo_unreserve(surf); - return -EBUSY; + return ret; } qxl_surface_evict_locked(qdev, surf, true); -- cgit v1.2.3 From 6ecf5c2b571e47b87568446f86b00838fcd0294d Mon Sep 17 00:00:00 2001 From: Frediano Ziglio Date: Wed, 3 Jun 2015 12:09:14 +0100 Subject: drm/qxl: Fix return for qxl_release_alloc This function return handle to allocated release object which is an int. Signed-off-by: Frediano Ziglio Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_release.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c index d9b25684ac98..6fd8e50e3506 100644 --- a/drivers/gpu/drm/qxl/qxl_release.c +++ b/drivers/gpu/drm/qxl/qxl_release.c @@ -122,7 +122,7 @@ static const struct fence_ops qxl_fence_ops = { .wait = qxl_fence_wait, }; -static uint64_t +static int qxl_release_alloc(struct qxl_device *qdev, int type, struct qxl_release **ret) { -- cgit v1.2.3 From de0b523a5a4c99859513238559d62e0dd4a9a67e Mon Sep 17 00:00:00 2001 From: Frediano Ziglio Date: Wed, 3 Jun 2015 12:09:15 +0100 Subject: drm/qxl: Handle correctly failures in qxl_alloc_relase_reserved Free resources correctly if function fails Signed-off-by: Frediano Ziglio Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_release.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c index 6fd8e50e3506..00604ed173a2 100644 --- a/drivers/gpu/drm/qxl/qxl_release.c +++ b/drivers/gpu/drm/qxl/qxl_release.c @@ -363,6 +363,7 @@ int qxl_alloc_release_reserved(struct qxl_device *qdev, unsigned long size, ret = qxl_release_bo_alloc(qdev, &qdev->current_release_bo[cur_idx]); if (ret) { mutex_unlock(&qdev->release_mutex); + qxl_release_free(qdev, *release); return ret; } } @@ -377,13 +378,17 @@ int qxl_alloc_release_reserved(struct qxl_device *qdev, unsigned long size, mutex_unlock(&qdev->release_mutex); - qxl_release_list_add(*release, bo); + ret = qxl_release_list_add(*release, bo); + qxl_bo_unref(&bo); + if (ret) { + qxl_release_free(qdev, *release); + return ret; + } info = qxl_release_map(qdev, *release); info->id = idr_ret; qxl_release_unmap(qdev, *release, info); - qxl_bo_unref(&bo); return ret; } -- cgit v1.2.3 From 72ec5650a85e8337d6364d16c65dd85a208b7986 Mon Sep 17 00:00:00 2001 From: Frediano Ziglio Date: Wed, 3 Jun 2015 12:09:16 +0100 Subject: drm/qxl: Remove format string errors Enable format string checks for qxl_io_log and remove resulting warnings which could lead to memory errors on different platform or just printing wrong information. Signed-off-by: Frediano Ziglio Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_cmd.c | 2 +- drivers/gpu/drm/qxl/qxl_display.c | 2 +- drivers/gpu/drm/qxl/qxl_drv.h | 2 +- drivers/gpu/drm/qxl/qxl_release.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_cmd.c b/drivers/gpu/drm/qxl/qxl_cmd.c index 3d270a4f4fd7..fdc1833b1af8 100644 --- a/drivers/gpu/drm/qxl/qxl_cmd.c +++ b/drivers/gpu/drm/qxl/qxl_cmd.c @@ -248,7 +248,7 @@ int qxl_garbage_collect(struct qxl_device *qdev) } } - QXL_INFO(qdev, "%s: %lld\n", __func__, i); + QXL_INFO(qdev, "%s: %d\n", __func__, i); return i; } diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index 4a0a8b29b0a1..a8dbb3ef4e3c 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -67,7 +67,7 @@ static int qxl_display_copy_rom_client_monitors_config(struct qxl_device *qdev) crc = crc32(0, (const uint8_t *)&qdev->rom->client_monitors_config, sizeof(qdev->rom->client_monitors_config)); if (crc != qdev->rom->client_monitors_config_crc) { - qxl_io_log(qdev, "crc mismatch: have %X (%d) != %X\n", crc, + qxl_io_log(qdev, "crc mismatch: have %X (%zd) != %X\n", crc, sizeof(qdev->rom->client_monitors_config), qdev->rom->client_monitors_config_crc); return 1; diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h index 7c6cafe21f5f..d8549690801d 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.h +++ b/drivers/gpu/drm/qxl/qxl_drv.h @@ -328,7 +328,7 @@ struct qxl_device { }; /* forward declaration for QXL_INFO_IO */ -void qxl_io_log(struct qxl_device *qdev, const char *fmt, ...); +__printf(2,3) void qxl_io_log(struct qxl_device *qdev, const char *fmt, ...); extern const struct drm_ioctl_desc qxl_ioctls[]; extern int qxl_max_ioctl; diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c index 00604ed173a2..b66ec331c17c 100644 --- a/drivers/gpu/drm/qxl/qxl_release.c +++ b/drivers/gpu/drm/qxl/qxl_release.c @@ -153,7 +153,7 @@ qxl_release_alloc(struct qxl_device *qdev, int type, return handle; } *ret = release; - QXL_INFO(qdev, "allocated release %lld\n", handle); + QXL_INFO(qdev, "allocated release %d\n", handle); release->id = handle; return handle; } -- cgit v1.2.3 From e07154e28cb079562fcc0be6915cb7d4890fdba1 Mon Sep 17 00:00:00 2001 From: Frediano Ziglio Date: Wed, 3 Jun 2015 12:09:17 +0100 Subject: drm/qxl: Move main reference counter to GEM object instead of TTM ones qxl_bo structure has two reference counters, one in the GEM object and another in the TTM object. The GEM object keep a counter to the TTM object so when GEM counter reached zero the TTM counter (using qxl_bo_unref) was decremented. The qxl object is fully freed (both GEM and TTM part are cleaned) when the TTM counter reach zero. One issue was that surface idr structure has no owning on qxl_bo objects however it contains a pointer to qxl_bo object. This caused some nasty race condition for instance qxl_bo object was reaped even after counter was already zero. This patch fix these races moving main counter (the one used by qxl_bo_(un)ref) to GEM object which cleanup routine (qxl_gem_object_free) remove the idr pointer (using qxl_surface_evict) when the counters are still valid. Signed-off-by: Frediano Ziglio Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_gem.c | 10 ++++++++-- drivers/gpu/drm/qxl/qxl_object.c | 11 ++++------- 2 files changed, 12 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_gem.c b/drivers/gpu/drm/qxl/qxl_gem.c index b96f0c9d89b2..d9746e904ef1 100644 --- a/drivers/gpu/drm/qxl/qxl_gem.c +++ b/drivers/gpu/drm/qxl/qxl_gem.c @@ -31,9 +31,15 @@ void qxl_gem_object_free(struct drm_gem_object *gobj) { struct qxl_bo *qobj = gem_to_qxl_bo(gobj); + struct qxl_device *qdev; + struct ttm_buffer_object *tbo; - if (qobj) - qxl_bo_unref(&qobj); + qdev = (struct qxl_device *)gobj->dev->dev_private; + + qxl_surface_evict(qdev, qobj, false); + + tbo = &qobj->tbo; + ttm_bo_unref(&tbo); } int qxl_gem_object_create(struct qxl_device *qdev, int size, diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c index cdeaf08fdc74..6d6f33de48f4 100644 --- a/drivers/gpu/drm/qxl/qxl_object.c +++ b/drivers/gpu/drm/qxl/qxl_object.c @@ -208,19 +208,16 @@ void qxl_bo_kunmap_atomic_page(struct qxl_device *qdev, void qxl_bo_unref(struct qxl_bo **bo) { - struct ttm_buffer_object *tbo; - if ((*bo) == NULL) return; - tbo = &((*bo)->tbo); - ttm_bo_unref(&tbo); - if (tbo == NULL) - *bo = NULL; + + drm_gem_object_unreference_unlocked(&(*bo)->gem_base); + *bo = NULL; } struct qxl_bo *qxl_bo_ref(struct qxl_bo *bo) { - ttm_bo_reference(&bo->tbo); + drm_gem_object_reference(&bo->gem_base); return bo; } -- cgit v1.2.3 From 74d9a6335dceb81a55821ac72daaa8f1c1554a83 Mon Sep 17 00:00:00 2001 From: Frediano Ziglio Date: Wed, 3 Jun 2015 12:09:18 +0100 Subject: drm/qxl: Simplify cleaning qxl processing command In qxlhw_handle_to_bo we incremented counters twice, one time for release object and one for reloc_info. In the main function however reloc_info references was drop much earlier than release so keeping the pointer only on release is safe and make cleaning process easier. Signed-off-by: Frediano Ziglio Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_ioctl.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c index 77fcde6f3465..00106294f21d 100644 --- a/drivers/gpu/drm/qxl/qxl_ioctl.c +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c @@ -122,10 +122,9 @@ static struct qxl_bo *qxlhw_handle_to_bo(struct qxl_device *qdev, qobj = gem_to_qxl_bo(gobj); ret = qxl_release_list_add(release, qobj); - if (ret) { - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_unreference_unlocked(gobj); + if (ret) return NULL; - } return qobj; } @@ -145,7 +144,7 @@ static int qxl_process_single_command(struct qxl_device *qdev, struct qxl_release *release; struct qxl_bo *cmd_bo; void *fb_cmd; - int i, j, ret, num_relocs; + int i, ret, num_relocs; int unwritten; switch (cmd->type) { @@ -269,12 +268,6 @@ static int qxl_process_single_command(struct qxl_device *qdev, qxl_release_fence_buffer_objects(release); out_free_bos: - for (j = 0; j < num_relocs; j++) { - if (reloc_info[j].dst_bo != cmd_bo) - drm_gem_object_unreference_unlocked(&reloc_info[j].dst_bo->gem_base); - if (reloc_info[j].src_bo && reloc_info[j].src_bo != cmd_bo) - drm_gem_object_unreference_unlocked(&reloc_info[j].src_bo->gem_base); - } out_free_release: if (ret) qxl_release_free(qdev, release); -- cgit v1.2.3 From ef1316961048988c6d044a298b5842c8288cc35b Mon Sep 17 00:00:00 2001 From: Frediano Ziglio Date: Wed, 3 Jun 2015 12:09:19 +0100 Subject: drm/qxl: Propagate correctly errors from qxlhw_handle_to_bo This function could return a NULL pointer in case of handle not present and in case of out of memory conditions however caller function always returned EINVAL error hiding a possible ENOMEM. This patch change the function to return the error instead to be able to propagate the error instead of assuming EINVAL. Signed-off-by: Frediano Ziglio Reviewed-by: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/qxl/qxl_ioctl.c | 33 ++++++++++++++------------------- 1 file changed, 14 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c index 00106294f21d..bda5c5f80c24 100644 --- a/drivers/gpu/drm/qxl/qxl_ioctl.c +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c @@ -107,9 +107,9 @@ apply_surf_reloc(struct qxl_device *qdev, struct qxl_reloc_info *info) } /* return holding the reference to this object */ -static struct qxl_bo *qxlhw_handle_to_bo(struct qxl_device *qdev, - struct drm_file *file_priv, uint64_t handle, - struct qxl_release *release) +static int qxlhw_handle_to_bo(struct qxl_device *qdev, + struct drm_file *file_priv, uint64_t handle, + struct qxl_release *release, struct qxl_bo **qbo_p) { struct drm_gem_object *gobj; struct qxl_bo *qobj; @@ -117,16 +117,17 @@ static struct qxl_bo *qxlhw_handle_to_bo(struct qxl_device *qdev, gobj = drm_gem_object_lookup(qdev->ddev, file_priv, handle); if (!gobj) - return NULL; + return -EINVAL; qobj = gem_to_qxl_bo(gobj); ret = qxl_release_list_add(release, qobj); drm_gem_object_unreference_unlocked(gobj); if (ret) - return NULL; + return ret; - return qobj; + *qbo_p = qobj; + return 0; } /* @@ -219,13 +220,10 @@ static int qxl_process_single_command(struct qxl_device *qdev, reloc_info[i].type = reloc.reloc_type; if (reloc.dst_handle) { - reloc_info[i].dst_bo = qxlhw_handle_to_bo(qdev, file_priv, - reloc.dst_handle, release); - if (!reloc_info[i].dst_bo) { - ret = -EINVAL; - reloc_info[i].src_bo = NULL; + ret = qxlhw_handle_to_bo(qdev, file_priv, reloc.dst_handle, release, + &reloc_info[i].dst_bo); + if (ret) goto out_free_bos; - } reloc_info[i].dst_offset = reloc.dst_offset; } else { reloc_info[i].dst_bo = cmd_bo; @@ -234,14 +232,11 @@ static int qxl_process_single_command(struct qxl_device *qdev, num_relocs++; /* reserve and validate the reloc dst bo */ - if (reloc.reloc_type == QXL_RELOC_TYPE_BO || reloc.src_handle > 0) { - reloc_info[i].src_bo = - qxlhw_handle_to_bo(qdev, file_priv, - reloc.src_handle, release); - if (!reloc_info[i].src_bo) { - ret = -EINVAL; + if (reloc.reloc_type == QXL_RELOC_TYPE_BO || reloc.src_handle) { + ret = qxlhw_handle_to_bo(qdev, file_priv, reloc.src_handle, release, + &reloc_info[i].src_bo); + if (ret) goto out_free_bos; - } reloc_info[i].src_offset = reloc.src_offset; } else { reloc_info[i].src_bo = NULL; -- cgit v1.2.3 From bf546f8158e2df2656494a475e6235634121c87c Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Wed, 3 Jun 2015 16:50:19 -0700 Subject: drm/i915/skl: Fix DMC API version in firmware file name 04 is the minor version. API version is ver1. So let's follow same scheme used on published version at 01.org. If really needed the minor version a follow-up updated will be done. But for now we need to move fwd and unblock end users. Signed-off-by: Rodrigo Vivi Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 5cb8cc18994a..bcb41e61877d 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -41,7 +41,7 @@ * be moved to FW_FAILED. */ -#define I915_CSR_SKL "i915/skl_dmc_ver4.bin" +#define I915_CSR_SKL "i915/skl_dmc_ver1.bin" MODULE_FIRMWARE(I915_CSR_SKL); -- cgit v1.2.3 From 6c7e66e617d3cc7eb84ee61deb216dcec4899563 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Thu, 4 Jun 2015 11:04:36 -0700 Subject: drm/bridge: dw-hdmi: Return number of EDID modes The dw_hdmi_connector_get_modes() function accidentally forgets to return the number of modes it added, although it has this information stored in a local variable. Let's fix that. Without this fix, drm_helper_probe_single_connector_modes_merge_bits() could get confused and always call drm_add_modes_noedid(). That's not right. Signed-off-by: Doug Anderson Tested-by: Yakir Yang Signed-off-by: Thierry Reding --- drivers/gpu/drm/bridge/dw_hdmi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c index 594f84c763cf..816d104ca4da 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.c +++ b/drivers/gpu/drm/bridge/dw_hdmi.c @@ -1395,7 +1395,7 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, connector); struct edid *edid; - int ret; + int ret = 0; if (!hdmi->ddc) return 0; @@ -1412,7 +1412,7 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) dev_dbg(hdmi->dev, "failed to get edid\n"); } - return 0; + return ret; } static enum drm_mode_status -- cgit v1.2.3 From dad3c3503462f59c6bec7edfa19dbde1857962c0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2015 18:32:17 +0200 Subject: drm/bridge: ptn3460: Include linux/gpio/consumer.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If GPIOLIB=n and asm-generic/gpio.h is not used: drivers/gpu/drm/bridge/ptn3460.c: In function ‘ptn3460_pre_enable’: drivers/gpu/drm/bridge/ptn3460.c:135: error: implicit declaration of function ‘gpiod_set_value’ drivers/gpu/drm/bridge/ptn3460.c: In function ‘ptn3460_probe’: drivers/gpu/drm/bridge/ptn3460.c:333: error: implicit declaration of function ‘devm_gpiod_get’ drivers/gpu/drm/bridge/ptn3460.c:333: warning: assignment makes pointer from integer without a cast drivers/gpu/drm/bridge/ptn3460.c:340: error: implicit declaration of function ‘gpiod_direction_output’ drivers/gpu/drm/bridge/ptn3460.c:346: warning: assignment makes pointer from integer without a cast Add the missing #include to fix this. Fixes: af478d8823 ("drm/bridge: ptn3460: use gpiod interface") Signed-off-by: Geert Uytterhoeven Cc: David Airlie Cc: dri-devel@lists.freedesktop.org Signed-off-by: Thierry Reding --- drivers/gpu/drm/bridge/ptn3460.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/bridge/ptn3460.c b/drivers/gpu/drm/bridge/ptn3460.c index ee7ba3cecf71..b1e0f0b07833 100644 --- a/drivers/gpu/drm/bridge/ptn3460.c +++ b/drivers/gpu/drm/bridge/ptn3460.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include -- cgit v1.2.3 From dcd43d6483a89210dba8726b3b49a4b3d9efdde7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2015 18:32:18 +0200 Subject: drm/bridge: ps8622: Include linux/gpio/consumer.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If GPIOLIB=n and asm-generic/gpio.h is not used: drivers/gpu/drm/bridge/ps8622.c: In function ‘ps8622_pre_enable’: drivers/gpu/drm/bridge/ps8622.c:368: error: implicit declaration of function ‘gpiod_set_value’ drivers/gpu/drm/bridge/ps8622.c: In function ‘ps8622_probe’: drivers/gpu/drm/bridge/ps8622.c:584: error: implicit declaration of function ‘devm_gpiod_get’ drivers/gpu/drm/bridge/ps8622.c:584: warning: assignment makes pointer from integer without a cast drivers/gpu/drm/bridge/ps8622.c:590: error: implicit declaration of function ‘gpiod_direction_output’ drivers/gpu/drm/bridge/ps8622.c:596: warning: assignment makes pointer from integer without a cast Add the missing #include to fix this. Fixes: f1336e6afb ("drm/bridge: Add I2C based driver for ps8622/ps8625 bridge") Signed-off-by: Geert Uytterhoeven Cc: David Airlie Cc: dri-devel@lists.freedesktop.org Signed-off-by: Thierry Reding --- drivers/gpu/drm/bridge/ps8622.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/bridge/ps8622.c b/drivers/gpu/drm/bridge/ps8622.c index 9534607cbd10..32c4601141de 100644 --- a/drivers/gpu/drm/bridge/ps8622.c +++ b/drivers/gpu/drm/bridge/ps8622.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3 From f3f375cd4e411b66511178be9a1dd0256ae41e77 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 14 Apr 2015 15:15:34 +0200 Subject: drm/bridge: Remove stale ptn3460.h include This header file declares prototypes of functions that are no longer used. Remove this file and all references to it. Signed-off-by: Thierry Reding --- drivers/gpu/drm/bridge/ptn3460.c | 2 -- drivers/gpu/drm/exynos/exynos_dp_core.c | 1 - include/drm/bridge/ptn3460.h | 45 --------------------------------- 3 files changed, 48 deletions(-) delete mode 100644 include/drm/bridge/ptn3460.h (limited to 'drivers') diff --git a/drivers/gpu/drm/bridge/ptn3460.c b/drivers/gpu/drm/bridge/ptn3460.c index b1e0f0b07833..0e081564e70d 100644 --- a/drivers/gpu/drm/bridge/ptn3460.c +++ b/drivers/gpu/drm/bridge/ptn3460.c @@ -24,8 +24,6 @@ #include -#include "bridge/ptn3460.h" - #include "drm_crtc.h" #include "drm_crtc_helper.h" #include "drm_edid.h" diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c index 1dbfba58f909..b178f530391f 100644 --- a/drivers/gpu/drm/exynos/exynos_dp_core.c +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c @@ -29,7 +29,6 @@ #include #include #include -#include #include "exynos_dp_core.h" #include "exynos_drm_fimd.h" diff --git a/include/drm/bridge/ptn3460.h b/include/drm/bridge/ptn3460.h deleted file mode 100644 index b11f8e17e72f..000000000000 --- a/include/drm/bridge/ptn3460.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2013 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DRM_BRIDGE_PTN3460_H_ -#define _DRM_BRIDGE_PTN3460_H_ - -struct drm_device; -struct drm_bridge; -struct drm_encoder; -struct i2c_client; -struct device_node; - -#if defined(CONFIG_DRM_PTN3460) || defined(CONFIG_DRM_PTN3460_MODULE) - -int ptn3460_init(struct drm_device *dev, struct drm_encoder *encoder, - struct i2c_client *client, struct device_node *node); - -void ptn3460_destroy(struct drm_bridge *bridge); - -#else - -static inline int ptn3460_init(struct drm_device *dev, - struct drm_encoder *encoder, struct i2c_client *client, - struct device_node *node) -{ - return 0; -} - -static inline void ptn3460_destroy(struct drm_bridge *bridge) -{ -} - -#endif - -#endif -- cgit v1.2.3 From 1a8f9056f59e019892c4ce192aa435c15cc37a73 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 14 Apr 2015 15:03:26 +0200 Subject: drm/panel: Constify OF match tables Both the Samsung LD9040 and Samsung S6E8AA0 panel drivers are missing a const qualifier for their OF match tables. This data is static and never changes, so can be read-only. Signed-off-by: Thierry Reding --- drivers/gpu/drm/panel/panel-ld9040.c | 2 +- drivers/gpu/drm/panel/panel-s6e8aa0.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/panel/panel-ld9040.c b/drivers/gpu/drm/panel/panel-ld9040.c index 08cf2c588c3d..0ab5b69a4bea 100644 --- a/drivers/gpu/drm/panel/panel-ld9040.c +++ b/drivers/gpu/drm/panel/panel-ld9040.c @@ -367,7 +367,7 @@ static int ld9040_remove(struct spi_device *spi) return 0; } -static struct of_device_id ld9040_of_match[] = { +static const struct of_device_id ld9040_of_match[] = { { .compatible = "samsung,ld9040" }, { } }; diff --git a/drivers/gpu/drm/panel/panel-s6e8aa0.c b/drivers/gpu/drm/panel/panel-s6e8aa0.c index 144b2733e3d7..30051108eec4 100644 --- a/drivers/gpu/drm/panel/panel-s6e8aa0.c +++ b/drivers/gpu/drm/panel/panel-s6e8aa0.c @@ -1041,7 +1041,7 @@ static int s6e8aa0_remove(struct mipi_dsi_device *dsi) return 0; } -static struct of_device_id s6e8aa0_of_match[] = { +static const struct of_device_id s6e8aa0_of_match[] = { { .compatible = "samsung,s6e8aa0" }, { } }; -- cgit v1.2.3 From 6343f22f8255f7b77beade7c3fcb9d89d33084c7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 14 Apr 2015 15:07:38 +0200 Subject: drm/panel: ld9040: Remove useless padding There's some useless padding in the struct spi_driver definition. Remove it since it serves no useful purpose. Signed-off-by: Thierry Reding --- drivers/gpu/drm/panel/panel-ld9040.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/panel/panel-ld9040.c b/drivers/gpu/drm/panel/panel-ld9040.c index 0ab5b69a4bea..9c27bded4c09 100644 --- a/drivers/gpu/drm/panel/panel-ld9040.c +++ b/drivers/gpu/drm/panel/panel-ld9040.c @@ -374,11 +374,11 @@ static const struct of_device_id ld9040_of_match[] = { MODULE_DEVICE_TABLE(of, ld9040_of_match); static struct spi_driver ld9040_driver = { - .probe = ld9040_probe, - .remove = ld9040_remove, + .probe = ld9040_probe, + .remove = ld9040_remove, .driver = { - .name = "ld9040", - .owner = THIS_MODULE, + .name = "ld9040", + .owner = THIS_MODULE, .of_match_table = ld9040_of_match, }, }; -- cgit v1.2.3 From 25f45e633892a45df2edbfd4a5dbbfc70e32487b Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Thu, 4 Jun 2015 12:18:27 +0800 Subject: drm/amdgpu: add zero timeout check in amdgpu_fence_wait_seq_timeout Signed-off-by: Jack Xiao Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 9ce6023a4261..48ca637c5029 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -522,6 +522,10 @@ long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev, u64 *target_seq, bool signaled; int i, r; + if (timeout == 0) { + return amdgpu_fence_any_seq_signaled(adev, target_seq); + } + while (!amdgpu_fence_any_seq_signaled(adev, target_seq)) { /* Save current sequence values, used to check for GPU lockups */ -- cgit v1.2.3 From 9298e52f8b51d1e4acd68f502832f3a97f8cf892 Mon Sep 17 00:00:00 2001 From: Christian König Date: Wed, 3 Jun 2015 21:31:20 +0200 Subject: drm/amdgpu: fix user ptr race condition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: monk liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index ad5b9c676fd8..e8409fea4bf1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -37,6 +37,7 @@ void amdgpu_gem_object_free(struct drm_gem_object *gobj) if (robj) { if (robj->gem_base.import_attach) drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); + amdgpu_mn_unregister(robj); amdgpu_bo_unref(&robj); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 7d801e016e31..8da64245b31b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -95,7 +95,6 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) bo = container_of(tbo, struct amdgpu_bo, tbo); amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL); - amdgpu_mn_unregister(bo); mutex_lock(&bo->adev->gem.mutex); list_del_init(&bo->list); -- cgit v1.2.3 From 890ee23fc60193d7c2bca17e099569f1510b3053 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Mon, 1 Jun 2015 14:35:03 +0800 Subject: drm/amdgpu: disable user fence interrupt (v2) amdgpu submits both kernel and user fences, but just need one interrupt, disable user fence interrupt and don't effect user fence. v2: fix merge error Signed-off-by: Chunming Zhou Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 2 +- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 13 +++++++++---- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++---- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- 13 files changed, 46 insertions(+), 26 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c33c1af36fa2..37aeed7b454d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -317,7 +317,7 @@ struct amdgpu_ring_funcs { void (*emit_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, - uint64_t seq, bool write64bit); + uint64_t seq, unsigned flags); bool (*emit_semaphore)(struct amdgpu_ring *ring, struct amdgpu_semaphore *semaphore, bool emit_wait); @@ -392,6 +392,9 @@ struct amdgpu_fence_driver { #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul) +#define AMDGPU_FENCE_FLAG_64BIT (1 << 0) +#define AMDGPU_FENCE_FLAG_INT (1 << 1) + struct amdgpu_fence { struct fence base; @@ -2142,7 +2145,7 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) -#define amdgpu_ring_emit_fence(r, addr, seq, write64bit) (r)->funcs->emit_fence((r), (addr), (seq), (write64bit)) +#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 48ca637c5029..5c9918d01bf9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -128,7 +128,9 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, fence_init(&(*fence)->base, &amdgpu_fence_ops, &adev->fence_queue.lock, adev->fence_context + ring->idx, (*fence)->seq); - amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, (*fence)->seq, false); + amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, + (*fence)->seq, + AMDGPU_FENCE_FLAG_INT); trace_amdgpu_fence_emit(ring->adev->ddev, ring->idx, (*fence)->seq); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 560c5fd347be..52dff75aac6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -216,7 +216,8 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, if (ib->user) { uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); addr += ib->user->offset; - amdgpu_ring_emit_fence(ring, addr, ib->fence->seq, true); + amdgpu_ring_emit_fence(ring, addr, ib->fence->seq, + AMDGPU_FENCE_FLAG_64BIT); } if (ib->vm) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 62018b37273e..1127a504f118 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -637,9 +637,9 @@ void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) * */ void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, - bool write64bits) + unsigned flags) { - WARN_ON(write64bits); + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); amdgpu_ring_write(ring, VCE_CMD_FENCE); amdgpu_ring_write(ring, addr); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index 4294854912e7..b6a9d0956c60 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -40,7 +40,7 @@ bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring, bool emit_wait); void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, - bool write64bit); + unsigned flags); int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring); int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring); diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index ef5e9f9b5ab2..fb931638a7e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -259,8 +259,9 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) * an interrupt if needed (CIK). */ static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, - bool write64bit) + unsigned flags) { + bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; /* write the fence */ amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); amdgpu_ring_write(ring, lower_32_bits(addr)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 5fefe402e085..afa703c0efeb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2414,8 +2414,10 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) * GPU caches. */ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, - u64 seq, bool write64bit) + u64 seq, unsigned flags) { + bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; + bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; /* Workaround for cache flush problems. First send a dummy EOP * event down the pipe with seq one below. */ @@ -2438,7 +2440,7 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, EVENT_INDEX(5))); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | - DATA_SEL(write64bit ? 2 : 1) | INT_SEL(2)); + DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); amdgpu_ring_write(ring, lower_32_bits(seq)); amdgpu_ring_write(ring, upper_32_bits(seq)); } @@ -2454,15 +2456,18 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, */ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, u64 addr, u64 seq, - bool write64bits) + unsigned flags) { + bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; + bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; + /* RELEASE_MEM - flush caches, send int */ amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5))); - amdgpu_ring_write(ring, DATA_SEL(write64bits ? 2 : 1) | INT_SEL(2)); + amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, upper_32_bits(addr)); amdgpu_ring_write(ring, lower_32_bits(seq)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 04b91523008c..6ae2d6be126a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3713,8 +3713,11 @@ static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring, } static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, - u64 seq, bool write64bit) + u64 seq, unsigned flags) { + bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; + bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; + /* EVENT_WRITE_EOP - flush caches, send int */ amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | @@ -3723,7 +3726,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, EVENT_INDEX(5))); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | - DATA_SEL(write64bit ? 2 : 1) | INT_SEL(2)); + DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); amdgpu_ring_write(ring, lower_32_bits(seq)); amdgpu_ring_write(ring, upper_32_bits(seq)); } @@ -3880,15 +3883,18 @@ static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring) static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, u64 addr, u64 seq, - bool write64bits) + unsigned flags) { + bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; + bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; + /* RELEASE_MEM - flush caches, send int */ amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5))); - amdgpu_ring_write(ring, DATA_SEL(write64bits ? 2 : 1) | INT_SEL(2)); + amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, upper_32_bits(addr)); amdgpu_ring_write(ring, lower_32_bits(seq)); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index d09aa7eeb40e..d7895885fe0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -292,8 +292,9 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) * an interrupt if needed (VI). */ static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, - bool write64bits) + unsigned flags) { + bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; /* write the fence */ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); amdgpu_ring_write(ring, lower_32_bits(addr)); @@ -301,7 +302,7 @@ static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se amdgpu_ring_write(ring, lower_32_bits(seq)); /* optionally write high bits as well */ - if (write64bits) { + if (write64bit) { addr += 4; amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); amdgpu_ring_write(ring, lower_32_bits(addr)); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 555c0e1e4c97..e3c1fde75363 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -347,8 +347,9 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) * an interrupt if needed (VI). */ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, - bool write64bits) + unsigned flags) { + bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; /* write the fence */ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); amdgpu_ring_write(ring, lower_32_bits(addr)); @@ -356,7 +357,7 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se amdgpu_ring_write(ring, lower_32_bits(seq)); /* optionally write high bits as well */ - if (write64bits) { + if (write64bit) { addr += 4; amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); amdgpu_ring_write(ring, lower_32_bits(addr)); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 292932a73c81..4efd671d7a9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -417,9 +417,9 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev) * Write a fence and a trap command to the ring. */ static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, - bool write64bit) + unsigned flags) { - WARN_ON(write64bit); + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); amdgpu_ring_write(ring, seq); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 004c56496fc4..b756bd99c0fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -461,9 +461,9 @@ static void uvd_v5_0_stop(struct amdgpu_device *adev) * Write a fence and a trap command to the ring. */ static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, - bool write64bit) + unsigned flags) { - WARN_ON(write64bit); + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); amdgpu_ring_write(ring, seq); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 8c790fb31e2f..49aa931b2cb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -457,9 +457,9 @@ static void uvd_v6_0_stop(struct amdgpu_device *adev) * Write a fence and a trap command to the ring. */ static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, - bool write64bit) + unsigned flags) { - WARN_ON(write64bit); + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); amdgpu_ring_write(ring, seq); -- cgit v1.2.3 From f4e04022edaec32af39db16e08ea316a6bb136f2 Mon Sep 17 00:00:00 2001 From: Valentin Rothberg Date: Fri, 5 Jun 2015 10:27:43 +0200 Subject: drm/amdkfd: avoid CONFIG_ prefix for non-Kconfig symbols The CONFIG_ prefix is reserved for Kconfig options in Make and CPP syntax. Various static analysis tools rely on this naming convention and check if CONFIG_ prefixed symbols are defined Kconfig. Hence add yet another prefix AMD_ to CONFIG_REG_{BASE,END,SISE} to apply to this convention and make static analysis tools happy. Signed-off-by: Valentin Rothberg Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c | 10 +++++----- drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h | 6 +++--- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c index 96153f28d73f..c34c393e9aea 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c @@ -445,7 +445,7 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, aw_reg_add_dword /= sizeof(uint32_t); packets_vec[0].bitfields2.reg_offset = - aw_reg_add_dword - CONFIG_REG_BASE; + aw_reg_add_dword - AMD_CONFIG_REG_BASE; packets_vec[0].reg_data[0] = cntl.u32All; @@ -458,7 +458,7 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, aw_reg_add_dword /= sizeof(uint32_t); packets_vec[1].bitfields2.reg_offset = - aw_reg_add_dword - CONFIG_REG_BASE; + aw_reg_add_dword - AMD_CONFIG_REG_BASE; packets_vec[1].reg_data[0] = addrHi.u32All; aw_reg_add_dword = @@ -470,7 +470,7 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, aw_reg_add_dword /= sizeof(uint32_t); packets_vec[2].bitfields2.reg_offset = - aw_reg_add_dword - CONFIG_REG_BASE; + aw_reg_add_dword - AMD_CONFIG_REG_BASE; packets_vec[2].reg_data[0] = addrLo.u32All; /* enable watch flag if address is not zero*/ @@ -488,7 +488,7 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, aw_reg_add_dword /= sizeof(uint32_t); packets_vec[3].bitfields2.reg_offset = - aw_reg_add_dword - CONFIG_REG_BASE; + aw_reg_add_dword - AMD_CONFIG_REG_BASE; packets_vec[3].reg_data[0] = cntl.u32All; status = dbgdev_diq_submit_ib( @@ -690,7 +690,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev, packets_vec[1].header.opcode = IT_SET_CONFIG_REG; packets_vec[1].header.type = PM4_TYPE_3; packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) - - CONFIG_REG_BASE; + AMD_CONFIG_REG_BASE; packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET; packets_vec[1].bitfields2.insert_vmid = 1; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h index 4b0dd5aa5306..03424c20920c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h @@ -48,9 +48,9 @@ enum { /* CONFIG reg space definition */ enum { - CONFIG_REG_BASE = 0x2000, /* in dwords */ - CONFIG_REG_END = 0x2B00, - CONFIG_REG_SIZE = CONFIG_REG_END - CONFIG_REG_BASE + AMD_CONFIG_REG_BASE = 0x2000, /* in dwords */ + AMD_CONFIG_REG_END = 0x2B00, + AMD_CONFIG_REG_SIZE = AMD_CONFIG_REG_END - AMD_CONFIG_REG_BASE }; /* SH reg space definition */ -- cgit v1.2.3 From 6235e15ea6d0f39ef72ecaf9d3add995550c60ee Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Thu, 30 Apr 2015 18:05:36 +0300 Subject: drm/amdkfd: add debug print to kfd_events.c Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 3cb37d220f60..b6e28dcaea1d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -313,6 +313,10 @@ static int create_signal_event(struct file *devkfd, p->signal_event_count, ev->event_id, ev->user_signal_address); + pr_debug("signal event number %zu created with id %d, address %p\n", + p->signal_event_count, ev->event_id, + ev->user_signal_address); + return 0; } -- cgit v1.2.3 From a82918f18a846e4e2be8613029d03c3cb3e99460 Mon Sep 17 00:00:00 2001 From: Ben Goz Date: Wed, 25 Mar 2015 13:12:20 +0200 Subject: drm/amdkfd: make reset wavefronts per process per device This commit moves the reset wavefront flag to per process per device data structure, so we can support multiple devices. Signed-off-by: Ben Goz Signed-off-by: Oded Gabbay --- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 7 ++++--- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 10 +++++----- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 21 ++++++++++++++++----- 3 files changed, 25 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 547b0a589693..4bb7f4223762 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -946,7 +946,7 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, { int retval; enum kfd_preempt_type_filter preempt_type; - struct kfd_process *p; + struct kfd_process_device *pdd; BUG_ON(!dqm); @@ -981,8 +981,9 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED, QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS); if (retval != 0) { - p = kfd_get_process(current); - p->reset_wavefronts = true; + pdd = kfd_get_process_device_data(dqm->dev, + kfd_get_process(current)); + pdd->reset_wavefronts = true; goto out; } pm_release_ib(&dqm->packets); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index cb79046e5c80..d0d5f4baf72d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -463,6 +463,11 @@ struct kfd_process_device { /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */ bool bound; + + /* This flag tells if we should reset all + * wavefronts on process termination + */ + bool reset_wavefronts; }; #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) @@ -519,11 +524,6 @@ struct kfd_process { event_pages */ u32 next_nonsignal_event_id; size_t signal_event_count; - /* - * This flag tells if we should reset all wavefronts on - * process termination - */ - bool reset_wavefronts; }; /** diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 56b904f5bdb1..8a1f999daa24 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -173,7 +173,7 @@ static void kfd_process_wq_release(struct work_struct *work) pr_debug("Releasing pdd (topology id %d) for process (pasid %d) in workqueue\n", pdd->dev->id, p->pasid); - if (p->reset_wavefronts) + if (pdd->reset_wavefronts) dbgdev_wave_reset_wavefronts(pdd->dev, p); amd_iommu_unbind_pasid(pdd->dev->pdev, p->pasid); @@ -222,6 +222,7 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, struct mm_struct *mm) { struct kfd_process *p; + struct kfd_process_device *pdd = NULL; /* * The kfd_process structure can not be free because the @@ -240,6 +241,15 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, /* In case our notifier is called before IOMMU notifier */ pqm_uninit(&p->pqm); + /* Iterate over all process device data structure and check + * if we should reset all wavefronts */ + list_for_each_entry(pdd, &p->per_device_data, per_device_list) + if (pdd->reset_wavefronts) { + pr_warn("amdkfd: Resetting all wave fronts\n"); + dbgdev_wave_reset_wavefronts(pdd->dev, p); + pdd->reset_wavefronts = false; + } + mutex_unlock(&p->mutex); /* @@ -305,8 +315,6 @@ static struct kfd_process *create_process(const struct task_struct *thread) if (kfd_init_apertures(process) != 0) goto err_init_apretures; - process->reset_wavefronts = false; - return process; err_init_apretures: @@ -348,6 +356,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev, INIT_LIST_HEAD(&pdd->qpd.queues_list); INIT_LIST_HEAD(&pdd->qpd.priv_queue_list); pdd->qpd.dqm = dev->dqm; + pdd->reset_wavefronts = false; list_add(&pdd->per_device_list, &p->per_device_data); } @@ -409,10 +418,12 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid) kfd_dbgmgr_destroy(dev->dbgmgr); pqm_uninit(&p->pqm); - if (p->reset_wavefronts) - dbgdev_wave_reset_wavefronts(dev, p); pdd = kfd_get_process_device_data(dev, p); + if (pdd->reset_wavefronts) { + dbgdev_wave_reset_wavefronts(pdd->dev, p); + pdd->reset_wavefronts = false; + } /* * Just mark pdd as unbound, because we still need it to call -- cgit v1.2.3 From eaccd6e7436340c7aba122f4456c6761c8c2dff2 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Sat, 6 Jun 2015 21:45:43 +0300 Subject: drm/amdkfd: Add missing properties to CZ device info This patch adds two missing properties initializations to the device info structure of CZ. As we don't have CZ support yet, it isn't critical, but its important to fix this now instead of forgetting about it later. Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 1d1e2e952a79..75312c82969f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -44,7 +44,10 @@ static const struct kfd_device_info kaveri_device_info = { static const struct kfd_device_info carrizo_device_info = { .asic_family = CHIP_CARRIZO, .max_pasid_bits = 16, + /* max num of queues for CZ.TODO should be a dynamic value */ + .max_no_of_hqd = 24, .ih_ring_entry_size = 4 * sizeof(uint32_t), + .event_interrupt_class = &event_interrupt_class_cik, .num_of_watch_points = 4, .mqd_size_aligned = MQD_SIZE_ALIGNED }; -- cgit v1.2.3 From da73b9fb56c14c6d537738e891906006a7960535 Mon Sep 17 00:00:00 2001 From: Oded Gabbay Date: Sat, 6 Jun 2015 22:17:44 +0300 Subject: drm/amdkfd: remove not used defines from cik_regs.h Signed-off-by: Oded Gabbay --- drivers/gpu/drm/amd/amdkfd/cik_regs.h | 177 +++------------------------------- 1 file changed, 13 insertions(+), 164 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdkfd/cik_regs.h b/drivers/gpu/drm/amd/amdkfd/cik_regs.h index 01ff332fabd4..183be5b8414f 100644 --- a/drivers/gpu/drm/amd/amdkfd/cik_regs.h +++ b/drivers/gpu/drm/amd/amdkfd/cik_regs.h @@ -23,33 +23,11 @@ #ifndef CIK_REGS_H #define CIK_REGS_H -#define IH_VMID_0_LUT 0x3D40u - -#define BIF_DOORBELL_CNTL 0x530Cu - -#define SRBM_GFX_CNTL 0xE44 -#define PIPEID(x) ((x) << 0) -#define MEID(x) ((x) << 2) -#define VMID(x) ((x) << 4) -#define QUEUEID(x) ((x) << 8) - -#define SQ_CONFIG 0x8C00 - -#define SH_MEM_BASES 0x8C28 /* if PTR32, these are the bases for scratch and lds */ #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ #define SHARED_BASE(x) ((x) << 16) /* LDS */ -#define SH_MEM_APE1_BASE 0x8C2C -/* if PTR32, this is the base location of GPUVM */ -#define SH_MEM_APE1_LIMIT 0x8C30 -/* if PTR32, this is the upper limit of GPUVM */ -#define SH_MEM_CONFIG 0x8C34 #define PTR32 (1 << 0) -#define PRIVATE_ATC (1 << 1) #define ALIGNMENT_MODE(x) ((x) << 2) -#define SH_MEM_ALIGNMENT_MODE_DWORD 0 -#define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 -#define SH_MEM_ALIGNMENT_MODE_STRICT 2 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 #define DEFAULT_MTYPE(x) ((x) << 4) #define APE1_MTYPE(x) ((x) << 7) @@ -58,137 +36,34 @@ #define MTYPE_CACHED 0 #define MTYPE_NONCACHED 3 - -#define SH_STATIC_MEM_CONFIG 0x9604u - -#define TC_CFG_L1_LOAD_POLICY0 0xAC68 -#define TC_CFG_L1_LOAD_POLICY1 0xAC6C -#define TC_CFG_L1_STORE_POLICY 0xAC70 -#define TC_CFG_L2_LOAD_POLICY0 0xAC74 -#define TC_CFG_L2_LOAD_POLICY1 0xAC78 -#define TC_CFG_L2_STORE_POLICY0 0xAC7C -#define TC_CFG_L2_STORE_POLICY1 0xAC80 -#define TC_CFG_L2_ATOMIC_POLICY 0xAC84 -#define TC_CFG_L1_VOLATILE 0xAC88 -#define TC_CFG_L2_VOLATILE 0xAC8C - -#define CP_PQ_WPTR_POLL_CNTL 0xC20C -#define WPTR_POLL_EN (1 << 31) - -#define CPC_INT_CNTL 0xC2D0 -#define CP_ME1_PIPE0_INT_CNTL 0xC214 -#define CP_ME1_PIPE1_INT_CNTL 0xC218 -#define CP_ME1_PIPE2_INT_CNTL 0xC21C -#define CP_ME1_PIPE3_INT_CNTL 0xC220 -#define CP_ME2_PIPE0_INT_CNTL 0xC224 -#define CP_ME2_PIPE1_INT_CNTL 0xC228 -#define CP_ME2_PIPE2_INT_CNTL 0xC22C -#define CP_ME2_PIPE3_INT_CNTL 0xC230 -#define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) -#define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) -#define PRIV_REG_INT_ENABLE (1 << 23) -#define TIME_STAMP_INT_ENABLE (1 << 26) -#define GENERIC2_INT_ENABLE (1 << 29) -#define GENERIC1_INT_ENABLE (1 << 30) -#define GENERIC0_INT_ENABLE (1 << 31) -#define CP_ME1_PIPE0_INT_STATUS 0xC214 -#define CP_ME1_PIPE1_INT_STATUS 0xC218 -#define CP_ME1_PIPE2_INT_STATUS 0xC21C -#define CP_ME1_PIPE3_INT_STATUS 0xC220 -#define CP_ME2_PIPE0_INT_STATUS 0xC224 -#define CP_ME2_PIPE1_INT_STATUS 0xC228 -#define CP_ME2_PIPE2_INT_STATUS 0xC22C -#define CP_ME2_PIPE3_INT_STATUS 0xC230 -#define DEQUEUE_REQUEST_INT_STATUS (1 << 13) -#define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) -#define PRIV_REG_INT_STATUS (1 << 23) -#define TIME_STAMP_INT_STATUS (1 << 26) -#define GENERIC2_INT_STATUS (1 << 29) -#define GENERIC1_INT_STATUS (1 << 30) -#define GENERIC0_INT_STATUS (1 << 31) - -#define CP_HPD_EOP_BASE_ADDR 0xC904 -#define CP_HPD_EOP_BASE_ADDR_HI 0xC908 -#define CP_HPD_EOP_VMID 0xC90C -#define CP_HPD_EOP_CONTROL 0xC910 -#define EOP_SIZE(x) ((x) << 0) -#define EOP_SIZE_MASK (0x3f << 0) -#define CP_MQD_BASE_ADDR 0xC914 -#define CP_MQD_BASE_ADDR_HI 0xC918 -#define CP_HQD_ACTIVE 0xC91C -#define CP_HQD_VMID 0xC920 - -#define CP_HQD_PERSISTENT_STATE 0xC924u #define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8) #define PRELOAD_REQ (1 << 0) -#define CP_HQD_PIPE_PRIORITY 0xC928u -#define CP_HQD_QUEUE_PRIORITY 0xC92Cu -#define CP_HQD_QUANTUM 0xC930u +#define MQD_CONTROL_PRIV_STATE_EN (1U << 8) + +#define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20) + +#define IB_ATC_EN (1U << 23) + #define QUANTUM_EN 1U #define QUANTUM_SCALE_1MS (1U << 4) #define QUANTUM_DURATION(x) ((x) << 8) -#define CP_HQD_PQ_BASE 0xC934 -#define CP_HQD_PQ_BASE_HI 0xC938 -#define CP_HQD_PQ_RPTR 0xC93C -#define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 -#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 -#define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 -#define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C -#define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 -#define DOORBELL_OFFSET(x) ((x) << 2) -#define DOORBELL_OFFSET_MASK (0x1fffff << 2) -#define DOORBELL_SOURCE (1 << 28) -#define DOORBELL_SCHD_HIT (1 << 29) -#define DOORBELL_EN (1 << 30) -#define DOORBELL_HIT (1 << 31) -#define CP_HQD_PQ_WPTR 0xC954 -#define CP_HQD_PQ_CONTROL 0xC958 -#define QUEUE_SIZE(x) ((x) << 0) -#define QUEUE_SIZE_MASK (0x3f << 0) #define RPTR_BLOCK_SIZE(x) ((x) << 8) -#define RPTR_BLOCK_SIZE_MASK (0x3f << 8) #define MIN_AVAIL_SIZE(x) ((x) << 20) -#define PQ_ATC_EN (1 << 23) -#define PQ_VOLATILE (1 << 26) -#define NO_UPDATE_RPTR (1 << 27) -#define UNORD_DISPATCH (1 << 28) -#define ROQ_PQ_IB_FLIP (1 << 29) -#define PRIV_STATE (1 << 30) -#define KMD_QUEUE (1 << 31) - #define DEFAULT_RPTR_BLOCK_SIZE RPTR_BLOCK_SIZE(5) #define DEFAULT_MIN_AVAIL_SIZE MIN_AVAIL_SIZE(3) -#define CP_HQD_IB_BASE_ADDR 0xC95Cu -#define CP_HQD_IB_BASE_ADDR_HI 0xC960u -#define CP_HQD_IB_RPTR 0xC964u -#define CP_HQD_IB_CONTROL 0xC968u -#define IB_ATC_EN (1U << 23) -#define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20) - -#define AQL_ENABLE 1 - -#define CP_HQD_DEQUEUE_REQUEST 0xC974 -#define DEQUEUE_REQUEST_DRAIN 1 -#define DEQUEUE_REQUEST_RESET 2 -#define DEQUEUE_INT (1U << 8) +#define PQ_ATC_EN (1 << 23) +#define NO_UPDATE_RPTR (1 << 27) -#define CP_HQD_SEMA_CMD 0xC97Cu -#define CP_HQD_MSG_TYPE 0xC980u -#define CP_HQD_ATOMIC0_PREOP_LO 0xC984u -#define CP_HQD_ATOMIC0_PREOP_HI 0xC988u -#define CP_HQD_ATOMIC1_PREOP_LO 0xC98Cu -#define CP_HQD_ATOMIC1_PREOP_HI 0xC990u -#define CP_HQD_HQ_SCHEDULER0 0xC994u -#define CP_HQD_HQ_SCHEDULER1 0xC998u +#define DOORBELL_OFFSET(x) ((x) << 2) +#define DOORBELL_EN (1 << 30) +#define PRIV_STATE (1 << 30) +#define KMD_QUEUE (1 << 31) -#define CP_MQD_CONTROL 0xC99C -#define MQD_VMID(x) ((x) << 0) -#define MQD_VMID_MASK (0xf << 0) -#define MQD_CONTROL_PRIV_STATE_EN (1U << 8) +#define AQL_ENABLE 1 #define SDMA_RB_VMID(x) (x << 24) #define SDMA_RB_ENABLE (1 << 0) @@ -202,33 +77,7 @@ #define SDMA_VA_SHARED_BASE(x) (x << 8) #define GRBM_GFX_INDEX 0x30800 -#define INSTANCE_INDEX(x) ((x) << 0) -#define SH_INDEX(x) ((x) << 8) -#define SE_INDEX(x) ((x) << 16) -#define SH_BROADCAST_WRITES (1 << 29) -#define INSTANCE_BROADCAST_WRITES (1 << 30) -#define SE_BROADCAST_WRITES (1 << 31) - -#define SQC_CACHES 0x30d20 -#define SQC_POLICY 0x8C38u -#define SQC_VOLATILE 0x8C3Cu -#define CP_PERFMON_CNTL 0x36020 - -#define ATC_VMID0_PASID_MAPPING 0x339Cu -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u #define ATC_VMID_PASID_MAPPING_VALID (1U << 31) -#define ATC_VM_APERTURE0_CNTL 0x3310u -#define ATS_ACCESS_MODE_NEVER 0 -#define ATS_ACCESS_MODE_ALWAYS 1 - -#define ATC_VM_APERTURE0_CNTL2 0x3318u -#define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u -#define ATC_VM_APERTURE0_LOW_ADDR 0x3300u -#define ATC_VM_APERTURE1_CNTL 0x3314u -#define ATC_VM_APERTURE1_CNTL2 0x331Cu -#define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu -#define ATC_VM_APERTURE1_LOW_ADDR 0x3304u - #endif -- cgit v1.2.3 From d3c8a0b2becf1015f502bf4b0f50fe18e0ed8a93 Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Mon, 8 Jun 2015 15:25:52 +0200 Subject: drm/sti: correctly test devm_ioremap() return In case of error, the function devm_ioremap_nocache() returns NULL not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun --- drivers/gpu/drm/sti/sti_dvo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/sti/sti_dvo.c b/drivers/gpu/drm/sti/sti_dvo.c index a9b678af85a6..d141d645bd13 100644 --- a/drivers/gpu/drm/sti/sti_dvo.c +++ b/drivers/gpu/drm/sti/sti_dvo.c @@ -499,8 +499,8 @@ static int sti_dvo_probe(struct platform_device *pdev) } dvo->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); - if (IS_ERR(dvo->regs)) - return PTR_ERR(dvo->regs); + if (!dvo->regs) + return -ENOMEM; dvo->clk_pix = devm_clk_get(dev, "dvo_pix"); if (IS_ERR(dvo->clk_pix)) { -- cgit v1.2.3 From 8eba270311dd752bde7326dcf9f89e46feb3faa8 Mon Sep 17 00:00:00 2001 From: Vincent Abriou Date: Fri, 5 Jun 2015 11:47:49 +0200 Subject: drm/sti: missing first pixel column on HDMI display VTG programing updated to fix the shift of one column observed on HDMI display. Signed-off-by: Vincent Abriou --- drivers/gpu/drm/sti/sti_vtg.c | 42 ++++++++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c index 9564f2568e2c..377fa2909450 100644 --- a/drivers/gpu/drm/sti/sti_vtg.c +++ b/drivers/gpu/drm/sti/sti_vtg.c @@ -62,7 +62,7 @@ #define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM) /* Delay introduced by the HDMI in nb of pixel */ -#define HDMI_DELAY (6) +#define HDMI_DELAY (5) /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */ #define AWG_DELAY_HD (-9) @@ -121,6 +121,32 @@ static void vtg_reset(struct sti_vtg *vtg) writel(1, vtg->regs + VTG_DRST_AUTOC); } +static void vtg_set_output_window(void __iomem *regs, + const struct drm_display_mode *mode) +{ + u32 video_top_field_start; + u32 video_top_field_stop; + u32 video_bottom_field_start; + u32 video_bottom_field_stop; + u32 xstart = sti_vtg_get_pixel_number(*mode, 0); + u32 ystart = sti_vtg_get_line_number(*mode, 0); + u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); + u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); + + /* Set output window to fit the display mode selected */ + video_top_field_start = (ystart << 16) | xstart; + video_top_field_stop = (ystop << 16) | xstop; + + /* Only progressive supported for now */ + video_bottom_field_start = video_top_field_start; + video_bottom_field_stop = video_top_field_stop; + + writel(video_top_field_start, regs + VTG_VID_TFO); + writel(video_top_field_stop, regs + VTG_VID_TFS); + writel(video_bottom_field_start, regs + VTG_VID_BFO); + writel(video_bottom_field_stop, regs + VTG_VID_BFS); +} + static void vtg_set_mode(struct sti_vtg *vtg, int type, const struct drm_display_mode *mode) { @@ -129,18 +155,14 @@ static void vtg_set_mode(struct sti_vtg *vtg, if (vtg->slave) vtg_set_mode(vtg->slave, VTG_TYPE_SLAVE_BY_EXT0, mode); + /* Set the number of clock cycles per line */ writel(mode->htotal, vtg->regs + VTG_CLKLN); - writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); - tmp = (mode->vtotal - mode->vsync_start + 1) << 16; - tmp |= mode->htotal - mode->hsync_start; - writel(tmp, vtg->regs + VTG_VID_TFO); - writel(tmp, vtg->regs + VTG_VID_BFO); + /* Set Half Line Per Field (only progressive supported for now) */ + writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); - tmp = (mode->vdisplay + mode->vtotal - mode->vsync_start + 1) << 16; - tmp |= mode->hdisplay + mode->htotal - mode->hsync_start; - writel(tmp, vtg->regs + VTG_VID_TFS); - writel(tmp, vtg->regs + VTG_VID_BFS); + /* Program output window */ + vtg_set_output_window(vtg->regs, mode); /* prepare VTG set 1 for HDMI */ tmp = (mode->hsync_end - mode->hsync_start + HDMI_DELAY) << 16; -- cgit v1.2.3 From 8b0a99ce9a12a49c96dd06d13141277220bf800c Mon Sep 17 00:00:00 2001 From: Vincent Abriou Date: Thu, 4 Jun 2015 10:42:22 +0200 Subject: drm/sti: VTG interrupt names are badly displayed VTG interrupt names are badly displayed using "cat /proc/interrupts". Simply use the VTG device name while registering the VTG interrupts to fix it. Signed-off-by: Vincent Abriou --- drivers/gpu/drm/sti/sti_vtg.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c index 377fa2909450..df855baffe74 100644 --- a/drivers/gpu/drm/sti/sti_vtg.c +++ b/drivers/gpu/drm/sti/sti_vtg.c @@ -333,7 +333,6 @@ static int vtg_probe(struct platform_device *pdev) struct device_node *np; struct sti_vtg *vtg; struct resource *res; - char irq_name[32]; int ret; vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL); @@ -364,13 +363,11 @@ static int vtg_probe(struct platform_device *pdev) return vtg->irq; } - snprintf(irq_name, sizeof(irq_name), "vsync-%s", - dev_name(vtg->dev)); - RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list); ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq, - vtg_irq_thread, IRQF_ONESHOT, irq_name, vtg); + vtg_irq_thread, IRQF_ONESHOT, + dev_name(dev), vtg); if (IS_ERR_VALUE(ret)) { DRM_ERROR("Failed to register VTG interrupt\n"); return ret; -- cgit v1.2.3 From 8661532a6cf841fdab20d7e1868e6fd99a226d32 Mon Sep 17 00:00:00 2001 From: Vincent Abriou Date: Fri, 5 Jun 2015 10:24:43 +0200 Subject: drm/sti: hdmi fix CEA-861E video format timing error HDMI analyzer tests showed that Vsync and Hsync signal were not compliant with the HDMI protocol. The first active pixel of a line is defined by HDMI_ACTIVE_VID_XMIN. The last active pixel of a line is defined by HDMI_ACTIVE_VID_XMAX. Signed-off-by: Vincent Abriou --- drivers/gpu/drm/sti/sti_hdmi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c index ae5424bd6b4c..f28a4d54487c 100644 --- a/drivers/gpu/drm/sti/sti_hdmi.c +++ b/drivers/gpu/drm/sti/sti_hdmi.c @@ -192,8 +192,8 @@ static void hdmi_active_area(struct sti_hdmi *hdmi) u32 xmin, xmax; u32 ymin, ymax; - xmin = sti_vtg_get_pixel_number(hdmi->mode, 0); - xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay - 1); + xmin = sti_vtg_get_pixel_number(hdmi->mode, 1); + xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay); ymin = sti_vtg_get_line_number(hdmi->mode, 0); ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1); -- cgit v1.2.3 From c58d6d1b6652b0a8db4aef7e93fb21ee869b5387 Mon Sep 17 00:00:00 2001 From: Vincent Abriou Date: Thu, 4 Jun 2015 13:59:02 +0200 Subject: drm/sti: vtg fix CEA-861E video format timing error HDMI analyzer tests showed that Vsync and Hsync signal were not compliant with the HDMI protocol. HDMI_DELAY should be taken into account in the VTG Vsync programming to reflect the 6 pixels shift introduced in the VTG Hsync programming. Signed-off-by: Vincent Abriou --- drivers/gpu/drm/sti/sti_vtg.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c index df855baffe74..aa8097137701 100644 --- a/drivers/gpu/drm/sti/sti_vtg.c +++ b/drivers/gpu/drm/sti/sti_vtg.c @@ -173,8 +173,11 @@ static void vtg_set_mode(struct sti_vtg *vtg, tmp |= 1; writel(tmp, vtg->regs + VTG_TOP_V_VD_1); writel(tmp, vtg->regs + VTG_BOT_V_VD_1); - writel(0, vtg->regs + VTG_TOP_V_HD_1); - writel(0, vtg->regs + VTG_BOT_V_HD_1); + + tmp = HDMI_DELAY << 16; + tmp |= HDMI_DELAY; + writel(tmp, vtg->regs + VTG_TOP_V_HD_1); + writel(tmp, vtg->regs + VTG_BOT_V_HD_1); /* prepare VTG set 2 for for HD DCS */ tmp = (mode->hsync_end - mode->hsync_start) << 16; -- cgit v1.2.3 From 7e9fca0baa3b3400ccb2b2a8a17822f7b04ea282 Mon Sep 17 00:00:00 2001 From: Christian König Date: Fri, 5 Jun 2015 10:06:04 +0200 Subject: drm/amdgpu: fix amdgpu_vm_bo_map MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need to reset the bo_va address, otherwise new mappings wouldn't be updated in the page table. Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index fd28e890693e..33696ee55349 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1002,6 +1002,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, list_add(&mapping->list, &bo_va->mappings); interval_tree_insert(&mapping->it, &vm->va); + bo_va->addr = 0; + /* Make sure the page tables are allocated */ saddr >>= amdgpu_vm_block_size; eaddr >>= amdgpu_vm_block_size; -- cgit v1.2.3 From 6c7fc503a47f9b87dfd7c76e34f808ab6870a82f Mon Sep 17 00:00:00 2001 From: Christian König Date: Fri, 5 Jun 2015 20:56:17 +0200 Subject: drm/amdgpu: fix saddr handling in amdgpu_vm_bo_unmap MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 33696ee55349..407882b233c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1084,6 +1084,8 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, struct amdgpu_bo_va_mapping *mapping; struct amdgpu_vm *vm = bo_va->vm; + saddr /= AMDGPU_GPU_PAGE_SIZE; + list_for_each_entry(mapping, &bo_va->mappings, list) { if (mapping->it.start == saddr) break; -- cgit v1.2.3 From 34b5f6a6d6d0e482c7ce498f60bce261e533821e Mon Sep 17 00:00:00 2001 From: Christian König Date: Mon, 8 Jun 2015 15:03:00 +0200 Subject: drm/amdgpu: cleanup VA IOCTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the unnecessary returned status and make the IOCTL write only. Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 64 +++++++++++---------------------- include/uapi/drm/amdgpu_drm.h | 18 ++-------- 2 files changed, 23 insertions(+), 59 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index e8409fea4bf1..0ec222295fee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -505,7 +505,7 @@ error_free: int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { - union drm_amdgpu_gem_va *args = data; + struct drm_amdgpu_gem_va *args = data; struct drm_gem_object *gobj; struct amdgpu_device *adev = dev->dev_private; struct amdgpu_fpriv *fpriv = filp->driver_priv; @@ -514,95 +514,73 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, uint32_t invalid_flags, va_flags = 0; int r = 0; - if (!adev->vm_manager.enabled) { - memset(args, 0, sizeof(*args)); - args->out.result = AMDGPU_VA_RESULT_ERROR; + if (!adev->vm_manager.enabled) return -ENOTTY; - } - if (args->in.va_address < AMDGPU_VA_RESERVED_SIZE) { + if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { dev_err(&dev->pdev->dev, "va_address 0x%lX is in reserved area 0x%X\n", - (unsigned long)args->in.va_address, + (unsigned long)args->va_address, AMDGPU_VA_RESERVED_SIZE); - memset(args, 0, sizeof(*args)); - args->out.result = AMDGPU_VA_RESULT_ERROR; return -EINVAL; } invalid_flags = ~(AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE); - if ((args->in.flags & invalid_flags)) { + if ((args->flags & invalid_flags)) { dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", - args->in.flags, invalid_flags); - memset(args, 0, sizeof(*args)); - args->out.result = AMDGPU_VA_RESULT_ERROR; + args->flags, invalid_flags); return -EINVAL; } - switch (args->in.operation) { + switch (args->operation) { case AMDGPU_VA_OP_MAP: case AMDGPU_VA_OP_UNMAP: break; default: dev_err(&dev->pdev->dev, "unsupported operation %d\n", - args->in.operation); - memset(args, 0, sizeof(*args)); - args->out.result = AMDGPU_VA_RESULT_ERROR; + args->operation); return -EINVAL; } - gobj = drm_gem_object_lookup(dev, filp, args->in.handle); - if (gobj == NULL) { - memset(args, 0, sizeof(*args)); - args->out.result = AMDGPU_VA_RESULT_ERROR; + gobj = drm_gem_object_lookup(dev, filp, args->handle); + if (gobj == NULL) return -ENOENT; - } + rbo = gem_to_amdgpu_bo(gobj); r = amdgpu_bo_reserve(rbo, false); if (r) { - if (r != -ERESTARTSYS) { - memset(args, 0, sizeof(*args)); - args->out.result = AMDGPU_VA_RESULT_ERROR; - } drm_gem_object_unreference_unlocked(gobj); return r; } + bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); if (!bo_va) { - memset(args, 0, sizeof(*args)); - args->out.result = AMDGPU_VA_RESULT_ERROR; - drm_gem_object_unreference_unlocked(gobj); + amdgpu_bo_unreserve(rbo); return -ENOENT; } - switch (args->in.operation) { + switch (args->operation) { case AMDGPU_VA_OP_MAP: - if (args->in.flags & AMDGPU_VM_PAGE_READABLE) + if (args->flags & AMDGPU_VM_PAGE_READABLE) va_flags |= AMDGPU_PTE_READABLE; - if (args->in.flags & AMDGPU_VM_PAGE_WRITEABLE) + if (args->flags & AMDGPU_VM_PAGE_WRITEABLE) va_flags |= AMDGPU_PTE_WRITEABLE; - if (args->in.flags & AMDGPU_VM_PAGE_EXECUTABLE) + if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE) va_flags |= AMDGPU_PTE_EXECUTABLE; - r = amdgpu_vm_bo_map(adev, bo_va, args->in.va_address, - args->in.offset_in_bo, args->in.map_size, + r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, + args->offset_in_bo, args->map_size, va_flags); break; case AMDGPU_VA_OP_UNMAP: - r = amdgpu_vm_bo_unmap(adev, bo_va, args->in.va_address); + r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); break; default: break; } - if (!r) { + if (!r) amdgpu_gem_va_update_vm(adev, bo_va); - memset(args, 0, sizeof(*args)); - args->out.result = AMDGPU_VA_RESULT_OK; - } else { - memset(args, 0, sizeof(*args)); - args->out.result = AMDGPU_VA_RESULT_ERROR; - } drm_gem_object_unreference_unlocked(gobj); return r; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 3b911b604fdf..4c465e10a5a6 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -55,7 +55,7 @@ #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) -#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va) +#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) @@ -290,10 +290,6 @@ struct drm_amdgpu_gem_op { #define AMDGPU_VA_OP_MAP 1 #define AMDGPU_VA_OP_UNMAP 2 -#define AMDGPU_VA_RESULT_OK 0 -#define AMDGPU_VA_RESULT_ERROR 1 -#define AMDGPU_VA_RESULT_VA_INVALID_ALIGNMENT 2 - /* Mapping flags */ /* readable mapping */ #define AMDGPU_VM_PAGE_READABLE (1 << 1) @@ -302,7 +298,7 @@ struct drm_amdgpu_gem_op { /* executable mapping, new for VI */ #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) -struct drm_amdgpu_gem_va_in { +struct drm_amdgpu_gem_va { /* GEM object handle */ uint32_t handle; uint32_t _pad; @@ -319,16 +315,6 @@ struct drm_amdgpu_gem_va_in { uint64_t map_size; }; -struct drm_amdgpu_gem_va_out { - uint32_t result; - uint32_t _pad; -}; - -union drm_amdgpu_gem_va { - struct drm_amdgpu_gem_va_in in; - struct drm_amdgpu_gem_va_out out; -}; - #define AMDGPU_HW_IP_GFX 0 #define AMDGPU_HW_IP_COMPUTE 1 #define AMDGPU_HW_IP_DMA 2 -- cgit v1.2.3 From 3e39ab90833b20eb7fbc4e472726000274739538 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 5 Jun 2015 15:04:33 -0400 Subject: drm/amdgpu: also print the pci revision when printing the pci ids MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The driver makes use of this information so print if to aid in debugging. Reviewed-by: Christian König Reviewed-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 36be03ce76c2..fec487d1c870 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1388,9 +1388,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; - DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", - amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, - pdev->subsystem_vendor, pdev->subsystem_device); + DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", + amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, + pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); /* mutex initialization are all done here so we * can recall function without having locking issues */ -- cgit v1.2.3 From bd5c97bc1ae77e8f2ec93a2dbe6d4080ae04a4c5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 5 Jun 2015 14:34:19 -0400 Subject: drm/amdgpu: set the gfx config properly for all CZ variants (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Need to adjust the number of CUs and RBs. v2: get proper values Reviewed-by: Christian König Reviewed-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 38 +++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 6ae2d6be126a..698ea6ce1185 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1933,9 +1933,43 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) case CHIP_CARRIZO: adev->gfx.config.max_shader_engines = 1; adev->gfx.config.max_tile_pipes = 2; - adev->gfx.config.max_cu_per_sh = 8; adev->gfx.config.max_sh_per_se = 1; - adev->gfx.config.max_backends_per_se = 2; + + switch (adev->pdev->revision) { + case 0xc4: + case 0x84: + case 0xc8: + case 0xcc: + /* B10 */ + adev->gfx.config.max_cu_per_sh = 8; + adev->gfx.config.max_backends_per_se = 2; + break; + case 0xc5: + case 0x81: + case 0x85: + case 0xc9: + case 0xcd: + /* B8 */ + adev->gfx.config.max_cu_per_sh = 6; + adev->gfx.config.max_backends_per_se = 2; + break; + case 0xc6: + case 0xca: + case 0xce: + /* B6 */ + adev->gfx.config.max_cu_per_sh = 6; + adev->gfx.config.max_backends_per_se = 2; + break; + case 0xc7: + case 0x87: + case 0xcb: + default: + /* B4 */ + adev->gfx.config.max_cu_per_sh = 4; + adev->gfx.config.max_backends_per_se = 1; + break; + } + adev->gfx.config.max_texture_channel_caches = 2; adev->gfx.config.max_gprs = 256; adev->gfx.config.max_gs_threads = 32; -- cgit v1.2.3 From 147dbfbc54e460682eba3494370ea33e9fd5e9b0 Mon Sep 17 00:00:00 2001 From: David Zhang Date: Thu, 11 Jun 2015 02:28:56 +0800 Subject: drm/amdgpu: remove the VI hardware semaphore in ring sync MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: David Zhang Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 698ea6ce1185..70cc6bd48926 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3783,11 +3783,10 @@ static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring, unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; if (ring->adev->asic_type == CHIP_TOPAZ || - ring->adev->asic_type == CHIP_TONGA) { - amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); - amdgpu_ring_write(ring, lower_32_bits(addr)); - amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); - } else { + ring->adev->asic_type == CHIP_TONGA) + /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */ + return false; + else { amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2)); amdgpu_ring_write(ring, lower_32_bits(addr)); amdgpu_ring_write(ring, upper_32_bits(addr)); -- cgit v1.2.3 From 454fc95e84a20024eb5d6c0fbc5ab648bae2a56f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Jun 2015 09:58:23 -0400 Subject: drm/amdgpu: fix the build on big endian MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some leftover copy and pastes from radeon that never got updated. Reviewed-by: Christian König Reported-by: Stephen Rothwell Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index fb931638a7e6..ab83cc1ca4cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -411,7 +411,8 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev) rb_bufsz = order_base_2(ring->ring_size / 4); rb_cntl = rb_bufsz << 1; #ifdef __BIG_ENDIAN - rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; + rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | + SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; #endif WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index afa703c0efeb..cb7907447b81 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2881,7 +2881,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) rb_bufsz = order_base_2(ring->ring_size / 8); tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; #ifdef __BIG_ENDIAN - tmp |= BUF_SWAP_32BIT; + tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT; #endif WREG32(mmCP_RB0_CNTL, tmp); @@ -3400,7 +3400,8 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) mqd->queue_state.cp_hqd_pq_control |= (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); #ifdef __BIG_ENDIAN - mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT; + mqd->queue_state.cp_hqd_pq_control |= + 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; #endif mqd->queue_state.cp_hqd_pq_control &= ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | -- cgit v1.2.3 From 5732a94f18cd69331036ab776bdf5e475702e2b4 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Jun 2015 13:51:25 -0400 Subject: drm/admgpu: move XDMA golden registers to dce code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Already moved other display registers. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/vi.c | 4 ---- 3 files changed, 18 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 926c8e0789b0..192dfe55b9ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -120,10 +120,19 @@ static const u32 golden_settings_tonga_a11[] = mmHDMI_CONTROL, 0x31000111, 0x00000011, }; +static const u32 tonga_mgcg_cgcg_init[] = +{ + mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, + mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, +}; + static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_TONGA: + amdgpu_program_register_sequence(adev, + tonga_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index bc60fd1844f3..a530c5dd1193 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -120,10 +120,19 @@ static const u32 cz_golden_settings_a11[] = mmFBC_MISC, 0x1f311fff, 0x14300000, }; +static const u32 cz_mgcg_cgcg_init[] = +{ + mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, + mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, +}; + static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_CARRIZO: + amdgpu_program_register_sequence(adev, + cz_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, cz_golden_settings_a11, (const u32)ARRAY_SIZE(cz_golden_settings_a11)); diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index be7c17610696..b71f41412f91 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -173,8 +173,6 @@ static const u32 tonga_mgcg_cgcg_init[] = mmPCIE_DATA, 0x000f0000, 0x00000000, mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, - mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, - mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, }; @@ -193,8 +191,6 @@ static const u32 cz_mgcg_cgcg_init[] = mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, mmPCIE_INDEX, 0xffffffff, 0x0140001c, mmPCIE_DATA, 0x000f0000, 0x00000000, - mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, - mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, }; -- cgit v1.2.3 From c61bf649270b28526704c2101d1ebd39f51d3f0c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Jun 2015 14:06:18 -0400 Subject: drm/amdgpu: whitespace cleanup in gmc8 golden regs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 6206fcd39df9..8135963a66be 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -71,7 +71,7 @@ static const u32 golden_settings_iceland_a11[] = static const u32 iceland_mgcg_cgcg_init[] = { - mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 + mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 }; static const u32 cz_mgcg_cgcg_init[] = -- cgit v1.2.3 From 6a00a09e49965d7414bacfe24adfc3f59c7d2647 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Jun 2015 14:33:03 -0400 Subject: drm/amdgpu: update to latest gfx8 golden register settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 70cc6bd48926..14242bd33363 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -116,11 +116,14 @@ static const u32 golden_settings_tonga_a11[] = mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, + mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, mmTCC_CTRL, 0x00100000, 0xf31fff7f, + mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, + mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, }; static const u32 tonga_golden_common_all[] = @@ -224,8 +227,10 @@ static const u32 golden_settings_iceland_a11[] = mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002, mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, + mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, mmTCC_CTRL, 0x00100000, 0xf31fff7f, + mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010, @@ -318,7 +323,9 @@ static const u32 cz_golden_settings_a11[] = mmGB_GPU_ID, 0x0000000f, 0x00000000, mmPA_SC_ENHANCE, 0xffffffff, 0x00000001, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, + mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, mmTA_CNTL_AUX, 0x000f000f, 0x00010000, + mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302 }; -- cgit v1.2.3 From 05188312e2ea8991c75bc4ae947d4dc1e7a3bb17 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Jun 2015 17:32:53 -0400 Subject: drm/amdgpu/cz: don't call smu_init on resume smu_init allocates buffers and initializes them. It does not touch the hw. There is no need to do it again on resume. It should really be part of sw_init (and smu_fini should be part of sw_fini), but we need the firmware sizes from the other IPs for firmware loading so we have to wait until sw init is done for all other IPs. Reviewed-by: Sonny Jiang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index f275b5d2d060..131b4733b112 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -1230,7 +1230,10 @@ static int cz_dpm_hw_init(void *handle) mutex_lock(&adev->pm.mutex); - /* init smc in dpm hw init */ + /* smu init only needs to be called at startup, not resume. + * It should be in sw_init, but requires the fw info gathered + * in sw_init from other IP modules. + */ ret = cz_smu_init(adev); if (ret) { DRM_ERROR("amdgpu: smc initialization failed\n"); @@ -1297,6 +1300,10 @@ static int cz_dpm_hw_fini(void *handle) mutex_lock(&adev->pm.mutex); + /* smu fini only needs to be called at teardown, not suspend. + * It should be in sw_fini, but we put it here for symmetry + * with smu init. + */ cz_smu_fini(adev); if (adev->pm.dpm_enabled) { @@ -1340,12 +1347,6 @@ static int cz_dpm_resume(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; mutex_lock(&adev->pm.mutex); - ret = cz_smu_init(adev); - if (ret) { - DRM_ERROR("amdgpu: smc resume failed\n"); - mutex_unlock(&adev->pm.mutex); - return ret; - } /* do the actual fw loading */ ret = cz_smu_start(adev); -- cgit v1.2.3 From aaf4ee3c0233893ac9586ede9cdcaa4a77ccb475 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Jun 2015 17:42:10 -0400 Subject: drm/amdgpu/tonga: don't call smu_init on resume smu_init allocates buffers and initializes them. It does not touch the hw. There is no need to do it again on resume. It should really be part of sw_init (and smu_fini should be part of sw_fini), but we need the firmware sizes from the other IPs for firmware loading so we have to wait until sw init is done for all other IPs. Reviewed-by: Sonny Jiang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/tonga_dpm.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c index 2d5b1bd52afa..204903897b4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c @@ -81,6 +81,10 @@ static int tonga_dpm_hw_init(void *handle) mutex_lock(&adev->pm.mutex); + /* smu init only needs to be called at startup, not resume. + * It should be in sw_init, but requires the fw info gathered + * in sw_init from other IP modules. + */ ret = tonga_smu_init(adev); if (ret) { DRM_ERROR("SMU initialization failed\n"); @@ -107,6 +111,10 @@ static int tonga_dpm_hw_fini(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; mutex_lock(&adev->pm.mutex); + /* smu fini only needs to be called at teardown, not suspend. + * It should be in sw_fini, but we put it here for symmetry + * with smu init. + */ tonga_smu_fini(adev); mutex_unlock(&adev->pm.mutex); return 0; @@ -114,20 +122,25 @@ static int tonga_dpm_hw_fini(void *handle) static int tonga_dpm_suspend(void *handle) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - tonga_dpm_hw_fini(adev); - return 0; } static int tonga_dpm_resume(void *handle) { + int ret; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - tonga_dpm_hw_init(adev); + mutex_lock(&adev->pm.mutex); - return 0; + ret = tonga_smu_start(adev); + if (ret) { + DRM_ERROR("SMU start failed\n"); + goto fail; + } + +fail: + mutex_unlock(&adev->pm.mutex); + return ret; } static int tonga_dpm_set_clockgating_state(void *handle, -- cgit v1.2.3 From b97aab014c6ba6133df1e26bd20c1ad7f50a5bff Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Jun 2015 17:46:30 -0400 Subject: drm/amdgpu/iceland: don't call smu_init on resume smu_init allocates buffers and initializes them. It does not touch the hw. There is no need to do it again on resume. It should really be part of sw_init (and smu_fini should be part of sw_fini), but we need the firmware sizes from the other IPs for firmware loading so we have to wait until sw init is done for all other IPs. Reviewed-by: Sonny Jiang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/iceland_dpm.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c index 4b773f29167a..208d55f41c7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c @@ -82,6 +82,10 @@ static int iceland_dpm_hw_init(void *handle) mutex_lock(&adev->pm.mutex); + /* smu init only needs to be called at startup, not resume. + * It should be in sw_init, but requires the fw info gathered + * in sw_init from other IP modules. + */ ret = iceland_smu_init(adev); if (ret) { DRM_ERROR("SMU initialization failed\n"); @@ -108,6 +112,10 @@ static int iceland_dpm_hw_fini(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; mutex_lock(&adev->pm.mutex); + /* smu fini only needs to be called at teardown, not suspend. + * It should be in sw_fini, but we put it here for symmetry + * with smu init. + */ iceland_smu_fini(adev); mutex_unlock(&adev->pm.mutex); return 0; @@ -115,20 +123,25 @@ static int iceland_dpm_hw_fini(void *handle) static int iceland_dpm_suspend(void *handle) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - iceland_dpm_hw_fini(adev); - return 0; } static int iceland_dpm_resume(void *handle) { + int ret; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - iceland_dpm_hw_init(adev); + mutex_lock(&adev->pm.mutex); - return 0; + ret = iceland_smu_start(adev); + if (ret) { + DRM_ERROR("SMU start failed\n"); + goto fail; + } + +fail: + mutex_unlock(&adev->pm.mutex); + return ret; } static int iceland_dpm_set_clockgating_state(void *handle, -- cgit v1.2.3 From b7a0776949a8f9db835ab652b6fa96b6e7d6972d Mon Sep 17 00:00:00 2001 From: Sonny Jiang Date: Thu, 28 May 2015 15:47:53 -0400 Subject: drm/amdgpu: enable vce powergating MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable VCE dpm and powergating. VCE dpm dynamically scales the VCE clocks on demand. Signed-off-by: Sonny Jiang Reviewed-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 ++++--- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 132 ++++++++++++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/vi.c | 2 +- 4 files changed, 148 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 37aeed7b454d..22866d1c3d69 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1509,6 +1509,7 @@ struct amdgpu_dpm_funcs { int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); bool (*vblank_too_short)(struct amdgpu_device *adev); void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); + void (*powergate_vce)(struct amdgpu_device *adev, bool gate); void (*enable_bapm)(struct amdgpu_device *adev, bool enable); void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); u32 (*get_fan_control_mode)(struct amdgpu_device *adev); @@ -2182,6 +2183,7 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) +#define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g)) #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 605a9e42f943..ed13baa7c976 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -656,19 +656,27 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) { - if (enable) { + if (adev->pm.funcs->powergate_vce) { mutex_lock(&adev->pm.mutex); - adev->pm.dpm.vce_active = true; - /* XXX select vce level based on ring/task */ - adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL; + /* enable/disable VCE */ + amdgpu_dpm_powergate_vce(adev, !enable); + mutex_unlock(&adev->pm.mutex); } else { - mutex_lock(&adev->pm.mutex); - adev->pm.dpm.vce_active = false; - mutex_unlock(&adev->pm.mutex); - } + if (enable) { + mutex_lock(&adev->pm.mutex); + adev->pm.dpm.vce_active = true; + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL; + mutex_unlock(&adev->pm.mutex); + } else { + mutex_lock(&adev->pm.mutex); + adev->pm.dpm.vce_active = false; + mutex_unlock(&adev->pm.mutex); + } - amdgpu_pm_compute_clocks(adev); + amdgpu_pm_compute_clocks(adev); + } } void amdgpu_pm_print_power_states(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index 131b4733b112..10a387424ff8 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -43,6 +43,7 @@ #include "gfx_v8_0.h" static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate); +static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate); static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps) { @@ -558,6 +559,7 @@ static int cz_dpm_late_init(void *handle) /* powerdown unused blocks for now */ cz_dpm_powergate_uvd(adev, true); + cz_dpm_powergate_vce(adev, true); return 0; } @@ -826,16 +828,16 @@ static void cz_init_vce_limit(struct amdgpu_device *adev) return; } - pi->vce_dpm.soft_min_clk = 0; - pi->vce_dpm.hard_min_clk = 0; + pi->vce_dpm.soft_min_clk = table->entries[0].ecclk; + pi->vce_dpm.hard_min_clk = table->entries[0].ecclk; cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel); level = cz_get_argument(adev); if (level < table->count) - clock = table->entries[level].evclk; + clock = table->entries[level].ecclk; else { /* future BIOS would fix this error */ DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n"); - clock = table->entries[table->count - 1].evclk; + clock = table->entries[table->count - 1].ecclk; } pi->vce_dpm.soft_max_clk = clock; @@ -1004,6 +1006,36 @@ static uint32_t cz_get_sclk_level(struct amdgpu_device *adev, return i; } +static uint32_t cz_get_eclk_level(struct amdgpu_device *adev, + uint32_t clock, uint16_t msg) +{ + int i = 0; + struct amdgpu_vce_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + + if (table->count == 0) + return 0; + + switch (msg) { + case PPSMC_MSG_SetEclkSoftMin: + case PPSMC_MSG_SetEclkHardMin: + for (i = 0; i < table->count-1; i++) + if (clock <= table->entries[i].ecclk) + break; + break; + case PPSMC_MSG_SetEclkSoftMax: + case PPSMC_MSG_SetEclkHardMax: + for (i = table->count - 1; i > 0; i--) + if (clock >= table->entries[i].ecclk) + break; + break; + default: + break; + } + + return i; +} + static int cz_program_bootup_state(struct amdgpu_device *adev) { struct cz_power_info *pi = cz_get_pi(adev); @@ -1285,6 +1317,7 @@ static int cz_dpm_disable(struct amdgpu_device *adev) /* powerup blocks */ cz_dpm_powergate_uvd(adev, false); + cz_dpm_powergate_vce(adev, false); cz_clear_voting_clients(adev); cz_stop_dpm(adev); @@ -1775,6 +1808,96 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) } } +static int cz_enable_vce_dpm(struct amdgpu_device *adev, bool enable) +{ + struct cz_power_info *pi = cz_get_pi(adev); + int ret = 0; + + if (enable && pi->caps_vce_dpm) { + pi->dpm_flags |= DPMFlags_VCE_Enabled; + DRM_DEBUG("VCE DPM Enabled.\n"); + + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_EnableAllSmuFeatures, VCE_DPM_MASK); + + } else { + pi->dpm_flags &= ~DPMFlags_VCE_Enabled; + DRM_DEBUG("VCE DPM Stopped\n"); + + ret = cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_DisableAllSmuFeatures, VCE_DPM_MASK); + } + + return ret; +} + +static int cz_update_vce_dpm(struct amdgpu_device *adev) +{ + struct cz_power_info *pi = cz_get_pi(adev); + struct amdgpu_vce_clock_voltage_dependency_table *table = + &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; + + /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */ + if (pi->caps_stable_power_state) { + pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk; + + } else { /* non-stable p-state cases. without vce.Arbiter.EcclkHardMin */ + pi->vce_dpm.hard_min_clk = table->entries[0].ecclk; + } + + cz_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_SetEclkHardMin, + cz_get_eclk_level(adev, + pi->vce_dpm.hard_min_clk, + PPSMC_MSG_SetEclkHardMin)); + return 0; +} + +static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) +{ + struct cz_power_info *pi = cz_get_pi(adev); + + if (pi->caps_vce_pg) { + if (pi->vce_power_gated != gate) { + if (gate) { + /* disable clockgating so we can properly shut down the block */ + amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_CG_STATE_UNGATE); + /* shutdown the VCE block */ + amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_PG_STATE_GATE); + + cz_enable_vce_dpm(adev, false); + /* TODO: to figure out why vce can't be poweroff. */ + /* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */ + pi->vce_power_gated = true; + } else { + cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON); + pi->vce_power_gated = false; + + /* re-init the VCE block */ + amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_PG_STATE_UNGATE); + /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */ + amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_CG_STATE_GATE); + + cz_update_vce_dpm(adev); + cz_enable_vce_dpm(adev, true); + } + } else { + if (! pi->vce_power_gated) { + cz_update_vce_dpm(adev); + } + } + } else { /*pi->caps_vce_pg*/ + cz_update_vce_dpm(adev); + cz_enable_vce_dpm(adev, true); + } + + return; +} + const struct amd_ip_funcs cz_dpm_ip_funcs = { .early_init = cz_dpm_early_init, .late_init = cz_dpm_late_init, @@ -1806,6 +1929,7 @@ static const struct amdgpu_dpm_funcs cz_dpm_funcs = { .force_performance_level = cz_dpm_force_dpm_level, .vblank_too_short = NULL, .powergate_uvd = cz_dpm_powergate_uvd, + .powergate_vce = cz_dpm_powergate_vce, }; static void cz_dpm_set_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index b71f41412f91..90fc93c2c1d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1263,7 +1263,7 @@ static int vi_common_early_init(void *handle) case CHIP_CARRIZO: adev->has_uvd = true; adev->cg_flags = 0; - adev->pg_flags = AMDGPU_PG_SUPPORT_UVD; + adev->pg_flags = AMDGPU_PG_SUPPORT_UVD | AMDGPU_PG_SUPPORT_VCE; adev->external_rev_id = adev->rev_id + 0x1; if (amdgpu_smc_load_fw && smc_enabled) adev->firmware.smu_load = true; -- cgit v1.2.3 From 4802ce11778664a69b308c5aa9b95350b76793be Mon Sep 17 00:00:00 2001 From: Christian König Date: Wed, 10 Jun 2015 17:20:11 +0200 Subject: drm/amdgpu: fix UVD/VCE VM emulation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index f6b224a69b3a..f09b2cba40ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -564,21 +564,33 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, return r; if (ring->funcs->parse_cs) { + struct amdgpu_bo_va_mapping *m; struct amdgpu_bo *aobj = NULL; - void *kptr; + uint64_t offset; + uint8_t *kptr; - amdgpu_cs_find_mapping(parser, chunk_ib->va_start, &aobj); + m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, + &aobj); if (!aobj) { DRM_ERROR("IB va_start is invalid\n"); return -EINVAL; } + if ((chunk_ib->va_start + chunk_ib->ib_bytes) > + (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { + DRM_ERROR("IB va_start+ib_bytes is invalid\n"); + return -EINVAL; + } + /* the IB should be reserved at this point */ - r = amdgpu_bo_kmap(aobj, &kptr); + r = amdgpu_bo_kmap(aobj, (void **)&kptr); if (r) { return r; } + offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; + kptr += chunk_ib->va_start - offset; + r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib); if (r) { DRM_ERROR("Failed to get ib !\n"); -- cgit v1.2.3 From 633ed3df9a65614f14e756424aaff0d317b1b637 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 10 Jun 2015 11:52:00 -0400 Subject: drm/amdgpu: don't enable/disable display twice on suspend/resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We were doing it in the common code and in the IP specific code. Remove the IP specific code. The common code handles the ordering properly. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 18 ------------------ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 18 ------------------ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 18 ------------------ 3 files changed, 54 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 192dfe55b9ab..5cde635978f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -3017,16 +3017,8 @@ static int dce_v10_0_hw_fini(void *handle) static int dce_v10_0_suspend(void *handle) { - struct drm_connector *connector; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - drm_kms_helper_poll_disable(adev->ddev); - - /* turn off display hw */ - list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { - drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); - } - amdgpu_atombios_scratch_regs_save(adev); dce_v10_0_hpd_fini(adev); @@ -3036,7 +3028,6 @@ static int dce_v10_0_suspend(void *handle) static int dce_v10_0_resume(void *handle) { - struct drm_connector *connector; struct amdgpu_device *adev = (struct amdgpu_device *)handle; dce_v10_0_init_golden_registers(adev); @@ -3057,15 +3048,6 @@ static int dce_v10_0_resume(void *handle) /* initialize hpd */ dce_v10_0_hpd_init(adev); - /* blat the mode back in */ - drm_helper_resume_force_mode(adev->ddev); - /* turn on display hw */ - list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { - drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); - } - - drm_kms_helper_poll_enable(adev->ddev); - return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index a530c5dd1193..95efd98b202d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3015,16 +3015,8 @@ static int dce_v11_0_hw_fini(void *handle) static int dce_v11_0_suspend(void *handle) { - struct drm_connector *connector; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - drm_kms_helper_poll_disable(adev->ddev); - - /* turn off display hw */ - list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { - drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); - } - amdgpu_atombios_scratch_regs_save(adev); dce_v11_0_hpd_fini(adev); @@ -3034,7 +3026,6 @@ static int dce_v11_0_suspend(void *handle) static int dce_v11_0_resume(void *handle) { - struct drm_connector *connector; struct amdgpu_device *adev = (struct amdgpu_device *)handle; dce_v11_0_init_golden_registers(adev); @@ -3056,15 +3047,6 @@ static int dce_v11_0_resume(void *handle) /* initialize hpd */ dce_v11_0_hpd_init(adev); - /* blat the mode back in */ - drm_helper_resume_force_mode(adev->ddev); - /* turn on display hw */ - list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { - drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); - } - - drm_kms_helper_poll_enable(adev->ddev); - return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 9e8b9f1fad18..72c27ac915f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2948,16 +2948,8 @@ static int dce_v8_0_hw_fini(void *handle) static int dce_v8_0_suspend(void *handle) { - struct drm_connector *connector; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - drm_kms_helper_poll_disable(adev->ddev); - - /* turn off display hw */ - list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { - drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); - } - amdgpu_atombios_scratch_regs_save(adev); dce_v8_0_hpd_fini(adev); @@ -2967,7 +2959,6 @@ static int dce_v8_0_suspend(void *handle) static int dce_v8_0_resume(void *handle) { - struct drm_connector *connector; struct amdgpu_device *adev = (struct amdgpu_device *)handle; amdgpu_atombios_scratch_regs_restore(adev); @@ -2986,15 +2977,6 @@ static int dce_v8_0_resume(void *handle) /* initialize hpd */ dce_v8_0_hpd_init(adev); - /* blat the mode back in */ - drm_helper_resume_force_mode(adev->ddev); - /* turn on display hw */ - list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { - drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); - } - - drm_kms_helper_poll_enable(adev->ddev); - return 0; } -- cgit v1.2.3 From 6d8db6ce239587c3d300d79fce3f5bb376232475 Mon Sep 17 00:00:00 2001 From: Sonny Jiang Date: Wed, 10 Jun 2015 13:46:36 -0400 Subject: drm/amdgpu: fix a amdgpu_dpm=0 bug Signed-off-by: Sonny Jiang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index 10a387424ff8..e4936a452bc6 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -557,9 +557,11 @@ static int cz_dpm_late_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - /* powerdown unused blocks for now */ - cz_dpm_powergate_uvd(adev, true); - cz_dpm_powergate_vce(adev, true); + if (amdgpu_dpm) { + /* powerdown unused blocks for now */ + cz_dpm_powergate_uvd(adev, true); + cz_dpm_powergate_vce(adev, true); + } return 0; } -- cgit v1.2.3 From 2b7edcad69ecf6c452871c80a336bc3430ca9942 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 10 Jun 2015 22:27:11 +0300 Subject: drm/virtio: checking for NULL instead of IS_ERR virtio_gpu_alloc_object() returns an error pointer, it never returns NULL. Fixes: dc5698e80cf7 ('Add virtio gpu driver.') Signed-off-by: Dan Carpenter Signed-off-by: Dave Airlie --- drivers/gpu/drm/virtio/virtgpu_fb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/virtio/virtgpu_fb.c b/drivers/gpu/drm/virtio/virtgpu_fb.c index 25bf333d5a45..df198d9e770c 100644 --- a/drivers/gpu/drm/virtio/virtgpu_fb.c +++ b/drivers/gpu/drm/virtio/virtgpu_fb.c @@ -299,8 +299,8 @@ static int virtio_gpufb_create(struct drm_fb_helper *helper, size = mode_cmd.pitches[0] * mode_cmd.height; obj = virtio_gpu_alloc_object(dev, size, false, true); - if (!obj) - return -ENOMEM; + if (IS_ERR(obj)) + return PTR_ERR(obj); virtio_gpu_resource_id_get(vgdev, &resid); virtio_gpu_cmd_create_resource(vgdev, resid, format, -- cgit v1.2.3 From 3f05eb4e3fc56df678f83925ced78bc97166b052 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 10 Jun 2015 22:27:51 +0300 Subject: drm/virtio: remove some dead code The goto is correct, and we never reach the return statement so just delete the dead code. Signed-off-by: Dan Carpenter Signed-off-by: Dave Airlie --- drivers/gpu/drm/virtio/virtgpu_ttm.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/virtio/virtgpu_ttm.c b/drivers/gpu/drm/virtio/virtgpu_ttm.c index e0e74c6bb959..b092d7b9a292 100644 --- a/drivers/gpu/drm/virtio/virtgpu_ttm.c +++ b/drivers/gpu/drm/virtio/virtgpu_ttm.c @@ -443,14 +443,12 @@ int virtio_gpu_ttm_init(struct virtio_gpu_device *vgdev) if (r) { DRM_ERROR("failed initializing buffer object driver(%d).\n", r); goto err_dev_init; - return r; } r = ttm_bo_init_mm(&vgdev->mman.bdev, TTM_PL_TT, 0); if (r) { DRM_ERROR("Failed initializing GTT heap.\n"); goto err_mm_init; - return r; } return 0; -- cgit v1.2.3 From 26716185516fc09723833d64f2af87db4e3eae7a Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sun, 19 Apr 2015 10:14:09 -0400 Subject: drm/msm/adreno: dump scratch regs and other info on hang Dump a bit more info when the GPU hangs, without having hang_debug enabled (which dumps a *lot* of registers). Also dump the scratch registers, as they are useful for determining where in the cmdstream the GPU hung (and they seem always safe to read when GPU has hung). Note that the freedreno gallium driver emits increasing counter values to SCRATCH6 (to identify tile #) and SCRATCH7 (to identify draw #), so these two in particular can be used to "triangulate" where in the cmdstream the GPU hung. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 3 +++ drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 3 ++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 +++++++++++++++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 4 files changed, 25 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index b66c53bdc039..0f0c45665dbd 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -295,9 +295,12 @@ static int a3xx_hw_init(struct msm_gpu *gpu) static void a3xx_recover(struct msm_gpu *gpu) { + adreno_dump_info(gpu); + /* dump registers before resetting gpu, if enabled: */ if (hang_debug) a3xx_dump(gpu); + gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1); gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0); diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 91221836c5ad..a53f1be05f75 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -268,6 +268,8 @@ static int a4xx_hw_init(struct msm_gpu *gpu) static void a4xx_recover(struct msm_gpu *gpu) { + adreno_dump_info(gpu); + /* dump registers before resetting gpu, if enabled: */ if (hang_debug) a4xx_dump(gpu); @@ -505,7 +507,6 @@ static const unsigned int a4xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { static void a4xx_dump(struct msm_gpu *gpu) { - adreno_dump(gpu); printk("status: %08x\n", gpu_read(gpu, REG_A4XX_RBBM_STATUS)); adreno_dump(gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index bbdcab0a56c1..a1e861316590 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -249,8 +249,13 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m) } #endif -/* would be nice to not have to duplicate the _show() stuff with printk(): */ -void adreno_dump(struct msm_gpu *gpu) +/* Dump common gpu status and scratch registers on any hang, to make + * the hangcheck logs more useful. The scratch registers seem always + * safe to read when GPU has hung (unlike some other regs, depending + * on how the GPU hung), and they are useful to match up to cmdstream + * dumps when debugging hangs: + */ +void adreno_dump_info(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int i; @@ -266,6 +271,18 @@ void adreno_dump(struct msm_gpu *gpu) printk("wptr: %d\n", adreno_gpu->memptrs->wptr); printk("rb wptr: %d\n", get_wptr(gpu->rb)); + for (i = 0; i < 8; i++) { + printk("CP_SCRATCH_REG%d: %u\n", i, + gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); + } +} + +/* would be nice to not have to duplicate the _show() stuff with printk(): */ +void adreno_dump(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + int i; + /* dump these out in a form that can be parsed by demsm: */ printk("IO:region %s 00000000 00020000\n", gpu->name); for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index a0cc30977e67..2b6b57baf6fd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -233,6 +233,7 @@ void adreno_idle(struct msm_gpu *gpu); #ifdef CONFIG_DEBUG_FS void adreno_show(struct msm_gpu *gpu, struct seq_file *m); #endif +void adreno_dump_info(struct msm_gpu *gpu); void adreno_dump(struct msm_gpu *gpu); void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords); -- cgit v1.2.3 From a5436e1d241488f58bbf7cd4a84fefc9c39c4b62 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 4 Jun 2015 10:12:22 -0400 Subject: drm/msm: add missing DRIVER_ATOMIC flag Somehow this got lost when msm atomic support was first merged. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_drv.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index c80a6bee2b18..7efd3071481d 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -885,6 +885,7 @@ static struct drm_driver msm_driver = { DRIVER_GEM | DRIVER_PRIME | DRIVER_RENDER | + DRIVER_ATOMIC | DRIVER_MODESET, .load = msm_load, .unload = msm_unload, -- cgit v1.2.3 From af6cb4c1a451b0e68a0581a6487f6c0423caeeb3 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 20 May 2015 10:50:30 -0400 Subject: drm/msm: update generated headers Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a2xx.xml.h | 6 +- drivers/gpu/drm/msm/adreno/a3xx.xml.h | 168 +++++++++- drivers/gpu/drm/msm/adreno/a4xx.xml.h | 420 ++++++++++++++++++++++-- drivers/gpu/drm/msm/adreno/adreno_common.xml.h | 6 +- drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 31 +- drivers/gpu/drm/msm/dsi/dsi.xml.h | 163 ++++++++- drivers/gpu/drm/msm/dsi/mmss_cc.xml.h | 12 +- drivers/gpu/drm/msm/dsi/sfpb.xml.h | 12 +- drivers/gpu/drm/msm/edp/edp.xml.h | 101 +++++- drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 99 +++++- drivers/gpu/drm/msm/hdmi/qfprom.xml.h | 12 +- drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h | 32 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 398 +++++++++++++++++++++- drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 14 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 10 +- drivers/gpu/drm/msm/mdp/mdp_common.xml.h | 16 +- drivers/gpu/drm/msm/mdp/mdp_kms.h | 2 +- 17 files changed, 1359 insertions(+), 143 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h index edc845fffdf4..23176e402796 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h @@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19) Copyright (C) 2013-2014 by the following authors: - Rob Clark (robclark) diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h index e91a739452d7..1c599e5cf318 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h @@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19) -Copyright (C) 2013-2014 by the following authors: +Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) Permission is hereby granted, free of charge, to any person obtaining @@ -130,6 +130,10 @@ enum a3xx_tex_fmt { TFMT_I420_Y = 24, TFMT_I420_U = 26, TFMT_I420_V = 27, + TFMT_ATC_RGB = 32, + TFMT_ATC_RGBA_EXPLICIT = 33, + TFMT_ETC1 = 34, + TFMT_ATC_RGBA_INTERPOLATED = 35, TFMT_DXT1 = 36, TFMT_DXT3 = 37, TFMT_DXT5 = 38, @@ -178,10 +182,13 @@ enum a3xx_tex_fmt { TFMT_32_SINT = 92, TFMT_32_32_SINT = 93, TFMT_32_32_32_32_SINT = 95, - TFMT_RGTC2_SNORM = 112, - TFMT_RGTC2_UNORM = 113, - TFMT_RGTC1_SNORM = 114, - TFMT_RGTC1_UNORM = 115, + TFMT_ETC2_RG11_SNORM = 112, + TFMT_ETC2_RG11_UNORM = 113, + TFMT_ETC2_R11_SNORM = 114, + TFMT_ETC2_R11_UNORM = 115, + TFMT_ETC2_RGBA8 = 116, + TFMT_ETC2_RGB8A1 = 117, + TFMT_ETC2_RGB8 = 118, }; enum a3xx_tex_fetchsize { @@ -209,14 +216,24 @@ enum a3xx_color_fmt { RB_R10G10B10A2_UNORM = 16, RB_A8_UNORM = 20, RB_R8_UNORM = 21, + RB_R16_FLOAT = 24, + RB_R16G16_FLOAT = 25, RB_R16G16B16A16_FLOAT = 27, RB_R11G11B10_FLOAT = 28, + RB_R16_SNORM = 32, + RB_R16G16_SNORM = 33, + RB_R16G16B16A16_SNORM = 35, + RB_R16_UNORM = 36, + RB_R16G16_UNORM = 37, + RB_R16G16B16A16_UNORM = 39, RB_R16_SINT = 40, RB_R16G16_SINT = 41, RB_R16G16B16A16_SINT = 43, RB_R16_UINT = 44, RB_R16G16_UINT = 45, RB_R16G16B16A16_UINT = 47, + RB_R32_FLOAT = 48, + RB_R32G32_FLOAT = 49, RB_R32G32B32A32_FLOAT = 51, RB_R32_SINT = 52, RB_R32G32_SINT = 53, @@ -265,6 +282,12 @@ enum a3xx_intp_mode { FLAT = 1, }; +enum a3xx_repl_mode { + S = 1, + T = 2, + ONE_T = 3, +}; + enum a3xx_tex_filter { A3XX_TEX_NEAREST = 0, A3XX_TEX_LINEAR = 1, @@ -751,7 +774,7 @@ static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) { - return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; + return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; } #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 @@ -854,6 +877,12 @@ static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode va { return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; } +#define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000 +#define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12 +static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) +{ + return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK; +} #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 @@ -1246,9 +1275,21 @@ static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105 -#define REG_A3XX_RB_STENCIL_BUF_INFO 0x00002106 +#define REG_A3XX_RB_STENCIL_INFO 0x00002106 +#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800 +#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11 +static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) +{ + return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; +} -#define REG_A3XX_RB_STENCIL_BUF_PITCH 0x00002107 +#define REG_A3XX_RB_STENCIL_PITCH 0x00002107 +#define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff +#define A3XX_RB_STENCIL_PITCH__SHIFT 0 +static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) +{ + return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK; +} #define REG_A3XX_RB_STENCILREFMASK 0x00002108 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff @@ -1356,6 +1397,7 @@ static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_ { return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; } +#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000 #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 @@ -1805,6 +1847,102 @@ static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } +#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003 +#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c +#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030 +#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0 +#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300 +#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00 +#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000 +#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000 +#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000 +#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000 +#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000 +#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000 +#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000 +#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000 +#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000 +#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK; +} +#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000 +#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30 +static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) +{ + return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK; +} #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a @@ -2107,6 +2245,12 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec +#define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003 +#define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 +static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) +{ + return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK; +} #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 @@ -2661,7 +2805,7 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) } #define REG_A3XX_TEX_CONST_3 0x00000003 -#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0000000f +#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x00007fff #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) { diff --git a/drivers/gpu/drm/msm/adreno/a4xx.xml.h b/drivers/gpu/drm/msm/adreno/a4xx.xml.h index 755723fd8ba5..3f06ecf62583 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a4xx.xml.h @@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19) -Copyright (C) 2013-2014 by the following authors: +Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) Permission is hereby granted, free of charge, to any person obtaining @@ -43,10 +43,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. enum a4xx_color_fmt { RB4_A8_UNORM = 1, + RB4_R8_UNORM = 2, + RB4_R4G4B4A4_UNORM = 8, + RB4_R5G5B5A1_UNORM = 10, RB4_R5G6R5_UNORM = 14, - RB4_Z16_UNORM = 15, + RB4_R8G8_UNORM = 15, + RB4_R8G8_SNORM = 16, + RB4_R8G8_UINT = 17, + RB4_R8G8_SINT = 18, + RB4_R16_FLOAT = 21, + RB4_R16_UINT = 22, + RB4_R16_SINT = 23, RB4_R8G8B8_UNORM = 25, RB4_R8G8B8A8_UNORM = 26, + RB4_R8G8B8A8_SNORM = 28, + RB4_R8G8B8A8_UINT = 29, + RB4_R8G8B8A8_SINT = 30, + RB4_R10G10B10A2_UNORM = 31, + RB4_R10G10B10A2_UINT = 34, + RB4_R11G11B10_FLOAT = 39, + RB4_R16G16_FLOAT = 42, + RB4_R16G16_UINT = 43, + RB4_R16G16_SINT = 44, + RB4_R32_FLOAT = 45, + RB4_R32_UINT = 46, + RB4_R32_SINT = 47, + RB4_R16G16B16A16_FLOAT = 54, + RB4_R16G16B16A16_UINT = 55, + RB4_R16G16B16A16_SINT = 56, + RB4_R32G32_FLOAT = 57, + RB4_R32G32_UINT = 58, + RB4_R32G32_SINT = 59, + RB4_R32G32B32A32_FLOAT = 60, + RB4_R32G32B32A32_UINT = 61, + RB4_R32G32B32A32_SINT = 62, }; enum a4xx_tile_mode { @@ -91,7 +121,14 @@ enum a4xx_vtx_fmt { VFMT4_16_16_UNORM = 29, VFMT4_16_16_16_UNORM = 30, VFMT4_16_16_16_16_UNORM = 31, + VFMT4_32_UINT = 32, + VFMT4_32_32_UINT = 33, + VFMT4_32_32_32_UINT = 34, + VFMT4_32_32_32_32_UINT = 35, + VFMT4_32_SINT = 36, VFMT4_32_32_SINT = 37, + VFMT4_32_32_32_SINT = 38, + VFMT4_32_32_32_32_SINT = 39, VFMT4_8_UINT = 40, VFMT4_8_8_UINT = 41, VFMT4_8_8_8_UINT = 42, @@ -125,12 +162,57 @@ enum a4xx_tex_fmt { TFMT4_8_UNORM = 4, TFMT4_8_8_UNORM = 14, TFMT4_8_8_8_8_UNORM = 28, + TFMT4_8_8_SNORM = 15, + TFMT4_8_8_8_8_SNORM = 29, + TFMT4_8_8_UINT = 16, + TFMT4_8_8_8_8_UINT = 30, + TFMT4_8_8_SINT = 17, + TFMT4_8_8_8_8_SINT = 31, + TFMT4_16_UINT = 21, + TFMT4_16_16_UINT = 41, + TFMT4_16_16_16_16_UINT = 54, + TFMT4_16_SINT = 22, + TFMT4_16_16_SINT = 42, + TFMT4_16_16_16_16_SINT = 55, + TFMT4_32_UINT = 44, + TFMT4_32_32_UINT = 57, + TFMT4_32_32_32_32_UINT = 64, + TFMT4_32_SINT = 45, + TFMT4_32_32_SINT = 58, + TFMT4_32_32_32_32_SINT = 65, TFMT4_16_FLOAT = 20, TFMT4_16_16_FLOAT = 40, TFMT4_16_16_16_16_FLOAT = 53, TFMT4_32_FLOAT = 43, TFMT4_32_32_FLOAT = 56, TFMT4_32_32_32_32_FLOAT = 63, + TFMT4_9_9_9_E5_FLOAT = 32, + TFMT4_11_11_10_FLOAT = 37, + TFMT4_ATC_RGB = 100, + TFMT4_ATC_RGBA_EXPLICIT = 101, + TFMT4_ATC_RGBA_INTERPOLATED = 102, + TFMT4_ETC2_RG11_UNORM = 103, + TFMT4_ETC2_RG11_SNORM = 104, + TFMT4_ETC2_R11_UNORM = 105, + TFMT4_ETC2_R11_SNORM = 106, + TFMT4_ETC1 = 107, + TFMT4_ETC2_RGB8 = 108, + TFMT4_ETC2_RGBA8 = 109, + TFMT4_ETC2_RGB8A1 = 110, + TFMT4_ASTC_4x4 = 111, + TFMT4_ASTC_5x4 = 112, + TFMT4_ASTC_5x5 = 113, + TFMT4_ASTC_6x5 = 114, + TFMT4_ASTC_6x6 = 115, + TFMT4_ASTC_8x5 = 116, + TFMT4_ASTC_8x6 = 117, + TFMT4_ASTC_8x8 = 118, + TFMT4_ASTC_10x5 = 119, + TFMT4_ASTC_10x6 = 120, + TFMT4_ASTC_10x8 = 121, + TFMT4_ASTC_10x10 = 122, + TFMT4_ASTC_12x10 = 123, + TFMT4_ASTC_12x12 = 124, }; enum a4xx_tex_fetchsize { @@ -147,9 +229,16 @@ enum a4xx_depth_format { DEPTH4_24_8 = 2, }; +enum a4xx_tess_spacing { + EQUAL_SPACING = 0, + ODD_SPACING = 2, + EVEN_SPACING = 3, +}; + enum a4xx_tex_filter { A4XX_TEX_NEAREST = 0, A4XX_TEX_LINEAR = 1, + A4XX_TEX_ANISO = 2, }; enum a4xx_tex_clamp { @@ -159,6 +248,14 @@ enum a4xx_tex_clamp { A4XX_TEX_CLAMP_NONE = 3, }; +enum a4xx_tex_aniso { + A4XX_TEX_ANISO_1 = 0, + A4XX_TEX_ANISO_2 = 1, + A4XX_TEX_ANISO_4 = 2, + A4XX_TEX_ANISO_8 = 3, + A4XX_TEX_ANISO_16 = 4, +}; + enum a4xx_tex_swiz { A4XX_TEX_X = 0, A4XX_TEX_Y = 1, @@ -279,13 +376,16 @@ static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002 #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004 #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008 +#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 +#define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) { return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; } +#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800 #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } @@ -310,6 +410,12 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val { return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; } +#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 +#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 +static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) +{ + return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; +} #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) @@ -322,6 +428,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) { return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; } +#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0x007fc000 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) @@ -449,7 +556,12 @@ static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare } #define REG_A4XX_RB_FS_OUTPUT 0x000020f9 -#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND 0x00000001 +#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff +#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0 +static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) +{ + return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; +} #define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 @@ -458,12 +570,54 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; } -#define REG_A4XX_RB_RENDER_CONTROL3 0x000020fb -#define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK 0x0000001f -#define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT 0 -static inline uint32_t A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE(uint32_t val) +#define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb +#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f +#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 +static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) { - return ((val) << A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT) & A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK; + return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; +} +#define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 +#define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 +static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) +{ + return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; +} +#define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 +#define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 +static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) +{ + return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; +} +#define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 +#define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 +static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) +{ + return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; +} +#define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 +#define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 +static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) +{ + return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; +} +#define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 +#define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 +static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) +{ + return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; +} +#define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 +#define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 +static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) +{ + return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; +} +#define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 +#define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 +static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) +{ + return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; } #define REG_A4XX_RB_COPY_CONTROL 0x000020fc @@ -547,7 +701,12 @@ static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) } #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 -#define A4XX_RB_FS_OUTPUT_REG_COLOR_PIPE_ENABLE 0x00000001 +#define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f +#define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0 +static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) +{ + return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; +} #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 @@ -930,6 +1089,10 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) #define REG_A4XX_CP_IB2_BUFSZ 0x00000209 +#define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c + +#define REG_A4XX_CP_ME_NRT_DATA 0x0000020d + #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 @@ -940,9 +1103,9 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) #define REG_A4XX_CP_ROQ_DATA 0x0000021d -#define REG_A4XX_CP_MEQ_ADDR 0x0000021e +#define REG_A4XX_CP_MEQ_ADDR 0x0000021e -#define REG_A4XX_CP_MEQ_DATA 0x0000021f +#define REG_A4XX_CP_MEQ_DATA 0x0000021f #define REG_A4XX_CP_MERCIU_ADDR 0x00000220 @@ -1004,12 +1167,17 @@ static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 #define REG_A4XX_SP_VS_STATUS 0x00000ec0 +#define REG_A4XX_SP_MODE_CONTROL 0x00000ec3 + #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 +#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080 +#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100 +#define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 @@ -1229,6 +1397,12 @@ static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 +#define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f +#define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 +static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) +{ + return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; +} #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 @@ -1236,6 +1410,12 @@ static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) { return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; } +#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000 +#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24 +static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) +{ + return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; +} static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } @@ -1254,6 +1434,20 @@ static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; } +#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300 + +#define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301 + +#define REG_A4XX_SP_CS_OBJ_START 0x00002302 + +#define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303 + +#define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304 + +#define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305 + +#define REG_A4XX_SP_CS_LENGTH_REG 0x00002306 + #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 @@ -1268,6 +1462,14 @@ static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; } +#define REG_A4XX_SP_HS_OBJ_START 0x0000230e + +#define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f + +#define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310 + +#define REG_A4XX_SP_HS_LENGTH_REG 0x00002312 + #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 @@ -1282,6 +1484,14 @@ static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; } +#define REG_A4XX_SP_DS_OBJ_START 0x00002335 + +#define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336 + +#define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337 + +#define REG_A4XX_SP_DS_LENGTH_REG 0x00002339 + #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 @@ -1296,6 +1506,12 @@ static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; } +#define REG_A4XX_SP_GS_OBJ_START 0x0000235c + +#define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d + +#define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e + #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 @@ -1418,6 +1634,10 @@ static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a +#define REG_A4XX_VGT_CL_INITIATOR 0x000021d0 + +#define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9 + #define REG_A4XX_VFD_CONTROL_0 0x00002200 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 @@ -1554,10 +1774,54 @@ static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 +#define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03 + #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 +#define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381 +#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff +#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0 +static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) +{ + return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; +} +#define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00 +#define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8 +static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) +{ + return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; +} +#define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000 +#define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16 +static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) +{ + return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; +} +#define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000 +#define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24 +static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) +{ + return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; +} + +#define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384 + +#define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387 + +#define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a + +#define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d + +#define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0 + +#define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1 + +#define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4 + +#define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5 + #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 @@ -1676,6 +1940,14 @@ static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; } +#define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076 +#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff +#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0 +static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) +{ + return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK; +} + #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 @@ -1828,6 +2100,8 @@ static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 +#define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05 + #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 @@ -1867,7 +2141,12 @@ static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) { return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; } -#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000 +#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000 +#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24 +static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) +{ + return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK; +} #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 @@ -1882,6 +2161,18 @@ static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) { return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; } +#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00 +#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10 +static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) +{ + return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK; +} +#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000 +#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18 +static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) +{ + return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK; +} #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff @@ -1891,6 +2182,8 @@ static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; } +#define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4 + #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 @@ -1904,6 +2197,7 @@ static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) { return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; } +#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) @@ -1930,6 +2224,7 @@ static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) { return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; } +#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) @@ -1956,6 +2251,7 @@ static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) { return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; } +#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) @@ -1982,6 +2278,7 @@ static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) { return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; } +#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) @@ -2008,6 +2305,7 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) { return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; } +#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) @@ -2021,6 +2319,36 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; } +#define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca + +#define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd + +#define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce + +#define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf + +#define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0 + +#define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1 + +#define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2 + +#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3 + +#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4 + +#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5 + +#define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6 + +#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7 + +#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8 + +#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9 + +#define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da + #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 @@ -2035,7 +2363,13 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) #define REG_A4XX_PC_BIN_BASE 0x000021c0 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 -#define A4XX_PC_PRIM_VTX_CNTL_VAROUT 0x00000001 +#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f +#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 +static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) +{ + return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; +} +#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 @@ -2044,8 +2378,45 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) #define REG_A4XX_PC_RESTART_INDEX 0x000021c6 #define REG_A4XX_PC_GS_PARAM 0x000021e5 +#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff +#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 +static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) +{ + return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; +} +#define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 +#define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 +static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) +{ + return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; +} +#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 +#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 +static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) +{ + return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; +} +#define A4XX_PC_GS_PARAM_LAYER 0x80000000 #define REG_A4XX_PC_HS_PARAM 0x000021e7 +#define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f +#define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 +static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) +{ + return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; +} +#define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000 +#define A4XX_PC_HS_PARAM_SPACING__SHIFT 21 +static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) +{ + return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; +} +#define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000 +#define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23 +static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) +{ + return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK; +} #define REG_A4XX_VBIF_VERSION 0x00003000 @@ -2074,16 +2445,10 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) #define REG_A4XX_UNKNOWN_0D01 0x00000d01 -#define REG_A4XX_UNKNOWN_0E05 0x00000e05 - #define REG_A4XX_UNKNOWN_0E42 0x00000e42 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 -#define REG_A4XX_UNKNOWN_0EC3 0x00000ec3 - -#define REG_A4XX_UNKNOWN_0F03 0x00000f03 - #define REG_A4XX_UNKNOWN_2001 0x00002001 #define REG_A4XX_UNKNOWN_209B 0x0000209b @@ -2124,10 +2489,6 @@ static inline uint32_t A4XX_UNKNOWN_20F7(float val) #define REG_A4XX_UNKNOWN_22D7 0x000022d7 -#define REG_A4XX_UNKNOWN_2381 0x00002381 - -#define REG_A4XX_UNKNOWN_23A0 0x000023a0 - #define REG_A4XX_TEX_SAMP_0 0x00000000 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 @@ -2160,6 +2521,12 @@ static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) { return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; } +#define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 +#define A4XX_TEX_SAMP_0_ANISO__SHIFT 14 +static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) +{ + return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; +} #define REG_A4XX_TEX_SAMP_1 0x00000001 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e @@ -2185,6 +2552,7 @@ static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) #define REG_A4XX_TEX_CONST_0 0x00000000 #define A4XX_TEX_CONST_0_TILED 0x00000001 +#define A4XX_TEX_CONST_0_SRGB 0x00000004 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h index 8531beb982e7..9562a1fa552b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h +++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h @@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19) Copyright (C) 2013-2014 by the following authors: - Rob Clark (robclark) diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h index 6ffc4f6c8af1..bd5b23bf9041 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h +++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h @@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19) -Copyright (C) 2013-2014 by the following authors: +Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) Permission is hereby granted, free of charge, to any person obtaining @@ -76,16 +76,11 @@ enum pc_di_primtype { DI_PT_LINELOOP = 7, DI_PT_RECTLIST = 8, DI_PT_POINTLIST_A3XX = 9, - DI_PT_QUADLIST = 13, - DI_PT_QUADSTRIP = 14, - DI_PT_POLYGON = 15, - DI_PT_2D_COPY_RECT_LIST_V0 = 16, - DI_PT_2D_COPY_RECT_LIST_V1 = 17, - DI_PT_2D_COPY_RECT_LIST_V2 = 18, - DI_PT_2D_COPY_RECT_LIST_V3 = 19, - DI_PT_2D_FILL_RECT_LIST = 20, - DI_PT_2D_LINE_STRIP = 21, - DI_PT_2D_TRI_STRIP = 22, + DI_PT_LINE_ADJ = 10, + DI_PT_LINESTRIP_ADJ = 11, + DI_PT_TRI_ADJ = 12, + DI_PT_TRISTRIP_ADJ = 13, + DI_PT_PATCHES = 34, }; enum pc_di_src_sel { @@ -192,6 +187,7 @@ enum adreno_state_block { SB_FRAG_TEX = 2, SB_FRAG_MIPADDR = 3, SB_VERT_SHADER = 4, + SB_GEOM_SHADER = 5, SB_FRAG_SHADER = 6, }; @@ -382,12 +378,19 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel va { return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; } +#define CP_DRAW_INDX_OFFSET_0_TESSELLATE 0x00000100 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) { return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; } +#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000 +#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20 +static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val) +{ + return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK; +} #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 1dcfae265e98..9791ea04bcbc 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -8,8 +8,17 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /usr2/hali/local/envytools/envytools/rnndb/dsi/dsi.xml ( 18681 bytes, from 2015-03-04 23:08:31) -- /usr2/hali/local/envytools/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-01-28 21:43:22) +- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23) +- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23) Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) @@ -394,6 +403,9 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 +#define REG_DSI_LANE_CTRL 0x000000a8 +#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000 + #define REG_DSI_LANE_SWAP_CTRL 0x000000ac #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0 @@ -835,5 +847,152 @@ static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 +#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 +#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001 + +#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 + +#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 + +#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c + +#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010 +#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002 + +#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 + +#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018 + +#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c + +#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 + +#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 + +#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 + +#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c + +#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 + +#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038 +#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f +#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK; +} +#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040 + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c +#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f +#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; +} +#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040 +#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6 +static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK; +} + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040 +#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff +#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK; +} + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044 +#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff +#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK; +} + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048 + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050 + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054 + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058 + +#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c + +#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 + +#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 + +#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068 +#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098 + +#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c + +#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 + +#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4 + +#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8 + +#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac + +#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0 + +#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4 + +#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8 + +#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc + +#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0 +#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001 + +#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4 + +#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8 + +#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc + +#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0 + +#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4 + #endif /* DSI_XML */ diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h index 695f99d4bec2..728152f3ef48 100644 --- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h +++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h @@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) -- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23) +- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23) Copyright (C) 2013-2014 by the following authors: - Rob Clark (robclark) diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h index 50ff9851d73d..26f268e2dd3d 100644 --- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h +++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h @@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) -- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23) +- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23) Copyright (C) 2013 by the following authors: - Rob Clark (robclark) diff --git a/drivers/gpu/drm/msm/edp/edp.xml.h b/drivers/gpu/drm/msm/edp/edp.xml.h index a29f1df15143..f9c71dceb5e2 100644 --- a/drivers/gpu/drm/msm/edp/edp.xml.h +++ b/drivers/gpu/drm/msm/edp/edp.xml.h @@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) -- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23) +- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23) -Copyright (C) 2013-2014 by the following authors: +Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) Permission is hereby granted, free of charge, to any person obtaining @@ -288,5 +288,92 @@ static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + #define REG_EDP_PHY_GLB_PHY_STATUS 0x00000598 +#define REG_EDP_28nm_PHY_PLL_REFCLK_CFG 0x00000000 + +#define REG_EDP_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 + +#define REG_EDP_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 + +#define REG_EDP_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c + +#define REG_EDP_28nm_PHY_PLL_VREG_CFG 0x00000010 + +#define REG_EDP_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 + +#define REG_EDP_28nm_PHY_PLL_DMUX_CFG 0x00000018 + +#define REG_EDP_28nm_PHY_PLL_AMUX_CFG 0x0000001c + +#define REG_EDP_28nm_PHY_PLL_GLB_CFG 0x00000020 +#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 +#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 +#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 +#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 + +#define REG_EDP_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 + +#define REG_EDP_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 + +#define REG_EDP_28nm_PHY_PLL_LPFR_CFG 0x0000002c + +#define REG_EDP_28nm_PHY_PLL_LPFC1_CFG 0x00000030 + +#define REG_EDP_28nm_PHY_PLL_LPFC2_CFG 0x00000034 + +#define REG_EDP_28nm_PHY_PLL_SDM_CFG0 0x00000038 + +#define REG_EDP_28nm_PHY_PLL_SDM_CFG1 0x0000003c + +#define REG_EDP_28nm_PHY_PLL_SDM_CFG2 0x00000040 + +#define REG_EDP_28nm_PHY_PLL_SDM_CFG3 0x00000044 + +#define REG_EDP_28nm_PHY_PLL_SDM_CFG4 0x00000048 + +#define REG_EDP_28nm_PHY_PLL_SSC_CFG0 0x0000004c + +#define REG_EDP_28nm_PHY_PLL_SSC_CFG1 0x00000050 + +#define REG_EDP_28nm_PHY_PLL_SSC_CFG2 0x00000054 + +#define REG_EDP_28nm_PHY_PLL_SSC_CFG3 0x00000058 + +#define REG_EDP_28nm_PHY_PLL_LKDET_CFG0 0x0000005c + +#define REG_EDP_28nm_PHY_PLL_LKDET_CFG1 0x00000060 + +#define REG_EDP_28nm_PHY_PLL_LKDET_CFG2 0x00000064 + +#define REG_EDP_28nm_PHY_PLL_TEST_CFG 0x00000068 +#define EDP_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG0 0x0000006c + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG1 0x00000070 + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG2 0x00000074 + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG3 0x00000078 + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG4 0x0000007c + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG5 0x00000080 + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG6 0x00000084 + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG7 0x00000088 + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG8 0x0000008c + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG9 0x00000090 + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG10 0x00000094 + +#define REG_EDP_28nm_PHY_PLL_CAL_CFG11 0x00000098 + +#define REG_EDP_28nm_PHY_PLL_EFUSE_CFG 0x0000009c + +#define REG_EDP_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 + #endif /* EDP_XML */ diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h index 350988740e9f..e6f034808371 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h @@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) -- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23) +- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23) Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) @@ -750,5 +750,92 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) #define REG_HDMI_8x74_BIST_PATN3 0x00000048 +#define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 + +#define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 + +#define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 + +#define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c + +#define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010 + +#define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 + +#define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018 + +#define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c + +#define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020 +#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 +#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 +#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 +#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 + +#define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 + +#define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 + +#define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c + +#define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 + +#define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 + +#define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038 + +#define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c + +#define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040 + +#define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044 + +#define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048 + +#define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c + +#define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050 + +#define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054 + +#define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058 + +#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c + +#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 + +#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 + +#define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068 +#define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070 + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074 + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078 + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080 + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084 + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088 + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090 + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094 + +#define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098 + +#define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c + +#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 + #endif /* HDMI_XML */ diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h index 43bb54a9afbf..978c3f70872a 100644 --- a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h +++ b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h @@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) -- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23) +- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23) Copyright (C) 2013 by the following authors: - Rob Clark (robclark) diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h index 1d39174d91fb..153fc487d683 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h @@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) -- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23) +- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23) -Copyright (C) 2013-2014 by the following authors: +Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) Permission is hereby granted, free of charge, to any person obtaining @@ -680,18 +680,18 @@ static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK; } -static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } -#define MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK 0xffff0000 -#define MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT 16 -static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val) +static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } +#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000 +#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT 16 +static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val) { - return ((val) << MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK; + return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK; } -#define MDP4_PIPE_FRAME_SIZE_WIDTH__MASK 0x0000ffff -#define MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT 0 -static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val) +#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff +#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0 +static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val) { - return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_FRAME_SIZE_WIDTH__MASK; + return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK; } static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h index b9a4ded6e400..50e17527e2e5 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h @@ -8,9 +8,17 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp5.xml ( 29312 bytes, from 2015-03-23 21:18:48) -- /local/mnt2/workspace2/sviau/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2014-06-02 18:31:15) -- /local/mnt2/workspace2/sviau/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2015-03-23 20:38:49) +- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) +- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23) +- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23) Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) @@ -120,6 +128,21 @@ enum mdp5_data_format { DATA_FORMAT_YUV = 1, }; +enum mdp5_block_size { + BLOCK_SIZE_64 = 0, + BLOCK_SIZE_128 = 1, +}; + +enum mdp5_rotate_mode { + ROTATE_0 = 0, + ROTATE_90 = 1, +}; + +enum mdp5_chroma_downsample_method { + DS_MTHD_NO_PIXEL_DROP = 0, + DS_MTHD_PIXEL_DROP = 1, +}; + #define MDP5_IRQ_WB_0_DONE 0x00000001 #define MDP5_IRQ_WB_1_DONE 0x00000002 #define MDP5_IRQ_WB_2_DONE 0x00000010 @@ -314,19 +337,19 @@ static inline uint32_t MDP5_MDP_IGC_LUT_REG_VAL(uint32_t val) #define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000 #define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000 -#define REG_MDP5_SPLIT_DPL_EN 0x000003f4 +static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_EN(uint32_t i0) { return 0x000002f4 + __offset_MDP(i0); } -#define REG_MDP5_SPLIT_DPL_UPPER 0x000003f8 -#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002 -#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004 -#define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010 -#define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100 +static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_UPPER(uint32_t i0) { return 0x000002f8 + __offset_MDP(i0); } +#define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002 +#define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004 +#define MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010 +#define MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100 -#define REG_MDP5_SPLIT_DPL_LOWER 0x000004f0 -#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002 -#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004 -#define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010 -#define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100 +static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_LOWER(uint32_t i0) { return 0x000003f0 + __offset_MDP(i0); } +#define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002 +#define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004 +#define MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010 +#define MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100 static inline uint32_t __offset_CTL(uint32_t idx) { @@ -782,7 +805,7 @@ static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000 #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK 0x00180000 #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT 19 -static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_sspp_fetch_type val) +static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_fetch_type val) { return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK; } @@ -1234,6 +1257,351 @@ static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x000000 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); } +static inline uint32_t __offset_WB(uint32_t idx) +{ + switch (idx) { + default: return INVALID_IDX(idx); + } +} +static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } +#define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK 0x00000003 +#define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT 0 +static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK; +} +#define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK 0x0000000c +#define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT 2 +static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK; +} +#define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK 0x00000030 +#define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT 4 +static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK; +} +#define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK 0x000000c0 +#define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT 6 +static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK; +} +#define MDP5_WB_DST_FORMAT_DSTC3_EN 0x00000100 +#define MDP5_WB_DST_FORMAT_DST_BPP__MASK 0x00000600 +#define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT 9 +static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK; +} +#define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK 0x00003000 +#define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT 12 +static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK; +} +#define MDP5_WB_DST_FORMAT_DST_ALPHA_X 0x00004000 +#define MDP5_WB_DST_FORMAT_PACK_TIGHT 0x00020000 +#define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB 0x00040000 +#define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK 0x00180000 +#define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT 19 +static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK; +} +#define MDP5_WB_DST_FORMAT_DST_DITHER_EN 0x00400000 +#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK 0x03800000 +#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT 23 +static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK; +} +#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK 0x3c000000 +#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT 26 +static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK; +} +#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK 0xc0000000 +#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT 30 +static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK; +} + +static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); } +#define MDP5_WB_DST_OP_MODE_BWC_ENC_EN 0x00000001 +#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK 0x00000006 +#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT 1 +static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK; +} +#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK 0x00000010 +#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT 4 +static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK; +} +#define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK 0x00000020 +#define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT 5 +static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK; +} +#define MDP5_WB_DST_OP_MODE_ROT_EN 0x00000040 +#define MDP5_WB_DST_OP_MODE_CSC_EN 0x00000100 +#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00000200 +#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 9 +static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK; +} +#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00000400 +#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 10 +static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK; +} +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN 0x00000800 +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK 0x00001000 +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12 +static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK; +} +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK 0x00002000 +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13 +static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK; +} +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK 0x00004000 +#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14 +static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val) +{ + return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK; +} + +static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); } +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK 0x00000003 +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT 0 +static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val) +{ + return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK; +} +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK 0x00000300 +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT 8 +static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val) +{ + return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK; +} +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK 0x00030000 +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT 16 +static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val) +{ + return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK; +} +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK 0x03000000 +#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT 24 +static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val) +{ + return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK; +} + +static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); } +#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK 0x0000ffff +#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT 0 +static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK; +} +#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK 0xffff0000 +#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT 16 +static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK; +} + +static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); } +#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK 0x0000ffff +#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT 0 +static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK; +} +#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK 0xffff0000 +#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT 16 +static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val) +{ + return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK; +} + +static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); } +#define MDP5_WB_OUT_SIZE_DST_W__MASK 0x0000ffff +#define MDP5_WB_OUT_SIZE_DST_W__SHIFT 0 +static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val) +{ + return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK; +} +#define MDP5_WB_OUT_SIZE_DST_H__MASK 0xffff0000 +#define MDP5_WB_OUT_SIZE_DST_H__SHIFT 16 +static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val) +{ + return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK; +} + +static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); } + +static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); } +#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff +#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK; +} +#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000 +#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT 16 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); } +#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff +#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK; +} +#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000 +#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT 16 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); } +#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff +#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK; +} +#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000 +#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT 16 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); } +#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff +#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK; +} +#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000 +#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT 16 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); } +#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff +#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } + +static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } +#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK 0x000000ff +#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK; +} +#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK 0x0000ff00 +#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT 8 +static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } + +static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } +#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK 0x000000ff +#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK; +} +#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK 0x0000ff00 +#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT 8 +static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } + +static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } +#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK 0x000001ff +#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK; +} + +static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } + +static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } +#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK 0x000001ff +#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT 0 +static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val) +{ + return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK; +} + static inline uint32_t __offset_INTF(uint32_t idx) { switch (idx) { diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c index e4e89567f51d..f4eeaf032f2e 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c @@ -281,22 +281,22 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, * start signal for the slave encoder */ if (intf_num == 1) - data |= MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX; + data |= MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX; else if (intf_num == 2) - data |= MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX; + data |= MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX; else return -EINVAL; /* Smart Panel, Sync mode */ - data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL; + data |= MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL; /* Make sure clocks are on when connectors calling this function. */ mdp5_enable(mdp5_kms); - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data); + mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), data); - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, - MDP5_SPLIT_DPL_LOWER_SMART_PANEL); - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); + mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0), + MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL); + mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1); mdp5_disable(mdp5_kms); return 0; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c index 1188f4bf1e60..f58c9b63a710 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c @@ -304,9 +304,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder, * to use the master's enable signal for the slave encoder. */ if (intf_num == 1) - data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC; + data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC; else if (intf_num == 2) - data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC; + data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC; else return -EINVAL; @@ -315,9 +315,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder, mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0), MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN); /* Dumb Panel, Sync mode */ - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0); - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data); - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); + mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), 0); + mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0), data); + mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1); mdp5_disable(mdp5_kms); return 0; diff --git a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h index a1d35f162c7f..641d036c5bcb 100644 --- a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h @@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23) - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) -- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) +- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23) +- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23) -Copyright (C) 2013-2014 by the following authors: +Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) Permission is hereby granted, free of charge, to any person obtaining @@ -52,7 +52,7 @@ enum mdp_chroma_samp_type { CHROMA_420 = 3, }; -enum mdp_sspp_fetch_type { +enum mdp_fetch_type { MDP_PLANE_INTERLEAVED = 0, MDP_PLANE_PLANAR = 1, MDP_PLANE_PSEUDO_PLANAR = 2, diff --git a/drivers/gpu/drm/msm/mdp/mdp_kms.h b/drivers/gpu/drm/msm/mdp/mdp_kms.h index 5ae4039d68e4..2d3428cb74d0 100644 --- a/drivers/gpu/drm/msm/mdp/mdp_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp_kms.h @@ -88,7 +88,7 @@ struct mdp_format { uint8_t unpack[4]; bool alpha_enable, unpack_tight; uint8_t cpp, unpack_count; - enum mdp_sspp_fetch_type fetch_type; + enum mdp_fetch_type fetch_type; enum mdp_chroma_samp_type chroma_sample; }; #define to_mdp_format(x) container_of(x, struct mdp_format, base) -- cgit v1.2.3 From 570655b09b065d2fff1b8ab9bdb8308f4c5a05a3 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Fri, 30 Jan 2015 20:18:11 +0530 Subject: drm/msm/mdp4: Support NV12MT format in mdp4 Using fb modifier flag, support NV12MT format in MDP4. v2: - rework the modifier's description [Daniel Vetter's comment] - drop .set_mode_config() callback [Rob Clark's comment] v3: - change VENDOR's name and restrict usage to NV12 [pointed by Daniel] Signed-off-by: Rob Clark --- drivers/gpu/drm/drm_crtc.c | 18 ++++++++++++++++++ drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 2 ++ drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 22 ++++++++++++++++++++++ include/uapi/drm/drm_fourcc.h | 15 +++++++++++++++ 4 files changed, 57 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 77f87b23a6e7..b69ed97d447c 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -3255,6 +3255,24 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r) r->modifier[i], i); return -EINVAL; } + + /* modifier specific checks: */ + switch (r->modifier[i]) { + case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE: + /* NOTE: the pitch restriction may be lifted later if it turns + * out that no hw has this restriction: + */ + if (r->pixel_format != DRM_FORMAT_NV12 || + width % 128 || height % 32 || + r->pitches[i] % 128) { + DRM_DEBUG_KMS("bad modifier data for plane %d\n", i); + return -EINVAL; + } + break; + + default: + break; + } } for (i = num_planes; i < 4; i++) { diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c index d847b9436194..88a75cbc8f71 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c @@ -119,6 +119,8 @@ static int mdp4_hw_init(struct msm_kms *kms) if (mdp4_kms->rev > 1) mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); + dev->mode_config.allow_fb_modifiers = true; + out: pm_runtime_put_sync(dev->dev); diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c index dbc068988377..0d1dbb737933 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c @@ -33,6 +33,21 @@ struct mdp4_plane { }; #define to_mdp4_plane(x) container_of(x, struct mdp4_plane, base) +/* MDP format helper functions */ +static inline +enum mdp4_frame_format mdp4_get_frame_format(struct drm_framebuffer *fb) +{ + bool is_tile = false; + + if (fb->modifier[1] == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE) + is_tile = true; + + if (fb->pixel_format == DRM_FORMAT_NV12 && is_tile) + return FRAME_TILE_YCBCR_420; + + return FRAME_LINEAR; +} + static void mdp4_plane_set_scanout(struct drm_plane *plane, struct drm_framebuffer *fb); static int mdp4_plane_mode_set(struct drm_plane *plane, @@ -205,6 +220,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane, uint32_t op_mode = 0; uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT; uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT; + enum mdp4_frame_format frame_type = mdp4_get_frame_format(fb); if (!(crtc && fb)) { DBG("%s: disabled!", mdp4_plane->name); @@ -304,6 +320,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane, MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) | MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) | MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) | + MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) | COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT)); mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe), @@ -324,6 +341,11 @@ static int mdp4_plane_mode_set(struct drm_plane *plane, mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step); mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step); + if (frame_type != FRAME_LINEAR) + mdp4_write(mdp4_kms, REG_MDP4_PIPE_SSTILE_FRAME_SIZE(pipe), + MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(src_w) | + MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(src_h)); + return 0; } diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 07735822a28f..2f295cde657e 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -207,4 +207,19 @@ */ #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) +/* + * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks + * + * Macroblocks are laid in a Z-shape, and each pixel data is following the + * standard NV12 style. + * As for NV12, an image is the result of two frame buffers: one for Y, + * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). + * Alignment requirements are (for each buffer): + * - multiple of 128 pixels for the width + * - multiple of 32 pixels for the height + * + * For more information: see http://linuxtv.org/downloads/v4l-dvb-apis/re32.html + */ +#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) + #endif /* DRM_FOURCC_H */ -- cgit v1.2.3 From 6490ad47404539b479ca33f96793c4624bef2924 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 4 Jun 2015 10:26:37 -0400 Subject: drm/msm: clarify downstream bus scaling A few spots in the driver have support for downstream android CONFIG_MSM_BUS_SCALING. This is mainly to simplify backporting the driver for various devices which do not have sufficient upstream kernel support. But the intentionally dead code seems to cause some confusion. Rename the #define to make this more clear. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +- drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c | 2 +- drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h | 2 +- drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c | 2 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 2 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 2 +- drivers/gpu/drm/msm/msm_gpu.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 2 +- 10 files changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index be83dee83d08..37b18e2c9a3c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -19,7 +19,7 @@ #include "adreno_gpu.h" -#if defined(CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF) +#if defined(DOWNSTREAM_CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF) # include #endif @@ -240,7 +240,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev = ADRENO_REV(3, 0, 5, 0); } -# ifdef CONFIG_MSM_BUS_SCALING +# ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING config.bus_scale_table = pdata->bus_scale_table; # endif #endif diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index a1e861316590..031579e1481f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -334,7 +334,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, gpu->fast_rate = config->fast_rate; gpu->slow_rate = config->slow_rate; gpu->bus_freq = config->bus_freq; -#ifdef CONFIG_MSM_BUS_SCALING +#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING gpu->bus_scale_table = config->bus_scale_table; #endif diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 2b6b57baf6fd..ab7f40bef9f1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -167,7 +167,7 @@ struct adreno_gpu { struct adreno_platform_config { struct adreno_rev rev; uint32_t fast_rate, slow_rate, bus_freq; -#ifdef CONFIG_MSM_BUS_SCALING +#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING struct msm_bus_scale_pdata *bus_scale_table; #endif }; diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c index 7896323b2631..89614c6a6c1b 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c @@ -38,7 +38,7 @@ static struct mdp4_kms *get_kms(struct drm_encoder *encoder) return to_mdp4_kms(to_mdp_kms(priv->kms)); } -#ifdef CONFIG_MSM_BUS_SCALING +#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING #include /* not ironically named at all.. no, really.. */ static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder) diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h index 0a5c58bde7a9..a537c078593b 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h @@ -229,7 +229,7 @@ static inline struct clk *mpd4_lvds_pll_init(struct drm_device *dev) } #endif -#ifdef CONFIG_MSM_BUS_SCALING +#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING static inline int match_dev_name(struct device *dev, void *data) { return !strcmp(dev_name(dev), data); diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c index 60ec8222c9f6..c04843376c54 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c @@ -38,7 +38,7 @@ static struct mdp4_kms *get_kms(struct drm_encoder *encoder) return to_mdp4_kms(to_mdp_kms(priv->kms)); } -#ifdef CONFIG_MSM_BUS_SCALING +#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING #include static void bs_init(struct mdp4_lcdc_encoder *mdp4_lcdc_encoder) { diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c index f4eeaf032f2e..5d321d9b10e8 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c @@ -30,7 +30,7 @@ static struct mdp5_kms *get_kms(struct drm_encoder *encoder) return to_mdp5_kms(to_mdp_kms(priv->kms)); } -#ifdef CONFIG_MSM_BUS_SCALING +#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING #include #include #include diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c index f58c9b63a710..84d0a7b92918 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c @@ -36,7 +36,7 @@ static struct mdp5_kms *get_kms(struct drm_encoder *encoder) return to_mdp5_kms(to_mdp_kms(priv->kms)); } -#ifdef CONFIG_MSM_BUS_SCALING +#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING #include #include #include diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 4a0dce587745..98977ab130ee 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -24,7 +24,7 @@ * Power Management: */ -#ifdef CONFIG_MSM_BUS_SCALING +#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING #include static void bs_init(struct msm_gpu *gpu) { diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index fd1e4b4a6d40..2c46f1d820e0 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -103,7 +103,7 @@ struct msm_gpu { struct clk *ebi1_clk, *grp_clks[5]; uint32_t fast_rate, slow_rate, bus_freq; -#ifdef CONFIG_MSM_BUS_SCALING +#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING struct msm_bus_scale_pdata *bus_scale_table; uint32_t bsc; #endif -- cgit v1.2.3 From de558cd2ae2e9999d0b6328c22c398ff85b6327c Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 6 May 2015 13:14:30 -0400 Subject: drm/msm: adreno a306 support As found in apq8016 (used in DragonBoard 410c) and msm8916. Note that numerically a306 is actually 307 (since a305c already claimed 306). Nice and confusing. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 12 +++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 8 ++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++++++ drivers/gpu/drm/msm/msm_gpu.c | 1 + drivers/gpu/drm/msm/msm_gpu.h | 2 +- 5 files changed, 25 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 0f0c45665dbd..fd266ed963b6 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -93,7 +93,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu) /* Set up AOOO: */ gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c); - + } else if (adreno_is_a306(adreno_gpu)) { + gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); + gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a); + gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a); } else if (adreno_is_a320(adreno_gpu)) { /* Set up 16 deep read/write request queues: */ gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); @@ -186,7 +189,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001); /* Enable Clock gating: */ - if (adreno_is_a320(adreno_gpu)) + if (adreno_is_a306(adreno_gpu)) + gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa); + else if (adreno_is_a320(adreno_gpu)) gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff); else if (adreno_is_a330v2(adreno_gpu)) gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa); @@ -271,7 +276,8 @@ static int a3xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]); /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */ - if (adreno_is_a305(adreno_gpu) || adreno_is_a320(adreno_gpu)) { + if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) || + adreno_is_a320(adreno_gpu)) { gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) | AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) | diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 37b18e2c9a3c..1ea2df524fac 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -41,6 +41,14 @@ static const struct adreno_info gpulist[] = { .pfpfw = "a300_pfp.fw", .gmem = SZ_256K, .init = a3xx_gpu_init, + }, { + .rev = ADRENO_REV(3, 0, 6, 0), + .revn = 307, /* because a305c is revn==306 */ + .name = "A306", + .pm4fw = "a300_pm4.fw", + .pfpfw = "a300_pfp.fw", + .gmem = SZ_128K, + .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), .revn = 320, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index ab7f40bef9f1..0a312e9d3afd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -197,6 +197,12 @@ static inline bool adreno_is_a305(struct adreno_gpu *gpu) return gpu->revn == 305; } +static inline bool adreno_is_a306(struct adreno_gpu *gpu) +{ + /* yes, 307, because a305c is 306 */ + return gpu->revn == 307; +} + static inline bool adreno_is_a320(struct adreno_gpu *gpu) { return gpu->revn == 320; diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 98977ab130ee..4016aef56c50 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -522,6 +522,7 @@ static irqreturn_t irq_handler(int irq, void *data) static const char *clk_names[] = { "src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk", + "alt_mem_iface_clk", }; int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 2c46f1d820e0..7b3ec21d5d77 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -100,7 +100,7 @@ struct msm_gpu { /* Power Control: */ struct regulator *gpu_reg, *gpu_cx; - struct clk *ebi1_clk, *grp_clks[5]; + struct clk *ebi1_clk, *grp_clks[6]; uint32_t fast_rate, slow_rate, bus_freq; #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING -- cgit v1.2.3 From d735fdc35b4433abb736e843cfd2d34913344b3a Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Tue, 12 May 2015 11:29:40 -0400 Subject: drm/msm: workaround for missing irq on a306/8x16 Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 031579e1481f..a3b54cc76495 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -176,6 +176,17 @@ int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, OUT_PKT3(ring, CP_INTERRUPT, 1); OUT_RING(ring, 0x80000000); + /* Workaround for missing irq issue on 8x16/a306. Unsure if the + * root cause is a platform issue or some a306 quirk, but this + * keeps things humming along: + */ + if (adreno_is_a306(adreno_gpu)) { + OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); + OUT_RING(ring, 0x00000000); + OUT_PKT3(ring, CP_INTERRUPT, 1); + OUT_RING(ring, 0x80000000); + } + #if 0 if (adreno_is_a3xx(adreno_gpu)) { /* Dummy set-constant to trigger context rollover */ -- cgit v1.2.3 From e5989ee1342a686764934fff01e743aa06803d21 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 14 May 2015 20:21:37 -0400 Subject: drm/msm/mdp5: fix for crash in disable path Seems like disable can race with complete_flip() in process of disabling a crtc, leading to: [ 49.065364] Call trace: [ 49.071441] [] mdp5_ctl_blend+0x20/0x1c0 [ 49.073788] [] mdp5_crtc_disable+0x3c/0xa8 [ 49.079348] [] disable_outputs.isra.4+0x11c/0x220 [ 49.085164] [] drm_atomic_helper_commit_modeset_disables+0x14/0x38 [ 49.091155] [] complete_commit+0x40/0xb8 [ 49.099136] [] msm_atomic_commit+0x364/0x398 [ 49.104430] [] drm_atomic_commit+0x3c/0x70 [ 49.110249] [] drm_atomic_helper_set_config+0x1b0/0x3e0 [ 49.116065] [] drm_mode_set_config_internal+0x64/0xf8 [ 49.122746] [] drm_framebuffer_remove+0xe4/0x128 [ 49.129171] [] drm_mode_rmfb+0xc0/0x100 [ 49.135420] [] drm_ioctl+0x258/0x4d0 [ 49.140889] [] do_vfs_ioctl+0x338/0x5d0 [ 49.145921] [] SyS_ioctl+0x88/0xa0 It makes no sense to free the ctl without disabling all stages, so lets just move them together to avoid the crash. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index c1530772187d..13dd7dd853a9 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -143,6 +143,8 @@ static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) } if (mdp5_crtc->ctl && !crtc->state->enable) { + /* set STAGE_UNUSED for all layers */ + mdp5_ctl_blend(mdp5_crtc->ctl, mdp5_crtc->lm, 0x00000000); mdp5_ctl_release(mdp5_crtc->ctl); mdp5_crtc->ctl = NULL; } @@ -274,9 +276,6 @@ static void mdp5_crtc_disable(struct drm_crtc *crtc) if (WARN_ON(!mdp5_crtc->enabled)) return; - /* set STAGE_UNUSED for all layers */ - mdp5_ctl_blend(mdp5_crtc->ctl, mdp5_crtc->lm, 0x00000000); - mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); mdp5_disable(mdp5_kms); -- cgit v1.2.3 From 9f68ef90aa383c01e143889989f20577605ca4f6 Mon Sep 17 00:00:00 2001 From: Nicholas Mc Guire Date: Sat, 4 Apr 2015 04:39:07 +0200 Subject: drm/msm: fixup wait_for_completion_timeout handling wait_for_completion_timeout return >= 0 but never negative so the check logic looks inconsistent. Further the return value of wait_for_completion_timeout was being passed up the call chain but the x call sites as drm_dp_i2c_do_msg()/drm_dp_dpcd_access() check for < 0 thus timeout was being treated as success case. drivers/gpu/drm/drm_dp_helper.c:drm_dp_i2c_do_msg() mutex_lock(&aux->hw_mutex); ret = aux->transfer(aux, msg); mutex_unlock(&aux->hw_mutex); if (ret < 0) { logic in edp_aux_transfer() seems incorrect as it could return 0 (timeout) but checks of <= 0 to indicate error so the return probably should be -ETIMEDOUT in case wait_for_completion_timeout returns 0 (timeout occurred). Signed-off-by: Nicholas Mc Guire Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/edp/edp_aux.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/edp/edp_aux.c b/drivers/gpu/drm/msm/edp/edp_aux.c index 208f9d47f82e..5f77bf0adf1d 100644 --- a/drivers/gpu/drm/msm/edp/edp_aux.c +++ b/drivers/gpu/drm/msm/edp/edp_aux.c @@ -119,6 +119,7 @@ ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux, struct drm_dp_aux_msg *msg) { struct edp_aux *aux = to_edp_aux(drm_aux); ssize_t ret; + unsigned long time_left; bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); bool read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ); @@ -147,15 +148,16 @@ ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux, struct drm_dp_aux_msg *msg) goto unlock_exit; DBG("wait_for_completion"); - ret = wait_for_completion_timeout(&aux->msg_comp, 300); - if (ret <= 0) { + time_left = wait_for_completion_timeout(&aux->msg_comp, 300); + if (!time_left) { /* * Clear GO and reset AUX channel * to cancel the current transaction. */ edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0); msm_edp_aux_ctrl(aux, 1); - pr_err("%s: aux timeout, %zd\n", __func__, ret); + pr_err("%s: aux timeout, %lu\n", __func__, time_left); + ret = -ETIMEDOUT; goto unlock_exit; } DBG("completion"); -- cgit v1.2.3 From 84c3b87b8b669e2d42209ba9fc9ddeffb90b3f17 Mon Sep 17 00:00:00 2001 From: Nicholas Mc Guire Date: Sat, 4 Apr 2015 04:39:08 +0200 Subject: drm/msm: fix HZ dependency of timeout The timeout is passed as a constant which makes it HZ dependent because jiffies are expected so it should be converted to jiffies. The actual value is not clear from the code - my best guess is that this should be 300 milliseconds given that other timeouts are in milliseconds based on looking at other drm drivers (e.g. exynos_drm_dsi.c:356 300ms, tegra/dpaux.c:188 250ms) - this needs to be confirmed by someone who knows the details of the driver. Signed-off-by: Nicholas Mc Guire Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/edp/edp_aux.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/edp/edp_aux.c b/drivers/gpu/drm/msm/edp/edp_aux.c index 5f77bf0adf1d..d950839edf91 100644 --- a/drivers/gpu/drm/msm/edp/edp_aux.c +++ b/drivers/gpu/drm/msm/edp/edp_aux.c @@ -148,7 +148,8 @@ ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux, struct drm_dp_aux_msg *msg) goto unlock_exit; DBG("wait_for_completion"); - time_left = wait_for_completion_timeout(&aux->msg_comp, 300); + time_left = wait_for_completion_timeout(&aux->msg_comp, + msecs_to_jiffies(300)); if (!time_left) { /* * Clear GO and reset AUX channel -- cgit v1.2.3 From a7c07690f25c69aa6a68565df904f1b77da725da Mon Sep 17 00:00:00 2001 From: Nicholas Mc Guire Date: Sat, 4 Apr 2015 04:39:09 +0200 Subject: drm/msm: drop redundant output in debug message wait_for_completion_timeout returns 0 in case of timeout so printing the return value here will always yield 0 and is therefor redundant - dropped. Signed-off-by: Nicholas Mc Guire Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/edp/edp_aux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/edp/edp_aux.c b/drivers/gpu/drm/msm/edp/edp_aux.c index d950839edf91..c760ea2206d0 100644 --- a/drivers/gpu/drm/msm/edp/edp_aux.c +++ b/drivers/gpu/drm/msm/edp/edp_aux.c @@ -157,7 +157,7 @@ ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux, struct drm_dp_aux_msg *msg) */ edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0); msm_edp_aux_ctrl(aux, 1); - pr_err("%s: aux timeout, %lu\n", __func__, time_left); + pr_err("%s: aux timeout,\n", __func__); ret = -ETIMEDOUT; goto unlock_exit; } -- cgit v1.2.3 From 07549dfbd9f218496eebf7d732bf3ab1c95882c2 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Fri, 5 Jun 2015 12:10:23 -0400 Subject: drm/msm/edp: fix build warning - missing prototype Fix build warning when building edp/edp_aux.o due to missing prototype for edp_aux_transfer. This function is only used in edp_aux.c so just make it static. Reported-by: Nicholas Mc Guire Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/edp/edp_aux.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/edp/edp_aux.c b/drivers/gpu/drm/msm/edp/edp_aux.c index c760ea2206d0..82789dd249ee 100644 --- a/drivers/gpu/drm/msm/edp/edp_aux.c +++ b/drivers/gpu/drm/msm/edp/edp_aux.c @@ -115,7 +115,8 @@ static int edp_msg_fifo_rx(struct edp_aux *aux, struct drm_dp_aux_msg *msg) * msm_edp_aux_ctrl() running concurrently in other threads, i.e. * start transaction only when AUX channel is fully enabled. */ -ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux, struct drm_dp_aux_msg *msg) +static ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux, + struct drm_dp_aux_msg *msg) { struct edp_aux *aux = to_edp_aux(drm_aux); ssize_t ret; -- cgit v1.2.3 From f28730c84fa987ba51e164cc4ecf2dac8d6dace1 Mon Sep 17 00:00:00 2001 From: jilai wang Date: Tue, 7 Apr 2015 13:51:32 -0400 Subject: drm/msm: Call drm_prime_gem_destroy to clean up imported GEM object If the GEM object is imported, drm_prime_gem_destroy needs to be called to clean up dma buffer related information. Signed-off-by: Jilai Wang Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_gem.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 52839769eb6c..dfc74a5736a3 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -540,6 +540,7 @@ void msm_gem_free_object(struct drm_gem_object *obj) if (msm_obj->pages) drm_free_large(msm_obj->pages); + drm_prime_gem_destroy(obj, msm_obj->sgt); } else { vunmap(msm_obj->vaddr); put_pages(obj); -- cgit v1.2.3 From 65c5e5426dfc474b2f0462cfc100c7608ab8a627 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Wed, 8 Apr 2015 11:37:40 +0530 Subject: drm/msm: dsi: Provide option to force continuous HS clock Some DSI peripherals rely on the HS clock on DSI clock lane as their clock source. If the clock lane transitions between HS and LP states, it can disrupt the functioning of such peripherals. The mipi dsi mode flag MIPI_DSI_CLOCK_NON_CONTINUOUS already exists for such peripheral drivers. Use it to configure the bit CLKLN_HS_FORCE_REQUEST in DSI_LANE_CTRL. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/dsi/dsi_host.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 649d20d29f92..ae061653ca06 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -787,6 +787,11 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123)); } + + if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) + dsi_write(msm_host, REG_DSI_LANE_CTRL, + DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); + data |= DSI_CTRL_ENABLE; dsi_write(msm_host, REG_DSI_CTRL, data); -- cgit v1.2.3 From a51d01f067b34b138deae6ff86276e807c606876 Mon Sep 17 00:00:00 2001 From: Nicholas Mc Guire Date: Sat, 11 Apr 2015 15:10:36 +0200 Subject: drm/msm: match wait_for_completion_timeout return type return type of wait_for_completion_timeout is unsigned long not int, this patch assigns the return value of wait_for_completion_timeout to an appropriately typed and named variable. Signed-off-by: Nicholas Mc Guire Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/edp/edp_ctrl.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c index 29e52d7c61c0..17ae0cc3db70 100644 --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c @@ -1018,7 +1018,7 @@ static void edp_ctrl_off_worker(struct work_struct *work) { struct edp_ctrl *ctrl = container_of( work, struct edp_ctrl, off_work); - int ret; + unsigned long time_left; mutex_lock(&ctrl->dev_mutex); @@ -1030,11 +1030,11 @@ static void edp_ctrl_off_worker(struct work_struct *work) reinit_completion(&ctrl->idle_comp); edp_state_ctrl(ctrl, EDP_STATE_CTRL_PUSH_IDLE); - ret = wait_for_completion_timeout(&ctrl->idle_comp, + time_left = wait_for_completion_timeout(&ctrl->idle_comp, msecs_to_jiffies(500)); - if (ret <= 0) - DBG("%s: idle pattern timedout, %d\n", - __func__, ret); + if (time_left <= 0) + DBG("%s: idle pattern timedout, %lu\n", + __func__, time_left); edp_state_ctrl(ctrl, 0); -- cgit v1.2.3 From c6d0baf1fdbe32594e6e8bf6870f3951d3cf6415 Mon Sep 17 00:00:00 2001 From: Nicholas Mc Guire Date: Sat, 11 Apr 2015 15:10:37 +0200 Subject: drm/msm: wait_for_completion_timeout return is never negative wait_for_completion_timeout returns >= 0 but never negative - so the error check should be against equality to 0 not <= 0. Signed-off-by: Nicholas Mc Guire Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/edp/edp_ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c index 17ae0cc3db70..43e549ba7258 100644 --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c @@ -1032,7 +1032,7 @@ static void edp_ctrl_off_worker(struct work_struct *work) time_left = wait_for_completion_timeout(&ctrl->idle_comp, msecs_to_jiffies(500)); - if (time_left <= 0) + if (!time_left) DBG("%s: idle pattern timedout, %lu\n", __func__, time_left); -- cgit v1.2.3 From 0c076bffd2575e3b30d63cbb908954cfdef2335a Mon Sep 17 00:00:00 2001 From: Nicholas Mc Guire Date: Sat, 11 Apr 2015 15:10:38 +0200 Subject: drm/msm: drop redundant debug output wait_for_completion_timeout returns 0 in case of timeout and never return < 0 so there is no additional information in printing the value of time_left here as it will always be 0, thus it can be dropped. Signed-off-by: Nicholas Mc Guire Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/edp/edp_ctrl.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c index 43e549ba7258..7991069dd492 100644 --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c @@ -1033,8 +1033,7 @@ static void edp_ctrl_off_worker(struct work_struct *work) time_left = wait_for_completion_timeout(&ctrl->idle_comp, msecs_to_jiffies(500)); if (!time_left) - DBG("%s: idle pattern timedout, %lu\n", - __func__, time_left); + DBG("%s: idle pattern timedout\n", __func__); edp_state_ctrl(ctrl, 0); -- cgit v1.2.3 From 0a5c9aad119c4415e14ece4c17cec66aa572e827 Mon Sep 17 00:00:00 2001 From: Hai Li Date: Tue, 28 Apr 2015 19:35:37 -0400 Subject: drm/msm: Use customized function to wait for atomic commit done MDP FLUSH registers could indicate if the previous flush updates has taken effect at vsync boundary. Making use of this H/W feature can catch the vsync that happened between CRTC atomic_flush and *_wait_for_vblanks, to avoid unnecessary wait. This change allows kms CRTCs to use their own *_wait_for_commit_done functions to wait for FLUSH register cleared at vsync, before commit completion. Signed-off-by: Hai Li Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | 39 ++++++++++++++++++++++ drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 7 ++++ drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h | 1 + drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 55 ++++++++++++++++++++++++++++---- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 11 +++++-- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 3 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 7 ++++ drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 + drivers/gpu/drm/msm/msm_atomic.c | 30 +++++++++++++++-- drivers/gpu/drm/msm/msm_kms.h | 3 ++ 10 files changed, 146 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c index 73afa21822b4..c4bb9d9c7667 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c @@ -51,6 +51,11 @@ struct mdp4_crtc { /* if there is a pending flip, these will be non-null: */ struct drm_pending_vblank_event *event; + /* Bits have been flushed at the last commit, + * used to decide if a vsync has happened since last commit. + */ + u32 flushed_mask; + #define PENDING_CURSOR 0x1 #define PENDING_FLIP 0x2 atomic_t pending; @@ -93,6 +98,8 @@ static void crtc_flush(struct drm_crtc *crtc) DBG("%s: flush=%08x", mdp4_crtc->name, flush); + mdp4_crtc->flushed_mask = flush; + mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); } @@ -537,6 +544,29 @@ static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) crtc_flush(crtc); } +static void mdp4_crtc_wait_for_flush_done(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); + struct mdp4_kms *mdp4_kms = get_kms(crtc); + int ret; + + ret = drm_crtc_vblank_get(crtc); + if (ret) + return; + + ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue, + !(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) & + mdp4_crtc->flushed_mask), + msecs_to_jiffies(50)); + if (ret <= 0) + dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp4_crtc->id); + + mdp4_crtc->flushed_mask = 0; + + drm_crtc_vblank_put(crtc); +} + uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc) { struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); @@ -600,6 +630,15 @@ void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer) mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel); } +void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc) +{ + /* wait_for_flush_done is the only case for now. + * Later we will have command mode CRTC to wait for + * other event. + */ + mdp4_crtc_wait_for_flush_done(crtc); +} + static const char *dma_names[] = { "DMA_P", "DMA_S", "DMA_E", }; diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c index 88a75cbc8f71..531e4acc2a87 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c @@ -159,6 +159,12 @@ static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s mdp4_disable(mdp4_kms); } +static void mdp4_wait_for_crtc_commit_done(struct msm_kms *kms, + struct drm_crtc *crtc) +{ + mdp4_crtc_wait_for_commit_done(crtc); +} + static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate, struct drm_encoder *encoder) { @@ -197,6 +203,7 @@ static const struct mdp_kms_funcs kms_funcs = { .disable_vblank = mdp4_disable_vblank, .prepare_commit = mdp4_prepare_commit, .complete_commit = mdp4_complete_commit, + .wait_for_crtc_commit_done = mdp4_wait_for_crtc_commit_done, .get_format = mdp_get_format, .round_pixclk = mdp4_round_pixclk, .preclose = mdp4_preclose, diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h index a537c078593b..c1ecb9d6bdef 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h @@ -206,6 +206,7 @@ uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc); void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file); void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config); void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer); +void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc); struct drm_crtc *mdp4_crtc_init(struct drm_device *dev, struct drm_plane *plane, int id, int ovlp_id, enum mdp4_dma dma_id); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index 13dd7dd853a9..672ffd4dde94 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -46,6 +46,11 @@ struct mdp5_crtc { /* if there is a pending flip, these will be non-null: */ struct drm_pending_vblank_event *event; + /* Bits have been flushed at the last commit, + * used to decide if a vsync has happened since last commit. + */ + u32 flushed_mask; + #define PENDING_CURSOR 0x1 #define PENDING_FLIP 0x2 atomic_t pending; @@ -82,12 +87,12 @@ static void request_pending(struct drm_crtc *crtc, uint32_t pending) mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank); } -static void crtc_flush(struct drm_crtc *crtc, u32 flush_mask) +static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) { struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); DBG("%s: flush=%08x", mdp5_crtc->name, flush_mask); - mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask); + return mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask); } /* @@ -95,7 +100,7 @@ static void crtc_flush(struct drm_crtc *crtc, u32 flush_mask) * so that we can safely queue unref to current fb (ie. next * vblank we know hw is done w/ previous scanout_fb). */ -static void crtc_flush_all(struct drm_crtc *crtc) +static u32 crtc_flush_all(struct drm_crtc *crtc) { struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct drm_plane *plane; @@ -103,7 +108,7 @@ static void crtc_flush_all(struct drm_crtc *crtc) /* this should not happen: */ if (WARN_ON(!mdp5_crtc->ctl)) - return; + return 0; drm_atomic_crtc_for_each_plane(plane, crtc) { flush_mask |= mdp5_plane_get_flush(plane); @@ -111,7 +116,7 @@ static void crtc_flush_all(struct drm_crtc *crtc) flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm); - crtc_flush(crtc, flush_mask); + return crtc_flush(crtc, flush_mask); } /* if file!=NULL, this is preclose potential cancel-flip path */ @@ -395,7 +400,9 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc) return; blend_setup(crtc); - crtc_flush_all(crtc); + + mdp5_crtc->flushed_mask = crtc_flush_all(crtc); + request_pending(crtc, PENDING_FLIP); } @@ -600,6 +607,32 @@ static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) DBG("%s: error: %08x", mdp5_crtc->name, irqstatus); } +static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); + int ret; + + /* Should not call this function if crtc is disabled. */ + if (!mdp5_crtc->ctl) + return; + + ret = drm_crtc_vblank_get(crtc); + if (ret) + return; + + ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue, + ((mdp5_ctl_get_commit_status(mdp5_crtc->ctl) & + mdp5_crtc->flushed_mask) == 0), + msecs_to_jiffies(50)); + if (ret <= 0) + dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id); + + mdp5_crtc->flushed_mask = 0; + + drm_crtc_vblank_put(crtc); +} + uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc) { struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); @@ -631,6 +664,7 @@ void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf) mdp5_crtc->vblank.irqmask = lm2ppdone(lm); else mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf); + mdp_irq_update(&mdp5_kms->base); mdp5_ctl_set_intf(mdp5_crtc->ctl, intf); @@ -648,6 +682,15 @@ struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc) return WARN_ON(!crtc) ? NULL : mdp5_crtc->ctl; } +void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc) +{ + /* wait_for_flush_done is the only case for now. + * Later we will have command mode CRTC to wait for + * other event. + */ + mdp5_crtc_wait_for_flush_done(crtc); +} + /* initialize crtc */ struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, struct drm_plane *plane, int id) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c index 5488b687c8d1..f2530f224a76 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c @@ -392,8 +392,10 @@ static u32 fix_sw_flush(struct mdp5_ctl *ctl, u32 flush_mask) * CTL registers need to be flushed in some circumstances; if that is the * case, some trigger bits will be present in both flush mask and * ctl->pending_ctl_trigger. + * + * Return H/W flushed bit mask. */ -int mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask) +u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask) { struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm; struct op_mode *pipeline = &ctl->pipeline; @@ -424,7 +426,12 @@ int mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask) refill_start_mask(ctl); } - return 0; + return flush_mask; +} + +u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl) +{ + return ctl_read(ctl, REG_MDP5_CTL_FLUSH(ctl->id)); } void mdp5_ctl_release(struct mdp5_ctl *ctl) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h index 7a62000994a1..4678228c4f14 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h @@ -88,7 +88,8 @@ u32 mdp_ctl_flush_mask_cursor(int cursor_id); u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf); /* @flush_mask: see CTL flush masks definitions below */ -int mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask); +u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask); +u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl); void mdp5_ctl_release(struct mdp5_ctl *ctl); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c index bbacf9d2b738..206f758f7d64 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c @@ -80,6 +80,12 @@ static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s mdp5_disable(mdp5_kms); } +static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms, + struct drm_crtc *crtc) +{ + mdp5_crtc_wait_for_commit_done(crtc); +} + static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, struct drm_encoder *encoder) { @@ -141,6 +147,7 @@ static const struct mdp_kms_funcs kms_funcs = { .disable_vblank = mdp5_disable_vblank, .prepare_commit = mdp5_prepare_commit, .complete_commit = mdp5_complete_commit, + .wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done, .get_format = mdp_get_format, .round_pixclk = mdp5_round_pixclk, .set_split_display = mdp5_set_split_display, diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h index 2c0de174cc09..e0eb24587c84 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h @@ -237,6 +237,7 @@ int mdp5_crtc_get_lm(struct drm_crtc *crtc); struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc); void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file); void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf); +void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc); struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, struct drm_plane *plane, int id); diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index 5b192128cda2..84c0a72b446b 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -84,6 +84,33 @@ static void commit_destroy(struct msm_commit *c) kfree(c); } +static void msm_atomic_wait_for_commit_done(struct drm_device *dev, + struct drm_atomic_state *old_state) +{ + struct drm_crtc *crtc; + struct msm_drm_private *priv = old_state->dev->dev_private; + struct msm_kms *kms = priv->kms; + int ncrtcs = old_state->dev->mode_config.num_crtc; + int i; + + for (i = 0; i < ncrtcs; i++) { + crtc = old_state->crtcs[i]; + + if (!crtc) + continue; + + if (!crtc->state->enable) + continue; + + /* Legacy cursor ioctls are completely unsynced, and userspace + * relies on that (by doing tons of cursor updates). */ + if (old_state->legacy_cursor_update) + continue; + + kms->funcs->wait_for_crtc_commit_done(kms, crtc); + } +} + /* The (potentially) asynchronous part of the commit. At this point * nothing can fail short of armageddon. */ @@ -115,7 +142,7 @@ static void complete_commit(struct msm_commit *c) * not be critical path) */ - drm_atomic_helper_wait_for_vblanks(dev, state); + msm_atomic_wait_for_commit_done(dev, state); drm_atomic_helper_cleanup_planes(dev, state); @@ -139,7 +166,6 @@ static void add_fb(struct msm_commit *c, struct drm_framebuffer *fb) c->fence = max(c->fence, msm_gem_fence(to_msm_bo(obj), MSM_PREP_READ)); } - int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) { diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index a9f17bdb4530..9bcabaada179 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -43,6 +43,9 @@ struct msm_kms_funcs { /* modeset, bracketing atomic_commit(): */ void (*prepare_commit)(struct msm_kms *kms, struct drm_atomic_state *state); void (*complete_commit)(struct msm_kms *kms, struct drm_atomic_state *state); + /* functions to wait for atomic commit completed on each CRTC */ + void (*wait_for_crtc_commit_done)(struct msm_kms *kms, + struct drm_crtc *crtc); /* misc: */ const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format); long (*round_pixclk)(struct msm_kms *kms, unsigned long rate, -- cgit v1.2.3 From 68cdbed90777ed0291214f30a3532a8f795b481e Mon Sep 17 00:00:00 2001 From: Hai Li Date: Tue, 28 Apr 2015 19:35:38 -0400 Subject: drm/msm/mdp5: Wait for PP_DONE irq for command mode CRTC atomic commit CRTCs in DSI command mode data path should wait for pingpong done, instead of vblank, to finish atomic commit. This change is to enable PP_DONE irq on command mode CRTCs and wait for this irq happens before atomic commit completion. Signed-off-by: Hai Li Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 4 -- drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 82 ++++++++++++++++++++----- 2 files changed, 66 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c index 5d321d9b10e8..ee31b16fe7ea 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c @@ -216,16 +216,12 @@ static void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder, static void mdp5_cmd_encoder_disable(struct drm_encoder *encoder) { struct mdp5_cmd_encoder *mdp5_cmd_enc = to_mdp5_cmd_encoder(encoder); - struct mdp5_kms *mdp5_kms = get_kms(encoder); struct mdp5_ctl *ctl = mdp5_crtc_get_ctl(encoder->crtc); struct mdp5_interface *intf = &mdp5_cmd_enc->intf; - int lm = mdp5_crtc_get_lm(encoder->crtc); if (WARN_ON(!mdp5_cmd_enc->enabled)) return; - /* Wait for the last frame done */ - mdp_irq_wait(&mdp5_kms->base, lm2ppdone(lm)); pingpong_tearcheck_disable(encoder); mdp5_ctl_set_encoder_state(ctl, false); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index 672ffd4dde94..dea3d2e559b1 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark * @@ -60,6 +60,11 @@ struct mdp5_crtc { struct mdp_irq vblank; struct mdp_irq err; + struct mdp_irq pp_done; + + struct completion pp_completion; + + bool cmd_mode; struct { /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/ @@ -87,6 +92,12 @@ static void request_pending(struct drm_crtc *crtc, uint32_t pending) mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank); } +static void request_pp_done_pending(struct drm_crtc *crtc) +{ + struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); + reinit_completion(&mdp5_crtc->pp_completion); +} + static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) { struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); @@ -281,6 +292,9 @@ static void mdp5_crtc_disable(struct drm_crtc *crtc) if (WARN_ON(!mdp5_crtc->enabled)) return; + if (mdp5_crtc->cmd_mode) + mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done); + mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); mdp5_disable(mdp5_kms); @@ -300,6 +314,9 @@ static void mdp5_crtc_enable(struct drm_crtc *crtc) mdp5_enable(mdp5_kms); mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err); + if (mdp5_crtc->cmd_mode) + mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done); + mdp5_crtc->enabled = true; } @@ -401,6 +418,15 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc) blend_setup(crtc); + /* PP_DONE irq is only used by command mode for now. + * It is better to request pending before FLUSH and START trigger + * to make sure no pp_done irq missed. + * This is safe because no pp_done will happen before SW trigger + * in command mode. + */ + if (mdp5_crtc->cmd_mode) + request_pp_done_pending(crtc); + mdp5_crtc->flushed_mask = crtc_flush_all(crtc); request_pending(crtc, PENDING_FLIP); @@ -607,6 +633,26 @@ static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) DBG("%s: error: %08x", mdp5_crtc->name, irqstatus); } +static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus) +{ + struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, + pp_done); + + complete(&mdp5_crtc->pp_completion); +} + +static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); + int ret; + + ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion, + msecs_to_jiffies(50)); + if (ret == 0) + dev_warn(dev->dev, "pp done time out, lm=%d\n", mdp5_crtc->lm); +} + static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; @@ -654,16 +700,18 @@ void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf) /* now that we know what irq's we want: */ mdp5_crtc->err.irqmask = intf2err(intf->num); - - /* Register command mode Pingpong done as vblank for now, - * so that atomic commit should wait for it to finish. - * Ideally, in the future, we should take rd_ptr done as vblank, - * and let atomic commit wait for pingpong done for commond mode. - */ - if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND) - mdp5_crtc->vblank.irqmask = lm2ppdone(lm); - else - mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf); + mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf); + + if ((intf->type == INTF_DSI) && + (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) { + mdp5_crtc->pp_done.irqmask = lm2ppdone(lm); + mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq; + mdp5_crtc->cmd_mode = true; + } else { + mdp5_crtc->pp_done.irqmask = 0; + mdp5_crtc->pp_done.irq = NULL; + mdp5_crtc->cmd_mode = false; + } mdp_irq_update(&mdp5_kms->base); @@ -684,11 +732,12 @@ struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc) void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc) { - /* wait_for_flush_done is the only case for now. - * Later we will have command mode CRTC to wait for - * other event. - */ - mdp5_crtc_wait_for_flush_done(crtc); + struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); + + if (mdp5_crtc->cmd_mode) + mdp5_crtc_wait_for_pp_done(crtc); + else + mdp5_crtc_wait_for_flush_done(crtc); } /* initialize crtc */ @@ -709,6 +758,7 @@ struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, spin_lock_init(&mdp5_crtc->lm_lock); spin_lock_init(&mdp5_crtc->cursor.lock); + init_completion(&mdp5_crtc->pp_completion); mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq; mdp5_crtc->err.irq = mdp5_crtc_err_irq; -- cgit v1.2.3 From 73dbf69638b760ce62fe6df4cece983ef28abc13 Mon Sep 17 00:00:00 2001 From: Fabian Frederick Date: Mon, 4 May 2015 19:03:54 +0200 Subject: drm/msm: use IS_ERR() to check msm_ioremap() return msm_ioremap() never returns NULL. There's no need for IS_ERR_OR_NULL() Signed-off-by: Fabian Frederick Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/dsi/dsi_phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy.c b/drivers/gpu/drm/msm/dsi/dsi_phy.c index f0cea8927388..61af19312711 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/dsi_phy.c @@ -300,12 +300,12 @@ struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev, return NULL; phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); - if (IS_ERR_OR_NULL(phy->base)) { + if (IS_ERR(phy->base)) { pr_err("%s: failed to map phy base\n", __func__); return NULL; } phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG"); - if (IS_ERR_OR_NULL(phy->reg_base)) { + if (IS_ERR(phy->reg_base)) { pr_err("%s: failed to map phy regulator base\n", __func__); return NULL; } -- cgit v1.2.3 From bdc80de2a6dbaa0d08c393b4ba8912a0ad4b047f Mon Sep 17 00:00:00 2001 From: Fabian Frederick Date: Mon, 4 May 2015 19:03:55 +0200 Subject: drm/msm: use IS_ERR() to check regulator_get() return regulator_get() never returns NULL. There's no need for IS_ERR_OR_NULL() Signed-off-by: Fabian Frederick Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index ae061653ca06..517e0709b77d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -273,7 +273,7 @@ static const struct dsi_config *dsi_get_config(struct msm_dsi_host *msm_host) u32 major = 0, minor = 0; gdsc_reg = regulator_get(&msm_host->pdev->dev, "gdsc"); - if (IS_ERR_OR_NULL(gdsc_reg)) { + if (IS_ERR(gdsc_reg)) { pr_err("%s: cannot get gdsc\n", __func__); goto fail; } -- cgit v1.2.3 From 825637b9c06cede2a742421b0ea6f24428099af3 Mon Sep 17 00:00:00 2001 From: Hai Li Date: Fri, 15 May 2015 13:04:04 -0400 Subject: drm/msm/dsi: Add DSI PLL clock driver support DSI byte clock and pixel clocks are sourced from DSI PLL. This change adds the DSI PLL source clock driver under common clock framework. This change handles DSI 28nm PLL only. Signed-off-by: Hai Li Signed-off-by: Archit Taneja Signed-off-by: Stephane Viau Signed-off-by: Wentao Xu Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/Kconfig | 7 + drivers/gpu/drm/msm/Makefile | 5 + drivers/gpu/drm/msm/dsi/dsi.h | 3 +- drivers/gpu/drm/msm/dsi/dsi_host.c | 10 +- drivers/gpu/drm/msm/dsi/dsi_phy.c | 3 +- drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 164 ++++++++ drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 89 ++++ drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 652 +++++++++++++++++++++++++++++ 8 files changed, 926 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 0a6f6764a37c..08ba8d0d93f5 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -46,3 +46,10 @@ config DRM_MSM_DSI Choose this option if you have a need for MIPI DSI connector support. +config DRM_MSM_DSI_PLL + bool "Enable DSI PLL driver in MSM DRM" + depends on DRM_MSM_DSI && COMMON_CLK + default y + help + Choose this option to enable DSI PLL driver which provides DSI + source clocks under common clock framework. diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index ab2086783fee..16a81b94d6f0 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -1,4 +1,5 @@ ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm +ccflags-$(CONFIG_DRM_MSM_DSI_PLL) += -Idrivers/gpu/drm/msm/dsi msm-y := \ adreno/adreno_device.o \ @@ -50,10 +51,14 @@ msm-y := \ msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o + msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ dsi/dsi_host.o \ dsi/dsi_manager.o \ dsi/dsi_phy.o \ mdp/mdp5/mdp5_cmd_encoder.o +msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \ + dsi/pll/dsi_pll_28nm.o + obj-$(CONFIG_DRM_MSM) += msm.o diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 10f54d4e379a..321964a6b27e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -103,7 +103,8 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi); struct msm_dsi_phy; enum msm_dsi_phy_type { MSM_DSI_PHY_UNKNOWN, - MSM_DSI_PHY_28NM, + MSM_DSI_PHY_28NM_HPM, + MSM_DSI_PHY_28NM_LP, MSM_DSI_PHY_MAX }; struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev, diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 517e0709b77d..8a246cfa5d19 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -64,7 +64,7 @@ static const struct dsi_config dsi_cfgs[] = { .major = MSM_DSI_VER_MAJOR_6G, .minor = MSM_DSI_6G_VER_MINOR_V1_0, .io_offset = DSI_6G_REG_SHIFT, - .phy_type = MSM_DSI_PHY_28NM, + .phy_type = MSM_DSI_PHY_28NM_HPM, .reg_cfg = { .num = 4, .regs = { @@ -79,7 +79,7 @@ static const struct dsi_config dsi_cfgs[] = { .major = MSM_DSI_VER_MAJOR_6G, .minor = MSM_DSI_6G_VER_MINOR_V1_1, .io_offset = DSI_6G_REG_SHIFT, - .phy_type = MSM_DSI_PHY_28NM, + .phy_type = MSM_DSI_PHY_28NM_HPM, .reg_cfg = { .num = 4, .regs = { @@ -94,7 +94,7 @@ static const struct dsi_config dsi_cfgs[] = { .major = MSM_DSI_VER_MAJOR_6G, .minor = MSM_DSI_6G_VER_MINOR_V1_1_1, .io_offset = DSI_6G_REG_SHIFT, - .phy_type = MSM_DSI_PHY_28NM, + .phy_type = MSM_DSI_PHY_28NM_HPM, .reg_cfg = { .num = 4, .regs = { @@ -109,7 +109,7 @@ static const struct dsi_config dsi_cfgs[] = { .major = MSM_DSI_VER_MAJOR_6G, .minor = MSM_DSI_6G_VER_MINOR_V1_2, .io_offset = DSI_6G_REG_SHIFT, - .phy_type = MSM_DSI_PHY_28NM, + .phy_type = MSM_DSI_PHY_28NM_HPM, .reg_cfg = { .num = 4, .regs = { @@ -124,7 +124,7 @@ static const struct dsi_config dsi_cfgs[] = { .major = MSM_DSI_VER_MAJOR_6G, .minor = MSM_DSI_6G_VER_MINOR_V1_3_1, .io_offset = DSI_6G_REG_SHIFT, - .phy_type = MSM_DSI_PHY_28NM, + .phy_type = MSM_DSI_PHY_28NM_LP, .reg_cfg = { .num = 4, .regs = { diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy.c b/drivers/gpu/drm/msm/dsi/dsi_phy.c index 61af19312711..4403f38bf220 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/dsi_phy.c @@ -311,7 +311,8 @@ struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev, } switch (type) { - case MSM_DSI_PHY_28NM: + case MSM_DSI_PHY_28NM_HPM: + case MSM_DSI_PHY_28NM_LP: dsi_phy_func_init(28nm); break; default: diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c new file mode 100644 index 000000000000..509376fdd112 --- /dev/null +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dsi_pll.h" + +static int dsi_pll_enable(struct msm_dsi_pll *pll) +{ + int i, ret = 0; + + /* + * Certain PLLs do not allow VCO rate update when it is on. + * Keep track of their status to turn on/off after set rate success. + */ + if (unlikely(pll->pll_on)) + return 0; + + /* Try all enable sequences until one succeeds */ + for (i = 0; i < pll->en_seq_cnt; i++) { + ret = pll->enable_seqs[i](pll); + DBG("DSI PLL %s after sequence #%d", + ret ? "unlocked" : "locked", i + 1); + if (!ret) + break; + } + + if (ret) { + DRM_ERROR("DSI PLL failed to lock\n"); + return ret; + } + + pll->pll_on = true; + + return 0; +} + +static void dsi_pll_disable(struct msm_dsi_pll *pll) +{ + if (unlikely(!pll->pll_on)) + return; + + pll->disable_seq(pll); + + pll->pll_on = false; +} + +/* + * DSI PLL Helper functions + */ +long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + + if (rate < pll->min_rate) + return pll->min_rate; + else if (rate > pll->max_rate) + return pll->max_rate; + else + return rate; +} + +int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + int ret; + + /* + * Certain PLLs need to update the same VCO rate and registers + * after resume in suspend/resume scenario. + */ + if (pll->restore_state) { + ret = pll->restore_state(pll); + if (ret) + goto error; + } + + ret = dsi_pll_enable(pll); + +error: + return ret; +} + +void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + + if (pll->save_state) + pll->save_state(pll); + + dsi_pll_disable(pll); +} + +void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev, + struct clk **clks, u32 num_clks) +{ + of_clk_del_provider(pdev->dev.of_node); + + if (!num_clks || !clks) + return; + + do { + clk_unregister(clks[--num_clks]); + clks[num_clks] = NULL; + } while (num_clks); +} + +/* + * DSI PLL API + */ +int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, + struct clk **byte_clk_provider, struct clk **pixel_clk_provider) +{ + if (pll->get_provider) + return pll->get_provider(pll, + byte_clk_provider, + pixel_clk_provider); + + return -EINVAL; +} + +void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) +{ + if (pll->destroy) + pll->destroy(pll); +} + +struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev, + enum msm_dsi_phy_type type, int id) +{ + struct device *dev = &pdev->dev; + struct msm_dsi_pll *pll; + + switch (type) { + case MSM_DSI_PHY_28NM_HPM: + case MSM_DSI_PHY_28NM_LP: + pll = msm_dsi_pll_28nm_init(pdev, type, id); + break; + default: + pll = ERR_PTR(-ENXIO); + break; + } + + if (IS_ERR(pll)) { + dev_err(dev, "%s: failed to init DSI PLL\n", __func__); + return NULL; + } + + pll->type = type; + + DBG("DSI:%d PLL registered", id); + + return pll; +} + diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h new file mode 100644 index 000000000000..5a3bb241c039 --- /dev/null +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DSI_PLL_H__ +#define __DSI_PLL_H__ + +#include +#include + +#include "dsi.h" + +#define NUM_DSI_CLOCKS_MAX 6 +#define MAX_DSI_PLL_EN_SEQS 10 + +struct msm_dsi_pll { + enum msm_dsi_phy_type type; + + struct clk_hw clk_hw; + bool pll_on; + + unsigned long min_rate; + unsigned long max_rate; + u32 en_seq_cnt; + + int (*enable_seqs[MAX_DSI_PLL_EN_SEQS])(struct msm_dsi_pll *pll); + void (*disable_seq)(struct msm_dsi_pll *pll); + int (*get_provider)(struct msm_dsi_pll *pll, + struct clk **byte_clk_provider, + struct clk **pixel_clk_provider); + void (*destroy)(struct msm_dsi_pll *pll); + void (*save_state)(struct msm_dsi_pll *pll); + int (*restore_state)(struct msm_dsi_pll *pll); +}; + +#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw) + +static inline void pll_write(void __iomem *reg, u32 data) +{ + msm_writel(data, reg); +} + +static inline u32 pll_read(const void __iomem *reg) +{ + return msm_readl(reg); +} + +static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us) +{ + pll_write(reg, data); + udelay(delay_us); +} + +static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns) +{ + pll_write((reg), data); + ndelay(delay_ns); +} + +/* + * DSI PLL Helper functions + */ + +/* clock callbacks */ +long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate); +int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw); +void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw); +/* misc */ +void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev, + struct clk **clks, u32 num_clks); + +/* + * Initialization for Each PLL Type + */ +struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, + enum msm_dsi_phy_type type, int id); + +#endif /* __DSI_PLL_H__ */ + diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c new file mode 100644 index 000000000000..eb8ac3097ff5 --- /dev/null +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c @@ -0,0 +1,652 @@ +/* + * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "dsi_pll.h" +#include "dsi.xml.h" + +/* + * DSI PLL 28nm - clock diagram (eg: DSI0): + * + * dsi0analog_postdiv_clk + * | dsi0indirect_path_div2_clk + * | | + * +------+ | +----+ | |\ dsi0byte_mux + * dsi0vco_clk --o--| DIV1 |--o--| /2 |--o--| \ | + * | +------+ +----+ | m| | +----+ + * | | u|--o--| /4 |-- dsi0pllbyte + * | | x| +----+ + * o--------------------------| / + * | |/ + * | +------+ + * o----------| DIV3 |------------------------- dsi0pll + * +------+ + */ + +#define POLL_MAX_READS 10 +#define POLL_TIMEOUT_US 50 + +#define NUM_PROVIDED_CLKS 2 + +#define VCO_REF_CLK_RATE 19200000 +#define VCO_MIN_RATE 350000000 +#define VCO_MAX_RATE 750000000 + +#define DSI_BYTE_PLL_CLK 0 +#define DSI_PIXEL_PLL_CLK 1 + +#define LPFR_LUT_SIZE 10 +struct lpfr_cfg { + unsigned long vco_rate; + u32 resistance; +}; + +/* Loop filter resistance: */ +static const struct lpfr_cfg lpfr_lut[LPFR_LUT_SIZE] = { + { 479500000, 8 }, + { 480000000, 11 }, + { 575500000, 8 }, + { 576000000, 12 }, + { 610500000, 8 }, + { 659500000, 9 }, + { 671500000, 10 }, + { 672000000, 14 }, + { 708500000, 10 }, + { 750000000, 11 }, +}; + +struct pll_28nm_cached_state { + unsigned long vco_rate; + u8 postdiv3; + u8 postdiv1; + u8 byte_mux; +}; + +struct dsi_pll_28nm { + struct msm_dsi_pll base; + + int id; + struct platform_device *pdev; + void __iomem *mmio; + + int vco_delay; + + /* private clocks: */ + struct clk *clks[NUM_DSI_CLOCKS_MAX]; + u32 num_clks; + + /* clock-provider: */ + struct clk *provided_clks[NUM_PROVIDED_CLKS]; + struct clk_onecell_data clk_data; + + struct pll_28nm_cached_state cached_state; +}; + +#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base) + +static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, + u32 nb_tries, u32 timeout_us) +{ + bool pll_locked = false; + u32 val; + + while (nb_tries--) { + val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS); + pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY); + + if (pll_locked) + break; + + udelay(timeout_us); + } + DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); + + return pll_locked; +} + +static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm) +{ + void __iomem *base = pll_28nm->mmio; + + /* + * Add HW recommended delays after toggling the software + * reset bit off and back on. + */ + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, + DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, 1); + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); +} + +/* + * Clock Callbacks + */ +static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct device *dev = &pll_28nm->pdev->dev; + void __iomem *base = pll_28nm->mmio; + unsigned long div_fbx1000, gen_vco_clk; + u32 refclk_cfg, frac_n_mode, frac_n_value; + u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; + u32 cal_cfg10, cal_cfg11; + u32 rem; + int i; + + VERB("rate=%lu, parent's=%lu", rate, parent_rate); + + /* Force postdiv2 to be div-4 */ + pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); + + /* Configure the Loop filter resistance */ + for (i = 0; i < LPFR_LUT_SIZE; i++) + if (rate <= lpfr_lut[i].vco_rate) + break; + if (i == LPFR_LUT_SIZE) { + dev_err(dev, "unable to get loop filter resistance. vco=%lu\n", + rate); + return -EINVAL; + } + pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); + + /* Loop filter capacitance values : c1 and c2 */ + pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); + pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); + + rem = rate % VCO_REF_CLK_RATE; + if (rem) { + refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; + frac_n_mode = 1; + div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); + gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); + } else { + refclk_cfg = 0x0; + frac_n_mode = 0; + div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); + gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); + } + + DBG("refclk_cfg = %d", refclk_cfg); + + rem = div_fbx1000 % 1000; + frac_n_value = (rem << 16) / 1000; + + DBG("div_fb = %lu", div_fbx1000); + DBG("frac_n_value = %d", frac_n_value); + + DBG("Generated VCO Clock: %lu", gen_vco_clk); + rem = 0; + sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); + sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; + if (frac_n_mode) { + sdm_cfg0 = 0x0; + sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); + sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET( + (u32)(((div_fbx1000 / 1000) & 0x3f) - 1)); + sdm_cfg3 = frac_n_value >> 8; + sdm_cfg2 = frac_n_value & 0xff; + } else { + sdm_cfg0 = DSI_28nm_PHY_PLL_SDM_CFG0_BYP; + sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV( + (u32)(((div_fbx1000 / 1000) & 0x3f) - 1)); + sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(0); + sdm_cfg2 = 0; + sdm_cfg3 = 0; + } + + DBG("sdm_cfg0=%d", sdm_cfg0); + DBG("sdm_cfg1=%d", sdm_cfg1); + DBG("sdm_cfg2=%d", sdm_cfg2); + DBG("sdm_cfg3=%d", sdm_cfg3); + + cal_cfg11 = (u32)(gen_vco_clk / (256 * 1000000)); + cal_cfg10 = (u32)((gen_vco_clk % (256 * 1000000)) / 1000000); + DBG("cal_cfg10=%d, cal_cfg11=%d", cal_cfg10, cal_cfg11); + + pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); + pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + + pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); + pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, + DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2)); + pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3, + DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3)); + pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); + + /* Add hardware recommended delay for correct PLL configuration */ + if (pll_28nm->vco_delay) + udelay(pll_28nm->vco_delay); + + pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); + pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); + pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31); + pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff); + pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff); + pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20); + + return 0; +} + +static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + + return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, + POLL_TIMEOUT_US); +} + +static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct msm_dsi_pll *pll = hw_clk_to_pll(hw); + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + void __iomem *base = pll_28nm->mmio; + u32 sdm0, doubler, sdm_byp_div; + u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3; + u32 ref_clk = VCO_REF_CLK_RATE; + unsigned long vco_rate; + + VERB("parent_rate=%lu", parent_rate); + + /* Check to see if the ref clk doubler is enabled */ + doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & + DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; + ref_clk += (doubler * VCO_REF_CLK_RATE); + + /* see if it is integer mode or sdm mode */ + sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); + if (sdm0 & DSI_28nm_PHY_PLL_SDM_CFG0_BYP) { + /* integer mode */ + sdm_byp_div = FIELD( + pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), + DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV) + 1; + vco_rate = ref_clk * sdm_byp_div; + } else { + /* sdm mode */ + sdm_dc_off = FIELD( + pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), + DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET); + DBG("sdm_dc_off = %d", sdm_dc_off); + sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), + DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0); + sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), + DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8); + sdm_freq_seed = (sdm3 << 8) | sdm2; + DBG("sdm_freq_seed = %d", sdm_freq_seed); + + vco_rate = (ref_clk * (sdm_dc_off + 1)) + + mult_frac(ref_clk, sdm_freq_seed, BIT(16)); + DBG("vco rate = %lu", vco_rate); + } + + DBG("returning vco rate = %lu", vco_rate); + + return vco_rate; +} + +static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { + .round_rate = msm_dsi_pll_helper_clk_round_rate, + .set_rate = dsi_pll_28nm_clk_set_rate, + .recalc_rate = dsi_pll_28nm_clk_recalc_rate, + .prepare = msm_dsi_pll_helper_clk_prepare, + .unprepare = msm_dsi_pll_helper_clk_unprepare, + .is_enabled = dsi_pll_28nm_clk_is_enabled, +}; + +/* + * PLL Callbacks + */ +static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct device *dev = &pll_28nm->pdev->dev; + void __iomem *base = pll_28nm->mmio; + u32 max_reads = 5, timeout_us = 100; + bool locked; + u32 val; + int i; + + DBG("id=%d", pll_28nm->id); + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + + for (i = 0; i < 2; i++) { + /* DSI Uniphy lock detect setting */ + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, + 0x0c, 100); + pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + + /* poll for PLL ready status */ + locked = pll_28nm_poll_for_ready(pll_28nm, + max_reads, timeout_us); + if (locked) + break; + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); + + val &= ~DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + } + + if (unlikely(!locked)) + dev_err(dev, "DSI PLL lock failed\n"); + else + DBG("DSI PLL Lock success"); + + return locked ? 0 : -EINVAL; +} + +static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct device *dev = &pll_28nm->pdev->dev; + void __iomem *base = pll_28nm->mmio; + bool locked; + u32 max_reads = 10, timeout_us = 50; + u32 val; + + DBG("id=%d", pll_28nm->id); + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500); + + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B | + DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); + + /* DSI PLL toggle lock detect setting */ + pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500); + pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512); + + locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us); + + if (unlikely(!locked)) + dev_err(dev, "DSI PLL lock failed\n"); + else + DBG("DSI PLL lock success"); + + return locked ? 0 : -EINVAL; +} + +static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + + DBG("id=%d", pll_28nm->id); + pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); +} + +static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; + void __iomem *base = pll_28nm->mmio; + + cached_state->postdiv3 = + pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); + cached_state->postdiv1 = + pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); + cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); + cached_state->vco_rate = __clk_get_rate(pll->clk_hw.clk); +} + +static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; + void __iomem *base = pll_28nm->mmio; + int ret; + + if ((cached_state->vco_rate != 0) && + (cached_state->vco_rate == __clk_get_rate(pll->clk_hw.clk))) { + ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw, + cached_state->vco_rate, 0); + if (ret) { + dev_err(&pll_28nm->pdev->dev, + "restore vco rate failed. ret=%d\n", ret); + return ret; + } + + pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, + cached_state->postdiv3); + pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, + cached_state->postdiv1); + pll_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG, + cached_state->byte_mux); + + cached_state->vco_rate = 0; + } + + return 0; +} + +static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll, + struct clk **byte_clk_provider, + struct clk **pixel_clk_provider) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + + if (byte_clk_provider) + *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK]; + if (pixel_clk_provider) + *pixel_clk_provider = + pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK]; + + return 0; +} + +static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); + int i; + + msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev, + pll_28nm->clks, pll_28nm->num_clks); + + for (i = 0; i < NUM_PROVIDED_CLKS; i++) + pll_28nm->provided_clks[i] = NULL; + + pll_28nm->num_clks = 0; + pll_28nm->clk_data.clks = NULL; + pll_28nm->clk_data.clk_num = 0; +} + +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) +{ + char clk_name[32], parent1[32], parent2[32], vco_name[32]; + struct clk_init_data vco_init = { + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .name = vco_name, + .ops = &clk_ops_dsi_pll_28nm_vco, + }; + struct device *dev = &pll_28nm->pdev->dev; + struct clk **clks = pll_28nm->clks; + struct clk **provided_clks = pll_28nm->provided_clks; + int num = 0; + int ret; + + DBG("%d", pll_28nm->id); + + snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id); + pll_28nm->base.clk_hw.init = &vco_init; + clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw); + + snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); + clks[num++] = clk_register_divider(dev, clk_name, + parent1, CLK_SET_RATE_PARENT, + pll_28nm->mmio + + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, + 0, 4, 0, NULL); + + snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); + snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id); + clks[num++] = clk_register_fixed_factor(dev, clk_name, + parent1, CLK_SET_RATE_PARENT, + 1, 2); + + snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id); + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); + clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] = + clk_register_divider(dev, clk_name, + parent1, 0, pll_28nm->mmio + + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, + 0, 8, 0, NULL); + + snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id); + snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); + snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); + clks[num++] = clk_register_mux(dev, clk_name, + (const char *[]){ + parent1, parent2 + }, 2, CLK_SET_RATE_PARENT, pll_28nm->mmio + + REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL); + + snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); + snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id); + clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] = + clk_register_fixed_factor(dev, clk_name, + parent1, CLK_SET_RATE_PARENT, 1, 4); + + pll_28nm->num_clks = num; + + pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS; + pll_28nm->clk_data.clks = provided_clks; + + ret = of_clk_add_provider(dev->of_node, + of_clk_src_onecell_get, &pll_28nm->clk_data); + if (ret) { + dev_err(dev, "failed to register clk provider: %d\n", ret); + return ret; + } + + return 0; +} + +struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, + enum msm_dsi_phy_type type, int id) +{ + struct dsi_pll_28nm *pll_28nm; + struct msm_dsi_pll *pll; + int ret; + + if (!pdev) + return ERR_PTR(-ENODEV); + + pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL); + if (!pll_28nm) + return ERR_PTR(-ENOMEM); + + pll_28nm->pdev = pdev; + pll_28nm->id = id; + + pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); + if (IS_ERR_OR_NULL(pll_28nm->mmio)) { + dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__); + return ERR_PTR(-ENOMEM); + } + + pll = &pll_28nm->base; + pll->min_rate = VCO_MIN_RATE; + pll->max_rate = VCO_MAX_RATE; + pll->get_provider = dsi_pll_28nm_get_provider; + pll->destroy = dsi_pll_28nm_destroy; + pll->disable_seq = dsi_pll_28nm_disable_seq; + pll->save_state = dsi_pll_28nm_save_state; + pll->restore_state = dsi_pll_28nm_restore_state; + + if (type == MSM_DSI_PHY_28NM_HPM) { + pll_28nm->vco_delay = 1; + + pll->en_seq_cnt = 3; + pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_hpm; + pll->enable_seqs[1] = dsi_pll_28nm_enable_seq_hpm; + pll->enable_seqs[2] = dsi_pll_28nm_enable_seq_hpm; + } else if (type == MSM_DSI_PHY_28NM_LP) { + pll_28nm->vco_delay = 1000; + + pll->en_seq_cnt = 1; + pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_lp; + } else { + dev_err(&pdev->dev, "phy type (%d) is not 28nm\n", type); + return ERR_PTR(-EINVAL); + } + + ret = pll_28nm_register(pll_28nm); + if (ret) { + dev_err(&pdev->dev, "failed to register PLL: %d\n", ret); + return ERR_PTR(ret); + } + + return pll; +} + -- cgit v1.2.3 From 9d32c4989c858af12b333ae9a3c160a91ff43934 Mon Sep 17 00:00:00 2001 From: Hai Li Date: Fri, 15 May 2015 13:04:05 -0400 Subject: drm/msm/dsi: Enable PLL driver in MSM DSI This change activates PLL driver for DSI to work with common clock framework. Signed-off-by: Hai Li Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/dsi/dsi.c | 14 +++++++ drivers/gpu/drm/msm/dsi/dsi.h | 43 ++++++++++++++++--- drivers/gpu/drm/msm/dsi/dsi_host.c | 60 ++++++++++++++++++++++---- drivers/gpu/drm/msm/dsi/dsi_manager.c | 79 +++++++++++++++++++++++++---------- drivers/gpu/drm/msm/dsi/dsi_phy.c | 68 ++++++++++++++++++++++++++++++ 5 files changed, 229 insertions(+), 35 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index ad50b80225f5..beb26dfca276 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -29,6 +29,12 @@ static void dsi_destroy(struct msm_dsi *msm_dsi) return; msm_dsi_manager_unregister(msm_dsi); + + if (msm_dsi->phy) { + msm_dsi_phy_destroy(msm_dsi->phy); + msm_dsi->phy = NULL; + } + if (msm_dsi->host) { msm_dsi_host_destroy(msm_dsi->host); msm_dsi->host = NULL; @@ -63,6 +69,14 @@ static struct msm_dsi *dsi_init(struct platform_device *pdev) if (ret) goto fail; + /* Init dsi PHY */ + msm_dsi->phy = msm_dsi_phy_init(pdev, msm_dsi->phy_type, msm_dsi->id); + if (!msm_dsi->phy) { + ret = -ENXIO; + pr_err("%s: phy init failed\n", __func__); + goto fail; + } + /* Register to dsi manager */ ret = msm_dsi_manager_register(msm_dsi); if (ret) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 321964a6b27e..8022814f7914 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -38,6 +38,13 @@ #define DSI_ENCODER_MASTER DSI_1 #define DSI_ENCODER_SLAVE DSI_0 +enum msm_dsi_phy_type { + MSM_DSI_PHY_UNKNOWN, + MSM_DSI_PHY_28NM_HPM, + MSM_DSI_PHY_28NM_LP, + MSM_DSI_PHY_MAX +}; + struct msm_dsi { struct drm_device *dev; struct platform_device *pdev; @@ -49,6 +56,8 @@ struct msm_dsi { struct msm_dsi_phy *phy; struct drm_panel *panel; unsigned long panel_flags; + + enum msm_dsi_phy_type phy_type; bool phy_enabled; /* the encoders we are hooked to (outside of dsi block) */ @@ -73,6 +82,29 @@ void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi); /* msm dsi */ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi); +/* dsi pll */ +struct msm_dsi_pll; +#ifdef CONFIG_DRM_MSM_DSI_PLL +struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev, + enum msm_dsi_phy_type type, int dsi_id); +void msm_dsi_pll_destroy(struct msm_dsi_pll *pll); +int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, + struct clk **byte_clk_provider, struct clk **pixel_clk_provider); +#else +static inline struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev, + enum msm_dsi_phy_type type, int id) { + return ERR_PTR(-ENODEV); +} +static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) +{ +} +static inline int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, + struct clk **byte_clk_provider, struct clk **pixel_clk_provider) +{ + return -ENODEV; +} +#endif + /* dsi host */ int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg); @@ -94,6 +126,8 @@ struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host, unsigned long *panel_flags); int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer); void msm_dsi_host_unregister(struct mipi_dsi_host *host); +int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, + struct msm_dsi_pll *src_pll); void msm_dsi_host_destroy(struct mipi_dsi_host *host); int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, struct drm_device *dev); @@ -101,18 +135,15 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi); /* dsi phy */ struct msm_dsi_phy; -enum msm_dsi_phy_type { - MSM_DSI_PHY_UNKNOWN, - MSM_DSI_PHY_28NM_HPM, - MSM_DSI_PHY_28NM_LP, - MSM_DSI_PHY_MAX -}; struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev, enum msm_dsi_phy_type type, int id); +void msm_dsi_phy_destroy(struct msm_dsi_phy *phy); int msm_dsi_phy_enable(struct msm_dsi_phy *phy, bool is_dual_panel, const unsigned long bit_rate, const unsigned long esc_rate); int msm_dsi_phy_disable(struct msm_dsi_phy *phy); void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy, u32 *clk_pre, u32 *clk_post); +struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy); + #endif /* __DSI_CONNECTOR_H__ */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 8a246cfa5d19..43ea8a30c121 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -205,6 +205,9 @@ struct msm_dsi_host { struct clk *byte_clk; struct clk *esc_clk; struct clk *pixel_clk; + struct clk *byte_clk_src; + struct clk *pixel_clk_src; + u32 byte_clk_rate; struct gpio_desc *disp_en_gpio; @@ -463,6 +466,22 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host) goto exit; } + msm_host->byte_clk_src = devm_clk_get(dev, "byte_clk_src"); + if (IS_ERR(msm_host->byte_clk_src)) { + ret = PTR_ERR(msm_host->byte_clk_src); + pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret); + msm_host->byte_clk_src = NULL; + goto exit; + } + + msm_host->pixel_clk_src = devm_clk_get(dev, "pixel_clk_src"); + if (IS_ERR(msm_host->pixel_clk_src)) { + ret = PTR_ERR(msm_host->pixel_clk_src); + pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret); + msm_host->pixel_clk_src = NULL; + goto exit; + } + exit: return ret; } @@ -1513,15 +1532,9 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); INIT_WORK(&msm_host->err_work, dsi_err_worker); - msm_dsi->phy = msm_dsi_phy_init(pdev, msm_host->cfg->phy_type, - msm_host->id); - if (!msm_dsi->phy) { - ret = -EINVAL; - pr_err("%s: phy init failed\n", __func__); - goto fail; - } msm_dsi->host = &msm_host->base; msm_dsi->id = msm_host->id; + msm_dsi->phy_type = msm_host->cfg->phy_type; DBG("Dsi Host %d initialized", msm_host->id); return 0; @@ -1829,6 +1842,39 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 iova, u32 len) wmb(); } +int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, + struct msm_dsi_pll *src_pll) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + struct clk *byte_clk_provider, *pixel_clk_provider; + int ret; + + ret = msm_dsi_pll_get_clk_provider(src_pll, + &byte_clk_provider, &pixel_clk_provider); + if (ret) { + pr_info("%s: can't get provider from pll, don't set parent\n", + __func__); + return 0; + } + + ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); + if (ret) { + pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", + __func__, ret); + goto exit; + } + + ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); + if (ret) { + pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", + __func__, ret); + goto exit; + } + +exit: + return ret; +} + int msm_dsi_host_enable(struct mipi_dsi_host *host) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 0a40f3c64e8b..87ac6612b6f8 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -60,6 +60,53 @@ static int dsi_mgr_parse_dual_panel(struct device_node *np, int id) return 0; } +static int dsi_mgr_host_register(int id) +{ + struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); + struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id); + struct msm_dsi *clk_master_dsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER); + struct msm_dsi_pll *src_pll; + int ret; + + if (!IS_DUAL_PANEL()) { + ret = msm_dsi_host_register(msm_dsi->host, true); + if (ret) + return ret; + + src_pll = msm_dsi_phy_get_pll(msm_dsi->phy); + ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll); + } else if (!other_dsi) { + ret = 0; + } else { + struct msm_dsi *mdsi = IS_MASTER_PANEL(id) ? + msm_dsi : other_dsi; + struct msm_dsi *sdsi = IS_MASTER_PANEL(id) ? + other_dsi : msm_dsi; + /* Register slave host first, so that slave DSI device + * has a chance to probe, and do not block the master + * DSI device's probe. + * Also, do not check defer for the slave host, + * because only master DSI device adds the panel to global + * panel list. The panel's device is the master DSI device. + */ + ret = msm_dsi_host_register(sdsi->host, false); + if (ret) + return ret; + ret = msm_dsi_host_register(mdsi->host, true); + if (ret) + return ret; + + /* PLL0 is to drive both 2 DSI link clocks in Dual DSI mode. */ + src_pll = msm_dsi_phy_get_pll(clk_master_dsi->phy); + ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll); + if (ret) + return ret; + ret = msm_dsi_host_set_src_pll(other_dsi->host, src_pll); + } + + return ret; +} + struct dsi_connector { struct drm_connector base; int id; @@ -652,7 +699,6 @@ int msm_dsi_manager_register(struct msm_dsi *msm_dsi) { struct msm_dsi_manager *msm_dsim = &msm_dsim_glb; int id = msm_dsi->id; - struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id); int ret; if (id > DSI_MAX) { @@ -670,31 +716,20 @@ int msm_dsi_manager_register(struct msm_dsi *msm_dsi) ret = dsi_mgr_parse_dual_panel(msm_dsi->pdev->dev.of_node, id); if (ret) { pr_err("%s: failed to parse dual panel info\n", __func__); - return ret; + goto fail; } - if (!IS_DUAL_PANEL()) { - ret = msm_dsi_host_register(msm_dsi->host, true); - } else if (!other_dsi) { - return 0; - } else { - struct msm_dsi *mdsi = IS_MASTER_PANEL(id) ? - msm_dsi : other_dsi; - struct msm_dsi *sdsi = IS_MASTER_PANEL(id) ? - other_dsi : msm_dsi; - /* Register slave host first, so that slave DSI device - * has a chance to probe, and do not block the master - * DSI device's probe. - * Also, do not check defer for the slave host, - * because only master DSI device adds the panel to global - * panel list. The panel's device is the master DSI device. - */ - ret = msm_dsi_host_register(sdsi->host, false); - if (ret) - return ret; - ret = msm_dsi_host_register(mdsi->host, true); + ret = dsi_mgr_host_register(id); + if (ret) { + pr_err("%s: failed to register mipi dsi host for DSI %d\n", + __func__, id); + goto fail; } + return 0; + +fail: + msm_dsim->dsi[id] = NULL; return ret; } diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy.c b/drivers/gpu/drm/msm/dsi/dsi_phy.c index 4403f38bf220..2b1c8fdb10de 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/dsi_phy.c @@ -34,10 +34,18 @@ struct dsi_dphy_timing { }; struct msm_dsi_phy { + struct platform_device *pdev; void __iomem *base; void __iomem *reg_base; int id; + + struct clk *ahb_clk; + struct dsi_dphy_timing timing; + enum msm_dsi_phy_type type; + + struct msm_dsi_pll *pll; + int (*enable)(struct msm_dsi_phy *phy, bool is_dual_panel, const unsigned long bit_rate, const unsigned long esc_rate); int (*disable)(struct msm_dsi_phy *phy); @@ -284,6 +292,27 @@ static int dsi_28nm_phy_disable(struct msm_dsi_phy *phy) return 0; } +static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) +{ + int ret; + + pm_runtime_get_sync(&phy->pdev->dev); + + ret = clk_prepare_enable(phy->ahb_clk); + if (ret) { + pr_err("%s: can't enable ahb clk, %d\n", __func__, ret); + pm_runtime_put_sync(&phy->pdev->dev); + } + + return ret; +} + +static void dsi_phy_disable_resource(struct msm_dsi_phy *phy) +{ + clk_disable_unprepare(phy->ahb_clk); + pm_runtime_put_sync(&phy->pdev->dev); +} + #define dsi_phy_func_init(name) \ do { \ phy->enable = dsi_##name##_phy_enable; \ @@ -294,6 +323,7 @@ struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev, enum msm_dsi_phy_type type, int id) { struct msm_dsi_phy *phy; + int ret; phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); if (!phy) @@ -320,11 +350,41 @@ struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev, return NULL; } + phy->type = type; phy->id = id; + phy->pdev = pdev; + + phy->ahb_clk = devm_clk_get(&pdev->dev, "iface_clk"); + if (IS_ERR(phy->ahb_clk)) { + pr_err("%s: Unable to get ahb clk\n", __func__); + return NULL; + } + + /* PLL init will call into clk_register which requires + * register access, so we need to enable power and ahb clock. + */ + ret = dsi_phy_enable_resource(phy); + if (ret) + return NULL; + + phy->pll = msm_dsi_pll_init(pdev, type, id); + if (!phy->pll) + pr_info("%s: pll init failed, need separate pll clk driver\n", + __func__); + + dsi_phy_disable_resource(phy); return phy; } +void msm_dsi_phy_destroy(struct msm_dsi_phy *phy) +{ + if (phy->pll) { + msm_dsi_pll_destroy(phy->pll); + phy->pll = NULL; + } +} + int msm_dsi_phy_enable(struct msm_dsi_phy *phy, bool is_dual_panel, const unsigned long bit_rate, const unsigned long esc_rate) { @@ -351,3 +411,11 @@ void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy, *clk_post = phy->timing.clk_post; } +struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy) +{ + if (!phy) + return NULL; + + return phy->pll; +} + -- cgit v1.2.3 From ec31abf6684ebe1134eb3320c96fb92e566eff74 Mon Sep 17 00:00:00 2001 From: Hai Li Date: Fri, 15 May 2015 13:04:06 -0400 Subject: drm/msm/dsi: Separate PHY to another platform device There are different types of PHY from one chipset to another, while the DSI host controller is relatively consistent across platforms. Also, the PLL inside PHY is providing the source of DSI byte and pixel clocks, which are used by DSI host controller. Separated devices for clock provider and clock consumer make DSI driver better fit into common clock framework. Signed-off-by: Hai Li Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/drm/msm/dsi.txt | 59 +++-- drivers/gpu/drm/msm/dsi/dsi.c | 45 +++- drivers/gpu/drm/msm/dsi/dsi.h | 25 +- drivers/gpu/drm/msm/dsi/dsi_host.c | 25 +- drivers/gpu/drm/msm/dsi/dsi_phy.c | 266 ++++++++++++++++++---- 5 files changed, 326 insertions(+), 94 deletions(-) (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/drm/msm/dsi.txt b/Documentation/devicetree/bindings/drm/msm/dsi.txt index ff8aebb2f8f8..cd8fe6cf536c 100644 --- a/Documentation/devicetree/bindings/drm/msm/dsi.txt +++ b/Documentation/devicetree/bindings/drm/msm/dsi.txt @@ -1,15 +1,12 @@ Qualcomm Technologies Inc. adreno/snapdragon DSI output +DSI Controller: Required properties: - compatible: * "qcom,mdss-dsi-ctrl" -- reg: Physical base address and length of the registers of controller, PLL, - PHY and PHY regulator +- reg: Physical base address and length of the registers of controller - reg-names: The names of register regions. The following regions are required: * "dsi_ctrl" - * "dsi_pll" - * "dsi_phy" - * "dsi_phy_regulator" - qcom,dsi-host-index: The ID of DSI controller hardware instance. This should be 0 or 1, since we have 2 DSI controllers at most for now. - interrupts: The interrupt signal from the DSI block. @@ -24,10 +21,10 @@ Required properties: * "iface_clk" * "mdp_core_clk" * "pixel_clk" -- #clock-cells: The value should be 1. - vdd-supply: phandle to vdd regulator device node - vddio-supply: phandle to vdd-io regulator device node - vdda-supply: phandle to vdda regulator device node +- qcom,dsi-phy: phandle to DSI PHY device node Optional properties: - panel@0: Node of panel connected to this DSI controller. @@ -42,22 +39,34 @@ Optional properties: - interrupt-parent: phandle to the MDP block if the interrupt signal is routed through MDP block +DSI PHY: +Required properties: +- compatible: Could be the following + * "qcom,dsi-phy-28nm-hpm" + * "qcom,dsi-phy-28nm-lp" +- reg: Physical base address and length of the registers of PLL, PHY and PHY + regulator +- reg-names: The names of register regions. The following regions are required: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_regulator" +- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should + be 0 or 1, since we have 2 DSI PHYs at most for now. +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: device clocks + See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required: + * "iface_clk" +- vddio-supply: phandle to vdd-io regulator device node + Example: mdss_dsi0: qcom,mdss_dsi@fd922800 { compatible = "qcom,mdss-dsi-ctrl"; qcom,dsi-host-index = <0>; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; - reg-names = - "dsi_ctrl", - "dsi_pll", - "dsi_phy", - "dsi_phy_regulator", - reg = <0xfd922800 0x200>, - <0xfd922a00 0xd4>, - <0xfd922b00 0x2b0>, - <0xfd922d80 0x7b>, - <0xfd828000 0x108>; + reg-names = "dsi_ctrl"; + reg = <0xfd922800 0x200>; power-domains = <&mmcc MDSS_GDSC>; clock-names = "bus_clk", @@ -75,11 +84,12 @@ Example: <&mmcc MDSS_AHB_CLK>, <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_PCLK0_CLK>; - #clock-cells = <1>; vdda-supply = <&pma8084_l2>; vdd-supply = <&pma8084_l22>; vddio-supply = <&pma8084_l12>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + qcom,dual-panel-mode; qcom,master-panel; qcom,sync-dual-panel; @@ -93,3 +103,18 @@ Example: backlight = <...>; }; }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-hpm"; + qcom,dsi-phy-index = <0>; + reg-names = + "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x2b0>, + <0xfd922d80 0x7b>; + clock-names = "iface_clk"; + clocks = <&mmcc MDSS_AHB_CLK>; + vddio-supply = <&pma8084_l12>; + }; diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index beb26dfca276..1f2561e2ff71 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -23,6 +23,34 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi) msm_dsi->encoders[MSM_DSI_CMD_ENCODER_ID]; } +static int dsi_get_phy(struct msm_dsi *msm_dsi) +{ + struct platform_device *pdev = msm_dsi->pdev; + struct platform_device *phy_pdev; + struct device_node *phy_node; + + phy_node = of_parse_phandle(pdev->dev.of_node, "qcom,dsi-phy", 0); + if (!phy_node) { + dev_err(&pdev->dev, "cannot find phy device\n"); + return -ENXIO; + } + + phy_pdev = of_find_device_by_node(phy_node); + if (phy_pdev) + msm_dsi->phy = platform_get_drvdata(phy_pdev); + + of_node_put(phy_node); + + if (!phy_pdev || !msm_dsi->phy) { + dev_err(&pdev->dev, "%s: phy driver is not ready\n", __func__); + return -EPROBE_DEFER; + } + + msm_dsi->phy_dev = get_device(&phy_pdev->dev); + + return 0; +} + static void dsi_destroy(struct msm_dsi *msm_dsi) { if (!msm_dsi) @@ -30,9 +58,10 @@ static void dsi_destroy(struct msm_dsi *msm_dsi) msm_dsi_manager_unregister(msm_dsi); - if (msm_dsi->phy) { - msm_dsi_phy_destroy(msm_dsi->phy); + if (msm_dsi->phy_dev) { + put_device(msm_dsi->phy_dev); msm_dsi->phy = NULL; + msm_dsi->phy_dev = NULL; } if (msm_dsi->host) { @@ -49,7 +78,6 @@ static struct msm_dsi *dsi_init(struct platform_device *pdev) int ret; if (!pdev) { - dev_err(&pdev->dev, "no dsi device\n"); ret = -ENXIO; goto fail; } @@ -69,13 +97,10 @@ static struct msm_dsi *dsi_init(struct platform_device *pdev) if (ret) goto fail; - /* Init dsi PHY */ - msm_dsi->phy = msm_dsi_phy_init(pdev, msm_dsi->phy_type, msm_dsi->id); - if (!msm_dsi->phy) { - ret = -ENXIO; - pr_err("%s: phy init failed\n", __func__); + /* GET dsi PHY */ + ret = dsi_get_phy(msm_dsi); + if (ret) goto fail; - } /* Register to dsi manager */ ret = msm_dsi_manager_register(msm_dsi); @@ -156,12 +181,14 @@ static struct platform_driver dsi_driver = { void __init msm_dsi_register(void) { DBG(""); + msm_dsi_phy_driver_register(); platform_driver_register(&dsi_driver); } void __exit msm_dsi_unregister(void) { DBG(""); + msm_dsi_phy_driver_unregister(); platform_driver_unregister(&dsi_driver); } diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 8022814f7914..92d697de4858 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -14,6 +14,7 @@ #ifndef __DSI_CONNECTOR_H__ #define __DSI_CONNECTOR_H__ +#include #include #include "drm_crtc.h" @@ -39,12 +40,27 @@ #define DSI_ENCODER_SLAVE DSI_0 enum msm_dsi_phy_type { - MSM_DSI_PHY_UNKNOWN, MSM_DSI_PHY_28NM_HPM, MSM_DSI_PHY_28NM_LP, MSM_DSI_PHY_MAX }; +#define DSI_DEV_REGULATOR_MAX 8 + +/* Regulators for DSI devices */ +struct dsi_reg_entry { + char name[32]; + int min_voltage; + int max_voltage; + int enable_load; + int disable_load; +}; + +struct dsi_reg_config { + int num; + struct dsi_reg_entry regs[DSI_DEV_REGULATOR_MAX]; +}; + struct msm_dsi { struct drm_device *dev; struct platform_device *pdev; @@ -57,7 +73,7 @@ struct msm_dsi { struct drm_panel *panel; unsigned long panel_flags; - enum msm_dsi_phy_type phy_type; + struct device *phy_dev; bool phy_enabled; /* the encoders we are hooked to (outside of dsi block) */ @@ -135,9 +151,8 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi); /* dsi phy */ struct msm_dsi_phy; -struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int id); -void msm_dsi_phy_destroy(struct msm_dsi_phy *phy); +void msm_dsi_phy_driver_register(void); +void msm_dsi_phy_driver_unregister(void); int msm_dsi_phy_enable(struct msm_dsi_phy *phy, bool is_dual_panel, const unsigned long bit_rate, const unsigned long esc_rate); int msm_dsi_phy_disable(struct msm_dsi_phy *phy); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 43ea8a30c121..bc2e405758e3 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -36,35 +36,19 @@ #define DSI_6G_REG_SHIFT 4 -#define DSI_REGULATOR_MAX 8 -struct dsi_reg_entry { - char name[32]; - int min_voltage; - int max_voltage; - int enable_load; - int disable_load; -}; - -struct dsi_reg_config { - int num; - struct dsi_reg_entry regs[DSI_REGULATOR_MAX]; -}; - struct dsi_config { u32 major; u32 minor; u32 io_offset; - enum msm_dsi_phy_type phy_type; struct dsi_reg_config reg_cfg; }; static const struct dsi_config dsi_cfgs[] = { - {MSM_DSI_VER_MAJOR_V2, 0, 0, MSM_DSI_PHY_UNKNOWN}, + {MSM_DSI_VER_MAJOR_V2, 0, 0, {0,} }, { /* 8974 v1 */ .major = MSM_DSI_VER_MAJOR_6G, .minor = MSM_DSI_6G_VER_MINOR_V1_0, .io_offset = DSI_6G_REG_SHIFT, - .phy_type = MSM_DSI_PHY_28NM_HPM, .reg_cfg = { .num = 4, .regs = { @@ -79,7 +63,6 @@ static const struct dsi_config dsi_cfgs[] = { .major = MSM_DSI_VER_MAJOR_6G, .minor = MSM_DSI_6G_VER_MINOR_V1_1, .io_offset = DSI_6G_REG_SHIFT, - .phy_type = MSM_DSI_PHY_28NM_HPM, .reg_cfg = { .num = 4, .regs = { @@ -94,7 +77,6 @@ static const struct dsi_config dsi_cfgs[] = { .major = MSM_DSI_VER_MAJOR_6G, .minor = MSM_DSI_6G_VER_MINOR_V1_1_1, .io_offset = DSI_6G_REG_SHIFT, - .phy_type = MSM_DSI_PHY_28NM_HPM, .reg_cfg = { .num = 4, .regs = { @@ -109,7 +91,6 @@ static const struct dsi_config dsi_cfgs[] = { .major = MSM_DSI_VER_MAJOR_6G, .minor = MSM_DSI_6G_VER_MINOR_V1_2, .io_offset = DSI_6G_REG_SHIFT, - .phy_type = MSM_DSI_PHY_28NM_HPM, .reg_cfg = { .num = 4, .regs = { @@ -124,7 +105,6 @@ static const struct dsi_config dsi_cfgs[] = { .major = MSM_DSI_VER_MAJOR_6G, .minor = MSM_DSI_6G_VER_MINOR_V1_3_1, .io_offset = DSI_6G_REG_SHIFT, - .phy_type = MSM_DSI_PHY_28NM_LP, .reg_cfg = { .num = 4, .regs = { @@ -197,7 +177,7 @@ struct msm_dsi_host { int id; void __iomem *ctrl_base; - struct regulator_bulk_data supplies[DSI_REGULATOR_MAX]; + struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; struct clk *mdp_core_clk; struct clk *ahb_clk; struct clk *axi_clk; @@ -1534,7 +1514,6 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) msm_dsi->host = &msm_host->base; msm_dsi->id = msm_host->id; - msm_dsi->phy_type = msm_host->cfg->phy_type; DBG("Dsi Host %d initialized", msm_host->id); return 0; diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy.c b/drivers/gpu/drm/msm/dsi/dsi_phy.c index 2b1c8fdb10de..2d3b33ce1cc5 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/dsi_phy.c @@ -11,12 +11,27 @@ * GNU General Public License for more details. */ +#include +#include + #include "dsi.h" #include "dsi.xml.h" #define dsi_phy_read(offset) msm_readl((offset)) #define dsi_phy_write(offset, data) msm_writel((data), (offset)) +struct dsi_phy_ops { + int (*enable)(struct msm_dsi_phy *phy, bool is_dual_panel, + const unsigned long bit_rate, const unsigned long esc_rate); + int (*disable)(struct msm_dsi_phy *phy); +}; + +struct dsi_phy_cfg { + enum msm_dsi_phy_type type; + struct dsi_reg_config reg_cfg; + struct dsi_phy_ops ops; +}; + struct dsi_dphy_timing { u32 clk_pre; u32 clk_post; @@ -40,17 +55,100 @@ struct msm_dsi_phy { int id; struct clk *ahb_clk; + struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; struct dsi_dphy_timing timing; - enum msm_dsi_phy_type type; + const struct dsi_phy_cfg *cfg; struct msm_dsi_pll *pll; - - int (*enable)(struct msm_dsi_phy *phy, bool is_dual_panel, - const unsigned long bit_rate, const unsigned long esc_rate); - int (*disable)(struct msm_dsi_phy *phy); }; +static int dsi_phy_regulator_init(struct msm_dsi_phy *phy) +{ + struct regulator_bulk_data *s = phy->supplies; + const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; + struct device *dev = &phy->pdev->dev; + int num = phy->cfg->reg_cfg.num; + int i, ret; + + for (i = 0; i < num; i++) + s[i].supply = regs[i].name; + + ret = devm_regulator_bulk_get(&phy->pdev->dev, num, s); + if (ret < 0) { + dev_err(dev, "%s: failed to init regulator, ret=%d\n", + __func__, ret); + return ret; + } + + for (i = 0; i < num; i++) { + if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) { + ret = regulator_set_voltage(s[i].consumer, + regs[i].min_voltage, regs[i].max_voltage); + if (ret < 0) { + dev_err(dev, + "regulator %d set voltage failed, %d\n", + i, ret); + return ret; + } + } + } + + return 0; +} + +static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy) +{ + struct regulator_bulk_data *s = phy->supplies; + const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; + int num = phy->cfg->reg_cfg.num; + int i; + + DBG(""); + for (i = num - 1; i >= 0; i--) + if (regs[i].disable_load >= 0) + regulator_set_load(s[i].consumer, + regs[i].disable_load); + + regulator_bulk_disable(num, s); +} + +static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy) +{ + struct regulator_bulk_data *s = phy->supplies; + const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; + struct device *dev = &phy->pdev->dev; + int num = phy->cfg->reg_cfg.num; + int ret, i; + + DBG(""); + for (i = 0; i < num; i++) { + if (regs[i].enable_load >= 0) { + ret = regulator_set_load(s[i].consumer, + regs[i].enable_load); + if (ret < 0) { + dev_err(dev, + "regulator %d set op mode failed, %d\n", + i, ret); + goto fail; + } + } + } + + ret = regulator_bulk_enable(num, s); + if (ret < 0) { + dev_err(dev, "regulator enable failed, %d\n", ret); + goto fail; + } + + return 0; + +fail: + for (i--; i >= 0; i--) + regulator_set_load(s[i].consumer, regs[i].disable_load); + return ret; +} + #define S_DIV_ROUND_UP(n, d) \ (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d))) @@ -313,51 +411,94 @@ static void dsi_phy_disable_resource(struct msm_dsi_phy *phy) pm_runtime_put_sync(&phy->pdev->dev); } -#define dsi_phy_func_init(name) \ - do { \ - phy->enable = dsi_##name##_phy_enable; \ - phy->disable = dsi_##name##_phy_disable; \ - } while (0) +static const struct dsi_phy_cfg dsi_phy_cfgs[MSM_DSI_PHY_MAX] = { + [MSM_DSI_PHY_28NM_HPM] = { + .type = MSM_DSI_PHY_28NM_HPM, + .reg_cfg = { + .num = 1, + .regs = { + {"vddio", 1800000, 1800000, 100000, 100}, + }, + }, + .ops = { + .enable = dsi_28nm_phy_enable, + .disable = dsi_28nm_phy_disable, + } + }, + [MSM_DSI_PHY_28NM_LP] = { + .type = MSM_DSI_PHY_28NM_LP, + .reg_cfg = { + .num = 1, + .regs = { + {"vddio", 1800000, 1800000, 100000, 100}, + }, + }, + .ops = { + .enable = dsi_28nm_phy_enable, + .disable = dsi_28nm_phy_disable, + } + }, +}; + +static const struct of_device_id dsi_phy_dt_match[] = { + { .compatible = "qcom,dsi-phy-28nm-hpm", + .data = &dsi_phy_cfgs[MSM_DSI_PHY_28NM_HPM],}, + { .compatible = "qcom,dsi-phy-28nm-lp", + .data = &dsi_phy_cfgs[MSM_DSI_PHY_28NM_LP],}, + {} +}; -struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev, - enum msm_dsi_phy_type type, int id) +static int dsi_phy_driver_probe(struct platform_device *pdev) { struct msm_dsi_phy *phy; + const struct of_device_id *match; int ret; phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); if (!phy) - return NULL; + return -ENOMEM; + + match = of_match_node(dsi_phy_dt_match, pdev->dev.of_node); + if (!match) + return -ENODEV; + + phy->cfg = match->data; + phy->pdev = pdev; + + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,dsi-phy-index", &phy->id); + if (ret) { + dev_err(&pdev->dev, + "%s: PHY index not specified, ret=%d\n", + __func__, ret); + goto fail; + } phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); if (IS_ERR(phy->base)) { - pr_err("%s: failed to map phy base\n", __func__); - return NULL; + dev_err(&pdev->dev, "%s: failed to map phy base\n", __func__); + ret = -ENOMEM; + goto fail; } phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG"); if (IS_ERR(phy->reg_base)) { - pr_err("%s: failed to map phy regulator base\n", __func__); - return NULL; + dev_err(&pdev->dev, + "%s: failed to map phy regulator base\n", __func__); + ret = -ENOMEM; + goto fail; } - switch (type) { - case MSM_DSI_PHY_28NM_HPM: - case MSM_DSI_PHY_28NM_LP: - dsi_phy_func_init(28nm); - break; - default: - pr_err("%s: unsupported type, %d\n", __func__, type); - return NULL; + ret = dsi_phy_regulator_init(phy); + if (ret) { + dev_err(&pdev->dev, "%s: failed to init regulator\n", __func__); + goto fail; } - phy->type = type; - phy->id = id; - phy->pdev = pdev; - phy->ahb_clk = devm_clk_get(&pdev->dev, "iface_clk"); if (IS_ERR(phy->ahb_clk)) { pr_err("%s: Unable to get ahb clk\n", __func__); - return NULL; + ret = PTR_ERR(phy->ahb_clk); + goto fail; } /* PLL init will call into clk_register which requires @@ -365,39 +506,84 @@ struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev, */ ret = dsi_phy_enable_resource(phy); if (ret) - return NULL; + goto fail; - phy->pll = msm_dsi_pll_init(pdev, type, id); + phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id); if (!phy->pll) - pr_info("%s: pll init failed, need separate pll clk driver\n", + dev_info(&pdev->dev, + "%s: pll init failed, need separate pll clk driver\n", __func__); dsi_phy_disable_resource(phy); - return phy; + platform_set_drvdata(pdev, phy); + + return 0; + +fail: + return ret; } -void msm_dsi_phy_destroy(struct msm_dsi_phy *phy) +static int dsi_phy_driver_remove(struct platform_device *pdev) { - if (phy->pll) { + struct msm_dsi_phy *phy = platform_get_drvdata(pdev); + + if (phy && phy->pll) { msm_dsi_pll_destroy(phy->pll); phy->pll = NULL; } + + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver dsi_phy_platform_driver = { + .probe = dsi_phy_driver_probe, + .remove = dsi_phy_driver_remove, + .driver = { + .name = "msm_dsi_phy", + .of_match_table = dsi_phy_dt_match, + }, +}; + +void __init msm_dsi_phy_driver_register(void) +{ + platform_driver_register(&dsi_phy_platform_driver); +} + +void __exit msm_dsi_phy_driver_unregister(void) +{ + platform_driver_unregister(&dsi_phy_platform_driver); } int msm_dsi_phy_enable(struct msm_dsi_phy *phy, bool is_dual_panel, const unsigned long bit_rate, const unsigned long esc_rate) { - if (!phy || !phy->enable) + int ret; + + if (!phy || !phy->cfg->ops.enable) return -EINVAL; - return phy->enable(phy, is_dual_panel, bit_rate, esc_rate); + + ret = dsi_phy_regulator_enable(phy); + if (ret) { + dev_err(&phy->pdev->dev, "%s: regulator enable failed, %d\n", + __func__, ret); + return ret; + } + + return phy->cfg->ops.enable(phy, is_dual_panel, bit_rate, esc_rate); } int msm_dsi_phy_disable(struct msm_dsi_phy *phy) { - if (!phy || !phy->disable) + if (!phy || !phy->cfg->ops.disable) return -EINVAL; - return phy->disable(phy); + + phy->cfg->ops.disable(phy); + dsi_phy_regulator_disable(phy); + + return 0; } void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy, -- cgit v1.2.3 From 9590e69db93d72684f6f1ae7307e2cac7aa5bca8 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 20 May 2015 09:21:41 +0200 Subject: drm/msm: use devm_gpiod_get_optional for optional reset gpio MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since 39b2bbe3d715 (gpio: add flags argument to gpiod_get*() functions) which appeared in v3.17-rc1, the gpiod_get* functions take an additional parameter that allows to specify direction and initial value for output. Also there is a variant to find optional gpios that returns NULL if there is no gpio instead of -ENOENT. Make use of both features to simplify the driver. This makes error checking more strict because errors like -ENOSYS ("no gpio support compiled in") or -EPROBE_DEFER ("gpio not ready yet") are handled correctly now. Furthermore this is one caller less that stops us making the flags argument to gpiod_get*() mandatory. Reviewed-by: Linus Walleij Signed-off-by: Uwe Kleine-König Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/dsi/dsi_host.c | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index bc2e405758e3..604d80b85e42 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1349,36 +1349,19 @@ static irqreturn_t dsi_host_irq(int irq, void *ptr) static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, struct device *panel_device) { - int ret; - - msm_host->disp_en_gpio = devm_gpiod_get(panel_device, - "disp-enable"); + msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, + "disp-enable", + GPIOD_OUT_LOW); if (IS_ERR(msm_host->disp_en_gpio)) { DBG("cannot get disp-enable-gpios %ld", PTR_ERR(msm_host->disp_en_gpio)); - msm_host->disp_en_gpio = NULL; - } - if (msm_host->disp_en_gpio) { - ret = gpiod_direction_output(msm_host->disp_en_gpio, 0); - if (ret) { - pr_err("cannot set dir to disp-en-gpios %d\n", ret); - return ret; - } + return PTR_ERR(msm_host->disp_en_gpio); } - msm_host->te_gpio = devm_gpiod_get(panel_device, "disp-te"); + msm_host->te_gpio = devm_gpiod_get(panel_device, "disp-te", GPIOD_IN); if (IS_ERR(msm_host->te_gpio)) { DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); - msm_host->te_gpio = NULL; - } - - if (msm_host->te_gpio) { - ret = gpiod_direction_input(msm_host->te_gpio); - if (ret) { - pr_err("%s: cannot set dir to disp-te-gpios, %d\n", - __func__, ret); - return ret; - } + return PTR_ERR(msm_host->te_gpio); } return 0; -- cgit v1.2.3 From 964a0754e49691d0d675ac00d09042118f098cd0 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Wed, 20 May 2015 15:59:31 -0700 Subject: drm/msm: dsi: fix compile errors when CONFIG_GPIOLIB=n MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I'm not sure where, exactly, but somewhere in here we must be relying on an implicit include. drivers/gpu/drm/msm/dsi/dsi_host.c: In function ‘dsi_host_init_panel_gpios’: drivers/gpu/drm/msm/dsi/dsi_host.c:1356:2: error: implicit declaration of function ‘devm_gpiod_get’ [-Werror=implicit-function-declaration] msm_host->disp_en_gpio = devm_gpiod_get(panel_device, ^ drivers/gpu/drm/msm/dsi/dsi_host.c:1356:25: warning: assignment makes pointer from integer without a cast [enabled by default] msm_host->disp_en_gpio = devm_gpiod_get(panel_device, ^ drivers/gpu/drm/msm/dsi/dsi_host.c:1364:3: error: implicit declaration of function ‘gpiod_direction_output’ [-Werror=implicit-function-declaration] ret = gpiod_direction_output(msm_host->disp_en_gpio, 0); ^ drivers/gpu/drm/msm/dsi/dsi_host.c:1371:20: warning: assignment makes pointer from integer without a cast [enabled by default] msm_host->te_gpio = devm_gpiod_get(panel_device, "disp-te"); ^ drivers/gpu/drm/msm/dsi/dsi_host.c:1378:3: error: implicit declaration of function ‘gpiod_direction_input’ [-Werror=implicit-function-declaration] ret = gpiod_direction_input(msm_host->te_gpio); ^ drivers/gpu/drm/msm/dsi/dsi_host.c: In function ‘msm_dsi_host_power_on’: drivers/gpu/drm/msm/dsi/dsi_host.c:1918:3: error: implicit declaration of function ‘gpiod_set_value’ [-Werror=implicit-function-declaration] gpiod_set_value(msm_host->disp_en_gpio, 1); ^ Signed-off-by: Brian Norris Cc: David Airlie Cc: Rob Clark Cc: Hai Li Cc: dri-devel@lists.freedesktop.org Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/dsi/dsi_host.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 604d80b85e42..de0400923303 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3 From 1efb92a306f08119c81de148b05afc24446b8d7a Mon Sep 17 00:00:00 2001 From: Hai Li Date: Fri, 22 May 2015 10:16:46 -0400 Subject: drm/msm/mdp5: Always generate active-high sync signals for DSI DSI video mode engine can only take active-high sync signals. This change prevents MDP5 sending active-low sync signals to DSI in any case. Signed-off-by: Hai Li Tested-by: Archit Taneja Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c index 84d0a7b92918..de97c08f3f1f 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c @@ -144,10 +144,14 @@ static void mdp5_encoder_mode_set(struct drm_encoder *encoder, mode->type, mode->flags); ctrl_pol = 0; - if (mode->flags & DRM_MODE_FLAG_NHSYNC) - ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW; - if (mode->flags & DRM_MODE_FLAG_NVSYNC) - ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW; + + /* DSI controller cannot handle active-low sync signals. */ + if (mdp5_encoder->intf.type != INTF_DSI) { + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW; + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW; + } /* probably need to get DATA_EN polarity from panel.. */ dtv_hsync_skew = 0; /* get this from panel? */ -- cgit v1.2.3 From f65c18c050b8386dbeec26e965bc018bb808cc88 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 27 May 2015 14:39:46 +0300 Subject: drm/msm/atomic: Clean up planes in the error paths of .atomic_commit() When the .atomic_commit() handler fails, clean up planes previoulsy prepared by drm_atomic_helper_prepare_planes() with a call to drm_atomic_helper_cleanup_planes(). Signed-off-by: Laurent Pinchart Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_atomic.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index 84c0a72b446b..b421c843c9df 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -213,8 +213,10 @@ int msm_atomic_commit(struct drm_device *dev, return ret; c = commit_init(state); - if (!c) - return -ENOMEM; + if (!c) { + ret = -ENOMEM; + goto error; + } /* * Figure out what crtcs we have: @@ -247,7 +249,7 @@ int msm_atomic_commit(struct drm_device *dev, ret = start_atomic(dev->dev_private, c->crtc_mask); if (ret) { kfree(c); - return ret; + goto error; } /* @@ -291,4 +293,8 @@ int msm_atomic_commit(struct drm_device *dev, complete_commit(c); return 0; + +error: + drm_atomic_helper_cleanup_planes(dev, state); + return ret; } -- cgit v1.2.3 From fbd4ae8a4eab0a3549f3646c3fb6ddbb414da4b3 Mon Sep 17 00:00:00 2001 From: Stephane Viau Date: Wed, 3 Jun 2015 17:27:21 -0400 Subject: drm/msm/mdp: Add support for more 32-bit RGB formats That will complete the lists of Alpha + RGB formats. Signed-off-by: Stephane Viau Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/mdp/mdp_format.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/mdp/mdp_format.c b/drivers/gpu/drm/msm/mdp/mdp_format.c index f683433b6727..7b0524dc1872 100644 --- a/drivers/gpu/drm/msm/mdp/mdp_format.c +++ b/drivers/gpu/drm/msm/mdp/mdp_format.c @@ -96,6 +96,12 @@ static const struct mdp_format formats[] = { /* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */ FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4, MDP_PLANE_INTERLEAVED, CHROMA_RGB), + FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4, + MDP_PLANE_INTERLEAVED, CHROMA_RGB), + FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4, + MDP_PLANE_INTERLEAVED, CHROMA_RGB), + FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4, + MDP_PLANE_INTERLEAVED, CHROMA_RGB), FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4, MDP_PLANE_INTERLEAVED, CHROMA_RGB), FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3, -- cgit v1.2.3 From 5e4eb82fc23bafa76b0b010f41401eb75db9a851 Mon Sep 17 00:00:00 2001 From: Stephane Viau Date: Thu, 4 Jun 2015 17:31:41 -0400 Subject: drm/msm/hdmi: Point to the right struct device DRM device's dev (hdmi->dev->dev) points to the mdss_mdp device handle. Instead, we should get a reference to the mdss_hdmi handle. Signed-off-by: Stephane Viau Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 32 +++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c index b62cdb968614..bf72ad62bf82 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c @@ -29,14 +29,14 @@ struct hdmi_connector { static int gpio_config(struct hdmi *hdmi, bool on) { - struct drm_device *dev = hdmi->dev; + struct device *dev = &hdmi->pdev->dev; const struct hdmi_platform_config *config = hdmi->config; int ret; if (on) { ret = gpio_request(config->ddc_clk_gpio, "HDMI_DDC_CLK"); if (ret) { - dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n", + dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", "HDMI_DDC_CLK", config->ddc_clk_gpio, ret); goto error1; } @@ -44,7 +44,7 @@ static int gpio_config(struct hdmi *hdmi, bool on) ret = gpio_request(config->ddc_data_gpio, "HDMI_DDC_DATA"); if (ret) { - dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n", + dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", "HDMI_DDC_DATA", config->ddc_data_gpio, ret); goto error2; } @@ -52,7 +52,7 @@ static int gpio_config(struct hdmi *hdmi, bool on) ret = gpio_request(config->hpd_gpio, "HDMI_HPD"); if (ret) { - dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n", + dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", "HDMI_HPD", config->hpd_gpio, ret); goto error3; } @@ -62,7 +62,7 @@ static int gpio_config(struct hdmi *hdmi, bool on) if (config->mux_en_gpio != -1) { ret = gpio_request(config->mux_en_gpio, "HDMI_MUX_EN"); if (ret) { - dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n", + dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", "HDMI_MUX_EN", config->mux_en_gpio, ret); goto error4; } @@ -72,7 +72,7 @@ static int gpio_config(struct hdmi *hdmi, bool on) if (config->mux_sel_gpio != -1) { ret = gpio_request(config->mux_sel_gpio, "HDMI_MUX_SEL"); if (ret) { - dev_err(dev->dev, "'%s'(%d) gpio_request failed: %d\n", + dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", "HDMI_MUX_SEL", config->mux_sel_gpio, ret); goto error5; } @@ -83,7 +83,7 @@ static int gpio_config(struct hdmi *hdmi, bool on) ret = gpio_request(config->mux_lpm_gpio, "HDMI_MUX_LPM"); if (ret) { - dev_err(dev->dev, + dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", "HDMI_MUX_LPM", config->mux_lpm_gpio, ret); @@ -136,7 +136,7 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector) { struct hdmi *hdmi = hdmi_connector->hdmi; const struct hdmi_platform_config *config = hdmi->config; - struct drm_device *dev = hdmi_connector->base.dev; + struct device *dev = &hdmi->pdev->dev; struct hdmi_phy *phy = hdmi->phy; uint32_t hpd_ctrl; int i, ret; @@ -144,7 +144,7 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector) for (i = 0; i < config->hpd_reg_cnt; i++) { ret = regulator_enable(hdmi->hpd_regs[i]); if (ret) { - dev_err(dev->dev, "failed to enable hpd regulator: %s (%d)\n", + dev_err(dev, "failed to enable hpd regulator: %s (%d)\n", config->hpd_reg_names[i], ret); goto fail; } @@ -152,7 +152,7 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector) ret = gpio_config(hdmi, true); if (ret) { - dev_err(dev->dev, "failed to configure GPIOs: %d\n", ret); + dev_err(dev, "failed to configure GPIOs: %d\n", ret); goto fail; } @@ -161,13 +161,13 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector) ret = clk_set_rate(hdmi->hpd_clks[i], config->hpd_freq[i]); if (ret) - dev_warn(dev->dev, "failed to set clk %s (%d)\n", + dev_warn(dev, "failed to set clk %s (%d)\n", config->hpd_clk_names[i], ret); } ret = clk_prepare_enable(hdmi->hpd_clks[i]); if (ret) { - dev_err(dev->dev, "failed to enable hpd clk: %s (%d)\n", + dev_err(dev, "failed to enable hpd clk: %s (%d)\n", config->hpd_clk_names[i], ret); goto fail; } @@ -204,7 +204,7 @@ static void hdp_disable(struct hdmi_connector *hdmi_connector) { struct hdmi *hdmi = hdmi_connector->hdmi; const struct hdmi_platform_config *config = hdmi->config; - struct drm_device *dev = hdmi_connector->base.dev; + struct device *dev = &hdmi->pdev->dev; int i, ret = 0; /* Disable HPD interrupt */ @@ -217,12 +217,12 @@ static void hdp_disable(struct hdmi_connector *hdmi_connector) ret = gpio_config(hdmi, false); if (ret) - dev_warn(dev->dev, "failed to unconfigure GPIOs: %d\n", ret); + dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret); for (i = 0; i < config->hpd_reg_cnt; i++) { ret = regulator_disable(hdmi->hpd_regs[i]); if (ret) - dev_warn(dev->dev, "failed to disable hpd regulator: %s (%d)\n", + dev_warn(dev, "failed to disable hpd regulator: %s (%d)\n", config->hpd_reg_names[i], ret); } } @@ -433,7 +433,7 @@ struct drm_connector *hdmi_connector_init(struct hdmi *hdmi) ret = hpd_enable(hdmi_connector); if (ret) { - dev_err(hdmi->dev->dev, "failed to enable HPD: %d\n", ret); + dev_err(&hdmi->pdev->dev, "failed to enable HPD: %d\n", ret); goto fail; } -- cgit v1.2.3 From 865807d0a96934593bc143e374b353d9c17e977f Mon Sep 17 00:00:00 2001 From: Stephane Viau Date: Thu, 4 Jun 2015 17:31:42 -0400 Subject: drm/msm/hdmi: Use pinctrl in HDMI driver Some targets (eg: msm8994) use the pinctrl framework to configure interface pins. This change adds support for initialization and pinctrl active/sleep state control for the HDMI driver. Signed-off-by: Stephane Viau Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/drm/msm/hdmi.txt | 6 ++++++ drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 11 +++++++++++ 2 files changed, 17 insertions(+) (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/drm/msm/hdmi.txt b/Documentation/devicetree/bindings/drm/msm/hdmi.txt index a29a55f3d937..c43aa53debed 100644 --- a/Documentation/devicetree/bindings/drm/msm/hdmi.txt +++ b/Documentation/devicetree/bindings/drm/msm/hdmi.txt @@ -20,6 +20,9 @@ Required properties: Optional properties: - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin +- pinctrl-names: the pin control state names; should contain "default" +- pinctrl-0: the default pinctrl state (active) +- pinctrl-1: the "sleep" pinctrl state Example: @@ -44,5 +47,8 @@ Example: qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; core-vdda-supply = <&pm8921_hdmi_mvs>; hdmi-mux-supply = <&ext_3p3v>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hpd_active &ddc_active &cec_active>; + pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; }; }; diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c index bf72ad62bf82..54aa93ff5473 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c @@ -16,6 +16,7 @@ */ #include +#include #include "msm_kms.h" #include "hdmi.h" @@ -150,6 +151,12 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector) } } + ret = pinctrl_pm_select_default_state(dev); + if (ret) { + dev_err(dev, "pinctrl state chg failed: %d\n", ret); + goto fail; + } + ret = gpio_config(hdmi, true); if (ret) { dev_err(dev, "failed to configure GPIOs: %d\n", ret); @@ -219,6 +226,10 @@ static void hdp_disable(struct hdmi_connector *hdmi_connector) if (ret) dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret); + ret = pinctrl_pm_select_sleep_state(dev); + if (ret) + dev_warn(dev, "pinctrl state chg failed: %d\n", ret); + for (i = 0; i < config->hpd_reg_cnt; i++) { ret = regulator_disable(hdmi->hpd_regs[i]); if (ret) -- cgit v1.2.3 From 56c2da8338d5cdfc0695eeed96ebe03cf2ac0321 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 11 May 2015 11:50:03 -0400 Subject: drm/msm: fix timeout calculation The 'timeout' value comes from userspace (CLOCK_MONOTONIC), but converting this directly to jiffies doesn't take into account the initial jiffies count at boot, which may differ from the base time of CLOCK_MONOTONIC. TODO: add ktime_delta_jiffies() when rebasing on 4.1 and use that instead of ktime_sub/ktime_to_timespec/timespec_to_jiffies combo (as suggested by Arnd) v2: switch over from 'struct timespec' to ktime_t throughout, since 'struct timespec' will be deprecated (as suggested by Arnd) v3: minor cosmetic tweaks Cc: Arnd Bergmann Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_atomic.c | 4 ++-- drivers/gpu/drm/msm/msm_drv.c | 26 ++++++++++++++++---------- drivers/gpu/drm/msm/msm_drv.h | 4 ++-- drivers/gpu/drm/msm/msm_gem.c | 3 +-- 4 files changed, 21 insertions(+), 16 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index b421c843c9df..1b22d8bfe142 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -204,7 +204,7 @@ int msm_atomic_commit(struct drm_device *dev, { int nplanes = dev->mode_config.num_total_plane; int ncrtcs = dev->mode_config.num_crtc; - struct timespec timeout; + ktime_t timeout; struct msm_commit *c; int i, ret; @@ -281,7 +281,7 @@ int msm_atomic_commit(struct drm_device *dev, return 0; } - jiffies_to_timespec(jiffies + msecs_to_jiffies(1000), &timeout); + timeout = ktime_add_ms(ktime_get(), 1000); ret = msm_wait_fence_interruptable(dev, c->fence, &timeout); if (ret) { diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 7efd3071481d..b7ef56ed8d1c 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -638,7 +638,7 @@ static void msm_debugfs_cleanup(struct drm_minor *minor) */ int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, - struct timespec *timeout) + ktime_t *timeout) { struct msm_drm_private *priv = dev->dev_private; int ret; @@ -656,14 +656,16 @@ int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, /* no-wait: */ ret = fence_completed(dev, fence) ? 0 : -EBUSY; } else { - unsigned long timeout_jiffies = timespec_to_jiffies(timeout); - unsigned long start_jiffies = jiffies; + ktime_t now = ktime_get(); unsigned long remaining_jiffies; - if (time_after(start_jiffies, timeout_jiffies)) + if (ktime_compare(*timeout, now) < 0) { remaining_jiffies = 0; - else - remaining_jiffies = timeout_jiffies - start_jiffies; + } else { + ktime_t rem = ktime_sub(*timeout, now); + struct timespec ts = ktime_to_timespec(rem); + remaining_jiffies = timespec_to_jiffies(&ts); + } ret = wait_event_interruptible_timeout(priv->fence_event, fence_completed(dev, fence), @@ -772,13 +774,17 @@ static int msm_ioctl_gem_new(struct drm_device *dev, void *data, args->flags, &args->handle); } -#define TS(t) ((struct timespec){ .tv_sec = (t).tv_sec, .tv_nsec = (t).tv_nsec }) +static inline ktime_t to_ktime(struct drm_msm_timespec timeout) +{ + return ktime_set(timeout.tv_sec, timeout.tv_nsec); +} static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, struct drm_file *file) { struct drm_msm_gem_cpu_prep *args = data; struct drm_gem_object *obj; + ktime_t timeout = to_ktime(args->timeout); int ret; if (args->op & ~MSM_PREP_FLAGS) { @@ -790,7 +796,7 @@ static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, if (!obj) return -ENOENT; - ret = msm_gem_cpu_prep(obj, args->op, &TS(args->timeout)); + ret = msm_gem_cpu_prep(obj, args->op, &timeout); drm_gem_object_unreference_unlocked(obj); @@ -840,14 +846,14 @@ static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, struct drm_file *file) { struct drm_msm_wait_fence *args = data; + ktime_t timeout = to_ktime(args->timeout); if (args->pad) { DRM_ERROR("invalid pad: %08x\n", args->pad); return -EINVAL; } - return msm_wait_fence_interruptable(dev, args->fence, - &TS(args->timeout)); + return msm_wait_fence_interruptable(dev, args->fence, &timeout); } static const struct drm_ioctl_desc msm_ioctls[] = { diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 04db4bd1b5b6..e7c5ea125d45 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -165,7 +165,7 @@ int msm_atomic_commit(struct drm_device *dev, int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, - struct timespec *timeout); + ktime_t *timeout); int msm_queue_fence_cb(struct drm_device *dev, struct msm_fence_cb *cb, uint32_t fence); void msm_update_fence(struct drm_device *dev, uint32_t fence); @@ -205,7 +205,7 @@ void msm_gem_move_to_active(struct drm_gem_object *obj, struct msm_gpu *gpu, bool write, uint32_t fence); void msm_gem_move_to_inactive(struct drm_gem_object *obj); int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, - struct timespec *timeout); + ktime_t *timeout); int msm_gem_cpu_fini(struct drm_gem_object *obj); void msm_gem_free_object(struct drm_gem_object *obj); int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index dfc74a5736a3..f211b80e3a1e 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -448,8 +448,7 @@ void msm_gem_move_to_inactive(struct drm_gem_object *obj) list_add_tail(&msm_obj->mm_list, &priv->inactive_list); } -int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, - struct timespec *timeout) +int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout) { struct drm_device *dev = obj->dev; struct msm_gem_object *msm_obj = to_msm_bo(obj); -- cgit v1.2.3 From 1a370be9ac51129e40b0ed7fa71d2b2b92bc47e5 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sun, 7 Jun 2015 13:46:04 -0400 Subject: drm/msm: restart queued submits after hang Track the list of in-flight submits. If the gpu hangs, retire up to an including the offending submit, and then re-submit the remainder. This way, for concurrently running piglit tests (for example), one failing test doesn't cause unrelated tests to fail simply because it's submit was queued up after one that triggered a hang. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_gem.h | 1 + drivers/gpu/drm/msm/msm_gem_submit.c | 1 - drivers/gpu/drm/msm/msm_gpu.c | 49 +++++++++++++++++++++++++++++++++--- drivers/gpu/drm/msm/msm_gpu.h | 2 ++ 4 files changed, 49 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h index 85d481e29276..6fc59bfeedeb 100644 --- a/drivers/gpu/drm/msm/msm_gem.h +++ b/drivers/gpu/drm/msm/msm_gem.h @@ -96,6 +96,7 @@ static inline uint32_t msm_gem_fence(struct msm_gem_object *msm_obj, struct msm_gem_submit { struct drm_device *dev; struct msm_gpu *gpu; + struct list_head node; /* node in gpu submit_list */ struct list_head bo_list; struct ww_acquire_ctx ticket; uint32_t fence; diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index cd0554f68316..6d7cd3fe21e7 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -314,7 +314,6 @@ static void submit_cleanup(struct msm_gem_submit *submit, bool fail) } ww_acquire_fini(&submit->ticket); - kfree(submit); } int msm_ioctl_gem_submit(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 4016aef56c50..8f70d9248ac5 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -265,6 +265,8 @@ static void inactive_start(struct msm_gpu *gpu) * Hangcheck detection for locked gpu: */ +static void retire_submits(struct msm_gpu *gpu, uint32_t fence); + static void recover_worker(struct work_struct *work) { struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); @@ -274,8 +276,19 @@ static void recover_worker(struct work_struct *work) mutex_lock(&dev->struct_mutex); if (msm_gpu_active(gpu)) { + struct msm_gem_submit *submit; + uint32_t fence = gpu->funcs->last_fence(gpu); + + /* retire completed submits, plus the one that hung: */ + retire_submits(gpu, fence + 1); + inactive_cancel(gpu); gpu->funcs->recover(gpu); + + /* replay the remaining submits after the one that hung: */ + list_for_each_entry(submit, &gpu->submit_list, node) { + gpu->funcs->submit(gpu, submit, NULL); + } } mutex_unlock(&dev->struct_mutex); @@ -418,6 +431,27 @@ out: * Cmdstream submission/retirement: */ +static void retire_submits(struct msm_gpu *gpu, uint32_t fence) +{ + struct drm_device *dev = gpu->dev; + + WARN_ON(!mutex_is_locked(&dev->struct_mutex)); + + while (!list_empty(&gpu->submit_list)) { + struct msm_gem_submit *submit; + + submit = list_first_entry(&gpu->submit_list, + struct msm_gem_submit, node); + + if (submit->fence <= fence) { + list_del(&submit->node); + kfree(submit); + } else { + break; + } + } +} + static void retire_worker(struct work_struct *work) { struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); @@ -428,6 +462,8 @@ static void retire_worker(struct work_struct *work) mutex_lock(&dev->struct_mutex); + retire_submits(gpu, fence); + while (!list_empty(&gpu->active_list)) { struct msm_gem_object *obj; @@ -467,21 +503,22 @@ int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, struct msm_drm_private *priv = dev->dev_private; int i, ret; + WARN_ON(!mutex_is_locked(&dev->struct_mutex)); + submit->fence = ++priv->next_fence; gpu->submitted_fence = submit->fence; inactive_cancel(gpu); + list_add_tail(&submit->node, &gpu->submit_list); + msm_rd_dump_submit(submit); gpu->submitted_fence = submit->fence; update_sw_cntrs(gpu); - ret = gpu->funcs->submit(gpu, submit, ctx); - priv->lastctx = ctx; - for (i = 0; i < submit->nr_bos; i++) { struct msm_gem_object *msm_obj = submit->bos[i].obj; @@ -505,6 +542,10 @@ int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE) msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence); } + + ret = gpu->funcs->submit(gpu, submit, ctx); + priv->lastctx = ctx; + hangcheck_timer_reset(gpu); return ret; @@ -545,6 +586,8 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, INIT_WORK(&gpu->inactive_work, inactive_worker); INIT_WORK(&gpu->recover_work, recover_worker); + INIT_LIST_HEAD(&gpu->submit_list); + setup_timer(&gpu->inactive_timer, inactive_handler, (unsigned long)gpu); setup_timer(&gpu->hangcheck_timer, hangcheck_handler, diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 7b3ec21d5d77..2bbe85a3d6f6 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -119,6 +119,8 @@ struct msm_gpu { struct timer_list hangcheck_timer; uint32_t hangcheck_fence; struct work_struct recover_work; + + struct list_head submit_list; }; static inline bool msm_gpu_active(struct msm_gpu *gpu) -- cgit v1.2.3 From 3c1dae0a07c651526f8e878d223a88f82caa5a50 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 11 Jun 2015 18:33:48 +0200 Subject: drm/tegra: dpaux: Fix transfers larger than 4 bytes The DPAUX read/write FIFO registers aren't sequential in the register space, causing transfers larger than 4 bytes to cause accesses to non- existing FIFO registers. Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support") Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dpaux.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index d6b55e3e3716..a43a836e6f88 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -72,34 +72,32 @@ static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer, size_t size) { - unsigned long offset = DPAUX_DP_AUXDATA_WRITE(0); size_t i, j; - for (i = 0; i < size; i += 4) { - size_t num = min_t(size_t, size - i, 4); + for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { + size_t num = min_t(size_t, size - i * 4, 4); unsigned long value = 0; for (j = 0; j < num; j++) - value |= buffer[i + j] << (j * 8); + value |= buffer[i * 4 + j] << (j * 8); - tegra_dpaux_writel(dpaux, value, offset++); + tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i)); } } static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer, size_t size) { - unsigned long offset = DPAUX_DP_AUXDATA_READ(0); size_t i, j; - for (i = 0; i < size; i += 4) { - size_t num = min_t(size_t, size - i, 4); + for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { + size_t num = min_t(size_t, size - i * 4, 4); unsigned long value; - value = tegra_dpaux_readl(dpaux, offset++); + value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i)); for (j = 0; j < num; j++) - buffer[i + j] = value >> (j * 8); + buffer[i * 4 + j] = value >> (j * 8); } } -- cgit v1.2.3 From 4553f733c68b66ef49f838aa24470d58caf76ff5 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 19 Jan 2015 16:15:04 +0100 Subject: drm/tegra: gem: Take into account IOMMU aperture The IOMMU may not always be able to address 2 GiB of memory. On Tegra20, the GART supports 32 MiB starting at 0x58000000. Also the aperture on Tegra30 and later is in fact the full 4 GiB, rather than just 2 GiB as currently assumed. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/drm.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 1833abd7d3aa..106208463b37 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -124,14 +124,22 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) return -ENOMEM; if (iommu_present(&platform_bus_type)) { + struct iommu_domain_geometry *geometry; + u64 start, end; + tegra->domain = iommu_domain_alloc(&platform_bus_type); if (!tegra->domain) { err = -ENOMEM; goto free; } - DRM_DEBUG("IOMMU context initialized\n"); - drm_mm_init(&tegra->mm, 0, SZ_2G); + geometry = &tegra->domain->geometry; + start = geometry->aperture_start; + end = geometry->aperture_end; + + DRM_DEBUG("IOMMU context initialized (aperture: %#llx-%#llx)\n", + start, end); + drm_mm_init(&tegra->mm, start, end - start + 1); } mutex_init(&tegra->clients_lock); -- cgit v1.2.3 From fd73caa5e72f0fcf9732b18d123eead96286fd5b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 14 Apr 2015 12:52:36 +0200 Subject: drm/tegra: gem: Flush pages after allocation Pages allocated from shmemfs don't end up being cleared and flushed on ARMv7, so they must be flushed explicitly. Use the DMA mapping API for that purpose, even though it's not used for anything else. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/gem.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c index 1217272a51f2..01e16e146bfe 100644 --- a/drivers/gpu/drm/tegra/gem.c +++ b/drivers/gpu/drm/tegra/gem.c @@ -189,7 +189,6 @@ static void tegra_bo_free(struct drm_device *drm, struct tegra_bo *bo) static int tegra_bo_get_pages(struct drm_device *drm, struct tegra_bo *bo) { struct scatterlist *s; - struct sg_table *sgt; unsigned int i; bo->pages = drm_gem_get_pages(&bo->gem); @@ -198,36 +197,28 @@ static int tegra_bo_get_pages(struct drm_device *drm, struct tegra_bo *bo) bo->num_pages = bo->gem.size >> PAGE_SHIFT; - sgt = drm_prime_pages_to_sg(bo->pages, bo->num_pages); - if (IS_ERR(sgt)) + bo->sgt = drm_prime_pages_to_sg(bo->pages, bo->num_pages); + if (IS_ERR(bo->sgt)) goto put_pages; /* - * Fake up the SG table so that dma_map_sg() can be used to flush the - * pages associated with it. Note that this relies on the fact that - * the DMA API doesn't hook into IOMMU on Tegra, therefore mapping is - * only cache maintenance. + * Fake up the SG table so that dma_sync_sg_for_device() can be used + * to flush the pages associated with it. * * TODO: Replace this by drm_clflash_sg() once it can be implemented * without relying on symbols that are not exported. */ - for_each_sg(sgt->sgl, s, sgt->nents, i) + for_each_sg(bo->sgt->sgl, s, bo->sgt->nents, i) sg_dma_address(s) = sg_phys(s); - if (dma_map_sg(drm->dev, sgt->sgl, sgt->nents, DMA_TO_DEVICE) == 0) - goto release_sgt; - - bo->sgt = sgt; + dma_sync_sg_for_device(drm->dev, bo->sgt->sgl, bo->sgt->nents, + DMA_TO_DEVICE); return 0; -release_sgt: - sg_free_table(sgt); - kfree(sgt); - sgt = ERR_PTR(-ENOMEM); put_pages: drm_gem_put_pages(&bo->gem, bo->pages, false, false); - return PTR_ERR(sgt); + return PTR_ERR(bo->sgt); } static int tegra_bo_alloc(struct drm_device *drm, struct tegra_bo *bo) -- cgit v1.2.3 From 8a8005e3e19915559b542bf85cc1b17024ee1d31 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 2 Jun 2015 13:13:01 +0200 Subject: drm/tegra: dpaux: Registers are 32-bit Use a sized unsigned 32-bit data type (u32) to store register contents. The DPAUX registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dpaux.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index a43a836e6f88..07b26972f487 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -56,15 +56,14 @@ static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work) return container_of(work, struct tegra_dpaux, work); } -static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux, - unsigned long offset) +static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux, + unsigned long offset) { return readl(dpaux->regs + (offset << 2)); } static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, - unsigned long value, - unsigned long offset) + u32 value, unsigned long offset) { writel(value, dpaux->regs + (offset << 2)); } @@ -76,7 +75,7 @@ static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer, for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { size_t num = min_t(size_t, size - i * 4, 4); - unsigned long value = 0; + u32 value = 0; for (j = 0; j < num; j++) value |= buffer[i * 4 + j] << (j * 8); @@ -92,7 +91,7 @@ static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer, for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { size_t num = min_t(size_t, size - i * 4, 4); - unsigned long value; + u32 value; value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i)); @@ -248,7 +247,7 @@ static irqreturn_t tegra_dpaux_irq(int irq, void *data) { struct tegra_dpaux *dpaux = data; irqreturn_t ret = IRQ_HANDLED; - unsigned long value; + u32 value; /* clear interrupts */ value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX); @@ -271,7 +270,7 @@ static int tegra_dpaux_probe(struct platform_device *pdev) { struct tegra_dpaux *dpaux; struct resource *regs; - unsigned long value; + u32 value; int err; dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL); @@ -463,7 +462,7 @@ int tegra_dpaux_detach(struct tegra_dpaux *dpaux) enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux) { - unsigned long value; + u32 value; value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); @@ -475,7 +474,7 @@ enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux) int tegra_dpaux_enable(struct tegra_dpaux *dpaux) { - unsigned long value; + u32 value; value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) | DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) | @@ -493,7 +492,7 @@ int tegra_dpaux_enable(struct tegra_dpaux *dpaux) int tegra_dpaux_disable(struct tegra_dpaux *dpaux) { - unsigned long value; + u32 value; value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; -- cgit v1.2.3 From c0d607e5a2b266131c7ef7aba10e0cdf50ee24c0 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 13 Apr 2015 15:09:26 -0700 Subject: drm/panel: simple: Add display timing for HannStar HSD100PXN1 Add support for the Hannstar HSD100PXN1 to the DRM simple panel driver. The HSD100PXN1 is an XGA (1024x768) panel with an 18-bit LVDS interface. It supports pixel clocks in the range of 55-75 MHz. This panel is offered for sale by Freescale as a companion part to its' i.MX5x Quick Start board and i.MX6 SABRE platforms with under the name MCIMX-LVDS1. Signed-off-by: Eric Nelson Signed-off-by: Thierry Reding --- .../bindings/panel/hannstar,hsd100pxn1.txt | 7 ++++++ drivers/gpu/drm/panel/panel-simple.c | 26 ++++++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/hannstar,hsd100pxn1.txt (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/panel/hannstar,hsd100pxn1.txt b/Documentation/devicetree/bindings/panel/hannstar,hsd100pxn1.txt new file mode 100644 index 000000000000..8270319a99de --- /dev/null +++ b/Documentation/devicetree/bindings/panel/hannstar,hsd100pxn1.txt @@ -0,0 +1,7 @@ +HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel + +Required properties: +- compatible: should be "hannstar,hsd100pxn1" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index a06d9d353bec..97b66b86ad8e 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -731,6 +731,29 @@ static const struct panel_desc hannstar_hsd070pww1 = { }, }; +static const struct display_timing hannstar_hsd100pxn1_timing = { + .pixelclock = { 55000000, 65000000, 75000000 }, + .hactive = { 1024, 1024, 1024 }, + .hfront_porch = { 40, 40, 40 }, + .hback_porch = { 220, 220, 220 }, + .hsync_len = { 20, 60, 100 }, + .vactive = { 768, 768, 768 }, + .vfront_porch = { 7, 7, 7 }, + .vback_porch = { 21, 21, 21 }, + .vsync_len = { 10, 10, 10 }, + .flags = DISPLAY_FLAGS_DE_HIGH, +}; + +static const struct panel_desc hannstar_hsd100pxn1 = { + .timings = &hannstar_hsd100pxn1_timing, + .num_timings = 1, + .bpc = 6, + .size = { + .width = 203, + .height = 152, + }, +}; + static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { .clock = 33333, .hdisplay = 800, @@ -1061,6 +1084,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "hannstar,hsd070pww1", .data = &hannstar_hsd070pww1, + }, { + .compatible = "hannstar,hsd100pxn1", + .data = &hannstar_hsd100pxn1, }, { .compatible = "hit,tx23d38vm0caa", .data = &hitachi_tx23d38vm0caa -- cgit v1.2.3 From 4946b0430c6933383d33adf101529b7085a4a682 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Wed, 20 May 2015 11:34:08 +0200 Subject: drm/panel: simple: Add bus format for HannStar HSD100PXN1 This patch adds the bus_format field to the HSD100PXN1 panel structure. Signed-off-by: Philipp Zabel Signed-off-by: Thierry Reding --- drivers/gpu/drm/panel/panel-simple.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 97b66b86ad8e..f94201b6e882 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -752,6 +752,7 @@ static const struct panel_desc hannstar_hsd100pxn1 = { .width = 203, .height = 152, }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, }; static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { -- cgit v1.2.3 From e2cd09b202c5d32804f72bc28a9ed5a7d8a34452 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 6 Mar 2015 17:16:43 +0200 Subject: drm: omapdrm: Store the rotation property in dev->mode_config Rotation is a standard property, store it in dev->mode_config.rotation_property. While at it, extract the properties initialization code to a separate function instead of running it for every plane. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_crtc.c | 4 +--- drivers/gpu/drm/omapdrm/omap_drv.c | 31 ++++++++++++++++++++++++++++--- drivers/gpu/drm/omapdrm/omap_drv.h | 1 - drivers/gpu/drm/omapdrm/omap_plane.c | 27 ++++----------------------- 4 files changed, 33 insertions(+), 30 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index f456544bf300..7a64765d0537 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -646,9 +646,7 @@ static int omap_crtc_page_flip_locked(struct drm_crtc *crtc, static int omap_crtc_set_property(struct drm_crtc *crtc, struct drm_property *property, uint64_t val) { - struct omap_drm_private *priv = crtc->dev->dev_private; - - if (property == priv->rotation_prop) { + if (property == crtc->dev->mode_config.rotation_property) { crtc->invert_dimensions = !!(val & ((1LL << DRM_ROTATE_90) | (1LL << DRM_ROTATE_270))); } diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index 94920d47e3b6..ce6a255d277a 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -151,6 +151,27 @@ static int omap_modeset_create_crtc(struct drm_device *dev, int id, return 0; } +static int omap_modeset_init_properties(struct drm_device *dev) +{ + struct omap_drm_private *priv = dev->dev_private; + + if (priv->has_dmm) { + dev->mode_config.rotation_property = + drm_mode_create_rotation_property(dev, + BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_90) | + BIT(DRM_ROTATE_180) | BIT(DRM_ROTATE_270) | + BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y)); + if (!dev->mode_config.rotation_property) + return -ENOMEM; + } + + priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3); + if (!priv->zorder_prop) + return -ENOMEM; + + return 0; +} + static int omap_modeset_init(struct drm_device *dev) { struct omap_drm_private *priv = dev->dev_private; @@ -165,6 +186,10 @@ static int omap_modeset_init(struct drm_device *dev) omap_drm_irq_install(dev); + ret = omap_modeset_init_properties(dev); + if (ret < 0) + return ret; + /* * We usually don't want to create a CRTC for each manager, at least * not until we have a way to expose private planes to userspace. @@ -583,7 +608,7 @@ static void dev_lastclose(struct drm_device *dev) DBG("lastclose: dev=%p", dev); - if (priv->rotation_prop) { + if (dev->mode_config.rotation_property) { /* need to restore default rotation state.. not sure * if there is a cleaner way to restore properties to * default state? Maybe a flag that properties should @@ -592,12 +617,12 @@ static void dev_lastclose(struct drm_device *dev) */ for (i = 0; i < priv->num_crtcs; i++) { drm_object_property_set_value(&priv->crtcs[i]->base, - priv->rotation_prop, 0); + dev->mode_config.rotation_property, 0); } for (i = 0; i < priv->num_planes; i++) { drm_object_property_set_value(&priv->planes[i]->base, - priv->rotation_prop, 0); + dev->mode_config.rotation_property, 0); } } diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index b31c79f15aed..a42a11c62106 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h @@ -114,7 +114,6 @@ struct omap_drm_private { bool has_dmm; /* properties: */ - struct drm_property *rotation_prop; struct drm_property *zorder_prop; /* irq handling: */ diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 1c6b63f39474..a1c9c08db345 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -297,33 +297,14 @@ void omap_plane_install_properties(struct drm_plane *plane, { struct drm_device *dev = plane->dev; struct omap_drm_private *priv = dev->dev_private; - struct drm_property *prop; if (priv->has_dmm) { - prop = priv->rotation_prop; - if (!prop) { - prop = drm_mode_create_rotation_property(dev, - BIT(DRM_ROTATE_0) | - BIT(DRM_ROTATE_90) | - BIT(DRM_ROTATE_180) | - BIT(DRM_ROTATE_270) | - BIT(DRM_REFLECT_X) | - BIT(DRM_REFLECT_Y)); - if (prop == NULL) - return; - priv->rotation_prop = prop; - } + struct drm_property *prop = dev->mode_config.rotation_property; + drm_object_attach_property(obj, prop, 0); } - prop = priv->zorder_prop; - if (!prop) { - prop = drm_property_create_range(dev, 0, "zorder", 0, 3); - if (prop == NULL) - return; - priv->zorder_prop = prop; - } - drm_object_attach_property(obj, prop, 0); + drm_object_attach_property(obj, priv->zorder_prop, 0); } int omap_plane_set_property(struct drm_plane *plane, @@ -333,7 +314,7 @@ int omap_plane_set_property(struct drm_plane *plane, struct omap_drm_private *priv = plane->dev->dev_private; int ret = -EINVAL; - if (property == priv->rotation_prop) { + if (property == plane->dev->mode_config.rotation_property) { DBG("%s: rotation: %02x", omap_plane->name, (uint32_t)val); omap_plane->win.rotation = val; ret = omap_plane_apply(plane); -- cgit v1.2.3 From a42133a780b368f9ed18045a4453f92292db4b18 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 17 Jan 2015 19:09:26 +0200 Subject: drm: omapdrm: Apply settings synchronously The omapdrm driver implements a mechanism to apply new settings (due to plane update, plane disable, plane property set, CRTC mode set or CRTC DPMS) asynchronously. While this improves performance, it adds a level of complexity that makes transition to the atomic update API close to impossible. Furthermore the atomic update API requires part of the apply operations to be synchronous (such as pinning the framebuffers), so the current implementation needs to be changed. Simplify the CRTC and plane code by making updates synchronous to prepare for the switch to the atomic update API. Asynchronous update will be implemented in a second step. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_crtc.c | 269 +++++++++++++---------------------- drivers/gpu/drm/omapdrm/omap_drv.c | 5 - drivers/gpu/drm/omapdrm/omap_drv.h | 23 +-- drivers/gpu/drm/omapdrm/omap_plane.c | 211 +++++++++++---------------- 4 files changed, 183 insertions(+), 325 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 7a64765d0537..e5fb8c6e25e6 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -17,6 +17,8 @@ * this program. If not, see . */ +#include + #include "omap_drv.h" #include @@ -46,36 +48,33 @@ struct omap_crtc { struct omap_video_timings timings; bool enabled; - struct omap_drm_apply apply; - - struct omap_drm_irq apply_irq; + struct omap_drm_irq vblank_irq; struct omap_drm_irq error_irq; - /* list of in-progress apply's: */ - struct list_head pending_applies; - - /* list of queued apply's: */ - struct list_head queued_applies; - - /* for handling queued and in-progress applies: */ - struct work_struct apply_work; + /* list of framebuffers to unpin */ + struct list_head pending_unpins; /* if there is a pending flip, these will be non-null: */ struct drm_pending_vblank_event *event; struct drm_framebuffer *old_fb; + struct completion completion; + /* for handling page flips without caring about what * the callback is called from. Possibly we should just * make omap_gem always call the cb from the worker so * we don't have to care about this.. - * - * XXX maybe fold into apply_work?? */ struct work_struct page_flip_work; bool ignore_digit_sync_lost; }; +struct omap_framebuffer_unpin { + struct list_head list; + struct drm_framebuffer *fb; +}; + /* ----------------------------------------------------------------------------- * Helper Functions */ @@ -142,7 +141,7 @@ static void omap_crtc_start_update(struct omap_overlay_manager *mgr) { } -/* Called only from CRTC pre_apply and suspend/resume handlers. */ +/* Called only from omap_crtc_setup and suspend/resume handlers. */ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) { struct drm_device *dev = crtc->dev; @@ -261,7 +260,7 @@ static const struct dss_mgr_ops mgr_ops = { }; /* ----------------------------------------------------------------------------- - * Apply Logic + * Setup and Flush */ static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) @@ -278,121 +277,93 @@ static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus); } -static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus) +static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus) { struct omap_crtc *omap_crtc = - container_of(irq, struct omap_crtc, apply_irq); - struct drm_crtc *crtc = &omap_crtc->base; + container_of(irq, struct omap_crtc, vblank_irq); + struct drm_device *dev = omap_crtc->base.dev; + unsigned long flags; - if (!dispc_mgr_go_busy(omap_crtc->channel)) { - struct omap_drm_private *priv = - crtc->dev->dev_private; - DBG("%s: apply done", omap_crtc->name); - __omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq); - queue_work(priv->wq, &omap_crtc->apply_work); - } + if (dispc_mgr_go_busy(omap_crtc->channel)) + return; + + DBG("%s: apply done", omap_crtc->name); + __omap_irq_unregister(dev, &omap_crtc->vblank_irq); + + spin_lock_irqsave(&dev->event_lock, flags); + + /* wakeup userspace */ + if (omap_crtc->event) + drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event); + + omap_crtc->event = NULL; + omap_crtc->old_fb = NULL; + + spin_unlock_irqrestore(&dev->event_lock, flags); + + complete(&omap_crtc->completion); } -static void apply_worker(struct work_struct *work) +int omap_crtc_flush(struct drm_crtc *crtc) { - struct omap_crtc *omap_crtc = - container_of(work, struct omap_crtc, apply_work); - struct drm_crtc *crtc = &omap_crtc->base; - struct drm_device *dev = crtc->dev; - struct omap_drm_apply *apply, *n; - bool need_apply; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct omap_framebuffer_unpin *fb, *next; - /* - * Synchronize everything on mode_config.mutex, to keep - * the callbacks and list modification all serialized - * with respect to modesetting ioctls from userspace. - */ - drm_modeset_lock(&crtc->mutex, NULL); - dispc_runtime_get(); + DBG("%s: GO", omap_crtc->name); - /* - * If we are still pending a previous update, wait.. when the - * pending update completes, we get kicked again. - */ - if (omap_crtc->apply_irq.registered) - goto out; - - /* finish up previous apply's: */ - list_for_each_entry_safe(apply, n, - &omap_crtc->pending_applies, pending_node) { - apply->post_apply(apply); - list_del(&apply->pending_node); - } + WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); + WARN_ON(omap_crtc->vblank_irq.registered); - need_apply = !list_empty(&omap_crtc->queued_applies); + dispc_runtime_get(); - /* then handle the next round of of queued apply's: */ - list_for_each_entry_safe(apply, n, - &omap_crtc->queued_applies, queued_node) { - apply->pre_apply(apply); - list_del(&apply->queued_node); - apply->queued = false; - list_add_tail(&apply->pending_node, - &omap_crtc->pending_applies); - } + if (dispc_mgr_is_enabled(omap_crtc->channel)) { + dispc_mgr_go(omap_crtc->channel); + omap_irq_register(crtc->dev, &omap_crtc->vblank_irq); - if (need_apply) { - enum omap_channel channel = omap_crtc->channel; + WARN_ON(!wait_for_completion_timeout(&omap_crtc->completion, + msecs_to_jiffies(100))); + reinit_completion(&omap_crtc->completion); + } - DBG("%s: GO", omap_crtc->name); + dispc_runtime_put(); - if (dispc_mgr_is_enabled(channel)) { - dispc_mgr_go(channel); - omap_irq_register(dev, &omap_crtc->apply_irq); - } else { - struct omap_drm_private *priv = dev->dev_private; - queue_work(priv->wq, &omap_crtc->apply_work); - } + /* Unpin and unreference pending framebuffers. */ + list_for_each_entry_safe(fb, next, &omap_crtc->pending_unpins, list) { + omap_framebuffer_unpin(fb->fb); + drm_framebuffer_unreference(fb->fb); + list_del(&fb->list); + kfree(fb); } -out: - dispc_runtime_put(); - drm_modeset_unlock(&crtc->mutex); + return 0; } -int omap_crtc_apply(struct drm_crtc *crtc, - struct omap_drm_apply *apply) +int omap_crtc_queue_unpin(struct drm_crtc *crtc, struct drm_framebuffer *fb) { struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct omap_framebuffer_unpin *unpin; - WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); - - /* no need to queue it again if it is already queued: */ - if (apply->queued) - return 0; - - apply->queued = true; - list_add_tail(&apply->queued_node, &omap_crtc->queued_applies); + unpin = kzalloc(sizeof(*unpin), GFP_KERNEL); + if (!unpin) + return -ENOMEM; - /* - * If there are no currently pending updates, then go ahead and - * kick the worker immediately, otherwise it will run again when - * the current update finishes. - */ - if (list_empty(&omap_crtc->pending_applies)) { - struct omap_drm_private *priv = crtc->dev->dev_private; - queue_work(priv->wq, &omap_crtc->apply_work); - } + unpin->fb = fb; + list_add_tail(&unpin->list, &omap_crtc->pending_unpins); return 0; } -static void omap_crtc_pre_apply(struct omap_drm_apply *apply) +static void omap_crtc_setup(struct drm_crtc *crtc) { - struct omap_crtc *omap_crtc = - container_of(apply, struct omap_crtc, apply); - struct drm_crtc *crtc = &omap_crtc->base; + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); struct omap_drm_private *priv = crtc->dev->dev_private; struct drm_encoder *encoder = NULL; unsigned int i; DBG("%s: enabled=%d", omap_crtc->name, omap_crtc->enabled); + dispc_runtime_get(); + for (i = 0; i < priv->num_encoders; i++) { if (priv->encoders[i]->crtc == crtc) { encoder = priv->encoders[i]; @@ -416,30 +387,8 @@ static void omap_crtc_pre_apply(struct omap_drm_apply *apply) omap_encoder_set_enabled(encoder, true); } } -} - -static void omap_crtc_post_apply(struct omap_drm_apply *apply) -{ - /* nothing needed for post-apply */ -} -void omap_crtc_flush(struct drm_crtc *crtc) -{ - struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - int loops = 0; - - while (!list_empty(&omap_crtc->pending_applies) || - !list_empty(&omap_crtc->queued_applies) || - omap_crtc->event || omap_crtc->old_fb) { - - if (++loops > 10) { - dev_err(crtc->dev->dev, - "omap_crtc_flush() timeout\n"); - break; - } - - schedule_timeout_uninterruptible(msecs_to_jiffies(20)); - } + dispc_runtime_put(); } /* ----------------------------------------------------------------------------- @@ -452,7 +401,7 @@ static void omap_crtc_destroy(struct drm_crtc *crtc) DBG("%s", omap_crtc->name); - WARN_ON(omap_crtc->apply_irq.registered); + WARN_ON(omap_crtc->vblank_irq.registered); omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); drm_crtc_cleanup(crtc); @@ -469,17 +418,21 @@ static void omap_crtc_dpms(struct drm_crtc *crtc, int mode) DBG("%s: %d", omap_crtc->name, mode); - if (enabled != omap_crtc->enabled) { - omap_crtc->enabled = enabled; - omap_crtc_apply(crtc, &omap_crtc->apply); + if (enabled == omap_crtc->enabled) + return; - /* Enable/disable all planes associated with the CRTC. */ - for (i = 0; i < priv->num_planes; i++) { - struct drm_plane *plane = priv->planes[i]; - if (plane->crtc == crtc) - WARN_ON(omap_plane_set_enable(plane, enabled)); - } + /* Enable/disable all planes associated with the CRTC. */ + for (i = 0; i < priv->num_planes; i++) { + struct drm_plane *plane = priv->planes[i]; + + if (plane->crtc == crtc) + WARN_ON(omap_plane_set_enable(plane, enabled)); } + + omap_crtc->enabled = enabled; + + omap_crtc_setup(crtc); + omap_crtc_flush(crtc); } static bool omap_crtc_mode_fixup(struct drm_crtc *crtc, @@ -518,8 +471,7 @@ static int omap_crtc_mode_set(struct drm_crtc *crtc, return omap_plane_mode_set(crtc->primary, crtc, crtc->primary->fb, 0, 0, mode->hdisplay, mode->vdisplay, - x, y, mode->hdisplay, mode->vdisplay, - NULL, NULL); + x, y, mode->hdisplay, mode->vdisplay); } static void omap_crtc_prepare(struct drm_crtc *crtc) @@ -541,36 +493,15 @@ static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, { struct drm_plane *plane = crtc->primary; struct drm_display_mode *mode = &crtc->mode; + int ret; - return omap_plane_mode_set(plane, crtc, crtc->primary->fb, - 0, 0, mode->hdisplay, mode->vdisplay, - x, y, mode->hdisplay, mode->vdisplay, - NULL, NULL); -} - -static void vblank_cb(void *arg) -{ - struct drm_crtc *crtc = arg; - struct drm_device *dev = crtc->dev; - struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - unsigned long flags; - struct drm_framebuffer *fb; - - spin_lock_irqsave(&dev->event_lock, flags); - - /* wakeup userspace */ - if (omap_crtc->event) - drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event); - - fb = omap_crtc->old_fb; - - omap_crtc->event = NULL; - omap_crtc->old_fb = NULL; - - spin_unlock_irqrestore(&dev->event_lock, flags); + ret = omap_plane_mode_set(plane, crtc, crtc->primary->fb, + 0, 0, mode->hdisplay, mode->vdisplay, + x, y, mode->hdisplay, mode->vdisplay); + if (ret < 0) + return ret; - if (fb) - drm_framebuffer_unreference(fb); + return omap_crtc_flush(crtc); } static void page_flip_worker(struct work_struct *work) @@ -584,12 +515,13 @@ static void page_flip_worker(struct work_struct *work) drm_modeset_lock(&crtc->mutex, NULL); omap_plane_mode_set(crtc->primary, crtc, crtc->primary->fb, 0, 0, mode->hdisplay, mode->vdisplay, - crtc->x, crtc->y, mode->hdisplay, mode->vdisplay, - vblank_cb, crtc); + crtc->x, crtc->y, mode->hdisplay, mode->vdisplay); + omap_crtc_flush(crtc); drm_modeset_unlock(&crtc->mutex); bo = omap_framebuffer_bo(crtc->primary->fb, 0); drm_gem_object_unreference_unlocked(bo); + drm_framebuffer_unreference(crtc->primary->fb); } static void page_flip_cb(void *arg) @@ -709,20 +641,17 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, crtc = &omap_crtc->base; INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker); - INIT_WORK(&omap_crtc->apply_work, apply_worker); - INIT_LIST_HEAD(&omap_crtc->pending_applies); - INIT_LIST_HEAD(&omap_crtc->queued_applies); + INIT_LIST_HEAD(&omap_crtc->pending_unpins); - omap_crtc->apply.pre_apply = omap_crtc_pre_apply; - omap_crtc->apply.post_apply = omap_crtc_post_apply; + init_completion(&omap_crtc->completion); omap_crtc->channel = channel; omap_crtc->name = channel_names[channel]; omap_crtc->pipe = id; - omap_crtc->apply_irq.irqmask = pipe2vbl(crtc); - omap_crtc->apply_irq.irq = omap_crtc_apply_irq; + omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc); + omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq; omap_crtc->error_irq.irqmask = dispc_mgr_get_sync_lost_irq(channel); diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index ce6a255d277a..bf02121d9ce8 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -550,7 +550,6 @@ static int dev_load(struct drm_device *dev, unsigned long flags) static int dev_unload(struct drm_device *dev) { struct omap_drm_private *priv = dev->dev_private; - int i; DBG("unload: dev=%p", dev); @@ -559,10 +558,6 @@ static int dev_unload(struct drm_device *dev) if (priv->fbdev) omap_fbdev_free(dev); - /* flush crtcs so the fbs get released */ - for (i = 0; i < priv->num_crtcs; i++) - omap_crtc_flush(priv->crtcs[i]); - omap_modeset_free(dev); omap_gem_deinit(dev); diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index a42a11c62106..6c0cb463b9dc 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h @@ -50,21 +50,6 @@ struct omap_drm_window { uint32_t src_w, src_h; }; -/* Once GO bit is set, we can't make further updates to shadowed registers - * until the GO bit is cleared. So various parts in the kms code that need - * to update shadowed registers queue up a pair of callbacks, pre_apply - * which is called before setting GO bit, and post_apply that is called - * after GO bit is cleared. The crtc manages the queuing, and everyone - * else goes thru omap_crtc_apply() using these callbacks so that the - * code which has to deal w/ GO bit state is centralized. - */ -struct omap_drm_apply { - struct list_head pending_node, queued_node; - bool queued; - void (*pre_apply)(struct omap_drm_apply *apply); - void (*post_apply)(struct omap_drm_apply *apply); -}; - /* For transiently registering for different DSS irqs that various parts * of the KMS code need during setup/configuration. We these are not * necessarily the same as what drm_vblank_get/put() are requesting, and @@ -153,13 +138,12 @@ void omap_fbdev_free(struct drm_device *dev); const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc); enum omap_channel omap_crtc_channel(struct drm_crtc *crtc); -int omap_crtc_apply(struct drm_crtc *crtc, - struct omap_drm_apply *apply); +int omap_crtc_flush(struct drm_crtc *crtc); +int omap_crtc_queue_unpin(struct drm_crtc *crtc, struct drm_framebuffer *fb); void omap_crtc_pre_init(void); void omap_crtc_pre_uninit(void); struct drm_crtc *omap_crtc_init(struct drm_device *dev, struct drm_plane *plane, enum omap_channel channel, int id); -void omap_crtc_flush(struct drm_crtc *crtc); struct drm_plane *omap_plane_init(struct drm_device *dev, int id, enum drm_plane_type type); @@ -169,8 +153,7 @@ int omap_plane_mode_set(struct drm_plane *plane, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, unsigned int src_x, unsigned int src_y, - unsigned int src_w, unsigned int src_h, - void (*fxn)(void *), void *arg); + unsigned int src_w, unsigned int src_h); void omap_plane_install_properties(struct drm_plane *plane, struct drm_mode_object *obj); int omap_plane_set_property(struct drm_plane *plane, diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index a1c9c08db345..99663ec011b7 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -17,8 +17,6 @@ * this program. If not, see . */ -#include "drm_flip_work.h" - #include "omap_drv.h" #include "omap_dmm_tiler.h" @@ -32,11 +30,6 @@ * plane funcs */ -struct callback { - void (*fxn)(void *); - void *arg; -}; - #define to_omap_plane(x) container_of(x, struct omap_plane, base) struct omap_plane { @@ -44,7 +37,6 @@ struct omap_plane { int id; /* TODO rename omap_plane -> omap_plane_id in omapdss so I can use the enum */ const char *name; struct omap_overlay_info info; - struct omap_drm_apply apply; /* position/orientation of scanout within the fb: */ struct omap_drm_window win; @@ -57,91 +49,66 @@ struct omap_plane { uint32_t formats[32]; struct omap_drm_irq error_irq; - - /* for deferring bo unpin's until next post_apply(): */ - struct drm_flip_work unpin_work; - - // XXX maybe get rid of this and handle vblank in crtc too? - struct callback apply_done_cb; }; -static void omap_plane_unpin_worker(struct drm_flip_work *work, void *val) -{ - struct omap_plane *omap_plane = - container_of(work, struct omap_plane, unpin_work); - struct drm_device *dev = omap_plane->base.dev; - - /* - * omap_framebuffer_pin/unpin are always called from priv->wq, - * so there's no need for locking here. - */ - omap_framebuffer_unpin(val); - mutex_lock(&dev->mode_config.mutex); - drm_framebuffer_unreference(val); - mutex_unlock(&dev->mode_config.mutex); -} - /* update which fb (if any) is pinned for scanout */ -static int omap_plane_update_pin(struct drm_plane *plane, - struct drm_framebuffer *fb) +static int omap_plane_update_pin(struct drm_plane *plane) { struct omap_plane *omap_plane = to_omap_plane(plane); struct drm_framebuffer *pinned_fb = omap_plane->pinned_fb; + struct drm_framebuffer *fb = omap_plane->enabled ? plane->fb : NULL; + int ret = 0; - if (pinned_fb != fb) { - int ret = 0; - - DBG("%p -> %p", pinned_fb, fb); + if (pinned_fb == fb) + return 0; - if (fb) { - drm_framebuffer_reference(fb); - ret = omap_framebuffer_pin(fb); - } + DBG("%p -> %p", pinned_fb, fb); - if (pinned_fb) - drm_flip_work_queue(&omap_plane->unpin_work, pinned_fb); + if (fb) { + drm_framebuffer_reference(fb); + ret = omap_framebuffer_pin(fb); + } - if (ret) { - dev_err(plane->dev->dev, "could not swap %p -> %p\n", - omap_plane->pinned_fb, fb); - drm_framebuffer_unreference(fb); - omap_plane->pinned_fb = NULL; - return ret; - } + if (pinned_fb) + omap_crtc_queue_unpin(plane->crtc, pinned_fb); - omap_plane->pinned_fb = fb; + if (ret) { + dev_err(plane->dev->dev, "could not swap %p -> %p\n", + omap_plane->pinned_fb, fb); + drm_framebuffer_unreference(fb); + omap_plane->pinned_fb = NULL; + return ret; } + omap_plane->pinned_fb = fb; + return 0; } -static void omap_plane_pre_apply(struct omap_drm_apply *apply) +static int omap_plane_setup(struct omap_plane *omap_plane) { - struct omap_plane *omap_plane = - container_of(apply, struct omap_plane, apply); - struct omap_drm_window *win = &omap_plane->win; + struct omap_overlay_info *info = &omap_plane->info; struct drm_plane *plane = &omap_plane->base; struct drm_device *dev = plane->dev; - struct omap_overlay_info *info = &omap_plane->info; struct drm_crtc *crtc = plane->crtc; - enum omap_channel channel; - bool enabled = omap_plane->enabled && crtc; int ret; - DBG("%s, enabled=%d", omap_plane->name, enabled); + DBG("%s, enabled=%d", omap_plane->name, omap_plane->enabled); /* if fb has changed, pin new fb: */ - omap_plane_update_pin(plane, enabled ? plane->fb : NULL); + ret = omap_plane_update_pin(plane); + if (ret) + return ret; + + dispc_runtime_get(); - if (!enabled) { + if (!omap_plane->enabled) { dispc_ovl_enable(omap_plane->id, false); - return; + goto done; } - channel = omap_crtc_channel(crtc); - /* update scanout: */ - omap_framebuffer_update_scanout(plane->fb, win, info); + omap_framebuffer_update_scanout(plane->fb, &omap_plane->win, info); DBG("%dx%d -> %dx%d (%d)", info->width, info->height, info->out_width, info->out_height, @@ -149,43 +116,22 @@ static void omap_plane_pre_apply(struct omap_drm_apply *apply) DBG("%d,%d %pad %pad", info->pos_x, info->pos_y, &info->paddr, &info->p_uv_addr); - dispc_ovl_set_channel_out(omap_plane->id, channel); + dispc_ovl_set_channel_out(omap_plane->id, + omap_crtc_channel(crtc)); /* and finally, update omapdss: */ ret = dispc_ovl_setup(omap_plane->id, info, false, omap_crtc_timings(crtc), false); if (ret) { dev_err(dev->dev, "dispc_ovl_setup failed: %d\n", ret); - return; + goto done; } dispc_ovl_enable(omap_plane->id, true); -} - -static void omap_plane_post_apply(struct omap_drm_apply *apply) -{ - struct omap_plane *omap_plane = - container_of(apply, struct omap_plane, apply); - struct drm_plane *plane = &omap_plane->base; - struct omap_drm_private *priv = plane->dev->dev_private; - struct callback cb; - - cb = omap_plane->apply_done_cb; - omap_plane->apply_done_cb.fxn = NULL; - - drm_flip_work_commit(&omap_plane->unpin_work, priv->wq); - - if (cb.fxn) - cb.fxn(cb.arg); -} -static int omap_plane_apply(struct drm_plane *plane) -{ - if (plane->crtc) { - struct omap_plane *omap_plane = to_omap_plane(plane); - return omap_crtc_apply(plane->crtc, &omap_plane->apply); - } - return 0; +done: + dispc_runtime_put(); + return ret; } int omap_plane_mode_set(struct drm_plane *plane, @@ -193,8 +139,7 @@ int omap_plane_mode_set(struct drm_plane *plane, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, unsigned int src_x, unsigned int src_y, - unsigned int src_w, unsigned int src_h, - void (*fxn)(void *), void *arg) + unsigned int src_w, unsigned int src_h) { struct omap_plane *omap_plane = to_omap_plane(plane); struct omap_drm_window *win = &omap_plane->win; @@ -209,17 +154,18 @@ int omap_plane_mode_set(struct drm_plane *plane, win->src_w = src_w; win->src_h = src_h; - if (fxn) { - /* omap_crtc should ensure that a new page flip - * isn't permitted while there is one pending: - */ - BUG_ON(omap_plane->apply_done_cb.fxn); + return omap_plane_setup(omap_plane); +} - omap_plane->apply_done_cb.fxn = fxn; - omap_plane->apply_done_cb.arg = arg; - } +int omap_plane_set_enable(struct drm_plane *plane, bool enable) +{ + struct omap_plane *omap_plane = to_omap_plane(plane); - return omap_plane_apply(plane); + if (enable == omap_plane->enabled) + return 0; + + omap_plane->enabled = enable; + return omap_plane_setup(omap_plane); } static int omap_plane_update(struct drm_plane *plane, @@ -230,6 +176,8 @@ static int omap_plane_update(struct drm_plane *plane, uint32_t src_w, uint32_t src_h) { struct omap_plane *omap_plane = to_omap_plane(plane); + int ret; + omap_plane->enabled = true; /* omap_plane_mode_set() takes adjusted src */ @@ -248,10 +196,14 @@ static int omap_plane_update(struct drm_plane *plane, plane->crtc = crtc; /* src values are in Q16 fixed point, convert to integer: */ - return omap_plane_mode_set(plane, crtc, fb, - crtc_x, crtc_y, crtc_w, crtc_h, - src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16, - NULL, NULL); + ret = omap_plane_mode_set(plane, crtc, fb, + crtc_x, crtc_y, crtc_w, crtc_h, + src_x >> 16, src_y >> 16, + src_w >> 16, src_h >> 16); + if (ret < 0) + return ret; + + return omap_crtc_flush(plane->crtc); } static int omap_plane_disable(struct drm_plane *plane) @@ -262,7 +214,14 @@ static int omap_plane_disable(struct drm_plane *plane) omap_plane->info.zorder = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : omap_plane->id; - return omap_plane_set_enable(plane, false); + if (!omap_plane->enabled) + return 0; + + /* Disabling a plane never fails. */ + omap_plane->enabled = false; + omap_plane_setup(omap_plane); + + return omap_crtc_flush(plane->crtc); } static void omap_plane_destroy(struct drm_plane *plane) @@ -275,22 +234,9 @@ static void omap_plane_destroy(struct drm_plane *plane) drm_plane_cleanup(plane); - drm_flip_work_cleanup(&omap_plane->unpin_work); - kfree(omap_plane); } -int omap_plane_set_enable(struct drm_plane *plane, bool enable) -{ - struct omap_plane *omap_plane = to_omap_plane(plane); - - if (enable == omap_plane->enabled) - return 0; - - omap_plane->enabled = enable; - return omap_plane_apply(plane); -} - /* helper to install properties which are common to planes and crtcs */ void omap_plane_install_properties(struct drm_plane *plane, struct drm_mode_object *obj) @@ -312,19 +258,30 @@ int omap_plane_set_property(struct drm_plane *plane, { struct omap_plane *omap_plane = to_omap_plane(plane); struct omap_drm_private *priv = plane->dev->dev_private; - int ret = -EINVAL; + int ret; if (property == plane->dev->mode_config.rotation_property) { DBG("%s: rotation: %02x", omap_plane->name, (uint32_t)val); omap_plane->win.rotation = val; - ret = omap_plane_apply(plane); } else if (property == priv->zorder_prop) { DBG("%s: zorder: %02x", omap_plane->name, (uint32_t)val); omap_plane->info.zorder = val; - ret = omap_plane_apply(plane); + } else { + return -EINVAL; } - return ret; + /* + * We're done if the plane is disabled, properties will be applied the + * next time it becomes enabled. + */ + if (!omap_plane->enabled) + return 0; + + ret = omap_plane_setup(omap_plane); + if (ret < 0) + return ret; + + return omap_crtc_flush(plane->crtc); } static const struct drm_plane_funcs omap_plane_funcs = { @@ -372,9 +329,6 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, if (!omap_plane) return ERR_PTR(-ENOMEM); - drm_flip_work_init(&omap_plane->unpin_work, - "unpin", omap_plane_unpin_worker); - omap_plane->nformats = omap_framebuffer_get_formats( omap_plane->formats, ARRAY_SIZE(omap_plane->formats), dss_feat_get_supported_color_modes(id)); @@ -383,9 +337,6 @@ struct drm_plane *omap_plane_init(struct drm_device *dev, plane = &omap_plane->base; - omap_plane->apply.pre_apply = omap_plane_pre_apply; - omap_plane->apply.post_apply = omap_plane_post_apply; - omap_plane->error_irq.irqmask = error_irqs[id]; omap_plane->error_irq.irq = omap_plane_error_irq; omap_irq_register(dev, &omap_plane->error_irq); -- cgit v1.2.3 From 077db4da28e247942f6cafcf36796440f871d0a5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 18 Jan 2015 16:36:19 +0200 Subject: drm: omapdrm: Rename omap_crtc_page_flip_locked to omap_crtc_page_flip The operation is called page_flip, rename its implementation accordingly. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_crtc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index e5fb8c6e25e6..7ef9147bde73 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -534,10 +534,10 @@ static void page_flip_cb(void *arg) queue_work(priv->wq, &omap_crtc->page_flip_work); } -static int omap_crtc_page_flip_locked(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_pending_vblank_event *event, - uint32_t page_flip_flags) +static int omap_crtc_page_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t page_flip_flags) { struct drm_device *dev = crtc->dev; struct omap_crtc *omap_crtc = to_omap_crtc(crtc); @@ -589,7 +589,7 @@ static int omap_crtc_set_property(struct drm_crtc *crtc, static const struct drm_crtc_funcs omap_crtc_funcs = { .set_config = drm_crtc_helper_set_config, .destroy = omap_crtc_destroy, - .page_flip = omap_crtc_page_flip_locked, + .page_flip = omap_crtc_page_flip, .set_property = omap_crtc_set_property, }; -- cgit v1.2.3 From 42fb61cc687822855bc140147a3ba044f23d023e Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 26 Jan 2015 02:58:51 +0200 Subject: drm: omapdrm: Rename omap_crtc page flip-related fields The old_fb field is only used to indicate whether a page flip is pending. Turn it into a bool named flip_pending. Rename event and page_flip_work to flip_event and flip_work for consistency. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_crtc.c | 47 ++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 7ef9147bde73..85129d56cf4c 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -54,19 +54,22 @@ struct omap_crtc { /* list of framebuffers to unpin */ struct list_head pending_unpins; - /* if there is a pending flip, these will be non-null: */ - struct drm_pending_vblank_event *event; - struct drm_framebuffer *old_fb; + /* + * The flip_pending flag indicates if a page flip has been queued and + * hasn't completed yet. The flip event, if any, is stored in + * flip_event. + * + * The flip_work work queue handles page flip requests without caring + * about what context the GEM async callback is called from. Possibly we + * should just make omap_gem always call the cb from the worker so we + * don't have to care about this. + */ + bool flip_pending; + struct drm_pending_vblank_event *flip_event; + struct work_struct flip_work; struct completion completion; - /* for handling page flips without caring about what - * the callback is called from. Possibly we should just - * make omap_gem always call the cb from the worker so - * we don't have to care about this.. - */ - struct work_struct page_flip_work; - bool ignore_digit_sync_lost; }; @@ -293,11 +296,12 @@ static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus) spin_lock_irqsave(&dev->event_lock, flags); /* wakeup userspace */ - if (omap_crtc->event) - drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event); + if (omap_crtc->flip_event) + drm_send_vblank_event(dev, omap_crtc->pipe, + omap_crtc->flip_event); - omap_crtc->event = NULL; - omap_crtc->old_fb = NULL; + omap_crtc->flip_event = NULL; + omap_crtc->flip_pending = false; spin_unlock_irqrestore(&dev->event_lock, flags); @@ -507,7 +511,7 @@ static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, static void page_flip_worker(struct work_struct *work) { struct omap_crtc *omap_crtc = - container_of(work, struct omap_crtc, page_flip_work); + container_of(work, struct omap_crtc, flip_work); struct drm_crtc *crtc = &omap_crtc->base; struct drm_display_mode *mode = &crtc->mode; struct drm_gem_object *bo; @@ -531,7 +535,7 @@ static void page_flip_cb(void *arg) struct omap_drm_private *priv = crtc->dev->dev_private; /* avoid assumptions about what ctxt we are called from: */ - queue_work(priv->wq, &omap_crtc->page_flip_work); + queue_work(priv->wq, &omap_crtc->flip_work); } static int omap_crtc_page_flip(struct drm_crtc *crtc, @@ -550,15 +554,16 @@ static int omap_crtc_page_flip(struct drm_crtc *crtc, spin_lock_irqsave(&dev->event_lock, flags); - if (omap_crtc->old_fb) { + if (omap_crtc->flip_pending) { spin_unlock_irqrestore(&dev->event_lock, flags); dev_err(dev->dev, "already a pending flip\n"); return -EBUSY; } - omap_crtc->event = event; - omap_crtc->old_fb = primary->fb = fb; - drm_framebuffer_reference(omap_crtc->old_fb); + omap_crtc->flip_event = event; + omap_crtc->flip_pending = true; + primary->fb = fb; + drm_framebuffer_reference(fb); spin_unlock_irqrestore(&dev->event_lock, flags); @@ -640,7 +645,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, crtc = &omap_crtc->base; - INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker); + INIT_WORK(&omap_crtc->flip_work, page_flip_worker); INIT_LIST_HEAD(&omap_crtc->pending_unpins); -- cgit v1.2.3 From f13ab00567273c70ffbecb59e8f11491cc108bbd Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 25 Jan 2015 22:06:45 +0200 Subject: drm: omapdrm: Simplify IRQ registration The omapdrm can't use drm_irq_install() and drm_irq_uninstall() as it delegates IRQ handling to the omapdss driver. However, the code still declares IRQ-related operations used by the DRM IRQ helpers, and calls them indirectly. Simplify the implementation by calling the functions directly or inlining them. The irq_enabled checks can then also be simplified as the call stacks guarantees that omap_drm_irq_install() and omap_drm_irq_uninstall() will never run concurrently. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_drv.c | 7 +-- drivers/gpu/drm/omapdrm/omap_drv.h | 6 +-- drivers/gpu/drm/omapdrm/omap_irq.c | 102 +++++++++---------------------------- 3 files changed, 25 insertions(+), 90 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index bf02121d9ce8..47fb99b3a375 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -656,8 +656,7 @@ static const struct file_operations omapdriver_fops = { }; static struct drm_driver omap_drm_driver = { - .driver_features = DRIVER_HAVE_IRQ | DRIVER_MODESET | DRIVER_GEM - | DRIVER_PRIME, + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME, .load = dev_load, .unload = dev_unload, .open = dev_open, @@ -668,10 +667,6 @@ static struct drm_driver omap_drm_driver = { .get_vblank_counter = drm_vblank_count, .enable_vblank = omap_irq_enable_vblank, .disable_vblank = omap_irq_disable_vblank, - .irq_preinstall = omap_irq_preinstall, - .irq_postinstall = omap_irq_postinstall, - .irq_uninstall = omap_irq_uninstall, - .irq_handler = omap_irq_handler, #ifdef CONFIG_DEBUG_FS .debugfs_init = omap_debugfs_init, .debugfs_cleanup = omap_debugfs_cleanup, diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index 6c0cb463b9dc..f1005b46a193 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h @@ -122,15 +122,11 @@ int omap_gem_resume(struct device *dev); int omap_irq_enable_vblank(struct drm_device *dev, int crtc_id); void omap_irq_disable_vblank(struct drm_device *dev, int crtc_id); -irqreturn_t omap_irq_handler(int irq, void *arg); -void omap_irq_preinstall(struct drm_device *dev); -int omap_irq_postinstall(struct drm_device *dev); -void omap_irq_uninstall(struct drm_device *dev); void __omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq); void __omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq); void omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq); void omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq); -int omap_drm_irq_uninstall(struct drm_device *dev); +void omap_drm_irq_uninstall(struct drm_device *dev); int omap_drm_irq_install(struct drm_device *dev); struct drm_fb_helper *omap_fbdev_init(struct drm_device *dev); diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c index 3eb097efc488..803aff0db768 100644 --- a/drivers/gpu/drm/omapdrm/omap_irq.c +++ b/drivers/gpu/drm/omapdrm/omap_irq.c @@ -187,7 +187,7 @@ void omap_irq_disable_vblank(struct drm_device *dev, int crtc_id) dispc_runtime_put(); } -irqreturn_t omap_irq_handler(int irq, void *arg) +static irqreturn_t omap_irq_handler(int irq, void *arg) { struct drm_device *dev = (struct drm_device *) arg; struct omap_drm_private *priv = dev->dev_private; @@ -222,23 +222,29 @@ irqreturn_t omap_irq_handler(int irq, void *arg) return IRQ_HANDLED; } -void omap_irq_preinstall(struct drm_device *dev) -{ - DBG("dev=%p", dev); - dispc_runtime_get(); - dispc_clear_irqstatus(0xffffffff); - dispc_runtime_put(); -} +/* + * We need a special version, instead of just using drm_irq_install(), + * because we need to register the irq via omapdss. Once omapdss and + * omapdrm are merged together we can assign the dispc hwmod data to + * ourselves and drop these and just use drm_irq_{install,uninstall}() + */ -int omap_irq_postinstall(struct drm_device *dev) +int omap_drm_irq_install(struct drm_device *dev) { struct omap_drm_private *priv = dev->dev_private; struct omap_drm_irq *error_handler = &priv->error_handler; - - DBG("dev=%p", dev); + int ret; INIT_LIST_HEAD(&priv->irq_list); + dispc_runtime_get(); + dispc_clear_irqstatus(0xffffffff); + dispc_runtime_put(); + + ret = dispc_request_irq(omap_irq_handler, dev); + if (ret < 0) + return ret; + error_handler->irq = omap_irq_error_handler; error_handler->irqmask = DISPC_IRQ_OCP_ERR; @@ -249,76 +255,22 @@ int omap_irq_postinstall(struct drm_device *dev) omap_irq_register(dev, error_handler); - return 0; -} - -void omap_irq_uninstall(struct drm_device *dev) -{ - DBG("dev=%p", dev); - // TODO prolly need to call drm_irq_uninstall() somewhere too -} - -/* - * We need a special version, instead of just using drm_irq_install(), - * because we need to register the irq via omapdss. Once omapdss and - * omapdrm are merged together we can assign the dispc hwmod data to - * ourselves and drop these and just use drm_irq_{install,uninstall}() - */ - -int omap_drm_irq_install(struct drm_device *dev) -{ - int ret; - - mutex_lock(&dev->struct_mutex); - - if (dev->irq_enabled) { - mutex_unlock(&dev->struct_mutex); - return -EBUSY; - } dev->irq_enabled = true; - mutex_unlock(&dev->struct_mutex); - - /* Before installing handler */ - if (dev->driver->irq_preinstall) - dev->driver->irq_preinstall(dev); - - ret = dispc_request_irq(dev->driver->irq_handler, dev); - if (ret < 0) { - mutex_lock(&dev->struct_mutex); - dev->irq_enabled = false; - mutex_unlock(&dev->struct_mutex); - return ret; - } - - /* After installing handler */ - if (dev->driver->irq_postinstall) - ret = dev->driver->irq_postinstall(dev); - - if (ret < 0) { - mutex_lock(&dev->struct_mutex); - dev->irq_enabled = false; - mutex_unlock(&dev->struct_mutex); - dispc_free_irq(dev); - } - - return ret; + return 0; } -int omap_drm_irq_uninstall(struct drm_device *dev) +void omap_drm_irq_uninstall(struct drm_device *dev) { unsigned long irqflags; - bool irq_enabled; int i; - mutex_lock(&dev->struct_mutex); - irq_enabled = dev->irq_enabled; + if (!dev->irq_enabled) + return; + dev->irq_enabled = false; - mutex_unlock(&dev->struct_mutex); - /* - * Wake up any waiters so they don't hang. - */ + /* Wake up any waiters so they don't hang. */ if (dev->num_crtcs) { spin_lock_irqsave(&dev->vbl_lock, irqflags); for (i = 0; i < dev->num_crtcs; i++) { @@ -330,13 +282,5 @@ int omap_drm_irq_uninstall(struct drm_device *dev) spin_unlock_irqrestore(&dev->vbl_lock, irqflags); } - if (!irq_enabled) - return -EINVAL; - - if (dev->driver->irq_uninstall) - dev->driver->irq_uninstall(dev); - dispc_free_irq(dev); - - return 0; } -- cgit v1.2.3 From 1d5e5ea1f6061ec9ad4f43928697f479aeb884c6 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 18 Jan 2015 16:57:36 +0200 Subject: drm: omapdrm: Cancel pending page flips when closing device Pending page flips must be cancelled when closing the device, otherwise their completion at next vblank will result in nasty effects, including possible oopses due to resources required to complete the page flip being freed. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_crtc.c | 21 ++++++++++++++++++++- drivers/gpu/drm/omapdrm/omap_drv.c | 6 ++++++ drivers/gpu/drm/omapdrm/omap_drv.h | 1 + 3 files changed, 27 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 85129d56cf4c..a60f4e49b55f 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -263,9 +263,28 @@ static const struct dss_mgr_ops mgr_ops = { }; /* ----------------------------------------------------------------------------- - * Setup and Flush + * Setup, Flush and Page Flip */ +void omap_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) +{ + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct drm_device *dev = crtc->dev; + unsigned long flags; + + spin_lock_irqsave(&dev->event_lock, flags); + + /* Only complete events queued for our file handle. */ + if (omap_crtc->flip_event && + file == omap_crtc->flip_event->base.file_priv) { + drm_send_vblank_event(dev, omap_crtc->pipe, + omap_crtc->flip_event); + omap_crtc->flip_event = NULL; + } + + spin_unlock_irqrestore(&dev->event_lock, flags); +} + static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) { struct omap_crtc *omap_crtc = diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index 47fb99b3a375..cf1b37e5374b 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -630,7 +630,13 @@ static void dev_lastclose(struct drm_device *dev) static void dev_preclose(struct drm_device *dev, struct drm_file *file) { + struct omap_drm_private *priv = dev->dev_private; + unsigned int i; + DBG("preclose: dev=%p", dev); + + for (i = 0; i < priv->num_crtcs; ++i) + omap_crtc_cancel_page_flip(priv->crtcs[i], file); } static void dev_postclose(struct drm_device *dev, struct drm_file *file) diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index f1005b46a193..774b9f6ab2d6 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h @@ -136,6 +136,7 @@ const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc); enum omap_channel omap_crtc_channel(struct drm_crtc *crtc); int omap_crtc_flush(struct drm_crtc *crtc); int omap_crtc_queue_unpin(struct drm_crtc *crtc, struct drm_framebuffer *fb); +void omap_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file); void omap_crtc_pre_init(void); void omap_crtc_pre_uninit(void); struct drm_crtc *omap_crtc_init(struct drm_device *dev, -- cgit v1.2.3 From 15d02e921c3e9859d4ffb5308013b5e67cd70749 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 25 Jan 2015 22:42:30 +0200 Subject: drm: omapdrm: Rework page flip handling To implement proper vblank control the driver will need to wait for page flip completion before disabling the vblank interrupt. This is made complex by the page flip implementation which queues and submits page flips to the hardware in two separate steps between which DRM locks are released. We thus need to avoid waiting on a page flip that has been queued but not submitted as submission and wait are covered by the same lock. Rework page flip handling as a first step by splitting the flip_pending boolean variable into an enumerated state and moving between states based on flip queue, submission and completion. The CANCELLED state will be used in a second step. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_crtc.c | 84 ++++++++++++++++++++++++++++--------- 1 file changed, 64 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index a60f4e49b55f..c086f72e488d 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -28,6 +28,13 @@ #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) +enum omap_page_flip_state { + OMAP_PAGE_FLIP_IDLE, + OMAP_PAGE_FLIP_WAIT, + OMAP_PAGE_FLIP_QUEUED, + OMAP_PAGE_FLIP_CANCELLED, +}; + struct omap_crtc { struct drm_crtc base; @@ -55,16 +62,19 @@ struct omap_crtc { struct list_head pending_unpins; /* - * The flip_pending flag indicates if a page flip has been queued and - * hasn't completed yet. The flip event, if any, is stored in - * flip_event. + * flip_state flag indicates the current page flap state: IDLE if no + * page queue has been submitted, WAIT when waiting for GEM async + * completion, QUEUED when the page flip has been queued to the hardware + * or CANCELLED when the CRTC is turned off before the flip gets queued + * to the hardware. The flip event, if any, is stored in flip_event. The + * flip_wait wait queue is used to wait for page flip completion. * * The flip_work work queue handles page flip requests without caring * about what context the GEM async callback is called from. Possibly we * should just make omap_gem always call the cb from the worker so we * don't have to care about this. */ - bool flip_pending; + enum omap_page_flip_state flip_state; struct drm_pending_vblank_event *flip_event; struct work_struct flip_work; @@ -285,6 +295,22 @@ void omap_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) spin_unlock_irqrestore(&dev->event_lock, flags); } +/* Must be called with dev->event_lock locked. */ +static void omap_crtc_complete_page_flip(struct drm_crtc *crtc, + enum omap_page_flip_state state) +{ + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct drm_device *dev = crtc->dev; + + if (omap_crtc->flip_event) { + drm_send_vblank_event(dev, omap_crtc->pipe, + omap_crtc->flip_event); + omap_crtc->flip_event = NULL; + } + + omap_crtc->flip_state = state; +} + static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) { struct omap_crtc *omap_crtc = @@ -312,16 +338,9 @@ static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus) DBG("%s: apply done", omap_crtc->name); __omap_irq_unregister(dev, &omap_crtc->vblank_irq); - spin_lock_irqsave(&dev->event_lock, flags); - /* wakeup userspace */ - if (omap_crtc->flip_event) - drm_send_vblank_event(dev, omap_crtc->pipe, - omap_crtc->flip_event); - - omap_crtc->flip_event = NULL; - omap_crtc->flip_pending = false; - + spin_lock_irqsave(&dev->event_lock, flags); + omap_crtc_complete_page_flip(&omap_crtc->base, OMAP_PAGE_FLIP_IDLE); spin_unlock_irqrestore(&dev->event_lock, flags); complete(&omap_crtc->completion); @@ -533,16 +552,41 @@ static void page_flip_worker(struct work_struct *work) container_of(work, struct omap_crtc, flip_work); struct drm_crtc *crtc = &omap_crtc->base; struct drm_display_mode *mode = &crtc->mode; + struct drm_device *dev = crtc->dev; + struct drm_framebuffer *fb; struct drm_gem_object *bo; + unsigned long flags; + bool queue_flip; drm_modeset_lock(&crtc->mutex, NULL); - omap_plane_mode_set(crtc->primary, crtc, crtc->primary->fb, - 0, 0, mode->hdisplay, mode->vdisplay, - crtc->x, crtc->y, mode->hdisplay, mode->vdisplay); - omap_crtc_flush(crtc); + + spin_lock_irqsave(&dev->event_lock, flags); + /* + * The page flip could have been cancelled while waiting for the GEM + * async operation to complete. Don't queue the flip in that case. + */ + if (omap_crtc->flip_state == OMAP_PAGE_FLIP_WAIT) { + omap_crtc->flip_state = OMAP_PAGE_FLIP_QUEUED; + queue_flip = true; + } else { + omap_crtc->flip_state = OMAP_PAGE_FLIP_IDLE; + queue_flip = false; + } + spin_unlock_irqrestore(&dev->event_lock, flags); + + fb = crtc->primary->fb; + + if (queue_flip) { + omap_plane_mode_set(crtc->primary, crtc, fb, + 0, 0, mode->hdisplay, mode->vdisplay, + crtc->x, crtc->y, mode->hdisplay, + mode->vdisplay); + omap_crtc_flush(crtc); + } + drm_modeset_unlock(&crtc->mutex); - bo = omap_framebuffer_bo(crtc->primary->fb, 0); + bo = omap_framebuffer_bo(fb, 0); drm_gem_object_unreference_unlocked(bo); drm_framebuffer_unreference(crtc->primary->fb); } @@ -573,14 +617,14 @@ static int omap_crtc_page_flip(struct drm_crtc *crtc, spin_lock_irqsave(&dev->event_lock, flags); - if (omap_crtc->flip_pending) { + if (omap_crtc->flip_state != OMAP_PAGE_FLIP_IDLE) { spin_unlock_irqrestore(&dev->event_lock, flags); dev_err(dev->dev, "already a pending flip\n"); return -EBUSY; } omap_crtc->flip_event = event; - omap_crtc->flip_pending = true; + omap_crtc->flip_state = OMAP_PAGE_FLIP_WAIT; primary->fb = fb; drm_framebuffer_reference(fb); -- cgit v1.2.3 From c397cfd496f8b129a44962e84a9206afa0d7e431 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 25 Jan 2015 22:42:30 +0200 Subject: drm: omapdrm: Turn vblank on/off when enabling/disabling CRTC The DRM core vblank handling mechanism requires drivers to forcefully turn vblank reporting off when disabling the CRTC, and to restore the vblank reporting status when enabling the CRTC. Implement this using the drm_crtc_vblank_on/off helpers. When disabling vblank we must first wait for page flips to complete, so implement page flip completion wait as well. Finally, drm_crtc_vblank_off() must be called at startup to synchronize the state of the vblank core code with the hardware, which is initially disabled. An interesting side effect is that the .disable_vblank() operation will now be called for the first time with the CRTC disabled and the DISPC runtime suspended. The dispc_runtime_get() call in .disable_vblank() is supposed to take care of that, but the operation is called with a spinlock held, which prevents it from sleeping. To fix that move DISPC runtime PM handling out of the vblank operations to the CRTC code, ensuring that the display controller will always be powered when enabling or disabling vblank interrupts. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_crtc.c | 78 +++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/omapdrm/omap_drv.c | 5 +++ drivers/gpu/drm/omapdrm/omap_irq.c | 4 -- 3 files changed, 79 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index c086f72e488d..1076bc0a7f78 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -76,6 +76,7 @@ struct omap_crtc { */ enum omap_page_flip_state flip_state; struct drm_pending_vblank_event *flip_event; + wait_queue_head_t flip_wait; struct work_struct flip_work; struct completion completion; @@ -309,6 +310,61 @@ static void omap_crtc_complete_page_flip(struct drm_crtc *crtc, } omap_crtc->flip_state = state; + + if (state == OMAP_PAGE_FLIP_IDLE) + wake_up(&omap_crtc->flip_wait); +} + +static bool omap_crtc_page_flip_pending(struct drm_crtc *crtc) +{ + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct drm_device *dev = crtc->dev; + unsigned long flags; + bool pending; + + spin_lock_irqsave(&dev->event_lock, flags); + pending = omap_crtc->flip_state != OMAP_PAGE_FLIP_IDLE; + spin_unlock_irqrestore(&dev->event_lock, flags); + + return pending; +} + +static void omap_crtc_wait_page_flip(struct drm_crtc *crtc) +{ + struct omap_crtc *omap_crtc = to_omap_crtc(crtc); + struct drm_device *dev = crtc->dev; + bool cancelled = false; + unsigned long flags; + + /* + * If we're still waiting for the GEM async operation to complete just + * cancel the page flip, as we're holding the CRTC mutex preventing the + * page flip work handler from queueing the page flip. + * + * We can't release the reference to the frame buffer here as the async + * operation doesn't keep its own reference to the buffer. We'll just + * let the page flip work queue handle that. + */ + spin_lock_irqsave(&dev->event_lock, flags); + if (omap_crtc->flip_state == OMAP_PAGE_FLIP_WAIT) { + omap_crtc_complete_page_flip(crtc, OMAP_PAGE_FLIP_CANCELLED); + cancelled = true; + } + spin_unlock_irqrestore(&dev->event_lock, flags); + + if (cancelled) + return; + + if (wait_event_timeout(omap_crtc->flip_wait, + !omap_crtc_page_flip_pending(crtc), + msecs_to_jiffies(50))) + return; + + dev_warn(crtc->dev->dev, "page flip timeout!\n"); + + spin_lock_irqsave(&dev->event_lock, flags); + omap_crtc_complete_page_flip(crtc, OMAP_PAGE_FLIP_IDLE); + spin_unlock_irqrestore(&dev->event_lock, flags); } static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) @@ -455,26 +511,39 @@ static void omap_crtc_dpms(struct drm_crtc *crtc, int mode) { struct omap_drm_private *priv = crtc->dev->dev_private; struct omap_crtc *omap_crtc = to_omap_crtc(crtc); - bool enabled = (mode == DRM_MODE_DPMS_ON); + bool enable = (mode == DRM_MODE_DPMS_ON); int i; DBG("%s: %d", omap_crtc->name, mode); - if (enabled == omap_crtc->enabled) + if (enable == omap_crtc->enabled) return; + if (!enable) { + omap_crtc_wait_page_flip(crtc); + dispc_runtime_get(); + drm_crtc_vblank_off(crtc); + dispc_runtime_put(); + } + /* Enable/disable all planes associated with the CRTC. */ for (i = 0; i < priv->num_planes; i++) { struct drm_plane *plane = priv->planes[i]; if (plane->crtc == crtc) - WARN_ON(omap_plane_set_enable(plane, enabled)); + WARN_ON(omap_plane_set_enable(plane, enable)); } - omap_crtc->enabled = enabled; + omap_crtc->enabled = enable; omap_crtc_setup(crtc); omap_crtc_flush(crtc); + + if (enable) { + dispc_runtime_get(); + drm_crtc_vblank_on(crtc); + dispc_runtime_put(); + } } static bool omap_crtc_mode_fixup(struct drm_crtc *crtc, @@ -709,6 +778,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, crtc = &omap_crtc->base; INIT_WORK(&omap_crtc->flip_work, page_flip_worker); + init_waitqueue_head(&omap_crtc->flip_wait); INIT_LIST_HEAD(&omap_crtc->pending_unpins); diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index cf1b37e5374b..e81fbc07ea9b 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -502,6 +502,7 @@ static int dev_load(struct drm_device *dev, unsigned long flags) { struct omap_drm_platform_data *pdata = dev->dev->platform_data; struct omap_drm_private *priv; + unsigned int i; int ret; DBG("load: dev=%p", dev); @@ -529,10 +530,14 @@ static int dev_load(struct drm_device *dev, unsigned long flags) return ret; } + /* Initialize vblank handling, start with all CRTCs disabled. */ ret = drm_vblank_init(dev, priv->num_crtcs); if (ret) dev_warn(dev->dev, "could not init vblank\n"); + for (i = 0; i < priv->num_crtcs; i++) + drm_crtc_vblank_off(priv->crtcs[i]); + priv->fbdev = omap_fbdev_init(dev); if (!priv->fbdev) { dev_warn(dev->dev, "omap_fbdev_init failed\n"); diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c index 803aff0db768..249c0330d6ce 100644 --- a/drivers/gpu/drm/omapdrm/omap_irq.c +++ b/drivers/gpu/drm/omapdrm/omap_irq.c @@ -152,12 +152,10 @@ int omap_irq_enable_vblank(struct drm_device *dev, int crtc_id) DBG("dev=%p, crtc=%d", dev, crtc_id); - dispc_runtime_get(); spin_lock_irqsave(&list_lock, flags); priv->vblank_mask |= pipe2vbl(crtc); omap_irq_update(dev); spin_unlock_irqrestore(&list_lock, flags); - dispc_runtime_put(); return 0; } @@ -179,12 +177,10 @@ void omap_irq_disable_vblank(struct drm_device *dev, int crtc_id) DBG("dev=%p, crtc=%d", dev, crtc_id); - dispc_runtime_get(); spin_lock_irqsave(&list_lock, flags); priv->vblank_mask &= ~pipe2vbl(crtc); omap_irq_update(dev); spin_unlock_irqrestore(&list_lock, flags); - dispc_runtime_put(); } static irqreturn_t omap_irq_handler(int irq, void *arg) -- cgit v1.2.3 From 0c19ac9d033eed734b0e38c9147a1c893c0e4b12 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 4 Mar 2015 18:24:18 +0200 Subject: drm: omapdrm: Fix page flip race with CRTC disable We can't rely on crtc->primary->fb in the page flip worker, as a racing CRTC disable (due for instance to an explicit framebuffer deletion from userspace) would set that field to NULL before the worker gets a change to run. Store the framebuffer queued for page flip in a new field of omap_crtc instead, and hold a reference to it. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_crtc.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 1076bc0a7f78..68abc4d7fa0d 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -66,7 +66,8 @@ struct omap_crtc { * page queue has been submitted, WAIT when waiting for GEM async * completion, QUEUED when the page flip has been queued to the hardware * or CANCELLED when the CRTC is turned off before the flip gets queued - * to the hardware. The flip event, if any, is stored in flip_event. The + * to the hardware. The flip event, if any, is stored in flip_event, and + * the framebuffer queued for page flip is stored in flip_fb. The * flip_wait wait queue is used to wait for page flip completion. * * The flip_work work queue handles page flip requests without caring @@ -76,6 +77,7 @@ struct omap_crtc { */ enum omap_page_flip_state flip_state; struct drm_pending_vblank_event *flip_event; + struct drm_framebuffer *flip_fb; wait_queue_head_t flip_wait; struct work_struct flip_work; @@ -630,6 +632,7 @@ static void page_flip_worker(struct work_struct *work) drm_modeset_lock(&crtc->mutex, NULL); spin_lock_irqsave(&dev->event_lock, flags); + /* * The page flip could have been cancelled while waiting for the GEM * async operation to complete. Don't queue the flip in that case. @@ -641,9 +644,11 @@ static void page_flip_worker(struct work_struct *work) omap_crtc->flip_state = OMAP_PAGE_FLIP_IDLE; queue_flip = false; } - spin_unlock_irqrestore(&dev->event_lock, flags); - fb = crtc->primary->fb; + fb = omap_crtc->flip_fb; + omap_crtc->flip_fb = NULL; + + spin_unlock_irqrestore(&dev->event_lock, flags); if (queue_flip) { omap_plane_mode_set(crtc->primary, crtc, fb, @@ -657,7 +662,7 @@ static void page_flip_worker(struct work_struct *work) bo = omap_framebuffer_bo(fb, 0); drm_gem_object_unreference_unlocked(bo); - drm_framebuffer_unreference(crtc->primary->fb); + drm_framebuffer_unreference(fb); } static void page_flip_cb(void *arg) @@ -692,10 +697,19 @@ static int omap_crtc_page_flip(struct drm_crtc *crtc, return -EBUSY; } + /* + * Store a reference to the framebuffer queued for page flip in the CRTC + * private structure. We can't rely on crtc->primary->fb in the page + * flip worker, as a racing CRTC disable (due for instance to an + * explicit framebuffer deletion from userspace) would set that field to + * NULL before the worker gets a change to run. + */ + drm_framebuffer_reference(fb); + omap_crtc->flip_fb = fb; omap_crtc->flip_event = event; omap_crtc->flip_state = OMAP_PAGE_FLIP_WAIT; + primary->fb = fb; - drm_framebuffer_reference(fb); spin_unlock_irqrestore(&dev->event_lock, flags); -- cgit v1.2.3 From 2d278f5414ae9cd535a7bdefaba2e2de38e116c7 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 5 Mar 2015 21:31:37 +0200 Subject: drm: omapdrm: Clean up #include's Use the <...> include style instead of "..." for DRM headers and sort the headers alphabetically to ease detection of duplicates. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/omap_connector.c | 6 +++--- drivers/gpu/drm/omapdrm/omap_crtc.c | 8 ++++---- drivers/gpu/drm/omapdrm/omap_debugfs.c | 6 +++--- drivers/gpu/drm/omapdrm/omap_dmm_tiler.c | 19 ++++++++++--------- drivers/gpu/drm/omapdrm/omap_drv.c | 6 +++--- drivers/gpu/drm/omapdrm/omap_drv.h | 8 ++++---- drivers/gpu/drm/omapdrm/omap_encoder.c | 10 ++++------ drivers/gpu/drm/omapdrm/omap_fb.c | 8 ++++---- drivers/gpu/drm/omapdrm/omap_fbdev.c | 6 +++--- drivers/gpu/drm/omapdrm/omap_gem.c | 4 ++-- drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c | 4 ++-- drivers/gpu/drm/omapdrm/omap_plane.c | 2 +- 12 files changed, 43 insertions(+), 44 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/omapdrm/omap_connector.c b/drivers/gpu/drm/omapdrm/omap_connector.c index 17739737dcf6..cd1b10d660ac 100644 --- a/drivers/gpu/drm/omapdrm/omap_connector.c +++ b/drivers/gpu/drm/omapdrm/omap_connector.c @@ -17,10 +17,10 @@ * this program. If not, see . */ -#include "omap_drv.h" +#include +#include -#include "drm_crtc.h" -#include "drm_crtc_helper.h" +#include "omap_drv.h" /* * connector funcs diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 68abc4d7fa0d..6840ed5c45a7 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -19,12 +19,12 @@ #include -#include "omap_drv.h" - +#include +#include #include #include -#include "drm_crtc.h" -#include "drm_crtc_helper.h" + +#include "omap_drv.h" #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) diff --git a/drivers/gpu/drm/omapdrm/omap_debugfs.c b/drivers/gpu/drm/omapdrm/omap_debugfs.c index d4c04d69fc4d..ee91a25127f9 100644 --- a/drivers/gpu/drm/omapdrm/omap_debugfs.c +++ b/drivers/gpu/drm/omapdrm/omap_debugfs.c @@ -17,12 +17,12 @@ * this program. If not, see . */ +#include +#include + #include "omap_drv.h" #include "omap_dmm_tiler.h" -#include "drm_fb_helper.h" - - #ifdef CONFIG_DEBUG_FS static int gem_show(struct seq_file *m, void *arg) diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c index 042038e8a662..f2daad8c3d96 100644 --- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c +++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c @@ -15,21 +15,22 @@ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include +#include +#include +#include #include +#include +#include +#include #include #include /* platform_device() */ -#include #include -#include -#include -#include #include -#include -#include -#include #include -#include -#include +#include +#include #include "omap_dmm_tiler.h" #include "omap_dmm_priv.h" diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index e81fbc07ea9b..dbd304691281 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -17,11 +17,11 @@ * this program. If not, see . */ -#include "omap_drv.h" +#include +#include -#include "drm_crtc_helper.h" -#include "drm_fb_helper.h" #include "omap_dmm_tiler.h" +#include "omap_drv.h" #define DRIVER_NAME MODULE_NAME #define DRIVER_DESC "OMAP DRM" diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index 774b9f6ab2d6..6448fa809215 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h @@ -20,15 +20,15 @@ #ifndef __OMAP_DRV_H__ #define __OMAP_DRV_H__ -#include